Add some style(9) touch ups; style(9) states that new code should follow
these conventions and, well, this is a new driver. Tested on: i386, sparc64 Reviewed by: scottl
This commit is contained in:
trhodes
parent
47f728c0bc
commit
4cf054f847
@ -108,7 +108,7 @@ struct esp_softc {
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struct resource *sc_irqres;
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void *sc_irq;
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struct lsi64854_softc *sc_dma; /* pointer to my dma */
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struct lsi64854_softc *sc_dma; /* pointer to my DMA */
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int sc_pri; /* SBUS priority */
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};
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@ -202,7 +202,7 @@ esp_sbus_attach(device_t dev)
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/*
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* allocate space for dma, in SUNW,fas there are no separate
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* dma device
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* dma devices
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*/
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lsc = malloc(sizeof (struct lsi64854_softc), M_DEVBUF, M_NOWAIT);
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@ -568,7 +568,7 @@ void
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esp_dma_stop(struct ncr53c9x_softc *sc)
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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u_int32_t csr;
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uint32_t csr;
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csr = L64854_GCSR(esc->sc_dma);
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csr &= ~D_EN_DMA;
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@ -116,7 +116,7 @@ int lsi64854debug = 0;
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void
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lsi64854_attach(struct lsi64854_softc *sc)
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{
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u_int32_t csr;
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uint32_t csr;
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sc->dv_name = device_get_nameunit(sc->sc_dev);
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@ -205,7 +205,7 @@ lsi64854_attach(struct lsi64854_softc *sc)
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} while (0)
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#define DMA_DRAIN(sc, dontpanic) do { \
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u_int32_t csr; \
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uint32_t csr; \
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/* \
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* DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \
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* and "drain" bits while it is still thinking about a \
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@ -228,13 +228,13 @@ lsi64854_attach(struct lsi64854_softc *sc)
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} \
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/* \
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* Wait for draining to finish \
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* rev0 & rev1 call this PACKCNT \
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* rev0 & rev1 call this PACKCNT \
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*/ \
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DMAWAIT(sc, L64854_GCSR(sc) & L64854_DRAINING, "DRAINING", dontpanic);\
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} while(0)
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#define DMA_FLUSH(sc, dontpanic) do { \
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u_int32_t csr; \
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uint32_t csr; \
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/* \
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* DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \
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* and "drain" bits while it is still thinking about a \
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@ -251,7 +251,7 @@ lsi64854_attach(struct lsi64854_softc *sc)
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void
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lsi64854_reset(struct lsi64854_softc *sc)
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{
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u_int32_t csr;
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uint32_t csr;
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DMA_FLUSH(sc, 1);
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csr = L64854_GCSR(sc);
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@ -346,7 +346,7 @@ int
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lsi64854_setup(struct lsi64854_softc *sc, caddr_t *addr, size_t *len,
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int datain, size_t *dmasize)
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{
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u_int32_t csr;
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uint32_t csr;
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DMA_FLUSH(sc, 0);
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@ -358,7 +358,7 @@ lsi64854_setup(struct lsi64854_softc *sc, caddr_t *addr, size_t *len,
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sc->sc_datain = datain;
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/*
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* the rules say we cannot transfer more than the limit
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* The rules say we cannot transfer more than the limit
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* of this DMA chip (64k for old and 16Mb for new),
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* and we cannot cross a 16Mb boundary.
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*/
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@ -427,7 +427,7 @@ lsi64854_scsi_intr(void *arg)
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struct lsi64854_softc *sc = arg;
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struct ncr53c9x_softc *nsc = sc->sc_client;
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int trans, resid;
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u_int32_t csr;
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uint32_t csr;
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csr = L64854_GCSR(sc);
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@ -550,7 +550,7 @@ int
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lsi64854_enet_intr(void *arg)
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{
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struct lsi64854_softc *sc = arg;
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u_int32_t csr;
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uint32_t csr;
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static int dodrain = 0;
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int rv;
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@ -608,7 +608,7 @@ int
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lsi64854_setup_pp(struct lsi64854_softc *sc, caddr_t *addr, size_t *len,
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int datain, size_t *dmasize)
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{
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u_int32_t csr;
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uint32_t csr;
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DMA_FLUSH(sc, 0);
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@ -668,7 +668,7 @@ lsi64854_pp_intr(void *arg)
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{
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struct lsi64854_softc *sc = arg;
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int ret, trans, resid = 0;
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u_int32_t csr;
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uint32_t csr;
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csr = L64854_GCSR(sc);
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@ -93,7 +93,7 @@ struct lsi64854_softc {
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#define DMA_ISACTIVE(sc) ((sc)->sc_active)
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#define DMA_ENINTR(sc) do { \
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u_int32_t csr = L64854_GCSR(sc); \
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uint32_t csr = L64854_GCSR(sc); \
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csr |= L64854_INT_EN; \
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L64854_SCSR(sc, csr); \
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} while (0)
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@ -101,7 +101,7 @@ struct lsi64854_softc {
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#define DMA_ISINTR(sc) (L64854_GCSR(sc) & (D_INT_PEND|D_ERR_PEND))
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#define DMA_GO(sc) do { \
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u_int32_t csr = L64854_GCSR(sc); \
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uint32_t csr = L64854_GCSR(sc); \
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csr |= D_EN_DMA; \
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L64854_SCSR(sc, csr); \
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sc->sc_active = 1; \
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@ -99,7 +99,7 @@
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* Based on aic6360 by Jarle Greipsland
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*
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* Acknowledgements: Many of the algorithms used in this driver are
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* inspired by the work of Julian Elischer (julian@tfs.com) and
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* inspired by the work of Julian Elischer (julian@FreeBSD.org) and
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* Charles Hannum (mycroft@duality.gnu.ai.mit.edu). Thanks a million!
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*/
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@ -216,7 +216,7 @@ ncr53c9x_lunsearch(struct ncr53c9x_tinfo *ti, int64_t lun)
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}
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/*
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* Attach this instance, and then all the sub-devices
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* Attach this instance, and then all the sub-devices.
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*/
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int
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ncr53c9x_attach(struct ncr53c9x_softc *sc)
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@ -770,7 +770,7 @@ ncr53c9x_select(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb)
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}
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/*
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* Who am I. This is where we tell the target that we are
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* Who am I? This is where we tell the target that we are
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* happy for it to disconnect etc.
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*/
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@ -817,7 +817,7 @@ ncr53c9x_get_ecb(struct ncr53c9x_softc *sc)
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}
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/*
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* DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS
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* DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS:
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*/
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/*
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@ -1043,7 +1043,7 @@ ncr53c9x_action(struct cam_sim *sim, union ccb *ccb)
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}
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/*
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* Used when interrupt driven I/O isn't allowed, e.g. during boot.
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* Used when interrupt driven I/O is not allowed, e.g. during boot.
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*/
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static void
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ncr53c9x_poll(struct cam_sim *sim)
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@ -1630,7 +1630,7 @@ ncr53c9x_msgin(struct ncr53c9x_softc *sc)
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gotit:
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NCR_MSGS(("gotmsg(%x) state %d", sc->sc_imess[0], sc->sc_state));
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/* we got complete message, flush the imess, */
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/* We got a complete message, flush the imess, */
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/* XXX nobody uses imlen below */
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sc->sc_imlen = 0;
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/*
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@ -1916,8 +1916,8 @@ ncr53c9x_msgout(struct ncr53c9x_softc *sc)
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* XXX - the NCR_ATN flag is not in sync with the actual ATN
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* condition on the SCSI bus. The 53c9x chip
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* automatically turns off ATN before sending the
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* message byte. (see also the comment below in the
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* default case when picking out a message to send)
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* message byte. (See also the comment below in the
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* default case when picking out a message to send.)
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*/
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if (sc->sc_flags & NCR_ATN) {
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if (sc->sc_prevphase != MESSAGE_OUT_PHASE) {
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@ -2420,7 +2420,7 @@ again:
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}
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/*
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* The C90 only inhibits FIFO writes until reselection
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* is complete, instead of waiting until the interrupt
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* is complete instead of waiting until the interrupt
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* status register has been read. So, if the reselect
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* happens while we were entering command bytes (for
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* another target) some of those bytes can appear in
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@ -2949,4 +2949,3 @@ ncr53c9x_watch(void *arg)
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mtx_unlock(&sc->sc_lock);
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callout_reset(&sc->sc_watchdog, 60 * hz, ncr53c9x_watch, sc);
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}
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@ -42,7 +42,7 @@
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#define NCR_FIFO 0x02 /* RW - FIFO data */
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#define NCR_CMD 0x03 /* RW - Command (2 deep) */
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#define NCR_CMD 0x03 /* RW - Command (2 deep) */
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#define NCRCMD_DMA 0x80 /* DMA Bit */
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#define NCRCMD_NOP 0x00 /* No Operation */
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#define NCRCMD_FLUSH 0x01 /* Flush FIFO */
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@ -75,7 +75,7 @@
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#define NCRCMD_SETATN 0x1a /* Set ATN */
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#define NCRCMD_RSTATN 0x1b /* Reset ATN */
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#define NCR_STAT 0x04 /* RO - Status */
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#define NCR_STAT 0x04 /* RO - Status */
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#define NCRSTAT_INT 0x80 /* Interrupt */
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#define NCRSTAT_GE 0x40 /* Gross Error */
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#define NCRSTAT_PE 0x20 /* Parity Error */
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@ -83,11 +83,11 @@
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#define NCRSTAT_VGC 0x08 /* Valid Group Code */
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#define NCRSTAT_PHASE 0x07 /* Phase bits */
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#define NCR_SELID 0x04 /* WO - Select/Reselect Bus ID */
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#define NCR_SELID 0x04 /* WO - Select/Reselect Bus ID */
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#define NCR_BUSID_HME 0x10 /* XXX HME reselect ID */
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#define NCR_BUSID_HME32 0x40 /* XXX HME to select more than 16 */
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#define NCR_INTR 0x05 /* RO - Interrupt */
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#define NCR_INTR 0x05 /* RO - Interrupt */
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#define NCRINTR_SBR 0x80 /* SCSI Bus Reset */
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#define NCRINTR_ILL 0x40 /* Illegal Command */
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#define NCRINTR_DIS 0x20 /* Disconnect */
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@ -97,16 +97,16 @@
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#define NCRINTR_SELATN 0x02 /* Select with ATN */
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#define NCRINTR_SEL 0x01 /* Selected */
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#define NCR_TIMEOUT 0x05 /* WO - Select/Reselect Timeout */
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#define NCR_TIMEOUT 0x05 /* WO - Select/Reselect Timeout */
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#define NCR_STEP 0x06 /* RO - Sequence Step */
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#define NCR_STEP 0x06 /* RO - Sequence Step */
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#define NCRSTEP_MASK 0x07 /* the last 3 bits */
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#define NCRSTEP_DONE 0x04 /* command went out */
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#define NCR_SYNCTP 0x06 /* WO - Synch Transfer Period */
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#define NCR_SYNCTP 0x06 /* WO - Synch Transfer Period */
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/* Default 5 (53C9X) */
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#define NCR_FFLAG 0x07 /* RO - FIFO Flags */
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#define NCR_FFLAG 0x07 /* RO - FIFO Flags */
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#define NCRFIFO_SS 0xe0 /* Sequence Step (Dup) */
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#define NCRFIFO_FF 0x1f /* Bytes in FIFO */
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@ -114,7 +114,7 @@
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/* 0 = ASYNC */
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/* 1 - 15 = SYNC bytes */
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#define NCR_CFG1 0x08 /* RW - Configuration #1 */
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#define NCR_CFG1 0x08 /* RW - Configuration #1 */
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#define NCRCFG1_SLOW 0x80 /* Slow Cable Mode */
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#define NCRCFG1_SRR 0x40 /* SCSI Reset Rep Int Dis */
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#define NCRCFG1_PTEST 0x20 /* Parity Test Mod */
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@ -122,7 +122,7 @@
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#define NCRCFG1_CTEST 0x08 /* Enable Chip Test */
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#define NCRCFG1_BUSID 0x07 /* Bus ID */
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#define NCR_CCF 0x09 /* WO - Clock Conversion Factor */
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#define NCR_CCF 0x09 /* WO - Clock Conversion Factor */
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/* 0 = 35.01 - 40MHz */
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/* NEVER SET TO 1 */
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/* 2 = 10MHz */
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@ -132,9 +132,9 @@
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/* 6 = 25.01 - 30MHz */
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/* 7 = 30.01 - 35MHz */
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#define NCR_TEST 0x0a /* WO - Test (Chip Test Only) */
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#define NCR_TEST 0x0a /* WO - Test (Chip Test Only) */
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#define NCR_CFG2 0x0b /* RW - Configuration #2 */
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#define NCR_CFG2 0x0b /* RW - Configuration #2 */
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#define NCRCFG2_RSVD 0xa0 /* reserved */
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#define NCRCFG2_FE 0x40 /* Features Enable */
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#define NCRCFG2_DREQ 0x10 /* DREQ High Impedance */
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@ -147,7 +147,7 @@
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#define NCRCFG2_HME32 0x80 /* HME 32 extended */
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/* Config #3 only on 53C9X */
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#define NCR_CFG3 0x0c /* RW - Configuration #3 */
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#define NCR_CFG3 0x0c /* RW - Configuration #3 */
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#define NCRCFG3_RSVD 0xe0 /* reserved */
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#define NCRCFG3_IDM 0x10 /* ID Message Res Check */
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#define NCRCFG3_QTE 0x08 /* Queue Tag Enable */
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@ -163,7 +163,7 @@
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*/
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/* Config #3 different on ESP406/FAS408 */
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#define NCR_ESPCFG3 0x0c /* RW - Configuration #3 */
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#define NCR_ESPCFG3 0x0c /* RW - Configuration #3 */
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#define NCRESPCFG3_IDM 0x80 /* ID Message Res Check */
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#define NCRESPCFG3_QTE 0x40 /* Queue Tag Enable */
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#define NCRESPCFG3_CDB 0x20 /* CDB 10-bytes OK */
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@ -174,7 +174,7 @@
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#define NCRESPCFG3_T8M 0x01 /* Threshold 8 Mode */
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/* Config #3 also different on NCR53CF9x/FAS216 */
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#define NCR_F9XCFG3 0x0c /* RW - Configuration #3 */
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#define NCR_F9XCFG3 0x0c /* RW - Configuration #3 */
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#define NCRF9XCFG3_IDM 0x80 /* ID Message Res Check */
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#define NCRF9XCFG3_QTE 0x40 /* Queue Tag Enable */
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#define NCRF9XCFG3_CDB 0x20 /* CDB 10-bytes OK */
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@ -195,7 +195,7 @@
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#define NCRFASCFG3_FASTCLK 0x01 /* fast clock mode */
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/* Config #4 only on ESP406/FAS408 */
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#define NCR_CFG4 0x0d /* RW - Configuration #4 */
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#define NCR_CFG4 0x0d /* RW - Configuration #4 */
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#define NCRCFG4_CRS1 0x80 /* Select register set #1 */
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#define NCRCFG4_RSVD 0x7b /* reserved */
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#define NCRCFG4_ACTNEG 0x04 /* Active negation */
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@ -207,7 +207,7 @@
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register 0x0d is set. This bit is common to both register sets.
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*/
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#define NCR_JMP 0x00 /* RO - Jumper Sense Register */
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#define NCR_JMP 0x00 /* RO - Jumper Sense Register */
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#define NCRJMP_RSVD 0xc0 /* reserved */
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#define NCRJMP_ROMSZ 0x20 /* ROM Size 1=16K, 0=32K */
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#define NCRJMP_J4 0x10 /* Jumper #4 */
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@ -216,9 +216,9 @@
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#define NCRJMP_J1 0x02 /* Jumper #1 */
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#define NCRJMP_J0 0x01 /* Jumper #0 */
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#define NCR_PIOFIFO 0x04 /* WO - PIO FIFO, 4 bytes deep */
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#define NCR_PIOFIFO 0x04 /* WO - PIO FIFO, 4 bytes deep */
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#define NCR_PSTAT 0x08 /* RW - PIO Status Register */
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#define NCR_PSTAT 0x08 /* RW - PIO Status Register */
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#define NCRPSTAT_PERR 0x80 /* PIO Error */
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#define NCRPSTAT_SIRQ 0x40 /* Active High of SCSI IRQ */
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#define NCRPSTAT_ATAI 0x20 /* ATA IRQ */
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@ -228,7 +228,7 @@
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#define NCRPSTAT_FFULL 0x02 /* PIO FIFO Full */
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#define NCRPSTAT_PIOM 0x01 /* PIO/DMA Mode */
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#define NCR_PIOI 0x0b /* RW - PIO Interrupt Enable */
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#define NCR_PIOI 0x0b /* RW - PIO Interrupt Enable */
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#define NCRPIOI_RSVD 0xe0 /* reserved */
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#define NCRPIOI_EMPTY 0x10 /* IRQ When Empty */
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#define NCRPIOI_13 0x08 /* IRQ When 1/3 */
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@ -236,7 +236,7 @@
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#define NCRPIOI_FULL 0x02 /* IRQ When Full */
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#define NCRPIOI_FINV 0x01 /* Flag Invert */
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#define NCR_CFG5 0x0d /* RW - Configuration #5 */
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#define NCR_CFG5 0x0d /* RW - Configuration #5 */
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#define NCRCFG5_CRS1 0x80 /* Select Register Set #1 */
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#define NCRCFG5_SRAM 0x40 /* SRAM Memory Map */
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#define NCRCFG5_AADDR 0x20 /* Auto Address */
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@ -246,10 +246,10 @@
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#define NCRCFG5_INTP 0x02 /* INT Polarity */
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#define NCRCFG5_AINT 0x01 /* ATA Interupt Enable */
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#define NCR_SIGNTR 0x0e /* RO - Signature */
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#define NCR_SIGNTR 0x0e /* RO - Signature */
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/* Am53c974 Config #3 */
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#define NCR_AMDCFG3 0x0c /* RW - Configuration #3 */
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#define NCR_AMDCFG3 0x0c /* RW - Configuration #3 */
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#define NCRAMDCFG3_IDM 0x80 /* ID Message Res Check */
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#define NCRAMDCFG3_QTE 0x40 /* Queue Tag Enable */
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||||
#define NCRAMDCFG3_CDB 0x20 /* CDB 10-bytes OK */
|
||||
@ -258,7 +258,7 @@
|
||||
#define NCRAMDCFG3_RSVD 0x07 /* Reserved */
|
||||
|
||||
/* Am53c974 Config #4 */
|
||||
#define NCR_AMDCFG4 0x0d /* RW - Configuration #4 */
|
||||
#define NCR_AMDCFG4 0x0d /* RW - Configuration #4 */
|
||||
#define NCRAMDCFG4_GE 0xc0 /* Glitch Eater */
|
||||
#define NCRAMDCFG4_GE12NS 0x00 /* Signal window 12ns */
|
||||
#define NCRAMDCFG4_GE25NS 0x80 /* Signal window 25ns */
|
||||
@ -272,19 +272,19 @@
|
||||
/*
|
||||
* FAS366
|
||||
*/
|
||||
#define NCR_RCL NCR_TCH /* Recommand counter low */
|
||||
#define NCR_RCH 0xf /* Recommand counter high */
|
||||
#define NCR_UID NCR_RCL /* fas366 part-uniq id */
|
||||
#define NCR_RCL NCR_TCH /* Recommand counter low */
|
||||
#define NCR_RCH 0xf /* Recommand counter high */
|
||||
#define NCR_UID NCR_RCL /* fas366 part-uniq id */
|
||||
|
||||
|
||||
/* status register #2 definitions (read only) */
|
||||
#define NCR_STAT2 NCR_CCF
|
||||
#define NCRFAS_STAT2_SEQCNT 0x01 /* Sequence counter bit 7-3 enabled */
|
||||
#define NCRFAS_STAT2_FLATCHED 0x02 /* FIFO flags register latched */
|
||||
#define NCRFAS_STAT2_CLATCHED 0x04 /* Xfer cntr & recommand ctr latched */
|
||||
#define NCRFAS_STAT2_CACTIVE 0x08 /* Command register is active */
|
||||
#define NCRFAS_STAT2_SCSI16 0x10 /* SCSI interface is wide */
|
||||
#define NCRFAS_STAT2_ISHUTTLE 0x20 /* FIFO Top register contains 1 byte */
|
||||
#define NCRFAS_STAT2_OSHUTTLE 0x40 /* next byte from FIFO is MSB */
|
||||
#define NCRFAS_STAT2_EMPTY 0x80 /* FIFO is empty */
|
||||
#define NCR_STAT2 NCR_CCF
|
||||
#define NCRFAS_STAT2_SEQCNT 0x01 /* Sequence counter bit 7-3 enabled */
|
||||
#define NCRFAS_STAT2_FLATCHED 0x02 /* FIFO flags register latched */
|
||||
#define NCRFAS_STAT2_CLATCHED 0x04 /* Xfer cntr & recommand ctr latched */
|
||||
#define NCRFAS_STAT2_CACTIVE 0x08 /* Command register is active */
|
||||
#define NCRFAS_STAT2_SCSI16 0x10 /* SCSI interface is wide */
|
||||
#define NCRFAS_STAT2_ISHUTTLE 0x20 /* FIFO Top register contains 1 byte */
|
||||
#define NCRFAS_STAT2_OSHUTTLE 0x40 /* next byte from FIFO is MSB */
|
||||
#define NCRFAS_STAT2_EMPTY 0x80 /* FIFO is empty */
|
||||
|
||||
|
||||
@ -85,8 +85,8 @@
|
||||
#define FREQTOCCF(freq) (((freq + 4) / 5))
|
||||
|
||||
/*
|
||||
* NCR 53c9x variants. Note, these values are used as indexes into
|
||||
* a table; don't modify them unless you know what you're doing.
|
||||
* NCR 53c9x variants. Note these values are used as indexes into
|
||||
* a table; do not modify them unless you know what you are doing.
|
||||
*/
|
||||
#define NCR_VARIANT_ESP100 0
|
||||
#define NCR_VARIANT_ESP100A 1
|
||||
@ -171,9 +171,9 @@ struct ncr53c9x_linfo {
|
||||
int64_t lun;
|
||||
LIST_ENTRY(ncr53c9x_linfo) link;
|
||||
time_t last_used;
|
||||
unsigned char used; /* # slots in use */
|
||||
unsigned char avail; /* where to start scanning */
|
||||
unsigned char busy;
|
||||
u_char used; /* # slots in use */
|
||||
u_char avail; /* where to start scanning */
|
||||
u_char busy;
|
||||
struct ncr53c9x_ecb *untagged;
|
||||
struct ncr53c9x_ecb *queued[NCR_TAG_DEPTH];
|
||||
};
|
||||
@ -361,7 +361,7 @@ struct ncr53c9x_softc {
|
||||
};
|
||||
|
||||
/* values for sc_state */
|
||||
#define NCR_IDLE 1 /* waiting for something to do */
|
||||
#define NCR_IDLE 1 /* Waiting for something to do */
|
||||
#define NCR_SELECTING 2 /* SCSI command is arbiting */
|
||||
#define NCR_RESELECTED 3 /* Has been reselected */
|
||||
#define NCR_IDENTIFIED 4 /* Has gotten IFY but not TAG */
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user