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arm64: rockchip: rk3399_pll: Fix copy paste

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RK3399 PLLs don't have mode_reg, use the correct register.

MFC after:	1 week
This commit is contained in:
manu 2019-02-26 17:20:03 +00:00
parent 2aca625774
commit 4d0588ce6e
1 changed files with 1 additions and 1 deletions
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2
sys/arm64/rockchip/clk/rk_clk_pll.c
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@ -427,7 +427,7 @@ rk3399_clk_pll_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout,
/* Setting to slow mode during frequency change */
reg = RK3399_CLK_PLL_MODE_SLOW << RK3399_CLK_PLL_MODE_SHIFT;
reg |= RK3399_CLK_PLL_MODE_MASK << RK_CLK_PLL_MASK_SHIFT;
WRITE4(clk, sc->mode_reg, reg);
WRITE4(clk, sc->base_offset + 0xC, reg);
/* Setting fbdiv */
READ4(clk, sc->base_offset, &reg);