Support for EEPROM and CPLD on XLP EVP boards.
On XLP evaluation platform, the board information is stored in an I2C eeprom and the network block configuration is available from a CPLD connected to the GBU (NOR flash bus). Add support for both of these.
This commit is contained in:
jchandra
parent
b1c8867097
commit
4d0abc074b
@ -36,44 +36,104 @@ __FBSDID("$FreeBSD$");
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <net/ethernet.h>
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#include <mips/nlm/hal/mips-extns.h>
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#include <mips/nlm/hal/haldefs.h>
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#include <mips/nlm/hal/iomap.h>
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#include <mips/nlm/hal/fmn.h>
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#include <mips/nlm/hal/pic.h>
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#include <mips/nlm/hal/sys.h>
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#include <mips/nlm/hal/uart.h>
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#include <mips/nlm/xlp.h>
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#include <mips/nlm/board.h>
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static uint8_t board_eeprom_buf[EEPROM_SIZE];
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static int board_eeprom_set;
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struct xlp_board_info xlp_board_info;
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int nlm_setup_xlp_board(void);
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static void
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nlm_print_processor_info(void)
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{
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uint32_t procid;
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int prid, rev;
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char *chip, *revstr;
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procid = mips_rd_prid();
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prid = (procid >> 8) & 0xff;
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rev = procid & 0xff;
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switch (prid) {
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case CHIP_PROCESSOR_ID_XLP_8XX:
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chip = "XLP 832";
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break;
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case CHIP_PROCESSOR_ID_XLP_3XX:
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chip = "XLP 3xx";
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break;
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case CHIP_PROCESSOR_ID_XLP_432:
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case CHIP_PROCESSOR_ID_XLP_416:
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chip = "XLP 4xx";
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break;
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default:
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chip = "XLP ?xx";
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break;
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}
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switch (rev) {
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case 0:
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revstr = "A0"; break;
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case 1:
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revstr = "A1"; break;
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case 2:
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revstr = "A2"; break;
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case 3:
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revstr = "B0"; break;
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default:
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revstr = "??"; break;
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}
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printf("Processor info:\n");
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printf(" Netlogic %s %s [%x]\n", chip, revstr, procid);
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}
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/*
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* All our knowledge of chip and board that cannot be detected by probing
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* at run-time goes here
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*/
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int
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static int
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nlm_setup_xlp_board(void)
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{
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struct xlp_board_info *boardp;
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int node;
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int rv;
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uint8_t *b;
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/* start with a clean slate */
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boardp = &xlp_board_info;
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memset(boardp, 0, sizeof(xlp_board_info));
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memset(boardp, 0, sizeof(*boardp));
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boardp->nodemask = 0x1; /* only node 0 */
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nlm_print_processor_info();
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for (node = 0; node < XLP_MAX_NODES; node++) {
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if ((boardp->nodemask & (1 << node)) == 0)
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continue;
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}
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return 0;
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b = board_eeprom_buf;
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rv = nlm_board_eeprom_read(0, EEPROM_I2CBUS, EEPROM_I2CADDR, 0, b,
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EEPROM_SIZE);
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if (rv == 0) {
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board_eeprom_set = 1;
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printf("Board info (EEPROM on i2c@%d at %#X):\n",
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EEPROM_I2CBUS, EEPROM_I2CADDR);
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printf(" Model: %7.7s %2.2s\n", &b[16], &b[24]);
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printf(" Serial #: %3.3s-%2.2s\n", &b[27], &b[31]);
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printf(" MAC addr: %02x:%02x:%02x:%02x:%02x:%02x\n",
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b[2], b[3], b[4], b[5], b[6], b[7]);
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} else
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printf("Board Info: Error on EEPROM read (i2c@%d %#X).\n",
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EEPROM_I2CBUS, EEPROM_I2CADDR);
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return (0);
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}
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int nlm_board_info_setup()
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int nlm_board_info_setup(void)
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{
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nlm_setup_xlp_board();
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return 0;
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return (0);
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}
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@ -36,11 +36,15 @@
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#define XLP_NAE_NPORTS 4
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#define XLP_I2C_MAXDEVICES 8
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struct xlp_i2c_devinfo {
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u_int addr; /* keep first, for i2c ivars to work */
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int bus;
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char *device;
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};
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/*
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* EVP board EEPROM info
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*/
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#define EEPROM_I2CBUS 1
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#define EEPROM_I2CADDR 0xAE
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#define EEPROM_SIZE 48
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#define EEPROM_MACADDR_OFFSET 2
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#if !defined(LOCORE) && !defined(__ASSEMBLY__)
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struct xlp_port_ivars {
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int port;
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@ -65,12 +69,19 @@ struct xlp_nae_ivars {
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struct xlp_board_info {
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u_int nodemask;
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struct xlp_node_info {
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struct xlp_i2c_devinfo i2c_devs[XLP_I2C_MAXDEVICES];
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struct xlp_nae_ivars nae_ivars;
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} nodes[XLP_MAX_NODES];
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};
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extern struct xlp_board_info xlp_board_info;
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int nlm_board_info_setup(void);
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int nlm_board_eeprom_read(int node, int i2cbus, int addr, int offs,
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uint8_t *buf,int sz);
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uint64_t nlm_board_cpld_base(int node, int chipselect);
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int nlm_board_cpld_majorversion(uint64_t cpldbase);
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int nlm_board_cpld_minorversion(uint64_t cpldbase);
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void nlm_board_cpld_reset(uint64_t cpldbase);
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int nlm_board_cpld_dboard_type(uint64_t cpldbase, int slot);
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#endif
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#endif
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113
sys/mips/nlm/board_cpld.c
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113
sys/mips/nlm/board_cpld.c
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@ -0,0 +1,113 @@
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/*-
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* Copyright (c) 2003-2012 Broadcom Corporation
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/endian.h>
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#include <mips/nlm/hal/mips-extns.h>
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#include <mips/nlm/hal/haldefs.h>
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#include <mips/nlm/hal/iomap.h>
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#include <mips/nlm/hal/gbu.h>
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#include <mips/nlm/board.h>
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#define CPLD_REVISION 0x0
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#define CPLD_RESET 0x1
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#define CPLD_CTRL 0x2
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#define CPLD_RSVD 0x3
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#define CPLD_PWR_CTRL 0x4
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#define CPLD_MISC 0x5
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#define CPLD_CTRL_STATUS 0x6
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#define CPLD_PWR_INTR_STATUS 0x7
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#define CPLD_DATA 0x8
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static __inline
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int nlm_cpld_read(uint64_t base, int reg)
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{
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uint16_t val;
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val = *(volatile uint16_t *)(long)(base + reg * 2);
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return bswap16(val);
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}
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static __inline void
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nlm_cpld_write(uint64_t base, int reg, uint16_t data)
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{
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bswap16(data);
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*(volatile uint16_t *)(long)(base + reg * 2) = data;
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}
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int
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nlm_board_cpld_majorversion(uint64_t base)
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{
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return (nlm_cpld_read(base, CPLD_REVISION) >> 8);
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}
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int
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nlm_board_cpld_minorversion(uint64_t base)
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{
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return (nlm_cpld_read(base, CPLD_REVISION) & 0xff);
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}
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uint64_t nlm_board_cpld_base(int node, int chipselect)
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{
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uint64_t gbubase, cpld_phys;
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gbubase = nlm_get_gbu_regbase(node);
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cpld_phys = nlm_read_gbu_reg(gbubase, GBU_CS_BASEADDR(chipselect));
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return (MIPS_PHYS_TO_KSEG1(cpld_phys << 8));
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}
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void
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nlm_board_cpld_reset(uint64_t base)
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{
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nlm_cpld_write(base, CPLD_RESET, 1 << 15);
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for(;;)
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__asm __volatile("wait");
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}
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/* get daughter board type */
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int
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nlm_board_cpld_dboard_type(uint64_t base, int slot)
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{
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uint16_t val;
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int shift = 0;
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switch (slot) {
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case 0: shift = 0; break;
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case 1: shift = 4; break;
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case 2: shift = 2; break;
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case 3: shift = 6; break;
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}
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val = nlm_cpld_read(base, CPLD_CTRL_STATUS) >> shift;
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return (val & 0x3);
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}
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172
sys/mips/nlm/board_eeprom.c
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172
sys/mips/nlm/board_eeprom.c
Normal file
@ -0,0 +1,172 @@
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/*-
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* Copyright (c) 2003-2012 Broadcom Corporation
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/endian.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/limits.h>
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#include <sys/bus.h>
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#include <dev/iicbus/iicoc.h>
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#include <mips/nlm/hal/haldefs.h>
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#include <mips/nlm/hal/iomap.h>
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#include <mips/nlm/hal/mips-extns.h> /* needed by board.h */
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#include <mips/nlm/board.h>
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/*
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* We have to read the EEPROM in early boot (now only for MAC addr)
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* but later for board information. Use simple polled mode driver
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* for I2C
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*/
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#define oc_read_reg(reg) nlm_read_reg(eeprom_i2c_base, reg)
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#define oc_write_reg(reg, val) nlm_write_reg(eeprom_i2c_base, reg, val)
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static uint64_t eeprom_i2c_base;
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static int
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oc_wait_on_status(uint8_t bit)
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{
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int tries = I2C_TIMEOUT;
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uint8_t status;
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do {
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status = oc_read_reg(OC_I2C_STATUS_REG);
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} while ((status & bit) != 0 && --tries > 0);
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return (tries == 0 ? -1: 0);
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}
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static int
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oc_rd_cmd(uint8_t cmd)
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{
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uint8_t data;
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oc_write_reg(OC_I2C_CMD_REG, cmd);
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if (oc_wait_on_status(OC_STATUS_TIP) < 0)
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return (-1);
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data = oc_read_reg(OC_I2C_DATA_REG);
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return (data);
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}
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static int
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oc_wr_cmd(uint8_t data, uint8_t cmd)
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{
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oc_write_reg(OC_I2C_DATA_REG, data);
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oc_write_reg(OC_I2C_CMD_REG, cmd);
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if (oc_wait_on_status(OC_STATUS_TIP) < 0)
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return (-1);
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return (0);
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}
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int
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nlm_board_eeprom_read(int node, int bus, int addr, int offs, uint8_t *buf,
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int sz)
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{
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int rd, i;
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char *err = NULL;
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eeprom_i2c_base = nlm_pcicfg_base(XLP_IO_I2C_OFFSET(node, bus)) +
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XLP_IO_PCI_HDRSZ;
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if (oc_wait_on_status(OC_STATUS_BUSY) < 0) {
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err = "Not idle";
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goto err_exit;
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}
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/* write start */
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if (oc_wr_cmd(addr, OC_COMMAND_START)) {
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err = "I2C write start failed.";
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goto err_exit;
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}
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if (oc_read_reg(OC_I2C_STATUS_REG) & OC_STATUS_NACK) {
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err = "No ack after start";
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goto err_exit_stop;
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}
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if (oc_read_reg(OC_I2C_STATUS_REG) & OC_STATUS_AL) {
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err = "I2C Bus Arbitration Lost";
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goto err_exit_stop;
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}
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/* Write offset */
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if (oc_wr_cmd(offs, OC_COMMAND_WRITE)) {
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err = "I2C write slave offset failed.";
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goto err_exit_stop;
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}
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if (oc_read_reg(OC_I2C_STATUS_REG) & OC_STATUS_NACK) {
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err = "No ack after write";
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goto err_exit_stop;
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}
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/* read start */
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if (oc_wr_cmd(addr | 1, OC_COMMAND_START)) {
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err = "I2C read start failed.";
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goto err_exit_stop;
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}
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if (oc_read_reg(OC_I2C_STATUS_REG) & OC_STATUS_NACK) {
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err = "No ack after read start";
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goto err_exit_stop;
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}
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for (i = 0; i < sz - 1; i++) {
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if ((rd = oc_rd_cmd(OC_COMMAND_READ)) < 0) {
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err = "I2C read data byte failed.";
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goto err_exit_stop;
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}
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buf[i] = rd;
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}
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/* last byte */
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if ((rd = oc_rd_cmd(OC_COMMAND_RDNACK)) < 0) {
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err = "I2C read last data byte failed.";
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goto err_exit_stop;
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}
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buf[sz - 1] = rd;
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err_exit_stop:
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oc_write_reg(OC_I2C_CMD_REG, OC_COMMAND_STOP);
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if (oc_wait_on_status(OC_STATUS_BUSY) < 0)
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printf("%s: stop failed", __func__);
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err_exit:
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if (err) {
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printf("%s: Failed (%s)\n", __func__, err);
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return (-1);
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}
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return (0);
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}
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@ -9,6 +9,8 @@ mips/nlm/cms.c standard
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mips/nlm/bus_space_rmi.c standard
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mips/nlm/bus_space_rmi_pci.c standard
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mips/nlm/mpreset.S standard
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mips/nlm/board_eeprom.c standard
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mips/nlm/board_cpld.c standard
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mips/nlm/xlp_pci.c optional pci
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mips/nlm/intern_dev.c optional pci
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mips/nlm/uart_pci_xlp.c optional uart
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100
sys/mips/nlm/hal/gbu.h
Normal file
100
sys/mips/nlm/hal/gbu.h
Normal file
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/*-
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* Copyright (c) 2003-2012 Broadcom Corporation
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
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* are met:
|
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*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
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*/
|
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#ifndef _NLM_HAL_GBU_H__
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#define _NLM_HAL_GBU_H__
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|
||||
/* Global Bus Unit (GBU) for flash Specific registers */
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|
||||
#define GBU_CS_BASEADDR(cs) (0x0+cs)
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||||
#define GBU_CS0_BASEADDR 0x0
|
||||
#define GBU_CS1_BASEADDR 0x1
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||||
#define GBU_CS2_BASEADDR 0x2
|
||||
#define GBU_CS3_BASEADDR 0x3
|
||||
#define GBU_CS4_BASEADDR 0x4
|
||||
#define GBU_CS5_BASEADDR 0x5
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||||
#define GBU_CS6_BASEADDR 0x6
|
||||
#define GBU_CS7_BASEADDR 0x7
|
||||
#define GBU_CS_BASELIMIT(cs) (0x8+cs)
|
||||
#define GBU_CS0_BASELIMIT 0x8
|
||||
#define GBU_CS1_BASELIMIT 0x9
|
||||
#define GBU_CS2_BASELIMIT 0xa
|
||||
#define GBU_CS3_BASELIMIT 0xb
|
||||
#define GBU_CS4_BASELIMIT 0xc
|
||||
#define GBU_CS5_BASELIMIT 0xd
|
||||
#define GBU_CS6_BASELIMIT 0xe
|
||||
#define GBU_CS7_BASELIMIT 0xf
|
||||
#define GBU_CS_DEVPARAM(cs) (0x10+cs)
|
||||
#define GBU_CS0_DEVPARAM 0x10
|
||||
#define GBU_CS1_DEVPARAM 0x11
|
||||
#define GBU_CS2_DEVPARAM 0x12
|
||||
#define GBU_CS3_DEVPARAM 0x13
|
||||
#define GBU_CS4_DEVPARAM 0x14
|
||||
#define GBU_CS5_DEVPARAM 0x15
|
||||
#define GBU_CS6_DEVPARAM 0x16
|
||||
#define GBU_CS7_DEVPARAM 0x17
|
||||
#define GBU_CS_DEVTIME0(cs) (0x18+cs)
|
||||
#define GBU_CS0_DEVTIME0 0x18
|
||||
#define GBU_CS1_DEVTIME0 0x1a
|
||||
#define GBU_CS2_DEVTIME0 0x1c
|
||||
#define GBU_CS3_DEVTIME0 0x1e
|
||||
#define GBU_CS4_DEVTIME0 0x20
|
||||
#define GBU_CS5_DEVTIME0 0x22
|
||||
#define GBU_CS6_DEVTIME0 0x24
|
||||
#define GBU_CS7_DEVTIME0 0x26
|
||||
#define GBU_CS_DEVTIME1(cs) (0x19+cs)
|
||||
#define GBU_CS0_DEVTIME1 0x19
|
||||
#define GBU_CS1_DEVTIME1 0x1b
|
||||
#define GBU_CS2_DEVTIME1 0x1d
|
||||
#define GBU_CS3_DEVTIME1 0x1f
|
||||
#define GBU_CS4_DEVTIME1 0x21
|
||||
#define GBU_CS5_DEVTIME1 0x23
|
||||
#define GBU_CS6_DEVTIME1 0x25
|
||||
#define GBU_CS7_DEVTIME1 0x27
|
||||
#define GBU_SYSCTRL 0x28
|
||||
#define GBU_BYTESWAP 0x29
|
||||
#define GBU_DI_TIMEOUT_VAL 0x2d
|
||||
#define GBU_INTSTAT 0x2e
|
||||
#define GBU_INTEN 0x2f
|
||||
#define GBU_STATUS 0x30
|
||||
#define GBU_ERRLOG0 0x2a
|
||||
#define GBU_ERRLOG1 0x2b
|
||||
#define GBU_ERRLOG2 0x2c
|
||||
|
||||
#if !defined(LOCORE) && !defined(__ASSEMBLY__)
|
||||
|
||||
#define nlm_read_gbu_reg(b, r) nlm_read_reg(b, r)
|
||||
#define nlm_write_gbu_reg(b, r, v) nlm_write_reg(b, r, v)
|
||||
#define nlm_get_gbu_pcibase(node) \
|
||||
nlm_pcicfg_base(XLP_IO_NOR_OFFSET(node))
|
||||
#define nlm_get_gbu_regbase(node) \
|
||||
(nlm_get_gbu_pcibase(node) + XLP_IO_PCI_HDRSZ)
|
||||
|
||||
#endif /* !LOCORE && !__ASSEMBLY__ */
|
||||
#endif /* _NLM_HAL_GBU_H__ */
|
||||
@ -29,12 +29,17 @@
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef _NLM_MSGRING_H
|
||||
#define _NLM_MSGRING_H
|
||||
#define CMS_DEFAULT_CREDIT 50
|
||||
|
||||
extern uint32_t xlp_msg_thread_mask;
|
||||
|
||||
struct nlm_fmn_msg;
|
||||
typedef void (*msgring_handler)(int, int, int, int, struct nlm_fmn_msg *, void *);
|
||||
|
||||
int register_msgring_handler(int startb, int endb, msgring_handler action,
|
||||
void *arg);
|
||||
int xlp_handle_msg_vc(u_int vcmask, int max_msgs);
|
||||
void xlp_msgring_cpu_init(int, int, int);
|
||||
void xlp_cms_enable_intr(int , int , int , int);
|
||||
#endif /* _NLM_MSGRING_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user