In the nested TLB fault handler, for a direct-mapped address, make

sure to clear the lower 12 bits. We're adding the translation
attributes to the physical address and non-zero bits in the first
12 bits would give us something unexpected, including invalid bit
values. Those trigger nested general protection faults.
We do not have to clear the region bits, because they are ignored
anyway, so we can replace an existing dep instruction with the one
we need.

This fixes GP faults for the swapper thread, as it's the only thread
that has a direct-mapped stack. Since the bug is in the nested TLB
fault handler, the frequency of hitting the GP is in the order of
hours/days under load.

sys/ia64/ia64/exception.S

@@ -1026,7 +1026,7 @@ IVT_ENTRY(Data_Nested_TLB, 0x1400)
 }
 {	.mii
 	mov		cr.itir=r26
-(p12)	dep		r28=0,r30,61,3
+(p12)	dep		r28=0,r30,0,12
 (p13)	extr.u		r28=r30,3*PAGE_SHIFT-8, PAGE_SHIFT-3	// dir L0 index
 	;;
 }