From 4dd9b0c085255b466ae920d87b038a47a1654e53 Mon Sep 17 00:00:00 2001 From: Joseph Koshy Date: Thu, 29 Nov 2007 06:43:58 +0000 Subject: [PATCH] Revert revision 1.4. Intel CPUs with family 0x6, model 0xE and later (i.e., Intel Core(TM)) have a PMC architecture that differs somewhat from previous CPUs in family 0x6. Even though the basic programming model is similar, the documented set of legal values that may be loaded into their PMC MSRs differs from that of the previous PMCs in family 0x6 and reusing bit values valid for the older PMCs could result in undefined behaviour in the general case. --- sys/dev/hwpmc/hwpmc_x86.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sys/dev/hwpmc/hwpmc_x86.c b/sys/dev/hwpmc/hwpmc_x86.c index 9b00b637c063..cb6db23bc1b6 100644 --- a/sys/dev/hwpmc/hwpmc_x86.c +++ b/sys/dev/hwpmc/hwpmc_x86.c @@ -82,7 +82,7 @@ pmc_intel_initialize(void) case 0x7: case 0x8: case 0xA: case 0xB: cputype = PMC_CPU_INTEL_PIII; break; - case 0x9: case 0xD: case 0xE: + case 0x9: case 0xD: cputype = PMC_CPU_INTEL_PM; break; }