Export ID_AA64PFR0_EL1 to userland
Create a user view of the ID_AA64PFR0_EL1 register with values common across all CPUs. Approved by: re (kib) Sponsored by: ABT Systems Ltd Differential Revision: https://reviews.freebsd.org/D17301
This commit is contained in:
andrew
parent
9fab1c4f94
commit
4ddccdfc0e
@ -88,6 +88,7 @@ struct cpu_desc {
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};
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struct cpu_desc cpu_desc[MAXCPU];
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struct cpu_desc user_cpu_desc;
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static u_int cpu_print_regs;
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#define PRINT_ID_AA64_AFR0 0x00000001
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#define PRINT_ID_AA64_AFR1 0x00000002
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@ -163,26 +164,77 @@ const struct cpu_implementers cpu_implementers[] = {
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CPU_IMPLEMENTER_NONE,
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};
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struct mrs_safe_value {
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u_int CRm;
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u_int Op2;
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uint64_t value;
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#define MRS_TYPE_MASK 0xf
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#define MRS_INVALID 0
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#define MRS_EXACT 1
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#define MRS_EXACT_VAL(x) (MRS_EXACT | ((x) << 4))
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#define MRS_EXACT_FIELD(x) ((x) >> 4)
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#define MRS_LOWER 2
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struct mrs_field {
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bool sign;
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u_int type;
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u_int shift;
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};
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static struct mrs_safe_value safe_values[] = {
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#define MRS_FIELD(_sign, _type, _shift) \
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{ \
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.sign = (_sign), \
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.type = (_type), \
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.shift = (_shift), \
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}
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#define MRS_FIELD_END { .type = MRS_INVALID, }
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static struct mrs_field id_aa64pfr0_fields[] = {
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MRS_FIELD(false, MRS_EXACT, ID_AA64PFR0_SVE_SHIFT),
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MRS_FIELD(false, MRS_EXACT, ID_AA64PFR0_RAS_SHIFT),
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MRS_FIELD(false, MRS_EXACT, ID_AA64PFR0_GIC_SHIFT),
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MRS_FIELD(true, MRS_LOWER, ID_AA64PFR0_ADV_SIMD_SHIFT),
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MRS_FIELD(true, MRS_LOWER, ID_AA64PFR0_FP_SHIFT),
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MRS_FIELD(false, MRS_EXACT, ID_AA64PFR0_EL3_SHIFT),
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MRS_FIELD(false, MRS_EXACT, ID_AA64PFR0_EL2_SHIFT),
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MRS_FIELD(false, MRS_LOWER, ID_AA64PFR0_EL1_SHIFT),
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MRS_FIELD(false, MRS_LOWER, ID_AA64PFR0_EL0_SHIFT),
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MRS_FIELD_END,
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};
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static struct mrs_field id_aa64dfr0_fields[] = {
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MRS_FIELD(false, MRS_EXACT, ID_AA64DFR0_PMS_VER_SHIFT),
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MRS_FIELD(false, MRS_EXACT, ID_AA64DFR0_CTX_CMPS_SHIFT),
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MRS_FIELD(false, MRS_EXACT, ID_AA64DFR0_WRPS_SHIFT),
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MRS_FIELD(false, MRS_EXACT, ID_AA64DFR0_BRPS_SHIFT),
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MRS_FIELD(false, MRS_EXACT, ID_AA64DFR0_PMU_VER_SHIFT),
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MRS_FIELD(false, MRS_EXACT, ID_AA64DFR0_TRACE_VER_SHIFT),
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MRS_FIELD(false, MRS_EXACT_VAL(0x6), ID_AA64DFR0_DEBUG_VER_SHIFT),
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MRS_FIELD_END,
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};
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struct mrs_user_reg {
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u_int CRm;
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u_int Op2;
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size_t offset;
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struct mrs_field *fields;
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};
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static struct mrs_user_reg user_regs[] = {
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{ /* id_aa64pfr0_el1 */
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.CRm = 4,
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.Op2 = 0,
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.value = ID_AA64PFR0_ADV_SIMD_NONE | ID_AA64PFR0_FP_NONE |
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ID_AA64PFR0_EL1_64 | ID_AA64PFR0_EL0_64,
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.offset = __offsetof(struct cpu_desc, id_aa64pfr0),
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.fields = id_aa64pfr0_fields,
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},
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{ /* id_aa64dfr0_el1 */
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.CRm = 5,
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.Op2 = 0,
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.value = ID_AA64DFR0_DEBUG_VER_8,
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.offset = __offsetof(struct cpu_desc, id_aa64dfr0),
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.fields = id_aa64dfr0_fields,
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},
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};
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#define CPU_DESC_FIELD(desc, idx) \
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*(uint64_t *)((char *)&(desc) + user_regs[(idx)].offset)
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static int
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user_mrs_handler(vm_offset_t va, uint32_t insn, struct trapframe *frame,
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uint32_t esr)
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@ -213,9 +265,9 @@ user_mrs_handler(vm_offset_t va, uint32_t insn, struct trapframe *frame,
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Op2 = mrs_Op2(insn);
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value = 0;
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for (i = 0; i < nitems(safe_values); i++) {
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if (safe_values[i].CRm == CRm && safe_values[i].Op2 == Op2) {
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value = safe_values[i].value;
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for (i = 0; i < nitems(user_regs); i++) {
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if (user_regs[i].CRm == CRm && user_regs[i].Op2 == Op2) {
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value = CPU_DESC_FIELD(user_cpu_desc, i);
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break;
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}
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}
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@ -255,13 +307,65 @@ user_mrs_handler(vm_offset_t va, uint32_t insn, struct trapframe *frame,
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return (1);
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}
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static void
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update_user_regs(u_int cpu)
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{
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struct mrs_field *fields;
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uint64_t cur, value;
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int i, j, cur_field, new_field;
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for (i = 0; i < nitems(user_regs); i++) {
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value = CPU_DESC_FIELD(cpu_desc[cpu], i);
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if (cpu == 0)
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cur = value;
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else
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cur = CPU_DESC_FIELD(user_cpu_desc, i);
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fields = user_regs[i].fields;
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for (j = 0; fields[j].type != 0; j++) {
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switch (fields[j].type & MRS_TYPE_MASK) {
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case MRS_EXACT:
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cur &= ~(0xfu << fields[j].shift);
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cur |=
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(uint64_t)MRS_EXACT_FIELD(fields[j].type) <<
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fields[j].shift;
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break;
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case MRS_LOWER:
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new_field = (value >> fields[j].shift) & 0xf;
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cur_field = (cur >> fields[j].shift) & 0xf;
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if ((fields[j].sign &&
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(int)new_field < (int)cur_field) ||
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(!fields[j].sign &&
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(u_int)new_field < (u_int)cur_field)) {
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cur &= ~(0xfu << fields[j].shift);
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cur |= new_field << fields[j].shift;
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}
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break;
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default:
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panic("Invalid field type: %d", fields[j].type);
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}
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}
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CPU_DESC_FIELD(user_cpu_desc, i) = cur;
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}
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}
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static void
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identify_cpu_sysinit(void *dummy __unused)
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{
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int cpu;
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/* Create a user visible cpu description with safe values */
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memset(&user_cpu_desc, 0, sizeof(user_cpu_desc));
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/* Safe values for these registers */
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user_cpu_desc.id_aa64pfr0 = ID_AA64PFR0_ADV_SIMD_NONE |
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ID_AA64PFR0_FP_NONE | ID_AA64PFR0_EL1_64 | ID_AA64PFR0_EL0_64;
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user_cpu_desc.id_aa64dfr0 = ID_AA64DFR0_DEBUG_VER_8;
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CPU_FOREACH(cpu) {
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print_cpu_features(cpu);
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update_user_regs(cpu);
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}
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install_undef_handler(true, user_mrs_handler);
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