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In general pmap implementations do not set the wired attribute on

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the temporary mappings that are used to implement operations like
pmap_zero_page().  There is no reason for the MIPS pmap to deviate
from that practice.
This commit is contained in:
Alan Cox 2012-10-06 19:33:52 +00:00
parent 61e100ee3b
commit 4ed2e31f01
1 changed files with 5 additions and 7 deletions
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12
sys/mips/mips/pmap.c
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@ -239,8 +239,7 @@ pmap_lmem_map1(vm_paddr_t phys)
sysm = &sysmap_lmem[cpu];
sysm->saved_intr = intr;
va = sysm->base;
npte = TLBLO_PA_TO_PFN(phys) |
PTE_D | PTE_V | PTE_G | PTE_W | PTE_C_CACHE;
npte = TLBLO_PA_TO_PFN(phys) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G;
pte = pmap_pte(kernel_pmap, va);
*pte = npte;
sysm->valid1 = 1;
@ -262,12 +261,10 @@ pmap_lmem_map2(vm_paddr_t phys1, vm_paddr_t phys2)
sysm->saved_intr = intr;
va1 = sysm->base;
va2 = sysm->base + PAGE_SIZE;
npte = TLBLO_PA_TO_PFN(phys1) |
PTE_D | PTE_V | PTE_G | PTE_W | PTE_C_CACHE;
npte = TLBLO_PA_TO_PFN(phys1) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G;
pte = pmap_pte(kernel_pmap, va1);
*pte = npte;
npte = TLBLO_PA_TO_PFN(phys2) |
PTE_D | PTE_V | PTE_G | PTE_W | PTE_C_CACHE;
npte = TLBLO_PA_TO_PFN(phys2) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G;
pte = pmap_pte(kernel_pmap, va2);
*pte = npte;
sysm->valid1 = 1;
@ -2329,7 +2326,8 @@ pmap_kenter_temporary(vm_paddr_t pa, int i)
cpu = PCPU_GET(cpuid);
sysm = &sysmap_lmem[cpu];
/* Since this is for the debugger, no locks or any other fun */
npte = TLBLO_PA_TO_PFN(pa) | PTE_D | PTE_V | PTE_G | PTE_W | PTE_C_CACHE;
npte = TLBLO_PA_TO_PFN(pa) | PTE_C_CACHE | PTE_D | PTE_V |
PTE_G;
pte = pmap_pte(kernel_pmap, sysm->base);
*pte = npte;
sysm->valid1 = 1;