The G45 docs indicate that all G4X chips use the new framecount register.

Intel agrees with my reading of the docs, make it so for all G4X chips.

The new register also has a 32 bit width as opposed to 24 bits.  Fix
things up so that the counters roll over properly.

MFC after:	3 days
This commit is contained in:
rnoland 2009-06-20 16:45:14 +00:00
parent 36023fcd02
commit 4f053b7460
3 changed files with 8 additions and 7 deletions

View File

@ -871,10 +871,13 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
_DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
if (IS_GM45(dev))
dev->driver->get_vblank_counter = gm45_get_vblank_counter;
else
if (IS_G4X(dev)) {
dev->driver->get_vblank_counter = g45_get_vblank_counter;
dev->max_vblank_count = 0xffffffff; /* 32 bits of frame count */
} else {
dev->driver->get_vblank_counter = i915_get_vblank_counter;
dev->max_vblank_count = 0x00ffffff; /* 24 bits of frame count */
}
#ifdef I915_HAVE_GEM
i915_gem_load(dev);

View File

@ -453,7 +453,7 @@ extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
extern int i915_enable_vblank(struct drm_device *dev, int crtc);
extern void i915_disable_vblank(struct drm_device *dev, int crtc);
extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
extern u32 g45_get_vblank_counter(struct drm_device *dev, int crtc);
extern int i915_vblank_swap(struct drm_device *dev, void *data,
struct drm_file *file_priv);

View File

@ -177,7 +177,7 @@ u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
return count;
}
u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
u32 g45_get_vblank_counter(struct drm_device *dev, int pipe)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
@ -516,8 +516,6 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
/* Unmask the interrupts that we always want on. */
dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;