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Add DDR flush registers for QCA955x.

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This commit is contained in:
Adrian Chadd 2015-03-04 03:51:54 +00:00
parent 1d556f272c
commit 4f1cbb2fdc
1 changed files with 7 additions and 0 deletions
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7
sys/mips/atheros/qca955xreg.h
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@ -198,4 +198,11 @@
#define QCA955X_PLL_VAL_100 0x00000101
#define QCA955X_PLL_VAL_10 0x00001616
/* DDR block */
#define QCA955X_DDR_REG_FLUSH_GE0 (AR71XX_APB_BASE + 0x9c)
#define QCA955X_DDR_REG_FLUSH_GE1 (AR71XX_APB_BASE + 0xa0)
#define QCA955X_DDR_REG_FLUSH_USB (AR71XX_APB_BASE + 0xa4)
#define QCA955X_DDR_REG_FLUSH_PCIE (AR71XX_APB_BASE + 0xa8)
#define QCA955X_DDR_REG_FLUSH_WMAC (AR71XX_APB_BASE + 0xac)
#endif /* __QCA955XREG_H__ */