Add support for JMicron JMC251/JMC261 Gigabit/Fast ethernet
controller with Card Read Host Controller. These controllers are multi-function devices and have the same ethernet core of JMC250/JMC260. Starting from REVFM 5(chip full mask revision) controllers have the following features. o eFuse support o PCD(Packet Completion Deferring) o More advanced PHY power saving Because these controllers started to use eFuse, station address modified by driver is permanent as if it was written to EEPROM. If you have to change station address please save your controller default address to safe place before reprogramming it. There is no way to restore factory default station address. Many thanks to JMicron for continuing to support FreeBSD. HW donated by: JMicron
This commit is contained in:
Pyun YongHyeon
parent
4d9ab34335
commit
4f1ff93a3b
@ -97,9 +97,9 @@ static struct jme_dev {
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const char *jme_name;
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} jme_devs[] = {
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{ VENDORID_JMICRON, DEVICEID_JMC250,
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"JMicron Inc, JMC250 Gigabit Ethernet" },
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"JMicron Inc, JMC25x Gigabit Ethernet" },
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{ VENDORID_JMICRON, DEVICEID_JMC260,
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"JMicron Inc, JMC260 Fast Ethernet" },
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"JMicron Inc, JMC26x Fast Ethernet" },
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};
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static int jme_miibus_readreg(device_t, int, int);
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@ -110,7 +110,9 @@ static int jme_mediachange(struct ifnet *);
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static int jme_probe(device_t);
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static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
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static int jme_eeprom_macaddr(struct jme_softc *);
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static int jme_efuse_macaddr(struct jme_softc *);
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static void jme_reg_macaddr(struct jme_softc *);
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static void jme_set_macaddr(struct jme_softc *, uint8_t *);
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static void jme_map_intr_vector(struct jme_softc *);
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static int jme_attach(device_t);
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static int jme_detach(device_t);
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@ -152,6 +154,8 @@ static void jme_set_filter(struct jme_softc *);
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static void jme_stats_clear(struct jme_softc *);
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static void jme_stats_save(struct jme_softc *);
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static void jme_stats_update(struct jme_softc *);
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static void jme_phy_down(struct jme_softc *);
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static void jme_phy_up(struct jme_softc *);
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static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
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static int sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS);
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static int sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
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@ -432,6 +436,55 @@ jme_eeprom_macaddr(struct jme_softc *sc)
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return (ENOENT);
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}
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static int
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jme_efuse_macaddr(struct jme_softc *sc)
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{
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uint32_t reg;
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int i;
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reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4);
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if ((reg & (EFUSE_CTL1_AUTOLOAD_ERR | EFUSE_CTL1_AUTOLAOD_DONE)) !=
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EFUSE_CTL1_AUTOLAOD_DONE)
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return (ENOENT);
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/* Reset eFuse controller. */
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reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL2, 4);
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reg |= EFUSE_CTL2_RESET;
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pci_write_config(sc->jme_dev, JME_EFUSE_CTL2, reg, 4);
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reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL2, 4);
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reg &= ~EFUSE_CTL2_RESET;
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pci_write_config(sc->jme_dev, JME_EFUSE_CTL2, reg, 4);
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/* Have eFuse reload station address to MAC controller. */
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reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4);
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reg &= ~EFUSE_CTL1_CMD_MASK;
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reg |= EFUSE_CTL1_CMD_AUTOLOAD | EFUSE_CTL1_EXECUTE;
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pci_write_config(sc->jme_dev, JME_EFUSE_CTL1, reg, 4);
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/*
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* Verify completion of eFuse autload command. It should be
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* completed within 108us.
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*/
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DELAY(110);
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for (i = 10; i > 0; i--) {
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reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4);
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if ((reg & (EFUSE_CTL1_AUTOLOAD_ERR |
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EFUSE_CTL1_AUTOLAOD_DONE)) != EFUSE_CTL1_AUTOLAOD_DONE) {
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DELAY(20);
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continue;
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}
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if ((reg & EFUSE_CTL1_EXECUTE) == 0)
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break;
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/* Station address loading is still in progress. */
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DELAY(20);
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}
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if (i == 0) {
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device_printf(sc->jme_dev, "eFuse autoload timed out.\n");
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return (ETIMEDOUT);
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}
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return (0);
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}
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static void
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jme_reg_macaddr(struct jme_softc *sc)
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{
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@ -446,6 +499,13 @@ jme_reg_macaddr(struct jme_softc *sc)
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device_printf(sc->jme_dev,
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"Failed to retrieve Ethernet address.\n");
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} else {
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/*
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* For controllers that use eFuse, the station address
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* could also be extracted from JME_PCI_PAR0 and
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* JME_PCI_PAR1 registers in PCI configuration space.
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* Each register holds exactly half of station address(24bits)
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* so use JME_PAR0, JME_PAR1 registers instead.
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*/
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sc->jme_eaddr[0] = (par0 >> 0) & 0xFF;
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sc->jme_eaddr[1] = (par0 >> 8) & 0xFF;
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sc->jme_eaddr[2] = (par0 >> 16) & 0xFF;
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@ -455,6 +515,42 @@ jme_reg_macaddr(struct jme_softc *sc)
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}
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}
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static void
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jme_set_macaddr(struct jme_softc *sc, uint8_t *eaddr)
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{
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uint32_t val;
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int i;
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if ((sc->jme_flags & JME_FLAG_EFUSE) != 0) {
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/*
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* Avoid reprogramming station address if the address
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* is the same as previous one. Note, reprogrammed
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* station address is permanent as if it was written
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* to EEPROM. So if station address was changed by
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* admistrator it's possible to lose factory configured
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* address when driver fails to restore its address.
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* (e.g. reboot or system crash)
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*/
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if (bcmp(eaddr, sc->jme_eaddr, ETHER_ADDR_LEN) != 0) {
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for (i = 0; i < ETHER_ADDR_LEN; i++) {
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val = JME_EFUSE_EEPROM_FUNC0 <<
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JME_EFUSE_EEPROM_FUNC_SHIFT;
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val |= JME_EFUSE_EEPROM_PAGE_BAR1 <<
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JME_EFUSE_EEPROM_PAGE_SHIFT;
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val |= (JME_PAR0 + i) <<
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JME_EFUSE_EEPROM_ADDR_SHIFT;
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val |= eaddr[i] << JME_EFUSE_EEPROM_DATA_SHIFT;
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pci_write_config(sc->jme_dev, JME_EFUSE_EEPROM,
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val | JME_EFUSE_EEPROM_WRITE, 4);
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}
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}
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} else {
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CSR_WRITE_4(sc, JME_PAR0,
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eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
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CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
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}
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}
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static void
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jme_map_intr_vector(struct jme_softc *sc)
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{
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@ -534,7 +630,7 @@ jme_attach(device_t dev)
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struct mii_data *mii;
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uint32_t reg;
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uint16_t burst;
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int error, i, msic, msixc, pmc;
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int error, i, mii_flags, msic, msixc, pmc;
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error = 0;
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sc = device_get_softc(dev);
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@ -636,11 +732,14 @@ jme_attach(device_t dev)
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goto fail;
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}
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/* Identify controller features and bugs. */
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if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2) {
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if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260 &&
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CHIPMODE_REVFM(sc->jme_chip_rev) == 2)
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sc->jme_flags |= JME_FLAG_DMA32BIT;
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sc->jme_flags |= JME_FLAG_TXCLK;
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if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5)
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sc->jme_flags |= JME_FLAG_EFUSE | JME_FLAG_PCCPCD;
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sc->jme_flags |= JME_FLAG_TXCLK | JME_FLAG_RXCLK;
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sc->jme_flags |= JME_FLAG_HWMIB;
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}
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@ -648,14 +747,20 @@ jme_attach(device_t dev)
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jme_reset(sc);
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/* Get station address. */
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reg = CSR_READ_4(sc, JME_SMBCSR);
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if ((reg & SMBCSR_EEPROM_PRESENT) != 0)
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error = jme_eeprom_macaddr(sc);
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if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) {
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if (error != 0 && (bootverbose))
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if ((sc->jme_flags & JME_FLAG_EFUSE) != 0) {
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error = jme_efuse_macaddr(sc);
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if (error == 0)
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jme_reg_macaddr(sc);
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} else {
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error = ENOENT;
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reg = CSR_READ_4(sc, JME_SMBCSR);
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if ((reg & SMBCSR_EEPROM_PRESENT) != 0)
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error = jme_eeprom_macaddr(sc);
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if (error != 0 && bootverbose)
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device_printf(sc->jme_dev,
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"ethernet hardware address not found in EEPROM.\n");
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jme_reg_macaddr(sc);
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if (error != 0)
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jme_reg_macaddr(sc);
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}
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/*
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@ -728,11 +833,17 @@ jme_attach(device_t dev)
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}
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ifp->if_capenable = ifp->if_capabilities;
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/* Wakeup PHY. */
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jme_phy_up(sc);
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mii_flags = MIIF_DOPAUSE;
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/* Ask PHY calibration to PHY driver. */
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if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5)
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mii_flags |= MIIF_MACPRIV0;
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/* Set up MII bus. */
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error = mii_attach(dev, &sc->jme_miibus, ifp, jme_mediachange,
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jme_mediastatus, BMSR_DEFCAPMASK,
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sc->jme_flags & JME_FLAG_FPGA ? MII_PHY_ANY : sc->jme_phyaddr,
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MII_OFFSET_ANY, MIIF_DOPAUSE);
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MII_OFFSET_ANY, mii_flags);
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if (error != 0) {
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device_printf(dev, "attaching PHYs failed\n");
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goto fail;
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@ -825,6 +936,9 @@ jme_detach(device_t dev)
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taskqueue_drain(sc->jme_tq, &sc->jme_int_task);
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taskqueue_drain(sc->jme_tq, &sc->jme_tx_task);
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taskqueue_drain(taskqueue_swi, &sc->jme_link_task);
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/* Restore possibly modified station address. */
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if ((sc->jme_flags & JME_FLAG_EFUSE) != 0)
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jme_set_macaddr(sc, sc->jme_eaddr);
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ether_ifdetach(ifp);
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}
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@ -1485,9 +1599,11 @@ jme_setwol(struct jme_softc *sc)
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CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) &
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~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 |
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GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000));
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if ((sc->jme_flags & JME_FLAG_RXCLK) != 0)
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CSR_WRITE_4(sc, JME_GPREG1,
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CSR_READ_4(sc, JME_GPREG1) | GPREG1_RX_MAC_CLK_DIS);
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/* No PME capability, PHY power down. */
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jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
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MII_BMCR, BMCR_PDOWN);
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jme_phy_down(sc);
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return;
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}
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@ -1519,8 +1635,7 @@ jme_setwol(struct jme_softc *sc)
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pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
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if ((ifp->if_capenable & IFCAP_WOL) == 0) {
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/* No WOL, PHY power down. */
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jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
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MII_BMCR, BMCR_PDOWN);
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jme_phy_down(sc);
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}
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}
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@ -1558,6 +1673,8 @@ jme_resume(device_t dev)
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pci_write_config(sc->jme_dev,
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pmc + PCIR_POWER_STATUS, pmstat, 2);
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}
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/* Wakeup PHY. */
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jme_phy_up(sc);
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ifp = sc->jme_ifp;
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if ((ifp->if_flags & IFF_UP) != 0) {
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ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
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@ -2210,6 +2327,13 @@ jme_link_task(void *arg, int pending)
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CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
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RXCSR_RXQ_START);
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CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
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/* Lastly enable TX/RX clock. */
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if ((sc->jme_flags & JME_FLAG_TXCLK) != 0)
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CSR_WRITE_4(sc, JME_GHC,
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CSR_READ_4(sc, JME_GHC) & ~GHC_TX_MAC_CLK_DIS);
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if ((sc->jme_flags & JME_FLAG_RXCLK) != 0)
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CSR_WRITE_4(sc, JME_GPREG1,
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CSR_READ_4(sc, JME_GPREG1) & ~GPREG1_RX_MAC_CLK_DIS);
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}
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ifp->if_drv_flags |= IFF_DRV_RUNNING;
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@ -2588,13 +2712,45 @@ jme_tick(void *arg)
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static void
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jme_reset(struct jme_softc *sc)
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{
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uint32_t ghc, gpreg;
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/* Stop receiver, transmitter. */
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jme_stop_rx(sc);
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jme_stop_tx(sc);
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/* Reset controller. */
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CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
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CSR_READ_4(sc, JME_GHC);
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DELAY(10);
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/*
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* Workaround Rx FIFO overruns seen under certain conditions.
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* Explicitly synchorize TX/RX clock. TX/RX clock should be
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* enabled only after enabling TX/RX MACs.
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*/
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if ((sc->jme_flags & (JME_FLAG_TXCLK | JME_FLAG_RXCLK)) != 0) {
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/* Disable TX clock. */
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CSR_WRITE_4(sc, JME_GHC, GHC_RESET | GHC_TX_MAC_CLK_DIS);
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/* Disable RX clock. */
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gpreg = CSR_READ_4(sc, JME_GPREG1);
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CSR_WRITE_4(sc, JME_GPREG1, gpreg | GPREG1_RX_MAC_CLK_DIS);
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gpreg = CSR_READ_4(sc, JME_GPREG1);
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/* De-assert RESET but still disable TX clock. */
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CSR_WRITE_4(sc, JME_GHC, GHC_TX_MAC_CLK_DIS);
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ghc = CSR_READ_4(sc, JME_GHC);
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/* Enable TX clock. */
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CSR_WRITE_4(sc, JME_GHC, ghc & ~GHC_TX_MAC_CLK_DIS);
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/* Enable RX clock. */
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CSR_WRITE_4(sc, JME_GPREG1, gpreg & ~GPREG1_RX_MAC_CLK_DIS);
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CSR_READ_4(sc, JME_GPREG1);
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/* Disable TX/RX clock again. */
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CSR_WRITE_4(sc, JME_GHC, GHC_TX_MAC_CLK_DIS);
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CSR_WRITE_4(sc, JME_GPREG1, gpreg | GPREG1_RX_MAC_CLK_DIS);
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} else
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CSR_WRITE_4(sc, JME_GHC, 0);
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CSR_READ_4(sc, JME_GHC);
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DELAY(10);
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CSR_WRITE_4(sc, JME_GHC, 0);
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}
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static void
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@ -2613,7 +2769,6 @@ jme_init_locked(struct jme_softc *sc)
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{
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struct ifnet *ifp;
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struct mii_data *mii;
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uint8_t eaddr[ETHER_ADDR_LEN];
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bus_addr_t paddr;
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uint32_t reg;
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int error;
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@ -2649,10 +2804,7 @@ jme_init_locked(struct jme_softc *sc)
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jme_init_ssb(sc);
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/* Reprogram the station address. */
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bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
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CSR_WRITE_4(sc, JME_PAR0,
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eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
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CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
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jme_set_macaddr(sc, IF_LLADDR(sc->jme_ifp));
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/*
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* Configure Tx queue.
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@ -2790,6 +2942,30 @@ jme_init_locked(struct jme_softc *sc)
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PCCRX_COAL_PKT_MASK;
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CSR_WRITE_4(sc, JME_PCCRX0, reg);
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/*
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* Configure PCD(Packet Completion Deferring). It seems PCD
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* generates an interrupt when the time interval between two
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* back-to-back incoming/outgoing packet is long enough for
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* it to reach its timer value 0. The arrival of new packets
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* after timer has started causes the PCD timer to restart.
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* Unfortunately, it's not clear how PCD is useful at this
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* moment, so just use the same of PCC parameters.
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*/
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if ((sc->jme_flags & JME_FLAG_PCCPCD) != 0) {
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sc->jme_rx_pcd_to = sc->jme_rx_coal_to;
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if (sc->jme_rx_coal_to > PCDRX_TO_MAX)
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sc->jme_rx_pcd_to = PCDRX_TO_MAX;
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sc->jme_tx_pcd_to = sc->jme_tx_coal_to;
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if (sc->jme_tx_coal_to > PCDTX_TO_MAX)
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sc->jme_tx_pcd_to = PCDTX_TO_MAX;
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reg = sc->jme_rx_pcd_to << PCDRX0_TO_THROTTLE_SHIFT;
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reg |= sc->jme_rx_pcd_to << PCDRX0_TO_SHIFT;
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CSR_WRITE_4(sc, PCDRX_REG(0), reg);
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reg = sc->jme_tx_pcd_to << PCDTX_TO_THROTTLE_SHIFT;
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reg |= sc->jme_tx_pcd_to << PCDTX_TO_SHIFT;
|
||||
CSR_WRITE_4(sc, JME_PCDTX, reg);
|
||||
}
|
||||
|
||||
/* Configure shadow status block but don't enable posting. */
|
||||
paddr = sc->jme_rdata.jme_ssb_block_paddr;
|
||||
CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
|
||||
@ -3195,6 +3371,43 @@ jme_stats_update(struct jme_softc *sc)
|
||||
stat->tx_bad_frames += ostat->tx_bad_frames;
|
||||
}
|
||||
|
||||
static void
|
||||
jme_phy_down(struct jme_softc *sc)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
||||
jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, BMCR_PDOWN);
|
||||
if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5) {
|
||||
reg = CSR_READ_4(sc, JME_PHYPOWDN);
|
||||
reg |= 0x0000000F;
|
||||
CSR_WRITE_4(sc, JME_PHYPOWDN, reg);
|
||||
reg = pci_read_config(sc->jme_dev, JME_PCI_PE1, 4);
|
||||
reg &= ~PE1_GIGA_PDOWN_MASK;
|
||||
reg |= PE1_GIGA_PDOWN_D3;
|
||||
pci_write_config(sc->jme_dev, JME_PCI_PE1, reg, 4);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
jme_phy_up(struct jme_softc *sc)
|
||||
{
|
||||
uint32_t reg;
|
||||
uint16_t bmcr;
|
||||
|
||||
bmcr = jme_miibus_readreg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR);
|
||||
bmcr &= ~BMCR_PDOWN;
|
||||
jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, bmcr);
|
||||
if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5) {
|
||||
reg = CSR_READ_4(sc, JME_PHYPOWDN);
|
||||
reg &= ~0x0000000F;
|
||||
CSR_WRITE_4(sc, JME_PHYPOWDN, reg);
|
||||
reg = pci_read_config(sc->jme_dev, JME_PCI_PE1, 4);
|
||||
reg &= ~PE1_GIGA_PDOWN_MASK;
|
||||
reg |= PE1_GIGA_PDOWN_DIS;
|
||||
pci_write_config(sc->jme_dev, JME_PCI_PE1, reg, 4);
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
|
||||
{
|
||||
|
||||
@ -63,6 +63,10 @@
|
||||
|
||||
#define JME_PCI_DBG 0x9C
|
||||
|
||||
#define JME_PCI_PAR0 0xA4 /* JMC25x/JMC26x REVFM >= 5 */
|
||||
|
||||
#define JME_PCI_PAR1 0xA8 /* JMC25x/JMC26x REVFM >= 5 */
|
||||
|
||||
#define JME_PCI_SPI 0xB0
|
||||
|
||||
#define SPI_ENB 0x00000010
|
||||
@ -71,6 +75,21 @@
|
||||
#define SPI_SCK_CTRL 0x00000002
|
||||
#define SPI_CS_N_CTRL 0x00000001
|
||||
|
||||
#define JME_EFUSE_CTL1 0xB8
|
||||
#define EFUSE_CTL1_DATA_MASK 0xF0000000
|
||||
#define EFUSE_CTL1_EXECUTE 0x08000000
|
||||
#define EFUSE_CTL1_CMD_AUTOLOAD 0x02000000
|
||||
#define EFUSE_CTL1_CMD_READ 0x04000000
|
||||
#define EFUSE_CTL1_CMD_BLOW 0x06000000
|
||||
#define EFUSE_CTL1_CMD_MASK 0x06000000
|
||||
#define EFUSE_CTL1_AUTOLOAD_ERR 0x00010000
|
||||
#define EFUSE_CTL1_BYTE_SEL_MASK 0x0000FF00
|
||||
#define EFUSE_CTL1_BIT_SEL_MASK 0x00000070
|
||||
#define EFUSE_CTL1_AUTOLAOD_DONE 0x00000001
|
||||
|
||||
#define JME_EFUSE_CTL2 0xBC
|
||||
#define EFUSE_CTL2_RESET 0x00008000
|
||||
|
||||
#define JME_PCI_PHYCFG0 0xC0
|
||||
|
||||
#define JME_PCI_PHYCFG1 0xC4
|
||||
@ -86,7 +105,7 @@
|
||||
/* PCIe link error/status. */
|
||||
#define JME_PCI_LES 0xD8
|
||||
|
||||
/* propeietary register 0. */
|
||||
/* Proprietary register 0. */
|
||||
#define JME_PCI_PE0 0xE0
|
||||
#define PE0_SPI_EXIST 0x00200000
|
||||
#define PE0_PME_D0 0x00100000
|
||||
@ -115,7 +134,31 @@
|
||||
#define PE0_PM_AUXC_MASK 0x00000007
|
||||
#define PE0_PM_AUXC_DEF 0x00000007
|
||||
|
||||
/* Proprietary register 1. */
|
||||
#define JME_PCI_PE1 0xE4
|
||||
#define PE1_GIGA_PDOWN_MASK 0x0000C000
|
||||
#define PE1_GIGA_PDOWN_DIS 0x00000000
|
||||
#define PE1_GIGA_PDOWN_D3 0x00004000
|
||||
#define PE1_GIGA_PDOWN_PCIE_SHUTDOWN 0x00008000
|
||||
#define PE1_GIGA_PDOWN_PCIE_IDDQ 0x0000C000
|
||||
|
||||
#define JME_EFUSE_EEPROM 0xE8
|
||||
#define JME_EFUSE_EEPROM_WRITE 0x80000000
|
||||
#define JME_EFUSE_EEPROM_FUNC_MASK 0x70000000
|
||||
#define JME_EFUSE_EEPROM_PAGE_MASK 0x0F000000
|
||||
#define JME_EFUSE_EEPROM_ADDR_MASK 0x00FF0000
|
||||
#define JME_EFUSE_EEPROM_DATA_MASK 0x0000FF00
|
||||
#define JME_EFUSE_EEPROM_SMBSTAT_MASK 0x000000FF
|
||||
#define JME_EFUSE_EEPROM_FUNC_SHIFT 28
|
||||
#define JME_EFUSE_EEPROM_PAGE_SHIFT 24
|
||||
#define JME_EFUSE_EEPROM_ADDR_SHIFT 16
|
||||
#define JME_EFUSE_EEPROM_DATA_SHIFT 8
|
||||
#define JME_EFUSE_EEPROM_SMBSTAT_SHIFT 0
|
||||
|
||||
#define JME_EFUSE_EEPROM_FUNC0 0
|
||||
#define JME_EFUSE_EEPROM_PAGE_BAR0 0
|
||||
#define JME_EFUSE_EEPROM_PAGE_BAR1 1
|
||||
#define JME_EFUSE_EEPROM_PAGE_BAR2 2
|
||||
|
||||
#define JME_PCI_PHYTEST 0xF8
|
||||
|
||||
@ -312,7 +355,7 @@
|
||||
#define RXMAC_PAD_10BYTES 0x00000002
|
||||
#define RXMAC_CSUM_ENB 0x00000001
|
||||
|
||||
/* Rx unicast MAC address. */
|
||||
/* Rx unicast MAC address. Read-only on JMC25x/JMC26x REVFM >= 5 */
|
||||
#define JME_PAR0 0x0038
|
||||
#define JME_PAR1 0x003C
|
||||
|
||||
@ -455,6 +498,7 @@
|
||||
#define JME_GIGARCHI 0x041C
|
||||
#define JME_GIGARDLO 0x0420
|
||||
#define JME_GIGARDHI 0x0424
|
||||
#define JME_PHYPOWDN 0x0424 /* JMC250/JMC260 REVFM >= 5 */
|
||||
|
||||
/* BIST status and control. */
|
||||
#define JME_GIGACSR 0x0428
|
||||
@ -627,6 +671,7 @@
|
||||
|
||||
/* General purpose register 1. */
|
||||
#define JME_GPREG1 0x080C
|
||||
#define GPREG1_RX_MAC_CLK_DIS 0x04000000 /* JMC250/JMC260 REVFM >= 2 */
|
||||
#define GPREG1_RSS_IPV6_10_100 0x00000040 /* JMC250 A2 */
|
||||
#define GPREG1_HDPX_FIX 0x00000020 /* JMC250 A2 */
|
||||
#define GPREG1_INTDLY_UNIT_16US 0x00000018 /* JMC250 A1, A2 */
|
||||
@ -816,6 +861,53 @@
|
||||
#define SHBASE_POST_FORCE 0x00000002
|
||||
#define SHBASE_POST_ENB 0x00000001
|
||||
|
||||
#define JME_PCDRX_BASE 0x0850
|
||||
#define JME_PCDRX_END 0x0857
|
||||
#define PCDRX_REG(x) (JME_PCDRX_BASE + (((x) / 2) * 4))
|
||||
#define PCDRX1_TO_THROTTLE_MASK 0xFF000000
|
||||
#define PCDRX1_TO_MASK 0x00FF0000
|
||||
#define PCDRX0_TO_THROTTLE_MASK 0x0000FF00
|
||||
#define PCDRX0_TO_MASK 0x000000FF
|
||||
#define PCDRX1_TO_THROTTLE_SHIFT 24
|
||||
#define PCDRX1_TO_SHIFT 16
|
||||
#define PCDRX0_TO_THROTTLE_SHIFT 8
|
||||
#define PCDRX0_TO_SHIFT 0
|
||||
#define PCDRX_TO_MIN 1
|
||||
#define PCDRX_TO_MAX 255
|
||||
|
||||
#define JME_PCDTX 0x0858
|
||||
#define PCDTX_TO_THROTTLE_MASK 0x0000FF00
|
||||
#define PCDTX_TO_MASK 0x000000FF
|
||||
#define PCDTX_TO_THROTTLE_SHIFT 8
|
||||
#define PCDTX_TO_SHIFT 0
|
||||
#define PCDTX_TO_MIN 1
|
||||
#define PCDTX_TO_MAX 255
|
||||
|
||||
#define JME_PCCPCD_STAT 0x085C
|
||||
#define PCCPCD_STAT_RX3_MASK 0xFF000000
|
||||
#define PCCPCD_STAT_RX2_MASK 0x00FF0000
|
||||
#define PCCPCD_STAT_RX1_MASK 0x0000FF00
|
||||
#define PCCPCD_STAT_RX0_MASK 0x000000FF
|
||||
#define PCCPCD_STAT_RX3_SHIFT 24
|
||||
#define PCCPCD_STAT_RX2_SHIFT 16
|
||||
#define PCCPCD_STAT_RX1_SHIFT 8
|
||||
#define PCCPCD_STAT_RX0_SHIFT 0
|
||||
|
||||
/* TX data throughput in KB. */
|
||||
#define JME_TX_THROUGHPUT 0x0860
|
||||
#define TX_THROUGHPUT_MASK 0x000FFFFF
|
||||
|
||||
/* RX data throughput in KB. */
|
||||
#define JME_RX_THROUGHPUT 0x0864
|
||||
#define RX_THROUGHPUT_MASK 0x000FFFFF
|
||||
|
||||
#define JME_LPI_CTL 0x086C
|
||||
#define LPI_STAT_ANC_ANF 0x00000010
|
||||
#define LPI_STAT_AN_TIMEOUT 0x00000008
|
||||
#define LPI_STAT_RX_LPI 0x00000004
|
||||
#define LPI_INT_ENB 0x00000002
|
||||
#define LPI_REQ 0x00000001
|
||||
|
||||
/* Timer 1 and 2. */
|
||||
#define JME_TIMER1 0x0870
|
||||
#define JME_TIMER2 0x0874
|
||||
@ -824,6 +916,15 @@
|
||||
#define TIMER_CNT_SHIFT 0
|
||||
#define TIMER_UNIT 1024 /* 1024us */
|
||||
|
||||
/* Timer 3. */
|
||||
#define JME_TIMER3 0x0878
|
||||
#define TIMER3_TIMEOUT 0x00010000
|
||||
#define TIMER3_TIMEOUT_COUNT_MASK 0x0000FF00 /* 130ms unit */
|
||||
#define TIMER3_TIMEOUT_VAL_MASK 0x000000E0
|
||||
#define TIMER3_ENB 0x00000001
|
||||
#define TIMER3_TIMEOUT_COUNT_SHIFT 8
|
||||
#define TIMER3_TIMEOUT_VALUE_SHIFT 1
|
||||
|
||||
/* Aggresive power mode control. */
|
||||
#define JME_APMC 0x087C
|
||||
#define APMC_PCIE_SDOWN_STAT 0x80000000
|
||||
|
||||
@ -185,19 +185,22 @@ struct jme_softc {
|
||||
uint32_t jme_tx_dma_size;
|
||||
uint32_t jme_rx_dma_size;
|
||||
int jme_flags;
|
||||
#define JME_FLAG_FPGA 0x0001
|
||||
#define JME_FLAG_PCIE 0x0002
|
||||
#define JME_FLAG_PCIX 0x0003
|
||||
#define JME_FLAG_MSI 0x0004
|
||||
#define JME_FLAG_MSIX 0x0010
|
||||
#define JME_FLAG_PMCAP 0x0020
|
||||
#define JME_FLAG_FASTETH 0x0040
|
||||
#define JME_FLAG_NOJUMBO 0x0080
|
||||
#define JME_FLAG_TXCLK 0x0100
|
||||
#define JME_FLAG_DMA32BIT 0x0200
|
||||
#define JME_FLAG_HWMIB 0x0400
|
||||
#define JME_FLAG_DETACH 0x4000
|
||||
#define JME_FLAG_LINK 0x8000
|
||||
#define JME_FLAG_FPGA 0x00000001
|
||||
#define JME_FLAG_PCIE 0x00000002
|
||||
#define JME_FLAG_PCIX 0x00000004
|
||||
#define JME_FLAG_MSI 0x00000008
|
||||
#define JME_FLAG_MSIX 0x00000010
|
||||
#define JME_FLAG_PMCAP 0x00000020
|
||||
#define JME_FLAG_FASTETH 0x00000040
|
||||
#define JME_FLAG_NOJUMBO 0x00000080
|
||||
#define JME_FLAG_RXCLK 0x00000100
|
||||
#define JME_FLAG_TXCLK 0x00000200
|
||||
#define JME_FLAG_DMA32BIT 0x00000400
|
||||
#define JME_FLAG_HWMIB 0x00000800
|
||||
#define JME_FLAG_EFUSE 0x00001000
|
||||
#define JME_FLAG_PCCPCD 0x00002000
|
||||
#define JME_FLAG_DETACH 0x40000000
|
||||
#define JME_FLAG_LINK 0x80000000
|
||||
|
||||
struct jme_hw_stats jme_ostats;
|
||||
struct jme_hw_stats jme_stats;
|
||||
@ -210,8 +213,10 @@ struct jme_softc {
|
||||
uint32_t jme_rxcsr;
|
||||
int jme_process_limit;
|
||||
int jme_tx_coal_to;
|
||||
int jme_tx_pcd_to;
|
||||
int jme_tx_coal_pkt;
|
||||
int jme_rx_coal_to;
|
||||
int jme_rx_pcd_to;
|
||||
int jme_rx_coal_pkt;
|
||||
volatile int jme_morework;
|
||||
|
||||
|
||||
@ -104,6 +104,7 @@ jmphy_attach(device_t dev)
|
||||
struct mii_softc *sc;
|
||||
struct mii_attach_args *ma;
|
||||
struct mii_data *mii;
|
||||
struct ifnet *ifp;
|
||||
|
||||
jsc = device_get_softc(dev);
|
||||
sc = &jsc->mii_sc;
|
||||
@ -118,6 +119,10 @@ jmphy_attach(device_t dev)
|
||||
sc->mii_service = jmphy_service;
|
||||
sc->mii_pdata = mii;
|
||||
|
||||
ifp = sc->mii_pdata->mii_ifp;
|
||||
if (strcmp(ifp->if_dname, "jme") == 0 &&
|
||||
(sc->mii_flags & MIIF_MACPRIV0) != 0)
|
||||
sc->mii_flags |= MIIF_PHYPRIV0;
|
||||
jsc->mii_oui = MII_OUI(ma->mii_id1, ma->mii_id2);
|
||||
jsc->mii_model = MII_MODEL(ma->mii_id2);
|
||||
jsc->mii_rev = MII_REV(ma->mii_id2);
|
||||
@ -265,6 +270,7 @@ static void
|
||||
jmphy_reset(struct mii_softc *sc)
|
||||
{
|
||||
struct jmphy_softc *jsc;
|
||||
uint16_t t2cr, val;
|
||||
int i;
|
||||
|
||||
jsc = (struct jmphy_softc *)sc;
|
||||
@ -279,6 +285,39 @@ jmphy_reset(struct mii_softc *sc)
|
||||
if ((PHY_READ(sc, MII_BMCR) & BMCR_RESET) == 0)
|
||||
break;
|
||||
}
|
||||
/* Perform vendor recommended PHY calibration. */
|
||||
if ((sc->mii_flags & MIIF_PHYPRIV0) != 0) {
|
||||
/* Select PHY test mode 1. */
|
||||
t2cr = PHY_READ(sc, MII_100T2CR);
|
||||
t2cr &= ~GTCR_TEST_MASK;
|
||||
t2cr |= 0x2000;
|
||||
PHY_WRITE(sc, MII_100T2CR, t2cr);
|
||||
/* Apply calibration patch. */
|
||||
PHY_WRITE(sc, JMPHY_SPEC_ADDR, JMPHY_SPEC_ADDR_READ |
|
||||
JMPHY_EXT_COMM_2);
|
||||
val = PHY_READ(sc, JMPHY_SPEC_DATA);
|
||||
val &= ~0x0002;
|
||||
val |= 0x0010 | 0x0001;
|
||||
PHY_WRITE(sc, JMPHY_SPEC_DATA, val);
|
||||
PHY_WRITE(sc, JMPHY_SPEC_ADDR, JMPHY_SPEC_ADDR_WRITE |
|
||||
JMPHY_EXT_COMM_2);
|
||||
|
||||
/* XXX 20ms to complete recalibration. */
|
||||
DELAY(20 * 1000);
|
||||
|
||||
PHY_READ(sc, MII_100T2CR);
|
||||
PHY_WRITE(sc, JMPHY_SPEC_ADDR, JMPHY_SPEC_ADDR_READ |
|
||||
JMPHY_EXT_COMM_2);
|
||||
val = PHY_READ(sc, JMPHY_SPEC_DATA);
|
||||
val &= ~(0x0001 | 0x0002 | 0x0010);
|
||||
PHY_WRITE(sc, JMPHY_SPEC_DATA, val);
|
||||
PHY_WRITE(sc, JMPHY_SPEC_ADDR, JMPHY_SPEC_ADDR_WRITE |
|
||||
JMPHY_EXT_COMM_2);
|
||||
/* Disable PHY test mode. */
|
||||
PHY_READ(sc, MII_100T2CR);
|
||||
t2cr &= ~GTCR_TEST_MASK;
|
||||
PHY_WRITE(sc, MII_100T2CR, t2cr);
|
||||
}
|
||||
}
|
||||
|
||||
static uint16_t
|
||||
|
||||
@ -105,4 +105,13 @@
|
||||
#define JMPHY_TMCTL 0x1A
|
||||
#define JMPHY_TMCTL_SLEEP_ENB 0x1000
|
||||
|
||||
/* PHY specific configuration register. */
|
||||
#define JMPHY_SPEC_ADDR 0x1E
|
||||
#define JMPHY_SPEC_ADDR_READ 0x4000
|
||||
#define JMPHY_SPEC_ADDR_WRITE 0x8000
|
||||
|
||||
#define JMPHY_SPEC_DATA 0x1F
|
||||
|
||||
#define JMPHY_EXT_COMM_2 0x32
|
||||
|
||||
#endif /* _DEV_MII_JMPHYREG_H_ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user