Several chipset drivers alter parameters relevant for the DMA tag creation,
i.e. alignment, max_address, max_iosize and segsize (only max_address is thought to have an negative impact regarding this issue though), after calling ata_dmainit() either directly or indirectly so these values have no effect or at least no effect on the DMA tags and the defaults are used for the latter instead. So change the drivers to set these parameters up-front and ata_dmainit() to honor them. Reviewd by: mav MFC after: 1 month
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@ -68,17 +68,28 @@ ata_dmainit(device_t dev)
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struct ata_channel *ch = device_get_softc(dev);
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struct ata_dc_cb_args dcba;
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ch->dma.alloc = ata_dmaalloc;
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ch->dma.free = ata_dmafree;
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ch->dma.setprd = ata_dmasetprd;
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ch->dma.load = ata_dmaload;
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ch->dma.unload = ata_dmaunload;
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ch->dma.alignment = 2;
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ch->dma.boundary = 65536;
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ch->dma.segsize = 65536;
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ch->dma.max_iosize = MIN((ATA_DMA_ENTRIES - 1) * PAGE_SIZE, MAXPHYS);
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ch->dma.max_address = BUS_SPACE_MAXADDR_32BIT;
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ch->dma.dma_slots = 1;
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if (ch->dma.alloc == NULL)
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ch->dma.alloc = ata_dmaalloc;
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if (ch->dma.free == NULL)
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ch->dma.free = ata_dmafree;
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if (ch->dma.setprd == NULL)
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ch->dma.setprd = ata_dmasetprd;
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if (ch->dma.load == NULL)
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ch->dma.load = ata_dmaload;
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if (ch->dma.unload == NULL)
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ch->dma.unload = ata_dmaunload;
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if (ch->dma.alignment == 0)
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ch->dma.alignment = 2;
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if (ch->dma.boundary == 0)
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ch->dma.boundary = 65536;
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if (ch->dma.segsize == 0)
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ch->dma.segsize = 65536;
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if (ch->dma.max_iosize == 0)
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ch->dma.max_iosize = MIN((ATA_DMA_ENTRIES - 1) * PAGE_SIZE, MAXPHYS);
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if (ch->dma.max_address == 0)
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ch->dma.max_address = BUS_SPACE_MAXADDR_32BIT;
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if (ch->dma.dma_slots == 0)
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ch->dma.dma_slots = 1;
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if (bus_dma_tag_create(bus_get_dma_tag(dev), ch->dma.alignment, 0,
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ch->dma.max_address, BUS_SPACE_MAXADDR,
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@ -1005,12 +1005,12 @@ ata_ahci_dmainit(device_t dev)
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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struct ata_channel *ch = device_get_softc(dev);
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ata_dmainit(dev);
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/* note start and stop are not used here */
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ch->dma.setprd = ata_ahci_dmasetprd;
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ch->dma.max_iosize = (ATA_AHCI_DMA_ENTRIES - 1) * PAGE_SIZE;
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if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_64BIT)
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ch->dma.max_address = BUS_SPACE_MAXADDR;
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ata_dmainit(dev);
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}
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static int
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@ -56,7 +56,6 @@ static int ata_cyrix_chipinit(device_t dev);
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static int ata_cyrix_ch_attach(device_t dev);
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static int ata_cyrix_setmode(device_t dev, int target, int mode);
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/*
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* Cyrix chipset support functions
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*/
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@ -89,15 +88,12 @@ static int
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ata_cyrix_ch_attach(device_t dev)
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{
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struct ata_channel *ch = device_get_softc(dev);
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int error;
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error = ata_pci_ch_attach(dev);
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ch->dma.alignment = 16;
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ch->dma.max_iosize = 64 * DEV_BSIZE;
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return (error);
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return (ata_pci_ch_attach(dev));
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}
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static int
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ata_cyrix_setmode(device_t dev, int target, int mode)
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{
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@ -614,7 +614,6 @@ ata_marvell_edma_dmainit(device_t dev)
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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struct ata_channel *ch = device_get_softc(dev);
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ata_dmainit(dev);
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/* note start and stop are not used here */
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ch->dma.setprd = ata_marvell_edma_dmasetprd;
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@ -625,6 +624,7 @@ ata_marvell_edma_dmainit(device_t dev)
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/* chip does not reliably do 64K DMA transfers */
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if (ctlr->chip->cfg2 == MV_50XX || ctlr->chip->cfg2 == MV_60XX)
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ch->dma.max_iosize = 64 * DEV_BSIZE;
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ata_dmainit(dev);
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}
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ATA_DECLARE_DRIVER(ata_marvell);
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@ -90,12 +90,10 @@ static int
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ata_national_ch_attach(device_t dev)
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{
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struct ata_channel *ch = device_get_softc(dev);
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int error;
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error = ata_pci_ch_attach(dev);
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ch->dma.alignment = 16;
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ch->dma.max_iosize = 64 * DEV_BSIZE;
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return (error);
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return (ata_pci_ch_attach(dev));
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}
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static int
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@ -979,13 +979,12 @@ ata_promise_mio_dmainit(device_t dev)
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{
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struct ata_channel *ch = device_get_softc(dev);
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ata_dmainit(dev);
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/* note start and stop are not used here */
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ch->dma.setprd = ata_promise_mio_setprd;
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ch->dma.max_iosize = 65536;
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ata_dmainit(dev);
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}
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#define MAXLASTSGSIZE (32 * sizeof(u_int32_t))
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static void
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ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
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@ -179,8 +179,6 @@ ata_serverworks_ch_attach(device_t dev)
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int ch_offset;
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int i;
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ata_pci_dmainit(dev);
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ch_offset = ch->unit * 0x100;
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for (i = ATA_DATA; i < ATA_MAX_RES; i++)
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@ -245,6 +243,8 @@ ata_serverworks_ch_attach(device_t dev)
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/* chip does not reliably do 64K DMA transfers */
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ch->dma.max_iosize = 64 * DEV_BSIZE;
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ata_pci_dmainit(dev);
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return 0;
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}
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@ -289,8 +289,6 @@ ata_sii_ch_attach(device_t dev)
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int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
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int i;
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ata_pci_dmainit(dev);
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for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
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ch->r_io[i].res = ctlr->r_res2;
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ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8);
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@ -332,6 +330,9 @@ ata_sii_ch_attach(device_t dev)
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ch->hw.status = ata_sii_status;
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if (ctlr->chip->cfg2 & SII_SETCLK)
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ch->flags |= ATA_CHECKS_CABLE;
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ata_pci_dmainit(dev);
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return 0;
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}
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@ -915,11 +916,11 @@ ata_siiprb_dmainit(device_t dev)
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{
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struct ata_channel *ch = device_get_softc(dev);
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ata_dmainit(dev);
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/* note start and stop are not used here */
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ch->dma.setprd = ata_siiprb_dmasetprd;
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ch->dma.max_address = BUS_SPACE_MAXADDR;
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ch->dma.max_iosize = (ATA_SIIPRB_DMA_ENTRIES - 1) * PAGE_SIZE;
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ata_dmainit(dev);
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}
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ATA_DECLARE_DRIVER(ata_sii);
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