Remove files repocopied to sys/sparc64/sbus.
This commit is contained in:
Tom Rhodes
parent
acad338196
commit
4fc173317b
@ -82,14 +82,14 @@ __FBSDID("$FreeBSD$");
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#include <machine/ofw_machdep.h>
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#include <machine/resource.h>
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#include <sys/rman.h>
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#include <sparc64/sbus/sbusvar.h>
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#include <cam/cam.h>
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#include <cam/cam_ccb.h>
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#include <cam/scsi/scsi_all.h>
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#include <dev/esp/lsi64854reg.h>
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#include <dev/esp/lsi64854var.h>
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#include <sparc64/sbus/lsi64854reg.h>
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#include <sparc64/sbus/lsi64854var.h>
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#include <sparc64/sbus/sbusvar.h>
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#include <dev/esp/ncr53c9xreg.h>
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#include <dev/esp/ncr53c9xvar.h>
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@ -1,722 +0,0 @@
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/*-
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* Copyright (c) 2004 Scott Long
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/* $NetBSD: lsi64854.c,v 1.22 2002/10/01 07:07:03 petrov Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Paul Kranenburg.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/resource.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <machine/bus.h>
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#include <cam/cam.h>
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#include <cam/cam_ccb.h>
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#include <cam/scsi/scsi_all.h>
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#include <dev/esp/lsi64854reg.h>
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#include <dev/esp/lsi64854var.h>
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#include <dev/esp/ncr53c9xreg.h>
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#include <dev/esp/ncr53c9xvar.h>
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void lsi64854_reset(struct lsi64854_softc *);
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int lsi64854_setup(struct lsi64854_softc *, caddr_t *, size_t *,
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int, size_t *);
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int lsi64854_setup_pp(struct lsi64854_softc *, caddr_t *, size_t *,
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int, size_t *);
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#ifdef DEBUG
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#define LDB_SCSI 1
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#define LDB_ENET 2
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#define LDB_PP 4
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#define LDB_ANY 0xff
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int lsi64854debug = 0;
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#define DPRINTF(a,x) do { if (lsi64854debug & (a)) printf x ; } while (0)
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#else
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#define DPRINTF(a,x)
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#endif
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#define MAX_DMA_SZ (16*1024*1024)
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/*
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* Finish attaching this DMA device.
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* Front-end must fill in these fields:
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* sc_regs
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* sc_burst
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* sc_channel (one of SCSI, ENET, PP)
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* sc_client (one of SCSI, ENET, PP `soft_c' pointers)
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*/
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void
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lsi64854_attach(struct lsi64854_softc *sc)
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{
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uint32_t csr;
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sc->dv_name = device_get_nameunit(sc->sc_dev);
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/* Indirect functions */
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switch (sc->sc_channel) {
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case L64854_CHANNEL_SCSI:
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sc->intr = lsi64854_scsi_intr;
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sc->setup = lsi64854_setup;
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break;
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case L64854_CHANNEL_ENET:
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sc->intr = lsi64854_enet_intr;
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break;
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case L64854_CHANNEL_PP:
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sc->setup = lsi64854_setup_pp;
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break;
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default:
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printf("%s: unknown channel\n", sc->dv_name);
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}
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sc->reset = lsi64854_reset;
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/* Allocate a dmamap */
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if (bus_dma_tag_create(sc->sc_parent_dmat, /* parent */
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1, 0, /* algnment, boundary */
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BUS_SPACE_MAXADDR, /* lowaddr */
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BUS_SPACE_MAXADDR, /* highaddr */
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NULL, NULL, /* filter, filterarg */
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MAX_DMA_SZ, /* maxsize */
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1, /* nsegments */
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MAX_DMA_SZ, /* maxsegsize */
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BUS_DMA_ALLOCNOW, /* flags */
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NULL, NULL, /* lockfunc, lockarg */
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&sc->sc_buffer_dmat)) {
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printf("%s: can't allocate buffer DMA tag\n", sc->dv_name);
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return;
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}
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if (bus_dmamap_create(sc->sc_buffer_dmat, 0, &sc->sc_dmamap) != 0) {
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printf("%s: DMA map create failed\n", sc->dv_name);
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return;
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}
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csr = L64854_GCSR(sc);
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sc->sc_rev = csr & L64854_DEVID;
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if (sc->sc_rev == DMAREV_HME) {
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return;
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}
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printf(": DMA rev ");
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switch (sc->sc_rev) {
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case DMAREV_0:
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printf("0");
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break;
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case DMAREV_ESC:
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printf("esc");
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break;
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case DMAREV_1:
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printf("1");
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break;
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case DMAREV_PLUS:
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printf("1+");
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break;
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case DMAREV_2:
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printf("2");
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break;
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default:
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printf("unknown (0x%x)", sc->sc_rev);
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}
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DPRINTF(LDB_ANY, (", burst 0x%x, csr 0x%x", sc->sc_burst, csr));
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printf("\n");
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}
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/*
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* DMAWAIT waits while condition is true
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*/
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#define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) { \
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int count = 500000; \
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while ((COND) && --count > 0) DELAY(1); \
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if (count == 0) { \
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printf("%s: line %d: CSR = 0x%lx\n", __FILE__, __LINE__, \
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(u_long)L64854_GCSR(SC)); \
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if (DONTPANIC) \
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printf(MSG); \
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else \
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panic(MSG); \
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} \
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} while (0)
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#define DMA_DRAIN(sc, dontpanic) do { \
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uint32_t csr; \
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/* \
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* DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \
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* and "drain" bits while it is still thinking about a \
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* request. \
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* other revs: D_ESC_R_PEND bit reads as 0 \
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*/ \
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DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\
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if (sc->sc_rev != DMAREV_HME) { \
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/* \
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* Select drain bit based on revision \
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* also clears errors and D_TC flag \
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*/ \
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csr = L64854_GCSR(sc); \
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if (sc->sc_rev == DMAREV_1 || sc->sc_rev == DMAREV_0) \
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csr |= D_ESC_DRAIN; \
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else \
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csr |= L64854_INVALIDATE; \
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\
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L64854_SCSR(sc,csr); \
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} \
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/* \
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* Wait for draining to finish \
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* rev0 & rev1 call this PACKCNT \
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*/ \
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DMAWAIT(sc, L64854_GCSR(sc) & L64854_DRAINING, "DRAINING", dontpanic);\
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} while(0)
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#define DMA_FLUSH(sc, dontpanic) do { \
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uint32_t csr; \
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/* \
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* DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \
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* and "drain" bits while it is still thinking about a \
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* request. \
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* other revs: D_ESC_R_PEND bit reads as 0 \
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*/ \
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DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\
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csr = L64854_GCSR(sc); \
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csr &= ~(L64854_WRITE|L64854_EN_DMA); /* no-ops on ENET */ \
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csr |= L64854_INVALIDATE; /* XXX FAS ? */ \
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L64854_SCSR(sc,csr); \
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} while(0)
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void
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lsi64854_reset(struct lsi64854_softc *sc)
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{
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uint32_t csr;
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DMA_FLUSH(sc, 1);
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csr = L64854_GCSR(sc);
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DPRINTF(LDB_ANY, ("lsi64854_reset: csr 0x%x\n", csr));
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/*
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* XXX is sync needed?
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if (sc->sc_dmamap->dm_nsegs > 0)
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bus_dmamap_unload(sc->sc_buffer_dmat, sc->sc_dmamap);
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*/
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if (sc->sc_rev == DMAREV_HME)
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L64854_SCSR(sc, csr | D_HW_RESET_FAS366);
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csr |= L64854_RESET; /* reset DMA */
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L64854_SCSR(sc, csr);
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DELAY(200); /* > 10 Sbus clocks(?) */
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/*DMAWAIT1(sc); why was this here? */
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csr = L64854_GCSR(sc);
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csr &= ~L64854_RESET; /* de-assert reset line */
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L64854_SCSR(sc, csr);
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DELAY(5); /* allow a few ticks to settle */
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csr = L64854_GCSR(sc);
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csr |= L64854_INT_EN; /* enable interrupts */
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if (sc->sc_rev > DMAREV_1 && sc->sc_channel == L64854_CHANNEL_SCSI) {
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if (sc->sc_rev == DMAREV_HME)
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csr |= D_TWO_CYCLE;
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else
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csr |= D_FASTER;
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}
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/* Set burst */
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switch (sc->sc_rev) {
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case DMAREV_HME:
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case DMAREV_2:
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csr &= ~L64854_BURST_SIZE;
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if (sc->sc_burst == 32) {
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csr |= L64854_BURST_32;
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} else if (sc->sc_burst == 16) {
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csr |= L64854_BURST_16;
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} else {
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csr |= L64854_BURST_0;
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}
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break;
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case DMAREV_ESC:
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csr |= D_ESC_AUTODRAIN; /* Auto-drain */
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if (sc->sc_burst == 32) {
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csr &= ~D_ESC_BURST;
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} else
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csr |= D_ESC_BURST;
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break;
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default:
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break;
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}
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L64854_SCSR(sc, csr);
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if (sc->sc_rev == DMAREV_HME) {
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bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR, 0);
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sc->sc_dmactl = csr;
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}
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sc->sc_active = 0;
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DPRINTF(LDB_ANY, ("lsi64854_reset: done, csr 0x%x\n", csr));
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}
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static void
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lsi64854_map_scsi(void *arg, bus_dma_segment_t *segs, int nseg, int error)
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{
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struct lsi64854_softc *sc;
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sc = (struct lsi64854_softc *)arg;
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if (nseg != 1)
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panic("%s: cannot map %d segments\n", sc->dv_name, nseg);
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bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap, sc->sc_datain ?
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BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
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bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR,
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segs[0].ds_addr);
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}
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#define DMAMAX(a) (MAX_DMA_SZ - ((a) & (MAX_DMA_SZ-1)))
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/*
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* setup a DMA transfer
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*/
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int
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lsi64854_setup(struct lsi64854_softc *sc, caddr_t *addr, size_t *len,
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int datain, size_t *dmasize)
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{
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uint32_t csr;
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DMA_FLUSH(sc, 0);
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#if 0
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DMACSR(sc) &= ~D_INT_EN;
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#endif
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sc->sc_dmaaddr = addr;
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sc->sc_dmalen = len;
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sc->sc_datain = datain;
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/*
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* The rules say we cannot transfer more than the limit
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* of this DMA chip (64k for old and 16Mb for new),
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* and we cannot cross a 16Mb boundary.
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*/
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*dmasize = sc->sc_dmasize =
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min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr));
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DPRINTF(LDB_ANY, ("dma_setup: dmasize = %ld\n", (long)sc->sc_dmasize));
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/*
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* XXX what length?
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*/
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if (sc->sc_rev == DMAREV_HME) {
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L64854_SCSR(sc, sc->sc_dmactl | L64854_RESET);
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L64854_SCSR(sc, sc->sc_dmactl);
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bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_CNT, *dmasize);
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}
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/* Program the DMA address */
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if (sc->sc_dmasize) {
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if (bus_dmamap_load(sc->sc_buffer_dmat, sc->sc_dmamap,
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*sc->sc_dmaaddr, sc->sc_dmasize,
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lsi64854_map_scsi, sc, 0) != 0)
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panic("%s: cannot allocate DVMA address", sc->dv_name);
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}
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if (sc->sc_rev == DMAREV_ESC) {
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/* DMA ESC chip bug work-around */
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long bcnt = sc->sc_dmasize;
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long eaddr = bcnt + (long)*sc->sc_dmaaddr;
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if ((eaddr & PAGE_MASK_8K) != 0)
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bcnt = roundup(bcnt, PAGE_SIZE_8K);
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bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_CNT,
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bcnt);
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}
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/* Setup DMA control register */
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csr = L64854_GCSR(sc);
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if (datain)
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csr |= L64854_WRITE;
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else
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csr &= ~L64854_WRITE;
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csr |= L64854_INT_EN;
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if (sc->sc_rev == DMAREV_HME) {
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csr |= (D_DSBL_SCSI_DRN | D_EN_DMA);
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}
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L64854_SCSR(sc, csr);
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return (0);
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}
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/*
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* Pseudo (chained) interrupt from the esp driver to kick the
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* current running DMA transfer. Called from ncr53c9x_intr()
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* for now.
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*
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* return 1 if it was a DMA continue.
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*/
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int
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lsi64854_scsi_intr(void *arg)
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{
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struct lsi64854_softc *sc = arg;
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struct ncr53c9x_softc *nsc = sc->sc_client;
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int trans, resid;
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uint32_t csr;
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|
||||
csr = L64854_GCSR(sc);
|
||||
|
||||
DPRINTF(LDB_SCSI, ("%s: dmaintr: addr 0x%x, csr %b\n", sc->dv_name,
|
||||
bus_space_read_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR),
|
||||
csr, DDMACSR_BITS));
|
||||
|
||||
if (csr & (D_ERR_PEND|D_SLAVE_ERR)) {
|
||||
printf("%s: error: csr=%b\n", sc->dv_name, csr, DDMACSR_BITS);
|
||||
csr &= ~D_EN_DMA; /* Stop DMA */
|
||||
/* Invalidate the queue; SLAVE_ERR bit is write-to-clear */
|
||||
csr |= D_INVALIDATE|D_SLAVE_ERR;
|
||||
L64854_SCSR(sc, csr);
|
||||
return (-1);
|
||||
}
|
||||
|
||||
/* This is an "assertion" :) */
|
||||
if (sc->sc_active == 0)
|
||||
panic("dmaintr: DMA wasn't active");
|
||||
|
||||
DMA_DRAIN(sc, 0);
|
||||
|
||||
/* DMA has stopped */
|
||||
csr &= ~D_EN_DMA;
|
||||
L64854_SCSR(sc, csr);
|
||||
sc->sc_active = 0;
|
||||
|
||||
if (sc->sc_dmasize == 0) {
|
||||
/* A "Transfer Pad" operation completed */
|
||||
DPRINTF(LDB_SCSI, ("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n",
|
||||
NCR_READ_REG(nsc, NCR_TCL) |
|
||||
(NCR_READ_REG(nsc, NCR_TCM) << 8),
|
||||
NCR_READ_REG(nsc, NCR_TCL),
|
||||
NCR_READ_REG(nsc, NCR_TCM)));
|
||||
return 0;
|
||||
}
|
||||
|
||||
resid = 0;
|
||||
/*
|
||||
* If a transfer onto the SCSI bus gets interrupted by the device
|
||||
* (e.g. for a SAVEPOINTER message), the data in the FIFO counts
|
||||
* as residual since the NCR53C9X counter registers get decremented
|
||||
* as bytes are clocked into the FIFO.
|
||||
*/
|
||||
if (!(csr & D_WRITE) &&
|
||||
(resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) {
|
||||
DPRINTF(LDB_SCSI, ("dmaintr: empty esp FIFO of %d ", resid));
|
||||
if (nsc->sc_rev == NCR_VARIANT_FAS366 &&
|
||||
(NCR_READ_REG(nsc, NCR_CFG3) & NCRFASCFG3_EWIDE))
|
||||
resid <<= 1;
|
||||
}
|
||||
|
||||
if ((nsc->sc_espstat & NCRSTAT_TC) == 0) {
|
||||
/*
|
||||
* `Terminal count' is off, so read the residue
|
||||
* out of the NCR53C9X counter registers.
|
||||
*/
|
||||
resid += (NCR_READ_REG(nsc, NCR_TCL) |
|
||||
(NCR_READ_REG(nsc, NCR_TCM) << 8) |
|
||||
((nsc->sc_cfg2 & NCRCFG2_FE)
|
||||
? (NCR_READ_REG(nsc, NCR_TCH) << 16)
|
||||
: 0));
|
||||
|
||||
if (resid == 0 && sc->sc_dmasize == 65536 &&
|
||||
(nsc->sc_cfg2 & NCRCFG2_FE) == 0)
|
||||
/* A transfer of 64K is encoded as `TCL=TCM=0' */
|
||||
resid = 65536;
|
||||
}
|
||||
|
||||
trans = sc->sc_dmasize - resid;
|
||||
if (trans < 0) { /* transferred < 0 ? */
|
||||
#if 0
|
||||
/*
|
||||
* This situation can happen in perfectly normal operation
|
||||
* if the ESP is reselected while using DMA to select
|
||||
* another target. As such, don't print the warning.
|
||||
*/
|
||||
printf("%s: xfer (%d) > req (%d)\n", sc->dv_name, trans,
|
||||
sc->sc_dmasize);
|
||||
#endif
|
||||
trans = sc->sc_dmasize;
|
||||
}
|
||||
|
||||
DPRINTF(LDB_SCSI, ("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n",
|
||||
NCR_READ_REG(nsc, NCR_TCL),
|
||||
NCR_READ_REG(nsc, NCR_TCM),
|
||||
(nsc->sc_cfg2 & NCRCFG2_FE)
|
||||
? NCR_READ_REG(nsc, NCR_TCH) : 0,
|
||||
trans, resid));
|
||||
|
||||
#if 0 /* XXX */
|
||||
if (sc->sc_dmamap->dm_nsegs > 0) {
|
||||
bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap,
|
||||
(csr & D_WRITE) != 0
|
||||
? BUS_DMASYNC_POSTREAD
|
||||
: BUS_DMASYNC_POSTWRITE);
|
||||
bus_dmamap_unload(sc->sc_buffer_dmat, sc->sc_dmamap);
|
||||
}
|
||||
#endif
|
||||
|
||||
*sc->sc_dmalen -= trans;
|
||||
*sc->sc_dmaaddr += trans;
|
||||
|
||||
#if 0 /* this is not normal operation just yet */
|
||||
if (*sc->sc_dmalen == 0 ||
|
||||
nsc->sc_phase != nsc->sc_prevphase)
|
||||
return 0;
|
||||
|
||||
/* and again */
|
||||
dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE);
|
||||
return 1;
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Pseudo (chained) interrupt to le driver to handle DMA errors.
|
||||
*/
|
||||
int
|
||||
lsi64854_enet_intr(void *arg)
|
||||
{
|
||||
struct lsi64854_softc *sc = arg;
|
||||
uint32_t csr;
|
||||
static int dodrain = 0;
|
||||
int rv;
|
||||
|
||||
csr = L64854_GCSR(sc);
|
||||
|
||||
/* If the DMA logic shows an interrupt, claim it */
|
||||
rv = ((csr & E_INT_PEND) != 0) ? 1 : 0;
|
||||
|
||||
if (csr & (E_ERR_PEND|E_SLAVE_ERR)) {
|
||||
printf("%s: error: csr=%b\n", sc->dv_name, csr, EDMACSR_BITS);
|
||||
csr &= ~L64854_EN_DMA; /* Stop DMA */
|
||||
/* Invalidate the queue; SLAVE_ERR bit is write-to-clear */
|
||||
csr |= E_INVALIDATE|E_SLAVE_ERR;
|
||||
L64854_SCSR(sc, csr);
|
||||
DMA_RESET(sc);
|
||||
dodrain = 1;
|
||||
return (1);
|
||||
}
|
||||
|
||||
if (dodrain) { /* XXX - is this necessary with D_DSBL_WRINVAL on? */
|
||||
int i = 10;
|
||||
csr |= E_DRAIN;
|
||||
L64854_SCSR(sc, csr);
|
||||
while (i-- > 0 && (L64854_GCSR(sc) & D_DRAINING))
|
||||
DELAY(1);
|
||||
}
|
||||
|
||||
return (rv | (*sc->sc_intrchain)(sc->sc_intrchainarg));
|
||||
}
|
||||
|
||||
static void
|
||||
lsi64854_map_pp(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
|
||||
{
|
||||
struct lsi64854_softc *sc;
|
||||
|
||||
sc = (struct lsi64854_softc *)arg;
|
||||
|
||||
if (nsegs != 1)
|
||||
panic("%s: cannot map %d segments\n", sc->dv_name, nsegs);
|
||||
|
||||
bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap, sc->sc_datain
|
||||
? BUS_DMASYNC_PREREAD
|
||||
: BUS_DMASYNC_PREWRITE);
|
||||
bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR,
|
||||
segs[0].ds_addr);
|
||||
|
||||
bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_CNT,
|
||||
sc->sc_dmasize);
|
||||
}
|
||||
|
||||
/*
|
||||
* setup a DMA transfer
|
||||
*/
|
||||
int
|
||||
lsi64854_setup_pp(struct lsi64854_softc *sc, caddr_t *addr, size_t *len,
|
||||
int datain, size_t *dmasize)
|
||||
{
|
||||
uint32_t csr;
|
||||
|
||||
DMA_FLUSH(sc, 0);
|
||||
|
||||
sc->sc_dmaaddr = addr;
|
||||
sc->sc_dmalen = len;
|
||||
sc->sc_datain = datain;
|
||||
|
||||
DPRINTF(LDB_PP, ("%s: pp start %ld@%p,%d\n", sc->dv_name,
|
||||
(long)*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0));
|
||||
|
||||
/*
|
||||
* the rules say we cannot transfer more than the limit
|
||||
* of this DMA chip (64k for old and 16Mb for new),
|
||||
* and we cannot cross a 16Mb boundary.
|
||||
*/
|
||||
*dmasize = sc->sc_dmasize =
|
||||
min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr));
|
||||
|
||||
DPRINTF(LDB_PP, ("dma_setup_pp: dmasize = %ld\n", (long)sc->sc_dmasize));
|
||||
|
||||
/* Program the DMA address */
|
||||
if (sc->sc_dmasize) {
|
||||
if (bus_dmamap_load(sc->sc_buffer_dmat, sc->sc_dmamap,
|
||||
*sc->sc_dmaaddr, sc->sc_dmasize,
|
||||
lsi64854_map_pp, sc, 0) != 0)
|
||||
panic("%s: pp cannot allocate DVMA address",
|
||||
sc->dv_name);
|
||||
}
|
||||
|
||||
/* Setup DMA control register */
|
||||
csr = L64854_GCSR(sc);
|
||||
csr &= ~L64854_BURST_SIZE;
|
||||
if (sc->sc_burst == 32) {
|
||||
csr |= L64854_BURST_32;
|
||||
} else if (sc->sc_burst == 16) {
|
||||
csr |= L64854_BURST_16;
|
||||
} else {
|
||||
csr |= L64854_BURST_0;
|
||||
}
|
||||
csr |= P_EN_DMA|P_INT_EN|P_EN_CNT;
|
||||
#if 0
|
||||
/* This bit is read-only in PP csr register */
|
||||
if (datain)
|
||||
csr |= P_WRITE;
|
||||
else
|
||||
csr &= ~P_WRITE;
|
||||
#endif
|
||||
L64854_SCSR(sc, csr);
|
||||
|
||||
return (0);
|
||||
}
|
||||
/*
|
||||
* Parallel port DMA interrupt.
|
||||
*/
|
||||
int
|
||||
lsi64854_pp_intr(void *arg)
|
||||
{
|
||||
struct lsi64854_softc *sc = arg;
|
||||
int ret, trans, resid = 0;
|
||||
uint32_t csr;
|
||||
|
||||
csr = L64854_GCSR(sc);
|
||||
|
||||
DPRINTF(LDB_PP, ("%s: pp intr: addr 0x%x, csr %b\n", sc->dv_name,
|
||||
bus_space_read_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR),
|
||||
csr, PDMACSR_BITS));
|
||||
|
||||
if (csr & (P_ERR_PEND|P_SLAVE_ERR)) {
|
||||
resid = bus_space_read_4(sc->sc_regt, sc->sc_regh,
|
||||
L64854_REG_CNT);
|
||||
printf("%s: pp error: resid %d csr=%b\n", sc->dv_name, resid,
|
||||
csr, PDMACSR_BITS);
|
||||
csr &= ~P_EN_DMA; /* Stop DMA */
|
||||
/* Invalidate the queue; SLAVE_ERR bit is write-to-clear */
|
||||
csr |= P_INVALIDATE|P_SLAVE_ERR;
|
||||
L64854_SCSR(sc, csr);
|
||||
return (1);
|
||||
}
|
||||
|
||||
ret = (csr & P_INT_PEND) != 0;
|
||||
|
||||
if (sc->sc_active != 0) {
|
||||
DMA_DRAIN(sc, 0);
|
||||
resid = bus_space_read_4(sc->sc_regt, sc->sc_regh,
|
||||
L64854_REG_CNT);
|
||||
}
|
||||
|
||||
/* DMA has stopped */
|
||||
csr &= ~D_EN_DMA;
|
||||
L64854_SCSR(sc, csr);
|
||||
sc->sc_active = 0;
|
||||
|
||||
trans = sc->sc_dmasize - resid;
|
||||
if (trans < 0) { /* transferred < 0 ? */
|
||||
trans = sc->sc_dmasize;
|
||||
}
|
||||
*sc->sc_dmalen -= trans;
|
||||
*sc->sc_dmaaddr += trans;
|
||||
|
||||
#if 0 /* XXX */
|
||||
if (sc->sc_dmamap->dm_nsegs > 0) {
|
||||
bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap,
|
||||
(csr & D_WRITE) != 0
|
||||
? BUS_DMASYNC_POSTREAD
|
||||
: BUS_DMASYNC_POSTWRITE);
|
||||
bus_dmamap_unload(sc->sc_buffer_dmat, sc->sc_dmamap);
|
||||
}
|
||||
#endif
|
||||
|
||||
return (ret != 0);
|
||||
}
|
||||
@ -1,205 +0,0 @@
|
||||
/* $NetBSD: lsi64854reg.h,v 1.4 1998/09/21 21:26:52 pk Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1998 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
|
||||
* by Paul Kranenburg.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by the NetBSD
|
||||
* Foundation, Inc. and its contributors.
|
||||
* 4. Neither the name of The NetBSD Foundation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/* $FreeBSD$ */
|
||||
|
||||
/*
|
||||
* LSI 64854 DMA engine. Contains three independent channels
|
||||
* designed to interface with (a) a NCR539X SCSI controller,
|
||||
* (b) a AM7990 Ethernet controller, (c) Parallel port hardware..
|
||||
*/
|
||||
|
||||
/*
|
||||
* Register offsets to bus handle.
|
||||
*/
|
||||
#define L64854_REG_CSR 0 /* Control bits */
|
||||
#define L64854_REG_ADDR 4 /* DMA Address */
|
||||
#define L64854_REG_CNT 8 /* DMA count */
|
||||
#define L64854_REG_CNT_MASK 0x00ffffff /* only 24 bits */
|
||||
#define L64854_REG_ENBAR 12 /* ENET Base register */
|
||||
#define L64854_REG_TEST 12 /* SCSI Test register */
|
||||
#define L64854_REG_HCR 16 /* PP Hardware Configuration */
|
||||
#define L64854_REG_OCR 18 /* PP Operation Configuration */
|
||||
#define L64854_REG_DR 20 /* PP Data register */
|
||||
#define L64854_REG_TCR 21 /* PP Transfer Control */
|
||||
#define L64854_REG_OR 22 /* PP Output register */
|
||||
#define L64854_REG_IR 23 /* PP Input register */
|
||||
#define L64854_REG_ICR 24 /* PP Interrupt Control */
|
||||
|
||||
|
||||
/*
|
||||
* Control bits common to all three channels.
|
||||
*/
|
||||
#define L64854_INT_PEND 0x00000001 /* Interrupt pending */
|
||||
#define L64854_ERR_PEND 0x00000002 /* Error pending */
|
||||
#define L64854_DRAINING 0x0000000c /* FIFO draining */
|
||||
#define L64854_INT_EN 0x00000010 /* Interrupt enable */
|
||||
#define L64854_INVALIDATE 0x00000020 /* Invalidate FIFO */
|
||||
#define L64854_SLAVE_ERR 0x00000040 /* Slave access size error */
|
||||
#define L64854_RESET 0x00000080 /* Reset device */
|
||||
#define L64854_WRITE 0x00000100 /* 1: xfer to memory */
|
||||
#define L64854_EN_DMA 0x00000200 /* enable DMA transfers */
|
||||
|
||||
#define L64854_BURST_SIZE 0x000c0000 /* Read/write burst size */
|
||||
#define L64854_BURST_0 0x00080000 /* no bursts (SCSI-only) */
|
||||
#define L64854_BURST_16 0x00000000 /* 16-byte bursts */
|
||||
#define L64854_BURST_32 0x00040000 /* 32-byte bursts */
|
||||
#define L64854_BURST_64 0x000c0000 /* 64-byte bursts (fas) */
|
||||
|
||||
#define L64854_RST_FAS366 0x08000000 /* FAS366 hardware reset */
|
||||
|
||||
#define L64854_DEVID 0xf0000000 /* device ID bits */
|
||||
|
||||
/*
|
||||
* SCSI DMA control bits.
|
||||
*/
|
||||
#define D_INT_PEND L64854_INT_PEND /* interrupt pending */
|
||||
#define D_ERR_PEND L64854_ERR_PEND /* error pending */
|
||||
#define D_DRAINING L64854_DRAINING /* fifo draining */
|
||||
#define D_INT_EN L64854_INT_EN /* interrupt enable */
|
||||
#define D_INVALIDATE L64854_INVALIDATE/* invalidate fifo */
|
||||
#define D_SLAVE_ERR L64854_SLAVE_ERR/* slave access size error */
|
||||
#define D_RESET L64854_RESET /* reset scsi */
|
||||
#define D_WRITE L64854_WRITE /* 1 = dev -> mem */
|
||||
#define D_EN_DMA L64854_EN_DMA /* enable DMA requests */
|
||||
#define D_EN_CNT 0x00002000 /* enable byte counter */
|
||||
#define D_TC 0x00004000 /* terminal count */
|
||||
#define D_WIDE_EN 0x00008000 /* enable wide mode SBUS DMA (fas) */
|
||||
#define D_DSBL_CSR_DRN 0x00010000 /* disable fifo drain on csr */
|
||||
#define D_DSBL_SCSI_DRN 0x00020000 /* disable fifo drain on reg */
|
||||
|
||||
#define D_DIAG 0x00100000 /* disable fifo drain on addr */
|
||||
#define D_TWO_CYCLE 0x00200000 /* 2 clocks per transfer */
|
||||
#define D_FASTER 0x00400000 /* 3 clocks per transfer */
|
||||
#define D_TCI_DIS 0x00800000 /* disable intr on D_TC */
|
||||
#define D_EN_NEXT 0x01000000 /* enable auto next address */
|
||||
#define D_DMA_ON 0x02000000 /* enable dma from scsi XXX */
|
||||
#define D_DSBL_PARITY_CHK \
|
||||
0x02000000 /* disable checking for parity on bus (default 1:fas) */
|
||||
#define D_A_LOADED 0x04000000 /* address loaded */
|
||||
#define D_NA_LOADED 0x08000000 /* next address loaded */
|
||||
#define D_HW_RESET_FAS366 \
|
||||
0x08000000 /* hardware reset FAS366 (fas) */
|
||||
#define D_DEV_ID L64854_DEVID /* device ID */
|
||||
#define DMAREV_0 0x00000000 /* Sunray DMA */
|
||||
#define DMAREV_ESC 0x40000000 /* DMA ESC array */
|
||||
#define DMAREV_1 0x80000000 /* 'DMA' */
|
||||
#define DMAREV_PLUS 0x90000000 /* 'DMA+' */
|
||||
#define DMAREV_2 0xa0000000 /* 'DMA2' */
|
||||
#define DMAREV_HME 0xb0000000 /* 'HME' */
|
||||
|
||||
/*
|
||||
* revisions 0,1 and ESC have different bits.
|
||||
*/
|
||||
#define D_ESC_DRAIN 0x00000040 /* rev0,1,esc: drain fifo */
|
||||
#define D_ESC_R_PEND 0x00000400 /* rev0,1: request pending */
|
||||
#define D_ESC_BURST 0x00000800 /* DMA ESC: 16 byte bursts */
|
||||
#define D_ESC_AUTODRAIN 0x00040000 /* DMA ESC: Auto-drain */
|
||||
|
||||
#define DDMACSR_BITS "\177\020" \
|
||||
"b\00INT\0b\01ERR\0f\02\02DRAINING\0b\04IEN\0" \
|
||||
"b\06SLVERR\0b\07RST\0b\10WRITE\0b\11ENDMA\0" \
|
||||
"b\15ENCNT\0b\16TC\0\b\20DSBL_CSR_DRN\0" \
|
||||
"b\21DSBL_SCSI_DRN\0f\22\2BURST\0b\25TWOCYCLE\0" \
|
||||
"b\26FASTER\0b\27TCIDIS\0b\30ENNXT\0b\031DMAON\0" \
|
||||
"b\32ALOADED\0b\33NALOADED\0"
|
||||
|
||||
|
||||
/*
|
||||
* ENET DMA control bits.
|
||||
*/
|
||||
#define E_INT_PEND L64854_INT_PEND /* interrupt pending */
|
||||
#define E_ERR_PEND L64854_ERR_PEND /* error pending */
|
||||
#define E_DRAINING L64854_DRAINING /* fifo draining */
|
||||
#define E_INT_EN L64854_INT_EN /* interrupt enable */
|
||||
#define E_INVALIDATE L64854_INVALIDATE/* invalidate fifo */
|
||||
#define E_SLAVE_ERR L64854_SLAVE_ERR/* slave access size error */
|
||||
#define E_RESET L64854_RESET /* reset ENET */
|
||||
#define E_reserved1 0x00000300 /* */
|
||||
#define E_DRAIN 0x00000400 /* force Ecache drain */
|
||||
#define E_DSBL_WR_DRN 0x00000800 /* disable Ecache drain on .. */
|
||||
#define E_DSBL_RD_DRN 0x00001000 /* disable Ecache drain on .. */
|
||||
#define E_reserved2 0x00006000 /* */
|
||||
#define E_ILACC 0x00008000 /* ... */
|
||||
#define E_DSBL_BUF_WR 0x00010000 /* no buffering of slave writes */
|
||||
#define E_DSBL_WR_INVAL 0x00020000 /* no Ecache invalidate on slave writes */
|
||||
|
||||
#define E_reserved3 0x00100000 /* */
|
||||
#define E_LOOP_TEST 0x00200000 /* loopback mode */
|
||||
#define E_TP_AUI 0x00400000 /* 1 for TP, 0 for AUI */
|
||||
#define E_reserved4 0x0c800000 /* */
|
||||
#define E_DEV_ID L64854_DEVID /* ID bits */
|
||||
|
||||
#define EDMACSR_BITS "\177\020" \
|
||||
"b\00INT\0b\01ERR\0f\02\02DRAINING\0b\04IEN\0" \
|
||||
"b\06SLVERR\0b\07RST\0b\10WRITE\0b\12DRAIN\0" \
|
||||
"b\13DSBL_WR_DRN\0b\14DSBL_RD_DRN\0b\17ILACC\0" \
|
||||
"b\20DSBL_BUF_WR\0b\21DSBL_WR_INVAL\0" \
|
||||
"b\25LOOPTEST\0b\26TP\0"
|
||||
|
||||
/*
|
||||
* PP DMA control bits.
|
||||
*/
|
||||
#define P_INT_PEND L64854_INT_PEND /* interrupt pending */
|
||||
#define P_ERR_PEND L64854_ERR_PEND /* error pending */
|
||||
#define P_DRAINING L64854_DRAINING /* fifo draining */
|
||||
#define P_INT_EN L64854_INT_EN /* interrupt enable */
|
||||
#define P_INVALIDATE L64854_INVALIDATE/* invalidate fifo */
|
||||
#define P_SLAVE_ERR L64854_SLAVE_ERR/* slave access size error */
|
||||
#define P_RESET L64854_RESET /* reset PP */
|
||||
#define P_WRITE L64854_WRITE /* 1: xfer to memory */
|
||||
#define P_EN_DMA L64854_EN_DMA /* enable DMA transfers */
|
||||
#define P_reserved1 0x00001c00 /* */
|
||||
#define P_EN_CNT 0x00002000 /* enable counter */
|
||||
#define P_TC 0x00004000 /* terminal count */
|
||||
#define P_reserved2 0x00038000 /* */
|
||||
|
||||
#define P_DIAG 0x00100000 /* ... */
|
||||
#define P_reserved3 0x00600000 /* */
|
||||
#define P_TCI_DIS 0x00800000 /* no interrupt on terminal count */
|
||||
#define P_EN_NEXT 0x01000000 /* enable DMA chaining */
|
||||
#define P_DMA_ON 0x02000000 /* DMA xfers enabled */
|
||||
#define P_A_LOADED 0x04000000 /* addr and byte count valid */
|
||||
#define P_NA_LOADED 0x08000000 /* next addr & count valid but not used */
|
||||
#define P_DEV_ID L64854_DEVID /* ID bits */
|
||||
|
||||
#define PDMACSR_BITS "\177\020" \
|
||||
"b\00INT\0b\01ERR\0f\02\02DRAINING\0b\04IEN\0" \
|
||||
"b\06SLVERR\0b\07RST\0b\10WRITE\0b\11ENDMA\0" \
|
||||
"b\15ENCNT\0b\16TC\0\b\24DIAG\0b\27TCIDIS\0" \
|
||||
"b\30ENNXT\0b\031DMAON\0b\32ALOADED\0b\33NALOADED\0"
|
||||
@ -1,114 +0,0 @@
|
||||
/* $NetBSD: lsi64854var.h,v 1.4 2001/03/29 02:58:39 petrov Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1998 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
|
||||
* by Paul Kranenburg.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by the NetBSD
|
||||
* Foundation, Inc. and its contributors.
|
||||
* 4. Neither the name of The NetBSD Foundation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/* $FreeBSD$ */
|
||||
|
||||
struct lsi64854_softc {
|
||||
device_t sc_dev;
|
||||
const char *dv_name;
|
||||
|
||||
int sc_rid;
|
||||
struct resource *sc_res;
|
||||
bus_space_handle_t sc_regh;
|
||||
bus_space_tag_t sc_regt;
|
||||
u_int sc_rev; /* revision */
|
||||
int sc_burst; /* max suported burst size */
|
||||
|
||||
int sc_channel;
|
||||
#define L64854_CHANNEL_SCSI 1
|
||||
#define L64854_CHANNEL_ENET 2
|
||||
#define L64854_CHANNEL_PP 3
|
||||
void *sc_client;
|
||||
|
||||
int sc_active; /* DMA active ? */
|
||||
bus_dmamap_t sc_dmamap; /* DMA map for bus_dma_* */
|
||||
|
||||
bus_dma_tag_t sc_parent_dmat;
|
||||
bus_dma_tag_t sc_buffer_dmat;
|
||||
int sc_datain;
|
||||
size_t sc_dmasize;
|
||||
caddr_t *sc_dmaaddr;
|
||||
size_t *sc_dmalen;
|
||||
|
||||
void (*reset)(struct lsi64854_softc *);/* reset routine */
|
||||
int (*setup)(struct lsi64854_softc *, caddr_t *, size_t *,
|
||||
int, size_t *); /* DMA setup */
|
||||
int (*intr)(void *); /* interrupt handler */
|
||||
|
||||
int (*sc_intrchain)(void *); /* next handler in intr chain */
|
||||
void *sc_intrchainarg; /* arg for next intr handler */
|
||||
|
||||
u_int sc_dmactl;
|
||||
};
|
||||
|
||||
#define L64854_GCSR(sc) \
|
||||
(bus_space_read_4((sc)->sc_regt, (sc)->sc_regh, L64854_REG_CSR))
|
||||
|
||||
#define L64854_SCSR(sc, csr) \
|
||||
bus_space_write_4((sc)->sc_regt, (sc)->sc_regh, L64854_REG_CSR, csr)
|
||||
|
||||
|
||||
/*
|
||||
* DMA engine interface functions.
|
||||
*/
|
||||
#define DMA_RESET(sc) (((sc)->reset)(sc))
|
||||
#define DMA_INTR(sc) (((sc)->intr)(sc))
|
||||
#define DMA_SETUP(sc, a, l, d, s) (((sc)->setup)(sc, a, l, d, s))
|
||||
|
||||
#define DMA_ISACTIVE(sc) ((sc)->sc_active)
|
||||
|
||||
#define DMA_ENINTR(sc) do { \
|
||||
uint32_t csr = L64854_GCSR(sc); \
|
||||
csr |= L64854_INT_EN; \
|
||||
L64854_SCSR(sc, csr); \
|
||||
} while (0)
|
||||
|
||||
#define DMA_ISINTR(sc) (L64854_GCSR(sc) & (D_INT_PEND|D_ERR_PEND))
|
||||
|
||||
#define DMA_GO(sc) do { \
|
||||
uint32_t csr = L64854_GCSR(sc); \
|
||||
csr |= D_EN_DMA; \
|
||||
L64854_SCSR(sc, csr); \
|
||||
sc->sc_active = 1; \
|
||||
} while (0)
|
||||
|
||||
|
||||
void lsi64854_attach(struct lsi64854_softc *);
|
||||
int lsi64854_scsi_intr(void *);
|
||||
int lsi64854_enet_intr(void *);
|
||||
int lsi64854_pp_intr(void *);
|
||||
Loading…
Reference in New Issue
Block a user