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Turn on the 0WS option for 16bit cards. Newer machines insert enough

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delay that without this the performance is unacceptable. The 83C690,
83C790, and 83C795 chips which this affects are all designed to work
with 0 waitstates in 16bit mode.
Also cleaned up the toggling of 16bit access mode that occurs during
normal operation; the previous code may not have done the right thing
in all cases.
This commit is contained in:
dg 1997-09-08 10:27:09 +00:00
parent 12e4ae6425
commit 4fcbd35c01
2 changed files with 54 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

45
sys/dev/ed/if_ed.c
View File

@ -24,7 +24,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: if_ed.c,v 1.117 1997/07/20 14:09:57 bde Exp $
* $Id: if_ed.c,v 1.118 1997/09/02 01:18:07 bde Exp $
*/
/*
@ -717,25 +717,35 @@ ed_probe_WD80x3(isa_dev)
sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + ED_WD_PROM + i);
/*
* Set upper address bits and 8/16 bit access to shared memory
* Set upper address bits, 8/16 bit access to shared memory, and
* zero waitstate operation for 16 bit cards.
*/
if (isa16bit) {
if (sc->is790) {
sc->wd_laar_proto = inb(sc->asic_addr + ED_WD_LAAR);
outb(sc->asic_addr + ED_WD_LAAR, ED_WD_LAAR_M16EN);
/*
* Enable zero waitstate operation
*/
outb(sc->asic_addr + ED_WD790_GCR, inb(sc->asic_addr +
ED_WD790_GCR) | ED_WD790_GCR_ZWSEN);
} else {
outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto =
ED_WD_LAAR_L16EN | ED_WD_LAAR_M16EN |
((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI)));
sc->wd_laar_proto = ED_WD_LAAR_L16EN | ED_WD_LAAR_0WS16 |
((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI);
}
/*
* Enable 16bit access
*/
outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto |
ED_WD_LAAR_M16EN);
} else {
if (((sc->type & ED_WD_SOFTCONFIG) ||
#ifdef TOSH_ETHER
(sc->type == ED_TYPE_TOSHIBA1) || (sc->type == ED_TYPE_TOSHIBA4) ||
#endif
(sc->type == ED_TYPE_WD8013EBT)) && (!sc->is790)) {
outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto =
((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI)));
sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) &
ED_WD_LAAR_ADDRHI;
outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto);
}
}
@ -788,8 +798,8 @@ ed_probe_WD80x3(isa_dev)
if (sc->is790) {
outb(sc->asic_addr + ED_WD_MSR, 0x00);
}
outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &=
~ED_WD_LAAR_M16EN));
outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto &
~ED_WD_LAAR_M16EN);
}
return (0);
}
@ -807,8 +817,8 @@ ed_probe_WD80x3(isa_dev)
if (sc->is790) {
outb(sc->asic_addr + ED_WD_MSR, 0x00);
}
outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &=
~ED_WD_LAAR_M16EN));
outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto &
~ED_WD_LAAR_M16EN);
}
return (ED_WD_IO_PORTS);
}
@ -2144,7 +2154,7 @@ outloop:
*/
case ED_VENDOR_WD_SMC:{
outb(sc->asic_addr + ED_WD_LAAR,
(sc->wd_laar_proto | ED_WD_LAAR_M16EN));
sc->wd_laar_proto | ED_WD_LAAR_M16EN);
if (sc->is790) {
outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB);
}
@ -2171,7 +2181,8 @@ outloop:
if (sc->is790) {
outb(sc->asic_addr + ED_WD_MSR, 0x00);
}
outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto);
outb(sc->asic_addr + ED_WD_LAAR,
sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
break;
}
}
@ -2534,8 +2545,7 @@ edintr_sc(sc)
(sc->vendor == ED_VENDOR_WD_SMC)) {
outb(sc->asic_addr + ED_WD_LAAR,
(sc->wd_laar_proto |=
ED_WD_LAAR_M16EN));
sc->wd_laar_proto | ED_WD_LAAR_M16EN);
if (sc->is790) {
outb(sc->asic_addr + ED_WD_MSR,
ED_WD_MSR_MENB);
@ -2551,8 +2561,7 @@ edintr_sc(sc)
outb(sc->asic_addr + ED_WD_MSR, 0x00);
}
outb(sc->asic_addr + ED_WD_LAAR,
(sc->wd_laar_proto &=
~ED_WD_LAAR_M16EN));
sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
}
}
}

45
sys/i386/isa/if_ed.c
View File

@ -24,7 +24,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: if_ed.c,v 1.117 1997/07/20 14:09:57 bde Exp $
* $Id: if_ed.c,v 1.118 1997/09/02 01:18:07 bde Exp $
*/
/*
@ -717,25 +717,35 @@ ed_probe_WD80x3(isa_dev)
sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + ED_WD_PROM + i);
/*
* Set upper address bits and 8/16 bit access to shared memory
* Set upper address bits, 8/16 bit access to shared memory, and
* zero waitstate operation for 16 bit cards.
*/
if (isa16bit) {
if (sc->is790) {
sc->wd_laar_proto = inb(sc->asic_addr + ED_WD_LAAR);
outb(sc->asic_addr + ED_WD_LAAR, ED_WD_LAAR_M16EN);
/*
* Enable zero waitstate operation
*/
outb(sc->asic_addr + ED_WD790_GCR, inb(sc->asic_addr +
ED_WD790_GCR) | ED_WD790_GCR_ZWSEN);
} else {
outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto =
ED_WD_LAAR_L16EN | ED_WD_LAAR_M16EN |
((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI)));
sc->wd_laar_proto = ED_WD_LAAR_L16EN | ED_WD_LAAR_0WS16 |
((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI);
}
/*
* Enable 16bit access
*/
outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto |
ED_WD_LAAR_M16EN);
} else {
if (((sc->type & ED_WD_SOFTCONFIG) ||
#ifdef TOSH_ETHER
(sc->type == ED_TYPE_TOSHIBA1) || (sc->type == ED_TYPE_TOSHIBA4) ||
#endif
(sc->type == ED_TYPE_WD8013EBT)) && (!sc->is790)) {
outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto =
((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI)));
sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) &
ED_WD_LAAR_ADDRHI;
outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto);
}
}
@ -788,8 +798,8 @@ ed_probe_WD80x3(isa_dev)
if (sc->is790) {
outb(sc->asic_addr + ED_WD_MSR, 0x00);
}
outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &=
~ED_WD_LAAR_M16EN));
outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto &
~ED_WD_LAAR_M16EN);
}
return (0);
}
@ -807,8 +817,8 @@ ed_probe_WD80x3(isa_dev)
if (sc->is790) {
outb(sc->asic_addr + ED_WD_MSR, 0x00);
}
outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &=
~ED_WD_LAAR_M16EN));
outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto &
~ED_WD_LAAR_M16EN);
}
return (ED_WD_IO_PORTS);
}
@ -2144,7 +2154,7 @@ outloop:
*/
case ED_VENDOR_WD_SMC:{
outb(sc->asic_addr + ED_WD_LAAR,
(sc->wd_laar_proto | ED_WD_LAAR_M16EN));
sc->wd_laar_proto | ED_WD_LAAR_M16EN);
if (sc->is790) {
outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB);
}
@ -2171,7 +2181,8 @@ outloop:
if (sc->is790) {
outb(sc->asic_addr + ED_WD_MSR, 0x00);
}
outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto);
outb(sc->asic_addr + ED_WD_LAAR,
sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
break;
}
}
@ -2534,8 +2545,7 @@ edintr_sc(sc)
(sc->vendor == ED_VENDOR_WD_SMC)) {
outb(sc->asic_addr + ED_WD_LAAR,
(sc->wd_laar_proto |=
ED_WD_LAAR_M16EN));
sc->wd_laar_proto | ED_WD_LAAR_M16EN);
if (sc->is790) {
outb(sc->asic_addr + ED_WD_MSR,
ED_WD_MSR_MENB);
@ -2551,8 +2561,7 @@ edintr_sc(sc)
outb(sc->asic_addr + ED_WD_MSR, 0x00);
}
outb(sc->asic_addr + ED_WD_LAAR,
(sc->wd_laar_proto &=
~ED_WD_LAAR_M16EN));
sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
}
}
}