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MFC r208149,208285:

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Add support for the U4 PCI-Express bridge chipset used in late-generation
Powermac G5 systems. MSI and several other things are not presently
supported.

The U3/U4 internal device support portions of this change were contributed
by Andreas Tobler.
This commit is contained in:
Nathan Whitehorn 2010-05-23 02:15:31 +00:00
parent 940ae4543b
commit 502a50e4eb
8 changed files with 1077 additions and 993 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
sys/conf/files.powerpc
View File

@ -140,7 +140,8 @@ powerpc/powermac/openpic_macio.c optional powermac pci
powerpc/powermac/pswitch.c optional powermac pswitch
powerpc/powermac/pmu.c optional powermac pmu
powerpc/powermac/smu.c optional powermac smu
powerpc/powermac/uninorth.c optional powermac pci
powerpc/powermac/uninorth.c optional powermac
powerpc/powermac/uninorthpci.c optional powermac pci
powerpc/powermac/vcoregpio.c optional powermac
powerpc/powerpc/altivec.c optional aim
powerpc/powerpc/atomic.S standard

6
sys/dev/pci/pci.c
View File

@ -53,7 +53,7 @@ __FBSDID("$FreeBSD$");
#include <machine/resource.h>
#include <machine/stdarg.h>
#if defined(__i386__) || defined(__amd64__)
#if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
#include <machine/intr_machdep.h>
#endif
@ -529,7 +529,7 @@ pci_read_extcap(device_t pcib, pcicfgregs *cfg)
{
#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
#define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
#if defined(__i386__) || defined(__amd64__)
#if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
uint64_t addr;
#endif
uint32_t val;
@ -573,7 +573,7 @@ pci_read_extcap(device_t pcib, pcicfgregs *cfg)
cfg->pp.pp_data = ptr + PCIR_POWER_DATA;
}
break;
#if defined(__i386__) || defined(__amd64__)
#if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
case PCIY_HT: /* HyperTransport */
/* Determine HT-specific capability type. */
val = REG(ptr + PCIR_HT_COMMAND, 2);

5
sys/powerpc/include/intr_machdep.h
View File

@ -30,6 +30,11 @@
#define INTR_VECTORS 256
/*
* Default base address for MSI messages on PowerPC
*/
#define MSI_INTEL_ADDR_BASE 0xfee00000
extern device_t pic;
extern device_t pic8259;

883
sys/powerpc/powermac/cpcht.c
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File diff suppressed because it is too large Load Diff

58
sys/powerpc/powermac/cpchtvar.h
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@ -1,58 +0,0 @@
/*-
* Copyright (C) 2008 Nathan Whitehorn
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _POWERPC_POWERMAC_CPCHTVAR_H_
#define _POWERPC_POWERMAC_CPCHTVAR_H_
struct cpcpci_range {
u_int32_t pci_hi;
u_int32_t pci_mid;
u_int32_t pci_lo;
u_int32_t junk;
u_int32_t host_hi;
u_int32_t host_lo;
u_int32_t size_hi;
u_int32_t size_lo;
};
struct cpcpci_softc {
device_t sc_dev;
phandle_t sc_node;
vm_offset_t sc_data;
int sc_bus;
struct cpcpci_range sc_range[6];
int sc_nrange;
int sc_iostart;
struct rman sc_io_rman;
struct rman sc_mem_rman;
bus_space_tag_t sc_iot;
bus_space_tag_t sc_memt;
bus_dma_tag_t sc_dmat;
struct ofw_bus_iinfo sc_pci_iinfo;
};
#endif /* _POWERPC_POWERMAC_CPCHTVAR_H_ */

1068
sys/powerpc/powermac/uninorth.c
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File diff suppressed because it is too large Load Diff

37
sys/powerpc/powermac/uninorthvar.h
View File

@ -63,16 +63,36 @@ struct uninorth_softc {
bus_dma_tag_t sc_dmat;
struct ofw_bus_iinfo sc_pci_iinfo;
int sc_u3;
int sc_ver;
};
struct unin_chip_softc {
vm_offset_t sc_physaddr;
u_int32_t sc_physaddr;
vm_offset_t sc_addr;
u_int sc_size;
u_int32_t sc_size;
struct rman sc_mem_rman;
int sc_version;
};
/*
* Format of a unin reg property entry.
*/
struct unin_chip_reg {
u_int32_t mr_base;
u_int32_t mr_size;
};
/*
* Per unin device structure.
*/
struct unin_chip_devinfo {
int udi_interrupts[6];
int udi_ninterrupts;
int udi_base;
struct ofw_bus_devinfo udi_obdinfo;
struct resource_list udi_resources;
};
/*
* Version register
*/
@ -81,7 +101,14 @@ struct unin_chip_softc {
/*
* Clock-control register
*/
#define UNIN_CLOCKCNTL 0x20
#define UNIN_CLOCKCNTL_GMAC 0x2
#define UNIN_CLOCKCNTL 0x20
#define UNIN_CLOCKCNTL_GMAC 0x2
/*
* Toggle registers
*/
#define UNIN_TOGGLE_REG 0xe0
#define UNIN_MPIC_RESET 0x2
#define UNIN_MPIC_OUTPUT_ENABLE 0x4
#endif /* _POWERPC_POWERMAC_UNINORTHVAR_H_ */

10
sys/powerpc/powerpc/openpic.c
View File

@ -100,6 +100,16 @@ openpic_attach(device_t dev)
sc->sc_bt = rman_get_bustag(sc->sc_memr);
sc->sc_bh = rman_get_bushandle(sc->sc_memr);
/* Reset the PIC */
x = openpic_read(sc, OPENPIC_CONFIG);
x |= OPENPIC_CONFIG_RESET;
openpic_write(sc, OPENPIC_CONFIG, x);
while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) {
powerpc_sync();
DELAY(100);
}
x = openpic_read(sc, OPENPIC_FEATURE);
switch (x & OPENPIC_FEATURE_VERSION_MASK) {
case 1: