Change the definition of the debugging registers to be an array, so
that we can index into it, rather than do pointer gymnastics on a structure containing 8 elements. Verified by: MD5 hash on the produced .o files.
This commit is contained in:
Poul-Henning Kamp
parent
858b84f550
commit
50c026e579
@ -487,7 +487,7 @@ i386_set_watch(watchnum, watchaddr, size, access, d)
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if (watchnum == -1) {
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for (i = 0, mask = 0x3; i < 4; i++, mask <<= 2)
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if ((d->dr7 & mask) == 0)
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if ((d->dr[7] & mask) == 0)
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break;
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if (i < 4)
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watchnum = i;
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@ -518,13 +518,13 @@ i386_set_watch(watchnum, watchaddr, size, access, d)
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mask |= access;
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/* clear the bits we are about to affect */
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d->dr7 &= ~((0x3 << (watchnum*2)) | (0x0f << (watchnum*4+16)));
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d->dr[7] &= ~((0x3 << (watchnum*2)) | (0x0f << (watchnum*4+16)));
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/* set drN register to the address, N=watchnum */
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DBREG_DRX(d,watchnum) = watchaddr;
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/* enable the watchpoint */
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d->dr7 |= (0x2 << (watchnum*2)) | (mask << (watchnum*4+16));
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d->dr[7] |= (0x2 << (watchnum*2)) | (mask << (watchnum*4+16));
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return (watchnum);
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}
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@ -539,7 +539,7 @@ i386_clr_watch(watchnum, d)
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if (watchnum < 0 || watchnum >= 4)
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return (-1);
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d->dr7 = d->dr7 & ~((0x3 << (watchnum*2)) | (0x0f << (watchnum*4+16)));
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d->dr[7] = d->dr[7] & ~((0x3 << (watchnum*2)) | (0x0f << (watchnum*4+16)));
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DBREG_DRX(d,watchnum) = 0;
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return (0);
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@ -559,7 +559,7 @@ db_md_set_watchpoint(addr, size)
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avail = 0;
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for(i=0; i<4; i++) {
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if ((d.dr7 & (3 << (i*2))) == 0)
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if ((d.dr[7] & (3 << (i*2))) == 0)
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avail++;
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}
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@ -567,7 +567,7 @@ db_md_set_watchpoint(addr, size)
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return (-1);
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for (i=0; i<4 && (size != 0); i++) {
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if ((d.dr7 & (3<<(i*2))) == 0) {
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if ((d.dr[7] & (3<<(i*2))) == 0) {
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if (size > 4)
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wsize = 4;
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else
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@ -598,7 +598,7 @@ db_md_clr_watchpoint(addr, size)
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fill_dbregs(NULL, &d);
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for(i=0; i<4; i++) {
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if (d.dr7 & (3 << (i*2))) {
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if (d.dr[7] & (3 << (i*2))) {
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if ((DBREG_DRX((&d), i) >= addr) &&
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(DBREG_DRX((&d), i) < addr+size))
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i386_clr_watch(i, &d);
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@ -638,10 +638,10 @@ db_md_list_watchpoints()
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db_printf(" watch status type len address\n");
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db_printf(" ----- -------- ---------- --- ----------\n");
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for (i=0; i<4; i++) {
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if (d.dr7 & (0x03 << (i*2))) {
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if (d.dr[7] & (0x03 << (i*2))) {
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unsigned type, len;
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type = (d.dr7 >> (16+(i*4))) & 3;
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len = (d.dr7 >> (16+(i*4)+2)) & 3;
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type = (d.dr[7] >> (16+(i*4))) & 3;
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len = (d.dr[7] >> (16+(i*4)+2)) & 3;
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db_printf(" %-5d %-8s %10s %3d 0x%08x\n",
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i, "enabled", watchtype_str(type),
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len+1, DBREG_DRX((&d),i));
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@ -2267,24 +2267,24 @@ fill_dbregs(struct thread *td, struct dbreg *dbregs)
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struct pcb *pcb;
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if (td == NULL) {
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dbregs->dr0 = rdr0();
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dbregs->dr1 = rdr1();
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dbregs->dr2 = rdr2();
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dbregs->dr3 = rdr3();
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dbregs->dr4 = rdr4();
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dbregs->dr5 = rdr5();
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dbregs->dr6 = rdr6();
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dbregs->dr7 = rdr7();
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dbregs->dr[0] = rdr0();
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dbregs->dr[1] = rdr1();
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dbregs->dr[2] = rdr2();
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dbregs->dr[3] = rdr3();
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dbregs->dr[4] = rdr4();
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dbregs->dr[5] = rdr5();
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dbregs->dr[6] = rdr6();
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dbregs->dr[7] = rdr7();
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} else {
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pcb = td->td_pcb;
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dbregs->dr0 = pcb->pcb_dr0;
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dbregs->dr1 = pcb->pcb_dr1;
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dbregs->dr2 = pcb->pcb_dr2;
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dbregs->dr3 = pcb->pcb_dr3;
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dbregs->dr4 = 0;
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dbregs->dr5 = 0;
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dbregs->dr6 = pcb->pcb_dr6;
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dbregs->dr7 = pcb->pcb_dr7;
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dbregs->dr[0] = pcb->pcb_dr0;
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dbregs->dr[1] = pcb->pcb_dr1;
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dbregs->dr[2] = pcb->pcb_dr2;
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dbregs->dr[3] = pcb->pcb_dr3;
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dbregs->dr[4] = 0;
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dbregs->dr[5] = 0;
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dbregs->dr[6] = pcb->pcb_dr6;
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dbregs->dr[7] = pcb->pcb_dr7;
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}
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return (0);
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}
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@ -2297,14 +2297,14 @@ set_dbregs(struct thread *td, struct dbreg *dbregs)
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u_int32_t mask1, mask2;
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if (td == NULL) {
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load_dr0(dbregs->dr0);
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load_dr1(dbregs->dr1);
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load_dr2(dbregs->dr2);
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load_dr3(dbregs->dr3);
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load_dr4(dbregs->dr4);
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load_dr5(dbregs->dr5);
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load_dr6(dbregs->dr6);
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load_dr7(dbregs->dr7);
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load_dr0(dbregs->dr[0]);
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load_dr1(dbregs->dr[1]);
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load_dr2(dbregs->dr[2]);
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load_dr3(dbregs->dr[3]);
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load_dr4(dbregs->dr[4]);
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load_dr5(dbregs->dr[5]);
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load_dr6(dbregs->dr[6]);
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load_dr7(dbregs->dr[7]);
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} else {
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/*
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* Don't let an illegal value for dr7 get set. Specifically,
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@ -2314,7 +2314,7 @@ set_dbregs(struct thread *td, struct dbreg *dbregs)
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*/
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for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 8;
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i++, mask1 <<= 2, mask2 <<= 2)
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if ((dbregs->dr7 & mask1) == mask2)
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if ((dbregs->dr[7] & mask1) == mask2)
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return (EINVAL);
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pcb = td->td_pcb;
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@ -2335,37 +2335,37 @@ set_dbregs(struct thread *td, struct dbreg *dbregs)
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*/
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if (suser(td) != 0) {
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if (dbregs->dr7 & 0x3) {
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if (dbregs->dr[7] & 0x3) {
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/* dr0 is enabled */
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if (dbregs->dr0 >= VM_MAXUSER_ADDRESS)
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if (dbregs->dr[0] >= VM_MAXUSER_ADDRESS)
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return (EINVAL);
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}
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if (dbregs->dr7 & (0x3<<2)) {
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if (dbregs->dr[7] & (0x3<<2)) {
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/* dr1 is enabled */
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if (dbregs->dr1 >= VM_MAXUSER_ADDRESS)
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if (dbregs->dr[1] >= VM_MAXUSER_ADDRESS)
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return (EINVAL);
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}
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if (dbregs->dr7 & (0x3<<4)) {
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if (dbregs->dr[7] & (0x3<<4)) {
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/* dr2 is enabled */
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if (dbregs->dr2 >= VM_MAXUSER_ADDRESS)
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if (dbregs->dr[2] >= VM_MAXUSER_ADDRESS)
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return (EINVAL);
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}
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if (dbregs->dr7 & (0x3<<6)) {
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if (dbregs->dr[7] & (0x3<<6)) {
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/* dr3 is enabled */
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if (dbregs->dr3 >= VM_MAXUSER_ADDRESS)
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if (dbregs->dr[3] >= VM_MAXUSER_ADDRESS)
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return (EINVAL);
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}
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}
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pcb->pcb_dr0 = dbregs->dr0;
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pcb->pcb_dr1 = dbregs->dr1;
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pcb->pcb_dr2 = dbregs->dr2;
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pcb->pcb_dr3 = dbregs->dr3;
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pcb->pcb_dr6 = dbregs->dr6;
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pcb->pcb_dr7 = dbregs->dr7;
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pcb->pcb_dr0 = dbregs->dr[0];
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pcb->pcb_dr1 = dbregs->dr[1];
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pcb->pcb_dr2 = dbregs->dr[2];
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pcb->pcb_dr3 = dbregs->dr[3];
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pcb->pcb_dr6 = dbregs->dr[6];
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pcb->pcb_dr7 = dbregs->dr[7];
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pcb->pcb_flags |= PCB_DBREGS;
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}
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@ -122,20 +122,17 @@ struct fpreg {
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* Register set accessible via /proc/$pid/dbregs.
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*/
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struct dbreg {
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unsigned int dr0; /* debug address register 0 */
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unsigned int dr1; /* debug address register 1 */
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unsigned int dr2; /* debug address register 2 */
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unsigned int dr3; /* debug address register 3 */
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unsigned int dr4; /* reserved */
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unsigned int dr5; /* reserved */
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unsigned int dr6; /* debug status register */
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unsigned int dr7; /* debug control register */
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unsigned int dr[8]; /* debug registers */
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/* Index 0-3: debug address registers */
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/* Index 4-5: reserved */
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/* Index 6: debug status */
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/* Index 7: debug control */
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};
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#define DBREG_DR7_EXEC 0x00 /* break on execute */
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#define DBREG_DR7_WRONLY 0x01 /* break on write */
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#define DBREG_DR7_RDWR 0x03 /* break on read or write */
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#define DBREG_DRX(d,x) ((&d->dr0)[x]) /* reference dr0 - dr7 by
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#define DBREG_DRX(d,x) (d->dr[(x)]) /* reference dr0 - dr7 by
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register number */
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@ -487,7 +487,7 @@ i386_set_watch(watchnum, watchaddr, size, access, d)
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if (watchnum == -1) {
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for (i = 0, mask = 0x3; i < 4; i++, mask <<= 2)
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if ((d->dr7 & mask) == 0)
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if ((d->dr[7] & mask) == 0)
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break;
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if (i < 4)
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watchnum = i;
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@ -518,13 +518,13 @@ i386_set_watch(watchnum, watchaddr, size, access, d)
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mask |= access;
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/* clear the bits we are about to affect */
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d->dr7 &= ~((0x3 << (watchnum*2)) | (0x0f << (watchnum*4+16)));
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d->dr[7] &= ~((0x3 << (watchnum*2)) | (0x0f << (watchnum*4+16)));
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/* set drN register to the address, N=watchnum */
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DBREG_DRX(d,watchnum) = watchaddr;
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/* enable the watchpoint */
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d->dr7 |= (0x2 << (watchnum*2)) | (mask << (watchnum*4+16));
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d->dr[7] |= (0x2 << (watchnum*2)) | (mask << (watchnum*4+16));
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return (watchnum);
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}
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@ -539,7 +539,7 @@ i386_clr_watch(watchnum, d)
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if (watchnum < 0 || watchnum >= 4)
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return (-1);
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d->dr7 = d->dr7 & ~((0x3 << (watchnum*2)) | (0x0f << (watchnum*4+16)));
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d->dr[7] = d->dr[7] & ~((0x3 << (watchnum*2)) | (0x0f << (watchnum*4+16)));
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DBREG_DRX(d,watchnum) = 0;
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return (0);
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@ -559,7 +559,7 @@ db_md_set_watchpoint(addr, size)
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avail = 0;
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for(i=0; i<4; i++) {
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if ((d.dr7 & (3 << (i*2))) == 0)
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if ((d.dr[7] & (3 << (i*2))) == 0)
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avail++;
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}
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@ -567,7 +567,7 @@ db_md_set_watchpoint(addr, size)
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return (-1);
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for (i=0; i<4 && (size != 0); i++) {
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if ((d.dr7 & (3<<(i*2))) == 0) {
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if ((d.dr[7] & (3<<(i*2))) == 0) {
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if (size > 4)
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wsize = 4;
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else
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@ -598,7 +598,7 @@ db_md_clr_watchpoint(addr, size)
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fill_dbregs(NULL, &d);
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for(i=0; i<4; i++) {
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if (d.dr7 & (3 << (i*2))) {
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if (d.dr[7] & (3 << (i*2))) {
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if ((DBREG_DRX((&d), i) >= addr) &&
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(DBREG_DRX((&d), i) < addr+size))
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i386_clr_watch(i, &d);
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@ -638,10 +638,10 @@ db_md_list_watchpoints()
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db_printf(" watch status type len address\n");
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db_printf(" ----- -------- ---------- --- ----------\n");
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for (i=0; i<4; i++) {
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if (d.dr7 & (0x03 << (i*2))) {
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if (d.dr[7] & (0x03 << (i*2))) {
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unsigned type, len;
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type = (d.dr7 >> (16+(i*4))) & 3;
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len = (d.dr7 >> (16+(i*4)+2)) & 3;
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type = (d.dr[7] >> (16+(i*4))) & 3;
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len = (d.dr[7] >> (16+(i*4)+2)) & 3;
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db_printf(" %-5d %-8s %10s %3d 0x%08x\n",
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i, "enabled", watchtype_str(type),
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len+1, DBREG_DRX((&d),i));
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@ -2267,24 +2267,24 @@ fill_dbregs(struct thread *td, struct dbreg *dbregs)
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struct pcb *pcb;
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if (td == NULL) {
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dbregs->dr0 = rdr0();
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dbregs->dr1 = rdr1();
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dbregs->dr2 = rdr2();
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dbregs->dr3 = rdr3();
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dbregs->dr4 = rdr4();
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dbregs->dr5 = rdr5();
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dbregs->dr6 = rdr6();
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dbregs->dr7 = rdr7();
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dbregs->dr[0] = rdr0();
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dbregs->dr[1] = rdr1();
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dbregs->dr[2] = rdr2();
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dbregs->dr[3] = rdr3();
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dbregs->dr[4] = rdr4();
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dbregs->dr[5] = rdr5();
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dbregs->dr[6] = rdr6();
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dbregs->dr[7] = rdr7();
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} else {
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pcb = td->td_pcb;
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dbregs->dr0 = pcb->pcb_dr0;
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dbregs->dr1 = pcb->pcb_dr1;
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dbregs->dr2 = pcb->pcb_dr2;
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dbregs->dr3 = pcb->pcb_dr3;
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dbregs->dr4 = 0;
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dbregs->dr5 = 0;
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dbregs->dr6 = pcb->pcb_dr6;
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dbregs->dr7 = pcb->pcb_dr7;
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dbregs->dr[0] = pcb->pcb_dr0;
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dbregs->dr[1] = pcb->pcb_dr1;
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dbregs->dr[2] = pcb->pcb_dr2;
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dbregs->dr[3] = pcb->pcb_dr3;
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dbregs->dr[4] = 0;
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dbregs->dr[5] = 0;
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dbregs->dr[6] = pcb->pcb_dr6;
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dbregs->dr[7] = pcb->pcb_dr7;
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}
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return (0);
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}
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@ -2297,14 +2297,14 @@ set_dbregs(struct thread *td, struct dbreg *dbregs)
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u_int32_t mask1, mask2;
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if (td == NULL) {
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load_dr0(dbregs->dr0);
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load_dr1(dbregs->dr1);
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load_dr2(dbregs->dr2);
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load_dr3(dbregs->dr3);
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load_dr4(dbregs->dr4);
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load_dr5(dbregs->dr5);
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load_dr6(dbregs->dr6);
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load_dr7(dbregs->dr7);
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load_dr0(dbregs->dr[0]);
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load_dr1(dbregs->dr[1]);
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load_dr2(dbregs->dr[2]);
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load_dr3(dbregs->dr[3]);
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load_dr4(dbregs->dr[4]);
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load_dr5(dbregs->dr[5]);
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load_dr6(dbregs->dr[6]);
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load_dr7(dbregs->dr[7]);
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} else {
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/*
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* Don't let an illegal value for dr7 get set. Specifically,
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@ -2314,7 +2314,7 @@ set_dbregs(struct thread *td, struct dbreg *dbregs)
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*/
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for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 8;
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i++, mask1 <<= 2, mask2 <<= 2)
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if ((dbregs->dr7 & mask1) == mask2)
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if ((dbregs->dr[7] & mask1) == mask2)
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return (EINVAL);
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pcb = td->td_pcb;
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@ -2335,37 +2335,37 @@ set_dbregs(struct thread *td, struct dbreg *dbregs)
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*/
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if (suser(td) != 0) {
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if (dbregs->dr7 & 0x3) {
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if (dbregs->dr[7] & 0x3) {
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/* dr0 is enabled */
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if (dbregs->dr0 >= VM_MAXUSER_ADDRESS)
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if (dbregs->dr[0] >= VM_MAXUSER_ADDRESS)
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return (EINVAL);
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}
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if (dbregs->dr7 & (0x3<<2)) {
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if (dbregs->dr[7] & (0x3<<2)) {
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||||
/* dr1 is enabled */
|
||||
if (dbregs->dr1 >= VM_MAXUSER_ADDRESS)
|
||||
if (dbregs->dr[1] >= VM_MAXUSER_ADDRESS)
|
||||
return (EINVAL);
|
||||
}
|
||||
|
||||
if (dbregs->dr7 & (0x3<<4)) {
|
||||
if (dbregs->dr[7] & (0x3<<4)) {
|
||||
/* dr2 is enabled */
|
||||
if (dbregs->dr2 >= VM_MAXUSER_ADDRESS)
|
||||
if (dbregs->dr[2] >= VM_MAXUSER_ADDRESS)
|
||||
return (EINVAL);
|
||||
}
|
||||
|
||||
if (dbregs->dr7 & (0x3<<6)) {
|
||||
if (dbregs->dr[7] & (0x3<<6)) {
|
||||
/* dr3 is enabled */
|
||||
if (dbregs->dr3 >= VM_MAXUSER_ADDRESS)
|
||||
if (dbregs->dr[3] >= VM_MAXUSER_ADDRESS)
|
||||
return (EINVAL);
|
||||
}
|
||||
}
|
||||
|
||||
pcb->pcb_dr0 = dbregs->dr0;
|
||||
pcb->pcb_dr1 = dbregs->dr1;
|
||||
pcb->pcb_dr2 = dbregs->dr2;
|
||||
pcb->pcb_dr3 = dbregs->dr3;
|
||||
pcb->pcb_dr6 = dbregs->dr6;
|
||||
pcb->pcb_dr7 = dbregs->dr7;
|
||||
pcb->pcb_dr0 = dbregs->dr[0];
|
||||
pcb->pcb_dr1 = dbregs->dr[1];
|
||||
pcb->pcb_dr2 = dbregs->dr[2];
|
||||
pcb->pcb_dr3 = dbregs->dr[3];
|
||||
pcb->pcb_dr6 = dbregs->dr[6];
|
||||
pcb->pcb_dr7 = dbregs->dr[7];
|
||||
|
||||
pcb->pcb_flags |= PCB_DBREGS;
|
||||
}
|
||||
|
||||
@ -122,20 +122,17 @@ struct fpreg {
|
||||
* Register set accessible via /proc/$pid/dbregs.
|
||||
*/
|
||||
struct dbreg {
|
||||
unsigned int dr0; /* debug address register 0 */
|
||||
unsigned int dr1; /* debug address register 1 */
|
||||
unsigned int dr2; /* debug address register 2 */
|
||||
unsigned int dr3; /* debug address register 3 */
|
||||
unsigned int dr4; /* reserved */
|
||||
unsigned int dr5; /* reserved */
|
||||
unsigned int dr6; /* debug status register */
|
||||
unsigned int dr7; /* debug control register */
|
||||
unsigned int dr[8]; /* debug registers */
|
||||
/* Index 0-3: debug address registers */
|
||||
/* Index 4-5: reserved */
|
||||
/* Index 6: debug status */
|
||||
/* Index 7: debug control */
|
||||
};
|
||||
|
||||
#define DBREG_DR7_EXEC 0x00 /* break on execute */
|
||||
#define DBREG_DR7_WRONLY 0x01 /* break on write */
|
||||
#define DBREG_DR7_RDWR 0x03 /* break on read or write */
|
||||
#define DBREG_DRX(d,x) ((&d->dr0)[x]) /* reference dr0 - dr7 by
|
||||
#define DBREG_DRX(d,x) (d->dr[(x)]) /* reference dr0 - dr7 by
|
||||
register number */
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user