Add the SPE feature mask for e500v1 and e500v2
On e500v2 SoCs it will now print: cpu0: Features 84e08000<PPC32,MMU,SPE,EFPS,EFPD,BOOKE> at bootup.
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@ -56,6 +56,9 @@ extern int cpu_features2;
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#define PPC_FEATURE_HAS_FPU 0x08000000
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#define PPC_FEATURE_HAS_MMU 0x04000000
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#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
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#define PPC_FEATURE_HAS_SPE 0x00800000
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#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
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#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
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#define PPC_FEATURE_BOOKE 0x00008000
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#define PPC_FEATURE_SMT 0x00004000
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#define PPC_FEATURE_ARCH_2_05 0x00001000
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@ -70,7 +73,8 @@ extern int cpu_features2;
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#define PPC_FEATURE_BITMASK \
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"\20" \
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"\040PPC32\037PPC64\035ALTIVEC\034FPU\033MMU\031UNIFIEDCACHE" \
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"\020BOOKE\017SMT\015ARCH205\013DFP\011ARCH206\010VSX"
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"\030SPE\027SPESFP\026DPESFP\020BOOKE\017SMT\015ARCH205\013DFP" \
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"\011ARCH206\010VSX"
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#define PPC_FEATURE2_BITMASK \
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"\20" \
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"\040ARCH207\037HTM\032VCRYPTO"
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@ -180,9 +180,12 @@ static const struct cputab models[] = {
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{ "Motorola PowerPC 8245", MPC8245, REVFMT_MAJMIN,
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PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
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{ "Freescale e500v1 core", FSL_E500v1, REVFMT_MAJMIN,
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PPC_FEATURE_BOOKE, 0, cpu_booke_setup },
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PPC_FEATURE_BOOKE | PPC_FEATURE_HAS_SPE | PPC_FEATURE_HAS_EFP_SINGLE,
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0, cpu_booke_setup },
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{ "Freescale e500v2 core", FSL_E500v2, REVFMT_MAJMIN,
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PPC_FEATURE_BOOKE, 0, cpu_booke_setup },
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PPC_FEATURE_BOOKE | PPC_FEATURE_HAS_SPE |
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PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_HAS_EFP_DOUBLE, 0,
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cpu_booke_setup },
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{ "Freescale e500mc core", FSL_E500mc, REVFMT_MAJMIN,
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PPC_FEATURE_BOOKE | PPC_FEATURE_HAS_FPU, 0, cpu_booke_setup },
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{ "Freescale e5500 core", FSL_E5500, REVFMT_MAJMIN,
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