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Use aperture base address from north bridge. Some BIOS does not encode

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misc. control registers correctly and it is inconsistent with north bridge.
In fact, there are too many broken BIOS implementations out there and we
cannot fix every possible combination but at least it is consistent with
what we advertise with ioctl(2).
This commit is contained in:
jkim 2006-08-21 19:10:58 +00:00
parent 527f3d6e4f
commit 51974d427a
2 changed files with 10 additions and 20 deletions
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15
sys/dev/agp/agp_amd64.c
View File

@ -182,14 +182,9 @@ agp_amd64_attach(device_t dev)
sc->n_mctrl = n;
if (bootverbose) {
if (bootverbose)
device_printf(dev, "%d Miscellaneous Control unit(s) found.\n",
sc->n_mctrl);
for (i = 0; i < sc->n_mctrl; i++)
device_printf(dev, "Aperture Base[%d]: 0x%08x\n", i,
pci_cfgregread(0, sc->mctrl[i], 3,
AGP_AMD64_APBASE, 4) & AGP_AMD64_APBASE_MASK);
}
if ((error = agp_generic_attach(dev)))
return error;
@ -380,11 +375,11 @@ agp_amd64_apbase_fixup(device_t dev)
uint32_t apbase;
int i;
apbase = pci_cfgregread(0, sc->mctrl[0], 3, AGP_AMD64_APBASE, 4);
sc->apbase = rman_get_start(sc->agp.as_aperture);
apbase = (sc->apbase >> 25) & AGP_AMD64_APBASE_MASK;
for (i = 0; i < sc->n_mctrl; i++)
pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APBASE,
apbase & ~(AGP_AMD64_APBASE_MASK & ~(uint32_t)0x7f), 4);
sc->apbase = apbase << 25;
pci_cfgregwrite(0, sc->mctrl[i], 3,
AGP_AMD64_APBASE, apbase, 4);
}
static void

15
sys/pci/agp_amd64.c
View File

@ -182,14 +182,9 @@ agp_amd64_attach(device_t dev)
sc->n_mctrl = n;
if (bootverbose) {
if (bootverbose)
device_printf(dev, "%d Miscellaneous Control unit(s) found.\n",
sc->n_mctrl);
for (i = 0; i < sc->n_mctrl; i++)
device_printf(dev, "Aperture Base[%d]: 0x%08x\n", i,
pci_cfgregread(0, sc->mctrl[i], 3,
AGP_AMD64_APBASE, 4) & AGP_AMD64_APBASE_MASK);
}
if ((error = agp_generic_attach(dev)))
return error;
@ -380,11 +375,11 @@ agp_amd64_apbase_fixup(device_t dev)
uint32_t apbase;
int i;
apbase = pci_cfgregread(0, sc->mctrl[0], 3, AGP_AMD64_APBASE, 4);
sc->apbase = rman_get_start(sc->agp.as_aperture);
apbase = (sc->apbase >> 25) & AGP_AMD64_APBASE_MASK;
for (i = 0; i < sc->n_mctrl; i++)
pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APBASE,
apbase & ~(AGP_AMD64_APBASE_MASK & ~(uint32_t)0x7f), 4);
sc->apbase = apbase << 25;
pci_cfgregwrite(0, sc->mctrl[i], 3,
AGP_AMD64_APBASE, apbase, 4);
}
static void