1) When mucking with mapping registers, it is best to *not* have
io or memory space access enabled. This patch defers the setting of these bits until after all of the mapping registers are probed. It might be even better to defer this until a particular mapping is activated and to disable that type of access when a new register is activated. 2) The PCI spec is very explicit about how mapping registers and the expansion ROM mapping register should be probed. This patch makes cardbus_add_map() follow the spec. 3) The PCI spec allows a device to use the same address decoder for expansion ROM access as is used for memory mapped register access. This patch carefully enables and disables ROM access along with resource (de)activiation. This doesn't include the prefetching detection stuff (maybe later when code is written to actually turn on prefetching). It also does not use the PCI definitions (yet, I'll try to put this in all at once later) Submitted by: Justin T. Gibbs
This commit is contained in:
jon
parent
49bd2bf060
commit
51f405ec6e
@ -112,8 +112,8 @@ static int cardbus_set_resource_method(device_t dev, device_t child, int type,
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int rid, u_long start, u_long count);
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static int cardbus_get_resource_method(device_t dev, device_t child, int type,
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int rid, u_long *startp, u_long *countp);
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static void cardbus_add_map(device_t bdev, device_t dev,
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pcicfgregs *cfg, int reg);
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static int cardbus_add_map(device_t bdev, device_t dev, pcicfgregs *cfg,
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int reg);
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static void cardbus_add_resources(device_t dev, pcicfgregs* cfg);
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static void cardbus_release_all_resources(device_t dev,
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struct resource_list *rl);
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@ -167,15 +167,10 @@ cardbus_detach(device_t dev)
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static void
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device_setup_regs(device_t bdev, int b, int s, int f, pcicfgregs *cfg)
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{
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PCIB_WRITE_CONFIG(bdev, b, s, f, PCIR_COMMAND,
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PCIB_READ_CONFIG(bdev, b, s, f, PCIR_COMMAND, 2) |
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PCIM_CMD_MEMEN|PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN,
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2);
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PCIB_WRITE_CONFIG(bdev, b, s, f, PCIR_INTLINE,
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pci_get_irq(device_get_parent(bdev)), 1);
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cfg->intline = PCIB_READ_CONFIG(bdev, b, s, f, PCIR_INTLINE, 1);
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PCIB_WRITE_CONFIG(bdev, b, s, f, PCIR_CACHELNSZ, 0x08, 1);
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cfg->cachelnsz = PCIB_READ_CONFIG(bdev, b, s, f, PCIR_CACHELNSZ, 1);
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@ -318,7 +313,7 @@ cardbus_read_device(device_t pcib, int b, int s, int f)
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return (NULL);
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cfg = &devlist_entry->cfg;
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cfg->bus = b;
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cfg->slot = s;
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cfg->func = f;
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@ -451,7 +446,7 @@ cardbus_readpcb(device_t pcib, int b, int s, int f)
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p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2);
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p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2);
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p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1);
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p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4);
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@ -548,7 +543,6 @@ cardbus_set_resource(device_t dev, device_t child, int type, int rid,
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struct cardbus_devinfo *dinfo = device_get_ivars(child);
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struct resource_list *rl = &dinfo->resources;
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resource_list_add(rl, type, rid, start, start + count - 1, count);
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if (rid == CARDBUS_ROM_REG) start |= 1;
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if (device_get_parent(child) == dev)
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pci_write_config(child, rid, start, 4);
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return 0;
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@ -618,24 +612,30 @@ cardbus_delete_resource_method(device_t dev, device_t child,
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BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid);
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}
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static void
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static int
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cardbus_add_map(device_t cbdev, device_t dev, pcicfgregs *cfg, int reg)
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{
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struct cardbus_devinfo *dinfo = device_get_ivars(dev);
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struct resource_list *rl = &dinfo->resources;
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struct resource_list_entry *rle;
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struct resource *res;
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device_t bdev = device_get_parent(cbdev);
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u_int32_t size;
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u_int32_t testval;
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int type;
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struct resource *res;
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if (reg == CARDBUS_ROM_REG)
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testval = CARDBUS_ROM_ADDRMASK;
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else
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testval = ~0;
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PCIB_WRITE_CONFIG(bdev, cfg->bus, cfg->slot, cfg->func,
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reg, 0xfffffff0, 4);
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reg, testval, 4);
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testval = PCIB_READ_CONFIG(bdev, cfg->bus, cfg->slot, cfg->func,
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reg, 4);
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if (testval == 0xfffffff0 || testval == 0) return;
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if (testval == ~0 || testval == 0)
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return 0;
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if ((testval&1) == 0)
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type = SYS_RES_MEMORY;
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@ -653,32 +653,53 @@ cardbus_add_map(device_t cbdev, device_t dev, pcicfgregs *cfg, int reg)
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rle->res = res;
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} else {
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device_printf(dev, "Unable to add map %02x\n", reg);
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type = 0;
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}
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return type;
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}
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static void
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cardbus_add_resources(device_t dev, pcicfgregs* cfg)
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{
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device_t cbdev = device_get_parent(dev);
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device_t bdev = device_get_parent(cbdev);
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struct cardbus_devinfo *dinfo = device_get_ivars(dev);
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struct resource_list *rl = &dinfo->resources;
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struct cardbus_quirk *q;
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struct resource_list_entry *rle;
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struct resource *res;
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int rid;
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u_int command;
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int type;
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int types;
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int i;
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types = 0;
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for (i = 0; i < cfg->nummaps; i++) {
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cardbus_add_map(cbdev, dev, cfg, PCIR_MAPS + i*4);
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type = cardbus_add_map(cbdev, dev, cfg, PCIR_MAPS + i*4);
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types |= 0x1 << type;
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}
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cardbus_add_map(cbdev, dev, cfg, CARDBUS_ROM_REG);
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type = cardbus_add_map(cbdev, dev, cfg, CARDBUS_ROM_REG);
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types |= 0x1 << type;
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for (q = &cardbus_quirks[0]; q->devid; q++) {
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if (q->devid == ((cfg->device << 16) | cfg->vendor)
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&& q->type == CARDBUS_QUIRK_MAP_REG)
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cardbus_add_map(cbdev, dev, cfg, q->arg1);
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&& q->type == CARDBUS_QUIRK_MAP_REG) {
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type = cardbus_add_map(cbdev, dev, cfg, q->arg1);
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types |= 0x1 << type;
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}
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}
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command = PCIB_READ_CONFIG(bdev, cfg->bus, cfg->slot,
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cfg->func, PCIR_COMMAND, 2);
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if ((types & (0x1 << SYS_RES_MEMORY)) != 0)
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command |= PCIM_CMD_MEMEN;
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if ((types & (0x1 << SYS_RES_IOPORT)) != 0)
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command |= PCIM_CMD_PORTEN;
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command |= PCIM_CMD_BUSMASTEREN;
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PCIB_WRITE_CONFIG(bdev, cfg->bus, cfg->slot, cfg->func,
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PCIR_COMMAND, command, 2);
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rid = 0;
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res = bus_generic_alloc_resource(cbdev, dev, SYS_RES_IRQ,
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&rid, 0, ~0, 1, RF_SHAREABLE);
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@ -719,11 +740,19 @@ cardbus_alloc_resource(device_t self, device_t child, int type,
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if (device_get_parent(child) == self || child == self)
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rle = resource_list_find(rl, type, *rid);
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if (rle) {
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if (flags & RF_ACTIVE)
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if (flags & RF_ACTIVE) {
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if (bus_activate_resource(child, type, *rid,
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rle->res)) {
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return NULL;
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}
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if (*rid == CARDBUS_ROM_REG) {
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uint32_t rom_reg;
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rom_reg = pci_read_config(child, *rid, 4);
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rom_reg |= CARDBUS_ROM_ENABLE;
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pci_write_config(child, *rid, rom_reg, 4);
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}
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}
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return rle->res; /* XXX: check if range within start/end */
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} else {
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res = bus_generic_alloc_resource(self, child, type, rid,
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@ -747,6 +776,20 @@ static int
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cardbus_release_resource(device_t dev, device_t child, int type, int rid,
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struct resource *r)
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{
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/*
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* According to the PCI 2.2 spec, devices may share an address
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* decoder between memory mapped ROM access and memory
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* mapped register access. To be safe, disable ROM access
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* whenever it is released.
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*/
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if (rid == CARDBUS_ROM_REG) {
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uint32_t rom_reg;
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rom_reg = pci_read_config(child, rid, 4);
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rom_reg &= ~CARDBUS_ROM_ENABLE;
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pci_write_config(child, rid, rom_reg, 4);
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}
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return bus_deactivate_resource(child, type, rid, r);
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}
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@ -300,7 +300,7 @@ cardbus_read_tuple_conf(device_t dev, device_t child, u_int32_t *space,
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{
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int i, j;
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u_int32_t e;
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e = pci_read_config(child, *off - *off%4, 4);
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for (j = *off%4; j>0; j--)
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e >>= 8;
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@ -361,7 +361,7 @@ cardbus_read_tuple_exrom(device_t dev, struct resource *mem, u_int32_t *space,
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*tupleid = image[0];
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*len = image[1];
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memcpy(tupledata, image+2, *len);
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*off += *len+2;
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*off += *len+2;
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return 0;
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}
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@ -434,7 +434,7 @@ cardbus_read_tuple(device_t dev, device_t child, u_int32_t *space,
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return EINVAL;
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}
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}
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static int
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decode_tuple(device_t dev, device_t child, int tupleid, int len,
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u_int8_t *tupledata, u_int32_t *space, u_int32_t *off)
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@ -460,7 +460,7 @@ cardbus_do_cis(device_t dev, device_t child)
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int len;
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int expect_linktarget;
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u_int32_t space, off;
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bzero(tupledata, MAXTUPLESIZE);
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expect_linktarget = TRUE;
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off = pci_read_config(child, CARDBUS_CIS_REG, 4);
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@ -470,7 +470,7 @@ cardbus_do_cis(device_t dev, device_t child)
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do {
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cardbus_read_tuple(dev, child, &space, &off, &tupleid, &len,
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tupledata);
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if (expect_linktarget && tupleid != CISTPL_LINKTARGET) {
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device_printf(dev, "Expecting link target, got 0x%x\n",
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tupleid);
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@ -481,6 +481,6 @@ cardbus_do_cis(device_t dev, device_t child)
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if (expect_linktarget != 0)
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return expect_linktarget;
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} while (tupleid != CISTPL_END);
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return 0;
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return 0;
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}
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@ -56,6 +56,8 @@
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# define CARDBUS_CIS_ASI_BAR5 0x06
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# define CARDBUS_CIS_ASI_ROM 0x07
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#define CARDBUS_ROM_REG 0x30
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# define CARDBUS_ROM_ENABLE 0x00000001
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# define CARDBUS_ROM_ADDRMASK 0xfffff800
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/* EXROM offsets for reading CIS */
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#define CARDBUS_EXROM_SIGNATURE 0x00
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