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======================
= Code Contributions =
======================
To make a contribution to a TianoCore project, follow these steps.
1. Create a change description in the format specified below to
use in the source control commit log.
2. Your commit message must include your "Signed-off-by" signature,
and "Contributed-under" message.
3. Your "Contributed-under" message explicitly states that the
contribution is made under the terms of the specified
contribution agreement. Your "Contributed-under" message
must include the name of contribution agreement and version.
For example: Contributed-under: TianoCore Contribution Agreement 1.0
The "TianoCore Contribution Agreement" is included below in
this document.
4. Submit your code to the TianoCore project using the process
that the project documents on its web page. If the process is
not documented, then submit the code on development email list
for the project.
5. It is preferred that contributions are submitted using the same
copyright license as the base project. When that is not possible,
then contributions using the following licenses can be accepted:
* BSD (2-clause): http://opensource.org/licenses/BSD-2-Clause
* BSD (3-clause): http://opensource.org/licenses/BSD-3-Clause
* MIT: http://opensource.org/licenses/MIT
* Python-2.0: http://opensource.org/licenses/Python-2.0
* Zlib: http://opensource.org/licenses/Zlib
Contributions of code put into the public domain can also be
accepted.
Contributions using other licenses might be accepted, but further
review will be required.
=====================================================
= Change Description / Commit Message / Patch Email =
=====================================================
Your change description should use the standard format for a
commit message, and must include your "Signed-off-by" signature
and the "Contributed-under" message.
== Sample Change Description / Commit Message =
=== Start of sample patch email message ===
From: Contributor Name <contributor@example.com>
Subject: [PATCH] CodeModule: Brief-single-line-summary
Full-commit-message
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Contributor Name <contributor@example.com>
---
An extra message for the patch email which will not be considered part
of the commit message can be added here.
Patch content inline or attached
=== End of sample patch email message ===
=== Notes for sample patch email ===
* The first line of commit message is taken from the email's subject
line following [PATCH]. The remaining portion of the commit message
is the email's content until the '---' line.
* git format-patch is one way to create this format
=== Definitions for sample patch email ===
* "CodeModule" is a short idenfier for the affected code. For
example MdePkg, or MdeModulePkg UsbBusDxe.
* "Brief-single-line-summary" is a short summary of the change.
* The entire first line should be less than ~70 characters.
* "Full-commit-message" a verbose multiple line comment describing
the change. Each line should be less than ~70 characters.
* "Contributed-under" explicitely states that the contribution is
made under the terms of the contribtion agreement. This
agreement is included below in this document.
* "Signed-off-by" is the contributor's signature identifying them
by their real/legal name and their email address.
========================================
= TianoCore Contribution Agreement 1.0 =
========================================
INTEL CORPORATION ("INTEL") MAKES AVAILABLE SOFTWARE, DOCUMENTATION,
INFORMATION AND/OR OTHER MATERIALS FOR USE IN THE TIANOCORE OPEN SOURCE
PROJECT (COLLECTIVELY "CONTENT"). USE OF THE CONTENT IS GOVERNED BY THE
TERMS AND CONDITIONS OF THIS AGREEMENT BETWEEN YOU AND INTEL AND/OR THE
TERMS AND CONDITIONS OF LICENSE AGREEMENTS OR NOTICES INDICATED OR
REFERENCED BELOW. BY USING THE CONTENT, YOU AGREE THAT YOUR USE OF THE
CONTENT IS GOVERNED BY THIS AGREEMENT AND/OR THE TERMS AND CONDITIONS
OF ANY APPLICABLE LICENSE AGREEMENTS OR NOTICES INDICATED OR REFERENCED
BELOW. IF YOU DO NOT AGREE TO THE TERMS AND CONDITIONS OF THIS
AGREEMENT AND THE TERMS AND CONDITIONS OF ANY APPLICABLE LICENSE
AGREEMENTS OR NOTICES INDICATED OR REFERENCED BELOW, THEN YOU MAY NOT
USE THE CONTENT.
Unless otherwise indicated, all Content made available on the TianoCore
site is provided to you under the terms and conditions of the BSD
License ("BSD"). A copy of the BSD License is available at
http://opensource.org/licenses/bsd-license.php
or when applicable, in the associated License.txt file.
Certain other content may be made available under other licenses as
indicated in or with such Content. (For example, in a License.txt file.)
You accept and agree to the following terms and conditions for Your
present and future Contributions submitted to TianoCore site. Except
for the license granted to Intel hereunder, You reserve all right,
title, and interest in and to Your Contributions.
== SECTION 1: Definitions ==
* "You" or "Contributor" shall mean the copyright owner or legal
entity authorized by the copyright owner that is making a
Contribution hereunder. All other entities that control, are
controlled by, or are under common control with that entity are
considered to be a single Contributor. For the purposes of this
definition, "control" means (i) the power, direct or indirect, to
cause the direction or management of such entity, whether by
contract or otherwise, or (ii) ownership of fifty percent (50%)
or more of the outstanding shares, or (iii) beneficial ownership
of such entity.
* "Contribution" shall mean any original work of authorship,
including any modifications or additions to an existing work,
that is intentionally submitted by You to the TinaoCore site for
inclusion in, or documentation of, any of the Content. For the
purposes of this definition, "submitted" means any form of
electronic, verbal, or written communication sent to the
TianoCore site or its representatives, including but not limited
to communication on electronic mailing lists, source code
control systems, and issue tracking systems that are managed by,
or on behalf of, the TianoCore site for the purpose of
discussing and improving the Content, but excluding
communication that is conspicuously marked or otherwise
designated in writing by You as "Not a Contribution."
== SECTION 2: License for Contributions ==
* Contributor hereby agrees that redistribution and use of the
Contribution in source and binary forms, with or without
modification, are permitted provided that the following
conditions are met:
** Redistributions of source code must retain the Contributor's
copyright notice, this list of conditions and the following
disclaimer.
** Redistributions in binary form must reproduce the Contributor's
copyright notice, this list of conditions and the following
disclaimer in the documentation and/or other materials provided
with the distribution.
* Disclaimer. None of the names of Contributor, Intel, or the names
of their respective contributors may be used to endorse or
promote products derived from this software without specific
prior written permission.
* Contributor grants a license (with the right to sublicense) under
claims of Contributor's patents that Contributor can license that
are infringed by the Contribution (as delivered by Contributor) to
make, use, distribute, sell, offer for sale, and import the
Contribution and derivative works thereof solely to the minimum
extent necessary for licensee to exercise the granted copyright
license; this patent license applies solely to those portions of
the Contribution that are unmodified. No hardware per se is
licensed.
* EXCEPT AS EXPRESSLY SET FORTH IN SECTION 3 BELOW, THE
CONTRIBUTION IS PROVIDED BY THE CONTRIBUTOR "AS IS" AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
CONTRIBUTOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THE
CONTRIBUTION, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
DAMAGE.
== SECTION 3: Representations ==
* You represent that You are legally entitled to grant the above
license. If your employer(s) has rights to intellectual property
that You create that includes Your Contributions, You represent
that You have received permission to make Contributions on behalf
of that employer, that Your employer has waived such rights for
Your Contributions.
* You represent that each of Your Contributions is Your original
creation (see Section 4 for submissions on behalf of others).
You represent that Your Contribution submissions include complete
details of any third-party license or other restriction
(including, but not limited to, related patents and trademarks)
of which You are personally aware and which are associated with
any part of Your Contributions.
== SECTION 4: Third Party Contributions ==
* Should You wish to submit work that is not Your original creation,
You may submit it to TianoCore site separately from any
Contribution, identifying the complete details of its source
and of any license or other restriction (including, but not
limited to, related patents, trademarks, and license agreements)
of which You are personally aware, and conspicuously marking the
work as "Submitted on behalf of a third-party: [named here]".
== SECTION 5: Miscellaneous ==
* Applicable Laws. Any claims arising under or relating to this
Agreement shall be governed by the internal substantive laws of
the State of Delaware or federal courts located in Delaware,
without regard to principles of conflict of laws.
* Language. This Agreement is in the English language only, which
language shall be controlling in all respects, and all versions
of this Agreement in any other language shall be for accommodation
only and shall not be binding. All communications and notices made
or given pursuant to this Agreement, and all documentation and
support to be provided, unless otherwise noted, shall be in the
English language.

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/** @file
Processor or Compiler specific defines and types for AArch64.
Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __PROCESSOR_BIND_H__
#define __PROCESSOR_BIND_H__
///
/// Define the processor type so other code can make processor based choices
///
#define MDE_CPU_AARCH64
//
// Make sure we are using the correct packing rules per EFI specification
//
#ifndef __GNUC__
#pragma pack()
#endif
#if _MSC_EXTENSIONS
//
// use Microsoft* C compiler dependent integer width types
//
typedef unsigned __int64 UINT64;
typedef __int64 INT64;
typedef unsigned __int32 UINT32;
typedef __int32 INT32;
typedef unsigned short UINT16;
typedef unsigned short CHAR16;
typedef short INT16;
typedef unsigned char BOOLEAN;
typedef unsigned char UINT8;
typedef char CHAR8;
typedef signed char INT8;
#else
//
// Assume standard AARCH64 alignment.
//
typedef unsigned long long UINT64;
typedef long long INT64;
typedef unsigned int UINT32;
typedef int INT32;
typedef unsigned short UINT16;
typedef unsigned short CHAR16;
typedef short INT16;
typedef unsigned char BOOLEAN;
typedef unsigned char UINT8;
typedef char CHAR8;
typedef signed char INT8;
#endif
///
/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions,
/// 8 bytes on supported 64-bit processor instructions)
///
typedef UINT64 UINTN;
///
/// Signed value of native width. (4 bytes on supported 32-bit processor instructions,
/// 8 bytes on supported 64-bit processor instructions)
///
typedef INT64 INTN;
//
// Processor specific defines
//
///
/// A value of native width with the highest bit set.
///
#define MAX_BIT 0x8000000000000000ULL
///
/// A value of native width with the two highest bits set.
///
#define MAX_2_BITS 0xC000000000000000ULL
///
/// Maximum legal AARCH64 address
///
#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL
///
/// Maximum legal AArch64 INTN and UINTN values.
///
#define MAX_INTN ((INTN)0x7FFFFFFFFFFFFFFFULL)
#define MAX_UINTN ((UINTN)0xFFFFFFFFFFFFFFFFULL)
///
/// The stack alignment required for AARCH64
///
#define CPU_STACK_ALIGNMENT 16
///
/// Page allocation granularity for AARCH64
///
#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)
#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x10000)
//
// Modifier to ensure that all protocol member functions and EFI intrinsics
// use the correct C calling convention. All protocol member functions and
// EFI intrinsics are required to modify their member functions with EFIAPI.
//
#define EFIAPI
// When compiling with Clang, we still use GNU as for the assembler, so we still
// need to define the GCC_ASM* macros.
#if defined(__GNUC__) || defined(__clang__)
///
/// For GNU assembly code, .global or .globl can declare global symbols.
/// Define this macro to unify the usage.
///
#define ASM_GLOBAL .globl
#define GCC_ASM_EXPORT(func__) \
.global _CONCATENATE (__USER_LABEL_PREFIX__, func__) ;\
.type ASM_PFX(func__), %function
#define GCC_ASM_IMPORT(func__) \
.extern _CONCATENATE (__USER_LABEL_PREFIX__, func__)
#endif
/**
Return the pointer to the first instruction of a function given a function pointer.
On ARM CPU architectures, these two pointer values are the same,
so the implementation of this macro is very simple.
@param FunctionPointer A pointer to a function.
@return The pointer to the first instruction of a function given a function pointer.
**/
#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)
#ifndef __USER_LABEL_PREFIX__
#define __USER_LABEL_PREFIX__
#endif
#endif

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/** @file
Processor or Compiler specific defines and types for ARM.
Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __PROCESSOR_BIND_H__
#define __PROCESSOR_BIND_H__
///
/// Define the processor type so other code can make processor based choices
///
#define MDE_CPU_ARM
//
// Make sure we are using the correct packing rules per EFI specification
//
#ifndef __GNUC__
#pragma pack()
#endif
//
// RVCT does not support the __builtin_unreachable() macro
//
#ifdef __ARMCC_VERSION
#define UNREACHABLE()
#endif
#if _MSC_EXTENSIONS
//
// use Microsoft* C compiler dependent integer width types
//
typedef unsigned __int64 UINT64;
typedef __int64 INT64;
typedef unsigned __int32 UINT32;
typedef __int32 INT32;
typedef unsigned short UINT16;
typedef unsigned short CHAR16;
typedef short INT16;
typedef unsigned char BOOLEAN;
typedef unsigned char UINT8;
typedef char CHAR8;
typedef signed char INT8;
#else
//
// Assume standard ARM alignment.
// Need to check portability of long long
//
typedef unsigned long long UINT64;
typedef long long INT64;
typedef unsigned int UINT32;
typedef int INT32;
typedef unsigned short UINT16;
typedef unsigned short CHAR16;
typedef short INT16;
typedef unsigned char BOOLEAN;
typedef unsigned char UINT8;
typedef char CHAR8;
typedef signed char INT8;
#endif
///
/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions,
/// 8 bytes on supported 64-bit processor instructions)
///
typedef UINT32 UINTN;
///
/// Signed value of native width. (4 bytes on supported 32-bit processor instructions,
/// 8 bytes on supported 64-bit processor instructions)
///
typedef INT32 INTN;
//
// Processor specific defines
//
///
/// A value of native width with the highest bit set.
///
#define MAX_BIT 0x80000000
///
/// A value of native width with the two highest bits set.
///
#define MAX_2_BITS 0xC0000000
///
/// Maximum legal ARM address
///
#define MAX_ADDRESS 0xFFFFFFFF
///
/// Maximum legal ARM INTN and UINTN values.
///
#define MAX_INTN ((INTN)0x7FFFFFFF)
#define MAX_UINTN ((UINTN)0xFFFFFFFF)
///
/// The stack alignment required for ARM
///
#define CPU_STACK_ALIGNMENT sizeof(UINT64)
///
/// Page allocation granularity for ARM
///
#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)
#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000)
//
// Modifier to ensure that all protocol member functions and EFI intrinsics
// use the correct C calling convention. All protocol member functions and
// EFI intrinsics are required to modify their member functions with EFIAPI.
//
#define EFIAPI
// When compiling with Clang, we still use GNU as for the assembler, so we still
// need to define the GCC_ASM* macros.
#if defined(__GNUC__) || defined(__clang__)
///
/// For GNU assembly code, .global or .globl can declare global symbols.
/// Define this macro to unify the usage.
///
#define ASM_GLOBAL .globl
#if !defined(__APPLE__)
///
/// ARM EABI defines that the linker should not manipulate call relocations
/// (do bl/blx conversion) unless the target symbol has function type.
/// CodeSourcery 2010.09 started requiring the .type to function properly
///
#define INTERWORK_FUNC(func__) .type ASM_PFX(func__), %function
#define GCC_ASM_EXPORT(func__) \
.global _CONCATENATE (__USER_LABEL_PREFIX__, func__) ;\
.type ASM_PFX(func__), %function
#define GCC_ASM_IMPORT(func__) \
.extern _CONCATENATE (__USER_LABEL_PREFIX__, func__)
#else
//
// .type not supported by Apple Xcode tools
//
#define INTERWORK_FUNC(func__)
#define GCC_ASM_EXPORT(func__) \
.globl _CONCATENATE (__USER_LABEL_PREFIX__, func__) \
#define GCC_ASM_IMPORT(name)
#endif
#endif
/**
Return the pointer to the first instruction of a function given a function pointer.
On ARM CPU architectures, these two pointer values are the same,
so the implementation of this macro is very simple.
@param FunctionPointer A pointer to a function.
@return The pointer to the first instruction of a function given a function pointer.
**/
#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)
#ifndef __USER_LABEL_PREFIX__
#define __USER_LABEL_PREFIX__
#endif
#endif

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/** @file
Processor or compiler specific defines and types for EBC.
We currently only have one EBC compiler so there may be some Intel compiler
specific functions in this file.
Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __PROCESSOR_BIND_H__
#define __PROCESSOR_BIND_H__
///
/// Define the processor type so other code can make processor based choices
///
#define MDE_CPU_EBC
//
// Native integer types
//
///
/// 1-byte signed value
///
typedef signed char INT8;
///
/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other
/// values are undefined.
///
typedef unsigned char BOOLEAN;
///
/// 1-byte unsigned value.
///
typedef unsigned char UINT8;
///
/// 1-byte Character.
///
typedef char CHAR8;
///
/// 2-byte signed value.
///
typedef short INT16;
///
/// 2-byte unsigned value.
///
typedef unsigned short UINT16;
///
/// 2-byte Character. Unless otherwise specified all strings are stored in the
/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.
///
typedef unsigned short CHAR16;
///
/// 4-byte signed value.
///
typedef int INT32;
///
/// 4-byte unsigned value.
///
typedef unsigned int UINT32;
///
/// 8-byte signed value.
///
typedef __int64 INT64;
///
/// 8-byte unsigned value.
///
typedef unsigned __int64 UINT64;
///
/// Signed value of native width. (4 bytes on supported 32-bit processor instructions,
/// 8 bytes on supported 64-bit processor instructions)
/// "long" type scales to the processor native size with EBC compiler
///
typedef long INTN;
///
/// The unsigned value of native width. (4 bytes on supported 32-bit processor instructions;
/// 8 bytes on supported 64-bit processor instructions)
/// "long" type scales to the processor native size with the EBC compiler.
///
typedef unsigned long UINTN;
///
/// A value of native width with the highest bit set.
/// Scalable macro to set the most significant bit in a natural number.
///
#define MAX_BIT (1ULL << (sizeof (INTN) * 8 - 1))
///
/// A value of native width with the two highest bits set.
/// Scalable macro to set the most 2 significant bits in a natural number.
///
#define MAX_2_BITS (3ULL << (sizeof (INTN) * 8 - 2))
///
/// Maximum legal EBC address
///
#define MAX_ADDRESS ((UINTN) ~0)
///
/// Maximum legal EBC INTN and UINTN values.
///
#define MAX_UINTN ((UINTN) ~0)
#define MAX_INTN ((INTN)~MAX_BIT)
///
/// The stack alignment required for EBC
///
#define CPU_STACK_ALIGNMENT sizeof(UINTN)
///
/// Page allocation granularity for EBC
///
#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)
#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000)
///
/// Modifier to ensure that all protocol member functions and EFI intrinsics
/// use the correct C calling convention. All protocol member functions and
/// EFI intrinsics are required to modify their member functions with EFIAPI.
///
#ifdef EFIAPI
///
/// If EFIAPI is already defined, then we use that definition.
///
#else
#define EFIAPI
#endif
/**
Return the pointer to the first instruction of a function given a function pointer.
On EBC architectures, these two pointer values are the same,
so the implementation of this macro is very simple.
@param FunctionPointer A pointer to a function.
@return The pointer to the first instruction of a function given a function pointer.
**/
#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)
#ifndef __USER_LABEL_PREFIX__
#define __USER_LABEL_PREFIX__
#endif
#endif

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/** @file
GUIDs used for ACPI entries in the EFI system table
These GUIDs point the ACPI tables as defined in the ACPI specifications.
ACPI 2.0 specification defines the ACPI 2.0 GUID. UEFI 2.0 defines the
ACPI 2.0 Table GUID and ACPI Table GUID.
Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
GUIDs defined in UEFI 2.0 spec.
**/
#ifndef __ACPI_GUID_H__
#define __ACPI_GUID_H__
#define ACPI_TABLE_GUID \
{ \
0xeb9d2d30, 0x2d88, 0x11d3, {0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \
}
#define EFI_ACPI_TABLE_GUID \
{ \
0x8868e871, 0xe4f1, 0x11d3, {0xbc, 0x22, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
}
#define ACPI_10_TABLE_GUID ACPI_TABLE_GUID
//
// ACPI 2.0 or newer tables should use EFI_ACPI_TABLE_GUID.
//
#define EFI_ACPI_20_TABLE_GUID EFI_ACPI_TABLE_GUID
extern EFI_GUID gEfiAcpiTableGuid;
extern EFI_GUID gEfiAcpi10TableGuid;
extern EFI_GUID gEfiAcpi20TableGuid;
#endif

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/** @file
GUID used as an FV filename for A Priori file. The A Priori file contains a
list of FV filenames that the DXE dispatcher will schedule reguardless of
the dependency grammar.
Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
GUID introduced in PI Version 1.0.
**/
#ifndef __APRIORI_GUID_H__
#define __APRIORI_GUID_H__
#define EFI_APRIORI_GUID \
{ \
0xfc510ee7, 0xffdc, 0x11d4, {0xbd, 0x41, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
}
extern EFI_GUID gAprioriGuid;
#endif

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/** @file
The GUID PEI_APRIORI_FILE_NAME_GUID definition is the file
name of the PEI a priori file that is stored in a firmware
volume.
Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
GUID introduced in PI Version 1.0.
**/
#ifndef __PEI_APRIORI_FILE_NAME_H__
#define __PEI_APRIORI_FILE_NAME_H__
#define PEI_APRIORI_FILE_NAME_GUID \
{ 0x1b45cc0a, 0x156a, 0x428a, { 0x62, 0XAF, 0x49, 0x86, 0x4d, 0xa0, 0xe6, 0xe6 } }
///
/// This file must be of type EFI_FV_FILETYPE_FREEFORM and must
/// contain a single section of type EFI_SECTION_RAW. For details on
/// firmware volumes, firmware file types, and firmware file section
/// types.
///
typedef struct {
///
/// An array of zero or more EFI_GUID type entries that match the file names of PEIM
/// modules in the same Firmware Volume. The maximum number of entries.
///
EFI_GUID FileNamesWithinVolume[1];
} PEI_APRIORI_FILE_CONTENTS;
extern EFI_GUID gPeiAprioriFileNameGuid;
#endif

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/** @file
Guid & data structure used for Capsule process result variables
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
GUIDs defined in UEFI 2.4 spec.
**/
#ifndef _CAPSULE_REPORT_GUID_H__
#define _CAPSULE_REPORT_GUID_H__
//
// This is the GUID for capsule result variable.
//
#define EFI_CAPSULE_REPORT_GUID \
{ \
0x39b68c46, 0xf7fb, 0x441b, {0xb6, 0xec, 0x16, 0xb0, 0xf6, 0x98, 0x21, 0xf3 } \
}
typedef struct {
///
/// Size in bytes of the variable including any data beyond header as specified by CapsuleGuid
///
UINT32 VariableTotalSize;
///
/// For alignment
///
UINT32 Reserved;
///
/// Guid from EFI_CAPSULE_HEADER
///
EFI_GUID CapsuleGuid;
///
/// Timestamp using system time when processing completed
///
EFI_TIME CapsuleProcessed;
///
/// Result of the capsule processing. Exact interpretation of any error code may depend
/// upon type of capsule processed
///
EFI_STATUS CapsuleStatus;
} EFI_CAPSULE_RESULT_VARIABLE_HEADER;
typedef struct {
///
/// Version of this structure, currently 0x00000001
///
UINT16 Version;
///
/// The index of the payload within the FMP capsule which was processed to generate this report
/// Starting from zero
///
UINT8 PayloadIndex;
///
/// The UpdateImageIndex from EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER
/// (after unsigned conversion from UINT8 to UINT16).
///
UINT8 UpdateImageIndex;
///
/// The UpdateImageTypeId Guid from EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER.
///
EFI_GUID UpdateImageTypeId;
///
/// In case of capsule loaded from disk, the zero-terminated array containing file name of capsule that was processed.
/// In case of capsule submitted directly to UpdateCapsule() there is no file name, and this field is required to contain a single 16-bit zero character
/// which is included in VariableTotalSize.
///
/// CHAR16 CapsuleFileName[];
///
///
/// This field will contain a zero-terminated CHAR16 string containing the text representation of the device path of device publishing Firmware Management Protocol
/// (if present). In case where device path is not present and the target is not otherwise known to firmware, or when payload was blocked by policy, or skipped,
/// this field is required to contain a single 16-bit zero character which is included in VariableTotalSize.
///
/// CHAR16 CapsuleTarget[];
///
} EFI_CAPSULE_RESULT_VARIABLE_FMP;
extern EFI_GUID gEfiCapsuleReportGuid;
#endif

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/** @file
GUID and related data structures used with the Debug Image Info Table.
Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
GUID defined in UEFI 2.0 spec.
**/
#ifndef __DEBUG_IMAGE_INFO_GUID_H__
#define __DEBUG_IMAGE_INFO_GUID_H__
#include <Protocol/LoadedImage.h>
///
/// EFI_DEBUG_IMAGE_INFO_TABLE configuration table GUID declaration.
///
#define EFI_DEBUG_IMAGE_INFO_TABLE_GUID \
{ \
0x49152e77, 0x1ada, 0x4764, {0xb7, 0xa2, 0x7a, 0xfe, 0xfe, 0xd9, 0x5e, 0x8b } \
}
#define EFI_DEBUG_IMAGE_INFO_UPDATE_IN_PROGRESS 0x01
#define EFI_DEBUG_IMAGE_INFO_TABLE_MODIFIED 0x02
#define EFI_DEBUG_IMAGE_INFO_TYPE_NORMAL 0x01
typedef struct {
UINT64 Signature; ///< A constant UINT64 that has the value EFI_SYSTEM_TABLE_SIGNATURE
EFI_PHYSICAL_ADDRESS EfiSystemTableBase; ///< The physical address of the EFI system table.
UINT32 Crc32; ///< A 32-bit CRC value that is used to verify the EFI_SYSTEM_TABLE_POINTER structure is valid.
} EFI_SYSTEM_TABLE_POINTER;
typedef struct {
///
/// Indicates the type of image info structure. For PE32 EFI images,
/// this is set to EFI_DEBUG_IMAGE_INFO_TYPE_NORMAL.
///
UINT32 ImageInfoType;
///
/// A pointer to an instance of the loaded image protocol for the associated image.
///
EFI_LOADED_IMAGE_PROTOCOL *LoadedImageProtocolInstance;
///
/// Indicates the image handle of the associated image.
///
EFI_HANDLE ImageHandle;
} EFI_DEBUG_IMAGE_INFO_NORMAL;
typedef union {
UINT32 *ImageInfoType;
EFI_DEBUG_IMAGE_INFO_NORMAL *NormalImage;
} EFI_DEBUG_IMAGE_INFO;
typedef struct {
///
/// UpdateStatus is used by the system to indicate the state of the debug image info table.
///
volatile UINT32 UpdateStatus;
///
/// The number of EFI_DEBUG_IMAGE_INFO elements in the array pointed to by EfiDebugImageInfoTable.
///
UINT32 TableSize;
///
/// A pointer to the first element of an array of EFI_DEBUG_IMAGE_INFO structures.
///
EFI_DEBUG_IMAGE_INFO *EfiDebugImageInfoTable;
} EFI_DEBUG_IMAGE_INFO_TABLE_HEADER;
extern EFI_GUID gEfiDebugImageInfoTableGuid;
#endif

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/** @file
GUID used to identify the DXE Services Table
Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
GUID introduced in PI Version 1.0.
**/
#ifndef __DXE_SERVICES_GUID_H__
#define __DXE_SERVICES_GUID_H__
#define DXE_SERVICES_TABLE_GUID \
{ \
0x5ad34ba, 0x6f02, 0x4214, {0x95, 0x2e, 0x4d, 0xa0, 0x39, 0x8e, 0x2b, 0xb9 } \
}
extern EFI_GUID gEfiDxeServicesTableGuid;
#endif

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/** @file
GUIDs for gBS->CreateEventEx Event Groups. Defined in UEFI spec 2.0 and PI 1.2.1.
Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __EVENT_GROUP_GUID__
#define __EVENT_GROUP_GUID__
#define EFI_EVENT_GROUP_EXIT_BOOT_SERVICES \
{ 0x27abf055, 0xb1b8, 0x4c26, { 0x80, 0x48, 0x74, 0x8f, 0x37, 0xba, 0xa2, 0xdf } }
extern EFI_GUID gEfiEventExitBootServicesGuid;
#define EFI_EVENT_GROUP_VIRTUAL_ADDRESS_CHANGE \
{ 0x13fa7698, 0xc831, 0x49c7, { 0x87, 0xea, 0x8f, 0x43, 0xfc, 0xc2, 0x51, 0x96 } }
extern EFI_GUID gEfiEventVirtualAddressChangeGuid;
#define EFI_EVENT_GROUP_MEMORY_MAP_CHANGE \
{ 0x78bee926, 0x692f, 0x48fd, { 0x9e, 0xdb, 0x1, 0x42, 0x2e, 0xf0, 0xd7, 0xab } }
extern EFI_GUID gEfiEventMemoryMapChangeGuid;
#define EFI_EVENT_GROUP_READY_TO_BOOT \
{ 0x7ce88fb3, 0x4bd7, 0x4679, { 0x87, 0xa8, 0xa8, 0xd8, 0xde, 0xe5, 0x0d, 0x2b } }
extern EFI_GUID gEfiEventReadyToBootGuid;
#define EFI_EVENT_GROUP_DXE_DISPATCH_GUID \
{ 0x7081e22f, 0xcac6, 0x4053, { 0x94, 0x68, 0x67, 0x57, 0x82, 0xcf, 0x88, 0xe5 }}
extern EFI_GUID gEfiEventDxeDispatchGuid;
#define EFI_END_OF_DXE_EVENT_GROUP_GUID \
{ 0x2ce967a, 0xdd7e, 0x4ffc, { 0x9e, 0xe7, 0x81, 0xc, 0xf0, 0x47, 0x8, 0x80 } }
extern EFI_GUID gEfiEndOfDxeEventGroupGuid;
#endif

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/** @file
GUID is the name of events used with CreateEventEx in order to be notified
when the EFI boot manager is about to boot a legacy boot option.
Events of this type are notificated just before Int19h is invoked.
Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
GUID introduced in PI Version 1.0.
**/
#ifndef __EVENT_LEGACY_BIOS_GUID_H__
#define __EVENT_LEGACY_BIOS_GUID_H__
#define EFI_EVENT_LEGACY_BOOT_GUID \
{ 0x2a571201, 0x4966, 0x47f6, {0x8b, 0x86, 0xf3, 0x1e, 0x41, 0xf3, 0x2f, 0x10 } }
extern EFI_GUID gEfiEventLegacyBootGuid;
#endif

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/** @file
Provides a GUID and a data structure that can be used with EFI_FILE_PROTOCOL.SetInfo()
and EFI_FILE_PROTOCOL.GetInfo() to set or get generic file information.
This GUID is defined in UEFI specification.
Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __FILE_INFO_H__
#define __FILE_INFO_H__
#define EFI_FILE_INFO_ID \
{ \
0x9576e92, 0x6d3f, 0x11d2, {0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b } \
}
typedef struct {
///
/// The size of the EFI_FILE_INFO structure, including the Null-terminated FileName string.
///
UINT64 Size;
///
/// The size of the file in bytes.
///
UINT64 FileSize;
///
/// PhysicalSize The amount of physical space the file consumes on the file system volume.
///
UINT64 PhysicalSize;
///
/// The time the file was created.
///
EFI_TIME CreateTime;
///
/// The time when the file was last accessed.
///
EFI_TIME LastAccessTime;
///
/// The time when the file's contents were last modified.
///
EFI_TIME ModificationTime;
///
/// The attribute bits for the file.
///
UINT64 Attribute;
///
/// The Null-terminated name of the file.
///
CHAR16 FileName[1];
} EFI_FILE_INFO;
///
/// The FileName field of the EFI_FILE_INFO data structure is variable length.
/// Whenever code needs to know the size of the EFI_FILE_INFO data structure, it needs to
/// be the size of the data structure without the FileName field. The following macro
/// computes this size correctly no matter how big the FileName array is declared.
/// This is required to make the EFI_FILE_INFO data structure ANSI compilant.
///
#define SIZE_OF_EFI_FILE_INFO OFFSET_OF (EFI_FILE_INFO, FileName)
extern EFI_GUID gEfiFileInfoGuid;
#endif

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/** @file
Provides a GUID and a data structure that can be used with EFI_FILE_PROTOCOL.GetInfo()
or EFI_FILE_PROTOCOL.SetInfo() to get or set information about the system's volume.
This GUID is defined in UEFI specification.
Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __FILE_SYSTEM_INFO_H__
#define __FILE_SYSTEM_INFO_H__
#define EFI_FILE_SYSTEM_INFO_ID \
{ \
0x9576e93, 0x6d3f, 0x11d2, {0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b } \
}
typedef struct {
///
/// The size of the EFI_FILE_SYSTEM_INFO structure, including the Null-terminated VolumeLabel string.
///
UINT64 Size;
///
/// TRUE if the volume only supports read access.
///
BOOLEAN ReadOnly;
///
/// The number of bytes managed by the file system.
///
UINT64 VolumeSize;
///
/// The number of available bytes for use by the file system.
///
UINT64 FreeSpace;
///
/// The nominal block size by which files are typically grown.
///
UINT32 BlockSize;
///
/// The Null-terminated string that is the volume's label.
///
CHAR16 VolumeLabel[1];
} EFI_FILE_SYSTEM_INFO;
///
/// The VolumeLabel field of the EFI_FILE_SYSTEM_INFO data structure is variable length.
/// Whenever code needs to know the size of the EFI_FILE_SYSTEM_INFO data structure, it needs
/// to be the size of the data structure without the VolumeLable field. The following macro
/// computes this size correctly no matter how big the VolumeLable array is declared.
/// This is required to make the EFI_FILE_SYSTEM_INFO data structure ANSI compilant.
///
#define SIZE_OF_EFI_FILE_SYSTEM_INFO OFFSET_OF (EFI_FILE_SYSTEM_INFO, VolumeLabel)
extern EFI_GUID gEfiFileSystemInfoGuid;
#endif

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/** @file
Provides a GUID and a data structure that can be used with EFI_FILE_PROTOCOL.GetInfo()
or EFI_FILE_PROTOCOL.SetInfo() to get or set the system's volume label.
This GUID is defined in UEFI specification.
Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __FILE_SYSTEM_VOLUME_LABEL_INFO_H__
#define __FILE_SYSTEM_VOLUME_LABEL_INFO_H__
#define EFI_FILE_SYSTEM_VOLUME_LABEL_ID \
{ \
0xDB47D7D3, 0xFE81, 0x11d3, {0x9A, 0x35, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D } \
}
typedef struct {
///
/// The Null-terminated string that is the volume's label.
///
CHAR16 VolumeLabel[1];
} EFI_FILE_SYSTEM_VOLUME_LABEL;
#define SIZE_OF_EFI_FILE_SYSTEM_VOLUME_LABEL \
OFFSET_OF (EFI_FILE_SYSTEM_VOLUME_LABEL, VolumeLabel)
extern EFI_GUID gEfiFileSystemVolumeLabelInfoIdGuid;
#endif

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/** @file
GUID is used to define the signed section.
Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
GUID introduced in PI Version 1.2.1.
**/
#ifndef __FIRMWARE_CONTENTS_SIGNED_GUID_H__
#define __FIRMWARE_CONTENTS_SIGNED_GUID_H__
#define EFI_FIRMWARE_CONTENTS_SIGNED_GUID \
{ 0xf9d89e8, 0x9259, 0x4f76, {0xa5, 0xaf, 0xc, 0x89, 0xe3, 0x40, 0x23, 0xdf } }
extern EFI_GUID gEfiFirmwareContentsSignedGuid;
#endif

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/** @file
Guid used to define the Firmware File System 2.
Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
GUIDs introduced in PI Version 1.0.
**/
#ifndef __FIRMWARE_FILE_SYSTEM2_GUID_H__
#define __FIRMWARE_FILE_SYSTEM2_GUID_H__
///
/// The firmware volume header contains a data field for
/// the file system GUID
///
#define EFI_FIRMWARE_FILE_SYSTEM2_GUID \
{ 0x8c8ce578, 0x8a3d, 0x4f1c, { 0x99, 0x35, 0x89, 0x61, 0x85, 0xc3, 0x2d, 0xd3 } }
///
/// A Volume Top File (VTF) is a file that must be
/// located such that the last byte of the file is
/// also the last byte of the firmware volume
///
#define EFI_FFS_VOLUME_TOP_FILE_GUID \
{ 0x1BA0062E, 0xC779, 0x4582, { 0x85, 0x66, 0x33, 0x6A, 0xE8, 0xF7, 0x8F, 0x9 } }
extern EFI_GUID gEfiFirmwareFileSystem2Guid;
extern EFI_GUID gEfiFirmwareVolumeTopFileGuid;
#endif

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/** @file
Guid used to define the Firmware File System 3.
Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
GUIDs introduced in PI Version 1.0.
**/
#ifndef __FIRMWARE_FILE_SYSTEM3_GUID_H__
#define __FIRMWARE_FILE_SYSTEM3_GUID_H__
///
/// The firmware volume header contains a data field for the file system GUID
/// {5473C07A-3DCB-4dca-BD6F-1E9689E7349A}
///
#define EFI_FIRMWARE_FILE_SYSTEM3_GUID \
{ 0x5473c07a, 0x3dcb, 0x4dca, { 0xbd, 0x6f, 0x1e, 0x96, 0x89, 0xe7, 0x34, 0x9a }}
extern EFI_GUID gEfiFirmwareFileSystem3Guid;
#endif // __FIRMWARE_FILE_SYSTEM3_GUID_H__

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/** @file
Guid & data structure used for Delivering Capsules Containing Updates to Firmware
Management Protocol
Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
GUIDs defined in UEFI 2.4 spec.
**/
#ifndef _FMP_CAPSULE_GUID_H__
#define _FMP_CAPSULE_GUID_H__
//
// This is the GUID of the capsule for Firmware Management Protocol.
//
#define EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID \
{ \
0x6dcbd5ed, 0xe82d, 0x4c44, {0xbd, 0xa1, 0x71, 0x94, 0x19, 0x9a, 0xd9, 0x2a } \
}
#pragma pack(1)
typedef struct {
UINT32 Version;
///
/// The number of drivers included in the capsule and the number of corresponding
/// offsets stored in ItemOffsetList array.
///
UINT16 EmbeddedDriverCount;
///
/// The number of payload items included in the capsule and the number of
/// corresponding offsets stored in the ItemOffsetList array.
///
UINT16 PayloadItemCount;
///
/// Variable length array of dimension [EmbeddedDriverCount + PayloadItemCount]
/// containing offsets of each of the drivers and payload items contained within the capsule
///
// UINT64 ItemOffsetList[];
} EFI_FIRMWARE_MANAGEMENT_CAPSULE_HEADER;
typedef struct {
UINT32 Version;
///
/// Used to identify device firmware targeted by this update. This guid is matched by
/// system firmware against ImageTypeId field within a EFI_FIRMWARE_IMAGE_DESCRIPTOR
///
EFI_GUID UpdateImageTypeId;
///
/// Passed as ImageIndex in call to EFI_FIRMWARE_MANAGEMENT_PROTOCOL.SetImage()
///
UINT8 UpdateImageIndex;
UINT8 reserved_bytes[3];
///
/// Size of the binary update image which immediately follows this structure
///
UINT32 UpdateImageSize;
///
/// Size of the VendorCode bytes which optionally immediately follow binary update image in the capsule
///
UINT32 UpdateVendorCodeSize;
///
/// The HardwareInstance to target with this update. If value is zero it means match all
/// HardwareInstances. This field allows update software to target only a single device in
/// cases where there are more than one device with the same ImageTypeId GUID.
/// This header is outside the signed data of the Authentication Info structure and
/// therefore can be modified without changing the Auth data.
///
UINT64 UpdateHardwareInstance;
} EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER;
#pragma pack()
#define EFI_FIRMWARE_MANAGEMENT_CAPSULE_HEADER_INIT_VERSION 0x00000001
#define EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER_INIT_VERSION 0x00000002
extern EFI_GUID gEfiFmpCapsuleGuid;
#endif

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/** @file
GUID for EFI (NVRAM) Variables.
Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
GUID defined in UEFI 2.1
**/
#ifndef __GLOBAL_VARIABLE_GUID_H__
#define __GLOBAL_VARIABLE_GUID_H__
#define EFI_GLOBAL_VARIABLE \
{ \
0x8BE4DF61, 0x93CA, 0x11d2, {0xAA, 0x0D, 0x00, 0xE0, 0x98, 0x03, 0x2B, 0x8C } \
}
extern EFI_GUID gEfiGlobalVariableGuid;
//
// Follow UEFI 2.4 spec:
// To prevent name collisions with possible future globally defined variables,
// other internal firmware data variables that are not defined here must be
// saved with a unique VendorGuid other than EFI_GLOBAL_VARIABLE or
// any other GUID defined by the UEFI Specification. Implementations must
// only permit the creation of variables with a UEFI Specification-defined
// VendorGuid when these variables are documented in the UEFI Specification.
//
// Note: except the globally defined variables defined below, the spec also defines
// L"Boot####" - A boot load option.
// L"Driver####" - A driver load option.
// L"SysPrep####" - A System Prep application load option.
// L"Key####" - Describes hot key relationship with a Boot#### load option.
// The attribute for them is NV+BS+RT, #### is a printed hex value, and no 0x or h
// is included in the hex value. They can not be expressed as a #define like other globally
// defined variables, it is because we can not list the Boot0000, Boot0001, etc one by one.
//
///
/// The language codes that the firmware supports. This value is deprecated.
/// Its attribute is BS+RT.
///
#define EFI_LANG_CODES_VARIABLE_NAME L"LangCodes"
///
/// The language code that the system is configured for. This value is deprecated.
/// Its attribute is NV+BS+RT.
///
#define EFI_LANG_VARIABLE_NAME L"Lang"
///
/// The firmware's boot managers timeout, in seconds, before initiating the default boot selection.
/// Its attribute is NV+BS+RT.
///
#define EFI_TIME_OUT_VARIABLE_NAME L"Timeout"
///
/// The language codes that the firmware supports.
/// Its attribute is BS+RT.
///
#define EFI_PLATFORM_LANG_CODES_VARIABLE_NAME L"PlatformLangCodes"
///
/// The language code that the system is configured for.
/// Its attribute is NV+BS+RT.
///
#define EFI_PLATFORM_LANG_VARIABLE_NAME L"PlatformLang"
///
/// The device path of the default input/output/error output console.
/// Its attribute is NV+BS+RT.
///
#define EFI_CON_IN_VARIABLE_NAME L"ConIn"
#define EFI_CON_OUT_VARIABLE_NAME L"ConOut"
#define EFI_ERR_OUT_VARIABLE_NAME L"ErrOut"
///
/// The device path of all possible input/output/error output devices.
/// Its attribute is BS+RT.
///
#define EFI_CON_IN_DEV_VARIABLE_NAME L"ConInDev"
#define EFI_CON_OUT_DEV_VARIABLE_NAME L"ConOutDev"
#define EFI_ERR_OUT_DEV_VARIABLE_NAME L"ErrOutDev"
///
/// The ordered boot option load list.
/// Its attribute is NV+BS+RT.
///
#define EFI_BOOT_ORDER_VARIABLE_NAME L"BootOrder"
///
/// The boot option for the next boot only.
/// Its attribute is NV+BS+RT.
///
#define EFI_BOOT_NEXT_VARIABLE_NAME L"BootNext"
///
/// The boot option that was selected for the current boot.
/// Its attribute is BS+RT.
///
#define EFI_BOOT_CURRENT_VARIABLE_NAME L"BootCurrent"
///
/// The types of boot options supported by the boot manager. Should be treated as read-only.
/// Its attribute is BS+RT.
///
#define EFI_BOOT_OPTION_SUPPORT_VARIABLE_NAME L"BootOptionSupport"
///
/// The ordered driver load option list.
/// Its attribute is NV+BS+RT.
///
#define EFI_DRIVER_ORDER_VARIABLE_NAME L"DriverOrder"
///
/// The ordered System Prep Application load option list.
/// Its attribute is NV+BS+RT.
///
#define EFI_SYS_PREP_ORDER_VARIABLE_NAME L"SysPrepOrder"
///
/// Identifies the level of hardware error record persistence
/// support implemented by the platform. This variable is
/// only modified by firmware and is read-only to the OS.
/// Its attribute is NV+BS+RT.
///
#define EFI_HW_ERR_REC_SUPPORT_VARIABLE_NAME L"HwErrRecSupport"
///
/// Whether the system is operating in setup mode (1) or not (0).
/// All other values are reserved. Should be treated as read-only.
/// Its attribute is BS+RT.
///
#define EFI_SETUP_MODE_NAME L"SetupMode"
///
/// The Key Exchange Key Signature Database.
/// Its attribute is NV+BS+RT+AT.
///
#define EFI_KEY_EXCHANGE_KEY_NAME L"KEK"
///
/// The public Platform Key.
/// Its attribute is NV+BS+RT+AT.
///
#define EFI_PLATFORM_KEY_NAME L"PK"
///
/// Array of GUIDs representing the type of signatures supported
/// by the platform firmware. Should be treated as read-only.
/// Its attribute is BS+RT.
///
#define EFI_SIGNATURE_SUPPORT_NAME L"SignatureSupport"
///
/// Whether the platform firmware is operating in Secure boot mode (1) or not (0).
/// All other values are reserved. Should be treated as read-only.
/// Its attribute is BS+RT.
///
#define EFI_SECURE_BOOT_MODE_NAME L"SecureBoot"
///
/// The OEM's default Key Exchange Key Signature Database. Should be treated as read-only.
/// Its attribute is BS+RT.
///
#define EFI_KEK_DEFAULT_VARIABLE_NAME L"KEKDefault"
///
/// The OEM's default public Platform Key. Should be treated as read-only.
/// Its attribute is BS+RT.
///
#define EFI_PK_DEFAULT_VARIABLE_NAME L"PKDefault"
///
/// The OEM's default secure boot signature store. Should be treated as read-only.
/// Its attribute is BS+RT.
///
#define EFI_DB_DEFAULT_VARIABLE_NAME L"dbDefault"
///
/// The OEM's default secure boot blacklist signature store. Should be treated as read-only.
/// Its attribute is BS+RT.
///
#define EFI_DBX_DEFAULT_VARIABLE_NAME L"dbxDefault"
///
/// The OEM's default secure boot timestamp signature store. Should be treated as read-only.
/// Its attribute is BS+RT.
///
#define EFI_DBT_DEFAULT_VARIABLE_NAME L"dbtDefault"
///
/// Allows the firmware to indicate supported features and actions to the OS.
/// Its attribute is BS+RT.
///
#define EFI_OS_INDICATIONS_SUPPORT_VARIABLE_NAME L"OsIndicationsSupported"
///
/// Allows the OS to request the firmware to enable certain features and to take certain actions.
/// Its attribute is NV+BS+RT.
///
#define EFI_OS_INDICATIONS_VARIABLE_NAME L"OsIndications"
///
/// Whether the system is configured to use only vendor provided
/// keys or not. Should be treated as read-only.
/// Its attribute is BS+RT.
///
#define EFI_VENDOR_KEYS_VARIABLE_NAME L"VendorKeys"
#endif

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/** @file
Guids used for the GPT (GUID Partition Table)
GPT defines a new disk partitioning scheme and also describes
usage of the legacy Master Boot Record (MBR) partitioning scheme.
Copyright (c) 2006 - 2007, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
GUIDs defined in UEFI 2.1 spec.
**/
#ifndef __GPT_GUID_H__
#define __GPT_GUID_H__
#define EFI_PART_TYPE_UNUSED_GUID \
{ \
0x00000000, 0x0000, 0x0000, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } \
}
#define EFI_PART_TYPE_EFI_SYSTEM_PART_GUID \
{ \
0xc12a7328, 0xf81f, 0x11d2, {0xba, 0x4b, 0x00, 0xa0, 0xc9, 0x3e, 0xc9, 0x3b } \
}
#define EFI_PART_TYPE_LEGACY_MBR_GUID \
{ \
0x024dee41, 0x33e7, 0x11d3, {0x9d, 0x69, 0x00, 0x08, 0xc7, 0x81, 0xf3, 0x9f } \
}
extern EFI_GUID gEfiPartTypeUnusedGuid;
extern EFI_GUID gEfiPartTypeSystemPartGuid;
extern EFI_GUID gEfiPartTypeLegacyMbrGuid;
#endif

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MdePkg/Include/Guid/GraphicsInfoHob.h Normal file
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/** @file
Hob guid for Information about the graphics mode.
Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
This HOB is introduced in in PI Version 1.4.
**/
#ifndef _GRAPHICS_INFO_HOB_GUID_H_
#define _GRAPHICS_INFO_HOB_GUID_H_
#include <Protocol/GraphicsOutput.h>
#define EFI_PEI_GRAPHICS_INFO_HOB_GUID \
{ \
0x39f62cce, 0x6825, 0x4669, { 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07 } \
}
#define EFI_PEI_GRAPHICS_DEVICE_INFO_HOB_GUID \
{ \
0xe5cb2ac9, 0xd35d, 0x4430, { 0x93, 0x6e, 0x1d, 0xe3, 0x32, 0x47, 0x8d, 0xe7 } \
}
typedef struct {
EFI_PHYSICAL_ADDRESS FrameBufferBase;
UINT32 FrameBufferSize;
EFI_GRAPHICS_OUTPUT_MODE_INFORMATION GraphicsMode;
} EFI_PEI_GRAPHICS_INFO_HOB;
typedef struct {
UINT16 VendorId; ///< Ignore if the value is 0xFFFF.
UINT16 DeviceId; ///< Ignore if the value is 0xFFFF.
UINT16 SubsystemVendorId; ///< Ignore if the value is 0xFFFF.
UINT16 SubsystemId; ///< Ignore if the value is 0xFFFF.
UINT8 RevisionId; ///< Ignore if the value is 0xFF.
UINT8 BarIndex; ///< Ignore if the value is 0xFF.
} EFI_PEI_GRAPHICS_DEVICE_INFO_HOB;
extern EFI_GUID gEfiGraphicsInfoHobGuid;
extern EFI_GUID gEfiGraphicsDeviceInfoHobGuid;
#endif

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MdePkg/Include/Guid/HardwareErrorVariable.h Normal file
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/** @file
GUID for hardware error record variables.
Copyright (c) 2007 - 2009, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
GUID defined in UEFI 2.1.
**/
#ifndef _HARDWARE_ERROR_VARIABLE_GUID_H_
#define _HARDWARE_ERROR_VARIABLE_GUID_H_
#define EFI_HARDWARE_ERROR_VARIABLE \
{ \
0x414E6BDD, 0xE47B, 0x47cc, {0xB2, 0x44, 0xBB, 0x61, 0x02, 0x0C, 0xF5, 0x16} \
}
extern EFI_GUID gEfiHardwareErrorVariableGuid;
#endif

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MdePkg/Include/Guid/HiiFormMapMethodGuid.h Normal file
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/** @file
Guid used to identify HII FormMap configuration method.
Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
GUID defined in UEFI 2.2 spec.
**/
#ifndef __EFI_HII_FORMMAP_GUID_H__
#define __EFI_HII_FORMMAP_GUID_H__
#define EFI_HII_STANDARD_FORM_GUID \
{ 0x3bd2f4ec, 0xe524, 0x46e4, { 0xa9, 0xd8, 0x51, 0x1, 0x17, 0x42, 0x55, 0x62 } }
extern EFI_GUID gEfiHiiStandardFormGuid;
#endif

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MdePkg/Include/Guid/HiiKeyBoardLayout.h Normal file
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/** @file
HII keyboard layout GUID as defined in UEFI2.1 specification
Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
GUIDs defined in UEFI 2.1 spec.
**/
#ifndef __HII_KEYBOARD_LAYOUT_GUID_H__
#define __HII_KEYBOARD_LAYOUT_GUID_H__
#define EFI_HII_SET_KEYBOARD_LAYOUT_EVENT_GUID \
{ 0x14982a4f, 0xb0ed, 0x45b8, { 0xa8, 0x11, 0x5a, 0x7a, 0x9b, 0xc2, 0x32, 0xdf }}
extern EFI_GUID gEfiHiiKeyBoardLayoutGuid;
#endif

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MdePkg/Include/Guid/HiiPlatformSetupFormset.h Normal file
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/** @file
GUID indicates that the form set contains forms designed to be used
for platform configuration and this form set will be displayed.
Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
GUID defined in UEFI 2.1.
**/
#ifndef __HII_PLATFORM_SETUP_FORMSET_GUID_H__
#define __HII_PLATFORM_SETUP_FORMSET_GUID_H__
#define EFI_HII_PLATFORM_SETUP_FORMSET_GUID \
{ 0x93039971, 0x8545, 0x4b04, { 0xb4, 0x5e, 0x32, 0xeb, 0x83, 0x26, 0x4, 0xe } }
#define EFI_HII_DRIVER_HEALTH_FORMSET_GUID \
{ 0xf22fc20c, 0x8cf4, 0x45eb, { 0x8e, 0x6, 0xad, 0x4e, 0x50, 0xb9, 0x5d, 0xd3 } }
#define EFI_HII_USER_CREDENTIAL_FORMSET_GUID \
{ 0x337f4407, 0x5aee, 0x4b83, { 0xb2, 0xa7, 0x4e, 0xad, 0xca, 0x30, 0x88, 0xcd } }
extern EFI_GUID gEfiHiiPlatformSetupFormsetGuid;
extern EFI_GUID gEfiHiiDriverHealthFormsetGuid;
extern EFI_GUID gEfiHiiUserCredentialFormsetGuid;
#endif

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MdePkg/Include/Guid/HobList.h Normal file
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/** @file
GUIDs used for HOB List entries
These GUIDs point the HOB List passed from PEI to DXE.
Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
GUID introduced in PI Version 1.0.
**/
#ifndef __HOB_LIST_GUID_H__
#define __HOB_LIST_GUID_H__
#define HOB_LIST_GUID \
{ \
0x7739f24c, 0x93d7, 0x11d4, {0x9a, 0x3a, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \
}
extern EFI_GUID gEfiHobListGuid;
#endif

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/** @file
Image signature database are defined for the signed image validation.
Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
GUIDs defined in UEFI 2.5 spec.
**/
#ifndef __IMAGE_AUTHTICATION_H__
#define __IMAGE_AUTHTICATION_H__
#include <Guid/GlobalVariable.h>
#include <Protocol/Hash.h>
#define EFI_IMAGE_SECURITY_DATABASE_GUID \
{ \
0xd719b2cb, 0x3d3a, 0x4596, { 0xa3, 0xbc, 0xda, 0xd0, 0xe, 0x67, 0x65, 0x6f } \
}
///
/// Varialbe name with guid EFI_IMAGE_SECURITY_DATABASE_GUID
/// for the authorized signature database.
///
#define EFI_IMAGE_SECURITY_DATABASE L"db"
///
/// Varialbe name with guid EFI_IMAGE_SECURITY_DATABASE_GUID
/// for the forbidden signature database.
///
#define EFI_IMAGE_SECURITY_DATABASE1 L"dbx"
///
/// Variable name with guid EFI_IMAGE_SECURITY_DATABASE_GUID
/// for the timestamp signature database.
///
#define EFI_IMAGE_SECURITY_DATABASE2 L"dbt"
#define SECURE_BOOT_MODE_ENABLE 1
#define SECURE_BOOT_MODE_DISABLE 0
#define SETUP_MODE 1
#define USER_MODE 0
//***********************************************************************
// Signature Database
//***********************************************************************
///
/// The format of a signature database.
///
#pragma pack(1)
typedef struct {
///
/// An identifier which identifies the agent which added the signature to the list.
///
EFI_GUID SignatureOwner;
///
/// The format of the signature is defined by the SignatureType.
///
UINT8 SignatureData[1];
} EFI_SIGNATURE_DATA;
typedef struct {
///
/// Type of the signature. GUID signature types are defined in below.
///
EFI_GUID SignatureType;
///
/// Total size of the signature list, including this header.
///
UINT32 SignatureListSize;
///
/// Size of the signature header which precedes the array of signatures.
///
UINT32 SignatureHeaderSize;
///
/// Size of each signature.
///
UINT32 SignatureSize;
///
/// Header before the array of signatures. The format of this header is specified
/// by the SignatureType.
/// UINT8 SignatureHeader[SignatureHeaderSize];
///
/// An array of signatures. Each signature is SignatureSize bytes in length.
/// EFI_SIGNATURE_DATA Signatures[][SignatureSize];
///
} EFI_SIGNATURE_LIST;
typedef struct {
///
/// The SHA256 hash of an X.509 certificate's To-Be-Signed contents.
///
EFI_SHA256_HASH ToBeSignedHash;
///
/// The time that the certificate shall be considered to be revoked.
///
EFI_TIME TimeOfRevocation;
} EFI_CERT_X509_SHA256;
typedef struct {
///
/// The SHA384 hash of an X.509 certificate's To-Be-Signed contents.
///
EFI_SHA384_HASH ToBeSignedHash;
///
/// The time that the certificate shall be considered to be revoked.
///
EFI_TIME TimeOfRevocation;
} EFI_CERT_X509_SHA384;
typedef struct {
///
/// The SHA512 hash of an X.509 certificate's To-Be-Signed contents.
///
EFI_SHA512_HASH ToBeSignedHash;
///
/// The time that the certificate shall be considered to be revoked.
///
EFI_TIME TimeOfRevocation;
} EFI_CERT_X509_SHA512;
#pragma pack()
///
/// This identifies a signature containing a SHA-256 hash. The SignatureHeader size shall
/// always be 0. The SignatureSize shall always be 16 (size of SignatureOwner component) +
/// 32 bytes.
///
#define EFI_CERT_SHA256_GUID \
{ \
0xc1c41626, 0x504c, 0x4092, {0xac, 0xa9, 0x41, 0xf9, 0x36, 0x93, 0x43, 0x28} \
}
///
/// This identifies a signature containing an RSA-2048 key. The key (only the modulus
/// since the public key exponent is known to be 0x10001) shall be stored in big-endian
/// order.
/// The SignatureHeader size shall always be 0. The SignatureSize shall always be 16 (size
/// of SignatureOwner component) + 256 bytes.
///
#define EFI_CERT_RSA2048_GUID \
{ \
0x3c5766e8, 0x269c, 0x4e34, {0xaa, 0x14, 0xed, 0x77, 0x6e, 0x85, 0xb3, 0xb6} \
}
///
/// This identifies a signature containing a RSA-2048 signature of a SHA-256 hash. The
/// SignatureHeader size shall always be 0. The SignatureSize shall always be 16 (size of
/// SignatureOwner component) + 256 bytes.
///
#define EFI_CERT_RSA2048_SHA256_GUID \
{ \
0xe2b36190, 0x879b, 0x4a3d, {0xad, 0x8d, 0xf2, 0xe7, 0xbb, 0xa3, 0x27, 0x84} \
}
///
/// This identifies a signature containing a SHA-1 hash. The SignatureSize shall always
/// be 16 (size of SignatureOwner component) + 20 bytes.
///
#define EFI_CERT_SHA1_GUID \
{ \
0x826ca512, 0xcf10, 0x4ac9, {0xb1, 0x87, 0xbe, 0x1, 0x49, 0x66, 0x31, 0xbd} \
}
///
/// TThis identifies a signature containing a RSA-2048 signature of a SHA-1 hash. The
/// SignatureHeader size shall always be 0. The SignatureSize shall always be 16 (size of
/// SignatureOwner component) + 256 bytes.
///
#define EFI_CERT_RSA2048_SHA1_GUID \
{ \
0x67f8444f, 0x8743, 0x48f1, {0xa3, 0x28, 0x1e, 0xaa, 0xb8, 0x73, 0x60, 0x80} \
}
///
/// This identifies a signature based on an X.509 certificate. If the signature is an X.509
/// certificate then verification of the signature of an image should validate the public
/// key certificate in the image using certificate path verification, up to this X.509
/// certificate as a trusted root. The SignatureHeader size shall always be 0. The
/// SignatureSize may vary but shall always be 16 (size of the SignatureOwner component) +
/// the size of the certificate itself.
/// Note: This means that each certificate will normally be in a separate EFI_SIGNATURE_LIST.
///
#define EFI_CERT_X509_GUID \
{ \
0xa5c059a1, 0x94e4, 0x4aa7, {0x87, 0xb5, 0xab, 0x15, 0x5c, 0x2b, 0xf0, 0x72} \
}
///
/// This identifies a signature containing a SHA-224 hash. The SignatureHeader size shall
/// always be 0. The SignatureSize shall always be 16 (size of SignatureOwner component) +
/// 28 bytes.
///
#define EFI_CERT_SHA224_GUID \
{ \
0xb6e5233, 0xa65c, 0x44c9, {0x94, 0x7, 0xd9, 0xab, 0x83, 0xbf, 0xc8, 0xbd} \
}
///
/// This identifies a signature containing a SHA-384 hash. The SignatureHeader size shall
/// always be 0. The SignatureSize shall always be 16 (size of SignatureOwner component) +
/// 48 bytes.
///
#define EFI_CERT_SHA384_GUID \
{ \
0xff3e5307, 0x9fd0, 0x48c9, {0x85, 0xf1, 0x8a, 0xd5, 0x6c, 0x70, 0x1e, 0x1} \
}
///
/// This identifies a signature containing a SHA-512 hash. The SignatureHeader size shall
/// always be 0. The SignatureSize shall always be 16 (size of SignatureOwner component) +
/// 64 bytes.
///
#define EFI_CERT_SHA512_GUID \
{ \
0x93e0fae, 0xa6c4, 0x4f50, {0x9f, 0x1b, 0xd4, 0x1e, 0x2b, 0x89, 0xc1, 0x9a} \
}
///
/// This identifies a signature containing the SHA256 hash of an X.509 certificate's
/// To-Be-Signed contents, and a time of revocation. The SignatureHeader size shall
/// always be 0. The SignatureSize shall always be 16 (size of the SignatureOwner component)
/// + 48 bytes for an EFI_CERT_X509_SHA256 structure. If the TimeOfRevocation is non-zero,
/// the certificate should be considered to be revoked from that time and onwards, and
/// otherwise the certificate shall be considered to always be revoked.
///
#define EFI_CERT_X509_SHA256_GUID \
{ \
0x3bd2a492, 0x96c0, 0x4079, {0xb4, 0x20, 0xfc, 0xf9, 0x8e, 0xf1, 0x03, 0xed } \
}
///
/// This identifies a signature containing the SHA384 hash of an X.509 certificate's
/// To-Be-Signed contents, and a time of revocation. The SignatureHeader size shall
/// always be 0. The SignatureSize shall always be 16 (size of the SignatureOwner component)
/// + 64 bytes for an EFI_CERT_X509_SHA384 structure. If the TimeOfRevocation is non-zero,
/// the certificate should be considered to be revoked from that time and onwards, and
/// otherwise the certificate shall be considered to always be revoked.
///
#define EFI_CERT_X509_SHA384_GUID \
{ \
0x7076876e, 0x80c2, 0x4ee6, {0xaa, 0xd2, 0x28, 0xb3, 0x49, 0xa6, 0x86, 0x5b } \
}
///
/// This identifies a signature containing the SHA512 hash of an X.509 certificate's
/// To-Be-Signed contents, and a time of revocation. The SignatureHeader size shall
/// always be 0. The SignatureSize shall always be 16 (size of the SignatureOwner component)
/// + 80 bytes for an EFI_CERT_X509_SHA512 structure. If the TimeOfRevocation is non-zero,
/// the certificate should be considered to be revoked from that time and onwards, and
/// otherwise the certificate shall be considered to always be revoked.
///
#define EFI_CERT_X509_SHA512_GUID \
{ \
0x446dbf63, 0x2502, 0x4cda, {0xbc, 0xfa, 0x24, 0x65, 0xd2, 0xb0, 0xfe, 0x9d } \
}
///
/// This identifies a signature containing a DER-encoded PKCS #7 version 1.5 [RFC2315]
/// SignedData value.
///
#define EFI_CERT_TYPE_PKCS7_GUID \
{ \
0x4aafd29d, 0x68df, 0x49ee, {0x8a, 0xa9, 0x34, 0x7d, 0x37, 0x56, 0x65, 0xa7} \
}
//***********************************************************************
// Image Execution Information Table Definition
//***********************************************************************
typedef UINT32 EFI_IMAGE_EXECUTION_ACTION;
#define EFI_IMAGE_EXECUTION_AUTHENTICATION 0x00000007
#define EFI_IMAGE_EXECUTION_AUTH_UNTESTED 0x00000000
#define EFI_IMAGE_EXECUTION_AUTH_SIG_FAILED 0x00000001
#define EFI_IMAGE_EXECUTION_AUTH_SIG_PASSED 0x00000002
#define EFI_IMAGE_EXECUTION_AUTH_SIG_NOT_FOUND 0x00000003
#define EFI_IMAGE_EXECUTION_AUTH_SIG_FOUND 0x00000004
#define EFI_IMAGE_EXECUTION_POLICY_FAILED 0x00000005
#define EFI_IMAGE_EXECUTION_INITIALIZED 0x00000008
//
// EFI_IMAGE_EXECUTION_INFO is added to EFI System Configuration Table
// and assigned the GUID EFI_IMAGE_SECURITY_DATABASE_GUID.
//
typedef struct {
///
/// Describes the action taken by the firmware regarding this image.
///
EFI_IMAGE_EXECUTION_ACTION Action;
///
/// Size of all of the entire structure.
///
UINT32 InfoSize;
///
/// If this image was a UEFI device driver (for option ROM, for example) this is the
/// null-terminated, user-friendly name for the device. If the image was for an application,
/// then this is the name of the application. If this cannot be determined, then a simple
/// NULL character should be put in this position.
/// CHAR16 Name[];
///
///
/// For device drivers, this is the device path of the device for which this device driver
/// was intended. In some cases, the driver itself may be stored as part of the system
/// firmware, but this field should record the device's path, not the firmware path. For
/// applications, this is the device path of the application. If this cannot be determined,
/// a simple end-of-path device node should be put in this position.
/// EFI_DEVICE_PATH_PROTOCOL DevicePath;
///
///
/// Zero or more image signatures. If the image contained no signatures,
/// then this field is empty.
/// EFI_SIGNATURE_LIST Signature;
///
} EFI_IMAGE_EXECUTION_INFO;
typedef struct {
///
/// Number of EFI_IMAGE_EXECUTION_INFO structures.
///
UINTN NumberOfImages;
///
/// Number of image instances of EFI_IMAGE_EXECUTION_INFO structures.
///
// EFI_IMAGE_EXECUTION_INFO InformationInfo[]
} EFI_IMAGE_EXECUTION_INFO_TABLE;
extern EFI_GUID gEfiImageSecurityDatabaseGuid;
extern EFI_GUID gEfiCertSha256Guid;
extern EFI_GUID gEfiCertRsa2048Guid;
extern EFI_GUID gEfiCertRsa2048Sha256Guid;
extern EFI_GUID gEfiCertSha1Guid;
extern EFI_GUID gEfiCertRsa2048Sha1Guid;
extern EFI_GUID gEfiCertX509Guid;
extern EFI_GUID gEfiCertSha224Guid;
extern EFI_GUID gEfiCertSha384Guid;
extern EFI_GUID gEfiCertSha512Guid;
extern EFI_GUID gEfiCertX509Sha256Guid;
extern EFI_GUID gEfiCertX509Sha384Guid;
extern EFI_GUID gEfiCertX509Sha512Guid;
extern EFI_GUID gEfiCertPkcs7Guid;
#endif

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/** @file
GUID for MdePkg PCD Token Space
Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _MDEPKG_TOKEN_SPACE_GUID_H_
#define _MDEPKG_TOKEN_SPACE_GUID_H_
#define MDEPKG_TOKEN_SPACE_GUID \
{ \
0x914AEBE7, 0x4635, 0x459b, { 0xAA, 0x1C, 0x11, 0xE2, 0x19, 0xB0, 0x3A, 0x10 } \
}
extern EFI_GUID gEfiMdePkgTokenSpaceGuid;
#endif

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MdePkg/Include/Guid/MemoryAllocationHob.h Normal file
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/** @file
GUIDs for HOBs used in memory allcation
Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
GUIDs introduced in PI Version 1.0.
**/
#ifndef __MEMORY_ALLOCATION_GUID_H__
#define __MEMORY_ALLOCATION_GUID_H__
#define EFI_HOB_MEMORY_ALLOC_BSP_STORE_GUID \
{0x564b33cd, 0xc92a, 0x4593, {0x90, 0xbf, 0x24, 0x73, 0xe4, 0x3c, 0x63, 0x22} };
#define EFI_HOB_MEMORY_ALLOC_STACK_GUID \
{0x4ed4bf27, 0x4092, 0x42e9, {0x80, 0x7d, 0x52, 0x7b, 0x1d, 0x0, 0xc9, 0xbd} }
#define EFI_HOB_MEMORY_ALLOC_MODULE_GUID \
{0xf8e21975, 0x899, 0x4f58, {0xa4, 0xbe, 0x55, 0x25, 0xa9, 0xc6, 0xd7, 0x7a} }
extern EFI_GUID gEfiHobMemoryAllocBspStoreGuid;
extern EFI_GUID gEfiHobMemoryAllocStackGuid;
extern EFI_GUID gEfiHobMemoryAllocModuleGuid;
#endif

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/** @file
GUIDs used for UEFI Memory Attributes Table in the UEFI 2.6 specification.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __UEFI_MEMORY_ATTRIBUTES_TABLE_H__
#define __UEFI_MEMORY_ATTRIBUTES_TABLE_H__
#define EFI_MEMORY_ATTRIBUTES_TABLE_GUID {\
0xdcfa911d, 0x26eb, 0x469f, {0xa2, 0x20, 0x38, 0xb7, 0xdc, 0x46, 0x12, 0x20} \
}
typedef struct {
UINT32 Version;
UINT32 NumberOfEntries;
UINT32 DescriptorSize;
UINT32 Reserved;
//EFI_MEMORY_DESCRIPTOR Entry[1];
} EFI_MEMORY_ATTRIBUTES_TABLE;
#define EFI_MEMORY_ATTRIBUTES_TABLE_VERSION 0x00000001
extern EFI_GUID gEfiMemoryAttributesTableGuid;
#endif

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/** @file
GUID used for MemoryOverwriteRequestControl UEFI variable defined in
TCG Platform Reset Attack Mitigation Specification 1.00.
See http://trustedcomputinggroup.org for the latest specification
The purpose of the MemoryOverwriteRequestControl UEFI variable is to give users (e.g., OS, loader) the ability to
indicate to the platform that secrets are present in memory and that the platform firmware must clear memory upon
a restart. The OS loader should not create the variable. Rather, the firmware is required to create it.
Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _MEMORY_OVERWRITE_CONTROL_DATA_GUID_H_
#define _MEMORY_OVERWRITE_CONTROL_DATA_GUID_H_
#define MEMORY_ONLY_RESET_CONTROL_GUID \
{ \
0xe20939be, 0x32d4, 0x41be, {0xa1, 0x50, 0x89, 0x7f, 0x85, 0xd4, 0x98, 0x29} \
}
///
/// Variable name is "MemoryOverwriteRequestControl" and it is a 1 byte unsigned value.
/// The attributes should be:
/// EFI_VARIABLE_NON_VOLATILE |
/// EFI_VARIABLE_BOOTSERVICE_ACCESS |
/// EFI_VARIABLE_RUNTIME_ACCESS
///
#define MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME L"MemoryOverwriteRequestControl"
///
/// 0 = Firmware MUST clear the MOR bi
/// 1 = Firmware MUST set the MOR bit
///
#define MOR_CLEAR_MEMORY_BIT_MASK 0x01
///
/// 0 = Firmware MAY autodetect a clean shutdown of the Static RTM OS.
/// 1 = Firmware MUST NOT autodetect a clean shutdown of the Static RTM OS.
///
#define MOR_DISABLEAUTODETECT_BIT_MASK 0x10
///
/// MOR field bit offset
///
#define MOR_CLEAR_MEMORY_BIT_OFFSET 0
#define MOR_DISABLEAUTODETECT_BIT_OFFSET 4
/**
Return the ClearMemory bit value 0 or 1.
@param mor 1 byte value that contains ClearMemory and DisableAutoDetect bit.
@return ClearMemory bit value
**/
#define MOR_CLEAR_MEMORY_VALUE(mor) (((UINT8)(mor) & MOR_CLEAR_MEMORY_BIT_MASK) >> MOR_CLEAR_MEMORY_BIT_OFFSET)
/**
Return the DisableAutoDetect bit value 0 or 1.
@param mor 1 byte value that contains ClearMemory and DisableAutoDetect bit.
@return DisableAutoDetect bit value
**/
#define MOR_DISABLE_AUTO_DETECT_VALUE(mor) (((UINT8)(mor) & MOR_DISABLEAUTODETECT_BIT_MASK) >> MOR_DISABLEAUTODETECT_BIT_OFFSET)
extern EFI_GUID gEfiMemoryOverwriteControlDataGuid;
#endif

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/** @file
GUIDs used for MPS entries in the UEFI 2.0 system table
ACPI is the primary means of exporting MPS information to the OS. MPS only was
included to support Itanium-based platform power on. So don't use it if you don't have too.
Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
GUIDs defined in UEFI 2.0 spec.
**/
#ifndef __MPS_GUID_H__
#define __MPS_GUID_H__
#define EFI_MPS_TABLE_GUID \
{ \
0xeb9d2d2f, 0x2d88, 0x11d3, {0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \
}
//
// GUID name defined in spec.
//
#define MPS_TABLE_GUID EFI_MPS_TABLE_GUID
extern EFI_GUID gEfiMpsTableGuid;
#endif

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/** @file
Terminal Device Path Vendor Guid.
Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
GUIDs defined in UEFI 2.0 spec.
**/
#ifndef __PC_ANSI_H__
#define __PC_ANSI_H__
#define EFI_PC_ANSI_GUID \
{ \
0xe0c14753, 0xf9be, 0x11d2, {0x9a, 0x0c, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \
}
#define EFI_VT_100_GUID \
{ \
0xdfa66065, 0xb419, 0x11d3, {0x9a, 0x2d, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \
}
#define EFI_VT_100_PLUS_GUID \
{ \
0x7baec70b, 0x57e0, 0x4c76, {0x8e, 0x87, 0x2f, 0x9e, 0x28, 0x08, 0x83, 0x43 } \
}
#define EFI_VT_UTF8_GUID \
{ \
0xad15a0d6, 0x8bec, 0x4acf, {0xa0, 0x73, 0xd0, 0x1d, 0xe7, 0x7e, 0x2d, 0x88 } \
}
#define DEVICE_PATH_MESSAGING_UART_FLOW_CONTROL \
{ \
0x37499a9d, 0x542f, 0x4c89, {0xa0, 0x26, 0x35, 0xda, 0x14, 0x20, 0x94, 0xe4 } \
}
#define EFI_SAS_DEVICE_PATH_GUID \
{ \
0xd487ddb4, 0x008b, 0x11d9, {0xaf, 0xdc, 0x00, 0x10, 0x83, 0xff, 0xca, 0x4d } \
}
extern EFI_GUID gEfiPcAnsiGuid;
extern EFI_GUID gEfiVT100Guid;
extern EFI_GUID gEfiVT100PlusGuid;
extern EFI_GUID gEfiVTUTF8Guid;
extern EFI_GUID gEfiUartDevicePathGuid;
extern EFI_GUID gEfiSasDevicePathGuid;
#endif

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/** @file
GUIDs used for UEFI Properties Table in the UEFI 2.5 specification.
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __EFI_PROPERTIES_TABLE_H__
#define __EFI_PROPERTIES_TABLE_H__
#define EFI_PROPERTIES_TABLE_GUID {\
0x880aaca3, 0x4adc, 0x4a04, {0x90, 0x79, 0xb7, 0x47, 0x34, 0x8, 0x25, 0xe5} \
}
typedef struct {
UINT32 Version;
UINT32 Length;
UINT64 MemoryProtectionAttribute;
} EFI_PROPERTIES_TABLE;
#define EFI_PROPERTIES_TABLE_VERSION 0x00010000
//
// Memory attribute (Not defined bit is reserved)
//
#define EFI_PROPERTIES_RUNTIME_MEMORY_PROTECTION_NON_EXECUTABLE_PE_DATA 0x1
extern EFI_GUID gEfiPropertiesTableGuid;
#endif

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/** @file
GUIDs used for SAL system table entries in the EFI system table.
SAL System Table contains Itanium-based processor centric information about
the system.
Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
GUIDs defined in UEFI 2.0 spec.
**/
#ifndef __SAL_SYSTEM_TABLE_GUID_H__
#define __SAL_SYSTEM_TABLE_GUID_H__
#define SAL_SYSTEM_TABLE_GUID \
{ \
0xeb9d2d32, 0x2d88, 0x11d3, {0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \
}
extern EFI_GUID gEfiSalSystemTableGuid;
#endif

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/** @file
GUIDs used to locate the SMBIOS tables in the UEFI 2.5 system table.
These GUIDs in the system table are the only legal ways to search for and
locate the SMBIOS tables. Do not search the 0xF0000 segment to find SMBIOS
tables.
Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
GUIDs defined in UEFI 2.5 spec.
**/
#ifndef __SMBIOS_GUID_H__
#define __SMBIOS_GUID_H__
#define SMBIOS_TABLE_GUID \
{ \
0xeb9d2d31, 0x2d88, 0x11d3, {0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \
}
#define SMBIOS3_TABLE_GUID \
{ \
0xf2fd1544, 0x9794, 0x4a2c, {0x99, 0x2e, 0xe5, 0xbb, 0xcf, 0x20, 0xe3, 0x94 } \
}
extern EFI_GUID gEfiSmbiosTableGuid;
extern EFI_GUID gEfiSmbios3TableGuid;
#endif

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/** @file
GUID used to identify id for the caller who is initiating the Status Code.
Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
These GUIDs and structures are defined in UEFI Platform Initialization Specification 1.2
Volume 3: Shared Architectural Elements
**/
#ifndef __PI_STATUS_CODE_DATA_TYPE_ID_GUID_H__
#define __PI_STATUS_CODE_DATA_TYPE_ID_GUID_H__
#include <PiDxe.h>
#include <Protocol/DebugSupport.h>
///
/// Global ID for the EFI_STATUS_CODE_STRING structure
///
#define EFI_STATUS_CODE_DATA_TYPE_STRING_GUID \
{ 0x92D11080, 0x496F, 0x4D95, { 0xBE, 0x7E, 0x03, 0x74, 0x88, 0x38, 0x2B, 0x0A } }
typedef enum {
///
/// A NULL-terminated ASCII string.
///
EfiStringAscii,
///
/// A double NULL-terminated Unicode string.
///
EfiStringUnicode,
///
/// An EFI_STATUS_CODE_STRING_TOKEN representing the string. The actual
/// string can be obtained by querying the HII Database
///
EfiStringToken
} EFI_STRING_TYPE;
///
/// Specifies the format of the data in EFI_STATUS_CODE_STRING_DATA.String.
///
typedef struct {
///
/// The HII package list which contains the string. Handle is a dynamic value that may
/// not be the same for different boots. Type EFI_HII_HANDLE is defined in
/// EFI_HII_DATABASE_PROTOCOL.NewPackageList() in the UEFI Specification.
///
EFI_HII_HANDLE Handle;
///
/// When combined with Handle, the string token can be used to retrieve the string.
/// Type EFI_STRING_ID is defined in EFI_IFR_OP_HEADER in the UEFI Specification.
///
EFI_STRING_ID Token;
} EFI_STATUS_CODE_STRING_TOKEN;
typedef union {
///
/// ASCII formatted string.
///
CHAR8 *Ascii;
///
/// Unicode formatted string.
///
CHAR16 *Unicode;
///
/// HII handle/token pair.
///
EFI_STATUS_CODE_STRING_TOKEN Hii;
} EFI_STATUS_CODE_STRING;
///
/// This data type defines a string type of extended data. A string can accompany
/// any status code. The string can provide additional information about the
/// status code. The string can be ASCII, Unicode, or a Human Interface Infrastructure
/// (HII) token/GUID pair.
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// sizeof (EFI_STATUS_CODE_STRING_DATA) - HeaderSize, and
/// DataHeader.Type should be
/// EFI_STATUS_CODE_DATA_TYPE_STRING_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// Specifies the format of the data in String.
///
EFI_STRING_TYPE StringType;
///
/// A pointer to the extended data. The data follows the format specified by
/// StringType.
///
EFI_STATUS_CODE_STRING String;
} EFI_STATUS_CODE_STRING_DATA;
extern EFI_GUID gEfiStatusCodeDataTypeStringGuid;
///
/// Global ID for the following structures:
/// - EFI_DEVICE_PATH_EXTENDED_DATA
/// - EFI_DEVICE_HANDLE_EXTENDED_DATA
/// - EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA
/// - EFI_COMPUTING_UNIT_VOLTAGE_ERROR_DATA
/// - EFI_COMPUTING_UNIT_MICROCODE_UPDATE_ERROR_DATA
/// - EFI_COMPUTING_UNIT_TIMER_EXPIRED_ERROR_DATA
/// - EFI_HOST_PROCESSOR_MISMATCH_ERROR_DATA
/// - EFI_MEMORY_RANGE_EXTENDED_DATA
/// - EFI_DEBUG_ASSERT_DATA
/// - EFI_STATUS_CODE_EXCEP_EXTENDED_DATA
/// - EFI_STATUS_CODE_START_EXTENDED_DATA
/// - EFI_LEGACY_OPROM_EXTENDED_DATA
///
#define EFI_STATUS_CODE_SPECIFIC_DATA_GUID \
{ 0x335984bd, 0xe805, 0x409a, { 0xb8, 0xf8, 0xd2, 0x7e, 0xce, 0x5f, 0xf7, 0xa6 } }
///
/// Extended data about the device path, which is used for many errors and
/// progress codes to point to the device.
///
/// The device path is used to point to the physical device in case there is more than one device
/// belonging to the same subclass. For example, the system may contain two USB keyboards and one
/// PS/2* keyboard. The driver that parses the status code can use the device path extended data to
/// differentiate between the three. The index field is not useful in this case because there is no standard
/// numbering convention. Device paths are preferred over using device handles because device handles
/// for a given device can change from one boot to another and do not mean anything beyond Boot
/// Services time. In certain cases, the bus driver may not create a device handle for a given device if it
/// detects a critical error. In these cases, the device path extended data can be used to refer to the
/// device, but there may not be any device handles with an instance of
/// EFI_DEVICE_PATH_PROTOCOL that matches DevicePath. The variable device path structure
/// is included in this structure to make it self sufficient.
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA). DataHeader.Size should be the size
/// of variable-length DevicePath, and DataHeader.Size is zero for a virtual
/// device that does not have a device path. DataHeader.Type should be
/// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The device path to the controller or the hardware device. Note that this parameter is a
/// variable-length device path structure and not a pointer to such a structure. This structure is
/// populated only if it is a physical device. For virtual devices, the Size field in DataHeader
/// is set to zero and this field is not populated.
///
// EFI_DEVICE_PATH_PROTOCOL DevicePath;
} EFI_DEVICE_PATH_EXTENDED_DATA;
///
/// Device handle Extended Data. Used for many
/// errors and progress codes to point to the device.
///
/// The handle of the device with which the progress or error code is associated. The handle is
/// guaranteed to be accurate only at the time the status code is reported. Handles are dynamic entities
/// between boots, so handles cannot be considered to be valid if the system has reset subsequent to the
/// status code being reported. Handles may be used to determine a wide variety of useful information
/// about the source of the status code.
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// sizeof (EFI_DEVICE_HANDLE_EXTENDED_DATA) - HeaderSize, and
/// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The device handle.
///
EFI_HANDLE Handle;
} EFI_DEVICE_HANDLE_EXTENDED_DATA;
///
/// This structure defines extended data describing a PCI resource allocation error.
///
/// @par Note:
/// The following structure contains variable-length fields and cannot be defined as a C-style
/// structure.
///
/// This extended data conveys details for a PCI resource allocation failure error. See the PCI
/// specification and the ACPI specification for details on PCI resource allocations and the format for
/// resource descriptors. This error does not detail why the resource allocation failed. It may be due to a
/// bad resource request or a lack of available resources to satisfy a valid request. The variable device
/// path structure and the resource structures are included in this structure to make it self sufficient.
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be sizeof
/// (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// (DevicePathSize + DevicePathSize + DevicePathSize +
/// sizeof(UINT32) + 3 * sizeof (UINT16) ), and DataHeader.Type
/// should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The PCI BAR. Applicable only for PCI devices. Ignored for all other devices.
///
UINT32 Bar;
///
/// DevicePathSize should be zero if it is a virtual device that is not associated with
/// a device path. Otherwise, this parameter is the length of the variable-length
/// DevicePath.
///
UINT16 DevicePathSize;
///
/// Represents the size the ReqRes parameter. ReqResSize should be zero if the
/// requested resources are not provided as a part of extended data.
///
UINT16 ReqResSize;
///
/// Represents the size the AllocRes parameter. AllocResSize should be zero if the
/// allocated resources are not provided as a part of extended data.
///
UINT16 AllocResSize;
///
/// The device path to the controller or the hardware device that did not get the requested
/// resources. Note that this parameter is the variable-length device path structure and not
/// a pointer to this structure.
///
// EFI_DEVICE_PATH_PROTOCOL DevicePath;
///
/// The requested resources in the format of an ACPI 2.0 resource descriptor. This
/// parameter is not a pointer; it is the complete resource descriptor.
///
// UINT8 ReqRes[];
///
/// The allocated resources in the format of an ACPI 2.0 resource descriptor. This
/// parameter is not a pointer; it is the complete resource descriptor.
///
// UINT8 AllocRes[];
} EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA;
///
/// This structure provides a calculation for base-10 representations.
///
/// Not consistent with PI 1.2 Specification.
/// This data type is not defined in the PI 1.2 Specification, but is
/// required by several of the other data structures in this file.
///
typedef struct {
///
/// The INT16 number by which to multiply the base-2 representation.
///
INT16 Value;
///
/// The INT16 number by which to raise the base-2 calculation.
///
INT16 Exponent;
} EFI_EXP_BASE10_DATA;
///
/// This structure provides the voltage at the time of error. It also provides
/// the threshold value indicating the minimum or maximum voltage that is considered
/// an error. If the voltage is less then the threshold, the error indicates that the
/// voltage fell below the minimum acceptable value. If the voltage is greater then the threshold,
/// the error indicates that the voltage rose above the maximum acceptable value.
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// sizeof (EFI_COMPUTING_UNIT_VOLTAGE_ERROR_DATA) -
/// HeaderSize, and DataHeader.Type should be
/// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The voltage value at the time of the error.
///
EFI_EXP_BASE10_DATA Voltage;
///
/// The voltage threshold.
///
EFI_EXP_BASE10_DATA Threshold;
} EFI_COMPUTING_UNIT_VOLTAGE_ERROR_DATA;
///
/// Microcode Update Extended Error Data
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// sizeof (EFI_COMPUTING_UNIT_MICROCODE_UPDATE_ERROR_DATA) -
/// HeaderSize, and DataHeader.Type should be
/// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The version of the microcode update from the header.
///
UINT32 Version;
} EFI_COMPUTING_UNIT_MICROCODE_UPDATE_ERROR_DATA;
///
/// This structure provides details about the computing unit timer expiration error.
/// The timer limit provides the timeout value of the timer prior to expiration.
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// sizeof (EFI_COMPUTING_UNIT_TIMER_EXPIRED_ERROR_DATA) -
/// HeaderSize, and DataHeader.Type should be
/// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The number of seconds that the computing unit timer was configured to expire.
///
EFI_EXP_BASE10_DATA TimerLimit;
} EFI_COMPUTING_UNIT_TIMER_EXPIRED_ERROR_DATA;
///
/// Attribute bits for EFI_HOST_PROCESSOR_MISMATCH_ERROR_DATA.Attributes
/// All other attributes are reserved for future use and must be initialized to 0.
///
///@{
#define EFI_COMPUTING_UNIT_MISMATCH_SPEED 0x0001
#define EFI_COMPUTING_UNIT_MISMATCH_FSB_SPEED 0x0002
#define EFI_COMPUTING_UNIT_MISMATCH_FAMILY 0x0004
#define EFI_COMPUTING_UNIT_MISMATCH_MODEL 0x0008
#define EFI_COMPUTING_UNIT_MISMATCH_STEPPING 0x0010
#define EFI_COMPUTING_UNIT_MISMATCH_CACHE_SIZE 0x0020
#define EFI_COMPUTING_UNIT_MISMATCH_OEM1 0x1000
#define EFI_COMPUTING_UNIT_MISMATCH_OEM2 0x2000
#define EFI_COMPUTING_UNIT_MISMATCH_OEM3 0x4000
#define EFI_COMPUTING_UNIT_MISMATCH_OEM4 0x8000
///@}
///
/// This structure defines extended data for processor mismatch errors.
///
/// This provides information to indicate which processors mismatch, and how they mismatch. The
/// status code contains the instance number of the processor that is in error. This structure's
/// Instance indicates the second processor that does not match. This differentiation allows the
/// consumer to determine which two processors do not match. The Attributes indicate what
/// mismatch is being reported. Because Attributes is a bit field, more than one mismatch can be
/// reported with one error code.
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// sizeof (EFI_ HOST_PROCESSOR_MISMATCH_ERROR_DATA) -
/// HeaderSize , and DataHeader.Type should be
/// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The unit number of the computing unit that does not match.
///
UINT32 Instance;
///
/// The attributes describing the failure.
///
UINT16 Attributes;
} EFI_HOST_PROCESSOR_MISMATCH_ERROR_DATA;
///
/// This structure provides details about the computing unit thermal failure.
///
/// This structure provides the temperature at the time of error. It also provides the threshold value
/// indicating the minimum temperature that is considered an error.
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// sizeof (EFI_COMPUTING_UNIT_THERMAL_ERROR_DATA) -
/// HeaderSize , and DataHeader.Type should be
/// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The thermal value at the time of the error.
///
EFI_EXP_BASE10_DATA Temperature;
///
/// The thermal threshold.
///
EFI_EXP_BASE10_DATA Threshold;
} EFI_COMPUTING_UNIT_THERMAL_ERROR_DATA;
///
/// Enumeration of valid cache types
///
typedef enum {
EfiInitCacheDataOnly,
EfiInitCacheInstrOnly,
EfiInitCacheBoth,
EfiInitCacheUnspecified
} EFI_INIT_CACHE_TYPE;
///
/// Embedded cache init extended data
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// sizeof (EFI_CACHE_INIT_DATA) - HeaderSize , and
/// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The cache level. Starts with 1 for level 1 cache.
///
UINT32 Level;
///
/// The type of cache.
///
EFI_INIT_CACHE_TYPE Type;
} EFI_CACHE_INIT_DATA;
///
///
///
typedef UINT32 EFI_CPU_STATE_CHANGE_CAUSE;
///
/// The reasons that the processor is disabled.
/// Used to fill in EFI_COMPUTING_UNIT_CPU_DISABLED_ERROR_DATA.Cause.
///
///@{
#define EFI_CPU_CAUSE_INTERNAL_ERROR 0x0001
#define EFI_CPU_CAUSE_THERMAL_ERROR 0x0002
#define EFI_CPU_CAUSE_SELFTEST_FAILURE 0x0004
#define EFI_CPU_CAUSE_PREBOOT_TIMEOUT 0x0008
#define EFI_CPU_CAUSE_FAILED_TO_START 0x0010
#define EFI_CPU_CAUSE_CONFIG_ERROR 0x0020
#define EFI_CPU_CAUSE_USER_SELECTION 0x0080
#define EFI_CPU_CAUSE_BY_ASSOCIATION 0x0100
#define EFI_CPU_CAUSE_UNSPECIFIED 0x8000
///@}
///
/// This structure provides information about the disabled computing unit.
///
/// This structure provides details as to why and how the computing unit was disabled. The causes
/// should cover the typical reasons a processor would be disabled. How the processor was disabled is
/// important because there are distinct differences between hardware and software disabling.
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// sizeof (EFI_COMPUTING_UNIT_CPU_DISABLED_ERROR_DATA) -
/// HeaderSize, and DataHeader.Type should be
/// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The reason for disabling the processor.
///
UINT32 Cause;
///
/// TRUE if the processor is disabled via software means such as not listing it in the ACPI tables.
/// Such a processor will respond to Interprocessor Interrupts (IPIs). FALSE if the processor is hardware
/// disabled, which means it is invisible to software and will not respond to IPIs.
///
BOOLEAN SoftwareDisabled;
} EFI_COMPUTING_UNIT_CPU_DISABLED_ERROR_DATA;
///
/// Memory Error Granularity Definition
///
typedef UINT8 EFI_MEMORY_ERROR_GRANULARITY;
///
/// Memory Error Granularities. Used to fill in EFI_MEMORY_EXTENDED_ERROR_DATA.Granularity.
///
///@{
#define EFI_MEMORY_ERROR_OTHER 0x01
#define EFI_MEMORY_ERROR_UNKNOWN 0x02
#define EFI_MEMORY_ERROR_DEVICE 0x03
#define EFI_MEMORY_ERROR_PARTITION 0x04
///@}
///
/// Memory Error Operation Definition
///
typedef UINT8 EFI_MEMORY_ERROR_OPERATION;
///
/// Memory Error Operations. Used to fill in EFI_MEMORY_EXTENDED_ERROR_DATA.Operation.
///
///@{
#define EFI_MEMORY_OPERATION_OTHER 0x01
#define EFI_MEMORY_OPERATION_UNKNOWN 0x02
#define EFI_MEMORY_OPERATION_READ 0x03
#define EFI_MEMORY_OPERATION_WRITE 0x04
#define EFI_MEMORY_OPERATION_PARTIAL_WRITE 0x05
///@}
///
/// This structure provides specific details about the memory error that was detected. It provides
/// enough information so that consumers can identify the exact failure and provides enough
/// information to enable corrective action if necessary.
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// sizeof (EFI_MEMORY_EXTENDED_ERROR_DATA) - HeaderSize, and
/// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The error granularity type.
///
EFI_MEMORY_ERROR_GRANULARITY Granularity;
///
/// The operation that resulted in the error being detected.
///
EFI_MEMORY_ERROR_OPERATION Operation;
///
/// The error syndrome, vendor-specific ECC syndrome, or CRC data associated with
/// the error. If unknown, should be initialized to 0.
/// Inconsistent with specification here:
/// This field in StatusCodes spec0.9 is defined as UINT32, keep code unchanged.
///
UINTN Syndrome;
///
/// The physical address of the error.
///
EFI_PHYSICAL_ADDRESS Address;
///
/// The range, in bytes, within which the error address can be determined.
///
UINTN Resolution;
} EFI_MEMORY_EXTENDED_ERROR_DATA;
///
/// A definition to describe that the operation is performed on multiple devices within the array.
/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device.
///
#define EFI_MULTIPLE_MEMORY_DEVICE_OPERATION 0xfffe
///
/// A definition to describe that the operation is performed on all devices within the array.
/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device.
///
#define EFI_ALL_MEMORY_DEVICE_OPERATION 0xffff
///
/// A definition to describe that the operation is performed on multiple arrays.
/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device.
///
#define EFI_MULTIPLE_MEMORY_ARRAY_OPERATION 0xfffe
///
/// A definition to describe that the operation is performed on all the arrays.
/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device.
///
#define EFI_ALL_MEMORY_ARRAY_OPERATION 0xffff
///
/// This extended data provides some context that consumers can use to locate a DIMM within the
/// overall memory scheme.
///
/// This extended data provides some context that consumers can use to locate a DIMM within the
/// overall memory scheme. The Array and Device numbers may indicate a specific DIMM, or they
/// may be populated with the group definitions in "Related Definitions" below.
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// sizeof (EFI_STATUS_CODE_DIMM_NUMBER) - HeaderSize, and
/// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The memory array number.
///
UINT16 Array;
///
/// The device number within that Array.
///
UINT16 Device;
} EFI_STATUS_CODE_DIMM_NUMBER;
///
/// This structure defines extended data describing memory modules that do not match.
///
/// This extended data may be used to convey the specifics of memory modules that do not match.
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// sizeof (EFI_MEMORY_MODULE_MISMATCH_ERROR_DATA) -
/// HeaderSize, and DataHeader.Type should be
/// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The instance number of the memory module that does not match.
///
EFI_STATUS_CODE_DIMM_NUMBER Instance;
} EFI_MEMORY_MODULE_MISMATCH_ERROR_DATA;
///
/// This structure defines extended data describing a memory range.
///
/// This extended data may be used to convey the specifics of a memory range. Ranges are specified
/// with a start address and a length.
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// sizeof (EFI_MEMORY_RANGE_EXTENDED_DATA) - HeaderSize, and
/// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The starting address of the memory range.
///
EFI_PHYSICAL_ADDRESS Start;
///
/// The length in bytes of the memory range.
///
EFI_PHYSICAL_ADDRESS Length;
} EFI_MEMORY_RANGE_EXTENDED_DATA;
///
/// This structure provides the assert information that is typically associated with a debug assertion failing.
///
/// The data indicates the location of the assertion that failed in the source code. This information
/// includes the file name and line number that are necessary to find the failing assertion in source code.
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// sizeof (EFI_DEBUG_ASSERT_DATA) - HeaderSize , and
/// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The line number of the source file where the fault was generated.
///
UINT32 LineNumber;
///
/// The size in bytes of FileName.
///
UINT32 FileNameSize;
///
/// A pointer to a NULL-terminated ASCII or Unicode string that represents
/// the file name of the source file where the fault was generated.
///
EFI_STATUS_CODE_STRING_DATA *FileName;
} EFI_DEBUG_ASSERT_DATA;
///
/// System Context Data EBC/IA32/IPF
///
typedef union {
///
/// The context of the EBC virtual machine when the exception was generated. Type
/// EFI_SYSTEM_CONTEXT_EBC is defined in EFI_DEBUG_SUPPORT_PROTOCOL
/// in the UEFI Specification.
///
EFI_SYSTEM_CONTEXT_EBC SystemContextEbc;
///
/// The context of the IA-32 processor when the exception was generated. Type
/// EFI_SYSTEM_CONTEXT_IA32 is defined in the
/// EFI_DEBUG_SUPPORT_PROTOCOL in the UEFI Specification.
///
EFI_SYSTEM_CONTEXT_IA32 SystemContextIa32;
///
/// The context of the Itanium(R) processor when the exception was generated. Type
/// EFI_SYSTEM_CONTEXT_IPF is defined in the
/// EFI_DEBUG_SUPPORT_PROTOCOL in the UEFI Specification.
///
EFI_SYSTEM_CONTEXT_IPF SystemContextIpf;
///
/// The context of the X64 processor when the exception was generated. Type
/// EFI_SYSTEM_CONTEXT_X64 is defined in the
/// EFI_DEBUG_SUPPORT_PROTOCOL in the UEFI Specification.
///
EFI_SYSTEM_CONTEXT_X64 SystemContextX64;
///
/// The context of the ARM processor when the exception was generated. Type
/// EFI_SYSTEM_CONTEXT_ARM is defined in the
/// EFI_DEBUG_SUPPORT_PROTOCOL in the UEFI Specification.
///
EFI_SYSTEM_CONTEXT_ARM SystemContextArm;
} EFI_STATUS_CODE_EXCEP_SYSTEM_CONTEXT;
///
/// This structure defines extended data describing a processor exception error.
///
/// This extended data allows the processor context that is present at the time of the exception to be
/// reported with the exception. The format and contents of the context data varies depending on the
/// processor architecture.
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// sizeof (EFI_STATUS_CODE_EXCEP_EXTENDED_DATA) - HeaderSize,
/// and DataHeader.Type should be
/// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The system context.
///
EFI_STATUS_CODE_EXCEP_SYSTEM_CONTEXT Context;
} EFI_STATUS_CODE_EXCEP_EXTENDED_DATA;
///
/// This structure defines extended data describing a call to a driver binding protocol start function.
///
/// This extended data records information about a Start() function call. Start() is a member of
/// the UEFI Driver Binding Protocol.
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// sizeof (EFI_STATUS_CODE_START_EXTENDED_DATA) - HeaderSize,
/// and DataHeader.Type should be
/// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The controller handle.
///
EFI_HANDLE ControllerHandle;
///
/// The driver binding handle.
///
EFI_HANDLE DriverBindingHandle;
///
/// The size of the RemainingDevicePath. It is zero if the Start() function is
/// called with RemainingDevicePath = NULL. The UEFI Specification allows
/// that the Start() function of bus drivers can be called in this way.
///
UINT16 DevicePathSize;
///
/// Matches the RemainingDevicePath parameter being passed to the Start() function.
/// Note that this parameter is the variable-length device path and not a pointer
/// to the device path.
///
// EFI_DEVICE_PATH_PROTOCOL RemainingDevicePath;
} EFI_STATUS_CODE_START_EXTENDED_DATA;
///
/// This structure defines extended data describing a legacy option ROM (OpROM).
///
/// The device handle and ROM image base can be used by consumers to determine which option ROM
/// failed. Due to the black-box nature of legacy option ROMs, the amount of information that can be
/// obtained may be limited.
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// sizeof (EFI_LEGACY_OPROM_EXTENDED_DATA) - HeaderSize, and
/// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The handle corresponding to the device that this legacy option ROM is being invoked.
///
EFI_HANDLE DeviceHandle;
///
/// The base address of the shadowed legacy ROM image. May or may not point to the shadow RAM area.
///
EFI_PHYSICAL_ADDRESS RomImageBase;
} EFI_LEGACY_OPROM_EXTENDED_DATA;
extern EFI_GUID gEfiStatusCodeSpecificDataGuid;
#endif

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/** @file
Guid & data structure used for EFI System Resource Table (ESRT)
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
GUIDs defined in UEFI 2.5 spec.
**/
#ifndef _SYSTEM_RESOURCE_TABLE_H__
#define _SYSTEM_RESOURCE_TABLE_H__
#define EFI_SYSTEM_RESOURCE_TABLE_GUID \
{ \
0xb122a263, 0x3661, 0x4f68, {0x99, 0x29, 0x78, 0xf8, 0xb0, 0xd6, 0x21, 0x80 } \
}
///
/// Current Entry Version
///
#define EFI_SYSTEM_RESOURCE_TABLE_FIRMWARE_RESOURCE_VERSION 1
///
/// Firmware Type Definitions
///
#define ESRT_FW_TYPE_UNKNOWN 0x00000000
#define ESRT_FW_TYPE_SYSTEMFIRMWARE 0x00000001
#define ESRT_FW_TYPE_DEVICEFIRMWARE 0x00000002
#define ESRT_FW_TYPE_UEFIDRIVER 0x00000003
///
/// Last Attempt Status Values
///
#define LAST_ATTEMPT_STATUS_SUCCESS 0x00000000
#define LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL 0x00000001
#define LAST_ATTEMPT_STATUS_ERROR_INSUFFICIENT_RESOURCES 0x00000002
#define LAST_ATTEMPT_STATUS_ERROR_INCORRECT_VERSION 0x00000003
#define LAST_ATTEMPT_STATUS_ERROR_INVALID_FORMAT 0x00000004
#define LAST_ATTEMPT_STATUS_ERROR_AUTH_ERROR 0x00000005
#define LAST_ATTEMPT_STATUS_ERROR_PWR_EVT_AC 0x00000006
#define LAST_ATTEMPT_STATUS_ERROR_PWR_EVT_BATT 0x00000007
typedef struct {
///
/// The firmware class field contains a GUID that identifies a firmware component
/// that can be updated via UpdateCapsule(). This GUID must be unique within all
/// entries of the ESRT.
///
EFI_GUID FwClass;
///
/// Identifies the type of firmware resource.
///
UINT32 FwType;
///
/// The firmware version field represents the current version of the firmware
/// resource, value must always increase as a larger number represents a newer
/// version.
///
UINT32 FwVersion;
///
/// The lowest firmware resource version to which a firmware resource can be
/// rolled back for the given system/device. Generally this is used to protect
/// against known and fixed security issues.
///
UINT32 LowestSupportedFwVersion;
///
/// The capsule flags field contains the CapsuleGuid flags (bits 0- 15) as defined
/// in the EFI_CAPSULE_HEADER that will be set in the capsule header.
///
UINT32 CapsuleFlags;
///
/// The last attempt version field describes the last firmware version for which
/// an update was attempted (uses the same format as Firmware Version).
/// Last Attempt Version is updated each time an UpdateCapsule() is attempted for
/// an ESRT entry and is preserved across reboots (non-volatile). However, in
/// cases where the attempt version is not recorded due to limitations in the
/// update process, the field shall set to zero after a failed update. Similarly,
/// in the case of a removable device, this value is set to 0 in cases where the
/// device has not been updated since being added to the system.
///
UINT32 LastAttemptVersion;
///
/// The last attempt status field describes the result of the last firmware update
/// attempt for the firmware resource entry.
/// LastAttemptStatus is updated each time an UpdateCapsule() is attempted for an
/// ESRT entry and is preserved across reboots (non-volatile).
/// If a firmware update has never been attempted or is unknown, for example after
/// fresh insertion of a removable device, LastAttemptStatus must be set to Success.
///
UINT32 LastAttemptStatus;
} EFI_SYSTEM_RESOURCE_ENTRY;
typedef struct {
///
/// The number of firmware resources in the table, must not be zero.
///
UINT32 FwResourceCount;
///
/// The maximum number of resource array entries that can be within the table
/// without reallocating the table, must not be zero.
///
UINT32 FwResourceCountMax;
///
/// The version of the EFI_SYSTEM_RESOURCE_ENTRY entities used in this table.
/// This field should be set to 1.
///
UINT64 FwResourceVersion;
///
/// Array of EFI_SYSTEM_RESOURCE_ENTRY
///
//EFI_SYSTEM_RESOURCE_ENTRY Entries[];
} EFI_SYSTEM_RESOURCE_TABLE;
extern EFI_GUID gEfiSystemResourceTableGuid;
#endif

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/** @file
GUID for system configuration table entry that points to the table
in case an entity in DXE wishes to update/change the vector table contents.
Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
GUID defined in PI 1.2.1 spec.
**/
#ifndef __EFI_VECTOR_HANDOFF_TABLE_H__
#define __EFI_VECTOR_HANDOFF_TABLE_H__
#include <Ppi/VectorHandoffInfo.h>
//
// System configuration table entry that points to the table
// in case an entity in DXE wishes to update/change the vector
// table contents.
//
#define EFI_VECTOR_HANDOF_TABLE_GUID \
{ 0x996ec11c, 0x5397, 0x4e73, { 0xb5, 0x8f, 0x82, 0x7e, 0x52, 0x90, 0x6d, 0xef }}
extern EFI_GUID gEfiVectorHandoffTableGuid;
#endif

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/** @file
GUID for UEFI WIN_CERTIFICATE structure.
Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
GUID defined in UEFI 2.0 spec.
**/
#ifndef __EFI_WIN_CERTIFICATE_H__
#define __EFI_WIN_CERTIFICATE_H__
//
// _WIN_CERTIFICATE.wCertificateType
//
#define WIN_CERT_TYPE_PKCS_SIGNED_DATA 0x0002
#define WIN_CERT_TYPE_EFI_PKCS115 0x0EF0
#define WIN_CERT_TYPE_EFI_GUID 0x0EF1
///
/// The WIN_CERTIFICATE structure is part of the PE/COFF specification.
///
typedef struct {
///
/// The length of the entire certificate,
/// including the length of the header, in bytes.
///
UINT32 dwLength;
///
/// The revision level of the WIN_CERTIFICATE
/// structure. The current revision level is 0x0200.
///
UINT16 wRevision;
///
/// The certificate type. See WIN_CERT_TYPE_xxx for the UEFI
/// certificate types. The UEFI specification reserves the range of
/// certificate type values from 0x0EF0 to 0x0EFF.
///
UINT16 wCertificateType;
///
/// The following is the actual certificate. The format of
/// the certificate depends on wCertificateType.
///
/// UINT8 bCertificate[ANYSIZE_ARRAY];
///
} WIN_CERTIFICATE;
///
/// WIN_CERTIFICATE_UEFI_GUID.CertType
///
#define EFI_CERT_TYPE_RSA2048_SHA256_GUID \
{0xa7717414, 0xc616, 0x4977, {0x94, 0x20, 0x84, 0x47, 0x12, 0xa7, 0x35, 0xbf } }
///
/// WIN_CERTIFICATE_UEFI_GUID.CertData
///
typedef struct {
EFI_GUID HashType;
UINT8 PublicKey[256];
UINT8 Signature[256];
} EFI_CERT_BLOCK_RSA_2048_SHA256;
///
/// Certificate which encapsulates a GUID-specific digital signature
///
typedef struct {
///
/// This is the standard WIN_CERTIFICATE header, where
/// wCertificateType is set to WIN_CERT_TYPE_EFI_GUID.
///
WIN_CERTIFICATE Hdr;
///
/// This is the unique id which determines the
/// format of the CertData. .
///
EFI_GUID CertType;
///
/// The following is the certificate data. The format of
/// the data is determined by the CertType.
/// If CertType is EFI_CERT_TYPE_RSA2048_SHA256_GUID,
/// the CertData will be EFI_CERT_BLOCK_RSA_2048_SHA256 structure.
///
UINT8 CertData[1];
} WIN_CERTIFICATE_UEFI_GUID;
///
/// Certificate which encapsulates the RSASSA_PKCS1-v1_5 digital signature.
///
/// The WIN_CERTIFICATE_UEFI_PKCS1_15 structure is derived from
/// WIN_CERTIFICATE and encapsulate the information needed to
/// implement the RSASSA-PKCS1-v1_5 digital signature algorithm as
/// specified in RFC2437.
///
typedef struct {
///
/// This is the standard WIN_CERTIFICATE header, where
/// wCertificateType is set to WIN_CERT_TYPE_UEFI_PKCS1_15.
///
WIN_CERTIFICATE Hdr;
///
/// This is the hashing algorithm which was performed on the
/// UEFI executable when creating the digital signature.
///
EFI_GUID HashAlgorithm;
///
/// The following is the actual digital signature. The
/// size of the signature is the same size as the key
/// (1024-bit key is 128 bytes) and can be determined by
/// subtracting the length of the other parts of this header
/// from the total length of the certificate as found in
/// Hdr.dwLength.
///
/// UINT8 Signature[];
///
} WIN_CERTIFICATE_EFI_PKCS1_15;
extern EFI_GUID gEfiCertTypeRsa2048Sha256Guid;
#endif

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/** @file
Processor or Compiler specific defines and types for IA-32 architecture.
Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __PROCESSOR_BIND_H__
#define __PROCESSOR_BIND_H__
///
/// Define the processor type so other code can make processor based choices.
///
#define MDE_CPU_IA32
//
// Make sure we are using the correct packing rules per EFI specification
//
#if !defined(__GNUC__)
#pragma pack()
#endif
#if defined(__INTEL_COMPILER)
//
// Disable ICC's remark #869: "Parameter" was never referenced warning.
// This is legal ANSI C code so we disable the remark that is turned on with -Wall
//
#pragma warning ( disable : 869 )
//
// Disable ICC's remark #1418: external function definition with no prior declaration.
// This is legal ANSI C code so we disable the remark that is turned on with /W4
//
#pragma warning ( disable : 1418 )
//
// Disable ICC's remark #1419: external declaration in primary source file
// This is legal ANSI C code so we disable the remark that is turned on with /W4
//
#pragma warning ( disable : 1419 )
//
// Disable ICC's remark #593: "Variable" was set but never used.
// This is legal ANSI C code so we disable the remark that is turned on with /W4
//
#pragma warning ( disable : 593 )
#endif
#if defined(_MSC_EXTENSIONS)
//
// Disable warning that make it impossible to compile at /W4
// This only works for Microsoft* tools
//
//
// Disabling bitfield type checking warnings.
//
#pragma warning ( disable : 4214 )
//
// Disabling the unreferenced formal parameter warnings.
//
#pragma warning ( disable : 4100 )
//
// Disable slightly different base types warning as CHAR8 * can not be set
// to a constant string.
//
#pragma warning ( disable : 4057 )
//
// ASSERT(FALSE) or while (TRUE) are legal constructs so suppress this warning
//
#pragma warning ( disable : 4127 )
//
// This warning is caused by functions defined but not used. For precompiled header only.
//
#pragma warning ( disable : 4505 )
//
// This warning is caused by empty (after preprocessing) source file. For precompiled header only.
//
#pragma warning ( disable : 4206 )
#if _MSC_VER == 1800 || _MSC_VER == 1900
//
// Disable these warnings for VS2013.
//
//
// This warning is for potentially uninitialized local variable, and it may cause false
// positive issues in VS2013 and VS2015 build
//
#pragma warning ( disable : 4701 )
//
// This warning is for potentially uninitialized local pointer variable, and it may cause
// false positive issues in VS2013 and VS2015 build
//
#pragma warning ( disable : 4703 )
#endif
#endif
#if defined(_MSC_EXTENSIONS)
//
// use Microsoft C compiler dependent integer width types
//
///
/// 8-byte unsigned value.
///
typedef unsigned __int64 UINT64;
///
/// 8-byte signed value.
///
typedef __int64 INT64;
///
/// 4-byte unsigned value.
///
typedef unsigned __int32 UINT32;
///
/// 4-byte signed value.
///
typedef __int32 INT32;
///
/// 2-byte unsigned value.
///
typedef unsigned short UINT16;
///
/// 2-byte Character. Unless otherwise specified all strings are stored in the
/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.
///
typedef unsigned short CHAR16;
///
/// 2-byte signed value.
///
typedef short INT16;
///
/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other
/// values are undefined.
///
typedef unsigned char BOOLEAN;
///
/// 1-byte unsigned value.
///
typedef unsigned char UINT8;
///
/// 1-byte Character.
///
typedef char CHAR8;
///
/// 1-byte signed value.
///
typedef signed char INT8;
#else
///
/// 8-byte unsigned value.
///
typedef unsigned long long UINT64;
///
/// 8-byte signed value.
///
typedef long long INT64;
///
/// 4-byte unsigned value.
///
typedef unsigned int UINT32;
///
/// 4-byte signed value.
///
typedef int INT32;
///
/// 2-byte unsigned value.
///
typedef unsigned short UINT16;
///
/// 2-byte Character. Unless otherwise specified all strings are stored in the
/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.
///
typedef unsigned short CHAR16;
///
/// 2-byte signed value.
///
typedef short INT16;
///
/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other
/// values are undefined.
///
typedef unsigned char BOOLEAN;
///
/// 1-byte unsigned value.
///
typedef unsigned char UINT8;
///
/// 1-byte Character
///
typedef char CHAR8;
///
/// 1-byte signed value
///
typedef signed char INT8;
#endif
///
/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions;
/// 8 bytes on supported 64-bit processor instructions.)
///
typedef UINT32 UINTN;
///
/// Signed value of native width. (4 bytes on supported 32-bit processor instructions;
/// 8 bytes on supported 64-bit processor instructions.)
///
typedef INT32 INTN;
//
// Processor specific defines
//
///
/// A value of native width with the highest bit set.
///
#define MAX_BIT 0x80000000
///
/// A value of native width with the two highest bits set.
///
#define MAX_2_BITS 0xC0000000
///
/// Maximum legal IA-32 address.
///
#define MAX_ADDRESS 0xFFFFFFFF
///
/// Maximum legal IA-32 INTN and UINTN values.
///
#define MAX_INTN ((INTN)0x7FFFFFFF)
#define MAX_UINTN ((UINTN)0xFFFFFFFF)
///
/// The stack alignment required for IA-32.
///
#define CPU_STACK_ALIGNMENT sizeof(UINTN)
///
/// Page allocation granularity for IA-32.
///
#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)
#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000)
//
// Modifier to ensure that all protocol member functions and EFI intrinsics
// use the correct C calling convention. All protocol member functions and
// EFI intrinsics are required to modify their member functions with EFIAPI.
//
#ifdef EFIAPI
///
/// If EFIAPI is already defined, then we use that definition.
///
#elif defined(_MSC_EXTENSIONS)
///
/// Microsoft* compiler specific method for EFIAPI calling convention.
///
#define EFIAPI __cdecl
#elif defined(__GNUC__)
///
/// GCC specific method for EFIAPI calling convention.
///
#define EFIAPI __attribute__((cdecl))
#else
///
/// The default for a non Microsoft* or GCC compiler is to assume the EFI ABI
/// is the standard.
///
#define EFIAPI
#endif
#if defined(__GNUC__)
///
/// For GNU assembly code, .global or .globl can declare global symbols.
/// Define this macro to unify the usage.
///
#define ASM_GLOBAL .globl
#endif
/**
Return the pointer to the first instruction of a function given a function pointer.
On IA-32 CPU architectures, these two pointer values are the same,
so the implementation of this macro is very simple.
@param FunctionPointer A pointer to a function.
@return The pointer to the first instruction of a function given a function pointer.
**/
#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)
#ifndef __USER_LABEL_PREFIX__
#define __USER_LABEL_PREFIX__ _
#endif
#endif

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/** @file
This file contains the latest ACPI definitions that are
consumed by drivers that do not care about ACPI versions.
Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _ACPI_H_
#define _ACPI_H_
#include <IndustryStandard/Acpi61.h>
#endif

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/** @file
ACPI 1.0b definitions from the ACPI Specification, revision 1.0b
Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _ACPI_1_0_H_
#define _ACPI_1_0_H_
#include <IndustryStandard/AcpiAml.h>
///
/// Common table header, this prefaces all ACPI tables, including FACS, but
/// excluding the RSD PTR structure.
///
typedef struct {
UINT32 Signature;
UINT32 Length;
} EFI_ACPI_COMMON_HEADER;
#pragma pack(1)
///
/// The common ACPI description table header. This structure prefaces most ACPI tables.
///
typedef struct {
UINT32 Signature;
UINT32 Length;
UINT8 Revision;
UINT8 Checksum;
UINT8 OemId[6];
UINT64 OemTableId;
UINT32 OemRevision;
UINT32 CreatorId;
UINT32 CreatorRevision;
} EFI_ACPI_DESCRIPTION_HEADER;
#pragma pack()
//
// Define for Desriptor
//
#define ACPI_SMALL_ITEM_FLAG 0x00
#define ACPI_LARGE_ITEM_FLAG 0x01
//
// Small Item Descriptor Name
//
#define ACPI_SMALL_IRQ_DESCRIPTOR_NAME 0x04
#define ACPI_SMALL_DMA_DESCRIPTOR_NAME 0x05
#define ACPI_SMALL_START_DEPENDENT_DESCRIPTOR_NAME 0x06
#define ACPI_SMALL_END_DEPENDENT_DESCRIPTOR_NAME 0x07
#define ACPI_SMALL_IO_PORT_DESCRIPTOR_NAME 0x08
#define ACPI_SMALL_FIXED_IO_PORT_DESCRIPTOR_NAME 0x09
#define ACPI_SMALL_VENDOR_DEFINED_DESCRIPTOR_NAME 0x0E
#define ACPI_SMALL_END_TAG_DESCRIPTOR_NAME 0x0F
//
// Large Item Descriptor Name
//
#define ACPI_LARGE_24_BIT_MEMORY_RANGE_DESCRIPTOR_NAME 0x01
#define ACPI_LARGE_VENDOR_DEFINED_DESCRIPTOR_NAME 0x04
#define ACPI_LARGE_32_BIT_MEMORY_RANGE_DESCRIPTOR_NAME 0x05
#define ACPI_LARGE_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR_NAME 0x06
#define ACPI_LARGE_DWORD_ADDRESS_SPACE_DESCRIPTOR_NAME 0x07
#define ACPI_LARGE_WORD_ADDRESS_SPACE_DESCRIPTOR_NAME 0x08
#define ACPI_LARGE_EXTENDED_IRQ_DESCRIPTOR_NAME 0x09
#define ACPI_LARGE_QWORD_ADDRESS_SPACE_DESCRIPTOR_NAME 0x0A
//
// Small Item Descriptor Value
//
#define ACPI_IRQ_NOFLAG_DESCRIPTOR 0x22
#define ACPI_IRQ_DESCRIPTOR 0x23
#define ACPI_DMA_DESCRIPTOR 0x2A
#define ACPI_START_DEPENDENT_DESCRIPTOR 0x30
#define ACPI_START_DEPENDENT_EX_DESCRIPTOR 0x31
#define ACPI_END_DEPENDENT_DESCRIPTOR 0x38
#define ACPI_IO_PORT_DESCRIPTOR 0x47
#define ACPI_FIXED_LOCATION_IO_PORT_DESCRIPTOR 0x4B
#define ACPI_END_TAG_DESCRIPTOR 0x79
//
// Large Item Descriptor Value
//
#define ACPI_24_BIT_MEMORY_RANGE_DESCRIPTOR 0x81
#define ACPI_32_BIT_MEMORY_RANGE_DESCRIPTOR 0x85
#define ACPI_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR 0x86
#define ACPI_DWORD_ADDRESS_SPACE_DESCRIPTOR 0x87
#define ACPI_WORD_ADDRESS_SPACE_DESCRIPTOR 0x88
#define ACPI_EXTENDED_INTERRUPT_DESCRIPTOR 0x89
#define ACPI_QWORD_ADDRESS_SPACE_DESCRIPTOR 0x8A
#define ACPI_ADDRESS_SPACE_DESCRIPTOR 0x8A
//
// Resource Type
//
#define ACPI_ADDRESS_SPACE_TYPE_MEM 0x00
#define ACPI_ADDRESS_SPACE_TYPE_IO 0x01
#define ACPI_ADDRESS_SPACE_TYPE_BUS 0x02
///
/// Power Management Timer frequency is fixed at 3.579545MHz.
///
#define ACPI_TIMER_FREQUENCY 3579545
//
// Ensure proper structure formats
//
#pragma pack(1)
///
/// The commond definition of QWORD, DWORD, and WORD
/// Address Space Descriptors.
///
typedef PACKED struct {
UINT8 Desc;
UINT16 Len;
UINT8 ResType;
UINT8 GenFlag;
UINT8 SpecificFlag;
UINT64 AddrSpaceGranularity;
UINT64 AddrRangeMin;
UINT64 AddrRangeMax;
UINT64 AddrTranslationOffset;
UINT64 AddrLen;
} EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR;
typedef PACKED union {
UINT8 Byte;
PACKED struct {
UINT8 Length : 3;
UINT8 Name : 4;
UINT8 Type : 1;
} Bits;
} ACPI_SMALL_RESOURCE_HEADER;
typedef PACKED struct {
PACKED union {
UINT8 Byte;
PACKED struct {
UINT8 Name : 7;
UINT8 Type : 1;
}Bits;
} Header;
UINT16 Length;
} ACPI_LARGE_RESOURCE_HEADER;
///
/// IRQ Descriptor.
///
typedef PACKED struct {
ACPI_SMALL_RESOURCE_HEADER Header;
UINT16 Mask;
} EFI_ACPI_IRQ_NOFLAG_DESCRIPTOR;
///
/// IRQ Descriptor.
///
typedef PACKED struct {
ACPI_SMALL_RESOURCE_HEADER Header;
UINT16 Mask;
UINT8 Information;
} EFI_ACPI_IRQ_DESCRIPTOR;
///
/// DMA Descriptor.
///
typedef PACKED struct {
ACPI_SMALL_RESOURCE_HEADER Header;
UINT8 ChannelMask;
UINT8 Information;
} EFI_ACPI_DMA_DESCRIPTOR;
///
/// I/O Port Descriptor
///
typedef PACKED struct {
ACPI_SMALL_RESOURCE_HEADER Header;
UINT8 Information;
UINT16 BaseAddressMin;
UINT16 BaseAddressMax;
UINT8 Alignment;
UINT8 Length;
} EFI_ACPI_IO_PORT_DESCRIPTOR;
///
/// Fixed Location I/O Port Descriptor.
///
typedef PACKED struct {
ACPI_SMALL_RESOURCE_HEADER Header;
UINT16 BaseAddress;
UINT8 Length;
} EFI_ACPI_FIXED_LOCATION_IO_PORT_DESCRIPTOR;
///
/// 24-Bit Memory Range Descriptor
///
typedef PACKED struct {
ACPI_LARGE_RESOURCE_HEADER Header;
UINT8 Information;
UINT16 BaseAddressMin;
UINT16 BaseAddressMax;
UINT16 Alignment;
UINT16 Length;
} EFI_ACPI_24_BIT_MEMORY_RANGE_DESCRIPTOR;
///
/// 32-Bit Memory Range Descriptor
///
typedef PACKED struct {
ACPI_LARGE_RESOURCE_HEADER Header;
UINT8 Information;
UINT32 BaseAddressMin;
UINT32 BaseAddressMax;
UINT32 Alignment;
UINT32 Length;
} EFI_ACPI_32_BIT_MEMORY_RANGE_DESCRIPTOR;
///
/// Fixed 32-Bit Fixed Memory Range Descriptor
///
typedef PACKED struct {
ACPI_LARGE_RESOURCE_HEADER Header;
UINT8 Information;
UINT32 BaseAddress;
UINT32 Length;
} EFI_ACPI_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR;
///
/// QWORD Address Space Descriptor
///
typedef PACKED struct {
ACPI_LARGE_RESOURCE_HEADER Header;
UINT8 ResType;
UINT8 GenFlag;
UINT8 SpecificFlag;
UINT64 AddrSpaceGranularity;
UINT64 AddrRangeMin;
UINT64 AddrRangeMax;
UINT64 AddrTranslationOffset;
UINT64 AddrLen;
} EFI_ACPI_QWORD_ADDRESS_SPACE_DESCRIPTOR;
///
/// DWORD Address Space Descriptor
///
typedef PACKED struct {
ACPI_LARGE_RESOURCE_HEADER Header;
UINT8 ResType;
UINT8 GenFlag;
UINT8 SpecificFlag;
UINT32 AddrSpaceGranularity;
UINT32 AddrRangeMin;
UINT32 AddrRangeMax;
UINT32 AddrTranslationOffset;
UINT32 AddrLen;
} EFI_ACPI_DWORD_ADDRESS_SPACE_DESCRIPTOR;
///
/// WORD Address Space Descriptor
///
typedef PACKED struct {
ACPI_LARGE_RESOURCE_HEADER Header;
UINT8 ResType;
UINT8 GenFlag;
UINT8 SpecificFlag;
UINT16 AddrSpaceGranularity;
UINT16 AddrRangeMin;
UINT16 AddrRangeMax;
UINT16 AddrTranslationOffset;
UINT16 AddrLen;
} EFI_ACPI_WORD_ADDRESS_SPACE_DESCRIPTOR;
///
/// Extended Interrupt Descriptor
///
typedef PACKED struct {
ACPI_LARGE_RESOURCE_HEADER Header;
UINT8 InterruptVectorFlags;
UINT8 InterruptTableLength;
UINT32 InterruptNumber[1];
} EFI_ACPI_EXTENDED_INTERRUPT_DESCRIPTOR;
#pragma pack()
///
/// The End tag identifies an end of resource data.
///
typedef struct {
UINT8 Desc;
UINT8 Checksum;
} EFI_ACPI_END_TAG_DESCRIPTOR;
//
// General use definitions
//
#define EFI_ACPI_RESERVED_BYTE 0x00
#define EFI_ACPI_RESERVED_WORD 0x0000
#define EFI_ACPI_RESERVED_DWORD 0x00000000
#define EFI_ACPI_RESERVED_QWORD 0x0000000000000000
//
// Resource Type Specific Flags
// Ref ACPI specification 6.4.3.5.5
//
// Bit [0] : Write Status, _RW
//
#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_READ_WRITE (1 << 0)
#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_READ_ONLY (0 << 0)
//
// Bit [2:1] : Memory Attributes, _MEM
//
#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_NON_CACHEABLE (0 << 1)
#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE (1 << 1)
#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_WRITE_COMBINING (2 << 1)
#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE (3 << 1)
//
// Bit [4:3] : Memory Attributes, _MTP
//
#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_MEMORY (0 << 3)
#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_RESERVED (1 << 3)
#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_ACPI (2 << 3)
#define EFI_APCI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_NVS (3 << 3)
//
// Bit [5] : Memory to I/O Translation, _TTP
//
#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_TYPE_TRANSLATION (1 << 5)
#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_TYPE_STATIC (0 << 5)
//
// IRQ Information
// Ref ACPI specification 6.4.2.1
//
#define EFI_ACPI_IRQ_SHARABLE_MASK 0x10
#define EFI_ACPI_IRQ_SHARABLE 0x10
#define EFI_ACPI_IRQ_POLARITY_MASK 0x08
#define EFI_ACPI_IRQ_HIGH_TRUE 0x00
#define EFI_ACPI_IRQ_LOW_FALSE 0x08
#define EFI_ACPI_IRQ_MODE 0x01
#define EFI_ACPI_IRQ_LEVEL_TRIGGERED 0x00
#define EFI_ACPI_IRQ_EDGE_TRIGGERED 0x01
//
// DMA Information
// Ref ACPI specification 6.4.2.2
//
#define EFI_ACPI_DMA_SPEED_TYPE_MASK 0x60
#define EFI_ACPI_DMA_SPEED_TYPE_COMPATIBILITY 0x00
#define EFI_ACPI_DMA_SPEED_TYPE_A 0x20
#define EFI_ACPI_DMA_SPEED_TYPE_B 0x40
#define EFI_ACPI_DMA_SPEED_TYPE_F 0x60
#define EFI_ACPI_DMA_BUS_MASTER_MASK 0x04
#define EFI_ACPI_DMA_BUS_MASTER 0x04
#define EFI_ACPI_DMA_TRANSFER_TYPE_MASK 0x03
#define EFI_ACPI_DMA_TRANSFER_TYPE_8_BIT 0x00
#define EFI_ACPI_DMA_TRANSFER_TYPE_8_BIT_AND_16_BIT 0x01
#define EFI_ACPI_DMA_TRANSFER_TYPE_16_BIT 0x10
//
// IO Information
// Ref ACPI specification 6.4.2.5
//
#define EFI_ACPI_IO_DECODE_MASK 0x01
#define EFI_ACPI_IO_DECODE_16_BIT 0x01
#define EFI_ACPI_IO_DECODE_10_BIT 0x00
//
// Memory Information
// Ref ACPI specification 6.4.3.4
//
#define EFI_ACPI_MEMORY_WRITE_STATUS_MASK 0x01
#define EFI_ACPI_MEMORY_WRITABLE 0x01
#define EFI_ACPI_MEMORY_NON_WRITABLE 0x00
//
// Ensure proper structure formats
//
#pragma pack(1)
//
// ACPI 1.0b table structures
//
///
/// Root System Description Pointer Structure.
///
typedef struct {
UINT64 Signature;
UINT8 Checksum;
UINT8 OemId[6];
UINT8 Reserved;
UINT32 RsdtAddress;
} EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
//
// Root System Description Table
// No definition needed as it is a common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
//
///
/// RSDT Revision (as defined in ACPI 1.0b specification).
///
#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
///
/// Fixed ACPI Description Table Structure (FADT).
///
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
UINT32 FirmwareCtrl;
UINT32 Dsdt;
UINT8 IntModel;
UINT8 Reserved1;
UINT16 SciInt;
UINT32 SmiCmd;
UINT8 AcpiEnable;
UINT8 AcpiDisable;
UINT8 S4BiosReq;
UINT8 Reserved2;
UINT32 Pm1aEvtBlk;
UINT32 Pm1bEvtBlk;
UINT32 Pm1aCntBlk;
UINT32 Pm1bCntBlk;
UINT32 Pm2CntBlk;
UINT32 PmTmrBlk;
UINT32 Gpe0Blk;
UINT32 Gpe1Blk;
UINT8 Pm1EvtLen;
UINT8 Pm1CntLen;
UINT8 Pm2CntLen;
UINT8 PmTmLen;
UINT8 Gpe0BlkLen;
UINT8 Gpe1BlkLen;
UINT8 Gpe1Base;
UINT8 Reserved3;
UINT16 PLvl2Lat;
UINT16 PLvl3Lat;
UINT16 FlushSize;
UINT16 FlushStride;
UINT8 DutyOffset;
UINT8 DutyWidth;
UINT8 DayAlrm;
UINT8 MonAlrm;
UINT8 Century;
UINT8 Reserved4;
UINT8 Reserved5;
UINT8 Reserved6;
UINT32 Flags;
} EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE;
///
/// FADT Version (as defined in ACPI 1.0b specification).
///
#define EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x01
#define EFI_ACPI_1_0_INT_MODE_DUAL_PIC 0
#define EFI_ACPI_1_0_INT_MODE_MULTIPLE_APIC 1
//
// Fixed ACPI Description Table Fixed Feature Flags
// All other bits are reserved and must be set to 0.
//
#define EFI_ACPI_1_0_WBINVD BIT0
#define EFI_ACPI_1_0_WBINVD_FLUSH BIT1
#define EFI_ACPI_1_0_PROC_C1 BIT2
#define EFI_ACPI_1_0_P_LVL2_UP BIT3
#define EFI_ACPI_1_0_PWR_BUTTON BIT4
#define EFI_ACPI_1_0_SLP_BUTTON BIT5
#define EFI_ACPI_1_0_FIX_RTC BIT6
#define EFI_ACPI_1_0_RTC_S4 BIT7
#define EFI_ACPI_1_0_TMR_VAL_EXT BIT8
#define EFI_ACPI_1_0_DCK_CAP BIT9
///
/// Firmware ACPI Control Structure.
///
typedef struct {
UINT32 Signature;
UINT32 Length;
UINT32 HardwareSignature;
UINT32 FirmwareWakingVector;
UINT32 GlobalLock;
UINT32 Flags;
UINT8 Reserved[40];
} EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
///
/// Firmware Control Structure Feature Flags.
/// All other bits are reserved and must be set to 0.
///
#define EFI_ACPI_1_0_S4BIOS_F BIT0
///
/// Multiple APIC Description Table header definition. The rest of the table
/// must be defined in a platform-specific manner.
///
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
UINT32 LocalApicAddress;
UINT32 Flags;
} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
///
/// MADT Revision (as defined in ACPI 1.0b specification).
///
#define EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x01
///
/// Multiple APIC Flags
/// All other bits are reserved and must be set to 0.
///
#define EFI_ACPI_1_0_PCAT_COMPAT BIT0
//
// Multiple APIC Description Table APIC structure types
// All other values between 0x05 an 0xFF are reserved and
// will be ignored by OSPM.
//
#define EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC 0x00
#define EFI_ACPI_1_0_IO_APIC 0x01
#define EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE 0x02
#define EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03
#define EFI_ACPI_1_0_LOCAL_APIC_NMI 0x04
//
// APIC Structure Definitions
//
///
/// Processor Local APIC Structure Definition.
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT8 AcpiProcessorId;
UINT8 ApicId;
UINT32 Flags;
} EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
///
/// Local APIC Flags. All other bits are reserved and must be 0.
///
#define EFI_ACPI_1_0_LOCAL_APIC_ENABLED BIT0
///
/// IO APIC Structure.
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT8 IoApicId;
UINT8 Reserved;
UINT32 IoApicAddress;
UINT32 SystemVectorBase;
} EFI_ACPI_1_0_IO_APIC_STRUCTURE;
///
/// Interrupt Source Override Structure.
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT8 Bus;
UINT8 Source;
UINT32 GlobalSystemInterruptVector;
UINT16 Flags;
} EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
///
/// Non-Maskable Interrupt Source Structure.
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT16 Flags;
UINT32 GlobalSystemInterruptVector;
} EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
///
/// Local APIC NMI Structure.
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT8 AcpiProcessorId;
UINT16 Flags;
UINT8 LocalApicInti;
} EFI_ACPI_1_0_LOCAL_APIC_NMI_STRUCTURE;
///
/// Smart Battery Description Table (SBST)
///
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
UINT32 WarningEnergyLevel;
UINT32 LowEnergyLevel;
UINT32 CriticalEnergyLevel;
} EFI_ACPI_1_0_SMART_BATTERY_DESCRIPTION_TABLE;
//
// Known table signatures
//
///
/// "RSD PTR " Root System Description Pointer.
///
#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
///
/// "APIC" Multiple APIC Description Table.
///
#define EFI_ACPI_1_0_APIC_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')
///
/// "DSDT" Differentiated System Description Table.
///
#define EFI_ACPI_1_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T')
///
/// "FACS" Firmware ACPI Control Structure.
///
#define EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S')
///
/// "FACP" Fixed ACPI Description Table.
///
#define EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P')
///
/// "PSDT" Persistent System Description Table.
///
#define EFI_ACPI_1_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')
///
/// "RSDT" Root System Description Table.
///
#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T')
///
/// "SBST" Smart Battery Specification Table.
///
#define EFI_ACPI_1_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T')
///
/// "SSDT" Secondary System Description Table.
///
#define EFI_ACPI_1_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')
#pragma pack()
#endif

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/** @file
ACPI 2.0 definitions from the ACPI Specification, revision 2.0
Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _ACPI_2_0_H_
#define _ACPI_2_0_H_
#include <IndustryStandard/Acpi10.h>
//
// Define for Desriptor
//
#define ACPI_LARGE_GENERIC_REGISTER_DESCRIPTOR_NAME 0x02
#define ACPI_GENERIC_REGISTER_DESCRIPTOR 0x82
//
// Ensure proper structure formats
//
#pragma pack(1)
///
/// Generic Register Descriptor
///
typedef PACKED struct {
ACPI_LARGE_RESOURCE_HEADER Header;
UINT8 AddressSpaceId;
UINT8 RegisterBitWidth;
UINT8 RegisterBitOffset;
UINT8 AddressSize;
UINT64 RegisterAddress;
} EFI_ACPI_GENERIC_REGISTER_DESCRIPTOR;
#pragma pack()
//
// Ensure proper structure formats
//
#pragma pack(1)
///
/// ACPI 2.0 Generic Address Space definition
///
typedef struct {
UINT8 AddressSpaceId;
UINT8 RegisterBitWidth;
UINT8 RegisterBitOffset;
UINT8 Reserved;
UINT64 Address;
} EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE;
//
// Generic Address Space Address IDs
//
#define EFI_ACPI_2_0_SYSTEM_MEMORY 0
#define EFI_ACPI_2_0_SYSTEM_IO 1
#define EFI_ACPI_2_0_PCI_CONFIGURATION_SPACE 2
#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER 3
#define EFI_ACPI_2_0_SMBUS 4
#define EFI_ACPI_2_0_FUNCTIONAL_FIXED_HARDWARE 0x7F
//
// ACPI 2.0 table structures
//
///
/// Root System Description Pointer Structure
///
typedef struct {
UINT64 Signature;
UINT8 Checksum;
UINT8 OemId[6];
UINT8 Revision;
UINT32 RsdtAddress;
UINT32 Length;
UINT64 XsdtAddress;
UINT8 ExtendedChecksum;
UINT8 Reserved[3];
} EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
///
/// RSD_PTR Revision (as defined in ACPI 2.0 spec.)
///
#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02
///
/// Common table header, this prefaces all ACPI tables, including FACS, but
/// excluding the RSD PTR structure
///
typedef struct {
UINT32 Signature;
UINT32 Length;
} EFI_ACPI_2_0_COMMON_HEADER;
//
// Root System Description Table
// No definition needed as it is a common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
//
///
/// RSDT Revision (as defined in ACPI 2.0 spec.)
///
#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
//
// Extended System Description Table
// No definition needed as it is a common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
//
///
/// XSDT Revision (as defined in ACPI 2.0 spec.)
///
#define EFI_ACPI_2_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
///
/// Fixed ACPI Description Table Structure (FADT)
///
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
UINT32 FirmwareCtrl;
UINT32 Dsdt;
UINT8 Reserved0;
UINT8 PreferredPmProfile;
UINT16 SciInt;
UINT32 SmiCmd;
UINT8 AcpiEnable;
UINT8 AcpiDisable;
UINT8 S4BiosReq;
UINT8 PstateCnt;
UINT32 Pm1aEvtBlk;
UINT32 Pm1bEvtBlk;
UINT32 Pm1aCntBlk;
UINT32 Pm1bCntBlk;
UINT32 Pm2CntBlk;
UINT32 PmTmrBlk;
UINT32 Gpe0Blk;
UINT32 Gpe1Blk;
UINT8 Pm1EvtLen;
UINT8 Pm1CntLen;
UINT8 Pm2CntLen;
UINT8 PmTmrLen;
UINT8 Gpe0BlkLen;
UINT8 Gpe1BlkLen;
UINT8 Gpe1Base;
UINT8 CstCnt;
UINT16 PLvl2Lat;
UINT16 PLvl3Lat;
UINT16 FlushSize;
UINT16 FlushStride;
UINT8 DutyOffset;
UINT8 DutyWidth;
UINT8 DayAlrm;
UINT8 MonAlrm;
UINT8 Century;
UINT16 IaPcBootArch;
UINT8 Reserved1;
UINT32 Flags;
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE ResetReg;
UINT8 ResetValue;
UINT8 Reserved2[3];
UINT64 XFirmwareCtrl;
UINT64 XDsdt;
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
} EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE;
///
/// FADT Version (as defined in ACPI 2.0 spec.)
///
#define EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x03
//
// Fixed ACPI Description Table Preferred Power Management Profile
//
#define EFI_ACPI_2_0_PM_PROFILE_UNSPECIFIED 0
#define EFI_ACPI_2_0_PM_PROFILE_DESKTOP 1
#define EFI_ACPI_2_0_PM_PROFILE_MOBILE 2
#define EFI_ACPI_2_0_PM_PROFILE_WORKSTATION 3
#define EFI_ACPI_2_0_PM_PROFILE_ENTERPRISE_SERVER 4
#define EFI_ACPI_2_0_PM_PROFILE_SOHO_SERVER 5
#define EFI_ACPI_2_0_PM_PROFILE_APPLIANCE_PC 6
//
// Fixed ACPI Description Table Boot Architecture Flags
// All other bits are reserved and must be set to 0.
//
#define EFI_ACPI_2_0_LEGACY_DEVICES BIT0
#define EFI_ACPI_2_0_8042 BIT1
//
// Fixed ACPI Description Table Fixed Feature Flags
// All other bits are reserved and must be set to 0.
//
#define EFI_ACPI_2_0_WBINVD BIT0
#define EFI_ACPI_2_0_WBINVD_FLUSH BIT1
#define EFI_ACPI_2_0_PROC_C1 BIT2
#define EFI_ACPI_2_0_P_LVL2_UP BIT3
#define EFI_ACPI_2_0_PWR_BUTTON BIT4
#define EFI_ACPI_2_0_SLP_BUTTON BIT5
#define EFI_ACPI_2_0_FIX_RTC BIT6
#define EFI_ACPI_2_0_RTC_S4 BIT7
#define EFI_ACPI_2_0_TMR_VAL_EXT BIT8
#define EFI_ACPI_2_0_DCK_CAP BIT9
#define EFI_ACPI_2_0_RESET_REG_SUP BIT10
#define EFI_ACPI_2_0_SEALED_CASE BIT11
#define EFI_ACPI_2_0_HEADLESS BIT12
#define EFI_ACPI_2_0_CPU_SW_SLP BIT13
///
/// Firmware ACPI Control Structure
///
typedef struct {
UINT32 Signature;
UINT32 Length;
UINT32 HardwareSignature;
UINT32 FirmwareWakingVector;
UINT32 GlobalLock;
UINT32 Flags;
UINT64 XFirmwareWakingVector;
UINT8 Version;
UINT8 Reserved[31];
} EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
///
/// FACS Version (as defined in ACPI 2.0 spec.)
///
#define EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x01
///
/// Firmware Control Structure Feature Flags
/// All other bits are reserved and must be set to 0.
///
#define EFI_ACPI_2_0_S4BIOS_F BIT0
///
/// Multiple APIC Description Table header definition. The rest of the table
/// must be defined in a platform specific manner.
///
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
UINT32 LocalApicAddress;
UINT32 Flags;
} EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
///
/// MADT Revision (as defined in ACPI 2.0 spec.)
///
#define EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x01
///
/// Multiple APIC Flags
/// All other bits are reserved and must be set to 0.
///
#define EFI_ACPI_2_0_PCAT_COMPAT BIT0
//
// Multiple APIC Description Table APIC structure types
// All other values between 0x09 an 0xFF are reserved and
// will be ignored by OSPM.
//
#define EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC 0x00
#define EFI_ACPI_2_0_IO_APIC 0x01
#define EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE 0x02
#define EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03
#define EFI_ACPI_2_0_LOCAL_APIC_NMI 0x04
#define EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE 0x05
#define EFI_ACPI_2_0_IO_SAPIC 0x06
#define EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC 0x07
#define EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES 0x08
//
// APIC Structure Definitions
//
///
/// Processor Local APIC Structure Definition
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT8 AcpiProcessorId;
UINT8 ApicId;
UINT32 Flags;
} EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
///
/// Local APIC Flags. All other bits are reserved and must be 0.
///
#define EFI_ACPI_2_0_LOCAL_APIC_ENABLED BIT0
///
/// IO APIC Structure
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT8 IoApicId;
UINT8 Reserved;
UINT32 IoApicAddress;
UINT32 GlobalSystemInterruptBase;
} EFI_ACPI_2_0_IO_APIC_STRUCTURE;
///
/// Interrupt Source Override Structure
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT8 Bus;
UINT8 Source;
UINT32 GlobalSystemInterrupt;
UINT16 Flags;
} EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
///
/// Non-Maskable Interrupt Source Structure
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT16 Flags;
UINT32 GlobalSystemInterrupt;
} EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
///
/// Local APIC NMI Structure
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT8 AcpiProcessorId;
UINT16 Flags;
UINT8 LocalApicLint;
} EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE;
///
/// Local APIC Address Override Structure
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT16 Reserved;
UINT64 LocalApicAddress;
} EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
///
/// IO SAPIC Structure
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT8 IoApicId;
UINT8 Reserved;
UINT32 GlobalSystemInterruptBase;
UINT64 IoSapicAddress;
} EFI_ACPI_2_0_IO_SAPIC_STRUCTURE;
///
/// Local SAPIC Structure
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT8 AcpiProcessorId;
UINT8 LocalSapicId;
UINT8 LocalSapicEid;
UINT8 Reserved[3];
UINT32 Flags;
} EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
///
/// Platform Interrupt Sources Structure
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT16 Flags;
UINT8 InterruptType;
UINT8 ProcessorId;
UINT8 ProcessorEid;
UINT8 IoSapicVector;
UINT32 GlobalSystemInterrupt;
UINT32 Reserved;
} EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
///
/// Smart Battery Description Table (SBST)
///
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
UINT32 WarningEnergyLevel;
UINT32 LowEnergyLevel;
UINT32 CriticalEnergyLevel;
} EFI_ACPI_2_0_SMART_BATTERY_DESCRIPTION_TABLE;
///
/// SBST Version (as defined in ACPI 2.0 spec.)
///
#define EFI_ACPI_2_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
///
/// Embedded Controller Boot Resources Table (ECDT)
/// The table is followed by a null terminated ASCII string that contains
/// a fully qualified reference to the name space object.
///
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE EcControl;
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE EcData;
UINT32 Uid;
UINT8 GpeBit;
} EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
///
/// ECDT Version (as defined in ACPI 2.0 spec.)
///
#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01
//
// Known table signatures
//
///
/// "RSD PTR " Root System Description Pointer
///
#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
///
/// "SPIC" Multiple SAPIC Description Table
///
/// BUGBUG: Don't know where this came from except SR870BN4 uses it.
/// #define EFI_ACPI_2_0_MULTIPLE_SAPIC_DESCRIPTION_TABLE_SIGNATURE 0x43495053
///
#define EFI_ACPI_2_0_MULTIPLE_SAPIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')
///
/// "BOOT" MS Simple Boot Spec
///
#define EFI_ACPI_2_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T')
///
/// "DBGP" MS Bebug Port Spec
///
#define EFI_ACPI_2_0_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P')
///
/// "DSDT" Differentiated System Description Table
///
#define EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T')
///
/// "ECDT" Embedded Controller Boot Resources Table
///
#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T')
///
/// "ETDT" Event Timer Description Table
///
#define EFI_ACPI_2_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T')
///
/// "FACS" Firmware ACPI Control Structure
///
#define EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S')
///
/// "FACP" Fixed ACPI Description Table
///
#define EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P')
///
/// "APIC" Multiple APIC Description Table
///
#define EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')
///
/// "PSDT" Persistent System Description Table
///
#define EFI_ACPI_2_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')
///
/// "RSDT" Root System Description Table
///
#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T')
///
/// "SBST" Smart Battery Specification Table
///
#define EFI_ACPI_2_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T')
///
/// "SLIT" System Locality Information Table
///
#define EFI_ACPI_2_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T')
///
/// "SPCR" Serial Port Concole Redirection Table
///
#define EFI_ACPI_2_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')
///
/// "SRAT" Static Resource Affinity Table
///
#define EFI_ACPI_2_0_STATIC_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T')
///
/// "SSDT" Secondary System Description Table
///
#define EFI_ACPI_2_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')
///
/// "SPMI" Server Platform Management Interface Table
///
#define EFI_ACPI_2_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I')
///
/// "XSDT" Extended System Description Table
///
#define EFI_ACPI_2_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T')
///
/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
///
#define EFI_ACPI_2_0_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')
#pragma pack()
#endif

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/** @file
ACPI 3.0 definitions from the ACPI Specification Revision 3.0b October 10, 2006
Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _ACPI_3_0_H_
#define _ACPI_3_0_H_
#include <IndustryStandard/Acpi20.h>
//
// Define for Desriptor
//
#define ACPI_LARGE_EXTENDED_ADDRESS_SPACE_DESCRIPTOR_NAME 0x0B
#define ACPI_EXTENDED_ADDRESS_SPACE_DESCRIPTOR 0x8B
//
// Ensure proper structure formats
//
#pragma pack(1)
///
/// Extended Address Space Descriptor
///
typedef PACKED struct {
ACPI_LARGE_RESOURCE_HEADER Header;
UINT8 ResType;
UINT8 GenFlag;
UINT8 SpecificFlag;
UINT8 RevisionId;
UINT8 Reserved;
UINT64 AddrSpaceGranularity;
UINT64 AddrRangeMin;
UINT64 AddrRangeMax;
UINT64 AddrTranslationOffset;
UINT64 AddrLen;
UINT64 TypeSpecificAttribute;
} EFI_ACPI_EXTENDED_ADDRESS_SPACE_DESCRIPTOR;
#pragma pack()
//
// Memory Type Specific Flags
//
#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_UC 0x0000000000000001
#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_WC 0x0000000000000002
#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_WT 0x0000000000000004
#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_WB 0x0000000000000008
#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_UCE 0x0000000000000010
#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_NV 0x0000000000008000
//
// Ensure proper structure formats
//
#pragma pack(1)
///
/// ACPI 3.0 Generic Address Space definition
///
typedef struct {
UINT8 AddressSpaceId;
UINT8 RegisterBitWidth;
UINT8 RegisterBitOffset;
UINT8 AccessSize;
UINT64 Address;
} EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE;
//
// Generic Address Space Address IDs
//
#define EFI_ACPI_3_0_SYSTEM_MEMORY 0
#define EFI_ACPI_3_0_SYSTEM_IO 1
#define EFI_ACPI_3_0_PCI_CONFIGURATION_SPACE 2
#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER 3
#define EFI_ACPI_3_0_SMBUS 4
#define EFI_ACPI_3_0_FUNCTIONAL_FIXED_HARDWARE 0x7F
//
// Generic Address Space Access Sizes
//
#define EFI_ACPI_3_0_UNDEFINED 0
#define EFI_ACPI_3_0_BYTE 1
#define EFI_ACPI_3_0_WORD 2
#define EFI_ACPI_3_0_DWORD 3
#define EFI_ACPI_3_0_QWORD 4
//
// ACPI 3.0 table structures
//
///
/// Root System Description Pointer Structure
///
typedef struct {
UINT64 Signature;
UINT8 Checksum;
UINT8 OemId[6];
UINT8 Revision;
UINT32 RsdtAddress;
UINT32 Length;
UINT64 XsdtAddress;
UINT8 ExtendedChecksum;
UINT8 Reserved[3];
} EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
///
/// RSD_PTR Revision (as defined in ACPI 3.0b spec.)
///
#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 3.0b) says current value is 2
///
/// Common table header, this prefaces all ACPI tables, including FACS, but
/// excluding the RSD PTR structure
///
typedef struct {
UINT32 Signature;
UINT32 Length;
} EFI_ACPI_3_0_COMMON_HEADER;
//
// Root System Description Table
// No definition needed as it is a common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
//
///
/// RSDT Revision (as defined in ACPI 3.0 spec.)
///
#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
//
// Extended System Description Table
// No definition needed as it is a common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
//
///
/// XSDT Revision (as defined in ACPI 3.0 spec.)
///
#define EFI_ACPI_3_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
///
/// Fixed ACPI Description Table Structure (FADT)
///
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
UINT32 FirmwareCtrl;
UINT32 Dsdt;
UINT8 Reserved0;
UINT8 PreferredPmProfile;
UINT16 SciInt;
UINT32 SmiCmd;
UINT8 AcpiEnable;
UINT8 AcpiDisable;
UINT8 S4BiosReq;
UINT8 PstateCnt;
UINT32 Pm1aEvtBlk;
UINT32 Pm1bEvtBlk;
UINT32 Pm1aCntBlk;
UINT32 Pm1bCntBlk;
UINT32 Pm2CntBlk;
UINT32 PmTmrBlk;
UINT32 Gpe0Blk;
UINT32 Gpe1Blk;
UINT8 Pm1EvtLen;
UINT8 Pm1CntLen;
UINT8 Pm2CntLen;
UINT8 PmTmrLen;
UINT8 Gpe0BlkLen;
UINT8 Gpe1BlkLen;
UINT8 Gpe1Base;
UINT8 CstCnt;
UINT16 PLvl2Lat;
UINT16 PLvl3Lat;
UINT16 FlushSize;
UINT16 FlushStride;
UINT8 DutyOffset;
UINT8 DutyWidth;
UINT8 DayAlrm;
UINT8 MonAlrm;
UINT8 Century;
UINT16 IaPcBootArch;
UINT8 Reserved1;
UINT32 Flags;
EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE ResetReg;
UINT8 ResetValue;
UINT8 Reserved2[3];
UINT64 XFirmwareCtrl;
UINT64 XDsdt;
EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
} EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE;
///
/// FADT Version (as defined in ACPI 3.0 spec.)
///
#define EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x04
//
// Fixed ACPI Description Table Preferred Power Management Profile
//
#define EFI_ACPI_3_0_PM_PROFILE_UNSPECIFIED 0
#define EFI_ACPI_3_0_PM_PROFILE_DESKTOP 1
#define EFI_ACPI_3_0_PM_PROFILE_MOBILE 2
#define EFI_ACPI_3_0_PM_PROFILE_WORKSTATION 3
#define EFI_ACPI_3_0_PM_PROFILE_ENTERPRISE_SERVER 4
#define EFI_ACPI_3_0_PM_PROFILE_SOHO_SERVER 5
#define EFI_ACPI_3_0_PM_PROFILE_APPLIANCE_PC 6
#define EFI_ACPI_3_0_PM_PROFILE_PERFORMANCE_SERVER 7
//
// Fixed ACPI Description Table Boot Architecture Flags
// All other bits are reserved and must be set to 0.
//
#define EFI_ACPI_3_0_LEGACY_DEVICES BIT0
#define EFI_ACPI_3_0_8042 BIT1
#define EFI_ACPI_3_0_VGA_NOT_PRESENT BIT2
#define EFI_ACPI_3_0_MSI_NOT_SUPPORTED BIT3
#define EFI_ACPI_3_0_PCIE_ASPM_CONTROLS BIT4
//
// Fixed ACPI Description Table Fixed Feature Flags
// All other bits are reserved and must be set to 0.
//
#define EFI_ACPI_3_0_WBINVD BIT0
#define EFI_ACPI_3_0_WBINVD_FLUSH BIT1
#define EFI_ACPI_3_0_PROC_C1 BIT2
#define EFI_ACPI_3_0_P_LVL2_UP BIT3
#define EFI_ACPI_3_0_PWR_BUTTON BIT4
#define EFI_ACPI_3_0_SLP_BUTTON BIT5
#define EFI_ACPI_3_0_FIX_RTC BIT6
#define EFI_ACPI_3_0_RTC_S4 BIT7
#define EFI_ACPI_3_0_TMR_VAL_EXT BIT8
#define EFI_ACPI_3_0_DCK_CAP BIT9
#define EFI_ACPI_3_0_RESET_REG_SUP BIT10
#define EFI_ACPI_3_0_SEALED_CASE BIT11
#define EFI_ACPI_3_0_HEADLESS BIT12
#define EFI_ACPI_3_0_CPU_SW_SLP BIT13
#define EFI_ACPI_3_0_PCI_EXP_WAK BIT14
#define EFI_ACPI_3_0_USE_PLATFORM_CLOCK BIT15
#define EFI_ACPI_3_0_S4_RTC_STS_VALID BIT16
#define EFI_ACPI_3_0_REMOTE_POWER_ON_CAPABLE BIT17
#define EFI_ACPI_3_0_FORCE_APIC_CLUSTER_MODEL BIT18
#define EFI_ACPI_3_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
///
/// Firmware ACPI Control Structure
///
typedef struct {
UINT32 Signature;
UINT32 Length;
UINT32 HardwareSignature;
UINT32 FirmwareWakingVector;
UINT32 GlobalLock;
UINT32 Flags;
UINT64 XFirmwareWakingVector;
UINT8 Version;
UINT8 Reserved[31];
} EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
///
/// FACS Version (as defined in ACPI 3.0 spec.)
///
#define EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x01
///
/// Firmware Control Structure Feature Flags
/// All other bits are reserved and must be set to 0.
///
#define EFI_ACPI_3_0_S4BIOS_F BIT0
//
// Differentiated System Description Table,
// Secondary System Description Table
// and Persistent System Description Table,
// no definition needed as they are common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.
//
#define EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
#define EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
///
/// Multiple APIC Description Table header definition. The rest of the table
/// must be defined in a platform specific manner.
///
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
UINT32 LocalApicAddress;
UINT32 Flags;
} EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
///
/// MADT Revision (as defined in ACPI 3.0 spec.)
///
#define EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x02
///
/// Multiple APIC Flags
/// All other bits are reserved and must be set to 0.
///
#define EFI_ACPI_3_0_PCAT_COMPAT BIT0
//
// Multiple APIC Description Table APIC structure types
// All other values between 0x09 an 0xFF are reserved and
// will be ignored by OSPM.
//
#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC 0x00
#define EFI_ACPI_3_0_IO_APIC 0x01
#define EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE 0x02
#define EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03
#define EFI_ACPI_3_0_LOCAL_APIC_NMI 0x04
#define EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE 0x05
#define EFI_ACPI_3_0_IO_SAPIC 0x06
#define EFI_ACPI_3_0_LOCAL_SAPIC 0x07
#define EFI_ACPI_3_0_PLATFORM_INTERRUPT_SOURCES 0x08
//
// APIC Structure Definitions
//
///
/// Processor Local APIC Structure Definition
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT8 AcpiProcessorId;
UINT8 ApicId;
UINT32 Flags;
} EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
///
/// Local APIC Flags. All other bits are reserved and must be 0.
///
#define EFI_ACPI_3_0_LOCAL_APIC_ENABLED BIT0
///
/// IO APIC Structure
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT8 IoApicId;
UINT8 Reserved;
UINT32 IoApicAddress;
UINT32 GlobalSystemInterruptBase;
} EFI_ACPI_3_0_IO_APIC_STRUCTURE;
///
/// Interrupt Source Override Structure
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT8 Bus;
UINT8 Source;
UINT32 GlobalSystemInterrupt;
UINT16 Flags;
} EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
///
/// Platform Interrupt Sources Structure Definition
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT16 Flags;
UINT8 InterruptType;
UINT8 ProcessorId;
UINT8 ProcessorEid;
UINT8 IoSapicVector;
UINT32 GlobalSystemInterrupt;
UINT32 PlatformInterruptSourceFlags;
UINT8 CpeiProcessorOverride;
UINT8 Reserved[31];
} EFI_ACPI_3_0_PLATFORM_INTERRUPT_APIC_STRUCTURE;
//
// MPS INTI flags.
// All other bits are reserved and must be set to 0.
//
#define EFI_ACPI_3_0_POLARITY (3 << 0)
#define EFI_ACPI_3_0_TRIGGER_MODE (3 << 2)
///
/// Non-Maskable Interrupt Source Structure
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT16 Flags;
UINT32 GlobalSystemInterrupt;
} EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
///
/// Local APIC NMI Structure
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT8 AcpiProcessorId;
UINT16 Flags;
UINT8 LocalApicLint;
} EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE;
///
/// Local APIC Address Override Structure
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT16 Reserved;
UINT64 LocalApicAddress;
} EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
///
/// IO SAPIC Structure
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT8 IoApicId;
UINT8 Reserved;
UINT32 GlobalSystemInterruptBase;
UINT64 IoSapicAddress;
} EFI_ACPI_3_0_IO_SAPIC_STRUCTURE;
///
/// Local SAPIC Structure
/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT8 AcpiProcessorId;
UINT8 LocalSapicId;
UINT8 LocalSapicEid;
UINT8 Reserved[3];
UINT32 Flags;
UINT32 ACPIProcessorUIDValue;
} EFI_ACPI_3_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
///
/// Platform Interrupt Sources Structure
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT16 Flags;
UINT8 InterruptType;
UINT8 ProcessorId;
UINT8 ProcessorEid;
UINT8 IoSapicVector;
UINT32 GlobalSystemInterrupt;
UINT32 PlatformInterruptSourceFlags;
} EFI_ACPI_3_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
///
/// Platform Interrupt Source Flags.
/// All other bits are reserved and must be set to 0.
///
#define EFI_ACPI_3_0_CPEI_PROCESSOR_OVERRIDE BIT0
///
/// Smart Battery Description Table (SBST)
///
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
UINT32 WarningEnergyLevel;
UINT32 LowEnergyLevel;
UINT32 CriticalEnergyLevel;
} EFI_ACPI_3_0_SMART_BATTERY_DESCRIPTION_TABLE;
///
/// SBST Version (as defined in ACPI 3.0 spec.)
///
#define EFI_ACPI_3_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
///
/// Embedded Controller Boot Resources Table (ECDT)
/// The table is followed by a null terminated ASCII string that contains
/// a fully qualified reference to the name space object.
///
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE EcControl;
EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE EcData;
UINT32 Uid;
UINT8 GpeBit;
} EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
///
/// ECDT Version (as defined in ACPI 3.0 spec.)
///
#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01
///
/// System Resource Affinity Table (SRAT. The rest of the table
/// must be defined in a platform specific manner.
///
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
UINT32 Reserved1; ///< Must be set to 1
UINT64 Reserved2;
} EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
///
/// SRAT Version (as defined in ACPI 3.0 spec.)
///
#define EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x02
//
// SRAT structure types.
// All other values between 0x02 an 0xFF are reserved and
// will be ignored by OSPM.
//
#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00
#define EFI_ACPI_3_0_MEMORY_AFFINITY 0x01
///
/// Processor Local APIC/SAPIC Affinity Structure Definition
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT8 ProximityDomain7To0;
UINT8 ApicId;
UINT32 Flags;
UINT8 LocalSapicEid;
UINT8 ProximityDomain31To8[3];
UINT8 Reserved[4];
} EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
///
/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.
///
#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
///
/// Memory Affinity Structure Definition
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT32 ProximityDomain;
UINT16 Reserved1;
UINT32 AddressBaseLow;
UINT32 AddressBaseHigh;
UINT32 LengthLow;
UINT32 LengthHigh;
UINT32 Reserved2;
UINT32 Flags;
UINT64 Reserved3;
} EFI_ACPI_3_0_MEMORY_AFFINITY_STRUCTURE;
//
// Memory Flags. All other bits are reserved and must be 0.
//
#define EFI_ACPI_3_0_MEMORY_ENABLED (1 << 0)
#define EFI_ACPI_3_0_MEMORY_HOT_PLUGGABLE (1 << 1)
#define EFI_ACPI_3_0_MEMORY_NONVOLATILE (1 << 2)
///
/// System Locality Distance Information Table (SLIT).
/// The rest of the table is a matrix.
///
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
UINT64 NumberOfSystemLocalities;
} EFI_ACPI_3_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
///
/// SLIT Version (as defined in ACPI 3.0 spec.)
///
#define EFI_ACPI_3_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01
//
// Known table signatures
//
///
/// "RSD PTR " Root System Description Pointer
///
#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
///
/// "APIC" Multiple APIC Description Table
///
#define EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')
///
/// "DSDT" Differentiated System Description Table
///
#define EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T')
///
/// "ECDT" Embedded Controller Boot Resources Table
///
#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T')
///
/// "FACP" Fixed ACPI Description Table
///
#define EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P')
///
/// "FACS" Firmware ACPI Control Structure
///
#define EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S')
///
/// "PSDT" Persistent System Description Table
///
#define EFI_ACPI_3_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')
///
/// "RSDT" Root System Description Table
///
#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T')
///
/// "SBST" Smart Battery Specification Table
///
#define EFI_ACPI_3_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T')
///
/// "SLIT" System Locality Information Table
///
#define EFI_ACPI_3_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T')
///
/// "SRAT" System Resource Affinity Table
///
#define EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T')
///
/// "SSDT" Secondary System Description Table
///
#define EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')
///
/// "XSDT" Extended System Description Table
///
#define EFI_ACPI_3_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T')
///
/// "BOOT" MS Simple Boot Spec
///
#define EFI_ACPI_3_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T')
///
/// "CPEP" Corrected Platform Error Polling Table
///
#define EFI_ACPI_3_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE SIGNATURE_32('C', 'P', 'E', 'P')
///
/// "DBGP" MS Debug Port Spec
///
#define EFI_ACPI_3_0_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P')
///
/// "ETDT" Event Timer Description Table
///
#define EFI_ACPI_3_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T')
///
/// "HPET" IA-PC High Precision Event Timer Table
///
#define EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE SIGNATURE_32('H', 'P', 'E', 'T')
///
/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
///
#define EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')
///
/// "SPCR" Serial Port Concole Redirection Table
///
#define EFI_ACPI_3_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')
///
/// "SPMI" Server Platform Management Interface Table
///
#define EFI_ACPI_3_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I')
///
/// "TCPA" Trusted Computing Platform Alliance Capabilities Table
///
#define EFI_ACPI_3_0_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE SIGNATURE_32('T', 'C', 'P', 'A')
///
/// "WDRT" Watchdog Resource Table
///
#define EFI_ACPI_3_0_WATCHDOG_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'R', 'T')
///
/// "WDAT" Watchdog Action Table
///
#define EFI_ACPI_3_0_WATCHDOG_ACTION_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'A', 'T')
///
/// "WSPT" Windows Specific Properties Table
///
#define EFI_ACPI_3_0_WINDOWS_SPECIFIC_PROPERTIES_TABLE_SIGNATURE SIGNATURE_32('W', 'S', 'P', 'T')
///
/// "iBFT" iSCSI Boot Firmware Table
///
#define EFI_ACPI_3_0_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T')
#pragma pack()
#endif

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/** @file
This file contains AML code definition in the latest ACPI spec.
Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _ACPI_AML_H_
#define _ACPI_AML_H_
//
// ACPI AML definition
//
//
// Primary OpCode
//
#define AML_ZERO_OP 0x00
#define AML_ONE_OP 0x01
#define AML_ALIAS_OP 0x06
#define AML_NAME_OP 0x08
#define AML_BYTE_PREFIX 0x0a
#define AML_WORD_PREFIX 0x0b
#define AML_DWORD_PREFIX 0x0c
#define AML_STRING_PREFIX 0x0d
#define AML_QWORD_PREFIX 0x0e
#define AML_SCOPE_OP 0x10
#define AML_BUFFER_OP 0x11
#define AML_PACKAGE_OP 0x12
#define AML_VAR_PACKAGE_OP 0x13
#define AML_METHOD_OP 0x14
#define AML_DUAL_NAME_PREFIX 0x2e
#define AML_MULTI_NAME_PREFIX 0x2f
#define AML_NAME_CHAR_A 0x41
#define AML_NAME_CHAR_B 0x42
#define AML_NAME_CHAR_C 0x43
#define AML_NAME_CHAR_D 0x44
#define AML_NAME_CHAR_E 0x45
#define AML_NAME_CHAR_F 0x46
#define AML_NAME_CHAR_G 0x47
#define AML_NAME_CHAR_H 0x48
#define AML_NAME_CHAR_I 0x49
#define AML_NAME_CHAR_J 0x4a
#define AML_NAME_CHAR_K 0x4b
#define AML_NAME_CHAR_L 0x4c
#define AML_NAME_CHAR_M 0x4d
#define AML_NAME_CHAR_N 0x4e
#define AML_NAME_CHAR_O 0x4f
#define AML_NAME_CHAR_P 0x50
#define AML_NAME_CHAR_Q 0x51
#define AML_NAME_CHAR_R 0x52
#define AML_NAME_CHAR_S 0x53
#define AML_NAME_CHAR_T 0x54
#define AML_NAME_CHAR_U 0x55
#define AML_NAME_CHAR_V 0x56
#define AML_NAME_CHAR_W 0x57
#define AML_NAME_CHAR_X 0x58
#define AML_NAME_CHAR_Y 0x59
#define AML_NAME_CHAR_Z 0x5a
#define AML_ROOT_CHAR 0x5c
#define AML_PARENT_PREFIX_CHAR 0x5e
#define AML_NAME_CHAR__ 0x5f
#define AML_LOCAL0 0x60
#define AML_LOCAL1 0x61
#define AML_LOCAL2 0x62
#define AML_LOCAL3 0x63
#define AML_LOCAL4 0x64
#define AML_LOCAL5 0x65
#define AML_LOCAL6 0x66
#define AML_LOCAL7 0x67
#define AML_ARG0 0x68
#define AML_ARG1 0x69
#define AML_ARG2 0x6a
#define AML_ARG3 0x6b
#define AML_ARG4 0x6c
#define AML_ARG5 0x6d
#define AML_ARG6 0x6e
#define AML_STORE_OP 0x70
#define AML_REF_OF_OP 0x71
#define AML_ADD_OP 0x72
#define AML_CONCAT_OP 0x73
#define AML_SUBTRACT_OP 0x74
#define AML_INCREMENT_OP 0x75
#define AML_DECREMENT_OP 0x76
#define AML_MULTIPLY_OP 0x77
#define AML_DIVIDE_OP 0x78
#define AML_SHIFT_LEFT_OP 0x79
#define AML_SHIFT_RIGHT_OP 0x7a
#define AML_AND_OP 0x7b
#define AML_NAND_OP 0x7c
#define AML_OR_OP 0x7d
#define AML_NOR_OP 0x7e
#define AML_XOR_OP 0x7f
#define AML_NOT_OP 0x80
#define AML_FIND_SET_LEFT_BIT_OP 0x81
#define AML_FIND_SET_RIGHT_BIT_OP 0x82
#define AML_DEREF_OF_OP 0x83
#define AML_CONCAT_RES_OP 0x84
#define AML_MOD_OP 0x85
#define AML_NOTIFY_OP 0x86
#define AML_SIZE_OF_OP 0x87
#define AML_INDEX_OP 0x88
#define AML_MATCH_OP 0x89
#define AML_CREATE_DWORD_FIELD_OP 0x8a
#define AML_CREATE_WORD_FIELD_OP 0x8b
#define AML_CREATE_BYTE_FIELD_OP 0x8c
#define AML_CREATE_BIT_FIELD_OP 0x8d
#define AML_OBJECT_TYPE_OP 0x8e
#define AML_CREATE_QWORD_FIELD_OP 0x8f
#define AML_LAND_OP 0x90
#define AML_LOR_OP 0x91
#define AML_LNOT_OP 0x92
#define AML_LEQUAL_OP 0x93
#define AML_LGREATER_OP 0x94
#define AML_LLESS_OP 0x95
#define AML_TO_BUFFER_OP 0x96
#define AML_TO_DEC_STRING_OP 0x97
#define AML_TO_HEX_STRING_OP 0x98
#define AML_TO_INTEGER_OP 0x99
#define AML_TO_STRING_OP 0x9c
#define AML_COPY_OBJECT_OP 0x9d
#define AML_MID_OP 0x9e
#define AML_CONTINUE_OP 0x9f
#define AML_IF_OP 0xa0
#define AML_ELSE_OP 0xa1
#define AML_WHILE_OP 0xa2
#define AML_NOOP_OP 0xa3
#define AML_RETURN_OP 0xa4
#define AML_BREAK_OP 0xa5
#define AML_BREAK_POINT_OP 0xcc
#define AML_ONES_OP 0xff
//
// Extended OpCode
//
#define AML_EXT_OP 0x5b
#define AML_EXT_MUTEX_OP 0x01
#define AML_EXT_EVENT_OP 0x02
#define AML_EXT_COND_REF_OF_OP 0x12
#define AML_EXT_CREATE_FIELD_OP 0x13
#define AML_EXT_LOAD_TABLE_OP 0x1f
#define AML_EXT_LOAD_OP 0x20
#define AML_EXT_STALL_OP 0x21
#define AML_EXT_SLEEP_OP 0x22
#define AML_EXT_ACQUIRE_OP 0x23
#define AML_EXT_SIGNAL_OP 0x24
#define AML_EXT_WAIT_OP 0x25
#define AML_EXT_RESET_OP 0x26
#define AML_EXT_RELEASE_OP 0x27
#define AML_EXT_FROM_BCD_OP 0x28
#define AML_EXT_TO_BCD_OP 0x29
#define AML_EXT_UNLOAD_OP 0x2a
#define AML_EXT_REVISION_OP 0x30
#define AML_EXT_DEBUG_OP 0x31
#define AML_EXT_FATAL_OP 0x32
#define AML_EXT_TIMER_OP 0x33
#define AML_EXT_REGION_OP 0x80
#define AML_EXT_FIELD_OP 0x81
#define AML_EXT_DEVICE_OP 0x82
#define AML_EXT_PROCESSOR_OP 0x83
#define AML_EXT_POWER_RES_OP 0x84
#define AML_EXT_THERMAL_ZONE_OP 0x85
#define AML_EXT_INDEX_FIELD_OP 0x86
#define AML_EXT_BANK_FIELD_OP 0x87
#define AML_EXT_DATA_REGION_OP 0x88
#endif

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/** @file
ACPI Alert Standard Format Description Table ASF! as described in the ASF2.0 Specification
Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _ALERT_STANDARD_FORMAT_TABLE_H_
#define _ALERT_STANDARD_FORMAT_TABLE_H_
#include <IndustryStandard/Acpi.h>
//
// Ensure proper structure formats
//
#pragma pack (1)
///
/// Information Record header that appears at the beginning of each record
///
typedef struct {
UINT8 Type;
UINT8 Reserved;
UINT16 RecordLength;
} EFI_ACPI_ASF_RECORD_HEADER;
///
/// This structure contains information that identifies the system's type
/// and configuration
///
typedef struct {
EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
UINT8 MinWatchDogResetValue;
UINT8 MinPollingInterval;
UINT16 SystemID;
UINT32 IANAManufactureID;
UINT8 FeatureFlags;
UINT8 Reserved[3];
} EFI_ACPI_ASF_INFO;
///
/// ASF Alert Data
///
typedef struct {
UINT8 DeviceAddress;
UINT8 Command;
UINT8 DataMask;
UINT8 CompareValue;
UINT8 EventSenseType;
UINT8 EventType;
UINT8 EventOffset;
UINT8 EventSourceType;
UINT8 EventSeverity;
UINT8 SensorNumber;
UINT8 Entity;
UINT8 EntityInstance;
} EFI_ACPI_ASF_ALERTDATA;
///
/// Alert sensors definition
///
typedef struct {
EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
UINT8 AssertionEventBitMask;
UINT8 DeassertionEventBitMask;
UINT8 NumberOfAlerts;
UINT8 ArrayElementLength; ///< For ASF version 1.0 and later, this filed is set to 0x0C
///
/// EFI_ACPI_ASF_ALERTDATA DeviceArray[ANYSIZE_ARRAY];
///
} EFI_ACPI_ASF_ALRT;
///
/// Alert Control Data
///
typedef struct {
UINT8 Function;
UINT8 DeviceAddress;
UINT8 Command;
UINT8 DataValue;
} EFI_ACPI_ASF_CONTROLDATA;
///
/// Alert Remote Control System Actions
///
typedef struct {
EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
UINT8 NumberOfControls;
UINT8 ArrayElementLength; ///< For ASF version 1.0 and later, this filed is set to 0x4
UINT16 RctlReserved;
///
/// EFI_ACPI_ASF_CONTROLDATA; DeviceArray[ANYSIZE_ARRAY];
///
} EFI_ACPI_ASF_RCTL;
///
/// Remote Control Capabilities
///
typedef struct {
EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
UINT8 RemoteControlCapabilities[7];
UINT8 RMCPCompletionCode;
UINT32 RMCPIANA;
UINT8 RMCPSpecialCommand;
UINT8 RMCPSpecialCommandParameter[2];
UINT8 RMCPBootOptions[2];
UINT8 RMCPOEMParameters[2];
} EFI_ACPI_ASF_RMCP;
///
/// SMBus Devices with fixed addresses
///
typedef struct {
EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
UINT8 SEEPROMAddress;
UINT8 NumberOfDevices;
///
/// UINT8 FixedSmbusAddresses[ANYSIZE_ARRAY];
///
} EFI_ACPI_ASF_ADDR;
///
/// ASF! Description Table Header
///
typedef EFI_ACPI_DESCRIPTION_HEADER EFI_ACPI_ASF_DESCRIPTION_HEADER;
///
/// The revision stored in ASF! DESCRIPTION TABLE as BCD value
///
#define EFI_ACPI_2_0_ASF_DESCRIPTION_TABLE_REVISION 0x20
///
/// "ASF!" ASF Description Table Signature
///
#define EFI_ACPI_ASF_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32 ('A', 'S', 'F', '!')
#pragma pack ()
#endif // _ALERT_STANDARD_FORMAT_TABLE_H

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/** @file
This file contains just some basic definitions that are needed by drivers
that dealing with ATA/ATAPI interface.
Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _ATAPI_H_
#define _ATAPI_H_
#pragma pack(1)
///
/// ATA5_IDENTIFY_DATA is defined in ATA-5.
/// (This structure is provided mainly for backward-compatibility support.
/// Old drivers may reference fields that are marked "obsolete" in
/// ATA_IDENTIFY_DATA, which currently conforms to ATA-8.)
///
typedef struct {
UINT16 config; ///< General Configuration.
UINT16 cylinders; ///< Number of Cylinders.
UINT16 reserved_2;
UINT16 heads; ///< Number of logical heads.
UINT16 vendor_data1;
UINT16 vendor_data2;
UINT16 sectors_per_track;
UINT16 vendor_specific_7_9[3];
CHAR8 SerialNo[20]; ///< ASCII
UINT16 vendor_specific_20_21[2];
UINT16 ecc_bytes_available;
CHAR8 FirmwareVer[8]; ///< ASCII
CHAR8 ModelName[40]; ///< ASCII
UINT16 multi_sector_cmd_max_sct_cnt;
UINT16 reserved_48;
UINT16 capabilities;
UINT16 reserved_50;
UINT16 pio_cycle_timing;
UINT16 reserved_52;
UINT16 field_validity;
UINT16 current_cylinders;
UINT16 current_heads;
UINT16 current_sectors;
UINT16 CurrentCapacityLsb;
UINT16 CurrentCapacityMsb;
UINT16 reserved_59;
UINT16 user_addressable_sectors_lo;
UINT16 user_addressable_sectors_hi;
UINT16 reserved_62;
UINT16 multi_word_dma_mode;
UINT16 advanced_pio_modes;
UINT16 min_multi_word_dma_cycle_time;
UINT16 rec_multi_word_dma_cycle_time;
UINT16 min_pio_cycle_time_without_flow_control;
UINT16 min_pio_cycle_time_with_flow_control;
UINT16 reserved_69_79[11];
UINT16 major_version_no;
UINT16 minor_version_no;
UINT16 command_set_supported_82; ///< word 82
UINT16 command_set_supported_83; ///< word 83
UINT16 command_set_feature_extn; ///< word 84
UINT16 command_set_feature_enb_85; ///< word 85
UINT16 command_set_feature_enb_86; ///< word 86
UINT16 command_set_feature_default; ///< word 87
UINT16 ultra_dma_mode; ///< word 88
UINT16 reserved_89_127[39];
UINT16 security_status;
UINT16 vendor_data_129_159[31];
UINT16 reserved_160_255[96];
} ATA5_IDENTIFY_DATA;
///
/// ATA_IDENTIFY_DATA strictly complies with ATA/ATAPI-8 Spec
/// to define the data returned by an ATA device upon successful
/// completion of the ATA IDENTIFY_DEVICE command.
///
typedef struct {
UINT16 config; ///< General Configuration.
UINT16 obsolete_1;
UINT16 specific_config; ///< Specific Configuration.
UINT16 obsolete_3;
UINT16 retired_4_5[2];
UINT16 obsolete_6;
UINT16 cfa_reserved_7_8[2];
UINT16 retired_9;
CHAR8 SerialNo[20]; ///< word 10~19
UINT16 retired_20_21[2];
UINT16 obsolete_22;
CHAR8 FirmwareVer[8]; ///< word 23~26
CHAR8 ModelName[40]; ///< word 27~46
UINT16 multi_sector_cmd_max_sct_cnt;
UINT16 trusted_computing_support;
UINT16 capabilities_49;
UINT16 capabilities_50;
UINT16 obsolete_51_52[2];
UINT16 field_validity;
UINT16 obsolete_54_58[5];
UINT16 multi_sector_setting;
UINT16 user_addressable_sectors_lo;
UINT16 user_addressable_sectors_hi;
UINT16 obsolete_62;
UINT16 multi_word_dma_mode;
UINT16 advanced_pio_modes;
UINT16 min_multi_word_dma_cycle_time;
UINT16 rec_multi_word_dma_cycle_time;
UINT16 min_pio_cycle_time_without_flow_control;
UINT16 min_pio_cycle_time_with_flow_control;
UINT16 additional_supported; ///< word 69
UINT16 reserved_70;
UINT16 reserved_71_74[4]; ///< Reserved for IDENTIFY PACKET DEVICE cmd.
UINT16 queue_depth;
UINT16 serial_ata_capabilities;
UINT16 reserved_77; ///< Reserved for Serial ATA
UINT16 serial_ata_features_supported;
UINT16 serial_ata_features_enabled;
UINT16 major_version_no;
UINT16 minor_version_no;
UINT16 command_set_supported_82; ///< word 82
UINT16 command_set_supported_83; ///< word 83
UINT16 command_set_feature_extn; ///< word 84
UINT16 command_set_feature_enb_85; ///< word 85
UINT16 command_set_feature_enb_86; ///< word 86
UINT16 command_set_feature_default; ///< word 87
UINT16 ultra_dma_mode; ///< word 88
UINT16 time_for_security_erase_unit;
UINT16 time_for_enhanced_security_erase_unit;
UINT16 advanced_power_management_level;
UINT16 master_password_identifier;
UINT16 hardware_configuration_test_result;
UINT16 obsolete_94;
UINT16 stream_minimum_request_size;
UINT16 streaming_transfer_time_for_dma;
UINT16 streaming_access_latency_for_dma_and_pio;
UINT16 streaming_performance_granularity[2]; ///< word 98~99
UINT16 maximum_lba_for_48bit_addressing[4]; ///< word 100~103
UINT16 streaming_transfer_time_for_pio;
UINT16 max_no_of_512byte_blocks_per_data_set_cmd;
UINT16 phy_logic_sector_support; ///< word 106
UINT16 interseek_delay_for_iso7779;
UINT16 world_wide_name[4]; ///< word 108~111
UINT16 reserved_for_128bit_wwn_112_115[4];
UINT16 reserved_for_technical_report;
UINT16 logic_sector_size_lo; ///< word 117
UINT16 logic_sector_size_hi; ///< word 118
UINT16 features_and_command_sets_supported_ext; ///< word 119
UINT16 features_and_command_sets_enabled_ext; ///< word 120
UINT16 reserved_121_126[6];
UINT16 obsolete_127;
UINT16 security_status; ///< word 128
UINT16 vendor_specific_129_159[31];
UINT16 cfa_power_mode; ///< word 160
UINT16 reserved_for_compactflash_161_167[7];
UINT16 device_nominal_form_factor;
UINT16 is_data_set_cmd_supported;
CHAR8 additional_product_identifier[8];
UINT16 reserved_174_175[2];
CHAR8 media_serial_number[60]; ///< word 176~205
UINT16 sct_command_transport; ///< word 206
UINT16 reserved_207_208[2];
UINT16 alignment_logic_in_phy_blocks; ///< word 209
UINT16 write_read_verify_sector_count_mode3[2]; ///< word 210~211
UINT16 verify_sector_count_mode2[2];
UINT16 nv_cache_capabilities;
UINT16 nv_cache_size_in_logical_block_lsw; ///< word 215
UINT16 nv_cache_size_in_logical_block_msw; ///< word 216
UINT16 nominal_media_rotation_rate;
UINT16 reserved_218;
UINT16 nv_cache_options; ///< word 219
UINT16 write_read_verify_mode; ///< word 220
UINT16 reserved_221;
UINT16 transport_major_revision_number;
UINT16 transport_minor_revision_number;
UINT16 reserved_224_229[6];
UINT64 extended_no_of_addressable_sectors;
UINT16 min_number_per_download_microcode_mode3; ///< word 234
UINT16 max_number_per_download_microcode_mode3; ///< word 235
UINT16 reserved_236_254[19];
UINT16 integrity_word;
} ATA_IDENTIFY_DATA;
///
/// ATAPI_IDENTIFY_DATA strictly complies with ATA/ATAPI-8 Spec
/// to define the data returned by an ATAPI device upon successful
/// completion of the ATA IDENTIFY_PACKET_DEVICE command.
///
typedef struct {
UINT16 config; ///< General Configuration.
UINT16 reserved_1;
UINT16 specific_config; ///< Specific Configuration.
UINT16 reserved_3_9[7];
CHAR8 SerialNo[20]; ///< word 10~19
UINT16 reserved_20_22[3];
CHAR8 FirmwareVer[8]; ///< word 23~26
CHAR8 ModelName[40]; ///< word 27~46
UINT16 reserved_47_48[2];
UINT16 capabilities_49;
UINT16 capabilities_50;
UINT16 obsolete_51;
UINT16 reserved_52;
UINT16 field_validity; ///< word 53
UINT16 reserved_54_61[8];
UINT16 dma_dir;
UINT16 multi_word_dma_mode; ///< word 63
UINT16 advanced_pio_modes; ///< word 64
UINT16 min_multi_word_dma_cycle_time;
UINT16 rec_multi_word_dma_cycle_time;
UINT16 min_pio_cycle_time_without_flow_control;
UINT16 min_pio_cycle_time_with_flow_control;
UINT16 reserved_69_70[2];
UINT16 obsolete_71_72[2];
UINT16 reserved_73_74[2];
UINT16 obsolete_75;
UINT16 serial_ata_capabilities;
UINT16 reserved_77; ///< Reserved for Serial ATA
UINT16 serial_ata_features_supported;
UINT16 serial_ata_features_enabled;
UINT16 major_version_no; ///< word 80
UINT16 minor_version_no; ///< word 81
UINT16 cmd_set_support_82;
UINT16 cmd_set_support_83;
UINT16 cmd_feature_support;
UINT16 cmd_feature_enable_85;
UINT16 cmd_feature_enable_86;
UINT16 cmd_feature_default;
UINT16 ultra_dma_select;
UINT16 time_required_for_sec_erase; ///< word 89
UINT16 time_required_for_enhanced_sec_erase; ///< word 90
UINT16 advanced_power_management_level;
UINT16 master_pwd_revison_code;
UINT16 hardware_reset_result; ///< word 93
UINT16 obsolete_94;
UINT16 reserved_95_107[13];
UINT16 world_wide_name[4]; ///< word 108~111
UINT16 reserved_for_128bit_wwn_112_115[4];
UINT16 reserved_116_118[3];
UINT16 command_and_feature_sets_supported; ///< word 119
UINT16 command_and_feature_sets_supported_enabled;
UINT16 reserved_121_124[4];
UINT16 atapi_byte_count_0_behavior; ///< word 125
UINT16 obsolete_126_127[2];
UINT16 security_status;
UINT16 reserved_129_159[31];
UINT16 cfa_reserved_160_175[16];
UINT16 reserved_176_221[46];
UINT16 transport_major_version;
UINT16 transport_minor_version;
UINT16 reserved_224_254[31];
UINT16 integrity_word;
} ATAPI_IDENTIFY_DATA;
///
/// Standard Quiry Data format, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
///
typedef struct {
UINT8 peripheral_type;
UINT8 RMB;
UINT8 version;
UINT8 response_data_format;
UINT8 addnl_length; ///< n - 4, Numbers of bytes following this one.
UINT8 reserved_5;
UINT8 reserved_6;
UINT8 reserved_7;
UINT8 vendor_info[8];
UINT8 product_id[16];
UINT8 product_revision_level[4];
UINT8 vendor_specific_36_55[55 - 36 + 1];
UINT8 reserved_56_95[95 - 56 + 1];
///
/// Vendor-specific parameters fields. The sizeof (ATAPI_INQUIRY_DATA) is 254
/// since allocation_length is one byte in ATAPI_INQUIRY_CMD.
///
UINT8 vendor_specific_96_253[253 - 96 + 1];
} ATAPI_INQUIRY_DATA;
///
/// Request Sense Standard Data, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
///
typedef struct {
UINT8 error_code : 7;
UINT8 valid : 1;
UINT8 reserved_1;
UINT8 sense_key : 4;
UINT8 reserved_2 : 1;
UINT8 Vendor_specifc_1 : 3;
UINT8 vendor_specific_3;
UINT8 vendor_specific_4;
UINT8 vendor_specific_5;
UINT8 vendor_specific_6;
UINT8 addnl_sense_length; ///< n - 7
UINT8 vendor_specific_8;
UINT8 vendor_specific_9;
UINT8 vendor_specific_10;
UINT8 vendor_specific_11;
UINT8 addnl_sense_code; ///< mandatory
UINT8 addnl_sense_code_qualifier; ///< mandatory
UINT8 field_replaceable_unit_code; ///< optional
UINT8 sense_key_specific_15 : 7;
UINT8 SKSV : 1;
UINT8 sense_key_specific_16;
UINT8 sense_key_specific_17;
} ATAPI_REQUEST_SENSE_DATA;
///
/// READ CAPACITY Data, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
///
typedef struct {
UINT8 LastLba3;
UINT8 LastLba2;
UINT8 LastLba1;
UINT8 LastLba0;
UINT8 BlockSize3;
UINT8 BlockSize2;
UINT8 BlockSize1;
UINT8 BlockSize0;
} ATAPI_READ_CAPACITY_DATA;
///
/// Capacity List Header + Current/Maximum Capacity Descriptor,
/// defined in SFF-8070i(ATAPI Removable Rewritable Specification).
///
typedef struct {
UINT8 reserved_0;
UINT8 reserved_1;
UINT8 reserved_2;
UINT8 Capacity_Length;
UINT8 LastLba3;
UINT8 LastLba2;
UINT8 LastLba1;
UINT8 LastLba0;
UINT8 DesCode : 2;
UINT8 reserved_9 : 6;
UINT8 BlockSize2;
UINT8 BlockSize1;
UINT8 BlockSize0;
} ATAPI_READ_FORMAT_CAPACITY_DATA;
///
/// Test Unit Ready Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
///
typedef struct {
UINT8 opcode;
UINT8 reserved_1;
UINT8 reserved_2;
UINT8 reserved_3;
UINT8 reserved_4;
UINT8 reserved_5;
UINT8 reserved_6;
UINT8 reserved_7;
UINT8 reserved_8;
UINT8 reserved_9;
UINT8 reserved_10;
UINT8 reserved_11;
} ATAPI_TEST_UNIT_READY_CMD;
///
/// INQUIRY Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
///
typedef struct {
UINT8 opcode;
UINT8 reserved_1 : 5;
UINT8 lun : 3;
UINT8 page_code; ///< defined in SFF8090i, V6
UINT8 reserved_3;
UINT8 allocation_length;
UINT8 reserved_5;
UINT8 reserved_6;
UINT8 reserved_7;
UINT8 reserved_8;
UINT8 reserved_9;
UINT8 reserved_10;
UINT8 reserved_11;
} ATAPI_INQUIRY_CMD;
///
/// REQUEST SENSE Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
///
typedef struct {
UINT8 opcode;
UINT8 reserved_1 : 5;
UINT8 lun : 3;
UINT8 reserved_2;
UINT8 reserved_3;
UINT8 allocation_length;
UINT8 reserved_5;
UINT8 reserved_6;
UINT8 reserved_7;
UINT8 reserved_8;
UINT8 reserved_9;
UINT8 reserved_10;
UINT8 reserved_11;
} ATAPI_REQUEST_SENSE_CMD;
///
/// READ (10) Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
///
typedef struct {
UINT8 opcode;
UINT8 reserved_1 : 5;
UINT8 lun : 3;
UINT8 Lba0;
UINT8 Lba1;
UINT8 Lba2;
UINT8 Lba3;
UINT8 reserved_6;
UINT8 TranLen0;
UINT8 TranLen1;
UINT8 reserved_9;
UINT8 reserved_10;
UINT8 reserved_11;
} ATAPI_READ10_CMD;
///
/// READ Format Capacity Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
///
typedef struct {
UINT8 opcode;
UINT8 reserved_1 : 5;
UINT8 lun : 3;
UINT8 reserved_2;
UINT8 reserved_3;
UINT8 reserved_4;
UINT8 reserved_5;
UINT8 reserved_6;
UINT8 allocation_length_hi;
UINT8 allocation_length_lo;
UINT8 reserved_9;
UINT8 reserved_10;
UINT8 reserved_11;
} ATAPI_READ_FORMAT_CAP_CMD;
///
/// MODE SENSE Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
///
typedef struct {
UINT8 opcode;
UINT8 reserved_1 : 5;
UINT8 lun : 3;
UINT8 page_code : 6;
UINT8 page_control : 2;
UINT8 reserved_3;
UINT8 reserved_4;
UINT8 reserved_5;
UINT8 reserved_6;
UINT8 parameter_list_length_hi;
UINT8 parameter_list_length_lo;
UINT8 reserved_9;
UINT8 reserved_10;
UINT8 reserved_11;
} ATAPI_MODE_SENSE_CMD;
///
/// ATAPI_PACKET_COMMAND is not defined in the ATA specification.
/// We add it here for the convenience of ATA/ATAPI module writers.
///
typedef union {
UINT16 Data16[6];
ATAPI_TEST_UNIT_READY_CMD TestUnitReady;
ATAPI_READ10_CMD Read10;
ATAPI_REQUEST_SENSE_CMD RequestSence;
ATAPI_INQUIRY_CMD Inquiry;
ATAPI_MODE_SENSE_CMD ModeSense;
ATAPI_READ_FORMAT_CAP_CMD ReadFormatCapacity;
} ATAPI_PACKET_COMMAND;
#pragma pack()
#define ATAPI_MAX_DMA_EXT_CMD_SECTORS 0x10000
#define ATAPI_MAX_DMA_CMD_SECTORS 0x100
// ATA/ATAPI Signature equates
#define ATA_SIGNATURE 0x0101 ///< defined in ACS-3
#define ATAPI_SIGNATURE 0xeb14 ///< defined in ACS-3
#define ATAPI_SIGNATURE_32 0xeb140101 ///< defined in ACS-3
// Spin Up Configuration definitions
#define ATA_SPINUP_CFG_REQUIRED_IDD_INCOMPLETE 0x37c8 ///< defined in ACS-3
#define ATA_SPINUP_CFG_REQUIRED_IDD_COMPLETE 0x738c ///< defined in ACS-3
#define ATA_SPINUP_CFG_NOT_REQUIRED_IDD_INCOMPLETE 0x8c73 ///< defined in ACS-3
#define ATA_SPINUP_CFG_NOT_REQUIRED_IDD_COMPLETE 0xc837 ///< defined in ACS-3
//
// ATA Packet Command Code
//
#define ATA_CMD_FORMAT_UNIT 0x04 ///< defined in ATAPI Removable Rewritable Media Devcies
#define ATA_CMD_SOFT_RESET 0x08 ///< defined from ATA-3
#define ATA_CMD_PACKET 0xA0 ///< defined from ATA-3
#define ATA_CMD_IDENTIFY_DEVICE 0xA1 ///< defined from ATA-3
#define ATA_CMD_SERVICE 0xA2 ///< defined from ATA-3
#define ATA_CMD_TEST_UNIT_READY 0x00 ///< defined from ATA-1
#define ATA_CMD_REQUEST_SENSE 0x03 ///< defined from ATA-4
#define ATA_CMD_INQUIRY 0x12 ///< defined in ATAPI Removable Rewritable Media Devcies
#define ATA_CMD_READ_FORMAT_CAPACITY 0x23 ///< defined in ATAPI Removable Rewritable Media Devcies
#define ATA_CMD_READ_CAPACITY 0x25 ///< defined in ATAPI Removable Rewritable Media Devcies
#define ATA_CMD_READ_10 0x28 ///< defined in ATAPI Removable Rewritable Media Devcies
#define ATA_CMD_WRITE_10 0x2A ///< defined in ATAPI Removable Rewritable Media Devcies
#define ATA_CMD_ATAPI_SEEK 0x2B ///< defined in ATAPI Removable Rewritable Media Devcies
#define ATA_CMD_WRITE_AND_VERIFY 0x2E ///< defined in ATAPI Removable Rewritable Media Devcies
#define ATA_CMD_VERIFY 0x2F ///< defined in ATAPI Removable Rewritable Media Devcies
#define ATA_CMD_READ_12 0xA8 ///< defined in ATAPI Removable Rewritable Media Devcies
#define ATA_CMD_WRITE_12 0xAA ///< defined in ATAPI Removable Rewritable Media Devcies
#define ATA_CMD_START_STOP_UNIT 0x1B ///< defined in ATAPI Removable Rewritable Media Devcies
#define ATA_CMD_PREVENT_ALLOW_MEDIA_REMOVAL 0x1E ///< defined in ATAPI Removable Rewritable Media Devcies
#define ATA_CMD_MODE_SELECT 0x55 ///< defined in ATAPI Removable Rewritable Media Devcies
#define ATA_CMD_MODE_SENSE 0x5A ///< defined in ATAPI Removable Rewritable Media Devcies
#define ATA_PAGE_CODE_READ_WRITE_ERROR 0x01 ///< defined in ATAPI Removable Rewritable Media Devcies
#define ATA_PAGE_CODE_CACHING_PAGE 0x08 ///< defined in ATAPI Removable Rewritable Media Devcies
#define ATA_PAGE_CODE_REMOVABLE_BLOCK_CAPABILITIES 0x1B ///< defined in ATAPI Removable Rewritable Media Devcies
#define ATA_PAGE_CODE_TIMER_PROTECT_PAGE 0x1C ///< defined in ATAPI Removable Rewritable Media Devcies
#define ATA_PAGE_CODE_RETURN_ALL_PAGES 0x3F ///< defined in ATAPI Removable Rewritable Media Devcies
#define ATA_CMD_GET_CONFIGURATION 0x46 ///< defined in ATAPI Multimedia Devices
#define ATA_GCCD_RT_FIELD_VALUE_ALL 0x00 ///< defined in ATAPI Multimedia Devices
#define ATA_GCCD_RT_FIELD_VALUE_CURRENT 0x01 ///< defined in ATAPI Multimedia Devices
#define ATA_GCCD_RT_FIELD_VALUE_SINGLE 0x02 ///< defined in ATAPI Multimedia Devices
#define ATA_GCCD_RT_FIELD_VALUE_RESERVED 0x03 ///< defined in ATAPI Multimedia Devices
#define ATA_FEATURE_LIST_PROFILE_LIST 0x0000 ///< defined in ATAPI Multimedia Devices
#define ATA_FEATURE_LIST_CORE 0x0001 ///< defined in ATAPI Multimedia Devices
#define ATA_FEATURE_LIST_MORPHING 0x0002 ///< defined in ATAPI Multimedia Devices
#define ATA_FEATURE_LIST_REMOVEABLE_MEDIUM 0x0003 ///< defined in ATAPI Multimedia Devices
#define ATA_FEATURE_LIST_WRITE_PROTECT 0x0004 ///< defined in ATAPI Multimedia Devices
///
/// Start/Stop and Eject Operations
///
///@{
#define ATA_CMD_SUBOP_STOP_DISC 0x00 ///< Stop the Disc
#define ATA_CMD_SUBOP_START_DISC 0x01 ///< Start the Disc and acquire the format type
#define ATA_CMD_SUBOP_EJECT_DISC 0x02 ///< Eject the Disc if possible
#define ATA_CMD_SUBOP_CLOSE_TRAY 0x03 ///< Load the Disc (Close Tray)
///@}
//
// ATA Commands Code
//
//
// Class 1: PIO Data-In Commands
//
#define ATA_CMD_IDENTIFY_DRIVE 0xec ///< defined from ATA-3
#define ATA_CMD_READ_BUFFER 0xe4 ///< defined from ATA-1
#define ATA_CMD_READ_SECTORS 0x20 ///< defined from ATA-1
#define ATA_CMD_READ_SECTORS_WITH_RETRY 0x21 ///< defined from ATA-1, obsoleted from ATA-5
#define ATA_CMD_READ_LONG 0x22 ///< defined from ATA-1, obsoleted from ATA-5
#define ATA_CMD_READ_LONG_WITH_RETRY 0x23 ///< defined from ATA-1, obsoleted from ATA-5
#define ATA_CMD_READ_SECTORS_EXT 0x24 ///< defined from ATA-6
#define ATA_CMD_READ_MULTIPLE 0xc4 ///< defined in ACS-3
#define ATA_CMD_READ_MULTIPLE_EXT 0x29 ///< defined in ACS-3
#define ATA_CMD_READ_LOG_EXT 0x2f ///< defined in ACS-3
//
// Class 2: PIO Data-Out Commands
//
#define ATA_CMD_FORMAT_TRACK 0x50 ///< defined from ATA-1, obsoleted from ATA-4
#define ATA_CMD_WRITE_BUFFER 0xe8 ///< defined from ATA-1
#define ATA_CMD_WRITE_SECTORS 0x30 ///< defined from ATA-1
#define ATA_CMD_WRITE_SECTORS_WITH_RETRY 0x31 ///< defined from ATA-1, obsoleted from ATA-5
#define ATA_CMD_WRITE_LONG 0x32 ///< defined from ATA-1, obsoleted from ATA-5
#define ATA_CMD_WRITE_LONG_WITH_RETRY 0x33 ///< defined from ATA-1, obsoleted from ATA-5
#define ATA_CMD_WRITE_VERIFY 0x3c ///< defined from ATA-1, obsoleted from ATA-5
#define ATA_CMD_WRITE_SECTORS_EXT 0x34 ///< defined from ATA-6
#define ATA_CMD_WRITE_MULTIPLE 0xc5 ///< defined in ACS-3
#define ATA_CMD_WRITE_MULTIPLE_EXT 0x39 ///< defined in ACS-3
//
// Class 3 No Data Command
//
#define ATA_CMD_ACK_MEDIA_CHANGE 0xdb ///< defined from ATA-1, obsoleted from ATA-5
#define ATA_CMD_BOOT_POST_BOOT 0xdc ///< defined from ATA-1, obsoleted from ATA-3
#define ATA_CMD_BOOT_PRE_BOOT 0xdd ///< defined from ATA-1, obsoleted from ATA-3
#define ATA_CMD_CHECK_POWER_MODE 0x98 ///< defined from ATA-1, obsoleted from ATA-4
#define ATA_CMD_CHECK_POWER_MODE_ALIAS 0xe5 ///< defined from ATA-1
#define ATA_CMD_DOOR_LOCK 0xde ///< defined from ATA-1
#define ATA_CMD_DOOR_UNLOCK 0xdf ///< defined from ATA-1
#define ATA_CMD_EXEC_DRIVE_DIAG 0x90 ///< defined from ATA-1
#define ATA_CMD_IDLE_ALIAS 0x97 ///< defined from ATA-1, obsoleted from ATA-4
#define ATA_CMD_IDLE 0xe3 ///< defined from ATA-1
#define ATA_CMD_IDLE_IMMEDIATE 0x95 ///< defined from ATA-1, obsoleted from ATA-4
#define ATA_CMD_IDLE_IMMEDIATE_ALIAS 0xe1 ///< defined from ATA-1
#define ATA_CMD_INIT_DRIVE_PARAM 0x91 ///< defined from ATA-1, obsoleted from ATA-6
#define ATA_CMD_RECALIBRATE 0x10 ///< defined from ATA-1, obsoleted from ATA-4
#define ATA_CMD_READ_DRIVE_STATE 0xe9 ///< defined from ATA-1, obsoleted from ATA-3
#define ATA_CMD_SET_MULTIPLE_MODE 0xC6 ///< defined from ATA-2
#define ATA_CMD_READ_VERIFY 0x40 ///< defined from ATA-1
#define ATA_CMD_READ_VERIFY_WITH_RETRY 0x41 ///< defined from ATA-1, obsoleted from ATA-5
#define ATA_CMD_SEEK 0x70 ///< defined from ATA-1
#define ATA_CMD_SET_FEATURES 0xef ///< defined from ATA-1
#define ATA_CMD_STANDBY 0x96 ///< defined from ATA-1, obsoleted from ATA-4
#define ATA_CMD_STANDBY_ALIAS 0xe2 ///< defined from ATA-1
#define ATA_CMD_STANDBY_IMMEDIATE 0x94 ///< defined from ATA-1, obsoleted from ATA-4
#define ATA_CMD_STANDBY_IMMEDIATE_ALIAS 0xe0 ///< defined from ATA-1
#define ATA_CMD_SLEEP 0xe6 ///< defined in ACS-3
#define ATA_CMD_READ_NATIVE_MAX_ADDRESS 0xf8 ///< defined in ATA-6
#define ATA_CMD_READ_NATIVE_MAX_ADDRESS_EXT 0x27 ///< defined in ATA-6
//
// Set Features Sub Command
//
#define ATA_SUB_CMD_ENABLE_VOLATILE_WRITE_CACHE 0x02 ///< defined in ACS-3
#define ATA_SUB_CMD_SET_TRANSFER_MODE 0x03 ///< defined in ACS-3
#define ATA_SUB_CMD_ENABLE_APM 0x05 ///< defined in ACS-3
#define ATA_SUB_CMD_ENABLE_PUIS 0x06 ///< defined in ACS-3
#define ATA_SUB_CMD_PUIS_SET_DEVICE_SPINUP 0x07 ///< defined in ACS-3
#define ATA_SUB_CMD_ENABLE_WRITE_READ_VERIFY 0x0b ///< defined in ACS-3
#define ATA_SUB_CMD_ENABLE_SATA_FEATURE 0x10 ///< defined in ACS-3
#define ATA_SUB_CMD_DISABLE_MEDIA_STATUS_NOTIFICATION 0x31 ///< defined in ACS-3
#define ATA_SUB_CMD_ENABLE_FREE_FALL_CONTROL 0x41 ///< defined in ACS-3
#define ATA_SUB_CMD_ACOUSTIC_MANAGEMENT_ENABLE 0x42 ///< defined in ACS-3
#define ATA_SUB_CMD_SET_MAX_HOST_INTERFACE_SECTOR_TIMES 0x43 ///< defined in ACS-3
#define ATA_SUB_CMD_EXTENDED_POWER_CONDITIONS 0x4a ///< defined in ACS-3
#define ATA_SUB_CMD_DISABLE_READ_LOOK_AHEAD 0x55 ///< defined in ACS-3
#define ATA_SUB_CMD_EN_DIS_DSN_FEATURE 0x63 ///< defined in ACS-3
#define ATA_SUB_CMD_DISABLE_REVERT_TO_POWER_ON_DEFAULTS 0x66 ///< defined in ACS-3
#define ATA_SUB_CMD_DISABLE_VOLATILE_WRITE_CACHE 0x82 ///< defined in ACS-3
#define ATA_SUB_CMD_DISABLE_APM 0x85 ///< defined in ACS-3
#define ATA_SUB_CMD_DISABLE_PUIS 0x86 ///< defined in ACS-3
#define ATA_SUB_CMD_DISABLE_WRITE_READ_VERIFY 0x8b ///< defined in ACS-3
#define ATA_SUB_CMD_DISABLE_SATA_FEATURE 0x90 ///< defined in ACS-3
#define ATA_SUB_CMD_ENABLE_MEDIA_STATUS_NOTIFICATION 0x95 ///< defined in ACS-3
#define ATA_SUB_CMD_ENABLE_READ_LOOK_AHEAD 0xaa ///< defined in ACS-3
#define ATA_SUB_CMD_DISABLE_FREE_FALL_CONTROL 0xc1 ///< defined in ACS-3
#define ATA_SUB_CMD_ACOUSTIC_MANAGEMENT_DISABLE 0xc2 ///< defined in ACS-3
#define ATA_SUB_CMD_EN_DIS_SENSE_DATA_REPORTING 0xc3 ///< defined in ACS-3
#define ATA_SUB_CMD_ENABLE_REVERT_TO_POWER_ON_DEFAULTS 0xcc ///< defined in ACS-3
//
// S.M.A.R.T
//
#define ATA_CMD_SMART 0xb0 ///< defined from ATA-3
#define ATA_CONSTANT_C2 0xc2 ///< reserved
#define ATA_CONSTANT_4F 0x4f ///< reserved
#define ATA_SMART_READ_DATA 0xd0 ///< defined in ACS-3
#define ATA_SMART_AUTOSAVE 0xd2 ///< defined in ACS-3
#define ATA_AUTOSAVE_DISABLE_ATTR 0x00
#define ATA_AUTOSAVE_ENABLE_ATTR 0xf1
#define ATA_SMART_EXECUTE_OFFLINE_IMMEDIATE 0xd4 ///< defined in ACS-3
#define ATA_EXECUTE_SMART_OFFLINE_ROUTINE 0x00 ///< defined in ACS-3
#define ATA_EXECUTE_SMART_OFFLINE_SHORT_SELFTEST 0x01 ///< defined in ACS-3
#define ATA_EXECUTE_SMART_OFFLINE_EXTENDED_SELFTEST 0x02 ///< defined in ACS-3
#define ATA_EXECUTE_SMART_OFFLINE_CONVEYANCE_SELFTEST 0x03 ///< defined in ACS-3
#define ATA_EXECUTE_SMART_OFFLINE_SELECTIVE_SELFTEST 0x04 ///< defined in ACS-3
#define ATA_SMART_ABORT_SELF_TEST_SUBROUTINE 0x7f ///< defined in ACS-3
#define ATA_EXECUTE_SMART_CAPTIVE_SHORT_SELFTEST 0x81 ///< defined in ACS-3
#define ATA_EXECUTE_SMART_CAPTIVE_EXTENDED_SELFTEST 0x82 ///< defined in ACS-3
#define ATA_EXECUTE_SMART_CAPTIVE_CONVEYANCE_SELFTEST 0x83 ///< defined in ACS-3
#define ATA_EXECUTE_SMART_CAPTIVE_SELECTIVE_SELFTEST 0x84 ///< defined in ACS-3
#define ATA_SMART_READLOG 0xd5 ///< defined in ACS-3
#define ATA_SMART_WRITELOG 0xd6 ///< defined in ACS-3
#define ATA_SMART_ENABLE_OPERATION 0xd8 ///< reserved
#define ATA_SMART_DISABLE_OPERATION 0xd9 ///< defined in ACS-3
#define ATA_SMART_RETURN_STATUS 0xda ///< defined from ATA-3
#define ATA_SMART_THRESHOLD_NOT_EXCEEDED_VALUE 0xc24f ///< defined in ACS-3
#define ATA_SMART_THRESHOLD_EXCEEDED_VALUE 0x2cf4 ///< defined in ACS-3
// SMART Log Definitions
#define ATA_SMART_LOG_DIRECTORY 0x00 ///< defined in ACS-3
#define ATA_SMART_SUM_SMART_ERROR_LOG 0x01 ///< defined in ACS-3
#define ATA_SMART_COMP_SMART_ERROR_LOG 0x02 ///< defined in ACS-3
#define ATA_SMART_EXT_COMP_SMART_ERROR_LOG 0x03 ///< defined in ACS-3
#define ATA_SMART_SMART_SELFTEST_LOG 0x06 ///< defined in ACS-3
#define ATA_SMART_EXT_SMART_SELFTEST_LOG 0x07 ///< defined in ACS-3
#define ATA_SMART_SELECTIVE_SELFTEST_LOG 0x09 ///< defined in ACS-3
#define ATA_SMART_HOST_VENDOR_SPECIFIC 0x80 ///< defined in ACS-3
#define ATA_SMART_DEVICE_VENDOR_SPECIFIC 0xa0 ///< defined in ACS-3
//
// Class 4: DMA Command
//
#define ATA_CMD_READ_DMA 0xc8 ///< defined from ATA-1
#define ATA_CMD_READ_DMA_WITH_RETRY 0xc9 ///< defined from ATA-1, obsoleted from ATA-5
#define ATA_CMD_READ_DMA_EXT 0x25 ///< defined from ATA-6
#define ATA_CMD_WRITE_DMA 0xca ///< defined from ATA-1
#define ATA_CMD_WRITE_DMA_WITH_RETRY 0xcb ///< defined from ATA-1, obsoleted from ATA-
#define ATA_CMD_WRITE_DMA_EXT 0x35 ///< defined from ATA-6
//
// ATA Security commands
//
#define ATA_CMD_SECURITY_SET_PASSWORD 0xf1 ///< defined in ACS-3
#define ATA_CMD_SECURITY_UNLOCK 0xf2 ///< defined in ACS-3
#define ATA_CMD_SECURITY_ERASE_PREPARE 0xf3 ///< defined in ACS-3
#define ATA_CMD_SECURITY_ERASE_UNIT 0xf4 ///< defined in ACS-3
#define ATA_CMD_SECURITY_FREEZE_LOCK 0xf5 ///< defined in ACS-3
#define ATA_CMD_SECURITY_DISABLE_PASSWORD 0xf6 ///< defined in ACS-3
#define ATA_SECURITY_BUFFER_LENGTH 512 ///< defined in ACS-3
//
// ATA Device Config Overlay
//
#define ATA_CMD_DEV_CONFIG_OVERLAY 0xb1 ///< defined from ATA-6
#define ATA_CMD_DEV_CONFIG_RESTORE_FEATURE 0xc0 ///< defined from ATA-6
#define ATA_CMD_DEV_CONFIG_FREEZELOCK_FEATURE 0xc1 ///< defined from ATA-6
#define ATA_CMD_DEV_CONFIG_IDENTIFY_FEATURE 0xc2 ///< defined from ATA-6
#define ATA_CMD_DEV_CONFIG_SET_FEATURE 0xc3 ///< defined from ATA-6
//
// ATA Trusted Computing Feature Set Commands
//
#define ATA_CMD_TRUSTED_NON_DATA 0x5b ///< defined in ACS-3
#define ATA_CMD_TRUSTED_RECEIVE 0x5c ///< defined in ACS-3
#define ATA_CMD_TRUSTED_RECEIVE_DMA 0x5d ///< defined in ACS-3
#define ATA_CMD_TRUSTED_SEND 0x5e ///< defined in ACS-3
#define ATA_CMD_TRUSTED_SEND_DMA 0x5f ///< defined in ACS-3
//
// ATA Trusted Receive Fields
//
#define ATA_TR_RETURN_SECURITY_PROTOCOL_INFORMATION 0x00 ///< defined in ACS-3
#define ATA_TR_SECURITY_PROTOCOL_JEDEC_RESERVED 0xec ///< defined in ACS-3
#define ATA_TR_SECURITY_PROTOCOL_SDCARD_RESERVED 0xed ///< defined in ACS-3
#define ATA_TR_SECURITY_PROTOCOL_IEEE1667_RESERVED 0xee ///< defined in ACS-3
//
// Equates used for Acoustic Flags
//
#define ATA_ACOUSTIC_LEVEL_BYPASS 0xff ///< defined from ATA-6
#define ATA_ACOUSTIC_LEVEL_MAXIMUM_PERFORMANCE 0xfe ///< defined from ATA-6
#define ATA_ACOUSTIC_LEVEL_QUIET 0x80 ///< defined from ATA-6
//
// Equates used for DiPM Support
//
#define ATA_CMD_DIPM_SUB 0x03 // defined in ACS-3 : Count value in SetFeature identification : 03h Device-initiated interface power state transitions
#define ATA_DIPM_ENABLE 0x10 // defined in ACS-3
#define ATA_DIPM_DISABLE 0x90 // defined in ACS-3
//
// Equates used for DevSleep Support
//
#define ATA_CMD_DEVSLEEP_SUB 0x09 // defined in SATA 3.2 Gold Spec : Count value in SetFeature identification : 09h Device Sleep
#define ATA_DEVSLEEP_ENABLE 0x10 // defined in SATA 3.2 Gold Spec
#define ATA_DEVSLEEP_DISABLE 0x90 // defined in SATA 3.2 Gold Spec
#define ATA_DEVSLP_EXIT_TIMEOUT 20 // MDAT - 20 ms
#define ATA_DEVSLP_MINIMUM_DETECTION_TIME 10 // DMDT - 10 us
#define ATA_DEVSLP_MINIMUM_ASSERTION_TIME 10 // DETO - 10 ms
//
// Set MAX Commands
//
#define ATA_CMD_SET_MAX_ADDRESS_EXT 0x37 ///< defined from ATA-6
#define ATA_CMD_SET_MAX_ADDRESS 0xf9 ///< defined from ATA-6
#define ATA_SET_MAX_SET_PASSWORD 0x01 ///< defined from ATA-6
#define ATA_SET_MAX_LOCK 0x02 ///< defined from ATA-6
#define ATA_SET_MAX_UNLOCK 0x03 ///< defined from ATA-6
#define ATA_SET_MAX_FREEZE_LOCK 0x04 ///< defined from ATA-6
///
/// Default content of device control register, disable INT,
/// Bit3 is set to 1 according ATA-1
///
#define ATA_DEFAULT_CTL (0x0a)
///
/// Default context of Device/Head Register,
/// Bit7 and Bit5 are set to 1 for back-compatibilities.
///
#define ATA_DEFAULT_CMD (0xa0)
#define ATAPI_MAX_BYTE_COUNT (0xfffe)
#define ATA_REQUEST_SENSE_ERROR (0x70) ///< defined in SFF-8070i
//
// Sense Key, Additional Sense Codes and Additional Sense Code Qualifier
// defined in MultiMedia Commands (MMC, MMC-2)
//
// Sense Key
//
#define ATA_SK_NO_SENSE (0x0)
#define ATA_SK_RECOVERY_ERROR (0x1)
#define ATA_SK_NOT_READY (0x2)
#define ATA_SK_MEDIUM_ERROR (0x3)
#define ATA_SK_HARDWARE_ERROR (0x4)
#define ATA_SK_ILLEGAL_REQUEST (0x5)
#define ATA_SK_UNIT_ATTENTION (0x6)
#define ATA_SK_DATA_PROTECT (0x7)
#define ATA_SK_BLANK_CHECK (0x8)
#define ATA_SK_VENDOR_SPECIFIC (0x9)
#define ATA_SK_RESERVED_A (0xA)
#define ATA_SK_ABORT (0xB)
#define ATA_SK_RESERVED_C (0xC)
#define ATA_SK_OVERFLOW (0xD)
#define ATA_SK_MISCOMPARE (0xE)
#define ATA_SK_RESERVED_F (0xF)
//
// Additional Sense Codes
//
#define ATA_ASC_NOT_READY (0x04)
#define ATA_ASC_MEDIA_ERR1 (0x10)
#define ATA_ASC_MEDIA_ERR2 (0x11)
#define ATA_ASC_MEDIA_ERR3 (0x14)
#define ATA_ASC_MEDIA_ERR4 (0x30)
#define ATA_ASC_MEDIA_UPSIDE_DOWN (0x06)
#define ATA_ASC_INVALID_CMD (0x20)
#define ATA_ASC_LBA_OUT_OF_RANGE (0x21)
#define ATA_ASC_INVALID_FIELD (0x24)
#define ATA_ASC_WRITE_PROTECTED (0x27)
#define ATA_ASC_MEDIA_CHANGE (0x28)
#define ATA_ASC_RESET (0x29) ///< Power On Reset or Bus Reset occurred.
#define ATA_ASC_ILLEGAL_FIELD (0x26)
#define ATA_ASC_NO_MEDIA (0x3A)
#define ATA_ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64)
//
// Additional Sense Code Qualifier
//
#define ATA_ASCQ_IN_PROGRESS (0x01)
//
// Error Register
//
#define ATA_ERRREG_BBK BIT7 ///< Bad block detected defined from ATA-1, obsoleted from ATA-2
#define ATA_ERRREG_UNC BIT6 ///< Uncorrectable Data defined from ATA-1, obsoleted from ATA-4
#define ATA_ERRREG_MC BIT5 ///< Media Change defined from ATA-1, obsoleted from ATA-4
#define ATA_ERRREG_IDNF BIT4 ///< ID Not Found defined from ATA-1, obsoleted from ATA-4
#define ATA_ERRREG_MCR BIT3 ///< Media Change Requested defined from ATA-1, obsoleted from ATA-4
#define ATA_ERRREG_ABRT BIT2 ///< Aborted Command defined from ATA-1
#define ATA_ERRREG_TK0NF BIT1 ///< Track 0 Not Found defined from ATA-1, obsoleted from ATA-4
#define ATA_ERRREG_AMNF BIT0 ///< Address Mark Not Found defined from ATA-1, obsoleted from ATA-4
//
// Status Register
//
#define ATA_STSREG_BSY BIT7 ///< Controller Busy defined from ATA-1
#define ATA_STSREG_DRDY BIT6 ///< Drive Ready defined from ATA-1
#define ATA_STSREG_DWF BIT5 ///< Drive Write Fault defined from ATA-1, obsoleted from ATA-4
#define ATA_STSREG_DF BIT5 ///< Drive Fault defined from ATA-6
#define ATA_STSREG_DSC BIT4 ///< Disk Seek Complete defined from ATA-1, obsoleted from ATA-4
#define ATA_STSREG_DRQ BIT3 ///< Data Request defined from ATA-1
#define ATA_STSREG_CORR BIT2 ///< Corrected Data defined from ATA-1, obsoleted from ATA-4
#define ATA_STSREG_IDX BIT1 ///< Index defined from ATA-1, obsoleted from ATA-4
#define ATA_STSREG_ERR BIT0 ///< Error defined from ATA-1
//
// Device Control Register
//
#define ATA_CTLREG_SRST BIT2 ///< Software Reset.
#define ATA_CTLREG_IEN_L BIT1 ///< Interrupt Enable #.
#endif

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/** @file
This file contains the Bluetooth definitions that are consumed by drivers.
These definitions are from Bluetooth Core Specification Version 4.0 June, 2010
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _BLUETOOTH_H_
#define _BLUETOOTH_H_
#pragma pack(1)
///
/// BLUETOOTH_ADDRESS
///
typedef struct {
///
/// 48bit Bluetooth device address.
///
UINT8 Address[6];
} BLUETOOTH_ADDRESS;
///
/// BLUETOOTH_CLASS_OF_DEVICE. See Bluetooth specification for detail.
///
typedef struct {
UINT8 FormatType:2;
UINT8 MinorDeviceClass: 6;
UINT16 MajorDeviceClass: 5;
UINT16 MajorServiceClass:11;
} BLUETOOTH_CLASS_OF_DEVICE;
#pragma pack()
#define BLUETOOTH_HCI_COMMAND_LOCAL_READABLE_NAME_MAX_SIZE 248
#define BLUETOOTH_HCI_LINK_KEY_SIZE 16
#endif

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/** @file
This file defines BMP file header data structures.
Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _BMP_H_
#define _BMP_H_
#pragma pack(1)
typedef struct {
UINT8 Blue;
UINT8 Green;
UINT8 Red;
UINT8 Reserved;
} BMP_COLOR_MAP;
typedef struct {
CHAR8 CharB;
CHAR8 CharM;
UINT32 Size;
UINT16 Reserved[2];
UINT32 ImageOffset;
UINT32 HeaderSize;
UINT32 PixelWidth;
UINT32 PixelHeight;
UINT16 Planes; ///< Must be 1
UINT16 BitPerPixel; ///< 1, 4, 8, or 24
UINT32 CompressionType;
UINT32 ImageSize; ///< Compressed image size in bytes
UINT32 XPixelsPerMeter;
UINT32 YPixelsPerMeter;
UINT32 NumberOfColors;
UINT32 ImportantColors;
} BMP_IMAGE_HEADER;
#pragma pack()
#endif

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/** @file
ACPI debug port 2 table definition, defined at
Microsoft DebugPort2Specification.
Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _DEBUG_PORT_2_TABLE_H_
#define _DEBUG_PORT_2_TABLE_H_
#include <IndustryStandard/Acpi.h>
//
// Ensure proper structure formats
//
#pragma pack(1)
//
// Debug Device Information structure.
//
typedef struct {
UINT8 Revision;
UINT16 Length;
UINT8 NumberofGenericAddressRegisters;
UINT16 NameSpaceStringLength;
UINT16 NameSpaceStringOffset;
UINT16 OemDataLength;
UINT16 OemDataOffset;
UINT16 PortType;
UINT16 PortSubtype;
UINT8 Reserved[2];
UINT16 BaseAddressRegisterOffset;
UINT16 AddressSizeOffset;
} EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT;
#define EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION 0x00
#define EFI_ACPI_DBG2_PORT_TYPE_SERIAL 0x8000
#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_FULL_16550 0x0000
#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_16550_SUBSET_COMPATIBLE_WITH_MS_DBGP_SPEC 0x0001
#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART 0x0003
#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_SBSA_GENERIC_UART_2X 0x000d
#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_SBSA_GENERIC_UART 0x000e
#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_DCC 0x000f
#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_BCM2835_UART 0x0010
#define EFI_ACPI_DBG2_PORT_TYPE_1394 0x8001
#define EFI_ACPI_DBG2_PORT_SUBTYPE_1394_STANDARD 0x0000
#define EFI_ACPI_DBG2_PORT_TYPE_USB 0x8002
#define EFI_ACPI_DBG2_PORT_SUBTYPE_USB_XHCI 0x0000
#define EFI_ACPI_DBG2_PORT_SUBTYPE_USB_EHCI 0x0001
#define EFI_ACPI_DBG2_PORT_TYPE_NET 0x8003
//
// Debug Port 2 Table definition.
//
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
UINT32 OffsetDbgDeviceInfo;
UINT32 NumberDbgDeviceInfo;
} EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE;
#pragma pack()
//
// DBG2 Revision (defined in spec)
//
#define EFI_ACPI_DEBUG_PORT_2_TABLE_REVISION 0x00
#endif

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/** @file
ACPI debug port table definition, defined at
Microsoft DebugPortSpecification.
Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _DEBUG_PORT_TABLE_H_
#define _DEBUG_PORT_TABLE_H_
#include <IndustryStandard/Acpi.h>
//
// Ensure proper structure formats
//
#pragma pack(1)
//
// Debug Port Table definition.
//
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
UINT8 InterfaceType;
UINT8 Reserved_37[3];
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE BaseAddress;
} EFI_ACPI_DEBUG_PORT_DESCRIPTION_TABLE;
#pragma pack()
//
// DBGP Revision (defined in spec)
//
#define EFI_ACPI_DEBUG_PORT_TABLE_REVISION 0x01
//
// Interface Type
//
#define EFI_ACPI_DBGP_INTERFACE_TYPE_FULL_16550 0
#define EFI_ACPI_DBGP_INTERFACE_TYPE_16550_SUBSET_COMPATIBLE_WITH_MS_DBGP_SPEC 1
#endif

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/** @file
This file contains the DHCPv4 and DHCPv6 option definitions and other configuration.
They are used to carry additional information and parameters in DHCP messages.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _DHCP_H_
#define _DHCP_H_
///
/// Dynamic Host Configuration Protocol for IPv4 (DHCPv4)
///
/// Dhcpv4 Options, definitions from RFC 2132
///
#define DHCP4_TAG_PAD 0 /// Pad Option
#define DHCP4_TAG_EOP 255 /// End Option
#define DHCP4_TAG_NETMASK 1 /// Subnet Mask
#define DHCP4_TAG_TIME_OFFSET 2 /// Time Offset from UTC
#define DHCP4_TAG_ROUTER 3 /// Router option,
#define DHCP4_TAG_TIME_SERVER 4 /// Time Server
#define DHCP4_TAG_NAME_SERVER 5 /// Name Server
#define DHCP4_TAG_DNS_SERVER 6 /// Domain Name Server
#define DHCP4_TAG_LOG_SERVER 7 /// Log Server
#define DHCP4_TAG_COOKIE_SERVER 8 /// Cookie Server
#define DHCP4_TAG_LPR_SERVER 9 /// LPR Print Server
#define DHCP4_TAG_IMPRESS_SERVER 10 /// Impress Server
#define DHCP4_TAG_RL_SERVER 11 /// Resource Location Server
#define DHCP4_TAG_HOSTNAME 12 /// Host Name
#define DHCP4_TAG_BOOTFILE_LEN 13 /// Boot File Size
#define DHCP4_TAG_DUMP 14 /// Merit Dump File
#define DHCP4_TAG_DOMAINNAME 15 /// Domain Name
#define DHCP4_TAG_SWAP_SERVER 16 /// Swap Server
#define DHCP4_TAG_ROOTPATH 17 /// Root path
#define DHCP4_TAG_EXTEND_PATH 18 /// Extensions Path
#define DHCP4_TAG_IPFORWARD 19 /// IP Forwarding Enable/Disable
#define DHCP4_TAG_NONLOCAL_SRR 20 /// on-Local Source Routing Enable/Disable
#define DHCP4_TAG_POLICY_SRR 21 /// Policy Filter
#define DHCP4_TAG_EMTU 22 /// Maximum Datagram Reassembly Size
#define DHCP4_TAG_TTL 23 /// Default IP Time-to-live
#define DHCP4_TAG_PATHMTU_AGE 24 /// Path MTU Aging Timeout
#define DHCP4_TAG_PATHMTU_PLATEAU 25 /// Path MTU Plateau Table
#define DHCP4_TAG_IFMTU 26 /// Interface MTU
#define DHCP4_TAG_SUBNET_LOCAL 27 /// All Subnets are Local
#define DHCP4_TAG_BROADCAST 28 /// Broadcast Address
#define DHCP4_TAG_DISCOVER_MASK 29 /// Perform Mask Discovery
#define DHCP4_TAG_SUPPLY_MASK 30 /// Mask Supplier
#define DHCP4_TAG_DISCOVER_ROUTE 31 /// Perform Router Discovery
#define DHCP4_TAG_ROUTER_SOLICIT 32 /// Router Solicitation Address
#define DHCP4_TAG_STATIC_ROUTE 33 /// Static Route
#define DHCP4_TAG_TRAILER 34 /// Trailer Encapsulation
#define DHCP4_TAG_ARPAGE 35 /// ARP Cache Timeout
#define DHCP4_TAG_ETHER_ENCAP 36 /// Ethernet Encapsulation
#define DHCP4_TAG_TCP_TTL 37 /// TCP Default TTL
#define DHCP4_TAG_KEEP_INTERVAL 38 /// TCP Keepalive Interval
#define DHCP4_TAG_KEEP_GARBAGE 39 /// TCP Keepalive Garbage
#define DHCP4_TAG_NIS_DOMAIN 40 /// Network Information Service Domain
#define DHCP4_TAG_NIS_SERVER 41 /// Network Information Servers
#define DHCP4_TAG_NTP_SERVER 42 /// Network Time Protocol Servers
#define DHCP4_TAG_VENDOR 43 /// Vendor Specific Information
#define DHCP4_TAG_NBNS 44 /// NetBIOS over TCP/IP Name Server
#define DHCP4_TAG_NBDD 45 /// NetBIOS Datagram Distribution Server
#define DHCP4_TAG_NBTYPE 46 /// NetBIOS over TCP/IP Node Type
#define DHCP4_TAG_NBSCOPE 47 /// NetBIOS over TCP/IP Scope
#define DHCP4_TAG_XFONT 48 /// X Window System Font Server
#define DHCP4_TAG_XDM 49 /// X Window System Display Manager
#define DHCP4_TAG_REQUEST_IP 50 /// Requested IP Address
#define DHCP4_TAG_LEASE 51 /// IP Address Lease Time
#define DHCP4_TAG_OVERLOAD 52 /// Option Overload
#define DHCP4_TAG_MSG_TYPE 53 /// DHCP Message Type
#define DHCP4_TAG_SERVER_ID 54 /// Server Identifier
#define DHCP4_TAG_PARA_LIST 55 /// Parameter Request List
#define DHCP4_TAG_MESSAGE 56 /// Message
#define DHCP4_TAG_MAXMSG 57 /// Maximum DHCP Message Size
#define DHCP4_TAG_T1 58 /// Renewal (T1) Time Value
#define DHCP4_TAG_T2 59 /// Rebinding (T2) Time Value
#define DHCP4_TAG_VENDOR_CLASS_ID 60 /// Vendor class identifier
#define DHCP4_TAG_CLIENT_ID 61 /// Client-identifier
#define DHCP4_TAG_NISPLUS 64 /// Network Information Service+ Domain
#define DHCP4_TAG_NISPLUS_SERVER 65 /// Network Information Service+ Servers
#define DHCP4_TAG_TFTP 66 /// TFTP server name
#define DHCP4_TAG_BOOTFILE 67 /// Bootfile name
#define DHCP4_TAG_MOBILEIP 68 /// Mobile IP Home Agent
#define DHCP4_TAG_SMTP 69 /// Simple Mail Transport Protocol Server
#define DHCP4_TAG_POP3 70 /// Post Office Protocol (POP3) Server
#define DHCP4_TAG_NNTP 71 /// Network News Transport Protocol Server
#define DHCP4_TAG_WWW 72 /// Default World Wide Web (WWW) Server
#define DHCP4_TAG_FINGER 73 /// Default Finger Server
#define DHCP4_TAG_IRC 74 /// Default Internet Relay Chat (IRC) Server
#define DHCP4_TAG_STTALK 75 /// StreetTalk Server
#define DHCP4_TAG_STDA 76 /// StreetTalk Directory Assistance Server
#define DHCP4_TAG_USER_CLASS_ID 77 /// User class identifier
#define DHCP4_TAG_ARCH 93 /// Client System Architecture Type, RFC 4578
#define DHCP4_TAG_UNDI 94 /// Client Network Interface Identifier, RFC 4578
#define DHCP4_TAG_UUID 97 /// Client Machine Identifier, RFC 4578
#define DHCP4_TAG_CLASSLESS_ROUTE 121 /// Classless Route
///
/// Dynamic Host Configuration Protocol for IPv6 (DHCPv6)
///
/// Enumeration of Dhcp6 message type, refers to section-5.3 of rfc-3315.
///
typedef enum {
Dhcp6MsgSolicit = 1,
Dhcp6MsgAdvertise = 2,
Dhcp6MsgRequest = 3,
Dhcp6MsgConfirm = 4,
Dhcp6MsgRenew = 5,
Dhcp6MsgRebind = 6,
Dhcp6MsgReply = 7,
Dhcp6MsgRelease = 8,
Dhcp6MsgDecline = 9,
Dhcp6MsgReconfigure = 10,
Dhcp6MsgInfoRequest = 11
} DHCP6_MSG_TYPE;
///
/// Enumeration of option code in Dhcp6 packet, refers to section-24.3 of rfc-3315.
///
typedef enum {
Dhcp6OptClientId = 1,
Dhcp6OptServerId = 2,
Dhcp6OptIana = 3,
Dhcp6OptIata = 4,
Dhcp6OptIaAddr = 5,
Dhcp6OptRequestOption = 6,
Dhcp6OptPreference = 7,
Dhcp6OptElapsedTime = 8,
Dhcp6OptReplayMessage = 9,
Dhcp6OptAuthentication = 11,
Dhcp6OptServerUnicast = 12,
Dhcp6OptStatusCode = 13,
Dhcp6OptRapidCommit = 14,
Dhcp6OptUserClass = 15,
Dhcp6OptVendorClass = 16,
Dhcp6OptVendorInfo = 17,
Dhcp6OptInterfaceId = 18,
Dhcp6OptReconfigMessage = 19,
Dhcp6OptReconfigureAccept = 20
} DHCP6_OPT_CODE;
///
/// Enumeration of status code recorded by IANA, refers to section-24.4 of rfc-3315.
///
typedef enum {
Dhcp6StsSuccess = 0,
Dhcp6StsUnspecFail = 1,
Dhcp6StsNoAddrsAvail = 2,
Dhcp6StsNoBinding = 3,
Dhcp6StsNotOnLink = 4,
Dhcp6StsUseMulticast = 5
} DHCP6_STS_CODE;
///
/// Enumeration of Duid type recorded by IANA, refers to section-24.5 of rfc-3315.
///
typedef enum {
Dhcp6DuidTypeLlt = 1,
Dhcp6DuidTypeEn = 2,
Dhcp6DuidTypeLl = 3,
Dhcp6DuidTypeUuid = 4
} DHCP6_DUID_TYPE;
/// Transmission and Retransmission Parameters
/// This section presents a table of values used to describe the message
/// transmission behavior of clients and servers.
///
/// Transmit parameters of solicit message, refers to section-5.5 of rfc-3315.
///
#define DHCP6_SOL_MAX_DELAY 1
#define DHCP6_SOL_IRT 1
#define DHCP6_SOL_MRC 0
#define DHCP6_SOL_MRT 120
#define DHCP6_SOL_MRD 0
///
/// Transmit parameters of request message, refers to section-5.5 of rfc-3315.
///
#define DHCP6_REQ_IRT 1
#define DHCP6_REQ_MRC 10
#define DHCP6_REQ_MRT 30
#define DHCP6_REQ_MRD 0
///
/// Transmit parameters of confirm message, refers to section-5.5 of rfc-3315.
///
#define DHCP6_CNF_MAX_DELAY 1
#define DHCP6_CNF_IRT 1
#define DHCP6_CNF_MRC 0
#define DHCP6_CNF_MRT 4
#define DHCP6_CNF_MRD 10
///
/// Transmit parameters of renew message, refers to section-5.5 of rfc-3315.
///
#define DHCP6_REN_IRT 10
#define DHCP6_REN_MRC 0
#define DHCP6_REN_MRT 600
#define DHCP6_REN_MRD 0
///
/// Transmit parameters of rebind message, refers to section-5.5 of rfc-3315.
///
#define DHCP6_REB_IRT 10
#define DHCP6_REB_MRC 0
#define DHCP6_REB_MRT 600
#define DHCP6_REB_MRD 0
///
/// Transmit parameters of information request message, refers to section-5.5 of rfc-3315.
///
#define DHCP6_INF_MAX_DELAY 1
#define DHCP6_INF_IRT 1
#define DHCP6_INF_MRC 0
#define DHCP6_INF_MRT 120
#define DHCP6_INF_MRD 0
///
/// Transmit parameters of release message, refers to section-5.5 of rfc-3315.
///
#define DHCP6_REL_IRT 1
#define DHCP6_REL_MRC 5
#define DHCP6_REL_MRT 0
#define DHCP6_REL_MRD 0
///
/// Transmit parameters of decline message, refers to section-5.5 of rfc-3315.
///
#define DHCP6_DEC_IRT 1
#define DHCP6_DEC_MRC 5
#define DHCP6_DEC_MRT 0
#define DHCP6_DEC_MRD 0
////
//// DHCPv6 Options, definitions from RFC 3315,RFC 5970 and RFC 3646.
////
#define DHCP6_OPT_CLIENT_ID 1 /// Client Identifier Option
#define DHCP6_OPT_SERVER_ID 2 /// Server Identifier Option
#define DHCP6_OPT_IA_NA 3 /// The Identity Association for Non-temporary Addresses option
#define DHCP6_OPT_IA_TA 4 /// The Identity Association for the Temporary Addresses
#define DHCP6_OPT_IAADDR 5 /// IA Address option
#define DHCP6_OPT_ORO 6 /// Request option
#define DHCP6_OPT_PREFERENCE 7 /// Preference option
#define DHCP6_OPT_ELAPSED_TIME 8 /// Elapsed Time Option
#define DHCP6_OPT_REPLAY_MSG 9 /// Relay Message option
#define DHCP6_OPT_AUTH 11 /// Authentication option
#define DHCP6_OPT_UNICAST 12 /// Server Unicast Option
#define DHCP6_OPT_STATUS_CODE 13 /// Status Code Option
#define DHCP6_OPT_RAPID_COMMIT 14 /// Rapid Commit option
#define DHCP6_OPT_USER_CLASS 15 /// User Class option
#define DHCP6_OPT_VENDOR_CLASS 16 /// Vendor Class Option
#define DHCP6_OPT_VENDOR_OPTS 17 /// Vendor-specific Information Option
#define DHCP6_OPT_INTERFACE_ID 18 /// Interface-Id Option
#define DHCP6_OPT_RECONFIG_MSG 19 /// Reconfigure Message Option
#define DHCP6_OPT_RECONFIG_ACCEPT 20 /// Reconfigure Accept Option
#define DHCP6_OPT_DNS_SERVERS 23 /// DNS Configuration options, RFC 3646
#define DHCP6_OPT_BOOT_FILE_URL 59 /// Assigned by IANA, RFC 5970
#define DHCP6_OPT_BOOT_FILE_PARAM 60 /// Assigned by IANA, RFC 5970
#define DHCP6_OPT_ARCH 61 /// Assigned by IANA, RFC 5970
#define DHCP6_OPT_UNDI 62 /// Assigned by IANA, RFC 5970
///
/// Processor Architecture Types
/// These identifiers are defined by IETF:
/// http://www.ietf.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xml
///
#define PXE_CLIENT_ARCH_X86_BIOS 0x0000 /// x86 BIOS for PXE
#define PXE_CLIENT_ARCH_IPF 0x0002 /// Itanium for PXE
#define PXE_CLIENT_ARCH_IA32 0x0006 /// x86 uefi for PXE
#define PXE_CLIENT_ARCH_X64 0x0007 /// x64 uefi for PXE
#define PXE_CLIENT_ARCH_EBC 0x0009 /// EBC for PXE
#define PXE_CLIENT_ARCH_ARM 0x000A /// Arm uefi 32 for PXE
#define PXE_CLIENT_ARCH_AARCH64 0x000B /// Arm uefi 64 for PXE
#define HTTP_CLIENT_ARCH_IA32 0x000F /// x86 uefi boot from http
#define HTTP_CLIENT_ARCH_X64 0x0010 /// x64 uefi boot from http
#define HTTP_CLIENT_ARCH_EBC 0x0011 /// EBC boot from http
#define HTTP_CLIENT_ARCH_ARM 0x0012 /// Arm uefi 32 boot from http
#define HTTP_CLIENT_ARCH_AARCH64 0x0013 /// Arm uefi 64 boot from http
#endif

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/** @file
DMA Remapping Reporting (DMAR) ACPI table definition from Intel(R)
Virtualization Technology for Directed I/O (VT-D) Architecture Specification.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
- Intel(R) Virtualization Technology for Directed I/O (VT-D) Architecture
Specification v2.4, Dated June 2016.
http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-directed-io-spec.pdf
@par Glossary:
- HPET - High Precision Event Timer
- NUMA - Non-uniform Memory Access
**/
#ifndef _DMA_REMAPPING_REPORTING_TABLE_H_
#define _DMA_REMAPPING_REPORTING_TABLE_H_
#pragma pack(1)
///
/// DMA-Remapping Reporting Structure definitions from section 8.1
///@{
#define EFI_ACPI_DMAR_REVISION 0x01
#define EFI_ACPI_DMAR_FLAGS_INTR_REMAP BIT0
#define EFI_ACPI_DMAR_FLAGS_X2APIC_OPT_OUT BIT1
///@}
///
/// Remapping Structure Types definitions from section 8.2
///@{
#define EFI_ACPI_DMAR_TYPE_DRHD 0x00
#define EFI_ACPI_DMAR_TYPE_RMRR 0x01
#define EFI_ACPI_DMAR_TYPE_ATSR 0x02
#define EFI_ACPI_DMAR_TYPE_RHSA 0x03
#define EFI_ACPI_DMAR_TYPE_ANDD 0x04
///@}
///
/// DMA-Remapping Hardware Unit definitions from section 8.3
///
#define EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL BIT0
///
/// DMA-Remapping Device Scope Entry Structure definitions from section 8.3.1
///@{
#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT 0x01
#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_BRIDGE 0x02
#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_IOAPIC 0x03
#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_MSI_CAPABLE_HPET 0x04
#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_ACPI_NAMESPACE_DEVICE 0x05
///@}
///
/// Root Port ATS Capability Reporting Structure definitions from section 8.5
///
#define EFI_ACPI_DMAR_ATSR_FLAGS_ALL_PORTS BIT0
///
/// Definition for DMA Remapping Structure Header
///
typedef struct {
UINT16 Type;
UINT16 Length;
} EFI_ACPI_DMAR_STRUCTURE_HEADER;
///
/// Definition for DMA-Remapping PCI Path
///
typedef struct {
UINT8 Device;
UINT8 Function;
} EFI_ACPI_DMAR_PCI_PATH;
///
/// Device Scope Structure is defined in section 8.3.1
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT16 Reserved2;
UINT8 EnumerationId;
UINT8 StartBusNumber;
} EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER;
/**
DMA-remapping hardware unit definition (DRHD) structure is defined in
section 8.3. This uniquely represents a remapping hardware unit present
in the platform. There must be at least one instance of this structure
for each PCI segment in the platform.
**/
typedef struct {
EFI_ACPI_DMAR_STRUCTURE_HEADER Header;
/**
- Bit[0]: INCLUDE_PCI_ALL
- If Set, this remapping hardware unit has under its scope all
PCI compatible devices in the specified Segment, except devices
reported under the scope of other remapping hardware units for
the same Segment.
- If Clear, this remapping hardware unit has under its scope only
devices in the specified Segment that are explicitly identified
through the DeviceScope field.
- Bits[7:1] Reserved.
**/
UINT8 Flags;
UINT8 Reserved;
///
/// The PCI Segment associated with this unit.
///
UINT16 SegmentNumber;
///
/// Base address of remapping hardware register-set for this unit.
///
UINT64 RegisterBaseAddress;
} EFI_ACPI_DMAR_DRHD_HEADER;
/**
Reserved Memory Region Reporting Structure (RMRR) is described in section 8.4
Reserved memory ranges that may be DMA targets may be reported through the
RMRR structures, along with the devices that requires access to the specified
reserved memory region.
**/
typedef struct {
EFI_ACPI_DMAR_STRUCTURE_HEADER Header;
UINT8 Reserved[2];
///
/// PCI Segment Number associated with devices identified through
/// the Device Scope field.
///
UINT16 SegmentNumber;
///
/// Base address of 4KB-aligned reserved memory region
///
UINT64 ReservedMemoryRegionBaseAddress;
/**
Last address of the reserved memory region. Value in this field must be
greater than the value in Reserved Memory Region Base Address field.
The reserved memory region size (Limit - Base + 1) must be an integer
multiple of 4KB.
**/
UINT64 ReservedMemoryRegionLimitAddress;
} EFI_ACPI_DMAR_RMRR_HEADER;
/**
Root Port ATS Capability Reporting (ATSR) structure is defined in section 8.5.
This structure is applicable only for platforms supporting Device-TLBs as
reported through the Extended Capability Register. For each PCI Segment in
the platform that supports Device-TLBs, BIOS provides an ATSR structure. The
ATSR structures identifies PCI-Express Root-Ports supporting Address
Translation Services (ATS) transactions. Software must enable ATS on endpoint
devices behind a Root Port only if the Root Port is reported as supporting
ATS transactions.
**/
typedef struct {
EFI_ACPI_DMAR_STRUCTURE_HEADER Header;
/**
- Bit[0]: ALL_PORTS:
- If Set, indicates all PCI Express Root Ports in the specified
PCI Segment supports ATS transactions.
- If Clear, indicates ATS transactions are supported only on
Root Ports identified through the Device Scope field.
- Bits[7:1] Reserved.
**/
UINT8 Flags;
UINT8 Reserved;
///
/// The PCI Segment associated with this ATSR structure
///
UINT16 SegmentNumber;
} EFI_ACPI_DMAR_ATSR_HEADER;
/**
Remapping Hardware Static Affinity (RHSA) is an optional structure defined
in section 8.6. This is intended to be used only on NUMA platforms with
Remapping hardware units and memory spanned across multiple nodes.
When used, there must be a RHSA structure for each Remapping hardware unit
reported through DRHD structure.
**/
typedef struct {
EFI_ACPI_DMAR_STRUCTURE_HEADER Header;
UINT8 Reserved[4];
///
/// Register Base Address of this Remap hardware unit reported in the
/// corresponding DRHD structure.
///
UINT64 RegisterBaseAddress;
///
/// Proximity Domain to which the Remap hardware unit identified by the
/// Register Base Address field belongs.
///
UINT32 ProximityDomain;
} EFI_ACPI_DMAR_RHSA_HEADER;
/**
An ACPI Name-space Device Declaration (ANDD) structure is defined in section
8.7 and uniquely represents an ACPI name-space enumerated device capable of
issuing DMA requests in the platform. ANDD structures are used in conjunction
with Device-Scope entries of type ACPI_NAMESPACE_DEVICE.
**/
typedef struct {
EFI_ACPI_DMAR_STRUCTURE_HEADER Header;
UINT8 Reserved[3];
/**
Each ACPI device enumerated through an ANDD structure must have a unique
value for this field. To report an ACPI device with ACPI Device Number
value of X, under the scope of a DRHD unit, a Device-Scope entry of type
ACPI_NAMESPACE_DEVICE is used with value of X in the Enumeration ID field.
The Start Bus Number and Path fields in the Device-Scope together
provides the 16-bit source-id allocated by platform for the ACPI device.
**/
UINT8 AcpiDeviceNumber;
} EFI_ACPI_DMAR_ANDD_HEADER;
/**
DMA Remapping Reporting Structure Header as defined in section 8.1
This header will be followed by list of Remapping Structures listed below
- DMA Remapping Hardware Unit Definition (DRHD)
- Reserved Memory Region Reporting (RMRR)
- Root Port ATS Capability Reporting (ATSR)
- Remapping Hardware Static Affinity (RHSA)
- ACPI Name-space Device Declaration (ANDD)
These structure types must by reported in numerical order.
i.e., All remapping structures of type 0 (DRHD) enumerated before remapping
structures of type 1 (RMRR), and so forth.
**/
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
/**
This field indicates the maximum DMA physical addressability supported by
this platform. The system address map reported by the BIOS indicates what
portions of this addresses are populated. The Host Address Width (HAW) of
the platform is computed as (N+1), where N is the value reported in this
field.
For example, for a platform supporting 40 bits of physical addressability,
the value of 100111b is reported in this field.
**/
UINT8 HostAddressWidth;
/**
- Bit[0]: INTR_REMAP - If Clear, the platform does not support interrupt
remapping. If Set, the platform supports interrupt remapping.
- Bit[1]: X2APIC_OPT_OUT - For firmware compatibility reasons, platform
firmware may Set this field to request system software to opt
out of enabling Extended xAPIC (X2APIC) mode. This field is
valid only when the INTR_REMAP field (bit 0) is Set.
- Bits[7:2] Reserved.
**/
UINT8 Flags;
UINT8 Reserved[10];
} EFI_ACPI_DMAR_HEADER;
#pragma pack()
#endif

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/** @file
ElTorito Partitions Format Definition.
This file includes some defintions from
1. "El Torito" Bootable CD-ROM Format Specification, Version 1.0.
2. Volume and File Structure of CDROM for Information Interchange,
Standard ECMA-119. (IS0 9660)
Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _ELTORITO_H_
#define _ELTORITO_H_
//
// CDROM_VOLUME_DESCRIPTOR.Types, defined in ISO 9660
//
#define CDVOL_TYPE_STANDARD 0x0
#define CDVOL_TYPE_CODED 0x1
#define CDVOL_TYPE_END 0xFF
///
/// CDROM_VOLUME_DESCRIPTOR.Id
///
#define CDVOL_ID "CD001"
///
/// CDROM_VOLUME_DESCRIPTOR.SystemId
///
#define CDVOL_ELTORITO_ID "EL TORITO SPECIFICATION"
//
// Indicator types
//
#define ELTORITO_ID_CATALOG 0x01
#define ELTORITO_ID_SECTION_BOOTABLE 0x88
#define ELTORITO_ID_SECTION_NOT_BOOTABLE 0x00
#define ELTORITO_ID_SECTION_HEADER 0x90
#define ELTORITO_ID_SECTION_HEADER_FINAL 0x91
//
// ELTORITO_CATALOG.Boot.MediaTypes
//
#define ELTORITO_NO_EMULATION 0x00
#define ELTORITO_12_DISKETTE 0x01
#define ELTORITO_14_DISKETTE 0x02
#define ELTORITO_28_DISKETTE 0x03
#define ELTORITO_HARD_DISK 0x04
#pragma pack(1)
///
/// CD-ROM Volume Descriptor
///
typedef union {
struct {
UINT8 Type;
CHAR8 Id[5]; ///< "CD001"
CHAR8 Reserved[82];
} Unknown;
///
/// Boot Record Volume Descriptor, defined in "El Torito" Specification.
///
struct {
UINT8 Type; ///< Must be 0
CHAR8 Id[5]; ///< "CD001"
UINT8 Version; ///< Must be 1
CHAR8 SystemId[32]; ///< "EL TORITO SPECIFICATION"
CHAR8 Unused[32]; ///< Must be 0
UINT8 EltCatalog[4]; ///< Absolute pointer to first sector of Boot Catalog
CHAR8 Unused2[13]; ///< Must be 0
} BootRecordVolume;
///
/// Primary Volumn Descriptor, defined in ISO 9660.
///
struct {
UINT8 Type;
CHAR8 Id[5]; ///< "CD001"
UINT8 Version;
UINT8 Unused; ///< Must be 0
CHAR8 SystemId[32];
CHAR8 VolumeId[32];
UINT8 Unused2[8]; ///< Must be 0
UINT32 VolSpaceSize[2]; ///< the number of Logical Blocks
} PrimaryVolume;
} CDROM_VOLUME_DESCRIPTOR;
///
/// Catalog Entry
///
typedef union {
struct {
CHAR8 Reserved[0x20];
} Unknown;
///
/// Catalog validation entry (Catalog header)
///
struct {
UINT8 Indicator; ///< Must be 01
UINT8 PlatformId;
UINT16 Reserved;
CHAR8 ManufacId[24];
UINT16 Checksum;
UINT16 Id55AA;
} Catalog;
///
/// Initial/Default Entry or Section Entry
///
struct {
UINT8 Indicator; ///< 88 = Bootable, 00 = Not Bootable
UINT8 MediaType : 4;
UINT8 Reserved1 : 4; ///< Must be 0
UINT16 LoadSegment;
UINT8 SystemType;
UINT8 Reserved2; ///< Must be 0
UINT16 SectorCount;
UINT32 Lba;
} Boot;
///
/// Section Header Entry
///
struct {
UINT8 Indicator; ///< 90 - Header, more header follw, 91 - Final Header
UINT8 PlatformId;
UINT16 SectionEntries; ///< Number of section entries following this header
CHAR8 Id[28];
} Section;
} ELTORITO_CATALOG;
#pragma pack()
#endif

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MdePkg/Include/IndustryStandard/Emmc.h Normal file
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/** @file
Header file for eMMC support.
This header file contains some definitions defined in EMMC4.5/EMMC5.0 spec.
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __EMMC_H__
#define __EMMC_H__
//
// EMMC command index
//
#define EMMC_GO_IDLE_STATE 0
#define EMMC_SEND_OP_COND 1
#define EMMC_ALL_SEND_CID 2
#define EMMC_SET_RELATIVE_ADDR 3
#define EMMC_SET_DSR 4
#define EMMC_SLEEP_AWAKE 5
#define EMMC_SWITCH 6
#define EMMC_SELECT_DESELECT_CARD 7
#define EMMC_SEND_EXT_CSD 8
#define EMMC_SEND_CSD 9
#define EMMC_SEND_CID 10
#define EMMC_STOP_TRANSMISSION 12
#define EMMC_SEND_STATUS 13
#define EMMC_BUSTEST_R 14
#define EMMC_GO_INACTIVE_STATE 15
#define EMMC_SET_BLOCKLEN 16
#define EMMC_READ_SINGLE_BLOCK 17
#define EMMC_READ_MULTIPLE_BLOCK 18
#define EMMC_BUSTEST_W 19
#define EMMC_SEND_TUNING_BLOCK 21
#define EMMC_SET_BLOCK_COUNT 23
#define EMMC_WRITE_BLOCK 24
#define EMMC_WRITE_MULTIPLE_BLOCK 25
#define EMMC_PROGRAM_CID 26
#define EMMC_PROGRAM_CSD 27
#define EMMC_SET_WRITE_PROT 28
#define EMMC_CLR_WRITE_PROT 29
#define EMMC_SEND_WRITE_PROT 30
#define EMMC_SEND_WRITE_PROT_TYPE 31
#define EMMC_ERASE_GROUP_START 35
#define EMMC_ERASE_GROUP_END 36
#define EMMC_ERASE 38
#define EMMC_FAST_IO 39
#define EMMC_GO_IRQ_STATE 40
#define EMMC_LOCK_UNLOCK 42
#define EMMC_SET_TIME 49
#define EMMC_PROTOCOL_RD 53
#define EMMC_PROTOCOL_WR 54
#define EMMC_APP_CMD 55
#define EMMC_GEN_CMD 56
typedef enum {
EmmcPartitionUserData = 0,
EmmcPartitionBoot1 = 1,
EmmcPartitionBoot2 = 2,
EmmcPartitionRPMB = 3,
EmmcPartitionGP1 = 4,
EmmcPartitionGP2 = 5,
EmmcPartitionGP3 = 6,
EmmcPartitionGP4 = 7,
EmmcPartitionUnknown
} EMMC_PARTITION_TYPE;
#pragma pack(1)
typedef struct {
UINT8 NotUsed:1; // Not used [0:0]
UINT8 Crc:7; // CRC [7:1]
UINT8 ManufacturingDate; // Manufacturing date [15:8]
UINT8 ProductSerialNumber[4]; // Product serial number [47:16]
UINT8 ProductRevision; // Product revision [55:48]
UINT8 ProductName[6]; // Product name [103:56]
UINT8 OemId; // OEM/Application ID [111:104]
UINT8 DeviceType:2; // Device/BGA [113:112]
UINT8 Reserved:6; // Reserved [119:114]
UINT8 ManufacturerId; // Manufacturer ID [127:120]
} EMMC_CID;
typedef struct {
UINT32 NotUsed:1; // Not used [0:0]
UINT32 Crc:7; // CRC [7:1]
UINT32 Ecc:2; // ECC code [9:8]
UINT32 FileFormat:2; // File format [11:10]
UINT32 TmpWriteProtect:1; // Temporary write protection [12:12]
UINT32 PermWriteProtect:1; // Permanent write protection [13:13]
UINT32 Copy:1; // Copy flag (OTP) [14:14]
UINT32 FileFormatGrp:1; // File format group [15:15]
UINT32 ContentProtApp:1; // Content protection application [16:16]
UINT32 Reserved:4; // Reserved [20:17]
UINT32 WriteBlPartial:1; // Partial blocks for write allowed [21:21]
UINT32 WriteBlLen:4; // Max. write data block length [25:22]
UINT32 R2WFactor:3; // Write speed factor [28:26]
UINT32 DefaultEcc:2; // Manufacturer default ECC [30:29]
UINT32 WpGrpEnable:1; // Write protect group enable [31:31]
UINT32 WpGrpSize:5; // Write protect group size [36:32]
UINT32 EraseGrpMult:5; // Erase group size multiplier [41:37]
UINT32 EraseGrpSize:5; // Erase group size [46:42]
UINT32 CSizeMult:3; // Device size multiplier [49:47]
UINT32 VddWCurrMax:3; // Max. write current @ VDD max [52:50]
UINT32 VddWCurrMin:3; // Max. write current @ VDD min [55:53]
UINT32 VddRCurrMax:3; // Max. read current @ VDD max [58:56]
UINT32 VddRCurrMin:3; // Max. read current @ VDD min [61:59]
UINT32 CSizeLow:2; // Device size low two bits [63:62]
UINT32 CSizeHigh:10; // Device size high eight bits [73:64]
UINT32 Reserved1:2; // Reserved [75:74]
UINT32 DsrImp:1; // DSR implemented [76:76]
UINT32 ReadBlkMisalign:1; // Read block misalignment [77:77]
UINT32 WriteBlkMisalign:1; // Write block misalignment [78:78]
UINT32 ReadBlPartial:1; // Partial blocks for read allowed [79:79]
UINT32 ReadBlLen:4; // Max. read data block length [83:80]
UINT32 Ccc:12; // Device command classes [95:84]
UINT32 TranSpeed:8; // Max. bus clock frequency [103:96]
UINT32 Nsac:8; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
UINT32 Taac:8; // Data read access-time 1 [119:112]
UINT32 Reserved2:2; // Reserved [121:120]
UINT32 SpecVers:4; // System specification version [125:122]
UINT32 CsdStructure:2; // CSD structure [127:126]
} EMMC_CSD;
typedef struct {
//
// Modes Segment
//
UINT8 Reserved[16]; // Reserved [15:0]
UINT8 SecureRemovalType; // Secure Removal Type R/W & R [16]
UINT8 ProductStateAwarenessEnablement; // Product state awareness enablement R/W/E & R [17]
UINT8 MaxPreLoadingDataSize[4]; // Max pre loading data size R [21:18]
UINT8 PreLoadingDataSize[4]; // Pre loading data size R/W/EP [25:22]
UINT8 FfuStatus; // FFU status R [26]
UINT8 Reserved1[2]; // Reserved [28:27]
UINT8 ModeOperationCodes; // Mode operation codes W/EP [29]
UINT8 ModeConfig; // Mode config R/W/EP [30]
UINT8 Reserved2; // Reserved [31]
UINT8 FlushCache; // Flushing of the cache W/EP [32]
UINT8 CacheCtrl; // Control to turn the Cache ON/OFF R/W/EP [33]
UINT8 PowerOffNotification; // Power Off Notification R/W/EP [34]
UINT8 PackedFailureIndex; // Packed command failure index R [35]
UINT8 PackedCommandStatus; // Packed command status R [36]
UINT8 ContextConf[15]; // Context configuration R/W/EP [51:37]
UINT8 ExtPartitionsAttribute[2]; // Extended Partitions Attribute R/W [53:52]
UINT8 ExceptionEventsStatus[2]; // Exception events status R [55:54]
UINT8 ExceptionEventsCtrl[2]; // Exception events control R/W/EP [57:56]
UINT8 DyncapNeeded; // Number of addressed group to be Released R [58]
UINT8 Class6Ctrl; // Class 6 commands control R/W/EP [59]
UINT8 IniTimeoutEmu; // 1st initialization after disabling sector size emulation R [60]
UINT8 DataSectorSize; // Sector size R [61]
UINT8 UseNativeSector; // Sector size emulation R/W [62]
UINT8 NativeSectorSize; // Native sector size R [63]
UINT8 VendorSpecificField[64]; // Vendor Specific Fields <vendor specific> [127:64]
UINT8 Reserved3[2]; // Reserved [129:128]
UINT8 ProgramCidCsdDdrSupport; // Program CID/CSD in DDR mode support R [130]
UINT8 PeriodicWakeup; // Periodic Wake-up R/W/E [131]
UINT8 TcaseSupport; // Package Case Temperature is controlled W/EP [132]
UINT8 ProductionStateAwareness; // Production state awareness R/W/E [133]
UINT8 SecBadBlkMgmnt; // Bad Block Management mode R/W [134]
UINT8 Reserved4; // Reserved [135]
UINT8 EnhStartAddr[4]; // Enhanced User Data Start Address R/W [139:136]
UINT8 EnhSizeMult[3]; // Enhanced User Data Area Size R/W [142:140]
UINT8 GpSizeMult[12]; // General Purpose Partition Size R/W [154:143]
UINT8 PartitionSettingCompleted; // Partitioning Setting R/W [155]
UINT8 PartitionsAttribute; // Partitions attribute R/W [156]
UINT8 MaxEnhSizeMult[3]; // Max Enhanced Area Size R [159:157]
UINT8 PartitioningSupport; // Partitioning Support R [160]
UINT8 HpiMgmt; // HPI management R/W/EP [161]
UINT8 RstFunction; // H/W reset function R/W [162]
UINT8 BkopsEn; // Enable background operations handshake R/W [163]
UINT8 BkopsStart; // Manually start background operations W/EP [164]
UINT8 SanitizeStart; // Start Sanitize operation W/EP [165]
UINT8 WrRelParam; // Write reliability parameter register R [166]
UINT8 WrRelSet; // Write reliability setting register R/W [167]
UINT8 RpmbSizeMult; // RPMB Size R [168]
UINT8 FwConfig; // FW configuration R/W [169]
UINT8 Reserved5; // Reserved [170]
UINT8 UserWp; // User area write protection register R/W,R/W/CP&R/W/EP [171]
UINT8 Reserved6; // Reserved [172]
UINT8 BootWp; // Boot area write protection register R/W&R/W/CP[173]
UINT8 BootWpStatus; // Boot write protection status registers R [174]
UINT8 EraseGroupDef; // High-density erase group definition R/W/EP [175]
UINT8 Reserved7; // Reserved [176]
UINT8 BootBusConditions; // Boot bus Conditions R/W/E [177]
UINT8 BootConfigProt; // Boot config protection R/W&R/W/CP[178]
UINT8 PartitionConfig; // Partition configuration R/W/E&R/W/EP[179]
UINT8 Reserved8; // Reserved [180]
UINT8 ErasedMemCont; // Erased memory content R [181]
UINT8 Reserved9; // Reserved [182]
UINT8 BusWidth; // Bus width mode W/EP [183]
UINT8 Reserved10; // Reserved [184]
UINT8 HsTiming; // High-speed interface timing R/W/EP [185]
UINT8 Reserved11; // Reserved [186]
UINT8 PowerClass; // Power class R/W/EP [187]
UINT8 Reserved12; // Reserved [188]
UINT8 CmdSetRev; // Command set revision R [189]
UINT8 Reserved13; // Reserved [190]
UINT8 CmdSet; // Command set R/W/EP [191]
//
// Properties Segment
//
UINT8 ExtCsdRev; // Extended CSD revision [192]
UINT8 Reserved14; // Reserved [193]
UINT8 CsdStructure; // CSD STRUCTURE [194]
UINT8 Reserved15; // Reserved [195]
UINT8 DeviceType; // Device type [196]
UINT8 DriverStrength; // I/O Driver Strength [197]
UINT8 OutOfInterruptTime; // Out-of-interrupt busy timing[198]
UINT8 PartitionSwitchTime; // Partition switching timing [199]
UINT8 PwrCl52M195V; // Power class for 52MHz at 1.95V [200]
UINT8 PwrCl26M195V; // Power class for 26MHz at 1.95V [201]
UINT8 PwrCl52M360V; // Power class for 52MHz at 3.6V [202]
UINT8 PwrCl26M360V; // Power class for 26MHz at 3.6V [203]
UINT8 Reserved16; // Reserved [204]
UINT8 MinPerfR4B26M; // Minimum Read Performance for 4bit at 26MHz [205]
UINT8 MinPerfW4B26M; // Minimum Write Performance for 4bit at 26MHz [206]
UINT8 MinPerfR8B26M4B52M; // Minimum Read Performance for 8bit at 26MHz, for 4bit at 52MHz [207]
UINT8 MinPerfW8B26M4B52M; // Minimum Write Performance for 8bit at 26MHz, for 4bit at 52MHz [208]
UINT8 MinPerfR8B52M; // Minimum Read Performance for 8bit at 52MHz [209]
UINT8 MinPerfW8B52M; // Minimum Write Performance for 8bit at 52MHz [210]
UINT8 Reserved17; // Reserved [211]
UINT8 SecCount[4]; // Sector Count [215:212]
UINT8 SleepNotificationTime; // Sleep Notification Timout [216]
UINT8 SATimeout; // Sleep/awake timeout [217]
UINT8 ProductionStateAwarenessTimeout; // Production state awareness timeout [218]
UINT8 SCVccq; // Sleep current (VCCQ) [219]
UINT8 SCVcc; // Sleep current (VCC) [220]
UINT8 HcWpGrpSize; // High-capacity write protect group size [221]
UINT8 RelWrSecC; // Reliable write sector count [222]
UINT8 EraseTimeoutMult; // High-capacity erase timeout [223]
UINT8 HcEraseGrpSize; // High-capacity erase unit size [224]
UINT8 AccSize; // Access size [225]
UINT8 BootSizeMult; // Boot partition size [226]
UINT8 Reserved18; // Reserved [227]
UINT8 BootInfo; // Boot information [228]
UINT8 SecTrimMult; // Secure TRIM Multiplier [229]
UINT8 SecEraseMult; // Secure Erase Multiplier [230]
UINT8 SecFeatureSupport; // Secure Feature support [231]
UINT8 TrimMult; // TRIM Multiplier [232]
UINT8 Reserved19; // Reserved [233]
UINT8 MinPerfDdrR8b52M; // Minimum Read Performance for 8bit at 52MHz in DDR mode [234]
UINT8 MinPerfDdrW8b52M; // Minimum Write Performance for 8bit at 52MHz in DDR mode [235]
UINT8 PwrCl200M130V; // Power class for 200MHz, at VCCQ=1.3V, VCC = 3.6V [236]
UINT8 PwrCl200M195V; // Power class for 200MHz at VCCQ=1.95V, VCC = 3.6V [237]
UINT8 PwrClDdr52M195V; // Power class for 52MHz, DDR at VCC= 1.95V [238]
UINT8 PwrClDdr52M360V; // Power class for 52MHz, DDR at VCC= 3.6V [239]
UINT8 Reserved20; // Reserved [240]
UINT8 IniTimeoutAp; // 1st initialization time after partitioning [241]
UINT8 CorrectlyPrgSectorsNum[4]; // Number of correctly programmed sectors [245:242]
UINT8 BkopsStatus; // Background operations status [246]
UINT8 PowerOffLongTime; // Power off notification(long) timeout [247]
UINT8 GenericCmd6Time; // Generic CMD6 timeout [248]
UINT8 CacheSize[4]; // Cache size [252:249]
UINT8 PwrClDdr200M360V; // Power class for 200MHz, DDR at VCC= 3.6V [253]
UINT8 FirmwareVersion[8]; // Firmware version [261:254]
UINT8 DeviceVersion[2]; // Device version [263:262]
UINT8 OptimalTrimUnitSize; // Optimal trim unit size[264]
UINT8 OptimalWriteSize; // Optimal write size [265]
UINT8 OptimalReadSize; // Optimal read size [266]
UINT8 PreEolInfo; // Pre EOL information [267]
UINT8 DeviceLifeTimeEstTypA; // Device life time estimation type A [268]
UINT8 DeviceLifeTimeEstTypB; // Device life time estimation type B [269]
UINT8 VendorProprietaryHealthReport[32]; // Vendor proprietary health report [301:270]
UINT8 NumOfFwSectorsProgrammed[4]; // Number of FW sectors correctly programmed [305:302]
UINT8 Reserved21[181]; // Reserved [486:306]
UINT8 FfuArg[4]; // FFU Argument [490:487]
UINT8 OperationCodeTimeout; // Operation codes timeout [491]
UINT8 FfuFeatures; // FFU features [492]
UINT8 SupportedModes; // Supported modes [493]
UINT8 ExtSupport; // Extended partitions attribute support [494]
UINT8 LargeUnitSizeM1; // Large Unit size [495]
UINT8 ContextCapabilities; // Context management capabilities [496]
UINT8 TagResSize; // Tag Resources Size [497]
UINT8 TagUnitSize; // Tag Unit Size [498]
UINT8 DataTagSupport; // Data Tag Support [499]
UINT8 MaxPackedWrites; // Max packed write commands [500]
UINT8 MaxPackedReads; // Max packed read commands[501]
UINT8 BkOpsSupport; // Background operations support [502]
UINT8 HpiFeatures; // HPI features [503]
UINT8 SupportedCmdSet; // Supported Command Sets [504]
UINT8 ExtSecurityErr; // Extended Security Commands Error [505]
UINT8 Reserved22[6]; // Reserved [511:506]
} EMMC_EXT_CSD;
#pragma pack()
#endif

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/** @file
ACPI high precision event timer table definition, at www.intel.com
Specification name is IA-PC HPET (High Precision Event Timers) Specification.
Copyright (c) 2007 - 2008, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _HIGH_PRECISION_EVENT_TIMER_TABLE_H_
#define _HIGH_PRECISION_EVENT_TIMER_TABLE_H_
#include <IndustryStandard/Acpi.h>
//
// Ensure proper structure formats
//
#pragma pack(1)
///
/// High Precision Event Timer Table header definition.
///
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
UINT32 EventTimerBlockId;
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE BaseAddressLower32Bit;
UINT8 HpetNumber;
UINT16 MainCounterMinimumClockTickInPeriodicMode;
UINT8 PageProtectionAndOemAttribute;
} EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER;
///
/// HPET Revision (defined in spec)
///
#define EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_REVISION 0x01
//
// Page protection setting
// Values 3 through 15 are reserved for use by the specification
//
#define EFI_ACPI_NO_PAGE_PROTECTION 0
#define EFI_ACPI_4KB_PAGE_PROTECTION 1
#define EFI_ACPI_64KB_PAGE_PROTECTION 2
#pragma pack()
#endif

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/** @file
Support for HSTI 1.0 specification, defined at
Microsoft Hardware Security Testability Specification.
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __HSTI_H__
#define __HSTI_H__
#pragma pack(1)
#define ADAPTER_INFO_PLATFORM_SECURITY_GUID \
{0x6be272c7, 0x1320, 0x4ccd, { 0x90, 0x17, 0xd4, 0x61, 0x2c, 0x01, 0x2b, 0x25 }}
#define PLATFORM_SECURITY_VERSION_VNEXTCS 0x00000003
#define PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE 0x00000001 // IHV
#define PLATFORM_SECURITY_ROLE_PLATFORM_IBV 0x00000002
#define PLATFORM_SECURITY_ROLE_IMPLEMENTOR_OEM 0x00000003
#define PLATFORM_SECURITY_ROLE_IMPLEMENTOR_ODM 0x00000004
typedef struct {
//
// Return PLATFORM_SECURITY_VERSION_VNEXTCS
//
UINT32 Version;
//
// The role of the publisher of this interface. Reference platform designers
// such as IHVs and IBVs are expected to return PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE
// and PLATFORM_SECURITY_ROLE_PLATFORM_IBV respectively.
// If the test modules from the designers are unable to fully verify all
// security features, then the platform implementers, OEMs and ODMs, will
// need to publish this interface with a role of Implementer.
//
UINT32 Role;
//
// Human readable vendor, model, & version of this implementation.
//
CHAR16 ImplementationID[256];
//
// The size in bytes of the SecurityFeaturesRequired and SecurityFeaturesEnabled arrays.
// The arrays must be the same size.
//
UINT32 SecurityFeaturesSize;
//
// IHV-defined bitfield corresponding to all security features which must be
// implemented to meet the security requirements defined by PLATFORM_SECURITY_VERSION Version.
//
//UINT8 SecurityFeaturesRequired[]; //Ignored for non-IHV
//
// Publisher-defined bitfield corresponding to all security features which
// have implemented programmatic tests in this module.
//
//UINT8 SecurityFeaturesImplemented[];
//
// Publisher-defined bitfield corresponding to all security features which
// have been verified implemented by this implementation.
//
//UINT8 SecurityFeaturesVerified[];
//
// A Null-terminated string, one failure per line (CR/LF terminated), with a
// unique identifier that the OEM/ODM can use to locate the documentation
// which will describe the steps to remediate the failure - a URL to the
// documentation is recommended.
//
//CHAR16 ErrorString[];
} ADAPTER_INFO_PLATFORM_SECURITY;
#pragma pack()
extern EFI_GUID gAdapterInfoPlatformSecurityGuid;
#endif

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/** @file
Hypertext Transfer Protocol -- HTTP/1.1 Standard definitions, from RFC 2616
This file contains common HTTP 1.1 definitions from RFC 2616
(C) Copyright 2015-2016 Hewlett Packard Enterprise Development LP<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __HTTP_11_H__
#define __HTTP_11_H__
#pragma pack(1)
///
/// HTTP Version (currently HTTP 1.1)
///
/// The version of an HTTP message is indicated by an HTTP-Version field
/// in the first line of the message.
///
#define HTTP_VERSION "HTTP/1.1"
///
/// HTTP Request Method definitions
///
/// The Method token indicates the method to be performed on the
/// resource identified by the Request-URI. The method is case-sensitive.
///
#define HTTP_METHOD_OPTIONS "OPTIONS"
#define HTTP_METHOD_GET "GET"
#define HTTP_METHOD_HEAD "HEAD"
#define HTTP_METHOD_POST "POST"
#define HTTP_METHOD_PUT "PUT"
#define HTTP_METHOD_DELETE "DELETE"
#define HTTP_METHOD_TRACE "TRACE"
#define HTTP_METHOD_CONNECT "CONNECT"
#define HTTP_METHOD_PATCH "PATCH"
///
/// Connect method has maximum length according to EFI_HTTP_METHOD defined in
/// UEFI2.5 spec so use this.
///
#define HTTP_METHOD_MAXIMUM_LEN sizeof (HTTP_METHOD_CONNECT)
///
/// Accept Request Header
/// The Accept request-header field can be used to specify certain media types which are
/// acceptable for the response. Accept headers can be used to indicate that the request
/// is specifically limited to a small set of desired types, as in the case of a request
/// for an in-line image.
///
#define HTTP_HEADER_ACCEPT "Accept"
///
/// Accept-Charset Request Header
/// The Accept-Charset request-header field can be used to indicate what character sets
/// are acceptable for the response. This field allows clients capable of understanding
/// more comprehensive or special-purpose character sets to signal that capability to a
/// server which is capable of representing documents in those character sets.
///
#define HTTP_HEADER_ACCEPT_CHARSET "Accept-Charset"
///
/// Accept-Language Request Header
/// The Accept-Language request-header field is similar to Accept,
/// but restricts the set of natural languages that are preferred
/// as a response to the request.
///
#define HTTP_HEADER_ACCEPT_LANGUAGE "Accept-Language"
///
/// Accept-Ranges Request Header
/// The Accept-Ranges response-header field allows the server to
/// indicate its acceptance of range requests for a resource:
///
#define HTTP_HEADER_ACCEPT_RANGES "Accept-Ranges"
///
/// Accept-Encoding Request Header
/// The Accept-Encoding request-header field is similar to Accept,
/// but restricts the content-codings that are acceptable in the response.
///
#define HTTP_HEADER_ACCEPT_ENCODING "Accept-Encoding"
///
/// Content-Encoding Header
/// The Content-Encoding entity-header field is used as a modifier to the media-type.
/// When present, its value indicates what additional content codings have been applied
/// to the entity-body, and thus what decoding mechanisms must be applied in order to
/// obtain the media-type referenced by the Content-Type header field. Content-Encoding
/// is primarily used to allow a document to be compressed without losing the identity
/// of its underlying media type.
///
#define HTTP_HEADER_CONTENT_ENCODING "Content-Encoding"
///
/// HTTP Content-Encoding Compression types
///
#define HTTP_CONTENT_ENCODING_IDENTITY "identity" /// No transformation is used. This is the default value for content coding.
#define HTTP_CONTENT_ENCODING_GZIP "gzip" /// Content-Encoding: GNU zip format (described in RFC 1952).
#define HTTP_CONTENT_ENCODING_COMPRESS "compress" /// encoding format produced by the common UNIX file compression program "compress".
#define HTTP_CONTENT_ENCODING_DEFLATE "deflate" /// The "zlib" format defined in RFC 1950 in combination with the "deflate"
/// compression mechanism described in RFC 1951.
///
/// Content-Type Header
/// The Content-Type entity-header field indicates the media type of the entity-body sent to
/// the recipient or, in the case of the HEAD method, the media type that would have been sent
/// had the request been a GET.
///
#define HTTP_HEADER_CONTENT_TYPE "Content-Type"
//
// Common Media Types defined in http://www.iana.org/assignments/media-types/media-types.xhtml
//
#define HTTP_CONTENT_TYPE_APP_JSON "application/json"
#define HTTP_CONTENT_TYPE_APP_OCTET_STREAM "application/octet-stream"
#define HTTP_CONTENT_TYPE_TEXT_HTML "text/html"
#define HTTP_CONTENT_TYPE_TEXT_PLAIN "text/plain"
#define HTTP_CONTENT_TYPE_TEXT_CSS "text/css"
#define HTTP_CONTENT_TYPE_TEXT_XML "text/xml"
#define HTTP_CONTENT_TYPE_IMAGE_GIF "image/gif"
#define HTTP_CONTENT_TYPE_IMAGE_JPEG "image/jpeg"
#define HTTP_CONTENT_TYPE_IMAGE_PNG "image/png"
#define HTTP_CONTENT_TYPE_IMAGE_SVG_XML "image/svg+xml"
///
/// Content-Length Header
/// The Content-Length entity-header field indicates the size of the entity-body,
/// in decimal number of OCTETs, sent to the recipient or, in the case of the HEAD
/// method, the size of the entity-body that would have been sent had the request been a GET.
///
#define HTTP_HEADER_CONTENT_LENGTH "Content-Length"
///
/// Transfer-Encoding Header
/// The Transfer-Encoding general-header field indicates what (if any) type of transformation
/// has been applied to the message body in order to safely transfer it between the sender
/// and the recipient. This differs from the content-coding in that the transfer-coding
/// is a property of the message, not of the entity.
///
#define HTTP_HEADER_TRANSFER_ENCODING "Transfer-Encoding"
///
/// User Agent Request Header
///
/// The User-Agent request-header field contains information about the user agent originating
/// the request. This is for statistical purposes, the tracing of protocol violations, and
/// automated recognition of user agents for the sake of tailoring responses to avoid
/// particular user agent limitations. User agents SHOULD include this field with requests.
/// The field can contain multiple product tokens and comments identifying the agent and any
/// subproducts which form a significant part of the user agent.
/// By convention, the product tokens are listed in order of their significance for
/// identifying the application.
///
#define HTTP_HEADER_USER_AGENT "User-Agent"
///
/// Host Request Header
///
/// The Host request-header field specifies the Internet host and port number of the resource
/// being requested, as obtained from the original URI given by the user or referring resource
///
#define HTTP_HEADER_HOST "Host"
///
/// Location Response Header
///
/// The Location response-header field is used to redirect the recipient to a location other than
/// the Request-URI for completion of the request or identification of a new resource.
/// For 201 (Created) responses, the Location is that of the new resource which was created by
/// the request. For 3xx responses, the location SHOULD indicate the server's preferred URI for
/// automatic redirection to the resource. The field value consists of a single absolute URI.
///
#define HTTP_HEADER_LOCATION "Location"
///
/// The If-Match request-header field is used with a method to make it conditional.
/// A client that has one or more entities previously obtained from the resource
/// can verify that one of those entities is current by including a list of their
/// associated entity tags in the If-Match header field.
/// The purpose of this feature is to allow efficient updates of cached information
/// with a minimum amount of transaction overhead. It is also used, on updating requests,
/// to prevent inadvertent modification of the wrong version of a resource.
/// As a special case, the value "*" matches any current entity of the resource.
///
#define HTTP_HEADER_IF_MATCH "If-Match"
///
/// The If-None-Match request-header field is used with a method to make it conditional.
/// A client that has one or more entities previously obtained from the resource can verify
/// that none of those entities is current by including a list of their associated entity
/// tags in the If-None-Match header field. The purpose of this feature is to allow efficient
/// updates of cached information with a minimum amount of transaction overhead. It is also used
/// to prevent a method (e.g. PUT) from inadvertently modifying an existing resource when the
/// client believes that the resource does not exist.
///
#define HTTP_HEADER_IF_NONE_MATCH "If-None-Match"
///
/// Authorization Request Header
/// The Authorization field value consists of credentials
/// containing the authentication information of the user agent for
/// the realm of the resource being requested.
///
#define HTTP_HEADER_AUTHORIZATION "Authorization"
///
/// ETAG Response Header
/// The ETag response-header field provides the current value of the entity tag
/// for the requested variant.
///
#define HTTP_HEADER_ETAG "ETag"
///
/// Custom header field checked by the iLO web server to
/// specify a client session key.
/// Example: X-Auth-Token: 24de6b1f8fa147ad59f6452def628798
///
#define HTTP_HEADER_X_AUTH_TOKEN "X-Auth-Token"
///
/// Expect Header
/// The "Expect" header field in a request indicates a certain set of
/// behaviors (expectations) that need to be supported by the server in
/// order to properly handle this request. The only such expectation
/// defined by this specification is 100-continue.
///
#define HTTP_HEADER_EXPECT "Expect"
///
/// Expect Header Value
///
#define HTTP_EXPECT_100_CONTINUE "100-continue"
#pragma pack()
#endif

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/** @file
The definition for iSCSI Boot Firmware Table, it's defined in Microsoft's
iSCSI Boot Firmware Table(iBFT) as Defined in ACPI 3.0b Specification.
Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _ISCSI_BOOT_FIRMWARE_TABLE_H_
#define _ISCSI_BOOT_FIRMWARE_TABLE_H_
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_REVISION 0x01
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_ALIGNMENT 8
///
/// Structure Type/ID
///
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_RESERVED_STRUCTURE_ID 0
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE_ID 1
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_ID 2
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_ID 3
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_ID 4
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_EXTERNSIONS_STRUCTURE_ID 5
///
/// from the definition of IP_PREFIX_ORIGIN Enumeration in MSDN,
/// not defined in Microsoft iBFT document.
///
typedef enum {
IpPrefixOriginOther = 0,
IpPrefixOriginManual,
IpPrefixOriginWellKnown,
IpPrefixOriginDhcp,
IpPrefixOriginRouterAdvertisement,
IpPrefixOriginUnchanged = 16
} IP_PREFIX_VALUE;
#pragma pack(1)
///
/// iBF Table Header
///
typedef struct {
UINT32 Signature;
UINT32 Length;
UINT8 Revision;
UINT8 Checksum;
UINT8 OemId[6];
UINT64 OemTableId;
UINT8 Reserved[24];
} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_HEADER;
///
/// Common Header of Boot Firmware Table Structure
///
typedef struct {
UINT8 StructureId;
UINT8 Version;
UINT16 Length;
UINT8 Index;
UINT8 Flags;
} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_HEADER;
///
/// Control Structure
///
typedef struct {
EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_HEADER Header;
UINT16 Extensions;
UINT16 InitiatorOffset;
UINT16 NIC0Offset;
UINT16 Target0Offset;
UINT16 NIC1Offset;
UINT16 Target1Offset;
} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE;
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE_VERSION 0x1
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE_FLAG_BOOT_FAILOVER BIT0
///
/// Initiator Structure
///
typedef struct {
EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_HEADER Header;
EFI_IPv6_ADDRESS ISnsServer;
EFI_IPv6_ADDRESS SlpServer;
EFI_IPv6_ADDRESS PrimaryRadiusServer;
EFI_IPv6_ADDRESS SecondaryRadiusServer;
UINT16 IScsiNameLength;
UINT16 IScsiNameOffset;
} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE;
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_VERSION 0x1
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_FLAG_BLOCK_VALID BIT0
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_FLAG_BOOT_SELECTED BIT1
///
/// NIC Structure
///
typedef struct {
EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_HEADER Header;
EFI_IPv6_ADDRESS Ip;
UINT8 SubnetMaskPrefixLength;
UINT8 Origin;
EFI_IPv6_ADDRESS Gateway;
EFI_IPv6_ADDRESS PrimaryDns;
EFI_IPv6_ADDRESS SecondaryDns;
EFI_IPv6_ADDRESS DhcpServer;
UINT16 VLanTag;
UINT8 Mac[6];
UINT16 PciLocation;
UINT16 HostNameLength;
UINT16 HostNameOffset;
} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE;
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_VERSION 0x1
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_BLOCK_VALID BIT0
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_BOOT_SELECTED BIT1
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_GLOBAL BIT2
///
/// Target Structure
///
typedef struct {
EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_HEADER Header;
EFI_IPv6_ADDRESS Ip;
UINT16 Port;
UINT8 BootLun[8];
UINT8 CHAPType;
UINT8 NicIndex;
UINT16 IScsiNameLength;
UINT16 IScsiNameOffset;
UINT16 CHAPNameLength;
UINT16 CHAPNameOffset;
UINT16 CHAPSecretLength;
UINT16 CHAPSecretOffset;
UINT16 ReverseCHAPNameLength;
UINT16 ReverseCHAPNameOffset;
UINT16 ReverseCHAPSecretLength;
UINT16 ReverseCHAPSecretOffset;
} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE;
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_VERSION 0x1
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_BLOCK_VALID BIT0
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_BOOT_SELECTED BIT1
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_RADIUS_CHAP BIT2
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_RADIUS_RCHAP BIT3
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_CHAP_TYPE_NO_CHAP 0
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_CHAP_TYPE_CHAP 1
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_CHAP_TYPE_MUTUAL_CHAP 2
#pragma pack()
#endif

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/** @file
IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
See IPMI specification, Appendix G, Command Assignments
and Appendix H, Sub-function Assignments.
Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _IPMI_H_
#define _IPMI_H_
#include <IndustryStandard/IpmiNetFnChassis.h>
#include <IndustryStandard/IpmiNetFnBridge.h>
#include <IndustryStandard/IpmiNetFnSensorEvent.h>
#include <IndustryStandard/IpmiNetFnApp.h>
#include <IndustryStandard/IpmiNetFnFirmware.h>
#include <IndustryStandard/IpmiNetFnStorage.h>
#include <IndustryStandard/IpmiNetFnTransport.h>
#include <IndustryStandard/IpmiNetFnGroupExtension.h>
#endif

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/** @file
IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
This file contains all NetFn App commands, including:
IPM Device "Global" Commands (Chapter 20)
Firmware Firewall & Command Discovery Commands (Chapter 21)
BMC Watchdog Timer Commands (Chapter 27)
IPMI Messaging Support Commands (Chapter 22)
RMCP+ Support and Payload Commands (Chapter 24)
See IPMI specification, Appendix G, Command Assignments
and Appendix H, Sub-function Assignments.
Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _IPMI_NET_FN_APP_H_
#define _IPMI_NET_FN_APP_H_
#pragma pack(1)
//
// Net function definition for App command
//
#define IPMI_NETFN_APP 0x06
//
// Below is Definitions for IPM Device "Global" Commands (Chapter 20)
//
//
// Definitions for Get Device ID command
//
#define IPMI_APP_GET_DEVICE_ID 0x1
//
// Constants and Structure definitions for "Get Device ID" command to follow here
//
typedef struct {
UINT8 CompletionCode;
UINT8 DeviceId;
UINT8 DeviceRevision : 4;
UINT8 Reserved : 3;
UINT8 DeviceSdr : 1;
UINT8 MajorFirmwareRev : 7;
UINT8 UpdateMode : 1;
UINT8 MinorFirmwareRev;
UINT8 SpecificationVersion;
UINT8 SensorDeviceSupport : 1;
UINT8 SdrRepositorySupport : 1;
UINT8 SelDeviceSupport : 1;
UINT8 FruInventorySupport : 1;
UINT8 IpmbMessageReceiver : 1;
UINT8 IpmbMessageGenerator : 1;
UINT8 BridgeSupport : 1;
UINT8 ChassisSupport : 1;
UINT8 ManufacturerId[3];
UINT16 ProductId;
UINT32 AuxFirmwareRevInfo;
} IPMI_GET_DEVICE_ID_RESPONSE;
//
// Definitions for Cold Reset command
//
#define IPMI_APP_COLD_RESET 0x2
//
// Constants and Structure definitions for "Cold Reset" command to follow here
//
//
// Definitions for Warm Reset command
//
#define IPMI_APP_WARM_RESET 0x3
//
// Constants and Structure definitions for "Warm Reset" command to follow here
//
//
// Definitions for Get Self Results command
//
#define IPMI_APP_GET_SELFTEST_RESULTS 0x4
//
// Constants and Structure definitions for "Get Self Test Results" command to follow here
//
typedef struct {
UINT8 CompletionCode;
UINT8 Result;
UINT8 Param;
} IPMI_SELF_TEST_RESULT_RESPONSE;
#define IPMI_APP_SELFTEST_NO_ERROR 0x55
#define IPMI_APP_SELFTEST_NOT_IMPLEMENTED 0x56
#define IPMI_APP_SELFTEST_ERROR 0x57
#define IPMI_APP_SELFTEST_FATAL_HW_ERROR 0x58
#define IPMI_APP_SELFTEST_INACCESSIBLE_SEL 0x80
#define IPMI_APP_SELFTEST_INACCESSIBLE_SDR 0x40
#define IPMI_APP_SELFTEST_INACCESSIBLE_FRU 0x20
#define IPMI_APP_SELFTEST_IPMB_SIGNAL_FAIL 0x10
#define IPMI_APP_SELFTEST_SDR_REPOSITORY_EMPTY 0x08
#define IPMI_APP_SELFTEST_FRU_CORRUPT 0x04
#define IPMI_APP_SELFTEST_FW_BOOTBLOCK_CORRUPT 0x02
#define IPMI_APP_SELFTEST_FW_CORRUPT 0x01
//
// Definitions for Manufacturing Test ON command
//
#define IPMI_APP_MANUFACTURING_TEST_ON 0x5
//
// Constants and Structure definitions for "Manufacturing Test ON" command to follow here
//
//
// Definitions for Set ACPI Power State command
//
#define IPMI_APP_SET_ACPI_POWERSTATE 0x6
//
// Constants and Structure definitions for "Set ACPI Power State" command to follow here
//
typedef struct {
UINT8 AcpiSystemPowerState : 7;
UINT8 AcpiSystemStateChange : 1;
UINT8 AcpiDevicePowerState : 7;
UINT8 AcpiDeviceStateChange : 1;
} IPMI_SET_ACPI_POWER_STATE_REQUEST;
//
// Definitions for Get ACPI Power State command
//
#define IPMI_APP_GET_ACPI_POWERSTATE 0x7
//
// Constants and Structure definitions for "Get ACPI Power State" command to follow here
//
//
// Definitions for Get Device GUID command
//
#define IPMI_APP_GET_DEVICE_GUID 0x8
//
// Constants and Structure definitions for "Get Device GUID" command to follow here
//
//
// Message structure definition for "Get Device Guid" IPMI command
//
typedef struct {
UINT8 CompletionCode;
UINT8 Guid[16];
} IPMI_GET_DEVICE_GUID_RESPONSE;
//
// Below is Definitions for BMC Watchdog Timer Commands (Chapter 27)
//
//
// Definitions for Reset WatchDog Timer command
//
#define IPMI_APP_RESET_WATCHDOG_TIMER 0x22
//
// Constants and Structure definitions for "Reset WatchDog Timer" command to follow here
//
typedef struct {
UINT8 TimerUse : 3;
UINT8 Reserved : 3;
UINT8 TimerRunning : 1;
UINT8 TimerUseExpirationFlagLog : 1;
} IPMI_WATCHDOG_TIMER_USE;
//
// Definitions for Set WatchDog Timer command
//
#define IPMI_APP_SET_WATCHDOG_TIMER 0x24
//
// Constants and Structure definitions for "Set WatchDog Timer" command to follow here
//
typedef struct {
IPMI_WATCHDOG_TIMER_USE TimerUse;
UINT8 TimerActions;
UINT8 PretimeoutInterval;
UINT8 TimerUseExpirationFlagsClear;
UINT16 InitialCountdownValue;
} IPMI_SET_WATCHDOG_TIMER_REQUEST;
//
// Definitions for Get WatchDog Timer command
//
#define IPMI_APP_GET_WATCHDOG_TIMER 0x25
//
// Constants and Structure definitions for "Get WatchDog Timer" command to follow here
//
typedef struct {
UINT8 CompletionCode;
IPMI_WATCHDOG_TIMER_USE TimerUse;
UINT8 TimerActions;
UINT8 PretimeoutInterval;
UINT8 TimerUseExpirationFlagsClear;
UINT16 InitialCountdownValue;
UINT16 PresentCountdownValue;
} IPMI_GET_WATCHDOG_TIMER_RESPONSE;
//
// Below is Definitions for IPMI Messaging Support Commands (Chapter 22)
//
//
// Definitions for Set BMC Global Enables command
//
#define IPMI_APP_SET_BMC_GLOBAL_ENABLES 0x2E
//
// Constants and Structure definitions for "Set BMC Global Enables " command to follow here
//
//
// Definitions for Get BMC Global Enables command
//
#define IPMI_APP_GET_BMC_GLOBAL_ENABLES 0x2F
//
// Constants and Structure definitions for "Get BMC Global Enables " command to follow here
//
//
// Definitions for Clear Message Flags command
//
#define IPMI_APP_CLEAR_MESSAGE_FLAGS 0x30
//
// Constants and Structure definitions for "Clear Message Flags" command to follow here
//
//
// Definitions for Get Message Flags command
//
#define IPMI_APP_GET_MESSAGE_FLAGS 0x31
//
// Constants and Structure definitions for "Get Message Flags" command to follow here
//
//
// Definitions for Enable Message Channel Receive command
//
#define IPMI_APP_ENABLE_MESSAGE_CHANNEL_RECEIVE 0x32
//
// Constants and Structure definitions for "Enable Message Channel Receive" command to follow here
//
//
// Definitions for Get Message command
//
#define IPMI_APP_GET_MESSAGE 0x33
//
// Constants and Structure definitions for "Get Message" command to follow here
//
//
// Definitions for Send Message command
//
#define IPMI_APP_SEND_MESSAGE 0x34
//
// Constants and Structure definitions for "Send Message" command to follow here
//
//
// Definitions for Read Event Message Buffer command
//
#define IPMI_APP_READ_EVENT_MSG_BUFFER 0x35
//
// Constants and Structure definitions for "Read Event Message Buffer" command to follow here
//
//
// Definitions for Get BT Interface Capabilities command
//
#define IPMI_APP_GET_BT_INTERFACE_CAPABILITY 0x36
//
// Constants and Structure definitions for "Get BT Interface Capabilities" command to follow here
//
//
// Definitions for Get System GUID command
//
#define IPMI_APP_GET_SYSTEM_GUID 0x37
//
// Constants and Structure definitions for "Get System GUID" command to follow here
//
//
// Definitions for Get Channel Authentication Capabilities command
//
#define IPMI_APP_GET_CHANNEL_AUTHENTICATION_CAPABILITIES 0x38
//
// Constants and Structure definitions for "Get Channel Authentication Capabilities" command to follow here
//
//
// Definitions for Get Session Challenge command
//
#define IPMI_APP_GET_SESSION_CHALLENGE 0x39
//
// Constants and Structure definitions for "Get Session Challenge" command to follow here
//
//
// Definitions for Activate Session command
//
#define IPMI_APP_ACTIVATE_SESSION 0x3A
//
// Constants and Structure definitions for "Activate Session" command to follow here
//
//
// Definitions for Set Session Privelege Level command
//
#define IPMI_APP_SET_SESSION_PRIVELEGE_LEVEL 0x3B
//
// Constants and Structure definitions for "Set Session Privelege Level" command to follow here
//
//
// Definitions for Close Session command
//
#define IPMI_APP_CLOSE_SESSION 0x3C
//
// Constants and Structure definitions for "Close Session" command to follow here
//
//
// Definitions for Get Session Info command
//
#define IPMI_APP_GET_SESSION_INFO 0x3D
//
// Constants and Structure definitions for "Get Session Info" command to follow here
//
//
// Definitions for Get Auth Code command
//
#define IPMI_APP_GET_AUTHCODE 0x3F
//
// Constants and Structure definitions for "Get AuthCode" command to follow here
//
//
// Definitions for Set Channel Access command
//
#define IPMI_APP_SET_CHANNEL_ACCESS 0x40
//
// Constants and Structure definitions for "Set Channel Access" command to follow here
//
//
// Definitions for Get Channel Access command
//
#define IPMI_APP_GET_CHANNEL_ACCESS 0x41
//
// Constants and Structure definitions for "Get Channel Access" command to follow here
//
typedef struct {
UINT8 ChannelNo : 4;
UINT8 Reserve1 : 4;
UINT8 Reserve2 : 6;
UINT8 MemoryType : 2;
} IPMI_GET_CHANNEL_ACCESS_REQUEST;
typedef struct {
UINT8 CompletionCode;
UINT8 AccessMode : 3;
UINT8 UserLevelAuthEnabled : 1;
UINT8 MessageAuthEnable : 1;
UINT8 Alert : 1;
UINT8 Reserve1 : 2;
UINT8 ChannelPriviledgeLimit : 4;
UINT8 Reserve2 : 4;
} IPMI_GET_CHANNEL_ACCESS_RESPONSE;
//
// Definitions for Get Channel Info command
//
#define IPMI_APP_GET_CHANNEL_INFO 0x42
//
// Constants and Structure definitions for "Get Channel Info" command to follow here
//
typedef struct {
UINT8 CompletionCode;
UINT8 ChannelNo : 4;
UINT8 Reserve1 : 4;
UINT8 ChannelMediumType : 7;
UINT8 Reserve2 : 1;
UINT8 ChannelProtocolType : 5;
UINT8 Reserve3 : 3;
UINT8 ActiveSessionCount : 6;
UINT8 SessionSupport : 2;
UINT8 VendorId[3];
UINT16 AuxChannelInfo;
} IPMI_GET_CHANNEL_INFO_RESPONSE;
//
// Definitions for Get Channel Info command
//
#define IPMI_APP_GET_CHANNEL_INFO 0x42
//
// Constants and Structure definitions for "Get Channel Info" command to follow here
//
//
// Definitions for Set User Access command
//
#define IPMI_APP_SET_USER_ACCESS 0x43
//
// Constants and Structure definitions for "Set User Access" command to follow here
//
//
// Definitions for Get User Access command
//
#define IPMI_APP_GET_USER_ACCESS 0x44
//
// Constants and Structure definitions for "Get User Access" command to follow here
//
//
// Definitions for Set User Name command
//
#define IPMI_APP_SET_USER_NAME 0x45
//
// Constants and Structure definitions for "Set User Name" command to follow here
//
//
// Definitions for Get User Name command
//
#define IPMI_APP_GET_USER_NAME 0x46
//
// Constants and Structure definitions for "Get User Name" command to follow here
//
//
// Definitions for Set User Password command
//
#define IPMI_APP_SET_USER_PASSWORD 0x47
//
// Constants and Structure definitions for "Set User Password" command to follow here
//
//
// Below is Definitions for RMCP+ Support and Payload Commands (Chapter 24)
//
//
// Definitions for Activate Payload command
//
#define IPMI_APP_ACTIVATE_PAYLOAD 0x48
//
// Constants and Structure definitions for "Activate Payload" command to follow here
//
//
// Definitions for De-Activate Payload command
//
#define IPMI_APP_DEACTIVATE_PAYLOAD 0x49
//
// Constants and Structure definitions for "DeActivate Payload" command to follow here
//
//
// Definitions for Get Payload activation Status command
//
#define IPMI_APP_GET_PAYLOAD_ACTIVATION_STATUS 0x4a
//
// Constants and Structure definitions for "Get Payload activation Status" command to follow here
//
//
// Definitions for Get Payload Instance Info command
//
#define IPMI_APP_GET_PAYLOAD_INSTANCE_INFO 0x4b
//
// Constants and Structure definitions for "Get Payload Instance Info" command to follow here
//
//
// Definitions for Set User Payload Access command
//
#define IPMI_APP_SET_USER_PAYLOAD_ACCESS 0x4C
//
// Constants and Structure definitions for "Set User Payload Access" command to follow here
//
//
// Definitions for Get User Payload Access command
//
#define IPMI_APP_GET_USER_PAYLOAD_ACCESS 0x4D
//
// Constants and Structure definitions for "Get User Payload Access" command to follow here
//
//
// Definitions for Get Channel Payload Support command
//
#define IPMI_APP_GET_CHANNEL_PAYLOAD_SUPPORT 0x4E
//
// Constants and Structure definitions for "Get Channel Payload Support" command to follow here
//
//
// Definitions for Get Channel Payload Version command
//
#define IPMI_APP_GET_CHANNEL_PAYLOAD_VERSION 0x4F
//
// Constants and Structure definitions for "Get Channel Payload Version" command to follow here
//
//
// Definitions for Get Channel OEM Payload Info command
//
#define IPMI_APP_GET_CHANNEL_OEM_PAYLOAD_INFO 0x50
//
// Constants and Structure definitions for "Get Channel OEM Payload Info" command to follow here
//
//
// Definitions for Master Write-Read command
//
#define IPMI_APP_MASTER_WRITE_READ 0x52
//
// Constants and Structure definitions for "Master Write Read" command to follow here
//
//
// Definitions for Get Channel Cipher Suites command
//
#define IPMI_APP_GET_CHANNEL_CIPHER_SUITES 0x54
//
// Constants and Structure definitions for "Get Channel Cipher Suites" command to follow here
//
//
// Below is Definitions for RMCP+ Support and Payload Commands (Chapter 24, Section 3)
//
//
// Definitions for Suspend-Resume Payload Encryption command
//
#define IPMI_APP_SUSPEND_RESUME_PAYLOAD_ENCRYPTION 0x55
//
// Constants and Structure definitions for "Suspend-Resume Payload Encryption" command to follow here
//
//
// Below is Definitions for IPMI Messaging Support Commands (Chapter 22, Section 25 and 9)
//
//
// Definitions for Set Channel Security Keys command
//
#define IPMI_APP_SET_CHANNEL_SECURITY_KEYS 0x56
//
// Constants and Structure definitions for "Set Channel Security Keys" command to follow here
//
//
// Definitions for Get System Interface Capabilities command
//
#define IPMI_APP_GET_SYSTEM_INTERFACE_CAPABILITIES 0x57
//
// Constants and Structure definitions for "Get System Interface Capabilities" command to follow here
//
#pragma pack()
#endif

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/** @file
IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
IPMI Intelligent Chassis Management Bus Bridge Specification Version 1.0,
Revision 1.3.
See IPMI specification, Appendix G, Command Assignments
and Appendix H, Sub-function Assignments.
Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _IPMI_NET_FN_BRIDGE_H_
#define _IPMI_NET_FN_BRIDGE_H_
//
// Net function definition for Bridge command
//
#define IPMI_NETFN_BRIDGE 0x02
//
// Definitions for Get Bridge State command
//
#define IPMI_BRIDGE_GET_STATE 0x00
//
// Constants and Structure definitions for "Get Bridge State" command to follow here
//
//
// Definitions for Set Bridge State command
//
#define IPMI_BRIDGE_SET_STATE 0x01
//
// Constants and Structure definitions for "Set Bridge State" command to follow here
//
//
// Definitions for Get ICMB Address command
//
#define IPMI_BRIDGE_GET_ICMB_ADDRESS 0x02
//
// Constants and Structure definitions for "Get ICMB Address" command to follow here
//
//
// Definitions for Set ICMB Address command
//
#define IPMI_BRIDGE_SET_ICMB_ADDRESS 0x03
//
// Constants and Structure definitions for "Set ICMB Address" command to follow here
//
//
// Definitions for Set Bridge Proxy Address command
//
#define IPMI_BRIDGE_SET_PROXY_ADDRESS 0x04
//
// Constants and Structure definitions for "Set Bridge Proxy Address" command to follow here
//
//
// Definitions for Get Bridge Statistics command
//
#define IPMI_BRIDGE_GET_BRIDGE_STATISTICS 0x05
//
// Constants and Structure definitions for "Get Bridge Statistics" command to follow here
//
//
// Definitions for Get ICMB Capabilities command
//
#define IPMI_BRIDGE_GET_ICMB_CAPABILITIES 0x06
//
// Constants and Structure definitions for "Get ICMB Capabilities" command to follow here
//
//
// Definitions for Clear Bridge Statistics command
//
#define IPMI_BRIDGE_CLEAR_STATISTICS 0x08
//
// Constants and Structure definitions for "Clear Bridge Statistics" command to follow here
//
//
// Definitions for Get Bridge Proxy Address command
//
#define IPMI_BRIDGE_GET_PROXY_ADDRESS 0x09
//
// Constants and Structure definitions for "Get Bridge Proxy Address" command to follow here
//
//
// Definitions for Get ICMB Connector Info command
//
#define IPMI_BRIDGE_GET_ICMB_CONNECTOR_INFO 0x0A
//
// Constants and Structure definitions for "Get ICMB Connector Info " command to follow here
//
//
// Definitions for Get ICMB Connection ID command
//
#define IPMI_BRIDGE_GET_ICMB_CONNECTION_ID 0x0B
//
// Constants and Structure definitions for "Get ICMB Connection ID" command to follow here
//
//
// Definitions for Get ICMB Connection ID command
//
#define IPMI_BRIDGE_SEND_ICMB_CONNECTION_ID 0x0C
//
// Constants and Structure definitions for "Send ICMB Connection ID" command to follow here
//
//
// Definitions for Prepare for Discoveery command
//
#define IPMI_BRIDGE_PREPARE_FOR_DISCOVERY 0x10
//
// Constants and Structure definitions for "Prepare for Discoveery" command to follow here
//
//
// Definitions for Get Addresses command
//
#define IPMI_BRIDGE_GET_ADDRESSES 0x11
//
// Constants and Structure definitions for "Get Addresses" command to follow here
//
//
// Definitions for Set Discovered command
//
#define IPMI_BRIDGE_SET_DISCOVERED 0x12
//
// Constants and Structure definitions for "Set Discovered" command to follow here
//
//
// Definitions for Get Chassis Device ID command
//
#define IPMI_BRIDGE_GET_CHASSIS_DEVICEID 0x13
//
// Constants and Structure definitions for "Get Chassis Device ID" command to follow here
//
//
// Definitions for Set Chassis Device ID command
//
#define IPMI_BRIDGE_SET_CHASSIS_DEVICEID 0x14
//
// Constants and Structure definitions for "Set Chassis Device ID" command to follow here
//
//
// Definitions for Bridge Request command
//
#define IPMI_BRIDGE_REQUEST 0x20
//
// Constants and Structure definitions for "Bridge Request" command to follow here
//
//
// Definitions for Bridge Message command
//
#define IPMI_BRIDGE_MESSAGE 0x21
//
// Constants and Structure definitions for "Bridge Message" command to follow here
//
//
// Definitions for Get Event Count command
//
#define IPMI_BRIDGE_GET_EVENT_COUNT 0x30
//
// Constants and Structure definitions for "Get Event Count" command to follow here
//
//
// Definitions for Set Event Destination command
//
#define IPMI_BRIDGE_SET_EVENT_DESTINATION 0x31
//
// Constants and Structure definitions for "Set Event Destination" command to follow here
//
//
// Definitions for Set Event Reception State command
//
#define IPMI_BRIDGE_SET_EVENT_RECEPTION_STATE 0x32
//
// Constants and Structure definitions for "Set Event Reception State" command to follow here
//
//
// Definitions for Set Event Reception State command
//
#define IPMI_BRIDGE_SET_EVENT_RECEPTION_STATE 0x32
//
// Constants and Structure definitions for "Set Event Reception State" command to follow here
//
//
// Definitions for Send ICMB Event Message command
//
#define IPMI_BRIDGE_SEND_ICMB_EVENT_MESSAGE 0x33
//
// Constants and Structure definitions for "Send ICMB Event Message" command to follow here
//
#endif

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/** @file
IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
This file contains all NetFn Chassis commands, including:
Chassis Commands (Chapter 28)
See IPMI specification, Appendix G, Command Assignments
and Appendix H, Sub-function Assignments.
Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _IPMI_NET_FN_CHASSIS_H_
#define _IPMI_NET_FN_CHASSIS_H_
#pragma pack (1)
//
// Net function definition for Chassis command
//
#define IPMI_NETFN_CHASSIS 0x00
//
// Below is Definitions for Chassis commands (Chapter 28)
//
//
// Definitions for Get Chassis Capabilities command
//
#define IPMI_CHASSIS_GET_CAPABILITIES 0x00
//
// Constants and Structure definitions for "Get Chassis Capabilities" command to follow here
//
//
// Definitions for Get Chassis Status command
//
#define IPMI_CHASSIS_GET_STATUS 0x01
//
// Constants and Structure definitions for "Get Chassis Status" command to follow here
//
//
// Definitions for Chassis Control command
//
#define IPMI_CHASSIS_CONTROL 0x02
//
// Constants and Structure definitions for "Chassis Control" command to follow here
//
//
// Definitions for Chassis Reset command
//
#define IPMI_CHASSIS_RESET 0x03
//
// Constants and Structure definitions for "Chassis Reset" command to follow here
//
//
// Definitions for Chassis Identify command
//
#define IPMI_CHASSIS_IDENTIFY 0x04
//
// Constants and Structure definitions for "Chassis Identify" command to follow here
//
//
// Definitions for Set Chassis Capabilities command
//
#define IPMI_CHASSIS_SET_CAPABILITIES 0x05
//
// Constants and Structure definitions for "Set Chassis Capabilities" command to follow here
//
//
// Definitions for Set Power Restore Policy command
//
#define IPMI_CHASSIS_SET_POWER_RESTORE_POLICY 0x06
//
// Constants and Structure definitions for "Set Power Restore Policy" command to follow here
//
//
// Definitions for Get System Restart Cause command
//
#define IPMI_CHASSIS_GET_SYSTEM_RESTART_CAUSE 0x07
//
// Constants and Structure definitions for "Get System Restart Cause" command to follow here
//
typedef enum {
Unknown,
ChassisControlCommand,
ResetViaPushButton,
PowerupViaPowerButton,
WatchdogExpiration,
Oem,
AutoPowerOnAlwaysRestore,
AutoPowerOnRestorePrevious,
ResetViaPef,
PowerCycleViaPef,
SoftReset,
PowerUpViaRtc
} IPMI_SYSTEM_RESTART_CAUSE;
typedef struct {
UINT8 CompletionCode;
UINT8 Cause:4;
UINT8 Reserved:4;
UINT8 ChannelNumber;
} IPMI_GET_SYSTEM_RESTART_CAUSE_RESPONSE;
//
// Definitions for Set System BOOT options command
//
#define IPMI_CHASSIS_SET_SYSTEM_BOOT_OPTIONS 0x08
//
// Constants and Structure definitions for "Set System boot options" command to follow here
//
typedef struct {
UINT8 ParameterSelector:7;
UINT8 MarkParameterInvalid:1;
UINT8 ParameterData[1];
} IPMI_SET_BOOT_OPTIONS_REQUEST;
//
// Definitions for Get System BOOT options command
//
#define IPMI_CHASSIS_GET_SYSTEM_BOOT_OPTIONS 0x09
//
// Constants and Structure definitions for "Get System boot options" command to follow here
//
typedef struct {
UINT8 ParameterSelector:7;
UINT8 Reserved:1;
UINT8 SetSelector;
UINT8 BlockSelector;
} IPMI_GET_BOOT_OPTIONS_REQUEST;
typedef struct {
UINT8 Parameter;
UINT8 Valid;
UINT8 Data1;
UINT8 Data2;
UINT8 Data3;
UINT8 Data4;
UINT8 Data5;
} IPMI_GET_THE_SYSTEM_BOOT_OPTIONS;
typedef struct {
UINT8 ParameterVersion;
UINT8 ParameterValid;
UINT8 ChannelNumber;
UINT32 SessionId;
UINT32 TimeStamp;
UINT8 Reserved[3];
} IPMI_BOOT_INITIATOR;
//
// Response Parameters for IPMI Get Boot Options
//
typedef struct {
UINT8 SetInProgress: 2;
UINT8 Reserved: 6;
} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_0;
typedef struct {
UINT8 ServicePartitionSelector;
} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_1;
typedef struct {
UINT8 ServicePartitionDiscovered:1;
UINT8 ServicePartitionScanRequest:1;
UINT8 Reserved: 5;
} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_2;
typedef struct {
UINT8 BmcBootFlagValid: 5;
UINT8 Reserved: 3;
} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_3;
typedef struct {
UINT8 WriteMask;
UINT8 BootInitiatorAcknowledgeData;
} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_4;
#define BOOT_OPTION_HANDLED_BY_BIOS 0x01
typedef struct {
//
// Data 1
//
UINT8 Reserved0:6;
UINT8 PersistentOptions:1;
UINT8 BootFlagValid:1;
//
// Data 2
//
UINT8 LockReset:1;
UINT8 ScreenBlank:1;
UINT8 BootDeviceSelector:4;
UINT8 LockKeyboard:1;
UINT8 CmosClear:1;
//
//
// Data 3
UINT8 ConsoleRedirection:2;
UINT8 LockSleep:1;
UINT8 UserPasswordBypass:1;
UINT8 ForceProgressEventTrap:1;
UINT8 BiosVerbosity:2;
UINT8 LockPower:1;
//
// Data 4
//
UINT8 BiosMuxControlOverride:2;
UINT8 BiosSharedModeOverride:1;
UINT8 Reserved1:4;
} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5;
typedef struct {
UINT8 ChannelNumber:4;
UINT8 Reserved:4;
UINT8 SessionId[4];
UINT8 BootInfoTimeStamp[4];
} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_6;
typedef struct {
UINT8 SetSelector;
UINT8 BlockData[16];
} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_7;
typedef union {
IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_0 Parm0;
IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_1 Parm1;
IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_2 Parm2;
IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_3 Parm3;
IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_4 Parm4;
IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5 Parm5;
IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_6 Parm6;
IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_7 Parm7;
} IPMI_BOOT_OPTIONS_PARAMETERS;
typedef struct {
UINT8 CompletionCode;
UINT8 ParameterVersion:4;
UINT8 Reserved:4;
UINT8 ParameterSelector:7;
UINT8 ParameterValid:1;
UINT8 ParameterData[1];
} IPMI_GET_BOOT_OPTIONS_RESPONSE;
//
// Definitions for Set front panel button enables command
//
#define IPMI_CHASSIS_SET_FRONT_PANEL_BUTTON_ENABLES 0x0A
typedef struct {
UINT8 DisablePoweroffButton:1;
UINT8 DisableResetButton:1;
UINT8 DisableDiagnosticInterruptButton:1;
UINT8 DisableStandbyButton:1;
UINT8 Reserved:4;
} IPMI_CHASSIS_SET_FRONT_PANEL_BUTTON_ENABLES_REQUEST;
//
// Constants and Structure definitions for "Set front panel button enables" command to follow here
//
//
// Definitions for Set Power Cycle Interval command
//
#define IPMI_CHASSIS_SET_POWER_CYCLE_INTERVALS 0x0B
//
// Constants and Structure definitions for "Set Power Cycle Interval" command to follow here
//
//
// Definitions for Get POH Counter command
//
#define IPMI_CHASSIS_GET_POH_COUNTER 0x0F
//
// Constants and Structure definitions for "Get POH Counter" command to follow here
//
#pragma pack()
#endif

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/** @file
IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _IPMI_NET_FN_FIRMWARE_H_
#define _IPMI_NET_FN_FIRMWARE_H_
//
// Net function definition for Firmware command
//
#define IPMI_NETFN_FIRMWARE 0x08
//
// All Firmware commands and their structure definitions to follow here
//
#endif

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/** @file
IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _IPMI_NET_FN_GROUP_EXTENSION_H_
#define _IPMI_NET_FN_GROUP_EXTENSION_H_
//
// Net function definition for Group Extension command
//
#define IPMI_NETFN_GROUP_EXT 0x2C
//
// All Group Extension commands and their structure definitions to follow here
//
#endif

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/** @file
IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
This file contains all NetFn Sensor/Event commands, including:
Event Commands (Chapter 29)
PEF and Alerting Commands (Chapter 30)
Sensor Device Commands (Chapter 35)
See IPMI specification, Appendix G, Command Assignments
and Appendix H, Sub-function Assignments.
Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _IPMI_NET_FN_SENSOR_EVENT_H_
#define _IPMI_NET_FN_SENSOR_EVENT_H_
#pragma pack(1)
//
// Net function definition for Sensor command
//
#define IPMI_NETFN_SENSOR_EVENT 0x04
//
// All Sensor commands and their structure definitions to follow here
//
//
// Definitions for Send Platform Event Message command
//
#define IPMI_SENSOR_PLATFORM_EVENT_MESSAGE 0x02
typedef struct {
UINT8 GeneratorId;
UINT8 EvMRevision;
UINT8 SensorType;
UINT8 SensorNumber;
UINT8 EventDirType;
UINT8 OEMEvData1;
UINT8 OEMEvData2;
UINT8 OEMEvData3;
} IPMI_PLATFORM_EVENT_MESSAGE_DATA_REQUEST;
#pragma pack()
#endif

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/** @file
IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
This file contains all NetFn Storage commands, including:
FRU Inventory Commands (Chapter 34)
SDR Repository (Chapter 33)
System Event Log(SEL) Commands (Chapter 31)
SEL Record Formats (Chapter 32)
See IPMI specification, Appendix G, Command Assignments
and Appendix H, Sub-function Assignments.
Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _IPMI_NET_FN_STORAGE_H_
#define _IPMI_NET_FN_STORAGE_H_
#pragma pack(1)
//
// Net function definition for Storage command
//
#define IPMI_NETFN_STORAGE 0x0A
//
// All Storage commands and their structure definitions to follow here
//
//
// Below is Definitions for FRU Inventory Commands (Chapter 34)
//
//
// Definitions for Get Fru Inventory Area Info command
//
#define IPMI_STORAGE_GET_FRU_INVENTORY_AREAINFO 0x10
//
// Constants and Structure definitions for "Get Fru Inventory Area Info" command to follow here
//
//
// Definitions for Get Fru Data command
//
#define IPMI_STORAGE_READ_FRU_DATA 0x11
//
// Constants and Structure definitions for "Get Fru Data" command to follow here
//
typedef struct {
UINT8 FruDeviceId;
UINT16 FruOffset;
} IPMI_FRU_COMMON_DATA;
typedef struct {
IPMI_FRU_COMMON_DATA Data;
UINT8 Count;
} IPMI_FRU_READ_COMMAND;
//
// Definitions for Write Fru Data command
//
#define IPMI_STORAGE_WRITE_FRU_DATA 0x12
//
// Constants and Structure definitions for "Write Fru Data" command to follow here
//
typedef struct {
IPMI_FRU_COMMON_DATA Data;
UINT8 FruData[16];
} IPMI_FRU_WRITE_COMMAND;
//
// Below is Definitions for SDR Repository (Chapter 33)
//
//
// Definitions for Get SDR Repository Info command
//
#define IPMI_STORAGE_GET_SDR_REPOSITORY_INFO 0x20
//
// Constants and Structure definitions for "Get SDR Repository Info" command to follow here
//
typedef struct {
UINT8 CompletionCode;
UINT8 Version;
UINT16 RecordCount;
UINT16 FreeSpace;
UINT32 RecentAdditionTimeStamp;
UINT32 RecentEraseTimeStamp;
UINT8 SdrRepAllocInfoCmd : 1;
UINT8 SdrRepReserveCmd : 1;
UINT8 PartialAddSdrCmd : 1;
UINT8 DeleteSdrRepCmd : 1;
UINT8 Reserved : 1;
UINT8 SdrRepUpdateOp : 2;
UINT8 Overflow : 1;
} IPMI_GET_SDR_REPOSITORY_INFO;
//
// Definitions for Get SDR Repository Allocateion Info command
//
#define IPMI_STORAGE_GET_SDR_REPOSITORY_ALLOCATION_INFO 0x21
//
// Constants and Structure definitions for "Get SDR Repository Allocateion Info" command to follow here
//
//
// Definitions for Reserve SDR Repository command
//
#define IPMI_STORAGE_RESERVE_SDR_REPOSITORY 0x22
//
// Constants and Structure definitions for "Reserve SDR Repository" command to follow here
//
//
// Definitions for Get SDR command
//
#define IPMI_STORAGE_GET_SDR 0x23
//
// Constants and Structure definitions for "Get SDR" command to follow here
//
typedef struct {
UINT16 RecordId; // 1
UINT8 Version; // 3
UINT8 RecordType; // 4
UINT8 RecordLength; // 5
UINT8 OwnerId; // 6
UINT8 OwnerLun; // 7
UINT8 SensorNumber; // 8
UINT8 EntityId; // 9
UINT8 EntityInstance; // 10
UINT8 EventScanningEnabled : 1; // 11
UINT8 EventScanningDisabled : 1; // 11
UINT8 InitSensorType : 1; // 11
UINT8 InitHysteresis : 1; // 11
UINT8 InitThresholds : 1; // 11
UINT8 InitEvent : 1; // 11
UINT8 InitScanning : 1; // 11
UINT8 Reserved : 1; // 11
UINT8 EventMessageControl : 2; // 12
UINT8 ThresholdAccessSupport : 2; // 12
UINT8 HysteresisSupport : 2; // 12
UINT8 ReArmSupport : 1; // 12
UINT8 IgnoreSensor : 1; // 12
UINT8 SensorType; // 13
UINT8 EventType; // 14
UINT8 Reserved1[7]; // 15
UINT8 UnitType; // 22
UINT8 Reserved2; // 23
UINT8 Linearization : 7; // 24
UINT8 Reserved3 : 1; // 24
UINT8 MLo; // 25
UINT8 Toleremce : 6; // 26
UINT8 MHi : 2; // 26
UINT8 BLo; // 27
UINT8 AccuracyLow : 6; // 28
UINT8 BHi : 2; // 28
UINT8 Reserved4 : 2; // 29
UINT8 AccuracyExp : 2; // 29
UINT8 AccuracyHi : 4; // 29
UINT8 BExp : 4; // 30
UINT8 RExp : 4; // 30
UINT8 NominalReadingSpscified : 1; // 31
UINT8 NominalMaxSpscified : 1; // 31
UINT8 NominalMinSpscified : 1; // 31
UINT8 Reserved5 : 5; // 31
UINT8 NominalReading; // 32
UINT8 Reserved6[4]; // 33
UINT8 UpperNonRecoverThreshold; // 37
UINT8 UpperCriticalThreshold; // 38
UINT8 UpperNonCriticalThreshold; // 39
UINT8 LowerNonRecoverThreshold; // 40
UINT8 LowerCriticalThreshold; // 41
UINT8 LowerNonCriticalThreshold; // 42
UINT8 Reserved7[5]; // 43
UINT8 IdStringLength; // 48
UINT8 AsciiIdString[16]; // 49 - 64
} IPMI_SDR_RECORD_STRUCT_1;
typedef struct {
UINT16 RecordId; // 1
UINT8 Version; // 3
UINT8 RecordType; // 4
UINT8 RecordLength; // 5
UINT8 OwnerId; // 6
UINT8 OwnerLun; // 7
UINT8 SensorNumber; // 8
UINT8 EntityId; // 9
UINT8 EntityInstance; // 10
UINT8 SensorScanning : 1; // 11
UINT8 EventScanning : 1; // 11
UINT8 InitSensorType : 1; // 11
UINT8 InitHysteresis : 1; // 11
UINT8 InitThresholds : 1; // 11
UINT8 InitEvent : 1; // 11
UINT8 InitScanning : 1; // 11
UINT8 Reserved : 1; // 11
UINT8 EventMessageControl : 2; // 12
UINT8 ThresholdAccessSupport : 2; // 12
UINT8 HysteresisSupport : 2; // 12
UINT8 ReArmSupport : 1; // 12
UINT8 IgnoreSensor : 1; // 12
UINT8 SensorType; // 13
UINT8 EventType; // 14
UINT8 Reserved1[7]; // 15
UINT8 UnitType; // 22
UINT8 Reserved2[9]; // 23
UINT8 IdStringLength; // 32
UINT8 AsciiIdString[16]; // 33 - 48
} IPMI_SDR_RECORD_STRUCT_2;
typedef struct {
UINT8 Reserved1 : 1;
UINT8 ControllerSlaveAddress : 7;
UINT8 FruDeviceId;
UINT8 BusId : 3;
UINT8 Lun : 2;
UINT8 Reserved : 2;
UINT8 LogicalFruDevice : 1;
UINT8 Reserved3 : 4;
UINT8 ChannelNumber : 4;
} IPMI_FRU_DATA_INFO;
typedef struct {
UINT16 RecordId; // 1
UINT8 Version; // 3
UINT8 RecordType; // 4
UINT8 RecordLength; // 5
IPMI_FRU_DATA_INFO FruDeviceData; // 6
UINT8 Reserved1; // 10
UINT8 DeviceType; // 11
UINT8 DeviceTypeModifier; // 12
UINT8 FruEntityId; // 13
UINT8 FruEntityInstance; // 14
UINT8 OemReserved; // 15
UINT8 Length : 4; // 16
UINT8 Reserved2 : 1; // 16
UINT8 StringType : 3; // 16
UINT8 String[16]; // 17
} IPMI_SDR_RECORD_STRUCT_11;
typedef struct {
UINT16 NextRecordId; //1
UINT16 RecordId; //3
UINT8 Version; //5
UINT8 RecordType; //6
UINT8 RecordLength; //7
UINT8 ManufacturerId[3]; //8
UINT8 StringChars[20];
} IPMI_SDR_RECORD_STRUCT_C0;
typedef struct {
UINT16 NextRecordId; //1
UINT16 RecordId; //3
UINT8 Version; //5
UINT8 RecordType; //6
UINT8 RecordLength; //7
} IPMI_SDR_RECORD_STRUCT_HEADER;
typedef union {
IPMI_SDR_RECORD_STRUCT_1 SensorType1;
IPMI_SDR_RECORD_STRUCT_2 SensorType2;
IPMI_SDR_RECORD_STRUCT_11 SensorType11;
IPMI_SDR_RECORD_STRUCT_C0 SensorTypeC0;
IPMI_SDR_RECORD_STRUCT_HEADER SensorHeader;
} IPMI_SENSOR_RECORD_STRUCT;
typedef struct {
UINT16 ReservationId;
UINT16 RecordId;
UINT8 RecordOffset;
UINT8 BytesToRead;
} IPMI_GET_SDR_REQUEST;
//
// Definitions for Add SDR command
//
#define IPMI_STORAGE_ADD_SDR 0x24
//
// Constants and Structure definitions for "Add SDR" command to follow here
//
//
// Definitions for Partial Add SDR command
//
#define IPMI_STORAGE_PARTIAL_ADD_SDR 0x25
//
// Constants and Structure definitions for "Partial Add SDR" command to follow here
//
//
// Definitions for Delete SDR command
//
#define IPMI_STORAGE_DELETE_SDR 0x26
//
// Constants and Structure definitions for "Delete SDR" command to follow here
//
//
// Definitions for Clear SDR Repository command
//
#define IPMI_STORAGE_CLEAR_SDR 0x27
//
// Constants and Structure definitions for "Clear SDR Repository" command to follow here
//
//
// Definitions for Get SDR Repository Time command
//
#define IPMI_STORAGE_GET_SDR_REPOSITORY_TIME 0x28
//
// Constants and Structure definitions for "Get SDR Repository Time" command to follow here
//
//
// Definitions for Set SDR Repository Time command
//
#define IPMI_STORAGE_SET_SDR_REPOSITORY_TIME 0x29
//
// Constants and Structure definitions for "Set SDR Repository Time" command to follow here
//
//
// Definitions for Enter SDR Repository Update Mode command
//
#define IPMI_STORAGE_ENTER_SDR_UPDATE_MODE 0x2A
//
// Constants and Structure definitions for "Enter SDR Repository Update Mode" command to follow here
//
//
// Definitions for Exit SDR Repository Update Mode command
//
#define IPMI_STORAGE_EXIT_SDR_UPDATE_MODE 0x2B
//
// Constants and Structure definitions for "Exit SDR Repository Update Mode" command to follow here
//
//
// Definitions for Run Initialize Agent command
//
#define IPMI_STORAGE_RUN_INIT_AGENT 0x2C
//
// Constants and Structure definitions for "Run Initialize Agent" command to follow here
//
//
// Below is Definitions for System Event Log(SEL) Commands (Chapter 31)
//
//
// Definitions for Get SEL Info command
//
#define IPMI_STORAGE_GET_SEL_INFO 0x40
//
// Constants and Structure definitions for "Get SEL Info" command to follow here
//
typedef struct {
UINT8 CompletionCode;
UINT8 Version; // Version of SEL
UINT16 NoOfEntries; // No of Entries in the SEL
UINT16 FreeSpace; // Free space in Bytes
UINT32 RecentAddTimeStamp; // Most Recent Addition of Time Stamp
UINT32 RecentEraseTimeStamp; // Most Recent Erasure of Time Stamp
UINT8 OperationSupport; // Operation Support
} IPMI_GET_SEL_INFO_RESPONSE;
//
// Definitions for Get SEL Allocation Info command
//
#define IPMI_STORAGE_GET_SEL_ALLOCATION_INFO 0x41
//
// Constants and Structure definitions for "Get SEL Allocation Info" command to follow here
//
//
// Definitions for Reserve SEL command
//
#define IPMI_STORAGE_RESERVE_SEL 0x42
//
// Constants and Structure definitions for "Reserve SEL" command to follow here
//
//
// Definitions for Get SEL Entry command
//
#define IPMI_STORAGE_GET_SEL_ENTRY 0x43
//
// Constants and Structure definitions for "Get SEL Entry" command to follow here
//
typedef struct {
UINT8 ReserveId[2]; // Reservation ID, LS Byte First
UINT8 SelRecID[2]; // Sel Record ID, LS Byte First
UINT8 Offset; // Offset Into Record
UINT8 BytesToRead; // Bytes to be Read, 0xFF for entire record
} IPMI_GET_SEL_ENTRY_REQUEST;
//
// Definitions for Add SEL Entry command
//
#define IPMI_STORAGE_ADD_SEL_ENTRY 0x44
//
// Constants and Structure definitions for "Add SEL Entry" command to follow here
//
//
// Definitions for Partial Add SEL Entry command
//
#define IPMI_STORAGE_PARTIAL_ADD_SEL_ENTRY 0x45
//
// Constants and Structure definitions for "Partial Add SEL Entry" command to follow here
//
//
// Definitions for Delete SEL Entry command
//
#define IPMI_STORAGE_DELETE_SEL_ENTRY 0x46
//
// Constants and Structure definitions for "Delete SEL Entry" command to follow here
//
typedef struct {
UINT8 ReserveId[2]; // Reservation ID, LS byte first
UINT8 RecordToDelete[2]; // Record to Delete, LS Byte First
} IPMI_DELETE_SEL_REQUEST;
//
// Definitions for Clear SEL command
//
#define IPMI_STORAGE_CLEAR_SEL 0x47
//
// Constants and Structure definitions for "Clear SEL" command to follow here
//
typedef struct {
UINT8 Reserve[2]; // Reserve ID, LSB first
UINT8 AscC; // Ascii for 'C' (0x43)
UINT8 AscL; // Ascii for 'L' (0x4c)
UINT8 AscR; // Ascii for 'R' (0x52)
UINT8 Erase; // 0xAA, Initiate Erase, 0x00 Get Erase Status
} IPMI_CLEAR_SEL_REQUEST;
//
// Definitions for Get SEL Time command
//
#define IPMI_STORAGE_GET_SEL_TIME 0x48
//
// Constants and Structure definitions for "Get SEL Time" command to follow here
//
//
// Definitions for Set SEL Time command
//
#define IPMI_STORAGE_SET_SEL_TIME 0x49
//
// Constants and Structure definitions for "Set SEL Time" command to follow here
//
//
// Definitions for Get Auxillary Log Status command
//
#define IPMI_STORAGE_GET_AUXILLARY_LOG_STATUS 0x5A
//
// Constants and Structure definitions for "Get Auxillary Log Status" command to follow here
//
//
// Definitions for Set Auxillary Log Status command
//
#define IPMI_STORAGE_SET_AUXILLARY_LOG_STATUS 0x5B
//
// Constants and Structure definitions for "Set Auxillary Log Status" command to follow here
//
#define IPMI_COMPLETE_SEL_RECORD 0xFF
//
// Below is Definitions for SEL Record Formats (Chapter 32)
//
typedef struct {
UINT16 RecordId;
UINT8 RecordType;
UINT32 TimeStamp;
UINT16 GeneratorId;
UINT8 EvMRevision;
UINT8 SensorType;
UINT8 SensorNumber;
UINT8 EventDirType;
UINT8 OEMEvData1;
UINT8 OEMEvData2;
UINT8 OEMEvData3;
} IPMI_SEL_EVENT_RECORD_DATA;
#define IPMI_SEL_SYSTEM_RECORD 0x02
#define IPMI_EVM_REVISION 0x04
#define IPMI_BIOS_ID 0x18
#define IPMI_FORMAT_REV 0x00
#define IPMI_FORMAT_REV1 0x01
#define IPMI_SOFTWARE_ID 0x01
#define IPMI_PLATFORM_VAL_ID 0x01
#define IPMI_GENERATOR_ID(i,f) ((i << 1) | (f << 1) | IPMI_SOFTWARE_ID)
#define IPMI_SENSOR_TYPE_EVENT_CODE_DISCRETE 0x6F
#define IPMI_OEM_SPECIFIC_DATA 0x02
#define IPMI_SENSOR_SPECIFIC_DATA 0x03
#pragma pack()
#endif

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@ -0,0 +1,566 @@
/** @file
IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
This file contains all NetFn Transport commands, including:
IPM LAN Commands (Chapter 23)
IPMI Serial/Modem Commands (Chapter 25)
SOL Commands (Chapter 26)
Command Forwarding Commands (Chapter 35b)
See IPMI specification, Appendix G, Command Assignments
and Appendix H, Sub-function Assignments.
Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _IPMI_NET_FN_TRANSPORT_H_
#define _IPMI_NET_FN_TRANSPORT_H_
#pragma pack(1)
//
// Net function definition for Transport command
//
#define IPMI_NETFN_TRANSPORT 0x0C
//
// Below is Definitions for IPM LAN Commands (Chapter 23)
//
//
// Definitions for Set Lan Configuration Parameters command
//
#define IPMI_TRANSPORT_SET_LAN_CONFIG_PARAMETERS 0x01
//
// Constants and Structure definitions for "Set Lan Configuration Parameters" command to follow here
//
//
// LAN Management Structure
//
typedef enum {
IpmiLanReserved1,
IpmiLanReserved2,
IpmiLanAuthType,
IpmiLanIpAddress,
IpmiLanIpAddressSource,
IpmiLanMacAddress,
IpmiLanSubnetMask,
IpmiLanIpv4HeaderParam,
IpmiLanPrimaryRcmpPort,
IpmiLanSecondaryRcmpPort,
IpmiLanBmcGeneratedArpCtrl,
IpmiLanArpInterval,
IpmiLanDefaultGateway,
IpmiLanDefaultGatewayMac,
IpmiLanBackupGateway,
IpmiLanBackupGatewayMac,
IpmiLanCommunityString,
IpmiLanReserved3,
IpmiLanDestinationType,
IpmiLanDestinationAddress
} IPMI_LAN_OPTION_TYPE;
//
// IP Address Source
//
typedef enum {
IpmiUnspecified,
IpmiStaticAddrsss,
IpmiDynamicAddressBmcDhcp,
IpmiDynamicAddressBiosDhcp,
IpmiDynamicAddressBmcNonDhcp
} IPMI_IP_ADDRESS_SRC;
//
// Destination Type
//
typedef enum {
IpmiPetTrapDestination,
IpmiDirectedEventDestination,
IpmiReserved1,
IpmiReserved2,
IpmiReserved3,
IpmiReserved4,
IpmiReserved5,
IpmiOem1,
IpmiOem2
} IPMI_LAN_DEST_TYPE_DEST_TYPE;
typedef struct {
UINT8 NoAuth : 1;
UINT8 MD2Auth : 1;
UINT8 MD5Auth : 1;
UINT8 Reserved1 : 1;
UINT8 StraightPswd : 1;
UINT8 OemType : 1;
UINT8 Reserved2 : 2;
} IPMI_LAN_AUTH_TYPE;
typedef struct {
UINT8 IpAddress[4];
} IPMI_LAN_IP_ADDRESS;
typedef struct {
UINT8 AddressSrc : 4;
UINT8 Reserved : 4;
} IPMI_LAN_IP_ADDRESS_SRC;
typedef struct {
UINT8 MacAddress[6];
} IPMI_LAN_MAC_ADDRESS;
typedef struct {
UINT8 IpAddress[4];
} IPMI_LAN_SUBNET_MASK;
typedef struct {
UINT8 TimeToLive;
UINT8 IpFlag : 3;
UINT8 Reserved1 : 5;
UINT8 Precedence : 3;
UINT8 Reserved2 : 1;
UINT8 ServiceType : 4;
} IPMI_LAN_IPV4_HDR_PARAM;
typedef struct {
UINT8 RcmpPortMsb;
UINT8 RcmpPortLsb;
} IPMI_LAN_RCMP_PORT;
typedef struct {
UINT8 EnableBmcArpResponse : 1;
UINT8 EnableBmcGratuitousArp : 1;
UINT8 Reserved : 6;
} IPMI_LAN_BMC_GENERATED_ARP_CONTROL;
typedef struct {
UINT8 ArpInterval;
} IPMI_LAN_ARP_INTERVAL;
typedef struct {
UINT8 Data[18];
} IPMI_LAN_COMMUNITY_STRING;
typedef struct {
UINT8 DestinationSelector : 4;
UINT8 Reserved2 : 4;
UINT8 DestinationType : 3;
UINT8 Reserved1 : 4;
UINT8 AlertAcknowledged : 1;
} IPMI_LAN_DEST_TYPE;
typedef struct {
UINT8 DestinationSelector : 4;
UINT8 Reserved1 : 4;
UINT8 AlertingIpAddressSelector : 4;
UINT8 AddressFormat : 4;
UINT8 UseDefaultGateway : 1;
UINT8 Reserved2 : 7;
IPMI_LAN_IP_ADDRESS AlertingIpAddress;
IPMI_LAN_MAC_ADDRESS AlertingMacAddress;
} IPMI_LAN_DEST_ADDRESS;
typedef union {
IPMI_LAN_AUTH_TYPE IpmiLanAuthType;
IPMI_LAN_IP_ADDRESS IpmiLanIpAddress;
IPMI_LAN_IP_ADDRESS_SRC IpmiLanIpAddressSrc;
IPMI_LAN_MAC_ADDRESS IpmiLanMacAddress;
IPMI_LAN_SUBNET_MASK IpmiLanSubnetMask;
IPMI_LAN_IPV4_HDR_PARAM IpmiLanIpv4HdrParam;
IPMI_LAN_RCMP_PORT IpmiLanPrimaryRcmpPort;
IPMI_LAN_BMC_GENERATED_ARP_CONTROL IpmiLanArpControl;
IPMI_LAN_ARP_INTERVAL IpmiLanArpInterval;
IPMI_LAN_COMMUNITY_STRING IpmiLanCommunityString;
IPMI_LAN_DEST_TYPE IpmiLanDestType;
IPMI_LAN_DEST_ADDRESS IpmiLanDestAddress;
} IPMI_LAN_OPTIONS;
//
// Definitions for Get Lan Configuration Parameters command
//
#define IPMI_TRANSPORT_GET_LAN_CONFIG_PARAMETERS 0x02
//
// Constants and Structure definitions for "Get Lan Configuration Parameters" command to follow here
//
//
// Definitions for Suspend BMC ARPs command
//
#define IPMI_TRANSPORT_SUSPEND_BMC_ARPS 0x03
//
// Constants and Structure definitions for "Suspend BMC ARPs" command to follow here
//
//
// Definitions for Get IP-UDP-RMCP Statistics command
//
#define IPMI_TRANSPORT_GET_PACKET_STATISTICS 0x04
//
// Constants and Structure definitions for "Get IP-UDP-RMCP Statistics" command to follow here
//
//
// Below is Definitions for IPMI Serial/Modem Commands (Chapter 25)
//
//
// Definitions for Set Serial/Modem Configuration command
//
#define IPMI_TRANSPORT_SET_SERIAL_CONFIGURATION 0x10
//
// Constants and Structure definitions for "Set Serial/Modem Configuration" command to follow here
//
//
// EMP OPTION DATA
//
typedef struct {
UINT8 NoAuthentication : 1;
UINT8 MD2Authentication : 1;
UINT8 MD5Authentication : 1;
UINT8 Reserved1 : 1;
UINT8 StraightPassword : 1;
UINT8 OemProprietary : 1;
UINT8 Reservd2 : 2;
} IPMI_EMP_AUTH_TYPE;
typedef struct {
UINT8 EnableBasicMode : 1;
UINT8 EnablePPPMode : 1;
UINT8 EnableTerminalMode : 1;
UINT8 Reserved1 : 2;
UINT8 SnoopOsPPPNegotiation : 1;
UINT8 Reserved2 : 1;
UINT8 DirectConnect : 1;
} IPMI_EMP_CONNECTION_TYPE;
typedef struct {
UINT8 InactivityTimeout : 4;
UINT8 Reserved : 4;
} IPMI_EMP_INACTIVITY_TIMEOUT;
typedef struct {
UINT8 IpmiCallback : 1;
UINT8 CBCPCallback : 1;
UINT8 Reserved1 : 6;
UINT8 CbcpEnableNoCallback : 1;
UINT8 CbcpEnablePreSpecifiedNumber : 1;
UINT8 CbcpEnableUserSpecifiedNumber : 1;
UINT8 CbcpEnableCallbackFromList : 1;
UINT8 Reserved : 4;
UINT8 CallbackDestination1;
UINT8 CallbackDestination2;
UINT8 CallbackDestination3;
} IPMI_EMP_CHANNEL_CALLBACK_CONTROL;
typedef struct {
UINT8 CloseSessionOnDCDLoss : 1;
UINT8 EnableSessionInactivityTimeout : 1;
UINT8 Reserved : 6;
} IPMI_EMP_SESSION_TERMINATION;
typedef struct {
UINT8 Reserved1 : 5;
UINT8 EnableDtrHangup : 1;
UINT8 FlowControl : 2;
UINT8 BitRate : 4;
UINT8 Reserved2 : 4;
UINT8 SaveSetting : 1;
UINT8 SetComPort : 1;
UINT8 Reserved3 : 6;
} IPMI_EMP_MESSAGING_COM_SETTING;
typedef struct {
UINT8 RingDurationInterval : 6;
UINT8 Reserved1 : 2;
UINT8 RingDeadTime : 4;
UINT8 Reserved : 4;
} IPMI_EMP_MODEM_RING_TIME;
typedef struct {
UINT8 Reserved;
UINT8 InitString[48];
} IPMI_EMP_MODEM_INIT_STRING;
typedef struct {
UINT8 EscapeSequence[5];
} IPMI_EMP_MODEM_ESC_SEQUENCE;
typedef struct {
UINT8 HangupSequence[8];
} IPMI_EMP_MODEM_HANGUP_SEQUENCE;
typedef struct {
UINT8 ModelDialCommend[8];
} IPMI_MODEM_DIALUP_COMMAND;
typedef struct {
UINT8 PageBlackoutInterval;
} IPMI_PAGE_BLACKOUT_INTERVAL;
typedef struct {
UINT8 CommunityString[18];
} IPMI_EMP_COMMUNITY_STRING;
typedef struct {
UINT8 Reserved5 : 4;
UINT8 DialStringSelector : 4;
} IPMI_DIAL_PAGE_DESTINATION;
typedef struct {
UINT8 TapAccountSelector : 4;
UINT8 Reserved : 4;
} IPMI_TAP_PAGE_DESTINATION;
typedef struct {
UINT8 PPPAccountSetSelector;
UINT8 DialStringSelector;
} IPMI_PPP_ALERT_DESTINATION;
typedef union {
IPMI_DIAL_PAGE_DESTINATION DialPageDestination;
IPMI_TAP_PAGE_DESTINATION TapPageDestination;
IPMI_PPP_ALERT_DESTINATION PppAlertDestination;
} IPMI_DEST_TYPE_SPECIFIC;
typedef struct {
UINT8 DestinationSelector : 4;
UINT8 Reserved1 : 4;
UINT8 DestinationType : 4;
UINT8 Reserved2 : 3;
UINT8 AlertAckRequired : 1;
UINT8 AlertAckTimeoutSeconds;
UINT8 NumRetriesCall : 3;
UINT8 Reserved3 : 1;
UINT8 NumRetryAlert : 3;
UINT8 Reserved4 : 1;
IPMI_DEST_TYPE_SPECIFIC DestinationTypeSpecific;
} IPMI_EMP_DESTINATION_INFO;
typedef struct {
UINT8 DestinationSelector : 4;
UINT8 Reserved1 : 4;
UINT8 Parity : 3;
UINT8 CharacterSize : 1;
UINT8 StopBit : 1;
UINT8 DtrHangup : 1;
UINT8 FlowControl : 2;
UINT8 BitRate : 4;
UINT8 Reserved2 : 4;
UINT8 SaveSetting : 1;
UINT8 SetComPort : 1;
UINT8 Reserved3 : 6;
} IPMI_EMP_DESTINATION_COM_SETTING;
typedef struct {
UINT8 DialStringSelector : 4;
UINT8 Reserved1 : 4;
UINT8 Reserved2;
UINT8 DialString[48];
} IPMI_DESTINATION_DIAL_STRING;
typedef union {
UINT32 IpAddressLong;
UINT8 IpAddress[4];
} IPMI_PPP_IP_ADDRESS;
typedef struct {
UINT8 IpAddressSelector : 4;
UINT8 Reserved1 : 4;
IPMI_PPP_IP_ADDRESS PppIpAddress;
} IPMI_DESTINATION_IP_ADDRESS;
typedef struct {
UINT8 TapSelector;
UINT8 TapServiceSelector : 4;
UINT8 TapDialStringSelector : 4;
} IPMI_DESTINATION_TAP_ACCOUNT;
typedef struct {
UINT8 TapSelector;
UINT8 PagerIdString[16];
} IPMI_TAP_PAGER_ID_STRING;
typedef union {
UINT8 OptionData;
IPMI_EMP_AUTH_TYPE EmpAuthType;
IPMI_EMP_CONNECTION_TYPE EmpConnectionType;
IPMI_EMP_INACTIVITY_TIMEOUT EmpInactivityTimeout;
IPMI_EMP_CHANNEL_CALLBACK_CONTROL EmpCallbackControl;
IPMI_EMP_SESSION_TERMINATION EmpSessionTermination;
IPMI_EMP_MESSAGING_COM_SETTING EmpMessagingComSetting;
IPMI_EMP_MODEM_RING_TIME EmpModemRingTime;
IPMI_EMP_MODEM_INIT_STRING EmpModemInitString;
IPMI_EMP_MODEM_ESC_SEQUENCE EmpModemEscSequence;
IPMI_EMP_MODEM_HANGUP_SEQUENCE EmpModemHangupSequence;
IPMI_MODEM_DIALUP_COMMAND EmpModemDialupCommand;
IPMI_PAGE_BLACKOUT_INTERVAL EmpPageBlackoutInterval;
IPMI_EMP_COMMUNITY_STRING EmpCommunityString;
IPMI_EMP_DESTINATION_INFO EmpDestinationInfo;
IPMI_EMP_DESTINATION_COM_SETTING EmpDestinationComSetting;
UINT8 CallRetryBusySignalInterval;
IPMI_DESTINATION_DIAL_STRING DestinationDialString;
IPMI_DESTINATION_IP_ADDRESS DestinationIpAddress;
IPMI_DESTINATION_TAP_ACCOUNT DestinationTapAccount;
IPMI_TAP_PAGER_ID_STRING TapPagerIdString;
} IPMI_EMP_OPTIONS;
//
// Definitions for Get Serial/Modem Configuration command
//
#define IPMI_TRANSPORT_GET_SERIAL_CONFIGURATION 0x11
//
// Constants and Structure definitions for "Get Serial/Modem Configuration" command to follow here
//
//
// Definitions for Set Serial/Modem Mux command
//
#define IPMI_TRANSPORT_SET_SERIAL_MUX 0x12
//
// Constants and Structure definitions for "Set Serial/Modem Mux" command to follow here
//
typedef struct {
UINT8 ChannelNo : 4;
UINT8 Reserved1 : 4;
UINT8 MuxSetting : 4;
UINT8 Reserved2 : 4;
} IPMI_SET_SERIAL_MODEM_MUX_COMMAND_REQUEST;
typedef struct {
UINT8 MuxSetToBmc : 1;
UINT8 CommandStatus : 1;
UINT8 MessagingSessionActive : 1;
UINT8 AlertInProgress : 1;
UINT8 Reserved2 : 2;
UINT8 MuxToBmcAllowed : 1;
UINT8 MuxToSystemBlocked : 1;
} IPMI_SET_SERIAL_MODEM_MUX_COMMAND_RESPONSE;
//
// Definitions for Get TAP Response Code command
//
#define IPMI_TRANSPORT_GET_TAP_RESPONSE_CODE 0x13
//
// Constants and Structure definitions for "Get TAP Response Code" command to follow here
//
//
// Definitions for Set PPP UDP Proxy Transmit Data command
//
#define IPMI_TRANSPORT_SET_PPP_UDP_PROXY_TXDATA 0x14
//
// Constants and Structure definitions for "Set PPP UDP Proxy Transmit Data" command to follow here
//
//
// Definitions for Get PPP UDP Proxy Transmit Data command
//
#define IPMI_TRANSPORT_GET_PPP_UDP_PROXY_TXDATA 0x15
//
// Constants and Structure definitions for "Get PPP UDP Proxy Transmit Data" command to follow here
//
//
// Definitions for Send PPP UDP Proxy Packet command
//
#define IPMI_TRANSPORT_SEND_PPP_UDP_PROXY_PACKET 0x16
//
// Constants and Structure definitions for "Send PPP UDP Proxy Packet" command to follow here
//
//
// Definitions for Get PPP UDP Proxy Receive Data command
//
#define IPMI_TRANSPORT_GET_PPP_UDP_PROXY_RX 0x17
//
// Constants and Structure definitions for "Get PPP UDP Proxy Receive Data" command to follow here
//
//
// Definitions for Serial/Modem connection active command
//
#define IPMI_TRANSPORT_SERIAL_CONNECTION_ACTIVE 0x18
//
// Constants and Structure definitions for "Serial/Modem connection active" command to follow here
//
//
// Definitions for Callback command
//
#define IPMI_TRANSPORT_CALLBACK 0x19
//
// Constants and Structure definitions for "Callback" command to follow here
//
//
// Definitions for Set user Callback Options command
//
#define IPMI_TRANSPORT_SET_USER_CALLBACK_OPTIONS 0x1A
//
// Constants and Structure definitions for "Set user Callback Options" command to follow here
//
//
// Definitions for Get user Callback Options command
//
#define IPMI_TRANSPORT_GET_USER_CALLBACK_OPTIONS 0x1B
//
// Constants and Structure definitions for "Get user Callback Options" command to follow here
//
//
// Below is Definitions for SOL Commands (Chapter 26)
//
//
// Definitions for SOL activating command
//
#define IPMI_TRANSPORT_SOL_ACTIVATING 0x20
//
// Constants and Structure definitions for "SOL activating" command to follow here
//
//
// Definitions for Set SOL Configuration Parameters command
//
#define IPMI_TRANSPORT_SET_SOL_CONFIG_PARAM 0x21
//
// Constants and Structure definitions for "Set SOL Configuration Parameters" command to follow here
//
//
// Definitions for Get SOL Configuration Parameters command
//
#define IPMI_TRANSPORT_GET_SOL_CONFIG_PARAM 0x22
//
// Constants and Structure definitions for "Get SOL Configuration Parameters" command to follow here
//
#pragma pack()
#endif

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/** @file
Defives data structures per MultiProcessor Specification Ver 1.4.
The MultiProcessor Specification defines an enhancement to the standard
to which PC manufacturers design DOS-compatible systems.
Copyright (c) 2007 - 2011, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _LEGACY_BIOS_MPTABLE_H_
#define _LEGACY_BIOS_MPTABLE_H_
#define EFI_LEGACY_MP_TABLE_REV_1_4 0x04
//
// Define MP table structures. All are packed.
//
#pragma pack(1)
#define EFI_LEGACY_MP_TABLE_FLOATING_POINTER_SIGNATURE SIGNATURE_32 ('_', 'M', 'P', '_')
typedef struct {
UINT32 Reserved1 : 6;
UINT32 MutipleClk : 1;
UINT32 Imcr : 1;
UINT32 Reserved2 : 24;
} FEATUREBYTE2_5;
typedef struct {
UINT32 Signature;
UINT32 PhysicalAddress;
UINT8 Length;
UINT8 SpecRev;
UINT8 Checksum;
UINT8 FeatureByte1;
FEATUREBYTE2_5 FeatureByte2_5;
} EFI_LEGACY_MP_TABLE_FLOATING_POINTER;
#define EFI_LEGACY_MP_TABLE_HEADER_SIGNATURE SIGNATURE_32 ('P', 'C', 'M', 'P')
typedef struct {
UINT32 Signature;
UINT16 BaseTableLength;
UINT8 SpecRev;
UINT8 Checksum;
CHAR8 OemId[8];
CHAR8 OemProductId[12];
UINT32 OemTablePointer;
UINT16 OemTableSize;
UINT16 EntryCount;
UINT32 LocalApicAddress;
UINT16 ExtendedTableLength;
UINT8 ExtendedChecksum;
UINT8 Reserved;
} EFI_LEGACY_MP_TABLE_HEADER;
typedef struct {
UINT8 EntryType;
} EFI_LEGACY_MP_TABLE_ENTRY_TYPE;
//
// Entry Type 0: Processor.
//
#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_PROCESSOR 0x00
typedef struct {
UINT8 Enabled : 1;
UINT8 Bsp : 1;
UINT8 Reserved : 6;
} EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR_FLAGS;
typedef struct {
UINT32 Stepping : 4;
UINT32 Model : 4;
UINT32 Family : 4;
UINT32 Reserved : 20;
} EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR_SIGNATURE;
typedef struct {
UINT32 Fpu : 1;
UINT32 Reserved1 : 6;
UINT32 Mce : 1;
UINT32 Cx8 : 1;
UINT32 Apic : 1;
UINT32 Reserved2 : 22;
} EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR_FEATURES;
typedef struct {
UINT8 EntryType;
UINT8 Id;
UINT8 Ver;
EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR_FLAGS Flags;
EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR_SIGNATURE Signature;
EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR_FEATURES Features;
UINT32 Reserved1;
UINT32 Reserved2;
} EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR;
//
// Entry Type 1: Bus.
//
#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_BUS 0x01
typedef struct {
UINT8 EntryType;
UINT8 Id;
CHAR8 TypeString[6];
} EFI_LEGACY_MP_TABLE_ENTRY_BUS;
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_CBUS "CBUS " // Corollary CBus
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_CBUSII "CBUSII" // Corollary CBUS II
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_EISA "EISA " // Extended ISA
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_FUTURE "FUTURE" // IEEE FutureBus
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_INTERN "INTERN" // Internal bus
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_ISA "ISA " // Industry Standard Architecture
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MBI "MBI " // Multibus I
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MBII "MBII " // Multibus II
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MCA "MCA " // Micro Channel Architecture
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MPI "MPI " // MPI
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MPSA "MPSA " // MPSA
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_NUBUS "NUBUS " // Apple Macintosh NuBus
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_PCI "PCI " // Peripheral Component Interconnect
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_PCMCIA "PCMCIA" // PC Memory Card International Assoc.
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_TC "TC " // DEC TurboChannel
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_VL "VL " // VESA Local Bus
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_VME "VME " // VMEbus
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_XPRESS "XPRESS" // Express System Bus
//
// Entry Type 2: I/O APIC.
//
#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_IOAPIC 0x02
typedef struct {
UINT8 Enabled : 1;
UINT8 Reserved : 7;
} EFI_LEGACY_MP_TABLE_ENTRY_IOAPIC_FLAGS;
typedef struct {
UINT8 EntryType;
UINT8 Id;
UINT8 Ver;
EFI_LEGACY_MP_TABLE_ENTRY_IOAPIC_FLAGS Flags;
UINT32 Address;
} EFI_LEGACY_MP_TABLE_ENTRY_IOAPIC;
//
// Entry Type 3: I/O Interrupt Assignment.
//
#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_IO_INT 0x03
typedef struct {
UINT16 Polarity : 2;
UINT16 Trigger : 2;
UINT16 Reserved : 12;
} EFI_LEGACY_MP_TABLE_ENTRY_INT_FLAGS;
typedef struct {
UINT8 IntNo : 2;
UINT8 Dev : 5;
UINT8 Reserved : 1;
} EFI_LEGACY_MP_TABLE_ENTRY_INT_FIELDS;
typedef union {
EFI_LEGACY_MP_TABLE_ENTRY_INT_FIELDS fields;
UINT8 byte;
} EFI_LEGACY_MP_TABLE_ENTRY_INT_SOURCE_BUS_IRQ;
typedef struct {
UINT8 EntryType;
UINT8 IntType;
EFI_LEGACY_MP_TABLE_ENTRY_INT_FLAGS Flags;
UINT8 SourceBusId;
EFI_LEGACY_MP_TABLE_ENTRY_INT_SOURCE_BUS_IRQ SourceBusIrq;
UINT8 DestApicId;
UINT8 DestApicIntIn;
} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT;
typedef enum {
EfiLegacyMpTableEntryIoIntTypeInt = 0,
EfiLegacyMpTableEntryIoIntTypeNmi = 1,
EfiLegacyMpTableEntryIoIntTypeSmi = 2,
EfiLegacyMpTableEntryIoIntTypeExtInt= 3,
} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_TYPE;
typedef enum {
EfiLegacyMpTableEntryIoIntFlagsPolaritySpec = 0x0,
EfiLegacyMpTableEntryIoIntFlagsPolarityActiveHigh = 0x1,
EfiLegacyMpTableEntryIoIntFlagsPolarityReserved = 0x2,
EfiLegacyMpTableEntryIoIntFlagsPolarityActiveLow = 0x3,
} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_FLAGS_POLARITY;
typedef enum {
EfiLegacyMpTableEntryIoIntFlagsTriggerSpec = 0x0,
EfiLegacyMpTableEntryIoIntFlagsTriggerEdge = 0x1,
EfiLegacyMpTableEntryIoIntFlagsTriggerReserved = 0x2,
EfiLegacyMpTableEntryIoIntFlagsTriggerLevel = 0x3,
} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_FLAGS_TRIGGER;
//
// Entry Type 4: Local Interrupt Assignment.
//
#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_LOCAL_INT 0x04
typedef struct {
UINT8 EntryType;
UINT8 IntType;
EFI_LEGACY_MP_TABLE_ENTRY_INT_FLAGS Flags;
UINT8 SourceBusId;
EFI_LEGACY_MP_TABLE_ENTRY_INT_SOURCE_BUS_IRQ SourceBusIrq;
UINT8 DestApicId;
UINT8 DestApicIntIn;
} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT;
typedef enum {
EfiLegacyMpTableEntryLocalIntTypeInt = 0,
EfiLegacyMpTableEntryLocalIntTypeNmi = 1,
EfiLegacyMpTableEntryLocalIntTypeSmi = 2,
EfiLegacyMpTableEntryLocalIntTypeExtInt = 3,
} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_TYPE;
typedef enum {
EfiLegacyMpTableEntryLocalIntFlagsPolaritySpec = 0x0,
EfiLegacyMpTableEntryLocalIntFlagsPolarityActiveHigh= 0x1,
EfiLegacyMpTableEntryLocalIntFlagsPolarityReserved = 0x2,
EfiLegacyMpTableEntryLocalIntFlagsPolarityActiveLow = 0x3,
} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_FLAGS_POLARITY;
typedef enum {
EfiLegacyMpTableEntryLocalIntFlagsTriggerSpec = 0x0,
EfiLegacyMpTableEntryLocalIntFlagsTriggerEdge = 0x1,
EfiLegacyMpTableEntryLocalIntFlagsTriggerReserved = 0x2,
EfiLegacyMpTableEntryLocalIntFlagsTriggerLevel = 0x3,
} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_FLAGS_TRIGGER;
//
// Entry Type 128: System Address Space Mapping.
//
#define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_SYS_ADDR_SPACE_MAPPING 0x80
typedef struct {
UINT8 EntryType;
UINT8 Length;
UINT8 BusId;
UINT8 AddressType;
UINT64 AddressBase;
UINT64 AddressLength;
} EFI_LEGACY_MP_TABLE_ENTRY_EXT_SYS_ADDR_SPACE_MAPPING;
typedef enum {
EfiLegacyMpTableEntryExtSysAddrSpaceMappingIo = 0,
EfiLegacyMpTableEntryExtSysAddrSpaceMappingMemory = 1,
EfiLegacyMpTableEntryExtSysAddrSpaceMappingPrefetch = 2,
} EFI_LEGACY_MP_TABLE_ENTRY_EXT_SYS_ADDR_SPACE_MAPPING_TYPE;
//
// Entry Type 129: Bus Hierarchy.
//
#define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_BUS_HIERARCHY 0x81
typedef struct {
UINT8 SubtractiveDecode : 1;
UINT8 Reserved : 7;
} EFI_LEGACY_MP_TABLE_ENTRY_EXT_BUS_HIERARCHY_BUSINFO;
typedef struct {
UINT8 EntryType;
UINT8 Length;
UINT8 BusId;
EFI_LEGACY_MP_TABLE_ENTRY_EXT_BUS_HIERARCHY_BUSINFO BusInfo;
UINT8 ParentBus;
UINT8 Reserved1;
UINT8 Reserved2;
UINT8 Reserved3;
} EFI_LEGACY_MP_TABLE_ENTRY_EXT_BUS_HIERARCHY;
//
// Entry Type 130: Compatibility Bus Address Space Modifier.
//
#define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_COMPAT_BUS_ADDR_SPACE_MODIFIER 0x82
typedef struct {
UINT8 RangeMode : 1;
UINT8 Reserved : 7;
} EFI_LEGACY_MP_TABLE_ENTRY_EXT_COMPAT_BUS_ADDR_SPACE_MODIFIER_ADDR_MODE;
typedef struct {
UINT8 EntryType;
UINT8 Length;
UINT8 BusId;
EFI_LEGACY_MP_TABLE_ENTRY_EXT_COMPAT_BUS_ADDR_SPACE_MODIFIER_ADDR_MODE AddrMode;
UINT32 PredefinedRangeList;
} EFI_LEGACY_MP_TABLE_ENTRY_EXT_COMPAT_BUS_ADDR_SPACE_MODIFIER;
#pragma pack()
#endif

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/** @file
ACPI Low Power Idle Table (LPIT) definitions
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
- ACPI Low Power Idle Table (LPIT) Revision 001, dated July 2014
http://www.uefi.org/sites/default/files/resources/ACPI_Low_Power_Idle_Table.pdf
@par Glossary:
- GAS - Generic Address Structure
- LPI - Low Power Idle
**/
#ifndef _LOW_POWER_IDLE_TABLE_H_
#define _LOW_POWER_IDLE_TABLE_H_
#include <IndustryStandard/Acpi.h>
#pragma pack(1)
///
/// LPI Structure Types
///
#define ACPI_LPI_STRUCTURE_TYPE_NATIVE_CSTATE 0x00
///
/// Low Power Idle (LPI) State Flags
///
typedef union {
struct {
UINT32 Disabled : 1; ///< If set, LPI state is not used
/**
If set, Residency counter is not available for this LPI state and
Residency Counter Frequency is invalid
**/
UINT32 CounterUnavailable : 1;
UINT32 Reserved : 30; ///< Reserved for future use. Must be zero
} Bits;
UINT32 Data32;
} ACPI_LPI_STATE_FLAGS;
///
/// Low Power Idle (LPI) structure with Native C-state instruction entry trigger descriptor
///
typedef struct {
UINT32 Type; ///< LPI State descriptor Type 0
UINT32 Length; ///< Length of LPI state Descriptor Structure
///
/// Unique LPI state identifier: zero based, monotonically increasing identifier
///
UINT16 UniqueId;
UINT8 Reserved[2]; ///< Must be Zero
ACPI_LPI_STATE_FLAGS Flags; ///< LPI state flags
/**
The LPI entry trigger, matching an existing _CST.Register object, represented as a
Generic Address Structure. All processors must request this state or deeper to trigger.
**/
EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE EntryTrigger;
UINT32 Residency; ///< Minimum residency or break-even in uSec
UINT32 Latency; ///< Worst case exit latency in uSec
/**
[optional] Residency counter, represented as a Generic Address Structure.
If not present, Flags[1] bit should be set.
**/
EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ResidencyCounter;
/**
[optional] Residency counter frequency in cycles per second. Value 0 indicates that
counter runs at TSC frequency. Valid only if Residency Counter is present.
**/
UINT64 ResidencyCounterFrequency;
} ACPI_LPI_NATIVE_CSTATE_DESCRIPTOR;
#pragma pack()
#endif

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/** @file
Legacy Master Boot Record Format Definition.
Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _MBR_H_
#define _MBR_H_
#define MBR_SIGNATURE 0xaa55
#define EXTENDED_DOS_PARTITION 0x05
#define EXTENDED_WINDOWS_PARTITION 0x0F
#define MAX_MBR_PARTITIONS 4
#define PMBR_GPT_PARTITION 0xEE
#define EFI_PARTITION 0xEF
#define MBR_SIZE 512
#pragma pack(1)
///
/// MBR Partition Entry
///
typedef struct {
UINT8 BootIndicator;
UINT8 StartHead;
UINT8 StartSector;
UINT8 StartTrack;
UINT8 OSIndicator;
UINT8 EndHead;
UINT8 EndSector;
UINT8 EndTrack;
UINT8 StartingLBA[4];
UINT8 SizeInLBA[4];
} MBR_PARTITION_RECORD;
///
/// MBR Partition Table
///
typedef struct {
UINT8 BootStrapCode[440];
UINT8 UniqueMbrSignature[4];
UINT8 Unknown[2];
MBR_PARTITION_RECORD Partition[MAX_MBR_PARTITIONS];
UINT16 Signature;
} MASTER_BOOT_RECORD;
#pragma pack()
#endif

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/** @file
ACPI memory mapped configuration space access table definition, defined at
in the PCI Firmware Specification, version 3.0.
Specification is available at http://www.pcisig.com.
Copyright (c) 2007 - 2008, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_H_
#define _MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_H_
//
// Ensure proper structure formats
//
#pragma pack(1)
///
/// Memory Mapped Configuration Space Access Table (MCFG)
/// This table is a basic description table header followed by
/// a number of base address allocation structures.
///
typedef struct {
UINT64 BaseAddress;
UINT16 PciSegmentGroupNumber;
UINT8 StartBusNumber;
UINT8 EndBusNumber;
UINT32 Reserved;
} EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE;
///
/// MCFG Table header definition. The rest of the table
/// must be defined in a platform specific manner.
///
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
UINT64 Reserved;
} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER;
///
/// MCFG Revision (defined in spec)
///
#define EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION 0x01
#pragma pack()
#endif

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/** @file
Support for Microsoft Secure MOR implementation, defined at
Microsoft Secure MOR implementation.
https://msdn.microsoft.com/en-us/library/windows/hardware/mt270973(v=vs.85).aspx
Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __MEMORY_OVERWRITE_REQUEST_CONTROL_LOCK_H__
#define __MEMORY_OVERWRITE_REQUEST_CONTROL_LOCK_H__
#define MEMORY_OVERWRITE_REQUEST_CONTROL_LOCK_GUID \
{ \
0xBB983CCF, 0x151D, 0x40E1, {0xA0, 0x7B, 0x4A, 0x17, 0xBE, 0x16, 0x82, 0x92} \
}
#define MEMORY_OVERWRITE_REQUEST_CONTROL_LOCK_NAME L"MemoryOverwriteRequestControlLock"
//
// VendorGuid: {BB983CCF-151D-40E1-A07B-4A17BE168292}
// Name: MemoryOverwriteRequestControlLock
// Attributes: NV+BS+RT
// GetVariable value in Data parameter: 0x0 (unlocked); 0x1 (locked without key); 0x2 (locked with key)
// SetVariable value in Data parameter: 0x0 (unlocked); 0x1 (locked);
// Revision 2 additionally accepts an 8-byte value that represents a shared secret key.
//
//
// Note: Setting MemoryOverwriteRequestControlLock does not commit to flash (just changes the internal lock state).
// Getting the variable returns the internal state and never exposes the key.
//
extern EFI_GUID gEfiMemoryOverwriteRequestControlLockGuid;
#endif

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/** @file
Definitions based on NVMe spec. version 1.1.
(C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
NVMe Specification 1.1
**/
#ifndef __NVM_E_H__
#define __NVM_E_H__
#pragma pack(1)
//
// controller register offsets
//
#define NVME_CAP_OFFSET 0x0000 // Controller Capabilities
#define NVME_VER_OFFSET 0x0008 // Version
#define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set
#define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear
#define NVME_CC_OFFSET 0x0014 // Controller Configuration
#define NVME_CSTS_OFFSET 0x001c // Controller Status
#define NVME_NSSR_OFFSET 0x0020 // NVM Subsystem Reset
#define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes
#define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base Address
#define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base Address
#define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 (admin) Tail Doorbell
#define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 (admin) Head Doorbell
//
// These register offsets are defined as 0x1000 + (N * (4 << CAP.DSTRD))
// Get the doorbell stride bit shift value from the controller capabilities.
//
#define NVME_SQTDBL_OFFSET(QID, DSTRD) 0x1000 + ((2 * (QID)) * (4 << (DSTRD))) // Submission Queue y (NVM) Tail Doorbell
#define NVME_CQHDBL_OFFSET(QID, DSTRD) 0x1000 + (((2 * (QID)) + 1) * (4 << (DSTRD))) // Completion Queue y (NVM) Head Doorbell
#pragma pack(1)
//
// 3.1.1 Offset 00h: CAP - Controller Capabilities
//
typedef struct {
UINT16 Mqes; // Maximum Queue Entries Supported
UINT8 Cqr:1; // Contiguous Queues Required
UINT8 Ams:2; // Arbitration Mechanism Supported
UINT8 Rsvd1:5;
UINT8 To; // Timeout
UINT16 Dstrd:4;
UINT16 Nssrs:1; // NVM Subsystem Reset Supported NSSRS
UINT16 Css:4; // Command Sets Supported - Bit 37
UINT16 Rsvd3:7;
UINT8 Mpsmin:4;
UINT8 Mpsmax:4;
UINT8 Rsvd4;
} NVME_CAP;
//
// 3.1.2 Offset 08h: VS - Version
//
typedef struct {
UINT16 Mnr; // Minor version number
UINT16 Mjr; // Major version number
} NVME_VER;
//
// 3.1.5 Offset 14h: CC - Controller Configuration
//
typedef struct {
UINT16 En:1; // Enable
UINT16 Rsvd1:3;
UINT16 Css:3; // I/O Command Set Selected
UINT16 Mps:4; // Memory Page Size
UINT16 Ams:3; // Arbitration Mechanism Selected
UINT16 Shn:2; // Shutdown Notification
UINT8 Iosqes:4; // I/O Submission Queue Entry Size
UINT8 Iocqes:4; // I/O Completion Queue Entry Size
UINT8 Rsvd2;
} NVME_CC;
//
// 3.1.6 Offset 1Ch: CSTS - Controller Status
//
typedef struct {
UINT32 Rdy:1; // Ready
UINT32 Cfs:1; // Controller Fatal Status
UINT32 Shst:2; // Shutdown Status
UINT32 Nssro:1; // NVM Subsystem Reset Occurred
UINT32 Rsvd1:27;
} NVME_CSTS;
//
// 3.1.8 Offset 24h: AQA - Admin Queue Attributes
//
typedef struct {
UINT16 Asqs:12; // Submission Queue Size
UINT16 Rsvd1:4;
UINT16 Acqs:12; // Completion Queue Size
UINT16 Rsvd2:4;
} NVME_AQA;
//
// 3.1.9 Offset 28h: ASQ - Admin Submission Queue Base Address
//
#define NVME_ASQ UINT64
//
// 3.1.10 Offset 30h: ACQ - Admin Completion Queue Base Address
//
#define NVME_ACQ UINT64
//
// 3.1.11 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell
//
typedef struct {
UINT16 Sqt;
UINT16 Rsvd1;
} NVME_SQTDBL;
//
// 3.1.12 Offset (1000h + ((2y + 1) * (4 << CAP.DSTRD))): CQyHDBL - Completion Queue y Head Doorbell
//
typedef struct {
UINT16 Cqh;
UINT16 Rsvd1;
} NVME_CQHDBL;
//
// NVM command set structures
//
// Read Command
//
typedef struct {
//
// CDW 10, 11
//
UINT64 Slba; /* Starting Sector Address */
//
// CDW 12
//
UINT16 Nlb; /* Number of Sectors */
UINT16 Rsvd1:10;
UINT16 Prinfo:4; /* Protection Info Check */
UINT16 Fua:1; /* Force Unit Access */
UINT16 Lr:1; /* Limited Retry */
//
// CDW 13
//
UINT32 Af:4; /* Access Frequency */
UINT32 Al:2; /* Access Latency */
UINT32 Sr:1; /* Sequential Request */
UINT32 In:1; /* Incompressible */
UINT32 Rsvd2:24;
//
// CDW 14
//
UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */
//
// CDW 15
//
UINT16 Elbat; /* Expected Logical Block Application Tag */
UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */
} NVME_READ;
//
// Write Command
//
typedef struct {
//
// CDW 10, 11
//
UINT64 Slba; /* Starting Sector Address */
//
// CDW 12
//
UINT16 Nlb; /* Number of Sectors */
UINT16 Rsvd1:10;
UINT16 Prinfo:4; /* Protection Info Check */
UINT16 Fua:1; /* Force Unit Access */
UINT16 Lr:1; /* Limited Retry */
//
// CDW 13
//
UINT32 Af:4; /* Access Frequency */
UINT32 Al:2; /* Access Latency */
UINT32 Sr:1; /* Sequential Request */
UINT32 In:1; /* Incompressible */
UINT32 Rsvd2:24;
//
// CDW 14
//
UINT32 Ilbrt; /* Initial Logical Block Reference Tag */
//
// CDW 15
//
UINT16 Lbat; /* Logical Block Application Tag */
UINT16 Lbatm; /* Logical Block Application Tag Mask */
} NVME_WRITE;
//
// Flush
//
typedef struct {
//
// CDW 10
//
UINT32 Flush; /* Flush */
} NVME_FLUSH;
//
// Write Uncorrectable command
//
typedef struct {
//
// CDW 10, 11
//
UINT64 Slba; /* Starting LBA */
//
// CDW 12
//
UINT32 Nlb:16; /* Number of Logical Blocks */
UINT32 Rsvd1:16;
} NVME_WRITE_UNCORRECTABLE;
//
// Write Zeroes command
//
typedef struct {
//
// CDW 10, 11
//
UINT64 Slba; /* Starting LBA */
//
// CDW 12
//
UINT16 Nlb; /* Number of Logical Blocks */
UINT16 Rsvd1:10;
UINT16 Prinfo:4; /* Protection Info Check */
UINT16 Fua:1; /* Force Unit Access */
UINT16 Lr:1; /* Limited Retry */
//
// CDW 13
//
UINT32 Rsvd2;
//
// CDW 14
//
UINT32 Ilbrt; /* Initial Logical Block Reference Tag */
//
// CDW 15
//
UINT16 Lbat; /* Logical Block Application Tag */
UINT16 Lbatm; /* Logical Block Application Tag Mask */
} NVME_WRITE_ZEROES;
//
// Compare command
//
typedef struct {
//
// CDW 10, 11
//
UINT64 Slba; /* Starting LBA */
//
// CDW 12
//
UINT16 Nlb; /* Number of Logical Blocks */
UINT16 Rsvd1:10;
UINT16 Prinfo:4; /* Protection Info Check */
UINT16 Fua:1; /* Force Unit Access */
UINT16 Lr:1; /* Limited Retry */
//
// CDW 13
//
UINT32 Rsvd2;
//
// CDW 14
//
UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */
//
// CDW 15
//
UINT16 Elbat; /* Expected Logical Block Application Tag */
UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */
} NVME_COMPARE;
typedef union {
NVME_READ Read;
NVME_WRITE Write;
NVME_FLUSH Flush;
NVME_WRITE_UNCORRECTABLE WriteUncorrectable;
NVME_WRITE_ZEROES WriteZeros;
NVME_COMPARE Compare;
} NVME_CMD;
typedef struct {
UINT16 Mp; /* Maximum Power */
UINT8 Rsvd1; /* Reserved as of Nvm Express 1.1 Spec */
UINT8 Mps:1; /* Max Power Scale */
UINT8 Nops:1; /* Non-Operational State */
UINT8 Rsvd2:6; /* Reserved as of Nvm Express 1.1 Spec */
UINT32 Enlat; /* Entry Latency */
UINT32 Exlat; /* Exit Latency */
UINT8 Rrt:5; /* Relative Read Throughput */
UINT8 Rsvd3:3; /* Reserved as of Nvm Express 1.1 Spec */
UINT8 Rrl:5; /* Relative Read Leatency */
UINT8 Rsvd4:3; /* Reserved as of Nvm Express 1.1 Spec */
UINT8 Rwt:5; /* Relative Write Throughput */
UINT8 Rsvd5:3; /* Reserved as of Nvm Express 1.1 Spec */
UINT8 Rwl:5; /* Relative Write Leatency */
UINT8 Rsvd6:3; /* Reserved as of Nvm Express 1.1 Spec */
UINT8 Rsvd7[16]; /* Reserved as of Nvm Express 1.1 Spec */
} NVME_PSDESCRIPTOR;
//
// Identify Controller Data
//
typedef struct {
//
// Controller Capabilities and Features 0-255
//
UINT16 Vid; /* PCI Vendor ID */
UINT16 Ssvid; /* PCI sub-system vendor ID */
UINT8 Sn[20]; /* Product serial number */
UINT8 Mn[40]; /* Proeduct model number */
UINT8 Fr[8]; /* Firmware Revision */
UINT8 Rab; /* Recommended Arbitration Burst */
UINT8 Ieee_oui[3]; /* Organization Unique Identifier */
UINT8 Cmic; /* Multi-interface Capabilities */
UINT8 Mdts; /* Maximum Data Transfer Size */
UINT8 Cntlid[2]; /* Controller ID */
UINT8 Rsvd1[176]; /* Reserved as of Nvm Express 1.1 Spec */
//
// Admin Command Set Attributes
//
UINT16 Oacs; /* Optional Admin Command Support */
#define NAMESPACE_MANAGEMENT_SUPPORTED BIT3
#define FW_DOWNLOAD_ACTIVATE_SUPPORTED BIT2
#define FORMAT_NVM_SUPPORTED BIT1
#define SECURITY_SEND_RECEIVE_SUPPORTED BIT0
UINT8 Acl; /* Abort Command Limit */
UINT8 Aerl; /* Async Event Request Limit */
UINT8 Frmw; /* Firmware updates */
UINT8 Lpa; /* Log Page Attributes */
UINT8 Elpe; /* Error Log Page Entries */
UINT8 Npss; /* Number of Power States Support */
UINT8 Avscc; /* Admin Vendor Specific Command Configuration */
UINT8 Apsta; /* Autonomous Power State Transition Attributes */
UINT8 Rsvd2[246]; /* Reserved as of Nvm Express 1.1 Spec */
//
// NVM Command Set Attributes
//
UINT8 Sqes; /* Submission Queue Entry Size */
UINT8 Cqes; /* Completion Queue Entry Size */
UINT16 Rsvd3; /* Reserved as of Nvm Express 1.1 Spec */
UINT32 Nn; /* Number of Namespaces */
UINT16 Oncs; /* Optional NVM Command Support */
UINT16 Fuses; /* Fused Operation Support */
UINT8 Fna; /* Format NVM Attributes */
UINT8 Vwc; /* Volatile Write Cache */
UINT16 Awun; /* Atomic Write Unit Normal */
UINT16 Awupf; /* Atomic Write Unit Power Fail */
UINT8 Nvscc; /* NVM Vendor Specific Command Configuration */
UINT8 Rsvd4; /* Reserved as of Nvm Express 1.1 Spec */
UINT16 Acwu; /* Atomic Compare & Write Unit */
UINT16 Rsvd5; /* Reserved as of Nvm Express 1.1 Spec */
UINT32 Sgls; /* SGL Support */
UINT8 Rsvd6[164]; /* Reserved as of Nvm Express 1.1 Spec */
//
// I/O Command set Attributes
//
UINT8 Rsvd7[1344]; /* Reserved as of Nvm Express 1.1 Spec */
//
// Power State Descriptors
//
NVME_PSDESCRIPTOR PsDescriptor[32];
UINT8 VendorData[1024]; /* Vendor specific data */
} NVME_ADMIN_CONTROLLER_DATA;
typedef struct {
UINT16 Ms; /* Metadata Size */
UINT8 Lbads; /* LBA Data Size */
UINT8 Rp:2; /* Relative Performance */
#define LBAF_RP_BEST 00b
#define LBAF_RP_BETTER 01b
#define LBAF_RP_GOOD 10b
#define LBAF_RP_DEGRADED 11b
UINT8 Rsvd1:6; /* Reserved as of Nvm Express 1.1 Spec */
} NVME_LBAFORMAT;
//
// Identify Namespace Data
//
typedef struct {
//
// NVM Command Set Specific
//
UINT64 Nsze; /* Namespace Size (total number of blocks in formatted namespace) */
UINT64 Ncap; /* Namespace Capacity (max number of logical blocks) */
UINT64 Nuse; /* Namespace Utilization */
UINT8 Nsfeat; /* Namespace Features */
UINT8 Nlbaf; /* Number of LBA Formats */
UINT8 Flbas; /* Formatted LBA size */
UINT8 Mc; /* Metadata Capabilities */
UINT8 Dpc; /* End-to-end Data Protection capabilities */
UINT8 Dps; /* End-to-end Data Protection Type Settings */
UINT8 Nmic; /* Namespace Multi-path I/O and Namespace Sharing Capabilities */
UINT8 Rescap; /* Reservation Capabilities */
UINT8 Rsvd1[88]; /* Reserved as of Nvm Express 1.1 Spec */
UINT64 Eui64; /* IEEE Extended Unique Identifier */
//
// LBA Format
//
NVME_LBAFORMAT LbaFormat[16];
UINT8 Rsvd2[192]; /* Reserved as of Nvm Express 1.1 Spec */
UINT8 VendorData[3712]; /* Vendor specific data */
} NVME_ADMIN_NAMESPACE_DATA;
//
// NvmExpress Admin Identify Cmd
//
typedef struct {
//
// CDW 10
//
UINT32 Cns:2;
UINT32 Rsvd1:30;
} NVME_ADMIN_IDENTIFY;
//
// NvmExpress Admin Create I/O Completion Queue
//
typedef struct {
//
// CDW 10
//
UINT32 Qid:16; /* Queue Identifier */
UINT32 Qsize:16; /* Queue Size */
//
// CDW 11
//
UINT32 Pc:1; /* Physically Contiguous */
UINT32 Ien:1; /* Interrupts Enabled */
UINT32 Rsvd1:14; /* reserved as of Nvm Express 1.1 Spec */
UINT32 Iv:16; /* Interrupt Vector for MSI-X or MSI*/
} NVME_ADMIN_CRIOCQ;
//
// NvmExpress Admin Create I/O Submission Queue
//
typedef struct {
//
// CDW 10
//
UINT32 Qid:16; /* Queue Identifier */
UINT32 Qsize:16; /* Queue Size */
//
// CDW 11
//
UINT32 Pc:1; /* Physically Contiguous */
UINT32 Qprio:2; /* Queue Priority */
UINT32 Rsvd1:13; /* Reserved as of Nvm Express 1.1 Spec */
UINT32 Cqid:16; /* Completion Queue ID */
} NVME_ADMIN_CRIOSQ;
//
// NvmExpress Admin Delete I/O Completion Queue
//
typedef struct {
//
// CDW 10
//
UINT16 Qid;
UINT16 Rsvd1;
} NVME_ADMIN_DEIOCQ;
//
// NvmExpress Admin Delete I/O Submission Queue
//
typedef struct {
//
// CDW 10
//
UINT16 Qid;
UINT16 Rsvd1;
} NVME_ADMIN_DEIOSQ;
//
// NvmExpress Admin Abort Command
//
typedef struct {
//
// CDW 10
//
UINT32 Sqid:16; /* Submission Queue identifier */
UINT32 Cid:16; /* Command Identifier */
} NVME_ADMIN_ABORT;
//
// NvmExpress Admin Firmware Activate Command
//
typedef struct {
//
// CDW 10
//
UINT32 Fs:3; /* Submission Queue identifier */
UINT32 Aa:2; /* Command Identifier */
UINT32 Rsvd1:27;
} NVME_ADMIN_FIRMWARE_ACTIVATE;
//
// NvmExpress Admin Firmware Image Download Command
//
typedef struct {
//
// CDW 10
//
UINT32 Numd; /* Number of Dwords */
//
// CDW 11
//
UINT32 Ofst; /* Offset */
} NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD;
//
// NvmExpress Admin Get Features Command
//
typedef struct {
//
// CDW 10
//
UINT32 Fid:8; /* Feature Identifier */
UINT32 Sel:3; /* Select */
UINT32 Rsvd1:21;
} NVME_ADMIN_GET_FEATURES;
//
// NvmExpress Admin Get Log Page Command
//
typedef struct {
//
// CDW 10
//
UINT32 Lid:8; /* Log Page Identifier */
#define LID_ERROR_INFO 0x1
#define LID_SMART_INFO 0x2
#define LID_FW_SLOT_INFO 0x3
UINT32 Rsvd1:8;
UINT32 Numd:12; /* Number of Dwords */
UINT32 Rsvd2:4; /* Reserved as of Nvm Express 1.1 Spec */
} NVME_ADMIN_GET_LOG_PAGE;
//
// NvmExpress Admin Set Features Command
//
typedef struct {
//
// CDW 10
//
UINT32 Fid:8; /* Feature Identifier */
UINT32 Rsvd1:23;
UINT32 Sv:1; /* Save */
} NVME_ADMIN_SET_FEATURES;
//
// NvmExpress Admin Format NVM Command
//
typedef struct {
//
// CDW 10
//
UINT32 Lbaf:4; /* LBA Format */
UINT32 Ms:1; /* Metadata Settings */
UINT32 Pi:3; /* Protection Information */
UINT32 Pil:1; /* Protection Information Location */
UINT32 Ses:3; /* Secure Erase Settings */
UINT32 Rsvd1:20;
} NVME_ADMIN_FORMAT_NVM;
//
// NvmExpress Admin Security Receive Command
//
typedef struct {
//
// CDW 10
//
UINT32 Rsvd1:8;
UINT32 Spsp:16; /* SP Specific */
UINT32 Secp:8; /* Security Protocol */
//
// CDW 11
//
UINT32 Al; /* Allocation Length */
} NVME_ADMIN_SECURITY_RECEIVE;
//
// NvmExpress Admin Security Send Command
//
typedef struct {
//
// CDW 10
//
UINT32 Rsvd1:8;
UINT32 Spsp:16; /* SP Specific */
UINT32 Secp:8; /* Security Protocol */
//
// CDW 11
//
UINT32 Tl; /* Transfer Length */
} NVME_ADMIN_SECURITY_SEND;
typedef union {
NVME_ADMIN_IDENTIFY Identify;
NVME_ADMIN_CRIOCQ CrIoCq;
NVME_ADMIN_CRIOSQ CrIoSq;
NVME_ADMIN_DEIOCQ DeIoCq;
NVME_ADMIN_DEIOSQ DeIoSq;
NVME_ADMIN_ABORT Abort;
NVME_ADMIN_FIRMWARE_ACTIVATE Activate;
NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD FirmwareImageDownload;
NVME_ADMIN_GET_FEATURES GetFeatures;
NVME_ADMIN_GET_LOG_PAGE GetLogPage;
NVME_ADMIN_SET_FEATURES SetFeatures;
NVME_ADMIN_FORMAT_NVM FormatNvm;
NVME_ADMIN_SECURITY_RECEIVE SecurityReceive;
NVME_ADMIN_SECURITY_SEND SecuritySend;
} NVME_ADMIN_CMD;
typedef struct {
UINT32 Cdw10;
UINT32 Cdw11;
UINT32 Cdw12;
UINT32 Cdw13;
UINT32 Cdw14;
UINT32 Cdw15;
} NVME_RAW;
typedef union {
NVME_ADMIN_CMD Admin; // Union of Admin commands
NVME_CMD Nvm; // Union of Nvm commands
NVME_RAW Raw;
} NVME_PAYLOAD;
//
// Submission Queue
//
typedef struct {
//
// CDW 0, Common to all comnmands
//
UINT8 Opc; // Opcode
UINT8 Fuse:2; // Fused Operation
UINT8 Rsvd1:5;
UINT8 Psdt:1; // PRP or SGL for Data Transfer
UINT16 Cid; // Command Identifier
//
// CDW 1
//
UINT32 Nsid; // Namespace Identifier
//
// CDW 2,3
//
UINT64 Rsvd2;
//
// CDW 4,5
//
UINT64 Mptr; // Metadata Pointer
//
// CDW 6-9
//
UINT64 Prp[2]; // First and second PRP entries
NVME_PAYLOAD Payload;
} NVME_SQ;
//
// Completion Queue
//
typedef struct {
//
// CDW 0
//
UINT32 Dword0;
//
// CDW 1
//
UINT32 Rsvd1;
//
// CDW 2
//
UINT16 Sqhd; // Submission Queue Head Pointer
UINT16 Sqid; // Submission Queue Identifier
//
// CDW 3
//
UINT16 Cid; // Command Identifier
UINT16 Pt:1; // Phase Tag
UINT16 Sc:8; // Status Code
UINT16 Sct:3; // Status Code Type
UINT16 Rsvd2:2;
UINT16 Mo:1; // More
UINT16 Dnr:1; // Do Not Retry
} NVME_CQ;
//
// Nvm Express Admin cmd opcodes
//
#define NVME_ADMIN_DEIOSQ_CMD 0x00
#define NVME_ADMIN_CRIOSQ_CMD 0x01
#define NVME_ADMIN_GET_LOG_PAGE_CMD 0x02
#define NVME_ADMIN_DEIOCQ_CMD 0x04
#define NVME_ADMIN_CRIOCQ_CMD 0x05
#define NVME_ADMIN_IDENTIFY_CMD 0x06
#define NVME_ADMIN_ABORT_CMD 0x08
#define NVME_ADMIN_SET_FEATURES_CMD 0x09
#define NVME_ADMIN_GET_FEATURES_CMD 0x0A
#define NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD 0x0C
#define NVME_ADMIN_NAMESACE_MANAGEMENT_CMD 0x0D
#define NVME_ADMIN_FW_COMMIT_CMD 0x10
#define NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD 0x11
#define NVME_ADMIN_NAMESACE_ATTACHMENT_CMD 0x15
#define NVME_ADMIN_FORMAT_NVM_CMD 0x80
#define NVME_ADMIN_SECURITY_SEND_CMD 0x81
#define NVME_ADMIN_SECURITY_RECEIVE_CMD 0x82
#define NVME_IO_FLUSH_OPC 0
#define NVME_IO_WRITE_OPC 1
#define NVME_IO_READ_OPC 2
typedef enum {
DeleteIOSubmissionQueueOpcode = NVME_ADMIN_DEIOSQ_CMD,
CreateIOSubmissionQueueOpcode = NVME_ADMIN_CRIOSQ_CMD,
GetLogPageOpcode = NVME_ADMIN_GET_LOG_PAGE_CMD,
DeleteIOCompletionQueueOpcode = NVME_ADMIN_DEIOCQ_CMD,
CreateIOCompletionQueueOpcode = NVME_ADMIN_CRIOCQ_CMD,
IdentifyOpcode = NVME_ADMIN_IDENTIFY_CMD,
AbortOpcode = NVME_ADMIN_ABORT_CMD,
SetFeaturesOpcode = NVME_ADMIN_SET_FEATURES_CMD,
GetFeaturesOpcode = NVME_ADMIN_GET_FEATURES_CMD,
AsyncEventRequestOpcode = NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD,
NamespaceManagementOpcode = NVME_ADMIN_NAMESACE_MANAGEMENT_CMD,
FirmwareCommitOpcode = NVME_ADMIN_FW_COMMIT_CMD,
FirmwareImageDownloadOpcode = NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD,
NamespaceAttachmentOpcode = NVME_ADMIN_NAMESACE_ATTACHMENT_CMD,
FormatNvmOpcode = NVME_ADMIN_FORMAT_NVM_CMD,
SecuritySendOpcode = NVME_ADMIN_SECURITY_SEND_CMD,
SecurityReceiveOpcode = NVME_ADMIN_SECURITY_RECEIVE_CMD
} NVME_ADMIN_COMMAND_OPCODE;
//
// Controller or Namespace Structure (CNS) field
// (ref. spec. v1.1 figure 82).
//
typedef enum {
IdentifyNamespaceCns = 0x0,
IdentifyControllerCns = 0x1,
IdentifyActiveNsListCns = 0x2
} NVME_ADMIN_IDENTIFY_CNS;
//
// Commit Action
// (ref. spec. 1.1 figure 60).
//
typedef enum {
ActivateActionReplace = 0x0,
ActivateActionReplaceActivate = 0x1,
ActivateActionActivate = 0x2
} NVME_FW_ACTIVATE_ACTION;
//
// Firmware Slot
// (ref. spec. 1.1 Figure 60).
//
typedef enum {
FirmwareSlotCtrlChooses = 0x0,
FirmwareSlot1 = 0x1,
FirmwareSlot2 = 0x2,
FirmwareSlot3 = 0x3,
FirmwareSlot4 = 0x4,
FirmwareSlot5 = 0x5,
FirmwareSlot6 = 0x6,
FirmwareSlot7 = 0x7
} NVME_FW_ACTIVATE_SLOT;
//
// Get Log Page ? Log Page Identifiers
// (ref. spec. v1.1 Figure 73).
//
typedef enum {
ErrorInfoLogID = LID_ERROR_INFO,
SmartHealthInfoLogID = LID_SMART_INFO,
FirmwareSlotInfoLogID = LID_FW_SLOT_INFO
} NVME_LOG_ID;
//
// Get Log Page ? Firmware Slot Information Log
// (ref. spec. v1.1 Figure 77).
//
typedef struct {
//
// Indicates the firmware slot from which the actively running firmware revision was loaded.
//
UINT8 ActivelyRunningFwSlot:3;
UINT8 :1;
//
// Indicates the firmware slot that is going to be activated at the next controller reset. If this field is 0h, then the controller does not indicate the firmware slot that is going to be activated at the next controller reset.
//
UINT8 NextActiveFwSlot:3;
UINT8 :1;
} NVME_ACTIVE_FW_INFO;
//
// Get Log Page ? Firmware Slot Information Log
// (ref. spec. v1.1 Figure 77).
//
typedef struct {
//
// Specifies information about the active firmware revision.
//s
NVME_ACTIVE_FW_INFO ActiveFwInfo;
UINT8 Reserved1[7];
//
// Contains the revision of the firmware downloaded to firmware slot 1/7. If no valid firmware revision is present or if this slot is unsupported, all zeros shall be returned.
//
CHAR8 FwRevisionSlot[7][8];
UINT8 Reserved2[448];
} NVME_FW_SLOT_INFO_LOG;
//
// SMART / Health Information (Log Identifier 02h)
// (ref. spec. v1.1 5.10.1.2)
//
typedef struct {
//
// This field indicates critical warnings for the state of the controller.
//
UINT8 CriticalWarningAvailableSpare:1;
UINT8 CriticalWarningTemperature:1;
UINT8 CriticalWarningReliability:1;
UINT8 CriticalWarningMediaReadOnly:1;
UINT8 CriticalWarningVolatileBackup:1;
UINT8 CriticalWarningReserved:3;
//
// Contains a value corresponding to a temperature in degrees Kelvin that represents the current composite temperature of the controller and namespace(s) associated with that controller. The manner in which this value is computed is implementation specific and may not represent the actual temperature of any physical point in the NVM subsystem.
//
UINT16 CompositeTemp;
//
// Contains a normalized percentage (0 to 100%) of the remaining spare capacity available.
//
UINT8 AvailableSpare;
//
// When the Available Spare falls below the threshold indicated in this field, an asynchronous event completion may occur. The value is indicated as a normalized percentage (0 to 100%).
//
UINT8 AvailableSpareThreshold;
//
// Contains a vendor specific estimate of the percentage of NVM subsystem life used based on the actual usage and the manufacturer?s prediction of NVM life. A value of 100 indicates that the estimated endurance of the NVM in the NVM subsystem has been consumed, but may not indicate an NVM subsystem failure. The value is allowed to exceed 100. Percentages greater than 254 shall be represented as 255. This value shall be updated once per power-on hour (when the controller is not in a sleep state).
//
UINT8 PercentageUsed;
UINT8 Reserved1[26];
//
// Contains the number of 512 byte data units the host has read from the controller; this value does not include metadata.
//
UINT8 DataUnitsRead[16];
//
// Contains the number of 512 byte data units the host has written to the controller; this value does not include metadata.
//
UINT8 DataUnitsWritten[16];
//
// Contains the number of read commands completed by the controller.
//
UINT8 HostReadCommands[16];
//
// Contains the number of write commands completed by the controller.
//
UINT8 HostWriteCommands[16];
//
// Contains the amount of time the controller is busy with I/O commands. This value is reported in minutes.
//
UINT8 ControllerBusyTime[16];
//
// Contains the number of power cycles.
//
UINT8 PowerCycles[16];
//
// Contains the number of power-on hours.
//
UINT8 PowerOnHours[16];
//
// Contains the number of unsafe shutdowns.
//
UINT8 UnsafeShutdowns[16];
//
// Contains the number of occurrences where the controller detected an unrecovered data integrity error.
//
UINT8 MediaAndDataIntegrityErrors[16];
//
// Contains the number of Error Information log entries over the life of the controller.
//
UINT8 NumberErrorInformationLogEntries[16];
//
// Contains the amount of time in minutes that the controller is operational and the Composite Temperature is greater than or equal to the Warning Composite Temperature Threshold (WCTEMP) field and less than the Critical Composite Temperature Threshold (CCTEMP) field in the Identify Controller data structure in Figure 90.
//
UINT32 WarningCompositeTemperatureTime;
//
// Contains the amount of time in minutes that the controller is operational and the Composite Temperature is greater the Critical Composite Temperature Threshold (CCTEMP) field in the Identify Controller data structure in Figure 90.
//
UINT32 CriticalCompositeTemperatureTime;
//
// Contains the current temperature in degrees Kelvin reported by the temperature sensor. An implementation that does not implement the temperature sensor reports a temperature of zero degrees Kelvin.
//
UINT16 TemperatureSensor[8];
UINT8 Reserved2[296];
} NVME_SMART_HEALTH_INFO_LOG;
#pragma pack()
#endif

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/** @file
Support for the latest PCI standard.
Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _PCI_H_
#define _PCI_H_
#include <IndustryStandard/Pci30.h>
#include <IndustryStandard/PciExpress21.h>
#include <IndustryStandard/PciExpress30.h>
#include <IndustryStandard/PciCodeId.h>
#endif

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/** @file
Support for PCI 2.2 standard.
This file includes the definitions in the following specifications,
PCI Local Bus Specification, 2.2
PCI-to-PCI Bridge Architecture Specification, Revision 1.2
PC Card Standard, 8.0
PCI Power Management Interface Specifiction, Revision 1.2
Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2014 - 2015, Hewlett-Packard Development Company, L.P.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _PCI22_H_
#define _PCI22_H_
#define PCI_MAX_BUS 255
#define PCI_MAX_DEVICE 31
#define PCI_MAX_FUNC 7
#pragma pack(1)
///
/// Common header region in PCI Configuration Space
/// Section 6.1, PCI Local Bus Specification, 2.2
///
typedef struct {
UINT16 VendorId;
UINT16 DeviceId;
UINT16 Command;
UINT16 Status;
UINT8 RevisionID;
UINT8 ClassCode[3];
UINT8 CacheLineSize;
UINT8 LatencyTimer;
UINT8 HeaderType;
UINT8 BIST;
} PCI_DEVICE_INDEPENDENT_REGION;
///
/// PCI Device header region in PCI Configuration Space
/// Section 6.1, PCI Local Bus Specification, 2.2
///
typedef struct {
UINT32 Bar[6];
UINT32 CISPtr;
UINT16 SubsystemVendorID;
UINT16 SubsystemID;
UINT32 ExpansionRomBar;
UINT8 CapabilityPtr;
UINT8 Reserved1[3];
UINT32 Reserved2;
UINT8 InterruptLine;
UINT8 InterruptPin;
UINT8 MinGnt;
UINT8 MaxLat;
} PCI_DEVICE_HEADER_TYPE_REGION;
///
/// PCI Device Configuration Space
/// Section 6.1, PCI Local Bus Specification, 2.2
///
typedef struct {
PCI_DEVICE_INDEPENDENT_REGION Hdr;
PCI_DEVICE_HEADER_TYPE_REGION Device;
} PCI_TYPE00;
///
/// PCI-PCI Bridge header region in PCI Configuration Space
/// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2
///
typedef struct {
UINT32 Bar[2];
UINT8 PrimaryBus;
UINT8 SecondaryBus;
UINT8 SubordinateBus;
UINT8 SecondaryLatencyTimer;
UINT8 IoBase;
UINT8 IoLimit;
UINT16 SecondaryStatus;
UINT16 MemoryBase;
UINT16 MemoryLimit;
UINT16 PrefetchableMemoryBase;
UINT16 PrefetchableMemoryLimit;
UINT32 PrefetchableBaseUpper32;
UINT32 PrefetchableLimitUpper32;
UINT16 IoBaseUpper16;
UINT16 IoLimitUpper16;
UINT8 CapabilityPtr;
UINT8 Reserved[3];
UINT32 ExpansionRomBAR;
UINT8 InterruptLine;
UINT8 InterruptPin;
UINT16 BridgeControl;
} PCI_BRIDGE_CONTROL_REGISTER;
///
/// PCI-to-PCI Bridge Configuration Space
/// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2
///
typedef struct {
PCI_DEVICE_INDEPENDENT_REGION Hdr;
PCI_BRIDGE_CONTROL_REGISTER Bridge;
} PCI_TYPE01;
typedef union {
PCI_TYPE00 Device;
PCI_TYPE01 Bridge;
} PCI_TYPE_GENERIC;
///
/// CardBus Conroller Configuration Space,
/// Section 4.5.1, PC Card Standard. 8.0
///
typedef struct {
UINT32 CardBusSocketReg; ///< Cardus Socket/ExCA Base
UINT8 Cap_Ptr;
UINT8 Reserved;
UINT16 SecondaryStatus; ///< Secondary Status
UINT8 PciBusNumber; ///< PCI Bus Number
UINT8 CardBusBusNumber; ///< CardBus Bus Number
UINT8 SubordinateBusNumber; ///< Subordinate Bus Number
UINT8 CardBusLatencyTimer; ///< CardBus Latency Timer
UINT32 MemoryBase0; ///< Memory Base Register 0
UINT32 MemoryLimit0; ///< Memory Limit Register 0
UINT32 MemoryBase1;
UINT32 MemoryLimit1;
UINT32 IoBase0;
UINT32 IoLimit0; ///< I/O Base Register 0
UINT32 IoBase1; ///< I/O Limit Register 0
UINT32 IoLimit1;
UINT8 InterruptLine; ///< Interrupt Line
UINT8 InterruptPin; ///< Interrupt Pin
UINT16 BridgeControl; ///< Bridge Control
} PCI_CARDBUS_CONTROL_REGISTER;
//
// Definitions of PCI class bytes and manipulation macros.
//
#define PCI_CLASS_OLD 0x00
#define PCI_CLASS_OLD_OTHER 0x00
#define PCI_CLASS_OLD_VGA 0x01
#define PCI_CLASS_MASS_STORAGE 0x01
#define PCI_CLASS_MASS_STORAGE_SCSI 0x00
#define PCI_CLASS_MASS_STORAGE_IDE 0x01
#define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
#define PCI_CLASS_MASS_STORAGE_IPI 0x03
#define PCI_CLASS_MASS_STORAGE_RAID 0x04
#define PCI_CLASS_MASS_STORAGE_OTHER 0x80
#define PCI_CLASS_NETWORK 0x02
#define PCI_CLASS_NETWORK_ETHERNET 0x00
#define PCI_CLASS_NETWORK_TOKENRING 0x01
#define PCI_CLASS_NETWORK_FDDI 0x02
#define PCI_CLASS_NETWORK_ATM 0x03
#define PCI_CLASS_NETWORK_ISDN 0x04
#define PCI_CLASS_NETWORK_OTHER 0x80
#define PCI_CLASS_DISPLAY 0x03
#define PCI_CLASS_DISPLAY_VGA 0x00
#define PCI_IF_VGA_VGA 0x00
#define PCI_IF_VGA_8514 0x01
#define PCI_CLASS_DISPLAY_XGA 0x01
#define PCI_CLASS_DISPLAY_3D 0x02
#define PCI_CLASS_DISPLAY_OTHER 0x80
#define PCI_CLASS_MEDIA 0x04
#define PCI_CLASS_MEDIA_VIDEO 0x00
#define PCI_CLASS_MEDIA_AUDIO 0x01
#define PCI_CLASS_MEDIA_TELEPHONE 0x02
#define PCI_CLASS_MEDIA_OTHER 0x80
#define PCI_CLASS_MEMORY_CONTROLLER 0x05
#define PCI_CLASS_MEMORY_RAM 0x00
#define PCI_CLASS_MEMORY_FLASH 0x01
#define PCI_CLASS_MEMORY_OTHER 0x80
#define PCI_CLASS_BRIDGE 0x06
#define PCI_CLASS_BRIDGE_HOST 0x00
#define PCI_CLASS_BRIDGE_ISA 0x01
#define PCI_CLASS_BRIDGE_EISA 0x02
#define PCI_CLASS_BRIDGE_MCA 0x03
#define PCI_CLASS_BRIDGE_P2P 0x04
#define PCI_IF_BRIDGE_P2P 0x00
#define PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01
#define PCI_CLASS_BRIDGE_PCMCIA 0x05
#define PCI_CLASS_BRIDGE_NUBUS 0x06
#define PCI_CLASS_BRIDGE_CARDBUS 0x07
#define PCI_CLASS_BRIDGE_RACEWAY 0x08
#define PCI_CLASS_BRIDGE_OTHER 0x80
#define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80
#define PCI_CLASS_SCC 0x07 ///< Simple communications controllers
#define PCI_SUBCLASS_SERIAL 0x00
#define PCI_IF_GENERIC_XT 0x00
#define PCI_IF_16450 0x01
#define PCI_IF_16550 0x02
#define PCI_IF_16650 0x03
#define PCI_IF_16750 0x04
#define PCI_IF_16850 0x05
#define PCI_IF_16950 0x06
#define PCI_SUBCLASS_PARALLEL 0x01
#define PCI_IF_PARALLEL_PORT 0x00
#define PCI_IF_BI_DIR_PARALLEL_PORT 0x01
#define PCI_IF_ECP_PARALLEL_PORT 0x02
#define PCI_IF_1284_CONTROLLER 0x03
#define PCI_IF_1284_DEVICE 0xFE
#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
#define PCI_SUBCLASS_MODEM 0x03
#define PCI_IF_GENERIC_MODEM 0x00
#define PCI_IF_16450_MODEM 0x01
#define PCI_IF_16550_MODEM 0x02
#define PCI_IF_16650_MODEM 0x03
#define PCI_IF_16750_MODEM 0x04
#define PCI_SUBCLASS_SCC_OTHER 0x80
#define PCI_CLASS_SYSTEM_PERIPHERAL 0x08
#define PCI_SUBCLASS_PIC 0x00
#define PCI_IF_8259_PIC 0x00
#define PCI_IF_ISA_PIC 0x01
#define PCI_IF_EISA_PIC 0x02
#define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 bye none-prefectable memory.
#define PCI_IF_APIC_CONTROLLER2 0x20
#define PCI_SUBCLASS_DMA 0x01
#define PCI_IF_8237_DMA 0x00
#define PCI_IF_ISA_DMA 0x01
#define PCI_IF_EISA_DMA 0x02
#define PCI_SUBCLASS_TIMER 0x02
#define PCI_IF_8254_TIMER 0x00
#define PCI_IF_ISA_TIMER 0x01
#define PCI_IF_EISA_TIMER 0x02
#define PCI_SUBCLASS_RTC 0x03
#define PCI_IF_GENERIC_RTC 0x00
#define PCI_IF_ISA_RTC 0x01
#define PCI_SUBCLASS_PNP_CONTROLLER 0x04 ///< HotPlug Controller
#define PCI_SUBCLASS_PERIPHERAL_OTHER 0x80
#define PCI_CLASS_INPUT_DEVICE 0x09
#define PCI_SUBCLASS_KEYBOARD 0x00
#define PCI_SUBCLASS_PEN 0x01
#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
#define PCI_SUBCLASS_SCAN_CONTROLLER 0x03
#define PCI_SUBCLASS_GAMEPORT 0x04
#define PCI_IF_GAMEPORT 0x00
#define PCI_IF_GAMEPORT1 0x10
#define PCI_SUBCLASS_INPUT_OTHER 0x80
#define PCI_CLASS_DOCKING_STATION 0x0A
#define PCI_SUBCLASS_DOCKING_GENERIC 0x00
#define PCI_SUBCLASS_DOCKING_OTHER 0x80
#define PCI_CLASS_PROCESSOR 0x0B
#define PCI_SUBCLASS_PROC_386 0x00
#define PCI_SUBCLASS_PROC_486 0x01
#define PCI_SUBCLASS_PROC_PENTIUM 0x02
#define PCI_SUBCLASS_PROC_ALPHA 0x10
#define PCI_SUBCLASS_PROC_POWERPC 0x20
#define PCI_SUBCLASS_PROC_MIPS 0x30
#define PCI_SUBCLASS_PROC_CO_PORC 0x40 ///< Co-Processor
#define PCI_CLASS_SERIAL 0x0C
#define PCI_CLASS_SERIAL_FIREWIRE 0x00
#define PCI_IF_1394 0x00
#define PCI_IF_1394_OPEN_HCI 0x10
#define PCI_CLASS_SERIAL_ACCESS_BUS 0x01
#define PCI_CLASS_SERIAL_SSA 0x02
#define PCI_CLASS_SERIAL_USB 0x03
#define PCI_IF_UHCI 0x00
#define PCI_IF_OHCI 0x10
#define PCI_IF_USB_OTHER 0x80
#define PCI_IF_USB_DEVICE 0xFE
#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
#define PCI_CLASS_SERIAL_SMB 0x05
#define PCI_CLASS_WIRELESS 0x0D
#define PCI_SUBCLASS_IRDA 0x00
#define PCI_SUBCLASS_IR 0x01
#define PCI_SUBCLASS_RF 0x10
#define PCI_SUBCLASS_WIRELESS_OTHER 0x80
#define PCI_CLASS_INTELLIGENT_IO 0x0E
#define PCI_CLASS_SATELLITE 0x0F
#define PCI_SUBCLASS_TV 0x01
#define PCI_SUBCLASS_AUDIO 0x02
#define PCI_SUBCLASS_VOICE 0x03
#define PCI_SUBCLASS_DATA 0x04
#define PCI_SECURITY_CONTROLLER 0x10 ///< Encryption and decryption controller
#define PCI_SUBCLASS_NET_COMPUT 0x00
#define PCI_SUBCLASS_ENTERTAINMENT 0x10
#define PCI_SUBCLASS_SECURITY_OTHER 0x80
#define PCI_CLASS_DPIO 0x11
#define PCI_SUBCLASS_DPIO 0x00
#define PCI_SUBCLASS_DPIO_OTHER 0x80
/**
Macro that checks whether the Base Class code of device matched.
@param _p Specified device.
@param c Base Class code needs matching.
@retval TRUE Base Class code matches the specified device.
@retval FALSE Base Class code doesn't match the specified device.
**/
#define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))
/**
Macro that checks whether the Base Class code and Sub-Class code of device matched.
@param _p Specified device.
@param c Base Class code needs matching.
@param s Sub-Class code needs matching.
@retval TRUE Base Class code and Sub-Class code match the specified device.
@retval FALSE Base Class code and Sub-Class code don't match the specified device.
**/
#define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
/**
Macro that checks whether the Base Class code, Sub-Class code and Interface code of device matched.
@param _p Specified device.
@param c Base Class code needs matching.
@param s Sub-Class code needs matching.
@param p Interface code needs matching.
@retval TRUE Base Class code, Sub-Class code and Interface code match the specified device.
@retval FALSE Base Class code, Sub-Class code and Interface code don't match the specified device.
**/
#define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
/**
Macro that checks whether device is a display controller.
@param _p Specified device.
@retval TRUE Device is a display controller.
@retval FALSE Device is not a display controller.
**/
#define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
/**
Macro that checks whether device is a VGA-compatible controller.
@param _p Specified device.
@retval TRUE Device is a VGA-compatible controller.
@retval FALSE Device is not a VGA-compatible controller.
**/
#define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_VGA)
/**
Macro that checks whether device is an 8514-compatible controller.
@param _p Specified device.
@retval TRUE Device is an 8514-compatible controller.
@retval FALSE Device is not an 8514-compatible controller.
**/
#define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_8514)
/**
Macro that checks whether device is built before the Class Code field was defined.
@param _p Specified device.
@retval TRUE Device is an old device.
@retval FALSE Device is not an old device.
**/
#define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)
/**
Macro that checks whether device is a VGA-compatible device built before the Class Code field was defined.
@param _p Specified device.
@retval TRUE Device is an old VGA-compatible device.
@retval FALSE Device is not an old VGA-compatible device.
**/
#define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
/**
Macro that checks whether device is an IDE controller.
@param _p Specified device.
@retval TRUE Device is an IDE controller.
@retval FALSE Device is not an IDE controller.
**/
#define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
/**
Macro that checks whether device is a SCSI bus controller.
@param _p Specified device.
@retval TRUE Device is a SCSI bus controller.
@retval FALSE Device is not a SCSI bus controller.
**/
#define IS_PCI_SCSI(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI)
/**
Macro that checks whether device is a RAID controller.
@param _p Specified device.
@retval TRUE Device is a RAID controller.
@retval FALSE Device is not a RAID controller.
**/
#define IS_PCI_RAID(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID)
/**
Macro that checks whether device is an ISA bridge.
@param _p Specified device.
@retval TRUE Device is an ISA bridge.
@retval FALSE Device is not an ISA bridge.
**/
#define IS_PCI_LPC(_p) IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)
/**
Macro that checks whether device is a PCI-to-PCI bridge.
@param _p Specified device.
@retval TRUE Device is a PCI-to-PCI bridge.
@retval FALSE Device is not a PCI-to-PCI bridge.
**/
#define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P)
/**
Macro that checks whether device is a Subtractive Decode PCI-to-PCI bridge.
@param _p Specified device.
@retval TRUE Device is a Subtractive Decode PCI-to-PCI bridge.
@retval FALSE Device is not a Subtractive Decode PCI-to-PCI bridge.
**/
#define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE)
/**
Macro that checks whether device is a 16550-compatible serial controller.
@param _p Specified device.
@retval TRUE Device is a 16550-compatible serial controller.
@retval FALSE Device is not a 16550-compatible serial controller.
**/
#define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)
/**
Macro that checks whether device is a Universal Serial Bus controller.
@param _p Specified device.
@retval TRUE Device is a Universal Serial Bus controller.
@retval FALSE Device is not a Universal Serial Bus controller.
**/
#define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
//
// the definition of Header Type
//
#define HEADER_TYPE_DEVICE 0x00
#define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
#define HEADER_TYPE_CARDBUS_BRIDGE 0x02
#define HEADER_TYPE_MULTI_FUNCTION 0x80
//
// Mask of Header type
//
#define HEADER_LAYOUT_CODE 0x7f
/**
Macro that checks whether device is a PCI-PCI bridge.
@param _p Specified device.
@retval TRUE Device is a PCI-PCI bridge.
@retval FALSE Device is not a PCI-PCI bridge.
**/
#define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
/**
Macro that checks whether device is a CardBus bridge.
@param _p Specified device.
@retval TRUE Device is a CardBus bridge.
@retval FALSE Device is not a CardBus bridge.
**/
#define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
/**
Macro that checks whether device is a multiple functions device.
@param _p Specified device.
@retval TRUE Device is a multiple functions device.
@retval FALSE Device is not a multiple functions device.
**/
#define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
///
/// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecure Specification,
///
#define PCI_BRIDGE_ROMBAR 0x38
#define PCI_MAX_BAR 0x0006
#define PCI_MAX_CONFIG_OFFSET 0x0100
#define PCI_VENDOR_ID_OFFSET 0x00
#define PCI_DEVICE_ID_OFFSET 0x02
#define PCI_COMMAND_OFFSET 0x04
#define PCI_PRIMARY_STATUS_OFFSET 0x06
#define PCI_REVISION_ID_OFFSET 0x08
#define PCI_CLASSCODE_OFFSET 0x09
#define PCI_CACHELINE_SIZE_OFFSET 0x0C
#define PCI_LATENCY_TIMER_OFFSET 0x0D
#define PCI_HEADER_TYPE_OFFSET 0x0E
#define PCI_BIST_OFFSET 0x0F
#define PCI_BASE_ADDRESSREG_OFFSET 0x10
#define PCI_CARDBUS_CIS_OFFSET 0x28
#define PCI_SVID_OFFSET 0x2C ///< SubSystem Vendor id
#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C
#define PCI_SID_OFFSET 0x2E ///< SubSystem ID
#define PCI_SUBSYSTEM_ID_OFFSET 0x2E
#define PCI_EXPANSION_ROM_BASE 0x30
#define PCI_CAPBILITY_POINTER_OFFSET 0x34
#define PCI_INT_LINE_OFFSET 0x3C ///< Interrupt Line Register
#define PCI_INT_PIN_OFFSET 0x3D ///< Interrupt Pin Register
#define PCI_MAXGNT_OFFSET 0x3E ///< Max Grant Register
#define PCI_MAXLAT_OFFSET 0x3F ///< Max Latency Register
//
// defined in PCI-to-PCI Bridge Architecture Specification
//
#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18
#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19
#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a
#define PCI_BRIDGE_SECONDARY_LATENCY_TIMER_OFFSET 0x1b
#define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E
#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E
///
/// Interrupt Line "Unknown" or "No connection" value defined for x86 based system
///
#define PCI_INT_LINE_UNKNOWN 0xFF
///
/// PCI Access Data Format
///
typedef union {
struct {
UINT32 Reg : 8;
UINT32 Func : 3;
UINT32 Dev : 5;
UINT32 Bus : 8;
UINT32 Reserved : 7;
UINT32 Enable : 1;
} Bits;
UINT32 Uint32;
} PCI_CONFIG_ACCESS_CF8;
#pragma pack()
#define EFI_PCI_COMMAND_IO_SPACE BIT0 ///< 0x0001
#define EFI_PCI_COMMAND_MEMORY_SPACE BIT1 ///< 0x0002
#define EFI_PCI_COMMAND_BUS_MASTER BIT2 ///< 0x0004
#define EFI_PCI_COMMAND_SPECIAL_CYCLE BIT3 ///< 0x0008
#define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE BIT4 ///< 0x0010
#define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP BIT5 ///< 0x0020
#define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND BIT6 ///< 0x0040
#define EFI_PCI_COMMAND_STEPPING_CONTROL BIT7 ///< 0x0080
#define EFI_PCI_COMMAND_SERR BIT8 ///< 0x0100
#define EFI_PCI_COMMAND_FAST_BACK_TO_BACK BIT9 ///< 0x0200
//
// defined in PCI-to-PCI Bridge Architecture Specification
//
#define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE BIT0 ///< 0x0001
#define EFI_PCI_BRIDGE_CONTROL_SERR BIT1 ///< 0x0002
#define EFI_PCI_BRIDGE_CONTROL_ISA BIT2 ///< 0x0004
#define EFI_PCI_BRIDGE_CONTROL_VGA BIT3 ///< 0x0008
#define EFI_PCI_BRIDGE_CONTROL_VGA_16 BIT4 ///< 0x0010
#define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT BIT5 ///< 0x0020
#define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS BIT6 ///< 0x0040
#define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK BIT7 ///< 0x0080
#define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER BIT8 ///< 0x0100
#define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER BIT9 ///< 0x0200
#define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS BIT10 ///< 0x0400
#define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR BIT11 ///< 0x0800
//
// Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard
//
#define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE BIT7 ///< 0x0080
#define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE BIT8 ///< 0x0100
#define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE BIT9 ///< 0x0200
#define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE BIT10 ///< 0x0400
//
// Following are the PCI status control bit
//
#define EFI_PCI_STATUS_CAPABILITY BIT4 ///< 0x0010
#define EFI_PCI_STATUS_66MZ_CAPABLE BIT5 ///< 0x0020
#define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE BIT7 ///< 0x0080
#define EFI_PCI_MASTER_DATA_PARITY_ERROR BIT8 ///< 0x0100
///
/// defined in PC Card Standard
///
#define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14
#pragma pack(1)
//
// PCI Capability List IDs and records
//
#define EFI_PCI_CAPABILITY_ID_PMI 0x01
#define EFI_PCI_CAPABILITY_ID_AGP 0x02
#define EFI_PCI_CAPABILITY_ID_VPD 0x03
#define EFI_PCI_CAPABILITY_ID_SLOTID 0x04
#define EFI_PCI_CAPABILITY_ID_MSI 0x05
#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
#define EFI_PCI_CAPABILITY_ID_SHPC 0x0C
///
/// Capabilities List Header
/// Section 6.7, PCI Local Bus Specification, 2.2
///
typedef struct {
UINT8 CapabilityID;
UINT8 NextItemPtr;
} EFI_PCI_CAPABILITY_HDR;
///
/// PMC - Power Management Capabilities
/// Section 3.2.3, PCI Power Management Interface Specifiction, Revision 1.2
///
typedef union {
struct {
UINT16 Version : 3;
UINT16 PmeClock : 1;
UINT16 Reserved : 1;
UINT16 DeviceSpecificInitialization : 1;
UINT16 AuxCurrent : 3;
UINT16 D1Support : 1;
UINT16 D2Support : 1;
UINT16 PmeSupport : 5;
} Bits;
UINT16 Data;
} EFI_PCI_PMC;
#define EFI_PCI_PMC_D3_COLD_MASK (BIT15)
///
/// PMCSR - Power Management Control/Status
/// Section 3.2.4, PCI Power Management Interface Specifiction, Revision 1.2
///
typedef union {
struct {
UINT16 PowerState : 2;
UINT16 ReservedForPciExpress : 1;
UINT16 NoSoftReset : 1;
UINT16 Reserved : 4;
UINT16 PmeEnable : 1;
UINT16 DataSelect : 4;
UINT16 DataScale : 2;
UINT16 PmeStatus : 1;
} Bits;
UINT16 Data;
} EFI_PCI_PMCSR;
#define PCI_POWER_STATE_D0 0
#define PCI_POWER_STATE_D1 1
#define PCI_POWER_STATE_D2 2
#define PCI_POWER_STATE_D3_HOT 3
///
/// PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions
/// Section 3.2.5, PCI Power Management Interface Specifiction, Revision 1.2
///
typedef union {
struct {
UINT8 Reserved : 6;
UINT8 B2B3 : 1;
UINT8 BusPowerClockControl : 1;
} Bits;
UINT8 Uint8;
} EFI_PCI_PMCSR_BSE;
///
/// Power Management Register Block Definition
/// Section 3.2, PCI Power Management Interface Specifiction, Revision 1.2
///
typedef struct {
EFI_PCI_CAPABILITY_HDR Hdr;
EFI_PCI_PMC PMC;
EFI_PCI_PMCSR PMCSR;
EFI_PCI_PMCSR_BSE BridgeExtention;
UINT8 Data;
} EFI_PCI_CAPABILITY_PMI;
///
/// A.G.P Capability
/// Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0
///
typedef struct {
EFI_PCI_CAPABILITY_HDR Hdr;
UINT8 Rev;
UINT8 Reserved;
UINT32 Status;
UINT32 Command;
} EFI_PCI_CAPABILITY_AGP;
///
/// VPD Capability Structure
/// Appendix I, PCI Local Bus Specification, 2.2
///
typedef struct {
EFI_PCI_CAPABILITY_HDR Hdr;
UINT16 AddrReg;
UINT32 DataReg;
} EFI_PCI_CAPABILITY_VPD;
///
/// Slot Numbering Capabilities Register
/// Section 3.2.6, PCI-to-PCI Bridge Architeture Specification, Revision 1.2
///
typedef struct {
EFI_PCI_CAPABILITY_HDR Hdr;
UINT8 ExpnsSlotReg;
UINT8 ChassisNo;
} EFI_PCI_CAPABILITY_SLOTID;
///
/// Message Capability Structure for 32-bit Message Address
/// Section 6.8.1, PCI Local Bus Specification, 2.2
///
typedef struct {
EFI_PCI_CAPABILITY_HDR Hdr;
UINT16 MsgCtrlReg;
UINT32 MsgAddrReg;
UINT16 MsgDataReg;
} EFI_PCI_CAPABILITY_MSI32;
///
/// Message Capability Structure for 64-bit Message Address
/// Section 6.8.1, PCI Local Bus Specification, 2.2
///
typedef struct {
EFI_PCI_CAPABILITY_HDR Hdr;
UINT16 MsgCtrlReg;
UINT32 MsgAddrRegLsdw;
UINT32 MsgAddrRegMsdw;
UINT16 MsgDataReg;
} EFI_PCI_CAPABILITY_MSI64;
///
/// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG,
/// CompactPCI Hot Swap Specification PICMG 2.1, R1.0
///
typedef struct {
EFI_PCI_CAPABILITY_HDR Hdr;
///
/// not finished - fields need to go here
///
} EFI_PCI_CAPABILITY_HOTPLUG;
///
/// Below macros (till PCI_BAR_NOCHANGE) were used by EfiIncompatiblePciDeviceSupport Protocol.
///
#ifndef DISABLE_NEW_DEPRECATED_INTERFACES
///
/// [ATTENTION] These macros are deprecated because they don't match Spec or not defined in Spec.
///
#define DEVICE_ID_NOCARE 0xFFFF ///< Deprecated. Value doesn't match Spec.
#define PCI_BAR_OLD_ALIGN 0xFFFFFFFFFFFFFFFFULL ///< Deprecated. Value isn't defined in Spec.
#define PCI_BAR_EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL ///< Deprecated. Value isn't defined in Spec.
#define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL ///< Deprecated. Value isn't defined in Spec.
#define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL ///< Deprecated. Value isn't defined in Spec.
#define PCI_BAR_ALL 0xFF ///< Deprecated. Value doesn't match Spec.
#define PCI_ACPI_UNUSED 0 ///< Deprecated. Macro name is too general.
#define PCI_BAR_NOCHANGE 0 ///< Deprecated. Macro name is too general.
#endif
#define PCI_BAR_IDX0 0x00
#define PCI_BAR_IDX1 0x01
#define PCI_BAR_IDX2 0x02
#define PCI_BAR_IDX3 0x03
#define PCI_BAR_IDX4 0x04
#define PCI_BAR_IDX5 0x05
///
/// EFI PCI Option ROM definitions
///
#define EFI_ROOT_BRIDGE_LIST 'eprb'
#define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1 ///< defined in UEFI Spec.
#define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55
#define PCI_DATA_STRUCTURE_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', 'R')
#define PCI_CODE_TYPE_PCAT_IMAGE 0x00
#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001 ///< defined in UEFI spec.
///
/// Standard PCI Expansion ROM Header
/// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1
///
typedef struct {
UINT16 Signature; ///< 0xaa55
UINT8 Reserved[0x16];
UINT16 PcirOffset;
} PCI_EXPANSION_ROM_HEADER;
///
/// Legacy ROM Header Extensions
/// Section 6.3.3.1, PCI Local Bus Specification, 2.2
///
typedef struct {
UINT16 Signature; ///< 0xaa55
UINT8 Size512;
UINT8 InitEntryPoint[3];
UINT8 Reserved[0x12];
UINT16 PcirOffset;
} EFI_LEGACY_EXPANSION_ROM_HEADER;
///
/// PCI Data Structure Format
/// Section 6.3.1.2, PCI Local Bus Specification, 2.2
///
typedef struct {
UINT32 Signature; ///< "PCIR"
UINT16 VendorId;
UINT16 DeviceId;
UINT16 Reserved0;
UINT16 Length;
UINT8 Revision;
UINT8 ClassCode[3];
UINT16 ImageLength;
UINT16 CodeRevision;
UINT8 CodeType;
UINT8 Indicator;
UINT16 Reserved1;
} PCI_DATA_STRUCTURE;
///
/// EFI PCI Expansion ROM Header
/// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1
///
typedef struct {
UINT16 Signature; ///< 0xaa55
UINT16 InitializationSize;
UINT32 EfiSignature; ///< 0x0EF1
UINT16 EfiSubsystem;
UINT16 EfiMachineType;
UINT16 CompressionType;
UINT8 Reserved[8];
UINT16 EfiImageHeaderOffset;
UINT16 PcirOffset;
} EFI_PCI_EXPANSION_ROM_HEADER;
typedef union {
UINT8 *Raw;
PCI_EXPANSION_ROM_HEADER *Generic;
EFI_PCI_EXPANSION_ROM_HEADER *Efi;
EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt;
} EFI_PCI_ROM_HEADER;
#pragma pack()
#endif

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/** @file
Support for PCI 2.3 standard.
Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _PCI23_H_
#define _PCI23_H_
#include <IndustryStandard/Pci22.h>
///
/// PCI_CLASS_MASS_STORAGE, Base Class 01h.
///
///@{
#define PCI_CLASS_MASS_STORAGE_ATA 0x05
#define PCI_IF_MASS_STORAGE_SINGLE_DMA 0x20
#define PCI_IF_MASS_STORAGE_CHAINED_DMA 0x30
///@}
///
/// PCI_CLASS_NETWORK, Base Class 02h.
///
///@{
#define PCI_CLASS_NETWORK_WORLDFIP 0x05
#define PCI_CLASS_NETWORK_PICMG_MULTI_COMPUTING 0x06
///@}
///
/// PCI_CLASS_BRIDGE, Base Class 06h.
///
///@{
#define PCI_CLASS_BRIDGE_SEMI_TRANSPARENT_P2P 0x09
#define PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_PRIMARY 0x40
#define PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_SECONDARY 0x80
#define PCI_CLASS_BRIDGE_INFINIBAND_TO_PCI 0x0A
///@}
///
/// PCI_CLASS_SCC, Base Class 07h.
///
///@{
#define PCI_SUBCLASS_GPIB 0x04
#define PCI_SUBCLASS_SMART_CARD 0x05
///@}
///
/// PCI_CLASS_SERIAL, Base Class 0Ch.
///
///@{
#define PCI_IF_EHCI 0x20
#define PCI_CLASS_SERIAL_IB 0x06
#define PCI_CLASS_SERIAL_IPMI 0x07
#define PCI_IF_IPMI_SMIC 0x00
#define PCI_IF_IPMI_KCS 0x01 ///< Keyboard Controller Style
#define PCI_IF_IPMI_BT 0x02 ///< Block Transfer
#define PCI_CLASS_SERIAL_SERCOS 0x08
#define PCI_CLASS_SERIAL_CANBUS 0x09
///@}
///
/// PCI_CLASS_WIRELESS, Base Class 0Dh.
///
///@{
#define PCI_SUBCLASS_BLUETOOTH 0x11
#define PCI_SUBCLASS_BROADBAND 0x12
///@}
///
/// PCI_CLASS_DPIO, Base Class 11h.
///
///@{
#define PCI_SUBCLASS_PERFORMANCE_COUNTERS 0x01
#define PCI_SUBCLASS_COMMUNICATION_SYNCHRONIZATION 0x10
#define PCI_SUBCLASS_MANAGEMENT_CARD 0x20
///@}
///
/// defined in PCI Express Spec.
///
#define PCI_EXP_MAX_CONFIG_OFFSET 0x1000
///
/// PCI Capability List IDs and records.
///
#define EFI_PCI_CAPABILITY_ID_PCIX 0x07
#pragma pack(1)
///
/// PCI-X Capabilities List,
/// Section 7.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b.
///
typedef struct {
EFI_PCI_CAPABILITY_HDR Hdr;
UINT16 CommandReg;
UINT32 StatusReg;
} EFI_PCI_CAPABILITY_PCIX;
///
/// PCI-X Bridge Capabilities List,
/// Section 8.6.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b.
///
typedef struct {
EFI_PCI_CAPABILITY_HDR Hdr;
UINT16 SecStatusReg;
UINT32 StatusReg;
UINT32 SplitTransCtrlRegUp;
UINT32 SplitTransCtrlRegDn;
} EFI_PCI_CAPABILITY_PCIX_BRDG;
#pragma pack()
#define PCI_CODE_TYPE_EFI_IMAGE 0x03
#endif

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/** @file
Support for PCI 3.0 standard.
Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __PCI30_H__
#define __PCI30_H__
#include <IndustryStandard/Pci23.h>
///
/// PCI_CLASS_MASS_STORAGE, Base Class 01h.
///
///@{
#define PCI_CLASS_MASS_STORAGE_SATADPA 0x06
#define PCI_IF_MASS_STORAGE_SATA 0x00
#define PCI_IF_MASS_STORAGE_AHCI 0x01
///@}
///
/// PCI_CLASS_WIRELESS, Base Class 0Dh.
///
///@{
#define PCI_SUBCLASS_ETHERNET_80211A 0x20
#define PCI_SUBCLASS_ETHERNET_80211B 0x21
///@}
/**
Macro that checks whether device is a SATA controller.
@param _p Specified device.
@retval TRUE Device is a SATA controller.
@retval FALSE Device is not a SATA controller.
**/
#define IS_PCI_SATADPA(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SATADPA)
///
/// PCI Capability List IDs and records
///
#define EFI_PCI_CAPABILITY_ID_PCIEXP 0x10
#pragma pack(1)
///
/// PCI Data Structure Format
/// Section 5.1.2, PCI Firmware Specification, Revision 3.0
///
typedef struct {
UINT32 Signature; ///< "PCIR"
UINT16 VendorId;
UINT16 DeviceId;
UINT16 DeviceListOffset;
UINT16 Length;
UINT8 Revision;
UINT8 ClassCode[3];
UINT16 ImageLength;
UINT16 CodeRevision;
UINT8 CodeType;
UINT8 Indicator;
UINT16 MaxRuntimeImageLength;
UINT16 ConfigUtilityCodeHeaderOffset;
UINT16 DMTFCLPEntryPointOffset;
} PCI_3_0_DATA_STRUCTURE;
#pragma pack()
#endif

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/** @file
The file lists the PCI class codes only defined in PCI code and ID assignment specification
revision 1.3.
Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __PCI_CODE_ID_H__
#define __PCI_CODE_ID_H__
///
/// PCI_CLASS_MASS_STORAGE, Base Class 01h.
///
///@{
#define PCI_IF_MASS_STORAGE_SCSI_VENDOR_SPECIFIC 0x00
#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_PQI 0x11
#define PCI_IF_MASS_STORAGE_SCSI_CONTROLLER_PQI 0x12
#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_CONTROLLER_PQI 0x13
#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_NVM_EXPRESS 0x21
#define PCI_IF_MASS_STORAGE_SATA_SERIAL_BUS 0x02
#define PCI_CLASS_MASS_STORAGE_SAS 0x07
#define PCI_IF_MASS_STORAGE_SAS 0x00
#define PCI_IF_MASS_STORAGE_SAS_SERIAL_BUS 0x01
#define PCI_CLASS_MASS_STORAGE_SOLID_STATE 0x08
#define PCI_IF_MASS_STORAGE_SOLID_STATE 0x00
#define PCI_IF_MASS_STORAGE_SOLID_STATE_NVMHCI 0x01
#define PCI_IF_MASS_STORAGE_SOLID_STATE_ENTERPRISE_NVMHCI 0x02
///@}
///
/// PCI_CLASS_NETWORK, Base Class 02h.
///
///@{
#define PCI_CLASS_NETWORK_INFINIBAND 0x07
///@}
///
/// PCI_CLASS_MEDIA, Base Class 04h.
///
///@{
#define PCI_CLASS_MEDIA_MIXED_MODE 0x03
///@}
///
/// PCI_CLASS_BRIDGE, Base Class 06h.
///
///@{
#define PCI_CLASS_BRIDGE_ADVANCED_SWITCHING_TO_PCI 0x0B
#define PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_CUSTOM 0x00
#define PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_ASI_SIG 0x01
///@}
///
/// PCI_CLASS_SYSTEM_PERIPHERAL, Base Class 08h.
///
///@{
#define PCI_IF_HPET 0x03
#define PCI_SUBCLASS_SD_HOST_CONTROLLER 0x05
#define PCI_SUBCLASS_IOMMU 0x06
///@}
///
/// PCI_CLASS_PROCESSOR, Base Class 0Bh.
///
///@{
#define PCI_SUBCLASS_PROC_OTHER 0x80
///@}
///
/// PCI_CLASS_SERIAL, Base Class 0Ch.
///
///@{
#define PCI_IF_XHCI 0x30
#define PCI_CLASS_SERIAL_OTHER 0x80
///@}
///
/// PCI_CLASS_SATELLITE, Base Class 0Fh.
///
///@{
#define PCI_SUBCLASS_SATELLITE_OTHER 0x80
///@}
///
/// PCI_CLASS_PROCESSING_ACCELERATOR, Base Class 12h.
///
///@{
#define PCI_CLASS_PROCESSING_ACCELERATOR 0x12
///@}
#endif

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/** @file
Support for the latest PCI standard.
Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
(C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _PCIEXPRESS21_H_
#define _PCIEXPRESS21_H_
#include <IndustryStandard/Pci30.h>
#pragma pack(1)
///
/// PCI Express Capability Structure
///
typedef union {
struct {
UINT16 Version : 4;
UINT16 DevicePortType : 4;
UINT16 SlotImplemented : 1;
UINT16 InterruptMessageNumber : 5;
UINT16 Undefined : 1;
UINT16 Reserved : 1;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_CAPABILITY;
#define PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT 0
#define PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT 1
#define PCIE_DEVICE_PORT_TYPE_ROOT_PORT 4
#define PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT 5
#define PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT 6
#define PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE 7
#define PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE 8
#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT 9
#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR 10
typedef union {
struct {
UINT32 MaxPayloadSize : 3;
UINT32 PhantomFunctions : 2;
UINT32 ExtendedTagField : 1;
UINT32 EndpointL0sAcceptableLatency : 3;
UINT32 EndpointL1AcceptableLatency : 3;
UINT32 Undefined : 3;
UINT32 RoleBasedErrorReporting : 1;
UINT32 Reserved : 2;
UINT32 CapturedSlotPowerLimitValue : 8;
UINT32 CapturedSlotPowerLimitScale : 2;
UINT32 FunctionLevelReset : 1;
UINT32 Reserved2 : 3;
} Bits;
UINT32 Uint32;
} PCI_REG_PCIE_DEVICE_CAPABILITY;
typedef union {
struct {
UINT16 CorrectableError : 1;
UINT16 NonFatalError : 1;
UINT16 FatalError : 1;
UINT16 UnsupportedRequest : 1;
UINT16 RelaxedOrdering : 1;
UINT16 MaxPayloadSize : 3;
UINT16 ExtendedTagField : 1;
UINT16 PhantomFunctions : 1;
UINT16 AuxPower : 1;
UINT16 NoSnoop : 1;
UINT16 MaxReadRequestSize : 3;
UINT16 BridgeConfigurationRetryOrFunctionLevelReset : 1;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_DEVICE_CONTROL;
typedef union {
struct {
UINT16 CorrectableError : 1;
UINT16 NonFatalError : 1;
UINT16 FatalError : 1;
UINT16 UnsupportedRequest : 1;
UINT16 AuxPower : 1;
UINT16 TransactionsPending : 1;
UINT16 Reserved : 10;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_DEVICE_STATUS;
typedef union {
struct {
UINT32 MaxLinkSpeed : 4;
UINT32 MaxLinkWidth : 6;
UINT32 Aspm : 2;
UINT32 L0sExitLatency : 3;
UINT32 L1ExitLatency : 3;
UINT32 ClockPowerManagement : 1;
UINT32 SurpriseDownError : 1;
UINT32 DataLinkLayerLinkActive : 1;
UINT32 LinkBandwidthNotification : 1;
UINT32 AspmOptionalityCompliance : 1;
UINT32 Reserved : 1;
UINT32 PortNumber : 8;
} Bits;
UINT32 Uint32;
} PCI_REG_PCIE_LINK_CAPABILITY;
#define PCIE_LINK_ASPM_L0S BIT0
#define PCIE_LINK_ASPM_L1 BIT1
typedef union {
struct {
UINT16 AspmControl : 2;
UINT16 Reserved : 1;
UINT16 ReadCompletionBoundary : 1;
UINT16 LinkDisable : 1;
UINT16 RetrainLink : 1;
UINT16 CommonClockConfiguration : 1;
UINT16 ExtendedSynch : 1;
UINT16 ClockPowerManagement : 1;
UINT16 HardwareAutonomousWidthDisable : 1;
UINT16 LinkBandwidthManagementInterrupt : 1;
UINT16 LinkAutonomousBandwidthInterrupt : 1;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_LINK_CONTROL;
typedef union {
struct {
UINT16 CurrentLinkSpeed : 4;
UINT16 NegotiatedLinkWidth : 6;
UINT16 Undefined : 1;
UINT16 LinkTraining : 1;
UINT16 SlotClockConfiguration : 1;
UINT16 DataLinkLayerLinkActive : 1;
UINT16 LinkBandwidthManagement : 1;
UINT16 LinkAutonomousBandwidth : 1;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_LINK_STATUS;
typedef union {
struct {
UINT32 AttentionButton : 1;
UINT32 PowerController : 1;
UINT32 MrlSensor : 1;
UINT32 AttentionIndicator : 1;
UINT32 PowerIndicator : 1;
UINT32 HotPlugSurprise : 1;
UINT32 HotPlugCapable : 1;
UINT32 SlotPowerLimitValue : 8;
UINT32 SlotPowerLimitScale : 2;
UINT32 ElectromechanicalInterlock : 1;
UINT32 NoCommandCompleted : 1;
UINT32 PhysicalSlotNumber : 13;
} Bits;
UINT32 Uint32;
} PCI_REG_PCIE_SLOT_CAPABILITY;
typedef union {
struct {
UINT32 AttentionButtonPressed : 1;
UINT32 PowerFaultDetected : 1;
UINT32 MrlSensorChanged : 1;
UINT32 PresenceDetectChanged : 1;
UINT32 CommandCompletedInterrupt : 1;
UINT32 HotPlugInterrupt : 1;
UINT32 AttentionIndicator : 2;
UINT32 PowerIndicator : 2;
UINT32 PowerController : 1;
UINT32 ElectromechanicalInterlock : 1;
UINT32 DataLinkLayerStateChanged : 1;
UINT32 Reserved : 3;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_SLOT_CONTROL;
typedef union {
struct {
UINT16 AttentionButtonPressed : 1;
UINT16 PowerFaultDetected : 1;
UINT16 MrlSensorChanged : 1;
UINT16 PresenceDetectChanged : 1;
UINT16 CommandCompleted : 1;
UINT16 MrlSensor : 1;
UINT16 PresenceDetect : 1;
UINT16 ElectromechanicalInterlock : 1;
UINT16 DataLinkLayerStateChanged : 1;
UINT16 Reserved : 7;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_SLOT_STATUS;
typedef union {
struct {
UINT16 SystemErrorOnCorrectableError : 1;
UINT16 SystemErrorOnNonFatalError : 1;
UINT16 SystemErrorOnFatalError : 1;
UINT16 PmeInterrupt : 1;
UINT16 CrsSoftwareVisibility : 1;
UINT16 Reserved : 11;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_ROOT_CONTROL;
typedef union {
struct {
UINT16 CrsSoftwareVisibility : 1;
UINT16 Reserved : 15;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_ROOT_CAPABILITY;
typedef union {
struct {
UINT32 PmeRequesterId : 16;
UINT32 PmeStatus : 1;
UINT32 PmePending : 1;
UINT32 Reserved : 14;
} Bits;
UINT32 Uint32;
} PCI_REG_PCIE_ROOT_STATUS;
typedef union {
struct {
UINT32 CompletionTimeoutRanges : 4;
UINT32 CompletionTimeoutDisable : 1;
UINT32 AriForwarding : 1;
UINT32 AtomicOpRouting : 1;
UINT32 AtomicOp32Completer : 1;
UINT32 AtomicOp64Completer : 1;
UINT32 Cas128Completer : 1;
UINT32 NoRoEnabledPrPrPassing : 1;
UINT32 LtrMechanism : 1;
UINT32 TphCompleter : 2;
UINT32 Reserved : 4;
UINT32 Obff : 2;
UINT32 ExtendedFmtField : 1;
UINT32 EndEndTlpPrefix : 1;
UINT32 MaxEndEndTlpPrefixes : 2;
UINT32 Reserved2 : 8;
} Bits;
UINT32 Uint32;
} PCI_REG_PCIE_DEVICE_CAPABILITY2;
#define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0
#define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1
typedef union {
struct {
UINT16 CompletionTimeoutValue : 4;
UINT16 CompletionTimeoutDisable : 1;
UINT16 AriForwarding : 1;
UINT16 AtomicOpRequester : 1;
UINT16 AtomicOpEgressBlocking : 1;
UINT16 IdoRequest : 1;
UINT16 IdoCompletion : 1;
UINT16 LtrMechanism : 2;
UINT16 Reserved : 2;
UINT16 Obff : 2;
UINT16 EndEndTlpPrefixBlocking : 1;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_DEVICE_CONTROL2;
#define PCIE_COMPLETION_TIMEOUT_50US_50MS 0
#define PCIE_COMPLETION_TIMEOUT_50US_100US 1
#define PCIE_COMPLETION_TIMEOUT_1MS_10MS 2
#define PCIE_COMPLETION_TIMEOUT_16MS_55MS 5
#define PCIE_COMPLETION_TIMEOUT_65MS_210MS 6
#define PCIE_COMPLETION_TIMEOUT_260MS_900MS 9
#define PCIE_COMPLETION_TIMEOUT_1S_3_5S 10
#define PCIE_COMPLETION_TIMEOUT_4S_13S 13
#define PCIE_COMPLETION_TIMEOUT_17S_64S 14
#define PCIE_DEVICE_CONTROL_OBFF_DISABLED 0
#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_A 1
#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_B 2
#define PCIE_DEVICE_CONTROL_OBFF_WAKE 3
typedef union {
struct {
UINT32 Reserved : 1;
UINT32 LinkSpeedsVector : 7;
UINT32 Crosslink : 1;
UINT32 Reserved2 : 23;
} Bits;
UINT32 Uint32;
} PCI_REG_PCIE_LINK_CAPABILITY2;
typedef union {
struct {
UINT16 TargetLinkSpeed : 4;
UINT16 EnterCompliance : 1;
UINT16 HardwareAutonomousSpeedDisable : 1;
UINT16 SelectableDeemphasis : 1;
UINT16 TransmitMargin : 3;
UINT16 EnterModifiedCompliance : 1;
UINT16 ComplianceSos : 1;
UINT16 CompliancePresetDeemphasis : 4;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_LINK_CONTROL2;
typedef union {
struct {
UINT16 CurrentDeemphasisLevel : 1;
UINT16 EqualizationComplete : 1;
UINT16 EqualizationPhase1Successful : 1;
UINT16 EqualizationPhase2Successful : 1;
UINT16 EqualizationPhase3Successful : 1;
UINT16 LinkEqualizationRequest : 1;
UINT16 Reserved : 10;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_LINK_STATUS2;
typedef struct {
EFI_PCI_CAPABILITY_HDR Hdr;
PCI_REG_PCIE_CAPABILITY Capability;
PCI_REG_PCIE_DEVICE_CAPABILITY DeviceCapability;
PCI_REG_PCIE_DEVICE_CONTROL DeviceControl;
PCI_REG_PCIE_DEVICE_STATUS DeviceStatus;
PCI_REG_PCIE_LINK_CAPABILITY LinkCapability;
PCI_REG_PCIE_LINK_CONTROL LinkControl;
PCI_REG_PCIE_LINK_STATUS LinkStatus;
PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability;
PCI_REG_PCIE_SLOT_CONTROL SlotControl;
PCI_REG_PCIE_SLOT_STATUS SlotStatus;
PCI_REG_PCIE_ROOT_CONTROL RootControl;
PCI_REG_PCIE_ROOT_CAPABILITY RootCapability;
PCI_REG_PCIE_ROOT_STATUS RootStatus;
PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCapability2;
PCI_REG_PCIE_DEVICE_CONTROL2 DeviceControl2;
UINT16 DeviceStatus2;
PCI_REG_PCIE_LINK_CAPABILITY2 LinkCapability2;
PCI_REG_PCIE_LINK_CONTROL2 LinkControl2;
PCI_REG_PCIE_LINK_STATUS2 LinkStatus2;
UINT32 SlotCapability2;
UINT16 SlotControl2;
UINT16 SlotStatus2;
} PCI_CAPABILITY_PCIEXP;
#define EFI_PCIE_CAPABILITY_BASE_OFFSET 0x100
#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY 0x10
#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET 0x24
#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING 0x20
#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET 0x28
#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING 0x20
//
// for SR-IOV
//
#define EFI_PCIE_CAPABILITY_ID_ARI 0x0E
#define EFI_PCIE_CAPABILITY_ID_ATS 0x0F
#define EFI_PCIE_CAPABILITY_ID_SRIOV 0x10
#define EFI_PCIE_CAPABILITY_ID_MRIOV 0x11
typedef struct {
UINT32 CapabilityHeader;
UINT32 Capability;
UINT16 Control;
UINT16 Status;
UINT16 InitialVFs;
UINT16 TotalVFs;
UINT16 NumVFs;
UINT8 FunctionDependencyLink;
UINT8 Reserved0;
UINT16 FirstVFOffset;
UINT16 VFStride;
UINT16 Reserved1;
UINT16 VFDeviceID;
UINT32 SupportedPageSize;
UINT32 SystemPageSize;
UINT32 VFBar[6];
UINT32 VFMigrationStateArrayOffset;
} SR_IOV_CAPABILITY_REGISTER;
#define EFI_PCIE_CAPABILITY_ID_SRIOV_CAPABILITIES 0x04
#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL 0x08
#define EFI_PCIE_CAPABILITY_ID_SRIOV_STATUS 0x0A
#define EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS 0x0C
#define EFI_PCIE_CAPABILITY_ID_SRIOV_TOTALVFS 0x0E
#define EFI_PCIE_CAPABILITY_ID_SRIOV_NUMVFS 0x10
#define EFI_PCIE_CAPABILITY_ID_SRIOV_FUNCTION_DEPENDENCY_LINK 0x12
#define EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF 0x14
#define EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE 0x16
#define EFI_PCIE_CAPABILITY_ID_SRIOV_VFDEVICEID 0x1A
#define EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE 0x1C
#define EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE 0x20
#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0 0x24
#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR1 0x28
#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR2 0x2C
#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR3 0x30
#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR4 0x34
#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5 0x38
#define EFI_PCIE_CAPABILITY_ID_SRIOV_VF_MIGRATION_STATE 0x3C
typedef struct {
UINT32 CapabilityId:16;
UINT32 CapabilityVersion:4;
UINT32 NextCapabilityOffset:12;
} PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER;
#define PCI_EXP_EXT_HDR PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID 0x0001
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER1 0x1
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER2 0x2
typedef union {
struct {
UINT32 Undefined : 1;
UINT32 Reserved : 3;
UINT32 DataLinkProtocolError : 1;
UINT32 SurpriseDownError : 1;
UINT32 Reserved2 : 6;
UINT32 PoisonedTlp : 1;
UINT32 FlowControlProtocolError : 1;
UINT32 CompletionTimeout : 1;
UINT32 CompleterAbort : 1;
UINT32 UnexpectedCompletion : 1;
UINT32 ReceiverOverflow : 1;
UINT32 MalformedTlp : 1;
UINT32 EcrcError : 1;
UINT32 UnsupportedRequestError : 1;
UINT32 AcsVoilation : 1;
UINT32 UncorrectableInternalError : 1;
UINT32 McBlockedTlp : 1;
UINT32 AtomicOpEgressBlocked : 1;
UINT32 TlpPrefixBlockedError : 1;
UINT32 Reserved3 : 6;
} Bits;
UINT32 Uint32;
} PCI_EXPRESS_REG_UNCORRECTABLE_ERROR;
typedef struct {
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorStatus;
PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorMask;
PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorSeverity;
UINT32 CorrectableErrorStatus;
UINT32 CorrectableErrorMask;
UINT32 AdvancedErrorCapabilitiesAndControl;
UINT32 HeaderLog[4];
UINT32 RootErrorCommand;
UINT32 RootErrorStatus;
UINT16 ErrorSourceIdentification;
UINT16 CorrectableErrorSourceIdentification;
UINT32 TlpPrefixLog[4];
} PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING;
#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID 0x0002
#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_MFVC 0x0009
#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_VER1 0x1
typedef struct {
UINT32 VcResourceCapability:24;
UINT32 PortArbTableOffset:8;
UINT32 VcResourceControl;
UINT16 Reserved1;
UINT16 VcResourceStatus;
} PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC;
typedef struct {
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
UINT32 ExtendedVcCount:3;
UINT32 PortVcCapability1:29;
UINT32 PortVcCapability2:24;
UINT32 VcArbTableOffset:8;
UINT16 PortVcControl;
UINT16 PortVcStatus;
PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC Capability[1];
} PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY;
#define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID 0x0003
#define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_VER1 0x1
typedef struct {
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
UINT64 SerialNumber;
} PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER;
#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID 0x0005
#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_VER1 0x1
typedef struct {
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
UINT32 ElementSelfDescription;
UINT32 Reserved;
UINT32 LinkEntry[1];
} PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION;
#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(LINK_DECLARATION) (UINT8)(((LINK_DECLARATION->ElementSelfDescription)&0x0000ff00)>>8)
#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID 0x0006
#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_VER1 0x1
typedef struct {
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
UINT32 RootComplexLinkCapabilities;
UINT16 RootComplexLinkControl;
UINT16 RootComplexLinkStatus;
} PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL;
#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID 0x0004
#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_VER1 0x1
typedef struct {
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
UINT32 DataSelect:8;
UINT32 Reserved:24;
UINT32 Data;
UINT32 PowerBudgetCapability:1;
UINT32 Reserved2:7;
UINT32 Reserved3:24;
} PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING;
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID 0x000D
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_VER1 0x1
typedef struct {
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
UINT16 AcsCapability;
UINT16 AcsControl;
UINT8 EgressControlVectorArray[1];
} PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED;
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x00000020))
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x0000FF00))
#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID 0x0007
#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_VER1 0x1
typedef struct {
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
UINT32 AssociationBitmap;
} PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION;
#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID 0x0008
#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_VER1 0x1
typedef PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTI_FUNCTION_VIRTUAL_CHANNEL_CAPABILITY;
#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID 0x000B
#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_VER1 0x1
typedef struct {
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
UINT32 VendorSpecificHeader;
UINT8 VendorSpecific[1];
} PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC;
#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(VENDOR) (UINT16)(((VENDOR->VendorSpecificHeader)&0xFFF00000)>>20)
#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID 0x000A
#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_VER1 0x1
typedef struct {
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
UINT16 VendorId;
UINT16 DeviceId;
UINT32 RcrbCapabilities;
UINT32 RcrbControl;
UINT32 Reserved;
} PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER;
#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID 0x0012
#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_VER1 0x1
typedef struct {
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
UINT16 MultiCastCapability;
UINT16 MulticastControl;
UINT64 McBaseAddress;
UINT64 McReceiveAddress;
UINT64 McBlockAll;
UINT64 McBlockUntranslated;
UINT64 McOverlayBar;
} PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST;
#define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID 0x0015
#define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_VER1 0x1
typedef struct {
UINT32 ResizableBarCapability;
UINT16 ResizableBarControl;
UINT16 Reserved;
} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY;
typedef struct {
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY Capability[1];
} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR;
#define GET_NUMBER_RESIZABLE_BARS(x) (((x->Capability[0].ResizableBarControl) & 0xE0) >> 5)
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID 0x000E
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_VER1 0x1
typedef struct {
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
UINT16 AriCapability;
UINT16 AriControl;
} PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY;
#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID 0x0016
#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_VER1 0x1
typedef struct {
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
UINT32 DpaCapability;
UINT32 DpaLatencyIndicator;
UINT16 DpaStatus;
UINT16 DpaControl;
UINT8 DpaPowerAllocationArray[1];
} PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION;
#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(POWER) (UINT16)(((POWER->DpaCapability)&0x0000000F))
#define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID 0x0018
#define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_VER1 0x1
typedef struct {
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
UINT16 MaxSnoopLatency;
UINT16 MaxNoSnoopLatency;
} PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING;
#define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID 0x0017
#define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_VER1 0x1
typedef struct {
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
UINT32 TphRequesterCapability;
UINT32 TphRequesterControl;
UINT16 TphStTable[1];
} PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH;
#define GET_TPH_TABLE_SIZE(x) ((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16)
#pragma pack()
#endif

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/** @file
Support for the PCI Express 3.0 standard.
This header file may not define all structures. Please extend as required.
Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _PCIEXPRESS30_H_
#define _PCIEXPRESS30_H_
#include <IndustryStandard/PciExpress21.h>
#pragma pack(1)
#define PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID 0x0019
#define PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_VER1 0x1
typedef union {
struct {
UINT32 PerformEqualization : 1;
UINT32 LinkEqualizationRequestInterruptEnable : 1;
UINT32 Reserved : 30;
} Bits;
UINT32 Uint32;
} PCI_EXPRESS_REG_LINK_CONTROL3;
typedef union {
struct {
UINT16 DownstreamPortTransmitterPreset : 4;
UINT16 DownstreamPortReceiverPresetHint : 3;
UINT16 Reserved : 1;
UINT16 UpstreamPortTransmitterPreset : 4;
UINT16 UpstreamPortReceiverPresetHint : 3;
UINT16 Reserved2 : 1;
} Bits;
UINT16 Uint16;
} PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL;
typedef struct {
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
PCI_EXPRESS_REG_LINK_CONTROL3 LinkControl3;
UINT32 LaneErrorStatus;
PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL EqualizationControl[2];
} PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE;
#pragma pack()
#endif

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/** @file
Support for the PCI Express 3.1 standard.
This header file may not define all structures. Please extend as required.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _PCIEXPRESS31_H_
#define _PCIEXPRESS31_H_
#include <IndustryStandard/PciExpress30.h>
#pragma pack(1)
#define PCI_EXPRESS_EXTENDED_CAPABILITY_L1_PM_SUBSTATES_ID 0x001E
#define PCI_EXPRESS_EXTENDED_CAPABILITY_L1_PM_SUBSTATES_VER1 0x1
typedef union {
struct {
UINT32 PciPmL12 : 1;
UINT32 PciPmL11 : 1;
UINT32 AspmL12 : 1;
UINT32 AspmL11 : 1;
UINT32 L1PmSubstates : 1;
UINT32 Reserved : 3;
UINT32 CommonModeRestoreTime : 8;
UINT32 TPowerOnScale : 2;
UINT32 Reserved2 : 1;
UINT32 TPowerOnValue : 5;
UINT32 Reserved3 : 8;
} Bits;
UINT32 Uint32;
} PCI_EXPRESS_REG_L1_PM_SUBSTATES_CAPABILITY;
typedef union {
struct {
UINT32 PciPmL12 : 1;
UINT32 PciPmL11 : 1;
UINT32 AspmL12 : 1;
UINT32 AspmL11 : 1;
UINT32 Reserved : 4;
UINT32 CommonModeRestoreTime : 8;
UINT32 LtrL12ThresholdValue : 10;
UINT32 Reserved2 : 3;
UINT32 LtrL12ThresholdScale : 3;
} Bits;
UINT32 Uint32;
} PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL1;
typedef union {
struct {
UINT32 TPowerOnScale : 2;
UINT32 Reserved : 1;
UINT32 TPowerOnValue : 5;
UINT32 Reserved2 : 24;
} Bits;
UINT32 Uint32;
} PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL2;
typedef struct {
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
PCI_EXPRESS_REG_L1_PM_SUBSTATES_CAPABILITY Capability;
PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL1 Control1;
PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL2 Control2;
} PCI_EXPRESS_EXTENDED_CAPABILITIES_L1_PM_SUBSTATES;
#pragma pack()
#endif

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/** @file
EFI image format for PE32, PE32+ and TE. Please note some data structures are
different for PE32 and PE32+. EFI_IMAGE_NT_HEADERS32 is for PE32 and
EFI_IMAGE_NT_HEADERS64 is for PE32+.
This file is coded to the Visual Studio, Microsoft Portable Executable and
Common Object File Format Specification, Revision 8.3 - February 6, 2013.
This file also includes some definitions in PI Specification, Revision 1.0.
Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __PE_IMAGE_H__
#define __PE_IMAGE_H__
//
// PE32+ Subsystem type for EFI images
//
#define EFI_IMAGE_SUBSYSTEM_EFI_APPLICATION 10
#define EFI_IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER 11
#define EFI_IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER 12
#define EFI_IMAGE_SUBSYSTEM_SAL_RUNTIME_DRIVER 13 ///< defined PI Specification, 1.0
//
// PE32+ Machine type for EFI images
//
#define IMAGE_FILE_MACHINE_I386 0x014c
#define IMAGE_FILE_MACHINE_IA64 0x0200
#define IMAGE_FILE_MACHINE_EBC 0x0EBC
#define IMAGE_FILE_MACHINE_X64 0x8664
#define IMAGE_FILE_MACHINE_ARMTHUMB_MIXED 0x01c2
#define IMAGE_FILE_MACHINE_ARM64 0xAA64
//
// EXE file formats
//
#define EFI_IMAGE_DOS_SIGNATURE SIGNATURE_16('M', 'Z')
#define EFI_IMAGE_OS2_SIGNATURE SIGNATURE_16('N', 'E')
#define EFI_IMAGE_OS2_SIGNATURE_LE SIGNATURE_16('L', 'E')
#define EFI_IMAGE_NT_SIGNATURE SIGNATURE_32('P', 'E', '\0', '\0')
///
/// PE images can start with an optional DOS header, so if an image is run
/// under DOS it can print an error message.
///
typedef struct {
UINT16 e_magic; ///< Magic number.
UINT16 e_cblp; ///< Bytes on last page of file.
UINT16 e_cp; ///< Pages in file.
UINT16 e_crlc; ///< Relocations.
UINT16 e_cparhdr; ///< Size of header in paragraphs.
UINT16 e_minalloc; ///< Minimum extra paragraphs needed.
UINT16 e_maxalloc; ///< Maximum extra paragraphs needed.
UINT16 e_ss; ///< Initial (relative) SS value.
UINT16 e_sp; ///< Initial SP value.
UINT16 e_csum; ///< Checksum.
UINT16 e_ip; ///< Initial IP value.
UINT16 e_cs; ///< Initial (relative) CS value.
UINT16 e_lfarlc; ///< File address of relocation table.
UINT16 e_ovno; ///< Overlay number.
UINT16 e_res[4]; ///< Reserved words.
UINT16 e_oemid; ///< OEM identifier (for e_oeminfo).
UINT16 e_oeminfo; ///< OEM information; e_oemid specific.
UINT16 e_res2[10]; ///< Reserved words.
UINT32 e_lfanew; ///< File address of new exe header.
} EFI_IMAGE_DOS_HEADER;
///
/// COFF File Header (Object and Image).
///
typedef struct {
UINT16 Machine;
UINT16 NumberOfSections;
UINT32 TimeDateStamp;
UINT32 PointerToSymbolTable;
UINT32 NumberOfSymbols;
UINT16 SizeOfOptionalHeader;
UINT16 Characteristics;
} EFI_IMAGE_FILE_HEADER;
///
/// Size of EFI_IMAGE_FILE_HEADER.
///
#define EFI_IMAGE_SIZEOF_FILE_HEADER 20
//
// Characteristics
//
#define EFI_IMAGE_FILE_RELOCS_STRIPPED BIT0 ///< 0x0001 Relocation info stripped from file.
#define EFI_IMAGE_FILE_EXECUTABLE_IMAGE BIT1 ///< 0x0002 File is executable (i.e. no unresolved externel references).
#define EFI_IMAGE_FILE_LINE_NUMS_STRIPPED BIT2 ///< 0x0004 Line nunbers stripped from file.
#define EFI_IMAGE_FILE_LOCAL_SYMS_STRIPPED BIT3 ///< 0x0008 Local symbols stripped from file.
#define EFI_IMAGE_FILE_BYTES_REVERSED_LO BIT7 ///< 0x0080 Bytes of machine word are reversed.
#define EFI_IMAGE_FILE_32BIT_MACHINE BIT8 ///< 0x0100 32 bit word machine.
#define EFI_IMAGE_FILE_DEBUG_STRIPPED BIT9 ///< 0x0200 Debugging info stripped from file in .DBG file.
#define EFI_IMAGE_FILE_SYSTEM BIT12 ///< 0x1000 System File.
#define EFI_IMAGE_FILE_DLL BIT13 ///< 0x2000 File is a DLL.
#define EFI_IMAGE_FILE_BYTES_REVERSED_HI BIT15 ///< 0x8000 Bytes of machine word are reversed.
///
/// Header Data Directories.
///
typedef struct {
UINT32 VirtualAddress;
UINT32 Size;
} EFI_IMAGE_DATA_DIRECTORY;
//
// Directory Entries
//
#define EFI_IMAGE_DIRECTORY_ENTRY_EXPORT 0
#define EFI_IMAGE_DIRECTORY_ENTRY_IMPORT 1
#define EFI_IMAGE_DIRECTORY_ENTRY_RESOURCE 2
#define EFI_IMAGE_DIRECTORY_ENTRY_EXCEPTION 3
#define EFI_IMAGE_DIRECTORY_ENTRY_SECURITY 4
#define EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC 5
#define EFI_IMAGE_DIRECTORY_ENTRY_DEBUG 6
#define EFI_IMAGE_DIRECTORY_ENTRY_COPYRIGHT 7
#define EFI_IMAGE_DIRECTORY_ENTRY_GLOBALPTR 8
#define EFI_IMAGE_DIRECTORY_ENTRY_TLS 9
#define EFI_IMAGE_DIRECTORY_ENTRY_LOAD_CONFIG 10
#define EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES 16
///
/// @attention
/// EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC means PE32 and
/// EFI_IMAGE_OPTIONAL_HEADER32 must be used. The data structures only vary
/// after NT additional fields.
///
#define EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC 0x10b
///
/// Optional Header Standard Fields for PE32.
///
typedef struct {
///
/// Standard fields.
///
UINT16 Magic;
UINT8 MajorLinkerVersion;
UINT8 MinorLinkerVersion;
UINT32 SizeOfCode;
UINT32 SizeOfInitializedData;
UINT32 SizeOfUninitializedData;
UINT32 AddressOfEntryPoint;
UINT32 BaseOfCode;
UINT32 BaseOfData; ///< PE32 contains this additional field, which is absent in PE32+.
///
/// Optional Header Windows-Specific Fields.
///
UINT32 ImageBase;
UINT32 SectionAlignment;
UINT32 FileAlignment;
UINT16 MajorOperatingSystemVersion;
UINT16 MinorOperatingSystemVersion;
UINT16 MajorImageVersion;
UINT16 MinorImageVersion;
UINT16 MajorSubsystemVersion;
UINT16 MinorSubsystemVersion;
UINT32 Win32VersionValue;
UINT32 SizeOfImage;
UINT32 SizeOfHeaders;
UINT32 CheckSum;
UINT16 Subsystem;
UINT16 DllCharacteristics;
UINT32 SizeOfStackReserve;
UINT32 SizeOfStackCommit;
UINT32 SizeOfHeapReserve;
UINT32 SizeOfHeapCommit;
UINT32 LoaderFlags;
UINT32 NumberOfRvaAndSizes;
EFI_IMAGE_DATA_DIRECTORY DataDirectory[EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES];
} EFI_IMAGE_OPTIONAL_HEADER32;
///
/// @attention
/// EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC means PE32+ and
/// EFI_IMAGE_OPTIONAL_HEADER64 must be used. The data structures only vary
/// after NT additional fields.
///
#define EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC 0x20b
///
/// Optional Header Standard Fields for PE32+.
///
typedef struct {
///
/// Standard fields.
///
UINT16 Magic;
UINT8 MajorLinkerVersion;
UINT8 MinorLinkerVersion;
UINT32 SizeOfCode;
UINT32 SizeOfInitializedData;
UINT32 SizeOfUninitializedData;
UINT32 AddressOfEntryPoint;
UINT32 BaseOfCode;
///
/// Optional Header Windows-Specific Fields.
///
UINT64 ImageBase;
UINT32 SectionAlignment;
UINT32 FileAlignment;
UINT16 MajorOperatingSystemVersion;
UINT16 MinorOperatingSystemVersion;
UINT16 MajorImageVersion;
UINT16 MinorImageVersion;
UINT16 MajorSubsystemVersion;
UINT16 MinorSubsystemVersion;
UINT32 Win32VersionValue;
UINT32 SizeOfImage;
UINT32 SizeOfHeaders;
UINT32 CheckSum;
UINT16 Subsystem;
UINT16 DllCharacteristics;
UINT64 SizeOfStackReserve;
UINT64 SizeOfStackCommit;
UINT64 SizeOfHeapReserve;
UINT64 SizeOfHeapCommit;
UINT32 LoaderFlags;
UINT32 NumberOfRvaAndSizes;
EFI_IMAGE_DATA_DIRECTORY DataDirectory[EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES];
} EFI_IMAGE_OPTIONAL_HEADER64;
///
/// @attention
/// EFI_IMAGE_NT_HEADERS32 is for use ONLY by tools.
///
typedef struct {
UINT32 Signature;
EFI_IMAGE_FILE_HEADER FileHeader;
EFI_IMAGE_OPTIONAL_HEADER32 OptionalHeader;
} EFI_IMAGE_NT_HEADERS32;
#define EFI_IMAGE_SIZEOF_NT_OPTIONAL32_HEADER sizeof (EFI_IMAGE_NT_HEADERS32)
///
/// @attention
/// EFI_IMAGE_HEADERS64 is for use ONLY by tools.
///
typedef struct {
UINT32 Signature;
EFI_IMAGE_FILE_HEADER FileHeader;
EFI_IMAGE_OPTIONAL_HEADER64 OptionalHeader;
} EFI_IMAGE_NT_HEADERS64;
#define EFI_IMAGE_SIZEOF_NT_OPTIONAL64_HEADER sizeof (EFI_IMAGE_NT_HEADERS64)
//
// Other Windows Subsystem Values
//
#define EFI_IMAGE_SUBSYSTEM_UNKNOWN 0
#define EFI_IMAGE_SUBSYSTEM_NATIVE 1
#define EFI_IMAGE_SUBSYSTEM_WINDOWS_GUI 2
#define EFI_IMAGE_SUBSYSTEM_WINDOWS_CUI 3
#define EFI_IMAGE_SUBSYSTEM_OS2_CUI 5
#define EFI_IMAGE_SUBSYSTEM_POSIX_CUI 7
///
/// Length of ShortName.
///
#define EFI_IMAGE_SIZEOF_SHORT_NAME 8
///
/// Section Table. This table immediately follows the optional header.
///
typedef struct {
UINT8 Name[EFI_IMAGE_SIZEOF_SHORT_NAME];
union {
UINT32 PhysicalAddress;
UINT32 VirtualSize;
} Misc;
UINT32 VirtualAddress;
UINT32 SizeOfRawData;
UINT32 PointerToRawData;
UINT32 PointerToRelocations;
UINT32 PointerToLinenumbers;
UINT16 NumberOfRelocations;
UINT16 NumberOfLinenumbers;
UINT32 Characteristics;
} EFI_IMAGE_SECTION_HEADER;
///
/// Size of EFI_IMAGE_SECTION_HEADER.
///
#define EFI_IMAGE_SIZEOF_SECTION_HEADER 40
//
// Section Flags Values
//
#define EFI_IMAGE_SCN_TYPE_NO_PAD BIT3 ///< 0x00000008 ///< Reserved.
#define EFI_IMAGE_SCN_CNT_CODE BIT5 ///< 0x00000020
#define EFI_IMAGE_SCN_CNT_INITIALIZED_DATA BIT6 ///< 0x00000040
#define EFI_IMAGE_SCN_CNT_UNINITIALIZED_DATA BIT7 ///< 0x00000080
#define EFI_IMAGE_SCN_LNK_OTHER BIT8 ///< 0x00000100 ///< Reserved.
#define EFI_IMAGE_SCN_LNK_INFO BIT9 ///< 0x00000200 ///< Section contains comments or some other type of information.
#define EFI_IMAGE_SCN_LNK_REMOVE BIT11 ///< 0x00000800 ///< Section contents will not become part of image.
#define EFI_IMAGE_SCN_LNK_COMDAT BIT12 ///< 0x00001000
#define EFI_IMAGE_SCN_ALIGN_1BYTES BIT20 ///< 0x00100000
#define EFI_IMAGE_SCN_ALIGN_2BYTES BIT21 ///< 0x00200000
#define EFI_IMAGE_SCN_ALIGN_4BYTES (BIT20|BIT21) ///< 0x00300000
#define EFI_IMAGE_SCN_ALIGN_8BYTES BIT22 ///< 0x00400000
#define EFI_IMAGE_SCN_ALIGN_16BYTES (BIT20|BIT22) ///< 0x00500000
#define EFI_IMAGE_SCN_ALIGN_32BYTES (BIT21|BIT22) ///< 0x00600000
#define EFI_IMAGE_SCN_ALIGN_64BYTES (BIT20|BIT21|BIT22) ///< 0x00700000
#define EFI_IMAGE_SCN_MEM_DISCARDABLE BIT25 ///< 0x02000000
#define EFI_IMAGE_SCN_MEM_NOT_CACHED BIT26 ///< 0x04000000
#define EFI_IMAGE_SCN_MEM_NOT_PAGED BIT27 ///< 0x08000000
#define EFI_IMAGE_SCN_MEM_SHARED BIT28 ///< 0x10000000
#define EFI_IMAGE_SCN_MEM_EXECUTE BIT29 ///< 0x20000000
#define EFI_IMAGE_SCN_MEM_READ BIT30 ///< 0x40000000
#define EFI_IMAGE_SCN_MEM_WRITE BIT31 ///< 0x80000000
///
/// Size of a Symbol Table Record.
///
#define EFI_IMAGE_SIZEOF_SYMBOL 18
//
// Symbols have a section number of the section in which they are
// defined. Otherwise, section numbers have the following meanings:
//
#define EFI_IMAGE_SYM_UNDEFINED (UINT16) 0 ///< Symbol is undefined or is common.
#define EFI_IMAGE_SYM_ABSOLUTE (UINT16) -1 ///< Symbol is an absolute value.
#define EFI_IMAGE_SYM_DEBUG (UINT16) -2 ///< Symbol is a special debug item.
//
// Symbol Type (fundamental) values.
//
#define EFI_IMAGE_SYM_TYPE_NULL 0 ///< no type.
#define EFI_IMAGE_SYM_TYPE_VOID 1 ///< no valid type.
#define EFI_IMAGE_SYM_TYPE_CHAR 2 ///< type character.
#define EFI_IMAGE_SYM_TYPE_SHORT 3 ///< type short integer.
#define EFI_IMAGE_SYM_TYPE_INT 4
#define EFI_IMAGE_SYM_TYPE_LONG 5
#define EFI_IMAGE_SYM_TYPE_FLOAT 6
#define EFI_IMAGE_SYM_TYPE_DOUBLE 7
#define EFI_IMAGE_SYM_TYPE_STRUCT 8
#define EFI_IMAGE_SYM_TYPE_UNION 9
#define EFI_IMAGE_SYM_TYPE_ENUM 10 ///< enumeration.
#define EFI_IMAGE_SYM_TYPE_MOE 11 ///< member of enumeration.
#define EFI_IMAGE_SYM_TYPE_BYTE 12
#define EFI_IMAGE_SYM_TYPE_WORD 13
#define EFI_IMAGE_SYM_TYPE_UINT 14
#define EFI_IMAGE_SYM_TYPE_DWORD 15
//
// Symbol Type (derived) values.
//
#define EFI_IMAGE_SYM_DTYPE_NULL 0 ///< no derived type.
#define EFI_IMAGE_SYM_DTYPE_POINTER 1
#define EFI_IMAGE_SYM_DTYPE_FUNCTION 2
#define EFI_IMAGE_SYM_DTYPE_ARRAY 3
//
// Storage classes.
//
#define EFI_IMAGE_SYM_CLASS_END_OF_FUNCTION ((UINT8) -1)
#define EFI_IMAGE_SYM_CLASS_NULL 0
#define EFI_IMAGE_SYM_CLASS_AUTOMATIC 1
#define EFI_IMAGE_SYM_CLASS_EXTERNAL 2
#define EFI_IMAGE_SYM_CLASS_STATIC 3
#define EFI_IMAGE_SYM_CLASS_REGISTER 4
#define EFI_IMAGE_SYM_CLASS_EXTERNAL_DEF 5
#define EFI_IMAGE_SYM_CLASS_LABEL 6
#define EFI_IMAGE_SYM_CLASS_UNDEFINED_LABEL 7
#define EFI_IMAGE_SYM_CLASS_MEMBER_OF_STRUCT 8
#define EFI_IMAGE_SYM_CLASS_ARGUMENT 9
#define EFI_IMAGE_SYM_CLASS_STRUCT_TAG 10
#define EFI_IMAGE_SYM_CLASS_MEMBER_OF_UNION 11
#define EFI_IMAGE_SYM_CLASS_UNION_TAG 12
#define EFI_IMAGE_SYM_CLASS_TYPE_DEFINITION 13
#define EFI_IMAGE_SYM_CLASS_UNDEFINED_STATIC 14
#define EFI_IMAGE_SYM_CLASS_ENUM_TAG 15
#define EFI_IMAGE_SYM_CLASS_MEMBER_OF_ENUM 16
#define EFI_IMAGE_SYM_CLASS_REGISTER_PARAM 17
#define EFI_IMAGE_SYM_CLASS_BIT_FIELD 18
#define EFI_IMAGE_SYM_CLASS_BLOCK 100
#define EFI_IMAGE_SYM_CLASS_FUNCTION 101
#define EFI_IMAGE_SYM_CLASS_END_OF_STRUCT 102
#define EFI_IMAGE_SYM_CLASS_FILE 103
#define EFI_IMAGE_SYM_CLASS_SECTION 104
#define EFI_IMAGE_SYM_CLASS_WEAK_EXTERNAL 105
//
// type packing constants
//
#define EFI_IMAGE_N_BTMASK 017
#define EFI_IMAGE_N_TMASK 060
#define EFI_IMAGE_N_TMASK1 0300
#define EFI_IMAGE_N_TMASK2 0360
#define EFI_IMAGE_N_BTSHFT 4
#define EFI_IMAGE_N_TSHIFT 2
//
// Communal selection types.
//
#define EFI_IMAGE_COMDAT_SELECT_NODUPLICATES 1
#define EFI_IMAGE_COMDAT_SELECT_ANY 2
#define EFI_IMAGE_COMDAT_SELECT_SAME_SIZE 3
#define EFI_IMAGE_COMDAT_SELECT_EXACT_MATCH 4
#define EFI_IMAGE_COMDAT_SELECT_ASSOCIATIVE 5
//
// the following values only be referred in PeCoff, not defined in PECOFF.
//
#define EFI_IMAGE_WEAK_EXTERN_SEARCH_NOLIBRARY 1
#define EFI_IMAGE_WEAK_EXTERN_SEARCH_LIBRARY 2
#define EFI_IMAGE_WEAK_EXTERN_SEARCH_ALIAS 3
///
/// Relocation format.
///
typedef struct {
UINT32 VirtualAddress;
UINT32 SymbolTableIndex;
UINT16 Type;
} EFI_IMAGE_RELOCATION;
///
/// Size of EFI_IMAGE_RELOCATION
///
#define EFI_IMAGE_SIZEOF_RELOCATION 10
//
// I386 relocation types.
//
#define EFI_IMAGE_REL_I386_ABSOLUTE 0x0000 ///< Reference is absolute, no relocation is necessary.
#define EFI_IMAGE_REL_I386_DIR16 0x0001 ///< Direct 16-bit reference to the symbols virtual address.
#define EFI_IMAGE_REL_I386_REL16 0x0002 ///< PC-relative 16-bit reference to the symbols virtual address.
#define EFI_IMAGE_REL_I386_DIR32 0x0006 ///< Direct 32-bit reference to the symbols virtual address.
#define EFI_IMAGE_REL_I386_DIR32NB 0x0007 ///< Direct 32-bit reference to the symbols virtual address, base not included.
#define EFI_IMAGE_REL_I386_SEG12 0x0009 ///< Direct 16-bit reference to the segment-selector bits of a 32-bit virtual address.
#define EFI_IMAGE_REL_I386_SECTION 0x000A
#define EFI_IMAGE_REL_I386_SECREL 0x000B
#define EFI_IMAGE_REL_I386_REL32 0x0014 ///< PC-relative 32-bit reference to the symbols virtual address.
//
// x64 processor relocation types.
//
#define IMAGE_REL_AMD64_ABSOLUTE 0x0000
#define IMAGE_REL_AMD64_ADDR64 0x0001
#define IMAGE_REL_AMD64_ADDR32 0x0002
#define IMAGE_REL_AMD64_ADDR32NB 0x0003
#define IMAGE_REL_AMD64_REL32 0x0004
#define IMAGE_REL_AMD64_REL32_1 0x0005
#define IMAGE_REL_AMD64_REL32_2 0x0006
#define IMAGE_REL_AMD64_REL32_3 0x0007
#define IMAGE_REL_AMD64_REL32_4 0x0008
#define IMAGE_REL_AMD64_REL32_5 0x0009
#define IMAGE_REL_AMD64_SECTION 0x000A
#define IMAGE_REL_AMD64_SECREL 0x000B
#define IMAGE_REL_AMD64_SECREL7 0x000C
#define IMAGE_REL_AMD64_TOKEN 0x000D
#define IMAGE_REL_AMD64_SREL32 0x000E
#define IMAGE_REL_AMD64_PAIR 0x000F
#define IMAGE_REL_AMD64_SSPAN32 0x0010
///
/// Based relocation format.
///
typedef struct {
UINT32 VirtualAddress;
UINT32 SizeOfBlock;
} EFI_IMAGE_BASE_RELOCATION;
///
/// Size of EFI_IMAGE_BASE_RELOCATION.
///
#define EFI_IMAGE_SIZEOF_BASE_RELOCATION 8
//
// Based relocation types.
//
#define EFI_IMAGE_REL_BASED_ABSOLUTE 0
#define EFI_IMAGE_REL_BASED_HIGH 1
#define EFI_IMAGE_REL_BASED_LOW 2
#define EFI_IMAGE_REL_BASED_HIGHLOW 3
#define EFI_IMAGE_REL_BASED_HIGHADJ 4
#define EFI_IMAGE_REL_BASED_MIPS_JMPADDR 5
#define EFI_IMAGE_REL_BASED_ARM_MOV32A 5
#define EFI_IMAGE_REL_BASED_ARM_MOV32T 7
#define EFI_IMAGE_REL_BASED_IA64_IMM64 9
#define EFI_IMAGE_REL_BASED_MIPS_JMPADDR16 9
#define EFI_IMAGE_REL_BASED_DIR64 10
///
/// Line number format.
///
typedef struct {
union {
UINT32 SymbolTableIndex; ///< Symbol table index of function name if Linenumber is 0.
UINT32 VirtualAddress; ///< Virtual address of line number.
} Type;
UINT16 Linenumber; ///< Line number.
} EFI_IMAGE_LINENUMBER;
///
/// Size of EFI_IMAGE_LINENUMBER.
///
#define EFI_IMAGE_SIZEOF_LINENUMBER 6
//
// Archive format.
//
#define EFI_IMAGE_ARCHIVE_START_SIZE 8
#define EFI_IMAGE_ARCHIVE_START "!<arch>\n"
#define EFI_IMAGE_ARCHIVE_END "`\n"
#define EFI_IMAGE_ARCHIVE_PAD "\n"
#define EFI_IMAGE_ARCHIVE_LINKER_MEMBER "/ "
#define EFI_IMAGE_ARCHIVE_LONGNAMES_MEMBER "// "
///
/// Archive Member Headers
///
typedef struct {
UINT8 Name[16]; ///< File member name - `/' terminated.
UINT8 Date[12]; ///< File member date - decimal.
UINT8 UserID[6]; ///< File member user id - decimal.
UINT8 GroupID[6]; ///< File member group id - decimal.
UINT8 Mode[8]; ///< File member mode - octal.
UINT8 Size[10]; ///< File member size - decimal.
UINT8 EndHeader[2]; ///< String to end header. (0x60 0x0A).
} EFI_IMAGE_ARCHIVE_MEMBER_HEADER;
///
/// Size of EFI_IMAGE_ARCHIVE_MEMBER_HEADER.
///
#define EFI_IMAGE_SIZEOF_ARCHIVE_MEMBER_HDR 60
//
// DLL Support
//
///
/// Export Directory Table.
///
typedef struct {
UINT32 Characteristics;
UINT32 TimeDateStamp;
UINT16 MajorVersion;
UINT16 MinorVersion;
UINT32 Name;
UINT32 Base;
UINT32 NumberOfFunctions;
UINT32 NumberOfNames;
UINT32 AddressOfFunctions;
UINT32 AddressOfNames;
UINT32 AddressOfNameOrdinals;
} EFI_IMAGE_EXPORT_DIRECTORY;
///
/// Hint/Name Table.
///
typedef struct {
UINT16 Hint;
UINT8 Name[1];
} EFI_IMAGE_IMPORT_BY_NAME;
///
/// Import Address Table RVA (Thunk Table).
///
typedef struct {
union {
UINT32 Function;
UINT32 Ordinal;
EFI_IMAGE_IMPORT_BY_NAME *AddressOfData;
} u1;
} EFI_IMAGE_THUNK_DATA;
#define EFI_IMAGE_ORDINAL_FLAG BIT31 ///< Flag for PE32.
#define EFI_IMAGE_SNAP_BY_ORDINAL(Ordinal) ((Ordinal & EFI_IMAGE_ORDINAL_FLAG) != 0)
#define EFI_IMAGE_ORDINAL(Ordinal) (Ordinal & 0xffff)
///
/// Import Directory Table
///
typedef struct {
UINT32 Characteristics;
UINT32 TimeDateStamp;
UINT32 ForwarderChain;
UINT32 Name;
EFI_IMAGE_THUNK_DATA *FirstThunk;
} EFI_IMAGE_IMPORT_DESCRIPTOR;
///
/// Debug Directory Format.
///
typedef struct {
UINT32 Characteristics;
UINT32 TimeDateStamp;
UINT16 MajorVersion;
UINT16 MinorVersion;
UINT32 Type;
UINT32 SizeOfData;
UINT32 RVA; ///< The address of the debug data when loaded, relative to the image base.
UINT32 FileOffset; ///< The file pointer to the debug data.
} EFI_IMAGE_DEBUG_DIRECTORY_ENTRY;
#define EFI_IMAGE_DEBUG_TYPE_CODEVIEW 2 ///< The Visual C++ debug information.
///
/// Debug Data Structure defined in Microsoft C++.
///
#define CODEVIEW_SIGNATURE_NB10 SIGNATURE_32('N', 'B', '1', '0')
typedef struct {
UINT32 Signature; ///< "NB10"
UINT32 Unknown;
UINT32 Unknown2;
UINT32 Unknown3;
//
// Filename of .PDB goes here
//
} EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY;
///
/// Debug Data Structure defined in Microsoft C++.
///
#define CODEVIEW_SIGNATURE_RSDS SIGNATURE_32('R', 'S', 'D', 'S')
typedef struct {
UINT32 Signature; ///< "RSDS".
UINT32 Unknown;
UINT32 Unknown2;
UINT32 Unknown3;
UINT32 Unknown4;
UINT32 Unknown5;
//
// Filename of .PDB goes here
//
} EFI_IMAGE_DEBUG_CODEVIEW_RSDS_ENTRY;
///
/// Debug Data Structure defined by Apple Mach-O to Coff utility.
///
#define CODEVIEW_SIGNATURE_MTOC SIGNATURE_32('M', 'T', 'O', 'C')
typedef struct {
UINT32 Signature; ///< "MTOC".
GUID MachOUuid;
//
// Filename of .DLL (Mach-O with debug info) goes here
//
} EFI_IMAGE_DEBUG_CODEVIEW_MTOC_ENTRY;
///
/// Resource format.
///
typedef struct {
UINT32 Characteristics;
UINT32 TimeDateStamp;
UINT16 MajorVersion;
UINT16 MinorVersion;
UINT16 NumberOfNamedEntries;
UINT16 NumberOfIdEntries;
//
// Array of EFI_IMAGE_RESOURCE_DIRECTORY_ENTRY entries goes here.
//
} EFI_IMAGE_RESOURCE_DIRECTORY;
///
/// Resource directory entry format.
///
typedef struct {
union {
struct {
UINT32 NameOffset:31;
UINT32 NameIsString:1;
} s;
UINT32 Id;
} u1;
union {
UINT32 OffsetToData;
struct {
UINT32 OffsetToDirectory:31;
UINT32 DataIsDirectory:1;
} s;
} u2;
} EFI_IMAGE_RESOURCE_DIRECTORY_ENTRY;
///
/// Resource directory entry for string.
///
typedef struct {
UINT16 Length;
CHAR16 String[1];
} EFI_IMAGE_RESOURCE_DIRECTORY_STRING;
///
/// Resource directory entry for data array.
///
typedef struct {
UINT32 OffsetToData;
UINT32 Size;
UINT32 CodePage;
UINT32 Reserved;
} EFI_IMAGE_RESOURCE_DATA_ENTRY;
///
/// Header format for TE images, defined in the PI Specification, 1.0.
///
typedef struct {
UINT16 Signature; ///< The signature for TE format = "VZ".
UINT16 Machine; ///< From the original file header.
UINT8 NumberOfSections; ///< From the original file header.
UINT8 Subsystem; ///< From original optional header.
UINT16 StrippedSize; ///< Number of bytes we removed from the header.
UINT32 AddressOfEntryPoint; ///< Offset to entry point -- from original optional header.
UINT32 BaseOfCode; ///< From original image -- required for ITP debug.
UINT64 ImageBase; ///< From original file header.
EFI_IMAGE_DATA_DIRECTORY DataDirectory[2]; ///< Only base relocation and debug directory.
} EFI_TE_IMAGE_HEADER;
#define EFI_TE_IMAGE_HEADER_SIGNATURE SIGNATURE_16('V', 'Z')
//
// Data directory indexes in our TE image header
//
#define EFI_TE_IMAGE_DIRECTORY_ENTRY_BASERELOC 0
#define EFI_TE_IMAGE_DIRECTORY_ENTRY_DEBUG 1
///
/// Union of PE32, PE32+, and TE headers.
///
typedef union {
EFI_IMAGE_NT_HEADERS32 Pe32;
EFI_IMAGE_NT_HEADERS64 Pe32Plus;
EFI_TE_IMAGE_HEADER Te;
} EFI_IMAGE_OPTIONAL_HEADER_UNION;
typedef union {
EFI_IMAGE_NT_HEADERS32 *Pe32;
EFI_IMAGE_NT_HEADERS64 *Pe32Plus;
EFI_TE_IMAGE_HEADER *Te;
EFI_IMAGE_OPTIONAL_HEADER_UNION *Union;
} EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION;
#endif

915
MdePkg/Include/IndustryStandard/Sal.h Normal file
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@ -0,0 +1,915 @@
/** @file
Main SAL API's defined in Intel Itanium Processor Family System Abstraction
Layer Specification Revision 3.2 (December 2003)
Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __SAL_API_H__
#define __SAL_API_H__
///
/// SAL return status type
///
typedef INTN EFI_SAL_STATUS;
///
/// Call completed without error.
///
#define EFI_SAL_SUCCESS ((EFI_SAL_STATUS) 0)
///
/// Call completed without error, but some information was lost due to overflow.
///
#define EFI_SAL_OVERFLOW ((EFI_SAL_STATUS) 1)
///
/// Call completed without error; effect a warm boot of the system to complete the update.
///
#define EFI_SAL_WARM_BOOT_NEEDED ((EFI_SAL_STATUS) 2)
///
/// More information is available for retrieval.
///
#define EFI_SAL_MORE_RECORDS ((EFI_SAL_STATUS) 3)
///
/// Not implemented.
///
#define EFI_SAL_NOT_IMPLEMENTED ((EFI_SAL_STATUS) - 1)
///
/// Invalid Argument.
///
#define EFI_SAL_INVALID_ARGUMENT ((EFI_SAL_STATUS) - 2)
///
/// Call completed without error.
///
#define EFI_SAL_ERROR ((EFI_SAL_STATUS) - 3)
///
/// Virtual address not registered.
///
#define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4)
///
/// No information available.
///
#define EFI_SAL_NO_INFORMATION ((EFI_SAL_STATUS) - 5)
///
/// Scratch buffer required.
///
#define EFI_SAL_NOT_ENOUGH_SCRATCH ((EFI_SAL_STATUS) - 9)
///
/// Return registers from SAL.
///
typedef struct {
///
/// SAL return status value in r8.
///
EFI_SAL_STATUS Status;
///
/// SAL returned value in r9.
///
UINTN r9;
///
/// SAL returned value in r10.
///
UINTN r10;
///
/// SAL returned value in r11.
///
UINTN r11;
} SAL_RETURN_REGS;
/**
Prototype of SAL procedures.
@param FunctionId Functional identifier.
The upper 32 bits are ignored and only the lower 32 bits
are used. The following functional identifiers are defined:
0x01XXXXXX - Architected SAL functional group.
0x02XXXXXX to 0x03XXXXXX - OEM SAL functional group. Each OEM is
allowed to use the entire range in the 0x02XXXXXX to 0x03XXXXXX range.
0x04XXXXXX to 0xFFFFFFFF - Reserved.
@param Arg1 The first parameter of the architected/OEM specific SAL functions.
@param Arg2 The second parameter of the architected/OEM specific SAL functions.
@param Arg3 The third parameter passed to the ESAL function based.
@param Arg4 The fourth parameter passed to the ESAL function based.
@param Arg5 The fifth parameter passed to the ESAL function based.
@param Arg6 The sixth parameter passed to the ESAL function.
@param Arg7 The seventh parameter passed to the ESAL function based.
@return r8 Return status: positive number indicates successful,
negative number indicates failure.
r9 Other return parameter in r9.
r10 Other return parameter in r10.
r11 Other return parameter in r11.
**/
typedef
SAL_RETURN_REGS
(EFIAPI *SAL_PROC)(
IN UINT64 FunctionId,
IN UINT64 Arg1,
IN UINT64 Arg2,
IN UINT64 Arg3,
IN UINT64 Arg4,
IN UINT64 Arg5,
IN UINT64 Arg6,
IN UINT64 Arg7
);
//
// SAL Procedure FunctionId definition
//
///
/// Register software code locations with SAL.
///
#define EFI_SAL_SET_VECTORS 0x01000000
///
/// Return Machine State information obtained by SAL.
///
#define EFI_SAL_GET_STATE_INFO 0x01000001
///
/// Obtain size of Machine State information.
///
#define EFI_SAL_GET_STATE_INFO_SIZE 0x01000002
///
/// Clear Machine State information.
///
#define EFI_SAL_CLEAR_STATE_INFO 0x01000003
///
/// Cause the processor to go into a spin loop within SAL.
///
#define EFI_SAL_MC_RENDEZ 0x01000004
///
/// Register the machine check interface layer with SAL.
///
#define EFI_SAL_MC_SET_PARAMS 0x01000005
///
/// Register the physical addresses of locations needed by SAL.
///
#define EFI_SAL_REGISTER_PHYSICAL_ADDR 0x01000006
///
/// Flush the instruction or data caches.
///
#define EFI_SAL_CACHE_FLUSH 0x01000008
///
/// Initialize the instruction and data caches.
///
#define EFI_SAL_CACHE_INIT 0x01000009
///
/// Read from the PCI configuration space.
///
#define EFI_SAL_PCI_CONFIG_READ 0x01000010
///
/// Write to the PCI configuration space.
///
#define EFI_SAL_PCI_CONFIG_WRITE 0x01000011
///
/// Return the base frequency of the platform.
///
#define EFI_SAL_FREQ_BASE 0x01000012
///
/// Returns information on the physical processor mapping within the platform.
///
#define EFI_SAL_PHYSICAL_ID_INFO 0x01000013
///
/// Update the contents of firmware blocks.
///
#define EFI_SAL_UPDATE_PAL 0x01000020
#define EFI_SAL_FUNCTION_ID_MASK 0x0000ffff
#define EFI_SAL_MAX_SAL_FUNCTION_ID 0x00000021
//
// SAL Procedure parameter definitions
// Not much point in using typedefs or enums because all params
// are UINT64 and the entry point is common
//
//
// Parameter of EFI_SAL_SET_VECTORS
//
// Vector type
//
#define EFI_SAL_SET_MCA_VECTOR 0x0
#define EFI_SAL_SET_INIT_VECTOR 0x1
#define EFI_SAL_SET_BOOT_RENDEZ_VECTOR 0x2
///
/// The format of a length_cs_n argument.
///
typedef struct {
UINT64 Length : 32;
UINT64 ChecksumValid : 1;
UINT64 Reserved1 : 7;
UINT64 ByteChecksum : 8;
UINT64 Reserved2 : 16;
} SAL_SET_VECTORS_CS_N;
//
// Parameter of EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE, and EFI_SAL_CLEAR_STATE_INFO
//
// Type of information
//
#define EFI_SAL_MCA_STATE_INFO 0x0
#define EFI_SAL_INIT_STATE_INFO 0x1
#define EFI_SAL_CMC_STATE_INFO 0x2
#define EFI_SAL_CP_STATE_INFO 0x3
//
// Parameter of EFI_SAL_MC_SET_PARAMS
//
// Unsigned 64-bit integer value for the parameter type of the machine check interface
//
#define EFI_SAL_MC_SET_RENDEZ_PARAM 0x1
#define EFI_SAL_MC_SET_WAKEUP_PARAM 0x2
#define EFI_SAL_MC_SET_CPE_PARAM 0x3
//
// Unsigned 64-bit integer value indicating whether interrupt vector or
// memory address is specified
//
#define EFI_SAL_MC_SET_INTR_PARAM 0x1
#define EFI_SAL_MC_SET_MEM_PARAM 0x2
//
// Parameter of EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR
//
// The encoded value of the entity whose physical address is registered
//
#define EFI_SAL_REGISTER_PAL_ADDR 0x0
//
// Parameter of EFI_SAL_CACHE_FLUSH
//
// Unsigned 64-bit integer denoting type of cache flush operation
//
#define EFI_SAL_FLUSH_I_CACHE 0x01
#define EFI_SAL_FLUSH_D_CACHE 0x02
#define EFI_SAL_FLUSH_BOTH_CACHE 0x03
#define EFI_SAL_FLUSH_MAKE_COHERENT 0x04
//
// Parameter of EFI_SAL_PCI_CONFIG_READ and EFI_SAL_PCI_CONFIG_WRITE
//
// PCI config size
//
#define EFI_SAL_PCI_CONFIG_ONE_BYTE 0x1
#define EFI_SAL_PCI_CONFIG_TWO_BYTES 0x2
#define EFI_SAL_PCI_CONFIG_FOUR_BYTES 0x4
//
// The type of PCI configuration address
//
#define EFI_SAL_PCI_COMPATIBLE_ADDRESS 0x0
#define EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS 0x1
///
/// The format of PCI Compatible Address.
///
typedef struct {
UINT64 Register : 8;
UINT64 Function : 3;
UINT64 Device : 5;
UINT64 Bus : 8;
UINT64 Segment : 8;
UINT64 Reserved : 32;
} SAL_PCI_ADDRESS;
///
/// The format of Extended Register Address.
///
typedef struct {
UINT64 Register : 8;
UINT64 ExtendedRegister : 4;
UINT64 Function : 3;
UINT64 Device : 5;
UINT64 Bus : 8;
UINT64 Segment : 16;
UINT64 Reserved : 20;
} SAL_PCI_EXTENDED_REGISTER_ADDRESS;
//
// Parameter of EFI_SAL_FREQ_BASE
//
// Unsigned 64-bit integer specifying the type of clock source
//
#define EFI_SAL_CPU_INPUT_FREQ_BASE 0x0
#define EFI_SAL_PLATFORM_IT_FREQ_BASE 0x1
#define EFI_SAL_PLATFORM_RTC_FREQ_BASE 0x2
//
// Parameter and return value of EFI_SAL_UPDATE_PAL
//
// Return parameter provides additional information on the
// failure when the status field contains a value of -3,
// returned in r9.
//
#define EFI_SAL_UPDATE_BAD_PAL_VERSION ((UINT64) -1)
#define EFI_SAL_UPDATE_PAL_AUTH_FAIL ((UINT64) -2)
#define EFI_SAL_UPDATE_PAL_BAD_TYPE ((UINT64) -3)
#define EFI_SAL_UPDATE_PAL_READONLY ((UINT64) -4)
#define EFI_SAL_UPDATE_PAL_WRITE_FAIL ((UINT64) -10)
#define EFI_SAL_UPDATE_PAL_ERASE_FAIL ((UINT64) -11)
#define EFI_SAL_UPDATE_PAL_READ_FAIL ((UINT64) -12)
#define EFI_SAL_UPDATE_PAL_CANT_FIT ((UINT64) -13)
///
/// 64-byte header of update data block.
///
typedef struct {
UINT32 Size;
UINT32 MmddyyyyDate;
UINT16 Version;
UINT8 Type;
UINT8 Reserved[5];
UINT64 FwVendorId;
UINT8 Reserved2[40];
} SAL_UPDATE_PAL_DATA_BLOCK;
///
/// Data structure pointed by the parameter param_buf.
/// It is a 16-byte aligned data structure in memory with a length of 32 bytes
/// that describes the new firmware. This information is organized in the form
/// of a linked list with each element describing one firmware component.
///
typedef struct _SAL_UPDATE_PAL_INFO_BLOCK {
struct _SAL_UPDATE_PAL_INFO_BLOCK *Next;
struct SAL_UPDATE_PAL_DATA_BLOCK *DataBlock;
UINT8 StoreChecksum;
UINT8 Reserved[15];
} SAL_UPDATE_PAL_INFO_BLOCK;
///
/// SAL System Table Definitions.
///
#pragma pack(1)
typedef struct {
///
/// The ASCII string representation of "SST_" that confirms the presence of the table.
///
UINT32 Signature;
///
/// The length of the entire table in bytes, starting from offset zero and including the
/// header and all entries indicated by the EntryCount field.
///
UINT32 Length;
///
/// The revision number of the Itanium Processor Family System Abstraction Layer
/// Specification supported by the SAL implementation, in binary coded decimal (BCD) format.
///
UINT16 SalRevision;
///
/// The number of entries in the variable portion of the table.
///
UINT16 EntryCount;
///
/// A modulo checksum of the entire table and the entries following this table.
///
UINT8 CheckSum;
///
/// Unused, must be zero.
///
UINT8 Reserved[7];
///
/// Version Number of the SAL_A firmware implementation in BCD format.
///
UINT16 SalAVersion;
///
/// Version Number of the SAL_B firmware implementation in BCD format.
///
UINT16 SalBVersion;
///
/// An ASCII identification string which uniquely identifies the manufacturer
/// of the system hardware.
///
UINT8 OemId[32];
///
/// An ASCII identification string which uniquely identifies a family of
/// compatible products from the manufacturer.
///
UINT8 ProductId[32];
///
/// Unused, must be zero.
///
UINT8 Reserved2[8];
} SAL_SYSTEM_TABLE_HEADER;
#define EFI_SAL_ST_HEADER_SIGNATURE "SST_"
#define EFI_SAL_REVISION 0x0320
//
// SAL System Types
//
#define EFI_SAL_ST_ENTRY_POINT 0
#define EFI_SAL_ST_MEMORY_DESCRIPTOR 1
#define EFI_SAL_ST_PLATFORM_FEATURES 2
#define EFI_SAL_ST_TR_USAGE 3
#define EFI_SAL_ST_PTC 4
#define EFI_SAL_ST_AP_WAKEUP 5
//
// SAL System Type Sizes
//
#define EFI_SAL_ST_ENTRY_POINT_SIZE 48
#define EFI_SAL_ST_MEMORY_DESCRIPTOR_SIZE 32
#define EFI_SAL_ST_PLATFORM_FEATURES_SIZE 16
#define EFI_SAL_ST_TR_USAGE_SIZE 32
#define EFI_SAL_ST_PTC_SIZE 16
#define EFI_SAL_ST_AP_WAKEUP_SIZE 16
///
/// Format of Entrypoint Descriptor Entry.
///
typedef struct {
UINT8 Type; ///< Type here should be 0.
UINT8 Reserved[7];
UINT64 PalProcEntry;
UINT64 SalProcEntry;
UINT64 SalGlobalDataPointer;
UINT64 Reserved2[2];
} SAL_ST_ENTRY_POINT_DESCRIPTOR;
///
/// Format of Platform Features Descriptor Entry.
///
typedef struct {
UINT8 Type; ///< Type here should be 2.
UINT8 PlatformFeatures;
UINT8 Reserved[14];
} SAL_ST_PLATFORM_FEATURES;
//
// Value of Platform Feature List
//
#define SAL_PLAT_FEAT_BUS_LOCK 0x01
#define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02
#define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04
///
/// Format of Translation Register Descriptor Entry.
///
typedef struct {
UINT8 Type; ///< Type here should be 3.
UINT8 TRType;
UINT8 TRNumber;
UINT8 Reserved[5];
UINT64 VirtualAddress;
UINT64 EncodedPageSize;
UINT64 Reserved1;
} SAL_ST_TR_DECRIPTOR;
//
// Type of Translation Register
//
#define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00
#define EFI_SAL_ST_TR_USAGE_DATA 01
///
/// Definition of Coherence Domain Information.
///
typedef struct {
UINT64 NumberOfProcessors;
UINT64 LocalIDRegister;
} SAL_COHERENCE_DOMAIN_INFO;
///
/// Format of Purge Translation Cache Coherence Domain Entry.
///
typedef struct {
UINT8 Type; ///< Type here should be 4.
UINT8 Reserved[3];
UINT32 NumberOfDomains;
SAL_COHERENCE_DOMAIN_INFO *DomainInformation;
} SAL_ST_CACHE_COHERENCE_DECRIPTOR;
///
/// Format of Application Processor Wake-Up Descriptor Entry.
///
typedef struct {
UINT8 Type; ///< Type here should be 5.
UINT8 WakeUpType;
UINT8 Reserved[6];
UINT64 ExternalInterruptVector;
} SAL_ST_AP_WAKEUP_DECRIPTOR;
///
/// Format of Firmware Interface Table (FIT) Entry.
///
typedef struct {
UINT64 Address;
UINT8 Size[3];
UINT8 Reserved;
UINT16 Revision;
UINT8 Type : 7;
UINT8 CheckSumValid : 1;
UINT8 CheckSum;
} EFI_SAL_FIT_ENTRY;
//
// FIT Types
//
#define EFI_SAL_FIT_FIT_HEADER_TYPE 0x00
#define EFI_SAL_FIT_PAL_B_TYPE 0x01
//
// Type from 0x02 to 0x0D is reserved.
//
#define EFI_SAL_FIT_PROCESSOR_SPECIFIC_PAL_A_TYPE 0x0E
#define EFI_SAL_FIT_PAL_A_TYPE 0x0F
//
// OEM-defined type range is from 0x10 to 0x7E.
// Here we defined the PEI_CORE type as 0x10
//
#define EFI_SAL_FIT_PEI_CORE_TYPE 0x10
#define EFI_SAL_FIT_UNUSED_TYPE 0x7F
//
// FIT Entry
//
#define EFI_SAL_FIT_ENTRY_PTR (0x100000000 - 32) // 4GB - 24
#define EFI_SAL_FIT_PALA_ENTRY (0x100000000 - 48) // 4GB - 32
#define EFI_SAL_FIT_PALB_TYPE 01
//
// Following definitions are for Error Record Structure
//
///
/// Format of TimeStamp field in Record Header.
///
typedef struct {
UINT8 Seconds;
UINT8 Minutes;
UINT8 Hours;
UINT8 Reserved;
UINT8 Day;
UINT8 Month;
UINT8 Year;
UINT8 Century;
} SAL_TIME_STAMP;
///
/// Definition of Record Header.
///
typedef struct {
UINT64 RecordId;
UINT16 Revision;
UINT8 ErrorSeverity;
UINT8 ValidationBits;
UINT32 RecordLength;
SAL_TIME_STAMP TimeStamp;
UINT8 OemPlatformId[16];
} SAL_RECORD_HEADER;
///
/// Definition of Section Header.
///
typedef struct {
GUID Guid;
UINT16 Revision;
UINT8 ErrorRecoveryInfo;
UINT8 Reserved;
UINT32 SectionLength;
} SAL_SEC_HEADER;
///
/// GUID of Processor Machine Check Errors.
///
#define SAL_PROCESSOR_ERROR_RECORD_INFO \
{ \
0xe429faf1, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
}
//
// Bit masks for valid bits of MOD_ERROR_INFO
//
#define CHECK_INFO_VALID_BIT_MASK 0x1
#define REQUESTOR_ID_VALID_BIT_MASK 0x2
#define RESPONDER_ID_VALID_BIT_MASK 0x4
#define TARGER_ID_VALID_BIT_MASK 0x8
#define PRECISE_IP_VALID_BIT_MASK 0x10
///
/// Definition of MOD_ERROR_INFO_STRUCT.
///
typedef struct {
UINT64 InfoValid : 1;
UINT64 ReqValid : 1;
UINT64 RespValid : 1;
UINT64 TargetValid : 1;
UINT64 IpValid : 1;
UINT64 Reserved : 59;
UINT64 Info;
UINT64 Req;
UINT64 Resp;
UINT64 Target;
UINT64 Ip;
} MOD_ERROR_INFO;
///
/// Definition of CPUID_INFO_STRUCT.
///
typedef struct {
UINT8 CpuidInfo[40];
UINT8 Reserved;
} CPUID_INFO;
typedef struct {
UINT64 FrLow;
UINT64 FrHigh;
} FR_STRUCT;
//
// Bit masks for PSI_STATIC_STRUCT.ValidFieldBits
//
#define MIN_STATE_VALID_BIT_MASK 0x1
#define BR_VALID_BIT_MASK 0x2
#define CR_VALID_BIT_MASK 0x4
#define AR_VALID_BIT_MASK 0x8
#define RR_VALID_BIT_MASK 0x10
#define FR_VALID_BIT_MASK 0x20
///
/// Definition of PSI_STATIC_STRUCT.
///
typedef struct {
UINT64 ValidFieldBits;
UINT8 MinStateInfo[1024];
UINT64 Br[8];
UINT64 Cr[128];
UINT64 Ar[128];
UINT64 Rr[8];
FR_STRUCT Fr[128];
} PSI_STATIC_STRUCT;
//
// Bit masks for SAL_PROCESSOR_ERROR_RECORD.ValidationBits
//
#define PROC_ERROR_MAP_VALID_BIT_MASK 0x1
#define PROC_STATE_PARAMETER_VALID_BIT_MASK 0x2
#define PROC_CR_LID_VALID_BIT_MASK 0x4
#define PROC_STATIC_STRUCT_VALID_BIT_MASK 0x8
#define CPU_INFO_VALID_BIT_MASK 0x1000000
///
/// Definition of Processor Machine Check Error Record.
///
typedef struct {
SAL_SEC_HEADER SectionHeader;
UINT64 ValidationBits;
UINT64 ProcErrorMap;
UINT64 ProcStateParameter;
UINT64 ProcCrLid;
MOD_ERROR_INFO CacheError[15];
MOD_ERROR_INFO TlbError[15];
MOD_ERROR_INFO BusError[15];
MOD_ERROR_INFO RegFileCheck[15];
MOD_ERROR_INFO MsCheck[15];
CPUID_INFO CpuInfo;
PSI_STATIC_STRUCT PsiValidData;
} SAL_PROCESSOR_ERROR_RECORD;
///
/// GUID of Platform Memory Device Error Info.
///
#define SAL_MEMORY_ERROR_RECORD_INFO \
{ \
0xe429faf2, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
}
//
// Bit masks for SAL_MEMORY_ERROR_RECORD.ValidationBits
//
#define MEMORY_ERROR_STATUS_VALID_BIT_MASK 0x1
#define MEMORY_PHYSICAL_ADDRESS_VALID_BIT_MASK 0x2
#define MEMORY_ADDR_BIT_MASK 0x4
#define MEMORY_NODE_VALID_BIT_MASK 0x8
#define MEMORY_CARD_VALID_BIT_MASK 0x10
#define MEMORY_MODULE_VALID_BIT_MASK 0x20
#define MEMORY_BANK_VALID_BIT_MASK 0x40
#define MEMORY_DEVICE_VALID_BIT_MASK 0x80
#define MEMORY_ROW_VALID_BIT_MASK 0x100
#define MEMORY_COLUMN_VALID_BIT_MASK 0x200
#define MEMORY_BIT_POSITION_VALID_BIT_MASK 0x400
#define MEMORY_PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x800
#define MEMORY_PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x1000
#define MEMORY_PLATFORM_TARGET_VALID_BIT_MASK 0x2000
#define MEMORY_PLATFORM_BUS_SPECIFIC_DATA_VALID_BIT_MASK 0x4000
#define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK 0x8000
#define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x10000
///
/// Definition of Platform Memory Device Error Info Record.
///
typedef struct {
SAL_SEC_HEADER SectionHeader;
UINT64 ValidationBits;
UINT64 MemErrorStatus;
UINT64 MemPhysicalAddress;
UINT64 MemPhysicalAddressMask;
UINT16 MemNode;
UINT16 MemCard;
UINT16 MemModule;
UINT16 MemBank;
UINT16 MemDevice;
UINT16 MemRow;
UINT16 MemColumn;
UINT16 MemBitPosition;
UINT64 ModRequestorId;
UINT64 ModResponderId;
UINT64 ModTargetId;
UINT64 BusSpecificData;
UINT8 MemPlatformOemId[16];
} SAL_MEMORY_ERROR_RECORD;
///
/// GUID of Platform PCI Bus Error Info.
///
#define SAL_PCI_BUS_ERROR_RECORD_INFO \
{ \
0xe429faf4, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
}
//
// Bit masks for SAL_PCI_BUS_ERROR_RECORD.ValidationBits
//
#define PCI_BUS_ERROR_STATUS_VALID_BIT_MASK 0x1
#define PCI_BUS_ERROR_TYPE_VALID_BIT_MASK 0x2
#define PCI_BUS_ID_VALID_BIT_MASK 0x4
#define PCI_BUS_ADDRESS_VALID_BIT_MASK 0x8
#define PCI_BUS_DATA_VALID_BIT_MASK 0x10
#define PCI_BUS_CMD_VALID_BIT_MASK 0x20
#define PCI_BUS_REQUESTOR_ID_VALID_BIT_MASK 0x40
#define PCI_BUS_RESPONDER_ID_VALID_BIT_MASK 0x80
#define PCI_BUS_TARGET_VALID_BIT_MASK 0x100
#define PCI_BUS_OEM_ID_VALID_BIT_MASK 0x200
#define PCI_BUS_OEM_DATA_STRUCT_VALID_BIT_MASK 0x400
///
/// Designated PCI Bus identifier.
///
typedef struct {
UINT8 BusNumber;
UINT8 SegmentNumber;
} PCI_BUS_ID;
///
/// Definition of Platform PCI Bus Error Info Record.
///
typedef struct {
SAL_SEC_HEADER SectionHeader;
UINT64 ValidationBits;
UINT64 PciBusErrorStatus;
UINT16 PciBusErrorType;
PCI_BUS_ID PciBusId;
UINT32 Reserved;
UINT64 PciBusAddress;
UINT64 PciBusData;
UINT64 PciBusCommand;
UINT64 PciBusRequestorId;
UINT64 PciBusResponderId;
UINT64 PciBusTargetId;
UINT8 PciBusOemId[16];
} SAL_PCI_BUS_ERROR_RECORD;
///
/// GUID of Platform PCI Component Error Info.
///
#define SAL_PCI_COMP_ERROR_RECORD_INFO \
{ \
0xe429faf6, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
}
//
// Bit masks for SAL_PCI_COMPONENT_ERROR_RECORD.ValidationBits
//
#define PCI_COMP_ERROR_STATUS_VALID_BIT_MASK 0x1
#define PCI_COMP_INFO_VALID_BIT_MASK 0x2
#define PCI_COMP_MEM_NUM_VALID_BIT_MASK 0x4
#define PCI_COMP_IO_NUM_VALID_BIT_MASK 0x8
#define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK 0x10
#define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20
///
/// Format of PCI Component Information to identify the device.
///
typedef struct {
UINT16 VendorId;
UINT16 DeviceId;
UINT8 ClassCode[3];
UINT8 FunctionNumber;
UINT8 DeviceNumber;
UINT8 BusNumber;
UINT8 SegmentNumber;
UINT8 Reserved[5];
} PCI_COMP_INFO;
///
/// Definition of Platform PCI Component Error Info.
///
typedef struct {
SAL_SEC_HEADER SectionHeader;
UINT64 ValidationBits;
UINT64 PciComponentErrorStatus;
PCI_COMP_INFO PciComponentInfo;
UINT32 PciComponentMemNum;
UINT32 PciComponentIoNum;
UINT8 PciBusOemId[16];
} SAL_PCI_COMPONENT_ERROR_RECORD;
///
/// Platform SEL Device Error Info.
///
#define SAL_SEL_DEVICE_ERROR_RECORD_INFO \
{ \
0xe429faf3, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
}
//
// Bit masks for SAL_SEL_DEVICE_ERROR_RECORD.ValidationBits
//
#define SEL_RECORD_ID_VALID_BIT_MASK 0x1;
#define SEL_RECORD_TYPE_VALID_BIT_MASK 0x2;
#define SEL_GENERATOR_ID_VALID_BIT_MASK 0x4;
#define SEL_EVM_REV_VALID_BIT_MASK 0x8;
#define SEL_SENSOR_TYPE_VALID_BIT_MASK 0x10;
#define SEL_SENSOR_NUM_VALID_BIT_MASK 0x20;
#define SEL_EVENT_DIR_TYPE_VALID_BIT_MASK 0x40;
#define SEL_EVENT_DATA1_VALID_BIT_MASK 0x80;
#define SEL_EVENT_DATA2_VALID_BIT_MASK 0x100;
#define SEL_EVENT_DATA3_VALID_BIT_MASK 0x200;
///
/// Definition of Platform SEL Device Error Info Record.
///
typedef struct {
SAL_SEC_HEADER SectionHeader;
UINT64 ValidationBits;
UINT16 SelRecordId;
UINT8 SelRecordType;
UINT32 TimeStamp;
UINT16 GeneratorId;
UINT8 EvmRevision;
UINT8 SensorType;
UINT8 SensorNum;
UINT8 EventDirType;
UINT8 Data1;
UINT8 Data2;
UINT8 Data3;
} SAL_SEL_DEVICE_ERROR_RECORD;
///
/// GUID of Platform SMBIOS Device Error Info.
///
#define SAL_SMBIOS_ERROR_RECORD_INFO \
{ \
0xe429faf5, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
}
//
// Bit masks for SAL_SMBIOS_DEVICE_ERROR_RECORD.ValidationBits
//
#define SMBIOS_EVENT_TYPE_VALID_BIT_MASK 0x1
#define SMBIOS_LENGTH_VALID_BIT_MASK 0x2
#define SMBIOS_TIME_STAMP_VALID_BIT_MASK 0x4
#define SMBIOS_DATA_VALID_BIT_MASK 0x8
///
/// Definition of Platform SMBIOS Device Error Info Record.
///
typedef struct {
SAL_SEC_HEADER SectionHeader;
UINT64 ValidationBits;
UINT8 SmbiosEventType;
UINT8 SmbiosLength;
UINT8 SmbiosBcdTimeStamp[6];
} SAL_SMBIOS_DEVICE_ERROR_RECORD;
///
/// GUID of Platform Specific Error Info.
///
#define SAL_PLATFORM_ERROR_RECORD_INFO \
{ \
0xe429faf7, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
}
//
// Bit masks for SAL_PLATFORM_SPECIFIC_ERROR_RECORD.ValidationBits
//
#define PLATFORM_ERROR_STATUS_VALID_BIT_MASK 0x1
#define PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x2
#define PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x4
#define PLATFORM_TARGET_VALID_BIT_MASK 0x8
#define PLATFORM_SPECIFIC_DATA_VALID_BIT_MASK 0x10
#define PLATFORM_OEM_ID_VALID_BIT_MASK 0x20
#define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40
#define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80
///
/// Definition of Platform Specific Error Info Record.
///
typedef struct {
SAL_SEC_HEADER SectionHeader;
UINT64 ValidationBits;
UINT64 PlatformErrorStatus;
UINT64 PlatformRequestorId;
UINT64 PlatformResponderId;
UINT64 PlatformTargetId;
UINT64 PlatformBusSpecificData;
UINT8 OemComponentId[16];
} SAL_PLATFORM_SPECIFIC_ERROR_RECORD;
///
/// Union of all the possible SAL Error Record Types.
///
typedef union {
SAL_RECORD_HEADER *RecordHeader;
SAL_PROCESSOR_ERROR_RECORD *SalProcessorRecord;
SAL_PCI_BUS_ERROR_RECORD *SalPciBusRecord;
SAL_PCI_COMPONENT_ERROR_RECORD *SalPciComponentRecord;
SAL_SEL_DEVICE_ERROR_RECORD *ImpiRecord;
SAL_SMBIOS_DEVICE_ERROR_RECORD *SmbiosRecord;
SAL_PLATFORM_SPECIFIC_ERROR_RECORD *PlatformRecord;
SAL_MEMORY_ERROR_RECORD *MemoryRecord;
UINT8 *Raw;
} SAL_ERROR_RECORDS_POINTERS;
#pragma pack()
#endif

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/** @file
Support for SCSI-2 standard
Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __SCSI_H__
#define __SCSI_H__
//
// SCSI command OP Code
//
//
// Commands for all device types
//
#define EFI_SCSI_OP_CHANGE_DEFINITION 0x40
#define EFI_SCSI_OP_COMPARE 0x39
#define EFI_SCSI_OP_COPY 0x18
#define EFI_SCSI_OP_COPY_VERIFY 0x3a
#define EFI_SCSI_OP_INQUIRY 0x12
#define EFI_SCSI_OP_LOG_SELECT 0x4c
#define EFI_SCSI_OP_LOG_SENSE 0x4d
#define EFI_SCSI_OP_MODE_SEL6 0x15
#define EFI_SCSI_OP_MODE_SEL10 0x55
#define EFI_SCSI_OP_MODE_SEN6 0x1a
#define EFI_SCSI_OP_MODE_SEN10 0x5a
#define EFI_SCSI_OP_READ_BUFFER 0x3c
#define EFI_SCSI_OP_RECEIVE_DIAG 0x1c
#define EFI_SCSI_OP_REQUEST_SENSE 0x03
#define EFI_SCSI_OP_SEND_DIAG 0x1d
#define EFI_SCSI_OP_TEST_UNIT_READY 0x00
#define EFI_SCSI_OP_WRITE_BUFF 0x3b
//
// Additional commands for Direct Access Devices
//
#define EFI_SCSI_OP_FORMAT 0x04
#define EFI_SCSI_OP_LOCK_UN_CACHE 0x36
#define EFI_SCSI_OP_PREFETCH 0x34
#define EFI_SCSI_OP_MEDIA_REMOVAL 0x1e
#define EFI_SCSI_OP_READ6 0x08
#define EFI_SCSI_OP_READ10 0x28
#define EFI_SCSI_OP_READ16 0x88
#define EFI_SCSI_OP_READ_CAPACITY 0x25
#define EFI_SCSI_OP_READ_CAPACITY16 0x9e
#define EFI_SCSI_OP_READ_DEFECT 0x37
#define EFI_SCSI_OP_READ_LONG 0x3e
#define EFI_SCSI_OP_REASSIGN_BLK 0x07
#define EFI_SCSI_OP_RELEASE 0x17
#define EFI_SCSI_OP_REZERO 0x01
#define EFI_SCSI_OP_SEARCH_DATA_E 0x31
#define EFI_SCSI_OP_SEARCH_DATA_H 0x30
#define EFI_SCSI_OP_SEARCH_DATA_L 0x32
#define EFI_SCSI_OP_SEEK6 0x0b
#define EFI_SCSI_OP_SEEK10 0x2b
#define EFI_SCSI_OP_SEND_DIAG 0x1d
#define EFI_SCSI_OP_SET_LIMIT 0x33
#define EFI_SCSI_OP_START_STOP_UNIT 0x1b
#define EFI_SCSI_OP_SYNC_CACHE 0x35
#define EFI_SCSI_OP_VERIFY 0x2f
#define EFI_SCSI_OP_WRITE6 0x0a
#define EFI_SCSI_OP_WRITE10 0x2a
#define EFI_SCSI_OP_WRITE16 0x8a
#define EFI_SCSI_OP_WRITE_VERIFY 0x2e
#define EFI_SCSI_OP_WRITE_LONG 0x3f
#define EFI_SCSI_OP_WRITE_SAME 0x41
#define EFI_SCSI_OP_UNMAP 0x42
//
// Additional commands for Sequential Access Devices
//
#define EFI_SCSI_OP_ERASE 0x19
#define EFI_SCSI_OP_LOAD_UNLOAD 0x1b
#define EFI_SCSI_OP_LOCATE 0x2b
#define EFI_SCSI_OP_READ_BLOCK_LIMIT 0x05
#define EFI_SCSI_OP_READ_POS 0x34
#define EFI_SCSI_OP_READ_REVERSE 0x0f
#define EFI_SCSI_OP_RECOVER_BUF_DATA 0x14
#define EFI_SCSI_OP_RESERVE_UNIT 0x16
#define EFI_SCSI_OP_REWIND 0x01
#define EFI_SCSI_OP_SPACE 0x11
#define EFI_SCSI_OP_VERIFY_TAPE 0x13
#define EFI_SCSI_OP_WRITE_FILEMARK 0x10
//
// Additional commands for Printer Devices
//
#define EFI_SCSI_OP_PRINT 0x0a
#define EFI_SCSI_OP_SLEW_PRINT 0x0b
#define EFI_SCSI_OP_STOP_PRINT 0x1b
#define EFI_SCSI_OP_SYNC_BUFF 0x10
//
// Additional commands for Processor Devices
//
#define EFI_SCSI_OP_RECEIVE 0x08
#define EFI_SCSI_OP_SEND 0x0a
//
// Additional commands for Write-Once Devices
//
#define EFI_SCSI_OP_MEDIUM_SCAN 0x38
#define EFI_SCSI_OP_SEARCH_DAT_E10 0x31
#define EFI_SCSI_OP_SEARCH_DAT_E12 0xb1
#define EFI_SCSI_OP_SEARCH_DAT_H10 0x30
#define EFI_SCSI_OP_SEARCH_DAT_H12 0xb0
#define EFI_SCSI_OP_SEARCH_DAT_L10 0x32
#define EFI_SCSI_OP_SEARCH_DAT_L12 0xb2
#define EFI_SCSI_OP_SET_LIMIT10 0x33
#define EFI_SCSI_OP_SET_LIMIT12 0xb3
#define EFI_SCSI_OP_VERIFY10 0x2f
#define EFI_SCSI_OP_VERIFY12 0xaf
#define EFI_SCSI_OP_WRITE12 0xaa
#define EFI_SCSI_OP_WRITE_VERIFY10 0x2e
#define EFI_SCSI_OP_WRITE_VERIFY12 0xae
//
// Additional commands for CD-ROM Devices
//
#define EFI_SCSI_OP_PLAY_AUD_10 0x45
#define EFI_SCSI_OP_PLAY_AUD_12 0xa5
#define EFI_SCSI_OP_PLAY_AUD_MSF 0x47
#define EFI_SCSI_OP_PLAY_AUD_TKIN 0x48
#define EFI_SCSI_OP_PLAY_TK_REL10 0x49
#define EFI_SCSI_OP_PLAY_TK_REL12 0xa9
#define EFI_SCSI_OP_READ_CD_CAPACITY 0x25
#define EFI_SCSI_OP_READ_HEADER 0x44
#define EFI_SCSI_OP_READ_SUB_CHANNEL 0x42
#define EFI_SCSI_OP_READ_TOC 0x43
//
// Additional commands for Scanner Devices
//
#define EFI_SCSI_OP_GET_DATABUFF_STAT 0x34
#define EFI_SCSI_OP_GET_WINDOW 0x25
#define EFI_SCSI_OP_OBJECT_POS 0x31
#define EFI_SCSI_OP_SCAN 0x1b
#define EFI_SCSI_OP_SET_WINDOW 0x24
//
// Additional commands for Optical Memory Devices
//
#define EFI_SCSI_OP_UPDATE_BLOCK 0x3d
//
// Additional commands for Medium Changer Devices
//
#define EFI_SCSI_OP_EXCHANGE_MEDIUM 0xa6
#define EFI_SCSI_OP_INIT_ELEMENT_STAT 0x07
#define EFI_SCSI_OP_POS_TO_ELEMENT 0x2b
#define EFI_SCSI_OP_REQUEST_VE_ADDR 0xb5
#define EFI_SCSI_OP_SEND_VOL_TAG 0xb6
//
// Additional commands for Communition Devices
//
#define EFI_SCSI_OP_GET_MESSAGE6 0x08
#define EFI_SCSI_OP_GET_MESSAGE10 0x28
#define EFI_SCSI_OP_GET_MESSAGE12 0xa8
#define EFI_SCSI_OP_SEND_MESSAGE6 0x0a
#define EFI_SCSI_OP_SEND_MESSAGE10 0x2a
#define EFI_SCSI_OP_SEND_MESSAGE12 0xaa
//
// SCSI Data Transfer Direction
//
#define EFI_SCSI_DATA_IN 0
#define EFI_SCSI_DATA_OUT 1
//
// Peripheral Device Type Definitions
//
#define EFI_SCSI_TYPE_DISK 0x00 ///< Direct-access device (e.g. magnetic disk)
#define EFI_SCSI_TYPE_TAPE 0x01 ///< Sequential-access device (e.g. magnetic tape)
#define EFI_SCSI_TYPE_PRINTER 0x02 ///< Printer device
#define EFI_SCSI_TYPE_PROCESSOR 0x03 ///< Processor device
#define EFI_SCSI_TYPE_WORM 0x04 ///< Write-once device (e.g. some optical disks)
#define EFI_SCSI_TYPE_CDROM 0x05 ///< CD-ROM device
#define EFI_SCSI_TYPE_SCANNER 0x06 ///< Scanner device
#define EFI_SCSI_TYPE_OPTICAL 0x07 ///< Optical memory device (e.g. some optical disks)
#define EFI_SCSI_TYPE_MEDIUMCHANGER 0x08 ///< Medium changer device (e.g. jukeboxes)
#define EFI_SCSI_TYPE_COMMUNICATION 0x09 ///< Communications device
#define EFI_SCSI_TYPE_ASCIT8_1 0x0A ///< Defined by ASC IT8 (Graphic arts pre-press devices)
#define EFI_SCSI_TYPE_ASCIT8_2 0x0B ///< Defined by ASC IT8 (Graphic arts pre-press devices)
//
// 0Ch - 1Eh are reserved
//
#define EFI_SCSI_TYPE_UNKNOWN 0x1F ///< Unknown or no device type
//
// Page Codes for INQUIRY command
//
#define EFI_SCSI_PAGE_CODE_SUPPORTED_VPD 0x00
#define EFI_SCSI_PAGE_CODE_BLOCK_LIMITS_VPD 0xB0
#pragma pack(1)
///
/// Standard INQUIRY data format
///
typedef struct {
UINT8 Peripheral_Type : 5;
UINT8 Peripheral_Qualifier : 3;
UINT8 DeviceType_Modifier : 7;
UINT8 Rmb : 1;
UINT8 Version;
UINT8 Response_Data_Format;
UINT8 Addnl_Length;
UINT8 Reserved_5_95[95 - 5 + 1];
} EFI_SCSI_INQUIRY_DATA;
///
/// Supported VPD Pages VPD page
///
typedef struct {
UINT8 Peripheral_Type : 5;
UINT8 Peripheral_Qualifier : 3;
UINT8 PageCode;
UINT8 PageLength2;
UINT8 PageLength1;
UINT8 SupportedVpdPageList[0x100];
} EFI_SCSI_SUPPORTED_VPD_PAGES_VPD_PAGE;
///
/// Block Limits VPD page
///
typedef struct {
UINT8 Peripheral_Type : 5;
UINT8 Peripheral_Qualifier : 3;
UINT8 PageCode;
UINT8 PageLength2;
UINT8 PageLength1;
UINT8 WriteSameNonZero : 1;
UINT8 Reserved_4 : 7;
UINT8 MaximumCompareAndWriteLength;
UINT8 OptimalTransferLengthGranularity2;
UINT8 OptimalTransferLengthGranularity1;
UINT8 MaximumTransferLength4;
UINT8 MaximumTransferLength3;
UINT8 MaximumTransferLength2;
UINT8 MaximumTransferLength1;
UINT8 OptimalTransferLength4;
UINT8 OptimalTransferLength3;
UINT8 OptimalTransferLength2;
UINT8 OptimalTransferLength1;
UINT8 MaximumPrefetchXdreadXdwriteTransferLength4;
UINT8 MaximumPrefetchXdreadXdwriteTransferLength3;
UINT8 MaximumPrefetchXdreadXdwriteTransferLength2;
UINT8 MaximumPrefetchXdreadXdwriteTransferLength1;
UINT8 MaximumUnmapLbaCount4;
UINT8 MaximumUnmapLbaCount3;
UINT8 MaximumUnmapLbaCount2;
UINT8 MaximumUnmapLbaCount1;
UINT8 MaximumUnmapBlockDescriptorCount4;
UINT8 MaximumUnmapBlockDescriptorCount3;
UINT8 MaximumUnmapBlockDescriptorCount2;
UINT8 MaximumUnmapBlockDescriptorCount1;
UINT8 OptimalUnmapGranularity4;
UINT8 OptimalUnmapGranularity3;
UINT8 OptimalUnmapGranularity2;
UINT8 OptimalUnmapGranularity1;
UINT8 UnmapGranularityAlignment4 : 7;
UINT8 UnmapGranularityAlignmentValid : 1;
UINT8 UnmapGranularityAlignment3;
UINT8 UnmapGranularityAlignment2;
UINT8 UnmapGranularityAlignment1;
UINT8 MaximumWriteSameLength4;
UINT8 MaximumWriteSameLength3;
UINT8 MaximumWriteSameLength2;
UINT8 MaximumWriteSameLength1;
UINT8 MaximumAtomicTransferLength4;
UINT8 MaximumAtomicTransferLength3;
UINT8 MaximumAtomicTransferLength2;
UINT8 MaximumAtomicTransferLength1;
UINT8 AtomicAlignment4;
UINT8 AtomicAlignment3;
UINT8 AtomicAlignment2;
UINT8 AtomicAlignment1;
UINT8 AtomicTransferLengthGranularity4;
UINT8 AtomicTransferLengthGranularity3;
UINT8 AtomicTransferLengthGranularity2;
UINT8 AtomicTransferLengthGranularity1;
UINT8 MaximumAtomicTransferLengthWithAtomicBoundary4;
UINT8 MaximumAtomicTransferLengthWithAtomicBoundary3;
UINT8 MaximumAtomicTransferLengthWithAtomicBoundary2;
UINT8 MaximumAtomicTransferLengthWithAtomicBoundary1;
UINT8 MaximumAtomicBoundarySize4;
UINT8 MaximumAtomicBoundarySize3;
UINT8 MaximumAtomicBoundarySize2;
UINT8 MaximumAtomicBoundarySize1;
} EFI_SCSI_BLOCK_LIMITS_VPD_PAGE;
///
/// Error codes 70h and 71h sense data format
///
typedef struct {
UINT8 Error_Code : 7;
UINT8 Valid : 1;
UINT8 Segment_Number;
UINT8 Sense_Key : 4;
UINT8 Reserved_21 : 1;
UINT8 Ili : 1;
UINT8 Reserved_22 : 2;
UINT8 Information_3_6[4];
UINT8 Addnl_Sense_Length; ///< Additional sense length (n-7)
UINT8 Vendor_Specific_8_11[4];
UINT8 Addnl_Sense_Code; ///< Additional sense code
UINT8 Addnl_Sense_Code_Qualifier; ///< Additional sense code qualifier
UINT8 Field_Replaceable_Unit_Code; ///< Field replaceable unit code
UINT8 Reserved_15_17[3];
} EFI_SCSI_SENSE_DATA;
///
/// SCSI Disk READ CAPACITY Data
///
typedef struct {
UINT8 LastLba3;
UINT8 LastLba2;
UINT8 LastLba1;
UINT8 LastLba0;
UINT8 BlockSize3;
UINT8 BlockSize2;
UINT8 BlockSize1;
UINT8 BlockSize0;
} EFI_SCSI_DISK_CAPACITY_DATA;
typedef struct {
UINT8 LastLba7;
UINT8 LastLba6;
UINT8 LastLba5;
UINT8 LastLba4;
UINT8 LastLba3;
UINT8 LastLba2;
UINT8 LastLba1;
UINT8 LastLba0;
UINT8 BlockSize3;
UINT8 BlockSize2;
UINT8 BlockSize1;
UINT8 BlockSize0;
UINT8 Protection;
UINT8 LogicPerPhysical;
UINT8 LowestAlignLogic2;
UINT8 LowestAlignLogic1;
UINT8 Reserved[16];
} EFI_SCSI_DISK_CAPACITY_DATA16;
typedef struct {
UINT16 DataLen;
UINT16 BlkDespDataLen;
UINT8 Reserved[4];
} EFI_SCSI_DISK_UNMAP_PARAM_LIST_HEADER;
typedef struct {
UINT64 Lba;
UINT32 BlockNum;
UINT8 Reserved[4];
} EFI_SCSI_DISK_UNMAP_BLOCK_DESP;
#pragma pack()
//
// Sense Key
//
#define EFI_SCSI_SK_NO_SENSE (0x0)
#define EFI_SCSI_SK_RECOVERY_ERROR (0x1)
#define EFI_SCSI_SK_NOT_READY (0x2)
#define EFI_SCSI_SK_MEDIUM_ERROR (0x3)
#define EFI_SCSI_SK_HARDWARE_ERROR (0x4)
#define EFI_SCSI_SK_ILLEGAL_REQUEST (0x5)
#define EFI_SCSI_SK_UNIT_ATTENTION (0x6)
#define EFI_SCSI_SK_DATA_PROTECT (0x7)
#define EFI_SCSI_SK_BLANK_CHECK (0x8)
#define EFI_SCSI_SK_VENDOR_SPECIFIC (0x9)
#define EFI_SCSI_SK_RESERVED_A (0xA)
#define EFI_SCSI_SK_ABORT (0xB)
#define EFI_SCSI_SK_RESERVED_C (0xC)
#define EFI_SCSI_SK_OVERFLOW (0xD)
#define EFI_SCSI_SK_MISCOMPARE (0xE)
#define EFI_SCSI_SK_RESERVED_F (0xF)
//
// Additional Sense Codes and Sense Code Qualifiers.
// Only some frequently used additional sense codes and qualifiers are
// defined here. Please refer to SCSI standard for full value definition.
//
#define EFI_SCSI_ASC_NOT_READY (0x04)
#define EFI_SCSI_ASCQ_IN_PROGRESS (0x01)
#define EFI_SCSI_ASC_MEDIA_ERR1 (0x10)
#define EFI_SCSI_ASC_MEDIA_ERR2 (0x11)
#define EFI_SCSI_ASC_MEDIA_ERR3 (0x14)
#define EFI_SCSI_ASC_MEDIA_ERR4 (0x30)
#define EFI_SCSI_ASC_MEDIA_UPSIDE_DOWN (0x06)
#define EFI_SCSI_ASC_INVALID_CMD (0x20)
#define EFI_SCSI_ASC_LBA_OUT_OF_RANGE (0x21)
#define EFI_SCSI_ASC_INVALID_FIELD (0x24)
#define EFI_SCSI_ASC_WRITE_PROTECTED (0x27)
#define EFI_SCSI_ASC_MEDIA_CHANGE (0x28)
#define EFI_SCSI_ASC_RESET (0x29) ///< Power On Reset or Bus Reset occurred
#define EFI_SCSI_ASC_ILLEGAL_FIELD (0x26)
#define EFI_SCSI_ASC_NO_MEDIA (0x3A)
#define EFI_SCSI_ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64)
#endif

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/** @file
Header file for SD memory card support.
This header file contains some definitions defined in SD Physical Layer Simplified
Specification Version 4.10 spec.
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __SD_H__
#define __SD_H__
//
// SD command index
//
#define SD_GO_IDLE_STATE 0
#define SD_ALL_SEND_CID 2
#define SD_SET_RELATIVE_ADDR 3
#define SD_SET_DSR 4
#define SDIO_SEND_OP_COND 5
#define SD_SWITCH_FUNC 6
#define SD_SELECT_DESELECT_CARD 7
#define SD_SEND_IF_COND 8
#define SD_SEND_CSD 9
#define SD_SEND_CID 10
#define SD_VOLTAGE_SWITCH 11
#define SD_STOP_TRANSMISSION 12
#define SD_SEND_STATUS 13
#define SD_GO_INACTIVE_STATE 15
#define SD_SET_BLOCKLEN 16
#define SD_READ_SINGLE_BLOCK 17
#define SD_READ_MULTIPLE_BLOCK 18
#define SD_SEND_TUNING_BLOCK 19
#define SD_SPEED_CLASS_CONTROL 20
#define SD_SET_BLOCK_COUNT 23
#define SD_WRITE_SINGLE_BLOCK 24
#define SD_WRITE_MULTIPLE_BLOCK 25
#define SD_PROGRAM_CSD 27
#define SD_SET_WRITE_PROT 28
#define SD_CLR_WRITE_PROT 29
#define SD_SEND_WRITE_PROT 30
#define SD_ERASE_WR_BLK_START 32
#define SD_ERASE_WR_BLK_END 33
#define SD_ERASE 38
#define SD_LOCK_UNLOCK 42
#define SD_READ_EXTR_SINGLE 48
#define SD_WRITE_EXTR_SINGLE 49
#define SDIO_RW_DIRECT 52
#define SDIO_RW_EXTENDED 53
#define SD_APP_CMD 55
#define SD_GEN_CMD 56
#define SD_READ_EXTR_MULTI 58
#define SD_WRITE_EXTR_MULTI 59
#define SD_SET_BUS_WIDTH 6 // ACMD6
#define SD_STATUS 13 // ACMD13
#define SD_SEND_NUM_WR_BLOCKS 22 // ACMD22
#define SD_SET_WR_BLK_ERASE_COUNT 23 // ACMD23
#define SD_SEND_OP_COND 41 // ACMD41
#define SD_SET_CLR_CARD_DETECT 42 // ACMD42
#define SD_SEND_SCR 51 // ACMD51
#pragma pack(1)
typedef struct {
UINT8 NotUsed:1; // Not used [0:0]
UINT8 Crc:7; // CRC [7:1]
UINT16 ManufacturingDate:12; // Manufacturing date [19:8]
UINT16 Reserved:4; // Reserved [23:20]
UINT8 ProductSerialNumber[4]; // Product serial number [55:24]
UINT8 ProductRevision; // Product revision [63:56]
UINT8 ProductName[5]; // Product name [103:64]
UINT8 OemId[2]; // OEM/Application ID [119:104]
UINT8 ManufacturerId; // Manufacturer ID [127:120]
} SD_CID;
typedef struct {
UINT32 NotUsed:1; // Not used [0:0]
UINT32 Crc:7; // CRC [7:1]
UINT32 Reserved:2; // Reserved [9:8]
UINT32 FileFormat:2; // File format [11:10]
UINT32 TmpWriteProtect:1; // Temporary write protection [12:12]
UINT32 PermWriteProtect:1; // Permanent write protection [13:13]
UINT32 Copy:1; // Copy flag (OTP) [14:14]
UINT32 FileFormatGrp:1; // File format group [15:15]
UINT32 Reserved1:5; // Reserved [20:16]
UINT32 WriteBlPartial:1; // Partial blocks for write allowed [21:21]
UINT32 WriteBlLen:4; // Max. write data block length [25:22]
UINT32 R2WFactor:3; // Write speed factor [28:26]
UINT32 Reserved2:2; // Manufacturer default ECC [30:29]
UINT32 WpGrpEnable:1; // Write protect group enable [31:31]
UINT32 WpGrpSize:7; // Write protect group size [38:32]
UINT32 SectorSize:7; // Erase sector size [45:39]
UINT32 EraseBlkEn:1; // Erase single block enable [46:46]
UINT32 CSizeMul:3; // device size multiplier [49:47]
UINT32 VddWCurrMax:3; // max. write current @VDD max [52:50]
UINT32 VddWCurrMin:3; // max. write current @VDD min [55:53]
UINT32 VddRCurrMax:3; // max. read current @VDD max [58:56]
UINT32 VddRCurrMin:3; // max. read current @VDD min [61:59]
UINT32 CSizeLow:2; // Device size low 2 bits [63:62]
UINT32 CSizeHigh:10; // Device size high 10 bits [73:64]
UINT32 Reserved4:2; // Reserved [75:74]
UINT32 DsrImp:1; // DSR implemented [76:76]
UINT32 ReadBlkMisalign:1; // Read block misalignment [77:77]
UINT32 WriteBlkMisalign:1; // Write block misalignment [78:78]
UINT32 ReadBlPartial:1; // Partial blocks for read allowed [79:79]
UINT32 ReadBlLen:4; // Max. read data block length [83:80]
UINT32 Ccc:12; // Card command classes [95:84]
UINT32 TranSpeed:8; // Max. data transfer rate [103:96]
UINT32 Nsac:8; // Data read access-time in CLK cycles (NSAC*100) [111:104]
UINT32 Taac:8; // Data read access-time [119:112]
UINT32 Reserved5:6; // Reserved [125:120]
UINT32 CsdStructure:2; // CSD structure [127:126]
} SD_CSD;
typedef struct {
UINT32 NotUsed:1; // Not used [0:0]
UINT32 Crc:7; // CRC [7:1]
UINT32 Reserved:2; // Reserved [9:8]
UINT32 FileFormat:2; // File format [11:10]
UINT32 TmpWriteProtect:1; // Temporary write protection [12:12]
UINT32 PermWriteProtect:1; // Permanent write protection [13:13]
UINT32 Copy:1; // Copy flag (OTP) [14:14]
UINT32 FileFormatGrp:1; // File format group [15:15]
UINT32 Reserved1:5; // Reserved [20:16]
UINT32 WriteBlPartial:1; // Partial blocks for write allowed [21:21]
UINT32 WriteBlLen:4; // Max. write data block length [25:22]
UINT32 R2WFactor:3; // Write speed factor [28:26]
UINT32 Reserved2:2; // Manufacturer default ECC [30:29]
UINT32 WpGrpEnable:1; // Write protect group enable [31:31]
UINT32 WpGrpSize:7; // Write protect group size [38:32]
UINT32 SectorSize:7; // Erase sector size [45:39]
UINT32 EraseBlkEn:1; // Erase single block enable [46:46]
UINT32 Reserved3:1; // Reserved [47:47]
UINT32 CSizeLow:16; // Device size low 16 bits [63:48]
UINT32 CSizeHigh:6; // Device size high 6 bits [69:64]
UINT32 Reserved4:6; // Reserved [75:70]
UINT32 DsrImp:1; // DSR implemented [76:76]
UINT32 ReadBlkMisalign:1; // Read block misalignment [77:77]
UINT32 WriteBlkMisalign:1; // Write block misalignment [78:78]
UINT32 ReadBlPartial:1; // Partial blocks for read allowed [79:79]
UINT32 ReadBlLen:4; // Max. read data block length [83:80]
UINT32 Ccc:12; // Card command classes [95:84]
UINT32 TranSpeed:8; // Max. data transfer rate [103:96]
UINT32 Nsac:8; // Data read access-time in CLK cycles (NSAC*100) [111:104]
UINT32 Taac:8; // Data read access-time [119:112]
UINT32 Reserved5:6; // Reserved [125:120]
UINT32 CsdStructure:2; // CSD structure [127:126]
} SD_CSD2;
typedef struct {
UINT32 Reserved; // Reserved [31:0]
UINT32 CmdSupport:4; // Command Support bits [35:32]
UINT32 Reserved1:6; // Reserved [41:36]
UINT32 SdSpec4:1; // Spec. Version 4.00 or higher [42:42]
UINT32 ExSecurity:4; // Extended Security Support [46:43]
UINT32 SdSpec3:1; // Spec. Version 3.00 or higher [47:47]
UINT32 SdBusWidths:4; // DAT Bus widths supported [51:48]
UINT32 SdSecurity:3; // CPRM security support [54:52]
UINT32 DataStatAfterErase:1; // Data status after erases [55]
UINT32 SdSpec:4; // SD Memory Card Spec. Version [59:56]
UINT32 ScrStructure:4; // SCR Structure [63:60]
} SD_SCR;
#pragma pack()
#endif

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/** @file
This file contains definitions for the SPD fields on an SDRAM.
Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _SDRAM_SPD_H_
#define _SDRAM_SPD_H_
#include <IndustryStandard/SdramSpdDdr3.h>
#include <IndustryStandard/SdramSpdDdr4.h>
#include <IndustryStandard/SdramSpdLpDdr.h>
//
// SDRAM SPD field definitions
//
#define SPD_MEMORY_TYPE 2
#define SPD_SDRAM_ROW_ADDR 3
#define SPD_SDRAM_COL_ADDR 4
#define SPD_SDRAM_MODULE_ROWS 5
#define SPD_SDRAM_MODULE_DATA_WIDTH_LSB 6
#define SPD_SDRAM_MODULE_DATA_WIDTH_MSB 7
#define SPD_SDRAM_ECC_SUPPORT 11
#define SPD_SDRAM_REFRESH 12
#define SPD_SDRAM_WIDTH 13
#define SPD_SDRAM_ERROR_WIDTH 14
#define SPD_SDRAM_BURST_LENGTH 16
#define SPD_SDRAM_NO_OF_BANKS 17
#define SPD_SDRAM_CAS_LATENCY 18
#define SPD_SDRAM_MODULE_ATTR 21
#define SPD_SDRAM_TCLK1_PULSE 9 ///< cycle time for highest cas latency
#define SPD_SDRAM_TAC1_PULSE 10 ///< access time for highest cas latency
#define SPD_SDRAM_TCLK2_PULSE 23 ///< cycle time for 2nd highest cas latency
#define SPD_SDRAM_TAC2_PULSE 24 ///< access time for 2nd highest cas latency
#define SPD_SDRAM_TCLK3_PULSE 25 ///< cycle time for 3rd highest cas latency
#define SPD_SDRAM_TAC3_PULSE 26 ///< access time for 3rd highest cas latency
#define SPD_SDRAM_MIN_PRECHARGE 27
#define SPD_SDRAM_ACTIVE_MIN 28
#define SPD_SDRAM_RAS_CAS 29
#define SPD_SDRAM_RAS_PULSE 30
#define SPD_SDRAM_DENSITY 31
//
// Memory Type Definitions
//
#define SPD_VAL_SDR_TYPE 4 ///< SDR SDRAM memory
#define SPD_VAL_DDR_TYPE 7 ///< DDR SDRAM memory
#define SPD_VAL_DDR2_TYPE 8 ///< DDR2 SDRAM memory
#define SPD_VAL_DDR3_TYPE 11 ///< DDR3 SDRAM memory
#define SPD_VAL_DDR4_TYPE 12 ///< DDR4 SDRAM memory
#define SPD_VAL_LPDDR3_TYPE 15 ///< LPDDR3 SDRAM memory
#define SPD_VAL_LPDDR4_TYPE 16 ///< LPDDR4 SDRAM memory
//
// ECC Type Definitions
//
#define SPD_ECC_TYPE_NONE 0x00 ///< No error checking
#define SPD_ECC_TYPE_PARITY 0x01 ///< No error checking
#define SPD_ECC_TYPE_ECC 0x02 ///< Error checking only
//
// Module Attributes (Bit positions)
//
#define SPD_BUFFERED 0x01
#define SPD_REGISTERED 0x02
#endif

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/** @file
This file contains definitions for SPD DDR3.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
- Serial Presence Detect (SPD) for DDR3 SDRAM Modules Document Release 6
http://www.jedec.org/sites/default/files/docs/4_01_02_11R21A.pdf
**/
#ifndef _SDRAM_SPD_DDR3_H_
#define _SDRAM_SPD_DDR3_H_
#pragma pack (push, 1)
typedef union {
struct {
UINT8 BytesUsed : 4; ///< Bits 3:0
UINT8 BytesTotal : 3; ///< Bits 6:4
UINT8 CrcCoverage : 1; ///< Bits 7:7
} Bits;
UINT8 Data;
} SPD3_DEVICE_DESCRIPTION_STRUCT;
typedef union {
struct {
UINT8 Minor : 4; ///< Bits 3:0
UINT8 Major : 4; ///< Bits 7:4
} Bits;
UINT8 Data;
} SPD3_REVISION_STRUCT;
typedef union {
struct {
UINT8 Type : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD3_DRAM_DEVICE_TYPE_STRUCT;
typedef union {
struct {
UINT8 ModuleType : 4; ///< Bits 3:0
UINT8 Reserved : 4; ///< Bits 7:4
} Bits;
UINT8 Data;
} SPD3_MODULE_TYPE_STRUCT;
typedef union {
struct {
UINT8 Density : 4; ///< Bits 3:0
UINT8 BankAddress : 3; ///< Bits 6:4
UINT8 Reserved : 1; ///< Bits 7:7
} Bits;
UINT8 Data;
} SPD3_SDRAM_DENSITY_BANKS_STRUCT;
typedef union {
struct {
UINT8 ColumnAddress : 3; ///< Bits 2:0
UINT8 RowAddress : 3; ///< Bits 5:3
UINT8 Reserved : 2; ///< Bits 7:6
} Bits;
UINT8 Data;
} SPD3_SDRAM_ADDRESSING_STRUCT;
typedef union {
struct {
UINT8 OperationAt1_50 : 1; ///< Bits 0:0
UINT8 OperationAt1_35 : 1; ///< Bits 1:1
UINT8 OperationAt1_25 : 1; ///< Bits 2:2
UINT8 Reserved : 5; ///< Bits 7:3
} Bits;
UINT8 Data;
} SPD3_MODULE_NOMINAL_VOLTAGE_STRUCT;
typedef union {
struct {
UINT8 SdramDeviceWidth : 3; ///< Bits 2:0
UINT8 RankCount : 3; ///< Bits 5:3
UINT8 Reserved : 2; ///< Bits 7:6
} Bits;
UINT8 Data;
} SPD3_MODULE_ORGANIZATION_STRUCT;
typedef union {
struct {
UINT8 PrimaryBusWidth : 3; ///< Bits 2:0
UINT8 BusWidthExtension : 2; ///< Bits 4:3
UINT8 Reserved : 3; ///< Bits 7:5
} Bits;
UINT8 Data;
} SPD3_MODULE_MEMORY_BUS_WIDTH_STRUCT;
typedef union {
struct {
UINT8 Divisor : 4; ///< Bits 3:0
UINT8 Dividend : 4; ///< Bits 7:4
} Bits;
UINT8 Data;
} SPD3_FINE_TIMEBASE_STRUCT;
typedef union {
struct {
UINT8 Dividend : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD3_MEDIUM_TIMEBASE_DIVIDEND_STRUCT;
typedef union {
struct {
UINT8 Divisor : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD3_MEDIUM_TIMEBASE_DIVISOR_STRUCT;
typedef struct {
SPD3_MEDIUM_TIMEBASE_DIVIDEND_STRUCT Dividend; ///< Medium Timebase (MTB) Dividend
SPD3_MEDIUM_TIMEBASE_DIVISOR_STRUCT Divisor; ///< Medium Timebase (MTB) Divisor
} SPD3_MEDIUM_TIMEBASE;
typedef union {
struct {
UINT8 tCKmin : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD3_TCK_MIN_MTB_STRUCT;
typedef union {
struct {
UINT16 Cl4 : 1; ///< Bits 0:0
UINT16 Cl5 : 1; ///< Bits 1:1
UINT16 Cl6 : 1; ///< Bits 2:2
UINT16 Cl7 : 1; ///< Bits 3:3
UINT16 Cl8 : 1; ///< Bits 4:4
UINT16 Cl9 : 1; ///< Bits 5:5
UINT16 Cl10 : 1; ///< Bits 6:6
UINT16 Cl11 : 1; ///< Bits 7:7
UINT16 Cl12 : 1; ///< Bits 8:8
UINT16 Cl13 : 1; ///< Bits 9:9
UINT16 Cl14 : 1; ///< Bits 10:10
UINT16 Cl15 : 1; ///< Bits 11:11
UINT16 Cl16 : 1; ///< Bits 12:12
UINT16 Cl17 : 1; ///< Bits 13:13
UINT16 Cl18 : 1; ///< Bits 14:14
UINT16 Reserved : 1; ///< Bits 15:15
} Bits;
UINT16 Data;
UINT8 Data8[2];
} SPD3_CAS_LATENCIES_SUPPORTED_STRUCT;
typedef union {
struct {
UINT8 tAAmin : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD3_TAA_MIN_MTB_STRUCT;
typedef union {
struct {
UINT8 tWRmin : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD3_TWR_MIN_MTB_STRUCT;
typedef union {
struct {
UINT8 tRCDmin : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD3_TRCD_MIN_MTB_STRUCT;
typedef union {
struct {
UINT8 tRRDmin : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD3_TRRD_MIN_MTB_STRUCT;
typedef union {
struct {
UINT8 tRPmin : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD3_TRP_MIN_MTB_STRUCT;
typedef union {
struct {
UINT8 tRASminUpper : 4; ///< Bits 3:0
UINT8 tRCminUpper : 4; ///< Bits 7:4
} Bits;
UINT8 Data;
} SPD3_TRAS_TRC_MIN_MTB_STRUCT;
typedef union {
struct {
UINT8 tRASmin : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD3_TRAS_MIN_MTB_STRUCT;
typedef union {
struct {
UINT8 tRCmin : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD3_TRC_MIN_MTB_STRUCT;
typedef union {
struct {
UINT16 tRFCmin : 16; ///< Bits 15:0
} Bits;
UINT16 Data;
UINT8 Data8[2];
} SPD3_TRFC_MIN_MTB_STRUCT;
typedef union {
struct {
UINT8 tWTRmin : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD3_TWTR_MIN_MTB_STRUCT;
typedef union {
struct {
UINT8 tRTPmin : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD3_TRTP_MIN_MTB_STRUCT;
typedef union {
struct {
UINT8 tFAWminUpper : 4; ///< Bits 3:0
UINT8 Reserved : 4; ///< Bits 7:4
} Bits;
UINT8 Data;
} SPD3_TFAW_MIN_MTB_UPPER_STRUCT;
typedef union {
struct {
UINT8 tFAWmin : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD3_TFAW_MIN_MTB_STRUCT;
typedef union {
struct {
UINT8 Rzq6 : 1; ///< Bits 0:0
UINT8 Rzq7 : 1; ///< Bits 1:1
UINT8 Reserved : 5; ///< Bits 6:2
UINT8 DllOff : 1; ///< Bits 7:7
} Bits;
UINT8 Data;
} SPD3_SDRAM_OPTIONAL_FEATURES_STRUCT;
typedef union {
struct {
UINT8 ExtendedTemperatureRange : 1; ///< Bits 0:0
UINT8 ExtendedTemperatureRefreshRate : 1; ///< Bits 1:1
UINT8 AutoSelfRefresh : 1; ///< Bits 2:2
UINT8 OnDieThermalSensor : 1; ///< Bits 3:3
UINT8 Reserved : 3; ///< Bits 6:4
UINT8 PartialArraySelfRefresh : 1; ///< Bits 7:7
} Bits;
UINT8 Data;
} SPD3_SDRAM_THERMAL_REFRESH_STRUCT;
typedef union {
struct {
UINT8 ThermalSensorAccuracy : 7; ///< Bits 6:0
UINT8 ThermalSensorPresence : 1; ///< Bits 7:7
} Bits;
UINT8 Data;
} SPD3_MODULE_THERMAL_SENSOR_STRUCT;
typedef union {
struct {
UINT8 SignalLoading : 2; ///< Bits 1:0
UINT8 Reserved : 2; ///< Bits 3:2
UINT8 DieCount : 3; ///< Bits 6:4
UINT8 SdramDeviceType : 1; ///< Bits 7:7
} Bits;
UINT8 Data;
} SPD3_SDRAM_DEVICE_TYPE_STRUCT;
typedef union {
struct {
INT8 tCKminFine : 8; ///< Bits 7:0
} Bits;
INT8 Data;
} SPD3_TCK_MIN_FTB_STRUCT;
typedef union {
struct {
INT8 tAAminFine : 8; ///< Bits 7:0
} Bits;
INT8 Data;
} SPD3_TAA_MIN_FTB_STRUCT;
typedef union {
struct {
INT8 tRCDminFine : 8; ///< Bits 7:0
} Bits;
INT8 Data;
} SPD3_TRCD_MIN_FTB_STRUCT;
typedef union {
struct {
INT8 tRPminFine : 8; ///< Bits 7:0
} Bits;
INT8 Data;
} SPD3_TRP_MIN_FTB_STRUCT;
typedef union {
struct {
INT8 tRCminFine : 8; ///< Bits 7:0
} Bits;
INT8 Data;
} SPD3_TRC_MIN_FTB_STRUCT;
typedef union {
struct {
UINT8 MaximumActivateCount : 4; ///< Bits 3:0
UINT8 MaximumActivateWindow : 2; ///< Bits 5:4
UINT8 VendorSpecific : 2; ///< Bits 7:6
} Bits;
UINT8 Data;
} SPD3_MAXIMUM_ACTIVE_COUNT_STRUCT;
typedef union {
struct {
UINT8 Height : 5; ///< Bits 4:0
UINT8 RawCardExtension : 3; ///< Bits 7:5
} Bits;
UINT8 Data;
} SPD3_UNBUF_MODULE_NOMINAL_HEIGHT;
typedef union {
struct {
UINT8 FrontThickness : 4; ///< Bits 3:0
UINT8 BackThickness : 4; ///< Bits 7:4
} Bits;
UINT8 Data;
} SPD3_UNBUF_MODULE_NOMINAL_THICKNESS;
typedef union {
struct {
UINT8 Card : 5; ///< Bits 4:0
UINT8 Revision : 2; ///< Bits 6:5
UINT8 Extension : 1; ///< Bits 7:7
} Bits;
UINT8 Data;
} SPD3_UNBUF_REFERENCE_RAW_CARD;
typedef union {
struct {
UINT8 MappingRank1 : 1; ///< Bits 0:0
UINT8 Reserved : 7; ///< Bits 7:1
} Bits;
UINT8 Data;
} SPD3_UNBUF_ADDRESS_MAPPING;
typedef union {
struct {
UINT8 Height : 5; ///< Bits 4:0
UINT8 Reserved : 3; ///< Bits 7:5
} Bits;
UINT8 Data;
} SPD3_RDIMM_MODULE_NOMINAL_HEIGHT;
typedef union {
struct {
UINT8 FrontThickness : 4; ///< Bits 3:0
UINT8 BackThickness : 4; ///< Bits 7:4
} Bits;
UINT8 Data;
} SPD3_RDIMM_MODULE_NOMINAL_THICKNESS;
typedef union {
struct {
UINT8 Card : 5; ///< Bits 4:0
UINT8 Revision : 2; ///< Bits 6:5
UINT8 Extension : 1; ///< Bits 7:7
} Bits;
UINT8 Data;
} SPD3_RDIMM_REFERENCE_RAW_CARD;
typedef union {
struct {
UINT8 RegisterCount : 2; ///< Bits 1:0
UINT8 DramRowCount : 2; ///< Bits 3:2
UINT8 RegisterType : 4; ///< Bits 7:4
} Bits;
UINT8 Data;
} SPD3_RDIMM_MODULE_ATTRIBUTES;
typedef union {
struct {
UINT8 HeatSpreaderThermalCharacteristics : 7; ///< Bits 6:0
UINT8 HeatSpreaderSolution : 1; ///< Bits 7:7
} Bits;
UINT8 Data;
} SPD3_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION;
typedef union {
struct {
UINT16 ContinuationCount : 7; ///< Bits 6:0
UINT16 ContinuationParity : 1; ///< Bits 7:7
UINT16 LastNonZeroByte : 8; ///< Bits 15:8
} Bits;
UINT16 Data;
UINT8 Data8[2];
} SPD3_MANUFACTURER_ID_CODE;
typedef union {
struct {
UINT8 RegisterRevisionNumber; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD3_RDIMM_REGISTER_REVISION_NUMBER;
typedef union {
struct {
UINT8 Bit0 : 1; ///< Bits 0:0
UINT8 Bit1 : 1; ///< Bits 1:1
UINT8 Bit2 : 1; ///< Bits 2:2
UINT8 Reserved : 5; ///< Bits 7:3
} Bits;
UINT8 Data;
} SPD3_RDIMM_REGISTER_TYPE;
typedef union {
struct {
UINT8 Reserved : 4; ///< Bits 0:3
UINT8 CommandAddressAOutputs : 2; ///< Bits 5:4
UINT8 CommandAddressBOutputs : 2; ///< Bits 7:6
} Bits;
UINT8 Data;
} SPD3_RDIMM_REGISTER_CONTROL_COMMAND_ADDRESS;
typedef union {
struct {
UINT8 ControlSignalsAOutputs : 2; ///< Bits 0:1
UINT8 ControlSignalsBOutputs : 2; ///< Bits 3:2
UINT8 Y1Y3ClockOutputs : 2; ///< Bits 5:4
UINT8 Y0Y2ClockOutputs : 2; ///< Bits 7:6
} Bits;
UINT8 Data;
} SPD3_RDIMM_REGISTER_CONTROL_CONTROL_CLOCK;
typedef union {
struct {
UINT8 Reserved0 : 4; ///< Bits 0:3
UINT8 Reserved1 : 4; ///< Bits 7:4
} Bits;
UINT8 Data;
} SPD3_RDIMM_REGISTER_CONTROL_RESERVED;
typedef union {
struct {
UINT8 Height : 5; ///< Bits 4:0
UINT8 Reserved : 3; ///< Bits 7:5
} Bits;
UINT8 Data;
} SPD3_LRDIMM_MODULE_NOMINAL_HEIGHT;
typedef union {
struct {
UINT8 FrontThickness : 4; ///< Bits 3:0
UINT8 BackThickness : 4; ///< Bits 7:4
} Bits;
UINT8 Data;
} SPD3_LRDIMM_MODULE_NOMINAL_THICKNESS;
typedef union {
struct {
UINT8 Card : 5; ///< Bits 4:0
UINT8 Revision : 2; ///< Bits 6:5
UINT8 Extension : 1; ///< Bits 7:7
} Bits;
UINT8 Data;
} SPD3_LRDIMM_REFERENCE_RAW_CARD;
typedef union {
struct {
UINT8 RegisterCount : 2; ///< Bits 1:0
UINT8 DramRowCount : 2; ///< Bits 3:2
UINT8 RegisterType : 4; ///< Bits 7:4
} Bits;
UINT8 Data;
} SPD3_LRDIMM_MODULE_ATTRIBUTES;
typedef union {
struct {
UINT8 AddressCommandPrelaunch : 1; ///< Bits 0:0
UINT8 Rank1Rank5Swap : 1; ///< Bits 1:1
UINT8 Reserved0 : 1; ///< Bits 2:2
UINT8 Reserved1 : 1; ///< Bits 3:3
UINT8 AddressCommandOutputs : 2; ///< Bits 5:4
UINT8 QxCS_nOutputs : 2; ///< Bits 7:6
} Bits;
UINT8 Data;
} SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH;
typedef union {
struct {
UINT8 QxOdtOutputs : 2; ///< Bits 1:0
UINT8 QxCkeOutputs : 2; ///< Bits 3:2
UINT8 Y1Y3ClockOutputs : 2; ///< Bits 5:4
UINT8 Y0Y2ClockOutputs : 2; ///< Bits 7:6
} Bits;
UINT8 Data;
} SPD3_LRDIMM_TIMING_DRIVE_STRENGTH;
typedef union {
struct {
UINT8 YExtendedDelay : 2; ///< Bits 1:0
UINT8 QxCS_n : 2; ///< Bits 3:2
UINT8 QxOdt : 2; ///< Bits 5:4
UINT8 QxCke : 2; ///< Bits 7:6
} Bits;
UINT8 Data;
} SPD3_LRDIMM_EXTENDED_DELAY;
typedef union {
struct {
UINT8 DelayY : 3; ///< Bits 2:0
UINT8 Reserved : 1; ///< Bits 3:3
UINT8 QxCS_n : 4; ///< Bits 7:4
} Bits;
UINT8 Data;
} SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXCS_N_QXCA;
typedef union {
struct {
UINT8 QxCS_n : 4; ///< Bits 3:0
UINT8 QxOdt : 4; ///< Bits 7:4
} Bits;
UINT8 Data;
} SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXODT_QXCKE;
typedef union {
struct {
UINT8 RC8MdqOdtStrength : 3; ///< Bits 2:0
UINT8 RC8Reserved : 1; ///< Bits 3:3
UINT8 RC9MdqOdtStrength : 3; ///< Bits 6:4
UINT8 RC9Reserved : 1; ///< Bits 7:7
} Bits;
UINT8 Data;
} SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH;
typedef union {
struct {
UINT8 RC10DA3ValueR0 : 1; ///< Bits 0:0
UINT8 RC10DA4ValueR0 : 1; ///< Bits 1:1
UINT8 RC10DA3ValueR1 : 1; ///< Bits 2:2
UINT8 RC10DA4ValueR1 : 1; ///< Bits 3:3
UINT8 RC11DA3ValueR0 : 1; ///< Bits 4:4
UINT8 RC11DA4ValueR0 : 1; ///< Bits 5:5
UINT8 RC11DA3ValueR1 : 1; ///< Bits 6:6
UINT8 RC11DA4ValueR1 : 1; ///< Bits 7:7
} Bits;
UINT8 Data;
} SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL;
typedef union {
struct {
UINT8 Driver_Impedance : 2; ///< Bits 1:0
UINT8 Rtt_Nom : 3; ///< Bits 4:2
UINT8 Reserved : 1; ///< Bits 5:5
UINT8 Rtt_WR : 2; ///< Bits 7:6
} Bits;
UINT8 Data;
} SPD3_LRDIMM_MR_1_2;
typedef union {
struct {
UINT8 MinimumDelayTime : 7; ///< Bits 0:6
UINT8 Reserved : 1; ///< Bits 7:7
} Bits;
UINT8 Data;
} SPD3_LRDIMM_MODULE_DELAY_TIME;
typedef struct {
UINT8 Year; ///< Year represented in BCD (00h = 2000)
UINT8 Week; ///< Year represented in BCD (47h = week 47)
} SPD3_MANUFACTURING_DATE;
typedef union {
UINT32 Data;
UINT16 SerialNumber16[2];
UINT8 SerialNumber8[4];
} SPD3_MANUFACTURER_SERIAL_NUMBER;
typedef struct {
UINT8 Location; ///< Module Manufacturing Location
} SPD3_MANUFACTURING_LOCATION;
typedef struct {
SPD3_MANUFACTURER_ID_CODE IdCode; ///< Module Manufacturer ID Code
SPD3_MANUFACTURING_LOCATION Location; ///< Module Manufacturing Location
SPD3_MANUFACTURING_DATE Date; ///< Module Manufacturing Year, in BCD (range: 2000-2255)
SPD3_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< Module Serial Number
} SPD3_UNIQUE_MODULE_ID;
typedef union {
UINT16 Crc[1];
UINT8 Data8[2];
} SPD3_CYCLIC_REDUNDANCY_CODE;
typedef struct {
SPD3_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2
SPD3_REVISION_STRUCT Revision; ///< 1 SPD Revision
SPD3_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type
SPD3_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type
SPD3_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks
SPD3_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing
SPD3_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 6 Module Nominal Voltage, VDD
SPD3_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 7 Module Organization
SPD3_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 8 Module Memory Bus Width
SPD3_FINE_TIMEBASE_STRUCT FineTimebase; ///< 9 Fine Timebase (FTB) Dividend / Divisor
SPD3_MEDIUM_TIMEBASE MediumTimebase; ///< 10-11 Medium Timebase (MTB) Dividend
SPD3_TCK_MIN_MTB_STRUCT tCKmin; ///< 12 SDRAM Minimum Cycle Time (tCKmin)
UINT8 Reserved0; ///< 13 Reserved
SPD3_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 14-15 CAS Latencies Supported
SPD3_TAA_MIN_MTB_STRUCT tAAmin; ///< 16 Minimum CAS Latency Time (tAAmin)
SPD3_TWR_MIN_MTB_STRUCT tWRmin; ///< 17 Minimum Write Recovery Time (tWRmin)
SPD3_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
SPD3_TRRD_MIN_MTB_STRUCT tRRDmin; ///< 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
SPD3_TRP_MIN_MTB_STRUCT tRPmin; ///< 20 Minimum Row Precharge Delay Time (tRPmin)
SPD3_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 21 Upper Nibbles for tRAS and tRC
SPD3_TRAS_MIN_MTB_STRUCT tRASmin; ///< 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte
SPD3_TRC_MIN_MTB_STRUCT tRCmin; ///< 23 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte
SPD3_TRFC_MIN_MTB_STRUCT tRFCmin; ///< 24-25 Minimum Refresh Recovery Delay Time (tRFCmin)
SPD3_TWTR_MIN_MTB_STRUCT tWTRmin; ///< 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
SPD3_TRTP_MIN_MTB_STRUCT tRTPmin; ///< 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
SPD3_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 28 Upper Nibble for tFAW
SPD3_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 29 Minimum Four Activate Window Delay Time (tFAWmin)
SPD3_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 30 SDRAM Optional Features
SPD3_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 31 SDRAM Thermal And Refresh Options
SPD3_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 32 Module Thermal Sensor
SPD3_SDRAM_DEVICE_TYPE_STRUCT SdramDeviceType; ///< 33 SDRAM Device Type
SPD3_TCK_MIN_FTB_STRUCT tCKminFine; ///< 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
SPD3_TAA_MIN_FTB_STRUCT tAAminFine; ///< 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
SPD3_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
SPD3_TRP_MIN_FTB_STRUCT tRPminFine; ///< 37 Minimum Row Precharge Delay Time (tRPmin)
SPD3_TRC_MIN_FTB_STRUCT tRCminFine; ///< 38 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)
UINT8 Reserved1[40 - 39 + 1]; ///< 39 - 40 Reserved
SPD3_MAXIMUM_ACTIVE_COUNT_STRUCT MacValue; ///< 41 SDRAM Maximum Active Count (MAC) Value
UINT8 Reserved2[59 - 42 + 1]; ///< 42 - 59 Reserved
} SPD3_BASE_SECTION;
typedef struct {
SPD3_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height
SPD3_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness
SPD3_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used
SPD3_UNBUF_ADDRESS_MAPPING AddressMappingEdgeConn; ///< 63 Address Mapping from Edge Connector to DRAM
UINT8 Reserved[116 - 64 + 1]; ///< 64-116 Reserved
} SPD3_MODULE_UNBUFFERED;
typedef struct {
SPD3_RDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height
SPD3_RDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness
SPD3_RDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used
SPD3_RDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 63 DIMM Module Attributes
SPD3_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION ThermalHeatSpreaderSolution; ///< 64 RDIMM Thermal Heat Spreader Solution
SPD3_MANUFACTURER_ID_CODE RegisterManufacturerIdCode; ///< 65-66 Register Manufacturer ID Code
SPD3_RDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber; ///< 67 Register Revision Number
SPD3_RDIMM_REGISTER_TYPE RegisterType; ///< 68 Register Type
SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc1Rc0; ///< 69 RC1 (MS Nibble) / RC0 (LS Nibble) - Reserved
SPD3_RDIMM_REGISTER_CONTROL_COMMAND_ADDRESS Rc3Rc2; ///< 70 RC3 (MS Nibble) / RC2 (LS Nibble) - Drive Strength, Command/Address
SPD3_RDIMM_REGISTER_CONTROL_CONTROL_CLOCK Rc5Rc4; ///< 71 RC5 (MS Nibble) / RC4 (LS Nibble) - Drive Strength, Control and Clock
SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc7Rc6; ///< 72 RC7 (MS Nibble) / RC6 (LS Nibble) - Reserved for Register Vendor
SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc9Rc8; ///< 73 RC9 (MS Nibble) / RC8 (LS Nibble) - Reserved
SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc11Rc10; ///< 74 RC11 (MS Nibble) / RC10 (LS Nibble) - Reserved
SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc13Rc12; ///< 75 RC12 (MS Nibble) / RC12 (LS Nibble) - Reserved
SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc15Rc14; ///< 76 RC15 (MS Nibble) / RC14 (LS Nibble) - Reserved
UINT8 Reserved[116 - 77 + 1]; ///< 77-116 Reserved
} SPD3_MODULE_REGISTERED;
typedef struct {
SPD3_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height
SPD3_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness
SPD3_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used
UINT8 Reserved[116 - 63 + 1]; ///< 63-116 Reserved
} SPD3_MODULE_CLOCKED;
typedef struct {
SPD3_LRDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height
SPD3_LRDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness
SPD3_LRDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used
SPD3_LRDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 63 Module Attributes
UINT8 MemoryBufferRevisionNumber; ///< 64 Memory Buffer Revision Number
SPD3_MANUFACTURER_ID_CODE ManufacturerIdCode; ///< 65-66 Memory Buffer Manufacturer ID Code
SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH TimingControlDriveStrengthCaCs; ///< 67 F0RC3 / F0RC2 - Timing Control & Drive Strength, CA & CS
SPD3_LRDIMM_TIMING_DRIVE_STRENGTH DriveStrength; ///< 68 F0RC5 / F0RC4 - Drive Strength, ODT & CKE and Y
SPD3_LRDIMM_EXTENDED_DELAY ExtendedDelay; ///< 69 F1RC11 / F1RC8 - Extended Delay for Y, CS and ODT & CKE
SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXCS_N_QXCA AdditiveDelayForCsCa; ///< 70 F1RC13 / F1RC12 - Additive Delay for CS and CA
SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXODT_QXCKE AdditiveDelayForOdtCke; ///< 71 F1RC15 / F1RC14 - Additive Delay for ODT & CKE
SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH MdqTerminationDriveStrengthFor800_1066; ///< 72 F1RC15 / F1RC14 - Additive Delay for ODT & CKE
SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxOdtControlFor800_1066; ///< 73 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066
SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxOdtControlFor800_1066; ///< 74 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066
SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxOdtControlFor800_1066; ///< 75 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066
SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxOdtControlFor800_1066; ///< 76 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066
SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor800_1066; ///< 77 MR1,2 Registers for 800 & 1066
SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH MdqTerminationDriveStrengthFor1333_1600; ///< 78 F1RC15 / F1RC14 - Additive Delay for ODT & CKE
SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxOdtControlFor1333_1600; ///< 79 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066
SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxOdtControlFor1333_1600; ///< 80 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066
SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxOdtControlFor1333_1600; ///< 81 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066
SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxOdtControlFor1333_1600; ///< 82 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066
SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor1333_1600; ///< 83 MR1,2 Registers for 800 & 1066
SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH MdqTerminationDriveStrengthFor1866_2133; ///< 84 F1RC15 / F1RC14 - Additive Delay for ODT & CKE
SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxOdtControlFor1866_2133; ///< 85 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066
SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxOdtControlFor1866_2133; ///< 86 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066
SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxOdtControlFor1866_2133; ///< 87 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066
SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxOdtControlFor1866_2133; ///< 88 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066
SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor1866_2133; ///< 89 MR1,2 Registers for 800 & 1066
SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_5V; ///< 90 Minimum Module Delay Time for 1.5 V
SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_5V; ///< 91 Maximum Module Delay Time for 1.5 V
SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_35V; ///< 92 Minimum Module Delay Time for 1.35 V
SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_35V; ///< 93 Maximum Module Delay Time for 1.35 V
SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_25V; ///< 94 Minimum Module Delay Time for 1.25 V
SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_25V; ///< 95 Maximum Module Delay Time for 1.25 V
UINT8 Reserved[101 - 96 + 1]; ///< 96-101 Reserved
UINT8 PersonalityByte[116 - 102 + 1]; ///< 102-116 Memory Buffer Personality Bytes
} SPD3_MODULE_LOADREDUCED;
typedef union {
SPD3_MODULE_UNBUFFERED Unbuffered; ///< 128-255 Unbuffered Memory Module Types
SPD3_MODULE_REGISTERED Registered; ///< 128-255 Registered Memory Module Types
SPD3_MODULE_CLOCKED Clocked; ///< 128-255 Registered Memory Module Types
SPD3_MODULE_LOADREDUCED LoadReduced; ///< 128-255 Load Reduced Memory Module Types
} SPD3_MODULE_SPECIFIC;
typedef struct {
UINT8 ModulePartNumber[145 - 128 + 1]; ///< 128-145 Module Part Number
} SPD3_MODULE_PART_NUMBER;
typedef struct {
UINT8 ModuleRevisionCode[147 - 146 + 1]; ///< 146-147 Module Revision Code
} SPD3_MODULE_REVISION_CODE;
typedef struct {
UINT8 ManufacturerSpecificData[175 - 150 + 1];///< 150-175 Manufacturer's Specific Data
} SPD3_MANUFACTURER_SPECIFIC;
///
/// DDR3 Serial Presence Detect structure
///
typedef struct {
SPD3_BASE_SECTION General; ///< 0-59 General Section
SPD3_MODULE_SPECIFIC Module; ///< 60-116 Module-Specific Section
SPD3_UNIQUE_MODULE_ID ModuleId; ///< 117-125 Unique Module ID
SPD3_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC)
SPD3_MODULE_PART_NUMBER ModulePartNumber; ///< 128-145 Module Part Number
SPD3_MODULE_REVISION_CODE ModuleRevisionCode; ///< 146-147 Module Revision Code
SPD3_MANUFACTURER_ID_CODE DramIdCode; ///< 148-149 Dram Manufacturer ID Code
SPD3_MANUFACTURER_SPECIFIC ManufacturerSpecificData; ///< 150-175 Manufacturer's Specific Data
UINT8 Reserved[255 - 176 + 1]; ///< 176-255 Open for Customer Use
} SPD_DDR3;
#pragma pack (pop)
#endif

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MdePkg/Include/IndustryStandard/SdramSpdDdr4.h Normal file
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/** @file
This file contains definitions for SPD DDR4.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
- Serial Presence Detect (SPD) for DDR4 SDRAM Modules Document Release 4
http://www.jedec.org/standards-documents/docs/spd412l-4
**/
#ifndef _SDRAM_SPD_DDR4_H_
#define _SDRAM_SPD_DDR4_H_
#pragma pack (push, 1)
typedef union {
struct {
UINT8 BytesUsed : 4; ///< Bits 3:0
UINT8 BytesTotal : 3; ///< Bits 6:4
UINT8 CrcCoverage : 1; ///< Bits 7:7
} Bits;
UINT8 Data;
} SPD4_DEVICE_DESCRIPTION_STRUCT;
typedef union {
struct {
UINT8 Minor : 4; ///< Bits 3:0
UINT8 Major : 4; ///< Bits 7:4
} Bits;
UINT8 Data;
} SPD4_REVISION_STRUCT;
typedef union {
struct {
UINT8 Type : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD4_DRAM_DEVICE_TYPE_STRUCT;
typedef union {
struct {
UINT8 ModuleType : 4; ///< Bits 3:0
UINT8 HybridMedia : 3; ///< Bits 6:4
UINT8 Hybrid : 1; ///< Bits 7:7
} Bits;
UINT8 Data;
} SPD4_MODULE_TYPE_STRUCT;
typedef union {
struct {
UINT8 Density : 4; ///< Bits 3:0
UINT8 BankAddress : 2; ///< Bits 5:4
UINT8 BankGroup : 2; ///< Bits 7:6
} Bits;
UINT8 Data;
} SPD4_SDRAM_DENSITY_BANKS_STRUCT;
typedef union {
struct {
UINT8 ColumnAddress : 3; ///< Bits 2:0
UINT8 RowAddress : 3; ///< Bits 5:3
UINT8 Reserved : 2; ///< Bits 7:6
} Bits;
UINT8 Data;
} SPD4_SDRAM_ADDRESSING_STRUCT;
typedef union {
struct {
UINT8 SignalLoading : 2; ///< Bits 1:0
UINT8 Reserved : 2; ///< Bits 3:2
UINT8 DieCount : 3; ///< Bits 6:4
UINT8 SdramPackageType : 1; ///< Bits 7:7
} Bits;
UINT8 Data;
} SPD4_PRIMARY_SDRAM_PACKAGE_TYPE_STRUCT;
typedef union {
struct {
UINT8 MaximumActivateCount : 4; ///< Bits 3:0
UINT8 MaximumActivateWindow : 2; ///< Bits 5:4
UINT8 Reserved : 2; ///< Bits 7:6
} Bits;
UINT8 Data;
} SPD4_SDRAM_OPTIONAL_FEATURES_STRUCT;
typedef union {
struct {
UINT8 Reserved : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD4_SDRAM_THERMAL_REFRESH_STRUCT;
typedef union {
struct {
UINT8 Reserved : 5; ///< Bits 4:0
UINT8 SoftPPR : 1; ///< Bits 5:5
UINT8 PostPackageRepair : 2; ///< Bits 7:6
} Bits;
UINT8 Data;
} SPD4_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT;
typedef union {
struct {
UINT8 SignalLoading : 2; ///< Bits 1:0
UINT8 DRAMDensityRatio : 2; ///< Bits 3:2
UINT8 DieCount : 3; ///< Bits 6:4
UINT8 SdramPackageType : 1; ///< Bits 7:7
} Bits;
UINT8 Data;
} SPD4_SECONDARY_SDRAM_PACKAGE_TYPE_STRUCT;
typedef union {
struct {
UINT8 OperationAt1_20 : 1; ///< Bits 0:0
UINT8 EndurantAt1_20 : 1; ///< Bits 1:1
UINT8 Reserved : 6; ///< Bits 7:2
} Bits;
UINT8 Data;
} SPD4_MODULE_NOMINAL_VOLTAGE_STRUCT;
typedef union {
struct {
UINT8 SdramDeviceWidth : 3; ///< Bits 2:0
UINT8 RankCount : 3; ///< Bits 5:3
UINT8 RankMix : 1; ///< Bits 6:6
UINT8 Reserved : 1; ///< Bits 7:7
} Bits;
UINT8 Data;
} SPD4_MODULE_ORGANIZATION_STRUCT;
typedef union {
struct {
UINT8 PrimaryBusWidth : 3; ///< Bits 2:0
UINT8 BusWidthExtension : 2; ///< Bits 4:3
UINT8 Reserved : 3; ///< Bits 7:5
} Bits;
UINT8 Data;
} SPD4_MODULE_MEMORY_BUS_WIDTH_STRUCT;
typedef union {
struct {
UINT8 Reserved : 7; ///< Bits 6:0
UINT8 ThermalSensorPresence : 1; ///< Bits 7:7
} Bits;
UINT8 Data;
} SPD4_MODULE_THERMAL_SENSOR_STRUCT;
typedef union {
struct {
UINT8 ExtendedBaseModuleType : 4; ///< Bits 3:0
UINT8 Reserved : 4; ///< Bits 7:4
} Bits;
UINT8 Data;
} SPD4_EXTENDED_MODULE_TYPE_STRUCT;
typedef union {
struct {
UINT8 Fine : 2; ///< Bits 1:0
UINT8 Medium : 2; ///< Bits 3:2
UINT8 Reserved : 4; ///< Bits 7:4
} Bits;
UINT8 Data;
} SPD4_TIMEBASE_STRUCT;
typedef union {
struct {
UINT8 tCKmin : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD4_TCK_MIN_MTB_STRUCT;
typedef union {
struct {
UINT8 tCKmax : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD4_TCK_MAX_MTB_STRUCT;
typedef union {
struct {
UINT32 Cl7 : 1; ///< Bits 0:0
UINT32 Cl8 : 1; ///< Bits 1:1
UINT32 Cl9 : 1; ///< Bits 2:2
UINT32 Cl10 : 1; ///< Bits 3:3
UINT32 Cl11 : 1; ///< Bits 4:4
UINT32 Cl12 : 1; ///< Bits 5:5
UINT32 Cl13 : 1; ///< Bits 6:6
UINT32 Cl14 : 1; ///< Bits 7:7
UINT32 Cl15 : 1; ///< Bits 8:8
UINT32 Cl16 : 1; ///< Bits 9:9
UINT32 Cl17 : 1; ///< Bits 10:10
UINT32 Cl18 : 1; ///< Bits 11:11
UINT32 Cl19 : 1; ///< Bits 12:12
UINT32 Cl20 : 1; ///< Bits 13:13
UINT32 Cl21 : 1; ///< Bits 14:14
UINT32 Cl22 : 1; ///< Bits 15:15
UINT32 Cl23 : 1; ///< Bits 16:16
UINT32 Cl24 : 1; ///< Bits 17:17
UINT32 Cl25 : 1; ///< Bits 18:18
UINT32 Cl26 : 1; ///< Bits 19:19
UINT32 Cl27 : 1; ///< Bits 20:20
UINT32 Cl28 : 1; ///< Bits 21:21
UINT32 Cl29 : 1; ///< Bits 22:22
UINT32 Cl30 : 1; ///< Bits 23:23
UINT32 Cl31 : 1; ///< Bits 24:24
UINT32 Cl32 : 1; ///< Bits 25:25
UINT32 Cl33 : 1; ///< Bits 26:26
UINT32 Cl34 : 1; ///< Bits 27:27
UINT32 Cl35 : 1; ///< Bits 28:28
UINT32 Cl36 : 1; ///< Bits 29:29
UINT32 Reserved : 1; ///< Bits 30:30
UINT32 ClRange : 1; ///< Bits 31:31
} Bits;
struct {
UINT32 Cl23 : 1; ///< Bits 0:0
UINT32 Cl24 : 1; ///< Bits 1:1
UINT32 Cl25 : 1; ///< Bits 2:2
UINT32 Cl26 : 1; ///< Bits 3:3
UINT32 Cl27 : 1; ///< Bits 4:4
UINT32 Cl28 : 1; ///< Bits 5:5
UINT32 Cl29 : 1; ///< Bits 6:6
UINT32 Cl30 : 1; ///< Bits 7:7
UINT32 Cl31 : 1; ///< Bits 8:8
UINT32 Cl32 : 1; ///< Bits 9:9
UINT32 Cl33 : 1; ///< Bits 10:10
UINT32 Cl34 : 1; ///< Bits 11:11
UINT32 Cl35 : 1; ///< Bits 12:12
UINT32 Cl36 : 1; ///< Bits 13:13
UINT32 Cl37 : 1; ///< Bits 14:14
UINT32 Cl38 : 1; ///< Bits 15:15
UINT32 Cl39 : 1; ///< Bits 16:16
UINT32 Cl40 : 1; ///< Bits 17:17
UINT32 Cl41 : 1; ///< Bits 18:18
UINT32 Cl42 : 1; ///< Bits 19:19
UINT32 Cl43 : 1; ///< Bits 20:20
UINT32 Cl44 : 1; ///< Bits 21:21
UINT32 Cl45 : 1; ///< Bits 22:22
UINT32 Cl46 : 1; ///< Bits 23:23
UINT32 Cl47 : 1; ///< Bits 24:24
UINT32 Cl48 : 1; ///< Bits 25:25
UINT32 Cl49 : 1; ///< Bits 26:26
UINT32 Cl50 : 1; ///< Bits 27:27
UINT32 Cl51 : 1; ///< Bits 28:28
UINT32 Cl52 : 1; ///< Bits 29:29
UINT32 Reserved : 1; ///< Bits 30:30
UINT32 ClRange : 1; ///< Bits 31:31
} HighRangeBits;
UINT32 Data;
UINT16 Data16[2];
UINT8 Data8[4];
} SPD4_CAS_LATENCIES_SUPPORTED_STRUCT;
typedef union {
struct {
UINT8 tAAmin : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD4_TAA_MIN_MTB_STRUCT;
typedef union {
struct {
UINT8 tRCDmin : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD4_TRCD_MIN_MTB_STRUCT;
typedef union {
struct {
UINT8 tRPmin : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD4_TRP_MIN_MTB_STRUCT;
typedef union {
struct {
UINT8 tRASminUpper : 4; ///< Bits 3:0
UINT8 tRCminUpper : 4; ///< Bits 7:4
} Bits;
UINT8 Data;
} SPD4_TRAS_TRC_MIN_MTB_STRUCT;
typedef union {
struct {
UINT8 tRASmin : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD4_TRAS_MIN_MTB_STRUCT;
typedef union {
struct {
UINT8 tRCmin : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD4_TRC_MIN_MTB_STRUCT;
typedef union {
struct {
UINT16 tRFCmin : 16; ///< Bits 15:0
} Bits;
UINT16 Data;
UINT8 Data8[2];
} SPD4_TRFC_MIN_MTB_STRUCT;
typedef union {
struct {
UINT8 tFAWminUpper : 4; ///< Bits 3:0
UINT8 Reserved : 4; ///< Bits 7:4
} Bits;
UINT8 Data;
} SPD4_TFAW_MIN_MTB_UPPER_STRUCT;
typedef union {
struct {
UINT8 tFAWmin : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD4_TFAW_MIN_MTB_STRUCT;
typedef union {
struct {
UINT8 tRRDmin : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD4_TRRD_MIN_MTB_STRUCT;
typedef union {
struct {
UINT8 tCCDmin : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD4_TCCD_MIN_MTB_STRUCT;
typedef union {
struct {
UINT8 tWRminMostSignificantNibble : 4; ///< Bits 3:0
UINT8 Reserved : 4; ///< Bits 7:4
} Bits;
UINT8 Data;
} SPD4_TWR_UPPER_NIBBLE_STRUCT;
typedef union {
struct {
UINT8 tWRmin : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD4_TWR_MIN_MTB_STRUCT;
typedef union {
struct {
UINT8 tWTR_SminMostSignificantNibble : 4; ///< Bits 3:0
UINT8 tWTR_LminMostSignificantNibble : 4; ///< Bits 7:4
} Bits;
UINT8 Data;
} SPD4_TWTR_UPPER_NIBBLE_STRUCT;
typedef union {
struct {
UINT8 tWTRmin : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD4_TWTR_MIN_MTB_STRUCT;
typedef union {
struct {
UINT8 BitOrderatSDRAM : 5; ///< Bits 4:0
UINT8 WiredtoUpperLowerNibble : 1; ///< Bits 5:5
UINT8 PackageRankMap : 2; ///< Bits 7:6
} Bits;
UINT8 Data;
} SPD4_CONNECTOR_BIT_MAPPING_BYTE_STRUCT;
typedef union {
struct {
INT8 tCCDminFine : 8; ///< Bits 7:0
} Bits;
INT8 Data;
} SPD4_TCCD_MIN_FTB_STRUCT;
typedef union {
struct {
INT8 tRRDminFine : 8; ///< Bits 7:0
} Bits;
INT8 Data;
} SPD4_TRRD_MIN_FTB_STRUCT;
typedef union {
struct {
INT8 tRCminFine : 8; ///< Bits 7:0
} Bits;
INT8 Data;
} SPD4_TRC_MIN_FTB_STRUCT;
typedef union {
struct {
INT8 tRPminFine : 8; ///< Bits 7:0
} Bits;
INT8 Data;
} SPD4_TRP_MIN_FTB_STRUCT;
typedef union {
struct {
INT8 tRCDminFine : 8; ///< Bits 7:0
} Bits;
INT8 Data;
} SPD4_TRCD_MIN_FTB_STRUCT;
typedef union {
struct {
INT8 tAAminFine : 8; ///< Bits 7:0
} Bits;
INT8 Data;
} SPD4_TAA_MIN_FTB_STRUCT;
typedef union {
struct {
INT8 tCKmaxFine : 8; ///< Bits 7:0
} Bits;
INT8 Data;
} SPD4_TCK_MAX_FTB_STRUCT;
typedef union {
struct {
INT8 tCKminFine : 8; ///< Bits 7:0
} Bits;
INT8 Data;
} SPD4_TCK_MIN_FTB_STRUCT;
typedef union {
struct {
UINT8 Height : 5; ///< Bits 4:0
UINT8 RawCardExtension : 3; ///< Bits 7:5
} Bits;
UINT8 Data;
} SPD4_UNBUF_MODULE_NOMINAL_HEIGHT;
typedef union {
struct {
UINT8 FrontThickness : 4; ///< Bits 3:0
UINT8 BackThickness : 4; ///< Bits 7:4
} Bits;
UINT8 Data;
} SPD4_UNBUF_MODULE_NOMINAL_THICKNESS;
typedef union {
struct {
UINT8 Card : 5; ///< Bits 4:0
UINT8 Revision : 2; ///< Bits 6:5
UINT8 Extension : 1; ///< Bits 7:7
} Bits;
UINT8 Data;
} SPD4_UNBUF_REFERENCE_RAW_CARD;
typedef union {
struct {
UINT8 MappingRank1 : 1; ///< Bits 0:0
UINT8 Reserved : 7; ///< Bits 7:1
} Bits;
UINT8 Data;
} SPD4_UNBUF_ADDRESS_MAPPING;
typedef union {
struct {
UINT8 Height : 5; ///< Bits 4:0
UINT8 Reserved : 3; ///< Bits 7:5
} Bits;
UINT8 Data;
} SPD4_RDIMM_MODULE_NOMINAL_HEIGHT;
typedef union {
struct {
UINT8 FrontThickness : 4; ///< Bits 3:0
UINT8 BackThickness : 4; ///< Bits 7:4
} Bits;
UINT8 Data;
} SPD4_RDIMM_MODULE_NOMINAL_THICKNESS;
typedef union {
struct {
UINT8 Card : 5; ///< Bits 4:0
UINT8 Revision : 2; ///< Bits 6:5
UINT8 Extension : 1; ///< Bits 7:7
} Bits;
UINT8 Data;
} SPD4_RDIMM_REFERENCE_RAW_CARD;
typedef union {
struct {
UINT8 RegisterCount : 2; ///< Bits 1:0
UINT8 DramRowCount : 2; ///< Bits 3:2
UINT8 RegisterType : 4; ///< Bits 7:4
} Bits;
UINT8 Data;
} SPD4_RDIMM_MODULE_ATTRIBUTES;
typedef union {
struct {
UINT8 HeatSpreaderThermalCharacteristics : 7; ///< Bits 6:0
UINT8 HeatSpreaderSolution : 1; ///< Bits 7:7
} Bits;
UINT8 Data;
} SPD4_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION;
typedef union {
struct {
UINT16 ContinuationCount : 7; ///< Bits 6:0
UINT16 ContinuationParity : 1; ///< Bits 7:7
UINT16 LastNonZeroByte : 8; ///< Bits 15:8
} Bits;
UINT16 Data;
UINT8 Data8[2];
} SPD4_MANUFACTURER_ID_CODE;
typedef union {
struct {
UINT8 RegisterRevisionNumber; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD4_RDIMM_REGISTER_REVISION_NUMBER;
typedef union {
struct {
UINT8 Rank1Mapping : 1; ///< Bits 0:0
UINT8 Reserved : 7; ///< Bits 7:1
} Bits;
UINT8 Data;
} SPD4_RDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM;
typedef union {
struct {
UINT8 Cke : 2; ///< Bits 1:0
UINT8 Odt : 2; ///< Bits 3:2
UINT8 CommandAddress : 2; ///< Bits 5:4
UINT8 ChipSelect : 2; ///< Bits 7:6
} Bits;
UINT8 Data;
} SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS;
typedef union {
struct {
UINT8 Y0Y2 : 2; ///< Bits 1:0
UINT8 Y1Y3 : 2; ///< Bits 3:2
UINT8 Reserved0 : 2; ///< Bits 5:4
UINT8 RcdOutputSlewRateControl : 1; ///< Bits 6:6
UINT8 Reserved1 : 1; ///< Bits 7:7
} Bits;
UINT8 Data;
} SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK;
typedef union {
struct {
UINT8 Height : 5; ///< Bits 4:0
UINT8 Reserved : 3; ///< Bits 7:5
} Bits;
UINT8 Data;
} SPD4_LRDIMM_MODULE_NOMINAL_HEIGHT;
typedef union {
struct {
UINT8 FrontThickness : 4; ///< Bits 3:0
UINT8 BackThickness : 4; ///< Bits 7:4
} Bits;
UINT8 Data;
} SPD4_LRDIMM_MODULE_NOMINAL_THICKNESS;
typedef union {
struct {
UINT8 Card : 5; ///< Bits 4:0
UINT8 Revision : 2; ///< Bits 6:5
UINT8 Extension : 1; ///< Bits 7:7
} Bits;
UINT8 Data;
} SPD4_LRDIMM_REFERENCE_RAW_CARD;
typedef union {
struct {
UINT8 RegisterCount : 2; ///< Bits 1:0
UINT8 DramRowCount : 2; ///< Bits 3:2
UINT8 RegisterType : 4; ///< Bits 7:4
} Bits;
UINT8 Data;
} SPD4_LRDIMM_MODULE_ATTRIBUTES;
typedef union {
struct {
UINT8 HeatSpreaderThermalCharacteristics : 7; ///< Bits 6:0
UINT8 HeatSpreaderSolution : 1; ///< Bits 7:7
} Bits;
UINT8 Data;
} SPD4_LRDIMM_THERMAL_HEAT_SPREADER_SOLUTION;
typedef union {
struct {
UINT8 RegisterRevisionNumber; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD4_LRDIMM_REGISTER_REVISION_NUMBER;
typedef union {
struct {
UINT8 Rank1Mapping : 1; ///< Bits 0:0
UINT8 Reserved : 7; ///< Bits 7:1
} Bits;
UINT8 Data;
} SPD4_LRDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM;
typedef union {
struct {
UINT8 Cke : 2; ///< Bits 1:0
UINT8 Odt : 2; ///< Bits 3:2
UINT8 CommandAddress : 2; ///< Bits 5:4
UINT8 ChipSelect : 2; ///< Bits 7:6
} Bits;
UINT8 Data;
} SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS;
typedef union {
struct {
UINT8 Y0Y2 : 2; ///< Bits 1:0
UINT8 Y1Y3 : 2; ///< Bits 3:2
UINT8 Reserved0 : 2; ///< Bits 5:4
UINT8 RcdOutputSlewRateControl : 1; ///< Bits 6:6
UINT8 Reserved1 : 1; ///< Bits 7:7
} Bits;
UINT8 Data;
} SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK;
typedef struct {
UINT8 DataBufferRevisionNumber;
} SPD4_LRDIMM_DATA_BUFFER_REVISION_NUMBER;
typedef union {
struct {
UINT8 DramVrefDQForPackageRank0 : 6; ///< Bits 5:0
UINT8 Reserved : 2; ///< Bits 7:6
} Bits;
UINT8 Data;
} SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK;
typedef struct {
UINT8 DataBufferVrefDQforDramInterface;
} SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE;
typedef union {
struct {
UINT8 DramInterfaceMdqDriveStrength : 4; ///< Bits 3:0
UINT8 DramInterfaceMdqReadTerminationStrength : 4; ///< Bits 7:4
} Bits;
UINT8 Data;
} SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE;
typedef union {
struct {
UINT8 DataRateLe1866 : 2; ///< Bits 1:0
UINT8 DataRateLe2400 : 2; ///< Bits 3:2
UINT8 DataRateLe3200 : 2; ///< Bits 5:4
UINT8 Reserved : 2; ///< Bits 7:6
} Bits;
UINT8 Data;
} SPD4_LRDIMM_DRAM_DRIVE_STRENGTH;
typedef union {
struct {
UINT8 Rtt_Nom : 3; ///< Bits 2:0
UINT8 Rtt_WR : 3; ///< Bits 5:3
UINT8 Reserved : 2; ///< Bits 7:6
} Bits;
UINT8 Data;
} SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE;
typedef union {
struct {
UINT8 PackageRanks0_1 : 3; ///< Bits 2:0
UINT8 PackageRanks2_3 : 3; ///< Bits 5:3
UINT8 Reserved : 2; ///< Bits 7:6
} Bits;
UINT8 Data;
} SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE;
typedef union {
struct {
UINT8 Rank0 : 1; ///< Bits 0:0
UINT8 Rank1 : 1; ///< Bits 1:1
UINT8 Rank2 : 1; ///< Bits 2:2
UINT8 Rank3 : 1; ///< Bits 3:3
UINT8 DataBuffer : 1; ///< Bits 4:4
UINT8 Reserved : 3; ///< Bits 7:5
} Bits;
UINT8 Data;
} SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE_RANGE;
typedef union {
struct {
UINT8 DataBufferGainAdjustment : 1; ///< Bits 0:0
UINT8 DataBufferDfe : 1; ///< Bits 1:1
UINT8 Reserved : 6; ///< Bits 7:2
} Bits;
UINT8 Data;
} SPD4_LRDIMM_DATA_BUFFER_DQ_DECISION_FEEDBACK_EQUALIZATION;
typedef UINT16 SPD4_NVDIMM_MODULE_PRODUCT_IDENTIFIER;
typedef union {
struct {
UINT16 ContinuationCount : 7; ///< Bits 6:0
UINT16 ContinuationParity : 1; ///< Bits 7:7
UINT16 LastNonZeroByte : 8; ///< Bits 15:8
} Bits;
UINT16 Data;
UINT8 Data8[2];
} SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_MANUFACTURER_ID_CODE;
typedef UINT16 SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_IDENTIFIER;
typedef UINT8 SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_REVISION_CODE;
typedef union {
struct {
UINT8 Card : 5; ///< Bits 4:0
UINT8 Revision : 2; ///< Bits 6:5
UINT8 Extension : 1; ///< Bits 7:7
} Bits;
UINT8 Data;
} SPD4_NVDIMM_REFERENCE_RAW_CARD;
typedef union {
struct {
UINT8 Reserved : 4; ///< Bits 3:0
UINT8 Extension : 4; ///< Bits 7:4
} Bits;
UINT8 Data;
} SPD4_NVDIMM_MODULE_CHARACTERISTICS;
typedef struct {
UINT8 Reserved;
UINT8 MediaType;
} SPD4_NVDIMM_HYBRID_MODULE_MEDIA_TYPES;
typedef UINT8 SPD4_NVDIMM_MAXIMUM_NONVOLATILE_MEMORY_INITIALIZATION_TIME;
typedef union {
struct {
UINT16 FunctionInterface : 5; ///< Bits 4:0
UINT16 FunctionClass : 5; ///< Bits 9:5
UINT16 BlockOffset : 4; ///< Bits 13:10
UINT16 Reserved : 1; ///< Bits 14:14
UINT16 Implemented : 1; ///< Bits 15:15
} Bits;
UINT16 Data;
UINT8 Data8[2];
} SPD4_NVDIMM_FUNCTION_INTERFACE_DESCRIPTOR;
typedef struct {
UINT8 Year; ///< Year represented in BCD (00h = 2000)
UINT8 Week; ///< Year represented in BCD (47h = week 47)
} SPD4_MANUFACTURING_DATE;
typedef union {
UINT32 Data;
UINT16 SerialNumber16[2];
UINT8 SerialNumber8[4];
} SPD4_MANUFACTURER_SERIAL_NUMBER;
typedef struct {
UINT8 Location; ///< Module Manufacturing Location
} SPD4_MANUFACTURING_LOCATION;
typedef struct {
SPD4_MANUFACTURER_ID_CODE IdCode; ///< Module Manufacturer ID Code
SPD4_MANUFACTURING_LOCATION Location; ///< Module Manufacturing Location
SPD4_MANUFACTURING_DATE Date; ///< Module Manufacturing Year, in BCD (range: 2000-2255)
SPD4_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< Module Serial Number
} SPD4_UNIQUE_MODULE_ID;
typedef union {
UINT16 Crc[1];
UINT8 Data8[2];
} SPD4_CYCLIC_REDUNDANCY_CODE;
typedef struct {
SPD4_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2
SPD4_REVISION_STRUCT Revision; ///< 1 SPD Revision
SPD4_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type
SPD4_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type
SPD4_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks
SPD4_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing
SPD4_PRIMARY_SDRAM_PACKAGE_TYPE_STRUCT PrimarySdramPackageType; ///< 6 Primary SDRAM Package Type
SPD4_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 7 SDRAM Optional Features
SPD4_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 8 SDRAM Thermal and Refresh Options
SPD4_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT OtherOptionalFeatures; ///< 9 Other SDRAM Optional Features
SPD4_SECONDARY_SDRAM_PACKAGE_TYPE_STRUCT SecondarySdramPackageType;///< 10 Secondary SDRAM Package Type
SPD4_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 11 Module Nominal Voltage, VDD
SPD4_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 12 Module Organization
SPD4_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 13 Module Memory Bus Width
SPD4_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 14 Module Thermal Sensor
SPD4_EXTENDED_MODULE_TYPE_STRUCT ExtendedModuleType; ///< 15 Extended Module Type
UINT8 Reserved0; ///< 16 Reserved
SPD4_TIMEBASE_STRUCT Timebase; ///< 17 Timebases
SPD4_TCK_MIN_MTB_STRUCT tCKmin; ///< 18 SDRAM Minimum Cycle Time (tCKmin)
SPD4_TCK_MAX_MTB_STRUCT tCKmax; ///< 19 SDRAM Maximum Cycle Time (tCKmax)
SPD4_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 20-23 CAS Latencies Supported
SPD4_TAA_MIN_MTB_STRUCT tAAmin; ///< 24 Minimum CAS Latency Time (tAAmin)
SPD4_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 25 Minimum RAS# to CAS# Delay Time (tRCDmin)
SPD4_TRP_MIN_MTB_STRUCT tRPmin; ///< 26 Minimum Row Precharge Delay Time (tRPmin)
SPD4_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 27 Upper Nibbles for tRAS and tRC
SPD4_TRAS_MIN_MTB_STRUCT tRASmin; ///< 28 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte
SPD4_TRC_MIN_MTB_STRUCT tRCmin; ///< 29 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte
SPD4_TRFC_MIN_MTB_STRUCT tRFC1min; ///< 30-31 Minimum Refresh Recovery Delay Time (tRFC1min)
SPD4_TRFC_MIN_MTB_STRUCT tRFC2min; ///< 32-33 Minimum Refresh Recovery Delay Time (tRFC2min)
SPD4_TRFC_MIN_MTB_STRUCT tRFC4min; ///< 34-35 Minimum Refresh Recovery Delay Time (tRFC4min)
SPD4_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 36 Upper Nibble for tFAW
SPD4_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 37 Minimum Four Activate Window Delay Time (tFAWmin)
SPD4_TRRD_MIN_MTB_STRUCT tRRD_Smin; ///< 38 Minimum Activate to Activate Delay Time (tRRD_Smin), different bank group
SPD4_TRRD_MIN_MTB_STRUCT tRRD_Lmin; ///< 39 Minimum Activate to Activate Delay Time (tRRD_Lmin), same bank group
SPD4_TCCD_MIN_MTB_STRUCT tCCD_Lmin; ///< 40 Minimum CAS to CAS Delay Time (tCCD_Lmin), Same Bank Group
SPD4_TWR_UPPER_NIBBLE_STRUCT tWRUpperNibble; ///< 41 Upper Nibble for tWRmin
SPD4_TWR_MIN_MTB_STRUCT tWRmin; ///< 42 Minimum Write Recovery Time (tWRmin)
SPD4_TWTR_UPPER_NIBBLE_STRUCT tWTRUpperNibble; ///< 43 Upper Nibbles for tWTRmin
SPD4_TWTR_MIN_MTB_STRUCT tWTR_Smin; ///< 44 Minimum Write to Read Time (tWTR_Smin), Different Bank Group
SPD4_TWTR_MIN_MTB_STRUCT tWTR_Lmin; ///< 45 Minimum Write to Read Time (tWTR_Lmin), Same Bank Group
UINT8 Reserved1[59 - 46 + 1]; ///< 46-59 Reserved
SPD4_CONNECTOR_BIT_MAPPING_BYTE_STRUCT BitMapping[77 - 60 + 1]; ///< 60-77 Connector to SDRAM Bit Mapping
UINT8 Reserved2[116 - 78 + 1]; ///< 78-116 Reserved
SPD4_TCCD_MIN_FTB_STRUCT tCCD_LminFine; ///< 117 Fine Offset for Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank group
SPD4_TRRD_MIN_FTB_STRUCT tRRD_LminFine; ///< 118 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Lmin), different bank group
SPD4_TRRD_MIN_FTB_STRUCT tRRD_SminFine; ///< 119 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Smin), same bank group
SPD4_TRC_MIN_FTB_STRUCT tRCminFine; ///< 120 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)
SPD4_TRP_MIN_FTB_STRUCT tRPminFine; ///< 121 Fine Offset for Minimum Row Precharge Delay Time (tRPabmin)
SPD4_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
SPD4_TAA_MIN_FTB_STRUCT tAAminFine; ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin)
SPD4_TCK_MAX_FTB_STRUCT tCKmaxFine; ///< 124 Fine Offset for SDRAM Minimum Cycle Time (tCKmax)
SPD4_TCK_MIN_FTB_STRUCT tCKminFine; ///< 125 Fine Offset for SDRAM Maximum Cycle Time (tCKmin)
SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC)
} SPD4_BASE_SECTION;
typedef struct {
SPD4_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height
SPD4_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness
SPD4_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used
SPD4_UNBUF_ADDRESS_MAPPING AddressMappingEdgeConn; ///< 131 Address Mapping from Edge Connector to DRAM
UINT8 Reserved[253 - 132 + 1]; ///< 132-253 Reserved
SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)
} SPD4_MODULE_UNBUFFERED;
typedef struct {
SPD4_RDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height
SPD4_RDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness
SPD4_RDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used
SPD4_RDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 131 DIMM Module Attributes
SPD4_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION DimmThermalHeatSpreaderSolution; ///< 132 RDIMM Thermal Heat Spreader Solution
SPD4_MANUFACTURER_ID_CODE RegisterManufacturerIdCode; ///< 133-134 Register Manufacturer ID Code
SPD4_RDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber; ///< 135 Register Revision Number
SPD4_RDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM AddressMappingFromRegisterToDRAM; ///< 136 Address Mapping from Register to DRAM
SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS RegisterOutputDriveStrengthForControlCommandAddress; ///< 137 Register Output Drive Strength for Control and Command Address
SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK RegisterOutputDriveStrengthForClock; ///< 138 Register Output Drive Strength for Clock
UINT8 Reserved[253 - 139 + 1]; ///< 253-139 Reserved
SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)
} SPD4_MODULE_REGISTERED;
typedef struct {
SPD4_LRDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height
SPD4_LRDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness
SPD4_LRDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used
SPD4_LRDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 131 DIMM Module Attributes
SPD4_LRDIMM_THERMAL_HEAT_SPREADER_SOLUTION ThermalHeatSpreaderSolution; ///< 132 RDIMM Thermal Heat Spreader Solution
SPD4_MANUFACTURER_ID_CODE RegisterManufacturerIdCode; ///< 133-134 Register Manufacturer ID Code
SPD4_LRDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber; ///< 135 Register Revision Number
SPD4_LRDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM AddressMappingFromRegisterToDram; ///< 136 Address Mapping from Register to DRAM
SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS RegisterOutputDriveStrengthForControlCommandAddress; ///< 137 Register Output Drive Strength for Control and Command Address
SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK RegisterOutputDriveStrengthForClock; ///< 138 Register Output Drive Strength for Clock
SPD4_LRDIMM_DATA_BUFFER_REVISION_NUMBER DataBufferRevisionNumber; ///< 139 Data Buffer Revision Number
SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank0; ///< 140 DRAM VrefDQ for Package Rank 0
SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank1; ///< 141 DRAM VrefDQ for Package Rank 1
SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank2; ///< 142 DRAM VrefDQ for Package Rank 2
SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank3; ///< 143 DRAM VrefDQ for Package Rank 3
SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE DataBufferVrefDQForDramInterface; ///< 144 Data Buffer VrefDQ for DRAM Interface
SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMdqDriveStrengthRttForDataRateLe1866; ///< 145 Data Buffer MDQ Drive Strength and RTT for data rate <= 1866
SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMdqDriveStrengthRttForDataRateLe2400; ///< 146 Data Buffer MDQ Drive Strength and RTT for data rate <=2400
SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMdqDriveStrengthRttForDataRateLe3200; ///< 147 Data Buffer MDQ Drive Strength and RTT for data rate <=3200
SPD4_LRDIMM_DRAM_DRIVE_STRENGTH DramDriveStrength; ///< 148 DRAM Drive Strength
SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DramOdtRttWrRttNomForDataRateLe1866; ///< 149 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 1866
SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DramOdtRttWrRttNomForDataRateLe2400; ///< 150 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 2400
SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DramOdtRttWrRttNomForDataRateLe3200; ///< 151 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 3200
SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DramOdtRttParkForDataRateLe1866; ///< 152 DRAM ODT (RTT_PARK) for data rate <= 1866
SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DramOdtRttParkForDataRateLe2400; ///< 153 DRAM ODT (RTT_PARK) for data rate <= 2400
SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DramOdtRttParkForDataRateLe3200; ///< 154 DRAM ODT (RTT_PARK) for data rate <= 3200
SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE_RANGE DataBufferVrefDQForDramInterfaceRange; ///< 155 Data Buffer VrefDQ for DRAM Interface Range
SPD4_LRDIMM_DATA_BUFFER_DQ_DECISION_FEEDBACK_EQUALIZATION DataBufferDqDecisionFeedbackEqualization; ///< 156 Data Buffer DQ Decision Feedback Equalization
UINT8 Reserved[253 - 157 + 1]; ///< 253-132 Reserved
SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)
} SPD4_MODULE_LOADREDUCED;
typedef struct {
UINT8 Reserved0[191 - 128 + 1]; ///< 128-191 Reserved
SPD4_NVDIMM_MODULE_PRODUCT_IDENTIFIER ModuleProductIdentifier; ///< 192-193 Module Product Identifier
SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_MANUFACTURER_ID_CODE SubsystemControllerManufacturerIdCode; ///< 194-195 Subsystem Controller Manufacturer's ID Code
SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_IDENTIFIER SubsystemControllerIdentifier; ///< 196-197 Subsystem Controller Identifier
SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_REVISION_CODE SubsystemControllerRevisionCode; ///< 198 Subsystem Controller Revision Code
SPD4_NVDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 199 Reference Raw Card Used
SPD4_NVDIMM_MODULE_CHARACTERISTICS ModuleCharacteristics; ///< 200 Module Characteristics
SPD4_NVDIMM_HYBRID_MODULE_MEDIA_TYPES HybridModuleMediaTypes; ///< 201-202 Hybrid Module Media Types
SPD4_NVDIMM_MAXIMUM_NONVOLATILE_MEMORY_INITIALIZATION_TIME MaximumNonVolatileMemoryInitializationTime; ///< 203 Maximum Non-Volatile Memory Initialization Time
SPD4_NVDIMM_FUNCTION_INTERFACE_DESCRIPTOR FunctionInterfaceDescriptors[8]; ///< 204-219 Function Interface Descriptors
UINT8 Reserved[253 - 220 + 1]; ///< 220-253 Reserved
SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)
} SPD4_MODULE_NVDIMM;
typedef union {
SPD4_MODULE_UNBUFFERED Unbuffered; ///< 128-255 Unbuffered Memory Module Types
SPD4_MODULE_REGISTERED Registered; ///< 128-255 Registered Memory Module Types
SPD4_MODULE_LOADREDUCED LoadReduced; ///< 128-255 Load Reduced Memory Module Types
SPD4_MODULE_NVDIMM NonVolatile; ///< 128-255 Non-Volatile (NVDIMM-N) Hybrid Memory Parameters
} SPD4_MODULE_SPECIFIC;
typedef struct {
UINT8 ModulePartNumber[348 - 329 + 1]; ///< 329-348 Module Part Number
} SPD4_MODULE_PART_NUMBER;
typedef struct {
UINT8 ManufacturerSpecificData[381 - 353 + 1]; ///< 353-381 Manufacturer's Specific Data
} SPD4_MANUFACTURER_SPECIFIC;
typedef UINT8 SPD4_MODULE_REVISION_CODE;///< 349 Module Revision Code
typedef UINT8 SPD4_DRAM_STEPPING; ///< 352 Dram Stepping
typedef struct {
SPD4_UNIQUE_MODULE_ID ModuleId; ///< 320-328 Unique Module ID
SPD4_MODULE_PART_NUMBER ModulePartNumber; ///< 329-348 Module Part Number
SPD4_MODULE_REVISION_CODE ModuleRevisionCode; ///< 349 Module Revision Code
SPD4_MANUFACTURER_ID_CODE DramIdCode; ///< 350-351 Dram Manufacturer ID Code
SPD4_DRAM_STEPPING DramStepping; ///< 352 Dram Stepping
SPD4_MANUFACTURER_SPECIFIC ManufacturerSpecificData; ///< 353-381 Manufacturer's Specific Data
UINT8 Reserved[2]; ///< 382-383 Reserved
} SPD4_MANUFACTURING_DATA;
typedef struct {
UINT8 Reserved[511 - 384 + 1]; ///< 384-511 Unbuffered Memory Module Types
} SPD4_END_USER_SECTION;
///
/// DDR4 Serial Presence Detect structure
///
typedef struct {
SPD4_BASE_SECTION Base; ///< 0-127 Base Configuration and DRAM Parameters
SPD4_MODULE_SPECIFIC Module; ///< 128-255 Module-Specific Section
UINT8 Reserved[319 - 256 + 1]; ///< 256-319 Reserved
SPD4_MANUFACTURING_DATA ManufactureInfo; ///< 320-383 Manufacturing Information
SPD4_END_USER_SECTION EndUser; ///< 384-511 End User Programmable
} SPD_DDR4;
#pragma pack (pop)
#endif

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/** @file
This file contains definitions for SPD LPDDR.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
- Serial Presence Detect (SPD) for LPDDR3 and LPDDR4 SDRAM Modules Document Release 2
http://www.jedec.org/standards-documents/docs/spd412m-2
**/
#ifndef _SDRAM_SPD_LPDDR_H_
#define _SDRAM_SPD_LPDDR_H_
#pragma pack (push, 1)
typedef union {
struct {
UINT8 BytesUsed : 4; ///< Bits 3:0
UINT8 BytesTotal : 3; ///< Bits 6:4
UINT8 CrcCoverage : 1; ///< Bits 7:7
} Bits;
UINT8 Data;
} SPD_LPDDR_DEVICE_DESCRIPTION_STRUCT;
typedef union {
struct {
UINT8 Minor : 4; ///< Bits 3:0
UINT8 Major : 4; ///< Bits 7:4
} Bits;
UINT8 Data;
} SPD_LPDDR_REVISION_STRUCT;
typedef union {
struct {
UINT8 Type : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD_LPDDR_DRAM_DEVICE_TYPE_STRUCT;
typedef union {
struct {
UINT8 ModuleType : 4; ///< Bits 3:0
UINT8 HybridMedia : 3; ///< Bits 6:4
UINT8 Hybrid : 1; ///< Bits 7:7
} Bits;
UINT8 Data;
} SPD_LPDDR_MODULE_TYPE_STRUCT;
typedef union {
struct {
UINT8 Density : 4; ///< Bits 3:0
UINT8 BankAddress : 2; ///< Bits 5:4
UINT8 BankGroup : 2; ///< Bits 7:6
} Bits;
UINT8 Data;
} SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT;
typedef union {
struct {
UINT8 ColumnAddress : 3; ///< Bits 2:0
UINT8 RowAddress : 3; ///< Bits 5:3
UINT8 Reserved : 2; ///< Bits 7:6
} Bits;
UINT8 Data;
} SPD_LPDDR_SDRAM_ADDRESSING_STRUCT;
typedef union {
struct {
UINT8 SignalLoading : 2; ///< Bits 1:0
UINT8 ChannelsPerDie : 2; ///< Bits 3:2
UINT8 DieCount : 3; ///< Bits 6:4
UINT8 SdramPackageType : 1; ///< Bits 7:7
} Bits;
UINT8 Data;
} SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT;
typedef union {
struct {
UINT8 MaximumActivateCount : 4; ///< Bits 3:0
UINT8 MaximumActivateWindow : 2; ///< Bits 5:4
UINT8 Reserved : 2; ///< Bits 7:6
} Bits;
UINT8 Data;
} SPD_LPDDR_SDRAM_OPTIONAL_FEATURES_STRUCT;
typedef union {
struct {
UINT8 Reserved : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT;
typedef union {
struct {
UINT8 Reserved : 5; ///< Bits 4:0
UINT8 SoftPPR : 1; ///< Bits 5:5
UINT8 PostPackageRepair : 2; ///< Bits 7:6
} Bits;
UINT8 Data;
} SPD_LPDDR_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT;
typedef union {
struct {
UINT8 OperationAt1_20 : 1; ///< Bits 0:0
UINT8 EndurantAt1_20 : 1; ///< Bits 1:1
UINT8 OperationAt1_10 : 1; ///< Bits 2:2
UINT8 EndurantAt1_10 : 1; ///< Bits 3:3
UINT8 OperationAtTBD2V : 1; ///< Bits 4:4
UINT8 EndurantAtTBD2V : 1; ///< Bits 5:5
UINT8 Reserved : 2; ///< Bits 7:6
} Bits;
UINT8 Data;
} SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT;
typedef union {
struct {
UINT8 SdramDeviceWidth : 3; ///< Bits 2:0
UINT8 RankCount : 3; ///< Bits 5:3
UINT8 Reserved : 2; ///< Bits 7:6
} Bits;
UINT8 Data;
} SPD_LPDDR_MODULE_ORGANIZATION_STRUCT;
typedef union {
struct {
UINT8 PrimaryBusWidth : 3; ///< Bits 2:0
UINT8 BusWidthExtension : 2; ///< Bits 4:3
UINT8 NumberofChannels : 3; ///< Bits 7:5
} Bits;
UINT8 Data;
} SPD_LPDDR_MODULE_MEMORY_BUS_WIDTH_STRUCT;
typedef union {
struct {
UINT8 Reserved : 7; ///< Bits 6:0
UINT8 ThermalSensorPresence : 1; ///< Bits 7:7
} Bits;
UINT8 Data;
} SPD_LPDDR_MODULE_THERMAL_SENSOR_STRUCT;
typedef union {
struct {
UINT8 ExtendedBaseModuleType : 4; ///< Bits 3:0
UINT8 Reserved : 4; ///< Bits 7:4
} Bits;
UINT8 Data;
} SPD_LPDDR_EXTENDED_MODULE_TYPE_STRUCT;
typedef union {
struct {
UINT8 ChipSelectLoading : 3; ///< Bits 2:0
UINT8 CommandAddressControlClockLoading : 3; ///< Bits 5:3
UINT8 DataStrobeMaskLoading : 2; ///< Bits 7:6
} Bits;
UINT8 Data;
} SPD_LPDDR_SIGNAL_LOADING_STRUCT;
typedef union {
struct {
UINT8 Fine : 2; ///< Bits 1:0
UINT8 Medium : 2; ///< Bits 3:2
UINT8 Reserved : 4; ///< Bits 7:4
} Bits;
UINT8 Data;
} SPD_LPDDR_TIMEBASE_STRUCT;
typedef union {
struct {
UINT8 tCKmin : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD_LPDDR_TCK_MIN_MTB_STRUCT;
typedef union {
struct {
UINT8 tCKmax : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD_LPDDR_TCK_MAX_MTB_STRUCT;
typedef union {
struct {
UINT32 Cl3 : 1; ///< Bits 0:0
UINT32 Cl6 : 1; ///< Bits 1:1
UINT32 Cl8 : 1; ///< Bits 2:2
UINT32 Cl9 : 1; ///< Bits 3:3
UINT32 Cl10 : 1; ///< Bits 4:4
UINT32 Cl11 : 1; ///< Bits 5:5
UINT32 Cl12 : 1; ///< Bits 6:6
UINT32 Cl14 : 1; ///< Bits 7:7
UINT32 Cl16 : 1; ///< Bits 8:8
UINT32 Reserved0 : 1; ///< Bits 9:9
UINT32 Cl20 : 1; ///< Bits 10:10
UINT32 Cl22 : 1; ///< Bits 11:11
UINT32 Cl24 : 1; ///< Bits 12:12
UINT32 Reserved1 : 1; ///< Bits 13:13
UINT32 Cl28 : 1; ///< Bits 14:14
UINT32 Reserved2 : 1; ///< Bits 15:15
UINT32 Cl32 : 1; ///< Bits 16:16
UINT32 Reserved3 : 1; ///< Bits 17:17
UINT32 Cl36 : 1; ///< Bits 18:18
UINT32 Reserved4 : 1; ///< Bits 19:19
UINT32 Cl40 : 1; ///< Bits 20:20
UINT32 Reserved5 : 11; ///< Bits 31:21
} Bits;
UINT32 Data;
UINT16 Data16[2];
UINT8 Data8[4];
} SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT;
typedef union {
struct {
UINT8 tAAmin : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD_LPDDR_TAA_MIN_MTB_STRUCT;
typedef union {
struct {
UINT8 ReadLatencyMode : 2; ///< Bits 1:0
UINT8 WriteLatencySet : 2; ///< Bits 3:2
UINT8 Reserved : 4; ///< Bits 7:4
} Bits;
UINT8 Data;
} SPD_LPDDR_RW_LATENCY_OPTION_STRUCT;
typedef union {
struct {
UINT8 tRCDmin : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD_LPDDR_TRCD_MIN_MTB_STRUCT;
typedef union {
struct {
UINT8 tRPab : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD_LPDDR_TRP_AB_MTB_STRUCT;
typedef union {
struct {
UINT8 tRPpb : 8; ///< Bits 7:0
} Bits;
UINT8 Data;
} SPD_LPDDR_TRP_PB_MTB_STRUCT;
typedef union {
struct {
UINT16 tRFCab : 16; ///< Bits 15:0
} Bits;
UINT16 Data;
UINT8 Data8[2];
} SPD_LPDDR_TRFC_AB_MTB_STRUCT;
typedef union {
struct {
UINT16 tRFCpb : 16; ///< Bits 15:0
} Bits;
UINT16 Data;
UINT8 Data8[2];
} SPD_LPDDR_TRFC_PB_MTB_STRUCT;
typedef union {
struct {
UINT8 BitOrderatSDRAM : 5; ///< Bits 4:0
UINT8 WiredtoUpperLowerNibble : 1; ///< Bits 5:5
UINT8 PackageRankMap : 2; ///< Bits 7:6
} Bits;
UINT8 Data;
} SPD_LPDDR_CONNECTOR_BIT_MAPPING_BYTE_STRUCT;
typedef union {
struct {
INT8 tRPpbFine : 8; ///< Bits 7:0
} Bits;
INT8 Data;
} SPD_LPDDR_TRP_PB_FTB_STRUCT;
typedef union {
struct {
INT8 tRPabFine : 8; ///< Bits 7:0
} Bits;
INT8 Data;
} SPD_LPDDR_TRP_AB_FTB_STRUCT;
typedef union {
struct {
INT8 tRCDminFine : 8; ///< Bits 7:0
} Bits;
INT8 Data;
} SPD_LPDDR_TRCD_MIN_FTB_STRUCT;
typedef union {
struct {
INT8 tAAminFine : 8; ///< Bits 7:0
} Bits;
INT8 Data;
} SPD_LPDDR_TAA_MIN_FTB_STRUCT;
typedef union {
struct {
INT8 tCKmaxFine : 8; ///< Bits 7:0
} Bits;
INT8 Data;
} SPD_LPDDR_TCK_MAX_FTB_STRUCT;
typedef union {
struct {
INT8 tCKminFine : 8; ///< Bits 7:0
} Bits;
INT8 Data;
} SPD_LPDDR_TCK_MIN_FTB_STRUCT;
typedef union {
struct {
UINT16 ContinuationCount : 7; ///< Bits 6:0
UINT16 ContinuationParity : 1; ///< Bits 7:7
UINT16 LastNonZeroByte : 8; ///< Bits 15:8
} Bits;
UINT16 Data;
UINT8 Data8[2];
} SPD_LPDDR_MANUFACTURER_ID_CODE;
typedef struct {
UINT8 Location; ///< Module Manufacturing Location
} SPD_LPDDR_MANUFACTURING_LOCATION;
typedef struct {
UINT8 Year; ///< Year represented in BCD (00h = 2000)
UINT8 Week; ///< Year represented in BCD (47h = week 47)
} SPD_LPDDR_MANUFACTURING_DATE;
typedef union {
UINT32 Data;
UINT16 SerialNumber16[2];
UINT8 SerialNumber8[4];
} SPD_LPDDR_MANUFACTURER_SERIAL_NUMBER;
typedef struct {
SPD_LPDDR_MANUFACTURER_ID_CODE IdCode; ///< Module Manufacturer ID Code
SPD_LPDDR_MANUFACTURING_LOCATION Location; ///< Module Manufacturing Location
SPD_LPDDR_MANUFACTURING_DATE Date; ///< Module Manufacturing Year, in BCD (range: 2000-2255)
SPD_LPDDR_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< Module Serial Number
} SPD_LPDDR_UNIQUE_MODULE_ID;
typedef union {
struct {
UINT8 FrontThickness : 4; ///< Bits 3:0
UINT8 BackThickness : 4; ///< Bits 7:4
} Bits;
UINT8 Data;
} SPD_LPDDR_MODULE_MAXIMUM_THICKNESS;
typedef union {
struct {
UINT8 Height : 5; ///< Bits 4:0
UINT8 RawCardExtension : 3; ///< Bits 7:5
} Bits;
UINT8 Data;
} SPD_LPDDR_MODULE_NOMINAL_HEIGHT;
typedef union {
struct {
UINT8 Card : 5; ///< Bits 4:0
UINT8 Revision : 2; ///< Bits 6:5
UINT8 Extension : 1; ///< Bits 7:7
} Bits;
UINT8 Data;
} SPD_LPDDR_REFERENCE_RAW_CARD;
typedef union {
UINT16 Crc[1];
UINT8 Data8[2];
} SPD_LPDDR_CYCLIC_REDUNDANCY_CODE;
typedef struct {
SPD_LPDDR_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2
SPD_LPDDR_REVISION_STRUCT Revision; ///< 1 SPD Revision
SPD_LPDDR_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type
SPD_LPDDR_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type
SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks
SPD_LPDDR_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing
SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT SdramPackageType; ///< 6 SDRAM Package Type
SPD_LPDDR_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 7 SDRAM Optional Features
SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 8 SDRAM Thermal and Refresh Options
SPD_LPDDR_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT OtherOptionalFeatures; ///< 9 Other SDRAM Optional Features
UINT8 Reserved0; ///< 10 Reserved
SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 11 Module Nominal Voltage, VDD
SPD_LPDDR_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 12 Module Organization
SPD_LPDDR_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 13 Module Memory Bus Width
SPD_LPDDR_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 14 Module Thermal Sensor
SPD_LPDDR_EXTENDED_MODULE_TYPE_STRUCT ExtendedModuleType; ///< 15 Extended Module Type
SPD_LPDDR_SIGNAL_LOADING_STRUCT SignalLoading; ///< 16 Signal Loading
SPD_LPDDR_TIMEBASE_STRUCT Timebase; ///< 17 Timebases
SPD_LPDDR_TCK_MIN_MTB_STRUCT tCKmin; ///< 18 SDRAM Minimum Cycle Time (tCKmin)
SPD_LPDDR_TCK_MAX_MTB_STRUCT tCKmax; ///< 19 SDRAM Maximum Cycle Time (tCKmax)
SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 20-23 CAS Latencies Supported
SPD_LPDDR_TAA_MIN_MTB_STRUCT tAAmin; ///< 24 Minimum CAS Latency Time (tAAmin)
SPD_LPDDR_RW_LATENCY_OPTION_STRUCT LatencySetOptions; ///< 25 Read and Write Latency Set Options
SPD_LPDDR_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 26 Minimum RAS# to CAS# Delay Time (tRCDmin)
SPD_LPDDR_TRP_AB_MTB_STRUCT tRPab; ///< 27 Minimum Row Precharge Delay Time (tRPab), all banks
SPD_LPDDR_TRP_PB_MTB_STRUCT tRPpb; ///< 28 Minimum Row Precharge Delay Time (tRPpb), per bank
SPD_LPDDR_TRFC_AB_MTB_STRUCT tRFCab; ///< 29-30 Minimum Refresh Recovery Delay Time (tRFCab), all banks
SPD_LPDDR_TRFC_PB_MTB_STRUCT tRFCpb; ///< 31-32 Minimum Refresh Recovery Delay Time (tRFCpb), per bank
UINT8 Reserved1[59 - 33 + 1]; ///< 33-59 Reserved
SPD_LPDDR_CONNECTOR_BIT_MAPPING_BYTE_STRUCT BitMapping[77 - 60 + 1]; ///< 60-77 Connector to SDRAM Bit Mapping
UINT8 Reserved2[119 - 78 + 1]; ///< 78-119 Reserved
SPD_LPDDR_TRP_PB_FTB_STRUCT tRPpbFine; ///< 120 Fine Offset for Minimum Row Precharge Delay Time (tRPpbFine), per bank
SPD_LPDDR_TRP_AB_FTB_STRUCT tRPabFine; ///< 121 Fine Offset for Minimum Row Precharge Delay Time (tRPabFine), all ranks
SPD_LPDDR_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
SPD_LPDDR_TAA_MIN_FTB_STRUCT tAAminFine; ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin)
SPD_LPDDR_TCK_MAX_FTB_STRUCT tCKmaxFine; ///< 124 Fine Offset for SDRAM Maximum Cycle Time (tCKmax)
SPD_LPDDR_TCK_MIN_FTB_STRUCT tCKminFine; ///< 125 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
SPD_LPDDR_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC)
} SPD_LPDDR_BASE_SECTION;
typedef struct {
SPD_LPDDR_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height
SPD_LPDDR_MODULE_MAXIMUM_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness
SPD_LPDDR_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used
UINT8 Reserved[253 - 131 + 1]; ///< 131-253 Reserved
SPD_LPDDR_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)
} SPD_LPDDR_MODULE_LPDIMM;
typedef struct {
SPD_LPDDR_MODULE_LPDIMM LpDimm; ///< 128-255 Unbuffered Memory Module Types
} SPD_LPDDR_MODULE_SPECIFIC;
typedef struct {
UINT8 ModulePartNumber[348 - 329 + 1]; ///< 329-348 Module Part Number
} SPD_LPDDR_MODULE_PART_NUMBER;
typedef struct {
UINT8 ManufacturerSpecificData[381 - 353 + 1]; ///< 353-381 Manufacturer's Specific Data
} SPD_LPDDR_MANUFACTURER_SPECIFIC;
typedef UINT8 SPD_LPDDR_MODULE_REVISION_CODE;///< 349 Module Revision Code
typedef UINT8 SPD_LPDDR_DRAM_STEPPING; ///< 352 Dram Stepping
typedef struct {
SPD_LPDDR_UNIQUE_MODULE_ID ModuleId; ///< 320-328 Unique Module ID
SPD_LPDDR_MODULE_PART_NUMBER ModulePartNumber; ///< 329-348 Module Part Number
SPD_LPDDR_MODULE_REVISION_CODE ModuleRevisionCode; ///< 349 Module Revision Code
SPD_LPDDR_MANUFACTURER_ID_CODE DramIdCode; ///< 350-351 Dram Manufacturer ID Code
SPD_LPDDR_DRAM_STEPPING DramStepping; ///< 352 Dram Stepping
SPD_LPDDR_MANUFACTURER_SPECIFIC ManufacturerSpecificData; ///< 353-381 Manufacturer's Specific Data
UINT8 Reserved[383 - 382 + 1]; ///< 382-383 Reserved
} SPD_LPDDR_MANUFACTURING_DATA;
typedef struct {
UINT8 Reserved[511 - 384 + 1]; ///< 384-511 End User Programmable
} SPD_LPDDR_END_USER_SECTION;
///
/// LPDDR Serial Presence Detect structure
///
typedef struct {
SPD_LPDDR_BASE_SECTION Base; ///< 0-127 Base Configuration and DRAM Parameters
SPD_LPDDR_MODULE_SPECIFIC Module; ///< 128-255 Module-Specific Section
UINT8 Reserved[319 - 256 + 1]; ///< 256-319 Hybrid Memory Parameters
SPD_LPDDR_MANUFACTURING_DATA ManufactureInfo; ///< 320-383 Manufacturing Information
SPD_LPDDR_END_USER_SECTION EndUser; ///< 384-511 End User Programmable
} SPD_LPDDR;
#pragma pack (pop)
#endif

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