Rename "saf1761_dci_xxx" into "saf1761_otg_xxx" to reflect that this
driver supports both host and device side mode. Sponsored by: DARPA, AFRL
This commit is contained in:
hselasky
parent
d8fcccb1e7
commit
529b37774d
2703
sys/dev/usb/controller/saf1761_otg.c
Normal file
2703
sys/dev/usb/controller/saf1761_otg.c
Normal file
File diff suppressed because it is too large
Load Diff
157
sys/dev/usb/controller/saf1761_otg.h
Normal file
157
sys/dev/usb/controller/saf1761_otg.h
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@ -0,0 +1,157 @@
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/* $FreeBSD$ */
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/*-
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* Copyright (c) 2014 Hans Petter Selasky <hselasky@FreeBSD.org>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _SAF1761_OTG_H_
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#define _SAF1761_OTG_H_
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#define SOTG_MAX_DEVICES (USB_MIN_DEVICES + 1)
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#define SOTG_FS_MAX_PACKET_SIZE 64
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#define SOTG_HS_MAX_PACKET_SIZE 512
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#define SOTG_NUM_PORTS 2 /* one Device and one Host port */
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#define SOTG_HOST_PORT_NUM 1
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#define SOTG_DEVICE_PORT_NUM 2
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#define SOTG_HOST_CHANNEL_MAX (3 * 32)
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#define SAF1761_READ_1(sc, reg) \
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bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)
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#define SAF1761_READ_2(sc, reg) \
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bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)
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#define SAF1761_READ_4(sc, reg) \
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bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)
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#define SAF1761_WRITE_1(sc, reg, data) \
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bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)
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#define SAF1761_WRITE_2(sc, reg, data) \
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bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)
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#define SAF1761_WRITE_4(sc, reg, data) \
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bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)
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struct saf1761_otg_softc;
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struct saf1761_otg_td;
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typedef uint8_t (saf1761_otg_cmd_t)(struct saf1761_otg_softc *, struct saf1761_otg_td *td);
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struct saf1761_otg_td {
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struct saf1761_otg_td *obj_next;
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saf1761_otg_cmd_t *func;
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struct usb_page_cache *pc;
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uint32_t offset;
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uint32_t remainder;
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uint32_t dw1_value;
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uint16_t max_packet_size;
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uint8_t ep_index;
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uint8_t ep_type;
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uint8_t channel;
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uint8_t error_any:1;
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uint8_t error_stall:1;
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uint8_t alt_next:1;
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uint8_t short_pkt:1;
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uint8_t did_stall:1;
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uint8_t toggle:1;
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uint8_t set_toggle:1;
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};
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struct saf1761_otg_std_temp {
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saf1761_otg_cmd_t *func;
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struct usb_page_cache *pc;
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struct saf1761_otg_td *td;
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struct saf1761_otg_td *td_next;
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uint32_t len;
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uint32_t offset;
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uint16_t max_frame_size;
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uint8_t short_pkt;
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/*
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* short_pkt = 0: transfer should be short terminated
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* short_pkt = 1: transfer should not be short terminated
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*/
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uint8_t setup_alt_next;
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uint8_t did_stall;
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};
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struct saf1761_otg_config_desc {
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struct usb_config_descriptor confd;
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struct usb_interface_descriptor ifcd;
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struct usb_endpoint_descriptor endpd;
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} __packed;
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union saf1761_otg_hub_temp {
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uWord wValue;
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struct usb_port_status ps;
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};
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struct saf1761_otg_flags {
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uint8_t change_connect:1;
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uint8_t change_suspend:1;
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uint8_t status_suspend:1; /* set if suspended */
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uint8_t status_vbus:1; /* set if present */
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uint8_t status_bus_reset:1; /* set if reset complete */
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uint8_t clocks_off:1;
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uint8_t port_powered:1;
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uint8_t port_enabled:1;
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uint8_t d_pulled_up:1;
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};
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struct saf1761_otg_softc {
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struct usb_bus sc_bus;
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union saf1761_otg_hub_temp sc_hub_temp;
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struct usb_device *sc_devices[SOTG_MAX_DEVICES];
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struct resource *sc_io_res;
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struct resource *sc_irq_res;
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void *sc_intr_hdl;
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bus_size_t sc_io_size;
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bus_space_tag_t sc_io_tag;
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bus_space_handle_t sc_io_hdl;
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uint32_t sc_host_async_map;
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uint32_t sc_host_intr_map;
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uint32_t sc_host_isoc_map;
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uint32_t sc_intr_enable; /* enabled interrupts */
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uint32_t sc_hw_mode; /* hardware mode */
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uint8_t sc_bounce_buffer[1024] __aligned(4);
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uint8_t sc_rt_addr; /* root HUB address */
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uint8_t sc_dv_addr; /* device address */
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uint8_t sc_conf; /* root HUB config */
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uint8_t sc_isreset; /* host mode */
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uint8_t sc_hub_idata[1];
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struct saf1761_otg_flags sc_flags;
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};
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/* prototypes */
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usb_error_t saf1761_otg_init(struct saf1761_otg_softc *sc);
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void saf1761_otg_uninit(struct saf1761_otg_softc *sc);
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void saf1761_otg_interrupt(struct saf1761_otg_softc *sc);
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#endif /* _SAF1761_OTG_H_ */
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253
sys/dev/usb/controller/saf1761_otg_fdt.c
Normal file
253
sys/dev/usb/controller/saf1761_otg_fdt.c
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@ -0,0 +1,253 @@
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/* $FreeBSD$ */
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/*-
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* Copyright (c) 2014 Hans Petter Selasky <hselasky@FreeBSD.org>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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||||
* are met:
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||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifdef USB_GLOBAL_INCLUDE_FILE
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#include USB_GLOBAL_INCLUDE_FILE
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#else
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#include <sys/stdint.h>
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#include <sys/stddef.h>
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#include <sys/param.h>
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#include <sys/queue.h>
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#include <sys/types.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/bus.h>
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#include <sys/module.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/condvar.h>
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#include <sys/sysctl.h>
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#include <sys/sx.h>
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#include <sys/unistd.h>
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#include <sys/callout.h>
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#include <sys/malloc.h>
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#include <sys/priv.h>
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#include <sys/rman.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/usb/usb.h>
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#include <dev/usb/usbdi.h>
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#include <dev/usb/usb_core.h>
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#include <dev/usb/usb_busdma.h>
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#include <dev/usb/usb_process.h>
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#include <dev/usb/usb_transfer.h>
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#include <dev/usb/usb_device.h>
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#include <dev/usb/usb_hub.h>
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#include <dev/usb/usb_util.h>
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#include <dev/usb/usb_controller.h>
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#include <dev/usb/usb_bus.h>
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#endif /* USB_GLOBAL_INCLUDE_FILE */
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#include <dev/usb/controller/saf1761_otg.h>
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#include <dev/usb/controller/saf1761_otg_reg.h>
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static device_probe_t saf1761_otg_fdt_probe;
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static device_attach_t saf1761_otg_fdt_attach;
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static device_detach_t saf1761_otg_fdt_detach;
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static device_method_t saf1761_otg_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, saf1761_otg_fdt_probe),
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DEVMETHOD(device_attach, saf1761_otg_fdt_attach),
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DEVMETHOD(device_detach, saf1761_otg_fdt_detach),
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DEVMETHOD(device_suspend, bus_generic_suspend),
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DEVMETHOD(device_resume, bus_generic_resume),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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DEVMETHOD_END
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};
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static driver_t saf1761_otg_driver = {
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.name = "saf1761",
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.methods = saf1761_otg_methods,
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.size = sizeof(struct saf1761_otg_softc),
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};
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static devclass_t saf1761_otg_devclass;
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DRIVER_MODULE(saf1761, simplebus, saf1761_otg_driver, saf1761_otg_devclass, 0, 0);
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MODULE_DEPEND(saf1761, usb, 1, 1, 1);
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static int
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saf1761_otg_fdt_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "nxp,usb-isp1761"))
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return (ENXIO);
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device_set_desc(dev, "ISP1761/SAF1761 DCI USB 2.0 Device Controller");
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return (0);
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}
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static int
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saf1761_otg_fdt_attach(device_t dev)
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{
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struct saf1761_otg_softc *sc = device_get_softc(dev);
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char param[24];
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int err;
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int rid;
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/* get configuration from FDT */
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/* get bus-width, if any */
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if (OF_getprop(ofw_bus_get_node(dev), "bus-width",
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¶m, sizeof(param)) > 0) {
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param[sizeof(param) - 1] = 0;
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if (strcmp(param, "32") == 0)
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sc->sc_hw_mode |= SOTG_HW_MODE_CTRL_DATA_BUS_WIDTH;
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} else {
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/* assume 32-bit data bus */
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sc->sc_hw_mode |= SOTG_HW_MODE_CTRL_DATA_BUS_WIDTH;
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}
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/* get analog over-current setting */
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if (OF_getprop(ofw_bus_get_node(dev), "analog-oc",
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¶m, sizeof(param)) > 0) {
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sc->sc_hw_mode |= SOTG_HW_MODE_CTRL_ANA_DIGI_OC;
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}
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/* get DACK polarity */
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if (OF_getprop(ofw_bus_get_node(dev), "dack-polarity",
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¶m, sizeof(param)) > 0) {
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sc->sc_hw_mode |= SOTG_HW_MODE_CTRL_DACK_POL;
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}
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/* get DREQ polarity */
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if (OF_getprop(ofw_bus_get_node(dev), "dreq-polarity",
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¶m, sizeof(param)) > 0) {
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sc->sc_hw_mode |= SOTG_HW_MODE_CTRL_DREQ_POL;
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}
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/* initialise some bus fields */
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sc->sc_bus.parent = dev;
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sc->sc_bus.devices = sc->sc_devices;
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sc->sc_bus.devices_max = SOTG_MAX_DEVICES;
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/* get all DMA memory */
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if (usb_bus_mem_alloc_all(&sc->sc_bus,
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USB_GET_DMA_TAG(dev), NULL)) {
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return (ENOMEM);
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}
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rid = 0;
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sc->sc_io_res =
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bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, RF_ACTIVE);
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if (!sc->sc_io_res) {
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goto error;
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}
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sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
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sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
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sc->sc_io_size = rman_get_size(sc->sc_io_res);
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rid = 0;
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sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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RF_SHAREABLE | RF_ACTIVE);
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if (sc->sc_irq_res == NULL) {
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goto error;
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}
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sc->sc_bus.bdev = device_add_child(dev, "usbus", -1);
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if (!(sc->sc_bus.bdev)) {
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goto error;
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}
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device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
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err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
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NULL, (driver_intr_t *)saf1761_otg_interrupt, sc, &sc->sc_intr_hdl);
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if (err) {
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sc->sc_intr_hdl = NULL;
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goto error;
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}
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err = saf1761_otg_init(sc);
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if (err) {
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device_printf(dev, "Init failed\n");
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goto error;
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}
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err = device_probe_and_attach(sc->sc_bus.bdev);
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if (err) {
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device_printf(dev, "USB probe and attach failed\n");
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goto error;
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}
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return (0);
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error:
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saf1761_otg_fdt_detach(dev);
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return (ENXIO);
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}
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static int
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saf1761_otg_fdt_detach(device_t dev)
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{
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struct saf1761_otg_softc *sc = device_get_softc(dev);
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device_t bdev;
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int err;
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if (sc->sc_bus.bdev) {
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bdev = sc->sc_bus.bdev;
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device_detach(bdev);
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device_delete_child(dev, bdev);
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}
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/* during module unload there are lots of children leftover */
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device_delete_children(dev);
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if (sc->sc_irq_res && sc->sc_intr_hdl) {
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/*
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* Only call uninit() after init()
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*/
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saf1761_otg_uninit(sc);
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err = bus_teardown_intr(dev, sc->sc_irq_res,
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sc->sc_intr_hdl);
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sc->sc_intr_hdl = NULL;
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}
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if (sc->sc_irq_res) {
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bus_release_resource(dev, SYS_RES_IRQ, 0,
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sc->sc_irq_res);
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sc->sc_irq_res = NULL;
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}
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if (sc->sc_io_res) {
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bus_release_resource(dev, SYS_RES_IOPORT, 0,
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sc->sc_io_res);
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sc->sc_io_res = NULL;
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}
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usb_bus_mem_free_all(&sc->sc_bus, NULL);
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return (0);
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}
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214
sys/dev/usb/controller/saf1761_otg_reg.h
Normal file
214
sys/dev/usb/controller/saf1761_otg_reg.h
Normal file
@ -0,0 +1,214 @@
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/* $FreeBSD$ */
|
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/*-
|
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* Copyright (c) 2014 Hans Petter Selasky <hselasky@FreeBSD.org>
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software was developed by SRI International and the University of
|
||||
* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
|
||||
* ("CTSRD"), as part of the DARPA CRASH research programme.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _SAF1761_OTG_REG_H_
|
||||
#define _SAF1761_OTG_REG_H_
|
||||
|
||||
/* Global registers */
|
||||
|
||||
#define SOTG_VEND_ID 0x370
|
||||
#define SOTG_PROD_ID 0x372
|
||||
#define SOTG_CTRL_SET 0x374
|
||||
#define SOTG_CTRL_CLR 0x376
|
||||
#define SOTG_CTRL_OTG_DISABLE (1 << 10)
|
||||
#define SOTG_CTRL_OTG_SE0_EN (1 << 9)
|
||||
#define SOTG_CTRL_BDIS_ACON_EN (1 << 8)
|
||||
#define SOTG_CTRL_SW_SEL_HC_DC (1 << 7)
|
||||
#define SOTG_CTRL_VBUS_CHRG (1 << 6)
|
||||
#define SOTG_CTRL_VBUS_DISCHRG (1 << 5)
|
||||
#define SOTG_CTRL_VBUS_DRV (1 << 4)
|
||||
#define SOTG_CTRL_SEL_CP_EXT (1 << 3)
|
||||
#define SOTG_CTRL_DM_PULL_DOWN (1 << 2)
|
||||
#define SOTG_CTRL_DP_PULL_DOWN (1 << 1)
|
||||
#define SOTG_CTRL_DP_PULL_UP (1 << 0)
|
||||
#define SOTG_STATUS 0x378
|
||||
#define SOTG_STATUS_B_SE0_SRP (1 << 8)
|
||||
#define SOTG_STATUS_B_SESS_END (1 << 7)
|
||||
#define SOTG_STATUS_RMT_CONN (1 << 4)
|
||||
#define SOTG_STATUS_ID (1 << 3)
|
||||
#define SOTG_STATUS_DP_SRP (1 << 2)
|
||||
#define SOTG_STATUS_A_B_SESS_VLD (1 << 1)
|
||||
#define SOTG_STATUS_VBUS_VLD (1 << 0)
|
||||
#define SOTG_IRQ_LATCH_SET 0x37C
|
||||
#define SOTG_IRQ_LATCH_CLR 0x37E
|
||||
#define SOTG_IRQ_ENABLE_SET 0x380
|
||||
#define SOTG_IRQ_ENABLE_CLR 0x382
|
||||
#define SOTG_IRQ_RISE_SET 0x384
|
||||
#define SOTG_IRQ_RISE_CLR 0x386
|
||||
#define SOTG_IRQ_OTG_TMR_TIMEOUT (1 << 9)
|
||||
#define SOTG_IRQ_B_SE0_SRP (1 << 8)
|
||||
#define SOTG_IRQ_B_SESS_END (1 << 7)
|
||||
#define SOTG_IRQ_BDIS_ACON (1 << 6)
|
||||
#define SOTG_IRQ_OTG_RESUME (1 << 5)
|
||||
#define SOTG_IRQ_RMT_CONN (1 << 4)
|
||||
#define SOTG_IRQ_ID (1 << 3)
|
||||
#define SOTG_IRQ_DP_SRP (1 << 2)
|
||||
#define SOTG_IRQ_A_B_SESS_VLD (1 << 1)
|
||||
#define SOTG_IRQ_VBUS_VLD (1 << 0)
|
||||
#define SOTG_TIMER_LOW_SET 0x388
|
||||
#define SOTG_TIMER_LOW_CLR 0x38A
|
||||
#define SOTG_TIMER_HIGH_SET 0x38C
|
||||
#define SOTG_TIMER_HIGH_CLR 0x38E
|
||||
#define SOTG_TIMER_START_TMR (1U << 15)
|
||||
|
||||
/* Peripheral controller specific registers */
|
||||
|
||||
#define SOTG_ADDRESS 0x200
|
||||
#define SOTG_ADDRESS_ENABLE (1 << 7)
|
||||
#define SOTG_MODE 0x20C
|
||||
#define SOTG_MODE_DMACLK_ON (1 << 9)
|
||||
#define SOTG_MODE_VBUSSTAT (1 << 8)
|
||||
#define SOTG_MODE_CLKAON (1 << 7)
|
||||
#define SOTG_MODE_SNDRSU (1 << 6)
|
||||
#define SOTG_MODE_GOSUSP (1 << 5)
|
||||
#define SOTG_MODE_SFRESET (1 << 4)
|
||||
#define SOTG_MODE_GLINTENA (1 << 3)
|
||||
#define SOTG_MODE_WKUPCS (1 << 2)
|
||||
#define SOTG_INTERRUPT_CFG 0x210
|
||||
#define SOTG_INTERRUPT_CFG_CDBGMOD (3 << 6)
|
||||
#define SOTG_INTERRUPT_CFG_DDBGMODIN (3 << 4)
|
||||
#define SOTG_INTERRUPT_CFG_DDBGMODOUT (3 << 2)
|
||||
#define SOTG_INTERRUPT_CFG_INTLVL (1 << 1)
|
||||
#define SOTG_INTERRUPT_CFG_INTPOL (1 << 0)
|
||||
#define SOTG_DEBUG 0x212
|
||||
#define SOTG_DEBUG_SET (1 << 0)
|
||||
#define SOTG_DCINTERRUPT_EN 0x214
|
||||
#define SOTG_HW_MODE_CTRL 0x300
|
||||
#define SOTG_HW_MODE_CTRL_ALL_ATX_RESET (1 << 31)
|
||||
#define SOTG_HW_MODE_CTRL_ANA_DIGI_OC (1 << 15)
|
||||
#define SOTG_HW_MODE_CTRL_DEV_DMA (1 << 11)
|
||||
#define SOTG_HW_MODE_CTRL_COMN_INT (1 << 10)
|
||||
#define SOTG_HW_MODE_CTRL_COMN_DMA (1 << 9)
|
||||
#define SOTG_HW_MODE_CTRL_DATA_BUS_WIDTH (1 << 8)
|
||||
#define SOTG_HW_MODE_CTRL_DACK_POL (1 << 6)
|
||||
#define SOTG_HW_MODE_CTRL_DREQ_POL (1 << 5)
|
||||
#define SOTG_HW_MODE_CTRL_INTR_POL (1 << 2)
|
||||
#define SOTG_HW_MODE_CTRL_INTR_LEVEL (1 << 1)
|
||||
#define SOTG_HW_MODE_CTRL_GLOBAL_INTR_EN (1 << 0)
|
||||
#define SOTG_OTG_CTRL 0x374
|
||||
#define SOTG_EP_INDEX 0x22c
|
||||
#define SOTG_EP_INDEX_EP0SETUP (1 << 5)
|
||||
#define SOTG_EP_INDEX_ENDP_INDEX_MASK (15 << 1)
|
||||
#define SOTG_EP_INDEX_ENDP_INDEX_SHIFT 1
|
||||
#define SOTG_EP_INDEX_DIR_IN (1 << 0)
|
||||
#define SOTG_EP_INDEX_DIR_OUT 0
|
||||
#define SOTG_CTRL_FUNC 0x228
|
||||
#define SOTG_CTRL_FUNC_CLBUF (1 << 4)
|
||||
#define SOTG_CTRL_FUNC_VENDP (1 << 3)
|
||||
#define SOTG_CTRL_FUNC_DSEN (1 << 2)
|
||||
#define SOTG_CTRL_FUNC_STATUS (1 << 1)
|
||||
#define SOTG_CTRL_FUNC_STALL (1 << 0)
|
||||
#define SOTG_DATA_PORT 0x220
|
||||
#define SOTG_BUF_LENGTH 0x21C
|
||||
#define SOTG_DCBUFFERSTATUS 0x21E
|
||||
#define SOTG_DCBUFFERSTATUS_FILLED_MASK (3 << 0)
|
||||
#define SOTG_EP_MAXPACKET 0x204
|
||||
#define SOTG_EP_TYPE 0x208
|
||||
#define SOTG_EP_TYPE_NOEMPPKT (1 << 4)
|
||||
#define SOTG_EP_TYPE_ENABLE (1 << 3)
|
||||
#define SOTG_EP_TYPE_DBLBUF (1 << 2)
|
||||
#define SOTG_EP_TYPE_EP_TYPE (3 << 0)
|
||||
#define SOTG_DMA_CMD 0x230
|
||||
#define SOTG_DMA_XFER_COUNT 0x234
|
||||
#define SOTG_DCDMA_CFG 0x238
|
||||
#define SOTG_DMA_HW 0x23C
|
||||
#define SOTG_DMA_IRQ_REASON 0x250
|
||||
#define SOTG_DMA_IRQ_ENABLE 0x254
|
||||
#define SOTG_DMA_EP 0x258
|
||||
#define SOTG_BURST_COUNTER 0x264
|
||||
#define SOTG_DCINTERRUPT 0x218
|
||||
#define SOTG_DCINTERRUPT_IEPRX(n) (1 << (10 + (2*(n))))
|
||||
#define SOTG_DCINTERRUPT_IEPTX(n) (1 << (11 + (2*(n))))
|
||||
#define SOTG_DCINTERRUPT_IEP0SETUP (1 << 8)
|
||||
#define SOTG_DCINTERRUPT_IEVBUS (1 << 7)
|
||||
#define SOTG_DCINTERRUPT_IEDMA (1 << 6)
|
||||
#define SOTG_DCINTERRUPT_IEHS_STA (1 << 5)
|
||||
#define SOTG_DCINTERRUPT_IERESM (1 << 4)
|
||||
#define SOTG_DCINTERRUPT_IESUSP (1 << 3)
|
||||
#define SOTG_DCINTERRUPT_IEPSOF (1 << 2)
|
||||
#define SOTG_DCINTERRUPT_IESOF (1 << 1)
|
||||
#define SOTG_DCINTERRUPT_IEBRST (1 << 0)
|
||||
#define SOTG_DCCHIP_ID 0x270
|
||||
#define SOTG_FRAME_NUM 0x274
|
||||
#define SOTG_FRAME_NUM_MICROSOFR_MASK 0x3800
|
||||
#define SOTG_FRAME_NUM_MICROSOFR_SHIFT 11
|
||||
#define SOTG_FRAME_NUM_SOFR_MASK 0x7FF
|
||||
#define SOTG_DCSCRATCH 0x278
|
||||
#define SOTG_UNLOCK_DEVICE 0x27C
|
||||
#define SOTG_UNLOCK_DEVICE_CODE 0xAA37
|
||||
#define SOTG_IRQ_PULSE_WIDTH 0x280
|
||||
#define SOTG_TEST_MODE 0x284
|
||||
#define SOTG_TEST_MODE_FORCEHS (1 << 7)
|
||||
#define SOTG_TEST_MODE_FORCEFS (1 << 4)
|
||||
#define SOTG_TEST_MODE_PRBS (1 << 3)
|
||||
#define SOTG_TEST_MODE_KSTATE (1 << 2)
|
||||
#define SOTG_TEST_MODE_JSTATE (1 << 1)
|
||||
#define SOTG_TEST_MODE_SE0_NAK (1 << 0)
|
||||
|
||||
/* Host controller specific registers */
|
||||
|
||||
#define SOTG_CONFIGFLAG 0x0060
|
||||
#define SOTG_CONFIGFLAG_ENABLE (1 << 0)
|
||||
#define SOTG_PORTSC1 0x0064
|
||||
#define SOTG_PORTSC1_PIC (3 << 14)
|
||||
#define SOTG_PORTSC1_PO (1 << 13)
|
||||
#define SOTG_PORTSC1_PP (1 << 12)
|
||||
#define SOTG_PORTSC1_LS (3 << 10)
|
||||
#define SOTG_PORTSC1_PR (1 << 8)
|
||||
#define SOTG_PORTSC1_SUSP (1 << 7)
|
||||
#define SOTG_PORTSC1_FPR (1 << 6)
|
||||
#define SOTG_PORTSC1_PED (1 << 2)
|
||||
#define SOTG_PORTSC1_ECSC (1 << 1)
|
||||
#define SOTG_PORTSC1_ECCS (1 << 0)
|
||||
#define SOTG_DATA_ADDR(x) (0x400 + (512 * (x)))
|
||||
#define SOTG_ASYNC_PDT(x) (0x400 + (60 * 1024) + ((x) * 32))
|
||||
#define SOTG_INTR_PDT(x) (0x400 + (61 * 1024) + ((x) * 32))
|
||||
#define SOTG_ISOC_PDT(x) (0x400 + (62 * 1024) + ((x) * 32))
|
||||
#define SOTG_HC_MEMORY_ADDR(x) (((x) - 0x400) >> 3)
|
||||
#define SOTG_SW_RESET 0x30C
|
||||
#define SOTG_SW_RESET_HC (1 << 1)
|
||||
#define SOTG_SW_RESET_ALL (1 << 0)
|
||||
#define SOTG_POWER_DOWN 0x354
|
||||
#define SOTG_POWER_DOWN_PORT3_PD (1 << 12)
|
||||
#define SOTG_POWER_DOWN_PORT2_PD (1 << 11)
|
||||
#define SOTG_POWER_DOWN_VBATDET_PWR (1 << 10)
|
||||
#define SOTG_POWER_DOWN_BIAS_EN (1 << 5)
|
||||
#define SOTG_POWER_DOWN_VREG_ON (1 << 4)
|
||||
#define SOTG_POWER_DOWN_OC3_PWR (1 << 3)
|
||||
#define SOTG_POWER_DOWN_OC2_PWR (1 << 2)
|
||||
#define SOTG_POWER_DOWN_OC1_PWR (1 << 1)
|
||||
#define SOTG_POWER_DOWN_HC_CLK_EN (1 << 0)
|
||||
#define SOTG_USBCMD 0x20
|
||||
#define SOTG_USBCMD_LHCR (1 << 7)
|
||||
#define SOTG_USBCMD_HCRESET (1 << 1)
|
||||
#define SOTG_USBCMD_RS (1 << 0)
|
||||
|
||||
#endif /* _SAF1761_OTG_REG_H_ */
|
||||
@ -36,7 +36,7 @@ S= ${.CURDIR}/../../..
|
||||
KMOD= saf1761
|
||||
SRCS= bus_if.h device_if.h usb_if.h \
|
||||
opt_bus.h opt_usb.h ofw_bus_if.h \
|
||||
saf1761_dci.c saf1761_dci_fdt.c \
|
||||
saf1761_otg.c saf1761_otg_fdt.c \
|
||||
pci_if.h
|
||||
|
||||
.include <bsd.kmod.mk>
|
||||
|
||||
Loading…
Reference in New Issue
Block a user