Allow cxgbtool to build with WARNS=6
MFC after: 1 week
This commit is contained in:
Navdeep Parhar
parent
8d521790d0
commit
5310975100
@ -85,7 +85,8 @@ struct reg_info {
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static const char *progname;
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static void __attribute__((noreturn)) usage(FILE *fp)
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static void
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usage(FILE *fp)
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{
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fprintf(fp, "Usage: %s <interface> [operation]\n", progname);
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fprintf(fp,
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@ -136,7 +137,8 @@ doit(const char *iff_name, unsigned long cmd, void *data)
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return ioctl(fd, cmd, data) < 0 ? -1 : 0;
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}
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static int get_int_arg(const char *s, uint32_t *valp)
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static int
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get_int_arg(const char *s, uint32_t *valp)
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{
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char *p;
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@ -172,11 +174,12 @@ write_reg(const char *iff_name, uint32_t addr, uint32_t val)
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err(1, "register write");
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}
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static int register_io(int argc, char *argv[], int start_arg,
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static int
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register_io(int argc, char *argv[], int start_arg,
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const char *iff_name)
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{
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char *p;
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uint32_t addr, val = 0, write = 0;
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uint32_t addr, val = 0, w = 0;
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if (argc != start_arg + 1) return -1;
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@ -184,14 +187,14 @@ static int register_io(int argc, char *argv[], int start_arg,
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if (p == argv[start_arg]) return -1;
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if (*p == '=' && p[1]) {
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val = strtoul(p + 1, &p, 0);
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write = 1;
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w = 1;
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}
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if (*p) {
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warnx("bad parameter \"%s\"", argv[start_arg]);
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return -1;
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}
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if (write)
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if (w)
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write_reg(iff_name, addr, val);
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else {
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val = read_reg(iff_name, addr);
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@ -200,9 +203,9 @@ static int register_io(int argc, char *argv[], int start_arg,
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return 0;
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}
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static int mdio_io(int argc, char *argv[], int start_arg, const char *iff_name)
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static int
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mdio_io(int argc, char *argv[], int start_arg, const char *iff_name)
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{
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struct ifreq ifr;
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struct ch_mii_data p;
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unsigned int cmd, phy_addr, reg, mmd, val;
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@ -230,12 +233,14 @@ static int mdio_io(int argc, char *argv[], int start_arg, const char *iff_name)
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return 0;
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}
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static inline uint32_t xtract(uint32_t val, int shift, int len)
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static inline
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uint32_t xtract(uint32_t val, int shift, int len)
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{
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return (val >> shift) & ((1 << len) - 1);
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}
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static int dump_block_regs(const struct reg_info *reg_array, uint32_t *regs)
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static int
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dump_block_regs(const struct reg_info *reg_array, uint32_t *regs)
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{
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uint32_t reg_val = 0; // silence compiler warning
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@ -254,7 +259,8 @@ static int dump_block_regs(const struct reg_info *reg_array, uint32_t *regs)
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return 1;
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}
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static int dump_regs_t2(int argc, char *argv[], int start_arg, uint32_t *regs)
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static int
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dump_regs_t2(int argc, char *argv[], int start_arg, uint32_t *regs)
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{
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int match = 0;
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char *block_name = NULL;
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@ -292,8 +298,8 @@ static int dump_regs_t2(int argc, char *argv[], int start_arg, uint32_t *regs)
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}
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#if defined(CONFIG_T3_REGS)
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static int dump_regs_t3(int argc, char *argv[], int start_arg, uint32_t *regs,
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int is_pcie)
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static int
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dump_regs_t3(int argc, char *argv[], int start_arg, uint32_t *regs, int is_pcie)
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{
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int match = 0;
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char *block_name = NULL;
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@ -353,8 +359,9 @@ static int dump_regs_t3(int argc, char *argv[], int start_arg, uint32_t *regs,
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return 0;
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}
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static int dump_regs_t3b(int argc, char *argv[], int start_arg, uint32_t *regs,
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int is_pcie)
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static int
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dump_regs_t3b(int argc, char *argv[], int start_arg, uint32_t *regs,
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int is_pcie)
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{
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int match = 0;
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char *block_name = NULL;
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@ -414,8 +421,9 @@ static int dump_regs_t3b(int argc, char *argv[], int start_arg, uint32_t *regs,
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return 0;
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}
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static int dump_regs_t3c(int argc, char *argv[], int start_arg, uint32_t *regs,
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int is_pcie)
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static int
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dump_regs_t3c(int argc, char *argv[], int start_arg, uint32_t *regs,
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int is_pcie)
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{
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int match = 0;
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char *block_name = NULL;
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@ -479,7 +487,7 @@ static int dump_regs_t3c(int argc, char *argv[], int start_arg, uint32_t *regs,
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static int
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dump_regs(int argc, char *argv[], int start_arg, const char *iff_name)
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{
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int i, vers, revision, is_pcie;
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int vers, revision, is_pcie;
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struct ch_ifconf_regs regs;
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regs.len = REGDUMP_SIZE;
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@ -514,7 +522,8 @@ dump_regs(int argc, char *argv[], int start_arg, const char *iff_name)
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return 0;
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}
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static int t3_meminfo(const uint32_t *regs)
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static int
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t3_meminfo(const uint32_t *regs)
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{
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enum {
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SG_EGR_CNTX_BADDR = 0x58,
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@ -592,11 +601,16 @@ static int t3_meminfo(const uint32_t *regs)
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return 0;
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}
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static int meminfo(int argc, char *argv[], int start_arg, const char *iff_name)
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static int
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meminfo(int argc, char *argv[], int start_arg, const char *iff_name)
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{
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int vers;
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struct ch_ifconf_regs regs;
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(void) argc;
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(void) argv;
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(void) start_arg;
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regs.len = REGDUMP_SIZE;
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if ((regs.data = malloc(regs.len)) == NULL)
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err(1, "can't malloc");
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@ -612,11 +626,11 @@ static int meminfo(int argc, char *argv[], int start_arg, const char *iff_name)
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return 0;
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}
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static int mtu_tab_op(int argc, char *argv[], int start_arg,
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const char *iff_name)
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static int
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mtu_tab_op(int argc, char *argv[], int start_arg, const char *iff_name)
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{
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struct ch_mtus m;
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int i;
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unsigned int i;
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if (argc == start_arg) {
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if (doit(iff_name, CHELSIO_GETMTUTAB, &m) < 0)
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@ -649,13 +663,14 @@ static int mtu_tab_op(int argc, char *argv[], int start_arg,
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}
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#ifdef CHELSIO_INTERNAL
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static void show_egress_cntxt(uint32_t data[])
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static void
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show_egress_cntxt(uint32_t data[])
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{
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printf("credits: %u\n", data[0] & 0x7fff);
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printf("GTS: %u\n", (data[0] >> 15) & 1);
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printf("index: %u\n", data[0] >> 16);
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printf("queue size: %u\n", data[1] & 0xffff);
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printf("base address: 0x%llx\n",
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printf("base address: 0x%" PRIx64 "\n",
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((data[1] >> 16) | ((uint64_t)data[2] << 16) |
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(((uint64_t)data[3] & 0xf) << 48)) << 12);
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printf("rsp queue #: %u\n", (data[3] >> 4) & 7);
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@ -667,9 +682,10 @@ static void show_egress_cntxt(uint32_t data[])
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printf("valid: %u\n", (data[3] >> 31) & 1);
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}
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static void show_fl_cntxt(uint32_t data[])
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static void
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show_fl_cntxt(uint32_t data[])
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{
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printf("base address: 0x%llx\n",
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printf("base address: 0x%" PRIx64 "\n",
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((uint64_t)data[0] | ((uint64_t)data[1] & 0xfffff) << 32) << 12);
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printf("index: %u\n", (data[1] >> 20) | ((data[2] & 0xf) << 12));
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printf("queue size: %u\n", (data[2] >> 4) & 0xffff);
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@ -680,11 +696,12 @@ static void show_fl_cntxt(uint32_t data[])
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printf("GTS: %u\n", (data[3] >> 31) & 1);
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}
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static void show_response_cntxt(uint32_t data[])
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static void
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show_response_cntxt(uint32_t data[])
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{
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printf("index: %u\n", data[0] & 0xffff);
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printf("size: %u\n", data[0] >> 16);
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printf("base address: 0x%llx\n",
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printf("base address: 0x%" PRIx64 "\n",
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((uint64_t)data[1] | ((uint64_t)data[2] & 0xfffff) << 32) << 12);
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printf("MSI-X/RspQ: %u\n", (data[2] >> 20) & 0x3f);
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printf("intr enable: %u\n", (data[2] >> 26) & 1);
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@ -694,11 +711,12 @@ static void show_response_cntxt(uint32_t data[])
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printf("FL threshold: %u\n", data[3]);
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}
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static void show_cq_cntxt(uint32_t data[])
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static void
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show_cq_cntxt(uint32_t data[])
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{
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printf("index: %u\n", data[0] & 0xffff);
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printf("size: %u\n", data[0] >> 16);
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printf("base address: 0x%llx\n",
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printf("base address: 0x%" PRIx64 "\n",
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((uint64_t)data[1] | ((uint64_t)data[2] & 0xfffff) << 32) << 12);
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printf("rsp queue #: %u\n", (data[2] >> 20) & 0x3f);
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printf("AN: %u\n", (data[2] >> 26) & 1);
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@ -710,8 +728,8 @@ static void show_cq_cntxt(uint32_t data[])
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printf("credit threshold: %u\n", data[3] >> 16);
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}
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static int get_sge_context(int argc, char *argv[], int start_arg,
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const char *iff_name)
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static int
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get_sge_context(int argc, char *argv[], int start_arg, const char *iff_name)
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{
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struct ch_cntxt ctx;
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@ -750,8 +768,8 @@ static int get_sge_context(int argc, char *argv[], int start_arg,
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#define ntohll(x) be64toh((x))
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static int get_sge_desc(int argc, char *argv[], int start_arg,
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const char *iff_name)
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static int
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get_sge_desc(int argc, char *argv[], int start_arg, const char *iff_name)
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{
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uint64_t *p, wr_hdr;
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unsigned int n = 1, qset, qnum;
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@ -796,7 +814,8 @@ static int get_sge_desc(int argc, char *argv[], int start_arg,
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}
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#endif
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static int get_tcb2(int argc, char *argv[], int start_arg, const char *iff_name)
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static int
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get_tcb2(int argc, char *argv[], int start_arg, const char *iff_name)
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{
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uint64_t *d;
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unsigned int i;
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@ -835,8 +854,9 @@ static int get_tcb2(int argc, char *argv[], int start_arg, const char *iff_name)
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return 0;
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}
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static int get_pm_page_spec(const char *s, unsigned int *page_size,
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unsigned int *num_pages)
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static int
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get_pm_page_spec(const char *s, unsigned int *page_size,
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unsigned int *num_pages)
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{
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char *p;
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unsigned long val;
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@ -854,7 +874,8 @@ static int get_pm_page_spec(const char *s, unsigned int *page_size,
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return *p;
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}
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static int conf_pm(int argc, char *argv[], int start_arg, const char *iff_name)
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static int
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conf_pm(int argc, char *argv[], int start_arg, const char *iff_name)
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{
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struct ch_pm pm;
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@ -884,8 +905,8 @@ static int conf_pm(int argc, char *argv[], int start_arg, const char *iff_name)
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}
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#ifdef CHELSIO_INTERNAL
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static int dump_tcam(int argc, char *argv[], int start_arg,
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const char *iff_name)
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static int
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dump_tcam(int argc, char *argv[], int start_arg, const char *iff_name)
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{
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unsigned int nwords;
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struct ch_tcam_word op;
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@ -907,7 +928,8 @@ static int dump_tcam(int argc, char *argv[], int start_arg,
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return 0;
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}
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static void hexdump_8b(unsigned int start, uint64_t *data, unsigned int len)
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static void
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hexdump_8b(unsigned int start, uint64_t *data, unsigned int len)
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{
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int i;
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@ -920,8 +942,8 @@ static void hexdump_8b(unsigned int start, uint64_t *data, unsigned int len)
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}
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}
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static int dump_mc7(int argc, char *argv[], int start_arg,
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const char *iff_name)
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static int
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dump_mc7(int argc, char *argv[], int start_arg, const char *iff_name)
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{
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struct ch_mem_range mem;
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unsigned int mem_id, addr, len;
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@ -959,10 +981,11 @@ static int dump_mc7(int argc, char *argv[], int start_arg,
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}
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#endif
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/* Max FW size is 32K including version, +4 bytes for the checksum. */
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/* Max FW size is 64K including version, +4 bytes for the checksum. */
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#define MAX_FW_IMAGE_SIZE (64 * 1024)
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static int load_fw(int argc, char *argv[], int start_arg, const char *iff_name)
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static int
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load_fw(int argc, char *argv[], int start_arg, const char *iff_name)
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{
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int fd, len;
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struct ch_mem_range op;
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@ -979,12 +1002,13 @@ static int load_fw(int argc, char *argv[], int start_arg, const char *iff_name)
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if (!op.buf)
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err(1, "load firmware");
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op.len = read(fd, op.buf, MAX_FW_IMAGE_SIZE + 1);
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if (op.len < 0)
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len = read(fd, op.buf, MAX_FW_IMAGE_SIZE + 1);
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if (len < 0)
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err(1, "load firmware");
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if (op.len > MAX_FW_IMAGE_SIZE)
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if (len > MAX_FW_IMAGE_SIZE)
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errx(1, "FW image too large");
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op.len = len;
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if (doit(iff_name, CHELSIO_LOAD_FW, &op) < 0)
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err(1, "load firmware");
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return 0;
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@ -993,8 +1017,8 @@ static int load_fw(int argc, char *argv[], int start_arg, const char *iff_name)
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/* Max BOOT size is 255*512 bytes including the BIOS boot ROM basic header */
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#define MAX_BOOT_IMAGE_SIZE (0xff * 512)
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static int load_boot(int argc, char *argv[],
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int start_arg, const char *iff_name)
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static int
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load_boot(int argc, char *argv[], int start_arg, const char *iff_name)
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{
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int fd, len;
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struct ch_mem_range op;
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@ -1024,7 +1048,8 @@ static int load_boot(int argc, char *argv[],
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return 0;
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}
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static int dump_proto_sram(const char *iff_name)
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static int
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dump_proto_sram(const char *iff_name)
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{
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int i, j;
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uint8_t buf[PROTO_SRAM_SIZE];
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@ -1054,15 +1079,20 @@ static int dump_proto_sram(const char *iff_name)
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return 0;
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}
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static int proto_sram_op(int argc, char *argv[], int start_arg,
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static int
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proto_sram_op(int argc, char *argv[], int start_arg,
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const char *iff_name)
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{
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(void) argv;
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(void) start_arg;
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if (argc == start_arg)
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return dump_proto_sram(iff_name);
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return -1;
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}
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static int dump_qset_params(const char *iff_name)
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static int
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dump_qset_params(const char *iff_name)
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{
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struct ch_qset_params qp;
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@ -1084,10 +1114,10 @@ static int dump_qset_params(const char *iff_name)
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return 0;
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}
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static int qset_config(int argc, char *argv[], int start_arg,
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const char *iff_name)
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static int
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qset_config(int argc, char *argv[], int start_arg, const char *iff_name)
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{
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struct ch_qset_params qp;
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(void) argv;
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if (argc == start_arg)
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return dump_qset_params(iff_name);
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@ -1095,11 +1125,13 @@ static int qset_config(int argc, char *argv[], int start_arg,
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return -1;
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}
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static int qset_num_config(int argc, char *argv[], int start_arg,
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const char *iff_name)
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static int
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qset_num_config(int argc, char *argv[], int start_arg, const char *iff_name)
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{
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struct ch_reg reg;
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(void) argv;
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|
||||
if (argc == start_arg) {
|
||||
if (doit(iff_name, CHELSIO_GET_QSET_NUM, ®) < 0)
|
||||
err(1, "get qsets");
|
||||
@ -1113,7 +1145,8 @@ static int qset_num_config(int argc, char *argv[], int start_arg,
|
||||
/*
|
||||
* Parse a string containing an IP address with an optional network prefix.
|
||||
*/
|
||||
static int parse_ipaddr(const char *s, uint32_t *addr, uint32_t *mask)
|
||||
static int
|
||||
parse_ipaddr(const char *s, uint32_t *addr, uint32_t *mask)
|
||||
{
|
||||
char *p, *slash;
|
||||
struct in_addr ia;
|
||||
@ -1143,7 +1176,8 @@ static int parse_ipaddr(const char *s, uint32_t *addr, uint32_t *mask)
|
||||
/*
|
||||
* Parse a string containing a value and an optional colon separated mask.
|
||||
*/
|
||||
static int parse_val_mask_param(const char *s, uint32_t *val, uint32_t *mask)
|
||||
static int
|
||||
parse_val_mask_param(const char *s, uint32_t *val, uint32_t *mask)
|
||||
{
|
||||
char *p;
|
||||
|
||||
@ -1156,14 +1190,15 @@ static int parse_val_mask_param(const char *s, uint32_t *val, uint32_t *mask)
|
||||
return *p ? -1 : 0;
|
||||
}
|
||||
|
||||
static int parse_trace_param(const char *s, uint32_t *val, uint32_t *mask)
|
||||
static int
|
||||
parse_trace_param(const char *s, uint32_t *val, uint32_t *mask)
|
||||
{
|
||||
return strchr(s, '.') ? parse_ipaddr(s, val, mask) :
|
||||
parse_val_mask_param(s, val, mask);
|
||||
}
|
||||
|
||||
static int trace_config(int argc, char *argv[], int start_arg,
|
||||
const char *iff_name)
|
||||
static int
|
||||
trace_config(int argc, char *argv[], int start_arg, const char *iff_name)
|
||||
{
|
||||
uint32_t val, mask;
|
||||
struct ch_trace trace;
|
||||
@ -1238,7 +1273,8 @@ static int trace_config(int argc, char *argv[], int start_arg,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int get_sched_param(int argc, char *argv[], int pos, unsigned int *valp)
|
||||
static int
|
||||
get_sched_param(int argc, char *argv[], int pos, unsigned int *valp)
|
||||
{
|
||||
if (pos + 1 >= argc)
|
||||
errx(1, "missing value for %s", argv[pos]);
|
||||
@ -1247,7 +1283,8 @@ static int get_sched_param(int argc, char *argv[], int pos, unsigned int *valp)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tx_sched(int argc, char *argv[], int start_arg, const char *iff_name)
|
||||
static int
|
||||
tx_sched(int argc, char *argv[], int start_arg, const char *iff_name)
|
||||
{
|
||||
struct ch_hw_sched op;
|
||||
unsigned int idx, val;
|
||||
@ -1293,7 +1330,8 @@ static int tx_sched(int argc, char *argv[], int start_arg, const char *iff_name)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pktsched(int argc, char *argv[], int start_arg, const char *iff_name)
|
||||
static int
|
||||
pktsched(int argc, char *argv[], int start_arg, const char *iff_name)
|
||||
{
|
||||
struct ch_pktsched_params op;
|
||||
unsigned int idx, min = -1, max, binding = -1;
|
||||
@ -1333,20 +1371,29 @@ static int pktsched(int argc, char *argv[], int start_arg, const char *iff_name)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int clear_stats(int argc, char *argv[], int start_arg,
|
||||
const char *iff_name)
|
||||
static int
|
||||
clear_stats(int argc, char *argv[], int start_arg, const char *iff_name)
|
||||
{
|
||||
(void) argc;
|
||||
(void) argv;
|
||||
(void) start_arg;
|
||||
|
||||
if (doit(iff_name, CHELSIO_CLEAR_STATS, NULL) < 0)
|
||||
err(1, "clearstats");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int get_up_la(int argc, char *argv[], int start_arg, const char *iff_name)
|
||||
static int
|
||||
get_up_la(int argc, char *argv[], int start_arg, const char *iff_name)
|
||||
{
|
||||
struct ch_up_la la;
|
||||
int i, idx, max_idx, entries;
|
||||
|
||||
(void) argc;
|
||||
(void) argv;
|
||||
(void) start_arg;
|
||||
|
||||
la.stopped = 0;
|
||||
la.idx = -1;
|
||||
la.bufsize = LA_BUFSIZE;
|
||||
@ -1372,11 +1419,16 @@ static int get_up_la(int argc, char *argv[], int start_arg, const char *iff_name
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int get_up_ioqs(int argc, char *argv[], int start_arg, const char *iff_name)
|
||||
static int
|
||||
get_up_ioqs(int argc, char *argv[], int start_arg, const char *iff_name)
|
||||
{
|
||||
struct ch_up_ioqs ioqs;
|
||||
int i, entries;
|
||||
|
||||
(void) argc;
|
||||
(void) argv;
|
||||
(void) start_arg;
|
||||
|
||||
bzero(&ioqs, sizeof(ioqs));
|
||||
ioqs.bufsize = IOQS_BUFSIZE;
|
||||
ioqs.data = malloc(IOQS_BUFSIZE);
|
||||
@ -1465,10 +1517,12 @@ run_cmd(int argc, char *argv[], const char *iff_name)
|
||||
static int
|
||||
run_cmd_loop(int argc, char *argv[], const char *iff_name)
|
||||
{
|
||||
int n, i;
|
||||
int n;
|
||||
unsigned int i;
|
||||
char buf[64];
|
||||
char *args[8], *s;
|
||||
|
||||
(void) argc;
|
||||
args[0] = argv[0];
|
||||
args[1] = argv[1];
|
||||
|
||||
@ -1481,11 +1535,8 @@ run_cmd_loop(int argc, char *argv[], const char *iff_name)
|
||||
for (;;) {
|
||||
fprintf(stdout, "> ");
|
||||
fflush(stdout);
|
||||
n = read(STDIN_FILENO, buf, sizeof(buf));
|
||||
if (n > sizeof(buf) - 1) {
|
||||
fprintf(stdout, "too much input.\n");
|
||||
return (0);
|
||||
} else if (n <= 0)
|
||||
n = read(STDIN_FILENO, buf, sizeof(buf) - 1);
|
||||
if (n <= 0)
|
||||
return (0);
|
||||
|
||||
if (buf[--n] != '\n')
|
||||
|
||||
@ -106,7 +106,7 @@ struct reg_info sge_regs[] = {
|
||||
{ "Packet_Too_Big", 3, 1 },
|
||||
{ "Packet_Mismatch", 4, 1 },
|
||||
{ "SG_RESPACCUTIMER", 0xc0, 0 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info mc3_regs[] = {
|
||||
@ -196,7 +196,7 @@ struct reg_info mc3_regs[] = {
|
||||
{ "MC3_Uncorr_Err", 1, 1 },
|
||||
{ "MC3_Parity_Err", 2, 8 },
|
||||
{ "MC3_Addr_Err", 10, 1 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info mc4_regs[] = {
|
||||
@ -276,7 +276,7 @@ struct reg_info mc4_regs[] = {
|
||||
{ "MC4_Corr_Err", 0, 1 },
|
||||
{ "MC4_Uncorr_Err", 1, 1 },
|
||||
{ "MC4_Addr_Err", 2, 1 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info tpi_regs[] = {
|
||||
@ -290,7 +290,7 @@ struct reg_info tpi_regs[] = {
|
||||
{ "INT_DIR", 31, 1 },
|
||||
{ "TPI_PAR", 0x29c, 0 },
|
||||
{ "TPIPAR", 0, 7 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info tp_regs[] = {
|
||||
@ -509,7 +509,7 @@ struct reg_info tp_regs[] = {
|
||||
{ "DROP_TICKS_CNT", 4, 26 },
|
||||
{ "NUM_PKTS_DROPPED", 0, 4 },
|
||||
{ "TP_TX_DROP_COUNT", 0x4bc, 0 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info rat_regs[] = {
|
||||
@ -532,7 +532,7 @@ struct reg_info rat_regs[] = {
|
||||
{ "CspiFramingError", 1, 1 },
|
||||
{ "SgeFramingError", 2, 1 },
|
||||
{ "TpFramingError", 3, 1 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info cspi_regs[] = {
|
||||
@ -560,7 +560,7 @@ struct reg_info cspi_regs[] = {
|
||||
{ "TXDrop", 2, 1 },
|
||||
{ "RXOverflow", 3, 1 },
|
||||
{ "RAMParityErr", 4, 1 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info espi_regs[] = {
|
||||
@ -660,7 +660,7 @@ struct reg_info espi_regs[] = {
|
||||
{ "Error_Ack", 9, 1 },
|
||||
{ "Unmapped_Err", 10, 1 },
|
||||
{ "Transaction_Timer", 16, 8 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info ulp_regs[] = {
|
||||
@ -682,7 +682,7 @@ struct reg_info ulp_regs[] = {
|
||||
{ "Pm_E2C_Wrt_Full", 24, 1 },
|
||||
{ "Pm_C2E_Wrt_Full", 25, 1 },
|
||||
{ "ULP_PIO_CTRL", 0x998, 0 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info pl_regs[] = {
|
||||
@ -712,7 +712,7 @@ struct reg_info pl_regs[] = {
|
||||
{ "PL_Intr_CSPI", 9, 1 },
|
||||
{ "PL_Intr_PCIX", 10, 1 },
|
||||
{ "PL_Intr_EXT", 11, 1 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info mc5_regs[] = {
|
||||
@ -833,5 +833,5 @@ struct reg_info mc5_regs[] = {
|
||||
{ "MC5_DATA_WRITE_CMD", 0xcf4, 0 },
|
||||
{ "MC5_DATA_READ_CMD", 0xcf8, 0 },
|
||||
{ "MC5_MASK_WRITE_CMD", 0xcfc, 0 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
@ -140,7 +140,7 @@ struct reg_info sge3_regs[] = {
|
||||
{ "DrbPriThrsh", 0, 16 },
|
||||
{ "SG_DEBUG_INDEX", 0x78, 0 },
|
||||
{ "SG_DEBUG_DATA", 0x7c, 0 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info pcix1_regs[] = {
|
||||
@ -212,7 +212,7 @@ struct reg_info pcix1_regs[] = {
|
||||
{ "WakeUp0", 2, 1 },
|
||||
{ "SleepMode1", 1, 1 },
|
||||
{ "SleepMode0", 0, 1 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info pcie0_regs[] = {
|
||||
@ -411,7 +411,7 @@ struct reg_info pcie0_regs[] = {
|
||||
{ "BISTDone", 24, 8 },
|
||||
{ "BISTCycleThresh", 3, 16 },
|
||||
{ "BISTMode", 0, 3 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3dbg_regs[] = {
|
||||
@ -557,7 +557,7 @@ struct reg_info t3dbg_regs[] = {
|
||||
{ "PMON_CDEL_MANUAL", 4, 1 },
|
||||
{ "PMON_MANUAL", 1, 1 },
|
||||
{ "PMON_AUTO", 0, 1 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info mc7_pmrx_regs[] = {
|
||||
@ -674,7 +674,7 @@ struct reg_info mc7_pmrx_regs[] = {
|
||||
{ "PE", 2, 15 },
|
||||
{ "UE", 1, 1 },
|
||||
{ "CE", 0, 1 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info mc7_pmtx_regs[] = {
|
||||
@ -791,7 +791,7 @@ struct reg_info mc7_pmtx_regs[] = {
|
||||
{ "PE", 2, 15 },
|
||||
{ "UE", 1, 1 },
|
||||
{ "CE", 0, 1 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info mc7_cm_regs[] = {
|
||||
@ -908,7 +908,7 @@ struct reg_info mc7_cm_regs[] = {
|
||||
{ "PE", 2, 15 },
|
||||
{ "UE", 1, 1 },
|
||||
{ "CE", 0, 1 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info cim_regs[] = {
|
||||
@ -1024,7 +1024,7 @@ struct reg_info cim_regs[] = {
|
||||
{ "CIM_CDEBUGDATA", 0x2d0, 0 },
|
||||
{ "CDebugDataH", 16, 16 },
|
||||
{ "CDebugDataL", 0, 16 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info tp1_regs[] = {
|
||||
@ -1384,7 +1384,7 @@ struct reg_info tp1_regs[] = {
|
||||
{ "TP_EMBED_OP_FIELD3", 0x4f4, 0 },
|
||||
{ "TP_EMBED_OP_FIELD4", 0x4f8, 0 },
|
||||
{ "TP_EMBED_OP_FIELD5", 0x4fc, 0 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info ulp2_rx_regs[] = {
|
||||
@ -1428,7 +1428,7 @@ struct reg_info ulp2_rx_regs[] = {
|
||||
{ "ULPRX_RQ_ULIMIT", 0x538, 0 },
|
||||
{ "ULPRX_PBL_LLIMIT", 0x53c, 0 },
|
||||
{ "ULPRX_PBL_ULIMIT", 0x540, 0 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info ulp2_tx_regs[] = {
|
||||
@ -1456,7 +1456,7 @@ struct reg_info ulp2_tx_regs[] = {
|
||||
{ "ULPTX_DMA_WEIGHT", 0x5ac, 0 },
|
||||
{ "D1_WEIGHT", 16, 16 },
|
||||
{ "D0_WEIGHT", 0, 16 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info pm1_rx_regs[] = {
|
||||
@ -1500,7 +1500,7 @@ struct reg_info pm1_rx_regs[] = {
|
||||
{ "ocspi1_ofifo2x_Tx_framing_error", 6, 1 },
|
||||
{ "iespi_par_error", 3, 3 },
|
||||
{ "ocspi_par_error", 0, 3 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info pm1_tx_regs[] = {
|
||||
@ -1544,7 +1544,7 @@ struct reg_info pm1_tx_regs[] = {
|
||||
{ "oespi1_ofifo2x_Tx_framing_error", 6, 1 },
|
||||
{ "icspi_par_error", 3, 3 },
|
||||
{ "oespi_par_error", 0, 3 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info mps0_regs[] = {
|
||||
@ -1585,7 +1585,7 @@ struct reg_info mps0_regs[] = {
|
||||
{ "RXTpParErr", 4, 2 },
|
||||
{ "TX1TpParErr", 2, 2 },
|
||||
{ "TX0TpParErr", 0, 2 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info cpl_switch_regs[] = {
|
||||
@ -1616,7 +1616,7 @@ struct reg_info cpl_switch_regs[] = {
|
||||
{ "cpl_map_tbl_idx", 0, 8 },
|
||||
{ "CPL_MAP_TBL_DATA", 0x65c, 0 },
|
||||
{ "cpl_map_tbl_data", 0, 8 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info smb0_regs[] = {
|
||||
@ -1682,7 +1682,7 @@ struct reg_info smb0_regs[] = {
|
||||
{ "DebugDataL", 0, 16 },
|
||||
{ "SMB_DEBUG_LA", 0x69c, 0 },
|
||||
{ "DebugLAReqAddr", 0, 10 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info i2cm0_regs[] = {
|
||||
@ -1695,7 +1695,7 @@ struct reg_info i2cm0_regs[] = {
|
||||
{ "Ack", 30, 1 },
|
||||
{ "Cont", 1, 1 },
|
||||
{ "Op", 0, 1 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info mi1_regs[] = {
|
||||
@ -1714,7 +1714,7 @@ struct reg_info mi1_regs[] = {
|
||||
{ "Busy", 31, 1 },
|
||||
{ "Inc", 2, 1 },
|
||||
{ "Op", 0, 2 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info jm1_regs[] = {
|
||||
@ -1727,7 +1727,7 @@ struct reg_info jm1_regs[] = {
|
||||
{ "JM_OP", 0x6cc, 0 },
|
||||
{ "Busy", 31, 1 },
|
||||
{ "Cnt", 0, 5 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info sf1_regs[] = {
|
||||
@ -1737,7 +1737,7 @@ struct reg_info sf1_regs[] = {
|
||||
{ "Cont", 3, 1 },
|
||||
{ "ByteCnt", 1, 2 },
|
||||
{ "Op", 0, 1 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info pl3_regs[] = {
|
||||
@ -1839,7 +1839,7 @@ struct reg_info pl3_regs[] = {
|
||||
{ "PL_REV", 0x6f4, 0 },
|
||||
{ "Rev", 0, 4 },
|
||||
{ "PL_CLI", 0x6f8, 0 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info mc5a_regs[] = {
|
||||
@ -2010,7 +2010,7 @@ struct reg_info mc5a_regs[] = {
|
||||
{ "ReadCmd", 0, 20 },
|
||||
{ "MC5_DB_MASK_WRITE_CMD", 0x7fc, 0 },
|
||||
{ "MaskWr", 0, 16 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info xgmac0_0_regs[] = {
|
||||
@ -2341,7 +2341,7 @@ struct reg_info xgmac0_0_regs[] = {
|
||||
{ "XGM_RX_SPI4_SOP_EOP_CNT", 0x9ac, 0 },
|
||||
{ "RxSPI4SopCnt", 16, 16 },
|
||||
{ "RxSPI4EopCnt", 0, 16 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info xgmac0_1_regs[] = {
|
||||
@ -2672,5 +2672,5 @@ struct reg_info xgmac0_1_regs[] = {
|
||||
{ "XGM_RX_SPI4_SOP_EOP_CNT", 0xbac, 0 },
|
||||
{ "RxSPI4SopCnt", 16, 16 },
|
||||
{ "RxSPI4EopCnt", 0, 16 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
@ -150,7 +150,7 @@ struct reg_info t3b_sge3_regs[] = {
|
||||
{ "DrbPriThrsh", 0, 16 },
|
||||
{ "SG_DEBUG_INDEX", 0x78, 0 },
|
||||
{ "SG_DEBUG_DATA", 0x7c, 0 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3b_pcix1_regs[] = {
|
||||
@ -222,7 +222,7 @@ struct reg_info t3b_pcix1_regs[] = {
|
||||
{ "WakeUp0", 2, 1 },
|
||||
{ "SleepMode1", 1, 1 },
|
||||
{ "SleepMode0", 0, 1 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3b_pcie0_regs[] = {
|
||||
@ -376,7 +376,7 @@ struct reg_info t3b_pcie0_regs[] = {
|
||||
{ "BeaconDetect", 2, 1 },
|
||||
{ "RxDetect", 1, 1 },
|
||||
{ "TxIdleDetect", 0, 1 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3b_t3dbg_regs[] = {
|
||||
@ -557,7 +557,7 @@ struct reg_info t3b_t3dbg_regs[] = {
|
||||
{ "BSEnLane1", 4, 1 },
|
||||
{ "BSInSelLane0", 1, 2 },
|
||||
{ "BSEnLane0", 0, 1 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3b_mc7_pmrx_regs[] = {
|
||||
@ -678,7 +678,7 @@ struct reg_info t3b_mc7_pmrx_regs[] = {
|
||||
{ "PE", 2, 15 },
|
||||
{ "UE", 1, 1 },
|
||||
{ "CE", 0, 1 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3b_mc7_pmtx_regs[] = {
|
||||
@ -799,7 +799,7 @@ struct reg_info t3b_mc7_pmtx_regs[] = {
|
||||
{ "PE", 2, 15 },
|
||||
{ "UE", 1, 1 },
|
||||
{ "CE", 0, 1 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3b_mc7_cm_regs[] = {
|
||||
@ -920,7 +920,7 @@ struct reg_info t3b_mc7_cm_regs[] = {
|
||||
{ "PE", 2, 15 },
|
||||
{ "UE", 1, 1 },
|
||||
{ "CE", 0, 1 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3b_cim_regs[] = {
|
||||
@ -1047,7 +1047,7 @@ struct reg_info t3b_cim_regs[] = {
|
||||
{ "PILADbgWrPtr", 0, 9 },
|
||||
{ "CIM_PO_LA_DEBUGDATA", 0x2e8, 0 },
|
||||
{ "CIM_PI_LA_DEBUGDATA", 0x2ec, 0 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3b_tp1_regs[] = {
|
||||
@ -1453,7 +1453,7 @@ struct reg_info t3b_tp1_regs[] = {
|
||||
{ "TP_EMBED_OP_FIELD3", 0x4f4, 0 },
|
||||
{ "TP_EMBED_OP_FIELD4", 0x4f8, 0 },
|
||||
{ "TP_EMBED_OP_FIELD5", 0x4fc, 0 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3b_ulp2_rx_regs[] = {
|
||||
@ -1497,7 +1497,7 @@ struct reg_info t3b_ulp2_rx_regs[] = {
|
||||
{ "ULPRX_RQ_ULIMIT", 0x538, 0 },
|
||||
{ "ULPRX_PBL_LLIMIT", 0x53c, 0 },
|
||||
{ "ULPRX_PBL_ULIMIT", 0x540, 0 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3b_ulp2_tx_regs[] = {
|
||||
@ -1525,7 +1525,7 @@ struct reg_info t3b_ulp2_tx_regs[] = {
|
||||
{ "ULPTX_DMA_WEIGHT", 0x5ac, 0 },
|
||||
{ "D1_WEIGHT", 16, 16 },
|
||||
{ "D0_WEIGHT", 0, 16 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3b_pm1_rx_regs[] = {
|
||||
@ -1569,7 +1569,7 @@ struct reg_info t3b_pm1_rx_regs[] = {
|
||||
{ "ocspi1_ofifo2x_Tx_framing_error", 6, 1 },
|
||||
{ "iespi_par_error", 3, 3 },
|
||||
{ "ocspi_par_error", 0, 3 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3b_pm1_tx_regs[] = {
|
||||
@ -1613,7 +1613,7 @@ struct reg_info t3b_pm1_tx_regs[] = {
|
||||
{ "oespi1_ofifo2x_Tx_framing_error", 6, 1 },
|
||||
{ "icspi_par_error", 3, 3 },
|
||||
{ "oespi_par_error", 0, 3 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3b_mps0_regs[] = {
|
||||
@ -1655,7 +1655,7 @@ struct reg_info t3b_mps0_regs[] = {
|
||||
{ "RXTpParErr", 4, 2 },
|
||||
{ "TX1TpParErr", 2, 2 },
|
||||
{ "TX0TpParErr", 0, 2 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3b_cpl_switch_regs[] = {
|
||||
@ -1686,7 +1686,7 @@ struct reg_info t3b_cpl_switch_regs[] = {
|
||||
{ "cpl_map_tbl_idx", 0, 8 },
|
||||
{ "CPL_MAP_TBL_DATA", 0x65c, 0 },
|
||||
{ "cpl_map_tbl_data", 0, 8 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3b_smb0_regs[] = {
|
||||
@ -1752,7 +1752,7 @@ struct reg_info t3b_smb0_regs[] = {
|
||||
{ "DebugDataL", 0, 16 },
|
||||
{ "SMB_DEBUG_LA", 0x69c, 0 },
|
||||
{ "DebugLAReqAddr", 0, 10 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3b_i2cm0_regs[] = {
|
||||
@ -1765,7 +1765,7 @@ struct reg_info t3b_i2cm0_regs[] = {
|
||||
{ "Ack", 30, 1 },
|
||||
{ "Cont", 1, 1 },
|
||||
{ "Op", 0, 1 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3b_mi1_regs[] = {
|
||||
@ -1784,7 +1784,7 @@ struct reg_info t3b_mi1_regs[] = {
|
||||
{ "Busy", 31, 1 },
|
||||
{ "Inc", 2, 1 },
|
||||
{ "Op", 0, 2 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3b_jm1_regs[] = {
|
||||
@ -1797,7 +1797,7 @@ struct reg_info t3b_jm1_regs[] = {
|
||||
{ "JM_OP", 0x6cc, 0 },
|
||||
{ "Busy", 31, 1 },
|
||||
{ "Cnt", 0, 5 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3b_sf1_regs[] = {
|
||||
@ -1807,7 +1807,7 @@ struct reg_info t3b_sf1_regs[] = {
|
||||
{ "Cont", 3, 1 },
|
||||
{ "ByteCnt", 1, 2 },
|
||||
{ "Op", 0, 1 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3b_pl3_regs[] = {
|
||||
@ -1917,7 +1917,7 @@ struct reg_info t3b_pl3_regs[] = {
|
||||
{ "PL_CLI", 0x6f8, 0 },
|
||||
{ "PL_LCK", 0x6fc, 0 },
|
||||
{ "Lck", 0, 2 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3b_mc5a_regs[] = {
|
||||
@ -2100,7 +2100,7 @@ struct reg_info t3b_mc5a_regs[] = {
|
||||
{ "ReadCmd", 0, 20 },
|
||||
{ "MC5_DB_MASK_WRITE_CMD", 0x7fc, 0 },
|
||||
{ "MaskWr", 0, 16 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3b_xgmac0_0_regs[] = {
|
||||
@ -2464,7 +2464,7 @@ struct reg_info t3b_xgmac0_0_regs[] = {
|
||||
{ "XGM_RX_SPI4_SOP_EOP_CNT", 0x9ac, 0 },
|
||||
{ "RxSPI4SopCnt", 16, 16 },
|
||||
{ "RxSPI4EopCnt", 0, 16 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3b_xgmac0_1_regs[] = {
|
||||
@ -2828,5 +2828,5 @@ struct reg_info t3b_xgmac0_1_regs[] = {
|
||||
{ "XGM_RX_SPI4_SOP_EOP_CNT", 0xbac, 0 },
|
||||
{ "RxSPI4SopCnt", 16, 16 },
|
||||
{ "RxSPI4EopCnt", 0, 16 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
@ -177,7 +177,7 @@ struct reg_info t3c_sge3_regs[] = {
|
||||
{ "DrbPriThrsh", 0, 16 },
|
||||
{ "SG_DEBUG_INDEX", 0x78, 0 },
|
||||
{ "SG_DEBUG_DATA", 0x7c, 0 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3c_pcix1_regs[] = {
|
||||
@ -282,7 +282,7 @@ struct reg_info t3c_pcix1_regs[] = {
|
||||
{ "IntSt", 4, 3 },
|
||||
{ "PIOSt", 2, 2 },
|
||||
{ "RFReqRdSt", 0, 2 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3c_pcie0_regs[] = {
|
||||
@ -475,7 +475,7 @@ struct reg_info t3c_pcie0_regs[] = {
|
||||
{ "P_WMark", 18, 11 },
|
||||
{ "NP_WMark", 11, 7 },
|
||||
{ "CPL_WMark", 0, 11 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3c_t3dbg_regs[] = {
|
||||
@ -656,7 +656,7 @@ struct reg_info t3c_t3dbg_regs[] = {
|
||||
{ "BSEnLane1", 4, 1 },
|
||||
{ "BSInSelLane0", 1, 2 },
|
||||
{ "BSEnLane0", 0, 1 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3c_mc7_pmrx_regs[] = {
|
||||
@ -777,7 +777,7 @@ struct reg_info t3c_mc7_pmrx_regs[] = {
|
||||
{ "PE", 2, 15 },
|
||||
{ "UE", 1, 1 },
|
||||
{ "CE", 0, 1 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3c_mc7_pmtx_regs[] = {
|
||||
@ -898,7 +898,7 @@ struct reg_info t3c_mc7_pmtx_regs[] = {
|
||||
{ "PE", 2, 15 },
|
||||
{ "UE", 1, 1 },
|
||||
{ "CE", 0, 1 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3c_mc7_cm_regs[] = {
|
||||
@ -1019,7 +1019,7 @@ struct reg_info t3c_mc7_cm_regs[] = {
|
||||
{ "PE", 2, 15 },
|
||||
{ "UE", 1, 1 },
|
||||
{ "CE", 0, 1 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3c_cim_regs[] = {
|
||||
@ -1194,7 +1194,7 @@ struct reg_info t3c_cim_regs[] = {
|
||||
{ "PILADbgWrPtr", 0, 9 },
|
||||
{ "CIM_PO_LA_DEBUGDATA", 0x2e8, 0 },
|
||||
{ "CIM_PI_LA_DEBUGDATA", 0x2ec, 0 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3c_tp1_regs[] = {
|
||||
@ -1667,7 +1667,7 @@ struct reg_info t3c_tp1_regs[] = {
|
||||
{ "TP_EMBED_OP_FIELD3", 0x4f4, 0 },
|
||||
{ "TP_EMBED_OP_FIELD4", 0x4f8, 0 },
|
||||
{ "TP_EMBED_OP_FIELD5", 0x4fc, 0 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3c_ulp2_rx_regs[] = {
|
||||
@ -1725,7 +1725,7 @@ struct reg_info t3c_ulp2_rx_regs[] = {
|
||||
{ "ULPRX_RQ_ULIMIT", 0x538, 0 },
|
||||
{ "ULPRX_PBL_LLIMIT", 0x53c, 0 },
|
||||
{ "ULPRX_PBL_ULIMIT", 0x540, 0 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3c_ulp2_tx_regs[] = {
|
||||
@ -1766,7 +1766,7 @@ struct reg_info t3c_ulp2_tx_regs[] = {
|
||||
{ "ULPTX_DMA_WEIGHT", 0x5ac, 0 },
|
||||
{ "D1_WEIGHT", 16, 16 },
|
||||
{ "D0_WEIGHT", 0, 16 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3c_pm1_rx_regs[] = {
|
||||
@ -1810,7 +1810,7 @@ struct reg_info t3c_pm1_rx_regs[] = {
|
||||
{ "ocspi1_ofifo2x_Tx_framing_error", 6, 1 },
|
||||
{ "iespi_par_error", 3, 3 },
|
||||
{ "ocspi_par_error", 0, 3 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3c_pm1_tx_regs[] = {
|
||||
@ -1854,7 +1854,7 @@ struct reg_info t3c_pm1_tx_regs[] = {
|
||||
{ "oespi1_ofifo2x_Tx_framing_error", 6, 1 },
|
||||
{ "icspi_par_error", 3, 3 },
|
||||
{ "oespi_par_error", 0, 3 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3c_mps0_regs[] = {
|
||||
@ -1896,7 +1896,7 @@ struct reg_info t3c_mps0_regs[] = {
|
||||
{ "RXTpParErr", 4, 2 },
|
||||
{ "TX1TpParErr", 2, 2 },
|
||||
{ "TX0TpParErr", 0, 2 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3c_cpl_switch_regs[] = {
|
||||
@ -1930,7 +1930,7 @@ struct reg_info t3c_cpl_switch_regs[] = {
|
||||
{ "cpl_map_tbl_idx", 0, 8 },
|
||||
{ "CPL_MAP_TBL_DATA", 0x65c, 0 },
|
||||
{ "cpl_map_tbl_data", 0, 8 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3c_smb0_regs[] = {
|
||||
@ -1996,7 +1996,7 @@ struct reg_info t3c_smb0_regs[] = {
|
||||
{ "DebugDataL", 0, 16 },
|
||||
{ "SMB_DEBUG_LA", 0x69c, 0 },
|
||||
{ "DebugLAReqAddr", 0, 10 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3c_i2cm0_regs[] = {
|
||||
@ -2009,7 +2009,7 @@ struct reg_info t3c_i2cm0_regs[] = {
|
||||
{ "Ack", 30, 1 },
|
||||
{ "Cont", 1, 1 },
|
||||
{ "Op", 0, 1 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3c_mi1_regs[] = {
|
||||
@ -2028,7 +2028,7 @@ struct reg_info t3c_mi1_regs[] = {
|
||||
{ "Busy", 31, 1 },
|
||||
{ "Inc", 2, 1 },
|
||||
{ "Op", 0, 2 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3c_jm1_regs[] = {
|
||||
@ -2041,7 +2041,7 @@ struct reg_info t3c_jm1_regs[] = {
|
||||
{ "JM_OP", 0x6cc, 0 },
|
||||
{ "Busy", 31, 1 },
|
||||
{ "Cnt", 0, 5 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3c_sf1_regs[] = {
|
||||
@ -2051,7 +2051,7 @@ struct reg_info t3c_sf1_regs[] = {
|
||||
{ "Cont", 3, 1 },
|
||||
{ "ByteCnt", 1, 2 },
|
||||
{ "Op", 0, 1 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3c_pl3_regs[] = {
|
||||
@ -2162,7 +2162,7 @@ struct reg_info t3c_pl3_regs[] = {
|
||||
{ "PL_CLI", 0x6f8, 0 },
|
||||
{ "PL_LCK", 0x6fc, 0 },
|
||||
{ "Lck", 0, 2 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3c_mc5a_regs[] = {
|
||||
@ -2346,7 +2346,7 @@ struct reg_info t3c_mc5a_regs[] = {
|
||||
{ "ReadCmd", 0, 20 },
|
||||
{ "MC5_DB_MASK_WRITE_CMD", 0x7fc, 0 },
|
||||
{ "MaskWr", 0, 16 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3c_xgmac0_0_regs[] = {
|
||||
@ -2730,7 +2730,7 @@ struct reg_info t3c_xgmac0_0_regs[] = {
|
||||
{ "XGM_RX_SPI4_SOP_EOP_CNT", 0x9ac, 0 },
|
||||
{ "RxSPI4SopCnt", 16, 16 },
|
||||
{ "RxSPI4EopCnt", 0, 16 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t3c_xgmac0_1_regs[] = {
|
||||
@ -3114,6 +3114,6 @@ struct reg_info t3c_xgmac0_1_regs[] = {
|
||||
{ "XGM_RX_SPI4_SOP_EOP_CNT", 0xbac, 0 },
|
||||
{ "RxSPI4SopCnt", 16, 16 },
|
||||
{ "RxSPI4EopCnt", 0, 16 },
|
||||
{ NULL }
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user