Add clocks for ethernet controllers on RK3328
Reviewed by: manu Differential Revision: https://reviews.freebsd.org/D25918
This commit is contained in:
Oleksandr Tymoshenko
parent
ff06230e67
commit
5414a8285f
@ -49,10 +49,31 @@ __FBSDID("$FreeBSD$");
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#include <arm64/rockchip/clk/rk_cru.h>
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/* Registers */
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#define RK3328_GRF_SOC_CON4 0x410
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#define RK3328_GRF_MAC_CON1 0x904
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#define RK3328_GRF_MAC_CON2 0x908
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/* GATES */
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#define SCLK_MAC2PHY_RXTX 83
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#define SCLK_MAC2PHY_SRC 84
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#define SCLK_MAC2PHY_REF 85
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#define SCLK_MAC2PHY_OUT 86
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#define SCLK_MAC2IO_RX 87
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#define SCLK_MAC2IO_TX 88
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#define SCLK_MAC2IO_REFOUT 89
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#define SCLK_MAC2IO_REF 90
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#define SCLK_MAC2IO_OUT 91
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#define SCLK_USB3OTG_REF 96
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#define SCLK_MAC2IO_SRC 99
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#define SCLK_MAC2IO 100
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#define SCLK_MAC2PHY 101
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#define SCLK_MAC2IO_EXT 102
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#define ACLK_USB3OTG 132
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#define ACLK_GMAC 146
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#define ACLK_MAC2PHY 149
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#define ACLK_MAC2IO 150
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#define ACLK_PERI 153
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#define PCLK_GPIO0 200
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#define PCLK_GPIO1 201
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@ -63,6 +84,9 @@ __FBSDID("$FreeBSD$");
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#define PCLK_I2C2 207
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#define PCLK_I2C3 208
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#define PCLK_TSADC 213
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#define PCLK_GMAC 220
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#define PCLK_MAC2PHY 222
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#define PCLK_MAC2IO 223
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#define PCLK_USB3PHY_OTG 224
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#define PCLK_USB3PHY_PIPE 225
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#define PCLK_USB3_GRF 226
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@ -87,6 +111,14 @@ static struct rk_cru_gate rk3328_gates[] = {
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CRU_GATE(0, "pclk_bus", "pclk_bus_pre", 0x220, 3)
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CRU_GATE(0, "pclk_phy_pre", "pclk_bus_pre", 0x220, 4)
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/* CRU_CLKGATE_CON8 */
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CRU_GATE(SCLK_MAC2IO_REF, "clk_mac2io_ref", "clk_mac2io", 0x224, 7)
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CRU_GATE(SCLK_MAC2IO_REFOUT, "clk_mac2io_refout", "clk_mac2io", 0x224, 6)
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CRU_GATE(SCLK_MAC2IO_TX, "clk_mac2io_tx", "clk_mac2io", 0x224, 5)
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CRU_GATE(SCLK_MAC2IO_RX, "clk_mac2io_rx", "clk_mac2io", 0x224, 4)
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CRU_GATE(SCLK_MAC2PHY_REF, "clk_mac2phy_ref", "clk_mac2phy", 0x224, 3)
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CRU_GATE(SCLK_MAC2PHY_RXTX, "clk_mac2phy_rxtx", "clk_mac2phy", 0x224, 1)
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/* CRU_CLKGATE_CON10 */
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CRU_GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", 0x228, 0)
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@ -116,6 +148,12 @@ static struct rk_cru_gate rk3328_gates[] = {
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CRU_GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0x24C, 14)
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CRU_GATE(HCLK_SDMMC_EXT, "hclk_sdmmc_ext", "hclk_peri", 0x24C, 15)
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/* CRU_CLKGATE_CON26 */
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CRU_GATE(ACLK_MAC2PHY, "aclk_mac2phy", "aclk_gmac", 0x268, 0)
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CRU_GATE(PCLK_MAC2PHY, "pclk_mac2phy", "pclk_gmac", 0x268, 1)
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CRU_GATE(ACLK_MAC2IO, "aclk_mac2io", "aclk_gmac", 0x268, 2)
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CRU_GATE(PCLK_MAC2IO, "pclk_mac2io", "pclk_gmac", 0x268, 3)
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/* CRU_CLKGATE_CON28 */
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CRU_GATE(PCLK_USB3PHY_OTG, "pclk_usb3phy_otg", "pclk_phy_pre", 0x270, 1)
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CRU_GATE(PCLK_USB3PHY_PIPE, "pclk_usb3phy_pipe", "pclk_phy_pre", 0x270, 2)
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@ -1077,6 +1115,210 @@ static struct rk_clk_composite_def ref_usb3otg_src = {
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.flags = RK_CLK_COMPOSITE_HAVE_GATE,
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};
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static const char *mac2io_src_parents[] = { "cpll", "gpll" };
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static struct rk_clk_composite_def mac2io_src = {
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.clkdef = {
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.id = SCLK_MAC2IO_SRC,
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.name = "clk_mac2io_src",
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.parent_names = mac2io_src_parents,
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.parent_cnt = nitems(mac2io_src_parents),
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},
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/* CRU_CLKSEL_CON27 */
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.muxdiv_offset = 0x16c,
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.mux_shift = 7,
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.mux_width = 1,
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.div_shift = 0,
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.div_width = 5,
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/* CRU_CLKGATE_CON3 */
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.gate_offset = 0x20c,
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.gate_shift = 1,
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.flags = RK_CLK_COMPOSITE_HAVE_GATE | RK_CLK_COMPOSITE_HAVE_MUX,
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};
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static const char *mac2io_out_parents[] = { "cpll", "gpll" };
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static struct rk_clk_composite_def mac2io_out = {
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.clkdef = {
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.id = SCLK_MAC2IO_OUT,
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.name = "clk_mac2io_out",
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.parent_names = mac2io_out_parents,
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.parent_cnt = nitems(mac2io_out_parents),
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},
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/* CRU_CLKSEL_CON27 */
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.muxdiv_offset = 0x16c,
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.mux_shift = 15,
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.mux_width = 1,
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.div_shift = 8,
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.div_width = 5,
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/* CRU_CLKGATE_CON3 */
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.gate_offset = 0x20c,
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.gate_shift = 5,
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.flags = RK_CLK_COMPOSITE_HAVE_GATE | RK_CLK_COMPOSITE_HAVE_MUX,
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};
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static const char *mac2io_parents[] = { "clk_mac2io_src", "gmac_clkin" };
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static struct rk_clk_composite_def mac2io = {
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.clkdef = {
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.id = SCLK_MAC2IO,
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.name = "clk_mac2io",
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.parent_names = mac2io_parents,
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.parent_cnt = nitems(mac2io_parents),
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},
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.muxdiv_offset = RK3328_GRF_MAC_CON1,
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.mux_shift = 10,
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.mux_width = 1,
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.flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_GRF
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};
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static const char *mac2io_ext_parents[] = { "clk_mac2io", "gmac_clkin" };
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static struct rk_clk_composite_def mac2io_ext = {
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.clkdef = {
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.id = SCLK_MAC2IO_EXT,
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.name = "clk_mac2io_ext",
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.parent_names = mac2io_ext_parents,
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.parent_cnt = nitems(mac2io_ext_parents),
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},
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.muxdiv_offset = RK3328_GRF_SOC_CON4,
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.mux_shift = 14,
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.mux_width = 1,
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.flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_GRF
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};
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static const char *mac2phy_src_parents[] = { "cpll", "gpll" };
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static struct rk_clk_composite_def mac2phy_src = {
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.clkdef = {
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.id = SCLK_MAC2PHY_SRC,
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.name = "clk_mac2phy_src",
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.parent_names = mac2phy_src_parents,
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.parent_cnt = nitems(mac2phy_src_parents),
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},
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/* CRU_CLKSEL_CON26 */
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.muxdiv_offset = 0x168,
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.mux_shift = 7,
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.mux_width = 1,
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.div_shift = 0,
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.div_width = 5,
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/* CRU_CLKGATE_CON3 */
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.gate_offset = 0x20c,
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.gate_shift = 0,
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.flags = RK_CLK_COMPOSITE_HAVE_GATE | RK_CLK_COMPOSITE_HAVE_MUX,
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};
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static const char *mac2phy_parents[] = { "clk_mac2phy_src", "phy_50m_out" };
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static struct rk_clk_composite_def mac2phy = {
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.clkdef = {
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.id = SCLK_MAC2PHY,
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.name = "clk_mac2phy",
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.parent_names = mac2phy_parents,
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.parent_cnt = nitems(mac2phy_parents),
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},
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.muxdiv_offset = RK3328_GRF_MAC_CON2,
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.mux_shift = 10,
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.mux_width = 1,
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.flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_GRF
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};
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static const char *mac2phy_out_parents[] = { "clk_mac2phy" };
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static struct rk_clk_composite_def mac2phy_out = {
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.clkdef = {
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.id = SCLK_MAC2PHY_OUT,
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.name = "clk_mac2phy_out",
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.parent_names = mac2phy_out_parents,
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.parent_cnt = nitems(mac2phy_out_parents),
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},
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/* CRU_CLKSEL_CON26 */
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.muxdiv_offset = 0x168,
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.div_shift = 8,
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.div_width = 2,
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/* CRU_CLKGATE_CON9 */
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.gate_offset = 0x224,
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.gate_shift = 2,
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.flags = RK_CLK_COMPOSITE_HAVE_GATE
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};
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static struct clk_fixed_def phy_50m_out = {
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.clkdef.name = "phy_50m_out",
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.freq = 50000000,
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};
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static struct clk_link_def gmac_clkin = {
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.clkdef.name = "gmac_clkin",
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};
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static const char *aclk_gmac_parents[] = { "cpll", "gpll" };
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static struct rk_clk_composite_def aclk_gmac = {
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.clkdef = {
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.id = ACLK_GMAC,
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.name = "aclk_gmac",
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.parent_names = aclk_gmac_parents,
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.parent_cnt = nitems(aclk_gmac_parents),
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},
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/* CRU_CLKSEL_CON35 */
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.muxdiv_offset = 0x18c,
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.mux_shift = 6,
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.mux_width = 2,
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.div_shift = 0,
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.div_width = 5,
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/* CRU_CLKGATE_CON3 */
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.gate_offset = 0x20c,
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.gate_shift = 2,
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.flags = RK_CLK_COMPOSITE_HAVE_GATE | RK_CLK_COMPOSITE_HAVE_MUX,
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};
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static const char *pclk_gmac_parents[] = { "aclk_gmac" };
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static struct rk_clk_composite_def pclk_gmac = {
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.clkdef = {
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.id = PCLK_GMAC,
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.name = "pclk_gmac",
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.parent_names = pclk_gmac_parents,
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.parent_cnt = nitems(pclk_gmac_parents),
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},
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/* CRU_CLKSEL_CON25 */
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.muxdiv_offset = 0x164,
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.div_shift = 8,
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.div_width = 3,
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/* CRU_CLKGATE_CON9 */
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.gate_offset = 0x224,
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.gate_shift = 0,
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.flags = RK_CLK_COMPOSITE_HAVE_GATE
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};
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static struct rk_clk rk3328_clks[] = {
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{
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.type = RK3328_CLK_PLL,
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@ -1175,6 +1417,50 @@ static struct rk_clk rk3328_clks[] = {
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.type = RK_CLK_COMPOSITE,
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.clk.composite = &usb3otg_suspend
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},
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{
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.type = RK_CLK_COMPOSITE,
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.clk.composite = &mac2io_src
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},
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{
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.type = RK_CLK_COMPOSITE,
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.clk.composite = &mac2io
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},
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{
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.type = RK_CLK_COMPOSITE,
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.clk.composite = &mac2io_out
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},
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{
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.type = RK_CLK_COMPOSITE,
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.clk.composite = &mac2io_ext
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},
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{
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.type = RK_CLK_COMPOSITE,
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.clk.composite = &mac2phy_src
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},
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{
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.type = RK_CLK_COMPOSITE,
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.clk.composite = &mac2phy
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},
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{
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.type = RK_CLK_COMPOSITE,
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.clk.composite = &mac2phy_out
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},
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{
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.type = RK_CLK_FIXED,
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.clk.fixed = &phy_50m_out
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},
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{
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.type = RK_CLK_LINK,
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.clk.link = &gmac_clkin
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},
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{
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.type = RK_CLK_COMPOSITE,
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.clk.composite = &aclk_gmac
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},
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{
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.type = RK_CLK_COMPOSITE,
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.clk.composite = &pclk_gmac
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},
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};
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static int
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