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Use the spitfire VIS block copy/zero functions also with cheetah-

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class CPUs. In theory one could also use versions additionally
taking advantage of the prefetch cache with cheetah-class CPUs,
in my worldstone runs these either didn't provide extra speedup
(USIII+) in comparison to the existing spitfire versions or were
even slightly slower (USIIIi) though, so they aren't committed
for now.
The basic problem leading to the VIS-based copy/zero functions
being initially disabled for cheetah-class CPUs was solved by
letting cheetah_init() clear DCR_IFPOE.
This commit is contained in:
marius 2008-11-16 19:30:17 +00:00
parent ed798111a5
commit 54885bc93a
1 changed files with 7 additions and 1 deletions
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8
sys/sparc64/sparc64/machdep.c
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@ -387,6 +387,12 @@ sparc64_init(caddr_t mdp, u_long o1, u_long o2, u_long o3, ofw_vec_t *vec)
case CPU_IMPL_ULTRASPARCII:
case CPU_IMPL_ULTRASPARCIIi:
case CPU_IMPL_ULTRASPARCIIe:
case CPU_IMPL_ULTRASPARCIII: /* NB: we've disabled P$. */
case CPU_IMPL_ULTRASPARCIIIp:
case CPU_IMPL_ULTRASPARCIIIi:
case CPU_IMPL_ULTRASPARCIV:
case CPU_IMPL_ULTRASPARCIVp:
case CPU_IMPL_ULTRASPARCIIIip:
cpu_block_copy = spitfire_block_copy;
cpu_block_zero = spitfire_block_zero;
break;
@ -772,7 +778,7 @@ sparc64_shutdown_final(void *dummy, int howto)
/* Turn the power off? */
if ((howto & RB_POWEROFF) != 0)
cpu_shutdown(&args);
/* In case of halt, return to the firmware */
/* In case of halt, return to the firmware. */
if ((howto & RB_HALT) != 0)
cpu_halt();
}