cxgbe(4) - NIC driver for Chelsio T4 (Terminator 4) based 10Gb/1Gb adapters.
MFC after: 3 weeks
This commit is contained in:
Navdeep Parhar
parent
6f068a4313
commit
54e4ee7163
@ -83,6 +83,7 @@ MAN= aac.4 \
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crypto.4 \
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cue.4 \
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cxgb.4 \
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cxgbe.4 \
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cy.4 \
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da.4 \
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dc.4 \
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@ -127,6 +127,7 @@ They have been applied to the following hardware drivers:
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.Xr bfe 4 ,
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.Xr bge 4 ,
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.Xr cas 4 ,
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.Xr cxgbe 4 ,
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.Xr dc 4 ,
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.Xr de 4 ,
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.Xr ed 4 ,
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167
share/man/man4/cxgbe.4
Normal file
167
share/man/man4/cxgbe.4
Normal file
@ -0,0 +1,167 @@
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.\" Copyright (c) 2011, Chelsio Inc
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.\" All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions are met:
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.\"
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.\" 1. Redistributions of source code must retain the above copyright notice,
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.\" this list of conditions and the following disclaimer.
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.\"
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" 3. Neither the name of the Chelsio Inc nor the names of its
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.\" contributors may be used to endorse or promote products derived from
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.\" this software without specific prior written permission.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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.\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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.\" LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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.\" POSSIBILITY OF SUCH DAMAGE.
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.\"
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.\" * Other names and brands may be claimed as the property of others.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd February 14, 2011
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.Dt CXGBE 4
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.Os
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.Sh NAME
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.Nm cxgbe
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.Nd "Chelsio T4 10Gb and 1Gb Ethernet adapter driver"
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.Sh SYNOPSIS
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To compile this driver into the kernel,
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place the following lines in your
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kernel configuration file:
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.Bd -ragged -offset indent
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.Cd "device cxgbe"
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.Ed
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.Pp
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To load the driver as a
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module at boot time, place the following line in
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.Xr loader.conf 5 :
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.Bd -literal -offset indent
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if_cxgbe_load="YES"
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.Ed
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.Sh DESCRIPTION
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The
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.Nm
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driver provides support for PCI Express Ethernet adapters based on
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the Chelsio Terminator 4 (T4) ASIC.
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The driver supprts Jumbo Frames, Transmit/Receive checksum offload,
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TCP segmentation offload (TSO), Large Receive Offload (LRO), VLAN
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tag insertion/extraction, VLAN checksum offload, VLAN TSO, and
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Receive Side Steering (RSS).
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For further hardware information and questions related to hardware
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requirements, see
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.Pa http://www.chelsio.com/ .
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.Pp
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For more information on configuring this device, see
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.Xr ifconfig 8 .
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.Sh HARDWARE
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The
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.Nm
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driver supports 10Gb and 1Gb Ethernet adapters based on the T4 ASIC:
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.Pp
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.Bl -bullet -compact
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.It
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Chelsio T420-CR
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.It
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Chelsio T422-CR
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.It
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Chelsio T440-CR
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.It
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Chelsio T420-BCH
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.It
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Chelsio T440-BCH
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.It
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Chelsio T440-CH
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.It
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Chelsio T420-SO
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.It
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Chelsio T420-CX
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.It
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Chelsio T420-BT
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.It
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Chelsio T404-BT
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.El
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.Sh LOADER TUNABLES
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Tunables can be set at the
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.Xr loader 8
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prompt before booting the kernel or stored in
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.Xr loader.conf 5 .
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.Bl -tag -width indent
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.It Va hw.cxgbe.max_ntxq_10G_port
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The maximum number of tx queues to use for a 10Gb port.
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The default value is 8.
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.It Va hw.cxgbe.max_nrxq_10G_port
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The maximum number of rx queues to use for a 10Gb port.
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The default value is 8.
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.It Va hw.cxgbe.max_ntxq_1G_port
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The maximum number of tx queues to use for a 1Gb port.
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The default value is 2.
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.It Va hw.cxgbe.max_nrxq_1G_port
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The maximum number of rx queues to use for a 1Gb port.
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The default value is 2.
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.It Va hw.cxgbe.holdoff_timer_idx_10G
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.It Va hw.cxgbe.holdoff_timer_idx_1G
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The timer index value to use to delay interrupts.
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The holdoff timer list has the values 1, 5, 10, 50, 100, and 200
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by default (all values are in microseconds) and the index selects a
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value from this list.
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The default value is 1 for both 10Gb and 1Gb ports, which means the
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timer value is 5us.
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.It Va hw.cxgbe.holdoff_pktc_idx_10G
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.It Va hw.cxgbe.holdoff_pktc_idx_1G
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The packet-count index value to use to delay interrupts.
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The packet-count list has the values 1, 8, 16, and 32 by default
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and the index selects a value from this list.
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The default value is 2 for both 10Gb and 1Gb ports, which means 16
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packets (or the holdoff timer going off) before an interrupt is
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generated.
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.It Va hw.cxgbe.qsize_txq
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The size, in number of entries, of the descriptor ring used for a tx
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queue.
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A buf_ring of the same size is also allocated for additional
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software queuing. See
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.Xr ifnet 9 .
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The default value is 1024.
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.It Va hw.cxgbe.qsize_rxq
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The size, in number of entries, of the descriptor ring used for an
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rx queue.
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The default value is 1024.
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.Sh SUPPORT
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For general information and support,
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go to the Chelsio support website at:
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.Pa http://www.chelsio.com/ .
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.Pp
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If an issue is identified with this driver with a supported adapter,
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email all the specific information related to the issue to
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.Aq support@chelsio.com .
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.Sh SEE ALSO
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.Xr altq 4 ,
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.Xr arp 4 ,
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.Xr cxgb 4 ,
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.Xr netintro 4 ,
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.Xr ng_ether 4 ,
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.Xr ifconfig 8
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.Sh HISTORY
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The
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.Nm
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device driver first appeared in
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.Fx 9.0
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.Sh AUTHORS
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.An -nosplit
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The
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.Nm
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driver was written by
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.An Navdeep Parhar Aq np@FreeBSD.org .
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@ -128,6 +128,7 @@ in the hardware is limited to the following devices:
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.Xr bce 4 ,
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.Xr bge 4 ,
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.Xr cxgb 4 ,
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.Xr cxgbe 4 ,
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.Xr em 4 ,
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.Xr igb 4 ,
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.Xr ixgb 4 ,
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@ -1902,6 +1902,8 @@ device xmphy # XaQti XMAC II
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# cas: Sun Cassini/Cassini+ and National Semiconductor DP83065 Saturn
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# cm: Arcnet SMC COM90c26 / SMC COM90c56
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# (and SMC COM90c66 in '56 compatibility mode) adapters.
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# cxgbe: Support for PCI express 10Gb/1Gb adapters based on the Chelsio T4
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# (Terminator 4) ASIC.
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# dc: Support for PCI fast ethernet adapters based on the DEC/Intel 21143
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# and various workalikes including:
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# the ADMtek AL981 Comet and AN985 Centaur, the ASIX Electronics
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@ -2073,6 +2075,7 @@ device wb # Winbond W89C840F
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device xl # 3Com 3c90x (``Boomerang'', ``Cyclone'')
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# PCI Ethernet NICs.
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device cxgbe # Chelsio T4 10GbE PCIe adapter
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device de # DEC/Intel DC21x4x (``Tulip'')
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device em # Intel Pro/1000 Gigabit Ethernet
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device igb # Intel Pro/1000 PCIE Gigabit Ethernet
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@ -853,6 +853,12 @@ dev/cxgb/sys/uipc_mvec.c optional cxgb pci \
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compile-with "${NORMAL_C} -I$S/dev/cxgb"
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dev/cxgb/cxgb_t3fw.c optional cxgb cxgb_t3fw \
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compile-with "${NORMAL_C} -I$S/dev/cxgb"
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dev/cxgbe/t4_main.c optional cxgbe pci \
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compile-with "${NORMAL_C} -I$S/dev/cxgbe"
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dev/cxgbe/t4_sge.c optional cxgbe pci \
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compile-with "${NORMAL_C} -I$S/dev/cxgbe"
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dev/cxgbe/common/t4_hw.c optional cxgbe pci \
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compile-with "${NORMAL_C} -I$S/dev/cxgbe"
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dev/cy/cy.c optional cy
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dev/cy/cy_isa.c optional cy isa
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dev/cy/cy_pci.c optional cy pci
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@ -82,8 +82,8 @@ INCLUDES+= -I$S/dev/twa
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# ... and XFS
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INCLUDES+= -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs
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# ... and the same for cxgb
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INCLUDES+= -I$S/dev/cxgb
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# ... and the same for cxgb and cxgbe
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INCLUDES+= -I$S/dev/cxgb -I$S/dev/cxgbe
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.endif
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569
sys/dev/cxgbe/adapter.h
Normal file
569
sys/dev/cxgbe/adapter.h
Normal file
@ -0,0 +1,569 @@
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/*-
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* Copyright (c) 2011 Chelsio Communications, Inc.
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* All rights reserved.
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* Written by: Navdeep Parhar <np@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef __T4_ADAPTER_H__
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#define __T4_ADAPTER_H__
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/types.h>
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#include <sys/malloc.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <machine/bus.h>
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#include <sys/socket.h>
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#include <sys/sysctl.h>
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#include <net/ethernet.h>
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#include <net/if.h>
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#include <net/if_media.h>
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#include <netinet/tcp_lro.h>
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#include "offload.h"
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#include "common/t4fw_interface.h"
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#define T4_FWNAME "t4fw"
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MALLOC_DECLARE(M_CXGBE);
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#define CXGBE_UNIMPLEMENTED(s) \
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panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__)
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#if defined(__i386__) || defined(__amd64__)
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static __inline void
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prefetch(void *x)
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{
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__asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
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}
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#else
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#define prefetch(x)
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#endif
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#ifdef __amd64__
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/* XXX: need systemwide bus_space_read_8/bus_space_write_8 */
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static __inline uint64_t
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t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
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bus_size_t offset)
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{
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KASSERT(tag == X86_BUS_SPACE_IO,
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("64-bit reads from I/O space not possible."));
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return (*(volatile uint64_t *)(handle + offset));
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}
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static __inline void
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t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh,
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bus_size_t offset, uint64_t value)
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{
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KASSERT(tag == X86_BUS_SPACE_IO,
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("64-bit writes to I/O space not possible."));
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*(volatile uint64_t *)(bsh + offset) = value;
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}
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#else
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static __inline uint64_t
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t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
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bus_size_t offset)
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{
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return (uint64_t)bus_space_read_4(tag, handle, offset) +
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((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32);
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}
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static __inline void
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t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh,
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bus_size_t offset, uint64_t value)
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{
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bus_space_write_4(tag, bsh, offset, value);
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bus_space_write_4(tag, bsh, offset + 4, value >> 32);
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}
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#endif
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struct adapter;
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typedef struct adapter adapter_t;
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enum {
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FW_IQ_QSIZE = 256,
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FW_IQ_ESIZE = 64, /* At least 64 mandated by the firmware spec */
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RX_IQ_QSIZE = 1024,
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RX_IQ_ESIZE = 64, /* At least 64 so CPL_RX_PKT will fit */
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RX_FL_ESIZE = 64, /* 8 64bit addresses */
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FL_BUF_SIZES = 4,
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TX_EQ_QSIZE = 1024,
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TX_EQ_ESIZE = 64,
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TX_SGL_SEGS = 36,
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TX_WR_FLITS = SGE_MAX_WR_LEN / 8
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};
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enum {
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/* adapter flags */
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FULL_INIT_DONE = (1 << 0),
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FW_OK = (1 << 1),
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INTR_FWD = (1 << 2),
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CXGBE_BUSY = (1 << 9),
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/* port flags */
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DOOMED = (1 << 0),
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VI_ENABLED = (1 << 1),
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};
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#define IS_DOOMED(pi) (pi->flags & DOOMED)
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#define SET_DOOMED(pi) do {pi->flags |= DOOMED;} while (0)
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#define IS_BUSY(sc) (sc->flags & CXGBE_BUSY)
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#define SET_BUSY(sc) do {sc->flags |= CXGBE_BUSY;} while (0)
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#define CLR_BUSY(sc) do {sc->flags &= ~CXGBE_BUSY;} while (0)
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struct port_info {
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device_t dev;
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struct adapter *adapter;
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struct ifnet *ifp;
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struct ifmedia media;
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struct mtx pi_lock;
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char lockname[16];
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unsigned long flags;
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int if_flags;
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uint16_t viid;
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int16_t xact_addr_filt;/* index of exact MAC address filter */
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uint16_t rss_size; /* size of VI's RSS table slice */
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uint8_t lport; /* associated offload logical port */
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int8_t mdio_addr;
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uint8_t port_type;
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uint8_t mod_type;
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uint8_t port_id;
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uint8_t tx_chan;
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/* These need to be int as they are used in sysctl */
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int ntxq; /* # of tx queues */
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int first_txq; /* index of first tx queue */
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int nrxq; /* # of rx queues */
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int first_rxq; /* index of first rx queue */
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int tmr_idx;
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int pktc_idx;
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int qsize_rxq;
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int qsize_txq;
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struct link_config link_cfg;
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struct port_stats stats;
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struct callout tick;
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struct sysctl_ctx_list ctx; /* lives from ifconfig up to down */
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struct sysctl_oid *oid_rxq;
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struct sysctl_oid *oid_txq;
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uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */
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};
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struct fl_sdesc {
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struct mbuf *m;
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bus_dmamap_t map;
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caddr_t cl;
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uint8_t tag_idx; /* the sc->fl_tag this map comes from */
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#ifdef INVARIANTS
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__be64 ba_tag;
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#endif
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};
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struct tx_desc {
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__be64 flit[8];
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};
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struct tx_map {
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struct mbuf *m;
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bus_dmamap_t map;
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};
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struct tx_sdesc {
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uint8_t desc_used; /* # of hardware descriptors used by the WR */
|
||||
uint8_t map_used; /* # of frames sent out in the WR */
|
||||
};
|
||||
|
||||
typedef void (iq_intr_handler_t)(void *);
|
||||
|
||||
enum {
|
||||
/* iq flags */
|
||||
IQ_ALLOCATED = (1 << 1), /* firmware resources allocated */
|
||||
IQ_STARTED = (1 << 2), /* started */
|
||||
};
|
||||
|
||||
/*
|
||||
* Ingress Queue: T4 is producer, driver is consumer.
|
||||
*/
|
||||
struct sge_iq {
|
||||
bus_dma_tag_t desc_tag;
|
||||
bus_dmamap_t desc_map;
|
||||
struct mtx iq_lock;
|
||||
char lockname[16];
|
||||
unsigned int flags;
|
||||
struct adapter *adapter;
|
||||
|
||||
__be64 *desc; /* KVA of descriptor ring */
|
||||
bus_addr_t ba; /* bus address of descriptor ring */
|
||||
const __be64 *cdesc; /* current descriptor */
|
||||
uint8_t gen; /* generation bit */
|
||||
uint8_t intr_params; /* interrupt holdoff parameters */
|
||||
int8_t intr_pktc_idx; /* packet count threshold index */
|
||||
uint8_t intr_next; /* holdoff for next interrupt */
|
||||
uint8_t esize; /* size (bytes) of each entry in the queue */
|
||||
uint16_t qsize; /* size (# of entries) of the queue */
|
||||
uint16_t cidx; /* consumer index */
|
||||
uint16_t cntxt_id; /* SGE context id for the iq */
|
||||
uint16_t abs_id; /* absolute SGE id for the iq */
|
||||
iq_intr_handler_t *handler;
|
||||
};
|
||||
|
||||
enum {
|
||||
/* eq flags */
|
||||
EQ_ALLOCATED = (1 << 1), /* firmware resources allocated */
|
||||
EQ_STARTED = (1 << 2), /* started */
|
||||
EQ_STALLED = (1 << 3), /* currently stalled */
|
||||
};
|
||||
|
||||
/*
|
||||
* Egress Queue: driver is producer, T4 is consumer.
|
||||
*
|
||||
* Note: A free list is an egress queue (driver produces the buffers and T4
|
||||
* consumes them) but it's special enough to have its own struct (see sge_fl).
|
||||
*/
|
||||
struct sge_eq {
|
||||
bus_dma_tag_t tx_tag; /* tag for transmit buffers */
|
||||
bus_dma_tag_t desc_tag;
|
||||
bus_dmamap_t desc_map;
|
||||
char lockname[16];
|
||||
unsigned int flags;
|
||||
struct mtx eq_lock;
|
||||
|
||||
struct tx_desc *desc; /* KVA of descriptor ring */
|
||||
bus_addr_t ba; /* bus address of descriptor ring */
|
||||
struct tx_sdesc *sdesc; /* KVA of software descriptor ring */
|
||||
struct buf_ring *br; /* tx buffer ring */
|
||||
struct sge_qstat *spg; /* status page, for convenience */
|
||||
uint16_t cap; /* max # of desc, for convenience */
|
||||
uint16_t avail; /* available descriptors, for convenience */
|
||||
uint16_t qsize; /* size (# of entries) of the queue */
|
||||
uint16_t cidx; /* consumer idx (desc idx) */
|
||||
uint16_t pidx; /* producer idx (desc idx) */
|
||||
uint16_t pending; /* # of descriptors used since last doorbell */
|
||||
uint32_t cntxt_id; /* SGE context id for the eq */
|
||||
|
||||
/* DMA maps used for tx */
|
||||
struct tx_map *maps;
|
||||
uint32_t map_total; /* # of DMA maps */
|
||||
uint32_t map_pidx; /* next map to be used */
|
||||
uint32_t map_cidx; /* reclaimed up to this index */
|
||||
uint32_t map_avail; /* # of available maps */
|
||||
} __aligned(CACHE_LINE_SIZE);
|
||||
|
||||
struct sge_fl {
|
||||
bus_dma_tag_t desc_tag;
|
||||
bus_dmamap_t desc_map;
|
||||
bus_dma_tag_t tag[FL_BUF_SIZES];
|
||||
uint8_t tag_idx;
|
||||
struct mtx fl_lock;
|
||||
char lockname[16];
|
||||
|
||||
__be64 *desc; /* KVA of descriptor ring, ptr to addresses */
|
||||
bus_addr_t ba; /* bus address of descriptor ring */
|
||||
struct fl_sdesc *sdesc; /* KVA of software descriptor ring */
|
||||
uint32_t cap; /* max # of buffers, for convenience */
|
||||
uint16_t qsize; /* size (# of entries) of the queue */
|
||||
uint16_t cntxt_id; /* SGE context id for the freelist */
|
||||
uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */
|
||||
uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */
|
||||
uint32_t needed; /* # of buffers needed to fill up fl. */
|
||||
uint32_t pending; /* # of bufs allocated since last doorbell */
|
||||
unsigned int dmamap_failed;
|
||||
};
|
||||
|
||||
/* txq: SGE egress queue + miscellaneous items */
|
||||
struct sge_txq {
|
||||
struct sge_eq eq; /* MUST be first */
|
||||
struct mbuf *m; /* held up due to temporary resource shortage */
|
||||
|
||||
/* stats for common events first */
|
||||
|
||||
uint64_t txcsum; /* # of times hardware assisted with checksum */
|
||||
uint64_t tso_wrs; /* # of IPv4 TSO work requests */
|
||||
uint64_t vlan_insertion;/* # of times VLAN tag was inserted */
|
||||
uint64_t imm_wrs; /* # of work requests with immediate data */
|
||||
uint64_t sgl_wrs; /* # of work requests with direct SGL */
|
||||
uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */
|
||||
uint64_t txpkts_wrs; /* # of coalesced tx work requests */
|
||||
uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */
|
||||
|
||||
/* stats for not-that-common events */
|
||||
|
||||
uint32_t no_dmamap; /* no DMA map to load the mbuf */
|
||||
uint32_t no_desc; /* out of hardware descriptors */
|
||||
uint32_t egr_update; /* # of SGE_EGR_UPDATE notifications for txq */
|
||||
};
|
||||
|
||||
enum {
|
||||
RXQ_LRO_ENABLED = (1 << 0)
|
||||
};
|
||||
/* rxq: SGE ingress queue + SGE free list + miscellaneous items */
|
||||
struct sge_rxq {
|
||||
struct sge_iq iq; /* MUST be first */
|
||||
struct sge_fl fl;
|
||||
|
||||
unsigned int flags;
|
||||
struct port_info *port; /* the port this rxq belongs to */
|
||||
struct lro_ctrl lro; /* LRO state */
|
||||
|
||||
/* stats for common events first */
|
||||
|
||||
uint64_t rxcsum; /* # of times hardware assisted with checksum */
|
||||
uint64_t vlan_extraction;/* # of times VLAN tag was extracted */
|
||||
|
||||
/* stats for not-that-common events */
|
||||
|
||||
} __aligned(CACHE_LINE_SIZE);
|
||||
|
||||
struct sge {
|
||||
uint16_t timer_val[SGE_NTIMERS];
|
||||
uint8_t counter_val[SGE_NCOUNTERS];
|
||||
|
||||
int nrxq; /* total rx queues (all ports and the rest) */
|
||||
int ntxq; /* total tx queues (all ports and the rest) */
|
||||
int niq; /* total ingress queues */
|
||||
int neq; /* total egress queues */
|
||||
|
||||
struct sge_iq fwq; /* Firmware event queue */
|
||||
struct sge_iq *fiq; /* Forwarded interrupt queues (INTR_FWD) */
|
||||
struct sge_txq *txq; /* NIC tx queues */
|
||||
struct sge_rxq *rxq; /* NIC rx queues */
|
||||
|
||||
uint16_t iq_start;
|
||||
int eq_start;
|
||||
struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */
|
||||
struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */
|
||||
};
|
||||
|
||||
struct adapter {
|
||||
device_t dev;
|
||||
struct cdev *cdev;
|
||||
|
||||
/* PCIe register resources */
|
||||
int regs_rid;
|
||||
struct resource *regs_res;
|
||||
int msix_rid;
|
||||
struct resource *msix_res;
|
||||
bus_space_handle_t bh;
|
||||
bus_space_tag_t bt;
|
||||
bus_size_t mmio_len;
|
||||
|
||||
unsigned int pf;
|
||||
unsigned int mbox;
|
||||
|
||||
/* Interrupt information */
|
||||
int intr_type;
|
||||
int intr_count;
|
||||
struct irq {
|
||||
struct resource *res;
|
||||
int rid;
|
||||
void *tag;
|
||||
} *irq;
|
||||
|
||||
bus_dma_tag_t dmat; /* Parent DMA tag */
|
||||
|
||||
struct sge sge;
|
||||
|
||||
struct port_info *port[MAX_NPORTS];
|
||||
uint8_t chan_map[NCHAN];
|
||||
|
||||
struct tid_info tids;
|
||||
|
||||
int registered_device_map;
|
||||
int open_device_map;
|
||||
int flags;
|
||||
|
||||
char fw_version[32];
|
||||
struct adapter_params params;
|
||||
struct t4_virt_res vres;
|
||||
|
||||
struct mtx sc_lock;
|
||||
char lockname[16];
|
||||
};
|
||||
|
||||
#define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock)
|
||||
#define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock)
|
||||
#define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED)
|
||||
#define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED)
|
||||
|
||||
#define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock)
|
||||
#define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock)
|
||||
#define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED)
|
||||
#define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED)
|
||||
|
||||
#define IQ_LOCK(iq) mtx_lock(&(iq)->iq_lock)
|
||||
#define IQ_UNLOCK(iq) mtx_unlock(&(iq)->iq_lock)
|
||||
#define IQ_LOCK_ASSERT_OWNED(iq) mtx_assert(&(iq)->iq_lock, MA_OWNED)
|
||||
#define IQ_LOCK_ASSERT_NOTOWNED(iq) mtx_assert(&(iq)->iq_lock, MA_NOTOWNED)
|
||||
|
||||
#define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock)
|
||||
#define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock)
|
||||
#define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock)
|
||||
#define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED)
|
||||
#define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED)
|
||||
|
||||
#define RXQ_LOCK(rxq) IQ_LOCK(&(rxq)->iq)
|
||||
#define RXQ_UNLOCK(rxq) IQ_UNLOCK(&(rxq)->iq)
|
||||
#define RXQ_LOCK_ASSERT_OWNED(rxq) IQ_LOCK_ASSERT_OWNED(&(rxq)->iq)
|
||||
#define RXQ_LOCK_ASSERT_NOTOWNED(rxq) IQ_LOCK_ASSERT_NOTOWNED(&(rxq)->iq)
|
||||
|
||||
#define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl)
|
||||
#define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl)
|
||||
#define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
|
||||
#define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
|
||||
|
||||
#define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock)
|
||||
#define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock)
|
||||
#define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock)
|
||||
#define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED)
|
||||
#define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED)
|
||||
|
||||
#define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq)
|
||||
#define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq)
|
||||
#define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq)
|
||||
#define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
|
||||
#define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
|
||||
|
||||
#define for_each_txq(pi, iter, txq) \
|
||||
txq = &pi->adapter->sge.txq[pi->first_txq]; \
|
||||
for (iter = 0; iter < pi->ntxq; ++iter, ++txq)
|
||||
#define for_each_rxq(pi, iter, rxq) \
|
||||
rxq = &pi->adapter->sge.rxq[pi->first_rxq]; \
|
||||
for (iter = 0; iter < pi->nrxq; ++iter, ++rxq)
|
||||
|
||||
#define NFIQ(sc) ((sc)->intr_count > 1 ? (sc)->intr_count - 1 : 1)
|
||||
|
||||
static inline uint32_t
|
||||
t4_read_reg(struct adapter *sc, uint32_t reg)
|
||||
{
|
||||
return bus_space_read_4(sc->bt, sc->bh, reg);
|
||||
}
|
||||
|
||||
static inline void
|
||||
t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
|
||||
{
|
||||
bus_space_write_4(sc->bt, sc->bh, reg, val);
|
||||
}
|
||||
|
||||
static inline uint64_t
|
||||
t4_read_reg64(struct adapter *sc, uint32_t reg)
|
||||
{
|
||||
return t4_bus_space_read_8(sc->bt, sc->bh, reg);
|
||||
}
|
||||
|
||||
static inline void
|
||||
t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
|
||||
{
|
||||
t4_bus_space_write_8(sc->bt, sc->bh, reg, val);
|
||||
}
|
||||
|
||||
static inline void
|
||||
t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
|
||||
{
|
||||
*val = pci_read_config(sc->dev, reg, 1);
|
||||
}
|
||||
|
||||
static inline void
|
||||
t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
|
||||
{
|
||||
pci_write_config(sc->dev, reg, val, 1);
|
||||
}
|
||||
|
||||
static inline void
|
||||
t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
|
||||
{
|
||||
*val = pci_read_config(sc->dev, reg, 2);
|
||||
}
|
||||
|
||||
static inline void
|
||||
t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
|
||||
{
|
||||
pci_write_config(sc->dev, reg, val, 2);
|
||||
}
|
||||
|
||||
static inline void
|
||||
t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
|
||||
{
|
||||
*val = pci_read_config(sc->dev, reg, 4);
|
||||
}
|
||||
|
||||
static inline void
|
||||
t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
|
||||
{
|
||||
pci_write_config(sc->dev, reg, val, 4);
|
||||
}
|
||||
|
||||
static inline struct port_info *
|
||||
adap2pinfo(struct adapter *sc, int idx)
|
||||
{
|
||||
return (sc->port[idx]);
|
||||
}
|
||||
|
||||
static inline void
|
||||
t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[])
|
||||
{
|
||||
bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN);
|
||||
}
|
||||
|
||||
static inline bool is_10G_port(const struct port_info *pi)
|
||||
{
|
||||
return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0);
|
||||
}
|
||||
|
||||
int t4_os_find_pci_capability(struct adapter *, int);
|
||||
int t4_os_pci_save_state(struct adapter *);
|
||||
int t4_os_pci_restore_state(struct adapter *);
|
||||
|
||||
void t4_os_portmod_changed(const struct adapter *, int);
|
||||
void t4_os_link_changed(struct adapter *, int, int);
|
||||
|
||||
void t4_sge_init(struct adapter *);
|
||||
int t4_create_dma_tag(struct adapter *);
|
||||
int t4_destroy_dma_tag(struct adapter *);
|
||||
int t4_setup_adapter_iqs(struct adapter *);
|
||||
int t4_teardown_adapter_iqs(struct adapter *);
|
||||
int t4_setup_eth_queues(struct port_info *);
|
||||
int t4_teardown_eth_queues(struct port_info *);
|
||||
void t4_intr_all(void *);
|
||||
void t4_intr_fwd(void *);
|
||||
void t4_intr_err(void *);
|
||||
void t4_intr_evt(void *);
|
||||
void t4_intr_data(void *);
|
||||
int t4_eth_tx(struct ifnet *, struct sge_txq *, struct mbuf *);
|
||||
void t4_update_fl_bufsize(struct ifnet *);
|
||||
|
||||
#endif
|
||||
517
sys/dev/cxgbe/common/common.h
Normal file
517
sys/dev/cxgbe/common/common.h
Normal file
@ -0,0 +1,517 @@
|
||||
/*-
|
||||
* Copyright (c) 2011 Chelsio Communications, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __CHELSIO_COMMON_H
|
||||
#define __CHELSIO_COMMON_H
|
||||
|
||||
#include "t4_hw.h"
|
||||
|
||||
|
||||
enum {
|
||||
MAX_NPORTS = 4, /* max # of ports */
|
||||
SERNUM_LEN = 24, /* Serial # length */
|
||||
EC_LEN = 16, /* E/C length */
|
||||
ID_LEN = 16, /* ID length */
|
||||
};
|
||||
|
||||
enum { MEM_EDC0, MEM_EDC1, MEM_MC };
|
||||
|
||||
enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST };
|
||||
|
||||
enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR };
|
||||
|
||||
enum {
|
||||
PAUSE_RX = 1 << 0,
|
||||
PAUSE_TX = 1 << 1,
|
||||
PAUSE_AUTONEG = 1 << 2
|
||||
};
|
||||
|
||||
#define FW_VERSION_MAJOR 1
|
||||
#define FW_VERSION_MINOR 2
|
||||
#define FW_VERSION_MICRO 65
|
||||
|
||||
struct port_stats {
|
||||
u64 tx_octets; /* total # of octets in good frames */
|
||||
u64 tx_frames; /* all good frames */
|
||||
u64 tx_bcast_frames; /* all broadcast frames */
|
||||
u64 tx_mcast_frames; /* all multicast frames */
|
||||
u64 tx_ucast_frames; /* all unicast frames */
|
||||
u64 tx_error_frames; /* all error frames */
|
||||
|
||||
u64 tx_frames_64; /* # of Tx frames in a particular range */
|
||||
u64 tx_frames_65_127;
|
||||
u64 tx_frames_128_255;
|
||||
u64 tx_frames_256_511;
|
||||
u64 tx_frames_512_1023;
|
||||
u64 tx_frames_1024_1518;
|
||||
u64 tx_frames_1519_max;
|
||||
|
||||
u64 tx_drop; /* # of dropped Tx frames */
|
||||
u64 tx_pause; /* # of transmitted pause frames */
|
||||
u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
|
||||
u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
|
||||
u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
|
||||
u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
|
||||
u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
|
||||
u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
|
||||
u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
|
||||
u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
|
||||
|
||||
u64 rx_octets; /* total # of octets in good frames */
|
||||
u64 rx_frames; /* all good frames */
|
||||
u64 rx_bcast_frames; /* all broadcast frames */
|
||||
u64 rx_mcast_frames; /* all multicast frames */
|
||||
u64 rx_ucast_frames; /* all unicast frames */
|
||||
u64 rx_too_long; /* # of frames exceeding MTU */
|
||||
u64 rx_jabber; /* # of jabber frames */
|
||||
u64 rx_fcs_err; /* # of received frames with bad FCS */
|
||||
u64 rx_len_err; /* # of received frames with length error */
|
||||
u64 rx_symbol_err; /* symbol errors */
|
||||
u64 rx_runt; /* # of short frames */
|
||||
|
||||
u64 rx_frames_64; /* # of Rx frames in a particular range */
|
||||
u64 rx_frames_65_127;
|
||||
u64 rx_frames_128_255;
|
||||
u64 rx_frames_256_511;
|
||||
u64 rx_frames_512_1023;
|
||||
u64 rx_frames_1024_1518;
|
||||
u64 rx_frames_1519_max;
|
||||
|
||||
u64 rx_pause; /* # of received pause frames */
|
||||
u64 rx_ppp0; /* # of received PPP prio 0 frames */
|
||||
u64 rx_ppp1; /* # of received PPP prio 1 frames */
|
||||
u64 rx_ppp2; /* # of received PPP prio 2 frames */
|
||||
u64 rx_ppp3; /* # of received PPP prio 3 frames */
|
||||
u64 rx_ppp4; /* # of received PPP prio 4 frames */
|
||||
u64 rx_ppp5; /* # of received PPP prio 5 frames */
|
||||
u64 rx_ppp6; /* # of received PPP prio 6 frames */
|
||||
u64 rx_ppp7; /* # of received PPP prio 7 frames */
|
||||
|
||||
u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
|
||||
u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
|
||||
u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
|
||||
u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
|
||||
u64 rx_trunc0; /* buffer-group 0 truncated packets */
|
||||
u64 rx_trunc1; /* buffer-group 1 truncated packets */
|
||||
u64 rx_trunc2; /* buffer-group 2 truncated packets */
|
||||
u64 rx_trunc3; /* buffer-group 3 truncated packets */
|
||||
};
|
||||
|
||||
struct lb_port_stats {
|
||||
u64 octets;
|
||||
u64 frames;
|
||||
u64 bcast_frames;
|
||||
u64 mcast_frames;
|
||||
u64 ucast_frames;
|
||||
u64 error_frames;
|
||||
|
||||
u64 frames_64;
|
||||
u64 frames_65_127;
|
||||
u64 frames_128_255;
|
||||
u64 frames_256_511;
|
||||
u64 frames_512_1023;
|
||||
u64 frames_1024_1518;
|
||||
u64 frames_1519_max;
|
||||
|
||||
u64 drop;
|
||||
|
||||
u64 ovflow0;
|
||||
u64 ovflow1;
|
||||
u64 ovflow2;
|
||||
u64 ovflow3;
|
||||
u64 trunc0;
|
||||
u64 trunc1;
|
||||
u64 trunc2;
|
||||
u64 trunc3;
|
||||
};
|
||||
|
||||
struct tp_tcp_stats {
|
||||
u32 tcpOutRsts;
|
||||
u64 tcpInSegs;
|
||||
u64 tcpOutSegs;
|
||||
u64 tcpRetransSegs;
|
||||
};
|
||||
|
||||
struct tp_usm_stats {
|
||||
u32 frames;
|
||||
u32 drops;
|
||||
u64 octets;
|
||||
};
|
||||
|
||||
struct tp_fcoe_stats {
|
||||
u32 framesDDP;
|
||||
u32 framesDrop;
|
||||
u64 octetsDDP;
|
||||
};
|
||||
|
||||
struct tp_err_stats {
|
||||
u32 macInErrs[4];
|
||||
u32 hdrInErrs[4];
|
||||
u32 tcpInErrs[4];
|
||||
u32 tnlCongDrops[4];
|
||||
u32 ofldChanDrops[4];
|
||||
u32 tnlTxDrops[4];
|
||||
u32 ofldVlanDrops[4];
|
||||
u32 tcp6InErrs[4];
|
||||
u32 ofldNoNeigh;
|
||||
u32 ofldCongDefer;
|
||||
};
|
||||
|
||||
struct tp_proxy_stats {
|
||||
u32 proxy[4];
|
||||
};
|
||||
|
||||
struct tp_cpl_stats {
|
||||
u32 req[4];
|
||||
u32 rsp[4];
|
||||
u32 tx_err[4];
|
||||
};
|
||||
|
||||
struct tp_rdma_stats {
|
||||
u32 rqe_dfr_mod;
|
||||
u32 rqe_dfr_pkt;
|
||||
};
|
||||
|
||||
struct tp_params {
|
||||
unsigned int ntxchan; /* # of Tx channels */
|
||||
unsigned int tre; /* log2 of core clocks per TP tick */
|
||||
unsigned int dack_re; /* DACK timer resolution */
|
||||
unsigned int la_mask; /* what events are recorded by TP LA */
|
||||
unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
|
||||
};
|
||||
|
||||
struct vpd_params {
|
||||
unsigned int cclk;
|
||||
u8 ec[EC_LEN + 1];
|
||||
u8 sn[SERNUM_LEN + 1];
|
||||
u8 id[ID_LEN + 1];
|
||||
};
|
||||
|
||||
struct pci_params {
|
||||
unsigned int vpd_cap_addr;
|
||||
unsigned char speed;
|
||||
unsigned char width;
|
||||
};
|
||||
|
||||
/*
|
||||
* Firmware device log.
|
||||
*/
|
||||
struct devlog_params {
|
||||
u32 memtype; /* which memory (EDC0, EDC1, MC) */
|
||||
u32 start; /* start of log in firmware memory */
|
||||
u32 size; /* size of log */
|
||||
};
|
||||
|
||||
struct adapter_params {
|
||||
struct tp_params tp;
|
||||
struct vpd_params vpd;
|
||||
struct pci_params pci;
|
||||
struct devlog_params devlog;
|
||||
|
||||
unsigned int sf_size; /* serial flash size in bytes */
|
||||
unsigned int sf_nsec; /* # of flash sectors */
|
||||
|
||||
unsigned int fw_vers;
|
||||
unsigned int tp_vers;
|
||||
u8 api_vers[7];
|
||||
|
||||
unsigned short mtus[NMTUS];
|
||||
unsigned short a_wnd[NCCTRL_WIN];
|
||||
unsigned short b_wnd[NCCTRL_WIN];
|
||||
|
||||
unsigned int mc_size; /* MC memory size */
|
||||
unsigned int nfilters; /* size of filter region */
|
||||
|
||||
unsigned int cim_la_size;
|
||||
|
||||
unsigned int nports; /* # of ethernet ports */
|
||||
unsigned int portvec;
|
||||
unsigned int rev; /* chip revision */
|
||||
unsigned int offload;
|
||||
|
||||
unsigned int ofldq_wr_cred;
|
||||
};
|
||||
|
||||
enum { /* chip revisions */
|
||||
T4_REV_A = 0,
|
||||
};
|
||||
|
||||
struct trace_params {
|
||||
u32 data[TRACE_LEN / 4];
|
||||
u32 mask[TRACE_LEN / 4];
|
||||
unsigned short snap_len;
|
||||
unsigned short min_len;
|
||||
unsigned char skip_ofst;
|
||||
unsigned char skip_len;
|
||||
unsigned char invert;
|
||||
unsigned char port;
|
||||
};
|
||||
|
||||
struct link_config {
|
||||
unsigned short supported; /* link capabilities */
|
||||
unsigned short advertising; /* advertised capabilities */
|
||||
unsigned short requested_speed; /* speed user has requested */
|
||||
unsigned short speed; /* actual link speed */
|
||||
unsigned char requested_fc; /* flow control user has requested */
|
||||
unsigned char fc; /* actual link flow control */
|
||||
unsigned char autoneg; /* autonegotiating? */
|
||||
unsigned char link_ok; /* link up? */
|
||||
};
|
||||
|
||||
#include "adapter.h"
|
||||
|
||||
#ifndef PCI_VENDOR_ID_CHELSIO
|
||||
# define PCI_VENDOR_ID_CHELSIO 0x1425
|
||||
#endif
|
||||
|
||||
#define for_each_port(adapter, iter) \
|
||||
for (iter = 0; iter < (adapter)->params.nports; ++iter)
|
||||
|
||||
static inline int is_offload(const struct adapter *adap)
|
||||
{
|
||||
return adap->params.offload;
|
||||
}
|
||||
|
||||
static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
|
||||
{
|
||||
return adap->params.vpd.cclk / 1000;
|
||||
}
|
||||
|
||||
static inline unsigned int us_to_core_ticks(const struct adapter *adap,
|
||||
unsigned int us)
|
||||
{
|
||||
return (us * adap->params.vpd.cclk) / 1000;
|
||||
}
|
||||
|
||||
static inline unsigned int dack_ticks_to_usec(const struct adapter *adap,
|
||||
unsigned int ticks)
|
||||
{
|
||||
return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap);
|
||||
}
|
||||
|
||||
void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, u32 val);
|
||||
int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, int polarity,
|
||||
int attempts, int delay, u32 *valp);
|
||||
|
||||
static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
|
||||
int polarity, int attempts, int delay)
|
||||
{
|
||||
return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
|
||||
delay, NULL);
|
||||
}
|
||||
|
||||
int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
|
||||
void *rpl, bool sleep_ok);
|
||||
|
||||
static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
|
||||
int size, void *rpl)
|
||||
{
|
||||
return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
|
||||
}
|
||||
|
||||
static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
|
||||
int size, void *rpl)
|
||||
{
|
||||
return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
|
||||
}
|
||||
|
||||
void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
|
||||
unsigned int data_reg, u32 *vals, unsigned int nregs,
|
||||
unsigned int start_idx);
|
||||
void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
|
||||
unsigned int data_reg, const u32 *vals,
|
||||
unsigned int nregs, unsigned int start_idx);
|
||||
|
||||
struct fw_filter_wr;
|
||||
|
||||
void t4_intr_enable(struct adapter *adapter);
|
||||
void t4_intr_disable(struct adapter *adapter);
|
||||
void t4_intr_clear(struct adapter *adapter);
|
||||
int t4_slow_intr_handler(struct adapter *adapter);
|
||||
|
||||
int t4_hash_mac_addr(const u8 *addr);
|
||||
int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
|
||||
struct link_config *lc);
|
||||
int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
|
||||
int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data);
|
||||
int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data);
|
||||
int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz);
|
||||
int t4_seeprom_wp(struct adapter *adapter, int enable);
|
||||
int t4_read_flash(struct adapter *adapter, unsigned int addr, unsigned int nwords,
|
||||
u32 *data, int byte_oriented);
|
||||
int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
|
||||
int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
|
||||
int t4_get_fw_version(struct adapter *adapter, u32 *vers);
|
||||
int t4_get_tp_version(struct adapter *adapter, u32 *vers);
|
||||
int t4_check_fw_version(struct adapter *adapter);
|
||||
int t4_init_hw(struct adapter *adapter, u32 fw_params);
|
||||
int t4_prep_adapter(struct adapter *adapter);
|
||||
int t4_port_init(struct port_info *p, int mbox, int pf, int vf);
|
||||
int t4_reinit_adapter(struct adapter *adap);
|
||||
void t4_fatal_err(struct adapter *adapter);
|
||||
int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
|
||||
int filter_index, int enable);
|
||||
void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
|
||||
int filter_index, int *enabled);
|
||||
int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
|
||||
int start, int n, const u16 *rspq, unsigned int nrspq);
|
||||
int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
|
||||
unsigned int flags);
|
||||
int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
|
||||
unsigned int flags, unsigned int defq);
|
||||
int t4_read_rss(struct adapter *adapter, u16 *entries);
|
||||
void t4_read_rss_key(struct adapter *adapter, u32 *key);
|
||||
void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx);
|
||||
void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, u32 *valp);
|
||||
void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, u32 val);
|
||||
void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
|
||||
u32 *vfl, u32 *vfh);
|
||||
void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index,
|
||||
u32 vfl, u32 vfh);
|
||||
u32 t4_read_rss_pf_map(struct adapter *adapter);
|
||||
void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap);
|
||||
u32 t4_read_rss_pf_mask(struct adapter *adapter);
|
||||
void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask);
|
||||
int t4_mps_set_active_ports(struct adapter *adap, unsigned int port_mask);
|
||||
void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
|
||||
void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
|
||||
void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
|
||||
int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n);
|
||||
int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n);
|
||||
int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
|
||||
unsigned int *valp);
|
||||
int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
|
||||
const unsigned int *valp);
|
||||
int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n,
|
||||
unsigned int *valp);
|
||||
int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
|
||||
void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
|
||||
unsigned int *pif_req_wrptr, unsigned int *pif_rsp_wrptr);
|
||||
void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
|
||||
int t4_mc_read(struct adapter *adap, u32 addr, __be32 *data, u64 *parity);
|
||||
int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *parity);
|
||||
int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 size,
|
||||
__be32 *data);
|
||||
|
||||
void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
|
||||
void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p);
|
||||
void t4_clr_port_stats(struct adapter *adap, int idx);
|
||||
|
||||
void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
|
||||
void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
|
||||
void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]);
|
||||
void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps,
|
||||
unsigned int *ipg);
|
||||
void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
|
||||
unsigned int mask, unsigned int val);
|
||||
void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
|
||||
void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st);
|
||||
void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st);
|
||||
void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st);
|
||||
void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st);
|
||||
void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st);
|
||||
void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
|
||||
struct tp_tcp_stats *v6);
|
||||
void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
|
||||
struct tp_fcoe_stats *st);
|
||||
void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
|
||||
const unsigned short *alpha, const unsigned short *beta);
|
||||
|
||||
void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
|
||||
|
||||
int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps);
|
||||
int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg);
|
||||
int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals,
|
||||
unsigned int start, unsigned int n);
|
||||
void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate);
|
||||
int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map);
|
||||
void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
|
||||
|
||||
void t4_wol_magic_enable(struct adapter *adap, unsigned int port, const u8 *addr);
|
||||
int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
|
||||
u64 mask0, u64 mask1, unsigned int crc, bool enable);
|
||||
|
||||
int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
|
||||
enum dev_master master, enum dev_state *state);
|
||||
int t4_fw_bye(struct adapter *adap, unsigned int mbox);
|
||||
int t4_early_init(struct adapter *adap, unsigned int mbox);
|
||||
int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
|
||||
int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
|
||||
unsigned int vf, unsigned int nparams, const u32 *params,
|
||||
u32 *val);
|
||||
int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
|
||||
unsigned int vf, unsigned int nparams, const u32 *params,
|
||||
const u32 *val);
|
||||
int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
|
||||
unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
|
||||
unsigned int rxqi, unsigned int rxq, unsigned int tc,
|
||||
unsigned int vi, unsigned int cmask, unsigned int pmask,
|
||||
unsigned int exactf, unsigned int rcaps, unsigned int wxcaps);
|
||||
int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
|
||||
unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
|
||||
unsigned int *rss_size);
|
||||
int t4_free_vi(struct adapter *adap, unsigned int mbox,
|
||||
unsigned int pf, unsigned int vf,
|
||||
unsigned int viid);
|
||||
int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
|
||||
int mtu, int promisc, int all_multi, int bcast, int vlanex,
|
||||
bool sleep_ok);
|
||||
int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, unsigned int viid,
|
||||
bool free, unsigned int naddr, const u8 **addr, u16 *idx,
|
||||
u64 *hash, bool sleep_ok);
|
||||
int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
|
||||
int idx, const u8 *addr, bool persist, bool add_smt);
|
||||
int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
|
||||
bool ucast, u64 vec, bool sleep_ok);
|
||||
int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
|
||||
bool rx_en, bool tx_en);
|
||||
int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
|
||||
unsigned int nblinks);
|
||||
int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
|
||||
unsigned int mmd, unsigned int reg, unsigned int *valp);
|
||||
int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
|
||||
unsigned int mmd, unsigned int reg, unsigned int val);
|
||||
int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,
|
||||
unsigned int pf, unsigned int vf, unsigned int iqid,
|
||||
unsigned int fl0id, unsigned int fl1id);
|
||||
int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
|
||||
unsigned int vf, unsigned int iqtype, unsigned int iqid,
|
||||
unsigned int fl0id, unsigned int fl1id);
|
||||
int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
|
||||
unsigned int vf, unsigned int eqid);
|
||||
int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
|
||||
unsigned int vf, unsigned int eqid);
|
||||
int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
|
||||
unsigned int vf, unsigned int eqid);
|
||||
int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
|
||||
enum ctxt_type ctype, u32 *data);
|
||||
int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype,
|
||||
u32 *data);
|
||||
int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
|
||||
#endif /* __CHELSIO_COMMON_H */
|
||||
4590
sys/dev/cxgbe/common/t4_hw.c
Normal file
4590
sys/dev/cxgbe/common/t4_hw.c
Normal file
File diff suppressed because it is too large
Load Diff
185
sys/dev/cxgbe/common/t4_hw.h
Normal file
185
sys/dev/cxgbe/common/t4_hw.h
Normal file
@ -0,0 +1,185 @@
|
||||
/*-
|
||||
* Copyright (c) 2011 Chelsio Communications, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __T4_HW_H
|
||||
#define __T4_HW_H
|
||||
|
||||
#include "osdep.h"
|
||||
|
||||
enum {
|
||||
NCHAN = 4, /* # of HW channels */
|
||||
MAX_MTU = 9600, /* max MAC MTU, excluding header + FCS */
|
||||
EEPROMSIZE = 17408, /* Serial EEPROM physical size */
|
||||
EEPROMVSIZE = 32768, /* Serial EEPROM virtual address space size */
|
||||
EEPROMPFSIZE = 1024, /* EEPROM writable area size for PFn, n>0 */
|
||||
RSS_NENTRIES = 2048, /* # of entries in RSS mapping table */
|
||||
TCB_SIZE = 128, /* TCB size */
|
||||
NMTUS = 16, /* size of MTU table */
|
||||
NCCTRL_WIN = 32, /* # of congestion control windows */
|
||||
NTX_SCHED = 8, /* # of HW Tx scheduling queues */
|
||||
PM_NSTATS = 5, /* # of PM stats */
|
||||
MBOX_LEN = 64, /* mailbox size in bytes */
|
||||
TRACE_LEN = 112, /* length of trace data and mask */
|
||||
FILTER_OPT_LEN = 36, /* filter tuple width for optional components */
|
||||
NWOL_PAT = 8, /* # of WoL patterns */
|
||||
WOL_PAT_LEN = 128, /* length of WoL patterns */
|
||||
};
|
||||
|
||||
enum {
|
||||
CIM_NUM_IBQ = 6, /* # of CIM IBQs */
|
||||
CIM_NUM_OBQ = 6, /* # of CIM OBQs */
|
||||
CIMLA_SIZE = 2048, /* # of 32-bit words in CIM LA */
|
||||
CIM_PIFLA_SIZE = 64, /* # of 192-bit words in CIM PIF LA */
|
||||
CIM_MALA_SIZE = 64, /* # of 160-bit words in CIM MA LA */
|
||||
CIM_IBQ_SIZE = 128, /* # of 128-bit words in a CIM IBQ */
|
||||
TPLA_SIZE = 128, /* # of 64-bit words in TP LA */
|
||||
ULPRX_LA_SIZE = 512, /* # of 256-bit words in ULP_RX LA */
|
||||
};
|
||||
|
||||
enum {
|
||||
SF_PAGE_SIZE = 256, /* serial flash page size */
|
||||
SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */
|
||||
};
|
||||
|
||||
/* SGE context types */
|
||||
enum ctxt_type { CTXT_EGRESS, CTXT_INGRESS, CTXT_FLM, CTXT_CNM };
|
||||
|
||||
enum { RSP_TYPE_FLBUF, RSP_TYPE_CPL, RSP_TYPE_INTR }; /* response entry types */
|
||||
|
||||
enum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV }; /* mailbox owners */
|
||||
|
||||
enum {
|
||||
SGE_MAX_WR_LEN = 512, /* max WR size in bytes */
|
||||
SGE_CTXT_SIZE = 24, /* size of SGE context */
|
||||
SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */
|
||||
SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */
|
||||
};
|
||||
|
||||
struct sge_qstat { /* data written to SGE queue status entries */
|
||||
volatile __be32 qid;
|
||||
volatile __be16 cidx;
|
||||
volatile __be16 pidx;
|
||||
};
|
||||
|
||||
#define S_QSTAT_PIDX 0
|
||||
#define M_QSTAT_PIDX 0xffff
|
||||
#define G_QSTAT_PIDX(x) (((x) >> S_QSTAT_PIDX) & M_QSTAT_PIDX)
|
||||
|
||||
#define S_QSTAT_CIDX 16
|
||||
#define M_QSTAT_CIDX 0xffff
|
||||
#define G_QSTAT_CIDX(x) (((x) >> S_QSTAT_CIDX) & M_QSTAT_CIDX)
|
||||
|
||||
/*
|
||||
* Structure for last 128 bits of response descriptors
|
||||
*/
|
||||
struct rsp_ctrl {
|
||||
__be32 hdrbuflen_pidx;
|
||||
__be32 pldbuflen_qid;
|
||||
union {
|
||||
u8 type_gen;
|
||||
__be64 last_flit;
|
||||
} u;
|
||||
};
|
||||
|
||||
#define S_RSPD_NEWBUF 31
|
||||
#define V_RSPD_NEWBUF(x) ((x) << S_RSPD_NEWBUF)
|
||||
#define F_RSPD_NEWBUF V_RSPD_NEWBUF(1U)
|
||||
|
||||
#define S_RSPD_LEN 0
|
||||
#define M_RSPD_LEN 0x7fffffff
|
||||
#define V_RSPD_LEN(x) ((x) << S_RSPD_LEN)
|
||||
#define G_RSPD_LEN(x) (((x) >> S_RSPD_LEN) & M_RSPD_LEN)
|
||||
|
||||
#define S_RSPD_QID S_RSPD_LEN
|
||||
#define M_RSPD_QID M_RSPD_LEN
|
||||
#define V_RSPD_QID(x) V_RSPD_LEN(x)
|
||||
#define G_RSPD_QID(x) G_RSPD_LEN(x)
|
||||
|
||||
#define S_RSPD_GEN 7
|
||||
#define V_RSPD_GEN(x) ((x) << S_RSPD_GEN)
|
||||
#define F_RSPD_GEN V_RSPD_GEN(1U)
|
||||
|
||||
#define S_RSPD_QOVFL 6
|
||||
#define V_RSPD_QOVFL(x) ((x) << S_RSPD_QOVFL)
|
||||
#define F_RSPD_QOVFL V_RSPD_QOVFL(1U)
|
||||
|
||||
#define S_RSPD_TYPE 4
|
||||
#define M_RSPD_TYPE 0x3
|
||||
#define V_RSPD_TYPE(x) ((x) << S_RSPD_TYPE)
|
||||
#define G_RSPD_TYPE(x) (((x) >> S_RSPD_TYPE) & M_RSPD_TYPE)
|
||||
|
||||
/* Rx queue interrupt deferral fields: counter enable and timer index */
|
||||
#define S_QINTR_CNT_EN 0
|
||||
#define V_QINTR_CNT_EN(x) ((x) << S_QINTR_CNT_EN)
|
||||
#define F_QINTR_CNT_EN V_QINTR_CNT_EN(1U)
|
||||
|
||||
#define S_QINTR_TIMER_IDX 1
|
||||
#define M_QINTR_TIMER_IDX 0x7
|
||||
#define V_QINTR_TIMER_IDX(x) ((x) << S_QINTR_TIMER_IDX)
|
||||
#define G_QINTR_TIMER_IDX(x) (((x) >> S_QINTR_TIMER_IDX) & M_QINTR_TIMER_IDX)
|
||||
|
||||
/* # of pages a pagepod can hold without needing another pagepod */
|
||||
#define PPOD_PAGES 4U
|
||||
|
||||
struct pagepod {
|
||||
__be64 vld_tid_pgsz_tag_color;
|
||||
__be64 len_offset;
|
||||
__be64 rsvd;
|
||||
__be64 addr[PPOD_PAGES + 1];
|
||||
};
|
||||
|
||||
#define S_PPOD_COLOR 0
|
||||
#define M_PPOD_COLOR 0x3F
|
||||
#define V_PPOD_COLOR(x) ((x) << S_PPOD_COLOR)
|
||||
|
||||
#define S_PPOD_TAG 6
|
||||
#define M_PPOD_TAG 0xFFFFFF
|
||||
#define V_PPOD_TAG(x) ((x) << S_PPOD_TAG)
|
||||
|
||||
#define S_PPOD_PGSZ 30
|
||||
#define M_PPOD_PGSZ 0x3
|
||||
#define V_PPOD_PGSZ(x) ((x) << S_PPOD_PGSZ)
|
||||
|
||||
#define S_PPOD_TID 32
|
||||
#define M_PPOD_TID 0xFFFFFF
|
||||
#define V_PPOD_TID(x) ((__u64)(x) << S_PPOD_TID)
|
||||
|
||||
#define S_PPOD_VALID 56
|
||||
#define V_PPOD_VALID(x) ((__u64)(x) << S_PPOD_VALID)
|
||||
#define F_PPOD_VALID V_PPOD_VALID(1ULL)
|
||||
|
||||
#define S_PPOD_LEN 32
|
||||
#define M_PPOD_LEN 0xFFFFFFFF
|
||||
#define V_PPOD_LEN(x) ((__u64)(x) << S_PPOD_LEN)
|
||||
|
||||
#define S_PPOD_OFST 0
|
||||
#define M_PPOD_OFST 0xFFFFFFFF
|
||||
#define V_PPOD_OFST(x) ((x) << S_PPOD_OFST)
|
||||
|
||||
#endif /* __T4_HW_H */
|
||||
2138
sys/dev/cxgbe/common/t4_msg.h
Normal file
2138
sys/dev/cxgbe/common/t4_msg.h
Normal file
File diff suppressed because it is too large
Load Diff
23972
sys/dev/cxgbe/common/t4_regs.h
Normal file
23972
sys/dev/cxgbe/common/t4_regs.h
Normal file
File diff suppressed because it is too large
Load Diff
192
sys/dev/cxgbe/common/t4_regs_values.h
Normal file
192
sys/dev/cxgbe/common/t4_regs_values.h
Normal file
@ -0,0 +1,192 @@
|
||||
/*-
|
||||
* Copyright (c) 2011 Chelsio Communications, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __T4_REGS_VALUES_H__
|
||||
#define __T4_REGS_VALUES_H__
|
||||
|
||||
/*
|
||||
* This file contains definitions for various T4 register value hardware
|
||||
* constants. The types of values encoded here are predominantly those for
|
||||
* register fields which control "modal" behavior. For the most part, we do
|
||||
* not include definitions for register fields which are simple numeric
|
||||
* metrics, etc.
|
||||
*
|
||||
* These new "modal values" use a naming convention which matches the
|
||||
* currently existing macros in t4_reg.h. For register field FOO which would
|
||||
* have S_FOO, M_FOO, V_FOO() and G_FOO() macros, we introduce X_FOO_{MODE}
|
||||
* definitions. These can be used as V_FOO(X_FOO_MODE) or as (G_FOO(x) ==
|
||||
* X_FOO_MODE).
|
||||
*
|
||||
* Note that this should all be part of t4_regs.h but the toolset used to
|
||||
* generate that file doesn't [yet] have the capability of collecting these
|
||||
* constants.
|
||||
*/
|
||||
|
||||
/*
|
||||
* SGE definitions.
|
||||
* ================
|
||||
*/
|
||||
|
||||
/*
|
||||
* SGE register field values.
|
||||
*/
|
||||
|
||||
/* CONTROL register */
|
||||
#define X_FLSPLITMODE_FLSPLITMIN 0
|
||||
#define X_FLSPLITMODE_ETHHDR 1
|
||||
#define X_FLSPLITMODE_IPHDR 2
|
||||
#define X_FLSPLITMODE_TCPHDR 3
|
||||
|
||||
#define X_DCASYSTYPE_FSB 0
|
||||
#define X_DCASYSTYPE_CSI 1
|
||||
|
||||
#define X_EGSTATPAGESIZE_64B 0
|
||||
#define X_EGSTATPAGESIZE_128B 1
|
||||
|
||||
#define X_RXPKTCPLMODE_DATA 0
|
||||
#define X_RXPKTCPLMODE_SPLIT 1
|
||||
|
||||
#define X_INGPCIEBOUNDARY_SHIFT 5
|
||||
#define X_INGPCIEBOUNDARY_32B 0
|
||||
#define X_INGPCIEBOUNDARY_64B 1
|
||||
#define X_INGPCIEBOUNDARY_128B 2
|
||||
#define X_INGPCIEBOUNDARY_256B 3
|
||||
#define X_INGPCIEBOUNDARY_512B 4
|
||||
#define X_INGPCIEBOUNDARY_1024B 5
|
||||
#define X_INGPCIEBOUNDARY_2048B 6
|
||||
#define X_INGPCIEBOUNDARY_4096B 7
|
||||
|
||||
#define X_INGPADBOUNDARY_SHIFT 5
|
||||
#define X_INGPADBOUNDARY_32B 0
|
||||
#define X_INGPADBOUNDARY_64B 1
|
||||
#define X_INGPADBOUNDARY_128B 2
|
||||
#define X_INGPADBOUNDARY_256B 3
|
||||
#define X_INGPADBOUNDARY_512B 4
|
||||
#define X_INGPADBOUNDARY_1024B 5
|
||||
#define X_INGPADBOUNDARY_2048B 6
|
||||
#define X_INGPADBOUNDARY_4096B 7
|
||||
|
||||
#define X_EGRPCIEBOUNDARY_SHIFT 5
|
||||
#define X_EGRPCIEBOUNDARY_32B 0
|
||||
#define X_EGRPCIEBOUNDARY_64B 1
|
||||
#define X_EGRPCIEBOUNDARY_128B 2
|
||||
#define X_EGRPCIEBOUNDARY_256B 3
|
||||
#define X_EGRPCIEBOUNDARY_512B 4
|
||||
#define X_EGRPCIEBOUNDARY_1024B 5
|
||||
#define X_EGRPCIEBOUNDARY_2048B 6
|
||||
#define X_EGRPCIEBOUNDARY_4096B 7
|
||||
|
||||
/* GTS register */
|
||||
#define SGE_TIMERREGS 6
|
||||
#define X_TIMERREG_COUNTER0 0
|
||||
#define X_TIMERREG_COUNTER1 1
|
||||
#define X_TIMERREG_COUNTER2 2
|
||||
#define X_TIMERREG_COUNTER3 3
|
||||
#define X_TIMERREG_COUNTER4 4
|
||||
#define X_TIMERREG_COUNTER5 5
|
||||
#define X_TIMERREG_RESTART_COUNTER 6
|
||||
#define X_TIMERREG_UPDATE_CIDX 7
|
||||
|
||||
/*
|
||||
* Egress Context field values
|
||||
*/
|
||||
#define EC_WR_UNITS 16
|
||||
|
||||
#define X_FETCHBURSTMIN_SHIFT 4
|
||||
#define X_FETCHBURSTMIN_16B 0
|
||||
#define X_FETCHBURSTMIN_32B 1
|
||||
#define X_FETCHBURSTMIN_64B 2
|
||||
#define X_FETCHBURSTMIN_128B 3
|
||||
|
||||
#define X_FETCHBURSTMAX_SHIFT 6
|
||||
#define X_FETCHBURSTMAX_64B 0
|
||||
#define X_FETCHBURSTMAX_128B 1
|
||||
#define X_FETCHBURSTMAX_256B 2
|
||||
#define X_FETCHBURSTMAX_512B 3
|
||||
|
||||
#define X_HOSTFCMODE_NONE 0
|
||||
#define X_HOSTFCMODE_INGRESS_QUEUE 1
|
||||
#define X_HOSTFCMODE_STATUS_PAGE 2
|
||||
#define X_HOSTFCMODE_BOTH 3
|
||||
|
||||
#define X_HOSTFCOWNER_UP 0
|
||||
#define X_HOSTFCOWNER_SGE 1
|
||||
|
||||
#define X_CIDXFLUSHTHRESH_1 0
|
||||
#define X_CIDXFLUSHTHRESH_2 1
|
||||
#define X_CIDXFLUSHTHRESH_4 2
|
||||
#define X_CIDXFLUSHTHRESH_8 3
|
||||
#define X_CIDXFLUSHTHRESH_16 4
|
||||
#define X_CIDXFLUSHTHRESH_32 5
|
||||
#define X_CIDXFLUSHTHRESH_64 6
|
||||
#define X_CIDXFLUSHTHRESH_128 7
|
||||
|
||||
#define X_IDXSIZE_UNIT 64
|
||||
|
||||
#define X_BASEADDRESS_ALIGN 512
|
||||
|
||||
/*
|
||||
* Ingress Context field values
|
||||
*/
|
||||
#define X_UPDATESCHEDULING_TIMER 0
|
||||
#define X_UPDATESCHEDULING_COUNTER_OPTTIMER 1
|
||||
|
||||
#define X_UPDATEDELIVERY_NONE 0
|
||||
#define X_UPDATEDELIVERY_INTERRUPT 1
|
||||
#define X_UPDATEDELIVERY_STATUS_PAGE 2
|
||||
#define X_UPDATEDELIVERY_BOTH 3
|
||||
|
||||
#define X_INTERRUPTDESTINATION_PCIE 0
|
||||
#define X_INTERRUPTDESTINATION_IQ 1
|
||||
|
||||
#define X_QUEUEENTRYSIZE_16B 0
|
||||
#define X_QUEUEENTRYSIZE_32B 1
|
||||
#define X_QUEUEENTRYSIZE_64B 2
|
||||
#define X_QUEUEENTRYSIZE_128B 3
|
||||
|
||||
#define IC_SIZE_UNIT 16
|
||||
#define IC_BASEADDRESS_ALIGN 512
|
||||
|
||||
#define X_RSPD_TYPE_FLBUF 0
|
||||
#define X_RSPD_TYPE_CPL 1
|
||||
#define X_RSPD_TYPE_INTR 2
|
||||
|
||||
/*
|
||||
* CIM definitions.
|
||||
* ================
|
||||
*/
|
||||
|
||||
/*
|
||||
* CIM register field values.
|
||||
*/
|
||||
#define X_MBOWNER_NONE 0
|
||||
#define X_MBOWNER_FW 1
|
||||
#define X_MBOWNER_PL 2
|
||||
|
||||
#endif /* __T4_REGS_VALUES_H__ */
|
||||
753
sys/dev/cxgbe/common/t4_tcb.h
Normal file
753
sys/dev/cxgbe/common/t4_tcb.h
Normal file
@ -0,0 +1,753 @@
|
||||
/*-
|
||||
* Copyright (c) 2011 Chelsio Communications, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*
|
||||
*/
|
||||
|
||||
/* This file is automatically generated --- changes will be lost */
|
||||
|
||||
#ifndef _T4_TCB_DEFS_H
|
||||
#define _T4_TCB_DEFS_H
|
||||
|
||||
/* 3:0 */
|
||||
#define W_TCB_ULP_TYPE 0
|
||||
#define S_TCB_ULP_TYPE 0
|
||||
#define M_TCB_ULP_TYPE 0xfULL
|
||||
#define V_TCB_ULP_TYPE(x) ((x) << S_TCB_ULP_TYPE)
|
||||
|
||||
/* 11:4 */
|
||||
#define W_TCB_ULP_RAW 0
|
||||
#define S_TCB_ULP_RAW 4
|
||||
#define M_TCB_ULP_RAW 0xffULL
|
||||
#define V_TCB_ULP_RAW(x) ((x) << S_TCB_ULP_RAW)
|
||||
|
||||
/* 23:12 */
|
||||
#define W_TCB_L2T_IX 0
|
||||
#define S_TCB_L2T_IX 12
|
||||
#define M_TCB_L2T_IX 0xfffULL
|
||||
#define V_TCB_L2T_IX(x) ((x) << S_TCB_L2T_IX)
|
||||
|
||||
/* 31:24 */
|
||||
#define W_TCB_SMAC_SEL 0
|
||||
#define S_TCB_SMAC_SEL 24
|
||||
#define M_TCB_SMAC_SEL 0xffULL
|
||||
#define V_TCB_SMAC_SEL(x) ((x) << S_TCB_SMAC_SEL)
|
||||
|
||||
/* 95:32 */
|
||||
#define W_TCB_T_FLAGS 1
|
||||
#define S_TCB_T_FLAGS 0
|
||||
#define M_TCB_T_FLAGS 0xffffffffffffffffULL
|
||||
#define V_TCB_T_FLAGS(x) ((__u64)(x) << S_TCB_T_FLAGS)
|
||||
|
||||
/* 105:96 */
|
||||
#define W_TCB_RSS_INFO 3
|
||||
#define S_TCB_RSS_INFO 0
|
||||
#define M_TCB_RSS_INFO 0x3ffULL
|
||||
#define V_TCB_RSS_INFO(x) ((x) << S_TCB_RSS_INFO)
|
||||
|
||||
/* 111:106 */
|
||||
#define W_TCB_TOS 3
|
||||
#define S_TCB_TOS 10
|
||||
#define M_TCB_TOS 0x3fULL
|
||||
#define V_TCB_TOS(x) ((x) << S_TCB_TOS)
|
||||
|
||||
/* 115:112 */
|
||||
#define W_TCB_T_STATE 3
|
||||
#define S_TCB_T_STATE 16
|
||||
#define M_TCB_T_STATE 0xfULL
|
||||
#define V_TCB_T_STATE(x) ((x) << S_TCB_T_STATE)
|
||||
|
||||
/* 119:116 */
|
||||
#define W_TCB_MAX_RT 3
|
||||
#define S_TCB_MAX_RT 20
|
||||
#define M_TCB_MAX_RT 0xfULL
|
||||
#define V_TCB_MAX_RT(x) ((x) << S_TCB_MAX_RT)
|
||||
|
||||
/* 123:120 */
|
||||
#define W_TCB_T_MAXSEG 3
|
||||
#define S_TCB_T_MAXSEG 24
|
||||
#define M_TCB_T_MAXSEG 0xfULL
|
||||
#define V_TCB_T_MAXSEG(x) ((x) << S_TCB_T_MAXSEG)
|
||||
|
||||
/* 127:124 */
|
||||
#define W_TCB_SND_SCALE 3
|
||||
#define S_TCB_SND_SCALE 28
|
||||
#define M_TCB_SND_SCALE 0xfULL
|
||||
#define V_TCB_SND_SCALE(x) ((x) << S_TCB_SND_SCALE)
|
||||
|
||||
/* 131:128 */
|
||||
#define W_TCB_RCV_SCALE 4
|
||||
#define S_TCB_RCV_SCALE 0
|
||||
#define M_TCB_RCV_SCALE 0xfULL
|
||||
#define V_TCB_RCV_SCALE(x) ((x) << S_TCB_RCV_SCALE)
|
||||
|
||||
/* 135:132 */
|
||||
#define W_TCB_T_RXTSHIFT 4
|
||||
#define S_TCB_T_RXTSHIFT 4
|
||||
#define M_TCB_T_RXTSHIFT 0xfULL
|
||||
#define V_TCB_T_RXTSHIFT(x) ((x) << S_TCB_T_RXTSHIFT)
|
||||
|
||||
/* 139:136 */
|
||||
#define W_TCB_T_DUPACKS 4
|
||||
#define S_TCB_T_DUPACKS 8
|
||||
#define M_TCB_T_DUPACKS 0xfULL
|
||||
#define V_TCB_T_DUPACKS(x) ((x) << S_TCB_T_DUPACKS)
|
||||
|
||||
/* 143:140 */
|
||||
#define W_TCB_TIMESTAMP_OFFSET 4
|
||||
#define S_TCB_TIMESTAMP_OFFSET 12
|
||||
#define M_TCB_TIMESTAMP_OFFSET 0xfULL
|
||||
#define V_TCB_TIMESTAMP_OFFSET(x) ((x) << S_TCB_TIMESTAMP_OFFSET)
|
||||
|
||||
/* 159:144 */
|
||||
#define W_TCB_RCV_ADV 4
|
||||
#define S_TCB_RCV_ADV 16
|
||||
#define M_TCB_RCV_ADV 0xffffULL
|
||||
#define V_TCB_RCV_ADV(x) ((x) << S_TCB_RCV_ADV)
|
||||
|
||||
/* 191:160 */
|
||||
#define W_TCB_TIMESTAMP 5
|
||||
#define S_TCB_TIMESTAMP 0
|
||||
#define M_TCB_TIMESTAMP 0xffffffffULL
|
||||
#define V_TCB_TIMESTAMP(x) ((x) << S_TCB_TIMESTAMP)
|
||||
|
||||
/* 223:192 */
|
||||
#define W_TCB_T_RTT_TS_RECENT_AGE 6
|
||||
#define S_TCB_T_RTT_TS_RECENT_AGE 0
|
||||
#define M_TCB_T_RTT_TS_RECENT_AGE 0xffffffffULL
|
||||
#define V_TCB_T_RTT_TS_RECENT_AGE(x) ((x) << S_TCB_T_RTT_TS_RECENT_AGE)
|
||||
|
||||
/* 255:224 */
|
||||
#define W_TCB_T_RTSEQ_RECENT 7
|
||||
#define S_TCB_T_RTSEQ_RECENT 0
|
||||
#define M_TCB_T_RTSEQ_RECENT 0xffffffffULL
|
||||
#define V_TCB_T_RTSEQ_RECENT(x) ((x) << S_TCB_T_RTSEQ_RECENT)
|
||||
|
||||
/* 271:256 */
|
||||
#define W_TCB_T_SRTT 8
|
||||
#define S_TCB_T_SRTT 0
|
||||
#define M_TCB_T_SRTT 0xffffULL
|
||||
#define V_TCB_T_SRTT(x) ((x) << S_TCB_T_SRTT)
|
||||
|
||||
/* 287:272 */
|
||||
#define W_TCB_T_RTTVAR 8
|
||||
#define S_TCB_T_RTTVAR 16
|
||||
#define M_TCB_T_RTTVAR 0xffffULL
|
||||
#define V_TCB_T_RTTVAR(x) ((x) << S_TCB_T_RTTVAR)
|
||||
|
||||
/* 319:288 */
|
||||
#define W_TCB_TX_MAX 9
|
||||
#define S_TCB_TX_MAX 0
|
||||
#define M_TCB_TX_MAX 0xffffffffULL
|
||||
#define V_TCB_TX_MAX(x) ((x) << S_TCB_TX_MAX)
|
||||
|
||||
/* 347:320 */
|
||||
#define W_TCB_SND_UNA_RAW 10
|
||||
#define S_TCB_SND_UNA_RAW 0
|
||||
#define M_TCB_SND_UNA_RAW 0xfffffffULL
|
||||
#define V_TCB_SND_UNA_RAW(x) ((x) << S_TCB_SND_UNA_RAW)
|
||||
|
||||
/* 375:348 */
|
||||
#define W_TCB_SND_NXT_RAW 10
|
||||
#define S_TCB_SND_NXT_RAW 28
|
||||
#define M_TCB_SND_NXT_RAW 0xfffffffULL
|
||||
#define V_TCB_SND_NXT_RAW(x) ((__u64)(x) << S_TCB_SND_NXT_RAW)
|
||||
|
||||
/* 403:376 */
|
||||
#define W_TCB_SND_MAX_RAW 11
|
||||
#define S_TCB_SND_MAX_RAW 24
|
||||
#define M_TCB_SND_MAX_RAW 0xfffffffULL
|
||||
#define V_TCB_SND_MAX_RAW(x) ((__u64)(x) << S_TCB_SND_MAX_RAW)
|
||||
|
||||
/* 431:404 */
|
||||
#define W_TCB_SND_REC_RAW 12
|
||||
#define S_TCB_SND_REC_RAW 20
|
||||
#define M_TCB_SND_REC_RAW 0xfffffffULL
|
||||
#define V_TCB_SND_REC_RAW(x) ((__u64)(x) << S_TCB_SND_REC_RAW)
|
||||
|
||||
/* 459:432 */
|
||||
#define W_TCB_SND_CWND 13
|
||||
#define S_TCB_SND_CWND 16
|
||||
#define M_TCB_SND_CWND 0xfffffffULL
|
||||
#define V_TCB_SND_CWND(x) ((__u64)(x) << S_TCB_SND_CWND)
|
||||
|
||||
/* 487:460 */
|
||||
#define W_TCB_SND_SSTHRESH 14
|
||||
#define S_TCB_SND_SSTHRESH 12
|
||||
#define M_TCB_SND_SSTHRESH 0xfffffffULL
|
||||
#define V_TCB_SND_SSTHRESH(x) ((__u64)(x) << S_TCB_SND_SSTHRESH)
|
||||
|
||||
/* 504:488 */
|
||||
#define W_TCB_TX_HDR_PTR_RAW 15
|
||||
#define S_TCB_TX_HDR_PTR_RAW 8
|
||||
#define M_TCB_TX_HDR_PTR_RAW 0x1ffffULL
|
||||
#define V_TCB_TX_HDR_PTR_RAW(x) ((x) << S_TCB_TX_HDR_PTR_RAW)
|
||||
|
||||
/* 521:505 */
|
||||
#define W_TCB_TX_LAST_PTR_RAW 15
|
||||
#define S_TCB_TX_LAST_PTR_RAW 25
|
||||
#define M_TCB_TX_LAST_PTR_RAW 0x1ffffULL
|
||||
#define V_TCB_TX_LAST_PTR_RAW(x) ((__u64)(x) << S_TCB_TX_LAST_PTR_RAW)
|
||||
|
||||
/* 553:522 */
|
||||
#define W_TCB_RCV_NXT 16
|
||||
#define S_TCB_RCV_NXT 10
|
||||
#define M_TCB_RCV_NXT 0xffffffffULL
|
||||
#define V_TCB_RCV_NXT(x) ((__u64)(x) << S_TCB_RCV_NXT)
|
||||
|
||||
/* 581:554 */
|
||||
#define W_TCB_RCV_WND 17
|
||||
#define S_TCB_RCV_WND 10
|
||||
#define M_TCB_RCV_WND 0xfffffffULL
|
||||
#define V_TCB_RCV_WND(x) ((__u64)(x) << S_TCB_RCV_WND)
|
||||
|
||||
/* 609:582 */
|
||||
#define W_TCB_RX_HDR_OFFSET 18
|
||||
#define S_TCB_RX_HDR_OFFSET 6
|
||||
#define M_TCB_RX_HDR_OFFSET 0xfffffffULL
|
||||
#define V_TCB_RX_HDR_OFFSET(x) ((__u64)(x) << S_TCB_RX_HDR_OFFSET)
|
||||
|
||||
/* 637:610 */
|
||||
#define W_TCB_TS_LAST_ACK_SENT_RAW 19
|
||||
#define S_TCB_TS_LAST_ACK_SENT_RAW 2
|
||||
#define M_TCB_TS_LAST_ACK_SENT_RAW 0xfffffffULL
|
||||
#define V_TCB_TS_LAST_ACK_SENT_RAW(x) ((x) << S_TCB_TS_LAST_ACK_SENT_RAW)
|
||||
|
||||
/* 665:638 */
|
||||
#define W_TCB_RX_FRAG0_START_IDX_RAW 19
|
||||
#define S_TCB_RX_FRAG0_START_IDX_RAW 30
|
||||
#define M_TCB_RX_FRAG0_START_IDX_RAW 0xfffffffULL
|
||||
#define V_TCB_RX_FRAG0_START_IDX_RAW(x) ((__u64)(x) << S_TCB_RX_FRAG0_START_IDX_RAW)
|
||||
|
||||
/* 693:666 */
|
||||
#define W_TCB_RX_FRAG1_START_IDX_OFFSET 20
|
||||
#define S_TCB_RX_FRAG1_START_IDX_OFFSET 26
|
||||
#define M_TCB_RX_FRAG1_START_IDX_OFFSET 0xfffffffULL
|
||||
#define V_TCB_RX_FRAG1_START_IDX_OFFSET(x) ((__u64)(x) << S_TCB_RX_FRAG1_START_IDX_OFFSET)
|
||||
|
||||
/* 721:694 */
|
||||
#define W_TCB_RX_FRAG0_LEN 21
|
||||
#define S_TCB_RX_FRAG0_LEN 22
|
||||
#define M_TCB_RX_FRAG0_LEN 0xfffffffULL
|
||||
#define V_TCB_RX_FRAG0_LEN(x) ((__u64)(x) << S_TCB_RX_FRAG0_LEN)
|
||||
|
||||
/* 749:722 */
|
||||
#define W_TCB_RX_FRAG1_LEN 22
|
||||
#define S_TCB_RX_FRAG1_LEN 18
|
||||
#define M_TCB_RX_FRAG1_LEN 0xfffffffULL
|
||||
#define V_TCB_RX_FRAG1_LEN(x) ((__u64)(x) << S_TCB_RX_FRAG1_LEN)
|
||||
|
||||
/* 765:750 */
|
||||
#define W_TCB_PDU_LEN 23
|
||||
#define S_TCB_PDU_LEN 14
|
||||
#define M_TCB_PDU_LEN 0xffffULL
|
||||
#define V_TCB_PDU_LEN(x) ((x) << S_TCB_PDU_LEN)
|
||||
|
||||
/* 782:766 */
|
||||
#define W_TCB_RX_PTR_RAW 23
|
||||
#define S_TCB_RX_PTR_RAW 30
|
||||
#define M_TCB_RX_PTR_RAW 0x1ffffULL
|
||||
#define V_TCB_RX_PTR_RAW(x) ((__u64)(x) << S_TCB_RX_PTR_RAW)
|
||||
|
||||
/* 799:783 */
|
||||
#define W_TCB_RX_FRAG1_PTR_RAW 24
|
||||
#define S_TCB_RX_FRAG1_PTR_RAW 15
|
||||
#define M_TCB_RX_FRAG1_PTR_RAW 0x1ffffULL
|
||||
#define V_TCB_RX_FRAG1_PTR_RAW(x) ((x) << S_TCB_RX_FRAG1_PTR_RAW)
|
||||
|
||||
/* 831:800 */
|
||||
#define W_TCB_MAIN_SLUSH 25
|
||||
#define S_TCB_MAIN_SLUSH 0
|
||||
#define M_TCB_MAIN_SLUSH 0xffffffffULL
|
||||
#define V_TCB_MAIN_SLUSH(x) ((x) << S_TCB_MAIN_SLUSH)
|
||||
|
||||
/* 846:832 */
|
||||
#define W_TCB_AUX1_SLUSH0 26
|
||||
#define S_TCB_AUX1_SLUSH0 0
|
||||
#define M_TCB_AUX1_SLUSH0 0x7fffULL
|
||||
#define V_TCB_AUX1_SLUSH0(x) ((x) << S_TCB_AUX1_SLUSH0)
|
||||
|
||||
/* 874:847 */
|
||||
#define W_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 26
|
||||
#define S_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 15
|
||||
#define M_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 0xfffffffULL
|
||||
#define V_TCB_RX_FRAG2_START_IDX_OFFSET_RAW(x) ((__u64)(x) << S_TCB_RX_FRAG2_START_IDX_OFFSET_RAW)
|
||||
|
||||
/* 891:875 */
|
||||
#define W_TCB_RX_FRAG2_PTR_RAW 27
|
||||
#define S_TCB_RX_FRAG2_PTR_RAW 11
|
||||
#define M_TCB_RX_FRAG2_PTR_RAW 0x1ffffULL
|
||||
#define V_TCB_RX_FRAG2_PTR_RAW(x) ((x) << S_TCB_RX_FRAG2_PTR_RAW)
|
||||
|
||||
/* 919:892 */
|
||||
#define W_TCB_RX_FRAG2_LEN_RAW 27
|
||||
#define S_TCB_RX_FRAG2_LEN_RAW 28
|
||||
#define M_TCB_RX_FRAG2_LEN_RAW 0xfffffffULL
|
||||
#define V_TCB_RX_FRAG2_LEN_RAW(x) ((__u64)(x) << S_TCB_RX_FRAG2_LEN_RAW)
|
||||
|
||||
/* 936:920 */
|
||||
#define W_TCB_RX_FRAG3_PTR_RAW 28
|
||||
#define S_TCB_RX_FRAG3_PTR_RAW 24
|
||||
#define M_TCB_RX_FRAG3_PTR_RAW 0x1ffffULL
|
||||
#define V_TCB_RX_FRAG3_PTR_RAW(x) ((__u64)(x) << S_TCB_RX_FRAG3_PTR_RAW)
|
||||
|
||||
/* 964:937 */
|
||||
#define W_TCB_RX_FRAG3_LEN_RAW 29
|
||||
#define S_TCB_RX_FRAG3_LEN_RAW 9
|
||||
#define M_TCB_RX_FRAG3_LEN_RAW 0xfffffffULL
|
||||
#define V_TCB_RX_FRAG3_LEN_RAW(x) ((__u64)(x) << S_TCB_RX_FRAG3_LEN_RAW)
|
||||
|
||||
/* 992:965 */
|
||||
#define W_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 30
|
||||
#define S_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 5
|
||||
#define M_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 0xfffffffULL
|
||||
#define V_TCB_RX_FRAG3_START_IDX_OFFSET_RAW(x) ((__u64)(x) << S_TCB_RX_FRAG3_START_IDX_OFFSET_RAW)
|
||||
|
||||
/* 1000:993 */
|
||||
#define W_TCB_PDU_HDR_LEN 31
|
||||
#define S_TCB_PDU_HDR_LEN 1
|
||||
#define M_TCB_PDU_HDR_LEN 0xffULL
|
||||
#define V_TCB_PDU_HDR_LEN(x) ((x) << S_TCB_PDU_HDR_LEN)
|
||||
|
||||
/* 1023:1001 */
|
||||
#define W_TCB_AUX1_SLUSH1 31
|
||||
#define S_TCB_AUX1_SLUSH1 9
|
||||
#define M_TCB_AUX1_SLUSH1 0x7fffffULL
|
||||
#define V_TCB_AUX1_SLUSH1(x) ((x) << S_TCB_AUX1_SLUSH1)
|
||||
|
||||
/* 840:832 */
|
||||
#define W_TCB_IRS_ULP 26
|
||||
#define S_TCB_IRS_ULP 0
|
||||
#define M_TCB_IRS_ULP 0x1ffULL
|
||||
#define V_TCB_IRS_ULP(x) ((x) << S_TCB_IRS_ULP)
|
||||
|
||||
/* 849:841 */
|
||||
#define W_TCB_ISS_ULP 26
|
||||
#define S_TCB_ISS_ULP 9
|
||||
#define M_TCB_ISS_ULP 0x1ffULL
|
||||
#define V_TCB_ISS_ULP(x) ((x) << S_TCB_ISS_ULP)
|
||||
|
||||
/* 863:850 */
|
||||
#define W_TCB_TX_PDU_LEN 26
|
||||
#define S_TCB_TX_PDU_LEN 18
|
||||
#define M_TCB_TX_PDU_LEN 0x3fffULL
|
||||
#define V_TCB_TX_PDU_LEN(x) ((x) << S_TCB_TX_PDU_LEN)
|
||||
|
||||
/* 879:864 */
|
||||
#define W_TCB_CQ_IDX_SQ 27
|
||||
#define S_TCB_CQ_IDX_SQ 0
|
||||
#define M_TCB_CQ_IDX_SQ 0xffffULL
|
||||
#define V_TCB_CQ_IDX_SQ(x) ((x) << S_TCB_CQ_IDX_SQ)
|
||||
|
||||
/* 895:880 */
|
||||
#define W_TCB_CQ_IDX_RQ 27
|
||||
#define S_TCB_CQ_IDX_RQ 16
|
||||
#define M_TCB_CQ_IDX_RQ 0xffffULL
|
||||
#define V_TCB_CQ_IDX_RQ(x) ((x) << S_TCB_CQ_IDX_RQ)
|
||||
|
||||
/* 911:896 */
|
||||
#define W_TCB_QP_ID 28
|
||||
#define S_TCB_QP_ID 0
|
||||
#define M_TCB_QP_ID 0xffffULL
|
||||
#define V_TCB_QP_ID(x) ((x) << S_TCB_QP_ID)
|
||||
|
||||
/* 927:912 */
|
||||
#define W_TCB_PD_ID 28
|
||||
#define S_TCB_PD_ID 16
|
||||
#define M_TCB_PD_ID 0xffffULL
|
||||
#define V_TCB_PD_ID(x) ((x) << S_TCB_PD_ID)
|
||||
|
||||
/* 959:928 */
|
||||
#define W_TCB_STAG 29
|
||||
#define S_TCB_STAG 0
|
||||
#define M_TCB_STAG 0xffffffffULL
|
||||
#define V_TCB_STAG(x) ((x) << S_TCB_STAG)
|
||||
|
||||
/* 985:960 */
|
||||
#define W_TCB_RQ_START 30
|
||||
#define S_TCB_RQ_START 0
|
||||
#define M_TCB_RQ_START 0x3ffffffULL
|
||||
#define V_TCB_RQ_START(x) ((x) << S_TCB_RQ_START)
|
||||
|
||||
/* 998:986 */
|
||||
#define W_TCB_RQ_MSN 30
|
||||
#define S_TCB_RQ_MSN 26
|
||||
#define M_TCB_RQ_MSN 0x1fffULL
|
||||
#define V_TCB_RQ_MSN(x) ((__u64)(x) << S_TCB_RQ_MSN)
|
||||
|
||||
/* 1002:999 */
|
||||
#define W_TCB_RQ_MAX_OFFSET 31
|
||||
#define S_TCB_RQ_MAX_OFFSET 7
|
||||
#define M_TCB_RQ_MAX_OFFSET 0xfULL
|
||||
#define V_TCB_RQ_MAX_OFFSET(x) ((x) << S_TCB_RQ_MAX_OFFSET)
|
||||
|
||||
/* 1015:1003 */
|
||||
#define W_TCB_RQ_WRITE_PTR 31
|
||||
#define S_TCB_RQ_WRITE_PTR 11
|
||||
#define M_TCB_RQ_WRITE_PTR 0x1fffULL
|
||||
#define V_TCB_RQ_WRITE_PTR(x) ((x) << S_TCB_RQ_WRITE_PTR)
|
||||
|
||||
/* 1019:1016 */
|
||||
#define W_TCB_RDMAP_OPCODE 31
|
||||
#define S_TCB_RDMAP_OPCODE 24
|
||||
#define M_TCB_RDMAP_OPCODE 0xfULL
|
||||
#define V_TCB_RDMAP_OPCODE(x) ((x) << S_TCB_RDMAP_OPCODE)
|
||||
|
||||
/* 1020:1020 */
|
||||
#define W_TCB_ORD_L_BIT_VLD 31
|
||||
#define S_TCB_ORD_L_BIT_VLD 28
|
||||
#define M_TCB_ORD_L_BIT_VLD 0x1ULL
|
||||
#define V_TCB_ORD_L_BIT_VLD(x) ((x) << S_TCB_ORD_L_BIT_VLD)
|
||||
|
||||
/* 1021:1021 */
|
||||
#define W_TCB_TX_FLUSH 31
|
||||
#define S_TCB_TX_FLUSH 29
|
||||
#define M_TCB_TX_FLUSH 0x1ULL
|
||||
#define V_TCB_TX_FLUSH(x) ((x) << S_TCB_TX_FLUSH)
|
||||
|
||||
/* 1022:1022 */
|
||||
#define W_TCB_TX_OOS_RXMT 31
|
||||
#define S_TCB_TX_OOS_RXMT 30
|
||||
#define M_TCB_TX_OOS_RXMT 0x1ULL
|
||||
#define V_TCB_TX_OOS_RXMT(x) ((x) << S_TCB_TX_OOS_RXMT)
|
||||
|
||||
/* 1023:1023 */
|
||||
#define W_TCB_TX_OOS_TXMT 31
|
||||
#define S_TCB_TX_OOS_TXMT 31
|
||||
#define M_TCB_TX_OOS_TXMT 0x1ULL
|
||||
#define V_TCB_TX_OOS_TXMT(x) ((x) << S_TCB_TX_OOS_TXMT)
|
||||
|
||||
/* 855:832 */
|
||||
#define W_TCB_RX_DDP_BUF0_OFFSET 26
|
||||
#define S_TCB_RX_DDP_BUF0_OFFSET 0
|
||||
#define M_TCB_RX_DDP_BUF0_OFFSET 0xffffffULL
|
||||
#define V_TCB_RX_DDP_BUF0_OFFSET(x) ((x) << S_TCB_RX_DDP_BUF0_OFFSET)
|
||||
|
||||
/* 879:856 */
|
||||
#define W_TCB_RX_DDP_BUF0_LEN 26
|
||||
#define S_TCB_RX_DDP_BUF0_LEN 24
|
||||
#define M_TCB_RX_DDP_BUF0_LEN 0xffffffULL
|
||||
#define V_TCB_RX_DDP_BUF0_LEN(x) ((__u64)(x) << S_TCB_RX_DDP_BUF0_LEN)
|
||||
|
||||
/* 903:880 */
|
||||
#define W_TCB_RX_DDP_FLAGS 27
|
||||
#define S_TCB_RX_DDP_FLAGS 16
|
||||
#define M_TCB_RX_DDP_FLAGS 0xffffffULL
|
||||
#define V_TCB_RX_DDP_FLAGS(x) ((__u64)(x) << S_TCB_RX_DDP_FLAGS)
|
||||
|
||||
/* 927:904 */
|
||||
#define W_TCB_RX_DDP_BUF1_OFFSET 28
|
||||
#define S_TCB_RX_DDP_BUF1_OFFSET 8
|
||||
#define M_TCB_RX_DDP_BUF1_OFFSET 0xffffffULL
|
||||
#define V_TCB_RX_DDP_BUF1_OFFSET(x) ((x) << S_TCB_RX_DDP_BUF1_OFFSET)
|
||||
|
||||
/* 951:928 */
|
||||
#define W_TCB_RX_DDP_BUF1_LEN 29
|
||||
#define S_TCB_RX_DDP_BUF1_LEN 0
|
||||
#define M_TCB_RX_DDP_BUF1_LEN 0xffffffULL
|
||||
#define V_TCB_RX_DDP_BUF1_LEN(x) ((x) << S_TCB_RX_DDP_BUF1_LEN)
|
||||
|
||||
/* 959:952 */
|
||||
#define W_TCB_AUX3_SLUSH 29
|
||||
#define S_TCB_AUX3_SLUSH 24
|
||||
#define M_TCB_AUX3_SLUSH 0xffULL
|
||||
#define V_TCB_AUX3_SLUSH(x) ((x) << S_TCB_AUX3_SLUSH)
|
||||
|
||||
/* 991:960 */
|
||||
#define W_TCB_RX_DDP_BUF0_TAG 30
|
||||
#define S_TCB_RX_DDP_BUF0_TAG 0
|
||||
#define M_TCB_RX_DDP_BUF0_TAG 0xffffffffULL
|
||||
#define V_TCB_RX_DDP_BUF0_TAG(x) ((x) << S_TCB_RX_DDP_BUF0_TAG)
|
||||
|
||||
/* 1023:992 */
|
||||
#define W_TCB_RX_DDP_BUF1_TAG 31
|
||||
#define S_TCB_RX_DDP_BUF1_TAG 0
|
||||
#define M_TCB_RX_DDP_BUF1_TAG 0xffffffffULL
|
||||
#define V_TCB_RX_DDP_BUF1_TAG(x) ((x) << S_TCB_RX_DDP_BUF1_TAG)
|
||||
|
||||
#define S_TF_MIGRATING 0
|
||||
#define V_TF_MIGRATING(x) ((x) << S_TF_MIGRATING)
|
||||
|
||||
#define S_TF_NON_OFFLOAD 1
|
||||
#define V_TF_NON_OFFLOAD(x) ((x) << S_TF_NON_OFFLOAD)
|
||||
|
||||
#define S_TF_LOCK_TID 2
|
||||
#define V_TF_LOCK_TID(x) ((x) << S_TF_LOCK_TID)
|
||||
|
||||
#define S_TF_KEEPALIVE 3
|
||||
#define V_TF_KEEPALIVE(x) ((x) << S_TF_KEEPALIVE)
|
||||
|
||||
#define S_TF_DACK 4
|
||||
#define V_TF_DACK(x) ((x) << S_TF_DACK)
|
||||
|
||||
#define S_TF_DACK_MSS 5
|
||||
#define V_TF_DACK_MSS(x) ((x) << S_TF_DACK_MSS)
|
||||
|
||||
#define S_TF_DACK_NOT_ACKED 6
|
||||
#define V_TF_DACK_NOT_ACKED(x) ((x) << S_TF_DACK_NOT_ACKED)
|
||||
|
||||
#define S_TF_NAGLE 7
|
||||
#define V_TF_NAGLE(x) ((x) << S_TF_NAGLE)
|
||||
|
||||
#define S_TF_SSWS_DISABLED 8
|
||||
#define V_TF_SSWS_DISABLED(x) ((x) << S_TF_SSWS_DISABLED)
|
||||
|
||||
#define S_TF_RX_FLOW_CONTROL_DDP 9
|
||||
#define V_TF_RX_FLOW_CONTROL_DDP(x) ((x) << S_TF_RX_FLOW_CONTROL_DDP)
|
||||
|
||||
#define S_TF_RX_FLOW_CONTROL_DISABLE 10
|
||||
#define V_TF_RX_FLOW_CONTROL_DISABLE(x) ((x) << S_TF_RX_FLOW_CONTROL_DISABLE)
|
||||
|
||||
#define S_TF_RX_CHANNEL 11
|
||||
#define V_TF_RX_CHANNEL(x) ((x) << S_TF_RX_CHANNEL)
|
||||
|
||||
#define S_TF_TX_CHANNEL0 12
|
||||
#define V_TF_TX_CHANNEL0(x) ((x) << S_TF_TX_CHANNEL0)
|
||||
|
||||
#define S_TF_TX_CHANNEL1 13
|
||||
#define V_TF_TX_CHANNEL1(x) ((x) << S_TF_TX_CHANNEL1)
|
||||
|
||||
#define S_TF_TX_QUIESCE 14
|
||||
#define V_TF_TX_QUIESCE(x) ((x) << S_TF_TX_QUIESCE)
|
||||
|
||||
#define S_TF_RX_QUIESCE 15
|
||||
#define V_TF_RX_QUIESCE(x) ((x) << S_TF_RX_QUIESCE)
|
||||
|
||||
#define S_TF_TX_PACE_AUTO 16
|
||||
#define V_TF_TX_PACE_AUTO(x) ((x) << S_TF_TX_PACE_AUTO)
|
||||
|
||||
#define S_TF_MASK_HASH 16
|
||||
#define V_TF_MASK_HASH(x) ((x) << S_TF_MASK_HASH)
|
||||
|
||||
#define S_TF_TX_PACE_FIXED 17
|
||||
#define V_TF_TX_PACE_FIXED(x) ((x) << S_TF_TX_PACE_FIXED)
|
||||
|
||||
#define S_TF_DIRECT_STEER_HASH 17
|
||||
#define V_TF_DIRECT_STEER_HASH(x) ((x) << S_TF_DIRECT_STEER_HASH)
|
||||
|
||||
#define S_TF_TX_QUEUE 18
|
||||
#define M_TF_TX_QUEUE 0x7ULL
|
||||
#define V_TF_TX_QUEUE(x) ((x) << S_TF_TX_QUEUE)
|
||||
|
||||
#define S_TF_TURBO 21
|
||||
#define V_TF_TURBO(x) ((x) << S_TF_TURBO)
|
||||
|
||||
#define S_TF_REPORT_TID 21
|
||||
#define V_TF_REPORT_TID(x) ((x) << S_TF_REPORT_TID)
|
||||
|
||||
#define S_TF_CCTRL_SEL0 22
|
||||
#define V_TF_CCTRL_SEL0(x) ((x) << S_TF_CCTRL_SEL0)
|
||||
|
||||
#define S_TF_DROP 22
|
||||
#define V_TF_DROP(x) ((x) << S_TF_DROP)
|
||||
|
||||
#define S_TF_CCTRL_SEL1 23
|
||||
#define V_TF_CCTRL_SEL1(x) ((x) << S_TF_CCTRL_SEL1)
|
||||
|
||||
#define S_TF_DIRECT_STEER 23
|
||||
#define V_TF_DIRECT_STEER(x) ((x) << S_TF_DIRECT_STEER)
|
||||
|
||||
#define S_TF_CORE_FIN 24
|
||||
#define V_TF_CORE_FIN(x) ((x) << S_TF_CORE_FIN)
|
||||
|
||||
#define S_TF_CORE_URG 25
|
||||
#define V_TF_CORE_URG(x) ((x) << S_TF_CORE_URG)
|
||||
|
||||
#define S_TF_CORE_MORE 26
|
||||
#define V_TF_CORE_MORE(x) ((x) << S_TF_CORE_MORE)
|
||||
|
||||
#define S_TF_CORE_PUSH 27
|
||||
#define V_TF_CORE_PUSH(x) ((x) << S_TF_CORE_PUSH)
|
||||
|
||||
#define S_TF_CORE_FLUSH 28
|
||||
#define V_TF_CORE_FLUSH(x) ((x) << S_TF_CORE_FLUSH)
|
||||
|
||||
#define S_TF_RCV_COALESCE_ENABLE 29
|
||||
#define V_TF_RCV_COALESCE_ENABLE(x) ((x) << S_TF_RCV_COALESCE_ENABLE)
|
||||
|
||||
#define S_TF_RCV_COALESCE_PUSH 30
|
||||
#define V_TF_RCV_COALESCE_PUSH(x) ((x) << S_TF_RCV_COALESCE_PUSH)
|
||||
|
||||
#define S_TF_RCV_COALESCE_LAST_PSH 31
|
||||
#define V_TF_RCV_COALESCE_LAST_PSH(x) ((x) << S_TF_RCV_COALESCE_LAST_PSH)
|
||||
|
||||
#define S_TF_RCV_COALESCE_HEARTBEAT 32
|
||||
#define V_TF_RCV_COALESCE_HEARTBEAT(x) ((__u64)(x) << S_TF_RCV_COALESCE_HEARTBEAT)
|
||||
|
||||
#define S_TF_INIT 33
|
||||
#define V_TF_INIT(x) ((__u64)(x) << S_TF_INIT)
|
||||
|
||||
#define S_TF_ACTIVE_OPEN 34
|
||||
#define V_TF_ACTIVE_OPEN(x) ((__u64)(x) << S_TF_ACTIVE_OPEN)
|
||||
|
||||
#define S_TF_ASK_MODE 35
|
||||
#define V_TF_ASK_MODE(x) ((__u64)(x) << S_TF_ASK_MODE)
|
||||
|
||||
#define S_TF_MOD_SCHD_REASON0 36
|
||||
#define V_TF_MOD_SCHD_REASON0(x) ((__u64)(x) << S_TF_MOD_SCHD_REASON0)
|
||||
|
||||
#define S_TF_MOD_SCHD_REASON1 37
|
||||
#define V_TF_MOD_SCHD_REASON1(x) ((__u64)(x) << S_TF_MOD_SCHD_REASON1)
|
||||
|
||||
#define S_TF_MOD_SCHD_REASON2 38
|
||||
#define V_TF_MOD_SCHD_REASON2(x) ((__u64)(x) << S_TF_MOD_SCHD_REASON2)
|
||||
|
||||
#define S_TF_MOD_SCHD_TX 39
|
||||
#define V_TF_MOD_SCHD_TX(x) ((__u64)(x) << S_TF_MOD_SCHD_TX)
|
||||
|
||||
#define S_TF_MOD_SCHD_RX 40
|
||||
#define V_TF_MOD_SCHD_RX(x) ((__u64)(x) << S_TF_MOD_SCHD_RX)
|
||||
|
||||
#define S_TF_TIMER 41
|
||||
#define V_TF_TIMER(x) ((__u64)(x) << S_TF_TIMER)
|
||||
|
||||
#define S_TF_DACK_TIMER 42
|
||||
#define V_TF_DACK_TIMER(x) ((__u64)(x) << S_TF_DACK_TIMER)
|
||||
|
||||
#define S_TF_PEER_FIN 43
|
||||
#define V_TF_PEER_FIN(x) ((__u64)(x) << S_TF_PEER_FIN)
|
||||
|
||||
#define S_TF_TX_COMPACT 44
|
||||
#define V_TF_TX_COMPACT(x) ((__u64)(x) << S_TF_TX_COMPACT)
|
||||
|
||||
#define S_TF_RX_COMPACT 45
|
||||
#define V_TF_RX_COMPACT(x) ((__u64)(x) << S_TF_RX_COMPACT)
|
||||
|
||||
#define S_TF_RDMA_ERROR 46
|
||||
#define V_TF_RDMA_ERROR(x) ((__u64)(x) << S_TF_RDMA_ERROR)
|
||||
|
||||
#define S_TF_RDMA_FLM_ERROR 47
|
||||
#define V_TF_RDMA_FLM_ERROR(x) ((__u64)(x) << S_TF_RDMA_FLM_ERROR)
|
||||
|
||||
#define S_TF_TX_PDU_OUT 48
|
||||
#define V_TF_TX_PDU_OUT(x) ((__u64)(x) << S_TF_TX_PDU_OUT)
|
||||
|
||||
#define S_TF_RX_PDU_OUT 49
|
||||
#define V_TF_RX_PDU_OUT(x) ((__u64)(x) << S_TF_RX_PDU_OUT)
|
||||
|
||||
#define S_TF_DUPACK_COUNT_ODD 50
|
||||
#define V_TF_DUPACK_COUNT_ODD(x) ((__u64)(x) << S_TF_DUPACK_COUNT_ODD)
|
||||
|
||||
#define S_TF_FAST_RECOVERY 51
|
||||
#define V_TF_FAST_RECOVERY(x) ((__u64)(x) << S_TF_FAST_RECOVERY)
|
||||
|
||||
#define S_TF_RECV_SCALE 52
|
||||
#define V_TF_RECV_SCALE(x) ((__u64)(x) << S_TF_RECV_SCALE)
|
||||
|
||||
#define S_TF_RECV_TSTMP 53
|
||||
#define V_TF_RECV_TSTMP(x) ((__u64)(x) << S_TF_RECV_TSTMP)
|
||||
|
||||
#define S_TF_RECV_SACK 54
|
||||
#define V_TF_RECV_SACK(x) ((__u64)(x) << S_TF_RECV_SACK)
|
||||
|
||||
#define S_TF_PEND_CTL0 55
|
||||
#define V_TF_PEND_CTL0(x) ((__u64)(x) << S_TF_PEND_CTL0)
|
||||
|
||||
#define S_TF_PEND_CTL1 56
|
||||
#define V_TF_PEND_CTL1(x) ((__u64)(x) << S_TF_PEND_CTL1)
|
||||
|
||||
#define S_TF_PEND_CTL2 57
|
||||
#define V_TF_PEND_CTL2(x) ((__u64)(x) << S_TF_PEND_CTL2)
|
||||
|
||||
#define S_TF_IP_VERSION 58
|
||||
#define V_TF_IP_VERSION(x) ((__u64)(x) << S_TF_IP_VERSION)
|
||||
|
||||
#define S_TF_CCTRL_ECN 59
|
||||
#define V_TF_CCTRL_ECN(x) ((__u64)(x) << S_TF_CCTRL_ECN)
|
||||
|
||||
#define S_TF_LPBK 59
|
||||
#define V_TF_LPBK(x) ((__u64)(x) << S_TF_LPBK)
|
||||
|
||||
#define S_TF_CCTRL_ECE 60
|
||||
#define V_TF_CCTRL_ECE(x) ((__u64)(x) << S_TF_CCTRL_ECE)
|
||||
|
||||
#define S_TF_REWRITE_DMAC 60
|
||||
#define V_TF_REWRITE_DMAC(x) ((__u64)(x) << S_TF_REWRITE_DMAC)
|
||||
|
||||
#define S_TF_CCTRL_CWR 61
|
||||
#define V_TF_CCTRL_CWR(x) ((__u64)(x) << S_TF_CCTRL_CWR)
|
||||
|
||||
#define S_TF_REWRITE_SMAC 61
|
||||
#define V_TF_REWRITE_SMAC(x) ((__u64)(x) << S_TF_REWRITE_SMAC)
|
||||
|
||||
#define S_TF_CCTRL_RFR 62
|
||||
#define V_TF_CCTRL_RFR(x) ((__u64)(x) << S_TF_CCTRL_RFR)
|
||||
|
||||
#define S_TF_DDP_INDICATE_OUT 16
|
||||
#define V_TF_DDP_INDICATE_OUT(x) ((x) << S_TF_DDP_INDICATE_OUT)
|
||||
|
||||
#define S_TF_DDP_ACTIVE_BUF 17
|
||||
#define V_TF_DDP_ACTIVE_BUF(x) ((x) << S_TF_DDP_ACTIVE_BUF)
|
||||
|
||||
#define S_TF_DDP_OFF 18
|
||||
#define V_TF_DDP_OFF(x) ((x) << S_TF_DDP_OFF)
|
||||
|
||||
#define S_TF_DDP_WAIT_FRAG 19
|
||||
#define V_TF_DDP_WAIT_FRAG(x) ((x) << S_TF_DDP_WAIT_FRAG)
|
||||
|
||||
#define S_TF_DDP_BUF_INF 20
|
||||
#define V_TF_DDP_BUF_INF(x) ((x) << S_TF_DDP_BUF_INF)
|
||||
|
||||
#define S_TF_DDP_RX2TX 21
|
||||
#define V_TF_DDP_RX2TX(x) ((x) << S_TF_DDP_RX2TX)
|
||||
|
||||
#define S_TF_DDP_BUF0_VALID 24
|
||||
#define V_TF_DDP_BUF0_VALID(x) ((x) << S_TF_DDP_BUF0_VALID)
|
||||
|
||||
#define S_TF_DDP_BUF0_INDICATE 25
|
||||
#define V_TF_DDP_BUF0_INDICATE(x) ((x) << S_TF_DDP_BUF0_INDICATE)
|
||||
|
||||
#define S_TF_DDP_BUF0_FLUSH 26
|
||||
#define V_TF_DDP_BUF0_FLUSH(x) ((x) << S_TF_DDP_BUF0_FLUSH)
|
||||
|
||||
#define S_TF_DDP_PSHF_ENABLE_0 27
|
||||
#define V_TF_DDP_PSHF_ENABLE_0(x) ((x) << S_TF_DDP_PSHF_ENABLE_0)
|
||||
|
||||
#define S_TF_DDP_PUSH_DISABLE_0 28
|
||||
#define V_TF_DDP_PUSH_DISABLE_0(x) ((x) << S_TF_DDP_PUSH_DISABLE_0)
|
||||
|
||||
#define S_TF_DDP_PSH_NO_INVALIDATE0 29
|
||||
#define V_TF_DDP_PSH_NO_INVALIDATE0(x) ((x) << S_TF_DDP_PSH_NO_INVALIDATE0)
|
||||
|
||||
#define S_TF_DDP_BUF1_VALID 32
|
||||
#define V_TF_DDP_BUF1_VALID(x) ((__u64)(x) << S_TF_DDP_BUF1_VALID)
|
||||
|
||||
#define S_TF_DDP_BUF1_INDICATE 33
|
||||
#define V_TF_DDP_BUF1_INDICATE(x) ((__u64)(x) << S_TF_DDP_BUF1_INDICATE)
|
||||
|
||||
#define S_TF_DDP_BUF1_FLUSH 34
|
||||
#define V_TF_DDP_BUF1_FLUSH(x) ((__u64)(x) << S_TF_DDP_BUF1_FLUSH)
|
||||
|
||||
#define S_TF_DDP_PSHF_ENABLE_1 35
|
||||
#define V_TF_DDP_PSHF_ENABLE_1(x) ((__u64)(x) << S_TF_DDP_PSHF_ENABLE_1)
|
||||
|
||||
#define S_TF_DDP_PUSH_DISABLE_1 36
|
||||
#define V_TF_DDP_PUSH_DISABLE_1(x) ((__u64)(x) << S_TF_DDP_PUSH_DISABLE_1)
|
||||
|
||||
#define S_TF_DDP_PSH_NO_INVALIDATE1 37
|
||||
#define V_TF_DDP_PSH_NO_INVALIDATE1(x) ((__u64)(x) << S_TF_DDP_PSH_NO_INVALIDATE1)
|
||||
|
||||
#endif /* _T4_TCB_DEFS_H */
|
||||
5392
sys/dev/cxgbe/common/t4fw_interface.h
Normal file
5392
sys/dev/cxgbe/common/t4fw_interface.h
Normal file
File diff suppressed because it is too large
Load Diff
86
sys/dev/cxgbe/offload.h
Normal file
86
sys/dev/cxgbe/offload.h
Normal file
@ -0,0 +1,86 @@
|
||||
/*-
|
||||
* Copyright (c) 2010 Chelsio Communications, Inc.
|
||||
* All rights reserved.
|
||||
* Written by: Navdeep Parhar <np@FreeBSD.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __T4_OFFLOAD_H__
|
||||
#define __T4_OFFLOAD_H__
|
||||
|
||||
/*
|
||||
* Max # of ATIDs. The absolute HW max is 16K but we keep it lower.
|
||||
*/
|
||||
#define MAX_ATIDS 8192U
|
||||
|
||||
struct serv_entry {
|
||||
void *data;
|
||||
};
|
||||
|
||||
union aopen_entry {
|
||||
void *data;
|
||||
union aopen_entry *next;
|
||||
};
|
||||
|
||||
/*
|
||||
* Holds the size, base address, free list start, etc of the TID, server TID,
|
||||
* and active-open TID tables. The tables themselves are allocated dynamically.
|
||||
*/
|
||||
struct tid_info {
|
||||
void **tid_tab;
|
||||
unsigned int ntids;
|
||||
|
||||
struct serv_entry *stid_tab;
|
||||
unsigned long *stid_bmap;
|
||||
unsigned int nstids;
|
||||
unsigned int stid_base;
|
||||
|
||||
union aopen_entry *atid_tab;
|
||||
unsigned int natids;
|
||||
|
||||
unsigned int nftids;
|
||||
unsigned int ftid_base;
|
||||
|
||||
union aopen_entry *afree;
|
||||
unsigned int atids_in_use;
|
||||
|
||||
unsigned int stids_in_use;
|
||||
};
|
||||
|
||||
struct t4_range {
|
||||
unsigned int start;
|
||||
unsigned int size;
|
||||
};
|
||||
|
||||
struct t4_virt_res { /* virtualized HW resources */
|
||||
struct t4_range ddp;
|
||||
struct t4_range iscsi;
|
||||
struct t4_range stag;
|
||||
struct t4_range rq;
|
||||
struct t4_range pbl;
|
||||
};
|
||||
|
||||
#endif
|
||||
153
sys/dev/cxgbe/osdep.h
Normal file
153
sys/dev/cxgbe/osdep.h
Normal file
@ -0,0 +1,153 @@
|
||||
/*-
|
||||
* Copyright (c) 2010 Chelsio Communications, Inc.
|
||||
* All rights reserved.
|
||||
* Written by: Navdeep Parhar <np@FreeBSD.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __CXGBE_OSDEP_H_
|
||||
#define __CXGBE_OSDEP_H_
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
#include <sys/ctype.h>
|
||||
#include <sys/types.h>
|
||||
#include <sys/param.h>
|
||||
#include <sys/endian.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/syslog.h>
|
||||
#include <dev/pci/pcireg.h>
|
||||
|
||||
#define CH_ERR(adap, fmt, ...) log(LOG_ERR, fmt, ##__VA_ARGS__)
|
||||
#define CH_WARN(adap, fmt, ...) log(LOG_WARNING, fmt, ##__VA_ARGS__)
|
||||
#define CH_ALERT(adap, fmt, ...) log(LOG_ALERT, fmt, ##__VA_ARGS__)
|
||||
#define CH_WARN_RATELIMIT(adap, fmt, ...) log(LOG_WARNING, fmt, ##__VA_ARGS__)
|
||||
|
||||
typedef int8_t s8;
|
||||
typedef int16_t s16;
|
||||
typedef int32_t s32;
|
||||
typedef int64_t s64;
|
||||
typedef uint8_t u8;
|
||||
typedef uint16_t u16;
|
||||
typedef uint32_t u32;
|
||||
typedef uint64_t u64;
|
||||
typedef uint8_t __u8;
|
||||
typedef uint16_t __u16;
|
||||
typedef uint32_t __u32;
|
||||
typedef uint64_t __u64;
|
||||
typedef uint8_t __be8;
|
||||
typedef uint16_t __be16;
|
||||
typedef uint32_t __be32;
|
||||
typedef uint64_t __be64;
|
||||
|
||||
#if BYTE_ORDER == BIG_ENDIAN
|
||||
#define __BIG_ENDIAN_BITFIELD
|
||||
#elif BYTE_ORDER == LITTLE_ENDIAN
|
||||
#define __LITTLE_ENDIAN_BITFIELD
|
||||
#else
|
||||
#error "Must set BYTE_ORDER"
|
||||
#endif
|
||||
|
||||
typedef boolean_t bool;
|
||||
#define false FALSE
|
||||
#define true TRUE
|
||||
|
||||
#undef msleep
|
||||
#define msleep(x) DELAY((x) * 1000)
|
||||
#define mdelay(x) DELAY((x) * 1000)
|
||||
#define udelay(x) DELAY(x)
|
||||
|
||||
#define __devinit
|
||||
#define simple_strtoul strtoul
|
||||
#define DIV_ROUND_UP(x, y) howmany(x, y)
|
||||
|
||||
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
|
||||
|
||||
#define swab16(x) bswap16(x)
|
||||
#define swab32(x) bswap32(x)
|
||||
#define swab64(x) bswap64(x)
|
||||
#define le16_to_cpu(x) le16toh(x)
|
||||
#define le32_to_cpu(x) le32toh(x)
|
||||
#define le64_to_cpu(x) le64toh(x)
|
||||
#define cpu_to_le16(x) htole16(x)
|
||||
#define cpu_to_le32(x) htole32(x)
|
||||
#define cpu_to_le64(x) htole64(x)
|
||||
#define be16_to_cpu(x) be16toh(x)
|
||||
#define be32_to_cpu(x) be32toh(x)
|
||||
#define be64_to_cpu(x) be64toh(x)
|
||||
#define cpu_to_be16(x) htobe16(x)
|
||||
#define cpu_to_be32(x) htobe32(x)
|
||||
#define cpu_to_be64(x) htobe64(x)
|
||||
|
||||
#define SPEED_10 10
|
||||
#define SPEED_100 100
|
||||
#define SPEED_1000 1000
|
||||
#define SPEED_10000 10000
|
||||
#define DUPLEX_HALF 0
|
||||
#define DUPLEX_FULL 1
|
||||
#define AUTONEG_DISABLE 0
|
||||
#define AUTONEG_ENABLE 1
|
||||
|
||||
#define PCI_CAP_ID_VPD PCIY_VPD
|
||||
#define PCI_VPD_ADDR PCIR_VPD_ADDR
|
||||
#define PCI_VPD_ADDR_F 0x8000
|
||||
#define PCI_VPD_DATA PCIR_VPD_DATA
|
||||
|
||||
#define PCI_CAP_ID_EXP PCIY_EXPRESS
|
||||
#define PCI_EXP_DEVCTL PCIR_EXPRESS_DEVICE_CTL
|
||||
#define PCI_EXP_DEVCTL_PAYLOAD PCIM_EXP_CTL_MAX_PAYLOAD
|
||||
#define PCI_EXP_DEVCTL_READRQ PCIM_EXP_CTL_MAX_READ_REQUEST
|
||||
#define PCI_EXP_LNKCTL PCIR_EXPRESS_LINK_CTL
|
||||
#define PCI_EXP_LNKSTA PCIR_EXPRESS_LINK_STA
|
||||
#define PCI_EXP_LNKSTA_CLS PCIM_LINK_STA_SPEED
|
||||
#define PCI_EXP_LNKSTA_NLW PCIM_LINK_STA_WIDTH
|
||||
|
||||
static inline int
|
||||
ilog2(long x)
|
||||
{
|
||||
KASSERT(x > 0 && powerof2(x), ("%s: invalid arg %ld", __func__, x));
|
||||
|
||||
return (flsl(x) - 1);
|
||||
}
|
||||
|
||||
static inline char *
|
||||
strstrip(char *s)
|
||||
{
|
||||
char c, *r, *trim_at;
|
||||
|
||||
while (isspace(*s))
|
||||
s++;
|
||||
r = trim_at = s;
|
||||
|
||||
while ((c = *s++) != 0) {
|
||||
if (!isspace(c))
|
||||
trim_at = s;
|
||||
}
|
||||
*trim_at = 0;
|
||||
|
||||
return (r);
|
||||
}
|
||||
|
||||
#endif
|
||||
58
sys/dev/cxgbe/t4_ioctl.h
Normal file
58
sys/dev/cxgbe/t4_ioctl.h
Normal file
@ -0,0 +1,58 @@
|
||||
/*-
|
||||
* Copyright (c) 2011 Chelsio Communications, Inc.
|
||||
* All rights reserved.
|
||||
* Written by: Navdeep Parhar <np@FreeBSD.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __T4_IOCTL_H__
|
||||
#define __T4_IOCTL_H__
|
||||
|
||||
/*
|
||||
* Ioctl commands specific to this driver.
|
||||
*/
|
||||
enum {
|
||||
T4_GET32 = 0x40, /* read 32 bit register */
|
||||
T4_SET32, /* write 32 bit register */
|
||||
T4_REGDUMP, /* dump of all registers */
|
||||
};
|
||||
|
||||
struct t4_reg32 {
|
||||
uint32_t addr;
|
||||
uint32_t val;
|
||||
};
|
||||
|
||||
#define T4_REGDUMP_SIZE (160 * 1024)
|
||||
struct t4_regdump {
|
||||
uint32_t version;
|
||||
uint32_t len; /* bytes */
|
||||
uint8_t *data;
|
||||
};
|
||||
|
||||
#define CHELSIO_T4_GETREG32 _IOWR('f', T4_GET32, struct t4_reg32)
|
||||
#define CHELSIO_T4_SETREG32 _IOW('f', T4_SET32, struct t4_reg32)
|
||||
#define CHELSIO_T4_REGDUMP _IOWR('f', T4_REGDUMP, struct t4_regdump)
|
||||
#endif
|
||||
2747
sys/dev/cxgbe/t4_main.c
Normal file
2747
sys/dev/cxgbe/t4_main.c
Normal file
File diff suppressed because it is too large
Load Diff
2392
sys/dev/cxgbe/t4_sge.c
Normal file
2392
sys/dev/cxgbe/t4_sge.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -70,6 +70,7 @@ SUBDIR= ${_3dfx} \
|
||||
${_cs} \
|
||||
${_ctau} \
|
||||
${_cxgb} \
|
||||
cxgbe \
|
||||
${_cyclic} \
|
||||
dc \
|
||||
dcons \
|
||||
|
||||
16
sys/modules/cxgbe/Makefile
Normal file
16
sys/modules/cxgbe/Makefile
Normal file
@ -0,0 +1,16 @@
|
||||
#
|
||||
# $FreeBSD$
|
||||
#
|
||||
|
||||
CXGBE = ${.CURDIR}/../../dev/cxgbe
|
||||
.PATH: ${CXGBE} ${CXGBE}/common
|
||||
|
||||
KMOD = if_cxgbe
|
||||
SRCS = t4_main.c t4_sge.c
|
||||
SRCS+= t4_hw.c
|
||||
SRCS+= device_if.h bus_if.h pci_if.h
|
||||
SRCS+= opt_inet.h
|
||||
|
||||
CFLAGS+= -g -I${CXGBE}
|
||||
|
||||
.include <bsd.kmod.mk>
|
||||
@ -109,6 +109,7 @@ static struct _devname {
|
||||
NETWORK("cas", "Sun Cassini/Cassini+ or NS DP83065 Saturn Ethernet"),
|
||||
NETWORK("cue", "CATC USB Ethernet adapter"),
|
||||
NETWORK("cxgb", "Chelsio T3 10Gb Ethernet card"),
|
||||
NETWORK("cxgbe", "Chelsio T4 10Gb Ethernet card"),
|
||||
NETWORK("fpa", "DEC DEFPA PCI FDDI card"),
|
||||
NETWORK("sr", "SDL T1/E1 sync serial PCI card"),
|
||||
NETWORK("cc3i", "SDL HSSI sync serial PCI card"),
|
||||
|
||||
Loading…
Reference in New Issue
Block a user