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Updates for the RMI MIPS platform code

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- set cache_coherent_dma flag in cpuinfo for XLR, this will make sure that
  BUS_DMA_COHERENT flag is handled correctly in busdma_machdep.c
- iodi.c, call device_get_name() just once
- clear RMI specific EIRR while intializing CPUs
- remove debug print in intr_machdep.c
This commit is contained in:
jchandra 2010-09-01 17:35:31 +00:00
parent a9a1b47f1d
commit 54fb9c3510
4 changed files with 13 additions and 10 deletions
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7
sys/mips/rmi/intr_machdep.c
View File

@ -62,8 +62,10 @@ static int intrcnt_index;
void void
xlr_enable_irq(int irq) xlr_enable_irq(int irq)
{ {
uint64_t eimr;
write_c0_eimr64(read_c0_eimr64() | (1ULL << irq)); eimr = read_c0_eimr64();
write_c0_eimr64(eimr | (1ULL << irq));
} }
void void
@ -128,9 +130,6 @@ xlr_establish_intr(const char *name, driver_filter_t filt,
* FIXME locking - not needed now, because we do this only on * FIXME locking - not needed now, because we do this only on
* startup from CPU0 * startup from CPU0
*/ */
printf("[%s] Setup intr %d called on cpu %d (%d)\n", name, irq,
xlr_cpu_id(), PCPU_GET(cpuid));
src = &xlr_interrupts[irq]; src = &xlr_interrupts[irq];
ie = src->ie; ie = src->ie;
if (ie == NULL) { if (ie == NULL) {

11
sys/mips/rmi/iodi.c
View File

@ -95,7 +95,7 @@ bridge_pcmcia_ack(int irq)
static int static int
iodi_setup_intr(device_t dev, device_t child, iodi_setup_intr(device_t dev, device_t child,
struct resource *ires, int flags, driver_filter_t * filt, struct resource *ires, int flags, driver_filter_t *filt,
driver_intr_t *intr, void *arg, void **cookiep) driver_intr_t *intr, void *arg, void **cookiep)
{ {
const char *name = device_get_name(child); const char *name = device_get_name(child);
@ -130,6 +130,7 @@ iodi_alloc_resource(device_t bus, device_t child, int type, int *rid,
u_long start, u_long end, u_long count, u_int flags) u_long start, u_long end, u_long count, u_int flags)
{ {
struct resource *res = malloc(sizeof(*res), M_DEVBUF, M_WAITOK); struct resource *res = malloc(sizeof(*res), M_DEVBUF, M_WAITOK);
const char *name = device_get_name(child);
int unit; int unit;
#ifdef DEBUG #ifdef DEBUG
@ -151,7 +152,7 @@ iodi_alloc_resource(device_t bus, device_t child, int type, int *rid,
} }
#endif #endif
if (strcmp(device_get_name(child), "uart") == 0) { if (strcmp(name, "uart") == 0) {
if ((unit = device_get_unit(child)) == 0) { /* uart 0 */ if ((unit = device_get_unit(child)) == 0) { /* uart 0 */
res->r_bushandle = (xlr_io_base + XLR_IO_UART_0_OFFSET); res->r_bushandle = (xlr_io_base + XLR_IO_UART_0_OFFSET);
} else if (unit == 1) { } else if (unit == 1) {
@ -160,13 +161,13 @@ iodi_alloc_resource(device_t bus, device_t child, int type, int *rid,
printf("%s: Unknown uart unit\n", __FUNCTION__); printf("%s: Unknown uart unit\n", __FUNCTION__);
res->r_bustag = uart_bus_space_mem; res->r_bustag = uart_bus_space_mem;
} else if (strcmp(device_get_name(child), "ehci") == 0) { } else if (strcmp(name, "ehci") == 0) {
res->r_bushandle = MIPS_PHYS_TO_KSEG1(0x1ef24000); res->r_bushandle = MIPS_PHYS_TO_KSEG1(0x1ef24000);
res->r_bustag = rmi_pci_bus_space; res->r_bustag = rmi_pci_bus_space;
} else if (strcmp(device_get_name(child), "cfi") == 0) { } else if (strcmp(name, "cfi") == 0) {
res->r_bushandle = MIPS_PHYS_TO_KSEG1(0x1c000000); res->r_bushandle = MIPS_PHYS_TO_KSEG1(0x1c000000);
res->r_bustag = 0; res->r_bustag = 0;
} else if (strcmp(device_get_name(child), "ata") == 0) { } else if (strcmp(name, "ata") == 0) {
res->r_bushandle = MIPS_PHYS_TO_KSEG1(0x1d000000); res->r_bushandle = MIPS_PHYS_TO_KSEG1(0x1d000000);
res->r_bustag = rmi_pci_bus_space; /* byte swapping (not really PCI) */ res->r_bustag = rmi_pci_bus_space; /* byte swapping (not really PCI) */
} }

2
sys/mips/rmi/pic.h
View File

@ -189,7 +189,7 @@ pic_ack(int picintr)
{ {
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
xlr_write_reg(mmio, PIC_INT_ACK, 1 << picintr); xlr_write_reg(mmio, PIC_INT_ACK, 1U << picintr);
} }
static __inline static __inline

3
sys/mips/rmi/xlr_machdep.c
View File

@ -266,6 +266,7 @@ mips_init(void)
init_param2(physmem); init_param2(physmem);
mips_cpu_init(); mips_cpu_init();
cpuinfo.cache_coherent_dma = TRUE;
pmap_bootstrap(); pmap_bootstrap();
#ifdef DDB #ifdef DDB
kdb_init(); kdb_init();
@ -298,6 +299,7 @@ xlr_pic_init(void)
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
int i, level, irq; int i, level, irq;
write_c0_eimr64(0ULL);
mtx_init(&xlr_pic_lock, "pic", NULL, MTX_SPIN); mtx_init(&xlr_pic_lock, "pic", NULL, MTX_SPIN);
xlr_write_reg(mmio, PIC_CTRL, 0); xlr_write_reg(mmio, PIC_CTRL, 0);
@ -574,6 +576,7 @@ platform_init_ap(int cpuid)
stat |= MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT; stat |= MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT;
mips_wr_status(stat); mips_wr_status(stat);
write_c0_eimr64(0ULL);
xlr_enable_irq(IRQ_IPI); xlr_enable_irq(IRQ_IPI);
xlr_enable_irq(IRQ_TIMER); xlr_enable_irq(IRQ_TIMER);
if (xlr_thr_id() == 0) { if (xlr_thr_id() == 0) {