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Do a read-after-write to ensure the interrupt register update is flushed

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to the hardware.

The QCA HAL has a comment noting that if this isn't done, modifications
to AR_IMR_S2 before AR_IMR is flushed may produce spurious interrupts.

Obtained from:	QCA
This commit is contained in:
Adrian Chadd 2014-04-27 23:31:42 +00:00
parent 9febee763b
commit 552c550628
1 changed files with 3 additions and 0 deletions
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3
sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c
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@ -337,6 +337,9 @@ ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints)
/* Write the new IMR and store off our SW copy. */ /* Write the new IMR and store off our SW copy. */
HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask); HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask);
OS_REG_WRITE(ah, AR_IMR, mask); OS_REG_WRITE(ah, AR_IMR, mask);
/* Flush write */
(void) OS_REG_READ(ah, AR_IMR);
mask = OS_REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM | mask = OS_REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
AR_IMR_S2_DTIM | AR_IMR_S2_DTIM |
AR_IMR_S2_DTIMSYNC | AR_IMR_S2_DTIMSYNC |