From 552dafa9532f4fdba4d75f9f2eacabf4b5c6a501 Mon Sep 17 00:00:00 2001 From: ian Date: Sun, 26 Oct 2014 03:44:19 +0000 Subject: [PATCH] MFC r271550, r271591: Replace the imx5 and imx6 iomux drivers with a single common driver that uses the new fdt_pinctrl interface. --- sys/arm/freescale/imx/files.imx51 | 2 +- sys/arm/freescale/imx/files.imx53 | 2 +- sys/arm/freescale/imx/files.imx6 | 2 +- sys/arm/freescale/imx/imx51_iomux.c | 249 -------- sys/arm/freescale/imx/imx51_iomuxreg.h | 761 ----------------------- sys/arm/freescale/imx/imx6_iomux.c | 225 ------- sys/arm/freescale/imx/imx6_iomuxreg.h | 798 ------------------------- sys/arm/freescale/imx/imx_iomux.c | 282 +++++++++ sys/arm/freescale/imx/std.imx51 | 2 + sys/arm/freescale/imx/std.imx53 | 2 + sys/arm/freescale/imx/std.imx6 | 2 + 11 files changed, 291 insertions(+), 2036 deletions(-) delete mode 100644 sys/arm/freescale/imx/imx51_iomux.c delete mode 100644 sys/arm/freescale/imx/imx51_iomuxreg.h delete mode 100644 sys/arm/freescale/imx/imx6_iomux.c delete mode 100644 sys/arm/freescale/imx/imx6_iomuxreg.h create mode 100644 sys/arm/freescale/imx/imx_iomux.c diff --git a/sys/arm/freescale/imx/files.imx51 b/sys/arm/freescale/imx/files.imx51 index abb75564eaeb..e7442d1f9897 100644 --- a/sys/arm/freescale/imx/files.imx51 +++ b/sys/arm/freescale/imx/files.imx51 @@ -19,7 +19,7 @@ arm/freescale/imx/bus_space.c standard arm/freescale/imx/tzic.c standard # IOMUX - external pins multiplexor -arm/freescale/imx/imx51_iomux.c standard +arm/freescale/imx/imx_iomux.c standard # GPIO arm/freescale/imx/imx_gpio.c optional gpio diff --git a/sys/arm/freescale/imx/files.imx53 b/sys/arm/freescale/imx/files.imx53 index 2b47814fba80..8b8a79704f32 100644 --- a/sys/arm/freescale/imx/files.imx53 +++ b/sys/arm/freescale/imx/files.imx53 @@ -22,7 +22,7 @@ dev/uart/uart_dev_imx.c optional uart arm/freescale/imx/tzic.c standard # IOMUX - external pins multiplexor -arm/freescale/imx/imx51_iomux.c standard +arm/freescale/imx/imx_iomux.c standard # GPIO arm/freescale/imx/imx_gpio.c optional gpio diff --git a/sys/arm/freescale/imx/files.imx6 b/sys/arm/freescale/imx/files.imx6 index d535a83a7c8c..03c2f7e81e3b 100644 --- a/sys/arm/freescale/imx/files.imx6 +++ b/sys/arm/freescale/imx/files.imx6 @@ -20,11 +20,11 @@ arm/arm/mpcore_timer.c standard arm/freescale/fsl_ocotp.c standard arm/freescale/imx/imx6_anatop.c standard arm/freescale/imx/imx6_ccm.c standard -arm/freescale/imx/imx6_iomux.c standard arm/freescale/imx/imx6_machdep.c standard arm/freescale/imx/imx6_mp.c optional smp arm/freescale/imx/imx6_pl310.c standard arm/freescale/imx/imx_common.c standard +arm/freescale/imx/imx_iomux.c standard arm/freescale/imx/imx_machdep.c standard arm/freescale/imx/imx_gpt.c standard arm/freescale/imx/imx_gpio.c optional gpio diff --git a/sys/arm/freescale/imx/imx51_iomux.c b/sys/arm/freescale/imx/imx51_iomux.c deleted file mode 100644 index 1953b7a95831..000000000000 --- a/sys/arm/freescale/imx/imx51_iomux.c +++ /dev/null @@ -1,249 +0,0 @@ -/* $NetBSD: imx51_iomux.c,v 1.3 2012/04/15 09:51:31 bsh Exp $ */ - -/* - * Copyright (c) 2009, 2010 Genetec Corporation. All rights reserved. - * Written by Hashimoto Kenichi for Genetec Corporation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/*- - * Copyright (c) 2012, 2013 The FreeBSD Foundation - * All rights reserved. - * - * Portions of this software were developed by Oleksandr Rybalko - * under sponsorship from the FreeBSD Foundation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include -#include - -#include -#include "imx51_iomuxreg.h" - - -#define IOMUX_WRITE(_sc, _r, _v) \ - bus_write_4((_sc)->sc_res, (_r), (_v)) -#define IOMUX_READ(_sc, _r) \ - bus_read_4((_sc)->sc_res, (_r)) -#define IOMUX_SET(_sc, _r, _m) \ - IOMUX_WRITE((_sc), (_r), IOMUX_READ((_sc), (_r)) | (_m)) -#define IOMUX_CLEAR(_sc, _r, _m) \ - IOMUX_WRITE((_sc), (_r), IOMUX_READ((_sc), (_r)) & ~(_m)) - -struct iomux_softc { - struct resource *sc_res; - device_t sc_dev; -}; - -static int iomux_probe(device_t); -static int iomux_attach(device_t); - -static struct iomux_softc *iomuxsc = NULL; - -static struct resource_spec imx_iomux_spec[] = { - { SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Global registers */ - { -1, 0 } -}; - -static int -iomux_probe(device_t dev) -{ - - if (!ofw_bus_status_okay(dev)) - return (ENXIO); - - if (!ofw_bus_is_compatible(dev, "fsl,imx51-iomux") && - !ofw_bus_is_compatible(dev, "fsl,imx53-iomux")) - return (ENXIO); - - device_set_desc(dev, "Freescale i.MX51 IO pins multiplexor"); - return (BUS_PROBE_DEFAULT); -} - -static int -iomux_attach(device_t dev) -{ - struct iomux_softc * sc; - - sc = device_get_softc(dev); - - if (bus_alloc_resources(dev, imx_iomux_spec, &sc->sc_res)) { - device_printf(dev, "could not allocate resources\n"); - return (ENXIO); - } - - iomuxsc = sc; - - /* - * XXX: place to fetch all info about pinmuxing from loader data - * (FDT blob) and apply. Loader (1st one) must care about - * device-to-device difference. - */ - - return (0); -} - -static void -iomux_set_function_sub(struct iomux_softc *sc, uint32_t pin, uint32_t fn) -{ - bus_size_t mux_ctl_reg = IOMUX_PIN_TO_MUX_ADDRESS(pin); - - if (mux_ctl_reg != IOMUX_MUX_NONE) - IOMUX_WRITE(sc, mux_ctl_reg, fn); -} - -void -iomux_set_function(unsigned int pin, unsigned int fn) -{ - - if (iomuxsc == NULL) - return; - iomux_set_function_sub(iomuxsc, pin, fn); -} - -static void -iomux_set_pad_sub(struct iomux_softc *sc, uint32_t pin, uint32_t config) -{ - bus_size_t pad_ctl_reg = IOMUX_PIN_TO_PAD_ADDRESS(pin); - - if (pad_ctl_reg != IOMUX_PAD_NONE) - IOMUX_WRITE(sc, pad_ctl_reg, config); -} - -void -iomux_set_pad(unsigned int pin, unsigned int config) -{ - - if (iomuxsc == NULL) - return; - iomux_set_pad_sub(iomuxsc, pin, config); -} - -static uint32_t -iomux_get_pad_config_sub(struct iomux_softc *sc, uint32_t pin) -{ - bus_size_t pad_reg = IOMUX_PIN_TO_PAD_ADDRESS(pin); - uint32_t result; - - result = IOMUX_READ(sc, pad_reg); - - return(result); -} - -unsigned int -iomux_get_pad_config(unsigned int pin) -{ - - return(iomux_get_pad_config_sub(iomuxsc, pin)); -} - -uint32_t -imx_iomux_gpr_get(u_int regnum) -{ - - KASSERT(iomuxsc != NULL, ("imx_iomux_gpr_get() called before attach")); - KASSERT(regnum >= 0 && regnum <= 1, - ("imx_iomux_gpr_get bad regnum %u", regnum)); - return (IOMUX_READ(iomuxsc, IOMUXC_GPR0 + regnum)); -} - -void -imx_iomux_gpr_set(u_int regnum, uint32_t val) -{ - - KASSERT(iomuxsc != NULL, ("imx_iomux_gpr_set() called before attach")); - KASSERT(regnum >= 0 && regnum <= 1, - ("imx_iomux_gpr_set bad regnum %u", regnum)); - IOMUX_WRITE(iomuxsc, IOMUXC_GPR0 + regnum, val); -} - -void -imx_iomux_gpr_set_masked(u_int regnum, uint32_t clrbits, uint32_t setbits) -{ - uint32_t val; - - KASSERT(iomuxsc != NULL, - ("imx_iomux_gpr_set_masked called before attach")); - KASSERT(regnum >= 0 && regnum <= 1, - ("imx_iomux_gpr_set_masked bad regnum %u", regnum)); - - val = IOMUX_READ(iomuxsc, IOMUXC_GPR0 + regnum); - val = (val & ~clrbits) | setbits; - IOMUX_WRITE(iomuxsc, IOMUXC_GPR0 + regnum, val); -} - -static device_method_t imx_iomux_methods[] = { - DEVMETHOD(device_probe, iomux_probe), - DEVMETHOD(device_attach, iomux_attach), - - DEVMETHOD_END -}; - -static driver_t imx_iomux_driver = { - "imx_iomux", - imx_iomux_methods, - sizeof(struct iomux_softc), -}; - -static devclass_t imx_iomux_devclass; - -EARLY_DRIVER_MODULE(imx_iomux, simplebus, imx_iomux_driver, - imx_iomux_devclass, 0, 0, BUS_PASS_CPU + BUS_PASS_ORDER_LATE); - diff --git a/sys/arm/freescale/imx/imx51_iomuxreg.h b/sys/arm/freescale/imx/imx51_iomuxreg.h deleted file mode 100644 index 1e90ffe58b06..000000000000 --- a/sys/arm/freescale/imx/imx51_iomuxreg.h +++ /dev/null @@ -1,761 +0,0 @@ -/* - * This file was generated automatically from PDF file by mkiomuxreg_imx51.rb - * - */ - -/*- - * Copyright (c) 2012, 2013 The FreeBSD Foundation - * All rights reserved. - * - * Portions of this software were developed by Oleksandr Rybalko - * under sponsorship from the FreeBSD Foundation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ - -#ifndef _IMX51_IOMUXREG_H -#define _IMX51_IOMUXREG_H - -#define IOMUXC_MUX_CTL 0x001c /* multiplex control */ -#define IOMUX_CONFIG_SION (1 << 4) -#define IOMUX_CONFIG_ALT0 (0) -#define IOMUX_CONFIG_ALT1 (1) -#define IOMUX_CONFIG_ALT2 (2) -#define IOMUX_CONFIG_ALT3 (3) -#define IOMUX_CONFIG_ALT4 (4) -#define IOMUX_CONFIG_ALT5 (5) -#define IOMUX_CONFIG_ALT6 (6) -#define IOMUX_CONFIG_ALT7 (7) -#define IOMUXC_PAD_CTL 0x03f0 /* pad control */ -#define PAD_CTL_HVE (1 << 13) -#define PAD_CTL_DDR_INPUT (1 << 9) -#define PAD_CTL_HYS (1 << 8) -#define PAD_CTL_PKE (1 << 7) -#define PAD_CTL_PUE (1 << 6) -#define PAD_CTL_PULL (PAD_CTL_PKE|PAD_CTL_PUE) -#define PAD_CTL_KEEPER (PAD_CTL_PKE|0) -#define PAD_CTL_PUS_100K_PD (0x0 << 4) -#define PAD_CTL_PUS_47K_PU (0x1 << 4) -#define PAD_CTL_PUS_100K_PU (0x2 << 4) -#define PAD_CTL_PUS_22K_PU (0x3 << 4) -#define PAD_CTL_ODE (1 << 3) /* opendrain */ -#define PAD_CTL_DSE_LOW (0x0 << 1) -#define PAD_CTL_DSE_MID (0x1 << 1) -#define PAD_CTL_DSE_HIGH (0x2 << 1) -#define PAD_CTL_DSE_MAX (0x3 << 1) -#define PAD_CTL_SRE (1 << 0) -#define IOMUXC_INPUT_CTL 0x08c4 /* input control */ -#define INPUT_DAISY_0 0 -#define INPUT_DAISY_1 1 -#define INPUT_DAISY_2 2 -#define INPUT_DAISY_3 3 -#define INPUT_DAISY_4 4 -#define INPUT_DAISY_5 5 -#define INPUT_DAISY_6 6 -#define INPUT_DAISY_7 7 - -/* - * IOMUX index - */ -#define IOMUX_PIN_TO_MUX_ADDRESS(pin) (((pin) >> 16) & 0xffff) -#define IOMUX_PIN_TO_PAD_ADDRESS(pin) (((pin) >> 0) & 0xffff) - -#define IOMUX_PIN(mux_adr, pad_adr) \ - (((mux_adr) << 16) | (((pad_adr) << 0))) -#define IOMUX_MUX_NONE 0xffff -#define IOMUX_PAD_NONE 0xffff - -/* register offset address */ -#define IOMUXC_GPR0 0x0000 -#define IOMUXC_GPR1 0x0004 -#define IOMUXC_OBSERVE_MUX_0 0x0008 -#define IOMUXC_OBSERVE_MUX_1 0x000c -#define IOMUXC_OBSERVE_MUX_2 0x0010 -#define IOMUXC_OBSERVE_MUX_3 0x0014 -#define IOMUXC_OBSERVE_MUX_4 0x0018 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA0 0x001c -#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA1 0x0020 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA2 0x0024 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA3 0x0028 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA4 0x002c -#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA5 0x0030 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA6 0x0034 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA7 0x0038 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA8 0x003c -#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA9 0x0040 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA10 0x0044 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA11 0x0048 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA12 0x004c -#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA13 0x0050 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA14 0x0054 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA15 0x0058 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_D16 0x005c -#define IOMUXC_SW_MUX_CTL_PAD_EIM_D17 0x0060 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_D18 0x0064 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_D19 0x0068 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_D20 0x006c -#define IOMUXC_SW_MUX_CTL_PAD_EIM_D21 0x0070 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_D22 0x0074 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_D23 0x0078 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_D24 0x007c -#define IOMUXC_SW_MUX_CTL_PAD_EIM_D25 0x0080 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_D26 0x0084 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_D27 0x0088 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_D28 0x008c -#define IOMUXC_SW_MUX_CTL_PAD_EIM_D29 0x0090 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_D30 0x0094 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_D31 0x0098 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_A16 0x009c -#define IOMUXC_SW_MUX_CTL_PAD_EIM_A17 0x00a0 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_A18 0x00a4 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_A19 0x00a8 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_A20 0x00ac -#define IOMUXC_SW_MUX_CTL_PAD_EIM_A21 0x00b0 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_A22 0x00b4 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_A23 0x00b8 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_A24 0x00bc -#define IOMUXC_SW_MUX_CTL_PAD_EIM_A25 0x00c0 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_A26 0x00c4 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_A27 0x00c8 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB0 0x00cc -#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB1 0x00d0 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB2 0x00d4 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB3 0x00d8 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_OE 0x00dc -#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS0 0x00e0 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS1 0x00e4 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS2 0x00e8 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS3 0x00ec -#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS4 0x00f0 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS5 0x00f4 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_DTACK 0x00f8 -#define IOMUXC_SW_MUX_CTL_PAD_EIM_LBA 0x00fc -#define IOMUXC_SW_MUX_CTL_PAD_EIM_CRE 0x0100 -#define IOMUXC_SW_MUX_CTL_PAD_DRAM_CS1 0x0104 -#define IOMUXC_SW_MUX_CTL_PAD_NANDF_WE_B 0x0108 -#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RE_B 0x010c -#define IOMUXC_SW_MUX_CTL_PAD_NANDF_ALE 0x0110 -#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CLE 0x0114 -#define IOMUXC_SW_MUX_CTL_PAD_NANDF_WP_B 0x0118 -#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB0 0x011c -#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB1 0x0120 -#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB2 0x0124 -#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB3 0x0128 -#define IOMUXC_SW_MUX_CTL_PAD_GPIO_NAND 0x012c -#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS0 0x0130 -#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS1 0x0134 -#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS2 0x0138 -#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS3 0x013c -#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS4 0x0140 -#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS5 0x0144 -#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS6 0x0148 -#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS7 0x014c -#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RDY_INT 0x0150 -#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D15 0x0154 -#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D14 0x0158 -#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D13 0x015c -#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D12 0x0160 -#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D11 0x0164 -#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D10 0x0168 -#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D9 0x016c -#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D8 0x0170 -#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D7 0x0174 -#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D6 0x0178 -#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D5 0x017c -#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D4 0x0180 -#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D3 0x0184 -#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D2 0x0188 -#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D1 0x018c -#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D0 0x0190 -#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D8 0x0194 -#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D9 0x0198 -#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D10 0x019c -#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D11 0x01a0 -#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D12 0x01a4 -#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D13 0x01a8 -#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D14 0x01ac -#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D15 0x01b0 -#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D16 0x01b4 -#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D17 0x01b8 -#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D18 0x01bc -#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D19 0x01c0 -#define IOMUXC_SW_MUX_CTL_PAD_CSI1_VSYNC 0x01c4 -#define IOMUXC_SW_MUX_CTL_PAD_CSI1_HSYNC 0x01c8 -#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D12 0x01cc -#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D13 0x01d0 -#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D14 0x01d4 -#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D15 0x01d8 -#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D16 0x01dc -#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D17 0x01e0 -#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D18 0x01e4 -#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D19 0x01e8 -#define IOMUXC_SW_MUX_CTL_PAD_CSI2_VSYNC 0x01ec -#define IOMUXC_SW_MUX_CTL_PAD_CSI2_HSYNC 0x01f0 -#define IOMUXC_SW_MUX_CTL_PAD_CSI2_PIXCLK 0x01f4 -#define IOMUXC_SW_MUX_CTL_PAD_I2C1_CLK 0x01f8 -#define IOMUXC_SW_MUX_CTL_PAD_I2C1_DAT 0x01fc -#define IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_TXD 0x0200 -#define IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_RXD 0x0204 -#define IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_CK 0x0208 -#define IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_FS 0x020c -#define IOMUXC_SW_MUX_CTL_PAD_CSPI1_MOSI 0x0210 -#define IOMUXC_SW_MUX_CTL_PAD_CSPI1_MISO 0x0214 -#define IOMUXC_SW_MUX_CTL_PAD_CSPI1_SS0 0x0218 -#define IOMUXC_SW_MUX_CTL_PAD_CSPI1_SS1 0x021c -#define IOMUXC_SW_MUX_CTL_PAD_CSPI1_RDY 0x0220 -#define IOMUXC_SW_MUX_CTL_PAD_CSPI1_SCLK 0x0224 -#define IOMUXC_SW_MUX_CTL_PAD_UART1_RXD 0x0228 -#define IOMUXC_SW_MUX_CTL_PAD_UART1_TXD 0x022c -#define IOMUXC_SW_MUX_CTL_PAD_UART1_RTS 0x0230 -#define IOMUXC_SW_MUX_CTL_PAD_UART1_CTS 0x0234 -#define IOMUXC_SW_MUX_CTL_PAD_UART2_RXD 0x0238 -#define IOMUXC_SW_MUX_CTL_PAD_UART2_TXD 0x023c -#define IOMUXC_SW_MUX_CTL_PAD_UART3_RXD 0x0240 -#define IOMUXC_SW_MUX_CTL_PAD_UART3_TXD 0x0244 -#define IOMUXC_SW_MUX_CTL_PAD_OWIRE_LINE 0x0248 -#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0 0x024c -#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1 0x0250 -#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2 0x0254 -#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3 0x0258 -#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0 0x025c -#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1 0x0260 -#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2 0x0264 -#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3 0x0268 -#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4 0x026c -#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL5 0x0270 -#define IOMUXC_SW_MUX_CTL_PAD_JTAG_DE_B 0x0274 -#define IOMUXC_SW_MUX_CTL_PAD_USBH1_CLK 0x0278 -#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DIR 0x027c -#define IOMUXC_SW_MUX_CTL_PAD_USBH1_STP 0x0280 -#define IOMUXC_SW_MUX_CTL_PAD_USBH1_NXT 0x0284 -#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA0 0x0288 -#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA1 0x028c -#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA2 0x0290 -#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA3 0x0294 -#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA4 0x0298 -#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA5 0x029c -#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA6 0x02a0 -#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA7 0x02a4 -#define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN11 0x02a8 -#define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN12 0x02ac -#define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN13 0x02b0 -#define IOMUXC_SW_MUX_CTL_PAD_DI1_D0_CS 0x02b4 -#define IOMUXC_SW_MUX_CTL_PAD_DI1_D1_CS 0x02b8 -#define IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_DIN 0x02bc -#define IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_DIO 0x02c0 -#define IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_CLK 0x02c4 -#define IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_RS 0x02c8 -#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT0 0x02cc -#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT1 0x02d0 -#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT2 0x02d4 -#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT3 0x02d8 -#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT4 0x02dc -#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT5 0x02e0 -#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT6 0x02e4 -#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT7 0x02e8 -#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT8 0x02ec -#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT9 0x02f0 -#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT10 0x02f4 -#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT11 0x02f8 -#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT12 0x02fc -#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT13 0x0300 -#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT14 0x0304 -#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT15 0x0308 -#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT16 0x030c -#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT17 0x0310 -#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT18 0x0314 -#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT19 0x0318 -#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT20 0x031c -#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT21 0x0320 -#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT22 0x0324 -#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT23 0x0328 -#define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN3 0x032c -#define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN2 0x0330 -#define IOMUXC_SW_MUX_CTL_PAD_DI_GP1 0x0334 -#define IOMUXC_SW_MUX_CTL_PAD_DI_GP2 0x0338 -#define IOMUXC_SW_MUX_CTL_PAD_DI_GP3 0x033c -#define IOMUXC_SW_MUX_CTL_PAD_DI2_PIN4 0x0340 -#define IOMUXC_SW_MUX_CTL_PAD_DI2_PIN2 0x0344 -#define IOMUXC_SW_MUX_CTL_PAD_DI2_PIN3 0x0348 -#define IOMUXC_SW_MUX_CTL_PAD_DI2_DISP_CLK 0x034c -#define IOMUXC_SW_MUX_CTL_PAD_DI_GP4 0x0350 -#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT0 0x0354 -#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT1 0x0358 -#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT2 0x035c -#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT3 0x0360 -#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT4 0x0364 -#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT5 0x0368 -#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT6 0x036c -#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT7 0x0370 -#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT8 0x0374 -#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT9 0x0378 -#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT10 0x037c -#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT11 0x0380 -#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT12 0x0384 -#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT13 0x0388 -#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT14 0x038c -#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT15 0x0390 -#define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD 0x0394 -#define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK 0x0398 -#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 0x039c -#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 0x03a0 -#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 0x03a4 -#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 0x03a8 -#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_0 0x03ac -#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_1 0x03b0 -#define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD 0x03b4 -#define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK 0x03b8 -#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 0x03bc -#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 0x03c0 -#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 0x03c4 -#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 0x03c8 -#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_2 0x03cc -#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_3 0x03d0 -#define IOMUXC_SW_MUX_CTL_PAD_PMIC_INT_REQ 0x03d4 -#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_4 0x03d8 -#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_5 0x03dc -#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_6 0x03e0 -#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_7 0x03e4 -#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_8 0x03e8 -#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_9 0x03ec -#define IOMUXC_SW_PAD_CTL_PAD_EIM_D16 0x03f0 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_D17 0x03f4 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_D18 0x03f8 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_D19 0x03fc -#define IOMUXC_SW_PAD_CTL_PAD_EIM_D20 0x0400 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_D21 0x0404 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_D22 0x0408 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_D23 0x040c -#define IOMUXC_SW_PAD_CTL_PAD_EIM_D24 0x0410 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_D25 0x0414 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_D26 0x0418 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_D27 0x041c -#define IOMUXC_SW_PAD_CTL_PAD_EIM_D28 0x0420 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_D29 0x0424 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_D30 0x0428 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_D31 0x042c -#define IOMUXC_SW_PAD_CTL_PAD_EIM_A16 0x0430 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_A17 0x0434 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_A18 0x0438 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_A19 0x043c -#define IOMUXC_SW_PAD_CTL_PAD_EIM_A20 0x0440 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_A21 0x0444 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_A22 0x0448 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_A23 0x044c -#define IOMUXC_SW_PAD_CTL_PAD_EIM_A24 0x0450 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_A25 0x0454 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_A26 0x0458 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_A27 0x045c -#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB0 0x0460 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB1 0x0464 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB2 0x0468 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB3 0x046c -#define IOMUXC_SW_PAD_CTL_PAD_EIM_OE 0x0470 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS0 0x0474 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS1 0x0478 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS2 0x047c -#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS3 0x0480 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS4 0x0484 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS5 0x0488 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_DTACK 0x048c -#define IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT 0x0490 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_LBA 0x0494 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK 0x0498 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_RW 0x049c -#define IOMUXC_SW_PAD_CTL_PAD_EIM_CRE 0x04a0 -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS 0x04a4 -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS 0x04a8 -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE 0x04ac -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 0x04b0 -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 0x04b4 -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK 0x04b8 -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 0x04bc -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 0x04c0 -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 0x04c4 -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 0x04c8 -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0 0x04cc -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1 0x04d0 -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x04d4 -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x04d8 -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 0x04dc -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 0x04e0 -#define IOMUXC_SW_PAD_CTL_PAD_NANDF_WE_B 0x04e4 -#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RE_B 0x04e8 -#define IOMUXC_SW_PAD_CTL_PAD_NANDF_ALE 0x04ec -#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CLE 0x04f0 -#define IOMUXC_SW_PAD_CTL_PAD_NANDF_WP_B 0x04f4 -#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB0 0x04f8 -#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB1 0x04fc -#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB2 0x0500 -#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB3 0x0504 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_SDBA2 0x0508 -#define IOMUXC_SW_PAD_CTL_PAD_EIM_SDODT1 0x050c -#define IOMUXC_SW_PAD_CTL_PAD_EIM_SDODT0 0x0510 -#define IOMUXC_SW_PAD_CTL_PAD_GPIO_NAND 0x0514 -#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS0 0x0518 -#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS1 0x051c -#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS2 0x0520 -#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS3 0x0524 -#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS4 0x0528 -#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS5 0x052c -#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS6 0x0530 -#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS7 0x0534 -#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RDY_INT 0x0538 -#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D15 0x053c -#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D14 0x0540 -#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D13 0x0544 -#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D12 0x0548 -#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D11 0x054c -#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D10 0x0550 -#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D9 0x0554 -#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D8 0x0558 -#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D7 0x055c -#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D6 0x0560 -#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D5 0x0564 -#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D4 0x0568 -#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D3 0x056c -#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D2 0x0570 -#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D1 0x0574 -#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D0 0x0578 -#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D8 0x057c -#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D9 0x0580 -#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D10 0x0584 -#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D11 0x0588 -#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D12 0x058c -#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D13 0x0590 -#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D14 0x0594 -#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D15 0x0598 -#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D16 0x059c -#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D17 0x05a0 -#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D18 0x05a4 -#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D19 0x05a8 -#define IOMUXC_SW_PAD_CTL_PAD_CSI1_VSYNC 0x05ac -#define IOMUXC_SW_PAD_CTL_PAD_CSI1_HSYNC 0x05b0 -#define IOMUXC_SW_PAD_CTL_PAD_CSI1_PIXCLK 0x05b4 -#define IOMUXC_SW_PAD_CTL_PAD_CSI1_MCLK 0x05b8 -#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D12 0x05bc -#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D13 0x05c0 -#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D14 0x05c4 -#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D15 0x05c8 -#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D16 0x05cc -#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D17 0x05d0 -#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D18 0x05d4 -#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D19 0x05d8 -#define IOMUXC_SW_PAD_CTL_PAD_CSI2_VSYNC 0x05dc -#define IOMUXC_SW_PAD_CTL_PAD_CSI2_HSYNC 0x05e0 -#define IOMUXC_SW_PAD_CTL_PAD_CSI2_PIXCLK 0x05e4 -#define IOMUXC_SW_PAD_CTL_PAD_I2C1_CLK 0x05e8 -#define IOMUXC_SW_PAD_CTL_PAD_I2C1_DAT 0x05ec -#define IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_TXD 0x05f0 -#define IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_RXD 0x05f4 -#define IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_CK 0x05f8 -#define IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_FS 0x05fc -#define IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI 0x0600 -#define IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO 0x0604 -#define IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 0x0608 -#define IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 0x060c -#define IOMUXC_SW_PAD_CTL_PAD_CSPI1_RDY 0x0610 -#define IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK 0x0614 -#define IOMUXC_SW_PAD_CTL_PAD_UART1_RXD 0x0618 -#define IOMUXC_SW_PAD_CTL_PAD_UART1_TXD 0x061c -#define IOMUXC_SW_PAD_CTL_PAD_UART1_RTS 0x0620 -#define IOMUXC_SW_PAD_CTL_PAD_UART1_CTS 0x0624 -#define IOMUXC_SW_PAD_CTL_PAD_UART2_RXD 0x0628 -#define IOMUXC_SW_PAD_CTL_PAD_UART2_TXD 0x062c -#define IOMUXC_SW_PAD_CTL_PAD_UART3_RXD 0x0630 -#define IOMUXC_SW_PAD_CTL_PAD_UART3_TXD 0x0634 -#define IOMUXC_SW_PAD_CTL_PAD_OWIRE_LINE 0x0638 -#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0 0x063c -#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1 0x0640 -#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2 0x0644 -#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3 0x0648 -#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0 0x064c -#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1 0x0650 -#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2 0x0654 -#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3 0x0658 -#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4 0x065c -#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL5 0x0660 -#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK 0x0664 -#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS 0x0668 -#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI 0x066c -#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB 0x0670 -#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD 0x0674 -#define IOMUXC_SW_PAD_CTL_PAD_USBH1_CLK 0x0678 -#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DIR 0x067c -#define IOMUXC_SW_PAD_CTL_PAD_USBH1_STP 0x0680 -#define IOMUXC_SW_PAD_CTL_PAD_USBH1_NXT 0x0684 -#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA0 0x0688 -#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA1 0x068c -#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA2 0x0690 -#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA3 0x0694 -#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA4 0x0698 -#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA5 0x069c -#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA6 0x06a0 -#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA7 0x06a4 -#define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 0x06a8 -#define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN12 0x06ac -#define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN13 0x06b0 -#define IOMUXC_SW_PAD_CTL_PAD_DI1_D0_CS 0x06b4 -#define IOMUXC_SW_PAD_CTL_PAD_DI1_D1_CS 0x06b8 -#define IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_DIN 0x06bc -#define IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_DIO 0x06c0 -#define IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_CLK 0x06c4 -#define IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_RS 0x06c8 -#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT0 0x06cc -#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT1 0x06d0 -#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT2 0x06d4 -#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT3 0x06d8 -#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT4 0x06dc -#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT5 0x06e0 -#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT6 0x06e4 -#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT7 0x06e8 -#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT8 0x06ec -#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT9 0x06f0 -#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT10 0x06f4 -#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT11 0x06f8 -#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT12 0x06fc -#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT13 0x0700 -#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT14 0x0704 -#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT15 0x0708 -#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT16 0x070c -#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT17 0x0710 -#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT18 0x0714 -#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT19 0x0718 -#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT20 0x071c -#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT21 0x0720 -#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT22 0x0724 -#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT23 0x0728 -#define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN3 0x072c -#define IOMUXC_SW_PAD_CTL_PAD_DI1_DISP_CLK 0x0730 -#define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN2 0x0734 -#define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN15 0x0738 -#define IOMUXC_SW_PAD_CTL_PAD_DI_GP1 0x073c -#define IOMUXC_SW_PAD_CTL_PAD_DI_GP2 0x0740 -#define IOMUXC_SW_PAD_CTL_PAD_DI_GP3 0x0744 -#define IOMUXC_SW_PAD_CTL_PAD_DI2_PIN4 0x0748 -#define IOMUXC_SW_PAD_CTL_PAD_DI2_PIN2 0x074c -#define IOMUXC_SW_PAD_CTL_PAD_DI2_PIN3 0x0750 -#define IOMUXC_SW_PAD_CTL_PAD_DI2_DISP_CLK 0x0754 -#define IOMUXC_SW_PAD_CTL_PAD_DI_GP4 0x0758 -#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT0 0x075c -#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT1 0x0760 -#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT2 0x0764 -#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT3 0x0768 -#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT4 0x076c -#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT5 0x0770 -#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT6 0x0774 -#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT7 0x0778 -#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT8 0x077c -#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT9 0x0780 -#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT10 0x0784 -#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT11 0x0788 -#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT12 0x078c -#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT13 0x0790 -#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT14 0x0794 -#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT15 0x0798 -#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD 0x079c -#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK 0x07a0 -#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 0x07a4 -#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 0x07a8 -#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 0x07ac -#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 0x07b0 -#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_0 0x07b4 -#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_1 0x07b8 -#define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD 0x07bc -#define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK 0x07c0 -#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 0x07c4 -#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 0x07c8 -#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 0x07cc -#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 0x07d0 -#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_2 0x07d4 -#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_3 0x07d8 -#define IOMUXC_SW_PAD_CTL_PAD_RESET_IN_B 0x07dc -#define IOMUXC_SW_PAD_CTL_PAD_POR_B 0x07e0 -#define IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1 0x07e4 -#define IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0 0x07e8 -#define IOMUXC_SW_PAD_CTL_PAD_PMIC_RDY 0x07ec -#define IOMUXC_SW_PAD_CTL_PAD_CKIL 0x07f0 -#define IOMUXC_SW_PAD_CTL_PAD_PMIC_STBY_REQ 0x07f4 -#define IOMUXC_SW_PAD_CTL_PAD_PMIC_ON_REQ 0x07f8 -#define IOMUXC_SW_PAD_CTL_PAD_PMIC_INT_REQ 0x07fc -#define IOMUXC_SW_PAD_CTL_PAD_CLK_SS 0x0800 -#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_4 0x0804 -#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_5 0x0808 -#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_6 0x080c -#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_7 0x0810 -#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_8 0x0814 -#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_9 0x0818 -#define IOMUXC_SW_PAD_CTL_GRP_CSI2_PKE0 0x081c -#define IOMUXC_SW_PAD_CTL_GRP_DDRPKS 0x0820 -#define IOMUXC_SW_PAD_CTL_GRP_EIM_SR1 0x0824 -#define IOMUXC_SW_PAD_CTL_GRP_DISP2_PKE0 0x0828 -#define IOMUXC_SW_PAD_CTL_GRP_DRAM_B4 0x082c -#define IOMUXC_SW_PAD_CTL_GRP_INDDR 0x0830 -#define IOMUXC_SW_PAD_CTL_GRP_EIM_SR2 0x0834 -#define IOMUXC_SW_PAD_CTL_GRP_PKEDDR 0x0838 -#define IOMUXC_SW_PAD_CTL_GRP_DDR_A0 0x083c -#define IOMUXC_SW_PAD_CTL_GRP_EMI_PKE0 0x0840 -#define IOMUXC_SW_PAD_CTL_GRP_EIM_SR3 0x0844 -#define IOMUXC_SW_PAD_CTL_GRP_DDR_A1 0x0848 -#define IOMUXC_SW_PAD_CTL_GRP_DDRAPUS 0x084c -#define IOMUXC_SW_PAD_CTL_GRP_EIM_SR4 0x0850 -#define IOMUXC_SW_PAD_CTL_GRP_EMI_SR5 0x0854 -#define IOMUXC_SW_PAD_CTL_GRP_EMI_SR6 0x0858 -#define IOMUXC_SW_PAD_CTL_GRP_HYSDDR0 0x085c -#define IOMUXC_SW_PAD_CTL_GRP_CSI1_PKE0 0x0860 -#define IOMUXC_SW_PAD_CTL_GRP_HYSDDR1 0x0864 -#define IOMUXC_SW_PAD_CTL_GRP_DISP1_PKE0 0x0868 -#define IOMUXC_SW_PAD_CTL_GRP_HYSDDR2 0x086c -#define IOMUXC_SW_PAD_CTL_GRP_HVDDR 0x0870 -#define IOMUXC_SW_PAD_CTL_GRP_HYSDDR3 0x0874 -#define IOMUXC_SW_PAD_CTL_GRP_DRAM_SR_B0 0x0878 -#define IOMUXC_SW_PAD_CTL_GRP_DDRAPKS 0x087c -#define IOMUXC_SW_PAD_CTL_GRP_DRAM_SR_B1 0x0880 -#define IOMUXC_SW_PAD_CTL_GRP_DDRPUS 0x0884 -#define IOMUXC_SW_PAD_CTL_GRP_EIM_DS1 0x0888 -#define IOMUXC_SW_PAD_CTL_GRP_DRAM_SR_B2 0x088c -#define IOMUXC_SW_PAD_CTL_GRP_PKEADDR 0x0890 -#define IOMUXC_SW_PAD_CTL_GRP_EIM_DS2 0x0894 -#define IOMUXC_SW_PAD_CTL_GRP_EIM_DS3 0x0898 -#define IOMUXC_SW_PAD_CTL_GRP_DRAM_SR_B4 0x089c -#define IOMUXC_SW_PAD_CTL_GRP_INMODE1 0x08a0 -#define IOMUXC_SW_PAD_CTL_GRP_DRAM_B0 0x08a4 -#define IOMUXC_SW_PAD_CTL_GRP_EIM_DS4 0x08a8 -#define IOMUXC_SW_PAD_CTL_GRP_DRAM_B1 0x08ac -#define IOMUXC_SW_PAD_CTL_GRP_DDR_SR_A0 0x08b0 -#define IOMUXC_SW_PAD_CTL_GRP_EMI_DS5 0x08b4 -#define IOMUXC_SW_PAD_CTL_GRP_DRAM_B2 0x08b8 -#define IOMUXC_SW_PAD_CTL_GRP_DDR_SR_A1 0x08bc -#define IOMUXC_SW_PAD_CTL_GRP_EMI_DS6 0x08c0 -#define IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT 0x08c4 -#define IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT 0x08c8 -#define IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT 0x08cc -#define IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT 0x08d0 -#define IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT 0x08d4 -#define IOMUXC_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT 0x08d8 -#define IOMUXC_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT 0x08dc -#define IOMUXC_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT 0x08e0 -#define IOMUXC_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT 0x08e4 -#define IOMUXC_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT 0x08e8 -#define IOMUXC_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT 0x08ec -#define IOMUXC_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT 0x08f0 -#define IOMUXC_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT 0x08f4 -#define IOMUXC_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT 0x08f8 -#define IOMUXC_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT 0x08fc -#define IOMUXC_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT 0x0900 -#define IOMUXC_CCM_IPP_DI0_CLK_SELECT_INPUT 0x0904 -#define IOMUXC_CCM_IPP_DI1_CLK_SELECT_INPUT 0x0908 -#define IOMUXC_CCM_PLL1_BYPASS_CLK_SELECT_INPUT 0x090c -#define IOMUXC_CCM_PLL2_BYPASS_CLK_SELECT_INPUT 0x0910 -#define IOMUXC_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT 0x0914 -#define IOMUXC_CSPI_IPP_IND_MISO_SELECT_INPUT 0x0918 -#define IOMUXC_CSPI_IPP_IND_MOSI_SELECT_INPUT 0x091c -#define IOMUXC_CSPI_IPP_IND_SS1_B_SELECT_INPUT 0x0920 -#define IOMUXC_CSPI_IPP_IND_SS2_B_SELECT_INPUT 0x0924 -#define IOMUXC_CSPI_IPP_IND_SS3_B_SELECT_INPUT 0x0928 -#define IOMUXC_DPLLIP1_L1T_TOG_EN_SELECT_INPUT 0x092c -#define IOMUXC_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT 0x0930 -#define IOMUXC_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT 0x0934 -#define IOMUXC_EMI_IPP_IND_RDY_INT_SELECT_INPUT 0x0938 -#define IOMUXC_ESDHC3_IPP_DAT0_IN_SELECT_INPUT 0x093c -#define IOMUXC_ESDHC3_IPP_DAT1_IN_SELECT_INPUT 0x0940 -#define IOMUXC_ESDHC3_IPP_DAT2_IN_SELECT_INPUT 0x0944 -#define IOMUXC_ESDHC3_IPP_DAT3_IN_SELECT_INPUT 0x0948 -#define IOMUXC_FEC_FEC_COL_SELECT_INPUT 0x094c -#define IOMUXC_FEC_FEC_CRS_SELECT_INPUT 0x0950 -#define IOMUXC_FEC_FEC_MDI_SELECT_INPUT 0x0954 -#define IOMUXC_FEC_FEC_RDATA_0_SELECT_INPUT 0x0958 -#define IOMUXC_FEC_FEC_RDATA_1_SELECT_INPUT 0x095c -#define IOMUXC_FEC_FEC_RDATA_2_SELECT_INPUT 0x0960 -#define IOMUXC_FEC_FEC_RDATA_3_SELECT_INPUT 0x0964 -#define IOMUXC_FEC_FEC_RX_CLK_SELECT_INPUT 0x0968 -#define IOMUXC_FEC_FEC_RX_DV_SELECT_INPUT 0x096c -#define IOMUXC_FEC_FEC_RX_ER_SELECT_INPUT 0x0970 -#define IOMUXC_FEC_FEC_TX_CLK_SELECT_INPUT 0x0974 -#define IOMUXC_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT 0x0978 -#define IOMUXC_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT 0x097c -#define IOMUXC_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT 0x0980 -#define IOMUXC_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT 0x0984 -#define IOMUXC_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT 0x0988 -#define IOMUXC_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT 0x098c -#define IOMUXC_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT 0x0990 -#define IOMUXC_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT 0x0994 -#define IOMUXC_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT 0x0998 -#define IOMUXC_HSC_MIPI_MIX_PAR0_VSYNC_SELECT_INPUT 0x09a4 -#define IOMUXC_HSC_MIPI_MIX_PAR1_DI_WAIT_SELECT_INPUT 0x09a8 -#define IOMUXC_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT 0x09ac -#define IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT 0x09b0 -#define IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT 0x09b4 -#define IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT 0x09b8 -#define IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT 0x09bc -#define IOMUXC_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT 0x09c0 -#define IOMUXC_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT 0x09c4 -#define IOMUXC_KPP_IPP_IND_COL_6_SELECT_INPUT 0x09c8 -#define IOMUXC_KPP_IPP_IND_COL_7_SELECT_INPUT 0x09cc -#define IOMUXC_KPP_IPP_IND_ROW_4_SELECT_INPUT 0x09d0 -#define IOMUXC_KPP_IPP_IND_ROW_5_SELECT_INPUT 0x09d4 -#define IOMUXC_KPP_IPP_IND_ROW_6_SELECT_INPUT 0x09d8 -#define IOMUXC_KPP_IPP_IND_ROW_7_SELECT_INPUT 0x09dc -#define IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT 0x09e0 -#define IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT 0x09e4 -#define IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT 0x09e8 -#define IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT 0x09ec -#define IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT 0x09f0 -#define IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT 0x09f4 -#define IOMUXC_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT 0x09f8 -#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT 0x09fc -#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT 0x0a00 -#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT 0x0a04 -#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT 0x0a08 -#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT 0x0a0c -#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT 0x0a10 -#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT 0x0a14 -#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT 0x0a18 -#define IOMUXC_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT 0x0a1c -#define IOMUXC_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT 0x0a20 -#define IOMUXC_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT 0x0a24 - -/* MUX & PAD Control */ - -#define MUX_PIN(name) \ - IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_##name, \ - IOMUXC_SW_PAD_CTL_PAD_##name) - -#define MUX_PIN_MUX(name) \ - IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_##name, IOMUX_PAD_NONE) - -#define MUX_PIN_PAD(name) \ - IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_##name) - -#define MUX_PIN_GRP(name) \ - IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_GRP_##name) - -#define MUX_PIN_PATH(name) \ - IOMUX_PIN(IOMUXC_##name##_SELECT_INPUT, IOMUX_MUX_NONE) - -/* INPUT Control */ - -#define MUX_SELECT(name) (name##_SELECT_INPUT) - -#endif /* _IMX51_IOMUXREG_H */ diff --git a/sys/arm/freescale/imx/imx6_iomux.c b/sys/arm/freescale/imx/imx6_iomux.c deleted file mode 100644 index b15e503071d2..000000000000 --- a/sys/arm/freescale/imx/imx6_iomux.c +++ /dev/null @@ -1,225 +0,0 @@ -/*- - * Copyright (c) 2014 Boris Samorodov - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include -#include - -#include -#include "imx6_iomuxreg.h" - -#define IOMUX_WRITE(_sc, _r, _v) \ - bus_write_4((_sc)->sc_res, (_r), (_v)) -#define IOMUX_READ(_sc, _r) \ - bus_read_4((_sc)->sc_res, (_r)) -#define IOMUX_SET(_sc, _r, _m) \ - IOMUX_WRITE((_sc), (_r), IOMUX_READ((_sc), (_r)) | (_m)) -#define IOMUX_CLEAR(_sc, _r, _m) \ - IOMUX_WRITE((_sc), (_r), IOMUX_READ((_sc), (_r)) & ~(_m)) - -struct imx6_iomux_softc { - struct resource *sc_res; - device_t sc_dev; -}; - -static struct imx6_iomux_softc *iomuxsc = NULL; - -static struct resource_spec imx6_iomux_spec[] = { - { SYS_RES_MEMORY, 0, RF_ACTIVE }, - { SYS_RES_IRQ, 0, RF_ACTIVE }, - { -1, 0 } -}; - -static int -imx6_iomux_probe(device_t dev) -{ - if (!ofw_bus_status_okay(dev)) - return (ENXIO); - - if (!ofw_bus_is_compatible(dev, "fsl,imx6-iomux")) - return (ENXIO); - - device_set_desc(dev, "Freescale i.MX6 IO pins multiplexor"); - return (BUS_PROBE_DEFAULT); - -} - -static int -imx6_iomux_attach(device_t dev) -{ - struct imx6_iomux_softc * sc; - - sc = device_get_softc(dev); - - if (bus_alloc_resources(dev, imx6_iomux_spec, &sc->sc_res)) { - device_printf(dev, "could not allocate resources\n"); - return (ENXIO); - } - - iomuxsc = sc; - - /* - * XXX: place to fetch all info about pinmuxing from loader data - * (FDT blob) and apply. Loader (1st one) must care about - * device-to-device difference. - */ - - return (0); -} - -static int -imx6_iomux_detach(device_t dev) -{ - - /* IOMUX registers are always accessible. */ - return (EBUSY); -} - -static void -iomux_set_pad_sub(struct imx6_iomux_softc *sc, uint32_t pin, uint32_t config) -{ - bus_size_t pad_ctl_reg = IOMUX_PIN_TO_PAD_ADDRESS(pin); - - if (pad_ctl_reg != IOMUX_PAD_NONE) - IOMUX_WRITE(sc, pad_ctl_reg, config); -} - -void -iomux_set_pad(unsigned int pin, unsigned int config) -{ - - if (iomuxsc == NULL) - return; - iomux_set_pad_sub(iomuxsc, pin, config); -} - -static void -iomux_set_function_sub(struct imx6_iomux_softc *sc, uint32_t pin, uint32_t fn) -{ - bus_size_t mux_ctl_reg = IOMUX_PIN_TO_MUX_ADDRESS(pin); - - if (mux_ctl_reg != IOMUX_MUX_NONE) - IOMUX_WRITE(sc, mux_ctl_reg, fn); -} - -void -iomux_set_function(unsigned int pin, unsigned int fn) -{ - - if (iomuxsc == NULL) - return; - iomux_set_function_sub(iomuxsc, pin, fn); -} - -static uint32_t -iomux_get_pad_config_sub(struct imx6_iomux_softc *sc, uint32_t pin) -{ - bus_size_t pad_reg = IOMUX_PIN_TO_PAD_ADDRESS(pin); - uint32_t result; - - result = IOMUX_READ(sc, pad_reg); - - return(result); -} - -unsigned int -iomux_get_pad_config(unsigned int pin) -{ - - return(iomux_get_pad_config_sub(iomuxsc, pin)); -} - - -uint32_t -imx_iomux_gpr_get(u_int regnum) -{ - - KASSERT(iomuxsc != NULL, ("imx_iomux_gpr_get() called before attach")); - KASSERT(regnum >= 0 && regnum <= 13, - ("imx_iomux_gpr_get bad regnum %u", regnum)); - return (IOMUX_READ(iomuxsc, IOMUXC_GPR0 + regnum)); -} - -void -imx_iomux_gpr_set(u_int regnum, uint32_t val) -{ - - KASSERT(iomuxsc != NULL, ("imx_iomux_gpr_set() called before attach")); - KASSERT(regnum >= 0 && regnum <= 13, - ("imx_iomux_gpr_set bad regnum %u", regnum)); - IOMUX_WRITE(iomuxsc, IOMUXC_GPR0 + regnum, val); -} - -void -imx_iomux_gpr_set_masked(u_int regnum, uint32_t clrbits, uint32_t setbits) -{ - uint32_t val; - - KASSERT(iomuxsc != NULL, - ("imx_iomux_gpr_set_masked called before attach")); - KASSERT(regnum >= 0 && regnum <= 13, - ("imx_iomux_gpr_set_masked bad regnum %u", regnum)); - - val = IOMUX_READ(iomuxsc, IOMUXC_GPR0 + regnum); - val = (val & ~clrbits) | setbits; - IOMUX_WRITE(iomuxsc, IOMUXC_GPR0 + regnum, val); -} - -static device_method_t imx6_iomux_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, imx6_iomux_probe), - DEVMETHOD(device_attach, imx6_iomux_attach), - DEVMETHOD(device_detach, imx6_iomux_detach), - - DEVMETHOD_END -}; - -static driver_t imx6_iomux_driver = { - "imx6_iomux", - imx6_iomux_methods, - sizeof(struct imx6_iomux_softc), -}; - -static devclass_t imx6_iomux_devclass; - -EARLY_DRIVER_MODULE(imx6_iomux, simplebus, imx6_iomux_driver, - imx6_iomux_devclass, 0, 0, BUS_PASS_CPU + BUS_PASS_ORDER_LATE); - - diff --git a/sys/arm/freescale/imx/imx6_iomuxreg.h b/sys/arm/freescale/imx/imx6_iomuxreg.h deleted file mode 100644 index 7b74cfc34cda..000000000000 --- a/sys/arm/freescale/imx/imx6_iomuxreg.h +++ /dev/null @@ -1,798 +0,0 @@ -/*- - * Copyright (c) 2014 Boris Samorodov - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ - -/* - * Pad : pin ("pin" is used at electric schemes, - * while at HW SOC it's named "pad"). - * Drive strength : the current that can be drawn with - * appropriate voltage (varies inversely with - * the supply impedance of the output pin). - * Drive strength enable (DSE) : The value of the current the pin uses. - * HiZ (HYZ) : high input impedance value. - * Daisy chain (DAISY) : the one after another interconnection of - * devices. - * On die termination (ODT) : the termination resistor for impedance - * matching. - * Software input on (SION) : the value to force the pin to be an input - * one (i.e. to force the pin state reading). - * Hysteresis (HYS) : Controls if the value of the input pin - * remains the same until a sufficient change - * is applied. - * Slow rate enable (SRE) : How slow the pin value changes (slow rate - * saves power). - * Open drain enable (ODE) : If the input pin drains on low input or - * goes down. - * Pull/keep enable (PKE) : Enables pull/keep functionality. - * PUll/keep select (PUE) : Selects if the pin is pullup/pulldown one - * or remains it's previous role. - * A note: I'm not sure why it's not PKS... - * Pullup (Pic.1)/pulldown (Pic.2): the pin's resistor connected to VCC (GND) - * to prevent random value drai. - * Pullup/pulldown select (PUS) : Selects the value of pullup/pulldown - * resistor. - * Open drain (Pic.3) : the output signal is applied to the base - * of a transistor whose collector is used - * as a pin. - * - * VCC o VCC o Open drain - * | | ----> pin - * +++ o| / - * | | R | Switch / - * +++ pullup o| .---. - * | | / |/ \ - * >---+------> Pin >---+------> Pin >---{--| ) - * | | \ |\ / - * o| +++ `--v' - * | Switch | | R \ - * o| +++ pulldown | - * | | | - * ----- ----- ----- - * --- --- --- - * - - - - * - * Pic.1 Pic.2 Pic.3 - */ - -#ifndef IMX6_IOMUXREG_H -#define IMX6_IOMUXREG_H - -/* - * Multiplex control - */ -#define IOMUXC_MUX_CTL 0x004c -#define IOMUX_CONFIG_SION (1<<4) -#define IOMUX_CONFIG_ALT0 0 -#define IOMUX_CONFIG_ALT1 1 -#define IOMUX_CONFIG_ALT2 2 -#define IOMUX_CONFIG_ALT3 3 -#define IOMUX_CONFIG_ALT4 4 -#define IOMUX_CONFIG_ALT5 5 -#define IOMUX_CONFIG_ALT6 6 -#define IOMUX_CONFIG_ALT7 7 - -/* - * Pad control - */ -#define IOMUXC_PAD_CTL 0x0360 - /* DDR Select Field */ -#define PAD_CTL_DDR_SEL_0 (0x0<<18) -#define PAD_CTL_DDR_SEL_1 (0x1<<18) -#define PAD_CTL_DDR_SEL_2 (0x2<<18) -#define PAD_CTL_DDR_SEL_3 (0x3<<18) -#define PAD_CTL_DDR_INPUT (0x1<<17) /* DDR/CMOS Input Mode Field */ -#define PAD_CTL_HYS (1<<16) /* Hysteresis Enable Field */ - /* PullUp/Down Config Field: */ -#define PAD_CTL_PUS_100K_PD (0x0<<14) /* 100K Ohm Pull Down */ -#define PAD_CTL_PUS_47K_PU (0x1<<14) /* 47K Ohn Pull Up */ -#define PAD_CTL_PUS_100K_PU (0x2<<14) /* 100K Ohm Pull Up */ -#define PAD_CTL_PUS_22K_PU (0x3<<14) /* 22K Ohm Pull Up */ -#define PAD_CTL_PUE (1<<13) /* Pull/Keep Select Field */ -#define PAD_CTL_PKE (1<<12) /* Pull/Keep Enable Field */ -#define PAD_CTL_ODE (1<<11) /* Open Drain Enable Field */ - /* On Die Termination Field: */ -#define PAD_CTL_ODT_DISABLED (0x0<<8) /* Disabled */ -#define PAD_CTL_ODT_1 (0x1<<8) -#define PAD_CTL_ODT_2 (0x2<<8) -#define PAD_CTL_ODT_3 (0x3<<8) -#define PAD_CTL_ODT_4 (0x4<<8) -#define PAD_CTL_ODT_5 (0x5<<8) -#define PAD_CTL_ODT_6 (0x6<<8) -#define PAD_CTL_ODT_7 (0x7<<8) - /* Speed Field: */ -#define PAD_CTL_SPEED_RESERVED0 (0x0<<6) /* RESERVED */ -#define PAD_CTL_SPEED_50_MHZ (0x1<<6) /* 50 MHz */ -#define PAD_CTL_SPEED_100_MHZ (0x2<<6) /* 100 MHz */ -#define PAD_CTL_SPEED_200_MHZ (0x3<<6) /* 200 MHz */ - /* Drive Strength Field */ -#define PAD_CTL_DSE_HIZ (0x0<<3) /* HI-Z */ -#define PAD_CTL_DSE_1 (0x1<<3) -#define PAD_CTL_DSE_2 (0x2<<3) -#define PAD_CTL_DSE_3 (0x3<<3) -#define PAD_CTL_DSE_4 (0x4<<3) -#define PAD_CTL_DSE_5 (0x5<<3) -#define PAD_CTL_DSE_6 (0x6<<3) -#define PAD_CTL_DSE_7 (0x7<<3) -#define PAD_CTL_SRE (0x1<<0) /* Slew rate Field */ - -/* - * Input control - */ -#define IOMUXC_INPUT_CTL 0x07b0 /* input control */ -#define INPUT_DAISY_0 0 -#define INPUT_DAISY_1 1 -#define INPUT_DAISY_2 2 -#define INPUT_DAISY_3 3 -#define INPUT_DAISY_4 4 -#define INPUT_DAISY_5 5 -#define INPUT_DAISY_6 6 -#define INPUT_DAISY_7 7 - -/* - * IOMUX index - */ -#define IOMUX_PIN_TO_MUX_ADDRESS(pin) (((pin) >> 16) & 0xffff) -#define IOMUX_PIN_TO_PAD_ADDRESS(pin) (((pin) >> 0) & 0xffff) -#define IOMUX_PIN(mux_adr, pad_adr) \ - (((mux_adr) << 16) | (((pad_adr) << 0))) -#define IOMUX_MUX_NONE 0xffff -#define IOMUX_PAD_NONE 0xffff - -/* - * MUX & PAD Control - */ -#define MUX_PIN(name) \ - IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_##name, \ - IOMUXC_SW_PAD_CTL_PAD_##name) - -#define MUX_PIN_MUX(name) \ - IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_##name, IOMUX_PAD_NONE) - -#define MUX_PIN_PAD(name) \ - IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_##name) - -#define MUX_PIN_GRP(name) \ - IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_GRP_##name) - -#define MUX_PIN_PATH(name) \ - IOMUX_PIN(IOMUXC_##name##_SELECT_INPUT, IOMUX_MUX_NONE) - -/* - * INPUT Control - */ -#define MUX_SELECT(name) (name##_SELECT_INPUT) - -/* - * Register names, offset addresses (and reset values for reference) - * from Chapter 36 IOMUX Controller (IOMUXC), IMX6DQRM, Rev.1, 04/2013 - * - * General Purpose Registers - */ -#define IOMUXC_GPR0 0x0000 /* 0x00000000 */ -#define IOMUXC_GPR1 0x0004 /* 0x48400005 */ -#define IOMUXC_GPR2 0x0008 /* 0x00000000 */ -#define IOMUXC_GPR3 0x000c /* 0x01e00000 */ -#define IOMUXC_GPR4 0x0010 /* 0x00000000 */ -#define IOMUXC_GPR5 0x0014 /* 0x00000000 */ -#define IOMUXC_GPR6 0x0018 /* 0x22222222 */ -#define IOMUXC_GPR7 0x001c /* 0x22222222 */ -#define IOMUXC_GPR8 0x0020 /* 0x00000000 */ -#define IOMUXC_GPR9 0x0024 /* 0x00000000 */ -#define IOMUXC_GPR10 0x0028 /* 0x00003800 */ -#define IOMUXC_GPR11 0x002c /* 0x00003800 */ -#define IOMUXC_GPR12 0x0030 /* 0x0f000000 */ -#define IOMUXC_GPR13 0x0034 /* 0x059124c4 */ -/* - * Pad Mux Registers - */ -#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 0x004c /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 0x0050 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 0x0054 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC 0x0058 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0 0x005c /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1 0x0060 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2 0x0064 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3 0x0068 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL 0x006c /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0 0x0070 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL 0x0074 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1 0x0078 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2 0x007c /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3 0x0080 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC 0x0084 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25 0x0088 /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_B 0x008c /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16 0x0090 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17 0x0094 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18 0x0098 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19 0x009c /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20 0x00a0 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x00a4 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22 0x00a8 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23 0x00ac /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_B 0x00b0 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24 0x00b4 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25 0x00b8 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26 0x00bc /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27 0x00c0 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 0x00c4 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29 0x00c8 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30 0x00cc /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31 0x00d0 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24 0x00d4 /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23 0x00d8 /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22 0x00dc /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21 0x00e0 /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20 0x00e4 /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19 0x00e8 /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18 0x00ec /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17 0x00f0 /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16 0x00f4 /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_B 0x00f8 /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_B 0x00fc /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_OE_B 0x0100 /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_RW 0x0104 /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_B 0x0108 /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_B 0x010c /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_B 0x0110 /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD00 0x0114 /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD01 0x0118 /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD02 0x011c /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD03 0x0120 /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD04 0x0124 /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD05 0x0128 /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD06 0x012c /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD07 0x0130 /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD08 0x0134 /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD09 0x0138 /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD10 0x013c /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD11 0x0140 /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD12 0x0144 /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD13 0x0148 /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD14 0x014c /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD15 0x0150 /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_B 0x0154 /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK 0x0158 /* 0x00000000 */ -#define IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK 0x015c /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15 0x0160 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02 0x0164 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03 0x0168 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04 0x016c /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00 0x0170 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01 0x0174 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02 0x0178 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03 0x017c /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04 0x0180 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05 0x0184 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06 0x0188 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07 0x018c /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08 0x0190 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09 0x0194 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10 0x0198 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11 0x019c /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12 0x01a0 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13 0x01a4 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14 0x01a8 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15 0x01ac /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16 0x01b0 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17 0x01b4 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18 0x01b8 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19 0x01bc /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20 0x01c0 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21 0x01c4 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22 0x01c8 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23 0x01cc /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO 0x01d0 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK 0x01d4 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER 0x01d8 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV 0x01dc /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1 0x01e0 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0 0x01e4 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN 0x01e8 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1 0x01ec /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0 0x01f0 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_ENET_MDC 0x01f4 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0 0x01f8 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0 0x01fc /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1 0x0200 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1 0x0204 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2 0x0208 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2 0x020c /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3 0x0210 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3 0x0214 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4 0x0218 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4 0x021c /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_GPIO00 0x0220 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_GPIO01 0x0224 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_GPIO09 0x0228 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_GPIO03 0x022c /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_GPIO06 0x0230 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_GPIO02 0x0234 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_GPIO04 0x0238 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_GPIO05 0x023c /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_GPIO07 0x0240 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_GPIO08 0x0244 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_GPIO16 0x0248 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_GPIO17 0x024c /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_GPIO18 0x0250 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_GPIO19 0x0254 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK 0x0258 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC 0x025c /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN 0x0260 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC 0x0264 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04 0x0268 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05 0x026c /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06 0x0270 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07 0x0274 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08 0x0278 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09 0x027c /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10 0x0280 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11 0x0284 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12 0x0288 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13 0x028c /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14 0x0290 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15 0x0294 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16 0x0298 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17 0x029c /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18 0x02a0 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19 0x02a4 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 0x02a8 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6 0x02ac /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5 0x02b0 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4 0x02b4 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD 0x02b8 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK 0x02bc /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0 0x02c0 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1 0x02c4 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2 0x02c8 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3 0x02cc /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_SD3_RESET 0x02d0 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE 0x02d4 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE 0x02d8 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B 0x02dc /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B 0x02e0 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B 0x02e4 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B 0x02e8 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B 0x02ec /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B 0x02f0 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD 0x02f4 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK 0x02f8 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 0x02fc /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 0x0300 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 0x0304 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 0x0308 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 0x030c /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 0x0310 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 0x0314 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 0x0318 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0 0x031c /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1 0x0320 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2 0x0324 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3 0x0328 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4 0x032c /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5 0x0330 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6 0x0334 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7 0x0338 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 0x033c /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 0x0340 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 0x0344 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD 0x0348 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 0x034c /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK 0x0350 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK 0x0354 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD 0x0358 /* 0x00000005 */ -#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 0x035c /* 0x00000005 */ -/* - * Pad Control registers - */ -#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 0x0360 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 0x0364 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 0x0368 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC 0x036c /* 0x00013030 */ -#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0 0x0370 /* 0x0001b030 */ -#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1 0x0374 /* 0x0001b030 */ -#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2 0x0378 /* 0x0001b030 */ -#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3 0x037c /* 0x0001b030 */ -#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL 0x0380 /* 0x00013030 */ -#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0 0x0384 /* 0x0001b030 */ -#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL 0x0388 /* 0x00013030 */ -#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1 0x038c /* 0x0001b030 */ -#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2 0x0390 /* 0x0001b030 */ -#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3 0x0394 /* 0x0001b030 */ -#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC 0x0398 /* 0x00013030 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25 0x039c /* 0x0000b0b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_B 0x03a0 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16 0x03a4 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17 0x03a8 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18 0x03ac /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19 0x03b0 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20 0x03b4 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21 0x03b8 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22 0x03bc /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23 0x03c0 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_B 0x03c4 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24 0x03c8 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25 0x03cc /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26 0x03d0 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27 0x03d4 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28 0x03d8 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29 0x03dc /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30 0x03e0 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31 0x03e4 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24 0x03e8 /* 0x0000b0b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23 0x03ec /* 0x0000b0b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22 0x03f0 /* 0x0000b0b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21 0x03f4 /* 0x0000b0b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20 0x03f8 /* 0x0000b0b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19 0x03fc /* 0x0000b0b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18 0x0400 /* 0x0000b0b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17 0x0404 /* 0x0000b0b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16 0x0408 /* 0x0000b0b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_B 0x040c /* 0x0000b0b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_B 0x0410 /* 0x0000b0b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_OE_B 0x0414 /* 0x0000b0b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_RW 0x0418 /* 0x0000b0b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_B 0x041c /* 0x0000b0b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_B 0x0420 /* 0x0000b0b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_B 0x0424 /* 0x0000b0b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD00 0x0428 /* 0x0000b0b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD01 0x042c /* 0x0000b0b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD02 0x0430 /* 0x0000b0b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD03 0x0434 /* 0x0000b0b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD04 0x0438 /* 0x0000b0b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD05 0x043c /* 0x0000b0b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD06 0x0440 /* 0x0000b0b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD07 0x0444 /* 0x0000b0b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD08 0x0448 /* 0x0000b0b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD09 0x044c /* 0x0000b0b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD10 0x0450 /* 0x0000b0b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD11 0x0454 /* 0x0000b0b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD12 0x0458 /* 0x0000b0b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD13 0x045c /* 0x0000b0b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD14 0x0460 /* 0x0000b0b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD15 0x0464 /* 0x0000b0b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_B 0x0468 /* 0x0000b060 */ -#define IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK 0x046c /* 0x0000b0b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK 0x0470 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15 0x0474 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02 0x0478 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03 0x047c /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04 0x0480 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00 0x0484 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01 0x0488 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02 0x048c /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03 0x0490 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04 0x0494 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05 0x0498 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06 0x049c /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07 0x04a0 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08 0x04a4 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09 0x04a8 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10 0x04ac /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11 0x04b0 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12 0x04b4 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13 0x04b8 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14 0x04bc /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15 0x04c0 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16 0x04c4 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17 0x04c8 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18 0x04cc /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19 0x04d0 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20 0x04d4 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21 0x04d8 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22 0x04dc /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23 0x04e0 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO 0x04e4 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK 0x04e8 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER 0x04ec /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV 0x04f0 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1 0x04f4 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0 0x04f8 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN 0x04fc /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1 0x0500 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0 0x0504 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_ENET_MDC 0x0508 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P 0x050c /* 0x00002030 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 0x0510 /* 0x00008030 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 0x0514 /* 0x00008030 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P 0x0518 /* 0x00002030 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P 0x051c /* 0x00002030 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 0x0520 /* 0x00008030 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P 0x0524 /* 0x00002030 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 0x0528 /* 0x00008030 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 0x052c /* 0x00008000 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01 0x0530 /* 0x00008000 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 0x0534 /* 0x00008000 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 0x0538 /* 0x00008000 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 0x053c /* 0x00008000 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 0x0540 /* 0x00008000 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 0x0544 /* 0x00008000 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 0x0548 /* 0x00008000 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 0x054c /* 0x00008000 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 0x0550 /* 0x00008000 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10 0x0554 /* 0x00008000 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11 0x0558 /* 0x00008000 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12 0x055c /* 0x00008000 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13 0x0560 /* 0x00008000 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14 0x0564 /* 0x00008000 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15 0x0568 /* 0x00008000 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B 0x056c /* 0x00008030 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B 0x0570 /* 0x00008000 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B 0x0574 /* 0x00008000 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B 0x0578 /* 0x00008030 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET 0x057c /* 0x00083030 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 0x0580 /* 0x00008000 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 0x0584 /* 0x00008000 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P 0x0588 /* 0x00008030 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 0x058c /* 0x0000b000 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 0x0590 /* 0x00003000 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P 0x0594 /* 0x00008030 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 0x0598 /* 0x00003000 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 0x059c /* 0x00003030 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 0x05a0 /* 0x00003030 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B 0x05a4 /* 0x00008000 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P 0x05a8 /* 0x00002030 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x05ac /* 0x00008030 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P 0x05b0 /* 0x00002030 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x05b4 /* 0x00008030 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P 0x05b8 /* 0x00002030 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 0x05bc /* 0x00008030 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P 0x05c0 /* 0x00002030 */ -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 0x05c4 /* 0x00008030 */ -#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0 0x05c8 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0 0x05cc /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1 0x05d0 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1 0x05d4 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2 0x05d8 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2 0x05dc /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3 0x05e0 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3 0x05e4 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4 0x05e8 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4 0x05ec /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_GPIO00 0x05f0 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_GPIO01 0x05f4 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_GPIO09 0x05f8 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_GPIO03 0x05fc /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_GPIO06 0x0600 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_GPIO02 0x0604 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_GPIO04 0x0608 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_GPIO05 0x060c /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_GPIO07 0x0610 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_GPIO08 0x0614 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_GPIO16 0x0618 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_GPIO17 0x061c /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_GPIO18 0x0620 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_GPIO19 0x0624 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK 0x0628 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC 0x062c /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN 0x0630 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC 0x0634 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04 0x0638 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05 0x063c /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06 0x0640 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07 0x0644 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08 0x0648 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09 0x064c /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10 0x0650 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11 0x0654 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12 0x0658 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13 0x065c /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14 0x0660 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15 0x0664 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16 0x0668 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17 0x066c /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18 0x0670 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19 0x0674 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS 0x0678 /* 0x00007060 */ -#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD 0x067c /* 0x0000b060 */ -#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB 0x0680 /* 0x00007060 */ -#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI 0x0684 /* 0x00007060 */ -#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK 0x0688 /* 0x00007060 */ -#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO 0x068c /* 0x000090b1 */ -#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7 0x0690 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6 0x0694 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5 0x0698 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4 0x069c /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD 0x06a0 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK 0x06a4 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0 0x06a8 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1 0x06ac /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2 0x06b0 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3 0x06b4 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET 0x06b8 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE 0x06bc /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE 0x06c0 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B 0x06c4 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B 0x06c8 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B 0x06cc /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B 0x06d0 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B 0x06d4 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B 0x06d8 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD 0x06dc /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK 0x06e0 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00 0x06e4 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01 0x06e8 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 0x06ec /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03 0x06f0 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04 0x06f4 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05 0x06f8 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06 0x06fc /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07 0x0700 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0 0x0704 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1 0x0708 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2 0x070c /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3 0x0710 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4 0x0714 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5 0x0718 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6 0x071c /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7 0x0720 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 0x0724 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 0x0728 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 0x072c /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD 0x0730 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 0x0734 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK 0x0738 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK 0x073c /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD 0x0740 /* 0x0001b0b0 */ -#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 0x0744 /* 0x0001b0b0 */ -/* - * Pad Group Control Registers - */ -#define IOMUXC_SW_PAD_CTL_GRP_B7DS 0x0748 /* 0x00000030 */ -#define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x074c /* 0x00000030 */ -#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x0750 /* 0x00000000 */ -#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0 0x0754 /* 0x00000000 */ -#define IOMUXC_SW_PAD_CTL_GRP_DDRPKE 0x0758 /* 0x00001000 */ -#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1 0x075c /* 0x00000000 */ -#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2 0x0760 /* 0x00000000 */ -#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3 0x0764 /* 0x00000000 */ -#define IOMUXC_SW_PAD_CTL_GRP_DDRPK 0x0768 /* 0x00002000 */ -#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4 0x076c /* 0x00000000 */ -#define IOMUXC_SW_PAD_CTL_GRP_DDRHYS 0x0770 /* 0x00000000 */ -#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE 0x0774 /* 0x00000000 */ -#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5 0x0778 /* 0x00000000 */ -#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6 0x077c /* 0x00000000 */ -#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7 0x0780 /* 0x00000000 */ -#define IOMUXC_SW_PAD_CTL_GRP_B0DS 0x0784 /* 0x00000030 */ -#define IOMUXC_SW_PAD_CTL_GRP_B1DS 0x0788 /* 0x00000030 */ -#define IOMUXC_SW_PAD_CTL_GRP_CTLDS 0x078c /* 0x00000030 */ -#define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII 0x0790 /* 0x00080000 */ -#define IOMUXC_SW_PAD_CTL_GRP_B2DS 0x0794 /* 0x00000030 */ -#define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 0x0798 /* 0x00080000 */ -#define IOMUXC_SW_PAD_CTL_GRP_B3DS 0x079c /* 0x00000030 */ -#define IOMUXC_SW_PAD_CTL_GRP_B4DS 0x07a0 /* 0x00000030 */ -#define IOMUXC_SW_PAD_CTL_GRP_B5DS 0x07a4 /* 0x00000030 */ -#define IOMUXC_SW_PAD_CTL_GRP_B6DS 0x07a8 /* 0x00000030 */ -#define IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM 0x07ac /* 0x00000000 */ -/* - * Select Input Registers - */ -#define IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT 0x07b0 /* 0x00000000 */ -#define IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT 0x07b4 /* 0x00000000 */ -#define IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT 0x07b8 /* 0x00000000 */ -#define IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT 0x07bc /* 0x00000000 */ -#define IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT 0x07c0 /* 0x00000000 */ -#define IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT 0x07c4 /* 0x00000000 */ -#define IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT 0x07c8 /* 0x00000000 */ -#define IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT 0x07cc /* 0x00000000 */ -#define IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT 0x07d0 /* 0x00000000 */ -#define IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT 0x07d4 /* 0x00000000 */ -#define IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT 0x07d8 /* 0x00000000 */ -#define IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT 0x07dc /* 0x00000000 */ -#define IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT 0x07e0 /* 0x00000000 */ -#define IOMUXC_FLEXCAN1_RX_SELECT_INPUT 0x07e4 /* 0x00000000 */ -#define IOMUXC_FLEXCAN2_RX_SELECT_INPUT 0x07e8 /* 0x00000000 */ -#define IOMUXC_CCM_PMIC_READY_SELECT_INPUT 0x07f0 /* 0x00000000 */ -#define IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT 0x07f4 /* 0x00000000 */ -#define IOMUXC_ECSPI1_MISO_SELECT_INPUT 0x07f8 /* 0x00000000 */ -#define IOMUXC_ECSPI1_MOSI_SELECT_INPUT 0x07fc /* 0x00000000 */ -#define IOMUXC_ECSPI1_SS0_SELECT_INPUT 0x0800 /* 0x00000000 */ -#define IOMUXC_ECSPI1_SS1_SELECT_INPUT 0x0804 /* 0x00000000 */ -#define IOMUXC_ECSPI1_SS2_SELECT_INPUT 0x0808 /* 0x00000000 */ -#define IOMUXC_ECSPI1_SS3_SELECT_INPUT 0x080c /* 0x00000000 */ -#define IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT 0x0810 /* 0x00000000 */ -#define IOMUXC_ECSPI2_MISO_SELECT_INPUT 0x0814 /* 0x00000000 */ -#define IOMUXC_ECSPI2_MOSI_SELECT_INPUT 0x0818 /* 0x00000000 */ -#define IOMUXC_ECSPI2_SS0_SELECT_INPUT 0x081c /* 0x00000000 */ -#define IOMUXC_ECSPI2_SS1_SELECT_INPUT 0x0820 /* 0x00000000 */ -#define IOMUXC_ECSPI4_SS0_SELECT_INPUT 0x0824 /* 0x00000000 */ -#define IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT 0x0828 /* 0x00000000 */ -#define IOMUXC_ECSPI5_MISO_SELECT_INPUT 0x082c /* 0x00000000 */ -#define IOMUXC_ECSPI5_MOSI_SELECT_INPUT 0x0830 /* 0x00000000 */ -#define IOMUXC_ECSPI5_SS0_SELECT_INPUT 0x0834 /* 0x00000000 */ -#define IOMUXC_ECSPI5_SS1_SELECT_INPUT 0x0838 /* 0x00000000 */ -#define IOMUXC_ENET_REF_CLK_SELECT_INPUT 0x083c /* 0x00000000 */ -#define IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT 0x0840 /* 0x00000000 */ -#define IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT 0x0844 /* 0x00000000 */ -#define IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT 0x0848 /* 0x00000000 */ -#define IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT 0x084c /* 0x00000000 */ -#define IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT 0x0850 /* 0x00000000 */ -#define IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT 0x0854 /* 0x00000000 */ -#define IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT 0x0858 /* 0x00000000 */ -#define IOMUXC_ESAI_RX_FS_SELECT_INPUT 0x085c /* 0x00000000 */ -#define IOMUXC_ESAI_TX_FS_SELECT_INPUT 0x0860 /* 0x00000000 */ -#define IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT 0x0864 /* 0x00000000 */ -#define IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT 0x0868 /* 0x00000000 */ -#define IOMUXC_ESAI_RX_CLK_SELECT_INPUT 0x086c /* 0x00000000 */ -#define IOMUXC_ESAI_TX_CLK_SELECT_INPUT 0x0870 /* 0x00000000 */ -#define IOMUXC_ESAI_SDO0_SELECT_INPUT 0x0874 /* 0x00000000 */ -#define IOMUXC_ESAI_SDO1_SELECT_INPUT 0x0878 /* 0x00000000 */ -#define IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT 0x087c /* 0x00000000 */ -#define IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT 0x0880 /* 0x00000000 */ -#define IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT 0x0884 /* 0x00000000 */ -#define IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT 0x0888 /* 0x00000000 */ -#define IOMUXC_HDMI_ICECIN_SELECT_INPUT 0x088c /* 0x00000000 */ -#define IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT 0x0890 /* 0x00000000 */ -#define IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT 0x0894 /* 0x00000000 */ -#define IOMUXC_I2C1_SCL_IN_SELECT_INPUT 0x0898 /* 0x00000000 */ -#define IOMUXC_I2C1_SDA_IN_SELECT_INPUT 0x089c /* 0x00000000 */ -#define IOMUXC_I2C2_SCL_IN_SELECT_INPUT 0x08a0 /* 0x00000000 */ -#define IOMUXC_I2C2_SDA_IN_SELECT_INPUT 0x08a4 /* 0x00000000 */ -#define IOMUXC_I2C3_SCL_IN_SELECT_INPUT 0x08a8 /* 0x00000000 */ -#define IOMUXC_I2C3_SDA_IN_SELECT_INPUT 0x08ac /* 0x00000000 */ -#define IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT 0x08b0 /* 0x00000000 */ -#define IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT 0x08b4 /* 0x00000000 */ -#define IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT 0x08b8 /* 0x00000000 */ -#define IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT 0x08bc /* 0x00000000 */ -#define IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT 0x08c0 /* 0x00000000 */ -#define IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT 0x08c4 /* 0x00000000 */ -#define IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT 0x08c8 /* 0x00000000 */ -#define IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT 0x08cc /* 0x00000000 */ -#define IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT 0x08d0 /* 0x00000000 */ -#define IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT 0x08d4 /* 0x00000000 */ -#define IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT 0x08d8 /* 0x00000000 */ -#define IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT 0x08dc /* 0x00000000 */ -#define IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT 0x08e0 /* 0x00000000 */ -#define IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT 0x08e4 /* 0x00000000 */ -#define IOMUXC_KEY_COL5_SELECT_INPUT 0x08e8 /* 0x00000000 */ -#define IOMUXC_KEY_COL6_SELECT_INPUT 0x08ec /* 0x00000000 */ -#define IOMUXC_KEY_COL7_SELECT_INPUT 0x08f0 /* 0x00000000 */ -#define IOMUXC_KEY_ROW5_SELECT_INPUT 0x08f4 /* 0x00000000 */ -#define IOMUXC_KEY_ROW6_SELECT_INPUT 0x08f8 /* 0x00000000 */ -#define IOMUXC_KEY_ROW7_SELECT_INPUT 0x08fc /* 0x00000000 */ -#define IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT 0x0900 /* 0x00000000 */ -#define IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT 0x0904 /* 0x00000000 */ -#define IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT 0x0908 /* 0x00000000 */ -#define IOMUXC_SDMA_EVENTS14_SELECT_INPUT 0x090c /* 0x00000000 */ -#define IOMUXC_SDMA_EVENTS15_SELECT_INPUT 0x0910 /* 0x00000000 */ -#define IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT 0x0914 /* 0x00000000 */ -#define IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT 0x0918 /* 0x00000000 */ -#define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT 0x091c /* 0x00000000 */ -#define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x0920 /* 0x00000000 */ -#define IOMUXC_UART2_UART_RTS_B_SELECT_INPUT 0x0924 /* 0x00000000 */ -#define IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT 0x0928 /* 0x00000000 */ -#define IOMUXC_UART3_UART_RTS_B_SELECT_INPUT 0x092c /* 0x00000000 */ -#define IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT 0x0930 /* 0x00000000 */ -#define IOMUXC_UART4_UART_RTS_B_SELECT_INPUT 0x0934 /* 0x00000000 */ -#define IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT 0x0938 /* 0x00000000 */ -#define IOMUXC_UART5_UART_RTS_B_SELECT_INPUT 0x093c /* 0x00000000 */ -#define IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT 0x0940 /* 0x00000000 */ -#define IOMUXC_USB_OTG_OC_SELECT_INPUT 0x0944 /* 0x00000000 */ -#define IOMUXC_USB_H1_OC_SELECT_INPUT 0x0948 /* 0x00000000 */ -#define IOMUXC_USDHC1_WP_ON_SELECT_INPUT 0x094c /* 0x00000000 */ - -#endif /* IMX6_IOMUXREG_H */ diff --git a/sys/arm/freescale/imx/imx_iomux.c b/sys/arm/freescale/imx/imx_iomux.c new file mode 100644 index 000000000000..e5d5085bf0e0 --- /dev/null +++ b/sys/arm/freescale/imx/imx_iomux.c @@ -0,0 +1,282 @@ +/*- + * Copyright (c) 2014 Ian Lepore + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * Pin mux and pad control driver for imx5 and imx6. + * + * This driver implements the fdt_pinctrl interface for configuring the gpio and + * peripheral pins based on fdt configuration data. + * + * When the driver attaches, it walks the entire fdt tree and automatically + * configures the pins for each device which has a pinctrl-0 property and whose + * status is "okay". In addition it implements the fdt_pinctrl_configure() + * method which any other driver can call at any time to reconfigure its pins. + * + * The nature of the fsl,pins property in fdt data makes this driver's job very + * easy. Instead of representing each pin and pad configuration using symbolic + * properties such as pullup-enable="true" and so on, the data simply contains + * the addresses of the registers that control the pins, and the raw values to + * store in those registers. + * + * The imx5 and imx6 SoCs also have a small number of "general purpose + * registers" in the iomuxc device which are used to control an assortment + * of completely unrelated aspects of SoC behavior. This driver provides other + * drivers with direct access to those registers via simple accessor functions. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +struct iomux_softc { + device_t dev; + struct resource *mem_res; + u_int last_gpreg; +}; + +static struct iomux_softc *iomux_sc; + +static struct ofw_compat_data compat_data[] = { + {"fsl,imx6dl-iomuxc", true}, + {"fsl,imx6q-iomuxc", true}, + {"fsl,imx6sl-iomuxc", true}, + {"fsl,imx6sx-iomuxc", true}, + {"fsl,imx53-iomuxc", true}, + {"fsl,imx51-iomuxc", true}, + {NULL, false}, +}; + +/* + * Each tuple in an fsl,pins property contains these fields. + */ +struct pincfg { + uint32_t mux_reg; + uint32_t padconf_reg; + uint32_t input_reg; + uint32_t mux_val; + uint32_t input_val; + uint32_t padconf_val; +}; + +static inline uint32_t +RD4(struct iomux_softc *sc, bus_size_t off) +{ + + return (bus_read_4(sc->mem_res, off)); +} + +static inline void +WR4(struct iomux_softc *sc, bus_size_t off, uint32_t val) +{ + + bus_write_4(sc->mem_res, off, val); +} + +static int +iomux_configure_pins(device_t dev, phandle_t cfgxref) +{ + struct iomux_softc * sc; + struct pincfg *cfgtuples, *cfg; + phandle_t cfgnode; + int i, ntuples; + + sc = device_get_softc(dev); + cfgnode = OF_node_from_xref(cfgxref); + ntuples = OF_getencprop_alloc(cfgnode, "fsl,pins", sizeof(*cfgtuples), + (void **)&cfgtuples); + if (ntuples < 0) + return (ENOENT); + if (ntuples == 0) + return (0); /* Empty property is not an error. */ + for (i = 0, cfg = cfgtuples; i < ntuples; i++, cfg++) { + WR4(sc, cfg->mux_reg, cfg->mux_val); + WR4(sc, cfg->input_reg, cfg->input_val); + WR4(sc, cfg->padconf_reg, cfg->padconf_val); + } + free(cfgtuples, M_OFWPROP); + return (0); +} + +static int +iomux_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) + return (ENXIO); + + device_set_desc(dev, "Freescale i.MX pin configuration"); + return (BUS_PROBE_DEFAULT); +} + +static int +iomux_detach(device_t dev) +{ + + /* This device is always present. */ + return (EBUSY); +} + +static int +iomux_attach(device_t dev) +{ + struct iomux_softc * sc; + int rid; + + sc = device_get_softc(dev); + sc->dev = dev; + + switch (imx_soc_type()) { + case IMXSOC_51: + sc->last_gpreg = 1; + break; + case IMXSOC_53: + sc->last_gpreg = 2; + break; + case IMXSOC_6DL: + case IMXSOC_6S: + case IMXSOC_6SL: + case IMXSOC_6Q: + sc->last_gpreg = 13; + break; + default: + device_printf(dev, "Unknown SoC type\n"); + return (ENXIO); + } + + rid = 0; + sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, + RF_ACTIVE); + if (sc->mem_res == NULL) { + device_printf(dev, "Cannot allocate memory resources\n"); + return (ENXIO); + } + + iomux_sc = sc; + + /* + * Register as a pinctrl device, and call the convenience function that + * walks the entire device tree invoking FDT_PINCTRL_CONFIGURE() on any + * pinctrl-0 property cells whose xref phandle refers to a configuration + * that is a child node of our node in the tree. + * + * The pinctrl bindings documentation specifically mentions that the + * pinctrl device itself may have a pinctrl-0 property which contains + * static configuration to be applied at device init time. The tree + * walk will automatically handle this for us when it passes through our + * node in the tree. + */ + fdt_pinctrl_register(dev, "fsl,pins"); + fdt_pinctrl_configure_tree(dev); + + return (0); +} + +uint32_t +imx_iomux_gpr_get(u_int regnum) +{ + struct iomux_softc * sc; + + sc = iomux_sc; + KASSERT(sc != NULL, ("%s called before attach", __FUNCTION__)); + KASSERT(regnum >= 0 && regnum <= sc->last_gpreg, + ("%s bad regnum %u, max %u", __FUNCTION__, regnum, sc->last_gpreg)); + + return (RD4(iomux_sc, regnum * 4)); +} + +void +imx_iomux_gpr_set(u_int regnum, uint32_t val) +{ + struct iomux_softc * sc; + + sc = iomux_sc; + KASSERT(sc != NULL, ("%s called before attach", __FUNCTION__)); + KASSERT(regnum >= 0 && regnum <= sc->last_gpreg, + ("%s bad regnum %u, max %u", __FUNCTION__, regnum, sc->last_gpreg)); + + WR4(iomux_sc, regnum * 4, val); +} + +void +imx_iomux_gpr_set_masked(u_int regnum, uint32_t clrbits, uint32_t setbits) +{ + struct iomux_softc * sc; + uint32_t val; + + sc = iomux_sc; + KASSERT(sc != NULL, ("%s called before attach", __FUNCTION__)); + KASSERT(regnum >= 0 && regnum <= sc->last_gpreg, + ("%s bad regnum %u, max %u", __FUNCTION__, regnum, sc->last_gpreg)); + + val = RD4(iomux_sc, regnum * 4); + val = (val & ~clrbits) | setbits; + WR4(iomux_sc, regnum * 4, val); +} + +static device_method_t imx_iomux_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, iomux_probe), + DEVMETHOD(device_attach, iomux_attach), + DEVMETHOD(device_detach, iomux_detach), + + /* fdt_pinctrl interface */ + DEVMETHOD(fdt_pinctrl_configure,iomux_configure_pins), + + DEVMETHOD_END +}; + +static driver_t imx_iomux_driver = { + "imx_iomux", + imx_iomux_methods, + sizeof(struct iomux_softc), +}; + +static devclass_t imx_iomux_devclass; + +EARLY_DRIVER_MODULE(imx_iomux, simplebus, imx_iomux_driver, + imx_iomux_devclass, 0, 0, BUS_PASS_CPU + BUS_PASS_ORDER_LATE); + diff --git a/sys/arm/freescale/imx/std.imx51 b/sys/arm/freescale/imx/std.imx51 index a6b6ffadd9e7..ce9d7d26be7e 100644 --- a/sys/arm/freescale/imx/std.imx51 +++ b/sys/arm/freescale/imx/std.imx51 @@ -10,5 +10,7 @@ options KERNPHYSADDR=0x90100000 makeoptions KERNPHYSADDR=0x90100000 options PHYSADDR=0x90000000 +device fdt_pinctrl + files "../freescale/imx/files.imx51" diff --git a/sys/arm/freescale/imx/std.imx53 b/sys/arm/freescale/imx/std.imx53 index 40fbb300a9c7..09bdb2d0e92c 100644 --- a/sys/arm/freescale/imx/std.imx53 +++ b/sys/arm/freescale/imx/std.imx53 @@ -10,5 +10,7 @@ options KERNPHYSADDR=0x70100000 makeoptions KERNPHYSADDR=0x70100000 options PHYSADDR=0x70000000 +device fdt_pinctrl + files "../freescale/imx/files.imx53" diff --git a/sys/arm/freescale/imx/std.imx6 b/sys/arm/freescale/imx/std.imx6 index 51f82a8e2f90..a559f17ceb06 100644 --- a/sys/arm/freescale/imx/std.imx6 +++ b/sys/arm/freescale/imx/std.imx6 @@ -13,5 +13,7 @@ options PHYSADDR = 0x10000000 options IPI_IRQ_START=0 options IPI_IRQ_END=15 +device fdt_pinctrl + files "../freescale/imx/files.imx6"