ARM: Add identifiers for ARM Cortex v8 and Marvell Sheeva v7 cores.
Not a functional change. MFC after: 3 days
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@ -165,7 +165,11 @@ cpuinfo_get_actlr_modifier(uint32_t *actlr_mask, uint32_t *actlr_set)
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if (cpuinfo.implementer == CPU_IMPLEMENTER_ARM) {
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switch (cpuinfo.part_number) {
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case CPU_ARCH_CORTEX_A72:
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case CPU_ARCH_CORTEX_A57:
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case CPU_ARCH_CORTEX_A53:
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/* Nothing to do for AArch32 */
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break;
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case CPU_ARCH_CORTEX_A17:
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case CPU_ARCH_CORTEX_A12: /* A12 is merged to A17 */
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/*
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@ -45,10 +45,18 @@
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#define CPU_ARCH_CORTEX_A12 0xC0D
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#define CPU_ARCH_CORTEX_A15 0xC0F
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#define CPU_ARCH_CORTEX_A17 0xC11
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#define CPU_ARCH_CORTEX_A53 0xD03
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#define CPU_ARCH_CORTEX_A57 0xD07
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#define CPU_ARCH_CORTEX_A72 0xD08
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/* QCOM */
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#define CPU_ARCH_KRAIT_300 0x06F
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/* MRVL */
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#define CPU_ARCH_SHEEVA_851 0x581 /* PJ4/PJ4B */
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#define CPU_ARCH_SHEEVA_584 0x584 /* PJ4B-MP/PJ4C */
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struct cpuinfo {
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/* raw id registers */
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uint32_t midr;
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