diff --git a/ObsoleteFiles.inc b/ObsoleteFiles.inc index 15e9f2b6df2f..16f8d2f93352 100644 --- a/ObsoleteFiles.inc +++ b/ObsoleteFiles.inc @@ -99,6 +99,8 @@ OLD_FILES+=usr/lib/clang/3.6.1/lib/freebsd/libclang_rt.ubsan_cxx-x86_64.a OLD_DIRS+=usr/lib/clang/3.6.1/lib/freebsd OLD_DIRS+=usr/lib/clang/3.6.1/lib OLD_DIRS+=usr/lib/clang/3.6.1 +# 20150719: Remove libarchive.pc +OLD_FILES+=usr/libdata/pkgconfig/libarchive.pc # 20150705: Rename DTrace provider man pages. OLD_FILES+=usr/share/man/man4/dtrace-io.4.gz OLD_FILES+=usr/share/man/man4/dtrace-ip.4.gz diff --git a/UPDATING b/UPDATING index b1cfe1490cbd..86c58088211e 100644 --- a/UPDATING +++ b/UPDATING @@ -92,7 +92,7 @@ NOTE TO PEOPLE WHO THINK THAT FreeBSD 11.x IS SLOW: 20150616: FreeBSD's old make (fmake) has been removed from the system. It is available as the devel/fmake port or via pkg install fmake. - + 20150615: The fix for the issue described in the 20150614 sendmail entry below has been been committed in revision 284436. The work @@ -115,7 +115,7 @@ NOTE TO PEOPLE WHO THINK THAT FreeBSD 11.x IS SLOW: this interoperability, sendmail can be configured to use a 2048 bit DH parameter by: - 1. Edit /etc/mail/`hostname`.mc + 1. Edit /etc/mail/`hostname`.mc 2. If a setting for confDH_PARAMETERS does not exist or exists and is set to a string beginning with '5', replace it with '2'. @@ -228,7 +228,7 @@ NOTE TO PEOPLE WHO THINK THAT FreeBSD 11.x IS SLOW: using a local socket. Users who have already enabled the local_unbound service should regenerate their configuration by running "service local_unbound setup" as root. - + 20150102: The GNU texinfo and GNU info pages have been removed. To be able to view GNU info pages please install texinfo from ports. @@ -619,7 +619,7 @@ NOTE TO PEOPLE WHO THINK THAT FreeBSD 11.x IS SLOW: The GNU Compiler Collection and C++ standard library (libstdc++) are no longer built by default on platforms where clang is the system compiler. You can enable them with the WITH_GCC and WITH_GNUCXX - options in src.conf. + options in src.conf. 20130905: The PROCDESC kernel option is now part of the GENERIC kernel @@ -973,7 +973,7 @@ NOTE TO PEOPLE WHO THINK THAT FreeBSD 11.x IS SLOW: 20120727: The sparc64 ZFS loader has been changed to no longer try to auto- detect ZFS providers based on diskN aliases but now requires these - to be explicitly listed in the OFW boot-device environment variable. + to be explicitly listed in the OFW boot-device environment variable. 20120712: The OpenSSL has been upgraded to 1.0.1c. Any binaries requiring diff --git a/bin/dd/dd.1 b/bin/dd/dd.1 index 1b4d57ef7189..0908642dd1cf 100644 --- a/bin/dd/dd.1 +++ b/bin/dd/dd.1 @@ -416,6 +416,7 @@ if necessary, to a 1MiB boundary: .Sh SEE ALSO .Xr cp 1 , .Xr mt 1 , +.Xr recoverdisk 1 , .Xr tr 1 , .Xr geom 4 .Sh STANDARDS diff --git a/bin/ls/Makefile b/bin/ls/Makefile index 3349b7ac4784..422d89116da4 100644 --- a/bin/ls/Makefile +++ b/bin/ls/Makefile @@ -5,12 +5,12 @@ PROG= ls SRCS= cmp.c ls.c print.c util.c -LIBADD= util +LIBADD= util xo .if !defined(RELEASE_CRUNCH) && \ ${MK_LS_COLORS} != no CFLAGS+= -DCOLORLS -LIBADD+= termcapw xo +LIBADD+= termcapw .endif .include diff --git a/bin/ls/ls.c b/bin/ls/ls.c index 926d2bccaef5..91ef9ea4e15a 100644 --- a/bin/ls/ls.c +++ b/bin/ls/ls.c @@ -119,7 +119,7 @@ static int f_nofollow; /* don't follow symbolic link arguments */ int f_nonprint; /* show unprintables as ? */ static int f_nosort; /* don't sort output */ int f_notabs; /* don't use tab-separated multi-col output */ -static int f_numericonly; /* don't convert uid/gid to name */ + int f_numericonly; /* don't convert uid/gid to name */ int f_octal; /* show unprintables as \xxx */ int f_octal_escape; /* like f_octal but use C escapes if possible */ static int f_recursive; /* ls subdirectories also */ @@ -158,6 +158,7 @@ main(int argc, char *argv[]) struct winsize win; int ch, fts_options, notused; char *p; + const char *errstr = NULL; #ifdef COLORLS char termcapbuf[1024]; /* termcap definition buffer */ char tcapbuf[512]; /* capability buffer */ @@ -170,7 +171,7 @@ main(int argc, char *argv[]) if (isatty(STDOUT_FILENO)) { termwidth = 80; if ((p = getenv("COLUMNS")) != NULL && *p != '\0') - termwidth = atoi(p); + termwidth = strtonum(p, 0, INT_MAX, &errstr); else if (ioctl(STDOUT_FILENO, TIOCGWINSZ, &win) != -1 && win.ws_col > 0) termwidth = win.ws_col; @@ -180,9 +181,12 @@ main(int argc, char *argv[]) /* retrieve environment variable, in case of explicit -C */ p = getenv("COLUMNS"); if (p) - termwidth = atoi(p); + termwidth = strtonum(p, 0, INT_MAX, &errstr); } + if (errstr) + termwidth = 80; + fts_options = FTS_PHYSICAL; if (getenv("LS_SAMESORT")) f_samesort = 1; @@ -191,6 +195,7 @@ main(int argc, char *argv[]) if (argc < 0) return (1); xo_set_flags(NULL, XOF_COLUMNS); + xo_set_version(LS_XO_VERSION); while ((ch = getopt(argc, argv, "1ABCD:FGHILPRSTUWXZabcdfghiklmnopqrstuwxy,")) != -1) { diff --git a/bin/ls/ls.h b/bin/ls/ls.h index 1a45eb4b04a8..e4867775b02b 100644 --- a/bin/ls/ls.h +++ b/bin/ls/ls.h @@ -37,6 +37,8 @@ #define HUMANVALSTR_LEN 5 +#define LS_XO_VERSION "1" + extern long blocksize; /* block size units */ extern int f_accesstime; /* use time of last access */ @@ -58,6 +60,7 @@ extern int f_statustime; /* use time of last mode change */ extern int f_thousands; /* show file sizes with thousands separators */ extern char *f_timeformat; /* user-specified time format */ extern int f_notabs; /* don't use tab-separated multi-col output */ +extern int f_numericonly; /* don't convert uid/gid to name */ extern int f_type; /* add type character for non-regular files */ #ifdef COLORLS extern int f_color; /* add type in color for non-regular files */ diff --git a/bin/ls/print.c b/bin/ls/print.c index 2d1425debf4e..08701c05134f 100644 --- a/bin/ls/print.c +++ b/bin/ls/print.c @@ -171,7 +171,7 @@ printlong(const DISPLAY *dp) xo_open_list("entry"); for (p = dp->list; p; p = p->fts_link) { - char *name; + char *name, *type; if (IS_NOPRINT(p)) continue; xo_open_instance("entry"); @@ -180,22 +180,46 @@ printlong(const DISPLAY *dp) if (name) xo_emit("{ke:name/%hs}", name); if (f_inode) - xo_emit("{:inode/%*ju} ", + xo_emit("{t:inode/%*ju} ", dp->s_inode, (uintmax_t)sp->st_ino); if (f_size) - xo_emit("{:blocks/%*jd} ", + xo_emit("{t:blocks/%*jd} ", dp->s_block, howmany(sp->st_blocks, blocksize)); strmode(sp->st_mode, buf); aclmode(buf, p); np = p->fts_pointer; xo_attr("value", "%03o", (int) sp->st_mode & ALLPERMS); - xo_emit("{t:mode/%s} {:links/%*u} {:user/%-*s} {:group/%-*s} ", - buf, dp->s_nlink, sp->st_nlink, - dp->s_user, np->user, dp->s_group, np->group); + if (f_numericonly) { + xo_emit("{t:mode/%s}{e:mode_octal/%03o} {t:links/%*u} {td:user/%-*s}{e:user/%ju} {td:group/%-*s}{e:group/%ju} ", + buf, (int) sp->st_mode & ALLPERMS, dp->s_nlink, sp->st_nlink, + dp->s_user, np->user, sp->st_uid, dp->s_group, np->group, sp->st_gid); + } else { + xo_emit("{t:mode/%s}{e:mode_octal/%03o} {t:links/%*u} {t:user/%-*s} {t:group/%-*s} ", + buf, (int) sp->st_mode & ALLPERMS, dp->s_nlink, sp->st_nlink, + dp->s_user, np->user, dp->s_group, np->group); + } + if (S_ISBLK(sp->st_mode)) + asprintf(&type, "block"); + if (S_ISCHR(sp->st_mode)) + asprintf(&type, "character"); + if (S_ISDIR(sp->st_mode)) + asprintf(&type, "directory"); + if (S_ISFIFO(sp->st_mode)) + asprintf(&type, "fifo"); + if (S_ISLNK(sp->st_mode)) + asprintf(&type, "symlink"); + if (S_ISREG(sp->st_mode)) + asprintf(&type, "regular"); + if (S_ISSOCK(sp->st_mode)) + asprintf(&type, "socket"); + if (S_ISWHT(sp->st_mode)) + asprintf(&type, "whiteout"); + xo_emit("{e:type/%s}", type); + free(type); if (f_flags) xo_emit("{:flags/%-*s} ", dp->s_flags, np->flags); if (f_label) - xo_emit("{:label/%-*s} ", dp->s_label, np->label); + xo_emit("{t:label/%-*s} ", dp->s_label, np->label); if (S_ISCHR(sp->st_mode) || S_ISBLK(sp->st_mode)) printdev(dp->s_size, sp->st_rdev); else @@ -238,6 +262,7 @@ printstream(const DISPLAY *dp) FTSENT *p; int chcnt; + xo_open_list("entry"); for (p = dp->list, chcnt = 0; p; p = p->fts_link) { if (p->fts_number == NO_PRINT) continue; @@ -247,12 +272,15 @@ printstream(const DISPLAY *dp) xo_emit("\n"); chcnt = 0; } + xo_open_instance("file"); chcnt += printaname(p, dp->s_inode, dp->s_block); + xo_close_instance("file"); if (p->fts_link) { xo_emit(", "); chcnt += 2; } } + xo_close_list("entry"); if (chcnt) xo_emit("\n"); } @@ -369,10 +397,10 @@ printaname(const FTSENT *p, u_long inodefield, u_long sizefield) sp = p->fts_statp; chcnt = 0; if (f_inode) - chcnt += xo_emit("{:inode/%*ju} ", + chcnt += xo_emit("{t:inode/%*ju} ", (int)inodefield, (uintmax_t)sp->st_ino); if (f_size) - chcnt += xo_emit("{:size/%*jd} ", + chcnt += xo_emit("{t:size/%*jd} ", (int)sizefield, howmany(sp->st_blocks, blocksize)); #ifdef COLORLS if (f_color) @@ -425,9 +453,11 @@ printtime(const char *field, time_t ftime) format = d_first ? "%e %b %Y" : "%b %e %Y"; strftime(longstring, sizeof(longstring), format, localtime(&ftime)); - snprintf(fmt, sizeof(fmt), "{:%s/%%hs} ", field); + snprintf(fmt, sizeof(fmt), "{d:%s/%%hs} ", field); xo_attr("value", "%ld", (long) ftime); xo_emit(fmt, longstring); + snprintf(fmt, sizeof(fmt), "{en:%s/%%ld} ", field); + xo_emit(fmt, (long) ftime); } static int diff --git a/bin/ps/ps.1 b/bin/ps/ps.1 index c777a6be2800..240fa20bae59 100644 --- a/bin/ps/ps.1 +++ b/bin/ps/ps.1 @@ -738,9 +738,9 @@ Display information on all system processes: .Xr procstat 1 , .Xr w 1 , .Xr kvm 3 , -.Xr libxo 3 +.Xr libxo 3 , .Xr strftime 3 , -.Xr xo_parse_args 3 +.Xr xo_parse_args 3 , .Xr mac 4 , .Xr procfs 5 , .Xr pstat 8 , diff --git a/bin/sh/sh.1 b/bin/sh/sh.1 index e5707c0ff721..e193d5da03c6 100644 --- a/bin/sh/sh.1 +++ b/bin/sh/sh.1 @@ -32,7 +32,7 @@ .\" from: @(#)sh.1 8.6 (Berkeley) 5/4/95 .\" $FreeBSD$ .\" -.Dd April 18, 2015 +.Dd July 11, 2015 .Dt SH 1 .Os .Sh NAME @@ -2846,6 +2846,4 @@ The utility does not recognize multibyte characters other than UTF-8. Splitting using .Va IFS -and the line editing library -.Xr editline 3 -do not recognize multibyte characters. +does not recognize multibyte characters. diff --git a/bin/stty/stty.c b/bin/stty/stty.c index b70f49fcad98..26e02e4d7297 100644 --- a/bin/stty/stty.c +++ b/bin/stty/stty.c @@ -47,6 +47,7 @@ __FBSDID("$FreeBSD$"); #include #include #include +#include #include #include #include @@ -61,7 +62,7 @@ main(int argc, char *argv[]) struct info i; enum FMT fmt; int ch; - const char *file; + const char *file, *errstr = NULL; fmt = NOTSET; i.fd = STDIN_FILENO; @@ -130,7 +131,9 @@ args: argc -= optind; if (isdigit(**argv)) { speed_t speed; - speed = atoi(*argv); + speed = strtonum(*argv, 0, UINT_MAX, &errstr); + if (errstr) + err(1, "speed"); cfsetospeed(&i.t, speed); cfsetispeed(&i.t, speed); i.set = 1; diff --git a/cddl/contrib/opensolaris/cmd/lockstat/lockstat.c b/cddl/contrib/opensolaris/cmd/lockstat/lockstat.c index 5c711600b06a..b59bee74f294 100644 --- a/cddl/contrib/opensolaris/cmd/lockstat/lockstat.c +++ b/cddl/contrib/opensolaris/cmd/lockstat/lockstat.c @@ -196,17 +196,17 @@ static ls_event_info_t g_event_info[LS_MAX_EVENTS] = { "lockstat:::spin-release", NULL, "lockstat:::spin-acquire" }, { 'H', "Lock", "R/W writer hold", "nsec", - "lockstat::rw_wunlock:rw-release", NULL, - "lockstat::rw_wlock:rw-acquire" }, + "lockstat:::rw-release", "arg1 == 0", + "lockstat:::rw-acquire" }, { 'H', "Lock", "R/W reader hold", "nsec", - "lockstat::rw_runlock:rw-release", NULL, - "lockstat::rw_rlock:rw-acquire" }, + "lockstat:::rw-release", "arg1 == 1", + "lockstat:::rw-acquire" }, { 'H', "Lock", "SX shared hold", "nsec", - "lockstat::sx_sunlock:sx-release", NULL, - "lockstat::sx_slock:sx-acquire" }, + "lockstat:::sx-release", "arg1 == 0", + "lockstat:::sx-acquire" }, { 'H', "Lock", "SX exclusive hold", "nsec", - "lockstat::sx_xunlock:sx-release", NULL, - "lockstat::sx_xlock:sx-acquire" }, + "lockstat:::sx-release", "arg1 == 1", + "lockstat:::sx-acquire" }, { 'H', "Lock", "Unknown event (type 38)", "units" }, { 'H', "Lock", "Unknown event (type 39)", "units" }, { 'H', "Lock", "Unknown event (type 40)", "units" }, diff --git a/contrib/sqlite3/sqlite3.c b/contrib/sqlite3/sqlite3.c index a8922e482839..8a80dcd0c936 100644 --- a/contrib/sqlite3/sqlite3.c +++ b/contrib/sqlite3/sqlite3.c @@ -49487,9 +49487,9 @@ static void walIndexWriteHdr(Wal *pWal){ pWal->hdr.isInit = 1; pWal->hdr.iVersion = WALINDEX_MAX_VERSION; walChecksumBytes(1, (u8*)&pWal->hdr, nCksum, 0, pWal->hdr.aCksum); - memcpy((void *)&aHdr[1], (void *)&pWal->hdr, sizeof(WalIndexHdr)); + memcpy((void *)&aHdr[1], (const void *)&pWal->hdr, sizeof(WalIndexHdr)); walShmBarrier(pWal); - memcpy((void *)&aHdr[0], (void *)&pWal->hdr, sizeof(WalIndexHdr)); + memcpy((void *)&aHdr[0], (const void *)&pWal->hdr, sizeof(WalIndexHdr)); } /* diff --git a/crypto/openssh/ssh.c b/crypto/openssh/ssh.c index eb69b72b9fa1..1c0784a9f2c2 100644 --- a/crypto/openssh/ssh.c +++ b/crypto/openssh/ssh.c @@ -1001,6 +1001,23 @@ main(int ac, char **av) shorthost[strcspn(thishost, ".")] = '\0'; snprintf(portstr, sizeof(portstr), "%d", options.port); + /* Find canonic host name. */ + if (strchr(host, '.') == 0) { + struct addrinfo hints; + struct addrinfo *ai = NULL; + int errgai; + memset(&hints, 0, sizeof(hints)); + hints.ai_family = options.address_family; + hints.ai_flags = AI_CANONNAME; + hints.ai_socktype = SOCK_STREAM; + errgai = getaddrinfo(host, NULL, &hints, &ai); + if (errgai == 0) { + if (ai->ai_canonname != NULL) + host = xstrdup(ai->ai_canonname); + freeaddrinfo(ai); + } + } + if (options.local_command != NULL) { debug3("expanding LocalCommand: %s", options.local_command); cp = options.local_command; diff --git a/etc/defaults/periodic.conf b/etc/defaults/periodic.conf index c70bee2b3c5c..fbc5d0ae1ebd 100644 --- a/etc/defaults/periodic.conf +++ b/etc/defaults/periodic.conf @@ -357,8 +357,12 @@ if [ -z "${source_periodic_confs_defined}" ]; then *) return 0 ;; esac ;; + '') + # Script run manually. + return 0 + ;; *) - echo "ASSERTION FAILED: Unexpected value for " \ + echo "ASSERTION FAILED: Unexpected value for" \ "\$PERIODIC: '$PERIODIC'" >&2 exit 127 ;; diff --git a/etc/devd.conf b/etc/devd.conf index 7a033a71dc48..04a090bdc805 100644 --- a/etc/devd.conf +++ b/etc/devd.conf @@ -296,7 +296,6 @@ detach 10 { # Button: Button pressed (0 for power, 1 for sleep) # CMBAT: ACPI battery events # Lid: Lid state (0 is closed, 1 is open) -# RCTL: Resource limits # Suspend, Resume: Suspend and resume notification # Thermal: ACPI thermal zone events # diff --git a/gnu/lib/Makefile b/gnu/lib/Makefile index 796cefcacc98..4fff36a48725 100644 --- a/gnu/lib/Makefile +++ b/gnu/lib/Makefile @@ -16,7 +16,7 @@ SUBDIR+= libssp SUBDIR+= tests .endif -.if ${MK_GDB} != "no" +.if ${MK_BINUTILS} != "no" && ${MK_GDB} != "no" SUBDIR+= libreadline .endif diff --git a/gnu/usr.bin/Makefile b/gnu/usr.bin/Makefile index 470b61220fa9..518000d65da7 100644 --- a/gnu/usr.bin/Makefile +++ b/gnu/usr.bin/Makefile @@ -16,6 +16,8 @@ SUBDIR= ${_binutils} \ sdiff \ ${_tests} +SUBDIR_DEPEND_gdb= ${_binutils} + .if ${MK_CXX} != "no" .if ${MK_GCC} != "no" _gperf= gperf @@ -39,13 +41,14 @@ _tests= tests .if ${MK_BINUTILS} != "no" _binutils= binutils -.endif -.if ${MK_GCC} != "no" -_cc= cc -.endif .if ${MK_GDB} != "no" _gdb= gdb .endif +.endif + +.if ${MK_GCC} != "no" +_cc= cc +.endif SUBDIR_PARALLEL= diff --git a/lib/libarchive/Makefile b/lib/libarchive/Makefile index 9dfad77aaf94..3870de2a40b9 100644 --- a/lib/libarchive/Makefile +++ b/lib/libarchive/Makefile @@ -37,12 +37,6 @@ CFLAGS+= -DPPMD_32BIT .endif NO_WCAST_ALIGN.clang= -.ifndef COMPAT_32BIT -beforeinstall: - ${INSTALL} -C -o ${LIBOWN} -g ${LIBGRP} -m ${LIBMODE} \ - ${.CURDIR}/libarchive.pc ${DESTDIR}${LIBDATADIR}/pkgconfig -.endif - .PATH: ${LIBARCHIVEDIR}/libarchive # Headers to be installed in /usr/include diff --git a/lib/libarchive/libarchive.pc b/lib/libarchive/libarchive.pc deleted file mode 100644 index 3aa1d0453cce..000000000000 --- a/lib/libarchive/libarchive.pc +++ /dev/null @@ -1,12 +0,0 @@ -# $FreeBSD$ -prefix=/usr -exec_prefix=${prefix} -libdir=${exec_prefix}/lib -includedir=${prefix}/include - -Name: libarchive -Description: library that can create and read several streaming archive formats -Version: 3.1.2 -Cflags: -I${includedir} -Libs: -L${libdir} -larchive -Libs.private: -lz -lbz2 -llzma -lbsdxml -lcrypto diff --git a/lib/libc/aarch64/Symbol.map b/lib/libc/aarch64/Symbol.map index 25e13f4ccad2..e47056a9d7a3 100644 --- a/lib/libc/aarch64/Symbol.map +++ b/lib/libc/aarch64/Symbol.map @@ -28,6 +28,7 @@ FBSD_1.0 { vfork; brk; sbrk; + makecontext; }; FBSDprivate_1.0 { @@ -35,4 +36,5 @@ FBSDprivate_1.0 { _end; curbrk; minbrk; + __makecontext; }; diff --git a/lib/libc/aarch64/gen/Makefile.inc b/lib/libc/aarch64/gen/Makefile.inc index bb70a36bf6e2..2ccc8340abb2 100644 --- a/lib/libc/aarch64/gen/Makefile.inc +++ b/lib/libc/aarch64/gen/Makefile.inc @@ -1,10 +1,12 @@ # $FreeBSD$ -SRCS+= fabs.S \ +SRCS+= _ctx_start.S \ + fabs.S \ flt_rounds.c \ fpgetmask.c \ fpsetmask.c \ ldexp.c \ + makecontext.c \ _setjmp.S \ _set_tp.c \ setjmp.S \ diff --git a/lib/libc/aarch64/gen/_ctx_start.S b/lib/libc/aarch64/gen/_ctx_start.S new file mode 100644 index 000000000000..8664f69667c3 --- /dev/null +++ b/lib/libc/aarch64/gen/_ctx_start.S @@ -0,0 +1,38 @@ +/*- + * Copyright (c) 2015 The FreeBSD Foundation + * All rights reserved. + * + * This software was developed by Andrew Turner under + * sponsorship from the FreeBSD Foundation. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +ENTRY(_ctx_start) + blr x19 /* Call func from makecontext */ + mov x0, x20 /* Load ucp saved in makecontext */ + bl _C_LABEL(ctx_done) + bl _C_LABEL(abort) +END(_ctx_start) diff --git a/lib/libc/aarch64/gen/makecontext.c b/lib/libc/aarch64/gen/makecontext.c new file mode 100644 index 000000000000..747d2c53b198 --- /dev/null +++ b/lib/libc/aarch64/gen/makecontext.c @@ -0,0 +1,86 @@ +/*- + * Copyright (c) 2015 The FreeBSD Foundation + * All rights reserved. + * + * This software was developed by Andrew Turner under + * sponsorship from the FreeBSD Foundation. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include + +#include + +#include +#include +#include +#include + +void _ctx_start(void); + +void +ctx_done(ucontext_t *ucp) +{ + + if (ucp->uc_link == NULL) { + exit(0); + } else { + setcontext((const ucontext_t *)ucp->uc_link); + abort(); + } +} + +__weak_reference(__makecontext, makecontext); + +void +__makecontext(ucontext_t *ucp, void (*func)(void), int argc, ...) +{ + struct gpregs *gp; + va_list ap; + int i; + + /* A valid context is required. */ + if (ucp == NULL) + return; + + if ((argc < 0) || (argc > 8)) + return; + + gp = &ucp->uc_mcontext.mc_gpregs; + + va_start(ap, argc); + /* Pass up to eight arguments in x0-7. */ + for (i = 0; i < argc && i < 8; i++) + gp->gp_x[i] = va_arg(ap, uint64_t); + va_end(ap); + + /* Set the stack */ + gp->gp_sp = STACKALIGN(ucp->uc_stack.ss_sp + ucp->uc_stack.ss_size); + /* Arrange for return via the trampoline code. */ + gp->gp_elr = (__register_t)_ctx_start; + gp->gp_x[19] = (__register_t)func; + gp->gp_x[20] = (__register_t)ucp; +} diff --git a/lib/libc/gen/syslog.3 b/lib/libc/gen/syslog.3 index 91404a3f2e12..b513adcd6343 100644 --- a/lib/libc/gen/syslog.3 +++ b/lib/libc/gen/syslog.3 @@ -28,7 +28,7 @@ .\" @(#)syslog.3 8.1 (Berkeley) 6/4/93 .\" $FreeBSD$ .\" -.Dd December 30, 2004 +.Dd July 21, 2015 .Dt SYSLOG 3 .Os .Sh NAME @@ -292,4 +292,4 @@ for later interpolation by .Pp Always use the proper secure idiom: .Pp -.Dl syslog("%s", string); +.Dl syslog(priority, "%s", string); diff --git a/lib/libc/gen/wordexp.3 b/lib/libc/gen/wordexp.3 index 02fc25312fe0..41b0d0c46df4 100644 --- a/lib/libc/gen/wordexp.3 +++ b/lib/libc/gen/wordexp.3 @@ -25,7 +25,7 @@ .\" .\" $FreeBSD$ .\" -.Dd July 29, 2004 +.Dd July 07, 2015 .Dt WORDEXP 3 .Os .Sh NAME @@ -202,5 +202,5 @@ but it does not use the same parser so it may be fooled. .Pp The current .Fn wordexp -implementation does not recognize multibyte characters, since the -shell (which it invokes to perform expansions) does not. +implementation does not recognize multibyte characters other than UTF-8, since +the shell (which it invokes to perform expansions) does not. diff --git a/lib/libc/sys/Makefile.inc b/lib/libc/sys/Makefile.inc index 5162563136d2..e672b69e7a43 100644 --- a/lib/libc/sys/Makefile.inc +++ b/lib/libc/sys/Makefile.inc @@ -235,6 +235,7 @@ MAN+= abort2.2 \ nanosleep.2 \ nfssvc.2 \ ntp_adjtime.2 \ + numa_getaffinity.2 \ open.2 \ pathconf.2 \ pdfork.2 \ @@ -395,6 +396,7 @@ MLINKS+=mount.2 nmount.2 \ MLINKS+=mq_receive.2 mq_timedreceive.2 MLINKS+=mq_send.2 mq_timedsend.2 MLINKS+=ntp_adjtime.2 ntp_gettime.2 +MLINKS+=numa_getaffinity.2 numa_setaffinity.2 MLINKS+=open.2 openat.2 MLINKS+=pathconf.2 fpathconf.2 MLINKS+=pathconf.2 lpathconf.2 diff --git a/lib/libc/sys/Symbol.map b/lib/libc/sys/Symbol.map index 194aa5bf0999..a3a613e24a44 100644 --- a/lib/libc/sys/Symbol.map +++ b/lib/libc/sys/Symbol.map @@ -400,6 +400,8 @@ FBSD_1.4 { futimens; ppoll; utimensat; + numa_setaffinity; + numa_getaffinity; }; FBSDprivate_1.0 { diff --git a/lib/libc/sys/madvise.2 b/lib/libc/sys/madvise.2 index 357e05ee7f8a..499bf67b8a91 100644 --- a/lib/libc/sys/madvise.2 +++ b/lib/libc/sys/madvise.2 @@ -28,7 +28,7 @@ .\" @(#)madvise.2 8.1 (Berkeley) 6/9/93 .\" $FreeBSD$ .\" -.Dd January 30, 2014 +.Dd July 12, 2015 .Dt MADVISE 2 .Os .Sh NAME @@ -79,9 +79,9 @@ pages in from backing store, but quickly map the pages already in memory into the calling process. .It Dv MADV_DONTNEED Allows the VM system to decrease the in-memory priority -of pages in the specified range. -Additionally future references to -this address range will incur a page fault. +of pages in the specified address range. +Consequently, future references to this address range are more likely +to incur a page fault. .It Dv MADV_FREE Gives the VM system the freedom to free pages, and tells the system that information in the specified page range diff --git a/lib/libc/sys/numa_getaffinity.2 b/lib/libc/sys/numa_getaffinity.2 new file mode 100644 index 000000000000..efb78e988210 --- /dev/null +++ b/lib/libc/sys/numa_getaffinity.2 @@ -0,0 +1,197 @@ +.\" Copyright (c) 2008 Christian Brueffer +.\" Copyright (c) 2008 Jeffrey Roberson +.\" Copyright (c) 2015 Adrian Chadd +.\" All rights reserved. +.\" +.\" Redistribution and use in source and binary forms, with or without +.\" modification, are permitted provided that the following conditions +.\" are met: +.\" 1. Redistributions of source code must retain the above copyright +.\" notice, this list of conditions and the following disclaimer. +.\" 2. Redistributions in binary form must reproduce the above copyright +.\" notice, this list of conditions and the following disclaimer in the +.\" documentation and/or other materials provided with the distribution. +.\" +.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +.\" SUCH DAMAGE. +.\" +.\" $FreeBSD$ +.\" +.Dd May 7, 2015 +.Dt NUMA_GETAFFINITY 2 +.Os +.Sh NAME +.Nm numa_getaffinity , +.Nm numa_setaffinity +.Nd manage NUMA affinity +.Sh LIBRARY +.Lb libc +.Sh SYNOPSIS +.In sys/param.h +.In sys/numa.h +.Ft int +.Fn numa_getaffinity "cpuwhich_t which" "id_t id" "struct vm_domain_policy_entry *policy" +.Ft int +.Fn numa_setaffinity "cpuwhich_t which" "id_t id" "const struct vm_domain_policy_entry *policy" +.Sh DESCRIPTION +.Fn numa_getaffinity +and +.Fn numa_setaffinity +allow the manipulation of NUMA policies available to processes and threads. +These functions may manipulate NUMA policies that contain many processes +or affect only a single object. +.Pp +Valid values for the +.Fa which +argument are documented in +.Xr cpuset 2 . +These arguments specify which object set are used. +Only +.Dv CPU_WHICH_TID +and +.Dv CPU_WHICH_PID +can be manipulated. +.Pp +The +.Fa policy +entry contains a vm_domain_policy_entry with the following fields: +.Bd -literal +struct vm_domain_policy_entry { + vm_domain_policy_type_t policy; /* VM policy */ + int domain; /* VM domain, if applicable */ +} +.Ed +.Fa vm_domain_policy_type_t policy +is one these: +.Bl -tag -width VM_POLICY_NONE +.It Dv VM_POLICY_NONE +Reset the domain back to none. +Any parent object NUMA domain policy will apply. +The only valid value for +.Dv domain +is -1. +.It Dv VM_POLICY_ROUND_ROBIN +Select round-robin policy. +Pages will be allocated round-robin from each VM domain in order. +The only valid value for +.Dv domain +is -1. +.It Dv VM_POLICY_FIXED_DOMAIN +Select fixed-domain only policy. +Pages will be allocated from the given +.Dv domain +which must be set to a valid VM domain. +Pages will not be allocated from another domain if +.Dv domain +is out of free pages. +.It Dv VM_POLICY_FIXED_DOMAIN_ROUND_ROBIN +Select fixed-domain only policy. +Pages will be allocated from +.Dv domain +which must be set to a valid VM domain. +If page allocation fails, pages will be round-robin +allocated from another domain if +.Dv domain +is out of free pages. +.It Dv VM_POLICY_FIRST_TOUCH +Select first-touch policy. +Pages will be allocated from the NUMA domain which the thread +is currently scheduled upon. +Pages will not be allocated from another domain if the current domain +is out of free pages. +The only valid value for +.Dv domain +is -1. +.It Dv VM_POLICY_FIRST_TOUCH_ROUND_ROBIN +Select first-touch policy. +Pages will be allocated from the NUMA domain which the thread +is currently scheduled upon. +Pages will be allocated round-robin from another domain if the +current domain is out of free pages. +The only valid value for +.Dv domain +is -1. +.El +.Pp +Note that the VM might assign some pages from other domains. +For example, if an existing page allocation is covered by a superpage +allocation. +.Pp +.Fn numa_getaffinity +retrieves the +NUMA policy from the object specified by +.Fa which +and +.Fa id +and stores it in the space provided by +.Fa policy . +.Pp +.Fn numa_setaffinity +attempts to set the NUMA policy for the object specified by +.Fa which +and +.Fa id +to the policy in +.Fa policy . +.Sh RETURN VALUES +.Rv -std +.Sh ERRORS +.Va errno +can contain these error codes: +.Bl -tag -width Er +.It Bq Er EINVAL +The +.Fa level +or +.Fa which +argument was not a valid value. +.It Bq Er EINVAL +The +.Fa policy +argument specified when calling +.Fn numa_setaffinity +did not contain a valid policy. +.It Bq Er EFAULT +The policy pointer passed was invalid. +.It Bq Er ESRCH +The object specified by the +.Fa id +and +.Fa which +arguments could not be found. +.It Bq Er ERANGE +The +.Fa domain +in the given policy +was out of the range of possible VM domains available. +.It Bq Er EPERM +The calling process did not have the credentials required to complete the +operation. +.El +.Sh SEE ALSO +.Xr cpuset 1 , +.Xr numactl 1 , +.Xr cpuset 2 , +.Xr cpuset_getaffinity 2 , +.Xr cpuset_getid 2 , +.Xr cpuset_setaffinity 2 , +.Xr cpuset_setid 2 , +.Xr pthread_affinity_np 3 , +.Xr pthread_attr_affinity_np 3 , +.Xr numa 4 +.Sh HISTORY +The +.Nm +family of system calls first appeared in +.Fx 11.0 . +.Sh AUTHORS +.An Adrian Chadd Aq Mt adrian@FreeBSD.org diff --git a/lib/libc/sys/wait.2 b/lib/libc/sys/wait.2 index 84b2b1a9d77d..a45e78a7bf22 100644 --- a/lib/libc/sys/wait.2 +++ b/lib/libc/sys/wait.2 @@ -362,6 +362,15 @@ field set to and the .Fa si_pid field set to the process ID of the process reporting status. +For the exited process, the +.Fa si_status +field of the +.Dv siginfo_t +structure contains the full 32 bit exit status passed to +.Xr _exit 2 ; +the +.Fa status +argument of other calls only returns 8 lowest bits of the exit status. .Pp When the .Dv WNOHANG @@ -656,13 +665,6 @@ is an extension; .Tn POSIX only permits this flag with .Fn waitid . -.Pp -.Tn POSIX -requires -.Fn waitid -to return the full 32 bits passed to -.Xr _exit 2 ; -this implementation only returns 8 bits like the other calls. .Sh HISTORY The .Fn wait diff --git a/lib/libc/tests/sys/Makefile b/lib/libc/tests/sys/Makefile index 5e457fd35c9d..89431bced322 100644 --- a/lib/libc/tests/sys/Makefile +++ b/lib/libc/tests/sys/Makefile @@ -12,9 +12,7 @@ NETBSD_ATF_TESTS_C+= clock_gettime_test NETBSD_ATF_TESTS_C+= connect_test NETBSD_ATF_TESTS_C+= dup_test NETBSD_ATF_TESTS_C+= fsync_test -.if ${MACHINE} != "arm64" # ARM64TODO: Missing makecontext NETBSD_ATF_TESTS_C+= getcontext_test -.endif NETBSD_ATF_TESTS_C+= getgroups_test NETBSD_ATF_TESTS_C+= getitimer_test NETBSD_ATF_TESTS_C+= getlogin_test diff --git a/lib/libkvm/kvm_proc.c b/lib/libkvm/kvm_proc.c index aed61a854919..bafe105513f7 100644 --- a/lib/libkvm/kvm_proc.c +++ b/lib/libkvm/kvm_proc.c @@ -66,6 +66,8 @@ __FBSDID("$FreeBSD$"); #include #include #include +#define _WANT_KW_EXITCODE +#include #include #include #include @@ -389,7 +391,7 @@ nopgrp: kp->ki_siglist = proc.p_siglist; SIGSETOR(kp->ki_siglist, mtd.td_siglist); kp->ki_sigmask = mtd.td_sigmask; - kp->ki_xstat = proc.p_xstat; + kp->ki_xstat = KW_EXITCODE(proc.p_xexit, proc.p_xsig); kp->ki_acflag = proc.p_acflag; kp->ki_lock = proc.p_lock; if (proc.p_state != PRS_ZOMBIE) { diff --git a/lib/libmd/Makefile b/lib/libmd/Makefile index 61bea29c96b1..c1f6eb9a03af 100644 --- a/lib/libmd/Makefile +++ b/lib/libmd/Makefile @@ -48,7 +48,8 @@ CLEANFILES+= md[245]hl.c md[245].ref md[245].3 mddriver \ # in which case: # * macros are used to rename symbols to libcrypt internal names # * no weak aliases are generated -CFLAGS+= -I${.CURDIR} -DWEAK_REFS +CFLAGS+= -I${.CURDIR} -I${.CURDIR}/../../sys/crypto/sha2 +CFLAGS+= -DWEAK_REFS .PATH: ${.CURDIR}/${MACHINE_ARCH} ${.CURDIR}/../../sys/crypto/sha2 .if exists(${MACHINE_ARCH}/sha.S) diff --git a/lib/libmd/sha256c.c b/lib/libmd/sha256c.c deleted file mode 100644 index 4227b0cfbfbb..000000000000 --- a/lib/libmd/sha256c.c +++ /dev/null @@ -1,312 +0,0 @@ -/*- - * Copyright 2005 Colin Percival - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include - -#include - -#include "sha256.h" - -#if BYTE_ORDER == BIG_ENDIAN - -/* Copy a vector of big-endian uint32_t into a vector of bytes */ -#define be32enc_vect(dst, src, len) \ - memcpy((void *)dst, (const void *)src, (size_t)len) - -/* Copy a vector of bytes into a vector of big-endian uint32_t */ -#define be32dec_vect(dst, src, len) \ - memcpy((void *)dst, (const void *)src, (size_t)len) - -#else /* BYTE_ORDER != BIG_ENDIAN */ - -/* - * Encode a length len/4 vector of (uint32_t) into a length len vector of - * (unsigned char) in big-endian form. Assumes len is a multiple of 4. - */ -static void -be32enc_vect(unsigned char *dst, const uint32_t *src, size_t len) -{ - size_t i; - - for (i = 0; i < len / 4; i++) - be32enc(dst + i * 4, src[i]); -} - -/* - * Decode a big-endian length len vector of (unsigned char) into a length - * len/4 vector of (uint32_t). Assumes len is a multiple of 4. - */ -static void -be32dec_vect(uint32_t *dst, const unsigned char *src, size_t len) -{ - size_t i; - - for (i = 0; i < len / 4; i++) - dst[i] = be32dec(src + i * 4); -} - -#endif /* BYTE_ORDER != BIG_ENDIAN */ - -/* Elementary functions used by SHA256 */ -#define Ch(x, y, z) ((x & (y ^ z)) ^ z) -#define Maj(x, y, z) ((x & (y | z)) | (y & z)) -#define SHR(x, n) (x >> n) -#define ROTR(x, n) ((x >> n) | (x << (32 - n))) -#define S0(x) (ROTR(x, 2) ^ ROTR(x, 13) ^ ROTR(x, 22)) -#define S1(x) (ROTR(x, 6) ^ ROTR(x, 11) ^ ROTR(x, 25)) -#define s0(x) (ROTR(x, 7) ^ ROTR(x, 18) ^ SHR(x, 3)) -#define s1(x) (ROTR(x, 17) ^ ROTR(x, 19) ^ SHR(x, 10)) - -/* SHA256 round function */ -#define RND(a, b, c, d, e, f, g, h, k) \ - t0 = h + S1(e) + Ch(e, f, g) + k; \ - t1 = S0(a) + Maj(a, b, c); \ - d += t0; \ - h = t0 + t1; - -/* Adjusted round function for rotating state */ -#define RNDr(S, W, i, k) \ - RND(S[(64 - i) % 8], S[(65 - i) % 8], \ - S[(66 - i) % 8], S[(67 - i) % 8], \ - S[(68 - i) % 8], S[(69 - i) % 8], \ - S[(70 - i) % 8], S[(71 - i) % 8], \ - W[i] + k) - -/* - * SHA256 block compression function. The 256-bit state is transformed via - * the 512-bit input block to produce a new state. - */ -static void -SHA256_Transform(uint32_t * state, const unsigned char block[64]) -{ - uint32_t W[64]; - uint32_t S[8]; - uint32_t t0, t1; - int i; - - /* 1. Prepare message schedule W. */ - be32dec_vect(W, block, 64); - for (i = 16; i < 64; i++) - W[i] = s1(W[i - 2]) + W[i - 7] + s0(W[i - 15]) + W[i - 16]; - - /* 2. Initialize working variables. */ - memcpy(S, state, 32); - - /* 3. Mix. */ - RNDr(S, W, 0, 0x428a2f98); - RNDr(S, W, 1, 0x71374491); - RNDr(S, W, 2, 0xb5c0fbcf); - RNDr(S, W, 3, 0xe9b5dba5); - RNDr(S, W, 4, 0x3956c25b); - RNDr(S, W, 5, 0x59f111f1); - RNDr(S, W, 6, 0x923f82a4); - RNDr(S, W, 7, 0xab1c5ed5); - RNDr(S, W, 8, 0xd807aa98); - RNDr(S, W, 9, 0x12835b01); - RNDr(S, W, 10, 0x243185be); - RNDr(S, W, 11, 0x550c7dc3); - RNDr(S, W, 12, 0x72be5d74); - RNDr(S, W, 13, 0x80deb1fe); - RNDr(S, W, 14, 0x9bdc06a7); - RNDr(S, W, 15, 0xc19bf174); - RNDr(S, W, 16, 0xe49b69c1); - RNDr(S, W, 17, 0xefbe4786); - RNDr(S, W, 18, 0x0fc19dc6); - RNDr(S, W, 19, 0x240ca1cc); - RNDr(S, W, 20, 0x2de92c6f); - RNDr(S, W, 21, 0x4a7484aa); - RNDr(S, W, 22, 0x5cb0a9dc); - RNDr(S, W, 23, 0x76f988da); - RNDr(S, W, 24, 0x983e5152); - RNDr(S, W, 25, 0xa831c66d); - RNDr(S, W, 26, 0xb00327c8); - RNDr(S, W, 27, 0xbf597fc7); - RNDr(S, W, 28, 0xc6e00bf3); - RNDr(S, W, 29, 0xd5a79147); - RNDr(S, W, 30, 0x06ca6351); - RNDr(S, W, 31, 0x14292967); - RNDr(S, W, 32, 0x27b70a85); - RNDr(S, W, 33, 0x2e1b2138); - RNDr(S, W, 34, 0x4d2c6dfc); - RNDr(S, W, 35, 0x53380d13); - RNDr(S, W, 36, 0x650a7354); - RNDr(S, W, 37, 0x766a0abb); - RNDr(S, W, 38, 0x81c2c92e); - RNDr(S, W, 39, 0x92722c85); - RNDr(S, W, 40, 0xa2bfe8a1); - RNDr(S, W, 41, 0xa81a664b); - RNDr(S, W, 42, 0xc24b8b70); - RNDr(S, W, 43, 0xc76c51a3); - RNDr(S, W, 44, 0xd192e819); - RNDr(S, W, 45, 0xd6990624); - RNDr(S, W, 46, 0xf40e3585); - RNDr(S, W, 47, 0x106aa070); - RNDr(S, W, 48, 0x19a4c116); - RNDr(S, W, 49, 0x1e376c08); - RNDr(S, W, 50, 0x2748774c); - RNDr(S, W, 51, 0x34b0bcb5); - RNDr(S, W, 52, 0x391c0cb3); - RNDr(S, W, 53, 0x4ed8aa4a); - RNDr(S, W, 54, 0x5b9cca4f); - RNDr(S, W, 55, 0x682e6ff3); - RNDr(S, W, 56, 0x748f82ee); - RNDr(S, W, 57, 0x78a5636f); - RNDr(S, W, 58, 0x84c87814); - RNDr(S, W, 59, 0x8cc70208); - RNDr(S, W, 60, 0x90befffa); - RNDr(S, W, 61, 0xa4506ceb); - RNDr(S, W, 62, 0xbef9a3f7); - RNDr(S, W, 63, 0xc67178f2); - - /* 4. Mix local working variables into global state */ - for (i = 0; i < 8; i++) - state[i] += S[i]; -} - -static unsigned char PAD[64] = { - 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -}; - -/* Add padding and terminating bit-count. */ -static void -SHA256_Pad(SHA256_CTX * ctx) -{ - unsigned char len[8]; - uint32_t r, plen; - - /* - * Convert length to a vector of bytes -- we do this now rather - * than later because the length will change after we pad. - */ - be64enc(len, ctx->count); - - /* Add 1--64 bytes so that the resulting length is 56 mod 64 */ - r = (ctx->count >> 3) & 0x3f; - plen = (r < 56) ? (56 - r) : (120 - r); - SHA256_Update(ctx, PAD, (size_t)plen); - - /* Add the terminating bit-count */ - SHA256_Update(ctx, len, 8); -} - -/* SHA-256 initialization. Begins a SHA-256 operation. */ -void -SHA256_Init(SHA256_CTX * ctx) -{ - - /* Zero bits processed so far */ - ctx->count = 0; - - /* Magic initialization constants */ - ctx->state[0] = 0x6A09E667; - ctx->state[1] = 0xBB67AE85; - ctx->state[2] = 0x3C6EF372; - ctx->state[3] = 0xA54FF53A; - ctx->state[4] = 0x510E527F; - ctx->state[5] = 0x9B05688C; - ctx->state[6] = 0x1F83D9AB; - ctx->state[7] = 0x5BE0CD19; -} - -/* Add bytes into the hash */ -void -SHA256_Update(SHA256_CTX * ctx, const void *in, size_t len) -{ - uint64_t bitlen; - uint32_t r; - const unsigned char *src = in; - - /* Number of bytes left in the buffer from previous updates */ - r = (ctx->count >> 3) & 0x3f; - - /* Convert the length into a number of bits */ - bitlen = len << 3; - - /* Update number of bits */ - ctx->count += bitlen; - - /* Handle the case where we don't need to perform any transforms */ - if (len < 64 - r) { - memcpy(&ctx->buf[r], src, len); - return; - } - - /* Finish the current block */ - memcpy(&ctx->buf[r], src, 64 - r); - SHA256_Transform(ctx->state, ctx->buf); - src += 64 - r; - len -= 64 - r; - - /* Perform complete blocks */ - while (len >= 64) { - SHA256_Transform(ctx->state, src); - src += 64; - len -= 64; - } - - /* Copy left over data into buffer */ - memcpy(ctx->buf, src, len); -} - -/* - * SHA-256 finalization. Pads the input data, exports the hash value, - * and clears the context state. - */ -void -SHA256_Final(unsigned char digest[32], SHA256_CTX * ctx) -{ - - /* Add padding */ - SHA256_Pad(ctx); - - /* Write the hash */ - be32enc_vect(digest, ctx->state, 32); - - /* Clear the context state */ - memset((void *)ctx, 0, sizeof(*ctx)); -} - -#ifdef WEAK_REFS -/* When building libmd, provide weak references. Note: this is not - activated in the context of compiling these sources for internal - use in libcrypt. - */ -#undef SHA256_Init -__weak_reference(_libmd_SHA256_Init, SHA256_Init); -#undef SHA256_Update -__weak_reference(_libmd_SHA256_Update, SHA256_Update); -#undef SHA256_Final -__weak_reference(_libmd_SHA256_Final, SHA256_Final); -#undef SHA256_Transform -__weak_reference(_libmd_SHA256_Transform, SHA256_Transform); -#endif diff --git a/lib/libusb/libusb20_desc.c b/lib/libusb/libusb20_desc.c index c5cfc9df1056..a40318246d00 100644 --- a/lib/libusb/libusb20_desc.c +++ b/lib/libusb/libusb20_desc.c @@ -137,15 +137,13 @@ libusb20_parse_config_desc(const void *config_desc) * Make a copy of the config descriptor, so that the caller can free * the inital config descriptor pointer! */ - ptr = (void *)(lub_endpoint + nendpoint); - memcpy(LIBUSB20_ADD_BYTES(ptr, 0), config_desc, pcdesc.len); + memcpy((void *)(lub_endpoint + nendpoint), config_desc, pcdesc.len); + + ptr = (const void *)(lub_endpoint + nendpoint); pcdesc.ptr = LIBUSB20_ADD_BYTES(ptr, 0); - config_desc = LIBUSB20_ADD_BYTES(ptr, 0); /* init config structure */ - ptr = config_desc; - LIBUSB20_INIT(LIBUSB20_CONFIG_DESC, &lub_config->desc); if (libusb20_me_decode(ptr, ptr[0], &lub_config->desc)) { diff --git a/lib/msun/man/cacos.3 b/lib/msun/man/cacos.3 index 0bf3f0fd4263..02f3f7454791 100644 --- a/lib/msun/man/cacos.3 +++ b/lib/msun/man/cacos.3 @@ -24,7 +24,7 @@ .\" .\" $FreeBSD$ .\" -.Dd May 27, 2013 +.Dd Jul 14, 2015 .Dt CACOS 3 .Os .Sh NAME @@ -98,11 +98,7 @@ functions perform the same operations in .Fa float precision. .Pp -.ie '\*[.T]'utf8' -. ds Un \[cu] -.el -. ds Un U -. +.ds Un \[cu] There is no universal convention for defining the principal values of these functions. The following table gives the branch cuts, and the corresponding ranges for the return values, adopted by the C language. diff --git a/release/Makefile.vagrant b/release/Makefile.vagrant index 307e21f72745..7ae64849e0ce 100644 --- a/release/Makefile.vagrant +++ b/release/Makefile.vagrant @@ -6,8 +6,7 @@ # VAGRANT_IMG?= ${.OBJDIR}/vagrant.vmdk -VAGRANT_UPLOAD_TGTS= vagrant-check-depends \ - atlas-do-upload +VAGRANT_UPLOAD_TGTS= vagrant-check-depends CLEANFILES+= ${VAGRANT_UPLOAD_TGTS} .if defined(VAGRANT_UPLOAD_CONF) && !empty(VAGRANT_UPLOAD_CONF) @@ -18,16 +17,20 @@ ATLAS${VAR}:= ${VAGRANT${VAR}} .endif .if ${BRANCH} == "STABLE" || ${BRANCH} == "CURRENT" || ${BRANCH} == "PRERELEASE" -SNAPSHOT_DATE!= date +-%Y-%m-%d +SNAPSHOT_DATE!= date +%Y%m%d .endif -VAGRANT_VERSION?= ${REVISION}-${BRANCH}${SNAPSHOT_DATE} +VAGRANT_VERSION!= date +%Y.%m.%d +VAGRANT_TARGET:= ${OSRELEASE}-${SNAPSHOT_DATE} +.if !empty(CLOUDWARE) +. for _PROVIDER in ${CLOUDWARE} +. if ${_PROVIDER:MVAGRANT*} +VAGRANT_PROVIDERS+= ${_PROVIDER:S/VAGRANT-//:tl} +. endif +. endfor +.endif +VAGRANT_PROVIDERS?= vmware virtualbox -VAGRANT_TARGET:= ${OSRELEASE}${SNAPSHOT_DATE}.box -VAGRANT_PROVIDERS?= vmware_desktop -#VAGRANT_PROVIDERS+= virtualbox - -vagrant-upload: ${VAGRANT_UPLOAD_TGTS} vagrant-check-depends: .for VAR in _KEY _USERNAME _VERSION @@ -47,48 +50,73 @@ vagrant-check-depends: . endif .endif -vagrant-do-package: cw-vagrant - -vagrant-do-package-vmware: vagrant-create-vmware-vmx vagrant-do-package - @cd ${.OBJDIR} && echo '{"provider":"vmware_desktop"}' > metadata.json - cd ${.OBJDIR} && tar -czf ${VAGRANT_TARGET} metadata.json vagrant.vmx vagrant.vmdk - touch ${.OBJDIR}/${.TARGET} - -atlas-do-upload: vagrant-do-package-vmware .for PROVIDER in ${VAGRANT_PROVIDERS} - ${.CURDIR}/scripts/atlas-upload.sh -b FreeBSD-${REVISION}-${BRANCH} -f ${VAGRANT_TARGET} -p ${PROVIDER} -k ${VAGRANT_KEY} -u ${VAGRANT_USERNAME} -v ${VAGRANT_VERSION} -.endfor - touch ${.OBJDIR}/${.TARGET} +CLEANFILES+= vagrant-do-package-${PROVIDER} ${VAGRANT_TARGET}.${PROVIDER}.box +CLEANDIRS+= ${PROVIDER} +VAGRANT_UPLOAD_TGTS+= vagrant-do-upload-${PROVIDER} -vagrant-create-vmware-vmx: - @cd ${.OBJDIR} && echo '.encoding = "UTF-8"' > vagrant.vmx - @cd ${.OBJDIR} && echo 'bios.bootorder = "hdd,CDROM"' >> vagrant.vmx - @cd ${.OBJDIR} && echo 'checkpoint.vmstate = ""' >> vagrant.vmx - @cd ${.OBJDIR} && echo 'cleanshutdown = "TRUE"' >> vagrant.vmx - @cd ${.OBJDIR} && echo 'config.version = "8"' >> vagrant.vmx - @cd ${.OBJDIR} && echo 'displayname = "${VAGRANT_TARGET}"' >> vagrant.vmx - @cd ${.OBJDIR} && echo 'ethernet0.addresstype = "generated"' >> vagrant.vmx - @cd ${.OBJDIR} && echo 'ethernet0.bsdname = "en0"' >> vagrant.vmx - @cd ${.OBJDIR} && echo 'ethernet0.connectiontype = "nat"' >> vagrant.vmx - @cd ${.OBJDIR} && echo 'ethernet0.displayname = "Ethernet"' >> vagrant.vmx - @cd ${.OBJDIR} && echo 'ethernet0.linkstatepropagation.enable = "FALSE"' >> vagrant.vmx - @cd ${.OBJDIR} && echo 'ethernet0.pcislotnumber = "33"' >> vagrant.vmx - @cd ${.OBJDIR} && echo 'ethernet0.present = "TRUE"' >> vagrant.vmx - @cd ${.OBJDIR} && echo 'ethernet0.virtualdev = "e1000"' >> vagrant.vmx - @cd ${.OBJDIR} && echo 'ethernet0.wakeonpcktrcv = "FALSE"' >> vagrant.vmx - @cd ${.OBJDIR} && echo 'floppy0.present = "FALSE"' >> vagrant.vmx - @cd ${.OBJDIR} && echo 'guestos = "freebsd-64"' >> vagrant.vmx - @cd ${.OBJDIR} && echo 'gui.fullscreenatpoweron = "FALSE"' >> vagrant.vmx - @cd ${.OBJDIR} && echo 'gui.viewmodeatpoweron = "windowed"' >> vagrant.vmx - @cd ${.OBJDIR} && echo 'memsize = "512"' >> vagrant.vmx - @cd ${.OBJDIR} && echo 'sound.startconnected = "FALSE"' >> vagrant.vmx - @cd ${.OBJDIR} && echo 'softpoweroff = "TRUE"' >> vagrant.vmx - @cd ${.OBJDIR} && echo 'scsi0.pcislotnumber = "16"' >> vagrant.vmx - @cd ${.OBJDIR} && echo 'scsi0.present = "TRUE"' >> vagrant.vmx - @cd ${.OBJDIR} && echo 'scsi0.virtualdev = "lsilogic"' >> vagrant.vmx - @cd ${.OBJDIR} && echo 'scsi0:0.filename = "vagrant.vmdk"' >> vagrant.vmx - @cd ${.OBJDIR} && echo 'scsi0:0.present = "TRUE"' >> vagrant.vmx - @cd ${.OBJDIR} && echo 'tools.synctime = "TRUE"' >> vagrant.vmx - @cd ${.OBJDIR} && echo 'usb.present = "FALSE"' >> vagrant.vmx - @cd ${.OBJDIR} && echo 'virtualhw.productcompatibility = "hosted"' >> vagrant.vmx - @cd ${.OBJDIR} && echo 'virtualhw.version = "9"' >> vagrant.vmx +${PROVIDER}: + @mkdir -p ${PROVIDER} + +${VAGRANT_TARGET}.${PROVIDER}.box: ${PROVIDER} cw-vagrant-${PROVIDER} vagrant-create-${PROVIDER}-metadata + @echo "==> PACKAGING: ${VAGRANT_TARGET}.${PROVIDER}.box in `pwd`" + @cp vagrant-${PROVIDER}.vmdk ${PROVIDER}/vagrant.vmdk +. if ${PROVIDER} == "virtualbox" + @(cd ${.OBJDIR}/${PROVIDER} && echo '{"provider":"${PROVIDER}"}' > metadata.json) + @(cd ${.OBJDIR}/${PROVIDER} && tar -czf ../${VAGRANT_TARGET}.${PROVIDER}.box metadata.json box.ovf vagrant.vmdk) +. elif ${PROVIDER} == "vmware" + @(cd ${.OBJDIR}/${PROVIDER} && echo '{"provider":"${PROVIDER}_desktop"}' > metadata.json) + @(cd ${.OBJDIR}/${PROVIDER} && tar -czf ../${VAGRANT_TARGET}.${PROVIDER}.box metadata.json vagrant.vmx vagrant.vmdk) +. endif + +CLEANFILES+= vagrant-do-upload-${PROVIDER} +vagrant-do-upload-${PROVIDER}: ${VAGRANT_TARGET}.${PROVIDER}.box +. if ${PROVIDER} == "virtualbox" + ${.CURDIR}/scripts/atlas-upload.sh -b ${TYPE}-${REVISION}-${BRANCH} -f ${VAGRANT_TARGET}.${PROVIDER}.box -p ${PROVIDER} -k ${VAGRANT_KEY} -u ${VAGRANT_USERNAME} -v ${VAGRANT_VERSION} +. elif ${PROVIDER} == "vmware" + ${.CURDIR}/scripts/atlas-upload.sh -b ${TYPE}-${REVISION}-${BRANCH} -f ${VAGRANT_TARGET}.${PROVIDER}.box -p ${PROVIDER}_desktop -k ${VAGRANT_KEY} -u ${VAGRANT_USERNAME} -v ${VAGRANT_VERSION} +. endif + touch ${.OBJDIR}/${.TARGET} +.endfor + +vagrant-upload: ${VAGRANT_UPLOAD_TGTS} + +vagrant-create-virtualbox-metadata: virtualbox/box.ovf + +virtualbox/box.ovf: ${.CURDIR}/scripts/box.ovf + cp ${.ALLSRC} virtualbox/ + +vmware/vagrant.vmx: + @(cd vmware && echo '.encoding = "UTF-8"' > vagrant.vmx) + @(cd vmware && echo 'bios.bootorder = "hdd,CDROM"' >> vagrant.vmx) + @(cd vmware && echo 'checkpoint.vmstate = ""' >> vagrant.vmx) + @(cd vmware && echo 'cleanshutdown = "TRUE"' >> vagrant.vmx) + @(cd vmware && echo 'config.version = "8"' >> vagrant.vmx) + @(cd vmware && echo 'displayname = "${VAGRANT_TARGET}"' >> vagrant.vmx) + @(cd vmware && echo 'ethernet0.addresstype = "generated"' >> vagrant.vmx) + @(cd vmware && echo 'ethernet0.bsdname = "en0"' >> vagrant.vmx) + @(cd vmware && echo 'ethernet0.connectiontype = "nat"' >> vagrant.vmx) + @(cd vmware && echo 'ethernet0.displayname = "Ethernet"' >> vagrant.vmx) + @(cd vmware && echo 'ethernet0.linkstatepropagation.enable = "FALSE"' >> vagrant.vmx) + @(cd vmware && echo 'ethernet0.pcislotnumber = "33"' >> vagrant.vmx) + @(cd vmware && echo 'ethernet0.present = "TRUE"' >> vagrant.vmx) + @(cd vmware && echo 'ethernet0.virtualdev = "e1000"' >> vagrant.vmx) + @(cd vmware && echo 'ethernet0.wakeonpcktrcv = "FALSE"' >> vagrant.vmx) + @(cd vmware && echo 'floppy0.present = "FALSE"' >> vagrant.vmx) + @(cd vmware && echo 'guestos = "freebsd-64"' >> vagrant.vmx) + @(cd vmware && echo 'gui.fullscreenatpoweron = "FALSE"' >> vagrant.vmx) + @(cd vmware && echo 'gui.viewmodeatpoweron = "windowed"' >> vagrant.vmx) + @(cd vmware && echo 'memsize = "512"' >> vagrant.vmx) + @(cd vmware && echo 'sound.startconnected = "FALSE"' >> vagrant.vmx) + @(cd vmware && echo 'softpoweroff = "TRUE"' >> vagrant.vmx) + @(cd vmware && echo 'scsi0.pcislotnumber = "16"' >> vagrant.vmx) + @(cd vmware && echo 'scsi0.present = "TRUE"' >> vagrant.vmx) + @(cd vmware && echo 'scsi0.virtualdev = "lsilogic"' >> vagrant.vmx) + @(cd vmware && echo 'scsi0:0.filename = "vagrant.vmdk"' >> vagrant.vmx) + @(cd vmware && echo 'scsi0:0.present = "TRUE"' >> vagrant.vmx) + @(cd vmware && echo 'tools.synctime = "TRUE"' >> vagrant.vmx) + @(cd vmware && echo 'usb.present = "FALSE"' >> vagrant.vmx) + @(cd vmware && echo 'virtualhw.productcompatibility = "hosted"' >> vagrant.vmx) + @(cd vmware && echo 'virtualhw.version = "9"' >> vagrant.vmx) + +vagrant-create-vmware-metadata: vmware/vagrant.vmx diff --git a/release/Makefile.vm b/release/Makefile.vm index f6e7831445a7..b39d05520768 100644 --- a/release/Makefile.vm +++ b/release/Makefile.vm @@ -19,7 +19,8 @@ CLOUDWARE?= AZURE \ EC2 \ GCE \ OPENSTACK \ - VAGRANT + VAGRANT-VIRTUALBOX \ + VAGRANT-VMWARE AZURE_FORMAT= vhdf AZURE_DESC= Microsoft Azure platform image AZURE_DISK= ${OSRELEASE}.${AZURE_FORMAT} @@ -32,9 +33,12 @@ GCE_DISK= disk.${GCE_FORMAT} OPENSTACK_FORMAT=qcow2 OPENSTACK_DESC= OpenStack platform image OPENSTACK_DISK= ${OSRELEASE}.${OPENSTACK_FORMAT} -VAGRANT_FORMAT= vmdk -VAGRANT_DESC= Vagrant Image -VAGRANT_DISK= ${OSRELEASE}.${VAGRANT_FORMAT} +VAGRANT-VIRTUALBOX_FORMAT= vmdk +VAGRANT-VIRTUALBOX_DESC= Vagrant Image for VirtualBox +VAGRANT-VIRTUALBOX_DISK= ${OSRELEASE}.vbox.${VAGRANT_FORMAT} +VAGRANT-VMWARE_FORMAT= vmdk +VAGRANT-VMWARE_DESC= Vagrant Image for VMWare +VAGRANT-VMWARE_DISK= ${OSRELEASE}.vmware.${VAGRANT_FORMAT} .if defined(WITH_CLOUDWARE) && !empty(WITH_CLOUDWARE) && !empty(CLOUDWARE) . for _CW in ${CLOUDWARE} diff --git a/release/doc/en_US.ISO8859-1/relnotes/article.xml b/release/doc/en_US.ISO8859-1/relnotes/article.xml index 6e56ac08d33d..4a6e577305ef 100644 --- a/release/doc/en_US.ISO8859-1/relnotes/article.xml +++ b/release/doc/en_US.ISO8859-1/relnotes/article.xml @@ -295,6 +295,11 @@ has been updated to support UTF-8, which additionally provides unicode support to &man.sh.1;. + The + &man.mkimg.1; utility has been updated to support the + MBR EFI partition + type. + The &man.ptrace.2; system call has been updated include support for Altivec registers on &os;/&arch.powerpc;. @@ -306,6 +311,15 @@ devices. The &man.devctl.8; utility uses the new &man.devctl.3; library. + The &man.netstat.1; utility has been + updated to link against the &man.libxo.3; shared + library. + + A new flag, -c, has + been added to the &man.mkimg.1; utility, which allows + specifying the capacity of the target disk image. + The &man.uefisign.8; utility has been added. @@ -314,11 +328,6 @@ been updated to prevent fetching updated binary patches when a previous upgrade has not been thoroughly completed. - The &man.netstat.1; utility has been - updated to link against the &man.libxo.3; shared - library. - A regression in the &man.libarchive.3; library that would prevent a directory from being included in the archive when --one-file-system is used @@ -331,16 +340,22 @@ directory traversal when extracting an archive, similar to &man.tar.1;. + A race condition in &man.wc.1; that + would cause final results to be sent to &man.stderr.4; when + receiving the SIGINFO signal has been + fixed. + The &man.chflags.1;, &man.chgrp.1;, &man.chmod.1;, and &man.chown.8; utilities now affect symbolic links when the -R flag is specified, as documented in &man.symlink.7;. - A race condition in &man.wc.1; that - would cause final results to be sent to &man.stderr.4; when - receiving the SIGINFO signal has been - fixed. + The &man.date.1; utility has been + updated to print the modification time of the file passed as + an argument to the -r flag, improving + compatibility with the GNU &man.date.1; + utility behavior. The &man.pw.8; utility has been updated with a new flag, -R, that sets the root @@ -376,6 +391,10 @@ sponsor="&scaleengine;">The &man.fstyp.8; utility has been updated to be able to detect &man.zfs.8; and &man.geli.8; filesystems. + + The &man.w.1; utility has been updated + to display the full IPv6 remote address of the host from which + a user is connected. @@ -385,9 +404,6 @@ sponsor="&darpa_afrl;">&man.lldb.1; has been updated to upstream snapshot version r196259. - Timezone data files have been updated to - version 2013i. - &man.byacc.1; has been updated to version 20140101. @@ -407,9 +423,6 @@ Clang have been updated to version 3.4. - file has been - updated to version 5.22. - The binutils suite of utilities has been updated to include upstream patches that add new relocations for &arch.powerpc; @@ -465,8 +478,8 @@ &man.resolvconf.8; utility has been updated to version 3.7.0. - bmake has - been updated to version 20150606. + The &man.nc.1; utility has been updated + to the OpenBSD 5.7 version. The &man.acpi.4; subsystem has been updated to version 20150515. @@ -474,6 +487,12 @@ The &man.file.1; utility has been updated to version 5.23. + bmake has + been updated to version 20150606. + + Timezone data files have been updated to + version 2015e. + sendmail has been updated to 8.15.2. Starting with &os; 11.0 and sendmail 8.15, sendmail uses uncompressed IPv6 addresses by @@ -481,12 +500,12 @@ example, instead of ::1, it will be 0:0:0:0:0:0:0:1. This permits a zero subnet to have a more specific match, such as different map entries for - IPv6:0:0 vs IPv6:0. This change requires that configuration - data (including maps, files, classes, custom ruleset, etc.) - must use the same format, so make certain such configuration - data is upgrading. As a very simple check search for patterns - like 'IPv6:[0-9a-fA-F:]*::' and 'IPv6::'. To return to the - old behavior, set the m4 option + IPv6:0:0 versus IPv6:0. This change requires that + configuration data (including maps, files, classes, custom + ruleset, etc.) must use the same format, so make certain such + configuration data is upgrading. As a very simple check + search for patterns like 'IPv6:[0-9a-fA-F:]*::' and 'IPv6::'. + To return to the old behavior, set the m4 option confUSE_COMPRESSED_IPV6_ADDRESSES or the cf option UseCompressedIPv6Addresses. @@ -533,6 +552,11 @@ If LOCALBASE is unset, it defaults to /usr/local. + A new &man.rc.8; script, + growfs, has been added, which will resize + the root filesystem on boot if /firstboot + exists. + The mrouted &man.rc.8; script has been removed from the base system. An equivalent script is available from the 110.clean-tmps has been updated to avoid crossing filesystem mount boundaries when cleaning files in /tmp. + + A new + &man.periodic.8; script, + 510.status-world-kernel, has been added, + which evaluates the running userland and kernel versions from + the &man.uname.1; -U and + -K arguments, and prints an error if the + system userland and kernel are not in sync. @@ -592,6 +624,11 @@ providing a wrapper around the &man.gpio.4; kernel interface. + The + &man.procctl.2; system call has been updated to include + a facility for non-&man.init.8; processes to be declared as + the reaper of child processes and their decendants. + The futimens() and utimensat() system calls have been added. See &man.utimensat.2; for more information. @@ -670,6 +707,14 @@ and asttrapexit() functions instead of checking within addressed kernel space. + A kernel panic triggered when destroying + a &man.vnet.9; &man.jail.8; configured with &man.gif.4; has + been fixed. + + A kernel panic triggered when destroying + a &man.vnet.9; &man.jail.8; configured with &man.gre.4; has + been fixed. + A bug in &man.ipfw.4; that could potentially lead to a kernel panic when using &man.dummynet.4; at layer 2 has been fixed. @@ -732,6 +777,15 @@ system. + A new module for creating + rpi.dtb has been added for the Raspberry + Pi. + + The + rpi.dtb module is now installed to + /boot/dtb/ by + default for the Raspberry Pi system. + Kernel support for Vector-Scalar eXtension (VSX) found on POWER7 and POWER8 hardware @@ -742,6 +796,33 @@ &powerpc; processors has been overhaulded to improve concurrency. + A new module for creating + the dtb module for AM335x systems has + been added. + + The + PAE_TABLES kernel configuration option has + been added for &os;/&arch.i386;, which instructs &man.pmap.9; + to use PAE format for page tables. + + The SIFTR kernel + configuration has been added, allowing building &man.siftr.4; + statically into the kernel. + + The &arch.arm; boot loader, + ubldr, is now relocatable. In addition, + ubldr.bin is now created during build + time, which is a stripped binary with an entry point of + 0, providing the ability to specify the + load address by running go + ${loadaddr} in + u-boot. + + The &man.nvd.4; and &man.nvme.4; drivers are + now included in the GENERIC kernel + configuration by default. + A new kernel configuration option, EM_MULTIQUEUE, has been added which enables @@ -841,6 +922,11 @@ The drm code has been updated to match &linux; version 3.8.13. + The &man.psm.4; driver has been updated + to include improved support for newer Synaptics ® + touchpads and the ClickPad ® mouse on newer + Lenovo ™ laptops. + Support for the Freescale PCI Root Complex device has been added. @@ -928,6 +1014,11 @@ The &man.alc.4; driver has been updated to support AR816x and AR817x ethernet controllers. + The &man.pfil.9; interface default hash + has been changed from Jenkins to + Murmur3, providing a 3-percent performance + increase in packets-per-second. + The &man.vxlan.4; driver has been added, which creates a virtual Layer 2 (Ethernet) network overlaid in a Layer 3 (IP/UDP) network. The &man.vxlan.4; driver is @@ -939,9 +1030,20 @@ been split into two separate modules, &man.gre.4; and &man.me.4;. + The &man.ral.4; driver has been updated + to support the RT5390 and RT5392 chipsets. + + The &man.sfxge.4; driver has been + updated to support Solarflare Flareon Ultra 7000-series + chipsets. + The &man.em.4; driver has been updated with improved transmission queue hang detection. + + The &man.cdce.4; driver has been updated + to include support for the RTL8153 chipset. @@ -977,10 +1079,6 @@ driver has been updated to correct performance counter sampling on G4 (MPC74xxx) and G5 class processors. - The &man.hwpmc.4; - driver has been updated to support the Freescale e500 - core. - The OpenCrypto framework has been @@ -988,6 +1086,10 @@ AES-GCM modes, both of which have also been added to the &man.aesni.4; driver. + The &man.hwpmc.4; + driver has been updated to support the Freescale e500 + core. + The &man.ig4.4; driver has been added, providing support for the fourth generation &intel; I2C SMBus. @@ -1036,6 +1138,11 @@ I/O, and uses hardware virtualization extensions for all other tasks, without the need for emulation. + The &man.bhyve.8; hypervisor has been + updated to support &amd; processors with + SVM and AMD-V hardware + extensions. + The &man.virtio.console.4; driver has been added, which provides an interface to VirtIO console devices through a &man.tty.4; device. @@ -1083,6 +1190,16 @@ The &man.nand.4; device is enabled for ARM devices by default. + Support for the Exynos 5420 + Octa system has been added. + + The SMP + option has been enabled for all Exynos 5 systems supported by + &os;. + + Support for the Toradex + Apalis i.MX6 development board has been added. + An issue that could cause instability when detecting SD cards on the Raspberry Pi SOC has been fixed. @@ -1092,6 +1209,17 @@ frequency and voltage control on the Raspberry Pi SOC. + Support to turn off the + BeagleBone Black system with the &man.shutdown.8; + -p flag or by invoking &man.poweroff.8; has + been added. + + Audio transmission drivers + have been added for Digital Audio Multiplexer + (AUDMUXM), Smart Direct Memory Access + Controller (SDMA), and Syncronous Serial + Interface (SSI). + Initial support for the ARM AArch64 architecture has been added. @@ -1153,6 +1281,11 @@ is administered with the &man.automount.8; userland utility, and the &man.automountd.8; and &man.autounmountd.8; daemons. + + Support + for the timeo, actimeo, + noac, and proto options + have been added to &man.mount.nfs.8;. @@ -1173,6 +1306,11 @@ Support for the disklabel64 partitioning scheme has been added to &man.gpart.8;. + + Support for the + apple-boot, apple-hfs, + and apple-ufs MBR + partitioning schemes have been added to &man.gpart.8;. @@ -1185,6 +1323,15 @@ Boot Loader Changes + The + memory test run at boot time on &os;/&arch.amd64; platforms + has been disabled by default. + + A new &man.ttys.5; class, + 3wire, has been added. This is similar to + the existing terminal classes, but does not have a defined + baudrate. + The &man.vt.4; driver has been made the default system console driver. The &man.syscons.4; driver is still available, and can be enabled by adding @@ -1193,15 +1340,20 @@ entering set kern.vty=sc at the &man.loader.8; prompt. + Support for bzipfs + has been added to the EFI loader. + The boot loader has been updated to support entering the GELI passphrase before loading the kernel. To enable this behavior, add geom_eli_passphrase_prompt="YES" to &man.loader.conf.5;. - The - memory test run at boot time on &os;/&arch.amd64; platforms - has been disabled by default. + The &man.ttys.5; file for &os;/&arch.arm; has been + updated to enable ttyu1, + ttyu2, and ttyu3 by + default, if the callin port is an active console port. @@ -1369,6 +1521,18 @@ Release Engineering build tools have been updated to include support for building &os;/&arch.arm64; virtual machine and memory stick installation images. + + The + Release Engineering build tools have been updated to support + building &os;/&arch.arm; images without external utilities for + supported boards where a corresponding + u-boot port exists in the Ports + Collection. + + The + &os;/&arch.i386; memory stick installation images are now + created using the &man.mkimg.1; utility, matching the way + the &os;/&arch.amd64; images are created. diff --git a/release/doc/share/xml/sponsor.ent b/release/doc/share/xml/sponsor.ent index c9810614a9ea..6d954f6f6f33 100644 --- a/release/doc/share/xml/sponsor.ent +++ b/release/doc/share/xml/sponsor.ent @@ -27,6 +27,7 @@ + @@ -42,6 +43,7 @@ + diff --git a/release/picobsd/build/picobsd b/release/picobsd/build/picobsd index 61eaa2215d84..2b04be4709b0 100755 --- a/release/picobsd/build/picobsd +++ b/release/picobsd/build/picobsd @@ -532,7 +532,11 @@ do_links() { # rootdir varname # if no argument default to objdir/SHLIBDIRPREFIX for both find_progs() { # programs # logverbose "find_progs: called with $*" - local i=`realpath ${o_objdir:-${_SHLIBDIRPREFIX}/..}` + # rev.284898 removed _SHLIBDIRPREFIX so we need to reconstruct + # its value in i1 + local i1=${_SHLIBDIRPREFIX:-${l_objtree}/${SRC}/tmp} + local i=`realpath ${o_objdir:-${i1}/..}` + # default values for -L and -P local dir="-P $i" local ldir="-L $i" diff --git a/release/scripts/atlas-upload.sh b/release/scripts/atlas-upload.sh index 63a5ba16b741..bf1dbf116dbc 100755 --- a/release/scripts/atlas-upload.sh +++ b/release/scripts/atlas-upload.sh @@ -28,20 +28,23 @@ ATLAS_API_URL='' ATLAS_UPLOAD_URL='https://binstore.hashicorp.com' -VERSION_DESCRIPTION="FreeBSD Snapshot Build" +DESCRIPTION="FreeBSD Snapshot Build" usage() { echo "${0} usage:" - echo "-b box-name -f box-to-upload -k api-key -p provider -u user -v version" + echo "-b box-name -d 'box description' -f box-to-upload -k api-key -p provider -u user -v version" return 1 } main () { - while getopts "b:f:k:p:u:v:" arg; do + while getopts "b:d:f:k:p:u:v:" arg; do case "${arg}" in b) BOX="${OPTARG}" ;; + d) + DESCRIPTION="${OPTARG}" + ;; f) FILE="${OPTARG}" ;; @@ -83,6 +86,7 @@ main () { echo "Creating box: ${BOX}" /usr/local/bin/curl -s https://atlas.hashicorp.com/api/v1/boxes -X POST -d "box[name]=${BOX}" -d "access_token=${KEY}" > /dev/null /usr/local/bin/curl -s https://atlas.hashicorp.com/api/v1/box/${USERNAME}/${BOX} -X PUT -d "box[is_private]=false" -d "access_token=${KEY}" > /dev/null + /usr/local/bin/curl -s https://atlas.hashicorp.com/api/v1/box/${USERNAME}/${BOX} -X PUT -d "box[description]='${DESCRIPTION}'" -d "access_token=${KEY}" > /dev/null else echo "Box already exists" fi @@ -97,7 +101,7 @@ main () { if [ $? != 0 ]; then echo "Creating version: ${VERSION}" /usr/local/bin/curl -s https://atlas.hashicorp.com/api/v1/box/${USERNAME}/${BOX}/versions -X POST -d "version[version]=${VERSION}" -d "access_token=${KEY}" > /dev/null - /usr/local/bin/curl -s https://atlas.hashicorp.com/api/v1/box/${USERNAME}/${BOX}/version/${VERSION} -X PUT -d "version[description]=${VERSION_DESCRIPTION}" -d "access_token=${KEY}" > /dev/null + /usr/local/bin/curl -s https://atlas.hashicorp.com/api/v1/box/${USERNAME}/${BOX}/version/${VERSION} -X PUT -d "version[description]=${DESCRIPTION}" -d "access_token=${KEY}" > /dev/null VERSIONRESULT=$(/usr/local/bin/curl -s "https://atlas.hashicorp.com/api/v1/box/${USERNAME}/${BOX}/version/${VERSION}?access_token=${KEY}") echo $VERSIONRESULT | grep "\"version\":\"${VERSION}\"" > /dev/null if [ $? != 0 ]; then diff --git a/release/scripts/box.ovf b/release/scripts/box.ovf new file mode 100644 index 000000000000..571e36fb6ab5 --- /dev/null +++ b/release/scripts/box.ovf @@ -0,0 +1,226 @@ + + + + + + + List of the virtual disks used in the package + + + + Logical networks used in the package + + Logical network used by this appliance. + + + + A virtual machine + + The kind of installed guest operating system + FreeBSD_64 + FreeBSD_64 + + + Virtual hardware requirements for a virtual machine + + Virtual Hardware Family + 0 + freebsd + virtualbox-2.2 + + + 1 virtual CPU + Number of virtual CPUs + 1 virtual CPU + 1 + 3 + 1 + + + MegaBytes + 512 MB of memory + Memory Size + 512 MB of memory + 2 + 4 + 512 + + + 0 + ideController0 + IDE Controller + ideController0 + 3 + PIIX4 + 5 + + + 1 + ideController1 + IDE Controller + ideController1 + 4 + PIIX4 + 5 + + + 0 + disk1 + Disk Image + disk1 + /disk/vmdisk1 + 5 + 3 + 17 + + + true + Ethernet adapter on 'NAT' + NAT + Ethernet adapter on 'NAT' + 6 + E1000 + 10 + + + + Complete VirtualBox machine configuration in VirtualBox format + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/release/tools/arm.subr b/release/tools/arm.subr index 564d9b66b1db..511f0b9593a3 100644 --- a/release/tools/arm.subr +++ b/release/tools/arm.subr @@ -112,10 +112,6 @@ arm_install_base() { >> ${CHROOTDIR}/${DESTDIR}/etc/fstab echo "md /tmp mfs rw,noatime,-s30m 0 0" \ >> ${CHROOTDIR}/${DESTDIR}/etc/fstab - echo "md /var/log mfs rw,noatime,-s15m 0 0" \ - >> ${CHROOTDIR}/${DESTDIR}/etc/fstab - echo "md /var/tmp mfs rw,noatime,-s12m 0 0" \ - >> ${CHROOTDIR}/${DESTDIR}/etc/fstab local hostname hostname="$(echo ${KERNEL} | tr '[:upper:]' '[:lower:]')" diff --git a/release/tools/vagrant-virtualbox.conf b/release/tools/vagrant-virtualbox.conf new file mode 100644 index 000000000000..ff14674ca708 --- /dev/null +++ b/release/tools/vagrant-virtualbox.conf @@ -0,0 +1,18 @@ +#!/bin/sh +# +# $FreeBSD$ +# + +. ${WORLDDIR}/release/tools/vagrant.conf + +export VM_EXTRA_PACKAGES="${VM_EXTRA_PACKAGES} virtualbox-ose-additions" + +vm_extra_pre_umount () { + # VirtualBox first boot pkgs + echo 'firstboot_pkgs_list="sudo rsync virtualbox-ose-additions"' >> ${DESTDIR}/etc/rc.conf + echo 'vboxguest_enable="YES"' >> ${DESTDIR}/etc/rc.conf + echo 'vboxservice_enable="YES"' >> ${DESTDIR}/etc/rc.conf + + # Setup the Vagrant common items + vagrant_common +} diff --git a/release/tools/vagrant-vmware.conf b/release/tools/vagrant-vmware.conf new file mode 100644 index 000000000000..330892bc7b85 --- /dev/null +++ b/release/tools/vagrant-vmware.conf @@ -0,0 +1,22 @@ +#!/bin/sh +# +# $FreeBSD$ +# + +. ${WORLDDIR}/release/tools/vagrant.conf + +export VM_EXTRA_PACKAGES="${VM_EXTRA_PACKAGES} open-vm-tools-nox11" + +vm_extra_pre_umount () { + # VMWare first boot pkgs + echo 'firstboot_pkgs_list="sudo rsync open-vm-tools-nox11"' >> ${DESTDIR}/etc/rc.conf + + echo 'vmware_guest_vmblock_enable="YES"' >> ${DESTDIR}/etc/rc.conf + echo 'vmware_guest_vmhgfs_enable="YES"' >> ${DESTDIR}/etc/rc.conf + echo 'vmware_guest_vmmemctl_enable="YES"' >> ${DESTDIR}/etc/rc.conf + echo 'vmware_guest_vmxnet_enable="YES"' >> ${DESTDIR}/etc/rc.conf + echo 'vmware_guestd_enable="YES"' >> ${DESTDIR}/etc/rc.conf + + # Setup the Vagrant common items + vagrant_common +} diff --git a/release/tools/vagrant.conf b/release/tools/vagrant.conf index 7e629caa4549..5617b96fa17d 100644 --- a/release/tools/vagrant.conf +++ b/release/tools/vagrant.conf @@ -10,18 +10,15 @@ export VM_EXTRA_PACKAGES="firstboot-freebsd-update firstboot-pkgs" # Set to a list of third-party software to enable in rc.conf(5). export VM_RC_LIST="firstboot_freebsd_update firstboot_pkgs" -vm_extra_pre_umount() { +vagrant_common () { # The firstboot_pkgs rc.d script will download the repository # catalogue and install or update pkg when the instance first # launches, so these files would just be replaced anyway; removing # them from the image allows it to boot faster. + env ASSUME_ALWAYS_YES=yes pkg -c ${DESTDIR} clean -y -a env ASSUME_ALWAYS_YES=yes pkg -c ${DESTDIR} delete -f -y pkg rm ${DESTDIR}/var/db/pkg/repo-*.sqlite - # The size of the EC2 root disk can be configured at instance launch - # time; expand our filesystem to fill the disk. - echo 'growfs_enable="YES"' >> ${DESTDIR}/etc/rc.conf - # Vagrant instances use DHCP to get their network configuration. echo 'ifconfig_DEFAULT="SYNCDHCP"' >> ${DESTDIR}/etc/rc.conf @@ -36,9 +33,6 @@ vm_extra_pre_umount() { echo 'sendmail_outbound_enable="NO"' >> ${DESTDIR}/etc/rc.conf echo 'sendmail_msp_queue_enable="NO"' >> ${DESTDIR}/etc/rc.conf - # sudo is required - echo 'firstboot_pkgs_list="sudo rsync"' >> ${DESTDIR}/etc/rc.conf - # Create the vagrant user with a password of vagrant /usr/sbin/pw -R ${DESTDIR} \ groupadd vagrant -g 1001 diff --git a/sbin/devd/devd.conf.5 b/sbin/devd/devd.conf.5 index 3956a7389737..a174de859fc9 100644 --- a/sbin/devd/devd.conf.5 +++ b/sbin/devd/devd.conf.5 @@ -41,7 +41,7 @@ .\" ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS .\" SOFTWARE. .\" -.Dd May 13, 2015 +.Dd July 11, 2015 .Dt DEVD.CONF 5 .Os .Sh NAME @@ -332,10 +332,34 @@ Battery events. Lid state ($notify=0x00 is closed, 0x01 is open). .It Li PROCESSOR Processor state/configuration ($notify=0x81 is a change in available Cx states). +.It Li Resume +Resume notification. +.It Li Suspend +Suspend notification. .It Li Thermal Thermal zone events. .El .Pp +.It Li CARP +Events related to the +.Xr carp 8 +protocol. +.Bl -tag -width ".Sy Subsystem" -compact +.It Sy Subsystem +.It Ar vhid@interface +The +.Dq subsystem +contains the actual CARP vhid and the name of the network interface +on which the event took place. +.Bl -tag -width ".Li MASTER" -compact +.It Sy Type +.It Li MASTER +Node become the master for a virtual host. +.It Li BACKUP +Node become the backup for a virtual host. +.El +.El +.Pp .It Li IFNET Events related to the network subsystem. .Bl -tag -width ".Sy Subsystem" -compact diff --git a/sbin/geom/class/multipath/gmultipath.8 b/sbin/geom/class/multipath/gmultipath.8 index cdb2e8aae7db..94713a7bdeb3 100644 --- a/sbin/geom/class/multipath/gmultipath.8 +++ b/sbin/geom/class/multipath/gmultipath.8 @@ -24,7 +24,7 @@ .\" .\" $FreeBSD$ .\" -.Dd June 11, 2015 +.Dd July 18, 2015 .Dt GMULTIPATH 8 .Os .Sh NAME @@ -107,10 +107,10 @@ When using the .Dq manual method, no metadata are stored on the devices, so the multipath device has to be configured by hand every time it is needed. -Additional device paths also won't be detected automatically. +Additional device paths also will not be detected automatically. The .Dq automatic -method uses on-disk metadata to detect device and all it's paths. +method uses on-disk metadata to detect device and all its paths. Metadata use the last sector of the underlying disk device and include device name and UUID. The UUID guarantees uniqueness in a shared storage environment @@ -350,6 +350,14 @@ GEOM_MULTIPATH: da0 added to FRED GEOM_MULTIPATH: da0 is now active path in FRED GEOM_MULTIPATH: da2 added to FRED .Ed +.Pp +To load the +.Nm +module at boot time, add this entry to +.Pa /boot/loader.conf : +.Bd -literal -offset ident +geom_multipath_load="YES" +.Ed .Sh SEE ALSO .Xr geom 4 , .Xr isp 4 , diff --git a/sbin/geom/class/part/geom_part.c b/sbin/geom/class/part/geom_part.c index 133e8f8281e9..44309f925b77 100644 --- a/sbin/geom/class/part/geom_part.c +++ b/sbin/geom/class/part/geom_part.c @@ -1106,14 +1106,11 @@ gpart_write_partcode(struct ggeom *gp, int idx, void *code, ssize_t size) if (pp != NULL) { snprintf(dsf, sizeof(dsf), "/dev/%s", pp->lg_name); + if (pp->lg_mediasize < size) + errx(EXIT_FAILURE, "%s: not enough space", dsf); fd = open(dsf, O_WRONLY); if (fd == -1) err(EXIT_FAILURE, "%s", dsf); - if (lseek(fd, size, SEEK_SET) != size) - errx(EXIT_FAILURE, "%s: not enough space", dsf); - if (lseek(fd, 0, SEEK_SET) != 0) - err(EXIT_FAILURE, "%s", dsf); - /* * When writing to a disk device, the write must be * sector aligned and not write to any partial sectors, @@ -1152,11 +1149,11 @@ gpart_write_partcode_vtoc8(struct ggeom *gp, int idx, void *code) if (pp->lg_sectorsize != sizeof(struct vtoc8)) errx(EXIT_FAILURE, "%s: unexpected sector " "size (%d)\n", dsf, pp->lg_sectorsize); + if (pp->lg_mediasize < VTOC_BOOTSIZE) + continue; fd = open(dsf, O_WRONLY); if (fd == -1) err(EXIT_FAILURE, "%s", dsf); - if (lseek(fd, VTOC_BOOTSIZE, SEEK_SET) != VTOC_BOOTSIZE) - continue; /* * We ignore the first VTOC_BOOTSIZE bytes of boot code in * order to avoid overwriting the label. diff --git a/sbin/geom/class/part/gpart.8 b/sbin/geom/class/part/gpart.8 index 8e8f858432b8..354d844349b7 100644 --- a/sbin/geom/class/part/gpart.8 +++ b/sbin/geom/class/part/gpart.8 @@ -24,7 +24,7 @@ .\" .\" $FreeBSD$ .\" -.Dd May 5, 2015 +.Dd July 14, 2015 .Dt GPART 8 .Os .Sh NAME @@ -933,6 +933,12 @@ start-up script. See .Xr gptboot 8 for more details. +.It Cm lenovofix +Setting this attribute overwrites the Protective MBR with a new one where +the 0xee partition is the second, rather than the first record. +This resolves a BIOS compatibility issue with some Lenovo models including the +X220, T420, and T520, allowing them to boot from GPT partitioned disks +without using EFI. .El .Pp The scheme-specific attributes for MBR: diff --git a/sbin/ggate/ggatec/ggatec.8 b/sbin/ggate/ggatec/ggatec.8 index 8545bafb1e85..705d42f657c2 100644 --- a/sbin/ggate/ggatec/ggatec.8 +++ b/sbin/ggate/ggatec/ggatec.8 @@ -24,7 +24,7 @@ .\" .\" $FreeBSD$ .\" -.Dd April 2, 2015 +.Dd July 14, 2015 .Dt GGATEC 8 .Os .Sh NAME @@ -71,8 +71,8 @@ utility is a network client for the GEOM Gate class. It is responsible for the creation of .Nm ggate devices and forwarding I/O requests between the -.Nm geom_gate.ko -kernel module and the +.Nm GEOM Gate +kernel subsystem and the .Xr ggated 8 network daemon. Available commands: @@ -111,7 +111,7 @@ Do not use .Dv TCP_NODELAY option on TCP sockets. .It Fl o Cm ro | wo | rw -Specify permission to use when opening the file or device: read-only +Specify permissions to use when opening the file or device: read-only .Pq Cm ro , write-only .Pq Cm wo , @@ -136,7 +136,7 @@ Default is 131072 (128kB). Sector size for .Nm ggate provider. -If not specified, it is taken from device, or set to 512 bytes for files. +If not specified, it is taken from the device, or set to 512 bytes for files. .It Fl t Ar timeout Number of seconds to wait before an I/O request will be canceled. Default is 0, which means no timeout. diff --git a/sbin/ggate/ggatec/ggatec.c b/sbin/ggate/ggatec/ggatec.c index 6f9263c8c30d..ea4f701abafa 100644 --- a/sbin/ggate/ggatec/ggatec.c +++ b/sbin/ggate/ggatec/ggatec.c @@ -447,6 +447,7 @@ g_gatec_create(void) /* * Ok, got both sockets, time to create provider. */ + memset(&ggioc, 0, sizeof(ggioc)); ggioc.gctl_version = G_GATE_VERSION; ggioc.gctl_mediasize = mediasize; ggioc.gctl_sectorsize = sectorsize; diff --git a/sbin/ggate/ggated/ggated.8 b/sbin/ggate/ggated/ggated.8 index 3560fe0bc9b5..dd6109aa61ef 100644 --- a/sbin/ggate/ggated/ggated.8 +++ b/sbin/ggate/ggated/ggated.8 @@ -24,7 +24,7 @@ .\" .\" $FreeBSD$ .\" -.Dd April 29, 2004 +.Dd July 14, 2015 .Dt GGATED 8 .Os .Sh NAME @@ -43,14 +43,14 @@ .Sh DESCRIPTION The .Nm -utility is a network server for GEOM Gate class. +utility is a network server for the GEOM Gate class. It runs on a server machine to service GEOM Gate requests from workers placed on a client machine. -Keep in mind, that connection between +Keep in mind, that connections between .Xr ggatec 8 and .Nm -is not encrypted. +are not encrypted. .Pp Available options: .Bl -tag -width ".Ar exports\ file" @@ -65,7 +65,7 @@ option on TCP sockets. .It Fl p Ar port Port on which .Nm -listens for connection. +listens for connections. Default is 3080. .It Fl R Ar rcvbuf Size of receive buffer to use. @@ -74,7 +74,7 @@ Default is 131072 (128kB). Size of send buffer to use. Default is 131072 (128kB). .It Fl v -Do not fork, run in foreground and print debug informations on standard +Do not fork, run in foreground and print debug information on standard output. .It Ar "exports file" An alternate location for the exports file. diff --git a/sbin/ggate/ggated/ggated.c b/sbin/ggate/ggated/ggated.c index 01aa00aca645..a340f01b1b5f 100644 --- a/sbin/ggate/ggated/ggated.c +++ b/sbin/ggate/ggated/ggated.c @@ -906,8 +906,8 @@ handshake(struct sockaddr *from, int sfd) ex = exports_find(from, &cinit, conn); if (ex == NULL) { - connection_remove(conn); sendfail(sfd, errno, NULL); + connection_remove(conn); return (0); } if (conn->c_mediasize == 0) { diff --git a/sbin/ggate/ggatel/ggatel.8 b/sbin/ggate/ggatel/ggatel.8 index 37e11cd8b2d6..f2eea7cf3fd5 100644 --- a/sbin/ggate/ggatel/ggatel.8 +++ b/sbin/ggate/ggatel/ggatel.8 @@ -24,7 +24,7 @@ .\" .\" $FreeBSD$ .\" -.Dd April 9, 2015 +.Dd July 14, 2015 .Dt GGATEL 8 .Os .Sh NAME @@ -62,7 +62,7 @@ It can be used as a replacement for devices or as a .Dq GEOMificator for non GEOM-aware devices, but it was mainly created as an example -on how to use and how to communicate with the GEOM Gate kernel module. +on how to use and how to communicate with the GEOM Gate kernel subsystem. .Pp Available commands: .Bl -tag -width ".Cm destroy" @@ -82,7 +82,8 @@ providers. Take over a previously created provider and handle pending and future requests. This is useful if the initial .Nm -process died. To prevent data loss, the given path must lead to the +process died. +To prevent data loss, the given path must lead to the regular file or device that was used to create the provider. .El .Pp @@ -93,7 +94,7 @@ Forcibly destroy .Nm ggate provider (cancels all pending requests). .It Fl o Cm ro | wo | rw -Specify permission to use when opening the file or device: read-only +Specify permissions to use when opening the file or device: read-only .Pq Cm ro , write-only .Pq Cm wo , @@ -105,7 +106,7 @@ Default is Sector size for .Nm ggate provider. -If not specified, it is taken from device, or set to 512 bytes for files. +If not specified, it is taken from the device, or set to 512 bytes for files. .It Fl t Ar timeout Number of seconds to wait before an I/O request will be canceled. 0 means no timeout. @@ -131,7 +132,7 @@ the .Dq Li fd0 device and use .Xr gbde 8 -to encrypt data on a floppy. +to encrypt data on a floppy disk. .Bd -literal -offset indent ggatel create -u 5 /dev/fd0 gbde init /dev/ggate5 diff --git a/sbin/ggate/ggatel/ggatel.c b/sbin/ggate/ggatel/ggatel.c index abfe7c18e41d..0b89df091d2a 100644 --- a/sbin/ggate/ggatel/ggatel.c +++ b/sbin/ggate/ggatel/ggatel.c @@ -173,6 +173,7 @@ g_gatel_create(void) fd = open(path, g_gate_openflags(flags) | O_DIRECT | O_FSYNC); if (fd == -1) err(EXIT_FAILURE, "Cannot open %s", path); + memset(&ggioc, 0, sizeof(ggioc)); ggioc.gctl_version = G_GATE_VERSION; ggioc.gctl_unit = unit; ggioc.gctl_mediasize = g_gate_mediasize(fd); diff --git a/sbin/newfs/newfs.8 b/sbin/newfs/newfs.8 index a4c035814d6d..a4067e940862 100644 --- a/sbin/newfs/newfs.8 +++ b/sbin/newfs/newfs.8 @@ -28,7 +28,7 @@ .\" @(#)newfs.8 8.6 (Berkeley) 5/3/95 .\" $FreeBSD$ .\" -.Dd October 1, 2013 +.Dd July 15, 2015 .Dt NEWFS 8 .Os .Sh NAME @@ -152,7 +152,7 @@ The expected average number of files per directory on the file system. .It Fl i Ar bytes Specify the density of inodes in the file system. The default is to create an inode for every -.Pq 4 * Ar frag-size +.Pq 2 * Ar frag-size bytes of data space. If fewer inodes are desired, a larger number should be used; to create more inodes a smaller number should be given. @@ -173,7 +173,7 @@ Clustering the metadata blocks speeds up random file access and decreases the running time of .Xr fsck 8 . By default -.Xr newfs 8 +.Nm sets it to half of the space reserved to minfree. .It Fl l Enable multilabel MAC on the new file system. @@ -228,7 +228,7 @@ for more details on how to set this option. The partition name (a..h) you want to use in case the underlying image is a file, so you do not have access to individual partitions through the filesystem. -Can also be used with a device, e.g. +Can also be used with a device, e.g., .Nm .Fl p Ar f .Ar /dev/da1s3 diff --git a/sbin/pfctl/pfctl.c b/sbin/pfctl/pfctl.c index c1ba12f4c3cb..ea0064b02b7e 100644 --- a/sbin/pfctl/pfctl.c +++ b/sbin/pfctl/pfctl.c @@ -1924,7 +1924,7 @@ pfctl_test_altqsupport(int dev, int opts) if (ioctl(dev, DIOCGETALTQS, &pa)) { if (errno == ENODEV) { - if (!(opts & PF_OPT_QUIET)) + if (opts & PF_OPT_VERBOSE) fprintf(stderr, "No ALTQ support in kernel\n" "ALTQ related functions disabled\n"); return (0); diff --git a/share/man/man4/Makefile b/share/man/man4/Makefile index 498f905b2d7e..cd4c91b466b6 100644 --- a/share/man/man4/Makefile +++ b/share/man/man4/Makefile @@ -364,6 +364,7 @@ MAN= aac.4 \ nsp.4 \ ${_ntb.4} \ null.4 \ + numa.4 \ ${_nvd.4} \ ${_nvme.4} \ ${_nvram.4} \ diff --git a/share/man/man4/ctl.4 b/share/man/man4/ctl.4 index 005f90830d4b..e170766eb7d0 100644 --- a/share/man/man4/ctl.4 +++ b/share/man/man4/ctl.4 @@ -23,7 +23,7 @@ .\" SUCH DAMAGE. .\" .\" $FreeBSD$ -.Dd July 3, 2015 +.Dd July 11, 2015 .Dt CTL 4 .Os .Sh NAME @@ -100,11 +100,14 @@ Defaults to 1. The number of outstanding commands to advertise to the iSCSI initiator. Technically, it is the difference between ExpCmdSN and MaxCmdSN fields in the iSCSI PDU. +Defaults to 256. .It Va kern.cam.ctl.iscsi.ping_timeout The number of seconds to wait for the iSCSI initiator to respond to a NOP-In PDU. In the event that there is no response within that time the session gets forcibly terminated. +Set to 0 to disable sending NOP-In PDUs. +Defaults to 5. .Sh SEE ALSO .Xr ctladm 8 , .Xr ctld 8 , diff --git a/share/man/man4/iscsi.4 b/share/man/man4/iscsi.4 index 3605db1127b5..1a0731dc38d6 100644 --- a/share/man/man4/iscsi.4 +++ b/share/man/man4/iscsi.4 @@ -23,7 +23,7 @@ .\" SUCH DAMAGE. .\" .\" $FreeBSD$ -.Dd June 20, 2015 +.Dd July 11, 2015 .Dt ISCSI 4 .Os .Sh NAME @@ -77,20 +77,25 @@ The number of seconds to wait for the target to respond to a NOP-Out PDU. In the event that there is no response within that time the session gets forcibly restarted. +Set to 0 to disable sending NOP-Out PDUs. +Defaults to 5. .It Va kern.iscsi.iscsid_timeout The number of seconds to wait for -.Xr ctld 8 +.Xr iscsid 8 to establish a session. After that time .Nm will abort and retry. +Defaults to 60. .It Va kern.iscsi.login_timeout The number of seconds to wait for a login attempt to succeed. After that time .Nm will abort and retry. +Defaults to 60. .It Va kern.iscsi.maxtags The maximum number of outstanding IO requests. +Defaults to 255. .It Va kern.iscsi.fail_on_disconnection Controls the behavior after an iSCSI connection has been dropped due to network problems. diff --git a/share/man/man4/numa.4 b/share/man/man4/numa.4 new file mode 100644 index 000000000000..984c4649df14 --- /dev/null +++ b/share/man/man4/numa.4 @@ -0,0 +1,172 @@ +.\" Copyright (c) 2015 Adrian Chadd +.\" All rights reserved. +.\" +.\" Redistribution and use in source and binary forms, with or without +.\" modification, are permitted provided that the following conditions +.\" are met: +.\" 1. Redistributions of source code must retain the above copyright +.\" notice, this list of conditions and the following disclaimer. +.\" 2. Redistributions in binary form must reproduce the above copyright +.\" notice, this list of conditions and the following disclaimer in the +.\" documentation and/or other materials provided with the distribution. +.\" +.\" THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND +.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE +.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +.\" SUCH DAMAGE. +.\" +.\" $FreeBSD$ +.\" +.Dd May 10, 2015 +.Dt NUMA 4 +.Os +.Sh NAME +.Nm NUMA +.Nd Non-Uniform Memory Access +.Sh SYNOPSIS +.Cd options SMP +.Cd options MAXMEMDOM=16 +.Pp +.In sys/numa.h +.In sys/cpuset.h +.In sys/bus.h +.Sh DESCRIPTION +Non-Uniform Memory Access is a computer architecture design which +involves unequal costs between processors, memory and IO devices +in a given system. +.Pp +In a +.Nm +architecture, the latency to access specific memory or IO devices +depends upon which processor the memory or device is attached to. +Accessing memory local to a processor is faster than accessing memory +that is connected to one of the other processors. +.Pp +.Nm +is enabled when the +.Cd MAXMEMDOM +option is used in a kernel configuration +file and is set to a value greater than 1. +.Pp +Thread and process +.Nm +policies are controlled with the +.Xr numa_setaffinity 2 +and +.Xr numa_getaffinity 2 +syscalls. +.Pp +The +.Xr numactl 1 +tool is available for starting processes with a non-default +policy, or to change the policy of an existing thread or process. +.Pp +Systems with non-uniform access to I/O devices may mark those devices +with the local VM domain identifier. +Drivers can find out their local domain information by calling +.Xr bus_get_domain 9 . +.Ss MIB Variables +The operation of +.Nm +is controlled and exposes information with these +.Xr sysctl 8 +MIB variables: +.Pp +.Bl -tag -width indent -compact +.It Va vm.ndomains +The number of VM domains which have been detected. +.Pp +.It Va vm.default_policy +The default VM domain allocation policy. +Defaults to "first-touch-rr". +The valid values are "first-touch", "first-touch-rr", +"rr", where "rr" is a short-hand for "round-robin." +See +.Xr numa_setaffinity 2 +for more information about the available policies. +.Pp +.It Va vm.phys_locality +A table indicating the relative cost of each VM domain to each other. +A value of 10 indicates equal cost. +A value of -1 means the locality map is not available or no +locality information is available. +.Pp +.It Va vm.phys_segs +The map of physical memory, grouped by VM domain. +.El +.Sh IMPLEMENTATION NOTES +The current +.Nm +implementation is VM-focused. +The hardware +.Nm +domains are mapped into a contiguous, non-sparse +VM domain space, starting from 0. +Thus, VM domain information (for example, the domain identifier) is not +necessarily the same as is found in the hardware specific information. +.Pp +The +.Nm +allocation policies are implemented as a policy and iterator in +.Pa sys/vm/vm_domain.c +and +.Pa sys/vm/vm_domain.h . +Policy information is available in both struct thread and struct proc. +Processes inherit +.Nm +policy from parent processes and threads inherit +.Nm +policy from parent threads. +Note that threads do not explicitly inherit their +.Nm +policy from processes. +Instead, if no thread policy is set, the system +will fall back to the process policy. +.Pp +For now, +.Nm +domain policies only influence physical page allocation in +.Pa sys/vm/vm_phys.c . +This is useful for userland memory allocation, but not for kernel +and driver memory allocation. +These features will be implemented in future work. +.Sh SEE ALSO +.Xr numactl 1 , +.Xr numa_getaffinity 2 , +.Xr numa_setaffinity 2 , +.Xr bus_get_domain 9 +.Sh HISTORY +.Nm +first appeared in +.Fx 9.0 +as a first-touch allocation policy with a fail-over to round-robin allocation +and was not configurable. +It was then modified in +.Fx 10.0 +to implement a round-robin allocation policy and was also not configurable. +.Pp +The +.Xr numa_getaffinity 2 +and +.Xr numa_setaffinity 2 +syscalls first appeared in +.Fx 11.0 . +.Pp +The +.Xr numactl 1 +tool first appeared in +.Fx 11.0 . +.Sh AUTHORS +This manual page written by +.An Adrian Chadd Aq Mt adrian@FreeBSD.org . +.Sh NOTES +No statistics are kept to indicate how often +.Nm +allocation policies succeed or fail. diff --git a/share/man/man4/proto.4 b/share/man/man4/proto.4 index 376060baa163..f541836ac62f 100644 --- a/share/man/man4/proto.4 +++ b/share/man/man4/proto.4 @@ -25,7 +25,7 @@ .\" .\" $FreeBSD$ .\" -.Dd July 3, 2015 +.Dd July 19, 2015 .Dt PROTO 4 .Os .\" @@ -47,6 +47,12 @@ module at boot time, place the following line in .Bd -literal -offset indent proto_load="YES" .Ed +.Pp +To have the driver attach to a device instead of its regular driver, +mention it in the list of devices assigned to the following loader variable: +.Bd -ragged -offset indent +hw.proto.attach="desc[,desc]" +.Ed .\" .Sh DESCRIPTION The diff --git a/share/man/man4/random.4 b/share/man/man4/random.4 index b93f6baefeb6..133fb3bb52a8 100644 --- a/share/man/man4/random.4 +++ b/share/man/man4/random.4 @@ -62,7 +62,7 @@ This sysctl will not return random bytes unless the .Xr random 4 -is seeded. +device is seeded. .Pp This initial seeding of random number generators diff --git a/share/man/man9/Makefile b/share/man/man9/Makefile index 21541908e218..695fa23cd2f3 100644 --- a/share/man/man9/Makefile +++ b/share/man/man9/Makefile @@ -1281,6 +1281,7 @@ MLINKS+=psignal.9 gsignal.9 \ MLINKS+=random.9 arc4rand.9 \ random.9 arc4random.9 \ random.9 read_random.9 \ + random.9 read_random_uio.9 \ random.9 srandom.9 MLINKS+=refcount.9 refcount_acquire.9 \ refcount.9 refcount_init.9 \ diff --git a/share/man/man9/crypto.9 b/share/man/man9/crypto.9 index 25326ff674ed..428c9b35b605 100644 --- a/share/man/man9/crypto.9 +++ b/share/man/man9/crypto.9 @@ -17,7 +17,7 @@ .\" .\" $FreeBSD$ .\" -.Dd July 8, 2015 +.Dd July 10, 2015 .Dt CRYPTO 9 .Os .Sh NAME @@ -40,6 +40,8 @@ .Ft void .Fn crypto_kdone "struct cryptkop *" .Ft int +.Fn crypto_find_driver "const char *" +.Ft int .Fn crypto_newsession "uint64_t *" "struct cryptoini *" int .Ft int .Fn crypto_freesession uint64_t @@ -157,15 +159,28 @@ was a fatal error in verifying the arguments). For session initialization and teardown there is no callback mechanism used. .Pp The +.Fn crypto_find_driver +function may be called to return the specific id of the provided name. +If the specified driver could not be found, the returned id is -1. +.Pp +The .Fn crypto_newsession routine is called by consumers of cryptographic services (such as the .Xr ipsec 4 stack) that wish to establish a new session with the framework. -On success, the first argument will contain the Session Identifier (SID). The second argument contains all the necessary information for the driver to establish the session. -The third argument indicates whether a -hardware driver (1) should be used or not (0). +The third argument is either a specific driver id, or one or both +of +.Dv CRYPTOCAP_F_HARDWARE , +to select hardware devices, +or +.Dv CRYPTOCAP_F_SOFTWARE , +to select software devices. +If both are specified, a hardware device will be returned +before a software device will be. +On success, the value pointed to by the first argument will be the +Session IDentifier (SID). The various fields in the .Vt cryptoini structure are: diff --git a/share/man/man9/nv.9 b/share/man/man9/nv.9 index 2184ae640566..8c4bb2095c17 100644 --- a/share/man/man9/nv.9 +++ b/share/man/man9/nv.9 @@ -66,7 +66,7 @@ .Ft int .Fn nvlist_error "const nvlist_t *nvl" .Ft void -.Fn nvlist_set_error "nvlist_t *nvl, int error" +.Fn nvlist_set_error "nvlist_t *nvl" "int error" .Ft bool .Fn nvlist_empty "const nvlist_t *nvl" .Ft int @@ -76,9 +76,9 @@ .Fn nvlist_clone "const nvlist_t *nvl" .\" .Ft void -.Fn nvlist_dump "const nvlist_t *nvl, int fd" +.Fn nvlist_dump "const nvlist_t *nvl" "int fd" .Ft void -.Fn nvlist_fdump "const nvlist_t *nvl, FILE *fp" +.Fn nvlist_fdump "const nvlist_t *nvl" "FILE *fp" .\" .Ft size_t .Fn nvlist_size "const nvlist_t *nvl" diff --git a/share/man/man9/random.9 b/share/man/man9/random.9 index 906b5e59679b..e2875e1798de 100644 --- a/share/man/man9/random.9 +++ b/share/man/man9/random.9 @@ -26,7 +26,7 @@ .\" .\" $FreeBSD$ .\" " -.Dd June 30, 2015 +.Dd July 16, 2015 .Dt RANDOM 9 .Os .Sh NAME @@ -34,6 +34,7 @@ .Nm arc4random , .Nm random , .Nm read_random , +.Nm read_random_uio , .Nm srandom .Nd supply pseudo-random numbers .Sh SYNOPSIS @@ -50,6 +51,8 @@ .In sys/random.h .Ft int .Fn read_random "void *buffer" "int count" +.Ft int +.Fn read_random_uio "struct uio *uio" "bool nonblock" .Sh DESCRIPTION The .Fn random @@ -117,11 +120,27 @@ necessary to know that no entropy has been returned. .Pp +The +.Fn read_random_uio +function behaves identically to +.Xr read 2 +on +.Pa /dev/random . +The +.Fa uio +argument points to a buffer where random data should be stored. +This function only returns data if the random device is seeded. +It blocks if unseeded, +except when the +.Fa nonblock +argument is true. +.Pp All the bits returned by .Fn random , -.Fn arc4rand +.Fn arc4rand , +.Fn read_random , and -.Fn read_random +.Fn read_random_uio are usable. For example, .Sq Li random()&01 @@ -168,6 +187,22 @@ The function returns the number of bytes placed in .Fa buffer . +.Pp +.Fn read_random_uio +returns zero when successful, +otherwise an error code is returned. +.Sh ERRORS +.Fn read_random_uio +may fail if: +.Bl -tag -width Er +.It Bq Er EFAULT +.Fa uio +points to an invalid memory region. +.It Bq Er EWOULDBLOCK +The random device is unseeded and +.Fa nonblock +is true. +.El .Sh AUTHORS .An Dan Moschuk wrote diff --git a/share/man/man9/random_harvest.9 b/share/man/man9/random_harvest.9 index cb89a05c3f5e..5c0693471c24 100644 --- a/share/man/man9/random_harvest.9 +++ b/share/man/man9/random_harvest.9 @@ -25,7 +25,7 @@ .\" .\" $FreeBSD$ .\" -.Dd June 30, 2015 +.Dd July 13, 2015 .Dt RANDOM_HARVEST 9 .Os .Sh NAME @@ -96,7 +96,7 @@ from harvesting, as they are high-rate sources. Some entropy is sacrificed, -but the hig rate of supply +but the high rate of supply will compensate for this. .Pp The @@ -121,7 +121,7 @@ and pass this in .Fa bits . .Pp Interrupt harvesting has been -in part simplified simplified +in part simplified for the kernel programmer. If a device driver registers an interrupt handler with diff --git a/sys/amd64/amd64/db_trace.c b/sys/amd64/amd64/db_trace.c index 39297d9b2ed0..381237b6b321 100644 --- a/sys/amd64/amd64/db_trace.c +++ b/sys/amd64/amd64/db_trace.c @@ -52,17 +52,8 @@ __FBSDID("$FreeBSD$"); #include #include -static db_varfcn_t db_dr0; -static db_varfcn_t db_dr1; -static db_varfcn_t db_dr2; -static db_varfcn_t db_dr3; -static db_varfcn_t db_dr4; -static db_varfcn_t db_dr5; -static db_varfcn_t db_dr6; -static db_varfcn_t db_dr7; static db_varfcn_t db_frame; -static db_varfcn_t db_rsp; -static db_varfcn_t db_ss; +static db_varfcn_t db_frame_seg; CTASSERT(sizeof(struct dbreg) == sizeof(((struct pcpu *)NULL)->pc_dbreg)); @@ -71,17 +62,17 @@ CTASSERT(sizeof(struct dbreg) == sizeof(((struct pcpu *)NULL)->pc_dbreg)); */ #define DB_OFFSET(x) (db_expr_t *)offsetof(struct trapframe, x) struct db_variable db_regs[] = { - { "cs", DB_OFFSET(tf_cs), db_frame }, - { "ds", DB_OFFSET(tf_ds), db_frame }, - { "es", DB_OFFSET(tf_es), db_frame }, - { "fs", DB_OFFSET(tf_fs), db_frame }, - { "gs", DB_OFFSET(tf_gs), db_frame }, - { "ss", NULL, db_ss }, + { "cs", DB_OFFSET(tf_cs), db_frame_seg }, + { "ds", DB_OFFSET(tf_ds), db_frame_seg }, + { "es", DB_OFFSET(tf_es), db_frame_seg }, + { "fs", DB_OFFSET(tf_fs), db_frame_seg }, + { "gs", DB_OFFSET(tf_gs), db_frame_seg }, + { "ss", DB_OFFSET(tf_ss), db_frame_seg }, { "rax", DB_OFFSET(tf_rax), db_frame }, { "rcx", DB_OFFSET(tf_rcx), db_frame }, { "rdx", DB_OFFSET(tf_rdx), db_frame }, { "rbx", DB_OFFSET(tf_rbx), db_frame }, - { "rsp", NULL, db_rsp }, + { "rsp", DB_OFFSET(tf_rsp), db_frame }, { "rbp", DB_OFFSET(tf_rbp), db_frame }, { "rsi", DB_OFFSET(tf_rsi), db_frame }, { "rdi", DB_OFFSET(tf_rdi), db_frame }, @@ -95,46 +86,23 @@ struct db_variable db_regs[] = { { "r15", DB_OFFSET(tf_r15), db_frame }, { "rip", DB_OFFSET(tf_rip), db_frame }, { "rflags", DB_OFFSET(tf_rflags), db_frame }, -#define DB_N_SHOW_REGS 24 /* Don't show registers after here. */ - { "dr0", NULL, db_dr0 }, - { "dr1", NULL, db_dr1 }, - { "dr2", NULL, db_dr2 }, - { "dr3", NULL, db_dr3 }, - { "dr4", NULL, db_dr4 }, - { "dr5", NULL, db_dr5 }, - { "dr6", NULL, db_dr6 }, - { "dr7", NULL, db_dr7 }, }; -struct db_variable *db_eregs = db_regs + DB_N_SHOW_REGS; +struct db_variable *db_eregs = db_regs + nitems(db_regs); -#define DB_DRX_FUNC(reg) \ -static int \ -db_ ## reg (vp, valuep, op) \ - struct db_variable *vp; \ - db_expr_t * valuep; \ - int op; \ -{ \ - if (op == DB_VAR_GET) \ - *valuep = r ## reg (); \ - else \ - load_ ## reg (*valuep); \ - return (1); \ -} - -DB_DRX_FUNC(dr0) -DB_DRX_FUNC(dr1) -DB_DRX_FUNC(dr2) -DB_DRX_FUNC(dr3) -DB_DRX_FUNC(dr4) -DB_DRX_FUNC(dr5) -DB_DRX_FUNC(dr6) -DB_DRX_FUNC(dr7) - -static __inline long -get_rsp(struct trapframe *tf) +static int +db_frame_seg(struct db_variable *vp, db_expr_t *valuep, int op) { - return ((ISPL(tf->tf_cs)) ? tf->tf_rsp : - (db_expr_t)tf + offsetof(struct trapframe, tf_rsp)); + uint16_t *reg; + + if (kdb_frame == NULL) + return (0); + + reg = (uint16_t *)((uintptr_t)kdb_frame + (db_expr_t)vp->valuep); + if (op == DB_VAR_GET) + *valuep = *reg; + else + *reg = *valuep; + return (1); } static int @@ -153,34 +121,6 @@ db_frame(struct db_variable *vp, db_expr_t *valuep, int op) return (1); } -static int -db_rsp(struct db_variable *vp, db_expr_t *valuep, int op) -{ - - if (kdb_frame == NULL) - return (0); - - if (op == DB_VAR_GET) - *valuep = get_rsp(kdb_frame); - else if (ISPL(kdb_frame->tf_cs)) - kdb_frame->tf_rsp = *valuep; - return (1); -} - -static int -db_ss(struct db_variable *vp, db_expr_t *valuep, int op) -{ - - if (kdb_frame == NULL) - return (0); - - if (op == DB_VAR_GET) - *valuep = (ISPL(kdb_frame->tf_cs)) ? kdb_frame->tf_ss : rss(); - else if (ISPL(kdb_frame->tf_cs)) - kdb_frame->tf_ss = *valuep; - return (1); -} - #define NORMAL 0 #define TRAP 1 #define INTERRUPT 2 @@ -188,9 +128,7 @@ db_ss(struct db_variable *vp, db_expr_t *valuep, int op) #define TRAP_INTERRUPT 5 static void db_nextframe(struct amd64_frame **, db_addr_t *, struct thread *); -static int db_numargs(struct amd64_frame *); -static void db_print_stack_entry(const char *, int, char **, long *, db_addr_t, - void *); +static void db_print_stack_entry(const char *, db_addr_t, void *); static void decode_syscall(int, struct thread *); static const char * watchtype_str(int type); @@ -198,62 +136,11 @@ int amd64_set_watch(int watchnum, unsigned long watchaddr, int size, int access, struct dbreg *d); int amd64_clr_watch(int watchnum, struct dbreg *d); -/* - * Figure out how many arguments were passed into the frame at "fp". - */ -static int -db_numargs(fp) - struct amd64_frame *fp; -{ -#if 1 - return (0); /* regparm, needs dwarf2 info */ -#else - long *argp; - int inst; - int args; - - argp = (long *)db_get_value((long)&fp->f_retaddr, 8, FALSE); - /* - * XXX etext is wrong for LKMs. We should attempt to interpret - * the instruction at the return address in all cases. This - * may require better fault handling. - */ - if (argp < (long *)btext || argp >= (long *)etext) { - args = 5; - } else { - inst = db_get_value((long)argp, 4, FALSE); - if ((inst & 0xff) == 0x59) /* popl %ecx */ - args = 1; - else if ((inst & 0xffff) == 0xc483) /* addl $Ibs, %esp */ - args = ((inst >> 16) & 0xff) / 4; - else - args = 5; - } - return (args); -#endif -} - static void -db_print_stack_entry(name, narg, argnp, argp, callpc, frame) - const char *name; - int narg; - char **argnp; - long *argp; - db_addr_t callpc; - void *frame; +db_print_stack_entry(const char *name, db_addr_t callpc, void *frame) { - db_printf("%s(", name); -#if 0 - while (narg) { - if (argnp) - db_printf("%s=", *argnp++); - db_printf("%lr", (long)db_get_value((long)argp, 8, FALSE)); - argp++; - if (--narg != 0) - db_printf(","); - } -#endif - db_printf(") at "); + + db_printf("%s() at ", name != NULL ? name : "??"); db_printsym(callpc, DB_STGY_PROC); if (frame != NULL) db_printf("/frame 0x%lx", (register_t)frame); @@ -348,7 +235,7 @@ db_nextframe(struct amd64_frame **fp, db_addr_t *ip, struct thread *td) return; } - db_print_stack_entry(name, 0, 0, 0, rip, &(*fp)->f_frame); + db_print_stack_entry(name, rip, &(*fp)->f_frame); /* * Point to base of trapframe which is just above the @@ -357,7 +244,7 @@ db_nextframe(struct amd64_frame **fp, db_addr_t *ip, struct thread *td) tf = (struct trapframe *)((long)*fp + 16); if (INKERNEL((long) tf)) { - rsp = get_rsp(tf); + rsp = tf->tf_rsp; rip = tf->tf_rip; rbp = tf->tf_rbp; switch (frame_type) { @@ -384,17 +271,13 @@ db_nextframe(struct amd64_frame **fp, db_addr_t *ip, struct thread *td) } static int -db_backtrace(struct thread *td, struct trapframe *tf, - struct amd64_frame *frame, db_addr_t pc, int count) +db_backtrace(struct thread *td, struct trapframe *tf, struct amd64_frame *frame, + db_addr_t pc, register_t sp, int count) { struct amd64_frame *actframe; -#define MAXNARG 16 - char *argnames[MAXNARG], **argnp = NULL; const char *name; - long *argp; db_expr_t offset; c_db_sym_t sym; - int narg; boolean_t first; if (count == -1) @@ -418,48 +301,51 @@ db_backtrace(struct thread *td, struct trapframe *tf, */ actframe = frame; if (first) { - if (tf != NULL) { + first = FALSE; + if (sym == C_DB_SYM_NULL && sp != 0) { + /* + * If a symbol couldn't be found, we've probably + * jumped to a bogus location, so try and use + * the return address to find our caller. + */ + db_print_stack_entry(name, pc, NULL); + pc = db_get_value(sp, 8, FALSE); + if (db_search_symbol(pc, DB_STGY_PROC, + &offset) == C_DB_SYM_NULL) + break; + continue; + } else if (tf != NULL) { int instr; instr = db_get_value(pc, 4, FALSE); if ((instr & 0xffffffff) == 0xe5894855) { /* pushq %rbp; movq %rsp, %rbp */ - actframe = (void *)(get_rsp(tf) - 8); + actframe = (void *)(tf->tf_rsp - 8); } else if ((instr & 0xffffff) == 0xe58948) { /* movq %rsp, %rbp */ - actframe = (void *)get_rsp(tf); + actframe = (void *)tf->tf_rsp; if (tf->tf_rbp == 0) { /* Fake frame better. */ frame = actframe; } } else if ((instr & 0xff) == 0xc3) { /* ret */ - actframe = (void *)(get_rsp(tf) - 8); + actframe = (void *)(tf->tf_rsp - 8); } else if (offset == 0) { /* Probably an assembler symbol. */ - actframe = (void *)(get_rsp(tf) - 8); + actframe = (void *)(tf->tf_rsp - 8); } } else if (strcmp(name, "fork_trampoline") == 0) { /* * Don't try to walk back on a stack for a * process that hasn't actually been run yet. */ - db_print_stack_entry(name, 0, 0, 0, pc, - actframe); + db_print_stack_entry(name, pc, actframe); break; } - first = FALSE; } - argp = &actframe->f_arg0; - narg = MAXNARG; - if (sym != NULL && db_sym_numargs(sym, &narg, argnames)) { - argnp = argnames; - } else { - narg = db_numargs(frame); - } - - db_print_stack_entry(name, narg, argnp, argp, pc, actframe); + db_print_stack_entry(name, pc, actframe); if (actframe != frame) { /* `frame' belongs to caller. */ @@ -473,7 +359,7 @@ db_backtrace(struct thread *td, struct trapframe *tf, if (INKERNEL((long)pc) && !INKERNEL((long)frame)) { sym = db_search_symbol(pc, DB_STGY_ANY, &offset); db_symbol_values(sym, &name, NULL); - db_print_stack_entry(name, 0, 0, 0, pc, frame); + db_print_stack_entry(name, pc, frame); break; } if (!INKERNEL((long) frame)) { @@ -495,17 +381,19 @@ db_trace_self(void) frame = (struct amd64_frame *)rbp; callpc = (db_addr_t)db_get_value((long)&frame->f_retaddr, 8, FALSE); frame = frame->f_frame; - db_backtrace(curthread, NULL, frame, callpc, -1); + db_backtrace(curthread, NULL, frame, callpc, 0, -1); } int db_trace_thread(struct thread *thr, int count) { struct pcb *ctx; + struct trapframe *tf; ctx = kdb_thr_ctx(thr); - return (db_backtrace(thr, NULL, (struct amd64_frame *)ctx->pcb_rbp, - ctx->pcb_rip, count)); + tf = thr == kdb_thread ? kdb_frame : NULL; + return (db_backtrace(thr, tf, (struct amd64_frame *)ctx->pcb_rbp, + ctx->pcb_rip, ctx->pcb_rsp, count)); } int diff --git a/sys/amd64/amd64/machdep.c b/sys/amd64/amd64/machdep.c index 58cb9786578f..a571390689a3 100644 --- a/sys/amd64/amd64/machdep.c +++ b/sys/amd64/amd64/machdep.c @@ -878,11 +878,26 @@ DB_SHOW_COMMAND(sysregs, db_show_sysregs) db_printf("cr2\t0x%016lx\n", rcr2()); db_printf("cr3\t0x%016lx\n", rcr3()); db_printf("cr4\t0x%016lx\n", rcr4()); - db_printf("EFER\t%016lx\n", rdmsr(MSR_EFER)); - db_printf("FEATURES_CTL\t%016lx\n", rdmsr(MSR_IA32_FEATURE_CONTROL)); - db_printf("DEBUG_CTL\t%016lx\n", rdmsr(MSR_DEBUGCTLMSR)); - db_printf("PAT\t%016lx\n", rdmsr(MSR_PAT)); - db_printf("GSBASE\t%016lx\n", rdmsr(MSR_GSBASE)); + if (rcr4() & CR4_XSAVE) + db_printf("xcr0\t0x%016lx\n", rxcr(0)); + db_printf("EFER\t0x%016lx\n", rdmsr(MSR_EFER)); + if (cpu_feature2 & (CPUID2_VMX | CPUID2_SMX)) + db_printf("FEATURES_CTL\t%016lx\n", + rdmsr(MSR_IA32_FEATURE_CONTROL)); + db_printf("DEBUG_CTL\t0x%016lx\n", rdmsr(MSR_DEBUGCTLMSR)); + db_printf("PAT\t0x%016lx\n", rdmsr(MSR_PAT)); + db_printf("GSBASE\t0x%016lx\n", rdmsr(MSR_GSBASE)); +} + +DB_SHOW_COMMAND(dbregs, db_show_dbregs) +{ + + db_printf("dr0\t0x%016lx\n", rdr0()); + db_printf("dr1\t0x%016lx\n", rdr1()); + db_printf("dr2\t0x%016lx\n", rdr2()); + db_printf("dr3\t0x%016lx\n", rdr3()); + db_printf("dr6\t0x%016lx\n", rdr6()); + db_printf("dr7\t0x%016lx\n", rdr7()); } #endif diff --git a/sys/amd64/amd64/stack_machdep.c b/sys/amd64/amd64/stack_machdep.c index 57908e202a0f..2412c93e069e 100644 --- a/sys/amd64/amd64/stack_machdep.c +++ b/sys/amd64/amd64/stack_machdep.c @@ -40,7 +40,7 @@ __FBSDID("$FreeBSD$"); #include static void -stack_capture(struct stack *st, register_t rbp) +stack_capture(struct thread *td, struct stack *st, register_t rbp) { struct amd64_frame *frame; vm_offset_t callpc; @@ -56,8 +56,8 @@ stack_capture(struct stack *st, register_t rbp) if (stack_put(st, callpc) == -1) break; if (frame->f_frame <= frame || - (vm_offset_t)frame->f_frame >= - (vm_offset_t)rbp + KSTACK_PAGES * PAGE_SIZE) + (vm_offset_t)frame->f_frame >= td->td_kstack + + td->td_kstack_pages * PAGE_SIZE) break; frame = frame->f_frame; } @@ -74,7 +74,7 @@ stack_save_td(struct stack *st, struct thread *td) panic("stack_save_td: running"); rbp = td->td_pcb->pcb_rbp; - stack_capture(st, rbp); + stack_capture(td, st, rbp); } void @@ -83,5 +83,5 @@ stack_save(struct stack *st) register_t rbp; __asm __volatile("movq %%rbp,%0" : "=r" (rbp)); - stack_capture(st, rbp); + stack_capture(curthread, st, rbp); } diff --git a/sys/amd64/cloudabi64/cloudabi64_sysvec.c b/sys/amd64/cloudabi64/cloudabi64_sysvec.c new file mode 100644 index 000000000000..428d9f7602da --- /dev/null +++ b/sys/amd64/cloudabi64/cloudabi64_sysvec.c @@ -0,0 +1,264 @@ +/*- + * Copyright (c) 2015 Nuxi, https://nuxi.nl/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + +extern const char *cloudabi64_syscallnames[]; +extern struct sysent cloudabi64_sysent[]; + +static register_t * +cloudabi64_copyout_strings(struct image_params *imgp) +{ + uintptr_t begin; + size_t len; + + /* Copy out program arguments. */ + len = imgp->args->begin_envv - imgp->args->begin_argv; + begin = rounddown2(USRSTACK - len, sizeof(register_t)); + copyout(imgp->args->begin_argv, (void *)begin, len); + return ((register_t *)begin); +} + +static int +cloudabi64_fixup(register_t **stack_base, struct image_params *imgp) +{ + char canarybuf[64]; + Elf64_Auxargs *args; + void *argdata, *canary; + size_t argdatalen; + int error; + + /* Store canary for stack smashing protection. */ + argdata = *stack_base; + arc4rand(canarybuf, sizeof(canarybuf), 0); + *stack_base -= howmany(sizeof(canarybuf), sizeof(register_t)); + canary = *stack_base; + error = copyout(canarybuf, canary, sizeof(canarybuf)); + if (error != 0) + return (error); + + /* + * Compute length of program arguments. As the argument data is + * binary safe, we had to add a trailing null byte in + * exec_copyin_data_fds(). Undo this by reducing the length. + */ + args = (Elf64_Auxargs *)imgp->auxargs; + argdatalen = imgp->args->begin_envv - imgp->args->begin_argv; + if (argdatalen > 0) + --argdatalen; + + /* Write out an auxiliary vector. */ + cloudabi64_auxv_t auxv[] = { +#define VAL(type, val) { .a_type = (type), .a_val = (val) } +#define PTR(type, ptr) { .a_type = (type), .a_ptr = (uintptr_t)(ptr) } + PTR(CLOUDABI_AT_ARGDATA, argdata), + VAL(CLOUDABI_AT_ARGDATALEN, argdatalen), + PTR(CLOUDABI_AT_CANARY, canary), + VAL(CLOUDABI_AT_CANARYLEN, sizeof(canarybuf)), + VAL(CLOUDABI_AT_NCPUS, mp_ncpus), + VAL(CLOUDABI_AT_PAGESZ, args->pagesz), + PTR(CLOUDABI_AT_PHDR, args->phdr), + VAL(CLOUDABI_AT_PHNUM, args->phnum), + VAL(CLOUDABI_AT_TID, curthread->td_tid), +#undef VAL +#undef PTR + { .a_type = CLOUDABI_AT_NULL }, + }; + *stack_base -= howmany(sizeof(auxv), sizeof(register_t)); + return (copyout(auxv, *stack_base, sizeof(auxv))); +} + +static int +cloudabi64_fetch_syscall_args(struct thread *td, struct syscall_args *sa) +{ + struct trapframe *frame = td->td_frame; + + /* Obtain system call number. */ + sa->code = frame->tf_rax; + if (sa->code >= CLOUDABI64_SYS_MAXSYSCALL) + return (ENOSYS); + sa->callp = &cloudabi64_sysent[sa->code]; + + /* Fetch system call arguments. */ + sa->args[0] = frame->tf_rdi; + sa->args[1] = frame->tf_rsi; + sa->args[2] = frame->tf_rdx; + sa->args[3] = frame->tf_rcx; /* Actually %r10. */ + sa->args[4] = frame->tf_r8; + sa->args[5] = frame->tf_r9; + + /* Default system call return values. */ + td->td_retval[0] = 0; + td->td_retval[1] = frame->tf_rdx; + return (0); +} + +static void +cloudabi64_set_syscall_retval(struct thread *td, int error) +{ + struct trapframe *frame = td->td_frame; + + switch (error) { + case 0: + /* System call succeeded. */ + frame->tf_rax = td->td_retval[0]; + frame->tf_rdx = td->td_retval[1]; + frame->tf_rflags &= ~PSL_C; + break; + case ERESTART: + /* Restart system call. */ + frame->tf_rip -= frame->tf_err; + frame->tf_r10 = frame->tf_rcx; + set_pcb_flags(td->td_pcb, PCB_FULL_IRET); + break; + case EJUSTRETURN: + break; + default: + /* System call returned an error. */ + frame->tf_rax = cloudabi_convert_errno(error); + frame->tf_rflags |= PSL_C; + break; + } +} + +static void +cloudabi64_schedtail(struct thread *td) +{ + struct trapframe *frame = td->td_frame; + + /* Initial register values for processes returning from fork. */ + frame->tf_rax = CLOUDABI_PROCESS_CHILD; + frame->tf_rdx = td->td_tid; +} + +void +cloudabi64_thread_setregs(struct thread *td, + const cloudabi64_threadattr_t *attr) +{ + struct trapframe *frame; + stack_t stack; + + /* Perform standard register initialization. */ + stack.ss_sp = (void *)attr->stack; + stack.ss_size = attr->stack_size; + cpu_set_upcall_kse(td, (void *)attr->entry_point, NULL, &stack); + + /* + * Pass in the thread ID of the new thread and the argument + * pointer provided by the parent thread in as arguments to the + * entry point. + */ + frame = td->td_frame; + frame->tf_rdi = td->td_tid; + frame->tf_rsi = attr->argument; +} + +static struct sysentvec cloudabi64_elf_sysvec = { + .sv_size = CLOUDABI64_SYS_MAXSYSCALL, + .sv_table = cloudabi64_sysent, + .sv_fixup = cloudabi64_fixup, + .sv_name = "CloudABI ELF64", + .sv_coredump = elf64_coredump, + .sv_pagesize = PAGE_SIZE, + .sv_minuser = VM_MIN_ADDRESS, + .sv_maxuser = VM_MAXUSER_ADDRESS, + .sv_usrstack = USRSTACK, + .sv_stackprot = VM_PROT_READ | VM_PROT_WRITE, + .sv_copyout_strings = cloudabi64_copyout_strings, + .sv_flags = SV_ABI_CLOUDABI, + .sv_set_syscall_retval = cloudabi64_set_syscall_retval, + .sv_fetch_syscall_args = cloudabi64_fetch_syscall_args, + .sv_syscallnames = cloudabi64_syscallnames, + .sv_schedtail = cloudabi64_schedtail, +}; + +INIT_SYSENTVEC(elf_sysvec, &cloudabi64_elf_sysvec); + +static Elf64_Brandinfo cloudabi64_brand = { + .brand = ELFOSABI_CLOUDABI, + .machine = EM_X86_64, + .sysvec = &cloudabi64_elf_sysvec, + .compat_3_brand = "CloudABI", +}; + +static int +cloudabi64_modevent(module_t mod, int type, void *data) +{ + + switch (type) { + case MOD_LOAD: + if (elf64_insert_brand_entry(&cloudabi64_brand) < 0) { + printf("Failed to add CloudABI ELF brand handler\n"); + return (EINVAL); + } + return (0); + case MOD_UNLOAD: + if (elf64_brand_inuse(&cloudabi64_brand)) + return (EBUSY); + if (elf64_remove_brand_entry(&cloudabi64_brand) < 0) { + printf("Failed to remove CloudABI ELF brand handler\n"); + return (EINVAL); + } + return (0); + default: + return (EOPNOTSUPP); + } +} + +static moduledata_t cloudabi64_module = { + "cloudabi64", + cloudabi64_modevent, + NULL +}; + +DECLARE_MODULE_TIED(cloudabi64, cloudabi64_module, SI_SUB_EXEC, SI_ORDER_ANY); +MODULE_DEPEND(cloudabi64, cloudabi, 1, 1, 1); diff --git a/sys/amd64/conf/GENERIC b/sys/amd64/conf/GENERIC index dd1aa8bed3e0..5c7f7c035f43 100644 --- a/sys/amd64/conf/GENERIC +++ b/sys/amd64/conf/GENERIC @@ -170,6 +170,7 @@ device ida # Compaq Smart RAID device mfi # LSI MegaRAID SAS device mlx # Mylex DAC960 family device mrsas # LSI/Avago MegaRAID SAS/SATA, 6Gb/s and 12Gb/s +device pmspcv # PMC-Sierra SAS/SATA Controller driver #XXX pointer/int warnings #device pst # Promise Supertrak SX6000 device twe # 3ware ATA RAID @@ -364,5 +365,5 @@ device vmx # VMware VMXNET3 Ethernet # Netmap provides direct access to TX/RX rings on supported NICs device netmap # netmap(4) support -# The cypto framework is required by IPSEC +# The crypto framework is required by IPSEC device crypto # Required by IPSEC diff --git a/sys/amd64/conf/NOTES b/sys/amd64/conf/NOTES index 97eefbfd7c13..bfcf9635f98a 100644 --- a/sys/amd64/conf/NOTES +++ b/sys/amd64/conf/NOTES @@ -22,7 +22,6 @@ options KDTRACE_HOOKS #device dtrace # DTrace modules -#device dtrace_lockstat #device dtrace_profile #device dtrace_sdt #device dtrace_fbt @@ -485,6 +484,10 @@ options ISCI_LOGGING # enable debugging in isci HAL device nvme # base NVMe driver device nvd # expose NVMe namespaces as disks, depends on nvme +# +# PMC-Sierra SAS/SATA controller +device pmspcv + # # SafeNet crypto driver: can be moved to the MI NOTES as soon as # it's tested on a big-endian machine @@ -617,6 +620,9 @@ options COMPAT_FREEBSD32 # Emulate spx device for client side of SVR3 local X interface #XXX#options SPX_HACK +# Enable 64-bit runtime support for CloudABI binaries. +options COMPAT_CLOUDABI64 + # Enable Linux ABI emulation #XXX#options COMPAT_LINUX diff --git a/sys/arm/allwinner/a10_gpio.c b/sys/arm/allwinner/a10_gpio.c index c461013431ab..dbff87d4f465 100644 --- a/sys/arm/allwinner/a10_gpio.c +++ b/sys/arm/allwinner/a10_gpio.c @@ -82,18 +82,16 @@ struct a10_gpio_softc { bus_space_tag_t sc_bst; bus_space_handle_t sc_bsh; void * sc_intrhand; - int sc_gpio_npins; - struct gpio_pin sc_gpio_pins[A10_GPIO_PINS]; }; -#define A10_GPIO_LOCK(_sc) mtx_lock(&_sc->sc_mtx) -#define A10_GPIO_UNLOCK(_sc) mtx_unlock(&_sc->sc_mtx) -#define A10_GPIO_LOCK_ASSERT(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED) +#define A10_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) +#define A10_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) +#define A10_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) -#define A10_GPIO_GP_CFG(_bank, _pin) 0x00 + ((_bank) * 0x24) + ((_pin)<<2) +#define A10_GPIO_GP_CFG(_bank, _idx) 0x00 + ((_bank) * 0x24) + ((_idx) << 2) #define A10_GPIO_GP_DAT(_bank) 0x10 + ((_bank) * 0x24) -#define A10_GPIO_GP_DRV(_bank, _pin) 0x14 + ((_bank) * 0x24) + ((_pin)<<2) -#define A10_GPIO_GP_PUL(_bank, _pin) 0x1c + ((_bank) * 0x24) + ((_pin)<<2) +#define A10_GPIO_GP_DRV(_bank, _idx) 0x14 + ((_bank) * 0x24) + ((_idx) << 2) +#define A10_GPIO_GP_PUL(_bank, _idx) 0x1c + ((_bank) * 0x24) + ((_idx) << 2) #define A10_GPIO_GP_INT_CFG0 0x200 #define A10_GPIO_GP_INT_CFG1 0x204 @@ -116,106 +114,106 @@ a10_gpio_get_function(struct a10_gpio_softc *sc, uint32_t pin) { uint32_t bank, func, offset; + /* Must be called with lock held. */ + A10_GPIO_LOCK_ASSERT(sc); + bank = pin / 32; - pin = pin - 32 * bank; - func = pin >> 3; + pin = pin % 32; offset = ((pin & 0x07) << 2); - A10_GPIO_LOCK(sc); - func = (A10_GPIO_READ(sc, A10_GPIO_GP_CFG(bank, func)) >> offset) & 7; - A10_GPIO_UNLOCK(sc); - - return (func); -} - -static uint32_t -a10_gpio_func_flag(uint32_t nfunc) -{ - - switch (nfunc) { + func = A10_GPIO_READ(sc, A10_GPIO_GP_CFG(bank, pin >> 3)); + switch ((func >> offset) & 0x7) { case A10_GPIO_INPUT: return (GPIO_PIN_INPUT); case A10_GPIO_OUTPUT: return (GPIO_PIN_OUTPUT); } + return (0); } static void a10_gpio_set_function(struct a10_gpio_softc *sc, uint32_t pin, uint32_t f) { - uint32_t bank, func, data, offset; + uint32_t bank, data, offset; /* Must be called with lock held. */ A10_GPIO_LOCK_ASSERT(sc); bank = pin / 32; - pin = pin - 32 * bank; - func = pin >> 3; + pin = pin % 32; offset = ((pin & 0x07) << 2); - data = A10_GPIO_READ(sc, A10_GPIO_GP_CFG(bank, func)); + data = A10_GPIO_READ(sc, A10_GPIO_GP_CFG(bank, pin >> 3)); data &= ~(7 << offset); data |= (f << offset); - A10_GPIO_WRITE(sc, A10_GPIO_GP_CFG(bank, func), data); + A10_GPIO_WRITE(sc, A10_GPIO_GP_CFG(bank, pin >> 3), data); +} + +static uint32_t +a10_gpio_get_pud(struct a10_gpio_softc *sc, uint32_t pin) +{ + uint32_t bank, offset, val; + + /* Must be called with lock held. */ + A10_GPIO_LOCK_ASSERT(sc); + + bank = pin / 32; + pin = pin % 32; + offset = ((pin & 0x0f) << 1); + + val = A10_GPIO_READ(sc, A10_GPIO_GP_PUL(bank, pin >> 4)); + switch ((val >> offset) & 0x3) { + case A10_GPIO_PULLDOWN: + return (GPIO_PIN_PULLDOWN); + case A10_GPIO_PULLUP: + return (GPIO_PIN_PULLUP); + } + + return (0); } static void a10_gpio_set_pud(struct a10_gpio_softc *sc, uint32_t pin, uint32_t state) { - uint32_t bank, offset, pull, val; + uint32_t bank, offset, val; /* Must be called with lock held. */ A10_GPIO_LOCK_ASSERT(sc); bank = pin / 32; - pin = pin - 32 * bank; - pull = pin >> 4; + pin = pin % 32; offset = ((pin & 0x0f) << 1); - val = A10_GPIO_READ(sc, A10_GPIO_GP_PUL(bank, pull)); + val = A10_GPIO_READ(sc, A10_GPIO_GP_PUL(bank, pin >> 4)); val &= ~(0x03 << offset); val |= (state << offset); - A10_GPIO_WRITE(sc, A10_GPIO_GP_PUL(bank, pull), val); + A10_GPIO_WRITE(sc, A10_GPIO_GP_PUL(bank, pin >> 4), val); } static void -a10_gpio_pin_configure(struct a10_gpio_softc *sc, struct gpio_pin *pin, - unsigned int flags) +a10_gpio_pin_configure(struct a10_gpio_softc *sc, uint32_t pin, uint32_t flags) { - A10_GPIO_LOCK(sc); + /* Must be called with lock held. */ + A10_GPIO_LOCK_ASSERT(sc); - /* - * Manage input/output. - */ - if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) { - pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT); - if (flags & GPIO_PIN_OUTPUT) { - pin->gp_flags |= GPIO_PIN_OUTPUT; - a10_gpio_set_function(sc, pin->gp_pin, - A10_GPIO_OUTPUT); - } else { - pin->gp_flags |= GPIO_PIN_INPUT; - a10_gpio_set_function(sc, pin->gp_pin, - A10_GPIO_INPUT); - } + /* Manage input/output. */ + if (flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) { + if (flags & GPIO_PIN_OUTPUT) + a10_gpio_set_function(sc, pin, A10_GPIO_OUTPUT); + else + a10_gpio_set_function(sc, pin, A10_GPIO_INPUT); } /* Manage Pull-up/pull-down. */ - pin->gp_flags &= ~(GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN); - if (flags & (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) { - if (flags & GPIO_PIN_PULLUP) { - pin->gp_flags |= GPIO_PIN_PULLUP; - a10_gpio_set_pud(sc, pin->gp_pin, A10_GPIO_PULLUP); - } else { - pin->gp_flags |= GPIO_PIN_PULLDOWN; - a10_gpio_set_pud(sc, pin->gp_pin, A10_GPIO_PULLDOWN); - } + if (flags & (GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN)) { + if (flags & GPIO_PIN_PULLUP) + a10_gpio_set_pud(sc, pin, A10_GPIO_PULLUP); + else + a10_gpio_set_pud(sc, pin, A10_GPIO_PULLDOWN); } else - a10_gpio_set_pud(sc, pin->gp_pin, A10_GPIO_NONE); - - A10_GPIO_UNLOCK(sc); + a10_gpio_set_pud(sc, pin, A10_GPIO_NONE); } static device_t @@ -239,20 +237,11 @@ a10_gpio_pin_max(device_t dev, int *maxpin) static int a10_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) { - struct a10_gpio_softc *sc = device_get_softc(dev); - int i; - for (i = 0; i < sc->sc_gpio_npins; i++) { - if (sc->sc_gpio_pins[i].gp_pin == pin) - break; - } - - if (i >= sc->sc_gpio_npins) + if (pin >= A10_GPIO_PINS) return (EINVAL); - A10_GPIO_LOCK(sc); - *caps = sc->sc_gpio_pins[i].gp_caps; - A10_GPIO_UNLOCK(sc); + *caps = A10_GPIO_DEFAULT_CAPS; return (0); } @@ -260,19 +249,15 @@ a10_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) static int a10_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) { - struct a10_gpio_softc *sc = device_get_softc(dev); - int i; + struct a10_gpio_softc *sc; - for (i = 0; i < sc->sc_gpio_npins; i++) { - if (sc->sc_gpio_pins[i].gp_pin == pin) - break; - } - - if (i >= sc->sc_gpio_npins) + if (pin >= A10_GPIO_PINS) return (EINVAL); + sc = device_get_softc(dev); A10_GPIO_LOCK(sc); - *flags = sc->sc_gpio_pins[i].gp_flags; + *flags = a10_gpio_get_function(sc, pin); + *flags |= a10_gpio_get_pud(sc, pin); A10_GPIO_UNLOCK(sc); return (0); @@ -281,20 +266,15 @@ a10_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) static int a10_gpio_pin_getname(device_t dev, uint32_t pin, char *name) { - struct a10_gpio_softc *sc = device_get_softc(dev); - int i; + uint32_t bank; - for (i = 0; i < sc->sc_gpio_npins; i++) { - if (sc->sc_gpio_pins[i].gp_pin == pin) - break; - } - - if (i >= sc->sc_gpio_npins) + if (pin >= A10_GPIO_PINS) return (EINVAL); - A10_GPIO_LOCK(sc); - memcpy(name, sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME); - A10_GPIO_UNLOCK(sc); + bank = pin / 32; + snprintf(name, GPIOMAXNAME - 1, "pin %d (P%c%d)", + pin, bank + 'A', pin % 32); + name[GPIOMAXNAME - 1] = '\0'; return (0); } @@ -302,18 +282,15 @@ a10_gpio_pin_getname(device_t dev, uint32_t pin, char *name) static int a10_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) { - struct a10_gpio_softc *sc = device_get_softc(dev); - int i; + struct a10_gpio_softc *sc; - for (i = 0; i < sc->sc_gpio_npins; i++) { - if (sc->sc_gpio_pins[i].gp_pin == pin) - break; - } - - if (i >= sc->sc_gpio_npins) + if (pin >= A10_GPIO_PINS) return (EINVAL); - a10_gpio_pin_configure(sc, &sc->sc_gpio_pins[i], flags); + sc = device_get_softc(dev); + A10_GPIO_LOCK(sc); + a10_gpio_pin_configure(sc, pin, flags); + A10_GPIO_UNLOCK(sc); return (0); } @@ -321,28 +298,22 @@ a10_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) static int a10_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) { - struct a10_gpio_softc *sc = device_get_softc(dev); - uint32_t bank, offset, data; - int i; + struct a10_gpio_softc *sc; + uint32_t bank, data; - for (i = 0; i < sc->sc_gpio_npins; i++) { - if (sc->sc_gpio_pins[i].gp_pin == pin) - break; - } - - if (i >= sc->sc_gpio_npins) + if (pin >= A10_GPIO_PINS) return (EINVAL); bank = pin / 32; - pin = pin - 32 * bank; - offset = pin & 0x1f; + pin = pin % 32; + sc = device_get_softc(dev); A10_GPIO_LOCK(sc); data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank)); if (value) - data |= (1 << offset); + data |= (1 << pin); else - data &= ~(1 << offset); + data &= ~(1 << pin); A10_GPIO_WRITE(sc, A10_GPIO_GP_DAT(bank), data); A10_GPIO_UNLOCK(sc); @@ -352,26 +323,20 @@ a10_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) static int a10_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) { - struct a10_gpio_softc *sc = device_get_softc(dev); - uint32_t bank, offset, reg_data; - int i; + struct a10_gpio_softc *sc; + uint32_t bank, reg_data; - for (i = 0; i < sc->sc_gpio_npins; i++) { - if (sc->sc_gpio_pins[i].gp_pin == pin) - break; - } - - if (i >= sc->sc_gpio_npins) + if (pin >= A10_GPIO_PINS) return (EINVAL); bank = pin / 32; - pin = pin - 32 * bank; - offset = pin & 0x1f; + pin = pin % 32; + sc = device_get_softc(dev); A10_GPIO_LOCK(sc); reg_data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank)); A10_GPIO_UNLOCK(sc); - *val = (reg_data & (1 << offset)) ? 1 : 0; + *val = (reg_data & (1 << pin)) ? 1 : 0; return (0); } @@ -379,28 +344,22 @@ a10_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) static int a10_gpio_pin_toggle(device_t dev, uint32_t pin) { - struct a10_gpio_softc *sc = device_get_softc(dev); - uint32_t bank, data, offset; - int i; + struct a10_gpio_softc *sc; + uint32_t bank, data; - for (i = 0; i < sc->sc_gpio_npins; i++) { - if (sc->sc_gpio_pins[i].gp_pin == pin) - break; - } - - if (i >= sc->sc_gpio_npins) + if (pin >= A10_GPIO_PINS) return (EINVAL); bank = pin / 32; - pin = pin - 32 * bank; - offset = pin & 0x1f; + pin = pin % 32; + sc = device_get_softc(dev); A10_GPIO_LOCK(sc); data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank)); - if (data & (1 << offset)) - data &= ~(1 << offset); + if (data & (1 << pin)) + data &= ~(1 << pin); else - data |= (1 << offset); + data |= (1 << pin); A10_GPIO_WRITE(sc, A10_GPIO_GP_DAT(bank), data); A10_GPIO_UNLOCK(sc); @@ -424,14 +383,14 @@ a10_gpio_probe(device_t dev) static int a10_gpio_attach(device_t dev) { - struct a10_gpio_softc *sc = device_get_softc(dev); - uint32_t func; - int i, rid; + int rid; phandle_t gpio; + struct a10_gpio_softc *sc; + sc = device_get_softc(dev); sc->sc_dev = dev; - mtx_init(&sc->sc_mtx, "a10 gpio", "gpio", MTX_DEF); + mtx_init(&sc->sc_mtx, "a10 gpio", "gpio", MTX_SPIN); rid = 0; sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, @@ -454,21 +413,10 @@ a10_gpio_attach(device_t dev) /* Find our node. */ gpio = ofw_bus_get_node(sc->sc_dev); - if (!OF_hasprop(gpio, "gpio-controller")) /* Node is not a GPIO controller. */ goto fail; - /* Initialize the software controlled pins. */ - for (i = 0; i < A10_GPIO_PINS; i++) { - snprintf(sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME, - "pin %d", i); - func = a10_gpio_get_function(sc, i); - sc->sc_gpio_pins[i].gp_pin = i; - sc->sc_gpio_pins[i].gp_caps = A10_GPIO_DEFAULT_CAPS; - sc->sc_gpio_pins[i].gp_flags = a10_gpio_func_flag(func); - } - sc->sc_gpio_npins = i; a10_gpio_sc = sc; sc->sc_busdev = gpiobus_attach_bus(dev); if (sc->sc_busdev == NULL) @@ -493,6 +441,14 @@ a10_gpio_detach(device_t dev) return (EBUSY); } +static phandle_t +a10_gpio_get_node(device_t dev, device_t bus) +{ + + /* We only have one child, the GPIO bus, which needs our own node. */ + return (ofw_bus_get_node(dev)); +} + static device_method_t a10_gpio_methods[] = { /* Device interface */ DEVMETHOD(device_probe, a10_gpio_probe), @@ -510,6 +466,9 @@ static device_method_t a10_gpio_methods[] = { DEVMETHOD(gpio_pin_set, a10_gpio_pin_set), DEVMETHOD(gpio_pin_toggle, a10_gpio_pin_toggle), + /* ofw_bus interface */ + DEVMETHOD(ofw_bus_get_node, a10_gpio_get_node), + DEVMETHOD_END }; diff --git a/sys/arm/arm/machdep.c b/sys/arm/arm/machdep.c index 99d45722c17f..67e081d2dbab 100644 --- a/sys/arm/arm/machdep.c +++ b/sys/arm/arm/machdep.c @@ -44,6 +44,7 @@ #include "opt_compat.h" #include "opt_ddb.h" +#include "opt_kstack_pages.h" #include "opt_platform.h" #include "opt_sched.h" #include "opt_timer.h" diff --git a/sys/arm/arm/trap-v6.c b/sys/arm/arm/trap-v6.c index b15062c05534..09fc0fc9376d 100644 --- a/sys/arm/arm/trap-v6.c +++ b/sys/arm/arm/trap-v6.c @@ -542,8 +542,8 @@ nogo: return; } - ksig.sig = (rv == KERN_PROTECTION_FAILURE) ? SIGBUS : SIGSEGV; - ksig.code = 0; + ksig.sig = SIGSEGV; + ksig.code = (rv == KERN_PROTECTION_FAILURE) ? SEGV_ACCERR : SEGV_MAPERR; ksig.addr = far; do_trapsignal: diff --git a/sys/arm/at91/at91_machdep.c b/sys/arm/at91/at91_machdep.c index 170d0296a077..62edfa674ab8 100644 --- a/sys/arm/at91/at91_machdep.c +++ b/sys/arm/at91/at91_machdep.c @@ -43,6 +43,7 @@ * Created : 17/09/94 */ +#include "opt_kstack_pages.h" #include "opt_platform.h" #include diff --git a/sys/arm/cavium/cns11xx/econa_machdep.c b/sys/arm/cavium/cns11xx/econa_machdep.c index b49053598718..1532cec8a798 100644 --- a/sys/arm/cavium/cns11xx/econa_machdep.c +++ b/sys/arm/cavium/cns11xx/econa_machdep.c @@ -38,6 +38,8 @@ #include __FBSDID("$FreeBSD$"); +#include "opt_kstack_pages.h" + #define _ARM32_BUS_DMA_PRIVATE #include #include diff --git a/sys/arm/conf/BEAGLEBONE b/sys/arm/conf/BEAGLEBONE index 8b06d20069ae..bee9427a19d5 100644 --- a/sys/arm/conf/BEAGLEBONE +++ b/sys/arm/conf/BEAGLEBONE @@ -32,7 +32,7 @@ makeoptions MODULES_EXTRA="dtb/am335x" options KDTRACE_HOOKS # Kernel DTrace hooks options DDB_CTF # all architectures - kernel ELF linker loads CTF data makeoptions WITH_CTF=1 -makeoptions MODULES_EXTRA+="opensolaris dtrace dtrace/lockstat dtrace/profile dtrace/fbt" +makeoptions MODULES_EXTRA+="opensolaris dtrace dtrace/profile dtrace/fbt" options HZ=100 options SCHED_4BSD # 4BSD scheduler diff --git a/sys/arm/conf/NOTES b/sys/arm/conf/NOTES index 885bfd17b042..9f47b5957f6c 100644 --- a/sys/arm/conf/NOTES +++ b/sys/arm/conf/NOTES @@ -98,7 +98,6 @@ options KDTRACE_HOOKS #device dtrace # DTrace modules -#device dtrace_lockstat #device dtrace_profile #device dtrace_sdt #device dtrace_fbt diff --git a/sys/arm/conf/std.armv6 b/sys/arm/conf/std.armv6 index c1c646bf15f2..b022ab596919 100644 --- a/sys/arm/conf/std.armv6 +++ b/sys/arm/conf/std.armv6 @@ -32,6 +32,7 @@ options SYSVSHM # SYSV-style shared memory options SYSVMSG # SYSV-style message queues options SYSVSEM # SYSV-style semaphores options _KPOSIX_PRIORITY_SCHEDULING # POSIX P1003_1B real-time extensions +options PRINTF_BUFR_SIZE=128 # Prevent printf output being interspersed. options KBD_INSTALL_CDEV # install a CDEV entry in /dev options FREEBSD_BOOT_LOADER # Process metadata passed from loader(8) options VFP # Enable floating point hardware support diff --git a/sys/arm/include/atomic-v4.h b/sys/arm/include/atomic-v4.h new file mode 100644 index 000000000000..7048178f3046 --- /dev/null +++ b/sys/arm/include/atomic-v4.h @@ -0,0 +1,442 @@ +/* $NetBSD: atomic.h,v 1.1 2002/10/19 12:22:34 bsh Exp $ */ + +/*- + * Copyright (C) 2003-2004 Olivier Houchard + * Copyright (C) 1994-1997 Mark Brinicombe + * Copyright (C) 1994 Brini + * All rights reserved. + * + * This code is derived from software written for Brini by Mark Brinicombe + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Brini. + * 4. The name of Brini may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_ATOMIC_V4_H_ +#define _MACHINE_ATOMIC_V4_H_ + +#ifndef _MACHINE_ATOMIC_H_ +#error Do not include this file directly, use +#endif + +#if __ARM_ARCH <= 5 +#define isb() __asm __volatile("mcr p15, 0, %0, c7, c5, 4" : : "r" (0) : "memory") +#define dsb() __asm __volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0) : "memory") +#define dmb() dsb() +#else +#error Only use this file with ARMv5 and earlier +#endif + +#define mb() dmb() +#define wmb() dmb() +#define rmb() dmb() + +#define __with_interrupts_disabled(expr) \ + do { \ + u_int cpsr_save, tmp; \ + \ + __asm __volatile( \ + "mrs %0, cpsr;" \ + "orr %1, %0, %2;" \ + "msr cpsr_fsxc, %1;" \ + : "=r" (cpsr_save), "=r" (tmp) \ + : "I" (PSR_I | PSR_F) \ + : "cc" ); \ + (expr); \ + __asm __volatile( \ + "msr cpsr_fsxc, %0" \ + : /* no output */ \ + : "r" (cpsr_save) \ + : "cc" ); \ + } while(0) + +static __inline uint32_t +__swp(uint32_t val, volatile uint32_t *ptr) +{ + __asm __volatile("swp %0, %2, [%3]" + : "=&r" (val), "=m" (*ptr) + : "r" (val), "r" (ptr), "m" (*ptr) + : "memory"); + return (val); +} + + +#ifdef _KERNEL +#define ARM_HAVE_ATOMIC64 + +static __inline void +atomic_add_32(volatile u_int32_t *p, u_int32_t val) +{ + __with_interrupts_disabled(*p += val); +} + +static __inline void +atomic_add_64(volatile u_int64_t *p, u_int64_t val) +{ + __with_interrupts_disabled(*p += val); +} + +static __inline void +atomic_clear_32(volatile uint32_t *address, uint32_t clearmask) +{ + __with_interrupts_disabled(*address &= ~clearmask); +} + +static __inline void +atomic_clear_64(volatile uint64_t *address, uint64_t clearmask) +{ + __with_interrupts_disabled(*address &= ~clearmask); +} + +static __inline u_int32_t +atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval) +{ + int ret; + + __with_interrupts_disabled( + { + if (*p == cmpval) { + *p = newval; + ret = 1; + } else { + ret = 0; + } + }); + return (ret); +} + +static __inline u_int64_t +atomic_cmpset_64(volatile u_int64_t *p, volatile u_int64_t cmpval, volatile u_int64_t newval) +{ + int ret; + + __with_interrupts_disabled( + { + if (*p == cmpval) { + *p = newval; + ret = 1; + } else { + ret = 0; + } + }); + return (ret); +} + + +static __inline uint32_t +atomic_fetchadd_32(volatile uint32_t *p, uint32_t v) +{ + uint32_t value; + + __with_interrupts_disabled( + { + value = *p; + *p += v; + }); + return (value); +} + +static __inline uint64_t +atomic_fetchadd_64(volatile uint64_t *p, uint64_t v) +{ + uint64_t value; + + __with_interrupts_disabled( + { + value = *p; + *p += v; + }); + return (value); +} + +static __inline uint64_t +atomic_load_64(volatile uint64_t *p) +{ + uint64_t value; + + __with_interrupts_disabled(value = *p); + return (value); +} + +static __inline void +atomic_set_32(volatile uint32_t *address, uint32_t setmask) +{ + __with_interrupts_disabled(*address |= setmask); +} + +static __inline void +atomic_set_64(volatile uint64_t *address, uint64_t setmask) +{ + __with_interrupts_disabled(*address |= setmask); +} + +static __inline void +atomic_store_64(volatile uint64_t *p, uint64_t value) +{ + __with_interrupts_disabled(*p = value); +} + +static __inline void +atomic_subtract_32(volatile u_int32_t *p, u_int32_t val) +{ + __with_interrupts_disabled(*p -= val); +} + +static __inline void +atomic_subtract_64(volatile u_int64_t *p, u_int64_t val) +{ + __with_interrupts_disabled(*p -= val); +} + +#else /* !_KERNEL */ + +static __inline void +atomic_add_32(volatile u_int32_t *p, u_int32_t val) +{ + int start, ras_start = ARM_RAS_START; + + __asm __volatile("1:\n" + "adr %1, 1b\n" + "str %1, [%0]\n" + "adr %1, 2f\n" + "str %1, [%0, #4]\n" + "ldr %1, [%2]\n" + "add %1, %1, %3\n" + "str %1, [%2]\n" + "2:\n" + "mov %1, #0\n" + "str %1, [%0]\n" + "mov %1, #0xffffffff\n" + "str %1, [%0, #4]\n" + : "+r" (ras_start), "=r" (start), "+r" (p), "+r" (val) + : : "memory"); +} + +static __inline void +atomic_clear_32(volatile uint32_t *address, uint32_t clearmask) +{ + int start, ras_start = ARM_RAS_START; + + __asm __volatile("1:\n" + "adr %1, 1b\n" + "str %1, [%0]\n" + "adr %1, 2f\n" + "str %1, [%0, #4]\n" + "ldr %1, [%2]\n" + "bic %1, %1, %3\n" + "str %1, [%2]\n" + "2:\n" + "mov %1, #0\n" + "str %1, [%0]\n" + "mov %1, #0xffffffff\n" + "str %1, [%0, #4]\n" + : "+r" (ras_start), "=r" (start), "+r" (address), "+r" (clearmask) + : : "memory"); + +} + +static __inline u_int32_t +atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval) +{ + register int done, ras_start = ARM_RAS_START; + + __asm __volatile("1:\n" + "adr %1, 1b\n" + "str %1, [%0]\n" + "adr %1, 2f\n" + "str %1, [%0, #4]\n" + "ldr %1, [%2]\n" + "cmp %1, %3\n" + "streq %4, [%2]\n" + "2:\n" + "mov %1, #0\n" + "str %1, [%0]\n" + "mov %1, #0xffffffff\n" + "str %1, [%0, #4]\n" + "moveq %1, #1\n" + "movne %1, #0\n" + : "+r" (ras_start), "=r" (done) + ,"+r" (p), "+r" (cmpval), "+r" (newval) : : "cc", "memory"); + return (done); +} + +static __inline uint32_t +atomic_fetchadd_32(volatile uint32_t *p, uint32_t v) +{ + uint32_t start, tmp, ras_start = ARM_RAS_START; + + __asm __volatile("1:\n" + "adr %1, 1b\n" + "str %1, [%0]\n" + "adr %1, 2f\n" + "str %1, [%0, #4]\n" + "ldr %1, [%3]\n" + "mov %2, %1\n" + "add %2, %2, %4\n" + "str %2, [%3]\n" + "2:\n" + "mov %2, #0\n" + "str %2, [%0]\n" + "mov %2, #0xffffffff\n" + "str %2, [%0, #4]\n" + : "+r" (ras_start), "=r" (start), "=r" (tmp), "+r" (p), "+r" (v) + : : "memory"); + return (start); +} + +static __inline void +atomic_set_32(volatile uint32_t *address, uint32_t setmask) +{ + int start, ras_start = ARM_RAS_START; + + __asm __volatile("1:\n" + "adr %1, 1b\n" + "str %1, [%0]\n" + "adr %1, 2f\n" + "str %1, [%0, #4]\n" + "ldr %1, [%2]\n" + "orr %1, %1, %3\n" + "str %1, [%2]\n" + "2:\n" + "mov %1, #0\n" + "str %1, [%0]\n" + "mov %1, #0xffffffff\n" + "str %1, [%0, #4]\n" + + : "+r" (ras_start), "=r" (start), "+r" (address), "+r" (setmask) + : : "memory"); +} + +static __inline void +atomic_subtract_32(volatile u_int32_t *p, u_int32_t val) +{ + int start, ras_start = ARM_RAS_START; + + __asm __volatile("1:\n" + "adr %1, 1b\n" + "str %1, [%0]\n" + "adr %1, 2f\n" + "str %1, [%0, #4]\n" + "ldr %1, [%2]\n" + "sub %1, %1, %3\n" + "str %1, [%2]\n" + "2:\n" + "mov %1, #0\n" + "str %1, [%0]\n" + "mov %1, #0xffffffff\n" + "str %1, [%0, #4]\n" + + : "+r" (ras_start), "=r" (start), "+r" (p), "+r" (val) + : : "memory"); +} + +#endif /* _KERNEL */ + +static __inline uint32_t +atomic_readandclear_32(volatile u_int32_t *p) +{ + + return (__swp(0, p)); +} + +#define atomic_cmpset_rel_32 atomic_cmpset_32 +#define atomic_cmpset_acq_32 atomic_cmpset_32 +#define atomic_set_rel_32 atomic_set_32 +#define atomic_set_acq_32 atomic_set_32 +#define atomic_clear_rel_32 atomic_clear_32 +#define atomic_clear_acq_32 atomic_clear_32 +#define atomic_add_rel_32 atomic_add_32 +#define atomic_add_acq_32 atomic_add_32 +#define atomic_subtract_rel_32 atomic_subtract_32 +#define atomic_subtract_acq_32 atomic_subtract_32 +#define atomic_store_rel_32 atomic_store_32 +#define atomic_store_rel_long atomic_store_long +#define atomic_load_acq_32 atomic_load_32 +#define atomic_load_acq_long atomic_load_long +#define atomic_add_acq_long atomic_add_long +#define atomic_add_rel_long atomic_add_long +#define atomic_subtract_acq_long atomic_subtract_long +#define atomic_subtract_rel_long atomic_subtract_long +#define atomic_clear_acq_long atomic_clear_long +#define atomic_clear_rel_long atomic_clear_long +#define atomic_set_acq_long atomic_set_long +#define atomic_set_rel_long atomic_set_long +#define atomic_cmpset_acq_long atomic_cmpset_long +#define atomic_cmpset_rel_long atomic_cmpset_long +#define atomic_load_acq_long atomic_load_long +#undef __with_interrupts_disabled + +static __inline void +atomic_add_long(volatile u_long *p, u_long v) +{ + + atomic_add_32((volatile uint32_t *)p, v); +} + +static __inline void +atomic_clear_long(volatile u_long *p, u_long v) +{ + + atomic_clear_32((volatile uint32_t *)p, v); +} + +static __inline int +atomic_cmpset_long(volatile u_long *dst, u_long old, u_long newe) +{ + + return (atomic_cmpset_32((volatile uint32_t *)dst, old, newe)); +} + +static __inline u_long +atomic_fetchadd_long(volatile u_long *p, u_long v) +{ + + return (atomic_fetchadd_32((volatile uint32_t *)p, v)); +} + +static __inline void +atomic_readandclear_long(volatile u_long *p) +{ + + atomic_readandclear_32((volatile uint32_t *)p); +} + +static __inline void +atomic_set_long(volatile u_long *p, u_long v) +{ + + atomic_set_32((volatile uint32_t *)p, v); +} + +static __inline void +atomic_subtract_long(volatile u_long *p, u_long v) +{ + + atomic_subtract_32((volatile uint32_t *)p, v); +} + +#endif /* _MACHINE_ATOMIC_H_ */ diff --git a/sys/arm/include/atomic-v6.h b/sys/arm/include/atomic-v6.h new file mode 100644 index 000000000000..06d8880192c7 --- /dev/null +++ b/sys/arm/include/atomic-v6.h @@ -0,0 +1,599 @@ +/* $NetBSD: atomic.h,v 1.1 2002/10/19 12:22:34 bsh Exp $ */ + +/*- + * Copyright (C) 2003-2004 Olivier Houchard + * Copyright (C) 1994-1997 Mark Brinicombe + * Copyright (C) 1994 Brini + * All rights reserved. + * + * This code is derived from software written for Brini by Mark Brinicombe + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Brini. + * 4. The name of Brini may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_ATOMIC_V6_H_ +#define _MACHINE_ATOMIC_V6_H_ + +#ifndef _MACHINE_ATOMIC_H_ +#error Do not include this file directly, use +#endif + +#if __ARM_ARCH >= 7 +#define isb() __asm __volatile("isb" : : : "memory") +#define dsb() __asm __volatile("dsb" : : : "memory") +#define dmb() __asm __volatile("dmb" : : : "memory") +#elif __ARM_ARCH >= 6 +#define isb() __asm __volatile("mcr p15, 0, %0, c7, c5, 4" : : "r" (0) : "memory") +#define dsb() __asm __volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0) : "memory") +#define dmb() __asm __volatile("mcr p15, 0, %0, c7, c10, 5" : : "r" (0) : "memory") +#else +#error Only use this file with ARMv6 and later +#endif + +#define mb() dmb() +#define wmb() dmb() +#define rmb() dmb() + +#define ARM_HAVE_ATOMIC64 + +#define ATOMIC_ACQ_REL_LONG(NAME) \ +static __inline void \ +atomic_##NAME##_acq_long(__volatile u_long *p, u_long v) \ +{ \ + atomic_##NAME##_long(p, v); \ + dmb(); \ +} \ + \ +static __inline void \ +atomic_##NAME##_rel_long(__volatile u_long *p, u_long v) \ +{ \ + dmb(); \ + atomic_##NAME##_long(p, v); \ +} + +#define ATOMIC_ACQ_REL(NAME, WIDTH) \ +static __inline void \ +atomic_##NAME##_acq_##WIDTH(__volatile uint##WIDTH##_t *p, uint##WIDTH##_t v)\ +{ \ + atomic_##NAME##_##WIDTH(p, v); \ + dmb(); \ +} \ + \ +static __inline void \ +atomic_##NAME##_rel_##WIDTH(__volatile uint##WIDTH##_t *p, uint##WIDTH##_t v)\ +{ \ + dmb(); \ + atomic_##NAME##_##WIDTH(p, v); \ +} + + +static __inline void +atomic_add_32(volatile uint32_t *p, uint32_t val) +{ + uint32_t tmp = 0, tmp2 = 0; + + __asm __volatile( + "1: ldrex %0, [%2] \n" + " add %0, %0, %3 \n" + " strex %1, %0, [%2] \n" + " cmp %1, #0 \n" + " it ne \n" + " bne 1b \n" + : "=&r" (tmp), "+r" (tmp2) + ,"+r" (p), "+r" (val) : : "cc", "memory"); +} + +static __inline void +atomic_add_64(volatile uint64_t *p, uint64_t val) +{ + uint64_t tmp; + uint32_t exflag; + + __asm __volatile( + "1: \n" + " ldrexd %Q[tmp], %R[tmp], [%[ptr]] \n" + " adds %Q[tmp], %Q[val] \n" + " adc %R[tmp], %R[tmp], %R[val] \n" + " strexd %[exf], %Q[tmp], %R[tmp], [%[ptr]] \n" + " teq %[exf], #0 \n" + " it ne \n" + " bne 1b \n" + : [exf] "=&r" (exflag), + [tmp] "=&r" (tmp) + : [ptr] "r" (p), + [val] "r" (val) + : "cc", "memory"); +} + +static __inline void +atomic_add_long(volatile u_long *p, u_long val) +{ + + atomic_add_32((volatile uint32_t *)p, val); +} + +ATOMIC_ACQ_REL(add, 32) +ATOMIC_ACQ_REL(add, 64) +ATOMIC_ACQ_REL_LONG(add) + +static __inline void +atomic_clear_32(volatile uint32_t *address, uint32_t setmask) +{ + uint32_t tmp = 0, tmp2 = 0; + + __asm __volatile( + "1: ldrex %0, [%2] \n" + " bic %0, %0, %3 \n" + " strex %1, %0, [%2] \n" + " cmp %1, #0 \n" + " it ne \n" + " bne 1b \n" + : "=&r" (tmp), "+r" (tmp2), "+r" (address), "+r" (setmask) + : : "cc", "memory"); +} + +static __inline void +atomic_clear_64(volatile uint64_t *p, uint64_t val) +{ + uint64_t tmp; + uint32_t exflag; + + __asm __volatile( + "1: \n" + " ldrexd %Q[tmp], %R[tmp], [%[ptr]] \n" + " bic %Q[tmp], %Q[val] \n" + " bic %R[tmp], %R[val] \n" + " strexd %[exf], %Q[tmp], %R[tmp], [%[ptr]] \n" + " teq %[exf], #0 \n" + " it ne \n" + " bne 1b \n" + : [exf] "=&r" (exflag), + [tmp] "=&r" (tmp) + : [ptr] "r" (p), + [val] "r" (val) + : "cc", "memory"); +} + +static __inline void +atomic_clear_long(volatile u_long *address, u_long setmask) +{ + + atomic_clear_32((volatile uint32_t *)address, setmask); +} + +ATOMIC_ACQ_REL(clear, 32) +ATOMIC_ACQ_REL(clear, 64) +ATOMIC_ACQ_REL_LONG(clear) + +static __inline uint32_t +atomic_cmpset_32(volatile uint32_t *p, uint32_t cmpval, uint32_t newval) +{ + uint32_t ret; + + __asm __volatile( + "1: ldrex %0, [%1] \n" + " cmp %0, %2 \n" + " itt ne \n" + " movne %0, #0 \n" + " bne 2f \n" + " strex %0, %3, [%1] \n" + " cmp %0, #0 \n" + " ite eq \n" + " moveq %0, #1 \n" + " bne 1b \n" + "2:" + : "=&r" (ret), "+r" (p), "+r" (cmpval), "+r" (newval) + : : "cc", "memory"); + return (ret); +} + +static __inline int +atomic_cmpset_64(volatile uint64_t *p, uint64_t cmpval, uint64_t newval) +{ + uint64_t tmp; + uint32_t ret; + + __asm __volatile( + "1: \n" + " ldrexd %Q[tmp], %R[tmp], [%[ptr]] \n" + " teq %Q[tmp], %Q[cmpval] \n" + " itee eq \n" + " teqeq %R[tmp], %R[cmpval] \n" + " movne %[ret], #0 \n" + " bne 2f \n" + " strexd %[ret], %Q[newval], %R[newval], [%[ptr]]\n" + " teq %[ret], #0 \n" + " it ne \n" + " bne 1b \n" + " mov %[ret], #1 \n" + "2: \n" + : [ret] "=&r" (ret), + [tmp] "=&r" (tmp) + : [ptr] "r" (p), + [cmpval] "r" (cmpval), + [newval] "r" (newval) + : "cc", "memory"); + return (ret); +} + +static __inline u_long +atomic_cmpset_long(volatile u_long *p, u_long cmpval, u_long newval) +{ + + return (atomic_cmpset_32((volatile uint32_t *)p, cmpval, newval)); +} + +static __inline uint32_t +atomic_cmpset_acq_32(volatile uint32_t *p, uint32_t cmpval, uint32_t newval) +{ + uint32_t ret; + + ret = atomic_cmpset_32(p, cmpval, newval); + dmb(); + return (ret); +} + +static __inline uint64_t +atomic_cmpset_acq_64(volatile uint64_t *p, uint64_t cmpval, uint64_t newval) +{ + uint64_t ret; + + ret = atomic_cmpset_64(p, cmpval, newval); + dmb(); + return (ret); +} + +static __inline u_long +atomic_cmpset_acq_long(volatile u_long *p, u_long cmpval, u_long newval) +{ + u_long ret; + + ret = atomic_cmpset_long(p, cmpval, newval); + dmb(); + return (ret); +} + +static __inline uint32_t +atomic_cmpset_rel_32(volatile uint32_t *p, uint32_t cmpval, uint32_t newval) +{ + + dmb(); + return (atomic_cmpset_32(p, cmpval, newval)); +} + +static __inline uint64_t +atomic_cmpset_rel_64(volatile uint64_t *p, uint64_t cmpval, uint64_t newval) +{ + + dmb(); + return (atomic_cmpset_64(p, cmpval, newval)); +} + +static __inline u_long +atomic_cmpset_rel_long(volatile u_long *p, u_long cmpval, u_long newval) +{ + + dmb(); + return (atomic_cmpset_long(p, cmpval, newval)); +} + +static __inline uint32_t +atomic_fetchadd_32(volatile uint32_t *p, uint32_t val) +{ + uint32_t tmp = 0, tmp2 = 0, ret = 0; + + __asm __volatile( + "1: ldrex %0, [%3] \n" + " add %1, %0, %4 \n" + " strex %2, %1, [%3] \n" + " cmp %2, #0 \n" + " it ne \n" + " bne 1b \n" + : "+r" (ret), "=&r" (tmp), "+r" (tmp2), "+r" (p), "+r" (val) + : : "cc", "memory"); + return (ret); +} + +static __inline uint64_t +atomic_fetchadd_64(volatile uint64_t *p, uint64_t val) +{ + uint64_t ret, tmp; + uint32_t exflag; + + __asm __volatile( + "1: \n" + " ldrexd %Q[tmp], %R[tmp], [%[ptr]] \n" + " adds %Q[tmp], %Q[ret], %Q[val] \n" + " adc %R[tmp], %R[ret], %R[val] \n" + " strexd %[exf], %Q[tmp], %R[tmp], [%[ptr]] \n" + " teq %[exf], #0 \n" + " it ne \n" + " bne 1b \n" + : [ret] "=&r" (ret), + [exf] "=&r" (exflag), + [tmp] "=&r" (tmp) + : [ptr] "r" (p), + [val] "r" (val) + : "cc", "memory"); + return (ret); +} + +static __inline u_long +atomic_fetchadd_long(volatile u_long *p, u_long val) +{ + + return (atomic_fetchadd_32((volatile uint32_t *)p, val)); +} + +static __inline uint32_t +atomic_load_acq_32(volatile uint32_t *p) +{ + uint32_t v; + + v = *p; + dmb(); + return (v); +} + +static __inline uint64_t +atomic_load_64(volatile uint64_t *p) +{ + uint64_t ret; + + /* + * The only way to atomically load 64 bits is with LDREXD which puts the + * exclusive monitor into the exclusive state, so reset it to open state + * with CLREX because we don't actually need to store anything. + */ + __asm __volatile( + "ldrexd %Q[ret], %R[ret], [%[ptr]] \n" + "clrex \n" + : [ret] "=&r" (ret) + : [ptr] "r" (p) + : "cc", "memory"); + return (ret); +} + +static __inline uint64_t +atomic_load_acq_64(volatile uint64_t *p) +{ + uint64_t ret; + + ret = atomic_load_64(p); + dmb(); + return (ret); +} + +static __inline u_long +atomic_load_acq_long(volatile u_long *p) +{ + u_long v; + + v = *p; + dmb(); + return (v); +} + +static __inline uint32_t +atomic_readandclear_32(volatile uint32_t *p) +{ + uint32_t ret, tmp = 0, tmp2 = 0; + + __asm __volatile( + "1: ldrex %0, [%3] \n" + " mov %1, #0 \n" + " strex %2, %1, [%3] \n" + " cmp %2, #0 \n" + " it ne \n" + " bne 1b \n" + : "=r" (ret), "=&r" (tmp), "+r" (tmp2), "+r" (p) + : : "cc", "memory"); + return (ret); +} + +static __inline uint64_t +atomic_readandclear_64(volatile uint64_t *p) +{ + uint64_t ret, tmp; + uint32_t exflag; + + __asm __volatile( + "1: \n" + " ldrexd %Q[ret], %R[ret], [%[ptr]] \n" + " mov %Q[tmp], #0 \n" + " mov %R[tmp], #0 \n" + " strexd %[exf], %Q[tmp], %R[tmp], [%[ptr]] \n" + " teq %[exf], #0 \n" + " it ne \n" + " bne 1b \n" + : [ret] "=&r" (ret), + [exf] "=&r" (exflag), + [tmp] "=&r" (tmp) + : [ptr] "r" (p) + : "cc", "memory"); + return (ret); +} + +static __inline u_long +atomic_readandclear_long(volatile u_long *p) +{ + + return (atomic_readandclear_32((volatile uint32_t *)p)); +} + +static __inline void +atomic_set_32(volatile uint32_t *address, uint32_t setmask) +{ + uint32_t tmp = 0, tmp2 = 0; + + __asm __volatile( + "1: ldrex %0, [%2] \n" + " orr %0, %0, %3 \n" + " strex %1, %0, [%2] \n" + " cmp %1, #0 \n" + " it ne \n" + " bne 1b \n" + : "=&r" (tmp), "+r" (tmp2), "+r" (address), "+r" (setmask) + : : "cc", "memory"); +} + +static __inline void +atomic_set_64(volatile uint64_t *p, uint64_t val) +{ + uint64_t tmp; + uint32_t exflag; + + __asm __volatile( + "1: \n" + " ldrexd %Q[tmp], %R[tmp], [%[ptr]] \n" + " orr %Q[tmp], %Q[val] \n" + " orr %R[tmp], %R[val] \n" + " strexd %[exf], %Q[tmp], %R[tmp], [%[ptr]] \n" + " teq %[exf], #0 \n" + " it ne \n" + " bne 1b \n" + : [exf] "=&r" (exflag), + [tmp] "=&r" (tmp) + : [ptr] "r" (p), + [val] "r" (val) + : "cc", "memory"); +} + +static __inline void +atomic_set_long(volatile u_long *address, u_long setmask) +{ + + atomic_set_32((volatile uint32_t *)address, setmask); +} + +ATOMIC_ACQ_REL(set, 32) +ATOMIC_ACQ_REL(set, 64) +ATOMIC_ACQ_REL_LONG(set) + +static __inline void +atomic_subtract_32(volatile uint32_t *p, uint32_t val) +{ + uint32_t tmp = 0, tmp2 = 0; + + __asm __volatile( + "1: ldrex %0, [%2] \n" + " sub %0, %0, %3 \n" + " strex %1, %0, [%2] \n" + " cmp %1, #0 \n" + " it ne \n" + " bne 1b \n" + : "=&r" (tmp), "+r" (tmp2), "+r" (p), "+r" (val) + : : "cc", "memory"); +} + +static __inline void +atomic_subtract_64(volatile uint64_t *p, uint64_t val) +{ + uint64_t tmp; + uint32_t exflag; + + __asm __volatile( + "1: \n" + " ldrexd %Q[tmp], %R[tmp], [%[ptr]] \n" + " subs %Q[tmp], %Q[val] \n" + " sbc %R[tmp], %R[tmp], %R[val] \n" + " strexd %[exf], %Q[tmp], %R[tmp], [%[ptr]] \n" + " teq %[exf], #0 \n" + " it ne \n" + " bne 1b \n" + : [exf] "=&r" (exflag), + [tmp] "=&r" (tmp) + : [ptr] "r" (p), + [val] "r" (val) + : "cc", "memory"); +} + +static __inline void +atomic_subtract_long(volatile u_long *p, u_long val) +{ + + atomic_subtract_32((volatile uint32_t *)p, val); +} + +ATOMIC_ACQ_REL(subtract, 32) +ATOMIC_ACQ_REL(subtract, 64) +ATOMIC_ACQ_REL_LONG(subtract) + +static __inline void +atomic_store_64(volatile uint64_t *p, uint64_t val) +{ + uint64_t tmp; + uint32_t exflag; + + /* + * The only way to atomically store 64 bits is with STREXD, which will + * succeed only if paired up with a preceeding LDREXD using the same + * address, so we read and discard the existing value before storing. + */ + __asm __volatile( + "1: \n" + " ldrexd %Q[tmp], %R[tmp], [%[ptr]] \n" + " strexd %[exf], %Q[val], %R[val], [%[ptr]] \n" + " teq %[exf], #0 \n" + " it ne \n" + " bne 1b \n" + : [tmp] "=&r" (tmp), + [exf] "=&r" (exflag) + : [ptr] "r" (p), + [val] "r" (val) + : "cc", "memory"); +} + +static __inline void +atomic_store_rel_32(volatile uint32_t *p, uint32_t v) +{ + + dmb(); + *p = v; +} + +static __inline void +atomic_store_rel_64(volatile uint64_t *p, uint64_t val) +{ + + dmb(); + atomic_store_64(p, val); +} + +static __inline void +atomic_store_rel_long(volatile u_long *p, u_long v) +{ + + dmb(); + *p = v; +} + +#undef ATOMIC_ACQ_REL +#undef ATOMIC_ACQ_REL_LONG + +#endif /* _MACHINE_ATOMIC_V6_H_ */ diff --git a/sys/arm/include/atomic.h b/sys/arm/include/atomic.h index 140a3bc36d8f..5379030e499f 100644 --- a/sys/arm/include/atomic.h +++ b/sys/arm/include/atomic.h @@ -42,1039 +42,18 @@ #include #include +#include + #ifndef _KERNEL #include #else #include #endif -#if defined (__ARM_ARCH_7__) || defined (__ARM_ARCH_7A__) -#define isb() __asm __volatile("isb" : : : "memory") -#define dsb() __asm __volatile("dsb" : : : "memory") -#define dmb() __asm __volatile("dmb" : : : "memory") -#elif defined (__ARM_ARCH_6__) || defined (__ARM_ARCH_6J__) || \ - defined (__ARM_ARCH_6K__) || defined (__ARM_ARCH_6T2__) || \ - defined (__ARM_ARCH_6Z__) || defined (__ARM_ARCH_6ZK__) -#define isb() __asm __volatile("mcr p15, 0, %0, c7, c5, 4" : : "r" (0) : "memory") -#define dsb() __asm __volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0) : "memory") -#define dmb() __asm __volatile("mcr p15, 0, %0, c7, c10, 5" : : "r" (0) : "memory") -#else -#define isb() __asm __volatile("mcr p15, 0, %0, c7, c5, 4" : : "r" (0) : "memory") -#define dsb() __asm __volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0) : "memory") -#define dmb() dsb() -#endif - -#define mb() dmb() -#define wmb() dmb() -#define rmb() dmb() - - - -/* - * It would be nice to use _HAVE_ARMv6_INSTRUCTIONS from machine/asm.h - * here, but that header can't be included here because this is C - * code. I would like to move the _HAVE_ARMv6_INSTRUCTIONS definition - * out of asm.h so it can be used in both asm and C code. - kientzle@ - */ -#if defined (__ARM_ARCH_7__) || \ - defined (__ARM_ARCH_7A__) || \ - defined (__ARM_ARCH_6__) || \ - defined (__ARM_ARCH_6J__) || \ - defined (__ARM_ARCH_6K__) || \ - defined (__ARM_ARCH_6T2__) || \ - defined (__ARM_ARCH_6Z__) || \ - defined (__ARM_ARCH_6ZK__) -#define ARM_HAVE_ATOMIC64 - -static __inline void -__do_dmb(void) -{ - -#if defined (__ARM_ARCH_7__) || defined (__ARM_ARCH_7A__) - __asm __volatile("dmb" : : : "memory"); -#else - __asm __volatile("mcr p15, 0, r0, c7, c10, 5" : : : "memory"); -#endif -} - -#define ATOMIC_ACQ_REL_LONG(NAME) \ -static __inline void \ -atomic_##NAME##_acq_long(__volatile u_long *p, u_long v) \ -{ \ - atomic_##NAME##_long(p, v); \ - __do_dmb(); \ -} \ - \ -static __inline void \ -atomic_##NAME##_rel_long(__volatile u_long *p, u_long v) \ -{ \ - __do_dmb(); \ - atomic_##NAME##_long(p, v); \ -} - -#define ATOMIC_ACQ_REL(NAME, WIDTH) \ -static __inline void \ -atomic_##NAME##_acq_##WIDTH(__volatile uint##WIDTH##_t *p, uint##WIDTH##_t v)\ -{ \ - atomic_##NAME##_##WIDTH(p, v); \ - __do_dmb(); \ -} \ - \ -static __inline void \ -atomic_##NAME##_rel_##WIDTH(__volatile uint##WIDTH##_t *p, uint##WIDTH##_t v)\ -{ \ - __do_dmb(); \ - atomic_##NAME##_##WIDTH(p, v); \ -} - -static __inline void -atomic_set_32(volatile uint32_t *address, uint32_t setmask) -{ - uint32_t tmp = 0, tmp2 = 0; - - __asm __volatile("1: ldrex %0, [%2]\n" - "orr %0, %0, %3\n" - "strex %1, %0, [%2]\n" - "cmp %1, #0\n" - "it ne\n" - "bne 1b\n" - : "=&r" (tmp), "+r" (tmp2) - , "+r" (address), "+r" (setmask) : : "cc", "memory"); - -} - -static __inline void -atomic_set_64(volatile uint64_t *p, uint64_t val) -{ - uint64_t tmp; - uint32_t exflag; - - __asm __volatile( - "1: \n" - " ldrexd %Q[tmp], %R[tmp], [%[ptr]]\n" - " orr %Q[tmp], %Q[val]\n" - " orr %R[tmp], %R[val]\n" - " strexd %[exf], %Q[tmp], %R[tmp], [%[ptr]]\n" - " teq %[exf], #0\n" - " it ne \n" - " bne 1b\n" - : [exf] "=&r" (exflag), - [tmp] "=&r" (tmp) - : [ptr] "r" (p), - [val] "r" (val) - : "cc", "memory"); -} - -static __inline void -atomic_set_long(volatile u_long *address, u_long setmask) -{ - u_long tmp = 0, tmp2 = 0; - - __asm __volatile("1: ldrex %0, [%2]\n" - "orr %0, %0, %3\n" - "strex %1, %0, [%2]\n" - "cmp %1, #0\n" - "it ne\n" - "bne 1b\n" - : "=&r" (tmp), "+r" (tmp2) - , "+r" (address), "+r" (setmask) : : "cc", "memory"); - -} - -static __inline void -atomic_clear_32(volatile uint32_t *address, uint32_t setmask) -{ - uint32_t tmp = 0, tmp2 = 0; - - __asm __volatile("1: ldrex %0, [%2]\n" - "bic %0, %0, %3\n" - "strex %1, %0, [%2]\n" - "cmp %1, #0\n" - "it ne\n" - "bne 1b\n" - : "=&r" (tmp), "+r" (tmp2) - ,"+r" (address), "+r" (setmask) : : "cc", "memory"); -} - -static __inline void -atomic_clear_64(volatile uint64_t *p, uint64_t val) -{ - uint64_t tmp; - uint32_t exflag; - - __asm __volatile( - "1: \n" - " ldrexd %Q[tmp], %R[tmp], [%[ptr]]\n" - " bic %Q[tmp], %Q[val]\n" - " bic %R[tmp], %R[val]\n" - " strexd %[exf], %Q[tmp], %R[tmp], [%[ptr]]\n" - " teq %[exf], #0\n" - " it ne \n" - " bne 1b\n" - : [exf] "=&r" (exflag), - [tmp] "=&r" (tmp) - : [ptr] "r" (p), - [val] "r" (val) - : "cc", "memory"); -} - -static __inline void -atomic_clear_long(volatile u_long *address, u_long setmask) -{ - u_long tmp = 0, tmp2 = 0; - - __asm __volatile("1: ldrex %0, [%2]\n" - "bic %0, %0, %3\n" - "strex %1, %0, [%2]\n" - "cmp %1, #0\n" - "it ne\n" - "bne 1b\n" - : "=&r" (tmp), "+r" (tmp2) - ,"+r" (address), "+r" (setmask) : : "cc", "memory"); -} - -static __inline u_int32_t -atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval) -{ - uint32_t ret; - - __asm __volatile("1: ldrex %0, [%1]\n" - "cmp %0, %2\n" - "itt ne\n" - "movne %0, #0\n" - "bne 2f\n" - "strex %0, %3, [%1]\n" - "cmp %0, #0\n" - "ite eq\n" - "moveq %0, #1\n" - "bne 1b\n" - "2:" - : "=&r" (ret) - ,"+r" (p), "+r" (cmpval), "+r" (newval) : : "cc", - "memory"); - return (ret); -} - -static __inline int -atomic_cmpset_64(volatile uint64_t *p, uint64_t cmpval, uint64_t newval) -{ - uint64_t tmp; - uint32_t ret; - - __asm __volatile( - "1: \n" - " ldrexd %Q[tmp], %R[tmp], [%[ptr]]\n" - " teq %Q[tmp], %Q[cmpval]\n" - " itee eq \n" - " teqeq %R[tmp], %R[cmpval]\n" - " movne %[ret], #0\n" - " bne 2f\n" - " strexd %[ret], %Q[newval], %R[newval], [%[ptr]]\n" - " teq %[ret], #0\n" - " it ne \n" - " bne 1b\n" - " mov %[ret], #1\n" - "2: \n" - : [ret] "=&r" (ret), - [tmp] "=&r" (tmp) - : [ptr] "r" (p), - [cmpval] "r" (cmpval), - [newval] "r" (newval) - : "cc", "memory"); - return (ret); -} - -static __inline u_long -atomic_cmpset_long(volatile u_long *p, volatile u_long cmpval, volatile u_long newval) -{ - u_long ret; - - __asm __volatile("1: ldrex %0, [%1]\n" - "cmp %0, %2\n" - "itt ne\n" - "movne %0, #0\n" - "bne 2f\n" - "strex %0, %3, [%1]\n" - "cmp %0, #0\n" - "ite eq\n" - "moveq %0, #1\n" - "bne 1b\n" - "2:" - : "=&r" (ret) - ,"+r" (p), "+r" (cmpval), "+r" (newval) : : "cc", - "memory"); - return (ret); -} - -static __inline u_int32_t -atomic_cmpset_acq_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval) -{ - u_int32_t ret = atomic_cmpset_32(p, cmpval, newval); - - __do_dmb(); - return (ret); -} - -static __inline uint64_t -atomic_cmpset_acq_64(volatile uint64_t *p, volatile uint64_t cmpval, volatile uint64_t newval) -{ - uint64_t ret = atomic_cmpset_64(p, cmpval, newval); - - __do_dmb(); - return (ret); -} - -static __inline u_long -atomic_cmpset_acq_long(volatile u_long *p, volatile u_long cmpval, volatile u_long newval) -{ - u_long ret = atomic_cmpset_long(p, cmpval, newval); - - __do_dmb(); - return (ret); -} - -static __inline u_int32_t -atomic_cmpset_rel_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval) -{ - - __do_dmb(); - return (atomic_cmpset_32(p, cmpval, newval)); -} - -static __inline uint64_t -atomic_cmpset_rel_64(volatile uint64_t *p, volatile uint64_t cmpval, volatile uint64_t newval) -{ - - __do_dmb(); - return (atomic_cmpset_64(p, cmpval, newval)); -} - -static __inline u_long -atomic_cmpset_rel_long(volatile u_long *p, volatile u_long cmpval, volatile u_long newval) -{ - - __do_dmb(); - return (atomic_cmpset_long(p, cmpval, newval)); -} - - -static __inline void -atomic_add_32(volatile u_int32_t *p, u_int32_t val) -{ - uint32_t tmp = 0, tmp2 = 0; - - __asm __volatile("1: ldrex %0, [%2]\n" - "add %0, %0, %3\n" - "strex %1, %0, [%2]\n" - "cmp %1, #0\n" - "it ne\n" - "bne 1b\n" - : "=&r" (tmp), "+r" (tmp2) - ,"+r" (p), "+r" (val) : : "cc", "memory"); -} - -static __inline void -atomic_add_64(volatile uint64_t *p, uint64_t val) -{ - uint64_t tmp; - uint32_t exflag; - - __asm __volatile( - "1: \n" - " ldrexd %Q[tmp], %R[tmp], [%[ptr]]\n" - " adds %Q[tmp], %Q[val]\n" - " adc %R[tmp], %R[tmp], %R[val]\n" - " strexd %[exf], %Q[tmp], %R[tmp], [%[ptr]]\n" - " teq %[exf], #0\n" - " it ne \n" - " bne 1b\n" - : [exf] "=&r" (exflag), - [tmp] "=&r" (tmp) - : [ptr] "r" (p), - [val] "r" (val) - : "cc", "memory"); -} - -static __inline void -atomic_add_long(volatile u_long *p, u_long val) -{ - u_long tmp = 0, tmp2 = 0; - - __asm __volatile("1: ldrex %0, [%2]\n" - "add %0, %0, %3\n" - "strex %1, %0, [%2]\n" - "cmp %1, #0\n" - "it ne\n" - "bne 1b\n" - : "=&r" (tmp), "+r" (tmp2) - ,"+r" (p), "+r" (val) : : "cc", "memory"); -} - -static __inline void -atomic_subtract_32(volatile u_int32_t *p, u_int32_t val) -{ - uint32_t tmp = 0, tmp2 = 0; - - __asm __volatile("1: ldrex %0, [%2]\n" - "sub %0, %0, %3\n" - "strex %1, %0, [%2]\n" - "cmp %1, #0\n" - "it ne\n" - "bne 1b\n" - : "=&r" (tmp), "+r" (tmp2) - ,"+r" (p), "+r" (val) : : "cc", "memory"); -} - -static __inline void -atomic_subtract_64(volatile uint64_t *p, uint64_t val) -{ - uint64_t tmp; - uint32_t exflag; - - __asm __volatile( - "1: \n" - " ldrexd %Q[tmp], %R[tmp], [%[ptr]]\n" - " subs %Q[tmp], %Q[val]\n" - " sbc %R[tmp], %R[tmp], %R[val]\n" - " strexd %[exf], %Q[tmp], %R[tmp], [%[ptr]]\n" - " teq %[exf], #0\n" - " it ne \n" - " bne 1b\n" - : [exf] "=&r" (exflag), - [tmp] "=&r" (tmp) - : [ptr] "r" (p), - [val] "r" (val) - : "cc", "memory"); -} - -static __inline void -atomic_subtract_long(volatile u_long *p, u_long val) -{ - u_long tmp = 0, tmp2 = 0; - - __asm __volatile("1: ldrex %0, [%2]\n" - "sub %0, %0, %3\n" - "strex %1, %0, [%2]\n" - "cmp %1, #0\n" - "it ne\n" - "bne 1b\n" - : "=&r" (tmp), "+r" (tmp2) - ,"+r" (p), "+r" (val) : : "cc", "memory"); -} - -ATOMIC_ACQ_REL(clear, 32) -ATOMIC_ACQ_REL(add, 32) -ATOMIC_ACQ_REL(subtract, 32) -ATOMIC_ACQ_REL(set, 32) -ATOMIC_ACQ_REL(clear, 64) -ATOMIC_ACQ_REL(add, 64) -ATOMIC_ACQ_REL(subtract, 64) -ATOMIC_ACQ_REL(set, 64) -ATOMIC_ACQ_REL_LONG(clear) -ATOMIC_ACQ_REL_LONG(add) -ATOMIC_ACQ_REL_LONG(subtract) -ATOMIC_ACQ_REL_LONG(set) - -#undef ATOMIC_ACQ_REL -#undef ATOMIC_ACQ_REL_LONG - -static __inline uint32_t -atomic_fetchadd_32(volatile uint32_t *p, uint32_t val) -{ - uint32_t tmp = 0, tmp2 = 0, ret = 0; - - __asm __volatile("1: ldrex %0, [%3]\n" - "add %1, %0, %4\n" - "strex %2, %1, [%3]\n" - "cmp %2, #0\n" - "it ne\n" - "bne 1b\n" - : "+r" (ret), "=&r" (tmp), "+r" (tmp2) - ,"+r" (p), "+r" (val) : : "cc", "memory"); - return (ret); -} - -static __inline uint32_t -atomic_readandclear_32(volatile u_int32_t *p) -{ - uint32_t ret, tmp = 0, tmp2 = 0; - - __asm __volatile("1: ldrex %0, [%3]\n" - "mov %1, #0\n" - "strex %2, %1, [%3]\n" - "cmp %2, #0\n" - "it ne\n" - "bne 1b\n" - : "=r" (ret), "=&r" (tmp), "+r" (tmp2) - ,"+r" (p) : : "cc", "memory"); - return (ret); -} - -static __inline uint32_t -atomic_load_acq_32(volatile uint32_t *p) -{ - uint32_t v; - - v = *p; - __do_dmb(); - return (v); -} - -static __inline void -atomic_store_rel_32(volatile uint32_t *p, uint32_t v) -{ - - __do_dmb(); - *p = v; -} - -static __inline uint64_t -atomic_fetchadd_64(volatile uint64_t *p, uint64_t val) -{ - uint64_t ret, tmp; - uint32_t exflag; - - __asm __volatile( - "1: \n" - " ldrexd %Q[tmp], %R[tmp], [%[ptr]]\n" - " adds %Q[tmp], %Q[ret], %Q[val]\n" - " adc %R[tmp], %R[ret], %R[val]\n" - " strexd %[exf], %Q[tmp], %R[tmp], [%[ptr]]\n" - " teq %[exf], #0\n" - " it ne \n" - " bne 1b\n" - : [ret] "=&r" (ret), - [exf] "=&r" (exflag), - [tmp] "=&r" (tmp) - : [ptr] "r" (p), - [val] "r" (val) - : "cc", "memory"); - return (ret); -} - -static __inline uint64_t -atomic_readandclear_64(volatile uint64_t *p) -{ - uint64_t ret, tmp; - uint32_t exflag; - - __asm __volatile( - "1: \n" - " ldrexd %Q[ret], %R[ret], [%[ptr]]\n" - " mov %Q[tmp], #0\n" - " mov %R[tmp], #0\n" - " strexd %[exf], %Q[tmp], %R[tmp], [%[ptr]]\n" - " teq %[exf], #0\n" - " it ne \n" - " bne 1b\n" - : [ret] "=&r" (ret), - [exf] "=&r" (exflag), - [tmp] "=&r" (tmp) - : [ptr] "r" (p) - : "cc", "memory"); - return (ret); -} - -static __inline uint64_t -atomic_load_64(volatile uint64_t *p) -{ - uint64_t ret; - - /* - * The only way to atomically load 64 bits is with LDREXD which puts the - * exclusive monitor into the exclusive state, so reset it to open state - * with CLREX because we don't actually need to store anything. - */ - __asm __volatile( - "1: \n" - " ldrexd %Q[ret], %R[ret], [%[ptr]]\n" - " clrex \n" - : [ret] "=&r" (ret) - : [ptr] "r" (p) - : "cc", "memory"); - return (ret); -} - -static __inline uint64_t -atomic_load_acq_64(volatile uint64_t *p) -{ - uint64_t ret; - - ret = atomic_load_64(p); - __do_dmb(); - return (ret); -} - -static __inline void -atomic_store_64(volatile uint64_t *p, uint64_t val) -{ - uint64_t tmp; - uint32_t exflag; - - /* - * The only way to atomically store 64 bits is with STREXD, which will - * succeed only if paired up with a preceeding LDREXD using the same - * address, so we read and discard the existing value before storing. - */ - __asm __volatile( - "1: \n" - " ldrexd %Q[tmp], %R[tmp], [%[ptr]]\n" - " strexd %[exf], %Q[tmp], %R[tmp], [%[ptr]]\n" - " teq %[exf], #0\n" - " it ne \n" - " bne 1b\n" - : [tmp] "=&r" (tmp), - [exf] "=&r" (exflag) - : [ptr] "r" (p), - [val] "r" (val) - : "cc", "memory"); -} - -static __inline void -atomic_store_rel_64(volatile uint64_t *p, uint64_t val) -{ - - __do_dmb(); - atomic_store_64(p, val); -} - -static __inline u_long -atomic_fetchadd_long(volatile u_long *p, u_long val) -{ - u_long tmp = 0, tmp2 = 0, ret = 0; - - __asm __volatile("1: ldrex %0, [%3]\n" - "add %1, %0, %4\n" - "strex %2, %1, [%3]\n" - "cmp %2, #0\n" - "it ne\n" - "bne 1b\n" - : "+r" (ret), "=&r" (tmp), "+r" (tmp2) - ,"+r" (p), "+r" (val) : : "cc", "memory"); - return (ret); -} - -static __inline u_long -atomic_readandclear_long(volatile u_long *p) -{ - u_long ret, tmp = 0, tmp2 = 0; - - __asm __volatile("1: ldrex %0, [%3]\n" - "mov %1, #0\n" - "strex %2, %1, [%3]\n" - "cmp %2, #0\n" - "it ne\n" - "bne 1b\n" - : "=r" (ret), "=&r" (tmp), "+r" (tmp2) - ,"+r" (p) : : "cc", "memory"); - return (ret); -} - -static __inline u_long -atomic_load_acq_long(volatile u_long *p) -{ - u_long v; - - v = *p; - __do_dmb(); - return (v); -} - -static __inline void -atomic_store_rel_long(volatile u_long *p, u_long v) -{ - - __do_dmb(); - *p = v; -} +#if __ARM_ARCH >= 6 +#include #else /* < armv6 */ - -#define __with_interrupts_disabled(expr) \ - do { \ - u_int cpsr_save, tmp; \ - \ - __asm __volatile( \ - "mrs %0, cpsr;" \ - "orr %1, %0, %2;" \ - "msr cpsr_fsxc, %1;" \ - : "=r" (cpsr_save), "=r" (tmp) \ - : "I" (PSR_I | PSR_F) \ - : "cc" ); \ - (expr); \ - __asm __volatile( \ - "msr cpsr_fsxc, %0" \ - : /* no output */ \ - : "r" (cpsr_save) \ - : "cc" ); \ - } while(0) - -static __inline uint32_t -__swp(uint32_t val, volatile uint32_t *ptr) -{ - __asm __volatile("swp %0, %2, [%3]" - : "=&r" (val), "=m" (*ptr) - : "r" (val), "r" (ptr), "m" (*ptr) - : "memory"); - return (val); -} - - -#ifdef _KERNEL -#define ARM_HAVE_ATOMIC64 - -static __inline void -atomic_set_32(volatile uint32_t *address, uint32_t setmask) -{ - __with_interrupts_disabled(*address |= setmask); -} - -static __inline void -atomic_set_64(volatile uint64_t *address, uint64_t setmask) -{ - __with_interrupts_disabled(*address |= setmask); -} - -static __inline void -atomic_clear_32(volatile uint32_t *address, uint32_t clearmask) -{ - __with_interrupts_disabled(*address &= ~clearmask); -} - -static __inline void -atomic_clear_64(volatile uint64_t *address, uint64_t clearmask) -{ - __with_interrupts_disabled(*address &= ~clearmask); -} - -static __inline u_int32_t -atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval) -{ - int ret; - - __with_interrupts_disabled( - { - if (*p == cmpval) { - *p = newval; - ret = 1; - } else { - ret = 0; - } - }); - return (ret); -} - -static __inline u_int64_t -atomic_cmpset_64(volatile u_int64_t *p, volatile u_int64_t cmpval, volatile u_int64_t newval) -{ - int ret; - - __with_interrupts_disabled( - { - if (*p == cmpval) { - *p = newval; - ret = 1; - } else { - ret = 0; - } - }); - return (ret); -} - -static __inline void -atomic_add_32(volatile u_int32_t *p, u_int32_t val) -{ - __with_interrupts_disabled(*p += val); -} - -static __inline void -atomic_add_64(volatile u_int64_t *p, u_int64_t val) -{ - __with_interrupts_disabled(*p += val); -} - -static __inline void -atomic_subtract_32(volatile u_int32_t *p, u_int32_t val) -{ - __with_interrupts_disabled(*p -= val); -} - -static __inline void -atomic_subtract_64(volatile u_int64_t *p, u_int64_t val) -{ - __with_interrupts_disabled(*p -= val); -} - -static __inline uint32_t -atomic_fetchadd_32(volatile uint32_t *p, uint32_t v) -{ - uint32_t value; - - __with_interrupts_disabled( - { - value = *p; - *p += v; - }); - return (value); -} - -static __inline uint64_t -atomic_fetchadd_64(volatile uint64_t *p, uint64_t v) -{ - uint64_t value; - - __with_interrupts_disabled( - { - value = *p; - *p += v; - }); - return (value); -} - -static __inline uint64_t -atomic_load_64(volatile uint64_t *p) -{ - uint64_t value; - - __with_interrupts_disabled(value = *p); - return (value); -} - -static __inline void -atomic_store_64(volatile uint64_t *p, uint64_t value) -{ - __with_interrupts_disabled(*p = value); -} - -#else /* !_KERNEL */ - -static __inline u_int32_t -atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval) -{ - register int done, ras_start = ARM_RAS_START; - - __asm __volatile("1:\n" - "adr %1, 1b\n" - "str %1, [%0]\n" - "adr %1, 2f\n" - "str %1, [%0, #4]\n" - "ldr %1, [%2]\n" - "cmp %1, %3\n" - "streq %4, [%2]\n" - "2:\n" - "mov %1, #0\n" - "str %1, [%0]\n" - "mov %1, #0xffffffff\n" - "str %1, [%0, #4]\n" - "moveq %1, #1\n" - "movne %1, #0\n" - : "+r" (ras_start), "=r" (done) - ,"+r" (p), "+r" (cmpval), "+r" (newval) : : "cc", "memory"); - return (done); -} - -static __inline void -atomic_add_32(volatile u_int32_t *p, u_int32_t val) -{ - int start, ras_start = ARM_RAS_START; - - __asm __volatile("1:\n" - "adr %1, 1b\n" - "str %1, [%0]\n" - "adr %1, 2f\n" - "str %1, [%0, #4]\n" - "ldr %1, [%2]\n" - "add %1, %1, %3\n" - "str %1, [%2]\n" - "2:\n" - "mov %1, #0\n" - "str %1, [%0]\n" - "mov %1, #0xffffffff\n" - "str %1, [%0, #4]\n" - : "+r" (ras_start), "=r" (start), "+r" (p), "+r" (val) - : : "memory"); -} - -static __inline void -atomic_subtract_32(volatile u_int32_t *p, u_int32_t val) -{ - int start, ras_start = ARM_RAS_START; - - __asm __volatile("1:\n" - "adr %1, 1b\n" - "str %1, [%0]\n" - "adr %1, 2f\n" - "str %1, [%0, #4]\n" - "ldr %1, [%2]\n" - "sub %1, %1, %3\n" - "str %1, [%2]\n" - "2:\n" - "mov %1, #0\n" - "str %1, [%0]\n" - "mov %1, #0xffffffff\n" - "str %1, [%0, #4]\n" - - : "+r" (ras_start), "=r" (start), "+r" (p), "+r" (val) - : : "memory"); -} - -static __inline void -atomic_set_32(volatile uint32_t *address, uint32_t setmask) -{ - int start, ras_start = ARM_RAS_START; - - __asm __volatile("1:\n" - "adr %1, 1b\n" - "str %1, [%0]\n" - "adr %1, 2f\n" - "str %1, [%0, #4]\n" - "ldr %1, [%2]\n" - "orr %1, %1, %3\n" - "str %1, [%2]\n" - "2:\n" - "mov %1, #0\n" - "str %1, [%0]\n" - "mov %1, #0xffffffff\n" - "str %1, [%0, #4]\n" - - : "+r" (ras_start), "=r" (start), "+r" (address), "+r" (setmask) - : : "memory"); -} - -static __inline void -atomic_clear_32(volatile uint32_t *address, uint32_t clearmask) -{ - int start, ras_start = ARM_RAS_START; - - __asm __volatile("1:\n" - "adr %1, 1b\n" - "str %1, [%0]\n" - "adr %1, 2f\n" - "str %1, [%0, #4]\n" - "ldr %1, [%2]\n" - "bic %1, %1, %3\n" - "str %1, [%2]\n" - "2:\n" - "mov %1, #0\n" - "str %1, [%0]\n" - "mov %1, #0xffffffff\n" - "str %1, [%0, #4]\n" - : "+r" (ras_start), "=r" (start), "+r" (address), "+r" (clearmask) - : : "memory"); - -} - -static __inline uint32_t -atomic_fetchadd_32(volatile uint32_t *p, uint32_t v) -{ - uint32_t start, tmp, ras_start = ARM_RAS_START; - - __asm __volatile("1:\n" - "adr %1, 1b\n" - "str %1, [%0]\n" - "adr %1, 2f\n" - "str %1, [%0, #4]\n" - "ldr %1, [%3]\n" - "mov %2, %1\n" - "add %2, %2, %4\n" - "str %2, [%3]\n" - "2:\n" - "mov %2, #0\n" - "str %2, [%0]\n" - "mov %2, #0xffffffff\n" - "str %2, [%0, #4]\n" - : "+r" (ras_start), "=r" (start), "=r" (tmp), "+r" (p), "+r" (v) - : : "memory"); - return (start); -} - -#endif /* _KERNEL */ - - -static __inline uint32_t -atomic_readandclear_32(volatile u_int32_t *p) -{ - - return (__swp(0, p)); -} - -#define atomic_cmpset_rel_32 atomic_cmpset_32 -#define atomic_cmpset_acq_32 atomic_cmpset_32 -#define atomic_set_rel_32 atomic_set_32 -#define atomic_set_acq_32 atomic_set_32 -#define atomic_clear_rel_32 atomic_clear_32 -#define atomic_clear_acq_32 atomic_clear_32 -#define atomic_add_rel_32 atomic_add_32 -#define atomic_add_acq_32 atomic_add_32 -#define atomic_subtract_rel_32 atomic_subtract_32 -#define atomic_subtract_acq_32 atomic_subtract_32 -#define atomic_store_rel_32 atomic_store_32 -#define atomic_store_rel_long atomic_store_long -#define atomic_load_acq_32 atomic_load_32 -#define atomic_load_acq_long atomic_load_long -#define atomic_add_acq_long atomic_add_long -#define atomic_add_rel_long atomic_add_long -#define atomic_subtract_acq_long atomic_subtract_long -#define atomic_subtract_rel_long atomic_subtract_long -#define atomic_clear_acq_long atomic_clear_long -#define atomic_clear_rel_long atomic_clear_long -#define atomic_set_acq_long atomic_set_long -#define atomic_set_rel_long atomic_set_long -#define atomic_cmpset_acq_long atomic_cmpset_long -#define atomic_cmpset_rel_long atomic_cmpset_long -#define atomic_load_acq_long atomic_load_long -#undef __with_interrupts_disabled - -static __inline void -atomic_add_long(volatile u_long *p, u_long v) -{ - - atomic_add_32((volatile uint32_t *)p, v); -} - -static __inline void -atomic_clear_long(volatile u_long *p, u_long v) -{ - - atomic_clear_32((volatile uint32_t *)p, v); -} - -static __inline int -atomic_cmpset_long(volatile u_long *dst, u_long old, u_long newe) -{ - - return (atomic_cmpset_32((volatile uint32_t *)dst, old, newe)); -} - -static __inline u_long -atomic_fetchadd_long(volatile u_long *p, u_long v) -{ - - return (atomic_fetchadd_32((volatile uint32_t *)p, v)); -} - -static __inline void -atomic_readandclear_long(volatile u_long *p) -{ - - atomic_readandclear_32((volatile uint32_t *)p); -} - -static __inline void -atomic_set_long(volatile u_long *p, u_long v) -{ - - atomic_set_32((volatile uint32_t *)p, v); -} - -static __inline void -atomic_subtract_long(volatile u_long *p, u_long v) -{ - - atomic_subtract_32((volatile uint32_t *)p, v); -} - - - +#include #endif /* Arch >= v6 */ static __inline int diff --git a/sys/arm/samsung/s3c2xx0/s3c24x0_machdep.c b/sys/arm/samsung/s3c2xx0/s3c24x0_machdep.c index fa60be53ea1f..bdd6cc6f449b 100644 --- a/sys/arm/samsung/s3c2xx0/s3c24x0_machdep.c +++ b/sys/arm/samsung/s3c2xx0/s3c24x0_machdep.c @@ -44,6 +44,7 @@ */ #include "opt_ddb.h" +#include "opt_kstack_pages.h" #include __FBSDID("$FreeBSD$"); diff --git a/sys/arm/xscale/i80321/ep80219_machdep.c b/sys/arm/xscale/i80321/ep80219_machdep.c index ad9190cfe3d6..98813718ba7d 100644 --- a/sys/arm/xscale/i80321/ep80219_machdep.c +++ b/sys/arm/xscale/i80321/ep80219_machdep.c @@ -48,6 +48,8 @@ #include __FBSDID("$FreeBSD$"); +#include "opt_kstack_pages.h" + #define _ARM32_BUS_DMA_PRIVATE #include #include diff --git a/sys/arm/xscale/i80321/iq31244_machdep.c b/sys/arm/xscale/i80321/iq31244_machdep.c index 681238780674..0df3609a055a 100644 --- a/sys/arm/xscale/i80321/iq31244_machdep.c +++ b/sys/arm/xscale/i80321/iq31244_machdep.c @@ -48,6 +48,8 @@ #include __FBSDID("$FreeBSD$"); +#include "opt_kstack_pages.h" + #define _ARM32_BUS_DMA_PRIVATE #include #include diff --git a/sys/arm/xscale/i8134x/crb_machdep.c b/sys/arm/xscale/i8134x/crb_machdep.c index 1ea82eead136..568be9ff83d0 100644 --- a/sys/arm/xscale/i8134x/crb_machdep.c +++ b/sys/arm/xscale/i8134x/crb_machdep.c @@ -48,6 +48,8 @@ #include __FBSDID("$FreeBSD$"); +#include "opt_kstack_pages.h" + #define _ARM32_BUS_DMA_PRIVATE #include #include diff --git a/sys/arm/xscale/ixp425/avila_machdep.c b/sys/arm/xscale/ixp425/avila_machdep.c index cbcd0fb696da..f37aa2937a7a 100644 --- a/sys/arm/xscale/ixp425/avila_machdep.c +++ b/sys/arm/xscale/ixp425/avila_machdep.c @@ -48,6 +48,8 @@ #include __FBSDID("$FreeBSD$"); +#include "opt_kstack_pages.h" + #define _ARM32_BUS_DMA_PRIVATE #include #include diff --git a/sys/arm/xscale/pxa/pxa_machdep.c b/sys/arm/xscale/pxa/pxa_machdep.c index 51b1efc59b50..4480c954c52b 100644 --- a/sys/arm/xscale/pxa/pxa_machdep.c +++ b/sys/arm/xscale/pxa/pxa_machdep.c @@ -46,6 +46,7 @@ */ #include "opt_ddb.h" +#include "opt_kstack_pages.h" #include __FBSDID("$FreeBSD$"); diff --git a/sys/arm64/acpica/pci_cfgreg.c b/sys/arm64/acpica/pci_cfgreg.c new file mode 100644 index 000000000000..e80803fbaa4a --- /dev/null +++ b/sys/arm64/acpica/pci_cfgreg.c @@ -0,0 +1,76 @@ +/*- + * Copyright (c) 2015 The FreeBSD Foundation + * All rights reserved. + * + * This software was developed by Semihalf under + * the sponsorship of the FreeBSD Foundation. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include + +#include + +/* + * This file contains stubs for ACPI PCI functions + */ + +/* + * Read configuration space register + */ +uint32_t +pci_cfgregread(int bus, int slot, int func, int reg, int bytes) +{ + + /* ARM64TODO */ + panic("pci_cfgregread not implemented"); + return (0); +} + +/* + * Write configuration space register + */ +void +pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes) +{ + + /* ARM64TODO */ + panic("pci_cfgregwrite not implemented"); +} + +/* + * Initialize access to configuration space + */ +int +pci_cfgregopen(void) +{ + + /* ARM64TODO */ + panic("pci_cfgregopen not implemented"); + return (0); +} diff --git a/sys/arm64/arm64/cpufunc_asm.S b/sys/arm64/arm64/cpufunc_asm.S index 9b17c21ea31c..49cd6f168379 100644 --- a/sys/arm64/arm64/cpufunc_asm.S +++ b/sys/arm64/arm64/cpufunc_asm.S @@ -61,17 +61,18 @@ __FBSDID("$FreeBSD$"); add x1, x1, x2 /* Add these to the size */ bic x0, x0, x4 /* Clear the low bit of the address */ 1: + dc \dcop, x0 + dsb ish .if \ic != 0 ic \icop, x0 + dsb ish .endif - dc \dcop, x0 add x0, x0, x3 /* Move to the next line */ subs x1, x1, x3 /* Reduce the size */ b.hi 1b /* Check if we are done */ .if \ic != 0 isb .endif - dsb ish ret .endm diff --git a/sys/arm64/arm64/gic_fdt.c b/sys/arm64/arm64/gic_fdt.c index 5b70624d7362..6c9338ad85b7 100644 --- a/sys/arm64/arm64/gic_fdt.c +++ b/sys/arm64/arm64/gic_fdt.c @@ -52,6 +52,7 @@ static struct ofw_compat_data compat_data[] = { {"arm,cortex-a7-gic", true}, {"arm,arm11mp-gic", true}, {"brcm,brahma-b15-gic", true}, + {"qcom,msm-qgic2", true}, {NULL, false} }; diff --git a/sys/arm64/arm64/gic_v3_its.c b/sys/arm64/arm64/gic_v3_its.c index 0a0b06b7ee1a..274a6aa2c230 100644 --- a/sys/arm64/arm64/gic_v3_its.c +++ b/sys/arm64/arm64/gic_v3_its.c @@ -44,6 +44,7 @@ __FBSDID("$FreeBSD$"); #include #include +#include #include #include @@ -89,6 +90,7 @@ static void its_free_tables(struct gic_v3_its_softc *); static void its_init_commandq(struct gic_v3_its_softc *); static int its_init_cpu(struct gic_v3_its_softc *); static void its_init_cpu_collection(struct gic_v3_its_softc *); +static uint32_t its_get_devid(device_t); static int its_cmd_send(struct gic_v3_its_softc *, struct its_cmd_desc *); @@ -133,6 +135,23 @@ const char *its_ptab_type[] = { [GITS_BASER_TYPE_RES7] = "Reserved (7)", }; +/* + * Vendor specific quirks. + * One needs to add appropriate entry to its_quirks[] + * table if the imlementation varies from the generic ARM ITS. + */ + +/* Cavium ThunderX PCI devid acquire function */ +static uint32_t its_get_devid_thunder(device_t); + +static const struct its_quirks its_quirks[] = { + { + .cpuid = CPU_ID_RAW(CPU_IMPL_CAVIUM, CPU_PART_THUNDER, 0, 0), + .cpuid_mask = CPU_IMPL_MASK | CPU_PART_MASK, + .devid_func = its_get_devid_thunder, + }, +}; + static struct gic_v3_its_softc *its_sc; #define gic_its_read(sc, len, reg) \ @@ -794,6 +813,26 @@ retry: return (0); } +static void +lpi_free_chunk(struct gic_v3_its_softc *sc, struct lpi_chunk *lpic) +{ + int start, end; + uint8_t *bitmap; + + bitmap = (uint8_t *)sc->its_lpi_bitmap; + + KASSERT((lpic->lpi_free == lpic->lpi_num), + ("Trying to free LPI chunk that is still in use.\n")); + + /* First bit of this chunk in a global bitmap */ + start = lpic->lpi_base - GIC_FIRST_LPI; + /* and last bit of this chunk... */ + end = start + lpic->lpi_num - 1; + + /* Finally free this chunk */ + bit_nclear(bitmap, start, end); +} + static void lpi_configure(struct gic_v3_its_softc *sc, struct its_dev *its_dev, uint32_t lpinum, boolean_t unmask) @@ -1300,10 +1339,13 @@ its_device_alloc_locked(struct gic_v3_its_softc *sc, device_t pci_dev, if (newdev != NULL) return (newdev); - devid = PCI_DEVID(pci_dev); + devid = its_get_devid(pci_dev); /* There was no previously created device. Create one now */ - newdev = malloc(sizeof(*newdev), M_GIC_V3_ITS, (M_WAITOK | M_ZERO)); + newdev = malloc(sizeof(*newdev), M_GIC_V3_ITS, (M_NOWAIT | M_ZERO)); + if (newdev == NULL) + return (NULL); + newdev->pci_dev = pci_dev; newdev->devid = devid; @@ -1321,7 +1363,12 @@ its_device_alloc_locked(struct gic_v3_its_softc *sc, device_t pci_dev, */ newdev->itt = (vm_offset_t)contigmalloc( roundup2(roundup2(nvecs, 2) * esize, 0x100), M_GIC_V3_ITS, - (M_WAITOK | M_ZERO), 0, ~0UL, 0x100, 0); + (M_NOWAIT | M_ZERO), 0, ~0UL, 0x100, 0); + if (newdev->itt == 0) { + lpi_free_chunk(sc, &newdev->lpis); + free(newdev, M_GIC_V3_ITS); + return (NULL); + } /* * XXX ARM64TODO: Currently all interrupts are going @@ -1353,6 +1400,77 @@ its_device_asign_lpi_locked(struct gic_v3_its_softc *sc, its_dev->lpis.lpi_free); its_dev->lpis.lpi_free--; } + +/* + * ITS quirks. + * Add vendor specific PCI devid function here. + */ +static uint32_t +its_get_devid_thunder(device_t pci_dev) +{ + int bsf; + int pem; + uint32_t bus; + + bus = pci_get_bus(pci_dev); + + bsf = PCI_RID(pci_get_bus(pci_dev), pci_get_slot(pci_dev), + pci_get_function(pci_dev)); + + /* ECAM is on bus=0 */ + if (bus == 0) { + return ((pci_get_domain(pci_dev) << PCI_RID_DOMAIN_SHIFT) | + bsf); + /* PEM otherwise */ + } else { + /* PEM (PCIe MAC/root complex) number is equal to domain */ + pem = pci_get_domain(pci_dev); + + /* + * Set appropriate device ID (passed by the HW along with + * the transaction to memory) for different root complex + * numbers using hard-coded domain portion for each group. + */ + if (pem < 3) + return ((0x1 << PCI_RID_DOMAIN_SHIFT) | bsf); + + if (pem < 6) + return ((0x3 << PCI_RID_DOMAIN_SHIFT) | bsf); + + if (pem < 9) + return ((0x9 << PCI_RID_DOMAIN_SHIFT) | bsf); + + if (pem < 12) + return ((0xB << PCI_RID_DOMAIN_SHIFT) | bsf); + } + + return (0); +} + +static __inline uint32_t +its_get_devid_default(device_t pci_dev) +{ + + return (PCI_DEVID_GENERIC(pci_dev)); +} + +static uint32_t +its_get_devid(device_t pci_dev) +{ + const struct its_quirks *quirk; + size_t i; + + for (i = 0; i < nitems(its_quirks); i++) { + quirk = &its_quirks[i]; + if (CPU_MATCH_RAW(quirk->cpuid_mask, quirk->cpuid)) { + if (quirk->devid_func != NULL) + return ((*quirk->devid_func)(pci_dev)); + } + } + + return (its_get_devid_default(pci_dev)); +} + /* * Message signalled interrupts handling. */ diff --git a/sys/arm64/arm64/gic_v3_var.h b/sys/arm64/arm64/gic_v3_var.h index 486e93808c1b..1621c0cfdffe 100644 --- a/sys/arm64/arm64/gic_v3_var.h +++ b/sys/arm64/arm64/gic_v3_var.h @@ -234,6 +234,15 @@ struct gic_v3_its_softc { struct mtx its_spin_mtx; }; +/* Stuff that is specific to the vendor's implementation */ +typedef uint32_t (*its_devid_func_t)(device_t); + +struct its_quirks { + uint64_t cpuid; + uint64_t cpuid_mask; + its_devid_func_t devid_func; +}; + extern devclass_t gic_v3_its_devclass; int gic_v3_its_detach(device_t); @@ -277,13 +286,12 @@ void lpi_mask_irq(device_t, uint32_t); reg, val); \ }) -#define PCI_DEVID(pci_dev) \ -({ \ - (((pci_get_domain(pci_dev) >> 2) << 19) | \ - ((pci_get_domain(pci_dev) % 4) << 16) | \ - (pci_get_bus(pci_dev) << 8) | \ - (pci_get_slot(pci_dev) << 3) | \ - (pci_get_function(pci_dev) << 0)); \ +#define PCI_DEVID_GENERIC(pci_dev) \ +({ \ + ((pci_get_domain(pci_dev) << PCI_RID_DOMAIN_SHIFT) | \ + (pci_get_bus(pci_dev) << PCI_RID_BUS_SHIFT) | \ + (pci_get_slot(pci_dev) << PCI_RID_SLOT_SHIFT) | \ + (pci_get_function(pci_dev) << PCI_RID_FUNC_SHIFT)); \ }) /* diff --git a/sys/arm64/arm64/intr_machdep.c b/sys/arm64/arm64/intr_machdep.c index 4a69187bfe95..7c383ee606fc 100644 --- a/sys/arm64/arm64/intr_machdep.c +++ b/sys/arm64/arm64/intr_machdep.c @@ -451,8 +451,7 @@ void arm_setup_ipihandler(driver_filter_t *filt, u_int ipi) { - /* ARM64TODO: The hard coded 16 will be fixed with am_intrng */ - arm_setup_intr("ipi", filt, NULL, (void *)((uintptr_t)ipi | 1<<16), ipi + 16, + arm_setup_intr("ipi", filt, NULL, (void *)((uintptr_t)ipi | 1<<16), ipi, INTR_TYPE_MISC | INTR_EXCL, NULL); arm_unmask_ipi(ipi); } @@ -460,7 +459,8 @@ arm_setup_ipihandler(driver_filter_t *filt, u_int ipi) void arm_unmask_ipi(u_int ipi) { - PIC_UNMASK(root_pic, ipi + 16); + + PIC_UNMASK(root_pic, ipi); } void @@ -494,9 +494,6 @@ ipi_cpu(int cpu, u_int ipi) CPU_ZERO(&cpus); CPU_SET(cpu, &cpus); - /* ARM64TODO: This will be fixed with arm_intrng */ - ipi += 16; - CTR2(KTR_SMP, "ipi_cpu: cpu: %d, ipi: %x", cpu, ipi); PIC_IPI_SEND(root_pic, cpus, ipi); } @@ -505,9 +502,6 @@ void ipi_selected(cpuset_t cpus, u_int ipi) { - /* ARM64TODO: This will be fixed with arm_intrng */ - ipi += 16; - CTR1(KTR_SMP, "ipi_selected: ipi: %x", ipi); PIC_IPI_SEND(root_pic, cpus, ipi); } diff --git a/sys/arm64/arm64/locore.S b/sys/arm64/arm64/locore.S index be7f0c710d6c..f7d7fe946e48 100644 --- a/sys/arm64/arm64/locore.S +++ b/sys/arm64/arm64/locore.S @@ -27,6 +27,7 @@ */ #include "assym.s" +#include "opt_kstack_pages.h" #include #include #include @@ -51,8 +52,6 @@ * We are loaded at a 2MiB aligned address */ -#define INIT_STACK_SIZE (PAGE_SIZE * 4) - .text .globl _start _start: @@ -180,8 +179,7 @@ ENTRY(mpentry) mp_virtdone: ldr x4, =secondary_stacks mov x5, #(PAGE_SIZE * KSTACK_PAGES) - sub x1, x0, #1 - mul x5, x1, x5 + mul x5, x0, x5 add sp, x4, x5 b init_secondary @@ -469,6 +467,9 @@ build_block_pagetable: lsl x12, x7, #2 orr x12, x12, #L2_BLOCK orr x12, x12, #(ATTR_AF) +#ifdef SMP + orr x12, x12, ATTR_SH(ATTR_SH_IS) +#endif /* Only use the output address bits */ lsr x9, x9, #L2_SHIFT @@ -532,7 +533,8 @@ mair: /* Device Normal, no cache Normal, write-back */ .quad MAIR_ATTR(0x00, 0) | MAIR_ATTR(0x44, 1) | MAIR_ATTR(0xff, 2) tcr: - .quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_ASID_16 | TCR_TG1_4K) + .quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_ASID_16 | TCR_TG1_4K | \ + TCR_CACHE_ATTRS | TCR_SMP_ATTRS) sctlr_set: /* Bits to set */ .quad (SCTLR_UCI | SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \ diff --git a/sys/arm64/arm64/mp_machdep.c b/sys/arm64/arm64/mp_machdep.c index 15aa290bdad4..469627e550d4 100644 --- a/sys/arm64/arm64/mp_machdep.c +++ b/sys/arm64/arm64/mp_machdep.c @@ -28,6 +28,7 @@ * */ +#include "opt_kstack_pages.h" #include "opt_platform.h" #include @@ -229,6 +230,16 @@ init_secondary(uint64_t cpu) pcpup->pc_curthread = pcpup->pc_idlethread; pcpup->pc_curpcb = pcpup->pc_idlethread->td_pcb; + /* + * Identify current CPU. This is necessary to setup + * affinity registers and to provide support for + * runtime chip identification. + */ + identify_cpu(); + + /* Configure the interrupt controller */ + arm_init_secondary(); + for (i = 0; i < COUNT_IPI; i++) arm_unmask_ipi(i); @@ -239,9 +250,6 @@ init_secondary(uint64_t cpu) vfp_init(); #endif - /* Configure the interrupt controller */ - arm_init_secondary(); - /* Enable interrupts */ intr_enable(); diff --git a/sys/arm64/arm64/pmap.c b/sys/arm64/arm64/pmap.c index 41c32346a04d..7e4182052bd6 100644 --- a/sys/arm64/arm64/pmap.c +++ b/sys/arm64/arm64/pmap.c @@ -428,8 +428,8 @@ pmap_bootstrap_dmap(vm_offset_t l1pt) KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index")); pmap_load_store(&l1[l1_slot], - (pa & ~L1_OFFSET) | ATTR_AF | L1_BLOCK | - ATTR_IDX(CACHED_MEMORY)); + (pa & ~L1_OFFSET) | ATTR_DEFAULT | + ATTR_IDX(CACHED_MEMORY) | L1_BLOCK); } cpu_dcache_wb_range((vm_offset_t)l1, PAGE_SIZE); @@ -860,8 +860,8 @@ pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa) while (size != 0) { l3 = pmap_l3(kernel_pmap, va); KASSERT(l3 != NULL, ("Invalid page table, va: 0x%lx", va)); - pmap_load_store(l3, (pa & ~L3_OFFSET) | ATTR_AF | L3_PAGE | - ATTR_IDX(DEVICE_MEMORY)); + pmap_load_store(l3, (pa & ~L3_OFFSET) | ATTR_DEFAULT | + ATTR_IDX(DEVICE_MEMORY) | L3_PAGE); PTE_SYNC(l3); va += PAGE_SIZE; @@ -953,8 +953,8 @@ pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) va = sva; for (i = 0; i < count; i++) { m = ma[i]; - pa = VM_PAGE_TO_PHYS(m) | ATTR_AF | - ATTR_IDX(m->md.pv_memattr) | ATTR_AP(ATTR_AP_RW) | L3_PAGE; + pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_AP(ATTR_AP_RW) | + ATTR_IDX(m->md.pv_memattr) | L3_PAGE; l3 = pmap_l3(kernel_pmap, va); pmap_load_store(l3, pa); PTE_SYNC(l3); @@ -1214,8 +1214,7 @@ _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp) l2 = (pd_entry_t *)PHYS_TO_DMAP(*l1 & ~ATTR_MASK); l2 = &l2[ptepindex & Ln_ADDR_MASK]; - pmap_load_store(l2, VM_PAGE_TO_PHYS(m) | ATTR_AF | - ATTR_IDX(CACHED_MEMORY) | L2_TABLE); + pmap_load_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE); PTE_SYNC(l2); } @@ -1907,14 +1906,14 @@ pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) VM_OBJECT_ASSERT_LOCKED(m->object); pa = VM_PAGE_TO_PHYS(m); - new_l3 = (pt_entry_t)(pa | ATTR_AF | L3_PAGE); + new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) | + L3_PAGE); if ((prot & VM_PROT_WRITE) == 0) new_l3 |= ATTR_AP(ATTR_AP_RO); if ((flags & PMAP_ENTER_WIRED) != 0) new_l3 |= ATTR_SW_WIRED; if ((va >> 63) == 0) new_l3 |= ATTR_AP(ATTR_AP_USER); - new_l3 |= ATTR_IDX(m->md.pv_memattr); CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa); @@ -2243,7 +2242,7 @@ pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, */ pmap_resident_count_inc(pmap, 1); - pa = VM_PAGE_TO_PHYS(m) | ATTR_AF | ATTR_IDX(m->md.pv_memattr) | + pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) | ATTR_AP(ATTR_AP_RW) | L3_PAGE; /* diff --git a/sys/arm64/arm64/swtch.S b/sys/arm64/arm64/swtch.S index 6774e767e7ae..a987134bc3b3 100644 --- a/sys/arm64/arm64/swtch.S +++ b/sys/arm64/arm64/swtch.S @@ -30,6 +30,7 @@ */ #include "assym.s" +#include "opt_kstack_pages.h" #include "opt_sched.h" #include diff --git a/sys/arm64/conf/GENERIC b/sys/arm64/conf/GENERIC index 1bd12b88cfd1..c4ef49d180b3 100644 --- a/sys/arm64/conf/GENERIC +++ b/sys/arm64/conf/GENERIC @@ -112,5 +112,5 @@ device bpf # Berkeley packet filter options FDT device acpi -# The cypto framework is required by IPSEC +# The crypto framework is required by IPSEC device crypto # Required by IPSEC diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index ab1de97feee0..55bf46530c5f 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -200,6 +200,28 @@ #define TCR_TG1_4K (2 << TCR_TG1_SHIFT) #define TCR_TG1_64K (3 << TCR_TG1_SHIFT) +#define TCR_SH1_SHIFT 28 +#define TCR_SH1_IS (0x3UL << TCR_SH1_SHIFT) +#define TCR_ORGN1_SHIFT 26 +#define TCR_ORGN1_WBWA (0x1UL << TCR_ORGN1_SHIFT) +#define TCR_IRGN1_SHIFT 24 +#define TCR_IRGN1_WBWA (0x1UL << TCR_IRGN1_SHIFT) +#define TCR_SH0_SHIFT 12 +#define TCR_SH0_IS (0x3UL << TCR_SH0_SHIFT) +#define TCR_ORGN0_SHIFT 10 +#define TCR_ORGN0_WBWA (0x1UL << TCR_ORGN0_SHIFT) +#define TCR_IRGN0_SHIFT 8 +#define TCR_IRGN0_WBWA (0x1UL << TCR_IRGN0_SHIFT) + +#define TCR_CACHE_ATTRS ((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\ + (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)) + +#ifdef SMP +#define TCR_SMP_ATTRS (TCR_SH0_IS | TCR_SH1_IS) +#else +#define TCR_SMP_ATTRS 0 +#endif + #define TCR_T1SZ_SHIFT 16 #define TCR_T0SZ_SHIFT 0 #define TCR_TxSZ(x) (((x) << TCR_T1SZ_SHIFT) | ((x) << TCR_T0SZ_SHIFT)) diff --git a/sys/arm64/include/cpu.h b/sys/arm64/include/cpu.h index b805ddd69b88..15cdd80d4e26 100644 --- a/sys/arm64/include/cpu.h +++ b/sys/arm64/include/cpu.h @@ -43,6 +43,7 @@ #include #include +#include #define TRAPF_PC(tfp) ((tfp)->tf_lr) #define TRAPF_USERMODE(tfp) (((tfp)->tf_elr & (1ul << 63)) == 0) @@ -92,10 +93,17 @@ #define CPU_VAR_MASK (0xf << 20) #define CPU_REV_MASK (0xf << 0) -#define CPU_MATCH(mask, impl, part, var, rev) \ - (((mask) & PCPU_GET(midr)) == (CPU_IMPL_TO_MIDR((impl)) | \ - CPU_PART_TO_MIDR((part)) | CPU_VAR_TO_MIDR((var)) | \ - CPU_REV_TO_MIDR((rev)))) +#define CPU_ID_RAW(impl, part, var, rev) \ + (CPU_IMPL_TO_MIDR((impl)) | \ + CPU_PART_TO_MIDR((part)) | CPU_VAR_TO_MIDR((var)) | \ + CPU_REV_TO_MIDR((rev))) + +#define CPU_MATCH(mask, impl, part, var, rev) \ + (((mask) & PCPU_GET(midr)) == \ + ((mask) & CPU_ID_RAW((impl), (part), (var), (rev)))) + +#define CPU_MATCH_RAW(mask, devid) \ + (((mask) & PCPU_GET(midr)) == ((mask) & (devid))) extern char btext[]; extern char etext[]; @@ -113,9 +121,11 @@ void swi_vm(void *v); static __inline uint64_t get_cyclecount(void) { + uint64_t ret; - /* TODO: This is bogus */ - return (1); + ret = READ_SPECIALREG(cntvct_el0); + + return (ret); } #define ADDRESS_TRANSLATE_FUNC(stage) \ diff --git a/sys/arm64/include/pci_cfgreg.h b/sys/arm64/include/pci_cfgreg.h index da23dbe43a4f..68b38aaeb5bb 100644 --- a/sys/arm64/include/pci_cfgreg.h +++ b/sys/arm64/include/pci_cfgreg.h @@ -1 +1,36 @@ -/* $FreeBSD$ */ +/*- + * Copyright (c) 2015 The FreeBSD Foundation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_PCI_CFGREG_H +#define _MACHINE_PCI_CFGREG_H + +int pci_cfgregopen(void); +uint32_t pci_cfgregread(int, int, int, int, int); +void pci_cfgregwrite(int, int, int, int, u_int32_t, int); + +#endif /* !_MACHINE_PCI_CFGREG_H */ diff --git a/sys/arm64/include/pte.h b/sys/arm64/include/pte.h index 2b694a6d9068..645cf3154226 100644 --- a/sys/arm64/include/pte.h +++ b/sys/arm64/include/pte.h @@ -63,6 +63,12 @@ typedef uint64_t pt_entry_t; /* page table entry */ #define ATTR_IDX(x) ((x) << 2) #define ATTR_IDX_MASK (7 << 2) +#ifdef SMP +#define ATTR_DEFAULT (ATTR_AF | ATTR_SH(ATTR_SH_IS)) +#else +#define ATTR_DEFAULT (ATTR_AF) +#endif + #define ATTR_DESCR_MASK 3 /* Level 0 table, 512GiB per entry */ diff --git a/sys/arm64/include/vmparam.h b/sys/arm64/include/vmparam.h index 9a2d6e544596..8ad602994e48 100644 --- a/sys/arm64/include/vmparam.h +++ b/sys/arm64/include/vmparam.h @@ -156,9 +156,9 @@ #define VM_MIN_KERNEL_ADDRESS (0xffffff8000000000UL) #define VM_MAX_KERNEL_ADDRESS (0xffffff8800000000UL) -/* Direct Map for 64 GiB of PA: 0x0 - 0xfffffffff */ +/* Direct Map for 128 GiB of PA: 0x0 - 0x1fffffffff */ #define DMAP_MIN_ADDRESS (0xffffffc000000000UL) -#define DMAP_MAX_ADDRESS (0xffffffcfffffffffUL) +#define DMAP_MAX_ADDRESS (0xffffffdfffffffffUL) #define DMAP_MIN_PHYSADDR (0x0000000000000000UL) #define DMAP_MAX_PHYSADDR (DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) diff --git a/sys/boot/arm/ixp425/boot2/arm_init.S b/sys/boot/arm/ixp425/boot2/arm_init.S index 9ede9fc605fd..15e1e6c87ed8 100644 --- a/sys/boot/arm/ixp425/boot2/arm_init.S +++ b/sys/boot/arm/ixp425/boot2/arm_init.S @@ -43,6 +43,7 @@ ASENTRY_NP(start) /* main should not return. If it does, spin forever */ infiniteLoop: b infiniteLoop +END(start) .Lstart: .word _edata @@ -52,5 +53,6 @@ infiniteLoop: ENTRY(cpu_id) mrc p15, 0, r0, c0, c0, 0 RET +END(cpu_id) /* End */ diff --git a/sys/boot/arm/ixp425/boot2/ixp425_board.c b/sys/boot/arm/ixp425/boot2/ixp425_board.c index d2bf81398e9a..c13f8ed52694 100644 --- a/sys/boot/arm/ixp425/boot2/ixp425_board.c +++ b/sys/boot/arm/ixp425/boot2/ixp425_board.c @@ -74,7 +74,7 @@ board_init(void) { struct board_config **pbp; - cputype = cpu_ident() & CPU_ID_CPU_MASK; + cputype = cpu_id() & CPU_ID_CPU_MASK; SET_FOREACH(pbp, boards) /* XXX pass down redboot board type */ diff --git a/sys/boot/arm/ixp425/boot2/lib.h b/sys/boot/arm/ixp425/boot2/lib.h index 1679e961ce2c..9c88030c2503 100644 --- a/sys/boot/arm/ixp425/boot2/lib.h +++ b/sys/boot/arm/ixp425/boot2/lib.h @@ -30,6 +30,8 @@ #include #include +int main(void); + void DELAY(int); int getc(int); diff --git a/sys/cam/ctl/ctl_backend_block.c b/sys/cam/ctl/ctl_backend_block.c index c56023bf787e..8ea52aa323df 100644 --- a/sys/cam/ctl/ctl_backend_block.c +++ b/sys/cam/ctl/ctl_backend_block.c @@ -2123,18 +2123,7 @@ ctl_be_block_open(struct ctl_be_block_softc *softc, return (1); } - if (!curthread->td_proc->p_fd->fd_cdir) { - curthread->td_proc->p_fd->fd_cdir = rootvnode; - VREF(rootvnode); - } - if (!curthread->td_proc->p_fd->fd_rdir) { - curthread->td_proc->p_fd->fd_rdir = rootvnode; - VREF(rootvnode); - } - if (!curthread->td_proc->p_fd->fd_jdir) { - curthread->td_proc->p_fd->fd_jdir = rootvnode; - VREF(rootvnode); - } + pwd_ensure_dirs(); again: NDINIT(&nd, LOOKUP, FOLLOW, UIO_SYSSPACE, be_lun->dev_path, curthread); diff --git a/sys/cddl/compat/opensolaris/kern/opensolaris_kobj.c b/sys/cddl/compat/opensolaris/kern/opensolaris_kobj.c index 9ff798a15b7b..52d695b4f5ae 100644 --- a/sys/cddl/compat/opensolaris/kern/opensolaris_kobj.c +++ b/sys/cddl/compat/opensolaris/kern/opensolaris_kobj.c @@ -67,21 +67,10 @@ static void * kobj_open_file_vnode(const char *file) { struct thread *td = curthread; - struct filedesc *fd; struct nameidata nd; int error, flags; - fd = td->td_proc->p_fd; - FILEDESC_XLOCK(fd); - if (fd->fd_rdir == NULL) { - fd->fd_rdir = rootvnode; - vref(fd->fd_rdir); - } - if (fd->fd_cdir == NULL) { - fd->fd_cdir = rootvnode; - vref(fd->fd_cdir); - } - FILEDESC_XUNLOCK(fd); + pwd_ensure_dirs(); flags = FREAD | O_NOFOLLOW; NDINIT(&nd, LOOKUP, 0, UIO_SYSSPACE, file, td); diff --git a/sys/cddl/compat/opensolaris/sys/proc.h b/sys/cddl/compat/opensolaris/sys/proc.h index 9f26f61adf42..1fe2e9ab342f 100644 --- a/sys/cddl/compat/opensolaris/sys/proc.h +++ b/sys/cddl/compat/opensolaris/sys/proc.h @@ -63,7 +63,7 @@ typedef struct proc proc_t; extern struct proc *zfsproc; static __inline kthread_t * -thread_create(caddr_t stk, size_t stksize, void (*proc)(void *), void *arg, +do_thread_create(caddr_t stk, size_t stksize, void (*proc)(void *), void *arg, size_t len, proc_t *pp, int state, pri_t pri) { kthread_t *td = NULL; @@ -88,6 +88,8 @@ thread_create(caddr_t stk, size_t stksize, void (*proc)(void *), void *arg, return (td); } +#define thread_create(stk, stksize, proc, arg, len, pp, state, pri) \ + do_thread_create(stk, stksize, proc, arg, len, pp, state, pri) #define thread_exit() kthread_exit() #endif /* _KERNEL */ diff --git a/sys/cddl/compat/opensolaris/sys/vnode.h b/sys/cddl/compat/opensolaris/sys/vnode.h index 22256cf1f1e5..d7bc7f7a1b24 100644 --- a/sys/cddl/compat/opensolaris/sys/vnode.h +++ b/sys/cddl/compat/opensolaris/sys/vnode.h @@ -162,7 +162,6 @@ vn_openat(char *pnamep, enum uio_seg seg, int filemode, int createmode, int fd) { struct thread *td = curthread; - struct filedesc *fdc; struct nameidata nd; int error, operation; @@ -179,17 +178,7 @@ vn_openat(char *pnamep, enum uio_seg seg, int filemode, int createmode, } ASSERT(umask == 0); - fdc = td->td_proc->p_fd; - FILEDESC_XLOCK(fdc); - if (fdc->fd_rdir == NULL) { - fdc->fd_rdir = rootvnode; - vref(fdc->fd_rdir); - } - if (fdc->fd_cdir == NULL) { - fdc->fd_cdir = rootvnode; - vref(fdc->fd_rdir); - } - FILEDESC_XUNLOCK(fdc); + pwd_ensure_dirs(); if (startvp != NULL) vref(startvp); diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/vnode.c b/sys/cddl/contrib/opensolaris/uts/common/fs/vnode.c index 83f29c154de9..b587ebd45196 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/vnode.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/vnode.c @@ -99,6 +99,6 @@ vn_rele_async(vnode_t *vp, taskq_t *taskq) (task_func_t *)vn_rele_inactive, vp, TQ_SLEEP) != 0); return; } - vp->v_usecount--; + refcount_release(&vp->v_usecount); vdropl(vp); } diff --git a/sys/cddl/dev/dtrace/amd64/dtrace_isa.c b/sys/cddl/dev/dtrace/amd64/dtrace_isa.c index 336befca218d..07a1b0a7ae8a 100644 --- a/sys/cddl/dev/dtrace/amd64/dtrace_isa.c +++ b/sys/cddl/dev/dtrace/amd64/dtrace_isa.c @@ -89,8 +89,8 @@ dtrace_getpcstack(pc_t *pcstack, int pcstack_limit, int aframes, } if (frame->f_frame <= frame || - (vm_offset_t)frame->f_frame >= - (vm_offset_t)rbp + KSTACK_PAGES * PAGE_SIZE) + (vm_offset_t)frame->f_frame >= curthread->td_kstack + + curthread->td_kstack_pages * PAGE_SIZE) break; frame = frame->f_frame; } @@ -469,8 +469,8 @@ dtrace_getstackdepth(int aframes) break; depth++; if (frame->f_frame <= frame || - (vm_offset_t)frame->f_frame >= - (vm_offset_t)rbp + KSTACK_PAGES * PAGE_SIZE) + (vm_offset_t)frame->f_frame >= curthread->td_kstack + + curthread->td_kstack_pages * PAGE_SIZE) break; frame = frame->f_frame; } diff --git a/sys/cddl/dev/dtrace/i386/dtrace_isa.c b/sys/cddl/dev/dtrace/i386/dtrace_isa.c index 04f205c5551f..63a7c085d261 100644 --- a/sys/cddl/dev/dtrace/i386/dtrace_isa.c +++ b/sys/cddl/dev/dtrace/i386/dtrace_isa.c @@ -92,8 +92,8 @@ dtrace_getpcstack(pc_t *pcstack, int pcstack_limit, int aframes, } if (frame->f_frame <= frame || - (vm_offset_t)frame->f_frame >= - (vm_offset_t)ebp + KSTACK_PAGES * PAGE_SIZE) + (vm_offset_t)frame->f_frame >= curthread->td_kstack + + curthread->td_kstack_pages * PAGE_SIZE) break; frame = frame->f_frame; } @@ -485,8 +485,8 @@ dtrace_getstackdepth(int aframes) break; depth++; if (frame->f_frame <= frame || - (vm_offset_t)frame->f_frame >= - (vm_offset_t)ebp + KSTACK_PAGES * PAGE_SIZE) + (vm_offset_t)frame->f_frame >= curthread->td_kstack + + curthread->td_kstack_pages * PAGE_SIZE) break; frame = frame->f_frame; } diff --git a/sys/cddl/dev/fbt/fbt.c b/sys/cddl/dev/fbt/fbt.c index 00ab7cf3264a..19018f987050 100644 --- a/sys/cddl/dev/fbt/fbt.c +++ b/sys/cddl/dev/fbt/fbt.c @@ -334,9 +334,7 @@ fbt_ctfoff_init(modctl_t *lf, linker_ctf_t *lc) return (EINVAL); } - if ((ctfoff = malloc(sizeof(uint32_t) * lc->nsym, M_LINKER, M_WAITOK)) == NULL) - return (ENOMEM); - + ctfoff = malloc(sizeof(uint32_t) * lc->nsym, M_LINKER, M_WAITOK); *lc->ctfoffp = ctfoff; for (i = 0; i < lc->nsym; i++, ctfoff++, symp++) { @@ -515,8 +513,8 @@ fbt_typoff_init(linker_ctf_t *lc) ctf_typemax++; *lc->typlenp = ctf_typemax; - if ((xp = malloc(sizeof(uint32_t) * ctf_typemax, M_LINKER, M_ZERO | M_WAITOK)) == NULL) - return (ENOMEM); + xp = malloc(sizeof(uint32_t) * ctf_typemax, M_LINKER, + M_ZERO | M_WAITOK); *lc->typoffp = xp; @@ -838,11 +836,7 @@ ctf_decl_push(ctf_decl_t *cd, linker_ctf_t *lc, ctf_id_t type) prec = CTF_PREC_BASE; } - if ((cdp = malloc(sizeof (ctf_decl_node_t), M_FBT, M_WAITOK)) == NULL) { - cd->cd_err = EAGAIN; - return; - } - + cdp = malloc(sizeof(*cdp), M_FBT, M_WAITOK); cdp->cd_type = type; cdp->cd_kind = kind; cdp->cd_n = n; diff --git a/sys/cddl/dev/lockstat/lockstat.c b/sys/cddl/dev/lockstat/lockstat.c deleted file mode 100644 index 71a863219b1d..000000000000 --- a/sys/cddl/dev/lockstat/lockstat.c +++ /dev/null @@ -1,326 +0,0 @@ -/* - * CDDL HEADER START - * - * The contents of this file are subject to the terms of the - * Common Development and Distribution License (the "License"). - * You may not use this file except in compliance with the License. - * - * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE - * or http://www.opensolaris.org/os/licensing. - * See the License for the specific language governing permissions - * and limitations under the License. - * - * When distributing Covered Code, include this CDDL HEADER in each - * file and include the License file at usr/src/OPENSOLARIS.LICENSE. - * If applicable, add the following below this CDDL HEADER, with the - * fields enclosed by brackets "[]" replaced with your own identifying - * information: Portions Copyright [yyyy] [name of copyright owner] - * - * CDDL HEADER END - * - * Portions Copyright (c) 2008-2009 Stacey Son - * - * $FreeBSD$ - * - */ - -/* - * Copyright 2006 Sun Microsystems, Inc. All rights reserved. - * Use is subject to license terms. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#if defined(__aarch64__) || defined(__amd64__) || defined(__arm__) || \ - defined(__i386__) || defined(__mips__) || defined(__powerpc__) -#define LOCKSTAT_AFRAMES 1 -#else -#error "architecture not supported" -#endif - -static d_open_t lockstat_open; -static void lockstat_provide(void *, dtrace_probedesc_t *); -static void lockstat_destroy(void *, dtrace_id_t, void *); -static void lockstat_enable(void *, dtrace_id_t, void *); -static void lockstat_disable(void *, dtrace_id_t, void *); -static void lockstat_load(void *); -static int lockstat_unload(void); - - -typedef struct lockstat_probe { - char *lsp_func; - char *lsp_name; - int lsp_probe; - dtrace_id_t lsp_id; -#ifdef __FreeBSD__ - int lsp_frame; -#endif -} lockstat_probe_t; - -#ifdef __FreeBSD__ -lockstat_probe_t lockstat_probes[] = -{ - /* Spin Locks */ - { LS_MTX_SPIN_LOCK, LSS_ACQUIRE, LS_MTX_SPIN_LOCK_ACQUIRE, - DTRACE_IDNONE, LOCKSTAT_AFRAMES }, - { LS_MTX_SPIN_LOCK, LSS_SPIN, LS_MTX_SPIN_LOCK_SPIN, - DTRACE_IDNONE, LOCKSTAT_AFRAMES }, - { LS_MTX_SPIN_UNLOCK, LSS_RELEASE, LS_MTX_SPIN_UNLOCK_RELEASE, - DTRACE_IDNONE, LOCKSTAT_AFRAMES }, - /* Adaptive Locks */ - { LS_MTX_LOCK, LSA_ACQUIRE, LS_MTX_LOCK_ACQUIRE, - DTRACE_IDNONE, (LOCKSTAT_AFRAMES + 1) }, - { LS_MTX_LOCK, LSA_BLOCK, LS_MTX_LOCK_BLOCK, - DTRACE_IDNONE, (LOCKSTAT_AFRAMES + 1) }, - { LS_MTX_LOCK, LSA_SPIN, LS_MTX_LOCK_SPIN, - DTRACE_IDNONE, (LOCKSTAT_AFRAMES + 1) }, - { LS_MTX_UNLOCK, LSA_RELEASE, LS_MTX_UNLOCK_RELEASE, - DTRACE_IDNONE, LOCKSTAT_AFRAMES }, - { LS_MTX_TRYLOCK, LSA_ACQUIRE, LS_MTX_TRYLOCK_ACQUIRE, - DTRACE_IDNONE, LOCKSTAT_AFRAMES }, - /* Reader/Writer Locks */ - { LS_RW_RLOCK, LSR_ACQUIRE, LS_RW_RLOCK_ACQUIRE, - DTRACE_IDNONE, LOCKSTAT_AFRAMES }, - { LS_RW_RLOCK, LSR_BLOCK, LS_RW_RLOCK_BLOCK, - DTRACE_IDNONE, LOCKSTAT_AFRAMES }, - { LS_RW_RLOCK, LSR_SPIN, LS_RW_RLOCK_SPIN, - DTRACE_IDNONE, LOCKSTAT_AFRAMES }, - { LS_RW_RUNLOCK, LSR_RELEASE, LS_RW_RUNLOCK_RELEASE, - DTRACE_IDNONE, LOCKSTAT_AFRAMES }, - { LS_RW_WLOCK, LSR_ACQUIRE, LS_RW_WLOCK_ACQUIRE, - DTRACE_IDNONE, LOCKSTAT_AFRAMES }, - { LS_RW_WLOCK, LSR_BLOCK, LS_RW_WLOCK_BLOCK, - DTRACE_IDNONE, LOCKSTAT_AFRAMES }, - { LS_RW_WLOCK, LSR_SPIN, LS_RW_WLOCK_SPIN, - DTRACE_IDNONE, LOCKSTAT_AFRAMES }, - { LS_RW_WUNLOCK, LSR_RELEASE, LS_RW_WUNLOCK_RELEASE, - DTRACE_IDNONE, LOCKSTAT_AFRAMES }, - { LS_RW_TRYUPGRADE, LSR_UPGRADE, LS_RW_TRYUPGRADE_UPGRADE, - DTRACE_IDNONE, LOCKSTAT_AFRAMES }, - { LS_RW_DOWNGRADE, LSR_DOWNGRADE, LS_RW_DOWNGRADE_DOWNGRADE, - DTRACE_IDNONE, LOCKSTAT_AFRAMES }, - /* Shared/Exclusive Locks */ - { LS_SX_SLOCK, LSX_ACQUIRE, LS_SX_SLOCK_ACQUIRE, - DTRACE_IDNONE, LOCKSTAT_AFRAMES }, - { LS_SX_SLOCK, LSX_BLOCK, LS_SX_SLOCK_BLOCK, - DTRACE_IDNONE, LOCKSTAT_AFRAMES }, - { LS_SX_SLOCK, LSX_SPIN, LS_SX_SLOCK_SPIN, - DTRACE_IDNONE, LOCKSTAT_AFRAMES }, - { LS_SX_SUNLOCK, LSX_RELEASE, LS_SX_SUNLOCK_RELEASE, - DTRACE_IDNONE, LOCKSTAT_AFRAMES }, - { LS_SX_XLOCK, LSX_ACQUIRE, LS_SX_XLOCK_ACQUIRE, - DTRACE_IDNONE, LOCKSTAT_AFRAMES }, - { LS_SX_XLOCK, LSX_BLOCK, LS_SX_XLOCK_BLOCK, - DTRACE_IDNONE, LOCKSTAT_AFRAMES }, - { LS_SX_XLOCK, LSX_SPIN, LS_SX_XLOCK_SPIN, - DTRACE_IDNONE, LOCKSTAT_AFRAMES }, - { LS_SX_XUNLOCK, LSX_RELEASE, LS_SX_XUNLOCK_RELEASE, - DTRACE_IDNONE, LOCKSTAT_AFRAMES }, - { LS_SX_TRYUPGRADE, LSX_UPGRADE, LS_SX_TRYUPGRADE_UPGRADE, - DTRACE_IDNONE, LOCKSTAT_AFRAMES }, - { LS_SX_DOWNGRADE, LSX_DOWNGRADE, LS_SX_DOWNGRADE_DOWNGRADE, - DTRACE_IDNONE, LOCKSTAT_AFRAMES }, - /* Thread Locks */ - { LS_THREAD_LOCK, LST_SPIN, LS_THREAD_LOCK_SPIN, - DTRACE_IDNONE, LOCKSTAT_AFRAMES }, - { NULL } -}; -#else -#error "OS not supported" -#endif - - -static struct cdevsw lockstat_cdevsw = { - .d_version = D_VERSION, - .d_open = lockstat_open, - .d_name = "lockstat", -}; - -static struct cdev *lockstat_cdev; -static dtrace_provider_id_t lockstat_id; - -/*ARGSUSED*/ -static void -lockstat_enable(void *arg, dtrace_id_t id, void *parg) -{ - lockstat_probe_t *probe = parg; - - ASSERT(!lockstat_probemap[probe->lsp_probe]); - - lockstat_probemap[probe->lsp_probe] = id; -#ifdef DOODAD - membar_producer(); -#endif - - lockstat_probe_func = dtrace_probe; -#ifdef DOODAD - membar_producer(); - - lockstat_hot_patch(); - membar_producer(); -#endif -} - -/*ARGSUSED*/ -static void -lockstat_disable(void *arg, dtrace_id_t id, void *parg) -{ - lockstat_probe_t *probe = parg; - int i; - - ASSERT(lockstat_probemap[probe->lsp_probe]); - - lockstat_probemap[probe->lsp_probe] = 0; -#ifdef DOODAD - lockstat_hot_patch(); - membar_producer(); -#endif - - /* - * See if we have any probes left enabled. - */ - for (i = 0; i < LS_NPROBES; i++) { - if (lockstat_probemap[i]) { - /* - * This probe is still enabled. We don't need to deal - * with waiting for all threads to be out of the - * lockstat critical sections; just return. - */ - return; - } - } - -} - -/*ARGSUSED*/ -static int -lockstat_open(struct cdev *dev __unused, int oflags __unused, - int devtype __unused, struct thread *td __unused) -{ - return (0); -} - -/*ARGSUSED*/ -static void -lockstat_provide(void *arg, dtrace_probedesc_t *desc) -{ - int i = 0; - - for (i = 0; lockstat_probes[i].lsp_func != NULL; i++) { - lockstat_probe_t *probe = &lockstat_probes[i]; - - if (dtrace_probe_lookup(lockstat_id, "kernel", - probe->lsp_func, probe->lsp_name) != 0) - continue; - - ASSERT(!probe->lsp_id); -#ifdef __FreeBSD__ - probe->lsp_id = dtrace_probe_create(lockstat_id, - "kernel", probe->lsp_func, probe->lsp_name, - probe->lsp_frame, probe); -#else - probe->lsp_id = dtrace_probe_create(lockstat_id, - "kernel", probe->lsp_func, probe->lsp_name, - LOCKSTAT_AFRAMES, probe); -#endif - } -} - -/*ARGSUSED*/ -static void -lockstat_destroy(void *arg, dtrace_id_t id, void *parg) -{ - lockstat_probe_t *probe = parg; - - ASSERT(!lockstat_probemap[probe->lsp_probe]); - probe->lsp_id = 0; -} - -static dtrace_pattr_t lockstat_attr = { -{ DTRACE_STABILITY_EVOLVING, DTRACE_STABILITY_EVOLVING, DTRACE_CLASS_COMMON }, -{ DTRACE_STABILITY_PRIVATE, DTRACE_STABILITY_PRIVATE, DTRACE_CLASS_UNKNOWN }, -{ DTRACE_STABILITY_PRIVATE, DTRACE_STABILITY_PRIVATE, DTRACE_CLASS_UNKNOWN }, -{ DTRACE_STABILITY_EVOLVING, DTRACE_STABILITY_EVOLVING, DTRACE_CLASS_COMMON }, -{ DTRACE_STABILITY_EVOLVING, DTRACE_STABILITY_EVOLVING, DTRACE_CLASS_COMMON }, -}; - -static dtrace_pops_t lockstat_pops = { - lockstat_provide, - NULL, - lockstat_enable, - lockstat_disable, - NULL, - NULL, - NULL, - NULL, - NULL, - lockstat_destroy -}; - -static void -lockstat_load(void *dummy) -{ - /* Create the /dev/dtrace/lockstat entry. */ - lockstat_cdev = make_dev(&lockstat_cdevsw, 0, UID_ROOT, GID_WHEEL, 0600, - "dtrace/lockstat"); - - if (dtrace_register("lockstat", &lockstat_attr, DTRACE_PRIV_USER, - NULL, &lockstat_pops, NULL, &lockstat_id) != 0) - return; -} - -static int -lockstat_unload() -{ - int error = 0; - - if ((error = dtrace_unregister(lockstat_id)) != 0) - return (error); - - destroy_dev(lockstat_cdev); - - return (error); -} - -/* ARGSUSED */ -static int -lockstat_modevent(module_t mod __unused, int type, void *data __unused) -{ - int error = 0; - - switch (type) { - case MOD_LOAD: - break; - - case MOD_UNLOAD: - break; - - case MOD_SHUTDOWN: - break; - - default: - error = EOPNOTSUPP; - break; - } - return (error); -} - -SYSINIT(lockstat_load, SI_SUB_DTRACE_PROVIDER, SI_ORDER_ANY, lockstat_load, NULL); -SYSUNINIT(lockstat_unload, SI_SUB_DTRACE_PROVIDER, SI_ORDER_ANY, lockstat_unload, NULL); - -DEV_MODULE(lockstat, lockstat_modevent, NULL); -MODULE_VERSION(lockstat, 1); -MODULE_DEPEND(lockstat, dtrace, 1, 1, 1); -MODULE_DEPEND(lockstat, opensolaris, 1, 1, 1); diff --git a/sys/cddl/dev/sdt/sdt.c b/sys/cddl/dev/sdt/sdt.c index 27cb03507536..a32131740890 100644 --- a/sys/cddl/dev/sdt/sdt.c +++ b/sys/cddl/dev/sdt/sdt.c @@ -50,6 +50,7 @@ #include #include #include +#include #include #include #include @@ -197,6 +198,8 @@ sdt_enable(void *arg __unused, dtrace_id_t id, void *parg) probe->id = id; probe->sdtp_lf->nenabled++; + if (strcmp(probe->prov->name, "lockstat") == 0) + lockstat_enabled++; } static void @@ -206,6 +209,8 @@ sdt_disable(void *arg __unused, dtrace_id_t id, void *parg) KASSERT(probe->sdtp_lf->nenabled > 0, ("no probes enabled")); + if (strcmp(probe->prov->name, "lockstat") == 0) + lockstat_enabled--; probe->id = 0; probe->sdtp_lf->nenabled--; } diff --git a/sys/compat/cloudabi/cloudabi_clock.c b/sys/compat/cloudabi/cloudabi_clock.c index a6b783c59117..8462f233b738 100644 --- a/sys/compat/cloudabi/cloudabi_clock.c +++ b/sys/compat/cloudabi/cloudabi_clock.c @@ -26,22 +26,100 @@ #include __FBSDID("$FreeBSD$"); +#include +#include +#include +#include + #include +#include +#include + +/* Converts a CloudABI clock ID to a FreeBSD clock ID. */ +static int +cloudabi_convert_clockid(cloudabi_clockid_t in, clockid_t *out) +{ + switch (in) { + case CLOUDABI_CLOCK_MONOTONIC: + *out = CLOCK_MONOTONIC; + return (0); + case CLOUDABI_CLOCK_PROCESS_CPUTIME_ID: + *out = CLOCK_PROCESS_CPUTIME_ID; + return (0); + case CLOUDABI_CLOCK_REALTIME: + *out = CLOCK_REALTIME; + return (0); + case CLOUDABI_CLOCK_THREAD_CPUTIME_ID: + *out = CLOCK_THREAD_CPUTIME_ID; + return (0); + default: + return (EINVAL); + } +} + +/* Converts a struct timespec to a CloudABI timestamp. */ +int +cloudabi_convert_timespec(const struct timespec *in, cloudabi_timestamp_t *out) +{ + cloudabi_timestamp_t s, ns; + + if (in->tv_sec < 0) { + /* Timestamps from before the Epoch cannot be expressed. */ + *out = 0; + return (EOVERFLOW); + } + s = in->tv_sec; + ns = in->tv_nsec; + if (s > UINT64_MAX / 1000000000 || + (s == UINT64_MAX / 1000000000 && ns > UINT64_MAX % 1000000000)) { + /* Addition of seconds and nanoseconds would overflow. */ + *out = UINT64_MAX; + return (EOVERFLOW); + } + *out = s * 1000000000 + ns; + return (0); +} int cloudabi_sys_clock_res_get(struct thread *td, struct cloudabi_sys_clock_res_get_args *uap) { + struct timespec ts; + cloudabi_timestamp_t cts; + int error; + clockid_t clockid; - /* Not implemented. */ - return (ENOSYS); + error = cloudabi_convert_clockid(uap->clock_id, &clockid); + if (error != 0) + return (error); + error = kern_clock_getres(td, clockid, &ts); + if (error != 0) + return (error); + error = cloudabi_convert_timespec(&ts, &cts); + if (error != 0) + return (error); + td->td_retval[0] = cts; + return (0); } int cloudabi_sys_clock_time_get(struct thread *td, struct cloudabi_sys_clock_time_get_args *uap) { + struct timespec ts; + cloudabi_timestamp_t cts; + int error; + clockid_t clockid; - /* Not implemented. */ - return (ENOSYS); + error = cloudabi_convert_clockid(uap->clock_id, &clockid); + if (error != 0) + return (error); + error = kern_clock_gettime(td, clockid, &ts); + if (error != 0) + return (error); + error = cloudabi_convert_timespec(&ts, &cts); + if (error != 0) + return (error); + td->td_retval[0] = cts; + return (0); } diff --git a/sys/compat/cloudabi/cloudabi_errno.c b/sys/compat/cloudabi/cloudabi_errno.c new file mode 100644 index 000000000000..5193cfc196e3 --- /dev/null +++ b/sys/compat/cloudabi/cloudabi_errno.c @@ -0,0 +1,121 @@ +/*- + * Copyright (c) 2015 Nuxi, https://nuxi.nl/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include + +#include +#include + +/* Converts a FreeBSD errno to a CloudABI errno. */ +cloudabi_errno_t +cloudabi_convert_errno(int error) +{ + static const int table[] = { + [E2BIG] = CLOUDABI_E2BIG, + [EACCES] = CLOUDABI_EACCES, + [EADDRINUSE] = CLOUDABI_EADDRINUSE, + [EADDRNOTAVAIL] = CLOUDABI_EADDRNOTAVAIL, + [EAFNOSUPPORT] = CLOUDABI_EAFNOSUPPORT, + [EAGAIN] = CLOUDABI_EAGAIN, + [EALREADY] = CLOUDABI_EALREADY, + [EBADF] = CLOUDABI_EBADF, + [EBADMSG] = CLOUDABI_EBADMSG, + [EBUSY] = CLOUDABI_EBUSY, + [ECANCELED] = CLOUDABI_ECANCELED, + [ECHILD] = CLOUDABI_ECHILD, + [ECONNABORTED] = CLOUDABI_ECONNABORTED, + [ECONNREFUSED] = CLOUDABI_ECONNREFUSED, + [ECONNRESET] = CLOUDABI_ECONNRESET, + [EDEADLK] = CLOUDABI_EDEADLK, + [EDESTADDRREQ] = CLOUDABI_EDESTADDRREQ, + [EDOM] = CLOUDABI_EDOM, + [EDQUOT] = CLOUDABI_EDQUOT, + [EEXIST] = CLOUDABI_EEXIST, + [EFAULT] = CLOUDABI_EFAULT, + [EFBIG] = CLOUDABI_EFBIG, + [EHOSTUNREACH] = CLOUDABI_EHOSTUNREACH, + [EIDRM] = CLOUDABI_EIDRM, + [EILSEQ] = CLOUDABI_EILSEQ, + [EINPROGRESS] = CLOUDABI_EINPROGRESS, + [EINTR] = CLOUDABI_EINTR, + [EINVAL] = CLOUDABI_EINVAL, + [EIO] = CLOUDABI_EIO, + [EISCONN] = CLOUDABI_EISCONN, + [EISDIR] = CLOUDABI_EISDIR, + [ELOOP] = CLOUDABI_ELOOP, + [EMFILE] = CLOUDABI_EMFILE, + [EMLINK] = CLOUDABI_EMLINK, + [EMSGSIZE] = CLOUDABI_EMSGSIZE, + [EMULTIHOP] = CLOUDABI_EMULTIHOP, + [ENAMETOOLONG] = CLOUDABI_ENAMETOOLONG, + [ENETDOWN] = CLOUDABI_ENETDOWN, + [ENETRESET] = CLOUDABI_ENETRESET, + [ENETUNREACH] = CLOUDABI_ENETUNREACH, + [ENFILE] = CLOUDABI_ENFILE, + [ENOBUFS] = CLOUDABI_ENOBUFS, + [ENODEV] = CLOUDABI_ENODEV, + [ENOENT] = CLOUDABI_ENOENT, + [ENOEXEC] = CLOUDABI_ENOEXEC, + [ENOLCK] = CLOUDABI_ENOLCK, + [ENOLINK] = CLOUDABI_ENOLINK, + [ENOMEM] = CLOUDABI_ENOMEM, + [ENOMSG] = CLOUDABI_ENOMSG, + [ENOPROTOOPT] = CLOUDABI_ENOPROTOOPT, + [ENOSPC] = CLOUDABI_ENOSPC, + [ENOSYS] = CLOUDABI_ENOSYS, + [ENOTCONN] = CLOUDABI_ENOTCONN, + [ENOTDIR] = CLOUDABI_ENOTDIR, + [ENOTEMPTY] = CLOUDABI_ENOTEMPTY, + [ENOTRECOVERABLE] = CLOUDABI_ENOTRECOVERABLE, + [ENOTSOCK] = CLOUDABI_ENOTSOCK, + [ENOTSUP] = CLOUDABI_ENOTSUP, + [ENOTTY] = CLOUDABI_ENOTTY, + [ENXIO] = CLOUDABI_ENXIO, + [EOVERFLOW] = CLOUDABI_EOVERFLOW, + [EOWNERDEAD] = CLOUDABI_EOWNERDEAD, + [EPERM] = CLOUDABI_EPERM, + [EPIPE] = CLOUDABI_EPIPE, + [EPROTO] = CLOUDABI_EPROTO, + [EPROTONOSUPPORT] = CLOUDABI_EPROTONOSUPPORT, + [EPROTOTYPE] = CLOUDABI_EPROTOTYPE, + [ERANGE] = CLOUDABI_ERANGE, + [EROFS] = CLOUDABI_EROFS, + [ESPIPE] = CLOUDABI_ESPIPE, + [ESRCH] = CLOUDABI_ESRCH, + [ESTALE] = CLOUDABI_ESTALE, + [ETIMEDOUT] = CLOUDABI_ETIMEDOUT, + [ETXTBSY] = CLOUDABI_ETXTBSY, + [EXDEV] = CLOUDABI_EXDEV, + [ENOTCAPABLE] = CLOUDABI_ENOTCAPABLE, + }; + + /* Unknown error: fall back to returning ENOSYS. */ + if (error < 0 || error >= nitems(table) || table[error] == 0) + return (error == 0 ? 0 : CLOUDABI_ENOSYS); + return (table[error]); +} diff --git a/sys/compat/cloudabi/cloudabi_fd.c b/sys/compat/cloudabi/cloudabi_fd.c index 5ac9015e7785..da3c0da59305 100644 --- a/sys/compat/cloudabi/cloudabi_fd.c +++ b/sys/compat/cloudabi/cloudabi_fd.c @@ -76,7 +76,7 @@ int cloudabi_sys_fd_dup(struct thread *td, struct cloudabi_sys_fd_dup_args *uap) { - return (kern_dup(td, 0, uap->from, 0)); + return (kern_dup(td, FDDUP_NORMAL, 0, uap->from, 0)); } int @@ -97,7 +97,7 @@ cloudabi_sys_fd_replace(struct thread *td, * clear the return value, as this system call yields no return * value. */ - error = kern_dup(td, FDDUP_MUSTREPLACE, uap->from, uap->to); + error = kern_dup(td, FDDUP_MUSTREPLACE, 0, uap->from, uap->to); td->td_retval[0] = 0; return (error); } diff --git a/sys/compat/cloudabi/cloudabi_file.c b/sys/compat/cloudabi/cloudabi_file.c index 46e5792f0959..034cf0159479 100644 --- a/sys/compat/cloudabi/cloudabi_file.c +++ b/sys/compat/cloudabi/cloudabi_file.c @@ -26,15 +26,43 @@ #include __FBSDID("$FreeBSD$"); +#include +#include +#include + #include +#include int cloudabi_sys_file_advise(struct thread *td, struct cloudabi_sys_file_advise_args *uap) { + int advice; - /* Not implemented. */ - return (ENOSYS); + switch (uap->advice) { + case CLOUDABI_ADVICE_DONTNEED: + advice = POSIX_FADV_DONTNEED; + break; + case CLOUDABI_ADVICE_NOREUSE: + advice = POSIX_FADV_NOREUSE; + break; + case CLOUDABI_ADVICE_NORMAL: + advice = POSIX_FADV_NORMAL; + break; + case CLOUDABI_ADVICE_RANDOM: + advice = POSIX_FADV_RANDOM; + break; + case CLOUDABI_ADVICE_SEQUENTIAL: + advice = POSIX_FADV_SEQUENTIAL; + break; + case CLOUDABI_ADVICE_WILLNEED: + advice = POSIX_FADV_WILLNEED; + break; + default: + return (EINVAL); + } + + return (kern_posix_fadvise(td, uap->fd, uap->offset, uap->len, advice)); } int @@ -42,8 +70,7 @@ cloudabi_sys_file_allocate(struct thread *td, struct cloudabi_sys_file_allocate_args *uap) { - /* Not implemented. */ - return (ENOSYS); + return (kern_posix_fallocate(td, uap->fd, uap->offset, uap->len)); } int diff --git a/sys/compat/cloudabi/cloudabi_mem.c b/sys/compat/cloudabi/cloudabi_mem.c index e519ed15be5b..5bc5a19adc68 100644 --- a/sys/compat/cloudabi/cloudabi_mem.c +++ b/sys/compat/cloudabi/cloudabi_mem.c @@ -26,64 +26,154 @@ #include __FBSDID("$FreeBSD$"); +#include +#include +#include + #include +#include + +/* Converts CloudABI's memory protection flags to FreeBSD's. */ +static int +convert_mprot(cloudabi_mprot_t in) +{ + int out; + + out = 0; + if (in & CLOUDABI_PROT_EXEC) + out |= PROT_EXEC; + if (in & CLOUDABI_PROT_WRITE) + out |= PROT_WRITE; + if (in & CLOUDABI_PROT_READ) + out |= PROT_READ; + return (out); +} int cloudabi_sys_mem_advise(struct thread *td, struct cloudabi_sys_mem_advise_args *uap) { + struct madvise_args madvise_args = { + .addr = uap->addr, + .len = uap->len + }; - /* Not implemented. */ - return (ENOSYS); + switch (uap->advice) { + case CLOUDABI_ADVICE_DONTNEED: + madvise_args.behav = MADV_DONTNEED; + break; + case CLOUDABI_ADVICE_NORMAL: + madvise_args.behav = MADV_NORMAL; + break; + case CLOUDABI_ADVICE_RANDOM: + madvise_args.behav = MADV_RANDOM; + break; + case CLOUDABI_ADVICE_SEQUENTIAL: + madvise_args.behav = MADV_SEQUENTIAL; + break; + case CLOUDABI_ADVICE_WILLNEED: + madvise_args.behav = MADV_WILLNEED; + break; + default: + return (EINVAL); + } + + return (sys_madvise(td, &madvise_args)); } int cloudabi_sys_mem_lock(struct thread *td, struct cloudabi_sys_mem_lock_args *uap) { + struct mlock_args mlock_args = { + .addr = uap->addr, + .len = uap->len + }; - /* Not implemented. */ - return (ENOSYS); + return (sys_mlock(td, &mlock_args)); } int cloudabi_sys_mem_map(struct thread *td, struct cloudabi_sys_mem_map_args *uap) { + struct mmap_args mmap_args = { + .addr = uap->addr, + .len = uap->len, + .prot = convert_mprot(uap->prot), + .fd = uap->fd, + .pos = uap->off + }; - /* Not implemented. */ - return (ENOSYS); + /* Translate flags. */ + if (uap->flags & CLOUDABI_MAP_ANON) + mmap_args.flags |= MAP_ANON; + if (uap->flags & CLOUDABI_MAP_FIXED) + mmap_args.flags |= MAP_FIXED; + if (uap->flags & CLOUDABI_MAP_PRIVATE) + mmap_args.flags |= MAP_PRIVATE; + if (uap->flags & CLOUDABI_MAP_SHARED) + mmap_args.flags |= MAP_SHARED; + + return (sys_mmap(td, &mmap_args)); } int cloudabi_sys_mem_protect(struct thread *td, struct cloudabi_sys_mem_protect_args *uap) { + struct mprotect_args mprotect_args = { + .addr = uap->addr, + .len = uap->len, + .prot = convert_mprot(uap->prot), + }; - /* Not implemented. */ - return (ENOSYS); + return (sys_mprotect(td, &mprotect_args)); } int cloudabi_sys_mem_sync(struct thread *td, struct cloudabi_sys_mem_sync_args *uap) { + struct msync_args msync_args = { + .addr = uap->addr, + .len = uap->len, + }; - /* Not implemented. */ - return (ENOSYS); + /* Convert flags. */ + switch (uap->flags & (CLOUDABI_MS_ASYNC | CLOUDABI_MS_SYNC)) { + case CLOUDABI_MS_ASYNC: + msync_args.flags |= MS_ASYNC; + break; + case CLOUDABI_MS_SYNC: + msync_args.flags |= MS_SYNC; + break; + default: + return (EINVAL); + } + if ((uap->flags & CLOUDABI_MS_INVALIDATE) != 0) + msync_args.flags |= MS_INVALIDATE; + + return (sys_msync(td, &msync_args)); } int cloudabi_sys_mem_unlock(struct thread *td, struct cloudabi_sys_mem_unlock_args *uap) { + struct munlock_args munlock_args = { + .addr = uap->addr, + .len = uap->len + }; - /* Not implemented. */ - return (ENOSYS); + return (sys_munlock(td, &munlock_args)); } int cloudabi_sys_mem_unmap(struct thread *td, struct cloudabi_sys_mem_unmap_args *uap) { + struct munmap_args munmap_args = { + .addr = uap->addr, + .len = uap->len + }; - /* Not implemented. */ - return (ENOSYS); + return (sys_munmap(td, &munmap_args)); } diff --git a/sys/compat/cloudabi/cloudabi_proc.c b/sys/compat/cloudabi/cloudabi_proc.c index faa39dcfbaab..1f4418f0b589 100644 --- a/sys/compat/cloudabi/cloudabi_proc.c +++ b/sys/compat/cloudabi/cloudabi_proc.c @@ -26,15 +26,32 @@ #include __FBSDID("$FreeBSD$"); +#include +#include +#include +#include +#include +#include +#include +#include + #include +#include int cloudabi_sys_proc_exec(struct thread *td, struct cloudabi_sys_proc_exec_args *uap) { + struct image_args args; + int error; - /* Not implemented. */ - return (ENOSYS); + error = exec_copyin_data_fds(td, &args, uap->data, uap->datalen, + uap->fds, uap->fdslen); + if (error == 0) { + args.fd = uap->fd; + error = kern_execve(td, &args, NULL); + } + return (error); } int @@ -42,24 +59,73 @@ cloudabi_sys_proc_exit(struct thread *td, struct cloudabi_sys_proc_exit_args *uap) { - /* Not implemented. */ - return (ENOSYS); + exit1(td, uap->rval, 0); + /* NOTREACHED */ } int cloudabi_sys_proc_fork(struct thread *td, struct cloudabi_sys_proc_fork_args *uap) { + struct proc *p2; + int error, fd; - /* Not implemented. */ - return (ENOSYS); + error = fork1(td, RFFDG | RFPROC | RFPROCDESC, 0, &p2, &fd, 0); + if (error != 0) + return (error); + /* Return the file descriptor to the parent process. */ + td->td_retval[0] = fd; + return (0); } int cloudabi_sys_proc_raise(struct thread *td, struct cloudabi_sys_proc_raise_args *uap) { + static const int signals[] = { + [CLOUDABI_SIGABRT] = SIGABRT, + [CLOUDABI_SIGALRM] = SIGALRM, + [CLOUDABI_SIGBUS] = SIGBUS, + [CLOUDABI_SIGCHLD] = SIGCHLD, + [CLOUDABI_SIGCONT] = SIGCONT, + [CLOUDABI_SIGFPE] = SIGFPE, + [CLOUDABI_SIGHUP] = SIGHUP, + [CLOUDABI_SIGILL] = SIGILL, + [CLOUDABI_SIGINT] = SIGINT, + [CLOUDABI_SIGKILL] = SIGKILL, + [CLOUDABI_SIGPIPE] = SIGPIPE, + [CLOUDABI_SIGQUIT] = SIGQUIT, + [CLOUDABI_SIGSEGV] = SIGSEGV, + [CLOUDABI_SIGSTOP] = SIGSTOP, + [CLOUDABI_SIGSYS] = SIGSYS, + [CLOUDABI_SIGTERM] = SIGTERM, + [CLOUDABI_SIGTRAP] = SIGTRAP, + [CLOUDABI_SIGTSTP] = SIGTSTP, + [CLOUDABI_SIGTTIN] = SIGTTIN, + [CLOUDABI_SIGTTOU] = SIGTTOU, + [CLOUDABI_SIGURG] = SIGURG, + [CLOUDABI_SIGUSR1] = SIGUSR1, + [CLOUDABI_SIGUSR2] = SIGUSR2, + [CLOUDABI_SIGVTALRM] = SIGVTALRM, + [CLOUDABI_SIGXCPU] = SIGXCPU, + [CLOUDABI_SIGXFSZ] = SIGXFSZ, + }; + ksiginfo_t ksi; + struct proc *p; - /* Not implemented. */ - return (ENOSYS); + if (uap->sig >= nitems(signals) || signals[uap->sig] == 0) { + /* Invalid signal, or the null signal. */ + return (uap->sig == 0 ? 0 : EINVAL); + } + + p = td->td_proc; + ksiginfo_init(&ksi); + ksi.ksi_signo = signals[uap->sig]; + ksi.ksi_code = SI_USER; + ksi.ksi_pid = p->p_pid; + ksi.ksi_uid = td->td_ucred->cr_ruid; + PROC_LOCK(p); + pksignal(p, ksi.ksi_signo, &ksi); + PROC_UNLOCK(p); + return (0); } diff --git a/sys/compat/cloudabi/cloudabi_random.c b/sys/compat/cloudabi/cloudabi_random.c index bd644c316353..76a93604d299 100644 --- a/sys/compat/cloudabi/cloudabi_random.c +++ b/sys/compat/cloudabi/cloudabi_random.c @@ -26,13 +26,28 @@ #include __FBSDID("$FreeBSD$"); +#include +#include +#include + #include int cloudabi_sys_random_get(struct thread *td, struct cloudabi_sys_random_get_args *uap) { + struct iovec iov = { + .iov_base = uap->buf, + .iov_len = uap->nbyte + }; + struct uio uio = { + .uio_iov = &iov, + .uio_iovcnt = 1, + .uio_resid = iov.iov_len, + .uio_segflg = UIO_USERSPACE, + .uio_rw = UIO_READ, + .uio_td = td + }; - /* Not implemented. */ - return (ENOSYS); + return (read_random_uio(&uio, false)); } diff --git a/sys/compat/cloudabi/cloudabi_sock.c b/sys/compat/cloudabi/cloudabi_sock.c index a332374f69c8..38aa4fedbd93 100644 --- a/sys/compat/cloudabi/cloudabi_sock.c +++ b/sys/compat/cloudabi/cloudabi_sock.c @@ -26,7 +26,11 @@ #include __FBSDID("$FreeBSD$"); +#include +#include + #include +#include int cloudabi_sys_sock_accept(struct thread *td, @@ -59,18 +63,37 @@ int cloudabi_sys_sock_listen(struct thread *td, struct cloudabi_sys_sock_listen_args *uap) { + struct listen_args listen_args = { + .s = uap->s, + .backlog = uap->backlog, + }; - /* Not implemented. */ - return (ENOSYS); + return (sys_listen(td, &listen_args)); } int cloudabi_sys_sock_shutdown(struct thread *td, struct cloudabi_sys_sock_shutdown_args *uap) { + struct shutdown_args shutdown_args = { + .s = uap->fd, + }; - /* Not implemented. */ - return (ENOSYS); + switch (uap->how) { + case CLOUDABI_SHUT_RD: + shutdown_args.how = SHUT_RD; + break; + case CLOUDABI_SHUT_WR: + shutdown_args.how = SHUT_WR; + break; + case CLOUDABI_SHUT_RD | CLOUDABI_SHUT_WR: + shutdown_args.how = SHUT_RDWR; + break; + default: + return (EINVAL); + } + + return (sys_shutdown(td, &shutdown_args)); } int diff --git a/sys/compat/cloudabi/cloudabi_thread.c b/sys/compat/cloudabi/cloudabi_thread.c index 051d420cd336..4b9eb54b57e5 100644 --- a/sys/compat/cloudabi/cloudabi_thread.c +++ b/sys/compat/cloudabi/cloudabi_thread.c @@ -26,6 +26,10 @@ #include __FBSDID("$FreeBSD$"); +#include +#include +#include + #include int @@ -37,11 +41,19 @@ cloudabi_sys_thread_exit(struct thread *td, return (ENOSYS); } +int +cloudabi_sys_thread_tcb_set(struct thread *td, + struct cloudabi_sys_thread_tcb_set_args *uap) +{ + + return (cpu_set_user_tls(td, uap->tcb)); +} + int cloudabi_sys_thread_yield(struct thread *td, struct cloudabi_sys_thread_yield_args *uap) { - /* Not implemented. */ - return (ENOSYS); + sched_relinquish(td); + return (0); } diff --git a/sys/compat/cloudabi/cloudabi_util.h b/sys/compat/cloudabi/cloudabi_util.h new file mode 100644 index 000000000000..d9e6f127eb97 --- /dev/null +++ b/sys/compat/cloudabi/cloudabi_util.h @@ -0,0 +1,41 @@ +/*- + * Copyright (c) 2015 Nuxi, https://nuxi.nl/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _CLOUDABI_UTIL_H_ +#define _CLOUDABI_UTIL_H_ + +#include + +struct timespec; + +/* Converts a FreeBSD errno to a CloudABI errno. */ +cloudabi_errno_t cloudabi_convert_errno(int); + +/* Converts a struct timespec to a CloudABI timestamp. */ +int cloudabi_convert_timespec(const struct timespec *, cloudabi_timestamp_t *); + +#endif diff --git a/sys/compat/cloudabi64/cloudabi64_fd.c b/sys/compat/cloudabi64/cloudabi64_fd.c index bbe236ae835c..b2fd67d8aaf8 100644 --- a/sys/compat/cloudabi64/cloudabi64_fd.c +++ b/sys/compat/cloudabi64/cloudabi64_fd.c @@ -26,41 +26,120 @@ #include __FBSDID("$FreeBSD$"); +#include +#include +#include +#include +#include +#include +#include + #include #include +/* Copies in 64-bit iovec structures from userspace. */ +static int +cloudabi64_copyinuio(const cloudabi64_iovec_t *iovp, size_t iovcnt, + struct uio **uiop) +{ + cloudabi64_iovec_t iovobj; + struct uio *uio; + struct iovec *iov; + size_t i; + int error; + + /* Allocate uio and iovecs. */ + if (iovcnt > UIO_MAXIOV) + return (EINVAL); + uio = malloc(sizeof(struct uio) + iovcnt * sizeof(struct iovec), + M_IOV, M_WAITOK); + iov = (struct iovec *)(uio + 1); + + /* Initialize uio. */ + uio->uio_iov = iov; + uio->uio_iovcnt = iovcnt; + uio->uio_segflg = UIO_USERSPACE; + uio->uio_offset = -1; + uio->uio_resid = 0; + + /* Copy in iovecs. */ + for (i = 0; i < iovcnt; i++) { + error = copyin(&iovp[i], &iovobj, sizeof(iovobj)); + if (error != 0) { + free(uio, M_IOV); + return (error); + } + iov[i].iov_base = (void *)iovobj.iov_base; + iov[i].iov_len = iovobj.iov_len; + if (iov[i].iov_len > SSIZE_MAX - uio->uio_resid) { + free(uio, M_IOV); + return (EINVAL); + } + uio->uio_resid += iov[i].iov_len; + } + + *uiop = uio; + return (0); +} + int cloudabi64_sys_fd_pread(struct thread *td, struct cloudabi64_sys_fd_pread_args *uap) { + struct uio *uio; + int error; - /* Not implemented. */ - return (ENOSYS); + error = cloudabi64_copyinuio(uap->iov, uap->iovcnt, &uio); + if (error != 0) + return (error); + error = kern_preadv(td, uap->fd, uio, uap->offset); + free(uio, M_IOV); + return (error); } int cloudabi64_sys_fd_pwrite(struct thread *td, struct cloudabi64_sys_fd_pwrite_args *uap) { + struct uio *uio; + int error; - /* Not implemented. */ - return (ENOSYS); + error = cloudabi64_copyinuio((const cloudabi64_iovec_t *)uap->iov, + uap->iovcnt, &uio); + if (error != 0) + return (error); + error = kern_pwritev(td, uap->fd, uio, uap->offset); + free(uio, M_IOV); + return (error); } int cloudabi64_sys_fd_read(struct thread *td, struct cloudabi64_sys_fd_read_args *uap) { + struct uio *uio; + int error; - /* Not implemented. */ - return (ENOSYS); + error = cloudabi64_copyinuio(uap->iov, uap->iovcnt, &uio); + if (error != 0) + return (error); + error = kern_readv(td, uap->fd, uio); + free(uio, M_IOV); + return (error); } int cloudabi64_sys_fd_write(struct thread *td, struct cloudabi64_sys_fd_write_args *uap) { + struct uio *uio; + int error; - /* Not implemented. */ - return (ENOSYS); + error = cloudabi64_copyinuio((const cloudabi64_iovec_t *)uap->iov, + uap->iovcnt, &uio); + if (error != 0) + return (error); + error = kern_writev(td, uap->fd, uio); + free(uio, M_IOV); + return (error); } diff --git a/sys/compat/cloudabi64/cloudabi64_proto.h b/sys/compat/cloudabi64/cloudabi64_proto.h index 9d33b7c938c9..2dbf1cbb1e19 100644 --- a/sys/compat/cloudabi64/cloudabi64_proto.h +++ b/sys/compat/cloudabi64/cloudabi64_proto.h @@ -3,7 +3,7 @@ * * DO NOT EDIT-- this file is automatically generated. * $FreeBSD$ - * created from FreeBSD: head/sys/compat/cloudabi64/syscalls.master 285307 2015-07-09 07:20:15Z ed + * created from FreeBSD: head/sys/compat/cloudabi64/syscalls.master 285790 2015-07-22 10:04:53Z ed */ #ifndef _CLOUDABI64_SYSPROTO_H_ @@ -43,6 +43,7 @@ struct cloudabi_sys_clock_time_get_args { }; struct cloudabi_sys_condvar_signal_args { char condvar_l_[PADL_(cloudabi_condvar_t *)]; cloudabi_condvar_t * condvar; char condvar_r_[PADR_(cloudabi_condvar_t *)]; + char scope_l_[PADL_(cloudabi_futexscope_t)]; cloudabi_futexscope_t scope; char scope_r_[PADR_(cloudabi_futexscope_t)]; char nwaiters_l_[PADL_(cloudabi_nthreads_t)]; cloudabi_nthreads_t nwaiters; char nwaiters_r_[PADR_(cloudabi_nthreads_t)]; }; struct cloudabi_sys_fd_close_args { @@ -193,6 +194,7 @@ struct cloudabi_sys_file_unlink_args { }; struct cloudabi_sys_lock_unlock_args { char lock_l_[PADL_(cloudabi_lock_t *)]; cloudabi_lock_t * lock; char lock_r_[PADR_(cloudabi_lock_t *)]; + char scope_l_[PADL_(cloudabi_futexscope_t)]; cloudabi_futexscope_t scope; char scope_r_[PADR_(cloudabi_futexscope_t)]; }; struct cloudabi_sys_mem_advise_args { char addr_l_[PADL_(void *)]; void * addr; char addr_r_[PADR_(void *)]; @@ -300,8 +302,9 @@ struct cloudabi64_sys_thread_create_args { }; struct cloudabi_sys_thread_exit_args { char lock_l_[PADL_(cloudabi_lock_t *)]; cloudabi_lock_t * lock; char lock_r_[PADR_(cloudabi_lock_t *)]; + char scope_l_[PADL_(cloudabi_futexscope_t)]; cloudabi_futexscope_t scope; char scope_r_[PADR_(cloudabi_futexscope_t)]; }; -struct cloudabi64_sys_thread_tcb_set_args { +struct cloudabi_sys_thread_tcb_set_args { char tcb_l_[PADL_(void *)]; void * tcb; char tcb_r_[PADR_(void *)]; }; struct cloudabi_sys_thread_yield_args { @@ -362,7 +365,7 @@ int cloudabi_sys_sock_shutdown(struct thread *, struct cloudabi_sys_sock_shutdow int cloudabi_sys_sock_stat_get(struct thread *, struct cloudabi_sys_sock_stat_get_args *); int cloudabi64_sys_thread_create(struct thread *, struct cloudabi64_sys_thread_create_args *); int cloudabi_sys_thread_exit(struct thread *, struct cloudabi_sys_thread_exit_args *); -int cloudabi64_sys_thread_tcb_set(struct thread *, struct cloudabi64_sys_thread_tcb_set_args *); +int cloudabi_sys_thread_tcb_set(struct thread *, struct cloudabi_sys_thread_tcb_set_args *); int cloudabi_sys_thread_yield(struct thread *, struct cloudabi_sys_thread_yield_args *); #ifdef COMPAT_43 @@ -443,7 +446,7 @@ int cloudabi_sys_thread_yield(struct thread *, struct cloudabi_sys_thread_yield_ #define CLOUDABI64_SYS_AUE_cloudabi_sys_sock_stat_get AUE_NULL #define CLOUDABI64_SYS_AUE_cloudabi64_sys_thread_create AUE_NULL #define CLOUDABI64_SYS_AUE_cloudabi_sys_thread_exit AUE_NULL -#define CLOUDABI64_SYS_AUE_cloudabi64_sys_thread_tcb_set AUE_NULL +#define CLOUDABI64_SYS_AUE_cloudabi_sys_thread_tcb_set AUE_NULL #define CLOUDABI64_SYS_AUE_cloudabi_sys_thread_yield AUE_NULL #undef PAD_ diff --git a/sys/compat/cloudabi64/cloudabi64_syscall.h b/sys/compat/cloudabi64/cloudabi64_syscall.h index 2904a9f0c25c..a3dce677ef1f 100644 --- a/sys/compat/cloudabi64/cloudabi64_syscall.h +++ b/sys/compat/cloudabi64/cloudabi64_syscall.h @@ -3,7 +3,7 @@ * * DO NOT EDIT-- this file is automatically generated. * $FreeBSD$ - * created from FreeBSD: head/sys/compat/cloudabi64/syscalls.master 285307 2015-07-09 07:20:15Z ed + * created from FreeBSD: head/sys/compat/cloudabi64/syscalls.master 285790 2015-07-22 10:04:53Z ed */ #define CLOUDABI64_SYS_cloudabi_sys_clock_res_get 0 @@ -61,6 +61,6 @@ #define CLOUDABI64_SYS_cloudabi_sys_sock_stat_get 52 #define CLOUDABI64_SYS_cloudabi64_sys_thread_create 53 #define CLOUDABI64_SYS_cloudabi_sys_thread_exit 54 -#define CLOUDABI64_SYS_cloudabi64_sys_thread_tcb_set 55 +#define CLOUDABI64_SYS_cloudabi_sys_thread_tcb_set 55 #define CLOUDABI64_SYS_cloudabi_sys_thread_yield 56 #define CLOUDABI64_SYS_MAXSYSCALL 57 diff --git a/sys/compat/cloudabi64/cloudabi64_syscalls.c b/sys/compat/cloudabi64/cloudabi64_syscalls.c index f8fe811fb48d..e92fa14c23f8 100644 --- a/sys/compat/cloudabi64/cloudabi64_syscalls.c +++ b/sys/compat/cloudabi64/cloudabi64_syscalls.c @@ -3,7 +3,7 @@ * * DO NOT EDIT-- this file is automatically generated. * $FreeBSD$ - * created from FreeBSD: head/sys/compat/cloudabi64/syscalls.master 285307 2015-07-09 07:20:15Z ed + * created from FreeBSD: head/sys/compat/cloudabi64/syscalls.master 285790 2015-07-22 10:04:53Z ed */ const char *cloudabi64_syscallnames[] = { @@ -62,6 +62,6 @@ const char *cloudabi64_syscallnames[] = { "cloudabi_sys_sock_stat_get", /* 52 = cloudabi_sys_sock_stat_get */ "cloudabi64_sys_thread_create", /* 53 = cloudabi64_sys_thread_create */ "cloudabi_sys_thread_exit", /* 54 = cloudabi_sys_thread_exit */ - "cloudabi64_sys_thread_tcb_set", /* 55 = cloudabi64_sys_thread_tcb_set */ + "cloudabi_sys_thread_tcb_set", /* 55 = cloudabi_sys_thread_tcb_set */ "cloudabi_sys_thread_yield", /* 56 = cloudabi_sys_thread_yield */ }; diff --git a/sys/compat/cloudabi64/cloudabi64_sysent.c b/sys/compat/cloudabi64/cloudabi64_sysent.c index ccfb95be30ae..380d0fa73ce9 100644 --- a/sys/compat/cloudabi64/cloudabi64_sysent.c +++ b/sys/compat/cloudabi64/cloudabi64_sysent.c @@ -3,7 +3,7 @@ * * DO NOT EDIT-- this file is automatically generated. * $FreeBSD$ - * created from FreeBSD: head/sys/compat/cloudabi64/syscalls.master 285307 2015-07-09 07:20:15Z ed + * created from FreeBSD: head/sys/compat/cloudabi64/syscalls.master 285790 2015-07-22 10:04:53Z ed */ #include @@ -70,6 +70,6 @@ struct sysent cloudabi64_sysent[] = { { AS(cloudabi_sys_sock_stat_get_args), (sy_call_t *)cloudabi_sys_sock_stat_get, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC }, /* 52 = cloudabi_sys_sock_stat_get */ { AS(cloudabi64_sys_thread_create_args), (sy_call_t *)cloudabi64_sys_thread_create, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC }, /* 53 = cloudabi64_sys_thread_create */ { AS(cloudabi_sys_thread_exit_args), (sy_call_t *)cloudabi_sys_thread_exit, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC }, /* 54 = cloudabi_sys_thread_exit */ - { AS(cloudabi64_sys_thread_tcb_set_args), (sy_call_t *)cloudabi64_sys_thread_tcb_set, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC }, /* 55 = cloudabi64_sys_thread_tcb_set */ + { AS(cloudabi_sys_thread_tcb_set_args), (sy_call_t *)cloudabi_sys_thread_tcb_set, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC }, /* 55 = cloudabi_sys_thread_tcb_set */ { 0, (sy_call_t *)cloudabi_sys_thread_yield, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC }, /* 56 = cloudabi_sys_thread_yield */ }; diff --git a/sys/compat/cloudabi64/cloudabi64_systrace_args.c b/sys/compat/cloudabi64/cloudabi64_systrace_args.c index 0084cad83d51..9c3241226e40 100644 --- a/sys/compat/cloudabi64/cloudabi64_systrace_args.c +++ b/sys/compat/cloudabi64/cloudabi64_systrace_args.c @@ -30,8 +30,9 @@ systrace_args(int sysnum, void *params, uint64_t *uarg, int *n_args) case 2: { struct cloudabi_sys_condvar_signal_args *p = params; uarg[0] = (intptr_t) p->condvar; /* cloudabi_condvar_t * */ - iarg[1] = p->nwaiters; /* cloudabi_nthreads_t */ - *n_args = 2; + iarg[1] = p->scope; /* cloudabi_futexscope_t */ + iarg[2] = p->nwaiters; /* cloudabi_nthreads_t */ + *n_args = 3; break; } /* cloudabi_sys_fd_close */ @@ -296,7 +297,8 @@ systrace_args(int sysnum, void *params, uint64_t *uarg, int *n_args) case 31: { struct cloudabi_sys_lock_unlock_args *p = params; uarg[0] = (intptr_t) p->lock; /* cloudabi_lock_t * */ - *n_args = 1; + iarg[1] = p->scope; /* cloudabi_futexscope_t */ + *n_args = 2; break; } /* cloudabi_sys_mem_advise */ @@ -493,12 +495,13 @@ systrace_args(int sysnum, void *params, uint64_t *uarg, int *n_args) case 54: { struct cloudabi_sys_thread_exit_args *p = params; uarg[0] = (intptr_t) p->lock; /* cloudabi_lock_t * */ - *n_args = 1; + iarg[1] = p->scope; /* cloudabi_futexscope_t */ + *n_args = 2; break; } - /* cloudabi64_sys_thread_tcb_set */ + /* cloudabi_sys_thread_tcb_set */ case 55: { - struct cloudabi64_sys_thread_tcb_set_args *p = params; + struct cloudabi_sys_thread_tcb_set_args *p = params; uarg[0] = (intptr_t) p->tcb; /* void * */ *n_args = 1; break; @@ -548,6 +551,9 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz) p = "cloudabi_condvar_t *"; break; case 1: + p = "cloudabi_futexscope_t"; + break; + case 2: p = "cloudabi_nthreads_t"; break; default: @@ -1026,6 +1032,9 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz) case 0: p = "cloudabi_lock_t *"; break; + case 1: + p = "cloudabi_futexscope_t"; + break; default: break; }; @@ -1363,11 +1372,14 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz) case 0: p = "cloudabi_lock_t *"; break; + case 1: + p = "cloudabi_futexscope_t"; + break; default: break; }; break; - /* cloudabi64_sys_thread_tcb_set */ + /* cloudabi_sys_thread_tcb_set */ case 55: switch(ndx) { case 0: @@ -1663,7 +1675,7 @@ systrace_return_setargdesc(int sysnum, int ndx, char *desc, size_t descsz) if (ndx == 0 || ndx == 1) p = "void"; break; - /* cloudabi64_sys_thread_tcb_set */ + /* cloudabi_sys_thread_tcb_set */ case 55: if (ndx == 0 || ndx == 1) p = "void"; diff --git a/sys/compat/cloudabi64/cloudabi64_thread.c b/sys/compat/cloudabi64/cloudabi64_thread.c index a77d6e226d02..04b1782329b9 100644 --- a/sys/compat/cloudabi64/cloudabi64_thread.c +++ b/sys/compat/cloudabi64/cloudabi64_thread.c @@ -26,23 +26,45 @@ #include __FBSDID("$FreeBSD$"); +#include +#include +#include + #include #include +#include + +struct thread_create_args { + cloudabi64_threadattr_t attr; + lwpid_t tid; +}; + +static int +initialize_thread(struct thread *td, void *thunk) +{ + struct thread_create_args *args = thunk; + + /* Save the thread ID, so it can be returned. */ + args->tid = td->td_tid; + + /* Set up initial register contents. */ + cloudabi64_thread_setregs(td, &args->attr); + return (0); +} int cloudabi64_sys_thread_create(struct thread *td, struct cloudabi64_sys_thread_create_args *uap) { + struct thread_create_args args; + int error; - /* Not implemented. */ - return (ENOSYS); -} - -int -cloudabi64_sys_thread_tcb_set(struct thread *td, - struct cloudabi64_sys_thread_tcb_set_args *uap) -{ - - /* Not implemented. */ - return (ENOSYS); + error = copyin(uap->attr, &args.attr, sizeof(args.attr)); + if (error != 0) + return (error); + error = thread_create(td, NULL, initialize_thread, &args); + if (error != 0) + return (error); + td->td_retval[0] = args.tid; + return (0); } diff --git a/usr.sbin/pw/fileupd.c b/sys/compat/cloudabi64/cloudabi64_util.h similarity index 67% rename from usr.sbin/pw/fileupd.c rename to sys/compat/cloudabi64/cloudabi64_util.h index dc327123a0fd..c56d4ccd25d0 100644 --- a/usr.sbin/pw/fileupd.c +++ b/sys/compat/cloudabi64/cloudabi64_util.h @@ -1,6 +1,5 @@ /*- - * Copyright (C) 1996 - * David L. Nugent. All rights reserved. + * Copyright (c) 2015 Nuxi, https://nuxi.nl/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -11,10 +10,10 @@ * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * - * THIS SOFTWARE IS PROVIDED BY DAVID L. NUGENT AND CONTRIBUTORS ``AS IS'' AND + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL DAVID L. NUGENT OR CONTRIBUTORS BE LIABLE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) @@ -22,26 +21,18 @@ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. + * + * $FreeBSD$ */ -#ifndef lint -static const char rcsid[] = - "$FreeBSD$"; -#endif /* not lint */ +#ifndef _CLOUDABI64_UTIL_H_ +#define _CLOUDABI64_UTIL_H_ -#include +#include -#include "pwupd.h" +struct thread; -int -extendarray(char ***buf, int * buflen, int needed) -{ - if (needed > *buflen) { - char **tmp = realloc(*buf, needed * sizeof(char *)); - if (tmp == NULL) - return -1; - *buf = tmp; - *buflen = needed; - } - return *buflen; -} +void cloudabi64_thread_setregs(struct thread *, + const cloudabi64_threadattr_t *); + +#endif diff --git a/sys/compat/cloudabi64/syscalls.master b/sys/compat/cloudabi64/syscalls.master index 42a74ca71d7c..ba1df9a4fa21 100644 --- a/sys/compat/cloudabi64/syscalls.master +++ b/sys/compat/cloudabi64/syscalls.master @@ -21,6 +21,7 @@ 2 AUE_NULL STD { void cloudabi_sys_condvar_signal( \ cloudabi_condvar_t *condvar, \ + cloudabi_futexscope_t scope, \ cloudabi_nthreads_t nwaiters); } 3 AUE_NULL STD { void cloudabi_sys_fd_close( \ @@ -130,7 +131,8 @@ cloudabi_ulflags_t flag); } 31 AUE_NULL STD { void cloudabi_sys_lock_unlock( \ - cloudabi_lock_t *lock); } + cloudabi_lock_t *lock, \ + cloudabi_futexscope_t scope); } 32 AUE_NULL STD { void cloudabi_sys_mem_advise( \ void *addr, size_t len, \ @@ -206,7 +208,7 @@ 53 AUE_NULL STD { cloudabi_tid_t cloudabi64_sys_thread_create( \ cloudabi64_threadattr_t *attr); } 54 AUE_NULL STD { void cloudabi_sys_thread_exit( \ - cloudabi_lock_t *lock); } -55 AUE_NULL STD { void cloudabi64_sys_thread_tcb_set( \ - void *tcb); } + cloudabi_lock_t *lock, \ + cloudabi_futexscope_t scope); } +55 AUE_NULL STD { void cloudabi_sys_thread_tcb_set(void *tcb); } 56 AUE_NULL STD { void cloudabi_sys_thread_yield(); } diff --git a/sys/compat/freebsd32/freebsd32_syscall.h b/sys/compat/freebsd32/freebsd32_syscall.h index 5e5bb0ad6ed7..91bf4b7b4503 100644 --- a/sys/compat/freebsd32/freebsd32_syscall.h +++ b/sys/compat/freebsd32/freebsd32_syscall.h @@ -455,4 +455,6 @@ #define FREEBSD32_SYS_freebsd32_ppoll 545 #define FREEBSD32_SYS_freebsd32_futimens 546 #define FREEBSD32_SYS_freebsd32_utimensat 547 -#define FREEBSD32_SYS_MAXSYSCALL 548 +#define FREEBSD32_SYS_numa_getaffinity 548 +#define FREEBSD32_SYS_numa_setaffinity 549 +#define FREEBSD32_SYS_MAXSYSCALL 550 diff --git a/sys/compat/freebsd32/freebsd32_syscalls.c b/sys/compat/freebsd32/freebsd32_syscalls.c index 143ed72107e6..5b5b52f144f4 100644 --- a/sys/compat/freebsd32/freebsd32_syscalls.c +++ b/sys/compat/freebsd32/freebsd32_syscalls.c @@ -581,4 +581,6 @@ const char *freebsd32_syscallnames[] = { "freebsd32_ppoll", /* 545 = freebsd32_ppoll */ "freebsd32_futimens", /* 546 = freebsd32_futimens */ "freebsd32_utimensat", /* 547 = freebsd32_utimensat */ + "numa_getaffinity", /* 548 = numa_getaffinity */ + "numa_setaffinity", /* 549 = numa_setaffinity */ }; diff --git a/sys/compat/freebsd32/freebsd32_sysent.c b/sys/compat/freebsd32/freebsd32_sysent.c index 6d2a7d48bd3a..14d357cd2f3a 100644 --- a/sys/compat/freebsd32/freebsd32_sysent.c +++ b/sys/compat/freebsd32/freebsd32_sysent.c @@ -618,4 +618,6 @@ struct sysent freebsd32_sysent[] = { { AS(freebsd32_ppoll_args), (sy_call_t *)freebsd32_ppoll, AUE_POLL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 545 = freebsd32_ppoll */ { AS(freebsd32_futimens_args), (sy_call_t *)freebsd32_futimens, AUE_FUTIMES, NULL, 0, 0, 0, SY_THR_STATIC }, /* 546 = freebsd32_futimens */ { AS(freebsd32_utimensat_args), (sy_call_t *)freebsd32_utimensat, AUE_FUTIMESAT, NULL, 0, 0, 0, SY_THR_STATIC }, /* 547 = freebsd32_utimensat */ + { AS(numa_getaffinity_args), (sy_call_t *)sys_numa_getaffinity, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 548 = numa_getaffinity */ + { AS(numa_setaffinity_args), (sy_call_t *)sys_numa_setaffinity, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 549 = numa_setaffinity */ }; diff --git a/sys/compat/freebsd32/freebsd32_systrace_args.c b/sys/compat/freebsd32/freebsd32_systrace_args.c index a2668aa7cb05..26e7a6d017a4 100644 --- a/sys/compat/freebsd32/freebsd32_systrace_args.c +++ b/sys/compat/freebsd32/freebsd32_systrace_args.c @@ -3327,6 +3327,24 @@ systrace_args(int sysnum, void *params, uint64_t *uarg, int *n_args) *n_args = 4; break; } + /* numa_getaffinity */ + case 548: { + struct numa_getaffinity_args *p = params; + iarg[0] = p->which; /* cpuwhich_t */ + iarg[1] = p->id; /* id_t */ + uarg[2] = (intptr_t) p->policy; /* struct vm_domain_policy * */ + *n_args = 3; + break; + } + /* numa_setaffinity */ + case 549: { + struct numa_setaffinity_args *p = params; + iarg[0] = p->which; /* cpuwhich_t */ + iarg[1] = p->id; /* id_t */ + uarg[2] = (intptr_t) p->policy; /* const struct vm_domain_policy * */ + *n_args = 3; + break; + } default: *n_args = 0; break; @@ -8923,6 +8941,38 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz) break; }; break; + /* numa_getaffinity */ + case 548: + switch(ndx) { + case 0: + p = "cpuwhich_t"; + break; + case 1: + p = "id_t"; + break; + case 2: + p = "struct vm_domain_policy *"; + break; + default: + break; + }; + break; + /* numa_setaffinity */ + case 549: + switch(ndx) { + case 0: + p = "cpuwhich_t"; + break; + case 1: + p = "id_t"; + break; + case 2: + p = "const struct vm_domain_policy *"; + break; + default: + break; + }; + break; default: break; }; @@ -10811,6 +10861,16 @@ systrace_return_setargdesc(int sysnum, int ndx, char *desc, size_t descsz) if (ndx == 0 || ndx == 1) p = "int"; break; + /* numa_getaffinity */ + case 548: + if (ndx == 0 || ndx == 1) + p = "int"; + break; + /* numa_setaffinity */ + case 549: + if (ndx == 0 || ndx == 1) + p = "int"; + break; default: break; }; diff --git a/sys/compat/freebsd32/syscalls.master b/sys/compat/freebsd32/syscalls.master index 91d1727a7f98..23c28263c575 100644 --- a/sys/compat/freebsd32/syscalls.master +++ b/sys/compat/freebsd32/syscalls.master @@ -1074,3 +1074,9 @@ 547 AUE_FUTIMESAT STD { int freebsd32_utimensat(int fd, \ char *path, \ struct timespec *times, int flag); } +548 AUE_NULL NOPROTO { int numa_getaffinity(cpuwhich_t which, \ + id_t id, \ + struct vm_domain_policy *policy); } +549 AUE_NULL NOPROTO { int numa_setaffinity(cpuwhich_t which, \ + id_t id, \ + const struct vm_domain_policy *policy); } diff --git a/sys/compat/linprocfs/linprocfs.c b/sys/compat/linprocfs/linprocfs.c index 25a832586c01..496afba8fcf6 100644 --- a/sys/compat/linprocfs/linprocfs.c +++ b/sys/compat/linprocfs/linprocfs.c @@ -873,10 +873,20 @@ linprocfs_doprocstatus(PFS_FILL_ARGS) static int linprocfs_doproccwd(PFS_FILL_ARGS) { + struct filedesc *fdp; + struct vnode *vp; char *fullpath = "unknown"; char *freepath = NULL; - vn_fullpath(td, p->p_fd->fd_cdir, &fullpath, &freepath); + fdp = p->p_fd; + FILEDESC_SLOCK(fdp); + vp = fdp->fd_cdir; + if (vp != NULL) + VREF(vp); + FILEDESC_SUNLOCK(fdp); + vn_fullpath(td, vp, &fullpath, &freepath); + if (vp != NULL) + vrele(vp); sbuf_printf(sb, "%s", fullpath); if (freepath) free(freepath, M_TEMP); @@ -889,12 +899,20 @@ linprocfs_doproccwd(PFS_FILL_ARGS) static int linprocfs_doprocroot(PFS_FILL_ARGS) { - struct vnode *rvp; + struct filedesc *fdp; + struct vnode *vp; char *fullpath = "unknown"; char *freepath = NULL; - rvp = jailed(p->p_ucred) ? p->p_fd->fd_jdir : p->p_fd->fd_rdir; - vn_fullpath(td, rvp, &fullpath, &freepath); + fdp = p->p_fd; + FILEDESC_SLOCK(fdp); + vp = jailed(p->p_ucred) ? fdp->fd_jdir : fdp->fd_rdir; + if (vp != NULL) + VREF(vp); + FILEDESC_SUNLOCK(fdp); + vn_fullpath(td, vp, &fullpath, &freepath); + if (vp != NULL) + vrele(vp); sbuf_printf(sb, "%s", fullpath); if (freepath) free(freepath, M_TEMP); @@ -1530,7 +1548,7 @@ linprocfs_uninit(PFS_INIT_ARGS) return (0); } -PSEUDOFS(linprocfs, 1, 0); +PSEUDOFS(linprocfs, 1, PR_ALLOW_MOUNT_LINPROCFS); #if defined(__amd64__) MODULE_DEPEND(linprocfs, linux_common, 1, 1, 1); #else diff --git a/sys/compat/linsysfs/linsysfs.c b/sys/compat/linsysfs/linsysfs.c index bc85ac354eb6..0d5273c0ba5d 100644 --- a/sys/compat/linsysfs/linsysfs.c +++ b/sys/compat/linsysfs/linsysfs.c @@ -275,7 +275,7 @@ linsysfs_uninit(PFS_INIT_ARGS) return (0); } -PSEUDOFS(linsysfs, 1, 0); +PSEUDOFS(linsysfs, 1, PR_ALLOW_MOUNT_LINSYSFS); #if defined(__amd64__) MODULE_DEPEND(linsysfs, linux_common, 1, 1, 1); #else diff --git a/sys/compat/linux/linux_fork.c b/sys/compat/linux/linux_fork.c index 394c26fffa5f..6b3749009bcf 100644 --- a/sys/compat/linux/linux_fork.c +++ b/sys/compat/linux/linux_fork.c @@ -398,7 +398,7 @@ linux_exit(struct thread *td, struct linux_exit_args *args) * exit via pthread_exit() try thr_exit() first. */ kern_thr_exit(td); - exit1(td, W_EXITCODE(args->rval, 0)); + exit1(td, args->rval, 0); /* NOTREACHED */ } diff --git a/sys/compat/linux/linux_misc.c b/sys/compat/linux/linux_misc.c index fa5feaf01daf..ccb618c51edf 100644 --- a/sys/compat/linux/linux_misc.c +++ b/sys/compat/linux/linux_misc.c @@ -1839,7 +1839,7 @@ linux_exit_group(struct thread *td, struct linux_exit_group_args *args) * SIGNAL_EXIT_GROUP is set. We ignore that (temporarily?) * as it doesnt occur often. */ - exit1(td, W_EXITCODE(args->error_code, 0)); + exit1(td, args->error_code, 0); /* NOTREACHED */ } diff --git a/sys/compat/ndis/subr_ndis.c b/sys/compat/ndis/subr_ndis.c index f3ba70084119..ac26a2e093fc 100644 --- a/sys/compat/ndis/subr_ndis.c +++ b/sys/compat/ndis/subr_ndis.c @@ -2817,10 +2817,7 @@ NdisOpenFile(status, filehandle, filelength, filename, highestaddr) /* Some threads don't have a current working directory. */ - if (td->td_proc->p_fd->fd_rdir == NULL) - td->td_proc->p_fd->fd_rdir = rootvnode; - if (td->td_proc->p_fd->fd_cdir == NULL) - td->td_proc->p_fd->fd_cdir = rootvnode; + pwd_ensure_dirs(); NDINIT(&nd, LOOKUP, FOLLOW, UIO_SYSSPACE, path, td); diff --git a/sys/compat/svr4/svr4_misc.c b/sys/compat/svr4/svr4_misc.c index ec4504e7f96f..b560764ca8e2 100644 --- a/sys/compat/svr4/svr4_misc.c +++ b/sys/compat/svr4/svr4_misc.c @@ -643,7 +643,7 @@ svr4_sys_fchroot(td, uap) goto fail; #endif VOP_UNLOCK(vp, 0); - error = change_root(vp, td); + error = pwd_chroot(td, vp); vrele(vp); return (error); fail: @@ -1277,7 +1277,7 @@ loop: /* Found a zombie, so cache info in local variables. */ pid = p->p_pid; - status = p->p_xstat; + status = KW_EXITCODE(p->p_xexit, p->p_xsig); ru = p->p_ru; PROC_STATLOCK(p); calcru(p, &ru.ru_utime, &ru.ru_stime); @@ -1304,7 +1304,7 @@ loop: p->p_flag |= P_WAITED; sx_sunlock(&proctree_lock); pid = p->p_pid; - status = W_STOPCODE(p->p_xstat); + status = W_STOPCODE(p->p_xsig); ru = p->p_ru; PROC_STATLOCK(p); calcru(p, &ru.ru_utime, &ru.ru_stime); diff --git a/sys/conf/NOTES b/sys/conf/NOTES index 5bbc29e97dad..b0619cbc4469 100644 --- a/sys/conf/NOTES +++ b/sys/conf/NOTES @@ -997,8 +997,7 @@ options ACCEPT_FILTER_HTTP # carried in TCP option 19. This option is commonly used to protect # TCP sessions (e.g. BGP) where IPSEC is not available nor desirable. # This is enabled on a per-socket basis using the TCP_MD5SIG socket option. -# This requires the use of 'device crypto', 'options IPSEC' -# or 'device cryptodev'. +# This requires the use of 'device crypto' and 'options IPSEC'. options TCP_SIGNATURE #include support for RFC 2385 # DUMMYNET enables the "dummynet" bandwidth limiter. You need IPFIREWALL @@ -2817,6 +2816,10 @@ options DCONS_FORCE_GDB=1 # force to be the gdb device # been fed back to OpenBSD. device crypto # core crypto support + +# Only install the cryptodev device if you are running tests, or know +# specifically why you need it. In most cases, it is not needed and +# will make things slower. device cryptodev # /dev/crypto for access to h/w device rndtest # FIPS 140-2 entropy tester @@ -2978,9 +2981,11 @@ options MAXFILES=999 # Random number generator # Only ONE of the below two may be used; they are mutually exclusive. -options RANDOM_YARROW # Yarrow CSPRNG (Default) -#options RANDOM_FORTUNA # Fortuna CSPRNG -options RANDOM_DEBUG # Debugging messages +# If neither is present, then the Fortuna algorithm is used. +options RANDOM_YARROW # Yarrow CSPRNG (old default) +#options RANDOM_DUMMY # Dummy CSPRNG that always blocks +# For developers. +options RANDOM_DEBUG # Extra debugging messages # Module to enable execution of application via emulators like QEMU options IMAGACT_BINMISC diff --git a/sys/conf/files b/sys/conf/files index e2fdfc8664a2..65cf92322332 100644 --- a/sys/conf/files +++ b/sys/conf/files @@ -246,7 +246,6 @@ cddl/contrib/opensolaris/uts/common/zmod/zutil.c optional zfs compile-with "${ cddl/contrib/opensolaris/uts/common/dtrace/dtrace.c optional dtrace compile-with "${DTRACE_C}" \ warning "kernel contains CDDL licensed DTRACE" cddl/dev/dtmalloc/dtmalloc.c optional dtmalloc | dtraceall compile-with "${CDDL_C}" -cddl/dev/lockstat/lockstat.c optional dtrace_lockstat | dtraceall compile-with "${CDDL_C}" cddl/dev/profile/profile.c optional dtrace_profile | dtraceall compile-with "${CDDL_C}" cddl/dev/sdt/sdt.c optional dtrace_sdt | dtraceall compile-with "${CDDL_C}" cddl/dev/fbt/fbt.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}" @@ -254,6 +253,7 @@ cddl/dev/systrace/systrace.c optional dtrace_systrace | dtraceall compile-with cddl/dev/prototype.c optional dtrace_prototype | dtraceall compile-with "${CDDL_C}" fs/nfsclient/nfs_clkdtrace.c optional dtnfscl nfscl | dtraceall nfscl compile-with "${CDDL_C}" compat/cloudabi/cloudabi_clock.c optional compat_cloudabi64 +compat/cloudabi/cloudabi_errno.c optional compat_cloudabi64 compat/cloudabi/cloudabi_fd.c optional compat_cloudabi64 compat/cloudabi/cloudabi_file.c optional compat_cloudabi64 compat/cloudabi/cloudabi_futex.c optional compat_cloudabi64 @@ -1201,7 +1201,7 @@ t4fw.fwo optional cxgbe \ no-implicit-rule \ clean "t4fw.fwo" t4fw.fw optional cxgbe \ - dependency "$S/dev/cxgbe/firmware/t4fw-1.11.27.0.bin.uu" \ + dependency "$S/dev/cxgbe/firmware/t4fw-1.14.2.0.bin.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "t4fw.fw" @@ -1225,7 +1225,7 @@ t5fw.fwo optional cxgbe \ no-implicit-rule \ clean "t5fw.fwo" t5fw.fw optional cxgbe \ - dependency "$S/dev/cxgbe/firmware/t5fw-1.11.27.0.bin.uu" \ + dependency "$S/dev/cxgbe/firmware/t5fw-1.14.2.0.bin.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "t5fw.fw" @@ -2068,6 +2068,102 @@ dev/pdq/if_fea.c optional fea eisa dev/pdq/if_fpa.c optional fpa pci dev/pdq/pdq.c optional nowerror fea eisa | fpa pci dev/pdq/pdq_ifsubr.c optional nowerror fea eisa | fpa pci +dev/pms/freebsd/driver/ini/src/agtiapi.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/sallsdk/spc/sadisc.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/sallsdk/spc/mpi.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/sallsdk/spc/saframe.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/sallsdk/spc/sahw.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/sallsdk/spc/sainit.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/sallsdk/spc/saint.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/sallsdk/spc/sampicmd.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/sallsdk/spc/sampirsp.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/sallsdk/spc/saphy.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/sallsdk/spc/saport.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/sallsdk/spc/sasata.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/sallsdk/spc/sasmp.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/sallsdk/spc/sassp.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/sallsdk/spc/satimer.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/sallsdk/spc/sautil.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/sallsdk/spc/saioctlcmd.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/sallsdk/spc/mpidebug.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/discovery/dm/dminit.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/discovery/dm/dmsmp.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/discovery/dm/dmdisc.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/discovery/dm/dmport.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/discovery/dm/dmtimer.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/discovery/dm/dmmisc.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/sat/src/sminit.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/sat/src/smmisc.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/sat/src/smsat.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/sat/src/smsatcb.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/sat/src/smsathw.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/sat/src/smtimer.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/tisa/sassata/common/tdinit.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/tisa/sassata/common/tdmisc.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/tisa/sassata/common/tdesgl.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/tisa/sassata/common/tdport.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/tisa/sassata/common/tdint.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/tisa/sassata/common/tdioctl.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/tisa/sassata/common/tdhw.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/tisa/sassata/common/ossacmnapi.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/tisa/sassata/common/tddmcmnapi.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/tisa/sassata/common/tdsmcmnapi.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/tisa/sassata/common/tdtimers.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/tisa/sassata/sas/ini/itdio.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/tisa/sassata/sas/ini/itdcb.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/tisa/sassata/sas/ini/itdinit.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/tisa/sassata/sas/ini/itddisc.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/tisa/sassata/sata/host/sat.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/tisa/sassata/sata/host/ossasat.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" +dev/pms/RefTisa/tisa/sassata/sata/host/sathw.c optional pmspcv \ + compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/ppbus/if_plip.c optional plip dev/ppbus/immio.c optional vpo dev/ppbus/lpbb.c optional lpbb @@ -2630,9 +2726,11 @@ dev/vt/hw/efifb/efifb.c optional vt_efifb dev/vt/hw/fb/vt_fb.c optional vt dev/vt/hw/vga/vt_vga.c optional vt vt_vga dev/vt/logo/logo_freebsd.c optional vt splash +dev/vt/logo/logo_beastie.c optional vt splash dev/vt/vt_buf.c optional vt dev/vt/vt_consolectl.c optional vt dev/vt/vt_core.c optional vt +dev/vt/vt_cpulogos.c optional vt splash dev/vt/vt_font.c optional vt dev/vt/vt_sysmouse.c optional vt dev/vte/if_vte.c optional vte pci @@ -3017,6 +3115,7 @@ kern/kern_module.c standard kern/kern_mtxpool.c standard kern/kern_mutex.c standard kern/kern_ntptime.c standard +kern/kern_numa.c standard kern/kern_osd.c standard kern/kern_physio.c standard kern/kern_pmc.c standard @@ -4043,6 +4142,7 @@ vm/vm_pager.c standard vm/vm_phys.c standard vm/vm_radix.c standard vm/vm_reserv.c standard +vm/vm_domain.c standard vm/vm_unix.c standard vm/vm_zeroidle.c standard vm/vnode_pager.c standard diff --git a/sys/conf/files.amd64 b/sys/conf/files.amd64 index 08fb59b50aa4..2cfb1b2fc140 100644 --- a/sys/conf/files.amd64 +++ b/sys/conf/files.amd64 @@ -137,6 +137,7 @@ amd64/amd64/trap.c standard amd64/amd64/uio_machdep.c standard amd64/amd64/uma_machdep.c standard amd64/amd64/vm_machdep.c standard +amd64/cloudabi64/cloudabi64_sysvec.c optional compat_cloudabi64 amd64/pci/pci_cfgreg.c optional pci cddl/contrib/opensolaris/common/atomic/amd64/opensolaris_atomic.S optional zfs | dtrace compile-with "${ZFS_S}" cddl/dev/dtrace/amd64/dtrace_asm.S optional dtrace compile-with "${DTRACE_S}" diff --git a/sys/conf/files.arm64 b/sys/conf/files.arm64 index d63594e16392..92a422d4a1bf 100644 --- a/sys/conf/files.arm64 +++ b/sys/conf/files.arm64 @@ -5,6 +5,7 @@ arm/arm/pmu.c standard arm64/acpica/acpi_machdep.c optional acpi arm64/acpica/OsdEnvironment.c optional acpi arm64/acpica/acpi_wakeup.c optional acpi +arm64/acpica/pci_cfgreg.c optional acpi pci arm64/arm64/autoconf.c standard arm64/arm64/bcopy.c standard arm64/arm64/bus_machdep.c standard diff --git a/sys/contrib/cloudabi/syscalldefs_md.h b/sys/contrib/cloudabi/syscalldefs_md.h index 95dd129aa626..272360edcdbe 100644 --- a/sys/contrib/cloudabi/syscalldefs_md.h +++ b/sys/contrib/cloudabi/syscalldefs_md.h @@ -43,6 +43,19 @@ typedef void IDENT(threadentry_t)(cloudabi_tid_t, PTR(void)); +// Auxiliary vector entry, used to provide paramters on startup. +typedef struct { + uint32_t a_type; + union { + MEMBER(IDENT(size_t)) a_val; + MEMBER(PTR(void)) a_ptr; + }; +} IDENT(auxv_t); +ASSERT_OFFSET(auxv_t, a_type, 0, 0); +ASSERT_OFFSET(auxv_t, a_val, 4, 8); +ASSERT_OFFSET(auxv_t, a_ptr, 4, 8); +ASSERT_SIZE(auxv_t, 8, 16); + typedef struct { MEMBER(PTR(const void)) iov_base; MEMBER(IDENT(size_t)) iov_len; @@ -161,29 +174,6 @@ typedef struct { ASSERT_OFFSET(send_out_t, so_datalen, 0, 0); ASSERT_SIZE(send_out_t, 4, 8); -typedef struct { - MEMBER(PTR(const void)) sd_arg; // Program argument data. - MEMBER(IDENT(size_t)) sd_arglen; // Program argument data size. - - MEMBER(PTR(void)) sd_elf_phdr; // ELF program header. - MEMBER(IDENT(size_t)) sd_elf_phdrlen; // ELF program header length. - - MEMBER(cloudabi_tid_t) sd_thread_id; // Thread ID. - MEMBER(uint64_t) sd_random_seed; // Random seed, used for SSP. - - MEMBER(uint32_t) sd_ncpus; // Number of CPUs. - MEMBER(uint32_t) sd_pagesize; // Page size. -} IDENT(startup_data_t); -ASSERT_OFFSET(startup_data_t, sd_arg, 0, 0); -ASSERT_OFFSET(startup_data_t, sd_arglen, 4, 8); -ASSERT_OFFSET(startup_data_t, sd_elf_phdr, 8, 16); -ASSERT_OFFSET(startup_data_t, sd_elf_phdrlen, 12, 24); -ASSERT_OFFSET(startup_data_t, sd_thread_id, 16, 32); -ASSERT_OFFSET(startup_data_t, sd_random_seed, 24, 40); -ASSERT_OFFSET(startup_data_t, sd_ncpus, 32, 48); -ASSERT_OFFSET(startup_data_t, sd_pagesize, 36, 52); -ASSERT_SIZE(startup_data_t, 40, 56); - typedef struct { MEMBER(cloudabi_userdata_t) userdata; MEMBER(uint16_t) flags; @@ -203,6 +193,8 @@ typedef struct { struct { MEMBER(PTR(_Atomic(cloudabi_condvar_t))) condvar; MEMBER(PTR(_Atomic(cloudabi_lock_t))) lock; + MEMBER(cloudabi_futexscope_t) condvar_scope; + MEMBER(cloudabi_futexscope_t) lock_scope; } condvar; // CLOUDABI_EVENTTYPE_FD_READ and CLOUDABI_EVENTTYPE_FD_WRITE: @@ -216,6 +208,7 @@ typedef struct { // and acquire a read or write lock. struct { MEMBER(PTR(_Atomic(cloudabi_lock_t))) lock; + MEMBER(cloudabi_futexscope_t) lock_scope; } lock; // CLOUDABI_EVENTTYPE_PROC_TERMINATE: Wait for a process to terminate. @@ -233,8 +226,11 @@ ASSERT_OFFSET(subscription_t, clock.timeout, 32, 32); ASSERT_OFFSET(subscription_t, clock.precision, 40, 40); ASSERT_OFFSET(subscription_t, condvar.condvar, 16, 16); ASSERT_OFFSET(subscription_t, condvar.lock, 20, 24); +ASSERT_OFFSET(subscription_t, condvar.condvar_scope, 24, 32); +ASSERT_OFFSET(subscription_t, condvar.lock_scope, 25, 33); ASSERT_OFFSET(subscription_t, fd_readwrite.fd, 16, 16); ASSERT_OFFSET(subscription_t, lock.lock, 16, 16); +ASSERT_OFFSET(subscription_t, lock.lock_scope, 20, 24); ASSERT_OFFSET(subscription_t, proc_terminate.fd, 16, 16); ASSERT_SIZE(subscription_t, 48, 48); diff --git a/sys/contrib/cloudabi/syscalldefs_mi.h b/sys/contrib/cloudabi/syscalldefs_mi.h index 75d79f44564d..23aa58c87a42 100644 --- a/sys/contrib/cloudabi/syscalldefs_mi.h +++ b/sys/contrib/cloudabi/syscalldefs_mi.h @@ -40,6 +40,19 @@ #define CLOUDABI_ADVICE_SEQUENTIAL 5 #define CLOUDABI_ADVICE_WILLNEED 6 +// Auxiliary vector entries. All entries that are also part of the +// x86-64 ABI use the same number. All extensions start at 256. +#define CLOUDABI_AT_ARGDATA 256 +#define CLOUDABI_AT_ARGDATALEN 257 +#define CLOUDABI_AT_CANARY 258 +#define CLOUDABI_AT_CANARYLEN 259 +#define CLOUDABI_AT_NCPUS 260 +#define CLOUDABI_AT_NULL 0 +#define CLOUDABI_AT_PAGESZ 6 +#define CLOUDABI_AT_PHDR 3 +#define CLOUDABI_AT_PHNUM 4 +#define CLOUDABI_AT_TID 261 + // Clocks. #define CLOUDABI_CLOCK_MONOTONIC 1 #define CLOUDABI_CLOCK_PROCESS_CPUTIME_ID 2 @@ -176,6 +189,10 @@ #define CLOUDABI_FILETYPE_SOCKET_STREAM 0x82 #define CLOUDABI_FILETYPE_SYMBOLIC_LINK 0x90 +// Futex object scopes. +#define CLOUDABI_FUTEXSCOPE_GLOBAL 1 +#define CLOUDABI_FUTEXSCOPE_PROCESS_LOCAL 2 + // Read-write lock related constants. #define CLOUDABI_LOCK_UNLOCKED 0 // Lock is unlocked. #define CLOUDABI_LOCK_WRLOCKED 0x40000000 // Lock is write locked. @@ -203,6 +220,9 @@ #define CLOUDABI_MAP_PRIVATE 0x4 #define CLOUDABI_MAP_SHARED 0x8 +// File descriptor that must be passed in when using CLOUDABI_MAP_ANON. +#define CLOUDABI_MAP_ANON_FD 0xffffffff + // msync() flags. #define CLOUDABI_MS_ASYNC 0x1 #define CLOUDABI_MS_INVALIDATE 0x2 @@ -334,6 +354,7 @@ typedef int64_t cloudabi_filedelta_t; // lseek(). typedef uint64_t cloudabi_filesize_t; // ftruncate(), struct stat::st_size. typedef uint8_t cloudabi_filetype_t; // struct stat::st_mode. typedef uint16_t cloudabi_fsflags_t; // file_stat_put(). +typedef uint8_t cloudabi_futexscope_t; // Scope of lock or condition variable. typedef uint64_t cloudabi_inode_t; // struct stat::st_ino. typedef uint32_t cloudabi_linkcount_t; // struct stat::st_nlink. typedef uint32_t cloudabi_lock_t; // pthread_{mutex,rwlock}_*(). diff --git a/sys/crypto/sha2/sha256.h b/sys/crypto/sha2/sha256.h index 80765ef8749d..c828379be5c9 100644 --- a/sys/crypto/sha2/sha256.h +++ b/sys/crypto/sha2/sha256.h @@ -40,6 +40,38 @@ typedef struct SHA256Context { } SHA256_CTX; __BEGIN_DECLS + +/* Ensure libmd symbols do not clash with libcrypto */ + +#ifndef SHA256_Init +#define SHA256_Init _libmd_SHA256_Init +#endif +#ifndef SHA256_Update +#define SHA256_Update _libmd_SHA256_Update +#endif +#ifndef SHA256_Final +#define SHA256_Final _libmd_SHA256_Final +#endif +#ifndef SHA256_End +#define SHA256_End _libmd_SHA256_End +#endif +#ifndef SHA256_File +#define SHA256_File _libmd_SHA256_File +#endif +#ifndef SHA256_FileChunk +#define SHA256_FileChunk _libmd_SHA256_FileChunk +#endif +#ifndef SHA256_Data +#define SHA256_Data _libmd_SHA256_Data +#endif + +#ifndef SHA256_Transform +#define SHA256_Transform _libmd_SHA256_Transform +#endif +#ifndef SHA256_version +#define SHA256_version _libmd_SHA256_version +#endif + void SHA256_Init(SHA256_CTX *); void SHA256_Update(SHA256_CTX *, const void *, size_t); void SHA256_Final(unsigned char [32], SHA256_CTX *); diff --git a/sys/crypto/sha2/sha256c.c b/sys/crypto/sha2/sha256c.c index 9c666df3ee25..da9b02cbd1bf 100644 --- a/sys/crypto/sha2/sha256c.c +++ b/sys/crypto/sha2/sha256c.c @@ -299,3 +299,18 @@ SHA256_Final(unsigned char digest[32], SHA256_CTX * ctx) /* Clear the context state */ memset((void *)ctx, 0, sizeof(*ctx)); } + +#ifdef WEAK_REFS +/* When building libmd, provide weak references. Note: this is not + activated in the context of compiling these sources for internal + use in libcrypt. + */ +#undef SHA256_Init +__weak_reference(_libmd_SHA256_Init, SHA256_Init); +#undef SHA256_Update +__weak_reference(_libmd_SHA256_Update, SHA256_Update); +#undef SHA256_Final +__weak_reference(_libmd_SHA256_Final, SHA256_Final); +#undef SHA256_Transform +__weak_reference(_libmd_SHA256_Transform, SHA256_Transform); +#endif diff --git a/sys/ddb/db_examine.c b/sys/ddb/db_examine.c index d4c5ed47208c..a41fcb5dae69 100644 --- a/sys/ddb/db_examine.c +++ b/sys/ddb/db_examine.c @@ -232,9 +232,13 @@ db_print_cmd(db_expr_t addr, bool have_addr, db_expr_t count, char *modif) void db_print_loc_and_inst(db_addr_t loc) { + db_expr_t off; + db_printsym(loc, DB_STGY_PROC); - db_printf(":\t"); - (void) db_disasm(loc, true); + if (db_search_symbol(loc, DB_STGY_PROC, &off) != C_DB_SYM_NULL) { + db_printf(":\t"); + (void)db_disasm(loc, true); + } } /* diff --git a/sys/ddb/db_main.c b/sys/ddb/db_main.c index 5ef6962ca678..3345bb69eead 100644 --- a/sys/ddb/db_main.c +++ b/sys/ddb/db_main.c @@ -110,7 +110,7 @@ X_db_search_symbol(db_symtab_t *symtab, db_addr_t off, db_strategy_t strat, diff = ~0UL; match = NULL; for (sym = (Elf_Sym*)symtab->start; (char*)sym < symtab->end; sym++) { - if (sym->st_name == 0) + if (sym->st_name == 0 || sym->st_shndx == SHN_UNDEF) continue; if (off < sym->st_value) continue; diff --git a/sys/ddb/db_print.c b/sys/ddb/db_print.c index 95550d15774e..e4efe0a560d7 100644 --- a/sys/ddb/db_print.c +++ b/sys/ddb/db_print.c @@ -56,7 +56,8 @@ db_show_regs(db_expr_t _1, bool _2, db_expr_t _3, char *_4) for (regp = db_regs; regp < db_eregs; regp++) { if (!db_read_variable(regp, &value)) continue; - db_printf("%-12s%#10lr", regp->name, (unsigned long)value); + db_printf("%-12s%#*lr", regp->name, + (int)(sizeof(unsigned long) * 2 + 2), (unsigned long)value); db_find_xtrn_sym_and_offset((db_addr_t)value, &name, &offset); if (name != NULL && offset <= (unsigned long)db_maxoff && offset != value) { diff --git a/sys/ddb/db_ps.c b/sys/ddb/db_ps.c index 3fc7afe5e225..553c22e9e4a9 100644 --- a/sys/ddb/db_ps.c +++ b/sys/ddb/db_ps.c @@ -30,6 +30,8 @@ #include __FBSDID("$FreeBSD$"); +#include "opt_kstack_pages.h" + #include #include #include diff --git a/sys/ddb/db_sym.c b/sys/ddb/db_sym.c index 61c1d5f67dae..ffcba7928476 100644 --- a/sys/ddb/db_sym.c +++ b/sys/ddb/db_sym.c @@ -31,6 +31,8 @@ #include __FBSDID("$FreeBSD$"); +#include "opt_kstack_pages.h" + #include #include #include diff --git a/sys/dev/ahci/ahci.c b/sys/dev/ahci/ahci.c index 5944326bf556..6a2c76665d87 100644 --- a/sys/dev/ahci/ahci.c +++ b/sys/dev/ahci/ahci.c @@ -181,12 +181,12 @@ ahci_attach(device_t dev) ctlr->sc_iomem.rm_type = RMAN_ARRAY; ctlr->sc_iomem.rm_descr = "I/O memory addresses"; if ((error = rman_init(&ctlr->sc_iomem)) != 0) { - bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); + ahci_free_mem(dev); return (error); } if ((error = rman_manage_region(&ctlr->sc_iomem, rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { - bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); + ahci_free_mem(dev); rman_fini(&ctlr->sc_iomem); return (error); } @@ -250,8 +250,7 @@ ahci_attach(device_t dev) BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, 0, NULL, NULL, &ctlr->dma_tag)) { - bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, - ctlr->r_mem); + ahci_free_mem(dev); rman_fini(&ctlr->sc_iomem); return (ENXIO); } @@ -261,8 +260,7 @@ ahci_attach(device_t dev) /* Setup interrupts. */ if ((error = ahci_setup_interrupt(dev)) != 0) { bus_dma_tag_destroy(ctlr->dma_tag); - bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, - ctlr->r_mem); + ahci_free_mem(dev); rman_fini(&ctlr->sc_iomem); return (error); } @@ -367,9 +365,26 @@ ahci_detach(device_t dev) bus_dma_tag_destroy(ctlr->dma_tag); /* Free memory. */ rman_fini(&ctlr->sc_iomem); + ahci_free_mem(dev); + return (0); +} + +void +ahci_free_mem(device_t dev) +{ + struct ahci_controller *ctlr = device_get_softc(dev); + + /* Release memory resources */ if (ctlr->r_mem) bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); - return (0); + if (ctlr->r_msix_table) + bus_release_resource(dev, SYS_RES_MEMORY, + ctlr->r_msix_tab_rid, ctlr->r_msix_table); + if (ctlr->r_msix_pba) + bus_release_resource(dev, SYS_RES_MEMORY, + ctlr->r_msix_pba_rid, ctlr->r_msix_pba); + + ctlr->r_msix_pba = ctlr->r_mem = ctlr->r_msix_table = NULL; } int diff --git a/sys/dev/ahci/ahci.h b/sys/dev/ahci/ahci.h index ac81737cfdda..0461953940f9 100644 --- a/sys/dev/ahci/ahci.h +++ b/sys/dev/ahci/ahci.h @@ -482,11 +482,15 @@ struct ahci_controller { device_t dev; bus_dma_tag_t dma_tag; int r_rid; + int r_msix_tab_rid; + int r_msix_pba_rid; uint16_t vendorid; /* Vendor ID from the bus */ uint16_t deviceid; /* Device ID from the bus */ uint16_t subvendorid; /* Subvendor ID from the bus */ uint16_t subdeviceid; /* Subdevice ID from the bus */ struct resource *r_mem; + struct resource *r_msix_table; + struct resource *r_msix_pba; struct rman sc_iomem; struct ahci_controller_irq { struct ahci_controller *ctlr; @@ -621,3 +625,4 @@ int ahci_child_location_str(device_t dev, device_t child, char *buf, bus_dma_tag_t ahci_get_dma_tag(device_t dev, device_t child); int ahci_ctlr_reset(device_t dev); int ahci_ctlr_setup(device_t dev); +void ahci_free_mem(device_t dev); diff --git a/sys/dev/ahci/ahci_pci.c b/sys/dev/ahci/ahci_pci.c index cdf2196831a6..a8f49a1cc365 100644 --- a/sys/dev/ahci/ahci_pci.c +++ b/sys/dev/ahci/ahci_pci.c @@ -373,6 +373,28 @@ ahci_ata_probe(device_t dev) return (BUS_PROBE_DEFAULT); } +static int +ahci_pci_read_msix_bars(device_t dev, uint8_t *table_bar, uint8_t *pba_bar) +{ + int cap_offset = 0, ret; + uint32_t val; + + if ((table_bar == NULL) || (pba_bar == NULL)) + return (EINVAL); + + ret = pci_find_cap(dev, PCIY_MSIX, &cap_offset); + if (ret != 0) + return (EINVAL); + + val = pci_read_config(dev, cap_offset + PCIR_MSIX_TABLE, 4); + *table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK); + + val = pci_read_config(dev, cap_offset + PCIR_MSIX_PBA, 4); + *pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK); + + return (0); +} + static int ahci_pci_attach(device_t dev) { @@ -380,6 +402,11 @@ ahci_pci_attach(device_t dev) int error, i; uint32_t devid = pci_get_devid(dev); uint8_t revid = pci_get_revid(dev); + int msi_count, msix_count; + uint8_t table_bar = 0, pba_bar = 0; + + msi_count = pci_msi_count(dev); + msix_count = pci_msix_count(dev); i = 0; while (ahci_ids[i].id != 0 && @@ -406,10 +433,57 @@ ahci_pci_attach(device_t dev) if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &ctlr->r_rid, RF_ACTIVE))) return ENXIO; + + /* Read MSI-x BAR IDs if supported */ + if (msix_count > 0) { + error = ahci_pci_read_msix_bars(dev, &table_bar, &pba_bar); + if (error == 0) { + ctlr->r_msix_tab_rid = table_bar; + ctlr->r_msix_pba_rid = pba_bar; + } else { + /* Failed to read BARs, disable MSI-x */ + msix_count = 0; + } + } + + /* Allocate resources for MSI-x table and PBA */ + if (msix_count > 0) { + /* + * Allocate new MSI-x table only if not + * allocated before. + */ + ctlr->r_msix_table = NULL; + if (ctlr->r_msix_tab_rid != ctlr->r_rid) { + /* Separate BAR for MSI-x */ + ctlr->r_msix_table = bus_alloc_resource_any(dev, SYS_RES_MEMORY, + &ctlr->r_msix_tab_rid, RF_ACTIVE); + if (ctlr->r_msix_table == NULL) { + ahci_free_mem(dev); + return (ENXIO); + } + } + + /* + * Allocate new PBA table only if not + * allocated before. + */ + ctlr->r_msix_pba = NULL; + if ((ctlr->r_msix_pba_rid != ctlr->r_msix_tab_rid) && + (ctlr->r_msix_pba_rid != ctlr->r_rid)) { + /* Separate BAR for PBA */ + ctlr->r_msix_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY, + &ctlr->r_msix_pba_rid, RF_ACTIVE); + if (ctlr->r_msix_pba == NULL) { + ahci_free_mem(dev); + return (ENXIO); + } + } + } + pci_enable_busmaster(dev); /* Reset controller */ if ((error = ahci_pci_ctlr_reset(dev)) != 0) { - bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); + ahci_free_mem(dev); return (error); }; @@ -426,24 +500,51 @@ ahci_pci_attach(device_t dev) resource_int_value(device_get_name(dev), device_get_unit(dev), "msi", &ctlr->msi); ctlr->numirqs = 1; + if (msi_count == 0 && msix_count == 0) + ctlr->msi = 0; if (ctlr->msi < 0) ctlr->msi = 0; - else if (ctlr->msi == 1) - ctlr->msi = min(1, pci_msi_count(dev)); - else if (ctlr->msi > 1) { + else if (ctlr->msi == 1) { + msi_count = min(1, msi_count); + msix_count = min(1, msix_count); + } else if (ctlr->msi > 1) ctlr->msi = 2; - ctlr->numirqs = pci_msi_count(dev); - } - /* Allocate MSI if needed/present. */ - if (ctlr->msi && pci_alloc_msi(dev, &ctlr->numirqs) != 0) { - ctlr->msi = 0; - ctlr->numirqs = 1; + + /* Allocate MSI/MSI-x if needed/present. */ + if (ctlr->msi > 0) { + error = ENXIO; + + /* Try to allocate MSI-x first */ + if (msix_count > 0) { + error = pci_alloc_msix(dev, &msix_count); + if (error == 0) + ctlr->numirqs = msix_count; + } + + /* + * Try to allocate MSI if msi_count is greater than 0 + * and if MSI-x allocation failed. + */ + if ((error != 0) && (msi_count > 0)) { + error = pci_alloc_msi(dev, &msi_count); + if (error == 0) + ctlr->numirqs = msi_count; + } + + /* Both MSI and MSI-x allocations failed */ + if (error != 0) { + ctlr->msi = 0; + device_printf(dev, "Failed to allocate MSI/MSI-x, " + "falling back to INTx\n"); + } } error = ahci_attach(dev); - if (error != 0) - if (ctlr->msi) + if (error != 0) { + if (ctlr->msi > 0) pci_release_msi(dev); + ahci_free_mem(dev); + } return error; } diff --git a/sys/dev/bwn/if_bwn.c b/sys/dev/bwn/if_bwn.c index 823908ad3278..39bd06fadae4 100644 --- a/sys/dev/bwn/if_bwn.c +++ b/sys/dev/bwn/if_bwn.c @@ -10805,7 +10805,7 @@ bwn_rfswitch(void *arg) KASSERT(mac->mac_status >= BWN_MAC_STATUS_STARTED, ("%s: invalid MAC status %d", __func__, mac->mac_status)); - if (mac->mac_phy.rf_rev >= 3 || mac->mac_phy.type == BWN_PHYTYPE_LP) { + if (mac->mac_phy.rev >= 3 || mac->mac_phy.type == BWN_PHYTYPE_LP) { if (!(BWN_READ_4(mac, BWN_RF_HWENABLED_HI) & BWN_RF_HWENABLED_HI_MASK)) cur = 1; diff --git a/sys/dev/cxgbe/adapter.h b/sys/dev/cxgbe/adapter.h index 0ec89e819b39..9390c51064b3 100644 --- a/sys/dev/cxgbe/adapter.h +++ b/sys/dev/cxgbe/adapter.h @@ -233,6 +233,7 @@ struct port_info { uint16_t viid; int16_t xact_addr_filt;/* index of exact MAC address filter */ uint16_t rss_size; /* size of VI's RSS table slice */ + uint16_t rss_base; /* start of VI's RSS table slice */ uint8_t lport; /* associated offload logical port */ int8_t mdio_addr; uint8_t port_type; diff --git a/sys/dev/cxgbe/common/t4_hw.c b/sys/dev/cxgbe/common/t4_hw.c index d140276722c5..7954188b04dd 100644 --- a/sys/dev/cxgbe/common/t4_hw.c +++ b/sys/dev/cxgbe/common/t4_hw.c @@ -5699,6 +5699,7 @@ int __devinit t4_port_init(struct port_info *p, int mbox, int pf, int vf) struct fw_port_cmd c; u16 rss_size; adapter_t *adap = p->adapter; + u32 param, val; memset(&c, 0, sizeof(c)); @@ -5737,6 +5738,17 @@ int __devinit t4_port_init(struct port_info *p, int mbox, int pf, int vf) init_link_config(&p->link_cfg, ntohs(c.u.info.pcap)); + param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | + V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | + V_FW_PARAMS_PARAM_YZ(p->viid); + ret = t4_query_params(adap, mbox, pf, vf, 1, ¶m, &val); + if (ret) + p->rss_base = 0xffff; + else { + /* MPASS((val >> 16) == rss_size); */ + p->rss_base = val & 0xffff; + } + return 0; } diff --git a/sys/dev/cxgbe/firmware/t4fw-1.11.27.0.bin.uu b/sys/dev/cxgbe/firmware/t4fw-1.11.27.0.bin.uu deleted file mode 100644 index 4c26f91527eb..000000000000 --- a/sys/dev/cxgbe/firmware/t4fw-1.11.27.0.bin.uu +++ /dev/null @@ -1,9019 +0,0 @@ -/*- - * Copyright (c) 2014 Chelsio Communications, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ -begin-base64 644 t4fw -AAAD6QELGwAAAQkEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA -AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA -AAAAAAAAAAAAAAAAAAAAAAAAA8wD2wPjAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA -AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA -AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 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b/sys/dev/cxgbe/firmware/t4fw-1.14.2.0.bin.uu @@ -0,0 +1,9486 @@ +/*- + * Copyright (c) 2015 Chelsio Communications, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +begin-base64 644 t4fw +AAAEHQEOAgAAAQkEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAABAAEDwQXAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 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+112,7 @@ # enable TP_OUT_CONFIG.IPIDSPLITMODE reg[0x7d04] = 0x00010000/0x00010000 - reg[0x7dc0] = 0x62f8849 # TP_SHIFT_CNT + reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT # TP_VLAN_PRI_MAP to select filter tuples # filter tuples : fragmentation, mpshittype, macmatch, ethertype, @@ -125,7 +125,7 @@ # Percentage of dynamic memory (in either the EDRAM or external MEM) # to use for TP RX payload - tp_pmrx = 34, 512 + tp_pmrx = 34 # TP RX payload page size tp_pmrx_pagesize = 64K @@ -135,7 +135,7 @@ # Percentage of dynamic memory (in either the EDRAM or external MEM) # to use for TP TX payload - tp_pmtx = 32, 512 + tp_pmtx = 32 # TP TX payload page size tp_pmtx_pagesize = 64K @@ -146,6 +146,9 @@ # TP OFLD MTUs tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600 + # ULPRX iSCSI Page Sizes + reg[0x19168] = 0x04020100 # 64K, 16K, 8K and 4K + # Some "definitions" to make the rest of this a bit more readable. We support # 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets" # per function per port ... @@ -392,7 +395,7 @@ pmask = all # access to all four ports ... nserver = 16 nhash = 2048 - tp_l2t = 1024 + tp_l2t = 1020 protocol = iscsi_initiator_fofld tp_ddp_iscsi = 2 iscsi_ntask = 2048 @@ -413,6 +416,7 @@ cmask = all # access to all channels pmask = all # access to all four ports ... nhash = 2048 + tp_l2t = 4 protocol = fcoe_initiator tp_ddp = 1 fcoe_nfcf = 16 @@ -543,8 +547,8 @@ dcb_app_tlv[2] = 3260, socketnum, 5 [fini] - version = 0x14250012 - checksum = 0x22f592a9 + version = 0x1425001c + checksum = 0x63a652b3 # Total resources used by above allocations: # Virtual Interfaces: 104 diff --git a/sys/dev/cxgbe/firmware/t4fw_interface.h b/sys/dev/cxgbe/firmware/t4fw_interface.h index 417bdae70b3a..bd436681641c 100644 --- a/sys/dev/cxgbe/firmware/t4fw_interface.h +++ b/sys/dev/cxgbe/firmware/t4fw_interface.h @@ -133,6 +133,8 @@ enum fw_wr_opcodes { FW_SCSI_TGT_RSP_WR = 0x37, FW_POFCOE_TCB_WR = 0x42, FW_POFCOE_ULPTX_WR = 0x43, + FW_ISCSI_TX_DATA_WR = 0x45, + FW_PTP_TX_PKT_WR = 0x46, FW_LASTC2E_WR = 0x70 }; @@ -647,10 +649,24 @@ struct fw_eth_tx_pkts_wr { __u8 type; }; +#define S_FW_PTP_TX_PKT_WR_IMMDLEN 0 +#define M_FW_PTP_TX_PKT_WR_IMMDLEN 0x1ff +#define V_FW_PTP_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_PTP_TX_PKT_WR_IMMDLEN) +#define G_FW_PTP_TX_PKT_WR_IMMDLEN(x) \ + (((x) >> S_FW_PTP_TX_PKT_WR_IMMDLEN) & M_FW_PTP_TX_PKT_WR_IMMDLEN) + +struct fw_eth_tx_pkt_ptp_wr { + __be32 op_immdlen; + __be32 equiq_to_len16; + __be64 r3; +}; + enum fw_eth_tx_eo_type { FW_ETH_TX_EO_TYPE_UDPSEG, FW_ETH_TX_EO_TYPE_TCPSEG, FW_ETH_TX_EO_TYPE_NVGRESEG, + FW_ETH_TX_EO_TYPE_VXLANSEG, + FW_ETH_TX_EO_TYPE_GENEVESEG, }; struct fw_eth_tx_eo_wr { @@ -690,6 +706,27 @@ struct fw_eth_tx_eo_wr { __be16 r4; __be32 plen; } nvgreseg; + struct fw_eth_tx_eo_vxlanseg { + __u8 type; + __u8 iphdroffout; + __be16 vxlanhdroff; + __be16 iphdroffin; + __be16 tcphdroffin; + __be16 mss; + __be16 r4; + __be32 plen; + + } vxlanseg; + struct fw_eth_tx_eo_geneveseg { + __u8 type; + __u8 iphdroffout; + __be16 genevehdroff; + __be16 iphdroffin; + __be16 tcphdroffin; + __be16 mss; + __be16 r4; + __be32 plen; + } geneveseg; } u; }; @@ -868,6 +905,8 @@ enum fw_flowc_mnem { FW_FLOWC_MNEM_EOSTATE = 10, FW_FLOWC_MNEM_SCHEDCLASS = 11, FW_FLOWC_MNEM_DCBPRIO = 12, + FW_FLOWC_MNEM_SND_SCALE = 13, + FW_FLOWC_MNEM_RCV_SCALE = 14, }; struct fw_flowc_mnemval { @@ -894,7 +933,7 @@ struct fw_ofld_tx_data_wr { __be32 op_to_immdlen; __be32 flowid_len16; __be32 plen; - __be32 lsodisable_to_proxy; + __be32 lsodisable_to_flags; }; #define S_FW_OFLD_TX_DATA_WR_LSODISABLE 31 @@ -924,68 +963,67 @@ struct fw_ofld_tx_data_wr { #define F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE \ V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(1U) -#define S_FW_OFLD_TX_DATA_WR_TUNNEL 19 -#define M_FW_OFLD_TX_DATA_WR_TUNNEL 0x1 -#define V_FW_OFLD_TX_DATA_WR_TUNNEL(x) ((x) << S_FW_OFLD_TX_DATA_WR_TUNNEL) -#define G_FW_OFLD_TX_DATA_WR_TUNNEL(x) \ - (((x) >> S_FW_OFLD_TX_DATA_WR_TUNNEL) & M_FW_OFLD_TX_DATA_WR_TUNNEL) -#define F_FW_OFLD_TX_DATA_WR_TUNNEL V_FW_OFLD_TX_DATA_WR_TUNNEL(1U) +#define S_FW_OFLD_TX_DATA_WR_FLAGS 0 +#define M_FW_OFLD_TX_DATA_WR_FLAGS 0xfffffff +#define V_FW_OFLD_TX_DATA_WR_FLAGS(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLAGS) +#define G_FW_OFLD_TX_DATA_WR_FLAGS(x) \ + (((x) >> S_FW_OFLD_TX_DATA_WR_FLAGS) & M_FW_OFLD_TX_DATA_WR_FLAGS) -#define S_FW_OFLD_TX_DATA_WR_SAVE 18 -#define M_FW_OFLD_TX_DATA_WR_SAVE 0x1 -#define V_FW_OFLD_TX_DATA_WR_SAVE(x) ((x) << S_FW_OFLD_TX_DATA_WR_SAVE) -#define G_FW_OFLD_TX_DATA_WR_SAVE(x) \ - (((x) >> S_FW_OFLD_TX_DATA_WR_SAVE) & M_FW_OFLD_TX_DATA_WR_SAVE) -#define F_FW_OFLD_TX_DATA_WR_SAVE V_FW_OFLD_TX_DATA_WR_SAVE(1U) -#define S_FW_OFLD_TX_DATA_WR_FLUSH 17 -#define M_FW_OFLD_TX_DATA_WR_FLUSH 0x1 -#define V_FW_OFLD_TX_DATA_WR_FLUSH(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLUSH) -#define G_FW_OFLD_TX_DATA_WR_FLUSH(x) \ - (((x) >> S_FW_OFLD_TX_DATA_WR_FLUSH) & M_FW_OFLD_TX_DATA_WR_FLUSH) -#define F_FW_OFLD_TX_DATA_WR_FLUSH V_FW_OFLD_TX_DATA_WR_FLUSH(1U) +/* Use fw_ofld_tx_data_wr structure */ +#define S_FW_ISCSI_TX_DATA_WR_FLAGS_HI 10 +#define M_FW_ISCSI_TX_DATA_WR_FLAGS_HI 0x3fffff +#define V_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ + ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) +#define G_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ + (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) & M_FW_ISCSI_TX_DATA_WR_FLAGS_HI) -#define S_FW_OFLD_TX_DATA_WR_URGENT 16 -#define M_FW_OFLD_TX_DATA_WR_URGENT 0x1 -#define V_FW_OFLD_TX_DATA_WR_URGENT(x) ((x) << S_FW_OFLD_TX_DATA_WR_URGENT) -#define G_FW_OFLD_TX_DATA_WR_URGENT(x) \ - (((x) >> S_FW_OFLD_TX_DATA_WR_URGENT) & M_FW_OFLD_TX_DATA_WR_URGENT) -#define F_FW_OFLD_TX_DATA_WR_URGENT V_FW_OFLD_TX_DATA_WR_URGENT(1U) +#define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 9 +#define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 0x1 +#define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ + ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) +#define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ + (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) & \ + M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) +#define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO \ + V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(1U) -#define S_FW_OFLD_TX_DATA_WR_MORE 15 -#define M_FW_OFLD_TX_DATA_WR_MORE 0x1 -#define V_FW_OFLD_TX_DATA_WR_MORE(x) ((x) << S_FW_OFLD_TX_DATA_WR_MORE) -#define G_FW_OFLD_TX_DATA_WR_MORE(x) \ - (((x) >> S_FW_OFLD_TX_DATA_WR_MORE) & M_FW_OFLD_TX_DATA_WR_MORE) -#define F_FW_OFLD_TX_DATA_WR_MORE V_FW_OFLD_TX_DATA_WR_MORE(1U) +#define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 8 +#define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 0x1 +#define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ + ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) +#define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ + (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) & \ + M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) +#define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI \ + V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(1U) -#define S_FW_OFLD_TX_DATA_WR_SHOVE 14 -#define M_FW_OFLD_TX_DATA_WR_SHOVE 0x1 -#define V_FW_OFLD_TX_DATA_WR_SHOVE(x) ((x) << S_FW_OFLD_TX_DATA_WR_SHOVE) -#define G_FW_OFLD_TX_DATA_WR_SHOVE(x) \ - (((x) >> S_FW_OFLD_TX_DATA_WR_SHOVE) & M_FW_OFLD_TX_DATA_WR_SHOVE) -#define F_FW_OFLD_TX_DATA_WR_SHOVE V_FW_OFLD_TX_DATA_WR_SHOVE(1U) +#define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 7 +#define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 0x1 +#define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ + ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) +#define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ + (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) & \ + M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) +#define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC \ + V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(1U) -#define S_FW_OFLD_TX_DATA_WR_ULPMODE 10 -#define M_FW_OFLD_TX_DATA_WR_ULPMODE 0xf -#define V_FW_OFLD_TX_DATA_WR_ULPMODE(x) ((x) << S_FW_OFLD_TX_DATA_WR_ULPMODE) -#define G_FW_OFLD_TX_DATA_WR_ULPMODE(x) \ - (((x) >> S_FW_OFLD_TX_DATA_WR_ULPMODE) & M_FW_OFLD_TX_DATA_WR_ULPMODE) +#define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 6 +#define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 0x1 +#define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ + ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) +#define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ + (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) & \ + M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) +#define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC \ + V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(1U) -#define S_FW_OFLD_TX_DATA_WR_ULPSUBMODE 6 -#define M_FW_OFLD_TX_DATA_WR_ULPSUBMODE 0xf -#define V_FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) \ - ((x) << S_FW_OFLD_TX_DATA_WR_ULPSUBMODE) -#define G_FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) \ - (((x) >> S_FW_OFLD_TX_DATA_WR_ULPSUBMODE) & \ - M_FW_OFLD_TX_DATA_WR_ULPSUBMODE) - -#define S_FW_OFLD_TX_DATA_WR_PROXY 5 -#define M_FW_OFLD_TX_DATA_WR_PROXY 0x1 -#define V_FW_OFLD_TX_DATA_WR_PROXY(x) ((x) << S_FW_OFLD_TX_DATA_WR_PROXY) -#define G_FW_OFLD_TX_DATA_WR_PROXY(x) \ - (((x) >> S_FW_OFLD_TX_DATA_WR_PROXY) & M_FW_OFLD_TX_DATA_WR_PROXY) -#define F_FW_OFLD_TX_DATA_WR_PROXY V_FW_OFLD_TX_DATA_WR_PROXY(1U) +#define S_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0 +#define M_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0x3f +#define V_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ + ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) +#define G_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ + (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) & M_FW_ISCSI_TX_DATA_WR_FLAGS_LO) struct fw_cmd_wr { __be32 op_dma; @@ -1912,10 +1950,10 @@ struct fw_ri_wr { enum fw_chnet_ifconf_wr_subop { FW_CHNET_IFCONF_WR_SUBOP_NONE = 0, - + FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET, FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET, - + FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET, FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET, @@ -1931,6 +1969,13 @@ enum fw_chnet_ifconf_wr_subop { FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET, FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET, + FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_SET, + FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_GET, + + FW_CHNET_IFCONF_WR_SUBOP_LINKLOCAL_ADDR_SET, + FW_CHNET_IFCONF_WR_SUBOP_RA_BASED_ADDR_SET, + FW_CHNET_IFCONF_WR_SUBOP_ADDR_EXPIRED, + FW_CHNET_IFCONF_WR_SUBOP_MAX, }; @@ -1957,17 +2002,14 @@ struct fw_chnet_ifconf_wr { __be64 r1; } ipv4; struct fw_chnet_ifconf_ipv6 { - __be64 linklocal_lo; - __be64 linklocal_hi; + __u8 prefix_len; + __u8 r0; + __be16 r1; + __be32 r2; + __be64 addr_hi; + __be64 addr_lo; __be64 router_hi; __be64 router_lo; - __be64 aconf_hi; - __be64 aconf_lo; - __be64 linklocal_aconf_hi; - __be64 linklocal_aconf_lo; - __be64 router_aconf_hi; - __be64 router_aconf_lo; - __be64 r0; } ipv6; } in_attr; } param; @@ -2449,6 +2491,13 @@ struct fw_foiscsi_ctrl_wr { #define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ) +#define S_FW_FOISCSI_CTRL_WR_IPV6 20 +#define M_FW_FOISCSI_CTRL_WR_IPV6 0x1 +#define V_FW_FOISCSI_CTRL_WR_IPV6(x) ((x) << S_FW_FOISCSI_CTRL_WR_IPV6) +#define G_FW_FOISCSI_CTRL_WR_IPV6(x) \ + (((x) >> S_FW_FOISCSI_CTRL_WR_IPV6) & M_FW_FOISCSI_CTRL_WR_IPV6) +#define F_FW_FOISCSI_CTRL_WR_IPV6 V_FW_FOISCSI_CTRL_WR_IPV6(1U) + struct fw_foiscsi_chap_wr { __be32 op_compl; __be32 flowid_len16; @@ -2966,16 +3015,16 @@ struct fw_scsi_tgt_rsp_wr { struct fw_pofcoe_tcb_wr { __be32 op_compl; __be32 equiq_to_len16; - __be64 cookie; + __be32 r4; + __be32 xfer_len; __be32 tid_to_port; __be16 x_id; __be16 vlan_id; + __be64 cookie; __be32 s_id; __be32 d_id; __be32 tag; - __be32 xfer_len; - __be32 r4; - __be16 r5; + __be16 r6; __be16 iqid; }; @@ -3011,6 +3060,113 @@ struct fw_pofcoe_ulptx_wr { __u64 cookie; }; +/******************************************************************* + * T10 DIF related definition + *******************************************************************/ +struct fw_tx_pi_header { + __be16 op_to_inline; + __u8 pi_interval_tag_type; + __u8 num_pi; + __be32 pi_start4_pi_end4; + __u8 tag_gen_enabled_pkd; + __u8 num_pi_dsg; + __be16 app_tag; + __be32 ref_tag; +}; + +#define S_FW_TX_PI_HEADER_OP 8 +#define M_FW_TX_PI_HEADER_OP 0xff +#define V_FW_TX_PI_HEADER_OP(x) ((x) << S_FW_TX_PI_HEADER_OP) +#define G_FW_TX_PI_HEADER_OP(x) \ + (((x) >> S_FW_TX_PI_HEADER_OP) & M_FW_TX_PI_HEADER_OP) + +#define S_FW_TX_PI_HEADER_ULPTXMORE 7 +#define M_FW_TX_PI_HEADER_ULPTXMORE 0x1 +#define V_FW_TX_PI_HEADER_ULPTXMORE(x) ((x) << S_FW_TX_PI_HEADER_ULPTXMORE) +#define G_FW_TX_PI_HEADER_ULPTXMORE(x) \ + (((x) >> S_FW_TX_PI_HEADER_ULPTXMORE) & M_FW_TX_PI_HEADER_ULPTXMORE) +#define F_FW_TX_PI_HEADER_ULPTXMORE V_FW_TX_PI_HEADER_ULPTXMORE(1U) + +#define S_FW_TX_PI_HEADER_PI_CONTROL 4 +#define M_FW_TX_PI_HEADER_PI_CONTROL 0x7 +#define V_FW_TX_PI_HEADER_PI_CONTROL(x) ((x) << S_FW_TX_PI_HEADER_PI_CONTROL) +#define G_FW_TX_PI_HEADER_PI_CONTROL(x) \ + (((x) >> S_FW_TX_PI_HEADER_PI_CONTROL) & M_FW_TX_PI_HEADER_PI_CONTROL) + +#define S_FW_TX_PI_HEADER_GUARD_TYPE 2 +#define M_FW_TX_PI_HEADER_GUARD_TYPE 0x1 +#define V_FW_TX_PI_HEADER_GUARD_TYPE(x) ((x) << S_FW_TX_PI_HEADER_GUARD_TYPE) +#define G_FW_TX_PI_HEADER_GUARD_TYPE(x) \ + (((x) >> S_FW_TX_PI_HEADER_GUARD_TYPE) & M_FW_TX_PI_HEADER_GUARD_TYPE) +#define F_FW_TX_PI_HEADER_GUARD_TYPE V_FW_TX_PI_HEADER_GUARD_TYPE(1U) + +#define S_FW_TX_PI_HEADER_VALIDATE 1 +#define M_FW_TX_PI_HEADER_VALIDATE 0x1 +#define V_FW_TX_PI_HEADER_VALIDATE(x) ((x) << S_FW_TX_PI_HEADER_VALIDATE) +#define G_FW_TX_PI_HEADER_VALIDATE(x) \ + (((x) >> S_FW_TX_PI_HEADER_VALIDATE) & M_FW_TX_PI_HEADER_VALIDATE) +#define F_FW_TX_PI_HEADER_VALIDATE V_FW_TX_PI_HEADER_VALIDATE(1U) + +#define S_FW_TX_PI_HEADER_INLINE 0 +#define M_FW_TX_PI_HEADER_INLINE 0x1 +#define V_FW_TX_PI_HEADER_INLINE(x) ((x) << S_FW_TX_PI_HEADER_INLINE) +#define G_FW_TX_PI_HEADER_INLINE(x) \ + (((x) >> S_FW_TX_PI_HEADER_INLINE) & M_FW_TX_PI_HEADER_INLINE) +#define F_FW_TX_PI_HEADER_INLINE V_FW_TX_PI_HEADER_INLINE(1U) + +#define S_FW_TX_PI_HEADER_PI_INTERVAL 7 +#define M_FW_TX_PI_HEADER_PI_INTERVAL 0x1 +#define V_FW_TX_PI_HEADER_PI_INTERVAL(x) \ + ((x) << S_FW_TX_PI_HEADER_PI_INTERVAL) +#define G_FW_TX_PI_HEADER_PI_INTERVAL(x) \ + (((x) >> S_FW_TX_PI_HEADER_PI_INTERVAL) & M_FW_TX_PI_HEADER_PI_INTERVAL) +#define F_FW_TX_PI_HEADER_PI_INTERVAL V_FW_TX_PI_HEADER_PI_INTERVAL(1U) + +#define S_FW_TX_PI_HEADER_TAG_TYPE 5 +#define M_FW_TX_PI_HEADER_TAG_TYPE 0x3 +#define V_FW_TX_PI_HEADER_TAG_TYPE(x) ((x) << S_FW_TX_PI_HEADER_TAG_TYPE) +#define G_FW_TX_PI_HEADER_TAG_TYPE(x) \ + (((x) >> S_FW_TX_PI_HEADER_TAG_TYPE) & M_FW_TX_PI_HEADER_TAG_TYPE) + +#define S_FW_TX_PI_HEADER_PI_START4 22 +#define M_FW_TX_PI_HEADER_PI_START4 0x3ff +#define V_FW_TX_PI_HEADER_PI_START4(x) ((x) << S_FW_TX_PI_HEADER_PI_START4) +#define G_FW_TX_PI_HEADER_PI_START4(x) \ + (((x) >> S_FW_TX_PI_HEADER_PI_START4) & M_FW_TX_PI_HEADER_PI_START4) + +#define S_FW_TX_PI_HEADER_PI_END4 0 +#define M_FW_TX_PI_HEADER_PI_END4 0x3fffff +#define V_FW_TX_PI_HEADER_PI_END4(x) ((x) << S_FW_TX_PI_HEADER_PI_END4) +#define G_FW_TX_PI_HEADER_PI_END4(x) \ + (((x) >> S_FW_TX_PI_HEADER_PI_END4) & M_FW_TX_PI_HEADER_PI_END4) + +#define S_FW_TX_PI_HEADER_TAG_GEN_ENABLED 6 +#define M_FW_TX_PI_HEADER_TAG_GEN_ENABLED 0x3 +#define V_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \ + ((x) << S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) +#define G_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \ + (((x) >> S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) & \ + M_FW_TX_PI_HEADER_TAG_GEN_ENABLED) + +enum fw_pi_error_type { + FW_PI_ERROR_GUARD_CHECK_FAILED = 0, +}; + +struct fw_pi_error { + __be32 err_type_pkd; + __be32 flowid_len16; + __be16 r2; + __be16 app_tag; + __be32 ref_tag; + __be32 pisc[4]; +}; + +#define S_FW_PI_ERROR_ERR_TYPE 24 +#define M_FW_PI_ERROR_ERR_TYPE 0xff +#define V_FW_PI_ERROR_ERR_TYPE(x) ((x) << S_FW_PI_ERROR_ERR_TYPE) +#define G_FW_PI_ERROR_ERR_TYPE(x) \ + (((x) >> S_FW_PI_ERROR_ERR_TYPE) & M_FW_PI_ERROR_ERR_TYPE) + /****************************************************************************** * C O M M A N D s @@ -3076,6 +3232,7 @@ enum fw_cmd_opcodes { FW_FCOE_SPARAMS_CMD = 0x35, FW_FCOE_STATS_CMD = 0x37, FW_FCOE_FCF_CMD = 0x38, + FW_PTP_CMD = 0x39, FW_LASTC2E_CMD = 0x40, FW_ERROR_CMD = 0x80, FW_DEBUG_CMD = 0x81, @@ -3166,6 +3323,7 @@ enum fw_ldst_addrspc { FW_LDST_ADDRSPC_PCIE_CFGS = 0x0040, FW_LDST_ADDRSPC_PCIE_DBG = 0x0041, FW_LDST_ADDRSPC_PCIE_PHY = 0x0042, + FW_LDST_ADDRSPC_CIM_Q = 0x0048, }; /* @@ -3217,15 +3375,34 @@ struct fw_ldst_cmd { __be16 vctl; __be16 rval; } mdio; - struct fw_ldst_mps { - __be16 fid_ctl; - __be16 rplcpf_pkd; - __be32 rplc127_96; - __be32 rplc95_64; - __be32 rplc63_32; - __be32 rplc31_0; - __be32 atrb; - __be16 vlan[16]; + struct fw_ldst_cim_rq { + __u8 req_first64[8]; + __u8 req_second64[8]; + __u8 resp_first64[8]; + __u8 resp_second64[8]; + __be32 r3[2]; + } cim_rq; + union fw_ldst_mps { + struct fw_ldst_mps_rplc { + __be16 fid_idx; + __be16 rplcpf_pkd; + __be32 rplc255_224; + __be32 rplc223_192; + __be32 rplc191_160; + __be32 rplc159_128; + __be32 rplc127_96; + __be32 rplc95_64; + __be32 rplc63_32; + __be32 rplc31_0; + } rplc; + struct fw_ldst_mps_atrb { + __be16 fid_mpsid; + __be16 r2[3]; + __be32 r3[2]; + __be32 r4; + __be32 atrb; + __be16 vlan[16]; + } atrb; } mps; struct fw_ldst_func { __u8 access_ctl; @@ -3275,85 +3452,94 @@ struct fw_ldst_cmd { #define G_FW_LDST_CMD_ADDRSPACE(x) \ (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE) -#define S_FW_LDST_CMD_CYCLES 16 -#define M_FW_LDST_CMD_CYCLES 0xffff -#define V_FW_LDST_CMD_CYCLES(x) ((x) << S_FW_LDST_CMD_CYCLES) -#define G_FW_LDST_CMD_CYCLES(x) \ +#define S_FW_LDST_CMD_CYCLES 16 +#define M_FW_LDST_CMD_CYCLES 0xffff +#define V_FW_LDST_CMD_CYCLES(x) ((x) << S_FW_LDST_CMD_CYCLES) +#define G_FW_LDST_CMD_CYCLES(x) \ (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES) -#define S_FW_LDST_CMD_MSG 31 -#define M_FW_LDST_CMD_MSG 0x1 -#define V_FW_LDST_CMD_MSG(x) ((x) << S_FW_LDST_CMD_MSG) -#define G_FW_LDST_CMD_MSG(x) \ +#define S_FW_LDST_CMD_MSG 31 +#define M_FW_LDST_CMD_MSG 0x1 +#define V_FW_LDST_CMD_MSG(x) ((x) << S_FW_LDST_CMD_MSG) +#define G_FW_LDST_CMD_MSG(x) \ (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG) -#define F_FW_LDST_CMD_MSG V_FW_LDST_CMD_MSG(1U) +#define F_FW_LDST_CMD_MSG V_FW_LDST_CMD_MSG(1U) #define S_FW_LDST_CMD_CTXTFLUSH 30 #define M_FW_LDST_CMD_CTXTFLUSH 0x1 #define V_FW_LDST_CMD_CTXTFLUSH(x) ((x) << S_FW_LDST_CMD_CTXTFLUSH) #define G_FW_LDST_CMD_CTXTFLUSH(x) \ (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH) -#define F_FW_LDST_CMD_CTXTFLUSH V_FW_LDST_CMD_CTXTFLUSH(1U) +#define F_FW_LDST_CMD_CTXTFLUSH V_FW_LDST_CMD_CTXTFLUSH(1U) -#define S_FW_LDST_CMD_PADDR 8 -#define M_FW_LDST_CMD_PADDR 0x1f -#define V_FW_LDST_CMD_PADDR(x) ((x) << S_FW_LDST_CMD_PADDR) -#define G_FW_LDST_CMD_PADDR(x) \ +#define S_FW_LDST_CMD_PADDR 8 +#define M_FW_LDST_CMD_PADDR 0x1f +#define V_FW_LDST_CMD_PADDR(x) ((x) << S_FW_LDST_CMD_PADDR) +#define G_FW_LDST_CMD_PADDR(x) \ (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR) -#define S_FW_LDST_CMD_MMD 0 -#define M_FW_LDST_CMD_MMD 0x1f -#define V_FW_LDST_CMD_MMD(x) ((x) << S_FW_LDST_CMD_MMD) -#define G_FW_LDST_CMD_MMD(x) \ +#define S_FW_LDST_CMD_MMD 0 +#define M_FW_LDST_CMD_MMD 0x1f +#define V_FW_LDST_CMD_MMD(x) ((x) << S_FW_LDST_CMD_MMD) +#define G_FW_LDST_CMD_MMD(x) \ (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD) -#define S_FW_LDST_CMD_FID 15 -#define M_FW_LDST_CMD_FID 0x1 -#define V_FW_LDST_CMD_FID(x) ((x) << S_FW_LDST_CMD_FID) -#define G_FW_LDST_CMD_FID(x) \ +#define S_FW_LDST_CMD_FID 15 +#define M_FW_LDST_CMD_FID 0x1 +#define V_FW_LDST_CMD_FID(x) ((x) << S_FW_LDST_CMD_FID) +#define G_FW_LDST_CMD_FID(x) \ (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID) -#define F_FW_LDST_CMD_FID V_FW_LDST_CMD_FID(1U) +#define F_FW_LDST_CMD_FID V_FW_LDST_CMD_FID(1U) -#define S_FW_LDST_CMD_CTL 0 -#define M_FW_LDST_CMD_CTL 0x7fff -#define V_FW_LDST_CMD_CTL(x) ((x) << S_FW_LDST_CMD_CTL) -#define G_FW_LDST_CMD_CTL(x) \ - (((x) >> S_FW_LDST_CMD_CTL) & M_FW_LDST_CMD_CTL) +#define S_FW_LDST_CMD_IDX 0 +#define M_FW_LDST_CMD_IDX 0x7fff +#define V_FW_LDST_CMD_IDX(x) ((x) << S_FW_LDST_CMD_IDX) +#define G_FW_LDST_CMD_IDX(x) \ + (((x) >> S_FW_LDST_CMD_IDX) & M_FW_LDST_CMD_IDX) -#define S_FW_LDST_CMD_RPLCPF 0 -#define M_FW_LDST_CMD_RPLCPF 0xff -#define V_FW_LDST_CMD_RPLCPF(x) ((x) << S_FW_LDST_CMD_RPLCPF) -#define G_FW_LDST_CMD_RPLCPF(x) \ +#define S_FW_LDST_CMD_RPLCPF 0 +#define M_FW_LDST_CMD_RPLCPF 0xff +#define V_FW_LDST_CMD_RPLCPF(x) ((x) << S_FW_LDST_CMD_RPLCPF) +#define G_FW_LDST_CMD_RPLCPF(x) \ (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF) -#define S_FW_LDST_CMD_CTRL 7 -#define M_FW_LDST_CMD_CTRL 0x1 -#define V_FW_LDST_CMD_CTRL(x) ((x) << S_FW_LDST_CMD_CTRL) -#define G_FW_LDST_CMD_CTRL(x) \ +#define S_FW_LDST_CMD_MPSID 0 +#define M_FW_LDST_CMD_MPSID 0x7fff +#define V_FW_LDST_CMD_MPSID(x) ((x) << S_FW_LDST_CMD_MPSID) +#define G_FW_LDST_CMD_MPSID(x) \ + (((x) >> S_FW_LDST_CMD_MPSID) & M_FW_LDST_CMD_MPSID) + +#define S_FW_LDST_CMD_CTRL 7 +#define M_FW_LDST_CMD_CTRL 0x1 +#define V_FW_LDST_CMD_CTRL(x) ((x) << S_FW_LDST_CMD_CTRL) +#define G_FW_LDST_CMD_CTRL(x) \ (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL) -#define F_FW_LDST_CMD_CTRL V_FW_LDST_CMD_CTRL(1U) +#define F_FW_LDST_CMD_CTRL V_FW_LDST_CMD_CTRL(1U) -#define S_FW_LDST_CMD_LC 4 -#define M_FW_LDST_CMD_LC 0x1 -#define V_FW_LDST_CMD_LC(x) ((x) << S_FW_LDST_CMD_LC) -#define G_FW_LDST_CMD_LC(x) (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC) -#define F_FW_LDST_CMD_LC V_FW_LDST_CMD_LC(1U) +#define S_FW_LDST_CMD_LC 4 +#define M_FW_LDST_CMD_LC 0x1 +#define V_FW_LDST_CMD_LC(x) ((x) << S_FW_LDST_CMD_LC) +#define G_FW_LDST_CMD_LC(x) \ + (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC) +#define F_FW_LDST_CMD_LC V_FW_LDST_CMD_LC(1U) -#define S_FW_LDST_CMD_AI 3 -#define M_FW_LDST_CMD_AI 0x1 -#define V_FW_LDST_CMD_AI(x) ((x) << S_FW_LDST_CMD_AI) -#define G_FW_LDST_CMD_AI(x) (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI) -#define F_FW_LDST_CMD_AI V_FW_LDST_CMD_AI(1U) +#define S_FW_LDST_CMD_AI 3 +#define M_FW_LDST_CMD_AI 0x1 +#define V_FW_LDST_CMD_AI(x) ((x) << S_FW_LDST_CMD_AI) +#define G_FW_LDST_CMD_AI(x) \ + (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI) +#define F_FW_LDST_CMD_AI V_FW_LDST_CMD_AI(1U) -#define S_FW_LDST_CMD_FN 0 -#define M_FW_LDST_CMD_FN 0x7 -#define V_FW_LDST_CMD_FN(x) ((x) << S_FW_LDST_CMD_FN) -#define G_FW_LDST_CMD_FN(x) (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN) +#define S_FW_LDST_CMD_FN 0 +#define M_FW_LDST_CMD_FN 0x7 +#define V_FW_LDST_CMD_FN(x) ((x) << S_FW_LDST_CMD_FN) +#define G_FW_LDST_CMD_FN(x) \ + (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN) -#define S_FW_LDST_CMD_SELECT 4 -#define M_FW_LDST_CMD_SELECT 0xf -#define V_FW_LDST_CMD_SELECT(x) ((x) << S_FW_LDST_CMD_SELECT) -#define G_FW_LDST_CMD_SELECT(x) \ +#define S_FW_LDST_CMD_SELECT 4 +#define M_FW_LDST_CMD_SELECT 0xf +#define V_FW_LDST_CMD_SELECT(x) ((x) << S_FW_LDST_CMD_SELECT) +#define G_FW_LDST_CMD_SELECT(x) \ (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT) #define S_FW_LDST_CMD_NACCESS 0 @@ -3362,16 +3548,16 @@ struct fw_ldst_cmd { #define G_FW_LDST_CMD_NACCESS(x) \ (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS) -#define S_FW_LDST_CMD_NSET 14 -#define M_FW_LDST_CMD_NSET 0x3 -#define V_FW_LDST_CMD_NSET(x) ((x) << S_FW_LDST_CMD_NSET) -#define G_FW_LDST_CMD_NSET(x) \ +#define S_FW_LDST_CMD_NSET 14 +#define M_FW_LDST_CMD_NSET 0x3 +#define V_FW_LDST_CMD_NSET(x) ((x) << S_FW_LDST_CMD_NSET) +#define G_FW_LDST_CMD_NSET(x) \ (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET) -#define S_FW_LDST_CMD_PID 6 -#define M_FW_LDST_CMD_PID 0x3 -#define V_FW_LDST_CMD_PID(x) ((x) << S_FW_LDST_CMD_PID) -#define G_FW_LDST_CMD_PID(x) \ +#define S_FW_LDST_CMD_PID 6 +#define M_FW_LDST_CMD_PID 0x3 +#define V_FW_LDST_CMD_PID(x) ((x) << S_FW_LDST_CMD_PID) +#define G_FW_LDST_CMD_PID(x) \ (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID) struct fw_reset_cmd { @@ -3381,12 +3567,12 @@ struct fw_reset_cmd { __be32 halt_pkd; }; -#define S_FW_RESET_CMD_HALT 31 -#define M_FW_RESET_CMD_HALT 0x1 -#define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT) -#define G_FW_RESET_CMD_HALT(x) \ +#define S_FW_RESET_CMD_HALT 31 +#define M_FW_RESET_CMD_HALT 0x1 +#define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT) +#define G_FW_RESET_CMD_HALT(x) \ (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT) -#define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U) +#define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U) enum { FW_HELLO_CMD_STAGE_OS = 0, @@ -3402,19 +3588,19 @@ struct fw_hello_cmd { __be32 fwrev; }; -#define S_FW_HELLO_CMD_ERR 31 -#define M_FW_HELLO_CMD_ERR 0x1 -#define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR) -#define G_FW_HELLO_CMD_ERR(x) \ +#define S_FW_HELLO_CMD_ERR 31 +#define M_FW_HELLO_CMD_ERR 0x1 +#define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR) +#define G_FW_HELLO_CMD_ERR(x) \ (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR) -#define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U) +#define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U) -#define S_FW_HELLO_CMD_INIT 30 -#define M_FW_HELLO_CMD_INIT 0x1 -#define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT) -#define G_FW_HELLO_CMD_INIT(x) \ +#define S_FW_HELLO_CMD_INIT 30 +#define M_FW_HELLO_CMD_INIT 0x1 +#define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT) +#define G_FW_HELLO_CMD_INIT(x) \ (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT) -#define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U) +#define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U) #define S_FW_HELLO_CMD_MASTERDIS 29 #define M_FW_HELLO_CMD_MASTERDIS 0x1 @@ -3449,10 +3635,10 @@ struct fw_hello_cmd { #define G_FW_HELLO_CMD_MBASYNCNOT(x) \ (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT) -#define S_FW_HELLO_CMD_STAGE 17 -#define M_FW_HELLO_CMD_STAGE 0x7 -#define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE) -#define G_FW_HELLO_CMD_STAGE(x) \ +#define S_FW_HELLO_CMD_STAGE 17 +#define M_FW_HELLO_CMD_STAGE 0x7 +#define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE) +#define G_FW_HELLO_CMD_STAGE(x) \ (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE) #define S_FW_HELLO_CMD_CLEARINIT 16 @@ -3564,6 +3750,7 @@ enum fw_caps_config_iscsi { FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010, FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020, + FW_CAPS_CONFIG_ISCSI_T10DIF = 0x00000040, }; enum fw_caps_config_fcoe { @@ -3610,19 +3797,19 @@ struct fw_caps_config_cmd { (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID) #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U) -#define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24 -#define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7 -#define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ +#define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24 +#define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7 +#define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) -#define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ +#define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \ M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) -#define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16 -#define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff -#define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ +#define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16 +#define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff +#define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) -#define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ +#define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \ M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) @@ -3634,6 +3821,7 @@ enum fw_params_mnem { FW_PARAMS_MNEM_PFVF = 2, /* function params */ FW_PARAMS_MNEM_REG = 3, /* limited register access */ FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ + FW_PARAMS_MNEM_CHNET = 5, /* chnet params */ FW_PARAMS_MNEM_LAST }; @@ -3671,6 +3859,39 @@ enum fw_params_param_dev { FW_PARAMS_PARAM_DEV_MCINIT = 0x16, FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, FW_PARAMS_PARAM_DEV_FWCACHE = 0x18, + FW_PARAMS_PARAM_DEV_RSSINFO = 0x19, +}; + +/* + * dev bypass parameters; actions and modes + */ +enum fw_params_param_dev_bypass { + + /* actions + */ + FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00, + FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01, + + /* modes + */ + FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00, + FW_PARAMS_PARAM_DEV_BYPASS_DROP = 0x1, + FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2, +}; + +enum fw_params_param_dev_phyfw { + FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00, + FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01, +}; + +enum fw_params_param_dev_diag { + FW_PARAM_DEV_DIAG_TMP = 0x00, + FW_PARAM_DEV_DIAG_VDD = 0x01, +}; + +enum fw_params_param_dev_fwcache { + FW_PARAM_DEV_FWCACHE_FLUSH = 0x00, + FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01, }; /* @@ -3734,35 +3955,16 @@ enum fw_params_param_dmaq { }; /* - * dev bypass parameters; actions and modes + * chnet parameters */ -enum fw_params_param_dev_bypass { - - /* actions - */ - FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00, - FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01, - - /* modes - */ - FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00, - FW_PARAMS_PARAM_DEV_BYPASS_DROP = 0x1, - FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2, +enum fw_params_param_chnet { + FW_PARAMS_PARAM_CHNET_FLAGS = 0x00, }; -enum fw_params_param_dev_phyfw { - FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00, - FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01, -}; - -enum fw_params_param_dev_diag { - FW_PARAM_DEV_DIAG_TMP = 0x00, - FW_PARAM_DEV_DIAG_VDD = 0x01, -}; - -enum fw_params_param_dev_fwcache { - FW_PARAM_DEV_FWCACHE_FLUSH = 0x00, - FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01, +enum fw_params_param_chnet_flags { + FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6 = 0x1, + FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_DAD = 0x2, + FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_MLDV2= 0x4, }; #define S_FW_PARAMS_MNEM 24 @@ -3810,16 +4012,16 @@ struct fw_params_cmd { } param[7]; }; -#define S_FW_PARAMS_CMD_PFN 8 -#define M_FW_PARAMS_CMD_PFN 0x7 -#define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN) -#define G_FW_PARAMS_CMD_PFN(x) \ +#define S_FW_PARAMS_CMD_PFN 8 +#define M_FW_PARAMS_CMD_PFN 0x7 +#define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN) +#define G_FW_PARAMS_CMD_PFN(x) \ (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN) -#define S_FW_PARAMS_CMD_VFN 0 -#define M_FW_PARAMS_CMD_VFN 0xff -#define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN) -#define G_FW_PARAMS_CMD_VFN(x) \ +#define S_FW_PARAMS_CMD_VFN 0 +#define M_FW_PARAMS_CMD_VFN 0xff +#define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN) +#define G_FW_PARAMS_CMD_VFN(x) \ (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN) struct fw_pfvf_cmd { @@ -3834,16 +4036,16 @@ struct fw_pfvf_cmd { __be32 r4; }; -#define S_FW_PFVF_CMD_PFN 8 -#define M_FW_PFVF_CMD_PFN 0x7 -#define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN) -#define G_FW_PFVF_CMD_PFN(x) \ +#define S_FW_PFVF_CMD_PFN 8 +#define M_FW_PFVF_CMD_PFN 0x7 +#define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN) +#define G_FW_PFVF_CMD_PFN(x) \ (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN) -#define S_FW_PFVF_CMD_VFN 0 -#define M_FW_PFVF_CMD_VFN 0xff -#define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN) -#define G_FW_PFVF_CMD_VFN(x) \ +#define S_FW_PFVF_CMD_VFN 0 +#define M_FW_PFVF_CMD_VFN 0xff +#define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN) +#define G_FW_PFVF_CMD_VFN(x) \ (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN) #define S_FW_PFVF_CMD_NIQFLINT 20 @@ -3852,46 +4054,47 @@ struct fw_pfvf_cmd { #define G_FW_PFVF_CMD_NIQFLINT(x) \ (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT) -#define S_FW_PFVF_CMD_NIQ 0 -#define M_FW_PFVF_CMD_NIQ 0xfffff -#define V_FW_PFVF_CMD_NIQ(x) ((x) << S_FW_PFVF_CMD_NIQ) -#define G_FW_PFVF_CMD_NIQ(x) \ +#define S_FW_PFVF_CMD_NIQ 0 +#define M_FW_PFVF_CMD_NIQ 0xfffff +#define V_FW_PFVF_CMD_NIQ(x) ((x) << S_FW_PFVF_CMD_NIQ) +#define G_FW_PFVF_CMD_NIQ(x) \ (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ) -#define S_FW_PFVF_CMD_TYPE 31 -#define M_FW_PFVF_CMD_TYPE 0x1 -#define V_FW_PFVF_CMD_TYPE(x) ((x) << S_FW_PFVF_CMD_TYPE) -#define G_FW_PFVF_CMD_TYPE(x) \ +#define S_FW_PFVF_CMD_TYPE 31 +#define M_FW_PFVF_CMD_TYPE 0x1 +#define V_FW_PFVF_CMD_TYPE(x) ((x) << S_FW_PFVF_CMD_TYPE) +#define G_FW_PFVF_CMD_TYPE(x) \ (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE) -#define F_FW_PFVF_CMD_TYPE V_FW_PFVF_CMD_TYPE(1U) +#define F_FW_PFVF_CMD_TYPE V_FW_PFVF_CMD_TYPE(1U) -#define S_FW_PFVF_CMD_CMASK 24 -#define M_FW_PFVF_CMD_CMASK 0xf -#define V_FW_PFVF_CMD_CMASK(x) ((x) << S_FW_PFVF_CMD_CMASK) -#define G_FW_PFVF_CMD_CMASK(x) \ +#define S_FW_PFVF_CMD_CMASK 24 +#define M_FW_PFVF_CMD_CMASK 0xf +#define V_FW_PFVF_CMD_CMASK(x) ((x) << S_FW_PFVF_CMD_CMASK) +#define G_FW_PFVF_CMD_CMASK(x) \ (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK) -#define S_FW_PFVF_CMD_PMASK 20 -#define M_FW_PFVF_CMD_PMASK 0xf -#define V_FW_PFVF_CMD_PMASK(x) ((x) << S_FW_PFVF_CMD_PMASK) -#define G_FW_PFVF_CMD_PMASK(x) \ +#define S_FW_PFVF_CMD_PMASK 20 +#define M_FW_PFVF_CMD_PMASK 0xf +#define V_FW_PFVF_CMD_PMASK(x) ((x) << S_FW_PFVF_CMD_PMASK) +#define G_FW_PFVF_CMD_PMASK(x) \ (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK) -#define S_FW_PFVF_CMD_NEQ 0 -#define M_FW_PFVF_CMD_NEQ 0xfffff -#define V_FW_PFVF_CMD_NEQ(x) ((x) << S_FW_PFVF_CMD_NEQ) -#define G_FW_PFVF_CMD_NEQ(x) \ +#define S_FW_PFVF_CMD_NEQ 0 +#define M_FW_PFVF_CMD_NEQ 0xfffff +#define V_FW_PFVF_CMD_NEQ(x) ((x) << S_FW_PFVF_CMD_NEQ) +#define G_FW_PFVF_CMD_NEQ(x) \ (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ) -#define S_FW_PFVF_CMD_TC 24 -#define M_FW_PFVF_CMD_TC 0xff -#define V_FW_PFVF_CMD_TC(x) ((x) << S_FW_PFVF_CMD_TC) -#define G_FW_PFVF_CMD_TC(x) (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC) +#define S_FW_PFVF_CMD_TC 24 +#define M_FW_PFVF_CMD_TC 0xff +#define V_FW_PFVF_CMD_TC(x) ((x) << S_FW_PFVF_CMD_TC) +#define G_FW_PFVF_CMD_TC(x) \ + (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC) -#define S_FW_PFVF_CMD_NVI 16 -#define M_FW_PFVF_CMD_NVI 0xff -#define V_FW_PFVF_CMD_NVI(x) ((x) << S_FW_PFVF_CMD_NVI) -#define G_FW_PFVF_CMD_NVI(x) \ +#define S_FW_PFVF_CMD_NVI 16 +#define M_FW_PFVF_CMD_NVI 0xff +#define V_FW_PFVF_CMD_NVI(x) ((x) << S_FW_PFVF_CMD_NVI) +#define G_FW_PFVF_CMD_NVI(x) \ (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI) #define S_FW_PFVF_CMD_NEXACTF 0 @@ -3900,10 +4103,10 @@ struct fw_pfvf_cmd { #define G_FW_PFVF_CMD_NEXACTF(x) \ (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF) -#define S_FW_PFVF_CMD_R_CAPS 24 -#define M_FW_PFVF_CMD_R_CAPS 0xff -#define V_FW_PFVF_CMD_R_CAPS(x) ((x) << S_FW_PFVF_CMD_R_CAPS) -#define G_FW_PFVF_CMD_R_CAPS(x) \ +#define S_FW_PFVF_CMD_R_CAPS 24 +#define M_FW_PFVF_CMD_R_CAPS 0xff +#define V_FW_PFVF_CMD_R_CAPS(x) ((x) << S_FW_PFVF_CMD_R_CAPS) +#define G_FW_PFVF_CMD_R_CAPS(x) \ (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS) #define S_FW_PFVF_CMD_WX_CAPS 16 @@ -3949,85 +4152,90 @@ struct fw_iq_cmd { __be64 fl1addr; }; -#define S_FW_IQ_CMD_PFN 8 -#define M_FW_IQ_CMD_PFN 0x7 -#define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN) -#define G_FW_IQ_CMD_PFN(x) (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN) +#define S_FW_IQ_CMD_PFN 8 +#define M_FW_IQ_CMD_PFN 0x7 +#define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN) +#define G_FW_IQ_CMD_PFN(x) \ + (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN) -#define S_FW_IQ_CMD_VFN 0 -#define M_FW_IQ_CMD_VFN 0xff -#define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN) -#define G_FW_IQ_CMD_VFN(x) (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN) +#define S_FW_IQ_CMD_VFN 0 +#define M_FW_IQ_CMD_VFN 0xff +#define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN) +#define G_FW_IQ_CMD_VFN(x) \ + (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN) -#define S_FW_IQ_CMD_ALLOC 31 -#define M_FW_IQ_CMD_ALLOC 0x1 -#define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC) -#define G_FW_IQ_CMD_ALLOC(x) \ +#define S_FW_IQ_CMD_ALLOC 31 +#define M_FW_IQ_CMD_ALLOC 0x1 +#define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC) +#define G_FW_IQ_CMD_ALLOC(x) \ (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC) -#define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U) +#define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U) -#define S_FW_IQ_CMD_FREE 30 -#define M_FW_IQ_CMD_FREE 0x1 -#define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE) -#define G_FW_IQ_CMD_FREE(x) (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE) -#define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U) +#define S_FW_IQ_CMD_FREE 30 +#define M_FW_IQ_CMD_FREE 0x1 +#define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE) +#define G_FW_IQ_CMD_FREE(x) \ + (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE) +#define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U) -#define S_FW_IQ_CMD_MODIFY 29 -#define M_FW_IQ_CMD_MODIFY 0x1 -#define V_FW_IQ_CMD_MODIFY(x) ((x) << S_FW_IQ_CMD_MODIFY) -#define G_FW_IQ_CMD_MODIFY(x) \ +#define S_FW_IQ_CMD_MODIFY 29 +#define M_FW_IQ_CMD_MODIFY 0x1 +#define V_FW_IQ_CMD_MODIFY(x) ((x) << S_FW_IQ_CMD_MODIFY) +#define G_FW_IQ_CMD_MODIFY(x) \ (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY) -#define F_FW_IQ_CMD_MODIFY V_FW_IQ_CMD_MODIFY(1U) +#define F_FW_IQ_CMD_MODIFY V_FW_IQ_CMD_MODIFY(1U) -#define S_FW_IQ_CMD_IQSTART 28 -#define M_FW_IQ_CMD_IQSTART 0x1 -#define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART) -#define G_FW_IQ_CMD_IQSTART(x) \ +#define S_FW_IQ_CMD_IQSTART 28 +#define M_FW_IQ_CMD_IQSTART 0x1 +#define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART) +#define G_FW_IQ_CMD_IQSTART(x) \ (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART) -#define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U) +#define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U) -#define S_FW_IQ_CMD_IQSTOP 27 -#define M_FW_IQ_CMD_IQSTOP 0x1 -#define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP) -#define G_FW_IQ_CMD_IQSTOP(x) \ +#define S_FW_IQ_CMD_IQSTOP 27 +#define M_FW_IQ_CMD_IQSTOP 0x1 +#define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP) +#define G_FW_IQ_CMD_IQSTOP(x) \ (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP) -#define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U) +#define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U) -#define S_FW_IQ_CMD_TYPE 29 -#define M_FW_IQ_CMD_TYPE 0x7 -#define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE) -#define G_FW_IQ_CMD_TYPE(x) (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE) +#define S_FW_IQ_CMD_TYPE 29 +#define M_FW_IQ_CMD_TYPE 0x7 +#define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE) +#define G_FW_IQ_CMD_TYPE(x) \ + (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE) -#define S_FW_IQ_CMD_IQASYNCH 28 -#define M_FW_IQ_CMD_IQASYNCH 0x1 -#define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH) -#define G_FW_IQ_CMD_IQASYNCH(x) \ +#define S_FW_IQ_CMD_IQASYNCH 28 +#define M_FW_IQ_CMD_IQASYNCH 0x1 +#define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH) +#define G_FW_IQ_CMD_IQASYNCH(x) \ (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH) -#define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U) +#define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U) -#define S_FW_IQ_CMD_VIID 16 -#define M_FW_IQ_CMD_VIID 0xfff -#define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID) -#define G_FW_IQ_CMD_VIID(x) (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID) +#define S_FW_IQ_CMD_VIID 16 +#define M_FW_IQ_CMD_VIID 0xfff +#define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID) +#define G_FW_IQ_CMD_VIID(x) \ + (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID) -#define S_FW_IQ_CMD_IQANDST 15 -#define M_FW_IQ_CMD_IQANDST 0x1 -#define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST) -#define G_FW_IQ_CMD_IQANDST(x) \ +#define S_FW_IQ_CMD_IQANDST 15 +#define M_FW_IQ_CMD_IQANDST 0x1 +#define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST) +#define G_FW_IQ_CMD_IQANDST(x) \ (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST) -#define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U) +#define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U) -#define S_FW_IQ_CMD_IQANUS 14 -#define M_FW_IQ_CMD_IQANUS 0x1 -#define V_FW_IQ_CMD_IQANUS(x) ((x) << S_FW_IQ_CMD_IQANUS) -#define G_FW_IQ_CMD_IQANUS(x) \ +#define S_FW_IQ_CMD_IQANUS 14 +#define M_FW_IQ_CMD_IQANUS 0x1 +#define V_FW_IQ_CMD_IQANUS(x) ((x) << S_FW_IQ_CMD_IQANUS) +#define G_FW_IQ_CMD_IQANUS(x) \ (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS) -#define F_FW_IQ_CMD_IQANUS V_FW_IQ_CMD_IQANUS(1U) +#define F_FW_IQ_CMD_IQANUS V_FW_IQ_CMD_IQANUS(1U) -#define S_FW_IQ_CMD_IQANUD 12 -#define M_FW_IQ_CMD_IQANUD 0x3 -#define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD) -#define G_FW_IQ_CMD_IQANUD(x) \ +#define S_FW_IQ_CMD_IQANUD 12 +#define M_FW_IQ_CMD_IQANUD 0x3 +#define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD) +#define G_FW_IQ_CMD_IQANUD(x) \ (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD) #define S_FW_IQ_CMD_IQANDSTINDEX 0 @@ -4041,32 +4249,32 @@ struct fw_iq_cmd { #define V_FW_IQ_CMD_IQDROPRSS(x) ((x) << S_FW_IQ_CMD_IQDROPRSS) #define G_FW_IQ_CMD_IQDROPRSS(x) \ (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS) -#define F_FW_IQ_CMD_IQDROPRSS V_FW_IQ_CMD_IQDROPRSS(1U) +#define F_FW_IQ_CMD_IQDROPRSS V_FW_IQ_CMD_IQDROPRSS(1U) #define S_FW_IQ_CMD_IQGTSMODE 14 #define M_FW_IQ_CMD_IQGTSMODE 0x1 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE) #define G_FW_IQ_CMD_IQGTSMODE(x) \ (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE) -#define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U) +#define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U) -#define S_FW_IQ_CMD_IQPCIECH 12 -#define M_FW_IQ_CMD_IQPCIECH 0x3 -#define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH) -#define G_FW_IQ_CMD_IQPCIECH(x) \ +#define S_FW_IQ_CMD_IQPCIECH 12 +#define M_FW_IQ_CMD_IQPCIECH 0x3 +#define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH) +#define G_FW_IQ_CMD_IQPCIECH(x) \ (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH) -#define S_FW_IQ_CMD_IQDCAEN 11 -#define M_FW_IQ_CMD_IQDCAEN 0x1 -#define V_FW_IQ_CMD_IQDCAEN(x) ((x) << S_FW_IQ_CMD_IQDCAEN) -#define G_FW_IQ_CMD_IQDCAEN(x) \ +#define S_FW_IQ_CMD_IQDCAEN 11 +#define M_FW_IQ_CMD_IQDCAEN 0x1 +#define V_FW_IQ_CMD_IQDCAEN(x) ((x) << S_FW_IQ_CMD_IQDCAEN) +#define G_FW_IQ_CMD_IQDCAEN(x) \ (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN) -#define F_FW_IQ_CMD_IQDCAEN V_FW_IQ_CMD_IQDCAEN(1U) +#define F_FW_IQ_CMD_IQDCAEN V_FW_IQ_CMD_IQDCAEN(1U) -#define S_FW_IQ_CMD_IQDCACPU 6 -#define M_FW_IQ_CMD_IQDCACPU 0x1f -#define V_FW_IQ_CMD_IQDCACPU(x) ((x) << S_FW_IQ_CMD_IQDCACPU) -#define G_FW_IQ_CMD_IQDCACPU(x) \ +#define S_FW_IQ_CMD_IQDCACPU 6 +#define M_FW_IQ_CMD_IQDCACPU 0x1f +#define V_FW_IQ_CMD_IQDCACPU(x) ((x) << S_FW_IQ_CMD_IQDCACPU) +#define G_FW_IQ_CMD_IQDCACPU(x) \ (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU) #define S_FW_IQ_CMD_IQINTCNTTHRESH 4 @@ -4075,36 +4283,39 @@ struct fw_iq_cmd { #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \ (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH) -#define S_FW_IQ_CMD_IQO 3 -#define M_FW_IQ_CMD_IQO 0x1 -#define V_FW_IQ_CMD_IQO(x) ((x) << S_FW_IQ_CMD_IQO) -#define G_FW_IQ_CMD_IQO(x) (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO) -#define F_FW_IQ_CMD_IQO V_FW_IQ_CMD_IQO(1U) +#define S_FW_IQ_CMD_IQO 3 +#define M_FW_IQ_CMD_IQO 0x1 +#define V_FW_IQ_CMD_IQO(x) ((x) << S_FW_IQ_CMD_IQO) +#define G_FW_IQ_CMD_IQO(x) \ + (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO) +#define F_FW_IQ_CMD_IQO V_FW_IQ_CMD_IQO(1U) -#define S_FW_IQ_CMD_IQCPRIO 2 -#define M_FW_IQ_CMD_IQCPRIO 0x1 -#define V_FW_IQ_CMD_IQCPRIO(x) ((x) << S_FW_IQ_CMD_IQCPRIO) -#define G_FW_IQ_CMD_IQCPRIO(x) \ +#define S_FW_IQ_CMD_IQCPRIO 2 +#define M_FW_IQ_CMD_IQCPRIO 0x1 +#define V_FW_IQ_CMD_IQCPRIO(x) ((x) << S_FW_IQ_CMD_IQCPRIO) +#define G_FW_IQ_CMD_IQCPRIO(x) \ (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO) -#define F_FW_IQ_CMD_IQCPRIO V_FW_IQ_CMD_IQCPRIO(1U) +#define F_FW_IQ_CMD_IQCPRIO V_FW_IQ_CMD_IQCPRIO(1U) -#define S_FW_IQ_CMD_IQESIZE 0 -#define M_FW_IQ_CMD_IQESIZE 0x3 -#define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE) -#define G_FW_IQ_CMD_IQESIZE(x) \ +#define S_FW_IQ_CMD_IQESIZE 0 +#define M_FW_IQ_CMD_IQESIZE 0x3 +#define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE) +#define G_FW_IQ_CMD_IQESIZE(x) \ (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE) -#define S_FW_IQ_CMD_IQNS 31 -#define M_FW_IQ_CMD_IQNS 0x1 -#define V_FW_IQ_CMD_IQNS(x) ((x) << S_FW_IQ_CMD_IQNS) -#define G_FW_IQ_CMD_IQNS(x) (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS) -#define F_FW_IQ_CMD_IQNS V_FW_IQ_CMD_IQNS(1U) +#define S_FW_IQ_CMD_IQNS 31 +#define M_FW_IQ_CMD_IQNS 0x1 +#define V_FW_IQ_CMD_IQNS(x) ((x) << S_FW_IQ_CMD_IQNS) +#define G_FW_IQ_CMD_IQNS(x) \ + (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS) +#define F_FW_IQ_CMD_IQNS V_FW_IQ_CMD_IQNS(1U) -#define S_FW_IQ_CMD_IQRO 30 -#define M_FW_IQ_CMD_IQRO 0x1 -#define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO) -#define G_FW_IQ_CMD_IQRO(x) (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO) -#define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U) +#define S_FW_IQ_CMD_IQRO 30 +#define M_FW_IQ_CMD_IQRO 0x1 +#define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO) +#define G_FW_IQ_CMD_IQRO(x) \ + (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO) +#define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U) #define S_FW_IQ_CMD_IQFLINTIQHSEN 28 #define M_FW_IQ_CMD_IQFLINTIQHSEN 0x3 @@ -4132,6 +4343,13 @@ struct fw_iq_cmd { #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \ (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP) +#define S_FW_IQ_CMD_FL0CONGDROP 16 +#define M_FW_IQ_CMD_FL0CONGDROP 0x1 +#define V_FW_IQ_CMD_FL0CONGDROP(x) ((x) << S_FW_IQ_CMD_FL0CONGDROP) +#define G_FW_IQ_CMD_FL0CONGDROP(x) \ + (((x) >> S_FW_IQ_CMD_FL0CONGDROP) & M_FW_IQ_CMD_FL0CONGDROP) +#define F_FW_IQ_CMD_FL0CONGDROP V_FW_IQ_CMD_FL0CONGDROP(1U) + #define S_FW_IQ_CMD_FL0CACHELOCK 15 #define M_FW_IQ_CMD_FL0CACHELOCK 0x1 #define V_FW_IQ_CMD_FL0CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL0CACHELOCK) @@ -4139,40 +4357,40 @@ struct fw_iq_cmd { (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK) #define F_FW_IQ_CMD_FL0CACHELOCK V_FW_IQ_CMD_FL0CACHELOCK(1U) -#define S_FW_IQ_CMD_FL0DBP 14 -#define M_FW_IQ_CMD_FL0DBP 0x1 -#define V_FW_IQ_CMD_FL0DBP(x) ((x) << S_FW_IQ_CMD_FL0DBP) -#define G_FW_IQ_CMD_FL0DBP(x) \ +#define S_FW_IQ_CMD_FL0DBP 14 +#define M_FW_IQ_CMD_FL0DBP 0x1 +#define V_FW_IQ_CMD_FL0DBP(x) ((x) << S_FW_IQ_CMD_FL0DBP) +#define G_FW_IQ_CMD_FL0DBP(x) \ (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP) -#define F_FW_IQ_CMD_FL0DBP V_FW_IQ_CMD_FL0DBP(1U) +#define F_FW_IQ_CMD_FL0DBP V_FW_IQ_CMD_FL0DBP(1U) #define S_FW_IQ_CMD_FL0DATANS 13 #define M_FW_IQ_CMD_FL0DATANS 0x1 #define V_FW_IQ_CMD_FL0DATANS(x) ((x) << S_FW_IQ_CMD_FL0DATANS) #define G_FW_IQ_CMD_FL0DATANS(x) \ (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS) -#define F_FW_IQ_CMD_FL0DATANS V_FW_IQ_CMD_FL0DATANS(1U) +#define F_FW_IQ_CMD_FL0DATANS V_FW_IQ_CMD_FL0DATANS(1U) #define S_FW_IQ_CMD_FL0DATARO 12 #define M_FW_IQ_CMD_FL0DATARO 0x1 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO) #define G_FW_IQ_CMD_FL0DATARO(x) \ (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO) -#define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U) +#define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U) #define S_FW_IQ_CMD_FL0CONGCIF 11 #define M_FW_IQ_CMD_FL0CONGCIF 0x1 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF) #define G_FW_IQ_CMD_FL0CONGCIF(x) \ (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF) -#define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U) +#define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U) #define S_FW_IQ_CMD_FL0ONCHIP 10 #define M_FW_IQ_CMD_FL0ONCHIP 0x1 #define V_FW_IQ_CMD_FL0ONCHIP(x) ((x) << S_FW_IQ_CMD_FL0ONCHIP) #define G_FW_IQ_CMD_FL0ONCHIP(x) \ (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP) -#define F_FW_IQ_CMD_FL0ONCHIP V_FW_IQ_CMD_FL0ONCHIP(1U) +#define F_FW_IQ_CMD_FL0ONCHIP V_FW_IQ_CMD_FL0ONCHIP(1U) #define S_FW_IQ_CMD_FL0STATUSPGNS 9 #define M_FW_IQ_CMD_FL0STATUSPGNS 0x1 @@ -4193,14 +4411,14 @@ struct fw_iq_cmd { #define V_FW_IQ_CMD_FL0FETCHNS(x) ((x) << S_FW_IQ_CMD_FL0FETCHNS) #define G_FW_IQ_CMD_FL0FETCHNS(x) \ (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS) -#define F_FW_IQ_CMD_FL0FETCHNS V_FW_IQ_CMD_FL0FETCHNS(1U) +#define F_FW_IQ_CMD_FL0FETCHNS V_FW_IQ_CMD_FL0FETCHNS(1U) #define S_FW_IQ_CMD_FL0FETCHRO 6 #define M_FW_IQ_CMD_FL0FETCHRO 0x1 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO) #define G_FW_IQ_CMD_FL0FETCHRO(x) \ (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO) -#define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U) +#define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U) #define S_FW_IQ_CMD_FL0HOSTFCMODE 4 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3 @@ -4208,40 +4426,40 @@ struct fw_iq_cmd { #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \ (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE) -#define S_FW_IQ_CMD_FL0CPRIO 3 -#define M_FW_IQ_CMD_FL0CPRIO 0x1 -#define V_FW_IQ_CMD_FL0CPRIO(x) ((x) << S_FW_IQ_CMD_FL0CPRIO) -#define G_FW_IQ_CMD_FL0CPRIO(x) \ +#define S_FW_IQ_CMD_FL0CPRIO 3 +#define M_FW_IQ_CMD_FL0CPRIO 0x1 +#define V_FW_IQ_CMD_FL0CPRIO(x) ((x) << S_FW_IQ_CMD_FL0CPRIO) +#define G_FW_IQ_CMD_FL0CPRIO(x) \ (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO) -#define F_FW_IQ_CMD_FL0CPRIO V_FW_IQ_CMD_FL0CPRIO(1U) +#define F_FW_IQ_CMD_FL0CPRIO V_FW_IQ_CMD_FL0CPRIO(1U) -#define S_FW_IQ_CMD_FL0PADEN 2 -#define M_FW_IQ_CMD_FL0PADEN 0x1 -#define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN) -#define G_FW_IQ_CMD_FL0PADEN(x) \ +#define S_FW_IQ_CMD_FL0PADEN 2 +#define M_FW_IQ_CMD_FL0PADEN 0x1 +#define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN) +#define G_FW_IQ_CMD_FL0PADEN(x) \ (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN) -#define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U) +#define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U) #define S_FW_IQ_CMD_FL0PACKEN 1 #define M_FW_IQ_CMD_FL0PACKEN 0x1 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN) #define G_FW_IQ_CMD_FL0PACKEN(x) \ (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN) -#define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U) +#define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U) #define S_FW_IQ_CMD_FL0CONGEN 0 #define M_FW_IQ_CMD_FL0CONGEN 0x1 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN) #define G_FW_IQ_CMD_FL0CONGEN(x) \ (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN) -#define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U) +#define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U) -#define S_FW_IQ_CMD_FL0DCAEN 15 -#define M_FW_IQ_CMD_FL0DCAEN 0x1 -#define V_FW_IQ_CMD_FL0DCAEN(x) ((x) << S_FW_IQ_CMD_FL0DCAEN) -#define G_FW_IQ_CMD_FL0DCAEN(x) \ +#define S_FW_IQ_CMD_FL0DCAEN 15 +#define M_FW_IQ_CMD_FL0DCAEN 0x1 +#define V_FW_IQ_CMD_FL0DCAEN(x) ((x) << S_FW_IQ_CMD_FL0DCAEN) +#define G_FW_IQ_CMD_FL0DCAEN(x) \ (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN) -#define F_FW_IQ_CMD_FL0DCAEN V_FW_IQ_CMD_FL0DCAEN(1U) +#define F_FW_IQ_CMD_FL0DCAEN V_FW_IQ_CMD_FL0DCAEN(1U) #define S_FW_IQ_CMD_FL0DCACPU 10 #define M_FW_IQ_CMD_FL0DCACPU 0x1f @@ -4249,16 +4467,16 @@ struct fw_iq_cmd { #define G_FW_IQ_CMD_FL0DCACPU(x) \ (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU) -#define S_FW_IQ_CMD_FL0FBMIN 7 -#define M_FW_IQ_CMD_FL0FBMIN 0x7 -#define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN) -#define G_FW_IQ_CMD_FL0FBMIN(x) \ +#define S_FW_IQ_CMD_FL0FBMIN 7 +#define M_FW_IQ_CMD_FL0FBMIN 0x7 +#define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN) +#define G_FW_IQ_CMD_FL0FBMIN(x) \ (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN) -#define S_FW_IQ_CMD_FL0FBMAX 4 -#define M_FW_IQ_CMD_FL0FBMAX 0x7 -#define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX) -#define G_FW_IQ_CMD_FL0FBMAX(x) \ +#define S_FW_IQ_CMD_FL0FBMAX 4 +#define M_FW_IQ_CMD_FL0FBMAX 0x7 +#define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX) +#define G_FW_IQ_CMD_FL0FBMAX(x) \ (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX) #define S_FW_IQ_CMD_FL0CIDXFTHRESHO 3 @@ -4280,6 +4498,13 @@ struct fw_iq_cmd { #define G_FW_IQ_CMD_FL1CNGCHMAP(x) \ (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP) +#define S_FW_IQ_CMD_FL1CONGDROP 16 +#define M_FW_IQ_CMD_FL1CONGDROP 0x1 +#define V_FW_IQ_CMD_FL1CONGDROP(x) ((x) << S_FW_IQ_CMD_FL1CONGDROP) +#define G_FW_IQ_CMD_FL1CONGDROP(x) \ + (((x) >> S_FW_IQ_CMD_FL1CONGDROP) & M_FW_IQ_CMD_FL1CONGDROP) +#define F_FW_IQ_CMD_FL1CONGDROP V_FW_IQ_CMD_FL1CONGDROP(1U) + #define S_FW_IQ_CMD_FL1CACHELOCK 15 #define M_FW_IQ_CMD_FL1CACHELOCK 0x1 #define V_FW_IQ_CMD_FL1CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL1CACHELOCK) @@ -4287,40 +4512,40 @@ struct fw_iq_cmd { (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK) #define F_FW_IQ_CMD_FL1CACHELOCK V_FW_IQ_CMD_FL1CACHELOCK(1U) -#define S_FW_IQ_CMD_FL1DBP 14 -#define M_FW_IQ_CMD_FL1DBP 0x1 -#define V_FW_IQ_CMD_FL1DBP(x) ((x) << S_FW_IQ_CMD_FL1DBP) -#define G_FW_IQ_CMD_FL1DBP(x) \ +#define S_FW_IQ_CMD_FL1DBP 14 +#define M_FW_IQ_CMD_FL1DBP 0x1 +#define V_FW_IQ_CMD_FL1DBP(x) ((x) << S_FW_IQ_CMD_FL1DBP) +#define G_FW_IQ_CMD_FL1DBP(x) \ (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP) -#define F_FW_IQ_CMD_FL1DBP V_FW_IQ_CMD_FL1DBP(1U) +#define F_FW_IQ_CMD_FL1DBP V_FW_IQ_CMD_FL1DBP(1U) #define S_FW_IQ_CMD_FL1DATANS 13 #define M_FW_IQ_CMD_FL1DATANS 0x1 #define V_FW_IQ_CMD_FL1DATANS(x) ((x) << S_FW_IQ_CMD_FL1DATANS) #define G_FW_IQ_CMD_FL1DATANS(x) \ (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS) -#define F_FW_IQ_CMD_FL1DATANS V_FW_IQ_CMD_FL1DATANS(1U) +#define F_FW_IQ_CMD_FL1DATANS V_FW_IQ_CMD_FL1DATANS(1U) #define S_FW_IQ_CMD_FL1DATARO 12 #define M_FW_IQ_CMD_FL1DATARO 0x1 #define V_FW_IQ_CMD_FL1DATARO(x) ((x) << S_FW_IQ_CMD_FL1DATARO) #define G_FW_IQ_CMD_FL1DATARO(x) \ (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO) -#define F_FW_IQ_CMD_FL1DATARO V_FW_IQ_CMD_FL1DATARO(1U) +#define F_FW_IQ_CMD_FL1DATARO V_FW_IQ_CMD_FL1DATARO(1U) #define S_FW_IQ_CMD_FL1CONGCIF 11 #define M_FW_IQ_CMD_FL1CONGCIF 0x1 #define V_FW_IQ_CMD_FL1CONGCIF(x) ((x) << S_FW_IQ_CMD_FL1CONGCIF) #define G_FW_IQ_CMD_FL1CONGCIF(x) \ (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF) -#define F_FW_IQ_CMD_FL1CONGCIF V_FW_IQ_CMD_FL1CONGCIF(1U) +#define F_FW_IQ_CMD_FL1CONGCIF V_FW_IQ_CMD_FL1CONGCIF(1U) #define S_FW_IQ_CMD_FL1ONCHIP 10 #define M_FW_IQ_CMD_FL1ONCHIP 0x1 #define V_FW_IQ_CMD_FL1ONCHIP(x) ((x) << S_FW_IQ_CMD_FL1ONCHIP) #define G_FW_IQ_CMD_FL1ONCHIP(x) \ (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP) -#define F_FW_IQ_CMD_FL1ONCHIP V_FW_IQ_CMD_FL1ONCHIP(1U) +#define F_FW_IQ_CMD_FL1ONCHIP V_FW_IQ_CMD_FL1ONCHIP(1U) #define S_FW_IQ_CMD_FL1STATUSPGNS 9 #define M_FW_IQ_CMD_FL1STATUSPGNS 0x1 @@ -4341,14 +4566,14 @@ struct fw_iq_cmd { #define V_FW_IQ_CMD_FL1FETCHNS(x) ((x) << S_FW_IQ_CMD_FL1FETCHNS) #define G_FW_IQ_CMD_FL1FETCHNS(x) \ (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS) -#define F_FW_IQ_CMD_FL1FETCHNS V_FW_IQ_CMD_FL1FETCHNS(1U) +#define F_FW_IQ_CMD_FL1FETCHNS V_FW_IQ_CMD_FL1FETCHNS(1U) #define S_FW_IQ_CMD_FL1FETCHRO 6 #define M_FW_IQ_CMD_FL1FETCHRO 0x1 #define V_FW_IQ_CMD_FL1FETCHRO(x) ((x) << S_FW_IQ_CMD_FL1FETCHRO) #define G_FW_IQ_CMD_FL1FETCHRO(x) \ (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO) -#define F_FW_IQ_CMD_FL1FETCHRO V_FW_IQ_CMD_FL1FETCHRO(1U) +#define F_FW_IQ_CMD_FL1FETCHRO V_FW_IQ_CMD_FL1FETCHRO(1U) #define S_FW_IQ_CMD_FL1HOSTFCMODE 4 #define M_FW_IQ_CMD_FL1HOSTFCMODE 0x3 @@ -4356,40 +4581,40 @@ struct fw_iq_cmd { #define G_FW_IQ_CMD_FL1HOSTFCMODE(x) \ (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE) -#define S_FW_IQ_CMD_FL1CPRIO 3 -#define M_FW_IQ_CMD_FL1CPRIO 0x1 -#define V_FW_IQ_CMD_FL1CPRIO(x) ((x) << S_FW_IQ_CMD_FL1CPRIO) -#define G_FW_IQ_CMD_FL1CPRIO(x) \ +#define S_FW_IQ_CMD_FL1CPRIO 3 +#define M_FW_IQ_CMD_FL1CPRIO 0x1 +#define V_FW_IQ_CMD_FL1CPRIO(x) ((x) << S_FW_IQ_CMD_FL1CPRIO) +#define G_FW_IQ_CMD_FL1CPRIO(x) \ (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO) -#define F_FW_IQ_CMD_FL1CPRIO V_FW_IQ_CMD_FL1CPRIO(1U) +#define F_FW_IQ_CMD_FL1CPRIO V_FW_IQ_CMD_FL1CPRIO(1U) -#define S_FW_IQ_CMD_FL1PADEN 2 -#define M_FW_IQ_CMD_FL1PADEN 0x1 -#define V_FW_IQ_CMD_FL1PADEN(x) ((x) << S_FW_IQ_CMD_FL1PADEN) -#define G_FW_IQ_CMD_FL1PADEN(x) \ +#define S_FW_IQ_CMD_FL1PADEN 2 +#define M_FW_IQ_CMD_FL1PADEN 0x1 +#define V_FW_IQ_CMD_FL1PADEN(x) ((x) << S_FW_IQ_CMD_FL1PADEN) +#define G_FW_IQ_CMD_FL1PADEN(x) \ (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN) -#define F_FW_IQ_CMD_FL1PADEN V_FW_IQ_CMD_FL1PADEN(1U) +#define F_FW_IQ_CMD_FL1PADEN V_FW_IQ_CMD_FL1PADEN(1U) #define S_FW_IQ_CMD_FL1PACKEN 1 #define M_FW_IQ_CMD_FL1PACKEN 0x1 #define V_FW_IQ_CMD_FL1PACKEN(x) ((x) << S_FW_IQ_CMD_FL1PACKEN) #define G_FW_IQ_CMD_FL1PACKEN(x) \ (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN) -#define F_FW_IQ_CMD_FL1PACKEN V_FW_IQ_CMD_FL1PACKEN(1U) +#define F_FW_IQ_CMD_FL1PACKEN V_FW_IQ_CMD_FL1PACKEN(1U) #define S_FW_IQ_CMD_FL1CONGEN 0 #define M_FW_IQ_CMD_FL1CONGEN 0x1 #define V_FW_IQ_CMD_FL1CONGEN(x) ((x) << S_FW_IQ_CMD_FL1CONGEN) #define G_FW_IQ_CMD_FL1CONGEN(x) \ (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN) -#define F_FW_IQ_CMD_FL1CONGEN V_FW_IQ_CMD_FL1CONGEN(1U) +#define F_FW_IQ_CMD_FL1CONGEN V_FW_IQ_CMD_FL1CONGEN(1U) -#define S_FW_IQ_CMD_FL1DCAEN 15 -#define M_FW_IQ_CMD_FL1DCAEN 0x1 -#define V_FW_IQ_CMD_FL1DCAEN(x) ((x) << S_FW_IQ_CMD_FL1DCAEN) -#define G_FW_IQ_CMD_FL1DCAEN(x) \ +#define S_FW_IQ_CMD_FL1DCAEN 15 +#define M_FW_IQ_CMD_FL1DCAEN 0x1 +#define V_FW_IQ_CMD_FL1DCAEN(x) ((x) << S_FW_IQ_CMD_FL1DCAEN) +#define G_FW_IQ_CMD_FL1DCAEN(x) \ (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN) -#define F_FW_IQ_CMD_FL1DCAEN V_FW_IQ_CMD_FL1DCAEN(1U) +#define F_FW_IQ_CMD_FL1DCAEN V_FW_IQ_CMD_FL1DCAEN(1U) #define S_FW_IQ_CMD_FL1DCACPU 10 #define M_FW_IQ_CMD_FL1DCACPU 0x1f @@ -4397,16 +4622,16 @@ struct fw_iq_cmd { #define G_FW_IQ_CMD_FL1DCACPU(x) \ (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU) -#define S_FW_IQ_CMD_FL1FBMIN 7 -#define M_FW_IQ_CMD_FL1FBMIN 0x7 -#define V_FW_IQ_CMD_FL1FBMIN(x) ((x) << S_FW_IQ_CMD_FL1FBMIN) -#define G_FW_IQ_CMD_FL1FBMIN(x) \ +#define S_FW_IQ_CMD_FL1FBMIN 7 +#define M_FW_IQ_CMD_FL1FBMIN 0x7 +#define V_FW_IQ_CMD_FL1FBMIN(x) ((x) << S_FW_IQ_CMD_FL1FBMIN) +#define G_FW_IQ_CMD_FL1FBMIN(x) \ (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN) -#define S_FW_IQ_CMD_FL1FBMAX 4 -#define M_FW_IQ_CMD_FL1FBMAX 0x7 -#define V_FW_IQ_CMD_FL1FBMAX(x) ((x) << S_FW_IQ_CMD_FL1FBMAX) -#define G_FW_IQ_CMD_FL1FBMAX(x) \ +#define S_FW_IQ_CMD_FL1FBMAX 4 +#define M_FW_IQ_CMD_FL1FBMAX 0x7 +#define V_FW_IQ_CMD_FL1FBMAX(x) ((x) << S_FW_IQ_CMD_FL1FBMAX) +#define G_FW_IQ_CMD_FL1FBMAX(x) \ (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX) #define S_FW_IQ_CMD_FL1CIDXFTHRESHO 3 @@ -4432,16 +4657,16 @@ struct fw_eq_mngt_cmd { __be64 eqaddr; }; -#define S_FW_EQ_MNGT_CMD_PFN 8 -#define M_FW_EQ_MNGT_CMD_PFN 0x7 -#define V_FW_EQ_MNGT_CMD_PFN(x) ((x) << S_FW_EQ_MNGT_CMD_PFN) -#define G_FW_EQ_MNGT_CMD_PFN(x) \ +#define S_FW_EQ_MNGT_CMD_PFN 8 +#define M_FW_EQ_MNGT_CMD_PFN 0x7 +#define V_FW_EQ_MNGT_CMD_PFN(x) ((x) << S_FW_EQ_MNGT_CMD_PFN) +#define G_FW_EQ_MNGT_CMD_PFN(x) \ (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN) -#define S_FW_EQ_MNGT_CMD_VFN 0 -#define M_FW_EQ_MNGT_CMD_VFN 0xff -#define V_FW_EQ_MNGT_CMD_VFN(x) ((x) << S_FW_EQ_MNGT_CMD_VFN) -#define G_FW_EQ_MNGT_CMD_VFN(x) \ +#define S_FW_EQ_MNGT_CMD_VFN 0 +#define M_FW_EQ_MNGT_CMD_VFN 0xff +#define V_FW_EQ_MNGT_CMD_VFN(x) ((x) << S_FW_EQ_MNGT_CMD_VFN) +#define G_FW_EQ_MNGT_CMD_VFN(x) \ (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN) #define S_FW_EQ_MNGT_CMD_ALLOC 31 @@ -4449,21 +4674,21 @@ struct fw_eq_mngt_cmd { #define V_FW_EQ_MNGT_CMD_ALLOC(x) ((x) << S_FW_EQ_MNGT_CMD_ALLOC) #define G_FW_EQ_MNGT_CMD_ALLOC(x) \ (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC) -#define F_FW_EQ_MNGT_CMD_ALLOC V_FW_EQ_MNGT_CMD_ALLOC(1U) +#define F_FW_EQ_MNGT_CMD_ALLOC V_FW_EQ_MNGT_CMD_ALLOC(1U) #define S_FW_EQ_MNGT_CMD_FREE 30 #define M_FW_EQ_MNGT_CMD_FREE 0x1 #define V_FW_EQ_MNGT_CMD_FREE(x) ((x) << S_FW_EQ_MNGT_CMD_FREE) #define G_FW_EQ_MNGT_CMD_FREE(x) \ (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE) -#define F_FW_EQ_MNGT_CMD_FREE V_FW_EQ_MNGT_CMD_FREE(1U) +#define F_FW_EQ_MNGT_CMD_FREE V_FW_EQ_MNGT_CMD_FREE(1U) #define S_FW_EQ_MNGT_CMD_MODIFY 29 #define M_FW_EQ_MNGT_CMD_MODIFY 0x1 #define V_FW_EQ_MNGT_CMD_MODIFY(x) ((x) << S_FW_EQ_MNGT_CMD_MODIFY) #define G_FW_EQ_MNGT_CMD_MODIFY(x) \ (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY) -#define F_FW_EQ_MNGT_CMD_MODIFY V_FW_EQ_MNGT_CMD_MODIFY(1U) +#define F_FW_EQ_MNGT_CMD_MODIFY V_FW_EQ_MNGT_CMD_MODIFY(1U) #define S_FW_EQ_MNGT_CMD_EQSTART 28 #define M_FW_EQ_MNGT_CMD_EQSTART 0x1 @@ -4477,7 +4702,7 @@ struct fw_eq_mngt_cmd { #define V_FW_EQ_MNGT_CMD_EQSTOP(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTOP) #define G_FW_EQ_MNGT_CMD_EQSTOP(x) \ (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP) -#define F_FW_EQ_MNGT_CMD_EQSTOP V_FW_EQ_MNGT_CMD_EQSTOP(1U) +#define F_FW_EQ_MNGT_CMD_EQSTOP V_FW_EQ_MNGT_CMD_EQSTOP(1U) #define S_FW_EQ_MNGT_CMD_CMPLIQID 20 #define M_FW_EQ_MNGT_CMD_CMPLIQID 0xfff @@ -4543,14 +4768,14 @@ struct fw_eq_mngt_cmd { #define V_FW_EQ_MNGT_CMD_CPRIO(x) ((x) << S_FW_EQ_MNGT_CMD_CPRIO) #define G_FW_EQ_MNGT_CMD_CPRIO(x) \ (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO) -#define F_FW_EQ_MNGT_CMD_CPRIO V_FW_EQ_MNGT_CMD_CPRIO(1U) +#define F_FW_EQ_MNGT_CMD_CPRIO V_FW_EQ_MNGT_CMD_CPRIO(1U) #define S_FW_EQ_MNGT_CMD_ONCHIP 18 #define M_FW_EQ_MNGT_CMD_ONCHIP 0x1 #define V_FW_EQ_MNGT_CMD_ONCHIP(x) ((x) << S_FW_EQ_MNGT_CMD_ONCHIP) #define G_FW_EQ_MNGT_CMD_ONCHIP(x) \ (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP) -#define F_FW_EQ_MNGT_CMD_ONCHIP V_FW_EQ_MNGT_CMD_ONCHIP(1U) +#define F_FW_EQ_MNGT_CMD_ONCHIP V_FW_EQ_MNGT_CMD_ONCHIP(1U) #define S_FW_EQ_MNGT_CMD_PCIECHN 16 #define M_FW_EQ_MNGT_CMD_PCIECHN 0x3 @@ -4569,7 +4794,7 @@ struct fw_eq_mngt_cmd { #define V_FW_EQ_MNGT_CMD_DCAEN(x) ((x) << S_FW_EQ_MNGT_CMD_DCAEN) #define G_FW_EQ_MNGT_CMD_DCAEN(x) \ (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN) -#define F_FW_EQ_MNGT_CMD_DCAEN V_FW_EQ_MNGT_CMD_DCAEN(1U) +#define F_FW_EQ_MNGT_CMD_DCAEN V_FW_EQ_MNGT_CMD_DCAEN(1U) #define S_FW_EQ_MNGT_CMD_DCACPU 26 #define M_FW_EQ_MNGT_CMD_DCACPU 0x1f @@ -4589,11 +4814,11 @@ struct fw_eq_mngt_cmd { #define G_FW_EQ_MNGT_CMD_FBMAX(x) \ (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX) -#define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO 19 -#define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO 0x1 -#define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ +#define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO 19 +#define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO 0x1 +#define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) -#define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ +#define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO) #define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U) @@ -4622,16 +4847,16 @@ struct fw_eq_eth_cmd { __be64 r9; }; -#define S_FW_EQ_ETH_CMD_PFN 8 -#define M_FW_EQ_ETH_CMD_PFN 0x7 -#define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN) -#define G_FW_EQ_ETH_CMD_PFN(x) \ +#define S_FW_EQ_ETH_CMD_PFN 8 +#define M_FW_EQ_ETH_CMD_PFN 0x7 +#define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN) +#define G_FW_EQ_ETH_CMD_PFN(x) \ (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN) -#define S_FW_EQ_ETH_CMD_VFN 0 -#define M_FW_EQ_ETH_CMD_VFN 0xff -#define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN) -#define G_FW_EQ_ETH_CMD_VFN(x) \ +#define S_FW_EQ_ETH_CMD_VFN 0 +#define M_FW_EQ_ETH_CMD_VFN 0xff +#define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN) +#define G_FW_EQ_ETH_CMD_VFN(x) \ (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN) #define S_FW_EQ_ETH_CMD_ALLOC 31 @@ -4639,40 +4864,40 @@ struct fw_eq_eth_cmd { #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC) #define G_FW_EQ_ETH_CMD_ALLOC(x) \ (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC) -#define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U) +#define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U) -#define S_FW_EQ_ETH_CMD_FREE 30 -#define M_FW_EQ_ETH_CMD_FREE 0x1 -#define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE) -#define G_FW_EQ_ETH_CMD_FREE(x) \ +#define S_FW_EQ_ETH_CMD_FREE 30 +#define M_FW_EQ_ETH_CMD_FREE 0x1 +#define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE) +#define G_FW_EQ_ETH_CMD_FREE(x) \ (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE) -#define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U) +#define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U) #define S_FW_EQ_ETH_CMD_MODIFY 29 #define M_FW_EQ_ETH_CMD_MODIFY 0x1 #define V_FW_EQ_ETH_CMD_MODIFY(x) ((x) << S_FW_EQ_ETH_CMD_MODIFY) #define G_FW_EQ_ETH_CMD_MODIFY(x) \ (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY) -#define F_FW_EQ_ETH_CMD_MODIFY V_FW_EQ_ETH_CMD_MODIFY(1U) +#define F_FW_EQ_ETH_CMD_MODIFY V_FW_EQ_ETH_CMD_MODIFY(1U) #define S_FW_EQ_ETH_CMD_EQSTART 28 #define M_FW_EQ_ETH_CMD_EQSTART 0x1 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART) #define G_FW_EQ_ETH_CMD_EQSTART(x) \ (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART) -#define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U) +#define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U) #define S_FW_EQ_ETH_CMD_EQSTOP 27 #define M_FW_EQ_ETH_CMD_EQSTOP 0x1 #define V_FW_EQ_ETH_CMD_EQSTOP(x) ((x) << S_FW_EQ_ETH_CMD_EQSTOP) #define G_FW_EQ_ETH_CMD_EQSTOP(x) \ (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP) -#define F_FW_EQ_ETH_CMD_EQSTOP V_FW_EQ_ETH_CMD_EQSTOP(1U) +#define F_FW_EQ_ETH_CMD_EQSTOP V_FW_EQ_ETH_CMD_EQSTOP(1U) -#define S_FW_EQ_ETH_CMD_EQID 0 -#define M_FW_EQ_ETH_CMD_EQID 0xfffff -#define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID) -#define G_FW_EQ_ETH_CMD_EQID(x) \ +#define S_FW_EQ_ETH_CMD_EQID 0 +#define M_FW_EQ_ETH_CMD_EQID 0xfffff +#define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID) +#define G_FW_EQ_ETH_CMD_EQID(x) \ (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID) #define S_FW_EQ_ETH_CMD_PHYSEQID 0 @@ -4707,14 +4932,14 @@ struct fw_eq_eth_cmd { #define V_FW_EQ_ETH_CMD_FETCHNS(x) ((x) << S_FW_EQ_ETH_CMD_FETCHNS) #define G_FW_EQ_ETH_CMD_FETCHNS(x) \ (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS) -#define F_FW_EQ_ETH_CMD_FETCHNS V_FW_EQ_ETH_CMD_FETCHNS(1U) +#define F_FW_EQ_ETH_CMD_FETCHNS V_FW_EQ_ETH_CMD_FETCHNS(1U) #define S_FW_EQ_ETH_CMD_FETCHRO 22 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO) #define G_FW_EQ_ETH_CMD_FETCHRO(x) \ (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO) -#define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U) +#define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U) #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3 @@ -4727,14 +4952,14 @@ struct fw_eq_eth_cmd { #define V_FW_EQ_ETH_CMD_CPRIO(x) ((x) << S_FW_EQ_ETH_CMD_CPRIO) #define G_FW_EQ_ETH_CMD_CPRIO(x) \ (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO) -#define F_FW_EQ_ETH_CMD_CPRIO V_FW_EQ_ETH_CMD_CPRIO(1U) +#define F_FW_EQ_ETH_CMD_CPRIO V_FW_EQ_ETH_CMD_CPRIO(1U) #define S_FW_EQ_ETH_CMD_ONCHIP 18 #define M_FW_EQ_ETH_CMD_ONCHIP 0x1 #define V_FW_EQ_ETH_CMD_ONCHIP(x) ((x) << S_FW_EQ_ETH_CMD_ONCHIP) #define G_FW_EQ_ETH_CMD_ONCHIP(x) \ (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP) -#define F_FW_EQ_ETH_CMD_ONCHIP V_FW_EQ_ETH_CMD_ONCHIP(1U) +#define F_FW_EQ_ETH_CMD_ONCHIP V_FW_EQ_ETH_CMD_ONCHIP(1U) #define S_FW_EQ_ETH_CMD_PCIECHN 16 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3 @@ -4742,10 +4967,10 @@ struct fw_eq_eth_cmd { #define G_FW_EQ_ETH_CMD_PCIECHN(x) \ (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN) -#define S_FW_EQ_ETH_CMD_IQID 0 -#define M_FW_EQ_ETH_CMD_IQID 0xffff -#define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID) -#define G_FW_EQ_ETH_CMD_IQID(x) \ +#define S_FW_EQ_ETH_CMD_IQID 0 +#define M_FW_EQ_ETH_CMD_IQID 0xffff +#define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID) +#define G_FW_EQ_ETH_CMD_IQID(x) \ (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID) #define S_FW_EQ_ETH_CMD_DCAEN 31 @@ -4753,7 +4978,7 @@ struct fw_eq_eth_cmd { #define V_FW_EQ_ETH_CMD_DCAEN(x) ((x) << S_FW_EQ_ETH_CMD_DCAEN) #define G_FW_EQ_ETH_CMD_DCAEN(x) \ (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN) -#define F_FW_EQ_ETH_CMD_DCAEN V_FW_EQ_ETH_CMD_DCAEN(1U) +#define F_FW_EQ_ETH_CMD_DCAEN V_FW_EQ_ETH_CMD_DCAEN(1U) #define S_FW_EQ_ETH_CMD_DCACPU 26 #define M_FW_EQ_ETH_CMD_DCACPU 0x1f @@ -4806,10 +5031,10 @@ struct fw_eq_eth_cmd { (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE) #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U) -#define S_FW_EQ_ETH_CMD_VIID 16 -#define M_FW_EQ_ETH_CMD_VIID 0xfff -#define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID) -#define G_FW_EQ_ETH_CMD_VIID(x) \ +#define S_FW_EQ_ETH_CMD_VIID 16 +#define M_FW_EQ_ETH_CMD_VIID 0xfff +#define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID) +#define G_FW_EQ_ETH_CMD_VIID(x) \ (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID) struct fw_eq_ctrl_cmd { @@ -4822,16 +5047,16 @@ struct fw_eq_ctrl_cmd { __be64 eqaddr; }; -#define S_FW_EQ_CTRL_CMD_PFN 8 -#define M_FW_EQ_CTRL_CMD_PFN 0x7 -#define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN) -#define G_FW_EQ_CTRL_CMD_PFN(x) \ +#define S_FW_EQ_CTRL_CMD_PFN 8 +#define M_FW_EQ_CTRL_CMD_PFN 0x7 +#define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN) +#define G_FW_EQ_CTRL_CMD_PFN(x) \ (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN) -#define S_FW_EQ_CTRL_CMD_VFN 0 -#define M_FW_EQ_CTRL_CMD_VFN 0xff -#define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN) -#define G_FW_EQ_CTRL_CMD_VFN(x) \ +#define S_FW_EQ_CTRL_CMD_VFN 0 +#define M_FW_EQ_CTRL_CMD_VFN 0xff +#define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN) +#define G_FW_EQ_CTRL_CMD_VFN(x) \ (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN) #define S_FW_EQ_CTRL_CMD_ALLOC 31 @@ -4839,21 +5064,21 @@ struct fw_eq_ctrl_cmd { #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC) #define G_FW_EQ_CTRL_CMD_ALLOC(x) \ (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC) -#define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U) +#define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U) #define S_FW_EQ_CTRL_CMD_FREE 30 #define M_FW_EQ_CTRL_CMD_FREE 0x1 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE) #define G_FW_EQ_CTRL_CMD_FREE(x) \ (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE) -#define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U) +#define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U) #define S_FW_EQ_CTRL_CMD_MODIFY 29 #define M_FW_EQ_CTRL_CMD_MODIFY 0x1 #define V_FW_EQ_CTRL_CMD_MODIFY(x) ((x) << S_FW_EQ_CTRL_CMD_MODIFY) #define G_FW_EQ_CTRL_CMD_MODIFY(x) \ (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY) -#define F_FW_EQ_CTRL_CMD_MODIFY V_FW_EQ_CTRL_CMD_MODIFY(1U) +#define F_FW_EQ_CTRL_CMD_MODIFY V_FW_EQ_CTRL_CMD_MODIFY(1U) #define S_FW_EQ_CTRL_CMD_EQSTART 28 #define M_FW_EQ_CTRL_CMD_EQSTART 0x1 @@ -4867,7 +5092,7 @@ struct fw_eq_ctrl_cmd { #define V_FW_EQ_CTRL_CMD_EQSTOP(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTOP) #define G_FW_EQ_CTRL_CMD_EQSTOP(x) \ (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP) -#define F_FW_EQ_CTRL_CMD_EQSTOP V_FW_EQ_CTRL_CMD_EQSTOP(1U) +#define F_FW_EQ_CTRL_CMD_EQSTOP V_FW_EQ_CTRL_CMD_EQSTOP(1U) #define S_FW_EQ_CTRL_CMD_CMPLIQID 20 #define M_FW_EQ_CTRL_CMD_CMPLIQID 0xfff @@ -4933,14 +5158,14 @@ struct fw_eq_ctrl_cmd { #define V_FW_EQ_CTRL_CMD_CPRIO(x) ((x) << S_FW_EQ_CTRL_CMD_CPRIO) #define G_FW_EQ_CTRL_CMD_CPRIO(x) \ (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO) -#define F_FW_EQ_CTRL_CMD_CPRIO V_FW_EQ_CTRL_CMD_CPRIO(1U) +#define F_FW_EQ_CTRL_CMD_CPRIO V_FW_EQ_CTRL_CMD_CPRIO(1U) #define S_FW_EQ_CTRL_CMD_ONCHIP 18 #define M_FW_EQ_CTRL_CMD_ONCHIP 0x1 #define V_FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << S_FW_EQ_CTRL_CMD_ONCHIP) #define G_FW_EQ_CTRL_CMD_ONCHIP(x) \ (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP) -#define F_FW_EQ_CTRL_CMD_ONCHIP V_FW_EQ_CTRL_CMD_ONCHIP(1U) +#define F_FW_EQ_CTRL_CMD_ONCHIP V_FW_EQ_CTRL_CMD_ONCHIP(1U) #define S_FW_EQ_CTRL_CMD_PCIECHN 16 #define M_FW_EQ_CTRL_CMD_PCIECHN 0x3 @@ -4959,7 +5184,7 @@ struct fw_eq_ctrl_cmd { #define V_FW_EQ_CTRL_CMD_DCAEN(x) ((x) << S_FW_EQ_CTRL_CMD_DCAEN) #define G_FW_EQ_CTRL_CMD_DCAEN(x) \ (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN) -#define F_FW_EQ_CTRL_CMD_DCAEN V_FW_EQ_CTRL_CMD_DCAEN(1U) +#define F_FW_EQ_CTRL_CMD_DCAEN V_FW_EQ_CTRL_CMD_DCAEN(1U) #define S_FW_EQ_CTRL_CMD_DCACPU 26 #define M_FW_EQ_CTRL_CMD_DCACPU 0x1f @@ -4979,11 +5204,11 @@ struct fw_eq_ctrl_cmd { #define G_FW_EQ_CTRL_CMD_FBMAX(x) \ (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX) -#define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO 19 -#define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO 0x1 -#define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ +#define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO 19 +#define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO 0x1 +#define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) -#define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ +#define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO) #define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U) @@ -5009,16 +5234,16 @@ struct fw_eq_ofld_cmd { __be64 eqaddr; }; -#define S_FW_EQ_OFLD_CMD_PFN 8 -#define M_FW_EQ_OFLD_CMD_PFN 0x7 -#define V_FW_EQ_OFLD_CMD_PFN(x) ((x) << S_FW_EQ_OFLD_CMD_PFN) -#define G_FW_EQ_OFLD_CMD_PFN(x) \ +#define S_FW_EQ_OFLD_CMD_PFN 8 +#define M_FW_EQ_OFLD_CMD_PFN 0x7 +#define V_FW_EQ_OFLD_CMD_PFN(x) ((x) << S_FW_EQ_OFLD_CMD_PFN) +#define G_FW_EQ_OFLD_CMD_PFN(x) \ (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN) -#define S_FW_EQ_OFLD_CMD_VFN 0 -#define M_FW_EQ_OFLD_CMD_VFN 0xff -#define V_FW_EQ_OFLD_CMD_VFN(x) ((x) << S_FW_EQ_OFLD_CMD_VFN) -#define G_FW_EQ_OFLD_CMD_VFN(x) \ +#define S_FW_EQ_OFLD_CMD_VFN 0 +#define M_FW_EQ_OFLD_CMD_VFN 0xff +#define V_FW_EQ_OFLD_CMD_VFN(x) ((x) << S_FW_EQ_OFLD_CMD_VFN) +#define G_FW_EQ_OFLD_CMD_VFN(x) \ (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN) #define S_FW_EQ_OFLD_CMD_ALLOC 31 @@ -5026,21 +5251,21 @@ struct fw_eq_ofld_cmd { #define V_FW_EQ_OFLD_CMD_ALLOC(x) ((x) << S_FW_EQ_OFLD_CMD_ALLOC) #define G_FW_EQ_OFLD_CMD_ALLOC(x) \ (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC) -#define F_FW_EQ_OFLD_CMD_ALLOC V_FW_EQ_OFLD_CMD_ALLOC(1U) +#define F_FW_EQ_OFLD_CMD_ALLOC V_FW_EQ_OFLD_CMD_ALLOC(1U) #define S_FW_EQ_OFLD_CMD_FREE 30 #define M_FW_EQ_OFLD_CMD_FREE 0x1 #define V_FW_EQ_OFLD_CMD_FREE(x) ((x) << S_FW_EQ_OFLD_CMD_FREE) #define G_FW_EQ_OFLD_CMD_FREE(x) \ (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE) -#define F_FW_EQ_OFLD_CMD_FREE V_FW_EQ_OFLD_CMD_FREE(1U) +#define F_FW_EQ_OFLD_CMD_FREE V_FW_EQ_OFLD_CMD_FREE(1U) #define S_FW_EQ_OFLD_CMD_MODIFY 29 #define M_FW_EQ_OFLD_CMD_MODIFY 0x1 #define V_FW_EQ_OFLD_CMD_MODIFY(x) ((x) << S_FW_EQ_OFLD_CMD_MODIFY) #define G_FW_EQ_OFLD_CMD_MODIFY(x) \ (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY) -#define F_FW_EQ_OFLD_CMD_MODIFY V_FW_EQ_OFLD_CMD_MODIFY(1U) +#define F_FW_EQ_OFLD_CMD_MODIFY V_FW_EQ_OFLD_CMD_MODIFY(1U) #define S_FW_EQ_OFLD_CMD_EQSTART 28 #define M_FW_EQ_OFLD_CMD_EQSTART 0x1 @@ -5054,7 +5279,7 @@ struct fw_eq_ofld_cmd { #define V_FW_EQ_OFLD_CMD_EQSTOP(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTOP) #define G_FW_EQ_OFLD_CMD_EQSTOP(x) \ (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP) -#define F_FW_EQ_OFLD_CMD_EQSTOP V_FW_EQ_OFLD_CMD_EQSTOP(1U) +#define F_FW_EQ_OFLD_CMD_EQSTOP V_FW_EQ_OFLD_CMD_EQSTOP(1U) #define S_FW_EQ_OFLD_CMD_EQID 0 #define M_FW_EQ_OFLD_CMD_EQID 0xfffff @@ -5114,14 +5339,14 @@ struct fw_eq_ofld_cmd { #define V_FW_EQ_OFLD_CMD_CPRIO(x) ((x) << S_FW_EQ_OFLD_CMD_CPRIO) #define G_FW_EQ_OFLD_CMD_CPRIO(x) \ (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO) -#define F_FW_EQ_OFLD_CMD_CPRIO V_FW_EQ_OFLD_CMD_CPRIO(1U) +#define F_FW_EQ_OFLD_CMD_CPRIO V_FW_EQ_OFLD_CMD_CPRIO(1U) #define S_FW_EQ_OFLD_CMD_ONCHIP 18 #define M_FW_EQ_OFLD_CMD_ONCHIP 0x1 #define V_FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << S_FW_EQ_OFLD_CMD_ONCHIP) #define G_FW_EQ_OFLD_CMD_ONCHIP(x) \ (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP) -#define F_FW_EQ_OFLD_CMD_ONCHIP V_FW_EQ_OFLD_CMD_ONCHIP(1U) +#define F_FW_EQ_OFLD_CMD_ONCHIP V_FW_EQ_OFLD_CMD_ONCHIP(1U) #define S_FW_EQ_OFLD_CMD_PCIECHN 16 #define M_FW_EQ_OFLD_CMD_PCIECHN 0x3 @@ -5140,7 +5365,7 @@ struct fw_eq_ofld_cmd { #define V_FW_EQ_OFLD_CMD_DCAEN(x) ((x) << S_FW_EQ_OFLD_CMD_DCAEN) #define G_FW_EQ_OFLD_CMD_DCAEN(x) \ (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN) -#define F_FW_EQ_OFLD_CMD_DCAEN V_FW_EQ_OFLD_CMD_DCAEN(1U) +#define F_FW_EQ_OFLD_CMD_DCAEN V_FW_EQ_OFLD_CMD_DCAEN(1U) #define S_FW_EQ_OFLD_CMD_DCACPU 26 #define M_FW_EQ_OFLD_CMD_DCACPU 0x1f @@ -5160,11 +5385,11 @@ struct fw_eq_ofld_cmd { #define G_FW_EQ_OFLD_CMD_FBMAX(x) \ (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX) -#define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO 19 -#define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO 0x1 -#define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ +#define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO 19 +#define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO 0x1 +#define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) -#define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ +#define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO) #define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U) @@ -5226,74 +5451,80 @@ struct fw_vi_cmd { __be64 r10; }; -#define S_FW_VI_CMD_PFN 8 -#define M_FW_VI_CMD_PFN 0x7 -#define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN) -#define G_FW_VI_CMD_PFN(x) (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN) +#define S_FW_VI_CMD_PFN 8 +#define M_FW_VI_CMD_PFN 0x7 +#define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN) +#define G_FW_VI_CMD_PFN(x) \ + (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN) -#define S_FW_VI_CMD_VFN 0 -#define M_FW_VI_CMD_VFN 0xff -#define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN) -#define G_FW_VI_CMD_VFN(x) (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN) +#define S_FW_VI_CMD_VFN 0 +#define M_FW_VI_CMD_VFN 0xff +#define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN) +#define G_FW_VI_CMD_VFN(x) \ + (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN) -#define S_FW_VI_CMD_ALLOC 31 -#define M_FW_VI_CMD_ALLOC 0x1 -#define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC) -#define G_FW_VI_CMD_ALLOC(x) \ +#define S_FW_VI_CMD_ALLOC 31 +#define M_FW_VI_CMD_ALLOC 0x1 +#define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC) +#define G_FW_VI_CMD_ALLOC(x) \ (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC) -#define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U) +#define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U) -#define S_FW_VI_CMD_FREE 30 -#define M_FW_VI_CMD_FREE 0x1 -#define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE) -#define G_FW_VI_CMD_FREE(x) (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE) -#define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U) +#define S_FW_VI_CMD_FREE 30 +#define M_FW_VI_CMD_FREE 0x1 +#define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE) +#define G_FW_VI_CMD_FREE(x) \ + (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE) +#define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U) -#define S_FW_VI_CMD_TYPE 15 -#define M_FW_VI_CMD_TYPE 0x1 -#define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE) -#define G_FW_VI_CMD_TYPE(x) (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE) -#define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U) +#define S_FW_VI_CMD_TYPE 15 +#define M_FW_VI_CMD_TYPE 0x1 +#define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE) +#define G_FW_VI_CMD_TYPE(x) \ + (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE) +#define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U) -#define S_FW_VI_CMD_FUNC 12 -#define M_FW_VI_CMD_FUNC 0x7 -#define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC) -#define G_FW_VI_CMD_FUNC(x) (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC) +#define S_FW_VI_CMD_FUNC 12 +#define M_FW_VI_CMD_FUNC 0x7 +#define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC) +#define G_FW_VI_CMD_FUNC(x) \ + (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC) -#define S_FW_VI_CMD_VIID 0 -#define M_FW_VI_CMD_VIID 0xfff -#define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID) -#define G_FW_VI_CMD_VIID(x) (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID) +#define S_FW_VI_CMD_VIID 0 +#define M_FW_VI_CMD_VIID 0xfff +#define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID) +#define G_FW_VI_CMD_VIID(x) \ + (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID) -#define S_FW_VI_CMD_PORTID 4 -#define M_FW_VI_CMD_PORTID 0xf -#define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID) -#define G_FW_VI_CMD_PORTID(x) \ +#define S_FW_VI_CMD_PORTID 4 +#define M_FW_VI_CMD_PORTID 0xf +#define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID) +#define G_FW_VI_CMD_PORTID(x) \ (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID) -#define S_FW_VI_CMD_NORSS 11 -#define M_FW_VI_CMD_NORSS 0x1 -#define V_FW_VI_CMD_NORSS(x) ((x) << S_FW_VI_CMD_NORSS) -#define G_FW_VI_CMD_NORSS(x) \ +#define S_FW_VI_CMD_NORSS 11 +#define M_FW_VI_CMD_NORSS 0x1 +#define V_FW_VI_CMD_NORSS(x) ((x) << S_FW_VI_CMD_NORSS) +#define G_FW_VI_CMD_NORSS(x) \ (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS) -#define F_FW_VI_CMD_NORSS V_FW_VI_CMD_NORSS(1U) +#define F_FW_VI_CMD_NORSS V_FW_VI_CMD_NORSS(1U) -#define S_FW_VI_CMD_RSSSIZE 0 -#define M_FW_VI_CMD_RSSSIZE 0x7ff -#define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) -#define G_FW_VI_CMD_RSSSIZE(x) \ +#define S_FW_VI_CMD_RSSSIZE 0 +#define M_FW_VI_CMD_RSSSIZE 0x7ff +#define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) +#define G_FW_VI_CMD_RSSSIZE(x) \ (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE) -#define S_FW_VI_CMD_IDSIIQ 0 -#define M_FW_VI_CMD_IDSIIQ 0x3ff -#define V_FW_VI_CMD_IDSIIQ(x) ((x) << S_FW_VI_CMD_IDSIIQ) -#define G_FW_VI_CMD_IDSIIQ(x) \ +#define S_FW_VI_CMD_IDSIIQ 0 +#define M_FW_VI_CMD_IDSIIQ 0x3ff +#define V_FW_VI_CMD_IDSIIQ(x) ((x) << S_FW_VI_CMD_IDSIIQ) +#define G_FW_VI_CMD_IDSIIQ(x) \ (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ) -#define S_FW_VI_CMD_IDSEIQ 0 -#define M_FW_VI_CMD_IDSEIQ 0x3ff -#define V_FW_VI_CMD_IDSEIQ(x) ((x) << S_FW_VI_CMD_IDSEIQ) -#define G_FW_VI_CMD_IDSEIQ(x) \ +#define S_FW_VI_CMD_IDSEIQ 0 +#define M_FW_VI_CMD_IDSEIQ 0x3ff +#define V_FW_VI_CMD_IDSEIQ(x) ((x) << S_FW_VI_CMD_IDSEIQ) +#define G_FW_VI_CMD_IDSEIQ(x) \ (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ) /* Special VI_MAC command index ids */ @@ -5329,10 +5560,10 @@ struct fw_vi_mac_cmd { } u; }; -#define S_FW_VI_MAC_CMD_VIID 0 -#define M_FW_VI_MAC_CMD_VIID 0xfff -#define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID) -#define G_FW_VI_MAC_CMD_VIID(x) \ +#define S_FW_VI_MAC_CMD_VIID 0 +#define M_FW_VI_MAC_CMD_VIID 0xfff +#define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID) +#define G_FW_VI_MAC_CMD_VIID(x) \ (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID) #define S_FW_VI_MAC_CMD_FREEMACS 31 @@ -5361,12 +5592,12 @@ struct fw_vi_mac_cmd { #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID) #define G_FW_VI_MAC_CMD_VALID(x) \ (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID) -#define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U) +#define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U) -#define S_FW_VI_MAC_CMD_PRIO 12 -#define M_FW_VI_MAC_CMD_PRIO 0x7 -#define V_FW_VI_MAC_CMD_PRIO(x) ((x) << S_FW_VI_MAC_CMD_PRIO) -#define G_FW_VI_MAC_CMD_PRIO(x) \ +#define S_FW_VI_MAC_CMD_PRIO 12 +#define M_FW_VI_MAC_CMD_PRIO 0x7 +#define V_FW_VI_MAC_CMD_PRIO(x) ((x) << S_FW_VI_MAC_CMD_PRIO) +#define G_FW_VI_MAC_CMD_PRIO(x) \ (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO) #define S_FW_VI_MAC_CMD_SMAC_RESULT 10 @@ -5375,10 +5606,10 @@ struct fw_vi_mac_cmd { #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \ (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT) -#define S_FW_VI_MAC_CMD_IDX 0 -#define M_FW_VI_MAC_CMD_IDX 0x3ff -#define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX) -#define G_FW_VI_MAC_CMD_IDX(x) \ +#define S_FW_VI_MAC_CMD_IDX 0 +#define M_FW_VI_MAC_CMD_IDX 0x3ff +#define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX) +#define G_FW_VI_MAC_CMD_IDX(x) \ (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX) /* T4 max MTU supported */ @@ -5410,18 +5641,18 @@ struct fw_vi_rxmode_cmd { #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \ (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN) -#define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12 -#define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3 -#define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ +#define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12 +#define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3 +#define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN) -#define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ +#define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN) -#define S_FW_VI_RXMODE_CMD_BROADCASTEN 10 -#define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3 -#define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ +#define S_FW_VI_RXMODE_CMD_BROADCASTEN 10 +#define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3 +#define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN) -#define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ +#define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & M_FW_VI_RXMODE_CMD_BROADCASTEN) #define S_FW_VI_RXMODE_CMD_VLANEXEN 8 @@ -5449,21 +5680,21 @@ struct fw_vi_enable_cmd { #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN) #define G_FW_VI_ENABLE_CMD_IEN(x) \ (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN) -#define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U) +#define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U) #define S_FW_VI_ENABLE_CMD_EEN 30 #define M_FW_VI_ENABLE_CMD_EEN 0x1 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN) #define G_FW_VI_ENABLE_CMD_EEN(x) \ (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN) -#define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U) +#define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U) #define S_FW_VI_ENABLE_CMD_LED 29 #define M_FW_VI_ENABLE_CMD_LED 0x1 #define V_FW_VI_ENABLE_CMD_LED(x) ((x) << S_FW_VI_ENABLE_CMD_LED) #define G_FW_VI_ENABLE_CMD_LED(x) \ (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED) -#define F_FW_VI_ENABLE_CMD_LED V_FW_VI_ENABLE_CMD_LED(1U) +#define F_FW_VI_ENABLE_CMD_LED V_FW_VI_ENABLE_CMD_LED(1U) #define S_FW_VI_ENABLE_CMD_DCB_INFO 28 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1 @@ -5582,10 +5813,10 @@ struct fw_vi_stats_cmd { #define G_FW_VI_STATS_CMD_NSTATS(x) \ (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS) -#define S_FW_VI_STATS_CMD_IX 0 -#define M_FW_VI_STATS_CMD_IX 0x1f -#define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX) -#define G_FW_VI_STATS_CMD_IX(x) \ +#define S_FW_VI_STATS_CMD_IX 0 +#define M_FW_VI_STATS_CMD_IX 0x1f +#define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX) +#define G_FW_VI_STATS_CMD_IX(x) \ (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX) struct fw_acl_mac_cmd { @@ -5603,24 +5834,24 @@ struct fw_acl_mac_cmd { __u8 macaddr3[6]; }; -#define S_FW_ACL_MAC_CMD_PFN 8 -#define M_FW_ACL_MAC_CMD_PFN 0x7 -#define V_FW_ACL_MAC_CMD_PFN(x) ((x) << S_FW_ACL_MAC_CMD_PFN) -#define G_FW_ACL_MAC_CMD_PFN(x) \ +#define S_FW_ACL_MAC_CMD_PFN 8 +#define M_FW_ACL_MAC_CMD_PFN 0x7 +#define V_FW_ACL_MAC_CMD_PFN(x) ((x) << S_FW_ACL_MAC_CMD_PFN) +#define G_FW_ACL_MAC_CMD_PFN(x) \ (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN) -#define S_FW_ACL_MAC_CMD_VFN 0 -#define M_FW_ACL_MAC_CMD_VFN 0xff -#define V_FW_ACL_MAC_CMD_VFN(x) ((x) << S_FW_ACL_MAC_CMD_VFN) -#define G_FW_ACL_MAC_CMD_VFN(x) \ +#define S_FW_ACL_MAC_CMD_VFN 0 +#define M_FW_ACL_MAC_CMD_VFN 0xff +#define V_FW_ACL_MAC_CMD_VFN(x) ((x) << S_FW_ACL_MAC_CMD_VFN) +#define G_FW_ACL_MAC_CMD_VFN(x) \ (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN) -#define S_FW_ACL_MAC_CMD_EN 31 -#define M_FW_ACL_MAC_CMD_EN 0x1 -#define V_FW_ACL_MAC_CMD_EN(x) ((x) << S_FW_ACL_MAC_CMD_EN) -#define G_FW_ACL_MAC_CMD_EN(x) \ +#define S_FW_ACL_MAC_CMD_EN 31 +#define M_FW_ACL_MAC_CMD_EN 0x1 +#define V_FW_ACL_MAC_CMD_EN(x) ((x) << S_FW_ACL_MAC_CMD_EN) +#define G_FW_ACL_MAC_CMD_EN(x) \ (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN) -#define F_FW_ACL_MAC_CMD_EN V_FW_ACL_MAC_CMD_EN(1U) +#define F_FW_ACL_MAC_CMD_EN V_FW_ACL_MAC_CMD_EN(1U) struct fw_acl_vlan_cmd { __be32 op_to_vfn; @@ -5643,12 +5874,12 @@ struct fw_acl_vlan_cmd { #define G_FW_ACL_VLAN_CMD_VFN(x) \ (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN) -#define S_FW_ACL_VLAN_CMD_EN 31 -#define M_FW_ACL_VLAN_CMD_EN 0x1 -#define V_FW_ACL_VLAN_CMD_EN(x) ((x) << S_FW_ACL_VLAN_CMD_EN) -#define G_FW_ACL_VLAN_CMD_EN(x) \ +#define S_FW_ACL_VLAN_CMD_EN 31 +#define M_FW_ACL_VLAN_CMD_EN 0x1 +#define V_FW_ACL_VLAN_CMD_EN(x) ((x) << S_FW_ACL_VLAN_CMD_EN) +#define G_FW_ACL_VLAN_CMD_EN(x) \ (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN) -#define F_FW_ACL_VLAN_CMD_EN V_FW_ACL_VLAN_CMD_EN(1U) +#define F_FW_ACL_VLAN_CMD_EN V_FW_ACL_VLAN_CMD_EN(1U) #define S_FW_ACL_VLAN_CMD_DROPNOVLAN 7 #define M_FW_ACL_VLAN_CMD_DROPNOVLAN 0x1 @@ -5657,12 +5888,12 @@ struct fw_acl_vlan_cmd { (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN) #define F_FW_ACL_VLAN_CMD_DROPNOVLAN V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U) -#define S_FW_ACL_VLAN_CMD_FM 6 -#define M_FW_ACL_VLAN_CMD_FM 0x1 -#define V_FW_ACL_VLAN_CMD_FM(x) ((x) << S_FW_ACL_VLAN_CMD_FM) -#define G_FW_ACL_VLAN_CMD_FM(x) \ +#define S_FW_ACL_VLAN_CMD_FM 6 +#define M_FW_ACL_VLAN_CMD_FM 0x1 +#define V_FW_ACL_VLAN_CMD_FM(x) ((x) << S_FW_ACL_VLAN_CMD_FM) +#define G_FW_ACL_VLAN_CMD_FM(x) \ (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM) -#define F_FW_ACL_VLAN_CMD_FM V_FW_ACL_VLAN_CMD_FM(1U) +#define F_FW_ACL_VLAN_CMD_FM V_FW_ACL_VLAN_CMD_FM(1U) /* port capabilities bitmap */ enum fw_port_cap { @@ -5680,6 +5911,8 @@ enum fw_port_cap { FW_PORT_CAP_FEC = 0x0800, FW_PORT_CAP_TECHKR = 0x1000, FW_PORT_CAP_TECHKX4 = 0x2000, + FW_PORT_CAP_802_3_PAUSE = 0x4000, + FW_PORT_CAP_802_3_ASM_DIR = 0x8000, }; #define S_FW_PORT_AUXLINFO_MDI 3 @@ -5706,7 +5939,7 @@ enum fw_port_cap { #define M_FW_PORT_AUXLINFO_FEC 0x1 #define V_FW_PORT_AUXLINFO_FEC(x) ((x) << S_FW_PORT_AUXLINFO_FEC) #define G_FW_PORT_AUXLINFO_FEC(x) \ - (((x) >> S_FW_PORT_AUXLINFO_FEC) & M_FW_PORT_AUXLINFO_FEC) + (((x) >> S_FW_PORT_AUXLINFO_FEC) & M_FW_PORT_AUXLINFO_FEC) #define F_FW_PORT_AUXLINFO_FEC V_FW_PORT_AUXLINFO_FEC(1U) #define S_FW_PORT_RCAP_AUX 11 @@ -5733,6 +5966,12 @@ enum fw_port_cap { #define G_FW_PORT_CAP_ANEG(x) \ (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG) +#define S_FW_PORT_CAP_802_3 14 +#define M_FW_PORT_CAP_802_3 0x3 +#define V_FW_PORT_CAP_802_3(x) ((x) << S_FW_PORT_CAP_802_3) +#define G_FW_PORT_CAP_802_3(x) \ + (((x) >> S_FW_PORT_CAP_802_3) & M_FW_PORT_CAP_802_3) + enum fw_port_mdi { FW_PORT_CAP_MDI_UNCHANGED, FW_PORT_CAP_MDI_AUTO, @@ -5791,10 +6030,11 @@ enum fw_dcb_app_tlv_sf { }; enum fw_port_dcb_versions { + FW_PORT_DCB_VER_UNKNOWN, FW_PORT_DCB_VER_CEE1D0, FW_PORT_DCB_VER_CEE1D01, FW_PORT_DCB_VER_IEEE, - FW_PORT_DCB_VER_UNKNOWN=7 + FW_PORT_DCB_VER_AUTO=7 }; enum fw_port_dcb_cfg { @@ -5863,7 +6103,7 @@ struct fw_port_cmd { __u8 auxlinfo; __u8 dcbxdis_pkd; __u8 r8_lo; - __be16 lpcap; + __be16 lpacap; __be64 r9; } info; struct fw_port_diags { @@ -5885,6 +6125,7 @@ struct fw_port_cmd { __u8 r10_lo[5]; __u8 num_tcs_supported; __u8 pgrate[8]; + __u8 tsa[8]; } pgrate; struct fw_port_dcb_priorate { __u8 type; @@ -5911,7 +6152,7 @@ struct fw_port_cmd { struct fw_port_dcb_control { __u8 type; __u8 all_syncd_pkd; - __be16 pfc_state_to_app_state; + __be16 dcb_version_to_app_state; __be32 r11; __be64 r12; } control; @@ -5919,64 +6160,64 @@ struct fw_port_cmd { } u; }; -#define S_FW_PORT_CMD_READ 22 -#define M_FW_PORT_CMD_READ 0x1 -#define V_FW_PORT_CMD_READ(x) ((x) << S_FW_PORT_CMD_READ) -#define G_FW_PORT_CMD_READ(x) \ +#define S_FW_PORT_CMD_READ 22 +#define M_FW_PORT_CMD_READ 0x1 +#define V_FW_PORT_CMD_READ(x) ((x) << S_FW_PORT_CMD_READ) +#define G_FW_PORT_CMD_READ(x) \ (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ) -#define F_FW_PORT_CMD_READ V_FW_PORT_CMD_READ(1U) +#define F_FW_PORT_CMD_READ V_FW_PORT_CMD_READ(1U) -#define S_FW_PORT_CMD_PORTID 0 -#define M_FW_PORT_CMD_PORTID 0xf -#define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID) -#define G_FW_PORT_CMD_PORTID(x) \ +#define S_FW_PORT_CMD_PORTID 0 +#define M_FW_PORT_CMD_PORTID 0xf +#define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID) +#define G_FW_PORT_CMD_PORTID(x) \ (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID) -#define S_FW_PORT_CMD_ACTION 16 -#define M_FW_PORT_CMD_ACTION 0xffff -#define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION) -#define G_FW_PORT_CMD_ACTION(x) \ +#define S_FW_PORT_CMD_ACTION 16 +#define M_FW_PORT_CMD_ACTION 0xffff +#define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION) +#define G_FW_PORT_CMD_ACTION(x) \ (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION) -#define S_FW_PORT_CMD_OVLAN3 7 -#define M_FW_PORT_CMD_OVLAN3 0x1 -#define V_FW_PORT_CMD_OVLAN3(x) ((x) << S_FW_PORT_CMD_OVLAN3) -#define G_FW_PORT_CMD_OVLAN3(x) \ +#define S_FW_PORT_CMD_OVLAN3 7 +#define M_FW_PORT_CMD_OVLAN3 0x1 +#define V_FW_PORT_CMD_OVLAN3(x) ((x) << S_FW_PORT_CMD_OVLAN3) +#define G_FW_PORT_CMD_OVLAN3(x) \ (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3) -#define F_FW_PORT_CMD_OVLAN3 V_FW_PORT_CMD_OVLAN3(1U) +#define F_FW_PORT_CMD_OVLAN3 V_FW_PORT_CMD_OVLAN3(1U) -#define S_FW_PORT_CMD_OVLAN2 6 -#define M_FW_PORT_CMD_OVLAN2 0x1 -#define V_FW_PORT_CMD_OVLAN2(x) ((x) << S_FW_PORT_CMD_OVLAN2) -#define G_FW_PORT_CMD_OVLAN2(x) \ +#define S_FW_PORT_CMD_OVLAN2 6 +#define M_FW_PORT_CMD_OVLAN2 0x1 +#define V_FW_PORT_CMD_OVLAN2(x) ((x) << S_FW_PORT_CMD_OVLAN2) +#define G_FW_PORT_CMD_OVLAN2(x) \ (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2) -#define F_FW_PORT_CMD_OVLAN2 V_FW_PORT_CMD_OVLAN2(1U) +#define F_FW_PORT_CMD_OVLAN2 V_FW_PORT_CMD_OVLAN2(1U) -#define S_FW_PORT_CMD_OVLAN1 5 -#define M_FW_PORT_CMD_OVLAN1 0x1 -#define V_FW_PORT_CMD_OVLAN1(x) ((x) << S_FW_PORT_CMD_OVLAN1) -#define G_FW_PORT_CMD_OVLAN1(x) \ +#define S_FW_PORT_CMD_OVLAN1 5 +#define M_FW_PORT_CMD_OVLAN1 0x1 +#define V_FW_PORT_CMD_OVLAN1(x) ((x) << S_FW_PORT_CMD_OVLAN1) +#define G_FW_PORT_CMD_OVLAN1(x) \ (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1) -#define F_FW_PORT_CMD_OVLAN1 V_FW_PORT_CMD_OVLAN1(1U) +#define F_FW_PORT_CMD_OVLAN1 V_FW_PORT_CMD_OVLAN1(1U) -#define S_FW_PORT_CMD_OVLAN0 4 -#define M_FW_PORT_CMD_OVLAN0 0x1 -#define V_FW_PORT_CMD_OVLAN0(x) ((x) << S_FW_PORT_CMD_OVLAN0) -#define G_FW_PORT_CMD_OVLAN0(x) \ +#define S_FW_PORT_CMD_OVLAN0 4 +#define M_FW_PORT_CMD_OVLAN0 0x1 +#define V_FW_PORT_CMD_OVLAN0(x) ((x) << S_FW_PORT_CMD_OVLAN0) +#define G_FW_PORT_CMD_OVLAN0(x) \ (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0) -#define F_FW_PORT_CMD_OVLAN0 V_FW_PORT_CMD_OVLAN0(1U) +#define F_FW_PORT_CMD_OVLAN0 V_FW_PORT_CMD_OVLAN0(1U) -#define S_FW_PORT_CMD_IVLAN0 3 -#define M_FW_PORT_CMD_IVLAN0 0x1 -#define V_FW_PORT_CMD_IVLAN0(x) ((x) << S_FW_PORT_CMD_IVLAN0) -#define G_FW_PORT_CMD_IVLAN0(x) \ +#define S_FW_PORT_CMD_IVLAN0 3 +#define M_FW_PORT_CMD_IVLAN0 0x1 +#define V_FW_PORT_CMD_IVLAN0(x) ((x) << S_FW_PORT_CMD_IVLAN0) +#define G_FW_PORT_CMD_IVLAN0(x) \ (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0) -#define F_FW_PORT_CMD_IVLAN0 V_FW_PORT_CMD_IVLAN0(1U) +#define F_FW_PORT_CMD_IVLAN0 V_FW_PORT_CMD_IVLAN0(1U) -#define S_FW_PORT_CMD_TXIPG 3 -#define M_FW_PORT_CMD_TXIPG 0x1fff -#define V_FW_PORT_CMD_TXIPG(x) ((x) << S_FW_PORT_CMD_TXIPG) -#define G_FW_PORT_CMD_TXIPG(x) \ +#define S_FW_PORT_CMD_TXIPG 3 +#define M_FW_PORT_CMD_TXIPG 0x1fff +#define V_FW_PORT_CMD_TXIPG(x) ((x) << S_FW_PORT_CMD_TXIPG) +#define G_FW_PORT_CMD_TXIPG(x) \ (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG) #define S_FW_PORT_CMD_FORCE_PINFO 0 @@ -5991,12 +6232,12 @@ struct fw_port_cmd { #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS) #define G_FW_PORT_CMD_LSTATUS(x) \ (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS) -#define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U) +#define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U) -#define S_FW_PORT_CMD_LSPEED 24 -#define M_FW_PORT_CMD_LSPEED 0x3f -#define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED) -#define G_FW_PORT_CMD_LSPEED(x) \ +#define S_FW_PORT_CMD_LSPEED 24 +#define M_FW_PORT_CMD_LSPEED 0x3f +#define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED) +#define G_FW_PORT_CMD_LSPEED(x) \ (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED) #define S_FW_PORT_CMD_TXPAUSE 23 @@ -6004,21 +6245,21 @@ struct fw_port_cmd { #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE) #define G_FW_PORT_CMD_TXPAUSE(x) \ (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE) -#define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U) +#define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U) #define S_FW_PORT_CMD_RXPAUSE 22 #define M_FW_PORT_CMD_RXPAUSE 0x1 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE) #define G_FW_PORT_CMD_RXPAUSE(x) \ (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE) -#define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U) +#define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U) #define S_FW_PORT_CMD_MDIOCAP 21 #define M_FW_PORT_CMD_MDIOCAP 0x1 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP) #define G_FW_PORT_CMD_MDIOCAP(x) \ (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP) -#define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U) +#define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U) #define S_FW_PORT_CMD_MDIOADDR 16 #define M_FW_PORT_CMD_MDIOADDR 0x1f @@ -6031,19 +6272,19 @@ struct fw_port_cmd { #define V_FW_PORT_CMD_LPTXPAUSE(x) ((x) << S_FW_PORT_CMD_LPTXPAUSE) #define G_FW_PORT_CMD_LPTXPAUSE(x) \ (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE) -#define F_FW_PORT_CMD_LPTXPAUSE V_FW_PORT_CMD_LPTXPAUSE(1U) +#define F_FW_PORT_CMD_LPTXPAUSE V_FW_PORT_CMD_LPTXPAUSE(1U) #define S_FW_PORT_CMD_LPRXPAUSE 14 #define M_FW_PORT_CMD_LPRXPAUSE 0x1 #define V_FW_PORT_CMD_LPRXPAUSE(x) ((x) << S_FW_PORT_CMD_LPRXPAUSE) #define G_FW_PORT_CMD_LPRXPAUSE(x) \ (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE) -#define F_FW_PORT_CMD_LPRXPAUSE V_FW_PORT_CMD_LPRXPAUSE(1U) +#define F_FW_PORT_CMD_LPRXPAUSE V_FW_PORT_CMD_LPRXPAUSE(1U) -#define S_FW_PORT_CMD_PTYPE 8 -#define M_FW_PORT_CMD_PTYPE 0x1f -#define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE) -#define G_FW_PORT_CMD_PTYPE(x) \ +#define S_FW_PORT_CMD_PTYPE 8 +#define M_FW_PORT_CMD_PTYPE 0x1f +#define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE) +#define G_FW_PORT_CMD_PTYPE(x) \ (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE) #define S_FW_PORT_CMD_LINKDNRC 5 @@ -6063,21 +6304,27 @@ struct fw_port_cmd { #define V_FW_PORT_CMD_DCBXDIS(x) ((x) << S_FW_PORT_CMD_DCBXDIS) #define G_FW_PORT_CMD_DCBXDIS(x) \ (((x) >> S_FW_PORT_CMD_DCBXDIS) & M_FW_PORT_CMD_DCBXDIS) -#define F_FW_PORT_CMD_DCBXDIS V_FW_PORT_CMD_DCBXDIS(1U) +#define F_FW_PORT_CMD_DCBXDIS V_FW_PORT_CMD_DCBXDIS(1U) -#define S_FW_PORT_CMD_APPLY 7 -#define M_FW_PORT_CMD_APPLY 0x1 -#define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY) -#define G_FW_PORT_CMD_APPLY(x) \ +#define S_FW_PORT_CMD_APPLY 7 +#define M_FW_PORT_CMD_APPLY 0x1 +#define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY) +#define G_FW_PORT_CMD_APPLY(x) \ (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY) -#define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U) +#define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U) #define S_FW_PORT_CMD_ALL_SYNCD 7 #define M_FW_PORT_CMD_ALL_SYNCD 0x1 #define V_FW_PORT_CMD_ALL_SYNCD(x) ((x) << S_FW_PORT_CMD_ALL_SYNCD) #define G_FW_PORT_CMD_ALL_SYNCD(x) \ (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD) -#define F_FW_PORT_CMD_ALL_SYNCD V_FW_PORT_CMD_ALL_SYNCD(1U) +#define F_FW_PORT_CMD_ALL_SYNCD V_FW_PORT_CMD_ALL_SYNCD(1U) + +#define S_FW_PORT_CMD_DCB_VERSION 12 +#define M_FW_PORT_CMD_DCB_VERSION 0x7 +#define V_FW_PORT_CMD_DCB_VERSION(x) ((x) << S_FW_PORT_CMD_DCB_VERSION) +#define G_FW_PORT_CMD_DCB_VERSION(x) \ + (((x) >> S_FW_PORT_CMD_DCB_VERSION) & M_FW_PORT_CMD_DCB_VERSION) #define S_FW_PORT_CMD_PFC_STATE 8 #define M_FW_PORT_CMD_PFC_STATE 0xf @@ -6110,8 +6357,8 @@ enum fw_port_type { FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */ FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */ FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */ - FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G */ - FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */ + FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G/1G/100M */ + FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M */ FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */ FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */ FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */ @@ -6120,6 +6367,7 @@ enum fw_port_type { FW_PORT_TYPE_BP_AP = 10, /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */ FW_PORT_TYPE_BP4_AP = 11, /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */ FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */ + FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */ FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */ FW_PORT_TYPE_BP40_BA = 15, /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */ @@ -6151,6 +6399,7 @@ enum fw_port_mod_sub_type { FW_PORT_MOD_SUB_TYPE_88x3120=0x4, FW_PORT_MOD_SUB_TYPE_BCM84834=0x5, FW_PORT_MOD_SUB_TYPE_BCM5482=0x6, + FW_PORT_MOD_SUB_TYPE_BCM84856=0x7, FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8, /* @@ -6175,14 +6424,8 @@ enum fw_port_link_dn_rc { FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */ FW_PORT_LINK_DN_RESERVED7 }; - -/* port stats */ -#define FW_NUM_PORT_STATS 50 -#define FW_NUM_PORT_TX_STATS 23 -#define FW_NUM_PORT_RX_STATS 27 - enum fw_port_stats_tx_index { - FW_STAT_TX_PORT_BYTES_IX, + FW_STAT_TX_PORT_BYTES_IX = 0, FW_STAT_TX_PORT_FRAMES_IX, FW_STAT_TX_PORT_BCAST_IX, FW_STAT_TX_PORT_MCAST_IX, @@ -6204,11 +6447,12 @@ enum fw_port_stats_tx_index { FW_STAT_TX_PORT_PPP4_IX, FW_STAT_TX_PORT_PPP5_IX, FW_STAT_TX_PORT_PPP6_IX, - FW_STAT_TX_PORT_PPP7_IX + FW_STAT_TX_PORT_PPP7_IX, + FW_NUM_PORT_TX_STATS }; enum fw_port_stat_rx_index { - FW_STAT_RX_PORT_BYTES_IX, + FW_STAT_RX_PORT_BYTES_IX = 0, FW_STAT_RX_PORT_FRAMES_IX, FW_STAT_RX_PORT_BCAST_IX, FW_STAT_RX_PORT_MCAST_IX, @@ -6234,8 +6478,14 @@ enum fw_port_stat_rx_index { FW_STAT_RX_PORT_PPP5_IX, FW_STAT_RX_PORT_PPP6_IX, FW_STAT_RX_PORT_PPP7_IX, - FW_STAT_RX_PORT_LESS_64B_IX + FW_STAT_RX_PORT_LESS_64B_IX, + FW_STAT_RX_PORT_MAC_ERROR_IX, + FW_NUM_PORT_RX_STATS }; +/* port stats */ +#define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + \ + FW_NUM_PORT_RX_STATS) + struct fw_port_stats_cmd { __be32 op_to_portid; @@ -6327,7 +6577,7 @@ struct fw_port_stats_cmd { #define V_FW_PORT_STATS_CMD_TX(x) ((x) << S_FW_PORT_STATS_CMD_TX) #define G_FW_PORT_STATS_CMD_TX(x) \ (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX) -#define F_FW_PORT_STATS_CMD_TX V_FW_PORT_STATS_CMD_TX(1U) +#define F_FW_PORT_STATS_CMD_TX V_FW_PORT_STATS_CMD_TX(1U) #define S_FW_PORT_STATS_CMD_IX 0 #define M_FW_PORT_STATS_CMD_IX 0x3f @@ -6390,18 +6640,18 @@ struct fw_port_lb_stats_cmd { } u; }; -#define S_FW_PORT_LB_STATS_CMD_LBPORT 0 -#define M_FW_PORT_LB_STATS_CMD_LBPORT 0xf -#define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \ +#define S_FW_PORT_LB_STATS_CMD_LBPORT 0 +#define M_FW_PORT_LB_STATS_CMD_LBPORT 0xf +#define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \ ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT) -#define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \ +#define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \ (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT) -#define S_FW_PORT_LB_STATS_CMD_NSTATS 4 -#define M_FW_PORT_LB_STATS_CMD_NSTATS 0x7 -#define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \ +#define S_FW_PORT_LB_STATS_CMD_NSTATS 4 +#define M_FW_PORT_LB_STATS_CMD_NSTATS 0x7 +#define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \ ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS) -#define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \ +#define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \ (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS) #define S_FW_PORT_LB_STATS_CMD_BG_BM 0 @@ -6455,11 +6705,11 @@ struct fw_port_trace_cmd { (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN) #define F_FW_PORT_TRACE_CMD_DUPLEN V_FW_PORT_TRACE_CMD_DUPLEN(1U) -#define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE 8 -#define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE 0x1f -#define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ +#define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE 8 +#define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE 0x1f +#define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) -#define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ +#define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \ M_FW_PORT_TRACE_CMD_RUNTFLTSIZE) @@ -6477,11 +6727,11 @@ struct fw_port_trace_mmap_cmd { __u8 map[224]; }; -#define S_FW_PORT_TRACE_MMAP_CMD_PORTID 0 -#define M_FW_PORT_TRACE_MMAP_CMD_PORTID 0xf -#define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ +#define S_FW_PORT_TRACE_MMAP_CMD_PORTID 0 +#define M_FW_PORT_TRACE_MMAP_CMD_PORTID 0xf +#define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID) -#define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ +#define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \ M_FW_PORT_TRACE_MMAP_CMD_PORTID) @@ -6491,57 +6741,107 @@ struct fw_port_trace_mmap_cmd { #define G_FW_PORT_TRACE_MMAP_CMD_FID(x) \ (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID) -#define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN 29 -#define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN 0x1 -#define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ +#define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN 29 +#define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN 0x1 +#define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) -#define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ +#define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \ M_FW_PORT_TRACE_MMAP_CMD_MMAPEN) #define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U) -#define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 28 -#define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 0x1 -#define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ +#define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 28 +#define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 0x1 +#define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) -#define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ +#define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \ M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) -#define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN \ - V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U) +#define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U) -#define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 8 -#define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 0x1f -#define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ +#define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 8 +#define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 0x1f +#define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) -#define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ +#define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \ M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) -#define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0 -#define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0x1f -#define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ +#define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0 +#define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0x1f +#define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) -#define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ +#define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \ M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) -#define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 18 -#define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 0x3fff -#define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ +#define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 18 +#define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 0x3fff +#define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) -#define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ +#define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \ M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) -#define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0 -#define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0x3fff -#define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ +#define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0 +#define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0x3fff +#define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) -#define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ +#define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \ M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) +enum fw_ptp_subop { + + /* none */ + FW_PTP_SC_INIT_TIMER = 0x00, + FW_PTP_SC_TX_TYPE = 0x01, + + /* init */ + FW_PTP_SC_RXTIME_STAMP = 0x08, + FW_PTP_SC_RDRX_TYPE = 0x09, + + /* ts */ + FW_PTP_SC_ADJ_FREQ = 0x10, + FW_PTP_SC_ADJ_TIME = 0x11, + FW_PTP_SC_ADJ_FTIME = 0x12, + FW_PTP_SC_WALL_CLOCK = 0x13, + FW_PTP_SC_GET_TIME = 0x14, + FW_PTP_SC_SET_TIME = 0x15, +}; + +struct fw_ptp_cmd { + __be32 op_to_portid; + __be32 retval_len16; + union fw_ptp { + struct fw_ptp_sc { + __u8 sc; + __u8 r3[7]; + } scmd; + struct fw_ptp_init { + __u8 sc; + __u8 txchan; + __be16 absid; + __be16 mode; + __be16 r3; + } init; + struct fw_ptp_ts { + __u8 sc; + __u8 r3; + __be16 ppb; + __be32 r4; + __be64 tm; + } ts; + } u; + __be64 r3; +}; + +#define S_FW_PTP_CMD_PORTID 0 +#define M_FW_PTP_CMD_PORTID 0xf +#define V_FW_PTP_CMD_PORTID(x) ((x) << S_FW_PTP_CMD_PORTID) +#define G_FW_PTP_CMD_PORTID(x) \ + (((x) >> S_FW_PTP_CMD_PORTID) & M_FW_PTP_CMD_PORTID) + struct fw_rss_ind_tbl_cmd { __be32 op_to_viid; __be32 retval_len16; @@ -6789,94 +7089,91 @@ struct fw_rss_glb_config_cmd { #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 #define FW_RSS_GLB_CONFIG_CMD_MODE_MAX 1 -#define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8 -#define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1 -#define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ +#define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8 +#define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1 +#define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) -#define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ +#define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \ M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) -#define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN \ - V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U) +#define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U) -#define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7 -#define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 0x1 -#define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ +#define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7 +#define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 0x1 +#define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) -#define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ +#define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \ M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) -#define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \ +#define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \ V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U) -#define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6 -#define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 0x1 -#define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ +#define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6 +#define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 0x1 +#define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) -#define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ +#define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \ M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) -#define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \ +#define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \ V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U) -#define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5 -#define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 0x1 -#define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ +#define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5 +#define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 0x1 +#define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) -#define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ +#define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \ M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) -#define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \ +#define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \ V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U) -#define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4 -#define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 0x1 -#define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ +#define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4 +#define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 0x1 +#define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) -#define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ +#define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \ M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) -#define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \ +#define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \ V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U) -#define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3 -#define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 0x1 -#define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ +#define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3 +#define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 0x1 +#define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) -#define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ +#define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \ M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) -#define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN \ - V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U) +#define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U) -#define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2 -#define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 0x1 -#define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ +#define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2 +#define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 0x1 +#define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) -#define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ +#define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \ M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) -#define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN \ - V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U) +#define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U) -#define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1 -#define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 0x1 -#define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ +#define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1 +#define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 0x1 +#define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) -#define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ +#define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \ M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) -#define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \ +#define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \ V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U) -#define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0 -#define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0x1 -#define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ +#define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0 +#define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0x1 +#define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) -#define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ +#define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \ M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) -#define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \ +#define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \ V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U) struct fw_rss_vi_config_cmd { @@ -6903,52 +7200,52 @@ struct fw_rss_vi_config_cmd { #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \ (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID) -#define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16 -#define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff -#define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ +#define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16 +#define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff +#define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) -#define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ +#define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \ M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) -#define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4 -#define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1 -#define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ +#define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4 +#define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1 +#define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) -#define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ +#define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \ M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) -#define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \ +#define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \ V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U) -#define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3 -#define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1 -#define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ +#define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3 +#define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1 +#define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) -#define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ +#define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \ M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) -#define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \ +#define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \ V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U) -#define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2 -#define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1 -#define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ +#define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2 +#define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1 +#define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) -#define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ +#define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \ M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) -#define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \ +#define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \ V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U) -#define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1 -#define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1 -#define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ +#define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1 +#define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1 +#define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) -#define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ +#define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \ M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) -#define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \ +#define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \ V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U) #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0 @@ -7071,7 +7368,8 @@ enum fw_devlog_facility { FW_DEVLOG_FACILITY_FCOE = 0x2E, FW_DEVLOG_FACILITY_FOISCSI = 0x30, FW_DEVLOG_FACILITY_FOFCOE = 0x32, - FW_DEVLOG_FACILITY_MAX = 0x32, + FW_DEVLOG_FACILITY_CHNET = 0x34, + FW_DEVLOG_FACILITY_MAX = 0x34 }; /* @@ -7098,18 +7396,18 @@ struct fw_devlog_cmd { __be32 r3[2]; }; -#define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 28 -#define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 0xf -#define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ +#define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 28 +#define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 0xf +#define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) -#define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ +#define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) -#define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0 -#define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff -#define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ +#define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0 +#define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff +#define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) -#define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ +#define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \ M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) @@ -7118,8 +7416,9 @@ enum fw_watchdog_actions { FW_WATCHDOG_ACTION_FLR = 1, FW_WATCHDOG_ACTION_BYPASS = 2, FW_WATCHDOG_ACTION_TMPCHK = 3, + FW_WATCHDOG_ACTION_PAUSEOFF = 4, - FW_WATCHDOG_ACTION_MAX = 4, + FW_WATCHDOG_ACTION_MAX = 5, }; #define FW_WATCHDOG_MAX_TIMEOUT_SECS 60 @@ -7151,19 +7450,19 @@ struct fw_clip_cmd { __be32 r4[2]; }; -#define S_FW_CLIP_CMD_ALLOC 31 -#define M_FW_CLIP_CMD_ALLOC 0x1 -#define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC) -#define G_FW_CLIP_CMD_ALLOC(x) \ +#define S_FW_CLIP_CMD_ALLOC 31 +#define M_FW_CLIP_CMD_ALLOC 0x1 +#define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC) +#define G_FW_CLIP_CMD_ALLOC(x) \ (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC) -#define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U) +#define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U) -#define S_FW_CLIP_CMD_FREE 30 -#define M_FW_CLIP_CMD_FREE 0x1 -#define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE) -#define G_FW_CLIP_CMD_FREE(x) \ +#define S_FW_CLIP_CMD_FREE 30 +#define M_FW_CLIP_CMD_FREE 0x1 +#define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE) +#define G_FW_CLIP_CMD_FREE(x) \ (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE) -#define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U) +#define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U) /****************************************************************************** * F O i S C S I C O M M A N D s @@ -7173,10 +7472,10 @@ struct fw_clip_cmd { enum fw_chnet_iface_cmd_subop { FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0, - + FW_CHNET_IFACE_CMD_SUBOP_LINK_UP, FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN, - + FW_CHNET_IFACE_CMD_SUBOP_MTU_SET, FW_CHNET_IFACE_CMD_SUBOP_MTU_GET, @@ -7214,10 +7513,6 @@ struct fw_chnet_iface_cmd { #define G_FW_CHNET_IFACE_CMD_IFSTATE(x) \ (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE) -/****************************************************************************** - * F O F C O E C O M M A N D s - ************************************/ - struct fw_fcoe_res_info_cmd { __be32 op_to_read; __be32 retval_len16; @@ -7258,11 +7553,11 @@ struct fw_fcoe_link_cmd { #define G_FW_FCOE_LINK_CMD_PORTID(x) \ (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID) -#define S_FW_FCOE_LINK_CMD_SUB_OPCODE 24 -#define M_FW_FCOE_LINK_CMD_SUB_OPCODE 0xff -#define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ +#define S_FW_FCOE_LINK_CMD_SUB_OPCODE 24 +#define M_FW_FCOE_LINK_CMD_SUB_OPCODE 0xff +#define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE) -#define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ +#define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE) #define S_FW_FCOE_LINK_CMD_FCFI 0 @@ -7301,14 +7596,14 @@ struct fw_fcoe_vnp_cmd { #define V_FW_FCOE_VNP_CMD_ALLOC(x) ((x) << S_FW_FCOE_VNP_CMD_ALLOC) #define G_FW_FCOE_VNP_CMD_ALLOC(x) \ (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC) -#define F_FW_FCOE_VNP_CMD_ALLOC V_FW_FCOE_VNP_CMD_ALLOC(1U) +#define F_FW_FCOE_VNP_CMD_ALLOC V_FW_FCOE_VNP_CMD_ALLOC(1U) #define S_FW_FCOE_VNP_CMD_FREE 30 #define M_FW_FCOE_VNP_CMD_FREE 0x1 #define V_FW_FCOE_VNP_CMD_FREE(x) ((x) << S_FW_FCOE_VNP_CMD_FREE) #define G_FW_FCOE_VNP_CMD_FREE(x) \ (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE) -#define F_FW_FCOE_VNP_CMD_FREE V_FW_FCOE_VNP_CMD_FREE(1U) +#define F_FW_FCOE_VNP_CMD_FREE V_FW_FCOE_VNP_CMD_FREE(1U) #define S_FW_FCOE_VNP_CMD_MODIFY 29 #define M_FW_FCOE_VNP_CMD_MODIFY 0x1 @@ -7504,11 +7799,11 @@ struct fw_fcoe_stats_cmd { #define G_FW_FCOE_STATS_CMD_PORT(x) \ (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT) -#define S_FW_FCOE_STATS_CMD_PORT_VALID 7 -#define M_FW_FCOE_STATS_CMD_PORT_VALID 0x1 -#define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \ +#define S_FW_FCOE_STATS_CMD_PORT_VALID 7 +#define M_FW_FCOE_STATS_CMD_PORT_VALID 0x1 +#define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \ ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID) -#define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \ +#define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \ (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & M_FW_FCOE_STATS_CMD_PORT_VALID) #define F_FW_FCOE_STATS_CMD_PORT_VALID V_FW_FCOE_STATS_CMD_PORT_VALID(1U) @@ -7554,21 +7849,21 @@ struct fw_fcoe_fcf_cmd { #define V_FW_FCOE_FCF_CMD_FPMA(x) ((x) << S_FW_FCOE_FCF_CMD_FPMA) #define G_FW_FCOE_FCF_CMD_FPMA(x) \ (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA) -#define F_FW_FCOE_FCF_CMD_FPMA V_FW_FCOE_FCF_CMD_FPMA(1U) +#define F_FW_FCOE_FCF_CMD_FPMA V_FW_FCOE_FCF_CMD_FPMA(1U) #define S_FW_FCOE_FCF_CMD_SPMA 5 #define M_FW_FCOE_FCF_CMD_SPMA 0x1 #define V_FW_FCOE_FCF_CMD_SPMA(x) ((x) << S_FW_FCOE_FCF_CMD_SPMA) #define G_FW_FCOE_FCF_CMD_SPMA(x) \ (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA) -#define F_FW_FCOE_FCF_CMD_SPMA V_FW_FCOE_FCF_CMD_SPMA(1U) +#define F_FW_FCOE_FCF_CMD_SPMA V_FW_FCOE_FCF_CMD_SPMA(1U) #define S_FW_FCOE_FCF_CMD_LOGIN 4 #define M_FW_FCOE_FCF_CMD_LOGIN 0x1 #define V_FW_FCOE_FCF_CMD_LOGIN(x) ((x) << S_FW_FCOE_FCF_CMD_LOGIN) #define G_FW_FCOE_FCF_CMD_LOGIN(x) \ (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN) -#define F_FW_FCOE_FCF_CMD_LOGIN V_FW_FCOE_FCF_CMD_LOGIN(1U) +#define F_FW_FCOE_FCF_CMD_LOGIN V_FW_FCOE_FCF_CMD_LOGIN(1U) #define S_FW_FCOE_FCF_CMD_PORTID 0 #define M_FW_FCOE_FCF_CMD_PORTID 0xf @@ -7615,49 +7910,49 @@ struct fw_error_cmd { } u; }; -#define S_FW_ERROR_CMD_FATAL 4 -#define M_FW_ERROR_CMD_FATAL 0x1 -#define V_FW_ERROR_CMD_FATAL(x) ((x) << S_FW_ERROR_CMD_FATAL) -#define G_FW_ERROR_CMD_FATAL(x) \ +#define S_FW_ERROR_CMD_FATAL 4 +#define M_FW_ERROR_CMD_FATAL 0x1 +#define V_FW_ERROR_CMD_FATAL(x) ((x) << S_FW_ERROR_CMD_FATAL) +#define G_FW_ERROR_CMD_FATAL(x) \ (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL) -#define F_FW_ERROR_CMD_FATAL V_FW_ERROR_CMD_FATAL(1U) +#define F_FW_ERROR_CMD_FATAL V_FW_ERROR_CMD_FATAL(1U) -#define S_FW_ERROR_CMD_TYPE 0 -#define M_FW_ERROR_CMD_TYPE 0xf -#define V_FW_ERROR_CMD_TYPE(x) ((x) << S_FW_ERROR_CMD_TYPE) -#define G_FW_ERROR_CMD_TYPE(x) \ +#define S_FW_ERROR_CMD_TYPE 0 +#define M_FW_ERROR_CMD_TYPE 0xf +#define V_FW_ERROR_CMD_TYPE(x) ((x) << S_FW_ERROR_CMD_TYPE) +#define G_FW_ERROR_CMD_TYPE(x) \ (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE) -#define S_FW_ERROR_CMD_PFN 8 -#define M_FW_ERROR_CMD_PFN 0x7 -#define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) -#define G_FW_ERROR_CMD_PFN(x) \ +#define S_FW_ERROR_CMD_PFN 8 +#define M_FW_ERROR_CMD_PFN 0x7 +#define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) +#define G_FW_ERROR_CMD_PFN(x) \ (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) -#define S_FW_ERROR_CMD_VFN 0 -#define M_FW_ERROR_CMD_VFN 0xff -#define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) -#define G_FW_ERROR_CMD_VFN(x) \ +#define S_FW_ERROR_CMD_VFN 0 +#define M_FW_ERROR_CMD_VFN 0xff +#define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) +#define G_FW_ERROR_CMD_VFN(x) \ (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) -#define S_FW_ERROR_CMD_PFN 8 -#define M_FW_ERROR_CMD_PFN 0x7 -#define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) -#define G_FW_ERROR_CMD_PFN(x) \ +#define S_FW_ERROR_CMD_PFN 8 +#define M_FW_ERROR_CMD_PFN 0x7 +#define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) +#define G_FW_ERROR_CMD_PFN(x) \ (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) -#define S_FW_ERROR_CMD_VFN 0 -#define M_FW_ERROR_CMD_VFN 0xff -#define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) -#define G_FW_ERROR_CMD_VFN(x) \ +#define S_FW_ERROR_CMD_VFN 0 +#define M_FW_ERROR_CMD_VFN 0xff +#define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) +#define G_FW_ERROR_CMD_VFN(x) \ (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) -#define S_FW_ERROR_CMD_MV 15 -#define M_FW_ERROR_CMD_MV 0x1 -#define V_FW_ERROR_CMD_MV(x) ((x) << S_FW_ERROR_CMD_MV) -#define G_FW_ERROR_CMD_MV(x) \ +#define S_FW_ERROR_CMD_MV 15 +#define M_FW_ERROR_CMD_MV 0x1 +#define V_FW_ERROR_CMD_MV(x) ((x) << S_FW_ERROR_CMD_MV) +#define G_FW_ERROR_CMD_MV(x) \ (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV) -#define F_FW_ERROR_CMD_MV V_FW_ERROR_CMD_MV(1U) +#define F_FW_ERROR_CMD_MV V_FW_ERROR_CMD_MV(1U) struct fw_debug_cmd { __be32 op_type; @@ -7683,10 +7978,10 @@ struct fw_debug_cmd { } u; }; -#define S_FW_DEBUG_CMD_TYPE 0 -#define M_FW_DEBUG_CMD_TYPE 0xff -#define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) -#define G_FW_DEBUG_CMD_TYPE(x) \ +#define S_FW_DEBUG_CMD_TYPE 0 +#define M_FW_DEBUG_CMD_TYPE 0xff +#define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) +#define G_FW_DEBUG_CMD_TYPE(x) \ (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE) /****************************************************************************** @@ -7802,6 +8097,42 @@ enum pcie_fw_eval { */ +/****************************************************************************** + * P C I E F W P F 7 R E G I S T E R + **********************************************/ + +/* + * PF7 stores the Firmware Device Log parameters which allows Host Drivers to + * access the "devlog" which needing to contact firmware. The encoding is + * mostly the same as that returned by the DEVLOG command except for the size + * which is encoded as the number of entries in multiples-1 of 128 here rather + * than the memory size as is done in the DEVLOG command. Thus, 0 means 128 + * and 15 means 2048. This of course in turn constrains the allowed values + * for the devlog size ... + */ +#define PCIE_FW_PF_DEVLOG 7 + +#define S_PCIE_FW_PF_DEVLOG_NENTRIES128 28 +#define M_PCIE_FW_PF_DEVLOG_NENTRIES128 0xf +#define V_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \ + ((x) << S_PCIE_FW_PF_DEVLOG_NENTRIES128) +#define G_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \ + (((x) >> S_PCIE_FW_PF_DEVLOG_NENTRIES128) & \ + M_PCIE_FW_PF_DEVLOG_NENTRIES128) + +#define S_PCIE_FW_PF_DEVLOG_ADDR16 4 +#define M_PCIE_FW_PF_DEVLOG_ADDR16 0xffffff +#define V_PCIE_FW_PF_DEVLOG_ADDR16(x) ((x) << S_PCIE_FW_PF_DEVLOG_ADDR16) +#define G_PCIE_FW_PF_DEVLOG_ADDR16(x) \ + (((x) >> S_PCIE_FW_PF_DEVLOG_ADDR16) & M_PCIE_FW_PF_DEVLOG_ADDR16) + +#define S_PCIE_FW_PF_DEVLOG_MEMTYPE 0 +#define M_PCIE_FW_PF_DEVLOG_MEMTYPE 0xf +#define V_PCIE_FW_PF_DEVLOG_MEMTYPE(x) ((x) << S_PCIE_FW_PF_DEVLOG_MEMTYPE) +#define G_PCIE_FW_PF_DEVLOG_MEMTYPE(x) \ + (((x) >> S_PCIE_FW_PF_DEVLOG_MEMTYPE) & M_PCIE_FW_PF_DEVLOG_MEMTYPE) + + /****************************************************************************** * B I N A R Y H E A D E R F O R M A T **********************************************/ @@ -7825,14 +8156,15 @@ struct fw_hdr { __u8 intfver_fcoe; __u32 reserved2; __u32 reserved3; - __u32 magic; /* runtime or bootstrap fw */ + __be32 magic; /* runtime or bootstrap fw */ __be32 flags; __be32 reserved6[23]; }; enum fw_hdr_chip { FW_HDR_CHIP_T4, - FW_HDR_CHIP_T5 + FW_HDR_CHIP_T5, + FW_HDR_CHIP_T6 }; #define S_FW_HDR_FW_VER_MAJOR 24 @@ -7865,26 +8197,30 @@ enum fw_hdr_chip { enum { T4FW_VERSION_MAJOR = 0x01, - T4FW_VERSION_MINOR = 0x0b, - T4FW_VERSION_MICRO = 0x1b, + T4FW_VERSION_MINOR = 0x0e, + T4FW_VERSION_MICRO = 0x02, T4FW_VERSION_BUILD = 0x00, T5FW_VERSION_MAJOR = 0x01, - T5FW_VERSION_MINOR = 0x0b, - T5FW_VERSION_MICRO = 0x1b, + T5FW_VERSION_MINOR = 0x0e, + T5FW_VERSION_MICRO = 0x02, T5FW_VERSION_BUILD = 0x00, }; enum { + /* T4 + */ T4FW_HDR_INTFVER_NIC = 0x00, T4FW_HDR_INTFVER_VNIC = 0x00, T4FW_HDR_INTFVER_OFLD = 0x00, T4FW_HDR_INTFVER_RI = 0x00, - T4FW_HDR_INTFVER_ISCSIPDU = 0x00, + T4FW_HDR_INTFVER_ISCSIPDU= 0x00, T4FW_HDR_INTFVER_ISCSI = 0x00, T4FW_HDR_INTFVER_FCOEPDU = 0x00, T4FW_HDR_INTFVER_FCOE = 0x00, + /* T5 + */ T5FW_HDR_INTFVER_NIC = 0x00, T5FW_HDR_INTFVER_VNIC = 0x00, T5FW_HDR_INTFVER_OFLD = 0x00, @@ -7893,6 +8229,17 @@ enum { T5FW_HDR_INTFVER_ISCSI = 0x00, T5FW_HDR_INTFVER_FCOEPDU= 0x00, T5FW_HDR_INTFVER_FCOE = 0x00, + + /* T6 + */ + T6FW_HDR_INTFVER_NIC = 0x00, + T6FW_HDR_INTFVER_VNIC = 0x00, + T6FW_HDR_INTFVER_OFLD = 0x00, + T6FW_HDR_INTFVER_RI = 0x00, + T6FW_HDR_INTFVER_ISCSIPDU= 0x00, + T6FW_HDR_INTFVER_ISCSI = 0x00, + T6FW_HDR_INTFVER_FCOEPDU= 0x00, + T6FW_HDR_INTFVER_FCOE = 0x00, }; enum { diff --git a/sys/dev/cxgbe/firmware/t5fw-1.11.27.0.bin.uu b/sys/dev/cxgbe/firmware/t5fw-1.11.27.0.bin.uu deleted file mode 100644 index e22a66b0bffa..000000000000 --- a/sys/dev/cxgbe/firmware/t5fw-1.11.27.0.bin.uu +++ /dev/null @@ -1,9028 +0,0 @@ -/*- - * Copyright (c) 2014 Chelsio Communications, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ -begin-base64 644 t5fw -AAED6gELGwAAAQQHAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA -AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA -AAAAAAAAAAAAAAAAAAAAAAAAA80D3APkAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA -AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA -AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 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modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +begin-base64 644 t5fw +AAEEiAEOAgAAAQQIAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAABGoEeQSBAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 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a/sys/dev/cxgbe/firmware/t5fw_cfg_uwire.txt +++ b/sys/dev/cxgbe/firmware/t5fw_cfg_uwire.txt @@ -1,49 +1,34 @@ # Chelsio T5 Factory Default configuration file. # -# Copyright (C) 2010-2014 Chelsio Communications. All rights reserved. +# Copyright (C) 2010-2015 Chelsio Communications. All rights reserved. # -# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF -# THIS FILE WILL RESULT IN A NON-FUNCTIONAL T4 ADAPTER AND MAY RESULT -# IN PHYSICAL DAMAGE TO T4 ADAPTERS. +# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF THIS FILE +# WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE +# TO ADAPTERS. -# This file provides the default, power-on configuration for 4-port T4-based + +# This file provides the default, power-on configuration for 4-port T5-based # adapters shipped from the factory. These defaults are designed to address -# the needs of the vast majority of T4 customers. The basic idea is to have -# a default configuration which allows a customer to plug a T4 adapter in and -# have it work regardless of OS, driver or application except in the most -# unusual and/or demanding customer applications. +# the needs of the vast majority of Terminator customers. The basic idea is to +# have a default configuration which allows a customer to plug a Terminator +# adapter in and have it work regardless of OS, driver or application except in +# the most unusual and/or demanding customer applications. # -# Many of the T4 resources which are described by this configuration are -# finite. This requires balancing the configuration/operation needs of +# Many of the Terminator resources which are described by this configuration +# are finite. This requires balancing the configuration/operation needs of # device drivers across OSes and a large number of customer application. # # Some of the more important resources to allocate and their constaints are: -# 1. Virtual Interfaces: 128. -# 2. Ingress Queues with Free Lists: 1024. PCI-E SR-IOV Virtual Functions -# must use a power of 2 Ingress Queues. -# 3. Egress Queues: 128K. PCI-E SR-IOV Virtual Functions must use a -# power of 2 Egress Queues. -# 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV -# Virtual Functions based off of a Physical Function all get the -# same umber of MSI-X Vectors as the base Physical Function. -# Additionally, regardless of whether Virtual Functions are enabled or -# not, their MSI-X "needs" are counted by the PCI-E implementation. -# And finally, all Physical Funcations capable of supporting Virtual -# Functions (PF0-3) must have the same number of configured TotalVFs in -# their SR-IOV Capabilities. +# 1. Virtual Interfaces: 256. +# 2. Ingress Queues with Free Lists: 1024. +# 3. Egress Queues: 128K. +# 4. MSI-X Vectors: 1088. # 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination # address matching on Ingress Packets. # # Some of the important OS/Driver resource needs are: # 6. Some OS Drivers will manage all resources through a single Physical -# Function (currently PF0 but it could be any Physical Function). Thus, -# this "Unified PF" will need to have enough resources allocated to it -# to allow for this. And because of the MSI-X resource allocation -# constraints mentioned above, this probably means we'll either have to -# severely limit the TotalVFs if we continue to use PF0 as the Unified PF -# or we'll need to move the Unified PF into the PF4-7 range since those -# Physical Functions don't have any Virtual Functions associated with -# them. +# Function (currently PF4 but it could be any Physical Function). # 7. Some OS Drivers will manage different ports and functions (NIC, # storage, etc.) on different Physical Functions. For example, NIC # functions for ports 0-3 on PF0-3, FCoE on PF4, iSCSI on PF5, etc. @@ -64,12 +49,10 @@ # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF. # (Plus a few for Firmware Event Queues, etc.) # -# 9. Some customers will want to use T4's PCI-E SR-IOV Capability to allow -# Virtual Machines to directly access T4 functionality via SR-IOV -# Virtual Functions and "PCI Device Passthrough" -- this is especially -# true for the NIC application functionality. (Note that there is -# currently no ability to use the TOE, FCoE, iSCSI, etc. via Virtual -# Functions so this is in fact solely limited to NIC.) +# 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual +# Machines to directly access T6 functionality via SR-IOV Virtual Functions +# and "PCI Device Passthrough" -- this is especially true for the NIC +# application functionality. # @@ -80,7 +63,7 @@ rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp # PL_TIMEOUT register - pl_timeout_value = 200 # the timeout value in units of us + pl_timeout_value = 10000 # the timeout value in units of us # The following Scatter Gather Engine (SGE) settings assume a 4KB Host # Page Size and a 64B L1 Cache Line Size. It programs the @@ -138,7 +121,7 @@ # enable TP_OUT_CONFIG.IPIDSPLITMODE reg[0x7d04] = 0x00010000/0x00010000 - reg[0x7dc0] = 0x062f8849 # TP_SHIFT_CNT + reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT # TP_VLAN_PRI_MAP to select filter tuples and enable ServerSram # filter control: compact, fcoemask @@ -146,14 +129,14 @@ # filter tuples : fragmentation, mpshittype, macmatch, ethertype, # protocol, tos, vlan, vnic_id, port, fcoe # valid filterModes are described the Terminator 5 Data Book - filterMode = srvrsram, fragmentation, mpshittype, protocol, vlan, port, fcoe + filterMode = fcoemask, srvrsram, fragmentation, mpshittype, protocol, vlan, port, fcoe # filter tuples enforced in LE active region (equal to or subset of filterMode) filterMask = protocol, fcoe # Percentage of dynamic memory (in either the EDRAM or external MEM) # to use for TP RX payload - tp_pmrx = 30, 512 + tp_pmrx = 30 # TP RX payload page size tp_pmrx_pagesize = 64K @@ -163,7 +146,7 @@ # Percentage of dynamic memory (in either the EDRAM or external MEM) # to use for TP TX payload - tp_pmtx = 50, 512 + tp_pmtx = 50 # TP TX payload page size tp_pmtx_pagesize = 64K @@ -183,6 +166,9 @@ # TP_PARA_REG0 reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6 + # ULPRX iSCSI Page Sizes + reg[0x19168] = 0x04020100 # 64K, 16K, 8K and 4K + # LE_DB_CONFIG reg[0x19c04] = 0x00400000/0x00400000 # LE Server SRAM Enable @@ -218,7 +204,7 @@ # NEQ_NIC = 64 # NIC Egress Queues (FL, ETHCTRL/TX) # NMPSTCAM_NIC = 16 # NIC MPS TCAM Entries (NPORTS*4) # NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ) -# +# # NVI_OFLD = 0 # Offload uses NIC function to access ports # NFLIQ_OFLD = 16 # Offload Ingress Queues with Free Lists # NETHCTRL_OFLD = 0 # Offload Ethernet Control/TX Queues @@ -322,20 +308,21 @@ # PF2_INT = 8 # NCPUS # PF3_INT = 8 # NCPUS # PF0_3_INT = 32 # PF0_INT + PF1_INT + PF2_INT + PF3_INT -# +# # PF4_INT = 128 # NMSIX_UNIFIED # PF5_INT = 32 # NMSIX_STORAGE # PF6_INT = 32 # NMSIX_STORAGE # PF7_INT = 0 # Nothing Assigned # PF4_7_INT = 192 # PF4_INT + PF5_INT + PF6_INT + PF7_INT -# +# # PF0_7_INT = 224 # PF0_3_INT + PF4_7_INT -# +# # With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries) # but we'll lower that to 16 to make our total 64 and a nice power of 2 ... # # NVF = 16 + # For those OSes which manage different ports on different PFs, we need # only enough resources to support a single port's NIC application functions # on PF0-3. The below assumes that we're only doing NIC with NCPUS "Queue @@ -354,6 +341,7 @@ cmask = all # access to all channels pmask = 0x1 # access to only one port + [function "1"] nvf = 16 # NVF on this function wx_caps = all # write/execute permissions for all commands @@ -366,6 +354,7 @@ cmask = all # access to all channels pmask = 0x2 # access to only one port + [function "2"] nvf = 16 # NVF on this function wx_caps = all # write/execute permissions for all commands @@ -378,6 +367,7 @@ cmask = all # access to all channels pmask = 0x4 # access to only one port + [function "3"] nvf = 16 # NVF on this function wx_caps = all # write/execute permissions for all commands @@ -390,6 +380,7 @@ cmask = all # access to all channels pmask = 0x8 # access to only one port + # Some OS Drivers manage all application functions for all ports via PF4. # Thus we need to provide a large number of resources here. For Egress # Queues we need to account for both TX Queues as well as Free List Queues @@ -403,6 +394,7 @@ niqflint = 170 # NFLIQ_UNIFIED + NLFIQ_WD nethctrl = 100 # NETHCTRL_UNIFIED + NETHCTRL_WD neq = 256 # NEQ_UNIFIED + NEQ_WD + nqpcq = 12288 nexactf = 40 # NMPSTCAM_UNIFIED cmask = all # access to all channels pmask = all # access to all four ports ... @@ -412,7 +404,7 @@ nfilter = 496 # number of filter region entries nserver = 496 # number of server region entries nhash = 12288 # number of hash region entries - protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu + protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif tp_l2t = 3072 tp_ddp = 2 tp_ddp_iscsi = 2 @@ -420,6 +412,7 @@ tp_pbl = 5 tp_rq = 7 + # We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may # need to have Virtual Interfaces on each of the four ports with up to NCPUS # "Queue Sets" each. @@ -431,7 +424,7 @@ niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA nethctrl = 32 # NPORTS*NCPUS neq = 64 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) - nexactf = 4 # NPORTS + nexactf = 16 # (NPORTS *(no of snmc grp + 1 hw mac) + 1 anmc grp)) rounded to 16. cmask = all # access to all channels pmask = all # access to all four ports ... nserver = 16 @@ -444,6 +437,7 @@ iscsi_nconn_per_session = 1 iscsi_ninitiator_instance = 64 + [function "6"] wx_caps = all # write/execute permissions for all commands r_caps = all # read permissions for all commands @@ -463,6 +457,8 @@ fcoe_nfcf = 16 fcoe_nvnp = 32 fcoe_nssn = 1024 + fcoe_nfcb = 256 + # The following function, 1023, is not an actual PCIE function but is used to # configure and reserve firmware internal resources that come from the global @@ -477,6 +473,7 @@ nexactf = 8 # NPORTS + DCBX + nfilter = 16 # number of filter region entries + # For Virtual functions, we only allow NIC functionality and we only allow # access to one port (1 << PF). Note that because of limitations in the # Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL @@ -494,6 +491,7 @@ cmask = all # access to all channels pmask = 0x1 # access to only one port ... + [function "1/*"] # NVF wx_caps = 0x82 # DMAQ | VF r_caps = 0x86 # DMAQ | VF | PORT @@ -505,6 +503,7 @@ cmask = all # access to all channels pmask = 0x2 # access to only one port ... + [function "2/*"] # NVF wx_caps = 0x82 # DMAQ | VF r_caps = 0x86 # DMAQ | VF | PORT @@ -516,6 +515,7 @@ cmask = all # access to all channels pmask = 0x4 # access to only one port ... + [function "3/*"] # NVF wx_caps = 0x82 # DMAQ | VF r_caps = 0x86 # DMAQ | VF | PORT @@ -527,6 +527,7 @@ cmask = all # access to all channels pmask = 0x8 # access to only one port ... + # MPS features a 196608 bytes ingress buffer that is used for ingress buffering # for packets from the wire as well as the loopback path of the L2 switch. The # folling params control how the buffer memory is distributed and the L2 flow @@ -552,6 +553,7 @@ dcb_app_tlv[1] = 0x8914, ethertype, 3 dcb_app_tlv[2] = 3260, socketnum, 5 + [port "1"] dcb = ppp, dcbx bg_mem = 25 @@ -563,6 +565,7 @@ dcb_app_tlv[1] = 0x8914, ethertype, 3 dcb_app_tlv[2] = 3260, socketnum, 5 + [port "2"] dcb = ppp, dcbx bg_mem = 25 @@ -574,6 +577,7 @@ dcb_app_tlv[1] = 0x8914, ethertype, 3 dcb_app_tlv[2] = 3260, socketnum, 5 + [port "3"] dcb = ppp, dcbx bg_mem = 25 @@ -585,9 +589,10 @@ dcb_app_tlv[1] = 0x8914, ethertype, 3 dcb_app_tlv[2] = 3260, socketnum, 5 + [fini] - version = 0x14250016 - checksum = 0xafaf8723 + version = 0x1425001c + checksum = 0xb1c3ae38 # Total resources used by above allocations: # Virtual Interfaces: 104 diff --git a/sys/dev/cxgbe/t4_main.c b/sys/dev/cxgbe/t4_main.c index 5c8805967f00..8c96715c0bd6 100644 --- a/sys/dev/cxgbe/t4_main.c +++ b/sys/dev/cxgbe/t4_main.c @@ -6342,9 +6342,9 @@ sysctl_mps_tcam(SYSCTL_HANDLER_ARGS) F_FW_CMD_REQUEST | F_FW_CMD_READ | V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); - ldst_cmd.u.mps.fid_ctl = + ldst_cmd.u.mps.rplc.fid_idx = htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | - V_FW_LDST_CMD_CTL(i)); + V_FW_LDST_CMD_IDX(i)); rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mps"); @@ -6360,10 +6360,10 @@ sysctl_mps_tcam(SYSCTL_HANDLER_ARGS) rc = 0; } else { sbuf_printf(sb, " %08x %08x %08x %08x", - be32toh(ldst_cmd.u.mps.rplc127_96), - be32toh(ldst_cmd.u.mps.rplc95_64), - be32toh(ldst_cmd.u.mps.rplc63_32), - be32toh(ldst_cmd.u.mps.rplc31_0)); + be32toh(ldst_cmd.u.mps.rplc.rplc127_96), + be32toh(ldst_cmd.u.mps.rplc.rplc95_64), + be32toh(ldst_cmd.u.mps.rplc.rplc63_32), + be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); } } else sbuf_printf(sb, "%36s", ""); @@ -8533,10 +8533,17 @@ static devclass_t cxgbe_devclass, cxl_devclass; DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0); MODULE_VERSION(t4nex, 1); MODULE_DEPEND(t4nex, firmware, 1, 1, 1); +#ifdef DEV_NETMAP +MODULE_DEPEND(t4nex, netmap, 1, 1, 1); +#endif /* DEV_NETMAP */ + DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0); MODULE_VERSION(t5nex, 1); MODULE_DEPEND(t5nex, firmware, 1, 1, 1); +#ifdef DEV_NETMAP +MODULE_DEPEND(t5nex, netmap, 1, 1, 1); +#endif /* DEV_NETMAP */ DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0); MODULE_VERSION(cxgbe, 1); diff --git a/sys/dev/cxgbe/t4_netmap.c b/sys/dev/cxgbe/t4_netmap.c index f54a67fe94c0..a4afb8a25794 100644 --- a/sys/dev/cxgbe/t4_netmap.c +++ b/sys/dev/cxgbe/t4_netmap.c @@ -917,8 +917,6 @@ cxgbe_netmap_txsync(struct netmap_kring *kring, int flags) kring->nr_hwtail -= kring->nkr_num_slots; } - nm_txsync_finalize(kring); - return (0); } @@ -931,7 +929,7 @@ cxgbe_netmap_rxsync(struct netmap_kring *kring, int flags) struct port_info *pi = ifp->if_softc; struct adapter *sc = pi->adapter; struct sge_nm_rxq *nm_rxq = &sc->sge.nm_rxq[pi->first_nm_rxq + kring->ring_id]; - u_int const head = nm_rxsync_prologue(kring); + u_int const head = kring->rhead; u_int n; int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; @@ -993,8 +991,6 @@ cxgbe_netmap_rxsync(struct netmap_kring *kring, int flags) } } - nm_rxsync_finalize(kring); - return (0); } diff --git a/sys/dev/cxgbe/tom/t4_cpl_io.c b/sys/dev/cxgbe/tom/t4_cpl_io.c index fe9e425ea063..147802d927bf 100644 --- a/sys/dev/cxgbe/tom/t4_cpl_io.c +++ b/sys/dev/cxgbe/tom/t4_cpl_io.c @@ -501,25 +501,23 @@ write_tx_wr(void *dst, struct toepcb *toep, unsigned int immdlen, /* for iscsi, the mode & submode setting is per-packet */ if (toep->ulp_mode == ULP_MODE_ISCSI) - wr_ulp_mode = V_FW_OFLD_TX_DATA_WR_ULPMODE(ulp_mode >> 4) | - V_FW_OFLD_TX_DATA_WR_ULPSUBMODE(ulp_mode & 3); + wr_ulp_mode = V_TX_ULP_MODE(ulp_mode >> 4) | + V_TX_ULP_SUBMODE(ulp_mode & 3); else - wr_ulp_mode = V_FW_OFLD_TX_DATA_WR_ULPMODE(toep->ulp_mode); + wr_ulp_mode = V_TX_ULP_MODE(toep->ulp_mode); - txwr->lsodisable_to_proxy = - htobe32(wr_ulp_mode | - V_FW_OFLD_TX_DATA_WR_URGENT(0) | /* XXX */ - V_FW_OFLD_TX_DATA_WR_SHOVE(shove)); + txwr->lsodisable_to_flags = htobe32(wr_ulp_mode | V_TX_URG(0) | /*XXX*/ + V_TX_SHOVE(shove)); txwr->plen = htobe32(plen); if (txalign > 0) { struct tcpcb *tp = intotcpcb(toep->inp); if (plen < 2 * tp->t_maxseg || is_10G_port(toep->port)) - txwr->lsodisable_to_proxy |= + txwr->lsodisable_to_flags |= htobe32(F_FW_OFLD_TX_DATA_WR_LSODISABLE); else - txwr->lsodisable_to_proxy |= + txwr->lsodisable_to_flags |= htobe32(F_FW_OFLD_TX_DATA_WR_ALIGNPLD | (tp->t_flags & TF_NODELAY ? 0 : F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE)); diff --git a/sys/dev/e1000/e1000_regs.h b/sys/dev/e1000/e1000_regs.h index 5c2e3f788cbf..952a7dc31859 100644 --- a/sys/dev/e1000/e1000_regs.h +++ b/sys/dev/e1000/e1000_regs.h @@ -552,7 +552,7 @@ #define E1000_WVBR 0x03554 /* VM Wrong Behavior - RWS */ #define E1000_RPLOLR 0x05AF0 /* Replication Offload - RW */ #define E1000_UTA 0x0A000 /* Unicast Table Array - RW */ -#define E1000_IOVTCL 0x05BBC /* IOV Control Register */ +#define E1000_IOVCTL 0x05BBC /* IOV Control Register */ #define E1000_VMRCTL 0X05D80 /* Virtual Mirror Rule Control */ #define E1000_VMRVLAN 0x05D90 /* Virtual Mirror Rule VLAN */ #define E1000_VMRVM 0x05DA0 /* Virtual Mirror Rule VM */ diff --git a/sys/dev/e1000/if_em.c b/sys/dev/e1000/if_em.c index 8032345d09ae..d080168dedbb 100644 --- a/sys/dev/e1000/if_em.c +++ b/sys/dev/e1000/if_em.c @@ -344,6 +344,9 @@ devclass_t em_devclass; DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); MODULE_DEPEND(em, pci, 1, 1, 1); MODULE_DEPEND(em, ether, 1, 1, 1); +#ifdef DEV_NETMAP +MODULE_DEPEND(em, netmap, 1, 1, 1); +#endif /* DEV_NETMAP */ /********************************************************************* * Tunable default values. @@ -5995,7 +5998,9 @@ DB_COMMAND(em_reset_dev, em_ddb_reset_dev) dev = devclass_get_device(dc, index); if (device_get_driver(dev) == &em_driver) { struct adapter *adapter = device_get_softc(dev); + EM_CORE_LOCK(adapter); em_init_locked(adapter); + EM_CORE_UNLOCK(adapter); } } } diff --git a/sys/dev/e1000/if_igb.c b/sys/dev/e1000/if_igb.c index 6ac6eb63c987..384a46bc223d 100644 --- a/sys/dev/e1000/if_igb.c +++ b/sys/dev/e1000/if_igb.c @@ -322,6 +322,9 @@ static devclass_t igb_devclass; DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0); MODULE_DEPEND(igb, pci, 1, 1, 1); MODULE_DEPEND(igb, ether, 1, 1, 1); +#ifdef DEV_NETMAP +MODULE_DEPEND(igb, netmap, 1, 1, 1); +#endif /* DEV_NETMAP */ /********************************************************************* * Tunable default values. diff --git a/sys/dev/e1000/if_lem.c b/sys/dev/e1000/if_lem.c index 894a74a9db81..f34010e5c86e 100644 --- a/sys/dev/e1000/if_lem.c +++ b/sys/dev/e1000/if_lem.c @@ -286,6 +286,9 @@ extern devclass_t em_devclass; DRIVER_MODULE(lem, pci, lem_driver, em_devclass, 0, 0); MODULE_DEPEND(lem, pci, 1, 1, 1); MODULE_DEPEND(lem, ether, 1, 1, 1); +#ifdef DEV_NETMAP +MODULE_DEPEND(lem, netmap, 1, 1, 1); +#endif /* DEV_NETMAP */ /********************************************************************* * Tunable default values. diff --git a/sys/dev/gpio/gpiobus.c b/sys/dev/gpio/gpiobus.c index bf5632b42c80..3d6a6cfe4bdf 100644 --- a/sys/dev/gpio/gpiobus.c +++ b/sys/dev/gpio/gpiobus.c @@ -394,9 +394,14 @@ gpiobus_print_child(device_t dev, device_t child) devi = GPIOBUS_IVAR(child); memset(pins, 0, sizeof(pins)); retval += bus_print_child_header(dev, child); - retval += printf(" at pin(s) "); - gpiobus_print_pins(devi, pins, sizeof(pins)); - retval += printf("%s", pins); + if (devi->npins > 0) { + if (devi->npins > 1) + retval += printf(" at pins "); + else + retval += printf(" at pin "); + gpiobus_print_pins(devi, pins, sizeof(pins)); + retval += printf("%s", pins); + } resource_list_print_type(&devi->rl, "irq", SYS_RES_IRQ, "%ld"); retval += bus_print_child_footer(dev, child); diff --git a/sys/dev/hyperv/netvsc/hv_netvsc_drv_freebsd.c b/sys/dev/hyperv/netvsc/hv_netvsc_drv_freebsd.c index aa310c2fd89f..f86afecdfc81 100644 --- a/sys/dev/hyperv/netvsc/hv_netvsc_drv_freebsd.c +++ b/sys/dev/hyperv/netvsc/hv_netvsc_drv_freebsd.c @@ -343,7 +343,15 @@ netvsc_attach(device_t dev) IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_TSO; ifp->if_capenable |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_TSO; - ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_TSO; + /* + * Only enable UDP checksum offloading when it is on 2012R2 or + * later. UDP checksum offloading doesn't work on earlier + * Windows releases. + */ + if (hv_vmbus_protocal_version >= HV_VMBUS_VERSION_WIN8_1) + ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_TSO; + else + ifp->if_hwassist = CSUM_TCP | CSUM_TSO; ret = hv_rf_on_device_add(device_ctx, &device_info); if (ret != 0) { @@ -1108,7 +1116,17 @@ hn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) ifp->if_hwassist &= ~(CSUM_TCP | CSUM_UDP); } else { ifp->if_capenable |= IFCAP_TXCSUM; - ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP); + /* + * Only enable UDP checksum offloading on + * Windows Server 2012R2 or later releases. + */ + if (hv_vmbus_protocal_version >= + HV_VMBUS_VERSION_WIN8_1) { + ifp->if_hwassist |= + (CSUM_TCP | CSUM_UDP); + } else { + ifp->if_hwassist |= CSUM_TCP; + } } } diff --git a/sys/dev/ichwd/ichwd.c b/sys/dev/ichwd/ichwd.c index fdaac711ce3a..9f8704f814ca 100644 --- a/sys/dev/ichwd/ichwd.c +++ b/sys/dev/ichwd/ichwd.c @@ -194,6 +194,35 @@ static struct ichwd_device ichwd_devices[] = { { DEVICEID_LPT0, "Intel Lynx Point watchdog timer", 10 }, { DEVICEID_LPT1, "Intel Lynx Point watchdog timer", 10 }, { DEVICEID_LPT2, "Intel Lynx Point watchdog timer", 10 }, + { DEVICEID_LPT3, "Intel Lynx Point watchdog timer", 10 }, + { DEVICEID_LPT4, "Intel Lynx Point watchdog timer", 10 }, + { DEVICEID_LPT5, "Intel Lynx Point watchdog timer", 10 }, + { DEVICEID_LPT6, "Intel Lynx Point watchdog timer", 10 }, + { DEVICEID_LPT7, "Intel Lynx Point watchdog timer", 10 }, + { DEVICEID_LPT8, "Intel Lynx Point watchdog timer", 10 }, + { DEVICEID_LPT9, "Intel Lynx Point watchdog timer", 10 }, + { DEVICEID_LPT10, "Intel Lynx Point watchdog timer", 10 }, + { DEVICEID_LPT11, "Intel Lynx Point watchdog timer", 10 }, + { DEVICEID_LPT12, "Intel Lynx Point watchdog timer", 10 }, + { DEVICEID_LPT13, "Intel Lynx Point watchdog timer", 10 }, + { DEVICEID_LPT14, "Intel Lynx Point watchdog timer", 10 }, + { DEVICEID_LPT15, "Intel Lynx Point watchdog timer", 10 }, + { DEVICEID_LPT16, "Intel Lynx Point watchdog timer", 10 }, + { DEVICEID_LPT17, "Intel Lynx Point watchdog timer", 10 }, + { DEVICEID_LPT18, "Intel Lynx Point watchdog timer", 10 }, + { DEVICEID_LPT19, "Intel Lynx Point watchdog timer", 10 }, + { DEVICEID_LPT20, "Intel Lynx Point watchdog timer", 10 }, + { DEVICEID_LPT21, "Intel Lynx Point watchdog timer", 10 }, + { DEVICEID_LPT22, "Intel Lynx Point watchdog timer", 10 }, + { DEVICEID_LPT23, "Intel Lynx Point watchdog timer", 10 }, + { DEVICEID_LPT24, "Intel Lynx Point watchdog timer", 10 }, + { DEVICEID_LPT25, "Intel Lynx Point watchdog timer", 10 }, + { DEVICEID_LPT26, "Intel Lynx Point watchdog timer", 10 }, + { DEVICEID_LPT27, "Intel Lynx Point watchdog timer", 10 }, + { DEVICEID_LPT28, "Intel Lynx Point watchdog timer", 10 }, + { DEVICEID_LPT29, "Intel Lynx Point watchdog timer", 10 }, + { DEVICEID_LPT30, "Intel Lynx Point watchdog timer", 10 }, + { DEVICEID_LPT31, "Intel Lynx Point watchdog timer", 10 }, { DEVICEID_WCPT2, "Intel Wildcat Point watchdog timer", 10 }, { DEVICEID_WCPT4, "Intel Wildcat Point watchdog timer", 10 }, { DEVICEID_WCPT6, "Intel Wildcat Point watchdog timer", 10 }, diff --git a/sys/dev/isp/isp.c b/sys/dev/isp/isp.c index 0e600d1a7b60..9e8e29b1fc7d 100644 --- a/sys/dev/isp/isp.c +++ b/sys/dev/isp/isp.c @@ -65,16 +65,18 @@ __FBSDID("$FreeBSD$"); */ #define MBOX_DELAY_COUNT 1000000 / 100 #define ISP_MARK_PORTDB(a, b, c) \ - isp_prt(isp, ISP_LOG_SANCFG, \ - "Chan %d ISP_MARK_PORTDB@LINE %d", b, __LINE__); \ - isp_mark_portdb(a, b, c) + do { \ + isp_prt(isp, ISP_LOG_SANCFG, \ + "Chan %d ISP_MARK_PORTDB@LINE %d", (b), __LINE__); \ + isp_mark_portdb((a), (b), (c)); \ + } while (0) /* * Local static data */ static const char fconf[] = "Chan %d PortDB[%d] changed:\n current =(0x%x@0x%06x 0x%08x%08x 0x%08x%08x)\n database=(0x%x@0x%06x 0x%08x%08x 0x%08x%08x)"; static const char notresp[] = "Not RESPONSE in RESPONSE Queue (type 0x%x) @ idx %d (next %d) nlooked %d"; -static const char topology[] = "Chan %d WWPN 0x%08x%08x PortID 0x%06x N-Port Handle %d, Connection '%s'"; +static const char topology[] = "Chan %d WWPN 0x%08x%08x PortID 0x%06x handle 0x%x, Connection '%s'"; static const char bun[] = "bad underrun (count %d, resid %d, status %s)"; static const char lipd[] = "Chan %d LIP destroyed %d active commands"; static const char sacq[] = "unable to acquire scratch area"; @@ -2222,37 +2224,11 @@ isp_fibre_init_2400(ispsoftc_t *isp) isp->isp_state = ISP_INITSTATE; } -static void -isp_del_all_init_entries(ispsoftc_t *isp, int chan) -{ - fcparam *fcp = FCPARAM(isp, chan); - fcportdb_t *lp; - int i; - - for (i = 0; i < MAX_FC_TARG; i++) { - lp = &fcp->portdb[i]; - if (lp->state == FC_PORTDB_STATE_NIL || lp->target_mode) - continue; - lp->state = FC_PORTDB_STATE_NIL; - isp_async(isp, ISPASYNC_DEV_GONE, chan, lp, 1); - if (lp->autologin == 0) { - (void) isp_plogx(isp, chan, lp->handle, - lp->portid, - PLOGX_FLG_CMD_LOGO | - PLOGX_FLG_IMPLICIT | - PLOGX_FLG_FREE_NPHDL, 0); - } else { - lp->autologin = 0; - } - lp->new_prli_word3 = 0; - lp->new_portid = 0; - } -} - static void isp_mark_portdb(ispsoftc_t *isp, int chan, int disposition) { fcparam *fcp = FCPARAM(isp, chan); + fcportdb_t *lp; int i; if (chan < 0 || chan >= isp->isp_nchan) { @@ -2260,32 +2236,28 @@ isp_mark_portdb(ispsoftc_t *isp, int chan, int disposition) return; } for (i = 0; i < MAX_FC_TARG; i++) { - if (fcp->portdb[i].target_mode) { - if (disposition < 0) { - isp_prt(isp, ISP_LOGTINFO, "isp_mark_portdb: Chan %d zeroing handle 0x" "%04x port 0x%06x", chan, - fcp->portdb[i].handle, fcp->portdb[i].portid); - ISP_MEMZERO(&fcp->portdb[i], sizeof (fcportdb_t)); - } - continue; - } - if (disposition == 0) { - ISP_MEMZERO(&fcp->portdb[i], sizeof (fcportdb_t)); - } else { - switch (fcp->portdb[i].state) { - case FC_PORTDB_STATE_CHANGED: - case FC_PORTDB_STATE_PENDING_VALID: - case FC_PORTDB_STATE_VALID: - case FC_PORTDB_STATE_PROBATIONAL: - fcp->portdb[i].state = FC_PORTDB_STATE_PROBATIONAL; - break; - case FC_PORTDB_STATE_ZOMBIE: - break; - case FC_PORTDB_STATE_NIL: - default: - ISP_MEMZERO(&fcp->portdb[i], sizeof (fcportdb_t)); - fcp->portdb[i].state = FC_PORTDB_STATE_NIL; - break; + lp = &fcp->portdb[i]; + switch (lp->state) { + case FC_PORTDB_STATE_PROBATIONAL: + case FC_PORTDB_STATE_DEAD: + case FC_PORTDB_STATE_CHANGED: + case FC_PORTDB_STATE_PENDING_VALID: + case FC_PORTDB_STATE_VALID: + if (disposition > 0) + lp->state = FC_PORTDB_STATE_PROBATIONAL; + else { + lp->state = FC_PORTDB_STATE_NIL; + isp_async(isp, ISPASYNC_DEV_GONE, chan, lp); } + break; + case FC_PORTDB_STATE_ZOMBIE: + break; + case FC_PORTDB_STATE_NIL: + case FC_PORTDB_STATE_NEW: + default: + ISP_MEMZERO(lp, sizeof(*lp)); + lp->state = FC_PORTDB_STATE_NIL; + break; } } } @@ -2473,7 +2445,7 @@ isp_port_login(ispsoftc_t *isp, uint16_t handle, uint32_t portid) return (MBOX_PORT_ID_USED | (mbs.param[1] << 16)); case MBOX_LOOP_ID_USED: - isp_prt(isp, ISP_LOG_SANCFG|ISP_LOG_WARN1, "isp_port_login: handle 0x%04x in use for port id 0x%02xXXXX", handle, mbs.param[1] & 0xff); + isp_prt(isp, ISP_LOG_SANCFG|ISP_LOG_WARN1, "isp_port_login: handle 0x%x in use for port id 0x%02xXXXX", handle, mbs.param[1] & 0xff); return (MBOX_LOOP_ID_USED); case MBOX_COMMAND_COMPLETE: @@ -2559,7 +2531,7 @@ isp_getpdb(ispsoftc_t *isp, int chan, uint16_t id, isp_pdb_t *pdb, int dolock) pdb->portid = BITS2WORD_24XX(un.bill.pdb_portid_bits); ISP_MEMCPY(pdb->portname, un.bill.pdb_portname, 8); ISP_MEMCPY(pdb->nodename, un.bill.pdb_nodename, 8); - isp_prt(isp, ISP_LOG_SANCFG, "Chan %d Port 0x%06x flags 0x%x curstate %x", chan, pdb->portid, un.bill.pdb_flags, un.bill.pdb_curstate); + isp_prt(isp, ISP_LOG_SANCFG, "Chan %d handle 0x%x Port 0x%06x flags 0x%x curstate %x", chan, id, pdb->portid, un.bill.pdb_flags, un.bill.pdb_curstate); if (un.bill.pdb_curstate < PDB2400_STATE_PLOGI_DONE || un.bill.pdb_curstate > PDB2400_STATE_LOGGED_IN) { mbs.param[0] = MBOX_NOT_LOGGED_IN; if (dolock) { @@ -2587,6 +2559,7 @@ isp_dump_chip_portdb(ispsoftc_t *isp, int chan, int dolock) isp_pdb_t pdb; int lim, loopid; + isp_prt(isp, ISP_LOG_SANCFG|ISP_LOGINFO, "Chan %d chip port dump", chan); if (ISP_CAP_2KLOGIN(isp)) { lim = NPH_MAX_2K; } else { @@ -2988,16 +2961,8 @@ isp_pdb_sync(ispsoftc_t *isp, int chan) for (dbidx = 0; dbidx < MAX_FC_TARG; dbidx++) { lp = &fcp->portdb[dbidx]; - if (lp->state == FC_PORTDB_STATE_NIL || lp->target_mode) { - continue; - } - - if (lp->state == FC_PORTDB_STATE_VALID) { - if (dbidx != FL_ID) { - isp_prt(isp, - ISP_LOGERR, "portdb idx %d already valid", - dbidx); - } + if (lp->state == FC_PORTDB_STATE_NIL || + lp->state == FC_PORTDB_STATE_VALID) { continue; } @@ -3005,7 +2970,7 @@ isp_pdb_sync(ispsoftc_t *isp, int chan) case FC_PORTDB_STATE_PROBATIONAL: case FC_PORTDB_STATE_DEAD: lp->state = FC_PORTDB_STATE_NIL; - isp_async(isp, ISPASYNC_DEV_GONE, chan, lp, 0); + isp_async(isp, ISPASYNC_DEV_GONE, chan, lp); if (lp->autologin == 0) { (void) isp_plogx(isp, chan, lp->handle, lp->portid, @@ -3029,17 +2994,14 @@ isp_pdb_sync(ispsoftc_t *isp, int chan) isp_async(isp, ISPASYNC_DEV_ARRIVED, chan, lp); lp->new_prli_word3 = 0; lp->new_portid = 0; - lp->announced = 0; break; case FC_PORTDB_STATE_CHANGED: -/* - * XXXX FIX THIS - */ lp->state = FC_PORTDB_STATE_VALID; isp_async(isp, ISPASYNC_DEV_CHANGED, chan, lp); + lp->portid = lp->new_portid; + lp->prli_word3 = lp->new_prli_word3; lp->new_prli_word3 = 0; lp->new_portid = 0; - lp->announced = 0; break; case FC_PORTDB_STATE_PENDING_VALID: lp->portid = lp->new_portid; @@ -3050,13 +3012,12 @@ isp_pdb_sync(ispsoftc_t *isp, int chan) lp->new_prli_word3 = 0; lp->new_portid = 0; } - lp->announced = 0; break; case FC_PORTDB_STATE_ZOMBIE: break; default: isp_prt(isp, ISP_LOGWARN, - "isp_scan_loop: state %d for idx %d", + "isp_pdb_sync: state %d for idx %d", lp->state, dbidx); isp_dump_portdb(isp, chan); } @@ -3127,7 +3088,6 @@ isp_scan_loop(ispsoftc_t *isp, int chan) isp_prt(isp, ISP_LOG_SANCFG, "Chan %d FC scan loop 0..%d", chan, lim-1); - /* * Run through the list and get the port database info for each one. */ @@ -3211,6 +3171,9 @@ isp_scan_loop(ispsoftc_t *isp, int chan) */ if (tmp.node_wwn == 0 || tmp.port_wwn == 0 || tmp.portid == 0) { int a, b, c; + isp_prt(isp, ISP_LOGWARN, + "Chan %d bad pdb (WWNN %016jx, WWPN %016jx, PortID %06x, W3 0x%x, H 0x%x) @ handle 0x%x", + chan, tmp.node_wwn, tmp.port_wwn, tmp.portid, tmp.prli_word3, tmp.handle, handle); a = (tmp.node_wwn == 0); b = (tmp.port_wwn == 0); c = (tmp.portid == 0); @@ -3220,13 +3183,10 @@ isp_scan_loop(ispsoftc_t *isp, int chan) tmp.port_wwn = isp_get_wwn(isp, chan, handle, 0); if (tmp.node_wwn && tmp.port_wwn) { - isp_prt(isp, ISP_LOGINFO, "DODGED!"); + isp_prt(isp, ISP_LOGWARN, "DODGED!"); goto cont; } } - isp_prt(isp, ISP_LOGWARN, - "Chan %d bad pdb (%1d%1d%1d) @ handle 0x%x", chan, - a, b, c, handle); isp_dump_portdb(isp, chan); continue; } @@ -3234,30 +3194,19 @@ isp_scan_loop(ispsoftc_t *isp, int chan) /* * Now search the entire port database - * for the same Port and Node WWN. + * for the same Port WWN. */ - for (i = 0; i < MAX_FC_TARG; i++) { - lp = &fcp->portdb[i]; - - if (lp->state == FC_PORTDB_STATE_NIL || lp->target_mode) { - continue; - } - if (lp->node_wwn != tmp.node_wwn) { - continue; - } - if (lp->port_wwn != tmp.port_wwn) { - continue; - } - + if (isp_find_pdb_by_wwn(isp, chan, tmp.port_wwn, &lp)) { /* * Okay- we've found a non-nil entry that matches. * Check to make sure it's probational or a zombie. */ if (lp->state != FC_PORTDB_STATE_PROBATIONAL && - lp->state != FC_PORTDB_STATE_ZOMBIE) { + lp->state != FC_PORTDB_STATE_ZOMBIE && + lp->state != FC_PORTDB_STATE_VALID) { isp_prt(isp, ISP_LOGERR, "Chan %d [%d] not probational/zombie (0x%x)", - chan, i, lp->state); + chan, FC_PORTDB_TGT(isp, chan, lp), lp->state); isp_dump_portdb(isp, chan); ISP_MARK_PORTDB(isp, chan, 1); isp_prt(isp, ISP_LOG_SANCFG, "Chan %d FC scan loop DONE (bad)", chan); @@ -3269,6 +3218,7 @@ isp_scan_loop(ispsoftc_t *isp, int chan) * automatically. */ lp->autologin = 1; + lp->node_wwn = tmp.node_wwn; /* * Check to make see if really still the same @@ -3279,7 +3229,7 @@ isp_scan_loop(ispsoftc_t *isp, int chan) lp->new_prli_word3 = tmp.prli_word3; lp->state = FC_PORTDB_STATE_PENDING_VALID; isp_prt(isp, ISP_LOG_SANCFG, "Chan %d Loop Port 0x%06x@0x%04x Pending Valid", chan, tmp.portid, tmp.handle); - break; + continue; } /* @@ -3296,13 +3246,6 @@ isp_scan_loop(ispsoftc_t *isp, int chan) lp->state = FC_PORTDB_STATE_CHANGED; lp->new_portid = tmp.portid; lp->new_prli_word3 = tmp.prli_word3; - break; - } - - /* - * Did we find and update an old entry? - */ - if (i < MAX_FC_TARG) { continue; } @@ -3311,9 +3254,6 @@ isp_scan_loop(ispsoftc_t *isp, int chan) * for it and save info for later disposition. */ for (i = 0; i < MAX_FC_TARG; i++) { - if (fcp->portdb[i].target_mode) { - continue; - } if (fcp->portdb[i].state == FC_PORTDB_STATE_NIL) { break; } @@ -3713,7 +3653,7 @@ isp_scan_fabric(ispsoftc_t *isp, int chan) * that have the same domain and area code as our own * portid. */ - if (ISP_CAP_MULTI_ID(isp)) { + if (ISP_CAP_MULTI_ID(isp) && isp->isp_nchan > 1) { if ((portid >> 8) == (fcp->isp_portid >> 8)) { isp_prt(isp, ISP_LOG_SANCFG, "Chan %d skip PortID 0x%06x", @@ -3739,7 +3679,7 @@ isp_scan_fabric(ispsoftc_t *isp, int chan) for (dbidx = 0; dbidx < MAX_FC_TARG; dbidx++) { lp = &fcp->portdb[dbidx]; - if (lp->state != FC_PORTDB_STATE_PROBATIONAL || lp->target_mode) { + if (lp->state != FC_PORTDB_STATE_PROBATIONAL) { continue; } if (lp->portid == portid) { @@ -3781,7 +3721,7 @@ isp_scan_fabric(ispsoftc_t *isp, int chan) if (r != 0) { lp->new_portid = portid; lp->state = FC_PORTDB_STATE_DEAD; - isp_prt(isp, ISP_LOG_SANCFG, "Chan %d Fabric Port 0x%06x is dead", chan, portid); + isp_prt(isp, ISP_LOG_SANCFG, "Chan %d Fabric PortID 0x%06x handle 0x%x is dead (%d)", chan, portid, lp->handle, r); continue; } @@ -3797,7 +3737,7 @@ isp_scan_fabric(ispsoftc_t *isp, int chan) if (pdb.handle != lp->handle || pdb.portid != portid || wwpn != lp->port_wwn || - wwnn != lp->node_wwn) { + (lp->node_wwn != 0 && wwnn != lp->node_wwn)) { isp_prt(isp, ISP_LOG_SANCFG, fconf, chan, dbidx, pdb.handle, pdb.portid, (uint32_t) (wwnn >> 32), (uint32_t) wwnn, @@ -3815,8 +3755,9 @@ isp_scan_fabric(ispsoftc_t *isp, int chan) * portid consistency after re-login. * */ - if (isp_login_device(isp, chan, portid, &pdb, - &oldhandle)) { + if ((fcp->role & ISP_ROLE_INITIATOR) == 0 || + isp_login_device(isp, chan, portid, &pdb, + &oldhandle)) { lp->new_portid = portid; lp->state = FC_PORTDB_STATE_DEAD; if (fcp->isp_loopstate != @@ -3837,7 +3778,7 @@ isp_scan_fabric(ispsoftc_t *isp, int chan) MAKE_WWN_FROM_NODE_NAME(wwnn, pdb.nodename); MAKE_WWN_FROM_NODE_NAME(wwpn, pdb.portname); if (wwpn != lp->port_wwn || - wwnn != lp->node_wwn) { + (lp->node_wwn != 0 && wwnn != lp->node_wwn)) { isp_prt(isp, ISP_LOGWARN, "changed WWN" " after relogin"); lp->new_portid = portid; @@ -3875,6 +3816,9 @@ isp_scan_fabric(ispsoftc_t *isp, int chan) continue; } + if ((fcp->role & ISP_ROLE_INITIATOR) == 0) + continue; + /* * Ah- a new entry. Search the database again for all non-NIL * entries to make sure we never ever make a new database entry @@ -3888,12 +3832,6 @@ isp_scan_fabric(ispsoftc_t *isp, int chan) lp <= &fcp->portdb[SNS_ID]) { continue; } - /* - * Skip any target mode entries. - */ - if (lp->target_mode) { - continue; - } if (lp->state == FC_PORTDB_STATE_NIL) { if (dbidx == MAX_FC_TARG) { dbidx = lp - fcp->portdb; @@ -3966,10 +3904,9 @@ isp_scan_fabric(ispsoftc_t *isp, int chan) if (dbidx >= FL_ID && dbidx <= SNS_ID) { continue; } - if (fcp->portdb[dbidx].target_mode) { - continue; - } - if (fcp->portdb[dbidx].node_wwn == wwnn && fcp->portdb[dbidx].port_wwn == wwpn) { + if ((fcp->portdb[dbidx].node_wwn == wwnn || + fcp->portdb[dbidx].node_wwn == 0) && + fcp->portdb[dbidx].port_wwn == wwpn) { break; } } @@ -4007,6 +3944,7 @@ isp_scan_fabric(ispsoftc_t *isp, int chan) */ lp = &fcp->portdb[dbidx]; lp->handle = handle; + lp->node_wwn = wwnn; lp->new_portid = portid; lp->new_prli_word3 = nr; if (lp->portid != portid || lp->prli_word3 != nr) { @@ -4393,7 +4331,7 @@ isp_start(XS_T *xs) isp_prt(isp, ISP_LOGDEBUG2, "XS_TGT(xs)=%d", target); lp = &fcp->portdb[target]; if (target < 0 || target >= MAX_FC_TARG || - lp->dev_map_idx == 0) { + lp->is_target == 0) { XS_SETERR(xs, HBA_SELTIMEOUT); return (CMD_COMPLETE); } @@ -4406,7 +4344,6 @@ isp_start(XS_T *xs) XS_SETERR(xs, HBA_SELTIMEOUT); return (CMD_COMPLETE); } - lp->dirty = 1; } else { sdparam *sdp = SDPARAM(isp, XS_CHANNEL(xs)); if ((sdp->role & ISP_ROLE_INITIATOR) == 0) { @@ -4417,6 +4354,7 @@ isp_start(XS_T *xs) if (sdp->update) { isp_spi_update(isp, XS_CHANNEL(xs)); } + lp = NULL; } start_again: @@ -4703,7 +4641,7 @@ isp_control(ispsoftc_t *isp, ispctl_t ctl, ...) break; } lp = &fcp->portdb[tgt]; - if (lp->dev_map_idx == 0 || + if (lp->is_target == 0 || lp->state != FC_PORTDB_STATE_VALID) { isp_prt(isp, ISP_LOGWARN, "Chan %d abort of no longer valid target %d", chan, tgt); break; @@ -4793,7 +4731,7 @@ isp_control(ispsoftc_t *isp, ispctl_t ctl, ...) break; } lp = &fcp->portdb[tgt]; - if (lp->dev_map_idx == 0 || + if (lp->is_target == 0 || lp->state != FC_PORTDB_STATE_VALID) { isp_prt(isp, ISP_LOGWARN, "Chan %d abort of no longer valid target %d", chan, tgt); break; @@ -5004,12 +4942,6 @@ isp_control(ispsoftc_t *isp, ispctl_t ctl, ...) role = va_arg(ap, int); va_end(ap); if (IS_FC(isp)) { -#ifdef ISP_TARGET_MODE - if ((role & ISP_ROLE_TARGET) == 0) - isp_del_all_wwn_entries(isp, chan); -#endif - if ((role & ISP_ROLE_INITIATOR) == 0) - isp_del_all_init_entries(isp, chan); r = isp_fc_change_role(isp, chan, role); } else { SDPARAM(isp, chan)->role = role; @@ -7887,26 +7819,26 @@ isp_setdfltfcparm(ispsoftc_t *isp, int chan) * not disturb an already active list of commands. */ -void +int isp_reinit(ispsoftc_t *isp, int do_load_defaults) { - int i; + int i, res = 0; isp_reset(isp, do_load_defaults); - if (isp->isp_state != ISP_RESETSTATE) { + res = EIO; isp_prt(isp, ISP_LOGERR, "%s: cannot reset card", __func__); ISP_DISABLE_INTS(isp); goto cleanup; } isp_init(isp); - if (isp->isp_state == ISP_INITSTATE) { isp->isp_state = ISP_RUNSTATE; } if (isp->isp_state != ISP_RUNSTATE) { + res = EIO; #ifndef ISP_TARGET_MODE isp_prt(isp, ISP_LOGWARN, "%s: not at runstate", __func__); #endif @@ -7923,18 +7855,16 @@ isp_reinit(ispsoftc_t *isp, int do_load_defaults) ISP_WRITE(isp, BIU2100_CSR, BIU2100_RISC_REGS); } } - } + } cleanup: - isp->isp_nactive = 0; - isp_clear_commands(isp); if (IS_FC(isp)) { - for (i = 0; i < isp->isp_nchan; i++) { + for (i = 0; i < isp->isp_nchan; i++) ISP_MARK_PORTDB(isp, i, -1); - } } + return (res); } /* diff --git a/sys/dev/isp/isp_freebsd.c b/sys/dev/isp/isp_freebsd.c index db7d788da7ec..f264b30adaf7 100644 --- a/sys/dev/isp/isp_freebsd.c +++ b/sys/dev/isp/isp_freebsd.c @@ -52,11 +52,10 @@ MODULE_DEPEND(isp, cam, 1, 1, 1); int isp_announced = 0; int isp_fabric_hysteresis = 5; int isp_loop_down_limit = 60; /* default loop down limit */ -int isp_change_is_bad = 0; /* "changed" devices are bad */ int isp_quickboot_time = 7; /* don't wait more than N secs for loop up */ int isp_gone_device_time = 30; /* grace time before reporting device lost */ int isp_autoconfig = 1; /* automatically attach/detach devices */ -static const char prom3[] = "Chan %d PortID 0x%06x Departed from Target %u because of %s"; +static const char prom3[] = "Chan %d [%u] PortID 0x%06x Departed because of %s"; static void isp_freeze_loopdown(ispsoftc_t *, int, char *); static d_ioctl_t ispioctl; @@ -102,18 +101,15 @@ isp_role_sysctl(SYSCTL_HANDLER_ARGS) ISP_LOCK(isp); old = FCPARAM(isp, chan)->role; + /* We don't allow target mode switch from here. */ + value = (old & ISP_ROLE_TARGET) | (value & ISP_ROLE_INITIATOR); + /* If nothing has changed -- we are done. */ if (value == old) { ISP_UNLOCK(isp); return (0); } - /* We don't allow target mode switch from here. */ - if ((value ^ old) & ISP_ROLE_TARGET) { - ISP_UNLOCK(isp); - return (EPERM); - } - /* Actually change the role. */ error = isp_control(isp, ISPCTL_CHANGE_ROLE, chan, value); ISP_UNLOCK(isp); @@ -474,9 +470,6 @@ ispioctl(struct cdev *dev, u_long c, caddr_t addr, int flags, struct thread *td) case ISP_RESETHBA: ISP_LOCK(isp); -#ifdef ISP_TARGET_MODE - isp_del_all_wwn_entries(isp, ISP_NOCHAN); -#endif isp_reinit(isp, 0); ISP_UNLOCK(isp); retval = 0; @@ -528,7 +521,7 @@ ispioctl(struct cdev *dev, u_long c, caddr_t addr, int flags, struct thread *td) break; } lp = &FCPARAM(isp, ifc->chan)->portdb[ifc->loopid]; - if (lp->state == FC_PORTDB_STATE_VALID || lp->target_mode) { + if (lp->state != FC_PORTDB_STATE_NIL) { ifc->role = (lp->prli_word3 & SVC3_ROLE_MASK) >> SVC3_ROLE_SHIFT; ifc->loopid = lp->handle; ifc->portid = lp->portid; @@ -1512,13 +1505,7 @@ isp_disable_lun(ispsoftc_t *isp, union ccb *ccb) done: if (status == CAM_REQ_CMP) { tptr->enabled = 0; - /* - * If we have no more luns enabled for this bus, - * delete all tracked wwns for it (if we are FC), - * and disable target mode. - */ if (is_any_lun_enabled(isp, bus) == 0) { - isp_del_all_wwn_entries(isp, bus); if (isp_disable_target_mode(isp, bus)) { status = CAM_REQ_CMP_ERR; } @@ -1911,10 +1898,10 @@ isp_target_start_ctio(ispsoftc_t *isp, union ccb *ccb, enum Start_Ctio_How how) cto->ct_header.rqs_entry_count = 1; cto->ct_header.rqs_seqno |= ATPD_SEQ_NOTIFY_CAM; ATPD_SET_SEQNO(cto, atp); - if (ISP_CAP_2KLOGIN(isp) == 0) { - ((ct2e_entry_t *)cto)->ct_iid = cso->init_id; + if (ISP_CAP_2KLOGIN(isp)) { + ((ct2e_entry_t *)cto)->ct_iid = atp->nphdl; } else { - cto->ct_iid = cso->init_id; + cto->ct_iid = atp->nphdl; if (ISP_CAP_SCCFW(isp) == 0) { cto->ct_lun = ccb->ccb_h.target_lun; } @@ -2454,26 +2441,24 @@ isp_handle_platform_atio2(ispsoftc_t *isp, at2_entry_t *aep) * We don't get 'suggested' sense data as we do with SCSI cards. */ atiop->sense_len = 0; - if (ISP_CAP_2KLOGIN(isp)) { - /* - * NB: We could not possibly have 2K logins if we - * NB: also did not have SCC FW. - */ - atiop->init_id = ((at2e_entry_t *)aep)->at_iid; - } else { - atiop->init_id = aep->at_iid; - } /* * If we're not in the port database, add ourselves. */ - if (!IS_2100(isp) && isp_find_pdb_by_loopid(isp, 0, atiop->init_id, &lp) == 0) { - uint64_t iid = - (((uint64_t) aep->at_wwpn[0]) << 48) | - (((uint64_t) aep->at_wwpn[1]) << 32) | - (((uint64_t) aep->at_wwpn[2]) << 16) | - (((uint64_t) aep->at_wwpn[3]) << 0); - isp_add_wwn_entry(isp, 0, iid, atiop->init_id, PORT_ANY, 0); + if (IS_2100(isp)) + atiop->init_id = nphdl; + else { + if ((isp_find_pdb_by_handle(isp, 0, nphdl, &lp) == 0 || + lp->state == FC_PORTDB_STATE_ZOMBIE)) { + uint64_t iid = + (((uint64_t) aep->at_wwpn[0]) << 48) | + (((uint64_t) aep->at_wwpn[1]) << 32) | + (((uint64_t) aep->at_wwpn[2]) << 16) | + (((uint64_t) aep->at_wwpn[3]) << 0); + isp_add_wwn_entry(isp, 0, iid, nphdl, PORT_ANY, 0); + isp_find_pdb_by_handle(isp, 0, nphdl, &lp); + } + atiop->init_id = FC_PORTDB_TGT(isp, 0, lp); } atiop->cdb_len = ATIO2_CDBLEN; ISP_MEMCPY(atiop->cdb_io.cdb_bytes, aep->at_cdb, ATIO2_CDBLEN); @@ -2502,7 +2487,7 @@ isp_handle_platform_atio2(ispsoftc_t *isp, at2_entry_t *aep) atp->orig_datalen = aep->at_datalen; atp->bytes_xfered = 0; atp->lun = lun; - atp->nphdl = atiop->init_id; + atp->nphdl = nphdl; atp->sid = PORT_ANY; atp->oxid = aep->at_oxid; atp->cdb0 = aep->at_cdb[0]; @@ -2531,7 +2516,6 @@ isp_handle_platform_atio7(ispsoftc_t *isp, at7_entry_t *aep) int cdbxlen; uint16_t lun, chan, nphdl = NIL_HANDLE; uint32_t did, sid; - uint64_t wwn = INI_NONE; fcportdb_t *lp; tstate_t *tptr; struct ccb_accept_tio *atiop; @@ -2549,7 +2533,7 @@ isp_handle_platform_atio7(ispsoftc_t *isp, at7_entry_t *aep) * If we can't, we're somewhat in trouble because we can't actually respond w/o that information. * We also, as a matter of course, need to know the WWN of the initiator too. */ - if (ISP_CAP_MULTI_ID(isp)) { + if (ISP_CAP_MULTI_ID(isp) && isp->isp_nchan > 1) { /* * Find the right channel based upon D_ID */ @@ -2594,11 +2578,11 @@ isp_handle_platform_atio7(ispsoftc_t *isp, at7_entry_t *aep) */ isp_prt(isp, ISP_LOGTINFO, "%s: [RX_ID 0x%x] D_ID 0x%06x found on Chan %d for S_ID 0x%06x wasn't in PDB already", __func__, aep->at_rxid, did, chan, sid); + isp_dump_portdb(isp, chan); isp_endcmd(isp, aep, NIL_HANDLE, chan, ECMD_TERMINATE, 0); return; } nphdl = lp->handle; - wwn = lp->port_wwn; /* * Get the tstate pointer @@ -2686,7 +2670,7 @@ isp_handle_platform_atio7(ispsoftc_t *isp, at7_entry_t *aep) SLIST_REMOVE_HEAD(&tptr->atios, sim_links.sle); tptr->atio_count--; ISP_PATH_PRT(isp, ISP_LOGTDEBUG2, atiop->ccb_h.path, "Take FREE ATIO count now %d\n", tptr->atio_count); - atiop->init_id = nphdl; + atiop->init_id = FC_PORTDB_TGT(isp, chan, lp); atiop->ccb_h.target_id = FCPARAM(isp, chan)->isp_loopid; atiop->ccb_h.target_lun = lun; atiop->sense_len = 0; @@ -3100,7 +3084,7 @@ isp_handle_platform_notify_fc(ispsoftc_t *isp, in_fcentry_t *inp) { tstate_t *tptr; uint16_t lun; - uint32_t loopid; + uint32_t loopid, sid; uint64_t wwn; atio_private_data_t *atp; fcportdb_t *lp; @@ -3116,10 +3100,12 @@ isp_handle_platform_notify_fc(ispsoftc_t *isp, in_fcentry_t *inp) } else { loopid = inp->in_iid; } - if (isp_find_pdb_by_loopid(isp, 0, loopid, &lp)) { + if (isp_find_pdb_by_handle(isp, 0, loopid, &lp)) { wwn = lp->port_wwn; + sid = lp->portid; } else { wwn = INI_ANY; + sid = PORT_ANY; } tptr = get_lun_statep(isp, 0, lun); if (tptr == NULL) { @@ -3151,7 +3137,7 @@ isp_handle_platform_notify_fc(ispsoftc_t *isp, in_fcentry_t *inp) nt->nt_tgt = FCPARAM(isp, 0)->isp_wwpn; nt->nt_wwn = wwn; nt->nt_nphdl = loopid; - nt->nt_sid = PORT_ANY; + nt->nt_sid = sid; nt->nt_did = PORT_ANY; nt->nt_lun = lun; nt->nt_need_ack = 1; @@ -3270,7 +3256,7 @@ isp_handle_platform_notify_24xx(ispsoftc_t *isp, in_fcentry_24xx_t *inot) case IN24XX_PORT_LOGOUT: ptr = "PORT LOGOUT"; - if (isp_find_pdb_by_loopid(isp, ISP_GET_VPIDX(isp, inot->in_vpidx), nphdl, &lp)) { + if (isp_find_pdb_by_handle(isp, ISP_GET_VPIDX(isp, inot->in_vpidx), nphdl, &lp)) { isp_del_wwn_entry(isp, ISP_GET_VPIDX(isp, inot->in_vpidx), lp->port_wwn, nphdl, lp->portid); } /* FALLTHROUGH */ @@ -3463,10 +3449,11 @@ isp_handle_platform_target_tmf(ispsoftc_t *isp, isp_notify_t *notify) goto bad; } - if (isp_find_pdb_by_sid(isp, notify->nt_channel, notify->nt_sid, &lp) == 0) { + if (isp_find_pdb_by_sid(isp, notify->nt_channel, notify->nt_sid, &lp) == 0 && + isp_find_pdb_by_handle(isp, notify->nt_channel, notify->nt_nphdl, &lp) == 0) { inot->initiator_id = CAM_TARGET_WILDCARD; } else { - inot->initiator_id = lp->handle; + inot->initiator_id = FC_PORTDB_TGT(isp, notify->nt_channel, lp); } inot->seq_id = notify->nt_tagval; inot->tag_id = notify->nt_tagval >> 32; @@ -4606,13 +4593,6 @@ isp_make_here(ispsoftc_t *isp, fcportdb_t *fcp, int chan, int tgt) xpt_free_ccb(ccb); return; } - - /* - * Since we're about to issue a rescan, mark this device as not - * reported gone. - */ - fcp->reported_gone = 0; - xpt_rescan(ccb); } @@ -4626,11 +4606,6 @@ isp_make_gone(ispsoftc_t *isp, fcportdb_t *fcp, int chan, int tgt) return; } if (xpt_create_path(&tp, NULL, cam_sim_path(fc->sim), tgt, CAM_LUN_WILDCARD) == CAM_REQ_CMP) { - /* - * We're about to send out the lost device async - * notification, so indicate that we have reported it gone. - */ - fcp->reported_gone = 1; xpt_async(AC_LOST_DEVICE, tp, NULL); xpt_free_path(tp); } @@ -4660,6 +4635,8 @@ isp_gdt_task(void *arg, int pending) ispsoftc_t *isp = fc->isp; int chan = fc - isp->isp_osinfo.pc.fc; fcportdb_t *lp; + struct ac_contract ac; + struct ac_device_changed *adc; int dbidx, more_to_do = 0; ISP_LOCK(isp); @@ -4670,19 +4647,27 @@ isp_gdt_task(void *arg, int pending) if (lp->state != FC_PORTDB_STATE_ZOMBIE) { continue; } - if (lp->dev_map_idx == 0 || lp->target_mode) { - continue; - } if (lp->gone_timer != 0) { - isp_prt(isp, ISP_LOG_SANCFG, "%s: Chan %d more to do for target %u (timer=%u)", __func__, chan, lp->dev_map_idx - 1, lp->gone_timer); lp->gone_timer -= 1; more_to_do++; continue; } - lp->dev_map_idx = 0; + isp_prt(isp, ISP_LOGCONFIG, prom3, chan, dbidx, lp->portid, "Gone Device Timeout"); + if (lp->is_target) { + lp->is_target = 0; + isp_make_gone(isp, lp, chan, dbidx); + } + if (lp->is_initiator) { + lp->is_initiator = 0; + ac.contract_number = AC_CONTRACT_DEV_CHG; + adc = (struct ac_device_changed *) ac.contract_data; + adc->wwpn = lp->port_wwn; + adc->port = lp->portid; + adc->target = dbidx; + adc->arrived = 0; + xpt_async(AC_CONTRACT, fc->path, &ac); + } lp->state = FC_PORTDB_STATE_NIL; - isp_prt(isp, ISP_LOGCONFIG, prom3, chan, lp->portid, dbidx, "Gone Device Timeout"); - isp_make_gone(isp, lp, chan, dbidx); } if (fc->ready) { if (more_to_do) { @@ -4718,6 +4703,8 @@ isp_ldt_task(void *arg, int pending) ispsoftc_t *isp = fc->isp; int chan = fc - isp->isp_osinfo.pc.fc; fcportdb_t *lp; + struct ac_contract ac; + struct ac_device_changed *adc; int dbidx, i; ISP_LOCK(isp); @@ -4730,18 +4717,12 @@ isp_ldt_task(void *arg, int pending) for (dbidx = 0; dbidx < MAX_FC_TARG; dbidx++) { lp = &FCPARAM(isp, chan)->portdb[dbidx]; - if (lp->state != FC_PORTDB_STATE_PROBATIONAL) { + if (lp->state == FC_PORTDB_STATE_NIL) continue; - } - if (lp->dev_map_idx == 0 || lp->target_mode) { - continue; - } /* * XXX: CLEAN UP AND COMPLETE ANY PENDING COMMANDS FIRST! */ - - for (i = 0; i < isp->isp_maxcmds; i++) { struct ccb_scsiio *xs; @@ -4758,19 +4739,24 @@ isp_ldt_task(void *arg, int pending) isp->isp_xflist[i].handle, chan, XS_TGT(xs), XS_LUN(xs)); } - /* - * Mark that we've announced that this device is gone.... - */ - lp->announced = 1; - lp->dev_map_idx = 0; - lp->state = FC_PORTDB_STATE_NIL; - isp_prt(isp, ISP_LOGCONFIG, prom3, chan, lp->portid, dbidx, "Loop Down Timeout"); - isp_make_gone(isp, lp, chan, dbidx); + isp_prt(isp, ISP_LOGCONFIG, prom3, chan, dbidx, lp->portid, "Loop Down Timeout"); + if (lp->is_target) { + lp->is_target = 0; + isp_make_gone(isp, lp, chan, dbidx); + } + if (lp->is_initiator) { + lp->is_initiator = 0; + ac.contract_number = AC_CONTRACT_DEV_CHG; + adc = (struct ac_device_changed *) ac.contract_data; + adc->wwpn = lp->port_wwn; + adc->port = lp->portid; + adc->target = dbidx; + adc->arrived = 0; + xpt_async(AC_CONTRACT, fc->path, &ac); + } } - if (FCPARAM(isp, chan)->role & ISP_ROLE_INITIATOR) { - isp_unfreeze_loopdown(isp, chan); - } + isp_unfreeze_loopdown(isp, chan); /* * The loop down timer has expired. Wake up the kthread * to notice that fact (or make it false). @@ -5585,7 +5571,7 @@ isp_done(XS_T *sccb) fcparam *fcp; fcp = FCPARAM(isp, XS_CHANNEL(sccb)); - fcp->portdb[XS_TGT(sccb)].reported_gone = 1; + fcp->portdb[XS_TGT(sccb)].is_target = 0; } if ((sccb->ccb_h.status & CAM_DEV_QFRZN) == 0) { sccb->ccb_h.status |= CAM_DEV_QFRZN; @@ -5608,15 +5594,16 @@ isp_done(XS_T *sccb) void isp_async(ispsoftc_t *isp, ispasync_t cmd, ...) { - int bus, now; - static const char prom0[] = "Chan %d PortID 0x%06x handle 0x%x %s %s WWPN 0x%08x%08x"; - static const char prom2[] = "Chan %d PortID 0x%06x handle 0x%x %s %s tgt %u WWPN 0x%08x%08x"; + int bus; + static const char prom[] = "Chan %d [%d] WWPN 0x%16jx PortID 0x%06x handle 0x%x %s %s"; char buf[64]; char *msg = NULL; target_id_t tgt; fcportdb_t *lp; struct isp_fc *fc; struct cam_path *tmppath; + struct ac_contract ac; + struct ac_device_changed *adc; va_list ap; switch (cmd) { @@ -5718,10 +5705,10 @@ isp_async(ispsoftc_t *isp, ispasync_t cmd, ...) if (fc->path) { isp_freeze_loopdown(isp, bus, msg); } - if (!callout_active(&fc->ldt)) { - callout_reset(&fc->ldt, fc->loop_down_limit * hz, isp_ldt, fc); - isp_prt(isp, ISP_LOG_SANCFG|ISP_LOGDEBUG0, "Starting Loop Down Timer @ %lu", (unsigned long) time_uptime); - } + } + if (!callout_active(&fc->ldt)) { + callout_reset(&fc->ldt, fc->loop_down_limit * hz, isp_ldt, fc); + isp_prt(isp, ISP_LOG_SANCFG|ISP_LOGDEBUG0, "Starting Loop Down Timer @ %lu", (unsigned long) time_uptime); } } isp_fcp_reset_crn(fc, /*tgt*/0, /*tgt_set*/ 0); @@ -5751,19 +5738,25 @@ isp_async(ispsoftc_t *isp, ispasync_t cmd, ...) lp = va_arg(ap, fcportdb_t *); va_end(ap); fc = ISP_FC_PC(isp, bus); - lp->announced = 0; - lp->gone_timer = 0; - if ((FCPARAM(isp, bus)->role & ISP_ROLE_INITIATOR) && (lp->prli_word3 & PRLI_WD3_TARGET_FUNCTION)) { - lp->dev_map_idx = (lp - FCPARAM(isp, bus)->portdb) + 1; - } + tgt = FC_PORTDB_TGT(isp, bus, lp); isp_gen_role_str(buf, sizeof (buf), lp->prli_word3); - if (lp->dev_map_idx) { - tgt = lp->dev_map_idx - 1; - isp_prt(isp, ISP_LOGCONFIG, prom2, bus, lp->portid, lp->handle, buf, "arrived at", tgt, (uint32_t) (lp->port_wwn >> 32), (uint32_t) lp->port_wwn); + isp_prt(isp, ISP_LOGCONFIG, prom, bus, tgt, lp->port_wwn, lp->portid, lp->handle, buf, "arrived"); + if ((FCPARAM(isp, bus)->role & ISP_ROLE_INITIATOR) && + (lp->prli_word3 & PRLI_WD3_TARGET_FUNCTION)) { + lp->is_target = 1; isp_fcp_reset_crn(fc, tgt, /*tgt_set*/ 1); isp_make_here(isp, lp, bus, tgt); - } else { - isp_prt(isp, ISP_LOGCONFIG, prom0, bus, lp->portid, lp->handle, buf, "arrived", (uint32_t) (lp->port_wwn >> 32), (uint32_t) lp->port_wwn); + } + if ((FCPARAM(isp, bus)->role & ISP_ROLE_TARGET) && + (lp->prli_word3 & PRLI_WD3_INITIATOR_FUNCTION)) { + lp->is_initiator = 1; + ac.contract_number = AC_CONTRACT_DEV_CHG; + adc = (struct ac_device_changed *) ac.contract_data; + adc->wwpn = lp->port_wwn; + adc->port = lp->portid; + adc->target = tgt; + adc->arrived = 1; + xpt_async(AC_CONTRACT, fc->path, &ac); } break; case ISPASYNC_DEV_CHANGED: @@ -5772,97 +5765,68 @@ isp_async(ispsoftc_t *isp, ispasync_t cmd, ...) lp = va_arg(ap, fcportdb_t *); va_end(ap); fc = ISP_FC_PC(isp, bus); - lp->announced = 0; - lp->gone_timer = 0; - if (isp_change_is_bad) { - lp->state = FC_PORTDB_STATE_NIL; - if (lp->dev_map_idx) { - tgt = lp->dev_map_idx - 1; - lp->dev_map_idx = 0; - isp_prt(isp, ISP_LOGCONFIG, prom3, bus, lp->portid, tgt, "change is bad"); - isp_make_gone(isp, lp, bus, tgt); - } else { - isp_gen_role_str(buf, sizeof (buf), lp->prli_word3); - isp_prt(isp, ISP_LOGCONFIG, prom0, bus, lp->portid, lp->handle, buf, "changed and departed", - (uint32_t) (lp->port_wwn >> 32), (uint32_t) lp->port_wwn); - } - } else { - lp->portid = lp->new_portid; - lp->prli_word3 = lp->new_prli_word3; - isp_gen_role_str(buf, sizeof (buf), lp->prli_word3); - if (lp->dev_map_idx) { - tgt = lp->dev_map_idx - 1; - isp_prt(isp, ISP_LOGCONFIG, prom2, bus, lp->portid, lp->handle, buf, "changed at", tgt, - (uint32_t) (lp->port_wwn >> 32), (uint32_t) lp->port_wwn); + tgt = FC_PORTDB_TGT(isp, bus, lp); + isp_gen_role_str(buf, sizeof (buf), lp->new_prli_word3); + isp_prt(isp, ISP_LOGCONFIG, prom, bus, tgt, lp->port_wwn, lp->new_portid, lp->handle, buf, "changed"); +changed: + if (lp->is_target != + ((FCPARAM(isp, bus)->role & ISP_ROLE_INITIATOR) && + (lp->new_prli_word3 & PRLI_WD3_TARGET_FUNCTION))) { + lp->is_target = !lp->is_target; + if (lp->is_target) { isp_fcp_reset_crn(fc, tgt, /*tgt_set*/ 1); + isp_make_here(isp, lp, bus, tgt); } else { - isp_prt(isp, ISP_LOGCONFIG, prom0, bus, lp->portid, lp->handle, buf, "changed", (uint32_t) (lp->port_wwn >> 32), (uint32_t) lp->port_wwn); + isp_make_gone(isp, lp, bus, tgt); + isp_fcp_reset_crn(fc, tgt, /*tgt_set*/ 1); } } + if (lp->is_initiator != + ((FCPARAM(isp, bus)->role & ISP_ROLE_TARGET) && + (lp->new_prli_word3 & PRLI_WD3_INITIATOR_FUNCTION))) { + lp->is_initiator = !lp->is_initiator; + ac.contract_number = AC_CONTRACT_DEV_CHG; + adc = (struct ac_device_changed *) ac.contract_data; + adc->wwpn = lp->port_wwn; + adc->port = lp->portid; + adc->target = tgt; + adc->arrived = lp->is_initiator; + xpt_async(AC_CONTRACT, fc->path, &ac); + } break; case ISPASYNC_DEV_STAYED: va_start(ap, cmd); bus = va_arg(ap, int); lp = va_arg(ap, fcportdb_t *); va_end(ap); + fc = ISP_FC_PC(isp, bus); + tgt = FC_PORTDB_TGT(isp, bus, lp); isp_gen_role_str(buf, sizeof (buf), lp->prli_word3); - if (lp->dev_map_idx) { - fc = ISP_FC_PC(isp, bus); - tgt = lp->dev_map_idx - 1; - isp_prt(isp, ISP_LOGCONFIG, prom2, bus, lp->portid, lp->handle, buf, "stayed at", tgt, - (uint32_t) (lp->port_wwn >> 32), (uint32_t) lp->port_wwn); - /* - * Only issue a rescan if we've actually reported - * that this device is gone. - */ - if (lp->reported_gone != 0) { - isp_prt(isp, ISP_LOGCONFIG, prom2, bus, lp->portid, lp->handle, buf, "rescanned at", tgt, - (uint32_t) (lp->port_wwn >> 32), (uint32_t) lp->port_wwn); - isp_make_here(isp, lp, bus, tgt); - } - } else { - isp_prt(isp, ISP_LOGCONFIG, prom0, bus, lp->portid, lp->handle, buf, "stayed", - (uint32_t) (lp->port_wwn >> 32), (uint32_t) lp->port_wwn); - } - break; + isp_prt(isp, ISP_LOGCONFIG, prom, bus, tgt, lp->port_wwn, lp->portid, lp->handle, buf, "stayed"); + goto changed; case ISPASYNC_DEV_GONE: va_start(ap, cmd); bus = va_arg(ap, int); lp = va_arg(ap, fcportdb_t *); - now = va_arg(ap, int); va_end(ap); fc = ISP_FC_PC(isp, bus); + tgt = FC_PORTDB_TGT(isp, bus, lp); /* - * If this has a virtual target and we haven't marked it - * that we're going to have isp_gdt tell the OS it's gone, - * set the isp_gdt timer running on it. - * - * If it isn't marked that isp_gdt is going to get rid of it, - * announce that it's gone. - * + * If this has a virtual target or initiator set the isp_gdt + * timer running on it to delay its departure. */ isp_gen_role_str(buf, sizeof (buf), lp->prli_word3); - if (lp->dev_map_idx && lp->announced == 0 && now) { - lp->announced = 1; - tgt = lp->dev_map_idx - 1; - lp->dev_map_idx = 0; - isp_make_gone(isp, lp, bus, tgt); - isp_prt(isp, ISP_LOGCONFIG, prom2, bus, lp->portid, lp->handle, buf, "gone at", tgt, (uint32_t) (lp->port_wwn >> 32), (uint32_t) lp->port_wwn); - isp_fcp_reset_crn(fc, tgt, /*tgt_set*/ 1); - } else if (lp->dev_map_idx && lp->announced == 0) { - lp->announced = 1; + if (lp->is_target || lp->is_initiator) { lp->state = FC_PORTDB_STATE_ZOMBIE; - lp->gone_timer = ISP_FC_PC(isp, bus)->gone_device_time; + lp->gone_timer = fc->gone_device_time; + isp_prt(isp, ISP_LOGCONFIG, prom, bus, tgt, lp->port_wwn, lp->portid, lp->handle, buf, "gone zombie"); if (fc->ready && !callout_active(&fc->gdt)) { isp_prt(isp, ISP_LOG_SANCFG|ISP_LOGDEBUG0, "Chan %d Starting Gone Device Timer with %u seconds time now %lu", bus, lp->gone_timer, (unsigned long)time_uptime); callout_reset(&fc->gdt, hz, isp_gdt, fc); } - tgt = lp->dev_map_idx - 1; - isp_prt(isp, ISP_LOGCONFIG, prom2, bus, lp->portid, lp->handle, buf, "gone zombie at", tgt, (uint32_t) (lp->port_wwn >> 32), (uint32_t) lp->port_wwn); - isp_fcp_reset_crn(fc, tgt, /*tgt_set*/ 1); - } else if (lp->announced == 0) { - isp_prt(isp, ISP_LOGCONFIG, prom0, bus, lp->portid, lp->handle, buf, "departed", (uint32_t) (lp->port_wwn >> 32), (uint32_t) lp->port_wwn); + break; } + isp_prt(isp, ISP_LOGCONFIG, prom, bus, tgt, lp->port_wwn, lp->portid, lp->handle, buf, "gone"); break; case ISPASYNC_CHANGE_NOTIFY: { @@ -5928,13 +5892,11 @@ isp_async(ispsoftc_t *isp, ispasync_t cmd, ...) case NT_LIP_RESET: case NT_LINK_UP: case NT_LINK_DOWN: + case NT_HBA_RESET: /* * No action need be taken here. */ break; - case NT_HBA_RESET: - isp_del_all_wwn_entries(isp, ISP_NOCHAN); - break; case NT_GLOBAL_LOGOUT: case NT_LOGOUT: /* @@ -5942,34 +5904,6 @@ isp_async(ispsoftc_t *isp, ispasync_t cmd, ...) */ isp_handle_platform_target_notify_ack(isp, notify); break; - case NT_ARRIVED: - { - struct ac_contract ac; - struct ac_device_changed *fc; - - ac.contract_number = AC_CONTRACT_DEV_CHG; - fc = (struct ac_device_changed *) ac.contract_data; - fc->wwpn = notify->nt_wwn; - fc->port = notify->nt_sid; - fc->target = notify->nt_nphdl; - fc->arrived = 1; - xpt_async(AC_CONTRACT, ISP_FC_PC(isp, notify->nt_channel)->path, &ac); - break; - } - case NT_DEPARTED: - { - struct ac_contract ac; - struct ac_device_changed *fc; - - ac.contract_number = AC_CONTRACT_DEV_CHG; - fc = (struct ac_device_changed *) ac.contract_data; - fc->wwpn = notify->nt_wwn; - fc->port = notify->nt_sid; - fc->target = notify->nt_nphdl; - fc->arrived = 0; - xpt_async(AC_CONTRACT, ISP_FC_PC(isp, notify->nt_channel)->path, &ac); - break; - } default: isp_prt(isp, ISP_LOGALL, "target notify code 0x%x", notify->nt_ncode); isp_handle_platform_target_notify_ack(isp, notify); @@ -6060,7 +5994,7 @@ isp_async(ispsoftc_t *isp, ispasync_t cmd, ...) nt->nt_tgt = TGT_ANY; } else { nt->nt_tgt = FCPARAM(isp, chan)->isp_wwpn; - if (isp_find_pdb_by_loopid(isp, chan, abts->abts_nphdl, &lp)) { + if (isp_find_pdb_by_handle(isp, chan, abts->abts_nphdl, &lp)) { nt->nt_wwn = lp->port_wwn; } else { nt->nt_wwn = INI_ANY; diff --git a/sys/dev/isp/isp_library.c b/sys/dev/isp/isp_library.c index 2f7dc4e0c25c..f7ee7bb99aec 100644 --- a/sys/dev/isp/isp_library.c +++ b/sys/dev/isp/isp_library.c @@ -411,10 +411,6 @@ isp_fc_runstate(ispsoftc_t *isp, int chan, int tval) } } - if ((fcp->role & ISP_ROLE_INITIATOR) == 0) { - return (0); - } - if (isp_control(isp, ISPCTL_SCAN_LOOP, chan) != 0) { isp_prt(isp, ISP_LOG_SANCFG, "isp_fc_runstate: scan loop fails on channel %d", chan); return (LOOP_PDB_RCVD); @@ -444,7 +440,7 @@ isp_dump_portdb(ispsoftc_t *isp, int chan) int i; for (i = 0; i < MAX_FC_TARG; i++) { - char mb[4], buf1[64], buf2[64]; + char buf1[64], buf2[64]; const char *dbs[8] = { "NIL ", "PROB", @@ -457,18 +453,13 @@ isp_dump_portdb(ispsoftc_t *isp, int chan) }; fcportdb_t *lp = &fcp->portdb[i]; - if (lp->state == FC_PORTDB_STATE_NIL && lp->target_mode == 0) { + if (lp->state == FC_PORTDB_STATE_NIL) { continue; } - if (lp->dev_map_idx) { - ISP_SNPRINTF(mb, sizeof (mb), "%3d", ((int) lp->dev_map_idx) - 1); - } else { - ISP_SNPRINTF(mb, sizeof (mb), "---"); - } isp_gen_role_str(buf1, sizeof (buf1), lp->prli_word3); isp_gen_role_str(buf2, sizeof (buf2), lp->new_prli_word3); - isp_prt(isp, ISP_LOGALL, "Chan %d [%d]: hdl 0x%x %s al%d tgt %s %s 0x%06x =>%s 0x%06x; WWNN 0x%08x%08x WWPN 0x%08x%08x", - chan, i, lp->handle, dbs[lp->state], lp->autologin, mb, buf1, lp->portid, buf2, lp->new_portid, + isp_prt(isp, ISP_LOGALL, "Chan %d [%d]: hdl 0x%x %s al%d %s 0x%06x =>%s 0x%06x; WWNN 0x%08x%08x WWPN 0x%08x%08x", + chan, i, lp->handle, dbs[lp->state], lp->autologin, buf1, lp->portid, buf2, lp->new_portid, (uint32_t) (lp->node_wwn >> 32), (uint32_t) (lp->node_wwn), (uint32_t) (lp->port_wwn >> 32), (uint32_t) (lp->port_wwn)); } } @@ -603,20 +594,8 @@ isp_fc_change_role(ispsoftc_t *isp, int chan, int new_role) return (ENXIO); } if (chan == 0) { - isp_clear_commands(isp); - isp_reset(isp, 0); - if (isp->isp_state != ISP_RESETSTATE) { - isp_prt(isp, ISP_LOGERR, "%s: cannot reset card", __func__); - return (EIO); - } fcp->role = new_role; - isp_init(isp); - if (isp->isp_state != ISP_INITSTATE) { - isp_prt(isp, ISP_LOGERR, "%s: cannot init card", __func__); - return (EIO); - } - isp->isp_state = ISP_RUNSTATE; - return (0); + return (isp_reinit(isp, 0)); } else if (ISP_CAP_MULTI_ID(isp)) { mbreg_t mbs; vp_modify_t *vp; @@ -2347,8 +2326,10 @@ isp_destroy_tgt_handle(ispsoftc_t *isp, uint32_t handle) } } +#endif + /* - * Find target mode entries + * Find port database entries */ int isp_find_pdb_by_wwn(ispsoftc_t *isp, int chan, uint64_t wwn, fcportdb_t **lptr) @@ -2359,10 +2340,10 @@ isp_find_pdb_by_wwn(ispsoftc_t *isp, int chan, uint64_t wwn, fcportdb_t **lptr) if (chan >= isp->isp_nchan) return (0); fcp = FCPARAM(isp, chan); - for (i = MAX_FC_TARG - 1; i >= 0; i--) { + for (i = 0; i < MAX_FC_TARG; i++) { fcportdb_t *lp = &fcp->portdb[i]; - if (lp->target_mode == 0) + if (lp->state == FC_PORTDB_STATE_NIL) continue; if (lp->port_wwn == wwn) { *lptr = lp; @@ -2372,8 +2353,10 @@ isp_find_pdb_by_wwn(ispsoftc_t *isp, int chan, uint64_t wwn, fcportdb_t **lptr) return (0); } +#ifdef ISP_TARGET_MODE + int -isp_find_pdb_by_loopid(ispsoftc_t *isp, int chan, uint32_t loopid, fcportdb_t **lptr) +isp_find_pdb_by_handle(ispsoftc_t *isp, int chan, uint32_t handle, fcportdb_t **lptr) { fcparam *fcp; int i; @@ -2381,9 +2364,15 @@ isp_find_pdb_by_loopid(ispsoftc_t *isp, int chan, uint32_t loopid, fcportdb_t ** if (chan >= isp->isp_nchan) return (0); fcp = FCPARAM(isp, chan); - if ((i = fcp->isp_tgt_map[loopid]) > 0) { - *lptr = &fcp->portdb[i - 1]; - return (1); + for (i = 0; i < MAX_FC_TARG; i++) { + fcportdb_t *lp = &fcp->portdb[i]; + + if (lp->state == FC_PORTDB_STATE_NIL) + continue; + if (lp->handle == handle) { + *lptr = lp; + return (1); + } } return (0); } @@ -2397,10 +2386,10 @@ isp_find_pdb_by_sid(ispsoftc_t *isp, int chan, uint32_t sid, fcportdb_t **lptr) if (chan >= isp->isp_nchan) return (0); fcp = FCPARAM(isp, chan); - for (i = MAX_FC_TARG - 1; i >= 0; i--) { + for (i = 0; i < MAX_FC_TARG; i++) { fcportdb_t *lp = &fcp->portdb[i]; - if (lp->target_mode == 0) + if (lp->state == FC_PORTDB_STATE_NIL) continue; if (lp->portid == sid) { *lptr = lp; @@ -2437,14 +2426,13 @@ isp_add_wwn_entry(ispsoftc_t *isp, int chan, uint64_t ini, uint16_t nphdl, uint3 char buf[64]; fcparam *fcp; fcportdb_t *lp; - isp_notify_t nt; - int i, something, take, taken; + int i, change; fcp = FCPARAM(isp, chan); if (nphdl >= MAX_NPORT_HANDLE) { - isp_prt(isp, ISP_LOGWARN, "Chan %d IID 0x%016llx " - "N-Port handle 0x%04x Port ID 0x%06x -- bad handle", - chan, (unsigned long long) ini, nphdl, s_id); + isp_prt(isp, ISP_LOGTINFO|ISP_LOGWARN, "Chan %d WWPN 0x%016llx " + "PortID 0x%06x handle 0x%x -- bad handle", + chan, (unsigned long long) ini, s_id, nphdl); return; } @@ -2453,146 +2441,118 @@ isp_add_wwn_entry(ispsoftc_t *isp, int chan, uint64_t ini, uint16_t nphdl, uint3 * with new parameters. Some cases of update can be suspicious, * so log them verbosely and dump the whole port database. */ - if ((i = fcp->isp_tgt_map[nphdl]) > 0) { - take = taken = i - 1; - lp = &fcp->portdb[taken]; - something = 0; + if ((VALID_INI(ini) && isp_find_pdb_by_wwn(isp, chan, ini, &lp)) || + (s_id != PORT_NONE && isp_find_pdb_by_sid(isp, chan, s_id, &lp))) { + change = 0; + lp->new_portid = lp->portid; + lp->new_prli_word3 = lp->prli_word3; if (s_id != PORT_NONE && lp->portid != s_id) { if (lp->portid == PORT_NONE) { isp_prt(isp, ISP_LOGTINFO, - "Chan %d IID 0x%016llx N-port handle 0x%04x " - "gets Port ID 0x%06x", + "Chan %d WWPN 0x%016llx handle 0x%x " + "gets PortID 0x%06x", chan, (unsigned long long) lp->port_wwn, nphdl, s_id); } else { isp_prt(isp, ISP_LOGTINFO|ISP_LOGWARN, - "Chan %d IID 0x%016llx N-port handle 0x%04x " - "changes Port ID 0x%06x to 0x%06x", + "Chan %d WWPN 0x%016llx handle 0x%x " + "changes PortID 0x%06x to 0x%06x", chan, (unsigned long long) lp->port_wwn, nphdl, lp->portid, s_id); if (isp->isp_dblev & (ISP_LOGTINFO|ISP_LOGWARN)) isp_dump_portdb(isp, chan); } - lp->portid = s_id; - something++; + lp->new_portid = s_id; + change++; } if (VALID_INI(ini) && lp->port_wwn != ini) { if (!VALID_INI(lp->port_wwn)) { isp_prt(isp, ISP_LOGTINFO, - "Chan %d N-port handle 0x%04x Port ID " - "0x%06x gets WWN 0x%016llxx", - chan, nphdl, lp->portid, + "Chan %d PortID 0x%06x handle 0x%x " + "gets WWN 0x%016llxx", + chan, lp->portid, nphdl, (unsigned long long) ini); } else if (lp->port_wwn != ini) { isp_prt(isp, ISP_LOGTINFO|ISP_LOGWARN, - "Chan %d N-port handle 0x%04x Port ID " - "0x%06x changes WWN 0x%016llx to 0x%016llx", - chan, nphdl, lp->portid, + "Chan %d PortID 0x%06x handle 0x%x " + "changes WWN 0x%016llx to 0x%016llx", + chan, lp->portid, nphdl, (unsigned long long) lp->port_wwn, (unsigned long long) ini); if (isp->isp_dblev & (ISP_LOGTINFO|ISP_LOGWARN)) isp_dump_portdb(isp, chan); } lp->port_wwn = ini; - something++; + change++; } - if (lp->prli_word3 != prli_params) { - lp->prli_word3 = prli_params; - isp_gen_role_str(buf, sizeof (buf), lp->prli_word3); + if (prli_params != 0 && lp->prli_word3 != prli_params) { + isp_gen_role_str(buf, sizeof (buf), prli_params); isp_prt(isp, ISP_LOGTINFO|ISP_LOGCONFIG, - "Chan %d IID 0x%016llx N-Port Handle 0x%04x " - "Port ID 0x%06x changes PRLI Word 3 %s", + "Chan %d WWPN 0x%016llx PortID 0x%06x " + "handle 0x%x changes PRLI Word 3 %s", chan, (unsigned long long) lp->port_wwn, - lp->handle, lp->portid, buf); - something++; + lp->portid, lp->handle, buf); + lp->new_prli_word3 = prli_params; + change++; } - if (!something) { + if (lp->handle != nphdl) { + isp_prt(isp, ISP_LOGTINFO|ISP_LOGCONFIG, + "Chan %d WWPN 0x%016llx PortID 0x%06x " + "changes handle 0x%x to 0x%x", + chan, (unsigned long long) lp->port_wwn, + lp->portid, lp->handle, nphdl); + lp->handle = nphdl; + change++; + } + lp->state = FC_PORTDB_STATE_VALID; + if (change) { + isp_async(isp, ISPASYNC_DEV_CHANGED, chan, lp); + lp->portid = lp->new_portid; + lp->prli_word3 = lp->new_prli_word3; + lp->new_prli_word3 = 0; + lp->new_portid = 0; + } else { isp_prt(isp, ISP_LOGTINFO, - "Chan %d IID 0x%016llx N-Port Handle 0x%04x " - "Port ID 0x%06x reentered", + "Chan %d WWPN 0x%016llx PortID 0x%06x " + "handle 0x%x reentered", chan, (unsigned long long) lp->port_wwn, - lp->handle, lp->portid); + lp->portid, lp->handle); + isp_async(isp, ISPASYNC_DEV_STAYED, chan, lp); } - } else - take = taken = -1; - - /* - * Search for records colliding on handler, Port ID or WWN. - * Remove any found collisions, logging suspicious cases of - * still valid records. - */ - for (i = 0; i < MAX_FC_TARG; i++) { - lp = &fcp->portdb[i]; - if (lp->target_mode == 0 || i == take) - continue; - if (lp->handle != nphdl && lp->portid != s_id && - lp->port_wwn != ini) - continue; - if (lp->state == FC_PORTDB_STATE_VALID) { - isp_prt(isp, ISP_LOGTINFO|ISP_LOGWARN, - "Chan %d IID 0x%016llx N-Port Handle 0x%04x " - "Port ID 0x%06x is conflicting", - chan, (unsigned long long) lp->port_wwn, - lp->handle, lp->portid); - if (isp->isp_dblev & (ISP_LOGTINFO|ISP_LOGWARN)) - isp_dump_portdb(isp, chan); - isp_del_wwn_entry(isp, chan, - lp->port_wwn, lp->handle, lp->portid); - } - ISP_MEMZERO(lp, sizeof (fcportdb_t)); - take = i; - } - - /* If valid record already exists -- we are done. */ - if (taken >= 0) return; + } /* Search for room to insert new record. */ - if (take < 0) { - for (i = MAX_FC_TARG - 1; i >= 0; i--) { - if (fcp->portdb[i].state == FC_PORTDB_STATE_NIL) { - take = i; - break; - } - } + for (i = 0; i < MAX_FC_TARG; i++) { + if (fcp->portdb[i].state == FC_PORTDB_STATE_NIL) + break; } - if (take < 0) { + if (i >= MAX_FC_TARG) { isp_prt(isp, ISP_LOGTINFO|ISP_LOGWARN, - "Chan %d IID 0x%016llx N-Port Handle 0x%04x Port ID 0x%06x " + "Chan %d WWPN 0x%016llx PortID 0x%06x handle 0x%x " "-- no room in port database", - chan, (unsigned long long) ini, nphdl, s_id); + chan, (unsigned long long) ini, s_id, nphdl); if (isp->isp_dblev & (ISP_LOGTINFO|ISP_LOGWARN)) isp_dump_portdb(isp, chan); return; } /* Insert new record and mark it valid. */ - lp = &fcp->portdb[take]; + lp = &fcp->portdb[i]; ISP_MEMZERO(lp, sizeof (fcportdb_t)); - lp->target_mode = 1; lp->handle = nphdl; lp->portid = s_id; lp->port_wwn = ini; - lp->prli_word3 = prli_params; + lp->prli_word3 = (prli_params != 0) ? prli_params : PRLI_WD3_INITIATOR_FUNCTION; lp->state = FC_PORTDB_STATE_VALID; - fcp->isp_tgt_map[nphdl] = take + 1; isp_gen_role_str(buf, sizeof (buf), lp->prli_word3); - isp_prt(isp, ISP_LOGTINFO, "Chan %d IID 0x%016llx N-Port Handle 0x%04x" - " Port ID 0x%06x vtgt %d %s added", chan, - (unsigned long long) ini, nphdl, s_id, take, buf); + isp_prt(isp, ISP_LOGTINFO, "Chan %d WWPN 0x%016llx " + "PortID 0x%06x handle 0x%x vtgt %d %s added", chan, + (unsigned long long) ini, s_id, nphdl, i, buf); - /* Notify above levels about new initiator arrival. */ - ISP_MEMZERO(&nt, sizeof (nt)); - nt.nt_hba = isp; - nt.nt_wwn = ini; - nt.nt_tgt = FCPARAM(isp, chan)->isp_wwpn; - nt.nt_sid = s_id; - nt.nt_did = FCPARAM(isp, chan)->isp_portid; - nt.nt_nphdl = nphdl; - nt.nt_channel = chan; - nt.nt_ncode = NT_ARRIVED; - isp_async(isp, ISPASYNC_TARGET_NOTIFY, &nt); + /* Notify above levels about new port arrival. */ + isp_async(isp, ISPASYNC_DEV_ARRIVED, chan, lp); } /* @@ -2602,45 +2562,27 @@ void isp_del_wwn_entry(ispsoftc_t *isp, int chan, uint64_t ini, uint16_t nphdl, uint32_t s_id) { fcparam *fcp; - isp_notify_t nt; fcportdb_t *lp; if (nphdl >= MAX_NPORT_HANDLE) { - isp_prt(isp, ISP_LOGWARN, "Chan %d IID 0x%016llx bad N-Port handle 0x%04x Port ID 0x%06x", - chan, (unsigned long long) ini, nphdl, s_id); + isp_prt(isp, ISP_LOGWARN, "Chan %d WWPN 0x%016llx PortID 0x%06x bad handle 0x%x", + chan, (unsigned long long) ini, s_id, nphdl); return; } fcp = FCPARAM(isp, chan); - if (fcp->isp_tgt_map[nphdl] == 0) { - lp = NULL; - } else { - lp = &fcp->portdb[fcp->isp_tgt_map[nphdl] - 1]; - if (lp->target_mode == 0) { - lp = NULL; - } - } - if (lp == NULL) { - isp_prt(isp, ISP_LOGWARN, "Chan %d IID 0x%016llx N-Port Handle 0x%04x Port ID 0x%06x cannot be found to be deleted", - chan, (unsigned long long) ini, nphdl, s_id); + if (isp_find_pdb_by_handle(isp, chan, nphdl, &lp) == 0) { + isp_prt(isp, ISP_LOGWARN, "Chan %d WWPN 0x%016llx PortID 0x%06x handle 0x%x cannot be found to be deleted", + chan, (unsigned long long) ini, s_id, nphdl); isp_dump_portdb(isp, chan); return; } - isp_prt(isp, ISP_LOGTINFO, "Chan %d IID 0x%016llx N-Port Handle 0x%04x Port ID 0x%06x vtgt %d deleted", - chan, (unsigned long long) lp->port_wwn, nphdl, lp->portid, fcp->isp_tgt_map[nphdl] - 1); - fcp->isp_tgt_map[nphdl] = 0; - lp->state = FC_PORTDB_STATE_DEAD; + isp_prt(isp, ISP_LOGTINFO, "Chan %d WWPN 0x%016llx PortID 0x%06x handle 0x%x vtgt %d deleted", + chan, (unsigned long long) lp->port_wwn, lp->portid, nphdl, FC_PORTDB_TGT(isp, chan, lp)); + lp->state = FC_PORTDB_STATE_NIL; - ISP_MEMZERO(&nt, sizeof (nt)); - nt.nt_hba = isp; - nt.nt_wwn = lp->port_wwn; - nt.nt_tgt = FCPARAM(isp, chan)->isp_wwpn; - nt.nt_sid = lp->portid; - nt.nt_did = FCPARAM(isp, chan)->isp_portid; - nt.nt_nphdl = nphdl; - nt.nt_channel = chan; - nt.nt_ncode = NT_DEPARTED; - isp_async(isp, ISPASYNC_TARGET_NOTIFY, &nt); + /* Notify above levels about gone port. */ + isp_async(isp, ISPASYNC_DEV_GONE, chan, lp); } void @@ -2671,11 +2613,11 @@ isp_del_all_wwn_entries(ispsoftc_t *isp, int chan) if (fcp == NULL) { return; } - for (i = 0; i < MAX_NPORT_HANDLE; i++) { - if (fcp->isp_tgt_map[i]) { - fcportdb_t *lp = &fcp->portdb[fcp->isp_tgt_map[i] - 1]; + for (i = 0; i < MAX_FC_TARG; i++) { + fcportdb_t *lp = &fcp->portdb[i]; + + if (lp->state != FC_PORTDB_STATE_NIL) isp_del_wwn_entry(isp, chan, lp->port_wwn, lp->handle, lp->portid); - } } } @@ -2702,7 +2644,7 @@ isp_del_wwn_entries(ispsoftc_t *isp, isp_notify_t *mp) * We need to find the actual entry so we can delete it. */ if (mp->nt_nphdl != NIL_HANDLE) { - if (isp_find_pdb_by_loopid(isp, mp->nt_channel, mp->nt_nphdl, &lp)) { + if (isp_find_pdb_by_handle(isp, mp->nt_channel, mp->nt_nphdl, &lp)) { isp_del_wwn_entry(isp, mp->nt_channel, lp->port_wwn, lp->handle, lp->portid); return; } @@ -2719,8 +2661,8 @@ isp_del_wwn_entries(ispsoftc_t *isp, isp_notify_t *mp) return; } } - isp_prt(isp, ISP_LOGWARN, "Chan %d unable to find entry to delete N-port handle 0x%04x initiator WWN 0x%016llx Port ID 0x%06x", - mp->nt_channel, mp->nt_nphdl, (unsigned long long) mp->nt_wwn, mp->nt_sid); + isp_prt(isp, ISP_LOGWARN, "Chan %d unable to find entry to delete WWPN 0x%016jx PortID 0x%06x handle 0x%x", + mp->nt_channel, mp->nt_wwn, mp->nt_sid, mp->nt_nphdl); } void diff --git a/sys/dev/isp/isp_library.h b/sys/dev/isp/isp_library.h index a326bfa7dd3a..cc0cfaa1c8cb 100644 --- a/sys/dev/isp/isp_library.h +++ b/sys/dev/isp/isp_library.h @@ -165,9 +165,10 @@ int isp_allocate_xs_tgt(ispsoftc_t *, void *, uint32_t *); void *isp_find_xs_tgt(ispsoftc_t *, uint32_t); uint32_t isp_find_tgt_handle(ispsoftc_t *, void *); void isp_destroy_tgt_handle(ispsoftc_t *, uint32_t); - +#endif int isp_find_pdb_by_wwn(ispsoftc_t *, int, uint64_t, fcportdb_t **); -int isp_find_pdb_by_loopid(ispsoftc_t *, int, uint32_t, fcportdb_t **); +#ifdef ISP_TARGET_MODE +int isp_find_pdb_by_handle(ispsoftc_t *, int, uint32_t, fcportdb_t **); int isp_find_pdb_by_sid(ispsoftc_t *, int, uint32_t, fcportdb_t **); void isp_find_chan_by_did(ispsoftc_t *, uint32_t, uint16_t *); void isp_add_wwn_entry(ispsoftc_t *, int, uint64_t, uint16_t, uint32_t, uint16_t); diff --git a/sys/dev/isp/isp_target.h b/sys/dev/isp/isp_target.h index 40a17326edc6..8922a337e5d1 100644 --- a/sys/dev/isp/isp_target.h +++ b/sys/dev/isp/isp_target.h @@ -51,8 +51,6 @@ typedef enum { NT_LOGOUT, NT_GLOBAL_LOGOUT, NT_CHANGED, - NT_ARRIVED, - NT_DEPARTED, NT_HBA_RESET } isp_ncode_t; diff --git a/sys/dev/isp/ispvar.h b/sys/dev/isp/ispvar.h index 27167faa7907..2d5379ac97b4 100644 --- a/sys/dev/isp/ispvar.h +++ b/sys/dev/isp/ispvar.h @@ -376,9 +376,6 @@ typedef struct { * duples. * * + There can never be two non-NIL entries with the same handle. - * - * + There can never be two non-NIL entries which have the same dev_map_idx - * value. */ typedef struct { /* @@ -389,8 +386,6 @@ typedef struct { uint16_t handle; /* - * The dev_map_idx, if nonzero, is the system virtual target ID (+1) - * * A device is 'autologin' if the firmware automatically logs into * it (re-logins as needed). Basically, local private loop devices. * @@ -398,27 +393,24 @@ typedef struct { * * The state is the current state of this entry. * + * The is_target is the current state of target on this port. + * + * The is_initiator is the current state of initiator on this port. + * * Portid is obvious, as are node && port WWNs. The new_role and * new_portid is for when we are pending a change. - * - * The 'target_mode' tag means that this entry arrived via a - * target mode command and is immune from normal flushing rules. - * You should also never see anything with an initiator role - * with this set. */ uint16_t prli_word3; /* PRLI parameters */ uint16_t new_prli_word3; /* Incoming new PRLI parameters */ - uint16_t dev_map_idx : 12, + uint16_t : 12, autologin : 1, /* F/W does PLOGI/PLOGO */ state : 3; - uint32_t : 7, - target_mode : 1, + uint32_t : 6, + is_target : 1, + is_initiator : 1, portid : 24; uint32_t - : 5, - reported_gone : 1, - announced : 1, - dirty : 1, /* commands have been run */ + : 8, new_portid : 24; uint64_t node_wwn; uint64_t port_wwn; @@ -434,6 +426,8 @@ typedef struct { #define FC_PORTDB_STATE_ZOMBIE 6 #define FC_PORTDB_STATE_VALID 7 +#define FC_PORTDB_TGT(isp, bus, pdb) (int)(lp - FCPARAM(isp, bus)->portdb) + /* * FC card specific information * @@ -485,18 +479,6 @@ typedef struct { */ fcportdb_t portdb[MAX_FC_TARG]; -#ifdef ISP_TARGET_MODE - /* - * This maps N-Port Handle to portdb entry so we - * don't have to search for every incoming command. - * - * The mapping function is to take any non-zero entry and - * subtract one to get the portdb index. This means that - * entries which are zero are unmapped (i.e., don't exist). - */ - uint16_t isp_tgt_map[MAX_NPORT_HANDLE]; -#endif - /* * Scratch DMA mapped in area to fetch Port Database stuff, etc. */ @@ -840,7 +822,7 @@ void isp_init(ispsoftc_t *); /* * Reset the ISP and call completion for any orphaned commands. */ -void isp_reinit(ispsoftc_t *, int); +int isp_reinit(ispsoftc_t *, int); /* * Internal Interrupt Service Routine diff --git a/sys/dev/ixgbe/if_ix.c b/sys/dev/ixgbe/if_ix.c index 77556267fa15..3787db390771 100644 --- a/sys/dev/ixgbe/if_ix.c +++ b/sys/dev/ixgbe/if_ix.c @@ -246,6 +246,9 @@ DRIVER_MODULE(ix, pci, ix_driver, ix_devclass, 0, 0); MODULE_DEPEND(ix, pci, 1, 1, 1); MODULE_DEPEND(ix, ether, 1, 1, 1); +#ifdef DEV_NETMAP +MODULE_DEPEND(ix, netmap, 1, 1, 1); +#endif /* DEV_NETMAP */ /* ** TUNEABLE PARAMETERS: @@ -270,7 +273,6 @@ SYSCTL_INT(_hw_ix, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, /* How many packets rxeof tries to clean at a time */ static int ixgbe_rx_process_limit = 256; -TUNABLE_INT("hw.ixgbe.rx_process_limit", &ixgbe_rx_process_limit); SYSCTL_INT(_hw_ix, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, &ixgbe_rx_process_limit, 0, "Maximum number of received packets to process at a time," @@ -278,7 +280,6 @@ SYSCTL_INT(_hw_ix, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, /* How many packets txeof tries to clean at a time */ static int ixgbe_tx_process_limit = 256; -TUNABLE_INT("hw.ixgbe.tx_process_limit", &ixgbe_tx_process_limit); SYSCTL_INT(_hw_ix, OID_AUTO, tx_process_limit, CTLFLAG_RDTUN, &ixgbe_tx_process_limit, 0, "Maximum number of sent packets to process at a time," @@ -439,6 +440,11 @@ ixgbe_attach(device_t dev) adapter->dev = adapter->osdep.dev = dev; hw = &adapter->hw; +#ifdef DEV_NETMAP + adapter->init_locked = ixgbe_init_locked; + adapter->stop_locked = ixgbe_stop; +#endif + /* Core Lock Init*/ IXGBE_CORE_LOCK_INIT(adapter, device_get_nameunit(dev)); @@ -5270,10 +5276,10 @@ ixgbe_vf_api_negotiate(struct adapter *adapter, struct ixgbe_vf *vf, uint32_t *msg) { - switch (msg[0]) { + switch (msg[1]) { case IXGBE_API_VER_1_0: case IXGBE_API_VER_1_1: - vf->api_ver = msg[0]; + vf->api_ver = msg[1]; ixgbe_send_vf_ack(adapter, vf, msg[0]); break; default: diff --git a/sys/dev/ixgbe/if_ixv.c b/sys/dev/ixgbe/if_ixv.c index cc2d63f1c9ba..d3230d837ae0 100644 --- a/sys/dev/ixgbe/if_ixv.c +++ b/sys/dev/ixgbe/if_ixv.c @@ -124,6 +124,18 @@ static void ixv_msix_mbx(void *); static void ixv_handle_que(void *, int); static void ixv_handle_mbx(void *, int); +#ifdef DEV_NETMAP +/* + * This is defined in , which is included by + * if_ix.c. + */ +extern void ixgbe_netmap_attach(struct adapter *adapter); + +#include +#include +#include +#endif /* DEV_NETMAP */ + /********************************************************************* * FreeBSD Device Interface Entry Points *********************************************************************/ @@ -145,6 +157,9 @@ devclass_t ixv_devclass; DRIVER_MODULE(ixv, pci, ixv_driver, ixv_devclass, 0, 0); MODULE_DEPEND(ixv, pci, 1, 1, 1); MODULE_DEPEND(ixv, ether, 1, 1, 1); +#ifdef DEV_NETMAP +MODULE_DEPEND(ix, netmap, 1, 1, 1); +#endif /* DEV_NETMAP */ /* XXX depend on 'ix' ? */ /* @@ -278,6 +293,11 @@ ixv_attach(device_t dev) adapter->dev = adapter->osdep.dev = dev; hw = &adapter->hw; +#ifdef DEV_NETMAP + adapter->init_locked = ixv_init_locked; + adapter->stop_locked = ixv_stop; +#endif + /* Core Lock Init*/ IXGBE_CORE_LOCK_INIT(adapter, device_get_nameunit(dev)); @@ -381,6 +401,9 @@ ixv_attach(device_t dev) adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig, ixv_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST); +#ifdef DEV_NETMAP + ixgbe_netmap_attach(adapter); +#endif /* DEV_NETMAP */ INIT_DEBUGOUT("ixv_attach: end"); return (0); @@ -444,6 +467,9 @@ ixv_detach(device_t dev) ether_ifdetach(adapter->ifp); callout_drain(&adapter->timer); +#ifdef DEV_NETMAP + netmap_detach(adapter->ifp); +#endif /* DEV_NETMAP */ ixv_free_pci_resources(adapter); bus_generic_detach(dev); if_free(adapter->ifp); @@ -1665,10 +1691,6 @@ ixv_initialize_receive_units(struct adapter *adapter) reg |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), reg); - /* Set the Tail Pointer */ - IXGBE_WRITE_REG(hw, IXGBE_VFRDT(rxr->me), - adapter->num_rx_desc - 1); - /* Set the processing limit */ rxr->process_limit = ixv_rx_process_limit; @@ -1687,6 +1709,35 @@ ixv_initialize_receive_units(struct adapter *adapter) msec_delay(1); } wmb(); + + /* Set the Tail Pointer */ +#ifdef DEV_NETMAP + /* + * In netmap mode, we must preserve the buffers made + * available to userspace before the if_init() + * (this is true by default on the TX side, because + * init makes all buffers available to userspace). + * + * netmap_reset() and the device specific routines + * (e.g. ixgbe_setup_receive_rings()) map these + * buffers at the end of the NIC ring, so here we + * must set the RDT (tail) register to make sure + * they are not overwritten. + * + * In this driver the NIC ring starts at RDH = 0, + * RDT points to the last slot available for reception (?), + * so RDT = num_rx_desc - 1 means the whole ring is available. + */ + if (ifp->if_capenable & IFCAP_NETMAP) { + struct netmap_adapter *na = NA(adapter->ifp); + struct netmap_kring *kring = &na->rx_rings[i]; + int t = na->num_rx_desc - 1 - nm_kr_rxspace(kring); + + IXGBE_WRITE_REG(hw, IXGBE_VFRDT(rxr->me), t); + } else +#endif /* DEV_NETMAP */ + IXGBE_WRITE_REG(hw, IXGBE_VFRDT(rxr->me), + adapter->num_rx_desc - 1); } rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); diff --git a/sys/dev/ixgbe/ix_txrx.c b/sys/dev/ixgbe/ix_txrx.c index c20b24e7064c..96012b5b2cda 100644 --- a/sys/dev/ixgbe/ix_txrx.c +++ b/sys/dev/ixgbe/ix_txrx.c @@ -210,11 +210,7 @@ ixgbe_mq_start(struct ifnet *ifp, struct mbuf *m) * If everything is setup correctly, it should be the * same bucket that the current CPU we're on is. */ -#if __FreeBSD_version < 1100054 - if (m->m_flags & M_FLOWID) { -#else if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) { -#endif #ifdef RSS if (rss_hash2bucket(m->m_pkthdr.flowid, M_HASHTYPE_GET(m), &bucket_id) == 0) @@ -1910,53 +1906,60 @@ ixgbe_rxeof(struct ix_queue *que) } if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) ixgbe_rx_checksum(staterr, sendmp, ptype); -#if __FreeBSD_version >= 800000 -#ifdef RSS - sendmp->m_pkthdr.flowid = - le32toh(cur->wb.lower.hi_dword.rss); -#if __FreeBSD_version < 1100054 - sendmp->m_flags |= M_FLOWID; -#endif - switch (pkt_info & IXGBE_RXDADV_RSSTYPE_MASK) { - case IXGBE_RXDADV_RSSTYPE_IPV4_TCP: - M_HASHTYPE_SET(sendmp, M_HASHTYPE_RSS_TCP_IPV4); - break; - case IXGBE_RXDADV_RSSTYPE_IPV4: - M_HASHTYPE_SET(sendmp, M_HASHTYPE_RSS_IPV4); - break; - case IXGBE_RXDADV_RSSTYPE_IPV6_TCP: - M_HASHTYPE_SET(sendmp, M_HASHTYPE_RSS_TCP_IPV6); - break; - case IXGBE_RXDADV_RSSTYPE_IPV6_EX: - M_HASHTYPE_SET(sendmp, M_HASHTYPE_RSS_IPV6_EX); - break; - case IXGBE_RXDADV_RSSTYPE_IPV6: - M_HASHTYPE_SET(sendmp, M_HASHTYPE_RSS_IPV6); - break; - case IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX: - M_HASHTYPE_SET(sendmp, M_HASHTYPE_RSS_TCP_IPV6_EX); - break; - case IXGBE_RXDADV_RSSTYPE_IPV4_UDP: - M_HASHTYPE_SET(sendmp, M_HASHTYPE_RSS_UDP_IPV4); - break; - case IXGBE_RXDADV_RSSTYPE_IPV6_UDP: - M_HASHTYPE_SET(sendmp, M_HASHTYPE_RSS_UDP_IPV6); - break; - case IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX: - M_HASHTYPE_SET(sendmp, M_HASHTYPE_RSS_UDP_IPV6_EX); - break; - default: + + /* + * In case of multiqueue, we have RXCSUM.PCSD bit set + * and never cleared. This means we have RSS hash + * available to be used. + */ + if (adapter->num_queues > 1) { + sendmp->m_pkthdr.flowid = + le32toh(cur->wb.lower.hi_dword.rss); + switch (pkt_info & IXGBE_RXDADV_RSSTYPE_MASK) { + case IXGBE_RXDADV_RSSTYPE_IPV4_TCP: + M_HASHTYPE_SET(sendmp, + M_HASHTYPE_RSS_TCP_IPV4); + break; + case IXGBE_RXDADV_RSSTYPE_IPV4: + M_HASHTYPE_SET(sendmp, + M_HASHTYPE_RSS_IPV4); + break; + case IXGBE_RXDADV_RSSTYPE_IPV6_TCP: + M_HASHTYPE_SET(sendmp, + M_HASHTYPE_RSS_TCP_IPV6); + break; + case IXGBE_RXDADV_RSSTYPE_IPV6_EX: + M_HASHTYPE_SET(sendmp, + M_HASHTYPE_RSS_IPV6_EX); + break; + case IXGBE_RXDADV_RSSTYPE_IPV6: + M_HASHTYPE_SET(sendmp, + M_HASHTYPE_RSS_IPV6); + break; + case IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX: + M_HASHTYPE_SET(sendmp, + M_HASHTYPE_RSS_TCP_IPV6_EX); + break; + case IXGBE_RXDADV_RSSTYPE_IPV4_UDP: + M_HASHTYPE_SET(sendmp, + M_HASHTYPE_RSS_UDP_IPV4); + break; + case IXGBE_RXDADV_RSSTYPE_IPV6_UDP: + M_HASHTYPE_SET(sendmp, + M_HASHTYPE_RSS_UDP_IPV6); + break; + case IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX: + M_HASHTYPE_SET(sendmp, + M_HASHTYPE_RSS_UDP_IPV6_EX); + break; + default: + M_HASHTYPE_SET(sendmp, + M_HASHTYPE_OPAQUE); + } + } else { + sendmp->m_pkthdr.flowid = que->msix; M_HASHTYPE_SET(sendmp, M_HASHTYPE_OPAQUE); } -#else /* RSS */ - sendmp->m_pkthdr.flowid = que->msix; -#if __FreeBSD_version >= 1100054 - M_HASHTYPE_SET(sendmp, M_HASHTYPE_OPAQUE); -#else - sendmp->m_flags |= M_FLOWID; -#endif -#endif /* RSS */ -#endif /* FreeBSD_version */ } next_desc: bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map, diff --git a/sys/dev/ixgbe/ixgbe.h b/sys/dev/ixgbe/ixgbe.h index 7f8aac59cc7e..5aa26fe9dde4 100644 --- a/sys/dev/ixgbe/ixgbe.h +++ b/sys/dev/ixgbe/ixgbe.h @@ -555,6 +555,10 @@ struct adapter { #ifdef PCI_IOV struct ixgbe_vf *vfs; #endif +#ifdef DEV_NETMAP + void (*init_locked)(struct adapter *); + void (*stop_locked)(void *); +#endif /* Misc stats maintained by the driver */ unsigned long dropped_pkts; diff --git a/sys/dev/ixgbe/ixgbe_vf.c b/sys/dev/ixgbe/ixgbe_vf.c index 2ce4d32a303b..a00b8be0238c 100644 --- a/sys/dev/ixgbe/ixgbe_vf.c +++ b/sys/dev/ixgbe/ixgbe_vf.c @@ -225,6 +225,8 @@ s32 ixgbe_reset_hw_vf(struct ixgbe_hw *hw) if (ret_val) return ret_val; + msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS; + if (msgbuf[0] != (IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_ACK) && msgbuf[0] != (IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_NACK)) return IXGBE_ERR_INVALID_MAC_ADDR; diff --git a/sys/dev/ixl/if_ixl.c b/sys/dev/ixl/if_ixl.c index 1a36c2a9e9f8..f4f070477a56 100644 --- a/sys/dev/ixl/if_ixl.c +++ b/sys/dev/ixl/if_ixl.c @@ -1141,7 +1141,8 @@ ixl_init_locked(struct ixl_pf *pf) bcopy(IF_LLADDR(vsi->ifp), tmpaddr, I40E_ETH_LENGTH_OF_ADDRESS); if (!cmp_etheraddr(hw->mac.addr, tmpaddr) && - i40e_validate_mac_addr(tmpaddr)) { + (i40e_validate_mac_addr(tmpaddr) == I40E_SUCCESS)) { + ixl_del_filter(vsi, hw->mac.addr, IXL_VLAN_ANY); bcopy(tmpaddr, hw->mac.addr, I40E_ETH_LENGTH_OF_ADDRESS); ret = i40e_aq_mac_address_write(hw, @@ -1151,6 +1152,8 @@ ixl_init_locked(struct ixl_pf *pf) device_printf(dev, "LLA address" "change failed!!\n"); return; + } else { + ixl_add_filter(vsi, hw->mac.addr, IXL_VLAN_ANY); } } diff --git a/sys/dev/mmc/mmc.c b/sys/dev/mmc/mmc.c index a61da4446c05..e8871c71b787 100644 --- a/sys/dev/mmc/mmc.c +++ b/sys/dev/mmc/mmc.c @@ -1381,17 +1381,18 @@ mmc_discover_cards(struct mmc_softc *sc) } /* - * We reselect the card here. Some cards become - * unselected and timeout with the above two commands, - * although the state tables / diagrams in the standard - * suggest they go back to the transfer state. The only - * thing we use from the sd_status is the erase sector - * size, but it is still nice to get that right. It is - * normally harmless for cards not misbehaving. The - * Atmel bridge will complain about this command timing - * out. Others seem to handle it correctly, so it may - * be a combination of card and controller. + * We deselect then reselect the card here. Some cards + * become unselected and timeout with the above two + * commands, although the state tables / diagrams in the + * standard suggest they go back to the transfer state. + * Other cards don't become deselected, and if we + * atttempt to blindly re-select them, we get timeout + * errors from some controllers. So we deselect then + * reselect to handle all situations. The only thing we + * use from the sd_status is the erase sector size, but + * it is still nice to get that right. */ + mmc_select_card(sc, 0); mmc_select_card(sc, ivar->rca); mmc_app_sd_status(sc, ivar->rca, ivar->raw_sd_status); mmc_app_decode_sd_status(ivar->raw_sd_status, diff --git a/sys/dev/netmap/if_em_netmap.h b/sys/dev/netmap/if_em_netmap.h index 99eaa6f01319..eae4f8c18ca0 100644 --- a/sys/dev/netmap/if_em_netmap.h +++ b/sys/dev/netmap/if_em_netmap.h @@ -198,8 +198,6 @@ em_netmap_txsync(struct netmap_kring *kring, int flags) } } - nm_txsync_finalize(kring); - return 0; } @@ -217,7 +215,7 @@ em_netmap_rxsync(struct netmap_kring *kring, int flags) u_int nic_i; /* index into the NIC ring */ u_int n; u_int const lim = kring->nkr_num_slots - 1; - u_int const head = nm_rxsync_prologue(kring); + u_int const head = kring->rhead; int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; /* device-specific */ @@ -303,9 +301,6 @@ em_netmap_rxsync(struct netmap_kring *kring, int flags) E1000_WRITE_REG(&adapter->hw, E1000_RDT(rxr->me), nic_i); } - /* tell userspace that there might be new packets */ - nm_rxsync_finalize(kring); - return 0; ring_reset: diff --git a/sys/dev/netmap/if_igb_netmap.h b/sys/dev/netmap/if_igb_netmap.h index c73846073341..33b7b3b66547 100644 --- a/sys/dev/netmap/if_igb_netmap.h +++ b/sys/dev/netmap/if_igb_netmap.h @@ -180,8 +180,6 @@ igb_netmap_txsync(struct netmap_kring *kring, int flags) kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); } - nm_txsync_finalize(kring); - return 0; } @@ -199,7 +197,7 @@ igb_netmap_rxsync(struct netmap_kring *kring, int flags) u_int nic_i; /* index into the NIC ring */ u_int n; u_int const lim = kring->nkr_num_slots - 1; - u_int const head = nm_rxsync_prologue(kring); + u_int const head = kring->rhead; int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; /* device-specific */ @@ -283,9 +281,6 @@ igb_netmap_rxsync(struct netmap_kring *kring, int flags) E1000_WRITE_REG(&adapter->hw, E1000_RDT(rxr->me), nic_i); } - /* tell userspace that there might be new packets */ - nm_rxsync_finalize(kring); - return 0; ring_reset: diff --git a/sys/dev/netmap/if_ixl_netmap.h b/sys/dev/netmap/if_ixl_netmap.h index d6aff1f8c9a8..f7e7baaf6bc2 100644 --- a/sys/dev/netmap/if_ixl_netmap.h +++ b/sys/dev/netmap/if_ixl_netmap.h @@ -68,9 +68,14 @@ extern int ixl_rx_miss, ixl_rx_miss_bufs, ixl_crcstrip; * count packets that might be missed due to lost interrupts. */ SYSCTL_DECL(_dev_netmap); -int ixl_rx_miss, ixl_rx_miss_bufs, ixl_crcstrip; +/* + * The xl driver by default strips CRCs and we do not override it. + */ +int ixl_rx_miss, ixl_rx_miss_bufs, ixl_crcstrip = 1; +#if 0 SYSCTL_INT(_dev_netmap, OID_AUTO, ixl_crcstrip, - CTLFLAG_RW, &ixl_crcstrip, 0, "strip CRC on rx frames"); + CTLFLAG_RW, &ixl_crcstrip, 1, "strip CRC on rx frames"); +#endif SYSCTL_INT(_dev_netmap, OID_AUTO, ixl_rx_miss, CTLFLAG_RW, &ixl_rx_miss, 0, "potentially missed rx intr"); SYSCTL_INT(_dev_netmap, OID_AUTO, ixl_rx_miss_bufs, @@ -268,8 +273,6 @@ ixl_netmap_txsync(struct netmap_kring *kring, int flags) kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); } - nm_txsync_finalize(kring); - return 0; } @@ -297,7 +300,7 @@ ixl_netmap_rxsync(struct netmap_kring *kring, int flags) u_int nic_i; /* index into the NIC ring */ u_int n; u_int const lim = kring->nkr_num_slots - 1; - u_int const head = nm_rxsync_prologue(kring); + u_int const head = kring->rhead; int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; /* device-specific */ @@ -408,9 +411,6 @@ ixl_netmap_rxsync(struct netmap_kring *kring, int flags) wr32(vsi->hw, rxr->tail, nic_i); } - /* tell userspace that there might be new packets */ - nm_rxsync_finalize(kring); - return 0; ring_reset: diff --git a/sys/dev/netmap/if_lem_netmap.h b/sys/dev/netmap/if_lem_netmap.h index 50eb1f719929..0ec9b1346609 100644 --- a/sys/dev/netmap/if_lem_netmap.h +++ b/sys/dev/netmap/if_lem_netmap.h @@ -302,8 +302,6 @@ lem_netmap_txsync(struct netmap_kring *kring, int flags) kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); } - nm_txsync_finalize(kring); - return 0; } @@ -321,7 +319,7 @@ lem_netmap_rxsync(struct netmap_kring *kring, int flags) u_int nic_i; /* index into the NIC ring */ u_int n; u_int const lim = kring->nkr_num_slots - 1; - u_int const head = nm_rxsync_prologue(kring); + u_int const head = kring->rhead; int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; /* device-specific */ @@ -466,9 +464,6 @@ lem_netmap_rxsync(struct netmap_kring *kring, int flags) E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), nic_i); } - /* tell userspace that there might be new packets */ - nm_rxsync_finalize(kring); - return 0; ring_reset: diff --git a/sys/dev/netmap/if_re_netmap.h b/sys/dev/netmap/if_re_netmap.h index 354f14df1c58..ac08aedd7962 100644 --- a/sys/dev/netmap/if_re_netmap.h +++ b/sys/dev/netmap/if_re_netmap.h @@ -159,8 +159,6 @@ re_netmap_txsync(struct netmap_kring *kring, int flags) } } - nm_txsync_finalize(kring); - return 0; } @@ -178,7 +176,7 @@ re_netmap_rxsync(struct netmap_kring *kring, int flags) u_int nic_i; /* index into the NIC ring */ u_int n; u_int const lim = kring->nkr_num_slots - 1; - u_int const head = nm_rxsync_prologue(kring); + u_int const head = kring->rhead; int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; /* device-specific */ @@ -273,9 +271,6 @@ re_netmap_rxsync(struct netmap_kring *kring, int flags) BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); } - /* tell userspace that there might be new packets */ - nm_rxsync_finalize(kring); - return 0; ring_reset: diff --git a/sys/dev/netmap/if_vtnet_netmap.h b/sys/dev/netmap/if_vtnet_netmap.h index 63f4fa9aa5df..791cee56bcee 100644 --- a/sys/dev/netmap/if_vtnet_netmap.h +++ b/sys/dev/netmap/if_vtnet_netmap.h @@ -214,9 +214,6 @@ vtnet_netmap_txsync(struct netmap_kring *kring, int flags) virtqueue_postpone_intr(vq, VQ_POSTPONE_SHORT); } -//out: - nm_txsync_finalize(kring); - return 0; } @@ -278,7 +275,7 @@ vtnet_netmap_rxsync(struct netmap_kring *kring, int flags) // u_int nic_i; /* index into the NIC ring */ u_int n; u_int const lim = kring->nkr_num_slots - 1; - u_int const head = nm_rxsync_prologue(kring); + u_int const head = kring->rhead; int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; /* device-specific */ @@ -340,9 +337,6 @@ vtnet_netmap_rxsync(struct netmap_kring *kring, int flags) vtnet_rxq_enable_intr(rxq); } - /* tell userspace that there might be new packets. */ - nm_rxsync_finalize(kring); - ND("[C] h %d c %d t %d hwcur %d hwtail %d", ring->head, ring->cur, ring->tail, kring->nr_hwcur, kring->nr_hwtail); diff --git a/sys/dev/netmap/ixgbe_netmap.h b/sys/dev/netmap/ixgbe_netmap.h index f1f03cb6d7a7..0f34e7218503 100644 --- a/sys/dev/netmap/ixgbe_netmap.h +++ b/sys/dev/netmap/ixgbe_netmap.h @@ -26,7 +26,7 @@ /* * $FreeBSD$ * - * netmap support for: ixgbe + * netmap support for: ixgbe (both ix and ixv) * * This file is meant to be a reference on how to implement * netmap support for a network driver. @@ -48,6 +48,7 @@ */ #include +void ixgbe_netmap_attach(struct adapter *adapter); /* * device-specific sysctl variables: @@ -120,20 +121,19 @@ ixgbe_netmap_reg(struct netmap_adapter *na, int onoff) struct adapter *adapter = ifp->if_softc; IXGBE_CORE_LOCK(adapter); - ixgbe_disable_intr(adapter); // XXX maybe ixgbe_stop ? + adapter->stop_locked(adapter); - /* Tell the stack that the interface is no longer active */ - ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); - - set_crcstrip(&adapter->hw, onoff); + if (!IXGBE_IS_VF(adapter)) + set_crcstrip(&adapter->hw, onoff); /* enable or disable flags and callbacks in na and ifp */ if (onoff) { nm_set_native_flags(na); } else { nm_clear_native_flags(na); } - ixgbe_init_locked(adapter); /* also enables intr */ - set_crcstrip(&adapter->hw, onoff); // XXX why twice ? + adapter->init_locked(adapter); /* also enables intr */ + if (!IXGBE_IS_VF(adapter)) + set_crcstrip(&adapter->hw, onoff); // XXX why twice ? IXGBE_CORE_UNLOCK(adapter); return (ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1); } @@ -266,7 +266,7 @@ ixgbe_netmap_txsync(struct netmap_kring *kring, int flags) BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); /* (re)start the tx unit up to slot nic_i (excluded) */ - IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(txr->me), nic_i); + IXGBE_WRITE_REG(&adapter->hw, txr->tail, nic_i); } /* @@ -310,7 +310,8 @@ ixgbe_netmap_txsync(struct netmap_kring *kring, int flags) * REPORT_STATUS in a few slots so TDH is the only * good way. */ - nic_i = IXGBE_READ_REG(&adapter->hw, IXGBE_TDH(kring->ring_id)); + nic_i = IXGBE_READ_REG(&adapter->hw, IXGBE_IS_VF(adapter) ? + IXGBE_VFTDH(kring->ring_id) : IXGBE_TDH(kring->ring_id)); if (nic_i >= kring->nkr_num_slots) { /* XXX can it happen ? */ D("TDH wrap %d", nic_i); nic_i -= kring->nkr_num_slots; @@ -322,8 +323,6 @@ ixgbe_netmap_txsync(struct netmap_kring *kring, int flags) } } - nm_txsync_finalize(kring); - return 0; } @@ -351,7 +350,7 @@ ixgbe_netmap_rxsync(struct netmap_kring *kring, int flags) u_int nic_i; /* index into the NIC ring */ u_int n; u_int const lim = kring->nkr_num_slots - 1; - u_int const head = nm_rxsync_prologue(kring); + u_int const head = kring->rhead; int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; /* device-specific */ @@ -381,7 +380,7 @@ ixgbe_netmap_rxsync(struct netmap_kring *kring, int flags) * rxr->next_to_check is set to 0 on a ring reinit */ if (netmap_no_pendintr || force_update) { - int crclen = ix_crcstrip ? 0 : 4; + int crclen = (ix_crcstrip || IXGBE_IS_VF(adapter) ) ? 0 : 4; uint16_t slot_flags = kring->nkr_slot_flags; nic_i = rxr->next_to_check; // or also k2n(kring->nr_hwtail) @@ -455,12 +454,9 @@ ixgbe_netmap_rxsync(struct netmap_kring *kring, int flags) * so move nic_i back by one unit */ nic_i = nm_prev(nic_i, lim); - IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(rxr->me), nic_i); + IXGBE_WRITE_REG(&adapter->hw, rxr->tail, nic_i); } - /* tell userspace that there might be new packets */ - nm_rxsync_finalize(kring); - return 0; ring_reset: @@ -475,7 +471,7 @@ ring_reset: * netmap mode will be disabled and the driver will only * operate in standard mode. */ -static void +void ixgbe_netmap_attach(struct adapter *adapter) { struct netmap_adapter na; diff --git a/sys/dev/netmap/netmap.c b/sys/dev/netmap/netmap.c index 11229ccf6b87..8094fe35256c 100644 --- a/sys/dev/netmap/netmap.c +++ b/sys/dev/netmap/netmap.c @@ -293,7 +293,7 @@ ports attached to the switch) * kring->nm_sync() == DEVICE_netmap_rxsync() * 2) device interrupt handler * na->nm_notify() == netmap_notify() - * - tx from host stack + * - rx from host stack * concurrently: * 1) host stack * netmap_transmit() @@ -313,31 +313,113 @@ ports attached to the switch) * * -= SYSTEM DEVICE WITH GENERIC SUPPORT =- * + * na == NA(ifp) == generic_netmap_adapter created in generic_netmap_attach() + * + * - tx from netmap userspace: + * concurrently: + * 1) ioctl(NIOCTXSYNC)/netmap_poll() in process context + * kring->nm_sync() == generic_netmap_txsync() + * linux: dev_queue_xmit() with NM_MAGIC_PRIORITY_TX + * generic_ndo_start_xmit() + * orig. dev. start_xmit + * FreeBSD: na->if_transmit() == orig. dev if_transmit + * 2) generic_mbuf_destructor() + * na->nm_notify() == netmap_notify() + * - rx from netmap userspace: + * 1) ioctl(NIOCRXSYNC)/netmap_poll() in process context + * kring->nm_sync() == generic_netmap_rxsync() + * mbq_safe_dequeue() + * 2) device driver + * generic_rx_handler() + * mbq_safe_enqueue() + * na->nm_notify() == netmap_notify() + * - rx from host stack: + * concurrently: + * 1) host stack + * linux: generic_ndo_start_xmit() + * netmap_transmit() + * FreeBSD: ifp->if_input() == netmap_transmit + * both: + * na->nm_notify() == netmap_notify() + * 2) ioctl(NIOCRXSYNC)/netmap_poll() in process context + * kring->nm_sync() == netmap_rxsync_from_host_compat + * netmap_rxsync_from_host(na, NULL, NULL) + * - tx to host stack: + * ioctl(NIOCTXSYNC)/netmap_poll() in process context + * kring->nm_sync() == netmap_txsync_to_host_compat + * netmap_txsync_to_host(na) + * NM_SEND_UP() + * FreeBSD: na->if_input() == ??? XXX + * linux: netif_rx() with NM_MAGIC_PRIORITY_RX * * - * -= VALE PORT =- + * -= VALE =- * + * INCOMING: * + * - VALE ports: + * ioctl(NIOCTXSYNC)/netmap_poll() in process context + * kring->nm_sync() == netmap_vp_txsync() * - * -= NETMAP PIPE =- + * - system device with native support: + * from cable: + * interrupt + * na->nm_notify() == netmap_bwrap_intr_notify(ring_nr != host ring) + * kring->nm_sync() == DEVICE_netmap_rxsync() + * netmap_vp_txsync() + * kring->nm_sync() == DEVICE_netmap_rxsync() + * from host stack: + * netmap_transmit() + * na->nm_notify() == netmap_bwrap_intr_notify(ring_nr == host ring) + * kring->nm_sync() == netmap_rxsync_from_host_compat() + * netmap_vp_txsync() * + * - system device with generic support: + * from device driver: + * generic_rx_handler() + * na->nm_notify() == netmap_bwrap_intr_notify(ring_nr != host ring) + * kring->nm_sync() == generic_netmap_rxsync() + * netmap_vp_txsync() + * kring->nm_sync() == generic_netmap_rxsync() + * from host stack: + * netmap_transmit() + * na->nm_notify() == netmap_bwrap_intr_notify(ring_nr == host ring) + * kring->nm_sync() == netmap_rxsync_from_host_compat() + * netmap_vp_txsync() * + * (all cases) --> nm_bdg_flush() + * dest_na->nm_notify() == (see below) * - * -= SYSTEM DEVICE WITH NATIVE SUPPORT, CONNECTED TO VALE, NO HOST RINGS =- + * OUTGOING: * + * - VALE ports: + * concurrently: + * 1) ioctlNIOCRXSYNC)/netmap_poll() in process context + * kring->nm_sync() == netmap_vp_rxsync() + * 2) from nm_bdg_flush() + * na->nm_notify() == netmap_notify() * + * - system device with native support: + * to cable: + * na->nm_notify() == netmap_bwrap_notify() + * netmap_vp_rxsync() + * kring->nm_sync() == DEVICE_netmap_txsync() + * netmap_vp_rxsync() + * to host stack: + * netmap_vp_rxsync() + * kring->nm_sync() == netmap_txsync_to_host_compat + * netmap_vp_rxsync_locked() * - * -= SYSTEM DEVICE WITH NATIVE SUPPORT, CONNECTED TO VALE, WITH HOST RINGS =- - * - * - * - * -= SYSTEM DEVICE WITH GENERIC SUPPORT, CONNECTED TO VALE, NO HOST RINGS =- - * - * - * - * -= SYSTEM DEVICE WITH GENERIC SUPPORT, CONNECTED TO VALE, WITH HOST RINGS =- - * - * + * - system device with generic adapter: + * to device driver: + * na->nm_notify() == netmap_bwrap_notify() + * netmap_vp_rxsync() + * kring->nm_sync() == generic_netmap_txsync() + * netmap_vp_rxsync() + * to host stack: + * netmap_vp_rxsync() + * kring->nm_sync() == netmap_txsync_to_host_compat + * netmap_vp_rxsync() * */ @@ -412,15 +494,6 @@ ports attached to the switch) MALLOC_DEFINE(M_NETMAP, "netmap", "Network memory map"); -/* - * The following variables are used by the drivers and replicate - * fields in the global memory pool. They only refer to buffers - * used by physical interfaces. - */ -u_int netmap_total_buffers; -u_int netmap_buf_size; -char *netmap_buffer_base; /* also address of an invalid buffer */ - /* user-controlled variables */ int netmap_verbose; @@ -446,7 +519,6 @@ SYSCTL_INT(_dev_netmap, OID_AUTO, adaptive_io, CTLFLAG_RW, int netmap_flags = 0; /* debug flags */ int netmap_fwd = 0; /* force transparent mode */ -int netmap_mmap_unreg = 0; /* allow mmap of unregistered fds */ /* * netmap_admode selects the netmap mode to use. @@ -464,22 +536,13 @@ int netmap_generic_rings = 1; /* number of queues in generic. */ SYSCTL_INT(_dev_netmap, OID_AUTO, flags, CTLFLAG_RW, &netmap_flags, 0 , ""); SYSCTL_INT(_dev_netmap, OID_AUTO, fwd, CTLFLAG_RW, &netmap_fwd, 0 , ""); -SYSCTL_INT(_dev_netmap, OID_AUTO, mmap_unreg, CTLFLAG_RW, &netmap_mmap_unreg, 0, ""); SYSCTL_INT(_dev_netmap, OID_AUTO, admode, CTLFLAG_RW, &netmap_admode, 0 , ""); SYSCTL_INT(_dev_netmap, OID_AUTO, generic_mit, CTLFLAG_RW, &netmap_generic_mit, 0 , ""); SYSCTL_INT(_dev_netmap, OID_AUTO, generic_ringsize, CTLFLAG_RW, &netmap_generic_ringsize, 0 , ""); SYSCTL_INT(_dev_netmap, OID_AUTO, generic_rings, CTLFLAG_RW, &netmap_generic_rings, 0 , ""); NMG_LOCK_T netmap_global_lock; - - -static void -nm_kr_get(struct netmap_kring *kr) -{ - while (NM_ATOMIC_TEST_AND_SET(&kr->nr_busy)) - tsleep(kr, 0, "NM_KR_GET", 4); -} - +int netmap_use_count = 0; /* number of active netmap instances */ /* * mark the ring as stopped, and run through the locks @@ -495,34 +558,14 @@ netmap_disable_ring(struct netmap_kring *kr) nm_kr_put(kr); } -/* stop or enable a single tx ring */ +/* stop or enable a single ring */ void -netmap_set_txring(struct netmap_adapter *na, u_int ring_id, int stopped) +netmap_set_ring(struct netmap_adapter *na, u_int ring_id, enum txrx t, int stopped) { if (stopped) - netmap_disable_ring(na->tx_rings + ring_id); + netmap_disable_ring(NMR(na, t) + ring_id); else - na->tx_rings[ring_id].nkr_stopped = 0; - /* nofify that the stopped state has changed. This is currently - *only used by bwrap to propagate the state to its own krings. - * (see netmap_bwrap_intr_notify). - */ - na->nm_notify(na, ring_id, NR_TX, NAF_DISABLE_NOTIFY); -} - -/* stop or enable a single rx ring */ -void -netmap_set_rxring(struct netmap_adapter *na, u_int ring_id, int stopped) -{ - if (stopped) - netmap_disable_ring(na->rx_rings + ring_id); - else - na->rx_rings[ring_id].nkr_stopped = 0; - /* nofify that the stopped state has changed. This is currently - *only used by bwrap to propagate the state to its own krings. - * (see netmap_bwrap_intr_notify). - */ - na->nm_notify(na, ring_id, NR_RX, NAF_DISABLE_NOTIFY); + NMR(na, t)[ring_id].nkr_stopped = 0; } @@ -531,20 +574,15 @@ void netmap_set_all_rings(struct netmap_adapter *na, int stopped) { int i; - u_int ntx, nrx; + enum txrx t; if (!nm_netmap_on(na)) return; - ntx = netmap_real_tx_rings(na); - nrx = netmap_real_rx_rings(na); - - for (i = 0; i < ntx; i++) { - netmap_set_txring(na, i, stopped); - } - - for (i = 0; i < nrx; i++) { - netmap_set_rxring(na, i, stopped); + for_rx_tx(t) { + for (i = 0; i < netmap_real_rings(na, t); i++) { + netmap_set_ring(na, i, t, stopped); + } } } @@ -657,7 +695,8 @@ netmap_update_config(struct netmap_adapter *na) txr = txd = rxr = rxd = 0; if (na->nm_config == NULL || - na->nm_config(na, &txr, &txd, &rxr, &rxd)) { + na->nm_config(na, &txr, &txd, &rxr, &rxd)) + { /* take whatever we had at init time */ txr = na->num_tx_rings; txd = na->num_tx_desc; @@ -688,6 +727,9 @@ netmap_update_config(struct netmap_adapter *na) return 1; } +static void netmap_txsync_to_host(struct netmap_adapter *na); +static int netmap_rxsync_from_host(struct netmap_adapter *na, struct thread *td, void *pwait); + /* kring->nm_sync callback for the host tx ring */ static int netmap_txsync_to_host_compat(struct netmap_kring *kring, int flags) @@ -738,73 +780,59 @@ netmap_krings_create(struct netmap_adapter *na, u_int tailroom) { u_int i, len, ndesc; struct netmap_kring *kring; - u_int ntx, nrx; + u_int n[NR_TXRX]; + enum txrx t; /* account for the (possibly fake) host rings */ - ntx = na->num_tx_rings + 1; - nrx = na->num_rx_rings + 1; + n[NR_TX] = na->num_tx_rings + 1; + n[NR_RX] = na->num_rx_rings + 1; - len = (ntx + nrx) * sizeof(struct netmap_kring) + tailroom; + len = (n[NR_TX] + n[NR_RX]) * sizeof(struct netmap_kring) + tailroom; na->tx_rings = malloc((size_t)len, M_DEVBUF, M_NOWAIT | M_ZERO); if (na->tx_rings == NULL) { D("Cannot allocate krings"); return ENOMEM; } - na->rx_rings = na->tx_rings + ntx; + na->rx_rings = na->tx_rings + n[NR_TX]; /* * All fields in krings are 0 except the one initialized below. * but better be explicit on important kring fields. */ - ndesc = na->num_tx_desc; - for (i = 0; i < ntx; i++) { /* Transmit rings */ - kring = &na->tx_rings[i]; - bzero(kring, sizeof(*kring)); - kring->na = na; - kring->ring_id = i; - kring->nkr_num_slots = ndesc; - if (i < na->num_tx_rings) { - kring->nm_sync = na->nm_txsync; - } else if (i == na->num_tx_rings) { - kring->nm_sync = netmap_txsync_to_host_compat; + for_rx_tx(t) { + ndesc = nma_get_ndesc(na, t); + for (i = 0; i < n[t]; i++) { + kring = &NMR(na, t)[i]; + bzero(kring, sizeof(*kring)); + kring->na = na; + kring->ring_id = i; + kring->tx = t; + kring->nkr_num_slots = ndesc; + if (i < nma_get_nrings(na, t)) { + kring->nm_sync = (t == NR_TX ? na->nm_txsync : na->nm_rxsync); + } else if (i == na->num_tx_rings) { + kring->nm_sync = (t == NR_TX ? + netmap_txsync_to_host_compat : + netmap_rxsync_from_host_compat); + } + kring->nm_notify = na->nm_notify; + kring->rhead = kring->rcur = kring->nr_hwcur = 0; + /* + * IMPORTANT: Always keep one slot empty. + */ + kring->rtail = kring->nr_hwtail = (t == NR_TX ? ndesc - 1 : 0); + snprintf(kring->name, sizeof(kring->name) - 1, "%s %s%d", na->name, + nm_txrx2str(t), i); + ND("ktx %s h %d c %d t %d", + kring->name, kring->rhead, kring->rcur, kring->rtail); + mtx_init(&kring->q_lock, (t == NR_TX ? "nm_txq_lock" : "nm_rxq_lock"), NULL, MTX_DEF); + init_waitqueue_head(&kring->si); } - /* - * IMPORTANT: Always keep one slot empty. - */ - kring->rhead = kring->rcur = kring->nr_hwcur = 0; - kring->rtail = kring->nr_hwtail = ndesc - 1; - snprintf(kring->name, sizeof(kring->name) - 1, "%s TX%d", na->name, i); - ND("ktx %s h %d c %d t %d", - kring->name, kring->rhead, kring->rcur, kring->rtail); - mtx_init(&kring->q_lock, "nm_txq_lock", NULL, MTX_DEF); - init_waitqueue_head(&kring->si); + init_waitqueue_head(&na->si[t]); } - ndesc = na->num_rx_desc; - for (i = 0; i < nrx; i++) { /* Receive rings */ - kring = &na->rx_rings[i]; - bzero(kring, sizeof(*kring)); - kring->na = na; - kring->ring_id = i; - kring->nkr_num_slots = ndesc; - if (i < na->num_rx_rings) { - kring->nm_sync = na->nm_rxsync; - } else if (i == na->num_rx_rings) { - kring->nm_sync = netmap_rxsync_from_host_compat; - } - kring->rhead = kring->rcur = kring->nr_hwcur = 0; - kring->rtail = kring->nr_hwtail = 0; - snprintf(kring->name, sizeof(kring->name) - 1, "%s RX%d", na->name, i); - ND("krx %s h %d c %d t %d", - kring->name, kring->rhead, kring->rcur, kring->rtail); - mtx_init(&kring->q_lock, "nm_rxq_lock", NULL, MTX_DEF); - init_waitqueue_head(&kring->si); - } - init_waitqueue_head(&na->tx_si); - init_waitqueue_head(&na->rx_si); - - na->tailroom = na->rx_rings + nrx; + na->tailroom = na->rx_rings + n[NR_RX]; return 0; } @@ -829,6 +857,10 @@ void netmap_krings_delete(struct netmap_adapter *na) { struct netmap_kring *kring = na->tx_rings; + enum txrx t; + + for_rx_tx(t) + netmap_knlist_destroy(&na->si[t]); /* we rely on the krings layout described above */ for ( ; kring != na->tailroom; kring++) { @@ -858,142 +890,35 @@ netmap_hw_krings_delete(struct netmap_adapter *na) } -/* create a new netmap_if for a newly registered fd. - * If this is the first registration of the adapter, - * also create the netmap rings and their in-kernel view, - * the netmap krings. - */ -/* call with NMG_LOCK held */ -static struct netmap_if* -netmap_if_new(struct netmap_adapter *na) -{ - struct netmap_if *nifp; - - if (netmap_update_config(na)) { - /* configuration mismatch, report and fail */ - return NULL; - } - - if (na->active_fds) /* already registered */ - goto final; - - /* create and init the krings arrays. - * Depending on the adapter, this may also create - * the netmap rings themselves - */ - if (na->nm_krings_create(na)) - return NULL; - - /* create all missing netmap rings */ - if (netmap_mem_rings_create(na)) - goto cleanup; - -final: - - /* in all cases, create a new netmap if */ - nifp = netmap_mem_if_new(na); - if (nifp == NULL) - goto cleanup; - - return (nifp); - -cleanup: - - if (na->active_fds == 0) { - netmap_mem_rings_delete(na); - na->nm_krings_delete(na); - } - - return NULL; -} - - -/* grab a reference to the memory allocator, if we don't have one already. The - * reference is taken from the netmap_adapter registered with the priv. - */ -/* call with NMG_LOCK held */ -static int -netmap_get_memory_locked(struct netmap_priv_d* p) -{ - struct netmap_mem_d *nmd; - int error = 0; - - if (p->np_na == NULL) { - if (!netmap_mmap_unreg) - return ENODEV; - /* for compatibility with older versions of the API - * we use the global allocator when no interface has been - * registered - */ - nmd = &nm_mem; - } else { - nmd = p->np_na->nm_mem; - } - if (p->np_mref == NULL) { - error = netmap_mem_finalize(nmd, p->np_na); - if (!error) - p->np_mref = nmd; - } else if (p->np_mref != nmd) { - /* a virtual port has been registered, but previous - * syscalls already used the global allocator. - * We cannot continue - */ - error = ENODEV; - } - return error; -} - - -/* call with NMG_LOCK *not* held */ -int -netmap_get_memory(struct netmap_priv_d* p) -{ - int error; - NMG_LOCK(); - error = netmap_get_memory_locked(p); - NMG_UNLOCK(); - return error; -} - - -/* call with NMG_LOCK held */ -static int -netmap_have_memory_locked(struct netmap_priv_d* p) -{ - return p->np_mref != NULL; -} - - -/* call with NMG_LOCK held */ -static void -netmap_drop_memory_locked(struct netmap_priv_d* p) -{ - if (p->np_mref) { - netmap_mem_deref(p->np_mref, p->np_na); - p->np_mref = NULL; - } -} - /* - * Call nm_register(ifp,0) to stop netmap mode on the interface and + * Undo everything that was done in netmap_do_regif(). In particular, + * call nm_register(ifp,0) to stop netmap mode on the interface and * revert to normal operation. - * The second argument is the nifp to work on. In some cases it is - * not attached yet to the netmap_priv_d so we need to pass it as - * a separate argument. */ /* call with NMG_LOCK held */ +static void netmap_unset_ringid(struct netmap_priv_d *); +static void netmap_rel_exclusive(struct netmap_priv_d *); static void -netmap_do_unregif(struct netmap_priv_d *priv, struct netmap_if *nifp) +netmap_do_unregif(struct netmap_priv_d *priv) { struct netmap_adapter *na = priv->np_na; NMG_LOCK_ASSERT(); na->active_fds--; + /* release exclusive use if it was requested on regif */ + netmap_rel_exclusive(priv); if (na->active_fds <= 0) { /* last instance */ if (netmap_verbose) D("deleting last instance for %s", na->name); + +#ifdef WITH_MONITOR + /* walk through all the rings and tell any monitor + * that the port is going to exit netmap mode + */ + netmap_monitor_stop(na); +#endif /* * (TO CHECK) This function is only called * when the last reference to this file descriptor goes @@ -1014,39 +939,36 @@ netmap_do_unregif(struct netmap_priv_d *priv, struct netmap_if *nifp) * XXX The wake up now must happen during *_down(), when * we order all activities to stop. -gl */ - netmap_knlist_destroy(&na->tx_si); - netmap_knlist_destroy(&na->rx_si); - /* delete rings and buffers */ netmap_mem_rings_delete(na); na->nm_krings_delete(na); } + /* possibily decrement counter of tx_si/rx_si users */ + netmap_unset_ringid(priv); /* delete the nifp */ - netmap_mem_if_delete(na, nifp); + netmap_mem_if_delete(na, priv->np_nifp); + /* drop the allocator */ + netmap_mem_deref(na->nm_mem, na); + /* mark the priv as unregistered */ + priv->np_na = NULL; + priv->np_nifp = NULL; } /* call with NMG_LOCK held */ static __inline int -nm_tx_si_user(struct netmap_priv_d *priv) +nm_si_user(struct netmap_priv_d *priv, enum txrx t) { return (priv->np_na != NULL && - (priv->np_txqlast - priv->np_txqfirst > 1)); + (priv->np_qlast[t] - priv->np_qfirst[t] > 1)); } -/* call with NMG_LOCK held */ -static __inline int -nm_rx_si_user(struct netmap_priv_d *priv) -{ - return (priv->np_na != NULL && - (priv->np_rxqlast - priv->np_rxqfirst > 1)); -} - - /* - * Destructor of the netmap_priv_d, called when the fd has - * no active open() and mmap(). Also called in error paths. + * Destructor of the netmap_priv_d, called when the fd is closed + * Action: undo all the things done by NIOCREGIF, + * On FreeBSD we need to track whether there are active mmap()s, + * and we use np_active_mmaps for that. On linux, the field is always 0. + * Return: 1 if we can free priv, 0 otherwise. * - * returns 1 if this is the last instance and we can free priv */ /* call with NMG_LOCK held */ int @@ -1054,29 +976,16 @@ netmap_dtor_locked(struct netmap_priv_d *priv) { struct netmap_adapter *na = priv->np_na; -#ifdef __FreeBSD__ - /* - * np_refcount is the number of active mmaps on - * this file descriptor - */ - if (--priv->np_refcount > 0) { + /* number of active references to this fd */ + if (--priv->np_refs > 0) { return 0; } -#endif /* __FreeBSD__ */ + netmap_use_count--; if (!na) { - return 1; //XXX is it correct? - } - netmap_do_unregif(priv, priv->np_nifp); - priv->np_nifp = NULL; - netmap_drop_memory_locked(priv); - if (priv->np_na) { - if (nm_tx_si_user(priv)) - na->tx_si_users--; - if (nm_rx_si_user(priv)) - na->rx_si_users--; - netmap_adapter_put(na); - priv->np_na = NULL; + return 1; //XXX is it correct? } + netmap_do_unregif(priv); + netmap_adapter_put(na); return 1; } @@ -1148,7 +1057,7 @@ static void netmap_grab_packets(struct netmap_kring *kring, struct mbq *q, int force) { u_int const lim = kring->nkr_num_slots - 1; - u_int const head = kring->ring->head; + u_int const head = kring->rhead; u_int n; struct netmap_adapter *na = kring->na; @@ -1231,11 +1140,10 @@ netmap_sw_to_nic(struct netmap_adapter *na) * can be among multiple user threads erroneously calling * this routine concurrently. */ -void +static void netmap_txsync_to_host(struct netmap_adapter *na) { struct netmap_kring *kring = &na->tx_rings[na->num_tx_rings]; - struct netmap_ring *ring = kring->ring; u_int const lim = kring->nkr_num_slots - 1; u_int const head = kring->rhead; struct mbq q; @@ -1246,14 +1154,12 @@ netmap_txsync_to_host(struct netmap_adapter *na) * the queue is drained in all cases. */ mbq_init(&q); - ring->cur = head; netmap_grab_packets(kring, &q, 1 /* force */); ND("have %d pkts in queue", mbq_len(&q)); kring->nr_hwcur = head; kring->nr_hwtail = head + lim; if (kring->nr_hwtail > lim) kring->nr_hwtail -= lim + 1; - nm_txsync_finalize(kring); netmap_send_up(na->ifp, &q); } @@ -1272,7 +1178,7 @@ netmap_txsync_to_host(struct netmap_adapter *na) * returns the number of packets delivered to tx queues in * transparent mode, or a negative value if error */ -int +static int netmap_rxsync_from_host(struct netmap_adapter *na, struct thread *td, void *pwait) { struct netmap_kring *kring = &na->rx_rings[na->num_rx_rings]; @@ -1281,11 +1187,13 @@ netmap_rxsync_from_host(struct netmap_adapter *na, struct thread *td, void *pwai u_int const lim = kring->nkr_num_slots - 1; u_int const head = kring->rhead; int ret = 0; - struct mbq *q = &kring->rx_queue; + struct mbq *q = &kring->rx_queue, fq; (void)pwait; /* disable unused warnings */ (void)td; + mbq_init(&fq); /* fq holds packets to be freed */ + mbq_lock(q); /* First part: import newly received packets */ @@ -1308,7 +1216,7 @@ netmap_rxsync_from_host(struct netmap_adapter *na, struct thread *td, void *pwai slot->len = len; slot->flags = kring->nkr_slot_flags; nm_i = nm_next(nm_i, lim); - m_freem(m); + mbq_enqueue(&fq, m); } kring->nr_hwtail = nm_i; } @@ -1323,13 +1231,15 @@ netmap_rxsync_from_host(struct netmap_adapter *na, struct thread *td, void *pwai kring->nr_hwcur = head; } - nm_rxsync_finalize(kring); - /* access copies of cur,tail in the kring */ if (kring->rcur == kring->rtail && td) /* no bufs available */ OS_selrecord(td, &kring->si); mbq_unlock(q); + + mbq_purge(&fq); + mbq_destroy(&fq); + return ret; } @@ -1363,9 +1273,11 @@ netmap_get_hw_na(struct ifnet *ifp, struct netmap_adapter **na) { /* generic support */ int i = netmap_admode; /* Take a snapshot. */ - int error = 0; struct netmap_adapter *prev_na; +#ifdef WITH_GENERIC struct netmap_generic_adapter *gna; + int error = 0; +#endif *na = NULL; /* default */ @@ -1401,6 +1313,7 @@ netmap_get_hw_na(struct ifnet *ifp, struct netmap_adapter **na) if (!NETMAP_CAPABLE(ifp) && i == NETMAP_ADMODE_NATIVE) return EOPNOTSUPP; +#ifdef WITH_GENERIC /* Otherwise, create a generic adapter and return it, * saving the previously used netmap adapter, if any. * @@ -1431,6 +1344,9 @@ netmap_get_hw_na(struct ifnet *ifp, struct netmap_adapter **na) ND("Created generic NA %p (prev %p)", gna, gna->prev); return 0; +#else /* !WITH_GENERIC */ + return EOPNOTSUPP; +#endif } @@ -1489,7 +1405,7 @@ netmap_get_na(struct nmreq *nmr, struct netmap_adapter **na, int create) return error; if (*na != NULL) /* valid match in netmap_get_bdg_na() */ - goto pipes; + goto out; /* * This must be a hardware na, lookup the name in the system. @@ -1509,14 +1425,6 @@ netmap_get_na(struct nmreq *nmr, struct netmap_adapter **na, int create) *na = ret; netmap_adapter_get(ret); -pipes: - /* - * If we are opening a pipe whose parent was not in netmap mode, - * we have to allocate the pipe array now. - * XXX get rid of this clumsiness (2014-03-15) - */ - error = netmap_pipe_alloc(*na, nmr); - out: if (error && ret != NULL) netmap_adapter_put(ret); @@ -1541,9 +1449,10 @@ out: * * hwcur, rhead, rtail and hwtail are reliable */ -u_int +static u_int nm_txsync_prologue(struct netmap_kring *kring) { +#define NM_ASSERT(t) if (t) { D("fail " #t); goto error; } struct netmap_ring *ring = kring->ring; u_int head = ring->head; /* read only once */ u_int cur = ring->cur; /* read only once */ @@ -1569,25 +1478,20 @@ nm_txsync_prologue(struct netmap_kring *kring) */ if (kring->rtail >= kring->rhead) { /* want rhead <= head <= rtail */ - if (head < kring->rhead || head > kring->rtail) - goto error; + NM_ASSERT(head < kring->rhead || head > kring->rtail); /* and also head <= cur <= rtail */ - if (cur < head || cur > kring->rtail) - goto error; + NM_ASSERT(cur < head || cur > kring->rtail); } else { /* here rtail < rhead */ /* we need head outside rtail .. rhead */ - if (head > kring->rtail && head < kring->rhead) - goto error; + NM_ASSERT(head > kring->rtail && head < kring->rhead); /* two cases now: head <= rtail or head >= rhead */ if (head <= kring->rtail) { /* want head <= cur <= rtail */ - if (cur < head || cur > kring->rtail) - goto error; + NM_ASSERT(cur < head || cur > kring->rtail); } else { /* head >= rhead */ /* cur must be outside rtail..head */ - if (cur > kring->rtail && cur < head) - goto error; + NM_ASSERT(cur > kring->rtail && cur < head); } } if (ring->tail != kring->rtail) { @@ -1600,12 +1504,13 @@ nm_txsync_prologue(struct netmap_kring *kring) return head; error: - RD(5, "%s kring error: hwcur %d rcur %d hwtail %d cur %d tail %d", + RD(5, "%s kring error: head %d cur %d tail %d rhead %d rcur %d rtail %d hwcur %d hwtail %d", kring->name, - kring->nr_hwcur, - kring->rcur, kring->nr_hwtail, - cur, ring->tail); + head, cur, ring->tail, + kring->rhead, kring->rcur, kring->rtail, + kring->nr_hwcur, kring->nr_hwtail); return n; +#undef NM_ASSERT } @@ -1620,14 +1525,14 @@ error: * hwcur and hwtail are reliable. * */ -u_int +static u_int nm_rxsync_prologue(struct netmap_kring *kring) { struct netmap_ring *ring = kring->ring; uint32_t const n = kring->nkr_num_slots; uint32_t head, cur; - ND("%s kc %d kt %d h %d c %d t %d", + ND(5,"%s kc %d kt %d h %d c %d t %d", kring->name, kring->nr_hwcur, kring->nr_hwtail, ring->head, ring->cur, ring->tail); @@ -1719,7 +1624,7 @@ netmap_ring_reinit(struct netmap_kring *kring) for (i = 0; i <= lim; i++) { u_int idx = ring->slot[i].buf_idx; u_int len = ring->slot[i].len; - if (idx < 2 || idx >= netmap_total_buffers) { + if (idx < 2 || idx >= kring->na->na_lut.objtotal) { RD(5, "bad index at slot %d idx %d len %d ", i, idx, len); ring->slot[i].buf_idx = 0; ring->slot[i].len = 0; @@ -1754,6 +1659,7 @@ netmap_interp_ringid(struct netmap_priv_d *priv, uint16_t ringid, uint32_t flags struct netmap_adapter *na = priv->np_na; u_int j, i = ringid & NETMAP_RING_MASK; u_int reg = flags & NR_REG_MASK; + enum txrx t; if (reg == NR_REG_DEFAULT) { /* convert from old ringid to flags */ @@ -1770,12 +1676,12 @@ netmap_interp_ringid(struct netmap_priv_d *priv, uint16_t ringid, uint32_t flags case NR_REG_ALL_NIC: case NR_REG_PIPE_MASTER: case NR_REG_PIPE_SLAVE: - priv->np_txqfirst = 0; - priv->np_txqlast = na->num_tx_rings; - priv->np_rxqfirst = 0; - priv->np_rxqlast = na->num_rx_rings; + for_rx_tx(t) { + priv->np_qfirst[t] = 0; + priv->np_qlast[t] = nma_get_nrings(na, t); + } ND("%s %d %d", "ALL/PIPE", - priv->np_rxqfirst, priv->np_rxqlast); + priv->np_qfirst[NR_RX], priv->np_qlast[NR_RX]); break; case NR_REG_SW: case NR_REG_NIC_SW: @@ -1783,31 +1689,27 @@ netmap_interp_ringid(struct netmap_priv_d *priv, uint16_t ringid, uint32_t flags D("host rings not supported"); return EINVAL; } - priv->np_txqfirst = (reg == NR_REG_SW ? - na->num_tx_rings : 0); - priv->np_txqlast = na->num_tx_rings + 1; - priv->np_rxqfirst = (reg == NR_REG_SW ? - na->num_rx_rings : 0); - priv->np_rxqlast = na->num_rx_rings + 1; + for_rx_tx(t) { + priv->np_qfirst[t] = (reg == NR_REG_SW ? + nma_get_nrings(na, t) : 0); + priv->np_qlast[t] = nma_get_nrings(na, t) + 1; + } ND("%s %d %d", reg == NR_REG_SW ? "SW" : "NIC+SW", - priv->np_rxqfirst, priv->np_rxqlast); + priv->np_qfirst[NR_RX], priv->np_qlast[NR_RX]); break; case NR_REG_ONE_NIC: if (i >= na->num_tx_rings && i >= na->num_rx_rings) { D("invalid ring id %d", i); return EINVAL; } - /* if not enough rings, use the first one */ - j = i; - if (j >= na->num_tx_rings) - j = 0; - priv->np_txqfirst = j; - priv->np_txqlast = j + 1; - j = i; - if (j >= na->num_rx_rings) - j = 0; - priv->np_rxqfirst = j; - priv->np_rxqlast = j + 1; + for_rx_tx(t) { + /* if not enough rings, use the first one */ + j = i; + if (j >= nma_get_nrings(na, t)) + j = 0; + priv->np_qfirst[t] = j; + priv->np_qlast[t] = j + 1; + } break; default: D("invalid regif type %d", reg); @@ -1818,10 +1720,10 @@ netmap_interp_ringid(struct netmap_priv_d *priv, uint16_t ringid, uint32_t flags if (netmap_verbose) { D("%s: tx [%d,%d) rx [%d,%d) id %d", na->name, - priv->np_txqfirst, - priv->np_txqlast, - priv->np_rxqfirst, - priv->np_rxqlast, + priv->np_qfirst[NR_TX], + priv->np_qlast[NR_TX], + priv->np_qfirst[NR_RX], + priv->np_qlast[NR_RX], i); } return 0; @@ -1837,6 +1739,7 @@ netmap_set_ringid(struct netmap_priv_d *priv, uint16_t ringid, uint32_t flags) { struct netmap_adapter *na = priv->np_na; int error; + enum txrx t; error = netmap_interp_ringid(priv, ringid, flags); if (error) { @@ -1850,13 +1753,109 @@ netmap_set_ringid(struct netmap_priv_d *priv, uint16_t ringid, uint32_t flags) * The default netmap_notify() callback will then * avoid signaling the global queue if nobody is using it */ - if (nm_tx_si_user(priv)) - na->tx_si_users++; - if (nm_rx_si_user(priv)) - na->rx_si_users++; + for_rx_tx(t) { + if (nm_si_user(priv, t)) + na->si_users[t]++; + } return 0; } +static void +netmap_unset_ringid(struct netmap_priv_d *priv) +{ + struct netmap_adapter *na = priv->np_na; + enum txrx t; + + for_rx_tx(t) { + if (nm_si_user(priv, t)) + na->si_users[t]--; + priv->np_qfirst[t] = priv->np_qlast[t] = 0; + } + priv->np_flags = 0; + priv->np_txpoll = 0; +} + + +/* check that the rings we want to bind are not exclusively owned by a previous + * bind. If exclusive ownership has been requested, we also mark the rings. + */ +static int +netmap_get_exclusive(struct netmap_priv_d *priv) +{ + struct netmap_adapter *na = priv->np_na; + u_int i; + struct netmap_kring *kring; + int excl = (priv->np_flags & NR_EXCLUSIVE); + enum txrx t; + + ND("%s: grabbing tx [%d, %d) rx [%d, %d)", + na->name, + priv->np_qfirst[NR_TX], + priv->np_qlast[NR_TX], + priv->np_qfirst[NR_RX], + priv->np_qlast[NR_RX]); + + /* first round: check that all the requested rings + * are neither alread exclusively owned, nor we + * want exclusive ownership when they are already in use + */ + for_rx_tx(t) { + for (i = priv->np_qfirst[t]; i < priv->np_qlast[t]; i++) { + kring = &NMR(na, t)[i]; + if ((kring->nr_kflags & NKR_EXCLUSIVE) || + (kring->users && excl)) + { + ND("ring %s busy", kring->name); + return EBUSY; + } + } + } + + /* second round: increment usage cound and possibly + * mark as exclusive + */ + + for_rx_tx(t) { + for (i = priv->np_qfirst[t]; i < priv->np_qlast[t]; i++) { + kring = &NMR(na, t)[i]; + kring->users++; + if (excl) + kring->nr_kflags |= NKR_EXCLUSIVE; + } + } + + return 0; + +} + +/* undo netmap_get_ownership() */ +static void +netmap_rel_exclusive(struct netmap_priv_d *priv) +{ + struct netmap_adapter *na = priv->np_na; + u_int i; + struct netmap_kring *kring; + int excl = (priv->np_flags & NR_EXCLUSIVE); + enum txrx t; + + ND("%s: releasing tx [%d, %d) rx [%d, %d)", + na->name, + priv->np_qfirst[NR_TX], + priv->np_qlast[NR_TX], + priv->np_qfirst[NR_RX], + priv->np_qlast[MR_RX]); + + + for_rx_tx(t) { + for (i = priv->np_qfirst[t]; i < priv->np_qlast[t]; i++) { + kring = &NMR(na, t)[i]; + if (excl) + kring->nr_kflags &= ~NKR_EXCLUSIVE; + kring->users--; + } + } +} + /* * possibly move the interface to netmap-mode. * If success it returns a pointer to netmap_if, otherwise NULL. @@ -1871,9 +1870,8 @@ netmap_set_ringid(struct netmap_priv_d *priv, uint16_t ringid, uint32_t flags) * The bwrap has to override this, since it has to forward * the request to the wrapped adapter (netmap_bwrap_config). * - * XXX netmap_if_new calls this again (2014-03-15) * - * na->nm_krings_create() [by netmap_if_new] + * na->nm_krings_create() * (create and init the krings array) * * One of the following: @@ -1927,15 +1925,14 @@ netmap_set_ringid(struct netmap_priv_d *priv, uint16_t ringid, uint32_t flags) * the hwna notify callback (to get the frames * coming from outside go through the bridge). * - * XXX maybe netmap_if_new() should be merged with this (2014-03-15). * */ -struct netmap_if * +int netmap_do_regif(struct netmap_priv_d *priv, struct netmap_adapter *na, - uint16_t ringid, uint32_t flags, int *err) + uint16_t ringid, uint32_t flags) { struct netmap_if *nifp = NULL; - int error, need_mem = 0; + int error; NMG_LOCK_ASSERT(); /* ring configuration may have changed, fetch from the card */ @@ -1943,57 +1940,121 @@ netmap_do_regif(struct netmap_priv_d *priv, struct netmap_adapter *na, priv->np_na = na; /* store the reference */ error = netmap_set_ringid(priv, ringid, flags); if (error) - goto out; - /* ensure allocators are ready */ - need_mem = !netmap_have_memory_locked(priv); - if (need_mem) { - error = netmap_get_memory_locked(priv); - ND("get_memory returned %d", error); + goto err; + error = netmap_mem_finalize(na->nm_mem, na); + if (error) + goto err; + + if (na->active_fds == 0) { + /* + * If this is the first registration of the adapter, + * also create the netmap rings and their in-kernel view, + * the netmap krings. + */ + + /* + * Depending on the adapter, this may also create + * the netmap rings themselves + */ + error = na->nm_krings_create(na); if (error) - goto out; + goto err_drop_mem; + + /* create all missing netmap rings */ + error = netmap_mem_rings_create(na); + if (error) + goto err_del_krings; } - /* Allocate a netmap_if and, if necessary, all the netmap_ring's */ - nifp = netmap_if_new(na); - if (nifp == NULL) { /* allocation failed */ + + /* now the kring must exist and we can check whether some + * previous bind has exclusive ownership on them + */ + error = netmap_get_exclusive(priv); + if (error) + goto err_del_rings; + + /* in all cases, create a new netmap if */ + nifp = netmap_mem_if_new(na); + if (nifp == NULL) { error = ENOMEM; - goto out; + goto err_rel_excl; } + na->active_fds++; if (!nm_netmap_on(na)) { /* Netmap not active, set the card in netmap mode * and make it use the shared buffers. */ /* cache the allocator info in the na */ - na->na_lut = netmap_mem_get_lut(na->nm_mem); - ND("%p->na_lut == %p", na, na->na_lut); - na->na_lut_objtotal = netmap_mem_get_buftotal(na->nm_mem); - na->na_lut_objsize = netmap_mem_get_bufsize(na->nm_mem); + netmap_mem_get_lut(na->nm_mem, &na->na_lut); + ND("%p->na_lut == %p", na, na->na_lut.lut); error = na->nm_register(na, 1); /* mode on */ - if (error) { - netmap_do_unregif(priv, nifp); - nifp = NULL; - } + if (error) + goto err_del_if; } -out: - *err = error; - if (error) { - /* we should drop the allocator, but only - * if we were the ones who grabbed it - */ - if (need_mem) - netmap_drop_memory_locked(priv); - priv->np_na = NULL; - } - if (nifp != NULL) { - /* - * advertise that the interface is ready bt setting ni_nifp. - * The barrier is needed because readers (poll and *SYNC) - * check for priv->np_nifp != NULL without locking - */ - wmb(); /* make sure previous writes are visible to all CPUs */ - priv->np_nifp = nifp; - } - return nifp; + + /* + * advertise that the interface is ready by setting np_nifp. + * The barrier is needed because readers (poll, *SYNC and mmap) + * check for priv->np_nifp != NULL without locking + */ + mb(); /* make sure previous writes are visible to all CPUs */ + priv->np_nifp = nifp; + + return 0; + +err_del_if: + memset(&na->na_lut, 0, sizeof(na->na_lut)); + na->active_fds--; + netmap_mem_if_delete(na, nifp); +err_rel_excl: + netmap_rel_exclusive(priv); +err_del_rings: + if (na->active_fds == 0) + netmap_mem_rings_delete(na); +err_del_krings: + if (na->active_fds == 0) + na->nm_krings_delete(na); +err_drop_mem: + netmap_mem_deref(na->nm_mem, na); +err: + priv->np_na = NULL; + return error; +} + + +/* + * update kring and ring at the end of txsync. + */ +static inline void +nm_txsync_finalize(struct netmap_kring *kring) +{ + /* update ring tail to what the kernel knows */ + kring->ring->tail = kring->rtail = kring->nr_hwtail; + + /* note, head/rhead/hwcur might be behind cur/rcur + * if no carrier + */ + ND(5, "%s now hwcur %d hwtail %d head %d cur %d tail %d", + kring->name, kring->nr_hwcur, kring->nr_hwtail, + kring->rhead, kring->rcur, kring->rtail); +} + + +/* + * update kring and ring at the end of rxsync + */ +static inline void +nm_rxsync_finalize(struct netmap_kring *kring) +{ + /* tell userspace that there might be new packets */ + //struct netmap_ring *ring = kring->ring; + ND("head %d cur %d tail %d -> %d", ring->head, ring->cur, ring->tail, + kring->nr_hwtail); + kring->ring->tail = kring->rtail = kring->nr_hwtail; + /* make a copy of the state for next round */ + kring->rhead = kring->ring->head; + kring->rcur = kring->ring->cur; } @@ -2021,6 +2082,7 @@ netmap_ioctl(struct cdev *dev, u_long cmd, caddr_t data, u_int i, qfirst, qlast; struct netmap_if *nifp; struct netmap_kring *krings; + enum txrx t; (void)dev; /* UNUSED */ (void)fflag; /* UNUSED */ @@ -2108,7 +2170,7 @@ netmap_ioctl(struct cdev *dev, u_long cmd, caddr_t data, do { u_int memflags; - if (priv->np_na != NULL) { /* thread already registered */ + if (priv->np_nifp != NULL) { /* thread already registered */ error = EBUSY; break; } @@ -2121,12 +2183,12 @@ netmap_ioctl(struct cdev *dev, u_long cmd, caddr_t data, error = EBUSY; break; } - nifp = netmap_do_regif(priv, na, nmr->nr_ringid, nmr->nr_flags, &error); - if (!nifp) { /* reg. failed, release priv and ref */ + error = netmap_do_regif(priv, na, nmr->nr_ringid, nmr->nr_flags); + if (error) { /* reg. failed, release priv and ref */ netmap_adapter_put(na); - priv->np_nifp = NULL; break; } + nifp = priv->np_nifp; priv->np_td = td; // XXX kqueue, debugging only /* return the offset of the netmap_if object */ @@ -2137,16 +2199,17 @@ netmap_ioctl(struct cdev *dev, u_long cmd, caddr_t data, error = netmap_mem_get_info(na->nm_mem, &nmr->nr_memsize, &memflags, &nmr->nr_arg2); if (error) { + netmap_do_unregif(priv); netmap_adapter_put(na); break; } if (memflags & NETMAP_MEM_PRIVATE) { *(uint32_t *)(uintptr_t)&nifp->ni_flags |= NI_PRIV_MEM; } - priv->np_txsi = (priv->np_txqlast - priv->np_txqfirst > 1) ? - &na->tx_si : &na->tx_rings[priv->np_txqfirst].si; - priv->np_rxsi = (priv->np_rxqlast - priv->np_rxqfirst > 1) ? - &na->rx_si : &na->rx_rings[priv->np_rxqfirst].si; + for_rx_tx(t) { + priv->np_si[t] = nm_si_user(priv, t) ? + &na->si[t] : &NMR(na, t)[priv->np_qfirst[t]].si; + } if (nmr->nr_arg3) { D("requested %d extra buffers", nmr->nr_arg3); @@ -2182,15 +2245,10 @@ netmap_ioctl(struct cdev *dev, u_long cmd, caddr_t data, break; } - if (cmd == NIOCTXSYNC) { - krings = na->tx_rings; - qfirst = priv->np_txqfirst; - qlast = priv->np_txqlast; - } else { - krings = na->rx_rings; - qfirst = priv->np_rxqfirst; - qlast = priv->np_rxqlast; - } + t = (cmd == NIOCTXSYNC ? NR_TX : NR_RX); + krings = NMR(na, t); + qfirst = priv->np_qfirst[t]; + qlast = priv->np_qlast[t]; for (i = qfirst; i < qlast; i++) { struct netmap_kring *kring = krings + i; @@ -2205,15 +2263,19 @@ netmap_ioctl(struct cdev *dev, u_long cmd, caddr_t data, kring->nr_hwcur); if (nm_txsync_prologue(kring) >= kring->nkr_num_slots) { netmap_ring_reinit(kring); - } else { - kring->nm_sync(kring, NAF_FORCE_RECLAIM); + } else if (kring->nm_sync(kring, NAF_FORCE_RECLAIM) == 0) { + nm_txsync_finalize(kring); } if (netmap_verbose & NM_VERB_TXSYNC) D("post txsync ring %d cur %d hwcur %d", i, kring->ring->cur, kring->nr_hwcur); } else { - kring->nm_sync(kring, NAF_FORCE_READ); + if (nm_rxsync_prologue(kring) >= kring->nkr_num_slots) { + netmap_ring_reinit(kring); + } else if (kring->nm_sync(kring, NAF_FORCE_READ) == 0) { + nm_rxsync_finalize(kring); + } microtime(&na->rx_rings[i].ring->ts); } nm_kr_put(kring); @@ -2221,9 +2283,11 @@ netmap_ioctl(struct cdev *dev, u_long cmd, caddr_t data, break; +#ifdef WITH_VALE case NIOCCONFIG: error = netmap_bdg_config(nmr); break; +#endif #ifdef __FreeBSD__ case FIONBIO: case FIOASYNC: @@ -2286,10 +2350,13 @@ netmap_poll(struct cdev *dev, int events, struct thread *td) struct netmap_priv_d *priv = NULL; struct netmap_adapter *na; struct netmap_kring *kring; - u_int i, check_all_tx, check_all_rx, want_tx, want_rx, revents = 0; + u_int i, check_all_tx, check_all_rx, want[NR_TXRX], revents = 0; +#define want_tx want[NR_TX] +#define want_rx want[NR_RX] struct mbq q; /* packets from hw queues to host stack */ void *pwait = dev; /* linux compatibility */ int is_kevent = 0; + enum txrx t; /* * In order to avoid nested locks, we need to "double check" @@ -2320,7 +2387,7 @@ netmap_poll(struct cdev *dev, int events, struct thread *td) D("No if registered"); return POLLERR; } - rmb(); /* make sure following reads are not from cache */ + mb(); /* make sure following reads are not from cache */ na = priv->np_na; @@ -2346,28 +2413,22 @@ netmap_poll(struct cdev *dev, int events, struct thread *td) * there are pending packets to send. The latter can be disabled * passing NETMAP_NO_TX_POLL in the NIOCREG call. */ - check_all_tx = nm_tx_si_user(priv); - check_all_rx = nm_rx_si_user(priv); + check_all_tx = nm_si_user(priv, NR_TX); + check_all_rx = nm_si_user(priv, NR_RX); /* * We start with a lock free round which is cheap if we have * slots available. If this fails, then lock and call the sync * routines. */ - for (i = priv->np_rxqfirst; want_rx && i < priv->np_rxqlast; i++) { - kring = &na->rx_rings[i]; - /* XXX compare ring->cur and kring->tail */ - if (!nm_ring_empty(kring->ring)) { - revents |= want_rx; - want_rx = 0; /* also breaks the loop */ - } - } - for (i = priv->np_txqfirst; want_tx && i < priv->np_txqlast; i++) { - kring = &na->tx_rings[i]; - /* XXX compare ring->cur and kring->tail */ - if (!nm_ring_empty(kring->ring)) { - revents |= want_tx; - want_tx = 0; /* also breaks the loop */ + for_rx_tx(t) { + for (i = priv->np_qfirst[t]; want[t] && i < priv->np_qlast[t]; i++) { + kring = &NMR(na, t)[i]; + /* XXX compare ring->cur and kring->tail */ + if (!nm_ring_empty(kring->ring)) { + revents |= want[t]; + want[t] = 0; /* also breaks the loop */ + } } } @@ -2386,7 +2447,7 @@ netmap_poll(struct cdev *dev, int events, struct thread *td) * used to skip rings with no pending transmissions. */ flush_tx: - for (i = priv->np_txqfirst; i < priv->np_txqlast; i++) { + for (i = priv->np_qfirst[NR_TX]; i < priv->np_qlast[NR_RX]; i++) { int found = 0; kring = &na->tx_rings[i]; @@ -2410,6 +2471,8 @@ flush_tx: } else { if (kring->nm_sync(kring, 0)) revents |= POLLERR; + else + nm_txsync_finalize(kring); } /* @@ -2423,12 +2486,12 @@ flush_tx: if (found) { /* notify other listeners */ revents |= want_tx; want_tx = 0; - na->nm_notify(na, i, NR_TX, 0); + kring->nm_notify(kring, 0); } } if (want_tx && retry_tx && !is_kevent) { OS_selrecord(td, check_all_tx ? - &na->tx_si : &na->tx_rings[priv->np_txqfirst].si); + &na->si[NR_TX] : &na->tx_rings[priv->np_qfirst[NR_TX]].si); retry_tx = 0; goto flush_tx; } @@ -2442,7 +2505,7 @@ flush_tx: int send_down = 0; /* transparent mode */ /* two rounds here for race avoidance */ do_retry_rx: - for (i = priv->np_rxqfirst; i < priv->np_rxqlast; i++) { + for (i = priv->np_qfirst[NR_RX]; i < priv->np_qlast[NR_RX]; i++) { int found = 0; kring = &na->rx_rings[i]; @@ -2454,6 +2517,12 @@ do_retry_rx: continue; } + if (nm_rxsync_prologue(kring) >= kring->nkr_num_slots) { + netmap_ring_reinit(kring); + revents |= POLLERR; + } + /* now we can use kring->rcur, rtail */ + /* * transparent mode support: collect packets * from the rxring(s). @@ -2468,17 +2537,18 @@ do_retry_rx: if (kring->nm_sync(kring, 0)) revents |= POLLERR; + else + nm_rxsync_finalize(kring); if (netmap_no_timestamp == 0 || kring->ring->flags & NR_TIMESTAMP) { microtime(&kring->ring->ts); } - /* after an rxsync we can use kring->rcur, rtail */ found = kring->rcur != kring->rtail; nm_kr_put(kring); if (found) { revents |= want_rx; retry_rx = 0; - na->nm_notify(na, i, NR_RX, 0); + kring->nm_notify(kring, 0); } } @@ -2497,7 +2567,7 @@ do_retry_rx: if (retry_rx && !is_kevent) OS_selrecord(td, check_all_rx ? - &na->rx_si : &na->rx_rings[priv->np_rxqfirst].si); + &na->si[NR_RX] : &na->rx_rings[priv->np_qfirst[NR_RX]].si); if (send_down > 0 || retry_rx) { retry_rx = 0; if (send_down) @@ -2523,6 +2593,8 @@ do_retry_rx: netmap_send_up(na->ifp, &q); return (revents); +#undef want_tx +#undef want_rx } @@ -2532,27 +2604,19 @@ static int netmap_hw_krings_create(struct netmap_adapter *); /* default notify callback */ static int -netmap_notify(struct netmap_adapter *na, u_int n_ring, - enum txrx tx, int flags) +netmap_notify(struct netmap_kring *kring, int flags) { - struct netmap_kring *kring; + struct netmap_adapter *na = kring->na; + enum txrx t = kring->tx; + + OS_selwakeup(&kring->si, PI_NET); + /* optimization: avoid a wake up on the global + * queue if nobody has registered for more + * than one ring + */ + if (na->si_users[t] > 0) + OS_selwakeup(&na->si[t], PI_NET); - if (tx == NR_TX) { - kring = na->tx_rings + n_ring; - OS_selwakeup(&kring->si, PI_NET); - /* optimization: avoid a wake up on the global - * queue if nobody has registered for more - * than one ring - */ - if (na->tx_si_users > 0) - OS_selwakeup(&na->tx_si, PI_NET); - } else { - kring = na->rx_rings + n_ring; - OS_selwakeup(&kring->si, PI_NET); - /* optimization: same as above */ - if (na->rx_si_users > 0) - OS_selwakeup(&na->rx_si, PI_NET); - } return 0; } @@ -2605,11 +2669,14 @@ netmap_attach_common(struct netmap_adapter *na) if (na->nm_mem == NULL) /* use the global allocator */ na->nm_mem = &nm_mem; + netmap_mem_get(na->nm_mem); +#ifdef WITH_VALE if (na->nm_bdg_attach == NULL) /* no special nm_bdg_attach callback. On VALE * attach, we need to interpose a bwrap */ na->nm_bdg_attach = netmap_bwrap_attach; +#endif return 0; } @@ -2626,8 +2693,8 @@ netmap_detach_common(struct netmap_adapter *na) na->nm_krings_delete(na); } netmap_pipe_dealloc(na); - if (na->na_flags & NAF_MEM_OWNER) - netmap_mem_private_delete(na->nm_mem); + if (na->nm_mem) + netmap_mem_put(na->nm_mem); bzero(na, sizeof(*na)); free(na, M_DEVBUF); } @@ -2678,7 +2745,7 @@ netmap_attach(struct netmap_adapter *arg) if (hwna == NULL) goto fail; hwna->up = *arg; - hwna->up.na_flags |= NAF_HOST_RINGS; + hwna->up.na_flags |= NAF_HOST_RINGS | NAF_NATIVE; strncpy(hwna->up.name, ifp->if_xname, sizeof(hwna->up.name)); hwna->nm_hw_register = hwna->up.nm_register; hwna->up.nm_register = netmap_hw_register; @@ -2691,7 +2758,7 @@ netmap_attach(struct netmap_adapter *arg) #ifdef linux if (ifp->netdev_ops) { /* prepare a clone of the netdev ops */ -#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 28) +#ifndef NETMAP_LINUX_HAVE_NETDEV_OPS hwna->nm_ndo.ndo_start_xmit = ifp->netdev_ops; #else hwna->nm_ndo = *ifp->netdev_ops; @@ -2702,7 +2769,7 @@ netmap_attach(struct netmap_adapter *arg) hwna->nm_eto = *ifp->ethtool_ops; } hwna->nm_eto.set_ringparam = linux_netmap_set_ringparam; -#ifdef ETHTOOL_SCHANNELS +#ifdef NETMAP_LINUX_HAVE_SET_CHANNELS hwna->nm_eto.set_channels = linux_netmap_set_channels; #endif if (arg->nm_config == NULL) { @@ -2710,17 +2777,9 @@ netmap_attach(struct netmap_adapter *arg) } #endif /* linux */ -#ifdef __FreeBSD__ if_printf(ifp, "netmap queues/slots: TX %d/%d, RX %d/%d\n", hwna->up.num_tx_rings, hwna->up.num_tx_desc, hwna->up.num_rx_rings, hwna->up.num_rx_desc); -#else - D("success for %s tx %d/%d rx %d/%d queues/slots", - hwna->up.name, - hwna->up.num_tx_rings, hwna->up.num_tx_desc, - hwna->up.num_rx_rings, hwna->up.num_rx_desc - ); -#endif return 0; fail: @@ -2788,16 +2847,19 @@ netmap_detach(struct ifnet *ifp) NMG_LOCK(); netmap_disable_all_rings(ifp); - if (!netmap_adapter_put(na)) { - /* someone is still using the adapter, - * tell them that the interface is gone - */ - na->ifp = NULL; - // XXX also clear NAF_NATIVE_ON ? - na->na_flags &= ~NAF_NETMAP_ON; - /* give them a chance to notice */ - netmap_enable_all_rings(ifp); + na->ifp = NULL; + na->na_flags &= ~NAF_NETMAP_ON; + /* + * if the netmap adapter is not native, somebody + * changed it, so we can not release it here. + * The NULL na->ifp will notify the new owner that + * the driver is gone. + */ + if (na->na_flags & NAF_NATIVE) { + netmap_adapter_put(na); } + /* give them a chance to notice */ + netmap_enable_all_rings(ifp); NMG_UNLOCK(); } @@ -2824,6 +2886,7 @@ netmap_transmit(struct ifnet *ifp, struct mbuf *m) struct mbq *q; int space; + kring = &na->rx_rings[na->num_rx_rings]; // XXX [Linux] we do not need this lock // if we follow the down/configure/up protocol -gl // mtx_lock(&na->core_lock); @@ -2834,7 +2897,6 @@ netmap_transmit(struct ifnet *ifp, struct mbuf *m) goto done; } - kring = &na->rx_rings[na->num_rx_rings]; q = &kring->rx_queue; // XXX reconsider long packets if we handle fragments @@ -2872,7 +2934,7 @@ done: if (m) m_freem(m); /* unconditionally wake up listeners */ - na->nm_notify(na, na->num_rx_rings, NR_RX, 0); + kring->nm_notify(kring, 0); /* this is normally netmap_notify(), but for nics * connected to a bridge it is netmap_bwrap_intr_notify(), * that possibly forwards the frames through the switch @@ -2953,7 +3015,7 @@ netmap_reset(struct netmap_adapter *na, enum txrx tx, u_int n, * We do the wakeup here, but the ring is not yet reconfigured. * However, we are under lock so there are no races. */ - na->nm_notify(na, n, tx, 0); + kring->nm_notify(kring, 0); return kring->ring->slot; } @@ -2977,6 +3039,7 @@ netmap_common_irq(struct ifnet *ifp, u_int q, u_int *work_done) { struct netmap_adapter *na = NA(ifp); struct netmap_kring *kring; + enum txrx t = (work_done ? NR_RX : NR_TX); q &= NETMAP_RING_MASK; @@ -2984,19 +3047,16 @@ netmap_common_irq(struct ifnet *ifp, u_int q, u_int *work_done) RD(5, "received %s queue %d", work_done ? "RX" : "TX" , q); } - if (work_done) { /* RX path */ - if (q >= na->num_rx_rings) - return; // not a physical queue - kring = na->rx_rings + q; + if (q >= nma_get_nrings(na, t)) + return; // not a physical queue + + kring = NMR(na, t) + q; + + if (t == NR_RX) { kring->nr_kflags |= NKR_PENDINTR; // XXX atomic ? - na->nm_notify(na, q, NR_RX, 0); *work_done = 1; /* do not fire napi again */ - } else { /* TX path */ - if (q >= na->num_tx_rings) - return; // not a physical queue - kring = na->tx_rings + q; - na->nm_notify(na, q, NR_TX, 0); } + kring->nm_notify(kring, 0); } @@ -3057,7 +3117,7 @@ extern struct cdevsw netmap_cdevsw; void netmap_fini(void) { - // XXX destroy_bridges() ? + netmap_uninit_bridges(); if (netmap_dev) destroy_dev(netmap_dev); netmap_mem_fini(); @@ -3087,10 +3147,14 @@ netmap_init(void) if (!netmap_dev) goto fail; - netmap_init_bridges(); + error = netmap_init_bridges(); + if (error) + goto fail; + #ifdef __FreeBSD__ nm_vi_init_index(); #endif + printf("netmap: loaded module\n"); return (0); fail: diff --git a/sys/dev/netmap/netmap_freebsd.c b/sys/dev/netmap/netmap_freebsd.c index 968724854ea6..8490ae85670b 100644 --- a/sys/dev/netmap/netmap_freebsd.c +++ b/sys/dev/netmap/netmap_freebsd.c @@ -24,6 +24,8 @@ */ /* $FreeBSD$ */ +#include "opt_inet.h" +#include "opt_inet6.h" #include #include @@ -148,9 +150,9 @@ nm_csum_tcpudp_ipv6(struct nm_ipv6hdr *ip6h, void *data, * Second argument is non-zero to intercept, 0 to restore */ int -netmap_catch_rx(struct netmap_adapter *na, int intercept) +netmap_catch_rx(struct netmap_generic_adapter *gna, int intercept) { - struct netmap_generic_adapter *gna = (struct netmap_generic_adapter *)na; + struct netmap_adapter *na = &gna->up.up; struct ifnet *ifp = na->ifp; if (intercept) { @@ -183,7 +185,7 @@ void netmap_catch_tx(struct netmap_generic_adapter *gna, int enable) { struct netmap_adapter *na = &gna->up.up; - struct ifnet *ifp = na->ifp; + struct ifnet *ifp = netmap_generic_getifp(gna); if (enable) { na->if_transmit = ifp->if_transmit; @@ -494,6 +496,7 @@ netmap_dev_pager_fault(vm_object_t object, vm_ooffset_t offset, { struct netmap_vm_handle_t *vmh = object->handle; struct netmap_priv_d *priv = vmh->priv; + struct netmap_adapter *na = priv->np_na; vm_paddr_t paddr; vm_page_t page; vm_memattr_t memattr; @@ -503,7 +506,7 @@ netmap_dev_pager_fault(vm_object_t object, vm_ooffset_t offset, object, (intmax_t)offset, prot, mres); memattr = object->memattr; pidx = OFF_TO_IDX(offset); - paddr = netmap_mem_ofstophys(priv->np_mref, offset); + paddr = netmap_mem_ofstophys(na->nm_mem, offset); if (paddr == 0) return VM_PAGER_FAIL; @@ -568,14 +571,14 @@ netmap_mmap_single(struct cdev *cdev, vm_ooffset_t *foff, error = devfs_get_cdevpriv((void**)&priv); if (error) goto err_unlock; + if (priv->np_nifp == NULL) { + error = EINVAL; + goto err_unlock; + } vmh->priv = priv; - priv->np_refcount++; + priv->np_refs++; NMG_UNLOCK(); - error = netmap_get_memory(priv); - if (error) - goto err_deref; - obj = cdev_pager_allocate(vmh, OBJT_DEVICE, &netmap_cdev_pager_ops, objsize, prot, *foff, NULL); @@ -590,7 +593,7 @@ netmap_mmap_single(struct cdev *cdev, vm_ooffset_t *foff, err_deref: NMG_LOCK(); - priv->np_refcount--; + priv->np_refs--; err_unlock: NMG_UNLOCK(); // err: @@ -598,8 +601,18 @@ err_unlock: return error; } - -// XXX can we remove this ? +/* + * On FreeBSD the close routine is only called on the last close on + * the device (/dev/netmap) so we cannot do anything useful. + * To track close() on individual file descriptors we pass netmap_dtor() to + * devfs_set_cdevpriv() on open(). The FreeBSD kernel will call the destructor + * when the last fd pointing to the device is closed. + * + * Note that FreeBSD does not even munmap() on close() so we also have + * to track mmap() ourselves, and postpone the call to + * netmap_dtor() is called when the process has no open fds and no active + * memory maps on /dev/netmap, as in linux. + */ static int netmap_close(struct cdev *dev, int fflag, int devtype, struct thread *td) { @@ -621,19 +634,20 @@ netmap_open(struct cdev *dev, int oflags, int devtype, struct thread *td) (void)devtype; (void)td; - // XXX wait or nowait ? priv = malloc(sizeof(struct netmap_priv_d), M_DEVBUF, M_NOWAIT | M_ZERO); if (priv == NULL) return ENOMEM; - + priv->np_refs = 1; error = devfs_set_cdevpriv(priv, netmap_dtor); - if (error) - return error; - - priv->np_refcount = 1; - - return 0; + if (error) { + free(priv, M_DEVBUF); + } else { + NMG_LOCK(); + netmap_use_count++; + NMG_UNLOCK(); + } + return error; } /******************** kqueue support ****************/ @@ -673,7 +687,7 @@ static void netmap_knrdetach(struct knote *kn) { struct netmap_priv_d *priv = (struct netmap_priv_d *)kn->kn_hook; - struct selinfo *si = &priv->np_rxsi->si; + struct selinfo *si = &priv->np_si[NR_RX]->si; D("remove selinfo %p", si); knlist_remove(&si->si_note, kn, 0); @@ -683,7 +697,7 @@ static void netmap_knwdetach(struct knote *kn) { struct netmap_priv_d *priv = (struct netmap_priv_d *)kn->kn_hook; - struct selinfo *si = &priv->np_txsi->si; + struct selinfo *si = &priv->np_si[NR_TX]->si; D("remove selinfo %p", si); knlist_remove(&si->si_note, kn, 0); @@ -773,7 +787,7 @@ netmap_kqfilter(struct cdev *dev, struct knote *kn) return 1; } /* the si is indicated in the priv */ - si = (ev == EVFILT_WRITE) ? priv->np_txsi : priv->np_rxsi; + si = priv->np_si[(ev == EVFILT_WRITE) ? NR_TX : NR_RX]; // XXX lock(priv) ? kn->kn_fop = (ev == EVFILT_WRITE) ? &netmap_wfiltops : &netmap_rfiltops; @@ -817,6 +831,16 @@ netmap_loader(__unused struct module *module, int event, __unused void *arg) break; case MOD_UNLOAD: + /* + * if some one is still using netmap, + * then the module can not be unloaded. + */ + if (netmap_use_count) { + D("netmap module can not be unloaded - netmap_use_count: %d", + netmap_use_count); + error = EBUSY; + break; + } netmap_fini(); break; diff --git a/sys/dev/netmap/netmap_generic.c b/sys/dev/netmap/netmap_generic.c index ecdb36824077..bc5b452cfaae 100644 --- a/sys/dev/netmap/netmap_generic.c +++ b/sys/dev/netmap/netmap_generic.c @@ -305,7 +305,7 @@ generic_netmap_register(struct netmap_adapter *na, int enable) } rtnl_lock(); /* Prepare to intercept incoming traffic. */ - error = netmap_catch_rx(na, 1); + error = netmap_catch_rx(gna, 1); if (error) { D("netdev_rx_handler_register() failed (%d)", error); goto register_handler; @@ -342,7 +342,7 @@ generic_netmap_register(struct netmap_adapter *na, int enable) netmap_catch_tx(gna, 0); /* Do not intercept packets on the rx path. */ - netmap_catch_rx(na, 0); + netmap_catch_rx(gna, 0); rtnl_unlock(); @@ -645,8 +645,6 @@ generic_netmap_txsync(struct netmap_kring *kring, int flags) generic_netmap_tx_clean(kring); - nm_txsync_finalize(kring); - return 0; } @@ -711,7 +709,7 @@ generic_netmap_rxsync(struct netmap_kring *kring, int flags) u_int nm_i; /* index into the netmap ring */ //j, u_int n; u_int const lim = kring->nkr_num_slots - 1; - u_int const head = nm_rxsync_prologue(kring); + u_int const head = kring->rhead; int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; if (head > lim) @@ -774,8 +772,6 @@ generic_netmap_rxsync(struct netmap_kring *kring, int flags) } kring->nr_hwcur = head; } - /* tell userspace that there might be new packets. */ - nm_rxsync_finalize(kring); IFRATE(rate_ctx.new.rxsync++); return 0; @@ -784,20 +780,25 @@ generic_netmap_rxsync(struct netmap_kring *kring, int flags) static void generic_netmap_dtor(struct netmap_adapter *na) { - struct ifnet *ifp = na->ifp; struct netmap_generic_adapter *gna = (struct netmap_generic_adapter*)na; + struct ifnet *ifp = netmap_generic_getifp(gna); struct netmap_adapter *prev_na = gna->prev; if (prev_na != NULL) { D("Released generic NA %p", gna); - if_rele(na->ifp); + if_rele(ifp); netmap_adapter_put(prev_na); + if (na->ifp == NULL) { + /* + * The driver has been removed without releasing + * the reference so we need to do it here. + */ + netmap_adapter_put(prev_na); + } } - if (ifp != NULL) { - WNA(ifp) = prev_na; - D("Restored native NA %p", prev_na); - na->ifp = NULL; - } + WNA(ifp) = prev_na; + D("Restored native NA %p", prev_na); + na->ifp = NULL; } /* @@ -834,6 +835,7 @@ generic_netmap_attach(struct ifnet *ifp) return ENOMEM; } na = (struct netmap_adapter *)gna; + strncpy(na->name, ifp->if_xname, sizeof(na->name)); na->ifp = ifp; na->num_tx_desc = num_tx_desc; na->num_rx_desc = num_rx_desc; diff --git a/sys/dev/netmap/netmap_kern.h b/sys/dev/netmap/netmap_kern.h index 95b3a5deda69..d38b3b242da9 100644 --- a/sys/dev/netmap/netmap_kern.h +++ b/sys/dev/netmap/netmap_kern.h @@ -34,26 +34,46 @@ #ifndef _NET_NETMAP_KERN_H_ #define _NET_NETMAP_KERN_H_ +#if defined(linux) + +#if defined(CONFIG_NETMAP_VALE) +#define WITH_VALE +#endif +#if defined(CONFIG_NETMAP_PIPE) +#define WITH_PIPES +#endif +#if defined(CONFIG_NETMAP_MONITOR) +#define WITH_MONITOR +#endif +#if defined(CONFIG_NETMAP_GENERIC) +#define WITH_GENERIC +#endif +#if defined(CONFIG_NETMAP_V1000) +#define WITH_V1000 +#endif + +#else /* not linux */ + #define WITH_VALE // comment out to disable VALE support #define WITH_PIPES #define WITH_MONITOR #define WITH_GENERIC +#endif + #if defined(__FreeBSD__) #define likely(x) __builtin_expect((long)!!(x), 1L) #define unlikely(x) __builtin_expect((long)!!(x), 0L) -#define NM_LOCK_T struct mtx +#define NM_LOCK_T struct mtx /* low level spinlock, used to protect queues */ -/* netmap global lock */ -#define NMG_LOCK_T struct sx -#define NMG_LOCK_INIT() sx_init(&netmap_global_lock, \ - "netmap global lock") -#define NMG_LOCK_DESTROY() sx_destroy(&netmap_global_lock) -#define NMG_LOCK() sx_xlock(&netmap_global_lock) -#define NMG_UNLOCK() sx_xunlock(&netmap_global_lock) -#define NMG_LOCK_ASSERT() sx_assert(&netmap_global_lock, SA_XLOCKED) +#define NM_MTX_T struct sx /* OS-specific mutex (sleepable) */ +#define NM_MTX_INIT(m) sx_init(&(m), #m) +#define NM_MTX_DESTROY(m) sx_destroy(&(m)) +#define NM_MTX_LOCK(m) sx_xlock(&(m)) +#define NM_MTX_UNLOCK(m) sx_xunlock(&(m)) +#define NM_MTX_ASSERT(m) sx_assert(&(m), SA_XLOCKED) #define NM_SELINFO_T struct nm_selinfo #define MBUF_LEN(m) ((m)->m_pkthdr.len) @@ -102,6 +122,8 @@ struct ethtool_ops { }; struct hrtimer { }; +#define NM_BNS_GET(b) +#define NM_BNS_PUT(b) #elif defined (linux) @@ -117,20 +139,12 @@ struct hrtimer { #define NM_ATOMIC_T volatile long unsigned int -#define NM_MTX_T struct mutex -#define NM_MTX_INIT(m, s) do { (void)s; mutex_init(&(m)); } while (0) -#define NM_MTX_DESTROY(m) do { (void)m; } while (0) +#define NM_MTX_T struct mutex /* OS-specific sleepable lock */ +#define NM_MTX_INIT(m) mutex_init(&(m)) +#define NM_MTX_DESTROY(m) do { (void)(m); } while (0) #define NM_MTX_LOCK(m) mutex_lock(&(m)) #define NM_MTX_UNLOCK(m) mutex_unlock(&(m)) -#define NM_MTX_LOCK_ASSERT(m) mutex_is_locked(&(m)) - -#define NMG_LOCK_T NM_MTX_T -#define NMG_LOCK_INIT() NM_MTX_INIT(netmap_global_lock, \ - "netmap_global_lock") -#define NMG_LOCK_DESTROY() NM_MTX_DESTROY(netmap_global_lock) -#define NMG_LOCK() NM_MTX_LOCK(netmap_global_lock) -#define NMG_UNLOCK() NM_MTX_UNLOCK(netmap_global_lock) -#define NMG_LOCK_ASSERT() NM_MTX_LOCK_ASSERT(netmap_global_lock) +#define NM_MTX_ASSERT(m) mutex_is_locked(&(m)) #ifndef DEV_NETMAP #define DEV_NETMAP @@ -152,6 +166,13 @@ struct hrtimer { #endif /* end - platform-specific code */ +#define NMG_LOCK_T NM_MTX_T +#define NMG_LOCK_INIT() NM_MTX_INIT(netmap_global_lock) +#define NMG_LOCK_DESTROY() NM_MTX_DESTROY(netmap_global_lock) +#define NMG_LOCK() NM_MTX_LOCK(netmap_global_lock) +#define NMG_UNLOCK() NM_MTX_UNLOCK(netmap_global_lock) +#define NMG_LOCK_ASSERT() NM_MTX_ASSERT(netmap_global_lock) + #define ND(format, ...) #define D(format, ...) \ do { \ @@ -185,6 +206,23 @@ const char *nm_dump_buf(char *p, int len, int lim, char *dst); extern NMG_LOCK_T netmap_global_lock; +enum txrx { NR_RX = 0, NR_TX = 1, NR_TXRX }; + +static __inline const char* +nm_txrx2str(enum txrx t) +{ + return (t== NR_RX ? "RX" : "TX"); +} + +static __inline enum txrx +nm_txrx_swap(enum txrx t) +{ + return (t== NR_RX ? NR_TX : NR_RX); +} + +#define for_rx_tx(t) for ((t) = 0; (t) < NR_TXRX; (t)++) + + /* * private, kernel view of a ring. Keeps track of the status of * a ring across system calls. @@ -259,6 +297,7 @@ struct netmap_kring { uint32_t nr_kflags; /* private driver flags */ #define NKR_PENDINTR 0x1 // Pending interrupt. +#define NKR_EXCLUSIVE 0x2 /* exclusive binding */ uint32_t nkr_num_slots; /* @@ -308,7 +347,10 @@ struct netmap_kring { // u_int nr_ntc; /* Emulation of a next-to-clean RX ring pointer. */ struct mbq rx_queue; /* intercepted rx mbufs. */ + uint32_t users; /* existing bindings for this ring */ + uint32_t ring_id; /* debugging */ + enum txrx tx; /* kind of ring (tx or rx) */ char name[64]; /* diagnostic */ /* [tx]sync callback for this kring. @@ -323,6 +365,7 @@ struct netmap_kring { * any of the nm_krings_create callbacks. */ int (*nm_sync)(struct netmap_kring *kring, int flags); + int (*nm_notify)(struct netmap_kring *kring, int flags); #ifdef WITH_PIPES struct netmap_kring *pipe; /* if this is a pipe ring, @@ -333,17 +376,25 @@ struct netmap_kring { */ #endif /* WITH_PIPES */ +#ifdef WITH_VALE + int (*save_notify)(struct netmap_kring *kring, int flags); +#endif + #ifdef WITH_MONITOR - /* pointer to the adapter that is monitoring this kring (if any) - */ - struct netmap_monitor_adapter *monitor; + /* array of krings that are monitoring this kring */ + struct netmap_kring **monitors; + uint32_t max_monitors; /* current size of the monitors array */ + uint32_t n_monitors; /* next unused entry in the monitor array */ /* - * Monitors work by intercepting the txsync and/or rxsync of the - * monitored krings. This is implemented by replacing - * the nm_sync pointer above and saving the previous - * one in save_sync below. + * Monitors work by intercepting the sync and notify callbacks of the + * monitored krings. This is implemented by replacing the pointers + * above and saving the previous ones in mon_* pointers below */ - int (*save_sync)(struct netmap_kring *kring, int flags); + int (*mon_sync)(struct netmap_kring *kring, int flags); + int (*mon_notify)(struct netmap_kring *kring, int flags); + + uint32_t mon_tail; /* last seen slot on rx */ + uint32_t mon_pos; /* index of this ring in the monitored ring array */ #endif } __attribute__((__aligned__(64))); @@ -414,8 +465,11 @@ tail->| |<-hwtail | |<-hwlease */ - -enum txrx { NR_RX = 0, NR_TX = 1 }; +struct netmap_lut { + struct lut_entry *lut; + uint32_t objtotal; /* max buffer index */ + uint32_t objsize; /* buffer size */ +}; struct netmap_vp_adapter; // forward @@ -445,13 +499,13 @@ struct netmap_adapter { * forwarding packets coming from this * interface */ -#define NAF_MEM_OWNER 8 /* the adapter is responsible for the - * deallocation of the memory allocator +#define NAF_MEM_OWNER 8 /* the adapter uses its own memory area + * that cannot be changed */ -#define NAF_NATIVE_ON 16 /* the adapter is native and the attached - * interface is in netmap mode. - * Virtual ports (vale, pipe, monitor...) - * should never use this flag. +#define NAF_NATIVE 16 /* the adapter is native. + * Virtual ports (non persistent vale ports, + * pipes, monitors...) should never use + * this flag. */ #define NAF_NETMAP_ON 32 /* netmap is active (either native or * emulated). Where possible (e.g. FreeBSD) @@ -469,7 +523,7 @@ struct netmap_adapter { u_int num_rx_rings; /* number of adapter receive rings */ u_int num_tx_rings; /* number of adapter transmit rings */ - u_int num_tx_desc; /* number of descriptor in each queue */ + u_int num_tx_desc; /* number of descriptor in each queue */ u_int num_rx_desc; /* tx_rings and rx_rings are private but allocated @@ -483,10 +537,10 @@ struct netmap_adapter { /* (used for leases) */ - NM_SELINFO_T tx_si, rx_si; /* global wait queues */ + NM_SELINFO_T si[NR_TXRX]; /* global wait queues */ /* count users of the global wait queues */ - int tx_si_users, rx_si_users; + int si_users[NR_TXRX]; void *pdev; /* used to store pci device */ @@ -544,6 +598,7 @@ struct netmap_adapter { int (*nm_txsync)(struct netmap_kring *kring, int flags); int (*nm_rxsync)(struct netmap_kring *kring, int flags); + int (*nm_notify)(struct netmap_kring *kring, int flags); #define NAF_FORCE_READ 1 #define NAF_FORCE_RECLAIM 2 /* return configuration information */ @@ -551,12 +606,6 @@ struct netmap_adapter { u_int *txr, u_int *txd, u_int *rxr, u_int *rxd); int (*nm_krings_create)(struct netmap_adapter *); void (*nm_krings_delete)(struct netmap_adapter *); - int (*nm_notify)(struct netmap_adapter *, - u_int ring, enum txrx, int flags); -#define NAF_DISABLE_NOTIFY 8 /* notify that the stopped state of the - * ring has changed (kring->nkr_stopped) - */ - #ifdef WITH_VALE /* * nm_bdg_attach() initializes the na_vp field to point @@ -593,9 +642,7 @@ struct netmap_adapter { * buffer addresses, and the total number of buffers. */ struct netmap_mem_d *nm_mem; - struct lut_entry *na_lut; - uint32_t na_lut_objtotal; /* max buffer index */ - uint32_t na_lut_objsize; /* buffer size */ + struct netmap_lut na_lut; /* additional information attached to this adapter * by other netmap subsystems. Currently used by @@ -603,16 +650,49 @@ struct netmap_adapter { */ void *na_private; -#ifdef WITH_PIPES /* array of pipes that have this adapter as a parent */ struct netmap_pipe_adapter **na_pipes; int na_next_pipe; /* next free slot in the array */ int na_max_pipes; /* size of the array */ -#endif /* WITH_PIPES */ char name[64]; }; +static __inline u_int +nma_get_ndesc(struct netmap_adapter *na, enum txrx t) +{ + return (t == NR_TX ? na->num_tx_desc : na->num_rx_desc); +} + +static __inline void +nma_set_ndesc(struct netmap_adapter *na, enum txrx t, u_int v) +{ + if (t == NR_TX) + na->num_tx_desc = v; + else + na->num_rx_desc = v; +} + +static __inline u_int +nma_get_nrings(struct netmap_adapter *na, enum txrx t) +{ + return (t == NR_TX ? na->num_tx_rings : na->num_rx_rings); +} + +static __inline void +nma_set_nrings(struct netmap_adapter *na, enum txrx t, u_int v) +{ + if (t == NR_TX) + na->num_tx_rings = v; + else + na->num_rx_rings = v; +} + +static __inline struct netmap_kring* +NMR(struct netmap_adapter *na, enum txrx t) +{ + return (t == NR_TX ? na->tx_rings : na->rx_rings); +} /* * If the NIC is owned by the kernel @@ -624,7 +704,6 @@ struct netmap_adapter { #define NETMAP_OWNED_BY_ANY(na) \ (NETMAP_OWNED_BY_KERN(na) || ((na)->active_fds > 0)) - /* * derived netmap adapters for various types of ports */ @@ -645,6 +724,8 @@ struct netmap_vp_adapter { /* VALE software port */ u_int virt_hdr_len; /* Maximum Frame Size, used in bdg_mismatch_datapath() */ u_int mfs; + /* Last source MAC on this port */ + uint64_t last_smac; }; @@ -689,15 +770,9 @@ struct netmap_generic_adapter { /* emulated device */ #endif /* WITH_GENERIC */ static __inline int -netmap_real_tx_rings(struct netmap_adapter *na) +netmap_real_rings(struct netmap_adapter *na, enum txrx t) { - return na->num_tx_rings + !!(na->na_flags & NAF_HOST_RINGS); -} - -static __inline int -netmap_real_rx_rings(struct netmap_adapter *na) -{ - return na->num_rx_rings + !!(na->na_flags & NAF_HOST_RINGS); + return nma_get_nrings(na, t) + !!(na->na_flags & NAF_HOST_RINGS); } #ifdef WITH_VALE @@ -751,9 +826,6 @@ struct netmap_bwrap_adapter { struct netmap_vp_adapter host; /* for host rings */ struct netmap_adapter *hwna; /* the underlying device */ - /* backup of the hwna notify callback */ - int (*save_notify)(struct netmap_adapter *, - u_int ring, enum txrx, int flags); /* backup of the hwna memory allocator */ struct netmap_mem_d *save_nmd; @@ -847,6 +919,12 @@ static __inline int nm_kr_tryget(struct netmap_kring *kr) return 0; } +static __inline void nm_kr_get(struct netmap_kring *kr) +{ + while (NM_ATOMIC_TEST_AND_SET(&kr->nr_busy)) + tsleep(kr, 0, "NM_KR_GET", 4); +} + /* * The following functions are used by individual drivers to @@ -895,25 +973,25 @@ const char *netmap_bdg_name(struct netmap_vp_adapter *); #define netmap_bdg_name(_vp) NULL #endif /* WITH_VALE */ -static inline int -nm_native_on(struct netmap_adapter *na) -{ - return na && na->na_flags & NAF_NATIVE_ON; -} - static inline int nm_netmap_on(struct netmap_adapter *na) { return na && na->na_flags & NAF_NETMAP_ON; } +static inline int +nm_native_on(struct netmap_adapter *na) +{ + return nm_netmap_on(na) && (na->na_flags & NAF_NATIVE); +} + /* set/clear native flags and if_transmit/netdev_ops */ static inline void nm_set_native_flags(struct netmap_adapter *na) { struct ifnet *ifp = na->ifp; - na->na_flags |= (NAF_NATIVE_ON | NAF_NETMAP_ON); + na->na_flags |= NAF_NETMAP_ON; #ifdef IFCAP_NETMAP /* or FreeBSD ? */ ifp->if_capenable |= IFCAP_NETMAP; #endif @@ -940,63 +1018,13 @@ nm_clear_native_flags(struct netmap_adapter *na) ifp->netdev_ops = (void *)na->if_transmit; ifp->ethtool_ops = ((struct netmap_hw_adapter*)na)->save_ethtool; #endif - na->na_flags &= ~(NAF_NATIVE_ON | NAF_NETMAP_ON); + na->na_flags &= ~NAF_NETMAP_ON; #ifdef IFCAP_NETMAP /* or FreeBSD ? */ ifp->if_capenable &= ~IFCAP_NETMAP; #endif } -/* - * validates parameters in the ring/kring, returns a value for head - * If any error, returns ring_size to force a reinit. - */ -uint32_t nm_txsync_prologue(struct netmap_kring *); - - -/* - * validates parameters in the ring/kring, returns a value for head, - * and the 'reserved' value in the argument. - * If any error, returns ring_size lim to force a reinit. - */ -uint32_t nm_rxsync_prologue(struct netmap_kring *); - - -/* - * update kring and ring at the end of txsync. - */ -static inline void -nm_txsync_finalize(struct netmap_kring *kring) -{ - /* update ring tail to what the kernel knows */ - kring->ring->tail = kring->rtail = kring->nr_hwtail; - - /* note, head/rhead/hwcur might be behind cur/rcur - * if no carrier - */ - ND(5, "%s now hwcur %d hwtail %d head %d cur %d tail %d", - kring->name, kring->nr_hwcur, kring->nr_hwtail, - kring->rhead, kring->rcur, kring->rtail); -} - - -/* - * update kring and ring at the end of rxsync - */ -static inline void -nm_rxsync_finalize(struct netmap_kring *kring) -{ - /* tell userspace that there might be new packets */ - //struct netmap_ring *ring = kring->ring; - ND("head %d cur %d tail %d -> %d", ring->head, ring->cur, ring->tail, - kring->nr_hwtail); - kring->ring->tail = kring->rtail = kring->nr_hwtail; - /* make a copy of the state for next round */ - kring->rhead = kring->ring->head; - kring->rcur = kring->ring->cur; -} - - /* check/fix address and len in tx rings */ #if 1 /* debug version */ #define NM_CHECK_ADDR_LEN(_na, _a, _l) do { \ @@ -1056,20 +1084,15 @@ void netmap_krings_delete(struct netmap_adapter *na); * terminate. The status change is then notified using the na nm_notify * callback. */ -void netmap_set_txring(struct netmap_adapter *, u_int ring_id, int stopped); -void netmap_set_rxring(struct netmap_adapter *, u_int ring_id, int stopped); +void netmap_set_ring(struct netmap_adapter *, u_int ring_id, enum txrx, int stopped); /* set the stopped/enabled status of all rings of the adapter. */ void netmap_set_all_rings(struct netmap_adapter *, int stopped); /* convenience wrappers for netmap_set_all_rings, used in drivers */ void netmap_disable_all_rings(struct ifnet *); void netmap_enable_all_rings(struct ifnet *); -int netmap_rxsync_from_host(struct netmap_adapter *na, struct thread *td, void *pwait); - -struct netmap_if * -netmap_do_regif(struct netmap_priv_d *priv, struct netmap_adapter *na, - uint16_t ringid, uint32_t flags, int *err); - +int netmap_do_regif(struct netmap_priv_d *priv, struct netmap_adapter *na, + uint16_t ringid, uint32_t flags); u_int nm_bound_var(u_int *v, u_int dflt, u_int lo, u_int hi, const char *msg); @@ -1088,7 +1111,7 @@ int netmap_get_hw_na(struct ifnet *ifp, struct netmap_adapter **na); * XXX in practice "unknown" might be handled same as broadcast. */ typedef u_int (*bdg_lookup_fn_t)(struct nm_bdg_fwd *ft, uint8_t *ring_nr, - const struct netmap_vp_adapter *); + struct netmap_vp_adapter *); typedef int (*bdg_config_fn_t)(struct nm_ifreq *); typedef void (*bdg_dtor_fn_t)(const struct netmap_vp_adapter *); struct netmap_bdg_ops { @@ -1098,7 +1121,7 @@ struct netmap_bdg_ops { }; u_int netmap_bdg_learning(struct nm_bdg_fwd *ft, uint8_t *dst_ring, - const struct netmap_vp_adapter *); + struct netmap_vp_adapter *); #define NM_BDG_MAXPORTS 254 /* up to 254 */ #define NM_BDG_BROADCAST NM_BDG_MAXPORTS @@ -1108,34 +1131,52 @@ u_int netmap_bdg_learning(struct nm_bdg_fwd *ft, uint8_t *dst_ring, /* these are redefined in case of no VALE support */ int netmap_get_bdg_na(struct nmreq *nmr, struct netmap_adapter **na, int create); -void netmap_init_bridges(void); +struct nm_bridge *netmap_init_bridges2(u_int); +void netmap_uninit_bridges2(struct nm_bridge *, u_int); +int netmap_init_bridges(void); +void netmap_uninit_bridges(void); int netmap_bdg_ctl(struct nmreq *nmr, struct netmap_bdg_ops *bdg_ops); int netmap_bdg_config(struct nmreq *nmr); #else /* !WITH_VALE */ #define netmap_get_bdg_na(_1, _2, _3) 0 -#define netmap_init_bridges(_1) +#define netmap_init_bridges(_1) 0 +#define netmap_uninit_bridges() #define netmap_bdg_ctl(_1, _2) EINVAL #endif /* !WITH_VALE */ #ifdef WITH_PIPES /* max number of pipes per device */ #define NM_MAXPIPES 64 /* XXX how many? */ -/* in case of no error, returns the actual number of pipes in nmr->nr_arg1 */ -int netmap_pipe_alloc(struct netmap_adapter *, struct nmreq *nmr); void netmap_pipe_dealloc(struct netmap_adapter *); int netmap_get_pipe_na(struct nmreq *nmr, struct netmap_adapter **na, int create); #else /* !WITH_PIPES */ #define NM_MAXPIPES 0 -#define netmap_pipe_alloc(_1, _2) EOPNOTSUPP +#define netmap_pipe_alloc(_1, _2) 0 #define netmap_pipe_dealloc(_1) -#define netmap_get_pipe_na(_1, _2, _3) 0 +#define netmap_get_pipe_na(nmr, _2, _3) \ + ({ int role__ = (nmr)->nr_flags & NR_REG_MASK; \ + (role__ == NR_REG_PIPE_MASTER || \ + role__ == NR_REG_PIPE_SLAVE) ? EOPNOTSUPP : 0; }) #endif #ifdef WITH_MONITOR int netmap_get_monitor_na(struct nmreq *nmr, struct netmap_adapter **na, int create); +void netmap_monitor_stop(struct netmap_adapter *na); #else -#define netmap_get_monitor_na(_1, _2, _3) 0 +#define netmap_get_monitor_na(nmr, _2, _3) \ + ((nmr)->nr_flags & (NR_MONITOR_TX | NR_MONITOR_RX) ? EOPNOTSUPP : 0) +#endif + +#ifdef CONFIG_NET_NS +struct net *netmap_bns_get(void); +void netmap_bns_put(struct net *); +void netmap_bns_getbridges(struct nm_bridge **, u_int *); +#else +#define netmap_bns_get() +#define netmap_bns_put(_1) +#define netmap_bns_getbridges(b, n) \ + do { *b = nm_bridges; *n = NM_BRIDGES; } while (0) #endif /* Various prototypes */ @@ -1186,8 +1227,8 @@ int netmap_adapter_put(struct netmap_adapter *na); /* * module variables */ -#define NETMAP_BUF_BASE(na) ((na)->na_lut[0].vaddr) -#define NETMAP_BUF_SIZE(na) ((na)->na_lut_objsize) +#define NETMAP_BUF_BASE(na) ((na)->na_lut.lut[0].vaddr) +#define NETMAP_BUF_SIZE(na) ((na)->na_lut.objsize) extern int netmap_mitigate; // XXX not really used extern int netmap_no_pendintr; extern int netmap_verbose; // XXX debugging @@ -1206,6 +1247,7 @@ extern int netmap_txsync_retry; extern int netmap_generic_mit; extern int netmap_generic_ringsize; extern int netmap_generic_rings; +extern int netmap_use_count; /* * NA returns a pointer to the struct netmap adapter from the ifp, @@ -1291,15 +1333,14 @@ netmap_reload_map(struct netmap_adapter *na, #else /* linux */ int nm_iommu_group_id(bus_dma_tag_t dev); -extern size_t netmap_mem_get_bufsize(struct netmap_mem_d *); #include static inline void netmap_load_map(struct netmap_adapter *na, bus_dma_tag_t tag, bus_dmamap_t map, void *buf) { - if (map) { - *map = dma_map_single(na->pdev, buf, netmap_mem_get_bufsize(na->nm_mem), + if (0 && map) { + *map = dma_map_single(na->pdev, buf, na->na_lut.objsize, DMA_BIDIRECTIONAL); } } @@ -1308,7 +1349,7 @@ static inline void netmap_unload_map(struct netmap_adapter *na, bus_dma_tag_t tag, bus_dmamap_t map) { - u_int sz = netmap_mem_get_bufsize(na->nm_mem); + u_int sz = na->na_lut.objsize; if (*map) { dma_unmap_single(na->pdev, *map, sz, @@ -1320,7 +1361,7 @@ static inline void netmap_reload_map(struct netmap_adapter *na, bus_dma_tag_t tag, bus_dmamap_t map, void *buf) { - u_int sz = netmap_mem_get_bufsize(na->nm_mem); + u_int sz = na->na_lut.objsize; if (*map) { dma_unmap_single(na->pdev, *map, sz, @@ -1418,9 +1459,9 @@ struct netmap_obj_pool; static inline void * NMB(struct netmap_adapter *na, struct netmap_slot *slot) { - struct lut_entry *lut = na->na_lut; + struct lut_entry *lut = na->na_lut.lut; uint32_t i = slot->buf_idx; - return (unlikely(i >= na->na_lut_objtotal)) ? + return (unlikely(i >= na->na_lut.objtotal)) ? lut[0].vaddr : lut[i].vaddr; } @@ -1428,63 +1469,45 @@ static inline void * PNMB(struct netmap_adapter *na, struct netmap_slot *slot, uint64_t *pp) { uint32_t i = slot->buf_idx; - struct lut_entry *lut = na->na_lut; - void *ret = (i >= na->na_lut_objtotal) ? lut[0].vaddr : lut[i].vaddr; + struct lut_entry *lut = na->na_lut.lut; + void *ret = (i >= na->na_lut.objtotal) ? lut[0].vaddr : lut[i].vaddr; - *pp = (i >= na->na_lut_objtotal) ? lut[0].paddr : lut[i].paddr; + *pp = (i >= na->na_lut.objtotal) ? lut[0].paddr : lut[i].paddr; return ret; } -/* Generic version of NMB, which uses device-specific memory. */ - - - -void netmap_txsync_to_host(struct netmap_adapter *na); - /* - * Structure associated to each thread which registered an interface. + * Structure associated to each netmap file descriptor. + * It is created on open and left unbound (np_nifp == NULL). + * A successful NIOCREGIF will set np_nifp and the first few fields; + * this is protected by a global lock (NMG_LOCK) due to low contention. * - * The first 4 fields of this structure are written by NIOCREGIF and - * read by poll() and NIOC?XSYNC. + * np_refs counts the number of references to the structure: one for the fd, + * plus (on FreeBSD) one for each active mmap which we track ourselves + * (linux automatically tracks them, but FreeBSD does not). + * np_refs is protected by NMG_LOCK. * - * There is low contention among writers (a correct user program - * should have none) and among writers and readers, so we use a - * single global lock to protect the structure initialization; - * since initialization involves the allocation of memory, - * we reuse the memory allocator lock. - * - * Read access to the structure is lock free. Readers must check that - * np_nifp is not NULL before using the other fields. - * If np_nifp is NULL initialization has not been performed, - * so they should return an error to userspace. - * - * The ref_done field is used to regulate access to the refcount in the - * memory allocator. The refcount must be incremented at most once for - * each open("/dev/netmap"). The increment is performed by the first - * function that calls netmap_get_memory() (currently called by - * mmap(), NIOCGINFO and NIOCREGIF). - * If the refcount is incremented, it is then decremented when the - * private structure is destroyed. + * Read access to the structure is lock free, because ni_nifp once set + * can only go to 0 when nobody is using the entry anymore. Readers + * must check that np_nifp != NULL before using the other fields. */ struct netmap_priv_d { struct netmap_if * volatile np_nifp; /* netmap if descriptor. */ struct netmap_adapter *np_na; uint32_t np_flags; /* from the ioctl */ - u_int np_txqfirst, np_txqlast; /* range of tx rings to scan */ - u_int np_rxqfirst, np_rxqlast; /* range of rx rings to scan */ + u_int np_qfirst[NR_TXRX], + np_qlast[NR_TXRX]; /* range of tx/rx rings to scan */ uint16_t np_txpoll; /* XXX and also np_rxpoll ? */ - struct netmap_mem_d *np_mref; /* use with NMG_LOCK held */ - /* np_refcount is only used on FreeBSD */ - int np_refcount; /* use with NMG_LOCK held */ + int np_refs; /* use with NMG_LOCK held */ /* pointers to the selinfo to be used for selrecord. * Either the local or the global one depending on the * number of rings. */ - NM_SELINFO_T *np_rxsi, *np_txsi; + NM_SELINFO_T *np_si[NR_TXRX]; struct thread *np_td; /* kqueue, just debugging */ }; @@ -1507,12 +1530,20 @@ struct netmap_monitor_adapter { */ int generic_netmap_attach(struct ifnet *ifp); -int netmap_catch_rx(struct netmap_adapter *na, int intercept); +int netmap_catch_rx(struct netmap_generic_adapter *na, int intercept); void generic_rx_handler(struct ifnet *ifp, struct mbuf *m);; void netmap_catch_tx(struct netmap_generic_adapter *na, int enable); int generic_xmit_frame(struct ifnet *ifp, struct mbuf *m, void *addr, u_int len, u_int ring_nr); int generic_find_num_desc(struct ifnet *ifp, u_int *tx, u_int *rx); void generic_find_num_queues(struct ifnet *ifp, u_int *txq, u_int *rxq); +static inline struct ifnet* +netmap_generic_getifp(struct netmap_generic_adapter *gna) +{ + if (gna->prev) + return gna->prev->ifp; + + return gna->up.up.ifp; +} //#define RATE_GENERIC /* Enables communication statistics for generic. */ #ifdef RATE_GENERIC diff --git a/sys/dev/netmap/netmap_mem2.c b/sys/dev/netmap/netmap_mem2.c index c823376dbab6..023604d49535 100644 --- a/sys/dev/netmap/netmap_mem2.c +++ b/sys/dev/netmap/netmap_mem2.c @@ -71,6 +71,7 @@ struct netmap_obj_params { u_int size; u_int num; }; + struct netmap_obj_pool { char name[NETMAP_POOL_MAX_NAMSZ]; /* name of the allocator */ @@ -106,16 +107,26 @@ struct netmap_obj_pool { u_int r_objsize; }; -#ifdef linux -// XXX a mtx would suffice here 20130415 lr -#define NMA_LOCK_T struct semaphore -#else /* !linux */ -#define NMA_LOCK_T struct mtx -#endif /* linux */ +#define NMA_LOCK_T NM_MTX_T -typedef int (*netmap_mem_config_t)(struct netmap_mem_d*); -typedef int (*netmap_mem_finalize_t)(struct netmap_mem_d*); -typedef void (*netmap_mem_deref_t)(struct netmap_mem_d*); + +struct netmap_mem_ops { + void (*nmd_get_lut)(struct netmap_mem_d *, struct netmap_lut*); + int (*nmd_get_info)(struct netmap_mem_d *, u_int *size, + u_int *memflags, uint16_t *id); + + vm_paddr_t (*nmd_ofstophys)(struct netmap_mem_d *, vm_ooffset_t); + int (*nmd_config)(struct netmap_mem_d *); + int (*nmd_finalize)(struct netmap_mem_d *); + void (*nmd_deref)(struct netmap_mem_d *); + ssize_t (*nmd_if_offset)(struct netmap_mem_d *, const void *vaddr); + void (*nmd_delete)(struct netmap_mem_d *); + + struct netmap_if * (*nmd_if_new)(struct netmap_adapter *); + void (*nmd_if_delete)(struct netmap_adapter *, struct netmap_if *); + int (*nmd_rings_create)(struct netmap_adapter *); + void (*nmd_rings_delete)(struct netmap_adapter *); +}; typedef uint16_t nm_memid_t; @@ -126,53 +137,145 @@ struct netmap_mem_d { u_int flags; #define NETMAP_MEM_FINALIZED 0x1 /* preallocation done */ int lasterr; /* last error for curr config */ - int refcount; /* existing priv structures */ + int active; /* active users */ + int refcount; /* the three allocators */ struct netmap_obj_pool pools[NETMAP_POOLS_NR]; - netmap_mem_config_t config; /* called with NMA_LOCK held */ - netmap_mem_finalize_t finalize; /* called with NMA_LOCK held */ - netmap_mem_deref_t deref; /* called with NMA_LOCK held */ - nm_memid_t nm_id; /* allocator identifier */ int nm_grp; /* iommu groupd id */ /* list of all existing allocators, sorted by nm_id */ struct netmap_mem_d *prev, *next; + + struct netmap_mem_ops *ops; }; +#define NMD_DEFCB(t0, name) \ +t0 \ +netmap_mem_##name(struct netmap_mem_d *nmd) \ +{ \ + return nmd->ops->nmd_##name(nmd); \ +} + +#define NMD_DEFCB1(t0, name, t1) \ +t0 \ +netmap_mem_##name(struct netmap_mem_d *nmd, t1 a1) \ +{ \ + return nmd->ops->nmd_##name(nmd, a1); \ +} + +#define NMD_DEFCB3(t0, name, t1, t2, t3) \ +t0 \ +netmap_mem_##name(struct netmap_mem_d *nmd, t1 a1, t2 a2, t3 a3) \ +{ \ + return nmd->ops->nmd_##name(nmd, a1, a2, a3); \ +} + +#define NMD_DEFNACB(t0, name) \ +t0 \ +netmap_mem_##name(struct netmap_adapter *na) \ +{ \ + return na->nm_mem->ops->nmd_##name(na); \ +} + +#define NMD_DEFNACB1(t0, name, t1) \ +t0 \ +netmap_mem_##name(struct netmap_adapter *na, t1 a1) \ +{ \ + return na->nm_mem->ops->nmd_##name(na, a1); \ +} + +NMD_DEFCB1(void, get_lut, struct netmap_lut *); +NMD_DEFCB3(int, get_info, u_int *, u_int *, uint16_t *); +NMD_DEFCB1(vm_paddr_t, ofstophys, vm_ooffset_t); +static int netmap_mem_config(struct netmap_mem_d *); +NMD_DEFCB(int, config); +NMD_DEFCB1(ssize_t, if_offset, const void *); +NMD_DEFCB(void, delete); + +NMD_DEFNACB(struct netmap_if *, if_new); +NMD_DEFNACB1(void, if_delete, struct netmap_if *); +NMD_DEFNACB(int, rings_create); +NMD_DEFNACB(void, rings_delete); + +static int netmap_mem_map(struct netmap_obj_pool *, struct netmap_adapter *); +static int netmap_mem_unmap(struct netmap_obj_pool *, struct netmap_adapter *); +static int nm_mem_assign_group(struct netmap_mem_d *, struct device *); + +#define NMA_LOCK_INIT(n) NM_MTX_INIT((n)->nm_mtx) +#define NMA_LOCK_DESTROY(n) NM_MTX_DESTROY((n)->nm_mtx) +#define NMA_LOCK(n) NM_MTX_LOCK((n)->nm_mtx) +#define NMA_UNLOCK(n) NM_MTX_UNLOCK((n)->nm_mtx) + +#ifdef NM_DEBUG_MEM_PUTGET +#define NM_DBG_REFC(nmd, func, line) \ + printf("%s:%d mem[%d] -> %d\n", func, line, (nmd)->nm_id, (nmd)->refcount); +#else +#define NM_DBG_REFC(nmd, func, line) +#endif + +#ifdef NM_DEBUG_MEM_PUTGET +void __netmap_mem_get(struct netmap_mem_d *nmd, const char *func, int line) +#else +void netmap_mem_get(struct netmap_mem_d *nmd) +#endif +{ + NMA_LOCK(nmd); + nmd->refcount++; + NM_DBG_REFC(nmd, func, line); + NMA_UNLOCK(nmd); +} + +#ifdef NM_DEBUG_MEM_PUTGET +void __netmap_mem_put(struct netmap_mem_d *nmd, const char *func, int line) +#else +void netmap_mem_put(struct netmap_mem_d *nmd) +#endif +{ + int last; + NMA_LOCK(nmd); + last = (--nmd->refcount == 0); + NM_DBG_REFC(nmd, func, line); + NMA_UNLOCK(nmd); + if (last) + netmap_mem_delete(nmd); +} + +int +netmap_mem_finalize(struct netmap_mem_d *nmd, struct netmap_adapter *na) +{ + if (nm_mem_assign_group(nmd, na->pdev) < 0) { + return ENOMEM; + } else { + nmd->ops->nmd_finalize(nmd); + } + + if (!nmd->lasterr && na->pdev) + netmap_mem_map(&nmd->pools[NETMAP_BUF_POOL], na); + + return nmd->lasterr; +} + +void +netmap_mem_deref(struct netmap_mem_d *nmd, struct netmap_adapter *na) +{ + NMA_LOCK(nmd); + netmap_mem_unmap(&nmd->pools[NETMAP_BUF_POOL], na); + NMA_UNLOCK(nmd); + return nmd->ops->nmd_deref(nmd); +} + + /* accessor functions */ -struct lut_entry* -netmap_mem_get_lut(struct netmap_mem_d *nmd) +static void +netmap_mem2_get_lut(struct netmap_mem_d *nmd, struct netmap_lut *lut) { - return nmd->pools[NETMAP_BUF_POOL].lut; + lut->lut = nmd->pools[NETMAP_BUF_POOL].lut; + lut->objtotal = nmd->pools[NETMAP_BUF_POOL].objtotal; + lut->objsize = nmd->pools[NETMAP_BUF_POOL]._objsize; } -u_int -netmap_mem_get_buftotal(struct netmap_mem_d *nmd) -{ - return nmd->pools[NETMAP_BUF_POOL].objtotal; -} - -size_t -netmap_mem_get_bufsize(struct netmap_mem_d *nmd) -{ - return nmd->pools[NETMAP_BUF_POOL]._objsize; -} - -#ifdef linux -#define NMA_LOCK_INIT(n) sema_init(&(n)->nm_mtx, 1) -#define NMA_LOCK_DESTROY(n) -#define NMA_LOCK(n) down(&(n)->nm_mtx) -#define NMA_UNLOCK(n) up(&(n)->nm_mtx) -#else /* !linux */ -#define NMA_LOCK_INIT(n) mtx_init(&(n)->nm_mtx, "netmap memory allocator lock", NULL, MTX_DEF) -#define NMA_LOCK_DESTROY(n) mtx_destroy(&(n)->nm_mtx) -#define NMA_LOCK(n) mtx_lock(&(n)->nm_mtx) -#define NMA_UNLOCK(n) mtx_unlock(&(n)->nm_mtx) -#endif /* linux */ - - struct netmap_obj_params netmap_params[NETMAP_POOLS_NR] = { [NETMAP_IF_POOL] = { .size = 1024, @@ -209,9 +312,7 @@ struct netmap_obj_params netmap_min_priv_params[NETMAP_POOLS_NR] = { * running in netmap mode. * Virtual (VALE) ports will have each its own allocator. */ -static int netmap_mem_global_config(struct netmap_mem_d *nmd); -static int netmap_mem_global_finalize(struct netmap_mem_d *nmd); -static void netmap_mem_global_deref(struct netmap_mem_d *nmd); +extern struct netmap_mem_ops netmap_mem_global_ops; /* forward */ struct netmap_mem_d nm_mem = { /* Our memory allocator. */ .pools = { [NETMAP_IF_POOL] = { @@ -236,24 +337,21 @@ struct netmap_mem_d nm_mem = { /* Our memory allocator. */ .nummax = 1000000, /* one million! */ }, }, - .config = netmap_mem_global_config, - .finalize = netmap_mem_global_finalize, - .deref = netmap_mem_global_deref, .nm_id = 1, .nm_grp = -1, .prev = &nm_mem, .next = &nm_mem, + + .ops = &netmap_mem_global_ops }; struct netmap_mem_d *netmap_last_mem_d = &nm_mem; /* blueprint for the private memory allocators */ -static int netmap_mem_private_config(struct netmap_mem_d *nmd); -static int netmap_mem_private_finalize(struct netmap_mem_d *nmd); -static void netmap_mem_private_deref(struct netmap_mem_d *nmd); +extern struct netmap_mem_ops netmap_mem_private_ops; /* forward */ const struct netmap_mem_d nm_blueprint = { .pools = { [NETMAP_IF_POOL] = { @@ -278,11 +376,10 @@ const struct netmap_mem_d nm_blueprint = { .nummax = 1000000, /* one million! */ }, }, - .config = netmap_mem_private_config, - .finalize = netmap_mem_private_finalize, - .deref = netmap_mem_private_deref, .flags = NETMAP_MEM_PRIVATE, + + .ops = &netmap_mem_private_ops }; /* memory allocator related sysctls */ @@ -382,8 +479,8 @@ nm_mem_assign_group(struct netmap_mem_d *nmd, struct device *dev) * First, find the allocator that contains the requested offset, * then locate the cluster through a lookup table. */ -vm_paddr_t -netmap_mem_ofstophys(struct netmap_mem_d* nmd, vm_ooffset_t offset) +static vm_paddr_t +netmap_mem2_ofstophys(struct netmap_mem_d* nmd, vm_ooffset_t offset) { int i; vm_ooffset_t o = offset; @@ -414,13 +511,13 @@ netmap_mem_ofstophys(struct netmap_mem_d* nmd, vm_ooffset_t offset) return 0; // XXX bad address } -int -netmap_mem_get_info(struct netmap_mem_d* nmd, u_int* size, u_int *memflags, +static int +netmap_mem2_get_info(struct netmap_mem_d* nmd, u_int* size, u_int *memflags, nm_memid_t *id) { int error = 0; NMA_LOCK(nmd); - error = nmd->config(nmd); + error = netmap_mem_config(nmd); if (error) goto out; if (size) { @@ -487,8 +584,8 @@ netmap_obj_offset(struct netmap_obj_pool *p, const void *vaddr) netmap_obj_offset(&(n)->pools[NETMAP_BUF_POOL], (v))) -ssize_t -netmap_mem_if_offset(struct netmap_mem_d *nmd, const void *addr) +static ssize_t +netmap_mem2_if_offset(struct netmap_mem_d *nmd, const void *addr) { ssize_t v; NMA_LOCK(nmd); @@ -648,7 +745,7 @@ netmap_extra_alloc(struct netmap_adapter *na, uint32_t *head, uint32_t n) static void netmap_extra_free(struct netmap_adapter *na, uint32_t head) { - struct lut_entry *lut = na->na_lut; + struct lut_entry *lut = na->na_lut.lut; struct netmap_mem_d *nmd = na->nm_mem; struct netmap_obj_pool *p = &nmd->pools[NETMAP_BUF_POOL]; uint32_t i, cur, *buf; @@ -1081,15 +1178,15 @@ error: -void +static void netmap_mem_private_delete(struct netmap_mem_d *nmd) { if (nmd == NULL) return; if (netmap_verbose) D("deleting %p", nmd); - if (nmd->refcount > 0) - D("bug: deleting mem allocator with refcount=%d!", nmd->refcount); + if (nmd->active > 0) + D("bug: deleting mem allocator with active=%d!", nmd->active); nm_mem_release_id(nmd); if (netmap_verbose) D("done deleting %p", nmd); @@ -1110,8 +1207,10 @@ static int netmap_mem_private_finalize(struct netmap_mem_d *nmd) { int err; - nmd->refcount++; + NMA_LOCK(nmd); + nmd->active++; err = netmap_mem_finalize_all(nmd); + NMA_UNLOCK(nmd); return err; } @@ -1119,8 +1218,10 @@ netmap_mem_private_finalize(struct netmap_mem_d *nmd) static void netmap_mem_private_deref(struct netmap_mem_d *nmd) { - if (--nmd->refcount <= 0) + NMA_LOCK(nmd); + if (--nmd->active <= 0) netmap_mem_reset_all(nmd); + NMA_UNLOCK(nmd); } @@ -1223,14 +1324,14 @@ netmap_mem_global_config(struct netmap_mem_d *nmd) { int i; - if (nmd->refcount) + if (nmd->active) /* already in use, we cannot change the configuration */ goto out; if (!netmap_memory_config_changed(nmd)) goto out; - D("reconfiguring"); + ND("reconfiguring"); if (nmd->flags & NETMAP_MEM_FINALIZED) { /* reset previous allocation */ @@ -1261,7 +1362,7 @@ netmap_mem_global_finalize(struct netmap_mem_d *nmd) if (netmap_mem_global_config(nmd)) goto out; - nmd->refcount++; + nmd->active++; if (nmd->flags & NETMAP_MEM_FINALIZED) { /* may happen if config is not changed */ @@ -1276,53 +1377,56 @@ netmap_mem_global_finalize(struct netmap_mem_d *nmd) out: if (nmd->lasterr) - nmd->refcount--; + nmd->active--; err = nmd->lasterr; return err; } -int -netmap_mem_init(void) -{ - NMA_LOCK_INIT(&nm_mem); - return (0); -} - -void -netmap_mem_fini(void) +static void +netmap_mem_global_delete(struct netmap_mem_d *nmd) { int i; for (i = 0; i < NETMAP_POOLS_NR; i++) { netmap_destroy_obj_allocator(&nm_mem.pools[i]); } + NMA_LOCK_DESTROY(&nm_mem); } +int +netmap_mem_init(void) +{ + NMA_LOCK_INIT(&nm_mem); + netmap_mem_get(&nm_mem); + return (0); +} + +void +netmap_mem_fini(void) +{ + netmap_mem_put(&nm_mem); +} + static void netmap_free_rings(struct netmap_adapter *na) { - struct netmap_kring *kring; - struct netmap_ring *ring; - if (!na->tx_rings) - return; - for (kring = na->tx_rings; kring != na->rx_rings; kring++) { - ring = kring->ring; - if (ring == NULL) - continue; - netmap_free_bufs(na->nm_mem, ring->slot, kring->nkr_num_slots); - netmap_ring_free(na->nm_mem, ring); - kring->ring = NULL; - } - for (/* cont'd from above */; kring != na->tailroom; kring++) { - ring = kring->ring; - if (ring == NULL) - continue; - netmap_free_bufs(na->nm_mem, ring->slot, kring->nkr_num_slots); - netmap_ring_free(na->nm_mem, ring); - kring->ring = NULL; + enum txrx t; + + for_rx_tx(t) { + u_int i; + for (i = 0; i < netmap_real_rings(na, t); i++) { + struct netmap_kring *kring = &NMR(na, t)[i]; + struct netmap_ring *ring = kring->ring; + + if (ring == NULL) + continue; + netmap_free_bufs(na->nm_mem, ring->slot, kring->nkr_num_slots); + netmap_ring_free(na->nm_mem, ring); + kring->ring = NULL; + } } } @@ -1333,99 +1437,63 @@ netmap_free_rings(struct netmap_adapter *na) * The kring array must follow the layout described * in netmap_krings_create(). */ -int -netmap_mem_rings_create(struct netmap_adapter *na) +static int +netmap_mem2_rings_create(struct netmap_adapter *na) { - struct netmap_ring *ring; - u_int len, ndesc; - struct netmap_kring *kring; - u_int i; + enum txrx t; NMA_LOCK(na->nm_mem); - /* transmit rings */ - for (i =0, kring = na->tx_rings; kring != na->rx_rings; kring++, i++) { - if (kring->ring) { - ND("%s %ld already created", kring->name, kring - na->tx_rings); - continue; /* already created by somebody else */ - } - ndesc = kring->nkr_num_slots; - len = sizeof(struct netmap_ring) + - ndesc * sizeof(struct netmap_slot); - ring = netmap_ring_malloc(na->nm_mem, len); - if (ring == NULL) { - D("Cannot allocate tx_ring"); - goto cleanup; - } - ND("txring at %p", ring); - kring->ring = ring; - *(uint32_t *)(uintptr_t)&ring->num_slots = ndesc; - *(int64_t *)(uintptr_t)&ring->buf_ofs = - (na->nm_mem->pools[NETMAP_IF_POOL].memtotal + - na->nm_mem->pools[NETMAP_RING_POOL].memtotal) - - netmap_ring_offset(na->nm_mem, ring); + for_rx_tx(t) { + u_int i; - /* copy values from kring */ - ring->head = kring->rhead; - ring->cur = kring->rcur; - ring->tail = kring->rtail; - *(uint16_t *)(uintptr_t)&ring->nr_buf_size = - netmap_mem_bufsize(na->nm_mem); - ND("%s h %d c %d t %d", kring->name, - ring->head, ring->cur, ring->tail); - ND("initializing slots for txring"); - if (i != na->num_tx_rings || (na->na_flags & NAF_HOST_RINGS)) { - /* this is a real ring */ - if (netmap_new_bufs(na->nm_mem, ring->slot, ndesc)) { - D("Cannot allocate buffers for tx_ring"); + for (i = 0; i <= nma_get_nrings(na, t); i++) { + struct netmap_kring *kring = &NMR(na, t)[i]; + struct netmap_ring *ring = kring->ring; + u_int len, ndesc; + + if (ring) { + ND("%s already created", kring->name); + continue; /* already created by somebody else */ + } + ndesc = kring->nkr_num_slots; + len = sizeof(struct netmap_ring) + + ndesc * sizeof(struct netmap_slot); + ring = netmap_ring_malloc(na->nm_mem, len); + if (ring == NULL) { + D("Cannot allocate %s_ring", nm_txrx2str(t)); goto cleanup; } - } else { - /* this is a fake tx ring, set all indices to 0 */ - netmap_mem_set_ring(na->nm_mem, ring->slot, ndesc, 0); - } - } + ND("txring at %p", ring); + kring->ring = ring; + *(uint32_t *)(uintptr_t)&ring->num_slots = ndesc; + *(int64_t *)(uintptr_t)&ring->buf_ofs = + (na->nm_mem->pools[NETMAP_IF_POOL].memtotal + + na->nm_mem->pools[NETMAP_RING_POOL].memtotal) - + netmap_ring_offset(na->nm_mem, ring); - /* receive rings */ - for ( i = 0 /* kring cont'd from above */ ; kring != na->tailroom; kring++, i++) { - if (kring->ring) { - ND("%s %ld already created", kring->name, kring - na->rx_rings); - continue; /* already created by somebody else */ - } - ndesc = kring->nkr_num_slots; - len = sizeof(struct netmap_ring) + - ndesc * sizeof(struct netmap_slot); - ring = netmap_ring_malloc(na->nm_mem, len); - if (ring == NULL) { - D("Cannot allocate rx_ring"); - goto cleanup; - } - ND("rxring at %p", ring); - kring->ring = ring; - *(uint32_t *)(uintptr_t)&ring->num_slots = ndesc; - *(int64_t *)(uintptr_t)&ring->buf_ofs = - (na->nm_mem->pools[NETMAP_IF_POOL].memtotal + - na->nm_mem->pools[NETMAP_RING_POOL].memtotal) - - netmap_ring_offset(na->nm_mem, ring); - - /* copy values from kring */ - ring->head = kring->rhead; - ring->cur = kring->rcur; - ring->tail = kring->rtail; - *(int *)(uintptr_t)&ring->nr_buf_size = - netmap_mem_bufsize(na->nm_mem); - ND("%s h %d c %d t %d", kring->name, - ring->head, ring->cur, ring->tail); - ND("initializing slots for rxring %p", ring); - if (i != na->num_rx_rings || (na->na_flags & NAF_HOST_RINGS)) { - /* this is a real ring */ - if (netmap_new_bufs(na->nm_mem, ring->slot, ndesc)) { - D("Cannot allocate buffers for rx_ring"); - goto cleanup; + /* copy values from kring */ + ring->head = kring->rhead; + ring->cur = kring->rcur; + ring->tail = kring->rtail; + *(uint16_t *)(uintptr_t)&ring->nr_buf_size = + netmap_mem_bufsize(na->nm_mem); + ND("%s h %d c %d t %d", kring->name, + ring->head, ring->cur, ring->tail); + ND("initializing slots for %s_ring", nm_txrx2str(txrx)); + if (i != nma_get_nrings(na, t) || (na->na_flags & NAF_HOST_RINGS)) { + /* this is a real ring */ + if (netmap_new_bufs(na->nm_mem, ring->slot, ndesc)) { + D("Cannot allocate buffers for %s_ring", nm_txrx2str(t)); + goto cleanup; + } + } else { + /* this is a fake ring, set all indices to 0 */ + netmap_mem_set_ring(na->nm_mem, ring->slot, ndesc, 0); } - } else { - /* this is a fake rx ring, set all indices to 1 */ - netmap_mem_set_ring(na->nm_mem, ring->slot, ndesc, 1); + /* ring info */ + *(uint16_t *)(uintptr_t)&ring->ringid = kring->ring_id; + *(uint16_t *)(uintptr_t)&ring->dir = kring->tx; } } @@ -1441,8 +1509,8 @@ cleanup: return ENOMEM; } -void -netmap_mem_rings_delete(struct netmap_adapter *na) +static void +netmap_mem2_rings_delete(struct netmap_adapter *na) { /* last instance, release bufs and rings */ NMA_LOCK(na->nm_mem); @@ -1461,16 +1529,20 @@ netmap_mem_rings_delete(struct netmap_adapter *na) * (number of tx/rx rings and descs) does not change while * the interface is in netmap mode. */ -struct netmap_if * -netmap_mem_if_new(struct netmap_adapter *na) +static struct netmap_if * +netmap_mem2_if_new(struct netmap_adapter *na) { struct netmap_if *nifp; ssize_t base; /* handy for relative offsets between rings and nifp */ - u_int i, len, ntx, nrx; + u_int i, len, n[NR_TXRX], ntot; + enum txrx t; - /* account for the (eventually fake) host rings */ - ntx = na->num_tx_rings + 1; - nrx = na->num_rx_rings + 1; + ntot = 0; + for_rx_tx(t) { + /* account for the (eventually fake) host rings */ + n[t] = nma_get_nrings(na, t) + 1; + ntot += n[t]; + } /* * the descriptor is followed inline by an array of offsets * to the tx and rx rings in the shared memory region. @@ -1478,7 +1550,7 @@ netmap_mem_if_new(struct netmap_adapter *na) NMA_LOCK(na->nm_mem); - len = sizeof(struct netmap_if) + (nrx + ntx) * sizeof(ssize_t); + len = sizeof(struct netmap_if) + (ntot * sizeof(ssize_t)); nifp = netmap_if_malloc(na->nm_mem, len); if (nifp == NULL) { NMA_UNLOCK(na->nm_mem); @@ -1496,12 +1568,12 @@ netmap_mem_if_new(struct netmap_adapter *na) * userspace to reach the ring from the nifp. */ base = netmap_if_offset(na->nm_mem, nifp); - for (i = 0; i < ntx; i++) { + for (i = 0; i < n[NR_TX]; i++) { *(ssize_t *)(uintptr_t)&nifp->ring_ofs[i] = netmap_ring_offset(na->nm_mem, na->tx_rings[i].ring) - base; } - for (i = 0; i < nrx; i++) { - *(ssize_t *)(uintptr_t)&nifp->ring_ofs[i+ntx] = + for (i = 0; i < n[NR_RX]; i++) { + *(ssize_t *)(uintptr_t)&nifp->ring_ofs[i+n[NR_TX]] = netmap_ring_offset(na->nm_mem, na->rx_rings[i].ring) - base; } @@ -1510,8 +1582,8 @@ netmap_mem_if_new(struct netmap_adapter *na) return (nifp); } -void -netmap_mem_if_delete(struct netmap_adapter *na, struct netmap_if *nifp) +static void +netmap_mem2_if_delete(struct netmap_adapter *na, struct netmap_if *nifp) { if (nifp == NULL) /* nothing to do */ @@ -1528,78 +1600,39 @@ static void netmap_mem_global_deref(struct netmap_mem_d *nmd) { - nmd->refcount--; - if (!nmd->refcount) + nmd->active--; + if (!nmd->active) nmd->nm_grp = -1; if (netmap_verbose) - D("refcount = %d", nmd->refcount); + D("active = %d", nmd->active); } -int -netmap_mem_finalize(struct netmap_mem_d *nmd, struct netmap_adapter *na) -{ - if (nm_mem_assign_group(nmd, na->pdev) < 0) { - return ENOMEM; - } else { - NMA_LOCK(nmd); - nmd->finalize(nmd); - NMA_UNLOCK(nmd); - } - - if (!nmd->lasterr && na->pdev) - netmap_mem_map(&nmd->pools[NETMAP_BUF_POOL], na); - - return nmd->lasterr; -} - -void -netmap_mem_deref(struct netmap_mem_d *nmd, struct netmap_adapter *na) -{ - NMA_LOCK(nmd); - netmap_mem_unmap(&nmd->pools[NETMAP_BUF_POOL], na); - if (nmd->refcount == 1) { - u_int i; - - /* - * Reset the allocator when it falls out of use so that any - * pool resources leaked by unclean application exits are - * reclaimed. - */ - for (i = 0; i < NETMAP_POOLS_NR; i++) { - struct netmap_obj_pool *p; - u_int j; - - p = &nmd->pools[i]; - p->objfree = p->objtotal; - /* - * Reproduce the net effect of the M_ZERO malloc() - * and marking of free entries in the bitmap that - * occur in finalize_obj_allocator() - */ - memset(p->bitmap, - '\0', - sizeof(uint32_t) * ((p->objtotal + 31) / 32)); - - /* - * Set all the bits in the bitmap that have - * corresponding buffers to 1 to indicate they are - * free. - */ - for (j = 0; j < p->objtotal; j++) { - if (p->lut[j].vaddr != NULL) { - p->bitmap[ (j>>5) ] |= ( 1 << (j & 31) ); - } - } - } - - /* - * Per netmap_mem_finalize_all(), - * buffers 0 and 1 are reserved - */ - nmd->pools[NETMAP_BUF_POOL].objfree -= 2; - nmd->pools[NETMAP_BUF_POOL].bitmap[0] = ~3; - } - nmd->deref(nmd); - NMA_UNLOCK(nmd); -} +struct netmap_mem_ops netmap_mem_global_ops = { + .nmd_get_lut = netmap_mem2_get_lut, + .nmd_get_info = netmap_mem2_get_info, + .nmd_ofstophys = netmap_mem2_ofstophys, + .nmd_config = netmap_mem_global_config, + .nmd_finalize = netmap_mem_global_finalize, + .nmd_deref = netmap_mem_global_deref, + .nmd_delete = netmap_mem_global_delete, + .nmd_if_offset = netmap_mem2_if_offset, + .nmd_if_new = netmap_mem2_if_new, + .nmd_if_delete = netmap_mem2_if_delete, + .nmd_rings_create = netmap_mem2_rings_create, + .nmd_rings_delete = netmap_mem2_rings_delete +}; +struct netmap_mem_ops netmap_mem_private_ops = { + .nmd_get_lut = netmap_mem2_get_lut, + .nmd_get_info = netmap_mem2_get_info, + .nmd_ofstophys = netmap_mem2_ofstophys, + .nmd_config = netmap_mem_private_config, + .nmd_finalize = netmap_mem_private_finalize, + .nmd_deref = netmap_mem_private_deref, + .nmd_if_offset = netmap_mem2_if_offset, + .nmd_delete = netmap_mem_private_delete, + .nmd_if_new = netmap_mem2_if_new, + .nmd_if_delete = netmap_mem2_if_delete, + .nmd_rings_create = netmap_mem2_rings_create, + .nmd_rings_delete = netmap_mem2_rings_delete +}; diff --git a/sys/dev/netmap/netmap_mem2.h b/sys/dev/netmap/netmap_mem2.h index 4c620bd4a780..ef0ff96d8e7f 100644 --- a/sys/dev/netmap/netmap_mem2.h +++ b/sys/dev/netmap/netmap_mem2.h @@ -117,9 +117,7 @@ extern struct netmap_mem_d nm_mem; -struct lut_entry* netmap_mem_get_lut(struct netmap_mem_d *); -u_int netmap_mem_get_buftotal(struct netmap_mem_d *); -size_t netmap_mem_get_bufsize(struct netmap_mem_d *); +void netmap_mem_get_lut(struct netmap_mem_d *, struct netmap_lut *); vm_paddr_t netmap_mem_ofstophys(struct netmap_mem_d *, vm_ooffset_t); int netmap_mem_finalize(struct netmap_mem_d *, struct netmap_adapter *); int netmap_mem_init(void); @@ -134,12 +132,34 @@ ssize_t netmap_mem_if_offset(struct netmap_mem_d *, const void *vaddr); struct netmap_mem_d* netmap_mem_private_new(const char *name, u_int txr, u_int txd, u_int rxr, u_int rxd, u_int extra_bufs, u_int npipes, int* error); -void netmap_mem_private_delete(struct netmap_mem_d *); +void netmap_mem_delete(struct netmap_mem_d *); + +//#define NM_DEBUG_MEM_PUTGET 1 + +#ifdef NM_DEBUG_MEM_PUTGET + +#define netmap_mem_get(nmd) \ + do { \ + __netmap_mem_get(nmd, __FUNCTION__, __LINE__); \ + } while (0) + +#define netmap_mem_put(nmd) \ + do { \ + __netmap_mem_put(nmd, __FUNCTION__, __LINE__); \ + } while (0) + +void __netmap_mem_get(struct netmap_mem_d *, const char *, int); +void __netmap_mem_put(struct netmap_mem_d *, const char *, int); +#else /* !NM_DEBUG_MEM_PUTGET */ + +void netmap_mem_get(struct netmap_mem_d *); +void netmap_mem_put(struct netmap_mem_d *); + +#endif /* !NM_DEBUG_PUTGET */ #define NETMAP_MEM_PRIVATE 0x2 /* allocator uses private address space */ #define NETMAP_MEM_IO 0x4 /* the underlying memory is mmapped I/O */ uint32_t netmap_extra_alloc(struct netmap_adapter *, uint32_t *, uint32_t n); - #endif diff --git a/sys/dev/netmap/netmap_monitor.c b/sys/dev/netmap/netmap_monitor.c index 746abb524d06..c303952417ff 100644 --- a/sys/dev/netmap/netmap_monitor.c +++ b/sys/dev/netmap/netmap_monitor.c @@ -28,7 +28,7 @@ * * Monitors * - * netmap monitors can be used to do zero-copy monitoring of network traffic + * netmap monitors can be used to do monitoring of network traffic * on another adapter, when the latter adapter is working in netmap mode. * * Monitors offer to userspace the same interface as any other netmap port, @@ -38,8 +38,24 @@ * monitored adapter. During registration, the user can choose if she wants * to intercept tx only, rx only, or both tx and rx traffic. * - * The monitor only sees the frames after they have been consumed in the - * monitored adapter: + * If the monitor is not able to cope with the stream of frames, excess traffic + * will be dropped. + * + * If the monitored adapter leaves netmap mode, the monitor has to be restarted. + * + * Monitors can be either zero-copy or copy-based. + * + * Copy monitors see the frames before they are consumed: + * + * - For tx traffic, this is when the application sends them, before they are + * passed down to the adapter. + * + * - For rx traffic, this is when they are received by the adapter, before + * they are sent up to the application, if any (note that, if no + * application is reading from a monitored ring, the ring will eventually + * fill up and traffic will stop). + * + * Zero-copy monitors only see the frames after they have been consumed: * * - For tx traffic, this is after the slots containing the frames have been * marked as free. Note that this may happen at a considerably delay after @@ -49,11 +65,9 @@ * has released them. In most cases, the consumer is a userspace * application which may have modified the frame contents. * - * If the monitor is not able to cope with the stream of frames, excess traffic - * will be dropped. - * - * Each ring can be monitored by at most one monitor. This may change in the - * future, if we implement monitor chaining. + * Several copy monitors may be active on any ring. Zero-copy monitors, + * instead, need exclusive access to each of the monitored rings. This may + * change in the future, if we implement zero-copy monitor chaining. * */ @@ -105,34 +119,320 @@ #define NM_MONITOR_MAXSLOTS 4096 -/* monitor works by replacing the nm_sync callbacks in the monitored rings. - * The actions to be performed are the same on both tx and rx rings, so we - * have collected them here +/* + ******************************************************************** + * functions common to both kind of monitors + ******************************************************************** + */ + +/* nm_sync callback for the monitor's own tx rings. + * This makes no sense and always returns error */ static int -netmap_monitor_parent_sync(struct netmap_kring *kring, int flags, u_int* ringptr) +netmap_monitor_txsync(struct netmap_kring *kring, int flags) { - struct netmap_monitor_adapter *mna = kring->monitor; - struct netmap_kring *mkring = &mna->up.rx_rings[kring->ring_id]; - struct netmap_ring *ring = kring->ring, *mring = mkring->ring; - int error; - int rel_slots, free_slots, busy; + RD(1, "%s %x", kring->name, flags); + return EIO; +} + +/* nm_sync callback for the monitor's own rx rings. + * Note that the lock in netmap_zmon_parent_sync only protects + * writers among themselves. Synchronization between writers + * (i.e., netmap_zmon_parent_txsync and netmap_zmon_parent_rxsync) + * and readers (i.e., netmap_zmon_rxsync) relies on memory barriers. + */ +static int +netmap_monitor_rxsync(struct netmap_kring *kring, int flags) +{ + ND("%s %x", kring->name, flags); + kring->nr_hwcur = kring->rcur; + mb(); + return 0; +} + +/* nm_krings_create callbacks for monitors. + * We could use the default netmap_hw_krings_zmon, but + * we don't need the mbq. + */ +static int +netmap_monitor_krings_create(struct netmap_adapter *na) +{ + return netmap_krings_create(na, 0); +} + +/* nm_krings_delete callback for monitors */ +static void +netmap_monitor_krings_delete(struct netmap_adapter *na) +{ + netmap_krings_delete(na); +} + + +static u_int +nm_txrx2flag(enum txrx t) +{ + return (t == NR_RX ? NR_MONITOR_RX : NR_MONITOR_TX); +} + +/* allocate the monitors array in the monitored kring */ +static int +nm_monitor_alloc(struct netmap_kring *kring, u_int n) +{ + size_t len; + struct netmap_kring **nm; + + if (n <= kring->max_monitors) + /* we already have more entries that requested */ + return 0; + + len = sizeof(struct netmap_kring *) * n; + nm = realloc(kring->monitors, len, M_DEVBUF, M_NOWAIT | M_ZERO); + if (nm == NULL) + return ENOMEM; + + kring->monitors = nm; + kring->max_monitors = n; + + return 0; +} + +/* deallocate the parent array in the parent adapter */ +static void +nm_monitor_dealloc(struct netmap_kring *kring) +{ + if (kring->monitors) { + if (kring->n_monitors > 0) { + D("freeing not empty monitor array for %s (%d dangling monitors)!", kring->name, + kring->n_monitors); + } + free(kring->monitors, M_DEVBUF); + kring->monitors = NULL; + kring->max_monitors = 0; + kring->n_monitors = 0; + } +} + +/* + * monitors work by replacing the nm_sync() and possibly the + * nm_notify() callbacks in the monitored rings. + */ +static int netmap_zmon_parent_txsync(struct netmap_kring *, int); +static int netmap_zmon_parent_rxsync(struct netmap_kring *, int); +static int netmap_monitor_parent_txsync(struct netmap_kring *, int); +static int netmap_monitor_parent_rxsync(struct netmap_kring *, int); +static int netmap_monitor_parent_notify(struct netmap_kring *, int); + + +/* add the monitor mkring to the list of monitors of kring. + * If this is the first monitor, intercept the callbacks + */ +static int +netmap_monitor_add(struct netmap_kring *mkring, struct netmap_kring *kring, int zcopy) +{ + int error = 0; + + /* sinchronize with concurrently running nm_sync()s */ + nm_kr_get(kring); + /* make sure the monitor array exists and is big enough */ + error = nm_monitor_alloc(kring, kring->n_monitors + 1); + if (error) + goto out; + kring->monitors[kring->n_monitors] = mkring; + mkring->mon_pos = kring->n_monitors; + kring->n_monitors++; + if (kring->n_monitors == 1) { + /* this is the first monitor, intercept callbacks */ + D("%s: intercept callbacks on %s", mkring->name, kring->name); + kring->mon_sync = kring->nm_sync; + /* zcopy monitors do not override nm_notify(), but + * we save the original one regardless, so that + * netmap_monitor_del() does not need to know the + * monitor type + */ + kring->mon_notify = kring->nm_notify; + if (kring->tx == NR_TX) { + kring->nm_sync = (zcopy ? netmap_zmon_parent_txsync : + netmap_monitor_parent_txsync); + } else { + kring->nm_sync = (zcopy ? netmap_zmon_parent_rxsync : + netmap_monitor_parent_rxsync); + if (!zcopy) { + /* also intercept notify */ + kring->nm_notify = netmap_monitor_parent_notify; + kring->mon_tail = kring->nr_hwtail; + } + } + } + +out: + nm_kr_put(kring); + return error; +} + + +/* remove the monitor mkring from the list of monitors of kring. + * If this is the last monitor, restore the original callbacks + */ +static void +netmap_monitor_del(struct netmap_kring *mkring, struct netmap_kring *kring) +{ + /* sinchronize with concurrently running nm_sync()s */ + nm_kr_get(kring); + kring->n_monitors--; + if (mkring->mon_pos != kring->n_monitors) { + kring->monitors[mkring->mon_pos] = kring->monitors[kring->n_monitors]; + kring->monitors[mkring->mon_pos]->mon_pos = mkring->mon_pos; + } + kring->monitors[kring->n_monitors] = NULL; + if (kring->n_monitors == 0) { + /* this was the last monitor, restore callbacks and delete monitor array */ + D("%s: restoring sync on %s: %p", mkring->name, kring->name, kring->mon_sync); + kring->nm_sync = kring->mon_sync; + kring->mon_sync = NULL; + if (kring->tx == NR_RX) { + D("%s: restoring notify on %s: %p", + mkring->name, kring->name, kring->mon_notify); + kring->nm_notify = kring->mon_notify; + kring->mon_notify = NULL; + } + nm_monitor_dealloc(kring); + } + nm_kr_put(kring); +} + + +/* This is called when the monitored adapter leaves netmap mode + * (see netmap_do_unregif). + * We need to notify the monitors that the monitored rings are gone. + * We do this by setting their mna->priv.np_na to NULL. + * Note that the rings are already stopped when this happens, so + * no monitor ring callback can be active. + */ +void +netmap_monitor_stop(struct netmap_adapter *na) +{ + enum txrx t; + + for_rx_tx(t) { + u_int i; + + for (i = 0; i < nma_get_nrings(na, t); i++) { + struct netmap_kring *kring = &NMR(na, t)[i]; + u_int j; + + for (j = 0; j < kring->n_monitors; j++) { + struct netmap_kring *mkring = + kring->monitors[j]; + struct netmap_monitor_adapter *mna = + (struct netmap_monitor_adapter *)mkring->na; + /* forget about this adapter */ + netmap_adapter_put(mna->priv.np_na); + mna->priv.np_na = NULL; + } + } + } +} + + +/* common functions for the nm_register() callbacks of both kind of + * monitors. + */ +static int +netmap_monitor_reg_common(struct netmap_adapter *na, int onoff, int zmon) +{ + struct netmap_monitor_adapter *mna = + (struct netmap_monitor_adapter *)na; + struct netmap_priv_d *priv = &mna->priv; + struct netmap_adapter *pna = priv->np_na; + struct netmap_kring *kring, *mkring; + int i; + enum txrx t; + + ND("%p: onoff %d", na, onoff); + if (onoff) { + if (pna == NULL) { + /* parent left netmap mode, fatal */ + D("%s: internal error", na->name); + return ENXIO; + } + for_rx_tx(t) { + if (mna->flags & nm_txrx2flag(t)) { + for (i = priv->np_qfirst[t]; i < priv->np_qlast[t]; i++) { + kring = &NMR(pna, t)[i]; + mkring = &na->rx_rings[i]; + netmap_monitor_add(mkring, kring, zmon); + } + } + } + na->na_flags |= NAF_NETMAP_ON; + } else { + if (pna == NULL) { + D("%s: parent left netmap mode, nothing to restore", na->name); + return 0; + } + na->na_flags &= ~NAF_NETMAP_ON; + for_rx_tx(t) { + if (mna->flags & nm_txrx2flag(t)) { + for (i = priv->np_qfirst[t]; i < priv->np_qlast[t]; i++) { + kring = &NMR(pna, t)[i]; + mkring = &na->rx_rings[i]; + netmap_monitor_del(mkring, kring); + } + } + } + } + return 0; +} + +/* + **************************************************************** + * functions specific for zero-copy monitors + **************************************************************** + */ + +/* + * Common function for both zero-copy tx and rx nm_sync() + * callbacks + */ +static int +netmap_zmon_parent_sync(struct netmap_kring *kring, int flags, enum txrx tx) +{ + struct netmap_kring *mkring = kring->monitors[0]; + struct netmap_ring *ring = kring->ring, *mring; + int error = 0; + int rel_slots, free_slots, busy, sent = 0; u_int beg, end, i; u_int lim = kring->nkr_num_slots - 1, - mlim = mkring->nkr_num_slots - 1; + mlim; // = mkring->nkr_num_slots - 1; + + if (mkring == NULL) { + RD(5, "NULL monitor on %s", kring->name); + return 0; + } + mring = mkring->ring; + mlim = mkring->nkr_num_slots - 1; /* get the relased slots (rel_slots) */ - beg = *ringptr; - error = kring->save_sync(kring, flags); - if (error) - return error; - end = *ringptr; + if (tx == NR_TX) { + beg = kring->nr_hwtail; + error = kring->mon_sync(kring, flags); + if (error) + return error; + end = kring->nr_hwtail; + } else { /* NR_RX */ + beg = kring->nr_hwcur; + end = kring->rhead; + } + rel_slots = end - beg; if (rel_slots < 0) rel_slots += kring->nkr_num_slots; if (!rel_slots) { - return 0; + /* no released slots, but we still need + * to call rxsync if this is a rx ring + */ + goto out_rxsync; } /* we need to lock the monitor receive ring, since it @@ -147,19 +447,18 @@ netmap_monitor_parent_sync(struct netmap_kring *kring, int flags, u_int* ringptr busy += mkring->nkr_num_slots; free_slots = mlim - busy; - if (!free_slots) { - mtx_unlock(&mkring->q_lock); - return 0; - } + if (!free_slots) + goto out; /* swap min(free_slots, rel_slots) slots */ if (free_slots < rel_slots) { beg += (rel_slots - free_slots); - if (beg > lim) - beg = 0; + if (beg >= kring->nkr_num_slots) + beg -= kring->nkr_num_slots; rel_slots = free_slots; } + sent = rel_slots; for ( ; rel_slots; rel_slots--) { struct netmap_slot *s = &ring->slot[beg]; struct netmap_slot *ms = &mring->slot[i]; @@ -168,6 +467,7 @@ netmap_monitor_parent_sync(struct netmap_kring *kring, int flags, u_int* ringptr tmp = ms->buf_idx; ms->buf_idx = s->buf_idx; s->buf_idx = tmp; + ND(5, "beg %d buf_idx %d", beg, tmp); tmp = ms->len; ms->len = s->len; @@ -182,143 +482,196 @@ netmap_monitor_parent_sync(struct netmap_kring *kring, int flags, u_int* ringptr mb(); mkring->nr_hwtail = i; +out: mtx_unlock(&mkring->q_lock); - /* notify the new frames to the monitor */ - mna->up.nm_notify(&mna->up, mkring->ring_id, NR_RX, 0); - return 0; + + if (sent) { + /* notify the new frames to the monitor */ + mkring->nm_notify(mkring, 0); + } + +out_rxsync: + if (tx == NR_RX) + error = kring->mon_sync(kring, flags); + + return error; +} + +/* callback used to replace the nm_sync callback in the monitored tx rings */ +static int +netmap_zmon_parent_txsync(struct netmap_kring *kring, int flags) +{ + ND("%s %x", kring->name, flags); + return netmap_zmon_parent_sync(kring, flags, NR_TX); +} + +/* callback used to replace the nm_sync callback in the monitored rx rings */ +static int +netmap_zmon_parent_rxsync(struct netmap_kring *kring, int flags) +{ + ND("%s %x", kring->name, flags); + return netmap_zmon_parent_sync(kring, flags, NR_RX); +} + + +static int +netmap_zmon_reg(struct netmap_adapter *na, int onoff) +{ + return netmap_monitor_reg_common(na, onoff, 1 /* zcopy */); +} + +/* nm_dtor callback for monitors */ +static void +netmap_zmon_dtor(struct netmap_adapter *na) +{ + struct netmap_monitor_adapter *mna = + (struct netmap_monitor_adapter *)na; + struct netmap_priv_d *priv = &mna->priv; + struct netmap_adapter *pna = priv->np_na; + + netmap_adapter_put(pna); +} + +/* + **************************************************************** + * functions specific for copy monitors + **************************************************************** + */ + +static void +netmap_monitor_parent_sync(struct netmap_kring *kring, u_int first_new, int new_slots) +{ + u_int j; + + for (j = 0; j < kring->n_monitors; j++) { + struct netmap_kring *mkring = kring->monitors[j]; + u_int i, mlim, beg; + int free_slots, busy, sent = 0, m; + u_int lim = kring->nkr_num_slots - 1; + struct netmap_ring *ring = kring->ring, *mring = mkring->ring; + u_int max_len = NETMAP_BUF_SIZE(mkring->na); + + mlim = mkring->nkr_num_slots - 1; + + /* we need to lock the monitor receive ring, since it + * is the target of bot tx and rx traffic from the monitored + * adapter + */ + mtx_lock(&mkring->q_lock); + /* get the free slots available on the monitor ring */ + i = mkring->nr_hwtail; + busy = i - mkring->nr_hwcur; + if (busy < 0) + busy += mkring->nkr_num_slots; + free_slots = mlim - busy; + + if (!free_slots) + goto out; + + /* copy min(free_slots, new_slots) slots */ + m = new_slots; + beg = first_new; + if (free_slots < m) { + beg += (m - free_slots); + if (beg >= kring->nkr_num_slots) + beg -= kring->nkr_num_slots; + m = free_slots; + } + + for ( ; m; m--) { + struct netmap_slot *s = &ring->slot[beg]; + struct netmap_slot *ms = &mring->slot[i]; + u_int copy_len = s->len; + char *src = NMB(kring->na, s), + *dst = NMB(mkring->na, ms); + + if (unlikely(copy_len > max_len)) { + RD(5, "%s->%s: truncating %d to %d", kring->name, + mkring->name, copy_len, max_len); + copy_len = max_len; + } + + memcpy(dst, src, copy_len); + ms->len = copy_len; + sent++; + + beg = nm_next(beg, lim); + i = nm_next(i, mlim); + } + mb(); + mkring->nr_hwtail = i; + out: + mtx_unlock(&mkring->q_lock); + + if (sent) { + /* notify the new frames to the monitor */ + mkring->nm_notify(mkring, 0); + } + } } /* callback used to replace the nm_sync callback in the monitored tx rings */ static int netmap_monitor_parent_txsync(struct netmap_kring *kring, int flags) { - ND("%s %x", kring->name, flags); - return netmap_monitor_parent_sync(kring, flags, &kring->nr_hwtail); + u_int first_new; + int new_slots; + + /* get the new slots */ + first_new = kring->nr_hwcur; + new_slots = kring->rhead - first_new; + if (new_slots < 0) + new_slots += kring->nkr_num_slots; + if (new_slots) + netmap_monitor_parent_sync(kring, first_new, new_slots); + return kring->mon_sync(kring, flags); } /* callback used to replace the nm_sync callback in the monitored rx rings */ static int netmap_monitor_parent_rxsync(struct netmap_kring *kring, int flags) { - ND("%s %x", kring->name, flags); - return netmap_monitor_parent_sync(kring, flags, &kring->rcur); + u_int first_new; + int new_slots, error; + + /* get the new slots */ + error = kring->mon_sync(kring, flags); + if (error) + return error; + first_new = kring->mon_tail; + new_slots = kring->nr_hwtail - first_new; + if (new_slots < 0) + new_slots += kring->nkr_num_slots; + if (new_slots) + netmap_monitor_parent_sync(kring, first_new, new_slots); + kring->mon_tail = kring->nr_hwtail; + return 0; } -/* nm_sync callback for the monitor's own tx rings. - * This makes no sense and always returns error - */ +/* callback used to replace the nm_notify() callback in the monitored rx rings */ static int -netmap_monitor_txsync(struct netmap_kring *kring, int flags) +netmap_monitor_parent_notify(struct netmap_kring *kring, int flags) { - D("%s %x", kring->name, flags); - return EIO; -} - -/* nm_sync callback for the monitor's own rx rings. - * Note that the lock in netmap_monitor_parent_sync only protects - * writers among themselves. Synchronization between writers - * (i.e., netmap_monitor_parent_txsync and netmap_monitor_parent_rxsync) - * and readers (i.e., netmap_monitor_rxsync) relies on memory barriers. - */ -static int -netmap_monitor_rxsync(struct netmap_kring *kring, int flags) -{ - ND("%s %x", kring->name, flags); - kring->nr_hwcur = kring->rcur; - mb(); - nm_rxsync_finalize(kring); - return 0; -} - -/* nm_krings_create callbacks for monitors. - * We could use the default netmap_hw_krings_monitor, but - * we don't need the mbq. - */ -static int -netmap_monitor_krings_create(struct netmap_adapter *na) -{ - return netmap_krings_create(na, 0); + ND(5, "%s %x", kring->name, flags); + /* ?xsync callbacks have tryget called by their callers + * (NIOCREGIF and poll()), but here we have to call it + * by ourself + */ + if (nm_kr_tryget(kring)) + goto out; + netmap_monitor_parent_rxsync(kring, NAF_FORCE_READ); + nm_kr_put(kring); +out: + return kring->mon_notify(kring, flags); } -/* nm_register callback for monitors. - * - * On registration, replace the nm_sync callbacks in the monitored - * rings with our own, saving the previous ones in the monitored - * rings themselves, where they are used by netmap_monitor_parent_sync. - * - * On de-registration, restore the original callbacks. We need to - * stop traffic while we are doing this, since the monitored adapter may - * have already started executing a netmap_monitor_parent_sync - * and may not like the kring->save_sync pointer to become NULL. - */ static int netmap_monitor_reg(struct netmap_adapter *na, int onoff) { - struct netmap_monitor_adapter *mna = - (struct netmap_monitor_adapter *)na; - struct netmap_priv_d *priv = &mna->priv; - struct netmap_adapter *pna = priv->np_na; - struct netmap_kring *kring; - int i; - - ND("%p: onoff %d", na, onoff); - if (onoff) { - if (!nm_netmap_on(pna)) { - /* parent left netmap mode, fatal */ - return ENXIO; - } - if (mna->flags & NR_MONITOR_TX) { - for (i = priv->np_txqfirst; i < priv->np_txqlast; i++) { - kring = &pna->tx_rings[i]; - kring->save_sync = kring->nm_sync; - kring->nm_sync = netmap_monitor_parent_txsync; - } - } - if (mna->flags & NR_MONITOR_RX) { - for (i = priv->np_rxqfirst; i < priv->np_rxqlast; i++) { - kring = &pna->rx_rings[i]; - kring->save_sync = kring->nm_sync; - kring->nm_sync = netmap_monitor_parent_rxsync; - } - } - na->na_flags |= NAF_NETMAP_ON; - } else { - if (!nm_netmap_on(pna)) { - /* parent left netmap mode, nothing to restore */ - return 0; - } - na->na_flags &= ~NAF_NETMAP_ON; - if (mna->flags & NR_MONITOR_TX) { - for (i = priv->np_txqfirst; i < priv->np_txqlast; i++) { - netmap_set_txring(pna, i, 1 /* stopped */); - kring = &pna->tx_rings[i]; - kring->nm_sync = kring->save_sync; - kring->save_sync = NULL; - netmap_set_txring(pna, i, 0 /* enabled */); - } - } - if (mna->flags & NR_MONITOR_RX) { - for (i = priv->np_rxqfirst; i < priv->np_rxqlast; i++) { - netmap_set_rxring(pna, i, 1 /* stopped */); - kring = &pna->rx_rings[i]; - kring->nm_sync = kring->save_sync; - kring->save_sync = NULL; - netmap_set_rxring(pna, i, 0 /* enabled */); - } - } - } - return 0; -} -/* nm_krings_delete callback for monitors */ -static void -netmap_monitor_krings_delete(struct netmap_adapter *na) -{ - netmap_krings_delete(na); + return netmap_monitor_reg_common(na, onoff, 0 /* no zcopy */); } - -/* nm_dtor callback for monitors */ static void netmap_monitor_dtor(struct netmap_adapter *na) { @@ -326,22 +679,7 @@ netmap_monitor_dtor(struct netmap_adapter *na) (struct netmap_monitor_adapter *)na; struct netmap_priv_d *priv = &mna->priv; struct netmap_adapter *pna = priv->np_na; - int i; - ND("%p", na); - if (nm_netmap_on(pna)) { - /* parent still in netmap mode, mark its krings as free */ - if (mna->flags & NR_MONITOR_TX) { - for (i = priv->np_txqfirst; i < priv->np_txqlast; i++) { - pna->tx_rings[i].monitor = NULL; - } - } - if (mna->flags & NR_MONITOR_RX) { - for (i = priv->np_rxqfirst; i < priv->np_rxqlast; i++) { - pna->rx_rings[i].monitor = NULL; - } - } - } netmap_adapter_put(pna); } @@ -354,6 +692,9 @@ netmap_get_monitor_na(struct nmreq *nmr, struct netmap_adapter **na, int create) struct netmap_adapter *pna; /* parent adapter */ struct netmap_monitor_adapter *mna; int i, error; + enum txrx t; + int zcopy = (nmr->nr_flags & NR_ZCOPY_MON); + char monsuff[10] = ""; if ((nmr->nr_flags & (NR_MONITOR_TX | NR_MONITOR_RX)) == 0) { ND("not a monitor"); @@ -400,44 +741,65 @@ netmap_get_monitor_na(struct nmreq *nmr, struct netmap_adapter **na, int create) D("ringid error"); goto put_out; } - if (nmr->nr_flags & NR_MONITOR_TX) { - for (i = mna->priv.np_txqfirst; i < mna->priv.np_txqlast; i++) { - struct netmap_kring *kring = &pna->tx_rings[i]; - if (kring->monitor) { - error = EBUSY; - D("ring busy"); - goto release_out; - } - kring->monitor = mna; - } - } - if (nmr->nr_flags & NR_MONITOR_RX) { - for (i = mna->priv.np_rxqfirst; i < mna->priv.np_rxqlast; i++) { - struct netmap_kring *kring = &pna->rx_rings[i]; - if (kring->monitor) { - error = EBUSY; - D("ring busy"); - goto release_out; - } - kring->monitor = mna; - } + if (mna->priv.np_qlast[NR_TX] - mna->priv.np_qfirst[NR_TX] == 1) { + snprintf(monsuff, 10, "-%d", mna->priv.np_qfirst[NR_TX]); } + snprintf(mna->up.name, sizeof(mna->up.name), "%s%s/%s%s%s", pna->name, + monsuff, + zcopy ? "z" : "", + (nmr->nr_flags & NR_MONITOR_RX) ? "r" : "", + (nmr->nr_flags & NR_MONITOR_TX) ? "t" : ""); - snprintf(mna->up.name, sizeof(mna->up.name), "mon:%s", pna->name); + if (zcopy) { + /* zero copy monitors need exclusive access to the monitored rings */ + for_rx_tx(t) { + if (! (nmr->nr_flags & nm_txrx2flag(t))) + continue; + for (i = mna->priv.np_qfirst[t]; i < mna->priv.np_qlast[t]; i++) { + struct netmap_kring *kring = &NMR(pna, t)[i]; + if (kring->n_monitors > 0) { + error = EBUSY; + D("ring %s already monitored by %s", kring->name, + kring->monitors[0]->name); + goto put_out; + } + } + } + mna->up.nm_register = netmap_zmon_reg; + mna->up.nm_dtor = netmap_zmon_dtor; + /* to have zero copy, we need to use the same memory allocator + * as the monitored port + */ + mna->up.nm_mem = pna->nm_mem; + mna->up.na_lut = pna->na_lut; + } else { + /* normal monitors are incompatible with zero copy ones */ + for_rx_tx(t) { + if (! (nmr->nr_flags & nm_txrx2flag(t))) + continue; + for (i = mna->priv.np_qfirst[t]; i < mna->priv.np_qlast[t]; i++) { + struct netmap_kring *kring = &NMR(pna, t)[i]; + if (kring->n_monitors > 0 && + kring->monitors[0]->na->nm_register == netmap_zmon_reg) + { + error = EBUSY; + D("ring busy"); + goto put_out; + } + } + } + mna->up.nm_rxsync = netmap_monitor_rxsync; + mna->up.nm_register = netmap_monitor_reg; + mna->up.nm_dtor = netmap_monitor_dtor; + } /* the monitor supports the host rings iff the parent does */ mna->up.na_flags = (pna->na_flags & NAF_HOST_RINGS); + /* a do-nothing txsync: monitors cannot be used to inject packets */ mna->up.nm_txsync = netmap_monitor_txsync; mna->up.nm_rxsync = netmap_monitor_rxsync; - mna->up.nm_register = netmap_monitor_reg; - mna->up.nm_dtor = netmap_monitor_dtor; mna->up.nm_krings_create = netmap_monitor_krings_create; mna->up.nm_krings_delete = netmap_monitor_krings_delete; - mna->up.nm_mem = pna->nm_mem; - mna->up.na_lut = pna->na_lut; - mna->up.na_lut_objtotal = pna->na_lut_objtotal; - mna->up.na_lut_objsize = pna->na_lut_objsize; - mna->up.num_tx_rings = 1; // XXX we don't need it, but field can't be zero /* we set the number of our rx_rings to be max(num_rx_rings, num_rx_rings) * in the parent @@ -458,7 +820,7 @@ netmap_get_monitor_na(struct nmreq *nmr, struct netmap_adapter **na, int create) error = netmap_attach_common(&mna->up); if (error) { D("attach_common error"); - goto release_out; + goto put_out; } /* remember the traffic directions we have to monitor */ @@ -478,16 +840,6 @@ netmap_get_monitor_na(struct nmreq *nmr, struct netmap_adapter **na, int create) return 0; -release_out: - D("monitor error"); - for (i = mna->priv.np_txqfirst; i < mna->priv.np_txqlast; i++) { - if (pna->tx_rings[i].monitor == mna) - pna->tx_rings[i].monitor = NULL; - } - for (i = mna->priv.np_rxqfirst; i < mna->priv.np_rxqlast; i++) { - if (pna->rx_rings[i].monitor == mna) - pna->rx_rings[i].monitor = NULL; - } put_out: netmap_adapter_put(pna); free(mna, M_DEVBUF); diff --git a/sys/dev/netmap/netmap_pipe.c b/sys/dev/netmap/netmap_pipe.c index 64828670c35b..67e840248c88 100644 --- a/sys/dev/netmap/netmap_pipe.c +++ b/sys/dev/netmap/netmap_pipe.c @@ -72,51 +72,31 @@ #define NM_PIPE_MAXSLOTS 4096 -int netmap_default_pipes = 0; /* default number of pipes for each nic */ +int netmap_default_pipes = 0; /* ignored, kept for compatibility */ SYSCTL_DECL(_dev_netmap); SYSCTL_INT(_dev_netmap, OID_AUTO, default_pipes, CTLFLAG_RW, &netmap_default_pipes, 0 , ""); /* allocate the pipe array in the parent adapter */ -int -netmap_pipe_alloc(struct netmap_adapter *na, struct nmreq *nmr) +static int +nm_pipe_alloc(struct netmap_adapter *na, u_int npipes) { size_t len; - int mode = nmr->nr_flags & NR_REG_MASK; - u_int npipes; + struct netmap_pipe_adapter **npa; - if (mode == NR_REG_PIPE_MASTER || mode == NR_REG_PIPE_SLAVE) { - /* this is for our parent, not for us */ + if (npipes <= na->na_max_pipes) + /* we already have more entries that requested */ return 0; - } + + if (npipes < na->na_next_pipe || npipes > NM_MAXPIPES) + return EINVAL; - /* TODO: we can resize the array if the new - * request can accomodate the already existing pipes - */ - if (na->na_pipes) { - nmr->nr_arg1 = na->na_max_pipes; - return 0; - } - - npipes = nmr->nr_arg1; - if (npipes == 0) - npipes = netmap_default_pipes; - nm_bound_var(&npipes, 0, 0, NM_MAXPIPES, NULL); - - if (npipes == 0) { - /* really zero, nothing to alloc */ - goto out; - } - - len = sizeof(struct netmap_pipe_adapter *) * npipes; - na->na_pipes = malloc(len, M_DEVBUF, M_NOWAIT | M_ZERO); - if (na->na_pipes == NULL) + len = sizeof(struct netmap_pipe_adapter *) * npipes; + npa = realloc(na->na_pipes, len, M_DEVBUF, M_NOWAIT | M_ZERO); + if (npa == NULL) return ENOMEM; + na->na_pipes = npa; na->na_max_pipes = npipes; - na->na_next_pipe = 0; - -out: - nmr->nr_arg1 = npipes; return 0; } @@ -126,7 +106,10 @@ void netmap_pipe_dealloc(struct netmap_adapter *na) { if (na->na_pipes) { - ND("freeing pipes for %s", na->name); + if (na->na_next_pipe > 0) { + D("freeing not empty pipe array for %s (%d dangling pipes)!", na->name, + na->na_next_pipe); + } free(na->na_pipes, M_DEVBUF); na->na_pipes = NULL; na->na_max_pipes = 0; @@ -155,8 +138,10 @@ static int netmap_pipe_add(struct netmap_adapter *parent, struct netmap_pipe_adapter *na) { if (parent->na_next_pipe >= parent->na_max_pipes) { - D("%s: no space left for pipes", parent->name); - return ENOMEM; + u_int npipes = parent->na_max_pipes ? 2*parent->na_max_pipes : 2; + int error = nm_pipe_alloc(parent, npipes); + if (error) + return error; } parent->na_pipes[parent->na_next_pipe] = na; @@ -172,8 +157,10 @@ netmap_pipe_remove(struct netmap_adapter *parent, struct netmap_pipe_adapter *na u_int n; n = --parent->na_next_pipe; if (n != na->parent_slot) { - parent->na_pipes[na->parent_slot] = - parent->na_pipes[n]; + struct netmap_pipe_adapter **p = + &parent->na_pipes[na->parent_slot]; + *p = parent->na_pipes[n]; + (*p)->parent_slot = na->parent_slot; } parent->na_pipes[n] = NULL; } @@ -208,7 +195,6 @@ netmap_pipe_txsync(struct netmap_kring *txkring, int flags) if (limit == 0) { /* either the rxring is full, or nothing to send */ - nm_txsync_finalize(txkring); /* actually useless */ return 0; } @@ -222,7 +208,9 @@ netmap_pipe_txsync(struct netmap_kring *txkring, int flags) *rs = *ts; *ts = tmp; - /* no need to report the buffer change */ + /* report the buffer change */ + ts->flags |= NS_BUF_CHANGED; + rs->flags |= NS_BUF_CHANGED; j = nm_next(j, lim_rx); k = nm_next(k, lim_tx); @@ -233,12 +221,11 @@ netmap_pipe_txsync(struct netmap_kring *txkring, int flags) txkring->nr_hwcur = k; txkring->nr_hwtail = nm_prev(k, lim_tx); - nm_txsync_finalize(txkring); ND(2, "after: hwcur %d hwtail %d cur %d head %d tail %d j %d", txkring->nr_hwcur, txkring->nr_hwtail, txkring->rcur, txkring->rhead, txkring->rtail, j); mb(); /* make sure rxkring->nr_hwtail is updated before notifying */ - rxkring->na->nm_notify(rxkring->na, rxkring->ring_id, NR_RX, 0); + rxkring->nm_notify(rxkring, 0); return 0; } @@ -254,12 +241,11 @@ netmap_pipe_rxsync(struct netmap_kring *rxkring, int flags) ND(5, "hwcur %d hwtail %d cur %d head %d tail %d", rxkring->nr_hwcur, rxkring->nr_hwtail, rxkring->rcur, rxkring->rhead, rxkring->rtail); mb(); /* paired with the first mb() in txsync */ - nm_rxsync_finalize(rxkring); if (oldhwcur != rxkring->nr_hwcur) { /* we have released some slots, notify the other end */ mb(); /* make sure nr_hwcur is updated before notifying */ - txkring->na->nm_notify(txkring->na, txkring->ring_id, NR_TX, 0); + txkring->nm_notify(txkring, 0); } return 0; } @@ -318,11 +304,13 @@ netmap_pipe_krings_create(struct netmap_adapter *na) (struct netmap_pipe_adapter *)na; struct netmap_adapter *ona = &pna->peer->up; int error = 0; + enum txrx t; + if (pna->peer_ref) { int i; /* case 1) above */ - D("%p: case 1, create everything", na); + ND("%p: case 1, create everything", na); error = netmap_krings_create(na, 0); if (error) goto err; @@ -338,10 +326,10 @@ netmap_pipe_krings_create(struct netmap_adapter *na) goto del_krings1; /* update our hidden ring pointers */ - for (i = 0; i < na->num_tx_rings + 1; i++) - na->tx_rings[i].save_ring = na->tx_rings[i].ring; - for (i = 0; i < na->num_rx_rings + 1; i++) - na->rx_rings[i].save_ring = na->rx_rings[i].ring; + for_rx_tx(t) { + for (i = 0; i < nma_get_nrings(na, t) + 1; i++) + NMR(na, t)[i].save_ring = NMR(na, t)[i].ring; + } /* now, create krings and rings of the other end */ error = netmap_krings_create(ona, 0); @@ -352,27 +340,28 @@ netmap_pipe_krings_create(struct netmap_adapter *na) if (error) goto del_krings2; - for (i = 0; i < ona->num_tx_rings + 1; i++) - ona->tx_rings[i].save_ring = ona->tx_rings[i].ring; - for (i = 0; i < ona->num_rx_rings + 1; i++) - ona->rx_rings[i].save_ring = ona->rx_rings[i].ring; + for_rx_tx(t) { + for (i = 0; i < nma_get_nrings(ona, t) + 1; i++) + NMR(ona, t)[i].save_ring = NMR(ona, t)[i].ring; + } /* cross link the krings */ - for (i = 0; i < na->num_tx_rings; i++) { - na->tx_rings[i].pipe = pna->peer->up.rx_rings + i; - na->rx_rings[i].pipe = pna->peer->up.tx_rings + i; - pna->peer->up.tx_rings[i].pipe = na->rx_rings + i; - pna->peer->up.rx_rings[i].pipe = na->tx_rings + i; + for_rx_tx(t) { + enum txrx r= nm_txrx_swap(t); /* swap NR_TX <-> NR_RX */ + for (i = 0; i < nma_get_nrings(na, t); i++) { + NMR(na, t)[i].pipe = NMR(&pna->peer->up, r) + i; + NMR(&pna->peer->up, r)[i].pipe = NMR(na, t) + i; + } } } else { int i; /* case 2) above */ /* recover the hidden rings */ ND("%p: case 2, hidden rings", na); - for (i = 0; i < na->num_tx_rings + 1; i++) - na->tx_rings[i].ring = na->tx_rings[i].save_ring; - for (i = 0; i < na->num_rx_rings + 1; i++) - na->rx_rings[i].ring = na->rx_rings[i].save_ring; + for_rx_tx(t) { + for (i = 0; i < nma_get_nrings(na, t) + 1; i++) + NMR(na, t)[i].ring = NMR(na, t)[i].save_ring; + } } return 0; @@ -423,6 +412,8 @@ netmap_pipe_reg(struct netmap_adapter *na, int onoff) { struct netmap_pipe_adapter *pna = (struct netmap_pipe_adapter *)na; + enum txrx t; + ND("%p: onoff %d", na, onoff); if (onoff) { na->na_flags |= NAF_NETMAP_ON; @@ -443,11 +434,10 @@ netmap_pipe_reg(struct netmap_adapter *na, int onoff) netmap_adapter_get(na); pna->peer->peer_ref = 1; /* hide our rings from netmap_mem_rings_delete */ - for (i = 0; i < na->num_tx_rings + 1; i++) { - na->tx_rings[i].ring = NULL; - } - for (i = 0; i < na->num_rx_rings + 1; i++) { - na->rx_rings[i].ring = NULL; + for_rx_tx(t) { + for (i = 0; i < nma_get_nrings(na, t) + 1; i++) { + NMR(na, t)[i].ring = NULL; + } } } return 0; @@ -481,6 +471,7 @@ netmap_pipe_krings_delete(struct netmap_adapter *na) (struct netmap_pipe_adapter *)na; struct netmap_adapter *ona; /* na of the other end */ int i; + enum txrx t; if (!pna->peer_ref) { ND("%p: case 2, kept alive by peer", na); @@ -496,10 +487,10 @@ netmap_pipe_krings_delete(struct netmap_adapter *na) * cleanup-after-error path */ return; } - for (i = 0; i < ona->num_tx_rings + 1; i++) - ona->tx_rings[i].ring = ona->tx_rings[i].save_ring; - for (i = 0; i < ona->num_rx_rings + 1; i++) - ona->rx_rings[i].ring = ona->rx_rings[i].save_ring; + for_rx_tx(t) { + for (i = 0; i < nma_get_nrings(ona, t) + 1; i++) + NMR(ona, t)[i].ring = NMR(ona, t)[i].save_ring; + } netmap_mem_rings_delete(ona); netmap_krings_delete(ona); } @@ -604,8 +595,6 @@ netmap_get_pipe_na(struct nmreq *nmr, struct netmap_adapter **na, int create) mna->up.nm_krings_delete = netmap_pipe_krings_delete; mna->up.nm_mem = pna->nm_mem; mna->up.na_lut = pna->na_lut; - mna->up.na_lut_objtotal = pna->na_lut_objtotal; - mna->up.na_lut_objsize = pna->na_lut_objsize; mna->up.num_tx_rings = 1; mna->up.num_rx_rings = 1; @@ -627,7 +616,7 @@ netmap_get_pipe_na(struct nmreq *nmr, struct netmap_adapter **na, int create) sna = malloc(sizeof(*mna), M_DEVBUF, M_NOWAIT | M_ZERO); if (sna == NULL) { error = ENOMEM; - goto free_mna; + goto unregister_mna; } /* most fields are the same, copy from master and then fix */ *sna = *mna; @@ -677,6 +666,8 @@ found: free_sna: free(sna, M_DEVBUF); +unregister_mna: + netmap_pipe_remove(pna, mna); free_mna: free(mna, M_DEVBUF); put_out: diff --git a/sys/dev/netmap/netmap_vale.c b/sys/dev/netmap/netmap_vale.c index 6b1fe1fdf94b..ddd7334a8378 100644 --- a/sys/dev/netmap/netmap_vale.c +++ b/sys/dev/netmap/netmap_vale.c @@ -222,6 +222,10 @@ struct nm_bridge { * the lookup function, and allocated on attach */ struct nm_hash_ent ht[NM_BDG_HASH]; + +#ifdef CONFIG_NET_NS + struct net *ns; +#endif /* CONFIG_NET_NS */ }; const char* @@ -234,12 +238,14 @@ netmap_bdg_name(struct netmap_vp_adapter *vp) } +#ifndef CONFIG_NET_NS /* * XXX in principle nm_bridges could be created dynamically * Right now we have a static array and deletions are protected * by an exclusive lock. */ -struct nm_bridge nm_bridges[NM_BRIDGES]; +struct nm_bridge *nm_bridges; +#endif /* !CONFIG_NET_NS */ /* @@ -283,10 +289,13 @@ static struct nm_bridge * nm_find_bridge(const char *name, int create) { int i, l, namelen; - struct nm_bridge *b = NULL; + struct nm_bridge *b = NULL, *bridges; + u_int num_bridges; NMG_LOCK_ASSERT(); + netmap_bns_getbridges(&bridges, &num_bridges); + namelen = strlen(NM_NAME); /* base length */ l = name ? strlen(name) : 0; /* actual length */ if (l < namelen) { @@ -304,8 +313,8 @@ nm_find_bridge(const char *name, int create) ND("--- prefix is '%.*s' ---", namelen, name); /* lookup the name, remember empty slot if there is one */ - for (i = 0; i < NM_BRIDGES; i++) { - struct nm_bridge *x = nm_bridges + i; + for (i = 0; i < num_bridges; i++) { + struct nm_bridge *x = bridges + i; if (x->bdg_active_ports == 0) { if (create && b == NULL) @@ -318,7 +327,7 @@ nm_find_bridge(const char *name, int create) break; } } - if (i == NM_BRIDGES && b) { /* name not found, can create entry */ + if (i == num_bridges && b) { /* name not found, can create entry */ /* initialize the bridge */ strncpy(b->bdg_basename, name, namelen); ND("create new bridge %s with ports %d", b->bdg_basename, @@ -331,6 +340,7 @@ nm_find_bridge(const char *name, int create) b->bdg_ops.lookup = netmap_bdg_learning; /* reset the MAC address table */ bzero(b->ht, sizeof(struct nm_hash_ent) * NM_BDG_HASH); + NM_BNS_GET(b); } return b; } @@ -373,7 +383,7 @@ nm_alloc_bdgfwd(struct netmap_adapter *na) l += sizeof(struct nm_bdg_q) * num_dstq; l += sizeof(uint16_t) * NM_BDG_BATCH_MAX; - nrings = netmap_real_tx_rings(na); + nrings = netmap_real_rings(na, NR_TX); kring = na->tx_rings; for (i = 0; i < nrings; i++) { struct nm_bdg_fwd *ft; @@ -458,6 +468,7 @@ netmap_bdg_detach_common(struct nm_bridge *b, int hw, int sw) if (lim == 0) { ND("marking bridge %s as free", b->bdg_basename); bzero(&b->bdg_ops, sizeof(b->bdg_ops)); + NM_BNS_PUT(b); } } @@ -495,17 +506,6 @@ netmap_vp_dtor(struct netmap_adapter *na) } } -/* nm_dtor callback for persistent VALE ports */ -static void -netmap_persist_vp_dtor(struct netmap_adapter *na) -{ - struct ifnet *ifp = na->ifp; - - netmap_vp_dtor(na); - na->ifp = NULL; - nm_vi_detach(ifp); -} - /* remove a persistent VALE port from the system */ static int nm_vi_destroy(const char *name) @@ -535,6 +535,7 @@ nm_vi_destroy(const char *name) */ if_rele(ifp); netmap_detach(ifp); + nm_vi_detach(ifp); return 0; err: @@ -576,7 +577,6 @@ nm_vi_create(struct nmreq *nmr) } /* persist-specific routines */ vpna->up.nm_bdg_ctl = netmap_vp_bdg_ctl; - vpna->up.nm_dtor = netmap_persist_vp_dtor; netmap_adapter_get(&vpna->up); NMG_UNLOCK(); D("created %s", ifp->if_xname); @@ -632,7 +632,7 @@ netmap_get_bdg_na(struct nmreq *nmr, struct netmap_adapter **na, int create) i = b->bdg_port_index[j]; vpna = b->bdg_ports[i]; // KASSERT(na != NULL); - D("checking %s", vpna->up.name); + ND("checking %s", vpna->up.name); if (!strcmp(vpna->up.name, nr_name)) { netmap_adapter_get(&vpna->up); ND("found existing if %s refs %d", nr_name) @@ -813,12 +813,15 @@ unlock_exit: int netmap_bdg_ctl(struct nmreq *nmr, struct netmap_bdg_ops *bdg_ops) { - struct nm_bridge *b; + struct nm_bridge *b, *bridges; struct netmap_adapter *na; struct netmap_vp_adapter *vpna; char *name = nmr->nr_name; int cmd = nmr->nr_cmd, namelen = strlen(name); int error = 0, i, j; + u_int num_bridges; + + netmap_bns_getbridges(&bridges, &num_bridges); switch (cmd) { case NETMAP_BDG_NEWIF: @@ -852,7 +855,6 @@ netmap_bdg_ctl(struct nmreq *nmr, struct netmap_bdg_ops *bdg_ops) break; } - name = name + b->bdg_namelen + 1; error = ENOENT; for (j = 0; j < b->bdg_active_ports; j++) { i = b->bdg_port_index[j]; @@ -866,7 +868,7 @@ netmap_bdg_ctl(struct nmreq *nmr, struct netmap_bdg_ops *bdg_ops) */ if (!strcmp(vpna->up.name, name)) { /* bridge index */ - nmr->nr_arg1 = b - nm_bridges; + nmr->nr_arg1 = b - bridges; nmr->nr_arg2 = i; /* port index */ error = 0; break; @@ -886,7 +888,7 @@ netmap_bdg_ctl(struct nmreq *nmr, struct netmap_bdg_ops *bdg_ops) NMG_LOCK(); for (error = ENOENT; i < NM_BRIDGES; i++) { - b = nm_bridges + i; + b = bridges + i; if (j >= b->bdg_active_ports) { j = 0; /* following bridges scan from 0 */ continue; @@ -984,7 +986,7 @@ netmap_vp_krings_create(struct netmap_adapter *na) u_int tailroom; int error, i; uint32_t *leases; - u_int nrx = netmap_real_rx_rings(na); + u_int nrx = netmap_real_rings(na, NR_RX); /* * Leases are attached to RX rings on vale ports @@ -1066,6 +1068,9 @@ nm_bdg_preflush(struct netmap_kring *kring, u_int end) ft[ft_i].ft_flags = slot->flags; ND("flags is 0x%x", slot->flags); + /* we do not use the buf changed flag, but we still need to reset it */ + slot->flags &= ~NS_BUF_CHANGED; + /* this slot goes into a list so initialize the link field */ ft[ft_i].ft_next = NM_FT_NULL; buf = ft[ft_i].ft_buf = (slot->flags & NS_INDIRECT) ? @@ -1180,7 +1185,7 @@ netmap_vp_reg(struct netmap_adapter *na, int onoff) */ u_int netmap_bdg_learning(struct nm_bdg_fwd *ft, uint8_t *dst_ring, - const struct netmap_vp_adapter *na) + struct netmap_vp_adapter *na) { uint8_t *buf = ft->ft_buf; u_int buf_len = ft->ft_len; @@ -1211,11 +1216,11 @@ netmap_bdg_learning(struct nm_bdg_fwd *ft, uint8_t *dst_ring, * The hash is somewhat expensive, there might be some * worthwhile optimizations here. */ - if ((buf[6] & 1) == 0) { /* valid src */ + if (((buf[6] & 1) == 0) && (na->last_smac != smac)) { /* valid src */ uint8_t *s = buf+6; sh = nm_bridge_rthash(s); // XXX hash of source /* update source port forwarding entry */ - ht[sh].mac = smac; /* XXX expire ? */ + na->last_smac = ht[sh].mac = smac; /* XXX expire ? */ ht[sh].ports = mysrc; if (netmap_verbose) D("src %02x:%02x:%02x:%02x:%02x:%02x on port %d", @@ -1229,7 +1234,6 @@ netmap_bdg_learning(struct nm_bdg_fwd *ft, uint8_t *dst_ring, } /* XXX otherwise return NM_BDG_UNKNOWN ? */ } - *dst_ring = 0; return dst; } @@ -1475,7 +1479,7 @@ retry: if (dst_na->retry && retry) { /* try to get some free slot from the previous run */ - dst_na->up.nm_notify(&dst_na->up, dst_nr, NR_RX, 0); + kring->nm_notify(kring, 0); /* actually useful only for bwraps, since there * the notify will trigger a txsync on the hwna. VALE ports * have dst_na->retry == 0 @@ -1616,7 +1620,7 @@ retry: kring->nr_hwtail = j; still_locked = 0; mtx_unlock(&kring->q_lock); - dst_na->up.nm_notify(&dst_na->up, dst_nr, NR_RX, 0); + kring->nm_notify(kring, 0); /* this is netmap_notify for VALE ports and * netmap_bwrap_notify for bwrap. The latter will * trigger a txsync on the underlying hwna @@ -1649,29 +1653,28 @@ netmap_vp_txsync(struct netmap_kring *kring, int flags) (struct netmap_vp_adapter *)kring->na; u_int done; u_int const lim = kring->nkr_num_slots - 1; - u_int const cur = kring->rcur; + u_int const head = kring->rhead; if (bridge_batch <= 0) { /* testing only */ - done = cur; // used all + done = head; // used all goto done; } if (!na->na_bdg) { - done = cur; + done = head; goto done; } if (bridge_batch > NM_BDG_BATCH) bridge_batch = NM_BDG_BATCH; - done = nm_bdg_preflush(kring, cur); + done = nm_bdg_preflush(kring, head); done: - if (done != cur) - D("early break at %d/ %d, tail %d", done, cur, kring->nr_hwtail); + if (done != head) + D("early break at %d/ %d, tail %d", done, head, kring->nr_hwtail); /* * packets between 'done' and 'cur' are left unsent. */ kring->nr_hwcur = done; kring->nr_hwtail = nm_prev(done, lim); - nm_txsync_finalize(kring); if (netmap_verbose) D("%s ring %d flags %d", na->up.name, kring->ring_id, flags); return 0; @@ -1687,7 +1690,7 @@ netmap_vp_rxsync_locked(struct netmap_kring *kring, int flags) struct netmap_adapter *na = kring->na; struct netmap_ring *ring = kring->ring; u_int nm_i, lim = kring->nkr_num_slots - 1; - u_int head = nm_rxsync_prologue(kring); + u_int head = kring->rhead; int n; if (head > lim) { @@ -1717,8 +1720,6 @@ netmap_vp_rxsync_locked(struct netmap_kring *kring, int flags) kring->nr_hwcur = head; } - /* tell userspace that there are new packets */ - nm_rxsync_finalize(kring); n = 0; done: return n; @@ -1804,12 +1805,18 @@ netmap_vp_create(struct nmreq *nmr, struct ifnet *ifp, struct netmap_vp_adapter na->num_rx_desc = nmr->nr_rx_slots; vpna->virt_hdr_len = 0; vpna->mfs = 1514; + vpna->last_smac = ~0llu; /*if (vpna->mfs > netmap_buf_size) TODO netmap_buf_size is zero?? vpna->mfs = netmap_buf_size; */ if (netmap_verbose) D("max frame size %u", vpna->mfs); - na->na_flags |= NAF_BDG_MAYSLEEP | NAF_MEM_OWNER; + na->na_flags |= NAF_BDG_MAYSLEEP; + /* persistent VALE ports look like hw devices + * with a native netmap adapter + */ + if (ifp) + na->na_flags |= NAF_NATIVE; na->nm_txsync = netmap_vp_txsync; na->nm_rxsync = netmap_vp_rxsync; na->nm_register = netmap_vp_reg; @@ -1832,7 +1839,7 @@ netmap_vp_create(struct nmreq *nmr, struct ifnet *ifp, struct netmap_vp_adapter err: if (na->nm_mem != NULL) - netmap_mem_private_delete(na->nm_mem); + netmap_mem_delete(na->nm_mem); free(vpna, M_DEVBUF); return error; } @@ -1913,75 +1920,33 @@ netmap_bwrap_dtor(struct netmap_adapter *na) * The bridge wrapper then sends the packets through the bridge. */ static int -netmap_bwrap_intr_notify(struct netmap_adapter *na, u_int ring_nr, enum txrx tx, int flags) +netmap_bwrap_intr_notify(struct netmap_kring *kring, int flags) { + struct netmap_adapter *na = kring->na; struct netmap_bwrap_adapter *bna = na->na_private; - struct netmap_vp_adapter *hostna = &bna->host; - struct netmap_kring *kring, *bkring; - struct netmap_ring *ring; - int is_host_ring = ring_nr == na->num_rx_rings; + struct netmap_kring *bkring; struct netmap_vp_adapter *vpna = &bna->up; + u_int ring_nr = kring->ring_id; int error = 0; if (netmap_verbose) - D("%s %s%d 0x%x", na->name, - (tx == NR_TX ? "TX" : "RX"), ring_nr, flags); - - if (flags & NAF_DISABLE_NOTIFY) { - /* the enabled/disabled state of the ring has changed, - * propagate the info to the wrapper (with tx/rx swapped) - */ - if (tx == NR_TX) { - netmap_set_rxring(&vpna->up, ring_nr, - na->tx_rings[ring_nr].nkr_stopped); - } else { - netmap_set_txring(&vpna->up, ring_nr, - na->rx_rings[ring_nr].nkr_stopped); - } - return 0; - } + D("%s %s 0x%x", na->name, kring->name, flags); if (!nm_netmap_on(na)) return 0; - /* we only care about receive interrupts */ - if (tx == NR_TX) - return 0; - - kring = &na->rx_rings[ring_nr]; - ring = kring->ring; + bkring = &vpna->up.tx_rings[ring_nr]; /* make sure the ring is not disabled */ if (nm_kr_tryget(kring)) return 0; - if (is_host_ring && hostna->na_bdg == NULL) { - error = bna->save_notify(na, ring_nr, tx, flags); - goto put_out; - } - - /* Here we expect ring->head = ring->cur = ring->tail - * because everything has been released from the previous round. - * However the ring is shared and we might have info from - * the wrong side (the tx ring). Hence we overwrite with - * the info from the rx kring. - */ if (netmap_verbose) - D("%s head %d cur %d tail %d (kring %d %d %d)", na->name, - ring->head, ring->cur, ring->tail, + D("%s head %d cur %d tail %d", na->name, kring->rhead, kring->rcur, kring->rtail); - ring->head = kring->rhead; - ring->cur = kring->rcur; - ring->tail = kring->rtail; - - if (is_host_ring) { - vpna = hostna; - ring_nr = 0; - } - /* simulate a user wakeup on the rx ring */ - /* fetch packets that have arrived. - * XXX maybe do this in a loop ? + /* simulate a user wakeup on the rx ring + * fetch packets that have arrived. */ error = kring->nm_sync(kring, 0); if (error) @@ -1992,33 +1957,18 @@ netmap_bwrap_intr_notify(struct netmap_adapter *na, u_int ring_nr, enum txrx tx, goto put_out; } - /* new packets are ring->cur to ring->tail, and the bkring - * had hwcur == ring->cur. So advance ring->cur to ring->tail + /* new packets are kring->rcur to kring->nr_hwtail, and the bkring + * had hwcur == bkring->rhead. So advance bkring->rhead to kring->nr_hwtail * to push all packets out. */ - ring->head = ring->cur = ring->tail; + bkring->rhead = bkring->rcur = kring->nr_hwtail; - /* also set tail to what the bwrap expects */ - bkring = &vpna->up.tx_rings[ring_nr]; - ring->tail = bkring->nr_hwtail; // rtail too ? - - /* pass packets to the switch */ - nm_txsync_prologue(bkring); // XXX error checking ? netmap_vp_txsync(bkring, flags); /* mark all buffers as released on this ring */ - ring->head = ring->cur = kring->nr_hwtail; - ring->tail = kring->rtail; + kring->rhead = kring->rcur = kring->rtail = kring->nr_hwtail; /* another call to actually release the buffers */ - if (!is_host_ring) { - error = kring->nm_sync(kring, 0); - } else { - /* mark all packets as released, as in the - * second part of netmap_rxsync_from_host() - */ - kring->nr_hwcur = kring->nr_hwtail; - nm_rxsync_finalize(kring); - } + error = kring->nm_sync(kring, 0); put_out: nm_kr_put(kring); @@ -2035,6 +1985,7 @@ netmap_bwrap_register(struct netmap_adapter *na, int onoff) struct netmap_adapter *hwna = bna->hwna; struct netmap_vp_adapter *hostna = &bna->host; int error; + enum txrx t; ND("%s %s", na->name, onoff ? "on" : "off"); @@ -2047,8 +1998,6 @@ netmap_bwrap_register(struct netmap_adapter *na, int onoff) * putting it in netmap mode */ hwna->na_lut = na->na_lut; - hwna->na_lut_objtotal = na->na_lut_objtotal; - hwna->na_lut_objsize = na->na_lut_objsize; if (hostna->na_bdg) { /* if the host rings have been attached to switch, @@ -2056,8 +2005,6 @@ netmap_bwrap_register(struct netmap_adapter *na, int onoff) * in the hostna also */ hostna->up.na_lut = na->na_lut; - hostna->up.na_lut_objtotal = na->na_lut_objtotal; - hostna->up.na_lut_objsize = na->na_lut_objsize; } /* cross-link the netmap rings @@ -2066,13 +2013,12 @@ netmap_bwrap_register(struct netmap_adapter *na, int onoff) * We need to do this now, after the initialization * of the kring->ring pointers */ - for (i = 0; i < na->num_rx_rings + 1; i++) { - hwna->tx_rings[i].nkr_num_slots = na->rx_rings[i].nkr_num_slots; - hwna->tx_rings[i].ring = na->rx_rings[i].ring; - } - for (i = 0; i < na->num_tx_rings + 1; i++) { - hwna->rx_rings[i].nkr_num_slots = na->tx_rings[i].nkr_num_slots; - hwna->rx_rings[i].ring = na->tx_rings[i].ring; + for_rx_tx(t) { + enum txrx r= nm_txrx_swap(t); /* swap NR_TX <-> NR_RX */ + for (i = 0; i < nma_get_nrings(na, r) + 1; i++) { + NMR(hwna, t)[i].nkr_num_slots = NMR(na, r)[i].nkr_num_slots; + NMR(hwna, t)[i].ring = NMR(na, r)[i].ring; + } } } @@ -2087,14 +2033,29 @@ netmap_bwrap_register(struct netmap_adapter *na, int onoff) netmap_vp_reg(&hostna->up, onoff); if (onoff) { - /* intercept the hwna nm_nofify callback */ - bna->save_notify = hwna->nm_notify; - hwna->nm_notify = netmap_bwrap_intr_notify; + u_int i; + /* intercept the hwna nm_nofify callback on the hw rings */ + for (i = 0; i < hwna->num_rx_rings; i++) { + hwna->rx_rings[i].save_notify = hwna->rx_rings[i].nm_notify; + hwna->rx_rings[i].nm_notify = netmap_bwrap_intr_notify; + } + i = hwna->num_rx_rings; /* for safety */ + /* save the host ring notify unconditionally */ + hwna->rx_rings[i].save_notify = hwna->rx_rings[i].nm_notify; + if (hostna->na_bdg) { + /* also intercept the host ring notify */ + hwna->rx_rings[i].nm_notify = netmap_bwrap_intr_notify; + } } else { - hwna->nm_notify = bna->save_notify; - hwna->na_lut = NULL; - hwna->na_lut_objtotal = 0; - hwna->na_lut_objsize = 0; + u_int i; + /* reset all notify callbacks (including host ring) */ + for (i = 0; i <= hwna->num_rx_rings; i++) { + hwna->rx_rings[i].nm_notify = hwna->rx_rings[i].save_notify; + hwna->rx_rings[i].save_notify = NULL; + } + hwna->na_lut.lut = NULL; + hwna->na_lut.objtotal = 0; + hwna->na_lut.objsize = 0; } return 0; @@ -2154,9 +2115,9 @@ netmap_bwrap_krings_create(struct netmap_adapter *na) * The corresponding krings must point back to the * hostna */ - hostna->tx_rings = na->tx_rings + na->num_tx_rings; + hostna->tx_rings = &na->tx_rings[na->num_tx_rings]; hostna->tx_rings[0].na = hostna; - hostna->rx_rings = na->rx_rings + na->num_rx_rings; + hostna->rx_rings = &na->rx_rings[na->num_rx_rings]; hostna->rx_rings[0].na = hostna; } @@ -2180,74 +2141,59 @@ netmap_bwrap_krings_delete(struct netmap_adapter *na) /* notify method for the bridge-->hwna direction */ static int -netmap_bwrap_notify(struct netmap_adapter *na, u_int ring_n, enum txrx tx, int flags) +netmap_bwrap_notify(struct netmap_kring *kring, int flags) { - struct netmap_bwrap_adapter *bna = - (struct netmap_bwrap_adapter *)na; + struct netmap_adapter *na = kring->na; + struct netmap_bwrap_adapter *bna = na->na_private; struct netmap_adapter *hwna = bna->hwna; - struct netmap_kring *kring, *hw_kring; - struct netmap_ring *ring; - u_int lim; + u_int ring_n = kring->ring_id; + u_int lim = kring->nkr_num_slots - 1; + struct netmap_kring *hw_kring; int error = 0; - if (tx == NR_TX) - return EINVAL; - - kring = &na->rx_rings[ring_n]; + ND("%s: na %s hwna %s", + (kring ? kring->name : "NULL!"), + (na ? na->name : "NULL!"), + (hwna ? hwna->name : "NULL!")); hw_kring = &hwna->tx_rings[ring_n]; - ring = kring->ring; - lim = kring->nkr_num_slots - 1; + + if (nm_kr_tryget(hw_kring)) + return 0; if (!nm_netmap_on(hwna)) return 0; - mtx_lock(&kring->q_lock); /* first step: simulate a user wakeup on the rx ring */ - netmap_vp_rxsync_locked(kring, flags); + netmap_vp_rxsync(kring, flags); ND("%s[%d] PRE rx(c%3d t%3d l%3d) ring(h%3d c%3d t%3d) tx(c%3d ht%3d t%3d)", na->name, ring_n, kring->nr_hwcur, kring->nr_hwtail, kring->nkr_hwlease, ring->head, ring->cur, ring->tail, hw_kring->nr_hwcur, hw_kring->nr_hwtail, hw_ring->rtail); - /* second step: the simulated user consumes all new packets */ - ring->head = ring->cur = ring->tail; - - /* third step: the new packets are sent on the tx ring + /* second step: the new packets are sent on the tx ring * (which is actually the same ring) */ - /* set tail to what the hw expects */ - ring->tail = hw_kring->rtail; - nm_txsync_prologue(&hwna->tx_rings[ring_n]); // XXX error checking ? + hw_kring->rhead = hw_kring->rcur = kring->nr_hwtail; error = hw_kring->nm_sync(hw_kring, flags); + if (error) + goto out; - /* fourth step: now we are back the rx ring */ + /* third step: now we are back the rx ring */ /* claim ownership on all hw owned bufs */ - ring->head = nm_next(ring->tail, lim); /* skip past reserved slot */ - ring->tail = kring->rtail; /* restore saved value of tail, for safety */ + kring->rhead = kring->rcur = nm_next(hw_kring->nr_hwtail, lim); /* skip past reserved slot */ - /* fifth step: the user goes to sleep again, causing another rxsync */ - netmap_vp_rxsync_locked(kring, flags); + /* fourth step: the user goes to sleep again, causing another rxsync */ + netmap_vp_rxsync(kring, flags); ND("%s[%d] PST rx(c%3d t%3d l%3d) ring(h%3d c%3d t%3d) tx(c%3d ht%3d t%3d)", na->name, ring_n, kring->nr_hwcur, kring->nr_hwtail, kring->nkr_hwlease, ring->head, ring->cur, ring->tail, hw_kring->nr_hwcur, hw_kring->nr_hwtail, hw_kring->rtail); - mtx_unlock(&kring->q_lock); +out: + nm_kr_put(hw_kring); return error; } -/* notify method for the bridge-->host-rings path */ -static int -netmap_bwrap_host_notify(struct netmap_adapter *na, u_int ring_n, enum txrx tx, int flags) -{ - struct netmap_bwrap_adapter *bna = na->na_private; - struct netmap_adapter *port_na = &bna->up.up; - if (tx == NR_TX || ring_n != 0) - return EINVAL; - return netmap_bwrap_notify(port_na, port_na->num_rx_rings, NR_RX, flags); -} - - /* nm_bdg_ctl callback for the bwrap. * Called on bridge-attach and detach, as an effect of vale-ctl -[ahd]. * On attach, it needs to provide a fake netmap_priv_d structure and @@ -2261,7 +2207,6 @@ netmap_bwrap_bdg_ctl(struct netmap_adapter *na, struct nmreq *nmr, int attach) { struct netmap_priv_d *npriv; struct netmap_bwrap_adapter *bna = (struct netmap_bwrap_adapter*)na; - struct netmap_if *nifp; int error = 0; if (attach) { @@ -2275,8 +2220,8 @@ netmap_bwrap_bdg_ctl(struct netmap_adapter *na, struct nmreq *nmr, int attach) npriv = malloc(sizeof(*npriv), M_DEVBUF, M_NOWAIT|M_ZERO); if (npriv == NULL) return ENOMEM; - nifp = netmap_do_regif(npriv, na, nmr->nr_ringid, nmr->nr_flags, &error); - if (!nifp) { + error = netmap_do_regif(npriv, na, nmr->nr_ringid, nmr->nr_flags); + if (error) { bzero(npriv, sizeof(*npriv)); free(npriv, M_DEVBUF); return error; @@ -2323,6 +2268,7 @@ netmap_bwrap_attach(const char *nr_name, struct netmap_adapter *hwna) struct netmap_adapter *na = NULL; struct netmap_adapter *hostna = NULL; int error = 0; + enum txrx t; /* make sure the NIC is not already in use */ if (NETMAP_OWNED_BY_ANY(hwna)) { @@ -2336,15 +2282,17 @@ netmap_bwrap_attach(const char *nr_name, struct netmap_adapter *hwna) } na = &bna->up.up; + na->na_private = bna; strncpy(na->name, nr_name, sizeof(na->name)); /* fill the ring data for the bwrap adapter with rx/tx meanings * swapped. The real cross-linking will be done during register, * when all the krings will have been created. */ - na->num_rx_rings = hwna->num_tx_rings; - na->num_tx_rings = hwna->num_rx_rings; - na->num_tx_desc = hwna->num_rx_desc; - na->num_rx_desc = hwna->num_tx_desc; + for_rx_tx(t) { + enum txrx r = nm_txrx_swap(t); /* swap NR_TX <-> NR_RX */ + nma_set_nrings(na, t, nma_get_nrings(hwna, r)); + nma_set_ndesc(na, t, nma_get_ndesc(hwna, r)); + } na->nm_dtor = netmap_bwrap_dtor; na->nm_register = netmap_bwrap_register; // na->nm_txsync = netmap_bwrap_txsync; @@ -2376,13 +2324,14 @@ netmap_bwrap_attach(const char *nr_name, struct netmap_adapter *hwna) hostna = &bna->host.up; snprintf(hostna->name, sizeof(hostna->name), "%s^", nr_name); hostna->ifp = hwna->ifp; - hostna->num_tx_rings = 1; - hostna->num_tx_desc = hwna->num_rx_desc; - hostna->num_rx_rings = 1; - hostna->num_rx_desc = hwna->num_tx_desc; + for_rx_tx(t) { + enum txrx r = nm_txrx_swap(t); + nma_set_nrings(hostna, t, 1); + nma_set_ndesc(hostna, t, nma_get_ndesc(hwna, r)); + } // hostna->nm_txsync = netmap_bwrap_host_txsync; // hostna->nm_rxsync = netmap_bwrap_host_rxsync; - hostna->nm_notify = netmap_bwrap_host_notify; + hostna->nm_notify = netmap_bwrap_notify; hostna->nm_mem = na->nm_mem; hostna->na_private = bna; hostna->na_vp = &bna->up; @@ -2416,7 +2365,7 @@ netmap_bwrap_attach(const char *nr_name, struct netmap_adapter *hwna) return 0; err_free: - netmap_mem_private_delete(na->nm_mem); + netmap_mem_delete(na->nm_mem); err_put: hwna->na_vp = hwna->na_hostvp = NULL; netmap_adapter_put(hwna); @@ -2425,13 +2374,54 @@ err_put: } - -void -netmap_init_bridges(void) +struct nm_bridge * +netmap_init_bridges2(u_int n) { int i; - bzero(nm_bridges, sizeof(struct nm_bridge) * NM_BRIDGES); /* safety */ - for (i = 0; i < NM_BRIDGES; i++) - BDG_RWINIT(&nm_bridges[i]); + struct nm_bridge *b; + + b = malloc(sizeof(struct nm_bridge) * n, M_DEVBUF, + M_NOWAIT | M_ZERO); + if (b == NULL) + return NULL; + for (i = 0; i < n; i++) + BDG_RWINIT(&b[i]); + return b; +} + +void +netmap_uninit_bridges2(struct nm_bridge *b, u_int n) +{ + int i; + + if (b == NULL) + return; + + for (i = 0; i < n; i++) + BDG_RWDESTROY(&b[i]); + free(b, M_DEVBUF); +} + +int +netmap_init_bridges(void) +{ +#ifdef CONFIG_NET_NS + return netmap_bns_register(); +#else + nm_bridges = netmap_init_bridges2(NM_BRIDGES); + if (nm_bridges == NULL) + return ENOMEM; + return 0; +#endif +} + +void +netmap_uninit_bridges(void) +{ +#ifdef CONFIG_NET_NS + netmap_bns_unregister(); +#else + netmap_uninit_bridges2(nm_bridges, NM_BRIDGES); +#endif } #endif /* WITH_VALE */ diff --git a/sys/dev/nvd/nvd.c b/sys/dev/nvd/nvd.c index b48fb3586a48..016d728547b6 100644 --- a/sys/dev/nvd/nvd.c +++ b/sys/dev/nvd/nvd.c @@ -278,6 +278,7 @@ nvd_new_disk(struct nvme_namespace *ns, void *ctrlr_arg) disk->d_maxsize = nvme_ns_get_max_io_xfer_size(ns); disk->d_sectorsize = nvme_ns_get_sector_size(ns); disk->d_mediasize = (off_t)nvme_ns_get_size(ns); + disk->d_delmaxsize = (off_t)nvme_ns_get_size(ns); if (TAILQ_EMPTY(&disk_head)) disk->d_unit = 0; diff --git a/sys/dev/ofw/ofw_bus_subr.c b/sys/dev/ofw/ofw_bus_subr.c index 233675d87225..47d6267b8d5d 100644 --- a/sys/dev/ofw/ofw_bus_subr.c +++ b/sys/dev/ofw/ofw_bus_subr.c @@ -170,7 +170,8 @@ ofw_bus_status_okay(device_t dev) const char *status; status = ofw_bus_get_status(dev); - if (status == NULL || strcmp(status, "okay") == 0) + if (status == NULL || strcmp(status, "okay") == 0 || + strcmp(status, "ok") == 0) return (1); return (0); @@ -444,7 +445,7 @@ ofw_bus_intr_to_rl(device_t dev, phandle_t node, if (OF_searchencprop(node, "interrupt-parent", &iparent, sizeof(iparent)) == -1) { for (iparent = node; iparent != 0; - iparent = OF_parent(node)) { + iparent = OF_parent(iparent)) { if (OF_hasprop(iparent, "interrupt-controller")) break; } diff --git a/sys/dev/pci/pcireg.h b/sys/dev/pci/pcireg.h index d68cb257a3fd..c48b269789fd 100644 --- a/sys/dev/pci/pcireg.h +++ b/sys/dev/pci/pcireg.h @@ -51,6 +51,7 @@ #define PCIE_ARI_SLOTMAX 0 #define PCIE_ARI_FUNCMAX 255 +#define PCI_RID_DOMAIN_SHIFT 16 #define PCI_RID_BUS_SHIFT 8 #define PCI_RID_SLOT_SHIFT 3 #define PCI_RID_FUNC_SHIFT 0 diff --git a/sys/dev/pms/RefTisa/discovery/api/dm.h b/sys/dev/pms/RefTisa/discovery/api/dm.h new file mode 100644 index 000000000000..18721fda5e19 --- /dev/null +++ b/sys/dev/pms/RefTisa/discovery/api/dm.h @@ -0,0 +1,163 @@ +/******************************************************************************* +** +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/******************************************************************************** +** +* dm.h +* +* Abstract: This module defines the contants, enum and #define definition used +* by Discovery Moduled (DM). +* +********************************************************************************/ + +#ifndef DM_H + +#define DM_H + +/************************************************* + * constants for type field in agsaMem_t + *************************************************/ +#define DM_CACHED_MEM 0x00 /**< CACHED memory type */ +#define DM_DMA_MEM 0x01 /**< DMA memory type */ +#define DM_CACHED_DMA_MEM 0x02 /**< CACHED DMA memory type */ + +/************************************************* + * constants for API return values + *************************************************/ +#define DM_RC_SUCCESS 0x00 /**< Successful function return value */ +#define DM_RC_FAILURE 0x01 /**< Failed function return value */ +#define DM_RC_BUSY 0x02 /**< Busy function return value */ +#define DM_RC_VERSION_INCOMPATIBLE 0x03 /**< Version miss match */ +#define DM_RC_VERSION_UNTESTED 0x04 /**< Version not tested */ + + + +/************************************************* + * Discovery option + *************************************************/ +#define DM_DISCOVERY_OPTION_FULL_START 0x00 /**< Full discovery */ +#define DM_DISCOVERY_OPTION_INCREMENTAL_START 0x01 /**< Incremental discovery */ +#define DM_DISCOVERY_OPTION_ABORT 0x02 /**< Discovery abort */ + + +/************************************************* + * Discovery status + *************************************************/ +enum dmDiscoveryState_e +{ + dmDiscCompleted = 0, + dmDiscFailed, + dmDiscAborted, + dmDiscAbortFailed, + dmDiscInProgress, + dmDiscAbortInvalid, /* no discovery to abort */ + dmDiscAbortInProgress, /* abort in progress */ + +}; + +/************************************************* + * Device status + *************************************************/ +enum dmDeviceState_e +{ + dmDeviceNoChange = 0, + dmDeviceArrival, + dmDeviceRemoval, + dmDeviceMCNChange, + dmDeviceRateChange, +}; + +typedef struct dmContext_s { + void *tdData; + void *dmData; +} dmContext_t; + +typedef struct{ + bit16 smpTimeout; + bit16 it_NexusTimeout; + bit16 firstBurstSize; + bit8 flag; + bit8 devType_S_Rate; + bit8 sasAddressHi[4]; + bit8 sasAddressLo[4]; + bit8 initiator_ssp_stp_smp; + bit8 target_ssp_stp_smp; + /* bit8 - bit14 are set by the user of DM such as TDM for directly attached expander + 0 - 7; PhyID + 8: non SMP or not + 9 - 10: types of expander, valid only when bit8 is set + 10b (2): edge expander + 11b (3): fanout expander + 11 - 14: MCN + */ + bit16 ext; + bit8 sataDeviceType; + bit8 reserved; +} dmDeviceInfo_t; + + +typedef struct{ + void *virtPtr; + void *osHandle; + bit32 physAddrUpper; + bit32 physAddrLower; + bit32 totalLength; + bit32 numElements; + bit32 singleElementLength; + bit32 alignment; + bit32 type; + bit32 reserved; +} dmMem_t; + +#define DM_NUM_MEM_CHUNKS 8 + +typedef struct{ + bit32 count; + dmMem_t dmMemory[DM_NUM_MEM_CHUNKS]; +} dmMemoryRequirement_t; + +typedef dmContext_t dmPortContext_t; + +typedef dmContext_t dmRoot_t; + +typedef struct{ + bit32 numDevHandles; + bit32 tbd1; + bit32 tbd2; +#ifdef DM_DEBUG + bit32 DMDebugLevel; +#endif + bit32 itNexusTimeout; +} dmSwConfig_t; + +typedef struct{ + bit8 sasRemoteAddressHi[4]; + bit8 sasRemoteAddressLo[4]; + bit8 sasLocalAddressHi[4]; + bit8 sasLocalAddressLo[4]; + bit32 flag; +} dmPortInfo_t; + + +#endif /* DM_H */ diff --git a/sys/dev/pms/RefTisa/discovery/api/dmapi.h b/sys/dev/pms/RefTisa/discovery/api/dmapi.h new file mode 100644 index 000000000000..5e569b8ada49 --- /dev/null +++ b/sys/dev/pms/RefTisa/discovery/api/dmapi.h @@ -0,0 +1,89 @@ +/******************************************************************************* +** +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +** +* $FreeBSD$ +* +********************************************************************************/ +/******************************************************************************** +* dmapi.h +* +* Abstract: This module contains function prototype of the Discovery +* Module (DM) API for initiator. +*******************************************************************************/ + +#ifndef DMAPI_H +#define DMAPI_H + +#include +#include + +osGLOBAL bit32 dmCreatePort( + dmRoot_t *dmRoot, + dmPortContext_t *dmPortContext, + dmPortInfo_t *dmPortInfo); + +osGLOBAL bit32 dmDestroyPort( + dmRoot_t *dmRoot, + dmPortContext_t *dmPortContext, + dmPortInfo_t *dmPortInfo); + +osGLOBAL bit32 dmRegisterDevice( + dmRoot_t *dmRoot, + dmPortContext_t *dmPortContext, + dmDeviceInfo_t *dmDeviceInfo, + agsaDevHandle_t *agDevHandle); + +osGLOBAL bit32 dmDiscover( + dmRoot_t *dmRoot, + dmPortContext_t *dmPortContext, + bit32 option); + +osGLOBAL void dmGetRequirements( + dmRoot_t *dmRoot, + dmSwConfig_t *swConfig, + dmMemoryRequirement_t *memoryRequirement, + bit32 *usecsPerTick, + bit32 *maxNumLocks); + +osGLOBAL void dmNotifyBC( + dmRoot_t *dmRoot, + dmPortContext_t *dmPortContext, + bit32 type); + +osGLOBAL bit32 dmQueryDiscovery( + dmRoot_t *dmRoot, + dmPortContext_t *dmPortContext); + +osGLOBAL bit32 +dmResetFailedDiscovery( + dmRoot_t *dmRoot, + dmPortContext_t *dmPortContext); + +osGLOBAL bit32 dmInitialize( + dmRoot_t *dmRoot, + agsaRoot_t *agRoot, + dmMemoryRequirement_t *memoryAllocated, + dmSwConfig_t *swConfig, + bit32 usecsPerTick ); + +osGLOBAL void dmTimerTick ( dmRoot_t *dmRoot ); + +#endif /* DMAPI_H */ diff --git a/sys/dev/pms/RefTisa/discovery/api/tddmapi.h b/sys/dev/pms/RefTisa/discovery/api/tddmapi.h new file mode 100644 index 000000000000..38ae4d081aa0 --- /dev/null +++ b/sys/dev/pms/RefTisa/discovery/api/tddmapi.h @@ -0,0 +1,119 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/******************************************************************************** +* tmdmapi.h +* +* Abstract: This module contains function prototype of the Discovery +* Module (DM) API callback for initiator. +*******************************************************************************/ + +#ifndef TDDMAPI_H + +#define TDDMAPI_H + +osGLOBAL void tddmCacheFlush( + dmRoot_t *dmRoot, + void *tdMemHandle, + void *virtPtr, + bit32 length + ); + +osGLOBAL void tddmCacheInvalidate( + dmRoot_t *dmRoot, + void *tdMemHandle, + void *virtPtr, + bit32 length + ); + +osGLOBAL void tddmCachePreFlush( + dmRoot_t *dmRoot, + void *tdMemHandle, + void *virtPtr, + bit32 length + ); + +osGLOBAL void tddmDiscoverCB( + dmRoot_t *dmRoot, + dmPortContext_t *dmPortContext, + bit32 eventStatus + ); + +osGLOBAL void tddmQueryDiscoveryCB( + dmRoot_t *dmRoot, + dmPortContext_t *dmPortContext, + bit32 discType, + bit32 discState + ); + +osGLOBAL void tddmReportDevice( + dmRoot_t *dmRoot, + dmPortContext_t *dmPortContext, + dmDeviceInfo_t *dmDeviceInfo, + dmDeviceInfo_t *dmExpDeviceInfo, + bit32 flag + ); + +osGLOBAL bit8 tddmSATADeviceTypeDecode(bit8 * pSignature); + +osGLOBAL void tddmSingleThreadedEnter( + dmRoot_t *dmRoot, + bit32 syncLockId + ); + +osGLOBAL void tddmSingleThreadedLeave( + dmRoot_t *dmRoot, + bit32 syncLockId + ); +osGLOBAL bit32 tddmGetTransportParam( + dmRoot_t *dmRoot, + char *key, + char *subkey1, + char *subkey2, + char *subkey3, + char *subkey4, + char *subkey5, + char *valueName, + char *buffer, + bit32 bufferLen, + bit32 *lenReceived + ); +osGLOBAL bit32 +tddmRotateQnumber( + dmRoot_t *dmRoot, + agsaDevHandle_t *agDevHandle + ); +#ifndef tddmLogDebugString +GLOBAL void tddmLogDebugString( + dmRoot_t *dmRoot, + bit32 level, + char *string, + void *ptr1, + void *ptr2, + bit32 value1, + bit32 value2 + ); +#endif + + +#endif /* TDDMAPI_H */ diff --git a/sys/dev/pms/RefTisa/discovery/dm/dmdefs.h b/sys/dev/pms/RefTisa/discovery/dm/dmdefs.h new file mode 100644 index 000000000000..c6032d0b5ec4 --- /dev/null +++ b/sys/dev/pms/RefTisa/discovery/dm/dmdefs.h @@ -0,0 +1,1229 @@ +/******************************************************************************* +** +* Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +** +* $FreeBSD$ +* +********************************************************************************/ +#ifndef __DMDEFS_H__ +#define __DMDEFS_H__ + +#include + +#define DIRECT_SMP +//#undef DIRECT_SMP + +/* the index for memory requirement, must be continious */ +#define DM_ROOT_MEM_INDEX 0 /**< the index of dm root memory */ +#define DM_PORT_MEM_INDEX 1 /**< the index of port context memory */ +#define DM_DEVICE_MEM_INDEX 2 /**< the index of Device descriptors memory */ +#define DM_EXPANDER_MEM_INDEX 3 /**< the index of Expander device descriptors memory */ +#define DM_SMP_MEM_INDEX 4 /**< the index of SMP command descriptors memory */ +#define DM_INDIRECT_SMP_MEM_INDEX 5 /**< the index of Indirect SMP command descriptors memory */ + + + +#define DM_MAX_NUM_PHYS 16 +#define DM_MAX_EXPANDER_PHYS 256 +#define DM_MAX_DEV 2048 +#define DM_MAX_EXPANDER_DEV 32 +#define DM_MAX_PORT_CONTEXT 16 +#define DM_MAX_SMP 32 +#define DM_MAX_INDIRECT_SMP DM_MAX_SMP + +#define DM_USECS_PER_TICK 1000000 /**< defines the heart beat of the LL layer 10ms */ + +/* +* FIS type +*/ +#define PIO_SETUP_DEV_TO_HOST_FIS 0x5F +#define REG_DEV_TO_HOST_FIS 0x34 +#define SET_DEV_BITS_FIS 0xA1 + +#define DEFAULT_KEY_BUFFER_SIZE 64 + +enum dm_locks_e +{ + DM_PORT_LOCK = 0, + DM_DEVICE_LOCK, + DM_EXPANDER_LOCK, + DM_TIMER_LOCK, + DM_SMP_LOCK, + DM_MAX_LOCKS +}; +/* default SMP timeout: 0xFFFF is the Maximum Allowed */ +#define DEFAULT_SMP_TIMEOUT 0xFFFF + +/* SMP direct payload size limit: IOMB direct payload size = 48 */ +#define SMP_DIRECT_PAYLOAD_LIMIT 44 + +#define SMP_INDIRECT_PAYLOAD 512 + +/* SMP maximum payload size allowed by SAS spec withtout CRC 4 bytes */ +#define SMP_MAXIMUM_PAYLOAD 1024 + +/*! \def MIN(a,b) +* \brief MIN macro +* +* use to find MIN of two values +*/ +#ifndef MIN +#define MIN(a,b) ((a) < (b) ? (a) : (b)) +#endif + +/*! \def MAX(a,b) +* \brief MAX macro +* +* use to find MAX of two values +*/ +#ifndef MAX +#define MAX(a,b) ((a) < (b) ? (b) : (a)) +#endif + +#ifndef agNULL +#define agNULL ((void *)0) +#endif + +/* for debugging print */ +#if defined(DM_DEBUG) + +/* +* for debugging purposes. +*/ +extern bit32 gDMDebugLevel; + +#define DM_DBG0(format) tddmLogDebugString(gDMDebugLevel, 0, format) +#define DM_DBG1(format) tddmLogDebugString(gDMDebugLevel, 1, format) +#define DM_DBG2(format) tddmLogDebugString(gDMDebugLevel, 2, format) +#define DM_DBG3(format) tddmLogDebugString(gDMDebugLevel, 3, format) +#define DM_DBG4(format) tddmLogDebugString(gDMDebugLevel, 4, format) +#define DM_DBG5(format) tddmLogDebugString(gDMDebugLevel, 5, format) +#define DM_DBG6(format) tddmLogDebugString(gDMDebugLevel, 6, format) + + +#else + +#define DM_DBG0(format) +#define DM_DBG1(format) +#define DM_DBG2(format) +#define DM_DBG3(format) +#define DM_DBG4(format) +#define DM_DBG5(format) +#define DM_DBG6(format) + +#endif /* DM_DEBUG */ + +//#define DM_ASSERT OS_ASSERT +//#define tddmLogDebugString TIDEBUG_MSG + +/* discovery related state */ +#define DM_DSTATE_NOT_STARTED 0 +#define DM_DSTATE_STARTED 1 +#define DM_DSTATE_COMPLETED 2 +#define DM_DSTATE_COMPLETED_WITH_FAILURE 3 + +/* SAS/SATA discovery status */ +#define DISCOVERY_NOT_START 0 /**< status indicates discovery not started */ +#define DISCOVERY_UP_STREAM 1 /**< status indicates discover upstream */ +#define DISCOVERY_DOWN_STREAM 2 /**< status indicates discover downstream */ +#define DISCOVERY_CONFIG_ROUTING 3 /**< status indicates discovery config routing table */ +#define DISCOVERY_SAS_DONE 4 /**< status indicates discovery done */ +#define DISCOVERY_REPORT_PHY_SATA 5 /**< status indicates discovery report phy sata */ + +/* SMP function */ +#define SMP_REPORT_GENERAL 0x00 +#define SMP_REPORT_MANUFACTURE_INFORMATION 0x01 +#define SMP_READ_GPIO_REGISTER 0x02 +#define SMP_DISCOVER 0x10 +#define SMP_REPORT_PHY_ERROR_LOG 0x11 +#define SMP_REPORT_PHY_SATA 0x12 +#define SMP_REPORT_ROUTING_INFORMATION 0x13 +#define SMP_WRITE_GPIO_REGISTER 0x82 +#define SMP_CONFIGURE_ROUTING_INFORMATION 0x90 +#define SMP_PHY_CONTROL 0x91 +#define SMP_PHY_TEST_FUNCTION 0x92 +#define SMP_PMC_SPECIFIC 0xC0 +#define SMP_DISCOVER_LIST 0x20 + + +/* SMP function results */ +#define SMP_FUNCTION_ACCEPTED 0x00 +#define UNKNOWN_SMP_FUNCTION 0x01 +#define SMP_FUNCTION_FAILED 0x02 +#define INVALID_REQUEST_FRAME_LENGTH 0x03 +#define INVALID_EXPANDER_CHANGE_COUNT 0x04 +#define SMP_FN_BUSY 0x05 +#define INCOMPLETE_DESCRIPTOR_LIST 0x06 +#define PHY_DOES_NOT_EXIST 0x10 +#define INDEX_DOES_NOT_EXIST 0x11 +#define PHY_DOES_NOT_SUPPORT_SATA 0x12 +#define UNKNOWN_PHY_OPERATION 0x13 +#define UNKNOWN_PHY_TEST_FUNCTION 0x14 +#define PHY_TEST_FUNCTION_IN_PROGRESS 0x15 +#define PHY_VACANT 0x16 +#define UNKNOWN_PHY_EVENT_SOURCE 0x17 +#define UNKNOWN_DESCRIPTOT_TYPE 0x18 +#define UNKNOWN_PHY_FILETER 0x19 +#define AFFILIATION_VIOLATION 0x1A +#define SMP_ZONE_VIOLATION 0x20 +#define NO_MANAGEMENT_ACCESS_RIGHTS 0x21 +#define UNKNOWN_ENABLE_DISABLE_ZONING_VALUE 0x22 +#define ZONE_LOCK_VIOLATION 0x23 +#define NOT_ACTIVATED 0x24 +#define ZONE_GROUP_OUT_OF_RANGE 0x25 +#define NO_PHYSICAL_PRESENCE 0x26 +#define SAVING_NOT_SUPPORTED 0x27 +#define SOURCE_ZONE_GROUP_DOES_NOT_EXIST 0x28 +#define DISABLED_PASSWORD_NOT_SUPPORTED 0x29 + +/* SMP PHY CONTROL OPERATION */ +#define SMP_PHY_CONTROL_NOP 0x00 +#define SMP_PHY_CONTROL_LINK_RESET 0x01 +#define SMP_PHY_CONTROL_HARD_RESET 0x02 +#define SMP_PHY_CONTROL_DISABLE 0x03 +#define SMP_PHY_CONTROL_CLEAR_ERROR_LOG 0x05 +#define SMP_PHY_CONTROL_CLEAR_AFFILIATION 0x06 +#define SMP_PHY_CONTROL_XMIT_SATA_PS_SIGNAL 0x07 + +#define DM_VEN_DEV_SPC 0x80010000 +#define DM_VEN_DEV_ADAPSPC 0x80810000 +#define DM_VEN_DEV_SPCv 0x80080000 +#define DM_VEN_DEV_SPCve 0x80090000 +#define DM_VEN_DEV_SPCvplus 0x80180000 +#define DM_VEN_DEV_SPCveplus 0x80190000 +#define DM_VEN_DEV_ADAPvplus 0x80880000 +#define DM_VEN_DEV_ADAPveplus 0x80890000 + +#define DMIsSPC(agr) (DM_VEN_DEV_SPC == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC */ +#define DMIsSPCADAP(agr) (DM_VEN_DEV_SPC == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC */ +#define DMIsSPCv(agr) (DM_VEN_DEV_SPCv == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCv */ +#define DMIsSPCve(agr) (DM_VEN_DEV_SPCve == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCve */ +#define DMIsSPCvplus(agr) (DM_VEN_DEV_SPCvplus == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCv+ */ +#define DMIsSPCveplus(agr) (DM_VEN_DEV_SPCveplus == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCve+ */ +#define DMIsSPCADAPvplus(agr) (DM_VEN_DEV_ADAPvplus == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCv+ */ +#define DMIsSPCADAPveplus(agr) (DM_VEN_DEV_ADAPveplus == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCve+ */ + +/**************************************************************** + * SAS 1.1 Spec + ****************************************************************/ +/* SMP header definition */ +typedef struct dmSMPFrameHeader_s +{ + bit8 smpFrameType; /* The first byte of SMP frame represents the SMP FRAME TYPE */ + bit8 smpFunction; /* The second byte of the SMP frame represents the SMP FUNCTION */ + bit8 smpFunctionResult; /* The third byte of SMP frame represents FUNCTION RESULT of the SMP response. */ + bit8 smpReserved; /* reserved */ +} dmSMPFrameHeader_t; + +/**************************************************************** + * report general request + ****************************************************************/ +#ifdef FOR_COMPLETENESS +typedef struct smpReqReportGeneral_s +{ + /* nothing. some compiler disallowed structure with no member */ +} smpReqReportGeneral_t; +#endif + +/**************************************************************** + * report general response + ****************************************************************/ +#define REPORT_GENERAL_CONFIGURING_BIT 0x2 +#define REPORT_GENERAL_CONFIGURABLE_BIT 0x1 +#define REPORT_GENERAL_LONG_RESPONSE_BIT 0x80 + +typedef struct smpRespReportGeneral_s +{ + bit8 expanderChangeCount16[2]; + bit8 expanderRouteIndexes16[2]; + bit8 reserved1; /* byte 9; has LONG Response for SAS 2 at bit 8 */ + bit8 numOfPhys; + bit8 configuring_configurable; + /* B7-2 : reserved */ + /* B1 : configuring */ + /* B0 : configurable */ + bit8 reserved4[17]; +} smpRespReportGeneral_t; + +#define REPORT_GENERAL_IS_CONFIGURING(pResp) \ + (((pResp)->configuring_configurable & REPORT_GENERAL_CONFIGURING_BIT) == \ + REPORT_GENERAL_CONFIGURING_BIT) + +#define REPORT_GENERAL_IS_CONFIGURABLE(pResp) \ + (((pResp)->configuring_configurable & REPORT_GENERAL_CONFIGURABLE_BIT) == \ + REPORT_GENERAL_CONFIGURABLE_BIT) + +#define REPORT_GENERAL_GET_ROUTEINDEXES(pResp) \ + DMA_BEBIT16_TO_BIT16(*(bit16 *)((pResp)->expanderRouteIndexes16)) + +#define REPORT_GENERAL_IS_LONG_RESPONSE(pResp) \ + (((pResp)->reserved1 & REPORT_GENERAL_LONG_RESPONSE_BIT) == \ + REPORT_GENERAL_LONG_RESPONSE_BIT) + +/**************************************************************** + * report manufacturer info response + ****************************************************************/ +typedef struct smpRespReportManufactureInfo_s +{ + bit8 reserved1[8]; + bit8 vendorIdentification[8]; + bit8 productIdentification[16]; + bit8 productRevisionLevel[4]; + bit8 vendorSpecific[20]; +} smpRespReportManufactureInfo_t; + +/**************************************************************** + * discover request + ****************************************************************/ +typedef struct smpReqDiscover_s +{ + bit32 reserved1; + bit8 reserved2; + bit8 phyIdentifier; + bit8 ignored; + bit8 reserved3; +} smpReqDiscover_t; + +/**************************************************************** + * discover response + ****************************************************************/ +typedef struct smpRespDiscover_s +{ + bit8 reserved1[4]; + bit8 reserved2; + bit8 phyIdentifier; + bit8 reserved3[2]; + bit8 attachedDeviceType; /* byte 12 */ + /* B7 : reserved */ + /* B6-4 : attachedDeviceType */ + /* B3-0 : reserved */ + bit8 negotiatedPhyLinkRate; /* byte 11 */ + /* B7-4 : reserved */ + /* B3-0 : negotiatedPhyLinkRate */ + bit8 attached_Ssp_Stp_Smp_Sata_Initiator; /* byte 14 */ + /* B7-4 : reserved */ + /* B3 : attachedSspInitiator */ + /* B2 : attachedStpInitiator */ + /* B1 : attachedSmpInitiator */ + /* B0 : attachedSataHost */ + bit8 attached_SataPS_Ssp_Stp_Smp_Sata_Target; /* byte 15 */ + /* B7 : attachedSataPortSelector */ + /* B6-4 : reserved */ + /* B3 : attachedSspTarget */ + /* B2 : attachedStpTarget */ + /* B1 : attachedSmpTarget */ + /* B0 : attachedSatadevice */ + bit8 sasAddressHi[4]; + bit8 sasAddressLo[4]; + bit8 attachedSasAddressHi[4]; + bit8 attachedSasAddressLo[4]; + bit8 attachedPhyIdentifier; + bit8 reserved9[7]; + bit8 programmedAndHardware_MinPhyLinkRate; + /* B7-4 : programmedMinPhyLinkRate */ + /* B3-0 : hardwareMinPhyLinkRate */ + bit8 programmedAndHardware_MaxPhyLinkRate; + /* B7-4 : programmedMaxPhyLinkRate */ + /* B3-0 : hardwareMaxPhyLinkRate */ + bit8 phyChangeCount; + bit8 virtualPhy_partialPathwayTimeout; /* byte 43 */ + /* B7 : virtualPhy*/ + /* B6-4 : reserved */ + /* B3-0 : partialPathwayTimeout */ + bit8 routingAttribute; + /* B7-4 : reserved */ + /* B3-0 : routingAttribute */ + bit8 reserved13[5]; + bit8 vendorSpecific[2]; +} smpRespDiscover_t; + +#define DISCRSP_SSP_BIT 0x08 +#define DISCRSP_STP_BIT 0x04 +#define DISCRSP_SMP_BIT 0x02 +#define DISCRSP_SATA_BIT 0x01 + +#define DISCRSP_SATA_PS_BIT 0x80 + +#define DISCRSP_GET_ATTACHED_DEVTYPE(pResp) \ + (((pResp)->attachedDeviceType & 0x70) >> 4) +#define DISCRSP_GET_LINKRATE(pResp) \ + ((pResp)->negotiatedPhyLinkRate & 0x0F) + +#define DISCRSP_IS_SSP_INITIATOR(pResp) \ + (((pResp)->attached_Ssp_Stp_Smp_Sata_Initiator & DISCRSP_SSP_BIT) == DISCRSP_SSP_BIT) +#define DISCRSP_IS_STP_INITIATOR(pResp) \ + (((pResp)->attached_Ssp_Stp_Smp_Sata_Initiator & DISCRSP_STP_BIT) == DISCRSP_STP_BIT) +#define DISCRSP_IS_SMP_INITIATOR(pResp) \ + (((pResp)->attached_Ssp_Stp_Smp_Sata_Initiator & DISCRSP_SMP_BIT) == DISCRSP_SMP_BIT) +#define DISCRSP_IS_SATA_HOST(pResp) \ + (((pResp)->attached_Ssp_Stp_Smp_Sata_Initiator & DISCRSP_SATA_BIT) == DISCRSP_SATA_BIT) + +#define DISCRSP_IS_SSP_TARGET(pResp) \ + (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & DISCRSP_SSP_BIT) == DISCRSP_SSP_BIT) +#define DISCRSP_IS_STP_TARGET(pResp) \ + (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & DISCRSP_STP_BIT) == DISCRSP_STP_BIT) +#define DISCRSP_IS_SMP_TARGET(pResp) \ + (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & DISCRSP_SMP_BIT) == DISCRSP_SMP_BIT) +#define DISCRSP_IS_SATA_DEVICE(pResp) \ + (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & DISCRSP_SATA_BIT) == DISCRSP_SATA_BIT) +#define DISCRSP_IS_SATA_PORTSELECTOR(pResp) \ + (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & DISCRSP_SATA_PS_BIT) == DISCRSP_SATA_PS_BIT) + +/* bit8 array[4] -> bit32 */ +#define DISCRSP_GET_SAS_ADDRESSHI(pResp) \ + DMA_BEBIT32_TO_BIT32(*(bit32 *)(pResp)->sasAddressHi) +#define DISCRSP_GET_SAS_ADDRESSLO(pResp) \ + DMA_BEBIT32_TO_BIT32(*(bit32 *)(pResp)->sasAddressLo) + +/* bit8 array[4] -> bit32 */ +#define DISCRSP_GET_ATTACHED_SAS_ADDRESSHI(pResp) \ + DMA_BEBIT32_TO_BIT32(*(bit32 *)(pResp)->attachedSasAddressHi) +#define DISCRSP_GET_ATTACHED_SAS_ADDRESSLO(pResp) \ + DMA_BEBIT32_TO_BIT32(*(bit32 *)(pResp)->attachedSasAddressLo) + +#define DISCRSP_VIRTUALPHY_BIT 0x80 +#define DISCRSP_IS_VIRTUALPHY(pResp) \ + (((pResp)->virtualPhy_partialPathwayTimeout & DISCRSP_VIRTUALPHY_BIT) == DISCRSP_VIRTUALPHY_BIT) + +#define DISCRSP_GET_ROUTINGATTRIB(pResp) \ + ((pResp)->routingAttribute & 0x0F) + +/**************************************************************** + * report route table request + ****************************************************************/ +typedef struct smpReqReportRouteTable_s +{ + bit8 reserved1[2]; + bit8 expanderRouteIndex16[20]; + bit8 reserved2; + bit8 phyIdentifier; + bit8 reserved3[2]; +} smpReqReportRouteTable_t; + +/**************************************************************** + * report route response + ****************************************************************/ +typedef struct smpRespReportRouteTable_s +{ + bit8 reserved1[2]; + bit8 expanderRouteIndex16[2]; + bit8 reserved2; + bit8 phyIdentifier; + bit8 reserved3[2]; + bit8 disabled; + /* B7 : expander route entry disabled */ + /* B6-0 : reserved */ + bit8 reserved5[3]; + bit8 routedSasAddressHi32[4]; + bit8 routedSasAddressLo32[4]; + bit8 reserved6[16]; +} smpRespReportRouteTable_t; + +/**************************************************************** + * configure route information request + ****************************************************************/ +typedef struct smpReqConfigureRouteInformation_s +{ + bit8 reserved1[2]; + bit8 expanderRouteIndex[2]; + bit8 reserved2; + bit8 phyIdentifier; + bit8 reserved3[2]; + bit8 disabledBit_reserved4; + bit8 reserved5[3]; + bit8 routedSasAddressHi[4]; + bit8 routedSasAddressLo[4]; + bit8 reserved6[16]; +} smpReqConfigureRouteInformation_t; + +/**************************************************************** + * configure route response + ****************************************************************/ +#ifdef FOR_COMPLETENESS +typedef struct smpRespConfigureRouteInformation_s +{ + /* nothing. some compiler disallowed structure with no member */ +} smpRespConfigureRouteInformation_t; +#endif + +/**************************************************************** + * report Phy Sata request + ****************************************************************/ +typedef struct smpReqReportPhySata_s +{ + bit8 reserved1[4]; + bit8 reserved2; + bit8 phyIdentifier; + bit8 reserved3[2]; +} smpReqReportPhySata_t; + +/**************************************************************** + * report Phy Sata response + ****************************************************************/ +typedef struct smpRespReportPhySata_s +{ + bit8 reserved1[4]; + bit8 reserved2; + bit8 phyIdentifier; + bit8 reserved3; + bit8 affiliations_sup_valid; + /* b7-2 : reserved */ + /* b1 : Affiliations supported */ + /* b0 : Affiliation valid */ + bit8 reserved5[4]; + bit8 stpSasAddressHi[4]; + bit8 stpSasAddressLo[4]; + bit8 regDevToHostFis[20]; + bit8 reserved6[4]; + bit8 affiliatedStpInitiatorSasAddressHi[4]; + bit8 affiliatedStpInitiatorSasAddressLo[4]; +} smpRespReportPhySata_t; + + +/**************************************************************** + * Phy Control request + ****************************************************************/ +typedef struct smpReqPhyControl_s +{ + bit8 reserved1[4]; + bit8 reserved2; + bit8 phyIdentifier; + bit8 phyOperation; + bit8 updatePartialPathwayTOValue; + /* b7-1 : reserved */ + /* b0 : update partial pathway timeout value */ + bit8 reserved3[20]; + bit8 programmedMinPhysicalLinkRate; + /* b7-4 : programmed Minimum Physical Link Rate*/ + /* b3-0 : reserved */ + bit8 programmedMaxPhysicalLinkRate; + /* b7-4 : programmed Maximum Physical Link Rate*/ + /* b3-0 : reserved */ + bit8 reserved4[2]; + bit8 partialPathwayTOValue; + /* b7-4 : reserved */ + /* b3-0 : partial Pathway TO Value */ + bit8 reserved5[3]; +} smpReqPhyControl_t; + +/**************************************************************** + * Phy Control response + ****************************************************************/ +#ifdef FOR_COMPLETENESS +typedef struct smpRespPhyControl_s +{ + /* nothing. some compiler disallowed structure with no member */ +} smpRespPhyControl_t; +#endif + + +/**************************************************************** + * SAS 2 Rev 14c Spec + ****************************************************************/ +/* SMP header definition */ +typedef struct tdssSMPFrameHeader2_s +{ + bit8 smpFrameType; /* The first byte of SMP frame represents the SMP FRAME TYPE */ + bit8 smpFunction; /* The second byte of the SMP frame represents the SMP FUNCTION */ + bit8 smpAllocLenFuncResult; /* The third byte of SMP frame represents ALLOCATED RESPONSE LENGTH of SMP request or FUNCTION RESULT of the SMP response. */ + bit8 smpReqResLen; /* The third byte of SMP frame represents REQUEST LENGTH of SMP request or RESPONSE LENGTH of the SMP response. */ +} tdssSMPFrameHeader2_t; + +/**************************************************************** + * report general request + ****************************************************************/ +#ifdef FOR_COMPLETENESS +typedef struct smpReqReportGeneral2_s +{ + /* nothing. some compiler disallowed structure with no member */ +} smpReqReportGeneral2_t; +#endif + +/**************************************************************** + * report general response + ****************************************************************/ +#define REPORT_GENERAL_TABLE_TO_TABLE_SUPPORTED_BIT 0x80 +#define REPORT_GENERAL_CONFIGURES_OTHERS_BIT 0x04 + +typedef struct smpRespReportGeneral2_s +{ + bit8 expanderChangeCount16[2]; /* byte 4-5 */ + bit8 expanderRouteIndexes16[2]; /* byte 6-7 */ + bit8 LongResponse; /* byte 8 */ + /* B7: LongResponse */ + /* B6-0: Reserved */ + bit8 numOfPhys; /* byte 9 */ + bit8 byte10; + /* B7 : TABLE TO TABLE SUPPORTED */ + /* B6 : ZONE CONFIGURING */ + /* B5 : SELF CONFIGURING */ + /* B4 : STP CONTINUE AWT */ + /* B3 : OPEN REJECT RETRY SUPPORTED */ + /* B2 : CONFIGURES OTHERS */ + /* B1 : CONFIGURING */ + /* B0 : EXTERNALLY CONFIGURABLE ROUTE TABLE */ + bit8 reserved1; /* byte11 */ + bit8 EnclosureLogicalID[8]; + bit8 reserved2[8]; /* upto byte27; Spec 1.1 */ + bit8 reserved3[2]; + bit8 STPBusInactivityTimeLimit[2]; + bit8 STPMaxConnectTimeLimit[2]; /* byte33 */ + bit8 STPSMPI_TNexusLossTime[2]; /* byte35 */ + bit8 byte36; + /* B7-6 : NUMBER OF ZONE GROUPS */ + /* B5 : RESERVED */ + /* B4 : ZONE LOCKED */ + /* B3 : PHYSICAL PRESENCE SUPPORTED */ + /* B2 : PHYSICAL PRESENCE ASSERTED */ + /* B1 : ZONING SUPPORTED */ + /* B0 : ZONING ENABLED */ + bit8 byte37; + /* B7-5 : RESERVED */ + /* B4 : SAVING */ + /* B3 : SAVING ZONE MANAGER PASSWORD SUPPORTED */ + /* B2 : SAVING ZONE PHY INFORMATION SUPPORTED */ + /* B1 : SAVING ZONE PERMISSION TABLE SUPPORTED */ + /* B0 : SAVING ZONING ENABLED SUPPORTED */ + bit8 MaxNumOfRoutedSASAddr[2]; /* byte39 */ + bit8 ActiveZoneManagerSASAddr[8]; /* byte47 */ + bit8 ZoneLockInactivityTimeLimit[2]; /* byte49 */ + bit8 reserved4[2]; + bit8 reserved5; /* byte52 */ + bit8 FirstEnclosureConnectorElementIdx; /* byte53 */ + bit8 NumOfEnclosureConnectorElementIdxs; /* byte54 */ + bit8 reserved6; /* byte55 */ + bit8 ReducedFunctionality; + /* B7: ReducedFunctionality */ + /* B6-0: Reserved */ + bit8 TimeToReducedFunctionality; + bit8 InitialTimeToReducedFunctionality; + bit8 MaxReducedFunctionalityTime; /* byte59 */ + bit8 LastSelfConfigurationStatusDescIdx[2]; + bit8 MaxNumOfStoredSelfConfigurationStatusDesc[2]; + bit8 LastPhyEventListDescIdx[2]; + bit8 MaxNumbOfStoredPhyEventListDesc[2]; /* byte67 */ + bit8 STPRejectToOpenLimit[2]; /* byte69 */ + bit8 reserved7[2]; /* byte71 */ + +} smpRespReportGeneral2_t; + +#define SAS2_REPORT_GENERAL_GET_ROUTEINDEXES(pResp) \ + DMA_BEBIT16_TO_BIT16(*(bit16 *)((pResp)->expanderRouteIndexes16)) + +#define SAS2_REPORT_GENERAL_IS_CONFIGURING(pResp) \ + (((pResp)->byte10 & REPORT_GENERAL_CONFIGURING_BIT) == \ + REPORT_GENERAL_CONFIGURING_BIT) + +#define SAS2_REPORT_GENERAL_IS_CONFIGURABLE(pResp) \ + (((pResp)->byte10 & REPORT_GENERAL_CONFIGURABLE_BIT) == \ + REPORT_GENERAL_CONFIGURABLE_BIT) + +#define SAS2_REPORT_GENERAL_IS_TABLE_TO_TABLE_SUPPORTED(pResp) \ + (((pResp)->byte10 & REPORT_GENERAL_TABLE_TO_TABLE_SUPPORTED_BIT) == \ + REPORT_GENERAL_TABLE_TO_TABLE_SUPPORTED_BIT) + +#define SAS2_REPORT_GENERAL_IS_CONFIGURES_OTHERS(pResp) \ + (((pResp)->byte10 & REPORT_GENERAL_CONFIGURES_OTHERS_BIT) == \ + REPORT_GENERAL_CONFIGURES_OTHERS_BIT) + +/**************************************************************** + * report manufacturer info request + ****************************************************************/ +#ifdef FOR_COMPLETENESS +typedef struct smpReqReportManufactureInfo2_s +{ + /* nothing. some compiler disallowed structure with no member */ +} smpReqReportManufactureInfo2_t; +#endif + +/**************************************************************** + * report manufacturer info response + ****************************************************************/ +typedef struct smpRespReportManufactureInfo2_s +{ + bit16 ExpanderChangeCount; /* byte 4-5 */ + bit8 reserved1[2]; /* byte 6-7 */ + bit8 SAS11Format; /* byte 8 */ + /* B7-1 : RESERVED */ + /* B0 : SAS-1.1 Format */ + bit8 reserved2[3]; /* byte 9-11 */ + bit8 vendorIdentification[8]; /* byte 12-19 */ + bit8 productIdentification[16]; /* byte 20-35 */ + bit8 productRevisionLevel[4]; /* byte 36-39 */ + bit8 componentVendorID[8]; /* byte 40-47 */ + bit8 componentID[2]; /* byte 48-49 */ + bit8 componentRevisionLevel; /* byte 50 */ + bit8 reserved3; /* byte 51 */ + bit8 vendorSpecific[8]; /* byte 52-59 */ +} smpRespReportManufactureInfo2_t; + +/**************************************************************** + * discover request + ****************************************************************/ +typedef struct smpReqDiscover2_s +{ + bit32 reserved1; /* byte 4 - 7 */ + bit8 IgnoreZoneGroup; /* byte 8 */ + bit8 phyIdentifier; /* byte 9 */ + bit16 reserved2; /* byte 10 - 11*/ +} smpReqDiscover2_t; + +/**************************************************************** + * discover response + ****************************************************************/ +typedef struct smpRespDiscover2_s +{ + bit16 ExpanderChangeCount; /* byte 4 - 5 */ + bit8 reserved1[3]; /* byte 6 - 8 */ + bit8 phyIdentifier; /* byte 9 */ + bit8 reserved2[2]; /* byte 10 - 11 */ + bit8 attachedDeviceTypeReason; /* byte 12 */ + /* B7 : RESERVED */ + /* B6-4 : Attached Device Type */ + /* B3-0 : Attached Reason */ + bit8 NegotiatedLogicalLinkRate; /* byte 13 */ + /* B7-4 : RESERVED */ + /* B3-0 : Negotiated Logical Link Rate */ + bit8 attached_Ssp_Stp_Smp_Sata_Initiator; /* byte 14 */ + /* B7-4 : reserved */ + /* B3 : attached SSP Initiator */ + /* B2 : attached STP Initiator */ + /* B1 : attached SMP Initiator */ + /* B0 : attached SATA Host */ + bit8 attached_SataPS_Ssp_Stp_Smp_Sata_Target; /* byte 15 */ + /* B7 : attached SATA Port Selector */ + /* B6-4 : reserved */ + /* B3 : attached SSP Target */ + /* B2 : attached STP Target */ + /* B1 : attached SMP Target */ + /* B0 : attached SATA device */ + bit8 sasAddressHi[4]; /* byte 16 - 19 */ + bit8 sasAddressLo[4]; /* byte 20 - 23 */ + bit8 attachedSasAddressHi[4]; /* byte 24 - 27 */ + bit8 attachedSasAddressLo[4]; /* byte 28 - 31 */ + bit8 attachedPhyIdentifier; /* byte 32 */ + bit8 byte33; /* byte 33 */ + /* B7-3 : reserved */ + /* B2 : attached Inside ZPSDS Persistent */ + /* B1 : attached Requested Inside ZPSDS */ + /* B0 : attached Break Reply Capable */ + bit8 reserved3[6]; /* byte 34 - 39; for indentify address frame related fields */ + bit8 programmedAndHardware_MinPhyLinkRate; /* byte 40 */ + /* B7-4 : programmedMinPhyLinkRate */ + /* B3-0 : hardwareMinPhyLinkRate */ + bit8 programmedAndHardware_MaxPhyLinkRate; /* byte 41 */ + /* B7-4 : programmedMaxPhyLinkRate */ + /* B3-0 : hardwareMaxPhyLinkRate */ + bit8 phyChangeCount; /* byte 42 */ + bit8 virtualPhy_partialPathwayTimeout; /* byte 43 */ + /* B7 : virtualPhy*/ + /* B6-4 : reserved */ + /* B3-0 : partialPathwayTimeout */ + bit8 routingAttribute; /* byte 44 */ + /* B7-4 : reserved */ + /* B3-0 : routingAttribute */ + bit8 ConnectorType; /* byte 45 */ + /* B7 : reserved */ + /* B6-0 : Connector Type */ + bit8 ConnectorElementIndex; /* byte 46 */ + bit8 ConnectorPhysicalLink; /* byte 47 */ + bit8 reserved4[2]; /* byte 48 - 49 */ + bit8 vendorSpecific[2]; /* byte 50 - 51*/ + bit8 AttachedDeviceName[8]; /* byte 52 - 59*/ + bit8 byte60; /* byte 60 */ + /* B7 : reserved */ + /* B6 : Requested Inside ZPSDS Changed By Expander */ + /* B5 : Inside ZPSDS Persistent */ + /* B4 : Requested Inside ZPSDS */ + /* B3 : reserved */ + /* B2 : Zone Group Persistent */ + /* B1 : Inside ZPSDS */ + /* B0 : Zoning Enabled */ + bit8 reserved5[2]; /* byte 61 - 62; zoning-related fields */ + bit8 ZoneGroup; /* byte 63 */ + bit8 SelfCongfiguringStatus; /* byte 64 */ + bit8 SelfCongfigurationLevelsCompleted; /* byte 65 */ + bit8 reserved6[2]; /* byte 66 - 67; self configuration related fields */ + bit8 SelfConfigurationSASAddressHi[4]; /* byte 68 - 71 */ + bit8 SelfConfigurationSASAddressLo[4]; /* byte 72 - 75 */ + bit8 ProgrammedphyCapabilities[4]; /* byte 76 - 79 */ + bit8 CurrentphyCapabilities[4]; /* byte 80 - 83 */ + bit8 AttachedphyCapabilities[4]; /* byte 84 - 87 */ + bit8 reserved7[6]; /* byte 88 - 93 */ + bit8 ReasonNegotiatedPhysicalLinkRate; /* byte 94 */ + bit8 NegotiatedSSCHWMuxingSupported; /* byte 95 */ + /* B7-2 : reserved */ + /* B1 : Negotiated SSC */ + /* B0 : HW Muxing Supported */ + bit8 byte96; /* byte 96 */ + /* B7-6 : reserved */ + /* B5 : Default Inside ZPSDS Persistent */ + /* B4 : Default Requested Inside ZPSDS */ + /* B3 : reserved */ + /* B2 : Default Zone Group Persistent */ + /* B1 : reserved */ + /* B0 : Default Zoning Enabled */ + bit8 reserved8; /* byte 97 */ + bit8 reserved9; /* byte 98 */ + bit8 DefaultZoneGroup; /* byte 99 */ + bit8 byte100; /* byte 100 */ + /* B7-6 : reserved */ + /* B5 : Saved Inside ZPSDS Persistent */ + /* B4 : Saved Requested Inside ZPSDS */ + /* B3 : reserved */ + /* B2 : Saved Zone Group Persistent */ + /* B1 : reserved */ + /* B0 : Saved Zoning Enabled */ + bit8 reserved10; /* byte 101 */ + bit8 reserved11; /* byte 102 */ + bit8 SavedZoneGroup; /* byte 103 */ + bit8 byte104; /* byte 104 */ + /* B7-6 : reserved */ + /* B5 : Shadow Inside ZPSDS Persistent */ + /* B4 : Shadow Requested Inside ZPSDS */ + /* B3 : reserved */ + /* B2 : Shadow Zone Group Persistent */ + /* B1-0 : reserved */ + bit8 reserved12; /* byte 105 */ + bit8 reserved13; /* byte 106 */ + bit8 ShadowZoneGroup; /* byte 107 */ + bit8 DeviceSlotNumber; /* byte 108 */ + bit8 GroupNumber; /* byte 109 */ + bit16 PathToEnclosure; /* byte 110 - 111 */ + +} smpRespDiscover2_t; + +#define SAS2_DISCRSP_SSP_BIT 0x08 +#define SAS2_DISCRSP_STP_BIT 0x04 +#define SAS2_DISCRSP_SMP_BIT 0x02 +#define SAS2_DISCRSP_SATA_BIT 0x01 + +#define SAS2_DISCRSP_SATA_PS_BIT 0x80 + +#define SAS2_MUXING_SUPPORTED 0x01 + +#define SAS2_DISCRSP_GET_ATTACHED_DEVTYPE(pResp) \ + (((pResp)->attachedDeviceTypeReason & 0x70) >> 4) +#define SAS2_DISCRSP_GET_LINKRATE(pResp) \ + ((pResp)->ReasonNegotiatedPhysicalLinkRate & 0x0F) +#define SAS2_DISCRSP_GET_LOGICAL_LINKRATE(pResp) \ + ((pResp)->NegotiatedLogicalLinkRate & 0x0F) + +#define SAS2_DISCRSP_IS_SSP_INITIATOR(pResp) \ + (((pResp)->attached_Ssp_Stp_Smp_Sata_Initiator & DISCRSP_SSP_BIT) == DISCRSP_SSP_BIT) +#define SAS2_DISCRSP_IS_STP_INITIATOR(pResp) \ + (((pResp)->attached_Ssp_Stp_Smp_Sata_Initiator & DISCRSP_STP_BIT) == DISCRSP_STP_BIT) +#define SAS2_DISCRSP_IS_SMP_INITIATOR(pResp) \ + (((pResp)->attached_Ssp_Stp_Smp_Sata_Initiator & DISCRSP_SMP_BIT) == DISCRSP_SMP_BIT) +#define SAS2_DISCRSP_IS_SATA_HOST(pResp) \ + (((pResp)->attached_Ssp_Stp_Smp_Sata_Initiator & DISCRSP_SATA_BIT) == DISCRSP_SATA_BIT) + +#define SAS2_DISCRSP_IS_SSP_TARGET(pResp) \ + (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & DISCRSP_SSP_BIT) == DISCRSP_SSP_BIT) +#define SAS2_DISCRSP_IS_STP_TARGET(pResp) \ + (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & DISCRSP_STP_BIT) == DISCRSP_STP_BIT) +#define SAS2_DISCRSP_IS_SMP_TARGET(pResp) \ + (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & DISCRSP_SMP_BIT) == DISCRSP_SMP_BIT) +#define SAS2_DISCRSP_IS_SATA_DEVICE(pResp) \ + (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & DISCRSP_SATA_BIT) == DISCRSP_SATA_BIT) +#define SAS2_DISCRSP_IS_SATA_PORTSELECTOR(pResp) \ + (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & DISCRSP_SATA_PS_BIT) == DISCRSP_SATA_PS_BIT) + +#define SAS2_DISCRSP_GET_SAS_ADDRESSHI(pResp) \ + DMA_BEBIT32_TO_BIT32(*(bit32 *)(pResp)->sasAddressHi) +#define SAS2_DISCRSP_GET_SAS_ADDRESSLO(pResp) \ + DMA_BEBIT32_TO_BIT32(*(bit32 *)(pResp)->sasAddressLo) + +#define SAS2_DISCRSP_GET_ATTACHED_SAS_ADDRESSHI(pResp) \ + DMA_BEBIT32_TO_BIT32(*(bit32 *)(pResp)->attachedSasAddressHi) +#define SAS2_DISCRSP_GET_ATTACHED_SAS_ADDRESSLO(pResp) \ + DMA_BEBIT32_TO_BIT32(*(bit32 *)(pResp)->attachedSasAddressLo) + +#define SAS2_DISCRSP_VIRTUALPHY_BIT 0x80 +#define SAS2_DISCRSP_IS_VIRTUALPHY(pResp) \ + (((pResp)->virtualPhy_partialPathwayTimeout & DISCRSP_VIRTUALPHY_BIT) == DISCRSP_VIRTUALPHY_BIT) + +#define SAS2_DISCRSP_GET_ROUTINGATTRIB(pResp) \ + ((pResp)->routingAttribute & 0x0F) + +#define SAS2_DISCRSP_IS_MUXING_SUPPORTED(pResp) \ + (((pResp)->NegotiatedSSCHWMuxingSupported & SAS2_MUXING_SUPPORTED) == SAS2_MUXING_SUPPORTED) + +/**************************************************************** + * discover list request + ****************************************************************/ +typedef struct smpReqDiscoverList2_s +{ + bit32 reserved1; /* byte 4 - 7 */ + bit8 StartingPhyID; /* byte 8 */ + bit8 MaxNumDiscoverDesc; /* byte 9 */ + bit8 byte10; /* byte 10 */ + /* B7 : Ignore Zone Group */ + /* B6-4 : Reserved */ + /* B3-0 : Phy Filter */ + bit8 byte11; /* byte 11 */ + /* B7-4 : Reserved */ + /* B6-4 : Descriptor Type */ + bit32 reserved2; /* byte 12 - 15 */ + bit8 VendorSpecific[12]; /* byte 16 - 27 */ +} smpReqDiscoverList2_t; + + + +/**************************************************************** + * discover list response + ****************************************************************/ +typedef struct smpRespDiscoverList2_s +{ + bit16 ExpanderChangeCount; /* byte 4 - 5 */ + bit16 reserved1; /* byte 6 - 7 */ + bit8 StartingPhyID; /* byte 8 */ + bit8 MaxNumDiscoverDesc; /* byte 9 */ + bit8 byte10; /* byte 10 */ + /* B7-4 : Reserved */ + /* B3-0 : Phy Filter */ + bit8 byte11; /* byte 11 */ + /* B7-4 : Reserved */ + /* B6-4 : Descriptor Type */ + bit8 DescLen; /* byte 12 */ + bit8 reserved2; /* byte 13 */ + bit16 reserved3; /* byte 14 - 15 */ + bit8 byte16; /* byte 16 */ + /* B7 : Zoning Supported */ + /* B6 : Zoning Enabled */ + /* B5-4 : Reserved */ + /* B3 : Self Configuring */ + /* B2 : Zone Configuring */ + /* B1 : Configuring */ + /* B0 : Externally Configurable Route Table */ + bit8 reserved4; /* byte 17 */ + bit16 LastDescIdx; /* byte 18 - 19 */ + bit16 LastPhyDescIdx; /* byte 20 - 21 */ + bit8 reserved5[10]; /* byte 22 - 31 */ + bit8 VendorSpecific[16]; /* byte 32 - 47 */ +} smpRespDiscoverList2_t; + + + +/**************************************************************** + * report route table request + ****************************************************************/ +typedef struct smpReqReportRouteTable2_s +{ + bit8 reserved1[2]; /* byte 4 - 5 */ + bit8 expanderRouteIndex16[20]; /* byte 6- 7 */ + bit8 reserved2; /* byte 8 */ + bit8 phyIdentifier; /* byte 9 */ + bit8 reserved3[2]; /* byte 10 -11 */ +} smpReqReportRouteTable2_t; + +/**************************************************************** + * report route response + ****************************************************************/ +typedef struct smpRespReportRouteTable2_s +{ + bit16 expanderChangeCount; /* byte 4 - 5 */ + bit16 expanderRouteIndex; /* byte 6 - 7 */ + bit8 reserved1; /* byte 8 */ + bit8 phyIdentifier; /* byte 9 */ + bit8 reserved2[2]; /* byte 10 - 11 */ + bit8 disabledBit_reserved3; /* byte 12 */ + /* B7 : Expander Route Entry Disabled */ + /* B6-0 : reserved */ + bit8 reserved4[3]; /* byte 13-15 */ + bit8 routedSasAddressHi[4]; /* byte 16-19 */ + bit8 routedSasAddressLo[4]; /* byte 20-23 */ + bit8 reserved5[16]; /* byte 24-39 */ +} smpRespReportRouteTable2_t; + +/**************************************************************** + * configure route information request + ****************************************************************/ +typedef struct smpReqConfigureRouteInformation2_s +{ + bit16 expectedExpanderChangeCount; /* byte 4-5 */ + bit16 expanderRouteIndex; /* byte 6-7 */ + bit8 reserved1; /* byte 8 */ + bit8 phyIdentifier; /* byte 9 */ + bit8 reserved2[2]; /* byte 10-11 */ + bit8 disabledBit_reserved3; /* byte 12 */ + /* B7 : Expander Route Entry Disabled */ + /* B6-0 : reserved */ + bit8 reserved4[3]; /* byte 13-15 */ + bit8 routedSasAddressHi[4]; /* byte 16-19 */ + bit8 routedSasAddressLo[4]; /* byte 20-23 */ + bit8 reserved5[16]; /* byte 24-39 */ +} smpReqConfigureRouteInformation2_t; + +/**************************************************************** + * configure route response + ****************************************************************/ +#ifdef FOR_COMPLETENESS +typedef struct smpRespConfigureRouteInformation2_s +{ + /* nothing. some compiler disallowed structure with no member */ +} smpRespConfigureRouteInformation2_t; +#endif + +/**************************************************************** + * report Phy Sata request + ****************************************************************/ +typedef struct smpReqReportPhySata2_s +{ + bit8 reserved1[5]; /* byte 4-8 */ + bit8 phyIdentifier; /* byte 9 */ + bit8 AffiliationContext; /* byte 10 */ + bit8 reserved2; /* byte 11 */ +} smpReqReportPhySata2_t; + +/**************************************************************** + * report Phy Sata response + ****************************************************************/ +typedef struct smpRespReportPhySata2_s +{ + bit16 expanderChangeCount; /* byte 4-5 */ + bit8 reserved1[3]; /* byte 6-8 */ + bit8 phyIdentifier; /* byte 9 */ + bit8 reserved2; /* byte 10 */ + bit8 byte11; /* byte 11 */ + /* b7-3 : reserved */ + /* b2 : STP I_T Nexus Loss Occurred */ + /* b1 : Affiliations supported */ + /* b0 : Affiliation valid */ + bit8 reserved3[4]; /* byte 12-15 */ + bit8 stpSasAddressHi[4]; /* byte 16-19 */ + bit8 stpSasAddressLo[4]; /* byte 20-23 */ + bit8 regDevToHostFis[20]; /* byte 24-43 */ + bit8 reserved4[4]; /* byte 44-47 */ + bit8 affiliatedStpInitiatorSasAddressHi[4]; /* byte 48-51 */ + bit8 affiliatedStpInitiatorSasAddressLo[4]; /* byte 52-55 */ + bit8 STPITNexusLossSASAddressHi[4]; /* byte 56-59 */ + bit8 STPITNexusLossSASAddressLo[4]; /* byte 60-63 */ + bit8 reserved5; /* byte 64 */ + bit8 AffiliationContext; /* byte 65 */ + bit8 CurrentAffiliationContexts; /* byte 66 */ + bit8 MaxAffiliationContexts; /* byte 67 */ + +} smpRespReportPhySata2_t; + +/**************************************************************** + * Phy Control request + ****************************************************************/ +typedef struct smpReqPhyControl2_s +{ + bit16 expectedExpanderChangeCount; /* byte 4-5 */ + bit8 reserved1[3]; /* byte 6-8 */ + bit8 phyIdentifier; /* byte 9 */ + bit8 phyOperation; /* byte 10 */ + bit8 updatePartialPathwayTOValue; /* byte 11 */ + /* b7-1 : reserved */ + /* b0 : update partial pathway timeout value */ + bit8 reserved2[12]; /* byte 12-23 */ + bit8 AttachedDeviceName[8]; /* byte 24-31 */ + bit8 programmedMinPhysicalLinkRate; /* byte 32 */ + /* b7-4 : programmed Minimum Physical Link Rate*/ + /* b3-0 : reserved */ + bit8 programmedMaxPhysicalLinkRate; /* byte 33 */ + /* b7-4 : programmed Maximum Physical Link Rate*/ + /* b3-0 : reserved */ + bit8 reserved3[2]; /* byte 34-35 */ + bit8 partialPathwayTOValue; /* byte 36 */ + /* b7-4 : reserved */ + /* b3-0 : partial Pathway TO Value */ + bit8 reserved4[3]; /* byte 37-39 */ + +} smpReqPhyControl2_t; + +/**************************************************************** + * Phy Control response + ****************************************************************/ +#ifdef FOR_COMPLETENESS +typedef struct smpRespPhyControl2_s +{ + /* nothing. some compiler disallowed structure with no member */ +} smpRespPhyControl2_t; +#endif + +#define SMP_REQUEST 0x40 +#define SMP_RESPONSE 0x41 + +/* bit8 array[4] -> bit32 */ +#define DM_GET_SAS_ADDRESSLO(sasAddressLo) \ + DMA_BEBIT32_TO_BIT32(*(bit32 *)sasAddressLo) + +#define DM_GET_SAS_ADDRESSHI(sasAddressHi) \ + DMA_BEBIT32_TO_BIT32(*(bit32 *)sasAddressHi) + + +#define DM_GET_LINK_RATE(input) (input & 0x0F) + +#define DM_SAS_CONNECTION_RATE_1_5G 0x08 +#define DM_SAS_CONNECTION_RATE_3_0G 0x09 +#define DM_SAS_CONNECTION_RATE_6_0G 0x0A +#define DM_SAS_CONNECTION_RATE_12_0G 0x0B + +#define DISCOVERY_CONFIGURING_TIMER_VALUE (3 * 1000 * 1000) /* 3 seconds */ +#define DISCOVERY_RETRIES 3 +#define CONFIGURE_ROUTE_TIMER_VALUE (1 * 1000 * 1000) /* 1 seconds */ +#define DEVICE_REGISTRATION_TIMER_VALUE (2 * 1000 * 1000) /* 2 seconds */ +#define SMP_RETRIES 5 +#define SMP_BUSY_TIMER_VALUE (1 * 1000 * 1000) /* 1 second */ +#define SMP_BUSY_RETRIES 5 +#define SATA_ID_DEVICE_DATA_TIMER_VALUE (3 * 1000 * 1000) /* 3 second */ +#define SATA_ID_DEVICE_DATA_RETRIES 3 +#define BC_TIMER_VALUE (5 * 1000 * 1000) /* 5 second */ +#define SMP_TIMER_VALUE (30 * 1000 * 1000) /* 30 second */ + +#define STP_DEVICE_TYPE 0 /* SATA behind expander 00*/ +#define SAS_DEVICE_TYPE 1 /* SSP or SMP 01 */ +#define SATA_DEVICE_TYPE 2 /* direct SATA 10 */ +#define ATAPI_DEVICE_FLAG 0x200000 /* ATAPI device flag*/ + + +/* ATA device type */ +#define SATA_ATA_DEVICE 0x01 /**< ATA ATA device type */ +#define SATA_ATAPI_DEVICE 0x02 /**< ATA ATAPI device type */ +#define SATA_PM_DEVICE 0x03 /**< ATA PM device type */ +#define SATA_SEMB_DEVICE 0x04 /**< ATA SEMB device type */ +#define SATA_SEMB_WO_SEP_DEVICE 0x05 /**< ATA SEMB without SEP device type */ +#define UNKNOWN_DEVICE 0xFF + + +/* SAS device type definition. SAS spec(r.7) p206 */ +#define SAS_NO_DEVICE 0 +#define SAS_END_DEVICE 1 +#define SAS_EDGE_EXPANDER_DEVICE 2 +#define SAS_FANOUT_EXPANDER_DEVICE 3 + +/* routing attributes */ +#define SAS_ROUTING_DIRECT 0x00 +#define SAS_ROUTING_SUBTRACTIVE 0x01 +#define SAS_ROUTING_TABLE 0x02 + +#define SAS_CONNECTION_RATE_1_5G 0x08 +#define SAS_CONNECTION_RATE_3_0G 0x09 +#define SAS_CONNECTION_RATE_6_0G 0x0A +#define SAS_CONNECTION_RATE_12_0G 0x0B + +#define IT_NEXUS_TIMEOUT 0x7D0 /* 2000 ms; old value was 0xFFFF */ + +/* bit8 array[4] -> bit32 */ +#define DEVINFO_GET_SAS_ADDRESSLO(devInfo) \ + DMA_BEBIT32_TO_BIT32(*(bit32 *)(devInfo)->sasAddressLo) + +#define DEVINFO_GET_SAS_ADDRESSHI(devInfo) \ + DMA_BEBIT32_TO_BIT32(*(bit32 *)(devInfo)->sasAddressHi) + +/* this macro is based on SAS spec, not sTSDK 0xC0 */ +#define DEVINFO_GET_DEVICETTYPE(devInfo) \ + (((devInfo)->devType_S_Rate & 0xC0) >> 6) + +#define DEVINFO_GET_LINKRATE(devInfo) \ + ((devInfo)->devType_S_Rate & 0x0F) + +/**< target device type */ +#define DM_DEFAULT_DEVICE 0 +#define DM_SAS_DEVICE 1 +#define DM_SATA_DEVICE 2 + +#define DEVICE_SSP_BIT 0x8 /* SSP Initiator port */ +#define DEVICE_STP_BIT 0x4 /* STP Initiator port */ +#define DEVICE_SMP_BIT 0x2 /* SMP Initiator port */ +#define DEVICE_SATA_BIT 0x1 /* SATA device, valid in the discovery response only */ + +#define DEVICE_IS_SSP_INITIATOR(DeviceData) \ + (((DeviceData)->initiator_ssp_stp_smp & DEVICE_SSP_BIT) == DEVICE_SSP_BIT) + +#define DEVICE_IS_STP_INITIATOR(DeviceData) \ + (((DeviceData)->initiator_ssp_stp_smp & DEVICE_STP_BIT) == DEVICE_STP_BIT) + +#define DEVICE_IS_SMP_INITIATOR(DeviceData) \ + (((DeviceData)->initiator_ssp_stp_smp & DEVICE_SMP_BIT) == DEVICE_SMP_BIT) + +#define DEVICE_IS_SSP_TARGET(DeviceData) \ + (((DeviceData)->target_ssp_stp_smp & DEVICE_SSP_BIT) == DEVICE_SSP_BIT) + +#define DEVICE_IS_STP_TARGET(DeviceData) \ + (((DeviceData)->target_ssp_stp_smp & DEVICE_STP_BIT) == DEVICE_STP_BIT) + +#define DEVICE_IS_SMP_TARGET(DeviceData) \ + (((DeviceData)->target_ssp_stp_smp & DEVICE_SMP_BIT) == DEVICE_SMP_BIT) + +#define DEVICE_IS_SATA_DEVICE(DeviceData) \ + (((DeviceData)->target_ssp_stp_smp & DEVICE_SATA_BIT) == DEVICE_SATA_BIT) + +/* bit8 array[4] -> bit32 */ +#define DEVINFO_GET_SAS_ADDRESSLO(devInfo) \ + DMA_BEBIT32_TO_BIT32(*(bit32 *)(devInfo)->sasAddressLo) + +#define DEVINFO_GET_SAS_ADDRESSHI(devInfo) \ + DMA_BEBIT32_TO_BIT32(*(bit32 *)(devInfo)->sasAddressHi) + +/* this macro is based on SAS spec, not sTSDK 0xC0 */ +#define DEVINFO_GET_DEVICETTYPE(devInfo) \ + (((devInfo)->devType_S_Rate & 0xC0) >> 6) + +#define DEVINFO_GET_LINKRATE(devInfo) \ + ((devInfo)->devType_S_Rate & 0x0F) + + +#define DEVINFO_GET_EXT_SMP(devInfo) \ + (((devInfo)->ext & 0x100) >> 8) + +#define DEVINFO_GET_EXT_EXPANDER_TYPE(devInfo) \ + (((devInfo)->ext & 0x600) >> 9) + +#define DEVINFO_GET_EXT_MCN(devInfo) \ + (((devInfo)->ext & 0x7800) >> 11) + + +#define DEVINFO_PUT_SMPTO(devInfo, smpto) \ + ((devInfo)->smpTimeout) = smpto + +#define DEVINFO_PUT_ITNEXUSTO(devInfo, itnexusto) \ + ((devInfo)->it_NexusTimeout) = itnexusto + +#define DEVINFO_PUT_FBS(devInfo, fbs) \ + ((devInfo)->firstBurstSize) = fbs + +#define DEVINFO_PUT_FLAG(devInfo, tlr) \ + ((devInfo)->flag) = tlr + +#define DEVINFO_PUT_DEV_S_RATE(devInfo, dev_s_rate) \ + ((devInfo)->devType_S_Rate) = dev_s_rate + +/* bit32 -> bit8 array[4] */ +#define DEVINFO_PUT_SAS_ADDRESSLO(devInfo, src32) \ + *(bit32 *)((devInfo)->sasAddressLo) = BIT32_TO_DMA_BEBIT32(src32) + +#define DEVINFO_PUT_SAS_ADDRESSHI(devInfo, src32) \ + *(bit32 *)((devInfo)->sasAddressHi) = BIT32_TO_DMA_BEBIT32(src32) + +#define DEVINFO_PUT_INITIATOR_SSP_STP_SMP(devInfo, ini_ssp_stp_smp) \ + ((devInfo)->initiator_ssp_stp_smp) = ini_ssp_stp_smp + +#define DEVINFO_PUT_TARGET_SSP_STP_SMP(devInfo, tgt_ssp_stp_smp) \ + ((devInfo)->target_ssp_stp_smp) = tgt_ssp_stp_smp + +#define DEVINFO_PUT_EXT(devInfo, extension) \ + ((devInfo)->ext) = extension + +#endif /* __DMDEFS_H__ */ + diff --git a/sys/dev/pms/RefTisa/discovery/dm/dmdisc.c b/sys/dev/pms/RefTisa/discovery/dm/dmdisc.c new file mode 100644 index 000000000000..a792fbe1e681 --- /dev/null +++ b/sys/dev/pms/RefTisa/discovery/dm/dmdisc.c @@ -0,0 +1,7466 @@ +/******************************************************************************* +** +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +** +********************************************************************************/ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#include +#include + +#include +#include +#include + +#ifdef FDS_DM +#include +#include +#include + +#include +#include +#include + +/*****************************************************************************/ +/*! \brief dmDiscover + * + * + * Purpose: A discovery is started by this function + * + * \param dmRoot: DM context handle. + * \param dmPortContext: Pointer to this instance of port context + * \param option: Discovery option + * + * \return: + * DM_RC_SUCCESS + * DM_RC_FAILURE + * + */ +/*****************************************************************************/ +osGLOBAL bit32 +dmDiscover( + dmRoot_t *dmRoot, + dmPortContext_t *dmPortContext, + bit32 option) +{ + dmIntPortContext_t *onePortContext = agNULL; + bit32 ret = DM_RC_FAILURE; + + DM_DBG3(("dmDiscover: start\n")); + onePortContext = (dmIntPortContext_t *)dmPortContext->dmData; + + if (onePortContext == agNULL) + { + DM_DBG1(("dmDiscover: onePortContext is NULL!!!\n")); + return DM_RC_FAILURE; + } + + if (onePortContext->valid == agFALSE) + { + DM_DBG1(("dmDiscover: invalid port!!!\n")); + return DM_RC_FAILURE; + } + + if (onePortContext->RegFailed == agTRUE) + { + DM_DBG1(("dmDiscover: Registration failed!!!\n")); + return DM_RC_FAILURE; + } + + switch ( option ) + { + case DM_DISCOVERY_OPTION_FULL_START: + DM_DBG3(("dmDiscover: full, pid %d\n", onePortContext->id)); + onePortContext->discovery.type = DM_DISCOVERY_OPTION_FULL_START; + dmDiscoveryResetMCN(dmRoot, onePortContext); + ret = dmFullDiscover(dmRoot, onePortContext); + break; + case DM_DISCOVERY_OPTION_INCREMENTAL_START: + DM_DBG3(("dmDiscover: incremental, pid %d\n", onePortContext->id)); + onePortContext->discovery.type = DM_DISCOVERY_OPTION_INCREMENTAL_START; + dmDiscoveryResetMCN(dmRoot, onePortContext); + ret = dmIncrementalDiscover(dmRoot, onePortContext, agFALSE); + break; + case DM_DISCOVERY_OPTION_ABORT: + DM_DBG3(("dmDiscover: abort\n")); + if (onePortContext->DiscoveryState != DM_DSTATE_COMPLETED) + { + if (onePortContext->discovery.pendingSMP == 0) + { + dmDiscoverAbort(dmRoot, onePortContext); + tddmDiscoverCB( + dmRoot, + onePortContext->dmPortContext, + dmDiscAborted + ); + } + else + { + DM_DBG3(("dmDiscover: abortInProgress\n")); + onePortContext->DiscoveryAbortInProgress = agTRUE; + tddmDiscoverCB( + dmRoot, + dmPortContext, + dmDiscAbortInProgress + ); + } + } + else + { + DM_DBG3(("dmDiscover: no discovery to abort\n")); + tddmDiscoverCB( + dmRoot, + dmPortContext, + dmDiscAbortInvalid + ); + } + ret = DM_RC_SUCCESS; + break; + default: + break; + } + return ret; +} + +osGLOBAL bit32 +dmFullDiscover( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ) +{ + dmExpander_t *oneExpander = agNULL; + dmSASSubID_t dmSASSubID; + dmDeviceData_t *oneExpDeviceData = agNULL; + + DM_DBG1(("dmFullDiscover: start\n")); + + if (onePortContext->valid == agFALSE) + { + DM_DBG1(("dmFullDiscover: invalid port!!!\n")); + return DM_RC_FAILURE; + } + + if (onePortContext->DiscoveryState == DM_DSTATE_STARTED) + { + DM_DBG1(("dmFullDiscover: no two instances of discovery allowed!!!\n")); + return DM_RC_FAILURE; + } + + onePortContext->DiscoveryState = DM_DSTATE_STARTED; + + dmSASSubID.sasAddressHi = onePortContext->sasRemoteAddressHi; + dmSASSubID.sasAddressLo = onePortContext->sasRemoteAddressLo; + + /* check OnePortContext->discovery.discoveringExpanderList */ + oneExpander = dmExpFind(dmRoot, onePortContext, dmSASSubID.sasAddressHi, dmSASSubID.sasAddressLo); + if (oneExpander != agNULL) + { + oneExpDeviceData = oneExpander->dmDevice; + } + else + { + /* check dmAllShared->mainExpanderList */ + oneExpander = dmExpMainListFind(dmRoot, onePortContext, dmSASSubID.sasAddressHi, dmSASSubID.sasAddressLo); + if (oneExpander != agNULL) + { + oneExpDeviceData = oneExpander->dmDevice; + } + } + + if (oneExpDeviceData != agNULL) + { + dmSASSubID.initiator_ssp_stp_smp = oneExpDeviceData->initiator_ssp_stp_smp; + dmSASSubID.target_ssp_stp_smp = oneExpDeviceData->target_ssp_stp_smp; + oneExpDeviceData->registered = agTRUE; + dmAddSASToSharedcontext(dmRoot, onePortContext, &dmSASSubID, oneExpDeviceData, 0xFF); + } + else + { + DM_DBG1(("dmFullDiscover:oneExpDeviceData is NULL!!!\n")); + return DM_RC_FAILURE; + } + + dmUpStreamDiscoverStart(dmRoot, onePortContext); + + return DM_RC_SUCCESS; +} + +osGLOBAL bit32 +dmIncrementalDiscover( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + bit32 flag + ) +{ + dmExpander_t *oneExpander = agNULL; + dmSASSubID_t dmSASSubID; + dmDeviceData_t *oneExpDeviceData = agNULL; + + DM_DBG1(("dmIncrementalDiscover: start\n")); + + if (onePortContext->valid == agFALSE) + { + DM_DBG1(("dmIncrementalDiscover: invalid port!!!\n")); + return DM_RC_FAILURE; + } + + /* TDM triggerred; let go DM triggerred */ + if (flag == agFALSE) + { + if (onePortContext->DiscoveryState == DM_DSTATE_STARTED) + { + DM_DBG1(("dmIncrementalDiscover: no two instances of discovery allowed!!!\n")); + return DM_RC_FAILURE; + } + } + + onePortContext->DiscoveryState = DM_DSTATE_STARTED; + onePortContext->discovery.type = DM_DISCOVERY_OPTION_INCREMENTAL_START; + + dmSASSubID.sasAddressHi = onePortContext->sasRemoteAddressHi; + dmSASSubID.sasAddressLo = onePortContext->sasRemoteAddressLo; + + /* check OnePortContext->discovery.discoveringExpanderList */ + oneExpander = dmExpFind(dmRoot, onePortContext, dmSASSubID.sasAddressHi, dmSASSubID.sasAddressLo); + if (oneExpander != agNULL) + { + oneExpDeviceData = oneExpander->dmDevice; + } + else + { + /* check dmAllShared->mainExpanderList */ + oneExpander = dmExpMainListFind(dmRoot, onePortContext, dmSASSubID.sasAddressHi, dmSASSubID.sasAddressLo); + if (oneExpander != agNULL) + { + oneExpDeviceData = oneExpander->dmDevice; + } + } + + if (oneExpDeviceData != agNULL) + { + dmSASSubID.initiator_ssp_stp_smp = oneExpDeviceData->initiator_ssp_stp_smp; + dmSASSubID.target_ssp_stp_smp = oneExpDeviceData->target_ssp_stp_smp; + oneExpDeviceData->registered = agTRUE; + dmAddSASToSharedcontext(dmRoot, onePortContext, &dmSASSubID, oneExpDeviceData, 0xFF); + } + else + { + DM_DBG1(("dmIncrementalDiscover:oneExpDeviceData is NULL!!!\n")); + return DM_RC_FAILURE; + } + + dmUpStreamDiscoverStart(dmRoot, onePortContext); + + return DM_RC_SUCCESS; +} + +osGLOBAL void +dmUpStreamDiscoverStart( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ) +{ +// dmExpander_t *oneExpander = agNULL; + bit32 sasAddressHi, sasAddressLo; + dmDeviceData_t *oneDeviceData; + dmExpander_t *oneExpander = agNULL; + + DM_DBG3(("dmUpStreamDiscoverStart: start\n")); + if (onePortContext->valid == agFALSE) + { + DM_DBG1(("dmUpStreamDiscoverStart: invalid port!!!\n")); + return; + } + /* + at this point, the 1st expander should have been registered. + find an expander from onePortContext + */ + sasAddressHi = onePortContext->sasRemoteAddressHi; + sasAddressLo = onePortContext->sasRemoteAddressLo; + DM_DBG3(("dmUpStreamDiscoverStart: Port Remote AddrHi 0x%08x Remote AddrLo 0x%08x\n", sasAddressHi, sasAddressLo)); + + oneDeviceData = dmDeviceFind(dmRoot, onePortContext, sasAddressHi, sasAddressLo); + +// oneDeviceData = oneExpander->dmDevice; +// start here + onePortContext->discovery.status = DISCOVERY_UP_STREAM; + if (oneDeviceData == agNULL) + { + DM_DBG1(("dmUpStreamDiscoverStart: oneExpander is NULL, wrong!!!\n")); + return; + } + else + { + if ( (oneDeviceData->SASSpecDeviceType == SAS_EDGE_EXPANDER_DEVICE) + || + (oneDeviceData->SASSpecDeviceType == SAS_FANOUT_EXPANDER_DEVICE) + || + DEVICE_IS_SMP_TARGET(oneDeviceData) + ) + { +#if 1 /* for incremental discovery */ + /* start here: if not on discoveringExpanderList, alloc and add + dmNewEXPorNot() + */ + oneExpander = dmExpFind(dmRoot, onePortContext, sasAddressHi, sasAddressLo); + if ( oneExpander == agNULL) + { + /* alloc and add */ + oneExpander = dmDiscoveringExpanderAlloc(dmRoot, onePortContext, oneDeviceData); + if ( oneExpander != agNULL) + { + dmDiscoveringExpanderAdd(dmRoot, onePortContext, oneExpander); + } + else + { + DM_DBG1(("dmUpStreamDiscoverStart: failed to allocate expander or discovey aborted!!!\n")); + return; + } + } +#endif + + dmUpStreamDiscovering(dmRoot, onePortContext, oneDeviceData); + } + else + { + DM_DBG1(("dmUpStreamDiscoverStart: oneDeviceData is not an Expander did %d, wrong!!!\n", oneDeviceData->id)); + return; + } + } + return; +} + +/* sends report general */ +osGLOBAL void +dmUpStreamDiscovering( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmDeviceData_t *oneDeviceData + ) +{ + dmList_t *ExpanderList; + dmExpander_t *oneNextExpander = agNULL; + + DM_DBG3(("dmUpStreamDiscovering: start\n")); + + if (onePortContext->valid == agFALSE) + { + DM_DBG1(("dmUpStreamDiscovering: invalid port!!!\n")); + return; + } + + tddmSingleThreadedEnter(dmRoot, DM_EXPANDER_LOCK); + if (DMLIST_EMPTY(&(onePortContext->discovery.discoveringExpanderList))) + { + tddmSingleThreadedLeave(dmRoot, DM_EXPANDER_LOCK); + DM_DBG3(("dmUpStreamDiscovering: should be the end\n")); + oneNextExpander = agNULL; + } + else + { + DMLIST_DEQUEUE_FROM_HEAD(&ExpanderList, &(onePortContext->discovery.discoveringExpanderList)); + oneNextExpander = DMLIST_OBJECT_BASE(dmExpander_t, linkNode, ExpanderList); + if ( oneNextExpander != agNULL) + { + DMLIST_ENQUEUE_AT_HEAD(&(oneNextExpander->linkNode), &(onePortContext->discovery.discoveringExpanderList)); + DM_DBG3(("dmUpStreamDiscovering tdsaSASUpStreamDiscovering: dequeue head\n")); + DM_DBG3(("dmUpStreamDiscovering: expander id %d\n", oneNextExpander->id)); + } + else + { + DM_DBG1(("dmUpStreamDiscovering: oneNextExpander is NULL!!!\n")); + } + tddmSingleThreadedLeave(dmRoot, DM_EXPANDER_LOCK); + + } + + if (oneNextExpander != agNULL) + { + dmReportGeneralSend(dmRoot, oneNextExpander->dmDevice); + } + else + { + DM_DBG3(("dmUpStreamDiscovering: No more expander list\n")); + dmDownStreamDiscoverStart(dmRoot, onePortContext, oneDeviceData); + } + + return; +} + +osGLOBAL void +dmDownStreamDiscoverStart( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmDeviceData_t *oneDeviceData + ) +{ + dmExpander_t *UpStreamExpander; + dmExpander_t *oneExpander; + + DM_DBG3(("dmDownStreamDiscoverStart: start\n")); + + if (dmDiscoverCheck(dmRoot, onePortContext) == agTRUE) + { + DM_DBG1(("dmDownStreamDiscoverStart: invalid port or aborted discovery!!!\n")); + return; + } + + /* set discovery status */ + onePortContext->discovery.status = DISCOVERY_DOWN_STREAM; + + /* If it's an expander */ + if ( (oneDeviceData->SASSpecDeviceType == SAS_EDGE_EXPANDER_DEVICE) + || (oneDeviceData->SASSpecDeviceType == SAS_FANOUT_EXPANDER_DEVICE) + || DEVICE_IS_SMP_TARGET(oneDeviceData) + ) + { + oneExpander = oneDeviceData->dmExpander; + UpStreamExpander = oneExpander->dmUpStreamExpander; + + /* If the two expanders are the root of two edge sets; sub-to-sub */ + if ( (UpStreamExpander != agNULL) && ( UpStreamExpander->dmUpStreamExpander == oneExpander ) ) + { + DM_DBG3(("dmDownStreamDiscoverStart: Root found pExpander=%p pUpStreamExpander=%p\n", + oneExpander, UpStreamExpander)); + //Saves the root expander + onePortContext->discovery.RootExp = oneExpander; + DM_DBG3(("dmDownStreamDiscoverStart: Root exp addrHi 0x%08x\n", oneExpander->dmDevice->SASAddressID.sasAddressHi)); + DM_DBG3(("dmDownStreamDiscoverStart: Root exp addrLo 0x%08x\n", oneExpander->dmDevice->SASAddressID.sasAddressLo)); + + /* reset up stream inform for pExpander */ + oneExpander->dmUpStreamExpander = agNULL; + /* Add the pExpander to discovering list */ + dmDiscoveringExpanderAdd(dmRoot, onePortContext, oneExpander); + + /* reset up stream inform for oneExpander */ + UpStreamExpander->dmUpStreamExpander = agNULL; + /* Add the UpStreamExpander to discovering list */ + dmDiscoveringExpanderAdd(dmRoot, onePortContext, UpStreamExpander); + } + /* If the two expanders are not the root of two edge sets. eg) one root */ + else + { + //Saves the root expander + onePortContext->discovery.RootExp = oneExpander; + + DM_DBG3(("dmDownStreamDiscoverStart: NO Root pExpander=%p\n", oneExpander)); + DM_DBG3(("dmDownStreamDiscoverStart: Root exp addrHi 0x%08x\n", oneExpander->dmDevice->SASAddressID.sasAddressHi)); + DM_DBG3(("dmDownStreamDiscoverStart: Root exp addrLo 0x%08x\n", oneExpander->dmDevice->SASAddressID.sasAddressLo)); + + /* (2.2.2.1) Add the pExpander to discovering list */ + dmDiscoveringExpanderAdd(dmRoot, onePortContext, oneExpander); + } + } + + /* Continue down stream discovering */ + dmDownStreamDiscovering(dmRoot, onePortContext, oneDeviceData); + + return; +} + +osGLOBAL void +dmDownStreamDiscovering( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmDeviceData_t *oneDeviceData + ) +{ + dmExpander_t *NextExpander = agNULL; + dmList_t *ExpanderList; + + DM_DBG3(("dmDownStreamDiscovering: start\n")); + + if (dmDiscoverCheck(dmRoot, onePortContext) == agTRUE) + { + DM_DBG1(("dmDownStreamDiscovering: invalid port or aborted discovery!!!\n")); + return; + } + + tddmSingleThreadedEnter(dmRoot, DM_EXPANDER_LOCK); + if (DMLIST_EMPTY(&(onePortContext->discovery.discoveringExpanderList))) + { + tddmSingleThreadedLeave(dmRoot, DM_EXPANDER_LOCK); + DM_DBG3(("dmDownStreamDiscovering: should be the end\n")); + NextExpander = agNULL; + } + else + { + DMLIST_DEQUEUE_FROM_HEAD(&ExpanderList, &(onePortContext->discovery.discoveringExpanderList));; + NextExpander = DMLIST_OBJECT_BASE(dmExpander_t, linkNode, ExpanderList); + if ( NextExpander != agNULL) + { + DMLIST_ENQUEUE_AT_HEAD(&(NextExpander->linkNode), &(onePortContext->discovery.discoveringExpanderList));; + DM_DBG3(("dmDownStreamDiscovering tdsaSASDownStreamDiscovering: dequeue head\n")); + DM_DBG3(("dmDownStreamDiscovering: expander id %d\n", NextExpander->id)); + } + else + { + DM_DBG1(("dmDownStreamDiscovering: NextExpander is NULL!!!\n")); + } + tddmSingleThreadedLeave(dmRoot, DM_EXPANDER_LOCK); + + } + + /* If there is an expander for continue discoving */ + if ( NextExpander != agNULL) + { + DM_DBG3(("dmDownStreamDiscovering: Found pNextExpander=%p discoveryStatus=0x%x\n", + NextExpander, onePortContext->discovery.status)); + + switch (onePortContext->discovery.status) + { + /* If the discovery status is DISCOVERY_DOWN_STREAM */ + case DISCOVERY_DOWN_STREAM: + /* Send report general for the next expander */ + DM_DBG3(("dmDownStreamDiscovering: DownStream pNextExpander=%p\n", NextExpander)); + DM_DBG3(("dmDownStreamDiscovering: oneDeviceData %p did %d\n", oneDeviceData, oneDeviceData->id)); + DM_DBG3(("dmDownStreamDiscovering: oneExpander %p did %d\n", oneDeviceData->dmExpander, oneDeviceData->dmExpander->id)); + + DM_DBG3(("dmDownStreamDiscovering: 2nd oneDeviceData %p did %d\n", NextExpander->dmDevice, NextExpander->dmDevice->id)); + DM_DBG3(("dmDownStreamDiscovering: 2nd oneExpander %p did %d\n", NextExpander, NextExpander->id)); + DM_DBG3(("dmDownStreamDiscovering: 2nd used oneExpander %p did %d\n", NextExpander->dmDevice->dmExpander, NextExpander->dmDevice->dmExpander->id)); + + if (NextExpander != NextExpander->dmDevice->dmExpander) + { + DM_DBG3(("dmDownStreamDiscovering: wrong!!!\n")); + } + + + dmReportGeneralSend(dmRoot, NextExpander->dmDevice); + break; + /* If the discovery status is DISCOVERY_CONFIG_ROUTING */ + case DISCOVERY_CONFIG_ROUTING: + case DISCOVERY_REPORT_PHY_SATA: + + /* set discovery status */ + onePortContext->discovery.status = DISCOVERY_DOWN_STREAM; + + DM_DBG3(("dmDownStreamDiscovering: pPort->discovery.status=DISCOVERY_CONFIG_ROUTING, make it DOWN_STREAM\n")); + /* If not the last phy */ + if ( NextExpander->discoveringPhyId < NextExpander->dmDevice->numOfPhys ) + { + DM_DBG3(("dmDownStreamDiscovering: pNextExpander->discoveringPhyId=0x%x pNextExpander->numOfPhys=0x%x. Send More Discover\n", + NextExpander->discoveringPhyId, NextExpander->dmDevice->numOfPhys)); + /* Send discover for the next expander */ + dmDiscoverSend(dmRoot, NextExpander->dmDevice); + } + /* If it's the last phy */ + else + { + DM_DBG3(("dmDownStreamDiscovering: Last Phy, remove expander%p start DownStream=%p\n", + NextExpander, NextExpander->dmDevice)); + dmDiscoveringExpanderRemove(dmRoot, onePortContext, NextExpander); + dmDownStreamDiscovering(dmRoot, onePortContext, NextExpander->dmDevice); + } + break; + + default: + DM_DBG3(("dmDownStreamDiscovering: *** Unknown pPort->discovery.status=0x%x\n", onePortContext->discovery.status)); + } + } + /* If no expander for continue discoving */ + else + { + DM_DBG3(("dmDownStreamDiscovering: No more expander DONE\n")); + /* discover done */ + dmDiscoverDone(dmRoot, onePortContext, DM_RC_SUCCESS); + } + + + return; +} + +osGLOBAL void +dmUpStreamDiscoverExpanderPhy( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmExpander_t *oneExpander, + smpRespDiscover_t *pDiscoverResp + ) +{ + agsaSASIdentify_t sasIdentify; + dmSASSubID_t dmSASSubID; + bit32 attachedSasHi, attachedSasLo; + dmExpander_t *AttachedExpander = agNULL; + bit8 connectionRate; + dmDeviceData_t *oneDeviceData = agNULL; + dmDeviceData_t *AttachedDevice = agNULL; + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + + + DM_DBG3(("dmUpStreamDiscoverExpanderPhy: start\n")); + + if (dmDiscoverCheck(dmRoot, onePortContext) == agTRUE) + { + DM_DBG1(("dmUpStreamDiscoverExpanderPhy: invalid port or aborted discovery!!!\n")); + return; + } + + if (oneExpander != oneExpander->dmDevice->dmExpander) + { + DM_DBG1(("dmUpStreamDiscoverExpanderPhy: wrong!!!\n")); + } + + dm_memset(&sasIdentify, 0, sizeof(agsaSASIdentify_t)); + + oneDeviceData = oneExpander->dmDevice; + + DM_DBG3(("dmUpStreamDiscoverExpanderPhy: Phy #%d of SAS %08x-%08x\n", + oneExpander->discoveringPhyId, + oneDeviceData->SASAddressID.sasAddressHi, + oneDeviceData->SASAddressID.sasAddressLo)); + + DM_DBG3((" Attached device: %s\n", + ( DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == 0 ? "No Device" : + (DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == 1 ? "End Device" : + (DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == 2 ? "Edge Expander" : "Fanout Expander"))))); + + + if ( DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) != SAS_NO_DEVICE) + { + DM_DBG3((" SAS address : %08x-%08x\n", + DISCRSP_GET_ATTACHED_SAS_ADDRESSHI(pDiscoverResp), + DISCRSP_GET_ATTACHED_SAS_ADDRESSLO(pDiscoverResp))); + DM_DBG3((" SSP Target : %d\n", DISCRSP_IS_SSP_TARGET(pDiscoverResp)?1:0)); + DM_DBG3((" STP Target : %d\n", DISCRSP_IS_STP_TARGET(pDiscoverResp)?1:0)); + DM_DBG3((" SMP Target : %d\n", DISCRSP_IS_SMP_TARGET(pDiscoverResp)?1:0)); + DM_DBG3((" SATA DEVICE : %d\n", DISCRSP_IS_SATA_DEVICE(pDiscoverResp)?1:0)); + DM_DBG3((" SSP Initiator : %d\n", DISCRSP_IS_SSP_INITIATOR(pDiscoverResp)?1:0)); + DM_DBG3((" STP Initiator : %d\n", DISCRSP_IS_STP_INITIATOR(pDiscoverResp)?1:0)); + DM_DBG3((" SMP Initiator : %d\n", DISCRSP_IS_SMP_INITIATOR(pDiscoverResp)?1:0)); + DM_DBG3((" Phy ID : %d\n", pDiscoverResp->phyIdentifier)); + DM_DBG3((" Attached Phy ID: %d\n", pDiscoverResp->attachedPhyIdentifier)); + } + + /* for debugging */ + if (oneExpander->discoveringPhyId != pDiscoverResp->phyIdentifier) + { + DM_DBG1(("dmUpStreamDiscoverExpanderPhy: !!! Incorrect SMP response !!!\n")); + DM_DBG1(("dmUpStreamDiscoverExpanderPhy: Request PhyID #%d Response PhyID #%d !!!\n", oneExpander->discoveringPhyId, pDiscoverResp->phyIdentifier)); + dmhexdump("NO_DEVICE", (bit8*)pDiscoverResp, sizeof(smpRespDiscover_t)); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + return; + } + + /* saving routing attribute for non self-configuring expanders */ + oneExpander->routingAttribute[pDiscoverResp->phyIdentifier] = (bit8)DISCRSP_GET_ROUTINGATTRIB(pDiscoverResp); + + if ( oneDeviceData->SASSpecDeviceType == SAS_FANOUT_EXPANDER_DEVICE ) + { + DM_DBG3(("dmUpStreamDiscoverExpanderPhy: SA_SAS_DEV_TYPE_FANOUT_EXPANDER\n")); + if ( DISCRSP_GET_ROUTINGATTRIB(pDiscoverResp) == SAS_ROUTING_SUBTRACTIVE) + { + DM_DBG1(("dmUpStreamDiscoverExpanderPhy: **** Topology Error subtractive routing on fanout expander device!!!\n")); + + /* discovery error */ + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier = oneExpander->discoveringPhyId; + DM_DBG1(("dmUpStreamDiscoverExpanderPhy: sasAddressHi 0x%08x sasAddressLo 0x%08x phyid 0x%x\n", + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi, + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo, + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier)); + + /* (2.1.3) discovery done */ + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + return; + } + } + else + { + DM_DBG3(("dmUpStreamDiscoverExpanderPhy: SA_SAS_DEV_TYPE_EDGE_EXPANDER\n")); + if ( DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) != SAS_NO_DEVICE) + { + /* Setup sasIdentify for the attached device */ + sasIdentify.phyIdentifier = pDiscoverResp->phyIdentifier; + sasIdentify.deviceType_addressFrameType = (bit8)(pDiscoverResp->attachedDeviceType & 0x70); + sasIdentify.initiator_ssp_stp_smp = pDiscoverResp->attached_Ssp_Stp_Smp_Sata_Initiator; + sasIdentify.target_ssp_stp_smp = pDiscoverResp->attached_SataPS_Ssp_Stp_Smp_Sata_Target; + *(bit32*)sasIdentify.sasAddressHi = *(bit32*)pDiscoverResp->attachedSasAddressHi; + *(bit32*)sasIdentify.sasAddressLo = *(bit32*)pDiscoverResp->attachedSasAddressLo; + + /* incremental discovery */ + dmSASSubID.sasAddressHi = SA_IDFRM_GET_SAS_ADDRESSHI(&sasIdentify); + dmSASSubID.sasAddressLo = SA_IDFRM_GET_SAS_ADDRESSLO(&sasIdentify); + dmSASSubID.initiator_ssp_stp_smp = sasIdentify.initiator_ssp_stp_smp; + dmSASSubID.target_ssp_stp_smp = sasIdentify.target_ssp_stp_smp; + + attachedSasHi = DISCRSP_GET_ATTACHED_SAS_ADDRESSHI(pDiscoverResp); + attachedSasLo = DISCRSP_GET_ATTACHED_SAS_ADDRESSLO(pDiscoverResp); + + /* If the phy has subtractive routing attribute */ + if ( DISCRSP_GET_ROUTINGATTRIB(pDiscoverResp) == SAS_ROUTING_SUBTRACTIVE) + { + DM_DBG3(("dmUpStreamDiscoverExpanderPhy: SA_SAS_ROUTING_SUBTRACTIVE\n")); + /* Setup upstream phys */ + dmExpanderUpStreamPhyAdd(dmRoot, oneExpander, (bit8) pDiscoverResp->attachedPhyIdentifier); + /* If the expander already has an upsteam device set up */ + if (oneExpander->hasUpStreamDevice == agTRUE) + { + /* just to update MCN */ + dmPortSASDeviceFind(dmRoot, onePortContext, attachedSasLo, attachedSasHi, oneDeviceData); + /* If the sas address doesn't match */ + if ( ((oneExpander->upStreamSASAddressHi != attachedSasHi) || + (oneExpander->upStreamSASAddressLo != attachedSasLo)) && + (DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_EDGE_EXPANDER_DEVICE || + DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_FANOUT_EXPANDER_DEVICE) + ) + { + /* TODO: discovery error, callback */ + DM_DBG1(("dmUpStreamDiscoverExpanderPhy: **** Topology Error subtractive routing error - inconsistent SAS address!!!\n")); + /* call back to notify discovery error */ + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier = oneExpander->discoveringPhyId; + DM_DBG1(("dmUpStreamDiscoverExpanderPhy: sasAddressHi 0x%08x sasAddressLo 0x%08x phyid 0x%x\n", + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi, + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo, + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier)); + /* discovery done */ + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + } + else + { + /* Setup SAS address for up stream device */ + oneExpander->hasUpStreamDevice = agTRUE; + oneExpander->upStreamSASAddressHi = attachedSasHi; + oneExpander->upStreamSASAddressLo = attachedSasLo; + if ( (onePortContext->sasLocalAddressHi != attachedSasHi) + || (onePortContext->sasLocalAddressLo != attachedSasLo) ) + { + /* Find the device from the discovered list */ + AttachedDevice = dmPortSASDeviceFind(dmRoot, onePortContext, attachedSasLo, attachedSasHi, oneDeviceData); + /* New device, If the device has been discovered before */ + if ( AttachedDevice != agNULL) /* old device */ + { + DM_DBG3(("dmUpStreamDiscoverExpanderPhy: Seen This Device Before\n")); + /* If attached device is an edge expander */ + if ( AttachedDevice->SASSpecDeviceType == SAS_EDGE_EXPANDER_DEVICE) + { + /* The attached device is an expander */ + AttachedExpander = AttachedDevice->dmExpander; + /* If the two expanders are the root of the two edge expander sets */ + if ( (AttachedExpander->upStreamSASAddressHi == + DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo)) + && (AttachedExpander->upStreamSASAddressLo == + DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo)) ) + { + /* Setup upstream expander for the pExpander */ + oneExpander->dmUpStreamExpander = AttachedExpander; + } + /* If the two expanders are not the root of the two edge expander sets */ + else + { + /* TODO: loop found, discovery error, callback */ + DM_DBG1(("dmUpStreamDiscoverExpanderPhy: **** Topology Error loop detection!!!\n")); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier = oneExpander->discoveringPhyId; + DM_DBG1(("dmUpStreamDiscoverExpanderPhy: sasAddressHi 0x%08x sasAddressLo 0x%08x phyid 0x%x\n", + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi, + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo, + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier)); + /* discovery done */ + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + } + /* If attached device is not an edge expander */ + else + { + /*TODO: should not happen, ASSERT */ + DM_DBG3(("dmUpStreamDiscoverExpanderPhy, *** Attached Device is not Edge. Confused!!!\n")); + } + } /* AttachedExpander != agNULL */ + /* New device, If the device has not been discovered before */ + else /* new device */ + { + /* Add the device */ + DM_DBG3(("dmUpStreamDiscoverExpanderPhy: New device\n")); + /* read minimum rate from the configuration + onePortContext->LinkRate is SPC's local link rate + */ + connectionRate = (bit8)MIN(onePortContext->LinkRate, DISCRSP_GET_LINKRATE(pDiscoverResp)); + DM_DBG3(("dmUpStreamDiscoverExpanderPhy: link rate 0x%x\n", onePortContext->LinkRate)); + DM_DBG3(("dmUpStreamDiscoverExpanderPhy: negotiatedPhyLinkRate 0x%x\n", DISCRSP_GET_LINKRATE(pDiscoverResp))); + DM_DBG3(("dmUpStreamDiscoverExpanderPhy: connectionRate 0x%x\n", connectionRate)); + if (DISCRSP_IS_STP_TARGET(pDiscoverResp) || DISCRSP_IS_SATA_DEVICE(pDiscoverResp)) + { + /* incremental discovery */ + if (onePortContext->discovery.type == DM_DISCOVERY_OPTION_FULL_START) + { + AttachedDevice = dmPortSASDeviceAdd( + dmRoot, + onePortContext, + sasIdentify, + agFALSE, + connectionRate, + dmAllShared->itNexusTimeout, + 0, + STP_DEVICE_TYPE, + oneDeviceData, + oneExpander, + pDiscoverResp->phyIdentifier + ); + } + else + { + /* incremental discovery */ + AttachedDevice = dmFindRegNValid( + dmRoot, + onePortContext, + &dmSASSubID + ); + /* not registered and not valid; add this*/ + if (AttachedDevice == agNULL) + { + AttachedDevice = dmPortSASDeviceAdd( + dmRoot, + onePortContext, + sasIdentify, + agFALSE, + connectionRate, + dmAllShared->itNexusTimeout, + 0, + STP_DEVICE_TYPE, + oneDeviceData, + oneExpander, + pDiscoverResp->phyIdentifier + ); + } + } + } /* DISCRSP_IS_STP_TARGET(pDiscoverResp) || DISCRSP_IS_SATA_DEVICE(pDiscoverResp) */ + else + { + /* incremental discovery */ + if (onePortContext->discovery.type == DM_DISCOVERY_OPTION_FULL_START) + { + AttachedDevice = dmPortSASDeviceAdd( + dmRoot, + onePortContext, + sasIdentify, + agFALSE, + connectionRate, + dmAllShared->itNexusTimeout, + 0, + SAS_DEVICE_TYPE, + oneDeviceData, + oneExpander, + pDiscoverResp->phyIdentifier + ); + } + else + { + /* incremental discovery */ + AttachedDevice = dmFindRegNValid( + dmRoot, + onePortContext, + &dmSASSubID + ); + /* not registered and not valid; add this*/ + if (AttachedDevice == agNULL) + { + AttachedDevice = dmPortSASDeviceAdd( + dmRoot, + onePortContext, + sasIdentify, + agFALSE, + connectionRate, + dmAllShared->itNexusTimeout, + 0, + SAS_DEVICE_TYPE, + oneDeviceData, + oneExpander, + pDiscoverResp->phyIdentifier + ); + } + } + } + /* If the device is added successfully */ + if ( AttachedDevice != agNULL) + { + + /* (3.1.2.3.2.3.2.1) callback about new device */ + if ( DISCRSP_IS_SSP_TARGET(pDiscoverResp) + || DISCRSP_IS_SSP_INITIATOR(pDiscoverResp) + || DISCRSP_IS_SMP_INITIATOR(pDiscoverResp) + || DISCRSP_IS_SMP_INITIATOR(pDiscoverResp) ) + { + DM_DBG3(("dmUpStreamDiscoverExpanderPhy: Found SSP/SMP SAS %08x-%08x\n", + attachedSasHi, attachedSasLo)); + } + else + { + DM_DBG3(("dmUpStreamDiscoverExpanderPhy: Found a SAS STP device.\n")); + } + /* If the attached device is an expander */ + if ( (DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_EDGE_EXPANDER_DEVICE) + || (DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_FANOUT_EXPANDER_DEVICE) ) + { + /* Allocate an expander data structure */ + AttachedExpander = dmDiscoveringExpanderAlloc( + dmRoot, + onePortContext, + AttachedDevice + ); + + DM_DBG3(("dmUpStreamDiscoverExpanderPhy: Found expander=%p\n", AttachedExpander)); + /* If allocate successfully */ + if ( AttachedExpander != agNULL) + { + /* Add the pAttachedExpander to discovering list */ + dmDiscoveringExpanderAdd(dmRoot, onePortContext, AttachedExpander); + /* Setup upstream expander for the pExpander */ + oneExpander->dmUpStreamExpander = AttachedExpander; + } + /* If failed to allocate */ + else + { + DM_DBG1(("dmUpStreamDiscoverExpanderPhy: Failed to allocate expander data structure!!!\n")); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + } + /* If the attached device is an end device */ + else + { + DM_DBG3(("dmUpStreamDiscoverExpanderPhy: Found end device\n")); + /* LP2006-05-26 added upstream device to the newly found device */ + AttachedDevice->dmExpander = oneExpander; + oneExpander->dmUpStreamExpander = agNULL; + } + } + else + { + DM_DBG1(("dmUpStreamDiscoverExpanderPhy: Failed to add a device!!!\n")); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + + + + } /* else, new device */ + } /* onePortContext->sasLocalAddressLo != attachedSasLo */ + } /* else */ + } /* DISCRSP_GET_ROUTINGATTRIB(pDiscoverResp) == SAS_ROUTING_SUBTRACTIVE */ + } /* DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) != SAS_NO_DEVICE */ + } /* big else */ + + + + oneExpander->discoveringPhyId ++; + if (onePortContext->discovery.status == DISCOVERY_UP_STREAM) + { + if ( oneExpander->discoveringPhyId < oneDeviceData->numOfPhys ) + { + DM_DBG3(("dmUpStreamDiscoverExpanderPhy: DISCOVERY_UP_STREAM find more ...\n")); + /* continue discovery for the next phy */ + dmDiscoverSend(dmRoot, oneDeviceData); + } + else + { + DM_DBG3(("dmUpStreamDiscoverExpanderPhy: DISCOVERY_UP_STREAM last phy continue upstream..\n")); + + /* for MCN */ + dmUpdateAllAdjacent(dmRoot, onePortContext, oneDeviceData); + /* remove the expander from the discovering list */ + dmDiscoveringExpanderRemove(dmRoot, onePortContext, oneExpander); + /* continue upstream discovering */ + dmUpStreamDiscovering(dmRoot, onePortContext, oneDeviceData); + } + } + else + { + DM_DBG3(("dmUpStreamDiscoverExpanderPhy: onePortContext->discovery.status not in DISCOVERY_UP_STREAM; status %d\n", onePortContext->discovery.status)); + + } + + DM_DBG3(("dmUpStreamDiscoverExpanderPhy: end return phyID#%d\n", oneExpander->discoveringPhyId - 1)); + + return; +} + +osGLOBAL void +dmUpStreamDiscover2ExpanderPhy( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmExpander_t *oneExpander, + smpRespDiscover2_t *pDiscoverResp + ) +{ + dmDeviceData_t *oneDeviceData; + dmDeviceData_t *AttachedDevice = agNULL; + dmExpander_t *AttachedExpander; + agsaSASIdentify_t sasIdentify; + bit8 connectionRate; + bit32 attachedSasHi, attachedSasLo; + dmSASSubID_t dmSASSubID; + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + + DM_DBG2(("dmUpStreamDiscover2ExpanderPhy: start\n")); + + if (dmDiscoverCheck(dmRoot, onePortContext) == agTRUE) + { + DM_DBG1(("dmUpStreamDiscover2ExpanderPhy: invalid port or aborted discovery!!!\n")); + return; + } + + if (oneExpander != oneExpander->dmDevice->dmExpander) + { + DM_DBG1(("dmUpStreamDiscover2ExpanderPhy: wrong!!!\n")); + } + + dm_memset(&sasIdentify, 0, sizeof(agsaSASIdentify_t)); + + oneDeviceData = oneExpander->dmDevice; + + DM_DBG2(("dmUpStreamDiscover2ExpanderPhy: Phy #%d of SAS %08x-%08x\n", + oneExpander->discoveringPhyId, + oneDeviceData->SASAddressID.sasAddressHi, + oneDeviceData->SASAddressID.sasAddressLo)); + + DM_DBG2((" Attached device: %s\n", + ( SAS2_DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == 0 ? "No Device" : + (SAS2_DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == 1 ? "End Device" : + (SAS2_DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == 2 ? "Edge Expander" : "Fanout Expander"))))); + + + if ( SAS2_DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) != SAS_NO_DEVICE) + { + DM_DBG2((" SAS address : %08x-%08x\n", + SAS2_DISCRSP_GET_ATTACHED_SAS_ADDRESSHI(pDiscoverResp), + SAS2_DISCRSP_GET_ATTACHED_SAS_ADDRESSLO(pDiscoverResp))); + DM_DBG2((" SSP Target : %d\n", SAS2_DISCRSP_IS_SSP_TARGET(pDiscoverResp)?1:0)); + DM_DBG2((" STP Target : %d\n", SAS2_DISCRSP_IS_STP_TARGET(pDiscoverResp)?1:0)); + DM_DBG2((" SMP Target : %d\n", SAS2_DISCRSP_IS_SMP_TARGET(pDiscoverResp)?1:0)); + DM_DBG2((" SATA DEVICE : %d\n", SAS2_DISCRSP_IS_SATA_DEVICE(pDiscoverResp)?1:0)); + DM_DBG2((" SSP Initiator : %d\n", SAS2_DISCRSP_IS_SSP_INITIATOR(pDiscoverResp)?1:0)); + DM_DBG2((" STP Initiator : %d\n", SAS2_DISCRSP_IS_STP_INITIATOR(pDiscoverResp)?1:0)); + DM_DBG2((" SMP Initiator : %d\n", SAS2_DISCRSP_IS_SMP_INITIATOR(pDiscoverResp)?1:0)); + DM_DBG2((" Phy ID : %d\n", pDiscoverResp->phyIdentifier)); + DM_DBG2((" Attached Phy ID: %d\n", pDiscoverResp->attachedPhyIdentifier)); + } + + if (oneExpander->discoveringPhyId != pDiscoverResp->phyIdentifier) + { + DM_DBG1(("dmUpStreamDiscover2ExpanderPhy: !!! Incorrect SMP response !!!\n")); + DM_DBG1(("dmUpStreamDiscover2ExpanderPhy: Request PhyID #%d Response PhyID #%d\n", oneExpander->discoveringPhyId, pDiscoverResp->phyIdentifier)); + dmhexdump("NO_DEVICE", (bit8*)pDiscoverResp, sizeof(smpRespDiscover2_t)); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + return; + } + + /* saving routing attribute for non self-configuring expanders */ + oneExpander->routingAttribute[pDiscoverResp->phyIdentifier] = SAS2_DISCRSP_GET_ROUTINGATTRIB(pDiscoverResp); + + if ( oneDeviceData->SASSpecDeviceType == SAS_FANOUT_EXPANDER_DEVICE ) + { + DM_DBG2(("dmUpStreamDiscover2ExpanderPhy: SA_SAS_DEV_TYPE_FANOUT_EXPANDER\n")); + if ( SAS2_DISCRSP_GET_ROUTINGATTRIB(pDiscoverResp) == SAS_ROUTING_SUBTRACTIVE) + { + DM_DBG1(("dmUpStreamDiscover2ExpanderPhy: **** Topology Error subtractive routing on fanout expander device!!!\n")); + + /* discovery error */ + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier = oneExpander->discoveringPhyId; + DM_DBG1(("dmUpStreamDiscover2ExpanderPhy: sasAddressHi 0x%08x sasAddressLo 0x%08x phyid 0x%x\n", + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi, + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo, + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier)); + + /* (2.1.3) discovery done */ + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + return; + } + } + else + { + DM_DBG2(("dmUpStreamDiscover2ExpanderPhy: SA_SAS_DEV_TYPE_EDGE_EXPANDER\n")); + + if ( SAS2_DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) != SAS_NO_DEVICE) + { + /* Setup sasIdentify for the attached device */ + sasIdentify.phyIdentifier = pDiscoverResp->phyIdentifier; + sasIdentify.deviceType_addressFrameType = pDiscoverResp->attachedDeviceTypeReason & 0x70; + sasIdentify.initiator_ssp_stp_smp = pDiscoverResp->attached_Ssp_Stp_Smp_Sata_Initiator; + sasIdentify.target_ssp_stp_smp = pDiscoverResp->attached_SataPS_Ssp_Stp_Smp_Sata_Target; + *(bit32*)sasIdentify.sasAddressHi = *(bit32*)pDiscoverResp->attachedSasAddressHi; + *(bit32*)sasIdentify.sasAddressLo = *(bit32*)pDiscoverResp->attachedSasAddressLo; + + /* incremental discovery */ + dmSASSubID.sasAddressHi = SA_IDFRM_GET_SAS_ADDRESSHI(&sasIdentify); + dmSASSubID.sasAddressLo = SA_IDFRM_GET_SAS_ADDRESSLO(&sasIdentify); + dmSASSubID.initiator_ssp_stp_smp = sasIdentify.initiator_ssp_stp_smp; + dmSASSubID.target_ssp_stp_smp = sasIdentify.target_ssp_stp_smp; + + attachedSasHi = SAS2_DISCRSP_GET_ATTACHED_SAS_ADDRESSHI(pDiscoverResp); + attachedSasLo = SAS2_DISCRSP_GET_ATTACHED_SAS_ADDRESSLO(pDiscoverResp); + + /* If the phy has subtractive routing attribute */ + if ( SAS2_DISCRSP_GET_ROUTINGATTRIB(pDiscoverResp) == SAS_ROUTING_SUBTRACTIVE) + { + DM_DBG2(("dmUpStreamDiscover2ExpanderPhy: SA_SAS_ROUTING_SUBTRACTIVE\n")); + /* Setup upstream phys */ + dmExpanderUpStreamPhyAdd(dmRoot, oneExpander, (bit8) pDiscoverResp->attachedPhyIdentifier); + /* If the expander already has an upsteam device set up */ + if (oneExpander->hasUpStreamDevice == agTRUE) + { + /* just to update MCN */ + dmPortSASDeviceFind(dmRoot, onePortContext, attachedSasLo, attachedSasHi, oneDeviceData); + /* If the sas address doesn't match */ + if ( ((oneExpander->upStreamSASAddressHi != attachedSasHi) || + (oneExpander->upStreamSASAddressLo != attachedSasLo)) && + (SAS2_DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_EDGE_EXPANDER_DEVICE || + SAS2_DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_FANOUT_EXPANDER_DEVICE) + ) + { + /* TODO: discovery error, callback */ + DM_DBG1(("dmUpStreamDiscover2ExpanderPhy: **** Topology Error subtractive routing error - inconsistent SAS address!!!\n")); + /* call back to notify discovery error */ + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier = oneExpander->discoveringPhyId; + DM_DBG1(("dmUpStreamDiscover2ExpanderPhy: sasAddressHi 0x%08x sasAddressLo 0x%08x phyid 0x%x\n", + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi, + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo, + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier)); + /* discovery done */ + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + } + else + { + /* Setup SAS address for up stream device */ + oneExpander->hasUpStreamDevice = agTRUE; + oneExpander->upStreamSASAddressHi = attachedSasHi; + oneExpander->upStreamSASAddressLo = attachedSasLo; + + if ( (onePortContext->sasLocalAddressHi != attachedSasHi) + || (onePortContext->sasLocalAddressLo != attachedSasLo) ) + { + /* Find the device from the discovered list */ + AttachedDevice = dmPortSASDeviceFind(dmRoot, onePortContext, attachedSasLo, attachedSasHi, oneDeviceData); + /* If the device has been discovered before */ + if ( AttachedDevice != agNULL) + { + DM_DBG2(("dmUpStreamDiscover2ExpanderPhy: Seen This Device Before\n")); + /* If attached device is an edge expander */ + if ( AttachedDevice->SASSpecDeviceType == SAS_EDGE_EXPANDER_DEVICE) + { + /* The attached device is an expander */ + AttachedExpander = AttachedDevice->dmExpander; + /* If the two expanders are the root of the two edge expander sets */ + if ( (AttachedExpander->upStreamSASAddressHi == + DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo)) + && (AttachedExpander->upStreamSASAddressLo == + DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo)) ) + { + /* Setup upstream expander for the pExpander */ + oneExpander->dmUpStreamExpander = AttachedExpander; + } + /* If the two expanders are not the root of the two edge expander sets */ + else + { + /* TODO: loop found, discovery error, callback */ + DM_DBG1(("dmUpStreamDiscover2ExpanderPhy: **** Topology Error loop detection!!!\n")); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier = oneExpander->discoveringPhyId; + DM_DBG1(("dmUpStreamDiscover2ExpanderPhy: sasAddressHi 0x%08x sasAddressLo 0x%08x phyid 0x%x\n", + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi, + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo, + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier)); + /* discovery done */ + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + } + /* If attached device is not an edge expander */ + else + { + /*TODO: should not happen, ASSERT */ + DM_DBG1(("dmUpStreamDiscover2ExpanderPhy, *** Attached Device is not Edge. Confused!!!\n")); + } + } + /* If the device has not been discovered before */ + else + { + /* Add the device */ + DM_DBG2(("dmUpStreamDiscover2ExpanderPhy: New device\n")); + /* read minimum rate from the configuration + onePortContext->LinkRate is SPC's local link rate + */ + connectionRate = MIN(onePortContext->LinkRate, SAS2_DISCRSP_GET_LOGICAL_LINKRATE(pDiscoverResp)); + DM_DBG2(("dmUpStreamDiscover2ExpanderPhy: link rate 0x%x\n", onePortContext->LinkRate)); + DM_DBG2(("dmUpStreamDiscover2ExpanderPhy: negotiatedPhyLinkRate 0x%x\n", SAS2_DISCRSP_GET_LINKRATE(pDiscoverResp))); + DM_DBG2(("dmUpStreamDiscover2ExpanderPhy: connectionRate 0x%x\n", connectionRate)); + //hhhhhhhh + if (SAS2_DISCRSP_IS_STP_TARGET(pDiscoverResp) || SAS2_DISCRSP_IS_SATA_DEVICE(pDiscoverResp)) + { + /* incremental discovery */ + if (onePortContext->discovery.type == DM_DISCOVERY_OPTION_FULL_START) + { + AttachedDevice = dmPortSASDeviceAdd( + dmRoot, + onePortContext, + sasIdentify, + agFALSE, + connectionRate, + dmAllShared->itNexusTimeout, + 0, + STP_DEVICE_TYPE, + oneDeviceData, + oneExpander, + pDiscoverResp->phyIdentifier + ); + } + else + { + /* incremental discovery */ + AttachedDevice = dmFindRegNValid( + dmRoot, + onePortContext, + &dmSASSubID + ); + /* not registered and not valid; add this*/ + if (AttachedDevice == agNULL) + { + AttachedDevice = dmPortSASDeviceAdd( + dmRoot, + onePortContext, + sasIdentify, + agFALSE, + connectionRate, + dmAllShared->itNexusTimeout, + 0, + STP_DEVICE_TYPE, + oneDeviceData, + oneExpander, + pDiscoverResp->phyIdentifier + ); + } + } + } + else + { + /* incremental discovery */ + if (onePortContext->discovery.type == DM_DISCOVERY_OPTION_FULL_START) + { + AttachedDevice = dmPortSASDeviceAdd( + dmRoot, + onePortContext, + sasIdentify, + agFALSE, + connectionRate, + dmAllShared->itNexusTimeout, + 0, + SAS_DEVICE_TYPE, + oneDeviceData, + oneExpander, + pDiscoverResp->phyIdentifier + ); + } + else + { + /* incremental discovery */ + AttachedDevice = dmFindRegNValid( + dmRoot, + onePortContext, + &dmSASSubID + ); + /* not registered and not valid; add this*/ + if (AttachedDevice == agNULL) + { + AttachedDevice = dmPortSASDeviceAdd( + dmRoot, + onePortContext, + sasIdentify, + agFALSE, + connectionRate, + dmAllShared->itNexusTimeout, + 0, + SAS_DEVICE_TYPE, + oneDeviceData, + oneExpander, + pDiscoverResp->phyIdentifier + ); + } + } + } + /* If the device is added successfully */ + if ( AttachedDevice != agNULL) + { + + /* (3.1.2.3.2.3.2.1) callback about new device */ + if ( SAS2_DISCRSP_IS_SSP_TARGET(pDiscoverResp) + || SAS2_DISCRSP_IS_SSP_INITIATOR(pDiscoverResp) + || SAS2_DISCRSP_IS_SMP_INITIATOR(pDiscoverResp) + || SAS2_DISCRSP_IS_SMP_INITIATOR(pDiscoverResp) ) + { + DM_DBG2(("dmUpStreamDiscover2ExpanderPhy: Found SSP/SMP SAS %08x-%08x\n", + attachedSasHi, attachedSasLo)); + } + else + { + DM_DBG2(("dmUpStreamDiscover2ExpanderPhy: Found a SAS STP device.\n")); + } + /* If the attached device is an expander */ + if ( (SAS2_DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_EDGE_EXPANDER_DEVICE) + || (SAS2_DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_FANOUT_EXPANDER_DEVICE) ) + { + /* Allocate an expander data structure */ + AttachedExpander = dmDiscoveringExpanderAlloc( + dmRoot, + onePortContext, + AttachedDevice + ); + + DM_DBG2(("dmUpStreamDiscover2ExpanderPhy: Found expander=%p\n", AttachedExpander)); + /* If allocate successfully */ + if ( AttachedExpander != agNULL) + { + /* Add the pAttachedExpander to discovering list */ + dmDiscoveringExpanderAdd(dmRoot, onePortContext, AttachedExpander); + /* Setup upstream expander for the pExpander */ + oneExpander->dmUpStreamExpander = AttachedExpander; + } + /* If failed to allocate */ + else + { + DM_DBG1(("dmUpStreamDiscover2ExpanderPhy, Failed to allocate expander data structure!!!\n")); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + } + /* If the attached device is an end device */ + else + { + DM_DBG2(("dmUpStreamDiscover2ExpanderPhy: Found end device\n")); + /* LP2006-05-26 added upstream device to the newly found device */ + AttachedDevice->dmExpander = oneExpander; + oneExpander->dmUpStreamExpander = agNULL; + } + } + else + { + DM_DBG1(("dmUpStreamDiscover2ExpanderPhy, Failed to add a device!!!\n")); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + } + } + } + } /* substractive routing */ + } + } + + oneExpander->discoveringPhyId ++; + if (onePortContext->discovery.status == DISCOVERY_UP_STREAM) + { + if ( oneExpander->discoveringPhyId < oneDeviceData->numOfPhys ) + { + DM_DBG2(("dmUpStreamDiscover2ExpanderPhy: DISCOVERY_UP_STREAM find more ...\n")); + /* continue discovery for the next phy */ + dmDiscoverSend(dmRoot, oneDeviceData); + } + else + { + DM_DBG2(("dmUpStreamDiscover2ExpanderPhy: DISCOVERY_UP_STREAM last phy continue upstream..\n")); + + /* for MCN */ + dmUpdateAllAdjacent(dmRoot, onePortContext, oneDeviceData); + /* remove the expander from the discovering list */ + dmDiscoveringExpanderRemove(dmRoot, onePortContext, oneExpander); + /* continue upstream discovering */ + dmUpStreamDiscovering(dmRoot, onePortContext, oneDeviceData); + } + } + else + { + DM_DBG2(("dmUpStreamDiscover2ExpanderPhy: onePortContext->discovery.status not in DISCOVERY_UP_STREAM; status %d\n", onePortContext->discovery.status)); + + } + + DM_DBG2(("dmUpStreamDiscover2ExpanderPhy: end return phyID#%d\n", oneExpander->discoveringPhyId - 1)); + + return; +} + + +osGLOBAL void +dmDownStreamDiscoverExpanderPhy( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmExpander_t *oneExpander, + smpRespDiscover_t *pDiscoverResp + ) +{ + agsaSASIdentify_t sasIdentify; + dmSASSubID_t dmSASSubID; + bit32 attachedSasHi, attachedSasLo; + dmExpander_t *AttachedExpander; + dmExpander_t *UpStreamExpander; + dmExpander_t *ConfigurableExpander = agNULL; + bit8 connectionRate, negotiatedPhyLinkRate; + bit32 configSASAddressHi; + bit32 configSASAddressLo; + bit32 dupConfigSASAddr = agFALSE; + dmDeviceData_t *oneDeviceData; + dmDeviceData_t *AttachedDevice = agNULL; + bit32 SAS2SAS11Check = agFALSE; + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + + + + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: start\n")); + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: exp addrHi 0x%08x\n", oneExpander->dmDevice->SASAddressID.sasAddressHi)); + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: exp addrLo 0x%08x\n", oneExpander->dmDevice->SASAddressID.sasAddressLo)); + + DM_ASSERT(dmRoot, "(dmDownStreamDiscoverExpanderPhy) dmRoot NULL"); + DM_ASSERT(onePortContext, "(dmDownStreamDiscoverExpanderPhy) pPort NULL"); + DM_ASSERT(oneExpander, "(dmDownStreamDiscoverExpanderPhy) pExpander NULL"); + DM_ASSERT(pDiscoverResp, "(dmDownStreamDiscoverExpanderPhy) pDiscoverResp NULL"); + + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: onePortContxt=%p oneExpander=%p\n", onePortContext, oneExpander)); + + if (dmDiscoverCheck(dmRoot, onePortContext) == agTRUE) + { + DM_DBG1(("dmDownStreamDiscoverExpanderPhy: invalid port or aborted discovery!!!\n")); + return; + } + + if (oneExpander != oneExpander->dmDevice->dmExpander) + { + DM_DBG1(("dmDownStreamDiscoverExpanderPhy: wrong!!!\n")); + } + + /* (1) Find the device structure of the expander */ + oneDeviceData = oneExpander->dmDevice; + + DM_ASSERT(oneDeviceData, "(dmDownStreamDiscoverExpanderPhy) pDevice NULL"); + + /* for debugging */ + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: Phy #%d of SAS %08x-%08x\n", + oneExpander->discoveringPhyId, + oneDeviceData->SASAddressID.sasAddressHi, + oneDeviceData->SASAddressID.sasAddressLo)); + + DM_DBG3((" Attached device: %s\n", + ( DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == 0 ? "No Device" : + (DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == 1 ? "End Device" : + (DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == 2 ? "Edge Expander" : "Fanout Expander"))))); + + + /* for debugging */ + if (oneExpander->discoveringPhyId != pDiscoverResp->phyIdentifier) + { + DM_DBG1(("dmDownStreamDiscoverExpanderPhy: !!! Incorrect SMP response !!!\n")); + DM_DBG1(("dmDownStreamDiscoverExpanderPhy: Request PhyID #%d Response PhyID #%d !!!\n", oneExpander->discoveringPhyId, pDiscoverResp->phyIdentifier)); + dmhexdump("NO_DEVICE", (bit8*)pDiscoverResp, sizeof(smpRespDiscover_t)); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + return; + } + + if ( DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) != SAS_NO_DEVICE) + { + DM_DBG3((" SAS address : %08x-%08x\n", + DISCRSP_GET_ATTACHED_SAS_ADDRESSHI(pDiscoverResp), + DISCRSP_GET_ATTACHED_SAS_ADDRESSLO(pDiscoverResp))); + DM_DBG3((" SSP Target : %d\n", DISCRSP_IS_SSP_TARGET(pDiscoverResp)?1:0)); + DM_DBG3((" STP Target : %d\n", DISCRSP_IS_STP_TARGET(pDiscoverResp)?1:0)); + DM_DBG3((" SMP Target : %d\n", DISCRSP_IS_SMP_TARGET(pDiscoverResp)?1:0)); + DM_DBG3((" SATA DEVICE : %d\n", DISCRSP_IS_SATA_DEVICE(pDiscoverResp)?1:0)); + DM_DBG3((" SSP Initiator : %d\n", DISCRSP_IS_SSP_INITIATOR(pDiscoverResp)?1:0)); + DM_DBG3((" STP Initiator : %d\n", DISCRSP_IS_STP_INITIATOR(pDiscoverResp)?1:0)); + DM_DBG3((" SMP Initiator : %d\n", DISCRSP_IS_SMP_INITIATOR(pDiscoverResp)?1:0)); + DM_DBG3((" Phy ID : %d\n", pDiscoverResp->phyIdentifier)); + DM_DBG3((" Attached Phy ID: %d\n", pDiscoverResp->attachedPhyIdentifier)); + + } + /* end for debugging */ + + /* saving routing attribute for non self-configuring expanders */ + oneExpander->routingAttribute[pDiscoverResp->phyIdentifier] = DISCRSP_GET_ROUTINGATTRIB(pDiscoverResp); + + oneExpander->discoverSMPAllowed = agTRUE; + + /* If a device is attached */ + if ( DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) != SAS_NO_DEVICE) + { + /* Setup sasIdentify for the attached device */ + sasIdentify.phyIdentifier = pDiscoverResp->phyIdentifier; + sasIdentify.deviceType_addressFrameType = pDiscoverResp->attachedDeviceType & 0x70; + sasIdentify.initiator_ssp_stp_smp = pDiscoverResp->attached_Ssp_Stp_Smp_Sata_Initiator; + sasIdentify.target_ssp_stp_smp = pDiscoverResp->attached_SataPS_Ssp_Stp_Smp_Sata_Target; + *(bit32*)sasIdentify.sasAddressHi = *(bit32*)pDiscoverResp->attachedSasAddressHi; + *(bit32*)sasIdentify.sasAddressLo = *(bit32*)pDiscoverResp->attachedSasAddressLo; + + /* incremental discovery */ + dmSASSubID.sasAddressHi = SA_IDFRM_GET_SAS_ADDRESSHI(&sasIdentify); + dmSASSubID.sasAddressLo = SA_IDFRM_GET_SAS_ADDRESSLO(&sasIdentify); + dmSASSubID.initiator_ssp_stp_smp = sasIdentify.initiator_ssp_stp_smp; + dmSASSubID.target_ssp_stp_smp = sasIdentify.target_ssp_stp_smp; + + attachedSasHi = DISCRSP_GET_ATTACHED_SAS_ADDRESSHI(pDiscoverResp); + attachedSasLo = DISCRSP_GET_ATTACHED_SAS_ADDRESSLO(pDiscoverResp); + + /* If it's a direct routing */ + if ( DISCRSP_GET_ROUTINGATTRIB(pDiscoverResp) == SAS_ROUTING_DIRECT) + { + /* If the attached device is an expander */ + if ( (DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_FANOUT_EXPANDER_DEVICE) + || (DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_EDGE_EXPANDER_DEVICE) ) + + { + DM_DBG1(("dmDownStreamDiscoverExpanderPhy: **** Topology Error direct routing can't connect to expander!!!\n")); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier = oneExpander->discoveringPhyId; + DM_DBG1(("dmDownStreamDiscoverExpanderPhy: sasAddressHi 0x%08x sasAddressLo 0x%08x phyid 0x%x\n", + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi, + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo, + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier)); + + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + return; + } + } + + /* If the expander's attached device is not myself */ + if ( (attachedSasHi != onePortContext->sasLocalAddressHi) + || (attachedSasLo != onePortContext->sasLocalAddressLo) ) + { + /* Find the attached device from discovered list */ + AttachedDevice = dmPortSASDeviceFind(dmRoot, onePortContext, attachedSasLo, attachedSasHi, oneDeviceData); + /* If the device has not been discovered before */ + if ( AttachedDevice == agNULL) //11 + { + /* If the phy has subtractive routing attribute */ + if ( DISCRSP_GET_ROUTINGATTRIB(pDiscoverResp) == SAS_ROUTING_SUBTRACTIVE && + (DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_EDGE_EXPANDER_DEVICE || + DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_FANOUT_EXPANDER_DEVICE) + ) + { + /* TODO: discovery error, callback */ + DM_DBG1(("dmDownStreamDiscoverExpanderPhy: Deferred!!! **** Topology Error subtractive routing error - inconsistent SAS address!!!\n")); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier = oneExpander->discoveringPhyId; + DM_DBG1(("dmDownStreamDiscoverExpanderPhy: sasAddressHi 0x%08x sasAddressLo 0x%08x phyid 0x%x\n", + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi, + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo, + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier)); + + onePortContext->discovery.DeferredError = agTRUE; + } + else /* 11 */ + { + /* Add the device */ + /* read minimum rate from the configuration + onePortContext->LinkRate is SPC's local link rate + */ + connectionRate = MIN(onePortContext->LinkRate, DISCRSP_GET_LINKRATE(pDiscoverResp)); + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: link rate 0x%x\n", DEVINFO_GET_LINKRATE(&oneDeviceData->agDeviceInfo))); + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: negotiatedPhyLinkRate 0x%x\n", DISCRSP_GET_LINKRATE(pDiscoverResp))); + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: connectionRate 0x%x\n", connectionRate)); + if (DISCRSP_IS_STP_TARGET(pDiscoverResp) || DISCRSP_IS_SATA_DEVICE(pDiscoverResp)) + { + if (onePortContext->discovery.type == DM_DISCOVERY_OPTION_FULL_START) + { + AttachedDevice = dmPortSASDeviceAdd( + dmRoot, + onePortContext, + sasIdentify, + agFALSE, + connectionRate, + dmAllShared->itNexusTimeout, + 0, + STP_DEVICE_TYPE, + oneDeviceData, + oneExpander, + pDiscoverResp->phyIdentifier + ); + } + else + { + /* incremental discovery */ + AttachedDevice = dmFindRegNValid( + dmRoot, + onePortContext, + &dmSASSubID + ); + /* not registered and not valid; add this*/ + if (AttachedDevice == agNULL) + { + AttachedDevice = dmPortSASDeviceAdd( + dmRoot, + onePortContext, + sasIdentify, + agFALSE, + connectionRate, + dmAllShared->itNexusTimeout, + 0, + STP_DEVICE_TYPE, + oneDeviceData, + oneExpander, + pDiscoverResp->phyIdentifier + ); + } + } + } /* DISCRSP_IS_STP_TARGET(pDiscoverResp) || DISCRSP_IS_SATA_DEVICE(pDiscoverResp) */ + else /* 22 */ + { + if (onePortContext->discovery.type == DM_DISCOVERY_OPTION_FULL_START) + { + AttachedDevice = dmPortSASDeviceAdd( + dmRoot, + onePortContext, + sasIdentify, + agFALSE, + connectionRate, + dmAllShared->itNexusTimeout, + 0, + SAS_DEVICE_TYPE, + oneDeviceData, + oneExpander, + pDiscoverResp->phyIdentifier + ); + } + else + { + /* incremental discovery */ + AttachedDevice = dmFindRegNValid( + dmRoot, + onePortContext, + &dmSASSubID + ); + /* not registered and not valid; add this*/ + if (AttachedDevice == agNULL) + { + AttachedDevice = dmPortSASDeviceAdd( + dmRoot, + onePortContext, + sasIdentify, + agFALSE, + connectionRate, + dmAllShared->itNexusTimeout, + 0, + SAS_DEVICE_TYPE, + oneDeviceData, + oneExpander, + pDiscoverResp->phyIdentifier + ); + } + } + } /* else 22 */ + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: newDevice pDevice=%p\n", AttachedDevice)); + /* If the device is added successfully */ + if ( AttachedDevice != agNULL) + { + if ( SA_IDFRM_IS_SSP_TARGET(&sasIdentify) + || SA_IDFRM_IS_SMP_TARGET(&sasIdentify) + || SA_IDFRM_IS_SSP_INITIATOR(&sasIdentify) + || SA_IDFRM_IS_SMP_INITIATOR(&sasIdentify) ) + { + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: Report a new SAS device !!\n")); + + } + else + { + if ( SA_IDFRM_IS_STP_TARGET(&sasIdentify) || + SA_IDFRM_IS_SATA_DEVICE(&sasIdentify) ) + { + + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: Found an STP or SATA device.\n")); + } + else + { + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: Found Other type of device.\n")); + } + } + + /* LP2006-05-26 added upstream device to the newly found device */ + AttachedDevice->dmExpander = oneExpander; + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: AttachedDevice %p did %d\n", AttachedDevice, AttachedDevice->id)); + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: Attached oneExpander %p did %d\n", AttachedDevice->dmExpander, AttachedDevice->dmExpander->id)); + + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: oneDeviceData %p did %d\n", oneDeviceData, oneDeviceData->id)); + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: oneExpander %p did %d\n", oneDeviceData->dmExpander, oneDeviceData->dmExpander->id)); + + /* If the phy has table routing attribute */ + if ( DISCRSP_GET_ROUTINGATTRIB(pDiscoverResp) == SAS_ROUTING_TABLE) + { + /* If the attached device is a fan out expander */ + if ( DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_FANOUT_EXPANDER_DEVICE) + { + /* TODO: discovery error, callback */ + DM_DBG1(("dmDownStreamDiscoverExpanderPhy: **** Topology Error two table routing phys are connected!!!\n")); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier = oneExpander->discoveringPhyId; + DM_DBG1(("dmDownStreamDiscoverExpanderPhy: sasAddressHi 0x%08x sasAddressLo 0x%08x phyid 0x%x\n", + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi, + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo, + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier)); + /* discovery done */ + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + else if ( DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_EDGE_EXPANDER_DEVICE) + { + /* Allocate an expander data structure */ + AttachedExpander = dmDiscoveringExpanderAlloc(dmRoot, onePortContext, AttachedDevice); + + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: Found a EDGE exp device.%p\n", AttachedExpander)); + /* If allocate successfully */ + if ( AttachedExpander != agNULL) + { + /* set up downstream information on configurable expander */ + dmExpanderDownStreamPhyAdd(dmRoot, oneExpander, (bit8) oneExpander->discoveringPhyId); + /* Setup upstream information */ + dmExpanderUpStreamPhyAdd(dmRoot, AttachedExpander, (bit8) oneExpander->discoveringPhyId); + AttachedExpander->hasUpStreamDevice = agTRUE; + AttachedExpander->upStreamSASAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + AttachedExpander->upStreamSASAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + AttachedExpander->dmUpStreamExpander = oneExpander; + /* (2.3.2.2.2.2.2.2.2) Add the pAttachedExpander to discovering list */ + dmDiscoveringExpanderAdd(dmRoot, onePortContext, AttachedExpander); + } + /* If failed to allocate */ + else + { + DM_DBG1(("dmDownStreamDiscoverExpanderPhy: Failed to allocate expander data structure!!!\n")); + /* discovery done */ + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + } + } /* DISCRSP_GET_ROUTINGATTRIB(pDiscoverResp) == SAS_ROUTING_TABLE */ + /* If status is still DISCOVERY_DOWN_STREAM */ + if ( onePortContext->discovery.status == DISCOVERY_DOWN_STREAM) + { + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: 1st before\n")); + dmDumpAllUpExp(dmRoot, onePortContext, oneExpander); + UpStreamExpander = oneExpander->dmUpStreamExpander; + ConfigurableExpander = dmFindConfigurableExp(dmRoot, onePortContext, oneExpander); + configSASAddressHi = DEVINFO_GET_SAS_ADDRESSHI(&AttachedDevice->agDeviceInfo); + configSASAddressLo = DEVINFO_GET_SAS_ADDRESSLO(&AttachedDevice->agDeviceInfo); + if (ConfigurableExpander) + { + if ( (ConfigurableExpander->dmDevice->SASAddressID.sasAddressHi + == DEVINFO_GET_SAS_ADDRESSHI(&AttachedDevice->agDeviceInfo)) && + (ConfigurableExpander->dmDevice->SASAddressID.sasAddressLo + == DEVINFO_GET_SAS_ADDRESSLO(&AttachedDevice->agDeviceInfo)) + ) + { /* directly attached between oneExpander and ConfigurableExpander */ + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: 1st before loc 1\n")); + configSASAddressHi = oneExpander->dmDevice->SASAddressID.sasAddressHi; + configSASAddressLo = oneExpander->dmDevice->SASAddressID.sasAddressLo; + } + else + { + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: 1st before loc 2\n")); + configSASAddressHi = DEVINFO_GET_SAS_ADDRESSHI(&AttachedDevice->agDeviceInfo); + configSASAddressLo = DEVINFO_GET_SAS_ADDRESSLO(&AttachedDevice->agDeviceInfo); + } + } /* if !ConfigurableExpander */ + + dupConfigSASAddr = dmDuplicateConfigSASAddr(dmRoot, + ConfigurableExpander, + configSASAddressHi, + configSASAddressLo + ); + + if ( ConfigurableExpander && dupConfigSASAddr == agFALSE) + { + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: 1st q123\n")); + UpStreamExpander->dmCurrentDownStreamExpander = oneExpander; + ConfigurableExpander->currentDownStreamPhyIndex = + dmFindCurrentDownStreamPhyIndex(dmRoot, ConfigurableExpander); + ConfigurableExpander->dmReturnginExpander = oneExpander; + dmRoutingEntryAdd(dmRoot, + ConfigurableExpander, + ConfigurableExpander->downStreamPhys[ConfigurableExpander->currentDownStreamPhyIndex], + configSASAddressHi, + configSASAddressLo + ); + } + } /* onePortContext->discovery.status == DISCOVERY_DOWN_STREAM */ + } /* AttachedDevice != agNULL */ + /* If fail to add the device */ + else + { + DM_DBG1(("dmDownStreamDiscoverExpanderPhy: Failed to add a device!!!\n")); + /* discovery done */ + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + } /* else 11 */ + } /* AttachedDevice == agNULL */ + /* If the device has been discovered before */ + else /* haha discovered before 33 */ + { + /* If the phy has subtractive routing attribute */ + if ( DISCRSP_GET_ROUTINGATTRIB(pDiscoverResp) == SAS_ROUTING_SUBTRACTIVE) + { + /* If the expander doesn't have up stream device */ + if ( oneExpander->hasUpStreamDevice == agFALSE) + { + /* TODO: discovery error, callback */ + DM_DBG1(("dmDownStreamDiscoverExpanderPhy: **** Topology Error loop, or end device connects to two expanders!!!\n")); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier = oneExpander->discoveringPhyId; + DM_DBG1(("dmDownStreamDiscoverExpanderPhy: sasAddressHi 0x%08x sasAddressLo 0x%08x phyid 0x%x\n", + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi, + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo, + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier)); + /* discovery done */ + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + /* If the expander has up stream device */ + else /* 44 */ + { + /* If sas address doesn't match */ + if ( (oneExpander->upStreamSASAddressHi != attachedSasHi) + || (oneExpander->upStreamSASAddressLo != attachedSasLo) ) + { + /* TODO: discovery error, callback */ + DM_DBG1(("dmDownStreamDiscoverExpanderPhy: **** Topology Error two subtractive phys!!!\n")); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier = oneExpander->discoveringPhyId; + DM_DBG1(("dmDownStreamDiscoverExpanderPhy: sasAddressHi 0x%08x sasAddressLo 0x%08x phyid 0x%x\n", + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi, + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo, + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier)); + /* discovery done */ + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + } /* else 44 */ + } /* DISCRSP_GET_ROUTINGATTRIB(pDiscoverResp) == SAS_ROUTING_SUBTRACTIVE */ + /* If the phy has table routing attribute */ + else if ( DISCRSP_GET_ROUTINGATTRIB(pDiscoverResp) == SAS_ROUTING_TABLE) + { + /* If the attached device is a fan out expander */ + if ( DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_FANOUT_EXPANDER_DEVICE) + { + /* (2.3.3.2.1.1) TODO: discovery error, callback */ + DM_DBG1(("dmDownStreamDiscoverExpanderPhy: **** Topology Error fan out expander to routing table phy!!!\n")); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier = oneExpander->discoveringPhyId; + DM_DBG1(("dmDownStreamDiscoverExpanderPhy: sasAddressHi 0x%08x sasAddressLo 0x%08x phyid 0x%x\n", + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi, + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo, + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier)); + /* discovery done */ + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + /* If the attached device is an edge expander */ + else if ( DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_EDGE_EXPANDER_DEVICE) + { + /* Setup up stream inform */ + AttachedExpander = AttachedDevice->dmExpander; + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: Found edge expander=%p\n", AttachedExpander)); + /* If the attached expander has up stream device */ + if ( AttachedExpander->hasUpStreamDevice == agTRUE) + { + /* compare the sas address */ + if ( (AttachedExpander->upStreamSASAddressHi + != DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo)) + || (AttachedExpander->upStreamSASAddressLo + != DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo))) + { + /* TODO: discovery error, callback */ + SAS2SAS11Check = dmSAS2SAS11ErrorCheck(dmRoot, onePortContext, AttachedExpander, oneExpander, oneExpander); + if (SAS2SAS11Check == agTRUE) + { + DM_DBG1(("dmDownStreamDiscoverExpanderPhy: **** Topology Error SAS2 and SAS1.1!!!\n")); + } + else + { + DM_DBG1(("dmDownStreamDiscoverExpanderPhy: **** Topology Error two table routing phys connected (1)!!!\n")); + } + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier = oneExpander->discoveringPhyId; + DM_DBG1(("dmDownStreamDiscoverExpanderPhy: sasAddressHi 0x%08x sasAddressLo 0x%08x phyid 0x%x\n", + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi, + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo, + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier)); + /* discovery done */ + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + else + { + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: Add edge expander=%p\n", AttachedExpander)); + /* set up downstream information on configurable expander */ + + dmExpanderDownStreamPhyAdd(dmRoot, oneExpander, (bit8) oneExpander->discoveringPhyId); + /* haha */ + dmExpanderUpStreamPhyAdd(dmRoot, AttachedExpander, (bit8) oneExpander->discoveringPhyId); + /* Add the pAttachedExpander to discovering list */ + dmDiscoveringExpanderAdd(dmRoot, onePortContext, AttachedExpander); + } + } /* AttachedExpander->hasUpStreamDevice == agTRUE */ + /* If the attached expander doesn't have up stream device */ + else + { + /* TODO: discovery error, callback */ + DM_DBG1(("dmDownStreamDiscoverExpanderPhy: **** Topology Error two table routing phys connected (2)!!!\n")); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier = oneExpander->discoveringPhyId; + DM_DBG1(("dmDownStreamDiscoverExpanderPhy: sasAddressHi 0x%08x sasAddressLo 0x%08x phyid 0x%x\n", + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi, + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo, + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier)); + /* discovery done */ + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + } /* DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_EDGE_EXPANDER_DEVICE */ + } /* DISCRSP_GET_ROUTINGATTRIB(pDiscoverResp) == SAS_ROUTING_TABLE */ + /* do this regradless of sub or table */ + /* If status is still DISCOVERY_DOWN_STREAM */ + if ( onePortContext->discovery.status == DISCOVERY_DOWN_STREAM) + { + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: 2nd before\n")); + dmDumpAllUpExp(dmRoot, onePortContext, oneExpander); + + UpStreamExpander = oneExpander->dmUpStreamExpander; + ConfigurableExpander = dmFindConfigurableExp(dmRoot, onePortContext, oneExpander); + configSASAddressHi = DEVINFO_GET_SAS_ADDRESSHI(&AttachedDevice->agDeviceInfo); + configSASAddressLo = DEVINFO_GET_SAS_ADDRESSLO(&AttachedDevice->agDeviceInfo); + if (ConfigurableExpander) + { + if ( (ConfigurableExpander->dmDevice->SASAddressID.sasAddressHi + == DEVINFO_GET_SAS_ADDRESSHI(&AttachedDevice->agDeviceInfo)) && + (ConfigurableExpander->dmDevice->SASAddressID.sasAddressLo + == DEVINFO_GET_SAS_ADDRESSLO(&AttachedDevice->agDeviceInfo)) + ) + { /* directly attached between oneExpander and ConfigurableExpander */ + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: 2nd before loc 1\n")); + configSASAddressHi = oneExpander->dmDevice->SASAddressID.sasAddressHi; + configSASAddressLo = oneExpander->dmDevice->SASAddressID.sasAddressLo; + } + else + { + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: 2nd before loc 2\n")); + configSASAddressHi = DEVINFO_GET_SAS_ADDRESSHI(&AttachedDevice->agDeviceInfo); + configSASAddressLo = DEVINFO_GET_SAS_ADDRESSLO(&AttachedDevice->agDeviceInfo); + } + } /* if !ConfigurableExpander */ + dupConfigSASAddr = dmDuplicateConfigSASAddr(dmRoot, + ConfigurableExpander, + configSASAddressHi, + configSASAddressLo + ); + if ( ConfigurableExpander && dupConfigSASAddr == agFALSE) + { + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: 2nd q123 \n")); + UpStreamExpander->dmCurrentDownStreamExpander = oneExpander; + ConfigurableExpander->currentDownStreamPhyIndex = + dmFindCurrentDownStreamPhyIndex(dmRoot, ConfigurableExpander); + ConfigurableExpander->dmReturnginExpander = oneExpander; + dmRoutingEntryAdd(dmRoot, + ConfigurableExpander, + ConfigurableExpander->downStreamPhys[ConfigurableExpander->currentDownStreamPhyIndex], + configSASAddressHi, + configSASAddressLo + ); + } + } /* onePortContext->discovery.status == DISCOVERY_DOWN_STREAM */ + /* incremental discovery */ + if (onePortContext->discovery.type == DM_DISCOVERY_OPTION_INCREMENTAL_START) + { + connectionRate = MIN(onePortContext->LinkRate, DISCRSP_GET_LINKRATE(pDiscoverResp)); + + if (DISCRSP_IS_STP_TARGET(pDiscoverResp) || DISCRSP_IS_SATA_DEVICE(pDiscoverResp)) + { + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: incremental SATA_STP\n")); + + dmPortSASDeviceAdd( + dmRoot, + onePortContext, + sasIdentify, + agFALSE, + connectionRate, + dmAllShared->itNexusTimeout, + 0, + STP_DEVICE_TYPE, + oneDeviceData, + oneExpander, + pDiscoverResp->phyIdentifier + ); + } + else + { + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: incremental SAS\n")); + + + dmPortSASDeviceAdd( + dmRoot, + onePortContext, + sasIdentify, + agFALSE, + connectionRate, + dmAllShared->itNexusTimeout, + 0, + SAS_DEVICE_TYPE, + oneDeviceData, + oneExpander, + pDiscoverResp->phyIdentifier + ); + + } + } /* onePortContext->discovery.type == DM_DISCOVERY_OPTION_INCREMENTAL_START */ + } /* else 33 */ + } /* (attachedSasLo != onePortContext->sasLocalAddressLo) */ + + else /* else 44 */ + { + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: Found Self\n")); + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: 3rd before\n")); + dmDumpAllUpExp(dmRoot, onePortContext, oneExpander); + + UpStreamExpander = oneExpander->dmUpStreamExpander; + ConfigurableExpander = dmFindConfigurableExp(dmRoot, onePortContext, oneExpander); + dupConfigSASAddr = dmDuplicateConfigSASAddr(dmRoot, + ConfigurableExpander, + onePortContext->sasLocalAddressHi, + onePortContext->sasLocalAddressLo + ); + + if ( ConfigurableExpander && dupConfigSASAddr == agFALSE) + { + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: 3rd q123 Setup routing table\n")); + UpStreamExpander->dmCurrentDownStreamExpander = oneExpander; + ConfigurableExpander->currentDownStreamPhyIndex = + dmFindCurrentDownStreamPhyIndex(dmRoot, ConfigurableExpander); + ConfigurableExpander->dmReturnginExpander = oneExpander; + dmRoutingEntryAdd(dmRoot, + ConfigurableExpander, + ConfigurableExpander->downStreamPhys[ConfigurableExpander->currentDownStreamPhyIndex], + onePortContext->sasLocalAddressHi, + onePortContext->sasLocalAddressLo + ); + } + } /* else 44 */ + } /* DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) != SAS_NO_DEVICE */ + /* If no device is attached */ + else + { + + DM_DBG2(("!!!!!!!!!!!!!!!!!!!!! SPIN SATA !!!!!!!!!!!!!!!!!!!!!!!!!!!\n")); + negotiatedPhyLinkRate = DISCRSP_GET_LINKRATE(pDiscoverResp); // added by thenil + + if (negotiatedPhyLinkRate == 0x03) + { + + DM_DBG1(("dmDownStreamDiscover2ExpanderPhy: SPIN SATA sent reset\n")); + dmPhyControlSend(dmRoot, + oneDeviceData, + SMP_PHY_CONTROL_HARD_RESET, + pDiscoverResp->phyIdentifier + ); + } + + /* do nothing */ + } + + + /* Increment the discovering phy id */ + oneExpander->discoveringPhyId ++; + + /* If the discovery status is DISCOVERY_DOWN_STREAM */ + if ( onePortContext->discovery.status == DISCOVERY_DOWN_STREAM ) + { + /* If not the last phy */ + if ( oneExpander->discoveringPhyId < oneDeviceData->numOfPhys ) + { + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: More Phys to discover\n")); + /* continue discovery for the next phy */ + dmDiscoverSend(dmRoot, oneDeviceData); + } + /* If the last phy */ + else + { + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: No More Phys\n")); + + /* for MCN */ + dmUpdateAllAdjacent(dmRoot, onePortContext, oneDeviceData); + /* remove the expander from the discovering list */ + dmDiscoveringExpanderRemove(dmRoot, onePortContext, oneExpander); + /* continue downstream discovering */ + dmDownStreamDiscovering(dmRoot, onePortContext, oneDeviceData); + } + } + else + { + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: onePortContext->discovery.status not in DISCOVERY_DOWN_STREAM; status %d\n", onePortContext->discovery.status)); + } + DM_DBG3(("dmDownStreamDiscoverExpanderPhy: end return phyID#%d\n", oneExpander->discoveringPhyId - 1)); + + return; +} + + +/* works at SAS2 expander (called in dmDownStreamDiscover2ExpanderPhy()) + if currentExpander is SAS2, called in dmDownStreamDiscover2ExpanderPhy() + if currentExpander is SAS1.1, called in dmDownStreamDiscoverExpanderPhy() +*/ +osGLOBAL bit32 +dmSAS2SAS11ErrorCheck( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmExpander_t *topExpander, + dmExpander_t *bottomExpander, + dmExpander_t *currentExpander + ) +{ + bit32 result = agFALSE, i = 0; + bit8 downStreamPhyID, upStreamPhyID; + + DM_DBG2(("dmSAS2SAS11ErrorCheck: start\n")); + + if (topExpander == agNULL) + { + DM_DBG2(("dmSAS2SAS11ErrorCheck: topExpander is NULL\n")); + return result; + } + if (bottomExpander == agNULL) + { + DM_DBG2(("dmSAS2SAS11ErrorCheck: bottomExpander is NULL\n")); + return result; + } + + if (currentExpander == agNULL) + { + DM_DBG2(("dmSAS2SAS11ErrorCheck: currentExpander is NULL\n")); + return result; + } + + DM_DBG2(("dmSAS2SAS11ErrorCheck: topExpander addrHi 0x%08x addrLo 0x%08x\n", + topExpander->dmDevice->SASAddressID.sasAddressHi, topExpander->dmDevice->SASAddressID.sasAddressLo)); + DM_DBG2(("dmSAS2SAS11ErrorCheck: bottomExpander addrHi 0x%08x addrLo 0x%08x\n", + bottomExpander->dmDevice->SASAddressID.sasAddressHi, bottomExpander->dmDevice->SASAddressID.sasAddressLo)); + DM_DBG2(("dmSAS2SAS11ErrorCheck: currentExpander addrHi 0x%08x addrLo 0x%08x\n", + currentExpander->dmDevice->SASAddressID.sasAddressHi, currentExpander->dmDevice->SASAddressID.sasAddressLo)); + + for (i=0;idownStreamPhys[i]; + upStreamPhyID = bottomExpander->upStreamPhys[i]; + if (currentExpander->SAS2 == 1) + { + if ( downStreamPhyID == upStreamPhyID && + topExpander->routingAttribute[downStreamPhyID] == SAS_ROUTING_TABLE && + bottomExpander->routingAttribute[i] == SAS_ROUTING_SUBTRACTIVE && + topExpander->SAS2 == 0 && + bottomExpander->SAS2 == 1 + ) + { + result = agTRUE; + break; + } + } + else if (currentExpander->SAS2 == 0) + { + if ( downStreamPhyID == upStreamPhyID && + topExpander->routingAttribute[downStreamPhyID] == SAS_ROUTING_SUBTRACTIVE && + bottomExpander->routingAttribute[i] == SAS_ROUTING_TABLE && + topExpander->SAS2 == 1 && + bottomExpander->SAS2 == 0 + ) + { + result = agTRUE; + break; + } + } + } + return result; +} + +osGLOBAL void +dmDownStreamDiscover2ExpanderPhy( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmExpander_t *oneExpander, + smpRespDiscover2_t *pDiscoverResp + ) +{ + dmDeviceData_t *oneDeviceData; + dmExpander_t *UpStreamExpander; + dmDeviceData_t *AttachedDevice = agNULL; + dmExpander_t *AttachedExpander; + agsaSASIdentify_t sasIdentify; + bit8 connectionRate; + bit32 attachedSasHi, attachedSasLo; + dmSASSubID_t dmSASSubID; + dmExpander_t *ConfigurableExpander = agNULL; + bit32 dupConfigSASAddr = agFALSE; + bit32 configSASAddressHi; + bit32 configSASAddressLo; + bit32 SAS2SAS11Check = agFALSE; + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + + + DM_DBG2(("dmDownStreamDiscover2ExpanderPhy: start\n")); + DM_DBG2(("dmDownStreamDiscover2ExpanderPhy: exp addrHi 0x%08x\n", oneExpander->dmDevice->SASAddressID.sasAddressHi)); + DM_DBG2(("dmDownStreamDiscover2ExpanderPhy: exp addrLo 0x%08x\n", oneExpander->dmDevice->SASAddressID.sasAddressLo)); + + DM_ASSERT(dmRoot, "(dmDownStreamDiscover2ExpanderPhy) dmRoot NULL"); + DM_ASSERT(onePortContext, "(dmDownStreamDiscover2ExpanderPhy) pPort NULL"); + DM_ASSERT(oneExpander, "(dmDownStreamDiscover2ExpanderPhy) pExpander NULL"); + DM_ASSERT(pDiscoverResp, "(dmDownStreamDiscover2ExpanderPhy) pDiscoverResp NULL"); + + DM_DBG2(("dmDownStreamDiscover2ExpanderPhy: onePortContxt=%p oneExpander=%p oneDeviceData=%p\n", onePortContext, oneExpander, oneExpander->dmDevice)); + + if (dmDiscoverCheck(dmRoot, onePortContext) == agTRUE) + { + DM_DBG1(("dmDownStreamDiscover2ExpanderPhy: invalid port or aborted discovery!!!\n")); + return; + } + + if (oneExpander != oneExpander->dmDevice->dmExpander) + { + DM_DBG1(("dmDownStreamDiscover2ExpanderPhy: wrong!!!\n")); + } + + + /* (1) Find the device structure of the expander */ + oneDeviceData = oneExpander->dmDevice; + + DM_ASSERT(oneDeviceData, "(dmDownStreamDiscover2ExpanderPhy) pDevice NULL"); + + /* for debugging */ + DM_DBG2(("dmDownStreamDiscover2ExpanderPhy: Phy #%d of SAS %08x-%08x\n", + oneExpander->discoveringPhyId, + oneDeviceData->SASAddressID.sasAddressHi, + oneDeviceData->SASAddressID.sasAddressLo)); + + DM_DBG2((" Attached device: %s\n", + ( SAS2_DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == 0 ? "No Device" : + (SAS2_DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == 1 ? "End Device" : + (SAS2_DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == 2 ? "Edge Expander" : "Fanout Expander"))))); + + + /* for debugging */ + if (oneExpander->discoveringPhyId != pDiscoverResp->phyIdentifier) + { + DM_DBG1(("dmDownStreamDiscover2ExpanderPhy: !!! Incorrect SMP response !!!\n")); + DM_DBG1(("dmDownStreamDiscover2ExpanderPhy: Request PhyID #%d Response PhyID #%d\n", oneExpander->discoveringPhyId, pDiscoverResp->phyIdentifier)); + dmhexdump("NO_DEVICE", (bit8*)pDiscoverResp, sizeof(smpRespDiscover2_t)); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + return; + } + + if ( SAS2_DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) != SAS_NO_DEVICE) + { + DM_DBG2((" SAS address : %08x-%08x\n", + SAS2_DISCRSP_GET_ATTACHED_SAS_ADDRESSHI(pDiscoverResp), + SAS2_DISCRSP_GET_ATTACHED_SAS_ADDRESSLO(pDiscoverResp))); + DM_DBG2((" SSP Target : %d\n", SAS2_DISCRSP_IS_SSP_TARGET(pDiscoverResp)?1:0)); + DM_DBG2((" STP Target : %d\n", SAS2_DISCRSP_IS_STP_TARGET(pDiscoverResp)?1:0)); + DM_DBG2((" SMP Target : %d\n", SAS2_DISCRSP_IS_SMP_TARGET(pDiscoverResp)?1:0)); + DM_DBG2((" SATA DEVICE : %d\n", SAS2_DISCRSP_IS_SATA_DEVICE(pDiscoverResp)?1:0)); + DM_DBG2((" SSP Initiator : %d\n", SAS2_DISCRSP_IS_SSP_INITIATOR(pDiscoverResp)?1:0)); + DM_DBG2((" STP Initiator : %d\n", SAS2_DISCRSP_IS_STP_INITIATOR(pDiscoverResp)?1:0)); + DM_DBG2((" SMP Initiator : %d\n", SAS2_DISCRSP_IS_SMP_INITIATOR(pDiscoverResp)?1:0)); + DM_DBG2((" Phy ID : %d\n", pDiscoverResp->phyIdentifier)); + DM_DBG2((" Attached Phy ID: %d\n", pDiscoverResp->attachedPhyIdentifier)); + + } + + /* saving routing attribute for non self-configuring expanders */ + oneExpander->routingAttribute[pDiscoverResp->phyIdentifier] = SAS2_DISCRSP_GET_ROUTINGATTRIB(pDiscoverResp); + + + oneExpander->discoverSMPAllowed = agTRUE; + + /* If a device is attached */ + if ( SAS2_DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) != SAS_NO_DEVICE) + { + /* Setup sasIdentify for the attached device */ + sasIdentify.phyIdentifier = pDiscoverResp->phyIdentifier; + sasIdentify.deviceType_addressFrameType = pDiscoverResp->attachedDeviceTypeReason & 0x70; + sasIdentify.initiator_ssp_stp_smp = pDiscoverResp->attached_Ssp_Stp_Smp_Sata_Initiator; + sasIdentify.target_ssp_stp_smp = pDiscoverResp->attached_SataPS_Ssp_Stp_Smp_Sata_Target; + *(bit32*)sasIdentify.sasAddressHi = *(bit32*)pDiscoverResp->attachedSasAddressHi; + *(bit32*)sasIdentify.sasAddressLo = *(bit32*)pDiscoverResp->attachedSasAddressLo; + + /* incremental discovery */ + dmSASSubID.sasAddressHi = SA_IDFRM_GET_SAS_ADDRESSHI(&sasIdentify); + dmSASSubID.sasAddressLo = SA_IDFRM_GET_SAS_ADDRESSLO(&sasIdentify); + dmSASSubID.initiator_ssp_stp_smp = sasIdentify.initiator_ssp_stp_smp; + dmSASSubID.target_ssp_stp_smp = sasIdentify.target_ssp_stp_smp; + + attachedSasHi = SAS2_DISCRSP_GET_ATTACHED_SAS_ADDRESSHI(pDiscoverResp); + attachedSasLo = SAS2_DISCRSP_GET_ATTACHED_SAS_ADDRESSLO(pDiscoverResp); + + /* If it's a direct routing */ + if ( SAS2_DISCRSP_GET_ROUTINGATTRIB(pDiscoverResp) == SAS_ROUTING_DIRECT) + { + /* If the attached device is an expander */ + if ( (SAS2_DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_FANOUT_EXPANDER_DEVICE) + || (SAS2_DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_EDGE_EXPANDER_DEVICE) ) + + { + DM_DBG1(("dmDownStreamDiscover2ExpanderPhy: **** Topology Error direct routing can't connect to expander!!!\n")); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier = oneExpander->discoveringPhyId; + + DM_DBG1(("dmDownStreamDiscover2ExpanderPhy: sasAddressHi 0x%08x sasAddressLo 0x%08x phyid 0x%x\n", + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi, + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo, + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier)); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + + return; + } + } + + /* If the expander's attached device is not myself */ + if ( (attachedSasHi != onePortContext->sasLocalAddressHi) + || (attachedSasLo != onePortContext->sasLocalAddressLo) ) + { + /* Find the attached device from discovered list */ + AttachedDevice = dmPortSASDeviceFind(dmRoot, onePortContext, attachedSasLo, attachedSasHi, oneDeviceData); + /* If the device has not been discovered before */ + if ( AttachedDevice == agNULL) //11 + { + //qqqqqq + if (0) + { + DM_DBG1(("dmDownStreamDiscover2ExpanderPhy: **** Topology Error subtractive routing error - inconsistent SAS address!!!\n")); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier = oneExpander->discoveringPhyId; + DM_DBG1(("dmDownStreamDiscover2ExpanderPhy: sasAddressHi 0x%08x sasAddressLo 0x%08x phyid 0x%x\n", + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi, + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo, + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier)); + /* discovery done */ + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + else + { + /* Add the device */ + /* read minimum rate from the configuration + onePortContext->LinkRate is SPC's local link rate + */ + connectionRate = MIN(onePortContext->LinkRate, SAS2_DISCRSP_GET_LOGICAL_LINKRATE(pDiscoverResp)); + DM_DBG2(("dmDownStreamDiscover2ExpanderPhy: link rate 0x%x\n", DEVINFO_GET_LINKRATE(&oneDeviceData->agDeviceInfo))); + DM_DBG2(("dmDownStreamDiscover2ExpanderPhy: negotiatedPhyLinkRate 0x%x\n", SAS2_DISCRSP_GET_LINKRATE(pDiscoverResp))); + DM_DBG2(("dmDownStreamDiscover2ExpanderPhy: connectionRate 0x%x\n", connectionRate)); + + if (SAS2_DISCRSP_IS_STP_TARGET(pDiscoverResp) || SAS2_DISCRSP_IS_SATA_DEVICE(pDiscoverResp)) + { + if (onePortContext->discovery.type == DM_DISCOVERY_OPTION_FULL_START) + { + AttachedDevice = dmPortSASDeviceAdd( + dmRoot, + onePortContext, + sasIdentify, + agFALSE, + connectionRate, + dmAllShared->itNexusTimeout, + 0, + STP_DEVICE_TYPE, + oneDeviceData, + oneExpander, + pDiscoverResp->phyIdentifier + ); + } + else + { + /* incremental discovery */ + AttachedDevice = dmFindRegNValid( + dmRoot, + onePortContext, + &dmSASSubID + ); + /* not registered and not valid; add this*/ + if (AttachedDevice == agNULL) + { + AttachedDevice = dmPortSASDeviceAdd( + dmRoot, + onePortContext, + sasIdentify, + agFALSE, + connectionRate, + dmAllShared->itNexusTimeout, + 0, + STP_DEVICE_TYPE, + oneDeviceData, + oneExpander, + pDiscoverResp->phyIdentifier + ); + } + } + } + else + { + if (onePortContext->discovery.type == DM_DISCOVERY_OPTION_FULL_START) + { + AttachedDevice = dmPortSASDeviceAdd( + dmRoot, + onePortContext, + sasIdentify, + agFALSE, + connectionRate, + dmAllShared->itNexusTimeout, + 0, + SAS_DEVICE_TYPE, + oneDeviceData, + oneExpander, + pDiscoverResp->phyIdentifier + ); + } + else + { + /* incremental discovery */ + AttachedDevice = dmFindRegNValid( + dmRoot, + onePortContext, + &dmSASSubID + ); + /* not registered and not valid; add this*/ + if (AttachedDevice == agNULL) + { + AttachedDevice = dmPortSASDeviceAdd( + dmRoot, + onePortContext, + sasIdentify, + agFALSE, + connectionRate, + dmAllShared->itNexusTimeout, + 0, + SAS_DEVICE_TYPE, + oneDeviceData, + oneExpander, + pDiscoverResp->phyIdentifier + ); + } + } + } + DM_DBG2(("dmDownStreamDiscover2ExpanderPhy: newDevice pDevice=%p\n", AttachedDevice)); + /* If the device is added successfully */ + if ( AttachedDevice != agNULL) + { + if ( SA_IDFRM_IS_SSP_TARGET(&sasIdentify) + || SA_IDFRM_IS_SMP_TARGET(&sasIdentify) + || SA_IDFRM_IS_SSP_INITIATOR(&sasIdentify) + || SA_IDFRM_IS_SMP_INITIATOR(&sasIdentify) ) + { + DM_DBG2(("dmDownStreamDiscover2ExpanderPhy: Report a new SAS device !!\n")); + + } + else + { + if ( SA_IDFRM_IS_STP_TARGET(&sasIdentify) || + SA_IDFRM_IS_SATA_DEVICE(&sasIdentify) ) + { + + DM_DBG2(("dmDownStreamDiscover2ExpanderPhy: Found an STP or SATA device.\n")); + } + else + { + DM_DBG2(("dmDownStreamDiscover2ExpanderPhy: Found Other type of device.\n")); + } + } + + /* LP2006-05-26 added upstream device to the newly found device */ + AttachedDevice->dmExpander = oneExpander; + DM_DBG3(("dmDownStreamDiscover2ExpanderPhy: AttachedDevice %p did %d\n", AttachedDevice, AttachedDevice->id)); + DM_DBG3(("dmDownStreamDiscover2ExpanderPhy: Attached oneExpander %p did %d\n", AttachedDevice->dmExpander, AttachedDevice->dmExpander->id)); + + DM_DBG3(("dmDownStreamDiscover2ExpanderPhy: oneDeviceData %p did %d\n", oneDeviceData, oneDeviceData->id)); + DM_DBG3(("dmDownStreamDiscover2ExpanderPhy: oneExpander %p did %d\n", oneDeviceData->dmExpander, oneDeviceData->dmExpander->id)); + + /* If the phy has table routing attribute */ + if ( SAS2_DISCRSP_GET_ROUTINGATTRIB(pDiscoverResp) == SAS_ROUTING_TABLE) + { + /* If the attached device is a fan out expander */ + if ( SAS2_DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_FANOUT_EXPANDER_DEVICE) + { + /* TODO: discovery error, callback */ + DM_DBG1(("dmDownStreamDiscover2ExpanderPhy: **** Topology Error two table routing phys are connected!!!\n")); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier = oneExpander->discoveringPhyId; + DM_DBG1(("dmDownStreamDiscover2ExpanderPhy: sasAddressHi 0x%08x sasAddressLo 0x%08x phyid 0x%x\n", + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi, + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo, + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier)); + /* discovery done */ + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + else if ( SAS2_DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_EDGE_EXPANDER_DEVICE) + { + /* Allocate an expander data structure */ + AttachedExpander = dmDiscoveringExpanderAlloc(dmRoot, onePortContext, AttachedDevice); + + DM_DBG2(("dmDownStreamDiscover2ExpanderPhy: Found a EDGE exp device.%p\n", AttachedExpander)); + /* If allocate successfully */ + if ( AttachedExpander != agNULL) + { + /* set up downstream information on configurable expander */ + + dmExpanderDownStreamPhyAdd(dmRoot, oneExpander, (bit8) oneExpander->discoveringPhyId); + + /* Setup upstream information */ + dmExpanderUpStreamPhyAdd(dmRoot, AttachedExpander, (bit8) oneExpander->discoveringPhyId); +//qqqqq + AttachedExpander->hasUpStreamDevice = agTRUE; + AttachedExpander->upStreamSASAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + AttachedExpander->upStreamSASAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + AttachedExpander->dmUpStreamExpander = oneExpander; + /* (2.3.2.2.2.2.2.2.2) Add the pAttachedExpander to discovering list */ + dmDiscoveringExpanderAdd(dmRoot, onePortContext, AttachedExpander); + } + /* If failed to allocate */ + else + { + DM_DBG1(("dmDownStreamDiscover2ExpanderPhy, Failed to allocate expander data structure!!!\n")); + /* discovery done */ + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + } + } + //qqqqq + else if ( SAS2_DISCRSP_GET_ROUTINGATTRIB(pDiscoverResp) == SAS_ROUTING_SUBTRACTIVE && + (SAS2_DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_FANOUT_EXPANDER_DEVICE || + SAS2_DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_EDGE_EXPANDER_DEVICE) + ) + { + /* Allocate an expander data structure */ + AttachedExpander = dmDiscoveringExpanderAlloc(dmRoot, onePortContext, AttachedDevice); + + DM_DBG2(("dmDownStreamDiscover2ExpanderPhy: Found a EDGE/FANOUT exp device.%p\n", AttachedExpander)); + /* If allocate successfully */ + if ( AttachedExpander != agNULL) + { + /* set up downstream information on configurable expander */ + dmExpanderDownStreamPhyAdd(dmRoot, oneExpander, (bit8) oneExpander->discoveringPhyId); + + /* Setup upstream information */ + dmExpanderUpStreamPhyAdd(dmRoot, AttachedExpander, (bit8) oneExpander->discoveringPhyId); + AttachedExpander->hasUpStreamDevice = agTRUE; + AttachedExpander->upStreamSASAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + AttachedExpander->upStreamSASAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + AttachedExpander->dmUpStreamExpander = oneExpander; + /* (2.3.2.2.2.2.2.2.2) Add the pAttachedExpander to discovering list */ + dmDiscoveringExpanderAdd(dmRoot, onePortContext, AttachedExpander); + } + /* If failed to allocate */ + else + { + DM_DBG1(("dmDownStreamDiscover2ExpanderPhy, Failed to allocate expander data structure (2)!!!\n")); + /* discovery done */ + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + + + } + /* If status is still DISCOVERY_DOWN_STREAM */ + if ( onePortContext->discovery.status == DISCOVERY_DOWN_STREAM && + onePortContext->discovery.ConfiguresOthers == agFALSE) + { + DM_DBG2(("dmDownStreamDiscover2ExpanderPhy: 1st before\n")); + dmDumpAllUpExp(dmRoot, onePortContext, oneExpander); + UpStreamExpander = oneExpander->dmUpStreamExpander; + ConfigurableExpander = dmFindConfigurableExp(dmRoot, onePortContext, oneExpander); + configSASAddressHi = DEVINFO_GET_SAS_ADDRESSHI(&AttachedDevice->agDeviceInfo); + configSASAddressLo = DEVINFO_GET_SAS_ADDRESSLO(&AttachedDevice->agDeviceInfo); + if (ConfigurableExpander) + { + if ( (ConfigurableExpander->dmDevice->SASAddressID.sasAddressHi + == DEVINFO_GET_SAS_ADDRESSHI(&AttachedDevice->agDeviceInfo)) && + (ConfigurableExpander->dmDevice->SASAddressID.sasAddressLo + == DEVINFO_GET_SAS_ADDRESSLO(&AttachedDevice->agDeviceInfo)) + ) + { /* directly attached between oneExpander and ConfigurableExpander */ + DM_DBG2(("dmDownStreamDiscover2ExpanderPhy: 1st before loc 1\n")); + configSASAddressHi = oneExpander->dmDevice->SASAddressID.sasAddressHi; + configSASAddressLo = oneExpander->dmDevice->SASAddressID.sasAddressLo; + } + else + { + DM_DBG2(("dmDownStreamDiscover2ExpanderPhy: 1st before loc 2\n")); + configSASAddressHi = DEVINFO_GET_SAS_ADDRESSHI(&AttachedDevice->agDeviceInfo); + configSASAddressLo = DEVINFO_GET_SAS_ADDRESSLO(&AttachedDevice->agDeviceInfo); + } + } /* if !ConfigurableExpander */ + dupConfigSASAddr = dmDuplicateConfigSASAddr(dmRoot, + ConfigurableExpander, + configSASAddressHi, + configSASAddressLo + ); + + + if ( ConfigurableExpander && dupConfigSASAddr == agFALSE) + { + DM_DBG2(("dmDownStreamDiscover2ExpanderPhy: 1st q123\n")); + UpStreamExpander->dmCurrentDownStreamExpander = oneExpander; + ConfigurableExpander->currentDownStreamPhyIndex = + dmFindCurrentDownStreamPhyIndex(dmRoot, ConfigurableExpander); + ConfigurableExpander->dmReturnginExpander = oneExpander; + dmRoutingEntryAdd(dmRoot, + ConfigurableExpander, + ConfigurableExpander->downStreamPhys[ConfigurableExpander->currentDownStreamPhyIndex], + configSASAddressHi, + configSASAddressLo + ); + } + } + } + /* If fail to add the device */ + else + { + DM_DBG1(("dmDownStreamDiscover2ExpanderPhy, Failed to add a device!!!\n")); + /* discovery done */ + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + } + } + /* If the device has been discovered before */ + else /* discovered before */ + { + /* If the phy has subtractive routing attribute */ + if ( SAS2_DISCRSP_GET_ROUTINGATTRIB(pDiscoverResp) == SAS_ROUTING_SUBTRACTIVE) + { + /* If the expander doesn't have up stream device */ + if ( oneExpander->hasUpStreamDevice == agFALSE) + { + /* TODO: discovery error, callback */ + DM_DBG1(("dmDownStreamDiscover2ExpanderPhy: **** Topology Error loop, or end device connects to two expanders!!!\n")); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier = oneExpander->discoveringPhyId; + DM_DBG1(("dmDownStreamDiscover2ExpanderPhy: sasAddressHi 0x%08x sasAddressLo 0x%08x phyid 0x%x\n", + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi, + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo, + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier)); + /* discovery done */ + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + /* If the expander has up stream device */ + else + { + +//qqqqq + /* If sas address doesn't match */ + if ( (oneExpander->upStreamSASAddressHi != attachedSasHi) + || (oneExpander->upStreamSASAddressLo != attachedSasLo) ) + { + /* TODO: discovery error, callback */ + DM_DBG1(("dmDownStreamDiscover2ExpanderPhy: **** two subtractive phys!!! Allowed in SAS2!!!\n")); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier = oneExpander->discoveringPhyId; + onePortContext->discovery.DeferredError = agTRUE; + + } + } + } + /* If the phy has table routing attribute */ + else if ( SAS2_DISCRSP_GET_ROUTINGATTRIB(pDiscoverResp) == SAS_ROUTING_TABLE) + { + /* If the attached device is a fan out expander */ + if ( SAS2_DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_FANOUT_EXPANDER_DEVICE) + { + /* (2.3.3.2.1.1) TODO: discovery error, callback */ + DM_DBG1(("dmDownStreamDiscover2ExpanderPhy: **** Topology Error fan out expander to routing table phy!!!\n")); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier = oneExpander->discoveringPhyId; + DM_DBG1(("dmDownStreamDiscover2ExpanderPhy: sasAddressHi 0x%08x sasAddressLo 0x%08x phyid 0x%x\n", + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi, + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo, + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier)); + /* discovery done */ + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + /* If the attached device is an edge expander */ + else if ( SAS2_DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_EDGE_EXPANDER_DEVICE) + { + /* Setup up stream inform */ + AttachedExpander = AttachedDevice->dmExpander; + DM_DBG2(("dmDownStreamDiscover2ExpanderPhy: Found edge expander=%p\n", AttachedExpander)); + //hhhhhh + /* If the attached expander has up stream device */ + if ( AttachedExpander->hasUpStreamDevice == agTRUE) + { + /* compare the sas address */ + if ( (AttachedExpander->upStreamSASAddressHi + != DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo)) + || (AttachedExpander->upStreamSASAddressLo + != DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo))) + { + if (AttachedExpander->TTTSupported && oneExpander->TTTSupported) + { + /* + needs further error checking + UpstreamExpanderOfAttachedExpander = AttachedExpander->UpStreamExpander + for (i=0;idownStreamPhys[i] != 0 && + } + */ + SAS2SAS11Check = dmSAS2SAS11ErrorCheck(dmRoot, onePortContext, AttachedExpander->dmUpStreamExpander, AttachedExpander, oneExpander); + if (SAS2SAS11Check == agTRUE) + { + + DM_DBG1(("dmDownStreamDiscover2ExpanderPhy: **** Topology Error SAS2 and SAS1.1!!!\n")); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier = oneExpander->discoveringPhyId; + DM_DBG1(("dmDownStreamDiscover2ExpanderPhy: sasAddressHi 0x%08x sasAddressLo 0x%08x phyid 0x%x\n", + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi, + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo, + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier)); + /* discovery done */ + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + else + { + DM_DBG1(("dmDownStreamDiscover2ExpanderPhy: Allowed Table to Table (1)\n")); + /* move on to the next phys but should be not proceed after oneExpander */ + oneExpander->UndoDueToTTTSupported = agTRUE; + onePortContext->discovery.DeferredError = agFALSE; + } + } + else + { + /* TODO: discovery error, callback */ + DM_DBG1(("dmDownStreamDiscover2ExpanderPhy: **** Topology Error two table routing phys connected (1)!!!\n")); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier = oneExpander->discoveringPhyId; + DM_DBG1(("dmDownStreamDiscover2ExpanderPhy: sasAddressHi 0x%08x sasAddressLo 0x%08x phyid 0x%x\n", + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi, + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo, + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier)); + /* discovery done */ + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + } + else + { + DM_DBG2(("dmDownStreamDiscover2ExpanderPhy: Add edge expander=%p\n", AttachedExpander)); + /* set up downstream information on configurable expander */ + + dmExpanderDownStreamPhyAdd(dmRoot, oneExpander, (bit8) oneExpander->discoveringPhyId); + /* haha */ + dmExpanderUpStreamPhyAdd(dmRoot, AttachedExpander, (bit8) oneExpander->discoveringPhyId); + /* Add the pAttachedExpander to discovering list */ + dmDiscoveringExpanderAdd(dmRoot, onePortContext, AttachedExpander); + } + } + /* If the attached expander doesn't have up stream device */ + else + { + if (AttachedExpander->TTTSupported && oneExpander->TTTSupported) + { + DM_DBG1(("dmDownStreamDiscover2ExpanderPhy: Allowed Table to Table (2)\n")); + /* move on to the next phys but should be not proceed after oneExpander */ + oneExpander->UndoDueToTTTSupported = agTRUE; + onePortContext->discovery.DeferredError = agFALSE; + } + else + { + /* TODO: discovery error, callback */ + DM_DBG1(("dmDownStreamDiscover2ExpanderPhy: **** Topology Error two table routing phys connected (2)!!!\n")); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier = oneExpander->discoveringPhyId; + DM_DBG1(("dmDownStreamDiscover2ExpanderPhy: sasAddressHi 0x%08x sasAddressLo 0x%08x phyid 0x%x\n", + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi, + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo, + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier)); + /* discovery done */ + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + } + } + } /* for else if (SAS2_DISCRSP_GET_ROUTINGATTRIB(pDiscoverResp) == SAS_ROUTING_TABLE) */ + + /* do this regradless of sub or table */ + /* If status is still DISCOVERY_DOWN_STREAM */ + if ( onePortContext->discovery.status == DISCOVERY_DOWN_STREAM && + onePortContext->discovery.ConfiguresOthers == agFALSE) + { + DM_DBG2(("dmDownStreamDiscover2ExpanderPhy: 2nd before\n")); + dmDumpAllUpExp(dmRoot, onePortContext, oneExpander); + + UpStreamExpander = oneExpander->dmUpStreamExpander; + ConfigurableExpander = dmFindConfigurableExp(dmRoot, onePortContext, oneExpander); + configSASAddressHi = DEVINFO_GET_SAS_ADDRESSHI(&AttachedDevice->agDeviceInfo); + configSASAddressLo = DEVINFO_GET_SAS_ADDRESSLO(&AttachedDevice->agDeviceInfo); + if (ConfigurableExpander) + { + if ( (ConfigurableExpander->dmDevice->SASAddressID.sasAddressHi + == DEVINFO_GET_SAS_ADDRESSHI(&AttachedDevice->agDeviceInfo)) && + (ConfigurableExpander->dmDevice->SASAddressID.sasAddressLo + == DEVINFO_GET_SAS_ADDRESSLO(&AttachedDevice->agDeviceInfo)) + ) + { /* directly attached between oneExpander and ConfigurableExpander */ + DM_DBG2(("dmDownStreamDiscover2ExpanderPhy: 2nd before loc 1\n")); + configSASAddressHi = oneExpander->dmDevice->SASAddressID.sasAddressHi; + configSASAddressLo = oneExpander->dmDevice->SASAddressID.sasAddressLo; + } + else + { + DM_DBG2(("dmDownStreamDiscover2ExpanderPhy: 2nd before loc 2\n")); + configSASAddressHi = DEVINFO_GET_SAS_ADDRESSHI(&AttachedDevice->agDeviceInfo); + configSASAddressLo = DEVINFO_GET_SAS_ADDRESSLO(&AttachedDevice->agDeviceInfo); + } + } /* if !ConfigurableExpander */ + dupConfigSASAddr = dmDuplicateConfigSASAddr(dmRoot, + ConfigurableExpander, + configSASAddressHi, + configSASAddressLo + ); + + if ( ConfigurableExpander && dupConfigSASAddr == agFALSE) + { + DM_DBG2(("dmDownStreamDiscover2ExpanderPhy: 2nd q123 \n")); + UpStreamExpander->dmCurrentDownStreamExpander = oneExpander; + ConfigurableExpander->currentDownStreamPhyIndex = + dmFindCurrentDownStreamPhyIndex(dmRoot, ConfigurableExpander); + ConfigurableExpander->dmReturnginExpander = oneExpander; + dmRoutingEntryAdd(dmRoot, + ConfigurableExpander, + ConfigurableExpander->downStreamPhys[ConfigurableExpander->currentDownStreamPhyIndex], + configSASAddressHi, + configSASAddressLo + ); + } + } /* if (onePortContext->discovery.status == DISCOVERY_DOWN_STREAM) */ + /* incremental discovery */ + if (onePortContext->discovery.type == DM_DISCOVERY_OPTION_INCREMENTAL_START) + { + connectionRate = MIN(onePortContext->LinkRate, SAS2_DISCRSP_GET_LOGICAL_LINKRATE(pDiscoverResp)); + + if (SAS2_DISCRSP_IS_STP_TARGET(pDiscoverResp) || SAS2_DISCRSP_IS_SATA_DEVICE(pDiscoverResp)) + { + DM_DBG2(("dmDownStreamDiscover2ExpanderPhy: incremental SATA_STP\n")); + + dmPortSASDeviceAdd( + dmRoot, + onePortContext, + sasIdentify, + agFALSE, + connectionRate, + dmAllShared->itNexusTimeout, + 0, + STP_DEVICE_TYPE, + oneDeviceData, + oneExpander, + pDiscoverResp->phyIdentifier + ); + } + else + { + DM_DBG2(("dmDownStreamDiscover2ExpanderPhy: incremental SAS\n")); + + dmPortSASDeviceAdd( + dmRoot, + onePortContext, + sasIdentify, + agFALSE, + connectionRate, + dmAllShared->itNexusTimeout, + 0, + SAS_DEVICE_TYPE, + oneDeviceData, + oneExpander, + pDiscoverResp->phyIdentifier + ); + + } + } + + + }/* else; existing devce */ + } /* not attached to myself */ + /* If the attached device is myself */ + else + { + DM_DBG2(("dmDownStreamDiscover2ExpanderPhy: Found Self\n")); + DM_DBG2(("dmDownStreamDiscover2ExpanderPhy: 3rd before\n")); + dmDumpAllUpExp(dmRoot, onePortContext, oneExpander); + + if (onePortContext->discovery.ConfiguresOthers == agFALSE) + { + UpStreamExpander = oneExpander->dmUpStreamExpander; + ConfigurableExpander = dmFindConfigurableExp(dmRoot, onePortContext, oneExpander); + dupConfigSASAddr = dmDuplicateConfigSASAddr(dmRoot, + ConfigurableExpander, + onePortContext->sasLocalAddressHi, + onePortContext->sasLocalAddressLo + ); + + if ( ConfigurableExpander && dupConfigSASAddr == agFALSE) + { + DM_DBG2(("dmDownStreamDiscover2ExpanderPhy: 3rd q123 Setup routing table\n")); + UpStreamExpander->dmCurrentDownStreamExpander = oneExpander; + ConfigurableExpander->currentDownStreamPhyIndex = + dmFindCurrentDownStreamPhyIndex(dmRoot, ConfigurableExpander); + ConfigurableExpander->dmReturnginExpander = oneExpander; + dmRoutingEntryAdd(dmRoot, + ConfigurableExpander, + ConfigurableExpander->downStreamPhys[ConfigurableExpander->currentDownStreamPhyIndex], + onePortContext->sasLocalAddressHi, + onePortContext->sasLocalAddressLo + ); + } + } + } + } + /* If no device is attached */ + else + { + } + + + /* Increment the discovering phy id */ + oneExpander->discoveringPhyId ++; + + /* If the discovery status is DISCOVERY_DOWN_STREAM */ + if ( onePortContext->discovery.status == DISCOVERY_DOWN_STREAM ) + { + /* If not the last phy */ + if ( oneExpander->discoveringPhyId < oneDeviceData->numOfPhys ) + { + DM_DBG2(("dmDownStreamDiscover2ExpanderPhy: More Phys to discover\n")); + /* continue discovery for the next phy */ + dmDiscoverSend(dmRoot, oneDeviceData); + } + /* If the last phy */ + else + { + DM_DBG2(("dmDownStreamDiscover2ExpanderPhy: No More Phys\n")); + + /* for MCN */ + dmUpdateAllAdjacent(dmRoot, onePortContext, oneDeviceData); + ConfigurableExpander = dmFindConfigurableExp(dmRoot, onePortContext, oneExpander); + if (oneExpander->UndoDueToTTTSupported == agTRUE && ConfigurableExpander != agNULL) +// if (oneExpander->UndoDueToTTTSupported == agTRUE) + { + DM_DBG2(("dmDownStreamDiscover2ExpanderPhy: Not sure!!!\n")); + dmDiscoveringUndoAdd(dmRoot, onePortContext, oneExpander); + oneExpander->UndoDueToTTTSupported = agFALSE; + } + + /* remove the expander from the discovering list */ + dmDiscoveringExpanderRemove(dmRoot, onePortContext, oneExpander); + /* continue downstream discovering */ + dmDownStreamDiscovering(dmRoot, onePortContext, oneDeviceData); + } + } + else + { + DM_DBG2(("dmDownStreamDiscover2ExpanderPhy: onePortContext->discovery.status not in DISCOVERY_DOWN_STREAM; status %d\n", onePortContext->discovery.status)); + } + DM_DBG2(("dmDownStreamDiscover2ExpanderPhy: end return phyID#%d\n", oneExpander->discoveringPhyId - 1)); + + return; +} + + +osGLOBAL void +dmDiscoveringUndoAdd( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmExpander_t *oneExpander + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmList_t *ExpanderList; + dmExpander_t *tempExpander; + dmIntPortContext_t *tmpOnePortContext = onePortContext; + + DM_DBG2(("dmDiscoveringUndoAdd: start\n")); + if (DMLIST_EMPTY(&(tmpOnePortContext->discovery.discoveringExpanderList))) + { + DM_DBG2(("dmDiscoveringUndoAdd: empty discoveringExpanderList\n")); + return; + } + +// DM_DBG2(("dmDiscoveringUndoAdd: before\n")); +// dmDumpAllExp(dmRoot, onePortContext, oneExpander); + + ExpanderList = tmpOnePortContext->discovery.discoveringExpanderList.flink; + while (ExpanderList != &(tmpOnePortContext->discovery.discoveringExpanderList)) + { + tempExpander = DMLIST_OBJECT_BASE(dmExpander_t, linkNode, ExpanderList); + if ( tempExpander == agNULL) + { + DM_DBG1(("dmDiscoveringUndoAdd: tempExpander is NULL!!!\n")); + return; + } + if (tempExpander->dmUpStreamExpander == oneExpander) + { + DM_DBG2(("dmDiscoveringUndoAdd: match!!! expander id %d\n", tempExpander->id)); + DM_DBG2(("dmDiscoveringUndoAdd: exp addrHi 0x%08x\n", tempExpander->dmDevice->SASAddressID.sasAddressHi)); + DM_DBG2(("dmDiscoveringUndoAdd: exp addrLo 0x%08x\n", tempExpander->dmDevice->SASAddressID.sasAddressLo)); + tddmSingleThreadedEnter(dmRoot, DM_EXPANDER_LOCK); + DMLIST_DEQUEUE_THIS(&(tempExpander->linkNode)); +// DMLIST_ENQUEUE_AT_TAIL(&(tempExpander->linkNode), &(dmAllShared->freeExpanderList)); + DMLIST_ENQUEUE_AT_TAIL(&(tempExpander->linkNode), &(dmAllShared->mainExpanderList)); + tddmSingleThreadedLeave(dmRoot, DM_EXPANDER_LOCK); + ExpanderList = tmpOnePortContext->discovery.discoveringExpanderList.flink; + } + if (DMLIST_EMPTY(&(tmpOnePortContext->discovery.discoveringExpanderList))) + { + DM_DBG2(("dmDiscoveringUndoAdd: hitting break\n")); + break; + } + ExpanderList = ExpanderList->flink; + } + +// DM_DBG2(("dmDiscoveringUndoAdd: after\n")); +// dmDumpAllExp(dmRoot, onePortContext, oneExpander); + return; +} + +osGLOBAL void +dmHandleZoneViolation( + dmRoot_t *dmRoot, + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + dmDeviceData_t *oneDeviceData, + dmSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ) +{ + dmIntPortContext_t *onePortContext = agNULL; + dmExpander_t *oneExpander = agNULL; + + DM_DBG1(("dmHandleZoneViolation: start\n")); + DM_DBG1(("dmHandleZoneViolation: sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG1(("dmHandleZoneViolation: sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + onePortContext = oneDeviceData->dmPortContext; + oneExpander = oneDeviceData->dmExpander; + if (dmDiscoverCheck(dmRoot, onePortContext) == agTRUE) + { + DM_DBG1(("dmHandleZoneViolation: invalid port or aborted discovery!!!\n")); + return; + } + /* for MCN */ + dmUpdateAllAdjacent(dmRoot, onePortContext, oneDeviceData); + /* remove the expander from the discovering list */ + dmDiscoveringExpanderRemove(dmRoot, onePortContext, oneExpander); + if ( onePortContext->discovery.status == DISCOVERY_UP_STREAM) + { + /* continue upstream discovering */ + dmUpStreamDiscovering(dmRoot, onePortContext, oneDeviceData); + } + else /* DISCOVERY_DOWN_STREAM or DISCOVERY_CONFIG_ROUTING */ + { + /* continue downstream discovering */ + dmDownStreamDiscovering(dmRoot, onePortContext, oneDeviceData); + } + return; +} + + +osGLOBAL void +dmUpStreamDiscoverExpanderPhySkip( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmExpander_t *oneExpander + ) + +{ + dmDeviceData_t *oneDeviceData; + DM_DBG3(("dmUpStreamDiscoverExpanderPhySkip: start\n")); + + oneDeviceData = oneExpander->dmDevice; + DM_DBG3(("dmUpStreamDiscoverExpanderPhySkip: sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG3(("dmUpStreamDiscoverExpanderPhySkip: sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + + oneExpander->discoveringPhyId++; + if (onePortContext->discovery.status == DISCOVERY_UP_STREAM) + { + if ( oneExpander->discoveringPhyId < oneDeviceData->numOfPhys ) + { + DM_DBG3(("dmUpStreamDiscoverExpanderPhySkip: More Phys to discover\n")); + /* continue discovery for the next phy */ + dmDiscoverSend(dmRoot, oneDeviceData); + } + else + { + DM_DBG3(("dmUpStreamDiscoverExpanderPhySkip: No More Phys\n")); + + /* for MCN */ + dmUpdateAllAdjacent(dmRoot, onePortContext, oneDeviceData); + /* remove the expander from the discovering list */ + dmDiscoveringExpanderRemove(dmRoot, onePortContext, oneExpander); + /* continue upstream discovering */ + dmUpStreamDiscovering(dmRoot, onePortContext, oneDeviceData); + } + } + else + { + DM_DBG3(("dmUpStreamDiscoverExpanderPhySkip: onePortContext->discovery.status not in DISCOVERY_UP_STREAM; status %d\n", onePortContext->discovery.status)); + + } + + DM_DBG3(("dmUpStreamDiscoverExpanderPhySkip: end return phyID#%d\n", oneExpander->discoveringPhyId - 1)); + + return; +} + + +osGLOBAL void +dmUpStreamDiscover2ExpanderPhySkip( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmExpander_t *oneExpander + ) +{ + dmDeviceData_t *oneDeviceData; + + DM_DBG2(("dmUpStreamDiscover2ExpanderPhySkip: start\n")); + oneDeviceData = oneExpander->dmDevice; + + oneExpander->discoveringPhyId++; + if (onePortContext->discovery.status == DISCOVERY_UP_STREAM) + { + if ( oneExpander->discoveringPhyId < oneDeviceData->numOfPhys ) + { + DM_DBG2(("dmUpStreamDiscover2ExpanderPhySkip: DISCOVERY_UP_STREAM find more ...\n")); + /* continue discovery for the next phy */ + dmDiscoverSend(dmRoot, oneDeviceData); + } + else + { + DM_DBG2(("dmUpStreamDiscover2ExpanderPhySkip: DISCOVERY_UP_STREAM last phy continue upstream..\n")); + + /* for MCN */ + dmUpdateAllAdjacent(dmRoot, onePortContext, oneDeviceData); + /* remove the expander from the discovering list */ + dmDiscoveringExpanderRemove(dmRoot, onePortContext, oneExpander); + /* continue upstream discovering */ + dmUpStreamDiscovering(dmRoot, onePortContext, oneDeviceData); + } + } + else + { + DM_DBG2(("dmUpStreamDiscover2ExpanderPhySkip: onePortContext->discovery.status not in DISCOVERY_UP_STREAM; status %d\n", onePortContext->discovery.status)); + } + + DM_DBG2(("dmUpStreamDiscover2ExpanderPhySkip: end return phyID#%d\n", oneExpander->discoveringPhyId - 1)); + + + return; +} + +osGLOBAL void +dmDownStreamDiscoverExpanderPhySkip( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmExpander_t *oneExpander + ) +{ + dmDeviceData_t *oneDeviceData; + DM_DBG3(("dmDownStreamDiscoverExpanderPhySkip: start\n")); + + oneDeviceData = oneExpander->dmDevice; + DM_DBG3(("dmDownStreamDiscoverExpanderPhySkip: sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG3(("dmDownStreamDiscoverExpanderPhySkip: sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + + /* Increment the discovering phy id */ + oneExpander->discoveringPhyId ++; + + /* If the discovery status is DISCOVERY_DOWN_STREAM */ + if ( onePortContext->discovery.status == DISCOVERY_DOWN_STREAM ) + { + /* If not the last phy */ + if ( oneExpander->discoveringPhyId < oneDeviceData->numOfPhys ) + { + DM_DBG3(("dmDownStreamDiscoverExpanderPhySkip: More Phys to discover\n")); + /* continue discovery for the next phy */ + dmDiscoverSend(dmRoot, oneDeviceData); + } + /* If the last phy */ + else + { + DM_DBG3(("dmDownStreamDiscoverExpanderPhySkip: No More Phys\n")); + + /* for MCN */ + dmUpdateAllAdjacent(dmRoot, onePortContext, oneDeviceData); + /* remove the expander from the discovering list */ + dmDiscoveringExpanderRemove(dmRoot, onePortContext, oneExpander); + /* continue downstream discovering */ + dmDownStreamDiscovering(dmRoot, onePortContext, oneDeviceData); + } + } + else + { + DM_DBG3(("dmDownStreamDiscoverExpanderPhySkip: onePortContext->discovery.status not in DISCOVERY_DOWN_STREAM; status %d\n", onePortContext->discovery.status)); + } + DM_DBG3(("dmDownStreamDiscoverExpanderPhySkip: end return phyID#%d\n", oneExpander->discoveringPhyId - 1)); + + + return; +} + +osGLOBAL void +dmDownStreamDiscover2ExpanderPhySkip( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmExpander_t *oneExpander + ) +{ + dmDeviceData_t *oneDeviceData; + + DM_DBG2(("dmDownStreamDiscover2ExpanderPhySkip: start\n")); + + oneDeviceData = oneExpander->dmDevice; + /* Increment the discovering phy id */ + oneExpander->discoveringPhyId ++; + + /* If the discovery status is DISCOVERY_DOWN_STREAM */ + if ( onePortContext->discovery.status == DISCOVERY_DOWN_STREAM ) + { + /* If not the last phy */ + if ( oneExpander->discoveringPhyId < oneDeviceData->numOfPhys ) + { + DM_DBG2(("dmDownStreamDiscover2ExpanderPhySkip: More Phys to discover\n")); + /* continue discovery for the next phy */ + dmDiscoverSend(dmRoot, oneDeviceData); + } + /* If the last phy */ + else + { + DM_DBG2(("dmDownStreamDiscover2ExpanderPhySkip: No More Phys\n")); + + /* for MCN */ + dmUpdateAllAdjacent(dmRoot, onePortContext, oneDeviceData); + /* remove the expander from the discovering list */ + dmDiscoveringExpanderRemove(dmRoot, onePortContext, oneExpander); + /* continue downstream discovering */ + dmDownStreamDiscovering(dmRoot, onePortContext, oneDeviceData); + } + } + else + { + DM_DBG2(("dmDownStreamDiscover2ExpanderPhySkip: onePortContext->discovery.status not in DISCOVERY_DOWN_STREAM; status %d\n", onePortContext->discovery.status)); + } + DM_DBG2(("dmDownStreamDiscover2ExpanderPhySkip: end return phyID#%d\n", oneExpander->discoveringPhyId - 1)); + return; +} + +osGLOBAL void +dmExpanderUpStreamPhyAdd( + dmRoot_t *dmRoot, + dmExpander_t *oneExpander, + bit8 phyId + ) +{ + bit32 i; + bit32 hasSet = agFALSE; + + DM_DBG3(("dmExpanderUpStreamPhyAdd: start, phyid %d\n", phyId)); + DM_DBG3(("dmExpanderUpStreamPhyAdd: exp addrHi 0x%08x\n", oneExpander->dmDevice->SASAddressID.sasAddressHi)); + DM_DBG3(("dmExpanderUpStreamPhyAdd: exp addrLo 0x%08x\n", oneExpander->dmDevice->SASAddressID.sasAddressLo)); + DM_DBG3(("dmExpanderUpStreamPhyAdd: phyid %d numOfUpStreamPhys %d\n", phyId, oneExpander->numOfUpStreamPhys)); + + for ( i = 0; i < oneExpander->numOfUpStreamPhys; i ++ ) + { + if ( oneExpander->upStreamPhys[i] == phyId ) + { + hasSet = agTRUE; + break; + } + } + + if ( hasSet == agFALSE ) + { + oneExpander->upStreamPhys[oneExpander->numOfUpStreamPhys ++] = phyId; + } + + DM_DBG3(("dmExpanderUpStreamPhyAdd: AFTER phyid %d numOfUpStreamPhys %d\n", phyId, oneExpander->numOfUpStreamPhys)); + + /* for debugging */ + for ( i = 0; i < oneExpander->numOfUpStreamPhys; i ++ ) + { + DM_DBG3(("dmExpanderUpStreamPhyAdd: index %d upstream[index] %d\n", i, oneExpander->upStreamPhys[i])); + } + return; +} + +osGLOBAL void +dmExpanderDownStreamPhyAdd( + dmRoot_t *dmRoot, + dmExpander_t *oneExpander, + bit8 phyId + ) +{ + bit32 i; + bit32 hasSet = agFALSE; + + DM_DBG3(("dmExpanderDownStreamPhyAdd: start, phyid %d\n", phyId)); + DM_DBG3(("dmExpanderDownStreamPhyAdd: exp addrHi 0x%08x\n", oneExpander->dmDevice->SASAddressID.sasAddressHi)); + DM_DBG3(("dmExpanderDownStreamPhyAdd: exp addrLo 0x%08x\n", oneExpander->dmDevice->SASAddressID.sasAddressLo)); + DM_DBG3(("dmExpanderDownStreamPhyAdd: phyid %d numOfDownStreamPhys %d\n", phyId, oneExpander->numOfDownStreamPhys)); + + for ( i = 0; i < oneExpander->numOfDownStreamPhys; i ++ ) + { + if ( oneExpander->downStreamPhys[i] == phyId ) + { + hasSet = agTRUE; + break; + } + } + + if ( hasSet == agFALSE ) + { + oneExpander->downStreamPhys[oneExpander->numOfDownStreamPhys ++] = phyId; + } + + DM_DBG3(("dmExpanderDownStreamPhyAdd: AFTER phyid %d numOfDownStreamPhys %d\n", phyId, oneExpander->numOfDownStreamPhys)); + + /* for debugging */ + for ( i = 0; i < oneExpander->numOfDownStreamPhys; i ++ ) + { + DM_DBG3(("dmExpanderDownStreamPhyAdd: index %d downstream[index] %d\n", i, oneExpander->downStreamPhys[i])); + } + return; +} + +osGLOBAL void +dmDiscoveryReportMCN( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmDeviceData_t *oneDeviceData = agNULL; + dmList_t *DeviceListList; + bit16 extension = 0; + dmDeviceData_t *oneAttachedExpDeviceData = agNULL; + + DM_DBG2(("dmDiscoveryReportMCN: start\n")); + +/* + if full disocvery, report all devices using MCN + if incremental discovery, + 1. compare MCN and PrevMCN + 2. report the changed ones; report MCN + 3. set PrevMCN to MCN + PrevMCN = MCN +*/ + + DeviceListList = dmAllShared->MainDeviceList.flink; + while (DeviceListList != &(dmAllShared->MainDeviceList)) + { + oneDeviceData = DMLIST_OBJECT_BASE(dmDeviceData_t, MainLink, DeviceListList); + if ( oneDeviceData == agNULL) + { + DM_DBG1(("dmDiscoveryReportMCN: oneDeviceData is NULL!!!\n")); + return; + } + DM_DBG3(("dmDiscoveryReportMCN: loop did %d\n", oneDeviceData->id)); + if (oneDeviceData->dmPortContext == onePortContext) + { + DM_DBG2(("dmDiscoveryReportMCN: oneDeviceData sasAddressHi 0x%08x sasAddressLo 0x%08x\n", + oneDeviceData->SASAddressID.sasAddressHi, oneDeviceData->SASAddressID.sasAddressLo)); + DM_DBG2(("dmDiscoveryReportMCN: MCN 0x%08x PrevMCN 0x%08x\n", oneDeviceData->MCN, oneDeviceData->PrevMCN)); + + if (onePortContext->discovery.type == DM_DISCOVERY_OPTION_FULL_START) + { + DM_DBG2(("dmDiscoveryReportMCN: FULL_START\n")); + } + else + { + DM_DBG2(("dmDiscoveryReportMCN: INCREMENTAL_START\n")); + } + /* + if MCN is 0, the device is removed + */ + if (oneDeviceData->MCN != oneDeviceData->PrevMCN && oneDeviceData->MCN != 0) + { + DM_DBG2(("dmDiscoveryReportMCN: reporting \n")); + extension = oneDeviceData->dmDeviceInfo.ext; + /* zero out MCN in extension */ + extension = extension & 0x7FF; + /* sets MCN in extension */ + extension = extension | (oneDeviceData->MCN << 11); + DEVINFO_PUT_EXT(&(oneDeviceData->dmDeviceInfo), extension); + DM_DBG5(("dmDiscoveryReportMCN: MCN 0x%08x PrevMCN 0x%08x\n", DEVINFO_GET_EXT_MCN(&(oneDeviceData->dmDeviceInfo)), oneDeviceData->PrevMCN)); + if (oneDeviceData->ExpDevice != agNULL) + { + DM_DBG2(("dmDiscoveryReportMCN: attached expander case\n")); + oneAttachedExpDeviceData = oneDeviceData->ExpDevice; + tddmReportDevice(dmRoot, onePortContext->dmPortContext, &oneDeviceData->dmDeviceInfo, &oneAttachedExpDeviceData->dmDeviceInfo, dmDeviceMCNChange); + } + else + { + DM_DBG2(("dmDiscoveryReportMCN: No attached expander case\n")); + tddmReportDevice(dmRoot, onePortContext->dmPortContext, &oneDeviceData->dmDeviceInfo, agNULL, dmDeviceMCNChange); + } + oneDeviceData->PrevMCN = oneDeviceData->MCN; + } + else + { + DM_DBG2(("dmDiscoveryReportMCN: No change; no reporting \n")); + if (oneDeviceData->MCN == 0) + { + oneDeviceData->PrevMCN = oneDeviceData->MCN; + } + } + + } + DeviceListList = DeviceListList->flink; + } + + return; +} + +osGLOBAL void +dmDiscoveryDumpMCN( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmDeviceData_t *oneDeviceData = agNULL; + dmList_t *DeviceListList; + + DM_DBG3(("dmDiscoveryDumpMCN: start\n")); + + DeviceListList = dmAllShared->MainDeviceList.flink; + while (DeviceListList != &(dmAllShared->MainDeviceList)) + { + oneDeviceData = DMLIST_OBJECT_BASE(dmDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + DM_DBG1(("dmDiscoveryDumpMCN: oneDeviceData is NULL!!!\n")); + return; + } + DM_DBG3(("dmDiscoveryDumpMCN: loop did %d\n", oneDeviceData->id)); + if (oneDeviceData->dmPortContext == onePortContext) + { + DM_DBG3(("dmDiscoveryDumpMCN: oneDeviceData sasAddressHi 0x%08x sasAddressLo 0x%08x\n", + oneDeviceData->SASAddressID.sasAddressHi, oneDeviceData->SASAddressID.sasAddressLo)); + DM_DBG3(("dmDiscoveryDumpMCN: MCN 0x%08x PrevMCN 0x%08x\n", oneDeviceData->MCN, oneDeviceData->PrevMCN)); + } + DeviceListList = DeviceListList->flink; + } + + return; +} + +osGLOBAL void +dmDiscoveryResetMCN( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmDeviceData_t *oneDeviceData = agNULL; + dmList_t *DeviceListList; + + DM_DBG2(("dmDiscoveryResetMCN: start\n")); + + /* reinitialize the device data belonging to this portcontext */ + DeviceListList = dmAllShared->MainDeviceList.flink; + while (DeviceListList != &(dmAllShared->MainDeviceList)) + { + oneDeviceData = DMLIST_OBJECT_BASE(dmDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + DM_DBG1(("dmDiscoveryResetMCN: oneDeviceData is NULL!!!\n")); + return; + } + DM_DBG3(("dmDiscoveryResetMCN: loop did %d\n", oneDeviceData->id)); + if (oneDeviceData->dmPortContext == onePortContext) + { + if (oneDeviceData->ExpDevice != agNULL) + { + DM_DBG2(("dmDiscoveryResetMCN: resetting oneDeviceData->ExpDevice\n")); + oneDeviceData->ExpDevice = agNULL; + } + DM_DBG3(("dmDiscoveryResetMCN: resetting MCN and MCNdone\n")); + oneDeviceData->MCN = 0; + + oneDeviceData->MCNDone = agFALSE; + DM_DBG2(("dmDiscoveryResetMCN: oneDeviceData sasAddressHi 0x%08x sasAddressLo 0x%08x\n", + oneDeviceData->SASAddressID.sasAddressHi, oneDeviceData->SASAddressID.sasAddressLo)); + } + DeviceListList = DeviceListList->flink; + } + + return; +} + + +/* +do min(oneDeviceData, found-one) in all upstream and downstream +find ajcanent expanders and mark it done; sees only ajcacent targets +*/ +osGLOBAL void +dmUpdateAllAdjacent( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmDeviceData_t *oneDeviceData /* current one */ + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmDeviceData_t *tmponeDeviceData = agNULL; + dmList_t *DeviceListList; + + DM_DBG2(("dmUpdateAllAdjacent: start\n")); + if (oneDeviceData == agNULL) + { + DM_DBG1(("dmUpdateAllAdjacent: oneDeviceData is NULL!!!\n")); + return; + } + + oneDeviceData->MCNDone = agTRUE; + + DM_DBG2(("dmUpdateAllAdjacent: oneDeviceData sasAddressHi 0x%08x sasAddressLo 0x%08x\n", + oneDeviceData->SASAddressID.sasAddressHi, oneDeviceData->SASAddressID.sasAddressLo)); + + + DeviceListList = dmAllShared->MainDeviceList.flink; + while (DeviceListList != &(dmAllShared->MainDeviceList)) + { + tmponeDeviceData = DMLIST_OBJECT_BASE(dmDeviceData_t, MainLink, DeviceListList); + if ( tmponeDeviceData == agNULL) + { + DM_DBG1(("dmUpdateAllAdjacent: tmponeDeviceData is NULL!!!\n")); + return; + } + DM_DBG3(("dmUpdateAllAdjacent: loop did %d\n", tmponeDeviceData->id)); + if (tmponeDeviceData->dmPortContext == onePortContext && tmponeDeviceData->ExpDevice == oneDeviceData) + { + DM_DBG2(("dmUpdateAllAdjacent: setting MCN DONE\n")); + DM_DBG2(("dmUpdateAllAdjacent: tmponeDeviceData sasAddressHi 0x%08x sasAddressLo 0x%08x\n", + tmponeDeviceData->SASAddressID.sasAddressHi, tmponeDeviceData->SASAddressID.sasAddressLo)); + tmponeDeviceData->MCNDone = agTRUE; + if (oneDeviceData->directlyAttached == agFALSE) + { + DM_DBG2(("dmUpdateAllAdjacent: tmponeDeviceData MCN 0x%x\n", tmponeDeviceData->MCN)); + DM_DBG2(("dmUpdateAllAdjacent: oneDeviceData MCN 0x%x\n", oneDeviceData->MCN)); + tmponeDeviceData->MCN = MIN(oneDeviceData->MCN, tmponeDeviceData->MCN); + } + + } + DeviceListList = DeviceListList->flink; + } + + return; + +} + +osGLOBAL void +dmUpdateMCN( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmDeviceData_t *AdjacentDeviceData, /* adjacent expander */ + dmDeviceData_t *oneDeviceData /* current one */ + ) +{ + + DM_DBG2(("dmUpdateMCN: start\n")); + + if (AdjacentDeviceData == agNULL) + { + DM_DBG1(("dmUpdateMCN: AdjacentDeviceData is NULL!!!\n")); + return; + } + + if (oneDeviceData == agNULL) + { + DM_DBG1(("dmUpdateMCN: oneDeviceData is NULL!!!\n")); + return; + } + + DM_DBG2(("dmUpdateMCN: Current sasAddressHi 0x%08x sasAddressLo 0x%08x\n", + oneDeviceData->SASAddressID.sasAddressHi, oneDeviceData->SASAddressID.sasAddressLo)); + + DM_DBG2(("dmUpdateMCN: AdjacentDeviceData one sasAddressHi 0x%08x sasAddressLo 0x%08x\n", + AdjacentDeviceData->SASAddressID.sasAddressHi, AdjacentDeviceData->SASAddressID.sasAddressLo)); + + if (onePortContext->discovery.status == DISCOVERY_UP_STREAM) + { + DM_DBG2(("dmUpdateMCN: DISCOVERY_UP_STREAM\n")); + } + + if (onePortContext->discovery.status == DISCOVERY_DOWN_STREAM) + { + DM_DBG2(("dmUpdateMCN: DISCOVERY_DOWN_STREAM\n")); + } + + + /* MCN */ + + /* directly attached one does not have MCN + update only adjacent device data + */ + + if (oneDeviceData->directlyAttached == agTRUE && AdjacentDeviceData->MCNDone == agFALSE) + { + AdjacentDeviceData->MCN++; + DM_DBG2(("dmUpdateMCN: case 1 oneDeviceData MCN 0x%x\n", oneDeviceData->MCN)); + DM_DBG2(("dmUpdateMCN: case 1 AdjacentDeviceData MCN 0x%x\n", AdjacentDeviceData->MCN)); + } + else if (AdjacentDeviceData->MCNDone == agFALSE) + { + AdjacentDeviceData->MCN++; + AdjacentDeviceData->MCN = MIN(oneDeviceData->MCN, AdjacentDeviceData->MCN); + DM_DBG2(("dmUpdateMCN: case 2 oneDeviceData MCN 0x%x\n", oneDeviceData->MCN)); + DM_DBG2(("dmUpdateMCN: case 2 AdjacentDeviceData MCN 0x%x\n", AdjacentDeviceData->MCN)); + } + + + return; +} +/* go through expander list and device list array ??? */ +osGLOBAL dmDeviceData_t * +dmPortSASDeviceFind( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + bit32 sasAddrLo, + bit32 sasAddrHi, + dmDeviceData_t *CurrentDeviceData /* current expander */ + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmDeviceData_t *oneDeviceData, *RetDeviceData=agNULL; + dmList_t *DeviceListList; + + DM_DBG3(("dmPortSASDeviceFind: start\n")); + DM_DBG3(("dmPortSASDeviceFind: sasAddressHi 0x%08x sasAddressLo 0x%08x\n", sasAddrHi, sasAddrLo)); + + DM_ASSERT((agNULL != dmRoot), ""); + DM_ASSERT((agNULL != onePortContext), ""); + + tddmSingleThreadedEnter(dmRoot, DM_DEVICE_LOCK); + + /* find a device's existence */ + DeviceListList = dmAllShared->MainDeviceList.flink; + if (onePortContext->discovery.type == DM_DISCOVERY_OPTION_FULL_START) + { + DM_DBG3(("dmPortSASDeviceFind: Full discovery\n")); + while (DeviceListList != &(dmAllShared->MainDeviceList)) + { + oneDeviceData = DMLIST_OBJECT_BASE(dmDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + DM_DBG1(("dmPortSASDeviceFind: oneDeviceData is NULL!!!\n")); + return agNULL; + } + if ((oneDeviceData->SASAddressID.sasAddressHi == sasAddrHi) && + (oneDeviceData->SASAddressID.sasAddressLo == sasAddrLo) && + (oneDeviceData->valid == agTRUE) && + (oneDeviceData->dmPortContext == onePortContext) + ) + { + DM_DBG3(("dmPortSASDeviceFind: Found pid %d did %d\n", onePortContext->id, oneDeviceData->id)); + DM_DBG3(("dmPortSASDeviceFind: sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG3(("dmPortSASDeviceFind: sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + RetDeviceData = oneDeviceData; + dmUpdateMCN(dmRoot, onePortContext, RetDeviceData, CurrentDeviceData); + break; + } + DeviceListList = DeviceListList->flink; + } + } + else + { + /* incremental discovery */ + DM_DBG3(("dmPortSASDeviceFind: Incremental discovery\n")); + while (DeviceListList != &(dmAllShared->MainDeviceList)) + { + oneDeviceData = DMLIST_OBJECT_BASE(dmDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + DM_DBG1(("dmPortSASDeviceFind: oneDeviceData is NULL!!!\n")); + return agNULL; + } + if ((oneDeviceData->SASAddressID.sasAddressHi == sasAddrHi) && + (oneDeviceData->SASAddressID.sasAddressLo == sasAddrLo) && + (oneDeviceData->valid2 == agTRUE) && + (oneDeviceData->dmPortContext == onePortContext) + ) + { + DM_DBG3(("dmPortSASDeviceFind: Found pid %d did %d\n", onePortContext->id, oneDeviceData->id)); + DM_DBG3(("dmPortSASDeviceFind: sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG3(("dmPortSASDeviceFind: sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + RetDeviceData = oneDeviceData; + dmUpdateMCN(dmRoot, onePortContext, RetDeviceData, CurrentDeviceData); + break; + } + DeviceListList = DeviceListList->flink; + } + } + + tddmSingleThreadedLeave(dmRoot, DM_DEVICE_LOCK); + + return RetDeviceData; +} + +bit32 +dmNewEXPorNot( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmSASSubID_t *dmSASSubID + ) +{ +// dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; +// dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmExpander_t *oneExpander = agNULL; + dmList_t *ExpanderList; + bit32 ret = agTRUE; + dmDeviceData_t *oneDeviceData = agNULL; + + DM_DBG3(("dmNewEXPorNot: start\n")); + + /* find a device's existence */ + ExpanderList = onePortContext->discovery.discoveringExpanderList.flink; + while (ExpanderList != &(onePortContext->discovery.discoveringExpanderList)) + { + oneExpander = DMLIST_OBJECT_BASE(dmExpander_t, linkNode, ExpanderList); + if ( oneExpander == agNULL) + { + DM_DBG1(("dmNewEXPorNot: oneExpander is NULL!!!\n")); + return agFALSE; + } + oneDeviceData = oneExpander->dmDevice; + if ((oneDeviceData->SASAddressID.sasAddressHi == dmSASSubID->sasAddressHi) && + (oneDeviceData->SASAddressID.sasAddressLo == dmSASSubID->sasAddressLo) && + (oneDeviceData->dmPortContext == onePortContext) + ) + { + DM_DBG3(("dmNewEXPorNot: Found pid %d did %d\n", onePortContext->id, oneDeviceData->id)); + ret = agFALSE; + break; + } + ExpanderList = ExpanderList->flink; + } + + return ret; +} + + +bit32 +dmNewSASorNot( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmSASSubID_t *dmSASSubID + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmDeviceData_t *oneDeviceData = agNULL; + dmList_t *DeviceListList; + bit32 ret = agTRUE; + + DM_DBG3(("dmNewSASorNot: start\n")); + + /* find a device's existence */ + DeviceListList = dmAllShared->MainDeviceList.flink; + while (DeviceListList != &(dmAllShared->MainDeviceList)) + { + oneDeviceData = DMLIST_OBJECT_BASE(dmDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + DM_DBG1(("dmNewSASorNot: oneDeviceData is NULL!!!\n")); + return agFALSE; + } + if ((oneDeviceData->SASAddressID.sasAddressHi == dmSASSubID->sasAddressHi) && + (oneDeviceData->SASAddressID.sasAddressLo == dmSASSubID->sasAddressLo) && + (oneDeviceData->dmPortContext == onePortContext) && + (oneDeviceData->registered == agTRUE) + ) + { + DM_DBG3(("dmNewSASorNot: Found pid %d did %d\n", onePortContext->id, oneDeviceData->id)); + ret = agFALSE; + break; + } + DeviceListList = DeviceListList->flink; + } + + return ret; +} +/* +call +osGLOBAL bit32 +tddmReportDevice( + dmRoot_t *dmRoot, + dmPortContext_t *dmPortContext, + dmDeviceInfo_t *dmDeviceInfo + ) +if not reported, report Device to TDM +*/ +osGLOBAL dmDeviceData_t * +dmPortSASDeviceAdd( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + agsaSASIdentify_t sasIdentify, + bit32 sasInitiator, + bit8 connectionRate, + bit32 itNexusTimeout, + bit32 firstBurstSize, + bit32 deviceType, + dmDeviceData_t *oneExpDeviceData, + dmExpander_t *dmExpander, + bit8 phyID + ) +{ + dmDeviceData_t *oneDeviceData = agNULL; + bit8 dev_s_rate = 0; + bit8 sasorsata = 1; + dmSASSubID_t dmSASSubID; + bit8 ExpanderConnectionRate = connectionRate; + dmDeviceData_t *oneAttachedExpDeviceData = agNULL; + bit16 extension = 0; + bit32 current_link_rate = 0; + + DM_DBG3(("dmPortSASDeviceAdd: start\n")); + DM_DBG3(("dmPortSASDeviceAdd: connectionRate %d\n", connectionRate)); + + dmSASSubID.sasAddressHi = SA_IDFRM_GET_SAS_ADDRESSHI(&sasIdentify); + dmSASSubID.sasAddressLo = SA_IDFRM_GET_SAS_ADDRESSLO(&sasIdentify); + dmSASSubID.initiator_ssp_stp_smp = sasIdentify.initiator_ssp_stp_smp; + dmSASSubID.target_ssp_stp_smp = sasIdentify.target_ssp_stp_smp; + + if (oneExpDeviceData != agNULL) + { + ExpanderConnectionRate = DEVINFO_GET_LINKRATE(&oneExpDeviceData->agDeviceInfo); + DM_DBG3(("dmPortSASDeviceAdd: ExpanderConnectionRate 0x%x\n", ExpanderConnectionRate)); + } + if (oneExpDeviceData != agNULL) + { + if (oneExpDeviceData->SASAddressID.sasAddressHi == 0x0 && + oneExpDeviceData->SASAddressID.sasAddressLo == 0x0) + { + DM_DBG1(("dmPortSASDeviceAdd: 1st Wrong expander!!!\n")); + } + } + /* old device and already reported to TDM */ + if ( agFALSE == dmNewSASorNot( + dmRoot, + onePortContext, + &dmSASSubID + ) + ) /* old device */ + { + DM_DBG3(("dmPortSASDeviceAdd: OLD qqqq initiator_ssp_stp_smp %d target_ssp_stp_smp %d\n", dmSASSubID.initiator_ssp_stp_smp, dmSASSubID.target_ssp_stp_smp)); + /* allocate a new device and set the valid bit */ + oneDeviceData = dmAddSASToSharedcontext( + dmRoot, + onePortContext, + &dmSASSubID, + oneExpDeviceData, + phyID + ); + if (oneDeviceData == agNULL) + { + DM_DBG1(("dmPortSASDeviceAdd: no more device, oneDeviceData is null!!!\n")); + } + /* If a device is allocated */ + if ( oneDeviceData != agNULL ) + { + + + if (onePortContext->discovery.status == DISCOVERY_UP_STREAM) + { + DM_DBG3(("dmPortSASDeviceAdd: OLD, UP_STREAM\n")); + } + if (onePortContext->discovery.status == DISCOVERY_DOWN_STREAM) + { + DM_DBG3(("dmPortSASDeviceAdd: OLD, DOWN_STREAM\n")); + } + + if (onePortContext->discovery.type == DM_DISCOVERY_OPTION_FULL_START) + { + DM_DBG3(("dmPortSASDeviceAdd: FULL_START\n")); + oneDeviceData->MCN++; + } + else + { + /* incremental */ + DM_DBG3(("dmPortSASDeviceAdd: INCREMENTAL_START\n")); + if (oneDeviceData->MCN == 0 && oneDeviceData->directlyAttached == agFALSE) + { + oneDeviceData->MCN++; + } + } + + DM_DBG3(("dmPortSASDeviceAdd: oneDeviceData MCN 0x%08x\n", oneDeviceData->MCN)); + DM_DBG3(("dmPortSASDeviceAdd: oneDeviceData sasAddressHi 0x%08x sasAddressLo 0x%08x\n", + oneDeviceData->SASAddressID.sasAddressHi, oneDeviceData->SASAddressID.sasAddressLo)); + + + DM_DBG3(("dmPortSASDeviceAdd: sasAddressHi 0x%08x\n", SA_IDFRM_GET_SAS_ADDRESSHI(&sasIdentify))); + DM_DBG3(("dmPortSASDeviceAdd: sasAddressLo 0x%08x\n", SA_IDFRM_GET_SAS_ADDRESSLO(&sasIdentify))); + +// oneDeviceData->sasIdentify = sasIdentify; + dm_memcpy(&(oneDeviceData->sasIdentify), &sasIdentify, sizeof(agsaSASIdentify_t)); + + DM_DBG3(("dmPortSASDeviceAdd: sasAddressHi 0x%08x\n", SA_IDFRM_GET_SAS_ADDRESSHI(&oneDeviceData->sasIdentify))); + DM_DBG3(("dmPortSASDeviceAdd: sasAddressLo 0x%08x\n", SA_IDFRM_GET_SAS_ADDRESSLO(&oneDeviceData->sasIdentify))); + + /* parse sasIDframe to fill in agDeviceInfo */ + DEVINFO_PUT_SMPTO(&oneDeviceData->agDeviceInfo, DEFAULT_SMP_TIMEOUT); + DEVINFO_PUT_ITNEXUSTO(&oneDeviceData->agDeviceInfo, (bit16)itNexusTimeout); + DEVINFO_PUT_FBS(&oneDeviceData->agDeviceInfo, (bit16)firstBurstSize); + DEVINFO_PUT_FLAG(&oneDeviceData->agDeviceInfo, 1); + + oneDeviceData->SASSpecDeviceType = SA_IDFRM_GET_DEVICETTYPE(&sasIdentify); + + /* adjusting connectionRate */ + oneAttachedExpDeviceData = oneDeviceData->ExpDevice; + if (oneAttachedExpDeviceData != agNULL) + { + connectionRate = MIN(connectionRate, DEVINFO_GET_LINKRATE(&oneAttachedExpDeviceData->agDeviceInfo)); + DM_DBG3(("dmPortSASDeviceAdd: 1st connectionRate 0x%x DEVINFO_GET_LINKRATE(&oneAttachedExpDeviceData->agDeviceInfo) 0x%x\n", + connectionRate, DEVINFO_GET_LINKRATE(&oneAttachedExpDeviceData->agDeviceInfo))); + } + else + { + DM_DBG3(("dmPortSASDeviceAdd: 1st oneAttachedExpDeviceData is NULL\n")); + } + + /* Device Type, SAS or SATA, connection rate; bit7 --- bit0 */ + sasorsata = (bit8)deviceType; + /* sTSDK spec device typ */ + dev_s_rate = dev_s_rate | (sasorsata << 4); + dev_s_rate = dev_s_rate | MIN(connectionRate, ExpanderConnectionRate); + /* detect link rate change */ + current_link_rate = DEVINFO_GET_LINKRATE(&oneDeviceData->agDeviceInfo); + if (current_link_rate != (bit32)MIN(connectionRate, ExpanderConnectionRate)) + { + DM_DBG1(("dmPortSASDeviceAdd: link rate changed current 0x%x new 0x%x\n", current_link_rate, MIN(connectionRate, ExpanderConnectionRate))); + DEVINFO_PUT_DEV_S_RATE(&oneDeviceData->dmDeviceInfo, dev_s_rate); + if (oneDeviceData->ExpDevice != agNULL) + { + oneAttachedExpDeviceData = oneDeviceData->ExpDevice; + tddmReportDevice(dmRoot, onePortContext->dmPortContext, &oneDeviceData->dmDeviceInfo, &oneAttachedExpDeviceData->dmDeviceInfo, dmDeviceRateChange); + } + else + { + tddmReportDevice(dmRoot, onePortContext->dmPortContext, &oneDeviceData->dmDeviceInfo, agNULL, dmDeviceArrival); + } + } + + DEVINFO_PUT_DEV_S_RATE(&oneDeviceData->agDeviceInfo, dev_s_rate); + + + DEVINFO_PUT_SAS_ADDRESSLO( + &oneDeviceData->agDeviceInfo, + SA_IDFRM_GET_SAS_ADDRESSLO(&oneDeviceData->sasIdentify) + ); + DEVINFO_PUT_SAS_ADDRESSHI( + &oneDeviceData->agDeviceInfo, + SA_IDFRM_GET_SAS_ADDRESSHI(&oneDeviceData->sasIdentify) + ); + oneDeviceData->agContext.osData = oneDeviceData; + oneDeviceData->agContext.sdkData = agNULL; + + + } + return oneDeviceData; + } /* old device */ + + + /* new device */ + + DM_DBG3(("dmPortSASDeviceAdd: NEW qqqq initiator_ssp_stp_smp %d target_ssp_stp_smp %d\n", dmSASSubID.initiator_ssp_stp_smp, dmSASSubID.target_ssp_stp_smp)); + + /* allocate a new device and set the valid bit */ + oneDeviceData = dmAddSASToSharedcontext( + dmRoot, + onePortContext, + &dmSASSubID, + oneExpDeviceData, + phyID + ); + if (oneDeviceData == agNULL) + { + DM_DBG1(("dmPortSASDeviceAdd: no more device, oneDeviceData is null !!!\n")); + } + + /* If a device is allocated */ + if ( oneDeviceData != agNULL ) + { + +// DM_DBG3(("dmPortSASDeviceAdd: sasAddressHi 0x%08x\n", SA_IDFRM_GET_SAS_ADDRESSHI(&sasIdentify))); +// DM_DBG3(("dmPortSASDeviceAdd: sasAddressLo 0x%08x\n", SA_IDFRM_GET_SAS_ADDRESSLO(&sasIdentify))); + +// oneDeviceData->sasIdentify = sasIdentify; + dm_memcpy(&(oneDeviceData->sasIdentify), &sasIdentify, sizeof(agsaSASIdentify_t)); + + if (onePortContext->discovery.status == DISCOVERY_UP_STREAM) + { + DM_DBG3(("dmPortSASDeviceAdd: NEW, UP_STREAM\n")); + } + if (onePortContext->discovery.status == DISCOVERY_DOWN_STREAM) + { + DM_DBG3(("dmPortSASDeviceAdd: NEW, DOWN_STREAM\n")); + } + + if (onePortContext->discovery.type == DM_DISCOVERY_OPTION_FULL_START) + { + DM_DBG3(("dmPortSASDeviceAdd: FULL_START\n")); + oneDeviceData->MCN++; + } + else + { + /* incremental */ + DM_DBG3(("dmPortSASDeviceAdd: INCREMENTAL_START\n")); + if (oneDeviceData->MCN == 0 && oneDeviceData->directlyAttached == agFALSE) + { + oneDeviceData->MCN++; + } + } + DM_DBG3(("dmPortSASDeviceAdd: oneDeviceData MCN 0x%08x\n", oneDeviceData->MCN)); + DM_DBG3(("dmPortSASDeviceAdd: oneDeviceData sasAddressHi 0x%08x sasAddressLo 0x%08x\n", + oneDeviceData->SASAddressID.sasAddressHi, oneDeviceData->SASAddressID.sasAddressLo)); + + DM_DBG3(("dmPortSASDeviceAdd: sasAddressHi 0x%08x\n", SA_IDFRM_GET_SAS_ADDRESSHI(&oneDeviceData->sasIdentify))); + DM_DBG3(("dmPortSASDeviceAdd: sasAddressLo 0x%08x\n", SA_IDFRM_GET_SAS_ADDRESSLO(&oneDeviceData->sasIdentify))); + + /* parse sasIDframe to fill in agDeviceInfo */ + DEVINFO_PUT_SMPTO(&oneDeviceData->agDeviceInfo, DEFAULT_SMP_TIMEOUT); + DEVINFO_PUT_ITNEXUSTO(&oneDeviceData->agDeviceInfo, (bit16)itNexusTimeout); + DEVINFO_PUT_FBS(&oneDeviceData->agDeviceInfo, (bit16)firstBurstSize); + DEVINFO_PUT_FLAG(&oneDeviceData->agDeviceInfo, 1); + + oneDeviceData->SASSpecDeviceType = SA_IDFRM_GET_DEVICETTYPE(&sasIdentify); + + /* adjusting connectionRate */ + oneAttachedExpDeviceData = oneDeviceData->ExpDevice; + if (oneAttachedExpDeviceData != agNULL) + { + connectionRate = MIN(connectionRate, DEVINFO_GET_LINKRATE(&oneAttachedExpDeviceData->agDeviceInfo)); + DM_DBG3(("dmPortSASDeviceAdd: 2nd connectionRate 0x%x DEVINFO_GET_LINKRATE(&oneAttachedExpDeviceData->agDeviceInfo) 0x%x\n", + connectionRate, DEVINFO_GET_LINKRATE(&oneAttachedExpDeviceData->agDeviceInfo))); + } + else + { + DM_DBG3(("dmPortSASDeviceAdd: 2nd oneAttachedExpDeviceData is NULL\n")); + } + + /* Device Type, SAS or SATA, connection rate; bit7 --- bit0 */ + sasorsata = (bit8)deviceType; + dev_s_rate = dev_s_rate | (sasorsata << 4); + dev_s_rate = dev_s_rate | MIN(connectionRate, ExpanderConnectionRate); + DEVINFO_PUT_DEV_S_RATE(&oneDeviceData->agDeviceInfo, dev_s_rate); + + + DEVINFO_PUT_SAS_ADDRESSLO( + &oneDeviceData->agDeviceInfo, + SA_IDFRM_GET_SAS_ADDRESSLO(&oneDeviceData->sasIdentify) + ); + DEVINFO_PUT_SAS_ADDRESSHI( + &oneDeviceData->agDeviceInfo, + SA_IDFRM_GET_SAS_ADDRESSHI(&oneDeviceData->sasIdentify) + ); + oneDeviceData->agContext.osData = oneDeviceData; + oneDeviceData->agContext.sdkData = agNULL; + + DM_DBG3(("dmPortSASDeviceAdd: did %d\n", oneDeviceData->id)); + + + /* reporting to TDM; setting dmDeviceInfo */ + DEVINFO_PUT_SMPTO(&oneDeviceData->dmDeviceInfo, DEFAULT_SMP_TIMEOUT); + DEVINFO_PUT_ITNEXUSTO(&oneDeviceData->dmDeviceInfo, (bit16)itNexusTimeout); + DEVINFO_PUT_FBS(&oneDeviceData->dmDeviceInfo, (bit16)firstBurstSize); + DEVINFO_PUT_FLAG(&oneDeviceData->dmDeviceInfo, 1); + DEVINFO_PUT_INITIATOR_SSP_STP_SMP(&oneDeviceData->dmDeviceInfo, dmSASSubID.initiator_ssp_stp_smp); + DEVINFO_PUT_TARGET_SSP_STP_SMP(&oneDeviceData->dmDeviceInfo, dmSASSubID.target_ssp_stp_smp); + extension = phyID; + + /* setting 6th bit of dev_s_rate */ + if (oneDeviceData->SASSpecDeviceType == SAS_EDGE_EXPANDER_DEVICE || + oneDeviceData->SASSpecDeviceType == SAS_FANOUT_EXPANDER_DEVICE ) + { + extension = (bit16)(extension | (1 << 8)); + } + DEVINFO_PUT_EXT(&oneDeviceData->dmDeviceInfo, extension); + + DEVINFO_PUT_DEV_S_RATE(&oneDeviceData->dmDeviceInfo, dev_s_rate); + + DEVINFO_PUT_SAS_ADDRESSLO( + &oneDeviceData->dmDeviceInfo, + SA_IDFRM_GET_SAS_ADDRESSLO(&oneDeviceData->sasIdentify) + ); + DEVINFO_PUT_SAS_ADDRESSHI( + &oneDeviceData->dmDeviceInfo, + SA_IDFRM_GET_SAS_ADDRESSHI(&oneDeviceData->sasIdentify) + ); + + if (oneDeviceData->ExpDevice != agNULL) + { + DM_DBG3(("dmPortSASDeviceAdd: attached expander case\n")); + oneAttachedExpDeviceData = oneDeviceData->ExpDevice; + /* + Puts attached expander's SAS address into dmDeviceInfo + */ + DEVINFO_PUT_SAS_ADDRESSLO( + &oneAttachedExpDeviceData->dmDeviceInfo, + oneAttachedExpDeviceData->SASAddressID.sasAddressLo + ); + DEVINFO_PUT_SAS_ADDRESSHI( + &oneAttachedExpDeviceData->dmDeviceInfo, + oneAttachedExpDeviceData->SASAddressID.sasAddressHi + ); + DM_DBG3(("dmPortSASDeviceAdd: oneAttachedExpDeviceData addrHi 0x%08x addrLo 0x%08x PhyID 0x%x ext 0x%x\n", + DM_GET_SAS_ADDRESSHI(oneAttachedExpDeviceData->dmDeviceInfo.sasAddressHi), + DM_GET_SAS_ADDRESSLO(oneAttachedExpDeviceData->dmDeviceInfo.sasAddressLo), + phyID, extension)); + + if (oneAttachedExpDeviceData->SASAddressID.sasAddressHi == 0x0 && + oneAttachedExpDeviceData->SASAddressID.sasAddressLo == 0x0) + { + DM_DBG1(("dmPortSASDeviceAdd: 2nd Wrong expander!!!\n")); + } + if (oneDeviceData->reported == agFALSE) + { + oneDeviceData->registered = agTRUE; + oneDeviceData->reported = agTRUE; + if (deviceType == STP_DEVICE_TYPE) + { + /*STP device, DM need send SMP Report Phy SATA to get the SATA device type */ + oneAttachedExpDeviceData->dmExpander->dmDeviceToProcess = oneDeviceData; + dmReportPhySataSend(dmRoot, oneAttachedExpDeviceData, phyID); + } + else + { + /* SAS or SMP device */ + tddmReportDevice(dmRoot, onePortContext->dmPortContext, &oneDeviceData->dmDeviceInfo, &oneAttachedExpDeviceData->dmDeviceInfo, dmDeviceArrival); + } + } + } + else + { + DM_DBG3(("dmPortSASDeviceAdd: NO attached expander case\n")); + if (oneDeviceData->reported == agFALSE) + { + oneDeviceData->registered = agTRUE; + oneDeviceData->reported = agTRUE; + tddmReportDevice(dmRoot, onePortContext->dmPortContext, &oneDeviceData->dmDeviceInfo, agNULL, dmDeviceArrival); + } + } + } + + return oneDeviceData; +} + +osGLOBAL dmDeviceData_t * +dmFindRegNValid( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmSASSubID_t *dmSASSubID + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmDeviceData_t *oneDeviceData = agNULL; + dmList_t *DeviceListList; + bit32 found = agFALSE; + DM_DBG3(("dmFindRegNValid: start\n")); + + /* find a device's existence */ + DeviceListList = dmAllShared->MainDeviceList.flink; + if (onePortContext->discovery.type == DM_DISCOVERY_OPTION_FULL_START) + { + DM_DBG3(("dmFindRegNValid: Full discovery\n")); + while (DeviceListList != &(dmAllShared->MainDeviceList)) + { + oneDeviceData = DMLIST_OBJECT_BASE(dmDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + DM_DBG1(("dmFindRegNValid: oneDeviceData is NULL!!!\n")); + return agFALSE; + } + if ((oneDeviceData->SASAddressID.sasAddressHi == dmSASSubID->sasAddressHi) && + (oneDeviceData->SASAddressID.sasAddressLo == dmSASSubID->sasAddressLo) && + (oneDeviceData->valid == agTRUE) && + (oneDeviceData->dmPortContext == onePortContext) + ) + { + DM_DBG3(("dmFindRegNValid: Found pid %d did %d\n", onePortContext->id, oneDeviceData->id)); + DM_DBG3(("dmFindRegNValid: sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG3(("dmFindRegNValid: sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + found = agTRUE; + break; + } + DeviceListList = DeviceListList->flink; + } + } + else + { + /* incremental discovery */ + DM_DBG3(("dmFindRegNValid: Incremental discovery\n")); + while (DeviceListList != &(dmAllShared->MainDeviceList)) + { + oneDeviceData = DMLIST_OBJECT_BASE(dmDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + DM_DBG1(("dmFindRegNValid: oneDeviceData is NULL!!!\n")); + return agFALSE; + } + if ((oneDeviceData->SASAddressID.sasAddressHi == dmSASSubID->sasAddressHi) && + (oneDeviceData->SASAddressID.sasAddressLo == dmSASSubID->sasAddressLo) && + (oneDeviceData->valid2 == agTRUE) && + (oneDeviceData->dmPortContext == onePortContext) + ) + { + DM_DBG3(("dmFindRegNValid: Found pid %d did %d\n", onePortContext->id, oneDeviceData->id)); + DM_DBG3(("dmFindRegNValid: sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG3(("dmFindRegNValid: sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + found = agTRUE; + break; + } + DeviceListList = DeviceListList->flink; + } + } + + + + if (found == agFALSE) + { + DM_DBG3(("dmFindRegNValid: end returning NULL\n")); + return agNULL; + } + else + { + DM_DBG3(("dmFindRegNValid: end returning NOT NULL\n")); + return oneDeviceData; + } +} + +osGLOBAL void +dmNotifyBC( + dmRoot_t *dmRoot, + dmPortContext_t *dmPortContext, + bit32 type) +{ + dmIntPortContext_t *onePortContext = agNULL; + + onePortContext = (dmIntPortContext_t *)dmPortContext->dmData; + + DM_DBG3(("dmNotifyBC: start\n")); + + if (onePortContext == agNULL) + { + DM_DBG1(("dmNotifyBC: onePortContext is NULL, wrong!!!\n")); + return; + } + + if (type == OSSA_HW_EVENT_BROADCAST_CHANGE) + { + if (onePortContext->DiscoveryAbortInProgress == agFALSE) + { + if (onePortContext->DiscoveryState == DM_DSTATE_COMPLETED) + { + DM_DBG3(("dmNotifyBC: BROADCAST_CHANGE\n")); + onePortContext->DiscoveryState = DM_DSTATE_NOT_STARTED; + onePortContext->discoveryOptions = DM_DISCOVERY_OPTION_INCREMENTAL_START; + /* processed broadcast change */ + onePortContext->discovery.SeenBC = agFALSE; + } + else + { + DM_DBG3(("dmNotifyBC: pid %d BROADCAST_CHANGE; updating SeenBC. Do nothing.\n", onePortContext->id)); + onePortContext->discovery.SeenBC = agTRUE; + } + } + } + else if (type == OSSA_HW_EVENT_BROADCAST_SES) + { + DM_DBG3(("dmNotifyBC: OSSA_HW_EVENT_BROADCAST_SES\n")); + } + else if (type == OSSA_HW_EVENT_BROADCAST_EXP) + { + DM_DBG3(("dmNotifyBC: OSSA_HW_EVENT_BROADCAST_EXP\n")); + } + else + { + DM_DBG3(("dmNotifyBC: unspecified broadcast type 0x%x\n", type)); + } + return; +} + + +#ifdef WORKED +/* triggers incremental discovery */ +osGLOBAL void +dmNotifyBC( + dmRoot_t *dmRoot, + dmPortContext_t *dmPortContext, + bit32 type) +{ + dmIntPortContext_t *onePortContext = agNULL; + + onePortContext = (dmIntPortContext_t *)dmPortContext->dmData; + + DM_DBG3(("dmNotifyBC: start\n")); + + + if (type == OSSA_HW_EVENT_BROADCAST_CHANGE) + { + if (onePortContext->DiscoveryState == DM_DSTATE_COMPLETED) + { + DM_DBG3(("dmNotifyBC: BROADCAST_CHANGE; does incremental discovery\n")); + onePortContext->DiscoveryState = DM_DSTATE_NOT_STARTED; + onePortContext->discoveryOptions = DM_DISCOVERY_OPTION_INCREMENTAL_START; + /* processed broadcast change */ + onePortContext->discovery.SeenBC = agFALSE; + if (onePortContext->discovery.ResetTriggerred == agTRUE) + { + DM_DBG3(("dmNotifyBC: tdsaBCTimer\n")); + dmBCTimer(dmRoot, onePortContext); + } + else + { + dmDiscover( + dmRoot, + dmPortContext, + DM_DISCOVERY_OPTION_INCREMENTAL_START + ); + } + } + else + { + DM_DBG3(("dmNotifyBC: pid %d BROADCAST_CHANGE; updating SeenBC. Do nothing.\n", onePortContext->id)); + onePortContext->discovery.SeenBC = agTRUE; + } + } + else if (type == OSSA_HW_EVENT_BROADCAST_SES) + { + DM_DBG3(("dmNotifyBC: OSSA_HW_EVENT_BROADCAST_SES\n")); + } + else if (type == OSSA_HW_EVENT_BROADCAST_EXP) + { + DM_DBG3(("dmNotifyBC: OSSA_HW_EVENT_BROADCAST_EXP\n")); + } + else + { + DM_DBG3(("dmNotifyBC: unspecified broadcast type 0x%x\n", type)); + } + return; +} +#endif + +osGLOBAL bit32 +dmResetFailedDiscovery( + dmRoot_t *dmRoot, + dmPortContext_t *dmPortContext) +{ + dmIntPortContext_t *onePortContext = agNULL; + + DM_DBG1(("dmResetFailedDiscovery: start\n")); + + onePortContext = (dmIntPortContext_t *)dmPortContext->dmData; + + if (onePortContext == agNULL) + { + DM_DBG1(("dmResetFailedDiscovery: onePortContext is NULL, wrong!!!\n")); + return DM_RC_FAILURE; + } + + if (onePortContext->DiscoveryState == DM_DSTATE_COMPLETED_WITH_FAILURE) + { + onePortContext->DiscoveryState = DM_DSTATE_COMPLETED; + } + else + { + DM_DBG1(("dmResetFailedDiscovery: discovery is NOT DM_DSTATE_COMPLETED_WITH_FAILURE. It is 0x%x\n", onePortContext->DiscoveryState)); + return DM_RC_FAILURE; + } + + return DM_RC_SUCCESS; +} + +osGLOBAL bit32 +dmQueryDiscovery( + dmRoot_t *dmRoot, + dmPortContext_t *dmPortContext) +{ + dmIntPortContext_t *onePortContext = agNULL; + + DM_DBG3(("dmQueryDiscovery: start\n")); + + onePortContext = (dmIntPortContext_t *)dmPortContext->dmData; + + if (onePortContext == agNULL) + { + DM_DBG1(("dmQueryDiscovery: onePortContext is NULL, wrong!!!\n")); + return DM_RC_FAILURE; + } + + /* call tddmQueryDiscoveryCB() */ + if (onePortContext->DiscoveryState == DM_DSTATE_COMPLETED) + { + tddmQueryDiscoveryCB(dmRoot, dmPortContext, onePortContext->discoveryOptions, dmDiscCompleted); + } + else if (onePortContext->DiscoveryState == DM_DSTATE_COMPLETED_WITH_FAILURE) + { + tddmQueryDiscoveryCB(dmRoot, dmPortContext, onePortContext->discoveryOptions, dmDiscFailed); + } + else + { + tddmQueryDiscoveryCB(dmRoot, dmPortContext, onePortContext->discoveryOptions, dmDiscInProgress); + } + + return DM_RC_SUCCESS; +} + + +/* + should only for an expander +*/ +osGLOBAL bit32 +dmRegisterDevice( + dmRoot_t *dmRoot, + dmPortContext_t *dmPortContext, + dmDeviceInfo_t *dmDeviceInfo, + agsaDevHandle_t *agDevHandle + ) +{ + + dmIntPortContext_t *onePortContext = agNULL; + dmExpander_t *oneExpander = agNULL; + bit32 sasAddressHi, sasAddressLo; + dmDeviceData_t *oneDeviceData = agNULL; + dmSASSubID_t dmSASSubID; + + DM_DBG3(("dmRegisterDevice: start\n")); + + onePortContext = (dmIntPortContext_t *)dmPortContext->dmData; + if (onePortContext == agNULL) + { + DM_DBG1(("dmRegisterDevice: onePortContext is NULL!!!\n")); + return DM_RC_FAILURE; + } + + if (onePortContext->valid == agFALSE) + { + DM_DBG1(("dmRegisterDevice: invalid port!!!\n")); + return DM_RC_FAILURE; + } + + onePortContext->RegFailed = agFALSE; + + /* tdssAddSASToSharedcontext() from ossaHwCB() +osGLOBAL void +tdssAddSASToSharedcontext( + tdsaPortContext_t *tdsaPortContext_Instance, + agsaRoot_t *agRoot, + agsaDevHandle_t *agDevHandle, + tdsaSASSubID_t *agSASSubID, + bit32 registered, + bit8 phyID, + bit32 flag + ); +from discovery +osGLOBAL tdsaDeviceData_t * +tdssNewAddSASToSharedcontext( + agsaRoot_t *agRoot, + tdsaPortContext_t *onePortContext, + tdsaSASSubID_t *agSASSubID, + tdsaDeviceData_t *oneExpDeviceData, + bit8 phyID + ); + + */ + /* start here */ + dmSASSubID.sasAddressHi = DM_GET_SAS_ADDRESSHI(dmDeviceInfo->sasAddressHi); + dmSASSubID.sasAddressLo = DM_GET_SAS_ADDRESSHI(dmDeviceInfo->sasAddressLo); + dmSASSubID.initiator_ssp_stp_smp = dmDeviceInfo->initiator_ssp_stp_smp; + dmSASSubID.target_ssp_stp_smp = dmDeviceInfo->target_ssp_stp_smp; + + oneDeviceData = dmAddSASToSharedcontext(dmRoot, onePortContext, &dmSASSubID, agNULL, 0xFF); + if (oneDeviceData == agNULL) + { + DM_DBG1(("dmRegisterDevice: oneDeviceData is NULL!!!\n")); + return DM_RC_FAILURE; + } + oneDeviceData->agDeviceInfo.devType_S_Rate = dmDeviceInfo->devType_S_Rate; + dm_memcpy(oneDeviceData->agDeviceInfo.sasAddressHi, dmDeviceInfo->sasAddressHi, 4); + dm_memcpy(oneDeviceData->agDeviceInfo.sasAddressLo, dmDeviceInfo->sasAddressLo, 4); + /* finds the type of expanders */ + if (DEVINFO_GET_EXT_SMP(dmDeviceInfo)) + { + if (DEVINFO_GET_EXT_EXPANDER_TYPE(dmDeviceInfo) == SAS_EDGE_EXPANDER_DEVICE) + { + oneDeviceData->SASSpecDeviceType = SAS_EDGE_EXPANDER_DEVICE; + } + else if (DEVINFO_GET_EXT_EXPANDER_TYPE(dmDeviceInfo) == SAS_FANOUT_EXPANDER_DEVICE) + { + oneDeviceData->SASSpecDeviceType = SAS_FANOUT_EXPANDER_DEVICE; + } + else + { + /* default */ + DM_DBG4(("dmRegisterDevice: no expander type. default to edge expander\n")); + oneDeviceData->SASSpecDeviceType = SAS_EDGE_EXPANDER_DEVICE; + } + } + + if (DEVINFO_GET_EXT_MCN(dmDeviceInfo) == 0xF) + { + DM_DBG1(("dmRegisterDevice: directly attached expander\n")); + oneDeviceData->directlyAttached = agTRUE; + oneDeviceData->dmDeviceInfo.ext = (bit16)(oneDeviceData->dmDeviceInfo.ext | (0xF << 11)); + } + else + { + DM_DBG1(("dmRegisterDevice: NOT directly attached expander\n")); + oneDeviceData->directlyAttached = agFALSE; + } + + if (onePortContext->DiscoveryState == DM_DSTATE_NOT_STARTED) + { + DM_DBG3(("dmRegisterDevice: DM_DSTATE_NOT_STARTED\n")); + /* before the discovery is started */ + oneExpander = dmDiscoveringExpanderAlloc(dmRoot, onePortContext, oneDeviceData); + if ( oneExpander != agNULL) + { + oneExpander->agDevHandle = agDevHandle; + /* update SAS address field */ + oneExpander->dmDevice->SASAddressID.sasAddressHi = DM_GET_SAS_ADDRESSHI(dmDeviceInfo->sasAddressHi); + oneExpander->dmDevice->SASAddressID.sasAddressLo = DM_GET_SAS_ADDRESSLO(dmDeviceInfo->sasAddressLo); + DM_DBG3(("dmRegisterDevice: AddrHi 0x%08x AddrLo 0x%08x\n", oneExpander->dmDevice->SASAddressID.sasAddressHi, oneExpander->dmDevice->SASAddressID.sasAddressLo)); + dmDiscoveringExpanderAdd(dmRoot, onePortContext, oneExpander); + } + else + { + DM_DBG1(("dmRegisterDevice: failed to allocate expander !!!\n")); + /* remember that the registration failed so that a discovery can't be started */ + onePortContext->RegFailed = agTRUE; + return DM_RC_FAILURE; + } + } + else + { + /* + the discovery has started. Alloc and add have been done. + find an expander using dmDeviceInfo, and update the expander's agDevHandle + call dmExpFind() + */ + DM_DBG3(("dmRegisterDevice: NOT DM_DSTATE_NOT_STARTED\n")); + sasAddressHi = DM_GET_SAS_ADDRESSHI(dmDeviceInfo->sasAddressHi); + sasAddressLo = DM_GET_SAS_ADDRESSLO(dmDeviceInfo->sasAddressLo); + DM_DBG3(("dmRegisterDevice: AddrHi 0x%08x AddrLo 0x%08x\n", sasAddressHi, sasAddressLo)); + oneExpander = dmExpFind(dmRoot, onePortContext, sasAddressHi, sasAddressLo); + if ( oneExpander != agNULL) + { + oneExpander->agDevHandle = agDevHandle; + } + else + { + DM_DBG1(("dmRegisterDevice: not allowed case, wrong !!!\n")); + return DM_RC_FAILURE; + } + } + + return DM_RC_SUCCESS; +} + +osGLOBAL dmExpander_t * +dmDiscoveringExpanderAlloc( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmDeviceData_t *oneDeviceData + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmExpander_t *oneExpander = agNULL; + dmList_t *ExpanderList; + + DM_DBG3(("dmDiscoveringExpanderAlloc: start\n")); + DM_DBG3(("dmDiscoveringExpanderAlloc: did %d\n", oneDeviceData->id)); + DM_DBG3(("dmDiscoveringExpanderAlloc: sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG3(("dmDiscoveringExpanderAlloc: sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + + if (onePortContext->valid == agFALSE) + { + DM_DBG1(("dmDiscoveringExpanderAlloc: invalid port!!!\n")); + return agNULL; + } + + + /* check exitence in dmAllShared->mainExpanderList */ + oneExpander = dmExpMainListFind(dmRoot, + onePortContext, + oneDeviceData->SASAddressID.sasAddressHi, + oneDeviceData->SASAddressID.sasAddressLo); + + if (oneExpander == agNULL) + { + tddmSingleThreadedEnter(dmRoot, DM_EXPANDER_LOCK); + if (DMLIST_EMPTY(&(dmAllShared->freeExpanderList))) + { + DM_DBG1(("dmDiscoveringExpanderAlloc: no free expanders pid %d!!!\n", onePortContext->id)); + tddmSingleThreadedLeave(dmRoot, DM_EXPANDER_LOCK); + return agNULL; + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_EXPANDER_LOCK); + } + + tddmSingleThreadedEnter(dmRoot, DM_EXPANDER_LOCK); + DMLIST_DEQUEUE_FROM_HEAD(&ExpanderList, &(dmAllShared->freeExpanderList)); + tddmSingleThreadedLeave(dmRoot, DM_EXPANDER_LOCK); + + oneExpander = DMLIST_OBJECT_BASE(dmExpander_t, linkNode, ExpanderList); + } + + if (oneExpander != agNULL) + { + DM_DBG1(("dmDiscoveringExpanderAlloc: pid %d exp id %d \n", onePortContext->id, oneExpander->id)); + + tddmSingleThreadedEnter(dmRoot, DM_EXPANDER_LOCK); + DMLIST_DEQUEUE_THIS(&(oneExpander->linkNode)); + tddmSingleThreadedLeave(dmRoot, DM_EXPANDER_LOCK); + + oneExpander->dmDevice = oneDeviceData; + oneExpander->dmUpStreamExpander = agNULL; + oneExpander->dmCurrentDownStreamExpander = agNULL; + oneExpander->dmReturnginExpander = agNULL; + oneExpander->hasUpStreamDevice = agFALSE; + oneExpander->numOfUpStreamPhys = 0; + oneExpander->currentUpStreamPhyIndex = 0; + oneExpander->discoveringPhyId = 0; + oneExpander->underDiscovering = agFALSE; + dm_memset( &(oneExpander->currentIndex), 0, sizeof(oneExpander->currentIndex)); + + oneDeviceData->dmExpander = oneExpander; + DM_DBG3(("dmDiscoveringExpanderAlloc: oneDeviceData %p did %d\n", oneDeviceData, oneDeviceData->id)); + DM_DBG3(("dmDiscoveringExpanderAlloc: oneExpander %p did %d\n", oneDeviceData->dmExpander, oneDeviceData->dmExpander->id)); + + } + + return oneExpander; +} + +osGLOBAL void +dmDiscoveringExpanderAdd( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmExpander_t *oneExpander + ) +{ + DM_DBG3(("dmDiscoveringExpanderAdd: start\n")); + DM_DBG3(("dmDiscoveringExpanderAdd: expander id %d\n", oneExpander->id)); + DM_DBG3(("dmDiscoveringExpanderAdd: exp addrHi 0x%08x\n", oneExpander->dmDevice->SASAddressID.sasAddressHi)); + DM_DBG3(("dmDiscoveringExpanderAdd: exp addrLo 0x%08x\n", oneExpander->dmDevice->SASAddressID.sasAddressLo)); + + if (onePortContext->valid == agFALSE) + { + DM_DBG1(("dmDiscoveringExpanderAdd: invalid port!!!\n")); + return; + } + if (onePortContext->discovery.status == DISCOVERY_UP_STREAM) + { + DM_DBG3(("dmDiscoveringExpanderAdd: UPSTREAM\n")); + } + else if (onePortContext->discovery.status == DISCOVERY_DOWN_STREAM) + { + DM_DBG3(("dmDiscoveringExpanderAdd: DOWNSTREAM\n")); + } + else + { + DM_DBG3(("dmDiscoveringExpanderAdd: status %d\n", onePortContext->discovery.status)); + } + + if ( oneExpander->underDiscovering == agFALSE) + { + DM_DBG3(("dmDiscoveringExpanderAdd: ADDED \n")); + + oneExpander->underDiscovering = agTRUE; + tddmSingleThreadedEnter(dmRoot, DM_EXPANDER_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(oneExpander->linkNode), &(onePortContext->discovery.discoveringExpanderList)); + tddmSingleThreadedLeave(dmRoot, DM_EXPANDER_LOCK); + } + + return; +} + +osGLOBAL dmExpander_t * +dmFindConfigurableExp( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmExpander_t *oneExpander + ) +{ + dmExpander_t *tempExpander; + dmIntPortContext_t *tmpOnePortContext = onePortContext; + dmExpander_t *ret = agNULL; + DM_DBG3(("dmFindConfigurableExp: start\n")); + + if (oneExpander == agNULL) + { + DM_DBG3(("dmFindConfigurableExp: NULL expander\n")); + return agNULL; + } + + DM_DBG3(("dmFindConfigurableExp: exp addrHi 0x%08x\n", oneExpander->dmDevice->SASAddressID.sasAddressHi)); + DM_DBG3(("dmFindConfigurableExp: exp addrLo 0x%08x\n", oneExpander->dmDevice->SASAddressID.sasAddressLo)); + + tddmSingleThreadedEnter(dmRoot, DM_EXPANDER_LOCK); + if (DMLIST_EMPTY(&(tmpOnePortContext->discovery.discoveringExpanderList))) + { + tddmSingleThreadedLeave(dmRoot, DM_EXPANDER_LOCK); + DM_DBG3(("dmFindConfigurableExp: empty UpdiscoveringExpanderList\n")); + return agNULL; + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_EXPANDER_LOCK); + } + tempExpander = oneExpander->dmUpStreamExpander; + while (tempExpander) + { + DM_DBG3(("dmFindConfigurableExp: loop exp addrHi 0x%08x\n", tempExpander->dmDevice->SASAddressID.sasAddressHi)); + DM_DBG3(("dmFindConfigurableExp: loop exp addrLo 0x%08x\n", tempExpander->dmDevice->SASAddressID.sasAddressLo)); + if (tempExpander->configRouteTable) + { + DM_DBG3(("dmFindConfigurableExp: found configurable expander\n")); + ret = tempExpander; + break; + } + tempExpander = tempExpander->dmUpStreamExpander; + } + + return ret; +} + +osGLOBAL bit32 +dmDuplicateConfigSASAddr( + dmRoot_t *dmRoot, + dmExpander_t *oneExpander, + bit32 configSASAddressHi, + bit32 configSASAddressLo + ) +{ + bit32 i; + bit32 ret = agFALSE; + DM_DBG3(("dmDuplicateConfigSASAddr: start\n")); + + if (oneExpander == agNULL) + { + DM_DBG3(("dmDuplicateConfigSASAddr: NULL expander\n")); + return agTRUE; + } + + if (oneExpander->dmDevice->SASAddressID.sasAddressHi == configSASAddressHi && + oneExpander->dmDevice->SASAddressID.sasAddressLo == configSASAddressLo + ) + { + DM_DBG3(("dmDuplicateConfigSASAddr: unnecessary\n")); + return agTRUE; + } + + DM_DBG3(("dmDuplicateConfigSASAddr: exp addrHi 0x%08x\n", oneExpander->dmDevice->SASAddressID.sasAddressHi)); + DM_DBG3(("dmDuplicateConfigSASAddr: exp addrLo 0x%08x\n", oneExpander->dmDevice->SASAddressID.sasAddressLo)); + DM_DBG3(("dmDuplicateConfigSASAddr: configsasAddressHi 0x%08x\n", configSASAddressHi)); + DM_DBG3(("dmDuplicateConfigSASAddr: configsasAddressLo 0x%08x\n", configSASAddressLo)); + DM_DBG3(("dmDuplicateConfigSASAddr: configSASAddrTableIndex %d\n", oneExpander->configSASAddrTableIndex)); + for(i=0;iconfigSASAddrTableIndex;i++) + { + if (oneExpander->configSASAddressHiTable[i] == configSASAddressHi && + oneExpander->configSASAddressLoTable[i] == configSASAddressLo + ) + { + DM_DBG3(("dmDuplicateConfigSASAddr: FOUND\n")); + ret = agTRUE; + break; + } + } + /* new one; let's add it */ + if (ret == agFALSE) + { + DM_DBG3(("dmDuplicateConfigSASAddr: adding configSAS Addr\n")); + DM_DBG3(("dmDuplicateConfigSASAddr: configSASAddrTableIndex %d\n", oneExpander->configSASAddrTableIndex)); + oneExpander->configSASAddressHiTable[oneExpander->configSASAddrTableIndex] = configSASAddressHi; + oneExpander->configSASAddressLoTable[oneExpander->configSASAddrTableIndex] = configSASAddressLo; + oneExpander->configSASAddrTableIndex++; + } + + return ret; +} + +osGLOBAL bit16 +dmFindCurrentDownStreamPhyIndex( + dmRoot_t *dmRoot, + dmExpander_t *oneExpander + ) +{ + dmExpander_t *DownStreamExpander; + bit16 index = 0; + bit16 i; + bit8 phyId = 0; + + DM_DBG3(("dmFindCurrentDownStreamPhyIndex: start\n")); + + if (oneExpander == agNULL) + { + DM_DBG1(("dmFindCurrentDownStreamPhyIndex: wrong, oneExpander is NULL!!!\n")); + return 0; + } + + DownStreamExpander = oneExpander->dmCurrentDownStreamExpander; + + if (DownStreamExpander == agNULL) + { + DM_DBG1(("dmFindCurrentDownStreamPhyIndex: wrong, DownStreamExpander is NULL!!!\n")); + return 0; + } + + DM_DBG3(("dmFindCurrentDownStreamPhyIndex: exp addrHi 0x%08x\n", oneExpander->dmDevice->SASAddressID.sasAddressHi)); + DM_DBG3(("dmFindCurrentDownStreamPhyIndex: exp addrLo 0x%08x\n", oneExpander->dmDevice->SASAddressID.sasAddressLo)); + DM_DBG3(("dmFindCurrentDownStreamPhyIndex: downstream exp addrHi 0x%08x\n", DownStreamExpander->dmDevice->SASAddressID.sasAddressHi)); + DM_DBG3(("dmFindCurrentDownStreamPhyIndex: downstream exp addrLo 0x%08x\n", DownStreamExpander->dmDevice->SASAddressID.sasAddressLo)); + DM_DBG3(("dmFindCurrentDownStreamPhyIndex: numOfDownStreamPhys %d\n", oneExpander->numOfDownStreamPhys)); + + phyId = DownStreamExpander->upStreamPhys[0]; + + DM_DBG3(("dmFindCurrentDownStreamPhyIndex: phyId %d\n", phyId)); + + for (i=0; inumOfDownStreamPhys;i++) + { + if (oneExpander->downStreamPhys[i] == phyId) + { + index = i; + break; + } + } + DM_DBG3(("dmFindCurrentDownStreamPhyIndex: index %d\n", index)); + return index; +} + +osGLOBAL bit32 +dmFindDiscoveringExpander( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmExpander_t *oneExpander + ) +{ + dmList_t *ExpanderList; + dmExpander_t *tempExpander; + dmIntPortContext_t *tmpOnePortContext = onePortContext; + bit32 ret = agFALSE; + + + DM_DBG3(("dmFindDiscoveringExpander: start\n")); + + DM_DBG3(("dmFindDiscoveringExpander: exp addrHi 0x%08x\n", oneExpander->dmDevice->SASAddressID.sasAddressHi)); + DM_DBG3(("dmFindDiscoveringExpander: exp addrLo 0x%08x\n", oneExpander->dmDevice->SASAddressID.sasAddressLo)); + + if (DMLIST_EMPTY(&(tmpOnePortContext->discovery.discoveringExpanderList))) + { + DM_DBG3(("dmFindDiscoveringExpander: empty discoveringExpanderList\n")); + return ret; + } + ExpanderList = tmpOnePortContext->discovery.discoveringExpanderList.flink; + while (ExpanderList != &(tmpOnePortContext->discovery.discoveringExpanderList)) + { + tempExpander = DMLIST_OBJECT_BASE(dmExpander_t, linkNode, ExpanderList); + if (tempExpander == oneExpander) + { + if (tempExpander != agNULL) + { + DM_DBG3(("dmFindDiscoveringExpander: match, expander id %d\n", tempExpander->id)); + DM_DBG3(("dmFindDiscoveringExpander: exp addrHi 0x%08x\n", tempExpander->dmDevice->SASAddressID.sasAddressHi)); + DM_DBG3(("dmFindDiscoveringExpander: exp addrLo 0x%08x\n", tempExpander->dmDevice->SASAddressID.sasAddressLo)); + } + ret = agTRUE; + break; + } + + ExpanderList = ExpanderList->flink; + } + + + return ret; +} + + +osGLOBAL void +dmDiscoveringExpanderRemove( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmExpander_t *oneExpander + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + + DM_DBG3(("dmDiscoveringExpanderRemove: start\n")); + DM_DBG3(("dmDiscoveringExpanderRemove: expander id %d\n", oneExpander->id)); + DM_DBG3(("dmDiscoveringExpanderRemove: exp addrHi 0x%08x\n", oneExpander->dmDevice->SASAddressID.sasAddressHi)); + DM_DBG3(("dmDiscoveringExpanderRemove: exp addrLo 0x%08x\n", oneExpander->dmDevice->SASAddressID.sasAddressLo)); + + DM_DBG3(("dmDiscoveringExpanderRemove: BEFORE\n")); + dmDumpAllExp(dmRoot, onePortContext, oneExpander); + dmDumpAllUpExp(dmRoot, onePortContext, oneExpander); + dmDumpAllFreeExp(dmRoot); + + // if is temporary till smp problem is fixed + if (dmFindDiscoveringExpander(dmRoot, onePortContext, oneExpander) == agTRUE) + { + DM_DBG3(("dmDiscoveringExpanderRemove: oneDeviceData %p did %d\n", oneExpander->dmDevice, oneExpander->dmDevice->id)); + DM_DBG3(("dmDiscoveringExpanderRemove: oneExpander %p did %d\n", oneExpander, oneExpander->id)); + + if (oneExpander != oneExpander->dmDevice->dmExpander) + { + DM_DBG3(("dmDiscoveringExpanderRemove: before !!! wrong !!!\n")); + } + oneExpander->underDiscovering = agFALSE; + oneExpander->discoveringPhyId = 0; + tddmSingleThreadedEnter(dmRoot, DM_EXPANDER_LOCK); + DMLIST_DEQUEUE_THIS(&(oneExpander->linkNode)); + tddmSingleThreadedLeave(dmRoot, DM_EXPANDER_LOCK); + + if (onePortContext->discovery.status == DISCOVERY_UP_STREAM) + { + DM_DBG3(("dmDiscoveringExpanderRemove: DISCOVERY_UP_STREAM\n")); + tddmSingleThreadedEnter(dmRoot, DM_EXPANDER_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(oneExpander->upNode), &(onePortContext->discovery.UpdiscoveringExpanderList)); + tddmSingleThreadedLeave(dmRoot, DM_EXPANDER_LOCK); + onePortContext->discovery.NumOfUpExp++; + } + else + { + DM_DBG3(("dmDiscoveringExpanderRemove: Status %d\n", onePortContext->discovery.status)); + tddmSingleThreadedEnter(dmRoot, DM_EXPANDER_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(oneExpander->linkNode), &(dmAllShared->mainExpanderList)); +// DMLIST_ENQUEUE_AT_TAIL(&(oneExpander->linkNode), &(dmAllShared->freeExpanderList)); + tddmSingleThreadedLeave(dmRoot, DM_EXPANDER_LOCK); + } + // error checking + if (oneExpander != oneExpander->dmDevice->dmExpander) + { + DM_DBG3(("dmDiscoveringExpanderRemove: after !!! wrong !!!\n")); + } + + } //end temp if + else + { + DM_DBG1(("dmDiscoveringExpanderRemove: !!! problem !!!\n")); + } + + DM_DBG3(("dmDiscoveringExpanderRemove: AFTER\n")); + + dmDumpAllExp(dmRoot, onePortContext, oneExpander); + dmDumpAllUpExp(dmRoot, onePortContext, oneExpander); + dmDumpAllFreeExp(dmRoot); + + return; +} + +/* + returns an expander with sasAddrLo, sasAddrHi from dmAllShared->mainExpanderList +*/ +osGLOBAL dmExpander_t * +dmExpMainListFind( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + bit32 sasAddrHi, + bit32 sasAddrLo + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmList_t *ExpanderList; + dmExpander_t *tempExpander; + + DM_DBG3(("dmExpMainListFind: start\n")); + + tddmSingleThreadedEnter(dmRoot, DM_EXPANDER_LOCK); + if (DMLIST_EMPTY(&(dmAllShared->mainExpanderList))) + { + DM_DBG1(("dmExpMainListFind: empty mainExpanderList\n")); + tddmSingleThreadedLeave(dmRoot, DM_EXPANDER_LOCK); + return agNULL; + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_EXPANDER_LOCK); + } + ExpanderList = dmAllShared->mainExpanderList.flink; + while (ExpanderList != &(dmAllShared->mainExpanderList)) + { + tempExpander = DMLIST_OBJECT_BASE(dmExpander_t, linkNode, ExpanderList); + if (tempExpander == agNULL) + { + DM_DBG1(("dmExpMainListFind: tempExpander is NULL!!!\n")); + return agNULL; + } + DM_DBG3(("dmExpMainListFind: expander id %d\n", tempExpander->id)); + DM_DBG3(("dmExpMainListFind: exp addrHi 0x%08x\n", tempExpander->dmDevice->SASAddressID.sasAddressHi)); + DM_DBG3(("dmExpMainListFind: exp addrLo 0x%08x\n", tempExpander->dmDevice->SASAddressID.sasAddressLo)); + if ((tempExpander->dmDevice->SASAddressID.sasAddressHi == sasAddrHi) && + (tempExpander->dmDevice->SASAddressID.sasAddressLo == sasAddrLo) && + (tempExpander->dmDevice->dmPortContext == onePortContext) + ) + { + DM_DBG3(("dmExpMainListFind: found expander id %d\n", tempExpander->id)); + DM_DBG3(("dmExpMainListFind: found exp addrHi 0x%08x\n", tempExpander->dmDevice->SASAddressID.sasAddressHi)); + DM_DBG3(("dmExpMainListFind: found exp addrLo 0x%08x\n", tempExpander->dmDevice->SASAddressID.sasAddressLo)); + return tempExpander; + } + ExpanderList = ExpanderList->flink; + } + return agNULL; + +} + +/* + returns an expander with sasAddrLo, sasAddrHi from discoveringExpanderList +*/ +osGLOBAL dmExpander_t * +dmExpFind( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + bit32 sasAddrHi, + bit32 sasAddrLo + ) +{ + dmList_t *ExpanderList; + dmExpander_t *tempExpander; + dmIntPortContext_t *tmpOnePortContext = onePortContext; + DM_DBG3(("dmExpFind: start\n")); + + tddmSingleThreadedEnter(dmRoot, DM_EXPANDER_LOCK); + if (DMLIST_EMPTY(&(tmpOnePortContext->discovery.discoveringExpanderList))) + { + DM_DBG3(("dmExpFind tdsaDumpAllExp: empty discoveringExpanderList\n")); + tddmSingleThreadedLeave(dmRoot, DM_EXPANDER_LOCK); + return agNULL; + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_EXPANDER_LOCK); + } + ExpanderList = tmpOnePortContext->discovery.discoveringExpanderList.flink; + while (ExpanderList != &(tmpOnePortContext->discovery.discoveringExpanderList)) + { + tempExpander = DMLIST_OBJECT_BASE(dmExpander_t, linkNode, ExpanderList); + if (tempExpander == agNULL) + { + DM_DBG1(("dmExpFind: tempExpander is NULL!!!\n")); + return agNULL; + } + DM_DBG3(("dmExpFind: expander id %d\n", tempExpander->id)); + DM_DBG3(("dmExpFind: exp addrHi 0x%08x\n", tempExpander->dmDevice->SASAddressID.sasAddressHi)); + DM_DBG3(("dmExpFind: exp addrLo 0x%08x\n", tempExpander->dmDevice->SASAddressID.sasAddressLo)); + if ((tempExpander->dmDevice->SASAddressID.sasAddressHi == sasAddrHi) && + (tempExpander->dmDevice->SASAddressID.sasAddressLo == sasAddrLo) && + (tempExpander->dmDevice->dmPortContext == onePortContext) + ) + { + DM_DBG3(("dmExpFind: found\n")); + return tempExpander; + } + ExpanderList = ExpanderList->flink; + } + return agNULL; +} + +osGLOBAL bit32 +dmDiscoverCheck( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ) +{ + DM_DBG3(("dmDiscoverCheck: start\n")); + + if (onePortContext == agNULL) + { + DM_DBG1(("dmDiscoverCheck: onePortContext is NULL!!!\n")); + return agTRUE; + } + if (onePortContext->valid == agFALSE) + { + DM_DBG1(("dmDiscoverCheck: invalid port!!!\n")); + return agTRUE; + } + if (onePortContext->DiscoveryState == DM_DSTATE_COMPLETED || + onePortContext->discovery.status == DISCOVERY_SAS_DONE + ) + { + DM_DBG1(("dmDiscoverCheck: aborted discovery!!!\n")); + tddmDiscoverCB( + dmRoot, + onePortContext->dmPortContext, + dmDiscAborted + ); + return agTRUE; + } + + return agFALSE; +} + +/* ??? needs to handle pending SMPs + move from dmAllShared->discoveringExpanderList to dmAllShared->mainExpanderList +*/ +osGLOBAL void +dmDiscoverAbort( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ) +{ + DM_DBG1(("dmDiscoverAbort: start\n")); + + if (onePortContext->DiscoveryState == DM_DSTATE_COMPLETED || + onePortContext->discovery.status == DISCOVERY_SAS_DONE) + { + DM_DBG1(("dmDiscoverAbort: not allowed case!!! onePortContext->DiscoveryState 0x%x onePortContext->discovery.status 0x%x\n", + onePortContext->DiscoveryState, onePortContext->discovery.status)); + return; + } + + onePortContext->DiscoveryState = DM_DSTATE_COMPLETED; + onePortContext->discovery.status = DISCOVERY_SAS_DONE; + + /* move from dmAllShared->discoveringExpanderList to dmAllShared->mainExpanderList */ + dmCleanAllExp(dmRoot, onePortContext); + + + return; + + +} + +/* move from dmAllShared->discoveringExpanderList to dmAllShared->mainExpanderList */ +osGLOBAL void +dmCleanAllExp( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmList_t *ExpanderList; + dmExpander_t *tempExpander; + dmExpander_t *oneExpander = agNULL; + dmIntPortContext_t *tmpOnePortContext = onePortContext; + + DM_DBG3(("dmCleanAllExp: start\n")); + DM_DBG3(("dmCleanAllExp: pid %d\n", onePortContext->id)); + + DM_DBG3(("dmCleanAllExp: before all clean up\n")); + dmDumpAllFreeExp(dmRoot); + + /* clean up UpdiscoveringExpanderList*/ + DM_DBG3(("dmCleanAllExp: clean discoveringExpanderList\n")); + if (!DMLIST_EMPTY(&(tmpOnePortContext->discovery.discoveringExpanderList))) + { + ExpanderList = tmpOnePortContext->discovery.discoveringExpanderList.flink; + while (ExpanderList != &(tmpOnePortContext->discovery.discoveringExpanderList)) + { + tempExpander = DMLIST_OBJECT_BASE(dmExpander_t, linkNode, ExpanderList); + if (tempExpander == agNULL) + { + DM_DBG1(("dmCleanAllExp: tempExpander is NULL!!!\n")); + return; + } + DM_DBG3(("dmCleanAllExp: exp addrHi 0x%08x\n", tempExpander->dmDevice->SASAddressID.sasAddressHi)); + DM_DBG3(("dmCleanAllExp: exp addrLo 0x%08x\n", tempExpander->dmDevice->SASAddressID.sasAddressLo)); + DM_DBG3(("dmCleanAllExp: exp id %d\n", tempExpander->id)); + + oneExpander = dmExpMainListFind(dmRoot, + tmpOnePortContext, + tempExpander->dmDevice->SASAddressID.sasAddressHi, + tempExpander->dmDevice->SASAddressID.sasAddressLo); + if (oneExpander == agNULL) + { + DM_DBG3(("dmCleanAllExp: moving\n")); + DM_DBG3(("dmCleanAllExp: moving, exp id %d\n", tempExpander->id)); + /* putting back to the free pool */ + tddmSingleThreadedEnter(dmRoot, DM_EXPANDER_LOCK); + DMLIST_DEQUEUE_THIS(&(tempExpander->linkNode)); +// DMLIST_ENQUEUE_AT_TAIL(&(tempExpander->linkNode), &(dmAllShared->freeExpanderList)); + DMLIST_ENQUEUE_AT_TAIL(&(tempExpander->linkNode), &(dmAllShared->mainExpanderList)); + + if (DMLIST_EMPTY(&(tmpOnePortContext->discovery.discoveringExpanderList))) + { + tddmSingleThreadedLeave(dmRoot, DM_EXPANDER_LOCK); + break; + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_EXPANDER_LOCK); + } + ExpanderList = tmpOnePortContext->discovery.discoveringExpanderList.flink; + } + else + { + DM_DBG3(("dmCleanAllExp: in mainExpanderList; skippig\n")); + ExpanderList = ExpanderList->flink; + } + } + } + else + { + DM_DBG3(("dmCleanAllExp: empty discoveringExpanderList\n")); + } + + /* reset discoveringExpanderList */ + DMLIST_INIT_HDR(&(tmpOnePortContext->discovery.discoveringExpanderList)); + + /* clean up UpdiscoveringExpanderList*/ + DM_DBG3(("dmCleanAllExp: clean UpdiscoveringExpanderList\n")); + if (DMLIST_EMPTY(&(tmpOnePortContext->discovery.UpdiscoveringExpanderList))) + { + DM_DBG3(("dmCleanAllExp: empty UpdiscoveringExpanderList\n")); + return; + } + ExpanderList = tmpOnePortContext->discovery.UpdiscoveringExpanderList.flink; + while (ExpanderList != &(tmpOnePortContext->discovery.UpdiscoveringExpanderList)) + { + tempExpander = DMLIST_OBJECT_BASE(dmExpander_t, upNode, ExpanderList); + if (tempExpander == agNULL) + { + DM_DBG1(("dmCleanAllExp: tempExpander is NULL!!!\n")); + return; + } + DM_DBG3(("dmCleanAllExp: exp addrHi 0x%08x\n", tempExpander->dmDevice->SASAddressID.sasAddressHi)); + DM_DBG3(("dmCleanAllExp: exp addrLo 0x%08x\n", tempExpander->dmDevice->SASAddressID.sasAddressLo)); + DM_DBG3(("dmCleanAllExp: exp id %d\n", tempExpander->id)); + oneExpander = dmExpMainListFind(dmRoot, + tmpOnePortContext, + tempExpander->dmDevice->SASAddressID.sasAddressHi, + tempExpander->dmDevice->SASAddressID.sasAddressLo); + if (oneExpander == agNULL) + { + DM_DBG3(("dmCleanAllExp: moving\n")); + DM_DBG3(("dmCleanAllExp: moving exp id %d\n", tempExpander->id)); + tddmSingleThreadedEnter(dmRoot, DM_EXPANDER_LOCK); + DMLIST_DEQUEUE_THIS(&(tempExpander->upNode)); + DMLIST_ENQUEUE_AT_TAIL(&(tempExpander->linkNode), &(dmAllShared->mainExpanderList)); + + if (DMLIST_EMPTY(&(tmpOnePortContext->discovery.UpdiscoveringExpanderList))) + { + tddmSingleThreadedLeave(dmRoot, DM_EXPANDER_LOCK); + break; + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_EXPANDER_LOCK); + } + ExpanderList = tmpOnePortContext->discovery.UpdiscoveringExpanderList.flink; + } + else + { + DM_DBG3(("dmCleanAllExp: in mainExpanderList; skippig\n")); + ExpanderList = ExpanderList->flink; + } + } + + /* reset UpdiscoveringExpanderList */ + DMLIST_INIT_HDR(&(tmpOnePortContext->discovery.UpdiscoveringExpanderList)); + + DM_DBG3(("dmCleanAllExp: after all clean up\n")); + dmDumpAllFreeExp(dmRoot); + + return; +} + +osGLOBAL void +dmInternalRemovals( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmDeviceData_t *oneDeviceData = agNULL; + dmList_t *DeviceListList; + + + DM_DBG3(("dmInternalRemovals: start\n")); + tddmSingleThreadedEnter(dmRoot, DM_DEVICE_LOCK); + if (DMLIST_EMPTY(&(dmAllShared->MainDeviceList))) + { + tddmSingleThreadedLeave(dmRoot, DM_DEVICE_LOCK); + DM_DBG3(("dmInternalRemovals: empty device list\n")); + return; + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_DEVICE_LOCK); + } + + DeviceListList = dmAllShared->MainDeviceList.flink; + while (DeviceListList != &(dmAllShared->MainDeviceList)) + { + oneDeviceData = DMLIST_OBJECT_BASE(dmDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + DM_DBG1(("dmInternalRemovals: oneDeviceData is NULL!!!\n")); + return; + } + DM_DBG3(("dmInternalRemovals: loop did %d\n", oneDeviceData->id)); + DM_DBG3(("dmInternalRemovals: sasAddrHi 0x%08x \n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG3(("dmInternalRemovals: sasAddrLo 0x%08x \n", oneDeviceData->SASAddressID.sasAddressLo)); + DM_DBG3(("dmInternalRemovals: valid %d\n", oneDeviceData->valid)); + DM_DBG3(("dmInternalRemovals: valid2 %d\n", oneDeviceData->valid2)); + DM_DBG3(("dmInternalRemovals: directlyAttached %d\n", oneDeviceData->directlyAttached)); + if ( oneDeviceData->dmPortContext == onePortContext) + { + DM_DBG3(("dmInternalRemovals: right portcontext pid %d\n", onePortContext->id)); + if (onePortContext->discovery.type == DM_DISCOVERY_OPTION_INCREMENTAL_START) + { + DM_DBG3(("dmInternalRemovals: incremental discovery\n")); + oneDeviceData->valid2 = agFALSE; + } + else + { + DM_DBG3(("dmInternalRemovals: full discovery\n")); + oneDeviceData->valid = agFALSE; + } + DeviceListList = DeviceListList->flink; + } + else + { + if (oneDeviceData->dmPortContext != agNULL) + { + DM_DBG3(("dmInternalRemovals: different portcontext; oneDeviceData->dmPortContext pid %d oneportcontext pid %d\n", oneDeviceData->dmPortContext->id, onePortContext->id)); + } + else + { + DM_DBG3(("dmInternalRemovals: different portcontext; oneDeviceData->dmPortContext pid NULL oneportcontext pid %d\n", onePortContext->id)); + } + DeviceListList = DeviceListList->flink; + } + } + + + return; +} + +osGLOBAL void +dmDiscoveryResetProcessed( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmDeviceData_t *oneDeviceData = agNULL; + dmList_t *DeviceListList; + + DM_DBG3(("dmDiscoveryResetProcessed: start\n")); + + /* reinitialize the device data belonging to this portcontext */ + DeviceListList = dmAllShared->MainDeviceList.flink; + while (DeviceListList != &(dmAllShared->MainDeviceList)) + { + oneDeviceData = DMLIST_OBJECT_BASE(dmDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + DM_DBG1(("dmDiscoveryResetProcessed: oneDeviceData is NULL!!!\n")); + return; + } + DM_DBG3(("dmDiscoveryResetProcessed: loop did %d\n", oneDeviceData->id)); + if (oneDeviceData->dmPortContext == onePortContext) + { + DM_DBG3(("dmDiscoveryResetProcessed: resetting procssed flag\n")); + oneDeviceData->processed = agFALSE; + } + DeviceListList = DeviceListList->flink; + } + + return; +} + +/* + calls +osGLOBAL void +tddmDiscoverCB( + dmRoot_t *dmRoot, + dmPortContext_t *dmPortContext, + bit32 eventStatus + ) + +*/ +osGLOBAL void +dmDiscoverDone( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + bit32 flag + ) +{ + + DM_DBG3(("dmDiscoverDone: start\n")); + DM_DBG3(("dmDiscoverDone: pid %d\n", onePortContext->id)); + + /* Set discovery status */ + onePortContext->discovery.status = DISCOVERY_SAS_DONE; + + + /* clean up expanders data strucures; move to free exp when device is cleaned */ + dmCleanAllExp(dmRoot, onePortContext); + + dmDumpAllMainExp(dmRoot, onePortContext); + + dmDiscoveryResetProcessed(dmRoot, onePortContext); + + dmDiscoveryDumpMCN(dmRoot, onePortContext); + + if (onePortContext->discovery.SeenBC == agTRUE) + { + DM_DBG3(("dmDiscoverDone: broadcast change; discover again\n")); + dmDiscoveryResetMCN(dmRoot, onePortContext); + + dmInternalRemovals(dmRoot, onePortContext); + + /* processed broadcast change */ + onePortContext->discovery.SeenBC = agFALSE; + if (onePortContext->discovery.ResetTriggerred == agTRUE) + { + DM_DBG3(("dmDiscoverDone: dmBCTimer\n")); + dmBCTimer(dmRoot, onePortContext); + } + else + { + + dmIncrementalDiscover(dmRoot, onePortContext, agTRUE); + } + } + else + { + onePortContext->DiscoveryState = DM_DSTATE_COMPLETED; + + if (onePortContext->discovery.type == DM_DISCOVERY_OPTION_FULL_START) + { + if (flag == DM_RC_SUCCESS) + { + + dmResetReported(dmRoot, + onePortContext + ); + + dmDiscoveryReportMCN(dmRoot, + onePortContext + ); + + + /* call tddmDiscoverCB() */ + tddmDiscoverCB( + dmRoot, + onePortContext->dmPortContext, + dmDiscCompleted + ); + } + else if (flag != DM_RC_SUCCESS || onePortContext->discovery.DeferredError == agTRUE) + { + onePortContext->DiscoveryState = DM_DSTATE_COMPLETED_WITH_FAILURE; + DM_DBG1(("dmDiscoverDone: Error; clean up!!!\n")); + + dmDiscoveryInvalidateDevices(dmRoot, + onePortContext + ); + + tddmDiscoverCB( + dmRoot, + onePortContext->dmPortContext, + dmDiscFailed + ); + } + } + else + { + if (flag == DM_RC_SUCCESS) + { + dmReportChanges(dmRoot, + onePortContext + ); + dmDiscoveryReportMCN(dmRoot, + onePortContext + ); + tddmDiscoverCB( + dmRoot, + onePortContext->dmPortContext, + dmDiscCompleted + ); + } + else if (flag != DM_RC_SUCCESS || onePortContext->discovery.DeferredError == agTRUE) + { + onePortContext->DiscoveryState = DM_DSTATE_COMPLETED_WITH_FAILURE; + dmDiscoveryInvalidateDevices(dmRoot, + onePortContext + ); + + tddmDiscoverCB( + dmRoot, + onePortContext->dmPortContext, + dmDiscFailed + ); + } + } + } + return; +} + +/* called by dmDiscoveryErrorRemovals() or dmReportRemovals() on discovery failure */ +osGLOBAL void +dmSubReportRemovals( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmDeviceData_t *oneDeviceData, + bit32 flag + ) +{ + dmDeviceData_t *oneAttachedExpDeviceData = agNULL; + DM_DBG3(("dmSubReportRemovals: start\n")); + + DM_DBG3(("dmSubReportRemovals: flag 0x%x\n", flag)); + if (flag == dmDeviceRemoval) + { + oneDeviceData->registered = agFALSE; + } + + if (oneDeviceData->ExpDevice != agNULL) + { + DM_DBG3(("dmSubReportRemovals: attached expander case\n")); + oneAttachedExpDeviceData = oneDeviceData->ExpDevice; + tddmReportDevice(dmRoot, onePortContext->dmPortContext, &oneDeviceData->dmDeviceInfo, &oneAttachedExpDeviceData->dmDeviceInfo, flag); + } + else + { + DM_DBG3(("dmSubReportRemovals: NO attached expander case\n")); + tddmReportDevice(dmRoot, onePortContext->dmPortContext, &oneDeviceData->dmDeviceInfo, agNULL, flag); + } + + + /* this function is called at the end of discovery; reinitalizes oneDeviceData->reported */ + oneDeviceData->reported = agFALSE; + return; +} + + +/* called by dmReportChanges() on discovery success */ +osGLOBAL void +dmSubReportChanges( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmDeviceData_t *oneDeviceData, + bit32 flag + ) +{ + dmDeviceData_t *oneAttachedExpDeviceData = agNULL; + DM_DBG3(("dmSubReportChanges: start\n")); + + DM_DBG3(("dmSubReportChanges: flag 0x%x\n", flag)); + if (flag == dmDeviceRemoval) + { + oneDeviceData->registered = agFALSE; + } + if (oneDeviceData->reported == agFALSE) + { + if (oneDeviceData->ExpDevice != agNULL) + { + DM_DBG3(("dmSubReportChanges: attached expander case\n")); + oneAttachedExpDeviceData = oneDeviceData->ExpDevice; + tddmReportDevice(dmRoot, onePortContext->dmPortContext, &oneDeviceData->dmDeviceInfo, &oneAttachedExpDeviceData->dmDeviceInfo, flag); + } + else + { + DM_DBG3(("dmSubReportChanges: NO attached expander case\n")); + tddmReportDevice(dmRoot, onePortContext->dmPortContext, &oneDeviceData->dmDeviceInfo, agNULL, flag); + } + } + else + { + DM_DBG3(("dmSubReportChanges: skip; been reported\n")); + } + + + /* this function is called at the end of discovery; reinitalizes oneDeviceData->reported */ + oneDeviceData->reported = agFALSE; + return; +} + +/* + should add or remove be reported per device??? +*/ +osGLOBAL void +dmReportChanges( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmDeviceData_t *oneDeviceData = agNULL; + dmList_t *DeviceListList; + bit32 added = agFALSE, removed = agFALSE; +// dmDeviceData_t *oneAttachedExpDeviceData = agNULL; + + DM_DBG3(("dmReportChanges: start\n")); + + tddmSingleThreadedEnter(dmRoot, DM_DEVICE_LOCK); + if (DMLIST_EMPTY(&(dmAllShared->MainDeviceList))) + { + tddmSingleThreadedLeave(dmRoot, DM_DEVICE_LOCK); + DM_DBG3(("dmReportChanges: empty device list\n")); + return; + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_DEVICE_LOCK); + } + + DeviceListList = dmAllShared->MainDeviceList.flink; + while (DeviceListList != &(dmAllShared->MainDeviceList)) + { + oneDeviceData = DMLIST_OBJECT_BASE(dmDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + DM_DBG1(("dmReportChanges: oneDeviceData is NULL!!!\n")); + return; + } + DM_DBG3(("dmReportChanges: sasAddrHi 0x%08x \n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG3(("dmReportChanges: sasAddrLo 0x%08x \n", oneDeviceData->SASAddressID.sasAddressLo)); + if ( oneDeviceData->dmPortContext == onePortContext) + { + DM_DBG3(("dmReportChanges: right portcontext\n")); + if (oneDeviceData->SASAddressID.sasAddressHi == onePortContext->sasRemoteAddressHi && + oneDeviceData->SASAddressID.sasAddressLo == onePortContext->sasRemoteAddressLo + ) + { + DM_DBG1(("dmReportChanges: keep, not reporting did 0x%x\n", oneDeviceData->id)); + oneDeviceData->valid = agTRUE; + oneDeviceData->valid2 = agFALSE; + } + else if ( (oneDeviceData->valid == agTRUE) && (oneDeviceData->valid2 == agTRUE) ) + { + DM_DBG3(("dmReportChanges: same\n")); + /* reset valid bit */ + oneDeviceData->valid = oneDeviceData->valid2; + oneDeviceData->valid2 = agFALSE; + dmSubReportChanges(dmRoot, onePortContext, oneDeviceData, dmDeviceNoChange); + } + else if ( (oneDeviceData->valid == agTRUE) && (oneDeviceData->valid2 == agFALSE) ) + { + DM_DBG3(("dmReportChanges: removed\n")); + removed = agTRUE; + /* reset valid bit */ + oneDeviceData->valid = oneDeviceData->valid2; + oneDeviceData->valid2 = agFALSE; + + onePortContext->RegisteredDevNums--; + dmSubReportChanges(dmRoot, onePortContext, oneDeviceData, dmDeviceRemoval); + } + else if ( (oneDeviceData->valid == agFALSE) && (oneDeviceData->valid2 == agTRUE) ) + { + DM_DBG3(("dmReportChanges: added\n")); + added = agTRUE; + /* reset valid bit */ + oneDeviceData->valid = oneDeviceData->valid2; + oneDeviceData->valid2 = agFALSE; + dmSubReportChanges(dmRoot, onePortContext, oneDeviceData, dmDeviceArrival); + } + else + { + DM_DBG3(("dmReportChanges: else\n")); + } + } + else + { + DM_DBG3(("dmReportChanges: different portcontext\n")); + } + DeviceListList = DeviceListList->flink; + } + /* + osGLOBAL void +tddmReportDevice( + dmRoot_t *dmRoot, + dmPortContext_t *dmPortContext, + dmDeviceInfo_t *dmDeviceInfo, + dmDeviceInfo_t *dmExpDeviceInfo, + bit32 flag + + ) + + */ + + /* arrival or removal at once */ + if (added == agTRUE) + { + DM_DBG3(("dmReportChanges: added at the end\n")); +#if 0 /* TBD */ + ostiInitiatorEvent( + tiRoot, + onePortContext->tiPortalContext, + agNULL, + tiIntrEventTypeDeviceChange, + tiDeviceArrival, + agNULL + ); +#endif + + } + if (removed == agTRUE) + { + DM_DBG3(("dmReportChanges: removed at the end\n")); +#if 0 /* TBD */ + ostiInitiatorEvent( + tiRoot, + onePortContext->tiPortalContext, + agNULL, + tiIntrEventTypeDeviceChange, + tiDeviceRemoval, + agNULL + ); +#endif + } + + if (onePortContext->discovery.forcedOK == agTRUE && added == agFALSE && removed == agFALSE) + { + DM_DBG3(("dmReportChanges: missed chance to report. forced to report OK\n")); + onePortContext->discovery.forcedOK = agFALSE; +#if 0 /* TBD */ + ostiInitiatorEvent( + tiRoot, + onePortContext->tiPortalContext, + agNULL, + tiIntrEventTypeDiscovery, + tiDiscOK, + agNULL + ); +#endif + } + + if (added == agFALSE && removed == agFALSE) + { + DM_DBG3(("dmReportChanges: the same\n")); + } + + return; +} + +osGLOBAL void +dmReportRemovals( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + bit32 flag + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmDeviceData_t *oneDeviceData = agNULL; + dmList_t *DeviceListList; + bit32 removed = agFALSE; + + DM_DBG1(("dmReportRemovals: start\n")); + + tddmSingleThreadedEnter(dmRoot, DM_DEVICE_LOCK); + if (DMLIST_EMPTY(&(dmAllShared->MainDeviceList))) + { + tddmSingleThreadedLeave(dmRoot, DM_DEVICE_LOCK); + DM_DBG3(("dmReportRemovals: empty device list\n")); + return; + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_DEVICE_LOCK); + } + + DeviceListList = dmAllShared->MainDeviceList.flink; + while (DeviceListList != &(dmAllShared->MainDeviceList)) + { + oneDeviceData = DMLIST_OBJECT_BASE(dmDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + DM_DBG1(("dmReportRemovals: oneDeviceData is NULL!!!\n")); + return; + } + DM_DBG3(("dmReportRemovals: loop did %d\n", oneDeviceData->id)); + DM_DBG3(("dmReportRemovals: sasAddrHi 0x%08x \n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG3(("dmReportRemovals: sasAddrLo 0x%08x \n", oneDeviceData->SASAddressID.sasAddressLo)); + DM_DBG3(("dmReportRemovals: valid %d\n", oneDeviceData->valid)); + DM_DBG3(("dmReportRemovals: valid2 %d\n", oneDeviceData->valid2)); + DM_DBG3(("dmReportRemovals: directlyAttached %d\n", oneDeviceData->directlyAttached)); + if ( oneDeviceData->dmPortContext == onePortContext) + { + DM_DBG3(("dmReportRemovals: right portcontext pid %d\n", onePortContext->id)); + if (oneDeviceData->SASAddressID.sasAddressHi == onePortContext->sasRemoteAddressHi && + oneDeviceData->SASAddressID.sasAddressLo == onePortContext->sasRemoteAddressLo + ) + { + DM_DBG1(("dmReportRemovals: keeping\n")); + oneDeviceData->valid = agTRUE; + oneDeviceData->valid2 = agFALSE; + } + else if (oneDeviceData->valid == agTRUE) + { + DM_DBG3(("dmReportRemovals: removing\n")); + + /* notify only reported devices to OS layer*/ + if ( DEVICE_IS_SSP_TARGET(oneDeviceData) || + DEVICE_IS_STP_TARGET(oneDeviceData) || + DEVICE_IS_SATA_DEVICE(oneDeviceData) + ) + { + removed = agTRUE; + } + + /* all targets except expanders */ + DM_DBG3(("dmReportRemovals: did %d\n", oneDeviceData->id)); + DM_DBG3(("dmReportRemovals: sasAddrHi 0x%08x \n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG3(("dmReportRemovals: sasAddrLo 0x%08x \n", oneDeviceData->SASAddressID.sasAddressLo)); + onePortContext->RegisteredDevNums--; + dmSubReportRemovals(dmRoot, onePortContext, oneDeviceData, dmDeviceRemoval); + + + /* reset valid bit */ + oneDeviceData->valid = agFALSE; + oneDeviceData->valid2 = agFALSE; + + + } + /* called by port invalid case */ + if (flag == agTRUE) + { + oneDeviceData->dmPortContext = agNULL; + } + DeviceListList = DeviceListList->flink; + } + else + { + if (oneDeviceData->dmPortContext != agNULL) + { + DM_DBG3(("dmReportRemovals: different portcontext; oneDeviceData->dmPortContext pid %d oneportcontext pid %d\n", oneDeviceData->dmPortContext->id, onePortContext->id)); + } + else + { + DM_DBG3(("dmReportRemovals: different portcontext; oneDeviceData->dmPortContext pid NULL oneportcontext pid %d\n", onePortContext->id)); + } + DeviceListList = DeviceListList->flink; + } + } + + if (removed == agTRUE) + { + DM_DBG3(("dmReportRemovals: removed at the end\n")); +#if 0 /* TBD */ + ostiInitiatorEvent( + tiRoot, + onePortContext->tiPortalContext, + agNULL, + tiIntrEventTypeDeviceChange, + tiDeviceRemoval, + agNULL + ); +#endif + } + + return; +} + +osGLOBAL void +dmResetReported( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmDeviceData_t *oneDeviceData = agNULL; + dmList_t *DeviceListList; + + DM_DBG3(("dmResetReported: start\n")); + + tddmSingleThreadedEnter(dmRoot, DM_DEVICE_LOCK); + if (DMLIST_EMPTY(&(dmAllShared->MainDeviceList))) + { + tddmSingleThreadedLeave(dmRoot, DM_DEVICE_LOCK); + DM_DBG3(("dmResetReported: empty device list\n")); + return; + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_DEVICE_LOCK); + } + + DeviceListList = dmAllShared->MainDeviceList.flink; + while (DeviceListList != &(dmAllShared->MainDeviceList)) + { + oneDeviceData = DMLIST_OBJECT_BASE(dmDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + DM_DBG1(("dmResetReported: oneDeviceData is NULL!!!\n")); + return; + } + DM_DBG3(("dmResetReported: loop did %d\n", oneDeviceData->id)); + DM_DBG3(("dmResetReported: sasAddrHi 0x%08x \n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG3(("dmResetReported: sasAddrLo 0x%08x \n", oneDeviceData->SASAddressID.sasAddressLo)); + DM_DBG3(("dmResetReported: valid %d\n", oneDeviceData->valid)); + DM_DBG3(("dmResetReported: valid2 %d\n", oneDeviceData->valid2)); + DM_DBG3(("dmResetReported: directlyAttached %d\n", oneDeviceData->directlyAttached)); + if ( oneDeviceData->dmPortContext == onePortContext) + { + DM_DBG3(("dmResetReported: right portcontext pid %d\n", onePortContext->id)); + oneDeviceData->reported = agFALSE; + DeviceListList = DeviceListList->flink; + } + else + { + if (oneDeviceData->dmPortContext != agNULL) + { + DM_DBG3(("dmResetReported: different portcontext; oneDeviceData->dmPortContext pid %d oneportcontext pid %d\n", oneDeviceData->dmPortContext->id, onePortContext->id)); + } + else + { + DM_DBG3(("dmResetReported: different portcontext; oneDeviceData->dmPortContext pid NULL oneportcontext pid %d\n", onePortContext->id)); + } + DeviceListList = DeviceListList->flink; + } + } + + return; +} + +/* called on discover failure */ +osGLOBAL void +dmDiscoveryInvalidateDevices( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmDeviceData_t *oneDeviceData = agNULL; + dmList_t *DeviceListList; + + DM_DBG1(("dmDiscoveryInvalidateDevices: start\n")); + + tddmSingleThreadedEnter(dmRoot, DM_DEVICE_LOCK); + if (DMLIST_EMPTY(&(dmAllShared->MainDeviceList))) + { + tddmSingleThreadedLeave(dmRoot, DM_DEVICE_LOCK); + DM_DBG3(("dmDiscoveryInvalidateDevices: empty device list\n")); + return; + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_DEVICE_LOCK); + } + DeviceListList = dmAllShared->MainDeviceList.flink; + while (DeviceListList != &(dmAllShared->MainDeviceList)) + { + oneDeviceData = DMLIST_OBJECT_BASE(dmDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + DM_DBG1(("dmDiscoveryInvalidateDevices: oneDeviceData is NULL!!!\n")); + return; + } + DM_DBG3(("dmDiscoveryInvalidateDevices: loop did %d\n", oneDeviceData->id)); + DM_DBG3(("dmDiscoveryInvalidateDevices: sasAddrHi 0x%08x \n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG3(("dmDiscoveryInvalidateDevices: sasAddrLo 0x%08x \n", oneDeviceData->SASAddressID.sasAddressLo)); + DM_DBG3(("dmDiscoveryInvalidateDevices: valid %d\n", oneDeviceData->valid)); + DM_DBG3(("dmDiscoveryInvalidateDevices: valid2 %d\n", oneDeviceData->valid2)); + DM_DBG3(("dmDiscoveryInvalidateDevices: directlyAttached %d\n", oneDeviceData->directlyAttached)); + if ( oneDeviceData->dmPortContext == onePortContext) + { + DM_DBG3(("dmDiscoveryInvalidateDevices: right portcontext pid %d\n", onePortContext->id)); + if (oneDeviceData->SASAddressID.sasAddressHi == onePortContext->sasRemoteAddressHi && + oneDeviceData->SASAddressID.sasAddressLo == onePortContext->sasRemoteAddressLo + ) + { + DM_DBG1(("dmDiscoveryInvalidateDevices: keeping\n")); + oneDeviceData->valid = agTRUE; + oneDeviceData->valid2 = agFALSE; + } + else + { + oneDeviceData->valid = agFALSE; + oneDeviceData->valid2 = agFALSE; + oneDeviceData->registered = agFALSE; + oneDeviceData->reported = agFALSE; + /* all targets other than expanders */ + DM_DBG3(("dmDiscoveryInvalidateDevices: did %d\n", oneDeviceData->id)); + DM_DBG3(("dmDiscoveryInvalidateDevices: sasAddrHi 0x%08x \n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG3(("dmDiscoveryInvalidateDevices: sasAddrLo 0x%08x \n", oneDeviceData->SASAddressID.sasAddressLo)); + onePortContext->RegisteredDevNums--; + } + DeviceListList = DeviceListList->flink; + } + else + { + if (oneDeviceData->dmPortContext != agNULL) + { + DM_DBG3(("dmDiscoveryInvalidateDevices: different portcontext; oneDeviceData->dmPortContext pid %d oneportcontext pid %d\n", oneDeviceData->dmPortContext->id, onePortContext->id)); + } + else + { + DM_DBG3(("dmDiscoveryInvalidateDevices: different portcontext; oneDeviceData->dmPortContext pid NULL oneportcontext pid %d\n", onePortContext->id)); + } + DeviceListList = DeviceListList->flink; + } + } + + return; +} + + +/* + should DM report the device removal to TDM on an error case? + or + DM simply removes the devices + For now, the second option. +*/ +osGLOBAL void +dmDiscoveryErrorRemovals( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmDeviceData_t *oneDeviceData = agNULL; + dmList_t *DeviceListList; + + DM_DBG1(("dmDiscoveryErrorRemovals: start\n")); + + tddmSingleThreadedEnter(dmRoot, DM_DEVICE_LOCK); + if (DMLIST_EMPTY(&(dmAllShared->MainDeviceList))) + { + tddmSingleThreadedLeave(dmRoot, DM_DEVICE_LOCK); + DM_DBG3(("dmDiscoveryErrorRemovals: empty device list\n")); + return; + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_DEVICE_LOCK); + } + DeviceListList = dmAllShared->MainDeviceList.flink; + while (DeviceListList != &(dmAllShared->MainDeviceList)) + { + oneDeviceData = DMLIST_OBJECT_BASE(dmDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + DM_DBG1(("dmDiscoveryErrorRemovals: oneDeviceData is NULL!!!\n")); + return; + } + DM_DBG3(("dmDiscoveryErrorRemovals: loop did %d\n", oneDeviceData->id)); + DM_DBG3(("dmDiscoveryErrorRemovals: sasAddrHi 0x%08x \n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG3(("dmDiscoveryErrorRemovals: sasAddrLo 0x%08x \n", oneDeviceData->SASAddressID.sasAddressLo)); + DM_DBG3(("dmDiscoveryErrorRemovals: valid %d\n", oneDeviceData->valid)); + DM_DBG3(("dmDiscoveryErrorRemovals: valid2 %d\n", oneDeviceData->valid2)); + DM_DBG3(("dmDiscoveryErrorRemovals: directlyAttached %d\n", oneDeviceData->directlyAttached)); + if ( oneDeviceData->dmPortContext == onePortContext) + { + DM_DBG3(("dmDiscoveryErrorRemovals: right portcontext pid %d\n", onePortContext->id)); + if (oneDeviceData->SASAddressID.sasAddressHi == onePortContext->sasRemoteAddressHi && + oneDeviceData->SASAddressID.sasAddressLo == onePortContext->sasRemoteAddressLo + ) + { + DM_DBG1(("dmDiscoveryErrorRemovals: keeping\n")); + oneDeviceData->valid = agTRUE; + oneDeviceData->valid2 = agFALSE; + } + else + { + oneDeviceData->valid = agFALSE; + oneDeviceData->valid2 = agFALSE; + + /* all targets other than expanders */ + DM_DBG3(("dmDiscoveryErrorRemovals: did %d\n", oneDeviceData->id)); + DM_DBG3(("dmDiscoveryErrorRemovals: sasAddrHi 0x%08x \n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG3(("dmDiscoveryErrorRemovals: sasAddrLo 0x%08x \n", oneDeviceData->SASAddressID.sasAddressLo)); + onePortContext->RegisteredDevNums--; + dmSubReportRemovals(dmRoot, onePortContext, oneDeviceData, dmDeviceRemoval); + + } + DeviceListList = DeviceListList->flink; + } + else + { + if (oneDeviceData->dmPortContext != agNULL) + { + DM_DBG3(("dmDiscoveryErrorRemovals: different portcontext; oneDeviceData->dmPortContext pid %d oneportcontext pid %d\n", oneDeviceData->dmPortContext->id, onePortContext->id)); + } + else + { + DM_DBG3(("dmDiscoveryErrorRemovals: different portcontext; oneDeviceData->dmPortContext pid NULL oneportcontext pid %d\n", onePortContext->id)); + } + DeviceListList = DeviceListList->flink; + } + } + + return; +} + +/* move from dmAllShared->mainExpanderList to dmAllShared->freeExpanderList */ +osGLOBAL void +dmDiscoveryExpanderCleanUp( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmExpander_t *oneExpander = agNULL; + dmList_t *ExpanderList = agNULL; + dmDeviceData_t *oneDeviceData = agNULL; + + DM_DBG3(("dmDiscoveryExpanderCleanUp: start\n")); + /* + be sure to call + osGLOBAL void + dmExpanderDeviceDataReInit( + dmRoot_t *dmRoot, + dmExpander_t *oneExpander + ); + + */ + + tddmSingleThreadedEnter(dmRoot, DM_EXPANDER_LOCK); + if (!DMLIST_EMPTY(&(dmAllShared->mainExpanderList))) + { + tddmSingleThreadedLeave(dmRoot, DM_EXPANDER_LOCK); + ExpanderList = dmAllShared->mainExpanderList.flink; + while (ExpanderList != &(dmAllShared->mainExpanderList)) + { + oneExpander = DMLIST_OBJECT_BASE(dmExpander_t, linkNode, ExpanderList); + if (oneExpander == agNULL) + { + DM_DBG1(("dmDiscoveryExpanderCleanUp: oneExpander is NULL!!!\n")); + return; + } + oneDeviceData = oneExpander->dmDevice; + DM_DBG3(("dmDiscoveryExpanderCleanUp: sasAddrHi 0x%08x \n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG3(("dmDiscoveryExpanderCleanUp: sasAddrLo 0x%08x \n", oneDeviceData->SASAddressID.sasAddressLo)); + if ( oneDeviceData->dmPortContext == onePortContext) + { + dmExpanderDeviceDataReInit(dmRoot, oneExpander); + tddmSingleThreadedEnter(dmRoot, DM_EXPANDER_LOCK); + DMLIST_DEQUEUE_THIS(&(oneExpander->linkNode)); + DMLIST_ENQUEUE_AT_TAIL(&(oneExpander->linkNode), &(dmAllShared->freeExpanderList)); + + if (DMLIST_EMPTY(&(dmAllShared->mainExpanderList))) + { + tddmSingleThreadedLeave(dmRoot, DM_EXPANDER_LOCK); + break; + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_EXPANDER_LOCK); + } + ExpanderList = dmAllShared->mainExpanderList.flink; + } + else + { + ExpanderList = ExpanderList->flink; + } + } + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_EXPANDER_LOCK); + DM_DBG3(("dmDiscoveryExpanderCleanUp: empty mainExpanderList\n")); + } + return; + +} + + +/* moves all devices from dmAllShared->MainDeviceList to dmAllShared->FreeDeviceList */ +osGLOBAL void +dmDiscoveryDeviceCleanUp( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmDeviceData_t *oneDeviceData = agNULL; + dmList_t *DeviceListList; + + DM_DBG3(("dmDiscoveryDeviceCleanUp: start\n")); + + tddmSingleThreadedEnter(dmRoot, DM_DEVICE_LOCK); + if (!DMLIST_EMPTY(&(dmAllShared->MainDeviceList))) + { + tddmSingleThreadedLeave(dmRoot, DM_DEVICE_LOCK); + DeviceListList = dmAllShared->MainDeviceList.flink; + while (DeviceListList != &(dmAllShared->MainDeviceList)) + { + oneDeviceData = DMLIST_OBJECT_BASE(dmDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + DM_DBG1(("dmDiscoveryDeviceCleanUp: oneDeviceData is NULL!!!\n")); + return; + } + DM_DBG3(("dmDiscoveryDeviceCleanUp: sasAddrHi 0x%08x \n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG3(("dmDiscoveryDeviceCleanUp: sasAddrLo 0x%08x \n", oneDeviceData->SASAddressID.sasAddressLo)); + if ( oneDeviceData->dmPortContext == onePortContext) + { + dmDeviceDataReInit(dmRoot, oneDeviceData); + tddmSingleThreadedEnter(dmRoot, DM_DEVICE_LOCK); + DMLIST_DEQUEUE_THIS(&(oneDeviceData->MainLink)); + DMLIST_ENQUEUE_AT_TAIL(&(oneDeviceData->FreeLink), &(dmAllShared->FreeDeviceList)); + + if (DMLIST_EMPTY(&(dmAllShared->MainDeviceList))) + { + tddmSingleThreadedLeave(dmRoot, DM_DEVICE_LOCK); + break; + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_DEVICE_LOCK); + } + onePortContext->RegisteredDevNums--; + DeviceListList = dmAllShared->MainDeviceList.flink; + } + else + { + DeviceListList = DeviceListList->flink; + } + } + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_DEVICE_LOCK); + DM_DBG3(("dmDiscoveryDeviceCleanUp: empty MainDeviceList\n")); + } + return; +} + + + +osGLOBAL void +dmDumpAllExp( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmExpander_t *oneExpander + ) +{ + DM_DBG3(("dmDumpAllExp: start\n")); + return; +} + + +osGLOBAL void +dmDumpAllUpExp( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmExpander_t *oneExpander + ) +{ + DM_DBG3(("dmDumpAllUpExp: start\n")); + return; +} + +osGLOBAL void +dmDumpAllFreeExp( + dmRoot_t *dmRoot + ) +{ + DM_DBG3(("dmDumpAllFreeExp: start\n")); + return; +} + +osGLOBAL void +dmDumpAllMainExp( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmList_t *ExpanderList; + dmExpander_t *tempExpander; + + DM_DBG3(("dmDumpAllMainExp: start\n")); + + tddmSingleThreadedEnter(dmRoot, DM_EXPANDER_LOCK); + if (DMLIST_EMPTY(&(dmAllShared->mainExpanderList))) + { + DM_DBG3(("dmDumpAllMainExp: empty discoveringExpanderList\n")); + tddmSingleThreadedLeave(dmRoot, DM_EXPANDER_LOCK); + return; + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_EXPANDER_LOCK); + } + + ExpanderList = dmAllShared->mainExpanderList.flink; + while (ExpanderList != &(dmAllShared->mainExpanderList)) + { + tempExpander = DMLIST_OBJECT_BASE(dmExpander_t, linkNode, ExpanderList); + if (tempExpander == agNULL) + { + DM_DBG1(("dmDumpAllMainExp: tempExpander is NULL!!!\n")); + return; + } + DM_DBG3(("dmDumpAllMainExp: expander id %d\n", tempExpander->id)); + DM_DBG3(("dmDumpAllMainExp: exp addrHi 0x%08x\n", tempExpander->dmDevice->SASAddressID.sasAddressHi)); + DM_DBG3(("dmDumpAllMainExp: exp addrLo 0x%08x\n", tempExpander->dmDevice->SASAddressID.sasAddressLo)); + if ((tempExpander->dmDevice->dmPortContext == onePortContext) + ) + { + DM_DBG3(("dmDumpAllMainExp: found expander id %d\n", tempExpander->id)); + DM_DBG3(("dmDumpAllMainExp: found exp addrHi 0x%08x\n", tempExpander->dmDevice->SASAddressID.sasAddressHi)); + DM_DBG3(("dmDumpAllMainExp: found exp addrLo 0x%08x\n", tempExpander->dmDevice->SASAddressID.sasAddressLo)); + } + ExpanderList = ExpanderList->flink; + } + return; +} + + +osGLOBAL void +dmDumpAllMainDevice( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmDeviceData_t *oneDeviceData = agNULL; + dmList_t *DeviceListList; + bit32 total = 0, port_total = 0; + + DM_DBG3(("dmDumpAllMainDevice: start\n")); + + tddmSingleThreadedEnter(dmRoot, DM_DEVICE_LOCK); + if (DMLIST_EMPTY(&(dmAllShared->MainDeviceList))) + { + DM_DBG3(("dmDumpAllMainDevice: empty discoveringExpanderList\n")); + tddmSingleThreadedLeave(dmRoot, DM_DEVICE_LOCK); + return; + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_DEVICE_LOCK); + } + + DeviceListList = dmAllShared->MainDeviceList.flink; + while (DeviceListList != &(dmAllShared->MainDeviceList)) + { + oneDeviceData = DMLIST_OBJECT_BASE(dmDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + DM_DBG3(("dmDumpAllMainDevice: oneDeviceData is NULL!!!\n")); + return; + } + DM_DBG3(("dmDumpAllMainDevice: oneDeviceData id %d\n", oneDeviceData->id)); + DM_DBG3(("dmDumpAllMainDevice: addrHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG3(("dmDumpAllMainDevice: addrLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + total++; + if ((oneDeviceData->dmPortContext == onePortContext) + ) + { + DM_DBG3(("dmDumpAllMainDevice: found oneDeviceData id %d\n", oneDeviceData->id)); + DM_DBG3(("dmDumpAllMainDevice: found addrHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG3(("dmDumpAllMainDevice: found addrLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + port_total++; + } + DeviceListList = DeviceListList->flink; + } + DM_DBG3(("dmDumpAllMainDevice: total %d port_totaol %d\n", total, port_total)); + + return; +} + + + +osGLOBAL dmDeviceData_t * +dmAddSASToSharedcontext( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmSASSubID_t *dmSASSubID, + dmDeviceData_t *oneExpDeviceData, + bit8 phyID + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmDeviceData_t *oneDeviceData = agNULL; + dmList_t *DeviceListList; + bit32 new_device = agTRUE; + + + DM_DBG3(("dmAddSASToSharedcontext: start\n")); + DM_DBG3(("dmAddSASToSharedcontext: oneportContext ID %d\n", onePortContext->id)); + + if (oneExpDeviceData != agNULL) + { + DM_DBG3(("dmAddSASToSharedcontext: oneExpDeviceData sasAddressHi 0x%08x sasAddressLo 0x%08x\n", + oneExpDeviceData->SASAddressID.sasAddressHi, oneExpDeviceData->SASAddressID.sasAddressLo)); + } + else + { + DM_DBG3(("dmAddSASToSharedcontext: oneExpDeviceData is NULL\n")); + } + /* find a device's existence */ + DeviceListList = dmAllShared->MainDeviceList.flink; + while (DeviceListList != &(dmAllShared->MainDeviceList)) + { + oneDeviceData = DMLIST_OBJECT_BASE(dmDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + DM_DBG1(("dmAddSASToSharedcontext: oneDeviceData is NULL!!!\n")); + return agNULL; + } + if ((oneDeviceData->SASAddressID.sasAddressHi == dmSASSubID->sasAddressHi) && + (oneDeviceData->SASAddressID.sasAddressLo == dmSASSubID->sasAddressLo) && + (oneDeviceData->dmPortContext == onePortContext) + ) + { + DM_DBG3(("dmAddSASToSharedcontext: pid %d did %d\n", onePortContext->id, oneDeviceData->id)); + new_device = agFALSE; + break; + } + DeviceListList = DeviceListList->flink; + } + + /* new device */ + if (new_device == agTRUE) + { + DM_DBG3(("dmAddSASToSharedcontext: new device\n")); + DM_DBG3(("dmAddSASToSharedcontext: sasAddressHi 0x%08x sasAddressLo 0x%08x\n", + dmSASSubID->sasAddressHi, dmSASSubID->sasAddressLo)); + tddmSingleThreadedEnter(dmRoot, DM_DEVICE_LOCK); + if (!DMLIST_NOT_EMPTY(&(dmAllShared->FreeDeviceList))) + { + tddmSingleThreadedLeave(dmRoot, DM_DEVICE_LOCK); + DM_DBG1(("dmAddSASToSharedcontext: empty DeviceData FreeLink\n")); + dmDumpAllMainDevice(dmRoot, onePortContext); + return agNULL; + } + + DMLIST_DEQUEUE_FROM_HEAD(&DeviceListList, &(dmAllShared->FreeDeviceList)); + tddmSingleThreadedLeave(dmRoot, DM_DEVICE_LOCK); + oneDeviceData = DMLIST_OBJECT_BASE(dmDeviceData_t, FreeLink, DeviceListList); + + if (oneDeviceData != agNULL) + { + DM_DBG3(("dmAddSASToSharedcontext: oneDeviceData %p pid %d did %d\n", oneDeviceData, onePortContext->id, oneDeviceData->id)); + + onePortContext->Count++; + oneDeviceData->dmRoot = dmRoot; + /* saving sas address */ + oneDeviceData->SASAddressID.sasAddressLo = dmSASSubID->sasAddressLo; + oneDeviceData->SASAddressID.sasAddressHi = dmSASSubID->sasAddressHi; + oneDeviceData->initiator_ssp_stp_smp = dmSASSubID->initiator_ssp_stp_smp; + oneDeviceData->target_ssp_stp_smp = dmSASSubID->target_ssp_stp_smp; + oneDeviceData->dmPortContext = onePortContext; + /* handles both SAS target and STP-target, SATA-device */ + if (!DEVICE_IS_SATA_DEVICE(oneDeviceData) && !DEVICE_IS_STP_TARGET(oneDeviceData)) + { + oneDeviceData->DeviceType = DM_SAS_DEVICE; + } + else + { + oneDeviceData->DeviceType = DM_SATA_DEVICE; + } + + if (oneExpDeviceData != agNULL) + { + oneDeviceData->ExpDevice = oneExpDeviceData; + } + + /* set phyID only when it has initial value of 0xFF */ + if (oneDeviceData->phyID == 0xFF) + { + oneDeviceData->phyID = phyID; + } + /* incremental discovery */ + /* add device to incremental-related link. Report using this link + when incremental discovery is done */ + if (onePortContext->DiscoveryState == DM_DSTATE_NOT_STARTED) + { + DM_DBG3(("dmAddSASToSharedcontext: DM_DSTATE_NOT_STARTED\n")); + DM_DBG3(("dmAddSASToSharedcontext: sasAddrHi 0x%08x \n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG3(("dmAddSASToSharedcontext: sasAddrLo 0x%08x \n", oneDeviceData->SASAddressID.sasAddressLo)); + oneDeviceData->valid = agTRUE; + } + else + { + if (onePortContext->discovery.type == DM_DISCOVERY_OPTION_INCREMENTAL_START) + { + DM_DBG3(("dmAddSASToSharedcontext: incremental discovery\n")); + DM_DBG3(("dmAddSASToSharedcontext: sasAddrHi 0x%08x \n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG3(("dmAddSASToSharedcontext: sasAddrLo 0x%08x \n", oneDeviceData->SASAddressID.sasAddressLo)); + oneDeviceData->valid2 = agTRUE; + } + else + { + DM_DBG3(("dmAddSASToSharedcontext: full discovery\n")); + DM_DBG3(("dmAddSASToSharedcontext: sasAddrHi 0x%08x \n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG3(("dmAddSASToSharedcontext: sasAddrLo 0x%08x \n", oneDeviceData->SASAddressID.sasAddressLo)); + oneDeviceData->valid = agTRUE; + } + } + /* add the devicedata to the portcontext */ + tddmSingleThreadedEnter(dmRoot, DM_DEVICE_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(oneDeviceData->MainLink), &(dmAllShared->MainDeviceList)); + tddmSingleThreadedLeave(dmRoot, DM_DEVICE_LOCK); + DM_DBG3(("dmAddSASToSharedcontext: one case pid %d did %d \n", onePortContext->id, oneDeviceData->id)); + DM_DBG3(("dmAddSASToSharedcontext: new case pid %d did %d phyID %d\n", onePortContext->id, oneDeviceData->id, oneDeviceData->phyID)); + } + } + else /* old device */ + { + DM_DBG3(("dmAddSASToSharedcontext: old device\n")); + DM_DBG3(("dmAddSASToSharedcontext: oneDeviceData %p did %d\n", oneDeviceData, oneDeviceData->id)); + DM_DBG3(("dmAddSASToSharedcontext: sasAddressHi 0x%08x sasAddressLo 0x%08x\n", + dmSASSubID->sasAddressHi, dmSASSubID->sasAddressLo)); + + oneDeviceData->dmRoot = dmRoot; + /* saving sas address */ + oneDeviceData->SASAddressID.sasAddressLo = dmSASSubID->sasAddressLo; + oneDeviceData->SASAddressID.sasAddressHi = dmSASSubID->sasAddressHi; + oneDeviceData->initiator_ssp_stp_smp = dmSASSubID->initiator_ssp_stp_smp; + oneDeviceData->target_ssp_stp_smp = dmSASSubID->target_ssp_stp_smp; + oneDeviceData->dmPortContext = onePortContext; + /* handles both SAS target and STP-target, SATA-device */ + if (!DEVICE_IS_SATA_DEVICE(oneDeviceData) && !DEVICE_IS_STP_TARGET(oneDeviceData)) + { + oneDeviceData->DeviceType = DM_SAS_DEVICE; + } + else + { + oneDeviceData->DeviceType = DM_SATA_DEVICE; + } + + if (oneExpDeviceData != agNULL) + { + oneDeviceData->ExpDevice = oneExpDeviceData; + } + + /* set phyID only when it has initial value of 0xFF */ + if (oneDeviceData->phyID == 0xFF) + { + oneDeviceData->phyID = phyID; + } + + if (onePortContext->DiscoveryState == DM_DSTATE_NOT_STARTED) + { + DM_DBG3(("dmAddSASToSharedcontext: DM_DSTATE_NOT_STARTED\n")); + DM_DBG3(("dmAddSASToSharedcontext: sasAddrHi 0x%08x \n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG3(("dmAddSASToSharedcontext: sasAddrLo 0x%08x \n", oneDeviceData->SASAddressID.sasAddressLo)); + oneDeviceData->valid = agTRUE; + } + else + { + if (onePortContext->discovery.type == DM_DISCOVERY_OPTION_INCREMENTAL_START) + { + DM_DBG3(("dmAddSASToSharedcontext: incremental discovery\n")); + DM_DBG3(("dmAddSASToSharedcontext: sasAddrHi 0x%08x \n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG3(("dmAddSASToSharedcontext: sasAddrLo 0x%08x \n", oneDeviceData->SASAddressID.sasAddressLo)); + oneDeviceData->valid2 = agTRUE; + } + else + { + DM_DBG3(("dmAddSASToSharedcontext: full discovery\n")); + DM_DBG3(("dmAddSASToSharedcontext: sasAddrHi 0x%08x \n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG3(("dmAddSASToSharedcontext: sasAddrLo 0x%08x \n", oneDeviceData->SASAddressID.sasAddressLo)); + oneDeviceData->valid = agTRUE; + } + } + DM_DBG3(("dmAddSASToSharedcontext: old case pid %d did %d phyID %d\n", onePortContext->id, oneDeviceData->id, oneDeviceData->phyID)); + + } + return oneDeviceData; +} + +/* no checking of valid and valid2 */ +osGLOBAL dmDeviceData_t * +dmDeviceFind( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + bit32 sasAddrHi, + bit32 sasAddrLo + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmDeviceData_t *oneDeviceData = agNULL; + dmList_t *DeviceListList; + bit32 found = agFALSE; + + DM_DBG3(("dmDeviceFind: start\n")); + /* find a device's existence */ + DeviceListList = dmAllShared->MainDeviceList.flink; + + while (DeviceListList != &(dmAllShared->MainDeviceList)) + { + oneDeviceData = DMLIST_OBJECT_BASE(dmDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + DM_DBG1(("dmDeviceFind: oneDeviceData is NULL!!!\n")); + return agNULL; + } + if ((oneDeviceData->SASAddressID.sasAddressHi == sasAddrHi) && + (oneDeviceData->SASAddressID.sasAddressLo == sasAddrLo) && +// (oneDeviceData->valid == agTRUE) && + (oneDeviceData->dmPortContext == onePortContext) + ) + { + DM_DBG3(("dmDeviceFind: Found pid %d did %d\n", onePortContext->id, oneDeviceData->id)); + DM_DBG3(("dmDeviceFind: sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG3(("dmDeviceFind: sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + found = agTRUE; + break; + } + DeviceListList = DeviceListList->flink; + } + + if (found == agFALSE) + { + DM_DBG3(("dmDeviceFind: end returning NULL\n")); + return agNULL; + } + else + { + DM_DBG3(("dmDeviceFind: end returning NOT NULL\n")); + return oneDeviceData; + } + +} + + +osGLOBAL void +dmBCTimer( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmDiscovery_t *discovery; + + DM_DBG3(("dmBCTimer: start\n")); + + discovery = &(onePortContext->discovery); + + tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK); + if (discovery->BCTimer.timerRunning == agTRUE) + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + dmKillTimer( + dmRoot, + &discovery->BCTimer + ); + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + } + + if (onePortContext->valid == agTRUE) + { + dmSetTimerRequest( + dmRoot, + &discovery->BCTimer, + BC_TIMER_VALUE/dmAllShared->usecsPerTick, + dmBCTimerCB, + onePortContext, + agNULL, + agNULL + ); + + dmAddTimer( + dmRoot, + &dmAllShared->timerlist, + &discovery->BCTimer + ); + + } + + + return; +} + + +osGLOBAL void +dmBCTimerCB( + dmRoot_t * dmRoot, + void * timerData1, + void * timerData2, + void * timerData3 + ) +{ + dmIntPortContext_t *onePortContext; + dmDiscovery_t *discovery; + + DM_DBG3(("dmBCTimerCB: start\n")); + + onePortContext = (dmIntPortContext_t *)timerData1; + discovery = &(onePortContext->discovery); + + tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK); + if (discovery->BCTimer.timerRunning == agTRUE) + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + dmKillTimer( + dmRoot, + &discovery->BCTimer + ); + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + } + + discovery->ResetTriggerred = agFALSE; + + if (onePortContext->valid == agTRUE) + { + dmDiscover(dmRoot, + onePortContext->dmPortContext, + DM_DISCOVERY_OPTION_INCREMENTAL_START + ); + } + return; +} + +/* discovery related SMP timers */ +osGLOBAL void +dmDiscoverySMPTimer(dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + bit32 functionCode, + dmSMPRequestBody_t *dmSMPRequestBody + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmDiscovery_t *discovery; + + DM_DBG3(("dmDiscoverySMPTimer: start\n")); + DM_DBG3(("dmDiscoverySMPTimer: pid %d SMPFn 0x%x\n", onePortContext->id, functionCode)); + + /* start the SMP timer which works as SMP application timer */ + discovery = &(onePortContext->discovery); + + tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK); + if (discovery->DiscoverySMPTimer.timerRunning == agTRUE) + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + dmKillTimer( + dmRoot, + &discovery->DiscoverySMPTimer + ); + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + } + + + dmSetTimerRequest( + dmRoot, + &discovery->DiscoverySMPTimer, + SMP_TIMER_VALUE/dmAllShared->usecsPerTick, + dmDiscoverySMPTimerCB, + onePortContext, + dmSMPRequestBody, + agNULL + ); + + dmAddTimer ( + dmRoot, + &dmAllShared->timerlist, + &discovery->DiscoverySMPTimer + ); + + return; +} + + +osGLOBAL void +dmDiscoverySMPTimerCB( + dmRoot_t * dmRoot, + void * timerData1, + void * timerData2, + void * timerData3 + ) +{ + agsaRoot_t *agRoot; + dmIntPortContext_t *onePortContext; + bit8 SMPFunction; +#ifndef DIRECT_SMP + dmSMPFrameHeader_t *dmSMPFrameHeader; + bit8 smpHeader[4]; +#endif + dmSMPRequestBody_t *dmSMPRequestBody; + dmDiscovery_t *discovery; + dmDeviceData_t *oneDeviceData; + agsaIORequest_t *agAbortIORequest = agNULL; + agsaIORequest_t *agToBeAbortIORequest = agNULL; + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmExpander_t *oneExpander = agNULL; + dmSMPRequestBody_t *dmAbortSMPRequestBody = agNULL; + dmList_t *SMPList; + + DM_DBG1(("dmDiscoverySMPTimerCB: start!!!\n")); + + onePortContext = (dmIntPortContext_t *)timerData1; + dmSMPRequestBody = (dmSMPRequestBody_t *)timerData2; + + discovery = &(onePortContext->discovery); + oneDeviceData = dmSMPRequestBody->dmDevice; + agToBeAbortIORequest = &(dmSMPRequestBody->agIORequest); + agRoot = dmAllShared->agRoot; + +#ifdef DIRECT_SMP + SMPFunction = dmSMPRequestBody->smpPayload[1]; +#else + saFrameReadBlock(agRoot, dmSMPRequestBody->IndirectSMP, 0, smpHeader, 4); + dmSMPFrameHeader = (dmSMPFrameHeader_t *)smpHeader; + SMPFunction = dmSMPFrameHeader->smpFunction; +#endif + + DM_DBG3(("dmDiscoverySMPTimerCB: SMP function 0x%x\n", SMPFunction)); + + tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK); + if (discovery->DiscoverySMPTimer.timerRunning == agTRUE) + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + dmKillTimer( + dmRoot, + &discovery->DiscoverySMPTimer + ); + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + } + +//for debugging +// saGetPendingPICI(agRoot); + + switch (SMPFunction) + { + case SMP_REPORT_GENERAL: /* fall through */ + case SMP_DISCOVER: /* fall through */ + case SMP_CONFIGURE_ROUTING_INFORMATION: /* fall through */ + DM_DBG1(("dmDiscoverySMPTimerCB: failing discovery, SMP function 0x%x !!!\n", SMPFunction)); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + return; /* no more things to do */ + case SMP_REPORT_PHY_SATA: + DM_DBG1(("dmDiscoverySMPTimerCB: failing discovery, SMP function SMP_REPORT_PHY_SATA !!!\n")); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + break; + default: + /* do nothing */ + DM_DBG1(("dmDiscoverySMPTimerCB: Error, not allowed case!!!\n")); + break; + } + + if (oneDeviceData->registered == agTRUE && (oneDeviceData->valid == agTRUE || oneDeviceData->valid2 == agTRUE) ) + { + /* call to saSMPAbort(one) */ + /* get an smp REQUEST from the free list */ + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + if (DMLIST_EMPTY(&(dmAllShared->freeSMPList))) + { + DM_DBG1(("dmDiscoverySMPTimerCB: no free SMP, can't abort SMP!!!\n")); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); + return; + } + else + { + DMLIST_DEQUEUE_FROM_HEAD(&SMPList, &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); + dmAbortSMPRequestBody = DMLIST_OBJECT_BASE(dmSMPRequestBody_t, Link, SMPList); + if (dmAbortSMPRequestBody == agNULL) + { + DM_DBG1(("dmDiscoverySMPTimerCB: dmAbortSMPRequestBody is NULL!!!\n")); + return; + } + DM_DBG5(("dmDiscoverySMPTimerCB: SMP id %d\n", dmAbortSMPRequestBody->id)); + } + + dmAbortSMPRequestBody->dmRoot = dmRoot; + + agAbortIORequest = &(dmAbortSMPRequestBody->agIORequest); + agAbortIORequest->osData = (void *) dmAbortSMPRequestBody; + agAbortIORequest->sdkData = agNULL; /* SALL takes care of this */ + + oneExpander = oneDeviceData->dmExpander; + + DM_DBG1(("dmDiscoverySMPTimerCB: calling saSMPAbort!!!\n")); + saSMPAbort(agRoot, + agAbortIORequest, + 0, + oneExpander->agDevHandle, + 0, /* abort one */ + agToBeAbortIORequest, + dmSMPAbortCB + ); + } + return; +} + + + + +osGLOBAL void +dmSMPBusyTimer(dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmDeviceData_t *oneDeviceData, + dmSMPRequestBody_t *dmSMPRequestBody + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmDiscovery_t *discovery; + + DM_DBG3(("dmSMPBusyTimer: start\n")); + DM_DBG3(("dmSMPBusyTimer: pid %d\n", onePortContext->id)); + + discovery = &(onePortContext->discovery); + + tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK); + if (discovery->SMPBusyTimer.timerRunning == agTRUE) + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + dmKillTimer( + dmRoot, + &discovery->SMPBusyTimer + ); + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + } + + dmSetTimerRequest( + dmRoot, + &discovery->SMPBusyTimer, + SMP_BUSY_TIMER_VALUE/dmAllShared->usecsPerTick, + dmSMPBusyTimerCB, + onePortContext, + oneDeviceData, + dmSMPRequestBody + ); + + dmAddTimer ( + dmRoot, + &dmAllShared->timerlist, + &discovery->SMPBusyTimer + ); + + + return; +} + +osGLOBAL void +dmSMPBusyTimerCB( + dmRoot_t * dmRoot, + void * timerData1, + void * timerData2, + void * timerData3 + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + agsaRoot_t *agRoot; + dmIntPortContext_t *onePortContext; + dmDeviceData_t *oneDeviceData; + dmSMPRequestBody_t *dmSMPRequestBody; + agsaSASRequestBody_t *agSASRequestBody; + agsaIORequest_t *agIORequest; + agsaDevHandle_t *agDevHandle; + dmDiscovery_t *discovery; + bit32 status = AGSA_RC_FAILURE; + dmExpander_t *oneExpander = agNULL; + + + DM_DBG3(("dmSMPBusyTimerCB: start\n")); + + onePortContext = (dmIntPortContext_t *)timerData1; + oneDeviceData = (dmDeviceData_t *)timerData2; + dmSMPRequestBody = (dmSMPRequestBody_t *)timerData3; + agRoot = dmAllShared->agRoot; + agIORequest = &(dmSMPRequestBody->agIORequest); + oneExpander = oneDeviceData->dmExpander; + agDevHandle = oneExpander->agDevHandle; + agSASRequestBody = &(dmSMPRequestBody->agSASRequestBody); + discovery = &(onePortContext->discovery); + + discovery->SMPRetries++; + + if (discovery->SMPRetries < SMP_BUSY_RETRIES) + { + status = saSMPStart( + agRoot, + agIORequest, + 0, + agDevHandle, + AGSA_SMP_INIT_REQ, + agSASRequestBody, + &dmsaSMPCompleted + ); + } + + if (status == AGSA_RC_SUCCESS) + { + discovery->SMPRetries = 0; + tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK); + if (discovery->SMPBusyTimer.timerRunning == agTRUE) + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + dmKillTimer( + dmRoot, + &discovery->SMPBusyTimer + ); + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + } + } + else if (status == AGSA_RC_FAILURE) + { + tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK); + if (discovery->SMPBusyTimer.timerRunning == agTRUE) + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + dmKillTimer( + dmRoot, + &discovery->SMPBusyTimer + ); + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + } + + discovery->SMPRetries = 0; + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + else /* AGSA_RC_BUSY */ + { + if (discovery->SMPRetries >= SMP_BUSY_RETRIES) + { + /* done with retris; give up */ + DM_DBG3(("dmSMPBusyTimerCB: retries are over\n")); + + tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK); + if (discovery->SMPBusyTimer.timerRunning == agTRUE) + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + dmKillTimer( + dmRoot, + &discovery->SMPBusyTimer + ); + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + } + + discovery->SMPRetries = 0; + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + + } + else + { + /* keep retrying */ + dmSMPBusyTimer(dmRoot, onePortContext, oneDeviceData, dmSMPRequestBody); + } + } + + return; +} + + +/* expander configuring timer */ +osGLOBAL void +dmDiscoveryConfiguringTimer(dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmDeviceData_t *oneDeviceData + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmDiscovery_t *discovery; + + DM_DBG3(("dmDiscoveryConfiguringTimer: start\n")); + DM_DBG3(("dmDiscoveryConfiguringTimer: pid %d\n", onePortContext->id)); + + discovery = &(onePortContext->discovery); + + tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK); + if (discovery->discoveryTimer.timerRunning == agTRUE) + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + dmKillTimer( + dmRoot, + &discovery->discoveryTimer + ); + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + } + + DM_DBG3(("dmDiscoveryConfiguringTimer: UsecsPerTick %d\n", dmAllShared->usecsPerTick)); + DM_DBG3(("dmDiscoveryConfiguringTimer: Timervalue %d\n", DISCOVERY_CONFIGURING_TIMER_VALUE/dmAllShared->usecsPerTick)); + + dmSetTimerRequest( + dmRoot, + &discovery->discoveryTimer, + DISCOVERY_CONFIGURING_TIMER_VALUE/dmAllShared->usecsPerTick, + dmDiscoveryConfiguringTimerCB, + onePortContext, + oneDeviceData, + agNULL + ); + + dmAddTimer ( + dmRoot, + &dmAllShared->timerlist, + &discovery->discoveryTimer + ); + + + return; +} + + +osGLOBAL void +dmDiscoveryConfiguringTimerCB( + dmRoot_t * dmRoot, + void * timerData1, + void * timerData2, + void * timerData3 + ) +{ + dmIntPortContext_t *onePortContext = agNULL; + dmDiscovery_t *discovery = agNULL; + dmDeviceData_t *oneDeviceData = agNULL; + + onePortContext = (dmIntPortContext_t *)timerData1; + oneDeviceData = (dmDeviceData_t *)timerData2; + discovery = &(onePortContext->discovery); + + DM_DBG3(("dmDiscoveryConfiguringTimerCB: start\n")); + + tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK); + if (discovery->discoveryTimer.timerRunning == agTRUE) + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + dmKillTimer( + dmRoot, + &discovery->discoveryTimer + ); + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + } + + if (oneDeviceData->valid == agTRUE || oneDeviceData->valid2 == agTRUE) + { + dmReportGeneralSend(dmRoot, oneDeviceData); + } + return; +} + +osGLOBAL void +dmConfigureRouteTimer(dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmExpander_t *oneExpander, + smpRespDiscover_t *pdmSMPDiscoverResp, + smpRespDiscover2_t *pdmSMPDiscover2Resp + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmDiscovery_t *discovery; + + DM_DBG3(("dmConfigureRouteTimer: start\n")); + + DM_DBG3(("dmConfigureRouteTimer: pid %d\n", onePortContext->id)); + + discovery = &(onePortContext->discovery); + + DM_DBG3(("dmConfigureRouteTimer: onePortContext %p oneExpander %p pdmSMPDiscoverResp %p\n", onePortContext, oneExpander, pdmSMPDiscoverResp)); + + DM_DBG3(("dmConfigureRouteTimer: discovery %p \n", discovery)); + + DM_DBG3(("dmConfigureRouteTimer: pid %d configureRouteRetries %d\n", onePortContext->id, discovery->configureRouteRetries)); + + DM_DBG3(("dmConfigureRouteTimer: discovery->status %d\n", discovery->status)); + + tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK); + if (discovery->configureRouteTimer.timerRunning == agTRUE) + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + dmKillTimer( + dmRoot, + &discovery->configureRouteTimer + ); + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + } + + DM_DBG3(("dmConfigureRouteTimer: UsecsPerTick %d\n", dmAllShared->usecsPerTick)); + DM_DBG3(("dmConfigureRouteTimer: Timervalue %d\n", CONFIGURE_ROUTE_TIMER_VALUE/dmAllShared->usecsPerTick)); + + if (oneExpander->SAS2 == 0) + { + /* SAS 1.1 */ + dmSetTimerRequest( + dmRoot, + &discovery->configureRouteTimer, + CONFIGURE_ROUTE_TIMER_VALUE/dmAllShared->usecsPerTick, + dmConfigureRouteTimerCB, + (void *)onePortContext, + (void *)oneExpander, + (void *)pdmSMPDiscoverResp + ); + } + else + { + /* SAS 2 */ + dmSetTimerRequest( + dmRoot, + &discovery->configureRouteTimer, + CONFIGURE_ROUTE_TIMER_VALUE/dmAllShared->usecsPerTick, + dmConfigureRouteTimerCB, + (void *)onePortContext, + (void *)oneExpander, + (void *)pdmSMPDiscover2Resp + ); + } + dmAddTimer ( + dmRoot, + &dmAllShared->timerlist, + &discovery->configureRouteTimer + ); + + return; +} + + +osGLOBAL void +dmConfigureRouteTimerCB( + dmRoot_t * dmRoot, + void * timerData1, + void * timerData2, + void * timerData3 + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmIntPortContext_t *onePortContext; + dmExpander_t *oneExpander; + smpRespDiscover_t *pdmSMPDiscoverResp = agNULL; + smpRespDiscover2_t *pdmSMPDiscover2Resp = agNULL; + dmDiscovery_t *discovery; + + + DM_DBG3(("dmConfigureRouteTimerCB: start\n")); + + onePortContext = (dmIntPortContext_t *)timerData1; + oneExpander = (dmExpander_t *)timerData2; + if (oneExpander->SAS2 == 0) + { + pdmSMPDiscoverResp = (smpRespDiscover_t *)timerData3; + } + else + { + pdmSMPDiscover2Resp = (smpRespDiscover2_t *)timerData3; + } + discovery = &(onePortContext->discovery); + + DM_DBG3(("dmConfigureRouteTimerCB: onePortContext %p oneExpander %p pdmSMPDiscoverResp %p\n", onePortContext, oneExpander, pdmSMPDiscoverResp)); + + DM_DBG3(("dmConfigureRouteTimerCB: discovery %p\n", discovery)); + + DM_DBG3(("dmConfigureRouteTimerCB: pid %d configureRouteRetries %d\n", onePortContext->id, discovery->configureRouteRetries)); + + DM_DBG3(("dmConfigureRouteTimerCB: discovery.status %d\n", discovery->status)); + + discovery->configureRouteRetries++; + if (discovery->configureRouteRetries >= dmAllShared->MaxRetryDiscovery) + { + DM_DBG3(("dmConfigureRouteTimerCB: retries are over\n")); + + tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK); + if (discovery->configureRouteTimer.timerRunning == agTRUE) + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + dmKillTimer( + dmRoot, + &discovery->configureRouteTimer + ); + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + } + + discovery->configureRouteRetries = 0; + /* failed the discovery */ + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + + return; + } + + + if (oneExpander->SAS2 == 0) + { + if (onePortContext->discovery.status == DISCOVERY_DOWN_STREAM) + { + DM_DBG3(("dmConfigureRouteTimerCB: proceed by calling dmDownStreamDiscoverExpanderPhy\n")); + dmhexdump("dmConfigureRouteTimerCB", (bit8*)pdmSMPDiscoverResp, sizeof(smpRespDiscover_t)); + discovery->configureRouteRetries = 0; + + dmDownStreamDiscoverExpanderPhy(dmRoot, onePortContext, oneExpander, pdmSMPDiscoverResp); + } + else + { + DM_DBG3(("dmConfigureRouteTimerCB: setting timer again\n")); + /* set the timer again */ + dmSetTimerRequest( + dmRoot, + &discovery->configureRouteTimer, + CONFIGURE_ROUTE_TIMER_VALUE/dmAllShared->usecsPerTick, + dmConfigureRouteTimerCB, + (void *)onePortContext, + (void *)oneExpander, + (void *)pdmSMPDiscoverResp + ); + + dmAddTimer ( + dmRoot, + &dmAllShared->timerlist, + &discovery->configureRouteTimer + ); + } + } /* SAS 1.1 */ + else + { + /* SAS 2 */ + if (onePortContext->discovery.status == DISCOVERY_DOWN_STREAM) + { + DM_DBG2(("dmConfigureRouteTimerCB: proceed by calling dmDownStreamDiscover2ExpanderPhy\n")); + dmhexdump("dmConfigureRouteTimerCB", (bit8*)pdmSMPDiscover2Resp, sizeof(smpRespDiscover2_t)); + + dmDownStreamDiscover2ExpanderPhy(dmRoot, onePortContext, oneExpander, pdmSMPDiscover2Resp); + } + else + { + DM_DBG2(("dmConfigureRouteTimerCB: setting timer again\n")); + /* set the timer again */ + dmSetTimerRequest( + dmRoot, + &discovery->configureRouteTimer, + CONFIGURE_ROUTE_TIMER_VALUE/dmAllShared->usecsPerTick, + dmConfigureRouteTimerCB, + (void *)onePortContext, + (void *)oneExpander, + (void *)pdmSMPDiscover2Resp + ); + + dmAddTimer ( + dmRoot, + &dmAllShared->timerlist, + &discovery->configureRouteTimer + ); + } + } + + return; +} +#endif /* FDS_ DM */ + diff --git a/sys/dev/pms/RefTisa/discovery/dm/dminit.c b/sys/dev/pms/RefTisa/discovery/dm/dminit.c new file mode 100644 index 000000000000..593db3555a58 --- /dev/null +++ b/sys/dev/pms/RefTisa/discovery/dm/dminit.c @@ -0,0 +1,933 @@ +/******************************************************************************* +** +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#include +#include + +#include +#include +#include + +#ifdef FDS_DM +#include +#include +#include + +#include +#include +#include + +#ifdef DM_DEBUG +bit32 gDMDebugLevel = 1; +#endif + +osGLOBAL void +dmGetRequirements( + dmRoot_t *dmRoot, + dmSwConfig_t *swConfig, + dmMemoryRequirement_t *memoryRequirement, + bit32 *usecsPerTick, + bit32 *maxNumLocks) +{ + bit32 memoryReqCount = 0; + bit32 max_expander = DM_MAX_EXPANDER_DEV; + char *buffer; + bit32 buffLen; + bit32 lenRecv = 0; + static char tmpBuffer[DEFAULT_KEY_BUFFER_SIZE]; + char *pLastUsedChar = agNULL; + char globalStr[] = "Global"; + char iniParmsStr[] = "InitiatorParms"; + char SwParmsStr[] = "SWParms"; + + DM_DBG3(("dmGetRequirements: start\n")); + /* sanity check */ + DM_ASSERT((agNULL != swConfig), ""); + DM_ASSERT((agNULL != memoryRequirement), ""); + DM_ASSERT((agNULL != usecsPerTick), ""); + DM_ASSERT((agNULL != maxNumLocks), ""); + + /* memory requirement for dmRoot, CACHE memory */ + memoryRequirement->dmMemory[DM_ROOT_MEM_INDEX].singleElementLength = sizeof(dmIntRoot_t); + memoryRequirement->dmMemory[DM_ROOT_MEM_INDEX].numElements = 1; + memoryRequirement->dmMemory[DM_ROOT_MEM_INDEX].totalLength = + (memoryRequirement->dmMemory[DM_ROOT_MEM_INDEX].singleElementLength) * (memoryRequirement->dmMemory[DM_ROOT_MEM_INDEX].numElements); + memoryRequirement->dmMemory[DM_ROOT_MEM_INDEX].alignment = 4; + memoryRequirement->dmMemory[DM_ROOT_MEM_INDEX].type = DM_CACHED_MEM; + memoryReqCount++; + + /* memory requirement for Port Context Links, CACHE memory */ + memoryRequirement->dmMemory[DM_PORT_MEM_INDEX].singleElementLength = sizeof(dmIntPortContext_t); + memoryRequirement->dmMemory[DM_PORT_MEM_INDEX].numElements = DM_MAX_PORT_CONTEXT; + memoryRequirement->dmMemory[DM_PORT_MEM_INDEX].totalLength = + (memoryRequirement->dmMemory[DM_PORT_MEM_INDEX].singleElementLength) * (memoryRequirement->dmMemory[DM_PORT_MEM_INDEX].numElements); + memoryRequirement->dmMemory[DM_PORT_MEM_INDEX].alignment = 4; + memoryRequirement->dmMemory[DM_PORT_MEM_INDEX].type = DM_CACHED_MEM; + memoryReqCount++; + + /* memory requirement for Device Links, CACHE memory */ + memoryRequirement->dmMemory[DM_DEVICE_MEM_INDEX].singleElementLength = sizeof(dmDeviceData_t); + memoryRequirement->dmMemory[DM_DEVICE_MEM_INDEX].numElements = DM_MAX_DEV; + memoryRequirement->dmMemory[DM_DEVICE_MEM_INDEX].totalLength = + (memoryRequirement->dmMemory[DM_DEVICE_MEM_INDEX].singleElementLength) * (memoryRequirement->dmMemory[DM_DEVICE_MEM_INDEX].numElements); + memoryRequirement->dmMemory[DM_DEVICE_MEM_INDEX].alignment = 4; + memoryRequirement->dmMemory[DM_DEVICE_MEM_INDEX].type = DM_CACHED_MEM; + memoryReqCount++; + + /* memory requirement for Expander Device Links, CACHE memory */ + /* + Maximum number of expanders are configurable + The default is DM_MAX_EXPANDER_DEV + */ + buffer = tmpBuffer; + buffLen = sizeof(tmpBuffer); + + dm_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((tddmGetTransportParam( + dmRoot, + globalStr, + iniParmsStr, + agNULL, + agNULL, + agNULL, + agNULL, + "MaxExpanders", + buffer, + buffLen, + &lenRecv + ) == DM_RC_SUCCESS) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + max_expander = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + max_expander = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + DM_DBG3(("dmGetRequirements: max_expander %d\n", max_expander)); + + + memoryRequirement->dmMemory[DM_EXPANDER_MEM_INDEX].singleElementLength = sizeof(dmExpander_t); + memoryRequirement->dmMemory[DM_EXPANDER_MEM_INDEX].numElements = max_expander; + memoryRequirement->dmMemory[DM_EXPANDER_MEM_INDEX].totalLength = + (memoryRequirement->dmMemory[DM_EXPANDER_MEM_INDEX].singleElementLength) * (memoryRequirement->dmMemory[DM_EXPANDER_MEM_INDEX].numElements); + memoryRequirement->dmMemory[DM_EXPANDER_MEM_INDEX].alignment = 4; + memoryRequirement->dmMemory[DM_EXPANDER_MEM_INDEX].type = DM_CACHED_MEM; + memoryReqCount++; + + /* memory requirement for SMP command Links, CACHE memory */ + memoryRequirement->dmMemory[DM_SMP_MEM_INDEX].singleElementLength = sizeof(dmSMPRequestBody_t); + memoryRequirement->dmMemory[DM_SMP_MEM_INDEX].numElements = DM_MAX_SMP; + memoryRequirement->dmMemory[DM_SMP_MEM_INDEX].totalLength = + (memoryRequirement->dmMemory[DM_SMP_MEM_INDEX].singleElementLength) * (memoryRequirement->dmMemory[DM_SMP_MEM_INDEX].numElements); + memoryRequirement->dmMemory[DM_SMP_MEM_INDEX].alignment = 4; + memoryRequirement->dmMemory[DM_SMP_MEM_INDEX].type = DM_CACHED_MEM; + memoryReqCount++; + + /* memory requirement for INDIRECT SMP command/response Links, DMA memory */ + memoryRequirement->dmMemory[DM_INDIRECT_SMP_MEM_INDEX].singleElementLength = SMP_INDIRECT_PAYLOAD; /* 512 */ + memoryRequirement->dmMemory[DM_INDIRECT_SMP_MEM_INDEX].numElements = DM_MAX_INDIRECT_SMP; + memoryRequirement->dmMemory[DM_INDIRECT_SMP_MEM_INDEX].totalLength = + (memoryRequirement->dmMemory[DM_INDIRECT_SMP_MEM_INDEX].singleElementLength) * (memoryRequirement->dmMemory[DM_INDIRECT_SMP_MEM_INDEX].numElements); + memoryRequirement->dmMemory[DM_INDIRECT_SMP_MEM_INDEX].alignment = 4; + memoryRequirement->dmMemory[DM_INDIRECT_SMP_MEM_INDEX].type = DM_DMA_MEM; + memoryReqCount++; + + + /* set up memory requirement count */ + memoryRequirement->count = memoryReqCount; + + /* requirement for locks */ + *maxNumLocks = DM_MAX_LOCKS; + + /* setup the time tick */ + *usecsPerTick = DM_USECS_PER_TICK; + + + /* set up the number of Expander device handles */ + swConfig->numDevHandles = DM_MAX_DEV; + swConfig->itNexusTimeout = IT_NEXUS_TIMEOUT; /* default is 2000 ms*/ + + dm_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((tddmGetTransportParam( + dmRoot, + globalStr, + SwParmsStr, + agNULL, + agNULL, + agNULL, + agNULL, + "IT_NEXUS_TIMEOUT", + buffer, + buffLen, + &lenRecv + ) == DM_RC_SUCCESS) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + swConfig->itNexusTimeout = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + swConfig->itNexusTimeout = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + + DM_DBG1(("dmGetRequirements: swConfig->itNexusTimeout 0x%X\n", swConfig->itNexusTimeout)); + + DM_DBG3(("dmGetRequirements: memoryReqCount %d\n", memoryRequirement->count)); + + return; +} +/* + ??? processing swConfig +*/ +osGLOBAL bit32 +dmInitialize( + dmRoot_t *dmRoot, + agsaRoot_t *agRoot, + dmMemoryRequirement_t *memoryAllocated, + dmSwConfig_t *swConfig, + bit32 usecsPerTick ) +{ + dmIntRoot_t *dmIntRoot; + dmIntPortContext_t *dmIntPortContext; + dmDeviceData_t *dmDevice; + dmExpander_t *dmExpander; + dmSMPRequestBody_t *dmSMPRequest; + bit8 *dmIndirectSMPRequest; + dmIntContext_t *dmAllShared; + bit32 i; + bit32 max_expander = DM_MAX_EXPANDER_DEV; + char *buffer; + bit32 buffLen; + bit32 lenRecv = 0; + static char tmpBuffer[DEFAULT_KEY_BUFFER_SIZE]; + char *pLastUsedChar = agNULL; + char globalStr[] = "Global"; + char iniParmsStr[] = "InitiatorParms"; + char SwParmsStr[] = "SWParms"; + + DM_DBG3(("dmInitialize: start\n")); + /* sanity check */ + DM_ASSERT((agNULL != dmRoot), ""); + DM_ASSERT((agNULL != agRoot), ""); + DM_ASSERT((agNULL != memoryAllocated), ""); + DM_ASSERT((agNULL != swConfig), ""); + DM_ASSERT((DM_ROOT_MEM_INDEX < memoryAllocated->count), ""); + DM_ASSERT((DM_PORT_MEM_INDEX < memoryAllocated->count), ""); + DM_ASSERT((DM_DEVICE_MEM_INDEX < memoryAllocated->count), ""); + DM_ASSERT((DM_EXPANDER_MEM_INDEX < memoryAllocated->count), ""); + DM_ASSERT((DM_SMP_MEM_INDEX < memoryAllocated->count), ""); + DM_ASSERT((DM_INDIRECT_SMP_MEM_INDEX < memoryAllocated->count), ""); + + /* Check the memory allocated */ + for ( i = 0; i < memoryAllocated->count; i ++ ) + { + /* If memory allocatation failed */ + if (memoryAllocated->dmMemory[i].singleElementLength && + memoryAllocated->dmMemory[i].numElements) + { + if ( (0 != memoryAllocated->dmMemory[i].numElements) + && (0 == memoryAllocated->dmMemory[i].totalLength) ) + { + /* return failure */ + DM_DBG1(("dmInitialize: Memory[%d] singleElementLength = 0x%0x numElements = 0x%x NOT allocated!!!\n", + i, + memoryAllocated->dmMemory[i].singleElementLength, + memoryAllocated->dmMemory[i].numElements)); + return DM_RC_FAILURE; + } + } + } + + /* DM's internal root */ + dmIntRoot = (dmIntRoot_t *) (memoryAllocated->dmMemory[DM_ROOT_MEM_INDEX].virtPtr); + dmRoot->dmData = (void *) dmIntRoot; + + dmAllShared = (dmIntContext_t *)&(dmIntRoot->dmAllShared); + /**< Initialize the TDM data part of the interrupt context */ + dmAllShared->dmRootOsData.dmRoot = dmRoot; + dmAllShared->dmRootOsData.dmAllShared = (void *) dmAllShared; + + /* Port Contexts */ + dmIntPortContext = (dmIntPortContext_t *) (memoryAllocated->dmMemory[DM_PORT_MEM_INDEX].virtPtr); + dmAllShared->PortContextMem = (dmIntPortContext_t *)dmIntPortContext; + + /* Devices */ + dmDevice = (dmDeviceData_t *) (memoryAllocated->dmMemory[DM_DEVICE_MEM_INDEX].virtPtr); + dmAllShared->DeviceMem = (dmDeviceData_t *)dmDevice; + + /* Expanders */ + dmExpander = (dmExpander_t *) (memoryAllocated->dmMemory[DM_EXPANDER_MEM_INDEX].virtPtr); + dmAllShared->ExpanderMem = (dmExpander_t *)dmExpander; + + /* SMP commands */ + dmSMPRequest = (dmSMPRequestBody_t *) (memoryAllocated->dmMemory[DM_SMP_MEM_INDEX].virtPtr); + dmAllShared->SMPMem = (dmSMPRequestBody_t *)dmSMPRequest; + + /* DMAable SMP request/reponse pointed by dmSMPRequestBody_t */ + dmIndirectSMPRequest = (bit8 *) (memoryAllocated->dmMemory[DM_INDIRECT_SMP_MEM_INDEX].virtPtr); + dmAllShared->IndirectSMPMem = (bit8 *)dmIndirectSMPRequest; + dmAllShared->IndirectSMPUpper32 = memoryAllocated->dmMemory[DM_INDIRECT_SMP_MEM_INDEX].physAddrUpper; + dmAllShared->IndirectSMPLower32 = memoryAllocated->dmMemory[DM_INDIRECT_SMP_MEM_INDEX].physAddrLower; + + dmAllShared->agRoot = agRoot; + + + dmAllShared->usecsPerTick = usecsPerTick; + dmAllShared->itNexusTimeout = IT_NEXUS_TIMEOUT;/*swConfig->itNexusTimeout;*/ + dmAllShared->MaxRetryDiscovery = DISCOVERY_RETRIES; + dmAllShared->RateAdjust = 0; + /**< initializes timers */ + dmInitTimers(dmRoot); + + /**< initializes port contexts */ + dmPortContextInit(dmRoot); + + /**< initializes devices */ + dmDeviceDataInit(dmRoot); + + /**< initializes expander devices */ + buffer = tmpBuffer; + buffLen = sizeof(tmpBuffer); + + dm_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((tddmGetTransportParam( + dmRoot, + globalStr, + iniParmsStr, + agNULL, + agNULL, + agNULL, + agNULL, + "MaxExpanders", + buffer, + buffLen, + &lenRecv + ) == DM_RC_SUCCESS) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + max_expander = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + max_expander = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + + dm_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((tddmGetTransportParam( + dmRoot, + globalStr, + SwParmsStr, + agNULL, + agNULL, + agNULL, + agNULL, + "IT_NEXUS_TIMEOUT", + buffer, + buffLen, + &lenRecv + ) == DM_RC_SUCCESS) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + dmAllShared->itNexusTimeout = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + dmAllShared->itNexusTimeout = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + + DM_DBG1(("dmAllShared->itNexusTimeout %d \n", dmAllShared->itNexusTimeout)); + + dm_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((tddmGetTransportParam( + dmRoot, + globalStr, + SwParmsStr, + agNULL, + agNULL, + agNULL, + agNULL, + "MaxRetryDiscovery", + buffer, + buffLen, + &lenRecv + ) == DM_RC_SUCCESS) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + dmAllShared->MaxRetryDiscovery = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + dmAllShared->MaxRetryDiscovery = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + + DM_DBG1(("dmAllShared->MaxRetryDiscovery %d \n", dmAllShared->MaxRetryDiscovery)); + + dm_memset(buffer, 0, buffLen); + lenRecv = 0; + if ((tddmGetTransportParam( + dmRoot, + globalStr, + SwParmsStr, + agNULL, + agNULL, + agNULL, + agNULL, + "RateAdjust", + buffer, + buffLen, + &lenRecv + ) == DM_RC_SUCCESS) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + dmAllShared->RateAdjust = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + dmAllShared->RateAdjust = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + DM_DBG1(("dmAllShared->RateAdjust %d \n", dmAllShared->RateAdjust)); + + dmExpanderDeviceDataInit(dmRoot, max_expander); + + /**< initializes SMP commands */ + dmSMPInit(dmRoot); + +#ifdef DM_DEBUG + gDMDebugLevel = swConfig->DMDebugLevel; +#endif + return DM_RC_SUCCESS; +} + +osGLOBAL void +dmSMPInit( + dmRoot_t *dmRoot + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmSMPRequestBody_t *dmSMPCommand = (dmSMPRequestBody_t *)dmAllShared->SMPMem; + bit8 *dmIndirectSMPReqRsp = (bit8 *)dmAllShared->IndirectSMPMem; + bit32 prev_PhysAddrLower; + + int i = 0; + DM_DBG3(("dmSMPInit: start \n")); + + DMLIST_INIT_HDR(&(dmAllShared->freeSMPList)); + + for(i=0;iIndirectSMPUpper32; + dmSMPCommand[i].IndirectSMPLower32 = dmAllShared->IndirectSMPLower32; + + prev_PhysAddrLower = dmAllShared->IndirectSMPLower32; + dmAllShared->IndirectSMPLower32 = dmAllShared->IndirectSMPLower32 + SMP_INDIRECT_PAYLOAD; + if (dmAllShared->IndirectSMPLower32 <= prev_PhysAddrLower) + { + dmAllShared->IndirectSMPUpper32++; + } + + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPCommand[i].Link), &(dmAllShared->freeSMPList)); + } + return; + +} + +osGLOBAL void +dmDeviceDataInit( + dmRoot_t *dmRoot + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmDeviceData_t *dmDeviceData = (dmDeviceData_t *)dmAllShared->DeviceMem; + int i; + + DM_DBG3(("dmDeviceDataInit: start \n")); + + DMLIST_INIT_HDR(&(dmAllShared->MainDeviceList)); + DMLIST_INIT_HDR(&(dmAllShared->FreeDeviceList)); + + for(i=0;iFreeDeviceList)); + } + + return; +} +osGLOBAL void +dmDeviceDataReInit( + dmRoot_t *dmRoot, + dmDeviceData_t *oneDeviceData + ) +{ + DM_DBG3(("dmDeviceDataReInit: start \n")); + + oneDeviceData->DeviceType = DM_DEFAULT_DEVICE; +// oneDeviceData->agDevHandle = agNULL; + + oneDeviceData->dmPortContext = agNULL; + oneDeviceData->dmExpander = agNULL; + oneDeviceData->ExpDevice = agNULL; + oneDeviceData->phyID = 0xFF; + oneDeviceData->SASAddressID.sasAddressHi = 0; + oneDeviceData->SASAddressID.sasAddressLo = 0; + oneDeviceData->valid = agFALSE; + oneDeviceData->valid2 = agFALSE; + oneDeviceData->processed = agFALSE; + oneDeviceData->initiator_ssp_stp_smp = 0; + oneDeviceData->target_ssp_stp_smp = 0; + oneDeviceData->numOfPhys = 0; +// oneDeviceData->registered = agFALSE; + oneDeviceData->directlyAttached = agFALSE; + oneDeviceData->SASSpecDeviceType = 0xFF; + oneDeviceData->IOStart = 0; + oneDeviceData->IOResponse = 0; + oneDeviceData->agDeviceResetContext.osData = agNULL; + oneDeviceData->agDeviceResetContext.sdkData = agNULL; + oneDeviceData->TRflag = agFALSE; + oneDeviceData->ResetCnt = 0; + oneDeviceData->registered = agFALSE; + oneDeviceData->reported = agFALSE; + + oneDeviceData->MCN = 0; + oneDeviceData->MCNDone = agFALSE; + oneDeviceData->PrevMCN = 0; + + dm_memset( &(oneDeviceData->dmDeviceInfo), 0, sizeof(dmDeviceInfo_t)); + + return; +} + + +osGLOBAL void +dmExpanderDeviceDataInit( + dmRoot_t *dmRoot, + bit32 max_exp + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmExpander_t *dmExpData = (dmExpander_t *)dmAllShared->ExpanderMem; + bit32 i = 0; + DM_DBG3(("dmExpanderDeviceDataInit: start \n")); + + DMLIST_INIT_HDR(&(dmAllShared->freeExpanderList)); + DMLIST_INIT_HDR(&(dmAllShared->mainExpanderList)); + + for(i=0;ifreeExpanderList)); + } + return; +} + +/* re-intialize an expander */ +osGLOBAL void +dmExpanderDeviceDataReInit( + dmRoot_t *dmRoot, + dmExpander_t *oneExpander + ) +{ + DM_DBG3(("dmExpanderDeviceDataReInit: start \n")); + oneExpander->dmRoot = agNULL; + oneExpander->agDevHandle = agNULL; + oneExpander->dmDevice = agNULL; + oneExpander->dmUpStreamExpander = agNULL; + oneExpander->dmCurrentDownStreamExpander = agNULL; + oneExpander->hasUpStreamDevice = agFALSE; + oneExpander->numOfUpStreamPhys = 0; + oneExpander->currentUpStreamPhyIndex = 0; + oneExpander->numOfDownStreamPhys = 0; + oneExpander->currentDownStreamPhyIndex = 0; + oneExpander->discoveringPhyId = 0; + oneExpander->underDiscovering = agFALSE; + oneExpander->dmReturnginExpander = agNULL; + oneExpander->discoverSMPAllowed = agTRUE; + dm_memset( &(oneExpander->currentIndex), 0, sizeof(oneExpander->currentIndex)); + dm_memset( &(oneExpander->upStreamPhys), 0, sizeof(oneExpander->upStreamPhys)); + dm_memset( &(oneExpander->downStreamPhys), 0, sizeof(oneExpander->downStreamPhys)); + dm_memset( &(oneExpander->routingAttribute), 0, sizeof(oneExpander->routingAttribute)); + oneExpander->configSASAddrTableIndex = 0; + dm_memset( &(oneExpander->configSASAddressHiTable), 0, sizeof(oneExpander->configSASAddressHiTable)); + dm_memset( &(oneExpander->configSASAddressLoTable), 0, sizeof(oneExpander->configSASAddressLoTable)); + oneExpander->SAS2 = 0; /* default is SAS 1.1 spec */ + oneExpander->TTTSupported = agFALSE; /* Table to Table is supported */ + oneExpander->UndoDueToTTTSupported = agFALSE; + + return; +} + +osGLOBAL void +dmPortContextInit( + dmRoot_t *dmRoot + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmIntPortContext_t *dmPortContext = (dmIntPortContext_t *)dmAllShared->PortContextMem; + int i = 0; +#ifdef TBD + int j = 0; +#endif + + DM_DBG3(("dmPortContextInit: start \n")); + + DMLIST_INIT_HDR(&(dmAllShared->MainPortContextList)); + DMLIST_INIT_HDR(&(dmAllShared->FreePortContextList)); + for(i=0;iFreePortContextList)); + } + +#ifdef DM_INTERNAL_DEBUG /* for debugging only */ + for(i=0;idiscovery); + + onePortContext->discovery.type = DM_DISCOVERY_OPTION_FULL_START; + onePortContext->discovery.retries = 0; + onePortContext->discovery.configureRouteRetries = 0; + onePortContext->discovery.deviceRetistrationRetries = 0; + onePortContext->discovery.pendingSMP = 0; + onePortContext->discovery.SeenBC = agFALSE; + onePortContext->discovery.forcedOK = agFALSE; + onePortContext->discovery.SMPRetries = 0; + onePortContext->discovery.DeferredError = agFALSE; + onePortContext->discovery.ConfiguresOthers = agFALSE; + onePortContext->discovery.ResetTriggerred = agFALSE; + + /* free expander lists */ + dmCleanAllExp(dmRoot, onePortContext); + + /* kill the discovery-related timers if they are running */ + tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK); + if (discovery->discoveryTimer.timerRunning == agTRUE) + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + dmKillTimer( + dmRoot, + &discovery->discoveryTimer + ); + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + } + + + tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK); + if (discovery->configureRouteTimer.timerRunning == agTRUE) + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + dmKillTimer( + dmRoot, + &discovery->configureRouteTimer + ); + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + } + + + tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK); + if (discovery->deviceRegistrationTimer.timerRunning == agTRUE) + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + dmKillTimer( + dmRoot, + &discovery->deviceRegistrationTimer + ); + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + } + + + tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK); + if (discovery->BCTimer.timerRunning == agTRUE) + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + dmKillTimer( + dmRoot, + &discovery->BCTimer + ); + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + } + + + tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK); + if (discovery->SMPBusyTimer.timerRunning == agTRUE) + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + dmKillTimer( + dmRoot, + &discovery->SMPBusyTimer + ); + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + } + + + tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK); + if (discovery->DiscoverySMPTimer.timerRunning == agTRUE) + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + dmKillTimer( + dmRoot, + &discovery->DiscoverySMPTimer + ); + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + } + + onePortContext->DiscoveryState = DM_DSTATE_NOT_STARTED; + onePortContext->DiscoveryAbortInProgress = agFALSE; + onePortContext->directAttatchedSAS = agFALSE; + onePortContext->DiscoveryRdyGiven = agFALSE; + onePortContext->SeenLinkUp = agFALSE; + + onePortContext->dmPortContext->dmData = agNULL; + onePortContext->dmPortContext = agNULL; + onePortContext->dmRoot = agNULL; + + onePortContext->LinkRate = 0; + onePortContext->Count = 0; + onePortContext->valid = agFALSE; + onePortContext->RegisteredDevNums = 0; + onePortContext->eventPhyID = 0xFF; + onePortContext->Transient = agFALSE; + + return; +} + + +osGLOBAL void +dmInitTimers( + dmRoot_t *dmRoot + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + +#ifdef DM_DEBUG_ENABLE + dmIntPortContext_t *dmPortContext = (dmIntPortContext_t *)dmAllShared->PortContextMem; + + DM_DBG6(("dmInitTimers: start \n")); + DM_DBG6(("dmInitTimers: ******* tdsaRoot %p \n", dmIntRoot)); + DM_DBG6(("dmInitTimers: ******* tdsaPortContext %p \n",dmPortContext)); +#endif + + /* initialize the timerlist */ + DMLIST_INIT_HDR(&(dmAllShared->timerlist)); + + return; +} +#endif /* FDS_ DM */ + + diff --git a/sys/dev/pms/RefTisa/discovery/dm/dmlist.h b/sys/dev/pms/RefTisa/discovery/dm/dmlist.h new file mode 100644 index 000000000000..ffeaa6e78e3a --- /dev/null +++ b/sys/dev/pms/RefTisa/discovery/dm/dmlist.h @@ -0,0 +1,161 @@ +/******************************************************************************* +** +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ + +#ifndef __DMLIST_H__ +#define __DMLIST_H__ + +typedef struct dmList_s dmList_t; + +struct dmList_s { + dmList_t *flink; + dmList_t *blink; +}; + +#define DMLIST_INIT_HDR(hdr) \ + do { \ + ((dmList_t *)(hdr))->flink = (dmList_t *)(hdr); \ + ((dmList_t *)(hdr))->blink = (dmList_t *)(hdr); \ + } while (0) + +#define DMLIST_INIT_ELEMENT(hdr) \ + do { \ + ((dmList_t *)(hdr))->flink = (dmList_t *)agNULL; \ + ((dmList_t *)(hdr))->blink = (dmList_t *)agNULL; \ + } while (0) + +#define DMLIST_ENQUEUE_AT_HEAD(toAddHdr,listHdr) \ + do { \ + ((dmList_t *)(toAddHdr))->flink = ((dmList_t *)(listHdr))->flink; \ + ((dmList_t *)(toAddHdr))->blink = (dmList_t *)(listHdr) ; \ + ((dmList_t *)(listHdr))->flink->blink = (dmList_t *)(toAddHdr); \ + ((dmList_t *)(listHdr))->flink = (dmList_t *)(toAddHdr); \ + } while (0) + +#define DMLIST_ENQUEUE_AT_TAIL(toAddHdr,listHdr) \ + do { \ + ((dmList_t *)(toAddHdr))->flink = (dmList_t *)(listHdr); \ + ((dmList_t *)(toAddHdr))->blink = ((dmList_t *)(listHdr))->blink; \ + ((dmList_t *)(listHdr))->blink->flink = (dmList_t *)(toAddHdr); \ + ((dmList_t *)(listHdr))->blink = (dmList_t *)(toAddHdr); \ + } while (0) + +#define DMLIST_EMPTY(listHdr) \ + (((dmList_t *)(listHdr))->flink == ((dmList_t *)(listHdr))) + +#define DMLIST_NOT_EMPTY(listHdr) \ + (!DMLIST_EMPTY(listHdr)) + +#define DMLIST_DEQUEUE_THIS(hdr) \ + do { \ + ((dmList_t *)(hdr))->blink->flink = ((dmList_t *)(hdr))->flink; \ + ((dmList_t *)(hdr))->flink->blink = ((dmList_t *)(hdr))->blink; \ + ((dmList_t *)(hdr))->flink = ((dmList_t *)(hdr))->blink = agNULL; \ + } while (0) + +#define DMLIST_DEQUEUE_FROM_HEAD_FAST(atHeadHdr,listHdr) \ + do { \ + *((dmList_t **)(atHeadHdr)) = ((dmList_t *)(listHdr))->flink; \ + (*((dmList_t **)(atHeadHdr)))->flink->blink = (dmList_t *)(listHdr); \ + ((dmList_t *)(listHdr))->flink = (*(dmList_t **)(atHeadHdr))->flink; \ + } while (0) + +#define DMLIST_DEQUEUE_FROM_HEAD(atHeadHdr,listHdr) \ +do { \ + if (DMLIST_NOT_EMPTY((listHdr))) \ + { \ + DMLIST_DEQUEUE_FROM_HEAD_FAST(atHeadHdr,listHdr); \ + } \ + else \ + { \ + (*((dmList_t **)(atHeadHdr))) = (dmList_t *)agNULL; \ + } \ +} while (0) + +#define DMLIST_DEQUEUE_FROM_TAIL_FAST(atTailHdr,listHdr) \ + do { \ + (*((dmList_t **)(atTailHdr))) = ((dmList_t *)(listHdr))->blink; \ + (*((dmList_t **)(atTailHdr)))->blink->flink = (dmList_t *)(listHdr); \ + ((dmList_t *)(listHdr))->blink = (*((dmList_t **)(atTailHdr)))->blink; \ + } while (0) + +#define DMLIST_DEQUEUE_FROM_TAIL(atTailHdr,listHdr) \ + do { \ + if (DMLIST_NOT_EMPTY((listHdr))) \ + { \ + DMLIST_DEQUEUE_FROM_TAIL_FAST(atTailHdr,listHdr); \ + } \ + else \ + { \ + (*((dmList_t **)(atTailHdr))) = (dmList_t *)agNULL; \ + } \ + } while (0) + +#define DMLIST_ENQUEUE_LIST_AT_TAIL_FAST(toAddListHdr, listHdr) \ + do { \ + ((dmList_t *)toAddListHdr)->blink->flink = ((dmList_t *)listHdr); \ + ((dmList_t *)toAddListHdr)->flink->blink = ((dmList_t *)listHdr)->blink; \ + ((dmList_t *)listHdr)->blink->flink = ((dmList_t *)toAddListHdr)->flink; \ + ((dmList_t *)listHdr)->blink = ((dmList_t *)toAddListHdr)->blink; \ + DMLIST_INIT_HDR(toAddListHdr); \ + } while (0) + +#define DMLIST_ENQUEUE_LIST_AT_TAIL(toAddListHdr, listHdr) \ + do { \ + if (DMLIST_NOT_EMPTY(toAddListHdr)) \ + { \ + DMLIST_ENQUEUE_LIST_AT_TAIL_FAST(toAddListHdr, listHdr); \ + } \ + } while (0) + +#define DMLIST_ENQUEUE_LIST_AT_HEAD_FAST(toAddListHdr, listHdr) \ + do { \ + ((dmList_t *)toAddListHdr)->blink->flink = ((dmList_t *)listHdr)->flink; \ + ((dmList_t *)toAddListHdr)->flink->blink = ((dmList_t *)listHdr); \ + ((dmList_t *)listHdr)->flink->blink = ((dmList_t *)toAddListHdr)->blink; \ + ((dmList_t *)listHdr)->flink = ((dmList_t *)toAddListHdr)->flink; \ + DMLIST_INIT_HDR(toAddListHdr); \ + } while (0) + +#define DMLIST_ENQUEUE_LIST_AT_HEAD(toAddListHdr, listHdr) \ + do { \ + if (DMLIST_NOT_EMPTY(toAddListHdr)) \ + { \ + DMLIST_ENQUEUE_LIST_AT_HEAD_FAST(toAddListHdr, listHdr); \ + } \ + } while (0) + +#define TD_FIELD_OFFSET(baseType,fieldName) \ + ((bit32)((bitptr)(&(((baseType *)0)->fieldName)))) + +#define DMLIST_OBJECT_BASE(baseType,fieldName,fieldPtr) \ + (void *)fieldPtr == (void *)0 ? (baseType *)0 : \ + ((baseType *)((bit8 *)(fieldPtr) - ((bitptr)(&(((baseType *)0)->fieldName))))) + + + + +#endif /* __DMLIST_H__ */ + + diff --git a/sys/dev/pms/RefTisa/discovery/dm/dmmisc.c b/sys/dev/pms/RefTisa/discovery/dm/dmmisc.c new file mode 100644 index 000000000000..7ac730b85d55 --- /dev/null +++ b/sys/dev/pms/RefTisa/discovery/dm/dmmisc.c @@ -0,0 +1,98 @@ +/******************************************************************************* +** +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#include +#include + +#include +#include +#include + +#ifdef FDS_DM +#include +#include +#include + +#include +#include +#include + +osGLOBAL void +*dm_memset(void *s, int c, bit32 n) +{ + bit32 i; + + char *dst = (char *)s; + for (i=0; i < n; i++) + { + dst[i] = (char) c; + } + return (void *)(&dst[i-n]); +} + +osGLOBAL void +*dm_memcpy(void *dst, void *src, bit32 count) +{ + bit32 x; + unsigned char *dst1 = (unsigned char *)dst; + unsigned char *src1 = (unsigned char *)src; + + for (x=0; x < count; x++) + dst1[x] = src1[x]; + + return dst; + +} + +/** hexidecimal dump */ +osGLOBAL void +dmhexdump(const char *ptitle, bit8 *pbuf, int len) +{ + int i; + DM_DBG1(("%s - dmhexdump(len=%d):\n", ptitle, (int)len)); + if (!pbuf) + { + DM_DBG1(("pbuf is NULL\n")); + return; + } + for (i = 0; i < len; ) + { + if (len - i > 4) + { + DM_DBG1((" 0x%02x, 0x%02x, 0x%02x, 0x%02x,\n", pbuf[i], pbuf[i+1], pbuf[i+2], pbuf[i+3])); + i += 4; + } + else + { + DM_DBG1((" 0x%02x,", pbuf[i])); + i++; + } + } + DM_DBG1(("\n")); +} +#endif /* FDS_ DM */ + diff --git a/sys/dev/pms/RefTisa/discovery/dm/dmport.c b/sys/dev/pms/RefTisa/discovery/dm/dmport.c new file mode 100644 index 000000000000..962d1326178e --- /dev/null +++ b/sys/dev/pms/RefTisa/discovery/dm/dmport.c @@ -0,0 +1,304 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#include +#include + +#include +#include +#include + +#ifdef FDS_DM +#include +#include +#include + +#include +#include +#include + +/*****************************************************************************/ +/*! \brief dmCreatePort + * + * + * Purpose: A port context is created by this function + * + * \param dmRoot: DM context handle. + * \param dmPortContext: Pointer to this instance of port context + * + * \return: + * DM_RC_SUCCESS + * DM_RC_FAILURE + * + */ +/*****************************************************************************/ +osGLOBAL bit32 +dmCreatePort( + dmRoot_t *dmRoot, + dmPortContext_t *dmPortContext, + dmPortInfo_t *dmPortInfo) +{ + dmIntRoot_t *dmIntRoot = agNULL; + dmIntContext_t *dmAllShared = agNULL; + dmIntPortContext_t *onePortContext = agNULL; + dmList_t *PortContextList = agNULL; + + DM_DBG3(("dmCreatePort: start\n")); + + if (dmRoot == agNULL) + { + DM_DBG1(("dmCreatePort: dmRoot is NULL, wrong!!!\n")); + return DM_RC_FAILURE; + } + + if (dmPortContext == agNULL) + { + DM_DBG1(("dmCreatePort: dmPortContext is NULL, wrong!!!\n")); + return DM_RC_FAILURE; + } + + /* the duplicacy of a port is checked */ + if (dmPortContext->dmData != agNULL) + { + DM_DBG1(("dmCreatePort: dmPortContext->dmData is not NULL, wrong, Already created!!!\n")); + return DM_RC_FAILURE; + } + + if (dmPortInfo == agNULL) + { + DM_DBG1(("dmCreatePort: dmPortInfo is NULL, wrong!!!\n")); + return DM_RC_FAILURE; + } + + dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + + if (dmIntRoot == agNULL) + { + DM_DBG1(("dmCreatePort: dmIntRoot is NULL, wrong!!!\n")); + return DM_RC_FAILURE; + } + + dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + + if (dmAllShared == agNULL) + { + DM_DBG1(("dmCreatePort: dmAllShared is NULL, wrong!!!\n")); + return DM_RC_FAILURE; + } + + tddmSingleThreadedEnter(dmRoot, DM_PORT_LOCK); + if (DMLIST_NOT_EMPTY(&(dmAllShared->FreePortContextList))) + { + DMLIST_DEQUEUE_FROM_HEAD(&PortContextList, &(dmAllShared->FreePortContextList)); + tddmSingleThreadedLeave(dmRoot, DM_PORT_LOCK); + onePortContext = DMLIST_OBJECT_BASE(dmIntPortContext_t, FreeLink, PortContextList); + if (onePortContext == agNULL) + { + DM_DBG1(("dmCreatePort: onePortContext is NULL in allocation, wrong!!!\n")); + return DM_RC_FAILURE; + } + + dmPortContext->dmData = onePortContext; + onePortContext->DiscoveryState = DM_DSTATE_NOT_STARTED; + onePortContext->discoveryOptions = DM_DISCOVERY_OPTION_FULL_START; + + onePortContext->dmRoot = dmRoot; + onePortContext->dmPortContext = dmPortContext; + onePortContext->valid = agTRUE; + onePortContext->RegFailed = agFALSE; + + onePortContext->LinkRate = DM_GET_LINK_RATE(dmPortInfo->flag); + DM_DBG3(("dmCreatePort: linkrate %0x\n", onePortContext->LinkRate)); + + onePortContext->sasRemoteAddressHi = DM_GET_SAS_ADDRESSHI(dmPortInfo->sasRemoteAddressHi); + onePortContext->sasRemoteAddressLo = DM_GET_SAS_ADDRESSLO(dmPortInfo->sasRemoteAddressLo); + onePortContext->sasLocalAddressHi = DM_GET_SAS_ADDRESSHI(dmPortInfo->sasLocalAddressHi); + onePortContext->sasLocalAddressLo = DM_GET_SAS_ADDRESSLO(dmPortInfo->sasLocalAddressLo); + DM_DBG3(("dmCreatePort: pid %d\n", onePortContext->id)); + DM_DBG3(("dmCreatePort: RemoteAddrHi 0x%08x RemoteAddrLo 0x%08x\n", onePortContext->sasRemoteAddressHi, onePortContext->sasRemoteAddressLo)); + DM_DBG3(("dmCreatePort: LocalAddrHi 0x%08x LocaAddrLo 0x%08x\n", onePortContext->sasLocalAddressHi, onePortContext->sasLocalAddressLo)); + + tddmSingleThreadedEnter(dmRoot, DM_PORT_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(onePortContext->MainLink), &(dmAllShared->MainPortContextList)); + tddmSingleThreadedLeave(dmRoot, DM_PORT_LOCK); + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_PORT_LOCK); + DM_DBG1(("dmCreatePort: Attention. no more free PortContext!!!\n")); + return DM_RC_FAILURE; + } + + return DM_RC_SUCCESS; +} + +/*****************************************************************************/ +/*! \brief dmDestroyPort + * + * + * Purpose: A port context is destroyed by this function + * + * \param dmRoot: DM context handle. + * \param dmPortContext: Pointer to this instance of port context + * + * \return: + * DM_RC_SUCCESS + * DM_RC_FAILURE + * + */ +/*****************************************************************************/ +osGLOBAL bit32 +dmDestroyPort( + dmRoot_t *dmRoot, + dmPortContext_t *dmPortContext, + dmPortInfo_t *dmPortInfo) +{ + dmIntRoot_t *dmIntRoot = agNULL; + dmIntContext_t *dmAllShared = agNULL; + dmIntPortContext_t *onePortContext = agNULL; + + DM_DBG1(("dmDestroyPort: start\n")); + if (dmRoot == agNULL) + { + DM_DBG1(("dmDestroyPort: dmRoot is NULL, wrong!!!\n")); + return DM_RC_FAILURE; + } + + if (dmPortContext == agNULL) + { + DM_DBG1(("dmDestroyPort: dmPortContext is NULL, wrong!!!\n")); + return DM_RC_FAILURE; + } + + if (dmPortInfo == agNULL) + { + DM_DBG1(("dmDestroyPort: dmPortInfo is NULL, wrong!!!\n")); + return DM_RC_FAILURE; + } + + dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + + if (dmIntRoot == agNULL) + { + DM_DBG1(("dmDestroyPort: dmIntRoot is NULL, wrong!!!\n")); + return DM_RC_FAILURE; + } + + dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + + if (dmAllShared == agNULL) + { + DM_DBG1(("dmDestroyPort: dmAllShared is NULL, wrong!!!\n")); + return DM_RC_FAILURE; + } + + /* + no device(expander) to be removed since all devices should + be in freelist at the end of discovery + But if the discovery is in progress, abort it and clean up + */ + onePortContext = (dmIntPortContext_t *)dmPortContext->dmData; + + if (onePortContext == agNULL) + { + DM_DBG1(("dmDestroyPort: onePortContext is NULL, wrong!!!\n")); + return DM_RC_FAILURE; + } + +#if 1 + if (onePortContext->DiscoveryState != DM_DSTATE_COMPLETED) + { + dmDiscoverAbort(dmRoot, onePortContext); + } + else + { + /* move devices from dmAllShared->MainDeviceList to dmAllShared->FreeDeviceList; dmDiscoveryDeviceCleanUp() + move from dmAllShared->mainExpanderList to dmAllShared->freeExpanderList; dmDiscoveryExpanderCleanUp() + */ + } +#endif + + if (onePortContext->DiscoveryState != DM_DSTATE_COMPLETED) + { + /* move from dmAllShared->discoveringExpanderList to dmAllShared->mainExpanderList + move from dmAllShared->UpdiscoveringExpanderList to dmAllShared->mainExpanderList + */ + dmCleanAllExp(dmRoot, onePortContext); + } + + /* move mainExpanderList then MainDeviceList */ + DM_DBG3(("dmDestroyPort: before dmDiscoveryExpanderCleanUp\n")); + dmDumpAllMainExp(dmRoot, onePortContext); + + /* move from dmAllShared->mainExpanderList to dmAllShared->freeExpanderList */ + dmDiscoveryExpanderCleanUp(dmRoot, onePortContext); + + DM_DBG3(("dmDestroyPort: after dmDiscoveryExpanderCleanUp\n")); + dmDumpAllMainExp(dmRoot, onePortContext); + + DM_DBG3(("dmDestroyPort: before dmDiscoveryDeviceCleanUp\n")); + dmDumpAllMainDevice(dmRoot, onePortContext); + /* move devices from dmAllShared->MainDeviceList to dmAllShared->FreeDeviceList */ + dmDiscoveryDeviceCleanUp(dmRoot, onePortContext); + + DM_DBG3(("dmDestroyPort: after dmDiscoveryDeviceCleanUp\n")); + dmDumpAllMainDevice(dmRoot, onePortContext); + + dmPortContextReInit(dmRoot, onePortContext); + + tddmSingleThreadedEnter(dmRoot, DM_PORT_LOCK); + + if (DMLIST_NOT_EMPTY(&(onePortContext->MainLink))) + { + DMLIST_DEQUEUE_THIS(&(onePortContext->MainLink)); + } + else + { + DM_DBG1(("dmDestroyPort: onePortContext->MainLink is NULL, wrong!!!\n")); + } + + if (DMLIST_NOT_EMPTY(&(onePortContext->FreeLink)) && DMLIST_NOT_EMPTY(&(dmAllShared->FreePortContextList))) + { + DMLIST_ENQUEUE_AT_TAIL(&(onePortContext->FreeLink), &(dmAllShared->FreePortContextList)); + } + else + { + DM_DBG1(("dmDestroyPort: onePortContext->FreeLink or dmAllShared->FreePortContextList is NULL, wrong!!!\n")); + } + + tddmSingleThreadedLeave(dmRoot, DM_PORT_LOCK); + + return DM_RC_SUCCESS; +} +#endif /* FDS_ DM */ + + + + + + + + diff --git a/sys/dev/pms/RefTisa/discovery/dm/dmproto.h b/sys/dev/pms/RefTisa/discovery/dm/dmproto.h new file mode 100644 index 000000000000..7f4252f63dbe --- /dev/null +++ b/sys/dev/pms/RefTisa/discovery/dm/dmproto.h @@ -0,0 +1,833 @@ +/******************************************************************************* +* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +#ifndef __DMPROTO_H__ +#define __DMPROTO_H__ + +#include + +/***************** util ****************************************/ +osGLOBAL void +*dm_memset(void *s, int c, bit32 n); + +osGLOBAL void +*dm_memcpy(void *dst, void *src, bit32 count); + +osGLOBAL void +dmhexdump(const char *ptitle, bit8 *pbuf, int len); + + +/* timer related */ +osGLOBAL void +dmInitTimers( + dmRoot_t *dmRoot + ); +osGLOBAL void +dmInitTimerRequest( + dmRoot_t *dmRoot, + dmTimerRequest_t *timerRequest + ); + +osGLOBAL void +dmSetTimerRequest( + dmRoot_t *dmRoot, + dmTimerRequest_t *timerRequest, + bit32 timeout, + dmTimerCBFunc_t CBFunc, + void *timerData1, + void *timerData2, + void *timerData3 + ); + +osGLOBAL void +dmAddTimer( + dmRoot_t *dmRoot, + dmList_t *timerListHdr, + dmTimerRequest_t *timerRequest + ); + +osGLOBAL void +dmKillTimer( + dmRoot_t *dmRoot, + dmTimerRequest_t *timerRequest + ); + +osGLOBAL void +dmProcessTimers( + dmRoot_t *dmRoot + ); + + + +osGLOBAL void +dmPortContextInit( + dmRoot_t *dmRoot + ); + +osGLOBAL void +dmPortContextReInit( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ); + +osGLOBAL void +dmDeviceDataInit( + dmRoot_t *dmRoot + ); + +osGLOBAL void +dmDeviceDataReInit( + dmRoot_t *dmRoot, + dmDeviceData_t *oneDeviceData + ); + +osGLOBAL void +dmExpanderDeviceDataInit( + dmRoot_t *dmRoot, + bit32 max_exp + ); + +osGLOBAL void +dmExpanderDeviceDataReInit( + dmRoot_t *dmRoot, + dmExpander_t *oneExpander + ); + + +osGLOBAL void +dmSMPInit( + dmRoot_t *dmRoot + ); + + +osGLOBAL bit32 +dmDiscoverCheck( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ); +osGLOBAL void +dmDiscoverAbort( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ); + + +osGLOBAL bit32 +dmFullDiscover( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ); + +osGLOBAL bit32 +dmIncrementalDiscover( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + bit32 flag + ); + +osGLOBAL dmExpander_t * +dmDiscoveringExpanderAlloc( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmDeviceData_t *oneDeviceData + ); +osGLOBAL void +dmDiscoveringExpanderAdd( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmExpander_t *oneExpander + ); + +osGLOBAL void +dmDiscoveringExpanderRemove( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmExpander_t *oneExpander + ); + +osGLOBAL dmExpander_t * +dmExpFind( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + bit32 sasAddrHi, + bit32 sasAddrLo + ); + +osGLOBAL dmExpander_t * +dmExpMainListFind( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + bit32 sasAddrHi, + bit32 sasAddrLo + ); + +osGLOBAL dmDeviceData_t * +dmDeviceFind( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + bit32 sasAddrHi, + bit32 sasAddrLo + ); + +osGLOBAL void +dmUpStreamDiscoverStart( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ); + +osGLOBAL void +dmUpStreamDiscovering( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmDeviceData_t *oneDeviceData + ); + +osGLOBAL void +dmDownStreamDiscovering( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmDeviceData_t *oneDeviceData + ); + +osGLOBAL void +dmDownStreamDiscoverStart( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmDeviceData_t *oneDeviceData + ); + +osGLOBAL void +dmCleanAllExp( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ); + +osGLOBAL void +dmInternalRemovals( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ); +osGLOBAL void +dmDiscoveryResetProcessed( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ); + +osGLOBAL void +dmDiscoverDone( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + bit32 flag + ); + +osGLOBAL void +dmUpStreamDiscoverExpanderPhy( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmExpander_t *oneExpander, + smpRespDiscover_t *pDiscoverResp + ); + +osGLOBAL void +dmUpStreamDiscover2ExpanderPhy( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmExpander_t *oneExpander, + smpRespDiscover2_t *pDiscoverResp + ); + +osGLOBAL void +dmDownStreamDiscoverExpanderPhy( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmExpander_t *oneExpander, + smpRespDiscover_t *pDiscoverResp + ); +osGLOBAL void +dmDownStreamDiscover2ExpanderPhy( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmExpander_t *oneExpander, + smpRespDiscover2_t *pDiscoverResp + ); + +osGLOBAL void +dmUpStreamDiscoverExpanderPhySkip( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmExpander_t *oneExpander + ); + +osGLOBAL void +dmUpStreamDiscover2ExpanderPhySkip( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmExpander_t *oneExpander + ); + +osGLOBAL void +dmDownStreamDiscoverExpanderPhySkip( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmExpander_t *oneExpander + ); +osGLOBAL void +dmDownStreamDiscover2ExpanderPhySkip( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmExpander_t *oneExpander + ); + +osGLOBAL void +dmDiscoveringUndoAdd( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmExpander_t *oneExpander + ); + + +osGLOBAL void +dmExpanderUpStreamPhyAdd( + dmRoot_t *dmRoot, + dmExpander_t *oneExpander, + bit8 phyId + ); + +osGLOBAL void +dmExpanderDownStreamPhyAdd( + dmRoot_t *dmRoot, + dmExpander_t *oneExpander, + bit8 phyId + ); + +osGLOBAL dmDeviceData_t * +dmPortSASDeviceFind( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + bit32 sasAddrLo, + bit32 sasAddrHi, + dmDeviceData_t *CurrentDeviceData + ); +bit32 +dmNewEXPorNot( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmSASSubID_t *dmSASSubID + ); + +bit32 +dmNewSASorNot( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmSASSubID_t *dmSASSubID + ); + +osGLOBAL dmDeviceData_t * +dmPortSASDeviceAdd( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + agsaSASIdentify_t sasIdentify, + bit32 sasInitiator, + bit8 connectionRate, + bit32 itNexusTimeout, + bit32 firstBurstSize, + bit32 deviceType, + dmDeviceData_t *oneDeviceData, + dmExpander_t *dmExpander, + bit8 phyID + ); + + +osGLOBAL dmDeviceData_t * +dmFindRegNValid( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmSASSubID_t *dmSASSubID + ); + +osGLOBAL dmExpander_t * +dmFindConfigurableExp( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmExpander_t *oneExpander + ); + +osGLOBAL bit32 +dmDuplicateConfigSASAddr( + dmRoot_t *dmRoot, + dmExpander_t *oneExpander, + bit32 configSASAddressHi, + bit32 configSASAddressLo + ); + + +osGLOBAL bit16 +dmFindCurrentDownStreamPhyIndex( + dmRoot_t *dmRoot, + dmExpander_t *oneExpander + ); + + +osGLOBAL bit32 +dmFindDiscoveringExpander( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmExpander_t *oneExpander + ); + +osGLOBAL void +dmDumpAllExp( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmExpander_t *oneExpander + ); + + +osGLOBAL void +dmDumpAllUpExp( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmExpander_t *oneExpander + ); + +osGLOBAL void +dmDumpAllFreeExp( + dmRoot_t *dmRoot + ); + +osGLOBAL void +dmDumpAllMainExp( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ); + +osGLOBAL void +dmDumpAllMainDevice( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ); + +osGLOBAL void +dmSubReportChanges( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmDeviceData_t *oneDeviceData, + bit32 flag + ); +osGLOBAL void +dmSubReportRemovals( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmDeviceData_t *oneDeviceData, + bit32 flag + ); + +osGLOBAL void +dmReportChanges( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ); + +osGLOBAL void +dmReportRemovals( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + bit32 flag + ); + +osGLOBAL void +dmDiscoveryDeviceCleanUp( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ); +osGLOBAL void +dmDiscoveryExpanderCleanUp( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ); + +osGLOBAL void +dmResetReported( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ); + +osGLOBAL void +dmDiscoveryErrorRemovals( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ); +osGLOBAL void +dmDiscoveryInvalidateDevices( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ); + +osGLOBAL dmDeviceData_t * +dmAddSASToSharedcontext( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmSASSubID_t *dmSASSubID, + dmDeviceData_t *oneExpDeviceData, + bit8 phyID + ); +osGLOBAL bit32 +dmSAS2SAS11ErrorCheck( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmExpander_t *topExpander, + dmExpander_t *bottomExpander, + dmExpander_t *currentExpander + ); + +osGLOBAL void +dmUpdateMCN( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmDeviceData_t *AdjacentDeviceData, /* adjacent expander */ + dmDeviceData_t *oneDeviceData /* current one */ + ); + +osGLOBAL void +dmUpdateAllAdjacent( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmDeviceData_t *oneDeviceData /* current one */ + ); +osGLOBAL void +dmDiscoveryResetMCN( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ); + +osGLOBAL void +dmDiscoveryDumpMCN( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ); + +osGLOBAL void +dmDiscoveryReportMCN( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ); + +GLOBAL void dmSetDeviceInfoCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaDevHandle_t *agDevHandle, + bit32 status, + bit32 option, + bit32 param + ); + +/*********************************** SMP-related *******************************************************/ +osGLOBAL void +dmsaSMPCompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle + ); + +osGLOBAL bit32 +dmSMPStart( + dmRoot_t *dmRoot, + agsaRoot_t *agRoot, + dmDeviceData_t *oneDeviceData, + bit32 functionCode, + bit8 *pSmpBody, + bit32 smpBodySize, + bit32 agRequestType + ); + +osGLOBAL void +dmReportGeneralSend( + dmRoot_t *dmRoot, + dmDeviceData_t *oneDeviceData + ); + +osGLOBAL void +dmReportGeneralRespRcvd( + dmRoot_t *dmRoot, + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + dmDeviceData_t *oneDeviceData, + dmSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ); + +osGLOBAL void +dmReportGeneral2RespRcvd( + dmRoot_t *dmRoot, + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + dmDeviceData_t *oneDeviceData, + dmSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ); + +osGLOBAL void +dmDiscoverSend( + dmRoot_t *dmRoot, + dmDeviceData_t *oneDeviceData + ); + +osGLOBAL void +dmDiscoverRespRcvd( + dmRoot_t *dmRoot, + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + dmDeviceData_t *oneDeviceData, + dmSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ); + +osGLOBAL void +dmDiscover2RespRcvd( + dmRoot_t *dmRoot, + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + dmDeviceData_t *oneDeviceData, + dmSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ); + +#ifdef NOT_YET +osGLOBAL void +dmDiscoverList2Send( + dmRoot_t *dmRoot, + dmDeviceData_t *oneDeviceData + ); + +osGLOBAL void +dmDiscoverList2RespRcvd( + dmRoot_t *dmRoot, + agsaRoot_t *agRoot, + dmDeviceData_t *oneDeviceData, + dmSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ); +#endif + +osGLOBAL void +dmReportPhySataSend( + dmRoot_t *dmRoot, + dmDeviceData_t *oneDeviceData, + bit8 phyId + ); + +osGLOBAL void +dmReportPhySataRcvd( + dmRoot_t *dmRoot, + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + dmDeviceData_t *oneDeviceData, + dmSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ); + +osGLOBAL void +dmReportPhySata2Rcvd( + dmRoot_t *dmRoot, + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + dmDeviceData_t *oneDeviceData, + dmSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ); + +osGLOBAL bit32 +dmRoutingEntryAdd( + dmRoot_t *dmRoot, + dmExpander_t *oneExpander, + bit32 phyId, + bit32 configSASAddressHi, + bit32 configSASAddressLo + ); + +osGLOBAL void +dmConfigRoutingInfoRespRcvd( + dmRoot_t *dmRoot, + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + dmDeviceData_t *oneDeviceData, + dmSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ); + +osGLOBAL void +dmConfigRoutingInfo2RespRcvd( + dmRoot_t *dmRoot, + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + dmDeviceData_t *oneDeviceData, + dmSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ); + +osGLOBAL bit32 +dmPhyControlSend( + dmRoot_t *dmRoot, + dmDeviceData_t *oneDeviceData, + bit8 phyOp, + bit8 phyID + ); + +osGLOBAL void +dmPhyControlRespRcvd( + dmRoot_t *dmRoot, + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + dmDeviceData_t *oneDeviceData, + dmSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ); + +osGLOBAL void +dmPhyControl2RespRcvd( + dmRoot_t *dmRoot, + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + dmDeviceData_t *oneDeviceData, + dmSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ); + +osGLOBAL void +dmPhyControlFailureRespRcvd( + dmRoot_t *dmRoot, + agsaRoot_t *agRoot, + dmDeviceData_t *oneDeviceData, + dmSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ); + +osGLOBAL void +dmHandleZoneViolation( + dmRoot_t *dmRoot, + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + dmDeviceData_t *oneDeviceData, + dmSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ); + +osGLOBAL void +dmSMPCompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle + ); + +osGLOBAL void +dmSMPAbortCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 flag, + bit32 status + ); + +osGLOBAL void +dmBCTimer( + dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext + ); + +osGLOBAL void +dmBCTimerCB( + dmRoot_t * dmRoot_t, + void * timerData1, + void * timerData2, + void * timerData3 + ); + +/*********************************** SMP-related *******************************************************/ +osGLOBAL void +dmDiscoverySMPTimer(dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + bit32 functionCode, + dmSMPRequestBody_t *dmSMPRequestBody + ); + +osGLOBAL void +dmDiscoverySMPTimerCB( + dmRoot_t * dmRoot, + void * timerData1, + void * timerData2, + void * timerData3 + ); + +osGLOBAL void +dmDiscoveryConfiguringTimer(dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmDeviceData_t *oneDeviceData + ); + + +osGLOBAL void +dmDiscoveryConfiguringTimerCB( + dmRoot_t * dmRoot, + void * timerData1, + void * timerData2, + void * timerData3 + ); + +osGLOBAL void +dmSMPBusyTimer(dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmDeviceData_t *oneDeviceData, + dmSMPRequestBody_t *dmSMPRequestBody + ); + +osGLOBAL void +dmSMPBusyTimerCB( + dmRoot_t * dmRoot, + void * timerData1, + void * timerData2, + void * timerData3 + ); + +osGLOBAL void +dmConfigureRouteTimer(dmRoot_t *dmRoot, + dmIntPortContext_t *onePortContext, + dmExpander_t *oneExpander, + smpRespDiscover_t *pdmSMPDiscoverResp, + smpRespDiscover2_t *pdmSMPDiscover2Resp + ); + +osGLOBAL void +dmConfigureRouteTimerCB( + dmRoot_t * dmRoot, + void * timerData1, + void * timerData2, + void * timerData3 + ); + +#endif /* __DMPROTO_H__ */ + + diff --git a/sys/dev/pms/RefTisa/discovery/dm/dmsmp.c b/sys/dev/pms/RefTisa/discovery/dm/dmsmp.c new file mode 100644 index 000000000000..9b439645dfd9 --- /dev/null +++ b/sys/dev/pms/RefTisa/discovery/dm/dmsmp.c @@ -0,0 +1,3743 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +** +********************************************************************************/ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#include +#include + +#include +#include +#include + +#ifdef FDS_DM +#include +#include +#include + +#include +#include +#include + +osGLOBAL bit32 +dmSMPStart( + dmRoot_t *dmRoot, + agsaRoot_t *agRoot, + dmDeviceData_t *oneDeviceData, + bit32 functionCode, + bit8 *pSmpBody, + bit32 smpBodySize, + bit32 agRequestType + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmIntPortContext_t *onePortContext = agNULL; + dmSMPRequestBody_t *dmSMPRequestBody = agNULL; +#ifndef DIRECT_SMP + dmSMPRequestBody_t *dmSMPResponseBody = agNULL; +#endif + agsaSASRequestBody_t *agSASRequestBody; + dmList_t *SMPList; + agsaDevHandle_t *agDevHandle; + agsaIORequest_t *agIORequest; + agsaSMPFrame_t *agSMPFrame; + bit32 expectedRspLen = 0; + dmSMPFrameHeader_t dmSMPFrameHeader; + dmExpander_t *oneExpander = agNULL; + bit32 status; + + DM_DBG5(("dmSMPStart: start\n")); + DM_DBG5(("dmSMPStart: 2nd sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG5(("dmSMPStart: 2nd sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + + dm_memset(&dmSMPFrameHeader, 0, sizeof(dmSMPFrameHeader_t)); + + onePortContext = oneDeviceData->dmPortContext; + + if (dmDiscoverCheck(dmRoot, onePortContext) == agTRUE) + { + DM_DBG1(("dmSMPStart: invalid port or aborted discovery!!!\n")); + return DM_RC_FAILURE; + } + + oneExpander = oneDeviceData->dmExpander; + if (oneExpander == agNULL) + { + DM_DBG1(("dmSMPStart: Wrong!!! oneExpander is NULL!!!\n")); + return DM_RC_FAILURE; + } + + if (onePortContext != agNULL) + { + DM_DBG5(("dmSMPStart: pid %d\n", onePortContext->id)); + /* increment the number of pending SMP */ + onePortContext->discovery.pendingSMP++; + } + else + { + DM_DBG1(("dmSMPStart: Wrong, onePortContext is NULL!!!\n")); + return DM_RC_FAILURE; + } + + /* get an smp REQUEST from the free list */ + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + if (DMLIST_EMPTY(&(dmAllShared->freeSMPList))) + { + DM_DBG1(("dmSMPStart: no free SMP!!!\n")); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); + /* undo increment the number of pending SMP */ + onePortContext->discovery.pendingSMP--; + return DM_RC_FAILURE; + } + else + { + DMLIST_DEQUEUE_FROM_HEAD(&SMPList, &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); + dmSMPRequestBody = DMLIST_OBJECT_BASE(dmSMPRequestBody_t, Link, SMPList); + } + + if (dmSMPRequestBody == agNULL) + { + DM_DBG1(("dmSMPStart: dmSMPRequestBody is NULL, wrong!!!\n")); + return DM_RC_FAILURE; + } + DM_DBG5(("dmSMPStart: SMP id %d\n", dmSMPRequestBody->id)); + + dmSMPRequestBody->dmRoot = dmRoot; + dmSMPRequestBody->dmDevice = oneDeviceData; + dmSMPRequestBody->dmPortContext = onePortContext; + + agDevHandle = oneExpander->agDevHandle; + + /* save the callback funtion */ + dmSMPRequestBody->SMPCompletionFunc = dmSMPCompleted; /* in dmsmp.c */ + + dmSMPRequestBody->retries = 0; + + agIORequest = &(dmSMPRequestBody->agIORequest); + agIORequest->osData = (void *) dmSMPRequestBody; + agIORequest->sdkData = agNULL; /* SALL takes care of this */ + + agSASRequestBody = &(dmSMPRequestBody->agSASRequestBody); + agSMPFrame = &(agSASRequestBody->smpFrame); + + /* sets dmSMPFrameHeader values */ + if (oneExpander->SAS2 == 0) + { + DM_DBG5(("dmSMPStart: SAS 1.1\n")); + switch (functionCode) + { + case SMP_REPORT_GENERAL: + expectedRspLen = sizeof(smpRespReportGeneral_t) + 4; + break; + case SMP_REPORT_MANUFACTURE_INFORMATION: + expectedRspLen = sizeof(smpRespReportManufactureInfo_t) + 4; + break; + case SMP_DISCOVER: + expectedRspLen = sizeof(smpRespDiscover_t) + 4; + break; + case SMP_REPORT_PHY_ERROR_LOG: + expectedRspLen = 32 - 4; + break; + case SMP_REPORT_PHY_SATA: + expectedRspLen = sizeof(smpRespReportPhySata_t) + 4; + break; + case SMP_REPORT_ROUTING_INFORMATION: + expectedRspLen = sizeof(smpRespReportRouteTable_t) + 4; + break; + case SMP_CONFIGURE_ROUTING_INFORMATION: + expectedRspLen = 4; + break; + case SMP_PHY_CONTROL: + expectedRspLen = 4; + break; + case SMP_PHY_TEST_FUNCTION: + expectedRspLen = 4; + break; + case SMP_PMC_SPECIFIC: + expectedRspLen = 4; + break; + default: + expectedRspLen = 0; + DM_DBG1(("dmSMPStart: SAS 1.1 error, undefined or unused smp function code 0x%x !!!\n", functionCode)); + return DM_RC_FAILURE; + } + /* SMP 1.1 header */ + dmSMPFrameHeader.smpFrameType = SMP_REQUEST; /* SMP request */ + dmSMPFrameHeader.smpFunction = (bit8)functionCode; + dmSMPFrameHeader.smpFunctionResult = 0; + dmSMPFrameHeader.smpReserved = 0; + } + else /* SAS 2 */ + { + DM_DBG2(("dmSMPStart: SAS 2\n")); + switch (functionCode) + { + case SMP_REPORT_GENERAL: + expectedRspLen = sizeof(smpRespReportGeneral2_t) + 4; + /* SMP 2.0 header */ + dmSMPFrameHeader.smpFrameType = SMP_REQUEST; /* SMP request */ + dmSMPFrameHeader.smpFunction = (bit8)functionCode; + dmSMPFrameHeader.smpFunctionResult = 0x11; + dmSMPFrameHeader.smpReserved = 0; + break; + case SMP_REPORT_MANUFACTURE_INFORMATION: + expectedRspLen = sizeof(smpRespReportManufactureInfo2_t) + 4; + break; + case SMP_DISCOVER: + expectedRspLen = sizeof(smpRespDiscover2_t) + 4; + /* SMP 2.0 header */ + dmSMPFrameHeader.smpFrameType = SMP_REQUEST; /* SMP request */ + dmSMPFrameHeader.smpFunction = (bit8)functionCode; +// dmSMPFrameHeader.smpFunctionResult = 0x6c; + dmSMPFrameHeader.smpFunctionResult = 0x1b; + dmSMPFrameHeader.smpReserved = 0x02; + break; + case SMP_REPORT_PHY_ERROR_LOG: + expectedRspLen = 32 - 4; + break; + case SMP_REPORT_PHY_SATA: + /* SMP 2.0 header */ + dmSMPFrameHeader.smpFrameType = SMP_REQUEST; /* SMP request */ + dmSMPFrameHeader.smpFunction = (bit8)functionCode; + dmSMPFrameHeader.smpFunctionResult = 0x10; + dmSMPFrameHeader.smpReserved = 0x02; + expectedRspLen = sizeof(smpRespReportPhySata2_t) + 4; + break; + case SMP_REPORT_ROUTING_INFORMATION: + expectedRspLen = sizeof(smpRespReportRouteTable2_t) + 4; + break; + case SMP_CONFIGURE_ROUTING_INFORMATION: + expectedRspLen = 4; + /* SMP 2.0 header */ + dmSMPFrameHeader.smpFrameType = SMP_REQUEST; /* SMP request */ + dmSMPFrameHeader.smpFunction = (bit8)functionCode; + dmSMPFrameHeader.smpFunctionResult = 0; + dmSMPFrameHeader.smpReserved = 0x09; + break; + case SMP_PHY_CONTROL: + expectedRspLen = 4; + /* SMP 2.0 header */ + dmSMPFrameHeader.smpFrameType = SMP_REQUEST; /* SMP request */ + dmSMPFrameHeader.smpFunction = (bit8)functionCode; + dmSMPFrameHeader.smpFunctionResult = 0; + dmSMPFrameHeader.smpReserved = 0x09; + break; + case SMP_PHY_TEST_FUNCTION: + expectedRspLen = 4; + break; + case SMP_DISCOVER_LIST: + expectedRspLen = SMP_MAXIMUM_PAYLOAD; /* 1024 without CRC */ + /* SMP 2.0 header */ + dmSMPFrameHeader.smpFrameType = SMP_REQUEST; /* SMP request */ + dmSMPFrameHeader.smpFunction = (bit8)functionCode; + dmSMPFrameHeader.smpFunctionResult = 0xFF; + dmSMPFrameHeader.smpReserved = 0x06; + break; + case SMP_PMC_SPECIFIC: + expectedRspLen = 4; + break; + default: + expectedRspLen = 0; + DM_DBG1(("dmSMPStart: SAS 2 error!!! undefined or unused smp function code 0x%x!!!\n", functionCode)); + return DM_RC_FAILURE; + } + } + + if (DMIsSPC(agRoot)) + { +#ifdef DIRECT_SMP /* direct SMP with 48 or less payload */ + if ( (smpBodySize + 4) <= SMP_DIRECT_PAYLOAD_LIMIT) /* 48 */ + { + DM_DBG5(("dmSMPStart: DIRECT smp payload\n")); + dm_memset(dmSMPRequestBody->smpPayload, 0, SMP_DIRECT_PAYLOAD_LIMIT); + dm_memcpy(dmSMPRequestBody->smpPayload, &dmSMPFrameHeader, 4); + dm_memcpy((dmSMPRequestBody->smpPayload)+4, pSmpBody, smpBodySize); + + /* direct SMP payload eg) REPORT_GENERAL, DISCOVER etc */ + agSMPFrame->outFrameBuf = dmSMPRequestBody->smpPayload; + agSMPFrame->outFrameLen = smpBodySize + 4; /* without last 4 byte crc */ + /* to specify DIRECT SMP response */ + agSMPFrame->inFrameLen = 0; + + /* temporary solution for T2D Combo*/ +#if defined (INITIATOR_DRIVER) && defined (TARGET_DRIVER) + /* force smp repsonse to be direct */ + agSMPFrame->expectedRespLen = 0; +#else + agSMPFrame->expectedRespLen = expectedRspLen; +#endif + } + else + { + DM_DBG5(("dmSMPStart: INDIRECT smp payload, TBD\n")); + } + +#else + + /* + dmSMPRequestBody is SMP request + dmSMPResponsebody is SMP response + */ + + /* get an smp RESPONSE from the free list */ + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + if (DMLIST_EMPTY(&(dmAllShared->freeSMPList))) + { + DM_DBG1(("dmSMPStart: no free SMP!!!\n")); + /* puy back dmSMPRequestBody to the freelist ???*/ +// DMLIST_DEQUEUE_THIS(&(dmSMPRequestBody->Link)); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPRequestBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); + + /* undo increment the number of pending SMP */ + onePortContext->discovery.pendingSMP--; + return DM_RC_FAILURE; + } + else + { + DMLIST_DEQUEUE_FROM_HEAD(&SMPList, &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); + dmSMPResponseBody = DMLIST_OBJECT_BASE(dmSMPRequestBody_t, Link, SMPList); + DM_DBG5(("dmSMPStart: SMP id %d\n", dmSMPResponseBody->id)); + } + + if (dmSMPResponseBody == agNULL) + { + DM_DBG1(("dmSMPStart: dmSMPResponseBody is NULL, wrong!!!\n")); + return DM_RC_FAILURE; + } + + /* fill in indirect SMP request fields */ + DM_DBG5(("dmSMPStart: INDIRECT smp payload\n")); + + /* save the pointer to SMP response in SMP request */ + dmSMPRequestBody->IndirectSMPResponse = dmSMPResponseBody; + /* SMP request and response initialization */ + dm_memset(dmSMPRequestBody->IndirectSMP, 0, smpBodySize + 4); + dm_memset(dmSMPResponseBody->IndirectSMP, 0, expectedRspLen); + + dm_memcpy(dmSMPRequestBody->IndirectSMP, &dmSMPFrameHeader, 4); + dm_memcpy(dmSMPRequestBody->IndirectSMP+4, pSmpBody, smpBodySize); + + /* Indirect SMP request */ + agSMPFrame->outFrameBuf = agNULL; + agSMPFrame->outFrameAddrUpper32 = dmSMPRequestBody->IndirectSMPUpper32; + agSMPFrame->outFrameAddrLower32 = dmSMPRequestBody->IndirectSMPLower32; + agSMPFrame->outFrameLen = smpBodySize + 4; /* without last 4 byte crc */ + + /* Indirect SMP response */ + agSMPFrame->expectedRespLen = expectedRspLen; + agSMPFrame->inFrameAddrUpper32 = dmSMPResponseBody->IndirectSMPUpper32; + agSMPFrame->inFrameAddrLower32 = dmSMPResponseBody->IndirectSMPLower32; + agSMPFrame->inFrameLen = expectedRspLen; /* without last 4 byte crc */ + +#endif + } + else /* SPCv controller */ + { + /* only direct mode for both request and response */ + DM_DBG5(("dmSMPStart: DIRECT smp payload\n")); + agSMPFrame->flag = 0; + dm_memset(dmSMPRequestBody->smpPayload, 0, SMP_DIRECT_PAYLOAD_LIMIT); + dm_memcpy(dmSMPRequestBody->smpPayload, &dmSMPFrameHeader, 4); + dm_memcpy((dmSMPRequestBody->smpPayload)+4, pSmpBody, smpBodySize); + + /* direct SMP payload eg) REPORT_GENERAL, DISCOVER etc */ + agSMPFrame->outFrameBuf = dmSMPRequestBody->smpPayload; + agSMPFrame->outFrameLen = smpBodySize + 4; /* without last 4 byte crc */ + /* to specify DIRECT SMP response */ + agSMPFrame->inFrameLen = 0; + + /* temporary solution for T2D Combo*/ +#if defined (INITIATOR_DRIVER) && defined (TARGET_DRIVER) + /* force smp repsonse to be direct */ + agSMPFrame->expectedRespLen = 0; +#else + agSMPFrame->expectedRespLen = expectedRspLen; +#endif + // tdhexdump("tdSMPStart", (bit8*)agSMPFrame->outFrameBuf, agSMPFrame->outFrameLen); + // tdhexdump("tdSMPStart new", (bit8*)tdSMPRequestBody->smpPayload, agSMPFrame->outFrameLen); + // tdhexdump("tdSMPStart - tdSMPRequestBody", (bit8*)tdSMPRequestBody, sizeof(tdssSMPRequestBody_t)); + } + + if (agDevHandle == agNULL) + { + DM_DBG1(("dmSMPStart: !!! agDevHandle is NULL !!! \n")); + } + else + { + status = saSMPStart( + agRoot, + agIORequest, + 0, + agDevHandle, + agRequestType, + agSASRequestBody, + &dmsaSMPCompleted + ); + + if (status == AGSA_RC_SUCCESS) + { + /* start SMP timer */ + if (functionCode == SMP_REPORT_GENERAL || functionCode == SMP_DISCOVER || + functionCode == SMP_REPORT_PHY_SATA || functionCode == SMP_CONFIGURE_ROUTING_INFORMATION + ) + { + dmDiscoverySMPTimer(dmRoot, onePortContext, functionCode, dmSMPRequestBody); + } + return DM_RC_SUCCESS; + } + else if (status == AGSA_RC_BUSY) + { + /* set timer */ + if (functionCode == SMP_REPORT_GENERAL || functionCode == SMP_DISCOVER || + functionCode == SMP_REPORT_PHY_SATA || functionCode == SMP_CONFIGURE_ROUTING_INFORMATION) + { + /* only for discovery related SMPs*/ + dmSMPBusyTimer(dmRoot, onePortContext, oneDeviceData, dmSMPRequestBody); + return DM_RC_SUCCESS; + } + else + { + DM_DBG1(("dmSMPStart: return DM_RC_BUSY!!! \n")); +#ifdef DIRECT_SMP + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPRequestBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); +#else + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPRequestBody->Link), &(dmAllShared->freeSMPList)); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPRequestBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); +#endif + return DM_RC_BUSY; + } + } + else /* AGSA_RC_FAILURE */ + { + DM_DBG1(("dmSMPStart: return DM_RC_FAILURE!!! \n")); + /* discovery failure or task management failure */ + if (functionCode == SMP_REPORT_GENERAL || functionCode == SMP_DISCOVER || + functionCode == SMP_REPORT_PHY_SATA || functionCode == SMP_CONFIGURE_ROUTING_INFORMATION) + { + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } +#ifdef DIRECT_SMP + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPRequestBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); +#else + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPRequestBody->Link), &(dmAllShared->freeSMPList)); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPRequestBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); +#endif + + return DM_RC_FAILURE; + } + } + return DM_RC_SUCCESS; +} + +osGLOBAL void +dmsaSMPCompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle + ) +{ + dmSMPRequestBody_t *pSMPRequestBody = (dmSMPRequestBody_t *) agIORequest->osData; + + /* SPC can't be SMP target */ + + DM_DBG5(("dmsaSMPCompleted: start\n")); + + if (pSMPRequestBody == agNULL) + { + DM_DBG1(("dmsaSMPCompleted: pSMPRequestBody is NULL!!! \n")); + return; + } + + if (pSMPRequestBody->SMPCompletionFunc == agNULL) + { + DM_DBG1(("dmsaSMPCompleted: pSMPRequestBody->SMPCompletionFunc is NULL!!!\n")); + return; + } + +#ifdef DM_INTERNAL_DEBUG /* debugging */ + DM_DBG3(("dmsaSMPCompleted: agIOrequest %p\n", agIORequest->osData)); + DM_DBG3(("dmsaSMPCompleted: sizeof(tdIORequestBody_t) %d 0x%x\n", sizeof(tdIORequestBody_t), + sizeof(tdIORequestBody_t))); + DM_DBG3(("dmsaSMPCompleted: SMPRequestbody %p\n", pSMPRequestBody)); + DM_DBG3(("dmsaSMPCompleted: calling callback fn\n")); + DM_DBG3(("dmsaSMPCompleted: callback fn %p\n",pSMPRequestBody->SMPCompletionFunc)); +#endif /* TD_INTERNAL_DEBUG */ + /* + if initiator, calling dmSMPCompleted() in dmsmp.c + */ + pSMPRequestBody->SMPCompletionFunc( + agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agFrameHandle + ); + + return; + +} + +osGLOBAL bit32 +dmPhyControlSend( + dmRoot_t *dmRoot, +// dmDeviceData_t *oneDeviceData, /* taget disk */ + dmDeviceData_t *oneExpDeviceData, /* taget disk */ + bit8 phyOp, +bit8 phyID // added + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + agsaRoot_t *agRoot = dmAllShared->agRoot; +// thenil +// dmDeviceData_t *oneExpDeviceData; + smpReqPhyControl_t smpPhyControlReq; +// bit8 phyID; + bit32 status; + + DM_DBG3(("dmPhyControlSend: start\n")); + + + + osti_memset(&smpPhyControlReq, 0, sizeof(smpReqPhyControl_t)); + + /* fill in SMP payload */ + smpPhyControlReq.phyIdentifier = phyID; + smpPhyControlReq.phyOperation = phyOp; + + status = dmSMPStart( + dmRoot, + agRoot, + oneExpDeviceData, + SMP_PHY_CONTROL, + (bit8 *)&smpPhyControlReq, + sizeof(smpReqPhyControl_t), + AGSA_SMP_INIT_REQ + ); + return status; +} + +osGLOBAL void +dmReportGeneralSend( + dmRoot_t *dmRoot, + dmDeviceData_t *oneDeviceData + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + agsaRoot_t *agRoot = dmAllShared->agRoot; + + DM_DBG3(("dmReportGeneralSend: start\n")); + DM_DBG3(("dmReportGeneralSend: oneDeviceData %p did %d\n", oneDeviceData, oneDeviceData->id)); + DM_DBG3(("dmReportGeneralSend: oneExpander %p did %d\n", oneDeviceData->dmExpander, oneDeviceData->dmExpander->id)); + + if (agRoot == agNULL) + { + DM_DBG1(("dmReportGeneralSend: agRoot is NULL!!!\n")); + return; + } + + dmSMPStart( + dmRoot, + agRoot, + oneDeviceData, + SMP_REPORT_GENERAL, + agNULL, + 0, + AGSA_SMP_INIT_REQ + ); + return; +} +osGLOBAL void +dmReportGeneralRespRcvd( + dmRoot_t *dmRoot, + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + dmDeviceData_t *oneDeviceData, + dmSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ) +{ + smpRespReportGeneral_t dmSMPReportGeneralResp; + smpRespReportGeneral_t *pdmSMPReportGeneralResp; + dmIntPortContext_t *onePortContext = agNULL; + dmDiscovery_t *discovery; + dmExpander_t *oneExpander = agNULL; +#ifndef DIRECT_SMP + dmSMPRequestBody_t *dmSMPRequestBody; + dmSMPRequestBody_t *dmSMPResponseBody = agNULL; +#endif + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + + DM_DBG3(("dmReportGeneralRespRcvd: start\n")); + DM_DBG3(("dmReportGeneralRespRcvd: sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG3(("dmReportGeneralRespRcvd: sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + +#ifndef DIRECT_SMP + dmSMPRequestBody = (dmSMPRequestBody_t *)agIORequest->osData; +#endif + pdmSMPReportGeneralResp = &dmSMPReportGeneralResp; + + dm_memset(&dmSMPReportGeneralResp, 0, sizeof(smpRespReportGeneral_t)); + +#ifdef DIRECT_SMP + saFrameReadBlock(agRoot, frameHandle, 4, pdmSMPReportGeneralResp, sizeof(smpRespReportGeneral_t)); +#else + dmSMPResponseBody = (dmSMPRequestBody_t *)dmSMPRequestBody->IndirectSMPResponse; + saFrameReadBlock(agRoot, dmSMPResponseBody->IndirectSMP, 4, pdmSMPReportGeneralResp, sizeof(smpRespReportGeneral_t)); +#endif + + onePortContext = oneDeviceData->dmPortContext; + discovery = &(onePortContext->discovery); + + if (dmDiscoverCheck(dmRoot, onePortContext) == agTRUE) + { + DM_DBG1(("dmReportGeneralRespRcvd: invalid port or aborted discovery!!!\n")); + return; + } + + if (frameHeader->smpFunctionResult == SMP_FUNCTION_ACCEPTED) + { + oneDeviceData->numOfPhys = (bit8) pdmSMPReportGeneralResp->numOfPhys; + oneExpander = oneDeviceData->dmExpander; + oneExpander->routingIndex = (bit16) REPORT_GENERAL_GET_ROUTEINDEXES(pdmSMPReportGeneralResp); + oneExpander->configReserved = 0; + oneExpander->configRouteTable = REPORT_GENERAL_IS_CONFIGURABLE(pdmSMPReportGeneralResp) ? 1 : 0; + oneExpander->configuring = REPORT_GENERAL_IS_CONFIGURING(pdmSMPReportGeneralResp) ? 1 : 0; + DM_DBG2(("dmReportGeneralRespRcvd: SAS 2 is %d\n", oneExpander->SAS2)); + DM_DBG3(("dmReportGeneralRespRcvd: oneDeviceData %p did %d\n", oneDeviceData, oneDeviceData->id)); + DM_DBG3(("dmReportGeneralRespRcvd: oneExpander %p did %d\n", oneExpander, oneExpander->id)); + + if ( oneExpander->SAS2 == 0 && REPORT_GENERAL_IS_LONG_RESPONSE(pdmSMPReportGeneralResp) == 1) + { + oneExpander->SAS2 = REPORT_GENERAL_IS_LONG_RESPONSE(pdmSMPReportGeneralResp); + DM_DBG2(("dmReportGeneralRespRcvd: SAS 2 Long Response=%d\n", REPORT_GENERAL_IS_LONG_RESPONSE(pdmSMPReportGeneralResp))); + dmReportGeneralSend(dmRoot, oneDeviceData); + return; + } + + DM_DBG3(("dmReportGeneralRespRcvd: oneExpander=%p numberofPhys=0x%x RoutingIndex=0x%x\n", + oneExpander, oneDeviceData->numOfPhys, oneExpander->routingIndex)); + DM_DBG3(("dmReportGeneralRespRcvd: configRouteTable=%d configuring=%d\n", + oneExpander->configRouteTable, oneExpander->configuring)); + + if (oneExpander->configuring == 1) + { + discovery->retries++; + if (discovery->retries >= dmAllShared->MaxRetryDiscovery) + { + DM_DBG1(("dmReportGeneralRespRcvd: retries are over!!!\n")); + DM_DBG1(("dmReportGeneralRespRcvd: sasAddressHi 0x%08x sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi, oneDeviceData->SASAddressID.sasAddressLo)); + discovery->retries = 0; + /* failed the discovery */ + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + else + { + DM_DBG3(("dmReportGeneralRespRcvd: keep retrying\n")); + DM_DBG1(("dmReportGeneralRespRcvd: Prep222389 RETRY at %d Maximum Retry is %d\n", discovery->retries, dmAllShared->MaxRetryDiscovery)); + DM_DBG1(("dmReportGeneralRespRcvd: sasAddressHi 0x%08x sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi, oneDeviceData->SASAddressID.sasAddressLo)); + // start timer for sending ReportGeneral + dmDiscoveryConfiguringTimer(dmRoot, onePortContext, oneDeviceData); + } + } + else + { + discovery->retries = 0; + dmDiscoverSend(dmRoot, oneDeviceData); + } + } + else + { + DM_DBG1(("dmReportGeneralRespRcvd: SMP failed; fn result 0x%x; stopping discovery !!!\n", frameHeader->smpFunctionResult)); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + return; +} + +osGLOBAL void +dmReportGeneral2RespRcvd( + dmRoot_t *dmRoot, + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + dmDeviceData_t *oneDeviceData, + dmSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ) +{ + smpRespReportGeneral2_t dmSMPReportGeneral2Resp; + smpRespReportGeneral2_t *pdmSMPReportGeneral2Resp; + dmExpander_t *oneExpander = agNULL; + dmIntPortContext_t *onePortContext = agNULL; + dmDiscovery_t *discovery; +#ifndef DIRECT_SMP + dmSMPRequestBody_t *dmSMPRequestBody; + dmSMPRequestBody_t *dmSMPResponseBody = agNULL; +#endif + bit32 ConfiguresOthers = agFALSE; + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + + + DM_DBG2(("dmReportGeneral2RespRcvd: start\n")); + DM_DBG2(("dmReportGeneral2RespRcvd: sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG2(("dmReportGeneral2RespRcvd: sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + +#ifndef DIRECT_SMP + dmSMPRequestBody = (dmSMPRequestBody_t *)agIORequest->osData; +#endif + pdmSMPReportGeneral2Resp = &dmSMPReportGeneral2Resp; + + dm_memset(&dmSMPReportGeneral2Resp, 0, sizeof(smpRespReportGeneral2_t)); + +#ifdef DIRECT_SMP + saFrameReadBlock(agRoot, frameHandle, 4, pdmSMPReportGeneral2Resp, sizeof(smpRespReportGeneral2_t)); +#else + dmSMPResponseBody = (dmSMPRequestBody_t *)dmSMPRequestBody->IndirectSMPResponse; + saFrameReadBlock(agRoot, dmSMPResponseBody->IndirectSMP, 4, pdmSMPReportGeneral2Resp, sizeof(smpRespReportGeneral2_t)); +#endif + + onePortContext = oneDeviceData->dmPortContext; + discovery = &(onePortContext->discovery); + if (dmDiscoverCheck(dmRoot, onePortContext) == agTRUE) + { + DM_DBG1(("dmReportGeneral2RespRcvd: invalid port or aborted discovery!!!\n")); + return; + } + +/* ??? start here */ + if (frameHeader->smpFunctionResult == SMP_FUNCTION_ACCEPTED) + { + oneDeviceData->numOfPhys = (bit8) pdmSMPReportGeneral2Resp->numOfPhys; + oneExpander = oneDeviceData->dmExpander; + oneExpander->routingIndex = (bit16) SAS2_REPORT_GENERAL_GET_ROUTEINDEXES(pdmSMPReportGeneral2Resp); + oneExpander->configReserved = 0; + oneExpander->configRouteTable = SAS2_REPORT_GENERAL_IS_CONFIGURABLE(pdmSMPReportGeneral2Resp) ? 1 : 0; + oneExpander->configuring = SAS2_REPORT_GENERAL_IS_CONFIGURING(pdmSMPReportGeneral2Resp) ? 1 : 0; + oneExpander->TTTSupported = SAS2_REPORT_GENERAL_IS_TABLE_TO_TABLE_SUPPORTED(pdmSMPReportGeneral2Resp) ? 1 : 0; + ConfiguresOthers = SAS2_REPORT_GENERAL_IS_CONFIGURES_OTHERS(pdmSMPReportGeneral2Resp) ? 1 : 0; + + DM_DBG2(("dmReportGeneral2RespRcvd: SAS 2 is %d\n", oneExpander->SAS2)); + DM_DBG3(("dmReportGeneral2RespRcvd: oneDeviceData %p did %d\n", oneDeviceData, oneDeviceData->id)); + DM_DBG3(("dmReportGeneral2RespRcvd: oneExpander %p did %d\n", oneExpander, oneExpander->id)); + + + DM_DBG2(("dmReportGeneral2RespRcvd: oneExpander=%p numberofPhys=0x%x RoutingIndex=0x%x\n", + oneExpander, oneDeviceData->numOfPhys, oneExpander->routingIndex)); + DM_DBG2(("dmReportGeneral2RespRcvd: configRouteTable=%d configuring=%d\n", + oneExpander->configRouteTable, oneExpander->configuring)); + if (ConfiguresOthers) + { + DM_DBG2(("dmReportGeneral2RespRcvd: ConfiguresOthers is true\n")); + discovery->ConfiguresOthers = agTRUE; + } + if (oneExpander->configuring == 1) + { + discovery->retries++; + if (discovery->retries >= dmAllShared->MaxRetryDiscovery) + { + DM_DBG1(("dmReportGeneral2RespRcvd: retries are over!!!\n")); + DM_DBG1(("dmReportGeneral2RespRcvd: sasAddressHi 0x%08x sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi, oneDeviceData->SASAddressID.sasAddressLo)); + + discovery->retries = 0; + /* failed the discovery */ + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + else + { + DM_DBG2(("dmReportGeneral2RespRcvd: keep retrying\n")); + DM_DBG1(("dmReportGeneral2RespRcvd: Prep222389 RETRY at %d Maximum Retry is %d\n", discovery->retries, dmAllShared->MaxRetryDiscovery)); + DM_DBG1(("dmReportGeneral2RespRcvd: sasAddressHi 0x%08x sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi, oneDeviceData->SASAddressID.sasAddressLo)); + // start timer for sending ReportGeneral + dmDiscoveryConfiguringTimer(dmRoot, onePortContext, oneDeviceData); + } + } + else + { + discovery->retries = 0; + dmDiscoverSend(dmRoot, oneDeviceData); + } + } + else + { + DM_DBG2(("dmReportGeneral2RespRcvd: SMP failed, stopping discovery\n")); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + + return; +} + + +osGLOBAL void +dmDiscoverSend( + dmRoot_t *dmRoot, + dmDeviceData_t *oneDeviceData + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + agsaRoot_t *agRoot = dmAllShared->agRoot; + smpReqDiscover_t smpDiscoverReq; + dmExpander_t *oneExpander; + + DM_DBG3(("dmDiscoverSend: start\n")); + DM_DBG3(("dmDiscoverSend: oneDeviceData %p did %d\n", oneDeviceData, oneDeviceData->id)); + oneExpander = oneDeviceData->dmExpander; + DM_DBG3(("dmDiscoverSend: oneExpander %p did %d\n", oneExpander, oneExpander->id)); + DM_DBG3(("dmDiscoverSend: phyID 0x%x\n", oneExpander->discoveringPhyId)); + + dm_memset(&smpDiscoverReq, 0, sizeof(smpReqDiscover_t)); + + smpDiscoverReq.reserved1 = 0; + smpDiscoverReq.reserved2 = 0; + smpDiscoverReq.phyIdentifier = oneExpander->discoveringPhyId; + smpDiscoverReq.reserved3 = 0; + + dmSMPStart( + dmRoot, + agRoot, + oneDeviceData, + SMP_DISCOVER, + (bit8 *)&smpDiscoverReq, + sizeof(smpReqDiscover_t), + AGSA_SMP_INIT_REQ + ); + return; +} + +osGLOBAL void +dmDiscoverRespRcvd( + dmRoot_t *dmRoot, + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + dmDeviceData_t *oneDeviceData, + dmSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ) +{ + dmIntPortContext_t *onePortContext = agNULL; + dmDiscovery_t *discovery; + smpRespDiscover_t *pdmSMPDiscoverResp; +#ifndef DIRECT_SMP + dmSMPRequestBody_t *dmSMPRequestBody; + dmSMPRequestBody_t *dmSMPResponseBody = agNULL; +#endif + dmExpander_t *oneExpander = agNULL; + + DM_DBG3(("dmDiscoverRespRcvd: start\n")); + DM_DBG3(("dmDiscoverRespRcvd: sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG3(("dmDiscoverRespRcvd: sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + + onePortContext = oneDeviceData->dmPortContext; + oneExpander = oneDeviceData->dmExpander; + discovery = &(onePortContext->discovery); +#ifndef DIRECT_SMP + dmSMPRequestBody = (dmSMPRequestBody_t *)agIORequest->osData; +#endif + DM_DBG3(("dmDiscoverRespRcvd: oneDeviceData %p did %d\n", oneDeviceData, oneDeviceData->id)); + DM_DBG3(("dmDiscoverRespRcvd: oneExpander %p did %d\n", oneExpander, oneExpander->id)); + + if (dmDiscoverCheck(dmRoot, onePortContext) == agTRUE) + { + DM_DBG1(("dmDiscoverRespRcvd: invalid port or aborted discovery!!!\n")); + return; + } + + pdmSMPDiscoverResp = &(discovery->SMPDiscoverResp); + +#ifdef DIRECT_SMP + saFrameReadBlock(agRoot, frameHandle, 4, pdmSMPDiscoverResp, sizeof(smpRespDiscover_t)); +#else + dmSMPResponseBody = (dmSMPRequestBody_t *)dmSMPRequestBody->IndirectSMPResponse; + saFrameReadBlock(agRoot, dmSMPResponseBody->IndirectSMP, 4, pdmSMPDiscoverResp, sizeof(smpRespDiscover_t)); +#endif + + if ( frameHeader->smpFunctionResult == SMP_FUNCTION_ACCEPTED) + { + if ( onePortContext->discovery.status == DISCOVERY_UP_STREAM) + { + dmUpStreamDiscoverExpanderPhy(dmRoot, onePortContext, oneExpander, pdmSMPDiscoverResp); + } + else if ( onePortContext->discovery.status == DISCOVERY_DOWN_STREAM) + { + dmDownStreamDiscoverExpanderPhy(dmRoot, onePortContext, oneExpander, pdmSMPDiscoverResp); + } + else if (onePortContext->discovery.status == DISCOVERY_CONFIG_ROUTING) + { + /* not done with configuring routing + 1. set the timer + 2. on timer expiration, call tdsaSASDownStreamDiscoverExpanderPhy() + */ + DM_DBG3(("dmDiscoverRespRcvd: still configuring routing; setting timer\n")); + DM_DBG3(("dmDiscoverRespRcvd: onePortContext %p oneDeviceData %p pdmSMPDiscoverResp %p\n", onePortContext, oneDeviceData, pdmSMPDiscoverResp)); + dmhexdump("dmDiscoverRespRcvd", (bit8*)pdmSMPDiscoverResp, sizeof(smpRespDiscover_t)); + + dmConfigureRouteTimer(dmRoot, onePortContext, oneExpander, pdmSMPDiscoverResp, agNULL); + } + else + { + /* nothing */ + } + } + else if (frameHeader->smpFunctionResult == PHY_VACANT) + { + DM_DBG3(("dmDiscoverRespRcvd: smpFunctionResult is PHY_VACANT, phyid %d\n", oneExpander->discoveringPhyId)); + if ( onePortContext->discovery.status == DISCOVERY_UP_STREAM) + { + dmUpStreamDiscoverExpanderPhySkip(dmRoot, onePortContext, oneExpander); + } + else if ( onePortContext->discovery.status == DISCOVERY_DOWN_STREAM) + { + dmDownStreamDiscoverExpanderPhySkip(dmRoot, onePortContext, oneExpander); + } + else if (onePortContext->discovery.status == DISCOVERY_CONFIG_ROUTING) + { + /* not done with configuring routing + 1. set the timer + 2. on timer expiration, call tdsaSASDownStreamDiscoverExpanderPhy() + */ + DM_DBG3(("dmDiscoverRespRcvd: still configuring routing; setting timer\n")); + DM_DBG3(("dmDiscoverRespRcvd: onePortContext %p oneDeviceData %p pdmSMPDiscoverResp %p\n", onePortContext, oneDeviceData, pdmSMPDiscoverResp)); + dmhexdump("dmDiscoverRespRcvd", (bit8*)pdmSMPDiscoverResp, sizeof(smpRespDiscover_t)); + + dmConfigureRouteTimer(dmRoot, onePortContext, oneExpander, pdmSMPDiscoverResp, agNULL); + } + } + else + { + DM_DBG1(("dmDiscoverRespRcvd: Discovery Error SMP function return result error=0x%x !!!\n", + frameHeader->smpFunctionResult)); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + + + + return; +} + +osGLOBAL void +dmDiscover2RespRcvd( + dmRoot_t *dmRoot, + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + dmDeviceData_t *oneDeviceData, + dmSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ) +{ + dmIntPortContext_t *onePortContext = agNULL; + dmDiscovery_t *discovery; + smpRespDiscover2_t *pdmSMPDiscover2Resp; +#ifndef DIRECT_SMP + dmSMPRequestBody_t *dmSMPRequestBody; + dmSMPRequestBody_t *dmSMPResponseBody = agNULL; +#endif + dmExpander_t *oneExpander = agNULL; + + DM_DBG2(("dmDiscover2RespRcvd: start\n")); + DM_DBG2(("dmDiscover2RespRcvd: sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG2(("dmDiscover2RespRcvd: sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + + onePortContext = oneDeviceData->dmPortContext; + oneExpander = oneDeviceData->dmExpander; + discovery = &(onePortContext->discovery); +#ifndef DIRECT_SMP + dmSMPRequestBody = (dmSMPRequestBody_t *)agIORequest->osData; +#endif + DM_DBG3(("dmDiscoverRespRcvd: oneDeviceData %p did %d\n", oneDeviceData, oneDeviceData->id)); + DM_DBG3(("dmDiscoverRespRcvd: oneExpander %p did %d\n", oneExpander, oneExpander->id)); + + if (dmDiscoverCheck(dmRoot, onePortContext) == agTRUE) + { + DM_DBG1(("dmDiscover2RespRcvd: invalid port or aborted discovery!!!\n")); + return; + } + + pdmSMPDiscover2Resp = &(discovery->SMPDiscover2Resp); + +#ifdef DIRECT_SMP + saFrameReadBlock(agRoot, frameHandle, 4, pdmSMPDiscover2Resp, sizeof(smpRespDiscover2_t)); +#else + dmSMPResponseBody = (dmSMPRequestBody_t *)dmSMPRequestBody->IndirectSMPResponse; + saFrameReadBlock(agRoot, dmSMPResponseBody->IndirectSMP, 4, pdmSMPDiscover2Resp, sizeof(smpRespDiscover2_t)); +#endif + + if ( frameHeader->smpFunctionResult == SMP_FUNCTION_ACCEPTED ) + { + DM_DBG2(("dmDiscover2RespRcvd: phyIdentifier %d\n", pdmSMPDiscover2Resp->phyIdentifier)); + DM_DBG2(("dmDiscover2RespRcvd: NegotiatedSSCHWMuxingSupported %d\n", pdmSMPDiscover2Resp->NegotiatedSSCHWMuxingSupported)); + DM_DBG2(("dmDiscover2RespRcvd: SAS2_MUXING_SUPPORTED %d\n", SAS2_DISCRSP_IS_MUXING_SUPPORTED(pdmSMPDiscover2Resp))); + DM_DBG2(("dmDiscover2RespRcvd: NegotiatedLogicalLinkRate %d\n", pdmSMPDiscover2Resp->NegotiatedLogicalLinkRate)); + DM_DBG2(("dmDiscover2RespRcvd: ReasonNegotiatedPhysicalLinkRate %d\n", pdmSMPDiscover2Resp->ReasonNegotiatedPhysicalLinkRate)); + DM_DBG2(("dmDiscover2RespRcvd: SAS2_DISCRSP_GET_LOGICAL_LINKRATE %d\n", SAS2_DISCRSP_GET_LOGICAL_LINKRATE(pdmSMPDiscover2Resp))); + DM_DBG2(("dmDiscover2RespRcvd: SAS2_DISCRSP_GET_LINKRATE %d\n", SAS2_DISCRSP_GET_LINKRATE(pdmSMPDiscover2Resp))); + +//NegotiatedLogicalLinkRate 13 +//ReasonNegotiatedPhysicalLinkRate 94 + if ( onePortContext->discovery.status == DISCOVERY_UP_STREAM) + { + dmUpStreamDiscover2ExpanderPhy(dmRoot, onePortContext, oneExpander, pdmSMPDiscover2Resp); + } + else if ( onePortContext->discovery.status == DISCOVERY_DOWN_STREAM) + { + dmDownStreamDiscover2ExpanderPhy(dmRoot, onePortContext, oneExpander, pdmSMPDiscover2Resp); + } + else if (onePortContext->discovery.status == DISCOVERY_CONFIG_ROUTING) + { + /* not done with configuring routing + 1. set the timer + 2. on timer expiration, call tdsaSASDownStreamDiscoverExpanderPhy() + */ + DM_DBG2(("dmDiscover2RespRcvd: still configuring routing; setting timer\n")); + DM_DBG2(("dmDiscover2RespRcvd: onePortContext %p oneDeviceData %p pdmSMPDiscover2Resp %p\n", onePortContext, oneDeviceData, pdmSMPDiscover2Resp)); + dmhexdump("dmDiscover2RespRcvd", (bit8*)pdmSMPDiscover2Resp, sizeof(smpRespDiscover2_t)); + dmConfigureRouteTimer(dmRoot, onePortContext, oneExpander, agNULL, pdmSMPDiscover2Resp); + } + else + { + /* nothing */ + } + } + else if (frameHeader->smpFunctionResult == PHY_VACANT) + { + DM_DBG2(("dmDiscover2RespRcvd: smpFunctionResult is PHY_VACANT, phyid %d\n", oneExpander->discoveringPhyId)); + if ( onePortContext->discovery.status == DISCOVERY_UP_STREAM) + { + dmUpStreamDiscover2ExpanderPhySkip(dmRoot, onePortContext, oneExpander); + } + else if ( onePortContext->discovery.status == DISCOVERY_DOWN_STREAM) + { + dmDownStreamDiscover2ExpanderPhySkip(dmRoot, onePortContext, oneExpander); + } + else if (onePortContext->discovery.status == DISCOVERY_CONFIG_ROUTING) + { + /* not done with configuring routing + 1. set the timer + 2. on timer expiration, call tdsaSASDownStreamDiscoverExpanderPhy() + */ + DM_DBG2(("dmDiscover2RespRcvd: still configuring routing; setting timer\n")); + DM_DBG2(("dmDiscover2RespRcvd: onePortContext %p oneDeviceData %p pdmSMPDiscover2Resp %p\n", onePortContext, oneDeviceData, pdmSMPDiscover2Resp)); + dmhexdump("dmDiscover2RespRcvd", (bit8*)pdmSMPDiscover2Resp, sizeof(smpRespDiscover2_t)); + dmConfigureRouteTimer(dmRoot, onePortContext, oneExpander, agNULL, pdmSMPDiscover2Resp); + } + else + { + /* nothing */ + } + } + else + { + DM_DBG1(("dmDiscover2RespRcvd: Discovery Error SMP function return result error=0x%x\n", + frameHeader->smpFunctionResult)); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + return; +} + +#ifdef NOT_YET +osGLOBAL void +tdsaDiscoverList2Send( + tiRoot_t *tiRoot, + tdsaDeviceData_t *oneDeviceData + ) +{ + agsaRoot_t *agRoot; + tdsaExpander_t *oneExpander; + smpReqDiscoverList2_t smpDiscoverListReq; + + DM_DBG1(("tdsaDiscoverList2Send: start\n")); + DM_DBG1(("tdsaDiscoverList2Send: device %p did %d\n", oneDeviceData, oneDeviceData->id)); + agRoot = oneDeviceData->agRoot; + oneExpander = oneDeviceData->dmExpander; + DM_DBG1(("tdsaDiscoverList2Send: phyID 0x%x\n", oneExpander->discoveringPhyId)); + + + osti_memset(&smpDiscoverListReq, 0, sizeof(smpReqDiscoverList2_t)); + + smpDiscoverListReq.reserved1 = 0; + smpDiscoverListReq.StartingPhyID = 0; + smpDiscoverListReq.MaxNumDiscoverDesc = 40; /* 40 for SHORT FORMAT; 8 for Long Format; SAS2 p630 */ + smpDiscoverListReq.byte10 = 0x2; /* phy filter; all but "no device attached" */ + smpDiscoverListReq.byte11 = 0x1; /* descriptor type; SHORT FORMAT */ + + + dmSMPStart( + dmRoot, + agRoot, + oneDeviceData, + SMP_DISCOVER_LIST, + (bit8 *)&smpDiscoverListReq, + sizeof(smpReqDiscoverList2_t), + AGSA_SMP_INIT_REQ, + agNULL + ); + return; +} + +osGLOBAL void +tdsaDiscoverList2RespRcvd( + tiRoot_t *tiRoot, + agsaRoot_t *agRoot, + tdsaDeviceData_t *oneDeviceData, + tdssSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ) +{ + return; +} +#endif /* not yet */ + +/***************************************************************************** +*! \brief dmReportPhySataSend +* +* Purpose: This function sends Report Phy SATA to a device. +* +* \param dmRoot: Pointer to the OS Specific module allocated dmRoot_t +* instance. +* \param oneDeviceData: Pointer to the device data. +* \param phyId: Phy Identifier. +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +dmReportPhySataSend( + dmRoot_t *dmRoot, + dmDeviceData_t *oneDeviceData, + bit8 phyId + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + agsaRoot_t *agRoot = dmAllShared->agRoot; + dmExpander_t *oneExpander; + smpReqReportPhySata_t smpReportPhySataReq; + + DM_DBG3(("dmReportPhySataSend: start\n")); + DM_DBG3(("dmReportPhySataSend: oneDeviceData %p did %d\n", oneDeviceData, oneDeviceData->id)); + DM_DBG3(("dmReportPhySataSend: sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG3(("dmReportPhySataSend: sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + + oneExpander = oneDeviceData->dmExpander; + + if (oneExpander == agNULL) + { + DM_DBG1(("dmReportPhySataSend: Error!!! expander is NULL\n")); + return; + } + DM_DBG3(("dmReportPhySataSend: device %p did %d\n", oneDeviceData, oneDeviceData->id)); + DM_DBG3(("dmReportPhySataSend: phyid %d\n", phyId)); + + dm_memset(&smpReportPhySataReq, 0, sizeof(smpReqReportPhySata_t)); + + smpReportPhySataReq.phyIdentifier = phyId; + + dmSMPStart( + dmRoot, + agRoot, + oneExpander->dmDevice, + SMP_REPORT_PHY_SATA, + (bit8 *)&smpReportPhySataReq, + sizeof(smpReqReportPhySata_t), + AGSA_SMP_INIT_REQ + ); + + return; +} +/***************************************************************************** +*! \brief dmReportPhySataRcvd +* +* Purpose: This function processes Report Phy SATA response. +* +* \param dmRoot_t: Pointer to the OS Specific module allocated dmRoot_t +* instance. +* \param agRoot: Pointer to chip/driver Instance. +* \param oneDeviceData: Pointer to the device data. +* \param frameHeader: Pointer to SMP frame header. +* \param frameHandle: A Handle used to refer to the response frame +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ + +osGLOBAL void +dmReportPhySataRcvd( + dmRoot_t *dmRoot, + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + dmDeviceData_t *oneDeviceData, + dmSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ) +{ + smpRespReportPhySata_t SMPreportPhySataResp; + smpRespReportPhySata_t *pSMPReportPhySataResp; + dmExpander_t *oneExpander = oneDeviceData->dmExpander; + dmIntPortContext_t *onePortContext = agNULL; + agsaFisRegDeviceToHost_t *fis; + dmDeviceData_t *SataDevice = agNULL; +#ifndef DIRECT_SMP + dmSMPRequestBody_t *tdSMPRequestBody; +#endif + bit8 sataDeviceType; + bit8 *bit8fis; + bit8 i = 0; + bit32 a = 0; + bit8 bit8fisarray[20]; + + DM_DBG3(("dmReportPhySataRcvd: start\n")); + DM_DBG3(("dmReportPhySataRcvd: sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG3(("dmReportPhySataRcvd: sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + +#ifndef DIRECT_SMP + tdSMPRequestBody = (dmSMPRequestBody_t *)agIORequest->osData; +#endif + /* get the current sata device hanlde stored in the expander structure */ + if (oneExpander != agNULL) + { + SataDevice = oneExpander->dmDeviceToProcess; + } + + if (SataDevice != agNULL) + { + DM_DBG3(("dmReportPhySataRcvd: sasAddressHi 0x%08x\n", SataDevice->SASAddressID.sasAddressHi)); + DM_DBG3(("dmReportPhySataRcvd: sasAddressLo 0x%08x\n", SataDevice->SASAddressID.sasAddressLo)); + } + else + { + DM_DBG3(("dmReportPhySataRcvd: SataDevice is NULL\n")); + } + + pSMPReportPhySataResp = &SMPreportPhySataResp; + +#ifdef DIRECT_SMP + saFrameReadBlock(agRoot, frameHandle, 4, pSMPReportPhySataResp, sizeof(smpRespReportPhySata_t)); +#else + saFrameReadBlock(agRoot, tdSMPRequestBody->IndirectSMPResp, 4, pSMPReportPhySataResp, sizeof(smpRespReportPhySata_t)); +#endif + + /* tdhexdump("dmReportPhySataRcvd", (bit8 *)pSMPReportPhySataResp, sizeof(smpRespReportPhySata_t));*/ + +#ifndef DIRECT_SMP + ostiFreeMemory( + dmRoot, + tdSMPRequestBody->IndirectSMPReqosMemHandle, + tdSMPRequestBody->IndirectSMPReqLen + ); + ostiFreeMemory( + dmRoot, + tdSMPRequestBody->IndirectSMPResposMemHandle, + tdSMPRequestBody->IndirectSMPRespLen + ); +#endif + + onePortContext = oneDeviceData->dmPortContext; + + if (dmDiscoverCheck(dmRoot, onePortContext) == agTRUE) + { + DM_DBG1(("dmReportPhySataRcvd: invalid port or aborted discovery!!!\n")); + return; + } + + if (SataDevice == agNULL) + { + DM_DBG1(("dmReportPhySataRcvd: SataDevice is NULL, wrong\n")); + dmDiscoverAbort(dmRoot, onePortContext); + return; + } + + if (frameHeader->smpFunctionResult == PHY_VACANT ) + { + DM_DBG1(("dmReportPhySataRcvd: smpFunctionResult == PHY_VACANT, wrong\n")); + return; + } + + if ( frameHeader->smpFunctionResult == SMP_FUNCTION_ACCEPTED ) + { + fis = (agsaFisRegDeviceToHost_t*) &SMPreportPhySataResp.regDevToHostFis; + if (fis->h.fisType == REG_DEV_TO_HOST_FIS) + { + /* save signature */ + DM_DBG3(("dmReportPhySataRcvd: saves the signature\n")); + /* saves signature */ + SataDevice->satSignature[0] = fis->d.sectorCount; + SataDevice->satSignature[1] = fis->d.lbaLow; + SataDevice->satSignature[2] = fis->d.lbaMid; + SataDevice->satSignature[3] = fis->d.lbaHigh; + SataDevice->satSignature[4] = fis->d.device; + SataDevice->satSignature[5] = 0; + SataDevice->satSignature[6] = 0; + SataDevice->satSignature[7] = 0; + + DM_DBG3(("dmReportPhySataRcvd: SATA Signature = %02x %02x %02x %02x %02x\n", + SataDevice->satSignature[0], + SataDevice->satSignature[1], + SataDevice->satSignature[2], + SataDevice->satSignature[3], + SataDevice->satSignature[4])); + + sataDeviceType = tddmSATADeviceTypeDecode(SataDevice->satSignature); + if( sataDeviceType == SATA_ATAPI_DEVICE) + { + SataDevice->agDeviceInfo.flag |= ATAPI_DEVICE_FLAG; + } + SataDevice->dmDeviceInfo.sataDeviceType = sataDeviceType; + } + /* Handling DataDomain buggy FIS */ + else if (fis->h.error == REG_DEV_TO_HOST_FIS) + { + /* needs to flip fis to host order */ + bit8fis = (bit8*)fis; + for (i=0;i<5;i++) + { + a = DMA_LEBIT32_TO_BIT32(*(bit32*)bit8fis); + DM_DBG3(("dmReportPhySataRcvd: a 0x%8x\n", a)); + bit8fisarray[4*i] = (a & 0xFF000000) >> 24; + bit8fisarray[4*i+1] = (a & 0x00FF0000) >> 16; + bit8fisarray[4*i+2] = (a & 0x0000FF00) >> 8; + bit8fisarray[4*i+3] = (a & 0x000000FF); + bit8fis = bit8fis + 4; + } + fis = (agsaFisRegDeviceToHost_t*) bit8fisarray; + /* save signature */ + DM_DBG3(("dmReportPhySataRcvd: DataDomain ATAPI saves the signature\n")); + /* saves signature */ + SataDevice->satSignature[0] = fis->d.sectorCount; + SataDevice->satSignature[1] = fis->d.lbaLow; + SataDevice->satSignature[2] = fis->d.lbaMid; + SataDevice->satSignature[3] = fis->d.lbaHigh; + SataDevice->satSignature[4] = fis->d.device; + SataDevice->satSignature[5] = 0; + SataDevice->satSignature[6] = 0; + SataDevice->satSignature[7] = 0; + + DM_DBG3(("dmReportPhySataRcvd: SATA Signature = %02x %02x %02x %02x %02x\n", + SataDevice->satSignature[0], + SataDevice->satSignature[1], + SataDevice->satSignature[2], + SataDevice->satSignature[3], + SataDevice->satSignature[4])); + + sataDeviceType = tddmSATADeviceTypeDecode(SataDevice->satSignature); + if( sataDeviceType == SATA_ATAPI_DEVICE) + { + SataDevice->agDeviceInfo.flag |= ATAPI_DEVICE_FLAG; + } + SataDevice->dmDeviceInfo.sataDeviceType = sataDeviceType; + } + else + { + DM_DBG3(("dmReportPhySataRcvd: getting next stp bride\n")); + } + + /* Continure to report this STP device to TD*/ + if (SataDevice->ExpDevice != agNULL) + { + tddmReportDevice(dmRoot, onePortContext->dmPortContext, &SataDevice->dmDeviceInfo, &SataDevice->ExpDevice->dmDeviceInfo, dmDeviceArrival); + } + else + { + tddmReportDevice(dmRoot, onePortContext->dmPortContext, &SataDevice->dmDeviceInfo, agNULL, dmDeviceArrival); + } + } + else + { + DM_DBG3(("dmReportPhySataRcvd: siReportPhySataRcvd SMP function return result %x\n", + frameHeader->smpFunctionResult)); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + + return; +} + +/***************************************************************************** +*! \brief dmReportPhySata2Rcvd +* +* Purpose: This function processes SAS2.0 Report Phy SATA response. +* +* \param dmRoot_t: Pointer to the OS Specific module allocated dmRoot_t +* instance. +* \param agRoot: Pointer to chip/driver Instance. +* \param oneDeviceData: Pointer to the device data. +* \param frameHeader: Pointer to SMP frame header. +* \param frameHandle: A Handle used to refer to the response frame +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +dmReportPhySata2Rcvd( + dmRoot_t *dmRoot, + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + dmDeviceData_t *oneDeviceData, + dmSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ) +{ + smpRespReportPhySata2_t SMPreportPhySataResp; + smpRespReportPhySata2_t *pSMPReportPhySataResp; + dmExpander_t *oneExpander = oneDeviceData->dmExpander; + dmIntPortContext_t *onePortContext = agNULL; + agsaFisRegDeviceToHost_t *fis; + dmDeviceData_t *SataDevice = agNULL; +#ifndef DIRECT_SMP + dmSMPRequestBody_t *tdSMPRequestBody; +#endif + bit8 sataDeviceType = 0; + bit8 *bit8fis; + bit8 i = 0; + bit32 a = 0; + bit8 bit8fisarray[20]; + + DM_DBG3(("dmReportPhySata2Rcvd: start\n")); + DM_DBG3(("dmReportPhySata2Rcvd: sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG3(("dmReportPhySata2Rcvd: sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + +#ifndef DIRECT_SMP + tdSMPRequestBody = (dmSMPRequestBody_t *)agIORequest->osData; +#endif + /* get the current sata device hanlde stored in the expander structure */ + if (oneExpander != agNULL) + { + SataDevice = oneExpander->dmDeviceToProcess; + } + + if (SataDevice != agNULL) + { + DM_DBG3(("dmReportPhySata2Rcvd: sasAddressHi 0x%08x\n", SataDevice->SASAddressID.sasAddressHi)); + DM_DBG3(("dmReportPhySata2Rcvd: sasAddressLo 0x%08x\n", SataDevice->SASAddressID.sasAddressLo)); + } + else + { + DM_DBG3(("dmReportPhySataRcvd: SataDevice is NULL\n")); + } + + pSMPReportPhySataResp = &SMPreportPhySataResp; + +#ifdef DIRECT_SMP + saFrameReadBlock(agRoot, frameHandle, 4, pSMPReportPhySataResp, sizeof(smpRespReportPhySata_t)); +#else + saFrameReadBlock(agRoot, tdSMPRequestBody->IndirectSMPResp, 4, pSMPReportPhySataResp, sizeof(smpRespReportPhySata_t)); +#endif + + /* tdhexdump("dmReportPhySataRcvd", (bit8 *)pSMPReportPhySataResp, sizeof(smpRespReportPhySata_t));*/ + +#ifndef DIRECT_SMP + ostiFreeMemory( + dmRoot, + tdSMPRequestBody->IndirectSMPReqosMemHandle, + tdSMPRequestBody->IndirectSMPReqLen + ); + ostiFreeMemory( + dmRoot, + tdSMPRequestBody->IndirectSMPResposMemHandle, + tdSMPRequestBody->IndirectSMPRespLen + ); +#endif + + onePortContext = oneDeviceData->dmPortContext; + + if (dmDiscoverCheck(dmRoot, onePortContext) == agTRUE) + { + DM_DBG1(("dmReportPhySata2Rcvd: invalid port or aborted discovery!!!\n")); + return; + } + + if (SataDevice == agNULL) + { + DM_DBG1(("dmReportPhySata2Rcvd: SataDevice is NULL, wrong\n")); + dmDiscoverAbort(dmRoot, onePortContext); + return; + } + + if ( frameHeader->smpFunctionResult == PHY_VACANT ) + { + DM_DBG1(("dmReportPhySata2Rcvd: smpFunctionResult == PHY_VACANT, wrong\n")); + return; + } + + if ( frameHeader->smpFunctionResult == SMP_FUNCTION_ACCEPTED ) + { + fis = (agsaFisRegDeviceToHost_t*) &SMPreportPhySataResp.regDevToHostFis; + if (fis->h.fisType == REG_DEV_TO_HOST_FIS) + { + /* save signature */ + DM_DBG3(("dmReportPhySata2Rcvd: saves the signature\n")); + /* saves signature */ + SataDevice->satSignature[0] = fis->d.sectorCount; + SataDevice->satSignature[1] = fis->d.lbaLow; + SataDevice->satSignature[2] = fis->d.lbaMid; + SataDevice->satSignature[3] = fis->d.lbaHigh; + SataDevice->satSignature[4] = fis->d.device; + SataDevice->satSignature[5] = 0; + SataDevice->satSignature[6] = 0; + SataDevice->satSignature[7] = 0; + DM_DBG3(("dmReportPhySata2Rcvd: SATA Signature = %02x %02x %02x %02x %02x\n", + SataDevice->satSignature[0], + SataDevice->satSignature[1], + SataDevice->satSignature[2], + SataDevice->satSignature[3], + SataDevice->satSignature[4])); + sataDeviceType = tddmSATADeviceTypeDecode(SataDevice->satSignature); + if( sataDeviceType == SATA_ATAPI_DEVICE) + { + SataDevice->agDeviceInfo.flag |= ATAPI_DEVICE_FLAG; + } + SataDevice->dmDeviceInfo.sataDeviceType = sataDeviceType; + } + /* Handling DataDomain buggy FIS */ + else if (fis->h.error == REG_DEV_TO_HOST_FIS) + { + /* needs to flip fis to host order */ + bit8fis = (bit8*)fis; + for (i=0;i<5;i++) + { + a = DMA_LEBIT32_TO_BIT32(*(bit32*)bit8fis); + DM_DBG3(("dmReportPhySata2Rcvd: a 0x%8x\n", a)); + bit8fisarray[4*i] = (a & 0xFF000000) >> 24; + bit8fisarray[4*i+1] = (a & 0x00FF0000) >> 16; + bit8fisarray[4*i+2] = (a & 0x0000FF00) >> 8; + bit8fisarray[4*i+3] = (a & 0x000000FF); + bit8fis = bit8fis + 4; + } + fis = (agsaFisRegDeviceToHost_t*) bit8fisarray; + /* save signature */ + DM_DBG3(("dmReportPhySata2Rcvd: DataDomain ATAPI saves the signature\n")); + /* saves signature */ + SataDevice->satSignature[0] = fis->d.sectorCount; + SataDevice->satSignature[1] = fis->d.lbaLow; + SataDevice->satSignature[2] = fis->d.lbaMid; + SataDevice->satSignature[3] = fis->d.lbaHigh; + SataDevice->satSignature[4] = fis->d.device; + SataDevice->satSignature[5] = 0; + SataDevice->satSignature[6] = 0; + SataDevice->satSignature[7] = 0; + DM_DBG3(("dmReportPhySata2Rcvd: SATA Signature = %02x %02x %02x %02x %02x\n", + SataDevice->satSignature[0], + SataDevice->satSignature[1], + SataDevice->satSignature[2], + SataDevice->satSignature[3], + SataDevice->satSignature[4])); + + sataDeviceType = tddmSATADeviceTypeDecode(SataDevice->satSignature); + if( sataDeviceType == SATA_ATAPI_DEVICE) + { + SataDevice->agDeviceInfo.flag |= ATAPI_DEVICE_FLAG; + } + SataDevice->dmDeviceInfo.sataDeviceType = sataDeviceType; + } + else + { + DM_DBG3(("dmReportPhySata2Rcvd: getting next stp bride\n")); + } + + /* Continue to report this STP device to TD*/ + if (SataDevice->ExpDevice != agNULL) + { + tddmReportDevice(dmRoot, onePortContext->dmPortContext, &SataDevice->dmDeviceInfo, &SataDevice->ExpDevice->dmDeviceInfo, dmDeviceArrival); + } + else + { + tddmReportDevice(dmRoot, onePortContext->dmPortContext, &SataDevice->dmDeviceInfo, agNULL, dmDeviceArrival); + } + + } + else + { + DM_DBG3(("dmReportPhySata2Rcvd: siReportPhySataRcvd SMP function return result %x\n", + frameHeader->smpFunctionResult)); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + + return; +} + + + +osGLOBAL bit32 +dmRoutingEntryAdd( + dmRoot_t *dmRoot, + dmExpander_t *oneExpander, + bit32 phyId, + bit32 configSASAddressHi, + bit32 configSASAddressLo + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + agsaRoot_t *agRoot = dmAllShared->agRoot; + bit32 ret = agTRUE; + dmIntPortContext_t *onePortContext; + smpReqConfigureRouteInformation_t confRoutingInfo; + bit32 i; + + DM_DBG3(("dmRoutingEntryAdd: start\n")); + DM_DBG3(("dmRoutingEntryAdd: exp addrHi 0x%08x\n", oneExpander->dmDevice->SASAddressID.sasAddressHi)); + DM_DBG3(("dmRoutingEntryAdd: exp addrLo 0x%08x\n", oneExpander->dmDevice->SASAddressID.sasAddressLo)); + DM_DBG3(("dmRoutingEntryAdd: phyid %d\n", phyId)); + + if (oneExpander->dmDevice->SASAddressID.sasAddressHi == configSASAddressHi && + oneExpander->dmDevice->SASAddressID.sasAddressLo == configSASAddressLo + ) + { + DM_DBG3(("dmRoutingEntryAdd: unnecessary\n")); + return ret; + } + if (oneExpander->routingAttribute[phyId] != SAS_ROUTING_TABLE) + { + DM_DBG3(("dmRoutingEntryAdd: not table routing, routing is %d\n", oneExpander->routingAttribute[phyId])); + return ret; + } + + onePortContext = oneExpander->dmDevice->dmPortContext; + + onePortContext->discovery.status = DISCOVERY_CONFIG_ROUTING; + + /* reset smpReqConfigureRouteInformation_t */ + dm_memset(&confRoutingInfo, 0, sizeof(smpReqConfigureRouteInformation_t)); + if ( oneExpander->currentIndex[phyId] < oneExpander->routingIndex ) + { + DM_DBG3(("dmRoutingEntryAdd: adding sasAddressHi 0x%08x\n", configSASAddressHi)); + DM_DBG3(("dmRoutingEntryAdd: adding sasAddressLo 0x%08x\n", configSASAddressLo)); + DM_DBG3(("dmRoutingEntryAdd: phyid %d currentIndex[phyid] %d\n", phyId, oneExpander->currentIndex[phyId])); + + oneExpander->configSASAddressHi = configSASAddressHi; + oneExpander->configSASAddressLo = configSASAddressLo; + confRoutingInfo.reserved1[0] = 0; + confRoutingInfo.reserved1[1] = 0; + OSSA_WRITE_BE_16(agRoot, confRoutingInfo.expanderRouteIndex, 0, (oneExpander->currentIndex[phyId])); + confRoutingInfo.reserved2 = 0; + confRoutingInfo.phyIdentifier = (bit8)phyId; + confRoutingInfo.reserved3[0] = 0; + confRoutingInfo.reserved3[1] = 0; + confRoutingInfo.disabledBit_reserved4 = 0; + confRoutingInfo.reserved5[0] = 0; + confRoutingInfo.reserved5[1] = 0; + confRoutingInfo.reserved5[2] = 0; + OSSA_WRITE_BE_32(agRoot, confRoutingInfo.routedSasAddressHi, 0, configSASAddressHi); + OSSA_WRITE_BE_32(agRoot, confRoutingInfo.routedSasAddressLo, 0, configSASAddressLo); + for ( i = 0; i < 16; i ++ ) + { + confRoutingInfo.reserved6[i] = 0; + } + dmSMPStart(dmRoot, agRoot, oneExpander->dmDevice, SMP_CONFIGURE_ROUTING_INFORMATION, (bit8 *)&confRoutingInfo, sizeof(smpReqConfigureRouteInformation_t), AGSA_SMP_INIT_REQ); + + oneExpander->currentIndex[phyId] ++; + } + else + { + DM_DBG3(("dmRoutingEntryAdd: Discovery Error routing index overflow for currentIndex=%d, routingIndex=%d\n", oneExpander->currentIndex[phyId], oneExpander->routingIndex)); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + + ret = agFALSE; + } + return ret; +} + + +osGLOBAL void +dmConfigRoutingInfoRespRcvd( + dmRoot_t *dmRoot, + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + dmDeviceData_t *oneDeviceData, + dmSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ) +{ + dmIntPortContext_t *onePortContext; + dmExpander_t *oneExpander = oneDeviceData->dmExpander; + dmExpander_t *UpStreamExpander; + dmExpander_t *DownStreamExpander; + dmExpander_t *ReturningExpander; + dmExpander_t *ConfigurableExpander; + dmDeviceData_t *ReturningExpanderDeviceData = agNULL; + bit32 dupConfigSASAddr = agFALSE; + + + DM_DBG3(("dmConfigRoutingInfoRespRcvd: start\n")); + DM_DBG3(("dmConfigRoutingInfoRespRcvd: exp addrHi 0x%08x\n", oneExpander->dmDevice->SASAddressID.sasAddressHi)); + DM_DBG3(("dmConfigRoutingInfoRespRcvd: exp addrLo 0x%08x\n", oneExpander->dmDevice->SASAddressID.sasAddressLo)); + + onePortContext = oneDeviceData->dmPortContext; + + if (dmDiscoverCheck(dmRoot, onePortContext) == agTRUE) + { + DM_DBG1(("dmConfigRoutingInfoRespRcvd: invalid port or aborted discovery!!!\n")); + return; + } + + if ( frameHeader->smpFunctionResult == SMP_FUNCTION_ACCEPTED || + frameHeader->smpFunctionResult == PHY_VACANT + ) + { + DownStreamExpander = oneExpander->dmCurrentDownStreamExpander; + if (DownStreamExpander != agNULL) + { + DownStreamExpander->currentUpStreamPhyIndex ++; + DM_DBG3(("dmConfigRoutingInfoRespRcvd: DownStreamExpander->currentUpStreamPhyIndex %d\n", DownStreamExpander->currentUpStreamPhyIndex)); + DM_DBG3(("dmConfigRoutingInfoRespRcvd: DownStreamExpander->numOfUpStreamPhys %d\n", DownStreamExpander->numOfUpStreamPhys)); + DM_DBG3(("dmConfigRoutingInfoRespRcvd: DownStreamExpander addrHi 0x%08x\n", DownStreamExpander->dmDevice->SASAddressID.sasAddressHi)); + DM_DBG3(("dmConfigRoutingInfoRespRcvd: DownStreamExpander addrLo 0x%08x\n", DownStreamExpander->dmDevice->SASAddressID.sasAddressLo)); + + } + + oneExpander->currentDownStreamPhyIndex++; + DM_DBG3(("dmConfigRoutingInfoRespRcvd: oneExpander->currentDownStreamPhyIndex %d oneExpander->numOfDownStreamPhys %d\n", oneExpander->currentDownStreamPhyIndex, oneExpander->numOfDownStreamPhys)); + + if ( (DownStreamExpander != agNULL) && + (DownStreamExpander->currentUpStreamPhyIndex < DownStreamExpander->numOfUpStreamPhys) + ) + { + DM_DBG3(("dmConfigRoutingInfoRespRcvd: first if\n")); + DM_DBG3(("dmConfigRoutingInfoRespRcvd: DownStreamExpander->currentUpStreamPhyIndex %d\n", DownStreamExpander->currentUpStreamPhyIndex)); + + DM_DBG3(("dmConfigRoutingInfoRespRcvd: DownStreamExpander->upStreamPhys[] %d\n", DownStreamExpander->upStreamPhys[DownStreamExpander->currentUpStreamPhyIndex])); + + dmRoutingEntryAdd(dmRoot, + oneExpander, + DownStreamExpander->upStreamPhys[DownStreamExpander->currentUpStreamPhyIndex], + oneExpander->configSASAddressHi, + oneExpander->configSASAddressLo + ); + } + else + { + /* traversing up till discovery Root onePortContext->discovery.RootExp */ + DM_DBG3(("dmConfigRoutingInfoRespRcvd: else\n")); + + UpStreamExpander = oneExpander->dmUpStreamExpander; + ConfigurableExpander = dmFindConfigurableExp(dmRoot, onePortContext, oneExpander); + if (UpStreamExpander != agNULL) + { + DM_DBG3(("dmConfigRoutingInfoRespRcvd: UpStreamExpander addrHi 0x%08x\n", UpStreamExpander->dmDevice->SASAddressID.sasAddressHi)); + DM_DBG3(("dmConfigRoutingInfoRespRcvd: UpStreamExpander addrLo 0x%08x\n", UpStreamExpander->dmDevice->SASAddressID.sasAddressLo)); + } + else + { + DM_DBG3(("dmConfigRoutingInfoRespRcvd: UpStreamExpander is NULL\n")); + } + dupConfigSASAddr = dmDuplicateConfigSASAddr(dmRoot, + ConfigurableExpander, + oneExpander->configSASAddressHi, + oneExpander->configSASAddressLo + ); + + if ( ConfigurableExpander != agNULL && dupConfigSASAddr == agFALSE) + { + DM_DBG3(("dmConfigRoutingInfoRespRcvd: else if\n")); + + DM_DBG3(("dmConfigRoutingInfoRespRcvd: ConfigurableExpander addrHi 0x%08x\n", ConfigurableExpander->dmDevice->SASAddressID.sasAddressHi)); + DM_DBG3(("dmConfigRoutingInfoRespRcvd: ConfigurableExpander addrLo 0x%08x\n", ConfigurableExpander->dmDevice->SASAddressID.sasAddressLo)); + + if ( UpStreamExpander != agNULL) + { + UpStreamExpander->dmCurrentDownStreamExpander = oneExpander; + } + ConfigurableExpander->currentDownStreamPhyIndex = + dmFindCurrentDownStreamPhyIndex(dmRoot, ConfigurableExpander); + ConfigurableExpander->dmReturnginExpander = oneExpander->dmReturnginExpander; + if ( DownStreamExpander != agNULL) + { + DownStreamExpander->currentUpStreamPhyIndex = 0; + } + DM_DBG3(("dmConfigRoutingInfoRespRcvd: ConfigurableExpander->currentDownStreamPhyIndex %d\n", ConfigurableExpander->currentDownStreamPhyIndex)); + + DM_DBG3(("dmConfigRoutingInfoRespRcvd: ConfigurableExpander->downStreamPhys[] %d\n", ConfigurableExpander->downStreamPhys[ConfigurableExpander->currentDownStreamPhyIndex])); + dmRoutingEntryAdd(dmRoot, + ConfigurableExpander, + ConfigurableExpander->downStreamPhys[ConfigurableExpander->currentDownStreamPhyIndex], + oneExpander->configSASAddressHi, + oneExpander->configSASAddressLo + ); + } + else + { + /* going back to where it was */ + /* ConfigRoutingInfo is done for a target */ + DM_DBG3(("dmConfigRoutingInfoRespRcvd: $$$$$$ my change $$$$$ \n")); + ReturningExpander = oneExpander->dmReturnginExpander; + if ( DownStreamExpander != agNULL) + { + DownStreamExpander->currentUpStreamPhyIndex = 0; + } + /* debugging */ + if (ReturningExpander != agNULL) + { + DM_DBG3(("dmConfigRoutingInfoRespRcvd: ReturningExpander addrHi 0x%08x\n", ReturningExpander->dmDevice->SASAddressID.sasAddressHi)); + DM_DBG3(("dmConfigRoutingInfoRespRcvd: ReturningExpander addrLo 0x%08x\n", ReturningExpander->dmDevice->SASAddressID.sasAddressLo)); + ReturningExpanderDeviceData = ReturningExpander->dmDevice; + } + + /* No longer in DISCOVERY_CONFIG_ROUTING */ + onePortContext->discovery.status = DISCOVERY_DOWN_STREAM; + + if (ReturningExpander != agNULL && ReturningExpanderDeviceData != agNULL) + { + /* If not the last phy */ + if ( ReturningExpander->discoveringPhyId < ReturningExpanderDeviceData->numOfPhys ) + { + DM_DBG3(("dmConfigRoutingInfoRespRcvd: More Phys to discover\n")); + /* continue discovery for the next phy */ + /* needs to send only one Discovery not multiple times */ + if (ReturningExpander->discoverSMPAllowed == agTRUE) + { + dmDiscoverSend(dmRoot, ReturningExpanderDeviceData); + } + if (ReturningExpander != agNULL) + { + ReturningExpander->discoverSMPAllowed = agFALSE; + } + } + /* If the last phy */ + else + { + DM_DBG3(("dmConfigRoutingInfoRespRcvd: No More Phys\n")); + ReturningExpander->discoverSMPAllowed = agTRUE; + + /* remove the expander from the discovering list */ + dmDiscoveringExpanderRemove(dmRoot, onePortContext, ReturningExpander); + /* continue downstream discovering */ + dmDownStreamDiscovering(dmRoot, onePortContext, ReturningExpanderDeviceData); + + //DownStreamExpander + } + } + } + } + } + else + { + DM_DBG1(("dmConfigRoutingInfoRespRcvd: Discovery Error SMP function return result error=0x%x !!!\n", frameHeader->smpFunctionResult)); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + return; +} + +osGLOBAL void +dmConfigRoutingInfo2RespRcvd( + dmRoot_t *dmRoot, + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + dmDeviceData_t *oneDeviceData, + dmSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ) +{ + dmExpander_t *oneExpander = oneDeviceData->dmExpander; + dmExpander_t *UpStreamExpander; + dmExpander_t *DownStreamExpander; + dmExpander_t *ReturningExpander; + dmExpander_t *ConfigurableExpander; + + dmIntPortContext_t *onePortContext; + dmDeviceData_t *ReturningExpanderDeviceData = agNULL; + bit32 dupConfigSASAddr = agFALSE; + + DM_DBG2(("dmConfigRoutingInfo2RespRcvd: start\n")); + DM_DBG2(("dmConfigRoutingInfo2RespRcvd: exp addrHi 0x%08x\n", oneExpander->dmDevice->SASAddressID.sasAddressHi)); + DM_DBG2(("dmConfigRoutingInfo2RespRcvd: exp addrLo 0x%08x\n", oneExpander->dmDevice->SASAddressID.sasAddressLo)); + + onePortContext = oneDeviceData->dmPortContext; + + if (dmDiscoverCheck(dmRoot, onePortContext) == agTRUE) + { + DM_DBG1(("dmConfigRoutingInfo2RespRcvd: invalid port or aborted discovery!!!\n")); + return; + } + + if (frameHeader->smpFunctionResult == PHY_VACANT) + { + DM_DBG1(("dmConfigRoutingInfo2RespRcvd: smpFunctionResult is PHY_VACANT\n")); + } + + if ( frameHeader->smpFunctionResult == SMP_FUNCTION_ACCEPTED || + frameHeader->smpFunctionResult == PHY_VACANT + ) + { + DownStreamExpander = oneExpander->dmCurrentDownStreamExpander; + if (DownStreamExpander != agNULL) + { + DownStreamExpander->currentUpStreamPhyIndex ++; + DM_DBG2(("dmConfigRoutingInfo2RespRcvd: DownStreamExpander->currentUpStreamPhyIndex %d\n", DownStreamExpander->currentUpStreamPhyIndex)); + DM_DBG2(("dmConfigRoutingInfo2RespRcvd: DownStreamExpander->numOfUpStreamPhys %d\n", DownStreamExpander->numOfUpStreamPhys)); + DM_DBG2(("dmConfigRoutingInfo2RespRcvd: DownStreamExpander addrHi 0x%08x\n", DownStreamExpander->dmDevice->SASAddressID.sasAddressHi)); + DM_DBG2(("dmConfigRoutingInfo2RespRcvd: DownStreamExpander addrLo 0x%08x\n", DownStreamExpander->dmDevice->SASAddressID.sasAddressLo)); + + } + + oneExpander->currentDownStreamPhyIndex++; + DM_DBG2(("dmConfigRoutingInfo2RespRcvd: oneExpander->currentDownStreamPhyIndex %d oneExpander->numOfDownStreamPhys %d\n", oneExpander->currentDownStreamPhyIndex, oneExpander->numOfDownStreamPhys)); + + if ( (DownStreamExpander != agNULL) && + (DownStreamExpander->currentUpStreamPhyIndex < DownStreamExpander->numOfUpStreamPhys) + ) + { + DM_DBG2(("dmConfigRoutingInfo2RespRcvd: first if\n")); + DM_DBG2(("dmConfigRoutingInfo2RespRcvd: DownStreamExpander->currentUpStreamPhyIndex %d\n", DownStreamExpander->currentUpStreamPhyIndex)); + + DM_DBG2(("dmConfigRoutingInfo2RespRcvd: DownStreamExpander->upStreamPhys[] %d\n", DownStreamExpander->upStreamPhys[DownStreamExpander->currentUpStreamPhyIndex])); + + dmRoutingEntryAdd(dmRoot, + oneExpander, + DownStreamExpander->upStreamPhys[DownStreamExpander->currentUpStreamPhyIndex], + oneExpander->configSASAddressHi, + oneExpander->configSASAddressLo + ); + } + else + { + /* traversing up till discovery Root onePortContext->discovery.RootExp */ + DM_DBG2(("dmConfigRoutingInfo2RespRcvd: else\n")); + + UpStreamExpander = oneExpander->dmUpStreamExpander; + ConfigurableExpander = dmFindConfigurableExp(dmRoot, onePortContext, oneExpander); + if (UpStreamExpander != agNULL) + { + DM_DBG2(("dmConfigRoutingInfo2RespRcvd: UpStreamExpander addrHi 0x%08x\n", UpStreamExpander->dmDevice->SASAddressID.sasAddressHi)); + DM_DBG2(("dmConfigRoutingInfo2RespRcvd: UpStreamExpander addrLo 0x%08x\n", UpStreamExpander->dmDevice->SASAddressID.sasAddressLo)); + } + else + { + DM_DBG2(("dmConfigRoutingInfo2RespRcvd: UpStreamExpander is NULL\n")); + } + dupConfigSASAddr = dmDuplicateConfigSASAddr(dmRoot, + ConfigurableExpander, + oneExpander->configSASAddressHi, + oneExpander->configSASAddressLo + ); + + if ( ConfigurableExpander != agNULL && dupConfigSASAddr == agFALSE) + { + DM_DBG2(("dmConfigRoutingInfo2RespRcvd: else if\n")); + + DM_DBG2(("dmConfigRoutingInfo2RespRcvd: ConfigurableExpander addrHi 0x%08x\n", ConfigurableExpander->dmDevice->SASAddressID.sasAddressHi)); + DM_DBG2(("dmConfigRoutingInfo2RespRcvd: ConfigurableExpander addrLo 0x%08x\n", ConfigurableExpander->dmDevice->SASAddressID.sasAddressLo)); + + if ( UpStreamExpander != agNULL) + { + UpStreamExpander->dmCurrentDownStreamExpander = oneExpander; + } + ConfigurableExpander->currentDownStreamPhyIndex = + dmFindCurrentDownStreamPhyIndex(dmRoot, ConfigurableExpander); + ConfigurableExpander->dmReturnginExpander = oneExpander->dmReturnginExpander; + if ( DownStreamExpander != agNULL) + { + DownStreamExpander->currentUpStreamPhyIndex = 0; + } + DM_DBG2(("dmConfigRoutingInfo2RespRcvd: ConfigurableExpander->currentDownStreamPhyIndex %d\n", ConfigurableExpander->currentDownStreamPhyIndex)); + + DM_DBG2(("dmConfigRoutingInfo2RespRcvd: ConfigurableExpander->downStreamPhys[] %d\n", ConfigurableExpander->downStreamPhys[ConfigurableExpander->currentDownStreamPhyIndex])); + dmRoutingEntryAdd(dmRoot, + ConfigurableExpander, + ConfigurableExpander->downStreamPhys[ConfigurableExpander->currentDownStreamPhyIndex], + oneExpander->configSASAddressHi, + oneExpander->configSASAddressLo + ); + } + else + { + /* going back to where it was */ + /* ConfigRoutingInfo is done for a target */ + DM_DBG2(("dmConfigRoutingInfo2RespRcvd: $$$$$$ my change $$$$$ \n")); + ReturningExpander = oneExpander->dmReturnginExpander; + if ( DownStreamExpander != agNULL) + { + DownStreamExpander->currentUpStreamPhyIndex = 0; + } + /* debugging */ + if (ReturningExpander != agNULL) + { + DM_DBG2(("dmConfigRoutingInfo2RespRcvd: ReturningExpander addrHi 0x%08x\n", ReturningExpander->dmDevice->SASAddressID.sasAddressHi)); + DM_DBG2(("dmConfigRoutingInfo2RespRcvd: ReturningExpander addrLo 0x%08x\n", ReturningExpander->dmDevice->SASAddressID.sasAddressLo)); + ReturningExpanderDeviceData = ReturningExpander->dmDevice; + } + + /* No longer in DISCOVERY_CONFIG_ROUTING */ + onePortContext->discovery.status = DISCOVERY_DOWN_STREAM; + + if (ReturningExpander != agNULL && ReturningExpanderDeviceData != agNULL) + { + /* If not the last phy */ + if ( ReturningExpander->discoveringPhyId < ReturningExpanderDeviceData->numOfPhys ) + { + DM_DBG2(("dmConfigRoutingInfo2RespRcvd: More Phys to discover\n")); + /* continue discovery for the next phy */ + /* needs to send only one Discovery not multiple times */ + if (ReturningExpander->discoverSMPAllowed == agTRUE) + { + dmDiscoverSend(dmRoot, ReturningExpanderDeviceData); + } + if (ReturningExpander != agNULL) + { + ReturningExpander->discoverSMPAllowed = agFALSE; + } + } + /* If the last phy */ + else + { + DM_DBG2(("dmConfigRoutingInfo2RespRcvd: No More Phys\n")); + ReturningExpander->discoverSMPAllowed = agTRUE; + + /* remove the expander from the discovering list */ + dmDiscoveringExpanderRemove(dmRoot, onePortContext, ReturningExpander); + /* continue downstream discovering */ + dmDownStreamDiscovering(dmRoot, onePortContext, ReturningExpanderDeviceData); + + //DownStreamExpander + } + } + } + } + } + else + { + DM_DBG1(("dmConfigRoutingInfo2RespRcvd: Discovery Error SMP function return result error=0x%x!!!\n", frameHeader->smpFunctionResult)); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + return; +} + + +/* no task management case here for phyControl*/ + +/* no task management case here for phyControl*/ +osGLOBAL void +dmPhyControlRespRcvd( + dmRoot_t *dmRoot, + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + dmDeviceData_t *oneDeviceData, + dmSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ) +{ + DM_DBG3(("dmPhyControlRespRcvd: start\n")); + DM_DBG3(("dmPhyControlRespRcvd: expander device AddrHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG3(("dmPhyControlRespRcvd: expander device AddrLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + + if (frameHeader->smpFunctionResult == SMP_FUNCTION_ACCEPTED) + { + DM_DBG3(("dmPhyControlRespRcvd: SMP success\n")); + } + else + { + DM_DBG1(("dmPhyControlRespRcvd: SMP failure; result 0x%x !!!\n", frameHeader->smpFunctionResult)); + } + + return; +} + +/* no task management case here for phyControl*/ +osGLOBAL void +dmPhyControl2RespRcvd( + dmRoot_t *dmRoot, + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + dmDeviceData_t *oneDeviceData, + dmSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ) +{ + DM_DBG2(("dmPhyControl2RespRcvd: start\n")); + DM_DBG2(("dmPhyControl2RespRcvd: expander device AddrHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + DM_DBG2(("dmPhyControl2RespRcvd: expander device AddrLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + + if (frameHeader->smpFunctionResult == SMP_FUNCTION_ACCEPTED) + { + DM_DBG2(("dmPhyControl2RespRcvd: SMP success\n")); + } + else + { + DM_DBG1(("dmPhyControl2RespRcvd: SMP failure; result 0x%x !!!\n", frameHeader->smpFunctionResult)); + } + + return; +} + +osGLOBAL void +dmPhyControlFailureRespRcvd( + dmRoot_t *dmRoot, + agsaRoot_t *agRoot, + dmDeviceData_t *oneDeviceData, + dmSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ) +{ + DM_DBG1(("dmPhyControlFailureRespRcvd: start\n")); + return; +} + +GLOBAL void dmSetDeviceInfoCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaDevHandle_t *agDevHandle, + bit32 status, + bit32 option, + bit32 param + ) +{ + dmRoot_t *dmRoot = agNULL; + agsaIORequest_t *agIORequest; + bit32 smstatus; + agsaSASRequestBody_t *agSASRequestBody; + dmSMPRequestBody_t *dmSMPRequestBody = agNULL; + dmIntPortContext_t *onePortContext = agNULL; + dmDeviceData_t *oneDeviceData; + bit8 SMPRequestFunction; + bit8 devType_S_Rate; + DM_DBG1(("dmSetDeviceInfoCB: start\n")); + DM_DBG4(("dmSetDeviceInfoCB: status 0x%x\n", status)); + DM_DBG4(("dmSetDeviceInfoCB: option 0x%x\n", option)); + DM_DBG4(("dmSetDeviceInfoCB: param 0x%x\n", param)); + if (status != OSSA_SUCCESS) + { + DM_DBG1(("dmSetDeviceInfoCB: status %d\n", status)); + DM_DBG1(("dmSetDeviceInfoCB: option 0x%x\n", option)); + DM_DBG1(("dmSetDeviceInfoCB: param 0x%x\n", param)); + if (option == 32) /* set connection rate */ + { + DM_DBG1(("dmSetDeviceInfoCB: IO failure\n")); + agIORequest = (agsaIORequest_t *)agContext->osData; + dmSMPRequestBody = (dmSMPRequestBody_t *)agIORequest->osData; + dmRoot = dmSMPRequestBody->dmRoot; + oneDeviceData = dmSMPRequestBody->dmDevice; + onePortContext = oneDeviceData->dmPortContext; + SMPRequestFunction = dmSMPRequestBody->smpPayload[1]; + if (SMPRequestFunction == SMP_REPORT_GENERAL || + SMPRequestFunction == SMP_DISCOVER || + SMPRequestFunction == SMP_REPORT_PHY_SATA || + SMPRequestFunction == SMP_CONFIGURE_ROUTING_INFORMATION + ) + { + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + else if (SMPRequestFunction == SMP_PHY_CONTROL) + { + /* task management failure */ + dmPhyControlFailureRespRcvd( + dmRoot, + agRoot, + oneDeviceData, + agNULL, + agNULL + ); + } + } + } + if (agDevHandle == agNULL) + { + DM_DBG1(("dmSetDeviceInfoCB: agDevHandle is NULL\n")); + return; + } + + /* retry SMP */ + if (option == 32) /* set connection rate */ + { + DM_DBG1(("dmSetDeviceInfoCB: set connection rate option\n")); + agIORequest = (agsaIORequest_t *)agContext->osData; + dmSMPRequestBody = (dmSMPRequestBody_t *)agIORequest->osData; + dmRoot = dmSMPRequestBody->dmRoot; + agSASRequestBody = &(dmSMPRequestBody->agSASRequestBody); + oneDeviceData = dmSMPRequestBody->dmDevice; + onePortContext = oneDeviceData->dmPortContext; + devType_S_Rate = oneDeviceData->agDeviceInfo.devType_S_Rate; + devType_S_Rate = (devType_S_Rate & 0xF0) | (param >> 28); + oneDeviceData->agDeviceInfo.devType_S_Rate = devType_S_Rate; + SMPRequestFunction = dmSMPRequestBody->smpPayload[1]; + DM_DBG1(("dmSetDeviceInfoCB: SMPRequestFunction 0x%x\n", SMPRequestFunction)); + DM_DBG1(("dmSetDeviceInfoCB: new rate is 0x%x\n", DEVINFO_GET_LINKRATE(&oneDeviceData->agDeviceInfo))); + smstatus = saSMPStart( + agRoot, + agIORequest, + 0, + agDevHandle, + AGSA_SMP_INIT_REQ, + agSASRequestBody, + &dmsaSMPCompleted + ); + if (status == AGSA_RC_SUCCESS) + { + /* increment the number of pending SMP */ + onePortContext->discovery.pendingSMP++; +// dmSMPRequestBody->retries++; + if (SMPRequestFunction == SMP_REPORT_GENERAL || SMPRequestFunction == SMP_DISCOVER || + SMPRequestFunction == SMP_REPORT_PHY_SATA || + SMPRequestFunction == SMP_CONFIGURE_ROUTING_INFORMATION + ) + { + /* start discovery-related SMP timer */ + dmDiscoverySMPTimer(dmRoot, onePortContext, (bit32)SMPRequestFunction, dmSMPRequestBody); + } + return; + } + else if (status == AGSA_RC_BUSY) + { + onePortContext->discovery.pendingSMP++; +// dmSMPRequestBody->retries++; + if (SMPRequestFunction == SMP_REPORT_GENERAL || + SMPRequestFunction == SMP_DISCOVER || + SMPRequestFunction == SMP_REPORT_PHY_SATA || + SMPRequestFunction == SMP_CONFIGURE_ROUTING_INFORMATION + ) + { + dmSMPBusyTimer(dmRoot, onePortContext, oneDeviceData, dmSMPRequestBody); + } + else if (SMPRequestFunction == SMP_PHY_CONTROL) + { + /* For taskmanagement SMP, let's fail task management failure */ + dmPhyControlFailureRespRcvd( + dmRoot, + agRoot, + oneDeviceData, + agNULL, + agNULL + ); + } + else + { + } + } + else /* AGSA_RC_FAILURE */ + { + if (SMPRequestFunction == SMP_REPORT_GENERAL || + SMPRequestFunction == SMP_DISCOVER || + SMPRequestFunction == SMP_REPORT_PHY_SATA || + SMPRequestFunction == SMP_CONFIGURE_ROUTING_INFORMATION + ) + { + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + else if (SMPRequestFunction == SMP_PHY_CONTROL) + { + /* task management failure */ + dmPhyControlFailureRespRcvd( + dmRoot, + agRoot, + oneDeviceData, + agNULL, + agNULL + ); + } + else + { + } + } + } + return; +} +/* smp completion */ +osGLOBAL void +dmSMPCompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle + ) +{ + dmIntRoot_t *dmIntRoot = agNULL; + dmIntContext_t *dmAllShared = agNULL; + dmSMPRequestBody_t *dmSMPRequestBody = agNULL; + agsaSMPFrame_t *agSMPFrame; + dmRoot_t *dmRoot = agNULL; + dmIntPortContext_t *onePortContext = agNULL; + dmIntPortContext_t *oldonePortContext; + dmExpander_t *oneExpander = agNULL; + dmDeviceData_t *oneDeviceData; + agsaDevHandle_t *agDevHandle = agNULL; + agsaSASRequestBody_t *agSASRequestBody; + bit8 smpHeader[4]; + bit8 SMPRequestFunction; + dmSMPFrameHeader_t *dmResponseSMPFrameHeader; + dmSMPFrameHeader_t *dmSMPFrameHeader; + bit8 *dmSMPPayload; + smpReqPhyControl_t *smpPhyControlReq; + smpReqPhyControl2_t *smpPhyControl2Req; +#ifndef DIRECT_SMP + dmSMPRequestBody_t *dmSMPResponseBody = agNULL; + dmSMPFrameHeader_t *dmRequestSMPFrameHeader; + bit8 smpRequestHeader[4]; +#endif + bit32 status; + bit32 ConnRate = SAS_CONNECTION_RATE_12_0G; + agsaContext_t *agContext = agNULL; + + DM_DBG3(("dmSMPCompleted: start\n")); + + dmSMPRequestBody = (dmSMPRequestBody_t *)agIORequest->osData; + + dmRoot = dmSMPRequestBody->dmRoot; + dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + + oneDeviceData = dmSMPRequestBody->dmDevice; + agSASRequestBody = &(dmSMPRequestBody->agSASRequestBody); + agSMPFrame = &(agSASRequestBody->smpFrame); + + if (oneDeviceData->valid == agFALSE && + oneDeviceData->valid2 == agFALSE && + oneDeviceData->dmPortContext == agNULL && + dmSMPRequestBody->dmPortContext->valid == agFALSE + ) + { + DM_DBG3(("dmSMPCompleted: port has been destroyed\n")); + /* all device, port information have been reset + just put smp to freeList + */ + /* SMP request */ + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPRequestBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); + +#ifndef DIRECT_SMP + /* SMP response */ + dmSMPResponseBody = (dmSMPRequestBody_t *)dmSMPRequestBody->IndirectSMPResponse; + if (dmSMPResponseBody == agNULL) + { + DM_DBG1(("dmSMPCompleted: Wrong, dmSMPResponseBody is NULL!!!\n")); + return; + } + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPResponseBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); +#endif + return; + } + + onePortContext = oneDeviceData->dmPortContext; + oneExpander = oneDeviceData->dmExpander; + agDevHandle = oneExpander->agDevHandle; + + +#ifdef DIRECT_SMP + SMPRequestFunction = dmSMPRequestBody->smpPayload[1]; +#else + saFrameReadBlock(agRoot, dmSMPRequestBody->IndirectSMP, 0, smpRequestHeader, 4); + dmRequestSMPFrameHeader = (dmSMPFrameHeader_t *)smpRequestHeader; + SMPRequestFunction = dmRequestSMPFrameHeader->smpFunction; +#endif + +#ifdef NOT_IN_USE + /* for debugging; dump SMP request payload */ + dmhexdump("smp payload", + (bit8 *)agSASRequestBody->smpFrame.outFrameBuf, + agSASRequestBody->smpFrame.outFrameLen + ); + dmhexdump("smp payload new", + (bit8 *)dmSMPRequestBody->smpPayload, + agSASRequestBody->smpFrame.outFrameLen + ); +#endif + + /* sanity check */ + if (onePortContext != agNULL) + { + DM_DBG5(("dmSMPCompleted: pid %d\n", onePortContext->id)); + } + else + { + DM_DBG1(("dmSMPCompleted: Wrong, onePortContext is NULL!!!\n")); + /* SMP request */ + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPRequestBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); + +#ifndef DIRECT_SMP + /* SMP response */ + dmSMPResponseBody = (dmSMPRequestBody_t *)dmSMPRequestBody->IndirectSMPResponse; + if (dmSMPResponseBody == agNULL) + { + DM_DBG1(("dmSMPCompleted: Wrong, dmSMPResponseBody is NULL!!!\n")); + return; + } + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPResponseBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); +#endif + return; + } + + oldonePortContext = dmSMPRequestBody->dmPortContext; + if (oldonePortContext != agNULL) + { + DM_DBG5(("dmSMPCompleted: old pid %d\n", oldonePortContext->id)); + } + else + { + DM_DBG1(("dmSMPCompleted: Wrong, oldonePortContext is NULL!!!\n")); + /* SMP request */ + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPRequestBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); + +#ifndef DIRECT_SMP + /* SMP response */ + dmSMPResponseBody = (dmSMPRequestBody_t *)dmSMPRequestBody->IndirectSMPResponse; + if (dmSMPResponseBody == agNULL) + { + DM_DBG1(("dmSMPCompleted: Wrong, dmSMPResponseBody is NULL!!!\n")); + return; + } + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPResponseBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); +#endif + return; + } + + /* decrement the number of pending SMP */ + onePortContext->discovery.pendingSMP--; + + + /* for port invalid case; + full discovery -> full discovery; incremental discovery -> full discovery + */ + if (onePortContext != oldonePortContext) + { + DM_DBG1(("dmSMPCompleted: portcontext has changed!!!\n")); + if (SMPRequestFunction == SMP_REPORT_GENERAL || SMPRequestFunction == SMP_DISCOVER || + SMPRequestFunction == SMP_REPORT_PHY_SATA || + SMPRequestFunction == SMP_CONFIGURE_ROUTING_INFORMATION + ) + { + /* stop SMP timer */ + tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK); + if (onePortContext->discovery.DiscoverySMPTimer.timerRunning == agTRUE) + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + dmKillTimer( + dmRoot, + &(onePortContext->discovery.DiscoverySMPTimer) + ); + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + } + + tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK); + if (oldonePortContext->discovery.DiscoverySMPTimer.timerRunning == agTRUE) + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + dmKillTimer( + dmRoot, + &(oldonePortContext->discovery.DiscoverySMPTimer) + ); + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + } + } + /* clean up expanders data strucures; move to free exp when device is cleaned */ + dmCleanAllExp(dmRoot, oldonePortContext); + /* remove devices */ + dmInternalRemovals(dmRoot, oldonePortContext); + + /* SMP request */ + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPRequestBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); + +#ifndef DIRECT_SMP + /* SMP response */ + dmSMPResponseBody = (dmSMPRequestBody_t *)dmSMPRequestBody->IndirectSMPResponse; + if (dmSMPResponseBody == agNULL) + { + DM_DBG1(("dmSMPCompleted: Wrong, dmSMPResponseBody is NULL!!!\n")); + return; + } + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPResponseBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); +#endif + + + return; + } + + if (onePortContext->valid == agFALSE || + onePortContext->DiscoveryState == DM_DSTATE_COMPLETED || + onePortContext->discovery.status == DISCOVERY_SAS_DONE || + onePortContext->DiscoveryAbortInProgress == agTRUE + ) + { + if (SMPRequestFunction == SMP_REPORT_GENERAL || SMPRequestFunction == SMP_DISCOVER || + SMPRequestFunction == SMP_REPORT_PHY_SATA || + SMPRequestFunction == SMP_CONFIGURE_ROUTING_INFORMATION + ) + { + /* stop SMP timer */ + tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK); + if (onePortContext->discovery.DiscoverySMPTimer.timerRunning == agTRUE) + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + dmKillTimer( + dmRoot, + &(onePortContext->discovery.DiscoverySMPTimer) + ); + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + } + + + + tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK); + if (oldonePortContext->discovery.DiscoverySMPTimer.timerRunning == agTRUE) + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + dmKillTimer( + dmRoot, + &(oldonePortContext->discovery.DiscoverySMPTimer) + ); + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + } + } + + /* SMP request */ + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPRequestBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); + +#ifndef DIRECT_SMP + /* SMP response */ + dmSMPResponseBody = (dmSMPRequestBody_t *)dmSMPRequestBody->IndirectSMPResponse; + if (dmSMPResponseBody == agNULL) + { + DM_DBG1(("dmSMPCompleted: Wrong, dmSMPResponseBody is NULL!!!\n")); + return; + } + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPResponseBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); +#endif + + if (onePortContext->discovery.pendingSMP == 0) + { + DM_DBG1(("dmSMPCompleted: aborting discovery\n")); + if (onePortContext->DiscoveryState == DM_DSTATE_COMPLETED || + onePortContext->discovery.status == DISCOVERY_SAS_DONE || + onePortContext->DiscoveryAbortInProgress == agTRUE + ) + { + onePortContext->DiscoveryAbortInProgress = agFALSE; + onePortContext->DiscoveryState = DM_DSTATE_COMPLETED; + onePortContext->discovery.status = DISCOVERY_SAS_DONE; + dmCleanAllExp(dmRoot, onePortContext); + if ( onePortContext->DiscoveryAbortInProgress == agTRUE) + { + tddmDiscoverCB( + dmRoot, + onePortContext->dmPortContext, + dmDiscAborted + ); + } + } + } + else + { + DM_DBG3(("dmSMPCompleted: not yet abort; non zero pendingSMP %d\n", onePortContext->discovery.pendingSMP)); + } + return; + } + + if (SMPRequestFunction == SMP_REPORT_GENERAL || SMPRequestFunction == SMP_DISCOVER || + SMPRequestFunction == SMP_REPORT_PHY_SATA || + SMPRequestFunction == SMP_CONFIGURE_ROUTING_INFORMATION + ) + { + /* stop SMP timer */ + tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK); + if (onePortContext->discovery.DiscoverySMPTimer.timerRunning == agTRUE) + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + dmKillTimer( + dmRoot, + &(onePortContext->discovery.DiscoverySMPTimer) + ); + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + } + + + tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK); + if (oldonePortContext->discovery.DiscoverySMPTimer.timerRunning == agTRUE) + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + dmKillTimer( + dmRoot, + &(oldonePortContext->discovery.DiscoverySMPTimer) + ); + } + else + { + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + } + } + + if (oneExpander->SAS2 == 0) + { + DM_DBG3(("dmSMPCompleted: SAS 1.1\n")); + if (agIOStatus == OSSA_IO_SUCCESS) + { + //tdhexdump("dmSMPCompleted", (bit8*)agFrameHandle, agIOInfoLen); + /* parsing SMP payload */ +#ifdef DIRECT_SMP + saFrameReadBlock(agRoot, agFrameHandle, 0, smpHeader, 4); +#else + dmSMPResponseBody = (dmSMPRequestBody_t *)dmSMPRequestBody->IndirectSMPResponse; + saFrameReadBlock(agRoot, dmSMPResponseBody->IndirectSMP, 0, smpHeader, 4); +#endif + dmResponseSMPFrameHeader = (dmSMPFrameHeader_t *)smpHeader; + + /* SMP function dependent payload */ + switch (dmResponseSMPFrameHeader->smpFunction) + { + case SMP_REPORT_GENERAL: + DM_DBG3(("dmSMPCompleted: report general\n")); + if (agIOInfoLen != sizeof(smpRespReportGeneral_t) + 4 && + dmResponseSMPFrameHeader->smpFunctionResult == SMP_FUNCTION_ACCEPTED) + { + DM_DBG3(("dmSMPCompleted: mismatch len agIOInfoLen 0x%x 0x%x\n", agIOInfoLen, (unsigned int)sizeof(smpRespReportGeneral_t) + 4)); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + + /* SMP request */ + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPRequestBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); + +#ifndef DIRECT_SMP + /* SMP response */ + dmSMPResponseBody = (dmSMPRequestBody_t *)dmSMPRequestBody->IndirectSMPResponse; + if (dmSMPResponseBody == agNULL) + { + DM_DBG1(("dmSMPCompleted: Wrong, dmSMPResponseBody is NULL!!!\n")); + return; + } + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPResponseBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); +#endif + return; + } + /* start here */ + dmReportGeneralRespRcvd( + dmRoot, + agRoot, + agIORequest, + oneDeviceData, + dmResponseSMPFrameHeader, + agFrameHandle + ); + break; + case SMP_DISCOVER: + DM_DBG3(("dmSMPCompleted: discover\n")); + if (agIOInfoLen != sizeof(smpRespDiscover_t) + 4 && + dmResponseSMPFrameHeader->smpFunctionResult == SMP_FUNCTION_ACCEPTED) + { + DM_DBG3(("dmSMPCompleted: mismatch len agIOInfoLen 0x%x 0x%x\n", agIOInfoLen, (unsigned int)sizeof(smpRespDiscover_t) + 4)); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + /* SMP request */ + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPRequestBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); + +#ifndef DIRECT_SMP + /* SMP response */ + dmSMPResponseBody = (dmSMPRequestBody_t *)dmSMPRequestBody->IndirectSMPResponse; + if (dmSMPResponseBody == agNULL) + { + DM_DBG1(("dmSMPCompleted: Wrong, dmSMPResponseBody is NULL!!!\n")); + return; + } + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPResponseBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); +#endif + return; + } + dmDiscoverRespRcvd( + dmRoot, + agRoot, + agIORequest, + oneDeviceData, + dmResponseSMPFrameHeader, + agFrameHandle + ); + break; + case SMP_REPORT_PHY_SATA: + DM_DBG3(("dmSMPCompleted: report phy sata\n")); + if (agIOInfoLen != sizeof(smpRespReportPhySata_t) + 4 && + dmResponseSMPFrameHeader->smpFunctionResult == SMP_FUNCTION_ACCEPTED) + { + DM_DBG3(("dmSMPCompleted: mismatch len agIOInfoLen 0x%x 0x%x\n", agIOInfoLen, (unsigned int)sizeof(smpRespReportPhySata_t) + 4)); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + /* SMP request */ + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPRequestBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); + +#ifndef DIRECT_SMP + /* SMP response */ + dmSMPResponseBody = (dmSMPRequestBody_t *)dmSMPRequestBody->IndirectSMPResponse; + if (dmSMPResponseBody == agNULL) + { + DM_DBG1(("dmSMPCompleted: Wrong, dmSMPResponseBody is NULL!!!\n")); + return; + } + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPResponseBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); +#endif + return; + } + dmReportPhySataRcvd( + dmRoot, + agRoot, + agIORequest, + oneDeviceData, + dmResponseSMPFrameHeader, + agFrameHandle + ); + break; + case SMP_CONFIGURE_ROUTING_INFORMATION: + DM_DBG3(("dmSMPCompleted: configure routing information\n")); + if (agIOInfoLen != 4 && + dmResponseSMPFrameHeader->smpFunctionResult == SMP_FUNCTION_ACCEPTED) + { + DM_DBG3(("dmSMPCompleted: mismatch len agIOInfoLen 0x%x 0x%x\n", agIOInfoLen, 4)); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + /* SMP request */ + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPRequestBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); + +#ifndef DIRECT_SMP + /* SMP response */ + dmSMPResponseBody = (dmSMPRequestBody_t *)dmSMPRequestBody->IndirectSMPResponse; + if (dmSMPResponseBody == agNULL) + { + DM_DBG1(("dmSMPCompleted: Wrong, dmSMPResponseBody is NULL!!!\n")); + return; + } + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPResponseBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); +#endif + return; + } + dmConfigRoutingInfoRespRcvd( + dmRoot, + agRoot, + agIORequest, + oneDeviceData, + dmResponseSMPFrameHeader, + agFrameHandle + ); + + break; + case SMP_PHY_CONTROL: + DM_DBG3(("dmSMPCompleted: phy control\n")); + if (agIOInfoLen != 4 && + dmResponseSMPFrameHeader->smpFunctionResult == SMP_FUNCTION_ACCEPTED) /*zero length is expected */ + { + DM_DBG3(("dmSMPCompleted: mismatch len agIOInfoLen 0x%x 0x%x\n", agIOInfoLen, 4)); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + + /* SMP request */ + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPRequestBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); + +#ifndef DIRECT_SMP + /* SMP response */ + dmSMPResponseBody = (dmSMPRequestBody_t *)dmSMPRequestBody->IndirectSMPResponse; + if (dmSMPResponseBody == agNULL) + { + DM_DBG1(("dmSMPCompleted: Wrong, dmSMPResponseBody is NULL!!!\n")); + return; + } + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPResponseBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); +#endif + return; + } + dmPhyControlRespRcvd( + dmRoot, + agRoot, + agIORequest, + oneDeviceData, + dmResponseSMPFrameHeader, + agFrameHandle + ); + break; + case SMP_REPORT_ROUTING_INFORMATION: /* fall through */ + case SMP_REPORT_PHY_ERROR_LOG: /* fall through */ + case SMP_PHY_TEST_FUNCTION: /* fall through */ + case SMP_REPORT_MANUFACTURE_INFORMATION: /* fall through */ + case SMP_READ_GPIO_REGISTER: /* fall through */ + case SMP_WRITE_GPIO_REGISTER: /* fall through */ + default: + DM_DBG1(("dmSMPCompleted: wrong SMP function 0x%x !!!\n", dmResponseSMPFrameHeader->smpFunction)); + DM_DBG1(("dmSMPCompleted: smpFrameType 0x%x !!!\n", dmResponseSMPFrameHeader->smpFrameType)); + DM_DBG1(("dmSMPCompleted: smpFunctionResult 0x%x !!!\n", dmResponseSMPFrameHeader->smpFunctionResult)); + DM_DBG1(("dmSMPCompleted: smpReserved 0x%x !!!\n", dmResponseSMPFrameHeader->smpReserved)); + dmhexdump("dmSMPCompleted: SMP payload !!!", (bit8 *)agFrameHandle, agIOInfoLen); + break; + } /* switch */ + } /* OSSA_IO_SUCCESS */ + else if (agIOStatus == OSSA_IO_ABORTED || agIOStatus == OSSA_IO_INVALID_LENGTH) + { + /* no retry this case */ + DM_DBG1(("dmSMPCompleted: OSSA_IO_ABORTED or OSSA_IO_INVALID_LENGTH, status 0x%x\n", agIOStatus)); + } + else if (agIOStatus == OSSA_IO_ERROR_INTERNAL_SMP_RESOURCE) + { + DM_DBG3(("dmSMPCompleted: OSSA_IO_ERROR_INTERNAL_SMP_RESOURCE\n")); + saFrameReadBlock(agRoot, agFrameHandle, 0, smpHeader, 4); + dmResponseSMPFrameHeader = (dmSMPFrameHeader_t *)smpHeader; + + status = saSMPStart( + agRoot, + agIORequest, + 0, + agDevHandle, + AGSA_SMP_INIT_REQ, + agSASRequestBody, + &dmsaSMPCompleted + ); + + if (status == AGSA_RC_SUCCESS) + { + /* increment the number of pending SMP */ + onePortContext->discovery.pendingSMP++; + if (SMPRequestFunction == SMP_REPORT_GENERAL || SMPRequestFunction == SMP_DISCOVER || + SMPRequestFunction == SMP_REPORT_PHY_SATA || + SMPRequestFunction == SMP_CONFIGURE_ROUTING_INFORMATION + ) + { + /* start discovery-related SMP timer */ + dmDiscoverySMPTimer(dmRoot, onePortContext, (bit32)(dmResponseSMPFrameHeader->smpFunction), dmSMPRequestBody); + } + return; + } + else if (status == AGSA_RC_BUSY) + { + if (dmResponseSMPFrameHeader->smpFunction == SMP_REPORT_GENERAL || + dmResponseSMPFrameHeader->smpFunction == SMP_DISCOVER || + dmResponseSMPFrameHeader->smpFunction == SMP_REPORT_PHY_SATA || + dmResponseSMPFrameHeader->smpFunction == SMP_CONFIGURE_ROUTING_INFORMATION + ) + { + dmSMPBusyTimer(dmRoot, onePortContext, oneDeviceData, dmSMPRequestBody); + } + else if (dmResponseSMPFrameHeader->smpFunction == SMP_PHY_CONTROL) + { + /* For taskmanagement SMP, let's fail task management failure */ + dmPhyControlFailureRespRcvd( + dmRoot, + agRoot, + oneDeviceData, + dmResponseSMPFrameHeader, + agFrameHandle + ); + } + else + { + } + } + else /* AGSA_RC_FAILURE */ + { + if (dmResponseSMPFrameHeader->smpFunction == SMP_REPORT_GENERAL || + dmResponseSMPFrameHeader->smpFunction == SMP_DISCOVER || + dmResponseSMPFrameHeader->smpFunction == SMP_REPORT_PHY_SATA || + dmResponseSMPFrameHeader->smpFunction == SMP_CONFIGURE_ROUTING_INFORMATION + ) + { + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + else if (dmResponseSMPFrameHeader->smpFunction == SMP_PHY_CONTROL) + { + /* task management failure */ + dmPhyControlFailureRespRcvd( + dmRoot, + agRoot, + oneDeviceData, + dmResponseSMPFrameHeader, + agFrameHandle + ); + } + else + { + } + } + } /* OSSA_IO_ERROR_INTERNAL_SMP_RESOURCE*/ + else + { + if (agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED || + agIOStatus == OSSA_IO_DS_NON_OPERATIONAL ) + { + DM_DBG1(("dmSMPCompleted: setting back to operational\n")); + saSetDeviceState(agRoot, agNULL, 0, agDevHandle, SA_DS_OPERATIONAL); + } + if (agIOStatus == OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED && dmAllShared->RateAdjust) + { + DM_DBG1(("dmSMPCompleted: OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n")); + DM_DBG1(("dmSMPCompleted: SMPRequestFunction 0x%x\n", SMPRequestFunction)); + ConnRate = DEVINFO_GET_LINKRATE(&oneDeviceData->agDeviceInfo); + if (ConnRate == SAS_CONNECTION_RATE_1_5G) + { + /* no retry; failure ??? */ + if (SMPRequestFunction == SMP_REPORT_GENERAL || + SMPRequestFunction == SMP_DISCOVER || + SMPRequestFunction == SMP_REPORT_PHY_SATA || + SMPRequestFunction == SMP_CONFIGURE_ROUTING_INFORMATION + ) + { + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + else if (SMPRequestFunction == SMP_PHY_CONTROL) + { + /* task management failure */ + dmPhyControlFailureRespRcvd( + dmRoot, + agRoot, + oneDeviceData, + agNULL, + agNULL + ); + } + else + { + } + } + else + { + ConnRate = ConnRate - 1; + } + agContext = &(dmSMPRequestBody->agContext); + agContext->osData = agIORequest; + saSetDeviceInfo(agRoot, agContext, 0, agDevHandle, 32, ConnRate << 28, dmSetDeviceInfoCB); + } + else + { + if (dmSMPRequestBody->retries < SMP_RETRIES) /* 5 */ + { + /* retry the SMP again */ + DM_DBG1(("dmSMPCompleted: failed, but retries %d agIOStatus 0x%x %d agIOInfoLen %d !!!\n", + dmSMPRequestBody->retries, agIOStatus, agIOStatus, agIOInfoLen)); + saFrameReadBlock(agRoot, agFrameHandle, 0, smpHeader, 4); + dmResponseSMPFrameHeader = (dmSMPFrameHeader_t *)smpHeader; + status = saSMPStart( + agRoot, + agIORequest, + 0, + agDevHandle, + AGSA_SMP_INIT_REQ, + agSASRequestBody, + &dmsaSMPCompleted + ); + if (status == AGSA_RC_SUCCESS) + { + /* increment the number of pending SMP */ + onePortContext->discovery.pendingSMP++; + dmSMPRequestBody->retries++; + if (SMPRequestFunction == SMP_REPORT_GENERAL || SMPRequestFunction == SMP_DISCOVER || + SMPRequestFunction == SMP_REPORT_PHY_SATA || + SMPRequestFunction == SMP_CONFIGURE_ROUTING_INFORMATION + ) + { + /* start discovery-related SMP timer */ + dmDiscoverySMPTimer(dmRoot, onePortContext, (bit32)(dmResponseSMPFrameHeader->smpFunction), dmSMPRequestBody); + } + return; + } + else if (status == AGSA_RC_BUSY) + { + onePortContext->discovery.pendingSMP++; + dmSMPRequestBody->retries++; + if (dmResponseSMPFrameHeader->smpFunction == SMP_REPORT_GENERAL || + dmResponseSMPFrameHeader->smpFunction == SMP_DISCOVER || + dmResponseSMPFrameHeader->smpFunction == SMP_REPORT_PHY_SATA || + dmResponseSMPFrameHeader->smpFunction == SMP_CONFIGURE_ROUTING_INFORMATION + ) + { + dmSMPBusyTimer(dmRoot, onePortContext, oneDeviceData, dmSMPRequestBody); + return; + } + else if (dmResponseSMPFrameHeader->smpFunction == SMP_PHY_CONTROL) + { + /* For taskmanagement SMP, let's fail task management failure */ + dmPhyControlFailureRespRcvd( + dmRoot, + agRoot, + oneDeviceData, + dmResponseSMPFrameHeader, + agFrameHandle + ); + } + else + { + } + } + else /* AGSA_RC_FAILURE */ + { + if (dmResponseSMPFrameHeader->smpFunction == SMP_REPORT_GENERAL || + dmResponseSMPFrameHeader->smpFunction == SMP_DISCOVER || + dmResponseSMPFrameHeader->smpFunction == SMP_REPORT_PHY_SATA || + dmResponseSMPFrameHeader->smpFunction == SMP_CONFIGURE_ROUTING_INFORMATION + ) + { + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + else if (dmResponseSMPFrameHeader->smpFunction == SMP_PHY_CONTROL) + { + /* task management failure */ + dmPhyControlFailureRespRcvd( + dmRoot, + agRoot, + oneDeviceData, + dmResponseSMPFrameHeader, + agFrameHandle + ); + } + else + { + } + } + } + else + { + dmSMPFrameHeader = (dmSMPFrameHeader_t *)agSMPFrame->outFrameBuf; + dmSMPPayload = (bit8 *)agSMPFrame->outFrameBuf + 4; + DM_DBG1(("dmSMPCompleted: failed. no more retry. agIOStatus 0x%x %d !!!\n", agIOStatus, agIOStatus)); + if (agIOStatus == OSSA_IO_DS_NON_OPERATIONAL) + { + DM_DBG1(("dmSMPCompleted: failed, agIOStatus is OSSA_IO_DS_NON_OPERATIONAL!!!\n")); + } + if (agIOStatus == OSSA_IO_DS_IN_RECOVERY) + { + DM_DBG1(("dmSMPCompleted: failed, agIOStatus is OSSA_IO_DS_IN_RECOVERY!!!\n")); + } + if (dmSMPFrameHeader->smpFunction == SMP_REPORT_GENERAL || + dmSMPFrameHeader->smpFunction == SMP_DISCOVER || + dmSMPFrameHeader->smpFunction == SMP_REPORT_PHY_SATA || + dmSMPFrameHeader->smpFunction == SMP_CONFIGURE_ROUTING_INFORMATION + ) + { + /* discovery failure */ + DM_DBG1(("dmSMPCompleted: SMP function 0x%x\n", dmSMPFrameHeader->smpFunction)); + DM_DBG1(("dmSMPCompleted: discover done with error\n")); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + else if (dmSMPFrameHeader->smpFunction == SMP_PHY_CONTROL) + { + DM_DBG3(("dmSMPCompleted: SMP_PHY_CONTROL\n")); + smpPhyControlReq = (smpReqPhyControl_t *)dmSMPPayload; + if (smpPhyControlReq->phyOperation == SMP_PHY_CONTROL_CLEAR_AFFILIATION) + { + DM_DBG3(("dmSMPCompleted: discover done with error\n")); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + else + { + DM_DBG3(("dmSMPCompleted: unknown phy operation 0x%x\n", smpPhyControlReq->phyOperation)); + } + } /* SMP_PHY_CONTROL */ + else + { + DM_DBG3(("dmSMPCompleted: SMP function 0x%x\n", dmSMPFrameHeader->smpFunction)); + } + } /* else */ + } /* for RateAdjust */ + } /* outer else */ + } /* SAS 1.1 */ + /************************************ SAS 2 ***********************************************/ + else + { + DM_DBG2(("dmSMPCompleted: SAS 2\n")); + if (agIOStatus == OSSA_IO_SUCCESS) + { + //tdhexdump("dmSMPCompleted", (bit8*)agFrameHandle, agIOInfoLen); + /* parsing SMP payload */ +#ifdef DIRECT_SMP + saFrameReadBlock(agRoot, agFrameHandle, 0, smpHeader, 4); +#else + dmSMPResponseBody = (dmSMPRequestBody_t *)dmSMPRequestBody->IndirectSMPResponse; + saFrameReadBlock(agRoot, dmSMPResponseBody->IndirectSMP, 0, smpHeader, 4); +#endif + dmResponseSMPFrameHeader = (dmSMPFrameHeader_t *)smpHeader; + + /* SMP function dependent payload */ + switch (dmResponseSMPFrameHeader->smpFunction) + { + case SMP_REPORT_GENERAL: + DM_DBG2(("dmSMPCompleted: report general\n")); + if ((agIOInfoLen != sizeof(smpRespReportGeneral2_t) + 4) && + dmResponseSMPFrameHeader->smpFunctionResult == SMP_FUNCTION_ACCEPTED + ) + { + DM_DBG1(("dmSMPCompleted: report general mismatch len agIOInfoLen 0x%x 0x%x\n", agIOInfoLen, (int)sizeof(smpRespReportGeneral2_t) + 4)); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + + /* SMP request */ + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPRequestBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); + +#ifndef DIRECT_SMP + /* SMP response */ + dmSMPResponseBody = (dmSMPRequestBody_t *)dmSMPRequestBody->IndirectSMPResponse; + if (dmSMPResponseBody == agNULL) + { + DM_DBG1(("dmSMPCompleted: Wrong, dmSMPResponseBody is NULL!!!\n")); + return; + } + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPResponseBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); +#endif + + return; + } + + dmReportGeneral2RespRcvd( + dmRoot, + agRoot, + agIORequest, + oneDeviceData, + dmResponseSMPFrameHeader, + agFrameHandle + ); + break; + case SMP_DISCOVER: + DM_DBG2(("dmSMPCompleted: discover\n")); + if ((agIOInfoLen != sizeof(smpRespDiscover2_t) + 4) && + dmResponseSMPFrameHeader->smpFunctionResult == SMP_FUNCTION_ACCEPTED + ) + { + DM_DBG1(("dmSMPCompleted: discover mismatch len agIOInfoLen 0x%x 0x%x\n", agIOInfoLen, (int)sizeof(smpRespDiscover2_t) + 4)); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + + /* SMP request */ + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPRequestBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); + +#ifndef DIRECT_SMP + /* SMP response */ + dmSMPResponseBody = (dmSMPRequestBody_t *)dmSMPRequestBody->IndirectSMPResponse; + if (dmSMPResponseBody == agNULL) + { + DM_DBG1(("dmSMPCompleted: Wrong, dmSMPResponseBody is NULL!!!\n")); + return; + } + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPResponseBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); +#endif + + return; + } + dmDiscover2RespRcvd( + dmRoot, + agRoot, + agIORequest, + oneDeviceData, + dmResponseSMPFrameHeader, + agFrameHandle + ); + break; + case SMP_REPORT_PHY_SATA: + DM_DBG2(("dmSMPCompleted: report phy sata\n")); + if ((agIOInfoLen != sizeof(smpRespReportPhySata2_t) + 4) && + dmResponseSMPFrameHeader->smpFunctionResult == SMP_FUNCTION_ACCEPTED + ) + { + DM_DBG1(("dmSMPCompleted: report phy sata mismatch len agIOInfoLen 0x%x 0x%x\n", agIOInfoLen, (int)sizeof(smpRespReportPhySata2_t) + 4)); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + + /* SMP request */ + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPRequestBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); + +#ifndef DIRECT_SMP + /* SMP response */ + dmSMPResponseBody = (dmSMPRequestBody_t *)dmSMPRequestBody->IndirectSMPResponse; + if (dmSMPResponseBody == agNULL) + { + DM_DBG1(("dmSMPCompleted: Wrong, dmSMPResponseBody is NULL!!!\n")); + return; + } + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPResponseBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); +#endif + + return; + } + dmReportPhySata2Rcvd( + dmRoot, + agRoot, + agIORequest, + oneDeviceData, + dmResponseSMPFrameHeader, + agFrameHandle + ); + break; + case SMP_CONFIGURE_ROUTING_INFORMATION: + DM_DBG2(("dmSMPCompleted: configure routing information\n")); + if (agIOInfoLen != 4 && + dmResponseSMPFrameHeader->smpFunctionResult == SMP_FUNCTION_ACCEPTED + ) + { + DM_DBG1(("dmSMPCompleted: configure routing information mismatch len agIOInfoLen 0x%x 0x%x\n", agIOInfoLen, 4)); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + + /* SMP request */ + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPRequestBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); + +#ifndef DIRECT_SMP + /* SMP response */ + dmSMPResponseBody = (dmSMPRequestBody_t *)dmSMPRequestBody->IndirectSMPResponse; + if (dmSMPResponseBody == agNULL) + { + DM_DBG1(("dmSMPCompleted: Wrong, dmSMPResponseBody is NULL!!!\n")); + return; + } + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPResponseBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); +#endif + + return; + } + dmConfigRoutingInfo2RespRcvd( + dmRoot, + agRoot, + agIORequest, + oneDeviceData, + dmResponseSMPFrameHeader, + agFrameHandle + ); + + break; + case SMP_PHY_CONTROL: + DM_DBG2(("dmSMPCompleted: phy control\n")); + if (agIOInfoLen != 4 && + dmResponseSMPFrameHeader->smpFunctionResult == SMP_FUNCTION_ACCEPTED + ) /*zero length is expected */ + { + DM_DBG1(("dmSMPCompleted: phy control mismatch len agIOInfoLen 0x%x 0x%x\n", agIOInfoLen, 4)); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + + /* SMP request */ + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPRequestBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); + +#ifndef DIRECT_SMP + /* SMP response */ + dmSMPResponseBody = (dmSMPRequestBody_t *)dmSMPRequestBody->IndirectSMPResponse; + if (dmSMPResponseBody == agNULL) + { + DM_DBG1(("dmSMPCompleted: Wrong, dmSMPResponseBody is NULL!!!\n")); + return; + } + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPResponseBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); +#endif + + return; + } + dmPhyControl2RespRcvd( + dmRoot, + agRoot, + agIORequest, + oneDeviceData, + dmResponseSMPFrameHeader, + agFrameHandle + ); + + + break; +#ifdef NOT_YET + case SMP_DISCOVER_LIST: + DM_DBG1(("dmSMPCompleted: SMP_DISCOVER_LIST\n")); + DM_DBG1(("dmSMPCompleted: agIOInfoLen 0x%x \n", agIOInfoLen)); + tdhexdump("dmSMPCompleted", (bit8*)agFrameHandle, agIOInfoLen); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + + /* SMP request */ + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPRequestBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); + +#ifndef DIRECT_SMP + /* SMP response */ + dmSMPResponseBody = (dmSMPRequestBody_t *)dmSMPRequestBody->IndirectSMPResponse; + if (dmSMPResponseBody == agNULL) + { + DM_DBG1(("dmSMPCompleted: Wrong, dmSMPResponseBody is NULL!!!\n")); + return; + } + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPResponseBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); +#endif + + return; + break; +#endif + case SMP_REPORT_ROUTING_INFORMATION: /* fall through */ + case SMP_REPORT_PHY_ERROR_LOG: /* fall through */ + case SMP_PHY_TEST_FUNCTION: /* fall through */ + case SMP_REPORT_MANUFACTURE_INFORMATION: /* fall through */ + case SMP_READ_GPIO_REGISTER: /* fall through */ + case SMP_WRITE_GPIO_REGISTER: /* fall through */ + default: + DM_DBG1(("dmSMPCompleted: wrong SMP function 0x%x\n", dmResponseSMPFrameHeader->smpFunction)); + DM_DBG1(("dmSMPCompleted: smpFrameType 0x%x\n", dmResponseSMPFrameHeader->smpFrameType)); + DM_DBG1(("dmSMPCompleted: smpFunctionResult 0x%x\n", dmResponseSMPFrameHeader->smpFunctionResult)); + DM_DBG1(("dmSMPCompleted: smpReserved 0x%x\n", dmResponseSMPFrameHeader->smpReserved)); + dmhexdump("dmSMPCompleted: SMP payload", (bit8 *)agFrameHandle, agIOInfoLen); + break; + } + } /* agIOStatus == OSSA_IO_SUCCESS */ + else if (agIOStatus == OSSA_IO_ABORTED || agIOStatus == OSSA_IO_INVALID_LENGTH) + { + /* no retry this case */ + DM_DBG1(("dmSMPCompleted: OSSA_IO_ABORTED or OSSA_IO_INVALID_LENGTH, status 0x%x\n", agIOStatus)); + } + else if (agIOStatus == OSSA_IO_ERROR_INTERNAL_SMP_RESOURCE) + { + DM_DBG1(("dmSMPCompleted: OSSA_IO_ERROR_INTERNAL_SMP_RESOURCE\n")); + saFrameReadBlock(agRoot, agFrameHandle, 0, smpHeader, 4); + dmResponseSMPFrameHeader = (dmSMPFrameHeader_t *)smpHeader; + + status = saSMPStart( + agRoot, + agIORequest, + 0, + agDevHandle, + AGSA_SMP_INIT_REQ, + agSASRequestBody, + &dmsaSMPCompleted + ); + + + if (status == AGSA_RC_SUCCESS) + { + /* increment the number of pending SMP */ + onePortContext->discovery.pendingSMP++; + if (SMPRequestFunction == SMP_REPORT_GENERAL || SMPRequestFunction == SMP_DISCOVER || + SMPRequestFunction == SMP_REPORT_PHY_SATA || + SMPRequestFunction == SMP_CONFIGURE_ROUTING_INFORMATION + ) + { + /* start discovery-related SMP timer */ + dmDiscoverySMPTimer(dmRoot, onePortContext, (bit32)(dmResponseSMPFrameHeader->smpFunction), dmSMPRequestBody); + } + return; + } + else if (status == AGSA_RC_BUSY) + { + if (dmResponseSMPFrameHeader->smpFunction == SMP_REPORT_GENERAL || + dmResponseSMPFrameHeader->smpFunction == SMP_DISCOVER || + dmResponseSMPFrameHeader->smpFunction == SMP_REPORT_PHY_SATA || + dmResponseSMPFrameHeader->smpFunction == SMP_CONFIGURE_ROUTING_INFORMATION + ) + { + dmSMPBusyTimer(dmRoot, onePortContext, oneDeviceData, dmSMPRequestBody); + } + else if (dmResponseSMPFrameHeader->smpFunction == SMP_PHY_CONTROL) + { + /* For taskmanagement SMP, let's fail task management failure */ + dmPhyControlFailureRespRcvd( + dmRoot, + agRoot, + oneDeviceData, + dmResponseSMPFrameHeader, + agFrameHandle + ); + } + else + { + } + } + else /* AGSA_RC_FAILURE */ + { + if (dmResponseSMPFrameHeader->smpFunction == SMP_REPORT_GENERAL || + dmResponseSMPFrameHeader->smpFunction == SMP_DISCOVER || + dmResponseSMPFrameHeader->smpFunction == SMP_REPORT_PHY_SATA || + dmResponseSMPFrameHeader->smpFunction == SMP_CONFIGURE_ROUTING_INFORMATION + ) + { + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + else if (dmResponseSMPFrameHeader->smpFunction == SMP_PHY_CONTROL) + { + /* task management failure */ + dmPhyControlFailureRespRcvd( + dmRoot, + agRoot, + oneDeviceData, + dmResponseSMPFrameHeader, + agFrameHandle + ); + } + else + { + } + } + } + else if (agIOStatus == OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION) + { + DM_DBG1(("dmSMPCompleted: OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); + /* + skip to the next expander + */ + dmHandleZoneViolation( + dmRoot, + agRoot, + agIORequest, + oneDeviceData, + agNULL, + agFrameHandle + ); + } + else + { + if (agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED || + agIOStatus == OSSA_IO_DS_NON_OPERATIONAL ) + { + DM_DBG1(("dmSMPCompleted: setting back to operational\n")); + saSetDeviceState(agRoot, agNULL, 0, agDevHandle, SA_DS_OPERATIONAL); + } + if (agIOStatus == OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED && dmAllShared->RateAdjust) + { + DM_DBG1(("dmSMPCompleted: OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n")); + DM_DBG1(("dmSMPCompleted: SMPRequestFunction 0x%x\n", SMPRequestFunction)); + ConnRate = DEVINFO_GET_LINKRATE(&oneDeviceData->agDeviceInfo); + if (ConnRate == SAS_CONNECTION_RATE_1_5G) + { + /* no retry; failure ??? */ + if (SMPRequestFunction == SMP_REPORT_GENERAL || + SMPRequestFunction == SMP_DISCOVER || + SMPRequestFunction == SMP_REPORT_PHY_SATA || + SMPRequestFunction == SMP_CONFIGURE_ROUTING_INFORMATION + ) + { + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + else if (SMPRequestFunction == SMP_PHY_CONTROL) + { + /* task management failure */ + dmPhyControlFailureRespRcvd( + dmRoot, + agRoot, + oneDeviceData, + agNULL, + agNULL + ); + } + else + { + } + } + else + { + ConnRate = ConnRate - 1; + } + agContext = &(dmSMPRequestBody->agContext); + agContext->osData = agIORequest; + saSetDeviceInfo(agRoot, agContext, 0, agDevHandle, 32, ConnRate << 28, dmSetDeviceInfoCB); + } + else + { + if (dmSMPRequestBody->retries < SMP_RETRIES) /* 5 */ + { + /* retry the SMP again */ + DM_DBG1(("dmSMPCompleted: failed! but retries %d agIOStatus 0x%x %d agIOInfoLen %d\n", + dmSMPRequestBody->retries, agIOStatus, agIOStatus, agIOInfoLen)); + saFrameReadBlock(agRoot, agFrameHandle, 0, smpHeader, 4); + dmResponseSMPFrameHeader = (dmSMPFrameHeader_t *)smpHeader; + status = saSMPStart( + agRoot, + agIORequest, + 0, + agDevHandle, + AGSA_SMP_INIT_REQ, + agSASRequestBody, + &dmsaSMPCompleted + ); + + if (status == AGSA_RC_SUCCESS) + { + /* increment the number of pending SMP */ + onePortContext->discovery.pendingSMP++; + dmSMPRequestBody->retries++; + if (SMPRequestFunction == SMP_REPORT_GENERAL || SMPRequestFunction == SMP_DISCOVER || + SMPRequestFunction == SMP_REPORT_PHY_SATA || + SMPRequestFunction == SMP_CONFIGURE_ROUTING_INFORMATION + ) + { + /* start discovery-related SMP timer */ + dmDiscoverySMPTimer(dmRoot, onePortContext, (bit32)(dmResponseSMPFrameHeader->smpFunction), dmSMPRequestBody); + } + return; + } + else if (status == AGSA_RC_BUSY) + { + onePortContext->discovery.pendingSMP++; + dmSMPRequestBody->retries++; + if (dmResponseSMPFrameHeader->smpFunction == SMP_REPORT_GENERAL || + dmResponseSMPFrameHeader->smpFunction == SMP_DISCOVER || + dmResponseSMPFrameHeader->smpFunction == SMP_REPORT_PHY_SATA || + dmResponseSMPFrameHeader->smpFunction == SMP_CONFIGURE_ROUTING_INFORMATION + ) + { + dmSMPBusyTimer(dmRoot, onePortContext, oneDeviceData, dmSMPRequestBody); + return; + } + else if (dmResponseSMPFrameHeader->smpFunction == SMP_PHY_CONTROL) + { + /* For taskmanagement SMP, let's fail task management failure */ + dmPhyControlFailureRespRcvd( + dmRoot, + agRoot, + oneDeviceData, + dmResponseSMPFrameHeader, + agFrameHandle + ); + } + else + { + } + } + else /* AGSA_RC_FAILURE */ + { + if (dmResponseSMPFrameHeader->smpFunction == SMP_REPORT_GENERAL || + dmResponseSMPFrameHeader->smpFunction == SMP_DISCOVER || + dmResponseSMPFrameHeader->smpFunction == SMP_REPORT_PHY_SATA || + dmResponseSMPFrameHeader->smpFunction == SMP_CONFIGURE_ROUTING_INFORMATION + ) + { + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + else if (dmResponseSMPFrameHeader->smpFunction == SMP_PHY_CONTROL) + { + /* task management failure */ + dmPhyControlFailureRespRcvd( + dmRoot, + agRoot, + oneDeviceData, + dmResponseSMPFrameHeader, + agFrameHandle + ); + } + else + { + } + } + } + else + { + dmSMPFrameHeader = (dmSMPFrameHeader_t *)agSMPFrame->outFrameBuf; + dmSMPPayload = (bit8 *)agSMPFrame->outFrameBuf + 4; + DM_DBG1(("dmSMPCompleted: failed! no more retry! agIOStatus 0x%x %d\n", agIOStatus, agIOStatus)); + if (agIOStatus == OSSA_IO_DS_NON_OPERATIONAL) + { + DM_DBG1(("dmSMPCompleted: failed! agIOStatus is OSSA_IO_DS_NON_OPERATIONAL\n")); + } + if (agIOStatus == OSSA_IO_DS_IN_RECOVERY) + { + DM_DBG1(("dmSMPCompleted: failed! agIOStatus is OSSA_IO_DS_IN_RECOVERY\n")); + } + if (dmSMPFrameHeader->smpFunction == SMP_REPORT_GENERAL || + dmSMPFrameHeader->smpFunction == SMP_DISCOVER || + dmSMPFrameHeader->smpFunction == SMP_REPORT_PHY_SATA || + dmSMPFrameHeader->smpFunction == SMP_CONFIGURE_ROUTING_INFORMATION + ) + { + /* discovery failure */ + DM_DBG1(("dmSMPCompleted: SMP function 0x%x\n", dmSMPFrameHeader->smpFunction)); + DM_DBG1(("dmSMPCompleted: discover done with error\n")); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + else if (dmSMPFrameHeader->smpFunction == SMP_PHY_CONTROL) + { + DM_DBG1(("dmSMPCompleted: SMP_PHY_CONTROL\n")); + smpPhyControl2Req = (smpReqPhyControl2_t *)dmSMPPayload; + if (smpPhyControl2Req->phyOperation == SMP_PHY_CONTROL_CLEAR_AFFILIATION) + { + DM_DBG1(("dmSMPCompleted: discover done with error\n")); + dmDiscoverDone(dmRoot, onePortContext, DM_RC_FAILURE); + } + else + { + DM_DBG1(("dmSMPCompleted: unknown phy operation 0x%x\n", smpPhyControl2Req->phyOperation)); + } + } /* SMP_PHY_CONTROL */ + else + { + DM_DBG1(("dmSMPCompleted: SMP function 0x%x\n", dmSMPFrameHeader->smpFunction)); + } + } /* else */ + } /* for RateAdjust */ + } /* outer else */ + } /* SAS 2 else */ + + /* SMP request */ + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPRequestBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); + +#ifndef DIRECT_SMP + /* SMP response */ + dmSMPResponseBody = (dmSMPRequestBody_t *)dmSMPRequestBody->IndirectSMPResponse; + if (dmSMPResponseBody == agNULL) + { + DM_DBG1(("dmSMPCompleted: Wrong, dmSMPResponseBody is NULL!!!\n")); + return; + } + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPResponseBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); +#endif + + return; +} + +osGLOBAL void +dmSMPAbortCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 flag, + bit32 status) +{ + dmRoot_t *dmRoot = agNULL; + dmIntRoot_t *dmIntRoot = agNULL; + dmIntContext_t *dmAllShared = agNULL; + dmSMPRequestBody_t *dmSMPRequestBody = (dmSMPRequestBody_t *) agIORequest->osData; + + DM_DBG5(("dmSMPAbortCB: start\n")); + + if (dmSMPRequestBody == agNULL) + { + DM_DBG1(("dmSMPAbortCB: pSMPRequestBody is NULL!!! \n")); + return; + } + + dmRoot = dmSMPRequestBody->dmRoot; + dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + + + /* put back into free smplist */ + tddmSingleThreadedEnter(dmRoot, DM_SMP_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(dmSMPRequestBody->Link), &(dmAllShared->freeSMPList)); + tddmSingleThreadedLeave(dmRoot, DM_SMP_LOCK); + + /* start here */ + if (flag == 2) + { + /* abort all per port */ + DM_DBG1(("dmSMPAbortCB: abort per port; not used!!!\n")); + } + else if (flag == 1) + { + /* abort all */ + DM_DBG1(("dmSMPAbortCB: abort all; not used!!!\n")); + } + else if (flag == 0) + { + /* abort one */ + DM_DBG1(("ossaSMPAbortCB: abort one\n")); + if (status != OSSA_IO_SUCCESS) + { + DM_DBG1(("dmSMPAbortCB: abort one, status 0x%x\n", status)); + } + } + else + { + DM_DBG1(("dmSMPAbortCB: not allowed case, flag 0x%x!!!\n", flag)); + } + + return; +} + + +#endif /* FDS_DM */ + + diff --git a/sys/dev/pms/RefTisa/discovery/dm/dmtimer.c b/sys/dev/pms/RefTisa/discovery/dm/dmtimer.c new file mode 100644 index 000000000000..dd79a5e3452a --- /dev/null +++ b/sys/dev/pms/RefTisa/discovery/dm/dmtimer.c @@ -0,0 +1,163 @@ +/******************************************************************************* +** +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +** +********************************************************************************/ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#include +#include + +#include +#include +#include + +#ifdef FDS_DM +#include +#include +#include + +#include +#include +#include + +osGLOBAL void +dmTimerTick(dmRoot_t *dmRoot ) +{ + DM_DBG6(("dmTimerTick: start\n")); + + dmProcessTimers(dmRoot); + + return; +} + +osGLOBAL void +dmInitTimerRequest( + dmRoot_t *dmRoot, + dmTimerRequest_t *timerRequest + ) +{ + timerRequest->timeout = 0; + timerRequest->timerCBFunc = agNULL; + timerRequest->timerData1 = agNULL; + timerRequest->timerData2 = agNULL; + timerRequest->timerData3 = agNULL; + DMLIST_INIT_ELEMENT((&timerRequest->timerLink)); +} + +osGLOBAL void +dmSetTimerRequest( + dmRoot_t *dmRoot, + dmTimerRequest_t *timerRequest, + bit32 timeout, + dmTimerCBFunc_t CBFunc, + void *timerData1, + void *timerData2, + void *timerData3 + ) +{ + timerRequest->timeout = timeout; + timerRequest->timerCBFunc = CBFunc; + timerRequest->timerData1 = timerData1; + timerRequest->timerData2 = timerData2; + timerRequest->timerData3 = timerData3; +} + +osGLOBAL void +dmAddTimer( + dmRoot_t *dmRoot, + dmList_t *timerListHdr, + dmTimerRequest_t *timerRequest + ) +{ + tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK); + DMLIST_ENQUEUE_AT_TAIL(&(timerRequest->timerLink), timerListHdr); + timerRequest->timerRunning = agTRUE; + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); +} + +osGLOBAL void +dmKillTimer( + dmRoot_t *dmRoot, + dmTimerRequest_t *timerRequest + ) +{ + tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK); + timerRequest->timerRunning = agFALSE; + DMLIST_DEQUEUE_THIS(&(timerRequest->timerLink)); + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); +} + + +osGLOBAL void +dmProcessTimers( + dmRoot_t *dmRoot + ) +{ + dmIntRoot_t *dmIntRoot = (dmIntRoot_t *)dmRoot->dmData; + dmIntContext_t *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared; + dmTimerRequest_t *timerRequest_to_process = agNULL; + dmList_t *timerlist_to_process, *nexttimerlist = agNULL; + + + timerlist_to_process = &dmAllShared->timerlist; + + timerlist_to_process = timerlist_to_process->flink; + + while ((timerlist_to_process != agNULL) && (timerlist_to_process != &dmAllShared->timerlist)) + { + nexttimerlist = timerlist_to_process->flink; + + tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK); + timerRequest_to_process = DMLIST_OBJECT_BASE(dmTimerRequest_t, timerLink, timerlist_to_process); + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + + if (timerRequest_to_process == agNULL) + { + DM_DBG1(("dmProcessTimers: timerRequest_to_process is NULL! Error!!!\n")); + return; + } + + timerRequest_to_process->timeout--; + + if (timerRequest_to_process->timeout == 0) + { + tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK); + timerRequest_to_process->timerRunning = agFALSE; + DMLIST_DEQUEUE_THIS(timerlist_to_process); + tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK); + /* calling call back function */ + (timerRequest_to_process->timerCBFunc)(dmRoot, + timerRequest_to_process->timerData1, + timerRequest_to_process->timerData2, + timerRequest_to_process->timerData3 + ); + } + timerlist_to_process = nexttimerlist; + } + + return; +} +#endif /* FDS_ DM */ + diff --git a/sys/dev/pms/RefTisa/discovery/dm/dmtypes.h b/sys/dev/pms/RefTisa/discovery/dm/dmtypes.h new file mode 100644 index 000000000000..3bcd8f9faa54 --- /dev/null +++ b/sys/dev/pms/RefTisa/discovery/dm/dmtypes.h @@ -0,0 +1,428 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +#ifndef __DMTYPES_H__ +#define __DMTYPES_H__ + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include +#ifdef TBD +#include +#endif + + +/* for SMP only */ +typedef void (*dmSMPCompleted_t) ( + agsaRoot_t *, + agsaIORequest_t *, + bit32 , + bit32 , + agsaFrameHandle_t + ); + + +/* timer functions ; both I and T */ +typedef void (*dmTimerCBFunc_t)(dmRoot_t *dmRoot, void *timerData1, void *timerData2, void *timerData3); + + +/** \brief data structure for timer request + * Timer requests are enqueued and dequeued using dmList_t + * and have a callback function + */ +typedef struct dmTimerRequest_s { + /* the number of ticks */ + bit32 timeout; + void *timerData1; + void *timerData2; + void *timerData3; + dmTimerCBFunc_t timerCBFunc; + dmList_t timerLink; + bit32 timerRunning; +} dmTimerRequest_t; + +typedef struct dmRootOsData_s { + dmRoot_t *dmRoot; /**< Pointer back to dmRoot */ + void *dmAllShared; /**< Pointer to dmContext_t */ + void *dmIni; /**< Pointer to SAS/SATA initiator */ +} dmRootOsData_t; + +typedef struct DMSASAddressID_s +{ + bit32 sasAddressLo; /**< HOST SAS address lower part */ + bit32 sasAddressHi; /**< HOST SAS address higher part */ + bit8 phyIdentifier; /**< PHY IDENTIFIER of the PHY */ +} DMSASAddressID_t; + +struct dmExpander_s; + +typedef struct dmDiscovery_s +{ + dmList_t discoveringExpanderList; + dmList_t UpdiscoveringExpanderList; + // tdList_t freeExpanderList; + bit32 status; + DMSASAddressID_t sasAddressIDDiscoverError; + agsaSATAIdentifyData_t *pSataIdentifyData; + struct dmExpander_s *RootExp; /* Root expander of discovery */ + bit32 NumOfUpExp; + bit32 type; /* discovery type: TDSA_DISCOVERY_OPTION_FULL_START + or TDSA_DISCOVERY_OPTION_INCREMENTAL_START*/ + bit32 retries; + bit32 configureRouteRetries; + bit32 deviceRetistrationRetries; + dmTimerRequest_t discoveryTimer; + dmTimerRequest_t configureRouteTimer; + dmTimerRequest_t deviceRegistrationTimer; + dmTimerRequest_t BCTimer; /* Broadcast Change timer for ResetTriggerred */ + smpRespDiscover_t SMPDiscoverResp; + smpRespDiscover2_t SMPDiscover2Resp; + bit32 pendingSMP; /* the number of pending SMP for this discovery */ + bit32 SeenBC; /* received Broadcast change */ + bit32 forcedOK; /* report DiscOK when chance is missed */ + dmTimerRequest_t SMPBusyTimer; /* SMP retry timer for saSMPStart busy */ + bit32 SMPRetries; /* number of SMP retries when LL returns busy for saSMPStart*/ + bit32 ResetTriggerred; /* Hard/Link reset triggerred by discovery */ + dmTimerRequest_t DiscoverySMPTimer; /* discovery-related SMP application Timer */ + /* For SAS 2 */ + bit32 DeferredError; /* Deferred Error for SAS 2 */ + bit32 ConfiguresOthers; /* exp configures others; no routing configuration */ +} dmDiscovery_t; + +typedef struct dmSASSubID_s +{ + bit32 sasAddressHi; + bit32 sasAddressLo; + bit8 initiator_ssp_stp_smp; + bit8 target_ssp_stp_smp; + +} dmSASSubID_t; + +struct dmDeviceData_s; + +typedef struct dmIntPortContext_s +{ + /**< current number of devices in this PortContext */ + bit32 Count; + bit32 DiscoveryState; + bit32 DiscoveryAbortInProgress; + /* passed by tiINIDiscoverTargets() + eg) discovery or rediscovery .... + */ + bit32 discoveryOptions; + /* Discovery ready is given? */ + bit32 DiscoveryRdyGiven; + /* Port has received link up */ + bit32 SeenLinkUp; + /* statistics */ + bit32 numAvailableTargets; + /* flag: indicates that discovery is trigggered by tiINIDiscoverTargets */ + bit32 osInitiatedDiscovery; + + bit32 id; /* for debugging only */ + dmList_t FreeLink; /**< free portcontext list */ + dmList_t MainLink; /**< in-use portcontext list */ + /**< SAS address of the remote device */ + bit32 sasRemoteAddressHi; /**< SAS address high part */ + bit32 sasRemoteAddressLo; /**< SAS address low part */ + /**< SAS ID frame of the remote device */ + agsaSASIdentify_t sasIDframe; + + /**< SAS address of the local device*/ + bit32 sasLocalAddressHi; /**< SAS address high part */ + bit32 sasLocalAddressLo; /**< SAS address low part */ +#ifdef TBD + /**< the list of PhyID belonging to this port */ + bit8 PhyIDList[DM_MAX_NUM_PHYS]; +#endif + dmPortContext_t *dmPortContext; + dmRoot_t *dmRoot; + +#ifdef TBD + /* used in tiINIDiscoverTarget() */ + agsaRoot_t *agRoot; + agsaPortContext_t *agPortContext; + /* maybe needs timers for saPhyStart() */ + + bit8 nativeSATAMode; /* boolean flag: whether the port is in Native SATA mode */ + bit8 remoteSignature[8]; /* the remote signature of the port is the port is in native SATA mode */ +#endif + bit8 directAttatchedSAS; /* boolean flag: whether the port connected directly to SAS end device*/ + /* SAS/SATA discovery information such as discoveringExpanderList */ + dmDiscovery_t discovery; + bit32 valid; + bit8 LinkRate; + bit32 RegisteredDevNums; /* registered number of devices */ + bit32 eventPhyID; /* used for saHwEventAck() */ + bit32 Transient; /* transient period between link up and link down/port recovery */ + bit32 RegFailed; /* Registration of expander belonging to this port failure */ + +} dmIntPortContext_t; + +typedef struct dmDeviceData_s { + + dmList_t FreeLink; /* free dev list */ + dmList_t MainLink; /* main(in use) dev list */ + dmList_t IncDisLink; /* Used for incremental Discovery only */ + bit32 id; /* for debugging only */ + bit8 DeviceType; + /* used in tiINIIOStart() */ + dmRoot_t *dmRoot; +// agsaDevHandle_t *agDevHandle; + + /* for SAS; remote device */ + // agsaSASDeviceInfo_t agSASDeviceInfo; + /* device's sas address */ + DMSASAddressID_t SASAddressID; + bit8 initiator_ssp_stp_smp; + bit8 target_ssp_stp_smp; + bit8 numOfPhys; + + /* SATA specific data */ + bit8 satSignature[8]; /* SATA device Signature*/ + + /**< pointer to tdsaPortcontext which the device belongs to */ + struct dmIntPortContext_s *dmPortContext; + /* validity of device */ + bit8 valid; + bit8 valid2; + bit8 processed; /* used in TD discovery */ +#ifdef AGTIAPI_CTL + bit8 discovered; +#endif + agsaDeviceInfo_t agDeviceInfo; + dmDeviceInfo_t dmDeviceInfo; + agsaContext_t agContext; /* used in saRegisterNewDevice()*/ + /**< pointer to dmExpander if Device is expander */ + struct dmExpander_s *dmExpander; + struct dmDeviceData_s *ExpDevice; /* Expander device which this device is attached to */ + + bit8 phyID; /* PhyID this device is attached to SPC or expander */ + agsaSASIdentify_t sasIdentify; /* used only in TD discovery */ + bit8 connectionRate; +// bit8 registered; + bit8 directlyAttached; + bit8 SASSpecDeviceType; /* 0 - 3; SAS_NO_DEVICE - SAS_FANOUT_EXPANDER_DEVICE */ + bit32 IOStart; + bit32 IOResponse; + agsaContext_t agDeviceResetContext; /* used in saLocalPhyControl() */ + bit32 TRflag; /* transport recovery flag; used only for tiINITransportRecovery */ + bit32 ResetCnt; /* number of reset to the device */ + bit32 registered; /* registered to LL */ + bit32 reported; /* reproted to TDM */ + bit32 MCN; /* MCN; initialized to 0; current value in discovery */ + bit32 MCNDone; /* done in updating MCN */ + bit32 PrevMCN; /* MCN; initialized to 0; previous value in discovery */ + +} dmDeviceData_t; + + +typedef struct dmExpander_s +{ + /* start of dmDeviceData */ +#ifdef TBD + dmList_t FreeLink; /* free dev list */ + dmList_t MainLink; /* main(in use) dev list */ +#endif + bit32 id; /* for debugging only */ + bit32 InQID; /* Inbound queue ID */ + bit32 OutQID; /* Outbound queue ID */ + bit8 DeviceType; + /* used in tiINIIOStart() */ + dmRoot_t *dmRoot; + agsaDevHandle_t *agDevHandle; + + dmList_t linkNode; /**< the link node data structure of the expander */ + dmList_t upNode; /**< the link node data structure of the expander */ + dmDeviceData_t *dmDevice; /**< the pointer to the device data */ + struct dmExpander_s *dmUpStreamExpander; /**< the pointer to the upstream expander device */ + bit8 hasUpStreamDevice; + bit8 discoveringPhyId; + bit16 routingIndex; /* maximum routing table index reported by expander */ + bit16 currentIndex[DM_MAX_EXPANDER_PHYS]; /* routing table index in use */ + /*ReportPhySataSend in DM */ + dmDeviceData_t *dmDeviceToProcess; /* on some callbacks, this is a link to the device of interest */ + + bit32 configSASAddressHi; + bit32 configSASAddressLo; + struct dmExpander_s *dmCurrentDownStreamExpander; + bit8 upStreamPhys[DM_MAX_EXPANDER_PHYS]; + bit16 numOfUpStreamPhys; + bit16 currentUpStreamPhyIndex; + bit32 upStreamSASAddressHi; + bit32 upStreamSASAddressLo; + bit32 underDiscovering; + bit32 configRouteTable: 1; + bit32 configuring: 1; + bit32 configReserved: 30; +#ifdef TBD + bit32 id; /* for debugging */ +#endif + struct dmExpander_s *dmReturnginExpander; + bit8 downStreamPhys[DM_MAX_EXPANDER_PHYS]; + bit16 numOfDownStreamPhys; + bit8 currentDownStreamPhyIndex; + bit32 discoverSMPAllowed; /* used only for configurable routers */ + bit8 routingAttribute[DM_MAX_EXPANDER_PHYS]; + bit32 configSASAddressHiTable[DM_MAX_DEV]; + bit32 configSASAddressLoTable[DM_MAX_DEV]; + bit32 configSASAddrTableIndex; + /* for SAS 2 */ + bit32 SAS2; /* supports SAS2 spec of not. The value of LONG RESPONSE + in report general response */ + bit32 TTTSupported; /* Table to Table is supported */ + bit32 UndoDueToTTTSupported; /* flag that indicates undo exp, device, route + configuration due to TTT */ + +} dmExpander_t; + +typedef struct dmIndirectSMPRequestBody_s { + dmList_t Link; + bit32 id; + +} dmIndirectSMPRequestBody_t; + +/* + should DM allocate a pool of SMP and manages it + or + depend on ostiAllocMemory() +*/ +typedef struct dmSMPRequestBody_s { + dmList_t Link; + dmSMPCompleted_t SMPCompletionFunc;/* must be the second */ + +#ifdef TBD + tiDeviceHandle_t *tiDevHandle; /* not used for TD generated SMP */ +#endif + agsaIORequest_t agIORequest; + agsaSASRequestBody_t agSASRequestBody; + agsaSATAInitiatorRequest_t agSATARequestBody; + /**< SMP response */ + //agsaSMPFrame_t SMPRsp; + dmDeviceData_t *dmDevice; + +#ifdef TBD + void *osMemHandle; + // can this be simply dmExpander_t + dmDeviceData_t *dmDevice; + tiIORequest_t *CurrentTaskTag; /* SMP is used for simulate target reset */ +#endif + dmRoot_t *dmRoot; +// dmExpander_t *dmExpander; + dmIntPortContext_t *dmPortContext; /* portcontext where SMP is sent from */ + bit8 smpPayload[SMP_DIRECT_PAYLOAD_LIMIT]; /* for smp retries; + only for direct SMP */ + bit32 retries; /* number of retries */ + /* for indirect SMP req/rsp */ + void *IndirectSMP; + bit32 IndirectSMPUpper32; + bit32 IndirectSMPLower32; + /* used only when SMP is INDIRECT SMP request. On SMP completion, + this is used to free up INDIRECT SMP response + */ + void *IndirectSMPResponse; /* dmSMPRequestBody_t */ + + + +#ifdef TBD + void *IndirectSMPReqosMemHandle; + void *IndirectSMPReq; + bit32 IndirectSMPReqLen; + bit32 IndirectSMPReqUpper32; + bit32 IndirectSMPReqLower32; + void *IndirectSMPResposMemHandle; + void *IndirectSMPResp; + bit32 IndirectSMPRespLen; + bit32 IndirectSMPRespUpper32; + bit32 IndirectSMPRespLower32; +#endif + bit32 id; + agsaContext_t agContext; +} dmSMPRequestBody_t; + + +typedef struct dmIntContext_s { + /**< agsaRoot_t->osData points to this */ + struct dmRootOsData_s dmRootOsData; + + bit32 usecsPerTick; +#ifdef TBD + dmRoot_t dmRootInt; /* for interrupt */ + dmRoot_t dmRootNonInt; /* for non-interrupt */ +#endif + + agsaRoot_t *agRoot; + + /**< software-related initialization params used in saInitialize() */ + dmSwConfig_t SwConfig; + + /**< timers used commonly in SAS/SATA */ + dmList_t timerlist; + /**< pointer to PortContext memory; */ + dmIntPortContext_t *PortContextMem; + + dmList_t FreePortContextList; + dmList_t MainPortContextList; + + /**< pointer to Device memory */ + dmDeviceData_t *DeviceMem; + dmList_t FreeDeviceList; + dmList_t MainDeviceList; + + /**< pointer to Expander memory */ + dmExpander_t *ExpanderMem; + dmList_t freeExpanderList; + dmList_t mainExpanderList; + + /**< pointer to SMP command memory */ + dmSMPRequestBody_t *SMPMem; + dmList_t freeSMPList; + + /**< pointer to Indirect SMP request/repsonse memory */ + bit8 *IndirectSMPMem; + bit32 IndirectSMPUpper32; + bit32 IndirectSMPLower32; + bit32 itNexusTimeout; + bit32 MaxRetryDiscovery; + bit32 RateAdjust; + +} dmIntContext_t; + +typedef struct dmIntRoot_s +{ + /**<< common data structure for SAS/SATA */ + dmIntContext_t dmAllShared; +} dmIntRoot_t; + +#endif /* __DMTYPES_H__ */ + diff --git a/sys/dev/pms/RefTisa/sallsdk/api/sa.h b/sys/dev/pms/RefTisa/sallsdk/api/sa.h new file mode 100644 index 000000000000..e13db5390f4e --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/api/sa.h @@ -0,0 +1,3957 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/*******************************************************************************/ +/*! \file sa.h + * \brief The file defines the constants, data structure, and functions defined by LL API + */ +/******************************************************************************/ + +#ifndef __SA_H__ +#define __SA_H__ + +#include +#include + +/* TestBase needed to have the 'Multi-Data fetch disable' feature */ +#define SA_CONFIG_MDFD_REGISTRY + +#define OSSA_OFFSET_OF(STRUCT_TYPE, FEILD) \ + (bitptr)&(((STRUCT_TYPE *)0)->FEILD) + +#if defined(SA_CPU_LITTLE_ENDIAN) + +#define OSSA_WRITE_LE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ + (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit16)(VALUE16); + +#define OSSA_WRITE_LE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ + (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit32)(VALUE32); + +#define OSSA_READ_LE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ + (*((bit16 *)ADDR16)) = (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) + +#define OSSA_READ_LE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ + (*((bit32 *)ADDR32)) = (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) + +#define OSSA_WRITE_BE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)((((bit16)VALUE16)>>8)&0xFF); \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)(((bit16)VALUE16)&0xFF); + +#define OSSA_WRITE_BE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)((((bit32)VALUE32)>>24)&0xFF); \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>8)&0xFF); \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)(((bit32)VALUE32)&0xFF); + +#define OSSA_READ_BE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ + (*(bit8 *)(((bit8 *)ADDR16)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ + (*(bit8 *)(((bit8 *)ADDR16))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); + +#define OSSA_READ_BE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ + (*(bit8 *)(((bit8 *)ADDR32)+3)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ + (*(bit8 *)(((bit8 *)ADDR32)+2)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); \ + (*(bit8 *)(((bit8 *)ADDR32)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))); \ + (*(bit8 *)(((bit8 *)ADDR32))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))); + +#define OSSA_WRITE_BYTE_STRING(AGROOT, DEST_ADDR, SRC_ADDR, LEN) \ + si_memcpy(DEST_ADDR, SRC_ADDR, LEN); + + +#elif defined(SA_CPU_BIG_ENDIAN) + +#define OSSA_WRITE_LE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit16)VALUE16)>>8)&0xFF); \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)(((bit16)VALUE16)&0xFF); + +#define OSSA_WRITE_LE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)((((bit32)VALUE32)>>24)&0xFF); \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>8)&0xFF); \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)(((bit32)VALUE32)&0xFF); + +#define OSSA_READ_LE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ + (*(bit8 *)(((bit8 *)ADDR16)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ + (*(bit8 *)(((bit8 *)ADDR16))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); + +#define OSSA_READ_LE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ + (*((bit8 *)(((bit8 *)ADDR32)+3))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ + (*((bit8 *)(((bit8 *)ADDR32)+2))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); \ + (*((bit8 *)(((bit8 *)ADDR32)+1))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))); \ + (*((bit8 *)(((bit8 *)ADDR32)))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))); + +#define OSSA_WRITE_BE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ + (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit16)(VALUE16); + +#define OSSA_WRITE_BE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ + (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit32)(VALUE32); + +#define OSSA_READ_BE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ + (*((bit16 *)ADDR16)) = (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); + +#define OSSA_READ_BE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ + (*((bit32 *)ADDR32)) = (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); + +#define OSSA_WRITE_BYTE_STRING(AGROOT, DEST_ADDR, SRC_ADDR, LEN) \ + si_memcpy(DEST_ADDR, SRC_ADDR, LEN); + +#else + +#error (Host CPU endianess undefined!!) + +#endif + +#define AGSA_WRITE_SGL(sglDest, sgLower, sgUpper, len, extReserved) \ + OSSA_WRITE_LE_32(agRoot, sglDest, 0, sgLower); \ + OSSA_WRITE_LE_32(agRoot, sglDest, 4, sgUpper); \ + OSSA_WRITE_LE_32(agRoot, sglDest, 8, len); \ + OSSA_WRITE_LE_32(agRoot, sglDest, 12, extReserved); + + +/************************************************************************** + * define byte swap macro * + **************************************************************************/ +/*! \def AGSA_FLIP_2_BYTES(_x) +* \brief AGSA_FLIP_2_BYTES macro +* +* use to flip two bytes +*/ +#define AGSA_FLIP_2_BYTES(_x) ((bit16)(((((bit16)(_x))&0x00FF)<<8)| \ + ((((bit16)(_x))&0xFF00)>>8))) + +/*! \def AGSA_FLIP_4_BYTES(_x) +* \brief AGSA_FLIP_4_BYTES macro +* +* use to flip four bytes +*/ +#define AGSA_FLIP_4_BYTES(_x) ((bit32)(((((bit32)(_x))&0x000000FF)<<24)| \ + ((((bit32)(_x))&0x0000FF00)<<8)| \ + ((((bit32)(_x))&0x00FF0000)>>8)| \ + ((((bit32)(_x))&0xFF000000)>>24))) + + +#if defined(SA_CPU_LITTLE_ENDIAN) + +/*! \def LEBIT16_TO_BIT16(_x) +* \brief LEBIT16_TO_BIT16 macro +* +* use to convert little endian bit16 to host bit16 +*/ +#ifndef LEBIT16_TO_BIT16 +#define LEBIT16_TO_BIT16(_x) (_x) +#endif + +/*! \def BIT16_TO_LEBIT16(_x) +* \brief BIT16_TO_LEBIT16 macro +* +* use to convert host bit16 to little endian bit16 +*/ +#ifndef BIT16_TO_LEBIT16 +#define BIT16_TO_LEBIT16(_x) (_x) +#endif + +/*! \def BEBIT16_TO_BIT16(_x) +* \brief BEBIT16_TO_BIT16 macro +* +* use to convert big endian bit16 to host bit16 +*/ +#ifndef BEBIT16_TO_BIT16 +#define BEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x) +#endif + +/*! \def BIT16_TO_BEBIT16(_x) +* \brief BIT16_TO_BEBIT16 macro +* +* use to convert host bit16 to big endian bit16 +*/ +#ifndef BIT16_TO_BEBIT16 +#define BIT16_TO_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x) +#endif + +/*! \def LEBIT32_TO_BIT32(_x) +* \brief LEBIT32_TO_BIT32 macro +* +* use to convert little endian bit32 to host bit32 +*/ +#ifndef LEBIT32_TO_BIT32 +#define LEBIT32_TO_BIT32(_x) (_x) +#endif + +/*! \def BIT32_TO_LEBIT32(_x) +* \brief BIT32_TO_LEBIT32 macro +* +* use to convert host bit32 to little endian bit32 +*/ +#ifndef BIT32_TO_LEBIT32 +#define BIT32_TO_LEBIT32(_x) (_x) +#endif + +/*! \def BEBIT32_TO_BIT32(_x) +* \brief BEBIT32_TO_BIT32 macro +* +* use to convert big endian bit32 to host bit32 +*/ +#ifndef BEBIT32_TO_BIT32 +#define BEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x) +#endif + +/*! \def BIT32_TO_BEBIT32(_x) +* \brief BIT32_TO_BEBIT32 macro +* +* use to convert host bit32 to big endian bit32 +*/ +#ifndef BIT32_TO_BEBIT32 +#define BIT32_TO_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x) +#endif + + +/* + * bit8 to Byte[x] of bit32 + */ +#ifndef BIT8_TO_BIT32_B0 +#define BIT8_TO_BIT32_B0(_x) ((bit32)(_x)) +#endif + +#ifndef BIT8_TO_BIT32_B1 +#define BIT8_TO_BIT32_B1(_x) (((bit32)(_x)) << 8) +#endif + +#ifndef BIT8_TO_BIT32_B2 +#define BIT8_TO_BIT32_B2(_x) (((bit32)(_x)) << 16) +#endif + +#ifndef BIT8_TO_BIT32_B3 +#define BIT8_TO_BIT32_B3(_x) (((bit32)(_x)) << 24) +#endif + +/* + * Byte[x] of bit32 to bit8 + */ +#ifndef BIT32_B0_TO_BIT8 +#define BIT32_B0_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF)) +#endif + +#ifndef BIT32_B1_TO_BIT8 +#define BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8)) +#endif + +#ifndef BIT32_B2_TO_BIT8 +#define BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16)) +#endif + +#ifndef BIT32_B3_TO_BIT8 +#define BIT32_B3_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24)) +#endif + +#elif defined(SA_CPU_BIG_ENDIAN) + +/*! \def LEBIT16_TO_BIT16(_x) +* \brief LEBIT16_TO_BIT16 macro +* +* use to convert little endian bit16 to host bit16 +*/ +#ifndef LEBIT16_TO_BIT16 +#define LEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x) +#endif + +/*! \def BIT16_TO_LEBIT16(_x) +* \brief BIT16_TO_LEBIT16 macro +* +* use to convert host bit16 to little endian bit16 +*/ +#ifndef BIT16_TO_LEBIT16 +#define BIT16_TO_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x) +#endif + +/*! \def BEBIT16_TO_BIT16(_x) +* \brief BEBIT16_TO_BIT16 macro +* +* use to convert big endian bit16 to host bit16 +*/ +#ifndef BEBIT16_TO_BIT16 +#define BEBIT16_TO_BIT16(_x) (_x) +#endif + +/*! \def BIT16_TO_BEBIT16(_x) +* \brief BIT16_TO_BEBIT16 macro +* +* use to convert host bit16 to big endian bit16 +*/ +#ifndef BIT16_TO_BEBIT16 +#define BIT16_TO_BEBIT16(_x) (_x) +#endif + +/*! \def LEBIT32_TO_BIT32(_x) +* \brief LEBIT32_TO_BIT32 macro +* +* use to convert little endian bit32 to host bit32 +*/ +#ifndef LEBIT32_TO_BIT32 +#define LEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x) +#endif + +/*! \def BIT32_TO_LEBIT32(_x) +* \brief BIT32_TO_LEBIT32 macro +* +* use to convert host bit32 to little endian bit32 +*/ +#ifndef BIT32_TO_LEBIT32 +#define BIT32_TO_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x) +#endif + +/*! \def BEBIT32_TO_BIT32(_x) +* \brief BEBIT32_TO_BIT32 macro +* +* use to convert big endian bit32 to host bit32 +*/ +#ifndef BEBIT32_TO_BIT32 +#define BEBIT32_TO_BIT32(_x) (_x) +#endif + +/*! \def BIT32_TO_BEBIT32(_x) +* \brief BIT32_TO_BEBIT32 macro +* +* use to convert host bit32 to big endian bit32 +*/ +#ifndef BIT32_TO_BEBIT32 +#define BIT32_TO_BEBIT32(_x) (_x) +#endif + + +/* + * bit8 to Byte[x] of bit32 + */ +#ifndef BIT8_TO_BIT32_B0 +#define BIT8_TO_BIT32_B0(_x) (((bit32)(_x)) << 24) +#endif + +#ifndef BIT8_TO_BIT32_B1 +#define BIT8_TO_BIT32_B1(_x) (((bit32)(_x)) << 16) +#endif + +#ifndef BIT8_TO_BIT32_B2 +#define BIT8_TO_BIT32_B2(_x) (((bit32)(_x)) << 8) +#endif + +#ifndef BIT8_TO_BIT32_B3 +#define BIT8_TO_BIT32_B3(_x) ((bit32)(_x)) +#endif + +/* + * Byte[x] of bit32 to bit8 + */ +#ifndef BIT32_B0_TO_BIT8 +#define BIT32_B0_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24)) +#endif + +#ifndef BIT32_B1_TO_BIT8 +#define BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16)) +#endif + +#ifndef BIT32_B2_TO_BIT8 +#define BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8)) +#endif + +#ifndef BIT32_B3_TO_BIT8 +#define BIT32_B3_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF)) +#endif + +#else + +#error No definition of SA_CPU_BIG_ENDIAN or SA_CPU_LITTLE_ENDIAN + +#endif + + +#if defined(SA_DMA_LITTLE_ENDIAN) + +/* + * ** bit32 to bit32 + * */ +#ifndef DMA_BIT32_TO_BIT32 +#define DMA_BIT32_TO_BIT32(_x) (_x) +#endif + +#ifndef DMA_LEBIT32_TO_BIT32 +#define DMA_LEBIT32_TO_BIT32(_x) (_x) +#endif + +#ifndef DMA_BEBIT32_TO_BIT32 +#define DMA_BEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x) +#endif + +#ifndef BIT32_TO_DMA_BIT32 +#define BIT32_TO_DMA_BIT32(_x) (_x) +#endif + +#ifndef BIT32_TO_DMA_LEBIT32 +#define BIT32_TO_DMA_LEBIT32(_x) (_x) +#endif + +#ifndef BIT32_TO_DMA_BEBIT32 +#define BIT32_TO_DMA_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x) +#endif + + +/* + * ** bit16 to bit16 + * */ +#ifndef DMA_BIT16_TO_BIT16 +#define DMA_BIT16_TO_BIT16(_x) (_x) +#endif + +#ifndef DMA_LEBIT16_TO_BIT16 +#define DMA_LEBIT16_TO_BIT16(_x) (_x) +#endif + +#ifndef DMA_BEBIT16_TO_BIT16 +#define DMA_BEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x) +#endif + +#ifndef BIT16_TO_DMA_BIT16 +#define BIT16_TO_DMA_BIT16(_x) (_x) +#endif + +#ifndef BIT16_TO_DMA_LEBIT16 +#define BIT16_TO_DMA_LEBIT16(_x) (_x) +#endif + +#ifndef BIT16_TO_DMA_BEBIT16 +#define BIT16_TO_DMA_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x) +#endif + +#if defined(SA_CPU_LITTLE_ENDIAN) + +#ifndef BEBIT32_TO_DMA_BEBIT32 +#define BEBIT32_TO_DMA_BEBIT32(_x) (_x) +#endif + +#ifndef LEBIT32_TO_DMA_LEBIT32 +#define LEBIT32_TO_DMA_LEBIT32(_x) (_x) +#endif + +#ifndef DMA_LEBIT32_TO_LEBIT32 +#define DMA_LEBIT32_TO_LEBIT32(_x) (_x) +#endif + +#ifndef DMA_BEBIT32_TO_BEBIT32 +#define DMA_BEBIT32_TO_BEBIT32(_x) (_x) +#endif + +/* + * ** bit16 to bit16 + * */ +#ifndef BEBIT16_TO_DMA_BEBIT16 +#define BEBIT16_TO_DMA_BEBIT16(_x) (_x) +#endif + +#ifndef LEBIT16_TO_DMA_LEBIT16 +#define LEBIT16_TO_DMA_LEBIT16(_x) (_x) +#endif + +#ifndef DMA_LEBIT16_TO_LEBIT16 +#define DMA_LEBIT16_TO_LEBIT16(_x) (_x) +#endif + +#ifndef DMA_BEBIT16_TO_BEBIT16 +#define DMA_BEBIT16_TO_BEBIT16(_x) (_x) +#endif + +#else /* defined(SA_CPU_BIG_ENDIAN) */ + + +/* + * ** bit32 to bit32 + * */ +#ifndef BEBIT32_TO_DMA_BEBIT32 +#define BEBIT32_TO_DMA_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x) +#endif + +#ifndef LEBIT32_TO_DMA_LEBIT32 +#define LEBIT32_TO_DMA_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x) +#endif + +#ifndef DMA_LEBIT32_TO_LEBIT32 +#define DMA_LEBIT32_TO_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x) +#endif + +#ifndef DMA_BEBIT32_TO_BEBIT32 +#define DMA_BEBIT32_TO_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x) +#endif + +/* + * ** bit16 to bit16 + * */ +#ifndef BEBIT16_TO_DMA_BEBIT16 +#define BEBIT16_TO_DMA_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x) +#endif + +#ifndef LEBIT16_TO_DMA_LEBIT16 +#define LEBIT16_TO_DMA_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x) +#endif + +#ifndef DMA_LEBIT16_TO_LEBIT16 +#define DMA_LEBIT16_TO_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x) +#endif + +#ifndef DMA_BEBIT16_TO_BEBIT16 +#define DMA_BEBIT16_TO_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x) +#endif + +#endif + +/* + * bit8 to Byte[x] of bit32 + */ +#ifndef BIT8_TO_DMA_BIT32_B0 +#define BIT8_TO_DMA_BIT32_B0(_x) ((bit32)(_x)) +#endif + +#ifndef BIT8_TO_DMA_BIT32_B1 +#define BIT8_TO_DMA_BIT32_B1(_x) (((bit32)(_x)) << 8) +#endif + +#ifndef BIT8_TO_DMA_BIT32_B2 +#define BIT8_TO_DMA_BIT32_B2(_x) (((bit32)(_x)) << 16) +#endif + +#ifndef BIT8_TO_DMA_BIT32_B3 +#define BIT8_TO_DMA_BIT32_B3(_x) (((bit32)(_x)) << 24) +#endif + +/* + * Byte[x] of bit32 to bit8 + */ +#ifndef DMA_BIT32_B0_TO_BIT8 +#define DMA_BIT32_B0_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF)) +#endif + +#ifndef DMA_BIT32_B1_TO_BIT8 +#define DMA_BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8)) +#endif + +#ifndef DMA_BIT32_B2_TO_BIT8 +#define DMA_BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16)) +#endif + +#ifndef DMA_BIT32_B3_TO_BIT8 +#define DMA_BIT32_B3_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24)) +#endif + +/*| | + | end of DMA access macros for LITTLE ENDIAN | + --------------------------------------------------------------------- + */ + +#elif defined(SA_DMA_BIG_ENDIAN) /* DMA big endian */ + +/*-------------------------------------------------------------------- + | DMA buffer access macros for BIG ENDIAN | + | | + */ + +/* bit32 to bit32 */ +#ifndef DMA_BEBIT32_TO_BIT32 +#define DMA_BEBIT32_TO_BIT32(_x) (_x) +#endif + +#ifndef DMA_LEBIT32_TO_BIT32 +#define DMA_LEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x) +#endif + +#ifndef BIT32_TO_DMA_BIT32 +#define BIT32_TO_DMA_BIT32(_x) (_x) +#endif + +#ifndef BIT32_TO_DMA_LEBIT32 +#define BIT32_TO_DMA_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x) +#endif + +#ifndef BIT32_TO_DMA_BEBIT32 +#define BIT32_TO_DMA_BEBIT32(_x) (_x) +#endif + +/* bit16 to bit16 */ +#ifndef DMA_BEBIT16_TO_BIT16 +#define DMA_BEBIT16_TO_BIT16(_x) (_x) +#endif + +#ifndef DMA_LEBIT16_TO_BIT16 +#define DMA_LEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x) +#endif + +#ifndef BIT16_TO_DMA_BIT16 +#define BIT16_TO_DMA_BIT16(_x) (_x) +#endif + +#ifndef BIT16_TO_DMA_LEBIT16 +#define BIT16_TO_DMA_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x) +#endif + +#ifndef BIT16_TO_DMA_BEBIT16 +#define BIT16_TO_DMA_BEBIT16(_x) (_x) +#endif + + +#if defined(SA_CPU_LITTLE_ENDIAN) /* CPU little endain */ + +/* bit32 to bit32 */ +#ifndef BEBIT32_TO_DMA_BEBIT32 +#define BEBIT32_TO_DMA_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x) +#endif + +#ifndef LEBIT32_TO_DMA_LEBIT32 +#define LEBIT32_TO_DMA_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x) +#endif + +#ifndef DMA_LEBIT32_TO_LEBIT32 +#define DMA_LEBIT32_TO_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x) +#endif + +#ifndef DMA_BEBIT32_TO_BEBIT32 +#define DMA_BEBIT32_TO_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x) +#endif + +/* bit16 to bit16 */ +#ifndef BEBIT16_TO_DMA_BEBIT16 +#define BEBIT16_TO_DMA_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x) +#endif + +#ifndef LEBIT16_TO_DMA_LEBIT16 +#define LEBIT16_TO_DMA_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x) +#endif + +#ifndef DMA_LEBIT16_TO_LEBIT16 +#define DMA_LEBIT16_TO_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x) +#endif + +#ifndef DMA_BEBIT16_TO_BEBIT16 +#define DMA_BEBIT16_TO_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x) +#endif + + +#else /* defined(SA_CPU_BIG_ENDIAN) */ + +/* bit32 to bit32 */ +#ifndef BEBIT32_TO_DMA_BEBIT32 +#define BEBIT32_TO_DMA_BEBIT32(_x) (_x) +#endif + +#ifndef LEBIT32_TO_DMA_LEBIT32 +#define LEBIT32_TO_DMA_LEBIT32(_x) (_x) +#endif + +#ifndef DMA_LEBIT32_TO_LEBIT32 +#define DMA_LEBIT32_TO_LEBIT32(_x) (_x) +#endif + +#ifndef DMA_BEBIT32_TO_BEBIT32 +#define DMA_BEBIT32_TO_BEBIT32(_x) (_x) +#endif + +/* bit16 to bit16 */ +#ifndef BEBIT16_TO_DMA_BEBIT16 +#define BEBIT16_TO_DMA_BEBIT16(_x) (_x) +#endif + +#ifndef LEBIT16_TO_DMA_LEBIT16 +#define LEBIT16_TO_DMA_LEBIT16(_x) (_x) +#endif + +#ifndef DMA_LEBIT16_TO_LEBIT16 +#define DMA_LEBIT16_TO_LEBIT16(_x) (_x) +#endif + +#ifndef DMA_BEBIT16_TO_BEBIT16 +#define DMA_BEBIT16_TO_BEBIT16(_x) (_x) +#endif + +#endif + +/* + * bit8 to Byte[x] of bit32 + */ +#ifndef BIT8_TO_DMA_BIT32_B0 +#define BIT8_TO_DMA_BIT32_B0(_x) (((bit32)(_x)) << 24) +#endif + +#ifndef BIT8_TO_DMA_BIT32_B1 +#define BIT8_TO_DMA_BIT32_B1(_x) (((bit32)(_x)) << 16) +#endif + +#ifndef BIT8_TO_DMA_BIT32_B2 +#define BIT8_TO_DMA_BIT32_B2(_x) (((bit32)(_x)) << 8) +#endif + +#ifndef BIT8_TO_DMA_BIT32_B3 +#define BIT8_TO_DMA_BIT32_B3(_x) ((bit32)(_x)) +#endif + +/* + * ** Byte[x] of bit32 to bit8 + * */ +#ifndef DMA_BIT32_B0_TO_BIT8 +#define DMA_BIT32_B0_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24)) +#endif + +#ifndef DMA_BIT32_B1_TO_BIT8 +#define DMA_BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16)) +#endif + +#ifndef DMA_BIT32_B2_TO_BIT8 +#define DMA_BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8)) +#endif + +#ifndef DMA_BIT32_B3_TO_BIT8 +#define DMA_BIT32_B3_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF)) +#endif + +/*| | + | end of DMA access macros for BIG ENDIAN | + --------------------------------------------------------------------- +*/ +#else + +#error No definition of SA_DMA_BIG_ENDIAN or SA_DMA_LITTLE_ENDIAN + +#endif /* DMA endian */ +/* + * End of DMA buffer access macros * + * * + ********************************************************************** + */ + +/************************************************************************************ + * * + * Constants defined for LL Layer starts * + * * + ************************************************************************************/ + +/********************************************************* + * sTSDK LL revision and Interface revision, FW version + *********************************************************/ + +#define FW_THIS_VERSION_SPC12G 0x03060005 + +#define FW_THIS_VERSION_SPC6G 0x02092400 +#define FW_THIS_VERSION_SPC 0x01110000 + + +#define STSDK_LL_INTERFACE_VERSION 0x20A +#define STSDK_LL_OLD_INTERFACE_VERSION 0x1 /* SPC and SPCv before 02030401 */ +#define STSDK_LL_VERSION FW_THIS_VERSION_SPC6G /**< current sTSDK version */ +#define MAX_FW_VERSION_SUPPORTED FW_THIS_VERSION_SPC6G /**< FW */ +#define MATCHING_V_FW_VERSION FW_THIS_VERSION_SPC6G /**< current V matching FW version */ +#define MIN_FW_SPCVE_VERSION_SUPPORTED 0x02000000 /**< 2.00 FW */ + +#define STSDK_LL_12G_INTERFACE_VERSION 0x302 +#define STSDK_LL_12G_VERSION FW_THIS_VERSION_SPC12G /**< current sTSDK version */ +#define MAX_FW_12G_VERSION_SUPPORTED FW_THIS_VERSION_SPC12G /**< FW */ +#define MATCHING_12G_V_FW_VERSION FW_THIS_VERSION_SPC12G /**< current V matching FW version */ +#define MIN_FW_12G_SPCVE_VERSION_SUPPORTED 0x03000000 /**< 3.00 FW */ + +#define STSDK_LL_SPC_VERSION 0x01100000 /**< current SPC FW version supported */ +#define MATCHING_SPC_FW_VERSION FW_THIS_VERSION_SPC /**< current SPC matching FW version */ +#define MIN_FW_SPC_VERSION_SUPPORTED 0x01062502 /**< 1.06d FW */ + +#define STSDK_LL_INTERFACE_VERSION_IGNORE_MASK 0xF00 +/************************************************* + * constants for API return values + *************************************************/ +#define AGSA_RC_SUCCESS 0x00 /**< Successful function return value */ +#define AGSA_RC_FAILURE 0x01 /**< Failed function return value */ +#define AGSA_RC_BUSY 0x02 /**< Busy function return value */ +/* current only return from saGetControllerInfo() and saGetControllerStatus() */ +#define AGSA_RC_HDA_NO_FW_RUNNING 0x03 /**< HDA mode and no FW running */ +#define AGSA_RC_FW_NOT_IN_READY_STATE 0x04 /**< FW not in ready state */ +/* current only return from saInitialize() for version checking */ +#define AGSA_RC_VERSION_INCOMPATIBLE 0x05 /**< Version mismatch */ +#define AGSA_RC_VERSION_UNTESTED 0x06 /**< Version not tested */ +#define AGSA_RC_NOT_SUPPORTED 0x07 /**< Operation not supported on the current hardware */ +#define AGSA_RC_COMPLETE 0x08 + +/************************************************* + * constants for type field in agsaMem_t + *************************************************/ +#define AGSA_CACHED_MEM 0x00 /**< CACHED memory type */ +#define AGSA_DMA_MEM 0x01 /**< DMA memory type */ +#define AGSA_CACHED_DMA_MEM 0x02 /**< CACHED DMA memory type */ + +#ifdef SA_ENABLE_TRACE_FUNCTIONS +#ifdef FAST_IO_TEST +#define AGSA_NUM_MEM_CHUNKS (12 + AGSA_MAX_INBOUND_Q + AGSA_MAX_OUTBOUND_Q) /**< max # of memory chunks supported */ +#else +#define AGSA_NUM_MEM_CHUNKS (11 + AGSA_MAX_INBOUND_Q + AGSA_MAX_OUTBOUND_Q) /**< max # of memory chunks supported */ +#endif +#else +#ifdef FAST_IO_TEST +#define AGSA_NUM_MEM_CHUNKS (11 + AGSA_MAX_INBOUND_Q + AGSA_MAX_OUTBOUND_Q) /**< max # of memory chunks supported */ +#else +#define AGSA_NUM_MEM_CHUNKS (10 + AGSA_MAX_INBOUND_Q + AGSA_MAX_OUTBOUND_Q) /**< max # of memory chunks supported */ +#endif +#endif /* END SA_ENABLE_TRACE_FUNCTIONS */ + + +/********************************** + * default constant for phy count + **********************************/ +#define AGSA_MAX_VALID_PHYS 16 /* was 8 for SPC */ /**< max # of phys supported by the hardware */ + +/************************************ + * default constant for Esgl entries + ************************************/ +#define MAX_ESGL_ENTRIES 10 /**< max # of extended SG list entry */ + +/******************************************* + * constant for max inbound/outbound queues + *******************************************/ +#define AGSA_MAX_INBOUND_Q 64 /**< max # of inbound queue */ +#define AGSA_MAX_OUTBOUND_Q 64 /**< max # of outbound queue */ +#define AGSA_MAX_BEST_INBOUND_Q 16 /* Max inbound Q number with good IO performance */ + +/**************************** + * Phy Control constants + ****************************/ +#define AGSA_PHY_LINK_RESET 0x01 +#define AGSA_PHY_HARD_RESET 0x02 +#define AGSA_PHY_GET_ERROR_COUNTS 0x03 /* SPC only used in original saLocalPhyControl */ +#define AGSA_PHY_CLEAR_ERROR_COUNTS 0x04 /* SPC only */ +#define AGSA_PHY_GET_BW_COUNTS 0x05 /* SPC only */ +#define AGSA_PHY_NOTIFY_ENABLE_SPINUP 0x10 +#define AGSA_PHY_BROADCAST_ASYNCH_EVENT 0x12 +#define AGSA_PHY_COMINIT_OOB 0x20 + +#define AGSA_SAS_PHY_ERR_COUNTERS_PAGE 0x01 /* retrieve the SAS PHY error counters */ +#define AGSA_SAS_PHY_ERR_COUNTERS_CLR_PAGE 0x02 /* retrieve the SAS PHY error counters After capturing the errors, the hardware error counters are cleared and restarted. */ +#define AGSA_SAS_PHY_BW_COUNTERS_PAGE 0x03 /* retrieve the SAS PHY transmit and receive bandwidth counters. */ +#define AGSA_SAS_PHY_ANALOG_SETTINGS_PAGE 0x04 /* retrieve the SAS PHY analog settings */ +#define AGSA_SAS_PHY_GENERAL_STATUS_PAGE 0x05 /* retrieve the SAS PHY general status for the PHY specified in the phyID parameter */ +#define AGSA_PHY_SNW3_PAGE 0x06 +#define AGSA_PHY_RATE_CONTROL_PAGE 0x07 /* Used to set several rate control parameters. */ +#define AGSA_SAS_PHY_MISC_PAGE 0x08 +#define AGSA_SAS_PHY_OPEN_REJECT_RETRY_BACKOFF_THRESHOLD_PAGE 0x08 /* Used to set retry and backoff threshold parameters. */ + +/***************** + * HW Reset + *****************/ +#define AGSA_CHIP_RESET 0x00 /**< flag to reset hard reset */ +#define AGSA_SOFT_RESET 0x01 /**< flag to reset the controller chip */ + +/*************************************** + * Discovery Types + ***************************************/ +#define AG_SA_DISCOVERY_TYPE_SAS 0x00 /**< flag to discover SAS devices */ +#define AG_SA_DISCOVERY_TYPE_SATA 0x01 /**< flag to discover SATA devices */ + +/*************************************** + * Discovery Options + ***************************************/ +#define AG_SA_DISCOVERY_OPTION_FULL_START 0x00 /**< flag to start full discovery */ +#define AG_SA_DISCOVERY_OPTION_INCREMENTAL_START 0x01 /**< flag to start incremental discovery */ +#define AG_SA_DISCOVERY_OPTION_ABORT 0x02 /**< flag to abort a discovery */ + +/**************************************************************** + * SSP/SMP/SATA Request type + ****************************************************************/ +/* bit31-28 - request type + bit27-16 - reserved + bit15-10 - SATA ATAP + bit9-8 - direction + bit7 - AUTO + bit6 - reserved + bit5 - EXT + bit4 - MSG + bit3-0 - Initiator, target or task mode (1 to 8) + */ +#define AGSA_REQTYPE_MASK 0xF0000000 /**< request type mask */ +#define AGSA_REQ_TYPE_UNKNOWN 0x00000000 /**< unknown request type */ +#define AGSA_SSP_REQTYPE 0x80000000 +#define AGSA_SMP_REQTYPE 0x40000000 +#define AGSA_SATA_REQTYPE 0x20000000 + +#define AGSA_DIR_MASK 0x00000300 +#define AGSA_AUTO_MASK 0x00000080 +#define AGSA_SATA_ATAP_MASK 0x0000FC00 + +#define AGSA_DIR_NONE 0x00000000 +#define AGSA_DIR_CONTROLLER_TO_HOST 0x00000100 /**< used to be called AGSA_DIR_READ */ +#define AGSA_DIR_HOST_TO_CONTROLLER 0x00000200 /**< used to be called AGSA_DIR_WRITE */ + +/* bit definition - AUTO mode */ +#define AGSA_AUTO_GOOD_RESPONSE 0x00000080 + +/* request type - not bit difination */ +#define AGSA_SSP_INIT 0x00000001 +#define AGSA_SSP_TGT_MODE 0x00000003 +#define AGSA_SSP_TASK_MGNT 0x00000005 +#define AGSA_SSP_TGT_RSP 0x00000006 +#define AGSA_SMP_INIT 0x00000007 +#define AGSA_SMP_TGT 0x00000008 + +/* request type for SSP Initiator and extend */ +#define AGSA_SSP_INIT_EXT (AGSA_SSP_INIT | AGSA_SSP_EXT_BIT) + +/* request type for SSP Initiator and indirect */ +#define AGSA_SSP_INIT_INDIRECT (AGSA_SSP_INIT | AGSA_SSP_INDIRECT_BIT) + +/* bit definition */ +#define AGSA_MSG 0x00000010 +#define AGSA_SSP_EXT_BIT 0x00000020 +#define AGSA_SSP_INDIRECT_BIT 0x00000040 +#define AGSA_MSG_BIT AGSA_MSG >> 2 + +/* agsaSSPIniEncryptIOStartCmd_t dirMTlr bits*/ +#define AGSA_INDIRECT_CDB_BIT 0x00000008 +#define AGSA_SKIP_MASK_BIT 0x00000010 +#define AGSA_ENCRYPT_BIT 0x00000020 +#define AGSA_DIF_BIT 0x00000040 +#define AGSA_DIF_LA_BIT 0x00000080 +#define AGSA_DIRECTION_BITS 0x00000300 +#define AGSA_SKIP_MASK_OFFSET_BITS 0x0F000000 +#define AGSA_SSP_INFO_LENGTH_BITS 0xF0000000 + +/* agsaSSPTgtIOStartCmd_t INITagAgrDir bits */ +#define AGSA_SSP_TGT_BITS_INI_TAG 0xFFFF0000 /* 16 31 */ +#define AGSA_SSP_TGT_BITS_ODS 0x00008000 /* 15 */ +#define AGSA_SSP_TGT_BITS_DEE_DIF 0x00004000 /* 14 */ +#define AGSA_SSP_TGT_BITS_DEE 0x00002000 /* 13 14 */ +#define AGSA_SSP_TGT_BITS_R 0x00001000 /* 12 */ +#define AGSA_SSP_TGT_BITS_DAD 0x00000600 /* 11 10 */ +#define AGSA_SSP_TGT_BITS_DIR 0x00000300 /* 8 9 */ +#define AGSA_SSP_TGT_BITS_DIR_IN 0x00000100 /* 8 9 */ +#define AGSA_SSP_TGT_BITS_DIR_OUT 0x00000200 /* 8 9 */ +#define AGSA_SSP_TGT_BITS_AGR 0x00000080 /* 7 */ +#define AGSA_SSP_TGT_BITS_RDF 0x00000040 /* 6 */ +#define AGSA_SSP_TGT_BITS_RTE 0x00000030 /* 4 5 */ +#define AGSA_SSP_TGT_BITS_AN 0x00000006 /* 2 3 */ + + +/* agsaSSPIniEncryptIOStartCmd_t DIF_flags bit definitions */ +#define AGSA_DIF_UPDATE_BITS 0xFC000000 +#define AGSA_DIF_VERIFY_BITS 0x03F00000 +#define AGSA_DIF_BLOCK_SIZE_BITS 0x000F0000 +#define AGSA_DIF_ENABLE_BLOCK_COUNT_BIT 0x00000040 +#define AGSA_DIF_CRC_SEED_BIT 0x00000020 +#define AGSA_DIF_CRC_INVERT_BIT 0x00000010 +#define AGSA_DIF_CRC_VERIFY_BIT 0x00000008 +#define AGSA_DIF_OP_BITS 0x00000007 + +#define AGSA_DIF_OP_INSERT 0x00000000 +#define AGSA_DIF_OP_VERIFY_AND_FORWARD 0x00000001 +#define AGSA_DIF_OP_VERIFY_AND_DELETE 0x00000002 +#define AGSA_DIF_OP_VERIFY_AND_REPLACE 0x00000003 +#define AGSA_DIF_OP_RESERVED2 0x00000004 +#define AGSA_DIF_OP_VERIFY_UDT_REPLACE_CRC 0x00000005 +#define AGSA_DIF_OP_RESERVED3 0x00000006 +#define AGSA_DIF_OP_REPLACE_UDT_REPLACE_CRC 0x00000007 + + +/* agsaSSPIniEncryptIOStartCmd_t EncryptFlagsLo bit definitions */ +#define AGSA_ENCRYPT_DEK_BITS 0xFFFFFF000 +#define AGSA_ENCRYPT_SKIP_DIF_BIT 0x000000010 +#define AGSA_ENCRYPT_KEY_TABLE_BITS 0x00000000C +#define AGSA_ENCRYPT_KEY_TAG_BIT 0x000000002 + +/* Cipher mode to be used for this I/O. */ +#define AGSA_ENCRYPT_ECB_Mode 0 +#define AGSA_ENCRYPT_XTS_Mode 0x6 + +/* agsaSSPIniEncryptIOStartCmd_t EncryptFlagsHi bit definitions */ +#define AGSA_ENCRYPT_KEK_SELECT_BITS 0x0000000E0 +#define AGSA_ENCRYPT_SECTOR_SIZE_BITS 0x00000001F + +/* defined in the sTSDK spec. */ +#define AGSA_SSP_INIT_NONDATA (AGSA_SSP_REQTYPE | AGSA_DIR_NONE | AGSA_SSP_INIT) /**< SSP initiator non data request type */ +#define AGSA_SSP_INIT_READ (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT) /**< SSP initiator read request type */ +#define AGSA_SSP_INIT_WRITE (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT) /**< SSP initiator write request type */ +#define AGSA_SSP_TGT_READ_DATA (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_TGT_MODE) /**< SSP target read data request type */ +#define AGSA_SSP_TGT_READ (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_TGT_MODE) /**< SSP target read data request type */ +#define AGSA_SSP_TGT_READ_GOOD_RESP (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_TGT_MODE | AGSA_AUTO_GOOD_RESPONSE) /**< SSP target read data with automatic good response request type */ +#define AGSA_SSP_TGT_WRITE_DATA (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_TGT_MODE) /**< SSP target write data request type */ +#define AGSA_SSP_TGT_WRITE (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_TGT_MODE) /**< SSP target write data request type */ +#define AGSA_SSP_TGT_WRITE_GOOD_RESP (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_TGT_MODE | AGSA_AUTO_GOOD_RESPONSE) /**< SSP target write data request type with automatic good response request type*/ +#define AGSA_SSP_TASK_MGNT_REQ (AGSA_SSP_REQTYPE | AGSA_SSP_TASK_MGNT) /**< SSP task management request type */ +#define AGSA_SSP_TGT_CMD_OR_TASK_RSP (AGSA_SSP_REQTYPE | AGSA_SSP_TGT_RSP) /**< SSP command or task management response request type */ +#define AGSA_SMP_INIT_REQ (AGSA_SMP_REQTYPE | AGSA_SMP_INIT) /**< SMP initiator request type */ +#define AGSA_SMP_TGT_RESPONSE (AGSA_SMP_REQTYPE | AGSA_SMP_TGT) /**< SMP target response request type */ +#define AGSA_SSP_INIT_READ_M (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT | AGSA_MSG) +#define AGSA_SSP_INIT_WRITE_M (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT | AGSA_MSG) +#define AGSA_SSP_TASK_MGNT_REQ_M (AGSA_SSP_REQTYPE | AGSA_SSP_TASK_MGNT | AGSA_MSG) +#define AGSA_SSP_INIT_READ_EXT (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT_EXT) /**< SSP initiator read request Ext type */ +#define AGSA_SSP_INIT_WRITE_EXT (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT_EXT) /**< SSP initiator write request Ext type */ + +#define AGSA_SSP_INIT_READ_INDIRECT (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT_INDIRECT) /**< SSP initiator read request indirect type */ +#define AGSA_SSP_INIT_WRITE_INDIRECT (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT_INDIRECT) /**< SSP initiator write request indirect type */ + +#define AGSA_SSP_INIT_READ_INDIRECT_M (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT_INDIRECT | AGSA_MSG) /**< SSP initiator read request indirect type */ +#define AGSA_SSP_INIT_WRITE_INDIRECT_M (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT_INDIRECT | AGSA_MSG) /**< SSP initiator write request indirect type */ +#define AGSA_SSP_INIT_READ_EXT_M (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT_EXT | AGSA_MSG) +#define AGSA_SSP_INIT_WRITE_EXT_M (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT_EXT | AGSA_MSG) + +#define AGSA_SMP_IOCTL_REQUEST 0xFFFFFFFF + +#define AGSA_SATA_ATAP_SRST_ASSERT 0x00000400 +#define AGSA_SATA_ATAP_SRST_DEASSERT 0x00000800 +#define AGSA_SATA_ATAP_EXECDEVDIAG 0x00000C00 +#define AGSA_SATA_ATAP_NON_DATA 0x00001000 +#define AGSA_SATA_ATAP_PIO 0x00001400 +#define AGSA_SATA_ATAP_DMA 0x00001800 +#define AGSA_SATA_ATAP_NCQ 0x00001C00 +#define AGSA_SATA_ATAP_PKT_DEVRESET 0x00002000 +#define AGSA_SATA_ATAP_PKT 0x00002400 + +#define AGSA_SATA_PROTOCOL_NON_DATA (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_NON_DATA) +#define AGSA_SATA_PROTOCOL_PIO_READ (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_PIO) /**< SATA PIO read request type */ +#define AGSA_SATA_PROTOCOL_DMA_READ (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_DMA) /**< SATA DMA read request type */ +#define AGSA_SATA_PROTOCOL_FPDMA_READ (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_NCQ) /**< SATA FDMA read request type */ +#define AGSA_SATA_PROTOCOL_PIO_WRITE (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_PIO) /**< SATA PIO read request type */ +#define AGSA_SATA_PROTOCOL_DMA_WRITE (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_DMA) /**< SATA DMA read request type */ +#define AGSA_SATA_PROTOCOL_FPDMA_WRITE (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_NCQ) /**< SATA FDMA read request type */ +#define AGSA_SATA_PROTOCOL_DEV_RESET (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_PKT_DEVRESET) /**< SATA device reset request type */ +#define AGSA_SATA_PROTOCOL_SRST_ASSERT (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_SRST_ASSERT) /**< SATA device reset assert */ +#define AGSA_SATA_PROTOCOL_SRST_DEASSERT (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_SRST_DEASSERT) /**< SATA device reset deassert */ +#define AGSA_SATA_PROTOCOL_D2H_PKT (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_PKT) +#define AGSA_SATA_PROTOCOL_H2D_PKT (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_PKT) +#define AGSA_SATA_PROTOCOL_NON_PKT (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_PKT) + + +#define AGSA_SATA_PROTOCOL_NON_DATA_M (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_NON_DATA | AGSA_MSG) +#define AGSA_SATA_PROTOCOL_PIO_READ_M (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_PIO | AGSA_MSG) /**< SATA PIO read request type */ +#define AGSA_SATA_PROTOCOL_DMA_READ_M (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_DMA | AGSA_MSG) /**< SATA DMA read request type */ +#define AGSA_SATA_PROTOCOL_FPDMA_READ_M (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_NCQ | AGSA_MSG) /**< SATA FDMA read request type */ +#define AGSA_SATA_PROTOCOL_PIO_WRITE_M (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_PIO | AGSA_MSG) /**< SATA PIO read request type */ +#define AGSA_SATA_PROTOCOL_DMA_WRITE_M (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_DMA | AGSA_MSG) /**< SATA DMA read request type */ +#define AGSA_SATA_PROTOCOL_FPDMA_WRITE_M (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_NCQ | AGSA_MSG) /**< SATA FDMA read request type */ +#define AGSA_SATA_PROTOCOL_D2H_PKT_M (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_PKT | AGSA_MSG) +#define AGSA_SATA_PROTOCOL_H2D_PKT_M (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_PKT | AGSA_MSG) +#define AGSA_SATA_PROTOCOL_NON_PKT_M (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_PKT | AGSA_MSG) +/* TestBase */ +#define AGSA_SATA_PROTOCOL_DEV_RESET_M (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_PKT_DEVRESET | AGSA_MSG) /**< SATA device reset request type */ + + + +#define AGSA_INTERRUPT_HANDLE_ALL_CHANNELS 0xFFFFFFFF /**< flag indicates handles interrupts for all channles */ + +/**************************************************************************** +** INBOUND Queue related macros +****************************************************************************/ +#define AGSA_IBQ_PRIORITY_NORMAL 0x0 +#define AGSA_IBQ_PRIORITY_HIGH 0x1 + +/**************************************************************************** +** Phy properties related macros +****************************************************************************/ +/* link rate */ +#define AGSA_PHY_MAX_LINK_RATE_MASK 0x0000000F /* bits 0-3 */ +#define AGSA_PHY_MAX_LINK_RATE_1_5G 0x00000001 /* 0001b */ +#define AGSA_PHY_MAX_LINK_RATE_3_0G 0x00000002 /* 0010b */ +#define AGSA_PHY_MAX_LINK_RATE_6_0G 0x00000004 /* 0100b */ +#define AGSA_PHY_MAX_LINK_RATE_12_0G 0x00000008 /* 1000b */ + +/* SAS/SATA mode */ +#define AGSA_PHY_MODE_MASK 0x00000030 /* bits 4-5 */ +#define AGSA_PHY_MODE_SAS 0x00000010 /* 01b */ +#define AGSA_PHY_MODE_SATA 0x00000020 /* 10b */ + +/* control spin-up hold */ +#define AGSA_PHY_SPIN_UP_HOLD_MASK 0x00000040 /* bit6 */ +#define AGSA_PHY_SPIN_UP_HOLD_ON 0x00000040 /* 1b */ +#define AGSA_PHY_SPIN_UP_HOLD_OFF 0x00000000 /* 0b */ + +/**************************************************************************** +** Device Info related macros +****************************************************************************/ +/* S (SAS/SATA) */ +#define AGSA_DEV_INFO_SASSATA_MASK 0x00000010 /* bit 4 */ +#define AGSA_DEV_INFO_SASSATA_SAS 0x00000010 /* 1b */ +#define AGSA_DEV_INFO_SASSATA_SATA 0x00000000 /* 0b */ + +/* Rate (link-rate) */ +#define AGSA_DEV_INFO_RATE_MASK 0x0000000F /* bits 0-3 */ +#define AGSA_DEV_INFO_RATE_1_5G 0x00000008 /* 8h */ +#define AGSA_DEV_INFO_RATE_3_0G 0x00000009 /* 9h */ +#define AGSA_DEV_INFO_RATE_6_0G 0x0000000A /* Ah */ +#define AGSA_DEV_INFO_RATE_12_0G 0x0000000B /* Bh */ + +/* devType */ +#define AGSA_DEV_INFO_DEV_TYPE_MASK 0x000000E0 /* bits 5-7 */ +#define AGSA_DEV_INFO_DEV_TYPE_END_DEVICE 0x00000020 /* 001b */ +#define AGSA_DEV_INFO_DEV_TYPE_EDGE_EXP_DEVICE 0x00000040 /* 010b */ +#define AGSA_DEV_INFO_DEV_TYPE_FANOUT_EXP_DEVICE 0x00000060 /* 011b */ + +/***************************************************************************** +** SAS TM Function definitions see SAS spec p308 Table 105 (Revision 7) +*****************************************************************************/ +#define AGSA_ABORT_TASK 0x01 +#define AGSA_ABORT_TASK_SET 0x02 +#define AGSA_CLEAR_TASK_SET 0x04 +#define AGSA_LOGICAL_UNIT_RESET 0x08 +#define AGSA_IT_NEXUS_RESET 0x10 +#define AGSA_CLEAR_ACA 0x40 +#define AGSA_QUERY_TASK 0x80 +#define AGSA_QUERY_TASK_SET 0x81 +#define AGSA_QUERY_UNIT_ATTENTION 0x82 + +/***************************************************************************** +** SAS TM Function Response Code see SAS spec p312 Table 111 (Revision 7) +*****************************************************************************/ +#define AGSA_TASK_MANAGEMENT_FUNCTION_COMPLETE 0x0 +#define AGSA_INVALID_FRAME 0x2 +#define AGSA_TASK_MANAGEMENT_FUNCTION_NOT_SUPPORTED 0x4 +#define AGSA_TASK_MANAGEMENT_FUNCTION_FAILED 0x5 +#define AGSA_TASK_MANAGEMENT_FUNCTION_SUCCEEDED 0x8 +#define AGSA_INCORRECT_LOGICAL_UNIT_NUMBER 0x9 +/* SAS spec 9.2.2.5.3 p356 Table 128 (Revision 9e) */ +#define AGSA_OVERLAPPED_TAG_ATTEMPTED 0xA + +#define AGSA_SATA_BSY_OVERRIDE 0x00080000 +#define AGSA_SATA_CLOSE_CLEAR_AFFILIATION 0x00400000 + +#define AGSA_MAX_SMPPAYLOAD_VIA_SFO 40 +#define AGSA_MAX_SSPPAYLOAD_VIA_SFO 36 + +/* SATA Initiator Request option field defintion */ +#define AGSA_RETURN_D2H_FIS_GOOD_COMPLETION 0x000001 +#define AGSA_SATA_ENABLE_ENCRYPTION 0x000004 +#define AGSA_SATA_ENABLE_DIF 0x000008 +#define AGSA_SATA_SKIP_QWORD 0xFFFF00 + +/* SAS Initiator Request flag definitions */ +/* Bits 0,1 use TLR_MASK */ + +#define AGSA_SAS_ENABLE_ENCRYPTION 0x0004 +#define AGSA_SAS_ENABLE_DIF 0x0008 + +#ifdef SAFLAG_USE_DIF_ENC_IOMB +#define AGSA_SAS_USE_DIF_ENC_OPSTART 0x0010 +#endif /* SAFLAG_USE_DIF_ENC_IOMB */ + +#define AGSA_SAS_ENABLE_SKIP_MASK 0x0010 +#define AGSA_SAS_SKIP_MASK_OFFSET 0xFFE0 + +/**************************************************************************** +** SMP Phy control Phy Operation field +****************************************************************************/ +#define AGSA_PHY_CONTROL_LINK_RESET_OP 0x1 +#define AGSA_PHY_CONTROL_HARD_RESET_OP 0x2 +#define AGSA_PHY_CONTROL_DISABLE 0x3 +#define AGSA_PHY_CONTROL_CLEAR_ERROR_LOG_OP 0x5 +#define AGSA_PHY_CONTROL_CLEAR_AFFILIATION 0x6 +#define AGSA_PHY_CONTROL_XMIT_SATA_PS_SIGNAL 0x7 + +/**************************************************************************** +** SAS Diagnostic Operation code +****************************************************************************/ +#define AGSA_SAS_DIAG_START 0x1 +#define AGSA_SAS_DIAG_END 0x0 + +/**************************************************************************** +** Port Control constants +****************************************************************************/ +#define AGSA_PORT_SET_SMP_PHY_WIDTH 0x1 +#define AGSA_PORT_SET_PORT_RECOVERY_TIME 0x2 +#define AGSA_PORT_IO_ABORT 0x3 +#define AGSA_PORT_SET_PORT_RESET_TIME 0x4 +#define AGSA_PORT_HARD_RESET 0x5 +#define AGSA_PORT_CLEAN_UP 0x6 +#define AGSA_STOP_PORT_RECOVERY_TIMER 0x7 + +/* Device State */ +#define SA_DS_OPERATIONAL 0x1 +#define SA_DS_PORT_IN_RESET 0x2 +#define SA_DS_IN_RECOVERY 0x3 +#define SA_DS_IN_ERROR 0x4 +#define SA_DS_NON_OPERATIONAL 0x7 + +/************************************************************************************ + * * + * Constants defined for LL Layer ends * + * * + ************************************************************************************/ + +/************************************************************************************ + * * + * Constants defined for OS Layer starts * + * * + ************************************************************************************/ +/***************************************** + * ossaXXX return values + ******************************************/ +/* common for all ossaXXX CB */ +#define OSSA_SUCCESS 0x00 /**< flag indicates successful callback status */ +#define OSSA_FAILURE 0x01 /**< flag indicates failed callback status */ + +/* ossaHwCB() */ +#define OSSA_RESET_PENDING 0x03 /**< flag indicates reset pending callback status */ +#define OSSA_CHIP_FAILED 0x04 /**< flag indicates chip failed callback status */ +#define OSSA_FREEZE_FAILED 0x05 /**< flag indicates freeze failed callback status */ + +/* ossaLocalPhyControl() */ +#define OSSA_PHY_CONTROL_FAILURE 0x03 /**< flag indicates phy Control operation failure */ + +/* ossaDeviceRegisterCB() */ +#define OSSA_FAILURE_OUT_OF_RESOURCE 0x01 /**< flag indicates failed callback status */ +#define OSSA_FAILURE_DEVICE_ALREADY_REGISTERED 0x02 /**< flag indicates failed callback status */ +#define OSSA_FAILURE_INVALID_PHY_ID 0x03 /**< flag indicates failed callback status */ +#define OSSA_FAILURE_PHY_ID_ALREADY_REGISTERED 0x04 /**< flag indicates failed callback status */ +#define OSSA_FAILURE_PORT_ID_OUT_OF_RANGE 0x05 /**< flag indicates failed callback status */ +#define OSSA_FAILURE_PORT_NOT_VALID_STATE 0x06 /**< flag indicates failed callback status */ +#define OSSA_FAILURE_DEVICE_TYPE_NOT_VALID 0x07 /**< flag indicates failed callback status */ +#define OSSA_ERR_DEVICE_HANDLE_UNAVAILABLE 0x1020 +#define OSSA_ERR_DEVICE_ALREADY_REGISTERED 0x1021 +#define OSSA_ERR_DEVICE_TYPE_NOT_VALID 0x1022 + +#define OSSA_MPI_ERR_DEVICE_ACCEPT_PENDING 0x1027 /**/ + +#define OSSA_ERR_PORT_INVALID 0x1041 +#define OSSA_ERR_PORT_STATE_NOT_VALID 0x1042 + +#define OSSA_ERR_PORT_SMP_PHY_WIDTH_EXCEED 0x1045 + +#define OSSA_ERR_PHY_ID_INVALID 0x1061 +#define OSSA_ERR_PHY_ID_ALREADY_REGISTERED 0x1062 + + + +/* ossaDeregisterDeviceCB() */ +#define OSSA_INVALID_HANDLE 0x02 /**< flag indicates failed callback status */ +#define OSSA_ERR_DEVICE_HANDLE_INVALID 0x1023 /* MPI_ERR_DEVICE_HANDLE_INVALID The device handle associated with DEVICE_ID does not exist. */ +#define OSSA_ERR_DEVICE_BUSY 0x1024 /* MPI_ERR_DEVICE_BUSY Device has outstanding I/Os. */ + + +#define OSSA_RC_ACCEPT 0x00 /**< flag indicates the result of the callback function */ +#define OSSA_RC_REJECT 0x01 /**< flag indicates the result of the callback function */ + +/* ossaSetDeviceStateCB() */ +#define OSSA_INVALID_STATE 0x0001 +#define OSSA_ERR_DEVICE_NEW_STATE_INVALID 0x1025 +#define OSSA_ERR_DEVICE_STATE_CHANGE_NOT_ALLOWED 0x1026 +#define OSSA_ERR_DEVICE_STATE_INVALID 0x0049 + +/* status of ossaSASDiagExecuteCB() */ +#define OSSA_DIAG_SUCCESS 0x00 /* Successful SAS diagnostic command. */ +#define OSSA_DIAG_INVALID_COMMAND 0x01 /* Invalid SAS diagnostic command. */ +#define OSSA_REGISTER_ACCESS_TIMEOUT 0x02 /* Register access has been timed-out. This is applicable only to the SPCv controller. */ +#define OSSA_DIAG_FAIL 0x02 /* SAS diagnostic command failed. This is applicable only to the SPC controller. */ +#define OSSA_DIAG_NOT_IN_DIAGNOSTIC_MODE 0x03 /* Attempted to execute SAS diagnostic command but PHY is not in diagnostic mode */ +#define OSSA_DIAG_INVALID_PHY 0x04 /* Attempted to execute SAS diagnostic command on an invalid/out-of-range PHY. */ +#define OSSA_MEMORY_ALLOC_FAILURE 0x05 /* Memory allocation failed in diagnostic. This is applicable only to the SPCv controller. */ + + +/* status of ossaSASDiagStartEndCB() */ +#define OSSA_DIAG_SE_SUCCESS 0x00 +#define OSSA_DIAG_SE_INVALID_PHY_ID 0x01 +#define OSSA_DIAG_PHY_NOT_DISABLED 0x02 +#define OSSA_DIAG_OTHER_FAILURE 0x03 /* SPC */ +#define OSSA_DIAG_OPCODE_INVALID 0x03 + +/* status of ossaPortControlCB() */ +#define OSSA_PORT_CONTROL_FAILURE 0x03 + +#define OSSA_MPI_ERR_PORT_IO_RESOURCE_UNAVAILABLE 0x1004 +#define OSSA_MPI_ERR_PORT_INVALID 0x1041 /**/ +#define OSSA_MPI_ERR_PORT_OP_NOT_IN_USE 0x1043 /**/ +#define OSSA_MPI_ERR_PORT_OP_NOT_SUPPORTED 0x1044 /**/ +#define OSSA_MPI_ERR_PORT_SMP_WIDTH_EXCEEDED 0x1045 /**/ +#define OSSA_MPI_ERR_PORT_NOT_IN_CORRECT_STATE 0x1047 /**/ + +/*regDumpNum of agsaRegDumpInfo_t */ +#define GET_GSM_SM_INFO 0x02 +#define GET_IOST_RB_INFO 0x03 + +/************************************************************************************ + * HW Events + ************************************************************************************/ +#define OSSA_HW_EVENT_RESET_START 0x01 /**< flag indicates reset started event */ +#define OSSA_HW_EVENT_RESET_COMPLETE 0x02 /**< flag indicates chip reset completed event */ +#define OSSA_HW_EVENT_PHY_STOP_STATUS 0x03 /**< flag indicates phy stop event status */ +#define OSSA_HW_EVENT_SAS_PHY_UP 0x04 /**< flag indicates SAS link up event */ +#define OSSA_HW_EVENT_SATA_PHY_UP 0x05 /**< flag indicates SATA link up event */ +#define OSSA_HW_EVENT_SATA_SPINUP_HOLD 0x06 /**< flag indicates SATA spinup hold event */ +#define OSSA_HW_EVENT_PHY_DOWN 0x07 /**< flag indicates link down event */ + +#define OSSA_HW_EVENT_BROADCAST_CHANGE 0x09 /**< flag indicates broadcast change event */ +/* not used spcv 0x0A*/ +#define OSSA_HW_EVENT_PHY_ERROR 0x0A /**< flag indicates link error event */ +#define OSSA_HW_EVENT_BROADCAST_SES 0x0B /**< flag indicates broadcast change (SES) event */ +#define OSSA_HW_EVENT_PHY_ERR_INBOUND_CRC 0x0C +#define OSSA_HW_EVENT_HARD_RESET_RECEIVED 0x0D /**< flag indicates hardware reset received event */ +/* not used spcv 0x0E*/ +#define OSSA_HW_EVENT_MALFUNCTION 0x0E /**< flag indicates unrecoverable Error */ +#define OSSA_HW_EVENT_ID_FRAME_TIMEOUT 0x0F /**< flag indicates ID Frame Timeout event */ +#define OSSA_HW_EVENT_BROADCAST_EXP 0x10 /**< flag indicates broadcast (EXPANDER) event */ +/* not used spcv 0x11*/ +#define OSSA_HW_EVENT_PHY_START_STATUS 0x11 /**< flag indicates phy start event status */ +#define OSSA_HW_EVENT_PHY_ERR_INVALID_DWORD 0x12 /**< flag indicates Link error invalid DWORD */ +#define OSSA_HW_EVENT_PHY_ERR_DISPARITY_ERROR 0x13 /**< flag indicates Phy error disparity */ +#define OSSA_HW_EVENT_PHY_ERR_CODE_VIOLATION 0x14 /**< flag indicates Phy error code violation */ +#define OSSA_HW_EVENT_PHY_ERR_LOSS_OF_DWORD_SYNCH 0x15 /**< flag indicates Link error loss of DWORD synch */ +#define OSSA_HW_EVENT_PHY_ERR_PHY_RESET_FAILED 0x16 /**< flag indicates Link error phy reset failed */ +#define OSSA_HW_EVENT_PORT_RECOVERY_TIMER_TMO 0x17 /**< flag indicates Port Recovery timeout */ +#define OSSA_HW_EVENT_PORT_RECOVER 0x18 /**< flag indicates Port Recovery */ +#define OSSA_HW_EVENT_PORT_RESET_TIMER_TMO 0x19 /**< flag indicates Port Reset Timer out */ +#define OSSA_HW_EVENT_PORT_RESET_COMPLETE 0x20 /**< flag indicates Port Reset Complete */ +#define OSSA_HW_EVENT_BROADCAST_ASYNCH_EVENT 0x21 /**< flag indicates Broadcast Asynch Event */ +#define OSSA_HW_EVENT_IT_NEXUS_LOSS 0x22 /**< Custom: H/W event for IT Nexus Loss */ + +#define OSSA_HW_EVENT_OPEN_RETRY_BACKOFF_THR_ADJUSTED 0x25 + +#define OSSA_HW_EVENT_ENCRYPTION 0x83 /**< TSDK internal flag indicating that an encryption event occurred */ +#define OSSA_HW_EVENT_MODE 0x84 /**< TSDK internal flag indicating that a controller mode page operation completed */ +#define OSSA_HW_EVENT_SECURITY_MODE 0x85 /**< TSDK internal flag indicating that saEncryptSetMode() completed */ + + +/* port state */ +#define OSSA_PORT_NOT_ESTABLISHED 0x00 /**< flag indicates port is not established */ +#define OSSA_PORT_VALID 0x01 /**< flag indicates port valid */ +#define OSSA_PORT_LOSTCOMM 0x02 /**< flag indicates port lost communication */ +#define OSSA_PORT_IN_RESET 0x04 /**< flag indicates port in reset state */ +#define OSSA_PORT_3RDPARTY_RESET 0x07 /**< flag indicates port in 3rd party reset state */ +#define OSSA_PORT_INVALID 0x08 /**< flag indicates port invalid */ + +/* status for agsaHWEventMode_t */ +#define OSSA_CTL_SUCCESS 0x0000 +#define OSSA_CTL_INVALID_CONFIG_PAGE 0x1001 +#define OSSA_CTL_INVALID_PARAM_IN_CONFIG_PAGE 0x1002 +#define OSSA_CTL_INVALID_ENCRYPTION_SECURITY_MODE 0x1003 +#define OSSA_CTL_RESOURCE_NOT_AVAILABLE 0x1004 +#define OSSA_CTL_CONTROLLER_NOT_IDLE 0x1005 +// #define OSSA_CTL_NVM_MEMORY_ACCESS_ERR 0x100B +#define OSSA_CTL_OPERATOR_AUTHENTICATION_FAILURE 0x100XX + + + +/************************************************************************************ + * General Events value + ************************************************************************************/ +#define OSSA_INBOUND_V_BIT_NOT_SET 0x01 +#define OSSA_INBOUND_OPC_NOT_SUPPORTED 0x02 +#define OSSA_INBOUND_IOMB_INVALID_OBID 0x03 + +/************************************************************************************ + * FW Flash Update status values + ************************************************************************************/ +#define OSSA_FLASH_UPDATE_COMPLETE_PENDING_REBOOT 0x00 /**< flag indicates fw flash update completed */ +#define OSSA_FLASH_UPDATE_IN_PROGRESS 0x01 /**< flag indicates fw flash update in progress */ +#define OSSA_FLASH_UPDATE_HDR_ERR 0x02 /**< flag indicates fw flash header error */ +#define OSSA_FLASH_UPDATE_OFFSET_ERR 0x03 /**< flag indicates fw flash offset error */ +#define OSSA_FLASH_UPDATE_CRC_ERR 0x04 /**< flag indicates fw flash CRC error */ +#define OSSA_FLASH_UPDATE_LENGTH_ERR 0x05 /**< flag indicates fw flash length error */ +#define OSSA_FLASH_UPDATE_HW_ERR 0x06 /**< flag indicates fw flash HW error */ +#define OSSA_FLASH_UPDATE_HMAC_ERR 0x0E /**< flag indicates fw flash Firmware image HMAC authentication failure.*/ + +#define OSSA_FLASH_UPDATE_DNLD_NOT_SUPPORTED 0x10 /**< flag indicates fw flash down load not supported */ +#define OSSA_FLASH_UPDATE_DISABLED 0x11 /**< flag indicates fw flash Update disabled */ +#define OSSA_FLASH_FWDNLD_DEVICE_UNSUPPORT 0x12 /**< flag indicates fw flash Update disabled */ + +/************************************************************************************ +* Discovery status values +************************************************************************************/ +#define OSSA_DISCOVER_STARTED 0x00 /**< flag indicates discover started */ +#define OSSA_DISCOVER_FOUND_DEVICE 0x01 /**< flag indicates discovery found a new device */ +#define OSSA_DISCOVER_REMOVED_DEVICE 0x02 /**< flag indicates discovery found a device removed */ +#define OSSA_DISCOVER_COMPLETE 0x03 /**< flag indicates discover completed */ +#define OSSA_DISCOVER_ABORT 0x04 /**< flag indicates discover error12 */ +#define OSSA_DISCOVER_ABORT_ERROR_1 0x05 /**< flag indicates discover error1 */ +#define OSSA_DISCOVER_ABORT_ERROR_2 0x06 /**< flag indicates discover error2 */ +#define OSSA_DISCOVER_ABORT_ERROR_3 0x07 /**< flag indicates discover error3 */ +#define OSSA_DISCOVER_ABORT_ERROR_4 0x08 /**< flag indicates discover error4 */ +#define OSSA_DISCOVER_ABORT_ERROR_5 0x09 /**< flag indicates discover error5 */ +#define OSSA_DISCOVER_ABORT_ERROR_6 0x0A /**< flag indicates discover error6 */ +#define OSSA_DISCOVER_ABORT_ERROR_7 0x0B /**< flag indicates discover error7 */ +#define OSSA_DISCOVER_ABORT_ERROR_8 0x0C /**< flag indicates discover error8 */ +#define OSSA_DISCOVER_ABORT_ERROR_9 0x0D /**< flag indicates discover error9 */ + +/*********************************************************************************** + * Log Debug Levels + ***********************************************************************************/ +#define OSSA_DEBUG_LEVEL_0 0x00 /**< debug level 0 */ +#define OSSA_DEBUG_LEVEL_1 0x01 /**< debug level 1 */ +#define OSSA_DEBUG_LEVEL_2 0x02 /**< debug level 2 */ +#define OSSA_DEBUG_LEVEL_3 0x03 /**< debug level 3 */ +#define OSSA_DEBUG_LEVEL_4 0x04 /**< debug level 4 */ + +#define OSSA_DEBUG_PRINT_INVALID_NUMBER 0xFFFFFFFF /**< the number won't be printed by OS layer */ + +#define OSSA_FRAME_TYPE_SSP_CMD 0x06 /**< flag indicates received frame is SSP command */ +#define OSSA_FRAME_TYPE_SSP_TASK 0x16 /**< flag indicates received frame is SSP task management */ + +/* Event Source Type of saRegisterEventCallback() */ +#define OSSA_EVENT_SOURCE_DEVICE_HANDLE_ADDED 0x00 +#define OSSA_EVENT_SOURCE_DEVICE_HANDLE_REMOVED 0x01 + +/* Status of Get Device Info CB */ +#define OSSA_DEV_INFO_INVALID_HANDLE 0x01 +#define OSSA_DEV_INFO_NO_EXTENDED_INFO 0x02 +#define OSSA_DEV_INFO_SAS_EXTENDED_INFO 0x03 +#define OSSA_DEV_INFO_SATA_EXTENDED_INFO 0x04 + +/* Diagnostic Command Type */ +#define AGSA_CMD_TYPE_DIAG_OPRN_PERFORM 0x00 +#define AGSA_CMD_TYPE_DIAG_OPRN_STOP 0x01 +#define AGSA_CMD_TYPE_DIAG_THRESHOLD_SPECIFY 0x02 +#define AGSA_CMD_TYPE_DIAG_RECEIVE_ENABLE 0x03 +#define AGSA_CMD_TYPE_DIAG_REPORT_GET 0x04 +#define AGSA_CMD_TYPE_DIAG_ERR_CNT_RESET 0x05 + +/* Command Description for CMD_TYPE DIAG_OPRN_PERFORM, DIAG_OPRN_STOP, THRESHOLD_SPECIFY */ +#define AGSA_CMD_DESC_PRBS 0x00 +#define AGSA_CMD_DESC_CJTPAT 0x01 +#define AGSA_CMD_DESC_USR_PATTERNS 0x02 +#define AGSA_CMD_DESC_PRBS_ERR_INSERT 0x08 +#define AGSA_CMD_DESC_PRBS_INVERT 0x09 +#define AGSA_CMD_DESC_CJTPAT_INVERT 0x0A +#define AGSA_CMD_DESC_CODE_VIOL_INSERT 0x0B +#define AGSA_CMD_DESC_DISP_ERR_INSERT 0x0C +#define AGSA_CMD_DESC_SSPA_PERF_EVENT_1 0x0E +#define AGSA_CMD_DESC_LINE_SIDE_ANA_LPBK 0x10 +#define AGSA_CMD_DESC_LINE_SIDE_DIG_LPBK 0x11 +#define AGSA_CMD_DESC_SYS_SIDE_ANA_LPBK 0x12 + +/* Command Description for CMD_TYPE DIAG_REPORT_GET and ERR_CNT_RESET */ +#define AGSA_CMD_DESC_PRBS_ERR_CNT 0x00 +#define AGSA_CMD_DESC_CODE_VIOL_ERR_CNT 0x01 +#define AGSA_CMD_DESC_DISP_ERR_CNT 0x02 +#define AGSA_CMD_DESC_LOST_DWD_SYNC_CNT 0x05 +#define AGSA_CMD_DESC_INVALID_DWD_CNT 0x06 +#define AGSA_CMD_DESC_CODE_VIOL_ERR_CNT_THHD 0x09 +#define AGSA_CMD_DESC_DISP_ERR_CNT_THHD 0x0A +#define AGSA_CMD_DESC_SSPA_PERF_CNT 0x0B +#define AGSA_CMD_DESC_PHY_RST_CNT 0x0C +#define AGSA_CMD_DESC_SSPA_PERF_1_THRESHOLD 0x0E + +#define AGSA_CMD_DESC_CODE_VIOL_ERR_THHD 0x19 +#define AGSA_CMD_DESC_DISP_ERR_THHD 0x1A +#define AGSA_CMD_DESC_RX_LINK_BANDWIDTH 0x1B +#define AGSA_CMD_DESC_TX_LINK_BANDWIDTH 0x1C +#define AGSA_CMD_DESC_ALL 0x1F + +/* NVMDevice type */ +#define AGSA_NVMD_TWI_DEVICES 0x00 +#define AGSA_NVMD_CONFIG_SEEPROM 0x01 +#define AGSA_NVMD_VPD_FLASH 0x04 +#define AGSA_NVMD_AAP1_REG_FLASH 0x05 +#define AGSA_NVMD_IOP_REG_FLASH 0x06 +#define AGSA_NVMD_EXPANSION_ROM 0x07 +#define AGSA_NVMD_REG_FLASH 0x05 + + +/* GET/SET NVMD Data Response errors */ +#define OSSA_NVMD_SUCCESS 0x0000 +#define OSSA_NVMD_MODE_ERROR 0x0001 +#define OSSA_NVMD_LENGTH_ERROR 0x0002 +#define OSSA_NVMD_TWI_ADDRESS_SIZE_ERROR 0x0005 +#define OSSA_NVMD_TWI_NACK_ERROR 0x2001 +#define OSSA_NVMD_TWI_LOST_ARB_ERROR 0x2002 +#define OSSA_NVMD_TWI_TIMEOUT_ERROR 0x2021 +#define OSSA_NVMD_TWI_BUS_NACK_ERROR 0x2081 +#define OSSA_NVMD_TWI_ARB_FAILED_ERROR 0x2082 +#define OSSA_NVMD_TWI_BUS_TIMEOUT_ERROR 0x20FF +#define OSSA_NVMD_FLASH_PARTITION_NUM_ERROR 0x9001 +#define OSSA_NVMD_FLASH_LENGTH_TOOBIG_ERROR 0x9002 +#define OSSA_NVMD_FLASH_PROGRAM_ERROR 0x9003 +#define OSSA_NVMD_FLASH_DEVICEID_ERROR 0x9004 +#define OSSA_NVMD_FLASH_VENDORID_ERROR 0x9005 +#define OSSA_NVMD_FLASH_ERASE_TIMEOUT_ERROR 0x9006 +#define OSSA_NVMD_FLASH_ERASE_ERROR 0x9007 +#define OSSA_NVMD_FLASH_BUSY_ERROR 0x9008 +#define OSSA_NVMD_FLASH_NOT_SUPPORT_DEVICE_ERROR 0x9009 +#define OSSA_NVMD_FLASH_CFI_INF_ERROR 0x900A +#define OSSA_NVMD_FLASH_MORE_ERASE_BLOCK_ERROR 0x900B +#define OSSA_NVMD_FLASH_READ_ONLY_ERROR 0x900C +#define OSSA_NVMD_FLASH_MAP_TYPE_ERROR 0x900D +#define OSSA_NVMD_FLASH_MAP_DISABLE_ERROR 0x900E + +/************************************************************ +* ossaHwCB Encryption encryptOperation of agsaHWEventEncrypt_t +************************************************************/ +#define OSSA_HW_ENCRYPT_KEK_UPDATE 0x0000 +#define OSSA_HW_ENCRYPT_KEK_UPDATE_AND_STORE 0x0001 +#define OSSA_HW_ENCRYPT_KEK_INVALIDTE 0x0002 +#define OSSA_HW_ENCRYPT_DEK_UPDATE 0x0003 +#define OSSA_HW_ENCRYPT_DEK_INVALIDTE 0x0004 +#define OSSA_HW_ENCRYPT_OPERATOR_MANAGEMENT 0x0005 +#define OSSA_HW_ENCRYPT_TEST_EXECUTE 0x0006 +#define OSSA_HW_ENCRYPT_SET_OPERATOR 0x0007 +#define OSSA_HW_ENCRYPT_GET_OPERATOR 0x0008 + + +/************************************************************ +* ossaHwCB Encryption status of agsaHWEventEncrypt_t +************************************************************/ +/* KEK and DEK managment status from PM */ +#define OSSA_INVALID_ENCRYPTION_SECURITY_MODE 0x1003 +#define OSSA_KEK_MGMT_SUBOP_NOT_SUPPORTED_ 0x2000 /*not in PM 101222*/ +#define OSSA_DEK_MGMT_SUBOP_NOT_SUPPORTED 0x2000 +#define OSSA_MPI_ENC_ERR_ILLEGAL_DEK_PARAM 0x2001 +#define OSSA_MPI_ERR_DEK_MANAGEMENT_DEK_UNWRAP_FAIL 0x2002 +#define OSSA_MPI_ENC_ERR_ILLEGAL_KEK_PARAM 0x2021 +#define OSSA_MPI_ERR_KEK_MANAGEMENT_KEK_UNWRAP_FAIL 0x2022 +#define OSSA_MPI_ERR_KEK_MANAGEMENT_NVRAM_OPERATION_FAIL 0x2023 + +/*encrypt operator management response status */ +#define OSSA_OPR_MGMT_OP_NOT_SUPPORTED 0x2060 +#define OSSA_MPI_ENC_ERR_OPR_PARAM_ILLEGAL 0x2061 +#define OSSA_MPI_ENC_ERR_OPR_ID_NOT_FOUND 0x2062 +#define OSSA_MPI_ENC_ERR_OPR_ROLE_NOT_MATCH 0x2063 +#define OSSA_MPI_ENC_ERR_OPR_MAX_NUM_EXCEEDED 0x2064 + +/*encrypt saSetOperator() response status */ +#define OSSA_MPI_ENC_ERR_CONTROLLER_NOT_IDLE 0x1005 +#define OSSA_MPI_ENC_NVM_MEM_ACCESS_ERR 0x100B + +/* agsaEncryptSMX | agsaEncryptCipherMode == cipherMode for saEncryptSetMode()*/ +/* Make sure all definitions are unique bits */ +#define agsaEncryptSMF 0x00000000 +#define agsaEncryptSMA 0x00000100 +#define agsaEncryptSMB 0x00000200 +#define agsaEncryptReturnSMF (1 << 12) +#define agsaEncryptAuthorize (1 << 13) + +/* +Bits 16-23: Allowable Cipher Mode(ACM) +Bit 16: Enable AES ECB. If set to 1, AES ECB is enable. If set to 0, AES ECB is disabled. +Bit 22: Enable AES XTS. If set to 1, AES XTS is enable. If set to 0, AES XTS is disabled. +*/ +#define agsaEncryptAcmMask 0x00ff0000 +#define agsaEncryptEnableAES_ECB (1 << 16) +#define agsaEncryptEnableAES_XTS (1 << 22) + + + +#define agsaEncryptCipherModeECB 0x00000001 +#define agsaEncryptCipherModeXTS 0x00000002 + + + +#define agsaEncryptStatusNoNVRAM 0x00000001 +#define agsaEncryptStatusNVRAMErr 0x00000002 + +/* + +Bin Hex Sector Total +00000 :0x0 512B 512 +11000 :0x1 520B 520 +00010 :0x2 4K 4096 +00011 :0x3 4K+64B 4160 +00100 :0x4 4K+128B 4224 + +11000 :0x18 512+8B 520 +11001 :0x19 520+8B 528 +11010 :0x1A 4K+8B 4104 +11011 :0x1B 4K+64B+8B 4168 +11100 :0x1C 4K+128B+8B 4232 + +*/ + +#define agsaEncryptSectorSize512 0 +/* define agsaEncryptSectorSize520 1 Not supported */ +#define agsaEncryptSectorSize4096 2 +#define agsaEncryptSectorSize4160 3 +#define agsaEncryptSectorSize4224 4 + +#define agsaEncryptDIFSectorSize520 (agsaEncryptSectorSize512 | 0x18) +#define agsaEncryptDIFSectorSize528 ( 0x19) +#define agsaEncryptDIFSectorSize4104 (agsaEncryptSectorSize4096 | 0x18) +#define agsaEncryptDIFSectorSize4168 (agsaEncryptSectorSize4160 | 0x18) +#define agsaEncryptDIFSectorSize4232 (agsaEncryptSectorSize4224 | 0x18) + + +#define AGSA_ENCRYPT_STORE_NVRAM 1 + +/************************************************************ +* ossaHwCB Mode page event definitions +************************************************************/ +#define agsaModePageGet 1 +#define agsaModePageSet 2 + +/************************************************************ +* saSgpio() SGPIO Function and Register type +************************************************************/ +#define AGSA_READ_SGPIO_REGISTER 0x02 +#define AGSA_WRITE_SGPIO_REGISTER 0x82 + +#define AGSA_SGPIO_CONFIG_REG 0x0 +#define AGSA_SGPIO_DRIVE_BY_DRIVE_RECEIVE_REG 0x1 +#define AGSA_SGPIO_GENERAL_PURPOSE_RECEIVE_REG 0x2 +#define AGSA_SGPIO_DRIVE_BY_DRIVE_TRANSMIT_REG 0x3 +#define AGSA_SGPIO_GENERAL_PURPOSE_TRANSMIT_REG 0x4 + +/************************************************************ +* ossaSGpioCB() Function result +************************************************************/ +#define OSSA_SGPIO_COMMAND_SUCCESS 0x00 +#define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_TYPE 0x01 +#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_TYPE 0x02 +#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_INDEX 0x03 +#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_COUNT 0x04 +#define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_REG_TYPE 0x05 +#define OSSA_SGPIO_CMD_ERROR_WRONG_FUNCTION 0x06 +#define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_TYPE_REG_INDEX 0x19 +#define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_TYPE_REG_CNT 0x81 +#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_TYPE_REG_INDEX 0x1A +#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_TYPE_REG_COUNT 0x82 +#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_INDEX_REG_COUNT 0x83 +#define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_REG_TYPE_REG_INDEX 0x1D +#define OSSA_SGPIO_CMD_ERROR_WRONG_ALL_HEADER_PARAMS 0x9D + +#define OSSA_SGPIO_MAX_READ_DATA_COUNT 0x0D +#define OSSA_SGPIO_MAX_WRITE_DATA_COUNT 0x0C + +/************************************************************ +* ossaGetDFEDataCB() status +************************************************************/ +#define OSSA_DFE_MPI_IO_SUCCESS 0x0000 +#define OSSA_DFE_DATA_OVERFLOW 0x0002 +#define OSSA_DFE_MPI_ERR_RESOURCE_UNAVAILABLE 0x1004 +#define OSSA_DFE_CHANNEL_DOWN 0x100E +#define OSSA_DFE_MEASUREMENT_IN_PROGRESS 0x100F +#define OSSA_DFE_CHANNEL_INVALID 0x1010 +#define OSSA_DFE_DMA_FAILURE 0x1011 + +/************************************************************************************ + * * + * Constants defined for OS Layer ends * + * * + ************************************************************************************/ + +/************************************************************************************ + * * + * Data Structures Defined for LL API start * + * * + ************************************************************************************/ +/** \brief data structure stores OS specific and LL specific context + * + * The agsaContext_t data structure contains two generic pointers, + * also known as handles, which are used to store OS Layer-specific and + * LL Layer-specific contexts. Only the handle specific to a layer can + * be modified by the layer. The other layer's handle must be returned + * unmodified when communicating between the layers. + + * A layer's handle is typically typecast to an instance of a layer-specific + * data structure. The layer can use its handle to point to any data type + * that is to be associated with a function call. A handle provides a way + * to uniquely identify responses when multiple calls to the same function + * are necessary. + * + */ +typedef struct agsaContext_s +{ + void *osData; /**< Pointer-sized value used internally by the OS Layer */ + void *sdkData; /**< Pointer-sized value used internally by the LL Layer */ +} agsaContext_t; + +/** \brief hold points to global data strutures used by the LL and OS Layers + * + * The agsaRoot_t data structure is used to hold pointer-sized values for + * internal use by the LL and OS Layers. It is intended that the + * sdkData element of the agsaRoot_t data structure be used to + * identify an instance of the hardware context. The sdkData + * element is set by the LL Layer in the saHwInitialize() + * function and returned to the OS Layer in the agsaRoot_t data + * structure + */ +typedef agsaContext_t agsaRoot_t; + +/** \brief holds the pointers to the device data structure used by the LL and OS Layers + * + * The agsaDevHandle_t data structure is the device instance handle. + * It holds pointer-sized values used internally by each of the LL and + * OS Layers. It is intended that the agsaDevHandle_t data + * structure be used to identify a specific device instance. A + * device instance is uniquely identified by its device handle. + */ +typedef agsaContext_t agsaDevHandle_t; + +/** \brief holds the pointers to the port data structure used by the LL and + * OS Layers + * + * The agsaPortContext_t data structure is used to describe an instance of + * SAS port or SATA port. It holds pointer-sized values used + * internally by each of the LL and OS Layers. + * + * When connected to other SAS end-devices or expanders, each instance of + * agsaPortContext_t represents a SAS local narrow-port or + * wide-port. + * + * When connected to SATA device, each instance of agsaPortContext_t + * represents a local SATA port. + * + */ +typedef agsaContext_t agsaPortContext_t; + +/** \brief data structure pointer to IO request structure + * + * It is intended that the agsaIORequest_t structure be used to + * uniquely identify each I/O Request for either target or + * initiator. The OS Layer is responsible for allocating and + * managing agsaIORequest_t structures. The LL Layer uses each + * structure only between calls to: saSSPStart() and + * ossaSSPCompleted(), saSATAStart() and ossaSATACompleted(), + * saSMPStart() and ossaSMPCompleted() + * + */ +typedef agsaContext_t agsaIORequest_t; + +/** \brief handle to access frame + * + * This data structure is the handle to access frame + */ +typedef void *agsaFrameHandle_t; + +/** \brief describe a SAS ReCofiguration structure in the SAS/SATA hardware + * + * Describe a SAS ReConfiguration in the SAS/SATA hardware + * + */ +typedef struct agsaSASReconfig_s { + bit32 flags; /* flag to indicate a change to the default parameter + bit31-30:reserved + bit29: a change to the default SAS/SATA ports is requested + bit28: the OPEN REJECT (RETRY) in command phase is requested + bit27: the OPEN REJECT (RETRY) in data phase is requested + bit26: REJECT will be mapped into OPEN REJECT + bit25: delay for SATA Head-of-Line blocking detection timeout + bit24-00:reserved */ + bit16 reserved0; /* reserved */ + bit8 reserved1; /* reserved */ + bit8 maxPorts; /* This field is valid if bit 29 of the flags field is set to 1 */ + bit16 openRejectRetriesCmd; /* This field is valid if bit 28 of the flags field is set to 1 */ + bit16 openRejectRetriesData; /* This field is valid if bit 27 of the flags field is set to 1.*/ + bit16 reserved2; /* reserved */ + bit16 sataHolTmo; /* This field is valid if bit 25 of the flags field is set to 1 */ +} agsaSASReconfig_t; + +/** \brief describe a Phy Analog Setup registers for a Controller in the SAS/SATA hardware + * + * Describe a Phy Analog Setup registers for a controller in the SAS/SATA hardware + * + */ +typedef struct agsaPhyAnalogSetupRegisters_s +{ + bit32 spaRegister0; + bit32 spaRegister1; + bit32 spaRegister2; + bit32 spaRegister3; + bit32 spaRegister4; + bit32 spaRegister5; + bit32 spaRegister6; + bit32 spaRegister7; + bit32 spaRegister8; + bit32 spaRegister9; +} agsaPhyAnalogSetupRegisters_t; + +#define MAX_INDEX 10 + +/** \brief + * + */ +typedef struct agsaPhyAnalogSetupTable_s +{ + agsaPhyAnalogSetupRegisters_t phyAnalogSetupRegisters[MAX_INDEX]; +} agsaPhyAnalogSetupTable_t; + +/** \brief describe a Phy Analog Setting + * + * Describe a Phy Analog Setup registers for a controller in the SAS/SATA hardware + * + */ +typedef struct agsaPhyAnalogSettingsPage_s +{ + bit32 Dword0; + bit32 Dword1; + bit32 Dword2; + bit32 Dword3; + bit32 Dword4; + bit32 Dword5; + bit32 Dword6; + bit32 Dword7; + bit32 Dword8; + bit32 Dword9; +} agsaPhyAnalogSettingsPage_t; + + +/** \brief describe a Open reject retry backoff threshold page + * + * Describe a Open reject retry backoff threshold registers in the SAS/SATA hardware + * + */ +typedef struct agsaSASPhyOpenRejectRetryBackOffThresholdPage_s +{ + bit32 Dword0; + bit32 Dword1; + bit32 Dword2; + bit32 Dword3; +} agsaSASPhyOpenRejectRetryBackOffThresholdPage_t; + +/** \brief describe a Phy Rate Control + * 4.56 agsaPhyRateControlPage_t + * Description + * This profile page is used to read or set several rate control + * parameters. The page code for this profile page is 0x07. This page can + * be READ by issuing saGetPhyProfile(). It can be read anytime and there + * is no need to quiesce the I/O to the controller. + * Related parameters can be modified by issuing saSetPhyProfile() before + * calling saPhyStart() to the PHY. + * Note: This page is applicable only to the SPCv controller. + * Usage + * Initiator and target. + */ +typedef struct agsaPhyRateControlPage_s +{ + bit32 Dword0; + bit32 Dword1; + bit32 Dword2; +} agsaPhyRateControlPage_t; + +/** + * Dword0 Bits 0-11: ALIGN_RATE(ALNR). Align Insertion rate is 2 in every + * ALIGN_RATE+1 DWord. The default value results in the standard compliant + * value of 2/256. This rate applies to out of connection, SMP and SSP + * connections. The default value is 0x0ff. Other bits are reserved. + * Dword1 Bits 0 -11: STP_ALIGN_RATE(STPALNR) Align Insertion rate is 2 in + * every ALIGN_RATE+1 DWords. Default value results in standard compliant + * value of 2/256. This rate applies to out of STP connections. The default + * value is 0x0ff. Other bits are reserved. + * Dword2 Bits 0-7: SSP_FRAME_RATE(SSPFRMR) The number of idle DWords + * between each SSP frame. 0 means no idle cycles. The default value is + * 0x0. Other bits are reserved. +**/ + +/** \brief describe a Register Dump information for a Controller in the SAS/SATA hardware + * + * Describe a register dump information for a controller in the SAS/SATA hardware + * + */ +typedef struct agsaRegDumpInfo_s +{ + bit8 regDumpSrc; + bit8 regDumpNum; + bit8 reserved[2]; + bit32 regDumpOffset; + bit32 directLen; + void *directData; + bit32 indirectAddrUpper32; + bit32 indirectAddrLower32; + bit32 indirectLen; +} agsaRegDumpInfo_t; + +/* +7 : SPC GSM register at [MEMBASE-III SHIFT = 0x00_0000] +8 : SPC GSM register at [MEMBASE-III SHIFT = 0x05_0000] +9 : BDMA GSM register at [MEMBASE-III SHIFT = 0x01_0000] +10: PCIe APP GSM register at [MEMBASE-III SHIFT = 0x01_0000] +11: PCIe PHY GSM register at [MEMBASE-III SHIFT = 0x01_0000] +12: PCIe CORE GSM register at [MEMBASE-III SHIFT = 0x01_0000] +13: OSSP GSM register at [MEMBASE-III SHIFT = 0x02_0000] +14: SSPA GSM register at [MEMBASE-III SHIFT = 0x03_0000] +15: SSPA GSM register at [MEMBASE-III SHIFT = 0x04_0000] +16: HSST GSM register at [MEMBASE-III SHIFT = 0x02_0000] +17: LMS_DSS(A) GSM register at [MEMBASE-III SHIFT = 0x03_0000] +18: SSPL_6G GSM register at [MEMBASE-III SHIFT = 0x03_0000] +19: HSST(A) GSM register at [MEMBASE-III SHIFT = 0x03_0000] +20: LMS_DSS(A) GSM register at [MEMBASE-III SHIFT = 0x04_0000] +21: SSPL_6G GSM register at [MEMBASE-III SHIFT = 0x04_0000] +22: HSST(A) GSM register at [MEMBASE-III SHIFT = 0x04_0000] +23: MBIC IOP GSM register at [MEMBASE-III SHIFT = 0x06_0000] +24: MBIC AAP1 GSM register at [MEMBASE-III SHIFT = 0x07_0000] +25: SPBC GSM register at [MEMBASE-III SHIFT = 0x09_0000] +26: GSM GSM register at [MEMBASE-III SHIFT = 0x70_0000] +*/ + +#define TYPE_GSM_SPACE 1 +#define TYPE_QUEUE 2 +#define TYPE_FATAL 3 +#define TYPE_NON_FATAL 4 +#define TYPE_INBOUND_QUEUE 5 +#define TYPE_OUTBOUND_QUEUE 6 + + +#define BAR_SHIFT_GSM_OFFSET 0x400000 + +#define ONE_MEGABYTE 0x100000 +#define SIXTYFOURKBYTE (1024 * 64) + + + +#define TYPE_INBOUND 1 +#define TYPE_OUTBOUND 2 + +typedef struct +{ + bit32 DataType; + union + { + struct + { + bit32 directLen; + bit32 directOffset; + bit32 readLen; + void *directData; + }gsmBuf; + + struct + { + bit16 queueType; + bit16 queueIndex; + bit32 directLen; + void *directData; + }queueBuf; + + struct + { + bit32 directLen; + bit32 directOffset; + bit32 readLen; + void *directData; + }dataBuf; + } BufferType; +} agsaForensicData_t; + +/** \brief describe a NVMData for a Controller in the SAS/SATA hardware + * + * Describe a NVMData for a controller in the SAS/SATA hardware + * + */ +typedef struct agsaNVMDData_s +{ + bit32 indirectPayload :1; + bit32 reserved :7; + bit32 TWIDeviceAddress :8; + bit32 TWIBusNumber :4; + bit32 TWIDevicePageSize :4; + bit32 TWIDeviceAddressSize :4; + bit32 NVMDevice :4; + bit32 directLen :8; + bit32 dataOffsetAddress :24; + void *directData; + bit32 indirectAddrUpper32; + bit32 indirectAddrLower32; + bit32 indirectLen; + bit32 signature; +} agsaNVMDData_t; + + +/* status of ossaPCIeDiagExecuteCB() is shared with ossaSASDiagExecuteCB() */ +#define OSSA_PCIE_DIAG_SUCCESS 0x0000 +#define OSSA_PCIE_DIAG_INVALID_COMMAND 0x0001 +#define OSSA_PCIE_DIAG_INTERNAL_FAILURE 0x0002 +#define OSSA_PCIE_DIAG_INVALID_CMD_TYPE 0x1006 +#define OSSA_PCIE_DIAG_INVALID_CMD_DESC 0x1007 +#define OSSA_PCIE_DIAG_INVALID_PCIE_ADDR 0x1008 +#define OSSA_PCIE_DIAG_INVALID_BLOCK_SIZE 0x1009 +#define OSSA_PCIE_DIAG_LENGTH_NOT_BLOCK_SIZE_ALIGNED 0x100A +#define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_MISMATCH 0x3000 +#define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH 0x3001 +#define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH 0x3002 +#define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_CRC_MISMATCH 0x3003 +#define OSSA_PCIE_DIAG_MPI_ERR_INVALID_LENGTH 0x0042 +#define OSSA_PCIE_DIAG_MPI_ERR_IO_RESOURCE_UNAVAILABLE 0x1004 +#define OSSA_PCIE_DIAG_MPI_ERR_CONTROLLER_NOT_IDLE 0x1005 + + +typedef struct agsaPCIeDiagExecute_s +{ + bit32 command; + bit32 flags; + bit16 initialIOSeed; + bit16 reserved; + bit32 rdAddrLower; + bit32 rdAddrUpper; + bit32 wrAddrLower; + bit32 wrAddrUpper; + bit32 len; + bit32 pattern; + bit8 udtArray[6]; + bit8 udrtArray[6]; +} agsaPCIeDiagExecute_t; + + +/** \brief agsaPCIeDiagResponse_t + * + * status of ossaPCIeDiagExecuteCB() + * The agsaPCIeDiagResponse_t structure is a parameter passed to + * ossaPCIeDiagExecuteCB() + * to contain a PCIe Diagnostic command response. + */ + +typedef struct agsaPCIeDiagResponse_s { + bit32 ERR_BLKH; + bit32 ERR_BLKL; + bit32 DWord8; + bit32 DWord9; + bit32 DWord10; + bit32 DWord11; + bit32 DIF_ERR; +} agsaPCIeDiagResponse_t; + + +/** \brief describe a fatal error information for a Controller in the SAS/SATA hardware + * + * Describe a fatal error information for a controller in the SAS/SATA hardware + * + */ +typedef struct agsaFatalErrorInfo_s +{ + bit32 errorInfo0; + bit32 errorInfo1; + bit32 errorInfo2; + bit32 errorInfo3; + bit32 regDumpBusBaseNum0; + bit32 regDumpOffset0; + bit32 regDumpLen0; + bit32 regDumpBusBaseNum1; + bit32 regDumpOffset1; + bit32 regDumpLen1; +} agsaFatalErrorInfo_t; + +/** \brief describe a information for a Event in the SAS/SATA hardware + * + * Describe a general information for a Event in the SAS/SATA hardware + * + */ +typedef struct agsaEventSource_s +{ + agsaPortContext_t *agPortContext; + bit32 event; + bit32 param; +} agsaEventSource_t; + +/** \brief describe a information for a Controller in the SAS/SATA hardware + * + * Describe a general information for a controller in the SAS/SATA hardware + * + */ +typedef struct agsaControllerInfo_s +{ + bit32 signature; /* coherent controller information */ + bit32 fwInterfaceRev; /* host and controller interface version */ + bit32 hwRevision; /* controller HW Revision number */ + bit32 fwRevision; /* controller FW Revision number */ + bit32 ilaRevision; /* controller ILA Revision number */ + bit32 maxPendingIO; /* maximum number of outstanding I/Os supported */ + bit32 maxDevices; /* Maximum Device Supported by controller */ + bit32 maxSgElements; /* maximum number of SG elements supported */ + bit32 queueSupport; /* maximum number of IQ and OQ supported + bit31-19 reserved + bit18 interrupt coalescing + bit17 reserved + bit16 high priority IQ supported + bit15-08 maximum number of OQ + bit07-00 maximum number of IQ */ + bit8 phyCount; /* number of phy available in the controller */ + bit8 controllerSetting;/* Controller setting + bit07-04 reserved + bit03-00 HDA setting */ + bit8 PCILinkRate; /* PCI generation 1/2/3 2.5g/5g/8g */ + bit8 PCIWidth; /* PCI number of lanes */ + bit32 sasSpecsSupport; /* the supported SAS spec. */ + bit32 sdkInterfaceRev; /* sdk interface reversion */ + bit32 sdkRevision; /* sdk reversion */ +} agsaControllerInfo_t; + +/** \brief describe a status for a Controller in the SAS/SATA hardware + * + * Describe a general status for a controller in the SAS/SATA hardware + * + */ +typedef struct agsaControllerStatus_s +{ + agsaFatalErrorInfo_t fatalErrorInfo; /* fatal error information */ + bit32 interfaceState; /* host and controller interface state + bit02-00 state of host and controller + bit16-03 reserved + bit31-16 detail of error based on error state */ + bit32 iqFreezeState0; /* freeze state of 1st set of IQ */ + bit32 iqFreezeState1; /* freeze state of 2nd set of IQ */ + bit32 tickCount0; /* tick count in second for internal CPU-0 */ + bit32 tickCount1; /* tick count in second for internal CPU-1 */ + bit32 tickCount2; /* tick count in second for internal CPU-2 */ + bit32 phyStatus[8]; /* status of phy 0 to phy 15 */ + bit32 recoverableErrorInfo[8]; /* controller specific recoverable error information */ + bit32 bootStatus; + bit16 bootComponentState[8]; + +} agsaControllerStatus_t; + +/** \brief describe a GPIO Event Setup Infomation in the SAS/SATA hardware + * + * Describe a configuration for a GPIO Event Setup Infomation in the SAS/SATA hardware + * + */ +typedef struct agsaGpioEventSetupInfo_s +{ + bit32 gpioPinMask; + bit32 gpioEventLevel; + bit32 gpioEventRisingEdge; + bit32 gpioEventFallingEdge; +} agsaGpioEventSetupInfo_t; + +/** \brief describe a GPIO Pin Setup Infomation in the SAS/SATA hardware + * + * Describe a configuration for a GPIO Pin Setup Infomation in the SAS/SATA hardware + * + */ +typedef struct agsaGpioPinSetupInfo_t +{ + bit32 gpioPinMask; + bit32 gpioInputEnabled; + bit32 gpioTypePart1; + bit32 gpioTypePart2; +} agsaGpioPinSetupInfo_t; + +/** \brief describe a serial GPIO operation in the SAS/SATA hardware + * + * Describe a configuration for a GPIO write Setup Infomation in the SAS/SATA hardware + * + */ +typedef struct agsaGpioWriteSetupInfo_s +{ + bit32 gpioWritemask; + bit32 gpioWriteVal; +}agsaGpioWriteSetupInfo_t; + +/** \brief describe a GPIO Read Infomation in the SAS/SATA hardware + * + * Describe a configuration for a GPIO read Infomation in the SAS/SATA hardware + * + */ +typedef struct agsaGpioReadInfo_s +{ + bit32 gpioReadValue; + bit32 gpioInputEnabled; /* GPIOIE */ + bit32 gpioEventLevelChangePart1; /* GPIEVCHANGE (pins 11-0) */ + bit32 gpioEventLevelChangePart2; /* GPIEVCHANGE (pins 23-20) */ + bit32 gpioEventRisingEdgePart1; /* GPIEVRISE (pins 11-0) */ + bit32 gpioEventRisingEdgePart2; /* GPIEVRISE (pins 23-20) */ + bit32 gpioEventFallingEdgePart1; /* GPIEVALL (pins 11-0) */ + bit32 gpioEventFallingEdgePart2; /* GPIEVALL (pins 23-20) */ +}agsaGpioReadInfo_t; + +/** \brief describe a serial GPIO request and response in the SAS/SATA hardware + * + * Describe the fields required for serial GPIO request and response in the SAS/SATA hardware + * + */ +typedef struct agsaSGpioReqResponse_s +{ + bit8 smpFrameType; /* 0x40 for request, 0x41 for response*/ + bit8 function; /* 0x02 for read, 0x82 for write */ + bit8 registerType; /* used only in request */ + bit8 registerIndex; /* used only in request */ + bit8 registerCount; /* used only in request */ + bit8 functionResult; /* used only in response */ + bit32 readWriteData[OSSA_SGPIO_MAX_READ_DATA_COUNT]; /* write data for request; read data for response */ +} agsaSGpioReqResponse_t; + + +/** \brief describe a serial GPIO operation response in the SAS/SATA hardware + * + * Describe the fields required for serial GPIO operations response in the SAS/SATA hardware + * + */ +typedef struct agsaSGpioCfg0 +{ + bit8 reserved1; + bit8 version:4; + bit8 reserved2:4; + bit8 gpRegisterCount:4; + bit8 cfgRegisterCount:3; + bit8 gpioEnable:1; + bit8 supportedDriveCount; +} agsaSGpioCfg0_t; + +/** \brief SGPIO configuration register 1 + * + * These fields constitute SGPIO configuration register 1, as defined by SFF-8485 spec + * + */ +typedef struct agsaSGpioCfg1{ + bit8 reserved; + bit8 blinkGenA:4; + bit8 blinkGenB:4; + bit8 maxActOn:4; + bit8 forceActOff:4; + bit8 stretchActOn:4; + bit8 stretchActOff:4; +} agsaSGpioCfg1_t; + +/** \brief describe a configuration for a PHY in the SAS/SATA hardware + * + * Describe a configuration for a PHY in the SAS/SATA hardware + * + */ +typedef struct agsaPhyConfig_s +{ + bit32 phyProperties; + /**< b31-b8 reserved */ + /**< b16-b19 SSC Disable */ + /**< b15-b8 phy analog setup index */ + /**< b7 phy analog setup enable */ + /**< b6 Control spin up hold */ + /**< b5-b4 SAS/SATA mode, bit4 - SAS, bit5 - SATA, 11b - Auto mode */ + /**< b3-b0 Max. Link Rate, bit0 - 1.5Gb/s, bit1 - 3.0Gb/s, + bit2 - 6.0Gb/s, bit3 - reserved */ +} agsaPhyConfig_t; + + +/** \brief Structure is used as a parameter passed in saLocalPhyControlCB() to describe the error counter + * + * Description + * This profile page is used to read or set the SNW-3 PHY capabilities of a + * SAS PHY. This page can be read by calling saGetPhyProfile(). It can be + * read anytime and there is no need to quiesce he I/O to the controller. + * The format of the 32-bit SNW3 is the same as defined in the SAS 2 + * specification. + * Local SNW3 can be modified by calling saSetPhyProfile() before + * saPhyStart() to the PHY. REQUESTED LOGICAL LINK RATE is reserved. + * The SPCv will calculate the PARITY field. + + * Note: This page is applicable only to the SPCv controller. + * Usage + * Initiator and target. + */ + +typedef struct agsaPhySNW3Page_s +{ + bit32 LSNW3; + bit32 RSNW3; +} agsaPhySNW3Page_t; + +/** \brief structure describe error counters of a PHY in the SAS/SATA + * + * Structure is used as a parameter passed in saLocalPhyControlCB() + * to describe the error counter + * + */ +typedef struct agsaPhyErrCounters_s +{ + bit32 invalidDword; /* Number of invalid dwords that have been + received outside of phy reset sequences.*/ + bit32 runningDisparityError; /* Number of dwords containing running disparity + errors that have been received outside of phy + reset sequences.*/ + bit32 lossOfDwordSynch; /* Number of times the phy has restarted the link + reset sequence because it lost dword synchronization.*/ + bit32 phyResetProblem; /* Number of times the phy did not obtain dword + synchronization during the final SAS speed + negotiation window.*/ + bit32 elasticityBufferOverflow; /* Number of times the phys receive elasticity + buffer has overflowed.*/ + bit32 receivedErrorPrimitive; /* Number of times the phy received an ERROR primitive */ + bit32 inboundCRCError; /* Number of inbound CRC Error */ + bit32 codeViolation; /* Number of code violation */ +} agsaPhyErrCounters_t; + + +/** \brief + * used in saGetPhyProfile + */ +typedef struct agsaPhyErrCountersPage_s +{ + bit32 invalidDword; + bit32 runningDisparityError; + bit32 codeViolation; + bit32 lossOfDwordSynch; + bit32 phyResetProblem; + bit32 inboundCRCError; +} agsaPhyErrCountersPage_t; + +/** \brief structure describes bandwidth counters of a PHY in the SAS/SATA + * + * Structure is used as a parameter passed in saGetPhyProfile() + * to describe the error counter + * + */ + +typedef struct agsaPhyBWCountersPage_s +{ + bit32 TXBWCounter; + bit32 RXBWCounter; +} agsaPhyBWCountersPage_t; + + + +/** \brief structure describe hardware configuration + * + * Structure is used as a parameter passed in saInitialize() to describe the + * configuration used during hardware initialization + * + */ +typedef struct agsaHwConfig_s +{ + bit32 phyCount; /**< Number of PHYs that are to be configured + and initialized. */ + bit32 hwInterruptCoalescingTimer; /**< Host Interrupt CoalescingTimer */ + bit32 hwInterruptCoalescingControl; /**< Host Interrupt CoalescingControl */ + bit32 intReassertionOption; /**< Interrupt Ressertion Option */ + bit32 hwOption; /** PCAD64 on 64 bit addressing */ + + agsaPhyAnalogSetupTable_t phyAnalogConfig; /**< Phy Analog Setting Table */ +} agsaHwConfig_t; + +/** \brief structure describe software configuration + * + * Structure is used as a parameter passed in saInitialize() to describe the + * configuration used during software initialization + * + */ +typedef struct agsaSwConfig_s +{ + bit32 maxActiveIOs; /**< Maximum active I/O requests supported */ + bit32 numDevHandles; /**< Number of SAS/SATA device handles allocated + in the pool */ + bit32 smpReqTimeout; /**< SMP request time out in millisecond */ + bit32 numberOfEventRegClients; /**< Maximum number of OS Layer clients for the event + registration defined by saRegisterEventCallback() */ + bit32 sizefEventLog1; /**< Size of Event Log 1 */ + bit32 sizefEventLog2; /**< Size of Event Log 2 */ + bit32 eventLog1Option; /**< Option of Event Log 1 */ + bit32 eventLog2Option; /**< Option of Event Log 2 */ + + bit32 fatalErrorInterruptEnable:1; /**< 0 Fatal Error Iterrupt Enable */ + bit32 sgpioSupportEnable:1; /**< 1 SGPIO Support Enable */ + bit32 fatalErrorInterruptVector:8; /**< 2-9 Fatal Error Interrupt Vector */ + bit32 max_MSI_InterruptVectors:8; /**< 10-18 Maximum MSI Interrupt Vectors */ + bit32 max_MSIX_InterruptVectors:8; /**< 18-25 Maximum MSIX Interrupt Vectors */ + bit32 legacyInt_X:1; /**< 26 Support Legacy Interrupt */ + bit32 hostDirectAccessSupport:1; /**< 27 Support HDA mode */ + bit32 hostDirectAccessMode:2; /**< 28-29 HDA mode: 00b - HDA SoftReset, 01b - HDA Normal */ + bit32 enableDIF:1; /**< 30 */ + bit32 enableEncryption:1; /**< 31 */ +#ifdef SA_CONFIG_MDFD_REGISTRY + bit32 disableMDF; /*disable MDF*/ +#endif + bit32 param1; /**< parameter1 */ + bit32 param2; /**< parameter2 */ + void *param3; /**< parameter3 */ + void *param4; /**< paramater4 */ + bit32 stallUsec; + bit32 FWConfig; + bit32 PortRecoveryResetTimer; + void *mpiContextTable; /** Pointer to a table that contains agsaMPIContext_t + entries. This table is used to fill in MPI table + fields. Values in this table are written to MPI table last. + Any previous values in MPI table are overwritten by values + in this table. */ + + bit32 mpiContextTablelen; /** Number of agsaMPIContext_t entries in mpiContextTable */ + +#if defined(SALLSDK_DEBUG) + bit32 sallDebugLevel; /**< Low Layer debug level */ +#endif + +#ifdef SA_ENABLE_PCI_TRIGGER + bit32 PCI_trigger; +#endif /* SA_ENABLE_PCI_TRIGGER */ + +#ifdef SA_ENABLE_TRACE_FUNCTIONS + bit32 TraceDestination; + bit32 TraceBufferSize; + bit32 TraceMask; +#endif /* SA_ENABLE_TRACE_FUNCTIONS */ +} agsaSwConfig_t; + + +typedef struct agsaQueueInbound_s +{ + bit32 elementCount:16; /* Maximum number of elements in the queue (queue depth). + A value of zero indicates that the host disabled this queue.*/ + bit32 elementSize:16; /* Size of each element in the queue in bytes.*/ + bit32 priority:2; /* Queue priority: + 00: normal priority + 01: high priority + 10: reserved + 11: reserved */ + bit32 reserved:30; +} agsaQueueInbound_t; + +typedef struct agsaQueueOutbound_s +{ + bit32 elementCount:16; /* Maximum number of elements in the queue (queue depth). + A value of zero indicates that the host disabled + this queue.*/ + bit32 elementSize:16; /* Size of each element in the queue in bytes.*/ + bit32 interruptDelay:16; /* Time, in usec, to delay interrupts to the host. + Zero means not to delay based on time. An + interrupt is passed to the host when either of + the interruptDelay or interruptCount parameters + is satisfied. Default value is 0.*/ + bit32 interruptCount:16; /* Number of interrupts required before passing to + the host. Zero means not to coalesce based on count. */ + bit32 interruptVectorIndex:8; /* MSI/MSI-X interrupt vector index. For MSI, when + Multiple Messages is enabled, this field is the + index to the MSI vectors derived from a single + Message Address and multiple Message Data. + For MSI-X, this field is the index to the + MSI-X Table Structure. */ + bit32 interruptEnable:1; /* 0b: No interrupt to host (host polling) + 1b: Interrupt enabled */ + bit32 reserved:23; + +} agsaQueueOutbound_t; + +typedef struct agsaPhyCalibrationTbl_s +{ + bit32 txPortConfig1; /* transmitter per port configuration 1 SAS_SATA G1 */ + bit32 txPortConfig2; /* transmitter per port configuration 2 SAS_SATA G1*/ + bit32 txPortConfig3; /* transmitter per port configuration 3 SAS_SATA G1*/ + bit32 txConfig1; /* transmitter configuration 1 */ + bit32 rvPortConfig1; /* reveiver per port configuration 1 SAS_SATA G1G2 */ + bit32 rvPortConfig2; /* reveiver per port configuration 2 SAS_SATA G3 */ + bit32 rvConfig1; /* reveiver per configuration 1 */ + bit32 rvConfig2; /* reveiver per configuration 2 */ + bit32 reserved[2]; /* reserved */ +} agsaPhyCalibrationTbl_t; + +typedef struct agsaQueueConfig_s +{ + bit16 numInboundQueues; + bit16 numOutboundQueues; + bit8 sasHwEventQueue[AGSA_MAX_VALID_PHYS]; + bit8 sataNCQErrorEventQueue[AGSA_MAX_VALID_PHYS]; + bit8 tgtITNexusEventQueue[AGSA_MAX_VALID_PHYS]; + bit8 tgtSSPEventQueue[AGSA_MAX_VALID_PHYS]; + bit8 tgtSMPEventQueue[AGSA_MAX_VALID_PHYS]; + bit8 iqNormalPriorityProcessingDepth; + bit8 iqHighPriorityProcessingDepth; + bit8 generalEventQueue; + bit8 tgtDeviceRemovedEventQueue; + bit32 queueOption; + agsaQueueInbound_t inboundQueues[AGSA_MAX_INBOUND_Q]; + agsaQueueOutbound_t outboundQueues[AGSA_MAX_OUTBOUND_Q]; +} agsaQueueConfig_t; + +#define OQ_SHARE_PATH_BIT 0x00000001 + +typedef struct agsaFwImg_s +{ + bit8 *aap1Img; /**< AAP1 Image */ + bit32 aap1Len; /**< AAP1 Image Length */ + bit8 *ilaImg; /**< ILA Image */ + bit32 ilaLen; /**< ILA Image Length */ + bit8 *iopImg; /**< IOP Image */ + bit32 iopLen; /**< IOP Image Length */ + bit8 *istrImg; /**< Init String */ + bit32 istrLen; /**< Init String Length */ +} agsaFwImg_t; + +/** \brief generic memory descriptor + * + * a generic memory descriptor used for describing a memory requirement in a structure + * + */ +typedef struct agsaMem_s +{ + void *virtPtr; /**< Virtual pointer to the memory chunk */ + void *osHandle; /**< Handle used for OS to free memory */ + bit32 phyAddrUpper; /**< Upper 32 bits of physical address */ + bit32 phyAddrLower; /**< Lower 32 bits of physical address */ + bit32 totalLength; /**< Total length in bytes allocated */ + bit32 numElements; /**< Number of elements */ + bit32 singleElementLength; /**< Size in bytes of an element */ + bit32 alignment; /**< Alignment in bytes needed. A value of one indicates + no specific alignment requirement */ + bit32 type; /**< DMA or Cache */ + bit32 reserved; /**< reserved */ +} agsaMem_t; + +/** \brief specify the controller Event Log for the SAS/SATA LL Layer + * + * data structure used in the saGetControllerEventLogInfo() function calls + * + */ +typedef struct agsaControllerEventLog_s +{ + agsaMem_t eventLog1; + agsaMem_t eventLog2; + bit32 eventLog1Option; + bit32 eventLog2Option; +} agsaControllerEventLog_t; + +/* Log Option - bit3-0 */ +#define DISABLE_LOGGING 0x0 +#define CRITICAL_ERROR 0x1 +#define WARNING 0x2 +#define NOTICE 0x3 +#define INFORMATION 0x4 +#define DEBUGGING 0x5 + +/** \brief specify the SAS Diagnostic Parameters for the SAS/SATA LL Layer + * + * data structure used in the saGetRequirements() and the saInitialize() function calls + * + */ +typedef struct agsaSASDiagExecute_s +{ + bit32 command; + bit32 param0; + bit32 param1; + bit32 param2; + bit32 param3; + bit32 param4; + bit32 param5; +} agsaSASDiagExecute_t; + + +/** \brief for the SAS/SATA LL Layer + * + * This data structure contains the general status of a SAS Phy. + * Section 4.60 + */ +typedef struct agsaSASPhyGeneralStatusPage_s +{ + bit32 Dword0; + bit32 Dword1; +} agsaSASPhyGeneralStatusPage_t; + + +/** \brief specify the memory allocation requirement for the SAS/SATA LL Layer + * + * data structure used in the saGetRequirements() and the saInitialize() function calls + * + */ +typedef struct agsaMemoryRequirement_s +{ + bit32 count; /**< The number of memory chunks used + in the agMemory table */ + agsaMem_t agMemory[AGSA_NUM_MEM_CHUNKS]; /**< The structure that defines the memory + requirement structure */ +} agsaMemoryRequirement_t; + + +/** \brief describe a SAS address and PHY Identifier + * + * This structure is used + * + */ +typedef struct agsaSASAddressID_s +{ + bit8 sasAddressLo[4]; /**< HOST SAS address lower part */ + bit8 sasAddressHi[4]; /**< HOST SAS address higher part */ + bit8 phyIdentifier; /**< PHY IDENTIFIER of the PHY */ +} agsaSASAddressID_t; + +/** \brief data structure provides some information about a SATA device + * + * data structure provides some information about a SATA device discovered + * following the SATA discovery. + * + */ +typedef struct agsaDeviceInfo_s +{ + bit16 smpTimeout; + bit16 it_NexusTimeout; + bit16 firstBurstSize; + bit8 reserved; + /* Not Used */ + bit8 devType_S_Rate; + /* Bit 6-7: reserved + Bit 4-5: Two-bit flag to specify a SSP/SMP, or directly attached SATA or STP device + 00: STP device + 01: SSP or SMP device + 10: Direct SATA device + Bit 0-3: Connection Rate field when opening the device. + Code Description: + 08h: 1.5 Gbps + 09h: 3.0 Gbps + 0ah: 6.0 Gbps + All others Reserved + */ + bit8 sasAddressHi[4]; + bit8 sasAddressLo[4]; + bit32 flag; +/* +flag +Bit 0: Retry flag. + 1b: enable SAS TLR (Transport Layer Retry). + 0b: disable SAS TLR (Transport Layer Retry). + When used during device registration, it is recommended that TLR is + enabled, i.e. set the bit to 1. +Bit 1: Priority setting for AWT (Arbitration Wait Time) for this device. + 0b: Default setting (recommended). Actual AWT value TBD. + 1b: Increase priority. Actual AWT value TBD. +Bit 2-3: Reserved +Bit 4-11: Zero-based PHY identifier. This field is used only if bits 4-5 in devType_S_Rate are set to 10b + which indicates a directly-attached SATA drive. +Bit 12-15: Reserved +Bit 16-19 : Maximum Connection Number. This field specifies the maximum number of connections that + can be established with the device concurrently. This field is set to the lowest port width along the pathway + from the controller to the device. This is applicable only to the SPCv controller. + However, for backward compatibility reasons, if this field is set to zero, it is treated as 1 so that the controller + can establish at least one connection. +Bit 20: Initiator Role + This bit indicates whether the device has SSP initiator role capability. This is applicable only to the SPCv controller. + 0b : The device has no SSP initiator capability. + 1b : The device has SSP initiator capability. +Bit 21: ATAPI Device Flag. (Only applies to the SPCv) Flag to indicate ATAPI protocol support + 0b : Device does not support ATAPI protocol. + 1b : Device supports ATAPI protocol. +Bit 22-31: Reserved +*/ +} agsaDeviceInfo_t; + + +#define DEV_INFO_MASK 0xFF +#define DEV_INFO_MCN_SHIFT 16 +#define DEV_INFO_IR_SHIFT 20 + +#define RETRY_DEVICE_FLAG (1 << SHIFT0) +#define AWT_DEVICE_FLAG (1 << SHIFT1) +#define SSP_DEVICE_FLAG (1 << SHIFT20) +#define ATAPI_DEVICE_FLAG 0x200000 /* bit21 */ +#define XFER_RDY_PRIORTY_DEVICE_FLAG (1 << SHIFT22) + + +#define DEV_LINK_RATE 0x3F + +#define SA_DEVINFO_GET_SAS_ADDRESSLO(devInfo) \ + DMA_BEBIT32_TO_BIT32(*(bit32 *)(devInfo)->sasAddressLo) + +#define SA_DEVINFO_GET_SAS_ADDRESSHI(devInfo) \ + DMA_BEBIT32_TO_BIT32(*(bit32 *)(devInfo)->sasAddressHi) + +#define SA_DEVINFO_GET_DEVICETTYPE(devInfo) \ + (((devInfo)->devType_S_Rate & 0xC0) >> 5) + +#define SA_DEVINFO_PUT_SAS_ADDRESSLO(devInfo, src32) \ + *(bit32 *)((devInfo)->sasAddressLo) = BIT32_TO_DMA_BEBIT32(src32) + +#define SA_DEVINFO_PUT_SAS_ADDRESSHI(devInfo, src32) \ + *(bit32 *)((devInfo)->sasAddressHi) = BIT32_TO_DMA_BEBIT32(src32) + +/** \brief data structure provides some information about a SATA device + * + * data structure provides some information about a SATA device discovered + * following the SATA discovery. + * + */ +typedef struct agsaSATADeviceInfo_s +{ + agsaDeviceInfo_t commonDevInfo; /**< The general/common part of the + SAS/SATA device information */ + bit8 connection; /**< How device is connected: + 0: Direct attached. + 1: Behind Port Multiplier, + portMultiplierField is valid. + 2: STP, stpPhyIdentifier is valid */ + + bit8 portMultiplierField; /**< The first 4 bits indicate that + the Port Multiplier field is defined + by SATA-II. This field is valid only + if the connection field above is + set to 1 */ + + bit8 stpPhyIdentifier; /**< PHY ID of the STP PHY. Valid only if + connection field is set to 2 (STP). */ + + bit8 reserved; + bit8 signature[8]; /**< The signature of SATA in Task + File registers following power up. + Only five bytes are defined by ATA. + The added three bytes are for + alignment purposes */ +} agsaSATADeviceInfo_t; + +/** \brief data structure provides some information about a SAS device + * + * data structure provides some information about a SAS device discovered + * following the SAS discovery + * + */ +typedef struct agsaSASDeviceInfo_s +{ + agsaDeviceInfo_t commonDevInfo; /**< The general/common part of the SAS/SATA + device information */ + bit8 initiator_ssp_stp_smp; /**< SAS initiator capabilities */ + /* b4-7: reserved */ + /* b3: SSP initiator port */ + /* b2: STP initiator port */ + /* b1: SMP initiator port */ + /* b0: reserved */ + bit8 target_ssp_stp_smp; /**< SAS target capabilities */ + /* b4-7: reserved */ + /* b3: SSP target port */ + /* b2: STP target port */ + /* b1: SMP target port */ + /* b0: reserved */ + bit32 numOfPhys; /**< Number of PHYs in the device */ + bit8 phyIdentifier; /**< PHY IDENTIFIER in IDENTIFY address + frame as defined by the SAS + specification. */ +} agsaSASDeviceInfo_t; + +#define SA_SASDEV_SSP_BIT SA_IDFRM_SSP_BIT /* SSP Initiator port */ +#define SA_SASDEV_STP_BIT SA_IDFRM_STP_BIT /* STP Initiator port */ +#define SA_SASDEV_SMP_BIT SA_IDFRM_SMP_BIT /* SMP Initiator port */ +#define SA_SASDEV_SATA_BIT SA_IDFRM_SATA_BIT /* SATA device, valid in the discovery response only */ + +#define SA_SASDEV_IS_SSP_INITIATOR(sasDev) \ + (((sasDev)->initiator_ssp_stp_smp & SA_SASDEV_SSP_BIT) == SA_SASDEV_SSP_BIT) + +#define SA_SASDEV_IS_STP_INITIATOR(sasDev) \ + (((sasDev)->initiator_ssp_stp_smp & SA_SASDEV_STP_BIT) == SA_SASDEV_STP_BIT) + +#define SA_SASDEV_IS_SMP_INITIATOR(sasDev) \ + (((sasDev)->initiator_ssp_stp_smp & SA_SASDEV_SMP_BIT) == SA_SASDEV_SMP_BIT) + +#define SA_SASDEV_IS_SSP_TARGET(sasDev) \ + (((sasDev)->target_ssp_stp_smp & SA_SASDEV_SSP_BIT) == SA_SASDEV_SSP_BIT) + +#define SA_SASDEV_IS_STP_TARGET(sasDev) \ + (((sasDev)->target_ssp_stp_smp & SA_SASDEV_STP_BIT) == SA_SASDEV_STP_BIT) + +#define SA_SASDEV_IS_SMP_TARGET(sasDev) \ + (((sasDev)->target_ssp_stp_smp & SA_SASDEV_SMP_BIT) == SA_SASDEV_SMP_BIT) + +#define SA_SASDEV_IS_SATA_DEVICE(sasDev) \ + (((sasDev)->target_ssp_stp_smp & SA_SASDEV_SATA_BIT) == SA_SASDEV_SATA_BIT) + + + + +/** \brief the data structure describe SG list + * + * the data structure describe SG list + * + */ +typedef struct _SASG_DESCRIPTOR +{ + bit32 sgLower; /**< Lower 32 bits of data area physical address */ + bit32 sgUpper; /**< Upper 32 bits of data area physical address */ + bit32 len; /**< Total data length in bytes */ +} SASG_DESCRIPTOR, * PSASG_DESCRIPTOR; + +/** \brief data structure used to pass information about the scatter-gather list to the LL Layer + * + * The ESGL pages are uncached, have a configurable number of SGL + * of (min, max) = (1, 10), and are 16-byte aligned. Although + * the application can configure the page size, the size must be + * incremented in TBD-byte increments. Refer the hardware + * documentation for more detail on the format of ESGL + * structure. + * + */ +typedef struct agsaSgl_s +{ + bit32 sgLower; /**< Lower 32 bits of data area physical address */ + bit32 sgUpper; /**< Upper 32 bits of data area physical address */ + bit32 len; /**< Total data length in bytes */ + bit32 extReserved; /**< bit31 is for extended sgl list */ +} agsaSgl_t; + +/** \brief data structure is used to pass information about the extended + * scatter-gather list (ESGL) to the LL Layer + * + * The agsaEsgl_t data structure is used to pass information about the + * extended scatter-gather list (ESGL) to the LL Layer. + * + * When ESGL is used, its starting address is specified the first descriptor + * entry (i.e. descriptor[0]) in agsaSgl_t structure. + * + * The ESGL pages are uncached, have a fixed number of SGL of 10, and are + * 16-byte aligned. Refer the hardware documentation for more + * detail on ESGL. + * + */ +typedef struct agsaEsgl_s +{ + agsaSgl_t descriptor[MAX_ESGL_ENTRIES]; +} agsaEsgl_t; + +/** \brief data structure describes an SSP Command INFORMATION UNIT + * + * data structure describes an SSP Command INFORMATION UNIT used for SSP command and is part of + * the SSP frame. + * + * Currently, Additional CDB length is supported to 16 bytes + * + */ +#define MAX_CDB_LEN 32 +typedef struct agsaSSPCmdInfoUnitExt_s +{ + bit8 lun[8]; + bit8 reserved1; + bit8 efb_tp_taskAttribute; + bit8 reserved2; + bit8 additionalCdbLen; + bit8 cdb[MAX_CDB_LEN]; +} agsaSSPCmdInfoUnitExt_t ; + +#define DIF_UDT_SIZE 6 + +/* difAction in agsaDif_t */ +#define AGSA_DIF_INSERT 0 +#define AGSA_DIF_VERIFY_FORWARD 1 +#define AGSA_DIF_VERIFY_DELETE 2 +#define AGSA_DIF_VERIFY_REPLACE 3 +#define AGSA_DIF_VERIFY_UDT_REPLACE_CRC 5 +#define AGSA_DIF_REPLACE_UDT_REPLACE_CRC 7 + +#define agsaDIFSectorSize512 0 +#define agsaDIFSectorSize520 1 +#define agsaDIFSectorSize4096 2 +#define agsaDIFSectorSize4160 3 + + + +typedef struct agsaDif_s +{ + agBOOLEAN enableDIFPerLA; + bit32 flags; + bit16 initialIOSeed; + bit16 reserved; + bit32 DIFPerLAAddrLo; + bit32 DIFPerLAAddrHi; + bit16 DIFPerLARegion0SecCount; + bit16 Reserved2; + bit8 udtArray[DIF_UDT_SIZE]; + bit8 udrtArray[DIF_UDT_SIZE]; +} agsaDif_t; + + +/* From LL SDK2 */ +#define DIF_FLAG_BITS_ACTION 0x00000007 /* 0-2*/ +#define DIF_FLAG_BITS_CRC_VER 0x00000008 /* 3 */ +#define DIF_FLAG_BITS_CRC_INV 0x00000010 /* 4 */ +#define DIF_FLAG_BITS_CRC_SEED 0x00000020 /* 5 */ +#define DIF_FLAG_BITS_UDT_REF_TAG 0x00000040 /* 6 */ +#define DIF_FLAG_BITS_UDT_APP_TAG 0x00000080 /* 7 */ +#define DIF_FLAG_BITS_UDTR_REF_BLKCOUNT 0x00000100 /* 8 */ +#define DIF_FLAG_BITS_UDTR_APP_BLKCOUNT 0x00000200 /* 9 */ +#define DIF_FLAG_BITS_CUST_APP_TAG 0x00000C00 /* 10 11*/ +#define DIF_FLAG_BITS_EPRC 0x00001000 /* 12 */ +#define DIF_FLAG_BITS_Reserved 0x0000E000 /* 13 14 15*/ +#define DIF_FLAG_BITS_BLOCKSIZE_MASK 0x00070000 /* 16 17 18 */ +#define DIF_FLAG_BITS_BLOCKSIZE_SHIFT 16 +#define DIF_FLAG_BITS_BLOCKSIZE_512 0x00000000 /* */ +#define DIF_FLAG_BITS_BLOCKSIZE_520 0x00010000 /* 16 */ +#define DIF_FLAG_BITS_BLOCKSIZE_4096 0x00020000 /* 17 */ +#define DIF_FLAG_BITS_BLOCKSIZE_4160 0x00030000 /* 16 17 */ +#define DIF_FLAG_BITS_UDTVMASK 0x03F00000 /* 20 21 22 23 24 25 */ +#define DIF_FLAG_BITS_UDTV_SHIFT 20 +#define DIF_FLAG_BITS_UDTUPMASK 0xF6000000 /* 26 27 28 29 30 31 */ +#define DIF_FLAG_BITS_UDTUPSHIFT 26 + +typedef struct agsaEncryptDek_s +{ + bit32 dekTable; + bit32 dekIndex; +} agsaEncryptDek_t; + +typedef struct agsaEncrypt_s +{ + agsaEncryptDek_t dekInfo; + bit32 kekIndex; + agBOOLEAN keyTagCheck; + agBOOLEAN enableEncryptionPerLA; /* new */ + bit32 sectorSizeIndex; + bit32 cipherMode; + bit32 keyTag_W0; + bit32 keyTag_W1; + bit32 tweakVal_W0; + bit32 tweakVal_W1; + bit32 tweakVal_W2; + bit32 tweakVal_W3; + bit32 EncryptionPerLAAddrLo; /* new */ + bit32 EncryptionPerLAAddrHi; /* new */ + bit16 EncryptionPerLRegion0SecCount; /* new */ + bit16 reserved; +} agsaEncrypt_t; + +/** \brief data structure describes a SAS SSP command request to be sent to the target device + * + * data structure describes a SAS SSP command request to be sent to the + * target device. This structure limits the CDB length in SSP + * command up to 16 bytes long. + * + * This data structure is one instance of the generic request issued to + * saSSPStart() and is passed as an agsaSASRequestBody_t . + * + */ +typedef struct agsaSSPInitiatorRequest_s +{ + agsaSgl_t agSgl; /**< This structure is used to define either + an ESGL list or a single SGL for the SSP + command operation */ + bit32 dataLength; /**< Total data length in bytes */ + bit16 firstBurstSize; /**< First Burst Size field as defined by + SAS specification */ + bit16 flag; /**< bit1-0 TLR as SAS specification + bit31-2 reserved */ + agsaSSPCmdInfoUnit_t sspCmdIU; /**< Structure containing SSP Command + INFORMATION UNIT */ + agsaDif_t dif; + agsaEncrypt_t encrypt; +#ifdef SA_TESTBASE_EXTRA + /* Added by TestBase */ + bit16 bstIndex; +#endif /* SA_TESTBASE_EXTRA */ +} agsaSSPInitiatorRequest_t; + +/** \brief data structure describes a SAS SSP command request Ext to be sent to the target device + * + * data structure describes a SAS SSP command request to be sent to the + * target device. This structure support the CDB length in SSP + * command more than 16 bytes long. + * + * This data structure is one instance of the generic request issued to + * saSSPStart() and is passed as an agsaSASRequestBody_t . + * + */ +typedef struct agsaSSPInitiatorRequestExt_s +{ + agsaSgl_t agSgl; /**< This structure is used to define either + an ESGL list or a single SGL for the SSP + command operation */ + bit32 dataLength; + bit16 firstBurstSize; + bit16 flag; + agsaSSPCmdInfoUnitExt_t sspCmdIUExt; + agsaDif_t dif; + agsaEncrypt_t encrypt; +} agsaSSPInitiatorRequestExt_t; + + +typedef struct agsaSSPInitiatorRequestIndirect_s +{ + agsaSgl_t agSgl; /**< This structure is used to define either + an ESGL list or a single SGL for the SSP + command operation */ + bit32 dataLength; + bit16 firstBurstSize; + bit16 flag; + bit32 sspInitiatorReqAddrUpper32; /**< The upper 32 bits of the 64-bit physical DMA address of the SSP initiator request buffer */ + bit32 sspInitiatorReqAddrLower32; /**< The lower 32 bits of the 64-bit physical DMA address of the SSP initiator request buffer */ + bit32 sspInitiatorReqLen; /**< Specifies the length of the SSP initiator request in bytes */ + agsaDif_t dif; + agsaEncrypt_t encrypt; + +}agsaSSPInitiatorRequestIndirect_t; + + + + +/** \brief data structure describes a SAS SSP target read and write request + * + * The agsaSSPTargetRequest_t data structure describes a SAS SSP target read + * and write request to be issued on the port. It includes the + * length of the data to be received or sent, an offset into the + * data block where the transfer is to start, and a list of + * scatter-gather buffers. + * + * This data structure is one instance of the generic request issued + * to saSSPStart() and is passed as an agsaSASRequestBody_t . + * + */ +/** bit definitions for sspOption + Bit 0-1: Transport Layer Retry setting for other phase: + 00b: No retry + 01b: Retry on ACK/NAK timeout + 10b: Retry on NAK received + 11b: Retry on both ACK/NAK timeout and NAK received + Bit 2-3: Transport Layer Retry setting for data phase: + 00b: No retry + 01b: Retry on ACK/NAK timeout + 10b: Retry on NAK received + 11b: Retry on both ACK/NAK timeout and NAK received + Bit 4: Retry Data Frame. Valid only on write command. Indicates whether Target supports RTL for this particular IO. + 1b: enabled + 0b: disabled + Bit 5: Auto good response on successful read (data transfer from target to initiator) request. + 1b: Enabled + 0b: Disabled + Bits 6-15 : Reserved. + */ +typedef struct agsaSSPTargetRequest_s +{ + agsaSgl_t agSgl; /**< This structure is used to define either an ESGL list or + a single SGL for the target read or write operation */ + bit32 dataLength; /**< Specifies the amount of data to be sent in this data phase */ + bit32 offset; /**< Specifies the offset into the overall data block + where this data phase is to begin */ + bit16 agTag; /**< Tag from ossaSSPReqReceived(). */ + bit16 sspOption; /**< SSP option for retry */ + agsaDif_t dif; +} agsaSSPTargetRequest_t; + +#define SSP_OPTION_BITS 0x3F /**< bit5-AGR, bit4-RDF bit3,2-RTE, bit1,0-AN */ +#define SSP_OPTION_ODS 0x8000 /**< bit15-ODS */ + +#define SSP_OPTION_OTHR_NO_RETRY 0 +#define SSP_OPTION_OTHR_RETRY_ON_ACK_NAK_TIMEOUT 1 +#define SSP_OPTION_OTHR_RETRY_ON_NAK_RECEIVED 2 +#define SSP_OPTION_OTHR_RETRY_ON_BOTH_ACK_NAK_TIMEOUT_AND_NAK_RECEIVED 3 + +#define SSP_OPTION_DATA_NO_RETRY 0 +#define SSP_OPTION_DATA_RETRY_ON_ACK_NAK_TIMEOUT 1 +#define SSP_OPTION_DATA_RETRY_ON_NAK_RECEIVED 2 +#define SSP_OPTION_DATA_RETRY_ON_BOTH_ACK_NAK_TIMEOUT_AND_NAK_RECEIVED 3 + +#define SSP_OPTION_RETRY_DATA_FRAME_ENABLED (1 << SHIFT4) +#define SSP_OPTION_AUTO_GOOD_RESPONSE (1 << SHIFT5) +#define SSP_OPTION_ENCRYPT (1 << SHIFT6) +#define SSP_OPTION_DIF (1 << SHIFT7) +#define SSP_OPTION_OVERRIDE_DEVICE_STATE (1 << SHIFT15) + + +/** \brief data structure describes a SAS SSP target response to be issued + * on the port + * + * This data structure is one instance of the generic request issued to + * saSSPStart() and is passed as an agsaSASRequestBody_t + * + */ +typedef struct agsaSSPTargetResponse_s +{ + bit32 agTag; /**< Tag from ossaSSPReqReceived(). */ + void *frameBuf; + bit32 respBufLength; /**< Specifies the length of the Response buffer */ + bit32 respBufUpper; /**< Upper 32 bit of physical address of OS Layer + allocated the Response buffer + (agsaSSPResponseInfoUnit_t). + Valid only when respBufLength is not zero */ + bit32 respBufLower; /**< Lower 32 bit of physical address of OS Layer + allocated the Response buffer + (agsaSSPResponseInfoUnit_t). + Valid only when respBufLength is not zero */ + bit32 respOption; /**< Bit 0-1: ACK and NAK retry option: + 00b: No retry + 01b: Retry on ACK/NAK timeout + 10b: Retry on NAK received + 11b: Retry on both ACK/NAK timeout and NAK received */ +} agsaSSPTargetResponse_t; + +#define RESP_OPTION_BITS 0x3 /** bit0-1 */ +#define RESP_OPTION_ODS 0x8000 /** bit15 */ + +/** \brief data structure describes a SMP request or response frame to be sent on the SAS port + * + * The agsaSMPFrame_t data structure describes a SMP request or response + * frame to be issued or sent on the SAS port. + * + * This data structure is one instance of the generic request issued to + * saSMPStart() and is passed as an agsaSASRequestBody_t . + * + */ +typedef struct agsaSMPFrame_s +{ + void *outFrameBuf; /**< if payload is less than 32 bytes,A virtual + frameBuf can be used. instead of physical + address. Set to NULL and use physical + address if payload is > 32 bytes */ + bit32 outFrameAddrUpper32; /**< The upper 32 bits of the 64-bit physical + DMA address of the SMP frame buffer */ + bit32 outFrameAddrLower32; /**< The lower 32 bits of the 64-bit physical + DMA address of the SMP frame buffer */ + bit32 outFrameLen; /**< Specifies the length of the SMP request + frame excluding the CRC field in bytes */ + bit32 inFrameAddrUpper32; /**< The upper 32 bits of the 64-bit phsical address + of DMA address of response SMP Frame buffer */ + bit32 inFrameAddrLower32; /**< The lower 32 bits of the 64-bit phsical address + of DMA address of response SMP Frame buffer */ + bit32 inFrameLen; /**< Specifies the length of the SMP response + frame excluding the CRC field in bytes */ + bit32 expectedRespLen; /**< Specifies the length of SMP Response */ + bit32 flag; /** For the SPCv controller: + Bit 0: Indirect Response (IR). This indicates + direct or indirect mode for SMP response frame + to be received. + 0b: Direct mode + 1b: Indirect mode + + Bit 1: Indirect Payload (IP). This indicates + direct or indirect mode for SMP request frame + to be sent. + 0b: Direct mode + 1b: Indirect mode + + Bits 2-31: Reserved + For the SPC controller: This is not applicable. + */ + +} agsaSMPFrame_t; + +#define smpFrameFlagDirectResponse 0 +#define smpFrameFlagIndirectResponse 1 +#define smpFrameFlagDirectPayload 0 +#define smpFrameFlagIndirectPayload 2 + +/** \brief union data structure specifies a request + * + * union data structure specifies a request + */ +typedef union agsaSASRequestBody_u +{ + agsaSSPInitiatorRequest_t sspInitiatorReq; /**< Structure containing the SSP initiator request, Support up to 16 bytes CDB */ + agsaSSPInitiatorRequestExt_t sspInitiatorReqExt; /**< Structure containing the SSP initiator request for CDB > 16 bytes */ + agsaSSPInitiatorRequestIndirect_t sspInitiatorReqIndirect; /**< Structure containing the SSP indirect initiator request */ + agsaSSPTargetRequest_t sspTargetReq; /**< Structure containing the SSP Target request */ + agsaSSPScsiTaskMgntReq_t sspTaskMgntReq; /**< Structure containing the SSP SCSI Task Management request */ + agsaSSPTargetResponse_t sspTargetResponse; /**< Structure containing the SSP Target response. */ + agsaSMPFrame_t smpFrame; /**< Structure containing SMP request or response frame */ +}agsaSASRequestBody_t; + + + + +/** \brief data structure describes an STP or direct connect SATA command + * + * The agsaSATAInitiatorRequest_t data structure describes an STP or direct + * connect SATA command request to be sent to the device and + * passed as a parameter to saSATAStart() function. + * + * This structure is an encapsulation of SATA FIS (Frame Information + * Structures), which enables the execution of ATA command + * descriptor using SATA transport + * + */ +typedef struct agsaSATAInitiatorRequest_s +{ + agsaSgl_t agSgl; /**< This structure is used to define either an ESGL + list or a single SGL for operation that involves + DMA transfer */ + + bit32 dataLength; /**< Total data length in bytes */ + + bit32 option; /**< Operational option, defined using the bit field. + b7-1: reserved + b0: AGSA-STP-CLOSE-CLEAR-AFFILIATION */ + + agsaSATAHostFis_t fis; /**< The FIS request */ + agsaDif_t dif; + agsaEncrypt_t encrypt; + bit8 scsiCDB[16]; +#ifdef SA_TESTBASE_EXTRA + /* Added by TestBase */ + bit16 bstIndex; +#endif /* SA_TESTBASE_EXTRA */ +} agsaSATAInitiatorRequest_t; + + +/* controller Configuration page */ +#define AGSA_SAS_PROTOCOL_TIMER_CONFIG_PAGE 0x04 +#define AGSA_INTERRUPT_CONFIGURATION_PAGE 0x05 +#define AGSA_IO_GENERAL_CONFIG_PAGE 0x06 +#define AGSA_ENCRYPTION_GENERAL_CONFIG_PAGE 0x20 +#define AGSA_ENCRYPTION_DEK_CONFIG_PAGE 0x21 +#define AGSA_ENCRYPTION_CONTROL_PARM_PAGE 0x22 +#define AGSA_ENCRYPTION_HMAC_CONFIG_PAGE 0x23 + +#ifdef HIALEAH_ENCRYPTION +typedef struct agsaEncryptGeneralPage_s { + bit32 numberOfKeksPageCode; /* 0x20 */ + bit32 KeyCardIdKekIndex; + bit32 KeyCardId3_0; + bit32 KeyCardId7_4; + bit32 KeyCardId11_8; +} agsaEncryptGeneralPage_t; +#else +typedef struct agsaEncryptGeneralPage_s { + bit32 pageCode; /* 0x20 */ + bit32 numberOfDeks; +} agsaEncryptGeneralPage_t; +#endif /* HIALEAH_ENCRYPTION */ + +#define AGSA_ENC_CONFIG_PAGE_KEK_NUMBER 0x0000FF00 +#define AGSA_ENC_CONFIG_PAGE_KEK_SHIFT 8 + +/* sTSDK 4.14 */ +typedef struct agsaEncryptDekConfigPage_s { + bit32 pageCode; + bit32 table0AddrLo; + bit32 table0AddrHi; + bit32 table0Entries; + bit32 table0BFES; + bit32 table1AddrLo; + bit32 table1AddrHi; + bit32 table1Entries; + bit32 table1BFES; +} agsaEncryptDekConfigPage_t; + +#define AGSA_ENC_DEK_CONFIG_PAGE_DEK_TABLE_NUMBER 0xF0000000 +#define AGSA_ENC_DEK_CONFIG_PAGE_DEK_TABLE_SHIFT SHIFT28 +#define AGSA_ENC_DEK_CONFIG_PAGE_DEK_CACHE_WAY 0x0F000000 +#define AGSA_ENC_DEK_CONFIG_PAGE_DEK_CACHE_SHIFT SHIFT24 + +/*sTSDK 4.18 */ +/* CCS (Current Crypto Services) and NOPR (Number of Operators) are valid only in GET_CONTROLLER_CONFIG */ +/* NAR, CORCAP and USRCAP are valid only when AUT==1 */ +typedef struct agsaEncryptControlParamPage_s { + bit32 pageCode; /* 0x22 */ + bit32 CORCAP; /* Crypto Officer Role Capabilities */ + bit32 USRCAP; /* User Role Capabilities */ + bit32 CCS; /* Current Crypto Services */ + bit32 NOPR; /* Number of Operators */ +} agsaEncryptControlParamPage_t; + +typedef struct agsaEncryptInfo_s { + bit32 encryptionCipherMode; + bit32 encryptionSecurityMode; + bit32 status; + bit32 flag; +} agsaEncryptInfo_t; + + +#define OperatorAuthenticationEnable_AUT 1 +#define ReturnToFactoryMode_ARF 2 + +/*sTSDK 4.19 */ +typedef struct agsaEncryptSelfTestBitMap_s { + bit32 AES_Test; + bit32 KEY_WRAP_Test; + bit32 HMAC_Test; +} agsaEncryptSelfTestBitMap_t; + +typedef struct agsaEncryptSelfTestStatusBitMap_s{ + bit32 AES_Status; + bit32 KEY_WRAP_Status; + bit32 HMAC_Status; +} agsaEncryptSelfTestStatusBitMap_t; + +typedef struct agsaEncryptHMACTestDescriptor_s +{ + bit32 Dword0; + bit32 MsgAddrLo; + bit32 MsgAddrHi; + bit32 MsgLen; + bit32 DigestAddrLo; + bit32 DigestAddrHi; + bit32 KeyAddrLo; + bit32 KeyAddrHi; + bit32 KeyLen; +} agsaEncryptHMACTestDescriptor_t; + +typedef struct agsaEncryptHMACTestResult_s +{ + bit32 Dword0; + bit32 Dword[12]; +} agsaEncryptHMACTestResult_t; + +typedef struct agsaEncryptSHATestDescriptor_s +{ + bit32 Dword0; + bit32 MsgAddrLo; + bit32 MsgAddrHi; + bit32 MsgLen; + bit32 DigestAddrLo; + bit32 DigestAddrHi; +} agsaEncryptSHATestDescriptor_t; + +typedef struct agsaEncryptSHATestResult_s +{ + bit32 Dword0; + bit32 Dword[12]; +} agsaEncryptSHATestResult_t; + +/* types of self test */ +#define AGSA_BIST_TEST 0x1 +#define AGSA_HMAC_TEST 0x2 +#define AGSA_SHA_TEST 0x3 + + +/*sTSDK 4.13 */ +typedef struct agsaEncryptDekBlob_s { + bit8 dekBlob[80]; +} agsaEncryptDekBlob_t; + +typedef struct agsaEncryptKekBlob_s { + bit8 kekBlob[48]; +} agsaEncryptKekBlob_t; + +/*sTSDK 4.45 */ +typedef struct agsaEncryptHMACConfigPage_s +{ + bit32 PageCode; + bit32 CustomerTag; + bit32 KeyAddrLo; + bit32 KeyAddrHi; +} agsaEncryptHMACConfigPage_t; + +/*sTSDK 4.38 */ +#define AGSA_ID_SIZE 31 +typedef struct agsaID_s { + bit8 ID[AGSA_ID_SIZE]; +}agsaID_t; + + +#define SA_OPR_MGMNT_FLAG_MASK 0x00003000 +#define SA_OPR_MGMNT_FLAG_SHIFT 12 + +/* */ +typedef struct agsaSASPhyMiscPage_s { + bit32 Dword0; + bit32 Dword1; +} agsaSASPhyMiscPage_t ; + + +typedef struct agsaHWEventEncrypt_s { + bit32 encryptOperation; + bit32 status; + bit32 eq; /* error qualifier */ + bit32 info; + void *handle; + void *param; +} agsaHWEventEncrypt_t; + +/*sTSDK 4.32 */ +typedef struct agsaHWEventMode_s { + bit32 modePageOperation; + bit32 status; + bit32 modePageLen; + void *modePage; + void *context; +} agsaHWEventMode_t; + +/*sTSDK 4.33 */ +typedef struct agsaInterruptConfigPage_s { + bit32 pageCode; + bit32 vectorMask0; + bit32 vectorMask1; + bit32 ICTC0; + bit32 ICTC1; + bit32 ICTC2; + bit32 ICTC3; + bit32 ICTC4; + bit32 ICTC5; + bit32 ICTC6; + bit32 ICTC7; +} agsaInterruptConfigPage_t; +typedef struct agsaIoGeneralPage_s { + bit32 pageCode; /* 0x06 */ + bit32 ActiveMask; + bit32 QrntTime; +} agsaIoGeneralPage_t; + +/* \brief data structure defines detail information about Agilent Error +* Detection Code (DIF) errors. +* +* The agsaDifDetails_t data structure defines detail information about +* PMC Error Detection Code (DIF) error. Please refer to the latest T10 SBC +* and SPC draft/specification for the definition of the Protection +* Information. +* +* This structure is filled by the function saGetDifErrorDetails(). +*/ + +typedef struct agsaDifDetails_s { + bit32 UpperLBA; + bit32 LowerLBA; + bit8 sasAddressHi[4]; + bit8 sasAddressLo[4]; + bit32 ExpectedCRCUDT01; + bit32 ExpectedUDT2345; + bit32 ActualCRCUDT01; + bit32 ActualUDT2345; + bit32 DIFErrDevID; + bit32 ErrBoffsetEDataLen; + void * frame; +} agsaDifDetails_t; + +/** \brief data structure for SAS protocol timer configuration page. + * + */ +typedef struct agsaSASProtocolTimerConfigurationPage_s{ + bit32 pageCode; /* 0 */ + bit32 MST_MSI; /* 1 */ + bit32 STP_SSP_MCT_TMO; /* 2 */ + bit32 STP_FRM_TMO; /* 3 */ + bit32 STP_IDLE_TMO; /* 4 */ + bit32 OPNRJT_RTRY_INTVL; /* 5 */ + bit32 Data_Cmd_OPNRJT_RTRY_TMO; /* 6 */ + bit32 Data_Cmd_OPNRJT_RTRY_THR; /* 7 */ + bit32 MAX_AIP; /* 8 */ +} agsaSASProtocolTimerConfigurationPage_t; + + +/** \brief data structure for firmware flash update saFwFlashUpdate(). + * + * The agsaUpdateFwFlash data structure specifies a request to saFwFlashUpdate() + */ +typedef struct agsaUpdateFwFlash_s +{ + bit32 currentImageOffset; + bit32 currentImageLen; + bit32 totalImageLen; + agsaSgl_t agSgl; +} agsaUpdateFwFlash_t; + + + +/** \brief data structure for extended firmware flash update saFwFlashExtUpdate(). + * + * The agsaFlashExtExecute_s data structure specifies a request to saFwFlashExtUpdate() + */ +typedef struct agsaFlashExtExecute_s +{ + bit32 command; + bit32 partOffset; + bit32 dataLen; + agsaSgl_t *agSgl; +} agsaFlashExtExecute_t; + + +/** \brief data structure for firmware flash update saFwFlashUpdate(). + * + * The agsaFlashExtResponse_t data structure specifies a request to ossaFlashExtExecuteCB().() + */ +typedef struct agsaFlashExtResponse_s +{ + bit32 epart_size; + bit32 epart_sect_size; +} agsaFlashExtResponse_t; + + +/** \brief data structure for set fields in MPI table. + * The agsaMPIContext_t data structure is used to set fields in MPI table. + * For details of MPI table, refer to PM8001 Tachyon SPC 8x6G Programmers' + * Manual PMC-2080222 or PM8008/PM8009/PM8018 Tachyon SPCv/SPCve/SPCv+ Programmers Manual + * PMC-2091148/PMC-2102373. + sTSDK section 4.39 + */ + +typedef struct agsaMPIContext_s +{ + bit32 MPITableType; + bit32 offset; + bit32 value; +} agsaMPIContext_t; + +#define AGSA_MPI_MAIN_CONFIGURATION_TABLE 1 +#define AGSA_MPI_GENERAL_STATUS_TABLE 2 +#define AGSA_MPI_INBOUND_QUEUE_CONFIGURATION_TABLE 3 +#define AGSA_MPI_OUTBOUND_QUEUE_CONFIGURATION_TABLE 4 +#define AGSA_MPI_SAS_PHY_ANALOG_SETUP_TABLE 5 +#define AGSA_MPI_INTERRUPT_VECTOR_TABLE 6 +#define AGSA_MPI_PER_SAS_PHY_ATTRIBUTE_TABLE 7 +#define AGSA_MPI_OUTBOUND_QUEUE_FAILOVER_TABLE 8 + + +/************************************************************/ +/*This flag and datastructure are specific for fw profiling, Now defined as compiler flag*/ +//#define SPC_ENABLE_PROFILE + +#ifdef SPC_ENABLE_PROFILE +typedef struct agsaFwProfile_s +{ + bit32 tcid; + bit32 processor; + bit32 cmd; + bit32 len; + bit32 codeStartAdd; + bit32 codeEndAdd; + agsaSgl_t agSgl; +} agsaFwProfile_t; +#endif +/************************************************************/ +/** \brief Callback definition for .ossaDeviceRegistration + * + */ +typedef void (*ossaDeviceRegistrationCB_t)( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + agsaDevHandle_t *agDevHandle, + bit32 deviceID + ); + +/** \brief Callback definition for + * + */ +typedef void (*ossaDeregisterDeviceHandleCB_t)( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaDevHandle_t *agDevHandle, + bit32 status + ); + +/** \brief Callback definition for + * + */ +typedef void (*ossaGenericCB_t)(void); + + +/** \brief Callback definition for abort SMP SSP SATA callback + * + */ +typedef void (*ossaGenericAbortCB_t)( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 flag, + bit32 status + ); + + +typedef void (*ossaLocalPhyControlCB_t)( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 phyId, + bit32 phyOperation, + bit32 status, + void *parm + ); + + +/** \brief Callback definition for + * + */ +typedef void (*ossaSATACompletedCB_t)( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + void *agFirstDword, + bit32 agIOInfoLen, + void *agParam + ); + + +/** \brief Callback definition for + * + */ +typedef void (*ossaSMPCompletedCB_t)( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle + ); + + +/** \brief Callback definition for + * + */ +typedef void (*ossaSSPCompletedCB_t)( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit16 sspTag, + bit32 agOtherInfo + ); + +/** \brief Callback definition for + * + */ +typedef void (*ossaSetDeviceInfoCB_t) ( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaDevHandle_t *agDevHandle, + bit32 status, + bit32 option, + bit32 param + ); + +typedef struct agsaOffloadDifDetails_s +{ + bit32 ExpectedCRCUDT01; + bit32 ExpectedUDT2345; + bit32 ActualCRCUDT01; + bit32 ActualUDT2345; + bit32 DIFErr; + bit32 ErrBoffset; +} agsaOffloadDifDetails_t; + +typedef struct agsaDifEncPayload_s +{ + agsaSgl_t SrcSgl; + bit32 SrcDL; + agsaSgl_t DstSgl; + bit32 DstDL; + agsaDif_t dif; + agsaEncrypt_t encrypt; +} agsaDifEncPayload_t; + +typedef void (*ossaVhistCaptureCB_t) ( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + bit32 len); + +typedef void (*ossaDIFEncryptionOffloadStartCB_t) ( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + agsaOffloadDifDetails_t *agsaOffloadDifDetails + ); + +#define SA_RESERVED_REQUEST_COUNT 16 + +#ifdef SA_FW_TIMER_READS_STATUS +#define SA_FW_TIMER_READS_STATUS_INTERVAL 20 +#endif /* SA_FW_TIMER_READS_STATUS */ + +#define SIZE_DW 4 /**< Size in bytes */ +#define SIZE_QW 8 /**< Size in bytes */ + +#define PCIBAR0 0 /**< PCI Base Address 0 */ +#define PCIBAR1 1 /**< PCI Base Address 1 */ +#define PCIBAR2 2 /**< PCI Base Address 2 */ +#define PCIBAR3 3 /**< PCI Base Address 3 */ +#define PCIBAR4 4 /**< PCI Base Address 4 */ +#define PCIBAR5 5 /**< PCI Base Address 5 */ + +/** \brief describe an element of SPC-SPCV converter + * + * This structure is used + * + */ +typedef struct agsaBarOffset_s +{ + bit32 Generic; /* */ + bit32 Bar; /* */ + bit32 Offset; /* */ + bit32 Length; /* */ +} agsaBarOffset_t; + +typedef union agsabit32bit64_U +{ + bit32 S32[2]; + bit64 B64; +} agsabit32bit64; + +/* +The agsaIOErrorEventStats_t data structure is used as parameter in ossaGetIOErrorStatsCB(),ossaGetIOEventStatsCB(). +This data structure contains the number of IO error and event. +*/ +typedef struct agsaIOErrorEventStats_s +{ + bit32 agOSSA_IO_COMPLETED_ERROR_SCSI_STATUS; + bit32 agOSSA_IO_ABORTED; + bit32 agOSSA_IO_OVERFLOW; + bit32 agOSSA_IO_UNDERFLOW; + bit32 agOSSA_IO_FAILED; + bit32 agOSSA_IO_ABORT_RESET; + bit32 agOSSA_IO_NOT_VALID; + bit32 agOSSA_IO_NO_DEVICE; + bit32 agOSSA_IO_ILLEGAL_PARAMETER; + bit32 agOSSA_IO_LINK_FAILURE; + bit32 agOSSA_IO_PROG_ERROR; + bit32 agOSSA_IO_DIF_IN_ERROR; + bit32 agOSSA_IO_DIF_OUT_ERROR; + bit32 agOSSA_IO_ERROR_HW_TIMEOUT; + bit32 agOSSA_IO_XFER_ERROR_BREAK; + bit32 agOSSA_IO_XFER_ERROR_PHY_NOT_READY; + bit32 agOSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED; + bit32 agOSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION; + bit32 agOSSA_IO_OPEN_CNX_ERROR_BREAK; + bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS; + bit32 agOSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION; + bit32 agOSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED; + bit32 agOSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY; + bit32 agOSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION; + bit32 agOSSA_IO_OPEN_CNX_ERROR_UNKNOWN_ERROR; + bit32 agOSSA_IO_XFER_ERROR_NAK_RECEIVED; + bit32 agOSSA_IO_XFER_ERROR_ACK_NAK_TIMEOUT; + bit32 agOSSA_IO_XFER_ERROR_PEER_ABORTED; + bit32 agOSSA_IO_XFER_ERROR_RX_FRAME; + bit32 agOSSA_IO_XFER_ERROR_DMA; + bit32 agOSSA_IO_XFER_ERROR_CREDIT_TIMEOUT; + bit32 agOSSA_IO_XFER_ERROR_SATA_LINK_TIMEOUT; + bit32 agOSSA_IO_XFER_ERROR_SATA; + bit32 agOSSA_IO_XFER_ERROR_ABORTED_DUE_TO_SRST; + bit32 agOSSA_IO_XFER_ERROR_REJECTED_NCQ_MODE; + bit32 agOSSA_IO_XFER_ERROR_ABORTED_NCQ_MODE; + bit32 agOSSA_IO_XFER_OPEN_RETRY_TIMEOUT; + bit32 agOSSA_IO_XFER_SMP_RESP_CONNECTION_ERROR; + bit32 agOSSA_IO_XFER_ERROR_UNEXPECTED_PHASE; + bit32 agOSSA_IO_XFER_ERROR_XFER_RDY_OVERRUN; + bit32 agOSSA_IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED; + bit32 agOSSA_IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT; + bit32 agOSSA_IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK; + bit32 agOSSA_IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK; + bit32 agOSSA_IO_XFER_ERROR_OFFSET_MISMATCH; + bit32 agOSSA_IO_XFER_ERROR_XFER_ZERO_DATA_LEN; + bit32 agOSSA_IO_XFER_CMD_FRAME_ISSUED; + bit32 agOSSA_IO_ERROR_INTERNAL_SMP_RESOURCE; + bit32 agOSSA_IO_PORT_IN_RESET; + bit32 agOSSA_IO_DS_NON_OPERATIONAL; + bit32 agOSSA_IO_DS_IN_RECOVERY; + bit32 agOSSA_IO_TM_TAG_NOT_FOUND; + bit32 agOSSA_IO_XFER_PIO_SETUP_ERROR; + bit32 agOSSA_IO_SSP_EXT_IU_ZERO_LEN_ERROR; + bit32 agOSSA_IO_DS_IN_ERROR; + bit32 agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY; + bit32 agOSSA_IO_ABORT_IN_PROGRESS; + bit32 agOSSA_IO_ABORT_DELAYED; + bit32 agOSSA_IO_INVALID_LENGTH; + bit32 agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT; + bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED; + bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO; + bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST; + bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE; + bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED; + bit32 agOSSA_IO_DS_INVALID; + bit32 agOSSA_IO_XFER_READ_COMPL_ERR; + bit32 agOSSA_IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR; + bit32 agOSSA_IO_XFR_ERROR_INTERNAL_CRC_ERROR; + bit32 agOSSA_MPI_IO_RQE_BUSY_FULL; + bit32 agOSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE; + bit32 agOSSA_MPI_ERR_ATAPI_DEVICE_BUSY; + bit32 agOSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS; + bit32 agOSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH; + bit32 agOSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID; + bit32 agOSSA_IO_XFR_ERROR_DEK_IV_MISMATCH; + bit32 agOSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR; + bit32 agOSSA_IO_XFR_ERROR_INTERNAL_RAM; + bit32 agOSSA_IO_XFR_ERROR_DIF_MISMATCH; + bit32 agOSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH; + bit32 agOSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH; + bit32 agOSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH; + bit32 agOSSA_IO_XFR_ERROR_INVALID_SSP_RSP_FRAME; + bit32 agOSSA_IO_XFER_ERR_EOB_DATA_OVERRUN; + bit32 agOSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS; + bit32 agOSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED; + bit32 agOSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE; + bit32 agOSSA_IO_XFER_ERROR_DIF_INTERNAL_ERROR; + bit32 agOSSA_MPI_ERR_OFFLOAD_DIF_OR_ENC_NOT_ENABLED; + bit32 agOSSA_IO_XFER_ERROR_DMA_ACTIVATE_TIMEOUT; + bit32 agOSSA_IO_UNKNOWN_ERROR; +} agsaIOErrorEventStats_t; + + +/************************************************************************************ + * * + * Data Structures Defined for LL API ends * + * * + ************************************************************************************/ +#ifdef SALL_API_TEST +typedef struct agsaIOCountInfo_s +{ + bit32 numSSPStarted; // saSSPStart() + bit32 numSSPAborted; // saSSPAbort() + bit32 numSSPAbortedCB; // ossaSSPAbortCB() + bit32 numSSPCompleted; // includes success and aborted IOs + bit32 numSMPStarted; // saSMPStart() + bit32 numSMPAborted; // saSMPAbort() + bit32 numSMPAbortedCB; // ossaSMPAbortCB() + bit32 numSMPCompleted; // includes success and aborted IOs + bit32 numSataStarted; // saSATAStart() + bit32 numSataAborted; // saSATAAbort() + bit32 numSataAbortedCB; // ossaSATAAbortCB() + bit32 numSataCompleted; // includes success and aborted IOs + bit32 numEchoSent; // saEchoCommand() + bit32 numEchoCB; // ossaEchoCB() + bit32 numUNKNWRespIOMB; // unknow Response IOMB received + bit32 numOurIntCount; //InterruptHandler() counter + bit32 numSpuriousInt; //spurious interrupts +// bit32 numSpInts[64]; //spuriours interrupts count for each OBQ (PI=CI) +// bit32 numSpInts1[64]; //spuriours interrupts count for each OBQ (PI!=CI) +} agsaIOCountInfo_t; + +/* Total IO Counter */ +#define LL_COUNTERS 17 +/* Counter Bit Map */ +#define COUNTER_SSP_START 0x000001 +#define COUNTER_SSP_ABORT 0x000002 +#define COUNTER_SSPABORT_CB 0x000004 +#define COUNTER_SSP_COMPLETEED 0x000008 +#define COUNTER_SMP_START 0x000010 +#define COUNTER_SMP_ABORT 0x000020 +#define COUNTER_SMPABORT_CB 0x000040 +#define COUNTER_SMP_COMPLETEED 0x000080 +#define COUNTER_SATA_START 0x000100 +#define COUNTER_SATA_ABORT 0x000200 +#define COUNTER_SATAABORT_CB 0x000400 +#define COUNTER_SATA_COMPLETEED 0x000800 +#define COUNTER_ECHO_SENT 0x001000 +#define COUNTER_ECHO_CB 0x002000 +#define COUNTER_UNKWN_IOMB 0x004000 +#define COUNTER_OUR_INT 0x008000 +#define COUNTER_SPUR_INT 0x010000 +#define ALL_COUNTERS 0xFFFFFF + +typedef union agsaLLCountInfo_s +{ + agsaIOCountInfo_t IOCounter; + bit32 arrayIOCounter[LL_COUNTERS]; +} agsaLLCountInfo_t; + +#endif /* SALL_API_TEST */ + +#define MAX_IO_DEVICE_ENTRIES 4096 /**< Maximum Device Entries */ + + +#ifdef SA_ENABLE_POISION_TLP +#define SA_PTNFE_POISION_TLP 1 /* Enable if one */ +#else /* SA_ENABLE_POISION_TLP */ +#define SA_PTNFE_POISION_TLP 0 /* Disable if zero default setting */ +#endif /* SA_ENABLE_POISION_TLP */ + +#ifdef SA_DISABLE_MDFD +#define SA_MDFD_MULTI_DATA_FETCH 1 /* Disable if one */ +#else /* SA_DISABLE_MDFD */ +#define SA_MDFD_MULTI_DATA_FETCH 0 /* Enable if zero default setting */ +#endif /* SA_DISABLE_MDFD */ + +#ifdef SA_ENABLE_ARBTE +#define SA_ARBTE 1 /* Enable if one */ +#else /* SA_ENABLE_ARBTE */ +#define SA_ARBTE 0 /* Disable if zero default setting */ +#endif /* SA_ENABLE_ARBTE */ + +#ifdef SA_DISABLE_OB_COAL +#define SA_OUTBOUND_COALESCE 0 /* Disable if zero */ +#else /* SA_DISABLE_OB_COAL */ +#define SA_OUTBOUND_COALESCE 1 /* Enable if one default setting */ +#endif /* SA_DISABLE_OB_COAL */ + + +/*********************************************************************************** + * * + * The OS Layer Functions Declarations start * + * * + ***********************************************************************************/ +#include "saosapi.h" +/*********************************************************************************** + * * + * The OS Layer Functions Declarations end * + * * + ***********************************************************************************/ + +/*********************************************************************************** + * * + * The LL Layer Functions Declarations start * + * * + ***********************************************************************************/ + +#ifdef FAST_IO_TEST +/* needs to be allocated by the xPrepare() caller, one struct per IO */ +typedef struct agsaFastCBBuf_s +{ + void *cb; + void *cbArg; + void *pSenseData; + bit8 *senseLen; + /* internal */ + void *oneDeviceData; /* tdsaDeviceData_t */ +} agsaFastCBBuf_t; + +typedef struct agsaFastCommand_s +{ + /* in */ + void *agRoot; + /* modified by TD tiFastPrepare() */ + void *devHandle; /* agsaDevHandle_t* */ + void *agSgl; /* agsaSgl_t* */ + bit32 dataLength; + bit32 extDataLength; + bit8 additionalCdbLen; + bit8 *cdb; + bit8 *lun; + /* modified by TD tiFastPrepare() */ + bit8 taskAttribute; /* TD_xxx */ + bit16 flag; /* TLR_MASK */ + bit32 agRequestType; + bit32 queueNum; + agsaFastCBBuf_t *safb; +} agsaFastCommand_t; +#endif + + + +/* Enable test by setting bits in gFPGA_TEST */ + +#define EnableFPGA_TEST_ICCcontrol 0x01 +#define EnableFPGA_TEST_ReadDEV 0x02 +#define EnableFPGA_TEST_WriteCALAll 0x04 +#define EnableFPGA_TEST_ReconfigSASParams 0x08 +#define EnableFPGA_TEST_LocalPhyControl 0x10 +#define EnableFPGA_TEST_PortControl 0x20 + + +/* +PM8001/PM8008/PM8009/PM8018 sTSDK Low-Level Architecture Specification +SDK2 +3.3 Encryption Status Definitions +Encryption engine generated errors. +Table 7 Encryption Engine Generated Errors +Error Definition +*/ + +/* +PM 1.01 +section 4.26.12.6 Encryption Errors +Table 51 lists initialization errors related to encryption functionality. For information on errors reported +for inbound IOMB commands, refer to the corresponding outbound response sections. The error codes +listed in Table 51 are reported in the Scratchpad 3 Register. +*/ +#define OSSA_ENCRYPT_ENGINE_FAILURE_MASK 0x00FF0000 /* Encrypt Engine failed the BIST Test */ +#define OSSA_ENCRYPT_SEEPROM_NOT_FOUND 0x01 /* SEEPROM is not installed. This condition is reported based on the bootstrap pin setting. */ +#define OSSA_ENCRYPT_SEEPROM_IPW_RD_ACCESS_TMO 0x02 /* SEEPROM access timeout detected while reading initialization password or Allowable Cipher Modes. */ +#define OSSA_ENCRYPT_SEEPROM_IPW_RD_CRC_ERR 0x03 /* CRC Error detected when reading initialization password or Allowable Cipher Modes. */ +#define OSSA_ENCRYPT_SEEPROM_IPW_INVALID 0x04 /* Initialization password read from SEEPROM doesn't match any valid password value. This could also mean SEEPROM is blank. */ +#define OSSA_ENCRYPT_SEEPROM_WR_ACCESS_TMO 0x05 /* access timeout detected while writing initialization password or Allowable Cipher Modes. */ +#define OSSA_ENCRYPT_FLASH_ACCESS_TMO 0x20 /* Timeout while reading flash memory. */ +#define OSSA_ENCRYPT_FLASH_SECTOR_ERASE_TMO 0x21 /* Flash sector erase timeout while writing to flash memory. */ +#define OSSA_ENCRYPT_FLASH_SECTOR_ERASE_ERR 0x22 /* Flash sector erase failure while writing to flash memory. */ +#define OSSA_ENCRYPT_FLASH_ECC_CHECK_ERR 0x23 /* Flash ECC check failure. */ +#define OSSA_ENCRYPT_FLASH_NOT_INSTALLED 0x24 /* Flash memory not installed, this error is only detected in Security Mode B. */ +#define OSSA_ENCRYPT_INITIAL_KEK_NOT_FOUND 0x40 /* Initial KEK is not found in the flash memory. This error is only detected in Security Mode B. */ +#define OSSA_ENCRYPT_AES_BIST_ERR 0x41 /* Built-In Test Failure */ +#define OSSA_ENCRYPT_KWP_BIST_FAILURE 0x42 /* Built-In Test Failed on Key Wrap Engine */ + +/* 0x01:ENC_ERR_SEEPROM_NOT_INSTALLED */ +/* 0x02:ENC_ERR_SEEPROM_IPW_RD_ACCESS_TMO */ +/* 0x03:ENC_ERR_SEEPROM_IPW_RD_CRC_ERR */ +/* 0x04:ENC_ERR_SEEPROM_IPW_INVALID */ +/* 0x05:ENC_ERR_SEEPROM_WR_ACCESS_TMO */ +/* 0x20:ENC_ERR_FLASH_ACCESS_TMO */ +/* 0x21:ENC_ERR_FLASH_SECTOR_ERASE_TMO */ +/* 0x22:ENC_ERR_FLASH_SECTOR_ERASE_FAILURE */ +/* 0x23:ENC_ERR_FLASH_ECC_CHECK_FAILURE */ +/* 0x24:ENC_ERR_FLASH_NOT_INSTALLED */ +/* 0x40:ENC_ERR_INITIAL_KEK_NOT_FOUND */ +/* 0x41:ENC_ERR_AES_BIST_FAILURE */ +/* 0x42:ENC_ERR_KWP_BIST_FAILURE */ + +/* +This field indicates self test failure in DIF engine bits [27:24]. +*/ + +#define OSSA_DIF_ENGINE_FAILURE_MASK 0x0F000000 /* DIF Engine failed the BIST Test */ + +#define OSSA_DIF_ENGINE_0_BIST_FAILURE 0x1 /* DIF Engine 0 failed the BIST Test */ +#define OSSA_DIF_ENGINE_1_BIST_FAILURE 0x2 /* DIF Engine 1 failed the BIST Test */ +#define OSSA_DIF_ENGINE_2_BIST_FAILURE 0x4 /* DIF Engine 2 failed the BIST Test */ +#define OSSA_DIF_ENGINE_3_BIST_FAILURE 0x8 /* DIF Engine 3 failed the BIST Test */ + +#define SA_ROLE_CAPABILITIES_CSP 0x001 +#define SA_ROLE_CAPABILITIES_OPR 0x002 +#define SA_ROLE_CAPABILITIES_SCO 0x004 +#define SA_ROLE_CAPABILITIES_STS 0x008 +#define SA_ROLE_CAPABILITIES_TST 0x010 +#define SA_ROLE_CAPABILITIES_KEK 0x020 +#define SA_ROLE_CAPABILITIES_DEK 0x040 +#define SA_ROLE_CAPABILITIES_IOS 0x080 +#define SA_ROLE_CAPABILITIES_FWU 0x100 +#define SA_ROLE_CAPABILITIES_PRM 0x200 + + +#include "saapi.h" +/*********************************************************************************** + * * + * The LL Layer Functions Declarations end * + * * + ***********************************************************************************/ + +#endif /*__SA_H__ */ diff --git a/sys/dev/pms/RefTisa/sallsdk/api/sa_err.h b/sys/dev/pms/RefTisa/sallsdk/api/sa_err.h new file mode 100644 index 000000000000..096b02160371 --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/api/sa_err.h @@ -0,0 +1,244 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/*******************************************************************************/ +/*! \file sa_err.h + * \brief The file defines the error code constants, defined by LL API + * + * + */ +/******************************************************************************/ + +#ifndef __SA_ERR_H__ +#define __SA_ERR_H__ + +/************************************************************************************ + * * + * Error Code Constants defined for LL Layer starts * + * * + ************************************************************************************/ + +/*********************************************************************************** + * SSP/SMP/SATA IO Completion Status values + ***********************************************************************************/ + +#define OSSA_IO_SUCCESS 0x00 /**< IO completes successfully */ +#define OSSA_IO_ABORTED 0x01 /**< IO aborted */ +#define OSSA_IO_OVERFLOW 0x02 /**< IO overflowed (SSP) */ +#define OSSA_IO_UNDERFLOW 0x03 /**< IO underflowed (SSP) */ +#define OSSA_IO_FAILED 0x04 /**< IO failed */ +#define OSSA_IO_ABORT_RESET 0x05 /**< IO abort because of reset */ +#define OSSA_IO_NOT_VALID 0x06 /**< IO not valid */ +#define OSSA_IO_NO_DEVICE 0x07 /**< IO is for non-existing device */ +#define OSSA_IO_ILLEGAL_PARAMETER 0x08 /**< IO is not supported (SSP) */ +/* The following two error codes 0x09 and 0x0A are not using */ +#define OSSA_IO_LINK_FAILURE 0x09 /**< IO failed because of link failure (SMP) */ +#define OSSA_IO_PROG_ERROR 0x0A /**< IO failed because of program error (SMP) */ + +#define OSSA_IO_DIF_IN_ERROR 0x0B /**< IO failed inbound DIF error (SSP) */ +#define OSSA_IO_DIF_OUT_ERROR 0x0C /**< IO failed outbound DIF error (SSP) */ +#define OSSA_IO_ERROR_HW_TIMEOUT 0x0D /**< SMP request/response failed due to HW timeout (SMP) */ +#define OSSA_IO_XFER_ERROR_BREAK 0x0E /**< IO aborted due to BREAK during connection */ +#define OSSA_IO_XFER_ERROR_PHY_NOT_READY 0x0F /**< IO aborted due to PHY NOT READY during connection*/ +#define OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED 0x10 /**< Open connection error */ +#define OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION 0x11 /**< Open connection error */ +#define OSSA_IO_OPEN_CNX_ERROR_BREAK 0x12 /**< Open connection error */ +#define OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS 0x13 /**< Open connection error */ +#define OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION 0x14 /**< Open connection error */ +#define OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED 0x15 /**< Open connection error */ +#define OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY 0x16 /**< Open connection error */ +#define OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION 0x17 /**< Open connection error */ +/* This error code 0x18 is not used on SPCv */ +#define OSSA_IO_OPEN_CNX_ERROR_UNKNOWN_ERROR 0x18 /**< Open connection error */ +#define OSSA_IO_XFER_ERROR_NAK_RECEIVED 0x19 /**< IO aborted due to transfer error with data NAK received*/ +#define OSSA_IO_XFER_ERROR_ACK_NAK_TIMEOUT 0x1A /**< IO aborted due to transfer error with data ACK/NAK timeout*/ +#define OSSA_IO_XFER_ERROR_PEER_ABORTED 0x1B +#define OSSA_IO_XFER_ERROR_RX_FRAME 0x1C +#define OSSA_IO_XFER_ERROR_DMA 0x1D +#define OSSA_IO_XFER_ERROR_CREDIT_TIMEOUT 0x1E /**< IO aborted due to CREDIT TIMEOUT during data transfer*/ +#define OSSA_IO_XFER_ERROR_SATA_LINK_TIMEOUT 0x1F +#define OSSA_IO_XFER_ERROR_SATA 0x20 + +/* This error code 0x22 is not used on SPCv */ +#define OSSA_IO_XFER_ERROR_ABORTED_DUE_TO_SRST 0x22 +#define OSSA_IO_XFER_ERROR_REJECTED_NCQ_MODE 0x21 +#define OSSA_IO_XFER_ERROR_ABORTED_NCQ_MODE 0x23 +#define OSSA_IO_XFER_OPEN_RETRY_TIMEOUT 0x24 /**< IO OPEN_RETRY_TIMEOUT */ +/* This error code 0x25 is not used on SPCv */ +#define OSSA_IO_XFER_SMP_RESP_CONNECTION_ERROR 0x25 +#define OSSA_IO_XFER_ERROR_UNEXPECTED_PHASE 0x26 +#define OSSA_IO_XFER_ERROR_XFER_RDY_OVERRUN 0x27 +#define OSSA_IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED 0x28 + +#define OSSA_IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT 0x30 +/* The following error code 0x31 and 0x32 are not using (obsolete) */ +#define OSSA_IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK 0x31 +#define OSSA_IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK 0x32 + +#define OSSA_IO_XFER_ERROR_OFFSET_MISMATCH 0x34 +#define OSSA_IO_XFER_ERROR_XFER_ZERO_DATA_LEN 0x35 +#define OSSA_IO_XFER_CMD_FRAME_ISSUED 0x36 +#define OSSA_IO_ERROR_INTERNAL_SMP_RESOURCE 0x37 +#define OSSA_IO_PORT_IN_RESET 0x38 +#define OSSA_IO_DS_NON_OPERATIONAL 0x39 +#define OSSA_IO_DS_IN_RECOVERY 0x3A +#define OSSA_IO_TM_TAG_NOT_FOUND 0x3B +#define OSSA_IO_XFER_PIO_SETUP_ERROR 0x3C +#define OSSA_IO_SSP_EXT_IU_ZERO_LEN_ERROR 0x3D +#define OSSA_IO_DS_IN_ERROR 0x3E +#define OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY 0x3F +#define OSSA_IO_ABORT_IN_PROGRESS 0x40 +#define OSSA_IO_ABORT_DELAYED 0x41 +#define OSSA_IO_INVALID_LENGTH 0x42 +#define OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT 0x43 +#define OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED 0x44 +#define OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO 0x45 +#define OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST 0x46 +#define OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE 0x47 +#define OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED 0x48 +#define OSSA_IO_DS_INVALID 0x49 + +#define OSSA_IO_XFER_READ_COMPL_ERR 0x0050 +/* WARNING: the value is not contiguous from here */ +#define OSSA_IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR 0x0052 +#define OSSA_IO_XFER_ERROR_DMA_ACTIVATE_TIMEOUT 0x0053 +#define OSSA_IO_XFR_ERROR_INTERNAL_CRC_ERROR 0x0054 +#define OSSA_MPI_IO_RQE_BUSY_FULL 0x0055 +#define OSSA_IO_XFER_ERR_EOB_DATA_OVERRUN 0x0056 /* This status is only for Hitach FW */ +#define OSSA_IO_XFR_ERROR_INVALID_SSP_RSP_FRAME 0x0057 +#define OSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED 0x0058 + +#define OSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE 0x1004 + +/*encrypt saSetOperator() response status */ +#define OSSA_MPI_ENC_ERR_CONTROLLER_NOT_IDLE 0x1005 +#define OSSA_MPI_ENC_NVM_MEM_ACCESS_ERR 0x100B + +#ifdef SA_TESTBASE_EXTRA +/* TestBase */ +#define OSSA_IO_HOST_BST_INVALID 0x1005 +#endif /* SA_TESTBASE_EXTRA */ + + +#define OSSA_MPI_ERR_OFFLOAD_RESOURCE_UNAVAILABLE 0x1012 +#define OSSA_MPI_ERR_OFFLOAD_DIF_OR_ENC_NOT_ENABLED 0x1013 +#define OSSA_MPI_ERR_ATAPI_DEVICE_BUSY 0x1024 + +/* Specifies the status of the PHY_START command */ +#define OSSA_MPI_IO_SUCCESS 0x00000000 /* PhyStart operation completed successfully */ +/* Specifies the status of the PHY_STOP command */ +#define OSSA_MPI_ERR_DEVICES_ATTACHED 0x00001046 /* All the devices in a port need to be deregistered if the PHY_STOP is for the last phy. */ +#define OSSA_MPI_ERR_INVALID_PHY_ID 0x00001061 /* identifier specified in the PHY_START command is invalid i.e out of supported range for this product. */ +#define OSSA_MPI_ERR_PHY_ALREADY_STARTED 0x00001063 /* An attempt to start a phy which is already started. */ +#define OSSA_MPI_ERR_PHY_NOT_STARTED 0x00001064 /* An attempt to stop a phy which is not started */ +#define OSSA_MPI_ERR_PHY_SUBOP_NOT_SUPPORTED 0x00001065 /* An attempt to use a sub operation that is not supported */ + +#define OSSA_MPI_ERR_INVALID_ANALOG_TBL_IDX 0x00001067 /* The Analog Setup Table Index used in the PHY_START command in invalid. */ +#define OSSA_MPI_ERR_PHY_PROFILE_PAGE_NOT_SUPPORTED 0x00001068 /* Unsupported profile page code specified in the GET_PHY_PROFILE Command */ +#define OSSA_MPI_ERR_PHY_PROFILE_PAGE_NOT_FOUND 0x00001069 /* Unsupported profile page code specified in the GET_PHY_PROFILE Command */ + +#define OSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS 0x2040 +/* + An encryption IO request failed due to DEK Key Tag mismatch. + The key tag supplied in the encryption IOMB does not match with the Key Tag in the referenced DEK Entry. +*/ +#define OSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH 0x2041 +#define OSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID 0x2042 +/* + An encryption I/O request failed + because the initial value (IV) in the unwrapped DEK blob didn't match the IV used to unwrap it. +*/ +#define OSSA_IO_XFR_ERROR_DEK_IV_MISMATCH 0x2043 +/* An encryption I/O request failed due to an internal RAM ECC or interface error while unwrapping the DEK. */ +#define OSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR 0x2044 +/* An encryption I/O request failed due to an internal RAM ECC or interface error while unwrapping the DEK. */ +#define OSSA_IO_XFR_ERROR_INTERNAL_RAM 0x2045 +/* + An encryption I/O request failed + because the DEK index specified in the I/O was outside the bounds of thetotal number of entries in the host DEK table. +*/ +#define OSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS 0x2046 +#define OSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE 0x2047 + +#define OSSA_MPI_ENC_ERR_UNSUPPORTED_OPTION 0x2080 +#define OSSA_MPI_ENC_ERR_ID_TRANSFER_FAILURE 0x2081 + +#define OSSA_MPI_ENC_OPERATOR_AUTH_FAILURE 0x2090 +#define OSSA_MPI_ENC_OPERATOR_OPERATOR_ALREADY_LOGGED_IN 0x2091 +#define OSSA_MPI_ENC_OPERATOR_ILLEGAL_PARAMETER 0x2092 + +/* define DIF IO response error status code */ +#define OSSA_IO_XFR_ERROR_DIF_MISMATCH 0x3000 +#define OSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH 0x3001 +#define OSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH 0x3002 +#define OSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH 0x3003 +#define OSSA_IO_XFER_ERROR_DIF_INTERNAL_ERROR 0x3004 + +#define OSSA_MPI_ERR_DIF_IS_NOT_ENABLED /* Indicates that saPCIeDiagExecute() is + * called with DIF but DIF is not enabled. + */ +/* define operator management response status and error qualifier code */ +#define OPR_MGMT_OP_NOT_SUPPORTED 0x2060 +#define OPR_MGMT_MPI_ENC_ERR_OPR_PARAM_ILLEGAL 0x2061 +#define OPR_MGMT_MPI_ENC_ERR_OPR_ID_NOT_FOUND 0x2062 +#define OPR_MGMT_MPI_ENC_ERR_OPR_ROLE_NOT_MATCH 0x2063 +#define OPR_MGMT_MPI_ENC_ERR_OPR_MAX_NUM_EXCEEDED 0x2064 +#define OPR_MGMT_MPI_ENC_ERR_KEK_UNWRAP_FAIL 0x2022 +#define OPR_MGMT_MPI_ENC_ERR_NVRAM_OPERATION_FAILURE 0x2023 + +/* When Status is 0x2061 */ +#define OPR_MGMT_ERR_QLFR_ILLEGAL_AUTHENTICATIONKEK_INDEX 0x1 +#define OPR_MGMT_ERR_QLFR_ILLEGAL_OPERATOR 0x2 +#define OPR_MGMT_ERR_QLFR_ILLEGAL_KEK_FORMAT 0x3 +#define OPR_MGMT_ERR_QLFR_WRONG_ROLE 0x4 + +/* When status is 0x2090 */ +/* invalid certificate: the certificate can not be unwrapped successfully by existing operators's KEKs */ +#define OPR_SET_ERR_QLFR_INVALID_CERT 0x01 +/* role mismatch: the role from the certificate doesn't match the one inside the controller. */ +#define OPR_SET_ERR_QLFR_ROLE_MISMATCH 0x02 +/* ID mismatch: the ID string from the certificate doesn't match the one inside the controller. */ +#define OPR_SET_ERR_QLFR_ID_MISMATCH 0x03 +/* When status is 0x2092 */ +/* invalid OPRIDX */ +#define OPR_SET_ERR_QLFR_INVALID_OPRIDX 0x04 +/* invalid access type */ +#define OPR_SET_ERR_QLFR_INVALID_ACCESS_TYPE 0x05 + +/* WARNING: This error code must always be the last number. + * If you add error code, modify this code also + * It is used as an index + */ + +/* SAS Reconfiguration error */ +#define OSSA_CONTROLLER_NOT_IDLE 0x1 +#define OSSA_INVALID_CONFIG_PARAM 0x2 + + +/************************************************************************************ + * * + * Constants defined for OS Layer ends * + * * + ************************************************************************************/ + +#endif /*__SA_ERR_H__ */ diff --git a/sys/dev/pms/RefTisa/sallsdk/api/sa_spec.h b/sys/dev/pms/RefTisa/sallsdk/api/sa_spec.h new file mode 100644 index 000000000000..39a14b956d26 --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/api/sa_spec.h @@ -0,0 +1,1194 @@ +/****************************************************************************** +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +******************************************************************************/ +/*****************************************************************************/ +/*! \file sa_spec.h + * \brief The file defines the constants defined by sas spec + */ + +/*****************************************************************************/ + +#ifndef __SA_SPEC_H__ +#define __SA_SPEC_H__ + +/**************************************************************** + * SAS Specification related defines * + ****************************************************************/ +#define SA_SAS_PROTOCOL_SMP 0x00 +#define SA_SAS_PROTOCOL_SSP 0x01 +#define SA_SAS_PROTOCOL_STP 0x02 + +#define SA_OPENFRM_SIZE (28) +#define SA_IDENTIFY_FRAME_SIZE (28) +//#define SAS_IDENTIFY_FRM_SIZE SA_IDENTIFY_FRAME_SIZE + +#define SA_SAS_FRAME_TYPE_SSP_DATA 0x01 +#define SA_SAS_FRAME_TYPE_SSP_XRDY 0x05 +#define SA_SAS_FRAME_TYPE_SSP_CMD 0x06 +#define SA_SAS_FRAME_TYPE_SSP_RSP 0x07 +#define SA_SAS_FRAME_TYPE_SSP_TASK 0x16 +#define SA_SAS_FRAME_TYPE_SMP_REQ 0x40 +#define SA_SAS_FRAME_TYPE_SMP_RSP 0x41 + +#define SA_SAS_CONNECTION_RATE_1_5G 0x08 +#define SA_SAS_CONNECTION_RATE_3_0G 0x09 +#define SA_SAS_CONNECTION_RATE_6_0G 0x0A +#define SA_SAS_CONNECTION_RATE_12_0G 0x0B + +#define SA_SAS_DEV_TYPE_NO_DEVICE 0x00 +#define SA_SAS_DEV_TYPE_END_DEVICE 0x01 +#define SA_SAS_DEV_TYPE_EDGE_EXPANDER 0x02 +#define SA_SAS_DEV_TYPE_FANOUT_EXPANDER 0x03 + +#define AGSA_DEV_TYPE_END_DEVICE (SA_SAS_DEV_TYPE_END_DEVICE << 4) +#define AGSA_DEV_TYPE_EDGE_EXPANDER (SA_SAS_DEV_TYPE_EDGE_EXPANDER << 4) +#define AGSA_DEV_TYPE_FAN_EXPANDER (SA_SAS_DEV_TYPE_FANOUT_EXPANDER << 4) + +#define SA_SAS_SMP_REPORT_GENERAL 0x00 +#define SA_SAS_SMP_REPORT_MANUFACTURE_INFORMATION 0x01 +#define SA_SAS_SMP_READ_GPIO_REGISTER 0x02 +#define SA_SAS_SMP_DISCOVER 0x10 +#define SA_SAS_SMP_REPORT_PHY_ERROR_LOG 0x11 +#define SA_SAS_SMP_REPORT_PHY_SATA 0x12 +#define SA_SAS_SMP_REPORT_ROUTING_INFORMATION 0x13 +#define SA_SAS_SMP_WRITE_GPIO_REGISTER 0x82 +#define SA_SAS_SMP_CONFIGURE_ROUTING_INFORMATION 0x90 +#define SA_SAS_SMP_PHY_CONTROL 0x91 +#define SA_SAS_SMP_PHY_TEST 0x92 + +#define SA_SAS_SMP_FUNCTION_ACCEPTED 0x00 +#define SA_SAS_SMP_FUNCTION_UNKNOWN 0x01 +#define SA_SAS_SMP_FUNCTION_FAILED 0x02 +#define SA_SAS_SMP_INVALID_REQ_FRAME_LENGTH 0x03 +#define SA_SAS_SMP_PHY_NOT_EXIST 0x10 + +#define SA_SAS_ROUTING_DIRECT 0x00 +#define SA_SAS_ROUTING_SUBTRACTIVE 0x01 +#define SA_SAS_ROUTING_TABLE 0x02 + +#define SA_SAS_PHYCTL_LINK_RESET 0x01 +#define SA_SAS_PHYCTL_HARD_RESET 0x02 +#define SA_SAS_PHYCTL_DISABLE 0x03 +#define SA_SAS_PHYCTL_CLEAR_ERROR_LOG 0x05 +#define SA_SAS_PHYCTL_CLEAR_AFFILIATION 0x06 +#define SA_SAS_PHYCTL_TRANSMIT_PS_SIGNAL 0x07 + +#define SA_SSP_CMDIU_LEN_BYTES 28 +#define SA_SSP_TMIU_LEN_BYTES 28 + + +#define SASD_DEV_SATA_MASK 0xF0 +#define SASD_DEV_SAS_MASK 0x0F + +#define SASD_DEV_SAS_END_DEVICE 0x01 /* SAS end device type */ +#define SASD_DEV_SAS_EDGE_EXPANDER 0x02 /* SAS edge expander device type */ +#define SASD_DEV_SAS_FAN_EXPANDER 0x03 /* SAS fan out expander device type */ + +#define SASD_DEV_SATA_ATA_DEVICE 0x10 /* SATA ATA device type */ +#define SASD_DEV_SATA_ATAPI_DEVICE 0x20 /* SATA ATAPI device type */ +#define SASD_DEV_SATA_PM_DEVICE 0x30 /* SATA PM device type */ +#define SASD_DEV_SATA_SEMB_DEVICE 0x40 /* SATA SEMB device type */ +#define SASD_DEV_SATA_SEMB_WO_SEP_DEVICE 0x50 /* SATA SEMB without SEP device type */ + +#define SASD_DEV_SATA_UNKNOWN_DEVICE 0xFF /* SAS SATA unknown device type */ + + +#define SASD_TASK_ATTR_SIMPLE 0x0 +#define SASD_TASK_ATTR_HEAD_OF_QUEUE 0x1 +#define SASD_TASK_ATTR_ORDERED 0x2 +#define SASD_TASK_ATTR_ACA 0x4 + + +/***************************************************************************** +** SAS TM Function definitions +*****************************************************************************/ +#define SASD_SAS_ABORT_TASK 0x01 +#define SASD_SAS_ABORT_TASK_SET 0x02 +#define SASD_SAS_CLEAR_TASK_SET 0x04 +#define SASD_SAS_LOGICAL_UNIT_RESET 0x08 +#define SASD_SAS_CLEAR_ACA 0x40 +#define SASD_SAS_QUARY_TASK 0x80 + +/**************************************************************** + * SATA Specification related defines * + ****************************************************************/ +#define SA_SATA_MAX_QUEUED_COMMANDS 32 +#define SA_SATA_MAX_PM_PORTS 15 + +#define SA_SATA_FIS_TYPE_HOST_2_DEV 0x27 +#define SA_SATA_FIS_TYPE_DEV_2_HOST 0x34 +#define SA_SATA_FIS_TYPE_SET_DEVICE 0xA1 +#define SA_SATA_FIS_TYPE_DMA_ACTIVE 0x39 +#define SA_SATA_FIS_TYPE_FDMA_SETUP 0x41 +#define SA_SATA_FIS_TYPE_BIST 0x58 + +#define SA_SATA_CMD_IDENTIFY_DEVICE 0xEC +#define SA_SATA_CMD_EXEC_DEV_DIAG 0x90 + +#define SA_SATA_CONTROL_SRST 0x04 + +#define SA_SATA_H2DREG_LEN_BYTES 20 +#define SA_SATA_H2D_BIST_LEN_BYTES 12 +/**************************************************************** + * SAS Specification related structures * + ****************************************************************/ + + + +/** \brief Structure for SATA BIST FIS + * + * The agsaFisBIST_t data structure describes a SATA FIS (Frame Information Structures) + * for FIS type BIST (Built In Self Test) Activate Bidirectional. + * + * This data structure is one instance of the SATA request structure agsaSATAInitiatorRequest_t, + * which is one instance of the generic request, issued to saSATAStart(). + */ + + +#define SA_SATA_BIST_PATTERN_T_BIT 0x80 +#define SA_SATA_BIST_PATTERN_A_BIT 0x40 +#define SA_SATA_BIST_PATTERN_S_BIT 0x20 +#define SA_SATA_BIST_PATTERN_L_BIT 0x10 +#define SA_SATA_BIST_PATTERN_F_BIT 0x08 +#define SA_SATA_BIST_PATTERN_P_BIT 0x04 +#define SA_SATA_BIST_PATTERN_R_BIT 0x02 +#define SA_SATA_BIST_PATTERN_V_BIT 0x01 + +/* + * The first SATA DWORD types. + */ +typedef struct agsaFisBISTHeader_s +{ + bit8 fisType; /* fisType, set to 58h for BIST */ + bit8 pmPort; + /* b7-b4 reserved */ + /* b3-b0 PM Port. device port address that the PM should deliver the FIS to */ + bit8 patternDefinition; + /* b7 : T Far end transmit only mode */ + /* b6 : A ALIGN Bypass (Do not Transmit Align Primitives) (valid only in combination with T Bit) (optional behavior) */ + /* b5 : S Bypass Scrambling (valid only in combination with T Bit) (optional behavior) */ + /* b4 : L Far End Retimed Loopback. Transmitter shall insert additional ALIGNS) */ + /* b3 : F Far End Analog (AFE) Loopback (Optional) */ + /* b2 : P Primitive bit. (valid only in combination with the T Bit) (optional behavior) */ + /* b1 : R Reserved */ + /* b0 : V Vendor Specific Test Mode. Causes all other bits to be ignored */ + bit8 reserved5; /* Reserved */ +} agsaFisBISTHeader_t; + + +typedef struct agsaFisRegD2HHeader_s +{ + bit8 fisType; /* fisType, set to 34h for DeviceToHostReg */ + bit8 i_pmPort; + /* b7 : reserved */ + /* b6 : I Interrupt bit */ + /* b5-b4 : reserved */ + /* b3-b0 : PM Port */ + bit8 status; /* Contains the contents to be placed in the Status(and Alternate status) + Register of the Shadow Command Block */ + bit8 error; /* Contains the contents to be placed in the Error register of the Shadow Command Block */ +} agsaFisRegD2HHeader_t; + +typedef struct agsaFisSetDevBitsHeader_s +{ + bit8 fisType; /* fisType, set to A1h for SetDeviceBit */ + bit8 n_i_pmPort; + /* b7 : n Bit. Notification bit. If set device needs attention. */ + /* b6 : i Bit. Interrupt Bit */ + /* b5-b4: reserved2 */ + /* b3-b0: PM Port */ + bit8 statusHi_Lo; + /* b7 : reserved */ + /* b6-b4: Status Hi. Contains the contents to be placed in bits 6, 5, and 4 of + the Status register of the Shadow Command Block */ + /* b3 : Reserved */ + /* b2-b0: Status Lo Contains the contents to be placed in bits 2,1, and 0 of the + Status register of the Shadow Command Block */ + bit8 error; /* Contains the contents to be placed in the Error register of + the Shadow Command Block */ +} agsaFisSetDevBitsHeader_t; + +typedef struct agsaFisRegH2DHeader_s +{ + bit8 fisType; /* fisType, set to 27h for DeviceToHostReg */ + bit8 c_pmPort; + /* b7 : C_bit This bit is set to one when the register transfer is + due to an update of the Command register */ + /* b6-b4: reserved */ + /* b3-b0: PM Port */ + bit8 command; /* Contains the contents of the Command register of + the Shadow Command Block */ + bit8 features; /* Contains the contents of the Features register of + the Shadow Command Block */ +} agsaFisRegH2DHeader_t; + +typedef struct agsaFisPioSetupHeader_s +{ + bit8 fisType; /* set to 5F */ + bit8 i_d_pmPort; + /* b7 : reserved */ + /* b6 : i bit. Interrupt bit */ + /* b5 : d bit. data transfer direction. set to 1 for device to host xfer */ + /* b4 : reserved */ + /* b3-b0: PM Port */ + bit8 status; + bit8 error; +} agsaFisPioSetupHeader_t; + +typedef union agsaFisHeader_s +{ + agsaFisBISTHeader_t Bist; + agsaFisRegD2HHeader_t D2H; + agsaFisRegH2DHeader_t H2D; + agsaFisSetDevBitsHeader_t SetDevBits; + agsaFisPioSetupHeader_t PioSetup; +} agsaFisHeader_t; + + +typedef struct agsaFisBISTData_s +{ + bit8 data[8]; /* BIST data */ +} agsaFisBISTData_t; + + +typedef struct agsaFisBIST_s +{ + agsaFisBISTHeader_t h; + agsaFisBISTData_t d; +} agsaFisBIST_t; + +/** \brief Structure for SATA Device to Host Register FIS + * + * The agsaFisRegDeviceToHost_t data structure describes a SATA FIS (Frame Information + * Structures) for FIS type Register Device to Host. + * + * This structure is used only as inbound data (device to host) to describe device to + * host response. + */ + +#define SA_SATA_RD2H_I_BIT 0x40 + +typedef struct agsaFisRegD2HData_s +{ + bit8 lbaLow; /* Contains the contents to be placed in the LBA Low register + of the Shadow Command Block */ + bit8 lbaMid; /* Contains the contents to be placed in the LBA Mid register + of the Shadow Command Block */ + + bit8 lbaHigh; /* Contains the contents to be placed in the LBA High register + of the Shadow Command Block */ + bit8 device; /* Contains the contents to be placed in the Device register of the Shadow Command Block */ + + bit8 lbaLowExp; /* Contains the contents of the expanded address field + of the Shadow Command Block */ + bit8 lbaMidExp; /* Contains the contents of the expanded address field + of the Shadow Command Block */ + bit8 lbaHighExp; /* Contains the contents of the expanded address field + of the Shadow Command Block */ + bit8 reserved4; /** reserved */ + + bit8 sectorCount; /* Contains the contents to be placed in the Sector + Count register of the Shadow Command Block */ + bit8 sectorCountExp; /* Contains the contents of the expanded address + field of the Shadow Command Block */ + bit8 reserved6; /* Reserved */ + bit8 reserved5; /* Reserved */ + bit32 reserved7; /* Reserved */ +} agsaFisRegD2HData_t; + + +typedef struct agsaFisRegDeviceToHost_s +{ + agsaFisRegD2HHeader_t h; + agsaFisRegD2HData_t d; +} agsaFisRegDeviceToHost_t; + + + +/** \brief Structure for SATA Host to Device Register FIS + * + * The agsaFisRegHostToDevice_t data structure describes a SATA FIS + * (Frame Information Structures) for FIS type Register Host to Device. + + * This data structure is one instance of the SATA request structure + * agsaSATAInitiatorRequest_t, which is one instance of the generic request, + * issued to saSATAStart(). + */ +typedef struct agsaFisRegH2DData_s +{ + bit8 lbaLow; /* Contains the contents of the LBA Low register of the Shadow Command Block */ + bit8 lbaMid; /* Contains the contents of the LBA Mid register of the Shadow Command Block */ + bit8 lbaHigh; /* Contains the contents of the LBA High register of the Shadow Command Block */ + bit8 device; /* Contains the contents of the Device register of the Shadow Command Block */ + + bit8 lbaLowExp; /* Contains the contents of the expanded address field of the + Shadow Command Block */ + bit8 lbaMidExp; /* Contains the contents of the expanded address field of the + Shadow Command Block */ + bit8 lbaHighExp; /* Contains the contents of the expanded address field of the + Shadow Command Block */ + bit8 featuresExp; /* Contains the contents of the expanded address field of the + Shadow Command Block */ + + bit8 sectorCount; /* Contains the contents of the Sector Count register of the + Shadow Command Block */ + bit8 sectorCountExp; /* Contains the contents of the expanded address field of + the Shadow Command Block */ + bit8 reserved4; /* Reserved */ + bit8 control; /* Contains the contents of the Device Control register of the + Shadow Command Block */ + bit32 reserved5; /* Reserved */ +} agsaFisRegH2DData_t; + +typedef struct agsaFisRegHostToDevice_s +{ + agsaFisRegH2DHeader_t h; + agsaFisRegH2DData_t d; +} agsaFisRegHostToDevice_t; + + +/** \brief Structure for SATA SetDeviceBit FIS + * + * The agsaFisSetDevBits_t data structure describes a SATA FIS (Frame Information Structures) + * for FIS type Set Device Bits - Device to Host. + * + * This structure is used only as inbound data (device to host) to describe device to host + * response. + */ +typedef struct agsaFisSetDevBitsData_s +{ + bit32 reserved6; /* Reserved */ +} agsaFisSetDevBitsData_t; + + +typedef struct agsaFisSetDevBits_s +{ + agsaFisSetDevBitsHeader_t h; + agsaFisSetDevBitsData_t d; +} agsaFisSetDevBits_t; + + +/** \brief union data structure specifies a FIS from host software + * + * union data structure specifies a FIS from host software + */ +typedef union agsaSATAHostFis_u +{ + agsaFisRegHostToDevice_t fisRegHostToDev; /* Structure containing the FIS request + for Register - Host to Device */ + agsaFisBIST_t fisBIST; /* Structure containing the FIS request for BIST */ +} agsaSATAHostFis_t; + +/** \brief + * + * This structure is used + * + */ +typedef struct agsaFisPioSetupData_s +{ + bit8 lbaLow; /* Contains the contents of the LBA Low register of the Shadow Command Block */ + bit8 lbaMid; /* Contains the contents of the LBA Mid register of the Shadow Command Block */ + bit8 lbaHigh; /* Contains the contents of the LBA High register of the Shadow Command Block */ + bit8 device; /* Contains the contents of the Device register of the Shadow Command Block */ + + bit8 lbaLowExp; /* Contains the contents of the expanded address field of the + Shadow Command Block */ + bit8 lbaMidExp; /* Contains the contents of the expanded address field of the + Shadow Command Block */ + bit8 lbaHighExp; /* Contains the contents of the expanded address field of the + Shadow Command Block */ + bit8 reserved1; /* reserved */ + + bit8 sectorCount; /* Contains the contents of the Sector Count register of the + Shadow Command Block */ + bit8 sectorCountExp; /* Contains the contents of the expanded address field of + the Shadow Command Block */ + bit8 reserved2; /* Reserved */ + bit8 e_status; /* Contains the new value of Status Reg of the Command block + at the conclusion of the subsequent Data FIS */ + bit8 reserved4[2]; /* Reserved */ + bit8 transferCount[2]; /* the number of bytes to be xfered in the subsequent Data FiS */ +} agsaFisPioSetupData_t; + + +typedef struct agsaFisPioSetup_s +{ + agsaFisPioSetupHeader_t h; + agsaFisPioSetupData_t d; +} agsaFisPioSetup_t; + + + +/** \brief describe SAS IDENTIFY address frame + * + * describe SAS IDENTIFY address frame, the CRC field is not included in the structure + * + */ +typedef struct agsaSASIdentify_s +{ + bit8 deviceType_addressFrameType; + /* b7 : reserved */ + /* b6-4 : device type */ + /* b3-0 : address frame type */ + bit8 reason; /* reserved */ + /* b7-4 : reserved */ + /* b3-0 : reason SAS2 */ + bit8 initiator_ssp_stp_smp; + /* b8-4 : reserved */ + /* b3 : SSP initiator port */ + /* b2 : STP initiator port */ + /* b1 : SMP initiator port */ + /* b0 : reserved */ + bit8 target_ssp_stp_smp; + /* b8-4 : reserved */ + /* b3 : SSP target port */ + /* b2 : STP target port */ + /* b1 : SMP target port */ + /* b0 : reserved */ + bit8 deviceName[8]; /* reserved */ + + bit8 sasAddressHi[4]; /* BE SAS address Lo */ + bit8 sasAddressLo[4]; /* BE SAS address Hi */ + + bit8 phyIdentifier; /* phy identifier of the phy transmitting the IDENTIFY address frame */ + bit8 zpsds_breakReplyCap; + /* b7-3 : reserved */ + /* b2 : Inside ZPSDS Persistent */ + /* b1 : Requested Inside ZPSDS */ + /* b0 : Break Reply Capable */ + bit8 reserved3[6]; /* reserved */ +} agsaSASIdentify_t; + +#define SA_IDFRM_GET_SAS_ADDRESSLO(identFrame) \ + DMA_BEBIT32_TO_BIT32(*(bit32 *)(identFrame)->sasAddressLo) + +#define SA_IDFRM_GET_SAS_ADDRESSHI(identFrame) \ + DMA_BEBIT32_TO_BIT32(*(bit32 *)(identFrame)->sasAddressHi) + +#define SA_IDFRM_GET_DEVICETTYPE(identFrame) \ + (((identFrame)->deviceType_addressFrameType & 0x70) >> 4) + +#define SA_IDFRM_PUT_SAS_ADDRESSLO(identFrame, src32) \ + ((*(bit32 *)((identFrame)->sasAddressLo)) = BIT32_TO_DMA_BEBIT32(src32)) + +#define SA_IDFRM_PUT_SAS_ADDRESSHI(identFrame, src32) \ + ((*(bit32 *)((identFrame)->sasAddressHi)) = BIT32_TO_DMA_BEBIT32(src32)) + +#define SA_IDFRM_SSP_BIT 0x8 /* SSP Initiator port */ +#define SA_IDFRM_STP_BIT 0x4 /* STP Initiator port */ +#define SA_IDFRM_SMP_BIT 0x2 /* SMP Initiator port */ +#define SA_IDFRM_SATA_BIT 0x1 /* SATA device, valid in the discovery response only */ + + +#define SA_IDFRM_IS_SSP_INITIATOR(identFrame) \ + (((identFrame)->initiator_ssp_stp_smp & SA_IDFRM_SSP_BIT) == SA_IDFRM_SSP_BIT) + +#define SA_IDFRM_IS_STP_INITIATOR(identFrame) \ + (((identFrame)->initiator_ssp_stp_smp & SA_IDFRM_STP_BIT) == SA_IDFRM_STP_BIT) + +#define SA_IDFRM_IS_SMP_INITIATOR(identFrame) \ + (((identFrame)->initiator_ssp_stp_smp & SA_IDFRM_SMP_BIT) == SA_IDFRM_SMP_BIT) + +#define SA_IDFRM_IS_SSP_TARGET(identFrame) \ + (((identFrame)->target_ssp_stp_smp & SA_IDFRM_SSP_BIT) == SA_IDFRM_SSP_BIT) + +#define SA_IDFRM_IS_STP_TARGET(identFrame) \ + (((identFrame)->target_ssp_stp_smp & SA_IDFRM_STP_BIT) == SA_IDFRM_STP_BIT) + +#define SA_IDFRM_IS_SMP_TARGET(identFrame) \ + (((identFrame)->target_ssp_stp_smp & SA_IDFRM_SMP_BIT) == SA_IDFRM_SMP_BIT) + +#define SA_IDFRM_IS_SATA_DEVICE(identFrame) \ + (((identFrame)->target_ssp_stp_smp & SA_IDFRM_SATA_BIT) == SA_IDFRM_SATA_BIT) + +/** \brief data structure provides the identify data of the SATA device + * + * data structure provides the identify data of the SATA device + * + */ +typedef struct agsaSATAIdentifyData_s +{ + bit16 rm_ataDevice; + /* b15-b9 : */ + /* b8 : ataDevice */ + /* b7-b1 : */ + /* b0 : removableMedia */ + bit16 word1_9[9]; /**< word 1 to 9 of identify device information */ + bit8 serialNumber[20]; /**< word 10 to 19 of identify device information, 20 ASCII chars */ + bit16 word20_22[3]; /**< word 20 to 22 of identify device information */ + bit8 firmwareVersion[8]; /**< word 23 to 26 of identify device information, 4 ASCII chars */ + bit8 modelNumber[40]; /**< word 27 to 46 of identify device information, 40 ASCII chars */ + bit16 word47_48[2]; /**< word 47 to 48 of identify device information, 40 ASCII chars */ + bit16 dma_lba_iod_ios_stimer; + /* b15-b14:word49_bit14_15 */ + /* b13 : standbyTimerSupported */ + /* b12 : word49_bit12 */ + /* b11 : IORDYSupported */ + /* b10 : IORDYDisabled */ + /* b9 : lbaSupported */ + /* b8 : dmaSupported */ + /* b7-b0 : retired */ + bit16 word50_52[3]; /**< word 50 to 52 of identify device information, 40 ASCII chars */ + bit16 valid_w88_w70; + /* b15-3 : word53_bit3_15 */ + /* b2 : validWord88 */ + /* b1 : validWord70_64 */ + /* b0 : word53_bit0 */ + bit16 word54_59[6]; /**< word54-59 of identify device information */ + bit16 numOfUserAddressableSectorsLo; /**< word60 of identify device information */ + bit16 numOfUserAddressableSectorsHi; /**< word61 of identify device information */ + bit16 word62_74[13]; /**< word62-74 of identify device information */ + bit16 queueDepth; + /* b15-5 : word75_bit5_15 */ + /* b4-0 : queueDepth */ + bit16 sataCapabilities; + /* b15-b11: word76_bit11_15 */ + /* b10 : phyEventCountersSupport */ + /* b9 : hostInitPowerMangment */ + /* b8 : nativeCommandQueuing */ + /* b7-b3 : word76_bit4_7 */ + /* b2 : sataGen2Supported (3.0 Gbps) */ + /* b1 : sataGen1Supported (1.5 Gbps) */ + /* b0 :word76_bit0 */ + bit16 word77; /**< word77 of identify device information */ + /* b15-b6 : word77 bit6_15, Reserved */ + /* b5 : DMA Setup Auto-Activate support */ + /* b4 : NCQ streaming support */ + /* b3-b1 : coded value indicating current negotiated SATA signal speed */ + /* b0 : shall be zero */ + bit16 sataFeaturesSupported; + /* b15-b7 : word78_bit7_15 */ + /* b6 : softSettingPreserveSupported */ + /* b5 : word78_bit5 */ + /* b4 : inOrderDataDeliverySupported */ + /* b3 : devInitPowerManagementSupported */ + /* b2 : autoActiveDMASupported */ + /* b1 : nonZeroBufOffsetSupported */ + /* b0 : word78_bit0 */ + bit16 sataFeaturesEnabled; + /* b15-7 : word79_bit7_15 */ + /* b6 : softSettingPreserveEnabled */ + /* b5 : word79_bit5 */ + /* b4 : inOrderDataDeliveryEnabled */ + /* b3 : devInitPowerManagementEnabled */ + /* b2 : autoActiveDMAEnabled */ + /* b1 : nonZeroBufOffsetEnabled */ + /* b0 : word79_bit0 */ + bit16 majorVersionNumber; + /* b15 : word80_bit15 */ + /* b14 : supportATA_ATAPI14 */ + /* b13 : supportATA_ATAPI13 */ + /* b12 : supportATA_ATAPI12 */ + /* b11 : supportATA_ATAPI11 */ + /* b10 : supportATA_ATAPI10 */ + /* b9 : supportATA_ATAPI9 */ + /* b8 : supportATA_ATAPI8 */ + /* b7 : supportATA_ATAPI7 */ + /* b6 : supportATA_ATAPI6 */ + /* b5 : supportATA_ATAPI5 */ + /* b4 : supportATA_ATAPI4 */ + /* b3 : supportATA3 */ + /* b2-0 : word80_bit0_2 */ + bit16 minorVersionNumber; /**< word81 of identify device information */ + bit16 commandSetSupported; + /* b15 : word82_bit15 */ + /* b14 : NOPSupported */ + /* b13 : READ_BUFFERSupported */ + /* b12 : WRITE_BUFFERSupported */ + /* b11 : word82_bit11 */ + /* b10 : hostProtectedAreaSupported */ + /* b9 : DEVICE_RESETSupported */ + /* b8 : SERVICEInterruptSupported */ + /* b7 : releaseInterruptSupported */ + /* b6 : lookAheadSupported */ + /* b5 : writeCacheSupported */ + /* b4 : word82_bit4 */ + /* b3 : mandPowerManagmentSupported */ + /* b2 : removableMediaSupported */ + /* b1 : securityModeSupported */ + /* b0 : SMARTSupported */ + bit16 commandSetSupported1; + /* b15-b14: word83_bit14_15 */ + /* b13 : FLUSH_CACHE_EXTSupported */ + /* b12 : mandatoryFLUSH_CACHESupported */ + /* b11 : devConfOverlaySupported */ + /* b10 : address48BitsSupported */ + /* b9 : autoAcousticManageSupported */ + /* b8 : SET_MAX_SecurityExtSupported */ + /* b7 : word83_bit7 */ + /* b6 : SET_FEATUREReqSpinupSupported */ + /* b5 : powerUpInStandyBySupported */ + /* b4 : removableMediaStNotifSupported */ + /* b3 : advanPowerManagmentSupported */ + /* b2 : CFASupported */ + /* b1 : DMAQueuedSupported */ + /* b0 : DOWNLOAD_MICROCODESupported */ + bit16 commandSetFeatureSupportedExt; + /* b15-b13: word84_bit13_15 */ + /* b12 : timeLimitRWContSupported */ + /* b11 : timeLimitRWSupported */ + /* b10 : writeURGBitSupported */ + /* b9 : readURGBitSupported */ + /* b8 : wwwNameSupported */ + /* b7 : WRITE_DMAQ_FUA_EXTSupported */ + /* b6 : WRITE_FUA_EXTSupported */ + /* b5 : generalPurposeLogSupported */ + /* b4 : streamingSupported */ + /* b3 : mediaCardPassThroughSupported */ + /* b2 : mediaSerialNoSupported */ + /* b1 : SMARTSelfRestSupported */ + /* b0 : SMARTErrorLogSupported */ + bit16 commandSetFeatureEnabled; + /* b15 : word85_bit15 */ + /* b14 : NOPEnabled */ + /* b13 : READ_BUFFEREnabled */ + /* b12 : WRITE_BUFFEREnabled */ + /* b11 : word85_bit11 */ + /* b10 : hostProtectedAreaEnabled */ + /* b9 : DEVICE_RESETEnabled */ + /* b8 : SERVICEInterruptEnabled */ + /* b7 : releaseInterruptEnabled */ + /* b6 : lookAheadEnabled */ + /* b5 : writeCacheEnabled */ + /* b4 : word85_bit4 */ + /* b3 : mandPowerManagmentEnabled */ + /* b2 : removableMediaEnabled */ + /* b1 : securityModeEnabled */ + /* b0 : SMARTEnabled */ + bit16 commandSetFeatureEnabled1; + /* b15-b14: word86_bit14_15 */ + /* b13 : FLUSH_CACHE_EXTEnabled */ + /* b12 : mandatoryFLUSH_CACHEEnabled */ + /* b11 : devConfOverlayEnabled */ + /* b10 : address48BitsEnabled */ + /* b9 : autoAcousticManageEnabled */ + /* b8 : SET_MAX_SecurityExtEnabled */ + /* b7 : word86_bit7 */ + /* b6 : SET_FEATUREReqSpinupEnabled */ + /* b5 : powerUpInStandyByEnabled */ + /* b4 : removableMediaStNotifEnabled */ + /* b3 : advanPowerManagmentEnabled */ + /* b2 : CFAEnabled */ + /* b1 : DMAQueuedEnabled */ + /* b0 : DOWNLOAD_MICROCODEEnabled */ + bit16 commandSetFeatureDefault; + /* b15-b13: word87_bit13_15 */ + /* b12 : timeLimitRWContEnabled */ + /* b11 : timeLimitRWEnabled */ + /* b10 : writeURGBitEnabled */ + /* b9 : readURGBitEnabled */ + /* b8 : wwwNameEnabled */ + /* b7 : WRITE_DMAQ_FUA_EXTEnabled */ + /* b6 : WRITE_FUA_EXTEnabled */ + /* b5 : generalPurposeLogEnabled */ + /* b4 : streamingEnabled */ + /* b3 : mediaCardPassThroughEnabled */ + /* b2 : mediaSerialNoEnabled */ + /* b1 : SMARTSelfRestEnabled */ + /* b0 : SMARTErrorLogEnabled */ + bit16 ultraDMAModes; + /* b15 : word88_bit15 */ + /* b14 : ultraDMAMode6Selected */ + /* b13 : ultraDMAMode5Selected */ + /* b12 : ultraDMAMode4Selected */ + /* b11 : ultraDMAMode3Selected */ + /* b10 : ultraDMAMode2Selected */ + /* b9 : ultraDMAMode1Selected */ + /* b8 : ultraDMAMode0Selected */ + /* b7 : word88_bit7 */ + /* b6 : ultraDMAMode6Supported */ + /* b5 : ultraDMAMode5Supported */ + /* b4 : ultraDMAMode4Supported */ + /* b3 : ultraDMAMode3Supported */ + /* b2 : ultraDMAMode2Supported */ + /* b1 : ultraDMAMode1Supported */ + /* b0 : ultraDMAMode0Supported */ + bit16 timeToSecurityErase; + bit16 timeToEnhhancedSecurityErase; + bit16 currentAPMValue; + bit16 masterPasswordRevCode; + bit16 hardwareResetResult; + /* b15-b14: word93_bit15_14 */ + /* b13 : deviceDetectedCBLIBbelow Vil */ + /* b12-b8 : device1 HardwareResetResult */ + /* b7-b0 : device0 HardwareResetResult */ + bit16 currentAutoAccousticManagementValue; + /* b15-b8 : Vendor recommended value */ + /* b7-b0 : current value */ + bit16 word95_99[5]; /**< word85-99 of identify device information */ + bit16 maxLBA0_15; /**< word100 of identify device information */ + bit16 maxLBA16_31; /**< word101 of identify device information */ + bit16 maxLBA32_47; /**< word102 of identify device information */ + bit16 maxLBA48_63; /**< word103 of identify device information */ + bit16 word104_107[4]; /**< word104-107 of identify device information */ + bit16 namingAuthority; + /* b15-b12: NAA_bit0_3 */ + /* b11-b0 : IEEE_OUI_bit12_23*/ + bit16 namingAuthority1; + /* b15-b4 : IEEE_OUI_bit0_11 */ + /* b3-b0 : uniqueID_bit32_35 */ + bit16 uniqueID_bit16_31; /**< word110 of identify device information */ + bit16 uniqueID_bit0_15; /**< word111 of identify device information */ + bit16 word112_126[15]; + bit16 removableMediaStatusNotificationFeature; + /* b15-b2 : word127_b16_2 */ + /* b1-b0 : supported set see ATAPI6 spec */ + bit16 securityStatus; + /* b15-b9 : word128_b15_9 */ + /* b8 : securityLevel */ + /* b7-b6 : word128_b7_6 */ + /* b5 : enhancedSecurityEraseSupported */ + /* b4 : securityCountExpired */ + /* b3 : securityFrozen */ + /* b2 : securityLocked */ + /* b1 : securityEnabled */ + /* b0 : securitySupported */ + bit16 vendorSpecific[31]; + bit16 cfaPowerMode1; + /* b15 : word 160 supported */ + /* b14 : word160_b14 */ + /* b13 : cfaPowerRequired */ + /* b12 : cfaPowerModeDisabled */ + /* b11-b0 : maxCurrentInMa */ + bit16 word161_175[15]; + bit16 currentMediaSerialNumber[30]; + bit16 word206_254[49]; /**< word206-254 of identify device information */ + bit16 integrityWord; + /* b15-b8 : cheksum */ + /* b7-b0 : signature */ +} agsaSATAIdentifyData_t; + + + + +/** \brief data structure describes an SSP Command INFORMATION UNIT + * + * data structure describes an SSP Command INFORMATION UNIT used for SSP command and is part of + * the SSP frame. + * + * Currently, only CDB up to 16 bytes is supported. Additional CDB length is supported to 0 bytes.. + * + */ +typedef struct agsaSSPCmdInfoUnit_s +{ + bit8 lun[8]; /* SCSI Logical Unit Number */ + bit8 reserved1; /* reserved */ + bit8 efb_tp_taskAttribute; + /* B7 : enabledFirstBurst */ + /* B6-3 : taskPriority */ + /* B2-0 : taskAttribute */ + bit8 reserved2; /* reserved */ + bit8 additionalCdbLen; + /* B7-2 : additionalCdbLen */ + /* B1-0 : reserved */ + bit8 cdb[16]; /* The SCSI CDB up to 16 bytes length */ +} agsaSSPCmdInfoUnit_t; + +#define SA_SSPCMD_GET_TASKATTRIB(pCmd) ((pCmd)->efb_tp_taskAttribute & 0x7) + + +/** \brief structure describes an SSP Response INFORMATION UNIT + * + * data structure describes an SSP Response INFORMATION UNIT used for SSP response to Command IU + * or Task IU and is part of the SSP frame + * + */ + +typedef struct agsaSSPResponseInfoUnit_s +{ + bit8 reserved1[10]; /* reserved */ + + bit8 dataPres; /* which data is present */ + /* B7-2 : reserved */ + /* B1-0 : data Present */ + bit8 status; /* SCSI status as define by SAM-3 */ + bit8 reserved4[4]; /* reserved */ + bit8 senseDataLen[4]; /* SCSI Sense Data length */ + bit8 responsedataLen[4]; /* Response data length */ + /* Follow by Response Data if any */ + /* Follow by Sense Data if any */ +} agsaSSPResponseInfoUnit_t; + + +typedef struct agsaSSPFrameFormat_s +{ + bit8 frameType; /* frame type */ + bit8 hdsa[3]; /* Hashed destination SAS Address */ + bit8 reserved1; + bit8 hssa[3]; /* Hashed source SAS Address */ + bit8 reserved2; + bit8 reserved3; + bit8 tlr_rdf; + /* B7-5 : reserved */ + /* B4-3 : TLR control*/ + /* B2 : Retry Data Frames */ + /* B1 : Retransmit */ + /* B0 : Changing Data Pointer */ + bit8 fill_bytes; + /* B7-2 : reserved */ + /* B1-0 : Number of Fill bytes*/ + bit8 reserved5; + bit8 reserved6[3]; + bit8 tag[2]; /* CMD or TM tag */ + bit8 tptt[2]; /* target port transfer tag */ + bit8 dataOffset[4]; /* data offset */ + /* Follow by IU */ +} agsaSSPFrameFormat_t; + + +typedef struct agsaSSPOpenFrame_s +{ + bit8 frameType; /* frame type */ + /* B7 : Initiator Port */ + /* B6-4 : Protocol */ + /* B3-0 : Address Frame Type */ + bit8 feat_connrate; + /* B7-4 : features */ + /* B3-0 : connection rate */ + bit8 initiatorConnTag[2]; /* Initiator connection tag */ + bit8 dstSasAddr[8]; /* Destination SAS Address */ + bit8 srcSasAddr[8]; /* Source SAS Address */ + bit8 zoneSrcGroup; /* Zone source group */ + bit8 pathwayBlockCount; /* pathway block count */ + bit8 arbWaitTime[2]; /* Arbitration Wait Time */ + bit8 moreCompatFeat[4]; /* More Compatibility Features */ + /* Follow by CRC */ +} agsaSSPOpenFrame_t; + +#define SA_SSPRESP_GET_SENSEDATALEN(pSSPResp) \ + DMA_BEBIT32_TO_BIT32(*(bit32*)(pSSPResp)->senseDataLen) + +#define SA_SSPRESP_GET_RESPONSEDATALEN(pSSPResp) \ + DMA_BEBIT32_TO_BIT32(*(bit32*)(pSSPResp)->responsedataLen) + +#define SA_SSPRESP_GET_DATAPRES(pSSPResp) ((pSSPResp)->dataPres & 0x3) + +/** \brief structure describes a SAS SSP Task Management command request + * + * The agsaSSPScsiTaskMgntReq_t data structure describes a SAS SSP Task Management command request sent by the + * initiator or received by the target. + * + * The response to Task Management is specified by agsaSSPResponseInfoUnit_t. + * + * This data structure is one instance of the generic request issued to saSSPStart() and is passed + * as an agsaSASRequestBody_t + * + */ +typedef struct agsaSSPScsiTaskMgntReq_s +{ + bit8 lun[8]; /* SCSI Logical Unit Number */ + bit16 reserved1; /* reserved */ + bit8 taskMgntFunction; /* task management function code */ + bit8 reserved2; /* reserved */ + bit16 tagOfTaskToBeManaged; /* Tag/context of task to be managed */ + bit16 reserved3; /* reserved */ + bit32 reserved4[3]; /* reserved */ + bit32 tmOption; /* Not part of SSP TMF IU */ + /* B7-2 : reserved */ + /* B1 : DS_OPTION */ + /* B0 : ADS_OPTION */ +} agsaSSPScsiTaskMgntReq_t; + + +/** \brief data structure describes the first four bytes of the SMP frame. + * + * The agsaSMPFrameHeader_t data structure describes the first four bytes of the SMP frame. + * + * + */ + +typedef struct agsaSMPFrameHeader_s +{ + bit8 smpFrameType; /* The first byte of SMP frame represents the SMP FRAME TYPE */ + bit8 smpFunction; /* The second byte of the SMP frame represents the SMP FUNCTION */ + bit8 smpFunctionResult; /* The third byte of SMP frame represents FUNCTION RESULT of the SMP response. */ + bit8 smpReserved; /* reserved */ +} agsaSMPFrameHeader_t; + +/**************************************************************** + * report general response + ****************************************************************/ +#define SA_REPORT_GENERAL_CONFIGURING_BIT 0x2 +#define SA_REPORT_GENERAL_CONFIGURABLE_BIT 0x1 + +typedef struct agsaSmpRespReportGeneral_s +{ + bit8 expanderChangeCount16[2]; + bit8 expanderRouteIndexes16[2]; + bit8 reserved1; + bit8 numOfPhys; + bit8 configuring_configurable; + /* B7-2 : reserved */ + /* B1 : configuring */ + /* B0 : configurable */ + bit8 reserved4[17]; +} agsaSmpRespReportGeneral_t; + +#define SA_REPORT_GENERAL_IS_CONFIGURING(pResp) \ + (((pResp)->configuring_configurable & SA_REPORT_GENERAL_CONFIGURING_BIT) == \ + SA_REPORT_GENERAL_CONFIGURING_BIT) + +#define SA_REPORT_GENERAL_IS_CONFIGURABLE(pResp) \ + (((pResp)->configuring_configurable & SA_REPORT_GENERAL_CONFIGURABLE_BIT) == \ + SA_REPORT_GENERAL_CONFIGURABLE_BIT) + +#define SA_REPORT_GENERAL_GET_ROUTEINDEXES(pResp) \ + DMA_BEBIT16_TO_BIT16(*(bit16 *)((pResp)->expanderRouteIndexes16)) + +/**************************************************************** + * report manufacturer info response + ****************************************************************/ +typedef struct agsaSmpRespReportManufactureInfo_s +{ + bit8 reserved1[8]; + bit8 vendorIdentification[8]; + bit8 productIdentification[16]; + bit8 productRevisionLevel[4]; + bit8 vendorSpecific[20]; +} agsaSmpRespReportManufactureInfo_t; + +/**************************************************************** + * discover request + ****************************************************************/ +typedef struct agsaSmpReqDiscover_s +{ + bit32 reserved1; + bit8 reserved2; + bit8 phyIdentifier; + bit8 ignored; + bit8 reserved3; +} agsaSmpReqDiscover_t; + +/**************************************************************** + * discover response + ****************************************************************/ +typedef struct agsaSmpRespDiscover_s +{ + bit8 reserved1[4]; + bit8 reserved2; + bit8 phyIdentifier; + bit8 reserved3[2]; + bit8 attachedDeviceType; + /* B7 : reserved */ + /* B6-4 : attachedDeviceType */ + /* B3-0 : reserved */ + bit8 negotiatedPhyLinkRate; + /* B7-4 : reserved */ + /* B3-0 : negotiatedPhyLinkRate */ + bit8 attached_Ssp_Stp_Smp_Sata_Initiator; + /* B7-4 : reserved */ + /* B3 : attachedSspInitiator */ + /* B2 : attachedStpInitiator */ + /* B1 : attachedSmpInitiator */ + /* B0 : attachedSataHost */ + bit8 attached_SataPS_Ssp_Stp_Smp_Sata_Target; + /* B7 : attachedSataPortSelector */ + /* B6-4 : reserved */ + /* B3 : attachedSspTarget */ + /* B2 : attachedStpTarget */ + /* B1 : attachedSmpTarget */ + /* B0 : attachedSatadevice */ + bit8 sasAddressHi[4]; + bit8 sasAddressLo[4]; + bit8 attachedSasAddressHi[4]; + bit8 attachedSasAddressLo[4]; + bit8 attachedPhyIdentifier; + bit8 reserved9[7]; + bit8 programmedAndHardware_MinPhyLinkRate; + /* B7-4 : programmedMinPhyLinkRate */ + /* B3-0 : hardwareMinPhyLinkRate */ + bit8 programmedAndHardware_MaxPhyLinkRate; + /* B7-4 : programmedMaxPhyLinkRate */ + /* B3-0 : hardwareMaxPhyLinkRate */ + bit8 phyChangeCount; + bit8 virtualPhy_partialPathwayTimeout; + /* B7 : virtualPhy*/ + /* B6-4 : reserved */ + /* B3-0 : partialPathwayTimeout */ + bit8 routingAttribute; + /* B7-4 : reserved */ + /* B3-0 : routingAttribute */ + bit8 reserved13[5]; + bit8 vendorSpecific[2]; +} agsaSmpRespDiscover_t; + +#define SA_DISCRSP_SSP_BIT 0x08 +#define SA_DISCRSP_STP_BIT 0x04 +#define SA_DISCRSP_SMP_BIT 0x02 +#define SA_DISCRSP_SATA_BIT 0x01 + +#define SA_DISCRSP_SATA_PS_BIT 0x80 + +#define SA_DISCRSP_GET_ATTACHED_DEVTYPE(pResp) \ + (((pResp)->attachedDeviceType & 0x70) >> 4) +#define SA_DISCRSP_GET_LINKRATE(pResp) \ + ((pResp)->negotiatedPhyLinkRate & 0x0F) + +#define SA_DISCRSP_IS_SSP_INITIATOR(pResp) \ + (((pResp)->attached_Ssp_Stp_Smp_Sata_Initiator & SA_DISCRSP_SSP_BIT) == SA_DISCRSP_SSP_BIT) +#define SA_DISCRSP_IS_STP_INITIATOR(pResp) \ + (((pResp)->attached_Ssp_Stp_Smp_Sata_Initiator & SA_DISCRSP_STP_BIT) == SA_DISCRSP_STP_BIT) +#define SA_DISCRSP_IS_SMP_INITIATOR(pResp) \ + (((pResp)->attached_Ssp_Stp_Smp_Sata_Initiator & SA_DISCRSP_SMP_BIT) == SA_DISCRSP_SMP_BIT) +#define SA_DISCRSP_IS_SATA_HOST(pResp) \ + (((pResp)->attached_Ssp_Stp_Smp_Sata_Initiator & SA_DISCRSP_SATA_BIT) == SA_DISCRSP_SATA_BIT) + +#define SA_DISCRSP_IS_SSP_TARGET(pResp) \ + (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & SA_DISCRSP_SSP_BIT) == SA_DISCRSP_SSP_BIT) +#define SA_DISCRSP_IS_STP_TARGET(pResp) \ + (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & SA_DISCRSP_STP_BIT) == SA_DISCRSP_STP_BIT) +#define SA_DISCRSP_IS_SMP_TARGET(pResp) \ + (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & SA_DISCRSP_SMP_BIT) == SA_DISCRSP_SMP_BIT) +#define SA_DISCRSP_IS_SATA_DEVICE(pResp) \ + (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & SA_DISCRSP_SATA_BIT) == SA_DISCRSP_SATA_BIT) +#define SA_DISCRSP_IS_SATA_PORTSELECTOR(pResp) \ + (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & SA_DISCRSP_SATA_PS_BIT) == SA_DISCRSP_SATA_PS_BIT) + +#define SA_DISCRSP_GET_SAS_ADDRESSHI(pResp) \ + DMA_BEBIT32_TO_BIT32(*(bit32 *)(pResp)->sasAddressHi) +#define SA_DISCRSP_GET_SAS_ADDRESSLO(pResp) \ + DMA_BEBIT32_TO_BIT32(*(bit32 *)(pResp)->sasAddressLo) + +#define SA_DISCRSP_GET_ATTACHED_SAS_ADDRESSHI(pResp) \ + DMA_BEBIT32_TO_BIT32(*(bit32 *)(pResp)->attachedSasAddressHi) +#define SA_DISCRSP_GET_ATTACHED_SAS_ADDRESSLO(pResp) \ + DMA_BEBIT32_TO_BIT32(*(bit32 *)(pResp)->attachedSasAddressLo) + +#define SA_DISCRSP_VIRTUALPHY_BIT 0x80 +#define SA_DISCRSP_IS_VIRTUALPHY(pResp) \ + (((pResp)->virtualPhy_partialPathwayTimeout & SA_DISCRSP_VIRTUALPHY_BIT) == SA_DISCRSP_VIRTUALPHY_BIT) + +#define SA_DISCRSP_GET_ROUTINGATTRIB(pResp) \ + ((pResp)->routingAttribute & 0x0F) + +/**************************************************************** + * report route table request + ****************************************************************/ +typedef struct agsaSmpReqReportRouteTable_s +{ + bit8 reserved1[2]; + bit8 expanderRouteIndex16[20]; + bit8 reserved2; + bit8 phyIdentifier; + bit8 reserved3[2]; +} agsaSmpReqReportRouteTable_t; + +/**************************************************************** + * report route response + ****************************************************************/ +typedef struct agsaSmpRespReportRouteTable_s +{ + bit8 reserved1[2]; + bit8 expanderRouteIndex16[2]; + bit8 reserved2; + bit8 phyIdentifier; + bit8 reserved3[2]; + bit8 disabled; + /* B7 : expander route entry disabled */ + /* B6-0 : reserved */ + bit8 reserved5[3]; + bit8 routedSasAddressHi32[4]; + bit8 routedSasAddressLo32[4]; + bit8 reserved6[16]; +} agsaSmpRespReportRouteTable_t; + +/**************************************************************** + * configure route information request + ****************************************************************/ +typedef struct agsaSmpReqConfigureRouteInformation_s +{ + bit8 reserved1[2]; + bit8 expanderRouteIndex[2]; + bit8 reserved2; + bit8 phyIdentifier; + bit8 reserved3[2]; + bit8 disabledBit_reserved4; + bit8 reserved5[3]; + bit8 routedSasAddressHi[4]; + bit8 routedSasAddressLo[4]; + bit8 reserved6[16]; +} agsaSmpReqConfigureRouteInformation_t; + +/**************************************************************** + * report Phy Sata request + ****************************************************************/ +typedef struct agsaSmpReqReportPhySata_s +{ + bit8 reserved1[4]; + bit8 reserved2; + bit8 phyIdentifier; + bit8 reserved3[2]; +} agsaSmpReqReportPhySata_t; + +/**************************************************************** + * report Phy Sata response + ****************************************************************/ +typedef struct agsaSmpRespReportPhySata_s +{ + bit8 reserved1[4]; + bit8 reserved2; + bit8 phyIdentifier; + bit8 reserved3; + bit8 affiliations_sup_valid; + /* b7-2 : reserved */ + /* b1 : Affiliations supported */ + /* b0 : Affiliation valid */ + bit8 reserved5[4]; + bit8 stpSasAddressHi[4]; + bit8 stpSasAddressLo[4]; + bit8 regDevToHostFis[20]; + bit8 reserved6[4]; + bit8 affiliatedStpInitiatorSasAddressHi[4]; + bit8 affiliatedStpInitiatorSasAddressLo[4]; +} agsaSmpRespReportPhySata_t; + +/**************************************************************** + * Phy Control request + ****************************************************************/ +typedef struct agsaSmpReqPhyControl_s +{ + bit8 reserved1[4]; + bit8 reserved2; + bit8 phyIdentifier; + bit8 phyOperation; + bit8 updatePartialPathwayTOValue; + /* b7-1 : reserved */ + /* b0 : update partial pathway timeout value */ + bit8 reserved3[20]; + bit8 programmedMinPhysicalLinkRate; + /* b7-4 : programmed Minimum Physical Link Rate*/ + /* b3-0 : reserved */ + bit8 programmedMaxPhysicalLinkRate; + /* b7-4 : programmed Maximum Physical Link Rate*/ + /* b3-0 : reserved */ + bit8 reserved4[2]; + bit8 partialPathwayTOValue; + /* b7-4 : reserved */ + /* b3-0 : partial Pathway TO Value */ + bit8 reserved5[3]; +} agsaSmpReqPhyControl_t; + + + + +#endif /*__SASPEC_H__ */ diff --git a/sys/dev/pms/RefTisa/sallsdk/api/saapi.h b/sys/dev/pms/RefTisa/sallsdk/api/saapi.h new file mode 100644 index 000000000000..9a4d8e09ad08 --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/api/saapi.h @@ -0,0 +1,728 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/*******************************************************************************/ +/*! \file saapi.h + * \brief The file defines the declaration of tSDK APIs + * + * + * + * + */ +/******************************************************************************/ + +#ifndef __SSDKAPI_H__ +#define __SSDKAPI_H__ + +/******************************************************************************** + * SA LL Function Declaration * + ********************************************************************************/ + +/*************************************************************************** + * Definition of interrupt related functions start * + ***************************************************************************/ + + +GLOBAL bit32 FORCEINLINE saDelayedInterruptHandler( + agsaRoot_t *agRoot, + bit32 interruptVectorIndex, + bit32 count + ); + +GLOBAL bit32 FORCEINLINE saInterruptHandler( + agsaRoot_t *agRoot, + bit32 interruptVectorIndex + ); + +GLOBAL void saSystemInterruptsActive( + agsaRoot_t *agRoot, + agBOOLEAN sysIntsActive + ); + +GLOBAL FORCEINLINE void saSystemInterruptsEnable( + agsaRoot_t *agRoot, + bit32 interruptVectorIndex + ); +/*************************************************************************** + * Definition of interrupt related functions end * + ***************************************************************************/ + + +/*************************************************************************** + * Definition of timer related functions start * + ***************************************************************************/ +GLOBAL void saTimerTick(agsaRoot_t *agRoot); +/*************************************************************************** + * Definition of timer related functions end * + ***************************************************************************/ + +/*************************************************************************** + * Definition of initialization related functions start * + ***************************************************************************/ +GLOBAL void saGetRequirements( + agsaRoot_t *agRoot, + agsaSwConfig_t *swConfig, + agsaMemoryRequirement_t *memoryRequirement, + bit32 *usecsPerTick, + bit32 *maxNumLocks + ); + +GLOBAL bit32 saInitialize( + agsaRoot_t *agRoot, + agsaMemoryRequirement_t *memoryAllocated, + agsaHwConfig_t *hwConfig, + agsaSwConfig_t *swConfig, + bit32 usecsPerTick + ); +/*************************************************************************** + * Definition of initialization related functions end * + ***************************************************************************/ + +/*************************************************************************** + * Definition of hardware related functions start * + ***************************************************************************/ +GLOBAL void saHwReset( + agsaRoot_t *agRoot, + bit32 resetType, + bit32 resetParm + ); + +GLOBAL void saHwShutdown(agsaRoot_t *agRoot); + +/*************************************************************************** + * Definition of hardware related functions end * + ***************************************************************************/ + +/*************************************************************************** + * Definition of phy related functions start * + ***************************************************************************/ +GLOBAL bit32 saPhyStart( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 phyId, + agsaPhyConfig_t *agPhyConfig, + agsaSASIdentify_t *agSASIdentify + ); + +GLOBAL bit32 saPhyStop( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 phyId + ); + + +GLOBAL bit32 saLocalPhyControl( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 phyId, + bit32 phyOperation, + ossaLocalPhyControlCB_t agCB + ); + +GLOBAL bit32 saGetPhyProfile( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 ppc, + bit32 phyID + ); + +GLOBAL bit32 saSetPhyProfile ( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 ppc, + bit32 length, + void *buffer, + bit32 phyID + ); + +GLOBAL bit32 saHwEventAck( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaEventSource_t *eventSource, + bit32 param0, + bit32 param1 + ); + + +/*************************************************************************** + * Definition of phy related functions end * + ***************************************************************************/ + +/*************************************************************************** + * Definition of discovery related functions start * + ***************************************************************************/ +GLOBAL bit32 saDiscover( + agsaRoot_t *agRoot, + agsaPortContext_t *agPortContext, + bit32 type, + bit32 option + ); +/*************************************************************************** + * Definition of discovery related functions end * + ***************************************************************************/ + +/*************************************************************************** + * Definition of frame related functions start * + ***************************************************************************/ +GLOBAL bit32 saFrameReadBit32( + agsaRoot_t *agRoot, + agsaFrameHandle_t agFrame, + bit32 frameOffset + ); + +GLOBAL void saFrameReadBlock( + agsaRoot_t *agRoot, + agsaFrameHandle_t agFrame, + bit32 frameOffset, + void *frameBuffer, + bit32 frameBufLen + ); +/*************************************************************************** + * Definition of frame related functions end * + ***************************************************************************/ + +/*************************************************************************** + * Definition of SATA related functions start * + ***************************************************************************/ +GLOBAL bit32 saSATAStart( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 queueNum, + agsaDevHandle_t *agDevHandle, + bit32 agRequestType, + agsaSATAInitiatorRequest_t *agSATAReq, + bit8 agTag, + ossaSATACompletedCB_t agCB + ); + +GLOBAL bit32 saSATAAbort( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 queueNum, + agsaDevHandle_t *agDevHandle, + bit32 flag, + void *abortParam, + ossaGenericAbortCB_t agCB + ); + +/*************************************************************************** + * Definition of SATA related functions end * + ***************************************************************************/ + +/*************************************************************************** + * Definition of SAS related functions start * + ***************************************************************************/ + +GLOBAL bit32 saSendSMPIoctl( + agsaRoot_t *agRoot, + agsaDevHandle_t *agDevHandle, + bit32 queueNum, + agsaSMPFrame_t *pSMPFrame, + ossaSMPCompletedCB_t agCB + ); + +GLOBAL bit32 saSMPStart( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 queueNum, + agsaDevHandle_t *agDevHandle, + bit32 agRequestType, + agsaSASRequestBody_t *agRequestBody, + ossaSMPCompletedCB_t agCB + ); + +GLOBAL bit32 saSMPAbort( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 queueNum, + agsaDevHandle_t *agDevHandle, + bit32 flag, + void *abortParam, + ossaGenericAbortCB_t agCB + ); + +GLOBAL bit32 saSSPStart( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 queueNum, + agsaDevHandle_t *agDevHandle, + bit32 agRequestType, + agsaSASRequestBody_t *agRequestBody, + agsaIORequest_t *agTMRequest, + ossaSSPCompletedCB_t agCB + ); + +#ifdef FAST_IO_TEST +GLOBAL void *saFastSSPPrepare( + void *ioHandle, + agsaFastCommand_t *fc, + ossaSSPCompletedCB_t cb, + void *cbArg); + +GLOBAL bit32 saFastSSPSend(void *ioHandle); +GLOBAL bit32 saFastSSPCancel(void *ioHandle); +#endif + +GLOBAL bit32 saSSPAbort( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 queueNum, + agsaDevHandle_t *agDevHandle, + bit32 flag, + void *abortParam, + ossaGenericAbortCB_t agCB + ); + +GLOBAL void saGetDifErrorDetails( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + agsaDifDetails_t *difDetails + ); + +GLOBAL bit32 saRegisterEventCallback( + agsaRoot_t *agRoot, + bit32 eventSourceType, + ossaGenericCB_t callbackPtr + ); + +/*************************************************************************** + * Definition of SAS related functions end * + ***************************************************************************/ + +/*************************************************************************** + * Definition of Device related functions start * + ***************************************************************************/ +GLOBAL bit32 saRegisterNewDevice( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaDeviceInfo_t *agDeviceInfo, + agsaPortContext_t *agPortContext, + bit16 hostAssignedDeviceId + ); + +GLOBAL bit32 saDeregisterDeviceHandle( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaDevHandle_t *agDevHandle, + bit32 queueNum + ); + +GLOBAL bit32 saGetDeviceHandles( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaPortContext_t *agPortContext, + bit32 flags, + agsaDevHandle_t *agDev[], + bit32 skipCount, + bit32 maxDevs + ); + +GLOBAL bit32 saGetDeviceInfo( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 option, + bit32 queueNum, + agsaDevHandle_t *agDevHandle + ); + +GLOBAL bit32 saGetDeviceState( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaDevHandle_t *agDevHandle + ); + +GLOBAL bit32 saSetDeviceInfo( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum , + agsaDevHandle_t *agDevHandle, + bit32 option, + bit32 param, + ossaSetDeviceInfoCB_t agCB + ); + +GLOBAL bit32 saSetDeviceState( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaDevHandle_t *agDevHandle, + bit32 newDeviceState + ); + +/*************************************************************************** + * Definition of Device related functions end * + ***************************************************************************/ + +/*************************************************************************** + * Definition of Misc related functions start * + ***************************************************************************/ +GLOBAL bit32 saFwFlashUpdate( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaUpdateFwFlash_t *flashUpdateInfo + ); + +GLOBAL bit32 saFlashExtExecute ( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaFlashExtExecute_t *agFlashExtExe + ); + +#ifdef SPC_ENABLE_PROFILE +GLOBAL bit32 saFwProfile( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaFwProfile_t *fwProfileInfo + ); +#endif + +GLOBAL bit32 saEchoCommand( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + void *echoPayload + ); + +GLOBAL bit32 saGetControllerInfo( + agsaRoot_t *agRoot, + agsaControllerInfo_t *controllerInfo + ); + +GLOBAL bit32 saGetControllerStatus( + agsaRoot_t *agRoot, + agsaControllerStatus_t *controllerStatus + ); + +GLOBAL bit32 saGetControllerEventLogInfo( + agsaRoot_t *agRoot, + agsaControllerEventLog_t *eventLogInfo + ); + +GLOBAL bit32 saGpioEventSetup( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaGpioEventSetupInfo_t *gpioEventSetupInfo + ); + +GLOBAL bit32 saGpioPinSetup( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaGpioPinSetupInfo_t *gpioPinSetupInfo + ); + +GLOBAL bit32 saGpioRead( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum + ); + +GLOBAL bit32 saGpioWrite( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 gpioWriteMask, + bit32 gpioWriteValue + ); + +GLOBAL bit32 saSASDiagExecute( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaSASDiagExecute_t *diag + ); + +GLOBAL bit32 saSASDiagStartEnd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 phyId, + bit32 operation + ); + +GLOBAL bit32 saGetTimeStamp( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum + ); + +GLOBAL bit32 saPortControl( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaPortContext_t *agPortContext, + bit32 portOperation, + bit32 param0, + bit32 param1 + ); + +GLOBAL bit32 saGetRegisterDump( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaRegDumpInfo_t *regDumpInfo + ); + +GLOBAL bit32 saGetForensicData( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaForensicData_t *forensicData + ); + +bit32 saGetIOErrorStats( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 flag + ); + +bit32 saGetIOEventStats( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 flag + ); + +GLOBAL bit32 saGetNVMDCommand( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaNVMDData_t *NVMDInfo + ); + +GLOBAL bit32 saSetNVMDCommand( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaNVMDData_t *NVMDInfo + ); + +GLOBAL bit32 saReconfigSASParams( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum , + agsaSASReconfig_t *agSASConfig + ); + +GLOBAL bit32 saSgpio( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaSGpioReqResponse_t *pSGpioReq + ); + +GLOBAL bit32 saPCIeDiagExecute( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaPCIeDiagExecute_t *diag); + + +GLOBAL bit32 saEncryptSelftestExecute( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 type, + bit32 length, + void *TestDescriptor); + +GLOBAL bit32 saSetOperator( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 flag, + void *cert); + +GLOBAL bit32 saGetOperator( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 option, + bit32 AddrHi, + bit32 AddrLo); + +GLOBAL bit32 saOperatorManagement( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 flag, + bit8 role, + agsaID_t *id, + agsaEncryptKekBlob_t *kblob); + + +/*************************************************************************** + * Definition of Misc. related functions end * + ***************************************************************************/ + +GLOBAL bit32 saSetControllerConfig( + agsaRoot_t *agRoot, + bit32 queueNum, + bit32 modePage, + bit32 length, + void *buffer, + agsaContext_t *agContext + ); + + +GLOBAL bit32 saGetControllerConfig( + agsaRoot_t *agRoot, + bit32 queueNum, + bit32 modePage, + bit32 flag0, + bit32 flag1, + agsaContext_t *agContext + ); + +GLOBAL bit32 saEncryptDekCacheUpdate( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 kekIndex, + bit32 dekTableSelect, + bit32 dekAddrHi, + bit32 dekAddrLo, + bit32 dekIndex, + bit32 dekNumberOfEntries, + bit32 dekBlobFormat, + bit32 dekTableKeyEntrySize + ); + +GLOBAL bit32 saEncryptDekCacheInvalidate( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 dekTable, + bit32 dekIndex + ); + +GLOBAL bit32 saEncryptGetMode( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaEncryptInfo_t *encryptInfo + ); + +GLOBAL bit32 saEncryptSetMode ( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaEncryptInfo_t *mode + ); + +GLOBAL bit32 saEncryptKekInvalidate( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 kekIndex + ); + +GLOBAL bit32 saEncryptKekUpdate( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 flags, + bit32 newKekIndex, + bit32 wrapperKekIndex, + bit32 blobFormat, + agsaEncryptKekBlob_t *encryptKekBlob + ); + +#ifdef HIALEAH_ENCRYPTION +GLOBAL bit32 saEncryptHilUpdate( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum + ); +#endif /* HIALEAH_ENCRYPTION */ + +GLOBAL bit32 saGetDFEData( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 interface, + bit32 laneNumber, + bit32 interations, + agsaSgl_t *agSgl); + + +GLOBAL bit32 saFatalInterruptHandler( + agsaRoot_t *agRoot, + bit32 interruptVectorIndex + ); + + +GLOBAL bit32 saDIFEncryptionOffloadStart( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 op, + agsaDifEncPayload_t *agsaDifEncPayload, + ossaDIFEncryptionOffloadStartCB_t agCB); + + +GLOBAL bit32 saVhistCapture( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 Channel, + bit32 NumBitLo, + bit32 NumBitHi, + bit32 PcieAddrLo, + bit32 PcieAddrHi, + bit32 ByteCount ); + + +GLOBAL void saCountActiveIORequests( agsaRoot_t *agRoot); + +#ifdef SA_64BIT_TIMESTAMP +osGLOBAL bit64 osTimeStamp64(void); +#endif /* SA_64BIT_TIMESTAMP */ + +#ifdef SALL_API_TEST +/*************************************************************************** + * Definition of LL Test related API functions start * + ***************************************************************************/ +GLOBAL bit32 saGetLLCounters( + agsaRoot_t *agRoot, + bit32 counters, + agsaLLCountInfo_t *LLCountInfo + ); + +GLOBAL bit32 saResetLLCounters( + agsaRoot_t *agRoot, + bit32 counters + ); +#endif + +#endif /*__SSDKAPI_H__ */ diff --git a/sys/dev/pms/RefTisa/sallsdk/api/saosapi.h b/sys/dev/pms/RefTisa/sallsdk/api/saosapi.h new file mode 100644 index 000000000000..02f874af75ba --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/api/saosapi.h @@ -0,0 +1,843 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/*******************************************************************************/ +/*! \file saosapi.h + * \brief The file defines the declaration of OS APIs + * + */ +/*******************************************************************************/ + +#ifndef __SSDKOSAPI_H__ +#define __SSDKOSAPI_H__ + +#ifdef LINUX +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18) + +#ifdef FORCEINLINE +#undef FORCEINLINE +#define FORCEINLINE +#endif + +#endif +#endif + +/*************************************************************************** + * Definition of register access related functions start * + ***************************************************************************/ +#ifndef ossaHwRegRead +GLOBAL FORCEINLINE +bit32 ossaHwRegRead( + agsaRoot_t *agRoot, + bit32 regOffset + ); +#endif + +#ifndef ossaHwRegWrite +GLOBAL FORCEINLINE +void ossaHwRegWrite( + agsaRoot_t *agRoot, + bit32 regOffset, + bit32 regValue + ); +#endif + +#ifndef ossaHwRegReadExt +GLOBAL FORCEINLINE +bit32 ossaHwRegReadExt( + agsaRoot_t *agRoot, + bit32 busBaseNumber, + bit32 regOffset + ); +#endif + +#ifndef ossaHwRegWriteExt +GLOBAL FORCEINLINE +void ossaHwRegWriteExt( + agsaRoot_t *agRoot, + bit32 busBaseNumber, + bit32 regOffset, + bit32 regValue + ); +#endif + +#ifndef ossaHwRegReadConfig32 +osGLOBAL bit32 ossaHwRegReadConfig32( + agsaRoot_t *agRoot, + bit32 regOffset + ); +#endif + + +/*************************************************************************** + * Definition of register access related functions end * + ***************************************************************************/ + +/*************************************************************************** + * Definition of thread related functions start * + ***************************************************************************/ +#ifndef ossaSingleThreadedEnter +GLOBAL FORCEINLINE void ossaSingleThreadedEnter( + agsaRoot_t *agRoot, + bit32 syncLockId + ); +#endif + +#ifndef ossaSingleThreadedLeave +GLOBAL FORCEINLINE void ossaSingleThreadedLeave( + agsaRoot_t *agRoot, + bit32 syncLockId + ); +#endif + +#ifndef ossaStallThread +GLOBAL void ossaStallThread( + agsaRoot_t *agRoot, + bit32 microseconds + ); +#endif +/*************************************************************************** + * Definition of thread related functions end * + ***************************************************************************/ + +/*************************************************************************** + * Definition of interrupt related functions start * + ***************************************************************************/ +#ifndef ossaDisableInterrupts +#define ossaDisableInterrupts(agRoot, interruptVectorIndex) \ +do \ +{ \ + agsaLLRoot_t *saROOT = (agsaLLRoot_t *)(agRoot->sdkData);\ + saROOT->DisableInterrupts(agRoot, interruptVectorIndex); \ +} while(0) +#endif + +#ifndef ossaReenableInterrupts +#define ossaReenableInterrupts(agRoot, interruptVectorIndex) \ +do \ +{ \ + agsaLLRoot_t *saROOT = (agsaLLRoot_t *)(agRoot->sdkData); \ + saROOT->ReEnableInterrupts(agRoot, interruptVectorIndex); \ +} while(0) +#endif + +/*************************************************************************** + * Definition of interrupt related functions end * + ***************************************************************************/ + +/*************************************************************************** + * Definition of cache related functions start * + ***************************************************************************/ +#ifndef ossaCacheInvalidate +GLOBAL FORCEINLINE void ossaCacheInvalidate( + agsaRoot_t *agRoot, + void *osMemHandle, + void *virtPtr, + bit32 length + ); +#endif + +#ifndef ossaCacheFlush +GLOBAL FORCEINLINE void ossaCacheFlush( + agsaRoot_t *agRoot, + void *osMemHandle, + void *virtPtr, + bit32 length + ); +#endif + +#ifndef ossaCachePreFlush +GLOBAL FORCEINLINE void ossaCachePreFlush( + agsaRoot_t *agRoot, + void *osMemHandle, + void *virtPtr, + bit32 length + ); +#endif + +/*************************************************************************** + * Definition of cache related functions end * + ***************************************************************************/ + +/*************************************************************************** + * Definition of hardware related functions start * + ***************************************************************************/ +#ifndef ossaHwCB +GLOBAL void ossaHwCB( + agsaRoot_t *agRoot, + agsaPortContext_t *agPortContext, + bit32 event, + bit32 eventParm1, + void *eventParm2, + void *eventParm3 + ); +#endif + +#ifndef ossaHwEventAckCB +GLOBAL void ossaHwEventAckCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status + ); +#endif +/*************************************************************************** + * Definition of hardware related functions end * + ***************************************************************************/ + +/*************************************************************************** + * Definition of SATA related functions start * + ***************************************************************************/ +#ifndef ossaSATACompleted +GLOBAL void ossaSATACompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + void *agFirstDword, + bit32 agIOInfoLen, + void *agParam + ); + +#endif + +#ifndef ossaSATAEvent +GLOBAL void ossaSATAEvent( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + agsaPortContext_t *agPortContext, + agsaDevHandle_t *agDevHandle, + bit32 event, + bit32 agIOInfoLen, + void *agParam + ); +#endif + +#ifndef ossaSATAAbortCB + GLOBAL void ossaSATAAbortCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 flag, + bit32 status + ); +#endif + +/*************************************************************************** + * Definition of SATA related functions end * + ***************************************************************************/ + + +/*************************************************************************** + * Definition of SAS related functions start * + ***************************************************************************/ +#ifndef ossaSSPEvent +GLOBAL void ossaSSPEvent( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + agsaPortContext_t *agPortContext, + agsaDevHandle_t *agDevHandle, + bit32 event, + bit16 sspTag, + bit32 agIOInfoLen, + void *agParam + ); +#endif + +osGLOBAL void +ossaSMPIoctlCompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle + ); + +#ifndef ossaSMPCompleted +GLOBAL void ossaSMPCompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle + ); +#endif + +#ifndef ossaSMPReqReceived +GLOBAL void ossaSMPReqReceived( + agsaRoot_t *agRoot, + agsaDevHandle_t *agDevHandle, + agsaFrameHandle_t agFrameHandle, + bit32 agFrameLength, + bit32 phyId + ); +#endif + +#ifndef ossaSSPCompleted +GLOBAL FORCEINLINE void ossaSSPCompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit16 sspTag, + bit32 agOtherInfo + ); +#endif + +#ifdef FAST_IO_TEST +GLOBAL void ossaFastSSPCompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *cbArg, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit16 sspTag, + bit32 agOtherInfo + ); +#endif + +#ifndef ossaSSPReqReceived +GLOBAL void ossaSSPReqReceived( + agsaRoot_t *agRoot, + agsaDevHandle_t *agDevHandle, + agsaFrameHandle_t agFrameHandle, + bit16 agInitiatorTag, + bit32 parameter, + bit32 agFrameLen + ); +#endif + +osGLOBAL void +ossaSSPIoctlCompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit16 sspTag, + bit32 agOtherInfo + ); + + +#ifndef ossaSSPAbortCB +GLOBAL void ossaSSPAbortCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 flag, + bit32 status + ); +#endif + +#ifndef ossaSMPAbortCB +GLOBAL void ossaSMPAbortCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 flag, + bit32 status + ); +#endif + +#ifndef ossaReconfigSASParamsCB +GLOBAL void ossaReconfigSASParamsCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + agsaSASReconfig_t *agSASConfig +); +#endif + +/*************************************************************************** + * Definition of SAS related functions end * + ***************************************************************************/ + +/*************************************************************************** + * Definition of Discovery related functions start * + ***************************************************************************/ +#ifndef ossaDiscoverSataCB +GLOBAL void ossaDiscoverSataCB( + agsaRoot_t *agRoot, + agsaPortContext_t *agPortContext, + bit32 event, + void *pParm1, + void *pParm2 + ); +#endif + +#ifndef ossaDiscoverSasCB +GLOBAL void ossaDiscoverSasCB( + agsaRoot_t *agRoot, + agsaPortContext_t *agPortContext, + bit32 event, + void *pParm1, + void *pParm2 + ); +#endif + +#ifndef ossaDeviceHandleAccept +GLOBAL bit32 ossaDeviceHandleAccept( + agsaRoot_t *agRoot, + agsaDevHandle_t *agDevHandle, + agsaSASDeviceInfo_t *agDeviceInfo, + agsaPortContext_t *agPortContext, + bit32 *hostAssignedDeviceId + ); +#endif + +#ifndef ossaGetDeviceHandlesCB +GLOBAL void ossaGetDeviceHandlesCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaPortContext_t *agPortContext, + agsaDevHandle_t *agDev[], + bit32 validDevs + ); +#endif + +#ifndef ossaGetDeviceInfoCB +GLOBAL void ossaGetDeviceInfoCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaDevHandle_t *agDevHandle, + bit32 status, + void *agInfo + ); +#endif + +#ifndef ossaDeviceHandleRemovedEvent +GLOBAL void ossaDeviceHandleRemovedEvent ( + agsaRoot_t *agRoot, + agsaDevHandle_t *agDevHandle, + agsaPortContext_t *agPortContext + ); +#endif + +#ifndef ossaGetDeviceStateCB +GLOBAL void ossaGetDeviceStateCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaDevHandle_t *agDevHandle, + bit32 status, + bit32 deviceState + ); +#endif + +#ifndef ossaSetDeviceInfoCB +GLOBAL void ossaSetDeviceInfoCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaDevHandle_t *agDevHandle, + bit32 status, + bit32 option, + bit32 param + ); +#endif + +#ifndef ossaSetDeviceStateCB +GLOBAL void ossaSetDeviceStateCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaDevHandle_t *agDevHandle, + bit32 status, + bit32 newDeviceState, + bit32 previousDeviceState + ); +#endif + +/*************************************************************************** + * Definition of Discovery related functions end * + ***************************************************************************/ + +/*************************************************************************** + * Definition of Misc. related functions start * + ***************************************************************************/ + +#ifndef ossaTimeStamp +GLOBAL bit32 ossaTimeStamp(agsaRoot_t *agRoot); +#endif /* ossaTimeStamp */ + +#ifndef ossaTimeStamp64 +GLOBAL bit64 ossaTimeStamp64(agsaRoot_t *agRoot); +#endif /* ossaTimeStamp64 */ + + +#ifndef ossaLocalPhyControlCB +GLOBAL void ossaLocalPhyControlCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 phyId, + bit32 phyOperation, + bit32 status, + void *parm); +#endif + +#ifndef ossaGetPhyProfileCB +GLOBAL void ossaGetPhyProfileCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + bit32 ppc, + bit32 phyID, + void *parm ); +#endif + +#ifndef ossaSetPhyProfileCB +GLOBAL void ossaSetPhyProfileCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + bit32 ppc, + bit32 phyID, + void *parm ); +#endif + +#ifndef ossaFwFlashUpdateCB +GLOBAL void ossaFwFlashUpdateCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status); +#endif + +#ifndef ossaFlashExtExecuteCB +GLOBAL void ossaFlashExtExecuteCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + bit32 command, + agsaFlashExtResponse_t *agFlashExtRsp); + +#endif + +#ifdef SPC_ENABLE_PROFILE +GLOBAL void ossaFwProfileCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + bit32 len + ); + +#endif +#ifndef ossaEchoCB +GLOBAL void ossaEchoCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + void *echoPayload); +#endif + +#ifndef ossaGpioResponseCB +GLOBAL void ossaGpioResponseCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + bit32 gpioReadValue, + agsaGpioPinSetupInfo_t *gpioPinSetupInfo, + agsaGpioEventSetupInfo_t *gpioEventSetupInfo); +#endif + +#ifndef ossaGpioEvent +GLOBAL void ossaGpioEvent( + agsaRoot_t *agRoot, + bit32 gpioEvent); +#endif + +#ifndef ossaSASDiagExecuteCB +GLOBAL void ossaSASDiagExecuteCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + bit32 command, + bit32 reportData); +#endif + +#ifndef ossaSASDiagStartEndCB +GLOBAL void ossaSASDiagStartEndCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status); +#endif + +#ifndef ossaGetTimeStampCB +GLOBAL void ossaGetTimeStampCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 timeStampLower, + bit32 timeStampUpper); +#endif + +#ifndef ossaPortControlCB +GLOBAL void ossaPortControlCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaPortContext_t *agPortContext, + bit32 portOperation, + bit32 status); +#endif + +#ifndef ossaGeneralEvent +GLOBAL void ossaGeneralEvent( + agsaRoot_t *agRoot, + bit32 status, + agsaContext_t *agContext, + bit32 *msg); +#endif + +#ifndef ossaGetRegisterDumpCB +void ossaGetRegisterDumpCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status); +#endif + +GLOBAL void ossaGetForensicDataCB ( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + agsaForensicData_t *forensicData + ); + + +#ifndef ossaGetNVMDResponseCB +GLOBAL void ossaGetNVMDResponseCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + bit8 indirectPayload, + bit32 agInfoLen, + agsaFrameHandle_t agFrameHandle ); +#endif + +#ifndef ossaSetNVMDResponseCB +GLOBAL void ossaSetNVMDResponseCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status ); +#endif + +#ifndef ossaQueueProcessed +#ifdef SALLSDK_TEST_SET_OB_QUEUE +GLOBAL void ossaQueueProcessed(agsaRoot_t *agRoot, + bit32 queue, + bit32 obpi, + bit32 obci); +#else +#define ossaQueueProcessed(agRoot, queue, obpi, obci) +#endif +#endif + +#ifndef ossaSGpioCB +GLOBAL void ossaSGpioCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaSGpioReqResponse_t *pSgpioResponse + ); +#endif + +#ifndef ossaPCIeDiagExecuteCB +GLOBAL void ossaPCIeDiagExecuteCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + bit32 command, + agsaPCIeDiagResponse_t *resp ); +#endif + +#ifndef ossaGetDFEDataCB +GLOBAL void ossaGetDFEDataCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + bit32 agInfoLen + ); +#endif + +#ifndef ossaVhistCaptureCB +GLOBAL void ossaVhistCaptureCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + bit32 len); +#endif + +#ifndef ossaGetIOErrorStatsCB +GLOBAL void ossaGetIOErrorStatsCB ( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + agsaIOErrorEventStats_t *stats + ); +#endif + +#ifndef ossaGetIOEventStatsCB +GLOBAL void ossaGetIOEventStatsCB ( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + agsaIOErrorEventStats_t *stats + ); +#endif + +#ifndef ossaOperatorManagementCB +GLOBAL void ossaOperatorManagementCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + bit32 eq + ); +#endif + + +#ifndef ossaEncryptSelftestExecuteCB +GLOBAL void ossaEncryptSelftestExecuteCB ( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + bit32 type, + bit32 length, + void *TestResult + ); + +#endif + +#ifndef ossaGetOperatorCB +GLOBAL void ossaGetOperatorCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + bit32 option, + bit32 num, + bit32 role, + agsaID_t *id + ); + +#endif + +#ifndef ossaSetOperatorCB +GLOBAL void ossaSetOperatorCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + bit32 eq + ); + +#endif + +#ifndef ossaDIFEncryptionOffloadStartCB +GLOBAL void ossaDIFEncryptionOffloadStartCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + agsaOffloadDifDetails_t *agsaOffloadDifDetails + ); +#endif + +/*************************************************************************** + * Definition of Misc related functions end * + ***************************************************************************/ + +/*************************************************************************** + * Definition of Debug related functions start * + ***************************************************************************/ +#ifndef ossaLogTrace0 +GLOBAL void ossaLogTrace0( + agsaRoot_t *agRoot, + bit32 traceCode + ); +#endif + +#ifndef ossaLogTrace1 +GLOBAL void ossaLogTrace1( + agsaRoot_t *agRoot, + bit32 traceCode, + bit32 value1 + ); +#endif + +#ifndef ossaLogTrace2 +GLOBAL void ossaLogTrace2( + agsaRoot_t *agRoot, + bit32 traceCode, + bit32 value1, + bit32 value2 + ); +#endif + +#ifndef ossaLogTrace3 +GLOBAL void ossaLogTrace3( + agsaRoot_t *agRoot, + bit32 traceCode, + bit32 value1, + bit32 value2, + bit32 value3 + ); +#endif + +#ifndef ossaLogTrace4 +GLOBAL void ossaLogTrace4( + agsaRoot_t *agRoot, + bit32 traceCode, + bit32 value1, + bit32 value2, + bit32 value3, + bit32 value4 + ); +#endif + +#ifndef ossaLogDebugString +GLOBAL void ossaLogDebugString( + agsaRoot_t *agRoot, + bit32 level, + char *string, + void *ptr1, + void *ptr2, + bit32 value1, + bit32 value2 + ); +#endif + +#ifdef SALLSDK_OS_IOMB_LOG_ENABLE +GLOBAL void ossaLogIomb(agsaRoot_t *agRoot, + bit32 queueNum, + agBOOLEAN isInbound, + void *pMsg, + bit32 msgLength); +#else +#define ossaLogIomb(a, b,c,d,e ) +#endif + +osGLOBAL void ossaPCI_TRIGGER(agsaRoot_t *agRoot ); + +#ifdef PERF_COUNT +osGLOBAL void ossaEnter(agsaRoot_t *agRoot, int io); +osGLOBAL void ossaLeave(agsaRoot_t *agRoot, int io); +#define OSSA_INP_ENTER(root) ossaEnter(root, 0) +#define OSSA_INP_LEAVE(root) ossaLeave(root, 0) +#define OSSA_OUT_ENTER(root) ossaEnter(root, 1) +#define OSSA_OUT_LEAVE(root) ossaLeave(root, 1) +#else +#define OSSA_INP_ENTER(root) +#define OSSA_INP_LEAVE(root) +#define OSSA_OUT_ENTER(root) +#define OSSA_OUT_LEAVE(root) +#endif +/*************************************************************************** + * Definition of Debug related functions end * + ***************************************************************************/ + +#endif /*__SSDKOSAPI_H__ */ diff --git a/sys/dev/pms/RefTisa/sallsdk/hda/64k/aap18008.h b/sys/dev/pms/RefTisa/sallsdk/hda/64k/aap18008.h new file mode 100644 index 000000000000..f3a6f5122771 --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/hda/64k/aap18008.h @@ -0,0 +1,32505 @@ +/******************************************************************************/ +/**Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. + * +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, +* +*INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +*ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +*SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +*OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +*WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +*THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +****************************************************************************/ + +/******************************************************************************* +** +** $RCSfile:$ +** +** $Date:$ +** +** $Revision:$ +** +** $Author:$ +** +** DESCRIPTION : This file is generated by img2c tool. +** Nerver try to change it manually. +** +*******************************************************************************/ + + + +/* Version Number: 02.09.24.00 */ + +const unsigned char spcv_aap1array[] = +{ + 0x7F,0x45,0x4C,0x46,0x01,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x02,0x00,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x20,0x00,0xBC,0x34,0x00,0x00,0x00, + 0xCC,0xDF,0x07,0x00,0x00,0x00,0x04,0x02,0x34,0x00,0x20,0x00,0x32,0x00,0x28,0x00, + 0x46,0x00,0x45,0x00,0x01,0x00,0x00,0x00,0x00,0x0B,0x00,0x00,0x80,0x04,0x00,0xBC, + 0x00,0x00,0x00,0x00,0x1C,0x01,0x00,0x00,0x1C,0x01,0x00,0x00,0x05,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x48,0x03,0x9C, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF8,0x06,0x00,0x07,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x99, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0x00,0x00,0x07,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0x10,0x99, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0x00,0x00,0x07,0x00,0x00,0x00, + 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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00, +}; diff --git a/sys/dev/pms/RefTisa/sallsdk/hda/64k/aap1img.h b/sys/dev/pms/RefTisa/sallsdk/hda/64k/aap1img.h new file mode 100644 index 000000000000..63b2a060a0e3 --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/hda/64k/aap1img.h @@ -0,0 +1,11782 @@ +/******************************************************************************/ +/** Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. + * +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, +* +*INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +*ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +*SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +*OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +*WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +*THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +****************************************************************************/ + +/******************************************************************************* +** +** $RCSfile:$ +** +** $Date: 2011-01-05 11:25:33 -0800 (Wed, 05 Jan 2011) $ +** +** $Revision: 106946 $ +** +** $Author: lindfors $ +** +** DESCRIPTION : This file is generated by img2c tool. +** Nerver try to change it manually. +** +*******************************************************************************/ + + + +/* Version Number: 01.10.10.00 */ + +const unsigned char aap1array[] = +{ + 0x7F,0x45,0x4C,0x46,0x01,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x02,0x00,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x05,0xC2,0x9F,0x34,0x00,0x00,0x00, + 0x93,0xD3,0x02,0x00,0x00,0x00,0x04,0x02,0x34,0x00,0x20,0x00,0x24,0x00,0x28,0x00, + 0x33,0x00,0x32,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x4D,0xBC, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x90,0x02,0x00,0x07,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xD0,0x4F,0xBC, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x07,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xD8,0x4F,0xBC, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0E,0x00,0x00,0x07,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE6,0x4F,0xBC, + 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0x2E,0xC5,0x9F,0xE0,0xD0,0x02,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x8F,0x02,0x00,0x00,0x08, + 0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x10,0xAE,0xC5,0x9F,0xE0,0xD0,0x02,0x00,0x00, + 0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0xA9,0x02,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0xE0,0xD0,0x02,0x00,0xB3,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x39,0xA3,0xF5,0x90,0x24,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00, +}; diff --git a/sys/dev/pms/RefTisa/sallsdk/hda/64k/ila8008.h b/sys/dev/pms/RefTisa/sallsdk/hda/64k/ila8008.h new file mode 100644 index 000000000000..e9e02b75dabf --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/hda/64k/ila8008.h @@ -0,0 +1,5776 @@ +/****************************************************************************** +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +******************************************************************************/ + +/******************************************************************************* +** +** $RCSfile:$ +** +** $Date:$ +** +** $Revision:$ +** +** $Author:$ +** +** DESCRIPTION : This file is generated by img2c tool. +** Nerver try to change it manually. +** +*******************************************************************************/ + + + +/* Version Number: 02.09.03.00 */ + +const unsigned char spcv_ilaarray[] = +{ + 0x01,0x00,0x11,0x04,0x00,0x00,0x00,0x00,0x25,0x80,0xE0,0x03,0x20,0xBE,0x17,0x3C, + 0x08,0x00,0xF7,0x26,0x23,0xB8,0x17,0x02,0x25,0x40,0xC0,0x00,0x25,0x30,0xA0,0x00, + 0x25,0x28,0x80,0x00,0x00,0xB8,0x04,0x40,0x44,0xCE,0x04,0x7C,0x00,0xB8,0x84,0x40, + 0x00,0x48,0x80,0x40,0x40,0x00,0x00,0x00,0xC0,0x00,0x00,0x00,0x00,0x78,0x04,0x40, + 0x00,0x00,0x00,0x00,0x02,0x1C,0x04,0x00,0xFF,0x00,0x63,0x30,0x3B,0x00,0x60,0x10, + 0x00,0x00,0x00,0x00,0x81,0x00,0x11,0x04,0x00,0x00,0x00,0x00,0x00,0x80,0x04,0x40, + 0xF8,0xFF,0x02,0x24,0x24,0x20,0x82,0x00,0x03,0x00,0x84,0x34,0x00,0x80,0x84,0x40, + 0x07,0x80,0x04,0x40,0x10,0x00,0x02,0x3C,0x25,0x20,0x82,0x00,0x07,0x80,0x84,0x40, + 0x0C,0xBD,0x16,0x3C,0x28,0x20,0xC8,0x8E,0x02,0x10,0x04,0x40,0x00,0x18,0x87,0x7C, + 0x12,0x00,0xE0,0x14,0x00,0x00,0x00,0x00,0x10,0x00,0x00,0x15,0x00,0x00,0x00,0x00, + 0xFF,0x00,0x04,0x24,0x20,0x00,0xC4,0xAE,0xFF,0xFF,0x04,0x3C,0x90,0x00,0xC4,0xAE, + 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All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +*******************************************************************************/ + +/******************************************************************************* +** +** DESCRIPTION : This file is generated by img2c tool. +** Never try to change it manually. +** +*******************************************************************************/ + + + +/* Version Number: 03.04.02.03 */ + +const unsigned char spcv12g_ilaarray[] = +{ + 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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00, +}; diff --git a/sys/dev/pms/RefTisa/sallsdk/hda/64k/ilaimg.h b/sys/dev/pms/RefTisa/sallsdk/hda/64k/ilaimg.h new file mode 100644 index 000000000000..74c88d9e95f7 --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/hda/64k/ilaimg.h @@ -0,0 +1,3429 @@ + +/****************************************************************************** +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +*********************************************************************************/ + +/******************************************************************************* +** +** $RCSfile:$ +** +** $Date: 2010-12-22 14:50:54 -0800 (Wed, 22 Dec 2010) $ +** +** $Revision: 106769 $ +** +** $Author: lindfors $ +** +** DESCRIPTION : This file is generated by img2c tool. +** Nerver try to change it manually. +** +*******************************************************************************/ + + + +/* Version Number: 01.10.00.00 */ + +const unsigned char ilaarray[] = +{ + 0x01,0x00,0x11,0x04,0x00,0x00,0x00,0x00,0x25,0x80,0xE0,0x03,0xC0,0xBF,0x17,0x3C, + 0x08,0x00,0xF7,0x26,0x23,0xB8,0x17,0x02,0x40,0x00,0x08,0x3C,0x02,0x00,0x08,0x35, + 0x00,0x60,0x88,0x40,0x00,0x90,0x80,0x40,0x07,0x00,0x08,0x24,0x00,0x98,0x88,0x40, + 0x00,0x68,0x80,0x40,0x00,0x48,0x80,0x40,0xFF,0xFF,0x08,0x24,0x00,0x58,0x88,0x40, + 0x00,0x60,0x08,0x40,0x00,0x00,0x00,0x00,0x40,0x00,0x01,0x3C,0x25,0x40,0x01,0x01, + 0x00,0x60,0x88,0x40,0x00,0xE0,0x09,0x3C,0xF8,0x1F,0x29,0x25,0x21,0x48,0x30,0x01, + 0xFF,0x3F,0x01,0x3C,0x00,0xF0,0x21,0x34,0x24,0x48,0x21,0x01,0x01,0x78,0x89,0x40, + 0x00,0x00,0x01,0x3C,0xF8,0x04,0x21,0x24,0x21,0x08,0x30,0x00,0x09,0xF8,0x20,0x00, + 0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 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b/sys/dev/pms/RefTisa/sallsdk/hda/64k/iop8008.h new file mode 100644 index 000000000000..56282f1ae15c --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/hda/64k/iop8008.h @@ -0,0 +1,17642 @@ +/****************************************************************************** + +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +******************************************************************************/ + +/******************************************************************************* +** +** $RCSfile:$ +** +** $Date:$ +** +** $Revision:$ +** +** $Author:$ +** +** DESCRIPTION : This file is generated by img2c tool. +** Nerver try to change it manually. +** +*******************************************************************************/ + + + +/* Version Number: 02.09.24.00 */ + +const unsigned char spcv_ioparray[] = +{ + 0x7F,0x45,0x4C,0x46,0x01,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x02,0x00,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x10,0x10,0xBC,0x34,0x00,0x00,0x00, + 0xF4,0x3F,0x04,0x00,0x00,0x00,0x04,0x02,0x34,0x00,0x20,0x00,0x2C,0x00,0x28,0x00, + 0x3E,0x00,0x3D,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xC0,0x0F,0x9C, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x00,0x00,0x07,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x99, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0x00,0x00,0x07,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0x10,0x99, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0x00,0x00,0x07,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0x11,0x99, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0x00,0x00,0x07,0x00,0x00,0x00, + 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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +}; diff --git a/sys/dev/pms/RefTisa/sallsdk/hda/64k/iop8070.h b/sys/dev/pms/RefTisa/sallsdk/hda/64k/iop8070.h new file mode 100644 index 000000000000..0675f25cc1aa --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/hda/64k/iop8070.h @@ -0,0 +1,17450 @@ +/****************************************************************************** +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +******************************************************************************/ + +/******************************************************************************* +** +** DESCRIPTION : This file is generated by img2c tool. +** Never try to change it manually. +** +*******************************************************************************/ + + + +/* Version Number: 03.04.14.03 */ + +const unsigned char spcv12g_ioparray[] = +{ + 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a/sys/dev/pms/RefTisa/sallsdk/hda/64k/iopimg.h b/sys/dev/pms/RefTisa/sallsdk/hda/64k/iopimg.h new file mode 100644 index 000000000000..21150bc66a08 --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/hda/64k/iopimg.h @@ -0,0 +1,21584 @@ +/****************************************************************************** +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +******************************************************************************/ + +/******************************************************************************* +** +** $RCSfile:$ +** +** $Date: 2011-01-05 11:25:33 -0800 (Wed, 05 Jan 2011) $ +** +** $Revision: 106946 $ +** +** $Author: lindfors $ +** +** DESCRIPTION : This file is generated by img2c tool. +** Nerver try to change it manually. +** +*******************************************************************************/ + + + +/* Version Number: 01.10.10.00 */ + +const unsigned char ioparray[] = +{ + 0x7F,0x45,0x4C,0x46,0x01,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x02,0x00,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0xE0,0x9F,0x34,0x00,0x00,0x00, + 0x41,0x38,0x05,0x00,0x00,0x00,0x04,0x02,0x34,0x00,0x20,0x00,0x27,0x00,0x28,0x00, + 0x32,0x00,0x31,0x00,0x01,0x00,0x00,0x00,0x20,0x05,0x00,0x00,0x40,0x86,0xC8,0x9F, + 0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x05,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x20,0x06,0x00,0x00,0x40,0x87,0xC8,0x9F, + 0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x05,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0xA0,0x06,0x00,0x00,0xC0,0x87,0xC8,0x9F, + 0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x05,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0xA8,0x06,0x00,0x00,0x00,0x00,0xC0,0xBF, + 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a/sys/dev/pms/RefTisa/sallsdk/hda/64k/istrimg.h b/sys/dev/pms/RefTisa/sallsdk/hda/64k/istrimg.h new file mode 100644 index 000000000000..2f46133f7394 --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/hda/64k/istrimg.h @@ -0,0 +1,589 @@ +/****************************************************************************** +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +*******************************************************************************/ + +/******************************************************************************* +** +** $RCSfile:$ +** +** $Date: 2011-01-05 11:25:33 -0800 (Wed, 05 Jan 2011) $ +** +** $Revision: 106946 $ +** +** $Author: lindfors $ +** +** DESCRIPTION : This file is generated by img2c tool. +** Nerver try to change it manually. +** +*******************************************************************************/ + + + +/* Version Number: 01.10.10.00 */ + +const unsigned char istrarray[] = +{ + 0x01,0xA5,0x5A,0x96,0x69,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x08,0x00,0x00,0x06,0x01,0x01,0x40,0x40,0x00,0x40,0x00,0x40,0x04,0x00,0x01,0x00, + 0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x01,0x01,0x24,0x00,0x00,0x00, + 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All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +******************************************************************************/ + +/******************************************************************************* +** +** DESCRIPTION : This file is generated by img2c tool. +** Never try to change it manually. +** +*******************************************************************************/ + + + +/* Version Number: 03.04.14.03 */ + +const unsigned char spcv12g_raaearray[] = +{ + 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All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ + +/*******************************************************************************/ +/*! \file mpi.c + * \brief The file is a MPI Libraries to implement the MPI functions + * + * The file implements the MPI Library functions. + * + */ +/*******************************************************************************/ +#include +__FBSDID("$FreeBSD$"); +#include + +#include + +#ifdef SA_ENABLE_TRACE_FUNCTIONS +#ifdef siTraceFileID +#undef siTraceFileID +#endif +#define siTraceFileID 'A' +#endif + +#ifdef LOOPBACK_MPI +extern int loopback; +#endif +/*******************************************************************************/ + +/*******************************************************************************/ +/*******************************************************************************/ +/* FUNCTIONS */ +/*******************************************************************************/ +/*******************************************************************************/ +/** \fn void mpiRequirementsGet(mpiConfig_t* config, mpiMemReq_t* memoryRequirement) + * \brief Retrieves the MPI layer resource requirements + * \param config MPI configuration for the Host MPI Message Unit + * \param memoryRequirement Returned data structure as defined by mpiMemReq_t + * that holds the different chunks of memory that are required + * + * The mpiRequirementsGet() function is used to determine the resource requirements + * for the SPC device interface + * + * Return: None + */ +/*******************************************************************************/ +void mpiRequirementsGet(mpiConfig_t* config, mpiMemReq_t* memoryRequirement) +{ + bit32 qIdx, numq; + mpiMemReq_t* memoryMap; + SA_DBG2(("Entering function:mpiRequirementsGet\n")); + SA_ASSERT((NULL != config), "config argument cannot be null"); + + memoryMap = memoryRequirement; + memoryMap->count = 0; + + /* MPI Memory region 0 for MSGU(AAP1) Event Log for fw */ + memoryMap->region[memoryMap->count].numElements = 1; + memoryMap->region[memoryMap->count].elementSize = sizeof(bit8) * config->mainConfig.eventLogSize; + memoryMap->region[memoryMap->count].totalLength = sizeof(bit8) * config->mainConfig.eventLogSize; + memoryMap->region[memoryMap->count].alignment = 32; + memoryMap->region[memoryMap->count].type = AGSA_DMA_MEM; + SA_DBG2(("mpiRequirementsGet:eventLogSize region[%d] 0x%X\n",memoryMap->count,memoryMap->region[memoryMap->count].totalLength )); + memoryMap->count++; + + SA_DBG2(("mpiRequirementsGet:eventLogSize region[%d] 0x%X\n",memoryMap->count,memoryMap->region[memoryMap->count].totalLength )); + /* MPI Memory region 1 for IOP Event Log for fw */ + memoryMap->region[memoryMap->count].numElements = 1; + memoryMap->region[memoryMap->count].elementSize = sizeof(bit8) * config->mainConfig.IOPeventLogSize; + memoryMap->region[memoryMap->count].totalLength = sizeof(bit8) * config->mainConfig.IOPeventLogSize; + memoryMap->region[memoryMap->count].alignment = 32; + memoryMap->region[memoryMap->count].type = AGSA_DMA_MEM; + SA_DBG2(("mpiRequirementsGet:IOPeventLogSize region[%d] 0x%X\n",memoryMap->count,memoryMap->region[memoryMap->count].totalLength )); + memoryMap->count++; + + /* MPI Memory region 2 for consumer Index of inbound queues */ + memoryMap->region[memoryMap->count].numElements = 1; + memoryMap->region[memoryMap->count].elementSize = sizeof(bit32) * config->numInboundQueues; + memoryMap->region[memoryMap->count].totalLength = sizeof(bit32) * config->numInboundQueues; + memoryMap->region[memoryMap->count].alignment = 4; + memoryMap->region[memoryMap->count].type = AGSA_DMA_MEM; + SA_DBG2(("mpiRequirementsGet:numInboundQueues region[%d] 0x%X\n",memoryMap->count,memoryMap->region[memoryMap->count].totalLength )); + memoryMap->count++; + + /* MPI Memory region 3 for producer Index of outbound queues */ + memoryMap->region[memoryMap->count].numElements = 1; + memoryMap->region[memoryMap->count].elementSize = sizeof(bit32) * config->numOutboundQueues; + memoryMap->region[memoryMap->count].totalLength = sizeof(bit32) * config->numOutboundQueues; + memoryMap->region[memoryMap->count].alignment = 4; + memoryMap->region[memoryMap->count].type = AGSA_DMA_MEM; + SA_DBG2(("mpiRequirementsGet:numOutboundQueues region[%d] 0x%X\n",memoryMap->count,memoryMap->region[memoryMap->count].totalLength )); + memoryMap->count++; + + /* MPI Memory regions 4, ... for the inbound queues - depends on configuration */ + numq = 0; + for(qIdx = 0; qIdx < config->numInboundQueues; qIdx++) + { + if(0 != config->inboundQueues[qIdx].numElements) + { + bit32 memSize = config->inboundQueues[qIdx].numElements * config->inboundQueues[qIdx].elementSize; + bit32 remainder = memSize & 127; + + /* Calculate the size of this queue padded to 128 bytes */ + if (remainder > 0) + { + memSize += (128 - remainder); + } + + if (numq == 0) + { + memoryMap->region[memoryMap->count].numElements = 1; + memoryMap->region[memoryMap->count].elementSize = memSize; + memoryMap->region[memoryMap->count].totalLength = memSize; + memoryMap->region[memoryMap->count].alignment = 128; + memoryMap->region[memoryMap->count].type = AGSA_CACHED_DMA_MEM; + } + else + { + memoryMap->region[memoryMap->count].elementSize += memSize; + memoryMap->region[memoryMap->count].totalLength += memSize; + } + + numq++; + + if ((0 == ((qIdx + 1) % MAX_QUEUE_EACH_MEM)) || + (qIdx == (bit32)(config->numInboundQueues - 1))) + { + SA_DBG2(("mpiRequirementsGet: (inboundQueues) memoryMap->region[%d].elementSize = %d\n", + memoryMap->count, memoryMap->region[memoryMap->count].elementSize)); + SA_DBG2(("mpiRequirementsGet: (inboundQueues) memoryMap->region[%d].numElements = %d\n", + memoryMap->count, memoryMap->region[memoryMap->count].numElements)); + + memoryMap->count++; + numq = 0; + } + } + } + + /* MPI Memory regions for the outbound queues - depends on configuration */ + numq = 0; + for(qIdx = 0; qIdx < config->numOutboundQueues; qIdx++) + { + if(0 != config->outboundQueues[qIdx].numElements) + { + bit32 memSize = config->outboundQueues[qIdx].numElements * config->outboundQueues[qIdx].elementSize; + bit32 remainder = memSize & 127; + + /* Calculate the size of this queue padded to 128 bytes */ + if (remainder > 0) + { + memSize += (128 - remainder); + } + + if (numq == 0) + { + memoryMap->region[memoryMap->count].numElements = 1; + memoryMap->region[memoryMap->count].elementSize = memSize; + memoryMap->region[memoryMap->count].totalLength = memSize; + memoryMap->region[memoryMap->count].alignment = 128; + memoryMap->region[memoryMap->count].type = AGSA_CACHED_DMA_MEM; + } + else + { + memoryMap->region[memoryMap->count].elementSize += memSize; + memoryMap->region[memoryMap->count].totalLength += memSize; + } + + numq++; + + if ((0 == ((qIdx + 1) % MAX_QUEUE_EACH_MEM)) || + (qIdx == (bit32)(config->numOutboundQueues - 1))) + { + SA_DBG2(("mpiRequirementsGet: (outboundQueues) memoryMap->region[%d].elementSize = %d\n", + memoryMap->count, memoryMap->region[memoryMap->count].elementSize)); + SA_DBG2(("mpiRequirementsGet: (outboundQueues) memoryMap->region[%d].numElements = %d\n", + memoryMap->count, memoryMap->region[memoryMap->count].numElements)); + + + memoryMap->count++; + numq = 0; + } + } + } + +} + +/*******************************************************************************/ +/** \fn mpiMsgFreeGet(mpiICQueue_t *circularQ, bit16 messageSize, void** messagePtr) + * \brief Retrieves a free message buffer from an inbound queue + * \param circularQ Pointer to an inbound circular queue + * \param messageSize Requested message size in bytes - only support 64 bytes/element + * \param messagePtr Pointer to the free message buffer payload (not including message header) or NULL if no free message buffers are available + * + * This function is used to retrieve a free message buffer for the given inbound queue of at least + * messageSize bytes. + * The caller can use the returned buffer to construct the message and then call mpiMsgProduce() + * to deliver the message to the device message unit or mpiMsgInvalidate() if the message buffer + * is not going to be used + * + * Return: + * AGSA_RC_SUCCESS if messagePtr contains a valid message buffer pointer + * AGSA_RC_FAILURE if messageSize larger than the elementSize of queue + * AGSA_RC_BUSY if there are not free message buffers (Queue full) + */ +/*******************************************************************************/ +GLOBAL FORCEINLINE +bit32 +mpiMsgFreeGet( + mpiICQueue_t *circularQ, + bit16 messageSize, + void** messagePtr + ) +{ + bit32 offset; + agsaRoot_t *agRoot=circularQ->agRoot; + mpiMsgHeader_t *msgHeader; + bit8 bcCount = 1; /* only support single buffer */ + + SA_DBG4(("Entering function:mpiMsgFreeGet\n")); + SA_ASSERT(NULL != circularQ, "circularQ cannot be null"); + SA_ASSERT(NULL != messagePtr, "messagePtr argument cannot be null"); + SA_ASSERT(0 != circularQ->numElements, "The number of elements in this queue is 0"); + + /* Checks is the requested message size can be allocated in this queue */ + if(messageSize > circularQ->elementSize) + { + SA_DBG1(("mpiMsgFreeGet: Message Size (%d) is larger than Q element size (%d)\n",messageSize,circularQ->elementSize)); + return AGSA_RC_FAILURE; + } + + /* Stores the new consumer index */ + OSSA_READ_LE_32(circularQ->agRoot, &circularQ->consumerIdx, circularQ->ciPointer, 0); + /* if inbound queue is full, return busy */ + /* This queue full logic may only works for bc == 1 ( == ) */ + /* ( pi + bc ) % size > ci not fully works for bc > 1 */ + /* To do - support bc > 1 case and wrap around case */ + if (((circularQ->producerIdx + bcCount) % circularQ->numElements) == circularQ->consumerIdx) + { + *messagePtr = NULL; + smTrace(hpDBG_VERY_LOUD,"Za", (((circularQ->producerIdx & 0xFFF) << 16) | (circularQ->consumerIdx & 0xFFF) )); + /* TP:Za IQ PI CI */ + ossaHwRegRead(agRoot, MSGU_HOST_SCRATCH_PAD_0); + SA_DBG1(("mpiMsgFreeGet: %d + %d == %d AGSA_RC_BUSY\n",circularQ->producerIdx,bcCount,circularQ->consumerIdx)); + + return AGSA_RC_BUSY; + } + + smTrace(hpDBG_VERY_LOUD,"Zb", (((circularQ->producerIdx & 0xFFF) << 16) | (circularQ->consumerIdx & 0xFFF) )); + /* TP:Zb IQ PI CI */ + + + /* get memory IOMB buffer address */ + offset = circularQ->producerIdx * circularQ->elementSize; + /* increment to next bcCount element */ + circularQ->producerIdx = (circularQ->producerIdx + bcCount) % circularQ->numElements; + + /* Adds that distance to the base of the region virtual address plus the message header size*/ + msgHeader = (mpiMsgHeader_t*) (((bit8 *)(circularQ->memoryRegion.virtPtr)) + offset); + + SA_DBG3(("mpiMsgFreeGet: msgHeader = %p Offset = 0x%x\n", (void *)msgHeader, offset)); + + /* Sets the message buffer in "allocated" state */ + /* bc always is 1 for inbound queue */ + /* temporarily store it in the native endian format, when the rest of the */ + /* header is filled, this would be converted to Little Endian */ + msgHeader->Header = (1<<24); + *messagePtr = ((bit8*)msgHeader) + sizeof(mpiMsgHeader_t); + + return AGSA_RC_SUCCESS; +} + +#ifdef LOOPBACK_MPI +GLOBAL bit32 mpiMsgFreeGetOQ(mpiOCQueue_t *circularQ, bit16 messageSize, void** messagePtr) +{ + bit32 offset; + mpiMsgHeader_t *msgHeader; + bit8 bcCount = 1; /* only support single buffer */ + + SA_DBG4(("Entering function:mpiMsgFreeGet\n")); + SA_ASSERT(NULL != circularQ, "circularQ cannot be null"); + SA_ASSERT(NULL != messagePtr, "messagePtr argument cannot be null"); + SA_ASSERT(0 != circularQ->numElements, "The number of elements in this queue is 0"); + + /* Checks is the requested message size can be allocated in this queue */ + if(messageSize > circularQ->elementSize) + { + SA_DBG1(("mpiMsgFreeGet: Message Size is not fit in\n")); + return AGSA_RC_FAILURE; + } + + /* Stores the new consumer index */ + //OSSA_READ_LE_32(circularQ->agRoot, &circularQ->consumerIdx, circularQ->ciPointer, 0); + /* if inbound queue is full, return busy */ + /* This queue full logic may only works for bc == 1 ( == ) */ + /* ( pi + bc ) % size > ci not fully works for bc > 1 */ + /* To do - support bc > 1 case and wrap around case */ + if (((circularQ->producerIdx + bcCount) % circularQ->numElements) == circularQ->consumerIdx) + { + *messagePtr = NULL; + return AGSA_RC_BUSY; + } + + /* get memory IOMB buffer address */ + offset = circularQ->producerIdx * circularQ->elementSize; + /* increment to next bcCount element */ + circularQ->producerIdx = (circularQ->producerIdx + bcCount) % circularQ->numElements; + + /* Adds that distance to the base of the region virtual address plus the message header size*/ + msgHeader = (mpiMsgHeader_t*) (((bit8 *)(circularQ->memoryRegion.virtPtr)) + offset); + + SA_DBG3(("mpiMsgFreeGet: msgHeader = %p Offset = 0x%x\n", (void *)msgHeader, offset)); + + /* Sets the message buffer in "allocated" state */ + /* bc always is 1 for inbound queue */ + /* temporarily store it in the native endian format, when the rest of the */ + /* header is filled, this would be converted to Little Endian */ + msgHeader->Header = (1<<24); + *messagePtr = ((bit8*)msgHeader) + sizeof(mpiMsgHeader_t); + + return AGSA_RC_SUCCESS; +} +#endif + +/*******************************************************************************/ +/** \fn mpiMsgProduce(mpiICQueue_t *circularQ, void *messagePtr, mpiMsgCategory_t category, bit16 opCode, bit8 responseQueue) + * \brief Add a header of IOMB then send to a inbound queue and update the Producer index + * \param circularQ Pointer to an inbound queue + * \param messagePtr Pointer to the message buffer payload (not including message header)) + * \param category Message category (ETHERNET, FC, SAS-SATA, SCSI) + * \param opCode Message operation code + * \param responseQueue If the message requires response, this paramater indicates the outbound queue for the response + * + * This function is used to sumit a message buffer, previously obtained from mpiMsgFreeGet() + * function call, to the given Inbound queue + * + * Return: + * AGSA_RC_SUCCESS if the message has been posted succesfully + */ +/*******************************************************************************/ +#ifdef FAST_IO_TEST +GLOBAL bit32 mpiMsgPrepare( + mpiICQueue_t *circularQ, + void *messagePtr, + mpiMsgCategory_t category, + bit16 opCode, + bit8 responseQueue, + bit8 hiPriority + ) +{ + mpiMsgHeader_t *msgHeader; + bit32 bc; + bit32 Header = 0; + bit32 hpriority = 0; + + SA_DBG4(("Entering function:mpiMsgProduce\n")); + SA_ASSERT(NULL != circularQ, "circularQ argument cannot be null"); + SA_ASSERT(NULL != messagePtr, "messagePtr argument cannot be null"); + SA_ASSERT(0 != circularQ->numElements, "The number of elements in this queue" + " is 0"); + SA_ASSERT(MPI_MAX_OUTBOUND_QUEUES > responseQueue, "oQueue ID is wrong"); + + /* Obtains the address of the entire message buffer, including the header */ + msgHeader = (mpiMsgHeader_t*)(((bit8*)messagePtr) - sizeof(mpiMsgHeader_t)); + /* Read the BC from header, its stored in native endian format when message + was allocated */ + /* intially */ + bc = (((msgHeader->Header) >> SHIFT24) & BC_MASK); + SA_DBG6(("mpiMsgProduce: msgHeader bc %d\n", bc)); + if (circularQ->priority) + hpriority = 1; + + /* Checks the message is in "allocated" state */ + SA_ASSERT(0 != bc, "The message buffer is not in \"allocated\" state " + "(bc == 0)"); + + Header = ((V_BIT << SHIFT31) | (hpriority << SHIFT30) | + ((bc & BC_MASK) << SHIFT24) | + ((responseQueue & OBID_MASK) << SHIFT16) | + ((category & CAT_MASK) << SHIFT12 ) | (opCode & OPCODE_MASK)); + + /* pre flush the IOMB cache line */ + ossaCachePreFlush(circularQ->agRoot, + (void *)circularQ->memoryRegion.appHandle, + (void *)msgHeader, circularQ->elementSize * bc); + OSSA_WRITE_LE_32(circularQ->agRoot, msgHeader, OSSA_OFFSET_OF(mpiMsgHeader_t, + Header), Header); + /* flush the IOMB cache line */ + ossaCacheFlush(circularQ->agRoot, (void *)circularQ->memoryRegion.appHandle, + (void *)msgHeader, circularQ->elementSize * bc); + + MPI_DEBUG_TRACE( circularQ->qNumber, + ((circularQ->producerIdx << 16 ) | circularQ->consumerIdx), + MPI_DEBUG_TRACE_IBQ, + (void *)msgHeader, + circularQ->elementSize); + + ossaLogIomb(circularQ->agRoot, + circularQ->qNumber, + TRUE, + (void *)msgHeader, + circularQ->elementSize); + + return AGSA_RC_SUCCESS; +} /* mpiMsgPrepare */ + +GLOBAL bit32 mpiMsgProduce( + mpiICQueue_t *circularQ, + void *messagePtr, + mpiMsgCategory_t category, + bit16 opCode, + bit8 responseQueue, + bit8 hiPriority + ) +{ + bit32 ret; + + ret = mpiMsgPrepare(circularQ, messagePtr, category, opCode, responseQueue, + hiPriority); + if (ret == AGSA_RC_SUCCESS) + { + /* update PI of inbound queue */ + ossaHwRegWriteExt(circularQ->agRoot, + circularQ->PIPCIBar, + circularQ->PIPCIOffset, + circularQ->producerIdx); + } + return ret; +} + +GLOBAL void mpiIBQMsgSend(mpiICQueue_t *circularQ) +{ + ossaHwRegWriteExt(circularQ->agRoot, + circularQ->PIPCIBar, + circularQ->PIPCIOffset, + circularQ->producerIdx); +} +#else /* FAST_IO_TEST */ + +GLOBAL FORCEINLINE +bit32 +mpiMsgProduce( + mpiICQueue_t *circularQ, + void *messagePtr, + mpiMsgCategory_t category, + bit16 opCode, + bit8 responseQueue, + bit8 hiPriority + ) +{ + mpiMsgHeader_t *msgHeader; + bit32 bc; + bit32 Header = 0; + bit32 hpriority = 0; + +#ifdef SA_FW_TEST_BUNCH_STARTS +#define Need_agRootDefined 1 +#endif /* SA_FW_TEST_BUNCH_STARTS */ + +#ifdef SA_ENABLE_TRACE_FUNCTIONS + bit32 i; +#define Need_agRootDefined 1 +#endif /* SA_ENABLE_TRACE_FUNCTIONS */ + +#ifdef MPI_DEBUG_TRACE_ENABLE +#define Need_agRootDefined 1 +#endif /* MPI_DEBUG_TRACE_ENABLE */ + +#ifdef Need_agRootDefined + agsaRoot_t *agRoot=circularQ->agRoot; +#ifdef SA_FW_TEST_BUNCH_STARTS + agsaLLRoot_t *saRoot = agNULL; + saRoot = agRoot->sdkData; +#endif /* SA_FW_TEST_BUNCH_STARTS */ + +#undef Need_agRootDefined +#endif /* Need_agRootDefined */ + + SA_DBG4(("Entering function:mpiMsgProduce\n")); + SA_ASSERT(NULL != circularQ, "circularQ argument cannot be null"); + SA_ASSERT(NULL != messagePtr, "messagePtr argument cannot be null"); + SA_ASSERT(0 != circularQ->numElements, "The number of elements in this queue is 0"); + SA_ASSERT(MPI_MAX_OUTBOUND_QUEUES > responseQueue, "oQueue ID is wrong"); + + /* REB Start extra trace */ + smTraceFuncEnter(hpDBG_VERY_LOUD,"22"); + /* REB End extra trace */ + + /* Obtains the address of the entire message buffer, including the header */ + msgHeader = (mpiMsgHeader_t*)(((bit8*)messagePtr) - sizeof(mpiMsgHeader_t)); + /* Read the BC from header, its stored in native endian format when message was allocated */ + /* intially */ + bc = (((msgHeader->Header) >> SHIFT24) & BC_MASK); + SA_DBG6(("mpiMsgProduce: msgHeader bc %d\n", bc)); + if (circularQ->priority) + { + hpriority = 1; + } + + /* Checks the message is in "allocated" state */ + SA_ASSERT(0 != bc, "The message buffer is not in \"allocated\" state (bc == 0)"); + + Header = ((V_BIT << SHIFT31) | + (hpriority << SHIFT30) | + ((bc & BC_MASK) << SHIFT24) | + ((responseQueue & OBID_MASK) << SHIFT16) | + ((category & CAT_MASK) << SHIFT12 ) | + (opCode & OPCODE_MASK)); + + /* pre flush the cache line */ + ossaCachePreFlush(circularQ->agRoot, (void *)circularQ->memoryRegion.appHandle, (void *)msgHeader, circularQ->elementSize * bc); + OSSA_WRITE_LE_32(circularQ->agRoot, msgHeader, OSSA_OFFSET_OF(mpiMsgHeader_t, Header), Header); + /* flush the cache line for IOMB */ + ossaCacheFlush(circularQ->agRoot, (void *)circularQ->memoryRegion.appHandle, (void *)msgHeader, circularQ->elementSize * bc); + + MPI_DEBUG_TRACE( circularQ->qNumber, + ((circularQ->producerIdx << 16 ) | circularQ->consumerIdx), + MPI_DEBUG_TRACE_IBQ, + (void *)msgHeader, + circularQ->elementSize); + + ossaLogIomb(circularQ->agRoot, + circularQ->qNumber, + TRUE, + (void *)msgHeader, + circularQ->elementSize); + +#if defined(SALLSDK_DEBUG) + MPI_IBQ_IOMB_LOG(circularQ->qNumber, (void *)msgHeader, circularQ->elementSize); +#endif /* SALLSDK_DEBUG */ + /* REB Start extra trace */ +#ifdef SA_ENABLE_TRACE_FUNCTIONS + smTrace(hpDBG_IOMB,"M1",circularQ->qNumber); + /* TP:M1 circularQ->qNumber */ + for (i=0; i<((bit32)bc*(circularQ->elementSize/4)); i++) + { + /* The -sizeof(mpiMsgHeader_t) is to account for mpiMsgProduce adding the header to the pMessage pointer */ + smTrace(hpDBG_IOMB,"MD",*( ((bit32 *)((bit8 *)messagePtr - sizeof(mpiMsgHeader_t))) + i)); + /* TP:MD Inbound IOMB Dword */ + } +#endif /* SA_ENABLE_TRACE_FUNCTIONS */ + + /* update PI of inbound queue */ + +#ifdef SA_FW_TEST_BUNCH_STARTS + if(saRoot->BunchStarts_Enable) + { + if (circularQ->BunchStarts_QPending == 0) + { + // store tick value for 1st deferred IO only + circularQ->BunchStarts_QPendingTick = saRoot->timeTick; + } + // update queue's pending count + circularQ->BunchStarts_QPending++; + + // update global pending count + saRoot->BunchStarts_Pending++; + + SA_DBG1(("mpiMsgProduce: BunchStarts - Global Pending %d\n", saRoot->BunchStarts_Pending)); + SA_DBG1(("mpiMsgProduce: BunchStarts - QPending %d, Q-%d\n", circularQ->BunchStarts_QPending, circularQ->qNumber)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "22"); + + return AGSA_RC_SUCCESS; + } + + saRoot->BunchStarts_Pending = 0; + circularQ->BunchStarts_QPending = 0; +#endif /* SA_FW_TEST_BUNCH_STARTS */ + ossaHwRegWriteExt(circularQ->agRoot, + circularQ->PIPCIBar, + circularQ->PIPCIOffset, + circularQ->producerIdx); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "22"); + + return AGSA_RC_SUCCESS; +} /* mpiMsgProduce */ +#endif /* FAST_IO_TEST */ + +#ifdef SA_FW_TEST_BUNCH_STARTS + +void mpiMsgProduceBunch( agsaLLRoot_t *saRoot) +{ + mpiICQueue_t *circularQ; + bit32 inq; + + for(inq=0; ((inq < saRoot->QueueConfig.numInboundQueues) && saRoot->BunchStarts_Pending); inq++) + { + circularQ= &saRoot->inboundQueue[inq]; + /* If any pending IOs present then either process if BunchStarts_Threshold + * IO limit reached or if the timer has popped + */ + if (circularQ->BunchStarts_QPending && + ((circularQ->BunchStarts_QPending >= saRoot->BunchStarts_Threshold) || + ((saRoot->timeTick - circularQ->BunchStarts_QPendingTick) >= saRoot->BunchStarts_TimeoutTicks)) + ) + { + if(circularQ->qNumber != inq) + { + SA_DBG1(("mpiMsgProduceBunch:circularQ->qNumber(%d) != inq(%d)\n",circularQ->qNumber, inq)); + } + + SA_DBG1(("mpiMsgProduceBunch: IQ=%d, PI=%d\n", inq, circularQ->producerIdx)); + SA_DBG1(("mpiMsgProduceBunch: Qpending=%d, TotPending=%d\n", circularQ->BunchStarts_QPending, saRoot->BunchStarts_Pending)); + + ossaHwRegWriteExt(circularQ->agRoot, + circularQ->PIPCIBar, + circularQ->PIPCIOffset, + circularQ->producerIdx); + + // update global pending count + saRoot->BunchStarts_Pending -= circularQ->BunchStarts_QPending; + + // clear current queue's pending count after processing + circularQ->BunchStarts_QPending = 0; + circularQ->BunchStarts_QPendingTick = saRoot->timeTick; + } + } +} +#endif /* SA_FW_TEST_BUNCH_STARTS */ + +/*******************************************************************************/ +/** \fn mpiMsgConsume(mpiOCQueue_t *circularQ, void *messagePtr1, + * mpiMsgCategory_t * pCategory, bit16 * pOpCode, bit8 * pBC) + * \brief Get a received message + * \param circularQ Pointer to a outbound queue + * \param messagePtr1 Pointer to the returned message buffer or NULL if no valid message + * \param pCategory Pointer to Message category (ETHERNET, FC, SAS-SATA, SCSI) + * \param pOpCode Pointer to Message operation code + * \param pBC Pointer to buffer count + * + * Consume a receive message in the specified outbound queue + * + * Return: + * AGSA_RC_SUCCESS if the message has been retrieved succesfully + * AGSA_RC_BUSY if the circular is empty + */ +/*******************************************************************************/ +GLOBAL FORCEINLINE +bit32 +mpiMsgConsume( + mpiOCQueue_t *circularQ, + void ** messagePtr1, + mpiMsgCategory_t *pCategory, + bit16 *pOpCode, + bit8 *pBC + ) +{ + mpiMsgHeader_t *msgHeader; + bit32 msgHeader_tmp; + + SA_ASSERT(NULL != circularQ, "circularQ argument cannot be null"); + SA_ASSERT(NULL != messagePtr1, "messagePtr1 argument cannot be null"); + SA_ASSERT(NULL != pCategory, "pCategory argument cannot be null"); + SA_ASSERT(NULL != pOpCode, "pOpCode argument cannot be null"); + SA_ASSERT(NULL != pBC, "pBC argument cannot be null"); + SA_ASSERT(0 != circularQ->numElements, "The number of elements in this queue is 0"); + + do + { + /* If there are not-yet-delivered messages ... */ + if(circularQ->producerIdx != circularQ->consumerIdx) + { + /* Get the pointer to the circular queue buffer element */ + msgHeader = (mpiMsgHeader_t*) ((bit8 *)(circularQ->memoryRegion.virtPtr) + circularQ->consumerIdx * circularQ->elementSize); + +#ifdef LOOPBACK_MPI + if (!loopback) +#endif + /* invalidate the cache line of IOMB */ + ossaCacheInvalidate(circularQ->agRoot, (void *)circularQ->memoryRegion.appHandle, (void *)msgHeader, circularQ->elementSize); + + + /* read header */ + OSSA_READ_LE_32(circularQ->agRoot, &msgHeader_tmp, msgHeader, 0); + + SA_DBG4(("mpiMsgConsume: process an IOMB, header=0x%x\n", msgHeader_tmp)); + + SA_ASSERT(0 != (msgHeader_tmp & HEADER_BC_MASK), "The bc field in the header is 0"); +#ifdef TEST + /* for debugging */ + if (0 == (msgHeader_tmp & HEADER_BC_MASK)) + { + SA_DBG1(("mpiMsgConsume: CI=%d PI=%d msgHeader=%p\n", circularQ->consumerIdx, circularQ->producerIdx, (void *)msgHeader)); + circularQ->consumerIdx = (circularQ->consumerIdx + 1) % circularQ->numElements; + /* update the CI of outbound queue - skip this blank IOMB, for test only */ + ossaHwRegWriteExt(circularQ->agRoot, + circularQ->CIPCIBar, + circularQ->CIPCIOffset, + circularQ->consumerIdx); + return AGSA_RC_FAILURE; + } +#endif + /* get message pointer of valid entry */ + if (0 != (msgHeader_tmp & HEADER_V_MASK)) + { + SA_ASSERT(circularQ->consumerIdx <= circularQ->numElements, "Multi-buffer messages cannot wrap around"); + + if (OPC_OUB_SKIP_ENTRY != (msgHeader_tmp & OPCODE_MASK)) + { + /* ... return the message payload */ + *messagePtr1 = ((bit8*)msgHeader) + sizeof(mpiMsgHeader_t); + *pCategory = (mpiMsgCategory_t)(msgHeader_tmp >> SHIFT12) & CAT_MASK; + *pOpCode = (bit16)(msgHeader_tmp & OPCODE_MASK); + *pBC = (bit8)((msgHeader_tmp >> SHIFT24) & BC_MASK); + + /* invalidate the cache line for IOMB */ +#ifdef LOOPBACK_MPI + if (!loopback) +#endif + ossaCacheInvalidate(circularQ->agRoot, (void *)circularQ->memoryRegion.appHandle, (void *)msgHeader, (*pBC - 1) * circularQ->elementSize); + +#if defined(SALLSDK_DEBUG) + SA_DBG3(("mpiMsgConsume: CI=%d PI=%d msgHeader=%p\n", circularQ->consumerIdx, circularQ->producerIdx, (void *)msgHeader)); + MPI_OBQ_IOMB_LOG(circularQ->qNumber, (void *)msgHeader, circularQ->elementSize); +#endif + return AGSA_RC_SUCCESS; + } + else + { + SA_DBG3(("mpiMsgConsume: SKIP_ENTRIES_IOMB BC=%d\n", (msgHeader_tmp >> SHIFT24) & BC_MASK)); + /* Updated comsumerIdx and skip it */ + circularQ->consumerIdx = (circularQ->consumerIdx + ((msgHeader_tmp >> SHIFT24) & BC_MASK)) % circularQ->numElements; + /* clean header to 0 */ + msgHeader_tmp = 0; + /*ossaSingleThreadedEnter(agRoot, LL_IOREQ_OBQ_LOCK);*/ + + OSSA_WRITE_LE_32(circularQ->agRoot, msgHeader, OSSA_OFFSET_OF(mpiMsgHeader_t, Header), msgHeader_tmp); + + /* update the CI of outbound queue */ + ossaHwRegWriteExt(circularQ->agRoot, + circularQ->CIPCIBar, + circularQ->CIPCIOffset, + circularQ->consumerIdx); + /* Update the producer index */ + OSSA_READ_LE_32(circularQ->agRoot, &circularQ->producerIdx, circularQ->piPointer, 0); + /*ossaSingleThreadedLeave(agRoot, LL_IOREQ_OBQ_LOCK); */ + } + } + else + { + /* V bit is not set */ +#if defined(SALLSDK_DEBUG) + agsaRoot_t *agRoot=circularQ->agRoot; + SA_DBG1(("mpiMsgConsume: V bit not set, PI=%d CI=%d msgHeader=%p\n", circularQ->producerIdx, circularQ->consumerIdx,(void *)msgHeader)); + SA_DBG1(("mpiMsgConsume: V bit not set, 0x%08X Q=%d \n", msgHeader_tmp, circularQ->qNumber)); + + MPI_DEBUG_TRACE(MPI_DEBUG_TRACE_QNUM_ERROR + circularQ->qNumber, + ((circularQ->producerIdx << 16 ) | circularQ->consumerIdx), + MPI_DEBUG_TRACE_OBQ, + (void *)(((bit8*)msgHeader) - sizeof(mpiMsgHeader_t)), + circularQ->elementSize); + + circularQ->consumerIdx = circularQ->consumerIdx % circularQ->numElements; + circularQ->consumerIdx ++; + OSSA_WRITE_LE_32(circularQ->agRoot, msgHeader, OSSA_OFFSET_OF(mpiMsgHeader_t, Header), msgHeader_tmp); + ossaHwRegWriteExt(agRoot, + circularQ->CIPCIBar, + circularQ->CIPCIOffset, + circularQ->consumerIdx); + MPI_OBQ_IOMB_LOG(circularQ->qNumber, (void *)msgHeader, circularQ->elementSize); +#endif + SA_DBG1(("mpiMsgConsume: V bit is not set!!!!! HW CI=%d\n", ossaHwRegReadExt(circularQ->agRoot, circularQ->CIPCIBar, circularQ->CIPCIOffset) )); + SA_ASSERT(0, "V bit is not set"); + return AGSA_RC_FAILURE; + } + } + else + { + /* Update the producer index from SPC */ + OSSA_READ_LE_32(circularQ->agRoot, &circularQ->producerIdx, circularQ->piPointer, 0); + } + } while(circularQ->producerIdx != circularQ->consumerIdx); /* while we don't have any more not-yet-delivered message */ + +#ifdef TEST + SA_DBG4(("mpiMsgConsume: Outbound queue is empty.\n")); +#endif + + /* report empty */ + return AGSA_RC_BUSY; +} + +/*******************************************************************************/ +/** \fn mpiMsgFreeSet(mpiOCQueue_t *circularQ, void *messagePtr) + * \brief Returns a received message to the outbound queue + * \param circularQ Pointer to an outbound queue + * \param messagePtr1 Pointer to the returned message buffer to free + * \param messagePtr2 Pointer to the returned message buffer to free if bc > 1 + * + * Returns consumed and processed message to the the specified outbounf queue + * + * Return: + * AGSA_RC_SUCCESS if the message has been returned succesfully + */ +/*******************************************************************************/ +GLOBAL FORCEINLINE +bit32 +mpiMsgFreeSet( + mpiOCQueue_t *circularQ, + void *messagePtr1, + bit8 bc + ) +{ + mpiMsgHeader_t *msgHeader; + + SA_DBG4(("Entering function:mpiMsgFreeSet\n")); + SA_ASSERT(NULL != circularQ, "circularQ argument cannot be null"); + SA_ASSERT(NULL != messagePtr1, "messagePtr1 argument cannot be null"); + SA_ASSERT(0 != circularQ->numElements, "The number of elements in this queue is 0"); + + /* Obtains the address of the entire message buffer, including the header */ + msgHeader = (mpiMsgHeader_t*)(((bit8*)messagePtr1) - sizeof(mpiMsgHeader_t)); + + if ( ((mpiMsgHeader_t*)((bit8*)circularQ->memoryRegion.virtPtr + circularQ->consumerIdx * circularQ->elementSize)) != msgHeader) + { + /* IOMB of CI points mismatch with Message Header - should never happened */ + SA_DBG1(("mpiMsgFreeSet: Wrong CI, Q %d ConsumeIdx = %d msgHeader 0x%08x\n",circularQ->qNumber, circularQ->consumerIdx ,msgHeader->Header)); + SA_DBG1(("mpiMsgFreeSet: msgHeader %p != %p\n", msgHeader,((mpiMsgHeader_t*)((bit8*)circularQ->memoryRegion.virtPtr + circularQ->consumerIdx * circularQ->elementSize)))); + +#ifdef LOOPBACK_MPI + if (!loopback) +#endif + /* Update the producer index from SPC */ + OSSA_READ_LE_32(circularQ->agRoot, &circularQ->producerIdx, circularQ->piPointer, 0); +#if defined(SALLSDK_DEBUG) + SA_DBG3(("mpiMsgFreeSet: ProducerIdx = %d\n", circularQ->producerIdx)); +#endif + return AGSA_RC_SUCCESS; + } + + /* ... free the circular queue buffer elements associated with the message ... */ + /*... by incrementing the consumer index (with wrap arround) */ + circularQ->consumerIdx = (circularQ->consumerIdx + bc) % circularQ->numElements; + + /* Invalidates this circular queue buffer element */ + + msgHeader->Header &= ~HEADER_V_MASK; /* Clear Valid bit to indicate IOMB consumed by host */ + SA_ASSERT(circularQ->consumerIdx <= circularQ->numElements, "Multi-buffer messages cannot wrap arround"); + + /* update the CI of outbound queue */ +#ifdef LOOPBACK_MPI + if (!loopback) +#endif + { + ossaHwRegWriteExt(circularQ->agRoot, + circularQ->CIPCIBar, + circularQ->CIPCIOffset, + circularQ->consumerIdx); + + /* Update the producer index from SPC */ + OSSA_READ_LE_32(circularQ->agRoot, &circularQ->producerIdx, circularQ->piPointer, 0); + } +#if defined(SALLSDK_DEBUG) + SA_DBG5(("mpiMsgFreeSet: CI=%d PI=%d\n", circularQ->consumerIdx, circularQ->producerIdx)); +#endif + return AGSA_RC_SUCCESS; +} + +#ifdef TEST +GLOBAL bit32 mpiRotateQnumber(agsaRoot_t *agRoot) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + bit32 denom; + bit32 ret = 0; + + /* inbound queue number */ + saRoot->IBQnumber++; + denom = saRoot->QueueConfig.numInboundQueues; + if (saRoot->IBQnumber % denom == 0) /* % Qnumber*/ + { + saRoot->IBQnumber = 0; + } + SA_DBG3(("mpiRotateQnumber: IBQnumber %d\n", saRoot->IBQnumber)); + + /* outbound queue number */ + saRoot->OBQnumber++; + denom = saRoot->QueueConfig.numOutboundQueues; + if (saRoot->OBQnumber % denom == 0) /* % Qnumber*/ + { + saRoot->OBQnumber = 0; + } + SA_DBG3(("mpiRotateQnumber: OBQnumber %d\n", saRoot->OBQnumber)); + + ret = (saRoot->OBQnumber << SHIFT16) | saRoot->IBQnumber; + return ret; +} +#endif + +#ifdef LOOPBACK_MPI +GLOBAL bit32 mpiMsgProduceOQ( + mpiOCQueue_t *circularQ, + void *messagePtr, + mpiMsgCategory_t category, + bit16 opCode, + bit8 responseQueue, + bit8 hiPriority + ) +{ + mpiMsgHeader_t *msgHeader; + bit32 bc; + bit32 Header = 0; + bit32 hpriority = 0; + + SA_DBG4(("Entering function:mpiMsgProduceOQ\n")); + SA_ASSERT(NULL != circularQ, "circularQ argument cannot be null"); + SA_ASSERT(NULL != messagePtr, "messagePtr argument cannot be null"); + SA_ASSERT(0 != circularQ->numElements, "The number of elements in this queue" + " is 0"); + SA_ASSERT(MPI_MAX_OUTBOUND_QUEUES > responseQueue, "oQueue ID is wrong"); + + /* REB Start extra trace */ + smTraceFuncEnter(hpDBG_VERY_LOUD, "2I"); + /* REB End extra trace */ + + /* Obtains the address of the entire message buffer, including the header */ + msgHeader = (mpiMsgHeader_t*)(((bit8*)messagePtr) - sizeof(mpiMsgHeader_t)); + /* Read the BC from header, its stored in native endian format when message + was allocated */ + /* intially */ + SA_DBG4(("mpiMsgProduceOQ: msgHeader %p opcode %d pi/ci %d / %d\n", msgHeader, opCode, circularQ->producerIdx, circularQ->consumerIdx)); + bc = (((msgHeader->Header) >> SHIFT24) & BC_MASK); + SA_DBG6(("mpiMsgProduceOQ: msgHeader bc %d\n", bc)); + if (circularQ->priority) + hpriority = 1; + + /* Checks the message is in "allocated" state */ + SA_ASSERT(0 != bc, "The message buffer is not in \"allocated\" state " + "(bc == 0)"); + + Header = ((V_BIT << SHIFT31) | (hpriority << SHIFT30) | + ((bc & BC_MASK) << SHIFT24) | + ((responseQueue & OBID_MASK) << SHIFT16) | + ((category & CAT_MASK) << SHIFT12 ) | (opCode & OPCODE_MASK)); + /* pre flush the IOMB cache line */ + //ossaCachePreFlush(circularQ->agRoot, + // (void *)circularQ->memoryRegion.appHandle, + // (void *)msgHeader, circularQ->elementSize * bc); + OSSA_WRITE_LE_32(circularQ->agRoot, msgHeader, OSSA_OFFSET_OF(mpiMsgHeader_t, + Header), Header); + + /* flush the IOMB cache line */ + //ossaCacheFlush(circularQ->agRoot, (void *)circularQ->memoryRegion.appHandle, + // (void *)msgHeader, circularQ->elementSize * bc); + + MPI_DEBUG_TRACE( circularQ->qNumber, + ((circularQ->producerIdx << 16 ) | circularQ->consumerIdx), + MPI_DEBUG_TRACE_OBQ, + (void *)msgHeader, + circularQ->elementSize); + + ossaLogIomb(circularQ->agRoot, + circularQ->qNumber, + TRUE, + (void *)msgHeader, + circularQ->elementSize); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2I"); + return AGSA_RC_SUCCESS; +} /* mpiMsgProduceOQ */ +#endif + diff --git a/sys/dev/pms/RefTisa/sallsdk/spc/mpi.h b/sys/dev/pms/RefTisa/sallsdk/spc/mpi.h new file mode 100644 index 000000000000..b727f25f0887 --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/spc/mpi.h @@ -0,0 +1,476 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ + +/*******************************************************************************/ +/*! \file mpi.h + * \brief The file defines the MPI constants and structures + * + * The file defines the MPI constants and structures + * + */ +/*******************************************************************************/ + +#ifndef __MPI_H__ +#define __MPI_H__ + +/*******************************************************************************/ + +/*******************************************************************************/ +/* CONSTANTS */ +/*******************************************************************************/ +/*******************************************************************************/ +#define MPI_QUEUE_PRIORITY_HIGHEST 0xFF /**< Highest queue priority */ +#define MPI_QUEUE_PRIORITY_LOWEST 0x00 /**< Lowest queue priority */ + +#define MPI_MAX_INBOUND_QUEUES 64 /**< Maximum number of inbound queues */ +#define MPI_MAX_OUTBOUND_QUEUES 64 /**< Maximum number of outbound queues */ + + /**< Max # of memory chunks supported */ +#define MPI_MAX_MEM_REGIONS (MPI_MAX_INBOUND_QUEUES + MPI_MAX_OUTBOUND_QUEUES) + 4 +#define MPI_LOGSIZE 4096 /**< default size */ + +#define MPI_IB_NUM_MASK 0x0000FFFF /**< Mask of Inbound Queue Number */ +#define MPI_OB_NUM_MASK 0xFFFF0000 /**< Mask of Outbound Queue Number */ +#define MPI_OB_SHIFT 16 /**< bits shift for outbound queue number */ + + +#define BAR0 0x10 +#define BAR1 0x14 +#define BAR2 0x18 +#define BAR3 0x1C +#define BAR4 0x20 +#define BAR5 0x24 + +/*******************************************************************************/ +/*******************************************************************************/ +/* ENUMERATIONS */ +/*******************************************************************************/ + +/*******************************************************************************/ +/*******************************************************************************/ +/** \enum mpiMsgCategory_e, + * \brief MPI message categories + */ +/*******************************************************************************/ +enum mpiMsgCategory_e +{ + MPI_CATEGORY_ETHERNET = 0, + MPI_CATEGORY_FC, + MPI_CATEGORY_SAS_SATA, + MPI_CATEGORY_SCSI +}; + +typedef enum mpiMsgCategory_e mpiMsgCategory_t; + +/*******************************************************************************/ +/*******************************************************************************/ +/* TYPES */ +/*******************************************************************************/ +/*******************************************************************************/ + + +/*******************************************************************************/ +/*******************************************************************************/ +/* DATA STRUCTURES */ +/*******************************************************************************/ +/*******************************************************************************/ + +/*******************************************************************************/ +/** \struct mpiMem_s + * \brief Structure that descibes memory regions + * + * The mpiMemoryDescriptor_t is used to describe the attributes for a memory + * region. Each element in the memory chunk has to be physically contiguous. + * Different elements in the memory chunk do not necessarily have to be + * contiguous to each other. + */ +/*******************************************************************************/ +struct mpiMem_s +{ + void* virtPtr; /**< Virtual pointer to the memory region */ + void* appHandle; /**< Handle used for the application to free memory */ + bit32 physAddrUpper; /**< Upper 32 bits of physical address */ + bit32 physAddrLower; /**< Lower 32 bits of physical address */ + bit32 totalLength; /**< Total length in bytes allocated */ + bit32 numElements; /**< Number of elements */ + bit32 elementSize; /**< Size in bytes of an element */ + bit32 alignment; /**< Alignment in bytes needed. A value of one indicates */ + /**< no specific alignment requirement */ + bit32 type; /**< Memory type */ + bit32 reserved; /**< Reserved */ +}; + +typedef struct mpiMem_s mpiMem_t; + +/*******************************************************************************/ +/** \struct mpiMemReq_s + * \brief Describes MPI memory requirements + * + * The mpiMemRequirements_t is used to specify the memory allocation requirement + * for the MPI. This is the data structure used in the mpiGetRequirements() + * and the mpiInitialize() function calls + */ +/*******************************************************************************/ +struct mpiMemReq_s +{ + bit32 count; /**< The number of element in the mpiMemory array */ + mpiMem_t region[MPI_MAX_MEM_REGIONS]; /**< Pointer to the array of structures that define memroy regions */ +}; + +typedef struct mpiMemReq_s mpiMemReq_t; + +/*******************************************************************************/ +/** \struct mpiQCQueue_s + * \brief Circular Queue descriptor + * + * This structure holds outbound circular queue attributes. + */ +/*******************************************************************************/ +struct mpiOCQueue_s +{ + bit32 qNumber; /**< this queue number */ + bit32 numElements; /**< The total number of queue elements. A value 0 disables the queue */ + bit32 elementSize; /**< The size of each queue element, in bytes */ + bit32 priority; /**< The queue priority. Possible values for this field are */ + /**< MPI_QUEUE_PRIORITY_HIGHEST and MPI_QUEUE_PRIORITY_LOWEST */ + bit32 CIPCIBar; /**< PCI Bar */ + bit32 CIPCIOffset; /**< PCI Offset */ + bit32 DIntTOffset; /**< Dynamic Interrupt Coalescing Timeout offset */ + void* piPointer; /**< pointer of PI (virtual address)*/ + mpiMem_t memoryRegion; /**< Queue's memory region descriptor */ + bit32 producerIdx; /**< Copy of the producer index */ + bit32 consumerIdx; /**< Copy of the consumer index */ + bit32 pcibar; /**< CPI Logical Bar Number */ + agsaRoot_t *agRoot; /**< Pointer of LL Layer structure */ +}; + +typedef struct mpiOCQueue_s mpiOCQueue_t; + +/*******************************************************************************/ +/** \struct mpiICQueue_s + * \brief Circular Queue descriptor + * + * This structure holds inbound circular queue attributes. + */ +/*******************************************************************************/ +struct mpiICQueue_s +{ + bit32 qNumber; /**< this queue number */ + bit32 numElements; /**< The total number of queue elements. A value 0 disables the queue */ + bit32 elementSize; /**< The size of each queue element, in bytes */ + bit32 priority; /**< The queue priority. Possible values for this field are */ + /**< MPI_QUEUE_PRIORITY_HIGHEST and MPI_QUEUE_PRIORITY_LOWEST */ + bit32 PIPCIBar; /**< PCI Bar */ + bit32 PIPCIOffset; /**< PCI Offset */ + void* ciPointer; /**< Pointer of CI (virtual Address) */ + mpiMem_t memoryRegion; /**< Queue's memory region descriptor */ + bit32 producerIdx; /**< Copy of the producer index */ + bit32 consumerIdx; /**< Copy of the consumer index */ +#ifdef SA_FW_TEST_BUNCH_STARTS + bit32 BunchStarts_QPending; // un-started bunched IOs on queue + bit32 BunchStarts_QPendingTick; // tick value when 1st IO is bunched +#endif /* SA_FW_TEST_BUNCH_STARTS */ + agsaRoot_t *agRoot; /**< Pointer of LL Layer structure */ +}; + +typedef struct mpiICQueue_s mpiICQueue_t; + +struct mpiHostLLConfigDescriptor_s +{ + bit32 regDumpPCIBAR; + bit32 iQNPPD_HPPD_GEvent; /**< inbound Queue Process depth */ + /* bit0-7 inbound normal priority process depth */ + /* bit8-15 inbound high priority process depth */ + /* bit16-23 OQ number to receive GENERAL_EVENT Notification */ + /* bit24-31 reserved */ + bit32 outboundHWEventPID0_3; /**< outbound HW event for PortId 0 to 3 */ + /* bit0-7 outbound queue number of SAS_HW event for PortId 0 */ + /* bit8-15 outbound queue number of SAS_HW event for PortId 1 */ + /* bit16-23 outbound queue number of SAS_HW event for PortId 2 */ + /* bit24-31 outbound queue number of SAS_HW event for PortId 3 */ + bit32 outboundHWEventPID4_7; /**< outbound HW event for PortId 4 to 7 */ + /* bit0-7 outbound queue number of SAS_HW event for PortId 4 */ + /* bit8-15 outbound queue number of SAS_HW event for PortId 5 */ + /* bit16-23 outbound queue number of SAS_HW event for PortId 6 */ + /* bit24-31 outbound queue number of SAS_HW event for PortId 7 */ + bit32 outboundNCQEventPID0_3; /**< outbound NCQ event for PortId 0 to 3 */ + /* bit0-7 outbound queue number of SATA_NCQ event for PortId 0 */ + /* bit8-15 outbound queue number of SATA_NCQ event for PortId 1 */ + /* bit16-23 outbound queue number of SATA_NCQ event for PortId 2 */ + /* bit24-31 outbound queue number of SATA_NCQ event for PortId 3 */ + bit32 outboundNCQEventPID4_7; /**< outbound NCQ event for PortId 4 to 7 */ + /* bit0-7 outbound queue number of SATA_NCQ event for PortId 4 */ + /* bit8-15 outbound queue number of SATA_NCQ event for PortId 5 */ + /* bit16-23 outbound queue number of SATA_NCQ event for PortId 6 */ + /* bit24-31 outbound queue number of SATA_NCQ event for PortId 7 */ + bit32 outboundTargetITNexusEventPID0_3; /**< outbound target ITNexus Event for PortId 0 to 3 */ + /* bit0-7 outbound queue number of ITNexus event for PortId 0 */ + /* bit8-15 outbound queue number of ITNexus event for PortId 1 */ + /* bit16-23 outbound queue number of ITNexus event for PortId 2 */ + /* bit24-31 outbound queue number of ITNexus event for PortId 3 */ + bit32 outboundTargetITNexusEventPID4_7; /**< outbound target ITNexus Event for PortId 4 to 7 */ + /* bit0-7 outbound queue number of ITNexus event for PortId 4 */ + /* bit8-15 outbound queue number of ITNexus event for PortId 5 */ + /* bit16-23 outbound queue number of ITNexus event for PortId 6 */ + /* bit24-31 outbound queue number of ITNexus event for PortId 7 */ + bit32 outboundTargetSSPEventPID0_3; /**< outbound target SSP event for PordId 0 to 3 */ + /* bit0-7 outbound queue number of SSP event for PortId 0 */ + /* bit8-15 outbound queue number of SSP event for PortId 1 */ + /* bit16-23 outbound queue number of SSP event for PortId 2 */ + /* bit24-31 outbound queue number of SSP event for PortId 3 */ + bit32 outboundTargetSSPEventPID4_7; /**< outbound target SSP event for PordId 4 to 7 */ + /* bit0-7 outbound queue number of SSP event for PortId 4 */ + /* bit8-15 outbound queue number of SSP event for PortId 5 */ + /* bit16-23 outbound queue number of SSP event for PortId 6 */ + /* bit24-31 outbound queue number of SSP event for PortId 7 */ + bit32 ioAbortDelay; /* was reserved */ /**< io Abort delay MPI_TABLE_CHANGE */ + bit32 custset; /**< custset */ + bit32 upperEventLogAddress; /**< Upper physical MSGU Event log address */ + bit32 lowerEventLogAddress; /**< Lower physical MSGU Event log address */ + bit32 eventLogSize; /**< Size of MSGU Event log, 0 means log disable */ + bit32 eventLogOption; /**< Option of MSGU Event log */ + /* bit3-0 log severity, 0x0 Disable Logging */ + /* 0x1 Critical Error */ + /* 0x2 Minor Error */ + /* 0x3 Warning */ + /* 0x4 Information */ + /* 0x5 Debugging */ + /* 0x6 - 0xF Reserved */ + bit32 upperIOPeventLogAddress; /**< Upper physical IOP Event log address */ + bit32 lowerIOPeventLogAddress; /**< Lower physical IOP Event log address */ + bit32 IOPeventLogSize; /**< Size of IOP Event log, 0 means log disable */ + bit32 IOPeventLogOption; /**< Option of IOP Event log */ + /* bit3-0 log severity, 0x0 Disable Logging */ + /* 0x1 Critical Error */ + /* 0x2 Minor Error */ + /* 0x3 Warning */ + /* 0x4 Information */ + /* 0x5 Debugging */ + /* 0x6 - 0xF Reserved */ + bit32 FatalErrorInterrupt; /**< Fatal Error Interrupt enable and vector */ + /* bit0 Fatal Error Interrupt Enable */ + /* bit1 PI/CI Address */ + /* bit5 enable or disable outbound coalesce */ + /* bit7-6 reserved */ + /* bit15-8 Fatal Error Interrupt Vector */ + /* bit31-16 Reserved */ + bit32 FatalErrorDumpOffset0; /**< Fatal Error Register Dump Offset for MSGU */ + bit32 FatalErrorDumpLength0; /**< Fatal Error Register Dump Length for MSGU */ + bit32 FatalErrorDumpOffset1; /**< Fatal Error Register Dump Offset for IOP */ + bit32 FatalErrorDumpLength1; /**< Fatal Error Register Dump Length for IOP */ + bit32 HDAModeFlags; /**< HDA Mode Flags */ + /* bit1-0 Bootstrap pins */ + /* bit2 Force HDA Mode bit */ + /* bit3 HDA Firmware load method */ + bit32 analogSetupTblOffset; /**< Phy Calibration Table offset */ + /* bit23-0 phy calib table offset */ + /* bit31-24 entry size */ + bit32 InterruptVecTblOffset; /**< DW23 Interrupt Vector Table */ + /* bit23-0 interrupt vector table offset */ + /* bit31-24 entry size */ + bit32 phyAttributeTblOffset; /**< DW24 SAS Phy Attribute Table Offset */ + /* bit23-0 phy attribute table offset */ + /* bit31-24 entry size */ + bit32 PortRecoveryTimerPortResetTimer; /**< DW25 Port Recovery Timer and Port Reset Timer */ + bit32 InterruptReassertionDelay; /**< DW26 Interrupt Reassertion Delay 0:23 Reserved 24:31 */ +}; + +typedef struct mpiHostLLConfigDescriptor_s mpiHostLLConfigDescriptor_t; + +/*******************************************************************************/ +/** \struct mpiInboundQueueDescriptor_s + * \brief MPI inbound queue attributes + * + * The mpiInboundQueueDescriptor_t structure is used to describe an inbound queue + * attributes + */ +/*******************************************************************************/ +struct mpiInboundQueueDescriptor_s +{ + bit32 numElements; /**< The total number of queue elements. A value 0 disables the queue */ + bit32 elementSize; /**< The size of each queue element, in bytes */ + bit32 priority; /**< The queue priority. Possible values for this field are */ + /**< MPI_QUEUE_PRIORITY_HIGHEST and MPI_QUEUE_PRIORITY_LOWEST */ + bit32 PIPCIBar; /**< PI PCIe Bar */ + bit32 PIOffset; /**< PI PCI Bar Offset */ + void* ciPointer; /**< Pointer of CI (virtual Address) */ +}; + +typedef struct mpiInboundQueueDescriptor_s mpiInboundQueueDescriptor_t; + +/*******************************************************************************/ +/** \struct mpiOutboundQueueDescriptor_s + * \brief MPI outbound queue attributes + * + * The mpiOutboundQueueDescriptor_t structure is used to describe an outbound queue + * attributes + */ +/*******************************************************************************/ +struct mpiOutboundQueueDescriptor_s +{ + bit32 numElements; /**< The total number of queue elements. A value 0 disables the queue */ + bit32 elementSize; /**< The size of each queue element, in bytes */ + bit32 interruptDelay; /**< Delay in microseconds before the interrupt is asserted */ + /**< if the interrupt threshold has not been reached */ + bit32 interruptThreshold; /**< Number of interrupt events before the interrupt is asserted */ + /**< If set to 0, interrupts for this queue are disablec */ + bit32 interruptVector; /**< Interrupt vector assigned to this queue */ + bit32 CIPCIBar; /**< offset 0x14:PCI BAR for CI Offset */ + bit32 CIOffset; /**< offset 0x18:Offset address for outbound queue CI */ + bit32 DIntTOffset; /**< Dynamic Interrupt Coalescing Timeout offset */ + bit32 interruptEnable; /**< Interrupt enable flag */ + void* piPointer; /**< pointer of PI (virtual address)*/ +}; + +typedef struct mpiOutboundQueueDescriptor_s mpiOutboundQueueDescriptor_t; + +/*******************************************************************************/ +/** \struct mpiPhyCalibration_s + * \brief MPI Phy Calibration Table + * + * The mpiPhyCalibration_s structure is used to set Phy Calibration + * attributes + */ +/*******************************************************************************/ +struct mpiPhyCalibration_s +{ + bit32 spaReg0; /* transmitter per port configuration 1 SAS_SATA G1 */ + bit32 spaReg1; /* transmitter per port configuration 2 SAS_SATA G1*/ + bit32 spaReg2; /* transmitter per port configuration 3 SAS_SATA G1*/ + bit32 spaReg3; /* transmitter configuration 1 */ + bit32 spaReg4; /* reveiver per port configuration 1 SAS_SATA G1G2 */ + bit32 spaReg5; /* reveiver per port configuration 2 SAS_SATA G3 */ + bit32 spaReg6; /* reveiver per configuration 1 */ + bit32 spaReg7; /* reveiver per configuration 2 */ + bit32 reserved[2]; /* reserved */ +}; + +typedef struct mpiPhyCalibration_s mpiPhyCalibration_t; + +#define ANALOG_SETUP_ENTRY_NO 10 +#define ANALOG_SETUP_ENTRY_SIZE 10 + + +/*******************************************************************************/ +/** \struct mpiConfig_s + * \brief MPI layer configuration parameters + * + * The mpiConfig_s structure is used as a parameter passed in + * mpiGetRequirements() and mpiInitialize() to describe the MPI software + * configuration + */ +/*******************************************************************************/ +struct mpiVConfig_s +{ + mpiHostLLConfigDescriptor_t mainConfig; /**< main part of configuration table */ + mpiInboundQueueDescriptor_t inboundQueues[MPI_MAX_INBOUND_QUEUES]; /**< mpiQueueDescriptor structures that provide initialization */ + /**< attributes for the inbound queues. The maximum number of */ + /**< inbound queues is MPI_MAX_INBOUND_QUEUES */ + mpiOutboundQueueDescriptor_t outboundQueues[MPI_MAX_OUTBOUND_QUEUES]; /**< mpiQueueDescriptor structures that provide initialization */ + /**< attributes for the outbound queues. The maximum number of */ + /**< inbound queues is MPI_MAX_OUTBOUND_QUEUES */ + agsaPhyAnalogSetupTable_t phyAnalogConfig; + mpiInterruptVT_t interruptVTable; + sasPhyAttribute_t phyAttributeTable; + bit16 numInboundQueues; + bit16 numOutboundQueues; + bit16 maxNumInboundQueues; + bit16 maxNumOutboundQueues; + bit32 queueOption; +}; + +/*******************************************************************************/ +/** \struct mpiConfig_s + * \brief MPI layer configuration parameters + * + * The mpiConfig_s structure is used as a parameter passed in + * mpiGetRequirements() and mpiInitialize() to describe the MPI software + * configuration + */ +/*******************************************************************************/ +struct mpiConfig_s +{ + mpiHostLLConfigDescriptor_t mainConfig; /**< main part of configuration table */ + mpiInboundQueueDescriptor_t inboundQueues[MPI_MAX_INBOUND_QUEUES]; /**< mpiQueueDescriptor structures that provide initialization */ + /**< attributes for the inbound queues. The maximum number of */ + /**< inbound queues is MPI_MAX_INBOUND_QUEUES */ + mpiOutboundQueueDescriptor_t outboundQueues[MPI_MAX_OUTBOUND_QUEUES]; /**< mpiQueueDescriptor structures that provide initialization */ + /**< attributes for the outbound queues. The maximum number of */ + /**< inbound queues is MPI_MAX_OUTBOUND_QUEUES */ + agsaPhyAnalogSetupTable_t phyAnalogConfig; + bit16 numInboundQueues; + bit16 numOutboundQueues; + bit16 maxNumInboundQueues; + bit16 maxNumOutboundQueues; + bit32 queueOption; +}; + +typedef struct mpiConfig_s mpiConfig_t; + +#define TX_PORT_CFG1_OFFSET 0x00 +#define TX_PORT_CFG2_OFFSET 0x04 +#define TX_PORT_CFG3_OFFSET 0x08 +#define TX_CFG_OFFSET 0x0c +#define RV_PORT_CFG1_OFFSET 0x10 +#define RV_PORT_CFG2_OFFSET 0x14 +#define RV_CFG1_OFFSET 0x18 +#define RV_CFG2_OFFSET 0x1c + +/*******************************************************************************/ +/*******************************************************************************/ +/* FUNCTIONS */ +/*******************************************************************************/ +/*******************************************************************************/ +/*******************************************************************************/ +void mpiRequirementsGet(mpiConfig_t *config, mpiMemReq_t *memoryRequirement); +FORCEINLINE bit32 mpiMsgFreeGet(mpiICQueue_t *circularQ, bit16 messageSize, void** messagePtr); +FORCEINLINE bit32 mpiMsgProduce(mpiICQueue_t *circularQ, void* messagePtr, + mpiMsgCategory_t category, bit16 opCode, + bit8 responseQueue, bit8 hiPriority); +#ifdef LOOPBACK_MPI +GLOBAL bit32 mpiMsgProduceOQ(mpiOCQueue_t *circularQ, void *messagePtr, + mpiMsgCategory_t category, bit16 opCode, + bit8 responseQueue, bit8 hiPriority); +GLOBAL bit32 mpiMsgFreeGetOQ(mpiOCQueue_t *circularQ, bit16 messageSize, + void** messagePtr); +#endif + +#ifdef FAST_IO_TEST +bit32 mpiMsgPrepare(mpiICQueue_t *circularQ, void* messagePtr, + mpiMsgCategory_t category, bit16 opCode, + bit8 responseQueue, bit8 hiPriority); + +bit32 mpiMsgProduceSend(mpiICQueue_t *circularQ, void* messagePtr, + mpiMsgCategory_t category, bit16 opCode, + bit8 responseQueue, bit8 hiPriority, int sendFl); +GLOBAL void mpiIBQMsgSend(mpiICQueue_t *circularQ); +#define INQ(queueNum) (bit8)(queueNum & MPI_IB_NUM_MASK) +#define OUQ(queueNum) (bit8)((queueNum & MPI_OB_NUM_MASK) >> MPI_OB_SHIFT) +#endif + +FORCEINLINE bit32 mpiMsgConsume(mpiOCQueue_t *circularQ, void** messagePtr1, mpiMsgCategory_t *pCategory, bit16* pOpCode, bit8 *pBC); +FORCEINLINE bit32 mpiMsgFreeSet(mpiOCQueue_t *circularQ, void* messagePtr1, bit8 bc); + +#endif /* __MPI_H__ */ + diff --git a/sys/dev/pms/RefTisa/sallsdk/spc/mpidebug.c b/sys/dev/pms/RefTisa/sallsdk/spc/mpidebug.c new file mode 100644 index 000000000000..4f83fe538b1d --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/spc/mpidebug.c @@ -0,0 +1,909 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ + +/*******************************************************************************/ +/*! \file mpidebug.c + * \brief The file is a MPI Libraries to implement the MPI debug and trace functions + * + * The file implements the MPI functions. + * + */ +/*******************************************************************************/ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#ifdef MPI_DEBUG_TRACE_ENABLE /* enable with CCBUILD_MPI_TRACE*/ + +/*******************************************************************************/ + +#ifdef OSLAYER_USE_HI_RES_TIMER +unsigned __int64 +GetHiResTimeStamp(void); +#endif /* OSLAYER_USE_HI_RES_TIMER */ +/*******************************************************************************/ +/*******************************************************************************/ +/* FUNCTIONS */ +/*******************************************************************************/ +mpiDebugObTrace_t obTraceData; +mpiDebugIbTrace_t ibTraceData; + +void mpiTraceInit(void) +{ + + SA_DBG1(("mpiTraceInit:obTraceData @ %p\n",&obTraceData )); + SA_DBG1(("mpiTraceInit:ibTraceData @ %p\n",&ibTraceData )); + SA_DBG1(("mpiTraceInit: num enties %d Ib Iomb size %d Ob Iomb size %d\n", + MPI_DEBUG_TRACE_BUFFER_MAX, + MPI_DEBUG_TRACE_IB_IOMB_SIZE, + MPI_DEBUG_TRACE_OB_IOMB_SIZE )); + + si_memset(&obTraceData, 0, sizeof(obTraceData)); + si_memset(&ibTraceData, 0, sizeof(ibTraceData)); +} + +void mpiTraceAdd( bit32 q,bit32 pici,bit32 ib, void *iomb, bit32 numBytes) +{ + bit32 curIdx; + mpiDebugIbTraceEntry_t *curIbTrace; + mpiDebugObTraceEntry_t *curObTrace; + + mpiDebugIbTrace_t * ibTrace = &ibTraceData; + mpiDebugObTrace_t * obTrace = &obTraceData; + + if (ib) + { + if(ibTrace->Idx >= MPI_DEBUG_TRACE_BUFFER_MAX) + { + ibTrace->Idx = 0; + } + curIdx = ibTrace->Idx; + + curIbTrace = &ibTrace->Data[curIdx]; + curIbTrace->pEntry = iomb; + curIbTrace->QNum = q; + curIbTrace->pici = pici; +#ifdef OSLAYER_USE_HI_RES_TIMER +#ifdef SA_64BIT_TIMESTAMP + curIbTrace->Time = ossaTimeStamp64(agNULL); +#else /* SA_64BIT_TIMESTAMP */ + curIbTrace->Time = ossaTimeStamp(agNULL); +#endif /* SA_64BIT_TIMESTAMP */ +#else /* OSLAYER_USE_HI_RES_TIMER */ + curIbTrace->Time = 0; +#endif + si_memcpy(curIbTrace->Iomb, iomb, MIN(numBytes, MPI_DEBUG_TRACE_IB_IOMB_SIZE)); + ibTrace->Idx++; + } + else + { + if(obTrace->Idx >= MPI_DEBUG_TRACE_BUFFER_MAX ) + { + obTrace->Idx = 0; + } + curIdx = obTrace->Idx; + curObTrace = &obTrace->Data[curIdx]; + curObTrace->pEntry = iomb; + curObTrace->QNum = q; + curObTrace->pici = pici; +#ifdef OSLAYER_USE_HI_RES_TIMER +#ifdef SA_64BIT_TIMESTAMP + curObTrace->Time = ossaTimeStamp64(agNULL); +#else /* SA_64BIT_TIMESTAMP */ + curObTrace->Time = ossaTimeStamp(agNULL); +#endif /* SA_64BIT_TIMESTAMP */ +#else /* OSLAYER_USE_HI_RES_TIMER */ + curObTrace->Time = 0; +#endif + si_memcpy(curObTrace->Iomb, iomb, MIN(numBytes, MPI_DEBUG_TRACE_OB_IOMB_SIZE)); + obTrace->Idx++; + } + + + return; +} + +#endif /* MPI_DEBUG_TRACE_ENABLE */ + + + +#ifdef SA_ENABLE_TRACE_FUNCTIONS + +/** + * fiEnableTracing + * + * This fucntion is called to initialize tracing of FC layer. + * + */ +void siEnableTracing (agsaRoot_t *agRoot) +{ + + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaSwConfig_t *swC = &saRoot->swConfig; + bit32 count; + + OS_ASSERT(saRoot != NULL, ""); + + if( saRoot->TraceBlockReInit != 0) + { + return; + } + + + /* Initialize tracing first */ + + for (count = 0; count < 10; count++) + { + saRoot->traceBuffLookup[count] = (bit8)('0' + count); + } + for (count = 0; count < 6; count++) + { + saRoot->traceBuffLookup[(bitptr)count + 10] = (bit8)('a' + count); + } + + + saRoot->TraceDestination = swC->TraceDestination; + saRoot->TraceMask = swC->TraceMask; + saRoot->CurrentTraceIndexWrapCount = 0; + saRoot->CurrentTraceIndex = 0; + saRoot->TraceBlockReInit = 1; + + + SA_DBG1(("siEnableTracing: \n" )); + + SA_DBG1 ((" length = %08x\n", saRoot->TraceBufferLength )); + SA_DBG1 ((" virt = %p\n", saRoot->TraceBuffer )); + SA_DBG1 ((" traceMask = %08x @ %p\n", saRoot->TraceMask, &saRoot->TraceMask)); + SA_DBG1 ((" last trace entry @ %p\n", &saRoot->CurrentTraceIndex)); + SA_DBG1 ((" TraceWrapAround = %x\n", saRoot->TraceMask & hpDBG_TraceBufferWrapAround ? 1 : 0)); + SA_DBG1 ((" da %p l %x\n",saRoot->TraceBuffer ,saRoot->TraceBufferLength)); + +#ifdef SA_PRINTOUT_IN_WINDBG +#ifndef DBG + DbgPrint("siTraceEnable: \n" ); + + DbgPrint(" length = %08x\n", saRoot->TraceBufferLength ); + DbgPrint(" virt = %p\n", saRoot->TraceBuffer ); + DbgPrint(" last trace entry @ %p\n", &saRoot->CurrentTraceIndex); + DbgPrint(" traceMask = %08x @ %p\n", saRoot->TraceMask, &saRoot->TraceMask); + DbgPrint(" da %p l %x\n",saRoot->TraceBuffer ,saRoot->TraceBufferLength); +#endif /* DBG */ +#endif /* SA_PRINTOUT_IN_WINDBG */ + /* + ** Init trace buffer with all spaces + */ + for (count = 0; count < saRoot->TraceBufferLength; count++) + { + saRoot->TraceBuffer[count] = (bit8)' '; + } + +} + + + +/** + * IF_DO_TRACE + * + * PURPOSE: convenience macro for the "to output or not to output" logic + * + * PARAMETERS: + * + * CALLS: + * + * SIDE EFFECTS & CAVEATS: + * + * ALGORITHM: + * + * + * + * MODIFICATION HISTORY *********************** + * + * ENGINEER NAME DATE DESCRIPTION + * ------------- -------- ----------- + */ + +#define IF_DO_TRACE \ + if ( (saRoot != NULL) && \ + (saRoot->TraceDestination & siTraceDestMask) && \ + (mask & saRoot->TraceMask) ) \ + + +/* #define TRACE_ENTER_LOCK ossaSingleThreadedEnter(agRoot, LL_TRACE_LOCK); */ +/* #define TRACE_LEAVE_LOCK ossaSingleThreadedLeave(agRoot, LL_TRACE_LOCK); */ +#define TRACE_ENTER_LOCK +#define TRACE_LEAVE_LOCK +/** + * BUFFER_WRAP_CHECK + * + * PURPOSE: Checks if the tracing buffer tracing index is too high. If it is, + * the buffer index gets reset to 0 or tracing stops.. + */ +#define BUFFER_WRAP_CHECK \ + if( (saRoot->CurrentTraceIndex + TMP_TRACE_BUFF_SIZE) \ + >= saRoot->TraceBufferLength ) \ + { \ + /* Trace wrap-Around is enabled. */ \ + if( saRoot->TraceMask & hpDBG_TraceBufferWrapAround ) \ + { \ + /* Fill the end of the buffer with spaces */ \ + for( i = saRoot->CurrentTraceIndex; \ + i < saRoot->TraceBufferLength; i++ ) \ + { \ + saRoot->TraceBuffer[i] = (bit8)' '; \ + } \ + /* Wrap the current trace index back to 0.. */ \ + saRoot->CurrentTraceIndex = 0; \ + saRoot->CurrentTraceIndexWrapCount++; \ + } \ + else \ + { \ + /* Don't do anything -- trace buffer is filled up */ \ + return; \ + } \ + } + +/** + * LOCAL_OS_LOG_DEBUG_STRING + * + * PURPOSE: protects against a change in the api for this function + * + * PARAMETERS: + * + * CALLS: + * + * SIDE EFFECTS & CAVEATS: + * + * ALGORITHM: + * + * + * + * MODIFICATION HISTORY *********************** + * + * ENGINEER NAME DATE DESCRIPTION + * ------------- -------- ----------- + * Laurent Chavey 03/09/00 - changed cast of 3rd parameter to (char *) + */ + #define LOCAL_OS_LOG_DEBUG_STRING(H,S) \ + osLogDebugString(H,hpDBG_ALWAYS,(char *)(S)) + +/****************************************************************************** +******************************************************************************* +** +** copyHex +** +** PURPOSE: Copies a hex version of a bit32 into a bit8 buffer +** +******************************************************************************* +******************************************************************************/ +#define copyHex(bit32Val, bitSize) \ +{ \ + bit32 nibbleLen = bitSize / 4; \ + bit32 scratch = 0; \ + for( i = 0; i < nibbleLen; i++ ) \ + { \ + bPtr[pos++] = \ + saRoot->traceBuffLookup[0xf & (bit32Val >> ((bitSize - 4) - (i << 2)))]; \ + i++; \ + bPtr[pos++] = \ + saRoot->traceBuffLookup[0xf & (bit32Val >> ((bitSize - 4) - (i << 2)))]; \ + /* Skip leading 0-s to save memory buffer space */ \ + if( !scratch \ + && (bPtr[pos-2] == '0') \ + && (bPtr[pos-1] == '0') ) \ + { \ + pos -= 2; \ + continue; \ + } \ + else \ + { \ + scratch = 1; \ + } \ + } \ + if( scratch == 0 ) \ + { \ + /* The value is 0 and nothing got put in the buffer. Do */ \ + /* print at least two zeros. */ \ + bPtr[pos++] = '0'; \ + bPtr[pos++] = '0'; \ + } \ +} + + +/** + * TRACE_OTHER_DEST + * + * PURPOSE: Check if any other destinations are enabled. If yes, use them + * for debug log. + */ +#define TRACE_OTHER_DEST \ + { \ + bit32 bitptrscratch; \ + if( saRoot->TraceDestination & smTraceDestDebugger ) \ + { \ + bPtr[pos++] = (bit8)'\n'; \ + bPtr[pos++] = (bit8)0; \ + LOCAL_OS_LOG_DEBUG_STRING(hpRoot, (char *)bPtr); \ + } \ + if( saRoot->TraceDestination & smTraceDestRegister ) \ + { \ + while( (pos & 0x3) != 0x3 ) \ + { \ + bPtr[pos++] = (bit8)' '; \ + } \ + bPtr[pos] = ' '; \ + for( i = 0; i < pos; i = i + 4 ) \ + { \ + bitptrscratch = bPtr[i+0]; \ + bitptrscratch <<= 8; \ + bitptrscratch |= bPtr[i+1]; \ + bitptrscratch <<= 8; \ + bitptrscratch |= bPtr[i+2]; \ + bitptrscratch <<= 8; \ + bitptrscratch |= bPtr[i+3]; \ + osChipRegWrite(hpRoot, \ + FC_rFMReceivedALPA, (bit32)bitptrscratch ); \ + } \ + } \ + } + + + +/** + * siGetCurrentTraceIndex() + * + * PURPOSE: Returns the current tracing index ( if tracing buffer is + * used ). + * + * PARAMETERS: + * + * CALLS: + * + * SIDE EFFECTS & CAVEATS: + * + * ALGORITHM: + * + * + * MODIFICATION HISTORY *********************** + * + * ENGINEER NAME DATE DESCRIPTION + * ------------- -------- ----------- + * Tom Nalepa 02/27/03 + * + * @param hpRoot + * + * @return + */ +GLOBAL bit32 siGetCurrentTraceIndex(agsaRoot_t *agRoot) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + return(saRoot->CurrentTraceIndex); +} + + + + +/** + * siResetTraceBuffer + * + * PURPOSE: Sets saRoot->CurrentTraceIndex to 0. + * + * @param hpRoot + * + * @return + */ +GLOBAL void siResetTraceBuffer(agsaRoot_t *agRoot) +{ + bit32 count; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + saRoot->CurrentTraceIndex = 0; + + for ( count = 0; count < saRoot->TraceBufferLength; count++ ) + { + saRoot->TraceBuffer[count] = (bit8)' '; + } +} + + +/** + * siTraceFuncEnter + * + * PURPOSE: Format a function entry trace and post it to the appropriate + * destination. + * + * PARAMETERS: + * + * CALLS: + * + * SIDE EFFECTS & CAVEATS: + * + * ALGORITHM: + * + * siTraceFuncEnter : _[Xxxxx_ + * fileid---^ ^------funcid + * + * + * MODIFICATION HISTORY *********************** + * + * ENGINEER NAME DATE DESCRIPTION + * ------------- -------- ----------- + * + * @param hpRoot + * @param mask + * @param fileid + * @param funcid + * + * @return + */ + +#define TMP_TRACE_BUFF_SIZE 32 + + +GLOBAL void siTraceFuncEnter( agsaRoot_t *agRoot, + bit32 mask, + bit32 fileid, + char * funcid) +{ +agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + bitptr i; + bit8 tmpB[TMP_TRACE_BUFF_SIZE]; + bit8 *bPtr; + bit8 pos = 0; + + IF_DO_TRACE + { + TRACE_ENTER_LOCK + if ( saRoot->TraceDestination & smTraceDestBuffer ) + { + BUFFER_WRAP_CHECK + bPtr = &saRoot->TraceBuffer[saRoot->CurrentTraceIndex]; + } + else + { + bPtr = tmpB; + } + bPtr[pos++] = (bit8)'['; + +#ifndef FC_DO_NOT_INCLUDE_FILE_NAME_TAGS_IN_ENTER_EXIT_TRACE + bPtr[pos++] = (bit8)fileid; +#endif + + for ( i=0; i<4; i++ ) + { + if ( funcid[i] == 0 ) + { + break; + } + bPtr[pos++] = (bit8)funcid[i]; + } + bPtr[pos++] = ' '; + if ( saRoot->traceLineFeedCnt > FC_TRACE_LINE_SIZE ) + { + bPtr[pos++] = '\r'; + bPtr[pos++] = '\n'; + saRoot->traceLineFeedCnt = 0; + } + saRoot->CurrentTraceIndex += pos; +// TRACE_OTHER_DEST + TRACE_LEAVE_LOCK + + } + return; +} + + +/** + * siTraceFuncExit + * + * PURPOSE: Format a function exit trace and post it to the appropriate + * destination. + * + * PARAMETERS: + * + * CALLS: + * + * SIDE EFFECTS & CAVEATS: + * + * ALGORITHM: + * + * siTraceFuncExit _Xxxxx]_ + * fileid---^ ^------funcid + * + * + * MODIFICATION HISTORY *********************** + * + * ENGINEER NAME DATE DESCRIPTION + * ------------- -------- ----------- + * + * @param hpRoot + * @param mask + * @param fileid + * @param funcid + * @param exitId + * + * @return + */ +GLOBAL void siTraceFuncExit( agsaRoot_t *agRoot, bit32 mask, char fileid, char * funcid, char exitId ) +{ + bitptr i; + bit8 tmpB[TMP_TRACE_BUFF_SIZE]; + bit8 *bPtr; + bit8 pos = 0; + + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + + IF_DO_TRACE + { + TRACE_ENTER_LOCK + if ( saRoot->TraceDestination & smTraceDestBuffer ) + { + BUFFER_WRAP_CHECK + bPtr = &saRoot->TraceBuffer[saRoot->CurrentTraceIndex]; + } + else + { + bPtr = tmpB; + } + +#ifndef FC_DO_NOT_INCLUDE_FILE_NAME_TAGS_IN_ENTER_EXIT_TRACE + bPtr[pos++] = (bit8)fileid; +#endif + + for ( i=0; i<4; i++ ) + { + if ( funcid[i] == 0 ) + { + break; + } + bPtr[pos++] = (bit8)funcid[i]; + } + bPtr[pos++] = (bit8)exitId; + bPtr[pos++] = (bit8)']'; + bPtr[pos++] = (bit8)' '; + if ( saRoot->traceLineFeedCnt > FC_TRACE_LINE_SIZE ) + { + bPtr[pos++] = '\r'; + bPtr[pos++] = '\n'; + saRoot->traceLineFeedCnt = 0; + } + saRoot->CurrentTraceIndex += pos; +// TRACE_OTHER_DEST + TRACE_LEAVE_LOCK + } + return; +} + +/** + * siTraceListRemove + * + * PURPOSE: Adds a trace tag for an exchange that is removed from a list + * + * PARAMETERS: + * + * CALLS: + * + * SIDE EFFECTS & CAVEATS: + * + * ALGORITHM: + * + * + * MODIFICATION HISTORY *********************** + * + * ENGINEER NAME DATE DESCRIPTION + * ------------- -------- ----------- + * Tom Nalepa 12/16/02 Initial Developmet + * + * @param hpRoot + * @param mask + * @param listId + * @param exchangeId + * + * @return + */ +GLOBAL void siTraceListRemove(agsaRoot_t *agRoot, + bit32 mask, + char listId, + bitptr exchangeId) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + bitptr i; + bit8 tmpB[TMP_TRACE_BUFF_SIZE]; + bit8 *bPtr; + bit8 pos = 0; + + IF_DO_TRACE + { + TRACE_ENTER_LOCK + if ( saRoot->TraceDestination & smTraceDestBuffer ) + { + BUFFER_WRAP_CHECK + bPtr = &saRoot->TraceBuffer[saRoot->CurrentTraceIndex]; + } + else + { + bPtr = tmpB; + } + bPtr[pos++] = (bit8)'<'; + bPtr[pos++] = (bit8)listId; + copyHex(exchangeId, 32); + bPtr[pos++] = (bit8)' '; + if ( saRoot->traceLineFeedCnt > FC_TRACE_LINE_SIZE ) + { + bPtr[pos++] = '\r'; + bPtr[pos++] = '\n'; + saRoot->traceLineFeedCnt = 0; + } + saRoot->CurrentTraceIndex += pos; +// TRACE_OTHER_DEST + TRACE_LEAVE_LOCK + } + return; +} + +/** + * siTraceListAdd + * + * PURPOSE: Adds a trace tag for an exchange that is added to a list + * + * PARAMETERS: + * + * CALLS: + * + * SIDE EFFECTS & CAVEATS: + * + * ALGORITHM: + * + * + * MODIFICATION HISTORY *********************** + * + * ENGINEER NAME DATE DESCRIPTION + * ------------- -------- ----------- + * Tom Nalepa 12/16/02 Initial Developmet + * + * @param hpRoot + * @param mask + * @param listId + * @param exchangeId + * + * @return + */ +GLOBAL void siTraceListAdd(agsaRoot_t *agRoot, + bit32 mask, + char listId, + bitptr exchangeId) +{ + + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + + bitptr i; + bit8 tmpB[TMP_TRACE_BUFF_SIZE]; + bit8 *bPtr; + bit8 pos = 0; + + IF_DO_TRACE + { + if ( saRoot->TraceDestination & smTraceDestBuffer ) + { + BUFFER_WRAP_CHECK + bPtr = &saRoot->TraceBuffer[saRoot->CurrentTraceIndex]; + } + else + { + bPtr = tmpB; + } + bPtr[pos++] = (bit8)'>'; + bPtr[pos++] = (bit8)listId; + copyHex(exchangeId, 32); + bPtr[pos++] = (bit8)' '; + if ( saRoot->traceLineFeedCnt > FC_TRACE_LINE_SIZE ) + { + bPtr[pos++] = '\r'; + bPtr[pos++] = '\n'; + saRoot->traceLineFeedCnt = 0; + } + saRoot->CurrentTraceIndex += pos; +// TRACE_OTHER_DEST + } + return; +} + +/** + * siTrace64 + * + * PURPOSE: Format a function parameter trace and post it to the appropriate + * destination. + * + * PARAMETERS: + * + * CALLS: + * + * SIDE EFFECTS & CAVEATS: + * + * ALGORITHM: + * + * siTrace : index is 0 for return value, 1 for first parm after "(" + * produces: _nn" XXXXXXXXXX + * index-----^ value--^ + * + * + * MODIFICATION HISTORY *********************** + * + * ENGINEER NAME DATE DESCRIPTION + * ------------- -------- ----------- + * + * @param hpRoot + * @param mask + * @param uId + * @param value + * + * @return + */ +GLOBAL void siTrace64(agsaRoot_t *agRoot, + bit32 mask, + char * uId, + bit64 value, + bit32 dataSizeInBits) +{ + + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + bitptr i; + bit8 tmpB[TMP_TRACE_BUFF_SIZE]; + bit8 *bPtr; + bit8 pos = 0; + + IF_DO_TRACE + { + if ( saRoot->TraceDestination & smTraceDestBuffer ) + { + BUFFER_WRAP_CHECK + bPtr = &saRoot->TraceBuffer[saRoot->CurrentTraceIndex]; + } + else + { + bPtr = tmpB; + } + bPtr[pos++] = (bit8)'"'; + bPtr[pos++] = (bit8)uId[0]; + bPtr[pos++] = (bit8)uId[1]; + bPtr[pos++] = (bit8)':'; + copyHex(value, dataSizeInBits); + bPtr[pos++] = (bit8)' '; + if ( saRoot->traceLineFeedCnt > FC_TRACE_LINE_SIZE ) + { + bPtr[pos++] = '\r'; + bPtr[pos++] = '\n'; + saRoot->traceLineFeedCnt = 0; + } + saRoot->CurrentTraceIndex += pos; +// TRACE_OTHER_DEST + } + return; +} + + + +/** + * siTrace + * + * PURPOSE: Format a function parameter trace and post it to the appropriate + * destination. + * + * PARAMETERS: + * + * CALLS: + * + * SIDE EFFECTS & CAVEATS: + * + * ALGORITHM: + * + * fiTrace : index is 0 for return value, 1 for first parm after "(" + * produces: _nn" XXXXXXXXXX + * index-----^ value--^ + * + * + * MODIFICATION HISTORY *********************** + * + * ENGINEER NAME DATE DESCRIPTION + * ------------- -------- ----------- + * + * @param hpRoot + * @param mask + * @param uId + * @param value + * + * @return + */ +GLOBAL void siTrace( agsaRoot_t *agRoot, + bit32 mask, + char * uId, + bit32 value, + bit32 dataSizeInBits) +{ + + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + + bitptr i; + bit8 tmpB[TMP_TRACE_BUFF_SIZE]; + bit8 *bPtr; + bit8 pos = 0; + + IF_DO_TRACE + { + if ( saRoot->TraceDestination & smTraceDestBuffer ) + { + BUFFER_WRAP_CHECK + bPtr = &saRoot->TraceBuffer[saRoot->CurrentTraceIndex]; + } + else + { + bPtr = tmpB; + } + bPtr[pos++] = (bit8)'"'; + bPtr[pos++] = (bit8)uId[0]; + bPtr[pos++] = (bit8)uId[1]; + bPtr[pos++] = (bit8)':'; + copyHex(value, dataSizeInBits); + bPtr[pos++] = (bit8)' '; + if ( saRoot->traceLineFeedCnt > FC_TRACE_LINE_SIZE ) + { + bPtr[pos++] = '\r'; + bPtr[pos++] = '\n'; + saRoot->traceLineFeedCnt = 0; + } + saRoot->CurrentTraceIndex += pos; +// TRACE_OTHER_DEST + } + return; +} + + +/*Set Wrap 0 for Wrapping non zero stops when full */ + + +GLOBAL void siTraceGetInfo(agsaRoot_t *agRoot, hpTraceBufferParms_t * pBParms) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)agRoot->sdkData; + + pBParms->TraceCompiled = TRUE; + + pBParms->TraceWrap = saRoot->TraceMask & 0x80000000; + pBParms->CurrentTraceIndexWrapCount = saRoot->CurrentTraceIndexWrapCount; + pBParms->BufferSize = saRoot->TraceBufferLength; + pBParms->CurrentIndex = saRoot->CurrentTraceIndex; + pBParms->pTrace = saRoot->TraceBuffer; + pBParms->pTraceIndexWrapCount = &saRoot->CurrentTraceIndexWrapCount; + pBParms->pTraceMask = &saRoot->TraceMask; + pBParms->pCurrentTraceIndex = &saRoot->CurrentTraceIndex; +} +/**/ + +GLOBAL void siTraceSetMask(agsaRoot_t *agRoot, bit32 TraceMask ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)agRoot->sdkData; + saRoot->TraceMask = TraceMask; +} + + + +#endif + + diff --git a/sys/dev/pms/RefTisa/sallsdk/spc/mpidebug.h b/sys/dev/pms/RefTisa/sallsdk/spc/mpidebug.h new file mode 100644 index 000000000000..e62a80c5771a --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/spc/mpidebug.h @@ -0,0 +1,283 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ + +/*******************************************************************************/ +/*! \file mpidebug.h + * \brief The file defines the debug constants and structures + * + */ +/*******************************************************************************/ + +#ifndef __MPIDEBUG_H__ +#define __MPIDEBUG_H__ + +/*******************************************************************************/ +#define MPI_DEBUG_TRACE_BUFFER_MAX 1024 +#define MPI_DEBUG_TRACE_OB_IOMB_SIZE 128 /* 64 */ +#define MPI_DEBUG_TRACE_IB_IOMB_SIZE 128 /* 64 */ +#define MPI_DEBUG_TRACE_IBQ 1 +#define MPI_DEBUG_TRACE_OBQ 0 +#define MPI_DEBUG_TRACE_QNUM_ERROR 100 /* Added to Qnumber to indicate error */ + +typedef struct mpiObDebugTraceEntry_s +{ + bit64 Time; + bit32 QNum; + bit32 pici; + void * pEntry; + bit32 Iomb[MPI_DEBUG_TRACE_OB_IOMB_SIZE/4]; +} mpiDebugObTraceEntry_t; + +typedef struct mpiIbDebugTraceEntry_s +{ + bit64 Time; + bit32 QNum; + bit32 pici; + void * pEntry; + bit32 Iomb[MPI_DEBUG_TRACE_IB_IOMB_SIZE/4]; +} mpiDebugIbTraceEntry_t; + +typedef struct mpiIbDebugTrace_s +{ + bit32 Idx; + bit32 Pad; + mpiDebugIbTraceEntry_t Data[MPI_DEBUG_TRACE_BUFFER_MAX]; +} mpiDebugIbTrace_t; + +typedef struct mpiObDebugTrace_s +{ + bit32 Idx; + bit32 Pad; + mpiDebugObTraceEntry_t Data[MPI_DEBUG_TRACE_BUFFER_MAX]; +} mpiDebugObTrace_t; + +void mpiTraceInit(void); +void mpiTraceAdd(bit32 q,bit32 pici,bit32 ib, void *iomb, bit32 numBytes); + +#endif /* __MPIDEBUG_H__ */ + + + + +/******************************************************************** +** File that contains debug-specific APIs ( driver tracing etc ) +*********************************************************************/ + +#ifndef __SPCDEBUG_H__ +#define __SPCDEBUG_H__ + + +/* +** console and trace levels +*/ + +#define hpDBG_ALWAYS 0x0000ffff +#define hpDBG_IOMB 0x00000040 +#define hpDBG_REGISTERS 0x00000020 +#define hpDBG_TICK_INT 0x00000010 +#define hpDBG_SCREAM 0x00000008 +#define hpDBG_VERY_LOUD 0x00000004 +#define hpDBG_LOUD 0x00000002 +#define hpDBG_ERROR 0x00000001 +#define hpDBG_NEVER 0x00000000 + +#define smTraceDestBuffer 0x00000001 +#define smTraceDestRegister 0x00000002 +#define smTraceDestDebugger 0x00000004 + + +#define siTraceDestMask (smTraceDestBuffer | \ + smTraceDestRegister | \ + smTraceDestDebugger) + +/* Trace buffer will continuously */ +/* trace and wrap-around on itself */ +/* when it reaches the end */ +#define hpDBG_TraceBufferWrapAround 0x80000000 +/* This features enables logging of trace time */ +/* stamps. Only certain key routines use this */ +/* feature because it tends to clog up the trace */ +/* buffer. */ +#define hpDBG_TraceBufferUseTimeStamp 0x40000000 +/* This features enables logging of trace sequential */ +/* stamps. Only certain key routines use this */ +/* feature because it tends to clog up the trace */ +/* buffer. */ +#define hpDBG_TraceBufferUseSequenceStamp 0x20000000 + +/* Trace IDs of various state machines */ +#define fiTraceSmChip 'C' +#define fiTraceSmPort 'P' +#define fiTraceSmLogin 'L' +#define fiTraceSmXchg 'X' +#define fiTraceSmFabr 'F' +#define fiTraceDiscFab 'D' +#define fiTraceDiscLoop 'M' +#define fiTraceFc2 'A' +#define fiTraceTgtState 'S' +#define fiTraceIniState 'I' + +/* Trace IDs of various queues */ +#define fiSfsFreeList 'Z' +#define fiSestFreeList 'W' +#define fiOsSfsFreeList 'G' +#define fiLgnFreeList 'K' +#define fiPortalFreeList 'l' +#define fiBusyList 'N' +#define fiOsSfsAllocList 'B' +#define fiTimerList 'V' +#define fiSfsWaitForRspList 'I' +#define fiLgnBusyList 'J' +#define fiPortalBusyList 'g' +#define fiWait4ErqList 'o' +#define fiXchgAbortList 'U' +#define fiXchgWaitList 'b' + +/* not used right now */ +#define fiSfsDeferFreeList 'q' +#define fiDeferBusyList 'm' +#define fiInvalidList 'X' +#define fiInvalidatedList 'a' +#define fiTmpXchList 'n' + +#define TMP_TRACE_BUFF_SIZE 32 +#define FC_TRACE_LINE_SIZE 70 +/******************************************************************************/ +/* Macro Conventions: we are assuming that the macros will be called inside */ +/* a function that already has a workable saRoot variable */ +/******************************************************************************/ + +/******************************************************************************/ +/* fiTraceState : ==> _!n_ _ss: XXXXXXXX _se: XXXXXXXX */ +/* statemachine --^ currentstate--^ triggerevent--^ */ +/* NOTE: shorthand forms available as macros below. */ +/******************************************************************************/ +#ifdef SA_ENABLE_TRACE_FUNCTIONS + + +void siResetTraceBuffer(agsaRoot_t *agRoot); +void siTraceFuncEnter(agsaRoot_t *agRoot, bit32 mask, bit32 fileid, char *funcid); + + +GLOBAL void siTraceFuncExit( agsaRoot_t *agRoot, bit32 mask, char fileid, char * funcid, char exitId ); + + +void siTrace(agsaRoot_t *agRoot, bit32 mask, char *uId, bit32 value, bit32 dataSizeInBits); +void siTrace64(agsaRoot_t *agRoot, bit32 mask, char *uId, bit64 value, bit32 dataSizeInBits); +bit32 siGetCurrentTraceIndex(agsaRoot_t *agRoot); +void siTraceListRemove(agsaRoot_t *agRoot, bit32 mask, char listId, bitptr exchangeId); +void siTraceListAdd(agsaRoot_t *agRoot, bit32 mask, char listId, bitptr exchangeId); +void siTraceState(agsaRoot_t *agRoot, bit32 mask, bit32 statemachine, bit32 currentstate, bit32 triggerevent); + +#define smTraceState(L,S,C,T) siTraceState(agRoot,L,S,C,T) +#define smTraceChipState(L,C,T) siTraceState(agRoot,L,fiTraceSmChip,C,T) +#define smTraceFabricState(L,C,T) siTraceState(agRoot,L,fiTraceSmFabr,C,T) +#define smTracePortState(L,C,T) siTraceState(agRoot,L,fiTraceSmPort,C,T) +#define smTraceLoginState(L,C,T) siTraceState(agRoot,L,fiTraceSmLogin,C,T) +#define smTraceXchgState(L,C,T) siTraceState(agRoot,L,fiTraceSmXchg,C,T) +#define smTraceDiscFabState(L,C,T) siTraceState(agRoot,L,fiTraceDiscFab,C,T) +#define smTraceDiscLoopState(L,C,T) siTraceState(agRoot,L,fiTraceDiscLoop,C,T) +#define smTraceFc2State(L,C,T) siTraceState(agRoot,L,fiTraceFc2,C,T) +#define smTraceScsiTgtState(L,C,T) siTraceState(agRoot,L,fiTraceTgtState,C,T) +#define smTraceScsiIniState(L,C,T) siTraceState(agRoot,L,fiTraceIniState,C,T) + +#define smResetTraceBuffer(L) siResetTraceBuffer(L) +#define smTraceFuncEnter(L,I) siTraceFuncEnter(agRoot,L,siTraceFileID,I) +#define smTraceFuncExit(L,S,I) siTraceFuncExit(agRoot,L,siTraceFileID,I,S) +#define smGetCurrentTraceIndex(L) siGetCurrentTraceIndex(L) +#define smTraceListRemove(R,L,I,V) siTraceListRemove(R,L,I,V) +#define smTraceListAdd(R,L,I,V) siTraceListAdd(R,L,I,V) + +#define smTrace(L,I,V) \ + /*lint -e506 */ \ + /*lint -e774 */ \ + if (sizeof(V) == 8) {siTrace64(agRoot,L,I,(bit64)V,64);} \ + else {siTrace(agRoot,L,I,(bit32)V,32);} \ + /*lint +e506 */ \ + /*lint +e774 */ + + +#else + +#define siTraceState(agRoot,L,fiTraceSmXchg,C,T) + +#define smTraceState(L,S,C,T) +#define smTraceChipState(L,C,T) +#define smTraceFabricState(L,C,T) +#define smTracePortState(L,C,T) +#define smTraceLoginState(L,C,T) +#define smTraceXchgState(L,C,T) +#define smTraceDiscFabState(L,C,T) +#define smTraceDiscLoopState(L,C,T) +#define smTraceFc2State(L,C,T) +#define smTraceScsiTgtState(L,C,T) +#define smTraceScsiIniState(L,C,T) + +#define smResetTraceBuffer(agRoot) +#define smTraceFuncEnter(L,I) +#define smTraceFuncExit(L,S,I) +#define smGetCurrentTraceIndex(L) +#define smTraceListRemove(L,I,V) +#define smTraceListAdd(L,I,V) + +#define smTrace(L,I,V) + +#endif + +struct hpTraceBufferParms_s { + bit32 TraceCompiled; + bit32 BufferSize; + bit32 CurrentTraceIndexWrapCount; + bit32 CurrentIndex; + bit32 TraceWrap; + bit8 * pTrace; + bit32 * pCurrentTraceIndex; + bit32 * pTraceIndexWrapCount; + bit32 * pTraceMask; +}; +typedef struct hpTraceBufferParms_s + hpTraceBufferParms_t; + +#ifdef SA_ENABLE_TRACE_FUNCTIONS + +GLOBAL void siTraceGetInfo(agsaRoot_t *agRoot, hpTraceBufferParms_t * pBParms); + +#define smTraceGetInfo(R,P) siTraceGetInfo(R,P) +#else +#define smTraceGetInfo(R,P) +#endif + + +void siEnableTracing ( agsaRoot_t *agRoot ); +#ifdef SA_ENABLE_TRACE_FUNCTIONS + +GLOBAL void siTraceSetMask(agsaRoot_t *agRoot, bit32 TraceMask ); + +#define smTraceSetMask(R,P) siTraceSetMask(R,P) +#else +#define smTraceSetMask(R,P) +#endif /* SA_ENABLE_TRACE_FUNCTIONS */ + +#endif /* #ifndef __SPCDEBUG_H__ */ + diff --git a/sys/dev/pms/RefTisa/sallsdk/spc/sadefs.h b/sys/dev/pms/RefTisa/sallsdk/spc/sadefs.h new file mode 100644 index 000000000000..b2388f70ee3e --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/spc/sadefs.h @@ -0,0 +1,320 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/*******************************************************************************/ +/*! \file sadefs.h + * \brief The file defines the constants used by LL layer + */ + +/*******************************************************************************/ + +#ifndef __SADEFS_H__ + +#define __SADEFS_H__ + +#define SA_LL_IBQ_PROTECT + +#define AGSA_MAX_VALID_PORTS AGSA_MAX_VALID_PHYS /**< defines the maximum number of ports */ + +#define NUM_TIMERS 2 /**< defines the maximum number of timers */ +#define SA_USECS_PER_TICK 1000000 /**< defines the heart beat of the LL layer 1us */ +#define MAX_ACTIVE_IO_REQUESTS 4096 /**< Maximum Active IO Requests */ +#define SMP_RESPONSE_FRAMES AGSA_MAX_VALID_PHYS /**< SMP Response Frame Buffer */ +#define MAX_NUM_VECTOR 64 /**< Maximum Number of Interrupt Vectors */ +#define REGISTER_DUMP_BUFF_SIZE 0x4000 /**< Maximum Fatal Error Register Dump Buffer Size */ +#define KBYTES 1024 + +/* number of IQ/OQ */ +#define IQ_NUM_32 32 +#define OQ_NUM_32 32 + +/* default value of Inbound/Outbound element size */ +#define INBOUND_DEPTH_SIZE 512 +#define OUTBOUND_DEPTH_SIZE 512 + +/* Priority of Queue */ +#define MPI_QUEUE_NORMAL 0 +#define MPI_QUEUE_PRIORITY 1 + +/* size of IOMB - multiple with 32 bytes */ +#define IOMB_SIZE64 64 +#define IOMB_SIZE96 96 +#define IOMB_SIZE128 128 +#define IOMB_SIZE256 256 + +/* DIR bit of IOMB for SSP read/write command */ +#define DIR_NODATA 0x000 +#define DIR_READ 0x100 +#define DIR_WRITE 0x200 + +/* TLR bits mask */ +#define TLR_MASK 0x00000003 +/* port and phy Id bits Mask */ + + +#define PORTID_MASK 0x0000000F +#define PORTID_V_MASK 0x000000FF +#define PHYID_MASK 0x0000000F +#define PHYID_V_MASK 0x000000FF +#define PORT_STATE_MASK 0x0000000F +#define PHY_IN_PORT_MASK 0x000000F0 + +#define SM_PHYID_MASK (smIS_SPC(agRoot) ? PHYID_MASK : PHYID_V_MASK ) +#define SM_PORTID_MASK (smIS_SPC(agRoot) ? PORTID_MASK : PORTID_V_MASK ) + +/* the index for memory requirement, must be continious */ +#define LLROOT_MEM_INDEX 0 /**< the index of root memory */ +#define DEVICELINK_MEM_INDEX (LLROOT_MEM_INDEX + 1) /**< the index of device descriptors memory */ +#define IOREQLINK_MEM_INDEX (DEVICELINK_MEM_INDEX+1) /**< the index of IO requests memory */ + +#ifdef SA_ENABLE_HDA_FUNCTIONS +#define HDA_DMA_BUFFER (IOREQLINK_MEM_INDEX+1) /** HDA Buffer */ +#else /* SA_ENABLE_HDA_FUNCTIONS */ +#define HDA_DMA_BUFFER (IOREQLINK_MEM_INDEX) /** HDA Buffer */ +#endif /* SA_ENABLE_HDA_FUNCTIONS */ + +#ifdef SA_ENABLE_TRACE_FUNCTIONS +#define LL_FUNCTION_TRACE (HDA_DMA_BUFFER+1) /**TraceLog */ +#else /* SA_ENABLE_TRACE_FUNCTIONS */ +#define LL_FUNCTION_TRACE HDA_DMA_BUFFER /**TraceLog */ +#endif /* END SA_ENABLE_TRACE_FUNCTIONS */ + +#define TIMERLINK_MEM_INDEX (LL_FUNCTION_TRACE+1) /**< the index of timers memory */ + +#ifdef FAST_IO_TEST +#define LL_FAST_IO (TIMERLINK_MEM_INDEX+1) +#define MPI_IBQ_OBQ_INDEX (LL_FAST_IO + 1) + +#else /* FAST_IO_TEST */ + +#define LL_FAST_IO TIMERLINK_MEM_INDEX +#define MPI_IBQ_OBQ_INDEX (LL_FAST_IO + 1) +#endif /* FAST_IO_TEST */ + +#define MPI_MEM_INDEX (MPI_IBQ_OBQ_INDEX - LLROOT_MEM_INDEX) + +#define MPI_EVENTLOG_INDEX 0 +#define MPI_IOP_EVENTLOG_INDEX 1 +#define MPI_CI_INDEX 2 +/* The following is a reference index */ +#define MPI_PI_INDEX (MPI_CI_INDEX + 1) +#define MPI_IBQ_INDEX (MPI_PI_INDEX + 1) +#define MPI_OBQ_INDEX (MPI_IBQ_INDEX + MPI_MAX_INBOUND_QUEUES) + +#define TOTAL_MPI_MEM_CHUNKS (MPI_MAX_INBOUND_QUEUES * 2) + MPI_IBQ_INDEX + + +#define LL_DEVICE_LOCK 0 +#define LL_PORT_LOCK (LL_DEVICE_LOCK+1) +#define LL_TIMER_LOCK (LL_PORT_LOCK+1) +#define LL_IOREQ_LOCKEQ_LOCK (LL_TIMER_LOCK+1) + +#ifdef FAST_IO_TEST +#define LL_FAST_IO_LOCK (LL_IOREQ_LOCKEQ_LOCK+1) +#else /* FAST_IO_TEST */ +#define LL_FAST_IO_LOCK (LL_IOREQ_LOCKEQ_LOCK) +#endif /* FAST_IO_TEST */ + +#ifdef SA_ENABLE_TRACE_FUNCTIONS +#define LL_TRACE_LOCK (LL_FAST_IO_LOCK+1) +#else /* SA_ENABLE_TRACE_FUNCTIONS */ +#define LL_TRACE_LOCK (LL_FAST_IO_LOCK) +#endif /* SA_ENABLE_TRACE_FUNCTIONS */ + +#ifdef MPI_DEBUG_TRACE_ENABLE +#define LL_IOMB_TRACE_LOCK (LL_TRACE_LOCK+1) +#else /* MPI_DEBUG_TRACE_ENABLE */ +#define LL_IOMB_TRACE_LOCK (LL_TRACE_LOCK) +#endif /* MPI_DEBUG_TRACE_ENABLE */ + +#define LL_IOREQ_OBQ_LOCK (LL_IOMB_TRACE_LOCK+1) + +#define LL_IOREQ_IBQ_LOCK (LL_IOREQ_OBQ_LOCK +1) +#define LL_IOREQ_IBQ_LOCK_PARM (LL_IOREQ_OBQ_LOCK + queueConfig->numOutboundQueues +1) +#define LL_IOREQ_IBQ0_LOCK (LL_IOREQ_OBQ_LOCK + saRoot->QueueConfig.numOutboundQueues +1) + + + +/* define phy states */ +#define PHY_STOPPED 0x00000000 /**< flag indicates phy stopped */ +#define PHY_UP 0x00000001 /**< flag indicates phy up */ +#define PHY_DOWN 0x00000002 /**< flag indicates phy down */ + +/* define port states */ +#define PORT_NORMAL 0x0000 +#define PORT_INVALIDATING 0x0002 + +/* define chip status */ +#define CHIP_NORMAL 0x0000 +#define CHIP_SHUTDOWN 0x0001 +#define CHIP_RESETTING 0x0002 +#define CHIP_RESET_FW 0x0004 +#define CHIP_FATAL_ERROR 0x0008 + +/* define device types */ +#define SAS_SATA_UNKNOWN_DEVICE 0xFF /**< SAS SATA unknown device type */ + +#define STP_DEVICE 0x00 /**< SATA device behind an expander */ +#define SSP_SMP_DEVICE 0x01 /**< SSP or SMP device type */ +#define DIRECT_SATA_DEVICE 0x02 /**< SATA direct device type */ + +/* SATA */ +#define SATA_FIS_MASK 0x00000001 +#define MAX_SATARESP_SUPPORT_BYTES 44 + +#define MARK_OFF 0xFFFFFFFF +#define PORT_MARK_OFF 0xFFFFFFFF +#define NO_FATAL_ERROR_VECTOR 0xFFFFFFFF + +#define SATA_PROTOCOL_RSRT_ASSERT 0x01 +#define SATA_PROTOCOL_RSRT_DEASSERT 0x02 +#define SATA_NON_DATA_PROTOCOL 0x0d +#define SATA_PIO_READ_PROTOCOL 0x0e +#define SATA_DMA_READ_PROTOCOL 0x0f +#define SATA_FPDMA_READ_PROTOCOL 0x10 +#define SATA_PIO_WRITE_PROTOCOL 0x11 +#define SATA_DMA_WRITE_PROTOCOL 0x12 +#define SATA_FPDMA_WRITE_PROTOCOL 0x13 +#define SATA_DEVICE_RESET_PROTOCOL 0x14 + +/* Definition for bit shift */ +#define SHIFT0 0 +#define SHIFT1 1 +#define SHIFT2 2 +#define SHIFT3 3 +#define SHIFT4 4 +#define SHIFT5 5 +#define SHIFT6 6 +#define SHIFT7 7 +#define SHIFT8 8 +#define SHIFT9 9 +#define SHIFT10 10 +#define SHIFT11 11 +#define SHIFT12 12 +#define SHIFT13 13 +#define SHIFT14 14 +#define SHIFT15 15 +#define SHIFT16 16 +#define SHIFT17 17 +#define SHIFT18 18 +#define SHIFT19 19 +#define SHIFT20 20 +#define SHIFT21 21 +#define SHIFT22 22 +#define SHIFT23 23 +#define SHIFT24 24 +#define SHIFT25 25 +#define SHIFT26 26 +#define SHIFT27 27 +#define SHIFT28 28 +#define SHIFT29 29 +#define SHIFT30 30 +#define SHIFT31 31 + +/* These flags used for saSSPAbort(), saSATAAbort() */ +#define ABORT_MASK 0x3 +#define ABORT_SINGLE 0x0 +#define ABORT_SCOPE 0x3 /* bits 0-1*/ +#define ABORT_ALL 0x1 +#define ABORT_TSDK_QUARANTINE 0x4 +#define ABORT_QUARANTINE_SPC 0x4 +#define ABORT_QUARANTINE_SPCV 0x8 + +/* These flags used for saGetRegDump() */ +#define REG_DUMP_NUM0 0x0 +#define REG_DUMP_NUM1 0x1 +#define REG_DUMP_NONFLASH 0x0 +#define REG_DUMP_FLASH 0x1 + +/* MSIX Interupts */ +#define MSIX_TABLE_OFFSET 0x2000 +#define MSIX_TABLE_ELEMENT_SIZE 0x10 +#define MSIX_INTERRUPT_CONTROL_OFFSET 0xC +#define MSIX_TABLE_BASE (MSIX_TABLE_OFFSET+MSIX_INTERRUPT_CONTROL_OFFSET) +#define MSIX_INTERRUPT_DISABLE 0x1 +#define MSIX_INTERRUPT_ENABLE 0x0 + +#define MAX_QUEUE_EACH_MEM 8 + +#define NUM_MEM_CHUNKS(Q, rem) ((((bit32)Q % rem) > 0) ? (bit32)(Q/rem+1) : (bit32)(Q/rem)) +#define NUM_QUEUES_IN_MEM(Q, rem) ((((bit32)Q % rem) > 0) ? (bit32)(Q%rem) : (bit32)(MAX_QUEUE_EACH_MEM)) + +#define MAX_DEV_BITS 0xFFFF0000 +#define PHY_COUNT_BITS 0x01f80000 +#define Q_SUPPORT_BITS 0x0007ffff +#define SAS_SPEC_BITS 0xfe000000 +#define HP_SUPPORT_BIT 0x00010000 +#define INT_COL_BIT 0x00040000 +#define INT_DELAY_BITS 0xFFFF +#define INT_THR_BITS 0xFF +#define INT_VEC_BITS 0xFF + +#define AUTO_HARD_RESET_DEREG_FLAG 0x00000001 +#define AUTO_FW_CLEANUP_DEREG_FLAG 0x00000002 + +#define BYTE_MASK 0xff + +#define INT_OPTION 0x7FFF +#define SMP_TO_DEFAULT 100 +#define ITL_TO_DEFAULT 0xFFFF + + +/* +agsaHwConfig_s hwOption +*/ +#define HW_CFG_PICI_EFFECTIVE_ADDRESS 0x1 + +/* SPC or SPCv ven dev Id */ + +#define SUBID_SPC 0x00000000 +#define SUBID_SPCV 0x56781234 + +#define VEN_DEV_SPC 0x80010000 +#define VEN_DEV_HIL 0x80810000 + +#define VEN_DEV_SPCV 0x80080000 +#define VEN_DEV_SPCVE 0x80090000 +#define VEN_DEV_SPCVP 0x80180000 +#define VEN_DEV_SPCVEP 0x80190000 + +#define VEN_DEV_SPC12V 0x80700000 +#define VEN_DEV_SPC12VE 0x80710000 +#define VEN_DEV_SPC12VP 0x80720000 +#define VEN_DEV_SPC12VEP 0x80730000 +#define VEN_DEV_9015 0x90150000 +#define VEN_DEV_9060 0x90600000 + +#define VEN_DEV_ADAPVEP 0x80890000 +#define VEN_DEV_ADAPVP 0x80880000 + + +#define VEN_DEV_SFC 0x80250000 + +/*DelRay PCIid */ +#define VEN_DEV_SPC12ADP 0x80740000 /* 8 ports */ +#define VEN_DEV_SPC12ADPE 0x80750000 /* 8 ports encrypt */ +#define VEN_DEV_SPC12ADPP 0x80760000 /* 16 ports */ +#define VEN_DEV_SPC12ADPEP 0x80770000 /* 16 ports encrypt */ +#define VEN_DEV_SPC12SATA 0x80060000 /* SATA HBA */ + +#endif /*__SADEFS_H__ */ diff --git a/sys/dev/pms/RefTisa/sallsdk/spc/sadisc.c b/sys/dev/pms/RefTisa/sallsdk/spc/sadisc.c new file mode 100644 index 000000000000..13916b204365 --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/spc/sadisc.c @@ -0,0 +1,864 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +/*******************************************************************************/ +/*! \file sadisc.c + * \brief The file implements the functions to do SAS/SATA discovery + */ + +/******************************************************************************/ + +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#ifdef SA_ENABLE_TRACE_FUNCTIONS +#ifdef siTraceFileID +#undef siTraceFileID +#endif +#define siTraceFileID 'C' +#endif + +/******************************************************************************/ +/*! \brief Start/Abort SAS/SATA discovery + * + * Start/Abort SAS/SATA discovery + * + * \param agRoot Handles for this instance of SAS/SATA hardware + * \param agPortContext Pointer to this instance of port context + * \param type Specifies the type(s) of discovery operation to start or cancel + * \param option Specified the discovery option + * + * \return If discovery is started/aborted successfully + * - \e AGSA_RC_SUCCESS discovery is started/aborted successfully + * - \e AGSA_RC_FAILURE discovery is not started/aborted successfully + * + */ +/*******************************************************************************/ +GLOBAL bit32 saDiscover( + agsaRoot_t *agRoot, + agsaPortContext_t *agPortContext, + bit32 type, + bit32 option + ) +{ + /* Currently not supported */ + return AGSA_RC_FAILURE; +} + +/******************************************************************************/ +/*! \brief Function for target to remove stale initiator device handle + * + * function is called to ask the LL layer to remove all LL layer and SPC firmware + * internal resources associated with a device handle + * + * \param agRoot Handles for this instance of SAS/SATA hardware + * \param agDevHandle Handle of the device that this I/O request will be made on + * + * \return If the device handle is removed successfully + * - \e AGSA_RC_SUCCESS the device handle is removed successfully + * - \e AGSA_RC_BUSY the device is busy, cannot be removed now + * + */ +/*******************************************************************************/ +GLOBAL bit32 saDeregisterDeviceHandle( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaDevHandle_t *agDevHandle, + bit32 queueNum + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaDeviceDesc_t *pDevice; + agsaPort_t *pPort; + bit32 ret = AGSA_RC_SUCCESS; + bit32 deviceid, portid; + bit32 deviceIdx; + + OS_ASSERT(agDevHandle != agNULL, "saDeregisterDeviceHandle agDevHandle is NULL"); + + smTraceFuncEnter(hpDBG_VERY_LOUD, "za"); + + if(agNULL == agDevHandle) + { + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "za"); + return AGSA_RC_FAILURE; + } + + pDevice = (agsaDeviceDesc_t *) (agDevHandle->sdkData); + + OS_ASSERT(pDevice != agNULL, "saDeregisterDeviceHandle pDevice is NULL"); + if(pDevice == agNULL) + { + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "za"); + return AGSA_RC_FAILURE; + } + + /* find device id */ + deviceid = pDevice->DeviceMapIndex; + deviceIdx = deviceid & DEVICE_ID_BITS; + OS_ASSERT(deviceIdx < MAX_IO_DEVICE_ENTRIES, "deviceIdx MAX_IO_DEVICE_ENTRIES"); + pPort = pDevice->pPort; + /* find port id */ + portid = pPort->portId; + + SA_DBG3(("saDeregisterDeviceHandle: start DeviceHandle %p\n", agDevHandle)); + SA_DBG1(("saDeregisterDeviceHandle: deviceId 0x%x Device Context %p\n", deviceid, pDevice)); + + if ((deviceid != saRoot->DeviceMap[deviceIdx].DeviceIdFromFW) || + (pDevice != saRoot->DeviceMap[deviceIdx].DeviceHandle)) + { + SA_DBG1(("saDeregisterDeviceHandle: Not match failure\n")); + ret = AGSA_RC_FAILURE; + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "za"); + return ret; + } + + /* Build IOMB and send it to SPC */ + ret = mpiDeregDevHandleCmd(agRoot, agContext, pDevice, deviceid, portid, queueNum); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "za"); + return ret; +} + +/******************************************************************************/ +/*! \brief Function for target to remove stale initiator device handle + * + * function is called to ask the LL layer to remove all LL layer internal resources + * associated with a device handle + * + * \param agRoot Handles for this instance of SAS/SATA hardware + * \param agDevHandle Handle of the device that this I/O request will be made on + * + * \return If the device handle is removed successfully + * - \e AGSA_RC_SUCCESS the device handle is removed successfully + * - \e AGSA_RC_BUSY the device is busy, cannot be removed now + * + */ +/*******************************************************************************/ +GLOBAL bit32 siRemoveDevHandle( + agsaRoot_t *agRoot, + agsaDevHandle_t *agDevHandle + ) +{ + agsaDeviceDesc_t *pDevice = (agsaDeviceDesc_t *) (agDevHandle->sdkData); + agsaPort_t *pPort; + bit32 ret = AGSA_RC_SUCCESS; + + OS_ASSERT(pDevice != agNULL, "siRemoveDevHandle is NULL"); + smTraceFuncEnter(hpDBG_VERY_LOUD,"zb"); + + if (pDevice == agNULL) + { + SA_DBG1(("siRemoveDevHandle: pDevice is NULL \n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "zb"); + return AGSA_RC_FAILURE; + } + + /* If it's to remove an initiator device handle */ + if ( &(pDevice->initiatorDevHandle) == agDevHandle ) + { + (pDevice->initiatorDevHandle).sdkData = agNULL; + } + /* If it's to remove an target device handle */ + else if ( &(pDevice->targetDevHandle) == agDevHandle ) + { + (pDevice->targetDevHandle).sdkData = agNULL; + } + else + { + SA_ASSERT(agFALSE, ""); + } + + /* remove the device descriptor if it doesn't have either initiator handle and target handle */ + if ( (agNULL == (pDevice->initiatorDevHandle).sdkData) + && (agNULL == (pDevice->targetDevHandle).sdkData) ) + { + /* Find the port of the device */ + pPort = pDevice->pPort; + + /* remove the device descriptor free discover list */ + switch ( pDevice->deviceType ) + { + case STP_DEVICE: /* fall through */ + case SSP_SMP_DEVICE: + case DIRECT_SATA_DEVICE: + { + SA_DBG3(("siRemoveDevHandle: remove device context %p\n", pDevice)); + siPortDeviceRemove(agRoot, pPort, pDevice, agTRUE); + break; + } + default: + { + SA_DBG1(("siRemoveDevHandle: switch. Not calling siPortDeviceRemove %d\n", pDevice->deviceType)); + break; + } + } + } + else + { + SA_DBG1(("siRemoveDevHandle: else. Not caling siPortDeviceRemove\n")); + } + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "zb"); + return ret; +} + +/******************************************************************************/ +/*! \brief Get Device Handles from a specific local port + * + * Get a Device Handles + * + * \param agRoot Handles for this instance of SAS/SATA hardware + * \param agsaContext Pointer to this API context + * \param agPortContext Pointer to this instance of port context + * \param flags Device flags + * \param agDev[] Pointer of array of device handles + * \param MaxDevs Specified Maximum number of Device Handles + * + * \return If GetDeviceHandles is successfully or failure + * - \e AGSA_RC_SUCCESS GetDeviceHandles is successfully + * - \e AGSA_RC_FAILURE GetDeviceHandles is not successfully + * + */ +/*******************************************************************************/ +GLOBAL bit32 saGetDeviceHandles( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaPortContext_t *agPortContext, + bit32 flags, + agsaDevHandle_t *agDev[], + bit32 skipCount, + bit32 MaxDevs + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaPort_t *pPort = (agsaPort_t *) (agPortContext->sdkData); + bit32 portIndex, i; + bit32 ret = AGSA_RC_SUCCESS; + + OS_ASSERT(pPort != agNULL, "saGetDeviceHandles is NULL"); + smTraceFuncEnter(hpDBG_VERY_LOUD,"zc"); + + if (pPort == agNULL) + { + SA_DBG1(("saGetDeviceHandles: pPort is NULL \n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "zc"); + return AGSA_RC_FAILURE; + } + + SA_DBG1(("saGetDeviceHandles: start portId %d\n", pPort->portId)); + + /* save the device handles arrary pointer */ + for (i = 0; i < MaxDevs; i ++) + { + saRoot->DeviceHandle[i] = agDev[i]; + } + + /* send GET_DEVICE_HANDLE IOMB to SPC */ + portIndex = pPort->portId; + mpiGetDeviceHandleCmd(agRoot, agContext, portIndex, flags, MaxDevs, queueNum, skipCount); + + /* return */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "zc"); + return ret; +} + +/******************************************************************************/ +/*! \brief Register New Device from a specific local port + * + * Register New Device API + * + * \param agRoot Handles for this instance of SAS/SATA hardware + * \param agContext Pointer to this API context + * \param agDeviceInfo Pointer to this instance of device info + * \param agPortContext Pointer to this instance of port context + * + * \return If discovery is started/aborted successfully + * - \e AGSA_RC_SUCCESS discovery is started/aborted successfully + * - \e AGSA_RC_FAILURE discovery is not started/aborted successfully + * + */ +/*******************************************************************************/ +GLOBAL bit32 saRegisterNewDevice( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaDeviceInfo_t *agDeviceInfo, + agsaPortContext_t *agPortContext, + bit16 hostAssignedDeviceId + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaRegDevCmd_t payload; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaPort_t *pPort = (agsaPort_t *) (agPortContext->sdkData); + agsaSASIdentify_t remoteIdentify; + bit32 i, phyId, sDTypeRate; + agsaDeviceDesc_t *pDevice = agNULL; + + OS_ASSERT(pPort != agNULL, "saRegisterNewDevice is NULL"); + OS_ASSERT(saRoot != agNULL, "saRoot is NULL"); + smTraceFuncEnter(hpDBG_VERY_LOUD,"zd"); + + if(saRoot == agNULL) + { + SA_DBG1(("saRegisterNewDevice: saRoot == agNULL\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "zd"); + return(AGSA_RC_FAILURE); + } + + if (pPort == agNULL) + { + SA_DBG1(("saRegisterNewDevice: pPort is NULL \n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "zd"); + return AGSA_RC_FAILURE; + } + + SA_DBG2(("saRegisterNewDevice: start portId %d Port Context %p\n", pPort->portId, agPortContext)); + + SA_DBG2(("saRegisterNewDevice: smpTimeout 0x%x\n", agDeviceInfo->smpTimeout)); + SA_DBG2(("saRegisterNewDevice: it_NexusTimeout 0x%x\n", agDeviceInfo->it_NexusTimeout)); + SA_DBG2(("saRegisterNewDevice: firstBurstSize 0x%x\n", agDeviceInfo->firstBurstSize)); + SA_DBG2(("saRegisterNewDevice: devType_S_Rate 0x%x\n", agDeviceInfo->devType_S_Rate)); + SA_DBG2(("saRegisterNewDevice: flag 0x%x\n", agDeviceInfo->flag)); + SA_DBG2(("saRegisterNewDevice: hostAssignedDeviceId 0x%x\n",hostAssignedDeviceId )); + SA_DBG2(("saRegisterNewDevice: Addr 0x%02x%02x%02x%02x 0x%02x%02x%02x%02x\n", + agDeviceInfo->sasAddressHi[0],agDeviceInfo->sasAddressHi[1],agDeviceInfo->sasAddressHi[2],agDeviceInfo->sasAddressHi[3], + agDeviceInfo->sasAddressLo[0],agDeviceInfo->sasAddressLo[1],agDeviceInfo->sasAddressLo[2],agDeviceInfo->sasAddressLo[3] )); + + agDeviceInfo->devType_S_Rate &= DEV_LINK_RATE; + + /* + Using agsaDeviceInfo_t, fill in only sas address and device type + of identify address frame + */ + si_memset(&remoteIdentify, 0, sizeof(agsaSASIdentify_t)); + for (i=0;i<4;i++) + { + remoteIdentify.sasAddressHi[i] = agDeviceInfo->sasAddressHi[i]; + remoteIdentify.sasAddressLo[i] = agDeviceInfo->sasAddressLo[i]; + } + remoteIdentify.deviceType_addressFrameType = (bit8)(agDeviceInfo->devType_S_Rate & 0xC0); + + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeReservedRequests)); /**/ + if(agNULL != pRequest) + { + saLlistIORemove(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + SA_DBG1(("saRegisterNewDevice, using saRoot->freeReservedRequests\n")); + } + else + { + SA_DBG1(("saRegisterNewDevice, No request from free list Not using saRoot->freeReservedRequests\n")); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "zd"); + return AGSA_RC_BUSY; + } + } + else + { + /* If LL Control request entry avaliable */ + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* checking bit5 for SATA direct device */ + if (!(agDeviceInfo->devType_S_Rate & 0x20)) + { + /* SAS device */ + /* Add SAS device to the device list */ + pDevice = siPortSASDeviceAdd(agRoot, + pPort, + remoteIdentify, + agFALSE, + agDeviceInfo->smpTimeout, + agDeviceInfo->it_NexusTimeout, + agDeviceInfo->firstBurstSize, + agDeviceInfo->devType_S_Rate, + (agDeviceInfo->flag & DEV_INFO_MASK)); + } + else + { + /* SATA device */ + /* Add SATA device to the device list */ + pDevice = siPortSATADeviceAdd(agRoot, + pPort, + agNULL, + agNULL, /* no signature */ + agFALSE, + 0, + agDeviceInfo->smpTimeout, + agDeviceInfo->it_NexusTimeout, + agDeviceInfo->firstBurstSize, + agDeviceInfo->devType_S_Rate, + (agDeviceInfo->flag & DEV_INFO_MASK)); + } + + SA_DBG1(("saRegisterNewDevice: Device Context %p, TypeRate 0x%x\n", pDevice, agDeviceInfo->devType_S_Rate)); + + pRequest->pDevice = pDevice; + + /* adjust the flag bit to build the IOMB; use only bit0 and 1 */ + sDTypeRate = agDeviceInfo->devType_S_Rate << SHIFT24; + sDTypeRate |= (agDeviceInfo->flag & 0x01); + /* set AWT flag */ + sDTypeRate |= (agDeviceInfo->flag & 0x02) << 1; + + /* If the host assigned device ID is used, then set the HA bit. */ + if ( hostAssignedDeviceId != 0 ) + { + sDTypeRate |= 2; + SA_DBG3(("saRegisterNewDevice:hostAssignedDeviceId 0x%x sDTypeRate 0x%x\n",hostAssignedDeviceId,sDTypeRate )); + } + + /* Add the MCN field */ + + sDTypeRate |= ((agDeviceInfo->flag >> DEV_INFO_MCN_SHIFT) & 0xf) << 4; + + /* Add the IR field */ + sDTypeRate |= ((agDeviceInfo->flag >> DEV_INFO_IR_SHIFT) & 0x1) << 3; + + /* Add the ATAPI protocol flag */ + sDTypeRate |= ((agDeviceInfo->flag & ATAPI_DEVICE_FLAG) << SHIFT9 ); + + /* Add the AWT flag */ + sDTypeRate |= (agDeviceInfo->flag & AWT_DEVICE_FLAG) ? (1 << SHIFT2) : 0; + + /* Add the XFER_READY flag */ + sDTypeRate |= (agDeviceInfo->flag & XFER_RDY_PRIORTY_DEVICE_FLAG) ? (1 << SHIFT31) : 0; + if(agDeviceInfo->flag & XFER_RDY_PRIORTY_DEVICE_FLAG) + { + SA_DBG1(("saRegisterNewDevice: sflag XFER_RDY_PRIORTY_DEVICE_FLAG sDTypeRate 0x%x\n",sDTypeRate )); + } +#ifdef CCFLAG_FORCE_AWT_ON + sDTypeRate |= (1 << SHIFT2); + SA_DBG1(("saRegisterNewDevice: Force AWT_DEVICE_FLAG sDTypeRate 0x%x\n",sDTypeRate )); +#endif /* CCFLAG_FORCE_AWT_ON */ + + /* create payload for IOMB */ + si_memset(&payload, 0, sizeof(agsaRegDevCmd_t)); + + SA_DBG2(("saRegisterNewDevice,flag 0x%08X\n",agDeviceInfo->flag)); + if ((agDeviceInfo->devType_S_Rate & 0x30) == 0x20) + { + if(smIS_SPC(agRoot)) + { + /* direct SATA device */ + phyId = (agDeviceInfo->flag & 0xF0); + } + else + { + phyId = (agDeviceInfo->flag & 0xF0) << SHIFT4; + } + } + else + { + phyId = 0; + } + + smTrace(hpDBG_VERY_LOUD,"QQ",phyId); + /* TP:QQ phyId */ + smTrace(hpDBG_VERY_LOUD,"QR",pPort->portId); + /* TP:QR portId */ + smTrace(hpDBG_VERY_LOUD,"QS",sDTypeRate); + /* TP:QS sDTypeRate */ + smTrace(hpDBG_VERY_LOUD,"QT",agDeviceInfo->it_NexusTimeout); + /* TP:QT agDeviceInfo->it_NexusTimeout */ + + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaRegDevCmd_t, phyIdportId), (bit32)(pPort->portId & PORTID_MASK) | phyId); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaRegDevCmd_t, dTypeLRateAwtHa), sDTypeRate); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaRegDevCmd_t, ITNexusTimeOut), (agDeviceInfo->it_NexusTimeout)); + + smTrace(hpDBG_VERY_LOUD,"QT",(bit32)(pPort->portId & PORTID_MASK) | phyId); + /* TP:QT phyIdportId */ + /* no conversion is needed since SAS address is in BE format */ + payload.sasAddrHi = *(bit32*)agDeviceInfo->sasAddressHi; + payload.sasAddrLo = *(bit32*)agDeviceInfo->sasAddressLo; + + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaRegDevCmd_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaRegDevCmd_t, DeviceId), ((bit32)hostAssignedDeviceId) << 16); + + if(smIS_SPC(agRoot)) + { + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_SPC_REG_DEV, IOMB_SIZE64, queueNum); + } + else + { + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_REG_DEV, IOMB_SIZE64, queueNum); + } + + if (AGSA_RC_SUCCESS != ret) + { + /* return the request to free pool */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("saRegisterNewDevice: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saRegisterNewDevice, sending IOMB failed\n" )); + } + SA_DBG3(("saRegisterNewDevice: end\n")); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "zd"); + return ret; +} + +/******************************************************************************/ +/*! \brief Register a callback for a specific event + * + * Register a callback for a Event API + * + * \param agRoot Handles for this instance of SAS/SATA hardware + * \param eventSourceType Event Type + * \param callbackPtr Function pointer to OS layer + * + * \return + * - \e AGSA_RC_SUCCESS + * - \e AGSA_RC_FAILURE + * + */ +/*******************************************************************************/ +GLOBAL bit32 saRegisterEventCallback( + agsaRoot_t *agRoot, + bit32 eventSourceType, + ossaGenericCB_t callbackPtr + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + bit32 ret = AGSA_RC_FAILURE; + + SA_DBG3(("saRegisterEventCallback: start\n")); + switch (eventSourceType) + { + case OSSA_EVENT_SOURCE_DEVICE_HANDLE_ADDED: + saRoot->DeviceRegistrationCB = (ossaDeviceRegistrationCB_t)callbackPtr; + ret = AGSA_RC_SUCCESS; + break; + case OSSA_EVENT_SOURCE_DEVICE_HANDLE_REMOVED: + saRoot->DeviceDeregistrationCB = (ossaDeregisterDeviceHandleCB_t) callbackPtr; + ret = AGSA_RC_SUCCESS; + break; + default: + SA_DBG1(("saRegisterEventCallback: not allowed case %d\n", eventSourceType)); + ret = AGSA_RC_FAILURE; + break; + } + return ret; +} + +/******************************************************************************/ +/*! \brief Get Device Information + * + * Get SAS/SATA device information API + * + * \param agRoot Handles for this instance of SAS/SATA hardware + * \param option device general information or extended information + * \param agDevHandle Pointer of device handle + * + * \return + * - \e AGSA_RC_SUCCESS + * - \e AGSA_RC_FAILURE + * + */ +/*******************************************************************************/ +GLOBAL bit32 saGetDeviceInfo( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 option, + bit32 queueNum, + agsaDevHandle_t *agDevHandle + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaDeviceDesc_t *pDevice = (agsaDeviceDesc_t *) (agDevHandle->sdkData); + bit32 deviceid; + bit32 ret = AGSA_RC_FAILURE; + + OS_ASSERT(pDevice != agNULL, "saGetDeviceInfo is NULL"); + smTraceFuncEnter(hpDBG_VERY_LOUD,"ze"); + + if (pDevice == agNULL) + { + SA_DBG1(("saGetDeviceInfo: pDevice is NULL \n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "ze"); + return AGSA_RC_FAILURE; + } + + /* Get deviceid */ + deviceid = pDevice->DeviceMapIndex; + SA_DBG3(("saGetDeviceInfo: start pDevice %p, deviceId %d\n", pDevice, deviceid)); + + /* verify the agDeviceHandle with the one in the deviceMap */ + if ((deviceid != saRoot->DeviceMap[deviceid & DEVICE_ID_BITS].DeviceIdFromFW) || + (pDevice != saRoot->DeviceMap[deviceid & DEVICE_ID_BITS].DeviceHandle)) + { + SA_DBG1(("saGetDeviceInfo: Not match failure or device not exist\n")); + ret = AGSA_RC_FAILURE; + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "ze"); + return ret; + } + + /* send IOMB to the SPC */ + ret = mpiGetDeviceInfoCmd(agRoot, agContext, deviceid, option, queueNum); + + SA_DBG3(("saGetDeviceInfo: end\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "ze"); + return ret; +} + +/******************************************************************************/ +/*! \brief Set Device Information + * + * Set SAS/SATA device information API + * + * \param agRoot Handles for this instance of SAS/SATA hardware + * \param agContext Pointer to this API context + * \param queueNum IQ/OQ number + * \param agDevHandle Pointer of device handle + * \param option device general information or extended information + * \param param Parameter of Set Device Infomation + * + * \return + * - \e AGSA_RC_SUCCESS + * - \e AGSA_RC_FAILURE + * + */ +/*******************************************************************************/ +GLOBAL bit32 saSetDeviceInfo( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaDevHandle_t *agDevHandle, + bit32 option, + bit32 param, + ossaSetDeviceInfoCB_t agCB + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaDeviceDesc_t *pDevice = (agsaDeviceDesc_t *) (agDevHandle->sdkData); + bit32 deviceid; + bit32 ret = AGSA_RC_FAILURE; + + OS_ASSERT(pDevice != agNULL, "saSetDeviceInfo is NULL"); + smTraceFuncEnter(hpDBG_VERY_LOUD,"zf"); + + SA_DBG2(("saSetDeviceInfo: start pDevice %p, option=0x%x param=0x0%x\n", pDevice, option, param)); + if(agNULL == pDevice ) + { + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "zf"); + return ret; + } + + + /* Get deviceid */ + deviceid = pDevice->DeviceMapIndex; + pDevice->option = option; + pDevice->param = param; + + SA_DBG3(("saSetDeviceInfo: deviceId %d\n", deviceid)); + + /* verify the agDeviceHandle with the one in the deviceMap */ + if ((deviceid != saRoot->DeviceMap[deviceid & DEVICE_ID_BITS].DeviceIdFromFW) || + (pDevice != saRoot->DeviceMap[deviceid & DEVICE_ID_BITS].DeviceHandle)) + { + SA_DBG1(("saSetDeviceInfo: Not match failure or device not exist\n")); + ret = AGSA_RC_FAILURE; + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "zf"); + return ret; + } + + /* send IOMB to the SPC */ + ret = mpiSetDeviceInfoCmd(agRoot, agContext, deviceid, option, queueNum, param, agCB); + + SA_DBG3(("saSetDeviceInfo: end\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "zf"); + return ret; +} + +/******************************************************************************/ +/*! \brief Get Device State + * + * Get SAS/SATA device state API + * + * \param agRoot Handles for this instance of SAS/SATA hardware + * \param agContext Pointer to this API context + * \param queueNum IQ/OQ number + * \param agDevHandle Pointer of device handler + * + * \return + * - \e AGSA_RC_SUCCESS + * - \e AGSA_RC_FAILURE + * + */ +/*******************************************************************************/ +GLOBAL bit32 saGetDeviceState( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaDevHandle_t *agDevHandle + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaDeviceDesc_t *pDevice = (agsaDeviceDesc_t *) (agDevHandle->sdkData); + bit32 deviceid; + bit32 ret = AGSA_RC_FAILURE; + + OS_ASSERT(pDevice != agNULL, "saGetDeviceState is NULL"); + smTraceFuncEnter(hpDBG_VERY_LOUD,"zg"); + + if (pDevice == agNULL) + { + SA_DBG1(("saGetDeviceState: pDevice is NULL \n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "zg"); + return AGSA_RC_FAILURE; + } + + SA_DBG3(("saGetDeviceState: start pDevice %p\n", pDevice)); + + /* Get deviceid */ + deviceid = pDevice->DeviceMapIndex; + + /* verify the agDeviceHandle with the one in the deviceMap */ + if ((deviceid != saRoot->DeviceMap[deviceid & DEVICE_ID_BITS].DeviceIdFromFW) || + (pDevice != saRoot->DeviceMap[deviceid & DEVICE_ID_BITS].DeviceHandle)) + { + SA_DBG1(("saGetDeviceState: Not match failure or device not exist\n")); + ret = AGSA_RC_FAILURE; + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "zg"); + return ret; + } + + /* send IOMB to the SPC */ + ret = mpiGetDeviceStateCmd(agRoot, agContext, deviceid, queueNum); + + SA_DBG3(("saGetDeviceState: end\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "zg"); + return ret; +} + +/******************************************************************************/ +/*! \brief Set Device State + * + * Set SAS/SATA device state API + * + * \param agRoot Handles for this instance of SAS/SATA hardware + * \param agContext Pointer to this API context + * \param queueNum IQ/OQ number + * \param agDevHandle Pointer of device handler + * \param newDeviceState new device state + * + * \return + * - \e AGSA_RC_SUCCESS + * - \e AGSA_RC_FAILURE + * + */ +/*******************************************************************************/ +GLOBAL bit32 saSetDeviceState( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaDevHandle_t *agDevHandle, + bit32 newDeviceState + ) +{ + agsaLLRoot_t *saRoot; + agsaDeviceDesc_t *pDevice; + bit32 deviceid; + bit32 ret = AGSA_RC_FAILURE; + + saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + OS_ASSERT(saRoot != agNULL, "saSetDeviceState saRoot"); + + if(saRoot == agNULL ) + { + SA_DBG1(("saSetDeviceState: saRoot is NULL\n")); + return ret; + } + + OS_ASSERT(agDevHandle != agNULL, "saSetDeviceState agDevHandle is NULL"); + + smTraceFuncEnter(hpDBG_VERY_LOUD,"zh"); + + if(agDevHandle == agNULL ) + { + SA_DBG1(("saSetDeviceState: agDevHandle is NULL\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "zh"); + return ret; + } + + pDevice = (agsaDeviceDesc_t *) (agDevHandle->sdkData); + + OS_ASSERT(pDevice != agNULL, "saSetDeviceState pDevice is NULL"); + + SA_DBG3(("saSetDeviceState: start pDevice %p\n", pDevice)); + + if(pDevice == agNULL ) + { + SA_DBG1(("saSetDeviceState: pDevice is NULL\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "zh"); + return ret; + } + /* Get deviceid */ + deviceid = pDevice->DeviceMapIndex; + + /* verify the agDeviceHandle with the one in the deviceMap */ + if ((deviceid != saRoot->DeviceMap[deviceid & DEVICE_ID_BITS].DeviceIdFromFW) || + (pDevice != saRoot->DeviceMap[deviceid & DEVICE_ID_BITS].DeviceHandle)) + { + SA_DBG1(("saSetDeviceState: Not match failure or device not exist\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "zh"); + return ret; + } + + /* send IOMB to the SPC */ + ret = mpiSetDeviceStateCmd(agRoot, agContext, deviceid, newDeviceState, queueNum); + + SA_DBG3(("saSetDeviceState: end\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "zh"); + return ret; +} diff --git a/sys/dev/pms/RefTisa/sallsdk/spc/saframe.c b/sys/dev/pms/RefTisa/sallsdk/spc/saframe.c new file mode 100644 index 000000000000..40951b7e2432 --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/spc/saframe.c @@ -0,0 +1,125 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +/*******************************************************************************/ +/*! \file saframe.c + * \brief The file implements the functions to read frame content + */ + + +/******************************************************************************/ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#ifdef SA_ENABLE_TRACE_FUNCTIONS +#ifdef siTraceFileID +#undef siTraceFileID +#endif +#define siTraceFileID 'D' +#endif + +/******************************************************************************/ +/*! \brief Read 32 bits from a frame + * + * Read 32 bits from a frame + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param agFrame The frame handler + * \param frameOffset Offset in bytes from the beginning of valid frame bytes or IU + to the 32-bit value to read + * + * \return The read value + * + */ +/*******************************************************************************/ +GLOBAL bit32 saFrameReadBit32( + agsaRoot_t *agRoot, + agsaFrameHandle_t agFrame, + bit32 frameOffset + ) +{ + bit8 *payloadAddr; + bit32 value = 0; + + smTraceFuncEnter(hpDBG_VERY_LOUD, "zr"); + + if ( agNULL != agFrame ) + { + /* Find the address of the payload */ + payloadAddr = (bit8 *)(agFrame) + frameOffset; + + /* read one DW Data */ + value = *(bit32 *)payloadAddr; + } + + + /* (5) return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "zr"); + return value; +} + +/******************************************************************************/ +/*! \brief Read a block from a frame + * + * Read a block from a frame + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param agFrame The frame handler + * \param frameOffset The offset of the frame to start read + * \param frameBuffer The pointer to the destination of data read from the frame + * \param frameBufLen Number of bytes to read from the frame + * + * \return -void- + * + */ +/*******************************************************************************/ +GLOBAL void saFrameReadBlock ( + agsaRoot_t *agRoot, + agsaFrameHandle_t agFrame, + bit32 frameOffset, + void *frameBuffer, + bit32 frameBufLen + ) +{ + bit8 *payloadAddr; + bit32 i; + + smTraceFuncEnter(hpDBG_VERY_LOUD, "zi"); + + /* Sanity check */ + SA_ASSERT(frameBufLen < 4096, "saFrameReadBlock read more than 4k"); + + if ( agNULL != agFrame ) + { + /* Find the address of the payload */ + payloadAddr = (bit8 *)(agFrame) + frameOffset; + /* Copy the frame data to the destination frame buffer */ + for ( i = 0; i < frameBufLen; i ++ ) + { + *(bit8 *)((bit8 *)frameBuffer + i) = *(bit8 *)(payloadAddr + i); + } + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "zi"); +} + diff --git a/sys/dev/pms/RefTisa/sallsdk/spc/saglobal.h b/sys/dev/pms/RefTisa/sallsdk/spc/saglobal.h new file mode 100644 index 000000000000..d51c604f0225 --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/spc/saglobal.h @@ -0,0 +1,56 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/*******************************************************************************/ +/*! \file saglobal.h + * \brief This file defines global types + */ + +/*******************************************************************************/ + +#ifndef __SAGLOBAL_H__ +#define __SAGLOBAL_H__ + +#include +#include +#include + +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif /* __SAGLOBAL_H__ */ diff --git a/sys/dev/pms/RefTisa/sallsdk/spc/sahw.c b/sys/dev/pms/RefTisa/sallsdk/spc/sahw.c new file mode 100644 index 000000000000..fe9278466217 --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/spc/sahw.c @@ -0,0 +1,3017 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +/*******************************************************************************/ +/*! \file sahw.c + * \brief The file implements the functions for reset and shutdown + */ +/******************************************************************************/ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#ifdef SA_ENABLE_HDA_FUNCTIONS +#ifndef SA_EXCLUDE_FW_IMG +/* +#include "istrimg.h" +#include "ilaimg.h" +#include "aap1img.h" +#include "iopimg.h" +*/ +#endif +#endif +#if defined(SALLSDK_DEBUG) +extern bit32 gLLSoftResetCounter; +#endif + +#ifdef SA_ENABLE_TRACE_FUNCTIONS +#ifdef siTraceFileID +#undef siTraceFileID +#endif +#define siTraceFileID 'E' +#endif + + +bit32 gWait_3 = 3; +bit32 gWait_2 = 2; + +bit32 gWaitmSec = 0; + + + +LOCAL bit32 si_V_SoftReset(agsaRoot_t *agRoot, bit32 signature); + + +LOCAL bit32 siSpcSoftResetRDYChk(agsaRoot_t *agRoot); + +#ifdef SA_ENABLE_HDA_FUNCTIONS +LOCAL void siPciMemCpy(agsaRoot_t *agRoot, bit32 dstoffset, void *src, + bit32 DWcount, bit32 busBaseNumber); + +LOCAL bit32 siBar4Cpy(agsaRoot_t *agRoot, bit32 offset, bit8 *parray, bit32 array_size); +#endif + +/******************************************************************************/ +/*! \brief Function to reset the Hardware + * + * The saHwReset() function is called to reset the SAS/SATA HW controller + * All outstanding I/Os are explicitly aborted. + * This API need to access before saInitialize() so checking saRoot is needed + * + * \param agRoot Handles for this instance of SAS/SATA hardware + * \param resetType The reset type + * \param resetParm The paramter passed for reset operation + * + * \return -void- + */ +/*******************************************************************************/ +GLOBAL void saHwReset( + agsaRoot_t *agRoot, + bit32 resetType, + bit32 resetParm + ) +{ + agsaLLRoot_t *saRoot = agNULL; + bit32 ret = AGSA_RC_SUCCESS; + bit32 value; + bit32 sysIntsActive = agFALSE; +#if defined(SALLSDK_DEBUG) + bit32 value1; + agsaControllerStatus_t controllerStatus; + agsaFatalErrorInfo_t fatal_error; +#endif + +#ifdef SOFT_RESET_TEST + DbgPrint("Reset Start\n"); +#endif + + smTraceFuncEnter(hpDBG_VERY_LOUD, "5a"); + + /* sanity check */ + SA_ASSERT( (agNULL != agRoot), ""); + if (agNULL != agRoot) + { + if (agNULL != agRoot->sdkData) + { + saRoot = (agsaLLRoot_t*) agRoot->sdkData; + sysIntsActive = saRoot->sysIntsActive; + if(sysIntsActive) + { + saSystemInterruptsActive(agRoot,agFALSE); + } + } + } + else + { + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5a"); + return; + } + + +#if defined(SALLSDK_DEBUG) + { + if (agNULL != agRoot->sdkData) + { + /* check fatal errors */ + value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1); + value1 = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2, MSGU_SCRATCH_PAD_2); + /* check AAP error */ + if( smIS_SPC(agRoot) ) + { + value &= SCRATCH_PAD_STATE_MASK; + value1 &= SCRATCH_PAD_STATE_MASK; + + if ((SCRATCH_PAD1_ERR == value) || (SCRATCH_PAD2_ERR == value1)) + { + + si_memset(&fatal_error, 0, sizeof(agsaFatalErrorInfo_t)); + /* read detail fatal errors */ + value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0, MSGU_SCRATCH_PAD_0); + fatal_error.errorInfo0 = value; + SA_DBG1(("saHwReset: ScratchPad0 AAP error code 0x%x\n", value)); + value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1); + fatal_error.errorInfo1 = value; + /* AAP error state */ + SA_DBG1(("saHwReset: AAP error state and error code 0x%x\n", value)); + value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2, MSGU_SCRATCH_PAD_2); + fatal_error.errorInfo2 = value; + /* IOP error state */ + SA_DBG1(("saHwReset: IOP error state and error code 0x%x\n", value)); + value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3, MSGU_SCRATCH_PAD_3); + SA_DBG1(("saHwReset: ScratchPad3 IOP error code 0x%x\n", value)); + fatal_error.errorInfo3 = value; + if (agNULL != saRoot) + { + fatal_error.regDumpBusBaseNum0 = saRoot->mainConfigTable.regDumpPCIBAR; + fatal_error.regDumpBusBaseNum1 = saRoot->mainConfigTable.regDumpPCIBAR; + fatal_error.regDumpLen0 = saRoot->mainConfigTable.FatalErrorDumpLength0; + fatal_error.regDumpLen1 = saRoot->mainConfigTable.FatalErrorDumpLength1; + fatal_error.regDumpOffset0 = saRoot->mainConfigTable.FatalErrorDumpOffset0; + fatal_error.regDumpOffset1 = saRoot->mainConfigTable.FatalErrorDumpOffset1; + } + + /* Call Back with error */ + SA_DBG1(("saHwReset: OSSA_HW_EVENT_MALFUNCTION SPC SP1 0x%x\n", value1)); + ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_MALFUNCTION, 0, (void *)&fatal_error, agNULL); + } + } + else + { + if( ( (value & SCRATCH_PAD1_V_BOOTLDR_ERROR) == SCRATCH_PAD1_V_BOOTLDR_ERROR)) + { + SA_DBG1(("saHwReset: ScratchPad1 SCRATCH_PAD1_V_BOOTLDR_ERROR 0x%x\n", value)); + } + if(SCRATCH_PAD1_V_ERROR_STATE(value)) + { + SA_DBG1(("saHwReset: ScratchPad1 SCRATCH_PAD1_V_ERROR_STATE 0x%x\n",SCRATCH_PAD1_V_ERROR_STATE(value) )); + } + if( (value & SCRATCH_PAD1_V_READY) == SCRATCH_PAD1_V_READY ) + { + SA_DBG1(("saHwReset: ScratchPad1 SCRATCH_PAD1_V_READY 0x%x\n", value)); + } + } + saGetControllerStatus(agRoot, &controllerStatus); + if (agNULL != saRoot) + { + /* display all pending Ios */ + siDumpActiveIORequests(agRoot, saRoot->swConfig.maxActiveIOs); + } + } + } +#endif /* SALLSDK_DEBUG */ + + /* Check the resetType */ + switch (resetType) + { + /* Reset the whole chip */ + case AGSA_CHIP_RESET: + { + /* callback with RESET_START */ + ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_START, OSSA_SUCCESS << SHIFT8, agNULL, agNULL); + + if (agNULL != agRoot->sdkData && agNULL != saRoot) + { + /* Set chip status */ + saRoot->chipStatus |= CHIP_RESETTING; + + /* Disable all interrupt */ + saSystemInterruptsActive(agRoot,agFALSE); + } + + /* do chip reset */ + siChipReset(agRoot); + + if (agNULL != saRoot) + { + /* clear up the internal resource */ + siInitResources(agRoot, + &saRoot->memoryAllocated, + &saRoot->hwConfig, + &saRoot->swConfig, + saRoot->usecsPerTick); + } + + /* callback with CHIP_RESET_COMPLETE with OSSA_SUCCESS */ + ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_COMPLETE, OSSA_SUCCESS << SHIFT8, agNULL, agNULL); + + if (agNULL != saRoot) + { + /* mask off reset FW status */ + saRoot->chipStatus &= ~CHIP_RESETTING; + } + break; + } + case AGSA_SOFT_RESET: + { + + if( smIS_SPCV(agRoot) ) + { + SA_DBG1(("saHwReset: AGSA_SOFT_RESET chip type V %d\n",smIS_SPCV(agRoot) )); + ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_START, OSSA_SUCCESS << SHIFT8, agNULL, agNULL); + if (agNULL != saRoot) + { + saRoot->ResetStartTick = saRoot->timeTick; + saCountActiveIORequests( agRoot); + } //delray end + + ret = siChipResetV( agRoot, SPC_SOFT_RESET_SIGNATURE ); + + if(agNULL !=saRoot) + { + /* clear up the internal resource */ + siInitResources(agRoot, + &saRoot->memoryAllocated, + &saRoot->hwConfig, + &saRoot->swConfig, + saRoot->usecsPerTick); + } + + if (AGSA_RC_SUCCESS == ret) + { + /* callback with CHIP_RESET_COMPLETE with OSSA_SUCCESS */ + SA_DBG1(("saHwReset: siChipResetV AGSA_RC_SUCCESS\n" )); + ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_COMPLETE, OSSA_SUCCESS << SHIFT8, agNULL, agNULL); + } + else + { + /* callback with CHIP_RESET_COMPLETE with OSSA_FAILURE */ + SA_DBG1(("saHwReset: siChipResetV not AGSA_RC_SUCCESS (0x%x)\n" ,ret)); + ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_COMPLETE, OSSA_FAILURE << SHIFT8, agNULL, agNULL); + if (agNULL != saRoot) + { + saRoot->ResetFailed = agTRUE; + SA_DBG1(("saHwReset: siChipResetV saRoot->ResetFailed ret (0x%x)\n" ,ret)); + } + + } + break; + } + else + { + if (agNULL != saRoot) + { + /* get register dump from GSM and save it to LL local memory */ + siGetRegisterDumpGSM(agRoot, (void *)&saRoot->registerDump0[0], + REG_DUMP_NUM0, 0, saRoot->mainConfigTable.FatalErrorDumpLength0); + siGetRegisterDumpGSM(agRoot, (void *)&saRoot->registerDump1[0], + REG_DUMP_NUM1, 0, saRoot->mainConfigTable.FatalErrorDumpLength1); + } + + /* callback with RESET_START */ + ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_START, OSSA_SUCCESS << SHIFT8, agNULL, agNULL); + + if (agNULL != agRoot->sdkData && agNULL != saRoot) + { + /* Set chip status */ + saRoot->chipStatus |= CHIP_RESET_FW; + + /* Disable all interrupt */ + saSystemInterruptsActive(agRoot,agFALSE); + saCountActiveIORequests( agRoot); //delray start + + } + + /* check HDA mode */ + value = ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_STATUS_BITS; + + if (value == BOOTTLOADERHDA_IDLE) + { + /* HDA mode */ + SA_DBG1(("saHwReset: HDA mode, value = 0x%x\n", value)); + ret = AGSA_RC_HDA_NO_FW_RUNNING; + } + else + { + /* do Soft Reset */ + ret = siSpcSoftReset(agRoot, SPC_SOFT_RESET_SIGNATURE); + } + if(agNULL !=saRoot) + { + /* clear up the internal resource */ + siInitResources(agRoot, + &saRoot->memoryAllocated, + &saRoot->hwConfig, + &saRoot->swConfig, + saRoot->usecsPerTick); + } + if (AGSA_RC_SUCCESS == ret) + { + /* callback with CHIP_RESET_COMPLETE with OSSA_SUCCESS */ + ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_COMPLETE, OSSA_SUCCESS << SHIFT8, agNULL, agNULL); + } + else if (AGSA_RC_HDA_NO_FW_RUNNING == ret) + { + /* callback with CHIP_RESET_COMPLETE with OSSA_CHIP_FAILED */ + ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_COMPLETE, OSSA_SUCCESS << SHIFT8, agNULL, agNULL); + } + else + { + /* callback with CHIP_RESET_COMPLETE with OSSA_FAILURE */ + ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_COMPLETE, (OSSA_FAILURE << SHIFT8), agNULL, agNULL); + } + + if (agNULL != saRoot) + { + /* mask off reset FW status */ + saRoot->chipStatus &= ~CHIP_RESET_FW; + } + break; + } + } + /* Unsupported type */ + default: + { + SA_DBG1(("saHwReset: Unsupported reset type %X\n",resetType)); + break; + } + } + + if (agNULL != saRoot) + { + if(sysIntsActive && ret == AGSA_RC_SUCCESS) + { + saSystemInterruptsActive(agRoot,agTRUE); + } + + saCountActiveIORequests( agRoot); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5a"); + } + + return; +} + +/******************************************************************************/ +/*! \brief Function to shutdown the Hardware + * + * The saHwShutdown() function is called to discontinue the use of the SAS/SATA + * hardware. Upon return, the SASA/SAT hardware instance does not generate any + * interrupts or any other bus accesses. All LL Layer hardware host resources + * (i.e. both cached and noncached memory) are no longer owned by the LL Layer. + * + * \param agRoot handles for this instance of SAS/SATA hardware + * + * \return -void- + */ +/*******************************************************************************/ +GLOBAL void saHwShutdown( + agsaRoot_t *agRoot + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + bit32 spad0 = 0; + smTraceFuncEnter(hpDBG_VERY_LOUD,"5b"); + + /* sanity check */ + SA_ASSERT( (agNULL != agRoot), ""); + SA_DBG1(("saHwShutdown: Shutting down .....\n")); + + if (agRoot->sdkData) + { + + spad0 = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); + + if(0xFFFFFFFF == spad0) + { + SA_ASSERT(0xFFFFFFFF == spad0, "saHwShutdown Chip PCI dead"); + + SA_DBG1(("saHwShutdown: Chip PCI dead SCRATCH_PAD0 0x%x\n", spad0)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5b"); + return; + } + + +#if defined(SALLSDK_DEBUG) + SA_DBG1(("saHwShutdown: SCRATCH_PAD0 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0, MSGU_SCRATCH_PAD_0))); + SA_DBG1(("saHwShutdown: SCRATCH_PAD1 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1))); + SA_DBG1(("saHwShutdown: SCRATCH_PAD2 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2, MSGU_SCRATCH_PAD_2))); + SA_DBG1(("saHwShutdown: SCRATCH_PAD3 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3, MSGU_SCRATCH_PAD_3))); + + if(1) + { + mpiOCQueue_t *circularQ; + int i; + SA_DBG4(("saHwShutdown:\n")); + for ( i = 0; i < saRoot->QueueConfig.numOutboundQueues; i++ ) + { + circularQ = &saRoot->outboundQueue[i]; + OSSA_READ_LE_32(circularQ->agRoot, &circularQ->producerIdx, circularQ->piPointer, 0); + if(circularQ->producerIdx != circularQ->consumerIdx) + { + SA_DBG1(("saHwShutdown: PI 0x%03x CI 0x%03x\n",circularQ->producerIdx, circularQ->consumerIdx )); + } + } + } +#endif /* SALLSDK_DBG */ + + if(smIS_SPCV(agRoot)) + { + + siScratchDump(agRoot); + + SA_DBG1(("saHwShutdown: SPC_V\n" )); + } + /* Set chip status */ + saRoot->chipStatus |= CHIP_SHUTDOWN; + + /* Un-Initialization Configuration Table */ + mpiUnInitConfigTable(agRoot); + if (saRoot->swConfig.hostDirectAccessSupport && !saRoot->swConfig.hostDirectAccessMode) + { + /* HDA mode - do HDAsoftReset */ + if(smIS_SPC(agRoot)) + { + /* HDA soft reset */ + siSpcSoftReset(agRoot, SPC_HDASOFT_RESET_SIGNATURE); + } + if(smIS_SPCV(agRoot)) + { + siChipResetV(agRoot, SPC_HDASOFT_RESET_SIGNATURE); + SA_DBG1(("saHwShutdown: HDA saRoot->ChipId == VEN_DEV_SPCV\n")); + } + } + else + { + /* do Normal softReset */ + if(smIS_SPC(agRoot)) + { + /* Soft Reset the SPC */ + siSpcSoftReset(agRoot, SPC_SOFT_RESET_SIGNATURE); + } + if(smIS_SPCV(agRoot)) + { + SA_DBG1(("saHwShutdown: saRoot->ChipId == VEN_DEV_SPCV\n")); + siChipResetV(agRoot, SPC_SOFT_RESET_SIGNATURE); + } + + } + + /* clean the LL resources */ + siInitResources(agRoot, + &saRoot->memoryAllocated, + &saRoot->hwConfig, + &saRoot->swConfig, + saRoot->usecsPerTick); + SA_DBG1(("saHwShutdown: Shutting down Complete\n")); + } + else + { + SA_DBG1(("saHwShutdown: No saRoot\n")); + if( smIS_SPCV(agRoot) ) + { + siChipResetV(agRoot, SPC_SOFT_RESET_SIGNATURE); + } + else + { + siSpcSoftReset(agRoot, SPC_SOFT_RESET_SIGNATURE); + } + } + /* agroot/saroot null do not access -trace OK */ + + SA_ASSERT( (agNULL != agRoot), "10"); + /* return */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5b"); + return; +} + + +/******************************************************************************/ +/*! \brief Generic Reset + * + * The siChipReset() function is called to reset the SPC chip. Upon return, + * the SPC chip got reset. The PCIe bus got reset. + * + * \param agRoot handles for this instance of SAS/SATA hardware + * + * \return -void- + */ +/*******************************************************************************/ + +GLOBAL void siChipReset( + agsaRoot_t *agRoot + ) +{ + agsaLLRoot_t *saRoot; + + /* sanity check */ + SA_ASSERT( (agNULL != agRoot), ""); + + saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + if(agNULL != saRoot) + { + smTraceFuncEnter(hpDBG_VERY_LOUD,"2C"); + + SA_DBG1(("siChipReset: saRoot->ChipId == VEN_DEV_SPCV\n")); + if(smIS_SPC(agRoot) ) + { + /* Soft Reset the SPC */ + siChipResetSpc( agRoot); + }else /* saRoot->ChipId == VEN_DEV_SPCV */ + { + siChipResetV( agRoot, SPC_SOFT_RESET_SIGNATURE); + } + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2C"); + } + +} + + +/******************************************************************************/ +/*! \brief Function to Reset the SPC V Hardware + * + * The siChipResetV() function is called to reset the SPC chip. Upon return, + * the SPC chip got reset. The PCIe bus got reset. + * + * \param agRoot handles for this instance of SAS/SATA hardware + * + * \return -void- + */ +/*******************************************************************************/ + +GLOBAL bit32 siChipResetV( + agsaRoot_t *agRoot, + bit32 signature + ) +{ + bit32 regVal; + bit32 returnVal = AGSA_RC_SUCCESS; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"3A"); + smTrace(hpDBG_LOUD,"Lr",ossaTimeStamp64(agRoot)); + regVal = ossaHwRegReadExt(agRoot,PCIBAR0 ,V_SoftResetRegister ); + + SA_DBG1(("siChipResetV: signature %X V_SoftResetRegister %X\n",signature,regVal)); + + if (signature == SPC_SOFT_RESET_SIGNATURE) + { + SA_DBG1(("siChipResetV: SPC_SOFT_RESET_SIGNATURE 0x%X\n",regVal)); + regVal = SPCv_Reset_Write_NormalReset; + } + else if (signature == SPC_HDASOFT_RESET_SIGNATURE) + { + SA_DBG1(("siChipResetV: SPCv load HDA 0x%X\n",regVal)); + regVal = SPCv_Reset_Write_SoftResetHDA; + } + else + { + SA_DBG1(("siChipResetV: Invalid SIGNATURE 0x%X regVal 0x%X a\n",signature ,regVal)); + regVal = 1; + } + + smTrace(hpDBG_LOUD,"Ls",ossaTimeStamp64(agRoot)); + ossaHwRegWriteExt(agRoot, PCIBAR0, V_SoftResetRegister, regVal); /* siChipResetV */ + smTrace(hpDBG_LOUD,"Lt",ossaTimeStamp64(agRoot)); + ossaStallThread(agRoot, (500 * 1000)); /* wait 500 milliseconds or PCIe will hang */ + /* Soft reset sequence (Normal mode) */ + smTrace(hpDBG_LOUD,"Lv",ossaTimeStamp64(agRoot)); + + if (signature == SPC_HDASOFT_RESET_SIGNATURE) + { + bit32 hda_status; + + hda_status = (ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28)); + + SA_DBG1(("siChipResetV: hda_status 0x%x\n",hda_status)); + + if((hda_status & SPC_V_HDAR_RSPCODE_MASK) != SPC_V_HDAR_IDLE) + { + SA_DBG1(("siChipResetV:SPC_HDASOFT_RESET_SIGNATURE SCRATCH_PAD1 = 0x%x \n",ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1))); + } + + SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE %X\n",regVal)); + + regVal = ossaHwRegReadExt(agRoot, PCIBAR0, V_SoftResetRegister ); /* siChipResetV */ + SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE %X\n",regVal)); + + if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_NoReset) + { + SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE AGSA_RC_FAILURE %X\n",regVal)); + returnVal = AGSA_RC_FAILURE; + } + if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_NormalResetOccurred ) + { + SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE AGSA_RC_FAILURE %X\n",regVal)); + returnVal = AGSA_RC_FAILURE; + } + if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_SoftResetHDAOccurred) + { + SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE AGSA_RC_SUCCESS %X\n",regVal)); + returnVal = AGSA_RC_SUCCESS; + } + if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_ChipResetOccurred) + { + SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE AGSA_RC_FAILURE %X\n",regVal)); + returnVal = AGSA_RC_FAILURE; + } + if(regVal == 0xFFFFFFFF) + { + SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE AGSA_RC_FAILURE %X\n",regVal)); + returnVal = AGSA_RC_FAILURE; + } + + SA_DBG1(("siChipResetV:SCRATCH_PAD1 = 0x%x a\n",ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1))); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "3A"); + return returnVal; + } + else if (signature == SPC_SOFT_RESET_SIGNATURE) + { + bit32 SCRATCH_PAD1; + bit32 max_wait_time; + bit32 max_wait_count; + smTrace(hpDBG_LOUD,"Lw",ossaTimeStamp64(agRoot)); + regVal = ossaHwRegReadExt(agRoot, PCIBAR0, V_SoftResetRegister ); /* siChipResetV */ + SA_DBG1(("siChipResetV: SPC_SOFT_RESET_SIGNATURE 0x%X\n",regVal)); + + if(regVal == 0xFFFFFFFF) + { + SA_DBG1(("siChipResetV: SPC_SOFT_RESET_SIGNATURE AGSA_RC_FAILURE %X\n",regVal)); + returnVal = AGSA_RC_FAILURE; + } + else if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_NoReset) + { + SA_DBG1(("siChipResetV:SPC_SOFT_RESET_SIGNATURE AGSA_RC_FAILURE %X\n",regVal)); + returnVal = AGSA_RC_FAILURE; + } + else if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_SoftResetHDAOccurred) + { + SA_DBG1(("siChipResetV: SPC_SOFT_RESET_SIGNATURE AGSA_RC_FAILURE 0x%X\n",regVal)); + returnVal = AGSA_RC_FAILURE; + } + else if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_ChipResetOccurred) + { + SA_DBG1(("siChipResetV: SPC_SOFT_RESET_SIGNATURE AGSA_RC_FAILURE 0x%X\n",regVal)); + returnVal = AGSA_RC_FAILURE; + } + else if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_NormalResetOccurred ) + { + SA_DBG1(("siChipResetV: SPC_SOFT_RESET_SIGNATURE AGSA_RC_SUCCESS 0x%X\n",regVal)); + returnVal = AGSA_RC_SUCCESS; + } + SA_DBG1(("siChipResetV:SCRATCH_PAD1 = 0x%x b\n",ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1))); + + if( returnVal != AGSA_RC_SUCCESS) + { + SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1) & SCRATCH_PAD1_V_BOOTSTATE_MASK; + if(SCRATCH_PAD1 == SCRATCH_PAD1_V_BOOTSTATE_HDA_SEEPROM ) + { + SA_DBG1(("siChipResetV: Reset done FW did not start BOOTSTATE_HDA_SEEPROM\n")); + return (returnVal); + } + else if(SCRATCH_PAD1 == SCRATCH_PAD1_V_BOOTSTATE_HDA_BOOTSTRAP) + { + SA_DBG1(("siChipResetV: Reset done FW did not start BOOTSTATE_HDA_BOOTSTRAP\n")); + return (returnVal); + } + else if(SCRATCH_PAD1 == SCRATCH_PAD1_V_BOOTSTATE_HDA_SOFTRESET ) + { + SA_DBG1(("siChipResetV: Reset done FW did not start BOOTSTATE_HDA_SOFTRESET\n")); + return (returnVal); + } + else if(SCRATCH_PAD1 == SCRATCH_PAD1_V_BOOTSTATE_CRIT_ERROR ) + { + SA_DBG1(("siChipResetV: Reset done FW did not start BOOTSTATE_CRIT_ERROR\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "3A"); + return (returnVal); + } + } + + /* RESET */ + smTrace(hpDBG_LOUD,"Lx",ossaTimeStamp64(agRoot)); + max_wait_time = (100 * 1000); /* wait 100 milliseconds */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); + } while ((SCRATCH_PAD1 == 0xFFFFFFFF ) && (max_wait_count -= WAIT_INCREMENT)); + + smTrace(hpDBG_LOUD,"Ly",ossaTimeStamp64(agRoot)); + SA_DBG1(("siChipResetV:SCRATCH_PAD1 = 0x%x (0x%x) PCIe ready took %d\n", SCRATCH_PAD1,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); + /* ILA */ + max_wait_time = (1000 * 1000); /* wait 1000 milliseconds */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); + } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_ILA_MASK) != SCRATCH_PAD1_V_ILA_MASK) && (max_wait_count -= WAIT_INCREMENT)); + SA_DBG1(("siChipResetV:SCRATCH_PAD1 = 0x%x SCRATCH_PAD1_V_ILA_MASK (0x%x)(0x%x) took %d\n", SCRATCH_PAD1,SCRATCH_PAD1_V_ILA_MASK,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); + + if (!max_wait_count) + { + returnVal = AGSA_RC_FAILURE; + SA_DBG1(("siChipResetV:Timeout SCRATCH_PAD1_V_ILA_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_ILA_MASK, SCRATCH_PAD1)); + } + /* RAAE */ + smTrace(hpDBG_LOUD,"Lz",ossaTimeStamp64(agRoot)); + max_wait_time = (1800 * 1000); /* wait 1800 milliseconds */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); + } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_RAAE_MASK) != SCRATCH_PAD1_V_RAAE_MASK) && (max_wait_count -= WAIT_INCREMENT)); + + SA_DBG1(("siChipResetV:SCRATCH_PAD1 = 0x%x SCRATCH_PAD1_V_RAAE_MASK (0x%x)(0x%x) took %d\n", SCRATCH_PAD1,SCRATCH_PAD1_V_RAAE_MASK,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); + + if (!max_wait_count) + { + returnVal = AGSA_RC_FAILURE; + SA_DBG1(("siChipResetV:Timeout SCRATCH_PAD1_V_RAAE_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_RAAE_MASK, SCRATCH_PAD1)); + } + /* IOP0 */ + smTrace(hpDBG_LOUD,"La",ossaTimeStamp64(agRoot)); + max_wait_time = (600 * 1000); /* wait 600 milliseconds */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); + } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_IOP0_MASK) != SCRATCH_PAD1_V_IOP0_MASK) && (max_wait_count -= WAIT_INCREMENT)); + SA_DBG1(("siChipResetV:SCRATCH_PAD1 = 0x%x SCRATCH_PAD1_V_IOP0_MASK(0x%x)(0x%x) took %d\n", SCRATCH_PAD1,SCRATCH_PAD1_V_IOP0_MASK,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); + + if (!max_wait_count) + { + returnVal = AGSA_RC_FAILURE; + SA_DBG1(("siChipResetV:Timeout SCRATCH_PAD1_V_IOP0_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_IOP0_MASK ,SCRATCH_PAD1)); + } + + if(smIS_SPCV_2_IOP(agRoot)) + { + /* IOP1 */ + smTrace(hpDBG_LOUD,"Lb",ossaTimeStamp64(agRoot)); + max_wait_time = (200 * 1000); /* wait 200 milliseconds */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); + } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_IOP1_MASK) != SCRATCH_PAD1_V_IOP1_MASK) && (max_wait_count -= WAIT_INCREMENT)); + SA_DBG1(("siChipResetV:SCRATCH_PAD1 = 0x%x SCRATCH_PAD1_V_IOP1_MASK (0x%x) (0x%x)(0x%x)\n", SCRATCH_PAD1,SCRATCH_PAD1_V_IOP1_MASK,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); + + if (!max_wait_count) + { + returnVal = AGSA_RC_FAILURE; + SA_DBG1(("siChipResetV: SCRATCH_PAD1_V_IOP1_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_IOP1_MASK, SCRATCH_PAD1)); + } + } + smTrace(hpDBG_LOUD,"Lc",ossaTimeStamp64(agRoot)); + regVal = ossaHwRegReadExt(agRoot,PCIBAR0 ,V_SoftResetRegister ); + SA_DBG1(("siChipResetV: Reset done 0x%X ERROR_STATE 0x%X\n",regVal, + SCRATCH_PAD1_V_ERROR_STATE( ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1) ) )); + if(SCRATCH_PAD1_V_ERROR_STATE( ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1)) ) + { + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "3A"); + return AGSA_RC_FAILURE; + } + + } + else /* signature = unknown */ + { + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "3A"); + return AGSA_RC_FAILURE; + } + + smTrace(hpDBG_LOUD,"Ld",ossaTimeStamp64(agRoot)); + + SA_DBG1(("siChipResetV: out V_SoftResetRegister %08X\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_SoftResetRegister) )); +#ifdef SOFT_RESET_TEST + DbgPrint("SCRATCH_PAD1 = 0x%x \n",ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1)); +#endif + smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "3A"); + return returnVal; + +} +/******************************************************************************/ +/*! \brief Function to Reset the SPC Hardware + * + * The siChipResetSpc() function is called to reset the SPC chip. Upon return, + * the SPC chip got reset. The PCIe bus got reset. + * + * \param agRoot handles for this instance of SAS/SATA hardware + * + * \return -void- + */ +/*******************************************************************************/ +GLOBAL void siChipResetSpc( + agsaRoot_t *agRoot + ) +{ + bit32 regVal; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"5c"); + + SA_DBG1(("siChipResetSpc: Chip Reset start\n")); + + /* Reset the chip */ + regVal = ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_RESET); + regVal &= ~(SPC_REG_RESET_DEVICE); + ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, regVal); /* siChipResetSpc */ + + /* delay 10 usec */ + ossaStallThread(agRoot, WAIT_INCREMENT); + + /* bring chip reset out of reset */ + regVal = ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_RESET); + regVal |= SPC_REG_RESET_DEVICE; + ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, regVal); /* siChipResetSpc */ + + /* delay 10 usec */ + ossaStallThread(agRoot, WAIT_INCREMENT); + + /* wait for 20 msec until the firmware gets reloaded */ + ossaStallThread(agRoot, (20 * 1000)); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5c"); + + SA_DBG1(("siChipResetSpc: Chip Reset Complete\n")); + + return; +} + + +GLOBAL bit32 siSoftReset( + agsaRoot_t *agRoot, + bit32 signature + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + + if(smIS_SPCV(agRoot)) + { + ret = si_V_SoftReset(agRoot, signature ); + } + else + { + ret = siSpcSoftReset(agRoot, signature ); + } + + return(ret); +} + +LOCAL bit32 si_V_SoftReset( + agsaRoot_t *agRoot, + bit32 signature + ) +{ + + bit32 ret = AGSA_RC_SUCCESS; + + ret = siChipResetV(agRoot, signature); + + if (signature == SPC_SOFT_RESET_SIGNATURE) + { + SA_DBG1(("si_V_SoftReset:SPC_SOFT_RESET_SIGNATURE\n")); + } + else if (signature == SPC_HDASOFT_RESET_SIGNATURE) + { + SA_DBG1(("si_V_SoftReset: SPC_HDASOFT_RESET_SIGNATURE\n")); + } + + SA_DBG1(("si_V_SoftReset: Reset Complete status 0x%X\n",ret)); + return ret; +} + +/******************************************************************************/ +/*! \brief Function to soft/FW reset the SPC + * + * The siSpcSoftReset() function is called to soft reset SPC. Upon return, + * the SPC FW got reset. The PCIe bus is not touched. + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param signature soft reset normal signature or HDA soft reset signature + * + * \return -void- + */ +/*******************************************************************************/ +GLOBAL bit32 siSpcSoftReset( + agsaRoot_t *agRoot, + bit32 signature + ) +{ + spc_configMainDescriptor_t mainCfg; + bit32 regVal, toggleVal; + bit32 max_wait_time; + bit32 max_wait_count; + bit32 regVal1, regVal2, regVal3; + + + /* sanity check */ + SA_ASSERT( (agNULL != agRoot), "agNULL != agRoot"); + if(agNULL != agRoot->sdkData) + { + smTraceFuncEnter(hpDBG_VERY_LOUD,"5t"); + } + + SA_DBG1(("siSpcSoftReset: start\n")); + + +#if defined(SALLSDK_DEBUG) + /* count SoftReset */ + gLLSoftResetCounter++; + SA_DBG1(("siSpcSoftReset: ResetCount = 0x%x\n", gLLSoftResetCounter)); +#endif + + /* step1: Check FW is ready for soft reset */ + + smTrace(hpDBG_VERY_LOUD,"Q1", 1); + /* TP:Q1 siSpcSoftReset */ + + if(AGSA_RC_FAILURE == siSpcSoftResetRDYChk(agRoot)) + { + SA_DBG1(("siSoftReset:siSoftResetRDYChk failed\n")); + if(agNULL != agRoot->sdkData) + { + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5t"); + } + return AGSA_RC_FAILURE; + } + + /* step 2: clear NMI status register on AAP1 and IOP, write the same value to clear */ + /* map 0x60000 to BAR4(0x20), BAR2(win) */ + smTrace(hpDBG_VERY_LOUD,"Q2", 2); + /* TP:Q2 siSpcSoftReset */ + if (AGSA_RC_FAILURE == siBar4Shift(agRoot, MBIC_AAP1_ADDR_BASE)) + { + SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", MBIC_AAP1_ADDR_BASE)); + if(agNULL != agRoot->sdkData) + { + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5t"); + } + + SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",1)); + return AGSA_RC_FAILURE; + } + regVal = ossaHwRegReadExt(agRoot, PCIBAR2, MBIC_NMI_ENABLE_VPE0_IOP); + SA_DBG1(("MBIC(A) - NMI Enable VPE0 (IOP): = 0x%x\n", regVal)); + ossaHwRegWriteExt(agRoot, PCIBAR2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0); /* siSpcSoftReset */ + + /* map 0x70000 to BAR4(0x20), BAR2(win) */ + if (AGSA_RC_FAILURE == siBar4Shift(agRoot, MBIC_IOP_ADDR_BASE)) + { + SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", MBIC_IOP_ADDR_BASE)); + if(agNULL != agRoot->sdkData) + { + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "5t"); + } + SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",2)); + return AGSA_RC_FAILURE; + } + regVal = ossaHwRegReadExt(agRoot, PCIBAR2, MBIC_NMI_ENABLE_VPE0_AAP1); + SA_DBG1(("MBIC(A) - NMI Enable VPE0 (AAP1): = 0x%x\n", regVal)); + ossaHwRegWriteExt(agRoot, PCIBAR2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0); /* siSpcSoftReset */ + + regVal = ossaHwRegReadExt(agRoot, PCIBAR1, PCIE_EVENT_INTERRUPT_ENABLE); + SA_DBG1(("PCIE - Event Interrupt Enable Register: = 0x%x\n", regVal)); + ossaHwRegWriteExt(agRoot, PCIBAR1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0); /* siSpcSoftReset */ + + regVal = ossaHwRegReadExt(agRoot, PCIBAR1, PCIE_EVENT_INTERRUPT); + SA_DBG1(("PCIE - Event Interrupt Register: = 0x%x\n", regVal)); + ossaHwRegWriteExt(agRoot, PCIBAR1, PCIE_EVENT_INTERRUPT, regVal); /* siSpcSoftReset */ + + regVal = ossaHwRegReadExt(agRoot, PCIBAR1, PCIE_ERROR_INTERRUPT_ENABLE); + SA_DBG1(("PCIE - Error Interrupt Enable Register: = 0x%x\n", regVal)); + ossaHwRegWriteExt(agRoot, PCIBAR1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0); /* siSpcSoftReset */ + + regVal = ossaHwRegReadExt(agRoot, PCIBAR1, PCIE_ERROR_INTERRUPT); + SA_DBG1(("PCIE - Error Interrupt Register: = 0x%x\n", regVal)); + ossaHwRegWriteExt(agRoot, PCIBAR1, PCIE_ERROR_INTERRUPT, regVal); /* siSpcSoftReset */ + + /* read the scratch pad 1 register bit 2 */ + regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1) & SCRATCH_PAD1_RST; + toggleVal = regVal ^ SCRATCH_PAD1_RST; + + /* set signature in host scratch pad0 register to tell SPC that the host performs the soft reset */ + ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_0, signature); + + /* read required registers for confirmming */ + /* map 0x0700000 to BAR4(0x20), BAR2(win) */ + if (AGSA_RC_FAILURE == siBar4Shift(agRoot, GSM_ADDR_BASE)) + { + SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", GSM_ADDR_BASE)); + if(agNULL != agRoot->sdkData) + { + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "5t"); + } + SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",3)); + return AGSA_RC_FAILURE; + } + + SA_DBG1(("GSM 0x0 (0x00007b88) - GSM Configuration and Reset = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_CONFIG_RESET))); + + smTrace(hpDBG_VERY_LOUD,"Q3", 3); + /* TP:Q3 siSpcSoftReset */ + + /* step 3: host read GSM Configuration and Reset register */ + regVal = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_CONFIG_RESET); + /* Put those bits to low */ + /* GSM XCBI offset = 0x70 0000 + 0x00 Bit 13 COM_SLV_SW_RSTB 1 + 0x00 Bit 12 QSSP_SW_RSTB 1 + 0x00 Bit 11 RAAE_SW_RSTB 1 + 0x00 Bit 9 RB_1_SW_RSTB 1 + 0x00 Bit 8 SM_SW_RSTB 1 + */ + regVal &= ~(0x00003b00); + /* host write GSM Configuration and Reset register */ + ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_CONFIG_RESET, regVal); /* siSpcSoftReset */ + SA_DBG1(("GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM Configuration and Reset is set to = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_CONFIG_RESET))); + +#if defined(SALLSDK_DEBUG) + /* debugging messge */ + SA_DBG1(("GSM 0x700018 - RAM ECC Double Bit Error Indication = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, RAM_ECC_DB_ERR))); + + SA_DBG1(("GSM 0x700058 - Read Address Parity Error Indication = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_INDIC))); + SA_DBG1(("GSM 0x700060 - Write Address Parity Error Indication = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_INDIC))); + SA_DBG1(("GSM 0x700068 - Write Data Parity Error Indication = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_INDIC))); +#endif + + /* step 4: */ + /* disable GSM - Read Address Parity Check */ + smTrace(hpDBG_VERY_LOUD,"Q4", 4); + /* TP:Q4 siSpcSoftReset */ + regVal1 = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_CHECK); + SA_DBG1(("GSM 0x700038 - Read Address Parity Check Enable = 0x%x\n", regVal1)); + ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_CHECK, 0x0); /* siSpcSoftReset */ + SA_DBG1(("GSM 0x700038 - Read Address Parity Check Enable is set to = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_CHECK))); + + /* disable GSM - Write Address Parity Check */ + regVal2 = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_CHECK); + SA_DBG1(("GSM 0x700040 - Write Address Parity Check Enable = 0x%x\n", regVal2)); + ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0); /* siSpcSoftReset */ + SA_DBG1(("GSM 0x700040 - Write Address Parity Check Enable is set to = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_CHECK))); + + /* disable GSM - Write Data Parity Check */ + regVal3 = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_CHECK); + SA_DBG1(("GSM 0x300048 - Write Data Parity Check Enable = 0x%x\n", regVal3)); + ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_CHECK, 0x0); /* siSpcSoftReset */ + SA_DBG1(("GSM 0x700048 - Write Data Parity Check Enable is set to = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_CHECK))); + /* step 5-a: delay 10 usec */ + smTrace(hpDBG_VERY_LOUD,"Q5", 5); + /* TP:Q5 siSpcSoftReset */ + ossaStallThread(agRoot, 10); + + /* step 5-b: set GPIO-0 output control to tristate anyway */ + if (AGSA_RC_FAILURE == siBar4Shift(agRoot, GPIO_ADDR_BASE)) + { + SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", GPIO_ADDR_BASE)); + if(agNULL != agRoot->sdkData) + { + smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "5t"); + } + SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",4)); + return AGSA_RC_FAILURE; + } + regVal = ossaHwRegReadExt(agRoot, PCIBAR2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET); + SA_DBG1(("GPIO Output Control Register: = 0x%x\n", regVal)); + /* set GPIO-0 output control to tri-state */ + regVal &= 0xFFFFFFFC; + ossaHwRegWriteExt(agRoot, PCIBAR2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal); /* siSpcSoftReset */ + + /* Step 6: Reset the IOP and AAP1 */ + /* map 0x00000 to BAR4(0x20), BAR2(win) */ + smTrace(hpDBG_VERY_LOUD,"Q6", 6); + /* TP:Q6 siSpcSoftReset */ + if (AGSA_RC_FAILURE == siBar4Shift(agRoot, SPC_TOP_LEVEL_ADDR_BASE)) + { + SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", SPC_TOP_LEVEL_ADDR_BASE)); + if(agNULL != agRoot->sdkData) + { + smTraceFuncExit(hpDBG_VERY_LOUD, 'f', "5t"); + } + SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",5)); + return AGSA_RC_FAILURE; + } + regVal = ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_RESET); + SA_DBG1(("Top Register before resetting IOP/AAP1: = 0x%x\n", regVal)); + regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS); + ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, regVal); /* siSpcSoftReset */ + + /* step 7: Reset the BDMA/OSSP */ + smTrace(hpDBG_VERY_LOUD,"Q7", 7); + /* TP:Q7 siSpcSoftReset */ + regVal = ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_RESET); + SA_DBG1(("Top Register before resetting BDMA/OSSP: = 0x%x\n", regVal)); + regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP); + ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, regVal); /* siSpcSoftReset */ + + /* step 8: delay 10 usec */ + smTrace(hpDBG_VERY_LOUD,"Q8", 8); + /* TP:Q8 siSpcSoftReset */ + + ossaStallThread(agRoot, WAIT_INCREMENT); + + /* step 9: bring the BDMA and OSSP out of reset */ + smTrace(hpDBG_VERY_LOUD,"Q9", 9); + /* TP:Q9 siSpcSoftReset */ + regVal = ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_RESET); + SA_DBG1(("Top Register before bringing up BDMA/OSSP: = 0x%x\n", regVal)); + regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP); + ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, regVal); /* siSpcSoftReset */ + + /* step 10: delay 10 usec */ + smTrace(hpDBG_VERY_LOUD,"QA", 10); + /* TP:QA siSpcSoftReset */ + ossaStallThread(agRoot, WAIT_INCREMENT); + + /* step 11: reads and sets the GSM Configuration and Reset Register */ + /* map 0x0700000 to BAR4(0x20), BAR2(win) */ + smTrace(hpDBG_VERY_LOUD,"QB", 11); + /* TP:QB siSpcSoftReset */ + if (AGSA_RC_FAILURE == siBar4Shift(agRoot, GSM_ADDR_BASE)) + { + SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", GSM_ADDR_BASE)); + if(agNULL != agRoot->sdkData) + { + smTraceFuncExit(hpDBG_VERY_LOUD, 'g', "5t"); + } + SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",5)); + return AGSA_RC_FAILURE; + } + SA_DBG1(("GSM 0x0 (0x00007b88) - GSM Configuration and Reset = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_CONFIG_RESET))); + regVal = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_CONFIG_RESET); + /* Put those bits to high */ + /* GSM XCBI offset = 0x70 0000 + 0x00 Bit 13 COM_SLV_SW_RSTB 1 + 0x00 Bit 12 QSSP_SW_RSTB 1 + 0x00 Bit 11 RAAE_SW_RSTB 1 + 0x00 Bit 9 RB_1_SW_RSTB 1 + 0x00 Bit 8 SM_SW_RSTB 1 + */ + regVal |= (GSM_CONFIG_RESET_VALUE); + ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_CONFIG_RESET, regVal); /* siSpcSoftReset */ + SA_DBG1(("GSM 0x0 (0x00004088 ==> 0x00007b88) - GSM Configuration and Reset is set to = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_CONFIG_RESET))); + +#if defined(SALLSDK_DEBUG) + /* debugging messge */ + SA_DBG1(("GSM 0x700018 - RAM ECC Double Bit Error Indication = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, RAM_ECC_DB_ERR))); + SA_DBG1(("GSM 0x700058 - Read Address Parity Error Indication = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_INDIC))); + SA_DBG1(("GSM 0x700060 - Write Address Parity Error Indication = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_INDIC))); + SA_DBG1(("GSM 0x700068 - Write Data Parity Error Indication = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_INDIC))); +#endif + + /* step 12: Restore GSM - Read Address Parity Check */ + smTrace(hpDBG_VERY_LOUD,"QC", 12); + /* TP:QC siSpcSoftReset */ + regVal = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_CHECK); /* just for debugging */ + SA_DBG1(("GSM 0x700038 - Read Address Parity Check Enable = 0x%x\n", regVal)); + ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_CHECK, regVal1); /* siSpcSoftReset */ + SA_DBG1(("GSM 0x700038 - Read Address Parity Check Enable is set to = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_CHECK))); + + /* Restore GSM - Write Address Parity Check */ + regVal = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_CHECK); /* just for debugging */ + SA_DBG1(("GSM 0x700040 - Write Address Parity Check Enable = 0x%x\n", regVal)); + ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2); /* siSpcSoftReset */ + SA_DBG1(("GSM 0x700040 - Write Address Parity Check Enable is set to = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_CHECK))); + + /* Restore GSM - Write Data Parity Check */ + regVal = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_CHECK); /* just for debugging */ + SA_DBG1(("GSM 0x700048 - Write Data Parity Check Enable = 0x%x\n", regVal)); + ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_CHECK, regVal3); /* siSpcSoftReset */ + SA_DBG1(("GSM 0x700048 - Write Data Parity Check Enable is set to = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_CHECK))); + + /* step 13: bring the IOP and AAP1 out of reset */ + /* map 0x00000 to BAR4(0x20), BAR2(win) */ + smTrace(hpDBG_VERY_LOUD,"QD", 13); + /* TP:QD siSpcSoftReset */ + if (AGSA_RC_FAILURE == siBar4Shift(agRoot, SPC_TOP_LEVEL_ADDR_BASE)) + { + SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", SPC_TOP_LEVEL_ADDR_BASE)); + if(agNULL != agRoot->sdkData) + { + smTraceFuncExit(hpDBG_VERY_LOUD, 'h', "5t"); + } + SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",7)); + return AGSA_RC_FAILURE; + } + regVal = ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_RESET); + SA_DBG1(("Top Register before bringing up IOP/AAP1: = 0x%x\n", regVal)); + regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS); + ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, regVal); /* siSpcSoftReset */ + + if (signature == SPC_SOFT_RESET_SIGNATURE) + { + /* step 14: delay 20 milli - Normal Mode */ + ossaStallThread(agRoot, WAIT_INCREMENT); + }else if (signature == SPC_HDASOFT_RESET_SIGNATURE) + { + /* step 14: delay 200 milli - HDA Mode */ + ossaStallThread(agRoot, 200 * 1000); + } + + /* check Soft Reset Normal mode or Soft Reset HDA mode */ + if (signature == SPC_SOFT_RESET_SIGNATURE) + { + /* step 15 (Normal Mode): wait until scratch pad1 register bit 2 toggled */ + max_wait_time = WAIT_SECONDS(2); /* 2 sec */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1) & SCRATCH_PAD1_RST; + } while ((regVal != toggleVal) && (max_wait_count -=WAIT_INCREMENT)); + + if ( !max_wait_count) + { + regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1); + SA_DBG1(("siSpcSoftReset: TIMEOUT:ToggleVal 0x%x, MSGU_SCRATCH_PAD1 = 0x%x\n", toggleVal, regVal)); + if(agNULL != agRoot->sdkData) + { + smTraceFuncExit(hpDBG_VERY_LOUD, 'i', "5t"); + } +#if defined(SALLSDK_DEBUG) + SA_DBG1(("siSpcSoftReset: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0))); + SA_DBG1(("siSpcSoftReset: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2))); + SA_DBG1(("siSpcSoftReset: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3))); +#endif + SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",8)); + return AGSA_RC_FAILURE; + } + + /* step 16 (Normal)step 15 (HDA) - Clear ODMR and ODCR */ + smTrace(hpDBG_VERY_LOUD,"QG", 16); + /* TP:QG siSpcSoftReset */ + + ossaHwRegWrite(agRoot, MSGU_ODCR, ODCR_CLEAR_ALL); + ossaHwRegWrite(agRoot, MSGU_ODMR, ODMR_CLEAR_ALL); + } + else if (signature == SPC_HDASOFT_RESET_SIGNATURE) + { + if(agNULL != agRoot->sdkData) + { + SA_DBG1(("siSpcSoftReset: HDA Soft Reset Complete\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'j', "5t"); + } + return AGSA_RC_SUCCESS; + } + + + /* step 17 (Normal Mode): wait for the FW and IOP to get ready - 1 sec timeout */ + /* Wait for the SPC Configuration Table to be ready */ + if (mpiWaitForConfigTable(agRoot, &mainCfg) == AGSA_RC_FAILURE) + { + regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1); + /* return error if MPI Configuration Table not ready */ + SA_DBG1(("siSpcSoftReset: SPC FW not ready SCRATCH_PAD1 = 0x%x\n", regVal)); + regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2); + /* return error if MPI Configuration Table not ready */ + SA_DBG1(("siSpcSoftReset: SPC FW not ready SCRATCH_PAD2 = 0x%x\n", regVal)); + if(agNULL != agRoot->sdkData) + { + smTraceFuncExit(hpDBG_VERY_LOUD, 'k', "5t"); + } +#if defined(SALLSDK_DEBUG) + SA_DBG1(("siSpcSoftReset: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0))); + SA_DBG1(("siSpcSoftReset: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3))); +#endif + SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",9)); + return AGSA_RC_FAILURE; + } + smTrace(hpDBG_VERY_LOUD,"QI", 18); + /* TP:QI siSpcSoftReset */ + + if(agNULL != agRoot->sdkData) + { + smTraceFuncExit(hpDBG_VERY_LOUD, 'l', "5t"); + } + + SA_DBG1(("siSpcSoftReset: Soft Reset Complete\n")); + + return AGSA_RC_SUCCESS; +} + +/******************************************************************************/ +/*! \brief Function to do BAR shifting + * + * The siBarShift() function is called to shift BAR base address + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param shiftValue shifting value + * + * \return success or fail + */ +/*******************************************************************************/ +GLOBAL bit32 siBar4Shift( + agsaRoot_t *agRoot, + bit32 shiftValue + ) +{ + bit32 regVal; + bit32 max_wait_time; + bit32 max_wait_count; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"5e"); + smTrace(hpDBG_VERY_LOUD,"GA",shiftValue); + /* TP:GA shiftValue */ + + SA_DBG2(("siBar4Shift: shiftValue 0x%x\n",shiftValue)); + + if(smIS_SPCV(agRoot) ) + { + ossaHwRegWriteExt(agRoot, PCIBAR0, V_MEMBASE_II_ShiftRegister, shiftValue); + /* confirm the setting is written */ + max_wait_time = WAIT_SECONDS(1); /* 1 sec */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + regVal = ossaHwRegReadExt(agRoot, PCIBAR0, V_MEMBASE_II_ShiftRegister); + } while ((regVal != shiftValue) && (max_wait_count -= WAIT_INCREMENT)); + + if (!max_wait_count) + { + SA_DBG1(("siBar4Shift: TIMEOUT: SPC_IBW_AXI_TRANSLATION_LOW = 0x%x\n", regVal)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5e"); + return AGSA_RC_FAILURE; + } + } + else if(smIS_SPC(agRoot)) + { + /* program the inbound AXI translation Lower Address */ + ossaHwRegWriteExt(agRoot, PCIBAR1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue); + + /* confirm the setting is written */ + max_wait_time = WAIT_SECONDS(1); /* 1 sec */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + regVal = ossaHwRegReadExt(agRoot, PCIBAR1, SPC_IBW_AXI_TRANSLATION_LOW); + } while ((regVal != shiftValue) && (max_wait_count -= WAIT_INCREMENT)); + + if (!max_wait_count) + { + SA_DBG1(("siBar4Shift: TIMEOUT: SPC_IBW_AXI_TRANSLATION_LOW = 0x%x\n", regVal)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5e"); + return AGSA_RC_FAILURE; + } + } + else + { + SA_DBG1(("siBar4Shift: hba type is not support\n")); + return AGSA_RC_FAILURE; + } + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "5e"); + + return AGSA_RC_SUCCESS; +} + +#ifdef SA_ENABLE_HDA_FUNCTIONS +/******************************************************************************/ +/*! \brief Function to force HDA mode the SPC + * + * The siHDAMode() function is called to force to HDA mode. Upon return, + * the SPC FW loaded. The PCIe bus is not touched. + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param HDAMode 0 - HDA soft reset mode, 1 - HDA mode + * \param fwImg points to structure containing fw images + * + * \return -void- + */ +/*******************************************************************************/ +GLOBAL bit32 siHDAMode( + agsaRoot_t *agRoot, + bit32 HDAMode, + agsaFwImg_t *userFwImg + ) +{ + spc_configMainDescriptor_t mainCfg; + bit32 regVal; + bit32 max_wait_time; + bit32 max_wait_count; + agsaFwImg_t flashImg; + bit32 startTime, endTime; // TestBase + bit32 stepTime[12]; // TestBase + + bit32 HDA_Been_Reset = agFALSE; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"5d"); + + /* sanity check */ + SA_ASSERT( (agNULL != agRoot), ""); + + SA_DBG1(("siHDAMode: start\n")); + + si_memset(&flashImg, 0, sizeof(flashImg)); +#ifndef SA_EXCLUDE_FW_IMG + + /* Set up built-in (default) FW image pointers */ +/* + flashImg.aap1Img = (bit8*)(&aap1array); + flashImg.aap1Len = sizeof(aap1array); + flashImg.ilaImg = (bit8*)(&ilaarray); + flashImg.ilaLen = sizeof(ilaarray); + flashImg.iopImg = (bit8*)(&ioparray); + flashImg.iopLen = sizeof(ioparray); +*/ +#endif + TryAfterReset: + + /* Set up user FW image pointers (if passed in) */ + if (userFwImg) + { + SA_DBG1(("siHDAMode: User fw structure @ %p\n",userFwImg)); + if (userFwImg->aap1Img && userFwImg->aap1Len) + { + flashImg.aap1Img = userFwImg->aap1Img; + flashImg.aap1Len = userFwImg->aap1Len; + SA_DBG1(("siHDAMode: User fw aap1 @ %p (%d)\n", flashImg.aap1Img, flashImg.aap1Len)); + } + if (userFwImg->ilaImg && userFwImg->ilaLen) + { + flashImg.ilaImg = userFwImg->ilaImg; + flashImg.ilaLen = userFwImg->ilaLen; + SA_DBG1(("siHDAMode: User fw ila @ %p (%d)\n", flashImg.ilaImg, flashImg.ilaLen)); + } + if (userFwImg->iopImg && userFwImg->iopLen) + { + flashImg.iopImg = userFwImg->iopImg; + flashImg.iopLen = userFwImg->iopLen; + SA_DBG1(("siHDAMode: User fw iop @ %p (%d)\n", flashImg.iopImg, flashImg.iopLen)); + } + if (userFwImg->istrImg && userFwImg->istrLen) + { + flashImg.istrImg = userFwImg->istrImg; + flashImg.istrLen = userFwImg->istrLen; + SA_DBG1(("siHDAMode: User fw istr @ %p (%d)\n", flashImg.istrImg, flashImg.istrLen)); + } + } + else + { + SA_DBG1(("siHDAMode: user supplied FW is not found\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5d"); + return AGSA_RC_FAILURE; + } + +#ifdef SA_EXCLUDE_FW_IMG + /* Check that fw images are setup properly */ + if (!(flashImg.aap1Img && flashImg.aap1Len && + flashImg.ilaImg && flashImg.ilaLen && + flashImg.iopImg && flashImg.iopLen && + flashImg.istrImg && flashImg.istrLen)) + { + SA_DBG1(("siHDAMode: Built-in FW img excluded and not user defined.\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5d"); + return AGSA_RC_FAILURE; + } +#endif + + /* Check HDA mode with Soft Reset */ + if (!HDAMode) + { + /* Try soft reset until it goes into HDA mode */ + siSpcSoftReset(agRoot, SPC_HDASOFT_RESET_SIGNATURE); + + /* read response state */ + regVal = ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_STATUS_BITS; + if (regVal != BOOTTLOADERHDA_IDLE) + { + /* Can not go into HDA mode with 200 ms wait - HDA Soft Reset failed */ + SA_DBG1(("siHDAMode: HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET = 0x%x\n", regVal)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "5d"); + return AGSA_RC_FAILURE; + } + + /* HDA Mode - Clear ODMR and ODCR */ + ossaHwRegWrite(agRoot, MSGU_ODCR, ODCR_CLEAR_ALL); + ossaHwRegWrite(agRoot, MSGU_ODMR, ODMR_CLEAR_ALL); + } + + /* Step 1: Poll BOOTTLOADERHDA_IDLE - HDA mode */ + SA_DBG1(("siHDAMode: Step1:Poll for HDAR_IDLE\n")); + max_wait_time = WAIT_SECONDS(gWait_2); /* 2 sec */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + regVal = ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_STATUS_BITS; + } while ((regVal != BOOTTLOADERHDA_IDLE) && (max_wait_count -= WAIT_INCREMENT)); + + if (!max_wait_count) + { + + if( !HDA_Been_Reset ) + { + + SA_DBG1(("siHDAMode: Reset: Step1:regVal =0x%x expect 0x%x\n", regVal,ILAHDA_AAP1_IMG_GET )); + siSpcSoftReset(agRoot, SPC_HDASOFT_RESET_SIGNATURE); + HDA_Been_Reset = agTRUE; + goto TryAfterReset; + + } + + SA_DBG1(("siHDAMode: Step1:TIMEOUT: HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET = 0x%x\n", regVal)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "5d"); + return AGSA_RC_FAILURE; + } + + /* Step 2: Push the init string to 0x0047E000 & data compare */ + SA_DBG1(("siHDAMode: Step2:Push the init string to 0x0047E000!\n")); + + if (AGSA_RC_FAILURE == siBar4Cpy(agRoot, ILA_ISTR_ADDROFFSETHDA, flashImg.istrImg, flashImg.istrLen)) + { + SA_DBG1(("siHDAMode: Step2:Copy ISTR array to 0x%x failed\n", ILA_ISTR_ADDROFFSETHDA)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "5d"); + return AGSA_RC_FAILURE; + } + + /* Tell FW ISTR is ready */ + regVal = (HDA_ISTR_DONE | (bit32)flashImg.istrLen); + ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_3, regVal); + SA_DBG1(("siHDAMode: Step2:Host Scratchpad 3 (AAP1-ISTR): 0x%x\n", regVal)); + + stepTime[2] = ossaTimeStamp(agRoot); // TestBase + SA_DBG1(("siHDAMode: End Step2: (step_time[2] = %d)\n", stepTime[2])); // TestBase + + /* Step 3: Write the HDA mode SoftReset signature */ + SA_DBG1(("siHDAMode: Step3:Set Signature!\n")); + /* set signature in host scratch pad0 register to tell SPC that the host performs the HDA mode */ + ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_0, SPC_HDASOFT_RESET_SIGNATURE); + + stepTime[3] = ossaTimeStamp(agRoot); // TestBase + SA_DBG1(("siHDAMode: End Step3: (step_time[3] = %d)\n", stepTime[3])); // TestBase + + // Priya (Apps) requested that the FW load time measurement be started here + startTime = ossaTimeStamp(agRoot); + SA_DBG1(("siHDAMode: Step4: Ready to push ILA to 0x00400000! (start_time = %d)\n", startTime)); // TestBase + + /* Step 4: Push the ILA image to 0x00400000 */ + SA_DBG1(("siHDAMode: Step4:Push the ILA to 0x00400000!\n")); + + if (AGSA_RC_FAILURE == siBar4Cpy(agRoot, 0x0, flashImg.ilaImg, flashImg.ilaLen)) + { + SA_DBG1(("siHDAMode:Step4:Copy ILA array to 0x%x failed\n", 0x0)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'f', "5d"); + return AGSA_RC_FAILURE; + } + + stepTime[4] = ossaTimeStamp(agRoot); + SA_DBG1(("siHDAMode: End Step4: (step_time[4] = %d, %d ms)\n", stepTime[4], (stepTime[4] - startTime))); // TestBase + + /* Step 5: Tell boot ROM to authenticate ILA and execute it */ + ossaHwRegWriteExt(agRoot, PCIBAR3, HDA_CMD_OFFSET1MB, 0); + ossaHwRegWriteExt(agRoot, PCIBAR3, HDA_CMD_OFFSET1MB+HDA_PAR_LEN_OFFSET, flashImg.ilaLen); + regVal = (ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_SEQ_ID_BITS ) >> SHIFT16; + regVal ++; + regVal = (HDA_C_PA << SHIFT24) | (regVal << SHIFT16) | HDAC_EXEC_CMD; + SA_DBG1(("siHDAMode: Step5:Execute ILA CMD: 0x%x\n", regVal)); + ossaHwRegWriteExt(agRoot, PCIBAR3, HDA_CMD_OFFSET1MB+HDA_CMD_CODE_OFFSET, regVal); /* Execute Command */ + + stepTime[5] = ossaTimeStamp(agRoot); + SA_DBG1(("siHDAMode: End Step5: (step_time[5] = %d, %d ms)\n", stepTime[5], (stepTime[5] - startTime))); // TestBase + + + /* Step 6: Checking response status from boot ROM, HDAR_EXEC (good), HDAR_BAD_CMD and HDAR_BAD_IMG */ + SA_DBG1(("siHDAMode: Step6:Checking boot ROM reponse status!\n")); + max_wait_time = WAIT_SECONDS(gWait_2); /* 2 sec */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + regVal = ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_STATUS_BITS; + if ((HDAR_EXEC == regVal) || (HDAR_BAD_IMG == regVal) || (HDAR_BAD_CMD == regVal)) + break; + } while (max_wait_count-=WAIT_INCREMENT); + + if (HDAR_BAD_IMG == regVal) + { + SA_DBG1(("siHDAMode: Step6:BAD IMG: HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET = 0x%x\n", regVal)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'g', "5d"); + return AGSA_RC_FAILURE; + } + if (HDAR_BAD_CMD == regVal) + { + SA_DBG1(("siHDAMode: Step6:BAD IMG: HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET = 0x%x\n", regVal)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'h', "5d"); + return AGSA_RC_FAILURE; + } + if (!max_wait_count) + { + SA_DBG1(("siHDAMode: Step6:TIMEOUT: HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET = 0x%x\n", regVal)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'i', "5d"); + return AGSA_RC_FAILURE; + } + + stepTime[6] = ossaTimeStamp(agRoot); + SA_DBG1(("siHDAMode: End Step6: (step_time[6] = %d, %d ms)\n", stepTime[6], (stepTime[6] - startTime))); // TestBase + + /* Step 7: Poll ILAHDA_AAP1IMGGET/Offset in MSGU Scratchpad 0 */ + /* Check MSGU Scratchpad 1 [1,0] == 00 */ + SA_DBG1(("siHDAMode: Step7:Poll ILAHDA_AAP1_IMG_GET!\n")); + regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1) & SCRATCH_PAD1_RST; + SA_DBG1(("siHDAMode: Step7:MSG Scratchpad 1: 0x%x\n", regVal)); + max_wait_time = WAIT_SECONDS(gWait_3); /* 3 sec */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0) >> SHIFT24; + } while ((regVal != ILAHDA_AAP1_IMG_GET) && (max_wait_count -= WAIT_INCREMENT)); + + if (!max_wait_count) + { + + if( !HDA_Been_Reset ) + { + + SA_DBG1(("siHDAMode: Reset: Step7:regVal =0x%x expect 0x%x\n", regVal,ILAHDA_AAP1_IMG_GET )); + siSpcSoftReset(agRoot, SPC_HDASOFT_RESET_SIGNATURE); + HDA_Been_Reset = agTRUE; + goto TryAfterReset; + + } + + SA_DBG1(("siHDAMode: TIMEOUT: Step7:regVal =0x%x expect 0x%x\n", regVal,ILAHDA_AAP1_IMG_GET )); +#if defined(SALLSDK_DEBUG) + SA_DBG1(("siHDAMode: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0))); + SA_DBG1(("siHDAMode: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1))); + SA_DBG1(("siHDAMode: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2))); + SA_DBG1(("siHDAMode: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3))); +#endif + smTraceFuncExit(hpDBG_VERY_LOUD, 'j', "5d"); + return AGSA_RC_FAILURE; + } + regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0); + SA_DBG1(("siHDAMode: Step7:MSG Scratchpad 0: 0x%x\n", regVal)); + regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0) & 0x00FFFFFF; + + stepTime[7] = ossaTimeStamp(agRoot); + SA_DBG1(("siHDAMode: End Step7: (step_time[7] = %d, %d ms)\n", stepTime[7], (stepTime[7] - startTime))); // TestBase + + /* Step 8: Copy AAP1 image, update the Host Scratchpad 3 */ + SA_DBG1(("siHDAMode: Step8:Push the AAP1 to 0x00400000 plus 0x%x\n", regVal)); + + if (AGSA_RC_FAILURE == siBar4Cpy(agRoot, regVal, flashImg.aap1Img, flashImg.aap1Len)) + { + SA_DBG1(("siHDAMode: Step8:Copy AAP1 array to 0x%x failed\n", regVal)); +#if defined(SALLSDK_DEBUG) + SA_DBG1(("siHDAMode: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0))); + SA_DBG1(("siHDAMode: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1))); + SA_DBG1(("siHDAMode: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2))); + SA_DBG1(("siHDAMode: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3))); +#endif + smTraceFuncExit(hpDBG_VERY_LOUD, 'k', "5d"); + return AGSA_RC_FAILURE; + } + + regVal = (HDA_AAP1_DONE | (bit32)flashImg.aap1Len); + ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_3, regVal); + SA_DBG1(("siHDAMode: Step8:Host Scratchpad 3 (AAP1): 0x%x\n", regVal)); + + stepTime[8] = ossaTimeStamp(agRoot); + SA_DBG1(("siHDAMode: End Step8: (step_time[8] = %d, %d ms)\n", stepTime[8], (stepTime[8] - startTime))); // TestBase + + /* Step 9: Poll ILAHDA_IOPIMGGET/Offset in MSGU Scratchpad 0 */ + SA_DBG1(("siHDAMode: Step9:Poll ILAHDA_IOP_IMG_GET!\n")); + max_wait_time = WAIT_SECONDS(gWait_2); /* 2 sec */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0) >> SHIFT24; + } while ((regVal != ILAHDA_IOP_IMG_GET) && (max_wait_count -= WAIT_INCREMENT)); + + if (!max_wait_count) + { + SA_DBG1(("siHDAMode: Step9:TIMEOUT:MSGU_SCRATCH_PAD_0 = 0x%x\n", regVal)); +#if defined(SALLSDK_DEBUG) + SA_DBG1(("siHDAMode: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1))); + SA_DBG1(("siHDAMode: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2))); + SA_DBG1(("siHDAMode: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3))); +#endif + smTraceFuncExit(hpDBG_VERY_LOUD, 'l', "5d"); + return AGSA_RC_FAILURE; + } + regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0); + SA_DBG1(("siHDAMode: Step9:MSG Scratchpad 0: 0x%x\n", regVal)); + regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0) & HDA_GSM_OFFSET_BITS; + + stepTime[9] = ossaTimeStamp(agRoot); + SA_DBG1(("siHDAMode: End Step9: (step_time[9] = %d, %d ms)\n", stepTime[9], (stepTime[9] - startTime))); // TestBase + + // saHdaLoadForceHalt(agRoot); // TestBase + + /* Step 10: Copy IOP image, update the Host Scratchpad 3 */ + SA_DBG1(("siHDAMode: Step10:Push the IOP to 0x00400000 plus 0x%x!\n", regVal)); + + if (AGSA_RC_FAILURE == siBar4Cpy(agRoot, regVal, flashImg.iopImg, flashImg.iopLen)) + { + SA_DBG1(("siHDAMode: Step10:Copy IOP array to 0x%x failed\n", regVal)); +#if defined(SALLSDK_DEBUG) + SA_DBG1(("siHDAMode: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1))); + SA_DBG1(("siHDAMode: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2))); + SA_DBG1(("siHDAMode: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3))); +#endif + smTraceFuncExit(hpDBG_VERY_LOUD, 'm', "5d"); + return AGSA_RC_FAILURE; + } + + regVal = (HDA_IOP_DONE | (bit32)flashImg.iopLen); + ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_3, regVal); + SA_DBG1(("siHDAMode: Step10:Host Scratchpad 3 (IOP): 0x%x\n", regVal)); + + stepTime[10] = ossaTimeStamp(agRoot); + SA_DBG1(("siHDAMode: End Step10: (step_time[10] = %d, %d ms)\n", stepTime[10], (stepTime[10] - startTime))); // TestBase + + /* Clear the signature */ + ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_0, 0); + + /* step 11: wait for the FW and IOP to get ready - 1 sec timeout */ + /* Wait for the SPC Configuration Table to be ready */ + stepTime[11] = ossaTimeStamp(agRoot); + SA_DBG1(("siHDAMode: Start Step11: Wait for FW ready. (step_time[11.1] = %d, %d ms)\n", stepTime[11], (stepTime[11] - startTime))); // TestBase + + endTime = ossaTimeStamp(agRoot); + SA_DBG1(("siHDAMode: End Step11: FW ready! (end_time= %d, fw_load_time = %d ms)\n", endTime, endTime - startTime)); // TestBase + + SA_DBG1(("siHDAMode: Step11:Poll for FW ready!\n")); + if (mpiWaitForConfigTable(agRoot, &mainCfg) == AGSA_RC_FAILURE) + { + regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1); + /* return error if MPI Configuration Table not ready */ + SA_DBG1(("siHDAMode: Step11:SPC FW not ready SCRATCH_PAD1 = 0x%x\n", regVal)); + regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2); + /* return error if MPI Configuration Table not ready */ + SA_DBG1(("siHDAMode: Step11:SPC FW not ready SCRATCH_PAD2 = 0x%x\n", regVal)); + /* read detail fatal errors */ + regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0); + SA_DBG1(("siHDAMode: Step11:ScratchPad0 AAP error code 0x%x\n", regVal)); + regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3); + SA_DBG1(("siHDAMode: Step11:ScratchPad3 IOP error code 0x%x\n", regVal)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'n', "5d"); + return AGSA_RC_FAILURE; + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'o', "5d"); + + SA_DBG1(("siHDAMode: HDA Mode Complete\n")); + + return AGSA_RC_SUCCESS; +} + +/******************************************************************************/ +/*! \brief memcopy cross PCI from host memory to card memory + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param dstoffset distination offset + * \param src source pointer + * \param DWcount DWord count + * \param busBaseNumber PCI Bus Base number + * + * \return -void- + * + */ +/*******************************************************************************/ +LOCAL void siPciMemCpy(agsaRoot_t *agRoot, + bit32 dstoffset, + void *src, + bit32 DWcount, + bit32 busBaseNumber + ) +{ + bit32 i, val; + bit32 *src1; + + src1 = (bit32 *)src; + + for (i= 0; i < DWcount; i++) + { + val = BIT32_TO_LEBIT32(src1[i]); + ossaHwRegWriteExt(agRoot, busBaseNumber, (dstoffset + i * 4), val); + } + + return; +} + +/******************************************************************************/ +/*! \brief Function to copy FW array + * + * The siBar4Cpy() function is called to copy FW array via BAR4 + * (PCIe spec: BAR4, MEMBASE-III in PM, PCIBAR2 in host driver) + * in 64-KB MEMBASE MODE. + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param offset destination offset + * \param parray pointer of array + * \param array_size size of array + * + * \return AGSA_RC_SUCCESS or AGSA_RC_FAILURE + */ +/*******************************************************************************/ +LOCAL bit32 siBar4Cpy( + agsaRoot_t *agRoot, + bit32 offset, + bit8 * parray, + bit32 array_size + ) +{ + bit32 dest_shift_addr, dest_offset, cpy_size; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"5f"); + + /* first time to shift */ + dest_shift_addr = (GSMSM_AXI_LOWERADDR+offset) & SHIFT_MASK; + dest_offset = offset & OFFSET_MASK; + do + { + if (AGSA_RC_FAILURE == siBar4Shift(agRoot, dest_shift_addr)) + { + SA_DBG1(("siHDAMode:Shift Bar4 to 0x%x failed\n", dest_shift_addr)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5f"); + return AGSA_RC_FAILURE; + } + + if ((dest_offset+array_size) > SIZE_64KB) + { + cpy_size = SIZE_64KB - dest_offset; + } + else + cpy_size = array_size; + + siPciMemCpy(agRoot, dest_offset, parray, (bit32)(CEILING(cpy_size,4)), PCIBAR2); + + array_size -= cpy_size; + dest_shift_addr += SIZE_64KB; + dest_offset = 0; + parray = parray + cpy_size; + } while (array_size !=0 ); + + /* Shift back to BAR4 original address */ + if (AGSA_RC_FAILURE == siBar4Shift(agRoot, 0x0)) + { + SA_DBG1(("siHDAMode:Shift Bar4 to 0x%x failed\n", 0x0)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5f"); + return AGSA_RC_FAILURE; + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "5f"); + + return AGSA_RC_SUCCESS; +} + +GLOBAL +bit32 siHDAMode_V( + agsaRoot_t *agRoot, + bit32 HDAMode, + agsaFwImg_t *userFwImg + ) +{ + bit32 returnVal = AGSA_RC_FAILURE; + bit32 save,i,biggest; + bit32 hda_status; + bit32 hda_command_complete = 0; + bit32 max_wait_time; + bit32 max_wait_count; + bit32 seq_id = 0; + bit32 base_Hi = 0; + bit32 base_Lo = 0; + bit8 * pbase; + + spcv_hda_cmd_t hdacmd; + spcv_hda_rsp_t hdarsp; + + agsaLLRoot_t *saRoot; + + /* sanity check */ + SA_ASSERT( (agNULL != agRoot), ""); + + saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + + /* sanity check */ + SA_ASSERT( (agNULL != saRoot), "saRoot is NULL"); + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2W"); + + SA_DBG1(("siHDAMode_V: HDAMode %X\n",HDAMode)); + + siScratchDump(agRoot); + if( agNULL == userFwImg) + { + SA_DBG1(("siHDAMode_V: No image agNULL == userFwImg\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2W"); + return returnVal; + } + + hda_status = (ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28)); + + SA_DBG1(("siHDAMode_V: hda_status 0x%08X\n",hda_status )); + SA_DBG1(("siHDAMode_V: STEP 1\n")); + + smTrace(hpDBG_VERY_LOUD,"2X",1 ); + /* TP:2X STEP 1 */ + + /* Find largest Physical chunk memory */ + for(i=0,biggest = 0,save = 0; i < saRoot->memoryAllocated.count; i++) + { + if( saRoot->memoryAllocated.agMemory[i].totalLength > biggest) + { + + if(biggest < saRoot->memoryAllocated.agMemory[i].totalLength) + { + save = i; + biggest = saRoot->memoryAllocated.agMemory[i].totalLength; + } + + } + } +/* +Step 1 The host reads the HDA response field RSP_CODE at byte offset 28:29 of the response block +for HDAR_IDLE (0x8002) via MEMBASE-I. A value other than HDAR_IDLE (0x8002) indicates that the +SPCv controller is not in HDA mode. Follow the steps described in Section 4.21.1 to bring the +SPCv controller into HDA mode. When the host reads the correct RSP_CODE, it indicates that the +SPCv controller boot ROM is ready to proceed to the next step of HDA initialization +*/ + + base_Hi = saRoot->memoryAllocated.agMemory[save].phyAddrUpper; + base_Lo = saRoot->memoryAllocated.agMemory[save].phyAddrLower; + pbase = saRoot->memoryAllocated.agMemory[save].virtPtr; + SA_DBG1(("siHDAMode_V:Use DMA memory at [%d] size 0x%x (%d) DMA Loc U 0x%08x L 0x%08x @%p\n",save, + biggest, + biggest, + base_Hi, + base_Lo, + pbase + )); + + + SA_DBG1(("siHDAMode_V: HDA aap1Img %p len %8d 0x%x\n", userFwImg->aap1Img, userFwImg->aap1Len , userFwImg->aap1Len )); + SA_DBG1(("siHDAMode_V: HDA ilaImg %p len %8d 0x%x\n", userFwImg->ilaImg, userFwImg->ilaLen , userFwImg->ilaLen )); + SA_DBG1(("siHDAMode_V: HDA iopImg %p len %8d 0x%x\n", userFwImg->iopImg, userFwImg->iopLen , userFwImg->iopLen )); + if(userFwImg->aap1Len > biggest) + { + SA_DBG1(("siHDAMode_V: HDA DMA area too small %d < %d aap1Len\n", biggest ,userFwImg->aap1Len)); + SA_ASSERT( (agNULL != agRoot), "aap1Len > biggest"); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2W"); + return returnVal; + } + if(userFwImg->ilaLen > biggest) + { + SA_DBG1(("siHDAMode_V: HDA DMA area too small %d < %d ilaLen\n", biggest ,userFwImg->ilaLen)); + SA_ASSERT( (agNULL != agRoot), "ilaLen > biggest"); + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "2W"); + return returnVal; + } + if(userFwImg->iopLen > biggest) + { + SA_DBG1(("siHDAMode_V: HDA DMA area too small %d < %d iopLen\n", biggest ,userFwImg->iopLen)); + SA_ASSERT( (agNULL != agRoot), "iopLen > biggest"); + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "2W"); + return returnVal; + } + + + if(HDA_STEP_2) + { /* ILA */ + si_memset(pbase, 0, biggest); + + if( userFwImg->ilaLen < biggest) + { + si_memcpy(pbase,userFwImg->ilaImg, userFwImg->ilaLen ); + } + else + { + SA_DBG1(("siHDAMode_V: userFwImg->ilaLen 0x%x < biggest 0x%x\n",userFwImg->ilaLen,biggest)); + } + + si_memset(&hdacmd,0,sizeof(spcv_hda_cmd_t)); + si_memset(&hdarsp,0,sizeof(spcv_hda_rsp_t)); + + hda_status = ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28); + if((hda_status & SPC_V_HDAR_RSPCODE_MASK) == SPC_V_HDAR_IDLE) + { + + hdacmd.cmdparm_0 = base_Lo; /* source DmaBase_l*/ + hdacmd.cmdparm_1 = base_Hi; /* source DmaBase_u*/ + hdacmd.cmdparm_2 = 0x1e200000; /* destin */ + hdacmd.cmdparm_3 = 0; /* destin */ + hdacmd.cmdparm_4 = userFwImg->ilaLen ; /* length */ + hdacmd.cmdparm_5 = 0;/* not used */ + hdacmd.cmdparm_6 = 0;/* not used */ + seq_id++; + hdacmd.C_PA_SEQ_ID_CMD_CODE = ( SPC_V_HDAC_PA << SHIFT24 ) | ( seq_id << SHIFT16 )| SPC_V_HDAC_DMA; + + SA_DBG1(("siHDAMode_V: Write SPC_V_HDAC_DMA STEP 2\n")); + /* + Step 2 + The host writes the HDAC_DMA (0x000 24) in the command field CMD_CODE via MEMBASE-I + for issuing the DMA command to ask the boot ROM to pull the ILA image via DMA into + GSM with the following parameters set up first: + Parameter 1:0: Host physical address for holding the HDA-ILA image. + Parameter 3:2: GSM physical address 0x1E20_0000. + Parameter 4: the length of the HDAILA image. + */ + + SA_DBG2(("siHDAMode_V: Write ILA to offset %X\n",hdacmd.cmdparm_2)); + + ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+0,hdacmd.cmdparm_0); + ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+4,hdacmd.cmdparm_1); + ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+8,hdacmd.cmdparm_2); + ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+12,hdacmd.cmdparm_3); + ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+16,hdacmd.cmdparm_4); + ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+20,hdacmd.cmdparm_5); + ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+24,hdacmd.cmdparm_6); + ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+28,hdacmd.C_PA_SEQ_ID_CMD_CODE); + + SA_DBG2(("siHDAMode_V: Command 0 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+0), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+4), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+8), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+12), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+16), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+20), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+24), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+28) )); + + SA_DBG2(("siHDAMode_V: command %X\n",hdacmd.C_PA_SEQ_ID_CMD_CODE )); + + max_wait_time = (2000 * 1000); /* wait 2 seconds */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; + hda_command_complete = 0; + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) & SPC_V_HDAR_SEQID_MASK ) >> SHIFT16) == seq_id; + } while (!hda_command_complete && (max_wait_count -= WAIT_INCREMENT)); + SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x STEP 2 took %d\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); + + smTrace(hpDBG_VERY_LOUD,"2Y",(max_wait_time - max_wait_count) ); + /* TP:2Y STEP 2 took */ + + + if(! hda_command_complete) + { + SA_DBG1(("siHDAMode_V:2SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register))); + SA_DBG1(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register))); + SA_DBG1(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register))); + SA_DBG1(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register))); + SA_DBG1(("siHDAMode_V:hda_command_complete failed Step 2\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "2W"); + return returnVal; + } + + + SA_DBG2(("siHDAMode_V:2SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register))); + SA_DBG2(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register))); + SA_DBG2(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register))); + SA_DBG2(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register))); + + } + + SA_DBG1(("siHDAMode_V: ILA DMA done\n" )); + } /* end ila */ + + if(HDA_STEP_3) + { + + SA_DBG1(("siHDAMode_V: STEP 3\n")); + /* + Step 3 + The host polls the HDA response field RSP_CODE for HDAR_IDLE (0x8002) via MEMBASE-I. The polling timeout + should be no more than 1 second. The response status, HDAR_IDLE with its status equal to 0x10, + indicates a DMA success response from the boot ROM. Response states that indicate a failure are: + HDAR_BAD_CMD HDAR_BAD_IMG HDAR_IDLE with its status equal to 0x11 + + */ + + max_wait_time = (2000 * 1000); /* wait 2 seconds */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; + hda_command_complete = 0; + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) & SPC_V_HDAR_SEQID_MASK ) >> SHIFT16) == seq_id; + } while (!hda_command_complete && (max_wait_count -= WAIT_INCREMENT)); + + SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x STEP 3 took %d\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); + smTrace(hpDBG_VERY_LOUD,"2Z",(max_wait_time - max_wait_count) ); + /* TP:2Z STEP 3 took */ + + if(! hda_command_complete) + { + + SA_DBG1(("siHDAMode_V: Response 0 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+0), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+4), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+8), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+12), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+16), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+20), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+24), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) )); + + + SA_DBG1(("siHDAMode_V:3SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register))); + SA_DBG1(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register))); + SA_DBG1(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register))); + SA_DBG1(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register))); + SA_DBG1(("siHDAMode_V:hda_command_complete failed Step 3\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'f', "2W"); + return returnVal; + } + + + hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) & SPC_V_HDAR_SEQID_MASK ) >> SHIFT16) == seq_id; + hda_status = (ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) & SPC_V_HDAR_RSPCODE_MASK ); + + SA_DBG2(("siHDAMode_V:ILA is ready hda_status %X hda_command_complete %d\n",hda_status ,hda_command_complete)); + + /* Tell FW ILA is ready */ + SA_DBG2(("siHDAMode_V: Response 0 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+0), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+4), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+8), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+12), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+16), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+20), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+24), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) )); + + SA_DBG2(("siHDAMode_V:3SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register))); + SA_DBG2(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register))); + SA_DBG2(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register))); + SA_DBG2(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register))); + + SA_DBG2(("siHDAMode_V: Step 3 MSGU_HOST_SCRATCH_PAD_3 write %X\n",HDA_ISTR_DONE)); + ossaHwRegWriteExt(agRoot, PCIBAR0,MSGU_HOST_SCRATCH_PAD_3 ,HDA_ISTR_DONE ); + + SA_DBG2(("siHDAMode_V:3SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register))); + SA_DBG2(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register))); + SA_DBG2(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register))); + SA_DBG2(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register))); + + } + + if(HDA_STEP_4) + { + + SA_DBG2(("siHDAMode_V: Exec ILA\n")); + si_memset(&hdacmd,0,sizeof(spcv_hda_cmd_t)); + si_memset(&hdarsp,0,sizeof(spcv_hda_rsp_t)); + + hdacmd.cmdparm_0 = 0x200000; /* length SPC_V_HDAC_EXEC*/; + hdacmd.cmdparm_1 = userFwImg->ilaLen ; /* length SPC_V_HDAC_EXEC*/; + seq_id++; + + hdacmd.C_PA_SEQ_ID_CMD_CODE = ( SPC_V_HDAC_PA << SHIFT24 ) | ( seq_id << SHIFT16 )| SPC_V_HDAC_EXEC; + + SA_DBG1(("siHDAMode_V: STEP 4\n")); + + /* + Step 4 + The host writes the HDAC_EXEC command (0x0002) via MEMBASE-I for the boot ROM to authenticate + and execute the HDA-ILA image. The host sets parameter 0 and parameter 1 for the HDA-ILA image + appropriately: + Parameter 0: Entry offset this value must be 0x20_0000. + Parameter 1: the HDA-ILA image length. + */ + + ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+0 ,hdacmd.cmdparm_0); + ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+4 ,hdacmd.cmdparm_1); + ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+8 ,hdacmd.cmdparm_2); + ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+12,hdacmd.cmdparm_3); + ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+16,hdacmd.cmdparm_4); + ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+20,hdacmd.cmdparm_5); + ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+24,hdacmd.cmdparm_6); + ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+28,hdacmd.C_PA_SEQ_ID_CMD_CODE); + + SA_DBG1(("siHDAMode_V: Exec ILA\n" )); + + SA_DBG2(("siHDAMode_V: Command 0 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+0), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+4), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+8), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+12), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+16), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+20), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+24), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+28) )); + + SA_DBG2(("siHDAMode_V: command %X\n",hdacmd.C_PA_SEQ_ID_CMD_CODE )); + + SA_DBG2(("siHDAMode_V:4SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register))); + SA_DBG2(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register))); + SA_DBG2(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register))); + SA_DBG2(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register))); + } // End Step 4 + if(HDA_STEP_5) + { + SA_DBG1(("siHDAMode_V: start wait STEP 5\n")); + + /* + Step 5 + The host continues polling for the HDA-ILA status via MEMBASE-I. The polling timeout should + be no more than 1 second. The response status HDAR_EXEC indicates a good response from the + boot ROM. Response states that indicate a failure are: + HDAR_BAD_CMD + HDAR_BAD_IMG + */ + + max_wait_time = (2000 * 1000); /* wait 2 seconds */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; + hda_command_complete = 0; + hda_status = (ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) & SPC_V_HDAR_RSPCODE_MASK ); + SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x hda_status 0x%x Begin STEP 5\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),hda_status)); + hda_status = 0; + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + hda_status = (ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) & SPC_V_HDAR_RSPCODE_MASK ); + hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) & SPC_V_HDAR_SEQID_MASK ) >> SHIFT16) == seq_id; + } while (hda_status != SPC_V_HDAR_EXEC && (max_wait_count -= WAIT_INCREMENT)); + + SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x hda_status 0x%x hda_command_complete 0x%x STEP 5 wait for seq_id took %d\n", + ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1), + hda_status, + hda_command_complete, + (max_wait_time - max_wait_count))); + + smTrace(hpDBG_VERY_LOUD,"2Z",(max_wait_time - max_wait_count) ); + /* TP:2Z STEP 5 took */ + + if(! hda_command_complete) + { + SA_DBG1(("siHDAMode_V: Response 0 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+0), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+4), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+8), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+12), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+16), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+20), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+24), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) )); + + SA_DBG1(("siHDAMode_V:5SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register))); + SA_DBG1(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register))); + SA_DBG1(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register))); + SA_DBG1(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register))); + SA_DBG1(("siHDAMode_V:hda_command_complete failed Step 5\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'g', "2W"); + return returnVal; + } + + if (hda_status != SPC_V_HDAR_EXEC) + { + SA_DBG1(("siHDAMode_V:ILA_EXEC_ERROR hda_status %X hda_command_complete %d\n",hda_status ,hda_command_complete)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'h', "2W"); + goto bootrom_err; + } + SA_DBG1(("siHDAMode_V: end seq_id updated STEP 5\n")); + } // End Step 5 + + if(HDA_STEP_6) + { + SA_DBG1(("siHDAMode_V: start STEP 6\n")); + + /* + Step 6 + The host polls the upper 8 bits [31:24] 5 of the Scratchpad 0 Register + (page 609) for the ILAHDA_RAAE_IMG_GET (0x11) state. Polling timeout + should be no more than 2 seconds. If a polling timeout occurs, the host + should check for a fatal error as described in Section 12.2. + If successful, the Host Scratchpad 4 Register (page 620) and Host + Scratchpad 5 Register (page 621) are set as follows: Host Scratchpad 4 + Register (page 620) holds the lower 32-bit host address of + the RAAE image. Host Scratchpad 5 Register (page 621) + holds the upper 32-bit host address of the RAAE image. + Then the host writes the command ILAHDAC_RAAE_IMG_DONE(0x81) to the upper + 8 bits [31:24] of the Host Scratchpad 3 Register (page 619) and writes the + sizeof the RAAE image to the lower 24 bits [23:0]. + */ + + max_wait_time = (2000 * 1000); /* wait 2 seconds */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; + hda_command_complete = 0; + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register) & 0xff000000 ) >> SHIFT24 ) == ILAHDA_RAAE_IMG_GET; + } while (!hda_command_complete && (max_wait_count -= WAIT_INCREMENT)); + + SA_DBG1(("siHDAMode_V:SCRATCH_PAD0 = 0x%x STEP 6 wait for ILAHDA_RAAE_IMG_GET took %d\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register),(max_wait_time - max_wait_count))); + smTrace(hpDBG_VERY_LOUD,"2b",(max_wait_time - max_wait_count) ); + /* TP:2b STEP 6 took */ + if(! hda_command_complete) + { + SA_DBG1(("siHDAMode_V:hda_command_complete failed Step 6\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'i', "2W"); + goto fw_err; + } + + si_memset(pbase, 0, biggest); + + if( userFwImg->aap1Len < biggest) + { + si_memcpy(pbase,userFwImg->aap1Img, userFwImg->aap1Len ); + } + else + { + SA_DBG1(("siHDAMode_V: userFwImg->aap1Len 0x%x < biggest 0x%x\n",userFwImg->aap1Len,biggest)); + } + /* + */ + /* upper */ + ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_5, base_Hi ); + SA_DBG3(("siHDAMode_V: MSGU_HOST_SCRATCH_PAD_5 0x%X\n", base_Hi)); + /* lower */ + ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_4, base_Lo ); + SA_DBG3(("siHDAMode_V: MSGU_HOST_SCRATCH_PAD_4 0x%X\n",base_Lo)); + /* len */ + ossaHwRegWriteExt(agRoot, PCIBAR0,MSGU_HOST_SCRATCH_PAD_3 ,(ILAHDAC_RAAE_IMG_DONE << SHIFT24) | userFwImg->aap1Len ); + SA_DBG1(("siHDAMode_V: write ILAHDAC_RAAE_IMG_DONE to MSGU_HOST_SCRATCH_PAD_3 0x%X\n",(ILAHDAC_RAAE_IMG_DONE << SHIFT24) | userFwImg->aap1Len)); + // ossaHwRegWriteExt(agRoot, PCIBAR0,MSGU_HOST_SCRATCH_PAD_4 , userFwImg->DmaBase_l); + + ossaStallThread(agRoot, gWaitmSec * 1000); + if(1) /* step in question */ + { + max_wait_time = (2000 * 1000); /* wait 2 seconds */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; + hda_command_complete = 0; + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register) & 0xff000000 ) >> SHIFT24 ) == ILAHDA_IOP_IMG_GET; + } while (!hda_command_complete && (max_wait_count -= WAIT_INCREMENT)); + + SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x STEP 7 wait for ILAHDA_IOP_IMG_GET took %d\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); + smTrace(hpDBG_VERY_LOUD,"2c",(max_wait_time - max_wait_count) ); + /* TP:2c STEP 6a ILAHDA_IOP_IMG_GET took */ + smTrace(hpDBG_VERY_LOUD,"2y",hda_command_complete ); + /* TP:2y hda_command_complete */ + + if(! hda_command_complete) + { + SA_DBG1(("siHDAMode_V:hda_command_complete failed Step 7\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'j', "2W"); + goto fw_err; + } + } + SA_DBG1(("siHDAMode_V: End V_Scratchpad_0_Register 0x%08X STEP 6\n",ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register))); + } + + if(HDA_STEP_7) + { + SA_DBG1(("siHDAMode_V: STEP 7\n")); + /* + Step 7 + The host polls (reads) the upper 8 bits 7 [31:24] of the Scratchpad 0 Register (page 609) + for ILAHDA_IOP_IMG_GET (0x10) state. The polling timeout should be no more than 2 seconds. + If a polling timeout occurs, the host should check for a fatal error as described in + Section 12.2. If successful, the Host Scratchpad 4 Register (page 620) and Host + Scratchpad 5 Register (page 621) are set as follows: + Host Scratchpad 4 Register (page 620) holds the lower host address of the IOP image. + Host Scratchpad 5 Register (page 621) holds the upper host address of the IOP image. + Then host writes the command ILAHDAC_IOP_IMG_DONE(0x80) to the upper 8 bits [31:24] of the + Host Scratchpad 3 Register (page 614)and writes the sizeof the IOP image to the lower 24 + bits [23:0]. + + */ + + si_memset(pbase, 0, biggest); + + if( userFwImg->iopLen < biggest) + { + si_memcpy(pbase,userFwImg->iopImg, userFwImg->iopLen ); + } + else + { + SA_DBG1(("siHDAMode_V: userFwImg->iopImg 0x%x < biggest 0x%x\n",userFwImg->iopLen,biggest)); + } + + /* upper */ + ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_5, base_Hi ); + SA_DBG3(("siHDAMode_V: MSGU_HOST_SCRATCH_PAD_5 0x%X\n", base_Hi)); + /* lower */ + ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_4, base_Lo ); + SA_DBG3(("siHDAMode_V: MSGU_HOST_SCRATCH_PAD_4 0x%X\n",base_Lo)); + SA_DBG2(("siHDAMode_V: MSGU_HOST_SCRATCH_PAD_4\n")); + /* len */ + ossaHwRegWriteExt(agRoot, PCIBAR0,MSGU_HOST_SCRATCH_PAD_3 ,(ILAHDAC_IOP_IMG_DONE << SHIFT24) | userFwImg->iopLen ); + SA_DBG2(("siHDAMode_V: MSGU_HOST_SCRATCH_PAD_3 0x%X\n",(ILAHDAC_IOP_IMG_DONE << SHIFT24) | userFwImg->iopLen)); + + + if(saRoot->swConfig.hostDirectAccessMode & 2 ) + { + /* Hda AES DIF offload */ + ossaHwRegWrite(agRoot, V_Scratchpad_Rsvd_0_Register, HDA_AES_DIF_FUNC); + SA_DBG1(("siHDAMode_V: V_Scratchpad_Rsvd_0_Register, HDA_AES_DIF_FUNC 0x%X\n",HDA_AES_DIF_FUNC)); + /* Hda AES DIF offload */ + } + + SA_DBG2(("siHDAMode_V: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register))); + SA_DBG2(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register))); + + + max_wait_time = (2000 * 1000); /* wait 2 seconds */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; + hda_command_complete = 0; + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register) & 0xff000000 ) >> SHIFT24 ) == ILAHDA_IOP_IMG_GET; + } while (!hda_command_complete && (max_wait_count -= WAIT_INCREMENT)); + + smTrace(hpDBG_VERY_LOUD,"2d",(max_wait_time - max_wait_count) ); + /* TP:2d STEP 7 ILAHDA_IOP_IMG_GET took */ + smTrace(hpDBG_VERY_LOUD,"2z",hda_command_complete ); + /* TP:2z hda_command_complete */ + + SA_DBG2(("siHDAMode_V:SCRATCH_PAD0 = 0x%x STEP 7 wait for ILAHDA_IOP_IMG_GET took %d\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register),(max_wait_time - max_wait_count))); + + if(! hda_command_complete) + { + SA_DBG1(("siHDAMode_V:7SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register))); + SA_DBG1(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register))); + SA_DBG1(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register))); + SA_DBG1(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register))); + SA_DBG1(("siHDAMode_V:hda_command_complete failed Step 7\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'k', "2W"); + return returnVal; + } + + + SA_DBG2(("siHDAMode_V:7SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register))); + SA_DBG2(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register))); + SA_DBG2(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register))); + SA_DBG2(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register))); + SA_DBG1(("siHDAMode_V: End STEP 7\n")); + } + + + if(HDA_STEP_8) + { + bit32 SCRATCH_PAD1; + + SA_DBG1(("siHDAMode_V: Check fw ready Step 8\n")); + + /* + Step 8 + IOP0/1 start-up sequence. The host polls the Scratchpad 1 Register (page 610) + bits [1:0] for RAAE_STATE, bits [13:12] for IOP1_STATE, and + bits [11:10] for IOP0_STATE to go to 11b (Ready state). + The polling timeout should be no more than 1 second. If a polling timeout occurs, + the host should check for a fatal error in Section 12.2. + */ + + returnVal = AGSA_RC_SUCCESS; + + max_wait_time = (1000 * 1000); /* wait 1000 milliseconds */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); + } while ((SCRATCH_PAD1 == 0xFFFFFFFF ) && (max_wait_count -= WAIT_INCREMENT)); + smTrace(hpDBG_VERY_LOUD,"HZ",(max_wait_time - max_wait_count) ); + /* TP:2f Step 8 PCI took */ + + SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x (0x%x) Step 8 PCIe took %d\n", SCRATCH_PAD1,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); + /* ILA */ + max_wait_time = (1000 * 1000); /* wait 1000 milliseconds */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); + } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_ILA_MASK) != SCRATCH_PAD1_V_ILA_MASK) && (max_wait_count -= WAIT_INCREMENT)); + + smTrace(hpDBG_VERY_LOUD,"2g",(max_wait_time - max_wait_count) ); + /* TP:2g Step 8 ILA took */ + + SA_DBG2(("siHDAMode_V:SCRATCH_PAD1 = 0x%x SCRATCH_PAD1_V_ILA_MASK (0x%x)(0x%x) took %d\n", SCRATCH_PAD1,SCRATCH_PAD1_V_ILA_MASK,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); + + if (!max_wait_count) + { + // Ignore for now returnVal = AGSA_RC_FAILURE; + SA_DBG1(("siHDAMode_V:Timeout SCRATCH_PAD1_V_ILA_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_ILA_MASK, SCRATCH_PAD1)); + } + + SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x SCRATCH_PAD1_V_ILA_MASK (0x%x)(0x%x) took %d\n", SCRATCH_PAD1,SCRATCH_PAD1_V_ILA_MASK,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); + + /* RAAE */ + max_wait_time = (1800 * 1000); /* wait 1800 milliseconds */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); + } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_RAAE_MASK) != SCRATCH_PAD1_V_RAAE_MASK) && (max_wait_count -= WAIT_INCREMENT)); + + SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x SCRATCH_PAD1_V_RAAE_MASK (0x%x)(0x%x) took %d\n", SCRATCH_PAD1,SCRATCH_PAD1_V_RAAE_MASK,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); + smTrace(hpDBG_VERY_LOUD,"2h",(max_wait_time - max_wait_count) ); + /* TP:2h Step 8 RAAE took */ + + if (!max_wait_count) + { + SA_DBG1(("siHDAMode_V:Timeout SCRATCH_PAD1_V_RAAE_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_RAAE_MASK, SCRATCH_PAD1)); + + } + /* IOP0 */ + max_wait_time = (600 * 1000); /* wait 600 milliseconds */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); + } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_IOP0_MASK) != SCRATCH_PAD1_V_IOP0_MASK) && (max_wait_count -= WAIT_INCREMENT)); + + SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x SCRATCH_PAD1_V_IOP0_MASK(0x%x)(0x%x) took %d\n", SCRATCH_PAD1,SCRATCH_PAD1_V_IOP0_MASK,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); + smTrace(hpDBG_VERY_LOUD,"2i",(max_wait_time - max_wait_count) ); + /* TP:2i Step 8 IOP took */ + + if (!max_wait_count) + { + returnVal = AGSA_RC_FAILURE; + SA_DBG1(("siHDAMode_V:Timeout SCRATCH_PAD1_V_IOP0_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_IOP0_MASK ,SCRATCH_PAD1)); + + } + + + SA_DBG1(("siHDAMode_V: Step 8 0x%X ERROR_STATE 0x%X\n",ossaHwRegReadExt(agRoot,PCIBAR0 ,V_SoftResetRegister ), + SCRATCH_PAD1_V_ERROR_STATE( ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1) ) )); + if (SCRATCH_PAD1_V_ERROR_STATE( ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1) )) + { + if(smIS_ENCRYPT(agRoot)) + { + SA_DBG1(("siHDAMode_V: Encryption and HDA mode not supported - failed Step 8\n" )); + } + else + { + SA_DBG1(("siHDAMode_V: ERROR_STATE failed Step 8\n" )); + } + returnVal = AGSA_RC_FAILURE; + smTraceFuncExit(hpDBG_VERY_LOUD, 'l', "2W"); + goto fw_err; + } + + } + SA_DBG1(("siHDAMode_V: returnVal 0x%X Step 8\n",returnVal)); +/* +Step 10 +The host continues with the normal SPCv Configuration Table initialization sequence +as described in Section 6.2.8.1. +*/ + if(saRoot->swConfig.hostDirectAccessMode & 2 ) + { + /* Hda AES DIF offload */ + SA_DBG1(("siHDAMode_V: AES/DIF 0x%08X offload enabled %s\n",ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3 ), + ((ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3 ) & (1 << SHIFT15)) ? "yes" :"no") )); + /* Hda AES DIF offload */ + /* ossaHwRegWrite(agRoot, V_Scratchpad_Rsvd_0_Register, 0); */ + /* Hda AES DIF offload */ + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'm', "2W"); + return returnVal; + +bootrom_err: + SA_DBG2(("siHDAMode_V: Response 0 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+0), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+4), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+8), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+12), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+16), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+20), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+24), + ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) )); + +fw_err: + SA_DBG2(("siHDAMode_V: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register))); + SA_DBG2(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register))); + SA_DBG2(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register))); + SA_DBG2(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register))); + return returnVal; +} + +#endif /* SA_ENABLE_HDA_FUNCTIONS */ + + + + +/******************************************************************************/ +/*! \brief Function to check FW is ready for soft reset + * + * The siSpcSoftResetRDYChk() function is called to check status of FW + * + * \param agRoot handles for this instance of SAS/SATA hardware + * + * \return success or fail + */ +/*******************************************************************************/ +LOCAL bit32 siSpcSoftResetRDYChk(agsaRoot_t *agRoot) +{ + bit32 regVal; + bit32 Scratchpad1; + bit32 Scratchpad2; + bit32 spad2notready = 0; +#if defined(SALLSDK_DEBUG) + bit32 regVal1; + bit32 regVal2; +#endif /* SALLSDK_DEBUG */ + + /* read the scratch pad 2 register bit 2 */ + regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2) & SCRATCH_PAD2_FWRDY_RST; + Scratchpad1 = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1); + if (regVal == SCRATCH_PAD2_FWRDY_RST) + { + /* FW assert happened, it is ready for soft reset */ + /* Do nothing */ + } + else + { + /* read bootloader response state */ + regVal = ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_STATUS_BITS; + if (regVal == BOOTTLOADERHDA_IDLE) + { + /* For customers wants to do soft reset even the chip is already in HDA mode */ + /* Do not need to trigger RB6 twice */ + ; + } + else + { + /* Trigger NMI twice via RB6 */ + if (AGSA_RC_FAILURE == siBar4Shift(agRoot, RB6_ACCESS_REG)) + { + SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", RB6_ACCESS_REG)); + return AGSA_RC_FAILURE; + } + + if(Scratchpad1 != (SCRATCH_PAD1_FW_INIT_ERR | SCRATCH_PAD1_AAP_ERROR_STATE)) + { + ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_RB6_OFFSET , RB6_MAGIC_NUMBER_RST); + + ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_RB6_OFFSET , RB6_MAGIC_NUMBER_RST); + } + else + { + SA_DBG1(("siSoftReset: ILA load fail SKIP RB6 access 0x%x\n",Scratchpad1 )); + } + SPAD2_NOT_READY: + /* wait for 100 ms */ + ossaStallThread(agRoot, ONE_HUNDRED_MILLISECS ); + Scratchpad2 = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2); + regVal = Scratchpad2 & SCRATCH_PAD2_FWRDY_RST; + if (regVal != SCRATCH_PAD2_FWRDY_RST) + { + if (spad2notready > WAIT_SECONDS(12) / ONE_HUNDRED_MILLISECS ) /**/ + { +#if defined(SALLSDK_DEBUG) + regVal1 = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1); + regVal2 = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2); + SA_DBG1(("siSpcSoftResetRDYChk: TIMEOUT:MSGU_SCRATCH_PAD1=0x%x, MSGU_SCRATCH_PAD2=0x%x\n", regVal1, regVal2)); + SA_DBG1(("siSpcSoftResetRDYChk: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0))); + SA_DBG1(("siSpcSoftResetRDYChk: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3))); +#endif /* SALLSDK_DEBUG */ + return AGSA_RC_SUCCESS; /* Timeout Ok reset anyway */ + } + + spad2notready++; + goto SPAD2_NOT_READY; + } + } + } + + return AGSA_RC_SUCCESS; +} + + +agsaBarOffset_t SPCTable[] = +{ + + { GEN_MSGU_IBDB_SET, PCIBAR0, MSGU_IBDB_SET, SIZE_DW }, /* 0x00 */ + { GEN_MSGU_ODR, PCIBAR0, MSGU_ODR, SIZE_DW }, /* 0x01 */ + { GEN_MSGU_ODCR, PCIBAR0, MSGU_ODCR, SIZE_DW }, /* 0x02 */ + { GEN_MSGU_SCRATCH_PAD_0, PCIBAR0, MSGU_SCRATCH_PAD_0, SIZE_DW }, /* 0x03 */ + { GEN_MSGU_SCRATCH_PAD_1, PCIBAR0, MSGU_SCRATCH_PAD_1, SIZE_DW }, /* 0x04 */ + { GEN_MSGU_SCRATCH_PAD_2, PCIBAR0, MSGU_SCRATCH_PAD_2, SIZE_DW }, /* 0x05 */ + { GEN_MSGU_SCRATCH_PAD_3, PCIBAR0, MSGU_SCRATCH_PAD_3, SIZE_DW }, /* 0x06 */ + { GEN_MSGU_HOST_SCRATCH_PAD_0, PCIBAR0, MSGU_HOST_SCRATCH_PAD_0, SIZE_DW }, /* 0x07 */ + { GEN_MSGU_HOST_SCRATCH_PAD_1, PCIBAR0, MSGU_HOST_SCRATCH_PAD_1, SIZE_DW }, /* 0x08 */ + { GEN_MSGU_HOST_SCRATCH_PAD_2, PCIBAR0, MSGU_HOST_SCRATCH_PAD_2, SIZE_DW }, /* 0x09 */ + { GEN_MSGU_HOST_SCRATCH_PAD_3, PCIBAR0, MSGU_HOST_SCRATCH_PAD_3, SIZE_DW }, /* 0x0a */ + { GEN_MSGU_ODMR, PCIBAR0, MSGU_ODMR, SIZE_DW }, /* 0x0b */ + { GEN_PCIE_TRIGGER, PCIBAR0, PCIE_TRIGGER_ON_REGISTER_READ, SIZE_DW }, /* 0x0c */ + { GEN_SPC_REG_RESET, PCIBAR2, SPC_REG_RESET, SIZE_DW }, /* 0x0d */ +}; + +agsaBarOffset_t SPC_V_Table[] = +{ + + { GEN_MSGU_IBDB_SET, PCIBAR0, V_Inbound_Doorbell_Set_Register, SIZE_DW }, /* 0x00 */ + { GEN_MSGU_ODR, PCIBAR0, V_Outbound_Doorbell_Set_Register, SIZE_DW }, /* 0x01 */ + { GEN_MSGU_ODCR, PCIBAR0, V_Outbound_Doorbell_Clear_Register, SIZE_DW }, /* 0x02 */ + { GEN_MSGU_SCRATCH_PAD_0, PCIBAR0, V_Scratchpad_0_Register, SIZE_DW }, /* 0x03 */ + { GEN_MSGU_SCRATCH_PAD_1, PCIBAR0, V_Scratchpad_1_Register, SIZE_DW }, /* 0x04 */ + { GEN_MSGU_SCRATCH_PAD_2, PCIBAR0, V_Scratchpad_2_Register, SIZE_DW }, /* 0x05 */ + { GEN_MSGU_SCRATCH_PAD_3, PCIBAR0, V_Scratchpad_3_Register, SIZE_DW }, /* 0x06 */ + { GEN_MSGU_HOST_SCRATCH_PAD_0, PCIBAR0, V_Host_Scratchpad_0_Register, SIZE_DW }, /* 0x07 */ + { GEN_MSGU_HOST_SCRATCH_PAD_1, PCIBAR0, V_Host_Scratchpad_1_Register, SIZE_DW }, /* 0x08 */ + { GEN_MSGU_HOST_SCRATCH_PAD_2, PCIBAR0, V_Host_Scratchpad_2_Register, SIZE_DW }, /* 0x09 */ + { GEN_MSGU_HOST_SCRATCH_PAD_3, PCIBAR0, V_Host_Scratchpad_3_Register, SIZE_DW }, /* 0x0a */ + { GEN_MSGU_ODMR, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register, SIZE_DW }, /* 0x0b */ + { GEN_PCIE_TRIGGER, PCIBAR0, PCIE_TRIGGER_ON_REGISTER_READ, SIZE_DW }, /* 0x0c */ + { GEN_SPC_REG_RESET, PCIBAR0, V_SoftResetRegister, SIZE_DW }, /* 0x0d */ +}; + + +/*******************************************************************************/ +/** + * + * \brief + * \param agsaRoot Pointer to a data structure containing both application + * and LL layer context handles + * \param Spc_type Device Id of hardware + * + * Return: + * None + */ +/*******************************************************************************/ +GLOBAL void siUpdateBarOffsetTable(agsaRoot_t *agRoot, + bit32 Spc_Type + ) +{ + + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + bit32 x; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"mf"); + + smTrace(hpDBG_VERY_LOUD,"9A",Spc_Type); + /* TP:9A Spc_Type */ + + if(Spc_Type == VEN_DEV_SPC) + { + si_memcpy(&saRoot->SpcBarOffset, SPCTable, sizeof(SPCTable)); + SA_DBG5(("siUpdateBarOffsetTable:sizeof(SPCTable) sizeof(agsaBarOffset_t)sizeof(SPCTable) / sizeof(agsaBarOffset_t) %X %X %X\n", + (unsigned int)sizeof(SPCTable), (unsigned int)sizeof(agsaBarOffset_t), + (unsigned int)(sizeof(SPCTable) / sizeof(agsaBarOffset_t)) + )); + } + else /* VEN_DEV_SPCV */ + { + si_memcpy(&saRoot->SpcBarOffset, SPC_V_Table, sizeof(SPC_V_Table)); + SA_DBG5(("siUpdateBarOffsetTable:sizeof(SPC_V_Table) sizeof(agsaBarOffset_t)sizeof(SPC_V_Table) / sizeof(agsaBarOffset_t) %X %X %X\n", + (unsigned int)sizeof(SPC_V_Table), + (unsigned int)sizeof(agsaBarOffset_t), + (unsigned int)(sizeof(SPC_V_Table) / sizeof(agsaBarOffset_t)) + )); + } + + for(x=0;x < sizeof(SPCTable) / sizeof(agsaBarOffset_t);x++) + { + + SA_DBG4(("%8X: %8X %8X %8X\n",saRoot->SpcBarOffset[x].Generic, + saRoot->SpcBarOffset[x].Bar, + saRoot->SpcBarOffset[x].Offset, + saRoot->SpcBarOffset[x].Length + )); + if(saRoot->SpcBarOffset[x].Generic != x) + { + SA_DBG1(("siUpdateBarOffsetTable: saRoot->SpcBarOffset[%x].Generic %X != %X\n",x, saRoot->SpcBarOffset[x].Generic, x)); + } + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "mf"); +} + + + +GLOBAL bit32 siHalRegReadExt( agsaRoot_t *agRoot, + bit32 generic, + bit32 regOffset + ) +{ + + agsaBarOffset_t * Table = agNULL; + bit32 retVal; + + /* sanity check */ + SA_ASSERT( (agNULL != agRoot), "agRoot"); + Table = WHATTABLE(agRoot); + SA_ASSERT( (agNULL != Table), "Table"); + +/* + if(Table[generic].Offset != regOffset) + { + + SA_DBG1(("siHalRegReadExt: Table[%x].Offset %x != regOffset %x\n",generic, + Table[generic].Offset, + regOffset )); + } +*/ + + if(Table[generic].Bar) + { + retVal = ossaHwRegReadExt(agRoot, + Table[generic].Bar, + Table[generic].Offset); + } + else + { + retVal = ossaHwRegRead(agRoot, + Table[generic].Offset); + } + + return(retVal); +} + + +GLOBAL void siHalRegWriteExt( + agsaRoot_t *agRoot, + bit32 generic, + bit32 regOffset, + bit32 regValue + ) +{ + agsaBarOffset_t * Table = agNULL; + + /* sanity check */ + SA_ASSERT( (agNULL != agRoot), "agRoot"); + + Table = WHATTABLE(agRoot); + SA_ASSERT( (agNULL != Table), "Table"); + + +/* + if(Table[generic].Offset != regOffset) + { + + SA_DBG1(("siHalRegWriteExt: Table[%x].Offset %x != regOffset %x\n",generic, + Table[generic].Offset, + regOffset )); + } +*/ + + SA_DBG6(("siHalRegWriteExt: Bar %x Offset %8X Wrote %8X\n", + Table[generic].Bar, + Table[generic].Offset, + regValue )); + + + if(Table[generic].Bar) + { + ossaHwRegWriteExt(agRoot, + Table[generic].Bar, + Table[generic].Offset, + regValue ); + }else + { + ossaHwRegWrite(agRoot, + Table[generic].Offset, + regValue ); + } +} + + + + +GLOBAL void siPCITriger(agsaRoot_t *agRoot) +{ + + SA_DBG1(("siPCITriger: Read PCIe Bar zero plus 0x%x\n", PCIE_TRIGGER_ON_REGISTER_READ)); + ossaHwRegReadExt(agRoot,PCIBAR0 ,PCIE_TRIGGER_ON_REGISTER_READ ); +} + + +GLOBAL bit32 siGetPciBar( + agsaRoot_t *agRoot + ) +{ + bit32 MSGUCfgTblBase = 0; + bit32 pcibar = 0; + MSGUCfgTblBase = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); + pcibar = (MSGUCfgTblBase & SCRATCH_PAD0_BAR_MASK) >> SHIFT26; + /* get pci Bar index */ + pcibar = (bit8)mpiGetPCIBarIndex(agRoot, pcibar); + + return(pcibar); +} + +GLOBAL bit32 siGetTableOffset( + agsaRoot_t *agRoot, + bit32 TableOffsetInTable + ) +{ + bit32 TableOffset; + bit32 MSGUCfgTblBase; + /* read scratch pad0 to get PCI BAR and offset of configuration table */ + MSGUCfgTblBase = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); + + MSGUCfgTblBase &= SCRATCH_PAD0_OFFSET_MASK; + + TableOffset = ossaHwRegReadExt(agRoot,siGetPciBar(agRoot) ,MSGUCfgTblBase +TableOffsetInTable ); + SA_DBG4(("GetTableOffset:TableOffset with size 0x%x\n", TableOffset)); + + /* Mask off size */ + TableOffset &= 0xFFFFFF; + TableOffset +=MSGUCfgTblBase; + return(TableOffset); + +} + + +GLOBAL void siCheckQs( + agsaRoot_t *agRoot + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + + mpiOCQueue_t *circularOQ; + mpiICQueue_t *circularIQ; + int i; + + for ( i = 0; i < saRoot->QueueConfig.numInboundQueues; i++ ) + { + circularIQ = &saRoot->inboundQueue[i]; + + OSSA_READ_LE_32(circularIQ->agRoot, &circularIQ->consumerIdx, circularIQ->ciPointer, 0); + if(circularIQ->producerIdx != circularIQ->consumerIdx) + { + SA_DBG1(("siCheckQs: In Q %d PI 0x%03x CI 0x%03x (%d) \n",i, + circularIQ->producerIdx, + circularIQ->consumerIdx, + (circularIQ->producerIdx > circularIQ->consumerIdx ? (circularIQ->producerIdx - circularIQ->consumerIdx) : (circularIQ->numElements - circularIQ->consumerIdx ) + circularIQ->producerIdx))); + } + } + + for ( i = 0; i < saRoot->QueueConfig.numOutboundQueues; i++ ) + { + circularOQ = &saRoot->outboundQueue[i]; + OSSA_READ_LE_32(circularOQ->agRoot, &circularOQ->producerIdx, circularOQ->piPointer, 0); + if(circularOQ->producerIdx != circularOQ->consumerIdx) + { + SA_DBG1(("siCheckQs: Out Q %d PI 0x%03x CI 0x%03x (%d) \n",i, + circularOQ->producerIdx, + circularOQ->consumerIdx, + (circularOQ->producerIdx > circularOQ->consumerIdx ? (circularOQ->producerIdx - circularOQ->consumerIdx) : (circularOQ->numElements - circularOQ->consumerIdx ) + circularOQ->producerIdx))); + + } + } + +} +GLOBAL void siPciCpyMem(agsaRoot_t *agRoot, + bit32 soffset, + const void *dst, + bit32 DWcount, + bit32 busBaseNumber + ) +{ + bit32 i, val,offset; + bit32 *dst1; + + dst1 = (bit32 *)dst; + + SA_DBG1(("siPciCpyMem:copy DWcount %d from offset 0x%x to %p\n",DWcount,soffset,dst)); + + for (i= 0; i < DWcount; i+=4,dst1++) + { + offset = (soffset + i / 4); + SA_ASSERT( (offset < (64 * 1024)), "siPciCpyMem offset too large"); + if(offset < (64 * 1024)) + { + val = ossaHwRegReadExt(agRoot, busBaseNumber, offset); + *dst1 = BIT32_TO_LEBIT32(val); + } + } + + return; +} diff --git a/sys/dev/pms/RefTisa/sallsdk/spc/sahwreg.h b/sys/dev/pms/RefTisa/sallsdk/spc/sahwreg.h new file mode 100644 index 000000000000..ca56f5b7c20d --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/spc/sahwreg.h @@ -0,0 +1,709 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/*******************************************************************************/ +/*! \file sahwreg.h + * \brief The file defines the register offset of hardware + */ +/******************************************************************************/ +#ifndef __SAHWREG_H__ + +#define __SAHWREG_H__ + +/* #define MSGU_ACCESS_VIA_XCBI */ /* Defined in build script now */ + +/* Message Unit Registers - BAR0(0x10), BAR0(win) */ +#ifdef SPC_I2O_ENABLE +/* i2o=1 space register offsets - MU_I2O_ENABLE */ +/* Currently FPGA use these offset */ +#define MSGU_IBDB_SET 0x20 +#define MSGU_HOST_INT_STATUS 0x30 +#define MSGU_HOST_INT_MASK 0x34 +#define MSGU_IOPIB_INT_STATUS 0x40 +#define MSGU_IOPIB_INT_MASK 0x44 +#define MSGU_IBDB_CLEAR 0x70 +#define MSGU_MSGU_CONTROL 0x74 +#define MSGU_ODR 0x9C +#define MSGU_ODCR 0xA0 +#define MSGU_SCRATCH_PAD_0 0xB0 +#define MSGU_SCRATCH_PAD_1 0xB4 +#define MSGU_SCRATCH_PAD_2 0xB8 +#define MSGU_SCRATCH_PAD_3 0xBC +#else +/* i2o=0 space register offsets - ~MU_I2O_ENABLE */ +#define MSGU_IBDB_SET 0x04 /* RevA - Write only, RevB - Read/Write */ +#define MSGU_HOST_INT_STATUS 0x08 +#define MSGU_HOST_INT_MASK 0x0C +#define MSGU_IOPIB_INT_STATUS 0x18 +#define MSGU_IOPIB_INT_MASK 0x1C +#define MSGU_IBDB_CLEAR 0x20 /* RevB - Host not use */ +#define MSGU_MSGU_CONTROL 0x24 +#define MSGU_ODR 0x3C /* RevB */ +#define MSGU_ODCR 0x40 /* RevB */ +#define MSGU_SCRATCH_PAD_0 0x44 +#define MSGU_SCRATCH_PAD_1 0x48 +#define MSGU_SCRATCH_PAD_2 0x4C +#define MSGU_SCRATCH_PAD_3 0x50 +#define MSGU_HOST_SCRATCH_PAD_0 0x54 +#define MSGU_HOST_SCRATCH_PAD_1 0x58 +#define MSGU_HOST_SCRATCH_PAD_2 0x5C +#define MSGU_HOST_SCRATCH_PAD_3 0x60 +#define MSGU_HOST_SCRATCH_PAD_4 0x64 +#define MSGU_HOST_SCRATCH_PAD_5 0x68 +#define MSGU_HOST_SCRATCH_PAD_6 0x6C +#define MSGU_HOST_SCRATCH_PAD_7 0x70 +#define MSGU_ODMR 0x74 /* RevB */ +#endif + + + + +/* +Table 215 Messaging Unit Address Map +Offset (Hex) Name Access Internal Offset Internal Name Comment +*/ + +#define V_Inbound_Doorbell_Set_Register 0x00 /* Host R/W Local INT 0x0 MSGU - Inbound Doorbell Set */ +#define V_Inbound_Doorbell_Set_RegisterU 0x04 /* Host R/W Local INT 0x4 MSGU - Inbound Doorbell Set */ +#define V_Inbound_Doorbell_Clear_Register 0x08 /* Host No access Local W, R all 0s 0x8 MSGU - Inbound Doorbell Clear */ +#define V_Inbound_Doorbell_Clear_RegisterU 0x0C /* Host No access Local W, R all 0s 0xC MSGU - Inbound Doorbell Clear */ +#define V_Inbound_Doorbell_Mask_Set_Register 0x10 /* Host RO Local R/W 0x10 MSGU - Inbound Doorbell Mask Set New in SPCv */ +#define V_Inbound_Doorbell_Mask_Set_RegisterU 0x14 /* Host RO Local R/W 0x14 MSGU - Inbound Doorbell Mask Set New in SPCv */ +#define V_Inbound_Doorbell_Mask_Clear_Register 0x18 /* Host RO Local W, R all 0s 0x18 MSGU - Inbound Doorbell Mask Clear New in SPCv */ +#define V_Inbound_Doorbell_Mask_Clear_RegisterU 0x1C /* Host RO Local W, R all 0s 0x1C MSGU - Inbound Doorbell Mask Clear New in SPCv */ +#define V_Outbound_Doorbell_Set_Register 0x20 /* Host RO Local R/W 0x20 MSGU - Outbound Doorbell Set */ +#define V_Outbound_Doorbell_Set_RegisterU 0x24 /* Host RO Local R/W 0x24 MSGU - Outbound Doorbell Set */ +#define V_Outbound_Doorbell_Clear_Register 0x28 /* Host W, R all 0s Local RO 0x28 MSGU - Outbound Doorbell Clear */ +#define V_Outbound_Doorbell_Clear_RegisterU 0x2C /* Host W, R all 0s Local RO 0x2C MSGU - Outbound Doorbell Clear */ +#define V_Outbound_Doorbell_Mask_Set_Register 0x30 /* Host RW Local RO 0x30 MSGU - Outbound Doorbell Mask Set 1's set */ +#define V_Outbound_Doorbell_Mask_Set_RegisterU 0x34 /* Host RW Local RO 0x30 MSGU - Outbound Doorbell Mask Set 1's set */ +#define V_Outbound_Doorbell_Mask_Clear_Register 0x38 /* Host W, R all 0s Local RO 0x38 MSGU - Outbound Doorbell Mask Clear New in SPCv 1's clear */ +#define V_Outbound_Doorbell_Mask_Clear_RegisterU 0x3C /* Host W, R all 0s Local RO 0x38 MSGU - Outbound Doorbell Mask Clear New in SPCv 1's clear */ +/* 0x40 Reserved R all 0s */ +#define V_Scratchpad_0_Register 0x44 /* Host RO Local R/W 0x120 MSGU - Scratchpad 0 */ +#define V_Scratchpad_1_Register 0x48 /* Host RO Local R/W 0x128 MSGU - Scratchpad 1 */ +#define V_Scratchpad_2_Register 0x4C /* Host RO Local R/W 0x130 MSGU - Scratchpad 2 */ +#define V_Scratchpad_3_Register 0x50 /* Host RO Local R/W 0x138 MSGU - Scratchpad 3 */ +#define V_Host_Scratchpad_0_Register 0x54 /* Host RW Local RO 0x140 MSGU - Scratchpad 4 */ +#define V_Host_Scratchpad_1_Register 0x58 /* Host RW Local RO 0x148 MSGU - Scratchpad 5 */ +#define V_Host_Scratchpad_2_Register 0x5C /* Host RW Local RO 0x150 MSGU - Scratchpad 6 */ +#define V_Host_Scratchpad_3_Register 0x60 /* Host RW Local RO 0x158 MSGU - Scratchpad 7 */ +#define V_Host_Scratchpad_4_Register 0x64 /* Host RW Local R/W 0x160 MSGU - Scratchpad 8 */ +#define V_Host_Scratchpad_5_Register 0x68 /* Host RW Local R/W 0x168 MSGU - Scratchpad 9 */ +#define V_Scratchpad_Rsvd_0_Register 0x6C /* Host RW Local R/W 0x170 MSGU - Scratchpad 10 */ +#define V_Scratchpad_Rsvd_1_Register 0x70 /* Host RW Local R/W 0x178 MSGU - Scratchpad 11 */ +/* 0x74 - 0xFF Reserved R all 0s */ +#define V_Outbound_Queue_Consumer_Indices_Base 0x100 /* typical value real offset is read from table to 0x1FF Host RW Local RO 0x1F100 – 0x1F1FF In DQ storage area*/ +#define V_Inbound_Queue_Producer_Indices 0x200 /* typical value real offset is read from table to 0x3FF Host RW Local RO 0x1F200 – 0x1F3FF In DQ storage area, also mapped as WSM*/ +/* + SPC_V SPC + Bar Name Offset Bar Name Offset + PCIBAR0, V_Inbound_Doorbell_Set_Register, 0x00 PCIBAR0, MSGU_IBDB_SET, 0x04 + PCIBAR0, V_Inbound_Doorbell_Clear_Register, 0x08 NA + PCIBAR0, V_Inbound_Doorbell_Mask_Set_Register, 0x10 NA + PCIBAR0, V_Inbound_Doorbell_Mask_Clear_Register, 0x18 NA + PCIBAR0, V_Outbound_Doorbell_Set_Register, 0x20 PCIBAR0, MSGU_ODR, 0x3C + PCIBAR0, V_Outbound_Doorbell_Clear_Register, 0x28 PCIBAR0, MSGU_ODCR, 0x40 + PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register, 0x30 PCIBAR0, MSGU_ODMR, 0x74 + PCIBAR0, V_Outbound_Doorbell_Mask_Clear_Register, 0x38 NA + PCIBAR0, V_Scratchpad_0_Register, 0x44 PCIBAR0, MSGU_SCRATCH_PAD_0, 0x44 + PCIBAR0, V_Scratchpad_1_Register, 0x48 PCIBAR0, MSGU_SCRATCH_PAD_1, 0x48 + PCIBAR0, V_Scratchpad_2_Register, 0x4C PCIBAR0, MSGU_SCRATCH_PAD_2, 0x4C + PCIBAR0, V_Scratchpad_3_Register, 0x50 PCIBAR0, MSGU_SCRATCH_PAD_3, 0x50 + PCIBAR0, V_Host_Scratchpad_0_Register, 0x54 PCIBAR0, MSGU_HOST_SCRATCH_PAD_0, 0x54 + PCIBAR0, V_Host_Scratchpad_1_Register, 0x58 PCIBAR0, MSGU_HOST_SCRATCH_PAD_1, 0x58 + PCIBAR0, V_Host_Scratchpad_2_Register, 0x5C PCIBAR0, MSGU_HOST_SCRATCH_PAD_2, 0x5C + PCIBAR0, V_Host_Scratchpad_3_Register, 0x60 PCIBAR0, MSGU_HOST_SCRATCH_PAD_3, 0x60 + +*/ + + +#define V_RamEccDbErr 0x00000018 +#define V_SoftResetRegister 0x1000 +#define V_MEMBASE_II_ShiftRegister 0x1010 + +#define V_GsmConfigReset 0 +#define V_GsmReadAddrParityCheck 0x38 +#define V_GsmWriteAddrParityCheck 0x40 +#define V_GsmWriteDataParityCheck 0x48 +#define V_GsmReadAddrParityIndic 0x58 +#define V_GsmWriteAddrParityIndic 0x60 +#define V_GsmWriteDataParityIndic 0x68 + + +#define SPCv_Reset_Reserved 0xFFFFFF3C +#define SPCv_Reset_Read_Mask 0xC0 +#define SPCv_Reset_Read_NoReset 0x0 +#define SPCv_Reset_Read_NormalResetOccurred 0x40 +#define SPCv_Reset_Read_SoftResetHDAOccurred 0x80 +#define SPCv_Reset_Read_ChipResetOccurred 0xC0 + + +#define SPCv_Reset_Write_NormalReset 0x1 +#define SPCv_Reset_Write_SoftResetHDA 0x2 +#define SPCv_Reset_Write_ChipReset 0x3 + +/* [31:8] Reserved -- Reserved Host R / Local R/W */ + +/* Indicator that a controller soft reset has occurred. +The bootloader sets this field when a soft reset occurs. Host is read only. +[7:6] +b00: No soft reset occurred. Device reset value. +b01: Normal soft reset occurred. +b10: Soft reset HDA mode occurred. +b11: Chip reset occurred. +Soft Reset Occurred SFT_RST_OCR +[5:2] Reserved -- Reserved b0000 Reserved +Host R/W / Local R +The controller soft reset type that is required by the host side. The host sets this field and the bootloader clears it. +b00: Ready for soft reset / normal status. +b01: Normal soft reset. +b10: Soft reset HDA mode. +b11: Chip reset. +Soft Reset Requested +SFT_RST_RQST +[1:0] + */ + + + + +/***** RevB - ODAR - Outbound DoorBell Auto-Clearing Register + ICT - Interrupt Coalescing Timer Register + ICC - Interrupt Coalescing Control Register + - BAR2(0x18), BAR1(win) *****/ +/****************** 64 KB BAR *****************/ +#define SPC_ODAR 0x00335C +#define SPC_ICTIMER 0x0033C0 +#define SPC_ICCONTROL 0x0033C4 + +/* BAR2(0x18), BAR1(win) */ +#define MSGU_XCBI_IBDB_REG 0x003034 /* PCIE - Message Unit Inbound Doorbell register */ +#define MSGU_XCBI_OBDB_REG 0x003354 /* PCIE - Message Unit Outbound Doorbell Interrupt Register */ +#define MSGU_XCBI_OBDB_MASK 0x003358 /* PCIE - Message Unit Outbound Doorbell Interrupt Mask Register */ +#define MSGU_XCBI_OBDB_CLEAR 0x00303C /* PCIE - Message Unit Outbound Doorbell Interrupt Clear Register */ + +/* RB6 offset */ +#define SPC_RB6_OFFSET 0x80C0 + +#define RB6_MAGIC_NUMBER_RST 0x1234 /* Magic number of soft reset for RB6 */ + +#ifdef MSGU_ACCESS_VIA_XCBI +#define MSGU_READ_IDR ossaHwRegReadExt(agRoot, PCIBAR1, MSGU_XCBI_IBDB_REG) +#define MSGU_READ_ODMR ossaHwRegReadExt(agRoot, PCIBAR1, MSGU_XCBI_OBDB_MASK) +#define MSGU_READ_ODR ossaHwRegReadExt(agRoot, PCIBAR1, MSGU_XCBI_OBDB_REG) +#define MSGU_READ_ODCR ossaHwRegReadExt(agRoot, PCIBAR1, MSGU_XCBI_OBDB_CLEAR) +#else +#define MSGU_READ_IDR siHalRegReadExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET) +#define MSGU_READ_ODMR siHalRegReadExt(agRoot, GEN_MSGU_ODMR, MSGU_ODMR) +#define MSGU_READ_ODR siHalRegReadExt(agRoot, GEN_MSGU_ODR, MSGU_ODR) +#define MSGU_READ_ODCR siHalRegReadExt(agRoot, GEN_MSGU_ODCR, MSGU_ODCR) +#endif + +/* bit definition for ODMR register */ +#define ODMR_MASK_ALL 0xFFFFFFFF /* mask all interrupt vector */ +#define ODMR_CLEAR_ALL 0 /* clear all interrupt vector */ +/* bit definition for ODMR register */ +#define ODCR_CLEAR_ALL 0xFFFFFFFF /* mask all interrupt vector */ + +/* bit definition for Inbound Doorbell register */ +#define IBDB_IBQ_UNFREEZE 0x08 /* Inbound doorbell bit3 */ +#define IBDB_IBQ_FREEZE 0x04 /* Inbound doorbell bit2 */ +#define IBDB_CFG_TABLE_RESET 0x02 /* Inbound doorbell bit1 */ +#define IBDB_CFG_TABLE_UPDATE 0x01 /* Inbound doorbell bit0 */ + +#define IBDB_MPIIU 0x08 /* Inbound doorbell bit3 - Unfreeze */ +#define IBDB_MPIIF 0x04 /* Inbound doorbell bit2 - Freeze */ +#define IBDB_MPICT 0x02 /* Inbound doorbell bit1 - Termination */ +#define IBDB_MPIINI 0x01 /* Inbound doorbell bit0 - Initialization */ + +/* bit mask definition for Scratch Pad0 register */ +#define SCRATCH_PAD0_BAR_MASK 0xFC000000 /* bit31-26 - mask bar */ +#define SCRATCH_PAD0_OFFSET_MASK 0x03FFFFFF /* bit25-0 - offset mask */ +#define SCRATCH_PAD0_AAPERR_MASK 0xFFFFFFFF /* if AAP error state */ + +/* state definition for Scratch Pad1 register */ +#define SCRATCH_PAD1_POR 0x00 /* power on reset state */ +#define SCRATCH_PAD1_SFR 0x01 /* soft reset state */ +#define SCRATCH_PAD1_ERR 0x02 /* error state */ +#define SCRATCH_PAD1_RDY 0x03 /* ready state */ +#define SCRATCH_PAD1_RST 0x04 /* soft reset toggle flag */ +#define SCRATCH_PAD1_AAP1RDY_RST 0x08 /* AAP1 ready for soft reset */ +#define SCRATCH_PAD1_STATE_MASK 0xFFFFFFF0 /* ScratchPad1 Mask other bits 31:4, bit1-0 State */ +#define SCRATCH_PAD1_RESERVED 0x000000F0 /* Scratch Pad1 Reserved bit 4 to 7 */ + + + +#define SCRATCH_PAD1_V_RAAE_MASK 0x00000003 /* 0 1 also ready */ +#define SCRATCH_PAD1_V_RAAE_ERR 0x00000002 /* 1 */ +#define SCRATCH_PAD1_V_ILA_MASK 0x0000000C /* 2 3 also ready */ +#define SCRATCH_PAD1_V_ILA_ERR 0x00000008 /* 3 */ +#define SCRATCH_PAD1_V_BOOTSTATE_MASK 0x00000070 /* 456 */ +#define SCRATCH_PAD1_V_BOOTSTATE_SUCESS 0x00000000 /* Load successful */ +#define SCRATCH_PAD1_V_BOOTSTATE_HDA_SEEPROM 0x00000010 /* HDA Mode SEEPROM Setting */ +#define SCRATCH_PAD1_V_BOOTSTATE_HDA_BOOTSTRAP 0x00000020 /* HDA Mode BootStrap Setting */ +#define SCRATCH_PAD1_V_BOOTSTATE_HDA_SOFTRESET 0x00000030 /* HDA Mode Soft Reset */ +#define SCRATCH_PAD1_V_BOOTSTATE_CRIT_ERROR 0x00000040 /* HDA Mode due to critical error */ +#define SCRATCH_PAD1_V_BOOTSTATE_R1 0x00000050 /* Reserved */ +#define SCRATCH_PAD1_V_BOOTSTATE_R2 0x00000060 /* Reserved */ +#define SCRATCH_PAD1_V_BOOTSTATE_FATAL 0x00000070 /* Fatal Error Boot process halted */ + + +#define SCRATCH_PAD1_V_ILA_IMAGE 0x00000080 /* 7 */ +#define SCRATCH_PAD1_V_FW_IMAGE 0x00000100 /* 8 */ +#define SCRATCH_PAD1_V_BIT9_RESERVED 0x00000200 /* 9 */ +#define SCRATCH_PAD1_V_IOP0_MASK 0x00000C00 /* 10 11 also ready */ +#define SCRATCH_PAD1_V_IOP0_ERR 0x00000800 /* 11 */ +#define SCRATCH_PAD1_V_IOP1_MASK 0x00003000 /* 12 13 also ready */ +#define SCRATCH_PAD1_V_IOP1_ERR 0x00002000 /* 13 */ +#define SCRATCH_PAD1_V_RESERVED 0xFFFFC000 /* 14-31 */ + +#define SCRATCH_PAD1_V_READY ( SCRATCH_PAD1_V_RAAE_MASK | SCRATCH_PAD1_V_ILA_MASK | SCRATCH_PAD1_V_IOP0_MASK ) /* */ +#define SCRATCH_PAD1_V_ERROR ( SCRATCH_PAD1_V_RAAE_ERR | SCRATCH_PAD1_V_ILA_ERR | SCRATCH_PAD1_V_IOP0_ERR | SCRATCH_PAD1_V_IOP1_ERR ) /* Scratch Pad1 13 11 3 1 */ + +#define SCRATCH_PAD1_V_ILA_ERROR_STATE(ScratchPad1) ((((ScratchPad1) & SCRATCH_PAD1_V_ILA_MASK ) == SCRATCH_PAD1_V_ILA_MASK) ? 0: \ + (((ScratchPad1) & SCRATCH_PAD1_V_ILA_MASK ) == SCRATCH_PAD1_V_ILA_ERR ) ? SCRATCH_PAD1_V_ILA_ERR : 0 ) + +#define SCRATCH_PAD1_V_RAAE_ERROR_STATE(ScratchPad1) ((((ScratchPad1) & SCRATCH_PAD1_V_RAAE_MASK ) == SCRATCH_PAD1_V_RAAE_MASK) ? 0: \ + (((ScratchPad1) & SCRATCH_PAD1_V_RAAE_MASK ) == SCRATCH_PAD1_V_RAAE_ERR) ? SCRATCH_PAD1_V_RAAE_ERR : 0 ) + +#define SCRATCH_PAD1_V_IOP0_ERROR_STATE(ScratchPad1) ((((ScratchPad1) & SCRATCH_PAD1_V_IOP0_MASK ) == SCRATCH_PAD1_V_IOP0_MASK) ? 0: \ + (((ScratchPad1) & SCRATCH_PAD1_V_IOP0_MASK ) == SCRATCH_PAD1_V_IOP0_ERR) ? SCRATCH_PAD1_V_IOP0_ERR : 0 ) + +#define SCRATCH_PAD1_V_IOP1_ERROR_STATE(ScratchPad1) ((((ScratchPad1) & SCRATCH_PAD1_V_IOP1_MASK ) == SCRATCH_PAD1_V_IOP1_MASK) ? 0: \ + (((ScratchPad1) & SCRATCH_PAD1_V_IOP1_MASK ) == SCRATCH_PAD1_V_IOP1_ERR) ? SCRATCH_PAD1_V_IOP1_ERR : 0 ) + +#define SCRATCH_PAD1_V_ERROR_STATE(ScratchPad1) ( SCRATCH_PAD1_V_ILA_ERROR_STATE(ScratchPad1) | \ + SCRATCH_PAD1_V_RAAE_ERROR_STATE(ScratchPad1) | \ + SCRATCH_PAD1_V_IOP0_ERROR_STATE(ScratchPad1) | \ + SCRATCH_PAD1_V_IOP1_ERROR_STATE(ScratchPad1) ) + +#define SCRATCH_PAD1_V_BOOTLDR_ERROR 0x00000070 /* Scratch Pad1 (6 5 4) */ + + +/* error bit definition */ +#define SCRATCH_PAD1_BDMA_ERR 0x80000000 /* bit31 */ +#define SCRATCH_PAD1_GSM_ERR 0x40000000 /* bit30 */ +#define SCRATCH_PAD1_MBIC1_ERR 0x20000000 /* bit29 */ +#define SCRATCH_PAD1_MBIC1_SET0_ERR 0x10000000 /* bit28 */ +#define SCRATCH_PAD1_MBIC1_SET1_ERR 0x08000000 /* bit27 */ +#define SCRATCH_PAD1_PMIC1_ERR 0x04000000 /* bit26 */ +#define SCRATCH_PAD1_PMIC2_ERR 0x02000000 /* bit25 */ +#define SCRATCH_PAD1_PMIC_EVENT_ERR 0x01000000 /* bit24 */ +#define SCRATCH_PAD1_OSSP_ERR 0x00800000 /* bit23 */ +#define SCRATCH_PAD1_SSPA_ERR 0x00400000 /* bit22 */ +#define SCRATCH_PAD1_SSPL_ERR 0x00200000 /* bit21 */ +#define SCRATCH_PAD1_HSST_ERR 0x00100000 /* bit20 */ +#define SCRATCH_PAD1_PCS_ERR 0x00080000 /* bit19 */ +#define SCRATCH_PAD1_FW_INIT_ERR 0x00008000 /* bit15 */ +#define SCRATCH_PAD1_FW_ASRT_ERR 0x00004000 /* bit14 */ +#define SCRATCH_PAD1_FW_WDG_ERR 0x00002000 /* bit13 */ +#define SCRATCH_PAD1_AAP_ERROR_STATE 0x00000002 /* bit1 */ +#define SCRATCH_PAD1_AAP_READY 0x00000003 /* bit1 & bit0 */ + + +/* state definition for Scratch Pad2 register */ +#define SCRATCH_PAD2_POR 0x00 /* power on state */ +#define SCRATCH_PAD2_SFR 0x01 /* soft reset state */ +#define SCRATCH_PAD2_ERR 0x02 /* error state */ +#define SCRATCH_PAD2_RDY 0x03 /* ready state */ +#define SCRATCH_PAD2_FWRDY_RST 0x04 /* FW ready for soft reset rdy flag */ +#define SCRATCH_PAD2_IOPRDY_RST 0x08 /* IOP ready for soft reset */ +#define SCRATCH_PAD2_STATE_MASK 0xFFFFFFF0 /* ScratchPad 2 Mask for other bits 31:4, bit1-0 State*/ +#define SCRATCH_PAD2_RESERVED 0x000000F0 /* Scratch Pad1 Reserved bit 4 to 7 */ + +/* error bit definition */ +#define SCRATCH_PAD2_BDMA_ERR 0x80000000 /* bit31 */ +#define SCRATCH_PAD2_GSM_ERR 0x40000000 /* bit30 */ +#define SCRATCH_PAD2_MBIC3_ERR 0x20000000 /* bit29 */ +#define SCRATCH_PAD2_MBIC3_SET0_ERR 0x10000000 /* bit28 */ +#define SCRATCH_PAD2_MBIC3_SET1_ERR 0x08000000 /* bit27 */ +#define SCRATCH_PAD2_PMIC1_ERR 0x04000000 /* bit26 */ +#define SCRATCH_PAD2_PMIC2_ERR 0x02000000 /* bit25 */ +#define SCRATCH_PAD2_PMIC_EVENT_ERR 0x01000000 /* bit24 */ +#define SCRATCH_PAD2_OSSP_ERR 0x00800000 /* bit23 */ +#define SCRATCH_PAD2_SSPA_ERR 0x00400000 /* bit22 */ +#define SCRATCH_PAD2_SSPL_ERR 0x00200000 /* bit21 */ +#define SCRATCH_PAD2_HSST_ERR 0x00100000 /* bit20 */ +#define SCRATCH_PAD2_PCS_ERR 0x00080000 /* bit19 */ + +#define SCRATCH_PAD2_FW_BOOT_ROM_ERROR 0x00010000 /* bit16 */ +#define SCRATCH_PAD2_FW_ILA_ERR 0x00008000 /* bit15 */ +#define SCRATCH_PAD2_FW_FLM_ERR 0x00004000 /* bit14 */ +#define SCRATCH_PAD2_FW_FW_ASRT_ERR 0x00002000 /* bit13 */ +#define SCRATCH_PAD2_FW_HW_WDG_ERR 0x00001000 /* bit12 */ +#define SCRATCH_PAD2_FW_GEN_EXCEPTION_ERR 0x00000800 /* bit11 */ +#define SCRATCH_PAD2_FW_UNDTMN_ERR 0x00000400 /* bit10 */ +#define SCRATCH_PAD2_FW_HW_FATAL_ERR 0x00000200 /* bit9 */ +#define SCRATCH_PAD2_FW_HW_NON_FATAL_ERR 0x00000100 /* bit8 */ +#define SCRATCH_PAD2_FW_HW_MASK 0x000000FF +#define SCRATCH_PAD2_HW_ERROR_INT_INDX_PCS_ERR 0x00 +#define SCRATCH_PAD2_HW_ERROR_INT_INDX_GSM_ERR 0x01 +#define SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP0_ERR 0x02 +#define SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP1_ERR 0x03 +#define SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP2_ERR 0x04 +#define SCRATCH_PAD2_HW_ERROR_INT_INDX_ERAAE_ERR 0x05 +#define SCRATCH_PAD2_HW_ERROR_INT_INDX_SDS_ERR 0x06 +#define SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_CORE_ERR 0x08 +#define SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_AL_ERR 0x0C +#define SCRATCH_PAD2_HW_ERROR_INT_INDX_MSGU_ERR 0x0E +#define SCRATCH_PAD2_HW_ERROR_INT_INDX_SPBC_ERR 0x0F +#define SCRATCH_PAD2_HW_ERROR_INT_INDX_BDMA_ERR 0x10 +#define SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSL2B_ERR 0x13 +#define SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSDC_ERR 0x14 +#define SCRATCH_PAD2_HW_ERROR_INT_INDX_UNDETERMINED_ERROR_OCCURRED 0xFF + + + +#define SCRATCH_PAD_ERROR_MASK 0xFFFFFF00 /* Error mask bits 31:8 */ +#define SCRATCH_PAD_STATE_MASK 0x00000003 /* State Mask bits 1:0 */ + +#define SPCV_RAAE_STATE_MASK 0x3 +#define SPCV_IOP0_STATE_MASK ((1 << 10) | (1 << 11)) +#define SPCV_IOP1_STATE_MASK ((1 << 12) | (1 << 13)) +#define SPCV_ERROR_VALUE 0x2 + + +#define SCRATCH_PAD3_FW_IMAGE_MASK 0x0000000F /* SPC 8x6G boots from Image */ +#define SCRATCH_PAD3_FW_IMAGE_FLAG_VALID 0x00000008 /* Image flag is valid */ +#define SCRATCH_PAD3_FW_IMAGE_B_VALID 0x00000004 /* Image B is valid */ +#define SCRATCH_PAD3_FW_IMAGE_A_VALID 0x00000002 /* Image A is valid */ +#define SCRATCH_PAD3_FW_IMAGE_B_ACTIVE 0x00000001 /* Image B is active */ + + +#define SCRATCH_PAD3_V_ 0x00000001 /* Image B is valid */ + +#define SCRATCH_PAD3_V_ENC_DISABLED 0x00000000 /* */ +#define SCRATCH_PAD3_V_ENC_DIS_ERR 0x00000001 /* */ +#define SCRATCH_PAD3_V_ENC_ENA_ERR 0x00000002 /* */ +#define SCRATCH_PAD3_V_ENC_READY 0x00000003 /* */ +#define SCRATCH_PAD3_V_ENC_MASK SCRATCH_PAD3_V_ENC_READY /* */ + +#define SCRATCH_PAD3_V_AUT 0x00000008 /* AUT Operator authentication*/ +#define SCRATCH_PAD3_V_ARF 0x00000004 /* ARF factory mode. */ + +#define SCRATCH_PAD3_V_XTS_ENABLED (1 << SHIFT14) /* */ +#define SCRATCH_PAD3_V_SMA_ENABLED (1 << SHIFT4 ) /* */ +#define SCRATCH_PAD3_V_SMB_ENABLED (1 << SHIFT5 ) /* */ +#define SCRATCH_PAD3_V_SMF_ENABLED 0 /* */ +#define SCRATCH_PAD3_V_SM_MASK 0x000000F0 /* */ +#define SCRATCH_PAD3_V_ERR_CODE 0x00FF0000 /* */ + + +/* Dynamic map through Bar4 - 0x00700000 */ +#define GSM_CONFIG_RESET 0x00000000 +#define RAM_ECC_DB_ERR 0x00000018 +#define GSM_READ_ADDR_PARITY_INDIC 0x00000058 +#define GSM_WRITE_ADDR_PARITY_INDIC 0x00000060 +#define GSM_WRITE_DATA_PARITY_INDIC 0x00000068 +#define GSM_READ_ADDR_PARITY_CHECK 0x00000038 +#define GSM_WRITE_ADDR_PARITY_CHECK 0x00000040 +#define GSM_WRITE_DATA_PARITY_CHECK 0x00000048 + +/* signature defintion for host scratch pad0 register */ +#define SPC_SOFT_RESET_SIGNATURE 0x252acbcd /* Signature for Soft Reset */ +#define SPC_HDASOFT_RESET_SIGNATURE 0xa5aa27d7 /* Signature for HDA Soft Reset without PCIe resetting */ + +/**** SPC Top-level Registers definition for Soft Reset/HDA mode ****/ +/****************** 64 KB BAR *****************/ +/* SPC Reset register - BAR4(0x20), BAR2(win) (need dynamic mapping) */ +#define SPC_REG_RESET 0x000000 /* reset register */ +#define SPC_REG_DEVICE_LCLK 0x000058 /* Device LCLK generation register */ + +#define SPC_READ_RESET_REG siHalRegReadExt(agRoot, GEN_SPC_REG_RESET, SPC_REG_RESET) + +#define SPC_WRITE_RESET_REG(value) ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, value); +/* NMI register - BAR4(0x20), BAR2(win) 0x060000/0x070000 */ +//#define MBIC_RAW_NMI_STAT_VPE0_IOP 0x0004C8 not used anymore +//#define MBIC_RAW_NMI_STAT_VPE0_AAP1 0x0104C8 not used anymore +#define MBIC_NMI_ENABLE_VPE0_IOP 0x000418 +#define MBIC_NMI_ENABLE_VPE0_AAP1 0x000418 + +/* PCIE registers - BAR2(0x18), BAR1(win) 0x010000 */ +#define PCIE_EVENT_INTERRUPT_ENABLE 0x003040 +#define PCIE_EVENT_INTERRUPT 0x003044 +#define PCIE_ERROR_INTERRUPT_ENABLE 0x003048 +#define PCIE_ERROR_INTERRUPT 0x00304C + +/* PCIe Message Unit Configuration Registers offset - BAR2(0x18), BAR1(win) 0x010000 */ +#define SPC_REG_MSGU_CONFIG 0x003018 +#define PMIC_MU_CFG_1_BITMSK_MU_MEM_ENABLE 0x00000010 + +/* bit difination for SPC_RESET register */ +#define SPC_REG_RESET_OSSP 0x00000001 +#define SPC_REG_RESET_RAAE 0x00000002 +#define SPC_REG_RESET_PCS_SPBC 0x00000004 +#define SPC_REG_RESET_PCS_IOP_SS 0x00000008 +#define SPC_REG_RESET_PCS_AAP1_SS 0x00000010 +#define SPC_REG_RESET_PCS_AAP2_SS 0x00000020 +#define SPC_REG_RESET_PCS_LM 0x00000040 +#define SPC_REG_RESET_PCS 0x00000080 +#define SPC_REG_RESET_GSM 0x00000100 +#define SPC_REG_RESET_DDR2 0x00010000 +#define SPC_REG_RESET_BDMA_CORE 0x00020000 +#define SPC_REG_RESET_BDMA_SXCBI 0x00040000 +#define SPC_REG_RESET_PCIE_AL_SXCBI 0x00080000 +#define SPC_REG_RESET_PCIE_PWR 0x00100000 +#define SPC_REG_RESET_PCIE_SFT 0x00200000 +#define SPC_REG_RESET_PCS_SXCBI 0x00400000 +#define SPC_REG_RESET_LMS_SXCBI 0x00800000 +#define SPC_REG_RESET_PMIC_SXCBI 0x01000000 +#define SPC_REG_RESET_PMIC_CORE 0x02000000 +#define SPC_REG_RESET_PCIE_PC_SXCBI 0x04000000 +#define SPC_REG_RESET_DEVICE 0x80000000 + +/* bit definition for SPC Device Revision register - BAR1 */ +#define SPC_REG_DEVICE_REV 0x000024 +#define SPC_REG_DEVICE_REV_MASK 0x0000000F + + +/* bit definition for SPC_REG_TOP_DEVICE_ID - BAR2 */ +#define SPC_REG_TOP_DEVICE_ID 0x20 +#define SPC_TOP_DEVICE_ID 0x8001 + +#define SPC_REG_TOP_BOOT_STRAP 0x8 +#define SPC_TOP_BOOT_STRAP 0x02C0A682 + + +/* For PHY Error */ +#define COUNT_OFFSET 0x4000 +#define LCLK_CLEAR 0x2 +#define LCLK 0x1 +#define CNTL_OFFSET 0x100 +#define L0_LCLK_CLEAR 0x2 +#define L0_LCLK 0x1 +#define DEVICE_LCLK_CLEAR 0x40 + +/****************** 64 KB BAR *****************/ +/* PHY Error Count Registers - BAR4(0x20), BAR2(win) (need dynamic mapping) */ +#define SPC_SSPL_COUNTER_CNTL 0x001030 +#define SPC_INVALID_DW_COUNT 0x001034 +#define SPC_RUN_DISP_ERROR_COUNT 0x001038 +#define SPC_CODE_VIOLATION_COUNT 0x00103C +#define SPC_LOSS_DW_SYNC_COUNT 0x001040 +#define SPC_PHY_RESET_PROBLEM_COUNT 0x001044 +#define SPC_READ_DEV_REV ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_DEVICE_REV); + +#define SPC_READ_COUNTER_CNTL(phyId) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_SSPL_COUNTER_CNTL + (COUNT_OFFSET * phyId)) +#define SPC_WRITE_COUNTER_CNTL(phyId, value) ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_SSPL_COUNTER_CNTL + (COUNT_OFFSET * phyId), value) +#define SPC_READ_INV_DW_COUNT(phyId) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_INVALID_DW_COUNT + (COUNT_OFFSET * phyId)) +#define SPC_READ_DISP_ERR_COUNT(phyId) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_RUN_DISP_ERROR_COUNT + (COUNT_OFFSET * phyId)) +#define SPC_READ_CODE_VIO_COUNT(phyId) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_CODE_VIOLATION_COUNT + (COUNT_OFFSET * phyId)) +#define SPC_READ_LOSS_DW_COUNT(phyId) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_LOSS_DW_SYNC_COUNT + (COUNT_OFFSET * phyId)) +#define SPC_READ_PHY_RESET_COUNT(phyId) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_PHY_RESET_PROBLEM_COUNT + (COUNT_OFFSET * phyId)) +/* PHY Error Count Control Registers - BAR2(0x18), BAR1(win) */ +#define SPC_L0_ERR_CNT_CNTL 0x0041B0 +#define SPC_READ_L0ERR_CNT_CNTL(phyId) ossaHwRegReadExt(agRoot, PCIBAR1, SPC_L0_ERR_CNT_CNTL + (CNTL_OFFSET * phyId)) +#define SPC_WRITE_L0ERR_CNT_CNTL(phyId, value) ossaHwRegWriteExt(agRoot, PCIBAR1, SPC_L0_ERR_CNT_CNTL + (CNTL_OFFSET * phyId), value) + +/* registers for BAR Shifting - BAR2(0x18), BAR1(win) */ +#define SPC_IBW_AXI_TRANSLATION_LOW 0x003258 + +/* HDA mode definitions */ +/* 256KB */ +#define HDA_CMD_OFFSET256K 0x0003FFC0 +#define HDA_RSP_OFFSET256K 0x0003FFE0 + +/* 512KB */ +#define HDA_CMD_OFFSET512K 0x0007FFC0 +#define HDA_RSP_OFFSET512K 0x0007FFE0 + +/* 768KB */ +#define HDA_CMD_OFFSET768K 0x000BFFC0 +#define HDA_RSP_OFFSET768K 0x000BFFE0 + +/* 1024KB - by default */ +#define HDA_CMD_OFFSET1MB 0x0000FEC0 +#define HDA_RSP_OFFSET1MB 0x0000FEE0 + + + +/* Table 27 Boot ROM HDA Protocol Command Format */ +typedef struct spcv_hda_cmd_s { +/* Offset Byte 3 Byte 2 Byte 1 Byte 0 */ + bit32 cmdparm_0; /* 0 Command Parameter 0 */ + bit32 cmdparm_1; /* 4 Command Parameter 1 */ + bit32 cmdparm_2; /* 8 Command Parameter 2 */ + bit32 cmdparm_3; /* 12 Command Parameter 3 */ + bit32 cmdparm_4; /* 16 Command Parameter 4 */ + bit32 cmdparm_5; /* 20 Command Parameter 5 */ + bit32 cmdparm_6; /* 24 Command Parameter 6 */ + bit32 C_PA_SEQ_ID_CMD_CODE; /* 28 C_PA SEQ_ID CMD_CODE */ +} spcv_hda_cmd_t; + +/* Table 28 Boot ROM HDA Protocol Response Format */ +typedef struct spcv_hda_rsp_s { +/* Offset Byte 3 Byte 2 Byte 1 Byte 0 */ + bit32 cmdparm_0; /* 0 Command Parameter 0 */ + bit32 cmdparm_1; /* 4 Command Parameter 1 */ + bit32 cmdparm_2; /* 8 Command Parameter 2 */ + bit32 cmdparm_3; /* 12 Command Parameter 3 */ + bit32 cmdparm_4; /* 16 Command Parameter 4 */ + bit32 cmdparm_5; /* 20 Command Parameter 5 */ + bit32 cmdparm_6; /* 24 Command Parameter 6 */ + bit32 R_PA_SEQ_ID_RSP_CODE; /* 28 C_PA SEQ_ID CMD_CODE */ +} spcv_hda_rsp_t; + +#define SPC_V_HDA_COMMAND_OFFSET 0x000042c0 +#define SPC_V_HDA_RESPONSE_OFFSET 0x000042e0 + + +#define HDA_C_PA_OFFSET 0x1F +#define HDA_SEQ_ID_OFFSET 0x1E +#define HDA_PAR_LEN_OFFSET 0x04 +#define HDA_CMD_CODE_OFFSET 0x1C +#define HDA_RSP_CODE_OFFSET 0x1C +#define SM_HDA_RSP_OFFSET1MB_PLUS_HDA_RSP_CODE_OFFSET (HDA_RSP_OFFSET1MB + HDA_RSP_CODE_OFFSET) + +/* commands */ +#define SPC_V_HDAC_PA 0xCB +#define SPC_V_HDAC_BUF_INFO 0x0001 +#define SPC_V_HDAC_EXEC 0x0002 +#define SPC_V_HDAC_RESET 0x0003 +#define SPC_V_HDAC_DMA 0x0004 + +#define SPC_V_HDAC_PA_MASK 0xFF000000 +#define SPC_V_HDAC_SEQID_MASK 0x00FF0000 +#define SPC_V_HDAC_CMDCODE_MASK 0x0000FFFF + +/* responses */ +#define SPC_V_HDAR_PA 0xDB +#define SPC_V_HDAR_BUF_INFO 0x8001 +#define SPC_V_HDAR_IDLE 0x8002 +#define SPC_V_HDAR_BAD_IMG 0x8003 +#define SPC_V_HDAR_BAD_CMD 0x8004 +#define SPC_V_HDAR_INTL_ERR 0x8005 +#define SPC_V_HDAR_EXEC 0x8006 + +#define SPC_V_HDAR_PA_MASK 0xFF000000 +#define SPC_V_HDAR_SEQID_MASK 0x00FF0000 +#define SPC_V_HDAR_RSPCODE_MASK 0x0000FFFF + +#define ILAHDA_RAAE_IMG_GET 0x11 +#define ILAHDA_IOP_IMG_GET 0x10 + +#define ILAHDAC_RAAE_IMG_DONE 0x81 + + +#define HDA_AES_DIF_FUNC 0xFEDFAE1F + + +/* Set MSGU Mapping Registers in BAR0 */ +#define PMIC_MU_CFG_1_BITMSK_MU_IO_ENABLE 0x00000001 +#define PMIC_MU_CFG_1_BITMSK_MU_IO_WIR 0x0000000C +#define PMIC_MU_CFG_1_BITMSK_MU_MEM_ENABLE 0x00000010 +#define PMIC_MU_CFG_1_BITMSK_MU_MEM_OFFSET 0xFFFFFC00 + +/* PMIC Init */ +#define MU_MEM_OFFSET 0x0 +#define MSGU_MU_IO_WIR 0x8 /* Window 0 */ + +#define BOOTTLOADERHDA_IDLE 0x8002 +#define HDAR_BAD_IMG 0x8003 +#define HDAR_BAD_CMD 0x8004 +#define HDAR_EXEC 0x8006 + +#define CEILING(X, rem) ((((bit32)X % rem) > 0) ? (bit32)(X/rem+1) : (bit32)(X/rem)) + +#define GSMSM_AXI_LOWERADDR 0x00400000 +#define SHIFT_MASK 0xFFFF0000 +#define OFFSET_MASK 0x0000FFFF +#define SIZE_64KB 0x00010000 +#define ILA_ISTR_ADDROFFSETHDA 0x0007E000 +#define HDA_STATUS_BITS 0x0000FFFF + +/* Scratchpad Reg: bit[31]: 1-CMDFlag 0-RSPFlag; bit[30,24]:CMD/RSP; bit[23,0]:Offset/Size - Shared with the host driver */ +/* ILA: Mandatory response / state codes in MSGU Scratchpad 0 */ +#define ILAHDA_IOP_IMG_GET 0x10 +#define ILAHDA_AAP1_IMG_GET 0x11 +#define ILAHDA_AAP2_IMG_GET 0x12 +#define ILAHDA_EXITGOOD 0x1F + +/* HOST: Mandatory command codes in Host Scratchpad 3 */ +#define ILAHDAC_IOP_IMG_DONE 0x00000080 +#define ILAHDAC_AAP1_IMG_DONE 0x00000081 +#define ILAHDAC_AAP2_IMG_DONE 0x00000082 +#define ILAHDAC_ISTR_IMG_DONE 0x00000083 +#define ILAHDAC_GOTOHDA 0x000000ff + +#define HDA_ISTR_DONE (bit32)(ILAHDAC_ISTR_IMG_DONE << 24) +#define HDA_AAP1_DONE (bit32)(ILAHDAC_AAP1_IMG_DONE << 24) +#define HDA_IOP_DONE (bit32)(ILAHDAC_IOP_IMG_DONE << 24) + +#define RB6_ACCESS_REG 0x6A0000 +#define HDAC_EXEC_CMD 0x0002 +#define HDA_C_PA 0xcb +#define HDA_SEQ_ID_BITS 0x00ff0000 +#define HDA_GSM_OFFSET_BITS 0x00FFFFFF +#define MBIC_AAP1_ADDR_BASE 0x060000 +#define MBIC_GSM_SM_BASE 0x04F0000 +#define MBIC_IOP_ADDR_BASE 0x070000 +#define GSM_ADDR_BASE 0x0700000 +#define SPC_TOP_LEVEL_ADDR_BASE 0x000000 +#define GSM_CONFIG_RESET_VALUE 0x00003b00 +#define GPIO_ADDR_BASE 0x00090000 +#define GPIO_GPIO_0_0UTPUT_CTL_OFFSET 0x0000010c + + +/* Scratchpad registers for fatal errors */ +#define SA_FATAL_ERROR_SP1_AAP1_ERR_MASK 0x3 +#define SA_FATAL_ERROR_SP2_IOP_ERR_MASK 0x3 +#define SA_FATAL_ERROR_FATAL_ERROR 0x2 + +/* PCIe Analyzer trigger */ +#define PCIE_TRIGGER_ON_REGISTER_READ V_Host_Scratchpad_2_Register /* PCI trigger on this offset */ + +#define PCI_TRIGGER_INIT_TEST 1 /* Setting adjustable paramater PciTrigger to match this value */ +#define PCI_TRIGGER_OFFSET_MISMATCH 2 /* Setting adjustable paramater PciTrigger to match this value */ +#define PCI_TRIGGER_COAL_IOMB_ERROR 4 /* Setting adjustable paramater PciTrigger to match this value */ +#define PCI_TRIGGER_COAL_INVALID 8 /* Setting adjustable paramater PciTrigger to match this value */ + + + + +/* */ + +enum spc_spcv_offsetmap_e +{ + GEN_MSGU_IBDB_SET=0, + GEN_MSGU_ODR, + GEN_MSGU_ODCR, + GEN_MSGU_SCRATCH_PAD_0, + GEN_MSGU_SCRATCH_PAD_1, + GEN_MSGU_SCRATCH_PAD_2, + GEN_MSGU_SCRATCH_PAD_3, + GEN_MSGU_HOST_SCRATCH_PAD_0, + GEN_MSGU_HOST_SCRATCH_PAD_1, + GEN_MSGU_HOST_SCRATCH_PAD_2, + GEN_MSGU_HOST_SCRATCH_PAD_3, + GEN_MSGU_ODMR, + GEN_PCIE_TRIGGER, + GEN_SPC_REG_RESET, +}; + + +#endif /*__SAHWREG_H__ */ + + + + diff --git a/sys/dev/pms/RefTisa/sallsdk/spc/sainit.c b/sys/dev/pms/RefTisa/sallsdk/spc/sainit.c new file mode 100644 index 000000000000..367c75ab6446 --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/spc/sainit.c @@ -0,0 +1,4664 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +/*******************************************************************************/ +/*! \file sainit.c + * \brief The file implements the functions to initialize the LL layer + * + */ +/******************************************************************************/ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#ifdef SA_ENABLE_TRACE_FUNCTIONS +#ifdef siTraceFileID +#undef siTraceFileID +#endif +#define siTraceFileID 'F' +#endif + +bit32 gLLDebugLevel = 3; + +#if defined(SALLSDK_DEBUG) +bit32 gLLDebugLevelSet = 0; // block reinitialize from updating +bit32 gLLLogFuncDebugLevel = 0; +bit32 gLLSoftResetCounter = 0; +#endif + +bit32 gPollForMissingInt; + +#ifdef FW_EVT_LOG_TST +void *eventLogAddress = 0; +#endif + +extern bit32 gWait_3; +extern bit32 gWait_2; +bit32 gFPGA_TEST = 0; // If set unblock fpga functions + +/******************************************************************************/ +/*! \brief Get the memory and lock requirement from LL layer + * + * Get the memory and lock requirement from LL layer + * + * \param agRoot Handles for this instance of SAS/SATA hardware + * \param swConfig Pointer to the software configuration + * \param memoryRequirement Point to the data structure that holds the different + * chunks of memory that are required + * \param usecsPerTick micro-seconds per tick for the LL layer + * \param maxNumLocks maximum number of locks for the LL layer + * + * \return -void- + * + */ +/*******************************************************************************/ +GLOBAL void saGetRequirements( + agsaRoot_t *agRoot, + agsaSwConfig_t *swConfig, + agsaMemoryRequirement_t *memoryRequirement, + bit32 *usecsPerTick, + bit32 *maxNumLocks + ) +{ + bit32 memoryReqCount = 0; + bit32 i; + static mpiConfig_t mpiConfig; + static mpiMemReq_t mpiMemoryRequirement; + + + /* sanity check */ + SA_ASSERT((agNULL != swConfig), ""); + SA_ASSERT((agNULL != memoryRequirement), ""); + SA_ASSERT((agNULL != usecsPerTick), ""); + SA_ASSERT((agNULL != maxNumLocks), ""); + + si_memset(&mpiMemoryRequirement, 0, sizeof(mpiMemReq_t)); + si_memset(&mpiConfig, 0, sizeof(mpiConfig_t)); + + SA_DBG1(("saGetRequirements:agRoot %p swConfig %p memoryRequirement %p usecsPerTick %p maxNumLocks %p\n",agRoot, swConfig,memoryRequirement,usecsPerTick,maxNumLocks)); + SA_DBG1(("saGetRequirements: usecsPerTick 0x%x (%d)\n",*usecsPerTick,*usecsPerTick)); + + /* Get Resource Requirements for SPC MPI */ + /* Set the default/specified requirements swConfig from TD layer */ + siConfiguration(agRoot, &mpiConfig, agNULL, swConfig); + mpiRequirementsGet(&mpiConfig, &mpiMemoryRequirement); + + /* memory requirement for saRoot, CACHE memory */ + memoryRequirement->agMemory[LLROOT_MEM_INDEX].singleElementLength = sizeof(agsaLLRoot_t); + memoryRequirement->agMemory[LLROOT_MEM_INDEX].numElements = 1; + memoryRequirement->agMemory[LLROOT_MEM_INDEX].totalLength = sizeof(agsaLLRoot_t); + memoryRequirement->agMemory[LLROOT_MEM_INDEX].alignment = sizeof(void *); + memoryRequirement->agMemory[LLROOT_MEM_INDEX].type = AGSA_CACHED_MEM; + memoryReqCount ++; + + SA_DBG1(("saGetRequirements: agMemory[LLROOT_MEM_INDEX] singleElementLength = 0x%x totalLength = 0x%x align = 0x%x type %x\n", + memoryRequirement->agMemory[LLROOT_MEM_INDEX].singleElementLength, + memoryRequirement->agMemory[LLROOT_MEM_INDEX].totalLength, + memoryRequirement->agMemory[LLROOT_MEM_INDEX].alignment, + memoryRequirement->agMemory[LLROOT_MEM_INDEX].type )); + + /* memory requirement for Device Links, CACHE memory */ + memoryRequirement->agMemory[DEVICELINK_MEM_INDEX].singleElementLength = sizeof(agsaDeviceDesc_t); + memoryRequirement->agMemory[DEVICELINK_MEM_INDEX].numElements = swConfig->numDevHandles; + memoryRequirement->agMemory[DEVICELINK_MEM_INDEX].totalLength = sizeof(agsaDeviceDesc_t) + * swConfig->numDevHandles; + memoryRequirement->agMemory[DEVICELINK_MEM_INDEX].alignment = sizeof(void *); + memoryRequirement->agMemory[DEVICELINK_MEM_INDEX].type = AGSA_CACHED_MEM; + memoryReqCount ++; + SA_DBG1(("saGetRequirements: agMemory[DEVICELINK_MEM_INDEX] singleElementLength = 0x%x totalLength = 0x%x align = 0x%x type %x\n", + memoryRequirement->agMemory[DEVICELINK_MEM_INDEX].singleElementLength, + memoryRequirement->agMemory[DEVICELINK_MEM_INDEX].totalLength, + memoryRequirement->agMemory[DEVICELINK_MEM_INDEX].alignment, + memoryRequirement->agMemory[DEVICELINK_MEM_INDEX].type )); + + /* memory requirement for IORequest Links, CACHE memory */ + memoryRequirement->agMemory[IOREQLINK_MEM_INDEX].singleElementLength = sizeof(agsaIORequestDesc_t); + /* + Add SA_RESERVED_REQUEST_COUNT to guarantee quality of service + */ + memoryRequirement->agMemory[IOREQLINK_MEM_INDEX].numElements = swConfig->maxActiveIOs + SA_RESERVED_REQUEST_COUNT; + memoryRequirement->agMemory[IOREQLINK_MEM_INDEX].totalLength = sizeof(agsaIORequestDesc_t) * + memoryRequirement->agMemory[IOREQLINK_MEM_INDEX].numElements; + memoryRequirement->agMemory[IOREQLINK_MEM_INDEX].alignment = sizeof(void *); + memoryRequirement->agMemory[IOREQLINK_MEM_INDEX].type = AGSA_CACHED_MEM; + memoryReqCount ++; + + SA_DBG1(("saGetRequirements: agMemory[IOREQLINK_MEM_INDEX] singleElementLength = 0x%x totalLength = 0x%x align = 0x%x type %x\n", + memoryRequirement->agMemory[IOREQLINK_MEM_INDEX].singleElementLength, + memoryRequirement->agMemory[IOREQLINK_MEM_INDEX].totalLength, + memoryRequirement->agMemory[IOREQLINK_MEM_INDEX].alignment, + memoryRequirement->agMemory[IOREQLINK_MEM_INDEX].type )); + + /* memory requirement for Timer Links, CACHE memory */ + memoryRequirement->agMemory[TIMERLINK_MEM_INDEX].singleElementLength = sizeof(agsaTimerDesc_t); + memoryRequirement->agMemory[TIMERLINK_MEM_INDEX].numElements = NUM_TIMERS; + memoryRequirement->agMemory[TIMERLINK_MEM_INDEX].totalLength = sizeof(agsaTimerDesc_t) * NUM_TIMERS; + memoryRequirement->agMemory[TIMERLINK_MEM_INDEX].alignment = sizeof(void *); + memoryRequirement->agMemory[TIMERLINK_MEM_INDEX].type = AGSA_CACHED_MEM; + memoryReqCount ++; + SA_DBG1(("saGetRequirements: agMemory[TIMERLINK_MEM_INDEX] singleElementLength = 0x%x totalLength = 0x%x align = 0x%x type %x\n", + memoryRequirement->agMemory[TIMERLINK_MEM_INDEX].singleElementLength, + memoryRequirement->agMemory[TIMERLINK_MEM_INDEX].totalLength, + memoryRequirement->agMemory[TIMERLINK_MEM_INDEX].alignment, + memoryRequirement->agMemory[TIMERLINK_MEM_INDEX].type )); + +#ifdef SA_ENABLE_TRACE_FUNCTIONS + + /* memory requirement for LL trace memory */ + memoryRequirement->agMemory[LL_FUNCTION_TRACE].singleElementLength = 1; + memoryRequirement->agMemory[LL_FUNCTION_TRACE].numElements = swConfig->TraceBufferSize; + memoryRequirement->agMemory[LL_FUNCTION_TRACE].totalLength = swConfig->TraceBufferSize; + memoryRequirement->agMemory[LL_FUNCTION_TRACE].alignment = sizeof(void *); + memoryRequirement->agMemory[LL_FUNCTION_TRACE].type = AGSA_CACHED_MEM; + memoryReqCount ++; + + SA_DBG1(("saGetRequirements: agMemory[LL_FUNCTION_TRACE] singleElementLength = 0x%x totalLength = 0x%x align = 0x%x type %x\n", + memoryRequirement->agMemory[LL_FUNCTION_TRACE].singleElementLength, + memoryRequirement->agMemory[LL_FUNCTION_TRACE].totalLength, + memoryRequirement->agMemory[LL_FUNCTION_TRACE].alignment, + memoryRequirement->agMemory[LL_FUNCTION_TRACE].type )); + +#endif /* END SA_ENABLE_TRACE_FUNCTIONS */ + +#ifdef FAST_IO_TEST + { + agsaMem_t *agMemory = memoryRequirement->agMemory; + + /* memory requirement for Super IO CACHE memory */ + agMemory[LL_FAST_IO].singleElementLength = sizeof(saFastRequest_t); + agMemory[LL_FAST_IO].numElements = LL_FAST_IO_SIZE; + agMemory[LL_FAST_IO].totalLength = LL_FAST_IO_SIZE * + agMemory[LL_FAST_IO].singleElementLength; + agMemory[LL_FAST_IO].alignment = sizeof(void*); + agMemory[LL_FAST_IO].type = AGSA_CACHED_MEM; + memoryReqCount ++; + + SA_DBG1(("saGetRequirements: agMemory[LL_FAST_IO] singleElementLength = 0x%x totalLength = 0x%x align = 0x%x type %x\n", + memoryRequirement->agMemory[LL_FAST_IO].singleElementLength, + memoryRequirement->agMemory[LL_FAST_IO].totalLength, + memoryRequirement->agMemory[LL_FAST_IO].alignment, + memoryRequirement->agMemory[LL_FAST_IO].type )); + + } +#endif + +#ifdef SA_ENABLE_HDA_FUNCTIONS + { + agsaMem_t *agMemory = memoryRequirement->agMemory; + + /* memory requirement for HDA FW image */ + agMemory[HDA_DMA_BUFFER].singleElementLength = (1024 * 1024); /* must be greater than size of aap1 fw image */ + agMemory[HDA_DMA_BUFFER].numElements = 1; + agMemory[HDA_DMA_BUFFER].totalLength = agMemory[HDA_DMA_BUFFER].numElements * + agMemory[HDA_DMA_BUFFER].singleElementLength; + agMemory[HDA_DMA_BUFFER].alignment = 32; + agMemory[HDA_DMA_BUFFER].type = AGSA_DMA_MEM; + memoryReqCount ++; + SA_DBG1(("saGetRequirements: agMemory[HDA_DMA_BUFFER] singleElementLength = 0x%x totalLength = 0x%x align = 0x%x type %x\n", + memoryRequirement->agMemory[HDA_DMA_BUFFER].singleElementLength, + memoryRequirement->agMemory[HDA_DMA_BUFFER].totalLength, + memoryRequirement->agMemory[HDA_DMA_BUFFER].alignment, + memoryRequirement->agMemory[HDA_DMA_BUFFER].type )); + } +#endif /* SA_ENABLE_HDA_FUNCTIONS */ + + /* memory requirement for MPI MSGU layer, DMA memory */ + for ( i = 0; i < mpiMemoryRequirement.count; i ++ ) + { + memoryRequirement->agMemory[memoryReqCount].singleElementLength = mpiMemoryRequirement.region[i].elementSize; + memoryRequirement->agMemory[memoryReqCount].numElements = mpiMemoryRequirement.region[i].numElements; + memoryRequirement->agMemory[memoryReqCount].totalLength = mpiMemoryRequirement.region[i].totalLength; + memoryRequirement->agMemory[memoryReqCount].alignment = mpiMemoryRequirement.region[i].alignment; + memoryRequirement->agMemory[memoryReqCount].type = mpiMemoryRequirement.region[i].type; + SA_DBG1(("saGetRequirements:MPI agMemory[%d] singleElementLength = 0x%x totalLength = 0x%x align = 0x%x type %x\n", + memoryReqCount, + memoryRequirement->agMemory[memoryReqCount].singleElementLength, + memoryRequirement->agMemory[memoryReqCount].totalLength, + memoryRequirement->agMemory[memoryReqCount].alignment, + memoryRequirement->agMemory[memoryReqCount].type )); + memoryReqCount ++; + } + + + /* requirement for locks */ + if (swConfig->param3 == agNULL) + { + *maxNumLocks = (LL_IOREQ_IBQ_LOCK + AGSA_MAX_INBOUND_Q ); + SA_DBG1(("saGetRequirements: param3 == agNULL maxNumLocks %d\n", *maxNumLocks )); + } + else + { + agsaQueueConfig_t *queueConfig; + queueConfig = (agsaQueueConfig_t *)swConfig->param3; + *maxNumLocks = (LL_IOREQ_IBQ_LOCK_PARM + queueConfig->numInboundQueues ); + SA_DBG1(("saGetRequirements: maxNumLocks %d\n", *maxNumLocks )); + } + + + /* setup the time tick */ + *usecsPerTick = SA_USECS_PER_TICK; + + SA_ASSERT(memoryReqCount < AGSA_NUM_MEM_CHUNKS, "saGetRequirements: Exceed max number of memory place holder"); + + /* set up memory requirement count */ + memoryRequirement->count = memoryReqCount; + + swConfig->legacyInt_X = 1; + swConfig->max_MSI_InterruptVectors = 32; + swConfig->max_MSIX_InterruptVectors = 64;//16; + + SA_DBG1(("saGetRequirements: swConfig->stallUsec %d\n",swConfig->stallUsec )); + +#ifdef SA_CONFIG_MDFD_REGISTRY + SA_DBG1(("saGetRequirements: swConfig->disableMDF %d\n",swConfig->disableMDF)); +#endif /*SA_CONFIG_MDFD_REGISTRY*/ + /*SA_DBG1(("saGetRequirements: swConfig->enableDIF %d\n",swConfig->enableDIF ));*/ + /*SA_DBG1(("saGetRequirements: swConfig->enableEncryption %d\n",swConfig->enableEncryption ));*/ +#ifdef SA_ENABLE_HDA_FUNCTIONS + swConfig->hostDirectAccessSupport = 1; + swConfig->hostDirectAccessMode = 0; +#else + swConfig->hostDirectAccessSupport = 0; + swConfig->hostDirectAccessMode = 0; +#endif + +} + +/******************************************************************************/ +/*! \brief Initialize the Hardware + * + * Initialize the Hardware + * + * \param agRoot Handles for this instance of SAS/SATA hardware + * \param memoryAllocated Point to the data structure that holds the different + chunks of memory that are required + * \param hwConfig Pointer to the hardware configuration + * \param swConfig Pointer to the software configuration + * \param usecsPerTick micro-seconds per tick for the LL layer + * + * \return If initialization is successful + * - \e AGSA_RC_SUCCESS initialization is successful + * - \e AGSA_RC_FAILURE initialization is not successful + */ +/*******************************************************************************/ +GLOBAL bit32 saInitialize( + agsaRoot_t *agRoot, + agsaMemoryRequirement_t *memoryAllocated, + agsaHwConfig_t *hwConfig, + agsaSwConfig_t *swConfig, + bit32 usecsPerTick + ) +{ + agsaLLRoot_t *saRoot; + agsaDeviceDesc_t *pDeviceDesc; + agsaIORequestDesc_t *pRequestDesc; + agsaTimerDesc_t *pTimerDesc; + agsaPort_t *pPort; + agsaPortMap_t *pPortMap; + agsaDeviceMap_t *pDeviceMap; + agsaIOMap_t *pIOMap; + bit32 maxNumIODevices; + bit32 i, j; + static mpiMemReq_t mpiMemoryAllocated; + bit32 Tried_NO_HDA = agFALSE; + bit32 Double_Reset_HDA = agFALSE; + bit32 ret = AGSA_RC_SUCCESS; +#ifdef FAST_IO_TEST + void *fr; /* saFastRequest_t */ + bit32 size; + bit32 alignment; +#endif + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + SA_ASSERT((agNULL != memoryAllocated), ""); + SA_ASSERT((agNULL != hwConfig), ""); + SA_ASSERT((agNULL != swConfig), ""); + SA_ASSERT((LLROOT_MEM_INDEX < memoryAllocated->count), ""); + SA_ASSERT((DEVICELINK_MEM_INDEX < memoryAllocated->count), ""); + SA_ASSERT((IOREQLINK_MEM_INDEX < memoryAllocated->count), ""); + SA_ASSERT((TIMERLINK_MEM_INDEX < memoryAllocated->count), ""); + + si_memset(&mpiMemoryAllocated, 0, sizeof(mpiMemReq_t)); + + si_macro_check(agRoot); + + SA_DBG1(("saInitialize: WAIT_INCREMENT %d\n", WAIT_INCREMENT )); + SA_DBG1(("saInitialize: usecsPerTick %d\n", usecsPerTick )); + if(! smIS_SPC(agRoot)) + { + if(! smIS_SPCV(agRoot)) + { + SA_DBG1(("saInitialize: ossaHwRegReadConfig32 ID reads as %08X\n", ossaHwRegReadConfig32(agRoot,0 ) )); + SA_DBG1(("saInitialize: expect %08X or %08X or\n", VEN_DEV_SPCV, VEN_DEV_SPCVE)); + SA_DBG1(("saInitialize: expect %08X or %08X or\n", VEN_DEV_SPCVP, VEN_DEV_SPCVEP)); + SA_DBG1(("saInitialize: expect %08X or %08X\n", VEN_DEV_ADAPVEP, VEN_DEV_ADAPVP)); + return AGSA_RC_FAILURE; + } + } + + if( smIS_SPC(agRoot) && smIS_SPCV(agRoot)) + { + SA_DBG1(("saInitialize: Macro error !smIS_SPC %d smIS_SPCv %d smIS_SFC %d\n",smIS_SPC(agRoot),smIS_SPCV(agRoot), smIS_SFC(agRoot) )); + return AGSA_RC_FAILURE; + } + + /* Check the memory allocated */ + for ( i = 0; i < memoryAllocated->count; i ++ ) + { + /* If memory allocation failed */ + if (memoryAllocated->agMemory[i].singleElementLength && + memoryAllocated->agMemory[i].numElements) + { + if ( (0 != memoryAllocated->agMemory[i].numElements) + && (0 == memoryAllocated->agMemory[i].totalLength) ) + { + /* return failure */ + SA_DBG1(("saInitialize:AGSA_RC_FAILURE Memory[%d] singleElementLength = 0x%x numElements = 0x%x NOT allocated\n", + i, + memoryAllocated->agMemory[i].singleElementLength, + memoryAllocated->agMemory[i].numElements)); + ret = AGSA_RC_FAILURE; + return ret; + } + else + { + SA_DBG1(("saInitialize: Memory[%d] singleElementLength = 0x%x numElements = 0x%x allocated %p\n", + i, + memoryAllocated->agMemory[i].singleElementLength, + memoryAllocated->agMemory[i].numElements, + memoryAllocated->agMemory[i].virtPtr)); + } + } + } + + /* Get the saRoot memory address */ + saRoot = (agsaLLRoot_t *) (memoryAllocated->agMemory[LLROOT_MEM_INDEX].virtPtr); + SA_ASSERT((agNULL != saRoot), "saRoot"); + if(agNULL == saRoot) + { + SA_DBG1(("saInitialize:AGSA_RC_FAILURE saRoot\n")); + return AGSA_RC_FAILURE; + } + + agRoot->sdkData = (void *) saRoot; + + SA_DBG1(("saInitialize: saRoot %p\n",saRoot)); + + if ( (memoryAllocated != &saRoot->memoryAllocated) || + (hwConfig != &saRoot->hwConfig) || + (swConfig != &saRoot->swConfig) ) + { + agsaMemoryRequirement_t *memA = &saRoot->memoryAllocated; + agsaHwConfig_t *hwC = &saRoot->hwConfig; + agsaSwConfig_t *swC = &saRoot->swConfig; + + /* Copy data here */ + + *memA = *memoryAllocated; + *hwC = *hwConfig; + *swC = *swConfig; + } + + +#if defined(SALLSDK_DEBUG) + if(gLLDebugLevelSet == 0) + { + gLLDebugLevelSet = 1; + gLLDebugLevel = swConfig->sallDebugLevel & 0xF; + SA_DBG1(("saInitialize: gLLDebugLevel %x\n",gLLDebugLevel)); + } +#endif /* SALLSDK_DEBUG */ + +#ifdef SA_ENABLE_TRACE_FUNCTIONS + + saRoot->TraceBufferLength = memoryAllocated->agMemory[LL_FUNCTION_TRACE].totalLength; + saRoot->TraceBuffer = memoryAllocated->agMemory[LL_FUNCTION_TRACE].virtPtr; + + siEnableTracing ( agRoot ); +/* +*/ + +#endif /* SA_ENABLE_TRACE_FUNCTIONS */ + +#ifdef FAST_IO_TEST + { + agsaMem_t *agMemory = memoryAllocated->agMemory; + + /* memory requirement for Super IO CACHE memory */ + size = sizeof(saRoot->freeFastReq) / sizeof(saRoot->freeFastReq[0]); + + SA_ASSERT(size == agMemory[LL_FAST_IO].numElements, ""); + SA_ASSERT(agMemory[LL_FAST_IO].virtPtr, ""); + SA_ASSERT((agMemory[LL_FAST_IO].singleElementLength == + sizeof(saFastRequest_t)) && + (agMemory[LL_FAST_IO].numElements == LL_FAST_IO_SIZE) && + (agMemory[LL_FAST_IO].totalLength == agMemory[LL_FAST_IO].numElements * + agMemory[LL_FAST_IO].singleElementLength), ""); + + for (i = 0, alignment = agMemory[LL_FAST_IO].alignment, + fr = agMemory[LL_FAST_IO].virtPtr; + i < size; i++, + fr = (void*)((bitptr)fr + (bitptr)(((bit32)sizeof(saFastRequest_t) + + alignment - 1) & ~(alignment - 1)))) + { + saRoot->freeFastReq[i] = fr; + } + saRoot->freeFastIdx = size; + } +#endif /* FAST_IO_TEST*/ + + smTraceFuncEnter(hpDBG_VERY_LOUD, "m1"); + + SA_DBG1(("saInitialize: swConfig->PortRecoveryResetTimer %x\n",swConfig->PortRecoveryResetTimer )); + + SA_DBG1(("saInitialize: hwDEVICE_ID_VENDID 0x%08x\n", ossaHwRegReadConfig32(agRoot,0))); + SA_DBG1(("saInitialize: CFGSTAT CFGCMD 0x%08x\n", ossaHwRegReadConfig32(agRoot,4))); + SA_DBG1(("saInitialize: CLSCODE REVID 0x%08x\n", ossaHwRegReadConfig32(agRoot,8))); + SA_DBG1(("saInitialize: BIST DT HDRTYPE LATTIM CLSIZE 0x%08x\n", ossaHwRegReadConfig32(agRoot,12))); + SA_DBG1(("saInitialize: hwSVID 0x%08x\n", ossaHwRegReadConfig32(agRoot,44))); + + +#ifdef SA_ENABLE_PCI_TRIGGER + + SA_DBG1(("saInitialize: SA_ENABLE_PCI_TRIGGER a 0x%08x %p\n", saRoot->swConfig.PCI_trigger,&saRoot->swConfig.PCI_trigger)); + + if( saRoot->swConfig.PCI_trigger & PCI_TRIGGER_INIT_TEST ) + { + SA_DBG1(("saInitialize: SA_ENABLE_PCI_TRIGGER 0x%08x %p\n", saRoot->swConfig.PCI_trigger,&saRoot->swConfig.PCI_trigger)); + saRoot->swConfig.PCI_trigger &= ~PCI_TRIGGER_INIT_TEST; + siPCITriger(agRoot); + } +#endif /* SA_ENABLE_PCI_TRIGGER */ + + + saRoot->ChipId = (ossaHwRegReadConfig32(agRoot,0) & 0xFFFF0000); + + SA_DBG1(("saInitialize: saRoot->ChipId 0x%08x\n", saRoot->ChipId)); + siUpdateBarOffsetTable(agRoot,saRoot->ChipId); + + if(saRoot->ChipId == VEN_DEV_SPC) + { + if(! smIS_SPC(agRoot)) + { + SA_DBG1(("saInitialize: smIS_SPC macro fail !!!!\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "m1"); + return AGSA_RC_FAILURE; + } + + SA_DBG1(("saInitialize: SPC \n" )); + } + else if(saRoot->ChipId == VEN_DEV_HIL ) + { + SA_DBG1(("saInitialize: SPC HIL\n" )); + if(! smIS_SPC(agRoot)) + { + SA_DBG1(("saInitialize: smIS_SPC macro fail !!!!\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "m1"); + return AGSA_RC_FAILURE; + } + } + else if(saRoot->ChipId == VEN_DEV_SPCV) + { + SA_DBG1(("saInitialize: SPC V\n" )); + if(! smIS_SPCV(agRoot)) + { + SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "m1"); + return AGSA_RC_FAILURE; + } + } + else if(saRoot->ChipId == VEN_DEV_SPCVE) + { + SA_DBG1(("saInitialize: SPC VE\n" )); + if(! smIS_SPCV(agRoot)) + { + SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "m1"); + return AGSA_RC_FAILURE; + } + } + else if(saRoot->ChipId == VEN_DEV_SPCVP) + { + SA_DBG1(("saInitialize: SPC VP\n" )); + if(! smIS_SPCV(agRoot)) + { + SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "m1"); + return AGSA_RC_FAILURE; + } + } + else if(saRoot->ChipId == VEN_DEV_SPCVEP) + { + SA_DBG1(("saInitialize: SPC VEP\n" )); + if(! smIS_SPCV(agRoot)) + { + SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'f', "m1"); + return AGSA_RC_FAILURE; + } + } + else if(saRoot->ChipId == VEN_DEV_ADAPVP) + { + SA_DBG1(("saInitialize: Adaptec 8088\n" )); + } + else if(saRoot->ChipId == VEN_DEV_ADAPVEP) + { + SA_DBG1(("saInitialize: Adaptec 8089\n" )); + } + else if(saRoot->ChipId == VEN_DEV_SPC12V) + { + SA_DBG1(("saInitialize: SPC 12V\n" )); + if(! smIS_SPCV(agRoot)) + { + SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'g', "m1"); + return AGSA_RC_FAILURE; + } + } + else if(saRoot->ChipId == VEN_DEV_SPC12VE) + { + SA_DBG1(("saInitialize: SPC 12VE\n" )); + if(! smIS_SPCV(agRoot)) + { + SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'h', "m1"); + return AGSA_RC_FAILURE; + } + } + else if(saRoot->ChipId == VEN_DEV_SPC12VP) + { + SA_DBG1(("saInitialize: SPC 12VP\n" )); + if(! smIS_SPCV(agRoot)) + { + SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'i', "m1"); + return AGSA_RC_FAILURE; + } + } + else if(saRoot->ChipId == VEN_DEV_SPC12VEP) + { + SA_DBG1(("saInitialize: SPC 12VEP\n" )); + if(! smIS_SPCV(agRoot)) + { + SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'j', "m1"); + return AGSA_RC_FAILURE; + } + } + else if(saRoot->ChipId == VEN_DEV_SPC12ADP) + { + SA_DBG1(("saInitialize: SPC 12ADP\n" )); + if(! smIS_SPCV(agRoot)) + { + SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'k', "m1"); + return AGSA_RC_FAILURE; + } + } + else if(saRoot->ChipId == VEN_DEV_SPC12ADPE) + { + SA_DBG1(("saInitialize: SPC 12ADPE\n" )); + if(! smIS_SPCV(agRoot)) + { + SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'l', "m1"); + return AGSA_RC_FAILURE; + } + } + else if(saRoot->ChipId == VEN_DEV_SPC12ADPP) + { + SA_DBG1(("saInitialize: SPC 12ADPP\n" )); + if(! smIS_SPCV(agRoot)) + { + SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'm', "m1"); + return AGSA_RC_FAILURE; + } + } + else if(saRoot->ChipId == VEN_DEV_SPC12ADPEP) + { + SA_DBG1(("saInitialize: SPC 12ADPEP\n" )); + if(! smIS_SPCV(agRoot)) + { + SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'n', "m1"); + return AGSA_RC_FAILURE; + } + } + else if(saRoot->ChipId == VEN_DEV_SPC12SATA) + { + SA_DBG1(("saInitialize: SPC12SATA\n" )); + if(! smIS_SPCV(agRoot)) + { + SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'o', "m1"); + return AGSA_RC_FAILURE; + } + } + else if(saRoot->ChipId == VEN_DEV_9015) + { + SA_DBG1(("saInitialize: SPC 12V FPGA\n" )); + if(! smIS_SPCV(agRoot)) + { + SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'p', "m1"); + return AGSA_RC_FAILURE; + } + } + else if(saRoot->ChipId == VEN_DEV_9060) + { + SA_DBG1(("saInitialize: SPC 12V FPGA B\n" )); + if(! smIS_SPCV(agRoot)) + { + SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'q', "m1"); + return AGSA_RC_FAILURE; + } + } + else if(saRoot->ChipId == VEN_DEV_SFC) + { + SA_DBG1(("saInitialize: SFC \n" )); + } + else + { + SA_DBG1(("saInitialize saRoot->ChipId %8X expect %8X or %8X\n", saRoot->ChipId,VEN_DEV_SPC, VEN_DEV_SPCV)); + SA_ASSERT(0, "ChipId"); + smTraceFuncExit(hpDBG_VERY_LOUD, 'r', "m1"); + return AGSA_RC_FAILURE; + } + + if( smIS_SPC(agRoot)) + { + SA_DBG1(("saInitialize: Rev is A %d B %d C %d\n",smIsCfgSpcREV_A(agRoot),smIsCfgSpcREV_B(agRoot),smIsCfgSpcREV_C(agRoot))); + } + else + { + SA_DBG1(("saInitialize: Rev is A %d B %d C %d\n",smIsCfgVREV_A(agRoot),smIsCfgVREV_B(agRoot),smIsCfgVREV_C(agRoot))); + } + + if( smIS_SPC(agRoot)) + { + SA_DBG1(("saInitialize: LINK_CTRL 0x%08x Speed 0x%X Lanes 0x%X \n", ossaHwRegReadConfig32(agRoot,128), + ((ossaHwRegReadConfig32(agRoot,128) & 0x000F0000) >> 16), + ((ossaHwRegReadConfig32(agRoot,128) & 0x0FF00000) >> 20) )); + } + else + { + SA_DBG1(("saInitialize: LINK_CTRL 0x%08x Speed 0x%X Lanes 0x%X \n", ossaHwRegReadConfig32(agRoot,208), + ((ossaHwRegReadConfig32(agRoot,208) & 0x000F0000) >> 16), + ((ossaHwRegReadConfig32(agRoot,208) & 0x0FF00000) >> 20) )); + } + + SA_DBG1(("saInitialize: V_SoftResetRegister %08X\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_SoftResetRegister ))); + +/* + SA_DBG1(("saInitialize:TOP_BOOT_STRAP STRAP_BIT %X\n", ossaHwRegReadExt(agRoot, PCIBAR1, 0) )); + + SA_DBG1(("SPC_REG_TOP_DEVICE_ID %8X expect %08X\n", ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_TOP_DEVICE_ID), SPC_TOP_DEVICE_ID)); + SA_DBG1(("SPC_REG_TOP_DEVICE_ID %8X expect %08X\n", siHalRegReadExt( agRoot, GEN_SPC_REG_TOP_DEVICE_ID,SPC_REG_TOP_DEVICE_ID ) , SPC_TOP_DEVICE_ID)); + + SA_DBG1(("SPC_REG_TOP_BOOT_STRAP %8X expect %08X\n", ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_TOP_BOOT_STRAP), SPC_TOP_BOOT_STRAP)); + + SA_DBG1(("swConfig->numSASDevHandles =%d\n", swConfig->numDevHandles)); +*/ + smTrace(hpDBG_VERY_LOUD,"29",swConfig->numDevHandles); + /* TP:29 swConfig->numDevHandles */ + + /* Setup Device link */ + /* Save the information of allocated device Link memory */ + saRoot->deviceLinkMem = memoryAllocated->agMemory[DEVICELINK_MEM_INDEX]; + if(agNULL == saRoot->deviceLinkMem.virtPtr) + { + SA_ASSERT(0, "deviceLinkMem"); + smTraceFuncExit(hpDBG_VERY_LOUD, 'q', "m1"); + return AGSA_RC_FAILURE; + } + + si_memset(saRoot->deviceLinkMem.virtPtr, 0, saRoot->deviceLinkMem.totalLength); + SA_DBG2(("saInitialize: [%d] saRoot->deviceLinkMem VirtPtr=%p PhysicalLo=%x Count=%x Total=%x type %x\n", + DEVICELINK_MEM_INDEX, + saRoot->deviceLinkMem.virtPtr, + saRoot->deviceLinkMem.phyAddrLower, + saRoot->deviceLinkMem.numElements, + saRoot->deviceLinkMem.totalLength, + saRoot->deviceLinkMem.type)); + + maxNumIODevices = swConfig->numDevHandles; + SA_DBG2(("saInitialize: maxNumIODevices=%d, swConfig->numDevHandles=%d \n", + maxNumIODevices, + swConfig->numDevHandles)); + +#ifdef SA_ENABLE_PCI_TRIGGER + SA_DBG1(("saInitialize: swConfig->PCI_trigger= 0x%x\n", swConfig->PCI_trigger)); +#endif /* SA_ENABLE_PCI_TRIGGER */ + + /* Setup free IO Devices link list */ + saLlistInitialize(&(saRoot->freeDevicesList)); + for ( i = 0; i < (bit32) maxNumIODevices; i ++ ) + { + /* get the pointer to the device descriptor */ + pDeviceDesc = (agsaDeviceDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->deviceLinkMem), i); + /* Initialize device descriptor */ + saLlinkInitialize(&(pDeviceDesc->linkNode)); + + pDeviceDesc->initiatorDevHandle.osData = agNULL; + pDeviceDesc->initiatorDevHandle.sdkData = agNULL; + pDeviceDesc->targetDevHandle.osData = agNULL; + pDeviceDesc->targetDevHandle.sdkData = agNULL; + pDeviceDesc->deviceType = SAS_SATA_UNKNOWN_DEVICE; + pDeviceDesc->pPort = agNULL; + pDeviceDesc->DeviceMapIndex = 0; + + saLlistInitialize(&(pDeviceDesc->pendingIORequests)); + + /* Add the device descriptor to the free IO device link list */ + saLlistAdd(&(saRoot->freeDevicesList), &(pDeviceDesc->linkNode)); + } + + /* Setup IO Request link */ + /* Save the information of allocated IO Request Link memory */ + saRoot->IORequestMem = memoryAllocated->agMemory[IOREQLINK_MEM_INDEX]; + si_memset(saRoot->IORequestMem.virtPtr, 0, saRoot->IORequestMem.totalLength); + + SA_DBG2(("saInitialize: [%d] saRoot->IORequestMem VirtPtr=%p PhysicalLo=%x Count=%x Total=%x type %x\n", + IOREQLINK_MEM_INDEX, + saRoot->IORequestMem.virtPtr, + saRoot->IORequestMem.phyAddrLower, + saRoot->IORequestMem.numElements, + saRoot->IORequestMem.totalLength, + saRoot->IORequestMem.type)); + + /* Setup free IO Request link list */ + saLlistIOInitialize(&(saRoot->freeIORequests)); + saLlistIOInitialize(&(saRoot->freeReservedRequests)); + for ( i = 0; i < swConfig->maxActiveIOs; i ++ ) + { + /* get the pointer to the request descriptor */ + pRequestDesc = (agsaIORequestDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->IORequestMem), i); + /* Initialize request descriptor */ + saLlinkInitialize(&(pRequestDesc->linkNode)); + + pRequestDesc->valid = agFALSE; + pRequestDesc->requestType = AGSA_REQ_TYPE_UNKNOWN; + pRequestDesc->pIORequestContext = agNULL; + pRequestDesc->HTag = i; + pRequestDesc->pDevice = agNULL; + pRequestDesc->pPort = agNULL; + + /* Add the request descriptor to the free Reserved Request link list */ + /* SMP request must get service so reserve one request when first SMP completes */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequestDesc->linkNode)); + } + else + { + /* Add the request descriptor to the free IO Request link list */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequestDesc->linkNode)); + } + + } + + /* Setup timer link */ + /* Save the information of allocated timer Link memory */ + saRoot->timerLinkMem = memoryAllocated->agMemory[TIMERLINK_MEM_INDEX]; + si_memset(saRoot->timerLinkMem.virtPtr, 0, saRoot->timerLinkMem.totalLength); + SA_DBG2(("saInitialize: [%d] saRoot->timerLinkMem VirtPtr=%p PhysicalLo=%x Count=%x Total=%x type %x\n", + TIMERLINK_MEM_INDEX, + saRoot->timerLinkMem.virtPtr, + saRoot->timerLinkMem.phyAddrLower, + saRoot->timerLinkMem.numElements, + saRoot->timerLinkMem.totalLength, + saRoot->timerLinkMem.type )); + + /* Setup free timer link list */ + saLlistInitialize(&(saRoot->freeTimers)); + for ( i = 0; i < NUM_TIMERS; i ++ ) + { + /* get the pointer to the timer descriptor */ + pTimerDesc = (agsaTimerDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->timerLinkMem), i); + /* Initialize timer descriptor */ + saLlinkInitialize(&(pTimerDesc->linkNode)); + + pTimerDesc->valid = agFALSE; + pTimerDesc->timeoutTick = 0; + pTimerDesc->pfnTimeout = agNULL; + pTimerDesc->Event = 0; + pTimerDesc->pParm = agNULL; + + /* Add the timer descriptor to the free timer link list */ + saLlistAdd(&(saRoot->freeTimers), &(pTimerDesc->linkNode)); + } + /* Setup valid timer link list */ + saLlistInitialize(&(saRoot->validTimers)); + + /* Setup Phys */ + /* Setup PhyCount */ + saRoot->phyCount = (bit8) hwConfig->phyCount; + /* Init Phy data structure */ + for ( i = 0; i < saRoot->phyCount; i ++ ) + { + saRoot->phys[i].pPort = agNULL; + saRoot->phys[i].phyId = (bit8) i; + + /* setup phy status is PHY_STOPPED */ + PHY_STATUS_SET(&(saRoot->phys[i]), PHY_STOPPED); + } + + /* Setup Ports */ + /* Setup PortCount */ + saRoot->portCount = saRoot->phyCount; + /* Setup free port link list */ + saLlistInitialize(&(saRoot->freePorts)); + for ( i = 0; i < saRoot->portCount; i ++ ) + { + /* get the pointer to the port */ + pPort = &(saRoot->ports[i]); + /* Initialize port */ + saLlinkInitialize(&(pPort->linkNode)); + + pPort->portContext.osData = agNULL; + pPort->portContext.sdkData = pPort; + pPort->portId = 0; + pPort->portIdx = (bit8) i; + pPort->status = PORT_NORMAL; + + for ( j = 0; j < saRoot->phyCount; j ++ ) + { + pPort->phyMap[j] = agFALSE; + } + + saLlistInitialize(&(pPort->listSASATADevices)); + + /* Add the port to the free port link list */ + saLlistAdd(&(saRoot->freePorts), &(pPort->linkNode)); + } + /* Setup valid port link list */ + saLlistInitialize(&(saRoot->validPorts)); + + /* Init sysIntsActive - default is interrupt enable */ + saRoot->sysIntsActive = agFALSE; + + /* setup timer tick granunarity */ + saRoot->usecsPerTick = usecsPerTick; + + /* setup smallest timer increment for stall */ + saRoot->minStallusecs = swConfig->stallUsec; + + SA_DBG1(("saInitialize: WAIT_INCREMENT %d\n" ,WAIT_INCREMENT )); + if (0 == WAIT_INCREMENT) + { + saRoot->minStallusecs = WAIT_INCREMENT_DEFAULT; + } + + /* initialize LL timer tick */ + saRoot->timeTick = 0; + + /* initialize device (de)registration callback fns */ + saRoot->DeviceRegistrationCB = agNULL; + saRoot->DeviceDeregistrationCB = agNULL; + + /* Initialize the PortMap for port context */ + for ( i = 0; i < saRoot->portCount; i ++ ) + { + pPortMap = &(saRoot->PortMap[i]); + + pPortMap->PortContext = agNULL; + pPortMap->PortID = PORT_MARK_OFF; + pPortMap->PortStatus = PORT_NORMAL; + saRoot->autoDeregDeviceflag[i] = 0; + } + + /* Initialize the DeviceMap for device handle */ + for ( i = 0; i < MAX_IO_DEVICE_ENTRIES; i ++ ) + { + pDeviceMap = &(saRoot->DeviceMap[i]); + + pDeviceMap->DeviceHandle = agNULL; + pDeviceMap->DeviceIdFromFW = i; + } + + /* Initialize the IOMap for IOrequest */ + for ( i = 0; i < MAX_ACTIVE_IO_REQUESTS; i ++ ) + { + pIOMap = &(saRoot->IOMap[i]); + + pIOMap->IORequest = agNULL; + pIOMap->Tag = MARK_OFF; + } + + /* setup mpi configuration */ + if (!swConfig->param3) + { + /* default configuration */ + siConfiguration(agRoot, &saRoot->mpiConfig, hwConfig, swConfig); + } + else + { + /* get from TD layer and save it */ + agsaQueueConfig_t *dCFG = &saRoot->QueueConfig; + agsaQueueConfig_t *sCFG = (agsaQueueConfig_t *)swConfig->param3; + + if (dCFG != sCFG) + { + *dCFG = *sCFG; + + if ((hwConfig->hwInterruptCoalescingTimer) || (hwConfig->hwInterruptCoalescingControl)) + { + for ( i = 0; i < sCFG->numOutboundQueues; i ++ ) + { + /* disable FW assisted coalescing */ + sCFG->outboundQueues[i].interruptDelay = 0; + sCFG->outboundQueues[i].interruptCount = 0; + } + + if(smIS_SPC(agRoot)) + { + if (hwConfig->hwInterruptCoalescingTimer == 0) + { + hwConfig->hwInterruptCoalescingTimer = 1; + SA_DBG1(("saInitialize:InterruptCoalescingTimer should not be zero. Force to 1\n")); + } + } + } + ret = siConfiguration(agRoot, &saRoot->mpiConfig, hwConfig, swConfig); + if (AGSA_RC_FAILURE == ret) + { + SA_DBG1(("saInitialize failure queue number=%d\n", saRoot->QueueConfig.numInboundQueues)); + agRoot->sdkData = agNULL; + smTraceFuncExit(hpDBG_VERY_LOUD, 'r', "m1"); + return ret; + } + } + } + + + saRoot->swConfig.param3 = &saRoot->QueueConfig; + + mpiMemoryAllocated.count = memoryAllocated->count - MPI_MEM_INDEX; + for ( i = 0; i < mpiMemoryAllocated.count; i ++ ) + { + mpiMemoryAllocated.region[i].virtPtr = memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].virtPtr; + mpiMemoryAllocated.region[i].appHandle = memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].osHandle; + mpiMemoryAllocated.region[i].physAddrUpper = memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].phyAddrUpper; + mpiMemoryAllocated.region[i].physAddrLower = memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].phyAddrLower; + mpiMemoryAllocated.region[i].totalLength = memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].totalLength; + mpiMemoryAllocated.region[i].numElements = memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].numElements; + mpiMemoryAllocated.region[i].elementSize = memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].singleElementLength; + mpiMemoryAllocated.region[i].alignment = memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].alignment; + mpiMemoryAllocated.region[i].type = memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].type; + SA_DBG2(("saInitialize: memoryAllocated->agMemory[%d] VirtPtr=%p PhysicalLo=%x Count=%x Total=%x type %x\n", + (MPI_IBQ_OBQ_INDEX + i), + memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].virtPtr, + memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].phyAddrLower, + memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].numElements, + memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].totalLength, + memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].type)); + + /* set to zeros */ + SA_DBG1(("saInitialize: Zero memory region %d virt %p allocated %d\n", + i,mpiMemoryAllocated.region[i].virtPtr, mpiMemoryAllocated.region[i].totalLength)); + si_memset(mpiMemoryAllocated.region[i].virtPtr , 0,mpiMemoryAllocated.region[i].totalLength); + + } + + if ((!swConfig->max_MSI_InterruptVectors) && + (!swConfig->max_MSIX_InterruptVectors) && + (!swConfig->legacyInt_X)) + { + /* polling mode */ + SA_DBG1(("saInitialize: configured as polling mode\n")); + } + else + { + + SA_DBG1(("saInitialize: swConfig->max_MSI_InterruptVectors %d\n",swConfig->max_MSI_InterruptVectors)); + SA_DBG1(("saInitialize: swConfig->max_MSIX_InterruptVectors %d\n",swConfig->max_MSIX_InterruptVectors)); + + if ((swConfig->legacyInt_X > 1) || (swConfig->max_MSI_InterruptVectors > 32) || + (swConfig->max_MSIX_InterruptVectors > 64)) + { + /* error */ + agRoot->sdkData = agNULL; + SA_DBG1(("saInitialize:AGSA_RC_FAILURE InterruptVectors A\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 's', "m1"); + return AGSA_RC_FAILURE; + } + if ((swConfig->legacyInt_X) && (swConfig->max_MSI_InterruptVectors)) + { + /* error */ + agRoot->sdkData = agNULL; + SA_DBG1(("saInitialize:AGSA_RC_FAILURE InterruptVectors B\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 't', "m1"); + return AGSA_RC_FAILURE; + } + else if ((swConfig->legacyInt_X) && (swConfig->max_MSIX_InterruptVectors)) + { + /* error */ + agRoot->sdkData = agNULL; + SA_DBG1(("saInitialize:AGSA_RC_FAILURE InterruptVectors C\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'u', "m1"); + return AGSA_RC_FAILURE; + } + else if ((swConfig->max_MSI_InterruptVectors) && (swConfig->max_MSIX_InterruptVectors)) + { + /* error */ + agRoot->sdkData = agNULL; + SA_DBG1(("saInitialize:AGSA_RC_FAILURE InterruptVectors D\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'v', "m1"); + return AGSA_RC_FAILURE; + } + } + + /* This section sets common interrupt for Legacy(IRQ) and MSI and MSIX types */ + if(smIS_SPC(agRoot)) + { + SA_DBG1(("saInitialize: SPC interrupts\n" )); + + if (swConfig->legacyInt_X) + { + saRoot->OurInterrupt = siOurLegacyInterrupt; /* Called in ISR*/ + saRoot->DisableInterrupts = siDisableLegacyInterrupts; /* Called in ISR*/ + saRoot->ReEnableInterrupts = siReenableLegacyInterrupts;/* Called in Delayed Int handler*/ + } + else if (swConfig->max_MSIX_InterruptVectors) + { + saRoot->OurInterrupt = siOurMSIXInterrupt; + saRoot->DisableInterrupts = siDisableMSIXInterrupts; + saRoot->ReEnableInterrupts = siReenableMSIXInterrupts; + } + else if (swConfig->max_MSI_InterruptVectors) + { + saRoot->OurInterrupt = siOurMSIInterrupt; + saRoot->DisableInterrupts = siDisableMSIInterrupts; + saRoot->ReEnableInterrupts = siReenableMSIInterrupts; + } + else + { + /* polling mode */ + saRoot->OurInterrupt = siOurLegacyInterrupt; /* Called in ISR*/ + saRoot->DisableInterrupts = siDisableLegacyInterrupts; /* Called in ISR*/ + saRoot->ReEnableInterrupts = siReenableLegacyInterrupts;/* Called in Delayed Int handler*/ + } + } + else + { + SA_DBG1(("saInitialize: SPC V interrupts\n" )); + if (swConfig->legacyInt_X ) + { + SA_DBG1(("saInitialize: SPC V legacyInt_X\n" )); + saRoot->OurInterrupt = siOurLegacy_V_Interrupt; /* Called in ISR*/ + saRoot->DisableInterrupts = siDisableLegacy_V_Interrupts; /* Called in ISR*/ + saRoot->ReEnableInterrupts = siReenableLegacy_V_Interrupts;/* Called in Delayed Int handler*/ + } + else if (swConfig->max_MSIX_InterruptVectors) + { + SA_DBG1(("saInitialize: SPC V max_MSIX_InterruptVectors %X\n", swConfig->max_MSIX_InterruptVectors)); + saRoot->OurInterrupt = siOurMSIX_V_Interrupt; /* */ + saRoot->DisableInterrupts = siDisableMSIX_V_Interrupts; + saRoot->ReEnableInterrupts = siReenableMSIX_V_Interrupts; + } + else if (swConfig->max_MSI_InterruptVectors) + { + SA_DBG1(("saInitialize: SPC V max_MSI_InterruptVectors\n" )); + saRoot->OurInterrupt = siOurMSIX_V_Interrupt; /* */ + saRoot->DisableInterrupts = siDisableMSIX_V_Interrupts; + saRoot->ReEnableInterrupts = siReenableMSIX_V_Interrupts; + } + else + { + /* polling mode */ + SA_DBG1(("saInitialize: SPC V polling mode\n" )); + saRoot->OurInterrupt = siOurLegacy_V_Interrupt; /* Called in ISR*/ + saRoot->DisableInterrupts = siDisableLegacy_V_Interrupts; /* Called in ISR*/ + saRoot->ReEnableInterrupts = siReenableLegacy_V_Interrupts;/* Called in Delayed Int handler*/ + } + SA_DBG1(("saInitialize: SPC V\n" )); + } + + saRoot->Use64bit = (saRoot->QueueConfig.numOutboundQueues > 32 ) ? 1 : 0; + if( smIS64bInt(agRoot)) + { + SA_DBG1(("saInitialize: Use 64 bits for interrupts %d %d\n" ,saRoot->Use64bit, saRoot->QueueConfig.numOutboundQueues )); + } + else + { + SA_DBG1(("saInitialize: Use 32 bits for interrupts %d %d\n",saRoot->Use64bit , saRoot->QueueConfig.numOutboundQueues )); + } + +#ifdef SA_LL_IBQ_PROTECT + SA_DBG1(("saInitialize: Inbound locking defined since LL_IOREQ_IBQ0_LOCK %d\n",LL_IOREQ_IBQ0_LOCK)); +#endif /* SA_LL_IBQ_PROTECT */ + + /* Disable interrupt */ + saRoot->DisableInterrupts(agRoot, 0); + SA_DBG1(("saInitialize: DisableInterrupts sysIntsActive %X\n" ,saRoot->sysIntsActive)); + +#ifdef SA_FW_TEST_BUNCH_STARTS + saRoot->BunchStarts_Enable = FALSE; + saRoot->BunchStarts_Threshold = 5; + saRoot->BunchStarts_Pending = 0; + saRoot->BunchStarts_TimeoutTicks = 10; // N x 100 ms +#endif /* SA_FW_TEST_BUNCH_STARTS */ + + /* clear the interrupt vector bitmap */ + for ( i = 0; i < MAX_NUM_VECTOR; i ++ ) + { + saRoot->interruptVecIndexBitMap[i] = 0; + saRoot->interruptVecIndexBitMap1[i] = 0; + } + +#if defined(SALLSDK_DEBUG) + smTrace(hpDBG_VERY_LOUD,"2Y",0); + /* TP:2Y SCRATCH_PAD */ + + SA_DBG1(("saInitialize: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_0))); + SA_DBG1(("saInitialize: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1))); + SA_DBG1(("saInitialize: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_2))); + SA_DBG1(("saInitialize: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_3))); +#endif /* SALLSDK_DEBUG */ + + if(smIS_SPCV(agRoot)) + { + bit32 ScratchPad1 =0; + bit32 ScratchPad3 =0; + + ScratchPad1 = ossaHwRegRead(agRoot,V_Scratchpad_1_Register); + ScratchPad3 = ossaHwRegRead(agRoot,V_Scratchpad_3_Register); + if((ScratchPad1 & SCRATCH_PAD1_V_RAAE_MASK) == SCRATCH_PAD1_V_RAAE_MASK) + { + if(((ScratchPad3 & SCRATCH_PAD3_V_ENC_MASK ) == SCRATCH_PAD3_V_ENC_DIS_ERR ) || + ((ScratchPad3 & SCRATCH_PAD3_V_ENC_MASK ) == SCRATCH_PAD3_V_ENC_ENA_ERR ) ) + { + SA_DBG1(("saInitialize:Warning Encryption Issue SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_3))); + } + } + } + + if( smIS_SPC(agRoot)) + { +#ifdef SA_ENABLE_HDA_FUNCTIONS + TryWithHDA_ON: + Double_Reset_HDA = TRUE; + + if (swConfig->hostDirectAccessSupport) + { + if (AGSA_RC_FAILURE == siHDAMode(agRoot, swConfig->hostDirectAccessMode, (agsaFwImg_t *)swConfig->param4)) + { + SA_DBG1(("saInitialize:AGSA_RC_FAILURE siHDAMode\n")); + agRoot->sdkData = agNULL; + smTraceFuncExit(hpDBG_VERY_LOUD, 'w', "m1"); + return AGSA_RC_FAILURE; + } + else + { + SA_DBG1(("saInitialize:1 Going to HDA mode HDA 0x%X \n",ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET))); + if(Double_Reset_HDA == agFALSE) + { + siSpcSoftReset(agRoot, SPC_HDASOFT_RESET_SIGNATURE); + SA_DBG1(("saInitialize: Double_Reset_HDA HDA 0x%X \n",ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET))); + Double_Reset_HDA = TRUE; + goto TryWithHDA_ON; + } + } + } + else + { + /* check FW is running */ + if (BOOTTLOADERHDA_IDLE == (ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_STATUS_BITS)) + { + /* HDA mode */ + SA_DBG1(("saInitialize: No HDA mode enable and FW is not running.\n")); + if(Tried_NO_HDA != agTRUE ) + { + + Tried_NO_HDA = TRUE; + swConfig->hostDirectAccessSupport = 1; + swConfig->hostDirectAccessMode = 1; + siSpcSoftReset(agRoot, SPC_HDASOFT_RESET_SIGNATURE); + SA_DBG1(("saInitialize: 2 Going to HDA mode HDA %X \n",ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET))); + goto TryWithHDA_ON; + } + else + { + SA_DBG1(("saInitialize: could not start HDA mode HDA %X \n",ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET))); + smTraceFuncExit(hpDBG_VERY_LOUD, 'x', "m1"); + + return AGSA_RC_FAILURE; + } + smTraceFuncExit(hpDBG_VERY_LOUD, 'y', "m1"); + return AGSA_RC_FAILURE; + } + } +#else /* SA_ENABLE_HDA_FUNCTIONS */ + /* check FW is running */ + if (BOOTTLOADERHDA_IDLE == (ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_STATUS_BITS) ) + { + /* HDA mode */ + SA_DBG1(("saInitialize: No HDA mode enable and FW is not running.\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'z', "m1"); + return AGSA_RC_FAILURE; + } +#endif /* SA_ENABLE_HDA_FUNCTIONS */ + } + else + { + SA_DBG1(("saInitialize: SPCv swConfig->hostDirectAccessMode %d swConfig->hostDirectAccessSupport %d\n",swConfig->hostDirectAccessMode,swConfig->hostDirectAccessSupport)); + if (swConfig->hostDirectAccessSupport) + { + bit32 hda_status; + bit32 soft_reset_status = AGSA_RC_SUCCESS; + + SA_DBG1(("saInitialize: SPCv load HDA\n")); + + hda_status = (ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28)); + + SA_DBG1(("saInitialize: hda_status 0x%x\n",hda_status)); + + siScratchDump(agRoot); + + if( swConfig->hostDirectAccessMode == 0) + { + soft_reset_status = siSoftReset(agRoot, SPC_HDASOFT_RESET_SIGNATURE); + if(soft_reset_status != AGSA_RC_SUCCESS) + { + agRoot->sdkData = agNULL; + SA_DBG1(("saInitialize:AGSA_RC_FAILURE soft_reset_status\n")); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'A', "m1"); + return AGSA_RC_FAILURE; + } + } + + if((hda_status & SPC_V_HDAR_RSPCODE_MASK) != SPC_V_HDAR_IDLE) + { + SA_DBG1(("saInitialize: hda_status not SPC_V_HDAR_IDLE 0x%08x\n", hda_status)); + soft_reset_status = siSoftReset(agRoot, SPC_HDASOFT_RESET_SIGNATURE); + hda_status = (ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28)); + if((hda_status & SPC_V_HDAR_RSPCODE_MASK) != SPC_V_HDAR_IDLE) + { + SA_DBG1(("saInitialize: 2 reset hda_status not SPC_V_HDAR_IDLE 0x%08x\n", hda_status)); + } + } + if(soft_reset_status != AGSA_RC_SUCCESS) + { + agRoot->sdkData = agNULL; + SA_DBG1(("saInitialize:AGSA_RC_FAILURE soft_reset_status A\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'B', "m1"); + return AGSA_RC_FAILURE; + } + +#ifdef SA_ENABLE_HDA_FUNCTIONS + if (AGSA_RC_FAILURE == siHDAMode_V(agRoot, swConfig->hostDirectAccessMode, (agsaFwImg_t *)swConfig->param4)) + { + SA_DBG1(("saInitialize:AGSA_RC_FAILURE siHDAMode_V\n")); + + siChipResetV(agRoot, SPC_HDASOFT_RESET_SIGNATURE); + agRoot->sdkData = agNULL; + smTraceFuncExit(hpDBG_VERY_LOUD, 'C', "m1"); + return AGSA_RC_FAILURE; + } +#endif /* SA_ENABLE_HDA_FUNCTIONS */ + + } + else + { + SA_DBG1(("saInitialize: SPCv normal\n")); + } + + } + + /* copy the table to the LL layer */ + si_memcpy(&saRoot->mpiConfig.phyAnalogConfig, &hwConfig->phyAnalogConfig, sizeof(agsaPhyAnalogSetupTable_t)); + +#ifdef SALL_API_TEST + /* Initialize the LL IO counter */ + si_memset(&saRoot->LLCounters, 0, sizeof(agsaIOCountInfo_t)); +#endif + + si_memset(&saRoot->IoErrorCount, 0, sizeof(agsaIOErrorEventStats_t)); + si_memset(&saRoot->IoEventCount, 0, sizeof(agsaIOErrorEventStats_t)); + if(smIS_SPC(agRoot)) + { + if( smIS_spc8081(agRoot)) + { + if (AGSA_RC_FAILURE == siBar4Shift(agRoot, MBIC_GSM_SM_BASE)) + { + SA_DBG1(("saInitialize: siBar4Shift FAILED ******************************************\n")); + } + } + siSpcSoftReset(agRoot, SPC_SOFT_RESET_SIGNATURE); + } + if(smIS_SPCV(agRoot)) + { + SA_DBG1(("saInitialize: saRoot->ChipId == VEN_DEV_SPCV\n")); + siChipResetV(agRoot, SPC_SOFT_RESET_SIGNATURE); + } + + /* MPI Initialization */ + ret = mpiInitialize(agRoot, &mpiMemoryAllocated, &saRoot->mpiConfig); + SA_DBG1(("saInitialize: MaxOutstandingIO 0x%x swConfig->maxActiveIOs 0x%x\n", saRoot->ControllerInfo.maxPendingIO,saRoot->swConfig.maxActiveIOs )); + +#ifdef SA_ENABLE_HDA_FUNCTIONS + if( ret == AGSA_RC_FAILURE && Tried_NO_HDA == agFALSE && smIS_SPC(agRoot)) + { /* FW not flashed */ + Tried_NO_HDA=agTRUE; + swConfig->hostDirectAccessSupport = 1; + swConfig->hostDirectAccessMode = 1; + siSoftReset(agRoot, SPC_SOFT_RESET_SIGNATURE); + SA_DBG1(("saInitialize: 3 Going to HDA mode HDA %X \n",ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET))); + goto TryWithHDA_ON; + } + +#endif /* SA_ENABLE_HDA_FUNCTIONS */ + + if( ret == AGSA_RC_FAILURE) + { + SA_DBG1(("saInitialize: AGSA_RC_FAILURE mpiInitialize\n")); + SA_DBG1(("saInitialize: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegRead(agRoot, V_Scratchpad_0_Register))); + SA_DBG1(("saInitialize: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegRead(agRoot, V_Scratchpad_1_Register))); + SA_DBG1(("saInitialize: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegRead(agRoot, V_Scratchpad_2_Register))); + SA_DBG1(("saInitialize: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, V_Scratchpad_3_Register))); + + if(saRoot->swConfig.fatalErrorInterruptEnable) + { + ossaDisableInterrupts(agRoot,saRoot->swConfig.fatalErrorInterruptVector ); + } + + agRoot->sdkData = agNULL; + smTraceFuncExit(hpDBG_VERY_LOUD, 'D', "m1"); + return ret; + } + + /* setup hardware interrupt coalescing control and timer registers */ + if(smIS_SPCV(agRoot)) + { + SA_DBG1(("saInitialize: SPC_V Not set hwInterruptCoalescingTimer\n" )); + SA_DBG1(("saInitialize: SPC_V Not set hwInterruptCoalescingControl\n" )); + } + else + { + ossaHwRegWriteExt(agRoot, PCIBAR1, SPC_ICTIMER,hwConfig->hwInterruptCoalescingTimer ); + ossaHwRegWriteExt(agRoot, PCIBAR1, SPC_ICCONTROL, hwConfig->hwInterruptCoalescingControl); + } + + + SA_DBG1(("saInitialize: swConfig->fatalErrorInterruptEnable %X\n",swConfig->fatalErrorInterruptEnable)); + + SA_DBG1(("saInitialize: saRoot->swConfig.fatalErrorInterruptVector %X\n",saRoot->swConfig.fatalErrorInterruptVector)); + SA_DBG1(("saInitialize: swConfig->max_MSI_InterruptVectors %X\n",swConfig->max_MSI_InterruptVectors)); + SA_DBG1(("saInitialize: swConfig->max_MSIX_InterruptVectors %X\n",swConfig->max_MSIX_InterruptVectors)); + SA_DBG1(("saInitialize: swConfig->legacyInt_X %X\n",swConfig->legacyInt_X)); + SA_DBG1(("saInitialize: swConfig->hostDirectAccessSupport %X\n",swConfig->hostDirectAccessSupport)); + SA_DBG1(("saInitialize: swConfig->hostDirectAccessMode %X\n",swConfig->hostDirectAccessMode)); + +#ifdef SA_CONFIG_MDFD_REGISTRY + SA_DBG1(("saInitialize: swConfig->disableMDF %X\n",swConfig->disableMDF)); +#endif /*SA_CONFIG_MDFD_REGISTRY*/ + /*SA_DBG1(("saInitialize: swConfig->enableDIF %X\n",swConfig->enableDIF));*/ + /*SA_DBG1(("saInitialize: swConfig->enableEncryption %X\n",swConfig->enableEncryption));*/ + + + /* log message if failure */ + if (AGSA_RC_FAILURE == ret) + { + SA_DBG1(("saInitialize:AGSA_RC_FAILURE mpiInitialize\n")); + /* Assign chip status */ + saRoot->chipStatus = CHIP_FATAL_ERROR; + } + else + { + /* Assign chip status */ + saRoot->chipStatus = CHIP_NORMAL; +#ifdef SA_FW_TIMER_READS_STATUS + siTimerAdd(agRoot,SA_FW_TIMER_READS_STATUS_INTERVAL, siReadControllerStatus,0,agNULL ); +#endif /* SA_FW_TIMER_READS_STATUS */ + } + + + if( ret == AGSA_RC_SUCCESS || ret == AGSA_RC_VERSION_UNTESTED) + { + if(gPollForMissingInt) + { + mpiOCQueue_t *circularQ; + SA_DBG1(("saInitialize: saRoot->sysIntsActive %X\n",saRoot->sysIntsActive)); + + circularQ = &saRoot->outboundQueue[0]; + OSSA_READ_LE_32(circularQ->agRoot, &circularQ->producerIdx, circularQ->piPointer, 0); + SA_DBG1(("saInitialize: PI 0x%03x CI 0x%03x\n",circularQ->producerIdx, circularQ->consumerIdx)); + } + } + + /* If fatal error interrupt enable we need checking it during the interrupt */ + SA_DBG1(("saInitialize: swConfig.fatalErrorInterruptEnable %d\n",saRoot->swConfig.fatalErrorInterruptEnable)); + SA_DBG1(("saInitialize: swConfig.fatalErrorInterruptVector %d\n",saRoot->swConfig.fatalErrorInterruptVector)); + SA_DBG1(("saInitialize: swConfig->max_MSIX_InterruptVectors %X\n",swConfig->max_MSIX_InterruptVectors)); + + if(saRoot->swConfig.fatalErrorInterruptEnable) + { + + SA_DBG1(("saInitialize: Doorbell_Set %08X U %08X\n", + ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_Register), + ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_RegisterU))); + SA_DBG1(("saInitialize: Doorbell_Mask %08X U %08X\n", + ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register ), + ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_RegisterU ))); + + ossaReenableInterrupts(agRoot,saRoot->swConfig.fatalErrorInterruptVector ); + + SA_DBG1(("saInitialize: Doorbell_Set %08X U %08X\n", + ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_Register), + ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_RegisterU))); + SA_DBG1(("saInitialize: Doorbell_Mask %08X U %08X\n", + ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register ), + ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_RegisterU ))); + } + + + SA_DBG1(("saInitialize: siDumpActiveIORequests\n")); + siDumpActiveIORequests(agRoot, saRoot->swConfig.maxActiveIOs); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'E', "m1"); + /* return */ + return ret; +} + + + +#ifdef SA_FW_TIMER_READS_STATUS + +bit32 siReadControllerStatus( + agsaRoot_t *agRoot, + bit32 Event, + void * pParm + ) +{ + bit32 to_ret =0; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + mpiReadGSTable(agRoot, &saRoot->mpiGSTable); + + if(smIS_SPCV_2_IOP(agRoot)) + { + if(saRoot->Iop1Tcnt_last == saRoot->mpiGSTable.Iop1Tcnt ) + SA_DBG2(("siReadControllerStatus: Iop1 %d STUCK\n", saRoot->mpiGSTable.Iop1Tcnt)); + } + + if( saRoot->MsguTcnt_last == saRoot->mpiGSTable.MsguTcnt || saRoot->IopTcnt_last == saRoot->mpiGSTable.IopTcnt ) + { + SA_DBG1(("siReadControllerStatus: Msgu %d Iop %d\n",saRoot->mpiGSTable.MsguTcnt, saRoot->mpiGSTable.IopTcnt)); + saFatalInterruptHandler(agRoot, saRoot->swConfig.fatalErrorInterruptVector ); + } + SA_DBG2(("siReadControllerStatus: Msgu %d Iop %d\n",saRoot->mpiGSTable.MsguTcnt, saRoot->mpiGSTable.IopTcnt)); + + saRoot->MsguTcnt_last = saRoot->mpiGSTable.MsguTcnt; + saRoot->IopTcnt_last = saRoot->mpiGSTable.IopTcnt; + saRoot->Iop1Tcnt_last = saRoot->mpiGSTable.Iop1Tcnt; + + + if(gPollForMissingInt) + { + mpiOCQueue_t *circularQ; + SA_DBG4(("siReadControllerStatus: saRoot->sysIntsActive %X\n",saRoot->sysIntsActive)); + + circularQ = &saRoot->outboundQueue[0]; + OSSA_READ_LE_32(circularQ->agRoot, &circularQ->producerIdx, circularQ->piPointer, 0); + if(circularQ->producerIdx != circularQ->consumerIdx) + { + SA_DBG1(("siReadControllerStatus: saRoot->sysIntsActive %X\n",saRoot->sysIntsActive)); + SA_DBG1(("siReadControllerStatus: PI 0x%03x CI 0x%03x\n",circularQ->producerIdx, circularQ->consumerIdx)); + + SA_DBG1(("siReadControllerStatus:IN MSGU_READ_ODMR %08X\n",siHalRegReadExt(agRoot, GEN_MSGU_ODMR, V_Outbound_Doorbell_Mask_Set_Register ))); + SA_DBG1(("siReadControllerStatus:MSGU_READ_ODR %08X\n",siHalRegReadExt(agRoot, GEN_MSGU_ODR, V_Outbound_Doorbell_Set_Register))); + ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Clear_Register, 0xFFFFFFFF ); + + } + } + + siTimerAdd(agRoot,SA_FW_TIMER_READS_STATUS_INTERVAL, siReadControllerStatus,Event,pParm ); + + return(to_ret); +} + +#endif /* SA_FW_TIMER_READS_STATUS */ + +/******************************************************************************/ +/*! \brief Routine to do SPC configuration with default or specified values + * + * Set up configuration table in LL Layer + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param mpiConfig MPI Configuration + * \param swConfig Pointer to the software configuration + * + * \return -void- + */ +/*******************************************************************************/ +GLOBAL bit32 siConfiguration( + agsaRoot_t *agRoot, + mpiConfig_t *mpiConfig, + agsaHwConfig_t *hwConfig, + agsaSwConfig_t *swConfig + ) +{ + agsaQueueConfig_t *queueConfig; + bit32 intOption, enable64 = 0; + bit8 i; + + + /* sanity check */ + SA_ASSERT( (agNULL != agRoot), ""); + + smTraceFuncEnter(hpDBG_VERY_LOUD,"m2"); + + si_memset(mpiConfig, 0, sizeof(mpiConfig_t)); + SA_DBG1(("siConfiguration: si_memset mpiConfig\n")); + +#if defined(SALLSDK_DEBUG) + sidump_swConfig(swConfig); +#endif + mpiConfig->mainConfig.custset = swConfig->FWConfig; + + SA_DBG1(("siConfiguration:custset %8X %8X\n",mpiConfig->mainConfig.custset,swConfig->FWConfig)); + + if (swConfig->param3 == agNULL) + { + SA_DBG1(("siConfiguration: swConfig->param3 == agNULL\n")); + /* initialize the mpiConfig */ + /* We configure the Host main part of configuration table */ + mpiConfig->mainConfig.iQNPPD_HPPD_GEvent = 0; + mpiConfig->mainConfig.outboundHWEventPID0_3 = 0; + mpiConfig->mainConfig.outboundHWEventPID4_7 = 0; + mpiConfig->mainConfig.outboundNCQEventPID0_3 = 0; + mpiConfig->mainConfig.outboundNCQEventPID4_7 = 0; + mpiConfig->mainConfig.outboundTargetITNexusEventPID0_3 = 0; + mpiConfig->mainConfig.outboundTargetITNexusEventPID4_7 = 0; + mpiConfig->mainConfig.outboundTargetSSPEventPID0_3 = 0; + mpiConfig->mainConfig.outboundTargetSSPEventPID4_7 = 0; + + mpiConfig->mainConfig.ioAbortDelay = 0; + + mpiConfig->mainConfig.upperEventLogAddress = 0; + mpiConfig->mainConfig.lowerEventLogAddress = 0; + mpiConfig->mainConfig.eventLogSize = MPI_LOGSIZE; + mpiConfig->mainConfig.eventLogOption = 0; + mpiConfig->mainConfig.upperIOPeventLogAddress = 0; + mpiConfig->mainConfig.lowerIOPeventLogAddress = 0; + mpiConfig->mainConfig.IOPeventLogSize = MPI_LOGSIZE; + mpiConfig->mainConfig.IOPeventLogOption = 0; + mpiConfig->mainConfig.FatalErrorInterrupt = 0; + + /* save the default value */ + mpiConfig->numInboundQueues = AGSA_MAX_INBOUND_Q; + mpiConfig->numOutboundQueues = AGSA_MAX_OUTBOUND_Q; + mpiConfig->maxNumInboundQueues = AGSA_MAX_INBOUND_Q; + mpiConfig->maxNumOutboundQueues = AGSA_MAX_OUTBOUND_Q; + + /* configure inbound queues */ + for ( i = 0; i < AGSA_MAX_INBOUND_Q; i ++ ) + { + mpiConfig->inboundQueues[i].numElements = INBOUND_DEPTH_SIZE; + mpiConfig->inboundQueues[i].elementSize = IOMB_SIZE64; + mpiConfig->inboundQueues[i].priority = MPI_QUEUE_NORMAL; + } + + /* configure outbound queues */ + for ( i = 0; i < AGSA_MAX_OUTBOUND_Q; i ++ ) + { + mpiConfig->outboundQueues[i].numElements = OUTBOUND_DEPTH_SIZE; + mpiConfig->outboundQueues[i].elementSize = IOMB_SIZE64; + mpiConfig->outboundQueues[i].interruptVector = 0; + mpiConfig->outboundQueues[i].interruptDelay = 0; + mpiConfig->outboundQueues[i].interruptThreshold = 0; + /* always enable OQ interrupt */ + mpiConfig->outboundQueues[i].interruptEnable = 1; + } + } + else + { /* Parm3 is not null */ + queueConfig = (agsaQueueConfig_t *)swConfig->param3; + +#if defined(SALLSDK_DEBUG) + sidump_Q_config( queueConfig ); +#endif + + SA_DBG1(("siConfiguration: swConfig->param3 == %p\n",queueConfig)); + + if ((queueConfig->numInboundQueues > AGSA_MAX_INBOUND_Q) || + (queueConfig->numOutboundQueues > AGSA_MAX_OUTBOUND_Q)) + { + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "m2"); + SA_DBG1(("siConfiguration:AGSA_RC_FAILURE MAX_Q\n")); + + return AGSA_RC_FAILURE; + } + + if ((queueConfig->numInboundQueues == 0 || + queueConfig->numOutboundQueues == 0 )) + { + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "m2"); + SA_DBG1(("siConfiguration:AGSA_RC_FAILURE NO_Q\n")); + return AGSA_RC_FAILURE; + } + mpiConfig->mainConfig.eventLogSize = swConfig->sizefEventLog1 * KBYTES; + mpiConfig->mainConfig.eventLogOption = swConfig->eventLog1Option; + mpiConfig->mainConfig.IOPeventLogSize = swConfig->sizefEventLog2 * KBYTES; + mpiConfig->mainConfig.IOPeventLogOption = swConfig->eventLog2Option; + + if ((queueConfig->numInboundQueues > IQ_NUM_32) || (queueConfig->numOutboundQueues > OQ_NUM_32)) + { + enable64 = 1; + } + + if (agNULL == hwConfig) + { + intOption = 0; + } + else + { + +#if defined(SALLSDK_DEBUG) + sidump_hwConfig(hwConfig); +#endif + + + if(smIS_SPCV(agRoot)) + { + intOption = 0; + } + else + { + intOption = hwConfig->intReassertionOption & INT_OPTION; + } + + } + + /* Enable SGPIO */ + swConfig->sgpioSupportEnable = 1; + + /* set bit for normal priority or high priority path */ + /* set fatal error interrupt enable and vector */ + /* set Interrupt Reassertion enable and 64 IQ/OQ enable */ + mpiConfig->mainConfig.FatalErrorInterrupt = + (swConfig->fatalErrorInterruptEnable) /* bit 0*/ | + (hwConfig == agNULL ? 0: (hwConfig->hwOption & HW_CFG_PICI_EFFECTIVE_ADDRESS ? (0x1 << SHIFT1): 0))| + (swConfig->sgpioSupportEnable ? (0x1 << SHIFT2): 0) | + /* compile option SA_ENABLE_POISION_TLP */(SA_PTNFE_POISION_TLP << SHIFT3) | +#ifdef SA_CONFIG_MDFD_REGISTRY + (swConfig->disableMDF ? (0x1 << SHIFT4): 0) | +#else + /* compile option SA_DISABLE_MDFD */ (SA_MDFD_MULTI_DATA_FETCH << SHIFT4) | +#endif /*SA_CONFIG_MDFD_REGISTRY*/ + /* compile option SA_DISABLE_OB_COAL */(SA_OUTBOUND_COALESCE << SHIFT5) | + /* compile option SA_ENABLE_ARBTE */(SA_ARBTE << SHIFT6) | + ((swConfig->fatalErrorInterruptVector & FATAL_ERROR_INT_BITS) << SHIFT8) | + (enable64 << SHIFT16) | + (intOption << SHIFT17); + + + SA_DBG1(("siConfiguration: swConfig->fatalErrorInterruptEnable %X\n",swConfig->fatalErrorInterruptEnable)); + SA_DBG1(("siConfiguration: swConfig->fatalErrorInterruptVector %X\n",swConfig->fatalErrorInterruptVector)); + + + + /* initialize the mpiConfig */ + /* We configure the Host main part of configuration table */ + mpiConfig->mainConfig.outboundTargetITNexusEventPID0_3 = 0; + mpiConfig->mainConfig.outboundTargetITNexusEventPID4_7 = 0; + mpiConfig->mainConfig.outboundTargetSSPEventPID0_3 = 0; + mpiConfig->mainConfig.outboundTargetSSPEventPID4_7 = 0; + mpiConfig->mainConfig.ioAbortDelay = 0; + mpiConfig->mainConfig.PortRecoveryTimerPortResetTimer = swConfig->PortRecoveryResetTimer; + + /* get parameter from queueConfig */ + mpiConfig->mainConfig.iQNPPD_HPPD_GEvent = queueConfig->iqNormalPriorityProcessingDepth | + (queueConfig->iqHighPriorityProcessingDepth << SHIFT8) | + (queueConfig->generalEventQueue << SHIFT16) | + (queueConfig->tgtDeviceRemovedEventQueue << SHIFT24); + + mpiConfig->mainConfig.outboundHWEventPID0_3 = queueConfig->sasHwEventQueue[0] | + (queueConfig->sasHwEventQueue[1] << SHIFT8) | + (queueConfig->sasHwEventQueue[2] << SHIFT16) | + (queueConfig->sasHwEventQueue[3] << SHIFT24); + mpiConfig->mainConfig.outboundHWEventPID4_7 = queueConfig->sasHwEventQueue[4] | + (queueConfig->sasHwEventQueue[5] << SHIFT8) | + (queueConfig->sasHwEventQueue[6] << SHIFT16) | + (queueConfig->sasHwEventQueue[7] << SHIFT24); + mpiConfig->mainConfig.outboundNCQEventPID0_3 = queueConfig->sataNCQErrorEventQueue[0] | + (queueConfig->sataNCQErrorEventQueue[1] << SHIFT8) | + (queueConfig->sataNCQErrorEventQueue[2] << SHIFT16) | + (queueConfig->sataNCQErrorEventQueue[3] << SHIFT24); + mpiConfig->mainConfig.outboundNCQEventPID4_7 = queueConfig->sataNCQErrorEventQueue[4] | + (queueConfig->sataNCQErrorEventQueue[5] << SHIFT8) | + (queueConfig->sataNCQErrorEventQueue[6] << SHIFT16) | + (queueConfig->sataNCQErrorEventQueue[7] << SHIFT24); + /* save it */ + mpiConfig->numInboundQueues = queueConfig->numInboundQueues; + mpiConfig->numOutboundQueues = queueConfig->numOutboundQueues; + mpiConfig->queueOption = queueConfig->queueOption; + + SA_DBG2(("siConfiguration: numInboundQueues=%d numOutboundQueues=%d\n", + queueConfig->numInboundQueues, + queueConfig->numOutboundQueues)); + + /* configure inbound queues */ + /* We configure the size of queue based on swConfig */ + for( i = 0; i < queueConfig->numInboundQueues; i ++ ) + { + mpiConfig->inboundQueues[i].numElements = (bit16)queueConfig->inboundQueues[i].elementCount; + mpiConfig->inboundQueues[i].elementSize = (bit16)queueConfig->inboundQueues[i].elementSize;; + mpiConfig->inboundQueues[i].priority = queueConfig->inboundQueues[i].priority; + + SA_DBG2(("siConfiguration: IBQ%d:elementCount=%d elementSize=%d priority=%d Total Size 0x%X\n", + i, + queueConfig->inboundQueues[i].elementCount, + queueConfig->inboundQueues[i].elementSize, + queueConfig->inboundQueues[i].priority, + queueConfig->inboundQueues[i].elementCount * queueConfig->inboundQueues[i].elementSize )); + } + + /* configura outbound queues */ + /* We configure the size of queue based on swConfig */ + for( i = 0; i < queueConfig->numOutboundQueues; i ++ ) + { + mpiConfig->outboundQueues[i].numElements = (bit16)queueConfig->outboundQueues[i].elementCount; + mpiConfig->outboundQueues[i].elementSize = (bit16)queueConfig->outboundQueues[i].elementSize; + mpiConfig->outboundQueues[i].interruptVector = (bit8)queueConfig->outboundQueues[i].interruptVectorIndex; + mpiConfig->outboundQueues[i].interruptDelay = (bit16)queueConfig->outboundQueues[i].interruptDelay; + mpiConfig->outboundQueues[i].interruptThreshold = (bit8)queueConfig->outboundQueues[i].interruptCount; + mpiConfig->outboundQueues[i].interruptEnable = (bit32)queueConfig->outboundQueues[i].interruptEnable; + + SA_DBG2(("siConfiguration: OBQ%d:elementCount=%d elementSize=%d interruptCount=%d interruptEnable=%d\n", + i, + queueConfig->outboundQueues[i].elementCount, + queueConfig->outboundQueues[i].elementSize, + queueConfig->outboundQueues[i].interruptCount, + queueConfig->outboundQueues[i].interruptEnable)); + } + } + + SA_DBG1(("siConfiguration:mpiConfig->mainConfig.FatalErrorInterrupt 0x%X\n",mpiConfig->mainConfig.FatalErrorInterrupt)); + SA_DBG1(("siConfiguration:swConfig->fatalErrorInterruptVector 0x%X\n",swConfig->fatalErrorInterruptVector)); + SA_DBG1(("siConfiguration:enable64 0x%X\n",enable64)); + SA_DBG1(("siConfiguration:PortRecoveryResetTimer 0x%X\n",swConfig->PortRecoveryResetTimer)); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "m2"); + + /* return */ + return AGSA_RC_SUCCESS; +} + +#ifdef FW_EVT_LOG_TST +void saLogDump(agsaRoot_t *agRoot, + U32 *eventLogSize, + U32 **eventLogAddress_) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + //mpiConfig_t *mpiConfig = &saRoot->mpiConfig; + mpiHostLLConfigDescriptor_t *mpiConfig = &saRoot->mainConfigTable; + + *eventLogAddress_ = (U32*)eventLogAddress; + *eventLogSize = (U32)mpiConfig->eventLogSize; +} +#endif + +/*******************************************************************************/ +/** \fn mpiInitialize(agsaRoot *agRoot, mpiMemReq_t* memoryAllocated, mpiConfig_t* config) + * \brief Initializes the MPI Message Unit + * \param agRoot Pointer to a data structure containing LL layer context handles + * \param memoryAllocated Data structure that holds the different chunks of memory that are allocated + * \param config MPI configuration + * + * This function is called to initialize SPC_HOST_MPI internal data structures and the SPC hardware. + * This function is competed synch->ronously (there is no callback) + * + * Return: + * AGSA_RC_SUCCESS if initialization succeeded. + * AGSA_RC_FAILURE if initialization failed. + */ +/*******************************************************************************/ +GLOBAL bit32 mpiInitialize(agsaRoot_t *agRoot, + mpiMemReq_t* memoryAllocated, + mpiConfig_t* config) +{ + static spc_configMainDescriptor_t mainCfg; /* main part of MPI configuration */ + static spc_inboundQueueDescriptor_t inQueueCfg; /* Inbound queue HW configuration structure */ + static spc_outboundQueueDescriptor_t outQueueCfg; /* Outbound queue HW configuration structure */ + bit16 qIdx, i, indexoffset; /* Queue index */ + bit16 mIdx = 0; /* Memory region index */ + bit32 MSGUCfgTblDWIdx, GSTLenMPIS; + bit32 MSGUCfgTblBase, ret = AGSA_RC_SUCCESS; + bit32 value, togglevalue; + bit32 saveOffset; + bit32 inboundoffset, outboundoffset; + bit8 pcibar; + bit16 maxinbound = AGSA_MAX_INBOUND_Q; + bit16 maxoutbound = AGSA_MAX_OUTBOUND_Q; + bit32 OB_CIPCIBar; + bit32 IB_PIPCIBar; + bit32 max_wait_time; + bit32 max_wait_count; + bit32 memOffset; + agsaLLRoot_t *saRoot; + mpiICQueue_t *circularIQ = agNULL; + mpiOCQueue_t *circularOQ; + + bit32 mpiUnInitFailed = 0; + bit32 mpiStartToggleFailed = 0; + + +#if defined(SALLSDK_DEBUG) + bit8 phycount = AGSA_MAX_VALID_PHYS; +#endif /* SALLSDK_DEBUG */ + + SA_DBG1(("mpiInitialize: Entering\n")); + SA_ASSERT(NULL != agRoot, "agRoot argument cannot be null"); + SA_ASSERT(NULL != memoryAllocated, "memoryAllocated argument cannot be null"); + SA_ASSERT(NULL != config, "config argument cannot be null"); + SA_ASSERT(0 == (sizeof(spc_inboundQueueDescriptor_t) % 4), "spc_inboundQueueDescriptor_t type size has to be divisible by 4"); + + saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + + si_memset(&mainCfg,0,sizeof(spc_configMainDescriptor_t)); + si_memset(&inQueueCfg,0,sizeof(spc_inboundQueueDescriptor_t)); + si_memset(&outQueueCfg,0,sizeof(spc_outboundQueueDescriptor_t)); + + SA_ASSERT((agNULL !=saRoot ), ""); + if(saRoot == agNULL) + { + SA_DBG1(("mpiInitialize: saRoot == agNULL\n")); + return(AGSA_RC_FAILURE); + } + smTraceFuncEnter(hpDBG_VERY_LOUD,"m3"); + + /*Shift BAR 4 for SPC HAILEAH*/ + if(smIS_SPC(agRoot)) + { + if( smIS_HIL(agRoot)) + { + if (AGSA_RC_FAILURE == siBar4Shift(agRoot, MBIC_GSM_SM_BASE)) + { + SA_DBG1(("mpiInitialize: siBar4Shift FAILED ******************************************\n")); + return AGSA_RC_FAILURE; + } + } + } + + /* Wait for the SPC Configuration Table to be ready */ + ret = mpiWaitForConfigTable(agRoot, &mainCfg); + if (AGSA_RC_FAILURE == ret) + { + /* return error if MPI Configuration Table not ready */ + SA_DBG1(("mpiInitialize: mpiWaitForConfigTable FAILED ******************************************\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "m3"); + return ret; + } + + /* read scratch pad0 to get PCI BAR and offset of configuration table */ + MSGUCfgTblBase = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); + /* get PCI BAR */ + MSGUCfgTblBase = (MSGUCfgTblBase & SCRATCH_PAD0_BAR_MASK) >> SHIFT26; + /* get pci Bar index */ + pcibar = (bit8)mpiGetPCIBarIndex(agRoot, MSGUCfgTblBase); + + SA_DBG1(("mpiInitialize: MSGUCfgTblBase = 0x%x\n", MSGUCfgTblBase)); +#if defined(SALLSDK_DEBUG) + /* get Phy count from configuration table */ + phycount = (bit8)((mainCfg.ContrlCapFlag & PHY_COUNT_BITS) >> SHIFT19); + + SA_DBG1(("mpiInitialize: Number of PHYs = 0x%x\n", phycount)); + + smTrace(hpDBG_VERY_LOUD,"70",phycount); + /* TP:70 phycount */ +#endif /* SALLSDK_DEBUG */ + + /* get High Priority IQ support flag */ + if (mainCfg.ContrlCapFlag & HP_SUPPORT_BIT) + { + SA_DBG1(("mpiInitialize: High Priority IQ support from SPC\n")); + } + /* get Interrupt Coalescing Support flag */ + if (mainCfg.ContrlCapFlag & INT_COL_BIT) + { + SA_DBG1(("mpiInitialize: Interrupt Coalescing support from SPC\n")); + } + + /* get configured the number of inbound/outbound queues */ + if (memoryAllocated->count == TOTAL_MPI_MEM_CHUNKS) + { + config->maxNumInboundQueues = AGSA_MAX_INBOUND_Q; + config->maxNumOutboundQueues = AGSA_MAX_OUTBOUND_Q; + } + else + { + config->maxNumInboundQueues = config->numInboundQueues; + config->maxNumOutboundQueues = config->numOutboundQueues; + maxinbound = config->numInboundQueues; + maxoutbound = config->numOutboundQueues; + } + + SA_DBG1(("mpiInitialize: Number of IQ %d\n", maxinbound)); + SA_DBG1(("mpiInitialize: Number of OQ %d\n", maxoutbound)); + + /* get inbound queue offset */ + inboundoffset = mainCfg.inboundQueueOffset; + /* get outbound queue offset */ + outboundoffset = mainCfg.outboundQueueOffset; + + if(smIS_SPCV(agRoot)) + { + SA_DBG2(("mpiInitialize: Offset of IQ %d\n", (inboundoffset & 0xFF000000) >> 24)); + SA_DBG2(("mpiInitialize: Offset of OQ %d\n", (outboundoffset & 0xFF000000) >> 24)); + inboundoffset &= 0x00FFFFFF; + outboundoffset &= 0x00FFFFFF; + } + /* get offset of the configuration table */ + MSGUCfgTblDWIdx = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); + MSGUCfgTblDWIdx = MSGUCfgTblDWIdx & SCRATCH_PAD0_OFFSET_MASK; + + saveOffset = MSGUCfgTblDWIdx; + + /* Checks if the configuration memory region size is the same as the mpiConfigMain */ + if(memoryAllocated->region[mIdx].totalLength != sizeof(bit8) * config->mainConfig.eventLogSize) + { + SA_DBG1(("ERROR: The memory region [%d] 0x%X != 0x%X does not have the size of the MSGU event log ******************************************\n", + mIdx,memoryAllocated->region[mIdx].totalLength,config->mainConfig.eventLogSize)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "m3"); + return AGSA_RC_FAILURE; + } + + mainCfg.iQNPPD_HPPD_GEvent = config->mainConfig.iQNPPD_HPPD_GEvent; + + if(smIS_SPCV(agRoot)) + { + mainCfg.outboundHWEventPID0_3 = 0; + mainCfg.outboundHWEventPID4_7 = 0; + mainCfg.outboundNCQEventPID0_3 = 0; + mainCfg.outboundNCQEventPID4_7 = 0; + mainCfg.outboundTargetITNexusEventPID0_3 = 0; + mainCfg.outboundTargetITNexusEventPID4_7 = 0; + mainCfg.outboundTargetSSPEventPID0_3 = 0; + mainCfg.outboundTargetSSPEventPID4_7 = 0; + mainCfg.ioAbortDelay = 0; /* SPCV reserved */ + mainCfg.custset = 0; + mainCfg.portRecoveryResetTimer = config->mainConfig.PortRecoveryTimerPortResetTimer; + SA_DBG1(("mpiInitialize:custset V %8X\n",mainCfg.custset)); + SA_DBG1(("mpiInitialize:portRecoveryResetTimer V %8X\n",mainCfg.portRecoveryResetTimer)); + + mainCfg.interruptReassertionDelay = saRoot->hwConfig.intReassertionOption; + SA_DBG1(("mpiInitialize:interruptReassertionDelay V %8X\n", mainCfg.interruptReassertionDelay)); + + + } + else + { + mainCfg.outboundHWEventPID0_3 = config->mainConfig.outboundHWEventPID0_3; + mainCfg.outboundHWEventPID4_7 = config->mainConfig.outboundHWEventPID4_7; + mainCfg.outboundNCQEventPID0_3 = config->mainConfig.outboundNCQEventPID0_3; + mainCfg.outboundNCQEventPID4_7 = config->mainConfig.outboundNCQEventPID4_7; + mainCfg.outboundTargetITNexusEventPID0_3 = config->mainConfig.outboundTargetITNexusEventPID0_3; + mainCfg.outboundTargetITNexusEventPID4_7 = config->mainConfig.outboundTargetITNexusEventPID4_7; + mainCfg.outboundTargetSSPEventPID0_3 = config->mainConfig.outboundTargetSSPEventPID0_3; + mainCfg.outboundTargetSSPEventPID4_7 = config->mainConfig.outboundTargetSSPEventPID4_7; + mainCfg.ioAbortDelay = config->mainConfig.ioAbortDelay; + mainCfg.custset = config->mainConfig.custset; + + SA_DBG1(("mpiInitialize:custset spc %8X\n",mainCfg.custset)); + + } +#ifdef FW_EVT_LOG_TST + eventLogAddress = memoryAllocated->region[mIdx].virtPtr; +#endif + mainCfg.upperEventLogAddress = memoryAllocated->region[mIdx].physAddrUpper; + mainCfg.lowerEventLogAddress = memoryAllocated->region[mIdx].physAddrLower; + mainCfg.eventLogSize = config->mainConfig.eventLogSize; + mainCfg.eventLogOption = config->mainConfig.eventLogOption; + + mIdx++; + + /* Checks if the configuration memory region size is the same as the mpiConfigMain */ + if(memoryAllocated->region[mIdx].totalLength != sizeof(bit8) * config->mainConfig.IOPeventLogSize) + { + SA_DBG1(("ERROR: The memory region does not have the size of the IOP event log\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "m3"); + return AGSA_RC_FAILURE; + } + + mainCfg.upperIOPeventLogAddress = memoryAllocated->region[mIdx].physAddrUpper; + mainCfg.lowerIOPeventLogAddress = memoryAllocated->region[mIdx].physAddrLower; + mainCfg.IOPeventLogSize = config->mainConfig.IOPeventLogSize; + mainCfg.IOPeventLogOption = config->mainConfig.IOPeventLogOption; + mainCfg.FatalErrorInterrupt = config->mainConfig.FatalErrorInterrupt; + + SA_DBG1(("mpiInitialize: iQNPPD_HPPD_GEvent 0x%x\n", mainCfg.iQNPPD_HPPD_GEvent)); + if(smIS_SPCV(agRoot)) + { + } + else + { + SA_DBG3(("mpiInitialize: outboundHWEventPID0_3 0x%x\n", mainCfg.outboundHWEventPID0_3)); + SA_DBG3(("mpiInitialize: outboundHWEventPID4_7 0x%x\n", mainCfg.outboundHWEventPID4_7)); + SA_DBG3(("mpiInitialize: outboundNCQEventPID0_3 0x%x\n", mainCfg.outboundNCQEventPID0_3)); + SA_DBG3(("mpiInitialize: outboundNCQEventPID4_7 0x%x\n", mainCfg.outboundNCQEventPID4_7)); + SA_DBG3(("mpiInitialize: outboundTargetITNexusEventPID0_3 0x%x\n", mainCfg.outboundTargetITNexusEventPID0_3)); + SA_DBG3(("mpiInitialize: outboundTargetITNexusEventPID4_7 0x%x\n", mainCfg.outboundTargetITNexusEventPID4_7)); + SA_DBG3(("mpiInitialize: outboundTargetSSPEventPID0_3 0x%x\n", mainCfg.outboundTargetSSPEventPID0_3)); + SA_DBG3(("mpiInitialize: outboundTargetSSPEventPID4_7 0x%x\n", mainCfg.outboundTargetSSPEventPID4_7)); + } + + SA_DBG3(("mpiInitialize: upperEventLogAddress 0x%x\n", mainCfg.upperEventLogAddress)); + SA_DBG3(("mpiInitialize: lowerEventLogAddress 0x%x\n", mainCfg.lowerEventLogAddress)); + SA_DBG3(("mpiInitialize: eventLogSize 0x%x\n", mainCfg.eventLogSize)); + SA_DBG3(("mpiInitialize: eventLogOption 0x%x\n", mainCfg.eventLogOption)); +#ifdef FW_EVT_LOG_TST + SA_DBG3(("mpiInitialize: eventLogAddress 0x%p\n", eventLogAddress)); +#endif + SA_DBG3(("mpiInitialize: upperIOPLogAddress 0x%x\n", mainCfg.upperIOPeventLogAddress)); + SA_DBG3(("mpiInitialize: lowerIOPLogAddress 0x%x\n", mainCfg.lowerIOPeventLogAddress)); + SA_DBG3(("mpiInitialize: IOPeventLogSize 0x%x\n", mainCfg.IOPeventLogSize)); + SA_DBG3(("mpiInitialize: IOPeventLogOption 0x%x\n", mainCfg.IOPeventLogOption)); + SA_DBG3(("mpiInitialize: FatalErrorInterrupt 0x%x\n", mainCfg.FatalErrorInterrupt)); + SA_DBG3(("mpiInitialize: HDAModeFlags 0x%x\n", mainCfg.HDAModeFlags)); + SA_DBG3(("mpiInitialize: analogSetupTblOffset 0x%08x\n", mainCfg.analogSetupTblOffset)); + + saRoot->mainConfigTable.iQNPPD_HPPD_GEvent = mainCfg.iQNPPD_HPPD_GEvent; + + if(smIS_SPCV(agRoot)) + { + /* SPCV - reserved fields */ + saRoot->mainConfigTable.outboundHWEventPID0_3 = 0; + saRoot->mainConfigTable.outboundHWEventPID4_7 = 0; + saRoot->mainConfigTable.outboundNCQEventPID0_3 = 0; + saRoot->mainConfigTable.outboundNCQEventPID4_7 = 0; + saRoot->mainConfigTable.outboundTargetITNexusEventPID0_3 = 0; + saRoot->mainConfigTable.outboundTargetITNexusEventPID4_7 = 0; + saRoot->mainConfigTable.outboundTargetSSPEventPID0_3 = 0; + saRoot->mainConfigTable.outboundTargetSSPEventPID4_7 = 0; + saRoot->mainConfigTable.ioAbortDelay = 0; + saRoot->mainConfigTable.custset = 0; + + } + else + { + saRoot->mainConfigTable.outboundHWEventPID0_3 = mainCfg.outboundHWEventPID0_3; + saRoot->mainConfigTable.outboundHWEventPID4_7 = mainCfg.outboundHWEventPID4_7; + saRoot->mainConfigTable.outboundNCQEventPID0_3 = mainCfg.outboundNCQEventPID0_3; + saRoot->mainConfigTable.outboundNCQEventPID4_7 = mainCfg.outboundNCQEventPID4_7; + saRoot->mainConfigTable.outboundTargetITNexusEventPID0_3 = mainCfg.outboundTargetITNexusEventPID0_3; + saRoot->mainConfigTable.outboundTargetITNexusEventPID4_7 = mainCfg.outboundTargetITNexusEventPID4_7; + saRoot->mainConfigTable.outboundTargetSSPEventPID0_3 = mainCfg.outboundTargetSSPEventPID0_3; + saRoot->mainConfigTable.outboundTargetSSPEventPID4_7 = mainCfg.outboundTargetSSPEventPID4_7; + saRoot->mainConfigTable.ioAbortDelay = mainCfg.ioAbortDelay; + saRoot->mainConfigTable.custset = mainCfg.custset; + + } + + saRoot->mainConfigTable.upperEventLogAddress = mainCfg.upperEventLogAddress; + saRoot->mainConfigTable.lowerEventLogAddress = mainCfg.lowerEventLogAddress; + saRoot->mainConfigTable.eventLogSize = mainCfg.eventLogSize; + saRoot->mainConfigTable.eventLogOption = mainCfg.eventLogOption; + saRoot->mainConfigTable.upperIOPeventLogAddress = mainCfg.upperIOPeventLogAddress; + saRoot->mainConfigTable.lowerIOPeventLogAddress = mainCfg.lowerIOPeventLogAddress; + saRoot->mainConfigTable.IOPeventLogSize = mainCfg.IOPeventLogSize; + saRoot->mainConfigTable.IOPeventLogOption = mainCfg.IOPeventLogOption; + saRoot->mainConfigTable.FatalErrorInterrupt = mainCfg.FatalErrorInterrupt; + + + if(smIS_SPCV(agRoot)) + { + ;/* SPCV - reserved fields */ + } + else + { + saRoot->mainConfigTable.HDAModeFlags = mainCfg.HDAModeFlags; + } + + saRoot->mainConfigTable.analogSetupTblOffset = mainCfg.analogSetupTblOffset; + + smTrace(hpDBG_VERY_LOUD,"71",mIdx); + /* TP:71 71 mIdx */ + + + + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IQNPPD_HPPD_OFFSET), + mainCfg.iQNPPD_HPPD_GEvent); + + SA_DBG3(("mpiInitialize: Offset 0x%08x mainCfg.iQNPPD_HPPD_GEvent 0x%x\n", (bit32)(MSGUCfgTblDWIdx + MAIN_IQNPPD_HPPD_OFFSET), mainCfg.iQNPPD_HPPD_GEvent)); + + if(smIS_SPC6V(agRoot)) + { + if(smIsCfgVREV_B(agRoot)) + { + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IO_ABORT_DELAY), + MAIN_IO_ABORT_DELAY_END_TO_END_CRC_DISABLE); + + SA_DBG1(("mpiInitialize:SPCV - MAIN_IO_ABORT_DELAY_END_TO_END_CRC_DISABLE\n" )); + } + if(smIsCfgVREV_C(agRoot)) + { + SA_DBG1(("mpiInitialize:SPCV - END_TO_END_CRC On\n" )); + } + SA_DBG3(("mpiInitialize:SPCV - rest reserved field \n" )); + ;/* SPCV - reserved field */ + } + else if(smIS_SPC(agRoot)) + { + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_OB_HW_EVENT_PID03_OFFSET), + mainCfg.outboundHWEventPID0_3); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_OB_HW_EVENT_PID47_OFFSET), + mainCfg.outboundHWEventPID4_7); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_OB_NCQ_EVENT_PID03_OFFSET), + mainCfg.outboundNCQEventPID0_3); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_OB_NCQ_EVENT_PID47_OFFSET), + mainCfg.outboundNCQEventPID4_7); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_TITNX_EVENT_PID03_OFFSET), + mainCfg.outboundTargetITNexusEventPID0_3); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_TITNX_EVENT_PID47_OFFSET), + mainCfg.outboundTargetITNexusEventPID4_7); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_OB_SSP_EVENT_PID03_OFFSET), + mainCfg.outboundTargetSSPEventPID0_3); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_OB_SSP_EVENT_PID47_OFFSET), + mainCfg.outboundTargetSSPEventPID4_7); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_CUSTOMER_SETTING), + mainCfg.custset); + }else + { + if(smIsCfgVREV_A(agRoot)) + { + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IO_ABORT_DELAY), + MAIN_IO_ABORT_DELAY_END_TO_END_CRC_DISABLE); /* */ + SA_DBG1(("mpiInitialize:SPCV12G - offset MAIN_IO_ABORT_DELAY 0x%x value MAIN_IO_ABORT_DELAY_END_TO_END_CRC_DISABLE 0x%x\n",MAIN_IO_ABORT_DELAY ,MAIN_IO_ABORT_DELAY_END_TO_END_CRC_DISABLE)); + SA_DBG1(("mpiInitialize:SPCV12G - END_TO_END_CRC OFF for rev A %d\n",smIsCfgVREV_A(agRoot) )); + } + else if(smIsCfgVREV_B(agRoot)) + { + SA_DBG1(("mpiInitialize:SPCV12G - END_TO_END_CRC ON rev B %d ****************************\n",smIsCfgVREV_B(agRoot) )); + /*ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IO_ABORT_DELAY), + MAIN_IO_ABORT_DELAY_END_TO_END_CRC_DISABLE); + */ + } + else if(smIsCfgVREV_C(agRoot)) + { + SA_DBG1(("mpiInitialize:SPCV12G - END_TO_END_CRC on rev C %d\n",smIsCfgVREV_C(agRoot) )); + } + else + { + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IO_ABORT_DELAY), + MAIN_IO_ABORT_DELAY_END_TO_END_CRC_DISABLE); + SA_DBG1(("mpiInitialize:SPCV12G - END_TO_END_CRC Off unknown rev 0x%x\n", ossaHwRegReadConfig32((agRoot), 8 ))); + } + } + + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_ADDR_HI), mainCfg.upperEventLogAddress); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_ADDR_LO), mainCfg.lowerEventLogAddress); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_BUFF_SIZE), mainCfg.eventLogSize); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_OPTION), mainCfg.eventLogOption); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_ADDR_HI), mainCfg.upperIOPeventLogAddress); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_ADDR_LO), mainCfg.lowerIOPeventLogAddress); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_BUFF_SIZE), mainCfg.IOPeventLogSize); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_OPTION), mainCfg.IOPeventLogOption); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_FATAL_ERROR_INTERRUPT), mainCfg.FatalErrorInterrupt); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_PRECTD_PRESETD), mainCfg.portRecoveryResetTimer); + + SA_DBG3(("mpiInitialize: Offset 0x%08x upperEventLogAddress 0x%x\n",(bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_ADDR_HI), mainCfg.upperEventLogAddress )); + SA_DBG3(("mpiInitialize: Offset 0x%08x lowerEventLogAddress 0x%x\n",(bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_ADDR_LO), mainCfg.lowerEventLogAddress )); + SA_DBG3(("mpiInitialize: Offset 0x%08x eventLogSize 0x%x\n",(bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_BUFF_SIZE), mainCfg.eventLogSize )); + SA_DBG3(("mpiInitialize: Offset 0x%08x eventLogOption 0x%x\n",(bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_OPTION), mainCfg.eventLogOption )); + SA_DBG3(("mpiInitialize: Offset 0x%08x upperIOPeventLogAddress 0x%x\n",(bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_ADDR_HI), mainCfg.upperIOPeventLogAddress )); + SA_DBG3(("mpiInitialize: Offset 0x%08x lowerIOPeventLogAddress 0x%x\n",(bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_ADDR_LO), mainCfg.lowerIOPeventLogAddress )); + SA_DBG3(("mpiInitialize: Offset 0x%08x IOPeventLogSize 0x%x\n",(bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_BUFF_SIZE), mainCfg.IOPeventLogSize )); + SA_DBG3(("mpiInitialize: Offset 0x%08x IOPeventLogOption 0x%x\n",(bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_OPTION), mainCfg.IOPeventLogOption )); + SA_DBG3(("mpiInitialize: Offset 0x%08x FatalErrorInterrupt 0x%x\n",(bit32)(MSGUCfgTblDWIdx + MAIN_FATAL_ERROR_INTERRUPT), mainCfg.FatalErrorInterrupt )); + SA_DBG3(("mpiInitialize: Offset 0x%08x PortRecoveryResetTimer 0x%x\n",(bit32)(MSGUCfgTblDWIdx + MAIN_PRECTD_PRESETD), mainCfg.portRecoveryResetTimer )); + + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IRAD_RESERVED), mainCfg.interruptReassertionDelay); + SA_DBG3(("mpiInitialize: Offset 0x%08x InterruptReassertionDelay 0x%x\n",(bit32)(MSGUCfgTblDWIdx + MAIN_IRAD_RESERVED), mainCfg.interruptReassertionDelay )); + + mIdx++; + + /* skip the ci and pi memory region */ + mIdx++; + mIdx++; + + smTrace(hpDBG_VERY_LOUD,"72",mIdx); + /* TP:72 mIdx */ + smTrace(hpDBG_VERY_LOUD,"Bc",maxinbound); + /* TP:Bc maxinbound */ + smTrace(hpDBG_VERY_LOUD,"Bd",pcibar); + /* TP:Bd pcibar */ + + /* index offset */ + indexoffset = 0; + memOffset = 0; + + /* Memory regions for the inbound queues */ + for(qIdx = 0; qIdx < maxinbound; qIdx++) + { + /* point back to the begin then plus offset to next queue */ + smTrace(hpDBG_VERY_LOUD,"Bd",pcibar); + /* TP:Bd pcibar */ + MSGUCfgTblDWIdx = saveOffset; + MSGUCfgTblDWIdx += inboundoffset; + MSGUCfgTblDWIdx += (sizeof(spc_inboundQueueDescriptor_t) * qIdx); + SA_DBG1(("mpiInitialize: A saveOffset 0x%x MSGUCfgTblDWIdx 0x%x\n",saveOffset ,MSGUCfgTblDWIdx)); + + /* if the MPI configuration says that this queue is disabled ... */ + if(0 == config->inboundQueues[qIdx].numElements) + { + /* ... Clears the configuration table for this queue */ + + inQueueCfg.elementPriSizeCount= 0; + inQueueCfg.upperBaseAddress = 0; + inQueueCfg.lowerBaseAddress = 0; + inQueueCfg.ciUpperBaseAddress = 0; + inQueueCfg.ciLowerBaseAddress = 0; + /* skip inQueueCfg.PIPCIBar (PM8000 write access) */ + /* skip inQueueCfg.PIOffset (PM8000 write access) */ + + /* Update the inbound configuration table in SPC GSM */ + mpiUpdateIBQueueCfgTable(agRoot, &inQueueCfg, MSGUCfgTblDWIdx, pcibar); + } + + /* If the queue is enabled, then ... */ + else + { + bit32 memSize = config->inboundQueues[qIdx].numElements * config->inboundQueues[qIdx].elementSize; + bit32 remainder = memSize & 127; + + /* Calculate the size of this queue padded to 128 bytes */ + if (remainder > 0) + { + memSize += (128 - remainder); + } + + /* ... first checks that the memory region has the right size */ + if( (memoryAllocated->region[mIdx].totalLength - memOffset < memSize) || + (NULL == memoryAllocated->region[mIdx].virtPtr) || + (0 == memoryAllocated->region[mIdx].totalLength)) + { + SA_DBG1(("mpiInitialize: ERROR The memory region does not have the right size for this inbound queue")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "m3"); + return AGSA_RC_FAILURE; + } + else + { + /* Then, using the MPI configuration argument, initializes the corresponding element on the saRoot */ + saRoot->inboundQueue[qIdx].numElements = config->inboundQueues[qIdx].numElements; + saRoot->inboundQueue[qIdx].elementSize = config->inboundQueues[qIdx].elementSize; + saRoot->inboundQueue[qIdx].priority = config->inboundQueues[qIdx].priority; + si_memcpy(&saRoot->inboundQueue[qIdx].memoryRegion, &memoryAllocated->region[mIdx], sizeof(mpiMem_t)); + saRoot->inboundQueue[qIdx].memoryRegion.virtPtr = + (bit8 *)saRoot->inboundQueue[qIdx].memoryRegion.virtPtr + memOffset; + saRoot->inboundQueue[qIdx].memoryRegion.physAddrLower += memOffset; + saRoot->inboundQueue[qIdx].memoryRegion.elementSize = memSize; + saRoot->inboundQueue[qIdx].memoryRegion.totalLength = memSize; + saRoot->inboundQueue[qIdx].memoryRegion.numElements = 1; + + /* Initialize the local copy of PIs, CIs */ + SA_DBG1(("mpiInitialize: queue %d PI CI zero\n",qIdx)); + saRoot->inboundQueue[qIdx].producerIdx = 0; + saRoot->inboundQueue[qIdx].consumerIdx = 0; + saRoot->inboundQueue[qIdx].agRoot = agRoot; + + /* MPI memory region for inbound CIs are 2 */ + saRoot->inboundQueue[qIdx].ciPointer = (((bit8 *)(memoryAllocated->region[MPI_CI_INDEX].virtPtr)) + qIdx * 4); + /* ... and in the local structure we will use to copy to the HW configuration table */ + + /* CI base address */ + inQueueCfg.elementPriSizeCount= config->inboundQueues[qIdx].numElements | + (config->inboundQueues[qIdx].elementSize << SHIFT16) | + (config->inboundQueues[qIdx].priority << SHIFT30); + inQueueCfg.upperBaseAddress = saRoot->inboundQueue[qIdx].memoryRegion.physAddrUpper; + inQueueCfg.lowerBaseAddress = saRoot->inboundQueue[qIdx].memoryRegion.physAddrLower; + inQueueCfg.ciUpperBaseAddress = memoryAllocated->region[MPI_CI_INDEX].physAddrUpper; + inQueueCfg.ciLowerBaseAddress = memoryAllocated->region[MPI_CI_INDEX].physAddrLower + qIdx * 4; + + /* write the configured data of inbound queue to SPC GSM */ + mpiUpdateIBQueueCfgTable(agRoot, &inQueueCfg, MSGUCfgTblDWIdx, pcibar); + /* get inbound PI PCI Bar and Offset */ + /* get the PI PCI Bar offset and convert it to logical BAR */ + IB_PIPCIBar = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + IB_PIPCI_BAR)); + saRoot->inboundQueue[qIdx].PIPCIBar = mpiGetPCIBarIndex(agRoot, IB_PIPCIBar); + saRoot->inboundQueue[qIdx].PIPCIOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + IB_PIPCI_BAR_OFFSET)); + saRoot->inboundQueue[qIdx].qNumber = qIdx; + + memOffset += memSize; + + if ((0 == ((qIdx + 1) % MAX_QUEUE_EACH_MEM)) || + (qIdx == (maxinbound - 1))) + { + mIdx++; + indexoffset += MAX_QUEUE_EACH_MEM; + memOffset = 0; + } + + } /* else for memeory ok */ + } /* queue enable */ + } /* loop for inbound queue */ + + smTrace(hpDBG_VERY_LOUD,"73",0); + /* TP:73 outbound queues */ + + /* index offset */ + indexoffset = 0; + memOffset = 0; + /* Let's process the memory regions for the outbound queues */ + for(qIdx = 0; qIdx < maxoutbound; qIdx++) + { + /* point back to the begin then plus offset to next queue */ + MSGUCfgTblDWIdx = saveOffset; + MSGUCfgTblDWIdx += outboundoffset; + MSGUCfgTblDWIdx += (sizeof(spc_outboundQueueDescriptor_t) * qIdx); + + /* if the MPI configuration says that this queue is disabled ... */ + if(0 == config->outboundQueues[qIdx].numElements) + { + /* ... Clears the configuration table for this queue */ + outQueueCfg.upperBaseAddress = 0; + outQueueCfg.lowerBaseAddress = 0; + outQueueCfg.piUpperBaseAddress = 0; + outQueueCfg.piLowerBaseAddress = 0; + /* skip outQueueCfg.CIPCIBar = 0; read access only */ + /* skip outQueueCfg.CIOffset = 0; read access only */ + outQueueCfg.elementSizeCount = 0; + outQueueCfg.interruptVecCntDelay = 0; + + /* Updated the configuration table in SPC GSM */ + mpiUpdateOBQueueCfgTable(agRoot, &outQueueCfg, MSGUCfgTblDWIdx, pcibar); + } + + /* If the outbound queue is enabled, then ... */ + else + { + bit32 memSize = config->outboundQueues[qIdx].numElements * config->outboundQueues[qIdx].elementSize; + bit32 remainder = memSize & 127; + + /* Calculate the size of this queue padded to 128 bytes */ + if (remainder > 0) + { + memSize += (128 - remainder); + } + + /* ... first checks that the memory region has the right size */ + if((memoryAllocated->region[mIdx].totalLength - memOffset < memSize) || + (NULL == memoryAllocated->region[mIdx].virtPtr) || + (0 == memoryAllocated->region[mIdx].totalLength)) + { + SA_DBG1(("ERROR: The memory region does not have the right size for this outbound queue")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "m3"); + return AGSA_RC_FAILURE; + } + else + { + /* Then, using the MPI configuration argument, initializes the corresponding element on the MPI context ... */ + saRoot->outboundQueue[qIdx].numElements = config->outboundQueues[qIdx].numElements; + saRoot->outboundQueue[qIdx].elementSize = config->outboundQueues[qIdx].elementSize; + si_memcpy(&saRoot->outboundQueue[qIdx].memoryRegion, &memoryAllocated->region[mIdx], sizeof(mpiMem_t)); + saRoot->outboundQueue[qIdx].memoryRegion.virtPtr = + (bit8 *)saRoot->outboundQueue[qIdx].memoryRegion.virtPtr + memOffset; + saRoot->outboundQueue[qIdx].memoryRegion.physAddrLower += memOffset; + saRoot->outboundQueue[qIdx].memoryRegion.elementSize = memSize; + saRoot->outboundQueue[qIdx].memoryRegion.totalLength = memSize; + saRoot->outboundQueue[qIdx].memoryRegion.numElements = 1; + saRoot->outboundQueue[qIdx].producerIdx = 0; + saRoot->outboundQueue[qIdx].consumerIdx = 0; + saRoot->outboundQueue[qIdx].agRoot = agRoot; + + /* MPI memory region for outbound PIs are 3 */ + saRoot->outboundQueue[qIdx].piPointer = (((bit8 *)(memoryAllocated->region[MPI_CI_INDEX + 1].virtPtr))+ qIdx * 4); + /* ... and in the local structure we will use to copy to the HW configuration table */ + outQueueCfg.upperBaseAddress = saRoot->outboundQueue[qIdx].memoryRegion.physAddrUpper; + outQueueCfg.lowerBaseAddress = saRoot->outboundQueue[qIdx].memoryRegion.physAddrLower; + + /* PI base address */ + outQueueCfg.piUpperBaseAddress = memoryAllocated->region[MPI_CI_INDEX + 1].physAddrUpper; + outQueueCfg.piLowerBaseAddress = memoryAllocated->region[MPI_CI_INDEX + 1].physAddrLower + qIdx * 4; + outQueueCfg.elementSizeCount = config->outboundQueues[qIdx].numElements | + (config->outboundQueues[qIdx].elementSize << SHIFT16); + + /* enable/disable interrupt - use saSystemInterruptsActive() API */ + /* instead of ossaHwRegWrite(agRoot, MSGU_ODMR, 0); */ + /* Outbound Doorbell Auto disable */ + /* LL does not use ossaHwRegWriteExt(agRoot, PCIBAR1, SPC_ODAR, 0xffffffff); */ + if (config->outboundQueues[qIdx].interruptEnable) + { + /* enable interrupt flag bit30 of outbound table */ + outQueueCfg.elementSizeCount |= OB_PROPERTY_INT_ENABLE; + } + if(smIS_SPCV(agRoot)) + { + outQueueCfg.interruptVecCntDelay = ((config->outboundQueues[qIdx].interruptVector & INT_VEC_BITS ) << SHIFT24); + } + else + { + outQueueCfg.interruptVecCntDelay = (config->outboundQueues[qIdx].interruptDelay & INT_DELAY_BITS) | + ((config->outboundQueues[qIdx].interruptThreshold & INT_THR_BITS ) << SHIFT16) | + ((config->outboundQueues[qIdx].interruptVector & INT_VEC_BITS ) << SHIFT24); + } + + /* create a VectorIndex Bit Map */ + if (qIdx < OQ_NUM_32) + { + saRoot->interruptVecIndexBitMap[config->outboundQueues[qIdx].interruptVector] |= (1 << qIdx); + SA_DBG2(("mpiInitialize:below 32 saRoot->interruptVecIndexBitMap[config->outboundQueues[qIdx].interruptVector] 0x%08x\n",saRoot->interruptVecIndexBitMap[config->outboundQueues[qIdx].interruptVector])); + } + else + { + saRoot->interruptVecIndexBitMap1[config->outboundQueues[qIdx].interruptVector] |= (1 << (qIdx - OQ_NUM_32)); + SA_DBG2(("mpiInitialize:Above 32 saRoot->interruptVecIndexBitMap1[config->outboundQueues[qIdx].interruptVector] 0x%08x\n",saRoot->interruptVecIndexBitMap1[config->outboundQueues[qIdx].interruptVector])); + } + /* Update the outbound configuration table */ + mpiUpdateOBQueueCfgTable(agRoot, &outQueueCfg, MSGUCfgTblDWIdx, pcibar); + + /* read the CI PCIBar offset and convert it to logical bar */ + OB_CIPCIBar = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + OB_CIPCI_BAR)); + saRoot->outboundQueue[qIdx].CIPCIBar = mpiGetPCIBarIndex(agRoot, OB_CIPCIBar); + saRoot->outboundQueue[qIdx].CIPCIOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + OB_CIPCI_BAR_OFFSET)); + saRoot->outboundQueue[qIdx].DIntTOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + OB_DYNAMIC_COALES_OFFSET)); + saRoot->outboundQueue[qIdx].qNumber = qIdx; + + memOffset += memSize; + + if ((0 == ((qIdx + 1) % MAX_QUEUE_EACH_MEM)) || + (qIdx == (maxoutbound - 1))) + { + mIdx++; + indexoffset += MAX_QUEUE_EACH_MEM; + memOffset =0; + } + } + } + } + + /* calculate number of vectors */ + saRoot->numInterruptVectors = 0; + for (qIdx = 0; qIdx < MAX_NUM_VECTOR; qIdx++) + { + if ((saRoot->interruptVecIndexBitMap[qIdx]) || (saRoot->interruptVecIndexBitMap1[qIdx])) + { + (saRoot->numInterruptVectors)++; + } + } + + SA_DBG2(("mpiInitialize:(saRoot->numInterruptVectors) 0x%x\n",(saRoot->numInterruptVectors))); + + if(smIS_SPCV(agRoot)) + { + /* setup interrupt vector table */ + mpiWrIntVecTable(agRoot,config); + } + + if(smIS_SPCV(agRoot)) + { + mpiWrAnalogSetupTable(agRoot,config); + } + + /* setup phy analog registers */ + mpiWriteCALAll(agRoot, &config->phyAnalogConfig); + + { + bit32 pcibar = 0; + bit32 TableOffset; + pcibar = siGetPciBar(agRoot); + TableOffset = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); + TableOffset &= SCRATCH_PAD0_OFFSET_MASK; + SA_DBG1(("mpiInitialize: mpiContextTable TableOffset 0x%08X contains 0x%08X\n",TableOffset,ossaHwRegReadExt(agRoot, pcibar, TableOffset ))); + + SA_ASSERT( (ossaHwRegReadExt(agRoot, pcibar, TableOffset ) == 0x53434D50), "Config table signiture"); + + SA_DBG1(("mpiInitialize: AGSA_MPI_MAIN_CONFIGURATION_TABLE 0x%08X\n", 0)); + SA_DBG1(("mpiInitialize: AGSA_MPI_GENERAL_STATUS_TABLE 0x%08X\n", (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_GST_OFFSET) & 0xFFFF ))); + SA_DBG1(("mpiInitialize: AGSA_MPI_INBOUND_QUEUE_CONFIGURATION_TABLE 0x%08X\n", (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_IBQ_OFFSET) & 0xFFFF))); + SA_DBG1(("mpiInitialize: AGSA_MPI_OUTBOUND_QUEUE_CONFIGURATION_TABLE 0x%08X\n", (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_OBQ_OFFSET) & 0xFFFF))); + SA_DBG1(("mpiInitialize: AGSA_MPI_SAS_PHY_ANALOG_SETUP_TABLE 0x%08X\n", (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_ANALOG_SETUP_OFFSET) & 0xFFFF ))); + SA_DBG1(("mpiInitialize: AGSA_MPI_INTERRUPT_VECTOR_TABLE 0x%08X\n", (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_INT_VEC_TABLE_OFFSET) & 0xFFFF))); + SA_DBG1(("mpiInitialize: AGSA_MPI_PER_SAS_PHY_ATTRIBUTE_TABLE 0x%08X\n", (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_PHY_ATTRIBUTE_OFFSET) & 0xFFFF))); + SA_DBG1(("mpiInitialize: AGSA_MPI_OUTBOUND_QUEUE_FAILOVER_TABLE 0x%08X\n", (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_MOQFOT_MOQFOES) & 0xFFFF))); + + } + + if(agNULL != saRoot->swConfig.mpiContextTable ) + { + agsaMPIContext_t * context = (agsaMPIContext_t * )saRoot->swConfig.mpiContextTable; + bit32 length = saRoot->swConfig.mpiContextTablelen; + bit32 pcibar = 0; + bit32 TableOffset; + pcibar = siGetPciBar(agRoot); + TableOffset = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); + TableOffset &= SCRATCH_PAD0_OFFSET_MASK; + SA_DBG1(("mpiInitialize: mpiContextTable TableOffset 0x%08X contains 0x%08X\n",TableOffset,ossaHwRegReadExt(agRoot, pcibar, TableOffset ))); + + SA_ASSERT( (ossaHwRegReadExt(agRoot, pcibar, TableOffset ) == 0x53434D50), "Config table signiture"); + if ( (ossaHwRegReadExt(agRoot, pcibar, TableOffset ) != 0x53434D50)) + { + SA_DBG1(("mpiInitialize: TableOffset 0x%x reads 0x%x expect 0x%x \n",TableOffset,ossaHwRegReadExt(agRoot, pcibar, TableOffset ),0x53434D50)); + } + + if(context ) + { + SA_DBG1(("mpiInitialize: MPITableType 0x%x context->offset 0x%x context->value 0x%x\n",context->MPITableType,context->offset,context->value)); + while( length != 0) + { + switch(context->MPITableType) + { + + bit32 OffsetInMain; + case AGSA_MPI_MAIN_CONFIGURATION_TABLE: + SA_DBG1(("mpiInitialize: AGSA_MPI_MAIN_CONFIGURATION_TABLE %d 0x%x + 0x%x = 0x%x\n",context->MPITableType,TableOffset, context->offset, context->value)); + OffsetInMain = TableOffset; + ossaHwRegWriteExt(agRoot, pcibar, OffsetInMain + (context->offset * 4) , context->value); + break; + case AGSA_MPI_GENERAL_STATUS_TABLE: + SA_DBG1(("mpiInitialize: AGSA_MPI_GENERAL_STATUS_TABLE %d offset 0x%x + 0x%x = 0x%x\n",context->MPITableType ,TableOffset+MAIN_GST_OFFSET, context->offset, context->value )); + OffsetInMain = (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_GST_OFFSET ) & 0xFFFF) + TableOffset; + ossaHwRegWriteExt(agRoot, pcibar, OffsetInMain + (context->offset * 4), context->value); + break; + case AGSA_MPI_INBOUND_QUEUE_CONFIGURATION_TABLE: + SA_DBG1(("mpiInitialize: AGSA_MPI_INBOUND_QUEUE_CONFIGURATION_TABLE %d offset 0x%x + 0x%x = 0x%x\n",context->MPITableType,TableOffset+MAIN_IBQ_OFFSET, context->offset, context->value)); + OffsetInMain = (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_IBQ_OFFSET ) & 0xFFFF) + TableOffset; + ossaHwRegWriteExt(agRoot, pcibar, OffsetInMain + (context->offset * 4), context->value); + break; + case AGSA_MPI_OUTBOUND_QUEUE_CONFIGURATION_TABLE: + SA_DBG1(("mpiInitialize: AGSA_MPI_OUTBOUND_QUEUE_CONFIGURATION_TABLE %d offset 0x%x + 0x%x = 0x%x\n",context->MPITableType,TableOffset+MAIN_OBQ_OFFSET, context->offset, context->value)); + OffsetInMain = (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_OBQ_OFFSET ) & 0xFFFF) + TableOffset; + ossaHwRegWriteExt(agRoot, pcibar, OffsetInMain + (context->offset * 4), context->value); + break; + case AGSA_MPI_SAS_PHY_ANALOG_SETUP_TABLE: + SA_DBG1(("mpiInitialize: AGSA_MPI_SAS_PHY_ANALOG_SETUP_TABLE %d offset 0x%x + 0x%x = 0x%x\n",context->MPITableType,TableOffset+MAIN_ANALOG_SETUP_OFFSET, context->offset, context->value)); + OffsetInMain = (ossaHwRegReadExt(agRoot, pcibar, TableOffset+ MAIN_ANALOG_SETUP_OFFSET) & 0xFFFF) + TableOffset; + ossaHwRegWriteExt(agRoot, pcibar, OffsetInMain + (context->offset * 4), context->value); + break; + case AGSA_MPI_INTERRUPT_VECTOR_TABLE: + SA_DBG1(("mpiInitialize: AGSA_MPI_INTERRUPT_VECTOR_TABLE %d offset 0x%x + 0x%x = 0x%x\n",context->MPITableType,TableOffset+MAIN_INT_VEC_TABLE_OFFSET, context->offset, context->value)); + OffsetInMain = (ossaHwRegReadExt(agRoot, pcibar, TableOffset+ MAIN_INT_VEC_TABLE_OFFSET) & 0xFFFF) + TableOffset; + ossaHwRegWriteExt(agRoot, pcibar, OffsetInMain + (context->offset * 4), context->value); + break; + case AGSA_MPI_PER_SAS_PHY_ATTRIBUTE_TABLE: + SA_DBG1(("mpiInitialize: AGSA_MPI_PER_SAS_PHY_ATTRIBUTE_TABLE %d offset 0x%x + 0x%x = 0x%x\n",context->MPITableType,TableOffset+MAIN_PHY_ATTRIBUTE_OFFSET, context->offset, context->value)); + OffsetInMain = (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_PHY_ATTRIBUTE_OFFSET ) & 0xFFFF) + TableOffset; + ossaHwRegWriteExt(agRoot, pcibar, OffsetInMain + (context->offset * 4), context->value); + break; + case AGSA_MPI_OUTBOUND_QUEUE_FAILOVER_TABLE: + SA_DBG1(("mpiInitialize: AGSA_MPI_OUTBOUND_QUEUE_FAILOVER_TABLE %d offset 0x%x + 0x%x = 0x%x\n",context->MPITableType,TableOffset+MAIN_MOQFOT_MOQFOES, context->offset, context->value)); + OffsetInMain = (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_MOQFOT_MOQFOES ) & 0xFFFF) + TableOffset; + ossaHwRegWriteExt(agRoot, pcibar, OffsetInMain + (context->offset * 4), context->value); + break; + default: + SA_DBG1(("mpiInitialize: error MPITableType unknown %d offset 0x%x value 0x%x\n",context->MPITableType, context->offset, context->value)); + break; + } + if(smIS_SPC12V(agRoot)) + { + if (saRoot->ControllerInfo.fwInterfaceRev > 0x301 ) + { + SA_DBG1(("mpiInitialize: MAIN_AWT_MIDRANGE 0x%08X\n", + ossaHwRegReadExt(agRoot, pcibar, TableOffset + MAIN_AWT_MIDRANGE) + )); + } + } + if(length >= sizeof(agsaMPIContext_t)) + { + length -= sizeof(agsaMPIContext_t); + context++; + + } + else + { + length = 0; + } + } + + } + + SA_DBG1(("mpiInitialize: context %p saRoot->swConfig.mpiContextTable %p %d\n",context,saRoot->swConfig.mpiContextTable,context == saRoot->swConfig.mpiContextTable ? 1 : 0)); + + if ( (ossaHwRegReadExt(agRoot, pcibar, TableOffset ) != 0x53434D50)) + { + SA_DBG1(("mpiInitialize:TableOffset 0x%x reads 0x%x expect 0x%x \n",TableOffset,ossaHwRegReadExt(agRoot, pcibar, TableOffset ),0x53434D50)); + } + + SA_ASSERT( (ossaHwRegReadExt(agRoot, pcibar, TableOffset ) == 0x53434D50), "Config table signiture After"); + } + /* At this point the Message Unit configuration table is set up. Now we need to ring the doorbell */ + togglevalue = 0; + + smTrace(hpDBG_VERY_LOUD,"74", siHalRegReadExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET )); + /* TP:74 Doorbell */ + + /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the table is updated */ + siHalRegWriteExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE); + + if(siHalRegReadExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET ) & SPC_MSGU_CFG_TABLE_UPDATE) + { + SA_DBG1(("mpiInitialize: SPC_MSGU_CFG_TABLE_UPDATE (0x%X) \n", siHalRegReadExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET))); + } + else + { + SA_DBG1(("mpiInitialize: SPC_MSGU_CFG_TABLE_UPDATE not set (0x%X)\n", siHalRegReadExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET))); + ossaStallThread(agRoot, WAIT_INCREMENT); + } + + smTrace(hpDBG_VERY_LOUD,"A5", siHalRegReadExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET )); + /* TP:A5 Doorbell */ + +/* +// ossaHwRegWrite(agRoot, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE); + MSGU_WRITE_IDR(SPC_MSGU_CFG_TABLE_UPDATE); +*/ + + + /* wait until Inbound DoorBell Clear Register toggled */ +WaitLonger: + max_wait_time = WAIT_SECONDS(gWait_2); /* 2 sec */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + value = MSGU_READ_IDR; + value &= SPC_MSGU_CFG_TABLE_UPDATE; + } while ((value != togglevalue) && (max_wait_count -= WAIT_INCREMENT)); + + smTrace(hpDBG_VERY_LOUD,"80", max_wait_count); + /* TP:80 TP max_wait_count */ + if (!max_wait_count && mpiStartToggleFailed < 5 ) + { + SA_DBG1(("mpiInitialize: mpiStartToggleFailed count %d\n", mpiStartToggleFailed)); + mpiStartToggleFailed++; + goto WaitLonger; + } + + if (!max_wait_count ) + { + + SA_DBG1(("mpiInitialize: TIMEOUT:IBDB value/toggle = 0x%x 0x%x\n", value, togglevalue)); + MSGUCfgTblDWIdx = saveOffset; + GSTLenMPIS = ossaHwRegReadExt(agRoot, pcibar, (bit32)MSGUCfgTblDWIdx + (bit32)(mainCfg.GSTOffset + GST_GSTLEN_MPIS_OFFSET)); + SA_DBG1(("mpiInitialize: MPI State = 0x%x\n", GSTLenMPIS)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'f', "m3"); + return AGSA_RC_FAILURE; + } + smTrace(hpDBG_VERY_LOUD,"81", mpiStartToggleFailed ); + /* TP:81 TP */ + + /* check the MPI-State for initialization */ + MSGUCfgTblDWIdx = saveOffset; + GSTLenMPIS = ossaHwRegReadExt(agRoot, pcibar, (bit32)MSGUCfgTblDWIdx + (bit32)(mainCfg.GSTOffset + GST_GSTLEN_MPIS_OFFSET)); + if ( (GST_MPI_STATE_UNINIT == (GSTLenMPIS & GST_MPI_STATE_MASK)) && ( mpiUnInitFailed < 5 ) ) + { + SA_DBG1(("mpiInitialize: MPI State = 0x%x mpiUnInitFailed count %d\n", GSTLenMPIS & GST_MPI_STATE_MASK,mpiUnInitFailed)); + ossaStallThread(agRoot, (20 * 1000)); + + mpiUnInitFailed++; + goto WaitLonger; + } + + if (GST_MPI_STATE_INIT != (GSTLenMPIS & GST_MPI_STATE_MASK)) + { + SA_DBG1(("mpiInitialize: Error Not GST_MPI_STATE_INIT MPI State = 0x%x\n", GSTLenMPIS & GST_MPI_STATE_MASK)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'g', "m3"); + return AGSA_RC_FAILURE; + } + smTrace(hpDBG_VERY_LOUD,"82", 0); + /* TP:82 TP */ + + /* check MPI Initialization error */ + GSTLenMPIS = GSTLenMPIS >> SHIFT16; + if (0x0000 != GSTLenMPIS) + { + SA_DBG1(("mpiInitialize: MPI Error = 0x%x\n", GSTLenMPIS)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'h', "m3"); + return AGSA_RC_FAILURE; + } + smTrace(hpDBG_VERY_LOUD,"83", 0); + /* TP:83 TP */ + + /* reread IQ PI offset from SPC if IQ/OQ > 32 */ + if ((maxinbound > IQ_NUM_32) || (maxoutbound > OQ_NUM_32)) + { + for(qIdx = 0; qIdx < maxinbound; qIdx++) + { + /* point back to the begin then plus offset to next queue */ + MSGUCfgTblDWIdx = saveOffset; + MSGUCfgTblDWIdx += inboundoffset; + MSGUCfgTblDWIdx += (sizeof(spc_inboundQueueDescriptor_t) * qIdx); + saRoot->inboundQueue[qIdx].PIPCIOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + IB_PIPCI_BAR_OFFSET)); + } + } + smTrace(hpDBG_VERY_LOUD,"84", 0); + /* TP:84 TP */ + + /* at least one inbound queue and one outbound queue enabled */ + if ((0 == config->inboundQueues[0].numElements) || (0 == config->outboundQueues[0].numElements)) + { + SA_DBG1(("mpiInitialize: Error,IQ0 or OQ0 have to enable\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'i', "m3"); + return AGSA_RC_FAILURE; + } + smTrace(hpDBG_VERY_LOUD,"85", 0); + /* TP:85 TP */ + + /* clean the inbound queues */ + for (i = 0; i < config->numInboundQueues; i ++) + { + if(0 != config->inboundQueues[i].numElements) + { + circularIQ = &saRoot->inboundQueue[i]; + si_memset(circularIQ->memoryRegion.virtPtr, 0, circularIQ->memoryRegion.totalLength); + si_memset(saRoot->inboundQueue[i].ciPointer, 0, sizeof(bit32)); + + if(smIS_SPCV(agRoot)) + { + ossaHwRegWriteExt(circularIQ->agRoot, circularIQ->PIPCIBar, circularIQ->PIPCIOffset, 0); + SA_DBG1(("mpiInitialize: SPC V writes IQ %2d offset 0x%x\n",i ,circularIQ->PIPCIOffset)); + } + } + } + smTrace(hpDBG_VERY_LOUD,"86", 0); + /* TP:86 TP */ + + /* clean the outbound queues */ + for (i = 0; i < config->numOutboundQueues; i ++) + { + if(0 != config->outboundQueues[i].numElements) + { + circularOQ = &saRoot->outboundQueue[i]; + si_memset(circularOQ->memoryRegion.virtPtr, 0, circularOQ->memoryRegion.totalLength); + si_memset(saRoot->outboundQueue[i].piPointer, 0, sizeof(bit32)); + if(smIS_SPCV(agRoot)) + { + ossaHwRegWriteExt(circularOQ->agRoot, circularOQ->CIPCIBar, circularOQ->CIPCIOffset, 0); + SA_DBG2(("mpiInitialize: SPC V writes OQ %2d offset 0x%x\n",i ,circularOQ->CIPCIOffset)); + } + + } + } + + + smTrace(hpDBG_VERY_LOUD,"75",0); + /* TP:75 AAP1 IOP */ + + /* read back AAP1 and IOP event log address and size */ + MSGUCfgTblDWIdx = saveOffset; + value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_ADDR_HI)); + saRoot->mainConfigTable.upperEventLogAddress = value; + SA_DBG1(("mpiInitialize: upperEventLogAddress 0x%x\n", value)); + value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_ADDR_LO)); + saRoot->mainConfigTable.lowerEventLogAddress = value; + SA_DBG1(("mpiInitialize: lowerEventLogAddress 0x%x\n", value)); + value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_BUFF_SIZE)); + saRoot->mainConfigTable.eventLogSize = value; + SA_DBG1(("mpiInitialize: eventLogSize 0x%x\n", value)); + value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_OPTION)); + saRoot->mainConfigTable.eventLogOption = value; + SA_DBG1(("mpiInitialize: eventLogOption 0x%x\n", value)); + SA_DBG1(("mpiInitialize: EventLog dd /p %08X`%08X L %x\n",saRoot->mainConfigTable.upperEventLogAddress,saRoot->mainConfigTable.lowerEventLogAddress,saRoot->mainConfigTable.eventLogSize/4 )); + + value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_ADDR_HI)); + saRoot->mainConfigTable.upperIOPeventLogAddress = value; + SA_DBG1(("mpiInitialize: upperIOPLogAddress 0x%x\n", value)); + value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_ADDR_LO)); + saRoot->mainConfigTable.lowerIOPeventLogAddress = value; + SA_DBG1(("mpiInitialize: lowerIOPLogAddress 0x%x\n", value)); + SA_DBG1(("mpiInitialize: IOPLog dd /p %08X`%08X L %x\n",saRoot->mainConfigTable.upperIOPeventLogAddress,saRoot->mainConfigTable.lowerIOPeventLogAddress,saRoot->mainConfigTable.IOPeventLogSize/4 )); + value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_BUFF_SIZE)); + saRoot->mainConfigTable.IOPeventLogSize = value; + SA_DBG1(("mpiInitialize: IOPeventLogSize 0x%x\n", value)); + value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_OPTION)); + saRoot->mainConfigTable.IOPeventLogOption = value; + SA_DBG1(("mpiInitialize: IOPeventLogOption 0x%x\n", value)); + value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_FATAL_ERROR_INTERRUPT)); + +#ifdef SA_PRINTOUT_IN_WINDBG +#ifndef DBG + DbgPrint("mpiInitialize: EventLog (%d) dd /p %08X`%08X L %x\n", + saRoot->mainConfigTable.eventLogOption, + saRoot->mainConfigTable.upperEventLogAddress, + saRoot->mainConfigTable.lowerEventLogAddress, + saRoot->mainConfigTable.eventLogSize/4 ); + DbgPrint("mpiInitialize: IOPLog (%d) dd /p %08X`%08X L %x\n", + saRoot->mainConfigTable.IOPeventLogOption, + saRoot->mainConfigTable.upperIOPeventLogAddress, + saRoot->mainConfigTable.lowerIOPeventLogAddress, + saRoot->mainConfigTable.IOPeventLogSize/4 ); +#endif /* DBG */ +#endif /* SA_PRINTOUT_IN_WINDBG */ + + saRoot->mainConfigTable.FatalErrorInterrupt = value; + smTrace(hpDBG_VERY_LOUD,"76",value); + /* TP:76 FatalErrorInterrupt */ + + SA_DBG1(("mpiInitialize: hwConfig->hwOption %X\n", saRoot->hwConfig.hwOption )); + + SA_DBG1(("mpiInitialize: FatalErrorInterrupt 0x%x\n", value)); + + /* read back Register Dump offset and length */ + value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_FATAL_ERROR_RDUMP0_OFFSET)); + saRoot->mainConfigTable.FatalErrorDumpOffset0 = value; + SA_DBG1(("mpiInitialize: FatalErrorDumpOffset0 0x%x\n", value)); + value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_FATAL_ERROR_RDUMP0_LENGTH)); + saRoot->mainConfigTable.FatalErrorDumpLength0 = value; + SA_DBG1(("mpiInitialize: FatalErrorDumpLength0 0x%x\n", value)); + value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_FATAL_ERROR_RDUMP1_OFFSET)); + saRoot->mainConfigTable.FatalErrorDumpOffset1 = value; + SA_DBG1(("mpiInitialize: FatalErrorDumpOffset1 0x%x\n", value)); + value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_FATAL_ERROR_RDUMP1_LENGTH)); + saRoot->mainConfigTable.FatalErrorDumpLength1 = value; + SA_DBG1(("mpiInitialize: FatalErrorDumpLength1 0x%x\n", value)); + + value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_PRECTD_PRESETD)); + saRoot->mainConfigTable.PortRecoveryTimerPortResetTimer = value; + + SA_DBG1(("mpiInitialize: PortRecoveryTimerPortResetTimer 0x%x\n", value)); + value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IRAD_RESERVED)); + saRoot->mainConfigTable.InterruptReassertionDelay = value; + + SA_DBG1(("mpiInitialize: InterruptReassertionDelay 0x%x\n", value)); + + + if(smIS_SPCV(agRoot)) + { + bit32 sp1; + sp1= ossaHwRegRead(agRoot,V_Scratchpad_1_Register ); + if(SCRATCH_PAD1_V_ERROR_STATE(sp1)) + { + SA_DBG1(("mpiInitialize: SCRATCH_PAD1_V_ERROR_STAT 0x%x\n",sp1 )); + ret = AGSA_RC_FAILURE; + } + + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'j', "m3"); + return ret; +} + +/*******************************************************************************/ +/** \fn mpiWaitForConfigTable(agsaRoot_t *agRoot, spc_configMainDescriptor_t *config) + * \brief Reading and Writing the Configuration Table + * \param agsaRoot Pointer to a data structure containing LL layer context handles + * \param config Pointer to Configuration Table + * + * Return: + * AGSA_RC_SUCCESS if read the configuration table from SPC sucessful + * AGSA_RC_FAILURE if read the configuration table from SPC failed + */ +/*******************************************************************************/ +GLOBAL bit32 mpiWaitForConfigTable(agsaRoot_t *agRoot, + spc_configMainDescriptor_t *config) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + bit32 MSGUCfgTblBase, ret = AGSA_RC_SUCCESS; + bit32 CfgTblDWIdx; + bit32 value, value1; + bit32 max_wait_time; + bit32 max_wait_count; + bit32 Signature, ExpSignature; + bit8 pcibar; + + SA_DBG2(("mpiWaitForConfigTable: Entering\n")); + SA_ASSERT(NULL != agRoot, "agRoot argument cannot be null"); + + smTraceFuncEnter(hpDBG_VERY_LOUD,"m4"); + + + /* check error state */ + value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1,MSGU_SCRATCH_PAD_1); + value1 = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2,MSGU_SCRATCH_PAD_2); + + if( smIS_SPC(agRoot) ) + { + SA_DBG1(("mpiWaitForConfigTable: Waiting for SPC FW becoming ready.P1 0x%X P2 0x%X\n",value,value1)); + + /* check AAP error */ + if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) + { + /* error state */ + SA_DBG1(("mpiWaitForConfigTable: AAP error state and code 0x%x, ScratchPad2=0x%x\n", value, value1)); +#if defined(SALLSDK_DEBUG) + SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD0 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0))); + SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD3 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3,MSGU_SCRATCH_PAD_3))); +#endif + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "m4"); + return AGSA_RC_FAILURE; + } + + /* check IOP error */ + if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) + { + /* error state */ + SA_DBG1(("mpiWaitForConfigTable: IOP error state and code 0x%x, ScratchPad1=0x%x\n", value1, value)); +#if defined(SALLSDK_DEBUG) + SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD0 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0))); + SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD3 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3,MSGU_SCRATCH_PAD_3))); +#endif + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "m4"); + return AGSA_RC_FAILURE; + } + + /* bit 4-31 of scratch pad1 should be zeros if it is not in error state */ +#ifdef DONT_DO /* */ + if (value & SCRATCH_PAD1_STATE_MASK) + { + /* error case */ + SA_DBG1(("mpiWaitForConfigTable: wrong state failure, scratchPad1 0x%x\n", value)); + SA_DBG1(("mpiWaitForConfigTable: ScratchPad0 AAP error code 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0))); +#if defined(SALLSDK_DEBUG) + SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD2 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2,MSGU_SCRATCH_PAD_0))); + SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD3 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3,MSGU_SCRATCH_PAD_3))); +#endif + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "m4"); + return AGSA_RC_FAILURE; + } + + /* bit 4-31 of scratch pad2 should be zeros if it is not in error state */ + if (value1 & SCRATCH_PAD2_STATE_MASK) + { + /* error case */ + SA_DBG1(("mpiWaitForConfigTable: wrong state failure, scratchPad2 0x%x\n", value1)); + SA_DBG1(("mpiWaitForConfigTable: ScratchPad3 IOP error code 0x%x\n",siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3,MSGU_SCRATCH_PAD_3) )); +#if defined(SALLSDK_DEBUG) + SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD0 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0))); + SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD1 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1,MSGU_SCRATCH_PAD_1))); +#endif + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "m4"); + + return AGSA_RC_FAILURE; + } +#endif /* DONT_DO */ + + /* checking the fw and IOP in ready state */ + max_wait_time = WAIT_SECONDS(gWait_2); /* 2 sec timeout */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); + /* wait until scratch pad 1 and 2 registers in ready state */ + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + value =siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1,MSGU_SCRATCH_PAD_1) & SCRATCH_PAD1_RDY; + value1 =siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2,MSGU_SCRATCH_PAD_2) & SCRATCH_PAD2_RDY; + if(smIS_SPCV(agRoot)) + { + SA_DBG1(("mpiWaitForConfigTable:VEN_DEV_SPCV force SCRATCH_PAD2 RDY 1 %08X 2 %08X\n" ,value,value1)); + value1 =3; + } + + if ((max_wait_count -= WAIT_INCREMENT) == 0) + { + SA_DBG1(("mpiWaitForConfigTable: Timeout!! SCRATCH_PAD1/2 value = 0x%x 0x%x\n", value, value1)); + break; + } + } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY)); + + if (!max_wait_count) + { + SA_DBG1(("mpiWaitForConfigTable: timeout failure\n")); +#if defined(SALLSDK_DEBUG) + SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD0 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0))); + SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD3 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3,MSGU_SCRATCH_PAD_3))); +#endif + smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "m4"); + return AGSA_RC_FAILURE; + } + + }else + { + + if(((value & SCRATCH_PAD1_V_BOOTSTATE_HDA_SEEPROM ) == SCRATCH_PAD1_V_BOOTSTATE_HDA_SEEPROM)) + { + SA_DBG1(("mpiWaitForConfigTable: HDA mode set in SEEPROM SP1 0x%X\n",value)); + } + if(((value & SCRATCH_PAD1_V_READY) != SCRATCH_PAD1_V_READY) || + (value == 0xffffffff)) + { + SA_DBG1(("mpiWaitForConfigTable: Waiting for _V_ FW becoming ready.P1 0x%X P2 0x%X\n",value,value1)); + + /* checking the fw and IOP in ready state */ + max_wait_time = WAIT_SECONDS(gWait_2); /* 2 sec timeout */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); + /* wait until scratch pad 1 and 2 registers in ready state */ + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1,MSGU_SCRATCH_PAD_1); + value1 = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2,MSGU_SCRATCH_PAD_2); + + if ((max_wait_count -= WAIT_INCREMENT) == 0) + { + SA_DBG1(("mpiWaitForConfigTable: Timeout!! SCRATCH_PAD1/2 value = 0x%x 0x%x\n", value, value1)); + return AGSA_RC_FAILURE; + } + } while (((value & SCRATCH_PAD1_V_READY) != SCRATCH_PAD1_V_READY) || + (value == 0xffffffff)); + } + } + + + SA_DBG1(("mpiWaitForConfigTable: FW Ready, SCRATCH_PAD1/2 value = 0x%x 0x%x\n", value, value1)); + + /* read scratch pad0 to get PCI BAR and offset of configuration table */ + MSGUCfgTblBase = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); + /* get offset */ + CfgTblDWIdx = MSGUCfgTblBase & SCRATCH_PAD0_OFFSET_MASK; + /* get PCI BAR */ + MSGUCfgTblBase = (MSGUCfgTblBase & SCRATCH_PAD0_BAR_MASK) >> SHIFT26; + + if(smIS_SPC(agRoot)) + { + if( smIS_spc8081(agRoot)) + { + if (BAR4 != MSGUCfgTblBase) + { + SA_DBG1(("mpiWaitForConfigTable: smIS_spc8081 PCI BAR is not BAR4, bar=0x%x - failure\n", MSGUCfgTblBase)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'f', "m4"); + return AGSA_RC_FAILURE; + } + } + else + { + if (BAR5 != MSGUCfgTblBase) + { + SA_DBG1(("mpiWaitForConfigTable: PCI BAR is not BAR5, bar=0x%x - failure\n", MSGUCfgTblBase)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'g', "m4"); + return AGSA_RC_FAILURE; + } + } + } + + /* convert the PCI BAR to logical bar number */ + pcibar = (bit8)mpiGetPCIBarIndex(agRoot, MSGUCfgTblBase); + + /* read signature from the configuration table */ + Signature = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx); + + /* Error return if the signature is not "PMCS" */ + ExpSignature = ('P') | ('M' << SHIFT8) | ('C' << SHIFT16) | ('S' << SHIFT24); + + if (Signature != ExpSignature) + { + SA_DBG1(("mpiWaitForConfigTable: Signature value = 0x%x\n", Signature)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'h', "m4"); + return AGSA_RC_FAILURE; + } + + /* save Signature */ + si_memcpy(&config->Signature, &Signature, sizeof(Signature)); + + /* read Interface Revsion from the configuration table */ + config->InterfaceRev = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_INTERFACE_REVISION); + + /* read FW Revsion from the configuration table */ + config->FWRevision = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_FW_REVISION); + + /* read Max Outstanding IO from the configuration table */ + config->MaxOutstandingIO = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_MAX_OUTSTANDING_IO_OFFSET); + + /* read Max SGL and Max Devices from the configuration table */ + config->MDevMaxSGL = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_MAX_SGL_OFFSET); + + /* read Controller Cap Flags from the configuration table */ + config->ContrlCapFlag = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_CNTRL_CAP_OFFSET); + + /* read GST Table Offset from the configuration table */ + config->GSTOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_GST_OFFSET); + + /* read Inbound Queue Offset from the configuration table */ + config->inboundQueueOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_IBQ_OFFSET); + + /* read Outbound Queue Offset from the configuration table */ + config->outboundQueueOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_OBQ_OFFSET); + + + if(smIS_SPCV(agRoot)) + { + ;/* SPCV - reserved field */ + } + else + { + /* read HDA Flags from the configuration table */ + config->HDAModeFlags = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_HDA_FLAGS_OFFSET); + } + + /* read analog Setting offset from the configuration table */ + config->analogSetupTblOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_ANALOG_SETUP_OFFSET); + + if(smIS_SPCV(agRoot)) + { + ;/* SPCV - reserved field */ + /* read interrupt vector table offset */ + config->InterruptVecTblOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_INT_VEC_TABLE_OFFSET); + /* read phy attribute table offset */ + config->phyAttributeTblOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_PHY_ATTRIBUTE_OFFSET); + SA_DBG1(("mpiWaitForConfigTable: INT Vector Tble Offset = 0x%x\n", config->InterruptVecTblOffset)); + SA_DBG1(("mpiWaitForConfigTable: Phy Attribute Tble Offset = 0x%x\n", config->phyAttributeTblOffset)); + } + else + { + ;/* SPC - Not used */ + } + + /* read Error Dump Offset and Length */ + config->FatalErrorDumpOffset0 = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_FATAL_ERROR_RDUMP0_OFFSET); + config->FatalErrorDumpLength0 = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_FATAL_ERROR_RDUMP0_LENGTH); + config->FatalErrorDumpOffset1 = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_FATAL_ERROR_RDUMP1_OFFSET); + config->FatalErrorDumpLength1 = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_FATAL_ERROR_RDUMP1_LENGTH); + + SA_DBG1(("mpiWaitForConfigTable: Interface Revision value = 0x%08x\n", config->InterfaceRev)); + SA_DBG1(("mpiWaitForConfigTable: FW Revision value = 0x%08x\n", config->FWRevision)); + + if(smIS_SPC(agRoot)) + { + SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%08x\n", STSDK_LL_SPC_VERSION)); + } + if(smIS_SPC6V(agRoot)) + { + SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%08x\n",STSDK_LL_VERSION )); + } + if(smIS_SPC12V(agRoot)) + { + SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%08x\n",STSDK_LL_12G_VERSION )); + } + + SA_DBG1(("mpiWaitForConfigTable: MaxOutstandingIO value = 0x%08x\n", config->MaxOutstandingIO)); + SA_DBG1(("mpiWaitForConfigTable: MDevMaxSGL value = 0x%08x\n", config->MDevMaxSGL)); + SA_DBG1(("mpiWaitForConfigTable: ContrlCapFlag value = 0x%08x\n", config->ContrlCapFlag)); + SA_DBG1(("mpiWaitForConfigTable: GSTOffset value = 0x%08x\n", config->GSTOffset)); + SA_DBG1(("mpiWaitForConfigTable: inboundQueueOffset value = 0x%08x\n", config->inboundQueueOffset)); + SA_DBG1(("mpiWaitForConfigTable: outboundQueueOffset value = 0x%08x\n", config->outboundQueueOffset)); + SA_DBG1(("mpiWaitForConfigTable: FatalErrorDumpOffset0 value = 0x%08x\n", config->FatalErrorDumpOffset0)); + SA_DBG1(("mpiWaitForConfigTable: FatalErrorDumpLength0 value = 0x%08x\n", config->FatalErrorDumpLength0)); + SA_DBG1(("mpiWaitForConfigTable: FatalErrorDumpOffset1 value = 0x%08x\n", config->FatalErrorDumpOffset1)); + SA_DBG1(("mpiWaitForConfigTable: FatalErrorDumpLength1 value = 0x%08x\n", config->FatalErrorDumpLength1)); + + + SA_DBG1(("mpiWaitForConfigTable: HDAModeFlags value = 0x%08x\n", config->HDAModeFlags)); + SA_DBG1(("mpiWaitForConfigTable: analogSetupTblOffset value = 0x%08x\n", config->analogSetupTblOffset)); + + /* check interface version */ + + if(smIS_SPC6V(agRoot)) + { + if (config->InterfaceRev != STSDK_LL_INTERFACE_VERSION) + { + SA_DBG1(("mpiWaitForConfigTable: V sTSDK interface ver. 0x%x does not match InterfaceRev 0x%x warning!\n", STSDK_LL_INTERFACE_VERSION, config->InterfaceRev)); + ret = AGSA_RC_VERSION_UNTESTED; + if ((config->InterfaceRev & STSDK_LL_INTERFACE_VERSION_IGNORE_MASK) != (STSDK_LL_INTERFACE_VERSION & STSDK_LL_INTERFACE_VERSION_IGNORE_MASK)) + { + SA_DBG1(("mpiWaitForConfigTable: V sTSDK interface ver. 0x%x incompatible with InterfaceRev 0x%x warning!\n", STSDK_LL_INTERFACE_VERSION, config->InterfaceRev)); + ret = AGSA_RC_VERSION_INCOMPATIBLE; + smTraceFuncExit(hpDBG_VERY_LOUD, 'i', "m4"); + return ret; + } + } + } + else if(smIS_SPC12V(agRoot)) + { + if (config->InterfaceRev != STSDK_LL_12G_INTERFACE_VERSION) + { + SA_DBG1(("mpiWaitForConfigTable: 12g V sTSDK interface ver. 0x%x does not match InterfaceRev 0x%x warning!\n", STSDK_LL_12G_INTERFACE_VERSION, config->InterfaceRev)); + ret = AGSA_RC_VERSION_UNTESTED; + if ((config->InterfaceRev & STSDK_LL_INTERFACE_VERSION_IGNORE_MASK) != (STSDK_LL_12G_INTERFACE_VERSION & STSDK_LL_INTERFACE_VERSION_IGNORE_MASK)) + { + SA_DBG1(("mpiWaitForConfigTable: V sTSDK interface ver. 0x%x incompatible with InterfaceRev 0x%x warning!\n", STSDK_LL_12G_INTERFACE_VERSION, config->InterfaceRev)); + ret = AGSA_RC_VERSION_INCOMPATIBLE; + ret = AGSA_RC_VERSION_UNTESTED; + smTraceFuncExit(hpDBG_VERY_LOUD, 'j', "m4"); + return ret; + } + } + } + else + { + if (config->InterfaceRev != STSDK_LL_OLD_INTERFACE_VERSION) + { + SA_DBG1(("mpiWaitForConfigTable: SPC sTSDK interface ver. 0x%08x not compatible with InterfaceRev 0x%x warning!\n", STSDK_LL_INTERFACE_VERSION, config->InterfaceRev)); + ret = AGSA_RC_VERSION_INCOMPATIBLE; + smTraceFuncExit(hpDBG_VERY_LOUD, 'k', "m4"); + return ret; + } + + } + + + /* Check FW versions */ + if(smIS_SPC6V(agRoot)) + { + SA_DBG1(("mpiWaitForConfigTable:6 sTSDK ver. sa.h 0x%08x config 0x%08x\n", STSDK_LL_VERSION, config->FWRevision)); + /* check FW and LL sTSDK version */ + if (config->FWRevision != MATCHING_V_FW_VERSION ) + { + if (config->FWRevision > MATCHING_V_FW_VERSION) + { + SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x hadn't tested with FW ver. 0x%08x warning!\n", STSDK_LL_VERSION, config->FWRevision)); + ret = AGSA_RC_VERSION_UNTESTED; + } + + else if (config->FWRevision < MIN_FW_SPCVE_VERSION_SUPPORTED) + { + SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x not compatible with FW ver. 0x%08x warning!\n", STSDK_LL_VERSION, config->FWRevision)); + ret = AGSA_RC_VERSION_INCOMPATIBLE; + smTraceFuncExit(hpDBG_VERY_LOUD, 'l', "m4"); + return ret; + } + else + { + SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x mismatch with FW ver. 0x%08x warning!\n",STSDK_LL_VERSION , config->FWRevision)); + ret = AGSA_RC_VERSION_UNTESTED; + } + } + }else if(smIS_SPC12V(agRoot)) + { + SA_DBG1(("mpiWaitForConfigTable:12 sTSDK ver. sa.h 0x%08x config 0x%08x\n", STSDK_LL_12G_VERSION, config->FWRevision)); + /* check FW and LL sTSDK version */ + if (config->FWRevision != MATCHING_12G_V_FW_VERSION ) + { + if (config->FWRevision > MATCHING_12G_V_FW_VERSION) + { + SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x hadn't tested with FW ver. 0x%08x warning!\n", STSDK_LL_12G_VERSION, config->FWRevision)); + ret = AGSA_RC_VERSION_UNTESTED; + } + + else if (config->FWRevision < MIN_FW_12G_SPCVE_VERSION_SUPPORTED) + { + SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x not compatible with FW ver. 0x%08x warning!\n", STSDK_LL_12G_VERSION, config->FWRevision)); + ret = AGSA_RC_VERSION_INCOMPATIBLE; + smTraceFuncExit(hpDBG_VERY_LOUD, 'm', "m4"); + return ret; + } + else + { + SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x mismatch with FW ver. 0x%08x warning!\n",STSDK_LL_12G_VERSION , config->FWRevision)); + ret = AGSA_RC_VERSION_UNTESTED; + } + } + } + else + { + if (config->FWRevision != MATCHING_SPC_FW_VERSION ) + { + if (config->FWRevision > MATCHING_SPC_FW_VERSION) + { + SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x hadn't tested with FW ver. 0x%08x warning!\n", STSDK_LL_SPC_VERSION, config->FWRevision)); + ret = AGSA_RC_VERSION_UNTESTED; + } + else if (config->FWRevision < MIN_FW_SPC_VERSION_SUPPORTED) + { + SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x not compatible with FW ver. 0x%08x warning!\n", STSDK_LL_SPC_VERSION, config->FWRevision)); + ret = AGSA_RC_VERSION_INCOMPATIBLE; + smTraceFuncExit(hpDBG_VERY_LOUD, 'n', "m4"); + return ret; + } + else + { + SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x mismatch with FW ver. 0x%08x warning!\n",STSDK_LL_SPC_VERSION , config->FWRevision)); + ret = AGSA_RC_VERSION_UNTESTED; + } + } + } + SA_DBG1(("mpiWaitForConfigTable: ILA version 0x%08X\n", ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_ILAT_ILAV_ILASMRN_ILAMRN_ILAMJN) )); + + + if(smIS_SPC12V(agRoot)) + { + if (config->InterfaceRev > 0x301 ) + { + SA_DBG1(("mpiWaitForConfigTable: MAIN_INACTIVE_ILA_REVSION 0x%08X\n", ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_INACTIVE_ILA_REVSION) )); + SA_DBG1(("mpiWaitForConfigTable: MAIN_SEEPROM_REVSION 0x%08X\n", ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_SEEPROM_REVSION) )); + } + } + + if(smIS_SPC12V(agRoot)) + { + if (config->InterfaceRev > 0x301 ) + { + SA_DBG1(("mpiWaitForConfigTable: MAIN_AWT_MIDRANGE 0x%08X\n", ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_AWT_MIDRANGE) )); + } + } + + + if(smIS_SFC(agRoot)) + { + /* always success for SFC*/ + ret = AGSA_RC_SUCCESS; + } + + if (agNULL != saRoot) + { + /* save the information */ + saRoot->ControllerInfo.signature = Signature; + saRoot->ControllerInfo.fwInterfaceRev = config->InterfaceRev; + + if(smIS_SPCV(agRoot)) + { + saRoot->ControllerInfo.hwRevision = (ossaHwRegReadConfig32(agRoot,8) & 0xFF); + SA_DBG1(("mpiWaitForConfigTable: hwRevision 0x%x\n",saRoot->ControllerInfo.hwRevision )); + } + else + { + saRoot->ControllerInfo.hwRevision = SPC_READ_DEV_REV; + } + + saRoot->ControllerInfo.fwRevision = config->FWRevision; + saRoot->ControllerInfo.ilaRevision = config->ilaRevision; + saRoot->ControllerInfo.maxPendingIO = config->MaxOutstandingIO; + saRoot->ControllerInfo.maxSgElements = config->MDevMaxSGL & 0xFFFF; + saRoot->ControllerInfo.maxDevices = (config->MDevMaxSGL & MAX_DEV_BITS) >> SHIFT16; + saRoot->ControllerInfo.queueSupport = config->ContrlCapFlag & Q_SUPPORT_BITS; + saRoot->ControllerInfo.phyCount = (bit8)((config->ContrlCapFlag & PHY_COUNT_BITS) >> SHIFT19); + saRoot->ControllerInfo.sasSpecsSupport = (config->ContrlCapFlag & SAS_SPEC_BITS) >> SHIFT25; + SA_DBG1(("mpiWaitForConfigTable: MaxOutstandingIO 0x%x swConfig->maxActiveIOs 0x%x\n", config->MaxOutstandingIO,saRoot->swConfig.maxActiveIOs )); + + if(smIS_SPCV(agRoot)) + { + ;/* SPCV - reserved field */ + } + else + { + saRoot->ControllerInfo.controllerSetting = (bit8)config->HDAModeFlags; + } + + saRoot->ControllerInfo.sdkInterfaceRev = STSDK_LL_INTERFACE_VERSION; + saRoot->ControllerInfo.sdkRevision = STSDK_LL_VERSION; + saRoot->mainConfigTable.regDumpPCIBAR = pcibar; + saRoot->mainConfigTable.FatalErrorDumpOffset0 = config->FatalErrorDumpOffset0; + saRoot->mainConfigTable.FatalErrorDumpLength0 = config->FatalErrorDumpLength0; + saRoot->mainConfigTable.FatalErrorDumpOffset1 = config->FatalErrorDumpOffset1; + saRoot->mainConfigTable.FatalErrorDumpLength1 = config->FatalErrorDumpLength1; + + if(smIS_SPCV(agRoot)) + { + ;/* SPCV - reserved field */ + } + else + { + saRoot->mainConfigTable.HDAModeFlags = config->HDAModeFlags; + } + + saRoot->mainConfigTable.analogSetupTblOffset = config->analogSetupTblOffset; + + if(smIS_SPCV(agRoot)) + { + saRoot->mainConfigTable.InterruptVecTblOffset = config->InterruptVecTblOffset; + saRoot->mainConfigTable.phyAttributeTblOffset = config->phyAttributeTblOffset; + saRoot->mainConfigTable.PortRecoveryTimerPortResetTimer = config->portRecoveryResetTimer; + } + + SA_DBG1(("mpiWaitForConfigTable: Signature = 0x%x\n", Signature)); + SA_DBG1(("mpiWaitForConfigTable: hwRevision = 0x%x\n", saRoot->ControllerInfo.hwRevision)); + SA_DBG1(("mpiWaitForConfigTable: FW Revision = 0x%x\n", config->FWRevision)); + SA_DBG1(("mpiWaitForConfigTable: Max Sgl = 0x%x\n", saRoot->ControllerInfo.maxSgElements)); + SA_DBG1(("mpiWaitForConfigTable: Max Device = 0x%x\n", saRoot->ControllerInfo.maxDevices)); + SA_DBG1(("mpiWaitForConfigTable: Queue Support = 0x%x\n", saRoot->ControllerInfo.queueSupport)); + SA_DBG1(("mpiWaitForConfigTable: Phy Count = 0x%x\n", saRoot->ControllerInfo.phyCount)); + SA_DBG1(("mpiWaitForConfigTable: sas Specs Support = 0x%x\n", saRoot->ControllerInfo.sasSpecsSupport)); + + } + + + if(ret != AGSA_RC_SUCCESS ) + { + SA_DBG1(("mpiWaitForConfigTable: return 0x%x not AGSA_RC_SUCCESS warning!\n", ret)); + } + + + smTraceFuncExit(hpDBG_VERY_LOUD, 'o', "m4"); + return ret; +} + +/*******************************************************************************/ +/** \fn mpiUnInitConfigTable(agsaRoot_t *agRoot, spc_configMainDescriptor_t *config) + * \brief UnInitialization Configuration Table + * \param agsaRoot Pointer to a data structure containing LL layer context handles + * + * Return: + * AGSA_RC_SUCCESS if Un-initialize the configuration table sucessful + * AGSA_RC_FAILURE if Un-initialize the configuration table failed + */ +/*******************************************************************************/ +GLOBAL bit32 mpiUnInitConfigTable(agsaRoot_t *agRoot) +{ + bit32 MSGUCfgTblBase; + bit32 CfgTblDWIdx, GSTOffset, GSTLenMPIS; + bit32 value, togglevalue; + bit32 max_wait_time; + bit32 max_wait_count; + bit8 pcibar; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"m7"); + SA_DBG1(("mpiUnInitConfigTable: agRoot %p\n",agRoot)); + SA_ASSERT(NULL != agRoot, "agRoot argument cannot be null"); + + togglevalue = 0; + + /* read scratch pad0 to get PCI BAR and offset of configuration table */ + MSGUCfgTblBase =siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); + + if(MSGUCfgTblBase == 0xFFFFFFFF) + { + SA_DBG1(("mpiUnInitConfigTable: MSGUCfgTblBase = 0x%x AGSA_RC_FAILURE\n",MSGUCfgTblBase)); + return AGSA_RC_FAILURE; + } + + /* get offset */ + CfgTblDWIdx = MSGUCfgTblBase & SCRATCH_PAD0_OFFSET_MASK; + /* get PCI BAR */ + MSGUCfgTblBase = (MSGUCfgTblBase & SCRATCH_PAD0_BAR_MASK) >> SHIFT26; + + /* convert the PCI BAR to logical bar number */ + pcibar = (bit8)mpiGetPCIBarIndex(agRoot, MSGUCfgTblBase); + + /* Write bit 1 to Inbound DoorBell Register */ + siHalRegWriteExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET); + + /* wait until Inbound DoorBell Clear Register toggled */ + max_wait_time = WAIT_SECONDS(gWait_2); /* 2 sec */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + value = MSGU_READ_IDR; + value &= SPC_MSGU_CFG_TABLE_RESET; + } while ((value != togglevalue) && (max_wait_count -= WAIT_INCREMENT)); + + if (!max_wait_count) + { + SA_DBG1(("mpiUnInitConfigTable: TIMEOUT:IBDB value/toggle = 0x%x 0x%x\n", value, togglevalue)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "m7"); + + if(smIS_SPC(agRoot) ) + { + return AGSA_RC_FAILURE; + } + + } + + /* check the MPI-State for termination in progress */ + /* wait until Inbound DoorBell Clear Register toggled */ + max_wait_time = WAIT_SECONDS(gWait_2); /* 2 sec */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); + GSTOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_GST_OFFSET); + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + + if(GSTOffset == 0xFFFFFFFF) + { + SA_DBG1(("mpiUnInitConfigTable:AGSA_RC_FAILURE GSTOffset = 0x%x\n",GSTOffset)); + return AGSA_RC_FAILURE; + } + + GSTLenMPIS = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + (bit32)(GSTOffset + GST_GSTLEN_MPIS_OFFSET)); + if (GST_MPI_STATE_UNINIT == (GSTLenMPIS & GST_MPI_STATE_MASK)) + { + break; + } + } while (max_wait_count -= WAIT_INCREMENT); + + if (!max_wait_count) + { + SA_DBG1(("mpiUnInitConfigTable: TIMEOUT, MPI State = 0x%x\n", GSTLenMPIS & GST_MPI_STATE_MASK)); +#if defined(SALLSDK_DEBUG) + + SA_DBG1(("mpiUnInitConfigTable: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_0))); + SA_DBG1(("mpiUnInitConfigTable: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1))); + SA_DBG1(("mpiUnInitConfigTable: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_2))); + SA_DBG1(("mpiUnInitConfigTable: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_3))); +#endif + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "m7"); + return AGSA_RC_FAILURE; + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "m7"); + return AGSA_RC_SUCCESS; +} + +/*******************************************************************************/ +/** \fn void mpiUpdateIBQueueCfgTable(agsaRoot_t *agRoot, spc_inboundQueueDescriptor_t *outQueueCfg, + * bit32 QueueTableOffset,bit8 pcibar) + * \brief Writing to the inbound queue of the Configuration Table + * \param agsaRoot Pointer to a data structure containing both application and LL layer context handles + * \param outQueueCfg Pointer to inbuond configuration area + * \param QueueTableOffset Queue configuration table offset + * \param pcibar PCI BAR + * + * Return: + * None + */ +/*******************************************************************************/ +GLOBAL void mpiUpdateIBQueueCfgTable(agsaRoot_t *agRoot, + spc_inboundQueueDescriptor_t *inQueueCfg, + bit32 QueueTableOffset, + bit8 pcibar) +{ + smTraceFuncEnter(hpDBG_VERY_LOUD,"m5"); + + smTrace(hpDBG_VERY_LOUD,"Ba",QueueTableOffset); + /* TP:Ba QueueTableOffset */ + smTrace(hpDBG_VERY_LOUD,"Bb",pcibar); + /* TP:Bb pcibar */ + + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + IB_PROPERITY_OFFSET), inQueueCfg->elementPriSizeCount); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + IB_BASE_ADDR_HI_OFFSET), inQueueCfg->upperBaseAddress); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + IB_BASE_ADDR_LO_OFFSET), inQueueCfg->lowerBaseAddress); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + IB_CI_BASE_ADDR_HI_OFFSET), inQueueCfg->ciUpperBaseAddress); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + IB_CI_BASE_ADDR_LO_OFFSET), inQueueCfg->ciLowerBaseAddress); + + + SA_DBG3(("mpiUpdateIBQueueCfgTable: Offset 0x%08x elementPriSizeCount 0x%x\n",(bit32)(QueueTableOffset + IB_PROPERITY_OFFSET), inQueueCfg->elementPriSizeCount)); + SA_DBG3(("mpiUpdateIBQueueCfgTable: Offset 0x%08x upperBaseAddress 0x%x\n",(bit32)(QueueTableOffset + IB_BASE_ADDR_HI_OFFSET), inQueueCfg->upperBaseAddress)); + SA_DBG3(("mpiUpdateIBQueueCfgTable: Offset 0x%08x lowerBaseAddress 0x%x\n",(bit32)(QueueTableOffset + IB_BASE_ADDR_LO_OFFSET), inQueueCfg->lowerBaseAddress)); + SA_DBG3(("mpiUpdateIBQueueCfgTable: Offset 0x%08x ciUpperBaseAddress 0x%x\n",(bit32)(QueueTableOffset + IB_CI_BASE_ADDR_HI_OFFSET), inQueueCfg->ciUpperBaseAddress)); + SA_DBG3(("mpiUpdateIBQueueCfgTable: Offset 0x%08x ciLowerBaseAddress 0x%x\n",(bit32)(QueueTableOffset + IB_CI_BASE_ADDR_LO_OFFSET), inQueueCfg->ciLowerBaseAddress)); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "m5"); +} + +/*******************************************************************************/ +/** \fn void mpiUpdateOBQueueCfgTable(agsaRoot_t *agRoot, spc_outboundQueueDescriptor_t *outQueueCfg, + * bit32 QueueTableOffset,bit8 pcibar) + * \brief Writing to the inbound queue of the Configuration Table + * \param agsaRoot Pointer to a data structure containing both application + * and LL layer context handles + * \param outQueueCfg Pointer to outbuond configuration area + * \param QueueTableOffset Queue configuration table offset + * \param pcibar PCI BAR + * + * Return: + * None + */ +/*******************************************************************************/ +GLOBAL void mpiUpdateOBQueueCfgTable(agsaRoot_t *agRoot, + spc_outboundQueueDescriptor_t *outQueueCfg, + bit32 QueueTableOffset, + bit8 pcibar) +{ + + smTraceFuncEnter(hpDBG_VERY_LOUD,"m8"); + + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + OB_PROPERITY_OFFSET), outQueueCfg->elementSizeCount); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + OB_BASE_ADDR_HI_OFFSET), outQueueCfg->upperBaseAddress); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + OB_BASE_ADDR_LO_OFFSET), outQueueCfg->lowerBaseAddress); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + OB_PI_BASE_ADDR_HI_OFFSET), outQueueCfg->piUpperBaseAddress); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + OB_PI_BASE_ADDR_LO_OFFSET), outQueueCfg->piLowerBaseAddress); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + OB_INTERRUPT_COALES_OFFSET), outQueueCfg->interruptVecCntDelay); + + SA_DBG3(("mpiUpdateOBQueueCfgTable: Offset 0x%08x elementSizeCount 0x%x\n",(bit32)(QueueTableOffset + OB_PROPERITY_OFFSET), outQueueCfg->elementSizeCount)); + SA_DBG3(("mpiUpdateOBQueueCfgTable: Offset 0x%08x upperBaseAddress 0x%x\n",(bit32)(QueueTableOffset + OB_BASE_ADDR_HI_OFFSET), outQueueCfg->upperBaseAddress)); + SA_DBG3(("mpiUpdateOBQueueCfgTable: Offset 0x%08x lowerBaseAddress 0x%x\n",(bit32)(QueueTableOffset + OB_BASE_ADDR_LO_OFFSET), outQueueCfg->lowerBaseAddress)); + SA_DBG3(("mpiUpdateOBQueueCfgTable: Offset 0x%08x piUpperBaseAddress 0x%x\n",(bit32)(QueueTableOffset + OB_PI_BASE_ADDR_HI_OFFSET), outQueueCfg->piUpperBaseAddress)); + SA_DBG3(("mpiUpdateOBQueueCfgTable: Offset 0x%08x piLowerBaseAddress 0x%x\n",(bit32)(QueueTableOffset + OB_PI_BASE_ADDR_LO_OFFSET), outQueueCfg->piLowerBaseAddress)); + SA_DBG3(("mpiUpdateOBQueueCfgTable: Offset 0x%08x interruptVecCntDelay 0x%x\n",(bit32)(QueueTableOffset + OB_INTERRUPT_COALES_OFFSET), outQueueCfg->interruptVecCntDelay)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "m8"); +} + + + +/*******************************************************************************/ +/** \fn void mpiUpdateOBQueueCfgTable(agsaRoot_t *agRoot, spc_outboundQueueDescriptor_t *outQueueCfg, + * bit32 QueueTableOffset,bit8 pcibar) + * \brief Writing to the inbound queue of the Configuration Table + * \param agsaRoot Pointer to a data structure containing both application + * and LL layer context handles + * \param outQueueCfg Pointer to outbuond configuration area + * \param QueueTableOffset Queue configuration table offset + * \param pcibar PCI BAR + * + * Return: + * None + */ +/*******************************************************************************/ +GLOBAL void mpiUpdateFatalErrorTable(agsaRoot_t *agRoot, + bit32 FerrTableOffset, + bit32 lowerBaseAddress, + bit32 upperBaseAddress, + bit32 length, + bit8 pcibar) +{ + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2U"); + + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(FerrTableOffset + MPI_FATAL_EDUMP_TABLE_LO_OFFSET), lowerBaseAddress); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(FerrTableOffset + MPI_FATAL_EDUMP_TABLE_HI_OFFSET), upperBaseAddress); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(FerrTableOffset + MPI_FATAL_EDUMP_TABLE_LENGTH), length); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(FerrTableOffset + MPI_FATAL_EDUMP_TABLE_HANDSHAKE), 0); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(FerrTableOffset + MPI_FATAL_EDUMP_TABLE_STATUS), 0); + + + SA_DBG3(("mpiUpdateFatalErrorTable: Offset 0x%08x MPI_FATAL_EDUMP_TABLE_LO_OFFSET 0x%x\n",FerrTableOffset + MPI_FATAL_EDUMP_TABLE_LO_OFFSET, lowerBaseAddress)); + SA_DBG3(("mpiUpdateFatalErrorTable: Offset 0x%08x MPI_FATAL_EDUMP_TABLE_HI_OFFSET 0x%x\n",FerrTableOffset + MPI_FATAL_EDUMP_TABLE_HI_OFFSET,upperBaseAddress )); + SA_DBG3(("mpiUpdateFatalErrorTable: Offset 0x%08x MPI_FATAL_EDUMP_TABLE_LENGTH 0x%x\n",FerrTableOffset + MPI_FATAL_EDUMP_TABLE_LENGTH, length)); + SA_DBG3(("mpiUpdateFatalErrorTable: Offset 0x%08x MPI_FATAL_EDUMP_TABLE_HANDSHAKE 0x%x\n",FerrTableOffset + MPI_FATAL_EDUMP_TABLE_HANDSHAKE,0 )); + SA_DBG3(("mpiUpdateFatalErrorTable: Offset 0x%08x MPI_FATAL_EDUMP_TABLE_STATUS 0x%x\n",FerrTableOffset + MPI_FATAL_EDUMP_TABLE_STATUS,0 )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2U"); +} + + +/*******************************************************************************/ +/** \fn bit32 mpiGetPCIBarIndex(agsaRoot_t *agRoot, pciBar) + * \brief Get PCI BAR Index from PCI BAR + * \param agsaRoot Pointer to a data structure containing both application and LL layer context handles + * \param pciBar - PCI BAR + * + * Return: + * PCI BAR Index + */ +/*******************************************************************************/ +GLOBAL bit32 mpiGetPCIBarIndex(agsaRoot_t *agRoot, bit32 pciBar) +{ + switch(pciBar) + { + case BAR0: + case BAR1: + pciBar = PCIBAR0; + break; + case BAR2: + case BAR3: + pciBar = PCIBAR1; + break; + case BAR4: + pciBar = PCIBAR2; + break; + case BAR5: + pciBar = PCIBAR3; + break; + default: + pciBar = PCIBAR0; + break; + } + + return pciBar; +} + +/*******************************************************************************/ +/** \fn void mpiReadGSTTable(agsaRoot_t *agRoot, spc_GSTableDescriptor_t *mpiGSTable) + * \brief Reading the General Status Table + * + * \param agsaRoot Handles for this instance of SAS/SATA LLL + * \param mpiGSTable Pointer of General Status Table + * + * Return: + * None + */ +/*******************************************************************************/ +GLOBAL void mpiReadGSTable(agsaRoot_t *agRoot, + spc_GSTableDescriptor_t *mpiGSTable) +{ + bit32 CFGTableOffset, TableOffset; + bit32 GSTableOffset; + bit8 i, pcibar; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"m9"); + + /* get offset of the configuration table */ + TableOffset = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); + + if(0xFFFFFFFF == TableOffset) + { + SA_ASSERT(0xFFFFFFFF == TableOffset, "Chip PCI dead"); + + SA_DBG1(("mpiReadGSTable: Chip PCI dead TableOffset 0x%x\n", TableOffset)); + return; + } + +// SA_DBG1(("mpiReadGSTable: TableOffset 0x%x\n", TableOffset)); + CFGTableOffset = TableOffset & SCRATCH_PAD0_OFFSET_MASK; + + /* get PCI BAR */ + TableOffset = (TableOffset & SCRATCH_PAD0_BAR_MASK) >> SHIFT26; + /* convert the PCI BAR to logical bar number */ + pcibar = (bit8)mpiGetPCIBarIndex(agRoot, TableOffset); + + /* read GST Table Offset from the configuration table */ + GSTableOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CFGTableOffset + MAIN_GST_OFFSET); +// SA_DBG1(("mpiReadGSTable: GSTableOffset 0x%x\n",GSTableOffset )); + + GSTableOffset = CFGTableOffset + GSTableOffset; + + mpiGSTable->GSTLenMPIS = ossaHwRegReadExt(agRoot, pcibar, (bit32)(GSTableOffset + GST_GSTLEN_MPIS_OFFSET)); + mpiGSTable->IQFreezeState0 = ossaHwRegReadExt(agRoot, pcibar, (bit32)(GSTableOffset + GST_IQ_FREEZE_STATE0_OFFSET)); + mpiGSTable->IQFreezeState1 = ossaHwRegReadExt(agRoot, pcibar, (bit32)(GSTableOffset + GST_IQ_FREEZE_STATE1_OFFSET)); + mpiGSTable->MsguTcnt = ossaHwRegReadExt(agRoot, pcibar, (bit32)(GSTableOffset + GST_MSGUTCNT_OFFSET)); + mpiGSTable->IopTcnt = ossaHwRegReadExt(agRoot, pcibar, (bit32)(GSTableOffset + GST_IOPTCNT_OFFSET)); + mpiGSTable->Iop1Tcnt = ossaHwRegReadExt(agRoot, pcibar, (bit32)(GSTableOffset + GST_IOP1TCNT_OFFSET)); + + SA_DBG4(("mpiReadGSTable: GSTLenMPIS 0x%x\n", mpiGSTable->GSTLenMPIS)); + SA_DBG4(("mpiReadGSTable: GSTLen 0x%x\n", (mpiGSTable->GSTLenMPIS & 0xfff8) >> SHIFT3)); + SA_DBG4(("mpiReadGSTable: IQFreezeState0 0x%x\n", mpiGSTable->IQFreezeState0)); + SA_DBG4(("mpiReadGSTable: IQFreezeState1 0x%x\n", mpiGSTable->IQFreezeState1)); + SA_DBG4(("mpiReadGSTable: MsguTcnt 0x%x\n", mpiGSTable->MsguTcnt)); + SA_DBG4(("mpiReadGSTable: IopTcnt 0x%x\n", mpiGSTable->IopTcnt)); + SA_DBG4(("mpiReadGSTable: Iop1Tcnt 0x%x\n", mpiGSTable->Iop1Tcnt)); + + + if(smIS_SPCV(agRoot)) + { + /***** read Phy State from SAS Phy Attribute Table */ + TableOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CFGTableOffset + MAIN_PHY_ATTRIBUTE_OFFSET); + TableOffset &= 0x00FFFFFF; + TableOffset = TableOffset + CFGTableOffset; + for (i = 0; i < 8; i++) + { + mpiGSTable->PhyState[i] = ossaHwRegReadExt(agRoot, pcibar, (bit32)(TableOffset + i * sizeof(phyAttrb_t))); + SA_DBG4(("mpiReadGSTable: PhyState[0x%x] 0x%x\n", i, mpiGSTable->PhyState[i])); + } + } + else + { + for (i = 0; i < 8; i++) + { + mpiGSTable->PhyState[i] = ossaHwRegReadExt(agRoot, pcibar, (bit32)(GSTableOffset + GST_PHYSTATE_OFFSET + i * 4)); + SA_DBG4(("mpiReadGSTable: PhyState[0x%x] 0x%x\n", i, mpiGSTable->PhyState[i])); + } + } + + mpiGSTable->GPIOpins = ossaHwRegReadExt(agRoot, pcibar, (bit32)(GSTableOffset + GST_GPIO_PINS_OFFSET)); + SA_DBG4(("mpiReadGSTable: GPIOpins 0x%x\n", mpiGSTable->GPIOpins)); + + for (i = 0; i < 8; i++) + { + mpiGSTable->recoverErrInfo[i] = ossaHwRegReadExt(agRoot, pcibar, (bit32)(GSTableOffset + GST_RERRINFO_OFFSET)); + SA_DBG4(("mpiReadGSTable: recoverErrInfo[0x%x] 0x%x\n", i, mpiGSTable->recoverErrInfo[i])); + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "m9"); + +} + +/*******************************************************************************/ +/** \fn void siInitResources(agsaRoot_t *agRoot) + * Initialization of LL resources + * + * \param agsaRoot Handles for this instance of SAS/SATA LLL + * \param memoryAllocated Point to the data structure that holds the different + * chunks of memory that are required + * + * Return: + * None + */ +/*******************************************************************************/ +GLOBAL void siInitResources(agsaRoot_t *agRoot, + agsaMemoryRequirement_t *memoryAllocated, + agsaHwConfig_t *hwConfig, + agsaSwConfig_t *swConfig, + bit32 usecsPerTick) +{ + agsaLLRoot_t *saRoot; + agsaDeviceDesc_t *pDeviceDesc; + agsaIORequestDesc_t *pRequestDesc; + agsaTimerDesc_t *pTimerDesc; + agsaPort_t *pPort; + agsaPortMap_t *pPortMap; + agsaDeviceMap_t *pDeviceMap; + agsaIOMap_t *pIOMap; + bit32 maxNumIODevices; + bit32 i, j; + mpiICQueue_t *circularIQ; + mpiOCQueue_t *circularOQ; + + if (agNULL == agRoot) + { + return; + } + + /* Get the saRoot memory address */ + saRoot = (agsaLLRoot_t *) (memoryAllocated->agMemory[LLROOT_MEM_INDEX].virtPtr); + agRoot->sdkData = (void *) saRoot; + + /* Setup Device link */ + /* Save the information of allocated device Link memory */ + saRoot->deviceLinkMem = memoryAllocated->agMemory[DEVICELINK_MEM_INDEX]; + si_memset(saRoot->deviceLinkMem.virtPtr, 0, saRoot->deviceLinkMem.totalLength); + SA_DBG2(("siInitResources: [%d] saRoot->deviceLinkMem VirtPtr=%p PhysicalLo=%x Count=%x Total=%x type %x\n" , + DEVICELINK_MEM_INDEX, + saRoot->deviceLinkMem.virtPtr, + saRoot->deviceLinkMem.phyAddrLower, + saRoot->deviceLinkMem.numElements, + saRoot->deviceLinkMem.totalLength, + saRoot->deviceLinkMem.type)); + + maxNumIODevices = swConfig->numDevHandles; + SA_DBG2(("siInitResources: maxNumIODevices=%d, swConfig->numDevHandles=%d \n", + maxNumIODevices, + swConfig->numDevHandles)); + + /* Setup free IO Devices link list */ + saLlistInitialize(&(saRoot->freeDevicesList)); + for ( i = 0; i < (bit32) maxNumIODevices; i ++ ) + { + /* get the pointer to the device descriptor */ + pDeviceDesc = (agsaDeviceDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->deviceLinkMem), i); + /* Initialize device descriptor */ + saLlinkInitialize(&(pDeviceDesc->linkNode)); + + pDeviceDesc->initiatorDevHandle.osData = agNULL; + pDeviceDesc->initiatorDevHandle.sdkData = agNULL; + pDeviceDesc->targetDevHandle.osData = agNULL; + pDeviceDesc->targetDevHandle.sdkData = agNULL; + pDeviceDesc->deviceType = SAS_SATA_UNKNOWN_DEVICE; + pDeviceDesc->pPort = agNULL; + pDeviceDesc->DeviceMapIndex = 0; + + saLlistInitialize(&(pDeviceDesc->pendingIORequests)); + + /* Add the device descriptor to the free IO device link list */ + saLlistAdd(&(saRoot->freeDevicesList), &(pDeviceDesc->linkNode)); + } + + /* Setup IO Request link */ + /* Save the information of allocated IO Request Link memory */ + saRoot->IORequestMem = memoryAllocated->agMemory[IOREQLINK_MEM_INDEX]; + si_memset(saRoot->IORequestMem.virtPtr, 0, saRoot->IORequestMem.totalLength); + + SA_DBG2(("siInitResources: [%d] saRoot->IORequestMem VirtPtr=%p PhysicalLo=%x Count=%x Total=%x type %x\n", + IOREQLINK_MEM_INDEX, + saRoot->IORequestMem.virtPtr, + saRoot->IORequestMem.phyAddrLower, + saRoot->IORequestMem.numElements, + saRoot->IORequestMem.totalLength, + saRoot->IORequestMem.type)); + + /* Setup free IO Request link list */ + saLlistIOInitialize(&(saRoot->freeIORequests)); + saLlistIOInitialize(&(saRoot->freeReservedRequests)); + for ( i = 0; i < swConfig->maxActiveIOs; i ++ ) + { + /* get the pointer to the request descriptor */ + pRequestDesc = (agsaIORequestDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->IORequestMem), i); + /* Initialize request descriptor */ + saLlinkIOInitialize(&(pRequestDesc->linkNode)); + + pRequestDesc->valid = agFALSE; + pRequestDesc->requestType = AGSA_REQ_TYPE_UNKNOWN; + pRequestDesc->pIORequestContext = agNULL; + pRequestDesc->HTag = i; + pRequestDesc->pDevice = agNULL; + pRequestDesc->pPort = agNULL; + + /* Add the request descriptor to the free IO Request link list */ + /* Add the request descriptor to the free Reserved Request link list */ + /* SMP request must get service so reserve one request when first SMP completes */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequestDesc->linkNode)); + } + else + { + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequestDesc->linkNode)); + } + } + + + /* Setup timer link */ + /* Save the information of allocated timer Link memory */ + saRoot->timerLinkMem = memoryAllocated->agMemory[TIMERLINK_MEM_INDEX]; + si_memset(saRoot->timerLinkMem.virtPtr, 0, saRoot->timerLinkMem.totalLength); + SA_DBG2(("siInitResources: [%d] saRoot->timerLinkMem VirtPtr=%p PhysicalLo=%x Count=%x Total=%x type %x\n", + TIMERLINK_MEM_INDEX, + saRoot->timerLinkMem.virtPtr, + saRoot->timerLinkMem.phyAddrLower, + saRoot->timerLinkMem.numElements, + saRoot->timerLinkMem.totalLength, + saRoot->timerLinkMem.type)); + + /* Setup free timer link list */ + saLlistInitialize(&(saRoot->freeTimers)); + for ( i = 0; i < NUM_TIMERS; i ++ ) + { + /* get the pointer to the timer descriptor */ + pTimerDesc = (agsaTimerDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->timerLinkMem), i); + /* Initialize timer descriptor */ + saLlinkInitialize(&(pTimerDesc->linkNode)); + + pTimerDesc->valid = agFALSE; + pTimerDesc->timeoutTick = 0; + pTimerDesc->pfnTimeout = agNULL; + pTimerDesc->Event = 0; + pTimerDesc->pParm = agNULL; + + /* Add the timer descriptor to the free timer link list */ + saLlistAdd(&(saRoot->freeTimers), &(pTimerDesc->linkNode)); + } + /* Setup valid timer link list */ + saLlistInitialize(&(saRoot->validTimers)); + + /* Setup Phys */ + /* Setup PhyCount */ + saRoot->phyCount = (bit8) hwConfig->phyCount; + /* Init Phy data structure */ + for ( i = 0; i < saRoot->phyCount; i ++ ) + { + saRoot->phys[i].pPort = agNULL; + saRoot->phys[i].phyId = (bit8) i; + + /* setup phy status is PHY_STOPPED */ + PHY_STATUS_SET(&(saRoot->phys[i]), PHY_STOPPED); + } + + /* Setup Ports */ + /* Setup PortCount */ + saRoot->portCount = saRoot->phyCount; + /* Setup free port link list */ + saLlistInitialize(&(saRoot->freePorts)); + for ( i = 0; i < saRoot->portCount; i ++ ) + { + /* get the pointer to the port */ + pPort = &(saRoot->ports[i]); + /* Initialize port */ + saLlinkInitialize(&(pPort->linkNode)); + + pPort->portContext.osData = agNULL; + pPort->portContext.sdkData = pPort; + pPort->portId = 0; + pPort->portIdx = (bit8) i; + pPort->status = PORT_NORMAL; + + for ( j = 0; j < saRoot->phyCount; j ++ ) + { + pPort->phyMap[j] = agFALSE; + } + + saLlistInitialize(&(pPort->listSASATADevices)); + + /* Add the port to the free port link list */ + saLlistAdd(&(saRoot->freePorts), &(pPort->linkNode)); + } + /* Setup valid port link list */ + saLlistInitialize(&(saRoot->validPorts)); + + /* Init sysIntsActive */ + saRoot->sysIntsActive = agFALSE; + + /* setup timer tick granunarity */ + saRoot->usecsPerTick = usecsPerTick; + + /* initialize LL timer tick */ + saRoot->timeTick = 0; + + /* initialize device (de)registration callback fns */ + saRoot->DeviceRegistrationCB = agNULL; + saRoot->DeviceDeregistrationCB = agNULL; + + /* Initialize the PortMap for port context */ + for ( i = 0; i < saRoot->portCount; i ++ ) + { + pPortMap = &(saRoot->PortMap[i]); + + pPortMap->PortContext = agNULL; + pPortMap->PortID = PORT_MARK_OFF; + pPortMap->PortStatus = PORT_NORMAL; + saRoot->autoDeregDeviceflag[i] = 0; + } + + /* Initialize the DeviceMap for device handle */ + for ( i = 0; i < MAX_IO_DEVICE_ENTRIES; i ++ ) + { + pDeviceMap = &(saRoot->DeviceMap[i]); + + pDeviceMap->DeviceHandle = agNULL; + pDeviceMap->DeviceIdFromFW = i; + } + + /* Initialize the IOMap for IOrequest */ + for ( i = 0; i < MAX_ACTIVE_IO_REQUESTS; i ++ ) + { + pIOMap = &(saRoot->IOMap[i]); + + pIOMap->IORequest = agNULL; + pIOMap->Tag = MARK_OFF; + } + + /* clean the inbound queues */ + for (i = 0; i < saRoot->QueueConfig.numInboundQueues; i ++) + { + if(0 != saRoot->inboundQueue[i].numElements) + { + circularIQ = &saRoot->inboundQueue[i]; + si_memset(circularIQ->memoryRegion.virtPtr, 0, circularIQ->memoryRegion.totalLength); + si_memset(saRoot->inboundQueue[i].ciPointer, 0, sizeof(bit32)); + } + } + /* clean the outbound queues */ + for (i = 0; i < saRoot->QueueConfig.numOutboundQueues; i ++) + { + if(0 != saRoot->outboundQueue[i].numElements) + { + circularOQ = &saRoot->outboundQueue[i]; + si_memset(circularOQ->memoryRegion.virtPtr, 0, circularOQ->memoryRegion.totalLength); + si_memset(saRoot->outboundQueue[i].piPointer, 0, sizeof(bit32)); + circularOQ->producerIdx = 0; + circularOQ->consumerIdx = 0; + SA_DBG3(("siInitResource: Q %d Clean PI 0x%03x CI 0x%03x\n", i,circularOQ->producerIdx, circularOQ->consumerIdx)); + } + } + + return; +} + +/*******************************************************************************/ +/** \fn void mpiReadCALTable(agsaRoot_t *agRoot, + * spc_SPASTable_t *mpiCALTable, bit32 index) + * \brief Reading the Phy Analog Setup Register Table + * \param agsaRoot Handles for this instance of SAS/SATA LLL + * \param mpiCALTable Pointer of Phy Calibration Table + * + * Return: + * None + */ +/*******************************************************************************/ +GLOBAL void mpiReadCALTable(agsaRoot_t *agRoot, + spc_SPASTable_t *mpiCALTable, + bit32 index) +{ + bit32 CFGTableOffset, TableOffset; + bit32 CALTableOffset; + bit8 pcibar; + + /* get offset of the configuration table */ + TableOffset = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); + + CFGTableOffset = TableOffset & SCRATCH_PAD0_OFFSET_MASK; + + /* get PCI BAR */ + TableOffset = (TableOffset & SCRATCH_PAD0_BAR_MASK) >> SHIFT26; + /* convert the PCI BAR to logical bar number */ + pcibar = (bit8)mpiGetPCIBarIndex(agRoot, TableOffset); + + /* read Calibration Table Offset from the configuration table */ + CALTableOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CFGTableOffset + MAIN_ANALOG_SETUP_OFFSET); + if(smIS_SPCV(agRoot)) + { + CALTableOffset &= 0x00FFFFFF; + } + CALTableOffset = CFGTableOffset + CALTableOffset + (index * ANALOG_SETUP_ENTRY_SIZE * 4); + + mpiCALTable->spaReg0 = ossaHwRegReadExt(agRoot, pcibar, (bit32)(CALTableOffset + TX_PORT_CFG1_OFFSET)); + mpiCALTable->spaReg1 = ossaHwRegReadExt(agRoot, pcibar, (bit32)(CALTableOffset + TX_PORT_CFG2_OFFSET)); + mpiCALTable->spaReg2 = ossaHwRegReadExt(agRoot, pcibar, (bit32)(CALTableOffset + TX_PORT_CFG3_OFFSET)); + mpiCALTable->spaReg3 = ossaHwRegReadExt(agRoot, pcibar, (bit32)(CALTableOffset + TX_CFG_OFFSET)); + mpiCALTable->spaReg4 = ossaHwRegReadExt(agRoot, pcibar, (bit32)(CALTableOffset + RV_PORT_CFG1_OFFSET)); + mpiCALTable->spaReg5 = ossaHwRegReadExt(agRoot, pcibar, (bit32)(CALTableOffset + RV_PORT_CFG2_OFFSET)); + mpiCALTable->spaReg6 = ossaHwRegReadExt(agRoot, pcibar, (bit32)(CALTableOffset + RV_CFG1_OFFSET)); + mpiCALTable->spaReg7 = ossaHwRegReadExt(agRoot, pcibar, (bit32)(CALTableOffset + RV_CFG2_OFFSET)); + + SA_DBG3(("mpiReadCALTable: spaReg0 0x%x\n", mpiCALTable->spaReg0)); + SA_DBG3(("mpiReadCALTable: spaReg1 0x%x\n", mpiCALTable->spaReg1)); + SA_DBG3(("mpiReadCALTable: spaReg2 0x%x\n", mpiCALTable->spaReg2)); + SA_DBG3(("mpiReadCALTable: spaReg3 0x%x\n", mpiCALTable->spaReg3)); + SA_DBG3(("mpiReadCALTable: spaReg4 0x%x\n", mpiCALTable->spaReg4)); + SA_DBG3(("mpiReadCALTable: spaReg5 0x%x\n", mpiCALTable->spaReg5)); + SA_DBG3(("mpiReadCALTable: spaReg6 0x%x\n", mpiCALTable->spaReg6)); + SA_DBG3(("mpiReadCALTable: spaReg7 0x%x\n", mpiCALTable->spaReg7)); +} + +/*******************************************************************************/ +/** \fn void mpiWriteCALTable(agsaRoot_t *agRoot, + * spc_SPASTable_t *mpiCALTable, index) + * \brief Writing the Phy Analog Setup Register Table + * \param agsaRoot Handles for this instance of SAS/SATA LLL + * \param mpiCALTable Pointer of Phy Calibration Table + * + * Return: + * None + */ +/*******************************************************************************/ +GLOBAL void mpiWriteCALTable(agsaRoot_t *agRoot, + spc_SPASTable_t *mpiCALTable, + bit32 index) +{ + bit32 CFGTableOffset, TableOffset; + bit32 CALTableOffset; + bit8 pcibar; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"m6"); + + /* get offset of the configuration table */ + TableOffset = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); + + CFGTableOffset = TableOffset & SCRATCH_PAD0_OFFSET_MASK; + + /* get PCI BAR */ + TableOffset = (TableOffset & SCRATCH_PAD0_BAR_MASK) >> SHIFT26; + /* convert the PCI BAR to logical bar number */ + pcibar = (bit8)mpiGetPCIBarIndex(agRoot, TableOffset); + + /* read Calibration Table Offset from the configuration table */ + CALTableOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CFGTableOffset + MAIN_ANALOG_SETUP_OFFSET); + if(smIS_SPCV(agRoot)) + { + CALTableOffset &= 0x00FFFFFF; + } + CALTableOffset = CFGTableOffset + CALTableOffset + (index * ANALOG_SETUP_ENTRY_SIZE * 4); + + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(CALTableOffset + TX_PORT_CFG1_OFFSET), mpiCALTable->spaReg0); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(CALTableOffset + TX_PORT_CFG2_OFFSET), mpiCALTable->spaReg1); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(CALTableOffset + TX_PORT_CFG3_OFFSET), mpiCALTable->spaReg2); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(CALTableOffset + TX_CFG_OFFSET), mpiCALTable->spaReg3); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(CALTableOffset + RV_PORT_CFG1_OFFSET), mpiCALTable->spaReg4); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(CALTableOffset + RV_PORT_CFG2_OFFSET), mpiCALTable->spaReg5); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(CALTableOffset + RV_CFG1_OFFSET), mpiCALTable->spaReg6); + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(CALTableOffset + RV_CFG2_OFFSET), mpiCALTable->spaReg7); + + SA_DBG4(("mpiWriteCALTable: Offset 0x%08x spaReg0 0x%x 0x%x 0x%x 0x%x\n",(bit32)(CALTableOffset + TX_PORT_CFG1_OFFSET), mpiCALTable->spaReg0, mpiCALTable->spaReg1, mpiCALTable->spaReg2, mpiCALTable->spaReg3)); + SA_DBG4(("mpiWriteCALTable: Offset 0x%08x spaReg4 0x%x 0x%x 0x%x 0x%x\n",(bit32)(CALTableOffset + RV_PORT_CFG1_OFFSET), mpiCALTable->spaReg4, mpiCALTable->spaReg5, mpiCALTable->spaReg6, mpiCALTable->spaReg7)); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "m6"); +} + +/*******************************************************************************/ +/** \fn void mpiWriteCALAll(agsaRoot_t *agRoot, + * agsaPhyAnalogSetupTable_t *mpiCALTable) + * \brief Writing the Phy Analog Setup Register Table + * \param agsaRoot Handles for this instance of SAS/SATA LLL + * \param mpiCALTable Pointer of Phy Calibration Table + * + * Return: + * None + */ +/*******************************************************************************/ +GLOBAL void mpiWriteCALAll(agsaRoot_t *agRoot, + agsaPhyAnalogSetupTable_t *mpiCALTable) +{ + bit8 i; + smTraceFuncEnter(hpDBG_VERY_LOUD,"mz"); + + if(smIS_SPCV(agRoot)) + { + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "mz"); + return; + } + + for (i = 0; i < MAX_INDEX; i++) + { + mpiWriteCALTable(agRoot, (spc_SPASTable_t *)&mpiCALTable->phyAnalogSetupRegisters[i], i); + } + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "mz"); +} + +GLOBAL void mpiWrAnalogSetupTable(agsaRoot_t *agRoot, + mpiConfig_t *config + ) +{ + + bit32 AnalogTableBase,CFGTableOffset, value,phy; + bit32 AnalogtableSize; + bit8 pcibar; + value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); + pcibar = (bit8)mpiGetPCIBarIndex(agRoot, value); + + CFGTableOffset = value & SCRATCH_PAD0_OFFSET_MASK; + AnalogtableSize = AnalogTableBase = ossaHwRegReadExt(agRoot,pcibar , (bit32)CFGTableOffset + MAIN_ANALOG_SETUP_OFFSET); + AnalogtableSize &= 0xFF000000; + AnalogtableSize >>= SHIFT24; + AnalogTableBase &= 0x00FFFFFF; + + AnalogTableBase = CFGTableOffset + AnalogTableBase; + +// config->phyAnalogConfig.phyAnalogSetupRegisters[0].spaRegister0 = 0; + SA_DBG1(("mpiWrAnalogSetupTable:Analogtable Base Offset %08X pcibar %d\n",AnalogTableBase, pcibar )); + + SA_DBG1(("mpiWrAnalogSetupTable:%d %d\n",(int)sizeof(agsaPhyAnalogSetupRegisters_t), AnalogtableSize)); + + for(phy = 0; phy < 10; phy++) /* upto 10 phys See PM*/ + { + ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 0 ),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister0 ); + ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 4 ),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister1 ); + ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 8 ),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister2 ); + ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 12),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister3 ); + ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 16),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister4 ); + ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 20),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister5 ); + ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 24),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister6 ); + ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 28),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister7 ); + ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 32),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister8 ); + ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 36),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister9 ); + + SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister0 0x%x 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) + 0,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister0 ,ossaHwRegReadExt(agRoot, pcibar,AnalogTableBase + ( AnalogtableSize * phy)+ 0 ))); + SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister1 0x%x 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) + 4,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister1 ,ossaHwRegReadExt(agRoot, pcibar,AnalogTableBase + ( AnalogtableSize * phy)+ 4 ))); + SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister2 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) + 8,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister2 )); + SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister3 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) +12,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister3 )); + SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister4 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) +16,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister4 )); + SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister5 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) +20,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister5 )); + SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister6 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) +24,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister6 )); + SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister7 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) +28,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister7 )); + SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister8 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) +32,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister8 )); + SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister9 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) +36,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister9 )); + } + +} + + +GLOBAL void mpiWrIntVecTable(agsaRoot_t *agRoot, + mpiConfig_t* config + ) +{ + bit32 CFGTableOffset, value; + bit32 INTVTableOffset; + bit32 ValuetoWrite; + bit8 pcibar, i,obq; + + /* get offset of the configuration table */ + value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); + + CFGTableOffset = value & SCRATCH_PAD0_OFFSET_MASK; + + /* get PCI BAR */ + value = (value & SCRATCH_PAD0_BAR_MASK) >> SHIFT26; + /* convert the PCI BAR to logical bar number */ + pcibar = (bit8)mpiGetPCIBarIndex(agRoot, value); + + /* read Interrupt Table Offset from the main configuration table */ + INTVTableOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CFGTableOffset + MAIN_INT_VEC_TABLE_OFFSET); + INTVTableOffset &= 0x00FFFFFF; + INTVTableOffset = CFGTableOffset + INTVTableOffset; + SA_DBG1(("mpiWrIntVecTable: Base Offset %08X\n",(bit32)(INTVTableOffset + INT_VT_Coal_CNT_TO ) )); + + for (i = 0; i < MAX_NUM_VECTOR; i ++) + { + bit32 found=0; + for (obq = 0; obq < MAX_NUM_VECTOR; obq++) + { /* find OBQ for vector i */ + if( config->outboundQueues[obq].interruptVector == i ) + { + found=1; + break; + } + } + + if(!found ) + { + continue; + } + + ValuetoWrite = (( config->outboundQueues[obq].interruptDelay << SHIFT15) | config->outboundQueues[obq].interruptThreshold ); + + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(INTVTableOffset + INT_VT_Coal_CNT_TO + i * sizeof(InterruptVT_t)), ValuetoWrite ); + + SA_DBG3(("mpiWrIntVecTable: Q %d interruptDelay 0x%X interruptThreshold 0x%X \n",i, + config->outboundQueues[i].interruptDelay, config->outboundQueues[i].interruptThreshold )); + + SA_DBG3(("mpiWrIntVecTable: %d INT_VT_Coal_CNT_TO Bar %d Offset %3X Writing 0x%08x\n",i, + pcibar, + (bit32)(INTVTableOffset + INT_VT_Coal_CNT_TO + i * sizeof(InterruptVT_t)), + ValuetoWrite)); + + } + + for (i = 0; i < MAX_NUM_VECTOR; i++) + { + /* read interrupt colescing control and timer */ + value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(INTVTableOffset + INT_VT_Coal_CNT_TO + i * sizeof(InterruptVT_t))); + SA_DBG4(("mpiWrIntVecTable: Offset 0x%08x Interrupt Colescing iccict[%02d] 0x%x\n", (bit32)(INTVTableOffset + INT_VT_Coal_CNT_TO + i * sizeof(InterruptVT_t)), i, value)); + } +} + +GLOBAL void mpiWrPhyAttrbTable(agsaRoot_t *agRoot, sasPhyAttribute_t *phyAttrib) +{ + bit32 CFGTableOffset, value; + bit32 PHYTableOffset; + bit8 pcibar, i; + + /* get offset of the configuration table */ + value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); + + CFGTableOffset = value & SCRATCH_PAD0_OFFSET_MASK; + + /* get PCI BAR */ + value = (value & SCRATCH_PAD0_BAR_MASK) >> SHIFT26; + /* convert the PCI BAR to logical bar number */ + pcibar = (bit8)mpiGetPCIBarIndex(agRoot, value); + + /* read Phy Attribute Table Offset from the configuration table */ + PHYTableOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CFGTableOffset + MAIN_PHY_ATTRIBUTE_OFFSET); + + PHYTableOffset &=0x00FFFFFF; + + PHYTableOffset = CFGTableOffset + PHYTableOffset + PHY_EVENT_OQ; + + SA_DBG1(("mpiWrPhyAttrbTable: PHYTableOffset 0x%08x\n", PHYTableOffset)); + + /* write OQ event per phy */ + for (i = 0; i < MAX_VALID_PHYS; i ++) + { + ossaHwRegWriteExt(agRoot, pcibar, (bit32)(PHYTableOffset + i * sizeof(phyAttrb_t)), phyAttrib->phyAttribute[i].phyEventOQ); + + SA_DBG3(("mpiWrPhyAttrbTable:%d Offset 0x%08x phyAttribute 0x%x\n",i,(bit32)(PHYTableOffset + i * sizeof(phyAttrb_t)), phyAttrib->phyAttribute[i].phyEventOQ )); + + + } + + for (i = 0; i < MAX_VALID_PHYS; i ++) + { + value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(PHYTableOffset + i * sizeof(phyAttrb_t))); + SA_DBG1(("mpiWrPhyAttrbTable: OQ Event per phy[%x] 0x%x\n", i, value)); + } +} + + +#ifdef TEST /******************************************************************/ +/*******************************************************************************/ +/** \fn mpiFreezeInboundQueue(agsaRoot_t *agRoot) + * \brief Freeze the inbound queue + * + * \param agRoot Handles for this instance of SAS/SATA hardware + * \param bitMapQueueNum0 bit map for inbound queue number 0 - 31 to freeze + * \param bitMapQueueNum1 bit map for inbound queue number 32 - 63 to freeze + * + * Return: + * AGSA_RC_SUCCESS if Un-initialize the configuration table sucessful + * AGSA_RC_FAILURE if Un-initialize the configuration table failed + */ +/*******************************************************************************/ +GLOBAL bit32 mpiFreezeInboundQueue(agsaRoot_t *agRoot, bit32 bitMapQueueNum0, bit32 bitMapQueueNum1) +{ + bit32 value, togglevalue; + bit32 max_wait_time; + bit32 max_wait_count; + + SA_DBG2(("Entering function:mpiFreezeInboundQueue\n")); + SA_ASSERT(NULL != agRoot, "agRoot argument cannot be null"); + + togglevalue = 0; + + if (bitMapQueueNum0) + { + /* update the inbound queue number to HOST_SCRATCH_PAD1 register for queue 0 to 31 */ + SA_DBG1(("mpiFreezeInboundQueue: SCRATCH_PAD0 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0))); + SA_DBG1(("mpiFreezeInboundQueue: SCRATCH_PAD3 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3,MSGU_SCRATCH_PAD_3))); + + value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_1); + value |= bitMapQueueNum0; + siHalRegWriteExt(agRoot, GEN_MSGU_HOST_SCRATCH_PAD_1, MSGU_HOST_SCRATCH_PAD_1, value); + } + + if (bitMapQueueNum1) + { + /* update the inbound queue number to HOST_SCRATCH_PAD2 register for queue 32 to 63 */ + value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2,MSGU_SCRATCH_PAD_2); + value |= bitMapQueueNum1; + siHalRegWriteExt(agRoot, GEN_MSGU_HOST_SCRATCH_PAD_2, MSGU_HOST_SCRATCH_PAD_2, value); + } + + /* Write bit 2 to Inbound DoorBell Register */ + siHalRegWriteExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET, IBDB_IBQ_FREEZE); + + /* wait until Inbound DoorBell Clear Register toggled */ + max_wait_time = WAIT_SECONDS(gWait_2); /* 2 sec */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + /* Read Inbound DoorBell Register - for RevB */ +// value = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_IBDB_SET); + value = MSGU_READ_IDR; + value &= IBDB_IBQ_FREEZE; + } while ((value != togglevalue) && (max_wait_count -= WAIT_INCREMENT)); + + if (!max_wait_count) + { + SA_DBG1(("mpiFreezeInboundQueue: IBDB value/toggle = 0x%x 0x%x\n", value, togglevalue)); + return AGSA_RC_FAILURE; + } + + return AGSA_RC_SUCCESS; +} + +/******************************************************************************/ +/** \fn mpiUnFreezeInboundQueue(agsaRoot_t *agRoot) + * \brief Freeze the inbound queue + * + * \param agRoot Handles for this instance of SAS/SATA hardware + * \param bitMapQueueNum0 bit map for inbound queue number 0 - 31 to freeze + * \param bitMapQueueNum1 bit map for inbound queue number 32 - 63 to freeze + * + * Return: + * AGSA_RC_SUCCESS if Un-initialize the configuration table sucessful + * AGSA_RC_FAILURE if Un-initialize the configuration table failed + */ +/******************************************************************************/ +GLOBAL bit32 mpiUnFreezeInboundQueue(agsaRoot_t *agRoot, bit32 bitMapQueueNum0, bit32 bitMapQueueNum1) +{ + bit32 value, togglevalue; + bit32 max_wait_time; + bit32 max_wait_count; + + SA_DBG2(("Entering function:mpiUnFreezeInboundQueue\n")); + SA_ASSERT(NULL != agRoot, "agRoot argument cannot be null"); + + togglevalue = 0; + + if (bitMapQueueNum0) + { + /* update the inbound queue number to HOST_SCRATCH_PAD1 register - for queue 0 to 31 */ + value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1,MSGU_SCRATCH_PAD_1); + value |= bitMapQueueNum0; + siHalRegWriteExt(agRoot, GEN_MSGU_HOST_SCRATCH_PAD_1, MSGU_HOST_SCRATCH_PAD_1, value); + } + + if (bitMapQueueNum1) + { + /* update the inbound queue number to HOST_SCRATCH_PAD2 register - for queue 32 to 63 */ + value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2,MSGU_SCRATCH_PAD_2); + value |= bitMapQueueNum1; + siHalRegWriteExt(agRoot, GEN_MSGU_HOST_SCRATCH_PAD_2, MSGU_HOST_SCRATCH_PAD_2, value); + } + + /* Write bit 2 to Inbound DoorBell Register */ + siHalRegWriteExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET, IBDB_IBQ_UNFREEZE); + + /* wait until Inbound DoorBell Clear Register toggled */ + max_wait_time = WAIT_SECONDS(gWait_2); /* 2 sec */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + /* Read Inbound DoorBell Register - for RevB */ + value = MSGU_READ_IDR; + value &= IBDB_IBQ_UNFREEZE; + } while ((value != togglevalue) && (max_wait_count -= WAIT_INCREMENT)); + + if (!max_wait_count) + { + SA_DBG1(("mpiUnFreezeInboundQueue: IBDB value/toggle = 0x%x 0x%x\n", value, togglevalue)); + return AGSA_RC_FAILURE; + } + + return AGSA_RC_SUCCESS; +} + +#endif /* TEST ****************************************************************/ + +GLOBAL bit32 si_check_V_HDA(agsaRoot_t *agRoot) +{ + bit32 ret = AGSA_RC_SUCCESS; + bit32 hda_status = 0; + + hda_status = (ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28)); + + SA_DBG1(("si_check_V_HDA: hda_status 0x%08X\n",hda_status )); + + if((hda_status & SPC_V_HDAR_RSPCODE_MASK) == SPC_V_HDAR_IDLE) + { + /* HDA mode */ + SA_DBG1(("si_check_V_HDA: HDA mode, value = 0x%x\n", hda_status)); + ret = AGSA_RC_HDA_NO_FW_RUNNING; + } + + + return(ret); +} +GLOBAL bit32 si_check_V_Ready(agsaRoot_t *agRoot) +{ + bit32 ret = AGSA_RC_SUCCESS; + bit32 SCRATCH_PAD1; + bit32 max_wait_time; + bit32 max_wait_count; +/* ILA */ + max_wait_time = (200 * 1000); /* wait 200 milliseconds */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); + } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_ILA_MASK) != SCRATCH_PAD1_V_ILA_MASK) && (max_wait_count -= WAIT_INCREMENT)); + + if (!max_wait_count) + { + SA_DBG1(("si_check_V_Ready: SCRATCH_PAD1_V_ILA_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_ILA_MASK, SCRATCH_PAD1)); + return( AGSA_RC_FAILURE); + } + /* RAAE */ + max_wait_time = (200 * 1000); /* wait 200 milliseconds */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); + } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_RAAE_MASK) != SCRATCH_PAD1_V_RAAE_MASK) && (max_wait_count -= WAIT_INCREMENT)); + + if (!max_wait_count) + { + SA_DBG1(("si_check_V_Ready: SCRATCH_PAD1_V_RAAE_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_RAAE_MASK, SCRATCH_PAD1)); + return( AGSA_RC_FAILURE); + + } + /* IOP0 */ + max_wait_time = (200 * 1000); /* wait 200 milliseconds */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); + } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_IOP0_MASK) != SCRATCH_PAD1_V_IOP0_MASK) && (max_wait_count -= WAIT_INCREMENT)); + + if (!max_wait_count) + { + SA_DBG1(("si_check_V_Ready: SCRATCH_PAD1_V_IOP0_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_IOP0_MASK ,SCRATCH_PAD1)); + return( AGSA_RC_FAILURE); + + } + + /* IOP1 */ + max_wait_time = (200 * 1000); /* wait 200 milliseconds */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); + } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_IOP1_MASK) != SCRATCH_PAD1_V_IOP1_MASK) && (max_wait_count -= WAIT_INCREMENT)); + + if (!max_wait_count) + { + SA_DBG1(("si_check_V_Ready: SCRATCH_PAD1_V_IOP1_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_IOP1_MASK, SCRATCH_PAD1)); + // return( AGSA_RC_FAILURE); + } + + return(ret); +} + +GLOBAL bit32 siScratchDump(agsaRoot_t *agRoot) +{ + bit32 SCRATCH_PAD1; + bit32 ret =0; +#ifdef SALLSDK_DEBUG + bit32 SCRATCH_PAD2; + bit32 SCRATCH_PAD3; + bit32 SCRATCH_PAD0; + + SCRATCH_PAD0 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_0); + SCRATCH_PAD2 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_2); + SCRATCH_PAD3 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_3); +#endif /* SALLSDK_DEBUG */ + SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); + SA_DBG1(("siScratchDump: SCRATCH_PAD 0 0x%08x 1 0x%08x 2 0x%08x 3 0x%08x\n",SCRATCH_PAD0,SCRATCH_PAD1,SCRATCH_PAD2,SCRATCH_PAD3 )); + + if((SCRATCH_PAD1 & SCRATCH_PAD1_V_RESERVED) == SCRATCH_PAD1_V_RESERVED ) + { + SA_DBG1(("siScratchDump: SCRATCH_PAD1 SCRATCH_PAD1_V_RESERVED 0x%08x\n", SCRATCH_PAD1_V_RESERVED)); + } + else + { + if((SCRATCH_PAD1 & SCRATCH_PAD1_V_RAAE_MASK) == SCRATCH_PAD1_V_RAAE_MASK ) + { + SA_DBG1(("siScratchDump: SCRATCH_PAD1 valid 0x%08x\n",SCRATCH_PAD0 )); + SA_DBG1(("siScratchDump: RAAE ready 0x%08x\n",SCRATCH_PAD1 & SCRATCH_PAD1_V_RAAE_MASK)); + } + if((SCRATCH_PAD1 & SCRATCH_PAD1_V_ILA_MASK) == SCRATCH_PAD1_V_ILA_MASK) + { + SA_DBG1(("siScratchDump: ILA ready 0x%08x\n", SCRATCH_PAD1 & SCRATCH_PAD1_V_ILA_MASK)); + } + + if(SCRATCH_PAD1 & SCRATCH_PAD1_V_BOOTSTATE_MASK) + { + SA_DBG1(("siScratchDump: BOOTSTATE not success 0x%08x\n",SCRATCH_PAD1 & SCRATCH_PAD1_V_BOOTSTATE_MASK)); + } + + if((SCRATCH_PAD1 & SCRATCH_PAD1_V_IOP0_MASK) == SCRATCH_PAD1_V_IOP0_MASK) + { + SA_DBG1(("siScratchDump: IOP0 ready 0x%08x\n",SCRATCH_PAD1 & SCRATCH_PAD1_V_IOP0_MASK)); + } + if((SCRATCH_PAD1 & SCRATCH_PAD1_V_IOP1_MASK) == SCRATCH_PAD1_V_IOP1_MASK) + { + SA_DBG1(("siScratchDump: IOP1 ready 0x%08x\n",SCRATCH_PAD1 & SCRATCH_PAD1_V_IOP1_MASK )); + } + if((SCRATCH_PAD1 & SCRATCH_PAD1_V_READY) == SCRATCH_PAD1_V_READY) + { + SA_DBG1(("siScratchDump: SCRATCH_PAD1_V_READY 0x%08x\n",SCRATCH_PAD1 & SCRATCH_PAD1_V_READY )); + } + if((SCRATCH_PAD1 & SCRATCH_PAD1_V_BOOTSTATE_MASK) == SCRATCH_PAD1_V_BOOTSTATE_MASK) + { + SA_DBG1(("siScratchDump: SCRATCH_PAD1_V_BOOTSTATE_MASK 0x%08x\n",SCRATCH_PAD1 & SCRATCH_PAD1_V_BOOTSTATE_MASK )); + } + } + return(ret); + +} + + +void si_macro_check(agsaRoot_t *agRoot) +{ + + SA_DBG1(("si_macro_check:smIS_SPC %d\n",smIS_SPC(agRoot) )); + SA_DBG1(("si_macro_check:smIS_HIL %d\n",smIS_HIL(agRoot) )); + SA_DBG1(("si_macro_check:smIS_SFC %d\n",smIS_SFC(agRoot) )); + + SA_DBG1(("si_macro_check:smIS_spc8001 %d\n",smIS_spc8001(agRoot) )); + SA_DBG1(("si_macro_check:smIS_spc8081 %d\n",smIS_spc8081(agRoot) )); + + SA_DBG1(("si_macro_check:smIS_SPCV8008 %d\n",smIS_SPCV8008(agRoot) )); + SA_DBG1(("si_macro_check:smIS_SPCV8009 %d\n",smIS_SPCV8009(agRoot) )); + SA_DBG1(("si_macro_check:smIS_SPCV8018 %d\n",smIS_SPCV8018(agRoot) )); + SA_DBG1(("si_macro_check:smIS_SPCV8019 %d\n",smIS_SPCV8019(agRoot) )); + SA_DBG1(("si_macro_check:smIS_ADAP8088 %d\n",smIS_ADAP8088(agRoot) )); + SA_DBG1(("si_macro_check:smIS_ADAP8089 %d\n",smIS_ADAP8089(agRoot) )); + SA_DBG1(("si_macro_check:smIS_SPCV8070 %d\n",smIS_SPCV8070(agRoot) )); + SA_DBG1(("si_macro_check:smIS_SPCV8071 %d\n",smIS_SPCV8071(agRoot) )); + SA_DBG1(("si_macro_check:smIS_SPCV8072 %d\n",smIS_SPCV8072(agRoot) )); + SA_DBG1(("si_macro_check:smIS_SPCV8073 %d\n",smIS_SPCV8073(agRoot) )); + SA_DBG1(("si_macro_check:smIS_SPCV8074 %d\n",smIS_SPCV8074(agRoot) )); + SA_DBG1(("si_macro_check:smIS_SPCV8075 %d\n",smIS_SPCV8075(agRoot) )); + SA_DBG1(("si_macro_check:smIS_SPCV8076 %d\n",smIS_SPCV8076(agRoot) )); + SA_DBG1(("si_macro_check:smIS_SPCV8077 %d\n",smIS_SPCV8077(agRoot) )); + SA_DBG1(("si_macro_check:smIS_SPCV9015 %d\n",smIS_SPCV9015(agRoot) )); + SA_DBG1(("si_macro_check:smIS_SPCV9060 %d\n",smIS_SPCV9060(agRoot) )); + SA_DBG1(("si_macro_check:smIS_SPCV %d\n",smIS_SPCV(agRoot) )); + + SA_DBG1(("si_macro_check:smIS64bInt %d\n", smIS64bInt(agRoot) )); + +} + diff --git a/sys/dev/pms/RefTisa/sallsdk/spc/saint.c b/sys/dev/pms/RefTisa/sallsdk/spc/saint.c new file mode 100644 index 000000000000..86c198338f12 --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/spc/saint.c @@ -0,0 +1,3872 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +/*******************************************************************************/ +/*! \file saint.c + * \brief The file implements the functions to handle/enable/disable interrupt + * + */ +/*******************************************************************************/ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#define SA_CLEAR_ODCR_IN_INTERRUPT + +//#define SA_TEST_FW_SPURIOUS_INT + +#ifdef SA_TEST_FW_SPURIOUS_INT +bit32 gOurIntCount = 0; +bit32 gSpuriousIntCount = 0; +bit32 gSpuriousInt[64]= +{ +0,0,0,0,0,0,0,0, +0,0,0,0,0,0,0,0, +0,0,0,0,0,0,0,0, +0,0,0,0,0,0,0,0, +0,0,0,0,0,0,0,0, +0,0,0,0,0,0,0,0, +0,0,0,0,0,0,0,0, +0,0,0,0,0,0,0,0 +}; +bit32 gSpuriousInt1[64]= +{ +0,0,0,0,0,0,0,0, +0,0,0,0,0,0,0,0, +0,0,0,0,0,0,0,0, +0,0,0,0,0,0,0,0, +0,0,0,0,0,0,0,0, +0,0,0,0,0,0,0,0, +0,0,0,0,0,0,0,0, +0,0,0,0,0,0,0,0 +}; +#endif /* SA_TEST_FW_SPURIOUS_INT */ + +#ifdef SA_ENABLE_TRACE_FUNCTIONS +#ifdef siTraceFileID +#undef siTraceFileID +#endif /* siTraceFileID */ +#define siTraceFileID 'G' +#endif /* SA_ENABLE_TRACE_FUNCTIONS */ + +LOCAL FORCEINLINE bit32 siProcessOBMsg( + agsaRoot_t *agRoot, + bit32 count, + bit32 queueNum + ); + +LOCAL bit32 siFatalInterruptHandler( + agsaRoot_t *agRoot, + bit32 interruptVectorIndex + ) +{ + agsaLLRoot_t *saRoot = agNULL; + agsaFatalErrorInfo_t fatal_error; + bit32 value; + bit32 ret = AGSA_RC_FAILURE; + bit32 Sendfatal = agTRUE; + + SA_ASSERT((agNULL != agRoot), ""); + if (agRoot == agNULL) + { + SA_DBG1(("siFatalInterruptHandler: agRoot == agNULL\n")); + return AGSA_RC_FAILURE; + } + saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + SA_ASSERT((agNULL != saRoot), ""); + if (saRoot == agNULL) + { + SA_DBG1(("siFatalInterruptHandler: saRoot == agNULL\n")); + return AGSA_RC_FAILURE; + } + + value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1); + if (saRoot->ResetFailed) + { + SA_DBG1(("siFatalInterruptHandler: ResetFailed\n")); + ossaDisableInterrupts(agRoot, interruptVectorIndex); + return AGSA_RC_FAILURE; + } + + if(SCRATCH_PAD1_V_ERROR_STATE( value ) ) + { + si_memset(&fatal_error, 0, sizeof(agsaFatalErrorInfo_t)); + /* read detail fatal errors */ + value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0, MSGU_SCRATCH_PAD_0); + fatal_error.errorInfo0 = value; + SA_DBG1(("siFatalInterruptHandler: ScratchPad0 AAP error 0x%x code 0x%x\n",SCRATCH_PAD1_V_ERROR_STATE( value ), value)); + + value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1); + fatal_error.errorInfo1 = value; + /* AAP error state */ + SA_DBG1(("siFatalInterruptHandler: AAP error state and error code 0x%x\n", value)); + value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2, MSGU_SCRATCH_PAD_2); + fatal_error.errorInfo2 = value; + SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2 0x%08x\n", fatal_error.errorInfo2 )); + +#if defined(SALLSDK_DEBUG) + if(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_ILA_ERR) + { + SA_DBG1(("siFatalInterruptHandler:SCRATCH_PAD1_V_ERROR_STATE SCRATCH_PAD2_FW_ILA_ERR 0x%08x\n", SCRATCH_PAD2_FW_ILA_ERR)); + } + if(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_FLM_ERR) + { + SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_FW_FLM_ERR 0x%08x\n", SCRATCH_PAD2_FW_FLM_ERR)); + } + if(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_FW_ASRT_ERR) + { + SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_FW_FW_ASRT_ERR 0x%08x\n", SCRATCH_PAD2_FW_FW_ASRT_ERR)); + } + if(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_WDG_ERR) + { + SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_FW_HW_WDG_ERR 0x%08x\n", SCRATCH_PAD2_FW_HW_WDG_ERR)); + } + if(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_GEN_EXCEPTION_ERR) + { + SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_FW_GEN_EXCEPTION_ERR 0x%08x\n", SCRATCH_PAD2_FW_GEN_EXCEPTION_ERR)); + } + if(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_UNDTMN_ERR) + { + SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_FW_UNDTMN_ERR 0x%08x\n",SCRATCH_PAD2_FW_UNDTMN_ERR )); + } + if(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_FATAL_ERR) + { + SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_FW_HW_FATAL_ERR 0x%08x\n", SCRATCH_PAD2_FW_HW_FATAL_ERR)); + } + if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_PCS_ERR ) + { + SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_PCS_ERR 0x%08x\n", value)); + } + if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_GSM_ERR ) + { + SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_GSM_ERR 0x%08x\n", value)); + } + if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP0_ERR ) + { + SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP0_ERR 0x%08x\n", value)); + } + if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) ==SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP1_ERR ) + { + SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP1_ERR 0x%08x\n", value)); + } + if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP2_ERR ) + { + SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP2_ERR 0x%08x\n", value)); + } + if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_ERAAE_ERR ) + { + SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_ERAAE_ERR 0x%08x\n", value)); + } + if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_SDS_ERR ) + { + SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_SDS_ERR 0x%08x\n", value)); + } + if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_CORE_ERR ) + { + SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_CORE_ERR 0x%08x\n", value)); + } + if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_AL_ERR ) + { + SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_AL_ERR 0x%08x\n", value)); + } + if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_MSGU_ERR ) + { + SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_MSGU_ERR 0x%08x\n", value)); + } + if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_SPBC_ERR ) + { + SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_SPBC_ERR 0x%08x\n", value)); + } + if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_BDMA_ERR ) + { + SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_BDMA_ERR 0x%08x\n", value)); + } + if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSL2B_ERR) + { + SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSL2B_ERR 0x%08x\n", value)); + } + if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSDC_ERR ) + { + SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSDC_ERR 0x%08x\n", value)); + } + if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_UNDETERMINED_ERROR_OCCURRED ) + { + SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_UNDETERMINED_ERROR_OCCURRED 0x%08x\n", value)); + } +#endif /* SALLSDK_DEBUG */ + + if( fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_NON_FATAL_ERR && + !(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_ILA_ERR) && + !(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_FLM_ERR) && + !(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_FW_ASRT_ERR) && + !(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_WDG_ERR) && + !(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_GEN_EXCEPTION_ERR) && + !(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_UNDTMN_ERR) && + !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_PCS_ERR) && + !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_GSM_ERR) && + !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP0_ERR) && + !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP2_ERR) && + !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_ERAAE_ERR) && + !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_SDS_ERR) && + !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_CORE_ERR) && + !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_AL_ERR) && + !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_MSGU_ERR) && + !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_SPBC_ERR) && + !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_BDMA_ERR) && + !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSL2B_ERR) && + !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSDC_ERR) && + !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_UNDETERMINED_ERROR_OCCURRED) && + !(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_FATAL_ERR) ) + { + SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_FW_HW_NON_FATAL_ERR 0x%08x\n", value)); + Sendfatal = agFALSE; + } + + value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3, MSGU_SCRATCH_PAD_3); + SA_DBG1(("siFatalInterruptHandler: ScratchPad3 IOP error code 0x%08x\n", value)); + fatal_error.errorInfo3 = value; + + if (agNULL != saRoot) + { + fatal_error.regDumpBusBaseNum0 = saRoot->mainConfigTable.regDumpPCIBAR; + fatal_error.regDumpOffset0 = saRoot->mainConfigTable.FatalErrorDumpOffset0; + fatal_error.regDumpLen0 = saRoot->mainConfigTable.FatalErrorDumpLength0; + fatal_error.regDumpBusBaseNum1 = saRoot->mainConfigTable.regDumpPCIBAR; + fatal_error.regDumpOffset1 = saRoot->mainConfigTable.FatalErrorDumpOffset1; + fatal_error.regDumpLen1 = saRoot->mainConfigTable.FatalErrorDumpLength1; + } + else + { + fatal_error.regDumpBusBaseNum0 = 0; + fatal_error.regDumpOffset0 = 0; + fatal_error.regDumpLen0 = 0; + fatal_error.regDumpBusBaseNum1 = 0; + fatal_error.regDumpOffset1 = 0; + fatal_error.regDumpLen1 = 0; + } + /* Call Back with error */ + SA_DBG1(("siFatalInterruptHandler: Sendfatal %x HostR0 0x%x\n",Sendfatal ,ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_Rsvd_0_Register ) )); + SA_DBG1(("siFatalInterruptHandler: ScratchPad2 0x%x ScratchPad3 0x%x\n", + ossaHwRegReadExt(agRoot, PCIBAR0,V_Host_Scratchpad_2_Register), + ossaHwRegReadExt(agRoot, PCIBAR0,V_Host_Scratchpad_3_Register) )); + + ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_MALFUNCTION, Sendfatal, (void *)&fatal_error, agNULL); + ret = AGSA_RC_SUCCESS; + } + else + { + bit32 host_reg0; + host_reg0 = ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_Rsvd_0_Register ); + if( host_reg0 == 0x2) + { + Sendfatal = agFALSE; + + SA_DBG1(("siFatalInterruptHandler: Non fatal ScratchPad1 0x%x HostR0 0x%x\n", value,host_reg0)); + SA_DBG1(("siFatalInterruptHandler: ScratchPad0 0x%x ScratchPad1 0x%x\n", + ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register), + ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_1_Register) )); + SA_DBG1(("siFatalInterruptHandler: ScratchPad2 0x%x ScratchPad3 0x%x\n", + ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_2_Register), + ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_3_Register) )); + + ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_MALFUNCTION, Sendfatal, (void *)&fatal_error, agNULL); + ret = AGSA_RC_SUCCESS; + } + else if( host_reg0 == HDA_AES_DIF_FUNC) + { + SA_DBG1(("siFatalInterruptHandler: HDA_AES_DIF_FUNC 0x%x\n", + ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_Rsvd_0_Register))); + Sendfatal = agFALSE; + ret = AGSA_RC_SUCCESS; + } + else + { + SA_DBG1(("siFatalInterruptHandler: No error detected ScratchPad1 0x%x HostR0 0x%x\n", value,host_reg0)); + SA_DBG1(("siFatalInterruptHandler: ScratchPad0 0x%x ScratchPad1 0x%x\n", + ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register), + ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_1_Register) )); + SA_DBG1(("siFatalInterruptHandler: ScratchPad2 0x%x ScratchPad3 0x%x\n", + ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_2_Register), + ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_3_Register) )); + + SA_DBG1(("siFatalInterruptHandler: Doorbell_Set %08X U %08X\n", + ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_Register), + ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_RegisterU))); + SA_DBG1(("siFatalInterruptHandler: Doorbell_Mask %08X U %08X\n", + ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register ), + ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_RegisterU ))); + + ret = AGSA_RC_FAILURE; + } + } + return ret; + +} + +GLOBAL bit32 saFatalInterruptHandler( + agsaRoot_t *agRoot, + bit32 interruptVectorIndex + ) +{ + agsaLLRoot_t *saRoot = agNULL; + bit32 ret = AGSA_RC_FAILURE; + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + SA_ASSERT((agNULL != saRoot), ""); + + if (saRoot->ResetFailed) + { + SA_DBG1(("saFatalInterruptHandler: ResetFailed\n")); + ossaDisableInterrupts(agRoot, interruptVectorIndex); + return AGSA_RC_FAILURE; + } + if (saRoot->swConfig.fatalErrorInterruptEnable != 1) + { + SA_DBG1(("saFatalInterruptHandler: fatalErrorInterrtupt is NOT enabled\n")); + ossaDisableInterrupts(agRoot, interruptVectorIndex); + return AGSA_RC_FAILURE; + } + + if (saRoot->swConfig.fatalErrorInterruptVector != interruptVectorIndex) + { + SA_DBG1(("saFatalInterruptHandler: interruptVectorIndex does not match 0x%x 0x%x\n", + saRoot->swConfig.fatalErrorInterruptVector, interruptVectorIndex)); + SA_DBG1(("saFatalInterruptHandler: ScratchPad0 0x%x ScratchPad1 0x%x\n", + ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register), + ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_1_Register) )); + SA_DBG1(("saFatalInterruptHandler: ScratchPad2 0x%x ScratchPad3 0x%x\n", + ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_2_Register), + ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_3_Register) )); + ossaDisableInterrupts(agRoot, interruptVectorIndex); + return AGSA_RC_FAILURE; + } + + ret = siFatalInterruptHandler(agRoot,interruptVectorIndex); + + + ossaDisableInterrupts(agRoot, interruptVectorIndex); + + return ret; +} +/******************************************************************************/ +/*! \brief Function to process the interrupts + * + * The saInterruptHandler() function is called after an interrupts has + * been received + * This function disables interrupts + * + * \param agRoot OS Layer-specific and LL Layer-specific context handles for this + * instance of SAS/SATA hardware + * \param interruptVectorIndex message that caused MSI message + * + * \return TRUE if we caused interrupt + * + */ +/*******************************************************************************/ +FORCEINLINE bit32 +saInterruptHandler( + agsaRoot_t *agRoot, + bit32 interruptVectorIndex + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + bit32 ToBeProcessedCount = 0; + bit32 our_int = 0; +#ifdef SA_TEST_FW_SPURIOUS_INT + bit8 i; +#endif/* SA_TEST_FW_SPURIOUS_INT */ + + if( agNULL == saRoot ) + { + /* Can be called before initialize is completed in a shared + interrupt environment like windows 2003 + */ + return(ToBeProcessedCount); + } + + if( (our_int = saRoot->OurInterrupt(agRoot,interruptVectorIndex)) == FALSE ) + { +#ifdef SA_TEST_FW_SPURIOUS_INT + gSpuriousIntCount++; + smTrace(hpDBG_REGISTERS,"S1",gSpuriousIntCount); + /* TP:S1 gSpuriousIntCount */ +#endif /* SA_TEST_FW_SPURIOUS_INT */ + return(ToBeProcessedCount); + } + + smTraceFuncEnter(hpDBG_TICK_INT, "5q"); + + smTrace(hpDBG_TICK_INT,"VI",interruptVectorIndex); + /* TP:Vi interrupt VectorIndex */ + + if ( agFALSE == saRoot->sysIntsActive ) + { + // SA_ASSERT(0, "saInterruptHandler sysIntsActive not set"); + +#ifdef SA_PRINTOUT_IN_WINDBG +#ifndef DBG + DbgPrint("saInterruptHandler: sysIntsActive not set Doorbell_Mask_Set %08X U %08X\n", + ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register), + ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_RegisterU) ); +#endif /* DBG */ +#endif /* SA_PRINTOUT_IN_WINDBG */ + + + SA_DBG1(("saInterruptHandler: Doorbell_Mask_Set %08X U %08X\n", + ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register), + ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_RegisterU))); + ossaDisableInterrupts(agRoot, interruptVectorIndex); + return(ToBeProcessedCount); + + } + + /* Allow replacement of disable interrupt */ + ossaDisableInterrupts(agRoot, interruptVectorIndex); + + +#ifdef SA_TEST_FW_SPURIOUS_INT + + /* count for my interrupt */ + gOurIntCount++; + + smTrace(hpDBG_REGISTERS,"S4",gOurIntCount); + /* TP:S4 gOurIntCount */ +#endif /* SA_TEST_FW_SPURIOUS_INT */ + + smTraceFuncExit(hpDBG_TICK_INT, 'a', "5q"); + return(TRUE); + +} + +/******************************************************************************/ +/*! \brief Function to disable MSIX interrupts + * + * siDisableMSIXInterrupts disables interrupts + * called thru macro ossaDisableInterrupts + * \param agRoot OS Layer-specific and LL Layer-specific context handles for this + * instance of SAS/SATA hardware + * \param interruptVectorIndex - vector index for message + * + */ +/*******************************************************************************/ +GLOBAL void siDisableMSIXInterrupts( + agsaRoot_t *agRoot, + bit32 interruptVectorIndex + ) +{ + bit32 msi_index; +#ifndef SA_CLEAR_ODCR_IN_INTERRUPT + bit32 value; +#endif /* SA_CLEAR_ODCR_IN_INTERRUPT */ + msi_index = interruptVectorIndex * MSIX_TABLE_ELEMENT_SIZE; + msi_index += MSIX_TABLE_BASE; + ossaHwRegWrite(agRoot,msi_index , MSIX_INTERRUPT_DISABLE); + ossaHwRegRead(agRoot, msi_index); /* Dummy read */ +#ifndef SA_CLEAR_ODCR_IN_INTERRUPT + value = (1 << interruptVectorIndex); + ossaHwRegWrite(agRoot, MSGU_ODCR, value); +#endif /* SA_CLEAR_ODCR_IN_INTERRUPT */ +} + +/******************************************************************************/ +/*! \brief Function to disable MSIX V interrupts + * + * siDisableMSIXInterrupts disables interrupts + * called thru macro ossaDisableInterrupts + * \param agRoot OS Layer-specific and LL Layer-specific context handles for this + * instance of SAS/SATA hardware + * \param interruptVectorIndex - vector index for message + * + */ +/*******************************************************************************/ +void siDisableMSIX_V_Interrupts( + agsaRoot_t *agRoot, + bit32 interruptVectorIndex + ) +{ + bit64 mask; + agsabit32bit64 u64; + mask =( (bit64)1 << interruptVectorIndex); + u64.B64 = mask; + if(smIS64bInt(agRoot)) + { + SA_DBG4(("siDisableMSIX_V_Interrupts: VI %d U 0x%08X L 0x%08X\n",interruptVectorIndex,u64.S32[1],u64.S32[0])); + ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Set_RegisterU,u64.S32[1]); + } + ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Set_Register, u64.S32[0]); + +} +/******************************************************************************/ +/*! \brief Function to disable MSI interrupts + * + * siDisableMSIInterrupts disables interrupts + * called thru macro ossaDisableInterrupts + * \param agRoot OS Layer-specific and LL Layer-specific context handles for this + * instance of SAS/SATA hardware + * \param interruptVectorIndex - vector index for message + * + */ +/*******************************************************************************/ +GLOBAL void siDisableMSIInterrupts( + agsaRoot_t *agRoot, + bit32 interruptVectorIndex + ) +{ + bit32 ODMRValue; + bit32 mask; + mask = 1 << interruptVectorIndex; + + /*Must be protected for interuption */ + ODMRValue = ossaHwRegRead(agRoot, MSGU_ODMR); + ODMRValue |= mask; + + ossaHwRegWrite(agRoot, MSGU_ODMR, ODMRValue); + ossaHwRegWrite(agRoot, MSGU_ODCR, mask); +} + +/******************************************************************************/ +/*! \brief Function to disable MSI V interrupts + * + * siDisableMSIInterrupts disables interrupts + * called thru macro ossaDisableInterrupts + * \param agRoot OS Layer-specific and LL Layer-specific context handles for this + * instance of SAS/SATA hardware + * \param interruptVectorIndex - vector index for message + * + */ +/*******************************************************************************/ +GLOBAL void siDisableMSI_V_Interrupts( + agsaRoot_t *agRoot, + bit32 interruptVectorIndex + ) +{ + SA_ASSERT(0, "Should not be called"); + SA_DBG4(("siDisableMSI_V_Interrupts:\n")); +} + +/******************************************************************************/ +/*! \brief Function to process Legacy interrupts + * + * siDisableLegacyInterrupts disables interrupts + * called thru macro ossaDisableInterrupts + * + * \param agRoot OS Layer-specific and LL Layer-specific context handles for this + * instance of SAS/SATA hardware + * \param interruptVectorIndex not used in legacy case + * + */ +/*******************************************************************************/ +GLOBAL void siDisableLegacyInterrupts( + agsaRoot_t *agRoot, + bit32 interruptVectorIndex + ) +{ + ossaHwRegWrite(agRoot, MSGU_ODMR, ODMR_MASK_ALL); +#ifndef SA_CLEAR_ODCR_IN_INTERRUPT + ossaHwRegWrite(agRoot, MSGU_ODCR, ODCR_CLEAR_ALL); +#endif /* SA_CLEAR_ODCR_IN_INTERRUPT */ +} + +/******************************************************************************/ +/*! \brief Function to process Legacy V interrupts + * + * siDisableLegacyInterrupts disables interrupts + * called thru macro ossaDisableInterrupts + * + * \param agRoot OS Layer-specific and LL Layer-specific context handles for this + * instance of SAS/SATA hardware + * \param interruptVectorIndex not used in legacy case + * + */ +/*******************************************************************************/ +GLOBAL void siDisableLegacy_V_Interrupts( + agsaRoot_t *agRoot, + bit32 interruptVectorIndex + ) +{ + + bit64 mask; + agsabit32bit64 u64; + mask =( (bit64)1 << interruptVectorIndex); + u64.B64 = mask; + + SA_DBG4(("siDisableLegacy_V_Interrupts:IN MSGU_READ_ODR %08X\n",siHalRegReadExt(agRoot, GEN_MSGU_ODR, V_Outbound_Doorbell_Set_Register))); + SA_DBG4(("siDisableLegacy_V_Interrupts:IN MSGU_READ_ODMR %08X\n",siHalRegReadExt(agRoot, GEN_MSGU_ODMR, V_Outbound_Doorbell_Mask_Set_Register ))); + if(smIS64bInt(agRoot)) + { + SA_DBG4(("siDisableLegacy_V_Interrupts: VI %d U 0x%08X L 0x%08X\n",interruptVectorIndex,u64.S32[1],u64.S32[0])); + ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Set_Register,u64.S32[1] ); + } + ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Set_RegisterU,u64.S32[0]); + +} +/******************************************************************************/ +/*! \brief Function to process MSIX interrupts + * + * siOurMSIXInterrupt checks if we generated interrupt + * called thru function pointer saRoot->OurInterrupt + * + * \param agRoot OS Layer-specific and LL Layer-specific context handles for this + * instance of SAS/SATA hardware + * \return always true + */ +/*******************************************************************************/ +GLOBAL bit32 siOurMSIXInterrupt( + agsaRoot_t *agRoot, + bit32 interruptVectorIndex + ) +{ + return(TRUE); +} + +/******************************************************************************/ +/*! \brief Function to process MSIX V interrupts + * + * siOurMSIXInterrupt checks if we generated interrupt + * called thru function pointer saRoot->OurInterrupt + * + * \param agRoot OS Layer-specific and LL Layer-specific context handles for this + * instance of SAS/SATA hardware + * \return always true + */ +/*******************************************************************************/ +GLOBAL bit32 siOurMSIX_V_Interrupt( + agsaRoot_t *agRoot, + bit32 interruptVectorIndex + ) +{ + return(TRUE); +} +/******************************************************************************/ +/*! \brief Function to process MSI interrupts + * + * siOurMSIInterrupt checks if we generated interrupt + * called thru function pointer saRoot->OurInterrupt + * + * \param agRoot OS Layer-specific and LL Layer-specific context handles for this + * instance of SAS/SATA hardware + * \return always true + */ +/*******************************************************************************/ +bit32 siOurMSIInterrupt( + agsaRoot_t *agRoot, + bit32 interruptVectorIndex + ) +{ + return(TRUE); +} + +/******************************************************************************/ +/*! \brief Function to process MSI V interrupts + * + * siOurMSIInterrupt checks if we generated interrupt + * called thru function pointer saRoot->OurInterrupt + * + * \param agRoot OS Layer-specific and LL Layer-specific context handles for this + * instance of SAS/SATA hardware + * \return always true + */ +/*******************************************************************************/ +bit32 siOurMSI_V_Interrupt( + agsaRoot_t *agRoot, + bit32 interruptVectorIndex + ) +{ + SA_DBG4((":siOurMSI_V_Interrupt\n")); + return(TRUE); +} + +/******************************************************************************/ +/*! \brief Function to process Legacy interrupts + * + * siOurLegacyInterrupt checks if we generated interrupt + * called thru function pointer saRoot->OurInterrupt + * + * \param agRoot OS Layer-specific and LL Layer-specific context handles for this + * instance of SAS/SATA hardware + * \return true if we claim interrupt + */ +/*******************************************************************************/ +bit32 siOurLegacyInterrupt( + agsaRoot_t *agRoot, + bit32 interruptVectorIndex + ) +{ + bit32 Int_masked; + bit32 Int_active; + Int_masked = MSGU_READ_ODMR; + Int_active = MSGU_READ_ODR; + + if(Int_masked & 1 ) + { + return(FALSE); + } + if(Int_active & 1 ) + { + + return(TRUE); + } + return(FALSE); +} + +/******************************************************************************/ +/*! \brief Function to process Legacy V interrupts + * + * siOurLegacyInterrupt checks if we generated interrupt + * called thru function pointer saRoot->OurInterrupt + * + * \param agRoot OS Layer-specific and LL Layer-specific context handles for this + * instance of SAS/SATA hardware + * \return true if we claim interrupt + */ +/*******************************************************************************/ +bit32 siOurLegacy_V_Interrupt( + agsaRoot_t *agRoot, + bit32 interruptVectorIndex + ) +{ + bit32 Int_active; + Int_active = siHalRegReadExt(agRoot, GEN_MSGU_ODR, V_Outbound_Doorbell_Set_Register ); + + return(Int_active ? TRUE : FALSE); +} + + +/******************************************************************************/ +/*! \brief Function to process the cause of interrupt + * + * The saDelayedInterruptHandler() function is called after an interrupt messages has + * been received it may be called by a deferred procedure call + * + * \param agRoot OS Layer-specific and LL Layer-specific context handles for this + * instance of SAS/SATA hardware + * \param interruptVectorIndex - vector index for message + * \param count Number of completion queue entries to consume + * + * \return number of messages processed + * + */ +/*******************************************************************************/ +FORCEINLINE bit32 +saDelayedInterruptHandler( + agsaRoot_t *agRoot, + bit32 interruptVectorIndex, + bit32 count + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + bit32 processedMsgCount = 0; + bit32 pad1 = 0; + bit32 host_reg0 = 0; +#if defined(SALLSDK_DEBUG) + bit32 host_reg1 = 0; +#endif + bit8 i = 0; + + OSSA_OUT_ENTER(agRoot); + + smTraceFuncEnter(hpDBG_VERY_LOUD,"5p"); + + smTrace(hpDBG_VERY_LOUD,"Vd",interruptVectorIndex); + /* TP:Vd delayed VectorIndex */ + smTrace(hpDBG_VERY_LOUD,"Vc",count); + /* TP:Vc IOMB count*/ + + if( saRoot->swConfig.fatalErrorInterruptEnable && + saRoot->swConfig.fatalErrorInterruptVector == interruptVectorIndex ) + { + pad1 = siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1); + host_reg0 = ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_Rsvd_0_Register ); + + + if(saRoot->swConfig.hostDirectAccessMode & 2 ) + { + if( host_reg0 == HDA_AES_DIF_FUNC) + { + host_reg0 = 0; + } + } + + +#if defined(SALLSDK_DEBUG) + host_reg1 = ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_Rsvd_1_Register ); +#endif + if( (SCRATCH_PAD1_V_ERROR_STATE( pad1 ) != 0 ) && host_reg0 ) + { + + SA_DBG1(("saDelayedInterruptHandler: vi %d Error %08X\n",interruptVectorIndex, SCRATCH_PAD1_V_ERROR_STATE( pad1 ))); + SA_DBG1(("saDelayedInterruptHandler: Sp 1 %08X Hr0 %08X Hr1 %08X\n",pad1,host_reg0,host_reg1 )); + SA_DBG1(("saDelayedInterruptHandler: SCRATCH_PAD1_V_ERROR_STATE %08X\n", SCRATCH_PAD1_V_ERROR_STATE( pad1 ))); + SA_DBG1(("saDelayedInterruptHandler: SCRATCH_PAD1_V_ILA_ERROR_STATE %08X\n", SCRATCH_PAD1_V_ILA_ERROR_STATE( pad1 ))); + SA_DBG1(("saDelayedInterruptHandler: SCRATCH_PAD1_V_RAAE_ERROR_STATE %08X\n", SCRATCH_PAD1_V_RAAE_ERROR_STATE( pad1 ))); + SA_DBG1(("saDelayedInterruptHandler: SCRATCH_PAD1_V_IOP0_ERROR_STATE %08X\n", SCRATCH_PAD1_V_IOP0_ERROR_STATE( pad1 ))); + SA_DBG1(("saDelayedInterruptHandler: SCRATCH_PAD1_V_IOP1_ERROR_STATE %08X\n", SCRATCH_PAD1_V_IOP1_ERROR_STATE( pad1 ))); + + siFatalInterruptHandler( agRoot, interruptVectorIndex ); + ossaDisableInterrupts(agRoot, interruptVectorIndex); + + } + else + { + SA_DBG2(("saDelayedInterruptHandler: Fatal Check VI %d SCRATCH_PAD1 %08X host_reg0 %08X host_reg1 %08X\n",interruptVectorIndex, pad1,host_reg0,host_reg1)); + SA_DBG2(("saDelayedInterruptHandler: ScratchPad0 0x%x ScratchPad1 0x%x\n", + ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register), + ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_1_Register) )); + SA_DBG2(("saDelayedInterruptHandler: ScratchPad2 0x%x ScratchPad3 0x%x\n", + ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_2_Register), + ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_3_Register) )); + + SA_DBG2(("saDelayedInterruptHandler: Doorbell_Set %08X U %08X\n", + ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_Register), + ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_RegisterU))); + SA_DBG2(("saDelayedInterruptHandler: Doorbell_Mask %08X U %08X\n", + ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register ), + ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_RegisterU ))); + } + + } + + +#ifdef SA_LNX_PERF_MODE + return siProcessOBMsg(agRoot, count, interruptVectorIndex); +#endif + + /* check all the configuration outbound queues within a vector bitmap */ + SA_ASSERT((saRoot->QueueConfig.numOutboundQueues < 65), "numOutboundQueue"); + + for ( i = 0; i < saRoot->QueueConfig.numOutboundQueues; i++ ) + { + /* process IOMB in the outbound queue 0 to 31 if bit set in the vector bitmap */ + if (i < OQ_NUM_32) + { + if (saRoot->interruptVecIndexBitMap[interruptVectorIndex] & (1 << i)) + { + processedMsgCount += siProcessOBMsg(agRoot, count, i); + } + else if (saRoot->QueueConfig.outboundQueues[i].interruptEnable == 0) + { + /* polling mode - interruptVectorIndex = 0 only and no bit set */ + processedMsgCount += siProcessOBMsg(agRoot, count, i); + } +#ifdef SA_FW_TEST_INTERRUPT_REASSERT + else if (saRoot->CheckAll) + { + /* polling mode - interruptVectorIndex = 0 only and no bit set */ + processedMsgCount += siProcessOBMsg(agRoot, count, i); + } +#endif /* SA_FW_TEST_INTERRUPT_REASSERT */ + + } + else + { + /* process IOMB in the outbound queue 32 to 63 if bit set in the vector bitmap */ + if (saRoot->interruptVecIndexBitMap1[interruptVectorIndex] & (1 << (i - OQ_NUM_32))) + { + processedMsgCount += siProcessOBMsg(agRoot, count, i); + } + /* check interruptEnable bit for polling mode of OQ */ + /* the following code can be removed, we do not care about the bit */ + else if (saRoot->QueueConfig.outboundQueues[i].interruptEnable == 0) + { + /* polling mode - interruptVectorIndex = 0 only and no bit set */ + processedMsgCount += siProcessOBMsg(agRoot, count, i); + } +#ifdef SA_FW_TEST_INTERRUPT_REASSERT + else if (saRoot->CheckAll) + { + /* polling mode - interruptVectorIndex = 0 only and no bit set */ + processedMsgCount += siProcessOBMsg(agRoot, count, i); + } +#endif /* SA_FW_TEST_INTERRUPT_REASSERT */ + } + } + +#ifdef SA_FW_TEST_INTERRUPT_REASSERT + saRoot->CheckAll = 0; +#endif /* SA_FW_TEST_INTERRUPT_REASSERT */ + +#ifndef SA_RENABLE_IN_OSLAYER + if ( agTRUE == saRoot->sysIntsActive ) + { + /* Allow replacement of enable interrupt */ + ossaReenableInterrupts(agRoot, interruptVectorIndex); + } +#endif /* SA_RENABLE_IN_OSLAYER */ + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5p"); + + OSSA_OUT_LEAVE(agRoot); + return processedMsgCount; +} + +/******************************************************************************/ +/*! \brief Function to reenable MSIX interrupts + * + * siReenableMSIXInterrupts reenableinterrupts + * called thru macro ossaReenableInterrupts + * + * \param agRoot OS Layer-specific and LL Layer-specific context handles for this + * instance of SAS/SATA hardware + * \param interruptVectorIndex - vector index for message + * + */ +/*******************************************************************************/ +void siReenableMSIXInterrupts( + agsaRoot_t *agRoot, + bit32 interruptVectorIndex + ) +{ + bit32 msi_index; +#ifdef SA_CLEAR_ODCR_IN_INTERRUPT + bit32 value; +#endif /* SA_CLEAR_ODCR_IN_INTERRUPT */ + msi_index = interruptVectorIndex * MSIX_TABLE_ELEMENT_SIZE; + msi_index += MSIX_TABLE_BASE; + ossaHwRegWriteExt(agRoot, PCIBAR0,msi_index, MSIX_INTERRUPT_ENABLE); + + SA_DBG4(("siReenableMSIXInterrupts:interruptVectorIndex %d\n",interruptVectorIndex)); + +#ifdef SA_CLEAR_ODCR_IN_INTERRUPT + value = (1 << interruptVectorIndex); + siHalRegWriteExt(agRoot, GEN_MSGU_ODCR, MSGU_ODCR, value); +#endif /* SA_CLEAR_ODCR_IN_INTERRUPT */ +} +/******************************************************************************/ +/*! \brief Function to reenable MSIX interrupts + * + * siReenableMSIXInterrupts reenableinterrupts + * called thru macro ossaReenableInterrupts + * + * \param agRoot OS Layer-specific and LL Layer-specific context handles for this + * instance of SAS/SATA hardware + * \param interruptVectorIndex - vector index for message + * + */ +/*******************************************************************************/ +void siReenableMSIX_V_Interrupts( + agsaRoot_t *agRoot, + bit32 interruptVectorIndex + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + bit64 mask; + agsabit32bit64 u64; + mask =( (bit64)1 << interruptVectorIndex); + u64.B64 = mask; + + SA_DBG4(("siReenableMSIX_V_Interrupts:\n")); + + if(saRoot->sysIntsActive) + { + if(smIS64bInt(agRoot)) + { + SA_DBG4(("siReenableMSIX_V_Interrupts: VI %d U 0x%08X L 0x%08X\n",interruptVectorIndex,u64.S32[1],u64.S32[0])); + ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Clear_RegisterU,u64.S32[1] ); + } + ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Clear_Register,u64.S32[0]); + } + else + { + SA_DBG1(("siReenableMSIX_V_Interrupts: VI %d sysIntsActive off\n",interruptVectorIndex)); + } + +} + +/******************************************************************************/ +/*! \brief Function to reenable MSI interrupts + * + * siReenableMSIXInterrupts reenableinterrupts + * called thru macro ossaReenableInterrupts + * + * \param agRoot OS Layer-specific and LL Layer-specific context handles for this + * instance of SAS/SATA hardware + * \param interruptVectorIndex - vector index for message + * + */ +/*******************************************************************************/ +GLOBAL void siReenableMSIInterrupts( + agsaRoot_t *agRoot, + bit32 interruptVectorIndex + ) +{ + bit32 ODMRValue; + + ODMRValue = siHalRegReadExt(agRoot, GEN_MSGU_ODMR, MSGU_ODMR); + ODMRValue &= ~(1 << interruptVectorIndex); + + siHalRegWriteExt(agRoot, GEN_MSGU_ODMR, MSGU_ODMR, ODMRValue); +} + +/******************************************************************************/ +/*! \brief Function to reenable MSI V interrupts + * + * siReenableMSIXInterrupts reenableinterrupts + * called thru macro ossaReenableInterrupts + * + * \param agRoot OS Layer-specific and LL Layer-specific context handles for this + * instance of SAS/SATA hardware + * \param interruptVectorIndex - vector index for message + * + */ +/*******************************************************************************/ +GLOBAL void siReenableMSI_V_Interrupts( + agsaRoot_t *agRoot, + bit32 interruptVectorIndex + ) +{ + SA_ASSERT(0, "Should not be called"); + + SA_DBG4(("siReenableMSI_V_Interrupts:\n")); + +} +/******************************************************************************/ +/*! \brief Function to reenable Legacy interrupts + * + * siReenableLegacyInterrupts reenableinterrupts + * called thru macro ossaReenableInterrupts + * + * \param agRoot OS Layer-specific and LL Layer-specific context handles for this + * instance of SAS/SATA hardware + * \param interruptVectorIndex always zero + * + */ +/*******************************************************************************/ +GLOBAL void siReenableLegacyInterrupts( + agsaRoot_t *agRoot, + bit32 interruptVectorIndex + ) +{ + siHalRegWriteExt(agRoot, GEN_MSGU_ODMR, MSGU_ODMR, ODMR_CLEAR_ALL); + +#ifdef SA_CLEAR_ODCR_IN_INTERRUPT + siHalRegWriteExt(agRoot, GEN_MSGU_ODCR, MSGU_ODCR, ODCR_CLEAR_ALL); +#endif /* SA_CLEAR_ODCR_IN_INTERRUPT */ +} + +/******************************************************************************/ +/*! \brief Function to reenable Legacy V interrupts + * + * siReenableLegacyInterrupts reenableinterrupts + * called thru macro ossaReenableInterrupts + * + * \param agRoot OS Layer-specific and LL Layer-specific context handles for this + * instance of SAS/SATA hardware + * \param interruptVectorIndex always zero + * + */ +/*******************************************************************************/ +GLOBAL void siReenableLegacy_V_Interrupts( + agsaRoot_t *agRoot, + bit32 interruptVectorIndex + ) +{ + + bit32 mask; + mask = 1 << interruptVectorIndex; + + SA_DBG5(("siReenableLegacy_V_Interrupts:IN MSGU_READ_ODR %08X\n",siHalRegReadExt(agRoot, GEN_MSGU_ODR, V_Outbound_Doorbell_Set_Register))); + SA_DBG5(("siReenableLegacy_V_Interrupts:IN MSGU_READ_ODMR %08X\n",siHalRegReadExt(agRoot, GEN_MSGU_ODMR, V_Outbound_Doorbell_Mask_Set_Register ))); + + ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Clear_Register, mask); + ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Clear_Register, mask ); + + + SA_DBG5(("siReenableLegacy_V_Interrupts:OUT MSGU_READ_ODMR %08X\n",siHalRegReadExt(agRoot, GEN_MSGU_ODMR, V_Outbound_Doorbell_Mask_Set_Register ))); + +} + +/******************************************************************************/ +/*! \brief Function to enable a single interrupt vector + * + * + * + * \param agRoot OS Layer-specific and LL Layer-specific context handles for this + * instance of SAS/SATA hardware + * \param interruptVectorIndex Interrupt vector to enable + * + */ +/*******************************************************************************/ +/******************************************************************************/ +/*! \brief saSystemInterruptsEnable + * Function to enable a single interrupt vector + * + * \param agRoot OS Layer-specific and LL Layer-specific context handles for this + * instance of SAS/SATA hardware + * \param interruptVectorIndex Interrupt vector to enable + * + */ +/*******************************************************************************/ +GLOBAL FORCEINLINE +void saSystemInterruptsEnable( + agsaRoot_t *agRoot, + bit32 interruptVectorIndex + ) +{ + ossaReenableInterrupts(agRoot, interruptVectorIndex); +} +/******************************************************************************/ +/*! \brief Routine to handle Outbound Message + * + * The handle for outbound message + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param count interrupt message count + * \param queueNum outbound queue + * + * \return + */ +/*******************************************************************************/ +LOCAL FORCEINLINE bit32 +siProcessOBMsg( + agsaRoot_t *agRoot, + bit32 count, + bit32 queueNum + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + mpiOCQueue_t *circularQ = agNULL; + void *pMsg1 = agNULL; + bit32 ret, processedMsgCount = 0; + bit32 ParseOBIombStatus = 0; +#ifdef SA_ENABLE_TRACE_FUNCTIONS + bit32 i = 0; +#endif + bit16 opcode = 0; + mpiMsgCategory_t category; + bit8 bc = 0; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"5r"); + + + SA_DBG3(("siProcessOBMsg: queueNum 0x%x\n", queueNum)); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_OBQ_LOCK + queueNum); + + circularQ = &saRoot->outboundQueue[queueNum]; + OSSA_READ_LE_32(circularQ->agRoot, &circularQ->producerIdx, circularQ->piPointer, 0); + + if (circularQ->producerIdx == circularQ->consumerIdx) + { + ossaSingleThreadedLeave(agRoot, LL_IOREQ_OBQ_LOCK + queueNum); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5r"); + return processedMsgCount; + } + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_OBQ_LOCK + queueNum); + + do + { + /* ossaSingleThreadedEnter(agRoot, LL_IOREQ_OBQ_LOCK + queueNum); */ + ret = mpiMsgConsume(circularQ, &pMsg1, &category, &opcode, &bc); + /* ossaSingleThreadedLeave(agRoot, LL_IOREQ_OBQ_LOCK + queueNum); */ + + if (AGSA_RC_SUCCESS == ret) + { + smTrace(hpDBG_IOMB,"M0",queueNum); + /* TP:M0 queueNum */ + smTrace(hpDBG_VERY_LOUD,"MA",opcode); + /* TP:MA opcode */ + smTrace(hpDBG_IOMB,"MB",category); + /* TP:MB category */ + +#ifdef SA_ENABLE_TRACE_FUNCTIONS + for (i=0; i<((bit32)bc*(circularQ->elementSize/4)); i++) + { + /* The -sizeof(mpiMsgHeader_t) is to account for mpiMsgConsume incrementing the pointer past the header*/ + smTrace(hpDBG_IOMB,"MC",*( ((bit32*)((bit8 *)pMsg1 - sizeof(mpiMsgHeader_t))) + i)); + /* TP:MC Outbound IOMB Dword */ + } +#endif + + MPI_DEBUG_TRACE( circularQ->qNumber,((circularQ->producerIdx << 16 ) | circularQ->consumerIdx),MPI_DEBUG_TRACE_OBQ, (void *)(((bit8*)pMsg1) - sizeof(mpiMsgHeader_t)), circularQ->elementSize); + + ossaLogIomb(circularQ->agRoot, + circularQ->qNumber, + FALSE, + (void *)(((bit8*)pMsg1) - sizeof(mpiMsgHeader_t)), + bc*circularQ->elementSize); + + ossaQueueProcessed(agRoot, queueNum, circularQ->producerIdx, circularQ->consumerIdx); + /* process the outbound message */ + ParseOBIombStatus = mpiParseOBIomb(agRoot, (bit32 *)pMsg1, category, opcode); + if (ParseOBIombStatus == AGSA_RC_FAILURE) + { + SA_DBG1(("siProcessOBMsg, Failed Q %2d PI 0x%03x CI 0x%03x\n", queueNum, circularQ->producerIdx, circularQ->consumerIdx)); +#if defined(SALLSDK_DEBUG) + /* free the message for debug: this is a hang! */ + + mpiMsgFreeSet(circularQ, pMsg1, bc); + processedMsgCount ++; +#endif /**/ + break; + } + + /* free the message from the outbound circular buffer */ + mpiMsgFreeSet(circularQ, pMsg1, bc); + processedMsgCount ++; + } + else + //if (AGSA_RC_BUSY == ret) // always (circularQ->producerIdx == circularQ->consumerIdx) + // || (AGSA_RC_FAILURE == ret) + { + break; + } + } + /* end of message processing if hit the count */ + while(count > processedMsgCount); + +/* #define SALLSDK_FATAL_ERROR_DETECT 1 */ +/* + this comments are to be removed + fill in 0x1D 0x1e 0x1f 0x20 in MPI table for + bit32 regDumpBusBaseNum0; + bit32 regDumpOffset0; + bit32 regDumpLen0; + bit32 regDumpBusBaseNum1; + bit32 regDumpOffset1; + bit32 regDumpLen1; + in agsaFatalErrorInfo_t + + ??? regDumpBusBaseNum0 and regDumpBusBaseNum1 + saRoot->mainConfigTable.regDumpPCIBAR = pcibar; + saRoot->mainConfigTable.FatalErrorDumpOffset0 = config->FatalErrorDumpOffset0; + saRoot->mainConfigTable.FatalErrorDumpLength0 = config->FatalErrorDumpLength0; + saRoot->mainConfigTable.FatalErrorDumpOffset1 = config->FatalErrorDumpOffset1; + saRoot->mainConfigTable.FatalErrorDumpLength1 = config->FatalErrorDumpLength1; + + + +*/ +#if defined(SALLSDK_FATAL_ERROR_DETECT) + + if( smIS_SPC(agRoot) ) /* SPC only */ + { + + /* any fatal error happened */ + /* executing this code impacts performance by 1% when no error is detected */ + { + agsaFatalErrorInfo_t fatal_error; + bit32 value; + bit32 value1; + + value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1); + value1 = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2, MSGU_SCRATCH_PAD_2); + + if( (value & SA_FATAL_ERROR_SP1_AAP1_ERR_MASK) == SA_FATAL_ERROR_FATAL_ERROR || + (value1 & SA_FATAL_ERROR_SP2_IOP_ERR_MASK) == SA_FATAL_ERROR_FATAL_ERROR ) + { + si_memset(&fatal_error, 0, sizeof(agsaFatalErrorInfo_t)); + /* read detail fatal errors */ + value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0, MSGU_SCRATCH_PAD_0); + fatal_error.errorInfo0 = value; + SA_DBG1(("siProcessOBMsg: ScratchPad0 AAP error code 0x%x\n", value)); + + value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1); + fatal_error.errorInfo1 = value; + /* AAP error state */ + SA_DBG1(("siProcessOBMsg: AAP error state and error code 0x%x\n", value)); + value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2, MSGU_SCRATCH_PAD_2); + fatal_error.errorInfo2 = value; + /* IOP error state */ + SA_DBG1(("siProcessOBMsg: IOP error state and error code 0x%x\n", value)); + value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3, MSGU_SCRATCH_PAD_3); + SA_DBG1(("siProcessOBMsg: ScratchPad3 IOP error code 0x%x\n", value)); + fatal_error.errorInfo3 = value; + + if (agNULL != saRoot) + { + fatal_error.regDumpBusBaseNum0 = saRoot->mainConfigTable.regDumpPCIBAR; + fatal_error.regDumpOffset0 = saRoot->mainConfigTable.FatalErrorDumpOffset0; + fatal_error.regDumpLen0 = saRoot->mainConfigTable.FatalErrorDumpLength0; + fatal_error.regDumpBusBaseNum1 = saRoot->mainConfigTable.regDumpPCIBAR; + fatal_error.regDumpOffset1 = saRoot->mainConfigTable.FatalErrorDumpOffset1; + fatal_error.regDumpLen1 = saRoot->mainConfigTable.FatalErrorDumpLength1; + } + else + { + fatal_error.regDumpBusBaseNum0 = 0; + fatal_error.regDumpOffset0 = 0; + fatal_error.regDumpLen0 = 0; + fatal_error.regDumpBusBaseNum1 = 0; + fatal_error.regDumpOffset1 = 0; + fatal_error.regDumpLen1 = 0; + } + /* Call Back with error */ + SA_DBG1(("siProcessOBMsg: SALLSDK_FATAL_ERROR_DETECT \n")); + ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_MALFUNCTION, 0, (void *)&fatal_error, agNULL); + } + } + } +#endif /* SALLSDK_FATAL_ERROR_DETECT */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5r"); + return processedMsgCount; +} + +/******************************************************************************/ +/*! \brief Function to enable/disable interrupts + * + * The saSystemInterruptsActive() function is called to indicate to the LL Layer + * whether interrupts are available. The parameter sysIntsActive indicates whether + * interrupts are available at this time. + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param sysIntsActive flag for enable/disable interrupt + * + * \return -void- + * + */ +/*******************************************************************************/ +GLOBAL void saSystemInterruptsActive( + agsaRoot_t *agRoot, + agBOOLEAN sysIntsActive + ) +{ + bit32 x; + agsaLLRoot_t *saRoot; + + SA_ASSERT((agNULL != agRoot), ""); + if (agRoot == agNULL) + { + SA_DBG1(("saSystemInterruptsActive: agRoot == agNULL\n")); + return; + } + saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + SA_ASSERT((agNULL != saRoot), ""); + if (saRoot == agNULL) + { + SA_DBG1(("saSystemInterruptsActive: saRoot == agNULL\n")); + return; + } + + smTraceFuncEnter(hpDBG_TICK_INT,"5s"); + SA_DBG1(("saSystemInterruptsActive: now 0x%X new 0x%x\n",saRoot->sysIntsActive,sysIntsActive)); + SA_DBG3(("saSystemInterruptsActive: Doorbell_Set %08X U %08X\n", + ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_Register), + ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_RegisterU))); + SA_DBG3(("saSystemInterruptsActive: Doorbell_Mask %08X U %08X\n", + ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register ), + ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_RegisterU ))); + + if( saRoot->sysIntsActive && sysIntsActive ) + { + SA_DBG1(("saSystemInterruptsActive: Already active 0x%X new 0x%x\n",saRoot->sysIntsActive,sysIntsActive)); + smTraceFuncExit(hpDBG_TICK_INT, 'a', "5s"); + return; + } + + if( !saRoot->sysIntsActive && !sysIntsActive ) + { + if(smIS_SPC(agRoot)) + { + siHalRegWriteExt(agRoot, GEN_MSGU_ODMR, MSGU_ODMR,AGSA_INTERRUPT_HANDLE_ALL_CHANNELS ); + } + else + { + ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Set_Register, AGSA_INTERRUPT_HANDLE_ALL_CHANNELS); + ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Set_RegisterU, AGSA_INTERRUPT_HANDLE_ALL_CHANNELS); + } + SA_DBG1(("saSystemInterruptsActive: Already disabled 0x%X new 0x%x\n",saRoot->sysIntsActive,sysIntsActive)); + smTraceFuncExit(hpDBG_TICK_INT, 'b', "5s"); + return; + } + + /* Set the flag is sdkData */ + saRoot->sysIntsActive = (bit8)sysIntsActive; + + + smTrace(hpDBG_TICK_INT,"Vq",sysIntsActive); + /* TP:Vq sysIntsActive */ + /* If sysIntsActive is true */ + if ( agTRUE == sysIntsActive ) + { + + SA_DBG1(("saSystemInterruptsActive: Doorbell_Set %08X U %08X\n", + ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_Register), + ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_RegisterU))); + SA_DBG1(("saSystemInterruptsActive: Doorbell_Mask_Set %08X U %08X\n", + ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register), + ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_RegisterU))); + if(smIS_SPCV(agRoot)) + { + ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Clear_Register, 0xFFFFFFFF); + ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Clear_RegisterU, 0xFFFFFFFF); + } + /* enable interrupt */ + for(x=0; x < saRoot->numInterruptVectors; x++) + { + ossaReenableInterrupts(agRoot,x ); + } + + if(saRoot->swConfig.fatalErrorInterruptEnable) + { + ossaReenableInterrupts(agRoot,saRoot->swConfig.fatalErrorInterruptVector ); + } + + siHalRegWriteExt(agRoot, GEN_MSGU_ODMR, MSGU_ODMR, 0); + } + /* If sysIntsActive is false */ + else + { + /* disable interrupt */ + if(smIS_SPC(agRoot)) + { + siHalRegWriteExt(agRoot, GEN_MSGU_ODMR, MSGU_ODMR,AGSA_INTERRUPT_HANDLE_ALL_CHANNELS ); + } + else + { + ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Set_Register, AGSA_INTERRUPT_HANDLE_ALL_CHANNELS); + ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Set_RegisterU, AGSA_INTERRUPT_HANDLE_ALL_CHANNELS); + } + } + + SA_DBG3(("saSystemInterruptsActive: Doorbell_Set %08X U %08X\n", + ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_Register), + ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_RegisterU))); + SA_DBG3(("saSystemInterruptsActive: Doorbell_Mask %08X U %08X\n", + ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register ), + ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_RegisterU ))); + + + smTraceFuncExit(hpDBG_TICK_INT, 'c', "5s"); +} + +/******************************************************************************/ +/*! \brief Routine to handle for received SAS with data payload event + * + * The handle for received SAS with data payload event + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param pRequest handles for the IOrequest + * \param pRespIU the pointer to the Response IU + * \param param Payload Length + * + * \return -void- + */ +/*******************************************************************************/ +GLOBAL void siEventSSPResponseWtDataRcvd( + agsaRoot_t *agRoot, + agsaIORequestDesc_t *pRequest, + agsaSSPResponseInfoUnit_t *pRespIU, + bit32 param, + bit32 sspTag + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaDeviceDesc_t *pDevice; + bit32 count = 0; + bit32 padCount; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"5g"); + + /* get frame handle */ + + /* If the request is still valid */ + if ( agTRUE == pRequest->valid ) + { + /* get device */ + pDevice = pRequest->pDevice; + + /* Delete the request from the pendingIORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + if (sspTag & SSP_RESCV_BIT) + { + /* get the pad count, bit 17 and 18 of sspTag */ + padCount = (sspTag >> SSP_RESCV_PAD_SHIFT) & 0x3; + /* get Residual Count */ + count = *(bit32 *)((bit8 *)pRespIU + param + padCount); + } + + (*(ossaSSPCompletedCB_t)(pRequest->completionCB))(agRoot, + pRequest->pIORequestContext, + OSSA_IO_SUCCESS, + param, + (void *)pRespIU, + (bit16)(sspTag & SSPTAG_BITS), + count); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("siEventSSPResponseWtDataRcvd: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + } + else + { + SA_DBG1(("siEventSSPResponseWtDataRcvd: pRequest->Valid not TRUE\n")); + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5g"); + + return; +} + +/******************************************************************************/ +/*! \brief Routine to handle successfully completed IO event + * + * Handle successfully completed IO + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param pRequest Pointer of IO request of the IO + * \param status status of the IO + * + * \return -void- + */ +/*******************************************************************************/ +GLOBAL FORCEINLINE void siIODone( + agsaRoot_t *agRoot, + agsaIORequestDesc_t *pRequest, + bit32 status, + bit32 sspTag + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaDeviceDesc_t *pDevice = agNULL; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"5h"); + + SA_ASSERT(NULL != pRequest, "pRequest cannot be null"); + + /* If the request is still valid */ + if ( agTRUE == pRequest->valid ) + { + /* get device */ + pDevice = pRequest->pDevice; + + /* process different request type */ + switch (pRequest->requestType & AGSA_REQTYPE_MASK) + { + case AGSA_SSP_REQTYPE: + { + SA_ASSERT(pRequest->valid, "pRequest not valid"); + pRequest->completionCB(agRoot, + pRequest->pIORequestContext, + OSSA_IO_SUCCESS, + 0, + agNULL, + (bit16)(sspTag & SSPTAG_BITS), + 0); + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* Delete the request from the pendingIORequests */ + saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + /* return the request to free pool */ + pRequest->valid = agFALSE; + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + + break; + } + case AGSA_SATA_REQTYPE: + { + SA_DBG5(("siIODone: SATA complete\n")); + + if ( agNULL != pRequest->pIORequestContext ) + { + SA_DBG5(("siIODone: Complete Request\n")); + + (*(ossaSATACompletedCB_t)(pRequest->completionCB))(agRoot, + pRequest->pIORequestContext, + OSSA_IO_SUCCESS, + agNULL, + 0, + agNULL); + } + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* Delete the request from the pendingIORequests */ + saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + pRequest->valid = agFALSE; + + break; + } + case AGSA_SMP_REQTYPE: + { + if ( agNULL != pRequest->pIORequestContext ) + { + (*(ossaSMPCompletedCB_t)(pRequest->completionCB))(agRoot, + pRequest->pIORequestContext, + OSSA_IO_SUCCESS, + 0, + agNULL); + } + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* Delete the request from the pendingSMPRequests */ + saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("siIODone: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + pRequest->valid = agFALSE; + + break; + } + default: + { + SA_DBG1(("siIODone: unknown request type (%x) is completed. HTag=0x%x\n", pRequest->requestType, pRequest->HTag)); + break; + } + } + } + else + { + SA_DBG1(("siIODone: The request is not valid any more. HTag=0x%x requestType=0x%x\n", pRequest->HTag, pRequest->requestType)); + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5h"); + +} + +/******************************************************************************/ +/*! \brief Routine to handle abnormal completed IO/SMP event + * + * Handle abnormal completed IO/SMP + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param pRequest Pointer of IO request of the IO + * \param status status of the IO + * \param param Length + * + * \return -void- + */ +/*******************************************************************************/ +GLOBAL void siAbnormal( + agsaRoot_t *agRoot, + agsaIORequestDesc_t *pRequest, + bit32 status, + bit32 param, + bit32 sspTag + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaDeviceDesc_t *pDevice; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"5i"); + + if (agNULL == pRequest) + { + SA_DBG1(("siAbnormal: pRequest is NULL.\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5i"); + return; + } + + /* If the request is still valid */ + if ( agTRUE == pRequest->valid ) + { + /* get device */ + + SA_ASSERT((pRequest->pIORequestContext->osData != pRequest->pIORequestContext->sdkData), "pIORequestContext"); + + pDevice = pRequest->pDevice; + + /* remove the IO request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + + smTrace(hpDBG_VERY_LOUD,"P6",status ); + /* TP:P6 siAbnormal status */ + smTrace(hpDBG_VERY_LOUD,"P7",param ); + /* TP:P7 siAbnormal param */ + /* process different request type */ + switch (pRequest->requestType & AGSA_REQTYPE_MASK) + { + case AGSA_SSP_REQTYPE: + { + (*(ossaSSPCompletedCB_t)(pRequest->completionCB))(agRoot, + pRequest->pIORequestContext, + status, + param, + agNULL, + (bit16)(sspTag & SSPTAG_BITS), + ((sspTag & SSP_AGR_S_BIT)? (1 << 0) : 0)); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* Delete the request from the pendingIORequests */ + saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("siAbnormal: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + break; + } + case AGSA_SATA_REQTYPE: + { + SA_DBG5(("siAbnormal: SATA \n")); + + if ( agNULL != pRequest->pIORequestContext ) + { + SA_DBG5(("siAbnormal: Calling SATACompletedCB\n")); + + (*(ossaSATACompletedCB_t)(pRequest->completionCB))(agRoot, + pRequest->pIORequestContext, + status, + agNULL, + param, + agNULL); + } + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* Delete the request from the pendingIORequests */ + saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + /* return the request to free pool */ + pRequest->valid = agFALSE; + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("siAbnormal: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + break; + } + case AGSA_SMP_REQTYPE: + { + if ( agNULL != pRequest->pIORequestContext ) + { + (*(ossaSMPCompletedCB_t)(pRequest->completionCB))(agRoot, + pRequest->pIORequestContext, + status, + param, + agNULL); + } + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* Delete the request from the pendingSMPRequests */ + saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + /* return the request to free pool */ + pRequest->valid = agFALSE; + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("siAbnormal: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + break; + } + default: + { + SA_DBG1(("siAbnormal: unknown request type (%x) is completed. Tag=0x%x\n", pRequest->requestType, pRequest->HTag)); + break; + } + } + + } + else + { + SA_DBG1(("siAbnormal: The request is not valid any more. Tag=0x%x\n", pRequest->HTag)); + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5i"); + + return; +} + + +/******************************************************************************/ +/*! \brief Routine to handle abnormal DIF completed IO/SMP event + * + * Handle abnormal completed IO/SMP + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param pRequest Pointer of IO request of the IO + * \param status status of the IO + * \param param Length + * + * \return -void- + */ +/*******************************************************************************/ +GLOBAL void siDifAbnormal( + agsaRoot_t *agRoot, + agsaIORequestDesc_t *pRequest, + bit32 status, + bit32 param, + bit32 sspTag, + bit32 *pMsg1 + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaDeviceDesc_t *pDevice; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2S"); + + if (agNULL == pRequest) + { + SA_DBG1(("siDifAbnormal: pRequest is NULL.\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2S"); + return; + } + + /* If the request is still valid */ + if ( agTRUE == pRequest->valid ) + { + /* get device */ + pDevice = pRequest->pDevice; + + /* remove the IO request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + + smTrace(hpDBG_VERY_LOUD,"P6",status ); + /* TP:P6 siDifAbnormal status */ + /* process different request type */ + switch (pRequest->requestType & AGSA_REQTYPE_MASK) + { + case AGSA_SSP_REQTYPE: + { + agsaDifDetails_t agDifDetails; + agsaSSPCompletionDifRsp_t *pIomb; + pIomb = (agsaSSPCompletionDifRsp_t *)pMsg1; + si_memset(&agDifDetails, 0, sizeof(agDifDetails)); + + OSSA_READ_LE_32(agRoot, &agDifDetails.UpperLBA, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,UpperLBA )); + OSSA_READ_LE_32(agRoot, &agDifDetails.LowerLBA, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,LowerLBA )); + OSSA_READ_LE_32(agRoot, &agDifDetails.sasAddressHi, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,sasAddressHi )); + OSSA_READ_LE_32(agRoot, &agDifDetails.sasAddressLo, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,sasAddressLo)); + OSSA_READ_LE_32(agRoot, &agDifDetails.ExpectedCRCUDT01, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,ExpectedCRCUDT01 )); + OSSA_READ_LE_32(agRoot, &agDifDetails.ExpectedUDT2345, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,ExpectedUDT2345)); + OSSA_READ_LE_32(agRoot, &agDifDetails.ActualCRCUDT01, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,ActualCRCUDT01 )); + OSSA_READ_LE_32(agRoot, &agDifDetails.ActualUDT2345, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,ActualUDT2345)); + OSSA_READ_LE_32(agRoot, &agDifDetails.DIFErrDevID, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,DIFErrDevID )); + OSSA_READ_LE_32(agRoot, &agDifDetails.ErrBoffsetEDataLen, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,ErrBoffsetEDataLen )); + agDifDetails.frame = (void *)(bit8*)(pIomb+ OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t, EDATA_FRM)); + + (*(ossaSSPCompletedCB_t)(pRequest->completionCB))(agRoot, + pRequest->pIORequestContext, + status, + param, + &agDifDetails, + (bit16)(sspTag & SSPTAG_BITS), + ((sspTag & SSP_AGR_S_BIT)? (1 << 0) : 0)); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* Delete the request from the pendingIORequests */ + saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("siDifAbnormal: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + break; + } + default: + { + SA_DBG1(("siDifAbnormal: unknown request type (%x) is completed. Tag=0x%x\n", pRequest->requestType, pRequest->HTag)); + break; + } + } + + } + else + { + SA_DBG1(("siDifAbnormal: The request is not valid any more. Tag=0x%x\n", pRequest->HTag)); + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2S"); + + return; +} + + +/******************************************************************************/ +/*! \brief Routine to handle for received SMP response event + * + * The handle for received SMP response event + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param pIomb Pointer of payload of IOMB + * \param payloadSize size of the payload + * \param tag the tag of the request SMP + * + * \return -void- + */ +/*******************************************************************************/ +GLOBAL void siSMPRespRcvd( + agsaRoot_t *agRoot, + agsaSMPCompletionRsp_t *pIomb, + bit32 payloadSize, + bit32 tag + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaFrameHandle_t frameHandle; + agsaIORequestDesc_t *pRequest; + agsaDeviceDesc_t *pDevice; + agsaPort_t *pPort; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"5j"); + + /* get the request */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + SA_ASSERT(pRequest, "pRequest"); + + /* get the port */ + pPort = pRequest->pPort; + SA_ASSERT(pPort, "pPort"); + + if (pRequest->IRmode == 0) + { + /* get frame handle - direct response mode */ + frameHandle = (agsaFrameHandle_t)(&(pIomb->SMPrsp[0])); +#if defined(SALLSDK_DEBUG) + SA_DBG3(("saSMPRespRcvd(direct): smpRspPtr=0x%p - len=0x%x\n", + frameHandle, + payloadSize + )); +#endif /* SALLSDK_DEBUG */ + } + else + { + /* indirect response mode */ + frameHandle = agNULL; + } + + /* If the request is still valid */ + if ( agTRUE == pRequest->valid ) + { + /* get device */ + pDevice = pRequest->pDevice; + SA_ASSERT(pDevice, "pDevice"); + + /* Delete the request from the pendingSMPRequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* If the request is from OS layer */ + if ( agNULL != pRequest->pIORequestContext ) + { + if (agNULL == frameHandle) + { + /* indirect mode */ + /* call back with success */ + (*(ossaSMPCompletedCB_t)(pRequest->completionCB))(agRoot, pRequest->pIORequestContext, OSSA_IO_SUCCESS, payloadSize, frameHandle); + } + else + { + /* direct mode */ + /* call back with success */ + (*(ossaSMPCompletedCB_t)(pRequest->completionCB))(agRoot, pRequest->pIORequestContext, OSSA_IO_SUCCESS, payloadSize, frameHandle); + } + } + + /* remove the IO request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("siSMPRespRcvd: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5j"); + + return; +} + +/******************************************************************************/ +/*! \brief Routine to handle for received Phy Up event + * + * The handle for received Phy Up event + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param phyId for the Phy Up event happened + * \param agSASIdentify is the remote phy Identify + * \param portId is the port context index of the phy up event + * \param deviceId is the device context index + * \param linkRate link up rate from SPC + * + * \return -void- + */ +/*******************************************************************************/ +GLOBAL void siEventPhyUpRcvd( + agsaRoot_t *agRoot, + bit32 phyId, + agsaSASIdentify_t *agSASIdentify, + bit32 portId, + bit32 npipps, + bit8 linkRate + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaPhy_t *pPhy = &(saRoot->phys[phyId]); + agsaPort_t *pPort; + agsaSASIdentify_t remoteIdentify; + agsaPortContext_t *agPortContext; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"5k"); + + /* Read remote SAS Identify from response message and save it */ + remoteIdentify = *agSASIdentify; + + /* get port context from portMap */ + SA_DBG2(("siEventPhyUpRcvd:PortID 0x%x PortStatus 0x%x PortContext %p\n",saRoot->PortMap[portId & PORTID_MASK].PortID,saRoot->PortMap[portId & PORTID_MASK].PortStatus,saRoot->PortMap[portId & PORTID_MASK].PortContext)); + agPortContext = (agsaPortContext_t *)saRoot->PortMap[portId].PortContext; + + SA_DBG2(("siEventPhyUpRcvd: portID %d PortContext %p linkRate 0x%X\n", portId, agPortContext,linkRate)); + if (smIS_SPCV8006(agRoot)) + { + SA_DBG1(("siEventPhyUpRcvd: SAS_PHY_UP received for SATA Controller\n")); + return; + } + + if (agNULL != agPortContext) + { + /* existing port */ + pPort = (agsaPort_t *) (agPortContext->sdkData); + pPort->portId = portId; + + /* include the phy to the port */ + pPort->phyMap[phyId] = agTRUE; + /* Set the port for the phy */ + saRoot->phys[phyId].pPort = pPort; + + /* Update port state */ + if (OSSA_PORT_VALID == (npipps & PORT_STATE_MASK)) + { + pPort->status &= ~PORT_INVALIDATING; + saRoot->PortMap[portId].PortStatus &= ~PORT_INVALIDATING; + SA_DBG1(("siEventPhyUpRcvd: portID %d PortContext %p, hitting workaround\n", portId, agPortContext)); + } + } + else + { + ossaSingleThreadedEnter(agRoot, LL_PORT_LOCK); + /* new port */ + /* Allocate a free port */ + pPort = (agsaPort_t *) saLlistGetHead(&(saRoot->freePorts)); + if (agNULL != pPort) + { + /* Acquire port list lock */ + saLlistRemove(&(saRoot->freePorts), &(pPort->linkNode)); + + /* setup the port data structure */ + pPort->portContext.osData = agNULL; + pPort->portContext.sdkData = pPort; + + /* Add to valid port list */ + saLlistAdd(&(saRoot->validPorts), &(pPort->linkNode)); + /* Release port list lock */ + ossaSingleThreadedLeave(agRoot, LL_PORT_LOCK); + + /* include the phy to the port */ + pPort->phyMap[phyId] = agTRUE; + /* Set the port for the phy */ + saRoot->phys[phyId].pPort = pPort; + + /* Setup portMap based on portId */ + saRoot->PortMap[portId].PortID = portId; + saRoot->PortMap[portId].PortContext = &(pPort->portContext); + pPort->portId = portId; + + SA_DBG3(("siEventPhyUpRcvd: NewPort portID %d PortContext %p\n", portId, saRoot->PortMap[portId].PortContext)); + } + else + { + ossaSingleThreadedLeave(agRoot, LL_PORT_LOCK); + /* pPort is agNULL*/ + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5k"); + return; + } + + if (OSSA_PORT_VALID == (npipps & PORT_STATE_MASK)) + { + pPort->status &= ~PORT_INVALIDATING; + saRoot->PortMap[portId].PortStatus &= ~PORT_INVALIDATING; + } + else + { + SA_DBG1(("siEventPhyUpRcvd: PortInvalid portID %d PortContext %p\n", portId, saRoot->PortMap[portId].PortContext)); + } + } + + /* adjust the bit fields before callback */ + phyId = (linkRate << SHIFT8) | phyId; + /* report PhyId, NPIP, PortState */ + phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16); + ossaHwCB(agRoot, &(pPort->portContext), OSSA_HW_EVENT_SAS_PHY_UP, phyId, agNULL, &remoteIdentify); + + /* set PHY_UP status */ + PHY_STATUS_SET(pPhy, PHY_UP); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5k"); + + /* return */ + return; +} + +/******************************************************************************/ +/*! \brief Routine to handle for received SATA signature event + * + * The handle for received SATA signature event + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param phyId the phy id of the phy received the frame + * \param pMsg the pointer to the message payload + * \param portId the port context index of the phy up event + * \param deviceId the device context index + * \param linkRate link up rate from SPC + * + * \return -void- + */ +/*******************************************************************************/ +GLOBAL void siEventSATASignatureRcvd( + agsaRoot_t *agRoot, + bit32 phyId, + void *pMsg, + bit32 portId, + bit32 npipps, + bit8 linkRate + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaPhy_t *pPhy = &(saRoot->phys[phyId]); + agsaPort_t *pPort = agNULL; + agsaPortContext_t *agPortContext; +#if defined(SALLSDK_DEBUG) + agsaFisRegDeviceToHost_t *fisD2H; + /* Read the D2H FIS */ + fisD2H = (agsaFisRegDeviceToHost_t *)pMsg; +#endif /* SALLSDK_DEBUG */ + + smTraceFuncEnter(hpDBG_VERY_LOUD,"5m"); + + SA_DBG5(("siEventSATASignatureRcvd: About to read the signatureFIS data\n")); + + + SA_DBG5(("agsaFisRegDeviceToHost_t:\n")); + SA_DBG5((" fisType = %x\n", fisD2H->h.fisType)); + SA_DBG5((" i_pmPort = %x\n", fisD2H->h.i_pmPort)); + SA_DBG5((" status = %x\n", fisD2H->h.status)); + SA_DBG5((" error = %x\n", fisD2H->h.error)); + + SA_DBG5((" lbaLow = %x\n", fisD2H->d.lbaLow)); + SA_DBG5((" lbaMid = %x\n", fisD2H->d.lbaMid)); + SA_DBG5((" lbaHigh = %x\n", fisD2H->d.lbaHigh)); + SA_DBG5((" device = %x\n", fisD2H->d.device)); + + SA_DBG5((" lbaLowExp = %x\n", fisD2H->d.lbaLowExp)); + SA_DBG5((" lbaMidExp = %x\n", fisD2H->d.lbaMidExp)); + SA_DBG5((" lbaHighExp = %x\n", fisD2H->d.lbaHighExp)); + SA_DBG5((" reserved4 = %x\n", fisD2H->d.reserved4)); + + SA_DBG5((" sectorCount = %x\n", fisD2H->d.sectorCount)); + SA_DBG5((" sectorCountExp = %x\n", fisD2H->d.sectorCountExp)); + SA_DBG5((" reserved5 = %x\n", fisD2H->d.reserved5)); + SA_DBG5((" reserved6 = %x\n", fisD2H->d.reserved6)); + + SA_DBG5((" reserved7 (32) = %08X\n", fisD2H->d.reserved7)); + + SA_DBG5(("siEventSATASignatureRcvd: GOOD signatureFIS data\n")); + +#if defined(SALLSDK_DEBUG) + /* read signature */ + pPhy->remoteSignature[0] = (bit8) fisD2H->d.sectorCount; + pPhy->remoteSignature[1] = (bit8) fisD2H->d.lbaLow; + pPhy->remoteSignature[2] = (bit8) fisD2H->d.lbaMid; + pPhy->remoteSignature[3] = (bit8) fisD2H->d.lbaHigh; + pPhy->remoteSignature[4] = (bit8) fisD2H->d.device; +#endif + + /* get port context from portMap */ + SA_DBG2(("siEventSATASignatureRcvd:PortID 0x%x PortStatus 0x%x PortContext %p\n",saRoot->PortMap[portId & PORTID_MASK].PortID,saRoot->PortMap[portId & PORTID_MASK].PortStatus,saRoot->PortMap[portId & PORTID_MASK].PortContext)); + agPortContext = (agsaPortContext_t *)saRoot->PortMap[portId].PortContext; + + SA_DBG2(("siEventSATASignatureRcvd: portID %d PortContext %p\n", portId, agPortContext)); + + if (agNULL != agPortContext) + { + /* exist port */ + pPort = (agsaPort_t *) (agPortContext->sdkData); + pPort->portId = portId; + + /* include the phy to the port */ + pPort->phyMap[phyId] = agTRUE; + /* Set the port for the phy */ + saRoot->phys[phyId].pPort = pPort; + } + else + { + ossaSingleThreadedEnter(agRoot, LL_PORT_LOCK); + /* new port */ + /* Allocate a free port */ + pPort = (agsaPort_t *) saLlistGetHead(&(saRoot->freePorts)); + if (agNULL != pPort) + { + /* Acquire port list lock */ + saLlistRemove(&(saRoot->freePorts), &(pPort->linkNode)); + + /* setup the port data structure */ + pPort->portContext.osData = agNULL; + pPort->portContext.sdkData = pPort; + + /* Add to valid port list */ + saLlistAdd(&(saRoot->validPorts), &(pPort->linkNode)); + /* Release port list lock */ + ossaSingleThreadedLeave(agRoot, LL_PORT_LOCK); + + /* include the phy to the port */ + pPort->phyMap[phyId] = agTRUE; + /* Set the port for the phy */ + saRoot->phys[phyId].pPort = pPort; + + /* Setup portMap based on portId */ + saRoot->PortMap[portId].PortID = portId; + saRoot->PortMap[portId].PortContext = &(pPort->portContext); + pPort->portId = portId; + SA_DBG3(("siEventSATASignatureRcvd: NewPort portID %d portContect %p\n", portId, saRoot->PortMap[portId].PortContext)); + } + else + { + ossaSingleThreadedLeave(agRoot, LL_PORT_LOCK); + /* pPort is agNULL*/ + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5m"); + return; + } + + if (OSSA_PORT_VALID == (npipps & PORT_STATE_MASK)) + { + pPort->status &= ~PORT_INVALIDATING; + saRoot->PortMap[portId].PortStatus &= ~PORT_INVALIDATING; + } + else + { + SA_DBG1(("siEventSATASignatureRcvd: PortInvalid portID %d PortContext %p\n", portId, saRoot->PortMap[portId].PortContext)); + } + } + + /* adjust the bit fields before callback */ + phyId = (linkRate << SHIFT8) | phyId; + /* report PhyId, NPIP, PortState */ + phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16); + ossaHwCB(agRoot, &(pPort->portContext), OSSA_HW_EVENT_SATA_PHY_UP, phyId, agNULL, pMsg); + + /* set PHY_UP status */ + PHY_STATUS_SET(pPhy, PHY_UP); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5m"); + + /* return */ + return; +} + + +/******************************************************************************/ +/*! \brief Process Outbound IOMB Message + * + * Process Outbound IOMB from SPC + * + * \param agRoot Handles for this instance of SAS/SATA LL Layer + * \param pMsg1 Pointer of Response IOMB message 1 + * \param category category of outbpond IOMB header + * \param opcode Opcode of Outbound IOMB header + * \param bc buffer count of IOMB header + * + * \return success or fail + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiParseOBIomb( + agsaRoot_t *agRoot, + bit32 *pMsg1, + mpiMsgCategory_t category, + bit16 opcode + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + bit32 ret = AGSA_RC_SUCCESS; + bit32 parserStatus = AGSA_RC_SUCCESS; + + smTraceFuncEnter(hpDBG_VERY_LOUD, "2f"); + + switch (opcode) + { + case OPC_OUB_COMBINED_SSP_COMP: + { + agsaSSPCoalescedCompletionRsp_t *pIomb = (agsaSSPCoalescedCompletionRsp_t *)pMsg1; + agsaIORequestDesc_t *pRequest = agNULL; + bit32 tag = 0; + bit32 sspTag = 0; + bit32 count = 0; + +#ifdef SALL_API_TEST + saRoot->LLCounters.IOCounter.numSSPCompleted++; + SA_DBG3(("mpiParseOBIomb, SSP_COMP Response received IOMB=%p %d\n", + pMsg1, saRoot->LLCounters.IOCounter.numSSPCompleted)); +#else + SA_DBG3(("mpiParseOBIomb, OPC_OUB_COMBINED_SSP_COMP Response received IOMB=%p\n", pMsg1)); +#endif + /* get Tag */ + for (count = 0; count < pIomb->coalescedCount; count++) + { + tag = pIomb->sspComplCxt[count].tag; + sspTag = pIomb->sspComplCxt[count].SSPTag; + pRequest = (agsaIORequestDesc_t *)saRoot->IOMap[tag].IORequest; + SA_ASSERT((pRequest), "pRequest"); + + if(pRequest == agNULL) + { + SA_DBG1(("mpiParseOBIomb,OPC_OUB_COMBINED_SSP_COMP Resp IOMB tag=0x%x, status=0x%x, param=0x%x, SSPTag=0x%x\n", tag, OSSA_IO_SUCCESS, 0, sspTag)); +#ifdef SA_ENABLE_PCI_TRIGGER + if( saRoot->swConfig.PCI_trigger & PCI_TRIGGER_COAL_IOMB_ERROR ) + { + siPCITriger(agRoot); + } +#endif /* SA_ENABLE_PCI_TRIGGER */ + return(AGSA_RC_FAILURE); + } + SA_ASSERT((pRequest->valid), "pRequest->valid"); + +#ifdef SA_ENABLE_PCI_TRIGGER + if(!pRequest->valid) + { + if( saRoot->swConfig.PCI_trigger & PCI_TRIGGER_COAL_INVALID ) + { + siPCITriger(agRoot); + } + } +#endif /* SA_ENABLE_PCI_TRIGGER */ + + + SA_DBG3(("mpiParseOBIomb, OPC_OUB_COMBINED_SSP_COMP IOMB tag=0x%x, status=0x%x, param=0x%x, SSPTag=0x%x\n", tag, OSSA_IO_SUCCESS, 0, sspTag)); + + /* Completion of SSP without Response Data */ + siIODone( agRoot, pRequest, OSSA_IO_SUCCESS, sspTag); + } + } + break; + + case OPC_OUB_SSP_COMP: + { +#ifdef SALL_API_TEST + saRoot->LLCounters.IOCounter.numSSPCompleted++; + SA_DBG3(("mpiParseOBIomb, SSP_COMP Response received IOMB=%p %d\n", + pMsg1, saRoot->LLCounters.IOCounter.numSSPCompleted)); +#else + SA_DBG3(("mpiParseOBIomb, SSP_COMP Response received IOMB=%p\n", pMsg1)); +#endif + /* process the SSP IO Completed response message */ + mpiSSPCompletion(agRoot, pMsg1); + break; + } + case OPC_OUB_COMBINED_SATA_COMP: + { + agsaSATACoalescedCompletionRsp_t *pIomb; + agsaIORequestDesc_t *pRequest; + bit32 tag; + bit32 count; + + #ifdef SALL_API_TEST + saRoot->LLCounters.IOCounter.numSSPCompleted++; + SA_DBG3(("mpiParseOBIomb, OPC_OUB_COMBINED_SATA_COMP Response received IOMB=%p %d\n", + pMsg1, saRoot->LLCounters.IOCounter.numSSPCompleted)); + #else + SA_DBG3(("mpiParseOBIomb, OPC_OUB_COMBINED_SATA_COMP Response received IOMB=%p\n", pMsg1)); + #endif + + pIomb = (agsaSATACoalescedCompletionRsp_t *)pMsg1; + /* get Tag */ + for (count = 0; count < pIomb->coalescedCount; count++) + { + tag = pIomb->stpComplCxt[count].tag; + pRequest = (agsaIORequestDesc_t *)saRoot->IOMap[tag].IORequest; + SA_ASSERT((pRequest), "pRequest"); + + if(pRequest == agNULL) + { + SA_DBG1(("mpiParseOBIomb,OPC_OUB_COMBINED_SATA_COMP Resp IOMB tag=0x%x, status=0x%x, param=0x%x\n", tag, OSSA_IO_SUCCESS, 0)); + return(AGSA_RC_FAILURE); + } + SA_ASSERT((pRequest->valid), "pRequest->valid"); + + SA_DBG3(("mpiParseOBIomb, OPC_OUB_COMBINED_SATA_COMP IOMB tag=0x%x, status=0x%x, param=0x%x\n", tag, OSSA_IO_SUCCESS, 0)); + + /* Completion of SATA without Response Data */ + siIODone( agRoot, pRequest, OSSA_IO_SUCCESS, 0); + } + break; + } + case OPC_OUB_SATA_COMP: + { +#ifdef SALL_API_TEST + saRoot->LLCounters.IOCounter.numSataCompleted++; + SA_DBG3(("mpiParseOBIomb, SATA_COMP Response received IOMB=%p %d\n", + pMsg1, saRoot->LLCounters.IOCounter.numSataCompleted)); +#else + SA_DBG3(("mpiParseOBIomb, SATA_COMP Response received IOMB=%p\n", pMsg1)); +#endif + /* process the response message */ + mpiSATACompletion(agRoot, pMsg1); + break; + } + case OPC_OUB_SSP_ABORT_RSP: + { +#ifdef SALL_API_TEST + saRoot->LLCounters.IOCounter.numSSPAbortedCB++; +#else + SA_DBG3(("mpiParseOBIomb, SSP_ABORT Response received IOMB=%p\n", pMsg1)); +#endif + /* process the response message */ + parserStatus = mpiSSPAbortRsp(agRoot, (agsaSSPAbortRsp_t *)pMsg1); + if(parserStatus != AGSA_RC_SUCCESS) + { + SA_DBG3(("mpiParseOBIomb, mpiSSPAbortRsp FAIL IOMB=%p\n", pMsg1)); + } + + break; + } + case OPC_OUB_SATA_ABORT_RSP: + { +#ifdef SALL_API_TEST + saRoot->LLCounters.IOCounter.numSataAbortedCB++; +#else + SA_DBG3(("mpiParseOBIomb, SATA_ABORT Response received IOMB=%p\n", pMsg1)); +#endif + /* process the response message */ + mpiSATAAbortRsp(agRoot, (agsaSATAAbortRsp_t *)pMsg1); + break; + } + case OPC_OUB_SATA_EVENT: + { + SA_DBG3(("mpiParseOBIomb, SATA_EVENT Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiSATAEvent(agRoot, (agsaSATAEventRsp_t *)pMsg1); + break; + } + case OPC_OUB_SSP_EVENT: + { + SA_DBG3(("mpiParseOBIomb, SSP_EVENT Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiSSPEvent(agRoot, (agsaSSPEventRsp_t *)pMsg1); + break; + } + case OPC_OUB_SMP_COMP: + { +#ifdef SALL_API_TEST + saRoot->LLCounters.IOCounter.numSMPCompleted++; + SA_DBG3(("mpiParseOBIomb, SMP_COMP Response received IOMB=%p, %d\n", + pMsg1, saRoot->LLCounters.IOCounter.numSMPCompleted)); +#else + SA_DBG3(("mpiParseOBIomb, SMP_COMP Response received IOMB=%p\n", pMsg1)); +#endif + /* process the response message */ + mpiSMPCompletion(agRoot, (agsaSMPCompletionRsp_t *)pMsg1); + break; + } + case OPC_OUB_ECHO: + { +#ifdef SALL_API_TEST + saRoot->LLCounters.IOCounter.numEchoCB++; + SA_DBG3(("mpiParseOBIomb, ECHO Response received %d\n", saRoot->LLCounters.IOCounter.numEchoCB)); +#else + SA_DBG3(("mpiParseOBIomb, ECHO Response received\n")); +#endif + /* process the response message */ + mpiEchoRsp(agRoot, (agsaEchoRsp_t *)pMsg1); + break; + } + case OPC_OUB_GET_NVMD_DATA: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_GET_NVMD_DATA received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiGetNVMDataRsp(agRoot, (agsaGetNVMDataRsp_t *)pMsg1); + break; + } + case OPC_OUB_SPC_HW_EVENT: + { + SA_ASSERT((smIS_SPC(agRoot)), "smIS_SPC"); + SA_DBG3(("mpiParseOBIomb, OPC_OUB_SPC_HW_EVENT Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiHWevent(agRoot, (agsaHWEvent_SPC_OUB_t *)pMsg1); + break; + } + case OPC_OUB_HW_EVENT: + { + SA_DBG3(("mpiParseOBIomb, HW_EVENT Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiHWevent(agRoot, (agsaHWEvent_SPC_OUB_t *)pMsg1); + break; + } + case OPC_OUB_PHY_START_RESPONSE: + { + SA_DBG1(("mpiParseOBIomb, OPC_OUB_PHY_START_RESPONSE Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiPhyStartEvent( agRoot, (agsaHWEvent_Phy_OUB_t *)pMsg1 ); + + break; + } + case OPC_OUB_PHY_STOP_RESPONSE: + { + SA_DBG1(("mpiParseOBIomb, OPC_OUB_PHY_STOP_RESPONSE Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiPhyStopEvent( agRoot, (agsaHWEvent_Phy_OUB_t *)pMsg1 ); + break; + } + + case OPC_OUB_LOCAL_PHY_CNTRL: + { + SA_DBG3(("mpiParseOBIomb, PHY CONTROL Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiPhyCntrlRsp(agRoot, (agsaLocalPhyCntrlRsp_t *)pMsg1); + break; + } + case OPC_OUB_SPC_DEV_REGIST: + { + SA_ASSERT((smIS_SPC(agRoot)), "smIS_SPC"); + SA_DBG3(("mpiParseOBIomb, OPC_OUB_SPC_DEV_REGIST Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiDeviceRegRsp(agRoot, (agsaDeviceRegistrationRsp_t *)pMsg1); + break; + } + case OPC_OUB_DEV_REGIST: + { + SA_DBG2(("mpiParseOBIomb, DEV_REGISTRATION Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiDeviceRegRsp(agRoot, (agsaDeviceRegistrationRsp_t *)pMsg1); + break; + } + case OPC_OUB_DEREG_DEV: + { + SA_DBG3(("mpiParseOBIomb, DEREGISTRATION DEVICE Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiDeregDevHandleRsp(agRoot, (agsaDeregDevHandleRsp_t *)pMsg1); + break; + } + case OPC_OUB_GET_DEV_HANDLE: + { + SA_DBG3(("mpiParseOBIomb, GET_DEV_HANDLE Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiGetDevHandleRsp(agRoot, (agsaGetDevHandleRsp_t *)pMsg1); + break; + } + case OPC_OUB_SPC_DEV_HANDLE_ARRIV: + { + SA_DBG3(("mpiParseOBIomb, SPC_DEV_HANDLE_ARRIV Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiDeviceHandleArrived(agRoot, (agsaDeviceHandleArrivedNotify_t *)pMsg1); + break; + } + case OPC_OUB_DEV_HANDLE_ARRIV: + { + SA_DBG3(("mpiParseOBIomb, DEV_HANDLE_ARRIV Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiDeviceHandleArrived(agRoot, (agsaDeviceHandleArrivedNotify_t *)pMsg1); + break; + } + case OPC_OUB_SSP_RECV_EVENT: + { + SA_DBG3(("mpiParseOBIomb, SSP_RECV_EVENT Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiSSPReqReceivedNotify(agRoot, (agsaSSPReqReceivedNotify_t *)pMsg1); + break; + } + case OPC_OUB_DEV_INFO: + { + SA_ASSERT((smIS_SPCV(agRoot)), "smIS_SPCV"); + SA_DBG3(("mpiParseOBIomb, DEV_INFO Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiGetDevInfoRsp(agRoot, (agsaGetDevInfoRspV_t *)pMsg1); + break; + } + case OPC_OUB_GET_PHY_PROFILE_RSP: + { + SA_ASSERT((smIS_SPCV(agRoot)), "smIS_SPCV"); + SA_DBG2(("mpiParseOBIomb, OPC_OUB_GET_PHY_PROFILE_RSP Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiGetPhyProfileRsp(agRoot, (agsaGetPhyProfileRspV_t *)pMsg1); + break; + } + case OPC_OUB_SET_PHY_PROFILE_RSP: + { + SA_ASSERT((smIS_SPCV(agRoot)), "smIS_SPCV"); + SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_PHY_PROFILE_RSP Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiSetPhyProfileRsp(agRoot, (agsaSetPhyProfileRspV_t *)pMsg1); + break; + } + case OPC_OUB_SPC_DEV_INFO: + { + SA_ASSERT((smIS_SPC(agRoot)), "smIS_SPC"); + SA_DBG3(("mpiParseOBIomb, DEV_INFO Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiGetDevInfoRspSpc(agRoot, (agsaGetDevInfoRsp_t *)pMsg1); + break; + } + case OPC_OUB_FW_FLASH_UPDATE: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_FW_FLASH_UPDATE Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiFwFlashUpdateRsp(agRoot, (agsaFwFlashUpdateRsp_t *)pMsg1); + break; + } + case OPC_OUB_FLASH_OP_EXT_RSP: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_FLASH_OP_EXT_RSP Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiFwExtFlashUpdateRsp(agRoot, (agsaFwFlashOpExtRsp_t *)pMsg1); + break; + } +#ifdef SPC_ENABLE_PROFILE + case OPC_OUB_FW_PROFILE: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_FW_PROFILE Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiFwProfileRsp(agRoot, (agsaFwProfileRsp_t *)pMsg1); + break; + } +#endif + case OPC_OUB_SET_NVMD_DATA: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_NVMD_DATA received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiSetNVMDataRsp(agRoot, (agsaSetNVMDataRsp_t *)pMsg1); + break; + } + case OPC_OUB_GPIO_RESPONSE: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_GPIO_RESPONSE Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiGPIORsp(agRoot, (agsaGPIORsp_t *)pMsg1); + break; + } + case OPC_OUB_GPIO_EVENT: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_GPIO_RESPONSE Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiGPIOEventRsp(agRoot, (agsaGPIOEvent_t *)pMsg1); + break; + } + case OPC_OUB_GENERAL_EVENT: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_GENERAL_EVENT Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiGeneralEventRsp(agRoot, (agsaGeneralEventRsp_t *)pMsg1); + break; + } + case OPC_OUB_SAS_DIAG_MODE_START_END: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_SAS_DIAG_MODE_START_END Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiSASDiagStartEndRsp(agRoot, (agsaSASDiagStartEndRsp_t *)pMsg1); + break; + } + case OPC_OUB_SAS_DIAG_EXECUTE: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_SAS_DIAG_EXECUTE_RSP Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiSASDiagExecuteRsp(agRoot, (agsaSASDiagExecuteRsp_t *)pMsg1); + break; + } + case OPC_OUB_GET_TIME_STAMP: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_GET_TIME_STAMP Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiGetTimeStampRsp(agRoot, (agsaGetTimeStampRsp_t *)pMsg1); + break; + } + + case OPC_OUB_SPC_SAS_HW_EVENT_ACK: + { + SA_ASSERT((smIS_SPC(agRoot)), "smIS_SPC"); + SA_DBG3(("mpiParseOBIomb,OPC_OUB_SPC_SAS_HW_EVENT_ACK Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiSASHwEventAckRsp(agRoot, (agsaSASHwEventAckRsp_t *)pMsg1); + break; + } + + case OPC_OUB_SAS_HW_EVENT_ACK: + { + SA_ASSERT((smIS_SPCV(agRoot)), "smIS_SPCV"); + SA_DBG1(("mpiParseOBIomb, OPC_OUB_SAS_HW_EVENT_ACK Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiSASHwEventAckRsp(agRoot, (agsaSASHwEventAckRsp_t *)pMsg1); + break; + } + case OPC_OUB_PORT_CONTROL: + { + SA_DBG1(("mpiParseOBIomb, OPC_OUB_PORT_CONTROL Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiPortControlRsp(agRoot, (agsaPortControlRsp_t *)pMsg1); + break; + } + case OPC_OUB_SMP_ABORT_RSP: + { +#ifdef SALL_API_TEST + saRoot->LLCounters.IOCounter.numSMPAbortedCB++; + SA_DBG3(("mpiParseOBIomb, SMP_ABORT Response received IOMB=%p, %d\n", + pMsg1, saRoot->LLCounters.IOCounter.numSMPAbortedCB)); +#else + SA_DBG3(("mpiParseOBIomb, OPC_OUB_SMP_ABORT_RSP Response received IOMB=%p\n", pMsg1)); +#endif + /* process the response message */ + mpiSMPAbortRsp(agRoot, (agsaSMPAbortRsp_t *)pMsg1); + break; + } + case OPC_OUB_DEVICE_HANDLE_REMOVAL: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_DEVICE_HANDLE_REMOVAL received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiDeviceHandleRemoval(agRoot, (agsaDeviceHandleRemoval_t *)pMsg1); + break; + } + case OPC_OUB_SET_DEVICE_STATE: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_DEVICE_STATE received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiSetDeviceStateRsp(agRoot, (agsaSetDeviceStateRsp_t *)pMsg1); + break; + } + case OPC_OUB_GET_DEVICE_STATE: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_GET_DEVICE_STATE received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiGetDeviceStateRsp(agRoot, (agsaGetDeviceStateRsp_t *)pMsg1); + break; + } + case OPC_OUB_SET_DEV_INFO: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_DEV_INFO received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiSetDevInfoRsp(agRoot, (agsaSetDeviceInfoRsp_t *)pMsg1); + break; + } + case OPC_OUB_SAS_RE_INITIALIZE: + { + SA_ASSERT((smIS_SPC(agRoot)), "smIS_SPC"); + SA_DBG3(("mpiParseOBIomb, OPC_OUB_SAS_RE_INITIALIZE received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiSasReInitializeRsp(agRoot, (agsaSasReInitializeRsp_t *)pMsg1); + break; + } + + case OPC_OUB_SGPIO_RESPONSE: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_SGPIO_RESPONSE Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiSGpioRsp(agRoot, (agsaSGpioRsp_t *)pMsg1); + break; + } + + case OPC_OUB_PCIE_DIAG_EXECUTE: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_PCIE_DIAG_EXECUTE Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiPCIeDiagExecuteRsp(agRoot, (agsaPCIeDiagExecuteRsp_t *)pMsg1); + break; + } + + case OPC_OUB_GET_VIST_CAP_RSP: + { + SA_DBG3(("mpiParseOBIomb, OPC_INB_GET_VIST_CAP Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiGetVHistRsp(agRoot, (agsaGetVHistCapRsp_t *)pMsg1); + break; + } + case 2104: + { + if(smIS_SPC6V(agRoot)) + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_GET_DFE_DATA_RSP Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiGetDFEDataRsp(agRoot, (agsaGetDDEFDataRsp_t *)pMsg1); + } + if(smIS_SPC12V(agRoot)) + { + SA_DBG3(("mpiParseOBIomb, OPC_INB_GET_VIST_CAP Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiGetVHistRsp(agRoot, (agsaGetVHistCapRsp_t *)pMsg1); + } + else + { + SA_DBG1(("mpiParseOBIomb, 2104 Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + } + break; + } + case OPC_OUB_SET_CONTROLLER_CONFIG: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_CONTROLLER_CONFIG Response received IOMB=%p\n", pMsg1)); + mpiSetControllerConfigRsp(agRoot, (agsaSetControllerConfigRsp_t *)pMsg1); + break; + } + case OPC_OUB_GET_CONTROLLER_CONFIG: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_GET_CONTROLLER_CONFIG Response received IOMB=%p\n", pMsg1)); + mpiGetControllerConfigRsp(agRoot, (agsaGetControllerConfigRsp_t *)pMsg1); + break; + } + case OPC_OUB_KEK_MANAGEMENT: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_KEK_MANAGEMENT Response received IOMB=%p\n", pMsg1)); + mpiKekManagementRsp(agRoot, (agsaKekManagementRsp_t *)pMsg1); + break; + } + case OPC_OUB_DEK_MANAGEMENT: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_DEK_MANAGEMENT Response received IOMB=%p\n", pMsg1)); + mpiDekManagementRsp(agRoot, (agsaDekManagementRsp_t *)pMsg1); + break; + } + case OPC_OUB_OPR_MGMT: + { + SA_DBG1(("mpiParseOBIomb, OPC_OUB_OPR_MGMT Response received IOMB=%p\n", pMsg1)); + mpiOperatorManagementRsp(agRoot, (agsaOperatorMangmenRsp_t *)pMsg1); + break; + } + case OPC_OUB_ENC_TEST_EXECUTE: + { + SA_DBG1(("mpiParseOBIomb, OPC_OUB_ENC_TEST_EXECUTE Response received IOMB=%p\n", pMsg1)); + mpiBistRsp(agRoot, (agsaEncryptBistRsp_t *)pMsg1); + break; + } + case OPC_OUB_SET_OPERATOR: + { + SA_DBG1(("mpiParseOBIomb, OPC_OUB_SET_OPERATOR Response received IOMB=%p\n", pMsg1)); + mpiSetOperatorRsp(agRoot, (agsaSetOperatorRsp_t *)pMsg1); + break; + } + case OPC_OUB_GET_OPERATOR: + { + SA_DBG1(("mpiParseOBIomb, OPC_OUB_GET_OPERATOR Response received IOMB=%p\n", pMsg1)); + mpiGetOperatorRsp(agRoot, (agsaGetOperatorRsp_t *)pMsg1); + break; + } + case OPC_OUB_DIF_ENC_OFFLOAD_RSP: + { + SA_ASSERT((smIS_SPCV(agRoot)), "smIS_SPCV"); + SA_DBG1(("mpiParseOBIomb, OPC_OUB_DIF_ENC_OFFLOAD_RSP Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiDifEncOffloadRsp(agRoot, (agsaDifEncOffloadRspV_t *)pMsg1); + break; + } + default: + { +#ifdef SALL_API_TEST + saRoot->LLCounters.IOCounter.numUNKNWRespIOMB++; + SA_DBG1(("mpiParseOBIomb, UnKnown Response received IOMB=%p, %d\n", + pMsg1, saRoot->LLCounters.IOCounter.numUNKNWRespIOMB)); +#else + SA_DBG1(("mpiParseOBIomb, Unknown IOMB Response received opcode 0x%X IOMB=%p\n",opcode, pMsg1)); +#endif + break; + } + } /* switch */ + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2f"); + + return ret; + +} + + +/******************************************************************************/ +/*! \brief SPC MPI SATA Completion + * + * This function handles the SATA completion. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb1 Pointer of Message1 + * \param bc buffer count + * + * \return The read value + * + */ +/*******************************************************************************/ +GLOBAL FORCEINLINE +bit32 mpiSATACompletion( + agsaRoot_t *agRoot, + bit32 *pIomb1 + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + bit32 status; + bit32 tag; + bit32 param; + agsaIORequestDesc_t *pRequest; + bit32 *agFirstDword; + bit32 *pResp; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2s"); + + OSSA_READ_LE_32(AGROOT, &tag, pIomb1, OSSA_OFFSET_OF(agsaSATACompletionRsp_t, tag)) ; + OSSA_READ_LE_32(AGROOT, &status, pIomb1, OSSA_OFFSET_OF(agsaSATACompletionRsp_t, status)) ; + OSSA_READ_LE_32(AGROOT, ¶m, pIomb1, OSSA_OFFSET_OF(agsaSATACompletionRsp_t, param)) ; + + SA_DBG3(("mpiSATACompletion: start, HTAG=0x%x\n", tag)); + + /* get IOrequest from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + SA_ASSERT((pRequest), "pRequest"); + + if(agNULL == pRequest) + { + SA_DBG1(("mpiSATACompletion: agNULL == pRequest tag 0x%X status 0x%X\n",tag, status )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2s"); + return AGSA_RC_FAILURE; + } + + SA_ASSERT((pRequest->valid), "pRequest->valid"); + if(!pRequest->valid) + { + SA_DBG1(("mpiSATACompletion: not valid IOMB tag=0x%x status=0x%x param=0x%x Device =0x%x\n", tag, status, param, + pRequest->pDevice ? pRequest->pDevice->DeviceMapIndex : -1)); + } + + switch (status) + { + case OSSA_IO_SUCCESS: + { + SA_DBG3(("mpiSATACompletion: OSSA_IO_SUCCESS, param=0x%x\n", param)); + if (!param) + { + /* SATA request completion */ + siIODone( agRoot, pRequest, OSSA_IO_SUCCESS, 0); + } + else + { + /* param number bytes of SATA Rsp */ + agFirstDword = &pIomb1[3]; + pResp = &pIomb1[4]; + + /* CB function to the up layer */ + /* Response Length not include firstDW */ + saRoot->IoErrorCount.agOSSA_IO_COMPLETED_ERROR_SCSI_STATUS++; + SA_DBG2(("mpiSATACompletion: param 0x%x agFirstDwordResp 0x%x Resp 0x%x tag 0x%x\n",param,*agFirstDword,*pResp ,tag)); + siEventSATAResponseWtDataRcvd(agRoot, pRequest, agFirstDword, pResp, (param - 4)); + } + + break; + } + case OSSA_IO_ABORTED: + { + SA_DBG2(("mpiSATACompletion: OSSA_IO_ABORTED tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_ABORTED++; + siAbnormal(agRoot, pRequest, status, param, 0); + break; + } + case OSSA_IO_UNDERFLOW: + { + /* SATA Completion with error */ + SA_DBG1(("mpiSATACompletion, OSSA_IO_UNDERFLOW tag 0x%X\n", tag)); + /*underflow means underrun, treat it as success*/ + saRoot->IoErrorCount.agOSSA_IO_UNDERFLOW++; + siAbnormal(agRoot, pRequest, status, param, 0); + break; + } + case OSSA_IO_NO_DEVICE: + { + SA_DBG1(("mpiSATACompletion, OSSA_IO_NO_DEVICE tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_NO_DEVICE++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + case OSSA_IO_XFER_ERROR_BREAK: + { + SA_DBG1(("mpiSATACompletion, OSSA_IO_XFER_ERROR_BREAK SPC tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_BREAK++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + case OSSA_IO_XFER_ERROR_PHY_NOT_READY: + { + SA_DBG1(("mpiSATACompletion, OSSA_IO_XFER_ERROR_PHY_NOT_READY tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_PHY_NOT_READY++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: + { + SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION: + { + SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_BREAK: + { + SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_BREAK SPC tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_BREAK++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: + { + SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION: + { + SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: + { + SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: + { + SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION: + { + SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + case OSSA_IO_XFER_ERROR_NAK_RECEIVED: + { + SA_DBG1(("mpiSATACompletion, OSSA_IO_XFER_ERROR_NAK_RECEIVED tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_NAK_RECEIVED++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + case OSSA_IO_XFER_ERROR_DMA: + { + SA_DBG1(("mpiSATACompletion, OSSA_IO_XFER_ERROR_DMA tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_DMA++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + case OSSA_IO_XFER_ERROR_SATA_LINK_TIMEOUT: + { + SA_DBG1(("mpiSATACompletion, OSSA_IO_XFER_ERROR_SATA_LINK_TIMEOUT tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_SATA_LINK_TIMEOUT++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + case OSSA_IO_XFER_ERROR_REJECTED_NCQ_MODE: + { + SA_DBG1(("mpiSATACompletion, OSSA_IO_XFER_ERROR_REJECTED_NCQ_MODE tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_REJECTED_NCQ_MODE++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + case OSSA_IO_XFER_OPEN_RETRY_TIMEOUT: + { + SA_DBG1(("mpiSATACompletion, OSSA_IO_XFER_OPEN_RETRY_TIMEOUT tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_XFER_OPEN_RETRY_TIMEOUT++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + case OSSA_IO_PORT_IN_RESET: + { + SA_DBG1(("mpiSATACompletion: OSSA_IO_PORT_IN_RESET tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_PORT_IN_RESET++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + case OSSA_IO_DS_NON_OPERATIONAL: + { + SA_DBG1(("mpiSATACompletion: OSSA_IO_DS_NON_OPERATIONAL tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_DS_NON_OPERATIONAL++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + case OSSA_IO_DS_IN_RECOVERY: + { + SA_DBG1(("mpiSATACompletion: OSSA_IO_DS_IN_RECOVERY tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_DS_IN_RECOVERY++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + case OSSA_IO_DS_IN_ERROR: + { + SA_DBG1(("mpiSATACompletion: OSSA_IO_DS_IN_ERROR tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_DS_IN_ERROR++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + + case OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: + { + SA_DBG1(("mpiSATACompletion: OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + case OSSA_IO_ABORT_IN_PROGRESS: + { + SA_DBG1(("mpiSATACompletion: OSSA_IO_ABORT_IN_PROGRESS tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_ABORT_IN_PROGRESS++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + case OSSA_IO_ABORT_DELAYED: + { + SA_DBG1(("mpiSATACompletion: OSSA_IO_ABORT_DELAYED tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_ABORT_DELAYED++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT: + { + SA_DBG1(("mpiSATACompletion: OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: + { + SA_DBG1(("mpiSATACompletion: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED HTAG = 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: + { + SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO tag 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO++; + siAbnormal(agRoot, pRequest, status, 0, 0 ); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: + { + SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST tag 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST++; + siAbnormal(agRoot, pRequest, status, 0, 0 ); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: + { + SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE tag 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE++; + siAbnormal(agRoot, pRequest, status, 0, 0 ); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: + { + SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED tag 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED++; + siAbnormal(agRoot, pRequest, status, 0, 0 ); + break; + } + case OSSA_IO_DS_INVALID: + { + SA_DBG1(("mpiSATACompletion: OSSA_IO_DS_INVALID tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_DS_INVALID++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + case OSSA_IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR: + { + SA_DBG1(("mpiSATACompletion: OSSA_IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + case OSSA_MPI_IO_RQE_BUSY_FULL: + { + SA_DBG1(("mpiSATACompletion: OSSA_MPI_IO_RQE_BUSY_FULL tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_MPI_IO_RQE_BUSY_FULL++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } +#ifdef REMOVED + case OSSA_IO_XFER_ERR_EOB_DATA_OVERRUN: + { + SA_DBG1(("mpiSATACompletion: OSSA_IO_XFER_ERR_EOB_DATA_OVERRUN tag 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_XFER_ERR_EOB_DATA_OVERRUN++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } +#endif + case OSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE: + { + SA_DBG1(("mpiSATACompletion: OPC_OUB_SATA_COMP:OSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE \n")); + saRoot->IoErrorCount.agOSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + case OSSA_MPI_ERR_ATAPI_DEVICE_BUSY: + { + SA_DBG1(("mpiSATACompletion: OSSA_MPI_ERR_ATAPI_DEVICE_BUSY tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_MPI_ERR_ATAPI_DEVICE_BUSY++; + siAbnormal(agRoot, pRequest, status, param, 0 ); + break; + } + case OSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS: + { + SA_DBG1(("mpiSATACompletion: OSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + case OSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID: + { + SA_DBG1(("mpiSATACompletion: OSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + case OSSA_IO_XFR_ERROR_DEK_IV_MISMATCH: + { + SA_DBG1(("mpiSATACompletion: OSSA_IO_XFR_ERROR_DEK_IV_MISMATCH tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_IV_MISMATCH++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + case OSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR: + { + SA_DBG1(("mpiSATACompletion: OSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED: + { + SA_DBG1(("mpiSATACompletion: OSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + + case OSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH: + { + SA_DBG1(("mpiSATACompletion: OSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + case OSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS: + { + SA_DBG1(("mpiSATACompletion: OSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + case OSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE: + { + SA_DBG1(("mpiSATACompletion: OSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE tag 0x%X\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + } + + default: + { + SA_DBG1(("mpiSATACompletion: Unknown status 0x%x tag 0x%x\n", status, tag)); + saRoot->IoErrorCount.agOSSA_IO_UNKNOWN_ERROR++; + siAbnormal(agRoot, pRequest, status, param, 0); + break; + } + } + + /* The HTag should equal to the IOMB tag */ + if (pRequest->HTag != tag) + { + SA_DBG1(("mpiSATACompletion: Error Htag %d not equal IOMBtag %d\n", pRequest->HTag, tag)); + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2s"); + return ret; +} + +/******************************************************************************/ +/*! \brief SPC MPI SSP Completion + * + * This function handles the SSP completion. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb1 Pointer of Message1 + * \param bc buffer count + * + * \return The read value + * + */ +/*******************************************************************************/ +GLOBAL FORCEINLINE +bit32 mpiSSPCompletion( + agsaRoot_t *agRoot, + bit32 *pIomb1 + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaSSPCompletionRsp_t *pIomb = (agsaSSPCompletionRsp_t *)pIomb1; + agsaIORequestDesc_t *pRequest = agNULL; + agsaSSPResponseInfoUnit_t *pRespIU = agNULL; + bit32 tag = 0; + bit32 sspTag = 0; + bit32 status, param = 0; + bit32 ret = AGSA_RC_SUCCESS; + + smTraceFuncEnter(hpDBG_VERY_LOUD, "5A"); + + /* get Tag */ + OSSA_READ_LE_32(agRoot, &tag, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionRsp_t, tag)); + OSSA_READ_LE_32(agRoot, &status, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionRsp_t, status)); + OSSA_READ_LE_32(agRoot, ¶m, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionRsp_t, param)); + OSSA_READ_LE_32(agRoot, &sspTag, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionRsp_t, SSPTag)); + /* get SSP_START IOrequest from IOMap */ + pRequest = (agsaIORequestDesc_t *)saRoot->IOMap[tag].IORequest; + SA_ASSERT((pRequest), "pRequest"); + + if(pRequest == agNULL) + { + SA_DBG1(("mpiSSPCompletion,AGSA_RC_FAILURE SSP Resp IOMB tag=0x%x, status=0x%x, param=0x%x, SSPTag=0x%x\n", tag, status, param, sspTag)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5A"); + return(AGSA_RC_FAILURE); + } + SA_ASSERT((pRequest->valid), "pRequest->valid"); + + if(!pRequest->valid) + { + SA_DBG1(("mpiSSPCompletion, SSP Resp IOMB tag=0x%x, status=0x%x, param=0x%x, SSPTag=0x%x Device =0x%x\n", tag, status, param, sspTag, + pRequest->pDevice ? pRequest->pDevice->DeviceMapIndex : -1)); + } + + switch (status) + { + case OSSA_IO_SUCCESS: + { + if (!param) + { + /* Completion of SSP without Response Data */ + siIODone( agRoot, pRequest, OSSA_IO_SUCCESS, sspTag); + } + else + { + /* Get SSP Response with Response Data */ + pRespIU = (agsaSSPResponseInfoUnit_t *)&(pIomb->SSPrsp); + if (pRespIU->status == 0x02 || pRespIU->status == 0x18 || + pRespIU->status == 0x30 || pRespIU->status == 0x40 ) + { + /* SCSI status is CHECK_CONDITION, RESV_CONFLICT, ACA_ACTIVE, TASK_ABORTED */ + saRoot->IoErrorCount.agOSSA_IO_COMPLETED_ERROR_SCSI_STATUS++; + SA_DBG2(("mpiSSPCompletion: pRespIU->status 0x%x tag 0x%x\n", pRespIU->status,tag)); + } + siEventSSPResponseWtDataRcvd(agRoot, pRequest, pRespIU, param, sspTag); + } + + break; + } + + case OSSA_IO_XFR_ERROR_INVALID_SSP_RSP_FRAME: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_INVALID_SSP_RSP_FRAME tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_INVALID_SSP_RSP_FRAME++; + /* Get SSP Response with Response Data */ + pRespIU = (agsaSSPResponseInfoUnit_t *)&(pIomb->SSPrsp); + if (pRespIU->status == 0x02 || pRespIU->status == 0x18 || + pRespIU->status == 0x30 || pRespIU->status == 0x40 ) + { + /* SCSI status is CHECK_CONDITION, RESV_CONFLICT, ACA_ACTIVE, TASK_ABORTED */ + saRoot->IoErrorCount.agOSSA_IO_COMPLETED_ERROR_SCSI_STATUS++; + SA_DBG2(("mpiSSPCompletion: pRespIU->status 0x%x tag 0x%x\n", pRespIU->status,tag)); + } + siEventSSPResponseWtDataRcvd(agRoot, pRequest, pRespIU, param, sspTag); + + break; + } + + case OSSA_IO_ABORTED: + { +#ifdef SALL_API_TEST + saRoot->LLCounters.IOCounter.numSSPAborted++; + SA_DBG3(("mpiSSPCompletion, OSSA_IO_ABORTED Response received IOMB=%p %d\n", + pIomb1, saRoot->LLCounters.IOCounter.numSSPAborted)); +#endif + SA_DBG2(("mpiSSPCompletion, OSSA_IO_ABORTED IOMB tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_ABORTED++; + /* SSP Abort CB */ + siAbnormal(agRoot, pRequest, status, param, sspTag); + break; + } + case OSSA_IO_UNDERFLOW: + { + /* SSP Completion with error */ + SA_DBG2(("mpiSSPCompletion, OSSA_IO_UNDERFLOW tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + /*saRoot->IoErrorCount.agOSSA_IO_UNDERFLOW++;*/ + siAbnormal(agRoot, pRequest, status, param, sspTag); + break; + } + case OSSA_IO_NO_DEVICE: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_NO_DEVICE tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_NO_DEVICE++; + siAbnormal(agRoot, pRequest, status, 0, sspTag); + break; + } + case OSSA_IO_XFER_ERROR_BREAK: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERROR_BREAK tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_BREAK++; + siAbnormal(agRoot, pRequest, status, 0, sspTag); + break; + } + case OSSA_IO_XFER_ERROR_PHY_NOT_READY: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERROR_PHY_NOT_READY tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_PHY_NOT_READY++; + siAbnormal(agRoot, pRequest, status, 0, sspTag); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED++; + siAbnormal(agRoot, pRequest, status, 0, sspTag); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION: + { + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION++; + siAbnormal(agRoot, pRequest, status, 0, sspTag); + SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_BREAK: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_BREAK tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_BREAK++; + siAbnormal(agRoot, pRequest, status, 0, sspTag); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS++; + siAbnormal(agRoot, pRequest, status, 0, sspTag); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION++; + siAbnormal(agRoot, pRequest, status, 0, sspTag); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED++; + siAbnormal(agRoot, pRequest, status, 0, sspTag); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION++; + siAbnormal(agRoot, pRequest, status, 0, sspTag); + break; + } + case OSSA_IO_XFER_ERROR_NAK_RECEIVED: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERROR_NAK_RECEIVED tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_NAK_RECEIVED++; + siAbnormal(agRoot, pRequest, status, 0, sspTag); + break; + } + case OSSA_IO_XFER_ERROR_ACK_NAK_TIMEOUT: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERROR_ACK_NAK_TIMEOUT tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_ACK_NAK_TIMEOUT++; + siAbnormal(agRoot, pRequest, status, 0, sspTag); + break; + } + case OSSA_IO_XFER_ERROR_DMA: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERROR_DMA tag 0x%x ssptag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_DMA++; + siAbnormal(agRoot, pRequest, status, 0, sspTag); + break; + } + case OSSA_IO_XFER_OPEN_RETRY_TIMEOUT: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_OPEN_RETRY_TIMEOUT tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_XFER_OPEN_RETRY_TIMEOUT++; + siAbnormal(agRoot, pRequest, status, 0, sspTag); + break; + } + case OSSA_IO_XFER_ERROR_UNEXPECTED_PHASE: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERROR_UNEXPECTED_PHASE tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_UNEXPECTED_PHASE++; + siAbnormal(agRoot, pRequest, status, 0, sspTag); + break; + } + case OSSA_IO_XFER_ERROR_OFFSET_MISMATCH: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERROR_OFFSET_MISMATCH tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_OFFSET_MISMATCH++; + siAbnormal(agRoot, pRequest, status, 0, sspTag); + break; + } + case OSSA_IO_PORT_IN_RESET: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_PORT_IN_RESET tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_PORT_IN_RESET++; + siAbnormal(agRoot, pRequest, status, 0, sspTag); + break; + } + case OSSA_IO_DS_NON_OPERATIONAL: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_DS_NON_OPERATIONAL tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_DS_NON_OPERATIONAL++; + siAbnormal(agRoot, pRequest, status, 0, sspTag); + break; + } + case OSSA_IO_DS_IN_RECOVERY: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_DS_IN_RECOVERY tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_DS_IN_RECOVERY++; + siAbnormal(agRoot, pRequest, status, 0, sspTag); + break; + } + case OSSA_IO_TM_TAG_NOT_FOUND: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_TM_TAG_NOT_FOUND tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_TM_TAG_NOT_FOUND++; + siAbnormal(agRoot, pRequest, status, 0, sspTag); + break; + } + case OSSA_IO_XFER_PIO_SETUP_ERROR: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_PIO_SETUP_ERROR tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_XFER_PIO_SETUP_ERROR++; + /* not allowed case. Therefore, return failed status */ + siAbnormal(agRoot, pRequest, OSSA_IO_FAILED, param, sspTag); + break; + } + case OSSA_IO_SSP_EXT_IU_ZERO_LEN_ERROR: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_SSP_IU_ZERO_LEN_ERROR tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_SSP_EXT_IU_ZERO_LEN_ERROR++; + siAbnormal(agRoot, pRequest, status, 0, sspTag); + break; + } + case OSSA_IO_DS_IN_ERROR: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_DS_IN_ERROR tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_DS_IN_ERROR++; + /* not allowed case. Therefore, return failed status */ + siAbnormal(agRoot, pRequest, OSSA_IO_FAILED, param, sspTag); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY++; + /* not allowed case. Therefore, return failed status */ + siAbnormal(agRoot, pRequest, OSSA_IO_FAILED, param, sspTag); + break; + } + case OSSA_IO_ABORT_IN_PROGRESS: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_ABORT_IN_PROGRESS tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_ABORT_IN_PROGRESS++; + /* not allowed case. Therefore, return failed status */ + siAbnormal(agRoot, pRequest, OSSA_IO_FAILED, param, sspTag); + break; + } + case OSSA_IO_ABORT_DELAYED: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_ABORT_DELAYED tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_ABORT_DELAYED++; + /* not allowed case. Therefore, return failed status */ + siAbnormal(agRoot, pRequest, OSSA_IO_FAILED, param, sspTag); + break; + } + case OSSA_IO_INVALID_LENGTH: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_INVALID_LENGTH tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_INVALID_LENGTH++; + /* not allowed case. Therefore, return failed status */ + siAbnormal(agRoot, pRequest, OSSA_IO_FAILED, param, sspTag); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT++; + /* not allowed case. Therefore, return failed status */ + siAbnormal(agRoot, pRequest, OSSA_IO_FAILED, param, sspTag); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED HTAG = 0x%x ssptag = 0x%x\n", tag, sspTag)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED++; + siAbnormal(agRoot, pRequest, status, 0, sspTag); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO++; + siAbnormal(agRoot, pRequest, status, param, sspTag); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST++; + siAbnormal(agRoot, pRequest, status, param, sspTag); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE++; + siAbnormal(agRoot, pRequest, status, param, sspTag); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED++; + siAbnormal(agRoot, pRequest, status, param, sspTag); + break; + } + case OSSA_IO_DS_INVALID: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_DS_INVALID tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_DS_INVALID++; + siAbnormal(agRoot, pRequest, status, param, sspTag); + break; + } + case OSSA_MPI_IO_RQE_BUSY_FULL: + { + SA_DBG1(("mpiSSPCompletion: OSSA_MPI_IO_RQE_BUSY_FULL tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_MPI_IO_RQE_BUSY_FULL++; + siAbnormal(agRoot, pRequest, status, param, sspTag); + break; + } + case OSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE: + { + SA_DBG1(("mpiSSPCompletion: OSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE++; + siAbnormal(agRoot, pRequest, status, param, sspTag); + break; + } + case OSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS++; + siAbnormal(agRoot, pRequest, status, param, sspTag); + break; + } + case OSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH++; + siAbnormal(agRoot, pRequest, status, param, sspTag); + break; + } + case OSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID++; + siAbnormal(agRoot, pRequest, status, param, sspTag); + break; + } + case OSSA_IO_XFR_ERROR_DEK_IV_MISMATCH: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DEK_IV_MISMATCH tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_IV_MISMATCH++; + siAbnormal(agRoot, pRequest, status, param, sspTag); + break; + } + case OSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR++; + siAbnormal(agRoot, pRequest, status, param, sspTag); + break; + } + case OSSA_IO_XFR_ERROR_INTERNAL_RAM: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_INTERNAL_RAM tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_INTERNAL_RAM++; + siAbnormal(agRoot, pRequest, status, param, sspTag); + break; + } + case OSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS++; + siAbnormal(agRoot, pRequest, status, param, sspTag); + break; + } + case OSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE++; + siAbnormal(agRoot, pRequest, status, param, sspTag); + break; + } +#ifdef SA_TESTBASE_EXTRA + /* TestBase */ + case OSSA_IO_HOST_BST_INVALID: + { + SA_DBG1(("mpiParseOBIomb, OPC_OUB_SSP_COMP: OSSA_IO_HOST_BST_INVALID 0x%x\n", status)); + siAbnormal(agRoot, pRequest, status, param, sspTag); + break; + } +#endif /* SA_TESTBASE_EXTRA */ + case OSSA_IO_XFR_ERROR_DIF_MISMATCH: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DIF_MISMATCH tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DIF_MISMATCH++; + siDifAbnormal(agRoot, pRequest, status, param, sspTag, pIomb1); + break; + } + case OSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH++; + siDifAbnormal(agRoot, pRequest, status, param, sspTag, pIomb1); + break; + } + case OSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH++; + siDifAbnormal(agRoot, pRequest, status, param, sspTag, pIomb1); + break; + } + case OSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH++; + siDifAbnormal(agRoot, pRequest, status, param, sspTag, pIomb1); + break; + } + case OSSA_IO_XFER_ERROR_DIF_INTERNAL_ERROR: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERROR_DIF_INTERNAL_ERROR tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_DIF_INTERNAL_ERROR++; + siDifAbnormal(agRoot, pRequest, status, param, sspTag, pIomb1); + break; + } + case OSSA_IO_XFER_ERR_EOB_DATA_OVERRUN: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERR_EOB_DATA_OVERRUN tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_XFER_ERR_EOB_DATA_OVERRUN++; + siAbnormal(agRoot, pRequest, status, param, sspTag); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED: + { + SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED++; + siAbnormal(agRoot, pRequest, status, param, sspTag); + break; + } + default: + { + SA_DBG1(("mpiSSPCompletion: Unknown tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); + /* not allowed case. Therefore, return failed status */ + saRoot->IoErrorCount.agOSSA_IO_UNKNOWN_ERROR++; + siAbnormal(agRoot, pRequest, OSSA_IO_FAILED, param, sspTag); + break; + } + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5A"); + return ret; +} diff --git a/sys/dev/pms/RefTisa/sallsdk/spc/saioctlcmd.c b/sys/dev/pms/RefTisa/sallsdk/spc/saioctlcmd.c new file mode 100644 index 000000000000..a577b1c694d9 --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/spc/saioctlcmd.c @@ -0,0 +1,4010 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +/*******************************************************************************/ +/*! \file saioctlcmd.c + * \brief The file implements the functions of IOCTL MPI Command/Response to/from SPC + * + */ +/******************************************************************************/ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#ifdef SA_ENABLE_TRACE_FUNCTIONS +#ifdef siTraceFileID +#undef siTraceFileID +#endif +#define siTraceFileID 'H' +#endif + +extern bit32 gFPGA_TEST; + +extern bit32 gWait_3; +extern bit32 gWait_2; + + + +LOCAL bit32 siGSMDump( + agsaRoot_t *agRoot, + bit32 gsmDumpOffset, + bit32 length, + void *directData); + +#ifdef SPC_ENABLE_PROFILE +/******************************************************************************/ +/*! \brief SPC FW Profile Command + * + * This command sends FW Flash Update Command to SPC. + * + * \param agRoot Handles for this instance of SAS/SATA LL + * \param agContext Context of SPC FW Flash Update Command + * \param queueNum Inbound/outbound queue number + * \param flashUpdateInfo Pointer of flash update information + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 saFwProfile( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaFwProfile_t *fwProfileInfo + ) +{ + bit32 ret = AGSA_RC_SUCCESS, retVal; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + mpiICQueue_t *circularQ; + void *pMessage; + agsaFwProfileIOMB_t *pPayload; + bit8 inq, outq; + bit32 i, tcid_processor_cmd = 0; + + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistGetHead(&(saRoot->freeIORequests)); + + /* If no LL Control request entry avaliable */ + if ( agNULL == pRequest ) + { + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saFwProfile, No request from free list\n" )); + return AGSA_RC_BUSY; + } + /* If LL Control request entry avaliable */ + else + { + /* Assign inbound and outbound Ring Buffer */ + inq = (bit8)(queueNum & MPI_IB_NUM_MASK); + outq = (bit8)((queueNum & MPI_OB_NUM_MASK) >> MPI_OB_SHIFT); + SA_ASSERT((AGSA_MAX_INBOUND_Q > inq), "The IBQ Number is out of range."); + + /* Remove the request from free list */ + saLlistRemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedEnter(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + /* Get a free inbound queue entry */ + circularQ = &saRoot->inboundQueue[inq]; + retVal = mpiMsgFreeGet(circularQ, IOMB_SIZE64, &pMessage); + + /* if message size is too large return failure */ + if (AGSA_RC_FAILURE == retVal) + { +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("saFwProfile, error when get free IOMB\n")); + return AGSA_RC_FAILURE; + } + + /* return busy if inbound queue is full */ + if (AGSA_RC_BUSY == retVal) + { +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saFwProfile, no more IOMB\n")); + return AGSA_RC_BUSY; + } + + pPayload = (agsaFwProfileIOMB_t *)pMessage; + tcid_processor_cmd = (((fwProfileInfo->tcid)<< 16) | ((fwProfileInfo->processor)<< 8) | fwProfileInfo->cmd); + /* Prepare the FW_FLASH_UPDATE IOMB payload */ + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaFwProfileIOMB_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaFwProfileIOMB_t, tcid_processor_cmd), tcid_processor_cmd); + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaFwProfileIOMB_t, codeStartAdd), fwProfileInfo->codeStartAdd); + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaFwProfileIOMB_t, codeEndAdd), fwProfileInfo->codeEndAdd); + + pPayload->SGLAL = fwProfileInfo->agSgl.sgLower; + pPayload->SGLAH = fwProfileInfo->agSgl.sgUpper; + pPayload->Len = fwProfileInfo->agSgl.len; + pPayload->extReserved = fwProfileInfo->agSgl.extReserved; + + /* fill up the reserved bytes with zero */ + for (i = 0; i < FWPROFILE_IOMB_RESERVED_LEN; i ++) + { + pPayload->reserved0[i] = 0; + } + + /* post the IOMB to SPC */ + ret = mpiMsgProduce(circularQ, (void *)pMessage, MPI_CATEGORY_SAS_SATA, OPC_INB_FW_PROFILE, outq, (bit8)circularQ->priority); + +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + + if (AGSA_RC_FAILURE == ret) + { + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saFwProfile, error when post FW_PROFILE IOMB\n")); + } + } + return ret; +} +#endif +/******************************************************************************/ +/*! \brief SPC FW Flash Update Command + * + * This command sends FW Flash Update Command to SPC. + * + * \param agRoot Handles for this instance of SAS/SATA LL + * \param agContext Context of SPC FW Flash Update Command + * \param queueNum Inbound/outbound queue number + * \param flashUpdateInfo Pointer of flash update information + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 saFwFlashUpdate( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaUpdateFwFlash_t *flashUpdateInfo + ) +{ + bit32 ret = AGSA_RC_SUCCESS, retVal; + agsaLLRoot_t *saRoot; + agsaIORequestDesc_t *pRequest; + mpiICQueue_t *circularQ; + void *pMessage; + agsaFwFlashUpdate_t *pPayload; + bit8 inq, outq; + bit32 i; + + SA_ASSERT((agNULL != agRoot), ""); + if (agRoot == agNULL) + { + SA_DBG1(("saFwFlashUpdate: agRoot == agNULL\n")); + return AGSA_RC_FAILURE; + } + saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + SA_ASSERT((agNULL != saRoot), ""); + if (saRoot == agNULL) + { + SA_DBG1(("saFwFlashUpdate: saRoot == agNULL\n")); + return AGSA_RC_FAILURE; + } + + + smTraceFuncEnter(hpDBG_VERY_LOUD, "6a"); + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) { + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saFwFlashUpdate, No request from free list\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "6a"); + return AGSA_RC_BUSY; + } + /* If LL Control request entry avaliable */ + else + { + /* Assign inbound and outbound Ring Buffer */ + inq = (bit8)(queueNum & MPI_IB_NUM_MASK); + outq = (bit8)((queueNum & MPI_OB_NUM_MASK) >> MPI_OB_SHIFT); + SA_ASSERT((AGSA_MAX_INBOUND_Q > inq), "The IBQ Number is out of range."); + /* Remove the request from free list */ + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedEnter(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + /* Get a free inbound queue entry */ + circularQ = &saRoot->inboundQueue[inq]; + retVal = mpiMsgFreeGet(circularQ, IOMB_SIZE64, &pMessage); + /* if message size is too large return failure */ + if (AGSA_RC_FAILURE == retVal) + { +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saFwFlashUpdate, error when get free IOMB\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "6a"); + return AGSA_RC_FAILURE; + } + /* return busy if inbound queue is full */ + if (AGSA_RC_BUSY == retVal) + { +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saFwFlashUpdate, no more IOMB\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "6a"); + return AGSA_RC_BUSY; + } + pPayload = (agsaFwFlashUpdate_t *)pMessage; + /* Prepare the FW_FLASH_UPDATE IOMB payload */ + OSSA_WRITE_LE_32( agRoot, pPayload, + OSSA_OFFSET_OF(agsaFwFlashUpdate_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32( agRoot, pPayload, + OSSA_OFFSET_OF(agsaFwFlashUpdate_t, curImageOffset), + flashUpdateInfo->currentImageOffset); + OSSA_WRITE_LE_32( agRoot, pPayload, + OSSA_OFFSET_OF(agsaFwFlashUpdate_t, curImageLen), + flashUpdateInfo->currentImageLen); + OSSA_WRITE_LE_32( agRoot, pPayload, + OSSA_OFFSET_OF(agsaFwFlashUpdate_t, totalImageLen), + flashUpdateInfo->totalImageLen); + pPayload->SGLAL = flashUpdateInfo->agSgl.sgLower; + pPayload->SGLAH = flashUpdateInfo->agSgl.sgUpper; + pPayload->Len = flashUpdateInfo->agSgl.len; + pPayload->extReserved = flashUpdateInfo->agSgl.extReserved; + /* fill up the reserved bytes with zero */ + for (i = 0; i < FWFLASH_IOMB_RESERVED_LEN; i ++) { + pPayload->reserved0[i] = 0; + } + /* post the IOMB to SPC */ + ret = mpiMsgProduce( circularQ, (void *)pMessage, MPI_CATEGORY_SAS_SATA, + OPC_INB_FW_FLASH_UPDATE, outq, (bit8)circularQ->priority); +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedLeave( agRoot, LL_IOREQ_IBQ0_LOCK + inq ); +#endif /* SA_LL_IBQ_PROTECT */ + if (AGSA_RC_FAILURE == ret) { + ossaSingleThreadedEnter( agRoot, LL_IOREQ_LOCKEQ_LOCK ); + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + /* return the request to free pool */ + saLlistIOAdd( &(saRoot->freeIORequests), &(pRequest->linkNode) ); + ossaSingleThreadedLeave( agRoot, LL_IOREQ_LOCKEQ_LOCK ); + SA_DBG1( ("saFwFlashUpdate, error when post FW_FLASH_UPDATE IOMB\n") ); + } + } + smTraceFuncExit( hpDBG_VERY_LOUD, 'd', "6a" ); + return ret; +} + + +GLOBAL bit32 saFlashExtExecute ( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaFlashExtExecute_t *agFlashExtExe) +{ + + bit32 ret = AGSA_RC_SUCCESS, retVal; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + mpiICQueue_t *circularQ; + void *pMessage; + agsaFwFlashOpExt_t *pPayload; + bit8 inq, outq; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2R"); + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saFlashExtExecute, No request from free list\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2R"); + return AGSA_RC_BUSY; + } + /* If LL Control request entry avaliable */ + else + { + /* Assign inbound and outbound Ring Buffer */ + inq = (bit8)(queueNum & MPI_IB_NUM_MASK); + outq = (bit8)((queueNum & MPI_OB_NUM_MASK) >> MPI_OB_SHIFT); + SA_ASSERT((AGSA_MAX_INBOUND_Q > inq), "The IBQ Number is out of range."); + + /* Remove the request from free list */ + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedEnter(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + /* Get a free inbound queue entry */ + circularQ = &saRoot->inboundQueue[inq]; + retVal = mpiMsgFreeGet(circularQ, IOMB_SIZE64, &pMessage); + + /* if message size is too large return failure */ + if (AGSA_RC_FAILURE == retVal) + { +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("saFlashExtExecute, error when get free IOMB\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2R"); + return AGSA_RC_FAILURE; + } + + /* return busy if inbound queue is full */ + if (AGSA_RC_BUSY == retVal) + { +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + + pRequest->valid = agFALSE; + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG3(("saFlashExtExecute, no more IOMB\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "2R"); + return AGSA_RC_BUSY; + } + + pPayload = (agsaFwFlashOpExt_t *)pMessage; + + si_memset(pPayload, 0, sizeof(agsaFwFlashOpExt_t)); + + + /* Prepare the FW_FLASH_UPDATE IOMB payload */ + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaFwFlashOpExt_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaFwFlashOpExt_t,Command ), agFlashExtExe->command); + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaFwFlashOpExt_t,PartOffset ), agFlashExtExe->partOffset); + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaFwFlashOpExt_t,DataLength ), agFlashExtExe->dataLen); + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaFwFlashOpExt_t,SGLAL ), agFlashExtExe->agSgl->sgLower); + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaFwFlashOpExt_t,SGLAH ), agFlashExtExe->agSgl->sgUpper); + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaFwFlashOpExt_t,Len ), agFlashExtExe->agSgl->len); + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaFwFlashOpExt_t,E_sgl ), agFlashExtExe->agSgl->extReserved); + + /* post the IOMB to SPC */ + ret = mpiMsgProduce(circularQ, (void *)pMessage, MPI_CATEGORY_SAS_SATA, OPC_INB_FLASH_OP_EXT, outq, (bit8)circularQ->priority); + +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + + + if (AGSA_RC_FAILURE == ret) + { + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saFlashExtExecute, error when post FW_FLASH_UPDATE IOMB\n")); + } + } + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "2R"); + + return ret; + +} + + +#ifdef SPC_ENABLE_PROFILE +/******************************************************************************/ +/*! \brief SPC FW_PROFILE Respond + * + * This command sends FW Profile Status to TD layer. + * + * \param agRoot Handles for this instance of SAS/SATA LL + * \param payload FW download response payload + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiFwProfileRsp( + agsaRoot_t *agRoot, + agsaFwProfileRsp_t *payload + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaContext_t *agContext; + + bit32 status, tag, len; + + /* get request from IOMap */ + OSSA_READ_LE_32(AGROOT, &tag, payload, OSSA_OFFSET_OF(agsaFwProfileRsp_t, tag)); + OSSA_READ_LE_32(AGROOT, &status, payload, OSSA_OFFSET_OF(agsaFwProfileRsp_t, status)); + OSSA_READ_LE_32(AGROOT, &len, payload, OSSA_OFFSET_OF(agsaFwProfileRsp_t, len)); + pRequest = saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + SA_DBG1(("mpiFwProfileRsp: the request is NULL. Tag=%x\n", tag)); + return AGSA_RC_FAILURE; + } + agContext = saRoot->IOMap[tag].agContext; + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + + if(!pRequest->valid) + { + SA_DBG1(("mpiPortControlRsp: pRequest->valid %d not set\n", pRequest->valid)); + } + + SA_ASSERT((pRequest->valid), "pRequest->valid"); + + pRequest->valid = agFALSE; + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + ossaFwProfileCB(agRoot, agContext, status, len); + + return ret; +} +#endif +/******************************************************************************/ +/*! \brief SPC FW_FLASH_UPDATE Respond + * + * This command sends FW Flash Update Status to TD layer. + * + * \param agRoot Handles for this instance of SAS/SATA LL + * \param payload FW download response payload + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiFwFlashUpdateRsp( + agsaRoot_t *agRoot, + agsaFwFlashUpdateRsp_t *payload + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaContext_t *agContext; + + bit32 status, tag; + smTraceFuncEnter(hpDBG_VERY_LOUD,"6b"); + + /* get request from IOMap */ + OSSA_READ_LE_32(AGROOT, &tag, payload, OSSA_OFFSET_OF(agsaFwFlashUpdateRsp_t, tag)); + OSSA_READ_LE_32(AGROOT, &status, payload, OSSA_OFFSET_OF(agsaFwFlashUpdateRsp_t, status)); + pRequest = saRoot->IOMap[tag].IORequest; + agContext = saRoot->IOMap[tag].agContext; + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_ASSERT((pRequest->valid), "pRequest->valid"); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiFwFlashUpdateRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + if(status > 1) + { + SA_DBG1(("mpiFwFlashUpdateRsp: status = 0x%x\n",status)); + } + + ossaFwFlashUpdateCB(agRoot, agContext, status); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "6b"); + + return ret; +} + +GLOBAL bit32 mpiFwExtFlashUpdateRsp( + agsaRoot_t *agRoot, + agsaFwFlashOpExtRsp_t *payload + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaContext_t *agContext; + + agsaFlashExtResponse_t FlashExtRsp; + + bit32 Command,Status, tag; + smTraceFuncEnter(hpDBG_VERY_LOUD,"2T"); + + /* get request from IOMap */ + OSSA_READ_LE_32(AGROOT, &tag, payload, OSSA_OFFSET_OF(agsaFwFlashOpExtRsp_t, tag)); + OSSA_READ_LE_32(AGROOT, &Command, payload, OSSA_OFFSET_OF(agsaFwFlashOpExtRsp_t,Command )); + OSSA_READ_LE_32(AGROOT, &Status, payload, OSSA_OFFSET_OF(agsaFwFlashOpExtRsp_t,Status )); + OSSA_READ_LE_32(AGROOT, &FlashExtRsp.epart_sect_size, payload, OSSA_OFFSET_OF(agsaFwFlashOpExtRsp_t,Epart_Size )); + OSSA_READ_LE_32(AGROOT, &FlashExtRsp.epart_size, payload, OSSA_OFFSET_OF(agsaFwFlashOpExtRsp_t,EpartSectSize )); + + pRequest = saRoot->IOMap[tag].IORequest; + agContext = saRoot->IOMap[tag].agContext; + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_ASSERT((pRequest->valid), "pRequest->valid"); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiFwExtFlashUpdateRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + if(Status > 1) + { + SA_DBG1(("mpiFwExtFlashUpdateRsp: status = 0x%x\n",Status)); + } + + ossaFlashExtExecuteCB(agRoot, agContext, Status,Command,&FlashExtRsp); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2T"); + + return ret; + +} + + +/******************************************************************************/ +/*! \brief SPC Get Controller Information Command + * + * This command sends Get Controller Information Command to SPC. + * + * \param agRoot Handles for this instance of SAS/SATA LL + * \param controllerInfo Controller Information + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ + +GLOBAL bit32 saGetControllerInfo( + agsaRoot_t *agRoot, + agsaControllerInfo_t *controllerInfo + ) +{ + + bit32 ret = AGSA_RC_SUCCESS; + bit32 max_wait_time; + bit32 max_wait_count; + bit32 ContrlCapFlag, MSGUCfgTblBase, CfgTblDWIdx; + bit32 value = 0, value1 = 0; + bit8 pcibar; + + if (agNULL != agRoot->sdkData) + { + smTraceFuncEnter(hpDBG_VERY_LOUD,"6e"); + } + /* clean the structure */ + si_memset(controllerInfo, 0, sizeof(agsaControllerInfo_t)); + + if(smIS_SPC6V(agRoot)) + { + controllerInfo->sdkInterfaceRev = STSDK_LL_INTERFACE_VERSION; + controllerInfo->sdkRevision = STSDK_LL_VERSION; + controllerInfo->hwRevision = (ossaHwRegReadConfig32(agRoot,8) & 0xFF); + }else if(smIS_SPC12V(agRoot)) + { + controllerInfo->sdkInterfaceRev = STSDK_LL_12G_INTERFACE_VERSION; + controllerInfo->sdkRevision = STSDK_LL_12G_VERSION; + controllerInfo->hwRevision = (ossaHwRegReadConfig32(agRoot,8) & 0xFF); + } else if(smIS_SPC(agRoot)) + { + controllerInfo->hwRevision = SPC_READ_DEV_REV; + controllerInfo->sdkInterfaceRev = MATCHING_SPC_FW_VERSION; + controllerInfo->sdkRevision = STSDK_LL_SPC_VERSION; + } + else + { + controllerInfo->hwRevision = (ossaHwRegReadConfig32(agRoot,8) & 0xFF); + } + + SA_DBG1(("saGetControllerInfo: SCRATCH_PAD0 value = 0x%x\n", siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_0, MSGU_SCRATCH_PAD_0))); + SA_DBG1(("saGetControllerInfo: SCRATCH_PAD1 value = 0x%x\n", siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1))); + SA_DBG1(("saGetControllerInfo: SCRATCH_PAD2 value = 0x%x\n", siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_2, MSGU_SCRATCH_PAD_2))); + SA_DBG1(("saGetControllerInfo: SCRATCH_PAD3 value = 0x%x\n", siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_3, MSGU_SCRATCH_PAD_3))); + SA_DBG1(("saGetControllerInfo: SCRATCH_PAD3 value = 0x%x\n", siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_3, MSGU_SCRATCH_PAD_3))); + + if(siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_0, MSGU_SCRATCH_PAD_0) == 0xFFFFFFFF) + { + SA_DBG1(("saGetControllerInfo:AGSA_RC_FAILURE SCRATCH_PAD0 value = 0x%x\n", + siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_0, MSGU_SCRATCH_PAD_0) ) ); + return AGSA_RC_FAILURE; + } + + if(siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_0, MSGU_SCRATCH_PAD_0) == 0xFFFFFFFF) + { + SA_DBG1(("saGetControllerInfo:AGSA_RC_FAILURE SCRATCH_PAD0 value = 0x%x\n", + siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_0, MSGU_SCRATCH_PAD_0) ) ); + return AGSA_RC_FAILURE; + } + + if( SCRATCH_PAD1_V_ERROR_STATE(siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1)) ) + { + SA_DBG1(("saGetControllerInfo: SCRATCH_PAD1 (0x%x) in error state ila %d raae %d Iop0 %d Iop1 %d\n", + siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1), + ( SCRATCH_PAD1_V_ILA_ERROR_STATE(siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1)) ? 1 : 0), + ( SCRATCH_PAD1_V_RAAE_ERROR_STATE(siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_1,MSGU_SCRATCH_PAD_1)) ? 1 : 0), + ( SCRATCH_PAD1_V_IOP0_ERROR_STATE(siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_1,MSGU_SCRATCH_PAD_1)) ? 1 : 0), + ( SCRATCH_PAD1_V_IOP1_ERROR_STATE(siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_1,MSGU_SCRATCH_PAD_1)) ? 1 : 0) )); + + } + + if(smIS_SPC(agRoot)) + { + /* check HDA mode */ + value = ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_STATUS_BITS; + + if (value == BOOTTLOADERHDA_IDLE) + { + /* HDA mode */ + SA_DBG1(("saGetControllerInfo: HDA mode, value = 0x%x\n", value)); + return AGSA_RC_HDA_NO_FW_RUNNING; + } + } + else + { + if(siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1) & SCRATCH_PAD1_V_RESERVED ) + { + SA_DBG1(("saGetControllerInfo: Warning SCRATCH_PAD1 reserved bits set value = 0x%x\n", siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1))); + } + if( si_check_V_HDA(agRoot)) + { + /* Check HDA */ + SA_DBG1(("saGetControllerInfo: HDA mode AGSA_RC_HDA_NO_FW_RUNNING\n" )); + return AGSA_RC_HDA_NO_FW_RUNNING; + } + + + } + + /* checking the fw AAP and IOP in ready state */ + max_wait_time = WAIT_SECONDS(gWait_2); /* 2 sec timeout */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); + /* wait until scratch pad 1 and 2 registers in ready state */ + if(smIS_SPCV(agRoot)) + { + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1); + value1 =siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2, MSGU_SCRATCH_PAD_2); + if(smIS_SPCV(agRoot)) + { + if((value & SCRATCH_PAD1_V_RESERVED) ) + { + SA_DBG1(("saGetControllerInfo: V reserved SCRATCH_PAD1 value = 0x%x (0x%x)\n", value, SCRATCH_PAD1_V_RESERVED)); + ret = AGSA_RC_FW_NOT_IN_READY_STATE; + break; + } + } + + if ((max_wait_count -= WAIT_INCREMENT) == 0) + { + SA_DBG1(("saGetControllerInfo: timeout SCRATCH_PAD1_V_READY !! SCRATCH_PAD1/2 value = 0x%x 0x%x\n", value, value1)); + break; + } + + } while (((value & SCRATCH_PAD1_V_READY) != SCRATCH_PAD1_V_READY) || (value == 0xffffffff)); + + } + else + { + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1); + /* checking bit 4 to 7 for reserved in case we get 0xFFFFFFFF */ + if (value & SCRATCH_PAD1_RESERVED) + { + SA_DBG1(("saGetControllerInfo: SCRATCH_PAD1 value = 0x%x\n", value)); + ret = AGSA_RC_FW_NOT_IN_READY_STATE; + break; + } + value1 =siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2,MSGU_SCRATCH_PAD_2); + /* checking bit 4 to 7 for reserved in case we get 0xFFFFFFFF */ + if (value1 & SCRATCH_PAD2_RESERVED) + { + SA_DBG1(("saGetControllerInfo: SCRATCH_PAD2 value = 0x%x\n", value1)); + ret = AGSA_RC_FW_NOT_IN_READY_STATE; + break; + } + if ((max_wait_count -= WAIT_INCREMENT) == 0) + { + SA_DBG1(("saGetControllerInfo: Timeout!! SCRATCH_PAD1/2 value = 0x%x 0x%x\n", value, value1)); + break; + } + } while (((value & SCRATCH_PAD_STATE_MASK) != SCRATCH_PAD1_RDY) || ((value1 & SCRATCH_PAD_STATE_MASK) != SCRATCH_PAD2_RDY)); + } + + if (!max_wait_count) + { + SA_DBG1(("saGetControllerInfo: timeout failure\n")); + ret = AGSA_RC_FW_NOT_IN_READY_STATE; + } + + if (ret == AGSA_RC_SUCCESS) + { + SA_DBG1(("saGetControllerInfo: FW Ready, SCRATCH_PAD1/2 value = 0x%x 0x%x\n", value, value1)); + + /* read scratch pad0 to get PCI BAR and offset of configuration table */ + MSGUCfgTblBase = siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_0, MSGU_SCRATCH_PAD_0); + /* get offset */ + CfgTblDWIdx = MSGUCfgTblBase & SCRATCH_PAD0_OFFSET_MASK; + /* get PCI BAR */ + MSGUCfgTblBase = (MSGUCfgTblBase & SCRATCH_PAD0_BAR_MASK) >> SHIFT26; + + /* convert the PCI BAR to logical bar number */ + pcibar = (bit8)mpiGetPCIBarIndex(agRoot, MSGUCfgTblBase); + + /* get controller information */ + controllerInfo->signature = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx); + controllerInfo->fwInterfaceRev = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_INTERFACE_REVISION); + controllerInfo->fwRevision = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_FW_REVISION); + controllerInfo->ilaRevision = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_ILAT_ILAV_ILASMRN_ILAMRN_ILAMJN); + controllerInfo->maxPendingIO = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_MAX_OUTSTANDING_IO_OFFSET); + controllerInfo->maxDevices = (ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_MAX_SGL_OFFSET) & MAIN_MAX_DEV_BITS); + controllerInfo->maxDevices = controllerInfo->maxDevices >> SHIFT16; + controllerInfo->maxSgElements = (ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_MAX_SGL_OFFSET) & MAIN_MAX_SGL_BITS); + + if( smIS_SPC(agRoot)) + { + SA_DBG2(("saGetControllerInfo: LINK_CTRL 0x%08x Speed 0x%X Lanes 0x%X \n", ossaHwRegReadConfig32(agRoot,128), + ((ossaHwRegReadConfig32(agRoot,128) & 0x000F0000) >> 16), + ((ossaHwRegReadConfig32(agRoot,128) & 0x0FF00000) >> 20) )); + controllerInfo->PCILinkRate = ((ossaHwRegReadConfig32(agRoot,128) & 0x000F0000) >> 16); + controllerInfo->PCIWidth = ((ossaHwRegReadConfig32(agRoot,128) & 0x0FF00000) >> 20); + } + else + { + SA_DBG2(("saGetControllerInfo: LINK_CTRL 0x%08x Speed 0x%X Lanes 0x%X \n", ossaHwRegReadConfig32(agRoot,208), + ((ossaHwRegReadConfig32(agRoot,208) & 0x000F0000) >> 16), + ((ossaHwRegReadConfig32(agRoot,208) & 0x0FF00000) >> 20) )); + controllerInfo->PCILinkRate = ((ossaHwRegReadConfig32(agRoot,208) & 0x000F0000) >> 16); + controllerInfo->PCIWidth = ((ossaHwRegReadConfig32(agRoot,208) & 0x0FF00000) >> 20); + } + + + ContrlCapFlag = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_CNTRL_CAP_OFFSET); + controllerInfo->queueSupport = ContrlCapFlag & MAIN_QSUPPORT_BITS; + controllerInfo->phyCount = (bit8)((ContrlCapFlag & MAIN_PHY_COUNT_MASK) >> SHIFT19); + + + if(smIS_SPCV(agRoot)) + { + controllerInfo->controllerSetting = (bit8)((siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1) & SCRATCH_PAD1_V_BOOTSTATE_MASK ) >> SHIFT4); + } + else + { + controllerInfo->controllerSetting = (bit8)(ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_HDA_FLAGS_OFFSET) & MAIN_HDA_FLAG_BITS); + } + controllerInfo->sasSpecsSupport = (ContrlCapFlag & MAIN_SAS_SUPPORT_BITS) >> SHIFT25; + } + + SA_DBG1(("saGetControllerInfo: signature 0x%X\n", controllerInfo->signature)); + SA_DBG1(("saGetControllerInfo: fwInterfaceRev 0x%X\n", controllerInfo->fwInterfaceRev)); + SA_DBG1(("saGetControllerInfo: hwRevision 0x%X\n", controllerInfo->hwRevision)); + SA_DBG1(("saGetControllerInfo: fwRevision 0x%X\n", controllerInfo->fwRevision)); + SA_DBG1(("saGetControllerInfo: ilaRevision 0x%X\n", controllerInfo->ilaRevision)); + SA_DBG1(("saGetControllerInfo: maxPendingIO 0x%X\n", controllerInfo->maxPendingIO)); + SA_DBG1(("saGetControllerInfo: maxDevices 0x%X\n", controllerInfo->maxDevices)); + SA_DBG1(("saGetControllerInfo: maxSgElements 0x%X\n", controllerInfo->maxSgElements)); + SA_DBG1(("saGetControllerInfo: queueSupport 0x%X\n", controllerInfo->queueSupport)); + SA_DBG1(("saGetControllerInfo: phyCount 0x%X\n", controllerInfo->phyCount)); + SA_DBG1(("saGetControllerInfo: controllerSetting 0x%X\n", controllerInfo->controllerSetting)); + SA_DBG1(("saGetControllerInfo: PCILinkRate 0x%X\n", controllerInfo->PCILinkRate)); + SA_DBG1(("saGetControllerInfo: PCIWidth 0x%X\n", controllerInfo->PCIWidth)); + SA_DBG1(("saGetControllerInfo: sasSpecsSupport 0x%X\n", controllerInfo->sasSpecsSupport)); + SA_DBG1(("saGetControllerInfo: sdkInterfaceRev 0x%X\n", controllerInfo->sdkInterfaceRev)); + SA_DBG1(("saGetControllerInfo: sdkRevision 0x%X\n", controllerInfo->sdkRevision)); + if (agNULL != agRoot->sdkData) + { + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "6e"); + } + return ret; +} + +/******************************************************************************/ +/*! \brief SPC Get Controller Status Command + * + * This command sends Get Controller Status Command to SPC. + * + * \param agRoot Handles for this instance of SAS/SATA LL + * \param controllerStatus controller status + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 saGetControllerStatus( + agsaRoot_t *agRoot, + agsaControllerStatus_t *controllerStatus + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + spc_GSTableDescriptor_t GSTable; + bit32 max_wait_time; + bit32 max_wait_count; + bit32 i, value, value1; + + if (agNULL != saRoot) + { + smTraceFuncEnter(hpDBG_VERY_LOUD,"6f"); + } + /* clean the structure */ + si_memset(controllerStatus, 0, sizeof(agsaControllerStatus_t)); + si_memset(&GSTable, 0, sizeof(spc_GSTableDescriptor_t)); + if(siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_0, MSGU_SCRATCH_PAD_0) == 0xFFFFFFFF) + { + SA_DBG1(("saGetControllerStatus:AGSA_RC_FAILURE SCRATCH_PAD0 value = 0x%x\n", siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_0, MSGU_SCRATCH_PAD_0))); + return AGSA_RC_FAILURE; + } + + if(siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_3) & (OSSA_ENCRYPT_ENGINE_FAILURE_MASK | OSSA_DIF_ENGINE_FAILURE_MASK)) + { + SA_DBG1(("saGetControllerStatus: BIST error in SCRATCHPAD 3 0x%x\n", siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_3, MSGU_SCRATCH_PAD_3))); + } + + if(smIS_SPC(agRoot)) + { + + /* read detail fatal errors */ + controllerStatus->fatalErrorInfo.errorInfo0 = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0); + controllerStatus->fatalErrorInfo.errorInfo1 = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1); + controllerStatus->fatalErrorInfo.errorInfo2 = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2); + controllerStatus->fatalErrorInfo.errorInfo3 = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3); + +#if defined(SALLSDK_DEBUG) + SA_DBG1(("saGetControllerStatus: SCRATCH_PAD0 value = 0x%x\n", controllerStatus->fatalErrorInfo.errorInfo0)); + SA_DBG1(("saGetControllerStatus: SCRATCH_PAD1 value = 0x%x\n", controllerStatus->fatalErrorInfo.errorInfo1)); + SA_DBG1(("saGetControllerStatus: SCRATCH_PAD2 value = 0x%x\n", controllerStatus->fatalErrorInfo.errorInfo2)); + SA_DBG1(("saGetControllerStatus: SCRATCH_PAD3 value = 0x%x\n", controllerStatus->fatalErrorInfo.errorInfo3)); +#endif + + /* check HDA mode */ + value = ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_STATUS_BITS; + + if (value == BOOTTLOADERHDA_IDLE) + { + /* HDA mode */ + SA_DBG1(("saGetControllerStatus: HDA mode, value = 0x%x\n", value)); + return AGSA_RC_HDA_NO_FW_RUNNING; + } + + /* check error state */ + value = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1); + value1 = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2); + + /* check AAP or IOP error */ + if ((SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) || (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK))) + { + if (agNULL != saRoot) + { + controllerStatus->fatalErrorInfo.regDumpBusBaseNum0 = saRoot->mainConfigTable.regDumpPCIBAR; + controllerStatus->fatalErrorInfo.regDumpOffset0 = saRoot->mainConfigTable.FatalErrorDumpOffset0; + controllerStatus->fatalErrorInfo.regDumpLen0 = saRoot->mainConfigTable.FatalErrorDumpLength0; + controllerStatus->fatalErrorInfo.regDumpBusBaseNum1 = saRoot->mainConfigTable.regDumpPCIBAR; + controllerStatus->fatalErrorInfo.regDumpOffset1 = saRoot->mainConfigTable.FatalErrorDumpOffset1; + controllerStatus->fatalErrorInfo.regDumpLen1 = saRoot->mainConfigTable.FatalErrorDumpLength1; + } + else + { + controllerStatus->fatalErrorInfo.regDumpBusBaseNum0 = 0; + controllerStatus->fatalErrorInfo.regDumpOffset0 = 0; + controllerStatus->fatalErrorInfo.regDumpLen0 = 0; + controllerStatus->fatalErrorInfo.regDumpBusBaseNum1 = 0; + controllerStatus->fatalErrorInfo.regDumpOffset1 = 0; + controllerStatus->fatalErrorInfo.regDumpLen1 = 0; + } + + if (agNULL != saRoot) + { + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "6f"); + } + return AGSA_RC_FW_NOT_IN_READY_STATE; + } + + /* checking the fw AAP and IOP in ready state */ + max_wait_time = WAIT_SECONDS(2); /* 2 sec timeout */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); + /* wait until scratch pad 1 and 2 registers in ready state */ + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + value = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1); + /* checking bit 4 to 7 for reserved in case we get 0xFFFFFFFF */ + if (value & SCRATCH_PAD1_RESERVED) + { + SA_DBG1(("saGetControllerStatus: (Reserved bit not 0) SCRATCH_PAD1 value = 0x%x\n", value)); + ret = AGSA_RC_FAILURE; + break; + } + + value1 = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2); + /* checking bit 4 to 7 for reserved in case we get 0xFFFFFFFF */ + if (value1 & SCRATCH_PAD2_RESERVED) + { + SA_DBG1(("saGetControllerStatus: (Reserved bit not 0) SCRATCH_PAD2 value = 0x%x\n", value1)); + ret = AGSA_RC_FAILURE; + break; + } + + if ((max_wait_count -=WAIT_INCREMENT) == 0) + { + SA_DBG1(("saGetControllerStatus: Timeout!! SCRATCH_PAD1/2 value = 0x%x 0x%x\n", value, value1)); + break; + } + } while (((value & SCRATCH_PAD_STATE_MASK) != SCRATCH_PAD1_RDY) || ((value1 & SCRATCH_PAD_STATE_MASK) != SCRATCH_PAD2_RDY)); + + if (!max_wait_count) + { + SA_DBG1(("saGetControllerStatus: timeout failure\n")); + ret = AGSA_RC_FAILURE; + } + + if (ret == AGSA_RC_SUCCESS) + { + SA_DBG1(("saGetControllerStatus: FW Ready, SCRATCH_PAD1/2 value = 0x%x 0x%x\n", value, value1)); + + /* read scratch pad0 to get PCI BAR and offset of configuration table */ + value = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0); + /* get offset */ + value1 = value & SCRATCH_PAD0_OFFSET_MASK; + /* get PCI BAR */ + value = (value & SCRATCH_PAD0_BAR_MASK) >> SHIFT26; + + /* read GST Table state */ + mpiReadGSTable(agRoot, &GSTable); + + /* read register dump information */ + controllerStatus->fatalErrorInfo.regDumpBusBaseNum0 = value; + controllerStatus->fatalErrorInfo.regDumpBusBaseNum1 = value; + /* convert the PCI BAR to logical bar number */ + value = (bit8)mpiGetPCIBarIndex(agRoot, value); + controllerStatus->fatalErrorInfo.regDumpOffset0 = ossaHwRegReadExt(agRoot, value, value1 + MAIN_FATAL_ERROR_RDUMP0_OFFSET); + controllerStatus->fatalErrorInfo.regDumpLen0 = ossaHwRegReadExt(agRoot, value, value1 + MAIN_FATAL_ERROR_RDUMP0_LENGTH); + controllerStatus->fatalErrorInfo.regDumpOffset1 = ossaHwRegReadExt(agRoot, value, value1 + MAIN_FATAL_ERROR_RDUMP1_OFFSET); + controllerStatus->fatalErrorInfo.regDumpLen1 = ossaHwRegReadExt(agRoot, value, value1 + MAIN_FATAL_ERROR_RDUMP1_LENGTH); + + /* AAP/IOP error state */ + SA_DBG2(("saGetControllerStatus: SCRATCH PAD0 0x%x\n", controllerStatus->fatalErrorInfo.errorInfo0)); + SA_DBG2(("saGetControllerStatus: SCRATCH PAD1 0x%x\n", controllerStatus->fatalErrorInfo.errorInfo1)); + SA_DBG2(("saGetControllerStatus: SCRATCH PAD2 0x%x\n", controllerStatus->fatalErrorInfo.errorInfo2)); + SA_DBG2(("saGetControllerStatus: SCRATCH PAD3 0x%x\n", controllerStatus->fatalErrorInfo.errorInfo3)); + /* Register Dump information */ + SA_DBG2(("saGetControllerStatus: RegDumpOffset0 0x%x\n", controllerStatus->fatalErrorInfo.regDumpOffset0)); + SA_DBG2(("saGetControllerStatus: RegDumpLen0 0x%x\n", controllerStatus->fatalErrorInfo.regDumpLen0)); + SA_DBG2(("saGetControllerStatus: RegDumpOffset1 0x%x\n", controllerStatus->fatalErrorInfo.regDumpOffset1)); + SA_DBG2(("saGetControllerStatus: RegDumpLen1 0x%x\n", controllerStatus->fatalErrorInfo.regDumpLen1)); + + controllerStatus->interfaceState = GSTable.GSTLenMPIS & GST_INF_STATE_BITS; + controllerStatus->iqFreezeState0 = GSTable.IQFreezeState0; + controllerStatus->iqFreezeState1 = GSTable.IQFreezeState1; + for (i = 0; i < 8; i++) + { + controllerStatus->phyStatus[i] = GSTable.PhyState[i]; + controllerStatus->recoverableErrorInfo[i] = GSTable.recoverErrInfo[i]; + } + controllerStatus->tickCount0 = GSTable.MsguTcnt; + controllerStatus->tickCount1 = GSTable.IopTcnt; + controllerStatus->tickCount2 = GSTable.Iop1Tcnt; + } + } + else + { + + SA_DBG1(("saGetControllerStatus: SPCv\n" )); + + + if(siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1) & SCRATCH_PAD1_V_RESERVED ) + { + SA_DBG1(("saGetControllerStatus: Warning SCRATCH_PAD1 reserved bits set value = 0x%x\n", siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1))); + } + if( si_check_V_HDA(agRoot)) + { + /* Check HDA */ + + controllerStatus->fatalErrorInfo.errorInfo0 = ossaHwRegRead(agRoot,V_Scratchpad_0_Register ); + controllerStatus->fatalErrorInfo.errorInfo1 = ossaHwRegRead(agRoot,V_Scratchpad_1_Register ); + controllerStatus->fatalErrorInfo.errorInfo2 = ossaHwRegRead(agRoot,V_Scratchpad_2_Register ); + controllerStatus->fatalErrorInfo.errorInfo3 = ossaHwRegRead(agRoot,V_Scratchpad_3_Register ); + SA_DBG1(("saGetControllerStatus: HDA mode, AGSA_RC_HDA_NO_FW_RUNNING errorInfo1 = 0x%x\n",controllerStatus->fatalErrorInfo.errorInfo1 )); + return AGSA_RC_HDA_NO_FW_RUNNING; + } + + ret = si_check_V_Ready(agRoot); + /* Check ready */ + if (ret == AGSA_RC_SUCCESS) + { + /* read GST Table state */ + mpiReadGSTable(agRoot, &GSTable); + controllerStatus->interfaceState = GSTable.GSTLenMPIS & GST_INF_STATE_BITS; + controllerStatus->iqFreezeState0 = GSTable.IQFreezeState0; + controllerStatus->iqFreezeState1 = GSTable.IQFreezeState1; + for (i = 0; i < 8; i++) + { + controllerStatus->phyStatus[i] = GSTable.PhyState[i]; + controllerStatus->recoverableErrorInfo[i] = GSTable.recoverErrInfo[i]; + } + controllerStatus->tickCount0 = GSTable.MsguTcnt; + controllerStatus->tickCount1 = GSTable.IopTcnt; + controllerStatus->tickCount2 = GSTable.Iop1Tcnt; + + controllerStatus->interfaceState = GSTable.GSTLenMPIS & GST_INF_STATE_BITS; + controllerStatus->iqFreezeState0 = GSTable.IQFreezeState0; + controllerStatus->iqFreezeState1 = GSTable.IQFreezeState1; + for (i = 0; i < 8; i++) + { + if( IS_SDKDATA(agRoot)) + { + if (agNULL != saRoot) + { + controllerStatus->phyStatus[i] = ((saRoot->phys[i+8].linkstatus << SHIFT8) | saRoot->phys[i].linkstatus); + } + } + else + { + controllerStatus->phyStatus[i] = 0; + } + controllerStatus->recoverableErrorInfo[i] = GSTable.recoverErrInfo[i]; + } + controllerStatus->tickCount0 = GSTable.MsguTcnt; + controllerStatus->tickCount1 = GSTable.IopTcnt; + controllerStatus->tickCount2 = GSTable.Iop1Tcnt; + + } + + SA_DBG1(("saGetControllerStatus: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegRead(agRoot, V_Scratchpad_0_Register))); + SA_DBG1(("saGetControllerStatus: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegRead(agRoot, V_Scratchpad_1_Register))); + SA_DBG1(("saGetControllerStatus: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegRead(agRoot, V_Scratchpad_2_Register))); + SA_DBG1(("saGetControllerStatus: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, V_Scratchpad_3_Register))); + + controllerStatus->fatalErrorInfo.errorInfo0 = ossaHwRegRead(agRoot,V_Scratchpad_0_Register ); + controllerStatus->fatalErrorInfo.errorInfo1 = ossaHwRegRead(agRoot,V_Scratchpad_1_Register ); + controllerStatus->fatalErrorInfo.errorInfo2 = ossaHwRegRead(agRoot,V_Scratchpad_2_Register ); + controllerStatus->fatalErrorInfo.errorInfo3 = ossaHwRegRead(agRoot,V_Scratchpad_3_Register ); + + controllerStatus->bootStatus = ( (( controllerStatus->fatalErrorInfo.errorInfo1 >> SHIFT9) & 1 ) | /* bit 1 */ + (( controllerStatus->fatalErrorInfo.errorInfo3 & 0x3) << SHIFT16) | /* bit 16 17 */ + ((( controllerStatus->fatalErrorInfo.errorInfo3 >> SHIFT14) & 0x7) << SHIFT18) | /* bit 18 19 20 */ + ((( controllerStatus->fatalErrorInfo.errorInfo3 >> SHIFT4 ) & 0x1) << SHIFT23) | /* bit 23 */ + ((( controllerStatus->fatalErrorInfo.errorInfo3 >> SHIFT16) & 0xFF) << SHIFT24) );/* bit 24 31 */ + + controllerStatus->bootComponentState[0] = (bit16) (( controllerStatus->fatalErrorInfo.errorInfo1 & 3 ) | 0x8000); /* RAAE_STATE */ + controllerStatus->bootComponentState[1] = (bit16) ((( controllerStatus->fatalErrorInfo.errorInfo1 >> SHIFT10) & 3 ) | 0x8000); /* IOP0_STATE */ + controllerStatus->bootComponentState[2] = (bit16) ((( controllerStatus->fatalErrorInfo.errorInfo1 >> SHIFT12) & 3 ) | 0x8000); /* IOP1_STATE */ + controllerStatus->bootComponentState[3] = (bit16) ((( controllerStatus->fatalErrorInfo.errorInfo1 >> SHIFT4) & 7 ) | 0x8000); /* BOOTLDR_STATE */ + controllerStatus->bootComponentState[4] = (bit16) ((( controllerStatus->fatalErrorInfo.errorInfo1 >> SHIFT2) & 3 ) | 0x8000); /* ILA State */ + controllerStatus->bootComponentState[5] = 0; + controllerStatus->bootComponentState[6] = 0; + controllerStatus->bootComponentState[7] = 0; + + + + if(controllerStatus->fatalErrorInfo.errorInfo0 == 0xFFFFFFFF) + { + ret = AGSA_RC_FAILURE; + } + + } + + SA_DBG1(("saGetControllerStatus: fatalErrorInfo.errorInfo0 0x%x\n", controllerStatus->fatalErrorInfo.errorInfo0)); + SA_DBG1(("saGetControllerStatus: fatalErrorInfo.errorInfo1 0x%x\n", controllerStatus->fatalErrorInfo.errorInfo1)); + SA_DBG1(("saGetControllerStatus: fatalErrorInfo.errorInfo2 0x%x\n", controllerStatus->fatalErrorInfo.errorInfo2)); + SA_DBG1(("saGetControllerStatus: fatalErrorInfo.errorInfo3 0x%x\n", controllerStatus->fatalErrorInfo.errorInfo3)); + SA_DBG1(("saGetControllerStatus: fatalErrorInfo.regDumpBusBaseNum0 0x%x\n", controllerStatus->fatalErrorInfo.regDumpBusBaseNum0)); + SA_DBG1(("saGetControllerStatus: fatalErrorInfo.regDumpOffset0 0x%x\n", controllerStatus->fatalErrorInfo.regDumpOffset0)); + SA_DBG1(("saGetControllerStatus: fatalErrorInfo.regDumpLen0 0x%x\n", controllerStatus->fatalErrorInfo.regDumpLen0)); + SA_DBG1(("saGetControllerStatus: fatalErrorInfo.regDumpBusBaseNum1 0x%x\n", controllerStatus->fatalErrorInfo.regDumpBusBaseNum1)); + SA_DBG1(("saGetControllerStatus: fatalErrorInfo.regDumpOffset1 0x%x\n", controllerStatus->fatalErrorInfo.regDumpOffset1)); + SA_DBG1(("saGetControllerStatus: fatalErrorInfo.regDumpLen1 0x%x\n", controllerStatus->fatalErrorInfo.regDumpLen1)); + + SA_DBG1(("saGetControllerStatus: interfaceState 0x%x\n", controllerStatus->interfaceState)); + SA_DBG1(("saGetControllerStatus: iqFreezeState0 0x%x\n", controllerStatus->iqFreezeState0)); + SA_DBG1(("saGetControllerStatus: iqFreezeState1 0x%x\n", controllerStatus->iqFreezeState1)); + SA_DBG1(("saGetControllerStatus: tickCount0 0x%x\n", controllerStatus->tickCount0)); + SA_DBG1(("saGetControllerStatus: tickCount1 0x%x\n", controllerStatus->tickCount1)); + SA_DBG1(("saGetControllerStatus: tickCount2 0x%x\n", controllerStatus->tickCount2)); + + SA_DBG1(("saGetControllerStatus: phyStatus[0] 0x%08x\n", controllerStatus->phyStatus[0])); + SA_DBG1(("saGetControllerStatus: phyStatus[1] 0x%08x\n", controllerStatus->phyStatus[1])); + SA_DBG1(("saGetControllerStatus: phyStatus[2] 0x%08x\n", controllerStatus->phyStatus[2])); + SA_DBG1(("saGetControllerStatus: phyStatus[3] 0x%08x\n", controllerStatus->phyStatus[3])); + SA_DBG1(("saGetControllerStatus: phyStatus[4] 0x%08x\n", controllerStatus->phyStatus[4])); + SA_DBG1(("saGetControllerStatus: phyStatus[5] 0x%08x\n", controllerStatus->phyStatus[5])); + SA_DBG1(("saGetControllerStatus: phyStatus[6] 0x%08x\n", controllerStatus->phyStatus[6])); + SA_DBG1(("saGetControllerStatus: phyStatus[7] 0x%08x\n", controllerStatus->phyStatus[7])); + + SA_DBG1(("saGetControllerStatus: recoverableErrorInfo[0] 0x%08x\n", controllerStatus->recoverableErrorInfo[0])); + SA_DBG1(("saGetControllerStatus: recoverableErrorInfo[1] 0x%08x\n", controllerStatus->recoverableErrorInfo[1])); + SA_DBG1(("saGetControllerStatus: recoverableErrorInfo[2] 0x%08x\n", controllerStatus->recoverableErrorInfo[2])); + SA_DBG1(("saGetControllerStatus: recoverableErrorInfo[3] 0x%08x\n", controllerStatus->recoverableErrorInfo[3])); + SA_DBG1(("saGetControllerStatus: recoverableErrorInfo[4] 0x%08x\n", controllerStatus->recoverableErrorInfo[4])); + SA_DBG1(("saGetControllerStatus: recoverableErrorInfo[5] 0x%08x\n", controllerStatus->recoverableErrorInfo[5])); + SA_DBG1(("saGetControllerStatus: recoverableErrorInfo[6] 0x%08x\n", controllerStatus->recoverableErrorInfo[6])); + SA_DBG1(("saGetControllerStatus: recoverableErrorInfo[7] 0x%08x\n", controllerStatus->recoverableErrorInfo[7])); + + SA_DBG1(("saGetControllerStatus: bootStatus 0x%08x\n", controllerStatus->bootStatus)); + SA_DBG1(("saGetControllerStatus: bootStatus Active FW Image %x\n", (controllerStatus->bootStatus & 1 ) ? 1 : 0 )); + SA_DBG1(("saGetControllerStatus: bootStatus Encryption Cap %x\n", ((controllerStatus->bootStatus & 0x30000 ) >> SHIFT16) )); + SA_DBG1(("saGetControllerStatus: bootStatus Encryption Sec Mode %x\n", ((controllerStatus->bootStatus & 0xC0000 ) >> SHIFT18) )); + SA_DBG1(("saGetControllerStatus: bootStatus Encryption AES XTS %x\n", (controllerStatus->bootStatus & 0x800000 ) ? 1 : 0 )); + SA_DBG1(("saGetControllerStatus: bootStatus Encryption Engine Stat 0x%x\n", ((controllerStatus->bootStatus & 0xFF000000 ) >> SHIFT24) )); + +/* + +Bit 0 : Active FW Image +0b: Primary Image +1b: Secondary Image + +Bit 16-17 : Encryption Capability +00: Not supported. Controller firmware version doesn't support encryption functionality. +01: Disabled due to error. Controller firmware supports encryption however, the functionality is currently disabled due to an error. The actual cause of the error is indicated in the error code field (bits [23:16]). +10: Enabled with Error. Encryption is currently enabled however, firmware encountered encryption-related error during initialization which might have caused the controller to enter SMF Security mode and/or disabled access to non-volatile memory for encryption-related information. The actual cause of the error is indicated in the error code field (bits [23:16]). +11: Enabled. Encryption functionality is enabled and fully functional. +Bit 18-21 : Encryption Current Security Mode +0000: Security Mode Factory +0001: Security Mode A +0010: Security Mode B +All other values are reserved. +Bit22: Reserved +Bit 23 : Encryption AES XTS Enabled +0: AES XTS is disabled. +1: AES XTS is enabled +Bit 24-31 : Encryption Engine Status +*/ + + + SA_DBG1(("saGetControllerStatus: bootComponentState[0] RAAE_STATE 0x%x\n", controllerStatus->bootComponentState[0])); + SA_DBG1(("saGetControllerStatus: bootComponentState[1] IOP0_STATE 0x%x\n", controllerStatus->bootComponentState[1])); + SA_DBG1(("saGetControllerStatus: bootComponentState[2] IOP1_STATE 0x%x\n", controllerStatus->bootComponentState[2])); + SA_DBG1(("saGetControllerStatus: bootComponentState[3] BOOTLDR_ 0x%x\n", controllerStatus->bootComponentState[3])); + SA_DBG1(("saGetControllerStatus: bootComponentState[4] ILA State 0x%x\n", controllerStatus->bootComponentState[4])); + SA_DBG1(("saGetControllerStatus: bootComponentState[5] 0x%x\n", controllerStatus->bootComponentState[5])); + SA_DBG1(("saGetControllerStatus: bootComponentState[6] 0x%x\n", controllerStatus->bootComponentState[6])); + SA_DBG1(("saGetControllerStatus: bootComponentState[7] 0x%x\n", controllerStatus->bootComponentState[7])); + + if (agNULL != saRoot) + { + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "6f"); + } + + return ret; +} + +/******************************************************************************/ +/*! \brief SPC Get Controller Event Log Information Command + * + * This command sends Get Controller Event Log Information Command to SPC. + * + * \param agRoot Handles for this instance of SAS/SATA LL + * \param eventLogInfo event log information + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 saGetControllerEventLogInfo( + agsaRoot_t *agRoot, + agsaControllerEventLog_t *eventLogInfo + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + + smTraceFuncEnter(hpDBG_VERY_LOUD,"6g"); + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + + eventLogInfo->eventLog1 = saRoot->memoryAllocated.agMemory[MPI_MEM_INDEX + MPI_EVENTLOG_INDEX]; + eventLogInfo->eventLog1Option = saRoot->mainConfigTable.eventLogOption; + eventLogInfo->eventLog2 = saRoot->memoryAllocated.agMemory[MPI_MEM_INDEX + MPI_IOP_EVENTLOG_INDEX]; + eventLogInfo->eventLog2Option = saRoot->mainConfigTable.IOPeventLogOption; + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "6g"); + + return ret; +} + +/******************************************************************************/ +/*! \brief SPC Set GPIO Event Setup Command + * + * This command sends GPIO Event Setup Command to SPC. + * + * \param agRoot Handles for this instance of SAS/SATA LL + * \param agsaContext Context of this command + * \param queueNum Queue number of inbound/outbound queue + * \param gpioEventSetupInfo Pointer of Event Setup Information structure + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 saGpioEventSetup( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaGpioEventSetupInfo_t *gpioEventSetupInfo + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaGPIOCmd_t payload; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"6h"); + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saGpioEventSetup, No request from free list\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "6h"); + return AGSA_RC_BUSY; + } + /* If LL Control request entry avaliable */ + else + { + /* Remove the request from free list */ + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + + /* set payload to zeros */ + si_memset(&payload, 0, sizeof(agsaGPIOCmd_t)); + /* build IOMB command and send to SPC */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGPIOCmd_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGPIOCmd_t, eOBIDGeGsGrGw), GPIO_GE_BIT); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGPIOCmd_t, GPIEVChange), gpioEventSetupInfo->gpioEventLevel); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGPIOCmd_t, GPIEVFall), gpioEventSetupInfo->gpioEventFallingEdge); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGPIOCmd_t, GPIEVRise), gpioEventSetupInfo->gpioEventRisingEdge); + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_GPIO, IOMB_SIZE64, queueNum); + if (AGSA_RC_SUCCESS != ret) + { + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("saGpioEventSetup: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + SA_DBG1(("saGpioEventSetup, sending IOMB failed\n" )); + } + } + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "6h"); + + return ret; +} + +/******************************************************************************/ +/*! \brief SPC Set GPIO Pin Setup Command + * + * This command sends GPIO Pin Setup Command to SPC. + * + * \param agRoot Handles for this instance of SAS/SATA LL + * \param agsaContext Context of this command + * \param queueNum Queue number of inbound/outbound queue + * \param gpioPinSetupInfo Pointer of Event Setup Information structure + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 saGpioPinSetup( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaGpioPinSetupInfo_t *gpioPinSetupInfo + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaGPIOCmd_t payload; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"6i"); + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saGpioPinSetup, No request from free list\n" )); + return AGSA_RC_BUSY; + } + /* If LL Control request entry avaliable */ + else + { + /* Remove the request from free list */ + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + + /* set payload to zeros */ + si_memset(&payload, 0, sizeof(agsaGPIOCmd_t)); + /* build IOMB command and send to SPC */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGPIOCmd_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGPIOCmd_t, eOBIDGeGsGrGw), GPIO_GS_BIT); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGPIOCmd_t, GpioIe), gpioPinSetupInfo->gpioInputEnabled); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGPIOCmd_t, OT11_0), gpioPinSetupInfo->gpioTypePart1); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGPIOCmd_t, OT19_12), gpioPinSetupInfo->gpioTypePart2); + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_GPIO, IOMB_SIZE64, queueNum); + if (AGSA_RC_SUCCESS != ret) + { + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("saGpioPinSetup: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + SA_DBG1(("saGpioPinSetup, sending IOMB failed\n" )); + } + } + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "6i"); + + return ret; +} + +/******************************************************************************/ +/*! \brief SPC GPIO Read Command + * + * This command sends GPIO Read Command to SPC. + * + * \param agRoot Handles for this instance of SAS/SATA LL + * \param agsaContext Context of this command + * \param queueNum Queue number of inbound/outbound queue + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 saGpioRead( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaGPIOCmd_t payload; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"6j"); + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saGpioRead, No request from free list\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "6j"); + return AGSA_RC_BUSY; + } + /* If LL Control request entry avaliable */ + else + { + /* Remove the request from free list */ + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + + /* set payload to zeros */ + si_memset(&payload, 0, sizeof(agsaGPIOCmd_t)); + /* build IOMB command and send to SPC */ + /* set GR bit */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGPIOCmd_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGPIOCmd_t, eOBIDGeGsGrGw), GPIO_GR_BIT); + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_GPIO, IOMB_SIZE64, queueNum); + if (AGSA_RC_SUCCESS != ret) + { + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("saGpioRead: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + SA_DBG1(("saGpioRead, sending IOMB failed\n" )); + } + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "6j"); + + return ret; +} + +/******************************************************************************/ +/*! \brief SPC GPIO Write Command + * + * This command sends GPIO Write Command to SPC. + * + * \param agRoot Handles for this instance of SAS/SATA LL + * \param agsaContext Context of this command + * \param queueNum Queue number of inbound/outbound queue + * \param gpioWriteMask GPIO Write Mask + * \param gpioWriteValue GPIO Write Value + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 saGpioWrite( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 gpioWriteMask, + bit32 gpioWriteValue + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaGPIOCmd_t payload; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"6k"); + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saGpioWrite, No request from free list\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "6k"); + return AGSA_RC_BUSY; + } + /* If LL Control request entry avaliable */ + else + { + /* Remove the request from free list */ + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + + /* set payload to zeros */ + si_memset(&payload, 0, sizeof(agsaGPIOCmd_t)); + /* build IOMB command and send to SPC */ + /* set GW bit */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGPIOCmd_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGPIOCmd_t, eOBIDGeGsGrGw), GPIO_GW_BIT); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGPIOCmd_t, GpioWrMsk), gpioWriteMask); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGPIOCmd_t, GpioWrVal), gpioWriteValue); + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_GPIO, IOMB_SIZE64, queueNum); + if (AGSA_RC_SUCCESS != ret) + { + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("saGpioWrite: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + SA_DBG1(("saGpioWrite, sending IOMB failed\n" )); + } + } + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "6k"); + + return ret; +} + +/******************************************************************************/ +/*! \brief SPC SAS Diagnostic Execute Command + * + * This command sends SAS Diagnostic Execute Command to SPC. + * + * \param agRoot Handles for this instance of SAS/SATA LL + * \param agsaContext Context of this command + * \param queueNum Queue number of inbound/outbound queue + * \param diag Pointer of SAS Diag Execute Structure + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 saSASDiagExecute( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaSASDiagExecute_t *diag + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = agNULL; + agsaIORequestDesc_t *pRequest = agNULL; + bit32 payload[32]; + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + + saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + /* sanity check */ + SA_ASSERT((agNULL != saRoot), ""); + + smTraceFuncEnter(hpDBG_VERY_LOUD,"6m"); + + SA_DBG2(("saSASDiagExecute,command 0x%X\n", diag->command )); + SA_DBG2(("saSASDiagExecute,param0 0x%X\n", diag->param0 )); + SA_DBG2(("saSASDiagExecute,param2 0x%X\n", diag->param2 )); + SA_DBG2(("saSASDiagExecute,param3 0x%X\n", diag->param3 )); + SA_DBG2(("saSASDiagExecute,param4 0x%X\n", diag->param4 )); + SA_DBG2(("saSASDiagExecute,param5 0x%X\n", diag->param5 )); + + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saSASDiagExecute, No request from free list\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "6m"); + return AGSA_RC_BUSY; + } + /* If LL Control request entry avaliable */ + else + { + /* Remove the request from free list */ + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + if(smIS_SPC(agRoot)) + { + diag->param5 = 0; /* Reserved for SPC */ + } + + /* set payload to zeros */ + si_memset(&payload, 0, sizeof(payload)); + /* set payload to zeros */ + if(smIS_SPCV(agRoot)) + { + /* build IOMB command and send to SPC */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSASDiagExecuteCmd_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSASDiagExecuteCmd_t, CmdTypeDescPhyId),diag->command ); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSASDiagExecuteCmd_t, Pat1Pat2), diag->param0 ); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSASDiagExecuteCmd_t, Threshold), diag->param1 ); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSASDiagExecuteCmd_t, CodePatErrMsk), diag->param2 ); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSASDiagExecuteCmd_t, Pmon), diag->param3 ); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSASDiagExecuteCmd_t, PERF1CTL), diag->param4 ); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSASDiagExecuteCmd_t, THRSHLD1), diag->param5 ); + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_SAS_DIAG_EXECUTE, IOMB_SIZE128, queueNum); + } + else + { + /* build IOMB command and send to SPC */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsa_SPC_SASDiagExecuteCmd_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsa_SPC_SASDiagExecuteCmd_t, CmdTypeDescPhyId),diag->command ); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsa_SPC_SASDiagExecuteCmd_t, Pat1Pat2), diag->param0 ); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsa_SPC_SASDiagExecuteCmd_t, Threshold), diag->param1 ); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsa_SPC_SASDiagExecuteCmd_t, CodePatErrMsk), diag->param2 ); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsa_SPC_SASDiagExecuteCmd_t, Pmon), diag->param3 ); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsa_SPC_SASDiagExecuteCmd_t, PERF1CTL), diag->param4 ); + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_SAS_DIAG_EXECUTE, IOMB_SIZE64, queueNum); + } + if (AGSA_RC_SUCCESS != ret) + { + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("saSASDiagExecute: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + SA_DBG1(("saSASDiagExecute, sending IOMB failed\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "6m"); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + return ret; + } + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "6m"); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + return ret; +} + +/******************************************************************************/ +/*! \brief SPC SAS Diagnostic Start/End Command + * + * This command sends SAS Diagnostic Start/End Command to SPC. + * + * \param agRoot Handles for this instance of SAS/SATA LL + * \param agsaContext Context of this command + * \param queueNum Queue number of inbound/outbound queue + * \param phyId Phy ID + * \param operation Operation of SAS Diagnostic + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 saSASDiagStartEnd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 phyId, + bit32 operation + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot; + agsaIORequestDesc_t *pRequest; + agsaSASDiagStartEndCmd_t payload; + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + if (agRoot == agNULL) + { + SA_DBG1(("saSASDiagStartEnd: agRoot == agNULL\n")); + return AGSA_RC_FAILURE; + } + saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + SA_ASSERT((agNULL != saRoot), ""); + if (saRoot == agNULL) + { + SA_DBG1(("saSASDiagStartEnd: saRoot == agNULL\n")); + return AGSA_RC_FAILURE; + } + + smTraceFuncEnter(hpDBG_VERY_LOUD,"6n"); + + SA_DBG3(("saSASDiagStartEnd, phyId 0x%x operation 0x%x\n",phyId,operation )); + + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saSASDiagStartEnd, No request from free list\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "6n"); + return AGSA_RC_BUSY; + } + /* If LL Control request entry avaliable */ + else + { + /* Remove the request from free list */ + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + + /* set payload to zeros */ + si_memset(&payload, 0, sizeof(agsaSASDiagStartEndCmd_t)); + /* build IOMB command and send to SPC */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSASDiagStartEndCmd_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSASDiagStartEndCmd_t, OperationPhyId), ((phyId & SM_PHYID_MASK) | (operation << SHIFT8))); + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_SAS_DIAG_MODE_START_END, IOMB_SIZE64, queueNum); + if (AGSA_RC_SUCCESS != ret) + { + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("saSASDiagStartEnd: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + SA_DBG1(("saSASDiagStartEnd, sending IOMB failed\n" )); + } + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "6n"); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + return ret; +} + +/******************************************************************************/ +/*! \brief Initiate a GET TIME STAMP command + * + * This function is called to initiate a Get Time Stamp command to the SPC. + * The completion of this function is reported in ossaGetTimeStampCB(). + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param agContext the context of this API + * \param queueNum queue number + * + * \return + * - SUCCESS or FAILURE + */ +/*******************************************************************************/ +GLOBAL bit32 saGetTimeStamp( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum + ) +{ + agsaIORequestDesc_t *pRequest; + agsaGetTimeStampCmd_t payload; + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot; + SA_ASSERT((agNULL != agRoot), ""); + if (agRoot == agNULL) + { + SA_DBG1(("saGetTimeStamp: agRoot == agNULL\n")); + return AGSA_RC_FAILURE; + } + saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + SA_ASSERT((agNULL != saRoot), ""); + if (saRoot == agNULL) + { + SA_DBG1(("saGetTimeStamp: saRoot == agNULL\n")); + return AGSA_RC_FAILURE; + } + + smTraceFuncEnter(hpDBG_VERY_LOUD,"6o"); + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + + SA_DBG3(("saGetTimeStamp: agContext %p\n", agContext)); + + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saGetTimeStamp, No request from free list\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "6o"); + return AGSA_RC_BUSY; + } + /* If LL Control request entry avaliable */ + else + { + /* Remove the request from free list */ + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + + /* build IOMB command and send to SPC */ + /* set payload to zeros */ + si_memset(&payload, 0, sizeof(agsaGetTimeStampCmd_t)); + + /* set tag */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetTimeStampCmd_t, tag), pRequest->HTag); + + /* build IOMB command and send to SPC */ + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_GET_TIME_STAMP, IOMB_SIZE64, queueNum); + if (AGSA_RC_SUCCESS != ret) + { + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("saGetTimeStamp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + SA_DBG1(("saGetTimeStamp, sending IOMB failed\n" )); + } + } + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "6o"); + + return ret; +} + +/******************************************************************************/ +/*! \brief Update IOMap Entry + * + * This function is called to update certain fields of IOMap Entry + * + * \param pIOMap IOMap Entry + * \param HTag Host Tag + * \param pRequest Request + * \parma agContext Context of this API + * + * \return NA + */ +/*******************************************************************************/ +static void saUpdateIOMap( + agsaIOMap_t *pIOMap, + bit32 HTag, + agsaIORequestDesc_t *pRequest, + agsaContext_t *agContext + ) +{ + pIOMap->Tag = HTag; + pIOMap->IORequest = (void *)pRequest; + pIOMap->agContext = agContext; +} + +/******************************************************************************/ +/*! \brief Get a request from free pool + * + * This function gets a request from free pool + * + * \param agRoot Handles for this instance of SAS/SATA LL + * \param agsaContext Context of this command + * + * \return + * - \e Pointer to request, in case of success + * - \e NULL, in case of failure + * + */ +/*******************************************************************************/ +agsaIORequestDesc_t* saGetRequestFromFreePool( + agsaRoot_t *agRoot, + agsaContext_t *agContext + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest = agNULL; + + /* Acquire LL_IOREQ_LOCKEQ_LOCK */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* Get request from free IORequests */ + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + if (pRequest != agNULL) + { + /* Remove the request from free list */ + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + + /* Release LL_IOREQ_LOCKEQ_LOCK */ + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* Add the request to IOMap */ + saUpdateIOMap(&saRoot->IOMap[pRequest->HTag], pRequest->HTag, pRequest, agContext); + pRequest->valid = agTRUE; + } + else + { + /* Release LL_IOREQ_LOCKEQ_LOCK */ + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + } + + return pRequest; +} + +/******************************************************************************/ +/*! \brief Return request to free pool + * + * This function returns the request to free pool + * + * \param agRoot Handles for this instance of SAS/SATA LL + * \param pRequest Request to be returned + * + * \return NA + * + */ +/*******************************************************************************/ +void saReturnRequestToFreePool( + agsaRoot_t *agRoot, + agsaIORequestDesc_t *pRequest + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + + SA_ASSERT((pRequest->valid), "pRequest->valid"); + + /* Remove the request from IOMap */ + saUpdateIOMap(&saRoot->IOMap[pRequest->HTag], MARK_OFF, agNULL, agNULL); + pRequest->valid = agFALSE; + + /* Acquire LL_IOREQ_LOCKEQ_LOCK */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + if (saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("saReturnRequestToFreePool: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* Return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + + /* Release LL_IOREQ_LOCKEQ_LOCK */ + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); +} +/******************************************************************************/ +/*! \brief Initiate a serial GPIO command + * + * This function is called to initiate a serial GPIO command to the SPC. + * The completion of this function is reported in ossaSgpioCB(). + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param agContext the context of this API + * \param queueNum queue number + * \param pSGpioReq Pointer to the serial GPIO fields + * + * \return + * - SUCCESS or FAILURE + */ +/*******************************************************************************/ +GLOBAL bit32 saSgpio( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaSGpioReqResponse_t *pSGpioReq + ) +{ + bit32 i; + agsaIORequestDesc_t *pRequest = agNULL; + agsaSGpioCmd_t payload = {0}; + bit32 ret = AGSA_RC_BUSY; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"6t"); + + /* Sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + + SA_DBG3(("saSgpio: agContext %p\n", agContext)); + + /* Get request from free pool */ + pRequest = saGetRequestFromFreePool(agRoot, agContext); + if (agNULL == pRequest) + { + SA_DBG1(("saSgpio, No request from free list\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "6t"); + } + else + { + /* Set payload to zeros */ + si_memset(&payload, 0, sizeof(agsaSGpioCmd_t)); + + /* set tag */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSGpioCmd_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSGpioCmd_t, regIndexRegTypeFunctionFrameType), + (pSGpioReq->smpFrameType | + ((bit32)pSGpioReq->function << 8) | + ((bit32)pSGpioReq->registerType << 16) | + ((bit32)pSGpioReq->registerIndex << 24))); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSGpioCmd_t, regCount), pSGpioReq->registerCount); + + if (SA_SAS_SMP_WRITE_GPIO_REGISTER == pSGpioReq->function) + { + for (i = 0; i < pSGpioReq->registerCount; i++) + { + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSGpioCmd_t, writeData) + (i * 4), pSGpioReq->readWriteData[i]); + } + } + + /* Build IOMB command and send to SPC */ + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_SGPIO, IOMB_SIZE64, queueNum); + if (AGSA_RC_SUCCESS != ret) + { + /* Return the request to free pool */ + saReturnRequestToFreePool(agRoot, pRequest); + SA_DBG1(("saSgpio, sending IOMB failed\n" )); + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "6t"); + } + + return ret; +} + +/******************************************************************************/ +/*! \brief for spc card read Error Registers to memory if error occur + * + * This function is called to get erorr registers content to memory if error occur. + * + * \param agRoot handles for this instance of SAS/SATA hardware + * + * \return + */ +/*******************************************************************************/ +LOCAL void siSpcGetErrorContent( + agsaRoot_t *agRoot + ) +{ + + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + bit32 value, value1; + + value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1) & SCRATCH_PAD_STATE_MASK; + value1 = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2, MSGU_SCRATCH_PAD_2) & SCRATCH_PAD_STATE_MASK; + /* check AAP error */ + if ((SCRATCH_PAD1_ERR == value) || (SCRATCH_PAD2_ERR == value1)) + { + /* fatal error */ + /* get register dump from GSM and save it to LL local memory */ + siGetRegisterDumpGSM(agRoot, (void *)&saRoot->registerDump0[0], + REG_DUMP_NUM0, 0, saRoot->mainConfigTable.FatalErrorDumpLength0); + siGetRegisterDumpGSM(agRoot, (void *)&saRoot->registerDump1[0], + REG_DUMP_NUM1, 0, saRoot->mainConfigTable.FatalErrorDumpLength1); + } +} + + +/******************************************************************************/ +/*! \brief for spcv card read Error Registers to memory if error occur + * + * This function is called to get erorr registers content to memory if error occur. + * + * \param agRoot handles for this instance of SAS/SATA hardware + * + * \return + */ +/*******************************************************************************/ +LOCAL void siSpcvGetErrorContent( + agsaRoot_t *agRoot + ) +{ + + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + bit32 value; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2d"); + value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1); + + if(((value & SPCV_RAAE_STATE_MASK) == SPCV_ERROR_VALUE) || + ((value & SPCV_IOP0_STATE_MASK) == SPCV_ERROR_VALUE) || + ((value & SPCV_IOP1_STATE_MASK) == SPCV_ERROR_VALUE) + ) + { + /* fatal error */ + /* get register dump from GSM and save it to LL local memory */ + siGetRegisterDumpGSM(agRoot, (void *)&saRoot->registerDump0[0], + REG_DUMP_NUM0, 0, saRoot->mainConfigTable.FatalErrorDumpLength0); + siGetRegisterDumpGSM(agRoot, (void *)&saRoot->registerDump1[0], + REG_DUMP_NUM1, 0, saRoot->mainConfigTable.FatalErrorDumpLength1); + } + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2d"); +} + +#define LEFT_BYTE_FAIL(x, v) \ + do {if( (x) < (v) ) return AGSA_RC_FAILURE; } while(0); + +LOCAL bit32 siDumpInboundQueue( + void * buffer, + bit32 length, + mpiICQueue_t *q + ) +{ + bit8 * _buf = buffer; + si_memcpy( _buf, (bit8*)(q->memoryRegion.virtPtr) + length, 128*256); + return AGSA_RC_SUCCESS; +} + +LOCAL bit32 siDumpOutboundQueue( + void * buffer, + bit32 length, + mpiOCQueue_t *q) +{ + bit8 * _buf = buffer; + si_memcpy( _buf, (bit8*)(q->memoryRegion.virtPtr) + length, 128*256); + return AGSA_RC_SUCCESS; +} + + +LOCAL bit32 siWaitForNonFatalTransfer( agsaRoot_t *agRoot,bit32 pcibar) +{ + bit32 status = AGSA_RC_SUCCESS; + bit32 ready; + bit32 max_wait_time; + bit32 max_wait_count; + smTraceFuncEnter(hpDBG_VERY_LOUD,"2c"); + + SA_DBG4(("siWaitForNonFatalTransfer:0 IBDBS 0x%x\n",ossaHwRegReadExt(agRoot,0 ,V_Inbound_Doorbell_Set_Register ) )); + /* Write FDDHSHK */ + + + /* Write bit7 of inbound doorbell set register step 3 */ + ossaHwRegWriteExt(agRoot, 0,V_Inbound_Doorbell_Set_Register, SPCV_MSGU_CFG_TABLE_TRANSFER_DEBUG_INFO ); + SA_DBG4(("siWaitForNonFatalTransfer:1 IBDBS 0x%x\n",ossaHwRegReadExt(agRoot,0 ,V_Inbound_Doorbell_Set_Register ) )); + + /* Poll bit7 of inbound doorbell set register until clear step 4 */ + max_wait_time = (2000 * 1000); /* wait 2 seconds */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + ready = ossaHwRegReadExt(agRoot,0 ,V_Inbound_Doorbell_Set_Register ); + } while ( (ready & SPCV_MSGU_CFG_TABLE_TRANSFER_DEBUG_INFO) && (max_wait_count -= WAIT_INCREMENT)); + if(max_wait_count == 0) + { + SA_DBG1(("siWaitForNonFatalTransfer:Timeout IBDBS 0x%x\n",ossaHwRegReadExt(agRoot,0 ,V_Inbound_Doorbell_Set_Register ) )); + status = AGSA_RC_FAILURE; + } + + SA_DBG4(("siWaitForNonFatalTransfer:3 IBDBS 0x%x\n",ossaHwRegReadExt(agRoot,0 ,V_Inbound_Doorbell_Set_Register ) )); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2c"); + return(status); +} + +LOCAL bit32 siWaitForFatalTransfer( agsaRoot_t *agRoot,bit32 pcibar) +{ + bit32 status = AGSA_RC_SUCCESS; + bit32 ready; + bit32 ErrorTableOffset; + bit32 max_wait_time; + bit32 max_wait_count; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2o"); + + ErrorTableOffset = siGetTableOffset( agRoot, MAIN_MERRDCTO_MERRDCES ); + + SA_DBG4(("siWaitForFatalTransfer: MPI_FATAL_EDUMP_TABLE_STATUS Offset 0x%x 0x%x\n",ErrorTableOffset+MPI_FATAL_EDUMP_TABLE_STATUS, ossaHwRegReadExt(agRoot,pcibar ,ErrorTableOffset+MPI_FATAL_EDUMP_TABLE_STATUS ))); + SA_DBG4(("siWaitForFatalTransfer: MPI_FATAL_EDUMP_TABLE_ACCUM_LEN Offset 0x%x 0x%x\n",ErrorTableOffset+MPI_FATAL_EDUMP_TABLE_ACCUM_LEN, ossaHwRegReadExt(agRoot,pcibar ,ErrorTableOffset+ MPI_FATAL_EDUMP_TABLE_ACCUM_LEN))); + /* + 2. Write 0x1 to the Fatal Error Debug Dump Handshake control [FDDHSHK] field in Table 73 and + read back the same field (by polling) until it is 0. This prompts the debug agent to copy the next + part of the debug data into GSM shared memory. To check the completion of the copy process, the + host must poll the Fatal/Non Fatal Debug Data Transfer Status [FDDTSTAT] field in the Table + Table 73. + */ + + /* Write FDDHSHK */ + ossaHwRegWriteExt(agRoot,pcibar ,ErrorTableOffset+MPI_FATAL_EDUMP_TABLE_HANDSHAKE, MPI_FATAL_EDUMP_HANDSHAKE_RDY ); + SA_DBG4(("siWaitForFatalTransfer:1 MPI_FATAL_EDUMP_TABLE_HANDSHAKE 0x%x\n",ossaHwRegReadExt(agRoot,pcibar ,ErrorTableOffset+MPI_FATAL_EDUMP_TABLE_HANDSHAKE ) )); + + /* Poll FDDHSHK until clear */ + max_wait_time = (2000 * 1000); /* wait 2 seconds */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + ready = ossaHwRegReadExt(agRoot,0 ,ErrorTableOffset+MPI_FATAL_EDUMP_TABLE_HANDSHAKE ); + } while (ready && (max_wait_count -= WAIT_INCREMENT)); + if(max_wait_count == 0) + { + SA_DBG1(("siWaitForFatalTransfer : 1 Timeout\n")); + status = AGSA_RC_FAILURE; + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2o"); + return(status); +} + + + +LOCAL bit32 siFatalErrorBuffer( + agsaRoot_t *agRoot, + agsaForensicData_t *forensicData + ) +{ + bit32 status = AGSA_RC_FAILURE; + bit32 pcibar; + bit32 ErrorTableOffset; + bit32 Accum_len = 0; + + agsaLLRoot_t *saRoot; + /* sanity check */ + SA_ASSERT( (agNULL != agRoot), ""); + saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + SA_ASSERT( (agNULL != saRoot), "saRoot"); + if(agNULL == saRoot ) + { + SA_DBG1(("siFatalErrorBuffer: agNULL saRoot\n")); + return(status); + } + + if(saRoot->ResetFailed ) + { + SA_DBG1(("siFatalErrorBuffer: saRoot->ResetFailed\n")); + return(status); + } + smTraceFuncEnter(hpDBG_VERY_LOUD,"2a"); + SA_DBG2(("siFatalErrorBuffer:In %p Offset 0x%08x Len 0x%08x Totel len 0x%x\n", + forensicData->BufferType.dataBuf.directData, + forensicData->BufferType.dataBuf.directOffset, + forensicData->BufferType.dataBuf.directLen, + forensicData->BufferType.dataBuf.readLen )); + + pcibar = siGetPciBar(agRoot); + ErrorTableOffset = siGetTableOffset( agRoot, MAIN_MERRDCTO_MERRDCES ); + + SA_DBG3(("siFatalErrorBuffer: MPI_FATAL_EDUMP_TABLE_STATUS 0x%x LEN 0x%x\n", + ossaHwRegReadExt(agRoot,pcibar ,ErrorTableOffset+MPI_FATAL_EDUMP_TABLE_STATUS), + ossaHwRegReadExt(agRoot,pcibar ,ErrorTableOffset+ MPI_FATAL_EDUMP_TABLE_ACCUM_LEN) )); + + /* + This section describes sequence for the host to capture debug data under fatal error conditions. + A fatal error is an error condition that stops the SPCv controller from normal operation and causes it + to be unresponsive to host requests. Since the firmware is non-operational, the host needs to pull the + debug dump information using PCIe MEMBASE II with the assistance of the debug agent which becomes + active when the main controller firmware fails. + */ + /* + To capture the fatal error debug data, the host must: + 1. Upon detecting the fatal error condition through a fatal error interrupt or by the MSGU scratchpad + registers, capture the first part of the fatal error debug data. Upon fatal error, the first part of the + debug data is located GSM shared memory and its length is updated in the Accumulative Debug + Data Length Transferred [ACCDDLEN] field in Table Table 82. To capture the first part: + */ + if(forensicData->BufferType.dataBuf.directOffset == 0) + { + /* start to get data */ + /* + a. Program the MEMBASE II Shifting Register with 0x00. + */ + ossaHwRegWriteExt(agRoot, pcibar,V_MEMBASE_II_ShiftRegister, saRoot->FatalForensicShiftOffset); // set base to zero + + saRoot->ForensicLastOffset =0; + saRoot->FatalForensicStep = 0; + saRoot->FatalBarLoc = 0; + saRoot->FatalForensicShiftOffset = 0; + + SA_DBG1(("siFatalErrorBuffer: directOffset zero SCRATCH_PAD1 0x%x\n", siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1) )); + } + + /* Read until Accum_len is retrived */ + Accum_len = ossaHwRegReadExt(agRoot,pcibar ,ErrorTableOffset+ MPI_FATAL_EDUMP_TABLE_ACCUM_LEN); + + SA_DBG2(("siFatalErrorBuffer: Accum_len 0x%x\n", Accum_len)); + if(Accum_len == 0xFFFFFFFF) + { + SA_DBG1(("siFatalErrorBuffer: Possible PCI issue 0x%x not expected\n", Accum_len)); + return(status); + } + + if( Accum_len == 0 || Accum_len >=0x100000 ) + { + SA_DBG1(("siFatalErrorBuffer: Accum_len == saRoot->FatalCurrentLength 0x%x\n", Accum_len)); + return(IOCTL_ERROR_NO_FATAL_ERROR); + } + + if(saRoot->FatalForensicStep == 0) /* PM Step 1a and 1b */ + { + moreData: + if(forensicData->BufferType.dataBuf.directData) + { + siPciCpyMem(agRoot,saRoot->FatalBarLoc ,forensicData->BufferType.dataBuf.directData,forensicData->BufferType.dataBuf.directLen ,1 ); + } + saRoot->FatalBarLoc += forensicData->BufferType.dataBuf.directLen; + forensicData->BufferType.dataBuf.directOffset += forensicData->BufferType.dataBuf.directLen; + saRoot->ForensicLastOffset += forensicData->BufferType.dataBuf.directLen; + forensicData->BufferType.dataBuf.readLen = forensicData->BufferType.dataBuf.directLen; + + if(saRoot->ForensicLastOffset >= Accum_len) + { + /* + e. Repeat the above 2 steps until all debug data is retrieved as specified in the Accumulative Debug + Data Length Transferred [ACCDDLEN] field. + NOTE: The ACCDDLEN field is cumulative so the host needs to take the difference from the + previous step. + */ + /* This section data ends get next section */ + SA_DBG1(("siFatalErrorBuffer: Accum_len reached 0x%x directOffset 0x%x\n",Accum_len,forensicData->BufferType.dataBuf.directOffset )); + saRoot->FatalBarLoc = 0; + saRoot->FatalForensicStep = 1; + saRoot->FatalForensicShiftOffset = 0; + status = AGSA_RC_COMPLETE; + return status; + } + if(saRoot->FatalBarLoc < (64*1024)) + { + SA_DBG2(("siFatalErrorBuffer: In same 64k FatalBarLoc 0x%x\n",saRoot->FatalBarLoc )); + status = AGSA_RC_SUCCESS; + return status; + } + /* + c. Increment the MEMBASE II Shifting Register value by 0x100. + */ + saRoot->FatalForensicShiftOffset+= 0x100; + ossaHwRegWriteExt(agRoot, pcibar,V_MEMBASE_II_ShiftRegister, saRoot->FatalForensicShiftOffset); + saRoot->FatalBarLoc = 0; + + SA_DBG1(("siFatalErrorBuffer: Get next bar data 0x%x\n",saRoot->FatalForensicShiftOffset)); + + status = AGSA_RC_SUCCESS; + + SA_DBG1(("siFatalErrorBuffer:Offset 0x%x BarLoc 0x%x\n",saRoot->FatalForensicShiftOffset,saRoot->FatalBarLoc )); + SA_DBG1(("siFatalErrorBuffer: step 0 status %d %p Offset 0x%x Len 0x%x total_len 0x%x\n", + status, + forensicData->BufferType.dataBuf.directData, + forensicData->BufferType.dataBuf.directOffset, + forensicData->BufferType.dataBuf.directLen, + forensicData->BufferType.dataBuf.readLen )); + return(status); + } + + if(saRoot->FatalForensicStep == 1) + { + + /* + 3. If Fatal/Non Fatal Debug Data Transfer Status [FDDTSTAT] field indicates status value of + 0x00000002 or 0x00000003, read the next part of the fatal debug data by taking the difference + between the preserved ACCDDLEN value from step 2 and the new ACCDDLEN value.To capture + the second part: + a. Program the MEMBASE II Shifting Register with 0x00. + */ + SA_DBG1(("siFatalErrorBuffer: FatalForensicStep 1 Accum_len 0x%X MPI_FATAL_EDUMP_TABLE_ACCUM_LEN 0x%x\n", + Accum_len, + ossaHwRegReadExt(agRoot,pcibar ,ErrorTableOffset+ MPI_FATAL_EDUMP_TABLE_ACCUM_LEN))); + + saRoot->FatalForensicShiftOffset = 0; /* location in 64k region */ + /* + b. Read 64K of the debug data. + */ + ossaHwRegWriteExt(agRoot, pcibar,V_MEMBASE_II_ShiftRegister ,saRoot->FatalForensicShiftOffset); + SA_DBG1(("siFatalErrorBuffer: FatalForensicStep 1\n" )); + /* + 2.Write 0x1 to the Fatal Error Debug Dump Handshake control [FDDHSHK] + field inTable 82 and read back the same field (by polling for 2 seconds) until it is 0. This prompts + the debug agent to copy the next part of the debug data into GSM shared memory. To check the + completion of the copy process, the host must poll the Fatal/Non Fatal Debug Data Transfer Status + [FDDTSTAT] field for 2 secondsin the MPI Fatal and Non-Fatal Error Dump Capture Table Table 82. + */ + siWaitForFatalTransfer( agRoot,pcibar); + + /* + d. Read the next 64K of the debug data. + */ + saRoot->FatalForensicStep = 0; + + if( ossaHwRegReadExt(agRoot,pcibar ,ErrorTableOffset+ MPI_FATAL_EDUMP_TABLE_STATUS) != MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE ) + { + + SA_DBG3(("siFatalErrorBuffer:Step 3\n" )); + SA_DBG3(("siFatalErrorBuffer:Step 3 MPI_FATAL_EDUMP_TABLE_STATUS 0x%x\n", ossaHwRegReadExt(agRoot,pcibar ,ErrorTableOffset+ MPI_FATAL_EDUMP_TABLE_STATUS ))); + /* + 2. Write FDDSTAT to 0x00000000 but preserve the Accumulative Debug Data Length Transferred + [ACCDDLEN] field. + */ + ossaHwRegWriteExt(agRoot,pcibar ,ErrorTableOffset+MPI_FATAL_EDUMP_TABLE_STATUS, 0 ); + /* + 4. If FDDSTAT is 0x00000002, repeat steps 2 and 3 until you reach this step with FDDSTAT being + equal to 0x00000003. + */ + goto moreData; + } + else + { + /* + When FDDSTAT equals 0x00000003 and ACCDDLEN is unchanged, then + */ + /* + the fatal error dump is complete. If ACCDDLEN increases, one more read step is required. + The content and format of the debug data is opaque to the host and must be forwarded to PMC-Sierra + Applications support for failure analysis. Debug data is retrieved in several iterations which enables + the host to use a smaller buffer and store the captured debug data in secondary storage during the process. + */ + + SA_DBG3(("siFatalErrorBuffer:Step 4\n" )); + SA_DBG1(("siFatalErrorBuffer: Done Read 0x%x accum 0x%x\n", + forensicData->BufferType.dataBuf.directOffset, + ossaHwRegReadExt(agRoot,pcibar ,ErrorTableOffset+ MPI_FATAL_EDUMP_TABLE_ACCUM_LEN))); + +#if defined(SALLSDK_DEBUG) + SA_DBG1(("siFatalErrorBuffer: SCRATCH_PAD1_V_ERROR_STATE 0x%x\n",SCRATCH_PAD1_V_ERROR_STATE( siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1) ))); + SA_DBG1(("siFatalErrorBuffer: SCRATCH_PAD0 value = 0x%x\n", siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_0, MSGU_SCRATCH_PAD_0))); + SA_DBG1(("siFatalErrorBuffer: SCRATCH_PAD1 value = 0x%x\n", siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1))); + SA_DBG1(("siFatalErrorBuffer: SCRATCH_PAD2 value = 0x%x\n", siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_2, MSGU_SCRATCH_PAD_2))); + SA_DBG1(("siFatalErrorBuffer: SCRATCH_PAD3 value = 0x%x\n", siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_3, MSGU_SCRATCH_PAD_3))); +#endif + forensicData->BufferType.dataBuf.readLen = 0xFFFFFFFF; + status = AGSA_RC_SUCCESS; + + } + } + + + SA_DBG3(("siFatalErrorBuffer:status 0x%x %p directOffset 0x%x directLen 0x%x readLen 0x%x\n", + status, + forensicData->BufferType.dataBuf.directData, + forensicData->BufferType.dataBuf.directOffset, + forensicData->BufferType.dataBuf.directLen, + forensicData->BufferType.dataBuf.readLen )); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2a"); + return(status); +} + +LOCAL bit32 siNonFatalErrorBuffer( + agsaRoot_t *agRoot, + agsaForensicData_t *forensicData + ) +{ + bit32 status = AGSA_RC_FAILURE; + bit32 pcibar; + bit32 ErrorTableOffset; + + //bit32 i; + bit32 ready; + bit32 biggest; + bit32 max_wait_time; + bit32 max_wait_count; + agsaLLRoot_t *saRoot; + /* sanity check */ + SA_ASSERT( (agNULL != agRoot), "agRoot"); + saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + SA_ASSERT( (agNULL != saRoot), "saRoot"); + if(agNULL == saRoot ) + { + SA_DBG1(("siNonFatalErrorBuffer: agNULL saRoot\n")); + return(status); + } + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2b"); + pcibar = siGetPciBar(agRoot); + ErrorTableOffset = siGetTableOffset( agRoot, MAIN_MERRDCTO_MERRDCES ); + + SA_DBG4(("siNonFatalErrorBuffer: ErrorTableOffset 0x%x\n",ErrorTableOffset )); + + SA_DBG4(("siNonFatalErrorBuffer: MPI_FATAL_EDUMP_TABLE_STATUS Offset 0x%x 0x%x\n", + ErrorTableOffset + MPI_FATAL_EDUMP_TABLE_STATUS, + ossaHwRegReadExt(agRoot,pcibar,ErrorTableOffset + MPI_FATAL_EDUMP_TABLE_STATUS))); + SA_DBG4(("siNonFatalErrorBuffer: MPI_FATAL_EDUMP_TABLE_ACCUM_LEN Offset 0x%x 0x%x\n", + ErrorTableOffset + MPI_FATAL_EDUMP_TABLE_ACCUM_LEN, + ossaHwRegReadExt(agRoot,pcibar,ErrorTableOffset + MPI_FATAL_EDUMP_TABLE_ACCUM_LEN))); + + biggest = saRoot->memoryAllocated.agMemory[HDA_DMA_BUFFER].totalLength; + + if(biggest >= forensicData->BufferType.dataBuf.directLen ) + { + biggest = forensicData->BufferType.dataBuf.directLen; + } + else + { + SA_DBG1(("siNonFatalErrorBuffer: directLen larger than DMA Buffer 0x%x < 0x%x\n", + biggest, forensicData->BufferType.dataBuf.directLen)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2b"); + return(AGSA_RC_FAILURE); + } + + if(saRoot->memoryAllocated.agMemory[HDA_DMA_BUFFER].virtPtr) + { + si_memset(saRoot->memoryAllocated.agMemory[HDA_DMA_BUFFER].virtPtr, 0, biggest); + } + else + { + SA_DBG1(("siNonFatalErrorBuffer: Error\n" )); + return(AGSA_RC_FAILURE); + } + + + if(forensicData->BufferType.dataBuf.directOffset) + { + /* Write FDDSTAT and ACCDDLEN to zero step 2 */ + ossaHwRegWriteExt(agRoot, pcibar, ErrorTableOffset + MPI_FATAL_EDUMP_TABLE_STATUS, 0); + goto skip_setup; + } + + SA_DBG1(("siNonFatalErrorBuffer: %p Offset 0x%x Len 0x%x total_len 0x%x\n", + forensicData->BufferType.dataBuf.directData, + forensicData->BufferType.dataBuf.directOffset, + forensicData->BufferType.dataBuf.directLen, + forensicData->BufferType.dataBuf.readLen )); + + SA_DBG1(("siNonFatalErrorBuffer: directOffset zero setup\n" )); + SA_DBG1(("siNonFatalErrorBuffer: MPI_FATAL_EDUMP_TABLE_STATUS 0x%x LEN 0x%x\n", + ossaHwRegReadExt(agRoot,pcibar ,ErrorTableOffset+MPI_FATAL_EDUMP_TABLE_STATUS), + ossaHwRegReadExt(agRoot,pcibar ,ErrorTableOffset+ MPI_FATAL_EDUMP_TABLE_ACCUM_LEN) )); + + SA_DBG1(("siNonFatalErrorBuffer: Clear V_Scratchpad_Rsvd_0_Register 0x%x\n", + ossaHwRegReadExt(agRoot, 0,V_Scratchpad_Rsvd_0_Register) )); + ossaHwRegWriteExt(agRoot, 0,V_Scratchpad_Rsvd_0_Register ,0); + + saRoot->ForensicLastOffset = 0; + + /* WriteACCDDLEN for error interface Step 0 */ + /*ossaHwRegWriteExt(agRoot, pcibar, ErrorTableOffset + MPI_FATAL_EDUMP_TABLE_ACCUM_LEN ,0);*/ + + /* Write DMA get Offset for error interface Step 1 */ + ossaHwRegWriteExt(agRoot, pcibar, ErrorTableOffset + MPI_FATAL_EDUMP_TABLE_LO_OFFSET, saRoot->memoryAllocated.agMemory[HDA_DMA_BUFFER].phyAddrLower); + ossaHwRegWriteExt(agRoot, pcibar, ErrorTableOffset + MPI_FATAL_EDUMP_TABLE_HI_OFFSET, saRoot->memoryAllocated.agMemory[HDA_DMA_BUFFER].phyAddrUpper); + ossaHwRegWriteExt(agRoot, pcibar, ErrorTableOffset + MPI_FATAL_EDUMP_TABLE_LENGTH, biggest); + + /* Write FDDSTAT and ACCDDLEN to zero step 2 */ + ossaHwRegWriteExt(agRoot, pcibar, ErrorTableOffset + MPI_FATAL_EDUMP_TABLE_STATUS, 0); + ossaHwRegWriteExt(agRoot, pcibar, ErrorTableOffset + MPI_FATAL_EDUMP_TABLE_ACCUM_LEN, 0); + + SA_DBG4(("siNonFatalErrorBuffer: MPI_FATAL_EDUMP_TABLE_STATUS Offset 0x%x 0x%x\n", + ErrorTableOffset + MPI_FATAL_EDUMP_TABLE_STATUS, + ossaHwRegReadExt(agRoot,pcibar,ErrorTableOffset + MPI_FATAL_EDUMP_TABLE_STATUS ))); + SA_DBG4(("siNonFatalErrorBuffer: MPI_FATAL_EDUMP_TABLE_ACCUM_LEN Offset 0x%x 0x%x\n", + ErrorTableOffset + MPI_FATAL_EDUMP_TABLE_ACCUM_LEN, + ossaHwRegReadExt(agRoot, pcibar, ErrorTableOffset + MPI_FATAL_EDUMP_TABLE_ACCUM_LEN))); + + if( 0 != ossaHwRegReadExt(agRoot, pcibar, ErrorTableOffset + MPI_FATAL_EDUMP_TABLE_ACCUM_LEN)) + { + SA_DBG1(("siNonFatalErrorBuffer: MPI_FATAL_EDUMP_TABLE_ACCUM_LEN 0x%x 0x%x\n", + forensicData->BufferType.dataBuf.directOffset, + ossaHwRegReadExt(agRoot, pcibar, ErrorTableOffset + MPI_FATAL_EDUMP_TABLE_ACCUM_LEN))); + } + skip_setup: + + if( saRoot->ForensicLastOffset == 0xFFFFFFFF) + { + forensicData->BufferType.dataBuf.readLen = 0xFFFFFFFF; + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2b"); + return(AGSA_RC_SUCCESS); + } + + + /* Write bit7 of inbound doorbell set register and wait for complete step 3 and 4*/ + siWaitForNonFatalTransfer(agRoot,pcibar); + + SA_DBG3(("siNonFatalErrorBuffer: MPI_FATAL_EDUMP_TABLE_STATUS 0x%x LEN 0x%x\n", + ossaHwRegReadExt(agRoot,pcibar ,ErrorTableOffset+MPI_FATAL_EDUMP_TABLE_STATUS), + ossaHwRegReadExt(agRoot,pcibar ,ErrorTableOffset+ MPI_FATAL_EDUMP_TABLE_ACCUM_LEN) )); + + + + max_wait_time = (2000 * 1000); /* wait 2 seconds */ + max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; + ready = ossaHwRegReadExt(agRoot,pcibar,ErrorTableOffset + MPI_FATAL_EDUMP_TABLE_STATUS ); + do + { + ossaStallThread(agRoot, WAIT_INCREMENT); + ready = ossaHwRegReadExt(agRoot,pcibar ,ErrorTableOffset + MPI_FATAL_EDUMP_TABLE_STATUS ); + forensicData->BufferType.dataBuf.directOffset = ossaHwRegReadExt(agRoot,pcibar,ErrorTableOffset + MPI_FATAL_EDUMP_TABLE_ACCUM_LEN); + if( ready == MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA ) + { + SA_DBG2(("siNonFatalErrorBuffer: More data available MPI_FATAL_EDUMP_TABLE_ACCUM_LEN 0x%x\n", ossaHwRegReadExt(agRoot,pcibar,ErrorTableOffset+ MPI_FATAL_EDUMP_TABLE_ACCUM_LEN) )); + break; + } + } while ( ready != MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE && (max_wait_count -= WAIT_INCREMENT)); + + + if(max_wait_count == 0 || ready == MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED) + { + status = AGSA_RC_FAILURE; + SA_DBG1(("siNonFatalErrorBuffer: timeout waiting ready\n")); + } + else + { + forensicData->BufferType.dataBuf.readLen = forensicData->BufferType.dataBuf.directOffset - saRoot->ForensicLastOffset; + if( ready == MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE && forensicData->BufferType.dataBuf.readLen == 0) + { + SA_DBG1(("siNonFatalErrorBuffer:ready 0x%x readLen 0x%x\n",ready ,forensicData->BufferType.dataBuf.readLen)); + saRoot->ForensicLastOffset = 0xFFFFFFFF; + } + else + { + saRoot->ForensicLastOffset = forensicData->BufferType.dataBuf.directOffset; + } + + if(forensicData->BufferType.dataBuf.directData ) + { + si_memcpy(forensicData->BufferType.dataBuf.directData, saRoot->memoryAllocated.agMemory[HDA_DMA_BUFFER].virtPtr,biggest); + } + status = AGSA_RC_SUCCESS; + } + /* step 5 */ + SA_DBG3(("siNonFatalErrorBuffer: %p directOffset 0x%x directLen 0x%x readLen 0x%x\n", + forensicData->BufferType.dataBuf.directData, + forensicData->BufferType.dataBuf.directOffset, + forensicData->BufferType.dataBuf.directLen, + forensicData->BufferType.dataBuf.readLen )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "2b"); + return(status); +} + + +LOCAL bit32 siGetForensicData( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaForensicData_t *forensicData + ) +{ + bit32 status = AGSA_RC_FAILURE; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2Z"); + + if(forensicData->DataType == TYPE_GSM_SPACE) + { +#define _1M 0x100000 + if( forensicData->BufferType.gsmBuf.directLen >= _1M ) + { + return AGSA_RC_FAILURE; + } + + if(forensicData->BufferType.dataBuf.readLen) + { + SA_DBG1(("siGetForensicData: Incorrect readLen 0x%08X\n", forensicData->BufferType.dataBuf.readLen)); + forensicData->BufferType.dataBuf.readLen = forensicData->BufferType.dataBuf.directLen; + } + if( forensicData->BufferType.dataBuf.directOffset >= ONE_MEGABYTE ) + { + SA_DBG1(("siGSMDump: total length > ONE_MEGABYTE 0x%x\n",forensicData->BufferType.dataBuf.directOffset)); + forensicData->BufferType.dataBuf.readLen = 0xFFFFFFFF; + return(AGSA_RC_SUCCESS); + } + if(smIS_SPC(agRoot)) + { + if( forensicData->BufferType.dataBuf.directLen >= SIXTYFOURKBYTE ) + { + SA_DBG1(("siGetForensicData directLen too large !\n")); + return AGSA_RC_FAILURE; + } + SA_DBG1(("siGetForensicData: TYPE_GSM_SPACE directLen 0x%X directOffset 0x%08X %p\n", + forensicData->BufferType.dataBuf.directLen, + forensicData->BufferType.dataBuf.directOffset, + forensicData->BufferType.dataBuf.directData )); + + + /* Shift BAR4 original address */ + if (AGSA_RC_FAILURE == siBar4Shift(agRoot, BAR_SHIFT_GSM_OFFSET + forensicData->BufferType.dataBuf.directOffset)) + { + SA_DBG1(("siGSMDump:Shift Bar4 to 0x%x failed\n", 0x0)); + return AGSA_RC_FAILURE; + } + + + //if( forensicData->BufferType.dataBuf.directOffset >= ONE_MEGABYTE ) + //{ + //SA_DBG1(("siGSMDump: total length > ONE_MEGABYTE 0x%x\n",forensicData->BufferType.dataBuf.directOffset)); + //forensicData->BufferType.dataBuf.readLen = 0xFFFFFFFF; + //return(AGSA_RC_SUCCESS); + //} + forensicData->BufferType.gsmBuf.directOffset = 0; + } + status = siGSMDump( agRoot, + forensicData->BufferType.gsmBuf.directOffset, + forensicData->BufferType.gsmBuf.directLen, + forensicData->BufferType.gsmBuf.directData ); + + if(status == AGSA_RC_SUCCESS) + { + forensicData->BufferType.dataBuf.readLen = forensicData->BufferType.dataBuf.directLen; + } + + if( forensicData->BufferType.dataBuf.directOffset == 0 ) + { + SA_DBG1(("siGetForensicData: TYPE_GSM_SPACE readLen 0x%08X\n", forensicData->BufferType.dataBuf.readLen)); + } + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2Z"); + + return status; + } + else if(forensicData->DataType == TYPE_INBOUND_QUEUE ) + { + mpiICQueue_t *circularQ = NULL; + SA_DBG2(("siGetForensicData: TYPE_INBOUND \n")); + + if(forensicData->BufferType.queueBuf.queueIndex >=AGSA_MAX_INBOUND_Q ) + { + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "2Z"); + return AGSA_RC_FAILURE; + } + circularQ = &saRoot->inboundQueue[forensicData->BufferType.queueBuf.queueIndex]; + status = siDumpInboundQueue( forensicData->BufferType.queueBuf.directData, + forensicData->BufferType.queueBuf.directLen, + circularQ ); + smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "2Z"); + return status; + } + else if(forensicData->DataType == TYPE_OUTBOUND_QUEUE ) + //else if( forensicData->BufferType.queueBuf.queueType == TYPE_OUTBOUND_QUEUE ) + { + mpiOCQueue_t *circularQ = NULL; + SA_DBG2(("siGetForensicData: TYPE_OUTBOUND\n")); + + if(forensicData->BufferType.queueBuf.queueIndex >= AGSA_MAX_OUTBOUND_Q ) + { + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "2Z"); + return AGSA_RC_FAILURE; + } + + circularQ = &saRoot->outboundQueue[forensicData->BufferType.queueBuf.queueIndex]; + status = siDumpOutboundQueue(forensicData->BufferType.queueBuf.directData, + forensicData->BufferType.queueBuf.directLen, + circularQ ); + smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "2Z"); + + return status; + } + else if(forensicData->DataType == TYPE_NON_FATAL ) + { + // if(smIS_SPCV(agRoot)) + // { + SA_DBG2(("siGetForensicData:TYPE_NON_FATAL \n")); + status = siNonFatalErrorBuffer(agRoot,forensicData); + // } + smTraceFuncExit(hpDBG_VERY_LOUD, 'f', "2Z"); + return status; + } + else if(forensicData->DataType == TYPE_FATAL ) + { + // if(smIS_SPCV(agRoot)) + //{ + SA_DBG2(("siGetForensicData:TYPE_NON_FATAL \n")); + status = siFatalErrorBuffer(agRoot,forensicData ); + // } + smTraceFuncExit(hpDBG_VERY_LOUD, 'g', "2Z"); + return status; + } + else + { + SA_DBG1(("siGetForensicData receive error parameter!\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'h', "2Z"); + return AGSA_RC_FAILURE; + } + smTraceFuncExit(hpDBG_VERY_LOUD, 'i', "2Z"); + + return status; +} + + +//GLOBAL bit32 saGetForensicData( +bit32 saGetForensicData( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaForensicData_t *forensicData + ) +{ + bit32 status; + status = siGetForensicData(agRoot, agContext, forensicData); + ossaGetForensicDataCB(agRoot, agContext, status, forensicData); + return status; +} + +bit32 saGetIOErrorStats( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 flag + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t*)agRoot->sdkData; + bit32 status = AGSA_RC_SUCCESS; + + ossaGetIOErrorStatsCB(agRoot, agContext, status, &saRoot->IoErrorCount); + + if (flag) + { + /* clear IO error counter */ + si_memset(&saRoot->IoErrorCount, 0, sizeof(agsaIOErrorEventStats_t)); + } + + return status; +} + +bit32 saGetIOEventStats( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 flag + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t*)agRoot->sdkData; + bit32 status = AGSA_RC_SUCCESS; + + ossaGetIOEventStatsCB(agRoot, agContext, status, &saRoot->IoEventCount); + + if (flag) + { + /* clear IO event counter */ + si_memset(&saRoot->IoEventCount, 0, sizeof(agsaIOErrorEventStats_t)); + } + + return status; +} + +/******************************************************************************/ +/*! \brief Initiate a GET REGISTER DUMP command + * + * This function is called to Get Register Dump from the SPC. + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param agContext the context of this API + * \param queueNum queue number + * \param regDumpInfo register dump information + * + * \return + * - SUCCESS or FAILURE + */ +/*******************************************************************************/ +//GLOBAL bit32 saGetRegisterDump( +bit32 saGetRegisterDump( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaRegDumpInfo_t *regDumpInfo + ) +{ + agsaLLRoot_t *saRoot = agNULL; + bit32 ret = AGSA_RC_SUCCESS; +// bit32 value, value1; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"6p"); + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + + saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + /* sanity check */ + SA_ASSERT((agNULL != saRoot), ""); + + /* sanity check */ + SA_ASSERT((agNULL != regDumpInfo), ""); + + SA_DBG3(("saGetRegisterDump: agContext %p\n", agContext)); + + if (regDumpInfo->regDumpSrc > 3) + { + SA_DBG1(("saGetRegisterDump, regDumpSrc %d or regDumpNum %d invalid\n", + regDumpInfo->regDumpNum, regDumpInfo->regDumpNum)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "6p"); + /* CB error for Register Dump */ + ossaGetRegisterDumpCB(agRoot, agContext, OSSA_FAILURE); + return AGSA_RC_FAILURE; + } + + switch(regDumpInfo->regDumpSrc) + { + case REG_DUMP_NONFLASH: + /*First 6 64k data from GSMDUMP, contains IOST and RB info*/ + if (regDumpInfo->regDumpNum == GET_IOST_RB_INFO) + { + regDumpInfo->regDumpOffset = regDumpInfo->regDumpOffset + 0; + ret = siGSMDump(agRoot, regDumpInfo->regDumpOffset, regDumpInfo->directLen, regDumpInfo->directData); + /* CB error for Register Dump */ + ossaGetRegisterDumpCB(agRoot, agContext, ret); + return ret; + } + /* Last 1MB data from GSMDUMP, contains GSM_SM info*/ + + if (regDumpInfo->regDumpNum == GET_GSM_SM_INFO) + { + /* GSM_SM - total 1 Mbytes */ + bit32 offset; + if(smIS_SPC(agRoot)) + { + offset = regDumpInfo->regDumpOffset + SPC_GSM_SM_OFFSET; + }else if(smIS_SPCV(agRoot)) + { + offset = regDumpInfo->regDumpOffset + SPCV_GSM_SM_OFFSET; + } else + { + SA_DBG1(("saGetRegisterDump: the device type is not support\n")); + return AGSA_RC_FAILURE; + } + + ret = siGSMDump(agRoot, offset, regDumpInfo->directLen, regDumpInfo->directData); + /* CB error for Register Dump */ + ossaGetRegisterDumpCB(agRoot, agContext, ret); + return ret; + } + + /* check fatal errors */ + if(smIS_SPC(agRoot)) { + siSpcGetErrorContent(agRoot); + } + else if(smIS_SPCV(agRoot)) { + siSpcvGetErrorContent(agRoot); + } + /* Then read from local copy */ + if (regDumpInfo->directLen > REGISTER_DUMP_BUFF_SIZE) + { + SA_DBG1(("saGetRegisterDump, Request too many bytes %d\n", + regDumpInfo->directLen)); + regDumpInfo->directLen = REGISTER_DUMP_BUFF_SIZE; + } + + if (regDumpInfo->regDumpNum == 0) + { + /* Copy the LL Local register dump0 data to the destination */ + si_memcpy(regDumpInfo->directData, (bit8 *)&saRoot->registerDump0[0] + + regDumpInfo->regDumpOffset, regDumpInfo->directLen); + } + else if( regDumpInfo->regDumpNum == 1) + { + /* Copy the LL Local register dump1 data to the destination */ + si_memcpy(regDumpInfo->directData, (bit8 *)&saRoot->registerDump1[0] + + regDumpInfo->regDumpOffset, regDumpInfo->directLen); + } else { + SA_DBG1(("saGetRegisterDump, the regDumpNum value is wrong %x\n", + regDumpInfo->regDumpNum)); + } + + /* CB for Register Dump */ + ossaGetRegisterDumpCB(agRoot, agContext, OSSA_SUCCESS); + break; + + case REG_DUMP_FLASH: + /* build IOMB command and send to SPC */ + ret = mpiNVMReadRegDumpCmd(agRoot, agContext, queueNum, + regDumpInfo->regDumpNum, + regDumpInfo->regDumpOffset, + regDumpInfo->indirectAddrUpper32, + regDumpInfo->indirectAddrLower32, + regDumpInfo->indirectLen); + + break; + + default: + break; + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "6p"); + + return ret; +} + +/******************************************************************************/ +/*! \brief Initiate a GET REGISTER DUMP from GSM command + * + * This function is called to Get Register Dump from the GSM of SPC. + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param destinationAddress address of the register dump data copied to + * \param regDumpNum Register Dump # 0 or 1 + * \param regDumpOffset Offset within the register dump area + * \param len Length in bytes of the register dump data to copy + * + * \return + * - SUCCESS or FAILURE + */ +/*******************************************************************************/ +//GLOBAL bit32 siGetRegisterDumpGSM( +bit32 siGetRegisterDumpGSM( + agsaRoot_t *agRoot, + void *destinationAddress, + bit32 regDumpNum, + bit32 regDumpOffset, + bit32 len + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + bit32 ret = AGSA_RC_SUCCESS; + bit32 rDumpOffset, rDumpLen; //, rDumpValue; + bit8 *dst; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2V"); + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + + dst = (bit8 *)destinationAddress; + + if (regDumpNum > 1) + { + SA_DBG1(("siGetRegisterDump, regDumpNum %d is invalid\n", regDumpNum)); + return AGSA_RC_FAILURE; + } + + if (!regDumpNum) + { + rDumpOffset = saRoot->mainConfigTable.FatalErrorDumpOffset0; + rDumpLen = saRoot->mainConfigTable.FatalErrorDumpLength0; + } + else + { + rDumpOffset = saRoot->mainConfigTable.FatalErrorDumpOffset1; + rDumpLen = saRoot->mainConfigTable.FatalErrorDumpLength1; + } + + if (len > rDumpLen) + { + SA_DBG1(("siGetRegisterDump, Request too many bytes %d, rDumpLen %d\n", len, rDumpLen)); + len = rDumpLen; + } + + if (regDumpOffset >= len) + { + SA_DBG1(("siGetRegisterDump, Offset is not within the area %d, regDumpOffset%d\n", rDumpLen, regDumpOffset)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2V"); + return AGSA_RC_FAILURE; + } + + /* adjust length to dword boundary */ + if ((len % 4) > 0) + { + len = (len/4 + 1) * 4; + } + + ret = siGSMDump(agRoot, rDumpOffset, len, dst); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2V"); + + return ret; +} + +/******************************************************************************/ +/*! \brief SPC Get NVMD Command + * + * This command sends GET_NVMD_DATA Command to SPC. + * + * \param agRoot Handles for this instance of SAS/SATA LL + * \param agContext Context of SPC FW Flash Update Command + * \param queueNum Inbound/outbound queue number + * \param NVMDInfo Pointer of NVM Device information + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +//GLOBAL bit32 saGetNVMDCommand( +bit32 saGetNVMDCommand( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaNVMDData_t *NVMDInfo + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + + /* build IOMB command and send to SPC */ + ret = mpiGetNVMDCmd(agRoot, agContext, NVMDInfo, queueNum); + + return ret; +} + +/******************************************************************************/ +/*! \brief SPC Set NVMD Command + * + * This command sends SET_NVMD_DATA Command to SPC. + * + * \param agRoot Handles for this instance of SAS/SATA LL + * \param agContext Context of SPC FW Flash Update Command + * \param queueNum Inbound/outbound queue number + * \param NVMDInfo Pointer of NVM Device information + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +//GLOBAL bit32 saSetNVMDCommand( +bit32 saSetNVMDCommand( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaNVMDData_t *NVMDInfo + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + + /* build IOMB command and send to SPC */ + ret = mpiSetNVMDCmd(agRoot, agContext, NVMDInfo, queueNum); + + return ret; +} + + +GLOBAL bit32 saSendSMPIoctl( + agsaRoot_t *agRoot, + agsaDevHandle_t *agDevHandle, + bit32 queueNum, + agsaSMPFrame_t *pSMPFrame, + ossaSMPCompletedCB_t agCB + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + //bit32 IR_IP_OV_res_phyId_DPdLen_res = 0; + bit32 retVal; + bit8 inq, outq; + agsaIORequestDesc_t *pRequest; + void *pMessage; + bit8 *payload_ptr; + agsaDeviceDesc_t *pDevice; + bit8 using_reserved = agFALSE; + agsaPort_t *pPort; + mpiICQueue_t *circularQ; + agsaLLRoot_t *saRoot = agNULL; +// agsaDevHandle_t *agDevHandle; + + saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + SA_ASSERT((agNULL != saRoot), ""); + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + + + + /* Get request from free IO Requests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); /**/ + + /* If no LL IO request entry available */ + if ( agNULL == pRequest ) + { + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeReservedRequests)); + + if(agNULL != pRequest) + { + using_reserved = agTRUE; + SA_DBG1(("saSMPStart, using saRoot->freeReservedRequests\n")); + } + else + { + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saSMPStart, No request from free list Not using saRoot->freeReservedRequests\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "9a"); + return AGSA_RC_BUSY; + } + } + + inq = (bit8)(queueNum & MPI_IB_NUM_MASK); + outq = (bit8)((queueNum & MPI_OB_NUM_MASK) >> MPI_OB_SHIFT); + + + + + SA_ASSERT((agNULL != agDevHandle), ""); + /* Find the outgoing port for the device */ + if (agNULL == agDevHandle->sdkData) + { + /* Device has been removed */ + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saSMPStart, Device has been removed. agDevHandle=%p\n", agDevHandle)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "9a"); + return AGSA_RC_FAILURE; + } + + pDevice = (agsaDeviceDesc_t *) (agDevHandle->sdkData); + + pPort = pDevice->pPort; + + + + /* If free IOMB avaliable */ + /* Remove the request from free list */ + if( using_reserved ) + { + saLlistIORemove(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + + /* Add the request to the pendingSMPRequests list of the device */ + saLlistIOAdd(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + SA_ASSERT((!pRequest->valid), "The pRequest is in use"); + pRequest->valid = agTRUE; + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* set up pRequest */ + pRequest->pIORequestContext = (agsaIORequest_t *)pRequest; + pRequest->pDevice = pDevice; + pRequest->pPort = pPort; + pRequest->startTick = saRoot->timeTick; + pRequest->completionCB = (ossaSSPCompletedCB_t)agCB; + pRequest->requestType = AGSA_SMP_IOCTL_REQUEST; + + /* Set request to the sdkData of agIORequest */ + // agIORequest->sdkData = pRequest; + + /* save tag to IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedEnter(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + + /* If LL IO request entry avaliable */ + /* Get a free inbound queue entry */ + circularQ = &saRoot->inboundQueue[inq]; + retVal = mpiMsgFreeGet(circularQ, IOMB_SIZE64, &pMessage); + + if (AGSA_RC_FAILURE == retVal) + { +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + /* if not sending return to free list rare */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + pRequest->valid = agFALSE; + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("saSMPStart, error when get free IOMB\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "9a"); + return AGSA_RC_FAILURE; + } + + /* return busy if inbound queue is full */ + if (AGSA_RC_BUSY == retVal) + { +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + /* if not sending return to free list rare */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + pRequest->valid = agFALSE; + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("saSMPStart, no more IOMB\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "9a"); + return AGSA_RC_BUSY; + } +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + + + if(smIS_SPC(agRoot)) + { + agsaSMPCmd_t payload; + + + bit32 IR_IP_OV_res_phyId_DPdLen_res = 0; + /* Prepare the payload of IOMB */ + si_memset(&payload, 0, sizeof(agsaSMPCmd_V_t)); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPCmd_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPCmd_t, deviceId), pDevice->DeviceMapIndex); + + + + /*Indirect request and response*/ + if (smpFrameFlagIndirectResponse & pSMPFrame->flag && smpFrameFlagIndirectPayload & pSMPFrame->flag) /* */ + { + + SA_DBG2(("saSMPStart:V Indirect payload and indirect response\n")); + + /* Indirect Response mode */ + pRequest->IRmode = INDIRECT_MODE; + IR_IP_OV_res_phyId_DPdLen_res = 3; + + + /* payload */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPCmd_t, SMPCmd[4]), (pSMPFrame->outFrameAddrLower32)); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPCmd_t, SMPCmd[5]), (pSMPFrame->outFrameAddrUpper32)); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPCmd_t, SMPCmd[6]), (pSMPFrame->outFrameLen)); + + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPCmd_t, SMPCmd[8]), (pSMPFrame->inFrameAddrLower32)); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPCmd_t, SMPCmd[9]), (pSMPFrame->inFrameAddrUpper32)); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPCmd_t, SMPCmd[10]), (pSMPFrame->inFrameLen)); + + } + + + IR_IP_OV_res_phyId_DPdLen_res |= (pSMPFrame->flag & 3); + /* fatal error if missing */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPCmd_t, IR_IP_OV_res_phyId_DPdLen_res), IR_IP_OV_res_phyId_DPdLen_res); + /* fatal error if missing */ + + + /* check IR bit */ + + /* Build IOMB command and send it to SPC */ + payload_ptr = (bit8 *)&payload; +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedEnter(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + + ret = mpiSMPCmd(agRoot, pMessage, OPC_INB_SMP_REQUEST, (agsaSMPCmd_t *)payload_ptr, inq, outq); + +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + + + } + else /* IOMB is different for SPCV SMP */ + { + agsaSMPCmd_V_t vpayload; + + + bit32 IR_IP_OV_res_phyId_DPdLen_res = 0; + /* Prepare the payload of IOMB */ + si_memset(&vpayload, 0, sizeof(agsaSMPCmd_V_t)); + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t, deviceId), pDevice->DeviceMapIndex); + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,SMPHDR ), *((bit32*)pSMPFrame->outFrameBuf+0) ); + + /*Indirect request and response*/ + if (smpFrameFlagIndirectResponse & pSMPFrame->flag && smpFrameFlagIndirectPayload & pSMPFrame->flag) /* */ + { + + SA_DBG2(("saSMPStart:V Indirect payload and indirect response\n")); + + /* Indirect Response mode */ + pRequest->IRmode = INDIRECT_MODE; + IR_IP_OV_res_phyId_DPdLen_res = 3; + + + /* payload */ + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,IndirL_SMPRF15_12 ), (pSMPFrame->outFrameAddrLower32)); + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,IndirH_or_SMPRF19_16 ), (pSMPFrame->outFrameAddrUpper32)); + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,IndirLen_or_SMPRF23_20 ), (pSMPFrame->outFrameLen)); + + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,ISRAL_or_SMPRF31_28), (pSMPFrame->inFrameAddrLower32)); + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,ISRAH_or_SMPRF35_32), (pSMPFrame->inFrameAddrUpper32)); + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,ISRL_or_SMPRF39_36), (pSMPFrame->inFrameLen)); + + } + + /*Direct request and indirect response*/ + else if (smpFrameFlagIndirectResponse & pSMPFrame->flag ) /* */ + { + + SA_DBG2(("saSMPStart:V Direct payload and indirect response\n")); + IR_IP_OV_res_phyId_DPdLen_res = (pSMPFrame->outFrameLen << SHIFT16) | pSMPFrame->flag; + + + /* Write IR_IP_OV_res_phyId_DPdLen_res field in the payload*/ + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t, IR_IP_OV_res_phyId_DPdLen_res), IR_IP_OV_res_phyId_DPdLen_res); + /* setup indirect response frame address */ + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t, ISRAL_or_SMPRF31_28 ), (pSMPFrame->inFrameAddrLower32)); + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t, ISRAH_or_SMPRF35_32 ), (pSMPFrame->inFrameAddrUpper32)); + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t, ISRL_or_SMPRF39_36 ), (pSMPFrame->inFrameLen)); + + } + IR_IP_OV_res_phyId_DPdLen_res |= (pSMPFrame->flag & 3); + /* fatal error if missing */ + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t, IR_IP_OV_res_phyId_DPdLen_res), IR_IP_OV_res_phyId_DPdLen_res); + /* fatal error if missing */ + + + /* check IR bit */ + +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedEnter(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + /* Build IOMB command and send it to SPCv */ + payload_ptr = (bit8 *)&vpayload; + ret = mpiSMPCmd(agRoot, pMessage, OPC_INB_SMP_REQUEST, (agsaSMPCmd_t *)payload_ptr, inq, outq); + +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + + + } + + + return ret; +} + + +/******************************************************************************/ +/*! \brief Reconfiguration of SAS Parameters Command + * + * This command Reconfigure the SAS parameters to SPC. + * + * \param agRoot Handles for this instance of SAS/SATA LL + * \param agContext Context of SPC FW Flash Update Command + * \param queueNum Inbound/outbound queue number + * \param agSASConfig Pointer of SAS Configuration Parameters + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +//GLOBAL bit32 saReconfigSASParams( +bit32 saReconfigSASParams( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum , + agsaSASReconfig_t *agSASConfig + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + + if(smIS_SPCV(agRoot)) + { + SA_DBG1(("saReconfigSASParams: AGSA_RC_FAILURE for SPCv\n" )); + return(AGSA_RC_FAILURE); + } + + /* build IOMB command and send to SPC */ + ret = mpiSasReinitializeCmd(agRoot, agContext, agSASConfig, queueNum); + + return ret; +} + +/******************************************************************************/ +/*! \brief Dump GSM registers from the controller + * + * \param agRoot Handles for this instance of SAS/SATA hardware + * \param gsmDumpOffset Offset of GSM + * \param length Max is 1 MB + * \param directData address of GSM data dump to + * + * \return + * - \e AGSA_RC_SUCCESS saGSMDump is successfully + * - \e AGSA_RC_FAILURE saGSMDump is not successfully + * + */ +/*******************************************************************************/ +//LOCAL bit32 siGSMDump( +bit32 siGSMDump( + agsaRoot_t *agRoot, + bit32 gsmDumpOffset, + bit32 length, + void *directData) +{ + bit8 *dst; + bit32 value, rem, offset = 0; + bit32 i, workOffset, dwLength; + bit32 bar = 0; + + SA_DBG1(("siGSMDump: gsmDumpOffset 0x%x length 0x%x\n", gsmDumpOffset, length)); + + /* check max is 64k chunks */ + if (length > (64 * 1024)) + { + SA_DBG1(("siGSMDump: Max length is greater than 64K bytes 0x%x\n", length)); + return AGSA_RC_FAILURE; + } + + if (gsmDumpOffset & 3) + { + SA_DBG1(("siGSMDump: Not allow NON_DW Boundary 0x%x\n", gsmDumpOffset)); + return AGSA_RC_FAILURE; + } + + if ((gsmDumpOffset + length) > ONE_MEGABYTE) + { + SA_DBG1(("siGSMDump: Out of GSM end address boundary 0x%x\n", (gsmDumpOffset+length))); + return AGSA_RC_FAILURE; + } + + if( smIS_SPCV(agRoot)) + { + bar = PCIBAR1; + } + else if( smIS_SPC(agRoot)) + { + bar = PCIBAR2; + } + else + { + SA_DBG1(("siGSMDump: device type is not supported")); + return AGSA_RC_FAILURE; + } + + workOffset = gsmDumpOffset & 0xFFFF0000; + offset = gsmDumpOffset & 0x0000FFFF; + gsmDumpOffset = workOffset; + + dst = (bit8 *)directData; + + /* adjust length to dword boundary */ + rem = length & 3; + dwLength = length >> 2; + + for (i =0; i < dwLength; i++) + { + if((workOffset + offset) > length ) + { + break; + } + value = ossaHwRegReadExt(agRoot, bar, (workOffset + offset) & 0x0000FFFF); + /* xfr for dw */ + si_memcpy(dst, &value, 4); + dst += 4; + offset += 4; + } + + if (rem != 0) + { + value = ossaHwRegReadExt(agRoot, bar, (workOffset + offset) & 0x0000FFFF); + /* xfr for non_dw */ + if(dst) + { + si_memcpy(dst, &value, rem); + } + } + + /* Shift back to BAR4 original address */ + if (AGSA_RC_FAILURE == siBar4Shift(agRoot, 0x0)) + { + SA_DBG1(("siGSMDump:Shift Bar4 to 0x%x failed\n", 0x0)); + return AGSA_RC_FAILURE; + } + + return AGSA_RC_SUCCESS; +} + +//GLOBAL bit32 saPCIeDiagExecute( +bit32 saPCIeDiagExecute( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaPCIeDiagExecute_t *diag) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = agNULL; + agsaIORequestDesc_t *pRequest; + bit32 payload[32]; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"6r"); + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + + saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + /* sanity check */ + SA_ASSERT((agNULL != saRoot), ""); + SA_ASSERT((agNULL != diag), ""); + + if(diag->len == 0) + { + SA_DBG1(("saPCIeDiagExecute, diag->len Zero\n")); + } + SA_DBG1(("saPCIeDiagExecute, diag->command 0x%X\n", diag->command )); + SA_DBG1(("saPCIeDiagExecute, diag->flags 0x%X\n",diag->flags )); + SA_DBG1(("saPCIeDiagExecute, diag->initialIOSeed 0x%X\n", diag->initialIOSeed)); + SA_DBG1(("saPCIeDiagExecute, diag->reserved 0x%X\n",diag->reserved )); + SA_DBG1(("saPCIeDiagExecute, diag->rdAddrLower 0x%X\n", diag->rdAddrLower)); + SA_DBG1(("saPCIeDiagExecute, diag->rdAddrUpper 0x%X\n", diag->rdAddrUpper )); + SA_DBG1(("saPCIeDiagExecute, diag->wrAddrLower 0x%X\n", diag->wrAddrLower)); + SA_DBG1(("saPCIeDiagExecute, diag->wrAddrUpper 0x%X\n",diag->wrAddrUpper )); + SA_DBG1(("saPCIeDiagExecute, diag->len 0x%X\n",diag->len )); + SA_DBG1(("saPCIeDiagExecute, diag->pattern 0x%X\n",diag->pattern )); + SA_DBG1(("saPCIeDiagExecute, %02X %02X %02X %02X %02X %02X\n", + diag->udtArray[0], + diag->udtArray[1], + diag->udtArray[2], + diag->udtArray[3], + diag->udtArray[4], + diag->udtArray[5] )); + + SA_DBG1(("saPCIeDiagExecute, %02X %02X %02X %02X %02X %02X\n", + diag->udrtArray[0], + diag->udrtArray[1], + diag->udrtArray[2], + diag->udrtArray[3], + diag->udrtArray[4], + diag->udrtArray[5])); + + + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saPCIeDiagExecute, No request from free list\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "6r"); + return AGSA_RC_BUSY; + } + /* If LL Control request entry avaliable */ + /* Remove the request from free list */ + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* set payload to zeros */ + si_memset(&payload, 0, sizeof(payload)); + + if(smIS_SPCV(agRoot)) + { + bit32 UDTR1_UDT0 ,UDT5_UDT2,UDTR5_UDTR2; + + UDTR5_UDTR2 = (( diag->udrtArray[5] << SHIFT24) | (diag->udrtArray[4] << SHIFT16) | (diag->udrtArray[3] << SHIFT8) | diag->udrtArray[2]); + UDT5_UDT2 = (( diag->udtArray[5] << SHIFT24) | (diag->udtArray[4] << SHIFT16) | (diag->udtArray[3] << SHIFT8) | diag->udtArray[2]); + UDTR1_UDT0 = (( diag->udrtArray[1] << SHIFT24) | (diag->udrtArray[0] << SHIFT16) | (diag->udtArray[1] << SHIFT8) | diag->udtArray[0]); + + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaPCIeDiagExecuteCmd_t, tag) , pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaPCIeDiagExecuteCmd_t, CmdTypeDesc), diag->command ); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaPCIeDiagExecuteCmd_t, UUM_EDA) , diag->flags); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaPCIeDiagExecuteCmd_t, UDTR1_UDT0) , UDTR1_UDT0); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaPCIeDiagExecuteCmd_t, UDT5_UDT2) , UDT5_UDT2); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaPCIeDiagExecuteCmd_t, UDTR5_UDTR2), UDTR5_UDTR2); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaPCIeDiagExecuteCmd_t, Res_IOS) , diag->initialIOSeed); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaPCIeDiagExecuteCmd_t, rdAddrLower), diag->rdAddrLower); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaPCIeDiagExecuteCmd_t, rdAddrUpper), diag->rdAddrUpper); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaPCIeDiagExecuteCmd_t, wrAddrLower), diag->wrAddrLower); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaPCIeDiagExecuteCmd_t, wrAddrUpper), diag->wrAddrUpper); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaPCIeDiagExecuteCmd_t, len), diag->len); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaPCIeDiagExecuteCmd_t, pattern), diag->pattern); + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_PCIE_DIAG_EXECUTE, IOMB_SIZE128, queueNum); + } + else + { + /* build IOMB command and send to SPC */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsa_SPC_PCIDiagExecuteCmd_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsa_SPC_PCIDiagExecuteCmd_t, CmdTypeDesc), diag->command ); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsa_SPC_PCIDiagExecuteCmd_t, rdAddrLower), diag->rdAddrLower); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsa_SPC_PCIDiagExecuteCmd_t, rdAddrUpper), diag->rdAddrUpper); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsa_SPC_PCIDiagExecuteCmd_t, wrAddrLower), diag->wrAddrLower); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsa_SPC_PCIDiagExecuteCmd_t, wrAddrUpper), diag->wrAddrUpper); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsa_SPC_PCIDiagExecuteCmd_t, len), diag->len); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsa_SPC_PCIDiagExecuteCmd_t, pattern), diag->pattern); + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_PCIE_DIAG_EXECUTE, IOMB_SIZE64, queueNum); + } + + if (AGSA_RC_SUCCESS != ret) + { + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("saPCIeDiagExecute, sending IOMB failed\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "6r"); + + return ret; + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "6r"); + return ret; +} + +//GLOBAL bit32 saGetDFEData( +bit32 saGetDFEData( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 interface, + bit32 laneNumber, + bit32 interations, + agsaSgl_t *agSgl) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = agNULL; + agsaIORequestDesc_t *pRequest = agNULL; + bit32 payload[32]; + bit32 reserved_In_Ln; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2X"); + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + SA_ASSERT((agNULL != saRoot), ""); + SA_ASSERT((agNULL != agSgl), ""); + + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saGetDFEData, No request from free list\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2X"); + return AGSA_RC_BUSY; + } + /* If LL Control request entry avaliable */ + /* Remove the request from free list */ + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* set payload to zeros */ + si_memset(&payload, 0, sizeof(payload)); + + if(smIS_SPCV(agRoot)) + { + reserved_In_Ln = ((interface & 0x1) << SHIFT7) | (laneNumber & 0x7F); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetDDEFDataCmd_t, tag) , pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetDDEFDataCmd_t, reserved_In_Ln) , reserved_In_Ln); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetDDEFDataCmd_t, MCNT) , interations); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetDDEFDataCmd_t, Buf_AddrL) , agSgl->sgLower); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetDDEFDataCmd_t, Buf_AddrH) , agSgl->sgUpper); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetDDEFDataCmd_t, Buf_Len) , agSgl->len); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetDDEFDataCmd_t, E_reserved) , agSgl->extReserved); + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_GET_DFE_DATA, IOMB_SIZE128, queueNum); + + } + else + { + /* SPC does not support this command */ + ret = AGSA_RC_FAILURE; + } + + if (AGSA_RC_SUCCESS != ret) + { + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("saPCIeDiagExecute, sending IOMB failed\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2X"); + return ret; + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "2X"); + return ret; +} + diff --git a/sys/dev/pms/RefTisa/sallsdk/spc/sallist.h b/sys/dev/pms/RefTisa/sallsdk/spc/sallist.h new file mode 100644 index 000000000000..0203a64f6f65 --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/spc/sallist.h @@ -0,0 +1,443 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/*******************************************************************************/ +/*! \file sallist.h + * \brief The file contains link list manipulation helper routines + * + */ +/*******************************************************************************/ + +#ifndef __SALLIST_H__ +#define __SALLIST_H__ + + +/******************************************************************** +********************************************************************* +** DATA STRUCTURES +********************************************************************/ + +/** \brief Structure of Link Data + * + * link data, need to be included at the start (offset 0) + * of any strutures that are to be stored in the link list + * + */ +typedef struct _SALINK +{ + struct _SALINK *pNext; + struct _SALINK *pPrev; + + /* + ** for assertion purpose only + */ + struct _SALINK * pHead; /* track the link list the link is a member of */ + +} SALINK, * PSALINK; + +/** \brief Structure of Link List + * + * link list basic pointers + * + */ +typedef struct _SALINK_LIST +{ + PSALINK pHead; + bit32 Count; + + SALINK Head; /* allways one link to speed up insert and delete */ + +} SALINK_LIST, * PSALINK_LIST; + + +/******************************************************************** +********************************************************************* +** MACROS +********************************************************************/ + +/*! \def saLlistInitialize(pList) +* \brief saLlistInitialize macro +* +* use to initialize a Link List +*/ +/******************************************************************************* +******************************************************************************** +** +** MODULE NAME: saLlistInitialize +** +** PURPOSE: Initialize a link list. +** +** PARAMETERS: PSALINK_LIST OUT - Link list definition. +** +** SIDE EFFECTS & CAVEATS: +** +** ALGORITHM: +** +********************************************************************************/ +/*lint -emacro(613,saLlistInitialize) */ + +#define saLlistInitialize(pList) {(pList)->pHead = &((pList)->Head); \ + (pList)->pHead->pNext = (pList)->pHead; \ + (pList)->pHead->pPrev = (pList)->pHead; \ + (pList)->Count = 0; \ + } + +#define saLlistIOInitialize(pList){(pList)->pHead = &((pList)->Head); \ + (pList)->pHead->pNext = (pList)->pHead; \ + (pList)->pHead->pPrev = (pList)->pHead; \ + (pList)->Count = 0; \ + } +/*! \def saLlinkInitialize(pLink) +* \brief saLlinkInitialize macro +* +* use to initialize a Link +*/ +/******************************************************************************** +******************************************************************************** +** +** MODULE NAME: saLlinkInitialize +** +** PURPOSE: Initialize a link. +** This function should be used to initialize a new link before it +** is used in the linked list. This will initialize the link so +** the assertion will work +** +** PARAMETERS: PSALINK IN - Link to be initialized. +** +** SIDE EFFECTS & CAVEATS: +** +** ALGORITHM: +** +******************************************************************************** +*******************************************************************************/ + +/*lint -emacro(613,saLlinkInitialize) */ + +#define saLlinkInitialize(pLink) { (pLink)->pHead = agNULL; \ + (pLink)->pNext = agNULL; \ + (pLink)->pPrev = agNULL; \ + } + +#define saLlinkIOInitialize(pLink) { (pLink)->pHead = agNULL; \ + (pLink)->pNext = agNULL; \ + (pLink)->pPrev = agNULL; \ + } +/*! \def saLlistAdd(pList, pLink) +* \brief saLlistAdd macro +* +* use to add a link to the tail of list +*/ +/******************************************************************************** +******************************************************************************** +** +** MODULE NAME: saLlistAdd +** +** PURPOSE: add a link at the tail of the list +** +** PARAMETERS: PSALINK_LIST OUT - Link list definition. +** PSALINK IN - Link to be inserted. +** +** SIDE EFFECTS & CAVEATS: +** !!! assumes that fcllistInitialize has been called on the linklist +** !!! if not, this function behavior is un-predictable +** +** The OS_ASSERT() is an assignment for debug code only +** +** ALGORITHM: +** +******************************************************************************** +*******************************************************************************/ + +/*lint -emacro(506,saLlistAdd) */ +/*lint -emacro(613,saLlistAdd) */ +/*lint -emacro(666,saLlistAdd) */ +/*lint -emacro(720,saLlistAdd) */ + +#define saLlistAdd(pList, pLink) { \ + (pLink)->pNext = (pList)->pHead; \ + (pLink)->pPrev = (pList)->pHead->pPrev; \ + (pLink)->pPrev->pNext = (pLink); \ + (pList)->pHead->pPrev = (pLink); \ + (pList)->Count ++; \ + (pLink)->pHead = (pList)->pHead; \ + } + +#define saLlistIOAdd(pList, pLink) { \ + (pLink)->pNext = (pList)->pHead; \ + (pLink)->pPrev = (pList)->pHead->pPrev; \ + (pLink)->pPrev->pNext = (pLink); \ + (pList)->pHead->pPrev = (pLink); \ + (pList)->Count ++; \ + (pLink)->pHead = (pList)->pHead; \ + } + +/*! \def saLlistInsert(pList, pLink, pNew) +* \brief saLlistInsert macro +* +* use to insert a link preceding the given one +*/ +/******************************************************************************** +******************************************************************************** +** +** MODULE NAME: saLlistInsert +** +** PURPOSE: insert a link preceding the given one +** +** PARAMETERS: PSALINK_LIST OUT - Link list definition. +** PSALINK IN - Link to be inserted after. +** PSALINK IN - Link to be inserted. +** +** SIDE EFFECTS & CAVEATS: +** !!! assumes that fcllistInitialize has been called on the linklist +** !!! if not, this function behavior is un-predictable +** +** The OS_ASSERT() is an assignment for debug code only +** +** ALGORITHM: +** +******************************************************************************** +*******************************************************************************/ + +/*lint -emacro(506,saLlistInsert) */ +/*lint -emacro(613,saLlistInsert) */ +/*lint -emacro(666,saLlistInsert) */ +/*lint -emacro(720,saLlistInsert) */ + +#define saLlistInsert(pList, pLink, pNew) { \ + (pNew)->pNext = (pLink); \ + (pNew)->pPrev = (pLink)->pPrev; \ + (pNew)->pPrev->pNext = (pNew); \ + (pLink)->pPrev = (pNew); \ + (pList)->Count ++; \ + (pNew)->pHead = (pList)->pHead; \ + } + +/*! \def saLlistRemove(pList, pLink) +* \brief saLlistRemove macro +* +* use to remove the link from the list +*/ +/******************************************************************************** +******************************************************************************** +** +** MODULE NAME: saLlistRemove +** +** PURPOSE: remove the link from the list. +** +** PARAMETERS: PSALINK_LIST OUT - Link list definition. +** PSALINK IN - Link to delet from list +** +** SIDE EFFECTS & CAVEATS: +** !!! assumes that fcllistInitialize has been called on the linklist +** !!! if not, this function behavior is un-predictable +** +** !!! No validation is made on the list or the validity of the link +** !!! the caller must make sure that the link is in the list +** +** +** ALGORITHM: +** +******************************************************************************** +*******************************************************************************/ + +/*lint -emacro(506,saLlistRemove) */ +/*lint -emacro(613,saLlistRemove) */ +/*lint -emacro(666,saLlistRemove) */ +/*lint -emacro(720,saLlistRemove) */ + +#define saLlistRemove(pList, pLink) { \ + (pLink)->pPrev->pNext = (pLink)->pNext; \ + (pLink)->pNext->pPrev = (pLink)->pPrev; \ + (pLink)->pHead = agNULL; \ + (pList)->Count --; \ + } + +#define saLlistIORemove(pList, pLink) { \ + (pLink)->pPrev->pNext = (pLink)->pNext; \ + (pLink)->pNext->pPrev = (pLink)->pPrev; \ + (pLink)->pHead = agNULL; \ + (pList)->Count --; \ + } +/*! \def saLlistGetHead(pList) +* \brief saLlistGetHead macro +* +* use to get the link following the head link +*/ +/******************************************************************************** +******************************************************************************** +** +** MODULE NAME: saLlistGetHead +** +** PURPOSE: get the link following the head link. +** +** PARAMETERS: PSALINK_LIST OUT - Link list definition. +** RETURNS - PSALINK the link following the head +** agNULL if the following link is the head +** +** SIDE EFFECTS & CAVEATS: +** !!! assumes that fcllistInitialize has been called on the linklist +** !!! if not, this function behavior is un-predictable +** +** ALGORITHM: +** +******************************************************************************** +*******************************************************************************/ +#define saLlistGetHead(pList) saLlistGetNext(pList,(pList)->pHead) + +#define saLlistIOGetHead(pList) saLlistGetNext(pList,(pList)->pHead) + +/*! \def saLlistGetTail(pList) +* \brief saLlistGetTail macro +* +* use to get the link preceding the tail link +*/ +/******************************************************************************** +******************************************************************************** +** +** MODULE NAME: saLlistGetTail +** +** PURPOSE: get the link preceding the tail link. +** +** PARAMETERS: PSALINK_LIST OUT - Link list definition. +** RETURNS - PSALINK the link preceding the head +** agNULL if the preceding link is the head +** +** SIDE EFFECTS & CAVEATS: +** +** ALGORITHM: +** +******************************************************************************** +*******************************************************************************/ +#define saLlistGetTail(pList) saLlistGetPrev((pList), (pList)->pHead) + +/*! \def saLlistGetCount(pList) +* \brief saLlistGetCount macro +* +* use to get the number of links in the list excluding head and tail +*/ +/******************************************************************************** +******************************************************************************** +** +** MODULE NAME: saLlistGetCount +** +** PURPOSE: get the number of links in the list excluding head and tail. +** +** PARAMETERS: PSALINK_LIST OUT - Link list definition. +** +** SIDE EFFECTS & CAVEATS: +** !!! assumes that fcllistInitialize has been called on the linklist +** !!! if not, this function behavior is un-predictable +** +** ALGORITHM: +** +******************************************************************************** +*******************************************************************************/ + +/*lint -emacro(613,saLlistGetCount) */ +/*lint -emacro(666,saLlistGetCount) */ + +#define saLlistGetCount(pList) ((pList)->Count) + +#define saLlistIOGetCount(pList) ((pList)->Count) + +/*! \def saLlistGetNext(pList, pLink) +* \brief saLlistGetNext macro +* +* use to get the next link in the list +*/ +/******************************************************************************** +******************************************************************************** +** +** MODULE NAME: saLlistGetNext +** +** PURPOSE: get the next link in the list. (one toward tail) +** +** PARAMETERS: PSALINK_LIST OUT - Link list definition. +** PSALINK IN - Link to get next to +** +** return PLINK - points to next link +** agNULL if next link is head +** +** SIDE EFFECTS & CAVEATS: +** !!! assumes that fcllistInitialize has been called on the linklist +** !!! if not, this function behavior is un-predictable +** +** !!! No validation is made on the list or the validity of the link +** !!! the caller must make sure that the link is in the list +** +** ALGORITHM: +** +******************************************************************************** +*******************************************************************************/ + +/*lint -emacro(613,saLlistGetNext) */ + +#define saLlistGetNext(pList, pLink) (((pLink)->pNext == (pList)->pHead) ? \ + agNULL : (pLink)->pNext) + +#define saLlistIOGetNext(pList, pLink) (((pLink)->pNext == (pList)->pHead) ? \ + agNULL : (pLink)->pNext) + +/*! \def saLlistGetPrev(pList, pLink) +* \brief saLlistGetPrev macro +* +* use to get the previous link in the list +*/ +/******************************************************************************** +******************************************************************************** +** +** MODULE NAME: saLlistGetPrev +** +** PURPOSE: get the previous link in the list. (one toward head) +** +** PARAMETERS: PSALINK_LIST OUT - Link list definition. +** PSALINK IN - Link to get prev to +** +** return PLINK - points to previous link +** agNULL if previous link is head +** +** SIDE EFFECTS & CAVEATS: +** !!! assumes that fcllistInitialize has been called on the linklist +** !!! if not, this function behavior is un-predictable +** +** !!! No validation is made on the list or the validity of the link +** !!! the caller must make sure that the link is in the list +** +** ALGORITHM: +** +******************************************************************************** +*******************************************************************************/ + +/*lint -emacro(613,saLlistGetPrev) */ + +#define saLlistGetPrev(pList, pLink) (((pLink)->pPrev == (pList)->pHead) ? \ + agNULL : (pLink)->pPrev) + + + +#define agObjectBase(baseType,fieldName,fieldPtr) \ + (void * ) fieldPtr == (void *) 0 ? (baseType *) 0 : \ + ((baseType *)((bit8 *)(fieldPtr) - ((bitptr)(&(((baseType *)0)->fieldName))))) + + +#endif /* #ifndef __SALLIST_H__*/ diff --git a/sys/dev/pms/RefTisa/sallsdk/spc/samacro.h b/sys/dev/pms/RefTisa/sallsdk/spc/samacro.h new file mode 100644 index 000000000000..4af84c75857c --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/spc/samacro.h @@ -0,0 +1,301 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/*******************************************************************************/ + +/*! \file samacro.h + * \brief The file defines macros used in LL sTSDK + */ + +/*******************************************************************************/ + +#ifndef __SAMACRO_H__ +#define __SAMACRO_H__ + +#if defined(SALLSDK_DEBUG) +#define MPI_IBQ_IOMB_LOG_ENABLE +#define MPI_OBQ_IOMB_LOG_ENABLE +#endif + +/*! \def MIN(a,b) +* \brief MIN macro +* +* use to find MIN of two values +*/ +#ifndef MIN +#define MIN(a,b) ((a) < (b) ? (a) : (b)) +#endif + +/*! \def MAX(a,b) +* \brief MAX macro +* +* use to find MAX of two values +*/ +#ifndef MAX +#define MAX(a,b) ((a) < (b) ? (b) : (a)) +#endif + +/************************************************************************************************* + * define Phy status macros * + *************************************************************************************************/ +/*! \def PHY_STATUS_SET(pPhy, value) +* \brief PHY_STATUS_SET macro +* +* use to set phy status +*/ +#define PHY_STATUS_SET(pPhy, value) ((pPhy)->status = (((pPhy)->status & 0xFFFF0000) | (value))) + +/*! \def PHY_STATUS_CHECK(pPhy, value) +* \brief PHY_STATUS_CHECK macro +* +* use to check phy status +*/ +#define PHY_STATUS_CHECK(pPhy, value) ( ((pPhy)->status & 0x0000FFFF) == (value) ) + + +/************************************************************************************ + * define CBUFFER operation macros * + ************************************************************************************/ +/*! \def AGSAMEM_ELEMENT_READ(pMem, index) +* \brief AGSAMEM_ELEMENT_READ macro +* +* use to read an element of a memory array +*/ +#define AGSAMEM_ELEMENT_READ(pMem, index) (((bit8 *)(pMem)->virtPtr) + (pMem)->singleElementLength * (index)) + +/************************************************************************************ + * define Chip ID macro * + ************************************************************************************/ + +#define SA_TREAT_SFC_AS_SPC + +#ifdef SA_TREAT_SFC_AS_SPC +#define SA_SFC_AS_SPC 1 +#define SA_SFC_AS_SPCV 0 +#else /* TREAT_SFC_AS_SPCv */ +#define SA_SFC_AS_SPC 0 +#define SA_SFC_AS_SPCV 1 +#endif /* SA_TREAT_SFC_AS_SPC */ + +#define IS_SDKDATA(agr) (((agr)->sdkData != agNULL ) ? 1 : 0) /* returns true if sdkdata is available */ + +#define smIsCfgSpcREV_A(agr) (8 ==( ossaHwRegReadConfig32((agr), 8 ) & 0xF) ? 1 : 0) /* returns true config space read is REVA */ +#define smIsCfgSpcREV_B(agr) (4 ==( ossaHwRegReadConfig32((agr), 8 ) & 0xF) ? 1 : 0) /* returns true config space read is REVB */ +#define smIsCfgSpcREV_C(agr) (5 ==( ossaHwRegReadConfig32((agr), 8 ) & 0xF) ? 1 : 0) /* returns true config space read is REVC */ + +#define smIsCfgVREV_A(agr) (4 ==( ossaHwRegReadConfig32((agr), 8 ) & 0xF) ? 1 : 0) /* returns true config space read is REVA */ +#define smIsCfgVREV_B(agr) (5 ==( ossaHwRegReadConfig32((agr), 8 ) & 0xF) ? 1 : 0) /* returns true config space read is REVB */ +#define smIsCfgVREV_C(agr) (6 ==( ossaHwRegReadConfig32((agr), 8 ) & 0xF) ? 1 : 0) /* returns true config space read is REVC */ + +#define smIsCfg8001(agr) (VEN_DEV_SPC == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC */ +#define smIsCfg8081(agr) (VEN_DEV_HIL == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000 ) ? 1 : 0) /* returns true config space read is Hialeah */ + +#define smIsCfg_V8025(agr) (VEN_DEV_SFC == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SFC */ + +#define smIsCfg_V8008(agr) (VEN_DEV_SPCV == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCv */ +#define smIsCfg_V8009(agr) (VEN_DEV_SPCVE == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCv */ +#define smIsCfg_V8018(agr) (VEN_DEV_SPCVP == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCv */ +#define smIsCfg_V8019(agr) (VEN_DEV_SPCVEP== (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCv */ + +#define smIsCfg_V8088(agr) (VEN_DEV_ADAPVP == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCv */ +#define smIsCfg_V8089(agr) (VEN_DEV_ADAPVEP== (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCv */ + +#define smIsCfg_V8070(agr) (VEN_DEV_SPC12V == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12v */ +#define smIsCfg_V8071(agr) (VEN_DEV_SPC12VE == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12v */ +#define smIsCfg_V8072(agr) (VEN_DEV_SPC12VP == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12v */ +#define smIsCfg_V8073(agr) (VEN_DEV_SPC12VEP== (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12v */ + +#define smIsCfg_V8074(agr) (VEN_DEV_SPC12ADP == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is Adaptec SPC12v */ +#define smIsCfg_V8075(agr) (VEN_DEV_SPC12ADPE == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is Adaptec SPC12v */ +#define smIsCfg_V8076(agr) (VEN_DEV_SPC12ADPP == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is Adaptec SPC12v */ +#define smIsCfg_V8077(agr) (VEN_DEV_SPC12ADPEP == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is Adaptec SPC12v */ +#define smIsCfg_V8006(agr) (VEN_DEV_SPC12SATA == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is Adaptec SPC12v */ +#define smIsCfg_V9015(agr) (VEN_DEV_9015 == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12v */ +#define smIsCfg_V9060(agr) (VEN_DEV_9060 == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12v */ + +#define smIsCfg_SPC_ANY(agr) ((smIsCfg8001((agr)) == 1) ? 1 : \ + (smIsCfg8081((agr)) == 1) ? 1 : \ + (smIsCfg_V8025((agr)) == 1) ? SA_SFC_AS_SPC : 0) + +#define smIS_SPCV8008(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPCV ) ? 1 : 0) : smIsCfg_V8008((agr))) +#define smIS_SPCV8009(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPCVE) ? 1 : 0) : smIsCfg_V8009((agr))) +#define smIS_SPCV8018(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPCVP) ? 1 : 0) : smIsCfg_V8018((agr))) +#define smIS_SPCV8019(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPCVEP) ? 1 : 0) : smIsCfg_V8019((agr))) +#define smIS_ADAP8088(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_ADAPVP) ? 1 : 0) : smIsCfg_V8088((agr))) +#define smIS_ADAP8089(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_ADAPVEP)? 1 : 0): smIsCfg_V8089((agr))) + +#define smIS_SPCV8070(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12V ) ? 1 : 0) : smIsCfg_V8070((agr))) +#define smIS_SPCV8071(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12VE) ? 1 : 0) : smIsCfg_V8071((agr))) +#define smIS_SPCV8072(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12VP) ? 1 : 0) : smIsCfg_V8072((agr))) +#define smIS_SPCV8073(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12VEP)? 1 : 0) : smIsCfg_V8073((agr))) + +#define smIS_SPCV8074(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12ADP ) ? 1 : 0) : smIsCfg_V8074((agr))) +#define smIS_SPCV8075(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12ADPE) ? 1 : 0) : smIsCfg_V8075((agr))) +#define smIS_SPCV8076(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12ADPP) ? 1 : 0) : smIsCfg_V8076((agr))) +#define smIS_SPCV8077(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12ADPEP)? 1 : 0) : smIsCfg_V8077((agr))) +#define smIS_SPCV8006(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12SATA) ? 1 : 0) : smIsCfg_V8006((agr))) +#define smIS_SPCV9015(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_9015) ? 1 : 0) : smIsCfg_V9015((agr))) +#define smIS_SPCV9060(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_9060) ? 1 : 0) : smIsCfg_V9060((agr))) + +#define smIS_SPCV8025(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SFC ) ? 1 : 0) : smIsCfg_V8025((agr))) + +#define smIS_SFC(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SFC ) ? 1 : 0) : smIsCfg_V8025((agr))) +#define smIS_spc8001(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC ) ? 1 : 0) : smIsCfg8001((agr))) +#define smIS_spc8081(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_HIL ) ? 1 : 0) : smIsCfg8081((agr))) + + + +#define smIS_SFC_AS_SPC(agr) ((smIS_SFC((agr)) == 1) ? SA_SFC_AS_SPC : 0 ) + +#define smIS_SFC_AS_V(agr) ((smIS_SFC((agr)) == 1 )? SA_SFC_AS_SPCV : 0 ) + +/* Use 64 bit interrupts for SPCv, before getting saroot. Once saroot available only use 64bit when needed */ +#define smIS64bInt(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->Use64bit) ? 1 : 0) : smIS_SPCV(agr)) + +#define WHATTABLE(agr) \ +( \ +IS_SDKDATA((agr)) ? \ + (smIS_SPC((agr)) ? &SPCTable[0] : (smIS_SPCV((agr)) ? &SPC_V_Table[0] : agNULL ) ) \ +: \ + (smIsCfg_SPC_ANY((agr)) ? &SPCTable[0] : (smIsCfg_V_ANY((agr)) ? &SPC_V_Table[0] : agNULL ) ) \ +) \ + +#if defined(SALLSDK_DEBUG) +/* +* for debugging purposes. +*/ +extern bit32 gLLDebugLevel; + +#define SA_DBG0(format) ossaLogDebugString(gLLDebugLevel, 0, format) +#define SA_DBG1(format) ossaLogDebugString(gLLDebugLevel, 1, format) +#define SA_DBG2(format) ossaLogDebugString(gLLDebugLevel, 2, format) +#define SA_DBG3(format) ossaLogDebugString(gLLDebugLevel, 3, format) +#define SA_DBG4(format) ossaLogDebugString(gLLDebugLevel, 4, format) +#define SA_DBG5(format) ossaLogDebugString(gLLDebugLevel, 5, format) +#define SA_DBG6(format) ossaLogDebugString(gLLDebugLevel, 6, format) + +#else + +#define SA_DBG0(format) +#define SA_DBG1(format) +#define SA_DBG2(format) +#define SA_DBG3(format) +#define SA_DBG4(format) +#define SA_DBG5(format) +#define SA_DBG6(format) + +#endif + +#define SA_ASSERT OS_ASSERT + +typedef enum siPrintType_e +{ + SA_8, + SA_16, + SA_32 +} siPrintType; + +#if defined(SALLSDK_DEBUG) +#define SA_PRINTBUF(lDebugLevel,lWidth,pHeader,pBuffer,lLength) siPrintBuffer(lDebugLevel,lWidth,pHeader,pBuffer,lLength) +#else +#define SA_PRINTBUF(lDebugLevel,lWidth,pHeader,pBuffer,lLength) +#endif + +#ifdef SALLSDK_DEBUG + +#define DBG_DUMP_SSPSTART_CMDIU(agDevHandle,agRequestType,agRequestBody) siDumpSSPStartIu(agDevHandle,agRequestType,agRequestBody) + +#else + +#define DBG_DUMP_SSPSTART_CMDIU(agDevHandle,agRequestType,agRequestBody) + +#endif + +#ifdef MPI_DEBUG_TRACE_ENABLE +#define MPI_DEBUG_TRACE_ENTER_LOCK ossaSingleThreadedEnter(agRoot, LL_IOMB_TRACE_LOCK); +#define MPI_DEBUG_TRACE_LEAVE_LOCK ossaSingleThreadedLeave(agRoot, LL_IOMB_TRACE_LOCK); + +#define MPI_DEBUG_TRACE( queue, pici, ib,iomb,count) \ + MPI_DEBUG_TRACE_ENTER_LOCK \ + mpiTraceAdd( (queue), (pici),(ib), (iomb), (count)); \ + MPI_DEBUG_TRACE_LEAVE_LOCK +#else +#define MPI_DEBUG_TRACE( queue, pici, ib,iomb,count) +#endif /* MPI_DEBUG_TRACE_ENABLE */ + +#ifdef MPI_IBQ_IOMB_LOG_ENABLE +#define MPI_IBQ_IOMB_LOG(qNumber, msgHeader, msgLength) \ +do \ +{ \ + bit32 i; \ + SA_DBG3(("\n")); \ + SA_DBG3(("mpiMsgProduce: IBQ %d\n", (qNumber))); \ + for (i = 0; i < msgLength/16; i++) \ + { \ + SA_DBG3(("Inb: DW %02d 0x%08x 0x%08x 0x%08x 0x%08x\n", i*4, *((bit32 *)msgHeader+(i*4)), \ + *((bit32 *)msgHeader+(i*4)+1), *((bit32 *)msgHeader+(i*4)+2), \ + *((bit32 *)msgHeader+(i*4)+3))); \ + } \ +} while(0) +#endif +#ifdef MPI_OBQ_IOMB_LOG_ENABLE +#define MPI_OBQ_IOMB_LOG(qNumber, msgHeader, msgLength) \ +do \ +{ \ + bit32 i; \ + SA_DBG3(("\n")); \ + SA_DBG3(("mpiMsgConsume: OBQ %d\n", qNumber)); \ + for (i = 0; i < msgLength/16; i++) \ + { \ + SA_DBG3(("Out: DW %02d 0x%08x 0x%08x 0x%08x 0x%08x\n", i*4, *((bit32 *)msgHeader+(i*4)), \ + *((bit32 *)msgHeader+(i*4)+1), *((bit32 *)msgHeader+(i*4)+2), \ + *((bit32 *)msgHeader+(i*4)+3))); \ + } \ +} while(0) +#endif + + +/************************************************************************************ + * Wait X Second * + ************************************************************************************/ + +#define WAIT_SECONDS(x) ((x) * 1000 * 1000 ) +#define ONE_HUNDRED_MILLISECS (100 * 1000) /* 100,000 microseconds */ + +#define WAIT_INCREMENT_DEFAULT 1000 +#define WAIT_INCREMENT (IS_SDKDATA(agRoot) ? ( ((agsaLLRoot_t *)(agRoot->sdkData))->minStallusecs ) : WAIT_INCREMENT_DEFAULT ) +// (((agsaLLRoot_t *)(agRoot->sdkData))->minStallusecs) + + +#define MAKE_MODULO(a,b) (((a) % (b)) ? ((a) - ((a) % (b))) : (a)) + + +#define HDA_STEP_2 1 +#define HDA_STEP_3 1 +#define HDA_STEP_4 1 +#define HDA_STEP_5 1 +#define HDA_STEP_6 1 +#define HDA_STEP_7 1 +#define HDA_STEP_8 1 + +#endif /* __SAMACRO_H__ */ diff --git a/sys/dev/pms/RefTisa/sallsdk/spc/sampicmd.c b/sys/dev/pms/RefTisa/sallsdk/spc/sampicmd.c new file mode 100644 index 000000000000..ab3712938f67 --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/spc/sampicmd.c @@ -0,0 +1,2938 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +/*******************************************************************************/ +/*! \file sampicmd.c + * \brief The file implements the functions of MPI Inbound IOMB/Command to SPC + * + */ +/******************************************************************************/ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#ifdef SA_ENABLE_TRACE_FUNCTIONS +#ifdef siTraceFileID +#undef siTraceFileID +#endif +#define siTraceFileID 'I' +#endif + +/******************************************************************************/ +/*! \brief SAS/SATA LL API ECHO Command + * + * This command used to test that MPI between host and SPC IOP is operational. + * + * \param agRoot Handles for this instance of SAS/SATA hardware + * \param agContext Context of SPC FW Flash Update Command + * \param queueNum Inbound/outbound queue number + * \param echoPayload Pointer of Echo payload of IOMB + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_BUSY the SPC is no resource, cannot send now + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 saEchoCommand( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + void *echoPayload +) +{ + bit32 ret = AGSA_RC_SUCCESS; + + smTraceFuncEnter(hpDBG_VERY_LOUD, "xa"); + + /* setup IOMB payload */ + ret = mpiEchoCmd(agRoot, queueNum, agContext, echoPayload); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "xa"); + + return ret; +} + +/******************************************************************************/ +/*! \brief Build a IOMB command and send to SPC + * + * Build an IOMB if there is a free message buffer and Send it to SPC + * + * \param agRoot Handles for this instance of SAS/SATA hardware + * \param payload Pointer of payload in the IOMB + * \param category Category of IOMB + * \param opcode Opcode of IOMB + * \param size Size of IOMB + * \param queueNum Inbound/outbound queue number + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_BUSY the SPC is no resource, cannot send now + * - \e AGSA_RC_FAILURE the MPI command is failure + */ +/*******************************************************************************/ +GLOBAL bit32 mpiBuildCmd( + agsaRoot_t *agRoot, + bit32 *payload, + mpiMsgCategory_t category, + bit16 opcode, + bit16 size, + bit32 queueNum + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + mpiICQueue_t *circularQ; + void *pMessage; + bit32 ret = AGSA_RC_SUCCESS; + bit32 retVal; + bit8 inq, outq; + + smTraceFuncEnter(hpDBG_VERY_LOUD, "xb"); + + inq = (bit8)(queueNum & MPI_IB_NUM_MASK); + outq = (bit8)((queueNum & MPI_OB_NUM_MASK) >> MPI_OB_SHIFT); + SA_ASSERT((AGSA_MAX_INBOUND_Q > inq), "The IBQ Number is out of range."); + SA_ASSERT((AGSA_MAX_OUTBOUND_Q > outq), "The OBQ Number is out of range."); + +#ifdef SA_USE_MAX_Q + outq = saRoot->QueueConfig.numOutboundQueues -1; + SA_DBG1(("mpiBuildCmd, set OBQ to %d\n",outq)); +#endif /* SA_USE_MAX_Q */ + /* get a free inbound queue entry */ + +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedEnter(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + + circularQ = &saRoot->inboundQueue[inq]; + retVal = mpiMsgFreeGet(circularQ, size, &pMessage); + + /* return FAILURE if error happened */ + if (AGSA_RC_FAILURE == retVal) + { +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + /* the message size exceeds the inbound queue message size */ + SA_DBG1(("mpiBuildCmd, failure\n")); + ret = AGSA_RC_FAILURE; + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "xb"); + return ret; + } + + /* return BUSY if no more inbound queue entry available */ + if (AGSA_RC_BUSY == retVal) + { + SA_DBG1(("mpiBuildCmd, no more IOMB\n")); + ret = AGSA_RC_BUSY; + } + else + { + /* copy payload if it is necessary */ + if (agNULL != payload) + { + si_memcpy(pMessage, payload, (size - sizeof(mpiMsgHeader_t))); + } + + /* post the message to SPC */ + if (AGSA_RC_FAILURE == mpiMsgProduce(circularQ, (void *)pMessage, category, opcode, outq, (bit8)circularQ->priority)) + { + ret = AGSA_RC_FAILURE; + } + } + +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "xb"); + return ret; +} + +/******************************************************************************/ +/*! \brief SPC MPI ECHO Command + * + * This command used to test that MPI between host and SPC IOP is operational. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param queueNum Inbound/outbound queue number + * \param tag Tag of this IOMB + * \param echoPayload Pointer to the ECHO payload of inbound IOMB + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_BUSY the SPC is no resource, cannot send now + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiEchoCmd( + agsaRoot_t *agRoot, + bit32 queueNum, + agsaContext_t *agContext, + void *echoPayload + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaEchoCmd_t payload; + + smTraceFuncEnter(hpDBG_VERY_LOUD, "xc"); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* Get request from free IORequests */ + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("mpiEchoCmd, No request from free list\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "xc"); + return AGSA_RC_BUSY; + } + /* If LL Control request entry avaliable */ + else + { + /* Remove the request from free list */ + SA_ASSERT((!pRequest->valid), "The pRequest is in use"); + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + + /* build IOMB command and send to SPC */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaEchoCmd_t, tag), pRequest->HTag); + /* copy Echo payload */ + si_memcpy(&payload.payload[0], echoPayload, (sizeof(agsaEchoCmd_t) - 4)); + /* build IOMB command and send to SPC */ + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_ECHO, IOMB_SIZE64, queueNum); + SA_DBG3(("mpiEchoCmd, return value = %d\n", ret)); + if (AGSA_RC_SUCCESS != ret) + { + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("mpiEchoCmd, sending IOMB failed\n" )); + } +#ifdef SALL_API_TEST + else + { + saRoot->LLCounters.IOCounter.numEchoSent++; + } +#endif + + } + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "xc"); + return ret; +} + + +/******************************************************************************/ +/*! \brief Get Phy Profile Command SPCv + * + * This command is get # of phys and support speeds from SPCV. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param agDevHandle Handle of device + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_BUSY the SPC is no resource, cannot send now + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ + + +GLOBAL bit32 mpiGetPhyProfileCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 Operation, + bit32 PhyId, + void *agCB + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + bit32 ret = AGSA_RC_SUCCESS; + agsaGetPhyProfileCmd_V_t payload; + + smTraceFuncEnter(hpDBG_VERY_LOUD, "xd"); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* Get request from free IORequests */ + pRequest = (agsaIORequestDesc_t *)saLlistGetHead(&(saRoot->freeIORequests)); + + SA_DBG1(("mpiGetPhyProfileCmd, Operation 0x%x PhyId %d \n",Operation ,PhyId )); + + /* If no LL Control request entry avalibale */ + if ( agNULL == pRequest ) + { + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("mpiGetPhyProfileCmd, No request from free list\n" )); + return AGSA_RC_BUSY; + } + /* If LL Control request entry avaliable */ + else + { + SA_ASSERT((!pRequest->valid), "The pRequest is in use"); + + /* Remove the request from free list */ + saLlistRemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + + pRequest->valid = agTRUE; + pRequest->completionCB = agCB; + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + + /* set payload to zeros */ + si_memset(&payload, 0, sizeof(agsaGetPhyProfileCmd_V_t)); + + /* set tag field */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetPhyProfileCmd_V_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetPhyProfileCmd_V_t, Reserved_Ppc_SOP_PHYID), (((Operation & 0xF) << SHIFT8 ) | (PhyId & 0xFF) ) ); + /* build IOMB command and send to SPC */ + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_GET_PHY_PROFILE, IOMB_SIZE128, 0); + if (AGSA_RC_SUCCESS != ret) + { + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + saLlistAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("mpiGetPhyProfileCmd, sending IOMB failed\n" )); + } + SA_DBG3(("mpiGetPhyProfileCmd, return value = %d\n", ret)); + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "xd"); + /* return value */ + return ret; +} + + +GLOBAL bit32 mpiVHistCapCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 Channel, + bit32 NumBitLo, + bit32 NumBitHi, + bit32 PcieAddrLo, + bit32 PcieAddrHi, + bit32 ByteCount ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaIORequestDesc_t *pRequest= agNULL; + bit32 ret = AGSA_RC_SUCCESS; + agsaGetVHistCap_V_t payload; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"3C"); + SA_DBG1(("mpiVHistCapCmd\n")); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* Get request from free IORequests */ + pRequest = (agsaIORequestDesc_t *)saLlistGetHead(&(saRoot->freeIORequests)); + /* If no LL Control request entry avalibale */ + if ( agNULL == pRequest ) + { + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1((", No request from free list\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "3C"); + return AGSA_RC_BUSY; + } + /* If LL Control request entry avaliable */ + else + { + SA_ASSERT((!pRequest->valid), "The pRequest is in use"); + /* Remove the request from free list */ + saLlistRemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + + pRequest->valid = agTRUE; + pRequest->completionCB = (void *)ossaGetPhyProfileCB; + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* set payload to zeros */ + si_memset(&payload, 0, sizeof(agsaGetVHistCap_V_t)); + + /* set tag field */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetVHistCap_V_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetVHistCap_V_t, Channel), Channel ); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetVHistCap_V_t, NumBitLo), NumBitLo); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetVHistCap_V_t, NumBitHi), NumBitHi); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetVHistCap_V_t, PcieAddrLo),PcieAddrLo); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetVHistCap_V_t, PcieAddrHi),PcieAddrHi); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetVHistCap_V_t, ByteCount), ByteCount ); + + + /* build IOMB command and send to SPC */ + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_GET_VHIST_CAP, IOMB_SIZE128,queueNum ); + if (AGSA_RC_SUCCESS != ret) + { + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + saLlistAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("mpiVHistCapCmd, sending IOMB failed\n" )); + } + SA_DBG3(("mpiVHistCapCmd, return value = %d\n", ret)); + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "3C"); + /* return value */ + + return(ret); +} + +GLOBAL bit32 mpiSetPhyProfileCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 Operation, + bit32 PhyId, + bit32 length, + void * buffer + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + bit32 ret = AGSA_RC_SUCCESS; + bit32 i; + agsaSetPhyProfileCmd_V_t payload; + bit32 * PageData =(bit32 * )buffer; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2P"); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* Get request from free IORequests */ + pRequest = (agsaIORequestDesc_t *)saLlistGetHead(&(saRoot->freeIORequests)); + + SA_DBG1(("mpiSetPhyProfileCmd, Operation 0x%x PhyId %d \n",Operation ,PhyId )); + + /* If no LL Control request entry avalibale */ + if ( agNULL == pRequest ) + { + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("mpiSetPhyProfileCmd, No request from free list\n" )); + return AGSA_RC_BUSY; + } + /* If LL Control request entry avaliable */ + else + { + SA_ASSERT((!pRequest->valid), "The pRequest is in use"); + /* Remove the request from free list */ + saLlistRemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + + pRequest->valid = agTRUE; + pRequest->SOP = (bit16) Operation; + pRequest->completionCB = (void *)ossaGetPhyProfileCB; + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + + /* set payload to zeros */ + si_memset(&payload, 0, sizeof(agsaSetPhyProfileCmd_V_t)); + + /* set tag field */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSetPhyProfileCmd_V_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSetPhyProfileCmd_V_t, Reserved_Ppc_SOP_PHYID), (((Operation & 0xF) << SHIFT8 ) | (PhyId & 0xFF) ) ); + + for(i=0; i < (length / sizeof(bit32)); i++) + { + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSetPhyProfileCmd_V_t, PageSpecificArea[i]),* (PageData+i) ); + } + + /* build IOMB command and send to SPC */ + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_SET_PHY_PROFILE, IOMB_SIZE128, 0); + if (AGSA_RC_SUCCESS != ret) + { + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + saLlistAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("mpiSetPhyProfileCmd, sending IOMB failed\n" )); + } + SA_DBG3(("mpiGetPhyProfileCmd, return value = %d\n", ret)); + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2P"); + /* return value */ + return ret; +} + + +/******************************************************************************/ +/*! \brief Get Device Information Command + * + * This command is get # of phys and support speeds from SPC. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param agDevHandle Handle of device + * \param deviceid Device Id + * \param opton oprion + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_BUSY the SPC is no resource, cannot send now + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiGetDeviceInfoCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 deviceid, + bit32 option, + bit32 queueNum + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + bit32 ret = AGSA_RC_SUCCESS; + agsaGetDevInfoCmd_t payload; + + SA_ASSERT((agNULL !=saRoot ), ""); + if(saRoot == agNULL) + { + SA_DBG1(("mpiGetDeviceInfoCmd: saRoot == agNULL\n")); + return(AGSA_RC_FAILURE); + } + smTraceFuncEnter(hpDBG_VERY_LOUD,"2K"); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* Get request from free IORequests */ + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + SA_DBG1(("mpiGetDeviceInfoCmd, No request from free list\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2K"); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + return AGSA_RC_BUSY; + } + /* If LL Control request entry avaliable */ + else + { + /* Remove the request from free list */ + SA_ASSERT((!pRequest->valid), "The pRequest is in use"); + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + pRequest->DeviceInfoCmdOption = (bit8)option; + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + + /* set payload to zeros */ + si_memset(&payload, 0, sizeof(agsaGetDevInfoCmd_t)); + + /* set tag field */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetDevInfoCmd_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetDevInfoCmd_t, DeviceId), deviceid); + /* build IOMB command and send to SPC */ + if( smIS_SPC(agRoot)) + { + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_SPC_GET_DEV_INFO, IOMB_SIZE64, queueNum); + } + else + { + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_GET_DEV_INFO, IOMB_SIZE64, queueNum); + } + if (AGSA_RC_SUCCESS != ret) + { + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("mpiGetDeviceInfoCmd, sending IOMB failed\n" )); + } + SA_DBG3(("mpiGetDeviceInfoCmd, return value = %d\n", ret)); + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2K"); + /* return value */ + return ret; +} + +/******************************************************************************/ +/*! \brief Set Device Information Command + * + * This command is Set Device Information to SPC. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param agDevHandle Handle of device + * \param deviceid Device Id + * \param opton oprion + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_BUSY the SPC is no resource, cannot send now + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiSetDeviceInfoCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 deviceid, + bit32 option, + bit32 queueNum, + bit32 param, + ossaSetDeviceInfoCB_t agCB + ) +{ + agsaLLRoot_t *saRoot = agNULL; + agsaIORequestDesc_t *pRequest = agNULL; + bit32 ret = AGSA_RC_SUCCESS; + agsaSetDevInfoCmd_t payload; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"xe"); + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + SA_ASSERT((agNULL != saRoot), ""); + + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + + SA_DBG2(("mpiSetDeviceInfoCmd, param 0x%08X option 0x%08X\n",param,option )); + + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + SA_DBG1(("mpiSetDeviceInfoCmd, No request from free list\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "xe"); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + return AGSA_RC_BUSY; + } + /* If LL Control request entry avaliable */ + else + { + /* Remove the request from free list */ + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + pRequest->completionCB = (ossaSSPCompletedCB_t)agCB; + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* set payload to zeros */ + si_memset(&payload, 0, sizeof(agsaSetDevInfoCmd_t)); + + /* set tag field */ + + if(smIS_SPC(agRoot)) + { + option &= SET_DEV_INFO_SPC_DW3_MASK; + param &= SET_DEV_INFO_SPC_DW4_MASK; + } + else + { + option &= SET_DEV_INFO_V_DW3_MASK; + param &= SET_DEV_INFO_V_DW4_MASK; + } + + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSetDevInfoCmd_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSetDevInfoCmd_t, deviceId), deviceid); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSetDevInfoCmd_t, SA_SR_SI), option); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSetDevInfoCmd_t, DEVA_MCN_R_ITNT), param ); + + /* build IOMB command and send to SPC */ + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_SET_DEV_INFO, IOMB_SIZE64, queueNum); + if (AGSA_RC_SUCCESS != ret) + { + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("mpiSetDeviceInfoCmd, sending IOMB failed\n" )); + } + SA_DBG3(("mpiSetDeviceInfoCmd, return value = %d\n", ret)); + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "xe"); + /* return value */ + + return ret; +} + +/******************************************************************************/ +/*! \brief SPC MPI Phy Start Command + * + * This command sends to SPC for the I/O. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param tag tage for IOMB + * \param phyId the phy id of the link will be started + * \param agPhyConfig the phy properity + * \param agSASIdentify the SAS identify frame will be sent by the phy + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_BUSY the SPC is no resource, cannot send now + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiPhyStartCmd( + agsaRoot_t *agRoot, + bit32 tag, + bit32 phyId, + agsaPhyConfig_t *agPhyConfig, + agsaSASIdentify_t *agSASIdentify, + bit32 queueNum + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaPhyStartCmd_t payload; + bit32 *pValue; + bit32 *ptemp; + bit32 index; + bit32 dw2 = 0; + +#if defined(SALLSDK_DEBUG) + bit32 Sscd; +#endif /* SALLSDK_DEBUG */ + smTraceFuncEnter(hpDBG_VERY_LOUD,"xg"); + + /* set payload to zeros */ + si_memset(&payload, 0, sizeof(agsaPhyStartCmd_t)); + + pValue = (bit32 *)agSASIdentify; + ptemp = (bit32 *)&payload.sasIdentify; + index = (agPhyConfig->phyProperties & 0x0ff00) >> SHIFT8; + +#if defined(SALLSDK_DEBUG) + Sscd = (agPhyConfig->phyProperties & 0xf0000) >> SHIFT16; +#endif /* SALLSDK_DEBUG */ + + SA_DBG1(("mpiPhyStartCmd,phyId = %d dw 2 0x%08X\n",phyId ,((phyId & SM_PHYID_MASK) | ((agPhyConfig->phyProperties & 0xfff) << SHIFT8) | (agPhyConfig->phyProperties & 0xf0000) ))); + + + SA_DBG2(("mpiPhyStartCmd,phyId 0x%x phyProperties 0x%x index 0x%x Sscd 0x%x\n",phyId, agPhyConfig->phyProperties,index,Sscd)); + + dw2 = ((phyId & SM_PHYID_MASK) | /* PHY id */ + ((agPhyConfig->phyProperties & 0x000000FF) << SHIFT8)| /* SLR Mode */ + (agPhyConfig->phyProperties & 0x000f0000) | /* SSCD */ + (agPhyConfig->phyProperties & 0x00700000) | /* setting bit20, bit21 and bit22 for optical mode */ + (agPhyConfig->phyProperties & 0x00800000) ); /* bit23 active cable mode BCT Disable 12g only*/ + + /* Haileah Phy analogsetting bit enable*/ + if(smIS_SPC(agRoot)) + { + if( smIS_spc8081(agRoot)) + { + dw2 = dw2 | 0x08000; + } + } + + SA_DBG1(("mpiPhyStartCmd,dw2 0x%08x\n",dw2)); + SA_ASSERT(((agSASIdentify->sasAddressHi[0] || agSASIdentify->sasAddressHi[1] || + agSASIdentify->sasAddressHi[2] || agSASIdentify->sasAddressHi[3] || + agSASIdentify->sasAddressLo[0] || agSASIdentify->sasAddressLo[1] || + agSASIdentify->sasAddressLo[2] || agSASIdentify->sasAddressLo[3])), "SAS Address Zero"); + + SA_DBG1(("mpiPhyStartCmd,SAS addr Hi 0x%02X%02X%02X%02X Lo 0x%02X%02X%02X%02X\n", + agSASIdentify->sasAddressHi[0],agSASIdentify->sasAddressHi[1], + agSASIdentify->sasAddressHi[2],agSASIdentify->sasAddressHi[3], + agSASIdentify->sasAddressLo[0],agSASIdentify->sasAddressLo[1], + agSASIdentify->sasAddressLo[2],agSASIdentify->sasAddressLo[3])); + + /* setup phy ID field */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaPhyStartCmd_t, SscdAseSHLmMlrPhyId),dw2); + + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaPhyStartCmd_t, tag), tag); + + /* setup analog setting index field */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaPhyStartCmd_t, analogSetupIdx), index); + /* copy SASIdentify to payload of IOMB */ + si_memcpy(ptemp, pValue, sizeof(agsaSASIdentify_t)); + + /* build IOMB command and send to SPC */ + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_PHYSTART, IOMB_SIZE64, queueNum); + + SA_DBG3(("mpiPhyStartCmd, return value = %d\n", ret)); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "xg"); + return ret; +} + +/******************************************************************************/ +/*! \brief SPC MPI Phy Stop Command + * + * This command sends to SPC for the I/O. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param tag tag of IOMB + * \param phyId To stop the phyId + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_BUSY the SPC is no resource, cannot send now + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiPhyStopCmd( + agsaRoot_t *agRoot, + bit32 tag, + bit32 phyId, + bit32 queueNum + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaPhyStopCmd_t payload; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"xh"); + + /* set payload to zeros */ + si_memset(&payload, 0, sizeof(agsaPhyStopCmd_t)); + + /* set tag */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaPhyStopCmd_t, tag), tag); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaPhyStopCmd_t, phyId), (phyId & SM_PHYID_MASK )); + /* build IOMB command and send to SPC */ + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_PHYSTOP, IOMB_SIZE64, queueNum); + + SA_DBG3(("mpiPhyStopCmd, return value = %d\n", ret)); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "xh"); + + return ret; +} + +/******************************************************************************/ +/*! \brief SPC MPI SMP Request Command + * + * This command sends to SPC for the SMP. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb pointer of IOMB + * \param opcode opcode of IOMB + * \param payload pointer of payload + * \param inq inbound queue number + * \param outq outbound queue number + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_BUSY the SPC is no resource, cannot send now + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiSMPCmd( + agsaRoot_t *agRoot, + void *pIomb, + bit16 opcode, + agsaSMPCmd_t *payload, + bit8 inq, + bit8 outq + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + mpiICQueue_t *circularQ; + bit32 ret = AGSA_RC_SUCCESS; +#if defined(SALLSDK_DEBUG) + mpiMsgHeader_t *msgHeader; + bit32 bc; +#endif /* SALLSDK_DEBUG */ + smTraceFuncEnter(hpDBG_VERY_LOUD,"xi"); + + SA_DBG6(("mpiSMPCmd: start\n")); + +#if defined(SALLSDK_DEBUG) + msgHeader = (mpiMsgHeader_t*)(((bit8*)pIomb) - sizeof(mpiMsgHeader_t)); + bc = (((msgHeader->Header) >> SHIFT24) & BC_MASK); +#endif /* SALLSDK_DEBUG */ + SA_DBG6(("mpiSMPCmd: before msgHeader bc %d\n", bc)); + + /* copy payload if it is necessary */ + if (agNULL != payload) + { + si_memcpy(pIomb, payload, sizeof(agsaSMPCmd_t)); + } + + SA_DBG6(("mpiSMPCmd: after msgHeader bc %d\n", bc)); + + /* post the IOMB to SPC */ + circularQ = &saRoot->inboundQueue[inq]; + if (AGSA_RC_FAILURE == mpiMsgProduce(circularQ, (void *)pIomb, MPI_CATEGORY_SAS_SATA, opcode, outq, (bit8)circularQ->priority)) + ret = AGSA_RC_FAILURE; + + SA_DBG3(("mpiSMPCmd, return value = %d\n", ret)); + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "xi"); + return ret; +} + +/******************************************************************************/ +/*! \brief SPC MPI Deregister Device Handle Command + * + * This command used to deregister(remove) the device handle. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param agDevHandle Device Handle + * \param deviceId index of device + * \param portId index of port + * \param queueNum IQ/OQ number + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_BUSY the SPC is no resource, cannot send now + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiDeregDevHandleCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaDeviceDesc_t *pDevice, + bit32 deviceId, + bit32 portId, + bit32 queueNum + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaDeregDevHandleCmd_t payload; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"xp"); + + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + SA_DBG1(("mpiDeregDevHandleCmd, No request from free list\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "xp"); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + return AGSA_RC_BUSY; + } + /* If LL Control request entry avaliable */ + else + { + pRequest->pDevice = pDevice; + /* Remove the request from free list */ + SA_ASSERT((!pRequest->valid), "The pRequest is in use"); + pRequest->valid = agTRUE; + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* clean the payload to zeros */ + si_memset(&payload, 0, sizeof(agsaDeregDevHandleCmd_t)); + + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaDeregDevHandleCmd_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaDeregDevHandleCmd_t, deviceId), deviceId); + + /* build IOMB command and send it to SPC */ + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_DEREG_DEV_HANDLE, IOMB_SIZE64, queueNum); + if (AGSA_RC_SUCCESS != ret) + { + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("mpiSetVPDCmd, sending IOMB failed\n" )); + } + SA_DBG3(("mpiDeregDevHandleCmd, return value = %d\n", ret)); + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "xp"); + + /* return value */ + return ret; +} + +/******************************************************************************/ +/*! \brief SPC MPI Get Device Handle Command + * + * This command used to get device handle. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param agContext Context of Device Handle Command + * \param portId index of port + * \param flags flags + * \param maxDevs Maximum Device Handles + * \param queueNum IQ/OQ number + * \param skipCount skip device entry count + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_BUSY the SPC is no resource, cannot send now + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiGetDeviceHandleCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 portId, + bit32 flags, + bit32 maxDevs, + bit32 queueNum, + bit32 skipCount + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaGetDevHandleCmd_t payload; + bit32 using_reserved = agFALSE; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"xj"); + + /* Get request from free CntrlRequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeReservedRequests)); /**/ + if(agNULL != pRequest) + { + using_reserved = agTRUE; + SA_DBG1(("mpiGetDeviceHandleCmd, using saRoot->freeReservedRequests\n")); + } + else + { + SA_DBG1(("mpiGetDeviceHandleCmd, No request from free list Not using saRoot->freeReservedRequests\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "xj"); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + return AGSA_RC_BUSY; + } + } + + /* Remove the request from free list */ + if( using_reserved ) + { + saLlistIORemove(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + SA_ASSERT((!pRequest->valid), "The pRequest is in use"); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + + /* clean the payload to zeros */ + si_memset(&payload, 0, sizeof(agsaGetDevHandleCmd_t)); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetDevHandleCmd_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetDevHandleCmd_t, DevADevTMaxDIDportId), + ((portId & PORTID_MASK) | (maxDevs << SHIFT8) | (flags << SHIFT24))); + /* set starting Number */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetDevHandleCmd_t, skipCount), skipCount); + + /* build IOMB command and send it to SPC */ + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_GET_DEV_HANDLE, IOMB_SIZE64, queueNum); + if (AGSA_RC_SUCCESS != ret) + { + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiGetDeviceHandleCmd: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("mpiGetDeviceHandleCmd, sending IOMB failed\n" )); + } + SA_DBG3(("mpiGetDeviceHandleCmd, return value = %d\n", ret)); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "xj"); + + return ret; +} + +/******************************************************************************/ +/*! \brief SPC MPI LOCAL PHY CONTROL Command + * + * This command used to do the SPC Phy operation. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param tag tag of IOMB + * \param phyId PHY Id + * \param operation operation of PHY control + * \param queueNum IQ/OQ number + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_BUSY the SPC is no resource, cannot send now + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiLocalPhyControlCmd( + agsaRoot_t *agRoot, + bit32 tag, + bit32 phyId, + bit32 operation, + bit32 queueNum + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLocalPhyCntrlCmd_t payload; + smTraceFuncEnter(hpDBG_VERY_LOUD,"xl"); + + SA_DBG3(("mpiLocalPhyControlCmd, phyId 0x%X operation 0x%x dw2 0x%x\n",phyId, operation,(((operation & BYTE_MASK) << SHIFT8) | (phyId & SM_PHYID_MASK)))); + + /* clean the payload field */ + si_memset(&payload, 0, sizeof(agsaLocalPhyCntrlCmd_t)); + + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaLocalPhyCntrlCmd_t, phyOpPhyId), + (((operation & BYTE_MASK) << SHIFT8) | (phyId & SM_PHYID_MASK))); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaLocalPhyCntrlCmd_t, tag), tag); + /* build IOMB command and send to SPC */ + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_LOCAL_PHY_CONTROL, IOMB_SIZE64, queueNum); + + SA_DBG3(("mpiLocalPhyControlCmd, return value = %d\n", ret)); + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "xl"); + return ret; +} + +/******************************************************************************/ +/*! \brief Device Handle Accept Command + * + * This command is Device Handle Accept IOMB to SPC. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param agContext Context for the set VPD command + * \param ctag controller tag + * \param deviceId device Id + * \param action action + * \param queueNum queue Number + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_BUSY the SPC is no resource, cannot send now + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiDevHandleAcceptCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 ctag, + bit32 deviceId, + bit32 action, + bit32 flag, + bit32 itlnx, + bit32 queueNum + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaDevHandleAcceptCmd_t payload; + bit32 DW4 =0; + bit32 mcn =0; + bit32 awt =0; + bit32 ha =0; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"xt"); + + if(deviceId & 0xFFFF0000) + { + ha = 1; + } + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot,LL_IOREQ_LOCKEQ_LOCK ); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + + SA_DBG2(("mpiDevHandleAcceptCmd, deviceId 0x%x action 0x%x flag 0x%x itlnx 0x%x\n",deviceId,action,flag,itlnx )); + + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + ossaSingleThreadedLeave(agRoot,LL_IOREQ_LOCKEQ_LOCK ); + SA_DBG1(("mpiDevHandleAcceptCmd, No request from free list\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "xt"); + return AGSA_RC_BUSY; + } + /* If LL Control request entry avaliable */ + else + { + /* Remove the request from free list */ + SA_ASSERT((!pRequest->valid), "The pRequest is in use"); + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* Do not mark as valid at this IOMB does not complete in OBQ */ + + /* set payload to zeros */ + si_memset(&payload, 0, sizeof(agsaDevHandleAcceptCmd_t)); + + /* set tag field */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaDevHandleAcceptCmd_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaDevHandleAcceptCmd_t, deviceId), deviceId); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaDevHandleAcceptCmd_t, Ctag), ctag); + mcn = (flag & 0xF0000) >>SHIFT16; + awt = (flag & 2)>>SHIFT1; + DW4 = (action << SHIFT24) | \ + mcn << SHIFT20 | \ + awt << SHIFT17 | \ + ha << SHIFT16 | \ + itlnx; + SA_DBG2(("mpiDevHandleAcceptCmd,DW4 0x%x\n",DW4 )); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaDevHandleAcceptCmd_t, DevA_MCN_R_R_HA_ITNT),DW4); + } + + /* build IOMB command and send to SPC */ + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_DEV_HANDLE_ACCEPT, IOMB_SIZE64, queueNum); + if (AGSA_RC_SUCCESS != ret) + { + SA_DBG1(("mpiDevHandleAcceptCmd, sending IOMB failed\n" )); + } + else + { + SA_DBG1(("mpiDevHandleAcceptCmd, sending IOMB succeeded\n" )); + } + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiDevHandleAcceptCmd: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + + /* return value */ + ossaSingleThreadedLeave(agRoot,LL_IOREQ_LOCKEQ_LOCK ); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "xt"); + return ret; +} + +/******************************************************************************/ +/*! \brief SPC READ REGISTER DUMP Command + * + * This command used to do the SPC Read Register Dump command. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param tag tag of IOMB + * \param cpuId CPU Id + * \param queueNum IQ/OQ number + * \param cpuId AAP1 or IOP + * \param cOffset offset of the register dump data + * \param addrHi Hi address if Register Dump data + * \param addrHi Low address if Register Dump data + * \param len the length of for read + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_BUSY the SPC is no resource, cannot send now + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiNVMReadRegDumpCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 cpuId, + bit32 cOffset, + bit32 addrHi, + bit32 addrLo, + bit32 len + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaGetNVMDataCmd_t payload; + bit32 nvmd = 0; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"xk"); + + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + SA_DBG1(("mpiNVMReadRegDumpCmd, No request from free list\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "xk"); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + return AGSA_RC_BUSY; + } + /* If LL Control request entry avaliable */ + else + { + /* Remove the request from free list */ + SA_ASSERT((!pRequest->valid), "The pRequest is in use"); + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* clean the payload field */ + si_memset(&payload, 0, sizeof(agsaGetNVMDataCmd_t)); + + /* only indirect mode */ + if (cpuId <= 1) + { + if (cpuId == 0) + nvmd = AAP1_RDUMP | IRMode; + else + nvmd = IOP_RDUMP | IRMode; + + /* setup IOMB */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetNVMDataCmd_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetNVMDataCmd_t, LEN_IR_VPDD), nvmd); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetNVMDataCmd_t, VPDOffset), cOffset); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetNVMDataCmd_t, respAddrLo), addrLo); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetNVMDataCmd_t, respAddrHi), addrHi); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetNVMDataCmd_t, respLen), len); + + /* build IOMB command and send to SPC */ + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_GET_NVMD_DATA, IOMB_SIZE64, queueNum); + } + else + { + SA_DBG1(("mpiNVMReadRegDumpCmd, Wrong device type\n" )); + ret = AGSA_RC_FAILURE; + } + + if (AGSA_RC_SUCCESS != ret) + { + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("mpiNVMReadRegDumpCmd, sending IOMB failed\n" )); + } + } + + SA_DBG3(("mpiNVMReadRegDumpCmd, return value = %d\n", ret)); + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "xk"); + + return ret; +} + +/******************************************************************************/ +/*! \brief Get NVM Data command + * + * This command is get NVM Data from SPC. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param agContext Context for the VPD command + * \param VPDInfo Pointer of VPD Information + * \param queueNum Queue Number of inbound/outbound queue + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_BUSY the SPC is no resource, cannot send now + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiGetNVMDCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaNVMDData_t *NVMDInfo, + bit32 queueNum + ) +{ + bit32 ret = AGSA_RC_FAILURE; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaGetNVMDataCmd_t payload; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"xr"); + + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + SA_DBG1(("mpiGetNVMDCmd, No request from free list\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "xr"); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + return AGSA_RC_BUSY; + } + /* If LL Control request entry avaliable */ + else + { + SA_DBG3(("mpiGetNVMDCmd, Build IOMB NVMDDevice= 0x%x\n", NVMDInfo->NVMDevice)); + /* Remove the request from free list */ + SA_ASSERT((!pRequest->valid), "The pRequest is in use"); + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* set payload to zeros */ + si_memset(&payload, 0, sizeof(agsaGetNVMDataCmd_t)); + /* set tag field */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetNVMDataCmd_t, tag), pRequest->HTag); + + if (NVMDInfo->indirectPayload) + { + /* indirect payload IP = 1 */ + switch (NVMDInfo->NVMDevice) + { + case AGSA_NVMD_TWI_DEVICES: + /* NVMD = 0 */ + /* indirect payload IP = 1 and 0x0 (TWI) */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetNVMDataCmd_t, LEN_IR_VPDD), + (NVMDInfo->TWIDeviceAddress << 16) | (NVMDInfo->TWIBusNumber << 12) | + (NVMDInfo->TWIDevicePageSize << 8) | (NVMDInfo->TWIDeviceAddressSize << 4) | + (NVMDInfo->indirectPayload << 31) | NVMDInfo->NVMDevice); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetNVMDataCmd_t, VPDOffset), + NVMDInfo->dataOffsetAddress); + break; + case AGSA_NVMD_CONFIG_SEEPROM: + /* NVMD = 1 */ + /* Data Offset should be 0 */ + if (NVMDInfo->dataOffsetAddress != 0) + { + /* Error for Offset */ + SA_DBG1(("mpiGetNVMDCmd, (IP=1)wrong offset = 0x%x\n", NVMDInfo->dataOffsetAddress)); + } + /* indirect payload IP = 1, NVMD = 0x1 (SEEPROM0) */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetNVMDataCmd_t, LEN_IR_VPDD), + (NVMDInfo->indirectPayload << SHIFT31) | (NVMDInfo->NVMDevice)); + break; + case AGSA_NVMD_VPD_FLASH: + /* indirect payload IP = 1 and 0x4 (FLASH) */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetNVMDataCmd_t, LEN_IR_VPDD), + (NVMDInfo->indirectPayload << SHIFT31) | NVMDInfo->NVMDevice); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetNVMDataCmd_t, VPDOffset), + NVMDInfo->dataOffsetAddress); + break; + case AGSA_NVMD_EXPANSION_ROM: + /* indirect payload IP = 1 and 0x7 (EXPANSION ROM PARTITION) */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetNVMDataCmd_t, LEN_IR_VPDD), + (NVMDInfo->indirectPayload << SHIFT31) | NVMDInfo->NVMDevice); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetNVMDataCmd_t, VPDOffset), + NVMDInfo->dataOffsetAddress); + break; + case AGSA_NVMD_AAP1_REG_FLASH: /* AGSA_NVMD_REG_FLASH SPCv uses 5 as well */ + /* indirect payload IP = 1 and 0x5 (AGSA_NVMD_AAP1_REG_FLASH ) */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetNVMDataCmd_t, LEN_IR_VPDD), + (NVMDInfo->indirectPayload << SHIFT31) | NVMDInfo->NVMDevice); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetNVMDataCmd_t, VPDOffset), + NVMDInfo->dataOffsetAddress); + break; + case AGSA_NVMD_IOP_REG_FLASH: + /* indirect payload IP = 1 and 0x6 ( AGSA_NVMD_IOP_REG_FLASH ) */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetNVMDataCmd_t, LEN_IR_VPDD), + (NVMDInfo->indirectPayload << SHIFT31) | NVMDInfo->NVMDevice); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetNVMDataCmd_t, VPDOffset), + NVMDInfo->dataOffsetAddress); + break; + + default: + SA_DBG1(("mpiGetNVMDCmd, (IP=1)wrong device type = 0x%x\n", NVMDInfo->NVMDevice)); + break; + } + + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetNVMDataCmd_t, respAddrLo), NVMDInfo->indirectAddrLower32); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetNVMDataCmd_t, respAddrHi), NVMDInfo->indirectAddrUpper32); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetNVMDataCmd_t, respLen), NVMDInfo->indirectLen); + /* build IOMB command and send to SPC */ + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_GET_NVMD_DATA, IOMB_SIZE64, queueNum); + } + else + { + /* direct payload IP = 0 only for TWI device */ + if (AGSA_NVMD_TWI_DEVICES == NVMDInfo->NVMDevice) + { + /* NVMD = 0 */ + /* indirect payload IP = 0 and 0x0 (TWI) */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetNVMDataCmd_t, LEN_IR_VPDD), + (NVMDInfo->TWIDeviceAddress << SHIFT16) | (NVMDInfo->TWIBusNumber << SHIFT12) | + (NVMDInfo->TWIDevicePageSize << SHIFT8) | (NVMDInfo->TWIDeviceAddressSize << SHIFT4) | + NVMDInfo->NVMDevice); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetNVMDataCmd_t, VPDOffset), + NVMDInfo->dataOffsetAddress | (NVMDInfo->directLen << SHIFT24)); + /* build IOMB command and send to SPC */ + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_GET_NVMD_DATA, IOMB_SIZE64, queueNum); + } + else + { + SA_DBG1(("mpiGetNVMDCmd, (IP=0)wrong device type = 0x%x\n", NVMDInfo->NVMDevice)); + ret = AGSA_RC_FAILURE; + /* CB for NVMD with error */ + ossaGetNVMDResponseCB(agRoot, agContext, OSSA_NVMD_MODE_ERROR, 0, NVMDInfo->directLen, agNULL); + } + } + + if (AGSA_RC_SUCCESS != ret) + { + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("mpiGetNVMDCmd, sending IOMB failed\n" )); + } + SA_DBG3(("mpiGetNVMDCmd, return value = %d\n", ret)); + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "xr"); + + /* return value */ + return ret; +} + +/******************************************************************************/ +/*! \brief Set NVM Data Command + * + * This command is set NVM Data to SPC. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param agContext Context for the set VPD command + * \param NVMDInfo pointer of VPD information + * \param queueNum queue Number + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_BUSY the SPC is no resource, cannot send now + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiSetNVMDCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaNVMDData_t *NVMDInfo, + bit32 queueNum + ) +{ + bit32 ret = AGSA_RC_FAILURE; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaSetNVMDataCmd_t payload; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"xm"); + + + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + SA_DBG1(("mpiSetNVMDCmd, No request from free list\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "xm"); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + return AGSA_RC_BUSY; + } + /* If LL Control request entry avaliable */ + else + { + SA_DBG3(("mpiSetNVMDCmd, Build IOMB NVMDDevice= 0x%x\n", NVMDInfo->NVMDevice)); + /* Remove the request from free list */ + SA_ASSERT((!pRequest->valid), "The pRequest is in use"); + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* set payload to zeros */ + si_memset(&payload, 0, sizeof(agsaSetNVMDataCmd_t)); + + /* set tag field */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSetNVMDataCmd_t, tag), pRequest->HTag); + + if (NVMDInfo->indirectPayload) + { + /* indirect payload IP = 1 */ + switch (NVMDInfo->NVMDevice) + { + case AGSA_NVMD_TWI_DEVICES: + /* NVMD = 0 */ + /* indirect payload IP = 1 and 0x0 (TWI) */ + /* set up signature */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSetNVMDataCmd_t, Data.indirectData.signature), NVMDInfo->signature); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSetNVMDataCmd_t, LEN_IR_VPDD), + (NVMDInfo->TWIDeviceAddress << SHIFT16) | (NVMDInfo->TWIBusNumber << SHIFT12) | + (NVMDInfo->TWIDevicePageSize << SHIFT8) | (NVMDInfo->TWIDeviceAddressSize << SHIFT4) | + (NVMDInfo->indirectPayload << SHIFT31) | NVMDInfo->NVMDevice); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSetNVMDataCmd_t, VPDOffset), + NVMDInfo->dataOffsetAddress); + break; + /* 0x01:SEEPROM-0 and 0x04:FLASH only in indirect mode */ + case AGSA_NVMD_CONFIG_SEEPROM: + /* NVMD=1 */ + /* Data Offset should be 0 */ + /* set up signature */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSetNVMDataCmd_t, Data.indirectData.signature), NVMDInfo->signature); + /* indirect payload IP = 1, NVMD = 0x1 (SEEPROM0) */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSetNVMDataCmd_t, LEN_IR_VPDD), + (NVMDInfo->indirectPayload << SHIFT31) | NVMDInfo->NVMDevice); + break; + case AGSA_NVMD_VPD_FLASH: + /* indirect payload IP = 1, NVMD=0x4 (FLASH) */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSetNVMDataCmd_t, LEN_IR_VPDD), + (NVMDInfo->indirectPayload << SHIFT31) | NVMDInfo->NVMDevice); + /* set up Offset */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSetNVMDataCmd_t, VPDOffset), + NVMDInfo->dataOffsetAddress); + break; + default: + SA_DBG1(("mpiSetNVMDCmd, (IP=1)wrong device type = 0x%x\n", NVMDInfo->NVMDevice)); + ret = AGSA_RC_FAILURE; + ossaSetNVMDResponseCB(agRoot, agContext, OSSA_NVMD_MODE_ERROR); + break; + } + + /* set up SGL field */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSetNVMDataCmd_t, Data.indirectData.ISglAL), (NVMDInfo->indirectAddrLower32)); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSetNVMDataCmd_t, Data.indirectData.ISglAH), (NVMDInfo->indirectAddrUpper32)); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSetNVMDataCmd_t, Data.indirectData.ILen), (NVMDInfo->indirectLen)); + /* build IOMB command and send to SPC */ + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_SET_NVMD_DATA, IOMB_SIZE64, queueNum); + } + else + { + /* direct payload IP = 0 */ + if (AGSA_NVMD_TWI_DEVICES == NVMDInfo->NVMDevice) + { + /* NVMD = 0 */ + /* indirect payload IP = 0 and 0x0 (TWI) */ + /* not allow write to Config SEEPROM for direct mode, so don't set singature */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSetNVMDataCmd_t, LEN_IR_VPDD), + (NVMDInfo->TWIDeviceAddress << SHIFT16) | (NVMDInfo->TWIBusNumber << SHIFT12) | + (NVMDInfo->TWIDevicePageSize << SHIFT8) | (NVMDInfo->TWIDeviceAddressSize << SHIFT4) | + NVMDInfo->NVMDevice); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSetNVMDataCmd_t, VPDOffset), + NVMDInfo->dataOffsetAddress | (NVMDInfo->directLen << SHIFT24)); + si_memcpy(&payload.Data.NVMData[0], NVMDInfo->directData, NVMDInfo->directLen); + /* build IOMB command and send to SPC */ + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_SET_NVMD_DATA, IOMB_SIZE64, queueNum); + } + else + { + SA_DBG1(("mpiSetNVMDCmd, (IP=0)wrong device type = 0x%x\n", NVMDInfo->NVMDevice)); + ret = AGSA_RC_FAILURE; + ossaSetNVMDResponseCB(agRoot, agContext, OSSA_NVMD_MODE_ERROR); + } + } + + if (AGSA_RC_SUCCESS != ret) + { + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("mpiSetVPDCmd, sending IOMB failed\n" )); + } + SA_DBG3(("mpiSetNVMDCmd, return value = %d\n", ret)); + } + + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "xm"); + return ret; +} + +/******************************************************************************/ +/*! \brief Set Device State command + * + * This command is set Device State to SPC. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param agContext Context for the Set Nexus State command + * \param deviceId DeviceId + * \param queueNum Queue Number of inbound/outbound queue + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_BUSY the SPC is no resource, cannot send now + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiSetDeviceStateCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 deviceId, + bit32 nds, + bit32 queueNum + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaSetDeviceStateCmd_t payload; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"xn"); + + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + SA_DBG1(("mpiSetDeviceStateCmd, No request from free list\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "xn"); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + return AGSA_RC_BUSY; + } + /* If LL Control request entry avaliable */ + else + { + SA_DBG3(("mpiSetDeviceStateCmd, Build IOMB DeviceId= 0x%x\n", deviceId)); + /* Remove the request from free list */ + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* set payload to zeros */ + si_memset(&payload, 0, sizeof(agsaSetDeviceStateCmd_t)); + /* set tag field */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSetDeviceStateCmd_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSetDeviceStateCmd_t, deviceId), deviceId); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSetDeviceStateCmd_t, NDS), nds); + + /* build IOMB command and send to SPC */ + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_SET_DEVICE_STATE, IOMB_SIZE64, queueNum); + if (AGSA_RC_SUCCESS != ret) + { + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("mpiSetNexusStateCmd, sending IOMB failed\n" )); + } + SA_DBG3(("mpiSetDeviceStateCmd, return value = %d\n", ret)); + } + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "xn"); + + return ret; +} + +/******************************************************************************/ +/*! \brief Get Device State command + * + * This command is get device State to SPC. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param agContext Context for the Get Nexus State command + * \param deviceId DeviceId + * \param queueNum Queue Number of inbound/outbound queue + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_BUSY the SPC is no resource, cannot send now + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiGetDeviceStateCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 deviceId, + bit32 queueNum + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaGetDeviceStateCmd_t payload; + bit32 using_reserved = agFALSE; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"xf"); + + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeReservedRequests)); /**/ + /* If no LL Control request entry available */ + if(agNULL != pRequest) + { + using_reserved = agTRUE; + SA_DBG1(("mpiGetDeviceStateCmd, using saRoot->freeReservedRequests\n")); + } + else + { + SA_DBG1(("mpiGetDeviceStateCmd, No request from free list Not using saRoot->freeReservedRequests\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "xf"); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + return AGSA_RC_BUSY; + } + + } + /* If LL Control request entry avaliable */ + SA_DBG3(("mpiGetDeviceStateCmd, Build IOMB DeviceId= 0x%x\n", deviceId)); + /* Remove the request from free list */ + if( using_reserved ) + { + saLlistIORemove(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* set payload to zeros */ + si_memset(&payload, 0, sizeof(agsaGetDeviceStateCmd_t)); + /* set tag field */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetDeviceStateCmd_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaGetDeviceStateCmd_t, deviceId), deviceId); + + /* build IOMB command and send to SPC */ + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_GET_DEVICE_STATE, IOMB_SIZE64, queueNum); + if (AGSA_RC_SUCCESS != ret) + { + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* remove the request from IOMap */ + SA_ASSERT((!pRequest->valid), "The pRequest is in use"); + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiGetDeviceStateCmd: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("mpiGetDeviceStateCmd, sending IOMB failed\n" )); + } + SA_DBG3(("mpiGetDeviceStateCmd, return value = %d\n", ret)); + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "xf"); + + return ret; +} + +/******************************************************************************/ +/*! \brief SAS ReInitialize command + * + * This command is Reinitialize SAS paremeters to SPC. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param agContext Context for the Get Nexus State command + * \param agSASConfig SAS Configuration Parameters + * \param queueNum Queue Number of inbound/outbound queue + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_BUSY the SPC is no resource, cannot send now + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiSasReinitializeCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaSASReconfig_t *agSASConfig, + bit32 queueNum + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaSasReInitializeCmd_t payload; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"xo"); + + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + SA_DBG1(("mpiSasReinitializeCmd, No request from free list\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "xo"); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + return AGSA_RC_BUSY; + } + /* If LL Control request entry avaliable */ + else + { + SA_DBG3(("mpiSasReinitializeCmd, Build IOMB SAS_RE_INITIALIZE\n")); + /* Remove the request from free list */ + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* set payload to zeros */ + si_memset(&payload, 0, sizeof(agsaSasReInitializeCmd_t)); + + /* set tag field */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSasReInitializeCmd_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSasReInitializeCmd_t, setFlags), agSASConfig->flags); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSasReInitializeCmd_t, MaxPorts), agSASConfig->maxPorts); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSasReInitializeCmd_t, openRejReCmdData), + (agSASConfig->openRejectRetriesCmd << SHIFT16) | agSASConfig->openRejectRetriesData); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSasReInitializeCmd_t, sataHOLTMO), agSASConfig->sataHolTmo); + + + /* build IOMB command and send to SPC */ + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_SAS_RE_INITIALIZE, IOMB_SIZE64, queueNum); + if (AGSA_RC_SUCCESS != ret) + { + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* remove the request from IOMap */ + SA_ASSERT((!pRequest->valid), "The pRequest is in use"); + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("mpiSasReinitializeCmd, sending IOMB failed\n" )); + } + SA_DBG3(("mpiSasReinitializeCmd, return value = %d\n", ret)); + } + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "xo"); + + return ret; +} + +/******************************************************************************/ +/*! \brief SAS Set Controller Configuration Command + * + * This command updates the contents of a controller mode page. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param agContext Context for the Get Nexus State command + * \param agControllerConfig Mode page being sent to the controller + * \param queueNum Queue Number of inbound/outbound queue + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_BUSY the SPC is no resource, cannot send now + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 +mpiSetControllerConfigCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaSetControllerConfigCmd_t *agControllerConfig, + bit32 queueNum, + bit8 modePageContext + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"x1"); + + SA_DBG2(("mpiSetControllerConfigCmd: agControllerConfig 0x%08x 0x%08x 0x%08x 0x%08x\n", + agControllerConfig->pageCode,agControllerConfig->configPage[0], + agControllerConfig->configPage[1], agControllerConfig->configPage[2])); + SA_DBG2(("mpiSetControllerConfigCmd: agControllerConfig 0x%08x 0x%08x 0x%08x 0x%08x\n", + agControllerConfig->configPage[3],agControllerConfig->configPage[4], + agControllerConfig->configPage[5], agControllerConfig->configPage[6])); + SA_DBG2(("mpiSetControllerConfigCmd: agControllerConfig 0x%08x 0x%08x 0x%08x 0x%08x\n", + agControllerConfig->configPage[7],agControllerConfig->configPage[8], + agControllerConfig->configPage[9], agControllerConfig->configPage[10])); + SA_DBG2(("mpiSetControllerConfigCmd: agControllerConfig 0x%08x 0x%08x\n", + agControllerConfig->configPage[11],agControllerConfig->configPage[12])); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* Get request from free IORequests */ + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + SA_DBG1(("mpiSetControllerConfigCmd, No request from free list\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "x1"); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + return AGSA_RC_BUSY; + } + /* If LL Control request entry avaliable */ + else + { + SA_DBG2(("mpiSetControllerConfigCmd, Build IOMB pageCode 0x%x configPage[0] 0x%x\n",agControllerConfig->pageCode,agControllerConfig->configPage[0])); + /* Remove the request from free list */ + SA_ASSERT((!pRequest->valid), "The pRequest is in use"); + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + pRequest->modePageContext = modePageContext; + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* set tag field */ + agControllerConfig->tag = pRequest->HTag; + ret = mpiBuildCmd(agRoot, (bit32 *)agControllerConfig, + MPI_CATEGORY_SAS_SATA, OPC_INB_SET_CONTROLLER_CONFIG, IOMB_SIZE64, 0); + + if (AGSA_RC_SUCCESS != ret) + { + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("mpiSetControllerConfigCmd, sending IOMB failed\n" )); + } + SA_DBG3(("mpiSetControllerConfigCmd, return value = %d\n", ret)); + } + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "x1"); + + return ret; +} + +/******************************************************************************/ +/*! \brief SAS Get Controller Configuration Command + * + * This command retrieves the contents of a controller mode page. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param agContext Context for the Get Nexus State command + * \param agControllerConfig Mode page to retrieve from the controller + * \param queueNum Queue Number of inbound/outbound queue + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_BUSY the SPC is no resource, cannot send now + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiGetControllerConfigCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaGetControllerConfigCmd_t *agControllerConfig, + bit32 queueNum + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"xq"); + + SA_DBG1(("mpiGetControllerConfigCmd: Tag 0x%0X Page Code %0X\n",agControllerConfig->tag,agControllerConfig->pageCode )); + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + SA_DBG1(("mpiGetControllerConfigCmd, No request from free list\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "xq"); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + return AGSA_RC_BUSY; + } + /* If LL Control request entry avaliable */ + else + { + SA_DBG3(("mpiGetControllerConfig, Build IOMB mpiGetControllerConfigCmd\n")); + /* Remove the request from free list */ + SA_ASSERT((!pRequest->valid), "The pRequest is in use"); + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* set tag field */ + agControllerConfig->tag = pRequest->HTag; + + ret = mpiBuildCmd(agRoot, (bit32 *) agControllerConfig, + MPI_CATEGORY_SAS_SATA, OPC_INB_GET_CONTROLLER_CONFIG, IOMB_SIZE64, 0); + + if (AGSA_RC_SUCCESS != ret) + { + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("mpiGetControllerConfigCmd, sending IOMB failed\n" )); + } + else + { + SA_DBG3(("mpiGetControllerConfigCmd, set OK\n")); + } + SA_DBG3(("mpiGetControllerConfigCmd, return value = %d\n", ret)); + } + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "xq"); + + return ret; +} + +/******************************************************************************/ +/*! \brief SAS Encryption KEK command + * + * This command updates one or more KEK in a controller that supports encryption. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param agContext Context for the Get Nexus State command + * \param agKekMgmt Kek information that will be sent to the controller + * \param queueNum Queue Number of inbound/outbound queue + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_BUSY the SPC is no resource, cannot send now + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiKekManagementCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaKekManagementCmd_t *agKekMgmt, + bit32 queueNum + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"x2"); + + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + SA_DBG1(("mpiKekManagementCmd, No request from free list\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "x2"); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + return AGSA_RC_BUSY; + } + /* If LL Control request entry avaliable */ + else + { + SA_DBG3(("mpiKekManagementCmd, Build OPC_INB_KEK_MANAGEMENT\n")); + /* Remove the request from free list */ + SA_ASSERT((!pRequest->valid), "The pRequest is in use"); + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + agKekMgmt->tag = pRequest->HTag; + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("mpiKekManagementCmd, 0x%X 0x%X 0x%X\n", agKekMgmt->tag,agKekMgmt->NEWKIDX_CURKIDX_KBF_Reserved_SKNV_KSOP, agKekMgmt->reserved )); + + ret = mpiBuildCmd(agRoot, (bit32 *)agKekMgmt, MPI_CATEGORY_SAS_SATA, OPC_INB_KEK_MANAGEMENT, IOMB_SIZE64, 0); + + if (AGSA_RC_SUCCESS != ret) + { + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("mpiKekManagementCmd, sending IOMB failed\n" )); + } + SA_DBG3(("mpiKekManagementCmd, return value = %d\n", ret)); + } + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "x2"); + + return ret; +} + +/******************************************************************************/ +/*! \brief SAS Encryption DEK management command + * + * This command updates one or more DEK in a controller that supports encryption. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param agContext Context for the Get Nexus State command + * \param agDekMgmt DEK information that will be sent to the controller + * \param queueNum Queue Number of inbound/outbound queue + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_BUSY the SPC is no resource, cannot send now + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiDekManagementCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaDekManagementCmd_t *agDekMgmt, + bit32 queueNum + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"xs"); + + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + SA_DBG1(("mpiDekManagementCmd, No request from free list\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "xs"); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + return AGSA_RC_BUSY; + } + /* If LL Control request entry avaliable */ + else + { + SA_DBG1(("mpiDekManagementCmd, Build OPC_INB_DEK_MANAGEMENT pRequest %p\n",pRequest)); + /* Remove the request from free list */ + SA_ASSERT((!pRequest->valid), "The pRequest is in use"); + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + agDekMgmt->tag = pRequest->HTag; + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("mpiDekManagementCmd: 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n", + agDekMgmt->tag, + agDekMgmt->KEKIDX_Reserved_TBLS_DSOP, + agDekMgmt->dekIndex, + agDekMgmt->tableAddrLo, + agDekMgmt->tableAddrHi, + agDekMgmt->tableEntries, + agDekMgmt->Reserved_DBF_TBL_SIZE )); + ret = mpiBuildCmd(agRoot, (bit32 *) agDekMgmt, MPI_CATEGORY_SAS_SATA, OPC_INB_DEK_MANAGEMENT, IOMB_SIZE64, 0); + + if (AGSA_RC_SUCCESS != ret) + { + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("mpiDekManagementCmd, sending IOMB failed\n" )); + } + SA_DBG3(("mpiDekManagementCmd, return value = %d\n", ret)); + } + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "xs"); + + return ret; +} + +/******************************************************************************/ +/*! \brief + * + * This command sends operator management command. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param agContext Context + * \param queueNum Queue Number of inbound/outbound queue + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_BUSY the SPC is no resource, cannot send now + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiOperatorManagementCmd( + agsaRoot_t *agRoot, + bit32 queueNum, + agsaContext_t *agContext, + agsaOperatorMangmentCmd_t *operatorcode ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2q"); + + SA_DBG1(("mpiOperatorManagementCmd, enter\n" )); + + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + SA_DBG1(("mpiOperatorManagementCmd, No request from free list\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2q"); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + return AGSA_RC_BUSY; + } + /* If LL Control request entry avaliable */ + else + { + SA_DBG1(("mpiOperatorManagementCmd, Build OPC_INB_OPR_MGMT\n")); + /* Remove the request from free list */ + SA_ASSERT((!pRequest->valid), "The pRequest is in use"); + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + operatorcode->tag = pRequest->HTag; + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + ret = mpiBuildCmd(agRoot, (bit32 *)operatorcode , MPI_CATEGORY_SAS_SATA, OPC_INB_OPR_MGMT, IOMB_SIZE128, 0); + + if (AGSA_RC_SUCCESS != ret) + { + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("mpiOperatorManagementCmd, sending IOMB failed\n" )); + } + SA_DBG1(("mpiOperatorManagementCmd, return value = %d\n", ret)); + } + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2q"); + + return ret; +} + +/******************************************************************************/ +/*! \brief + * + * This command sends encrypt self test command. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param agContext Context + * \param queueNum Queue Number of inbound/outbound queue + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_BUSY the SPC is no resource, cannot send now + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiEncryptBistCmd( + agsaRoot_t *agRoot, + bit32 queueNum, + agsaContext_t *agContext, + agsaEncryptBist_t *bist ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2z"); + + SA_DBG1(("mpiEncryptBistCmd, enter\n" )); + + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + SA_DBG1(("mpiEncryptBistCmd, No request from free list\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2z"); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + return AGSA_RC_BUSY; + } + /* If LL Control request entry avaliable */ + else + { + SA_DBG1(("mpiEncryptBistCmd, Build OPC_INB_ENC_TEST_EXECUTE\n")); + /* Remove the request from free list */ + SA_ASSERT((!pRequest->valid), "The pRequest is in use"); + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + bist->tag = pRequest->HTag; + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("mpiEncryptBistCmd: 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n", + bist->tag, + bist->r_subop, + bist->testDiscption[0], + bist->testDiscption[1], + bist->testDiscption[2], + bist->testDiscption[3], + bist->testDiscption[4] )); + ret = mpiBuildCmd(agRoot, (bit32 *)bist , MPI_CATEGORY_SAS_SATA, OPC_INB_ENC_TEST_EXECUTE, IOMB_SIZE64, 0); + + if (AGSA_RC_SUCCESS != ret) + { + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("mpiEncryptBistCmd, sending IOMB failed\n" )); + } + SA_DBG1(("mpiEncryptBistCmd, return value = %d\n", ret)); + } + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2z"); + + return ret; +} + +/******************************************************************************/ +/*! \brief + * + * This command sends set operator command. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param agContext Context + * \param queueNum Queue Number of inbound/outbound queue + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_BUSY the SPC is no resource, cannot send now + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 +mpiSetOperatorCmd( + agsaRoot_t *agRoot, + bit32 queueNum, + agsaContext_t *agContext, + agsaSetOperatorCmd_t *operatorcode + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"39"); + + SA_DBG1(("mpiSetOperatorCmd, enter\n" )); + + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + SA_DBG1(("mpiSetOperatorCmd, No request from free list\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "39"); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + return AGSA_RC_BUSY; + } + /* If LL Control request entry avaliable */ + else + { + SA_DBG1(("mpiSetOperatorCmd, Build OPC_INB_SET_OPERATOR\n")); + /* Remove the request from free list */ + SA_ASSERT((!pRequest->valid), "The pRequest is in use"); + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + operatorcode->tag = pRequest->HTag; + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + ret = mpiBuildCmd(agRoot, (bit32 *)operatorcode, MPI_CATEGORY_SAS_SATA, OPC_INB_SET_OPERATOR, IOMB_SIZE64, 0); + + if (AGSA_RC_SUCCESS != ret) + { + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("mpiSetOperatorCmd, sending IOMB failed\n" )); + } + SA_DBG1(("mpiSetOperatorCmd, return value = %d\n", ret)); + } + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "39"); + + return ret; +} + +/******************************************************************************/ +/*! \brief + * + * This command sends get operator command. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param agContext Context + * \param queueNum Queue Number of inbound/outbound queue + * + * \return If the MPI command is sent to SPC successfully + * - \e AGSA_RC_SUCCESS the MPI command is successfully + * - \e AGSA_RC_BUSY the SPC is no resource, cannot send now + * - \e AGSA_RC_FAILURE the MPI command is failure + * + */ +/*******************************************************************************/ +GLOBAL bit32 +mpiGetOperatorCmd( + agsaRoot_t *agRoot, + bit32 queueNum, + agsaContext_t *agContext, + agsaGetOperatorCmd_t *operatorcode + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"3e"); + + SA_DBG1(("mpiGetOperatorCmd, enter\n" )); + + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + SA_DBG1(("mpiGetOperatorCmd, No request from free list\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "3e"); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + return AGSA_RC_BUSY; + } + /* If LL Control request entry avaliable */ + else + { + SA_DBG1(("mpiGetOperatorCmd, Build OPC_INB_GET_OPERATOR\n")); + /* Remove the request from free list */ + SA_ASSERT((!pRequest->valid), "The pRequest is in use"); + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + operatorcode->tag = pRequest->HTag; + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + ret = mpiBuildCmd(agRoot, (bit32 *)operatorcode, MPI_CATEGORY_SAS_SATA, OPC_INB_GET_OPERATOR, IOMB_SIZE64, 0); + + if (AGSA_RC_SUCCESS != ret) + { + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("mpiGetOperatorCmd, sending IOMB failed\n" )); + } + SA_DBG1(("mpiGetOperatorCmd, return value = %d\n", ret)); + } + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "3e"); + + return ret; +} + +GLOBAL bit32 mpiDIFEncryptionOffloadCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 op, + agsaDifEncPayload_t *agDifEncOffload, + ossaDIFEncryptionOffloadStartCB_t agCB + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + bit32 dw8=0; + bit32 dw9=0; + bit32 dw10=0; + bit32 dw14=0; + bit32 dw15=0; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaDifEncOffloadCmd_t payload; + smTraceFuncEnter(hpDBG_VERY_LOUD,"2b"); + + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + SA_DBG1(("mpiDIFEncryptionOffloadCmd: No request from free list\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2b"); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + return AGSA_RC_BUSY; + } + /* If LL Control request entry avaliable */ + else + { + SA_DBG1(("mpiDIFEncryptionOffloadCmd: Build OPC_INB_DIF_ENC_OFFLOAD_CMD pRequest %p\n",pRequest)); + /* Remove the request from free list */ + SA_ASSERT((!pRequest->valid), "The pRequest is in use"); + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + pRequest->completionCB = (ossaSSPCompletedCB_t)agCB; + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + si_memset(&payload, 0, sizeof(agsaDifEncOffloadCmd_t)); + SA_DBG1(("mpiDIFEncryptionOffloadCmd: op %d\n",op)); + + if(smIS_SPCV(agRoot)) + { + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaDifEncOffloadCmd_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaDifEncOffloadCmd_t, option), op); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaDifEncOffloadCmd_t, Src_Data_Len), agDifEncOffload->SrcDL); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaDifEncOffloadCmd_t, Dst_Data_Len), agDifEncOffload->DstDL); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaDifEncOffloadCmd_t, flags), agDifEncOffload->dif.flags); + + dw8 = agDifEncOffload->dif.udrtArray[1] << SHIFT24 | + agDifEncOffload->dif.udrtArray[0] << SHIFT16 | + agDifEncOffload->dif.udtArray[1] << SHIFT8 | + agDifEncOffload->dif.udtArray[0]; + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaDifEncOffloadCmd_t, UDTR01UDT01), dw8); + + dw9 = agDifEncOffload->dif.udtArray[5] << SHIFT24 | + agDifEncOffload->dif.udtArray[4] << SHIFT16 | + agDifEncOffload->dif.udtArray[3] << SHIFT8 | + agDifEncOffload->dif.udtArray[2]; + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaDifEncOffloadCmd_t, UDT2345), dw9); + dw10 = agDifEncOffload->dif.udrtArray[5] << SHIFT24 | + agDifEncOffload->dif.udrtArray[4] << SHIFT16 | + agDifEncOffload->dif.udrtArray[3] << SHIFT8 | + agDifEncOffload->dif.udrtArray[2]; + + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaDifEncOffloadCmd_t, UDTR2345), dw10); + + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaDifEncOffloadCmd_t, DPLR0SecCnt_IOSeed), + agDifEncOffload->dif.DIFPerLARegion0SecCount << SHIFT16 | + agDifEncOffload->dif.initialIOSeed); + + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaDifEncOffloadCmd_t, DPL_Addr_Lo) , agDifEncOffload->dif.DIFPerLAAddrLo); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaDifEncOffloadCmd_t, DPL_Addr_Hi) , agDifEncOffload->dif.DIFPerLAAddrHi); + + dw14 = agDifEncOffload->encrypt.dekInfo.dekIndex << SHIFT8 | + (agDifEncOffload->encrypt.dekInfo.dekTable & 0x3) << SHIFT2 | + (agDifEncOffload->encrypt.keyTagCheck & 0x1) << SHIFT1; + + if (agDifEncOffload->encrypt.cipherMode == agsaEncryptCipherModeXTS) + { + dw14 |= AGSA_ENCRYPT_XTS_Mode << SHIFT4; + } + else + { + dw14 |= (agDifEncOffload->encrypt.cipherMode & 0xF) << SHIFT4; + } + + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaDifEncOffloadCmd_t, KeyIndex_CMode_KTS_ENT_R), dw14); + + dw15 = agDifEncOffload->encrypt.EncryptionPerLRegion0SecCount << SHIFT16 | + (agDifEncOffload->encrypt.kekIndex & 0xF) << SHIFT5 | + (agDifEncOffload->encrypt.sectorSizeIndex & 0x1F); + + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaDifEncOffloadCmd_t, EPLR0SecCnt_KS_ENSS), dw15); + + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaDifEncOffloadCmd_t, keyTag_W0), agDifEncOffload->encrypt.keyTag_W0); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaDifEncOffloadCmd_t, keyTag_W1), agDifEncOffload->encrypt.keyTag_W1); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaDifEncOffloadCmd_t, tweakVal_W0), agDifEncOffload->encrypt.tweakVal_W0); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaDifEncOffloadCmd_t, tweakVal_W1), agDifEncOffload->encrypt.tweakVal_W1); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaDifEncOffloadCmd_t, tweakVal_W2), agDifEncOffload->encrypt.tweakVal_W2); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaDifEncOffloadCmd_t, tweakVal_W3), agDifEncOffload->encrypt.tweakVal_W3); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaDifEncOffloadCmd_t, EPL_Addr_Lo), agDifEncOffload->encrypt.EncryptionPerLAAddrLo); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaDifEncOffloadCmd_t, EPL_Addr_Hi), agDifEncOffload->encrypt.EncryptionPerLAAddrHi); + + si_memcpy((bit32 *) &(payload.SrcSgl), (bit32 *) &(agDifEncOffload->SrcSgl), sizeof(agsaSgl_t)); + si_memcpy((bit32 *) &(payload.DstSgl), (bit32 *) &(agDifEncOffload->DstSgl), sizeof(agsaSgl_t)); + + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_DIF_ENC_OFFLOAD_CMD, IOMB_SIZE128, queueNum); + + } + else + { + /* SPC does not support this command */ + ret = AGSA_RC_FAILURE; + } + + if (AGSA_RC_SUCCESS != ret) + { + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("mpiDIFEncryptionOffloadCmd: sending IOMB failed\n" )); + } + SA_DBG3(("mpiDIFEncryptionOffloadCmd: return value = %d\n", ret)); + } + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2b"); + + return ret; +} + diff --git a/sys/dev/pms/RefTisa/sallsdk/spc/sampidefs.h b/sys/dev/pms/RefTisa/sallsdk/spc/sampidefs.h new file mode 100644 index 000000000000..4c0931b0e5ed --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/spc/sampidefs.h @@ -0,0 +1,1969 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/*******************************************************************************/ +/*! \file sampidefs.h + * \brief The file defines the constants used by SAS/SATA LL layer + * + */ + +/*******************************************************************************/ + +#ifndef __SAMPIDEFS_H__ + +#define __SAMPIDEFS_H__ + +/* for Request Opcode of IOMB */ +#define OPC_INB_ECHO 0x001 /* */ + +#define OPC_INB_PHYSTART 0x004 /* */ +#define OPC_INB_PHYSTOP 0x005 /* */ +#define OPC_INB_SSPINIIOSTART 0x006 /* */ +#define OPC_INB_SSPINITMSTART 0x007 /* */ +#define OPC_INB_SSPINIEXTIOSTART 0x008 /* V reserved */ +#define OPC_INB_DEV_HANDLE_ACCEPT 0x009 /* */ +#define OPC_INB_SSPTGTIOSTART 0x00a /* */ +#define OPC_INB_SSPTGTRSPSTART 0x00b /* */ +#define OPC_INB_SSP_ABORT 0x00f /* */ +#define OPC_INB_DEREG_DEV_HANDLE 0x010 /* 16 */ +#define OPC_INB_GET_DEV_HANDLE 0x011 /* 17 */ +#define OPC_INB_SMP_REQUEST 0x012 /* 18 */ + +#define OPC_INB_SMP_ABORT 0x014 /* 20 */ + +#define OPC_INB_SPC_REG_DEV 0x016 /* 22 V reserved */ +#define OPC_INB_SATA_HOST_OPSTART 0x017 /* 23 */ +#define OPC_INB_SATA_ABORT 0x018 /* 24 */ +#define OPC_INB_LOCAL_PHY_CONTROL 0x019 /* 25 */ +#define OPC_INB_SPC_GET_DEV_INFO 0x01a /* 26 V reserved */ + +#define OPC_INB_FW_FLASH_UPDATE 0x020 /* 32 */ + +#define OPC_INB_GPIO 0x022 /* 34 */ +#define OPC_INB_SAS_DIAG_MODE_START_END 0x023 /* 35 */ +#define OPC_INB_SAS_DIAG_EXECUTE 0x024 /* 36 */ +#define OPC_INB_SPC_SAS_HW_EVENT_ACK 0x025 /* 37 V reserved */ +#define OPC_INB_GET_TIME_STAMP 0x026 /* 38 */ +#define OPC_INB_PORT_CONTROL 0x027 /* 39 */ +#define OPC_INB_GET_NVMD_DATA 0x028 /* 40 */ +#define OPC_INB_SET_NVMD_DATA 0x029 /* 41 */ +#define OPC_INB_SET_DEVICE_STATE 0x02a /* 42 */ +#define OPC_INB_GET_DEVICE_STATE 0x02b /* 43 */ +#define OPC_INB_SET_DEV_INFO 0x02c /* 44 */ +#define OPC_INB_SAS_RE_INITIALIZE 0x02d /* 45 V reserved */ +#define OPC_INB_SGPIO 0x02e /* 46 */ +#define OPC_INB_PCIE_DIAG_EXECUTE 0x02f /* 47 */ + +#define OPC_INB_SET_CONTROLLER_CONFIG 0x030 /* 48 */ +#define OPC_INB_GET_CONTROLLER_CONFIG 0x031 /* 49 */ + +#define OPC_INB_REG_DEV 0x032 /* 50 SPCV */ +#define OPC_INB_SAS_HW_EVENT_ACK 0x033 /* 51 SPCV */ +#define OPC_INB_GET_DEV_INFO 0x034 /* 52 SPCV */ +#define OPC_INB_GET_PHY_PROFILE 0x035 /* 53 SPCV */ +#define OPC_INB_FLASH_OP_EXT 0x036 /* 54 SPCV */ +#define OPC_INB_SET_PHY_PROFILE 0x037 /* 55 SPCV */ +#define OPC_INB_GET_DFE_DATA 0x038 /* 56 SPCV */ +#define OPC_INB_GET_VHIST_CAP 0x039 /* 57 SPCV12g */ + + +#define OPC_INB_KEK_MANAGEMENT 0x100 /* 256 SPCV */ +#define OPC_INB_DEK_MANAGEMENT 0x101 /* 257 SPCV */ +#define OPC_INB_SSP_DIF_ENC_OPSTART 0x102 /* 258 SPCV */ +#define OPC_INB_SATA_DIF_ENC_OPSTART 0x103 /* 259 SPCV */ +#define OPC_INB_OPR_MGMT 0x104 /* 260 SPCV */ +#define OPC_INB_ENC_TEST_EXECUTE 0x105 /* 261 SPCV */ +#define OPC_INB_SET_OPERATOR 0x106 /* 262 SPCV */ +#define OPC_INB_GET_OPERATOR 0x107 /* 263 SPCV */ +#define OPC_INB_DIF_ENC_OFFLOAD_CMD 0x110 /* 272 SPCV */ + +#define OPC_INB_FW_PROFILE 0x888 /* 2184 SPCV */ + +/* for Response Opcode of IOMB */ +#define OPC_OUB_ECHO 0x001 /* 1 */ + +#define OPC_OUB_SPC_HW_EVENT 0x004 /* 4 V reserved Now OPC_OUB_HW_EVENT */ +#define OPC_OUB_SSP_COMP 0x005 /* 5 */ +#define OPC_OUB_SMP_COMP 0x006 /* 6 */ +#define OPC_OUB_LOCAL_PHY_CNTRL 0x007 /* 7 */ + +#define OPC_OUB_SPC_DEV_REGIST 0x00a /* 10 V reserved Now OPC_OUB_DEV_REGIST */ +#define OPC_OUB_DEREG_DEV 0x00b /* 11 */ +#define OPC_OUB_GET_DEV_HANDLE 0x00c /* 12 */ +#define OPC_OUB_SATA_COMP 0x00d /* 13 */ +#define OPC_OUB_SATA_EVENT 0x00e /* 14 */ +#define OPC_OUB_SSP_EVENT 0x00f /* 15 */ + +#define OPC_OUB_SPC_DEV_HANDLE_ARRIV 0x010 /* 16 V reserved Now OPC_OUB_DEV_HANDLE_ARRIV */ + +#define OPC_OUB_SSP_RECV_EVENT 0x012 /* 18 */ +#define OPC_OUB_SPC_DEV_INFO 0x013 /* 19 V reserved Now OPC_OUB_DEV_INFO*/ +#define OPC_OUB_FW_FLASH_UPDATE 0x014 /* 20 */ + +#define OPC_OUB_GPIO_RESPONSE 0x016 /* 22 */ +#define OPC_OUB_GPIO_EVENT 0x017 /* 23 */ +#define OPC_OUB_GENERAL_EVENT 0x018 /* 24 */ + +#define OPC_OUB_SSP_ABORT_RSP 0x01a /* 26 */ +#define OPC_OUB_SATA_ABORT_RSP 0x01b /* 27 */ +#define OPC_OUB_SAS_DIAG_MODE_START_END 0x01c /* 28 */ +#define OPC_OUB_SAS_DIAG_EXECUTE 0x01d /* 29 */ +#define OPC_OUB_GET_TIME_STAMP 0x01e /* 30 */ +#define OPC_OUB_SPC_SAS_HW_EVENT_ACK 0x01f /* 31 V reserved Now OPC_OUB_SAS_HW_EVENT_ACK*/ +#define OPC_OUB_PORT_CONTROL 0x020 /* 32 */ +#define OPC_OUB_SKIP_ENTRY 0x021 /* 33 */ +#define OPC_OUB_SMP_ABORT_RSP 0x022 /* 34 */ +#define OPC_OUB_GET_NVMD_DATA 0x023 /* 35 */ +#define OPC_OUB_SET_NVMD_DATA 0x024 /* 36 */ +#define OPC_OUB_DEVICE_HANDLE_REMOVAL 0x025 /* 37 */ +#define OPC_OUB_SET_DEVICE_STATE 0x026 /* 38 */ +#define OPC_OUB_GET_DEVICE_STATE 0x027 /* 39 */ +#define OPC_OUB_SET_DEV_INFO 0x028 /* 40 */ +#define OPC_OUB_SAS_RE_INITIALIZE 0x029 /* 41 V reserved not replaced */ + +#define OPC_OUB_HW_EVENT 0x700 /* 1792 SPCV Was OPC_OUB_SPC_HW_EVENT*/ +#define OPC_OUB_DEV_HANDLE_ARRIV 0x720 /* 1824 SPCV Was OPC_OUB_SPC_DEV_HANDLE_ARRIV*/ + +#define OPC_OUB_PHY_START_RESPONSE 0x804 /* 2052 SPCV */ +#define OPC_OUB_PHY_STOP_RESPONSE 0x805 /* 2053 SPCV */ +#define OPC_OUB_SGPIO_RESPONSE 0x82E /* 2094 SPCV */ +#define OPC_OUB_PCIE_DIAG_EXECUTE 0x82F /* 2095 SPCV */ + +#define OPC_OUB_SET_CONTROLLER_CONFIG 0x830 /* 2096 SPCV */ +#define OPC_OUB_GET_CONTROLLER_CONFIG 0x831 /* 2097 SPCV */ +#define OPC_OUB_DEV_REGIST 0x832 /* 2098 SPCV */ +#define OPC_OUB_SAS_HW_EVENT_ACK 0x833 /* 2099 SPCV */ +#define OPC_OUB_DEV_INFO 0x834 /* 2100 SPCV */ +#define OPC_OUB_GET_PHY_PROFILE_RSP 0x835 /* 2101 SPCV */ +#define OPC_OUB_FLASH_OP_EXT_RSP 0x836 /* 2102 SPCV */ +#define OPC_OUB_SET_PHY_PROFILE_RSP 0x837 /* 2103 SPCV */ +#define OPC_OUB_GET_DFE_DATA_RSP 0x838 /* 2104 SPCV */ +#define OPC_OUB_GET_VIST_CAP_RSP 0x839 /* Can be 2104 for SPCV12g */ + +#define OPC_OUB_FW_PROFILE 0x888 /* 2184 */ + +#define OPC_OUB_KEK_MANAGEMENT 0x900 /* 2304 SPCV */ +#define OPC_OUB_DEK_MANAGEMENT 0x901 /* 2305 SPCV */ +#define OPC_OUB_COMBINED_SSP_COMP 0x902 /* 2306 SPCV */ +#define OPC_OUB_COMBINED_SATA_COMP 0x903 /* 2307 SPCV */ +#define OPC_OUB_OPR_MGMT 0x904 /* 2308 SPCV */ +#define OPC_OUB_ENC_TEST_EXECUTE 0x905 /* 2309 SPCV */ +#define OPC_OUB_SET_OPERATOR 0x906 /* 2310 SPCV */ +#define OPC_OUB_GET_OPERATOR 0x907 /* 2311 SPCV */ +#define OPC_OUB_DIF_ENC_OFFLOAD_RSP 0x910 /* 2320 SPCV */ + +/* Definitions for encryption key management */ +#define KEK_MGMT_SUBOP_INVALIDATE 0x1 +#define KEK_MGMT_SUBOP_UPDATE 0x2 +#define KEK_MGMT_SUBOP_KEYCARDINVALIDATE 0x3 +#define KEK_MGMT_SUBOP_KEYCARDUPDATE 0x4 + +#define DEK_MGMT_SUBOP_INVALIDATE 0x1 +#define DEK_MGMT_SUBOP_UPDATE 0x2 + +/*************************************************** + * typedef for IOMB structure + ***************************************************/ +/** \brief the data structure of Echo Command + * + * use to describe MPI Echo Command (64 bytes) + * + */ +typedef struct agsaEchoCmd_s { + bit32 tag; + bit32 payload[14]; +} agsaEchoCmd_t; + +/** \brief the data structure of PHY Start Command + * + * use to describe MPI PHY Start Command (64 bytes) + * + */ +typedef struct agsaPhyStartCmd_s { + bit32 tag; + bit32 SscdAseSHLmMlrPhyId; + agsaSASIdentify_t sasIdentify; + bit32 analogSetupIdx; + bit32 SAWT_DAWT; + bit32 reserved[5]; +} agsaPhyStartCmd_t; + +#define SPINHOLD_DISABLE (0x00 << 14) +#define SPINHOLD_ENABLE (0x01 << 14) +#define LINKMODE_SAS (0x01 << 12) +#define LINKMODE_DSATA (0x02 << 12) +#define LINKMODE_AUTO (0x03 << 12) +#define LINKRATE_15 (0x01 << 8) +#define LINKRATE_30 (0x02 << 8) +#define LINKRATE_60 (0x04 << 8) +#define LINKRATE_12 (0x08 << 8) + +/** \brief the data structure of PHY Stop Command + * + * use to describe MPI PHY Start Command (64 bytes) + * + */ +typedef struct agsaPhyStopCmd_s { + bit32 tag; + bit32 phyId; + bit32 reserved[13]; +} agsaPhyStopCmd_t; + +/** \brief the data structure of SSP INI IO Start Command + * + * use to describe MPI SSP INI IO Start Command (64 bytes) + * + */ +typedef struct agsaSSPIniIOStartCmd_s { + bit32 tag; + bit32 deviceId; + bit32 dataLen; + bit32 dirMTlr; + agsaSSPCmdInfoUnit_t SSPInfoUnit; + bit32 AddrLow0; + bit32 AddrHi0; + bit32 Len0; + bit32 E0; +} agsaSSPIniIOStartCmd_t; + +/** \brief the data structure of SSP INI TM Start Command + * + * use to describe MPI SSP INI TM Start Command (64 bytes) + * + */ +typedef struct agsaSSPIniTMStartCmd_s { + bit32 tag; + bit32 deviceId; + bit32 relatedTag; + bit32 TMfunction; + bit8 lun[8]; + bit32 dsAdsMReport; + bit32 reserved[8]; +} agsaSSPIniTMStartCmd_t; + +/** \brief the data structure of SSP INI Extended IO Start Command + * + * use to describe MPI SSP INI Extended CDB Start Command (96 bytes to support 32 CDB) + * + */ +typedef struct agsaSSPIniExtIOStartCmd_s { + bit32 tag; + bit32 deviceId; + bit32 dataLen; + bit32 SSPIuLendirMTlr; + bit8 SSPIu[1]; + /* variable lengh */ + /* bit32 AddrLow0; */ + /* bit32 AddrHi0; */ + /* bit32 Len0; */ + /* bit32 E0; */ +} agsaSSPIniExtIOStartCmd_t; + +typedef struct agsaSSPIniEncryptIOStartCmd_s +{ + bit32 tag; /* 1 */ + bit32 deviceId; /* 2 */ + bit32 dataLen; /* 3 */ + bit32 dirMTlr; /* 4 */ + bit32 sspiu_0_3_indcdbalL; /* 5 */ + bit32 sspiu_4_7_indcdbalH; /* 6 */ + bit32 sspiu_8_11; /* 7 */ + bit32 sspiu_12_15; /* 8 */ + bit32 sspiu_16_19; /* 9 */ + bit32 sspiu_19_23; /* 10 */ + bit32 sspiu_24_27; /* 11 */ + bit32 epl_descL; /* 12 */ + bit32 dpl_descL; /* 13 */ + bit32 edpl_descH; /* 14 */ + bit32 DIF_flags; /* 15 */ + bit32 udt; /* 16 0x10 */ + bit32 udtReplacementLo; /* 17 */ + bit32 udtReplacementHi; /* 18 */ + bit32 DIF_seed; /* 19 */ + bit32 encryptFlagsLo; /* 20 0x14 */ + bit32 encryptFlagsHi; /* 21 */ + bit32 keyTag_W0; /* 22 */ + bit32 keyTag_W1; /* 23 */ + bit32 tweakVal_W0; /* 24 0x18 */ + bit32 tweakVal_W1; /* 25 */ + bit32 tweakVal_W2; /* 26 */ + bit32 tweakVal_W3; /* 27 */ + bit32 AddrLow0; /* 28 0x1C */ + bit32 AddrHi0; /* 29 */ + bit32 Len0; /* 30 */ + bit32 E0; /* 31 */ +} agsaSSPIniEncryptIOStartCmd_t; + +/** \brief the data structure of SSP Abort Command + * + * use to describe MPI SSP Abort Command (64 bytes) + * + */ +typedef struct agsaSSPAbortCmd_s { + bit32 tag; + bit32 deviceId; + bit32 HTagAbort; + bit32 abortAll; + bit32 reserved[11]; +} agsaSSPAbortCmd_t; + +/** \brief the data structure of Register Device Command + * + * use to describe MPI DEVICE REGISTER Command (64 bytes) + * + */ +typedef struct agsaRegDevCmd_s { + bit32 tag; + bit32 phyIdportId; + bit32 dTypeLRateAwtHa; + bit32 ITNexusTimeOut; + bit32 sasAddrHi; + bit32 sasAddrLo; + bit32 DeviceId; + bit32 reserved[8]; +} agsaRegDevCmd_t; + +/** \brief the data structure of Deregister Device Handle Command + * + * use to describe MPI DEREGISTER DEVIDE HANDLE Command (64 bytes) + * + */ +typedef struct agsaDeregDevHandleCmd_s { + bit32 tag; + bit32 deviceId; + bit32 portId; + bit32 reserved[12]; +} agsaDeregDevHandleCmd_t; + +/** \brief the data structure of Get Device Handle Command + * + * use to describe MPI GET DEVIDE HANDLE Command (64 bytes) + * + */ +typedef struct agsaGetDevHandleCmd_s { + bit32 tag; + bit32 DevADevTMaxDIDportId; + bit32 skipCount; + bit32 reserved[12]; +} agsaGetDevHandleCmd_t; + +/** \brief the data structure of SMP Request Command + * + * use to describe MPI SMP REQUEST Command (64 bytes) + * + */ + +typedef struct agsaSMPCmd_s { + bit32 tag; + bit32 deviceId; + bit32 IR_IP_OV_res_phyId_DPdLen_res; + /* Bits [0] - IR */ + /* Bits [1] - IP */ + /* Bits [15:2] - Reserved */ + /* Bits [23:16] - Len */ + /* Bits [31:24] - Reserved */ + bit32 SMPCmd[12]; +} agsaSMPCmd_t; + + +typedef struct agsaSMPCmd_V_s { + bit32 tag; /* 1 */ + bit32 deviceId; /* 2 */ + bit32 IR_IP_OV_res_phyId_DPdLen_res;/* 3 */ + /* Bits [0] - IR */ + /* Bits [1] - IP */ + /* Bits [15:2] - Reserved */ + /* Bits [23:16] - Len */ + /* Bits [31:24] - Reserved */ + bit32 SMPHDR; /* 4 */ + bit32 SMP3_0; /* 5 */ + bit32 SMP7_4; /* 6 */ + bit32 SMP11_8; /* 7 */ + bit32 IndirL_SMPRF15_12; /* 8 */ + bit32 IndirH_or_SMPRF19_16; /* 9 */ + bit32 IndirLen_or_SMPRF23_20; /* 10 */ + bit32 R_or_SMPRF27_24; /* 11 */ + bit32 ISRAL_or_SMPRF31_28; /* 12 */ + bit32 ISRAH_or_SMPRF35_32; /* 13 */ + bit32 ISRL_or_SMPRF39_36; /* 14 */ + bit32 R_or_SMPRF43_40; /* 15 */ +} agsaSMPCmd_V_t; + +/** \brief the data structure of SMP Abort Command + * + * use to describe MPI SMP Abort Command (64 bytes) + * + */ +typedef struct agsaSMPAbortCmd_s { + bit32 tag; + bit32 deviceId; + bit32 HTagAbort; + bit32 Scp; + bit32 reserved[11]; +} agsaSMPAbortCmd_t; + +/** \brief the data structure of SATA Start Command + * + * use to describe MPI SATA Start Command (64 bytes) + * + */ +typedef struct agsaSATAStartCmd_s { + bit32 tag; /* 1 */ + bit32 deviceId; /* 2 */ + bit32 dataLen; /* 3 */ + bit32 optNCQTagataProt; /* 4 */ + agsaFisRegHostToDevice_t sataFis; /* 5 6 7 8 9 */ + bit32 reserved1; /* 10 */ + bit32 reserved2; /* 11 */ + bit32 AddrLow0; /* 12 */ + bit32 AddrHi0; /* 13 */ + bit32 Len0; /* 14 */ + bit32 E0; /* 15 */ + bit32 ATAPICDB[4]; /* 16-19 */ +} agsaSATAStartCmd_t; + +typedef struct agsaSATAEncryptStartCmd_s +{ + bit32 tag; /* 1 */ + bit32 IniDeviceId; /* 2 */ + bit32 dataLen; /* 3 */ + bit32 optNCQTagataProt; /* 4 */ + agsaFisRegHostToDevice_t sataFis; /* 5 6 7 8 9 */ + bit32 reserved1; /* 10 */ + bit32 Res_EPL_DESCL; /* 11 */ + bit32 resSKIPBYTES; /* 12 */ + bit32 Res_DPL_DESCL_NDPLR; /* 13 DIF per LA Address lo if DPLE is 1 */ + bit32 Res_EDPL_DESCH; /* 14 DIF per LA Address hi if DPLE is 1 */ + bit32 DIF_flags; /* 15 */ + bit32 udt; /* 16 */ + bit32 udtReplacementLo; /* 17 */ + bit32 udtReplacementHi; /* 18 */ + bit32 DIF_seed; /* 19 */ + bit32 encryptFlagsLo; /* 20 */ + bit32 encryptFlagsHi; /* 21 */ + bit32 keyTagLo; /* 22 */ + bit32 keyTagHi; /* 23 */ + bit32 tweakVal_W0; /* 24 */ + bit32 tweakVal_W1; /* 25 */ + bit32 tweakVal_W2; /* 26 */ + bit32 tweakVal_W3; /* 27 */ + bit32 AddrLow0; /* 28 */ + bit32 AddrHi0; /* 29 */ + bit32 Len0; /* 30 */ + bit32 E0; /* 31 */ +} agsaSATAEncryptStartCmd_t; + +/** \brief the data structure of SATA Abort Command + * + * use to describe MPI SATA Abort Command (64 bytes) + * + */ +typedef struct agsaSATAAbortCmd_s { + bit32 tag; + bit32 deviceId; + bit32 HTagAbort; + bit32 abortAll; + bit32 reserved[11]; +} agsaSATAAbortCmd_t; + +/** \brief the data structure of Local PHY Control Command + * + * use to describe MPI LOCAL PHY CONTROL Command (64 bytes) + * + */ +typedef struct agsaLocalPhyCntrlCmd_s { + bit32 tag; + bit32 phyOpPhyId; + bit32 reserved1[14]; +} agsaLocalPhyCntrlCmd_t; + +/** \brief the data structure of Get Device Info Command + * + * use to describe MPI GET DEVIDE INFO Command (64 bytes) + * + */ +typedef struct agsaGetDevInfoCmd_s { + bit32 tag; + bit32 DeviceId; + bit32 reserved[13]; +} agsaGetDevInfoCmd_t; + +/** \brief the data structure of HW Reset Command + * + * use to describe MPI HW Reset Command (64 bytes) + * + */ +typedef struct agsaHWResetCmd_s { + bit32 option; + bit32 reserved[14]; +} agsaHWResetCmd_t; + +/** \brief the data structure of Firmware download + * + * use to describe MPI FW DOWNLOAD Command (64 bytes) + */ +typedef struct agsaFwFlashUpdate_s { + bit32 tag; + bit32 curImageOffset; + bit32 curImageLen; + bit32 totalImageLen; + bit32 reserved0[7]; + bit32 SGLAL; + bit32 SGLAH; + bit32 Len; + bit32 extReserved; +} agsaFwFlashUpdate_t; + + +/** \brief the data structure EXT Flash Op + * + * use to describe Extented Flash Operation Command (128 bytes) + */ +typedef struct agsaFwFlashOpExt_s { + bit32 tag; + bit32 Command; + bit32 PartOffset; + bit32 DataLength; + bit32 Reserved0[7]; + bit32 SGLAL; + bit32 SGLAH; + bit32 Len; + bit32 E_sgl; + bit32 Reserved[15]; +} agsaFwFlashOpExt_t; + +/** \brief the data structure EXT Flash Op + * + * use to describe Extented Flash Operation Command (64 bytes) + */ +typedef struct agsaFwFlashOpExtRsp_s { + bit32 tag; + bit32 Command; + bit32 Status; + bit32 Epart_Size; + bit32 EpartSectSize; + bit32 Reserved[10]; +} agsaFwFlashOpExtRsp_t; + + +#define FWFLASH_IOMB_RESERVED_LEN 0x07 + +#ifdef SPC_ENABLE_PROFILE +typedef struct agsaFwProfileIOMB_s { + bit32 tag; + bit32 tcid_processor_cmd; + bit32 codeStartAdd; + bit32 codeEndAdd; + bit32 reserved0[7]; + bit32 SGLAL; + bit32 SGLAH; + bit32 Len; + bit32 extReserved; +} agsaFwProfileIOMB_t; +#define FWPROFILE_IOMB_RESERVED_LEN 0x07 +#endif +/** \brief the data structure of GPIO Commannd + * + * use to describe MPI GPIO Command (64 bytes) + */ +typedef struct agsaGPIOCmd_s { + bit32 tag; + bit32 eOBIDGeGsGrGw; + bit32 GpioWrMsk; + bit32 GpioWrVal; + bit32 GpioIe; + bit32 OT11_0; + bit32 OT19_12; /* reserved for SPCv controller */ + bit32 GPIEVChange; + bit32 GPIEVRise; + bit32 GPIEVFall; + bit32 reserved[5]; +} agsaGPIOCmd_t; + + +#define GPIO_GW_BIT 0x1 +#define GPIO_GR_BIT 0x2 +#define GPIO_GS_BIT 0x4 +#define GPIO_GE_BIT 0x8 + +/** \brief the data structure of SAS Diagnostic Start/End Command + * + * use to describe MPI SAS Diagnostic Start/End Command (64 bytes) + */ +typedef struct agsaSASDiagStartEndCmd_s { + bit32 tag; + bit32 OperationPhyId; + bit32 reserved[13]; +} agsaSASDiagStartEndCmd_t; + +/** \brief the data structure of SAS Diagnostic Execute Command + * + * use to describe MPI SAS Diagnostic Execute Command for SPCv (128 bytes) + */ +typedef struct agsaSASDiagExecuteCmd_s { + bit32 tag; /* 1 */ + bit32 CmdTypeDescPhyId;/* 2 */ + bit32 Pat1Pat2; /* 3 */ + bit32 Threshold; /* 4 */ + bit32 CodePatErrMsk; /* 5 */ + bit32 Pmon; /* 6 */ + bit32 PERF1CTL; /* 7 */ + bit32 THRSHLD1; /* 8 */ + bit32 reserved[23]; /* 9 31 */ +} agsaSASDiagExecuteCmd_t; + + +/** \brief the data structure of SAS Diagnostic Execute Command + * + * use to describe MPI SAS Diagnostic Execute Command for SPC (64 bytes) + */ +typedef struct agsa_SPC_SASDiagExecuteCmd_s { + bit32 tag; /* 1 */ + bit32 CmdTypeDescPhyId;/* 2 */ + bit32 Pat1Pat2; /* 3 */ + bit32 Threshold; /* 4 */ + bit32 CodePatErrMsk; /* 5 */ + bit32 Pmon; /* 6 */ + bit32 PERF1CTL; /* 7 */ + bit32 reserved[8]; /* 8 15 */ +} agsa_SPC_SASDiagExecuteCmd_t; +#define SAS_DIAG_PARAM_BYTES 24 + + +/** \brief the data structure of SSP TGT IO Start Command + * + * use to describe MPI SSP TGT IO Start Command (64 bytes) + * + */ +typedef struct agsaSSPTgtIOStartCmd_s { + bit32 tag; /* 1 */ + bit32 deviceId; /* 2 */ + bit32 dataLen; /* 3 */ + bit32 dataOffset; /* 4 */ + bit32 INITagAgrDir; /* 5 */ + bit32 reserved; /* 6 */ + bit32 DIF_flags; /* 7 */ + bit32 udt; /* 8 */ + bit32 udtReplacementLo; /* 9 */ + bit32 udtReplacementHi; /* 10 */ + bit32 DIF_seed; /* 11 */ + bit32 AddrLow0; /* 12 */ + bit32 AddrHi0; /* 13 */ + bit32 Len0; /* 14 */ + bit32 E0; /* 15 */ +} agsaSSPTgtIOStartCmd_t; + +/** \brief the data structure of SSP TGT Response Start Command + * + * use to describe MPI SSP TGT Response Start Command (64 bytes) + * + */ +typedef struct agsaSSPTgtRspStartCmd_s { + bit32 tag; + bit32 deviceId; + bit32 RspLen; + bit32 INITag_IP_AN; + bit32 reserved[7]; + bit32 AddrLow0; + bit32 AddrHi0; + bit32 Len0; + bit32 E0; +} agsaSSPTgtRspStartCmd_t; + +/** \brief the data structure of Device Handle Accept Command + * + * use to describe MPI Device Handle Accept Command (64 bytes) + * + */ +typedef struct agsaDevHandleAcceptCmd_s { + bit32 tag; + bit32 Ctag; + bit32 deviceId; + bit32 DevA_MCN_R_R_HA_ITNT; + bit32 reserved[11]; +} agsaDevHandleAcceptCmd_t; + +/** \brief the data structure of SAS HW Event Ack Command + * + * use to describe MPI SAS HW Event Ack Command (64 bytes) + * + */ +typedef struct agsaSASHwEventAckCmd_s { + bit32 tag; + bit32 sEaPhyIdPortId; + bit32 Param0; + bit32 Param1; + bit32 reserved[11]; +} agsaSASHwEventAckCmd_t; + +/** \brief the data structure of Get Time Stamp Command + * + * use to describe MPI Get Time Stamp Command (64 bytes) + * + */ +typedef struct agsaGetTimeStampCmd_s { + bit32 tag; + bit32 reserved[14]; +} agsaGetTimeStampCmd_t; + +/** \brief the data structure of Port Control Command + * + * use to describe MPI Port Control Command (64 bytes) + * + */ +typedef struct agsaPortControlCmd_s { + bit32 tag; + bit32 portOPPortId; + bit32 Param0; + bit32 Param1; + bit32 reserved[11]; +} agsaPortControlCmd_t; + +/** \brief the data structure of Set NVM Data Command + * + * use to describe MPI Set NVM Data Command (64 bytes) + * + */ +typedef struct agNVMIndirect_s { + bit32 signature; + bit32 reserved[7]; + bit32 ISglAL; + bit32 ISglAH; + bit32 ILen; + bit32 reserved1; +} agNVMIndirect_t; + +typedef union agsaSetNVMData_s { + bit32 NVMData[12]; + agNVMIndirect_t indirectData; +} agsaSetNVMData_t; + +typedef struct agsaSetNVMDataCmd_s { + bit32 tag; + bit32 LEN_IR_VPDD; + bit32 VPDOffset; + agsaSetNVMData_t Data; +} agsaSetNVMDataCmd_t; + +/** \brief the data structure of Get NVM Data Command + * + * use to describe MPI Get NVM Data Command (64 bytes) + * + */ +typedef struct agsaGetNVMDataCmd_s { + bit32 tag; + bit32 LEN_IR_VPDD; + bit32 VPDOffset; + bit32 reserved[8]; + bit32 respAddrLo; + bit32 respAddrHi; + bit32 respLen; + bit32 reserved1; +} agsaGetNVMDataCmd_t; + +#define TWI_DEVICE 0x0 +#define C_SEEPROM 0x1 +#define VPD_FLASH 0x4 +#define AAP1_RDUMP 0x5 +#define IOP_RDUMP 0x6 +#define EXPAN_ROM 0x7 + +#define DIRECT_MODE 0x0 +#define INDIRECT_MODE 0x1 + +#define IRMode 0x80000000 +#define IPMode 0x80000000 +#define NVMD_TYPE 0x0000000F +#define NVMD_STAT 0x0000FFFF +#define NVMD_LEN 0xFF000000 + +#define TWI_DEVICE 0x0 +#define SEEPROM 0x1 + +/** \brief the data structure of Set Device State Command + * + * use to describe MPI Set Device State Command (64 bytes) + * + */ +typedef struct agsaSetDeviceStateCmd_s { + bit32 tag; + bit32 deviceId; + bit32 NDS; + bit32 reserved[12]; +} agsaSetDeviceStateCmd_t; + +#define DS_OPERATIONAL 0x01 +#define DS_IN_RECOVERY 0x03 +#define DS_IN_ERROR 0x04 +#define DS_NON_OPERATIONAL 0x07 + +/** \brief the data structure of Get Device State Command + * + * use to describe MPI Get Device State Command (64 bytes) + * + */ +typedef struct agsaGetDeviceStateCmd_s { + bit32 tag; + bit32 deviceId; + bit32 reserved[13]; +} agsaGetDeviceStateCmd_t; + +/** \brief the data structure of Set Device Info Command + * + * use to describe MPI OPC_INB_SET_DEV_INFO (0x02c) Command (64 bytes) + * + */ +typedef struct agsaSetDevInfoCmd_s { + bit32 tag; + bit32 deviceId; + bit32 SA_SR_SI; + bit32 DEVA_MCN_R_ITNT; + bit32 reserved[11]; +} agsaSetDevInfoCmd_t; + +#define SET_DEV_INFO_V_DW3_MASK 0x0000003F +#define SET_DEV_INFO_V_DW4_MASK 0xFF07FFFF +#define SET_DEV_INFO_SPC_DW3_MASK 0x7 +#define SET_DEV_INFO_SPC_DW4_MASK 0x003FFFF + +#define SET_DEV_INFO_V_DW3_SM_SHIFT 3 +#define SET_DEV_INFO_V_DW3_SA_SHIFT 2 +#define SET_DEV_INFO_V_DW3_SR_SHIFT 1 +#define SET_DEV_INFO_V_DW3_SI_SHIFT 0 + +#define SET_DEV_INFO_V_DW4_MCN_SHIFT 24 +#define SET_DEV_INFO_V_DW4_AWT_SHIFT 17 +#define SET_DEV_INFO_V_DW4_RETRY_SHIFT 16 +#define SET_DEV_INFO_V_DW4_ITNEXUS_SHIFT 0 + +/** \brief the data structure of SAS Re_Initialize Command + * + * use to describe MPI SAS RE_INITIALIZE Command (64 bytes) + * + */ +typedef struct agsaSasReInitializeCmd_s { + bit32 tag; + bit32 setFlags; + bit32 MaxPorts; + bit32 openRejReCmdData; + bit32 sataHOLTMO; + bit32 reserved[10]; +} agsaSasReInitializeCmd_t; + + +/** \brief the data structure of SGPIO Command + * + * use to describe MPI serial GPIO Command (64 bytes) + * + */ +typedef struct agsaSGpioCmd_s { + bit32 tag; + bit32 regIndexRegTypeFunctionFrameType; + bit32 regCount; + bit32 writeData[OSSA_SGPIO_MAX_WRITE_DATA_COUNT]; +} agsaSGpioCmd_t; + +/** \brief the data structure of PCIE Diagnostic Command + * + * use to describe MPI PCIE Diagnostic Command for SPCv (128 bytes) + * + */ +typedef struct agsaPCIeDiagExecuteCmd_s { + bit32 tag; /* 1 */ + bit32 CmdTypeDesc; /* 2 */ + bit32 UUM_EDA; /* 3 */ + bit32 UDTR1_UDT0; /* 4 */ + bit32 UDT5_UDT2; /* 5 */ + bit32 UDTR5_UDTR2; /* 6 */ + bit32 Res_IOS; /* 7 */ + bit32 rdAddrLower; /* 8 */ + bit32 rdAddrUpper; /* 9 */ + bit32 wrAddrLower; /* 10 */ + bit32 wrAddrUpper; /* 11 */ + bit32 len; /* 12 */ + bit32 pattern; /* 13 */ + bit32 reserved2[2]; /* 14 15 */ + bit32 reserved3[16]; /* 15 31 */ +} agsaPCIeDiagExecuteCmd_t; + + +/** \brief the data structure of PCI Diagnostic Command for SPC + * + * use to describe MPI PCI Diagnostic Command for SPC (64 bytes) + * + */ +typedef struct agsa_SPC_PCIDiagExecuteCmd_s { + bit32 tag; + bit32 CmdTypeDesc; + bit32 reserved1[5]; + bit32 rdAddrLower; + bit32 rdAddrUpper; + bit32 wrAddrLower; + bit32 wrAddrUpper; + bit32 len; + bit32 pattern; + bit32 reserved2[2]; +} agsa_SPC_PCIDiagExecuteCmd_t; + +/** \brief the data structure of GET DFE Data Command + * + * use to describe GET DFE Data Command for SPCv (128 bytes) + * + */ +typedef struct agsaGetDDEFDataCmd_s { + bit32 tag; /* 1 */ + bit32 reserved_In_Ln;/* 2 */ + bit32 MCNT; /* 3 */ + bit32 reserved1[3]; /* 4 - 6 */ + bit32 Buf_AddrL; /* 7 */ + bit32 Buf_AddrH; /* 8 */ + bit32 Buf_Len; /* 9 */ + bit32 E_reserved; /* 10 */ + bit32 reserved2[21]; /* 11 - 31 */ +} agsaGetDDEFDataCmd_t; + + +/*********************************************** + * outbound IOMBs + ***********************************************/ +/** \brief the data structure of Echo Response + * + * use to describe MPI Echo Response (64 bytes) + * + */ +typedef struct agsaEchoRsp_s { + bit32 tag; + bit32 payload[14]; +} agsaEchoRsp_t; + +/** \brief the data structure of HW Event from Outbound + * + * use to describe MPI HW Event (64 bytes) + * + */ +typedef struct agsaHWEvent_SPC_OUB_s { + bit32 LRStatusEventPhyIdPortId; + bit32 EVParam; + bit32 NpipPortState; + agsaSASIdentify_t sasIdentify; + agsaFisRegDeviceToHost_t sataFis; +} agsaHWEvent_SPC_OUB_t; + +#define PHY_ID_BITS 0x000000F0 +#define LINK_RATE_MASK 0xF0000000 +#define STATUS_BITS 0x0F000000 +#define HW_EVENT_BITS 0x00FFFF00 + +typedef struct agsaHWEvent_Phy_OUB_s { + bit32 tag; + bit32 Status; + bit32 ReservedPhyId; +} agsaHWEvent_Phy_OUB_t; + +/** \brief the data structure of HW Event from Outbound + * + * use to describe MPI HW Event (64 bytes) + * + */ +typedef struct agsaHWEvent_V_OUB_s { + bit32 LRStatEventPortId; + bit32 EVParam; + bit32 RsvPhyIdNpipRsvPortState; + agsaSASIdentify_t sasIdentify; + agsaFisRegDeviceToHost_t sataFis; +} agsaHWEvent_V_OUB_t; + +#define PHY_ID_V_BITS 0x00FF0000 +#define NIPP_V_BITS 0x0000FF00 + + + +/** \brief the data structure of SSP Completion Response + * + * use to describe MPI SSP Completion Response (1024 bytes) + * + */ +typedef struct agsaSSPCompletionRsp_s { + bit32 tag; + bit32 status; + bit32 param; + bit32 SSPTag; + agsaSSPResponseInfoUnit_t SSPrsp; + bit32 respData; + bit32 senseData[5]; + bit32 respData1[239]; +} agsaSSPCompletionRsp_t; + + +/** \brief the data structure of SSP Completion DIF Response + * + * use to describe MPI SSP Completion DIF Response (1024 bytes) + * + */ +typedef struct agsaSSPCompletionDifRsp_s { + bit32 tag; + bit32 status; + bit32 param; + bit32 SSPTag; + bit32 Device_Id; + bit32 UpperLBA; + bit32 LowerLBA; + bit32 sasAddressHi; + bit32 sasAddressLo; + bit32 ExpectedCRCUDT01; + bit32 ExpectedUDT2345; + bit32 ActualCRCUDT01; + bit32 ActualUDT2345; + bit32 DIFErrDevID; + bit32 ErrBoffsetEDataLen; + bit32 EDATA_FRM; + +} agsaSSPCompletionDifRsp_t; + + +/* SSPTag bit fields Bits [31:16] */ +#define SSP_RESCV_BIT 0x00010000 /* Bits [16] */ +#define SSP_RESCV_PAD 0x00060000 /* Bits [18:17] */ +#define SSP_RESCV_PAD_SHIFT 17 +#define SSP_AGR_S_BIT (1 << 19) /* Bits [19] */ + +/** \brief the data structure of SMP Completion Response + * + * use to describe MPI SMP Completion Response (1024 bytes) + * + */ +typedef struct agsaSMPCompletionRsp_s { + bit32 tag; + bit32 status; + bit32 param; + bit32 SMPrsp[252]; +} agsaSMPCompletionRsp_t; + +/** \brief the data structure of Deregister Device Response + * + * use to describe MPI Deregister Device Response (64 bytes) + * + */ +typedef struct agsaDeregDevHandleRsp_s { + bit32 tag; + bit32 status; + bit32 deviceId; + bit32 reserved[12]; +} agsaDeregDevHandleRsp_t; + +/** \brief the data structure of Get Device Handle Response + * + * use to describe MPI Get Device Handle Response (64 bytes) + * + */ +typedef struct agsaGetDevHandleRsp_s { + bit32 tag; + bit32 DeviceIdcPortId; + bit32 deviceId[13]; +} agsaGetDevHandleRsp_t; + +#define DEVICE_IDC_BITS 0x00FFFF00 +#define DEVICE_ID_BITS 0x00000FFF + +/** \brief the data structure of Local Phy Control Response + * + * use to describe MPI Local Phy Control Response (64 bytes) + * + */ +typedef struct agsaLocalPhyCntrlRsp_s { + bit32 tag; + bit32 phyOpId; + bit32 status; + bit32 reserved[12]; +} agsaLocalPhyCntrlRsp_t; + +#define LOCAL_PHY_OP_BITS 0x0000FF00 +#define LOCAL_PHY_PHYID 0x000000FF + +/** \brief the data structure of DEVICE_REGISTRATION Response + * + * use to describe device registration response (64 bytes) + * + */ +typedef struct agsaDeviceRegistrationRsp_s { + bit32 tag; + bit32 status; + bit32 deviceId; + bit32 reserved[12]; +} agsaDeviceRegistrationRsp_t; + + +#define FAILURE_OUT_OF_RESOURCE 0x01 /* The device registration failed because the SPC 8x6G is running out of device handle resources. The parameter DEVICE_ID is not used. */ +#define FAILURE_DEVICE_ALREADY_REGISTERED 0x02 /* The device registration failed because the SPC 8x6G detected an existing device handle with a similar SAS address. The parameter DEVICE_ID contains the existing DEVICE _ID assigned to the SAS device. */ +#define FAILURE_INVALID_PHY_ID 0x03 /* Only for directly-attached SATA registration. The device registration failed because the SPC 8x6G detected an invalid (out-of-range) PHY ID. */ +#define FAILURE_PHY_ID_ALREADY_REGISTERED 0x04 /* Only for directly-attached SATA registration. The device registration failed because the SPC 8x6G detected an already -registered PHY ID for a directly attached SATA drive. */ +#define FAILURE_PORT_ID_OUT_OF_RANGE 0x05 /* PORT_ID specified in the REGISTER_DEVICE Command is out-of range (0-7). */ +#define FAILURE_PORT_NOT_VALID_STATE 0x06 /* The PORT_ID specified in the REGISTER_DEVICE Command is not in PORT_VALID state. */ +#define FAILURE_DEVICE_TYPE_NOT_VALID 0x07 /* The device type, specified in the ‘S field in the REGISTER_DEVICE Command is not valid. */ + +#define MPI_ERR_DEVICE_HANDLE_UNAVAILABLE 0x1020 /* The device registration failed because the SPCv controller is running out of device handle resources. The parameter DEVICE_ID is not used. */ +#define MPI_ERR_DEVICE_ALREADY_REGISTERED 0x1021 /* The device registration failed because the SPCv controller detected an existing device handle with the same SAS address. The parameter DEVICE_ID contains the existing DEVICE _ID assigned to the SAS device. */ +#define MPI_ERR_DEVICE_TYPE_NOT_VALID 0x1022 /* The device type, specified in the ‘S field in the REGISTER_DEVICE_HANDLE Command (page 274) is not valid. */ +#define MPI_ERR_PORT_INVALID_PORT_ID 0x1041 /* specified in the REGISTER_DEVICE_HANDLE Command (page 274) is invalid. i.e Out of supported range */ +#define MPI_ERR_PORT_STATE_NOT_VALID 0x1042 /* The PORT_ID specified in the REGISTER_DEVICE_HANDLE Command (page 274) is not in PORT_VALID state. */ +#define MPI_ERR_PORT_STATE_NOT_IN_USE 0x1043 +#define MPI_ERR_PORT_OP_NOT_SUPPORTED 0x1044 +#define MPI_ERR_PORT_SMP_PHY_WIDTH_EXCEED 0x1045 +#define MPI_ERR_PORT_NOT_IN_CORRECT_STATE 0x1047 /*MPI_ERR_DEVICE_ACCEPT_PENDING*/ + + +#define MPI_ERR_PHY_ID_INVALID 0x1061 /* Only for directly-attached SATA registration. The device registration failed because the SPCv controller detected an invalid (out-of-range) PHY ID. */ +#define MPI_ERR_PHY_ID_ALREADY_REGISTERED 0x1062 /* Only for directly-attached SATA registration. The device registration failed because the SPCv controller detected an alreadyregistered PHY ID for a directly-attached SATA drive. */ + + + + +/** \brief the data structure of SATA Completion Response + * + * use to describe MPI SATA Completion Response (64 bytes) + * + */ +typedef struct agsaSATACompletionRsp_s { + bit32 tag; + bit32 status; + bit32 param; + bit32 FSATArsp; + bit32 respData[11]; +} agsaSATACompletionRsp_t; + +/** \brief the data structure of SATA Event Response + * + * use to describe MPI SATA Event Response (64 bytes) + * + */ +typedef struct agsaSATAEventRsp_s { + bit32 tag; + bit32 event; + bit32 portId; + bit32 deviceId; + bit32 reserved[11]; +} agsaSATAEventRsp_t; + +/** \brief the data structure of SSP Event Response + * + * use to describe MPI SSP Event Response (64 bytes) + * + */ +typedef struct agsaSSPEventRsp_s { + bit32 tag; + bit32 event; + bit32 portId; + bit32 deviceId; + bit32 SSPTag; + bit32 EVT_PARAM0_or_LBAH; + bit32 EVT_PARAM1_or_LBAL; + bit32 SAS_ADDRH; + bit32 SAS_ADDRL; + bit32 UDT1_E_UDT0_E_CRC_E; + bit32 UDT5_E_UDT4_E_UDT3_E_UDT2_E; + bit32 UDT1_A_UDT0_A_CRC_A; + bit32 UDT5_A_UDT4_A_UDT3_A_UDT2_A; + bit32 HW_DEVID_Reserved_DIF_ERR; + bit32 EDATA_LEN_ERR_BOFF; + bit32 EDATA_FRM; +} agsaSSPEventRsp_t; + +#define SSPTAG_BITS 0x0000FFFF + +/** \brief the data structure of Get Device Info Response + * + * use to describe MPI Get Device Info Response (64 bytes) + * + */ +typedef struct agsaGetDevInfoRspSpc_s { + bit32 tag; + bit32 status; + bit32 deviceId; + bit32 dTypeSrateSMPTOArPortID; + bit32 FirstBurstSizeITNexusTimeOut; + bit8 sasAddrHi[4]; + bit8 sasAddrLow[4]; + bit32 reserved[8]; +} agsaGetDevInfoRsp_t; + +#define SMPTO_BITS 0xFFFF +#define NEXUSTO_BITS 0xFFFF +#define FIRST_BURST 0xFFFF +#define FLAG_BITS 0x3 +#define LINK_RATE_BITS 0xFF +#define DEV_TYPE_BITS 0x30000000 + +/** \brief the data structure of Get Device Info Response V + * + * use to describe MPI Get Device Info Response (64 bytes) + * + */ +typedef struct agsaGetDevInfoRspV_s { + bit32 tag; + bit32 status; + bit32 deviceId; + bit32 ARSrateSMPTimeOutPortID; + bit32 IRMcnITNexusTimeOut; + bit8 sasAddrHi[4]; + bit8 sasAddrLow[4]; + bit32 reserved[8]; +} agsaGetDevInfoRspV_t; + +#define SMPTO_VBITS 0xFFFF +#define NEXUSTO_VBITS 0xFFFF +#define FIRST_BURST_MCN 0xF +#define FLAG_VBITS 0x3 +#define LINK_RATE_VBITS 0xFF +#define DEV_TYPE_VBITS 0x10000000 + + +/** \brief the data structure of Get Phy Profile Command IOMB V + * + */ +typedef struct agsaGetPhyProfileCmd_V_s { + bit32 tag; + bit32 Reserved_Ppc_SOP_PHYID; + bit32 reserved[29]; +} agsaGetPhyProfileCmd_V_t; + + +/** \brief the data structure of Get Phy Profile Response IOMB V + * + */ +typedef struct agsaGetPhyProfileRspV_s { + bit32 tag; + bit32 status; + bit32 Reserved_Ppc_SOP_PHYID; + bit32 PageSpecificArea[12]; +} agsaGetPhyProfileRspV_t; + +/** \brief the data structure of Set Phy Profile Command IOMB V + * + */ +typedef struct agsaSetPhyProfileCmd_V_s { + bit32 tag; + bit32 Reserved_Ppc_SOP_PHYID; + bit32 PageSpecificArea[29]; +} agsaSetPhyProfileCmd_V_t; + +/** \brief the data structure of GetVis Command IOMB V + * OPC_OUB_GET_VIST_CAP_RSP + */ +typedef struct agsaGetVHistCap_V_s { + bit32 tag; + bit32 Channel; + bit32 NumBitLo; + bit32 NumBitHi; + bit32 reserved0; + bit32 reserved1; + bit32 PcieAddrLo; + bit32 PcieAddrHi; + bit32 ByteCount; + bit32 reserved2[22]; +} agsaGetVHistCap_V_t; + +/** \brief the data structure of Set Phy Profile Response IOMB V + * + */ +typedef struct agsaSetPhyProfileRspV_s { + bit32 tag; + bit32 status; + bit32 Reserved_Ppc_PHYID; + bit32 PageSpecificArea[12]; +} agsaSetPhyProfileRspV_t; + +typedef struct agsaGetPhyInfoV_s { + bit32 tag; + bit32 Reserved_SOP_PHYID; + bit32 reserved[28]; +} agsaGetPhyInfoV_t; + + +#define SPC_GET_SAS_PHY_ERR_COUNTERS 1 +#define SPC_GET_SAS_PHY_ERR_COUNTERS_CLR 2 +#define SPC_GET_SAS_PHY_BW_COUNTERS 3 + + +/** \brief the data structure of FW_FLASH_UPDATE Response + * + * use to describe MPI FW_FLASH_UPDATE Response (64 bytes) + * + */ +typedef struct agsaFwFlashUpdateRsp_s { + bit32 tag; + bit32 status; + bit32 reserved[13]; +} agsaFwFlashUpdateRsp_t; + +#ifdef SPC_ENABLE_PROFILE +typedef struct agsaFwProfileRsp_s { + bit32 tag; + bit32 status; + bit32 len; + bit32 reserved[12]; +} agsaFwProfileRsp_t; +#endif +/** \brief the data structure of GPIO Response + * + * use to describe MPI GPIO Response (64 bytes) + */ +typedef struct agsaGPIORsp_s { + bit32 tag; + bit32 reserved[2]; + bit32 GpioRdVal; + bit32 GpioIe; + bit32 OT11_0; + bit32 OT19_12; + bit32 GPIEVChange; + bit32 GPIEVRise; + bit32 GPIEVFall; + bit32 reserved1[5]; +} agsaGPIORsp_t; + +/** \brief the data structure of GPIO Event + * + * use to describe MPI GPIO Event Response (64 bytes) + */ +typedef struct agsaGPIOEvent_s { + bit32 GpioEvent; + bit32 reserved[14]; +} agsaGPIOEvent_t; + +/** \brief the data structure of GENERAL_EVENT Response + * + * use to describe MPI GENERNAL_EVENT Notification (64 bytes) + * + */ +typedef struct agsaGenernalEventRsp_s { + bit32 status; + bit32 inboundIOMB[14]; +} agsaGenernalEventRsp_t; + +/** \brief the data structure of SSP_ABORT Response + * + * use to describe MPI SSP_ABORT (64 bytes) + * + */ +typedef struct agsaSSPAbortRsp_s { + bit32 tag; + bit32 status; + bit32 scp; + bit32 reserved[12]; +} agsaSSPAbortRsp_t; + +/** \brief the data structure of SATA_ABORT Response + * + * use to describe MPI SATA_ABORT (64 bytes) + * + */ +typedef struct agsaSATAAbortRsp_s { + bit32 tag; + bit32 status; + bit32 scp; + bit32 reserved[12]; +} agsaSATAAbortRsp_t; + +/** \brief the data structure of SAS Diagnostic Start/End Response + * + * use to describe MPI SAS Diagnostic Start/End Response (64 bytes) + * + */ +typedef struct agsaSASDiagStartEndRsp_s { + bit32 tag; + bit32 Status; + bit32 reserved[13]; +} agsaSASDiagStartEndRsp_t; + +/** \brief the data structure of SAS Diagnostic Execute Response + * + * use to describe MPI SAS Diagnostic Execute Response (64 bytes) + * + */ +typedef struct agsaSASDiagExecuteRsp_s { + bit32 tag; + bit32 CmdTypeDescPhyId; + bit32 Status; + bit32 ReportData; + bit32 reserved[11]; +} agsaSASDiagExecuteRsp_t; + +/** \brief the data structure of General Event Notification Response + * + * use to describe MPI General Event Notification Response (64 bytes) + * + */ +typedef struct agsaGeneralEventRsp_s { + bit32 status; + bit32 inbIOMBpayload[14]; +} agsaGeneralEventRsp_t; + +#define GENERAL_EVENT_PAYLOAD 14 +#define OPCODE_BITS 0x00000fff + +/* +Table 171 GENERAL_EVENT Notification Status Field Codes +Value Name Description +*/ +#define GEN_EVENT_IOMB_V_BIT_NOT_SET 0x01 /* INBOUND_ Inbound IOMB is received with the V bit in the IOMB header not set. */ +#define GEN_EVENT_INBOUND_IOMB_OPC_NOT_SUPPORTED 0x02 /* Inbound IOMB is received with an unsupported OPC. */ +#define GEN_EVENT_IOMB_INVALID_OBID 0x03 /* INBOUND Inbound IOMB is received with an invalid OBID. */ +#define GEN_EVENT_DS_IN_NON_OPERATIONAL 0x39 /* DEVICE_HANDLE_ACCEPT command failed due to the device being in DS_NON_OPERATIONAL state. */ +#define GEN_EVENT_DS_IN_RECOVERY 0x3A /* DEVICE_HANDLE_ACCEPT command failed due to device being in DS_IN_RECOVERY state. */ +#define GEN_EVENT_DS_INVALID 0x49 /* DEVICE_HANDLE_ACCEPT command failed due to device being in DS_INVALID state. */ + +#define GEN_EVENT_IO_XFER_READ_COMPL_ERR 0x50 /* Indicates the PCIe Read Request to fetch one or more inbound IOMBs received + a failed completion response. The first and second Dwords of the + INBOUND IOMB field ( Dwords 2 and 3) contains information to identifying + the location in the inbound queue where the error occurred. + Dword 2 bits[15:0] contains the inbound queue number. + Dword 2 bits[31:16] specifies how many consecutive IOMBs were affected + by the failed DMA. + Dword 3 specifies the Consumer Index [CI] of the inbound queue where + the DMA operation failed.*/ + +/** \brief the data structure of SSP Request Received Notification + * + * use to describe MPI SSP Request Received Notification ( 1024 bytes) + * + */ +typedef struct agsaSSPReqReceivedNotify_s { + bit32 deviceId; + bit32 iniTagSSPIul; + bit32 frameTypeHssa; + bit32 TlrHdsa; + bit32 SSPIu[251]; +} agsaSSPReqReceivedNotify_t; + +#define SSPIUL_BITS 0x0000FFFF +#define INITTAG_BITS 0x0000FFFF +#define FRAME_TYPE 0x000000FF +#define TLR_BITS 0x00000300 + +/** \brief the data structure of Device Handle Arrived Notification + * + * use to describe MPI Device Handle Arrived Notification ( 64 bytes) + * + */ +typedef struct agsaDeviceHandleArrivedNotify_s { + bit32 CTag; + bit32 HostAssignedIdFwdDeviceId; + bit32 ProtConrPortId; + bit8 sasAddrHi[4]; + bit8 sasAddrLow[4]; + bit32 reserved[10]; + +} agsaDeviceHandleArrivedNotify_t; + + +#define Conrate_V_MASK 0x0000F000 +#define Conrate_V_SHIFT 12 +#define Conrate_SPC_MASK 0x0000F000 +#define Conrate_SPC_SHIFT 4 + +#define Protocol_SPC_MASK 0x00000700 +#define Protocol_SPC_SHIFT 8 +#define Protocol_SPC_MASK 0x00000700 +#define Protocol_SPC_SHIFT 8 + +#define PortId_V_MASK 0xFF +#define PortId_SPC_MASK 0x0F + +#define PROTOCOL_BITS 0x00000700 +#define PROTOCOL_SHIFT 8 + +#define SHIFT_REG_64K_MASK 0xffff0000 +#define SHIFT_REG_BIT_SHIFT 8 +#define SPC_GSM_SM_OFFSET 0x400000 +#define SPCV_GSM_SM_OFFSET 0x0 + +/** \brief the data structure of Get Time Stamp Response + * + * use to describe MPI Get TIme Stamp Response ( 64 bytes) + * + */ +typedef struct agsaGetTimeStampRsp_s { + bit32 tag; + bit32 timeStampLower; + bit32 timeStampUpper; + bit32 reserved[12]; +} agsaGetTimeStampRsp_t; + +/** \brief the data structure of SAS HW Event Ack Response + * + * use to describe SAS HW Event Ack Response ( 64 bytes) + * + */ +typedef struct agsaSASHwEventAckRsp_s { + bit32 tag; + bit32 status; + bit32 reserved[13]; +} agsaSASHwEventAckRsp_t; + +/** \brief the data structure of Port Control Response + * + * use to describe Port Control Response ( 64 bytes) + * + */ +typedef struct agsaPortControlRsp_s { + bit32 tag; + bit32 portOPPortId; + bit32 status; + bit32 rsvdPortState; + bit32 reserved[11]; +} agsaPortControlRsp_t; + +/** \brief the data structure of SMP Abort Response + * + * use to describe SMP Abort Response ( 64 bytes) + * + */ +typedef struct agsaSMPAbortRsp_s { + bit32 tag; + bit32 status; + bit32 scp; + bit32 reserved[12]; +} agsaSMPAbortRsp_t; + +/** \brief the data structure of Get NVMD Data Response + * + * use to describe MPI Get NVMD Data Response (64 bytes) + * + */ +typedef struct agsaGetNVMDataRsp_s { + bit32 tag; + bit32 iRTdaBnDpsAsNvm; + bit32 DlenStatus; + bit32 NVMData[12]; +} agsaGetNVMDataRsp_t; + +/** \brief the data structure of Set NVMD Data Response + * + * use to describe MPI Set NVMD Data Response (64 bytes) + * + */ +typedef struct agsaSetNVMDataRsp_s { + bit32 tag; + bit32 iPTdaBnDpsAsNvm; + bit32 status; + bit32 reserved[12]; +} agsaSetNVMDataRsp_t; + +/** \brief the data structure of Device Handle Removal + * + * use to describe MPI Device Handle Removel Notification (64 bytes) + * + */ +typedef struct agsaDeviceHandleRemoval_s { + bit32 portId; + bit32 deviceId; + bit32 reserved[13]; +} agsaDeviceHandleRemoval_t; + +/** \brief the data structure of Set Device State Response + * + * use to describe MPI Set Device State Response (64 bytes) + * + */ +typedef struct agsaSetDeviceStateRsp_s { + bit32 tag; + bit32 status; + bit32 deviceId; + bit32 pds_nds; + bit32 reserved[11]; +} agsaSetDeviceStateRsp_t; + +#define NDS_BITS 0x0F +#define PDS_BITS 0xF0 + +/** \brief the data structure of Get Device State Response + * + * use to describe MPI Get Device State Response (64 bytes) + * + */ +typedef struct agsaGetDeviceStateRsp_s { + bit32 tag; + bit32 status; + bit32 deviceId; + bit32 ds; + bit32 reserved[11]; +} agsaGetDeviceStateRsp_t; + +/** \brief the data structure of Set Device Info Response + * + * use to describe MPI Set Device Info Response (64 bytes) + * + */ +typedef struct agsaSetDeviceInfoRsp_s { + bit32 tag; + bit32 status; + bit32 deviceId; + bit32 SA_SR_SI; + bit32 A_R_ITNT; + bit32 reserved[10]; +} agsaSetDeviceInfoRsp_t; + +/** \brief the data structure of SAS Re_Initialize Response + * + * use to describe MPI SAS RE_INITIALIZE Response (64 bytes) + * + */ +typedef struct agsaSasReInitializeRsp_s { + bit32 tag; + bit32 status; + bit32 setFlags; + bit32 MaxPorts; + bit32 openRejReCmdData; + bit32 sataHOLTMO; + bit32 reserved[9]; +} agsaSasReInitializeRsp_t; + +/** \brief the data structure of SGPIO Response + * + * use to describe MPI serial GPIO Response IOMB (64 bytes) + * + */ +typedef struct agsaSGpioRsp_s { + bit32 tag; + bit32 resultFunctionFrameType; + bit32 readData[OSSA_SGPIO_MAX_READ_DATA_COUNT]; +} agsaSGpioRsp_t; + + +/** \brief the data structure of PCIe diag response + * + * use to describe PCIe diag response IOMB (64 bytes) + * + */ + +typedef struct agsaPCIeDiagExecuteRsp_s { + bit32 tag; /* 1 */ + bit32 CmdTypeDesc; /* 2 */ + bit32 Status; /* 3 */ + bit32 reservedDW4; /* 4 */ + bit32 reservedDW5; /* 5 */ + bit32 ERR_BLKH; /* 6 */ + bit32 ERR_BLKL; /* 7 */ + bit32 DWord8; /* 8 */ + bit32 DWord9; /* 9 */ + bit32 DWord10; /* 10 */ + bit32 DWord11; /* 11 */ + bit32 DIF_ERR; /* 12 */ + bit32 reservedDW13; /* 13 */ + bit32 reservedDW14; /* 14 */ + bit32 reservedDW15; /* 15 */ +} agsaPCIeDiagExecuteRsp_t; + +/** \brief the data structure of PCI diag response + * + * use to describe PCI diag response IOMB for SPC (64 bytes) + * + */ + +typedef struct agsa_SPC_PCIeDiagExecuteRsp_s { + bit32 tag; /* 1 */ + bit32 CmdTypeDesc; /* 2 */ + bit32 Status; /* 3 */ + bit32 reserved[12]; /* 4 15 */ +} agsa_SPC_PCIeDiagExecuteRsp_t; + +/** \brief the data structure of GET DFE Data Response + * + * use to describe GET DFE Data Response for SPCv (64 bytes) + * + */ +typedef struct agsaGetDDEFDataRsp_s { + bit32 tag; /* 1 */ + bit32 status; /* 2 */ + bit32 reserved_In_Ln;/* 3 */ + bit32 MCNT; /* 4 */ + bit32 NBT; /* 5 */ + bit32 reserved[10]; /* 6 - 15 */ +} agsaGetDDEFDataRsp_t; + +/** \brief the data structure of GET Vis Data Response + * + * use to describe GET Vis Data Response for SPCv (64 bytes) + * + */ +typedef struct agsaGetVHistCapRsp_s { + bit32 tag; /* 1 */ + bit32 status; /* 2 */ + bit32 channel; /* 3 */ + bit32 BistLo; /* 4 */ + bit32 BistHi; /* 5 */ + bit32 BytesXfered; /* 6 */ + bit32 PciLo; /* 7 */ + bit32 PciHi; /* 8 */ + bit32 PciBytecount; /* 9 */ + bit32 reserved[5]; /* 10 - 15 */ +} agsaGetVHistCapRsp_t; + +typedef struct agsaSetControllerConfigCmd_s { + bit32 tag; + bit32 pageCode; + bit32 configPage[13]; /* Page code specific fields */ +} agsaSetControllerConfigCmd_t; + + +typedef struct agsaSetControllerConfigRsp_s { + bit32 tag; + bit32 status; + bit32 errorQualifierPage; + bit32 reserved[12]; +} agsaSetControllerConfigRsp_t; + +typedef struct agsaGetControllerConfigCmd_s { + bit32 tag; + bit32 pageCode; + bit32 INT_VEC_MSK0; + bit32 INT_VEC_MSK1; + bit32 reserved[11]; +} agsaGetControllerConfigCmd_t; + +typedef struct agsaGetControllerConfigRsp_s { + bit32 tag; + bit32 status; + bit32 errorQualifier; + bit32 configPage[12]; /* Page code specific fields */ +} agsaGetControllerConfigRsp_t; + +typedef struct agsaDekManagementCmd_s { + bit32 tag; + bit32 KEKIDX_Reserved_TBLS_DSOP; + bit32 dekIndex; + bit32 tableAddrLo; + bit32 tableAddrHi; + bit32 tableEntries; + bit32 Reserved_DBF_TBL_SIZE; +} agsaDekManagementCmd_t; + +typedef struct agsaDekManagementRsp_s { + bit32 tag; + bit32 status; + bit32 flags; + bit32 dekIndex; + bit32 errorQualifier; + bit32 reserved[12]; +} agsaDekManagementRsp_t; + +typedef struct agsaKekManagementCmd_s { + bit32 tag; + bit32 NEWKIDX_CURKIDX_KBF_Reserved_SKNV_KSOP; + bit32 reserved; + bit32 kekBlob[12]; +} agsaKekManagementCmd_t; + +typedef struct agsaKekManagementRsp_s { + bit32 tag; + bit32 status; + bit32 flags; + bit32 errorQualifier; + bit32 reserved[12]; +} agsaKekManagementRsp_t; + + +typedef struct agsaCoalSspComplCxt_s { + bit32 tag; + bit16 SSPTag; + bit16 reserved; +} agsaCoalSspComplCxt_t; + +/** \brief the data structure of SSP Completion Response + * + * use to describe MPI SSP Completion Response (1024 bytes) + * + */ +typedef struct agsaSSPCoalescedCompletionRsp_s { + bit32 coalescedCount; + agsaCoalSspComplCxt_t sspComplCxt[1]; /* Open ended array */ +} agsaSSPCoalescedCompletionRsp_t; + + +/** \brief the data structure of SATA Completion Response + * + * use to describe MPI SATA Completion Response (1024 bytes) + * + */ +typedef struct agsaCoalStpComplCxt_s { + bit32 tag; + bit16 reserved; +} agsaCoalStpComplCxt_t; + +typedef struct agsaSATACoalescedCompletionRsp_s { + bit32 coalescedCount; + agsaCoalStpComplCxt_t stpComplCxt[1]; /* Open ended array */ +} agsaSATACoalescedCompletionRsp_t; + + +/** \brief the data structure of Operator Mangement Command + * + * use to describe OPR_MGMT Command (128 bytes) + * + */ +typedef struct agsaOperatorMangmentCmd_s{ + bit32 tag; /* 1 */ + bit32 OPRIDX_AUTIDX_R_KBF_PKT_OMO;/* 2 */ + bit8 IDString_Role[32]; /* 3 10 */ +#ifndef HAILEAH_HOST_6G_COMPITIBILITY_FLAG + agsaEncryptKekBlob_t Kblob; /* 11 22 */ +#endif + bit32 reserved[8]; /* 23 31 */ +} agsaOperatorMangmentCmd_t; + + +/* + * + * use to describe OPR_MGMT Response (64 bytes) + * + */ +typedef struct agsaOperatorMangmentRsp_s { + bit32 tag; /* 1 */ + bit32 status; /* 2 */ + bit32 OPRIDX_AUTIDX_R_OMO; /* 3 */ + bit32 errorQualifier; /* 4 */ + bit32 reserved[10]; /* 5 15 */ +} agsaOperatorMangmenRsp_t; + +/** \brief the data structure of Set Operator Command + * + * use to describe Set Operator Command (64 bytes) + * + */ +typedef struct agsaSetOperatorCmd_s{ + bit32 tag; /* 1 */ + bit32 OPRIDX_PIN_ACS; /* 2 */ + bit32 cert[10]; /* 3 12 */ + bit32 reserved[3]; /* 13 15 */ +} agsaSetOperatorCmd_t; + +/* + * + * use to describe Set Operator Response (64 bytes) + * + */ +typedef struct agsaSetOperatorRsp_s { + bit32 tag; /* 1 */ + bit32 status; /* 2 */ + bit32 ERR_QLFR_OPRIDX_PIN_ACS;/* 3 */ + bit32 reserved[12]; /* 4 15 */ +} agsaSetOperatorRsp_t; + +/** \brief the data structure of Get Operator Command + * + * use to describe Get Operator Command (64 bytes) + * + */ +typedef struct agsaGetOperatorCmd_s{ + bit32 tag; /* 1 */ + bit32 option; /* 2 */ + bit32 OprBufAddrLo; /* 3 */ + bit32 OprBufAddrHi; /* 4*/ + bit32 reserved[11]; /*5 15*/ +} agsaGetOperatorCmd_t; + +/* + * + * use to describe Get Operator Response (64 bytes) + * + */ +typedef struct agsaGetOperatorRsp_s { + bit32 tag; /* 1 */ + bit32 status; /* 2 */ + bit32 Num_Option; /* 3 */ + bit32 IDString[8]; /* 4 11*/ + bit32 reserved[4]; /* 12 15*/ +} agsaGetOperatorRsp_t; + +/* + * + * use to start Encryption BIST (128 bytes) + * 0x105 + */ +typedef struct agsaEncryptBist_s { + bit32 tag; /* 1 */ + bit32 r_subop; /* 2 */ + bit32 testDiscption[28]; /* 3 31 */ +} agsaEncryptBist_t; + +/* + * + * use to describe Encryption BIST Response (64 bytes) + * 0x905 + */ + +typedef struct agsaEncryptBistRsp_s { + bit32 tag; /* 1 */ + bit32 status; /* 2 */ + bit32 subop; /* 3 */ + bit32 testResults[11]; /* 4 15 */ +} agsaEncryptBistRsp_t; + +/** \brief the data structure of DifEncOffload Command + * + * use to describe Set DifEncOffload Command (128 bytes) + * + */ +typedef struct agsaDifEncOffloadCmd_s{ + bit32 tag; /* 1 */ + bit32 option; /* 2 */ + bit32 reserved[2]; /* 3-4 */ + bit32 Src_Data_Len; /* 5 */ + bit32 Dst_Data_Len; /* 6 */ + bit32 flags; /* 7 */ + bit32 UDTR01UDT01; /* 8 */ + bit32 UDT2345; /* 9 */ + bit32 UDTR2345; /* 10 */ + bit32 DPLR0SecCnt_IOSeed; /* 11 */ + bit32 DPL_Addr_Lo; /* 12 */ + bit32 DPL_Addr_Hi; /* 13 */ + bit32 KeyIndex_CMode_KTS_ENT_R; /* 14 */ + bit32 EPLR0SecCnt_KS_ENSS; /* 15 */ + bit32 keyTag_W0; /* 16 */ + bit32 keyTag_W1; /* 17 */ + bit32 tweakVal_W0; /* 18 */ + bit32 tweakVal_W1; /* 19 */ + bit32 tweakVal_W2; /* 20 */ + bit32 tweakVal_W3; /* 21 */ + bit32 EPL_Addr_Lo; /* 22 */ + bit32 EPL_Addr_Hi; /* 23 */ + agsaSgl_t SrcSgl; /* 24-27 */ + agsaSgl_t DstSgl; /* 28-31 */ +} agsaDifEncOffloadCmd_t; + +/* + * + * use to describe DIF/Encryption Offload Response (32 bytes) + * 0x910 + */ +typedef struct agsaDifEncOffloadRspV_s { + bit32 tag; + bit32 status; + bit32 ExpectedCRCUDT01; + bit32 ExpectedUDT2345; + bit32 ActualCRCUDT01; + bit32 ActualUDT2345; + bit32 DIFErr; + bit32 ErrBoffset; +} agsaDifEncOffloadRspV_t; + +#endif /*__SAMPIDEFS_H__ */ diff --git a/sys/dev/pms/RefTisa/sallsdk/spc/sampirsp.c b/sys/dev/pms/RefTisa/sallsdk/spc/sampirsp.c new file mode 100644 index 000000000000..c9af17bbf01e --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/spc/sampirsp.c @@ -0,0 +1,7876 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +/*******************************************************************************/ +/*! \file sampirsp.c + * \brief The file implements the functions of MPI Outbound Response Message + * + */ +/******************************************************************************/ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#ifdef SA_ENABLE_TRACE_FUNCTIONS +#ifdef siTraceFileID +#undef siTraceFileID +#endif +#define siTraceFileID 'J' +#endif + +/******************************************************************************/ +/* Protoytpes */ +void saReturnRequestToFreePool( + agsaRoot_t *agRoot, + agsaIORequestDesc_t *pRequest + ); + +/******************************************************************************/ +/*! \brief Process Outbound IOMB Message + * + * Process Outbound IOMB from SPC + * + * \param agRoot Handles for this instance of SAS/SATA LL Layer + * \param pMsg1 Pointer of Response IOMB message 1 + * \param category category of outbpond IOMB header + * \param opcode Opcode of Outbound IOMB header + * \param bc buffer count of IOMB header + * + * \return success or fail + * + */ +/*******************************************************************************/ +#if 0 +FORCEINLINE bit32 +mpiParseOBIomb( + agsaRoot_t *agRoot, + bit32 *pMsg1, + mpiMsgCategory_t category, + bit16 opcode + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + bit32 ret = AGSA_RC_SUCCESS; + bit32 parserStatus = AGSA_RC_SUCCESS; + + smTraceFuncEnter(hpDBG_VERY_LOUD, "2f"); + + switch (opcode) + { + case OPC_OUB_COMBINED_SSP_COMP: + { + agsaSSPCoalescedCompletionRsp_t *pIomb = (agsaSSPCoalescedCompletionRsp_t *)pMsg1; + agsaIORequestDesc_t *pRequest = agNULL; + bit32 tag = 0; + bit32 sspTag = 0; + bit32 count = 0; + +#ifdef SALL_API_TEST + saRoot->LLCounters.IOCounter.numSSPCompleted++; + SA_DBG3(("mpiParseOBIomb, SSP_COMP Response received IOMB=%p %d\n", + pMsg1, saRoot->LLCounters.IOCounter.numSSPCompleted)); +#else + SA_DBG3(("mpiParseOBIomb, OPC_OUB_COMBINED_SSP_COMP Response received IOMB=%p\n", pMsg1)); +#endif + /* get Tag */ + for (count = 0; count < pIomb->coalescedCount; count++) + { + tag = pIomb->sspComplCxt[count].tag; + sspTag = pIomb->sspComplCxt[count].SSPTag; + pRequest = (agsaIORequestDesc_t *)saRoot->IOMap[tag].IORequest; + SA_ASSERT((pRequest), "pRequest"); + + if(pRequest == agNULL) + { + SA_DBG1(("mpiParseOBIomb,OPC_OUB_COMBINED_SSP_COMP Resp IOMB tag=0x%x, status=0x%x, param=0x%x, SSPTag=0x%x\n", tag, OSSA_IO_SUCCESS, 0, sspTag)); + return(AGSA_RC_FAILURE); + } + SA_ASSERT((pRequest->valid), "pRequest->valid"); + + SA_DBG3(("mpiParseOBIomb, OPC_OUB_COMBINED_SSP_COMP IOMB tag=0x%x, status=0x%x, param=0x%x, SSPTag=0x%x\n", tag, OSSA_IO_SUCCESS, 0, sspTag)); + + /* Completion of SSP without Response Data */ + siIODone( agRoot, pRequest, OSSA_IO_SUCCESS, sspTag); + } + } + break; + + case OPC_OUB_SSP_COMP: + { +#ifdef SALL_API_TEST + saRoot->LLCounters.IOCounter.numSSPCompleted++; + SA_DBG3(("mpiParseOBIomb, SSP_COMP Response received IOMB=%p %d\n", + pMsg1, saRoot->LLCounters.IOCounter.numSSPCompleted)); +#else + SA_DBG3(("mpiParseOBIomb, SSP_COMP Response received IOMB=%p\n", pMsg1)); +#endif + /* process the SSP IO Completed response message */ + mpiSSPCompletion(agRoot, pMsg1); + break; + } + case OPC_OUB_COMBINED_SATA_COMP: + { + agsaSATACoalescedCompletionRsp_t *pIomb; + agsaIORequestDesc_t *pRequest; + bit32 tag; + bit32 count; + + #ifdef SALL_API_TEST + saRoot->LLCounters.IOCounter.numSSPCompleted++; + SA_DBG3(("mpiParseOBIomb, OPC_OUB_COMBINED_SATA_COMP Response received IOMB=%p %d\n", + pMsg1, saRoot->LLCounters.IOCounter.numSSPCompleted)); + #else + SA_DBG3(("mpiParseOBIomb, OPC_OUB_COMBINED_SATA_COMP Response received IOMB=%p\n", pMsg1)); + #endif + + pIomb = (agsaSATACoalescedCompletionRsp_t *)pMsg1; + /* get Tag */ + for (count = 0; count < pIomb->coalescedCount; count++) + { + tag = pIomb->stpComplCxt[count].tag; + pRequest = (agsaIORequestDesc_t *)saRoot->IOMap[tag].IORequest; + SA_ASSERT((pRequest), "pRequest"); + + if(pRequest == agNULL) + { + SA_DBG1(("mpiParseOBIomb,OPC_OUB_COMBINED_SATA_COMP Resp IOMB tag=0x%x, status=0x%x, param=0x%x\n", tag, OSSA_IO_SUCCESS, 0)); + return(AGSA_RC_FAILURE); + } + SA_ASSERT((pRequest->valid), "pRequest->valid"); + + SA_DBG3(("mpiParseOBIomb, OPC_OUB_COMBINED_SATA_COMP IOMB tag=0x%x, status=0x%x, param=0x%x\n", tag, OSSA_IO_SUCCESS, 0)); + + /* Completion of SATA without Response Data */ + siIODone( agRoot, pRequest, OSSA_IO_SUCCESS, 0); + } + break; + } + case OPC_OUB_SATA_COMP: + { +#ifdef SALL_API_TEST + saRoot->LLCounters.IOCounter.numSataCompleted++; + SA_DBG3(("mpiParseOBIomb, SATA_COMP Response received IOMB=%p %d\n", + pMsg1, saRoot->LLCounters.IOCounter.numSataCompleted)); +#else + SA_DBG3(("mpiParseOBIomb, SATA_COMP Response received IOMB=%p\n", pMsg1)); +#endif + /* process the response message */ + mpiSATACompletion(agRoot, pMsg1); + break; + } + case OPC_OUB_SSP_ABORT_RSP: + { +#ifdef SALL_API_TEST + saRoot->LLCounters.IOCounter.numSSPAbortedCB++; +#else + SA_DBG3(("mpiParseOBIomb, SSP_ABORT Response received IOMB=%p\n", pMsg1)); +#endif + /* process the response message */ + parserStatus = mpiSSPAbortRsp(agRoot, (agsaSSPAbortRsp_t *)pMsg1); + if(parserStatus != AGSA_RC_SUCCESS) + { + SA_DBG3(("mpiParseOBIomb, mpiSSPAbortRsp FAIL IOMB=%p\n", pMsg1)); + } + + break; + } + case OPC_OUB_SATA_ABORT_RSP: + { +#ifdef SALL_API_TEST + saRoot->LLCounters.IOCounter.numSataAbortedCB++; +#else + SA_DBG3(("mpiParseOBIomb, SATA_ABORT Response received IOMB=%p\n", pMsg1)); +#endif + /* process the response message */ + mpiSATAAbortRsp(agRoot, (agsaSATAAbortRsp_t *)pMsg1); + break; + } + case OPC_OUB_SATA_EVENT: + { + SA_DBG3(("mpiParseOBIomb, SATA_EVENT Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiSATAEvent(agRoot, (agsaSATAEventRsp_t *)pMsg1); + break; + } + case OPC_OUB_SSP_EVENT: + { + SA_DBG3(("mpiParseOBIomb, SSP_EVENT Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiSSPEvent(agRoot, (agsaSSPEventRsp_t *)pMsg1); + break; + } + case OPC_OUB_SMP_COMP: + { +#ifdef SALL_API_TEST + saRoot->LLCounters.IOCounter.numSMPCompleted++; + SA_DBG3(("mpiParseOBIomb, SMP_COMP Response received IOMB=%p, %d\n", + pMsg1, saRoot->LLCounters.IOCounter.numSMPCompleted)); +#else + SA_DBG3(("mpiParseOBIomb, SMP_COMP Response received IOMB=%p\n", pMsg1)); +#endif + /* process the response message */ + mpiSMPCompletion(agRoot, (agsaSMPCompletionRsp_t *)pMsg1); + break; + } +#ifndef BIOS + case OPC_OUB_ECHO: + { +#ifdef SALL_API_TEST + saRoot->LLCounters.IOCounter.numEchoCB++; + SA_DBG3(("mpiParseOBIomb, ECHO Response received %d\n", saRoot->LLCounters.IOCounter.numEchoCB)); +#else + SA_DBG3(("mpiParseOBIomb, ECHO Response received\n")); +#endif + /* process the response message */ + mpiEchoRsp(agRoot, (agsaEchoRsp_t *)pMsg1); + break; + } +#endif + case OPC_OUB_GET_NVMD_DATA: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_GET_NVMD_DATA received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiGetNVMDataRsp(agRoot, (agsaGetNVMDataRsp_t *)pMsg1); + break; + } + case OPC_OUB_SPC_HW_EVENT: + { + SA_ASSERT((smIS_SPC(agRoot)), "smIS_SPC"); + SA_DBG3(("mpiParseOBIomb, OPC_OUB_SPC_HW_EVENT Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiHWevent(agRoot, (agsaHWEvent_SPC_OUB_t *)pMsg1); + break; + } + case OPC_OUB_HW_EVENT: + { + SA_DBG3(("mpiParseOBIomb, HW_EVENT Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiHWevent(agRoot, (agsaHWEvent_SPC_OUB_t *)pMsg1); + break; + } + case OPC_OUB_PHY_START_RESPONSE: + { + SA_DBG1(("mpiParseOBIomb, OPC_OUB_PHY_START_RESPONSE Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiPhyStartEvent( agRoot, (agsaHWEvent_Phy_OUB_t *)pMsg1 ); + + break; + } + case OPC_OUB_PHY_STOP_RESPONSE: + { + SA_DBG1(("mpiParseOBIomb, OPC_OUB_PHY_STOP_RESPONSE Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiPhyStopEvent( agRoot, (agsaHWEvent_Phy_OUB_t *)pMsg1 ); + break; + } + + case OPC_OUB_LOCAL_PHY_CNTRL: + { + SA_DBG3(("mpiParseOBIomb, PHY CONTROL Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiPhyCntrlRsp(agRoot, (agsaLocalPhyCntrlRsp_t *)pMsg1); + break; + } + case OPC_OUB_SPC_DEV_REGIST: + { + SA_ASSERT((smIS_SPC(agRoot)), "smIS_SPC"); + SA_DBG3(("mpiParseOBIomb, OPC_OUB_SPC_DEV_REGIST Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiDeviceRegRsp(agRoot, (agsaDeviceRegistrationRsp_t *)pMsg1); + break; + } + case OPC_OUB_DEV_REGIST: + { + SA_DBG2(("mpiParseOBIomb, DEV_REGISTRATION Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiDeviceRegRsp(agRoot, (agsaDeviceRegistrationRsp_t *)pMsg1); + break; + } + case OPC_OUB_DEREG_DEV: + { + SA_DBG3(("mpiParseOBIomb, DEREGISTRATION DEVICE Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiDeregDevHandleRsp(agRoot, (agsaDeregDevHandleRsp_t *)pMsg1); + break; + } +#ifndef BIOS + case OPC_OUB_GET_DEV_HANDLE: + { + SA_DBG3(("mpiParseOBIomb, GET_DEV_HANDLE Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiGetDevHandleRsp(agRoot, (agsaGetDevHandleRsp_t *)pMsg1); + break; + } +#endif + case OPC_OUB_SPC_DEV_HANDLE_ARRIV: + { + SA_DBG3(("mpiParseOBIomb, SPC_DEV_HANDLE_ARRIV Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiDeviceHandleArrived(agRoot, (agsaDeviceHandleArrivedNotify_t *)pMsg1); + break; + } + case OPC_OUB_DEV_HANDLE_ARRIV: + { + SA_DBG3(("mpiParseOBIomb, DEV_HANDLE_ARRIV Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiDeviceHandleArrived(agRoot, (agsaDeviceHandleArrivedNotify_t *)pMsg1); + break; + } +#if 0 //Sunitha + case OPC_OUB_THERM_HW_EVENT: + { + SA_DBG3(("mpiParseOBIomb, THERM_HW_EVENT Response received IOMB=%p\n", pMsg1)); + ossaLogThermalEvent(agRoot, (agsaThermal_Hw_Event_Notify_t *)pMsg1); + break; + } +#endif //Sunitha + case OPC_OUB_SSP_RECV_EVENT: + { + SA_DBG3(("mpiParseOBIomb, SSP_RECV_EVENT Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiSSPReqReceivedNotify(agRoot, (agsaSSPReqReceivedNotify_t *)pMsg1); + break; + } + case OPC_OUB_DEV_INFO: + { + SA_ASSERT((smIS_SPCV(agRoot)), "smIS_SPCV"); + SA_DBG3(("mpiParseOBIomb, DEV_INFO Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiGetDevInfoRsp(agRoot, (agsaGetDevInfoRspV_t *)pMsg1); + break; + } +#ifndef BIOS + case OPC_OUB_GET_PHY_PROFILE_RSP: + { + SA_ASSERT((smIS_SPCV(agRoot)), "smIS_SPCV"); + SA_DBG2(("mpiParseOBIomb, OPC_OUB_GET_PHY_PROFILE_RSP Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiGetPhyProfileRsp(agRoot, (agsaGetPhyProfileRspV_t *)pMsg1); + break; + } + case OPC_OUB_SET_PHY_PROFILE_RSP: + { + SA_ASSERT((smIS_SPCV(agRoot)), "smIS_SPCV"); + SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_PHY_PROFILE_RSP Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiSetPhyProfileRsp(agRoot, (agsaSetPhyProfileRspV_t *)pMsg1); + break; + } +#endif /* BIOS */ + case OPC_OUB_SPC_DEV_INFO: + { + SA_ASSERT((smIS_SPC(agRoot)), "smIS_SPC"); + SA_DBG3(("mpiParseOBIomb, DEV_INFO Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiGetDevInfoRspSpc(agRoot, (agsaGetDevInfoRsp_t *)pMsg1); + break; + } + case OPC_OUB_FW_FLASH_UPDATE: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_FW_FLASH_UPDATE Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiFwFlashUpdateRsp(agRoot, (agsaFwFlashUpdateRsp_t *)pMsg1); + break; + } + case OPC_OUB_FLASH_OP_EXT_RSP: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_FW_FLASH_UPDATE Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiFwExtFlashUpdateRsp(agRoot, (agsaFwFlashOpExtRsp_t *)pMsg1); + break; + } +#ifndef BIOS +#ifdef SPC_ENABLE_PROFILE + case OPC_OUB_FW_PROFILE: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_FW_PROFILE Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiFwProfileRsp(agRoot, (agsaFwProfileRsp_t *)pMsg1); + break; + } +#endif + case OPC_OUB_SET_NVMD_DATA: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_NVMD_DATA received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiSetNVMDataRsp(agRoot, (agsaSetNVMDataRsp_t *)pMsg1); + break; + } + + case OPC_OUB_GPIO_RESPONSE: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_GPIO_RESPONSE Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiGPIORsp(agRoot, (agsaGPIORsp_t *)pMsg1); + break; + } + case OPC_OUB_GPIO_EVENT: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_GPIO_RESPONSE Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiGPIOEventRsp(agRoot, (agsaGPIOEvent_t *)pMsg1); + break; + } +#endif /* BIOS */ + case OPC_OUB_GENERAL_EVENT: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_GENERAL_EVENT Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiGeneralEventRsp(agRoot, (agsaGeneralEventRsp_t *)pMsg1); + break; + } +#ifndef BIOS + case OPC_OUB_SAS_DIAG_MODE_START_END: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_SAS_DIAG_MODE_START_END Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiSASDiagStartEndRsp(agRoot, (agsaSASDiagStartEndRsp_t *)pMsg1); + break; + } + case OPC_OUB_SAS_DIAG_EXECUTE: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_SAS_DIAG_EXECUTE_RSP Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiSASDiagExecuteRsp(agRoot, (agsaSASDiagExecuteRsp_t *)pMsg1); + break; + } +#endif /* BIOS */ + case OPC_OUB_GET_TIME_STAMP: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_GET_TIME_STAMP Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiGetTimeStampRsp(agRoot, (agsaGetTimeStampRsp_t *)pMsg1); + break; + } + + case OPC_OUB_SPC_SAS_HW_EVENT_ACK: + { + SA_ASSERT((smIS_SPC(agRoot)), "smIS_SPC"); + SA_DBG3(("mpiParseOBIomb,OPC_OUB_SPC_SAS_HW_EVENT_ACK Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiSASHwEventAckRsp(agRoot, (agsaSASHwEventAckRsp_t *)pMsg1); + break; + } + + case OPC_OUB_SAS_HW_EVENT_ACK: + { + SA_ASSERT((smIS_SPCV(agRoot)), "smIS_SPCV"); + SA_DBG3(("mpiParseOBIomb, OPC_OUB_SAS_HW_EVENT_ACK Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiSASHwEventAckRsp(agRoot, (agsaSASHwEventAckRsp_t *)pMsg1); + break; + } + case OPC_OUB_PORT_CONTROL: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_PORT_CONTROL Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiPortControlRsp(agRoot, (agsaPortControlRsp_t *)pMsg1); + break; + } + case OPC_OUB_SMP_ABORT_RSP: + { +#ifdef SALL_API_TEST + saRoot->LLCounters.IOCounter.numSMPAbortedCB++; + SA_DBG3(("mpiParseOBIomb, SMP_ABORT Response received IOMB=%p, %d\n", + pMsg1, saRoot->LLCounters.IOCounter.numSMPAbortedCB)); +#else + SA_DBG3(("mpiParseOBIomb, OPC_OUB_SMP_ABORT_RSP Response received IOMB=%p\n", pMsg1)); +#endif + /* process the response message */ + mpiSMPAbortRsp(agRoot, (agsaSMPAbortRsp_t *)pMsg1); + break; + } + case OPC_OUB_DEVICE_HANDLE_REMOVAL: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_DEVICE_HANDLE_REMOVAL received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiDeviceHandleRemoval(agRoot, (agsaDeviceHandleRemoval_t *)pMsg1); + break; + } + case OPC_OUB_SET_DEVICE_STATE: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_DEVICE_STATE received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiSetDeviceStateRsp(agRoot, (agsaSetDeviceStateRsp_t *)pMsg1); + break; + } + +#ifndef BIOS + case OPC_OUB_GET_DEVICE_STATE: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_GET_DEVICE_STATE received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiGetDeviceStateRsp(agRoot, (agsaGetDeviceStateRsp_t *)pMsg1); + break; + } +#endif /* BIOS */ + + case OPC_OUB_SET_DEV_INFO: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_DEV_INFO received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiSetDevInfoRsp(agRoot, (agsaSetDeviceInfoRsp_t *)pMsg1); + break; + } + +#ifndef BIOS_DEBUG + case OPC_OUB_SAS_RE_INITIALIZE: + { + SA_ASSERT((smIS_SPC(agRoot)), "smIS_SPC"); + SA_DBG3(("mpiParseOBIomb, OPC_OUB_SAS_RE_INITIALIZE received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiSasReInitializeRsp(agRoot, (agsaSasReInitializeRsp_t *)pMsg1); + break; + } +#endif /* BIOS */ + + case OPC_OUB_SGPIO_RESPONSE: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_SGPIO_RESPONSE Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiSGpioRsp(agRoot, (agsaSGpioRsp_t *)pMsg1); + break; + } + +#ifndef BIOS + case OPC_OUB_PCIE_DIAG_EXECUTE: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_PCIE_DIAG_EXECUTE Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiPCIeDiagExecuteRsp(agRoot, (agsaPCIeDiagExecuteRsp_t *)pMsg1); + break; + } + case 2104: //delray start + { + if(smIS_SPC6V(agRoot)) + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_GET_DFE_DATA_RSP Response received IOMB=%p\n", pMsg1)); + /* process the response message */ + mpiGetDFEDataRsp(agRoot, (agsaGetDDEFDataRsp_t *)pMsg1); + } + if(smIS_SPC12V(agRoot)) + { + SA_DBG3(("mpiParseOBIomb, OPC_INB_GET_VIST_CAP Response received IOMB=%p\n", pMsg1)); + mpiGetVisRsp(agRoot, (agsaGetVisCapRsp_t *)pMsg1); + } + else + { + SA_DBG1(("mpiParseOBIomb, 2104 Response received IOMB=%p\n", pMsg1)); + } + break; + } +#endif /* BIOS */ + case OPC_OUB_SET_CONTROLLER_CONFIG: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_CONTROLLER_CONFIG Response received IOMB=%p\n", pMsg1)); + mpiSetControllerConfigRsp(agRoot, (agsaSetControllerConfigRsp_t *)pMsg1); + break; + } +#ifndef BIOS + case OPC_OUB_GET_CONTROLLER_CONFIG: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_GET_CONTROLLER_CONFIG Response received IOMB=%p\n", pMsg1)); + mpiGetControllerConfigRsp(agRoot, (agsaGetControllerConfigRsp_t *)pMsg1); + break; + } + case OPC_OUB_KEK_MANAGEMENT: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_KEK_MANAGEMENT Response received IOMB=%p\n", pMsg1)); + mpiKekManagementRsp(agRoot, (agsaKekManagementRsp_t *)pMsg1); + break; + } +#endif /* BIOS */ +#ifdef UN_USED_FUNC + case OPC_OUB_DEK_MANAGEMENT: + { + SA_DBG3(("mpiParseOBIomb, OPC_OUB_DEK_MANAGEMENT Response received IOMB=%p\n", pMsg1)); + mpiDekManagementRsp(agRoot, (agsaDekManagementRsp_t *)pMsg1); + break; + } +#endif +#ifndef BIOS + case OPC_OUB_OPR_MGMT: + { + SA_DBG1(("mpiParseOBIomb, OPC_OUB_OPR_MGMT Response received IOMB=%p\n", pMsg1)); + mpiOperatorManagementRsp(agRoot, (agsaOperatorMangmenRsp_t *)pMsg1); + break; + } + case OPC_OUB_ENC_TEST_EXECUTE: + { + SA_DBG1(("mpiParseOBIomb, OPC_OUB_ENC_TEST_EXECUTE Response received IOMB=%p\n", pMsg1)); + mpiBistRsp(agRoot, (agsaEncryptBistRsp_t *)pMsg1); + break; + } +#endif /* BIOS */ + case OPC_OUB_SET_OPERATOR: + { + SA_DBG1(("mpiParseOBIomb, OPC_OUB_SET_OPERATOR Response received IOMB=%p\n", pMsg1)); + mpiSetOperatorRsp(agRoot, (agsaSetOperatorRsp_t *)pMsg1); + break; + } + case OPC_OUB_GET_OPERATOR: + { + SA_DBG1(("mpiParseOBIomb, OPC_OUB_GET_OPERATOR Response received IOMB=%p\n", pMsg1)); + mpiGetOperatorRsp(agRoot, (agsaGetOperatorRsp_t *)pMsg1); + break; + } + case OPC_OUB_DIF_ENC_OFFLOAD_RSP://delray start + { + SA_ASSERT((smIS_SPCV(agRoot)), "smIS_SPCV"); + SA_DBG1(("mpiParseOBIomb, OPC_OUB_DIF_ENC_OFFLOAD_RSP Response received IOMB=%p\n", pMsg1)); + mpiDifEncOffloadRsp(agRoot, (agsaDifEncOffloadRspV_t *)pMsg1); + break; + } //delray end + default: + { +#ifdef SALL_API_TEST + saRoot->LLCounters.IOCounter.numUNKNWRespIOMB++; + SA_DBG1(("mpiParseOBIomb, UnKnown Response received IOMB=%p, %d\n", + pMsg1, saRoot->LLCounters.IOCounter.numUNKNWRespIOMB)); +#else + SA_DBG1(("mpiParseOBIomb, Unknown IOMB Response received opcode 0x%X IOMB=%p\n",opcode, pMsg1)); +#endif + break; + } + } /* switch */ + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2f"); + + return ret; + +} +#endif + +#ifndef BIOS +#endif + +/******************************************************************************/ +/*! \brief ECHO Response + * + * This routine handles the response of ECHO Command + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb Pointer of IOMB Mesage + * + * \return sucess or fail + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiEchoRsp( + agsaRoot_t *agRoot, + agsaEchoRsp_t *pIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaContext_t *agContext; + bit32 tag; + + smTraceFuncEnter(hpDBG_VERY_LOUD, "2g"); + + SA_DBG3(("mpiEchoRsp: HTAG=0x%x\n", pIomb->tag)); + + /* get request from IOMap */ + OSSA_READ_LE_32(agRoot, &tag, pIomb, OSSA_OFFSET_OF(agsaEchoRsp_t, tag)); + + pRequest = (agsaIORequestDesc_t *)saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + SA_DBG1(("mpiEchoRsp: Bad Response IOMB!!! pRequest is NULL. TAG=0x%x\n", tag)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2g"); + return AGSA_RC_FAILURE; + } + + agContext = saRoot->IOMap[tag].agContext; + + ossaEchoCB(agRoot, agContext, (void *)&pIomb->payload[0]); + + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_ASSERT((pRequest->valid), "pRequest->valid"); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiEchoRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2g"); + return ret; +} + +/******************************************************************************/ +/*! \brief Get NVM Data Response + * + * This routine handles the response of GET NVM Data Response + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb Pointer of IOMB Mesage + * + * \return sucess or fail + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiGetNVMDataRsp( + agsaRoot_t *agRoot, + agsaGetNVMDataRsp_t *pIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaContext_t *agContext; + bit32 i, dataLen; + bit32 DlenStatus, tag, iRTdaBnDpsAsNvm; + + smTraceFuncEnter(hpDBG_VERY_LOUD, "2h"); + + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaGetNVMDataRsp_t, tag)); + OSSA_READ_LE_32(AGROOT, &DlenStatus, pIomb, OSSA_OFFSET_OF(agsaGetNVMDataRsp_t, DlenStatus)); + OSSA_READ_LE_32(AGROOT, &iRTdaBnDpsAsNvm, pIomb, OSSA_OFFSET_OF(agsaGetNVMDataRsp_t, iRTdaBnDpsAsNvm)); + OSSA_READ_LE_32(AGROOT, &dataLen, pIomb, OSSA_OFFSET_OF(agsaGetNVMDataRsp_t, NVMData[10])) ; + + SA_DBG1(("mpiGetNVMDataRsp: HTAG=0x%x\n", tag)); + + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t *)saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + SA_DBG1(("mpiGetNVMDataRsp: Bad Response IOMB!!! pRequest is NULL.\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2h"); + return AGSA_RC_FAILURE; + } + + agContext = saRoot->IOMap[tag].agContext; + + if (iRTdaBnDpsAsNvm & IRMode) + { + /* indirect mode - IR bit set */ + SA_DBG1(("mpiGetNVMDataRsp: OSSA_SUCCESS, IR=1, DataLen=%d\n", dataLen)); + if (((iRTdaBnDpsAsNvm & NVMD_TYPE) == AGSA_NVMD_CONFIG_SEEPROM) || + ((iRTdaBnDpsAsNvm & NVMD_TYPE) == AGSA_NVMD_VPD_FLASH) || + ((iRTdaBnDpsAsNvm & NVMD_TYPE) == AGSA_NVMD_TWI_DEVICES) || + ((iRTdaBnDpsAsNvm & NVMD_TYPE) == AGSA_NVMD_EXPANSION_ROM) || + ((iRTdaBnDpsAsNvm & NVMD_TYPE) == AGSA_NVMD_IOP_REG_FLASH)) + { + /* CB for NVMD */ +//#ifdef UN_USED_FUNC + ossaGetNVMDResponseCB(agRoot, agContext, (DlenStatus & NVMD_STAT), INDIRECT_MODE, dataLen, agNULL); +//#endif + } + else if (((iRTdaBnDpsAsNvm & NVMD_TYPE) == AAP1_RDUMP) || + ((iRTdaBnDpsAsNvm & NVMD_TYPE) == IOP_RDUMP)) + { +#ifdef UN_USED_FUNC + if ((DlenStatus & NVMD_STAT) == 0) + { + /* CB for Register Dump */ + + ossaGetRegisterDumpCB(agRoot, agContext, OSSA_SUCCESS); + } + else + { + /* CB for Register Dump */ + ossaGetRegisterDumpCB(agRoot, agContext, OSSA_FAILURE); + } +#endif + } + else + { + /* Should not be happened */ + SA_DBG1(("mpiGetNVMDataRsp: (IR=1)Wrong Device type 0x%x\n", iRTdaBnDpsAsNvm)); + } + } + else /* direct mode */ + { + SA_DBG1(("mpiGetNVMDataRsp: OSSA_SUCCESS, IR=0, DataLen=%d\n", ((DlenStatus & NVMD_LEN) >> SHIFT24))); + for (i = 0; i < (((DlenStatus & NVMD_LEN) >> SHIFT24)/4); i++) + { + SA_DBG1(("mpiGetNVMDataRsp: OSSA_SUCCESS, NVMDATA=0x%x\n", pIomb->NVMData[i])); + } + if (((iRTdaBnDpsAsNvm & NVMD_TYPE) == AGSA_NVMD_CONFIG_SEEPROM) || + ((iRTdaBnDpsAsNvm & NVMD_TYPE) == AGSA_NVMD_VPD_FLASH) || + ((iRTdaBnDpsAsNvm & NVMD_TYPE) == AGSA_NVMD_TWI_DEVICES)) + { + /* CB for NVMD */ + // char * safe_type_pun = (char *)(&pIomb->NVMData[0]); +#ifdef UN_USED_FUNC + ossaGetNVMDResponseCB(agRoot, agContext, (DlenStatus & NVMD_STAT), DIRECT_MODE, + ((DlenStatus & NVMD_LEN) >> SHIFT24), (agsaFrameHandle_t *)safe_type_pun); +#endif + } + else if (((iRTdaBnDpsAsNvm & NVMD_TYPE) == AAP1_RDUMP) || + ((iRTdaBnDpsAsNvm & NVMD_TYPE) == IOP_RDUMP)) + { +#ifdef UN_USED_FUNC + + if ((DlenStatus & NVMD_STAT) == 0) + { + /* CB for Register Dump */ + ossaGetRegisterDumpCB(agRoot, agContext, OSSA_SUCCESS); + } + else + { + /* CB for Register Dump */ + ossaGetRegisterDumpCB(agRoot, agContext, OSSA_FAILURE); + } +#endif + } + else + { + /* Should not be happened */ + SA_DBG1(("mpiGetNVMDataRsp: (IR=0)Wrong Device type 0x%x\n", iRTdaBnDpsAsNvm)); + } + } + + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_ASSERT((pRequest->valid), "pRequest->valid"); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiGetNVMDataRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2h"); + + /* return value */ + return ret; +} + +/******************************************************************************/ +/*! \brief Phy Event Response from SPCv + * + * Process Phy Event from SPC + * + * \param agRoot Handles for this instance of SAS/SATA LL Layer + * \param pIomb pointer of IOMB + * + * \return success or fail + * + */ +/*******************************************************************************/ + +GLOBAL bit32 mpiPhyStartEvent( + agsaRoot_t *agRoot, + agsaHWEvent_Phy_OUB_t *pIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + + bit32 phyId; + bit32 IOMBStatus; + bit32 tag; + + agsaIORequestDesc_t *pRequest; + agsaContext_t *agContext; + bit32 HwCBStatus; + + if(saRoot == agNULL) + { + SA_DBG1(("mpiPhyStartEvent: saRoot == agNULL\n")); + return(AGSA_RC_FAILURE); + } + smTraceFuncEnter(hpDBG_VERY_LOUD, "2H"); + + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaHWEvent_Phy_OUB_t, tag)) ; + + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + agContext = saRoot->IOMap[tag].agContext; + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + if (agNULL == pRequest) + { + SA_DBG1(("mpiPhyStartEvent: Bad Response IOMB!!! pRequest is NULL. TAG=0x%x \n", tag)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2H"); + return AGSA_RC_FAILURE; + } + + SA_DBG1(("mpiPhyStartEvent: Status 0x%X PhyId 0x%X\n",pIomb->Status,pIomb->ReservedPhyId)); + + OSSA_READ_LE_32(AGROOT, &IOMBStatus, pIomb, OSSA_OFFSET_OF(agsaHWEvent_Phy_OUB_t,Status )); + OSSA_READ_LE_32(AGROOT, &phyId, pIomb, OSSA_OFFSET_OF(agsaHWEvent_Phy_OUB_t,ReservedPhyId )); + + switch (IOMBStatus) + { + case OSSA_MPI_IO_SUCCESS: /* PhyStart operation completed successfully */ + HwCBStatus = 0; + saRoot->phys[phyId].linkstatus = 1; + SA_DBG1(("mpiPhyStartEvent:MPI_IO_SUCCESS IOMBStatus 0x%x for phyId 0x%x\n",IOMBStatus,phyId)); + /* Callback with PHY_UP */ + break; + case OSSA_MPI_ERR_INVALID_PHY_ID: /* identifier specified in the PHY_START command is invalid i.e out of supported range for this product. */ + HwCBStatus = 1; + saRoot->phys[phyId].linkstatus = 0; + SA_DBG1(("mpiPhyStartEvent: MPI_ERR_INVALID_PHY_ID IOMBStatus 0x%x for phyId 0x%x\n",IOMBStatus,phyId)); + ret = AGSA_RC_FAILURE; + break; + case OSSA_MPI_ERR_PHY_ALREADY_STARTED: + HwCBStatus = 2; + saRoot->phys[phyId].linkstatus = 1; + SA_DBG1(("mpiPhyStartEvent: MPI_ERR_PHY_ALREADY_STARTED IOMBStatus 0x%x for phyId 0x%x\n",IOMBStatus,phyId)); + ret = AGSA_RC_FAILURE; + break; + case OSSA_MPI_ERR_INVALID_ANALOG_TBL_IDX: + HwCBStatus = 4; + saRoot->phys[phyId].linkstatus = 0; + SA_DBG1(("mpiPhyStartEvent: MPI_ERR_INVALID_ANALOG_TBL_IDX IOMBStatus 0x%x for phyId 0x%x\n",IOMBStatus,phyId)); + ret = AGSA_RC_FAILURE; + break; + default: + HwCBStatus = 3; + saRoot->phys[phyId].linkstatus = 0; + SA_DBG1(("mpiPhyStartEvent: Unknown IOMBStatus 0x%x for phyId 0x%x\n",IOMBStatus,phyId)); + ret = AGSA_RC_FAILURE; + break; + } + + ossaHwCB(agRoot,agNULL, OSSA_HW_EVENT_PHY_START_STATUS ,((HwCBStatus << SHIFT8) | phyId) ,agContext, agNULL); + + /* return the request to free pool */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_ASSERT((pRequest->valid), "pRequest->valid"); + pRequest->valid = agFALSE; + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiPhyStartEvent: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + return(ret); +} + + +GLOBAL bit32 mpiPhyStopEvent( + agsaRoot_t *agRoot, + agsaHWEvent_Phy_OUB_t *pIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + bit32 phyId; + + bit32 IOMBStatus; + bit32 HwCBStatus; + + bit32 tag; + + agsaIORequestDesc_t *pRequest; + agsaContext_t *agContext; + + agsaPhy_t *pPhy; + agsaPort_t *pPort; + + + if(saRoot == agNULL) + { + SA_DBG1(("mpiPhyStopEvent: saRoot == agNULL\n")); + return(AGSA_RC_FAILURE); + } + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaHWEvent_Phy_OUB_t, tag)) ; + + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + agContext = saRoot->IOMap[tag].agContext; + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + if (agNULL == pRequest) + { + SA_DBG1(("mpiPhyStopEvent: Bad Response IOMB!!! pRequest is NULL. TAG=0x%x \n", tag)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2H"); + return AGSA_RC_FAILURE; + } + + OSSA_READ_LE_32(AGROOT, &IOMBStatus, pIomb, OSSA_OFFSET_OF(agsaHWEvent_Phy_OUB_t,Status )); + OSSA_READ_LE_32(AGROOT, &phyId, pIomb, OSSA_OFFSET_OF(agsaHWEvent_Phy_OUB_t,ReservedPhyId )); + SA_DBG1(("mpiPhyStopEvent: Status %08X PhyId %08X\n",IOMBStatus,phyId)); + + if(smIS_SPCV(agRoot)) + { + phyId &= 0xff; // SPCv PHY_ID is one byte wide + } + + saRoot->phys[phyId].linkstatus = 0; + + switch (IOMBStatus) + { + case OSSA_MPI_IO_SUCCESS: /* PhyStart operation completed successfully */ + SA_DBG1(("mpiPhyStopEvent:MPI_IO_SUCCESS 0x%x for phyId 0x%x\n",IOMBStatus,phyId)); + HwCBStatus = 0; + /* Callback with PHY_DOWN */ + break; + case OSSA_MPI_ERR_INVALID_PHY_ID: /* identifier specified in the PHY_START command is invalid i.e out of supported range for this product. */ + SA_DBG1(("mpiPhyStopEvent: MPI_ERR_INVALID_PHY_ID 0x%x for phyId 0x%x\n",IOMBStatus,phyId)); + HwCBStatus = 1; + break; + case OSSA_MPI_ERR_PHY_NOT_STARTED: /* An attempt to stop a phy which is not started */ + HwCBStatus = 4; + SA_DBG1(("mpiPhyStopEvent: 0x%x for phyId 0x%x\n",IOMBStatus,phyId)); + break; + + case OSSA_MPI_ERR_DEVICES_ATTACHED: /* All the devices in a port need to be deregistered if the PHY_STOP is for the last phy */ + HwCBStatus = 2; + SA_DBG1(("mpiPhyStopEvent: 0x%x for phyId 0x%x\n",IOMBStatus,phyId)); + break; + + default: + HwCBStatus = 3; + SA_DBG1(("mpiPhyStopEvent: Unknown Status 0x%x for phyId 0x%x\n",IOMBStatus,phyId)); + break; + } + + + if(HwCBStatus == 0) + { + pPhy = &(saRoot->phys[phyId]); + /* get the port of the phy */ + pPort = pPhy->pPort; + if ( agNULL != pPort ) + { + SA_DBG1(("siPhyStopCB: phy%d invalidating port\n", phyId)); + /* invalid port state, remove the port */ + pPort->status |= PORT_INVALIDATING; + saRoot->PortMap[pPort->portId].PortStatus |= PORT_INVALIDATING; + /* invalid the port */ + siPortInvalid(agRoot, pPort); + /* map out the portmap */ + saRoot->PortMap[pPort->portId].PortContext = agNULL; + saRoot->PortMap[pPort->portId].PortID = PORT_MARK_OFF; + saRoot->PortMap[pPort->portId].PortStatus |= PORT_INVALIDATING; + ossaHwCB(agRoot,&(pPort->portContext) , OSSA_HW_EVENT_PHY_STOP_STATUS, ((HwCBStatus << SHIFT8) | phyId ),agContext, agNULL); + } + else + { + SA_DBG1(("siPhyStopCB: phy%d - Port is not established\n", phyId)); + ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_PHY_STOP_STATUS, ((HwCBStatus << SHIFT8) | phyId ) , agContext, agNULL); + } + + /* set PHY_STOPPED status */ + PHY_STATUS_SET(pPhy, PHY_STOPPED); + + /* Exclude the phy from a port */ + if ( agNULL != pPort ) + { + /* Acquire port list lock */ + ossaSingleThreadedEnter(agRoot, LL_PORT_LOCK); + + /* Delete the phy from the port */ + pPort->phyMap[phyId] = agFALSE; + saRoot->phys[phyId].pPort = agNULL; + + /* Release port list lock */ + ossaSingleThreadedLeave(agRoot, LL_PORT_LOCK); + } + + } + else + { + SA_DBG1(("siPhyStopCB: Error phy%d - Port is not established\n", phyId)); + ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_PHY_STOP_STATUS, ((HwCBStatus << SHIFT8) | phyId ) , agContext, agNULL); + } + + /* return the request to free pool */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_ASSERT((pRequest->valid), "pRequest->valid"); + pRequest->valid = agFALSE; + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiPhyStartEvent: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + return(ret); +} + + +/******************************************************************************/ +/*! \brief Hardware Event Response from SPC + * + * Process HW Event from SPC + * + * \param agRoot Handles for this instance of SAS/SATA LL Layer + * \param pIomb pointer of IOMB + * + * \return success or fail + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiHWevent( + agsaRoot_t *agRoot, + agsaHWEvent_SPC_OUB_t *pIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaPortContext_t *agPortContext; + agsaSASIdentify_t *IDframe; + agsaFisRegDeviceToHost_t *sataFis; + agsaContext_t *agContext; + agsaPort_t *pPort = agNULL; + bit32 phyId; + bit32 portId; + bit32 Event; + bit32 tag, status; + bit8 linkRate; + bit32 LREventPhyIdPortId; + bit32 npipps, eventParam,npip,port_state; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2j"); + + SA_ASSERT((agNULL !=saRoot ), ""); + if(saRoot == agNULL) + { + SA_DBG1(("mpiHWevent: saRoot == agNULL\n")); + return(AGSA_RC_FAILURE); + } + if(smIS_SPC(agRoot)) + { + OSSA_READ_LE_32(AGROOT, &LREventPhyIdPortId, pIomb, OSSA_OFFSET_OF(agsaHWEvent_SPC_OUB_t, LRStatusEventPhyIdPortId)); + OSSA_READ_LE_32(AGROOT, &npipps, pIomb, OSSA_OFFSET_OF(agsaHWEvent_SPC_OUB_t, NpipPortState)); + OSSA_READ_LE_32(AGROOT, &eventParam, pIomb, OSSA_OFFSET_OF(agsaHWEvent_SPC_OUB_t, EVParam)); + SA_DBG2(("mpiHWEvent: S, LREventPhyIdPortId 0x%08x npipps 0x%08x eventParam 0x%08x\n", LREventPhyIdPortId ,npipps ,eventParam )); + + /* get port context */ + portId = LREventPhyIdPortId & PORTID_MASK; + smTrace(hpDBG_VERY_LOUD,"QK",portId); + /* TP:QK portId */ + + /* get phyId */ + phyId = (LREventPhyIdPortId & PHY_ID_BITS) >> SHIFT4; + + smTrace(hpDBG_VERY_LOUD,"QK",npipps); + /* TP:QK npipps */ + smTrace(hpDBG_VERY_LOUD,"QL",portId); + /* TP:QL portId */ + smTrace(hpDBG_VERY_LOUD,"QM",phyId); + /* TP:QM phyId */ + + SA_DBG1(("mpiHWEvent:SPC, PhyID %d PortID %d NPIP 0x%x PS 0x%x\n", + phyId, portId, (npipps & PHY_IN_PORT_MASK) >> SHIFT4, (npipps & PORT_STATE_MASK))); + } + else + { + OSSA_READ_LE_32(AGROOT, &LREventPhyIdPortId, pIomb, OSSA_OFFSET_OF(agsaHWEvent_V_OUB_t, LRStatEventPortId)); + OSSA_READ_LE_32(AGROOT, &npipps, pIomb, OSSA_OFFSET_OF(agsaHWEvent_V_OUB_t, RsvPhyIdNpipRsvPortState)); + OSSA_READ_LE_32(AGROOT, &eventParam, pIomb, OSSA_OFFSET_OF(agsaHWEvent_V_OUB_t, EVParam)); + SA_DBG2(("mpiHWEvent: V, LREventPhyIdPortId 0x%08x npipps 0x%08x eventParam 0x%08x\n", LREventPhyIdPortId ,npipps ,eventParam )); + + smTrace(hpDBG_VERY_LOUD,"QN",npipps); + /* TP:QN npipps */ + + /* get port context */ + portId = LREventPhyIdPortId & PORTID_MASK; + + smTrace(hpDBG_VERY_LOUD,"QO",portId); + /* TP:QO portId */ + + /* get phyId */ + phyId = (npipps & PHY_ID_V_BITS) >> SHIFT16; + smTrace(hpDBG_VERY_LOUD,"QP",phyId); + /* TP:QP phyId */ + + /* get npipps */ + npip =(npipps & 0xFF00 ) >> SHIFT4; + port_state =(npipps & 0xF ); + npipps = npip | port_state; // Make it look like SPCs nipps + + + SA_DBG1(("mpiHWEvent: V, PhyID 0x%x PortID 0x%x NPIP 0x%x PS 0x%x npipps 0x%x\n", + phyId, portId,npip,port_state,npipps)); + } + + Event = (LREventPhyIdPortId & HW_EVENT_BITS) >> SHIFT8; + + /* get Link Rate */ + linkRate = (bit8)((LREventPhyIdPortId & LINK_RATE_MASK) >> SHIFT28); + /* get status byte */ + status = (LREventPhyIdPortId & STATUS_BITS) >> SHIFT24; + + smTrace(hpDBG_VERY_LOUD,"HA",portId); + /* TP:HA portId */ + smTrace(hpDBG_VERY_LOUD,"HB",linkRate); + /* TP:HB linkRate */ + smTrace(hpDBG_VERY_LOUD,"HC",phyId); + /* TP:HC phyId */ + smTrace(hpDBG_VERY_LOUD,"HD",npipps); + /* TP:HD npipps */ + smTrace(hpDBG_VERY_LOUD,"HE",status); + /* TP:HE status */ + + if (portId > saRoot->phyCount) + { + if (OSSA_PORT_NOT_ESTABLISHED == (npipps & PORT_STATE_MASK)) + { + /* out of range checking for portId */ + SA_DBG1(("mpiHWEvent: PORT_ID is out of range, PhyID %d PortID %d\n", + phyId, portId)); + /* port is not estiblished */ + agPortContext = agNULL; + } + else + { + /* portId is bad and state is correct - should not happen */ + SA_DBG1(("mpiHWEvent: PORT_ID is bad with correct Port State, PhyID %d PortID %d\n", + phyId, portId)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2j"); + return AGSA_RC_FAILURE; + } + } + else + { + SA_DBG2(("mpiHWEvent:PortID 0x%x PortStatus 0x%x PortContext %p\n",saRoot->PortMap[portId & PORTID_MASK].PortID,saRoot->PortMap[portId & PORTID_MASK].PortStatus,saRoot->PortMap[portId & PORTID_MASK].PortContext)); + agPortContext = (agsaPortContext_t *)saRoot->PortMap[portId].PortContext; + } + + if(agPortContext == agNULL) + { + SA_DBG1(("mpiHWEvent: agPortContext is NULL, PhyID %d PortID %d\n", + phyId, portId)); + } + + smTrace(hpDBG_VERY_LOUD,"HF",Event); + /* TP:HF OSSA_HW_EVENT */ + + switch (Event) + { + case OSSA_HW_EVENT_SAS_PHY_UP: + { + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_SAS_PHY_UP, PhyID %d PortID %d NPIP 0x%x PS 0x%x\n", + phyId, portId, (npipps & PHY_IN_PORT_MASK) >> SHIFT4, (npipps & PORT_STATE_MASK))); + + /* get SAS Identify info */ + IDframe = (agsaSASIdentify_t *)&pIomb->sasIdentify; + /* Callback about SAS link up */ + saRoot->phys[phyId].linkstatus |= 2; + saRoot->phys[phyId].sasIdentify.phyIdentifier = IDframe->phyIdentifier; + saRoot->phys[phyId].sasIdentify.deviceType_addressFrameType = IDframe->deviceType_addressFrameType; + + si_memcpy(&(saRoot->phys[phyId].sasIdentify.sasAddressHi),&(IDframe->sasAddressHi),4); + si_memcpy(&(saRoot->phys[phyId].sasIdentify.sasAddressLo),&(IDframe->sasAddressLo),4); + siEventPhyUpRcvd(agRoot, phyId, IDframe, portId, npipps, linkRate); + break; + } + case OSSA_HW_EVENT_SATA_PHY_UP: + { + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_SATA_PHY_UP, PhyID %d PortID %d NPIP 0x%x PS 0x%x\n", + phyId, portId, (npipps & PHY_IN_PORT_MASK) >> SHIFT4, (npipps & PORT_STATE_MASK))); + + /* get SATA FIS info */ + saRoot->phys[phyId].linkstatus |= 2; + sataFis = (agsaFisRegDeviceToHost_t *)&pIomb->sataFis; + /* Callback about SATA Link Up */ + siEventSATASignatureRcvd(agRoot, phyId, (void *)sataFis, portId, npipps, linkRate); + break; + } + case OSSA_HW_EVENT_SATA_SPINUP_HOLD: + { + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_SATA_SPINUP_HOLD, PhyID %d\n", phyId)); + ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_SATA_SPINUP_HOLD, phyId, agNULL, agNULL); + break; + } + case OSSA_HW_EVENT_PHY_DOWN: + { + agsaPhy_t *pPhy = &(saRoot->phys[phyId]); + + if(pPhy) { + osti_memset(&pPhy->sasIdentify,0,sizeof(agsaSASIdentify_t)); + } + saRoot->phys[phyId].linkstatus &= 1; + if (agNULL != agPortContext) + { + pPort = (agsaPort_t *) (agPortContext->sdkData); + } + + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_PHY_DOWN, PhyID %d PortID %d NPIP 0x%x PS 0x%x\n", + phyId, portId, (npipps & PHY_IN_PORT_MASK) >> SHIFT4, npipps & PORT_STATE_MASK)); + + /* callback */ + if ( agNULL != pPort ) + { + if (OSSA_PORT_VALID == (npipps & PORT_STATE_MASK)) + { + pPort->status &= ~PORT_INVALIDATING; + saRoot->PortMap[portId].PortStatus &= ~PORT_INVALIDATING; + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_PHY_DOWN, PhyID %d ~PORT_INVALIDATING \n", phyId)); + } + else + { + if (OSSA_PORT_INVALID == (npipps & PORT_STATE_MASK)) + { + /* set port invalid flag */ + pPort->status |= PORT_INVALIDATING; + saRoot->PortMap[portId].PortStatus |= PORT_INVALIDATING; + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_PHY_DOWN PortInvalid portID %d PortContext %p NPIP 0x%x\n", portId, agPortContext,npipps)); + } + else + { + if (OSSA_PORT_IN_RESET == (npipps & PORT_STATE_MASK)) + { + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_PHY_DOWN PortInReset portID %d PortContext %p\n", portId, agPortContext)); + } + else + { + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_PHY_DOWN Not PortInReset portID %d PortContext %p\n", portId, agPortContext)); + } + } + } + + /* report PhyId, NPIP, PortState */ + phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16); + /* Callback with PHY_DOWN */ + ossaHwCB(agRoot, agPortContext, OSSA_HW_EVENT_PHY_DOWN, phyId, agNULL, agNULL); + } + else + { + /* no portcontext.- error */ + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_PHY_DOWN PhyDown pPort is NULL.\n")); + } + + /* set PHY_DOWN status */ + PHY_STATUS_SET(pPhy, PHY_DOWN); + break; + } + case OSSA_HW_EVENT_PHY_ERR_INBOUND_CRC: + { + agsaPhyErrCountersPage_t errorParam; + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_PHY_ERR_INBOUND_CRC, PhyID %d PortID %d NPIP 0x%x PS 0x%x\n", + phyId, portId, (npipps & PHY_IN_PORT_MASK) >> SHIFT4, npipps & PORT_STATE_MASK)); + si_memset(&errorParam, 0, sizeof(agsaPhyErrCountersPage_t)); + errorParam.inboundCRCError = eventParam; + /* report PhyId, NPIP, PortState */ + phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16); + ossaHwCB(agRoot, agPortContext, OSSA_HW_EVENT_PHY_ERR_INBOUND_CRC, phyId, (void *)&errorParam, agNULL); + break; + } + case OSSA_HW_EVENT_HARD_RESET_RECEIVED: + { + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_HARD_RESET_RECEIVED, PhyID %d PortID %d NPIP 0x%x PS 0x%x\n", + phyId, portId, (npipps & PHY_IN_PORT_MASK) >> SHIFT4, npipps & PORT_STATE_MASK)); + /* report PhyId, NPIP, PortState */ + phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16); + ossaHwCB(agRoot, agPortContext, OSSA_HW_EVENT_HARD_RESET_RECEIVED, phyId, agNULL, agNULL); + break; + } + case OSSA_HW_EVENT_PHY_ERR_INVALID_DWORD: + { + agsaPhyErrCountersPage_t errorParam; + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_LINK_ERR_INVALID_DWORD, PhyID %d PortID %d NPIP 0x%x PS 0x%x\n", + phyId, portId, (npipps & PHY_IN_PORT_MASK) >> SHIFT4, npipps & PORT_STATE_MASK)); + si_memset(&errorParam, 0, sizeof(agsaPhyErrCountersPage_t)); + errorParam.invalidDword = eventParam; + phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16); + ossaHwCB(agRoot, agPortContext, OSSA_HW_EVENT_PHY_ERR_INVALID_DWORD, phyId, (void *)&errorParam, agNULL); + break; + } + case OSSA_HW_EVENT_PHY_ERR_DISPARITY_ERROR: + { + agsaPhyErrCountersPage_t errorParam; + SA_DBG3(("mpiHWEvent: OSSA_HW_EVENT_LINK_ERR_DISPARITY_ERROR, PhyID %d PortID %d NPIP 0x%x PS 0x%x\n", + phyId, portId, (npipps & PHY_IN_PORT_MASK) >> SHIFT4, npipps & PORT_STATE_MASK)); + /* report PhyId, NPIP, PortState */ + si_memset(&errorParam, 0, sizeof(agsaPhyErrCountersPage_t)); + errorParam.runningDisparityError = eventParam; + phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16); + ossaHwCB(agRoot, agPortContext, OSSA_HW_EVENT_PHY_ERR_DISPARITY_ERROR, phyId, (void *)&errorParam, agNULL); + break; + } + case OSSA_HW_EVENT_PHY_ERR_CODE_VIOLATION: + { + agsaPhyErrCountersPage_t errorParam; + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_LINK_ERR_CODE_VIOLATION, PhyID %d PortID %d NPIP 0x%x PS 0x%x\n", + phyId, portId, (npipps & PHY_IN_PORT_MASK) >> SHIFT4, npipps & PORT_STATE_MASK)); + /* report PhyId, NPIP, PortState */ + si_memset(&errorParam, 0, sizeof(agsaPhyErrCountersPage_t)); + errorParam.codeViolation = eventParam; + phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16); + ossaHwCB(agRoot, agPortContext, OSSA_HW_EVENT_PHY_ERR_CODE_VIOLATION, phyId, (void *)&errorParam, agNULL); + break; + } + case OSSA_HW_EVENT_PHY_ERR_LOSS_OF_DWORD_SYNCH: + { + agsaPhyErrCountersPage_t errorParam; + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH, PhyID %d PortID %d NPIP 0x%x PS 0x%x\n", + phyId, portId, (npipps & PHY_IN_PORT_MASK) >> SHIFT4, npipps & PORT_STATE_MASK)); + /* report PhyId, NPIP, PortState */ + si_memset(&errorParam, 0, sizeof(agsaPhyErrCountersPage_t)); + errorParam.lossOfDwordSynch = eventParam; + phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16); + ossaHwCB(agRoot, agPortContext, OSSA_HW_EVENT_PHY_ERR_LOSS_OF_DWORD_SYNCH, phyId, (void *)&errorParam, agNULL); + break; + } + case OSSA_HW_EVENT_PORT_RECOVERY_TIMER_TMO: + { + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_PORT_RECOVERY_TIMER_TMO, PhyID %d PortID %d NPIP 0x%x PS 0x%x\n", + phyId, portId, (npipps & PHY_IN_PORT_MASK) >> SHIFT4, npipps & PORT_STATE_MASK)); + + if (agNULL != agPortContext) + { + pPort = (agsaPort_t *) (agPortContext->sdkData); + } + else + { + SA_ASSERT((agPortContext), "agPortContext agNULL was there a PHY UP?"); + return(AGSA_RC_FAILURE); + } + + /* report PhyId, NPIP, PortState */ + phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16); + ossaHwCB(agRoot, agPortContext, OSSA_HW_EVENT_PORT_RECOVERY_TIMER_TMO, phyId, agNULL, agNULL); + + if (OSSA_PORT_VALID == (npipps & PORT_STATE_MASK)) + { + pPort->status &= ~PORT_INVALIDATING; + saRoot->PortMap[portId].PortStatus &= ~PORT_INVALIDATING; + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_PORT_RECOVERY_TIMER_TMO NOT PORT_INVALIDATING portID %d PortContext %p\n", portId, agPortContext)); + } + else + { + if (OSSA_PORT_INVALID == (npipps & PORT_STATE_MASK)) + { + /* set port invalid flag */ + pPort->status |= PORT_INVALIDATING; + saRoot->PortMap[portId].PortStatus |= PORT_INVALIDATING; + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_PORT_RECOVERY_TIMER_TMO PORT_INVALIDATING portID %d PortContext %p\n", portId, agPortContext)); + } + else + { + if (OSSA_PORT_IN_RESET == (npipps & PORT_STATE_MASK)) + { + SA_DBG1(("mpiHWEvent: PortInReset portID %d PortContext %p\n", portId, agPortContext)); + } + } + } + break; + } + case OSSA_HW_EVENT_PORT_RECOVER: + { + if (agNULL != agPortContext) + { + pPort = (agsaPort_t *) (agPortContext->sdkData); + } + + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_PORT_RECOVER, PhyID %d PortID %d NPIP 0x%x PS 0x%x\n", + phyId, portId, (npipps & PHY_IN_PORT_MASK) >> SHIFT4, npipps & PORT_STATE_MASK)); + + if (OSSA_PORT_VALID == (npipps & PORT_STATE_MASK)) + { + if (agNULL != pPort) + { + /* reset port invalid flag */ + pPort->status &= ~PORT_INVALIDATING; + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_PORT_RECOVER NOT PORT_INVALIDATING portID %d PortContext %p\n", portId, agPortContext)); + } + saRoot->PortMap[portId].PortStatus &= ~PORT_INVALIDATING; + } + /* get SAS Identify info */ + IDframe = (agsaSASIdentify_t *)&pIomb->sasIdentify; + /* report PhyId, NPIP, PortState and LinkRate */ + phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16) | (linkRate << SHIFT8); + ossaHwCB(agRoot, agPortContext, OSSA_HW_EVENT_PORT_RECOVER, phyId, agNULL, (void *)IDframe); + break; + } + case OSSA_HW_EVENT_PHY_STOP_STATUS: + { + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_PHY_STOP_STATUS PhyId=0x%x, status=0x%x eventParam=0x%x\n", phyId, status,eventParam)); + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaHWEvent_SPC_OUB_t, EVParam)); + + switch(eventParam) + { + case 0: + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_PHY_STOP_STATUS Stopped 0\n" )); + break; + case 1: + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_PHY_STOP_STATUS INVALID_PHY 1\n" )); + break; + case 2: + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_PHY_STOP_STATUS DEVICES_ATTACHED 2\n" )); + break; + case 3: + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_PHY_STOP_STATUS OTHER_FAILURE 3\n" )); + break; + case 4: + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_PHY_STOP_STATUS PHY_NOT_ENABLED 4\n" )); + break; + default: + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_PHY_STOP_STATUS Unknown code 0x%x\n", eventParam)); + break; + } + + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_PHY_STOP_STATUS phyId 0x%x status 0x%x eventParam 0x%x\n", phyId, status,eventParam)); + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + SA_ASSERT((pRequest), "pRequest NULL"); + SA_ASSERT((pRequest->valid), "pRequest->valid"); + + agContext = saRoot->IOMap[tag].agContext; + + siPhyStopCB(agRoot, phyId, status, agContext, portId, npipps); + + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiHWevent: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + break; + } + case OSSA_HW_EVENT_BROADCAST_CHANGE: + { + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_BROADCAST_CHANGE, PhyID %d PortID %d NPIP 0x%x PS 0x%x\n", + phyId, portId, (npipps & PHY_IN_PORT_MASK) >> SHIFT4, npipps & PORT_STATE_MASK)); + /* report PhyId, NPIP, PortState */ + phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16); + ossaHwCB(agRoot, agPortContext, OSSA_HW_EVENT_BROADCAST_CHANGE, phyId, agNULL, agNULL); + break; + } + case OSSA_HW_EVENT_BROADCAST_SES: + { + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_BROADCAST_CHANGE_SES, PhyID %d PortID %d NPIP 0x%x PS 0x%x\n", + phyId, portId, (npipps & PHY_IN_PORT_MASK) >> SHIFT4, npipps & PORT_STATE_MASK)); + /* report PhyId, NPIP, PortState */ + phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16); + ossaHwCB(agRoot, agPortContext, OSSA_HW_EVENT_BROADCAST_SES, phyId, agNULL, agNULL); + break; + } + case OSSA_HW_EVENT_BROADCAST_EXP: + { + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_BROADCAST_EXP, PhyID %d PortID %d NPIP 0x%x PS 0x%x\n", + phyId, portId, (npipps & PHY_IN_PORT_MASK) >> SHIFT4, npipps & PORT_STATE_MASK)); + /* report PhyId, NPIP, PortState */ + phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16); + ossaHwCB(agRoot, agPortContext, OSSA_HW_EVENT_BROADCAST_EXP, phyId, agNULL, agNULL); + break; + } + case OSSA_HW_EVENT_ID_FRAME_TIMEOUT: + { + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_ID_FRAME_TIMEOUT, PhyID %d PortID %d NPIP 0x%x PS 0x%x\n", + phyId, portId, (npipps & PHY_IN_PORT_MASK) >> SHIFT4, npipps & PORT_STATE_MASK)); + /* report PhyId, NPIP, PortState */ + phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16); + ossaHwCB(agRoot, agPortContext, OSSA_HW_EVENT_ID_FRAME_TIMEOUT, phyId, agNULL, agNULL); + break; + } + case OSSA_HW_EVENT_PHY_START_STATUS: + { + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaHWEvent_SPC_OUB_t, EVParam)) ; + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + + SA_ASSERT((pRequest), "pRequest"); + if( pRequest == agNULL) + { + SA_DBG1(("mpiHWevent: pRequest (%p) NULL\n", pRequest)); + ret = AGSA_RC_FAILURE; + break; + } + + agContext = saRoot->IOMap[tag].agContext; + + /* makeup for CB */ + status = (status << 8) | phyId; + ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_PHY_START_STATUS, status, agContext, agNULL); + + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_ASSERT((pRequest->valid), "pRequest->valid"); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiHWevent: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_PHY_START_STATUS, PhyID %d\n", phyId)); + + break; + } + case OSSA_HW_EVENT_PHY_ERR_PHY_RESET_FAILED: + { + agsaPhyErrCountersPage_t errorParam; + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_PHY_ERR_PHY_RESET_FAILED, PhyID %d PortID %d NPIP 0x%x PS 0x%x\n", + phyId, portId, (npipps & PHY_IN_PORT_MASK) >> SHIFT4, npipps & PORT_STATE_MASK)); + /* report PhyId, NPIP, PortState */ + si_memset(&errorParam, 0, sizeof(agsaPhyErrCountersPage_t)); + errorParam.phyResetProblem = eventParam; + phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16); + ossaHwCB(agRoot, agPortContext, OSSA_HW_EVENT_PHY_ERR_PHY_RESET_FAILED, phyId, (void *)&errorParam, agNULL); + break; + } + case OSSA_HW_EVENT_PORT_RESET_TIMER_TMO: + { + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_PORT_RESET_TIMER_TMO, PhyID %d PortID %d\n", phyId, portId)); + /* report PhyId, NPIP, PortState */ + phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16); + ossaHwCB(agRoot, agPortContext, OSSA_HW_EVENT_PORT_RESET_TIMER_TMO, phyId, agNULL, agNULL); + break; + } + case OSSA_HW_EVENT_PORT_RESET_COMPLETE: + { + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_PORT_RESET_COMPLETE, PhyID %d PortID %d\n", phyId, portId)); + /* get SAS Identify info */ + IDframe = (agsaSASIdentify_t *)&pIomb->sasIdentify; + /* report PhyId, NPIP, PortState and LinkRate */ + phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16) | (linkRate << SHIFT8); + ossaHwCB(agRoot, agPortContext, OSSA_HW_EVENT_PORT_RESET_COMPLETE, phyId, agNULL, (void *)IDframe); + break; + } + case OSSA_HW_EVENT_BROADCAST_ASYNCH_EVENT: + { + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_BROADCAST_ASYNCH_EVENT, PhyID %d PortID %d\n", phyId, portId)); + /* report PhyId, NPIP, PortState */ + phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16); + ossaHwCB(agRoot, agPortContext, OSSA_HW_EVENT_BROADCAST_ASYNCH_EVENT, phyId, agNULL, agNULL); + break; + } + case OSSA_HW_EVENT_IT_NEXUS_LOSS: + { + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_IT_NEXUS_LOSS, PhyID %d PortID %d status 0x%X\n", phyId, portId,status)); + break; + } + case OSSA_HW_EVENT_OPEN_RETRY_BACKOFF_THR_ADJUSTED: + { + SA_DBG1(("mpiHWEvent: OSSA_HW_EVENT_OPEN_RETRY_BACKOFF_THR_ADJUSTED, PhyID %d PortID %d status 0x%X\n", phyId, portId,status)); + ossaHwCB(agRoot, agPortContext, OSSA_HW_EVENT_OPEN_RETRY_BACKOFF_THR_ADJUSTED, phyId, agNULL, agNULL); + break; + } + + default: + { + SA_DBG1(("mpiHWEvent: Unknown HW Event 0x%x status 0x%X\n", Event ,status)); + break; + } + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2j"); + return ret; +} + +/******************************************************************************/ +/*! \brief SPC MPI SMP Completion + * + * This function handles the SMP completion. + * + * \param agRoot Handles for this instance of SAS/SATA hardware + * \param pIomb pointer of Message1 + * \param bc buffer count + * + * \return The read value + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiSMPCompletion( + agsaRoot_t *agRoot, + agsaSMPCompletionRsp_t *pIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + bit32 status; + bit32 tag; + bit32 param; + agsaIORequestDesc_t *pRequest; + + SA_DBG3(("mpiSMPCompletion: start, HTAG=0x%x\n", pIomb->tag)); + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2k"); + + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaSMPCompletionRsp_t, tag)) ; + OSSA_READ_LE_32(AGROOT, &status, pIomb, OSSA_OFFSET_OF(agsaSMPCompletionRsp_t, status)) ; + OSSA_READ_LE_32(AGROOT, ¶m, pIomb, OSSA_OFFSET_OF(agsaSMPCompletionRsp_t, param)) ; + /* get SMP request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + SA_DBG1(("mpiSMPCompletion: Bad Response IOMB!!! pRequest is NULL. TAG=0x%x STATUS=0x%x PARAM=0x%x\n", tag, status, param)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2k"); + return AGSA_RC_FAILURE; + } + + switch (status) + { + case OSSA_IO_SUCCESS: + SA_DBG3(("mpiSMPCompletion: OSSA_IO_SUCCESS HTAG = 0x%x\n", tag)); + /* process message */ + siSMPRespRcvd(agRoot, pIomb, param, tag); + break; + + case OSSA_IO_OVERFLOW: + SA_DBG1(("mpiSMPCompletion: OSSA_IO_OVERFLOW HTAG = 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_OVERFLOW++; + /* SMP failed */ + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + + case OSSA_IO_ABORTED: + SA_DBG1(("mpiSMPCompletion: OSSA_IO_ABORTED HTAG = 0x%x\n", tag)); + + saRoot->IoErrorCount.agOSSA_IO_ABORTED++; +#ifdef SA_PRINTOUT_IN_WINDBG +#ifndef DBG + DbgPrint("agOSSA_IO_ABORTED %d\n", saRoot->IoErrorCount.agOSSA_IO_ABORTED); +#endif /* DBG */ +#endif /* SA_PRINTOUT_IN_WINDBG */ + /* SMP failed */ + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + + case OSSA_IO_NO_DEVICE: + SA_DBG1(("mpiSMPCompletion: OSSA_IO_NO_DEVICE HTAG = 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_NO_DEVICE++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + + case OSSA_IO_ERROR_HW_TIMEOUT: + SA_DBG1(("mpiSMPCompletion: OSSA_IO_ERROR_HW_TIMEOUT HTAG = 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_ERROR_HW_TIMEOUT++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + + case OSSA_IO_XFER_ERROR_BREAK: + SA_DBG1(("mpiSMPCompletion: OSSA_IO_XFER_ERROR_BREAK HTAG = 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_BREAK++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + + case OSSA_IO_XFER_ERROR_PHY_NOT_READY: + SA_DBG1(("mpiSMPCompletion: OSSA_IO_XFER_ERROR_PHY_NOT_READY HTAG = 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_PHY_NOT_READY++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + + case OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: + SA_DBG1(("mpiSMPCompletion: OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED HTAG = 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + + case OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION: + SA_DBG1(("mpiSMPCompletion: OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION HTAG = 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + + case OSSA_IO_OPEN_CNX_ERROR_BREAK: + SA_DBG1(("mpiSMPCompletion: OSSA_IO_OPEN_CNX_ERROR_BREAK HTAG = 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_BREAK++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: + SA_DBG1(("mpiSMPCompletion: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS HTAG = 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + + case OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION: + SA_DBG1(("mpiSMPCompletion: OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION HTAG = 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + + case OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: + SA_DBG1(("mpiSMPCompletion: OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED HTAG = 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + + case OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION: + SA_DBG1(("mpiSMPCompletion: OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION HTAG = 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + + case OSSA_IO_XFER_ERROR_RX_FRAME: + SA_DBG1(("mpiSMPCompletion: OSSA_IO_XFER_ERROR_RX_FRAME HTAG = 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_RX_FRAME++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + + case OSSA_IO_XFER_OPEN_RETRY_TIMEOUT: + SA_DBG1(("mpiSMPCompletion: OSSA_IO_XFER_OPEN_RETRY_TIMEOUT HTAG = 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_XFER_OPEN_RETRY_TIMEOUT++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + + case OSSA_IO_ERROR_INTERNAL_SMP_RESOURCE: + SA_DBG1(("mpiSMPCompletion: OSSA_IO_ERROR_INTERNAL_SMP_RESOURCE HTAG = 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_ERROR_INTERNAL_SMP_RESOURCE++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + + case OSSA_IO_PORT_IN_RESET: + SA_DBG1(("mpiSMPCompletion: OSSA_IO_PORT_IN_RESET HTAG = 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_PORT_IN_RESET++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + + case OSSA_IO_DS_NON_OPERATIONAL: + SA_DBG1(("mpiSMPCompletion: OSSA_IO_DS_NON_OPERATIONAL HTAG = 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_DS_NON_OPERATIONAL++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + + case OSSA_IO_DS_IN_RECOVERY: + SA_DBG1(("mpiSMPCompletion: OSSA_IO_DS_IN_RECOVERY HTAG = 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_DS_IN_RECOVERY++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + + case OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: + SA_DBG1(("mpiSMPCompletion: OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY HTAG = 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + + case OSSA_IO_ABORT_IN_PROGRESS: + SA_DBG1(("mpiSMPCompletion: OSSA_IO_ABORT_IN_PROGRESS HTAG = 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_ABORT_IN_PROGRESS++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + + case OSSA_IO_ABORT_DELAYED: + SA_DBG1(("mpiSMPCompletion:OSSA_IO_ABORT_DELAYED HTAG = 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_ABORT_DELAYED++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + + case OSSA_IO_INVALID_LENGTH: + SA_DBG1(("mpiSMPCompletion: OSSA_IO_INVALID_LENGTH HTAG = 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_INVALID_LENGTH++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: + SA_DBG1(("mpiSMPCompletion: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED HTAG = 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: + SA_DBG1(("mpiSMPCompletion: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO HTAG = 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: + SA_DBG1(("mpiSMPCompletion: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST HTAG = 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: + SA_DBG1(("mpiSMPCompletion: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE HTAG = 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: + SA_DBG1(("mpiSMPCompletion: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED HTAG = 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + + case OSSA_IO_DS_INVALID: + SA_DBG1(("mpiSMPCompletion: OSSA_IO_DS_INVALID HTAG = 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_DS_INVALID++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + + case OSSA_IO_XFER_READ_COMPL_ERR: + SA_DBG1(("mpiSMPCompletion: OSSA_IO_XFER_READ_COMPL_ERR HTAG = 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_XFER_READ_COMPL_ERR++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + + case OSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE: + SA_DBG1(("mpiSMPCompletion: OSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE HTAG = 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + + case OSSA_MPI_ERR_OFFLOAD_DIF_OR_ENC_NOT_ENABLED: + SA_DBG1(("mpiSMPCompletion: OSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE HTAG = 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_MPI_ERR_OFFLOAD_DIF_OR_ENC_NOT_ENABLED++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + + case OSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED: + SA_DBG1(("mpiSMPCompletion: OSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED HTAG = 0x%x\n", tag)); + saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED++; + siAbnormal(agRoot, pRequest, status, 0, 0); + break; + + default: + SA_DBG1(("mpiSMPCompletion: Unknown Status = 0x%x Tag 0x%x\n", status, tag)); + saRoot->IoErrorCount.agOSSA_IO_UNKNOWN_ERROR++; + /* not allowed case. Therefore, assert */ + SA_ASSERT((agFALSE), "mpiSMPCompletion: Unknown Status"); + break; + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2k"); + return ret; +} + +/******************************************************************************/ +/*! \brief SPC MPI Get Device Handle Command Response + * + * This function handles the response of Get Device Handle Command. + * + * \param agRoot Handles for this instance of SAS/SATA hardware + * \param pIomb pointer of Message + * \param bc buffer count + * + * \return The read value + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiGetDevHandleRsp( + agsaRoot_t *agRoot, + agsaGetDevHandleRsp_t *pIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaPortContext_t *agPortContext; + agsaContext_t *agContext; + agsaDeviceDesc_t *pDevice; + bit8 portId; + bit32 deviceid=0, deviceIdc, i; + bit32 DeviceIdcPortId, tag; + + SA_DBG3(("mpiGetDevHandleRsp: start, HTAG=0x%x\n", pIomb->tag)); + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2m"); + + OSSA_READ_LE_32(AGROOT, &DeviceIdcPortId, pIomb, OSSA_OFFSET_OF(agsaGetDevHandleRsp_t, DeviceIdcPortId)) ; + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaGetDevHandleRsp_t, tag)) ; + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + agContext = saRoot->IOMap[tag].agContext; + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + if (agNULL == pRequest) + { + SA_DBG1(("mpiGetDevHandleRsp: Bad Response IOMB!!! pRequest is NULL. TAG=0x%x DeviceIdcPortId=0x%x\n", tag, DeviceIdcPortId)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2m"); + return AGSA_RC_FAILURE; + } + + /* get port context */ + portId = (bit8)(DeviceIdcPortId & PORTID_MASK); + SA_DBG2(("mpiGetDevHandleRsp:PortID 0x%x PortStatus 0x%x PortContext %p\n",saRoot->PortMap[portId & PORTID_MASK].PortID,saRoot->PortMap[portId & PORTID_MASK].PortStatus,saRoot->PortMap[portId & PORTID_MASK].PortContext)); + agPortContext = (agsaPortContext_t *)saRoot->PortMap[portId].PortContext; + + /* get Device ID count */ + deviceIdc = (bit8)((DeviceIdcPortId & DEVICE_IDC_BITS) >> SHIFT8); + + /* based on the deviceIDC to get all device handles */ + for (i = 0; i < deviceIdc; i++) + { + OSSA_READ_LE_32(AGROOT, &deviceid, pIomb, OSSA_OFFSET_OF(agsaGetDevHandleRsp_t, deviceId[i])) ; + /* find device handle from device index */ + pDevice = (agsaDeviceDesc_t *)saRoot->DeviceMap[deviceid & DEVICE_ID_BITS].DeviceHandle; + if (pDevice->targetDevHandle.sdkData) + saRoot->DeviceHandle[i] = &(pDevice->targetDevHandle); + else + saRoot->DeviceHandle[i] = &(pDevice->initiatorDevHandle); + } + + SA_DBG1(("mpiGetDevHandleRsp:deviceid 0x%x 0x%x\n",deviceid, (deviceid & DEVICE_ID_BITS))); + /* call back oslayer */ + ossaGetDeviceHandlesCB(agRoot, agContext, agPortContext, saRoot->DeviceHandle, deviceIdc); + + /* return the request to free pool */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_ASSERT((pRequest->valid), "pRequest->valid"); + pRequest->valid = agFALSE; + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiGetDevHandleRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2m"); + + return ret; +} + +/******************************************************************************/ +/*! \brief SPC MPI Phy Control Command Response + * + * This function handles the response of PHY Control Command. + * + * \param agRoot Handles for this instance of SAS/SATA hardware + * \param pIomb pointer of Message + * + * \return The read value + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiPhyCntrlRsp( + agsaRoot_t *agRoot, + agsaLocalPhyCntrlRsp_t *pIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaContext_t *agContext = agNULL; + bit32 phyId, operation, status, tag, phyOpId; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2n"); + + SA_DBG3(("mpiPhyCntrlRsp: start, HTAG=0x%x,\n", pIomb->tag)); + + /* get tag */ + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaLocalPhyCntrlRsp_t, tag)) ; + OSSA_READ_LE_32(AGROOT, &phyOpId, pIomb, OSSA_OFFSET_OF(agsaLocalPhyCntrlRsp_t, phyOpId)) ; + OSSA_READ_LE_32(AGROOT, &status, pIomb, OSSA_OFFSET_OF(agsaLocalPhyCntrlRsp_t, status)) ; + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + SA_DBG1(("mpiPhyCntrlRsp: Bad Response IOMB!!! pRequest is NULL. TAG=0x%x STATUS=0x%x PhyOpId=0x%x\n", tag, status, phyOpId)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2n"); + return AGSA_RC_FAILURE; + } + agContext = saRoot->IOMap[tag].agContext; + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + phyId = phyOpId & LOCAL_PHY_PHYID; + operation = (phyOpId & LOCAL_PHY_OP_BITS) >> SHIFT8; + + + SA_DBG3(("mpiPhyCntrlRsp: phyId=0x%x Operation=0x%x Status=0x%x\n", phyId, operation, status)); + + if( pRequest->completionCB == agNULL ) + { + /* call back with the status */ + ossaLocalPhyControlCB(agRoot, agContext, phyId, operation, status, agNULL); + } + else + { + (*(ossaLocalPhyControlCB_t)(pRequest->completionCB))(agRoot, agContext, phyId, operation, status, agNULL ); + } + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_ASSERT((pRequest->valid), "pRequest->valid"); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiPhyCntrlRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2n"); + return ret; +} + +/******************************************************************************/ +/*! \brief SPC MPI Device Register Command Response + * + * This function handles the response of Device Register Command. + * + * \param agRoot Handles for this instance of SAS/SATA hardware + * \param pIomb pointer of Message + * + * \return The read value + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiDeviceRegRsp( + agsaRoot_t *agRoot, + agsaDeviceRegistrationRsp_t *pIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = agNULL; + agsaIORequestDesc_t *pRequest; + agsaContext_t *agContext; + bit32 deviceId; + agsaDeviceDesc_t *pDevice = agNULL; + agsaDeviceDesc_t *pDeviceRemove = agNULL; + bit32 deviceIdx,status, tag; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2p"); + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + SA_ASSERT((agNULL != saRoot), ""); + + SA_DBG3(("mpiDeviceRegRsp: start, HTAG=0x%x\n", pIomb->tag)); + + SA_ASSERT((NULL != saRoot->DeviceRegistrationCB), "DeviceRegistrationCB can not be NULL"); + OSSA_READ_LE_32(AGROOT, &deviceId, pIomb, OSSA_OFFSET_OF(agsaDeviceRegistrationRsp_t, deviceId)) ; + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaDeviceRegistrationRsp_t, tag)) ; + OSSA_READ_LE_32(AGROOT, &status, pIomb, OSSA_OFFSET_OF(agsaDeviceRegistrationRsp_t, status)) ; + + SA_DBG1(("mpiDeviceRegRsp: deviceID 0x%x \n", deviceId)); + + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + SA_DBG1(("mpiDeviceRegRsp: Bad IOMB!!! pRequest is NULL. TAG=0x%x, STATUS=0x%x DEVICEID=0x%x\n", tag, status, deviceId)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2p"); + return AGSA_RC_FAILURE; + } + + pDevice = pRequest->pDevice; + + agContext = saRoot->IOMap[tag].agContext; + SA_ASSERT((pRequest->valid), "pRequest->valid"); + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + /* get Device Id or status */ + SA_DBG3(("mpiDeviceRegRsp: hosttag 0x%x\n", tag)); + SA_DBG3(("mpiDeviceRegRsp: deviceID 0x%x Device Context %p\n", deviceId, pDevice)); + + if (agNULL == pDevice) + { + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiDeviceRegRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("mpiDeviceRegRsp: warning!!! no device is found\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2p"); + return AGSA_RC_FAILURE; + } + + if (agNULL == saRoot->DeviceRegistrationCB) + { + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiDeviceRegRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("mpiDeviceRegRsp: warning!!! no DeviceRegistrationCB is found\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "2p"); + return AGSA_RC_FAILURE; + } + + + if(smIS_SPCV(agRoot)) + { + switch( status) + { + case 0: + status = OSSA_SUCCESS; + break; + case MPI_ERR_DEVICE_HANDLE_UNAVAILABLE: + status = OSSA_FAILURE_OUT_OF_RESOURCE; + break; + case MPI_ERR_DEVICE_ALREADY_REGISTERED: + status = OSSA_FAILURE_DEVICE_ALREADY_REGISTERED; + break; + case MPI_ERR_PHY_ID_INVALID: + status = OSSA_FAILURE_INVALID_PHY_ID; + break; + case MPI_ERR_PHY_ID_ALREADY_REGISTERED: + status = OSSA_FAILURE_PHY_ID_ALREADY_REGISTERED; + break; + case MPI_ERR_PORT_INVALID_PORT_ID: + status = OSSA_FAILURE_PORT_ID_OUT_OF_RANGE; + break; + case MPI_ERR_PORT_STATE_NOT_VALID: + status = OSSA_FAILURE_PORT_NOT_VALID_STATE; + break; + case MPI_ERR_DEVICE_TYPE_NOT_VALID: + status = OSSA_FAILURE_DEVICE_TYPE_NOT_VALID; + break; + default: + SA_ASSERT((0), "DeviceRegistration Unknown status"); + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiDeviceRegRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + return AGSA_RC_FAILURE; + } + } + + switch (status) + { + case OSSA_SUCCESS: + /* mapping the device handle and device id */ + deviceIdx = deviceId & DEVICE_ID_BITS; + OS_ASSERT(deviceIdx < MAX_IO_DEVICE_ENTRIES, "deviceIdx MAX_IO_DEVICE_ENTRIES"); + saRoot->DeviceMap[deviceIdx].DeviceIdFromFW = deviceId; + saRoot->DeviceMap[deviceIdx].DeviceHandle = (void *)pDevice; + pDevice->DeviceMapIndex = deviceId; + + (*(ossaDeviceRegistrationCB_t)(saRoot->DeviceRegistrationCB))(agRoot, + agContext, + OSSA_SUCCESS, + &pDevice->targetDevHandle, + deviceId + ); + + break; + case OSSA_FAILURE_OUT_OF_RESOURCE: + SA_DBG1(("mpiDeviceRegRsp: OSSA_FAILURE_OUT_OF_RESOURCE\n")); + /* remove device from LL device list */ + siPortDeviceRemove(agRoot, pDevice->pPort, pDevice, agFALSE); + + /* call ossaDeviceRegistrationCB_t */ + (*(ossaDeviceRegistrationCB_t)(saRoot->DeviceRegistrationCB))(agRoot, + agContext, + OSSA_FAILURE_OUT_OF_RESOURCE, + &pDevice->targetDevHandle, + deviceId + ); + + + break; + case OSSA_FAILURE_DEVICE_ALREADY_REGISTERED: + /* get original device handle and device id */ + pDeviceRemove = pDevice; + deviceIdx = deviceId & DEVICE_ID_BITS; + OS_ASSERT(deviceIdx < MAX_IO_DEVICE_ENTRIES, "deviceIdx MAX_IO_DEVICE_ENTRIES"); + pDevice = (agsaDeviceDesc_t *)saRoot->DeviceMap[deviceIdx].DeviceHandle; + SA_DBG1(("mpiDeviceRegRsp: OSSA_FAILURE_DEVICE_ALREADY_REGISTERED, existing deviceContext %p\n", pDevice)); + /* no auto registration */ + if (pDevice != agNULL) + { + /* remove device from LL device list */ + siPortDeviceListRemove(agRoot, pDevice->pPort, pDeviceRemove); + + /* call ossaDeviceRegistrationCB_t */ + (*(ossaDeviceRegistrationCB_t)(saRoot->DeviceRegistrationCB))(agRoot, + agContext, + OSSA_FAILURE_DEVICE_ALREADY_REGISTERED, + &pDevice->targetDevHandle, + deviceId + ); + } + else + { + SA_DBG1(("mpiDeviceRegRsp: pDevice is NULL. TAG=0x%x, STATUS=0x%x DEVICEID=0x%x\n", tag, status, deviceId)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "2p"); + return AGSA_RC_FAILURE; + } + + break; + case OSSA_FAILURE_INVALID_PHY_ID: + SA_DBG1(("mpiDeviceRegRsp: OSSA_FAILURE_INVALID_PHY_ID\n")); + /* remove device from LL device list */ + siPortDeviceRemove(agRoot, pDevice->pPort, pDevice, agFALSE); + + /* call ossaDeviceRegistrationCB_t */ + (*(ossaDeviceRegistrationCB_t)(saRoot->DeviceRegistrationCB))(agRoot, + agContext, + OSSA_FAILURE_INVALID_PHY_ID, + &pDevice->targetDevHandle, + deviceId + ); + break; + case OSSA_FAILURE_PHY_ID_ALREADY_REGISTERED: + /* get original device handle and device id */ + pDeviceRemove = pDevice; + deviceIdx = deviceId & DEVICE_ID_BITS; + OS_ASSERT(deviceIdx < MAX_IO_DEVICE_ENTRIES, "deviceIdx MAX_IO_DEVICE_ENTRIES"); + pDevice = (agsaDeviceDesc_t *)saRoot->DeviceMap[deviceIdx].DeviceHandle; + SA_DBG1(("mpiDeviceRegRsp: OSSA_FAILURE_PHY_ID_ALREADY_REGISTERED, existing deviceContext %p\n", pDevice)); + /* no auto registration */ + if (pDevice != agNULL) + { + /* remove device from LL device list */ + siPortDeviceListRemove(agRoot, pDevice->pPort, pDeviceRemove); + + /* call ossaDeviceRegistrationCB_t */ + (*(ossaDeviceRegistrationCB_t)(saRoot->DeviceRegistrationCB))(agRoot, + agContext, + OSSA_FAILURE_PHY_ID_ALREADY_REGISTERED, + &pDevice->targetDevHandle, + deviceId + ); + } + else + { + SA_DBG1(("mpiDeviceRegRsp: pDevice is NULL. TAG=0x%x, STATUS=0x%x DEVICEID=0x%x\n", tag, status, deviceId)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "2p"); + return AGSA_RC_FAILURE; + } + + break; + case OSSA_FAILURE_PORT_ID_OUT_OF_RANGE: + SA_DBG1(("mpiDeviceRegRsp: OSSA_FAILURE_OUT_OF_RESOURCE\n")); + /* remove device from LL device list */ + siPortDeviceRemove(agRoot, pDevice->pPort, pDevice, agFALSE); + + /* call ossaDeviceRegistrationCB_t */ + (*(ossaDeviceRegistrationCB_t)(saRoot->DeviceRegistrationCB))(agRoot, + agContext, + OSSA_FAILURE_PORT_ID_OUT_OF_RANGE, + &pDevice->targetDevHandle, + deviceId + ); + break; + case OSSA_FAILURE_PORT_NOT_VALID_STATE: + SA_DBG1(("mpiDeviceRegRsp: OSSA_FAILURE_PORT_NOT_VALID_STATE\n")); + /* remove device from LL device list */ + siPortDeviceRemove(agRoot, pDevice->pPort, pDevice, agFALSE); + + /* call ossaDeviceRegistrationCB_t */ + (*(ossaDeviceRegistrationCB_t)(saRoot->DeviceRegistrationCB))(agRoot, + agContext, + OSSA_FAILURE_PORT_NOT_VALID_STATE, + &pDevice->targetDevHandle, + deviceId + ); + break; + case OSSA_FAILURE_DEVICE_TYPE_NOT_VALID: + SA_DBG1(("mpiDeviceRegRsp: OSSA_FAILURE_DEVICE_TYPE_NOT_VALID\n")); + /* remove device from LL device list */ + siPortDeviceRemove(agRoot, pDevice->pPort, pDevice, agFALSE); + /* call ossaDeviceRegistrationCB_t */ + (*(ossaDeviceRegistrationCB_t)(saRoot->DeviceRegistrationCB))(agRoot, + agContext, + OSSA_FAILURE_DEVICE_TYPE_NOT_VALID, + &pDevice->targetDevHandle, + deviceId + ); + break; + default: + SA_DBG3(("mpiDeviceRegRsp, unknown status in response %d\n", status)); + break; + } + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiDeviceRegRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'f', "2p"); + return ret; +} + +/******************************************************************************/ +/*! \brief SPC MPI Deregister Device Command Response + * + * This function handles the response of Deregister Command. + * + * \param agRoot Handles for this instance of SAS/SATA hardware + * \param pIomb pointer of Message + * + * \return The read value + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiDeregDevHandleRsp( + agsaRoot_t *agRoot, + agsaDeregDevHandleRsp_t *pIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaDevHandle_t *agDevHandle; + agsaContext_t *agContext; + agsaDeviceDesc_t *pDevice; + bit32 deviceIdx, status, tag; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2r"); + SA_ASSERT((NULL != saRoot->DeviceDeregistrationCB), "DeviceDeregistrationCB can not be NULL"); + + SA_DBG3(("mpiDeregDevHandleRsp: start, HTAG=0x%x\n", pIomb->tag)); + + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaDeregDevHandleRsp_t, tag)) ; + OSSA_READ_LE_32(AGROOT, &status, pIomb, OSSA_OFFSET_OF(agsaDeregDevHandleRsp_t, status)) ; + OSSA_READ_LE_32(AGROOT, &deviceIdx, pIomb, OSSA_OFFSET_OF(agsaDeregDevHandleRsp_t, deviceId)) ; + /* get request from IOMap */ + + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + SA_DBG1(("mpiDeregDevHandleRsp: Bad Response IOMB!!! pRequest is NULL. TAG=0x%x STATUS=0x%x deviceIdx 0x%x\n", tag, status,deviceIdx)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2r"); + return AGSA_RC_FAILURE; + } + + agContext = saRoot->IOMap[tag].agContext; + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + SA_ASSERT((pRequest->valid), "pRequest->valid"); + + pDevice = pRequest->pDevice; + if (pDevice != agNULL) + { + if (pDevice->targetDevHandle.sdkData) + { + agDevHandle = &(pDevice->targetDevHandle); + } + else + { + agDevHandle = &(pDevice->initiatorDevHandle); + } + } + else + { + SA_DBG1(("mpiDeregDevHandleRsp: pDevice is NULL")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2r"); + return AGSA_RC_FAILURE; + } + + if (agNULL == agDevHandle) + { + SA_DBG1(("mpiDeregDevHandleRsp: warning!!! no deviceHandle is found")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "2r"); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiDeregDevHandleRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + return AGSA_RC_FAILURE; + } + + SA_DBG1(("mpiDeregDevHandleRsp: deviceID 0x%x Device Context %p\n", pDevice->DeviceMapIndex, pDevice)); + + if (agNULL == saRoot->DeviceDeregistrationCB) + { + SA_DBG1(("mpiDeregDevHandleRsp: warning!!! no DeviceDeregistrationCB is found")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "2r"); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiDeregDevHandleRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + return AGSA_RC_FAILURE; + } + + switch (status) + { + case OSSA_SUCCESS: + (*(ossaDeregisterDeviceHandleCB_t)(saRoot->DeviceDeregistrationCB))(agRoot, + agContext, + agDevHandle, + OSSA_SUCCESS + ); + siRemoveDevHandle(agRoot, agDevHandle); + break; + case OSSA_ERR_DEVICE_HANDLE_INVALID: + case OSSA_INVALID_HANDLE: + (*(ossaDeregisterDeviceHandleCB_t)(saRoot->DeviceDeregistrationCB))(agRoot, + agContext, + agDevHandle, + status + ); +// already removed and no device to remove +// siRemoveDevHandle(agRoot, agDevHandle); + SA_DBG1(("mpiDeregDevRegRsp, OSSA_INVALID_HANDLE status in response %d\n", status)); + break; + case OSSA_ERR_DEVICE_BUSY: + (*(ossaDeregisterDeviceHandleCB_t)(saRoot->DeviceDeregistrationCB))(agRoot, + agContext, + agDevHandle, + status + ); + SA_DBG1(("mpiDeregDevRegRsp, OSSA_ERR_DEVICE_BUSY status in response %d\n", status)); + ret = AGSA_RC_BUSY; + break; + default: + SA_DBG1(("mpiDeregDevRegRsp, unknown status in response 0x%X\n", status)); + break; + } + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiDeregDevHandleRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "2r"); + return ret; +} + + +/******************************************************************************/ +/*! \brief Get Phy Profile Response SPCv + * + * This routine handles the response of Get Phy Profile Command Response + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb Pointer of IOMB Message + * + * \return sucess or fail + * SPC only + */ +/*******************************************************************************/ + +GLOBAL bit32 mpiGetPhyProfileRsp( + agsaRoot_t *agRoot, + agsaGetPhyProfileRspV_t *pIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaContext_t *agContext; + bit32 status, tag; + + bit32 Reserved_SOP_PHYID; + bit32 PhyId; + bit32 SOP; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2J"); + OSSA_READ_LE_32(agRoot, &status, pIomb, OSSA_OFFSET_OF(agsaGetPhyProfileRspV_t, status)); + OSSA_READ_LE_32(agRoot, &tag, pIomb, OSSA_OFFSET_OF(agsaGetPhyProfileRspV_t, tag)); + /* get TAG */ + SA_DBG1(("mpiGetPhyProfileRsp: HTag=0x%x\n", tag)); + + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + SA_DBG1(("mpiGetPhyProfileRsp: Bad Response IOMB!!! pRequest is NULL. TAG=0x%x STATUS=0x%x\n", tag, status)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2J"); + return AGSA_RC_FAILURE; + } + + agContext = saRoot->IOMap[tag].agContext; + + OSSA_READ_LE_32(agRoot, &Reserved_SOP_PHYID, pIomb, OSSA_OFFSET_OF(agsaGetPhyProfileRspV_t,Reserved_Ppc_SOP_PHYID )); + + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + SA_ASSERT((pRequest->valid), "pRequest->valid"); + SA_DBG1(("mpiGetPhyProfileRsp: %p\n",pIomb)); + SA_DBG1(("mpiGetPhyProfileRsp: completionCB %p\n",pRequest->completionCB )); + + SOP = (Reserved_SOP_PHYID & 0xFF00) >> SHIFT8; + PhyId = Reserved_SOP_PHYID & 0xFF; + + /* check status success or failure */ + if (status) + { + /* status is FAILED */ + SA_DBG1(("mpiGetPhyProfileRsp:AGSA_RC_FAILURE 0x%08X\n", status)); + switch(SOP) + { + case AGSA_SAS_PHY_ERR_COUNTERS_PAGE: + { + SA_DBG1(("mpiGetPhyProfileRsp: AGSA_SAS_PHY_ERR_COUNTERS_PAGE SOP 0x%x\n", SOP)); + ossaGetPhyProfileCB(agRoot, agContext, status, SOP, PhyId , agNULL ); + break; + } + case AGSA_SAS_PHY_ERR_COUNTERS_CLR_PAGE: + { + SA_DBG1(("mpiGetPhyProfileRsp: AGSA_SAS_PHY_ERR_COUNTERS_CLR_PAGE SOP 0x%x\n", SOP)); + ossaGetPhyProfileCB(agRoot, agContext, status, SOP, PhyId , agNULL ); + break; + } + case AGSA_SAS_PHY_BW_COUNTERS_PAGE: + { + SA_DBG1(("mpiGetPhyProfileRsp: GET_SAS_PHY_BW_COUNTERS SOP 0x%x\n", SOP)); + ossaGetPhyProfileCB(agRoot, agContext, status, SOP, PhyId , agNULL ); + break; + } + case AGSA_SAS_PHY_ANALOG_SETTINGS_PAGE: + { + SA_DBG1(("mpiGetPhyProfileRsp: AGSA_SAS_PHY_ANALOG_SETTINGS_PAGE SOP 0x%x\n", SOP)); + ossaGetPhyProfileCB(agRoot, agContext, status, SOP, PhyId , agNULL ); + break; + } + case AGSA_SAS_PHY_GENERAL_STATUS_PAGE: + { + SA_DBG1(("mpiGetPhyProfileRsp: AGSA_SAS_PHY_GENERAL_STATUS_PAGE SOP 0x%x\n", SOP)); + ossaGetPhyProfileCB(agRoot, agContext, status, SOP, PhyId , agNULL ); + break; + } + case AGSA_PHY_SNW3_PAGE: + { + SA_DBG1(("mpiGetPhyProfileRsp: AGSA_PHY_SNW3_PAGE SOP 0x%x\n", SOP)); + ossaGetPhyProfileCB(agRoot, agContext, status, SOP, PhyId , agNULL ); + break; + } + case AGSA_PHY_RATE_CONTROL_PAGE: + { + SA_DBG1(("mpiGetPhyProfileRsp: AGSA_PHY_RATE_CONTROL_PAGE SOP 0x%x\n", SOP)); + ossaGetPhyProfileCB(agRoot, agContext, status, SOP, PhyId , agNULL ); + break; + } + case AGSA_SAS_PHY_OPEN_REJECT_RETRY_BACKOFF_THRESHOLD_PAGE: + { + SA_DBG1(("mpiGetPhyProfileRsp: AGSA_SAS_PHY_OPEN_REJECT_RETRY_BACKOFF_THRESHOLD_PAGE SOP 0x%x\n", SOP)); + ossaGetPhyProfileCB(agRoot, agContext, status, SOP, PhyId , agNULL ); + break; + } + default: + { + SA_DBG1(("mpiGetPhyProfileRsp: undefined SOP 0x%x\n", SOP)); + break; + } + } + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2J"); + return AGSA_RC_FAILURE; + } + else + { + SA_DBG1(("mpiGetPhyProfileRsp: SUCCESS type 0x%X\n",SOP )); + switch(SOP) + { + case AGSA_SAS_PHY_ERR_COUNTERS_CLR_PAGE: + /* call back with the status */ + SA_DBG1(("mpiGetPhyProfileRsp: AGSA_SAS_PHY_ERR_COUNTERS_CLR_PAGE PhyId %d\n",PhyId)); + ossaGetPhyProfileCB(agRoot, agContext, status, SOP, PhyId , agNULL); + break; + case AGSA_SAS_PHY_ERR_COUNTERS_PAGE: + { + + agsaPhyErrCountersPage_t Errors; + + OSSA_READ_LE_32(agRoot, &Errors.invalidDword, pIomb, OSSA_OFFSET_OF(agsaGetPhyProfileRspV_t,PageSpecificArea[0] )); + OSSA_READ_LE_32(agRoot, &Errors.runningDisparityError, pIomb, OSSA_OFFSET_OF(agsaGetPhyProfileRspV_t,PageSpecificArea[1] )); + OSSA_READ_LE_32(agRoot, &Errors.codeViolation, pIomb, OSSA_OFFSET_OF(agsaGetPhyProfileRspV_t,PageSpecificArea[2] )); + OSSA_READ_LE_32(agRoot, &Errors.lossOfDwordSynch, pIomb, OSSA_OFFSET_OF(agsaGetPhyProfileRspV_t,PageSpecificArea[3] )); + OSSA_READ_LE_32(agRoot, &Errors.phyResetProblem, pIomb, OSSA_OFFSET_OF(agsaGetPhyProfileRspV_t,PageSpecificArea[4] )); + OSSA_READ_LE_32(agRoot, &Errors.inboundCRCError, pIomb, OSSA_OFFSET_OF(agsaGetPhyProfileRspV_t,PageSpecificArea[5] )); + + /* call back with the status */ + ossaGetPhyProfileCB(agRoot, agContext, status, SOP, PhyId , &Errors); + /* status is SUCCESS */ + + SA_DBG3(("mpiGetPhyProfileRsp: pIomb %p\n",pIomb)); + SA_DBG1(("mpiGetPhyProfileRsp: Reserved_SOP_PHYID 0x%08X\n",Reserved_SOP_PHYID)); + SA_DBG1(("mpiGetPhyProfileRsp: invalidDword 0x%08X\n",Errors.invalidDword )); + SA_DBG1(("mpiGetPhyProfileRsp: runningDisparityError 0x%08X\n",Errors.runningDisparityError )); + SA_DBG1(("mpiGetPhyProfileRsp: codeViolation 0x%08X\n",Errors.codeViolation )); + SA_DBG1(("mpiGetPhyProfileRsp: lossOfDwordSynch 0x%08X\n",Errors.lossOfDwordSynch )); + SA_DBG1(("mpiGetPhyProfileRsp: phyResetProblem 0x%08X\n",Errors.phyResetProblem )); + SA_DBG1(("mpiGetPhyProfileRsp: inboundCRCError 0x%08X\n",Errors.inboundCRCError )); + break; + + } + case AGSA_SAS_PHY_BW_COUNTERS_PAGE: + { + + agsaPhyBWCountersPage_t bw_counts; + OSSA_READ_LE_32(agRoot, &bw_counts.TXBWCounter, pIomb, OSSA_OFFSET_OF(agsaGetPhyProfileRspV_t,PageSpecificArea[0] )); + OSSA_READ_LE_32(agRoot, &bw_counts.RXBWCounter, pIomb, OSSA_OFFSET_OF(agsaGetPhyProfileRspV_t,PageSpecificArea[1] )); + + SA_DBG1(("mpiGetPhyProfileRsp: GET_SAS_PHY_BW_COUNTERS TX 0x%08X RX 0x%08X\n",bw_counts.TXBWCounter,bw_counts.RXBWCounter)); + /* call back with the status */ + ossaGetPhyProfileCB(agRoot, agContext, status, SOP, PhyId, &bw_counts); + break; + } + case AGSA_SAS_PHY_ANALOG_SETTINGS_PAGE: + { + agsaPhyAnalogSettingsPage_t analog; + + SA_DBG1(("mpiGetPhyProfileRsp: AGSA_SAS_PHY_ANALOG_SETTINGS_PAGE 0x%X\n",SOP)); + OSSA_READ_LE_32(agRoot, &analog.Dword0, pIomb, OSSA_OFFSET_OF(agsaGetPhyProfileRspV_t,PageSpecificArea[0] )); + OSSA_READ_LE_32(agRoot, &analog.Dword1, pIomb, OSSA_OFFSET_OF(agsaGetPhyProfileRspV_t,PageSpecificArea[1] )); + OSSA_READ_LE_32(agRoot, &analog.Dword2, pIomb, OSSA_OFFSET_OF(agsaGetPhyProfileRspV_t,PageSpecificArea[2] )); + OSSA_READ_LE_32(agRoot, &analog.Dword3, pIomb, OSSA_OFFSET_OF(agsaGetPhyProfileRspV_t,PageSpecificArea[3] )); + OSSA_READ_LE_32(agRoot, &analog.Dword4, pIomb, OSSA_OFFSET_OF(agsaGetPhyProfileRspV_t,PageSpecificArea[4] )); + /* call back with the status */ + ossaGetPhyProfileCB(agRoot, agContext, status, SOP, PhyId, &analog); + break; + } + + case AGSA_SAS_PHY_GENERAL_STATUS_PAGE: + { + agsaSASPhyGeneralStatusPage_t GenStatus; + OSSA_READ_LE_32(agRoot, &GenStatus.Dword0, pIomb, OSSA_OFFSET_OF(agsaGetPhyProfileRspV_t,PageSpecificArea[0] )); + OSSA_READ_LE_32(agRoot, &GenStatus.Dword1, pIomb, OSSA_OFFSET_OF(agsaGetPhyProfileRspV_t,PageSpecificArea[1] )); + SA_DBG1(("mpiGetPhyProfileRsp: AGSA_SAS_PHY_GENERAL_STATUS_PAGE SOP 0x%x 0x%x 0x%x\n", SOP,GenStatus.Dword0,GenStatus.Dword1)); + ossaGetPhyProfileCB(agRoot, agContext, status, SOP, PhyId , &GenStatus ); + break; + } + case AGSA_PHY_SNW3_PAGE: + { + agsaPhySNW3Page_t Snw3; + OSSA_READ_LE_32(agRoot, &Snw3.LSNW3, pIomb, OSSA_OFFSET_OF(agsaGetPhyProfileRspV_t,PageSpecificArea[0] )); + OSSA_READ_LE_32(agRoot, &Snw3.RSNW3, pIomb, OSSA_OFFSET_OF(agsaGetPhyProfileRspV_t,PageSpecificArea[1] )); + + SA_DBG1(("mpiGetPhyProfileRsp: AGSA_PHY_SNW3_PAGE SOP 0x%x\n", SOP)); + ossaGetPhyProfileCB(agRoot, agContext, status, SOP, PhyId , &Snw3 ); + break; + } + case AGSA_PHY_RATE_CONTROL_PAGE: + { + agsaPhyRateControlPage_t RateControl; + OSSA_READ_LE_32(agRoot, &RateControl.Dword0, pIomb, OSSA_OFFSET_OF(agsaGetPhyProfileRspV_t,PageSpecificArea[0] )); + OSSA_READ_LE_32(agRoot, &RateControl.Dword1, pIomb, OSSA_OFFSET_OF(agsaGetPhyProfileRspV_t,PageSpecificArea[1] )); + OSSA_READ_LE_32(agRoot, &RateControl.Dword2, pIomb, OSSA_OFFSET_OF(agsaGetPhyProfileRspV_t,PageSpecificArea[2] )); + SA_DBG1(("mpiGetPhyProfileRsp: AGSA_PHY_RATE_CONTROL_PAGE SOP 0x%x\n", SOP)); + ossaGetPhyProfileCB(agRoot, agContext, status, SOP, PhyId , &RateControl ); + break; + } + case AGSA_SAS_PHY_OPEN_REJECT_RETRY_BACKOFF_THRESHOLD_PAGE: + { + agsaSASPhyOpenRejectRetryBackOffThresholdPage_t Backoff; + OSSA_READ_LE_32(agRoot, &Backoff.Dword0, pIomb, OSSA_OFFSET_OF(agsaGetPhyProfileRspV_t,PageSpecificArea[0] )); + OSSA_READ_LE_32(agRoot, &Backoff.Dword1, pIomb, OSSA_OFFSET_OF(agsaGetPhyProfileRspV_t,PageSpecificArea[1] )); + OSSA_READ_LE_32(agRoot, &Backoff.Dword2, pIomb, OSSA_OFFSET_OF(agsaGetPhyProfileRspV_t,PageSpecificArea[2] )); + OSSA_READ_LE_32(agRoot, &Backoff.Dword3, pIomb, OSSA_OFFSET_OF(agsaGetPhyProfileRspV_t,PageSpecificArea[3] )); + SA_DBG1(("mpiGetPhyProfileRsp: AGSA_SAS_PHY_OPEN_REJECT_RETRY_BACKOFF_THRESHOLD_PAGE SOP 0x%x\n", SOP)); + ossaGetPhyProfileCB(agRoot, agContext, status, SOP, PhyId , &Backoff ); + break; + } + default: + { + SA_DBG1(("mpiGetPhyProfileRsp: undefined successful SOP 0x%x\n", SOP)); + break; + } + + } + } + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiGetPhyProfileRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "2J"); + return ret; +} + + +GLOBAL bit32 mpiSetPhyProfileRsp( + agsaRoot_t *agRoot, + agsaSetPhyProfileRspV_t *pIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaContext_t *agContext; + bit32 status, tag; + + bit32 Reserved_Ppc_PHYID; + bit32 PhyId; + bit16 SOP; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2Q"); + OSSA_READ_LE_32(agRoot, &status, pIomb, OSSA_OFFSET_OF(agsaSetPhyProfileRspV_t, status)); + OSSA_READ_LE_32(agRoot, &tag, pIomb, OSSA_OFFSET_OF(agsaSetPhyProfileRspV_t, tag)); + OSSA_READ_LE_32(agRoot, &Reserved_Ppc_PHYID, pIomb, OSSA_OFFSET_OF(agsaSetPhyProfileRspV_t, Reserved_Ppc_PHYID)); + /* get TAG */ + SA_DBG1(("mpiSetPhyProfileRsp: HTag=0x%x\n", tag)); + + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + SA_DBG1(("mpiSetPhyProfileRsp: Bad Response IOMB!!! pRequest is NULL. TAG=0x%x STATUS=0x%x\n", tag, status)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2Q"); + return AGSA_RC_FAILURE; + } + + agContext = saRoot->IOMap[tag].agContext; + + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + SA_DBG1(("mpiSetPhyProfileRsp: %p\n",pIomb)); + + SOP = pRequest->SOP; + PhyId = Reserved_Ppc_PHYID & 0xFF; + + /* check status success or failure */ + if (status) + { + /* status is FAILED */ + SA_DBG1(("mpiSetPhyProfileRsp:AGSA_RC_FAILURE 0x%08X\n", status)); + switch(SOP) + { + case AGSA_SAS_PHY_ANALOG_SETTINGS_PAGE: + { + SA_DBG1(("mpiSetPhyProfileRsp: AGSA_SAS_PHY_ANALOG_SETTINGS_PAGE SOP 0x%x\n", SOP)); + ossaSetPhyProfileCB(agRoot, agContext, status, SOP, PhyId, agNULL ); + break; + } + case AGSA_PHY_SNW3_PAGE: + { + SA_DBG1(("mpiSetPhyProfileRsp: AGSA_PHY_SNW3_PAGE SOP 0x%x\n", SOP)); + ossaSetPhyProfileCB(agRoot, agContext, status, SOP, PhyId, agNULL ); + break; + } + + case AGSA_PHY_RATE_CONTROL_PAGE: + { + SA_DBG1(("mpiSetPhyProfileRsp: AGSA_PHY_RATE_CONTROL_PAGE SOP 0x%x\n", SOP)); + ossaSetPhyProfileCB(agRoot, agContext, status, SOP, PhyId, agNULL ); + break; + } + case AGSA_SAS_PHY_MISC_PAGE: + { + SA_DBG1(("mpiSetPhyProfileRsp: AGSA_SAS_PHY_MISC_PAGE SOP 0x%x\n", SOP)); + ossaSetPhyProfileCB(agRoot, agContext, status, SOP, PhyId, agNULL ); + break; + } + + default: + { + SA_DBG1(("mpiSetPhyProfileRsp: undefined SOP 0x%x\n", SOP)); + break; + } + } + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2Q"); + return AGSA_RC_FAILURE; + } + else + { + SA_DBG1(("mpiSetPhyProfileRsp: SUCCESS type 0x%X\n",SOP )); + switch(SOP) + { + case AGSA_PHY_SNW3_PAGE: + case AGSA_PHY_RATE_CONTROL_PAGE: + { + SA_DBG1(("mpiSetPhyProfileRsp: Status 0x%x SOP 0x%x PhyId %d\n",status, SOP, PhyId)); + ossaSetPhyProfileCB(agRoot, agContext, status, SOP, PhyId, agNULL ); + break; + + } + case AGSA_SAS_PHY_ANALOG_SETTINGS_PAGE: + { + agsaPhyAnalogSettingsPage_t analog; + + SA_DBG1(("mpiSetPhyProfileRsp: AGSA_SAS_PHY_ANALOG_SETTINGS_PAGE 0x%X\n",SOP)); + OSSA_READ_LE_32(agRoot, &analog.Dword0, pIomb, OSSA_OFFSET_OF(agsaSetPhyProfileRspV_t,PageSpecificArea[0] )); + OSSA_READ_LE_32(agRoot, &analog.Dword1, pIomb, OSSA_OFFSET_OF(agsaSetPhyProfileRspV_t,PageSpecificArea[1] )); + OSSA_READ_LE_32(agRoot, &analog.Dword2, pIomb, OSSA_OFFSET_OF(agsaSetPhyProfileRspV_t,PageSpecificArea[2] )); + OSSA_READ_LE_32(agRoot, &analog.Dword3, pIomb, OSSA_OFFSET_OF(agsaSetPhyProfileRspV_t,PageSpecificArea[3] )); + OSSA_READ_LE_32(agRoot, &analog.Dword4, pIomb, OSSA_OFFSET_OF(agsaSetPhyProfileRspV_t,PageSpecificArea[4] )); + /* call back with the status */ + ossaSetPhyProfileCB(agRoot, agContext, status, SOP, PhyId, &analog ); + break; + } + default: + { + SA_DBG1(("mpiSetPhyProfileRsp: undefined successful SOP 0x%x\n", SOP)); + break; + } + + } + } + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_ASSERT((pRequest->valid), "pRequest->valid"); + SA_DBG1(("mpiSetPhyProfileRsp: completionCB %p\n",pRequest->completionCB )); + + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiSetPhyProfileRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "2Q"); + return ret; +} + + + +/******************************************************************************/ +/*! \brief Get Device Information Response + * + * This routine handles the response of Get Device Info Command Response + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb Pointer of IOMB Message + * + * \return sucess or fail + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiGetDevInfoRsp( + agsaRoot_t *agRoot, + agsaGetDevInfoRspV_t *pIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaDevHandle_t *agDevHandle; + agsaDeviceDesc_t *pDevice; + agsaContext_t *agContext; + agsaDeviceInfo_t commonDevInfo; + bit32 ARSrateSMPTimeOutPortID, IRMcnITNexusTimeOut, status, tag; + bit32 deviceid; + bit32 sasAddrHi; + bit32 sasAddrLow; +#if defined(SALLSDK_DEBUG) + bit32 option; +#endif /* SALLSDK_DEBUG */ + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2M"); + OSSA_READ_LE_32(AGROOT, &status, pIomb, OSSA_OFFSET_OF(agsaGetDevInfoRspV_t, status)); + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaGetDevInfoRspV_t, tag)); + /* get TAG */ + SA_DBG3(("mpiGetDevInfoRsp: HTag=0x%x\n", tag)); + + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + SA_DBG1(("mpiGetDevInfoRsp: Bad Response IOMB!!! pRequest is NULL. TAG=0x%x STATUS=0x%x\n", tag, status)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2M"); + return AGSA_RC_FAILURE; + } + + agContext = saRoot->IOMap[tag].agContext; + + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + SA_ASSERT((pRequest->valid), "pRequest->valid"); + + /* check status success or failure */ + if (status) + { + /* status is FAILED */ + ossaGetDeviceInfoCB(agRoot, agContext, agNULL, OSSA_DEV_INFO_INVALID_HANDLE, agNULL); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2M"); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; +#if defined(SALLSDK_DEBUG) + option = (bit32)pRequest->DeviceInfoCmdOption; +#endif /* SALLSDK_DEBUG */ + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiGetDevInfoRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + return AGSA_RC_FAILURE; + } + + /* status is SUCCESS */ + OSSA_READ_LE_32(AGROOT, &deviceid, pIomb, OSSA_OFFSET_OF(agsaGetDevInfoRspV_t, deviceId)); + OSSA_READ_LE_32(AGROOT, &ARSrateSMPTimeOutPortID, pIomb, OSSA_OFFSET_OF(agsaGetDevInfoRspV_t, ARSrateSMPTimeOutPortID)); + OSSA_READ_LE_32(AGROOT, &IRMcnITNexusTimeOut, pIomb, OSSA_OFFSET_OF(agsaGetDevInfoRspV_t, IRMcnITNexusTimeOut)); + OSSA_READ_LE_32(AGROOT, &sasAddrHi, pIomb, OSSA_OFFSET_OF(agsaGetDevInfoRspV_t,sasAddrHi[0] )); + OSSA_READ_LE_32(AGROOT, &sasAddrLow, pIomb, OSSA_OFFSET_OF(agsaGetDevInfoRspV_t,sasAddrLow[0] )); + + /* find device handle from device index */ + pDevice = (agsaDeviceDesc_t *)saRoot->DeviceMap[deviceid & DEVICE_ID_BITS].DeviceHandle; + if (pDevice != agNULL) + { + if (pDevice->targetDevHandle.sdkData) + { + agDevHandle = &(pDevice->targetDevHandle); + } + else + { + agDevHandle = &(pDevice->initiatorDevHandle); + } + } + else + { + SA_DBG1(("mpiGetDevInfoRsp: pDevice is NULL")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "2M"); + return AGSA_RC_FAILURE; + } + + if (agDevHandle == agNULL) + { + SA_DBG1(("mpiGetDevInfoRsp: warning!!! no deviceHandle is found")); + ossaGetDeviceInfoCB(agRoot, agContext, agNULL, OSSA_DEV_INFO_INVALID_HANDLE, agNULL); + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "2M"); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; +#if defined(SALLSDK_DEBUG) + option = (bit32)pRequest->DeviceInfoCmdOption; +#endif /* SALLSDK_DEBUG */ + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiGetDevInfoRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + return AGSA_RC_FAILURE; + } + + /* setup common device information */ + si_memset(&commonDevInfo, 0, sizeof(agsaDeviceInfo_t)); + commonDevInfo.smpTimeout = (bit16)((ARSrateSMPTimeOutPortID >> SHIFT8 ) & SMPTO_VBITS); + commonDevInfo.it_NexusTimeout = (bit16)(IRMcnITNexusTimeOut & NEXUSTO_VBITS); + commonDevInfo.firstBurstSize = (bit16)((IRMcnITNexusTimeOut >> SHIFT16) & FIRST_BURST_MCN); + commonDevInfo.devType_S_Rate = (bit8)((ARSrateSMPTimeOutPortID >> SHIFT24) & 0x3f); + commonDevInfo.flag = (bit32)((ARSrateSMPTimeOutPortID >> SHIFT30 ) & FLAG_VBITS); + commonDevInfo.flag |= IRMcnITNexusTimeOut & 0xf0000; + if (IRMcnITNexusTimeOut & 0x1000000) + { + commonDevInfo.flag |= 0x100000; + } + + /* check SAS device then copy SAS Address */ + if ( ((ARSrateSMPTimeOutPortID & DEV_TYPE_BITS) >> SHIFT28 == 0x00) || + ((ARSrateSMPTimeOutPortID & DEV_TYPE_BITS) >> SHIFT28 == 0x01)) + { + /* copy the sasAddressHi byte-by-byte : no endianness */ + commonDevInfo.sasAddressHi[0] = pIomb->sasAddrHi[0]; + commonDevInfo.sasAddressHi[1] = pIomb->sasAddrHi[1]; + commonDevInfo.sasAddressHi[2] = pIomb->sasAddrHi[2]; + commonDevInfo.sasAddressHi[3] = pIomb->sasAddrHi[3]; + + /* copy the sasAddressLow byte-by-byte : no endianness */ + commonDevInfo.sasAddressLo[0] = pIomb->sasAddrLow[0]; + commonDevInfo.sasAddressLo[1] = pIomb->sasAddrLow[1]; + commonDevInfo.sasAddressLo[2] = pIomb->sasAddrLow[2]; + commonDevInfo.sasAddressLo[3] = pIomb->sasAddrLow[3]; + } + + /* copy common device information to SAS and SATA device common header*/ + si_memcpy(&pDevice->devInfo.sasDeviceInfo.commonDevInfo, &commonDevInfo, sizeof(agsaDeviceInfo_t)); + si_memcpy(&pDevice->devInfo.sataDeviceInfo.commonDevInfo, &commonDevInfo, sizeof(agsaDeviceInfo_t)); + + /* setup device firstBurstSize infomation */ + pDevice->devInfo.sataDeviceInfo.commonDevInfo.firstBurstSize = + (bit16)((IRMcnITNexusTimeOut >> SHIFT16) & FIRST_BURST); + + /* Display Device Information */ + SA_DBG3(("mpiGetDevInfoRsp: smpTimeout=0x%x\n", pDevice->devInfo.sasDeviceInfo.commonDevInfo.smpTimeout)); + SA_DBG3(("mpiGetDevInfoRsp: it_NexusTimeout=0x%x\n", pDevice->devInfo.sasDeviceInfo.commonDevInfo.it_NexusTimeout)); + SA_DBG3(("mpiGetDevInfoRsp: firstBurstSize=0x%x\n", pDevice->devInfo.sasDeviceInfo.commonDevInfo.firstBurstSize)); + SA_DBG3(("mpiGetDevInfoRsp: devType_S_Rate=0x%x\n", pDevice->devInfo.sasDeviceInfo.commonDevInfo.devType_S_Rate)); + + /* + D518 P2I[15-12]: Disk HP DG0146FAMWL , HPDE, WWID=5000c500:17459a31, 6.0G + */ + + SA_DBG1(("mpiGetDevInfoRsp: Device 0x%08X flag 0x%08X %s WWID= %02x%02x%02x%02x:%02x%02x%02x%02x, %s\n", + deviceid, + pDevice->devInfo.sasDeviceInfo.commonDevInfo.flag, + (pDevice->devInfo.sasDeviceInfo.commonDevInfo.devType_S_Rate & 0xF0) == 0x20 ? "SATA DA" : + (pDevice->devInfo.sasDeviceInfo.commonDevInfo.devType_S_Rate & 0xF0) == 0x10 ? "SSP/SMP" : + (pDevice->devInfo.sasDeviceInfo.commonDevInfo.devType_S_Rate & 0xF0) == 0x0 ? " STP " : "Unknown", + + pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressHi[3], + pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressHi[2], + pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressHi[1], + pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressHi[0], + pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressLo[3], + pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressLo[2], + pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressLo[1], + pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressLo[0], + + (pDevice->devInfo.sasDeviceInfo.commonDevInfo.devType_S_Rate & 0xF) == 8 ? " 1.5G" : + (pDevice->devInfo.sasDeviceInfo.commonDevInfo.devType_S_Rate & 0xF) == 9 ? " 3.0G" : + (pDevice->devInfo.sasDeviceInfo.commonDevInfo.devType_S_Rate & 0xF) == 10 ? " 6.0G" : + (pDevice->devInfo.sasDeviceInfo.commonDevInfo.devType_S_Rate & 0xF) == 11 ? "12.0G" : "????" )); + + ossaGetDeviceInfoCB(agRoot, agContext, agDevHandle, OSSA_DEV_INFO_NO_EXTENDED_INFO, &commonDevInfo); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; +#if defined(SALLSDK_DEBUG) + option = (bit32)pRequest->DeviceInfoCmdOption; +#endif /* SALLSDK_DEBUG */ + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiGetDevInfoRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "2M"); + return ret; +} + +/******************************************************************************/ +/*! \brief Get Device Information Response + * + * This routine handles the response of Get Device Info Command Response + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb Pointer of IOMB Message + * + * \return sucess or fail + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiGetDevInfoRspSpc( + agsaRoot_t *agRoot, + agsaGetDevInfoRsp_t *pIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaDevHandle_t *agDevHandle; + agsaDeviceDesc_t *pDevice; + agsaContext_t *agContext; + bit32 dTypeSrateSMPTOPortID, FirstBurstSizeITNexusTimeOut, status, tag; + bit32 deviceid; + bit32 sasAddrHi; + bit32 sasAddrLow; + bit32 Info_avail = 0; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2t"); + OSSA_READ_LE_32(AGROOT, &status, pIomb, OSSA_OFFSET_OF(agsaGetDevInfoRsp_t, status)); + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaGetDevInfoRsp_t, tag)); + /* get TAG */ + SA_DBG3(("mpiGetDevInfoRspSpc: HTag=0x%x\n", tag)); + + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + SA_DBG1(("mpiGetDevInfoRspSpc: Bad Response IOMB!!! pRequest is NULL. TAG=0x%x STATUS=0x%x\n", tag, status)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2t"); + return AGSA_RC_FAILURE; + } + + agContext = saRoot->IOMap[tag].agContext; + + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + SA_ASSERT((pRequest->valid), "pRequest->valid"); + + /* check status success or failure */ + if (status) + { + /* status is FAILED */ + ossaGetDeviceInfoCB(agRoot, agContext, agNULL, OSSA_DEV_INFO_INVALID_HANDLE, agNULL); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2t"); + return AGSA_RC_FAILURE; + } + + /* status is SUCCESS */ + OSSA_READ_LE_32(AGROOT, &deviceid, pIomb, OSSA_OFFSET_OF(agsaGetDevInfoRsp_t, deviceId)); + OSSA_READ_LE_32(AGROOT, &dTypeSrateSMPTOPortID, pIomb, OSSA_OFFSET_OF(agsaGetDevInfoRsp_t, dTypeSrateSMPTOArPortID)); + OSSA_READ_LE_32(AGROOT, &FirstBurstSizeITNexusTimeOut, pIomb, OSSA_OFFSET_OF(agsaGetDevInfoRsp_t, FirstBurstSizeITNexusTimeOut)); + OSSA_READ_LE_32(AGROOT, &sasAddrHi, pIomb, OSSA_OFFSET_OF(agsaGetDevInfoRsp_t, sasAddrHi[0])); + OSSA_READ_LE_32(AGROOT, &sasAddrLow, pIomb, OSSA_OFFSET_OF(agsaGetDevInfoRsp_t, sasAddrLow[0])); + + + SA_DBG2(("mpiGetDevInfoRspSpc:deviceid 0x%08X\n",deviceid)); + SA_DBG2(("mpiGetDevInfoRspSpc:dTypeSrateSMPTOPortID 0x%08X\n",dTypeSrateSMPTOPortID)); + SA_DBG2(("mpiGetDevInfoRspSpc:FirstBurstSizeITNexusTimeOut 0x%08X\n",FirstBurstSizeITNexusTimeOut)); + SA_DBG2(("mpiGetDevInfoRspSpc:sasAddrHi 0x%08X\n",sasAddrHi)); + SA_DBG2(("mpiGetDevInfoRspSpc:sasAddrLow 0x%08X\n",sasAddrLow)); + + + /* find device handle from device index */ + pDevice = (agsaDeviceDesc_t *)saRoot->DeviceMap[deviceid & DEVICE_ID_BITS].DeviceHandle; + if (pDevice != agNULL) + { + if (pDevice->targetDevHandle.sdkData) + { + agDevHandle = &(pDevice->targetDevHandle); + } + else + { + agDevHandle = &(pDevice->initiatorDevHandle); + } + } + else + { + SA_DBG1(("mpiGetDevInfoRspSpc: pDevice is NULL")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "2t"); + return AGSA_RC_FAILURE; + } + + if (agDevHandle == agNULL) + { + SA_DBG1(("mpiGetDevInfoRspSpc: warning!!! no deviceHandle is found")); + ossaGetDeviceInfoCB(agRoot, agContext, agNULL, OSSA_DEV_INFO_INVALID_HANDLE, agNULL); + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "2t"); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiGetDevInfoRspSpc: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + return AGSA_RC_FAILURE; + } + + Info_avail = OSSA_DEV_INFO_NO_EXTENDED_INFO; + + /* setup device common infomation */ + pDevice->devInfo.sasDeviceInfo.commonDevInfo.smpTimeout = + (bit16)((dTypeSrateSMPTOPortID >> SHIFT8 ) & SMPTO_BITS); + + pDevice->devInfo.sataDeviceInfo.commonDevInfo.smpTimeout = + (bit16)((dTypeSrateSMPTOPortID >> SHIFT8 ) & SMPTO_BITS); + + pDevice->devInfo.sasDeviceInfo.commonDevInfo.it_NexusTimeout = + (bit16)(FirstBurstSizeITNexusTimeOut & NEXUSTO_BITS); + + pDevice->devInfo.sataDeviceInfo.commonDevInfo.it_NexusTimeout = + (bit16)(FirstBurstSizeITNexusTimeOut & NEXUSTO_BITS); + + pDevice->devInfo.sasDeviceInfo.commonDevInfo.firstBurstSize = + (bit16)((FirstBurstSizeITNexusTimeOut >> SHIFT16) & FIRST_BURST); + + pDevice->devInfo.sataDeviceInfo.commonDevInfo.firstBurstSize = + (bit16)((FirstBurstSizeITNexusTimeOut >> SHIFT16) & FIRST_BURST); + + pDevice->devInfo.sasDeviceInfo.commonDevInfo.flag = (bit32)((dTypeSrateSMPTOPortID >> SHIFT4 ) & FLAG_BITS); + + pDevice->devInfo.sataDeviceInfo.commonDevInfo.flag = (bit32)((dTypeSrateSMPTOPortID >> SHIFT4 ) & FLAG_BITS); + + pDevice->devInfo.sasDeviceInfo.commonDevInfo.devType_S_Rate = + (bit8)((dTypeSrateSMPTOPortID >> SHIFT24) & LINK_RATE_BITS); + + pDevice->devInfo.sataDeviceInfo.commonDevInfo.devType_S_Rate = + (bit8)((dTypeSrateSMPTOPortID >> SHIFT24) & LINK_RATE_BITS); + + /* check SAS device then copy SAS Address */ + if ( ((dTypeSrateSMPTOPortID & DEV_TYPE_BITS) >> SHIFT28 == 0x00) || + ((dTypeSrateSMPTOPortID & DEV_TYPE_BITS) >> SHIFT28 == 0x01)) + { + /* copy the sasAddressHi byte-by-byte : no endianness */ + pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressHi[0] = pIomb->sasAddrHi[0]; + pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressHi[1] = pIomb->sasAddrHi[1]; + pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressHi[2] = pIomb->sasAddrHi[2]; + pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressHi[3] = pIomb->sasAddrHi[3]; + + /* copy the sasAddressLow byte-by-byte : no endianness */ + pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressLo[0] = pIomb->sasAddrLow[0]; + pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressLo[1] = pIomb->sasAddrLow[1]; + pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressLo[2] = pIomb->sasAddrLow[2]; + pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressLo[3] = pIomb->sasAddrLow[3]; + } + + /* Display Device Information */ + SA_DBG3(("mpiGetDevInfoRspSpc: smpTimeout= 0x%x\n", pDevice->devInfo.sasDeviceInfo.commonDevInfo.smpTimeout)); + SA_DBG3(("mpiGetDevInfoRspSpc: it_NexusTimeout=0x%x\n", pDevice->devInfo.sasDeviceInfo.commonDevInfo.it_NexusTimeout)); + SA_DBG3(("mpiGetDevInfoRspSpc: firstBurstSize= 0x%x\n", pDevice->devInfo.sasDeviceInfo.commonDevInfo.firstBurstSize)); + SA_DBG3(("mpiGetDevInfoRspSpc: devType_S_Rate= 0x%x\n", pDevice->devInfo.sasDeviceInfo.commonDevInfo.devType_S_Rate)); + + + SA_DBG1(("Device SPC deviceid 0x%08X flag 0x%08X %s WWID= %02x%02x%02x%02x:%02x%02x%02x%02x, %s\n", + deviceid, + pDevice->devInfo.sasDeviceInfo.commonDevInfo.flag, + (pDevice->devInfo.sasDeviceInfo.commonDevInfo.devType_S_Rate & 0xF0) == 0x20 ? "SATA DA" : + (pDevice->devInfo.sasDeviceInfo.commonDevInfo.devType_S_Rate & 0xF0) == 0x10 ? "SSP/SMP" : + (pDevice->devInfo.sasDeviceInfo.commonDevInfo.devType_S_Rate & 0xF0) == 0x0 ? " STP " : "Unknown", + + pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressHi[3], + pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressHi[2], + pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressHi[1], + pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressHi[0], + pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressLo[3], + pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressLo[2], + pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressLo[1], + pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressLo[0], + + (pDevice->devInfo.sasDeviceInfo.commonDevInfo.devType_S_Rate & 0xF) == 8 ? " 1.5G" : + (pDevice->devInfo.sasDeviceInfo.commonDevInfo.devType_S_Rate & 0xF) == 9 ? " 3.0G" : + (pDevice->devInfo.sasDeviceInfo.commonDevInfo.devType_S_Rate & 0xF) == 10 ? " 6.0G" : + (pDevice->devInfo.sasDeviceInfo.commonDevInfo.devType_S_Rate & 0xF) == 11 ? "12.0G" : "????" )); + + ossaGetDeviceInfoCB(agRoot, agContext, agDevHandle, Info_avail, &pDevice->devInfo.sasDeviceInfo.commonDevInfo); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiGetDevInfoRspSpc: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "2t"); + return ret; +} + +/******************************************************************************/ +/*! \brief Set Device Information Response + * + * This routine handles the response of Set Device Info Command Response + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb Pointer of IOMB Message + * + * \return sucess or fail + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiSetDevInfoRsp( + agsaRoot_t *agRoot, + agsaSetDeviceInfoRsp_t *pIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaDevHandle_t *agDevHandle; + agsaDeviceDesc_t *pDevice; + agsaContext_t *agContext; + bit32 tag, status, deviceid, option, param; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2v"); + OSSA_READ_LE_32(AGROOT, &status, pIomb, OSSA_OFFSET_OF(agsaSetDeviceInfoRsp_t, status)); + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaSetDeviceInfoRsp_t, tag)); + /* get TAG */ + SA_DBG3(("mpiSetDevInfoRsp: HTag=0x%x\n", tag)); + + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + SA_DBG1(("mpiSetDevInfoRsp: Bad Response IOMB!!! pRequest is NULL. TAG=0x%x STATUS=0x%x\n", tag, status)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2v"); + return AGSA_RC_FAILURE; + } + + agContext = saRoot->IOMap[tag].agContext; + + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + SA_ASSERT((pRequest->valid), "pRequest->valid"); + /* check status success or failure */ + if (status) + { + /* status is FAILED */ + if (pRequest->completionCB == agNULL) + { + SA_DBG1(("mpiSetDevInfoRsp: status is FAILED pRequest->completionCB == agNULL\n" )); + ossaSetDeviceInfoCB(agRoot, agContext, agNULL, status, 0, 0); + } + else + { + SA_DBG1(("mpiSetDevInfoRsp: status is FAILED use CB\n" )); + (*(ossaSetDeviceInfoCB_t)(pRequest->completionCB))(agRoot, agContext, agNULL, status, 0, 0); + } + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2v"); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + return AGSA_RC_FAILURE; + } + + /* status is SUCCESS */ + OSSA_READ_LE_32(AGROOT, &deviceid, pIomb, OSSA_OFFSET_OF(agsaSetDeviceInfoRsp_t, deviceId)); + OSSA_READ_LE_32(AGROOT, &option, pIomb, OSSA_OFFSET_OF(agsaSetDeviceInfoRsp_t, SA_SR_SI)); + OSSA_READ_LE_32(AGROOT, ¶m, pIomb, OSSA_OFFSET_OF(agsaSetDeviceInfoRsp_t, A_R_ITNT)); + + /* find device handle from device index */ + pDevice = (agsaDeviceDesc_t *)saRoot->DeviceMap[deviceid & DEVICE_ID_BITS].DeviceHandle; + if (pDevice != agNULL) + { + if (pDevice->targetDevHandle.sdkData) + { + agDevHandle = &(pDevice->targetDevHandle); + } + else + { + agDevHandle = &(pDevice->initiatorDevHandle); + } + } + else + { + SA_DBG1(("mpiSetDevInfoRsp: pDevice is NULL")); + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "2v"); + return AGSA_RC_FAILURE; + } + + if (agDevHandle == agNULL) + { + SA_DBG1(("mpiSetDevInfoRsp: warning!!! no deviceHandle is found")); + if (pRequest->completionCB == agNULL) + { + ossaSetDeviceInfoCB(agRoot, agContext, agNULL, OSSA_IO_NO_DEVICE, 0, 0); + } + else + { + (*(ossaSetDeviceInfoCB_t)(pRequest->completionCB))(agRoot, agContext, agNULL, OSSA_IO_NO_DEVICE, 0, 0); + } + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "2v"); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + return AGSA_RC_FAILURE; + } + + SA_DBG2(("mpiSetDevInfoRsp:, option 0x%X param 0x%X\n", option, param)); + + if(smIS_SPCV(agRoot)) + { + SA_DBG2(("mpiSetDevInfoRsp:was option 0x%X param 0x%X\n", option, param)); + SA_DBG2(("mpiSetDevInfoRsp:pDevice->option 0x%X pDevice->param 0x%X\n", pDevice->option, pDevice->param)); + option |= pDevice->option; + param |= pDevice->param; + SA_DBG2(("mpiSetDevInfoRsp:now option 0x%X param 0x%X\n", option, param)); + if (pRequest->completionCB == agNULL) + { + ossaSetDeviceInfoCB(agRoot, agContext, agDevHandle, OSSA_SUCCESS, option, param); + } + else + { + (*(ossaSetDeviceInfoCB_t)(pRequest->completionCB))(agRoot, agContext, agDevHandle, OSSA_SUCCESS, option, param); + } + } + else + { + SA_DBG2(("mpiSetDevInfoRsp:, option 0x%X param 0x%X\n", option, param)); + if (pRequest->completionCB == agNULL) + { + ossaSetDeviceInfoCB(agRoot, agContext, agDevHandle, OSSA_SUCCESS, option, param); + } + else + { + (*(ossaSetDeviceInfoCB_t)(pRequest->completionCB))(agRoot, agContext, agDevHandle, OSSA_SUCCESS, option, param); + } + } + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "2v"); + return ret; +} + +/******************************************************************************/ +/*! \brief SPC MPI SSP Event + * + * This function handles the SAS Event. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb pointer of Message + * + * \return The read value + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiSSPEvent( + agsaRoot_t *agRoot, + agsaSSPEventRsp_t *pIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaPortContext_t *agPortContext; + agsaDevHandle_t *agDevHandle; + agsaDeviceDesc_t *pDevice; + bit32 event,deviceId; + bit32 deviceIdx, tag, portId_tmp; + bit32 SSPTag; + bit16 sspTag; + bit8 portId; + + agsaDifDetails_t Dif_details; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2u"); + + OSSA_READ_LE_32(AGROOT, &event, pIomb, OSSA_OFFSET_OF(agsaSSPEventRsp_t, event)); + OSSA_READ_LE_32(AGROOT, &deviceId, pIomb, OSSA_OFFSET_OF(agsaSSPEventRsp_t, deviceId)); + OSSA_READ_LE_32(AGROOT, &portId_tmp, pIomb, OSSA_OFFSET_OF(agsaSSPEventRsp_t, portId)); + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaSSPEventRsp_t, tag)); + OSSA_READ_LE_32(AGROOT, &SSPTag, pIomb, OSSA_OFFSET_OF(agsaSSPEventRsp_t, SSPTag)); + + + sspTag = (bit16)(SSPTag & SSPTAG_BITS); + + /* get IORequest from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + + SA_ASSERT((pRequest), "pRequest"); + + if(agNULL == pRequest) + { + SA_DBG1(("mpiSSPEvent: agNULL == pRequest event 0x%X\n", event)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2u"); + return AGSA_RC_FAILURE; + } + + /* get port context */ + portId = (bit8)(portId_tmp & PORTID_MASK); + SA_DBG2(("mpiSSPEvent:PortID 0x%x PortStatus 0x%x PortContext %p\n",saRoot->PortMap[portId & PORTID_MASK].PortID,saRoot->PortMap[portId & PORTID_MASK].PortStatus,saRoot->PortMap[portId & PORTID_MASK].PortContext)); + agPortContext = (agsaPortContext_t *)saRoot->PortMap[portId].PortContext; + /* get device Id */ + deviceIdx = deviceId & DEVICE_ID_BITS; + OS_ASSERT(deviceIdx < MAX_IO_DEVICE_ENTRIES, "deviceIdx MAX_IO_DEVICE_ENTRIES"); + /* find device handle from device index */ + pDevice = (agsaDeviceDesc_t *)saRoot->DeviceMap[deviceIdx].DeviceHandle; + + if( agNULL == pDevice ) + { + OS_ASSERT(pDevice, "pDevice"); + agDevHandle = agNULL; + } + else + { + if (pDevice->targetDevHandle.sdkData) + { + agDevHandle = &(pDevice->targetDevHandle); + } + else + { + agDevHandle = &(pDevice->initiatorDevHandle); + } + } + + switch (event) + { + case OSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH: + case OSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH: + case OSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH: + case OSSA_IO_XFR_ERROR_DIF_MISMATCH: + { + + SA_DBG1(("mpiSSPEvent: DIF Event 0x%x HTAG = 0x%x\n", event, tag)); + + OSSA_READ_LE_32(AGROOT, &Dif_details.UpperLBA, pIomb, OSSA_OFFSET_OF(agsaSSPEventRsp_t, EVT_PARAM0_or_LBAH)); + OSSA_READ_LE_32(AGROOT, &Dif_details.LowerLBA, pIomb, OSSA_OFFSET_OF(agsaSSPEventRsp_t, EVT_PARAM1_or_LBAL)); + OSSA_READ_LE_32(AGROOT, &Dif_details.sasAddressHi, pIomb, OSSA_OFFSET_OF(agsaSSPEventRsp_t, SAS_ADDRH)); + OSSA_READ_LE_32(AGROOT, &Dif_details.sasAddressLo, pIomb, OSSA_OFFSET_OF(agsaSSPEventRsp_t, SAS_ADDRL)); + OSSA_READ_LE_32(AGROOT, &Dif_details.ExpectedCRCUDT01, pIomb, OSSA_OFFSET_OF(agsaSSPEventRsp_t, UDT1_E_UDT0_E_CRC_E)); + OSSA_READ_LE_32(AGROOT, &Dif_details.ExpectedUDT2345, pIomb, OSSA_OFFSET_OF(agsaSSPEventRsp_t, UDT5_E_UDT4_E_UDT3_E_UDT2_E)); + OSSA_READ_LE_32(AGROOT, &Dif_details.ActualCRCUDT01, pIomb, OSSA_OFFSET_OF(agsaSSPEventRsp_t, UDT1_A_UDT0_A_CRC_A)); + OSSA_READ_LE_32(AGROOT, &Dif_details.ActualUDT2345, pIomb, OSSA_OFFSET_OF(agsaSSPEventRsp_t, UDT5_A_UDT4_A_UDT3_A_UDT2_A)); + OSSA_READ_LE_32(AGROOT, &Dif_details.DIFErrDevID, pIomb, OSSA_OFFSET_OF(agsaSSPEventRsp_t, HW_DEVID_Reserved_DIF_ERR)); + OSSA_READ_LE_32(AGROOT, &Dif_details.ErrBoffsetEDataLen, pIomb, OSSA_OFFSET_OF(agsaSSPEventRsp_t, EDATA_LEN_ERR_BOFF)); + + SA_DBG2(("mpiSSPEvent: UpperLBA. 0x%08X LowerLBA. 0x%08X\n",Dif_details.UpperLBA, Dif_details.LowerLBA)); + SA_DBG2(("mpiSSPEvent: sasAddressHi. 0x%02X%02X%02X%02X sasAddressLo. 0x%02X%02X%02X%02X\n", + Dif_details.sasAddressHi[0],Dif_details.sasAddressHi[1],Dif_details.sasAddressHi[2],Dif_details.sasAddressHi[3], + Dif_details.sasAddressLo[0],Dif_details.sasAddressLo[1],Dif_details.sasAddressLo[2],Dif_details.sasAddressLo[3])); + SA_DBG2(("mpiSSPEvent: ExpectedCRCUDT01. 0x%08X ExpectedUDT2345. 0x%08X\n",Dif_details.ExpectedCRCUDT01, Dif_details.ExpectedUDT2345)); + SA_DBG2(("mpiSSPEvent: ActualCRCUDT01. 0x%08X ActualUDT2345. 0x%08X\n",Dif_details.ActualCRCUDT01, Dif_details.ActualUDT2345)); + SA_DBG2(("mpiSSPEvent: DIFErrDevID. 0x%08X ErrBoffsetEDataLen. 0x%08X\n",Dif_details.DIFErrDevID, Dif_details.ErrBoffsetEDataLen)); + } + + default: + { + SA_DBG3(("mpiSSPEvent: Non DIF event")); + break; + } + } + + + /* get event */ + switch (event) + { + case OSSA_IO_OVERFLOW: + { + SA_DBG1(("mpiSSPEvent: OSSA_IO_OVERFLOW tag 0x%x ssptag 0x%x\n", tag, sspTag)); + saRoot->IoEventCount.agOSSA_IO_OVERFLOW++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag, 0,agNULL); + break; + } + case OSSA_IO_XFER_ERROR_BREAK: + { + SA_DBG1(("mpiSSPEvent: OSSA_IO_XFER_ERROR_BREAK tag 0x%x ssptag 0x%x\n", tag, sspTag)); + saRoot->IoEventCount.agOSSA_IO_XFER_ERROR_BREAK++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag, 0,agNULL); + break; + } + case OSSA_IO_XFER_ERROR_PHY_NOT_READY: + { + SA_DBG1(("mpiSSPEvent: OSSA_IO_XFER_ERROR_PHY_NOT_READY tag 0x%x ssptag 0x%x\n", tag, sspTag)); + saRoot->IoEventCount.agOSSA_IO_XFER_ERROR_PHY_NOT_READY++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag, 0,agNULL); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: + { + SA_DBG1(("mpiSSPEvent: OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED tag 0x%x ssptag 0x%x\n", tag, sspTag)); + saRoot->IoEventCount.agOSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag, 0,agNULL); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION: + { + SA_DBG1(("mpiSSPEvent: OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION tag 0x%x ssptag 0x%x\n", tag, sspTag)); + saRoot->IoEventCount.agOSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag, 0,agNULL); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_BREAK: + { + SA_DBG1(("mpiSSPEvent: OSSA_IO_OPEN_CNX_ERROR_BREAK tag 0x%x ssptag 0x%x\n", tag, sspTag)); + saRoot->IoEventCount.agOSSA_IO_OPEN_CNX_ERROR_BREAK++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag, 0,agNULL); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: + { + SA_DBG1(("mpiSSPEvent: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS tag 0x%x ssptag 0x%x\n", tag, sspTag)); + saRoot->IoEventCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag, 0,agNULL); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION: + { + SA_DBG1(("mpiSSPEvent: OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION tag 0x%x ssptag 0x%x\n", tag, sspTag)); + saRoot->IoEventCount.agOSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag, 0,agNULL); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: + { + SA_DBG1(("mpiSSPEvent: OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED tag 0x%x ssptag 0x%x\n", tag, sspTag)); + saRoot->IoEventCount.agOSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag, 0,agNULL); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION: + { + SA_DBG1(("mpiSSPEvent: OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION tag 0x%x ssptag 0x%x\n", tag, sspTag)); + saRoot->IoEventCount.agOSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag, 0,agNULL); + break; + } + case OSSA_IO_XFER_ERROR_NAK_RECEIVED: + { + SA_DBG1(("mpiSSPEvent: OSSA_IO_XFER_ERROR_NAK_RECEIVED tag 0x%x ssptag 0x%x\n", tag, sspTag)); + saRoot->IoEventCount.agOSSA_IO_XFER_ERROR_NAK_RECEIVED++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag, 0,agNULL); + break; + } + case OSSA_IO_XFER_ERROR_ACK_NAK_TIMEOUT: + { + SA_DBG1(("mpiSSPEvent: OSSA_IO_XFER_ERROR_ACK_NAK_TIMEOUT tag 0x%x ssptag 0x%x\n", tag, sspTag)); + saRoot->IoEventCount.agOSSA_IO_XFER_ERROR_ACK_NAK_TIMEOUT++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag, 0,agNULL); + break; + } + case OSSA_IO_XFER_ERROR_OFFSET_MISMATCH: + { + SA_DBG1(("mpiSSPEvent: OSSA_IO_XFER_ERROR_OFFSET_MISMATCH tag 0x%x ssptag 0x%x\n", tag, sspTag)); +#ifdef SA_ENABLE_PCI_TRIGGER + if( saRoot->swConfig.PCI_trigger & PCI_TRIGGER_OFFSET_MISMATCH ) + { + siPCITriger(agRoot); + } +#endif /* SA_ENABLE_PCI_TRIGGER */ + saRoot->IoEventCount.agOSSA_IO_XFER_ERROR_OFFSET_MISMATCH++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag, 0,agNULL); + break; + } + case OSSA_IO_XFER_ERROR_XFER_ZERO_DATA_LEN: + { + SA_DBG1(("mpiSSPEvent: OSSA_IO_XFER_ERROR_XFER_ZERO_DATA_LEN tag 0x%x ssptag 0x%x\n", tag, sspTag)); + saRoot->IoEventCount.agOSSA_IO_XFER_ERROR_XFER_ZERO_DATA_LEN++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag, 0,agNULL); + break; + } + case OSSA_IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT: + { + SA_DBG1(("mpiSSPEvent: OSSA_IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT tag 0x%x ssptag 0x%x\n", tag, sspTag)); + saRoot->IoEventCount.agOSSA_IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag, 0,agNULL); + break; + } + case OSSA_IO_XFER_OPEN_RETRY_TIMEOUT: + { + SA_DBG1(("mpiSSPEvent: OSSA_IO_XFER_OPEN_RETRY_TIMEOUT tag 0x%x ssptag 0x%x\n", tag, sspTag)); + saRoot->IoEventCount.agOSSA_IO_XFER_OPEN_RETRY_TIMEOUT++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag, 0,agNULL); + break; + } + case OSSA_IO_XFER_ERROR_XFER_RDY_OVERRUN: + { + SA_DBG1(("mpiSSPEvent: OSSA_IO_XFER_ERROR_XFER_RDY_OVERRUN tag 0x%x ssptag 0x%x\n", tag, sspTag)); + saRoot->IoEventCount.agOSSA_IO_XFER_ERROR_XFER_RDY_OVERRUN++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag, 0,agNULL); + break; + } + case OSSA_IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: + { + SA_DBG1(("mpiSSPEvent: OSSA_IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED tag 0x%x ssptag 0x%x\n", tag, sspTag)); + saRoot->IoEventCount.agOSSA_IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag, 0,agNULL); + break; + } + case OSSA_IO_XFER_CMD_FRAME_ISSUED: + { + SA_DBG1(("mpiSSPEvent: OSSA_IO_XFER_CMD_FRAME_ISSUED tag 0x%x ssptag 0x%x\n", tag, sspTag)); + saRoot->IoEventCount.agOSSA_IO_XFER_CMD_FRAME_ISSUED++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag, 0,agNULL); + break; + } + case OSSA_IO_XFER_ERROR_UNEXPECTED_PHASE: + { + SA_DBG1(("mpiSSPEvent: OSSA_IO_XFER_ERROR_UNEXPECTED_PHASE tag 0x%x ssptag 0x%x\n", tag, sspTag)); + saRoot->IoEventCount.agOSSA_IO_XFER_ERROR_UNEXPECTED_PHASE++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag, 0,agNULL); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: + { + SA_DBG1(("mpiSSPEvent:OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED HTAG = 0x%x sspTag = 0x%x\n", tag, sspTag)); + saRoot->IoEventCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag, 0,agNULL); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: + { + SA_DBG1(("mpiSSPEvent: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO tag 0x%x ssptag 0x%x\n", tag, sspTag)); + saRoot->IoEventCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag, 0,agNULL); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: + { + SA_DBG1(("mpiSSPEvent: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST tag 0x%x ssptag 0x%x\n", tag, sspTag)); + saRoot->IoEventCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag, 0,agNULL); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: + { + SA_DBG1(("mpiSSPEvent: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE tag 0x%x ssptag 0x%x\n", tag, sspTag)); + saRoot->IoEventCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag, 0,agNULL); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: + { + SA_DBG1(("mpiSSPEvent: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED tag 0x%x ssptag 0x%x\n", tag, sspTag)); + saRoot->IoEventCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag, 0,agNULL); + break; + } + case OSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS: + { + SA_DBG1(("mpiSSPEvent: OSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS tag 0x%x ssptag 0x%x\n", tag, sspTag)); + saRoot->IoEventCount.agOSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag, 0,agNULL); + break; + } + case OSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH: + { + SA_DBG1(("mpiSSPEvent: OSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH tag 0x%x ssptag 0x%x\n", tag, sspTag)); + saRoot->IoEventCount.agOSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag, 0,agNULL); + break; + } + case OSSA_IO_XFR_ERROR_INTERNAL_CRC_ERROR: + { + SA_DBG1(("mpiSSPEvent: OSSA_IO_XFR_ERROR_INTERNAL_CRC_ERROR HTAG = 0x%x\n", tag)); + saRoot->IoEventCount.agOSSA_IO_XFR_ERROR_INTERNAL_CRC_ERROR++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag, 0,agNULL); + break; + } + case OSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH: + { + SA_DBG1(("mpiSSPEvent: OSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH tag 0x%x ssptag 0x%x\n", tag, sspTag)); + saRoot->IoEventCount.agOSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag,sizeof(agsaDifDetails_t),&Dif_details); + break; + } + case OSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH: + { + SA_DBG1(("mpiSSPEvent: OSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH tag 0x%x ssptag 0x%x\n", tag, sspTag)); + saRoot->IoEventCount.agOSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag,sizeof(agsaDifDetails_t),&Dif_details); + break; + } + case OSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH: + { + SA_DBG1(("mpiSSPEvent: OSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH tag 0x%x ssptag 0x%x\n", tag, sspTag)); + saRoot->IoEventCount.agOSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag,sizeof(agsaDifDetails_t),&Dif_details); + break; + } + case OSSA_IO_XFR_ERROR_DIF_MISMATCH: + { + SA_DBG1(("mpiSSPEvent: OSSA_IO_XFR_ERROR_DIF_MISMATCH tag 0x%x ssptag 0x%x\n", tag, sspTag)); + saRoot->IoEventCount.agOSSA_IO_XFR_ERROR_DIF_MISMATCH++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag,sizeof(agsaDifDetails_t),&Dif_details); + break; + } + case OSSA_IO_XFER_ERR_EOB_DATA_OVERRUN: + { + SA_DBG1(("mpiSSPEvent: OSSA_IO_XFER_ERR_EOB_DATA_OVERRUN tag 0x%x ssptag 0x%x\n", tag, sspTag)); + saRoot->IoEventCount.agOSSA_IO_XFER_ERR_EOB_DATA_OVERRUN++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag, 0, agNULL); + break; + } + case OSSA_IO_XFER_READ_COMPL_ERR: + { + SA_DBG1(("mpiSSPEvent: OSSA_IO_XFER_READ_COMPL_ERR tag 0x%x ssptag 0x%x\n", tag, sspTag)); + saRoot->IoEventCount.agOSSA_IO_XFER_READ_COMPL_ERR++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag, 0, agNULL); + break; + } + default: + { + SA_DBG1(("mpiSSPEvent: Unknown Event 0x%x tag 0x%x ssptag 0x%x\n", event, tag, sspTag)); + saRoot->IoEventCount.agOSSA_IO_UNKNOWN_ERROR++; + ossaSSPEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, sspTag, 0,agNULL); + break; + } + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2u"); + /* return value */ + return ret; +} + +/******************************************************************************/ +/*! \brief SPC MPI SATA Event + * + * This function handles the SATA Event. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb pointer of Message + * + * \return The read value + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiSATAEvent( + agsaRoot_t *agRoot, + agsaSATAEventRsp_t *pIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest = agNULL; + agsaPortContext_t *agPortContext; + agsaDevHandle_t *agDevHandle; + agsaDeviceDesc_t *pDevice; + bit32 deviceIdx, portId_tmp, event, tag, deviceId; + bit8 portId; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2w"); + + /* get port context */ + OSSA_READ_LE_32(AGROOT, &portId_tmp, pIomb, OSSA_OFFSET_OF(agsaSATAEventRsp_t, portId)); + OSSA_READ_LE_32(AGROOT, &deviceId, pIomb, OSSA_OFFSET_OF(agsaSATAEventRsp_t, deviceId)); + OSSA_READ_LE_32(AGROOT, &event, pIomb, OSSA_OFFSET_OF(agsaSATAEventRsp_t, event)); + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaSATAEventRsp_t, tag)); + + if (OSSA_IO_XFER_ERROR_ABORTED_NCQ_MODE != event) + { + /* get IORequest from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + } + /* get port context - only for OSSA_IO_XFER_ERROR_ABORTED_NCQ_MODE */ + portId = (bit8)(portId_tmp & PORTID_MASK); + SA_DBG2(("mpiSATAEvent:PortID 0x%x PortStatus 0x%x PortContext %p\n",saRoot->PortMap[portId & PORTID_MASK].PortID,saRoot->PortMap[portId & PORTID_MASK].PortStatus,saRoot->PortMap[portId & PORTID_MASK].PortContext)); + agPortContext = (agsaPortContext_t *)saRoot->PortMap[portId].PortContext; + /* get device Id - only for OSSA_IO_XFER_ERROR_ABORTED_NCQ_MODE*/ + deviceIdx = deviceId & DEVICE_ID_BITS; + OS_ASSERT(deviceIdx < MAX_IO_DEVICE_ENTRIES, "deviceIdx MAX_IO_DEVICE_ENTRIES"); + /* find device handle from device index */ + pDevice = (agsaDeviceDesc_t *)saRoot->DeviceMap[deviceIdx].DeviceHandle; + agDevHandle = &(pDevice->targetDevHandle); + + /* get event */ + switch (event) + { + case OSSA_IO_OVERFLOW: + { + SA_DBG1(("mpiSATAEvent: OSSA_IO_OVERFLOW HTAG = 0x%x\n", tag)); + saRoot->IoEventCount.agOSSA_IO_OVERFLOW++; + ossaSATAEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, 0, agNULL); + break; + } + case OSSA_IO_XFER_ERROR_BREAK: + { + SA_DBG1(("mpiSATAEvent: OSSA_IO_XFER_ERROR_BREAK HTAG = 0x%x\n", tag)); + saRoot->IoEventCount.agOSSA_IO_XFER_ERROR_BREAK++; + ossaSATAEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, 0, agNULL); + break; + } + case OSSA_IO_XFER_ERROR_PHY_NOT_READY: + { + SA_DBG1(("mpiSATAEvent: OSSA_IO_XFER_ERROR_PHY_NOT_READY HTAG = 0x%x\n", tag)); + saRoot->IoEventCount.agOSSA_IO_XFER_ERROR_PHY_NOT_READY++; + ossaSATAEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, 0, agNULL); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: + { + SA_DBG1(("mpiSATAEvent: OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED HTAG = 0x%x\n", tag)); + saRoot->IoEventCount.agOSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED++; + ossaSATAEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, 0, agNULL); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION: + { + SA_DBG1(("mpiSATAEvent: OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION HTAG = 0x%x\n", tag)); + saRoot->IoEventCount.agOSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION++; + ossaSATAEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, 0, agNULL); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_BREAK: + { + SA_DBG1(("mpiSATAEvent: OSSA_IO_OPEN_CNX_ERROR_BREAK HTAG = 0x%x\n", tag)); + saRoot->IoEventCount.agOSSA_IO_OPEN_CNX_ERROR_BREAK++; + ossaSATAEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, 0, agNULL); + break; + } + + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: + { + SA_DBG1(("mpiSATAEvent: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST HTAG = 0x%x\n", tag)); + saRoot->IoEventCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST++; + ossaSATAEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, 0, agNULL); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: + { + SA_DBG1(("mpiSATAEvent: HTAG = 0x%x\n", tag)); + saRoot->IoEventCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE++; + ossaSATAEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, 0, agNULL); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: + { + SA_DBG1(("mpiSATAEvent:OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED HTAG = 0x%x\n", tag)); + saRoot->IoEventCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED++; + ossaSATAEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, 0, agNULL); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: + { + SA_DBG1(("mpiSATAEvent: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS HTAG = 0x%x\n", tag)); + saRoot->IoEventCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS++; + ossaSATAEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, 0, agNULL); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION: + { + SA_DBG1(("mpiSATAEvent: OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION HTAG = 0x%x\n", tag)); + saRoot->IoEventCount.agOSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION++; + ossaSATAEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, 0, agNULL); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: + { + SA_DBG1(("mpiSATAEvent: OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED HTAG = 0x%x\n", tag)); + saRoot->IoEventCount.agOSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED++; + ossaSATAEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, 0, agNULL); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION: + { + SA_DBG1(("mpiSATAEvent: OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION HTAG = 0x%x\n", tag)); + saRoot->IoEventCount.agOSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION++; + ossaSATAEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, 0, agNULL); + break; + } + case OSSA_IO_XFER_ERROR_NAK_RECEIVED: + { + SA_DBG1(("mpiSATAEvent: OSSA_IO_XFER_ERROR_NAK_RECEIVED HTAG = 0x%x\n", tag)); + saRoot->IoEventCount.agOSSA_IO_XFER_ERROR_NAK_RECEIVED++; + ossaSATAEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, 0, agNULL); + break; + } + case OSSA_IO_XFER_ERROR_ABORTED_NCQ_MODE: + { + SA_DBG1(("mpiSATAEvent: OSSA_IO_XFER_ERROR_ABORTED_NCQ_MODE HTAG = 0x%x\n", tag)); + saRoot->IoEventCount.agOSSA_IO_XFER_ERROR_ABORTED_NCQ_MODE++; + ossaSATAEvent(agRoot, agNULL, agPortContext, agDevHandle, event, 0, agNULL); + break; + } + case OSSA_IO_XFER_ERROR_OFFSET_MISMATCH: + { + SA_DBG1(("mpiSATAEvent: OSSA_IO_XFER_ERROR_OFFSET_MISMATCH HTAG = 0x%x\n", tag)); + saRoot->IoEventCount.agOSSA_IO_XFER_ERROR_OFFSET_MISMATCH++; + ossaSATAEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, 0, agNULL); + break; + } + case OSSA_IO_XFER_ERROR_XFER_ZERO_DATA_LEN: + { + SA_DBG1(("mpiSATAEvent: OSSA_IO_XFER_ERROR_XFER_ZERO_DATA_LEN HTAG = 0x%x\n", tag)); + saRoot->IoEventCount.agOSSA_IO_XFER_ERROR_XFER_ZERO_DATA_LEN++; + ossaSATAEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, 0, agNULL); + break; + } + case OSSA_IO_XFER_OPEN_RETRY_TIMEOUT: + { + SA_DBG1(("mpiSATAEvent: OSSA_IO_XFER_OPEN_RETRY_TIMEOUT HTAG = 0x%x\n", tag)); + saRoot->IoEventCount.agOSSA_IO_XFER_OPEN_RETRY_TIMEOUT++; + ossaSATAEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, 0, agNULL); + break; + } + case OSSA_IO_XFER_ERROR_PEER_ABORTED: + { + SA_DBG1(("mpiSATAEvent: OSSA_IO_XFER_ERROR_PEER_ABORTED HTAG = 0x%x\n", tag)); + saRoot->IoEventCount.agOSSA_IO_XFER_ERROR_PEER_ABORTED++; + ossaSATAEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, 0, agNULL); + break; + } + case OSSA_IO_XFER_CMD_FRAME_ISSUED: + { + SA_DBG1(("mpiSATAEvent: OSSA_IO_XFER_CMD_FRAME_ISSUED HTAG = 0x%x\n", tag)); + saRoot->IoEventCount.agOSSA_IO_XFER_CMD_FRAME_ISSUED++; + ossaSATAEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, 0, agNULL); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: + { + SA_DBG1(("mpiSATAEvent, OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY HTAG = 0x%x\n", tag)); + saRoot->IoEventCount.agOSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY++; + ossaSATAEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, 0, agNULL); + break; + } + case OSSA_IO_XFER_ERROR_UNEXPECTED_PHASE: + { + SA_DBG1(("mpiSATAEvent, OSSA_IO_XFER_ERROR_UNEXPECTED_PHASE HTAG = 0x%x\n", tag)); + saRoot->IoEventCount.agOSSA_IO_XFER_ERROR_UNEXPECTED_PHASE++; + ossaSATAEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, 0, agNULL); + break; + } + case OSSA_IO_XFER_ERROR_XFER_RDY_OVERRUN: + { + SA_DBG1(("mpiSATAEvent, OSSA_IO_XFER_ERROR_XFER_RDY_OVERRUN HTAG = 0x%x\n", tag)); + saRoot->IoEventCount.agOSSA_IO_XFER_ERROR_XFER_RDY_OVERRUN++; + ossaSATAEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, 0, agNULL); + break; + } + case OSSA_IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: + { + SA_DBG1(("mpiSATAEvent, OSSA_IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED HTAG = 0x%x\n", tag)); + saRoot->IoEventCount.agOSSA_IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED++; + ossaSATAEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, 0, agNULL); + break; + } + case OSSA_IO_XFER_PIO_SETUP_ERROR: + { + SA_DBG1(("mpiSATAEvent: OSSA_IO_XFER_PIO_SETUP_ERROR HTAG = 0x%x\n", tag)); + saRoot->IoEventCount.agOSSA_IO_XFER_PIO_SETUP_ERROR++; + ossaSATAEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, 0, agNULL); + break; + } + case OSSA_IO_XFR_ERROR_DIF_MISMATCH: + { + SA_DBG1(("mpiSATAEvent: OSSA_IO_XFR_ERROR_DIF_MISMATCH HTAG = 0x%x\n", tag)); + saRoot->IoEventCount.agOSSA_IO_XFR_ERROR_DIF_MISMATCH++; + ossaSATAEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, 0, agNULL); + break; + } + case OSSA_IO_XFR_ERROR_INTERNAL_CRC_ERROR: + { + SA_DBG1(("mpiSATAEvent: OSSA_IO_XFR_ERROR_INTERNAL_CRC_ERROR HTAG = 0x%x\n", tag)); + saRoot->IoEventCount.agOSSA_IO_XFR_ERROR_INTERNAL_CRC_ERROR++; + ossaSATAEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, 0, agNULL); + break; + } + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: + { + SA_DBG1(("mpiSATAEvent: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED HTAG = 0x%x\n", tag)); + saRoot->IoEventCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED++; + ossaSATAEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, 0, agNULL); + break; + } + case OSSA_IO_XFER_ERR_EOB_DATA_OVERRUN: + { + SA_DBG1(("mpiSATAEvent: OSSA_IO_XFER_ERR_EOB_DATA_OVERRUN HTAG = 0x%x\n", tag)); + saRoot->IoEventCount.agOSSA_IO_XFER_ERR_EOB_DATA_OVERRUN++; + ossaSATAEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, 0, agNULL); + break; + } + case OSSA_IO_XFER_ERROR_DMA_ACTIVATE_TIMEOUT: + { + SA_DBG1(("mpiSATAEvent: OSSA_IO_XFER_ERROR_DMA_ACTIVATE_TIMEOUT HTAG = 0x%x\n", tag)); + saRoot->IoEventCount.agOSSA_IO_XFER_ERROR_DMA_ACTIVATE_TIMEOUT++; + ossaSATAEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, 0, agNULL); + break; + } + default: + { + SA_DBG1(("mpiSATAEvent: Unknown Event 0x%x HTAG = 0x%x\n", event, tag)); + saRoot->IoEventCount.agOSSA_IO_UNKNOWN_ERROR++; + ossaSATAEvent(agRoot, pRequest->pIORequestContext, agPortContext, agDevHandle, event, 0, agNULL); + break; + } + } + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2w"); + return ret; +} + +/******************************************************************************/ +/*! \brief Set NVM Data Response + * + * This routine handles the response of SET NVM Data Response + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb Pointer of IOMB Mesage + * + * \return sucess or fail + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiSetNVMDataRsp( + agsaRoot_t *agRoot, + agsaSetNVMDataRsp_t *pIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaContext_t *agContext; + bit32 tag, status, iPTdaBnDpsAsNvm; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2x"); + + SA_DBG1(("mpiSetNVMDataRsp: HTag=0x%x\n", pIomb->tag)); + + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaSetNVMDataRsp_t, tag)); + OSSA_READ_LE_32(AGROOT, &iPTdaBnDpsAsNvm, pIomb, OSSA_OFFSET_OF(agsaSetNVMDataRsp_t, iPTdaBnDpsAsNvm)); + OSSA_READ_LE_32(AGROOT, &status, pIomb, OSSA_OFFSET_OF(agsaSetNVMDataRsp_t, status)); + + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + SA_DBG1(("mpiSetNVMDataRsp: Bad Response IOMB!!! pRequest is NULL. TAG=0x%x STATUS=0x%x\n", tag, status)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2x"); + return AGSA_RC_FAILURE; + } + + agContext = saRoot->IOMap[tag].agContext; + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + SA_ASSERT((pRequest->valid), "pRequest->valid"); + + if (((iPTdaBnDpsAsNvm & NVMD_TYPE) == AGSA_NVMD_CONFIG_SEEPROM) || + ((iPTdaBnDpsAsNvm & NVMD_TYPE) == AGSA_NVMD_VPD_FLASH) || + ((iPTdaBnDpsAsNvm & NVMD_TYPE) == AGSA_NVMD_TWI_DEVICES)) + { + /* CB for VPD for SEEPROM-0, VPD_FLASH and TWI */ + ossaSetNVMDResponseCB(agRoot, agContext, (status & NVMD_STAT)); + } + else + { + /* should not happend */ + SA_DBG1(("mpiSetNVMDataRsp: NVMD is wrong. TAG=0x%x STATUS=0x%x\n", tag, (iPTdaBnDpsAsNvm & NVMD_TYPE))); + ret = AGSA_RC_FAILURE; + } + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2x"); + return ret; +} + +/******************************************************************************/ +/*! \brief SPC MPI SSP ABORT Response + * + * This function handles the SSP Abort Response. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb pointer of Message + * + * \return The read value + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiSSPAbortRsp( + agsaRoot_t *agRoot, + agsaSSPAbortRsp_t *pIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaDeviceDesc_t *pDevice; + bit32 tag, status, scope; + smTraceFuncEnter(hpDBG_VERY_LOUD,"2y"); + + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaSSPAbortRsp_t, tag)); + OSSA_READ_LE_32(AGROOT, &status, pIomb, OSSA_OFFSET_OF(agsaSSPAbortRsp_t, status)); + OSSA_READ_LE_32(AGROOT, &scope, pIomb, OSSA_OFFSET_OF(agsaSSPAbortRsp_t, scp)); + scope &= 3; + /* get IORequest from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + + if (agNULL == pRequest) + { + /* remove the SSP_ABORT or SATA_ABORT request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + SA_ASSERT((pRequest), "pRequest"); + SA_DBG1(("mpiSSPAbortRsp: the request is NULL. Tag=%x\n", tag)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2y"); + return AGSA_RC_FAILURE; + } + + + if ( agTRUE == pRequest->valid ) + { + pDevice = pRequest->pDevice; + SA_ASSERT((pRequest->pDevice), "pRequest->pDevice"); + + SA_DBG3(("mpiSSPAbortRsp: request abort is valid Htag 0x%x\n", tag)); + /* remove the SSP_ABORT or SATA_ABORT request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + + if( pRequest->completionCB == agNULL ) + { + ossaSSPAbortCB(agRoot, pRequest->pIORequestContext, scope, status); + } + else + { + (*(ossaGenericAbortCB_t)(pRequest->completionCB))(agRoot, pRequest->pIORequestContext, scope, status); + } + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* Delete the request from the pendingIORequests */ + saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiSSPAbortRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + + if(scope) + { + siCountActiveIORequestsOnDevice( agRoot, pDevice->DeviceMapIndex ); + } + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + } + else + { + ret = AGSA_RC_FAILURE; + SA_DBG1(("mpiSSPAbortRsp: the request is not valid any more. Tag=%x\n", pRequest->HTag)); + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2y"); + return ret; +} + +/******************************************************************************/ +/*! \brief SPC MPI SATA ABORT Response + * + * This function handles the SATA Event. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb pointer of Message + * + * \return The read value + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiSATAAbortRsp( + agsaRoot_t *agRoot, + agsaSATAAbortRsp_t *pIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaDeviceDesc_t *pDevice; + bit32 tag, status, scope; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"3B"); + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaSATAAbortRsp_t, tag)); + OSSA_READ_LE_32(AGROOT, &status, pIomb, OSSA_OFFSET_OF(agsaSATAAbortRsp_t, status)); + OSSA_READ_LE_32(AGROOT, &scope, pIomb, OSSA_OFFSET_OF(agsaSATAAbortRsp_t, scp)); + + /* get IORequest from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + + if (agNULL == pRequest) + { + /* remove the SSP_ABORT or SATA_ABORT request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + SA_DBG1(("mpiSATAAbortRsp: the request is NULL. Tag=%x\n", tag)); + SA_ASSERT((pRequest), "pRequest"); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "3B"); + return AGSA_RC_FAILURE; + } + + if ( agTRUE == pRequest->valid ) + { + pDevice = pRequest->pDevice; + SA_ASSERT((pRequest->pDevice), "pRequest->pDevice"); + + SA_DBG3(("mpiSATAAbortRsp: request abort is valid Htag 0x%x\n", tag)); + + if( pRequest->completionCB == agNULL ) + { + ossaSATAAbortCB(agRoot, pRequest->pIORequestContext, scope, status); + } + else + { + (*(ossaGenericAbortCB_t)(pRequest->completionCB))(agRoot, pRequest->pIORequestContext, scope, status); + } + /* remove the SATA_ABORT request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* Delete the request from the pendingIORequests */ + saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + } + else + { + ret = AGSA_RC_FAILURE; + SA_DBG1(("mpiSATAAbortRsp: the request is not valid any more. Tag=%x\n", pRequest->HTag)); + } + + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "3B"); + return ret; +} + +/******************************************************************************/ +/*! \brief Set GPIO Response + * + * This routine handles the response of GPIO Command + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb Pointer of IOMB Mesage + * + * \return sucess or fail + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiGPIORsp( + agsaRoot_t *agRoot, + agsaGPIORsp_t *pIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaContext_t *agContext; + agsaIORequestDesc_t *pRequest; + agsaGpioPinSetupInfo_t pinSetupInfo; + agsaGpioEventSetupInfo_t eventSetupInfo; + bit32 GpioIe, OT11_0, OT19_12, GPIEVChange, GPIEVFall, GPIEVRise, GpioRdVal, tag; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"5C"); + + SA_DBG3(("mpiGPIORsp: HTag=0x%x\n", pIomb->tag)); + + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaGPIORsp_t, tag)); + + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + SA_DBG1(("mpiGPIORsp: Bad Response IOMB!!! pRequest is NULL. TAG=0x%x\n", tag)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5C"); + return AGSA_RC_FAILURE; + } + + agContext = saRoot->IOMap[tag].agContext; + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + SA_ASSERT((pRequest->valid), "pRequest->valid"); + + /* set payload to zeros */ + si_memset(&pinSetupInfo, 0, sizeof(agsaGpioPinSetupInfo_t)); + si_memset(&eventSetupInfo, 0, sizeof(agsaGpioEventSetupInfo_t)); + + OSSA_READ_LE_32(AGROOT, &GpioIe, pIomb, OSSA_OFFSET_OF(agsaGPIORsp_t, GpioIe)); + OSSA_READ_LE_32(AGROOT, &OT11_0, pIomb, OSSA_OFFSET_OF(agsaGPIORsp_t, OT11_0)); + OSSA_READ_LE_32(AGROOT, &OT19_12, pIomb, OSSA_OFFSET_OF(agsaGPIORsp_t, OT19_12)); + OSSA_READ_LE_32(AGROOT, &GPIEVChange, pIomb, OSSA_OFFSET_OF(agsaGPIORsp_t, GPIEVChange)); + OSSA_READ_LE_32(AGROOT, &GPIEVFall, pIomb, OSSA_OFFSET_OF(agsaGPIORsp_t, GPIEVFall)); + OSSA_READ_LE_32(AGROOT, &GPIEVRise, pIomb, OSSA_OFFSET_OF(agsaGPIORsp_t, GPIEVRise)); + OSSA_READ_LE_32(AGROOT, &GpioRdVal, pIomb, OSSA_OFFSET_OF(agsaGPIORsp_t, GpioRdVal)); + pinSetupInfo.gpioInputEnabled = GpioIe; + pinSetupInfo.gpioTypePart1 = OT11_0; + pinSetupInfo.gpioTypePart2 = OT19_12; + eventSetupInfo.gpioEventLevel = GPIEVChange; + eventSetupInfo.gpioEventFallingEdge = GPIEVFall; + eventSetupInfo.gpioEventRisingEdge = GPIEVRise; + + ossaGpioResponseCB(agRoot, agContext, OSSA_IO_SUCCESS, GpioRdVal, + &pinSetupInfo, + &eventSetupInfo); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiGPIORsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5C"); + return ret; +} + +/******************************************************************************/ +/*! \brief Set GPIO Event Response + * + * This routine handles the response of GPIO Event + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb Pointer of IOMB Mesage + * + * \return sucess or fail + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiGPIOEventRsp( + agsaRoot_t *agRoot, + agsaGPIOEvent_t *pIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + bit32 GpioEvent; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"3D"); + + OSSA_READ_LE_32(AGROOT, &GpioEvent, pIomb, OSSA_OFFSET_OF(agsaGPIOEvent_t, GpioEvent)); + + ossaGpioEvent(agRoot, GpioEvent); + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "3D"); + return ret; +} + +/******************************************************************************/ +/*! \brief SAS Diagnostic Start/End Response + * + * This routine handles the response of SAS Diagnostic Start/End Command + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb Pointer of IOMB Mesage + * + * \return sucess or fail + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiSASDiagStartEndRsp( + agsaRoot_t *agRoot, + agsaSASDiagStartEndRsp_t *pIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaContext_t *agContext; + bit32 tag, Status; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2F"); + + SA_DBG3(("mpiSASDiagStartEndRsp: HTAG=0x%x\n", pIomb->tag)); + + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaSASDiagStartEndRsp_t, tag)); + OSSA_READ_LE_32(AGROOT, &Status, pIomb, OSSA_OFFSET_OF(agsaSASDiagStartEndRsp_t, Status)); + + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + SA_DBG1(("mpiSASDiagStartEndRsp: Bad Response IOMB!!! pRequest is NULL. TAG=0x%x STATUS=0x%x\n", tag, Status)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2F"); + return AGSA_RC_FAILURE; + } + + agContext = saRoot->IOMap[tag].agContext; + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + SA_ASSERT((pRequest->valid), "pRequest->valid"); + + switch(Status) + { + + case OSSA_DIAG_SE_SUCCESS: + SA_DBG3(("mpiSASDiagStartEndRsp: Status OSSA_DIAG_SE_SUCCESS 0x%X \n", Status)); + break; + case OSSA_DIAG_SE_INVALID_PHY_ID: + SA_DBG1(("mpiSASDiagStartEndRsp: Status OSSA_DIAG_SE_INVALID_PHY_ID 0x%X \n", Status)); + break; + case OSSA_DIAG_PHY_NOT_DISABLED: + SA_DBG1(("mpiSASDiagStartEndRsp: Status OSSA_DIAG_PHY_NOT_DISABLED Status 0x%X \n", Status)); + break; + case OSSA_DIAG_OTHER_FAILURE: + if(smIS_SPCV(agRoot)) + { + SA_DBG1(("mpiSASDiagStartEndRsp: Status OSSA_DIAG_OTHER_FAILURE Status 0x%X \n", Status)); + } + else + { + SA_DBG1(("mpiSASDiagStartEndRsp: Status OSSA_DIAG_OPCODE_INVALID Status 0x%X \n", Status)); + } + break; + default: + SA_DBG1(("mpiSASDiagStartEndRsp:Status UNKNOWN 0x%X \n", Status)); + break; + } + + ossaSASDiagStartEndCB(agRoot, agContext, Status); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiSASDiagStartEndRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2F"); + return ret; +} + +/******************************************************************************/ +/*! \brief SAS Diagnostic Execute Response + * + * This routine handles the response of SAS Diagnostic Execute Command + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb Pointer of IOMB Mesage + * + * \return sucess or fail + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiSASDiagExecuteRsp( + agsaRoot_t *agRoot, + agsaSASDiagExecuteRsp_t *pIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaContext_t *agContext; + bit32 tag, Status, CmdTypeDescPhyId, ReportData; + smTraceFuncEnter(hpDBG_VERY_LOUD,"3G"); + + SA_DBG3(("mpiSASDiagExecuteRsp: HTAG=0x%x\n", pIomb->tag)); + + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaSASDiagExecuteRsp_t, tag)); + OSSA_READ_LE_32(AGROOT, &Status, pIomb, OSSA_OFFSET_OF(agsaSASDiagExecuteRsp_t, Status)); + OSSA_READ_LE_32(AGROOT, &CmdTypeDescPhyId, pIomb, OSSA_OFFSET_OF(agsaSASDiagExecuteRsp_t, CmdTypeDescPhyId)); + OSSA_READ_LE_32(AGROOT, &ReportData, pIomb, OSSA_OFFSET_OF(agsaSASDiagExecuteRsp_t, ReportData)); + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + SA_DBG1(("mpiSASDiagExecuteRsp: Bad Response IOMB!!! pRequest is NULL.TAG=0x%x STATUS=0x%x\n", tag, Status)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "3G"); + return AGSA_RC_FAILURE; + } + + switch(Status) + { + + case OSSA_DIAG_SUCCESS: + SA_DBG3(("mpiSASDiagExecuteRsp: Status OSSA_DIAG_SUCCESS 0x%X \n", Status)); + break; + case OSSA_DIAG_INVALID_COMMAND: + if(smIS_SPCV(agRoot)) + { + SA_DBG1(("mpiSASDiagExecuteRsp: Status OSSA_DIAG_INVALID_COMMAND Status 0x%X \n", Status)); + } + else + { + SA_DBG1(("mpiSASDiagExecuteRsp: Status OSSA_DIAG_FAIL Status 0x%X \n", Status)); + } + break; + case OSSA_REGISTER_ACCESS_TIMEOUT: + SA_DBG1(("mpiSASDiagExecuteRsp: Status OSSA_REGISTER_ACCESS_TIMEOUT Status 0x%X \n", Status)); + break; + case OSSA_DIAG_NOT_IN_DIAGNOSTIC_MODE: + SA_DBG1(("mpiSASDiagExecuteRsp: Status OSSA_DIAG_NOT_IN_DIAGNOSTIC_MODE Status 0x%X \n", Status)); + break; + case OSSA_DIAG_INVALID_PHY: + SA_DBG1(("mpiSASDiagExecuteRsp: Status OSSA_DIAG_INVALID_PHY Status 0x%X \n", Status)); + break; + case OSSA_MEMORY_ALLOC_FAILURE: + SA_DBG1(("mpiSASDiagExecuteRsp: Status Status 0x%X \n", Status)); + break; + + default: + SA_DBG1(("mpiSASDiagExecuteRsp:Status UNKNOWN 0x%X \n", Status)); + break; + } + + + agContext = saRoot->IOMap[tag].agContext; + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + SA_ASSERT((pRequest->valid), "pRequest->valid"); + + ossaSASDiagExecuteCB(agRoot, agContext, Status, CmdTypeDescPhyId, ReportData); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiSASDiagExecuteRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "3G"); + + /* return value */ + return ret; +} + +/******************************************************************************/ +/*! \brief SAS General Event Notification Response + * + * This routine handles the response of Inbound IOMB Command with error case + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb Pointer of IOMB Mesage + * + * \return sucess or fail + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiGeneralEventRsp( + agsaRoot_t *agRoot, + agsaGeneralEventRsp_t *pIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + bit32 i; + bit32 status; + bit32 tag; + agsaIORequestDesc_t *pRequest; + agsaDeviceDesc_t *pDevice; + agsaContext_t *agContext = NULL; + agsaGeneralEventRsp_t GenEventData; + agsaHWEventEncrypt_t agEvent; + bit16 OpCode = 0; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"3H"); + + si_memset(&GenEventData,0,sizeof(agsaGeneralEventRsp_t)); + + OSSA_READ_LE_32(AGROOT, &status, pIomb, OSSA_OFFSET_OF(agsaGeneralEventRsp_t, status)); + + SA_DBG3(("mpiGeneralEventRsp: %p\n", pIomb)); + + SA_DBG1(("mpiGeneralEventRsp: OpCode 0x%X status 0x%x\n",pIomb->inbIOMBpayload[0] & OPCODE_BITS, status)); + + for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++) + { + OSSA_READ_LE_32(AGROOT, &GenEventData.inbIOMBpayload[i], pIomb, OSSA_OFFSET_OF(agsaGeneralEventRsp_t,inbIOMBpayload[i] )); + } + SA_DBG1(("mpiGeneralEventRsp: inbIOMBpayload 0x%08x 0x%08x 0x%08x 0x%08x\n", + GenEventData.inbIOMBpayload[0],GenEventData.inbIOMBpayload[1], + GenEventData.inbIOMBpayload[2],GenEventData.inbIOMBpayload[3] )); + SA_DBG1(("mpiGeneralEventRsp: inbIOMBpayload 0x%08x 0x%08x 0x%08x 0x%08x\n", + GenEventData.inbIOMBpayload[4],GenEventData.inbIOMBpayload[8], + GenEventData.inbIOMBpayload[6],GenEventData.inbIOMBpayload[7] )); + + switch (status) /*status */ + { + + case GEN_EVENT_IOMB_V_BIT_NOT_SET: + SA_DBG1(("mpiGeneralEventRsp: GEN_EVENT_IOMB_V_BIT_NOT_SET\n" )); + break; + case GEN_EVENT_INBOUND_IOMB_OPC_NOT_SUPPORTED: + SA_DBG1(("mpiGeneralEventRsp: GEN_EVENT_INBOUND_IOMB_OPC_NOT_SUPPORTED\n" )); + break; + case GEN_EVENT_IOMB_INVALID_OBID: + SA_DBG1(("mpiGeneralEventRsp: GEN_EVENT_IOMB_INVALID_OBID\n" )); + break; + case GEN_EVENT_DS_IN_NON_OPERATIONAL: + SA_DBG1(("mpiGeneralEventRsp: GEN_EVENT_DS_IN_NON_OPERATIONAL\n" )); + break; + case GEN_EVENT_DS_IN_RECOVERY: + SA_DBG1(("mpiGeneralEventRsp: GEN_EVENT_DS_IN_RECOVERY\n" )); + break; + case GEN_EVENT_DS_INVALID: + SA_DBG1(("mpiGeneralEventRsp: GEN_EVENT_DS_INVALID\n" )); + break; + case GEN_EVENT_IO_XFER_READ_COMPL_ERR: + SA_DBG1(("mpiGeneralEventRsp: GEN_EVENT_IO_XFER_READ_COMPL_ERR 0x%x 0x%x 0x%x\n", + GenEventData.inbIOMBpayload[0], + GenEventData.inbIOMBpayload[1], + GenEventData.inbIOMBpayload[1] )); + ossaGeneralEvent(agRoot, status, agContext, GenEventData.inbIOMBpayload); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "3H"); + return(ret); + default: + SA_DBG1(("mpiGeneralEventRsp: Unknown General Event status!!! 0x%x\n", status)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "3H"); + return AGSA_RC_FAILURE; + } + + OpCode = (bit16)(GenEventData.inbIOMBpayload[0] & OPCODE_BITS); + tag = GenEventData.inbIOMBpayload[1]; + SA_DBG1(("mpiGeneralEventRsp:OpCode 0x%X [0] 0x%08x\n" ,OpCode,(bit16)(GenEventData.inbIOMBpayload[0] & OPCODE_BITS))); + + switch (OpCode) /* OpCode */ + { + case OPC_INB_DEV_HANDLE_ACCEPT: + case OPC_INB_ECHO: + case OPC_INB_FW_FLASH_UPDATE: + case OPC_INB_GET_NVMD_DATA: + case OPC_INB_SET_NVMD_DATA: + case OPC_INB_DEREG_DEV_HANDLE: + case OPC_INB_SPC_GET_DEV_INFO: + case OPC_INB_GET_DEV_HANDLE: + case OPC_INB_SPC_REG_DEV: + case OPC_INB_SAS_DIAG_EXECUTE: + case OPC_INB_SAS_DIAG_MODE_START_END: + case OPC_INB_PHYSTART: + case OPC_INB_PHYSTOP: + case OPC_INB_LOCAL_PHY_CONTROL: + case OPC_INB_GPIO: + case OPC_INB_GET_TIME_STAMP: + case OPC_INB_PORT_CONTROL: + case OPC_INB_SET_DEVICE_STATE: + case OPC_INB_GET_DEVICE_STATE: + case OPC_INB_SET_DEV_INFO: +// case OPC_INB_PCIE_DIAG_EXECUTE: + case OPC_INB_SAS_HW_EVENT_ACK: + case OPC_INB_SAS_RE_INITIALIZE: + case OPC_INB_KEK_MANAGEMENT: + case OPC_INB_SET_OPERATOR: + case OPC_INB_GET_OPERATOR: +// case OPC_INB_SGPIO: + +#ifdef SPC_ENABLE_PROFILE + case OPC_INB_FW_PROFILE: +#endif + /* Uses the tag table, so we have to free it up */ + + SA_ASSERT((tag < AGSA_MAX_VALID_PORTS * saRoot->swConfig.maxActiveIOs), + "OPC_OUB_GENERAL_EVENT tag out of range"); + SA_ASSERT((saRoot->IOMap[ tag < (AGSA_MAX_VALID_PORTS * saRoot->swConfig.maxActiveIOs) ? tag : 0 ].Tag != MARK_OFF), + "OPC_OUB_GENERAL_EVENT tag not in use 1"); + +#if defined(SALLSDK_DEBUG) + if (tag > AGSA_MAX_VALID_PORTS * saRoot->swConfig.maxActiveIOs) + { + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "3H"); + return AGSA_RC_FAILURE; + } +#endif /* SALLSDK_DEBUG */ + + SA_DBG1(("mpiGeneralEventRsp:OpCode found 0x%x htag 0x%x\n",OpCode, tag)); + /* get agContext */ + agContext = saRoot->IOMap[tag].agContext; + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if(pRequest) + { + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_ASSERT((pRequest->valid), "pRequest->valid"); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiGeneralEventRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + } + else + { + SA_DBG1(("mpiGeneralEventRsp:pRequest (%p) NULL\n", pRequest)); + ret = AGSA_RC_FAILURE; + } + break; + /* ???? */ + case OPC_INB_SATA_HOST_OPSTART: + case OPC_INB_SATA_ABORT: + case OPC_INB_SSPINIIOSTART: + case OPC_INB_SSPINITMSTART: + case OPC_INB_SSPINIEXTIOSTART: + case OPC_INB_SSPTGTIOSTART: + case OPC_INB_SSPTGTRSPSTART: + case OPC_INB_SSP_DIF_ENC_OPSTART: + case OPC_INB_SATA_DIF_ENC_OPSTART: + + case OPC_INB_SSP_ABORT: + case OPC_INB_SMP_REQUEST: + case OPC_INB_SMP_ABORT: + { + /* Uses the tag table, so we have to free it up */ + SA_DBG1(("mpiGeneralEventRsp:OpCode found 0x%x htag 0x%x\n",OpCode, tag)); + + tag = GenEventData.inbIOMBpayload[1]; + + SA_ASSERT((tag < AGSA_MAX_VALID_PORTS * saRoot->swConfig.maxActiveIOs), + "OPC_OUB_GENERAL_EVENT tag out of range"); + SA_ASSERT((saRoot->IOMap[ tag < (AGSA_MAX_VALID_PORTS * saRoot->swConfig.maxActiveIOs) ? tag : 0 ].Tag != MARK_OFF), + "OPC_OUB_GENERAL_EVENT tag not in use 2"); +#if defined(SALLSDK_DEBUG) + if (tag > AGSA_MAX_VALID_PORTS * saRoot->swConfig.maxActiveIOs) + { + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "3H"); + return AGSA_RC_FAILURE; + } +#endif + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if(pRequest) + { + pDevice = pRequest->pDevice; + /* return the request to free pool */ + /* get IORequestContext */ + agContext = (agsaContext_t *)pRequest->pIORequestContext; + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_ASSERT((pRequest->valid), "pRequest->valid"); + pRequest->valid = agFALSE; + saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiGeneralEventRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + break; + } + else + { + SA_DBG1(("mpiGeneralEventRsp:pRequest (%p) NULL\n", pRequest)); + ret = AGSA_RC_FAILURE; + } + } + default: + { + SA_DBG1(("mpiGeneralEventRsp:OpCode Not found 0x%x htag 0x%x\n",OpCode, tag)); + ret = AGSA_RC_FAILURE; + + /* Uses the tag table, so we have to free it up */ + tag = GenEventData.inbIOMBpayload[1]; + + SA_ASSERT((tag < AGSA_MAX_VALID_PORTS * saRoot->swConfig.maxActiveIOs), + "OPC_OUB_GENERAL_EVENT tag out of range"); + SA_ASSERT((saRoot->IOMap[ tag < (AGSA_MAX_VALID_PORTS * saRoot->swConfig.maxActiveIOs) ? tag : 0 ].Tag != MARK_OFF), + "OPC_OUB_GENERAL_EVENT tag not in use 3"); + +#if defined(SALLSDK_DEBUG) + if (tag > AGSA_MAX_VALID_PORTS * saRoot->swConfig.maxActiveIOs) + { + smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "3H"); + return AGSA_RC_FAILURE; + } +#endif + /* get agContext */ + agContext = saRoot->IOMap[tag].agContext; + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if (pRequest == agNULL) + { + smTraceFuncExit(hpDBG_VERY_LOUD, 'f', "3H"); + return AGSA_RC_FAILURE; + } + + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_ASSERT((pRequest->valid), "pRequest->valid"); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiGeneralEventRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + break; + } + ret = AGSA_RC_FAILURE; + + } + + switch (OpCode) /* OpCode */ + { + + case OPC_INB_KEK_MANAGEMENT: + { + bit32 flags = GenEventData.inbIOMBpayload[2]; + + SA_DBG1(("mpiGeneralEventRsp: OPC_INB_KEK_MANAGEMENT 0x%x htag 0x%x flags 0x%x\n",OpCode, tag, flags)); + if (flags & 0xFF00) /* update and store*/ + { + agEvent.encryptOperation = OSSA_HW_ENCRYPT_KEK_UPDATE_AND_STORE; + SA_DBG1(("mpiGeneralEventRsp: OSSA_HW_ENCRYPT_KEK_UPDATE_AND_STORE\n")); + } + else /* update */ + { + agEvent.encryptOperation = OSSA_HW_ENCRYPT_KEK_UPDATE; + SA_DBG1(("mpiGeneralEventRsp: OSSA_HW_ENCRYPT_KEK_UPDATE\n")); + } + agEvent.status = OSSA_INVALID_ENCRYPTION_SECURITY_MODE; + si_memset(&agEvent, 0, sizeof(agsaHWEventEncrypt_t)); + agEvent.status = status; + + SA_DBG1(("mpiGeneralEventRsp: ossaHwCB OSSA_HW_EVENT_ENCRYPTION\n" )); + ossaHwCB(agRoot, NULL, OSSA_HW_EVENT_ENCRYPTION, 0, (void*)&agEvent, agContext); + break; + } + case OPC_INB_OPR_MGMT: + si_memset(&agEvent, 0, sizeof(agsaHWEventEncrypt_t)); + agEvent.status = status; + agEvent.encryptOperation = OSSA_HW_ENCRYPT_OPERATOR_MANAGEMENT; + + SA_DBG1(("mpiGeneralEventRsp: OSSA_HW_ENCRYPT_OPERATOR_MANAGEMENT\n" )); + ossaOperatorManagementCB(agRoot, agContext, status, 0); + break; + case OPC_INB_SET_OPERATOR: + SA_DBG1(("mpiGeneralEventRsp: OSSA_HW_ENCRYPT_SET_OPERATOR\n" )); + ossaSetOperatorCB(agRoot,agContext,0xFF,0xFF ); + break; + case OPC_INB_GET_OPERATOR: + SA_DBG1(("mpiGeneralEventRsp: OSSA_HW_ENCRYPT_GET_OPERATOR\n" )); + ossaGetOperatorCB(agRoot,agContext,0xFF,0xFF,0xFF,0xFF,agNULL ); + break; + case OPC_INB_ENC_TEST_EXECUTE: + si_memset(&agEvent, 0, sizeof(agsaHWEventEncrypt_t)); + agEvent.status = status; + agEvent.encryptOperation = OSSA_HW_ENCRYPT_TEST_EXECUTE; + + SA_DBG1(("mpiGeneralEventRsp: OSSA_HW_ENCRYPT_TEST_EXECUTE\n" )); + ossaHwCB(agRoot, NULL, OSSA_HW_EVENT_ENCRYPTION, 0, (void*)&agEvent, agContext); + break; + default: + SA_DBG1(("mpiGeneralEventRsp: MGMNT OpCode Not found 0x%x\n",OpCode )); + ossaGeneralEvent(agRoot, status, agContext, GenEventData.inbIOMBpayload); + break; + } + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'g', "3H"); + return ret; +} + +/******************************************************************************/ +/*! \brief SPC MPI SSP Request Received Event (target mode) + * + * This function handles the SSP Request Received Event. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pMsg1 pointer of Message + * + * \return The read value + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiSSPReqReceivedNotify( + agsaRoot_t *agRoot, + agsaSSPReqReceivedNotify_t *pMsg1) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaDeviceDesc_t *pDevice; + bit32 deviceid, iniTagSSPIul, frameTypeHssa, TlrHdsa; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"3J"); + /* convert endiness if necassary */ + OSSA_READ_LE_32(AGROOT, &deviceid, pMsg1, OSSA_OFFSET_OF(agsaSSPReqReceivedNotify_t, deviceId)); + OSSA_READ_LE_32(AGROOT, &iniTagSSPIul, pMsg1, OSSA_OFFSET_OF(agsaSSPReqReceivedNotify_t, iniTagSSPIul)); + OSSA_READ_LE_32(AGROOT, &frameTypeHssa, pMsg1, OSSA_OFFSET_OF(agsaSSPReqReceivedNotify_t, frameTypeHssa)); + OSSA_READ_LE_32(AGROOT, &TlrHdsa, pMsg1, OSSA_OFFSET_OF(agsaSSPReqReceivedNotify_t, TlrHdsa)); + /* deviceId -> agDeviceHandle */ + pDevice = (agsaDeviceDesc_t *)saRoot->DeviceMap[deviceid & DEVICE_ID_BITS].DeviceHandle; + + if (agNULL == pDevice) + { + SA_DBG1(("mpiSSPReqReceivedNotify: warning!!! no deviceHandle is found")); + } + else + { + /* type punning only safe through char *. See gcc -fstrict_aliasing. */ + char * safe_type_pun = (char *)&(pMsg1->SSPIu[0]); + if( pDevice->initiatorDevHandle.sdkData != agNULL) + { + ossaSSPReqReceived(agRoot, &(pDevice->initiatorDevHandle), + (agsaFrameHandle_t *)safe_type_pun, + (bit16)((iniTagSSPIul >> SHIFT16) & INITTAG_BITS), + ((frameTypeHssa >> SHIFT24) & FRAME_TYPE) | + ((TlrHdsa >> SHIFT16) & TLR_BITS), + (iniTagSSPIul & SSPIUL_BITS)); + }else if( pDevice->targetDevHandle.sdkData != agNULL) + { + ossaSSPReqReceived(agRoot, &(pDevice->targetDevHandle), + (agsaFrameHandle_t *)safe_type_pun, + (bit16)((iniTagSSPIul >> SHIFT16) & INITTAG_BITS), + ((frameTypeHssa >> SHIFT24) & FRAME_TYPE) | + ((TlrHdsa >> SHIFT16) & TLR_BITS), + (iniTagSSPIul & SSPIUL_BITS)); + }else + { + SA_ASSERT(0, "Device handle sdkData not set"); + } + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "3J"); + return ret; +} + +/******************************************************************************/ +/*! \brief SPC MPI Device Handle Arrived Event (target mode) + * + * This function handles the Device Handle Arrived Event. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pMsg1 pointer of Message + * + * \return The read value + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiDeviceHandleArrived( + agsaRoot_t *agRoot, + agsaDeviceHandleArrivedNotify_t *pMsg1) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaDeviceDesc_t *pDevice; + agsaPort_t *pPort; + agsaSASDeviceInfo_t pDeviceInfo; + agsaPortContext_t *agPortContext; + agsaSASIdentify_t remoteIdentify; + bit32 CTag; + bit32 FwdDeviceId; + bit32 ProtConrPortId; + bit32 portId; + bit32 conRate; + bit8 i, protocol, dTypeSRate; + bit32 HostAssignedId; + + if(saRoot == agNULL) + { + SA_ASSERT((saRoot != agNULL), "saRoot"); + return AGSA_RC_FAILURE; + } + + smTraceFuncEnter(hpDBG_VERY_LOUD,"3L"); + /* convert endiness if necassary */ + OSSA_READ_LE_32(AGROOT, &CTag, pMsg1, OSSA_OFFSET_OF(agsaDeviceHandleArrivedNotify_t, CTag)); + OSSA_READ_LE_32(AGROOT, &FwdDeviceId, pMsg1, OSSA_OFFSET_OF(agsaDeviceHandleArrivedNotify_t, HostAssignedIdFwdDeviceId)); + OSSA_READ_LE_32(AGROOT, &ProtConrPortId, pMsg1, OSSA_OFFSET_OF(agsaDeviceHandleArrivedNotify_t, ProtConrPortId)); + + + if(smIS_SPCV(agRoot)) + { + portId = ProtConrPortId & PortId_V_MASK; + conRate = (ProtConrPortId & Conrate_V_MASK ) >> Conrate_V_SHIFT; + + HostAssignedId = (FwdDeviceId & 0xFFFF0000) >> SHIFT16; + if(HostAssignedId) + { + SA_DBG1(("mpiDeviceHandleArrived: HostAssignedId 0x%X\n",HostAssignedId)); + } + } + else + { + portId = ProtConrPortId & PortId_SPC_MASK; + conRate = (ProtConrPortId & Conrate_SPC_MASK ) >> Conrate_SPC_SHIFT; + } + protocol =(bit8)((ProtConrPortId & PROTOCOL_BITS ) >> PROTOCOL_SHIFT); + + SA_DBG1(("mpiDeviceHandleArrived: New Port portID %d deviceid 0x%X conRate 0x%X protocol 0x%X\n",portId, FwdDeviceId,conRate,protocol)); + + /* Port Map */ + agPortContext = saRoot->PortMap[portId].PortContext; + if (agNULL == agPortContext) + { + ossaSingleThreadedEnter(agRoot, LL_PORT_LOCK); + /* new port */ + /* Acquire port list lock */ + /* Allocate a free port */ + pPort = (agsaPort_t *) saLlistGetHead(&(saRoot->freePorts)); + if (agNULL != pPort) + { + saLlistRemove(&(saRoot->freePorts), &(pPort->linkNode)); + + /* setup the port data structure */ + pPort->portContext.osData = agNULL; + pPort->portContext.sdkData = pPort; + pPort->tobedeleted = agFALSE; + /* Add to valid port list */ + saLlistAdd(&(saRoot->validPorts), &(pPort->linkNode)); + /* Release port list lock */ + ossaSingleThreadedLeave(agRoot, LL_PORT_LOCK); + + /* Setup portMap based on portId */ + saRoot->PortMap[portId].PortID = portId; + saRoot->PortMap[portId].PortContext = &(pPort->portContext); + saRoot->PortMap[portId].PortStatus &= ~PORT_INVALIDATING; + pPort->portId = portId; + + pPort->status &= ~PORT_INVALIDATING; + SA_DBG3(("mpiDeviceHandleArrived: ~PORT_INVALIDATING New Port portID %d PortContext %p\n",saRoot->PortMap[pPort->portId].PortID , &pPort->portContext)); + } + else + { + ossaSingleThreadedLeave(agRoot, LL_PORT_LOCK); + SA_DBG2(("mpiDeviceHandleArrived:Port NULL\n")); + /* pPort is agNULL*/ + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "3L"); + return AGSA_RC_FAILURE; + } + } + else + { + /* exist port */ + pPort = (agsaPort_t *) (agPortContext->sdkData); + pPort->status &= ~PORT_INVALIDATING; + pPort->portId =portId; + saRoot->PortMap[pPort->portId].PortStatus &= ~PORT_INVALIDATING; + + SA_DBG1(("mpiDeviceHandleArrived: ~PORT_INVALIDATING Old port portID %d PortContext %p\n", portId, &pPort->portContext)); + + } + /* build Device Information structure */ + si_memset(&pDeviceInfo, 0, sizeof(agsaSASDeviceInfo_t)); + if (ProtConrPortId & PROTOCOL_BITS) + { + protocol = SA_IDFRM_SSP_BIT; /* SSP */ + pDeviceInfo.commonDevInfo.devType_S_Rate = (bit8)(conRate | 0x10); + + } + else + { + protocol = SA_IDFRM_SMP_BIT; /* SMP */ + pDeviceInfo.commonDevInfo.devType_S_Rate = (bit8)conRate; + } + pDeviceInfo.initiator_ssp_stp_smp = protocol; + pDeviceInfo.numOfPhys = 1; + pDeviceInfo.commonDevInfo.sasAddressHi[0] = pMsg1->sasAddrHi[0]; + pDeviceInfo.commonDevInfo.sasAddressHi[1] = pMsg1->sasAddrHi[1]; + pDeviceInfo.commonDevInfo.sasAddressHi[2] = pMsg1->sasAddrHi[2]; + pDeviceInfo.commonDevInfo.sasAddressHi[3] = pMsg1->sasAddrHi[3]; + pDeviceInfo.commonDevInfo.sasAddressLo[0] = pMsg1->sasAddrLow[0]; + pDeviceInfo.commonDevInfo.sasAddressLo[1] = pMsg1->sasAddrLow[1]; + pDeviceInfo.commonDevInfo.sasAddressLo[2] = pMsg1->sasAddrLow[2]; + pDeviceInfo.commonDevInfo.sasAddressLo[3] = pMsg1->sasAddrLow[3]; + pDeviceInfo.commonDevInfo.flag = 0; + pDeviceInfo.commonDevInfo.it_NexusTimeout = ITL_TO_DEFAULT; + + /* deviceId -> agDeviceHandle */ + pDevice = (agsaDeviceDesc_t *)saRoot->DeviceMap[FwdDeviceId & DEVICE_ID_BITS].DeviceHandle; + + if (agNULL == pDevice) + { + /* new device */ + si_memset(&remoteIdentify, 0, sizeof(agsaSASIdentify_t)); + for (i=0;i<4;i++) + { + remoteIdentify.sasAddressHi[i] = pMsg1->sasAddrHi[i]; + remoteIdentify.sasAddressLo[i] = pMsg1->sasAddrLow[i]; + } + remoteIdentify.deviceType_addressFrameType = (bit8)(pDeviceInfo.commonDevInfo.devType_S_Rate & 0xC0); + dTypeSRate = pDeviceInfo.commonDevInfo.devType_S_Rate; + /* get Device from free Device List */ + pDevice = siPortSASDeviceAdd(agRoot, pPort, remoteIdentify, agTRUE, SMP_TO_DEFAULT, ITL_TO_DEFAULT, 0, dTypeSRate, 0); + if (agNULL == pDevice) + { + SA_DBG1(("mpiDeviceHandleArrived: Device Handle is NULL, Out of Resources Error.\n")); + } + else + { + bit32 AccStatus = 0; + bit32 SaveId = FwdDeviceId & 0xFFFF; + /* mapping the device handle and device id */ + saRoot->DeviceMap[FwdDeviceId & DEVICE_ID_BITS].DeviceIdFromFW = FwdDeviceId; + saRoot->DeviceMap[FwdDeviceId & DEVICE_ID_BITS].DeviceHandle = (void *)pDevice; + pDevice->DeviceMapIndex = FwdDeviceId; + SA_DBG2(("mpiDeviceHandleArrived: New deviceID 0x%x Device Context %p DeviceTypeSRate 0x%x\n", FwdDeviceId, pDevice, dTypeSRate)); + + /* Call Back */ + AccStatus = ossaDeviceHandleAccept(agRoot, &(pDevice->initiatorDevHandle), &pDeviceInfo, agPortContext,&FwdDeviceId ); + + HostAssignedId = (FwdDeviceId & 0xFFFF0000) >> SHIFT16; + if(HostAssignedId) + { + if( SaveId == (FwdDeviceId & 0xFFFF) ) + { + + saRoot->DeviceMap[FwdDeviceId & DEVICE_ID_BITS].DeviceIdFromFW = FwdDeviceId; + pDevice->DeviceMapIndex = FwdDeviceId; + + SA_DBG1(("mpiDeviceHandleArrived:FwdDeviceId 0x%x HostAssignedId 0x%x\n",FwdDeviceId,HostAssignedId)); + } + else + { + SA_DBG1(("mpiDeviceHandleArrived:Id mangled expect 0x%x Got 0x%x\n",SaveId, (FwdDeviceId & 0xFFFF))); + ret = AGSA_RC_FAILURE; + } + } + + /* get AWT flag and ITLN_TMO value */ + + if(AccStatus == OSSA_RC_ACCEPT ) + { + /* build DEVICE_HANDLE_ACCEPT IOMB and send to SPC with action=accept */ + mpiDevHandleAcceptCmd(agRoot, agNULL, CTag, FwdDeviceId, 0, pDeviceInfo.commonDevInfo.flag, pDeviceInfo.commonDevInfo.it_NexusTimeout, 0); + } + else + { + mpiDevHandleAcceptCmd(agRoot, agNULL, CTag, FwdDeviceId, 1, pDeviceInfo.commonDevInfo.flag, pDeviceInfo.commonDevInfo.it_NexusTimeout, 0); + } + } + } + + SA_DBG1(("mpiDeviceHandleArrived Device 0x%08X flag 0x%08X %s WWID= %02x%02x%02x%02x:%02x%02x%02x%02x, %s\n", + FwdDeviceId, + pDevice->devInfo.sasDeviceInfo.commonDevInfo.flag, + (pDevice->devInfo.sasDeviceInfo.commonDevInfo.devType_S_Rate & 0xF0) == 0x20 ? "SATA DA" : + (pDevice->devInfo.sasDeviceInfo.commonDevInfo.devType_S_Rate & 0xF0) == 0x10 ? "SSP/SMP" : + (pDevice->devInfo.sasDeviceInfo.commonDevInfo.devType_S_Rate & 0xF0) == 0x0 ? " STP " : "Unknown", + + pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressHi[3], + pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressHi[2], + pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressHi[1], + pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressHi[0], + pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressLo[3], + pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressLo[2], + pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressLo[1], + pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressLo[0], + + (pDevice->devInfo.sasDeviceInfo.commonDevInfo.devType_S_Rate & 0xF) == 8 ? " 1.5G" : + (pDevice->devInfo.sasDeviceInfo.commonDevInfo.devType_S_Rate & 0xF) == 9 ? " 3.0G" : + (pDevice->devInfo.sasDeviceInfo.commonDevInfo.devType_S_Rate & 0xF) == 10 ? " 6.0G" : + (pDevice->devInfo.sasDeviceInfo.commonDevInfo.devType_S_Rate & 0xF) == 11 ? "12.0G" : "????" )); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "3L"); + return ret; +} + +/******************************************************************************/ +/*! \brief Get Time Stamp Response + * + * This routine handles the response of Get Time Stamp Command + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb Pointer of IOMB Mesage + * + * \return sucess or fail + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiGetTimeStampRsp( + agsaRoot_t *agRoot, + agsaGetTimeStampRsp_t *pIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaContext_t *agContext; + bit32 tag, timeStampLower, timeStampUpper; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"3M"); + + SA_DBG3(("mpiGetTimeStampRsp: HTAG=0x%x\n", pIomb->tag)); + + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaGetTimeStampRsp_t, tag)); + OSSA_READ_LE_32(AGROOT, &timeStampLower, pIomb, OSSA_OFFSET_OF(agsaGetTimeStampRsp_t, timeStampLower)); + OSSA_READ_LE_32(AGROOT, &timeStampUpper, pIomb, OSSA_OFFSET_OF(agsaGetTimeStampRsp_t, timeStampUpper)); + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + SA_DBG1(("mpiGetTimeStampRsp: Bad Response IOMB!!! pRequest is NULL.TAG=0x%x\n", tag)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "3M"); + return AGSA_RC_FAILURE; + } + + agContext = saRoot->IOMap[tag].agContext; + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + SA_ASSERT((pRequest->valid), "pRequest->valid"); + + SA_DBG3(("mpiGetTimeStampRsp: timeStampLower 0x%x timeStampUpper 0x%x\n", timeStampLower, timeStampUpper)); + + ossaGetTimeStampCB(agRoot, agContext, timeStampLower, timeStampUpper); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiGetTimeStampRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "3M"); + return ret; +} + +/******************************************************************************/ +/*! \brief SAS HW Event Ack Response + * + * This routine handles the response of SAS HW Event Ack Command + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb Pointer of IOMB Mesage + * + * \return sucess or fail + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiSASHwEventAckRsp( + agsaRoot_t *agRoot, + agsaSASHwEventAckRsp_t *pIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaContext_t *agContext; + agsaPort_t *pPort; + bit32 tag, status; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2N"); + + SA_DBG2(("mpiSASHwEventAckRsp: Htag=0x%x %p\n", pIomb->tag,pIomb)); + + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaSASHwEventAckRsp_t, tag)); + OSSA_READ_LE_32(AGROOT, &status, pIomb, OSSA_OFFSET_OF(agsaSASHwEventAckRsp_t, status)); + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + SA_DBG1(("mpiSASHwEventAckRsp: Bad Response IOMB!!! pRequest is NULL.TAG=0x%x Status=0x%x\n", tag, status)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2N"); + return AGSA_RC_FAILURE; + } + + agContext = saRoot->IOMap[tag].agContext; + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + SA_ASSERT((pRequest->valid), "pRequest->valid"); + + SA_DBG1(("mpiSASHwEventAckRsp: status 0x%x Htag=0x%x HwAckType=0x%x\n",status,pIomb->tag,pRequest->HwAckType )); + + ossaHwEventAckCB(agRoot, agContext, status); + + pPort = pRequest->pPort; + if (agNULL != pPort) + { + SA_DBG1(("mpiSASHwEventAckRsp: pPort %p tobedeleted %d\n", pPort, pPort->tobedeleted)); + if (pPort->status & PORT_INVALIDATING && pPort->tobedeleted ) + { + SA_DBG1(("mpiSASHwEventAckRsp: PORT_INVALIDATING portInvalid portID %d pPort %p, nulling out PortContext\n", pPort->portId, pPort)); + /* invalid the port */ + siPortInvalid(agRoot, pPort); + /* map out the portmap */ + saRoot->PortMap[pPort->portId].PortContext = agNULL; + saRoot->PortMap[pPort->portId].PortID = PORT_MARK_OFF; + saRoot->PortMap[pPort->portId].PortStatus |= PORT_INVALIDATING; + } + else + { + SA_DBG1(("mpiSASHwEventAckRsp:pPort->status 0x%x Htag=0x%x %p\n",pPort->status, pIomb->tag,pIomb)); + } + } + else + { + SA_DBG1(("mpiSASHwEventAckRsp: pPort is NULL, no portId, HTag=0x%x\n", tag)); + } + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiSASHwEventAckRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2N"); + return ret; +} + +/******************************************************************************/ +/*! \brief Port Control Response + * + * This routine handles the response of SAS HW Event Ack Command + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb Pointer of IOMB Mesage + * + * \return sucess or fail + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiPortControlRsp( + agsaRoot_t *agRoot, + agsaPortControlRsp_t *pIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest = agNULL; + agsaContext_t *agContext = agNULL; + agsaPortContext_t *agPortContext = agNULL; + bit32 tag; + bit32 port =0; + bit32 operation =0; + bit32 status =0; + bit32 portState =0; + bit32 portOperation =0; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"3O"); + + SA_DBG2(("mpiPortControlRsp: HTag=0x%x\n", pIomb->tag)); + + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaPortControlRsp_t, tag)); + OSSA_READ_LE_32(AGROOT, &operation, pIomb, OSSA_OFFSET_OF(agsaPortControlRsp_t, portOPPortId)); + OSSA_READ_LE_32(AGROOT, &status, pIomb, OSSA_OFFSET_OF(agsaPortControlRsp_t, status)); + OSSA_READ_LE_32(AGROOT, &portState, pIomb, OSSA_OFFSET_OF(agsaPortControlRsp_t,rsvdPortState )); + + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + SA_DBG1(("mpiPortControlRsp: Bad Response IOMB!!! pRequest is NULL.TAG=0x%x Status=0x%x\n", tag, status)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "3O"); + return AGSA_RC_FAILURE; + } + + agContext = saRoot->IOMap[tag].agContext; + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + SA_ASSERT((pRequest->valid), "pRequest->valid"); + + if(!pRequest->valid) + { + SA_DBG1(("mpiPortControlRsp: pRequest->valid %d not set\n", pRequest->valid)); + } + + SA_DBG2(("mpiPortControlRsp: pRequest->completionCB %p\n", pRequest->completionCB)); + + port = operation & PORTID_MASK; + + if(port < AGSA_MAX_VALID_PORTS ) + { + SA_DBG2(("mpiPortControlRsp: PortID 0x%x PortStatus 0x%x PortContext %p\n", + saRoot->PortMap[port].PortID, + saRoot->PortMap[port].PortStatus, + saRoot->PortMap[port].PortContext)); + + agPortContext = (agsaPortContext_t *)saRoot->PortMap[port].PortContext; + } + SA_DBG2(("mpiPortControlRsp: PortID 0x%x PortStatus 0x%x PortContext %p\n",saRoot->PortMap[operation & PORTID_MASK].PortID,saRoot->PortMap[operation & PORTID_MASK].PortStatus,saRoot->PortMap[operation & PORTID_MASK].PortContext)); + agPortContext = (agsaPortContext_t *)saRoot->PortMap[operation & PORTID_MASK].PortContext; + SA_DBG1(("mpiPortControlRsp: agPortContext %p\n",agPortContext )); + + + SA_DBG2(("mpiPortControlRsp: portID 0x%x status 0x%x\n", (operation & PORTID_MASK), status)); + + SA_DBG1(("mpiPortControlRsp: portID 0x%x status 0x%x agPortContext %p\n",port, status,agPortContext)); + + portOperation = (((operation & LOCAL_PHY_OP_BITS) >> SHIFT8) | (portState << SHIFT28) ); + + SA_DBG1(("mpiPortControlRsp: portState 0x%x operation 0x%x portOperation 0x%x\n",portState, operation,portOperation )); + + switch(portOperation) + { + case AGSA_PORT_SET_SMP_PHY_WIDTH: + SA_DBG1(("mpiPortControlRsp: AGSA_PORT_SET_SMP_PHY_WIDTH operation 0x%x\n",operation )); + break; + case AGSA_PORT_SET_PORT_RECOVERY_TIME: + SA_DBG1(("mpiPortControlRsp: AGSA_PORT_SET_PORT_RECOVERY_TIME operation 0x%x\n",operation )); + break; + case AGSA_PORT_IO_ABORT: + SA_DBG1(("mpiPortControlRsp: AGSA_PORT_IO_ABORT operation 0x%x\n",operation )); + break; + case AGSA_PORT_SET_PORT_RESET_TIME: + SA_DBG1(("mpiPortControlRsp: AGSA_PORT_SET_PORT_RESET_TIME operation 0x%x\n",operation )); + break; + case AGSA_PORT_HARD_RESET: + SA_DBG1(("mpiPortControlRsp: AGSA_PORT_HARD_RESET operation 0x%x\n",operation )); + break; + case AGSA_PORT_CLEAN_UP: + SA_DBG1(("mpiPortControlRsp: AGSA_PORT_CLEAN_UP operation 0x%x\n",operation )); + break; + case AGSA_STOP_PORT_RECOVERY_TIMER: + SA_DBG1(("mpiPortControlRsp: AGSA_STOP_PORT_RECOVERY_TIMER operation 0x%x\n",operation )); + break; + default: + { + SA_DBG1(("mpiPortControlRsp: Unknown operation 0x%x\n",operation )); + } + } + + ossaPortControlCB(agRoot, agContext, agPortContext, portOperation, status); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiPortControlRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "3O"); + /* return value */ + return ret; +} + +/******************************************************************************/ +/*! \brief SPC MPI SMP ABORT Response + * + * This function handles the SMP Abort Response. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb pointer of Message + * + * \return The read value + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiSMPAbortRsp( + agsaRoot_t *agRoot, + agsaSMPAbortRsp_t *pIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaDeviceDesc_t *pDevice; + bit32 tag, scp, status; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"3P"); + + SA_DBG3(("mpiSMPAbortRsp: HTag=0x%x Status=0x%x\n", pIomb->tag, pIomb->status)); + + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaSMPAbortRsp_t, tag)); + OSSA_READ_LE_32(AGROOT, &status, pIomb, OSSA_OFFSET_OF(agsaSMPAbortRsp_t, status)); + OSSA_READ_LE_32(AGROOT, &scp, pIomb, OSSA_OFFSET_OF(agsaSMPAbortRsp_t, scp)); + + /* get IORequest from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + + if (agNULL == pRequest) + { + SA_DBG1(("mpiSMPAbortRsp: pRequest is NULL, HTag=0x%x Status=0x%x\n", pIomb->tag, pIomb->status)); + SA_ASSERT((pRequest), "pRequest"); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "3P"); + return AGSA_RC_FAILURE; + } + + if ( agTRUE == pRequest->valid ) + { + pDevice = pRequest->pDevice; + SA_ASSERT((pRequest->pDevice), "pRequest->pDevice"); + + SA_DBG3(("mpiSMPAbortRsp: request abort is valid Htag 0x%x\n", tag)); + + /* remove the SSP_ABORT or SATA_ABORT request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + if( pRequest->completionCB == agNULL ) + { + SA_DBG1(("mpiSMPAbortRsp: ************************************************* Valid for Expander only tag 0x%x\n", tag)); + ossaSMPAbortCB(agRoot, pRequest->pIORequestContext, scp, status); + } + else + { + (*(ossaGenericAbortCB_t)(pRequest->completionCB))(agRoot, pRequest->pIORequestContext, scp, status); + } + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* Delete the request from the pendingIORequests */ + saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiSMPAbortRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + } + else + { + ret = AGSA_RC_FAILURE; + SA_DBG1(("mpiSMPAbortRsp: the request is not valid any more. Tag=%x\n", pRequest->HTag)); + } + + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "3P"); + + return ret; +} + +/******************************************************************************/ +/*! \brief SPC MPI Device Handle Arrived Event (target mode) + * + * This function handles the Device Handle Arrived Event. + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pMsg1 pointer of Message + * + * \return The read value + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiDeviceHandleRemoval( + agsaRoot_t *agRoot, + agsaDeviceHandleRemoval_t *pMsg1) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaDeviceDesc_t *pDevice; + agsaPortContext_t *agPortContext; + bit32 portId; + bit32 deviceid, deviceIdx; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"3R"); + + /* convert endiness if necassary */ + OSSA_READ_LE_32(AGROOT, &portId, pMsg1, OSSA_OFFSET_OF(agsaDeviceHandleRemoval_t, portId)); + OSSA_READ_LE_32(AGROOT, &deviceid, pMsg1, OSSA_OFFSET_OF(agsaDeviceHandleRemoval_t, deviceId)); + + SA_DBG3(("mpiDeviceHandleRemoval: portId=0x%x deviceId=0x%x\n", portId, deviceid)); + + pDevice = saRoot->DeviceMap[deviceid & DEVICE_ID_BITS].DeviceHandle; + SA_DBG2(("mpiDeviceHandleRemoval:PortID 0x%x PortStatus 0x%x PortContext %p\n", + saRoot->PortMap[portId & PORTID_MASK].PortID, + saRoot->PortMap[portId & PORTID_MASK].PortStatus, + saRoot->PortMap[portId & PORTID_MASK].PortContext)); + agPortContext = (agsaPortContext_t *)saRoot->PortMap[portId & PORTID_MASK].PortContext; + + /* Call Back */ + SA_DBG1(("mpiDeviceHandleRemoval: portId=0x%x deviceId=0x%x autoDeregDeviceflag=0x%x\n", portId, deviceid,saRoot->autoDeregDeviceflag[portId & PORTID_MASK])); + if (pDevice->targetDevHandle.sdkData) + { + ossaDeviceHandleRemovedEvent(agRoot, &(pDevice->targetDevHandle), agPortContext); + + if (saRoot->autoDeregDeviceflag[portId & PORTID_MASK]) + { + /* remove the DeviceMap and MapIndex */ + deviceIdx = pDevice->DeviceMapIndex & DEVICE_ID_BITS; + SA_DBG1(("mpiDeviceHandleRemoval: A Freed portId=0x%x deviceId=0x%x\n", portId, deviceid)); + OS_ASSERT(deviceIdx < MAX_IO_DEVICE_ENTRIES, "deviceIdx MAX_IO_DEVICE_ENTRIES"); + + saRoot->DeviceMap[deviceIdx].DeviceIdFromFW = 0; + saRoot->DeviceMap[deviceIdx].DeviceHandle = agNULL; + pDevice->DeviceMapIndex = 0; + + /* Reset the device data structure */ + pDevice->pPort = agNULL; + pDevice->targetDevHandle.sdkData = agNULL; + pDevice->targetDevHandle.osData = agNULL; + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + saLlistAdd(&(saRoot->freeDevicesList), &(pDevice->linkNode)); + SA_DBG1(("mpiDeviceHandleRemoval: portId=0x%x deviceId=0x%x\n", portId, deviceid)); + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + } + } + else + { + if (pDevice->initiatorDevHandle.sdkData) + { + ossaDeviceHandleRemovedEvent(agRoot, &(pDevice->initiatorDevHandle), agPortContext); + + if (saRoot->autoDeregDeviceflag[portId & PORTID_MASK]) + { + /* remove the DeviceMap and MapIndex */ + deviceIdx = pDevice->DeviceMapIndex & DEVICE_ID_BITS; + SA_DBG1(("mpiDeviceHandleRemoval: A Freed portId=0x%x deviceId=0x%x\n", portId, deviceid)); + OS_ASSERT(deviceIdx < MAX_IO_DEVICE_ENTRIES, "deviceIdx MAX_IO_DEVICE_ENTRIES"); + saRoot->DeviceMap[deviceIdx].DeviceIdFromFW = 0; + saRoot->DeviceMap[deviceIdx].DeviceHandle = agNULL; + pDevice->DeviceMapIndex = 0; + + /* Reset the device data structure */ + pDevice->pPort = agNULL; + pDevice->initiatorDevHandle.sdkData = agNULL; + pDevice->initiatorDevHandle.osData = agNULL; + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + saLlistAdd(&(saRoot->freeDevicesList), &(pDevice->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + } + } + else + { + /* no callback because bad device_id */ + SA_DBG1(("mpiDeviceHandleRemoval: Bad Device Handle, deviceId=0x%x\n", deviceid)); + } + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "3R"); + return ret; +} + +/******************************************************************************/ +/*! \brief Set Device State Response + * + * This routine handles the response of SET Device State Response + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb Pointer of IOMB Mesage + * + * \return sucess or fail + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiSetDeviceStateRsp( + agsaRoot_t *agRoot, + agsaSetDeviceStateRsp_t *pIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaDevHandle_t *agDevHandle; + agsaDeviceDesc_t *pDevice; + agsaContext_t *agContext; + bit32 tag, status, deviceState, deviceId; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"3Q"); + + SA_DBG1(("mpiSetDeviceStateRsp: HTag=0x%x, deviceId=0x%x\n", pIomb->tag, pIomb->deviceId)); + + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaSetDeviceStateRsp_t, tag)); + OSSA_READ_LE_32(AGROOT, &deviceId, pIomb, OSSA_OFFSET_OF(agsaSetDeviceStateRsp_t, deviceId)); + OSSA_READ_LE_32(AGROOT, &status, pIomb, OSSA_OFFSET_OF(agsaSetDeviceStateRsp_t, status)); + + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + SA_DBG1(("mpiSetDeviceStateRsp: Bad Response IOMB!!! pRequest is NULL. TAG=0x%x STATUS=0x%x\n", tag, status)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "3Q"); + return AGSA_RC_FAILURE; + } + + agContext = saRoot->IOMap[tag].agContext; + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + SA_ASSERT((pRequest->valid), "pRequest->valid"); + + /* status is SUCCESS */ + OSSA_READ_LE_32(AGROOT, &deviceState, pIomb, OSSA_OFFSET_OF(agsaSetDeviceStateRsp_t, pds_nds)); + + /* find device handle from device index */ + pDevice = (agsaDeviceDesc_t *)saRoot->DeviceMap[deviceId & DEVICE_ID_BITS].DeviceHandle; + if (agNULL == pDevice) + { + SA_DBG1(("mpiSetDeviceStateRsp: DeviceHandle is NULL!!! deviceId=0x%x TAG=0x%x STATUS=0x%x \n", deviceId, tag, status)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "3Q"); + return AGSA_RC_FAILURE; + } + + if (pDevice->targetDevHandle.sdkData) + { + agDevHandle = &(pDevice->targetDevHandle); + } + else + { + agDevHandle = &(pDevice->initiatorDevHandle); + } + + if (agDevHandle == agNULL) + { + SA_DBG1(("mpiSetDeviceStateRsp: warning!!! no deviceHandle is found")); + ossaSetDeviceStateCB(agRoot, agContext, agNULL, OSSA_IO_NO_DEVICE, 0, 0); + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "3Q"); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiSetDeviceStateRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + return AGSA_RC_FAILURE; + } + + ossaSetDeviceStateCB(agRoot, agContext, agDevHandle, status, (deviceState & NDS_BITS), + (deviceState & PDS_BITS) >> SHIFT4); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiSetDeviceStateRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "3Q"); + return ret; +} + +/******************************************************************************/ +/*! \brief Get Device State Response + * + * This routine handles the response of GET Device State Response + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb Pointer of IOMB Mesage + * + * \return sucess or fail + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiGetDeviceStateRsp( + agsaRoot_t *agRoot, + agsaGetDeviceStateRsp_t *pIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaDevHandle_t *agDevHandle; + agsaDeviceDesc_t *pDevice; + agsaContext_t *agContext; + bit32 tag, status, deviceId, deviceState; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"3W"); + + SA_DBG1(("mpiGetDeviceStateRsp: HTag=0x%x, deviceId=0x%x\n", pIomb->tag, pIomb->deviceId)); + + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaGetDeviceStateRsp_t, tag)); + OSSA_READ_LE_32(AGROOT, &deviceId, pIomb, OSSA_OFFSET_OF(agsaGetDeviceStateRsp_t, deviceId)); + OSSA_READ_LE_32(AGROOT, &status, pIomb, OSSA_OFFSET_OF(agsaGetDeviceStateRsp_t, status)); + + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + SA_DBG1(("mpiGetDeviceStateRsp: Bad Response IOMB!!! pRequest is NULL. TAG=0x%x STATUS=0x%x\n", tag, status)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "3W"); + return AGSA_RC_FAILURE; + } + + agContext = saRoot->IOMap[tag].agContext; + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + SA_ASSERT((pRequest->valid), "pRequest->valid"); + + /* status is SUCCESS */ + OSSA_READ_LE_32(AGROOT, &deviceState, pIomb, OSSA_OFFSET_OF(agsaGetDeviceStateRsp_t, ds)); + + /* find device handle from device index */ + pDevice = (agsaDeviceDesc_t *)saRoot->DeviceMap[deviceId & DEVICE_ID_BITS].DeviceHandle; + if (pDevice != agNULL) + { + if (pDevice->targetDevHandle.sdkData) + { + agDevHandle = &(pDevice->targetDevHandle); + } + else + { + agDevHandle = &(pDevice->initiatorDevHandle); + } + } + else + { + SA_DBG1(("mpiGetDeviceStateRsp: pDevice is NULL")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "3W"); + return AGSA_RC_FAILURE; + } + + if (agDevHandle == agNULL) + { + SA_DBG1(("mpiGetDeviceStateRsp: warning!!! no deviceHandle is found")); + ossaGetDeviceStateCB(agRoot, agContext, agNULL, OSSA_IO_NO_DEVICE, 0); + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "3W"); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiGetDeviceStateRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + return AGSA_RC_FAILURE; + } + + ossaGetDeviceStateCB(agRoot, agContext, agDevHandle, status, deviceState); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiGetDeviceStateRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "3W"); + return ret; +} + +/******************************************************************************/ +/*! \brief SAS ReInitialize Response + * + * This routine handles the response of SAS Reinitialize Response + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb Pointer of IOMB Mesage + * + * \return sucess or fail + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiSasReInitializeRsp( + agsaRoot_t *agRoot, + agsaSasReInitializeRsp_t *pIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaContext_t *agContext; + agsaSASReconfig_t SASReconfig; + bit32 tag, status, setFlags, MaxPorts; + bit32 openRejReCmdData, sataHOLTMO; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"3X"); + + SA_DBG1(("mpiSasReInitializeRsp: HTag=0x%x, status=0x%x\n", pIomb->tag, pIomb->status)); + + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaSasReInitializeRsp_t, tag)); + OSSA_READ_LE_32(AGROOT, &status, pIomb, OSSA_OFFSET_OF(agsaSasReInitializeRsp_t, status)); + OSSA_READ_LE_32(AGROOT, &setFlags, pIomb, OSSA_OFFSET_OF(agsaSasReInitializeRsp_t, setFlags)); + OSSA_READ_LE_32(AGROOT, &MaxPorts, pIomb, OSSA_OFFSET_OF(agsaSasReInitializeRsp_t, MaxPorts)); + OSSA_READ_LE_32(AGROOT, &openRejReCmdData, pIomb, OSSA_OFFSET_OF(agsaSasReInitializeRsp_t, openRejReCmdData)); + OSSA_READ_LE_32(AGROOT, &sataHOLTMO, pIomb, OSSA_OFFSET_OF(agsaSasReInitializeRsp_t, sataHOLTMO)); + + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + SA_DBG1(("mpiSasReInitializeRsp: Bad Response IOMB!!! pRequest is NULL. TAG=0x%x STATUS=0x%x\n", tag, status)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "3X"); + return AGSA_RC_FAILURE; + } + + agContext = saRoot->IOMap[tag].agContext; + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + SA_ASSERT((pRequest->valid), "pRequest->valid"); + + SASReconfig.flags = setFlags; + SASReconfig.maxPorts = (bit8)(MaxPorts & 0xFF); + SASReconfig.openRejectRetriesCmd = (bit16)((openRejReCmdData & 0xFFFF0000) >> SHIFT16); + SASReconfig.openRejectRetriesData = (bit16)(openRejReCmdData & 0x0000FFFF); + SASReconfig.sataHolTmo = (bit16)(sataHOLTMO & 0xFFFF); + ossaReconfigSASParamsCB(agRoot, agContext, status, &SASReconfig); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiSasReInitializeRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "3X"); + + return ret; +} + +/******************************************************************************/ +/*! \brief serial GPIO Response + * + * This routine handles the response of serial GPIO Response + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb Pointer of IOMB Mesage + * + * \return sucess or fail + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiSGpioRsp( + agsaRoot_t *agRoot, + agsaSGpioRsp_t *pInIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest = NULL; + agsaContext_t *agContext = NULL; + bit32 i, tag, resultFunctionFrameType; + agsaSGpioReqResponse_t SgpioResponse = {0}; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"3Y"); + + SA_DBG3(("mpiSGpioRsp: HTAG=0x%x\n", pInIomb->tag)); + + OSSA_READ_LE_32(AGROOT, &tag, pInIomb, OSSA_OFFSET_OF(agsaSGpioRsp_t, tag)); + OSSA_READ_LE_32(AGROOT, &resultFunctionFrameType, pInIomb, OSSA_OFFSET_OF(agsaSGpioRsp_t, resultFunctionFrameType)); + + SgpioResponse.smpFrameType = resultFunctionFrameType & 0xFF; + SgpioResponse.function = (resultFunctionFrameType & 0xFF00) >> 8; + SgpioResponse.functionResult = (resultFunctionFrameType & 0xFF0000) >> 16; + + if (SA_SAS_SMP_READ_GPIO_REGISTER == SgpioResponse.function) + { + for (i = 0; i < OSSA_SGPIO_MAX_READ_DATA_COUNT; i++) + { + OSSA_READ_LE_32(AGROOT, &SgpioResponse.readWriteData[i], pInIomb, OSSA_OFFSET_OF(agsaSGpioRsp_t, readData) + (i * 4)); + } + } + + /* Get the request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + SA_DBG1(("mpiSGpioRsp: Bad Response IOMB!!! pRequest is NULL.TAG=0x%x STATUS=0x%x\n", tag, SgpioResponse.functionResult)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "3Y"); + ret = AGSA_RC_FAILURE; + } + else + { + agContext = saRoot->IOMap[tag].agContext; + ossaSGpioCB(agRoot, agContext, &SgpioResponse); + + /* Return the request to free pool */ + saReturnRequestToFreePool(agRoot, pRequest); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "3Y"); + } + + return ret; +} + +/******************************************************************************/ +/*! \brief PCIE Diagnostics Response + * + * This routine handles the response of PCIE Diagnostics Response + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb Pointer of IOMB Mesage + * + * \return sucess or fail + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiPCIeDiagExecuteRsp( + agsaRoot_t *agRoot, + void *pInIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = agNULL; + agsaIORequestDesc_t *pRequest; + agsaContext_t *agContext; + bit32 tag, Status, Command; + agsaPCIeDiagResponse_t pciediadrsp; + bit32 *pIomb = (bit32 *)pInIomb; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"3Z"); + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + SA_ASSERT((agNULL != saRoot), ""); + + si_memset(&pciediadrsp, 0, sizeof(agsaPCIeDiagResponse_t)); + + if(smIS_SPCV(agRoot)) + { + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaPCIeDiagExecuteRsp_t,tag)); + OSSA_READ_LE_32(AGROOT, &Command, pIomb, OSSA_OFFSET_OF(agsaPCIeDiagExecuteRsp_t,CmdTypeDesc)); + OSSA_READ_LE_32(AGROOT, &Status, pIomb, OSSA_OFFSET_OF(agsaPCIeDiagExecuteRsp_t,Status)); + OSSA_READ_LE_32(AGROOT, &pciediadrsp.ERR_BLKH, pIomb, OSSA_OFFSET_OF(agsaPCIeDiagExecuteRsp_t,ERR_BLKH )); + OSSA_READ_LE_32(AGROOT, &pciediadrsp.ERR_BLKL, pIomb, OSSA_OFFSET_OF(agsaPCIeDiagExecuteRsp_t,ERR_BLKL )); + OSSA_READ_LE_32(AGROOT, &pciediadrsp.DWord8, pIomb, OSSA_OFFSET_OF(agsaPCIeDiagExecuteRsp_t,DWord8 )); + OSSA_READ_LE_32(AGROOT, &pciediadrsp.DWord9, pIomb, OSSA_OFFSET_OF(agsaPCIeDiagExecuteRsp_t,DWord9 )); + OSSA_READ_LE_32(AGROOT, &pciediadrsp.DWord10, pIomb, OSSA_OFFSET_OF(agsaPCIeDiagExecuteRsp_t,DWord10 )); + OSSA_READ_LE_32(AGROOT, &pciediadrsp.DWord11, pIomb, OSSA_OFFSET_OF(agsaPCIeDiagExecuteRsp_t,DWord11 )); + OSSA_READ_LE_32(AGROOT, &pciediadrsp.DIF_ERR, pIomb, OSSA_OFFSET_OF(agsaPCIeDiagExecuteRsp_t,DIF_ERR )); + SA_DBG3(("mpiPCIeDiagExecuteRsp: HTAG=0x%x\n",tag)); + } + else + { + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsa_SPC_PCIeDiagExecuteRsp_t,tag)); + OSSA_READ_LE_32(AGROOT, &Command, pIomb, OSSA_OFFSET_OF(agsa_SPC_PCIeDiagExecuteRsp_t,CmdTypeDesc)); + OSSA_READ_LE_32(AGROOT, &Status, pIomb, OSSA_OFFSET_OF(agsa_SPC_PCIeDiagExecuteRsp_t,Status)); + SA_DBG3(("mpiPCIeDiagExecuteRsp: SPC HTAG=0x%x\n",tag)); + } + + switch(Status) + { + case OSSA_PCIE_DIAG_SUCCESS: + SA_DBG3(("mpiPCIeDiagExecuteRsp: OSSA_PCIE_DIAG_SUCCESS TAG=0x%x STATUS=0x%x\n", tag, Status)); + break; + case OSSA_IO_INVALID_LENGTH: + SA_DBG1(("mpiPCIeDiagExecuteRsp: OSSA_IO_INVALID_LENGTH TAG=0x%x STATUS=0x%x\n", tag, Status)); + break; + case OSSA_PCIE_DIAG_INVALID_COMMAND: + SA_DBG1(("mpiPCIeDiagExecuteRsp: OSSA_PCIE_DIAG_INVALID_COMMAND TAG=0x%x STATUS=0x%x\n", tag, Status)); + break; + case OSSA_PCIE_DIAG_INTERNAL_FAILURE: + SA_DBG1(("mpiPCIeDiagExecuteRsp: OSSA_PCIE_DIAG_INTERNAL_FAILURE TAG=0x%x STATUS=0x%x\n", tag, Status)); + break; + case OSSA_PCIE_DIAG_INVALID_CMD_TYPE: + SA_DBG1(("mpiPCIeDiagExecuteRsp: OSSA_PCIE_DIAG_INVALID_CMD_TYPE TAG=0x%x STATUS=0x%x\n", tag, Status)); + break; + case OSSA_PCIE_DIAG_INVALID_CMD_DESC: + SA_DBG1(("mpiPCIeDiagExecuteRsp: OSSA_PCIE_DIAG_INVALID_CMD_DESC TAG=0x%x STATUS=0x%x\n", tag, Status)); + break; + case OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH: + SA_DBG1(("mpiPCIeDiagExecuteRsp: OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH TAG=0x%x STATUS=0x%x\n", tag, Status)); + break; + case OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_CRC_MISMATCH: + SA_DBG1(("mpiPCIeDiagExecuteRsp: OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_CRC_MISMATCH TAG=0x%x STATUS=0x%x\n", tag, Status)); + break; + case OSSA_PCIE_DIAG_INVALID_PCIE_ADDR: + SA_DBG1(("mpiPCIeDiagExecuteRsp: OSSA_PCIE_DIAG_INVALID_PCIE_ADDR TAG=0x%x STATUS=0x%x\n", tag, Status)); + break; + case OSSA_PCIE_DIAG_INVALID_BLOCK_SIZE: + SA_DBG1(("mpiPCIeDiagExecuteRsp: OSSA_PCIE_DIAG_INVALID_BLOCK_SIZE TAG=0x%x STATUS=0x%x\n", tag, Status)); + break; + case OSSA_PCIE_DIAG_LENGTH_NOT_BLOCK_SIZE_ALIGNED: + SA_DBG1(("mpiPCIeDiagExecuteRsp: OSSA_PCIE_DIAG_LENGTH_NOT_BLOCK_SIZE_ALIGNED TAG=0x%x STATUS=0x%x\n", tag, Status)); + break; + case OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_MISMATCH: + SA_DBG1(("mpiPCIeDiagExecuteRsp: OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_MISMATCH TAG=0x%x STATUS=0x%x\n", tag, Status)); + break; + case OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH: + SA_DBG1(("mpiPCIeDiagExecuteRsp: OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH TAG=0x%x STATUS=0x%x\n", tag, Status)); + break; + default: + SA_DBG1(("mpiPCIeDiagExecuteRsp: UNKNOWN status TAG=0x%x STATUS=0x%x\n", tag, Status)); + break; + } + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + SA_DBG1(("mpiPCIeDiagExecuteRsp: Bad Response IOMB!!! pRequest is NULL.TAG=0x%x STATUS=0x%x\n", tag, Status)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "3Z"); + return AGSA_RC_FAILURE; + } + + agContext = saRoot->IOMap[tag].agContext; + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + SA_ASSERT((pRequest->valid), "pRequest->valid"); + + ossaPCIeDiagExecuteCB(agRoot, agContext, Status, Command,&pciediadrsp); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiPCIeDiagExecuteRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "3Z"); + + /* return value */ + return ret; +} +/******************************************************************************/ +/*! \brief Get DFE Data command Response + * + * This routine handles the response of Get DFE Data command Response + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb Pointer of IOMB Mesage + * + * \return sucess or fail + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiGetDFEDataRsp( + agsaRoot_t *agRoot, + void *pIomb + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = agNULL; + agsaIORequestDesc_t *pRequest; + agsaContext_t *agContext; + bit32 tag = 0, status = 0, In_Ln = 0, MCNT = 0, NBT = 0; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2Y"); + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + SA_ASSERT((agNULL != saRoot), ""); + + if(smIS_SPCV(agRoot)) + { + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaGetDDEFDataRsp_t,tag)); + OSSA_READ_LE_32(AGROOT, &status, pIomb, OSSA_OFFSET_OF(agsaGetDDEFDataRsp_t,status)); + OSSA_READ_LE_32(AGROOT, &In_Ln, pIomb, OSSA_OFFSET_OF(agsaGetDDEFDataRsp_t,reserved_In_Ln)); + OSSA_READ_LE_32(AGROOT, &MCNT, pIomb, OSSA_OFFSET_OF(agsaGetDDEFDataRsp_t,MCNT)); + OSSA_READ_LE_32(AGROOT, &NBT, pIomb, OSSA_OFFSET_OF(agsaGetDDEFDataRsp_t,NBT)); + } + else + { + /* SPC does not support this command */ + } + + switch(status) + { + case OSSA_DFE_MPI_IO_SUCCESS: + SA_DBG3(("mpiGetDFEDataRsp: OSSA_DFE_MPI_IO_SUCCESS TAG=0x%x STATUS=0x%x\n", tag, status)); + break; + case OSSA_DFE_DATA_OVERFLOW: + SA_DBG1(("mpiGetDFEDataRsp: OSSA_DFE_DATA_OVERFLOW TAG=0x%x STATUS=0x%x\n", tag, status)); + break; + case OSSA_DFE_MPI_ERR_RESOURCE_UNAVAILABLE: + SA_DBG1(("mpiGetDFEDataRsp: OSSA_DFE_MPI_ERR_RESOURCE_UNAVAILABLE TAG=0x%x STATUS=0x%x\n", tag, status)); + break; + case OSSA_DFE_CHANNEL_DOWN: + SA_DBG1(("mpiGetDFEDataRsp: OSSA_DFE_CHANNEL_DOWN TAG=0x%x STATUS=0x%x\n", tag, status)); + break; + case OSSA_DFE_MEASUREMENT_IN_PROGRESS: + SA_DBG1(("mpiGetDFEDataRsp: OSSA_DFE_MEASUREMENT_IN_PROGRESS TAG=0x%x STATUS=0x%x\n", tag, status)); + break; + case OSSA_DFE_CHANNEL_INVALID: + SA_DBG1(("mpiGetDFEDataRsp: OSSA_DFE_CHANNEL_INVALID TAG=0x%x STATUS=0x%x\n", tag, status)); + break; + case OSSA_DFE_DMA_FAILURE: + SA_DBG1(("mpiGetDFEDataRsp: OSSA_DFE_DMA_FAILURE TAG=0x%x STATUS=0x%x\n", tag, status)); + break; + default: + SA_DBG1(("mpiGetDFEDataRsp: UNKNOWN status TAG=0x%x STATUS=0x%x\n", tag, status)); + break; + } + + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + SA_DBG1(("mpiGetDFEDataRsp: Bad Response IOMB!!! pRequest is NULL.TAG=0x%x STATUS=0x%x\n", tag, status)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2Y"); + return AGSA_RC_FAILURE; + } + + agContext = saRoot->IOMap[tag].agContext; + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + SA_ASSERT((pRequest->valid), "pRequest->valid"); + + ossaGetDFEDataCB(agRoot, agContext, status, NBT); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiGetDFEDataRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2Y"); + + return ret; +} + + +/******************************************************************************/ +/*! \brief SAS Set Controller Config Response + * + * This routine handles the response of Set Controller Config Command + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb Pointer of IOMB Mesage + * + * \return sucess or fail + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiSetControllerConfigRsp( + agsaRoot_t *agRoot, + agsaSetControllerConfigRsp_t *pIomb + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaHWEventMode_t agMode; + bit32 status, errorQualifierPage, tag; + bit32 errorQualifier; + bit32 pagetype; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"3a"); + + SA_DBG1(("mpiSetControllerConfigRsp: HTag=0x%x\n", pIomb->tag)); + + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaSetControllerConfigRsp_t, tag)); + OSSA_READ_LE_32(AGROOT, &status, pIomb, OSSA_OFFSET_OF(agsaSetControllerConfigRsp_t, status)); + OSSA_READ_LE_32(AGROOT, &errorQualifierPage, pIomb, OSSA_OFFSET_OF(agsaSetControllerConfigRsp_t, errorQualifierPage)); + + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + SA_DBG1(("mpiSetControllerConfigRsp: Bad Response IOMB!!! pRequest is NULL. TAG=0x%x STATUS=0x%x\n", tag, status)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "3a"); + return AGSA_RC_FAILURE; + } + + si_memset(&agMode, 0, sizeof(agsaHWEventMode_t)); + agMode.modePageOperation = agsaModePageSet; + agMode.status = status; + agMode.context = saRoot->IOMap[tag].agContext; + errorQualifier = (errorQualifierPage & 0xFFFF0000) >> SHIFT16; + pagetype = (errorQualifierPage & 0xFF); + + if(status ) + { + SA_DBG1(("mpiSetControllerConfigRsp: Error detected tag 0x%x pagetype 0x%x status 0x%x errorQualifier 0x%x\n", + tag, pagetype,status, errorQualifier)); + } + else + { + SA_DBG1(("mpiSetControllerConfigRsp: tag 0x%x pagetype 0x%x status 0x%x\n", tag, pagetype,status )); + } + + + switch( pagetype) + { + case AGSA_ENCRYPTION_DEK_CONFIG_PAGE: + case AGSA_SAS_PROTOCOL_TIMER_CONFIG_PAGE: + case AGSA_INTERRUPT_CONFIGURATION_PAGE: + case AGSA_ENCRYPTION_HMAC_CONFIG_PAGE: + case AGSA_IO_GENERAL_CONFIG_PAGE: + /*case AGSA_ENCRYPTION_CONTROL_PARM_PAGE:*/ + /* Report the event before freeing the IOMB */ + SA_DBG1(("mpiSetControllerConfigRsp:OSSA_HW_EVENT_MODE\n")); + ossaHwCB(agRoot,agMode.context, OSSA_HW_EVENT_MODE, errorQualifierPage, (void *) &agMode, 0); + + + break; + + case AGSA_ENCRYPTION_GENERAL_CONFIG_PAGE: + SA_DBG1(("mpiSetControllerConfigRsp:warning!!!! GENERAL_CONFIG_PAGE is read only, cannot be set\n")); + break; + + /* why we need to read the scrach pad register when handling ENCRYPTION_SECURITY_PARM_PAGE??? */ + case AGSA_ENCRYPTION_CONTROL_PARM_PAGE: + { + bit32 ScratchPad1 = 0; + bit32 ScratchPad3 = 0; + agsaEncryptInfo_t encrypt; + agsaEncryptInfo_t *encryptInfo = &encrypt; + SA_DBG1(("mpiSetControllerConfigRsp: AGSA_ENCRYPTION_CONTROL_PARM_PAGE\n" )); + + if( pRequest->modePageContext) + { + pRequest->modePageContext = agFALSE; + } + + si_memset(&encrypt, 0, sizeof(agsaEncryptInfo_t)); + encryptInfo->status = 0; + encryptInfo->encryptionCipherMode = 0; + encryptInfo->encryptionSecurityMode = 0; + + ScratchPad1 = ossaHwRegRead(agRoot,V_Scratchpad_1_Register); + ScratchPad3 = ossaHwRegRead(agRoot,V_Scratchpad_3_Register); + if( ScratchPad3 & SCRATCH_PAD3_V_XTS_ENABLED) + { + encryptInfo->encryptionCipherMode = agsaEncryptCipherModeXTS; + } + if( (ScratchPad3 & SCRATCH_PAD3_V_SM_MASK ) == SCRATCH_PAD3_V_SMF_ENABLED ) + { + encryptInfo->encryptionSecurityMode = agsaEncryptSMF; + } + if( (ScratchPad3 & SCRATCH_PAD3_V_SM_MASK ) == SCRATCH_PAD3_V_SMA_ENABLED) + { + encryptInfo->encryptionSecurityMode = agsaEncryptSMA; + } + if( (ScratchPad3 & SCRATCH_PAD3_V_SM_MASK ) == SCRATCH_PAD3_V_SMB_ENABLED ) + { + encryptInfo->encryptionSecurityMode = agsaEncryptSMB; + } + if((ScratchPad1 & SCRATCH_PAD1_V_RAAE_MASK) == SCRATCH_PAD1_V_RAAE_MASK) + { + if((ScratchPad3 & SCRATCH_PAD3_V_ENC_MASK) == SCRATCH_PAD3_V_ENC_READY ) /* 3 */ + { + encryptInfo->status = AGSA_RC_SUCCESS; + } + else if((ScratchPad3 & SCRATCH_PAD3_V_ENC_READY) == SCRATCH_PAD3_V_ENC_DISABLED) /* 0 */ + { + encryptInfo->status = 0xFFFF; + encryptInfo->encryptionCipherMode = 0; + encryptInfo->encryptionSecurityMode = 0; + } + else if((ScratchPad3 & SCRATCH_PAD3_V_ENC_MASK ) == SCRATCH_PAD3_V_ENC_DIS_ERR) /* 1 */ + { + encryptInfo->status = (ScratchPad3 & SCRATCH_PAD3_V_ERR_CODE ) >> SHIFT16; + } + else if((ScratchPad3 & SCRATCH_PAD3_V_ENC_MASK ) == SCRATCH_PAD3_V_ENC_ENA_ERR) /* 2 */ + { + encryptInfo->status = (ScratchPad3 & SCRATCH_PAD3_V_ERR_CODE ) >> SHIFT16; + } + } + else if((ScratchPad1 & SCRATCH_PAD1_V_RAAE_MASK) == SCRATCH_PAD1_V_RAAE_ERR) + { + SA_DBG1(("mpiSetControllerConfigRsp, RAAE not ready SPC AGSA_RC_FAILURE\n")); + encryptInfo->status = 0xFFFF; + encryptInfo->encryptionCipherMode = 0; + encryptInfo->encryptionSecurityMode = 0; + } + else if((ScratchPad1 & SCRATCH_PAD1_V_RAAE_MASK) == 0x0 ) + { + SA_DBG2(("mpiSetControllerConfigRsp, RAAE not ready AGSA_RC_BUSY\n")); + } + + SA_DBG2(("mpiSetControllerConfigRsp, encryptionCipherMode 0x%x encryptionSecurityMode 0x%x status 0x%x\n", + encryptInfo->encryptionCipherMode, + encryptInfo->encryptionSecurityMode, + encryptInfo->status)); + SA_DBG2(("mpiSetControllerConfigRsp, ScratchPad3 0x%x\n",ScratchPad3)); + SA_DBG1(("mpiSetControllerConfigRsp:AGSA_ENCRYPTION_CONTROL_PARM_PAGE 0x%X\n", agMode.modePageOperation)); + ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_SECURITY_MODE, errorQualifier, (void *)encryptInfo, agMode.context); + break; + } + + default: + SA_DBG1(("mpiSetControllerConfigRsp: Unknown page code 0x%X\n", pagetype)); + break; + } + + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_ASSERT((pRequest->valid), "pRequest->valid"); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiSetControllerRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "3a"); + return AGSA_RC_SUCCESS; + +} + +/******************************************************************************/ +/*! \brief SAS Get Controller Config Response + * + * This routine handles the response of Get Controller Config Command + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb Pointer of IOMB Mesage + * + * \return sucess or fail + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiGetControllerConfigRsp( + agsaRoot_t *agRoot, + agsaGetControllerConfigRsp_t *pIomb + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaHWEventMode_t agMode; + bit32 status, errorQualifier, tag; + bit32 configPage[12]; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"3b"); + + si_memset(&agMode, 0, sizeof(agsaHWEventMode_t)); + si_memset(configPage, 0, sizeof(configPage)); + + + SA_DBG2(("mpiGetControllerConfigRsp: HTag=0x%x\n", pIomb->tag)); + + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaGetControllerConfigRsp_t, tag)); + OSSA_READ_LE_32(AGROOT, &status, pIomb, OSSA_OFFSET_OF(agsaGetControllerConfigRsp_t, status)); + OSSA_READ_LE_32(AGROOT, &errorQualifier, pIomb, OSSA_OFFSET_OF(agsaGetControllerConfigRsp_t, errorQualifier)); + OSSA_READ_LE_32(AGROOT, &configPage[0], pIomb, OSSA_OFFSET_OF(agsaGetControllerConfigRsp_t,configPage[0] )); + OSSA_READ_LE_32(AGROOT, &configPage[1], pIomb, OSSA_OFFSET_OF(agsaGetControllerConfigRsp_t,configPage[1] )); + OSSA_READ_LE_32(AGROOT, &configPage[2], pIomb, OSSA_OFFSET_OF(agsaGetControllerConfigRsp_t,configPage[2] )); + OSSA_READ_LE_32(AGROOT, &configPage[3], pIomb, OSSA_OFFSET_OF(agsaGetControllerConfigRsp_t,configPage[3] )); + OSSA_READ_LE_32(AGROOT, &configPage[4], pIomb, OSSA_OFFSET_OF(agsaGetControllerConfigRsp_t,configPage[4] )); + OSSA_READ_LE_32(AGROOT, &configPage[5], pIomb, OSSA_OFFSET_OF(agsaGetControllerConfigRsp_t,configPage[5] )); + + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + SA_DBG1(("mpiGetControllerConfigRsp: Bad Response IOMB!!! pRequest is NULL. TAG=0x%x STATUS=0x%x\n", tag, status)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "3b"); + return AGSA_RC_FAILURE; + } + + si_memset(&agMode, 0, sizeof(agsaHWEventMode_t)); + agMode.modePageOperation = agsaModePageGet; + agMode.status = status; + + SA_DBG1(("mpiGetControllerConfigRsp: page 0x%x status 0x%x errorQualifier 0x%x \n", (pIomb->configPage[0] & 0xFF),status, errorQualifier)); + + switch (pIomb->configPage[0] & 0xFF) + { + case AGSA_SAS_PROTOCOL_TIMER_CONFIG_PAGE: + agMode.modePageLen = sizeof(agsaSASProtocolTimerConfigurationPage_t); + SA_DBG1(("mpiGetControllerConfigRsp: AGSA_SAS_PROTOCOL_TIMER_CONFIG_PAGE page len 0x%x \n",agMode.modePageLen)); + break; + case AGSA_INTERRUPT_CONFIGURATION_PAGE: + agMode.modePageLen = sizeof(agsaInterruptConfigPage_t); + SA_DBG1(("mpiGetControllerConfigRsp: AGSA_INTERRUPT_CONFIGURATION_PAGE page len 0x%x \n",agMode.modePageLen)); + break; + case AGSA_IO_GENERAL_CONFIG_PAGE: + agMode.modePageLen = sizeof(agsaIoGeneralPage_t); + SA_DBG1(("mpiGetControllerConfigRsp: AGSA_IO_GENERAL_CONFIG_PAGE page len 0x%x \n",agMode.modePageLen)); + break; + case AGSA_ENCRYPTION_GENERAL_CONFIG_PAGE: + agMode.modePageLen = sizeof(agsaEncryptGeneralPage_t); + SA_DBG1(("mpiGetControllerConfigRsp: AGSA_ENCRYPTION_GENERAL_CONFIG_PAGE page len 0x%x \n",agMode.modePageLen)); +#ifdef HIALEAH_ENCRYPTION + saRoot->EncGenPage.numberOfKeksPageCode = configPage[0]; + saRoot->EncGenPage.KeyCardIdKekIndex = configPage[1]; + saRoot->EncGenPage.KeyCardId3_0 = configPage[2]; + saRoot->EncGenPage.KeyCardId7_4 = configPage[3]; + saRoot->EncGenPage.KeyCardId11_8 = configPage[4]; + + SA_DBG1(("mpiGetControllerConfigRsp: numberOfKeksPageCode 0x%x\n",saRoot->EncGenPage.numberOfKeksPageCode)); + SA_DBG1(("mpiGetControllerConfigRsp: KeyCardIdKekIndex 0x%x\n",saRoot->EncGenPage.KeyCardIdKekIndex)); + SA_DBG1(("mpiGetControllerConfigRsp: KeyCardId3_0 0x%x\n",saRoot->EncGenPage.KeyCardId3_0)); + SA_DBG1(("mpiGetControllerConfigRsp: KeyCardId7_4 0x%x\n",saRoot->EncGenPage.KeyCardId7_4)); + SA_DBG1(("mpiGetControllerConfigRsp: KeyCardId11_8 0x%x\n",saRoot->EncGenPage.KeyCardId11_8)); +#endif /* HIALEAH_ENCRYPTION */ + + break; + case AGSA_ENCRYPTION_DEK_CONFIG_PAGE: + agMode.modePageLen = sizeof(agsaEncryptDekConfigPage_t); + SA_DBG1(("mpiGetControllerConfigRsp: AGSA_ENCRYPTION_DEK_CONFIG_PAGE page len 0x%x \n",agMode.modePageLen)); + break; + case AGSA_ENCRYPTION_CONTROL_PARM_PAGE: + agMode.modePageLen = sizeof(agsaEncryptControlParamPage_t); + SA_DBG1(("mpiGetControllerConfigRsp: AGSA_ENCRYPTION_CONTROL_PARM_PAGE page len 0x%x \n",agMode.modePageLen)); + break; + case AGSA_ENCRYPTION_HMAC_CONFIG_PAGE: + agMode.modePageLen = sizeof(agsaEncryptHMACConfigPage_t); + SA_DBG1(("mpiGetControllerConfigRsp: AGSA_ENCRYPTION_HMAC_CONFIG_PAGE page len 0x%x \n",agMode.modePageLen)); + break; + default: + agMode.modePageLen = 0; + SA_DBG1(("mpiGetControllerConfigRsp: Unknown !!! page len 0x%x \n",agMode.modePageLen)); + break; + } + + agMode.modePage = (void *) &pIomb->configPage[0]; + agMode.context = saRoot->IOMap[tag].agContext; + + /* Report the event before freeing the IOMB */ + ossaHwCB(agRoot, NULL, OSSA_HW_EVENT_MODE, errorQualifier, (void *) &agMode, 0); + + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_ASSERT((pRequest->valid), "pRequest->valid"); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiGetControllerRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "3b"); + return AGSA_RC_SUCCESS; +} + +/******************************************************************************/ +/*! \brief KEK Management Response + * + * This routine handles the response of the KEK management message + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb Pointer of IOMB Mesage + * + * \return sucess or fail + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiKekManagementRsp( + agsaRoot_t *agRoot, + agsaKekManagementRsp_t *pIomb + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaContext_t *agContext; + agsaHWEventEncrypt_t agEvent; + bit32 status, errorQualifier, tag, flags; + smTraceFuncEnter(hpDBG_VERY_LOUD,"2A"); + + SA_DBG1(("mpiKekManagementRsp: HTag=0x%x\n", pIomb->tag)); + + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaKekManagementRsp_t, tag)); + OSSA_READ_LE_32(AGROOT, &status, pIomb, OSSA_OFFSET_OF(agsaKekManagementRsp_t, status)); + OSSA_READ_LE_32(AGROOT, &flags, pIomb, OSSA_OFFSET_OF(agsaKekManagementRsp_t, flags)); + OSSA_READ_LE_32(AGROOT, &errorQualifier, pIomb, OSSA_OFFSET_OF(agsaKekManagementRsp_t, errorQualifier)); + + + SA_DBG1(("mpiKekManagementRsp:status 0x%x flags 0x%x errorQualifier 0x%x\n", status, flags, errorQualifier)); + + si_memset(&agEvent, 0, sizeof(agsaHWEventEncrypt_t)); + if ((flags & 0xFF) == KEK_MGMT_SUBOP_UPDATE) + { + SA_DBG1(("mpiKekManagementRsp:KEK_MGMT_SUBOP_UPDATE 0x%x \n", status)); + if (flags & 0xFF00) /* update and store*/ + { + agEvent.encryptOperation = OSSA_HW_ENCRYPT_KEK_UPDATE_AND_STORE; + } + else /* update */ + { + agEvent.encryptOperation = OSSA_HW_ENCRYPT_KEK_UPDATE; + } + agEvent.status = status; + if (status == OSSA_MPI_ENC_ERR_ILLEGAL_KEK_PARAM) + { + agEvent.eq = errorQualifier; + } + agEvent.info = 0; + /* Store the new KEK index in agEvent.handle */ + agEvent.handle = (void *) ((bitptr) (flags >> 24)); + /* Store the current KEK index in agEvent.param */ + agEvent.param = (void *) ((bitptr) (flags >> 16) & 0xFF); + + } + + else if ((flags & 0xFF) == KEK_MGMT_SUBOP_INVALIDATE) + { + agEvent.encryptOperation = OSSA_HW_ENCRYPT_KEK_INVALIDTE; + agEvent.status = status; + if (status == OSSA_MPI_ENC_ERR_ILLEGAL_KEK_PARAM) + { + agEvent.eq = errorQualifier; + } + agEvent.info = 0; + /* Store the new KEK index in agEvent.handle */ + agEvent.handle = (void *) ((bitptr) (flags >> 24)); + /* Store the current KEK index in agEvent.param */ + agEvent.param = (void *) ((bitptr) (flags >> 16) & 0xFF); + } + + else if ((flags & 0xFF) == KEK_MGMT_SUBOP_KEYCARDINVALIDATE) + { + agEvent.encryptOperation = OSSA_HW_ENCRYPT_KEK_UPDATE_AND_STORE; + agEvent.status = status; + if (status == OSSA_MPI_ENC_ERR_ILLEGAL_KEK_PARAM) + { + agEvent.eq = errorQualifier; + } + agEvent.info = 0; + /* Store the new KEK index in agEvent.handle */ + agEvent.handle = (void *) ((bitptr) (flags >> 24)); + /* Store the current KEK index in agEvent.param */ + agEvent.param = (void *) ((bitptr) (flags >> 16) & 0xFF); + + } + + else if ((flags & 0xFF) == KEK_MGMT_SUBOP_KEYCARDUPDATE) + { + agEvent.encryptOperation = OSSA_HW_ENCRYPT_KEK_UPDATE; + agEvent.status = status; + if (status == OSSA_MPI_ENC_ERR_ILLEGAL_KEK_PARAM) + { + agEvent.eq = errorQualifier; + } + agEvent.info = 0; + /* Store the new KEK index in agEvent.handle */ + agEvent.handle = (void *) ((bitptr) (flags >> 24)); + /* Store the current KEK index in agEvent.param */ + agEvent.param = (void *) ((bitptr) (flags >> 16) & 0xFF); + + } + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + SA_DBG1(("mpiKekManagementRsp: Bad Response IOMB!!! pRequest is NULL. TAG=0x%x STATUS=0x%x\n", tag, status)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2A"); + return AGSA_RC_FAILURE; + } + + agContext = saRoot->IOMap[tag].agContext; + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + ossaHwCB(agRoot, NULL, OSSA_HW_EVENT_ENCRYPTION, 0, (void *) &agEvent, agContext); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_ASSERT((pRequest->valid), "pRequest->valid"); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiKekManagementRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2A"); + + return AGSA_RC_SUCCESS; +} + +/******************************************************************************/ +/*! \brief DEK Management Response + * + * This routine handles the response of the DEK management message + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb Pointer of IOMB Mesage + * + * \return sucess or fail + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiDekManagementRsp( + agsaRoot_t *agRoot, + agsaDekManagementRsp_t *pIomb + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaContext_t *agContext; + agsaHWEventEncrypt_t agEvent; + bit32 flags, status, errorQualifier, tag, dekIndex; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2B"); + + SA_DBG1(("mpiDekManagementRsp: HTag=0x%x\n", pIomb->tag)); + + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaDekManagementRsp_t, tag)); + OSSA_READ_LE_32(AGROOT, &status, pIomb, OSSA_OFFSET_OF(agsaDekManagementRsp_t, status)); + OSSA_READ_LE_32(AGROOT, &flags, pIomb, OSSA_OFFSET_OF(agsaDekManagementRsp_t, flags)); + OSSA_READ_LE_32(AGROOT, &errorQualifier, pIomb, OSSA_OFFSET_OF(agsaDekManagementRsp_t, errorQualifier)); + OSSA_READ_LE_32(AGROOT, &dekIndex, pIomb, OSSA_OFFSET_OF(agsaDekManagementRsp_t, dekIndex)); + + SA_DBG2(("mpiDekManagementRsp:tag =0x%x\n",tag )); + SA_DBG2(("mpiDekManagementRsp:status =0x%x\n", status)); + SA_DBG2(("mpiDekManagementRsp:flags =0x%x\n",flags )); + SA_DBG2(("mpiDekManagementRsp:errorQualifier =0x%x\n", errorQualifier)); + SA_DBG2(("mpiDekManagementRsp:dekIndex =0x%x\n",dekIndex )); + + si_memset(&agEvent, 0, sizeof(agsaHWEventEncrypt_t)); + if ((flags & 0xFF) == DEK_MGMT_SUBOP_UPDATE) + { + agEvent.encryptOperation = OSSA_HW_ENCRYPT_DEK_UPDATE; + } + else + { + agEvent.encryptOperation = OSSA_HW_ENCRYPT_DEK_INVALIDTE; + } + agEvent.status = status; + if (status == OSSA_MPI_ENC_ERR_ILLEGAL_DEK_PARAM || OSSA_MPI_ERR_DEK_MANAGEMENT_DEK_UNWRAP_FAIL) + { + agEvent.eq = errorQualifier; + } + /* Store the DEK in agEvent.info */ + agEvent.info = (flags >> 8) & 0xF; + /* Store the KEK index in agEvent.handle */ + agEvent.handle = (void *) ((bitptr) (flags >> 24)); + /* Store the DEK index in agEvent.param */ + agEvent.param = (void *) (bitptr) dekIndex; + + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + SA_DBG1(("mpiDekManagementRsp: Bad Response IOMB!!! pRequest is NULL. TAG=0x%x STATUS=0x%x\n", tag, status)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2B"); + return AGSA_RC_FAILURE; + } + + agContext = saRoot->IOMap[tag].agContext; + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + ossaHwCB(agRoot, NULL, OSSA_HW_EVENT_ENCRYPTION, 0, (void *) &agEvent,agContext ); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_ASSERT((pRequest->valid), "pRequest->valid"); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiDekManagementRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2B"); + + return AGSA_RC_SUCCESS; +} + +/******************************************************************************/ +/*! \brief Operator Management Response + * + * This routine handles the response of the Operator management message + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb Pointer of IOMB Mesage + * + * \return sucess or fail + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiOperatorManagementRsp( + agsaRoot_t *agRoot, + agsaOperatorMangmenRsp_t *pIomb + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaContext_t *agContext; + agsaHWEventEncrypt_t agEvent; + bit32 OPRIDX_AUTIDX_R_OMO,status, errorQualifier, tag; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"36"); + + SA_DBG1(("mpiOperatorManagementRsp: HTag=0x%x\n", pIomb->tag)); + + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaOperatorMangmenRsp_t, tag)); + OSSA_READ_LE_32(AGROOT, &status, pIomb, OSSA_OFFSET_OF(agsaOperatorMangmenRsp_t, status)); + OSSA_READ_LE_32(AGROOT, &OPRIDX_AUTIDX_R_OMO, pIomb, OSSA_OFFSET_OF(agsaOperatorMangmenRsp_t, OPRIDX_AUTIDX_R_OMO)); + OSSA_READ_LE_32(AGROOT, &errorQualifier, pIomb, OSSA_OFFSET_OF(agsaOperatorMangmenRsp_t, errorQualifier)); + + SA_DBG2(("mpiOperatorManagementRsp:tag =0x%x\n",tag )); + SA_DBG2(("mpiOperatorManagementRsp:status =0x%x\n", status)); + SA_DBG2(("mpiOperatorManagementRsp:OPRIDX_AUTIDX_R_OMO =0x%x\n",OPRIDX_AUTIDX_R_OMO )); + SA_DBG2(("mpiOperatorManagementRsp:errorQualifier =0x%x\n", errorQualifier)); + + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + SA_DBG1(("mpiOperatorManagementRsp: Bad Response IOMB!!! pRequest is NULL. TAG=0x%x STATUS=0x%x\n", tag, status)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "36"); + return AGSA_RC_FAILURE; + } + + agContext = saRoot->IOMap[tag].agContext; + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + si_memset(&agEvent, 0, sizeof(agsaHWEventEncrypt_t)); + agEvent.status = status; + agEvent.info = OPRIDX_AUTIDX_R_OMO; + agEvent.encryptOperation = OSSA_HW_ENCRYPT_OPERATOR_MANAGEMENT; + if (status == OPR_MGMT_MPI_ENC_ERR_OPR_PARAM_ILLEGAL) + { + agEvent.eq = errorQualifier; + } + + ossaOperatorManagementCB(agRoot, agContext, status, errorQualifier); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_ASSERT((pRequest->valid), "pRequest->valid"); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiOperatorManagementRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "36"); + + return AGSA_RC_SUCCESS; +} + +GLOBAL bit32 mpiBistRsp( + agsaRoot_t *agRoot, + agsaEncryptBistRsp_t *pIomb + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaContext_t *agContext; + agsaHWEventEncrypt_t agEvent; + bit32 status; + bit32 results[11]; + bit32 length; + bit32 subop; + bit32 tag; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"37"); + + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaEncryptBistRsp_t, tag)); + OSSA_READ_LE_32(AGROOT, &status, pIomb, OSSA_OFFSET_OF(agsaEncryptBistRsp_t, status)); + OSSA_READ_LE_32(AGROOT, &subop, pIomb, OSSA_OFFSET_OF(agsaEncryptBistRsp_t, subop)); + OSSA_READ_LE_32(AGROOT, &results[0], pIomb, OSSA_OFFSET_OF(agsaEncryptBistRsp_t, testResults[0])); + OSSA_READ_LE_32(AGROOT, &results[1], pIomb, OSSA_OFFSET_OF(agsaEncryptBistRsp_t, testResults[1])); + OSSA_READ_LE_32(AGROOT, &results[2], pIomb, OSSA_OFFSET_OF(agsaEncryptBistRsp_t, testResults[2])); + OSSA_READ_LE_32(AGROOT, &results[3], pIomb, OSSA_OFFSET_OF(agsaEncryptBistRsp_t, testResults[3])); + OSSA_READ_LE_32(AGROOT, &results[4], pIomb, OSSA_OFFSET_OF(agsaEncryptBistRsp_t, testResults[4])); + OSSA_READ_LE_32(AGROOT, &results[5], pIomb, OSSA_OFFSET_OF(agsaEncryptBistRsp_t, testResults[5])); + OSSA_READ_LE_32(AGROOT, &results[6], pIomb, OSSA_OFFSET_OF(agsaEncryptBistRsp_t, testResults[6])); + OSSA_READ_LE_32(AGROOT, &results[7], pIomb, OSSA_OFFSET_OF(agsaEncryptBistRsp_t, testResults[7])); + OSSA_READ_LE_32(AGROOT, &results[8], pIomb, OSSA_OFFSET_OF(agsaEncryptBistRsp_t, testResults[8])); + OSSA_READ_LE_32(AGROOT, &results[9], pIomb, OSSA_OFFSET_OF(agsaEncryptBistRsp_t, testResults[9])); + OSSA_READ_LE_32(AGROOT, &results[10], pIomb, OSSA_OFFSET_OF(agsaEncryptBistRsp_t, testResults[10])); + + subop &= 0xFF; + SA_DBG1(("mpiBistRsp: HTag=0x%x subops =0x%x status =0x%x\n",pIomb->tag, subop, status)); + + switch(subop) + { + case AGSA_BIST_TEST: + length = sizeof(agsaEncryptSelfTestStatusBitMap_t); + break; + case AGSA_SHA_TEST: + length = sizeof(agsaEncryptSHATestResult_t); + break; + case AGSA_HMAC_TEST: + length = sizeof(agsaEncryptHMACTestResult_t); + break; + default: + length = 0; + break; + } + + si_memset(&agEvent, 0, sizeof(agsaHWEventEncrypt_t)); + agEvent.status = status; + agEvent.encryptOperation = OSSA_HW_ENCRYPT_TEST_EXECUTE; + agEvent.info = length; + agEvent.eq = subop; + agEvent.handle = agNULL; + agEvent.param = &results; + + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + SA_DBG1(("mpiBistRsp: Bad Response IOMB!!! pRequest is NULL. TAG=0x%x STATUS=0x%x\n", tag, status)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "37"); + return AGSA_RC_FAILURE; + } + + agContext = saRoot->IOMap[tag].agContext; + + ossaHwCB(agRoot, NULL, OSSA_HW_EVENT_ENCRYPTION, 0, (void*)&agEvent, agContext); + + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_ASSERT((pRequest->valid), "pRequest->valid"); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiBistRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "37"); + + return AGSA_RC_SUCCESS; +} + +/******************************************************************************/ +/*! \brief Set Operator Response + * + * This routine handles the response of the Operator management message + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb Pointer of IOMB Mesage + * + * \return sucess or fail + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiSetOperatorRsp( + agsaRoot_t *agRoot, + agsaSetOperatorRsp_t *pIomb + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest = agNULL; + agsaContext_t *agContext = agNULL; + bit32 ERR_QLFR_OPRIDX_PIN_ACS, OPRIDX_PIN_ACS, status, errorQualifier, tag = 0; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"38"); + + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaSetOperatorRsp_t, tag)); + OSSA_READ_LE_32(AGROOT, &status, pIomb, OSSA_OFFSET_OF(agsaSetOperatorRsp_t, status)); + OSSA_READ_LE_32(AGROOT, &ERR_QLFR_OPRIDX_PIN_ACS, pIomb, OSSA_OFFSET_OF(agsaSetOperatorRsp_t, ERR_QLFR_OPRIDX_PIN_ACS)); + + errorQualifier = ERR_QLFR_OPRIDX_PIN_ACS >> 16; + OPRIDX_PIN_ACS = ERR_QLFR_OPRIDX_PIN_ACS & 0xFFFF; + + SA_DBG1(("mpiSetOperatorRsp: HTag=0x%x ERR_QLFR=0x%x OPRIDX_PIN_ACS=0x%x \n",tag, errorQualifier, OPRIDX_PIN_ACS)); + + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + SA_DBG1(("mpiSetOperatorRsp: Bad Response IOMB!!! pRequest is NULL. TAG=0x%x STATUS=0x%x\n", tag, status)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "38"); + return AGSA_RC_FAILURE; + } + + agContext = saRoot->IOMap[tag].agContext; + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + + ossaSetOperatorCB(agRoot,agContext,status,errorQualifier ); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_ASSERT((pRequest->valid), "pRequest->valid"); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiSetOperatorRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "38"); + + return AGSA_RC_SUCCESS; +} + +/******************************************************************************/ +/*! \brief Get Operator Response + * + * This routine handles the response of the Operator management message + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb Pointer of IOMB Mesage + * + * \return sucess or fail + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiGetOperatorRsp( + agsaRoot_t *agRoot, + agsaGetOperatorRsp_t *pIomb + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaContext_t *agContext; + bit32 Num_Option, NumOperators ,status, tag; + bit8 option, Role = 0; + bit32 IDstr[8]; + bit8 *tmpIDstr = agNULL; + agsaID_t *IDString = agNULL; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"3f"); + + si_memset(&IDstr, 0, sizeof(IDstr)); + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaGetOperatorRsp_t, tag)); + OSSA_READ_LE_32(AGROOT, &status, pIomb, OSSA_OFFSET_OF(agsaGetOperatorRsp_t, status)); + OSSA_READ_LE_32(AGROOT, &Num_Option, pIomb, OSSA_OFFSET_OF(agsaGetOperatorRsp_t, Num_Option)); + OSSA_READ_LE_32(AGROOT, &IDstr[0], pIomb, OSSA_OFFSET_OF(agsaGetOperatorRsp_t, IDString[0])); + OSSA_READ_LE_32(AGROOT, &IDstr[1], pIomb, OSSA_OFFSET_OF(agsaGetOperatorRsp_t, IDString[1])); + OSSA_READ_LE_32(AGROOT, &IDstr[2], pIomb, OSSA_OFFSET_OF(agsaGetOperatorRsp_t, IDString[2])); + OSSA_READ_LE_32(AGROOT, &IDstr[3], pIomb, OSSA_OFFSET_OF(agsaGetOperatorRsp_t, IDString[3])); + OSSA_READ_LE_32(AGROOT, &IDstr[4], pIomb, OSSA_OFFSET_OF(agsaGetOperatorRsp_t, IDString[4])); + OSSA_READ_LE_32(AGROOT, &IDstr[5], pIomb, OSSA_OFFSET_OF(agsaGetOperatorRsp_t, IDString[5])); + OSSA_READ_LE_32(AGROOT, &IDstr[6], pIomb, OSSA_OFFSET_OF(agsaGetOperatorRsp_t, IDString[6])); + OSSA_READ_LE_32(AGROOT, &IDstr[7], pIomb, OSSA_OFFSET_OF(agsaGetOperatorRsp_t, IDString[7])); + + SA_DBG1(("mpiGetOperatorRsp:tag=0x%x status=0x%x Num_Option=0x%x IDString_Role=0x%x\n", + tag, status, Num_Option, IDstr[0])); + + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + SA_DBG1(("mpiGetOperatorRsp: Bad Response IOMB!!! pRequest is NULL. TAG=0x%x STATUS=0x%x\n", tag, status)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "3f"); + return AGSA_RC_FAILURE; + } + + agContext = saRoot->IOMap[tag].agContext; + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + option = Num_Option & 0xFF; + NumOperators = (Num_Option >> SHIFT8) & 0xFF; + /* current operator's Role/ID, valid only if option == 1 */ + if ( option == 1) + { + /* extra the role value as parameter */ + Role = IDstr[0] & 0xFF; + tmpIDstr = (bit8*)&IDstr[0]; + tmpIDstr++; /* skip role byte */ + IDString = (agsaID_t *)tmpIDstr; + SA_DBG1(("mpiGetOperatorRsp: OSSA_IO_SUCCESS\n")); + SA_DBG2(("mpiGetOperatorRsp: 0x%02x 0x%02x 0x%02x 0x%02x\n",IDString->ID[0], IDString->ID[1], IDString->ID[2], IDString->ID[3])); + SA_DBG2(("mpiGetOperatorRsp: 0x%02x 0x%02x 0x%02x 0x%02x\n",IDString->ID[4], IDString->ID[5], IDString->ID[6], IDString->ID[7])); + SA_DBG2(("mpiGetOperatorRsp: 0x%02x 0x%02x 0x%02x 0x%02x\n",IDString->ID[8], IDString->ID[9], IDString->ID[10],IDString->ID[11])); + SA_DBG2(("mpiGetOperatorRsp: 0x%02x 0x%02x 0x%02x 0x%02x\n",IDString->ID[12],IDString->ID[13],IDString->ID[14],IDString->ID[15])); + SA_DBG2(("mpiGetOperatorRsp: 0x%02x 0x%02x 0x%02x 0x%02x\n",IDString->ID[16],IDString->ID[17],IDString->ID[18],IDString->ID[19])); + SA_DBG2(("mpiGetOperatorRsp: 0x%02x 0x%02x 0x%02x 0x%02x\n",IDString->ID[20],IDString->ID[21],IDString->ID[22],IDString->ID[23])); + SA_DBG2(("mpiGetOperatorRsp: 0x%02x 0x%02x 0x%02x 0x%02x\n",IDString->ID[24],IDString->ID[25],IDString->ID[26],IDString->ID[27])); + SA_DBG2(("mpiGetOperatorRsp: 0x%02x 0x%02x 0x%02x\n", IDString->ID[28],IDString->ID[29],IDString->ID[30])); + } + + SA_DBG1(("mpiGetOperatorRsp:status 0x%x option 0x%x Role 0x%x\n",status,option,Role )); + + ossaGetOperatorCB(agRoot,agContext,status,option,NumOperators ,Role,IDString ); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_ASSERT((pRequest->valid), "pRequest->valid"); + pRequest->valid = agFALSE; + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("mpiGetOperatorRsp: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "3f"); + + return AGSA_RC_SUCCESS; +} + + +GLOBAL bit32 mpiGetVHistRsp( + agsaRoot_t *agRoot, + agsaGetVHistCapRsp_t *pIomb + ) +{ + + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = agNULL; + agsaIORequestDesc_t *pRequest; + agsaContext_t *agContext; + + bit32 tag = 0; /* 1 */ + bit32 status = 0; /* 2 */ + bit32 channel; /* 3 */ + bit32 BistLo; /* 4 */ + bit32 BistHi; /* 5 */ + bit32 BytesXfered = 0; /* 6 */ + bit32 PciLo; /* 7 */ + bit32 PciHi; /* 8 */ + bit32 PciBytecount = 0; /* 9 */ + + smTraceFuncEnter(hpDBG_VERY_LOUD,"3K"); + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + SA_ASSERT((agNULL != saRoot), ""); + + if(smIS_SPC12V(agRoot)) + { + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaGetVHistCapRsp_t,tag)); + OSSA_READ_LE_32(AGROOT, &status, pIomb, OSSA_OFFSET_OF(agsaGetVHistCapRsp_t,status)); + OSSA_READ_LE_32(AGROOT, &channel, pIomb, OSSA_OFFSET_OF(agsaGetVHistCapRsp_t,channel)); + OSSA_READ_LE_32(AGROOT, &BistLo, pIomb, OSSA_OFFSET_OF(agsaGetVHistCapRsp_t,BistLo)); + OSSA_READ_LE_32(AGROOT, &BistHi, pIomb, OSSA_OFFSET_OF(agsaGetVHistCapRsp_t,BistHi)); + OSSA_READ_LE_32(AGROOT, &BytesXfered, pIomb, OSSA_OFFSET_OF(agsaGetVHistCapRsp_t,BytesXfered)); + OSSA_READ_LE_32(AGROOT, &PciLo, pIomb, OSSA_OFFSET_OF(agsaGetVHistCapRsp_t,PciLo)); + OSSA_READ_LE_32(AGROOT, &PciHi, pIomb, OSSA_OFFSET_OF(agsaGetVHistCapRsp_t,PciHi)); + OSSA_READ_LE_32(AGROOT, &PciBytecount, pIomb, OSSA_OFFSET_OF(agsaGetVHistCapRsp_t,PciBytecount)); + } + else + { + /* SPC does not support this command */ + SA_DBG1(("mpiGetVHistRsp: smIS_SPC12V only\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "3K"); + return AGSA_RC_FAILURE; + } + + SA_DBG3(("mpiGetVHistRsp: HTag=0x%x\n", tag)); + + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + SA_DBG1(("mpiGetVHistRsp: Bad Response IOMB!!! pRequest is NULL. TAG=0x%x STATUS=0x%x\n", tag, status)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "3K"); + return AGSA_RC_FAILURE; + } + + agContext = saRoot->IOMap[tag].agContext; + + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + SA_ASSERT((pRequest->valid), "pRequest->valid"); + + /* check status success or failure */ + if (status) + { + SA_DBG1(("mpiGetVHistRsp: status is FAILED, status = %x\n", status )); + + if (pRequest->completionCB == agNULL) + { + ossaVhistCaptureCB(agRoot, agContext, status, BytesXfered); + } + else + { + (*(ossaVhistCaptureCB_t)(pRequest->completionCB))(agRoot, agContext, status, BytesXfered); + } + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "3K"); + return AGSA_RC_FAILURE; + } + + /* status is SUCCESS */ + SA_DBG1(("mpiGetVHistRsp: status is SUCCESS\n" )); + + if (pRequest->completionCB == agNULL) + { + ossaVhistCaptureCB(agRoot, agContext, status, BytesXfered); + } + else + { + (*(ossaVhistCaptureCB_t)(pRequest->completionCB))(agRoot, agContext, status, BytesXfered); + } + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "3K"); + + return ret; +} + + + +/******************************************************************************/ +/*! \brief DifEncOffload Response + * + * This routine handles the response of the DifEncOffload Response + * + * \param agRoot Handles for this instance of SAS/SATA LLL + * \param pIomb Pointer of IOMB Mesage + * + * \return sucess or fail + * + */ +/*******************************************************************************/ +GLOBAL bit32 mpiDifEncOffloadRsp( + agsaRoot_t *agRoot, + agsaDifEncOffloadRspV_t *pIomb + ) +{ + + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaContext_t *agContext; + bit32 tag, status; + agsaOffloadDifDetails_t details; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"3F"); + + OSSA_READ_LE_32(AGROOT, &tag, pIomb, OSSA_OFFSET_OF(agsaDifEncOffloadRspV_t, tag)); + OSSA_READ_LE_32(AGROOT, &status, pIomb, OSSA_OFFSET_OF(agsaDifEncOffloadRspV_t, status)); + /* get TAG */ + SA_DBG3(("mpiDifEncOffloadRsp: HTag=0x%x\n", tag)); + + /* get request from IOMap */ + pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; + if (agNULL == pRequest) + { + SA_DBG1(("mpiDifEncOffloadRsp: Bad Response IOMB!!! pRequest is NULL. TAG=0x%x STATUS=0x%x\n", tag, status)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "3F"); + return AGSA_RC_FAILURE; + } + + agContext = saRoot->IOMap[tag].agContext; + + /* remove the request from IOMap */ + saRoot->IOMap[tag].Tag = MARK_OFF; + saRoot->IOMap[tag].IORequest = agNULL; + saRoot->IOMap[tag].agContext = agNULL; + + SA_ASSERT((pRequest->valid), "pRequest->valid"); + + /* check status success or failure */ + if (status) + { + SA_DBG1(("mpiDifEncOffloadRsp: status is FAILED, status = %x\n", status )); + + if (status == OSSA_IO_XFR_ERROR_DIF_MISMATCH || status == OSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH || + status == OSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH || status == OSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH) + { + si_memset(&details, 0, sizeof(agsaOffloadDifDetails_t)); + OSSA_READ_LE_32(AGROOT, &details.ExpectedCRCUDT01, pIomb, OSSA_OFFSET_OF(agsaDifEncOffloadRspV_t, ExpectedCRCUDT01)); + OSSA_READ_LE_32(AGROOT, &details.ExpectedUDT2345, pIomb, OSSA_OFFSET_OF(agsaDifEncOffloadRspV_t, ExpectedUDT2345)); + OSSA_READ_LE_32(AGROOT, &details.ActualCRCUDT01, pIomb, OSSA_OFFSET_OF(agsaDifEncOffloadRspV_t, ActualCRCUDT01)); + OSSA_READ_LE_32(AGROOT, &details.ActualUDT2345, pIomb, OSSA_OFFSET_OF(agsaDifEncOffloadRspV_t, ActualUDT2345)); + OSSA_READ_LE_32(AGROOT, &details.DIFErr, pIomb, OSSA_OFFSET_OF(agsaDifEncOffloadRspV_t, DIFErr)); + OSSA_READ_LE_32(AGROOT, &details.ErrBoffset, pIomb, OSSA_OFFSET_OF(agsaDifEncOffloadRspV_t, ErrBoffset)); + + if (pRequest->completionCB == agNULL) + { + ossaDIFEncryptionOffloadStartCB(agRoot, agContext, status, &details); + } + else + { + (*(ossaDIFEncryptionOffloadStartCB_t)(pRequest->completionCB))(agRoot, agContext, status, &details); + } + } + else + { + if (pRequest->completionCB == agNULL) + { + ossaDIFEncryptionOffloadStartCB(agRoot, agContext, status, agNULL); + } + else + { + (*(ossaDIFEncryptionOffloadStartCB_t)(pRequest->completionCB))(agRoot, agContext, status, agNULL); + } + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "3F"); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + return AGSA_RC_FAILURE; + } + + /* status is SUCCESS */ + SA_DBG1(("mpiDifEncOffloadRsp: status is SUCCESS\n" )); + + if (pRequest->completionCB == agNULL) + { + ossaDIFEncryptionOffloadStartCB(agRoot, agContext, status, agNULL); + } + else + { + (*(ossaDIFEncryptionOffloadStartCB_t)(pRequest->completionCB))(agRoot, agContext, status, agNULL); + } + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* return value */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "3F"); + + return ret; +} + diff --git a/sys/dev/pms/RefTisa/sallsdk/spc/saphy.c b/sys/dev/pms/RefTisa/sallsdk/spc/saphy.c new file mode 100644 index 000000000000..3603129827bb --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/spc/saphy.c @@ -0,0 +1,1302 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +/*******************************************************************************/ +/*! \file saphy.c + * \brief The file implements the functions to Start, Stop a phy + * + * + */ +/******************************************************************************/ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#ifdef SA_ENABLE_TRACE_FUNCTIONS +#ifdef siTraceFileID +#undef siTraceFileID +#endif +#define siTraceFileID 'K' +#endif + + +extern bit32 gFPGA_TEST; +/******************************************************************************/ +/*! \brief Start a Phy + * + * Start a Phy + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param agContext + * \param phyId the phy id of the link will be started + * \param agPhyConfig the phy configuration + * \param agSASIdentify the SAS identify frame will be sent by the phy + * + * \return If phy is started successfully + * - \e AGSA_RC_SUCCESS phy is started successfully + * - \e AGSA_RC_BUSY phy is already started or starting + * - \e AGSA_RC_FAILURE phy is not started successfully + */ +/*******************************************************************************/ +GLOBAL bit32 saPhyStart( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 phyId, + agsaPhyConfig_t *agPhyConfig, + agsaSASIdentify_t *agSASIdentify + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + bit32 ret = AGSA_RC_SUCCESS; + bit32 using_reserved = agFALSE; + + smTraceFuncEnter(hpDBG_VERY_LOUD, "7a"); + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + SA_ASSERT((agNULL != agSASIdentify), ""); + + SA_DBG3(("saPhyStart: phy%d started with ID %08X:%08X\n", + phyId, + SA_IDFRM_GET_SAS_ADDRESSHI(agSASIdentify), + SA_IDFRM_GET_SAS_ADDRESSLO(agSASIdentify))); + + /* If phyId is invalid, return failure */ + if ( phyId >= saRoot->phyCount ) + { + ret = AGSA_RC_FAILURE; + } + /* If phyId is valid */ + else + { + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); /* */ + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeReservedRequests)); + /* If no LL Control request entry available */ + if(agNULL != pRequest) + { + using_reserved = agTRUE; + SA_DBG1(("saPhyStart, using saRoot->freeReservedRequests\n")); + } + else + { + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saPhyStart, No request from free list Not using saRoot->freeReservedRequests\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "7a"); + return AGSA_RC_BUSY; + } + } + SA_ASSERT((!pRequest->valid), "The pRequest is in use"); + pRequest->valid = agTRUE; + /* If LL Control request entry avaliable */ + if( using_reserved ) + { + saLlistIORemove(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* Remove the request from free list */ + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + + /* Build the Phy Start IOMB command and send to SPC */ + + smTrace(hpDBG_VERY_LOUD,"P2", phyId); + /* TP:P2 phyId */ + + ret = mpiPhyStartCmd(agRoot, pRequest->HTag, phyId, agPhyConfig, agSASIdentify, queueNum); + if (AGSA_RC_SUCCESS != ret) + { + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("saPhyStart: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saPhyStart, sending IOMB failed\n" )); + } + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "7a"); + + return ret; +} + +/******************************************************************************/ +/*! \brief Stop a Phy + * + * Stop a Phy + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param agContext the context of this API + * \param phyId the phy id of the link will be stopped + * + * \return If phy is stopped successfully + * - \e AGSA_RC_SUCCESS phy is stopped successfully + * - \e AGSA_RC_FAILURE phy is not stopped successfully + */ +/*******************************************************************************/ +GLOBAL bit32 saPhyStop( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 phyId + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + bit32 ret = AGSA_RC_SUCCESS; + bit32 using_reserved = agFALSE; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"7b"); + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + + SA_DBG2(("saPhyStop: phy%d stop\n", phyId)); + + if(1) + { + mpiOCQueue_t *circularQ; + int i; + SA_DBG4(("saPhyStop:\n")); + for ( i = 0; i < saRoot->QueueConfig.numOutboundQueues; i++ ) + { + circularQ = &saRoot->outboundQueue[i]; + OSSA_READ_LE_32(circularQ->agRoot, &circularQ->producerIdx, circularQ->piPointer, 0); + if(circularQ->producerIdx != circularQ->consumerIdx) + { + SA_DBG1(("saPhyStop: PI 0x%03x CI 0x%03x\n",circularQ->producerIdx, circularQ->consumerIdx )); + } + } + } + + if(smIS_SPC(agRoot)) + { + phyId &= 0xF; + } + /* If phyId is invalid, return failure */ + if ( (phyId & 0xF) >= saRoot->phyCount ) + { + ret = AGSA_RC_FAILURE; + SA_DBG1(("saPhyStop: phy%d - failure with phyId\n", phyId)); + } + else + { + /* If phyId is valid */ + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); /**/ + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeReservedRequests)); + /* If no LL Control request entry available */ + if(agNULL != pRequest) + { + using_reserved = agTRUE; + SA_DBG1(("saPhyStop: using saRoot->freeReservedRequests\n")); + } + else + { + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saPhyStop, No request from free list Not using saRoot->freeReservedRequests\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "7b"); + return AGSA_RC_BUSY; + } + } + /* Remove the request from free list */ + if( using_reserved ) + { + saLlistIORemove(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_ASSERT((!pRequest->valid), "The pRequest is in use"); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + + /* build IOMB command and send to SPC */ + ret = mpiPhyStopCmd(agRoot, pRequest->HTag, phyId, queueNum); + if (AGSA_RC_SUCCESS != ret) + { + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG2(("saPhyStop: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saPhyStop, sending IOMB failed\n" )); + } + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "7b"); + + return ret; +} + +/******************************************************************************/ +/*! \brief CallBack Routine to stop a Phy + * + * CallBack for Stop a Phy + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param phyId the phy id of the link will be stopped + * \param status the status of the phy + * \param agContext the context of the saPhyStop + * + * \return If phy is stopped successfully + * - \e AGSA_RC_SUCCESS phy is stopped successfully + * - \e AGSA_RC_FAILURE phy is not stopped successfully + */ +/*******************************************************************************/ +GLOBAL bit32 siPhyStopCB( + agsaRoot_t *agRoot, + bit32 phyId, + bit32 status, + agsaContext_t *agContext, + bit32 portId, + bit32 npipps + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaPhy_t *pPhy; + agsaPort_t *pPort; + bit32 ret = AGSA_RC_SUCCESS; + bit32 iomb_status = status; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"7c"); + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + + /* If phyId is invalid, return failure */ + if ( phyId >= saRoot->phyCount ) + { + ret = AGSA_RC_FAILURE; + SA_DBG1(("siPhyStopCB: phy%d - failure with phyId\n", phyId)); + /* makeup for CB */ + status = (status << SHIFT8) | phyId; + status |= ((npipps & PORT_STATE_MASK) << SHIFT16); + ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_PHY_STOP_STATUS, status, agContext, agNULL); + } + /* If phyId is valid */ + else + { + pPhy = &(saRoot->phys[phyId]); + + /* get the port of the phy */ + pPort = pPhy->pPort; + + /* makeup for CB */ + status = (status << SHIFT8) | phyId; + status |= ((npipps & PORT_STATE_MASK) << SHIFT16); + /* Callback to stop phy */ + if ( agNULL != pPort ) + { + if ( iomb_status == OSSA_SUCCESS && (OSSA_PORT_INVALID == (npipps & PORT_STATE_MASK) )) + { + SA_DBG1(("siPhyStopCB: phy%d invalidating port\n", phyId)); + /* invalid port state, remove the port */ + pPort->status |= PORT_INVALIDATING; + saRoot->PortMap[portId].PortStatus |= PORT_INVALIDATING; + /* invalid the port */ + siPortInvalid(agRoot, pPort); + /* map out the portmap */ + saRoot->PortMap[pPort->portId].PortContext = agNULL; + saRoot->PortMap[pPort->portId].PortID = PORT_MARK_OFF; + saRoot->PortMap[pPort->portId].PortStatus |= PORT_INVALIDATING; + } + ossaHwCB(agRoot, &(pPort->portContext), OSSA_HW_EVENT_PHY_STOP_STATUS, status, agContext, agNULL); + } + else + { + SA_DBG1(("siPhyStopCB: phy%d - Port is not established\n", phyId)); + ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_PHY_STOP_STATUS, status, agContext, agNULL); + } + + /* set PHY_STOPPED status */ + PHY_STATUS_SET(pPhy, PHY_STOPPED); + + /* Exclude the phy from a port */ + if ( agNULL != pPort ) + { + /* Acquire port list lock */ + ossaSingleThreadedEnter(agRoot, LL_PORT_LOCK); + + /* Delete the phy from the port */ + pPort->phyMap[phyId] = agFALSE; + saRoot->phys[phyId].pPort = agNULL; + + /* Release port list lock */ + ossaSingleThreadedLeave(agRoot, LL_PORT_LOCK); + } + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "7c"); + + /* return */ + return ret; +} + +/******************************************************************************/ +/*! \brief Initiate a Local PHY control command + * + * This function is called to initiate a PHY control command to the local PHY. + * The completion of this function is reported in ossaLocalPhyControlCB() + + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param agContext the context of this API + * \param phyId phy number + * \param phyOperation + * one of AGSA_PHY_LINK_RESET, AGSA_PHY_HARD_RESET, AGSA_PHY_ENABLE_SPINUP + * + * \return + * - none + */ +/*******************************************************************************/ +GLOBAL bit32 saLocalPhyControl( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 phyId, + bit32 phyOperation, + ossaLocalPhyControlCB_t agCB + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaPhyErrCounters_t errorParam; + bit32 ret = AGSA_RC_SUCCESS; + bit32 value, value1, value2, copyPhyId; + bit32 count = 100; + bit32 using_reserved = agFALSE; + + + /* sanity check */ + SA_ASSERT((agNULL != saRoot), ""); + if(saRoot == agNULL) + { + SA_DBG1(("saLocalPhyControl: saRoot == agNULL\n")); + return(AGSA_RC_FAILURE); + } + smTraceFuncEnter(hpDBG_VERY_LOUD,"7d"); + + si_memset(&errorParam,0,sizeof(agsaPhyErrCounters_t)); + SA_DBG2(("saLocalPhyControl: phy%d operation %08X\n", phyId, phyOperation)); + + switch(phyOperation) + { + case AGSA_PHY_LINK_RESET: + case AGSA_PHY_HARD_RESET: + case AGSA_PHY_NOTIFY_ENABLE_SPINUP: + case AGSA_PHY_BROADCAST_ASYNCH_EVENT: + case AGSA_PHY_COMINIT_OOB: + { + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); /**/ + + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeReservedRequests)); + /* If no LL Control request entry available */ + if(agNULL != pRequest) + { + using_reserved = agTRUE; + SA_DBG1(("saLocalPhyControl, using saRoot->freeReservedRequests\n")); + } + else + { + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saLocalPhyControl, No request from free list Not using saRoot->freeReservedRequests\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "7d"); + return AGSA_RC_BUSY; + } + } + if( using_reserved ) + { + saLlistIORemove(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + /* Remove the request from free list */ + SA_ASSERT((!pRequest->valid), "The pRequest is in use"); + pRequest->completionCB = (void*)agCB; + // pRequest->abortCompletionCB = agCB; + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* Build the local phy control IOMB command and send to SPC */ + ret = mpiLocalPhyControlCmd(agRoot, pRequest->HTag, phyId, phyOperation, queueNum); + if (AGSA_RC_SUCCESS != ret) + { + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("saLocalPhyControl: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + SA_DBG1(("saLocalPhyControl, sending IOMB failed\n" )); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + return ret; + } + } + break; + case AGSA_PHY_GET_ERROR_COUNTS: + { + if(smIS_SPCV(agRoot)) + { + + SA_ASSERT((smIS_SPC(agRoot)), "SPC only"); + SA_DBG1(("saLocalPhyControl: V AGSA_PHY_GET_ERROR_COUNTS\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "7d"); + return AGSA_RC_FAILURE; + } + /* If phyId is invalid, return failure */ + if ( phyId >= saRoot->phyCount ) + { + ret = AGSA_RC_FAILURE; + si_memset(&errorParam, 0, sizeof(agsaPhyErrCounters_t)); + SA_DBG1(("saLocalPhyControl: phy%d - failure with phyId\n", phyId)); + /* call back with the status */ + + if( agCB == agNULL ) + { + ossaLocalPhyControlCB(agRoot, agContext, phyId, phyOperation, OSSA_FAILURE, (void *)&errorParam); + } + else + { + agCB(agRoot, agContext, phyId, phyOperation, OSSA_FAILURE, (void *)&errorParam); + } + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "7d"); + return ret; + } + /* save phyId */ + copyPhyId = phyId; + /* map 0x030000 or 0x040000 based on phyId to BAR4(0x20), BAT2(win) to access the register */ + if (phyId < 4) + { + /* for phyId = 0, 1, 2, 3 */ + value = 0x030000; + } + else + { + /* for phyId = 4, 5, 6, 7 */ + phyId = phyId - 4; + value = 0x040000; + } + + /* Need to make sure DEVICE_LCLK_GENERATION register bit 6 is 0 */ + value1 = ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_DEVICE_LCLK); + + SA_DBG3(("saLocalPhyControl: TOP DEVICE LCLK Register value = %08X\n", value1)); + /* If LCLK_CLEAR bit set then disable it */ + if (value1 & DEVICE_LCLK_CLEAR) + { + ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_DEVICE_LCLK, (value1 & 0xFFFFFFBF) ); + SA_DBG3(("saLocalPhyControl: TOP DEVICE LCLK value = %08X\n", (value1 & 0xFFFFFFBF))); + } + + if (AGSA_RC_FAILURE == siBar4Shift(agRoot, value)) + { + SA_DBG1(("saLocalPhyControl:Shift Bar4 to 0x%x failed\n", value)); + phyId = copyPhyId; + /* call back with the status */ + + if( agCB == agNULL ) + { + ossaLocalPhyControlCB(agRoot, agContext, phyId, phyOperation, OSSA_FAILURE, (void *)&errorParam); + } + else + { + agCB(agRoot, agContext, phyId, phyOperation, OSSA_FAILURE, (void *)&errorParam); + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "7d"); + return AGSA_RC_FAILURE; + } + + /* set LCLK = 1 and LCLK_CLEAR = 0 */ + SPC_WRITE_COUNTER_CNTL(phyId, LCLK); + + /* LCLK bit should be low to be able to read error registers */ + while((value = SPC_READ_COUNTER_CNTL(phyId)) & LCLK) + { + if(--count == 0) + { + SA_DBG1(("saLocalPhyControl: Timeout,SPC_COUNTER_CNTL value = %08X\n", value)); + ret = AGSA_RC_FAILURE; + break; + } + } /* while */ + + value = SPC_READ_COUNTER_CNTL(phyId); + SA_DBG3(("saLocalPhyControl: SPC_COUNTER_CNTL value = %08X\n", value)); + + /* invalidDword */ + errorParam.invalidDword = SPC_READ_INV_DW_COUNT(phyId); + /* runningDisparityError */ + errorParam.runningDisparityError = SPC_READ_DISP_ERR_COUNT(phyId); + /* lossOfDwordSynch */ + errorParam.lossOfDwordSynch = SPC_READ_LOSS_DW_COUNT(phyId); + /* phyResetProblem */ + errorParam.phyResetProblem = SPC_READ_PHY_RESET_COUNT(phyId); + /* codeViolation */ + errorParam.codeViolation = SPC_READ_CODE_VIO_COUNT(phyId); + /* never occurred in SPC8x6G */ + errorParam.elasticityBufferOverflow = 0; + errorParam.receivedErrorPrimitive = 0; + errorParam.inboundCRCError = 0; + + SA_DBG3(("saLocalPhyControl:INV_DW_COUNT 0x%x\n", SPC_READ_INV_DW_COUNT(phyId))); + SA_DBG3(("saLocalPhyControl:DISP_ERR_COUNT 0x%x\n", SPC_READ_DISP_ERR_COUNT(phyId))); + SA_DBG3(("saLocalPhyControl:LOSS_DW_COUNT 0x%x\n", SPC_READ_LOSS_DW_COUNT(phyId))); + SA_DBG3(("saLocalPhyControl:PHY_RESET_COUNT 0x%x\n", SPC_READ_PHY_RESET_COUNT(phyId))); + SA_DBG3(("saLocalPhyControl:CODE_VIOLATION_COUNT 0x%x\n", SPC_READ_CODE_VIO_COUNT(phyId))); + + /* Shift back to BAR4 original address */ + if (AGSA_RC_FAILURE == siBar4Shift(agRoot, 0x0)) + { + SA_DBG1(("saLocalPhyControl:Shift Bar4 to 0x%x failed\n", 0x0)); + ret = AGSA_RC_FAILURE; + } + + /* restore back the Top Device LCLK generation register value */ + ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_DEVICE_LCLK, value1); + + /* restore phyId */ + phyId = copyPhyId; + /* call back with the status */ + + if (AGSA_RC_SUCCESS == ret) + { + if( agCB == agNULL ) + { + ossaLocalPhyControlCB(agRoot, agContext, copyPhyId, phyOperation, OSSA_SUCCESS, (void *)&errorParam); + } + else + { + agCB(agRoot, agContext, copyPhyId, phyOperation, OSSA_SUCCESS, (void *)&errorParam); + } + } + else + { + if( agCB == agNULL ) + { + ossaLocalPhyControlCB(agRoot, agContext, phyId, phyOperation, OSSA_FAILURE, (void *)&errorParam); + } + else + { + agCB(agRoot, agContext, phyId, phyOperation, OSSA_FAILURE, (void *)&errorParam); + } + } + break; + } + case AGSA_PHY_CLEAR_ERROR_COUNTS: + { + if(smIS_SPCV(agRoot)) + { + + SA_ASSERT((smIS_SPC(agRoot)), "SPC only"); + SA_DBG1(("saLocalPhyControl: V AGSA_PHY_CLEAR_ERROR_COUNTS\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "7d"); + return AGSA_RC_FAILURE; + } + /* If phyId is invalid, return failure */ + if ( phyId >= saRoot->phyCount ) + { + si_memset(&errorParam, 0, sizeof(agsaPhyErrCountersPage_t)); + SA_DBG3(("saLocalPhyControl(CLEAR): phy%d - failure with phyId\n", phyId)); + /* call back with the status */ + if( agCB == agNULL ) + { + ossaLocalPhyControlCB(agRoot, agContext, phyId, phyOperation, OSSA_FAILURE, (void *)&errorParam); + } + else + { + agCB(agRoot, agContext, phyId, phyOperation, OSSA_FAILURE, (void *)&errorParam); + } + smTraceFuncExit(hpDBG_VERY_LOUD, 'f', "7d"); + return AGSA_RC_FAILURE; + } + /* save phyId */ + copyPhyId = phyId; + /* map 0x030000 or 0x040000 based on phyId to BAR4(0x20), BAT2(win) to access the register */ + if (phyId < 4) + { + /* for phyId = 0, 1, 2, 3 */ + value = 0x030000; + } + else + { + /* for phyId = 4, 5, 6, 7 */ + phyId = phyId - 4; + value = 0x040000; + } + /* Need to make sure DEVICE_LCLK_GENERATION register bit 6 is 1 */ + value2 = ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_DEVICE_LCLK); + + SA_DBG3(("saLocalPhyControl: TOP DEVICE LCLK Register value = %08X\n", value2)); + /* If LCLK_CLEAR bit not set then set it */ + if ((value2 & DEVICE_LCLK_CLEAR) == 0) + { + ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_DEVICE_LCLK, (value2 | DEVICE_LCLK_CLEAR) ); + SA_DBG3(("saLocalPhyControl: TOP DEVICE LCLK value = %08X\n", (value2 & 0xFFFFFFBF))); + } + + if (AGSA_RC_FAILURE == siBar4Shift(agRoot, value)) + { + SA_DBG1(("saLocalPhyControl(CLEAR):Shift Bar4 to 0x%x failed\n", value)); + phyId = copyPhyId; + /* call back with the status */ + if( agCB == agNULL ) + { + ossaLocalPhyControlCB(agRoot, agContext, phyId, phyOperation, OSSA_FAILURE, (void *)&errorParam); + } + else + { + agCB(agRoot, agContext, phyId, phyOperation, OSSA_FAILURE, (void *)&errorParam); + } + smTraceFuncExit(hpDBG_VERY_LOUD, 'g', "7d"); + return AGSA_RC_FAILURE; + } + + /* read Counter Control register */ + value1 = SPC_READ_COUNTER_CNTL(phyId); + SA_DBG3(("saLocalPhyControl(CLEAR): SPC_COUNTER_CNTL value = %08X\n", value1)); + /* set LCLK and LCLK_CLEAR */ + SPC_WRITE_COUNTER_CNTL(phyId, (LCLK_CLEAR | LCLK)); + /* read back the value of register */ + /* poll LCLK bit = 0 */ + while((value = SPC_READ_COUNTER_CNTL(phyId)) & LCLK) + { + if(--count == 0) + { + SA_DBG1(("saLocalPhyControl: Timeout,SPC_COUNTER_CNTL value = %08X\n", value)); + ret = AGSA_RC_FAILURE; + break; + } + } /* while */ + + value = SPC_READ_COUNTER_CNTL(phyId); + SA_DBG3(("saLocalPhyControl(CLEAR): SPC_COUNTER_CNTL value = %08X\n", value)); + + /* restore the value */ + SPC_WRITE_COUNTER_CNTL(phyId, value1); + + /* Shift back to BAR4 original address */ + if (AGSA_RC_FAILURE == siBar4Shift(agRoot, 0x0)) + { + SA_DBG1(("saLocalPhyControl:Shift Bar4 to 0x%x failed\n", 0x0)); + ret = AGSA_RC_FAILURE; + } + + /* restore back the Top Device LCLK generation register value */ + ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_DEVICE_LCLK, value2); + + /* restore phyId */ + phyId = copyPhyId; + /* call back with the status */ + if (AGSA_RC_SUCCESS == ret) + { + if( agCB == agNULL ) + { + ossaLocalPhyControlCB(agRoot, agContext, phyId, phyOperation, OSSA_SUCCESS, agNULL); + } + else + { + agCB(agRoot, agContext, phyId, phyOperation, OSSA_SUCCESS, agNULL); + } + } + else + { + if( agCB == agNULL ) + { + ossaLocalPhyControlCB(agRoot, agContext, phyId, phyOperation, OSSA_FAILURE, (void *)&errorParam); + } + else + { + agCB(agRoot, agContext, phyId, phyOperation, OSSA_FAILURE, (void *)&errorParam); + } + } + break; + } + case AGSA_PHY_GET_BW_COUNTS: + { + SA_ASSERT((smIS_SPC(agRoot)), "SPCv only"); + SA_DBG1(("saLocalPhyControl: AGSA_PHY_GET_BW_COUNTS\n" )); + break; + } + + default: + ret = AGSA_RC_FAILURE; + SA_ASSERT(agFALSE, "(saLocalPhyControl) Unknown operation"); + break; + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'h', "7d"); + return ret; +} + + +GLOBAL bit32 saGetPhyProfile( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 ppc, + bit32 phyId + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + + agsaLLRoot_t *saRoot = agNULL; + agsaPhyErrCountersPage_t errorParam; + + ossaLocalPhyControlCB_t agCB = ossaGetPhyProfileCB; + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + SA_ASSERT((agNULL != saRoot), ""); + + if(saRoot == agNULL) + { + SA_DBG3(("saGetPhyProfile : saRoot is NULL")); + return AGSA_RC_FAILURE; + } + + SA_DBG1(("saGetPhyProfile: ppc 0x%x phyID %d\n", ppc,phyId)); + + switch(ppc) + { + case AGSA_SAS_PHY_ERR_COUNTERS_PAGE: + { + if(smIS_SPCV(agRoot)) + { + + SA_DBG1(("saGetPhyProfile: V AGSA_SAS_PHY_ERR_COUNTERS_PAGE\n" )); + + ret = mpiGetPhyProfileCmd( agRoot,agContext,ppc ,phyId,agCB); + smTraceFuncExit(hpDBG_VERY_LOUD, 'i', "7d"); + return ret; + } + } + case AGSA_SAS_PHY_ERR_COUNTERS_CLR_PAGE: + { + /* If phyId is invalid, return failure */ + if ( phyId >= saRoot->phyCount ) + { + si_memset(&errorParam, 0, sizeof(agsaPhyErrCountersPage_t)); + SA_DBG3(("saGetPhyProfile(CLEAR): phy%d - failure with phyId\n", phyId)); + /* call back with the status */ + ossaGetPhyProfileCB(agRoot, agContext, phyId, ppc, OSSA_FAILURE, (void *)&errorParam); + smTraceFuncExit(hpDBG_VERY_LOUD, 'j', "7d"); + return AGSA_RC_FAILURE; + } + if(smIS_SPCV(agRoot)) + { + SA_DBG1(("saGetPhyProfile: V AGSA_SAS_PHY_ERR_COUNTERS_CLR_PAGE\n" )); + + ret = mpiGetPhyProfileCmd( agRoot,agContext, ppc,phyId,agCB); + smTraceFuncExit(hpDBG_VERY_LOUD, 'k', "7d"); + return ret; + } + + } + case AGSA_SAS_PHY_BW_COUNTERS_PAGE: + { + SA_DBG1(("saGetPhyProfile: AGSA_SAS_PHY_BW_COUNTERS_PAGE\n" )); + ret = mpiGetPhyProfileCmd( agRoot,agContext,ppc ,phyId,agCB); + break; + } + case AGSA_SAS_PHY_ANALOG_SETTINGS_PAGE: + { + SA_DBG1(("saGetPhyProfile: AGSA_SAS_PHY_ANALOG_SETTINGS_PAGE\n" )); + ret = mpiGetPhyProfileCmd( agRoot,agContext,ppc ,phyId,agCB); + break; + } + + case AGSA_SAS_PHY_GENERAL_STATUS_PAGE: + { + SA_DBG1(("saGetPhyProfile: AGSA_SAS_PHY_GENERAL_STATUS_PAGE\n" )); + ret = mpiGetPhyProfileCmd( agRoot,agContext,ppc ,phyId,agCB); + break; + } + case AGSA_PHY_SNW3_PAGE: + { + SA_DBG1(("saGetPhyProfile: AGSA_PHY_SNW3_PAGE\n" )); + ret = mpiGetPhyProfileCmd( agRoot,agContext,ppc ,phyId,agCB); + break; + } + case AGSA_PHY_RATE_CONTROL_PAGE: + { + SA_DBG1(("saGetPhyProfile: AGSA_PHY_RATE_CONTROL_PAGE\n" )); + ret = mpiGetPhyProfileCmd( agRoot,agContext,ppc ,phyId,agCB); + break; + } + case AGSA_SAS_PHY_OPEN_REJECT_RETRY_BACKOFF_THRESHOLD_PAGE: + { + SA_DBG1(("saGetPhyProfile: AGSA_SAS_PHY_OPEN_REJECT_RETRY_BACKOFF_THRESHOLD_PAGE\n" )); + ret = mpiGetPhyProfileCmd( agRoot,agContext,ppc ,phyId,agCB); + break; + } + + default: + SA_DBG1(("saGetPhyProfile: Unknown operation 0x%X\n",ppc )); + SA_ASSERT(agFALSE, "saGetPhyProfile Unknown operation " ); + break; + + } + return ret; + +} + + +GLOBAL bit32 saSetPhyProfile ( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 ppc, + bit32 length, + void *buffer, + bit32 phyID + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + + SA_DBG1(("saSetPhyProfile: ppc 0x%x length 0x%x phyID %d\n", ppc,length,phyID)); + + switch(ppc) + { + case AGSA_SAS_PHY_ANALOG_SETTINGS_PAGE: + { + SA_DBG1(("saSetPhyProfile: AGSA_SAS_PHY_ANALOG_SETTINGS_PAGE\n" )); + ret = mpiSetPhyProfileCmd( agRoot,agContext,ppc ,phyID,length,buffer); + break; + } + case AGSA_PHY_SNW3_PAGE: + { + SA_DBG1(("saSetPhyProfile: AGSA_PHY_SNW3_PAGE\n" )); + ret = mpiSetPhyProfileCmd( agRoot,agContext,ppc ,phyID,length,buffer); + break; + } + case AGSA_PHY_RATE_CONTROL_PAGE: + { + SA_DBG1(("saSetPhyProfile: AGSA_PHY_RATE_CONTROL_PAGE\n" )); + ret = mpiSetPhyProfileCmd( agRoot,agContext,ppc ,phyID,length,buffer); + break; + } + case AGSA_SAS_PHY_MISC_PAGE: + { + SA_DBG1(("saSetPhyProfile: AGSA_SAS_PHY_MISC_PAGE\n")); + ret = mpiSetPhyProfileCmd( agRoot,agContext,ppc ,phyID,length,buffer); + break; + } + + default: + SA_DBG1(("saSetPhyProfile: Unknown operation 0x%X\n",ppc )); + SA_ASSERT(agFALSE, "saSetPhyProfile Unknown operation " ); + ret = AGSA_RC_FAILURE; + break; + } + return ret; +} + + +/******************************************************************************/ +/*! \brief Initiate a HW Event Ack command + * + * This function is called to initiate a HW Event Ack command to the SPC. + * The completion of this function is reported in ossaHwEventAckCB(). + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param agContext the context of this API + * \param queueNum queue number + * \param eventSource point to the event source structure + * \param param0 + * \param param1 + * + * \return + * - none + */ +/*******************************************************************************/ +GLOBAL bit32 saHwEventAck( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaEventSource_t *eventSource, + bit32 param0, + bit32 param1 + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaPortContext_t *agPortContext; + agsaPort_t *pPort = agNULL; + agsaSASHwEventAckCmd_t payload; + bit32 phyportid; + bit32 ret = AGSA_RC_SUCCESS; + bit32 using_reserved = agFALSE; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"7e"); + + /* sanity check */ + SA_ASSERT((agNULL != saRoot), ""); + if(saRoot == agNULL) + { + SA_DBG1(("saHwEventAck: saRoot == agNULL\n")); + return(AGSA_RC_FAILURE); + } + + SA_DBG2(("saHwEventAck: agContext %p eventSource %p\n", agContext, eventSource)); + SA_DBG1(("saHwEventAck: event 0x%x param0 0x%x param1 0x%x\n", eventSource->event, param0, param1)); + + agPortContext = eventSource->agPortContext; + + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); /**/ + + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeReservedRequests)); /**/ + if(agNULL != pRequest) + { + using_reserved = agTRUE; + SA_DBG1(("saHwEventAck, using saRoot->freeReservedRequests\n")); + } + else + { + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* If no LL Control request entry available */ + SA_DBG1(("saHwEventAck, No request from free list Not using saRoot->freeReservedRequests\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "7e"); + return AGSA_RC_BUSY; + } + } + if( using_reserved ) + { + saLlistIORemove(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* Remove the request from free list */ + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_ASSERT((!pRequest->valid), "The pRequest is in use"); + + SA_DBG2(("saHwEventAck: queueNum 0x%x HTag 0x%x\n",queueNum ,pRequest->HTag)); + + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + + /* build IOMB command and send to SPC */ + /* set payload to zeros */ + si_memset(&payload, 0, sizeof(agsaSASHwEventAckCmd_t)); + + /* find port id */ + if (agPortContext) + { + pPort = (agsaPort_t *) (agPortContext->sdkData); + if (pPort) + { + if(eventSource->event == OSSA_HW_EVENT_PHY_DOWN) + { + pPort->tobedeleted = agTRUE; + } + SA_DBG3(("saHwEventAck,pPort->portId %X\n",pPort->portId)); + + if(smIS_SPC(agRoot)) + { + /* fillup PORT_ID field */ + phyportid = pPort->portId & 0xF; + } + else + { + /* fillup PORT_ID field */ + phyportid = pPort->portId & 0xFF; + + } + } + else + { + /* pPort is NULL - set PORT_ID to not intialized */ + if(smIS_SPC(agRoot)) + { + phyportid = 0xF; + } + else + { + phyportid = 0xFF; + } + } + } + else + { + /* agPortContext is NULL - set PORT_ID to not intialized */ + if(smIS_SPC(agRoot)) + { + phyportid = 0xF; + } + else + { + phyportid = 0xFF; + } + } + + pRequest->pPort = pPort; + + SA_DBG3(("saHwEventAck,eventSource->param 0x%X\n",eventSource->param)); + SA_DBG3(("saHwEventAck,eventSource->event 0x%X\n",eventSource->event)); + + if(smIS_SPC(agRoot)) + { + /* fillup up PHY_ID */ + phyportid |= ((eventSource->param & 0x0000000F) << 4); + /* fillup SEA field */ + phyportid |= (eventSource->event & 0x0000FFFF) << 8; + SA_DBG3(("saHwEventAck: portId 0x%x phyId 0x%x SEA 0x%x\n", phyportid & 0xF, + eventSource->param & 0x0000000F, eventSource->event & 0x0000FFFF)); + } + else + { + /* fillup up PHY_ID */ + phyportid |= ((eventSource->param & 0x000000FF) << SHIFT24); + /* fillup SEA field */ + phyportid |= (eventSource->event & 0x00FFFFFF) << SHIFT8; + SA_DBG3(("saHwEventAck: portId 0x%x phyId 0x%x SEA 0x%x\n", phyportid & 0xFF, + eventSource->param & 0x0000000F, eventSource->event & 0x0000FFFF)); + } + + pRequest->HwAckType = (bit16)phyportid; + + SA_DBG1(("saHwEventAck,phyportid 0x%X HwAckType 0x%X\n",phyportid,pRequest->HwAckType)); + /* set tag */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSASHwEventAckCmd_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSASHwEventAckCmd_t, sEaPhyIdPortId), phyportid); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSASHwEventAckCmd_t, Param0), param0); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSASHwEventAckCmd_t, Param1), param1); + + /* build IOMB command and send to SPC */ + + if(smIS_SPC(agRoot)) + { + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_SPC_SAS_HW_EVENT_ACK, IOMB_SIZE64, queueNum); + } + else + { + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_SAS_HW_EVENT_ACK, IOMB_SIZE64, queueNum); + } + + if (AGSA_RC_SUCCESS != ret) + { + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("saHwEventAck: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saHwEventAck, sending IOMB failed\n" )); + } + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "7e"); + + return ret; +} + + +GLOBAL bit32 saVhistCapture( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 Channel, + bit32 NumBitLo, + bit32 NumBitHi, + bit32 PcieAddrLo, + bit32 PcieAddrHi, + bit32 ByteCount ) +{ + + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + bit32 ret = AGSA_RC_SUCCESS; + bit32 using_reserved = agFALSE; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"3N"); + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + + SA_DBG1(("saVhistCapture:Channel 0x%08X 0x%08X%08X 0x%08X%08X count 0x%X\n",Channel, NumBitHi, NumBitLo ,PcieAddrHi,PcieAddrLo,ByteCount)); + + { + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); /* */ + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeReservedRequests)); + /* If no LL Control request entry available */ + if(agNULL != pRequest) + { + using_reserved = agTRUE; + SA_DBG1((", using saRoot->freeReservedRequests\n")); + } + else + { + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saVhistCapture: No request from free list Not using saRoot->freeReservedRequests\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "3N"); + return AGSA_RC_BUSY; + } + } + SA_ASSERT((!pRequest->valid), "The pRequest is in use"); + pRequest->valid = agTRUE; + /* If LL Control request entry avaliable */ + if( using_reserved ) + { + saLlistIORemove(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* Remove the request from free list */ + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + + /* Build the VhisCapture IOMB command and send to SPCv */ + + ret = mpiVHistCapCmd(agRoot,agContext, queueNum, Channel, NumBitLo, NumBitHi ,PcieAddrLo, PcieAddrHi, ByteCount); + if (AGSA_RC_SUCCESS != ret) + { + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("saPhyStart: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saVhistCapture: sending IOMB failed\n" )); + } + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "3N"); + + return ret; +} + diff --git a/sys/dev/pms/RefTisa/sallsdk/spc/saport.c b/sys/dev/pms/RefTisa/sallsdk/spc/saport.c new file mode 100644 index 000000000000..9238741657d5 --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/spc/saport.c @@ -0,0 +1,1423 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +/*******************************************************************************/ +/*! \file saport.c + * \brief The file implements the functions to handle port + * + */ +/******************************************************************************/ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#ifdef SA_ENABLE_TRACE_FUNCTIONS +#ifdef siTraceFileID +#undef siTraceFileID +#endif +#define siTraceFileID 'L' +#endif + + +extern bit32 gFPGA_TEST; +/******************************************************************************/ +/*! \brief Add a SAS device to the discovery list of the port + * + * Add a SAS device from the discovery list of the port + * + * \param agRoot handles for this instance of SAS/SATA LLL + * \param pPort + * \param sasIdentify + * \param sasInitiator + * \param smpTimeout + * \param itNexusTimeout + * \param firstBurstSize + * \param dTypeSRate -- device type and link rate + * \param flag + * + * \return -the device descriptor- + */ +/*******************************************************************************/ +GLOBAL agsaDeviceDesc_t *siPortSASDeviceAdd( + agsaRoot_t *agRoot, + agsaPort_t *pPort, + agsaSASIdentify_t sasIdentify, + bit32 sasInitiator, + bit32 smpTimeout, + bit32 itNexusTimeout, + bit32 firstBurstSize, + bit8 dTypeSRate, + bit32 flag + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaDeviceDesc_t *pDevice; + + SA_DBG3(("siPortSASDeviceAdd: start\n")); + + smTraceFuncEnter(hpDBG_VERY_LOUD, "23"); + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + SA_ASSERT((agNULL != pPort), ""); + + /* Acquire Device Lock */ + ossaSingleThreadedEnter(agRoot, LL_DEVICE_LOCK); + + /* Try to Allocate from device list */ + pDevice = (agsaDeviceDesc_t *) saLlistGetHead(&(saRoot->freeDevicesList)); + + /* If device handle available */ + if ( agNULL != pDevice) + { + int i; + + /* Remove from free device list */ + saLlistRemove(&(saRoot->freeDevicesList), &(pDevice->linkNode)); + + /* Initialize device descriptor */ + if ( agTRUE == sasInitiator ) + { + pDevice->initiatorDevHandle.sdkData = pDevice; + pDevice->targetDevHandle.sdkData = agNULL; + } + else + { + pDevice->initiatorDevHandle.sdkData = agNULL; + pDevice->targetDevHandle.sdkData = pDevice; + } + + pDevice->initiatorDevHandle.osData = agNULL; + pDevice->targetDevHandle.osData = agNULL; + + /* setup device type */ + pDevice->deviceType = (bit8)((dTypeSRate & 0x30) >> SHIFT4); + SA_DBG3(("siPortSASDeviceAdd: Device Type 0x%x, Port Context %p\n", pDevice->deviceType, pPort)); + pDevice->pPort = pPort; + saLlistInitialize(&(pDevice->pendingIORequests)); + + /* setup sasDeviceInfo */ + pDevice->devInfo.sasDeviceInfo.commonDevInfo.smpTimeout = (bit16)smpTimeout; + pDevice->devInfo.sasDeviceInfo.commonDevInfo.it_NexusTimeout = (bit16)itNexusTimeout; + pDevice->devInfo.sasDeviceInfo.commonDevInfo.firstBurstSize = (bit16)firstBurstSize; + pDevice->devInfo.sasDeviceInfo.commonDevInfo.devType_S_Rate = dTypeSRate; + pDevice->devInfo.sasDeviceInfo.commonDevInfo.flag = flag; + for (i = 0; i < 4; i++) + { + pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressHi[i] = sasIdentify.sasAddressHi[i]; + pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressLo[i] = sasIdentify.sasAddressLo[i]; + } + pDevice->devInfo.sasDeviceInfo.initiator_ssp_stp_smp = sasIdentify.initiator_ssp_stp_smp; + pDevice->devInfo.sasDeviceInfo.target_ssp_stp_smp = sasIdentify.target_ssp_stp_smp; + pDevice->devInfo.sasDeviceInfo.phyIdentifier = sasIdentify.phyIdentifier; + + /* Add to discoverd device for the port */ + saLlistAdd(&(pPort->listSASATADevices), &(pDevice->linkNode)); + + /* Release Device Lock */ + ossaSingleThreadedLeave(agRoot, LL_DEVICE_LOCK); + + /* Log Messages */ + SA_DBG3(("siPortSASDeviceAdd: sasIdentify addrHI 0x%x\n", SA_IDFRM_GET_SAS_ADDRESSHI(&sasIdentify))); + SA_DBG3(("siPortSASDeviceAdd: sasIdentify addrLO 0x%x\n", SA_IDFRM_GET_SAS_ADDRESSLO(&sasIdentify))); + + } + else + { + /* Release Device Lock */ + ossaSingleThreadedLeave(agRoot, LL_DEVICE_LOCK); + SA_ASSERT((agNULL != pDevice), ""); + SA_DBG1(("siPortSASDeviceAdd: device allocation failed\n")); + } + SA_DBG3(("siPortSASDeviceAdd: end\n")); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "23"); + return pDevice; +} + +/******************************************************************************/ +/*! \brief The function to remove a device descriptor + * + * The function to remove a device descriptor + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param pPort The pointer to the port + * \param pDevice The pointer to the device + * + * \return -void- + */ +/*******************************************************************************/ +GLOBAL void siPortDeviceRemove( + agsaRoot_t *agRoot, + agsaPort_t *pPort, + agsaDeviceDesc_t *pDevice, + bit32 unmap + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + bit32 deviceIdx; + + smTraceFuncEnter(hpDBG_VERY_LOUD, "24"); + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + SA_ASSERT((agNULL != pPort), ""); + SA_ASSERT((agNULL != pDevice), ""); + SA_ASSERT((SAS_SATA_UNKNOWN_DEVICE != pDevice->deviceType), ""); + + /* remove the device from discovered list */ + SA_DBG3(("siPortDeviceRemove(SAS/SATA): DeviceIndex %d Device Context %p\n", pDevice->DeviceMapIndex, pDevice)); + + ossaSingleThreadedEnter(agRoot, LL_DEVICE_LOCK); + saLlistRemove(&(pPort->listSASATADevices), &(pDevice->linkNode)); + + /* Reset the device data structure */ + pDevice->pPort = agNULL; + pDevice->initiatorDevHandle.osData = agNULL; + pDevice->initiatorDevHandle.sdkData = agNULL; + pDevice->targetDevHandle.osData = agNULL; + pDevice->targetDevHandle.sdkData = agNULL; + + saLlistAdd(&(saRoot->freeDevicesList), &(pDevice->linkNode)); + + if(unmap) + { + /* remove the DeviceMap and MapIndex */ + deviceIdx = pDevice->DeviceMapIndex & DEVICE_ID_BITS; + OS_ASSERT(deviceIdx < MAX_IO_DEVICE_ENTRIES, "deviceIdx MAX_IO_DEVICE_ENTRIES"); + + saRoot->DeviceMap[deviceIdx].DeviceIdFromFW = 0; + saRoot->DeviceMap[deviceIdx].DeviceHandle = agNULL; + pDevice->DeviceMapIndex = 0; + } + ossaSingleThreadedLeave(agRoot, LL_DEVICE_LOCK); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "24"); + + return; +} + +/******************************************************************************/ +/*! \brief Add a SATA device to the discovery list of the port + * + * Add a SATA device from the discovery list of the port + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param pPort + * \param pSTPBridge + * \param pSignature + * \param pm + * \param pmField + * \param smpReqTimeout + * \param itNexusTimeout + * \param firstBurstSize + * \param dTypeSRate + * + * \return -the device descriptor- + */ +/*******************************************************************************/ +GLOBAL agsaDeviceDesc_t *siPortSATADeviceAdd( + agsaRoot_t *agRoot, + agsaPort_t *pPort, + agsaDeviceDesc_t *pSTPBridge, + bit8 *pSignature, + bit8 pm, + bit8 pmField, + bit32 smpReqTimeout, + bit32 itNexusTimeout, + bit32 firstBurstSize, + bit8 dTypeSRate, + bit32 flag + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaDeviceDesc_t *pDevice; + + smTraceFuncEnter(hpDBG_VERY_LOUD, "25"); + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + SA_ASSERT((agNULL != pPort), ""); + + /* Acquire Device Lock */ + ossaSingleThreadedEnter(agRoot, LL_DEVICE_LOCK); + + /* Try to Allocate from device list */ + pDevice = (agsaDeviceDesc_t *) saLlistGetHead(&(saRoot->freeDevicesList)); + + /* If device handle available */ + if ( agNULL != pDevice) + { + int i; + + /* Remove from free device list */ + saLlistRemove(&(saRoot->freeDevicesList), &(pDevice->linkNode)); + + /* Initialize the device descriptor */ + pDevice->initiatorDevHandle.sdkData = agNULL; + pDevice->targetDevHandle.sdkData = pDevice; + pDevice->initiatorDevHandle.osData = agNULL; + pDevice->targetDevHandle.osData = agNULL; + + pDevice->deviceType = (bit8)((dTypeSRate & 0x30) >> SHIFT4); + SA_DBG3(("siPortSATADeviceAdd: DeviceType 0x%x Port Context %p\n", pDevice->deviceType, pPort)); + + /* setup device common infomation */ + pDevice->devInfo.sataDeviceInfo.commonDevInfo.smpTimeout = (bit16)smpReqTimeout; + pDevice->devInfo.sataDeviceInfo.commonDevInfo.it_NexusTimeout = (bit16)itNexusTimeout; + pDevice->devInfo.sataDeviceInfo.commonDevInfo.firstBurstSize = (bit16)firstBurstSize; + pDevice->devInfo.sataDeviceInfo.commonDevInfo.devType_S_Rate = dTypeSRate; + pDevice->devInfo.sataDeviceInfo.commonDevInfo.flag = flag; + for (i = 0; i < 4; i++) + { + pDevice->devInfo.sataDeviceInfo.commonDevInfo.sasAddressHi[i] = 0; + pDevice->devInfo.sataDeviceInfo.commonDevInfo.sasAddressLo[i] = 0; + } + /* setup SATA device information */ + pDevice->devInfo.sataDeviceInfo.connection = pm; + pDevice->devInfo.sataDeviceInfo.portMultiplierField = pmField; + pDevice->devInfo.sataDeviceInfo.stpPhyIdentifier = 0; + pDevice->pPort = pPort; + + /* Add to discoverd device for the port */ + saLlistAdd(&(pPort->listSASATADevices), &(pDevice->linkNode)); + + /* Release Device Lock */ + ossaSingleThreadedLeave(agRoot, LL_DEVICE_LOCK); + } + else + { + /* Release Device Lock */ + ossaSingleThreadedLeave(agRoot, LL_DEVICE_LOCK); + SA_ASSERT((agNULL != pDevice), ""); + SA_DBG1(("siPortSATADeviceAdd: device allocation failed\n")); + } + SA_DBG3(("siPortSATADeviceAdd: end\n")); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "25"); + return pDevice; +} + +/******************************************************************************/ +/*! \brief Invalid a port + * + * Invalid a port + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param pPort + * + * \return -void- + */ +/*******************************************************************************/ +GLOBAL void siPortInvalid( + agsaRoot_t *agRoot, + agsaPort_t *pPort + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + smTraceFuncEnter(hpDBG_VERY_LOUD, "26"); + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + SA_ASSERT((agNULL != pPort), ""); + + /* set port's status to invalidating */ + pPort->status |= PORT_INVALIDATING; + + /* Remove from validPort and add the port back to the free port link list */ + ossaSingleThreadedEnter(agRoot, LL_PORT_LOCK); + saLlistRemove(&(saRoot->validPorts), &(pPort->linkNode)); + saLlistAdd(&(saRoot->freePorts), &(pPort->linkNode)); + pPort->tobedeleted = agFALSE; + ossaSingleThreadedLeave(agRoot, LL_PORT_LOCK); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "26"); + + /* return */ +} + +/******************************************************************************/ +/*! \brief The function to remove a device descriptor + * + * The function to remove a device descriptor + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param pPort The pointer to the port + * \param pDevice The pointer to the device + * + * \return -void- + */ +/*******************************************************************************/ +GLOBAL void siPortDeviceListRemove( + agsaRoot_t *agRoot, + agsaPort_t *pPort, + agsaDeviceDesc_t *pDevice + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + + smTraceFuncEnter(hpDBG_VERY_LOUD, "27"); + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + SA_ASSERT((agNULL != pPort), ""); + SA_ASSERT((agNULL != pDevice), ""); + SA_ASSERT((SAS_SATA_UNKNOWN_DEVICE != pDevice->deviceType), ""); + + /* remove the device from discovered list */ + SA_DBG3(("siPortDeviceListRemove(SAS/SATA): PortID %d Device Context %p\n", pPort->portId, pDevice)); + + ossaSingleThreadedEnter(agRoot, LL_DEVICE_LOCK); + saLlistRemove(&(pPort->listSASATADevices), &(pDevice->linkNode)); + + /* Reset the device data structure */ + pDevice->pPort = agNULL; + pDevice->initiatorDevHandle.osData = agNULL; + pDevice->initiatorDevHandle.sdkData = agNULL; + pDevice->targetDevHandle.osData = agNULL; + pDevice->targetDevHandle.sdkData = agNULL; + + saLlistAdd(&(saRoot->freeDevicesList), &(pDevice->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_DEVICE_LOCK); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "27"); + return; +} + +/******************************************************************************/ +/*! \brief Initiate a Port COntrol IOMB command + * + * This function is called to initiate a Port COntrol command to the SPC. + * The completion of this function is reported in ossaPortControlCB(). + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param agContext the context of this API + * \param queueNum queue number + * \param agPortContext point to the event source structure + * \param param0 parameter 0 + * \param param1 parameter 1 + * + * \return - successful or failure + */ +/*******************************************************************************/ +GLOBAL bit32 saPortControl( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaPortContext_t *agPortContext, + bit32 portOperation, + bit32 param0, + bit32 param1 + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaPort_t *pPort; + bit32 ret = AGSA_RC_SUCCESS; + bit32 opportId; + agsaPortControlCmd_t payload; + bit32 using_reserved = agFALSE; + + + /* sanity check */ + SA_ASSERT((agNULL !=saRoot ), ""); + SA_ASSERT((agNULL != agPortContext), ""); + if(saRoot == agNULL) + { + SA_DBG1(("saPortControl: saRoot == agNULL\n")); + return(AGSA_RC_FAILURE); + } + smTraceFuncEnter(hpDBG_VERY_LOUD, "28"); + + SA_DBG1(("saPortControl: portContext %p portOperation 0x%x param0 0x%x param1 0x%x\n", agPortContext, portOperation, param0, param1)); + + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); /**/ + /* If no LL Control request entry available */ + if ( agNULL == pRequest ) + { + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeReservedRequests)); + /* If no LL Control request entry available */ + if(agNULL != pRequest) + { + using_reserved = agTRUE; + SA_DBG2(("saPortControl, using saRoot->freeReservedRequests\n")); + } + else + { + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saPortControl, No request from free list Not using saRoot->freeReservedRequests\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "28"); + return AGSA_RC_BUSY; + } + } + + /* If LL Control request entry avaliable */ + if( using_reserved ) + { + saLlistIORemove(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* Remove the request from free list */ + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + SA_ASSERT((!pRequest->valid), "The pRequest is in use"); + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + saRoot->IOMap[pRequest->HTag].agContext = agContext; + pRequest->valid = agTRUE; + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* build IOMB command and send to SPC */ + /* set payload to zeros */ + si_memset(&payload, 0, sizeof(agsaPortControlCmd_t)); + + /* find port id */ + pPort = (agsaPort_t *) (agPortContext->sdkData); + opportId = (pPort->portId & PORTID_MASK) | (portOperation << SHIFT8); + /* set tag */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaPortControlCmd_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaPortControlCmd_t, portOPPortId), opportId); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaPortControlCmd_t, Param0), param0); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaPortControlCmd_t, Param1), param1); + + SA_DBG1(("saPortControl: portId 0x%x portOperation 0x%x\n", (pPort->portId & PORTID_MASK),portOperation)); + + /* build IOMB command and send to SPC */ + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_PORT_CONTROL, IOMB_SIZE64, queueNum); + if (AGSA_RC_SUCCESS != ret) + { + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + pRequest->valid = agFALSE; + /* return the request to free pool */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + if (saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("saPortControl: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saPortControl, sending IOMB failed\n" )); + } + else + { + if (portOperation == AGSA_PORT_HARD_RESET) + { + SA_DBG1(("saPortControl,0x%x AGSA_PORT_HARD_RESET 0x%x param0 0x%x\n", + pPort->portId, param0, param0 & AUTO_HARD_RESET_DEREG_FLAG)); + saRoot->autoDeregDeviceflag[pPort->portId & PORTID_MASK] = param0 & AUTO_HARD_RESET_DEREG_FLAG; + } + else if (portOperation == AGSA_PORT_CLEAN_UP) + { + SA_DBG1(("saPortControl, 0x%x AGSA_PORT_CLEAN_UP param0 0x%x %d\n", pPort->portId, param0,((param0 & AUTO_FW_CLEANUP_DEREG_FLAG) ? 0:1))); + saRoot->autoDeregDeviceflag[pPort->portId & PORTID_MASK] = ((param0 & AUTO_FW_CLEANUP_DEREG_FLAG) ? 0:1); + } + SA_DBG1(("saPortControl, sending IOMB SUCCESS, portId 0x%x autoDeregDeviceflag=0x%x\n", pPort->portId,saRoot->autoDeregDeviceflag[pPort->portId & PORTID_MASK])); + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "28"); + + return ret; +} + +/** + * saEncryptGetMode() + * + * Returns the status, working state and sector size + * registers of the encryption engine + * + * @param saRoot + * @param encryptInfo + * + * @return + */ +GLOBAL bit32 saEncryptGetMode(agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaEncryptInfo_t *encryptInfo) +{ + bit32 ret = AGSA_RC_NOT_SUPPORTED; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"29"); + agContext = agContext; /* Lint*/ + SA_DBG4(("saEncryptGetMode, encryptInfo %p\n",encryptInfo )); + if(smIS_SPCV(agRoot)) + { + bit32 ScratchPad1 =0; + bit32 ScratchPad3 =0; + + encryptInfo->status = 0; + encryptInfo->encryptionCipherMode = 0; + encryptInfo->encryptionSecurityMode = 0; + encryptInfo->flag = 0; + + ScratchPad1 = ossaHwRegRead(agRoot,V_Scratchpad_1_Register); + ScratchPad3 = ossaHwRegRead(agRoot,V_Scratchpad_3_Register); + if((ScratchPad1 & SCRATCH_PAD1_V_RAAE_MASK) == SCRATCH_PAD1_V_RAAE_MASK) + { + if((ScratchPad3 & SCRATCH_PAD3_V_ENC_MASK) == SCRATCH_PAD3_V_ENC_READY ) /* 3 */ + { + if( ScratchPad3 & SCRATCH_PAD3_V_XTS_ENABLED) + { + encryptInfo->encryptionCipherMode = agsaEncryptCipherModeXTS; + } + if( (ScratchPad3 & SCRATCH_PAD3_V_SM_MASK ) == SCRATCH_PAD3_V_SMF_ENABLED ) + { + encryptInfo->encryptionSecurityMode = agsaEncryptSMF; + } + if( (ScratchPad3 & SCRATCH_PAD3_V_SM_MASK ) == SCRATCH_PAD3_V_SMA_ENABLED) + { + encryptInfo->encryptionSecurityMode = agsaEncryptSMA; + } + if( (ScratchPad3 & SCRATCH_PAD3_V_SM_MASK ) == SCRATCH_PAD3_V_SMB_ENABLED ) + { + encryptInfo->encryptionSecurityMode = agsaEncryptSMB; + } + encryptInfo->status = AGSA_RC_SUCCESS; + ret = AGSA_RC_SUCCESS; + } + else if((ScratchPad3 & SCRATCH_PAD3_V_ENC_READY) == SCRATCH_PAD3_V_ENC_DISABLED) /* 0 */ + { + SA_DBG1(("saEncryptGetMode, SCRATCH_PAD3_V_ENC_DISABLED 1 0x%08X 3 0x%08X\n",ScratchPad1,ScratchPad3 )); + encryptInfo->status = 0xFFFF; + encryptInfo->encryptionCipherMode = 0; + encryptInfo->encryptionSecurityMode = 0; + ret = AGSA_RC_NOT_SUPPORTED; + } + else if((ScratchPad3 & SCRATCH_PAD3_V_ENC_MASK ) == SCRATCH_PAD3_V_ENC_DIS_ERR) /* 1 */ + { + SA_DBG1(("saEncryptGetMode, SCRATCH_PAD3_V_ENC_DIS_ERR 1 0x%08X 3 0x%08X\n",ScratchPad1,ScratchPad3 )); + encryptInfo->status = (ScratchPad3 & SCRATCH_PAD3_V_ERR_CODE ) >> SHIFT16; + if( ScratchPad3 & SCRATCH_PAD3_V_XTS_ENABLED) + { + encryptInfo->encryptionCipherMode = agsaEncryptCipherModeXTS; + } + if( (ScratchPad3 & SCRATCH_PAD3_V_SM_MASK ) == SCRATCH_PAD3_V_SMF_ENABLED ) + { + encryptInfo->encryptionSecurityMode = agsaEncryptSMF; + } + if( (ScratchPad3 & SCRATCH_PAD3_V_SM_MASK ) == SCRATCH_PAD3_V_SMA_ENABLED) + { + encryptInfo->encryptionSecurityMode = agsaEncryptSMA; + } + if( (ScratchPad3 & SCRATCH_PAD3_V_SM_MASK ) == SCRATCH_PAD3_V_SMB_ENABLED ) + { + encryptInfo->encryptionSecurityMode = agsaEncryptSMB; + } + ret = AGSA_RC_FAILURE; + } + else if((ScratchPad3 & SCRATCH_PAD3_V_ENC_MASK ) == SCRATCH_PAD3_V_ENC_ENA_ERR) /* 2 */ + { + + SA_DBG1(("saEncryptGetMode, SCRATCH_PAD3_V_ENC_ENA_ERR 1 0x%08X 3 0x%08X\n",ScratchPad1,ScratchPad3 )); + encryptInfo->status = (ScratchPad3 & SCRATCH_PAD3_V_ERR_CODE ) >> SHIFT16; + if( ScratchPad3 & SCRATCH_PAD3_V_XTS_ENABLED) + { + encryptInfo->encryptionCipherMode = agsaEncryptCipherModeXTS; + SA_DBG1(("saEncryptGetMode, SCRATCH_PAD3_V_ENC_ENA_ERR 2 0x%08X 3 0x%08X\n",ScratchPad1,ScratchPad3 )); + } + if( (ScratchPad3 & SCRATCH_PAD3_V_SM_MASK ) == SCRATCH_PAD3_V_SMF_ENABLED ) + { + SA_DBG1(("saEncryptGetMode, SCRATCH_PAD3_V_ENC_ENA_ERR 3 0x%08X 3 0x%08X\n",ScratchPad1,ScratchPad3 )); + encryptInfo->encryptionSecurityMode = agsaEncryptSMF; + } + if( (ScratchPad3 & SCRATCH_PAD3_V_SM_MASK ) == SCRATCH_PAD3_V_SMA_ENABLED) + { + encryptInfo->encryptionSecurityMode = agsaEncryptSMA; + } + if( (ScratchPad3 & SCRATCH_PAD3_V_SM_MASK ) == SCRATCH_PAD3_V_SMB_ENABLED ) + { + encryptInfo->encryptionSecurityMode = agsaEncryptSMB; + } + + SA_DBG1(("saEncryptGetMode,encryptInfo status 0x%08X CipherMode 0x%X SecurityMode 0x%X\n" , + encryptInfo->status, + encryptInfo->encryptionCipherMode, + encryptInfo->encryptionSecurityMode)); + +#ifdef CCFLAGS_SPCV_FPGA_REVB /*The FPGA platform hasn't EEPROM*/ + ret = AGSA_RC_SUCCESS; +#else + ret = AGSA_RC_FAILURE; +#endif + } + } + else if((ScratchPad1 & SCRATCH_PAD1_V_RAAE_MASK) == SCRATCH_PAD1_V_RAAE_ERR) + { + SA_DBG1(("saEncryptGetMode, SCRATCH_PAD1_V_RAAE_ERR 1 0x%08X 3 0x%08X\n",ScratchPad1,ScratchPad3 )); + ret = AGSA_RC_FAILURE; + } + else if((ScratchPad1 & SCRATCH_PAD1_V_RAAE_MASK) == 0x0 ) + { + SA_DBG1(("saEncryptGetMode, RAAE not ready AGSA_RC_BUSY 1 0x%08X 3 0x%08X\n",ScratchPad1,ScratchPad3 )); + ret = AGSA_RC_BUSY; + } + if(ScratchPad3 & SCRATCH_PAD3_V_AUT) + { + encryptInfo->flag |= OperatorAuthenticationEnable_AUT; + } + if(ScratchPad3 & SCRATCH_PAD3_V_ARF) + { + encryptInfo->flag |= ReturnToFactoryMode_ARF; + } + + SA_DBG2(("saEncryptGetMode, encryptionCipherMode 0x%x encryptionSecurityMode 0x%x flag 0x%x status 0x%x\n", + encryptInfo->encryptionCipherMode, + encryptInfo->encryptionSecurityMode, + encryptInfo->flag, + encryptInfo->status)); + SA_DBG2(("saEncryptGetMode, ScratchPad3 0x%x returns 0x%x\n",ScratchPad3, ret)); + + } + else + { + SA_DBG1(("saEncryptGetMode, SPC AGSA_RC_NOT_SUPPORTED\n")); + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "29"); + return ret; +} + +/**/ +GLOBAL bit32 saEncryptSetMode ( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + agsaEncryptInfo_t *mode + ) + +{ + bit32 ret = AGSA_RC_NOT_SUPPORTED; + agsaSetControllerConfigCmd_t agControllerConfig; + agsaSetControllerConfigCmd_t *pagControllerConfig = &agControllerConfig; + bit32 smode = 0; + + if(smIS_SPCV(agRoot)) + { + bit32 ScratchPad1 =0; + + ScratchPad1 = ossaHwRegRead(agRoot,V_Scratchpad_1_Register); + if((ScratchPad1 & SCRATCH_PAD1_V_RAAE_MASK) == SCRATCH_PAD1_V_RAAE_MASK) + { + si_memset(pagControllerConfig,0,sizeof(agsaSetControllerConfigCmd_t)); + + SA_DBG2(("saEncryptSetMode, encryptionCipherMode 0x%x encryptionSecurityMode 0x%x status 0x%x\n", + mode->encryptionCipherMode, + mode->encryptionSecurityMode, + mode->status + )); + + smode = mode->encryptionSecurityMode; + + if( mode->encryptionCipherMode & agsaEncryptCipherModeXTS) + { + smode |= 1 << SHIFT22; + } + + + pagControllerConfig->pageCode = AGSA_ENCRYPTION_CONTROL_PARM_PAGE | smode; + pagControllerConfig->tag =0; + + SA_DBG2(("saEncryptSetMode,tag 0x%x pageCode 0x%x\n", + pagControllerConfig->tag, + pagControllerConfig->pageCode + )); + + SA_DBG2(("saEncryptSetMode, 0x%x 0x%x 0x%x 0x%x\n", + pagControllerConfig->configPage[0], + pagControllerConfig->configPage[1], + pagControllerConfig->configPage[2], + pagControllerConfig->configPage[3] + )); + + SA_DBG2(("saEncryptSetMode, 0x%x 0x%x 0x%x 0x%x\n", + pagControllerConfig->configPage[4], + pagControllerConfig->configPage[5], + pagControllerConfig->configPage[6], + pagControllerConfig->configPage[7] + )); + + SA_DBG2(("saEncryptSetMode, 0x%x 0x%x 0x%x 0x%x\n", + pagControllerConfig->configPage[8], + pagControllerConfig->configPage[9], + pagControllerConfig->configPage[10], + pagControllerConfig->configPage[11] + )); + + ret = mpiSetControllerConfigCmd(agRoot,agContext,pagControllerConfig,queueNum,agTRUE); + + SA_DBG2(("saEncryptSetMode, pageCode 0x%x tag 0x%x status 0x%x\n", + pagControllerConfig->pageCode, + pagControllerConfig->tag, + ret + )); + } + else + { + SA_DBG2(("saEncryptSetMode,ScratchPad1 not ready %08X\n",ScratchPad1 )); + ret = AGSA_RC_BUSY; + } + + } + return ret; +} + + + +/** + * saEncryptKekUpdate() + * + * Replace a KEK within the controller + * + * @param saRoot + * @param flags + * @param newKekIndex + * @param wrapperKekIndex + * @param encryptKekBlob + * + * @return + */ +GLOBAL bit32 saEncryptKekUpdate( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 flags, + bit32 newKekIndex, + bit32 wrapperKekIndex, + bit32 blobFormat, + agsaEncryptKekBlob_t *encryptKekBlob + ) +{ + agsaKekManagementCmd_t payload; + bit32 ret, i; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"30"); + + SA_DBG2(("saEncryptKekUpdate, flags 0x%x newKekIndex 0x%x wrapperKekIndex 0x%x encryptKekBlob %p\n",flags,newKekIndex,wrapperKekIndex,encryptKekBlob)); + SA_DBG2(("saEncryptKekUpdate, 0x%02X%02X%02X%02X 0x%02X%02X%02X%02X\n", + encryptKekBlob->kekBlob[0],encryptKekBlob->kekBlob[1], + encryptKekBlob->kekBlob[2],encryptKekBlob->kekBlob[3], + encryptKekBlob->kekBlob[4],encryptKekBlob->kekBlob[5], + encryptKekBlob->kekBlob[6],encryptKekBlob->kekBlob[7])); + SA_DBG2(("saEncryptKekUpdate, 0x%02X%02X%02X%02X 0x%02X%02X%02X%02X\n", + encryptKekBlob->kekBlob[ 8],encryptKekBlob->kekBlob[ 9], + encryptKekBlob->kekBlob[10],encryptKekBlob->kekBlob[11], + encryptKekBlob->kekBlob[12],encryptKekBlob->kekBlob[13], + encryptKekBlob->kekBlob[14],encryptKekBlob->kekBlob[15])); + SA_DBG2(("saEncryptKekUpdate, 0x%02X%02X%02X%02X 0x%02X%02X%02X%02X\n", + encryptKekBlob->kekBlob[16],encryptKekBlob->kekBlob[17], + encryptKekBlob->kekBlob[18],encryptKekBlob->kekBlob[19], + encryptKekBlob->kekBlob[20],encryptKekBlob->kekBlob[21], + encryptKekBlob->kekBlob[22],encryptKekBlob->kekBlob[23])); + SA_DBG2(("saEncryptKekUpdate, 0x%02X%02X%02X%02X 0x%02X%02X%02X%02X\n", + encryptKekBlob->kekBlob[24],encryptKekBlob->kekBlob[25], + encryptKekBlob->kekBlob[26],encryptKekBlob->kekBlob[27], + encryptKekBlob->kekBlob[28],encryptKekBlob->kekBlob[29], + encryptKekBlob->kekBlob[30],encryptKekBlob->kekBlob[31])); + SA_DBG2(("saEncryptKekUpdate, 0x%02X%02X%02X%02X 0x%02X%02X%02X%02X\n", + encryptKekBlob->kekBlob[32],encryptKekBlob->kekBlob[33], + encryptKekBlob->kekBlob[34],encryptKekBlob->kekBlob[35], + encryptKekBlob->kekBlob[36],encryptKekBlob->kekBlob[37], + encryptKekBlob->kekBlob[38],encryptKekBlob->kekBlob[39])); + SA_DBG2(("saEncryptKekUpdate, 0x%02X%02X%02X%02X 0x%02X%02X%02X%02X\n", + encryptKekBlob->kekBlob[40],encryptKekBlob->kekBlob[41], + encryptKekBlob->kekBlob[42],encryptKekBlob->kekBlob[43], + encryptKekBlob->kekBlob[44],encryptKekBlob->kekBlob[45], + encryptKekBlob->kekBlob[46],encryptKekBlob->kekBlob[47])); + /* create payload for IOMB */ + si_memset(&payload, 0, sizeof(agsaKekManagementCmd_t)); + + OSSA_WRITE_LE_32(agRoot, + &payload, + OSSA_OFFSET_OF(agsaKekManagementCmd_t, NEWKIDX_CURKIDX_KBF_Reserved_SKNV_KSOP), + (newKekIndex << SHIFT24) | (wrapperKekIndex << SHIFT16) | blobFormat << SHIFT14 | (flags << SHIFT8) | KEK_MGMT_SUBOP_UPDATE); + for (i = 0; i < 12; i++) + { + + OSSA_WRITE_LE_32(agRoot, + &payload, + OSSA_OFFSET_OF(agsaKekManagementCmd_t, kekBlob[i ]), + (bit32)*(bit32*)&encryptKekBlob->kekBlob[i * sizeof(bit32)] ); +/**/ + } + + ret = mpiKekManagementCmd(agRoot, agContext, &payload, queueNum ); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "30"); + return ret; +} + + +#ifdef HIALEAH_ENCRYPTION + +GLOBAL bit32 saEncryptHilUpdate( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum + ) +{ + agsaKekManagementCmd_t payload; + + bit32 ScratchPad1 =0; + bit32 ScratchPad3 =0; + bit32 ret =0; + + ScratchPad1 = ossaHwRegRead(agRoot,V_Scratchpad_1_Register); + ScratchPad3 = ossaHwRegRead(agRoot,V_Scratchpad_3_Register); + + + smTraceFuncEnter(hpDBG_VERY_LOUD,"xxx"); + + SA_DBG2(("saEncryptHilUpdate ScratchPad1 0x08%x ScratchPad3 0x08%x\n",ScratchPad1,ScratchPad3)); + /* create payload for IOMB */ + si_memset(&payload, 0, sizeof(agsaKekManagementCmd_t)); + + OSSA_WRITE_LE_32(agRoot, + &payload, + OSSA_OFFSET_OF(agsaKekManagementCmd_t, NEWKIDX_CURKIDX_KBF_Reserved_SKNV_KSOP), + (1 << SHIFT24) | (1 << SHIFT16) | (1 << SHIFT8) | KEK_MGMT_SUBOP_KEYCARDUPDATE); +/**/ + + ret = mpiKekManagementCmd(agRoot, agContext, &payload, queueNum ); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "xxx"); + return ret; +} +#endif /* HIALEAH_ENCRYPTION */ + +/** + * saEncryptKekInvalidate() + * + * Remove a KEK from the controller + * + * @param saRoot + * @param flags + * @param newKekIndex + * @param wrapperKekIndex + * @param encryptKekBlob + * + * @return + */ +GLOBAL bit32 saEncryptKekInvalidate( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 kekIndex + ) +{ + agsaKekManagementCmd_t payload; + bit32 ret; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"31"); + + SA_DBG2(("saEncryptKekInvalidate, kekIndex 0x%x \n",kekIndex)); + + + /* create payload for IOMB */ + si_memset(&payload, 0, sizeof(agsaDekManagementCmd_t)); + + OSSA_WRITE_LE_32(agRoot, + &payload, + OSSA_OFFSET_OF(agsaKekManagementCmd_t, NEWKIDX_CURKIDX_KBF_Reserved_SKNV_KSOP), + kekIndex << SHIFT16 | KEK_MGMT_SUBOP_INVALIDATE); + + ret = mpiKekManagementCmd(agRoot, agContext, &payload, queueNum ); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "31"); + return ret; +} + +/** + * saEncryptDekCacheUpdate() + * + * Replace a DEK within the controller cache + * + * @param saRoot + * @param kekIndex + * @param dekTableSelect + * @param dekAddrHi + * @param dekAddrLo + * @param dekIndex + * @param dekNumberOfEntries + * + * @return + */ +GLOBAL bit32 saEncryptDekCacheUpdate( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 kekIndex, + bit32 dekTableSelect, + bit32 dekAddrHi, + bit32 dekAddrLo, + bit32 dekIndex, + bit32 dekNumberOfEntries, + bit32 dekBlobFormat, + bit32 dekTableKeyEntrySize + ) +{ + agsaDekManagementCmd_t payload; + bit32 ret; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"32"); + + SA_DBG2(("saEncryptDekCacheUpdate, kekIndex 0x%x dekTableSelect 0x%x dekAddrHi 0x%x dekAddrLo 0x%x\n", + kekIndex, + dekTableSelect, + dekAddrHi, + dekAddrLo )); + SA_DBG2(("saEncryptDekCacheUpdate, dekIndex 0x%x dekNumberOfEntries 0x%x dekBlobFormat 0x%x dekTableKeyEntrySize 0x%x\n", + dekIndex, + dekNumberOfEntries, + dekBlobFormat, + dekTableKeyEntrySize)); + + /* create payload for IOMB */ + si_memset(&payload, 0, sizeof(agsaDekManagementCmd_t)); + + OSSA_WRITE_LE_32(agRoot, + &payload, + OSSA_OFFSET_OF(agsaDekManagementCmd_t, KEKIDX_Reserved_TBLS_DSOP), + (kekIndex << SHIFT24) | (dekTableSelect << SHIFT8) | DEK_MGMT_SUBOP_UPDATE); + + OSSA_WRITE_LE_32(agRoot, + &payload, + OSSA_OFFSET_OF(agsaDekManagementCmd_t, dekIndex), + dekIndex); + + OSSA_WRITE_LE_32(agRoot, + &payload, + OSSA_OFFSET_OF(agsaDekManagementCmd_t, tableAddrLo), + dekAddrLo); + + OSSA_WRITE_LE_32(agRoot, + &payload, + OSSA_OFFSET_OF(agsaDekManagementCmd_t, tableAddrHi), + dekAddrHi); + + OSSA_WRITE_LE_32(agRoot, + &payload, + OSSA_OFFSET_OF(agsaDekManagementCmd_t, tableEntries), + dekNumberOfEntries); + + OSSA_WRITE_LE_32(agRoot, + &payload, + OSSA_OFFSET_OF(agsaDekManagementCmd_t, Reserved_DBF_TBL_SIZE), + dekBlobFormat << SHIFT8 | dekTableKeyEntrySize ); + + ret = mpiDekManagementCmd(agRoot, agContext, &payload, queueNum); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "32"); + return ret; +} + +/** + * saEncryptDekCacheInvalidate() + * + * Remove a DEK from the controller cache + * + * @param saRoot + * @param kekIndex + * @param dekTable + * @param dekAddrHi + * @param dekAddrLo + * @param dekIndex + * @param dekNumberOfEntries + * + * @return + */ +GLOBAL bit32 saEncryptDekCacheInvalidate( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 dekTable, + bit32 dekIndex + ) +{ + agsaDekManagementCmd_t payload; + bit32 ret; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"33"); + + SA_DBG2(("saEncryptDekCacheInvalidate,dekTable 0x%x dekIndex 0x%x\n",dekTable,dekIndex)); + + /* create payload for IOMB */ + si_memset(&payload, 0, sizeof(agsaDekManagementCmd_t)); + + OSSA_WRITE_LE_32(agRoot, + &payload, + OSSA_OFFSET_OF(agsaDekManagementCmd_t, KEKIDX_Reserved_TBLS_DSOP), + (dekTable << SHIFT8) | DEK_MGMT_SUBOP_INVALIDATE); + + OSSA_WRITE_LE_32(agRoot, + &payload, + OSSA_OFFSET_OF(agsaDekManagementCmd_t, dekIndex), + dekIndex); + + /* Assume all DEKs are 80 bytes*/ + OSSA_WRITE_LE_32(agRoot, + &payload, + OSSA_OFFSET_OF(agsaDekManagementCmd_t, Reserved_DBF_TBL_SIZE), + 4); + + ret = mpiDekManagementCmd(agRoot, agContext, &payload, queueNum); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "33"); + return ret; +} + +/** + * saDIFEncryptionOffloadStart() + * + * initiate the SPCv controller offload function + * + * @param saRoot + * @param agContext + * @param queueNum + * @param op + * @param agsaDifEncPayload + * @param agCB + * + * @return + */ +GLOBAL bit32 saDIFEncryptionOffloadStart( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 op, + agsaDifEncPayload_t *agsaDifEncPayload, + ossaDIFEncryptionOffloadStartCB_t agCB) +{ + bit32 ret = AGSA_RC_FAILURE; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"3I"); + SA_DBG1(("saDIFEncryptionOffloadStart: start op=%d, agsaDifEncPayload=%p\n", op, agsaDifEncPayload)); + + if(smIS_SPCV(agRoot)) + { + ret = mpiDIFEncryptionOffloadCmd(agRoot, agContext, queueNum, op, agsaDifEncPayload, agCB); + } + else + { + SA_DBG1(("saDIFEncryptionOffloadStart: spcv only AGSA_RC_FAILURE \n")); + } + + SA_DBG1(("saDIFEncryptionOffloadStart: end status 0x%x\n",ret)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "3I"); + return ret; +} + +/** + * saSetControllerConfig() + * + * Update a controller mode page + * + * @param saRoot + * @param modePage + * @param length + * @param buffer + * @param agContext + * + * @return + */ +GLOBAL bit32 saSetControllerConfig( + agsaRoot_t *agRoot, + bit32 queueNum, + bit32 modePage, + bit32 length, + void *buffer, + agsaContext_t *agContext + ) +{ + agsaSetControllerConfigCmd_t agControllerConfig; + bit32 *src; + bit32 i, ret; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"34"); + + + if(smIS_SPCV(agRoot)) + { + + SA_DBG2(("saSetControllerConfig: queueNum %d modePage 0x%x length %d\n",queueNum,modePage,length )); + + /* If the page is well known, validate the size of the buffer */ + if (((modePage == AGSA_INTERRUPT_CONFIGURATION_PAGE) && (length != sizeof(agsaInterruptConfigPage_t ))) || + ((modePage == AGSA_ENCRYPTION_DEK_CONFIG_PAGE) && (length != sizeof(agsaEncryptDekConfigPage_t))) || + ((modePage == AGSA_ENCRYPTION_CONTROL_PARM_PAGE) && (length != sizeof(agsaEncryptControlParamPage_t ))) || + ((modePage == AGSA_ENCRYPTION_HMAC_CONFIG_PAGE) && (length != sizeof(agsaEncryptHMACConfigPage_t ))) || + ((modePage == AGSA_SAS_PROTOCOL_TIMER_CONFIG_PAGE) && (length != sizeof(agsaSASProtocolTimerConfigurationPage_t ))) ) + { + SA_DBG1(("saSetControllerConfig: AGSA_RC_FAILURE queueNum %d modePage 0x%x length %d\n",queueNum,modePage,length )); + ret = AGSA_RC_FAILURE; + } + else if(modePage == AGSA_ENCRYPTION_GENERAL_CONFIG_PAGE) + { + SA_DBG1(("saSetControllerConfig: Warning!!!!GENERAL_CONFIG_PAGE cannot be set\n")); + ret = AGSA_RC_FAILURE; + } + else + { + /* Copy the raw mode page data into something that can be wrapped in an IOMB. */ + si_memset(&agControllerConfig, 0, sizeof(agsaSetControllerConfigCmd_t)); + + agControllerConfig.tag = 0; /*HTAG */ + + src = (bit32 *) buffer; + + for (i = 0; i < (length / 4); i++) + { + OSSA_WRITE_LE_32(agRoot, + &agControllerConfig, + OSSA_OFFSET_OF(agsaSetControllerConfigCmd_t, pageCode) + (i * 4), + *src); + + src++; + } + ret = mpiSetControllerConfigCmd(agRoot, agContext, &agControllerConfig, queueNum,agFALSE); + if(ret) + { + SA_DBG1(("saSetControllerConfig: AGSA_RC_FAILURE (sending) queueNum %d modePage 0x%x length %d\n",queueNum,modePage,length )); + } + + } + } + else + { + SA_DBG1(("saSetControllerConfig: spcv only AGSA_RC_FAILURE queueNum %d modePage 0x%x length %d\n",queueNum,modePage,length )); + ret = AGSA_RC_FAILURE; + } + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "34"); + return ret; +} + + +/** + * saGetControllerConfig() + * + * Retrieve the contents of a controller mode page + * + * @param saRoot + * @param modePage + * @param agContext + * + * @return + */ +GLOBAL bit32 saGetControllerConfig( + agsaRoot_t *agRoot, + bit32 queueNum, + bit32 modePage, + bit32 flag0, + bit32 flag1, + agsaContext_t *agContext + ) +{ + bit32 ret; + agsaGetControllerConfigCmd_t agControllerConfig; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"35"); + + SA_DBG2(("saGetControllerConfig, modePage 0x%x agContext %p flag0 0x%08x flag1 0x%08x\n",modePage,agContext, flag0, flag1 )); + if(smIS_SPCV(agRoot)) + { + si_memset(&agControllerConfig, 0, sizeof(agsaGetControllerConfigCmd_t)); + + agControllerConfig.pageCode = modePage; + if(modePage == AGSA_INTERRUPT_CONFIGURATION_PAGE) + { + agControllerConfig.INT_VEC_MSK0 = flag0; + agControllerConfig.INT_VEC_MSK1 = flag1; + } + ret = mpiGetControllerConfigCmd(agRoot, agContext, &agControllerConfig, queueNum); + } + else + { + SA_DBG1(("saGetControllerConfig: spcv only AGSA_RC_FAILURE queueNum %d modePage 0x%x flag0 0x%08x flag1 0x%08x\n",queueNum,modePage, flag0, flag1 )); + ret = AGSA_RC_FAILURE; + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "35"); + return ret; +} + +GLOBAL bit32 saEncryptSelftestExecute ( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 type, + bit32 length, + void *TestDescriptor) +{ + bit32 ret = AGSA_RC_SUCCESS; + + agsaEncryptBist_t bist; + smTraceFuncEnter(hpDBG_VERY_LOUD,"2e"); + si_memset(&bist, 0, (sizeof(agsaEncryptBist_t))); + + SA_DBG1(("saEncryptSelftestExecute, enter\n" )); + bist.r_subop = (type & 0xFF); + + si_memcpy(&bist.testDiscption,TestDescriptor,length ); + + /* setup IOMB payload */ + ret = mpiEncryptBistCmd( agRoot, queueNum, agContext, &bist ); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2e"); + + return (ret); +} +GLOBAL bit32 saOperatorManagement( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 flag, + bit8 role, + agsaID_t *id, + agsaEncryptKekBlob_t *kblob) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaOperatorMangmentCmd_t opmcmd; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2i"); + + SA_DBG1(("saOperatorManagement, enter\n" )); + + si_memset(&opmcmd, 0, sizeof(agsaOperatorMangmentCmd_t)); + /*role = ((flag & SA_OPR_MGMNT_FLAG_MASK) >> SA_OPR_MGMNT_FLAG_SHIFT);*/ + + flag = (flag & ~SA_OPR_MGMNT_FLAG_MASK); + + opmcmd.OPRIDX_AUTIDX_R_KBF_PKT_OMO = flag; + + opmcmd.IDString_Role[0] = (bit8)role; + SA_DBG1(("saOperatorManagement, role 0x%X flags 0x%08X\n", role, opmcmd.OPRIDX_AUTIDX_R_KBF_PKT_OMO )); + + si_memcpy(&opmcmd.IDString_Role[1], id->ID, AGSA_ID_SIZE); + si_memcpy(&opmcmd.Kblob, kblob, sizeof(agsaEncryptKekBlob_t)); + + /* setup IOMB payload */ + ret = mpiOperatorManagementCmd(agRoot, queueNum, agContext, &opmcmd); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2i"); + + return (ret); +} + +/* + The command is for an operator to login to/logout from SPCve. + Only when all IOs are quiesced, can an operator logout. + + flag: + Access type (ACS) [4 bits] + 0x1: login + 0x2: logout + Others: reserved + KEYopr pinned in the KEK RAM (PIN) [1 bit] + 0: not pinned, operator ID table will be searched during authentication. + 1: pinned, OPRIDX is referenced to unwrap the certificate. + KEYopr Index in the KEK RAM (OPRIDX) [8 bits] + If KEYopr is pinned in the KEK RAM, OPRIDX is to reference to the KEK for authentication + + cert + Operator Certificate (CERT) [40 bytes] + + response calls ossaSetOperatorCB +*/ + +GLOBAL bit32 +saSetOperator( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 flag, + void *cert + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaSetOperatorCmd_t SetOperatorCmd; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"3c"); + SA_DBG1(("saSetOperator, flag 0x%x cert %p\n",flag, cert)); + + /* initialize set operator IOMB */ + si_memset(&SetOperatorCmd, 0, sizeof(agsaSetOperatorCmd_t)); + SetOperatorCmd.OPRIDX_PIN_ACS = flag; + si_memcpy((bit8*)SetOperatorCmd.cert, (bit8*)cert, 40); + + /* setup IOMB payload */ + ret = mpiSetOperatorCmd(agRoot, queueNum, agContext, &SetOperatorCmd); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "3c"); + return (ret); +} + +/* + The command is to get role and ID of either current or all operators from SPCve. + Option + 0x1: current operator + 0x2: all operators + Others: reserved + + OprBufAddr + the host buffer address to store the role and ID of all operators. Valid only when option == 0x2. + Buffer size must be 1KB to store max 32 operators's role and ID. + response calls ossaGetOperatorCB +*/ +GLOBAL bit32 +saGetOperator( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 option, + bit32 AddrHi, + bit32 AddrLo + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaGetOperatorCmd_t GetOperatorCmd; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"3d"); + SA_DBG1(("saGetOperator, option 0x%x 0x%08x_%08x\n",option,AddrHi,AddrLo )); + + /* initialize get operator IOMB */ + si_memset(&GetOperatorCmd, 0, sizeof(agsaGetOperatorCmd_t)); + GetOperatorCmd.option = option; + GetOperatorCmd.OprBufAddrLo = AddrLo; + GetOperatorCmd.OprBufAddrHi = AddrHi; + + /* setup IOMB payload */ + ret = mpiGetOperatorCmd(agRoot, queueNum, agContext, &GetOperatorCmd); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "3d"); + + return (ret); +} + diff --git a/sys/dev/pms/RefTisa/sallsdk/spc/saproto.h b/sys/dev/pms/RefTisa/sallsdk/spc/saproto.h new file mode 100644 index 000000000000..a4cae8c9eacf --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/spc/saproto.h @@ -0,0 +1,947 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/*******************************************************************************/ +/*! \file saproto.h + * \brief The file defines the function delcaration for internal used function + * + */ +/******************************************************************************/ + +#ifndef __SAPROTO_H__ + +#define __SAPROTO_H__ + +/* function declaration */ +/*** SATIMER.C ***/ +GLOBAL agsaTimerDesc_t *siTimerAdd( + agsaRoot_t *agRoot, + bit32 timeout, + agsaCallback_t pfnTimeout, + bit32 Event, + void * pParm + ); + +GLOBAL void siTimerRemove( + agsaRoot_t *agRoot, + agsaTimerDesc_t *pTimer + ); + +GLOBAL void siTimerRemoveAll(agsaRoot_t *agRoot); + +/*** SAINIT.C ***/ +GLOBAL bit32 siConfiguration(agsaRoot_t *agRoot, + mpiConfig_t *mpiConfig, + agsaHwConfig_t *hwConfig, + agsaSwConfig_t *swConfig + ); + +GLOBAL bit32 mpiInitialize(agsaRoot_t *agRoot, + mpiMemReq_t *memoryAllocated, + mpiConfig_t *config + ); + +GLOBAL bit32 mpiWaitForConfigTable(agsaRoot_t *agRoot, + spc_configMainDescriptor_t *config + ); + +GLOBAL void mpiUpdateIBQueueCfgTable(agsaRoot_t *agRoot, + spc_inboundQueueDescriptor_t *inQueueCfg, + bit32 QueueTableOffset, + bit8 pcibar + ); + +GLOBAL void mpiUpdateOBQueueCfgTable(agsaRoot_t *agRoot, + spc_outboundQueueDescriptor_t *outQueueCfg, + bit32 QueueTableOffset, + bit8 pcibar + ); +GLOBAL void mpiUpdateFatalErrorTable(agsaRoot_t *agRoot, + bit32 FerrTableOffset, + bit32 lowerBaseAddress, + bit32 upperBaseAddress, + bit32 length, + bit8 pcibar); + +GLOBAL bit32 mpiGetPCIBarIndex(agsaRoot_t *agRoot, + bit32 pciBar + ); + +GLOBAL bit32 mpiUnInitConfigTable(agsaRoot_t *agRoot); + +GLOBAL void mpiReadGSTable(agsaRoot_t *agRoot, + spc_GSTableDescriptor_t *mpiGSTable); + +GLOBAL void siInitResources(agsaRoot_t *agRoot, + agsaMemoryRequirement_t *memoryAllocated, + agsaHwConfig_t *hwConfig, + agsaSwConfig_t *swConfig, + bit32 usecsPerTick); + +GLOBAL void mpiReadCALTable(agsaRoot_t *agRoot, + spc_SPASTable_t *mpiCALTable, + bit32 index); + +GLOBAL void mpiWriteCALTable(agsaRoot_t *agRoot, + spc_SPASTable_t *mpiCALTable, + bit32 index); + +GLOBAL void mpiWriteCALAll(agsaRoot_t *agRoot, + agsaPhyAnalogSetupTable_t *mpiCALTable); + +GLOBAL void mpiWrIntVecTable(agsaRoot_t *agRoot, + mpiConfig_t* config + ); + +GLOBAL void mpiWrAnalogSetupTable(agsaRoot_t *agRoot, + mpiConfig_t *config + ); + + +GLOBAL void mpiWrPhyAttrbTable(agsaRoot_t *agRoot, + sasPhyAttribute_t *phyAttrib + ); + +/*** SAPHY.C ***/ +GLOBAL bit32 siPhyStopCB( + agsaRoot_t *agRoot, + bit32 phyId, + bit32 status, + agsaContext_t *agContext, + bit32 portId, + bit32 npipps + ); + +/*** SAPORT.C ***/ +GLOBAL void siPortInvalid( + agsaRoot_t *agRoot, + agsaPort_t *pPort + ); + +GLOBAL agsaDeviceDesc_t *siPortSASDeviceAdd( + agsaRoot_t *agRoot, + agsaPort_t *pPort, + agsaSASIdentify_t sasIdentify, + bit32 sasInitiator, + bit32 smpTimeout, + bit32 itNexusTimeout, + bit32 firstBurstSize, + bit8 dTypeSRate, + bit32 flag + ); + +GLOBAL void siPortDeviceRemove( + agsaRoot_t *agRoot, + agsaPort_t *pPort, + agsaDeviceDesc_t *pDevice, + bit32 unmap + ); + +GLOBAL agsaDeviceDesc_t *siPortSATADeviceAdd( + agsaRoot_t *agRoot, + agsaPort_t *pPort, + agsaDeviceDesc_t *pSTPBridge, + bit8 *pSignature, + bit8 pm, + bit8 pmField, + bit32 smpReqTimeout, + bit32 itNexusTimeout, + bit32 firstBurstSize, + bit8 dTypeSRate, + bit32 flag + ); + +GLOBAL void siPortDeviceListRemove( + agsaRoot_t *agRoot, + agsaPort_t *pPort, + agsaDeviceDesc_t *pDevice + ); + +/*** SASATA.C ***/ +GLOBAL void siSATASignatureCpy( + bit8 *pDstSignature, + bit8 *pSrcSignature + ); + +/*** SASSP.C ***/ + +/*** SAHW.C ***/ +#ifdef SA_ENABLE_HDA_FUNCTIONS +GLOBAL bit32 siHDAMode( + agsaRoot_t *agRoot, + bit32 HDAMode, + agsaFwImg_t *userFwImg + ); + +GLOBAL bit32 siHDAMode_V( + agsaRoot_t *agRoot, + bit32 HDAMode, + agsaFwImg_t *userFwImg + ); + +#endif + +GLOBAL bit32 siBar4Shift( + agsaRoot_t *agRoot, + bit32 shiftValue + ); + + +GLOBAL bit32 siSoftReset( + agsaRoot_t *agRoot, + bit32 signature + ); + +GLOBAL bit32 siSpcSoftReset( + agsaRoot_t *agRoot, + bit32 signature + ); + +GLOBAL void siChipReset( + agsaRoot_t *agRoot + ); + + +GLOBAL bit32 siChipResetV( + agsaRoot_t *agRoot, + bit32 signature + ); + +GLOBAL void siChipResetSpc( + agsaRoot_t *agRoot + ); + + +/*** SAUTIL.C ***/ +GLOBAL void siPrintBuffer( + bit32 debugLevel, + siPrintType type, + char *header, + void *a, + bit32 length + ); +int siIsHexDigit(char a); +GLOBAL FORCEINLINE void* si_memcpy(void *dst, void *src, bit32 count); +GLOBAL FORCEINLINE void* si_memset(void *s, int c, bit32 n); + +GLOBAL void siDumpActiveIORequests( + agsaRoot_t *agRoot, + bit32 count); + + +GLOBAL void siClearActiveIORequests( agsaRoot_t *agRoot); + +GLOBAL void siCountActiveIORequestsOnDevice( agsaRoot_t *agRoot, bit32 device ); +GLOBAL void siClearActiveIORequestsOnDevice( agsaRoot_t *agRoot, bit32 device ); + + + +/*** SAINT.C ***/ +GLOBAL void siEventPhyUpRcvd( + agsaRoot_t *agRoot, + bit32 phyId, + agsaSASIdentify_t *agSASIdentify, + bit32 portId, + bit32 npipps, + bit8 linkRate + ); + +GLOBAL void siEventSATASignatureRcvd( + agsaRoot_t *agRoot, + bit32 phyId, + void *pMsg, + bit32 portId, + bit32 npipps, + bit8 linkRate + ); + +GLOBAL FORCEINLINE void siIODone( + agsaRoot_t *agRoot, + agsaIORequestDesc_t *pRequest, + bit32 status, + bit32 sspTag + ); + +GLOBAL void siAbnormal( + agsaRoot_t *agRoot, + agsaIORequestDesc_t *pRequest, + bit32 status, + bit32 param, + bit32 sspTag + ); + +GLOBAL void siDifAbnormal( + agsaRoot_t *agRoot, + agsaIORequestDesc_t *pRequest, + bit32 status, + bit32 param, + bit32 sspTag, + bit32 *pMsg1 + ); + +GLOBAL void siEventSSPResponseWtDataRcvd( + agsaRoot_t *agRoot, + agsaIORequestDesc_t *pRequest, + agsaSSPResponseInfoUnit_t *pRespIU, + bit32 param, + bit32 sspTag + ); + +GLOBAL void siSMPRespRcvd( + agsaRoot_t *agRoot, + agsaSMPCompletionRsp_t *pIomb, + bit32 payloadSize, + bit32 tag + ); + +GLOBAL void siEventSATAResponseWtDataRcvd( + agsaRoot_t *agRoot, + agsaIORequestDesc_t *pRequest, + bit32 *agFirstDword, + bit32 *pResp, + bit32 lengthResp + ); + +/*** SADISC.C ***/ +GLOBAL bit32 siRemoveDevHandle( + agsaRoot_t *agRoot, + agsaDevHandle_t *agDevHandle + ); + +/*** SAMPIRSP.C ***/ +GLOBAL FORCEINLINE bit32 mpiParseOBIomb( + agsaRoot_t *agRoot, + bit32 *pMsg1, + mpiMsgCategory_t category, + bit16 opcode + ); + +GLOBAL bit32 mpiEchoRsp( + agsaRoot_t *agRoot, + agsaEchoRsp_t *pIomb + ); + +GLOBAL bit32 mpiGetNVMDataRsp( + agsaRoot_t *agRoot, + agsaGetNVMDataRsp_t *pIomb + ); + +GLOBAL bit32 mpiHWevent( + agsaRoot_t *agRoot, + agsaHWEvent_SPC_OUB_t *pIomb + ); + +GLOBAL bit32 mpiPhyStartEvent( + agsaRoot_t *agRoot, + agsaHWEvent_Phy_OUB_t *pIomb + ); + +GLOBAL bit32 mpiPhyStopEvent( + agsaRoot_t *agRoot, + agsaHWEvent_Phy_OUB_t *pIomb + ); + +GLOBAL bit32 mpiSMPCompletion( + agsaRoot_t *agRoot, + agsaSMPCompletionRsp_t *pIomb + ); + +GLOBAL bit32 mpiGetDevInfoRspSpc( + agsaRoot_t *agRoot, + agsaGetDevInfoRsp_t *pIomb + ); + +GLOBAL bit32 mpiGetPhyProfileRsp( + agsaRoot_t *agRoot, + agsaGetPhyProfileRspV_t *pIomb + ); + +GLOBAL bit32 mpiSetPhyProfileRsp( + agsaRoot_t *agRoot, + agsaSetPhyProfileRspV_t *pIomb + ); + +GLOBAL bit32 mpiGetDevInfoRsp( + agsaRoot_t *agRoot, + agsaGetDevInfoRspV_t *pIomb + ); + +GLOBAL bit32 mpiGetDevHandleRsp( + agsaRoot_t *agRoot, + agsaGetDevHandleRsp_t *pIomb + ); + +GLOBAL bit32 mpiPhyCntrlRsp( + agsaRoot_t *agRoot, + agsaLocalPhyCntrlRsp_t *pIomb + ); + +GLOBAL bit32 mpiDeviceRegRsp( + agsaRoot_t *agRoot, + agsaDeviceRegistrationRsp_t *pIomb + ); + +GLOBAL bit32 mpiDeregDevHandleRsp( + agsaRoot_t *agRoot, + agsaDeregDevHandleRsp_t *pIomb + ); + +GLOBAL FORCEINLINE bit32 mpiSSPCompletion( + agsaRoot_t *agRoot, + bit32 *pIomb + ); + +GLOBAL FORCEINLINE bit32 mpiSATACompletion( + agsaRoot_t *agRoot, + bit32 *pIomb + ); + +GLOBAL bit32 mpiSSPEvent( + agsaRoot_t *agRoot, + agsaSSPEventRsp_t *pIomb + ); + +GLOBAL bit32 mpiSATAEvent( + agsaRoot_t *agRoot, + agsaSATAEventRsp_t *pIomb + ); + +GLOBAL bit32 mpiFwFlashUpdateRsp( + agsaRoot_t *agRoot, + agsaFwFlashUpdateRsp_t *payload + ); + + +GLOBAL bit32 mpiFwExtFlashUpdateRsp( + agsaRoot_t *agRoot, + agsaFwFlashOpExtRsp_t *payload + ); + +#ifdef SPC_ENABLE_PROFILE +GLOBAL bit32 mpiFwProfileRsp( + agsaRoot_t *agRoot, + agsaFwProfileRsp_t *payload + ); +#endif +GLOBAL bit32 mpiSetNVMDataRsp( + agsaRoot_t *agRoot, + agsaSetNVMDataRsp_t *pIomb + ); + +GLOBAL bit32 mpiSSPAbortRsp( + agsaRoot_t *agRoot, + agsaSSPAbortRsp_t *pIomb + ); + +GLOBAL bit32 mpiSATAAbortRsp( + agsaRoot_t *agRoot, + agsaSATAAbortRsp_t *pIomb + ); + +GLOBAL bit32 mpiGPIORsp( + agsaRoot_t *agRoot, + agsaGPIORsp_t *pIomb + ); + +GLOBAL bit32 mpiGPIOEventRsp( + agsaRoot_t *agRoot, + agsaGPIOEvent_t *pIomb + ); + +GLOBAL bit32 mpiSASDiagStartEndRsp( + agsaRoot_t *agRoot, + agsaSASDiagStartEndRsp_t *pIomb + ); + +GLOBAL bit32 mpiSASDiagExecuteRsp( + agsaRoot_t *agRoot, + agsaSASDiagExecuteRsp_t *pIomb + ); + +GLOBAL bit32 mpiGeneralEventRsp( + agsaRoot_t *agRoot, + agsaGeneralEventRsp_t *pIomb + ); + +GLOBAL bit32 mpiSSPReqReceivedNotify( + agsaRoot_t *agRoot, + agsaSSPReqReceivedNotify_t *pMsg1 + ); + +GLOBAL bit32 mpiDeviceHandleArrived( + agsaRoot_t *agRoot, + agsaDeviceHandleArrivedNotify_t *pMsg1 + ); + +GLOBAL bit32 mpiGetTimeStampRsp( + agsaRoot_t *agRoot, + agsaGetTimeStampRsp_t *pIomb + ); + +GLOBAL bit32 mpiSASHwEventAckRsp( + agsaRoot_t *agRoot, + agsaSASHwEventAckRsp_t *pIomb + ); + +GLOBAL bit32 mpiSetDevInfoRsp( + agsaRoot_t *agRoot, + agsaSetDeviceInfoRsp_t *pIomb + ); + +GLOBAL bit32 mpiSetDeviceStateRsp( + agsaRoot_t *agRoot, + agsaSetDeviceStateRsp_t *pIomb + ); + +GLOBAL bit32 mpiGetDeviceStateRsp( + agsaRoot_t *agRoot, + agsaGetDeviceStateRsp_t *pIomb + ); + +GLOBAL bit32 mpiSasReInitializeRsp( + agsaRoot_t *agRoot, + agsaSasReInitializeRsp_t *pIomb + ); + +GLOBAL bit32 mpiSetControllerConfigRsp( + agsaRoot_t *agRoot, + agsaSetControllerConfigRsp_t *pIomb + ); + +GLOBAL bit32 mpiGetControllerConfigRsp( + agsaRoot_t *agRoot, + agsaGetControllerConfigRsp_t *pIomb + ); + +GLOBAL bit32 mpiKekManagementRsp( + agsaRoot_t *agRoot, + agsaKekManagementRsp_t *pIomb + ); + +GLOBAL bit32 mpiDekManagementRsp( + agsaRoot_t *agRoot, + agsaDekManagementRsp_t *pIomb + ); + +GLOBAL bit32 mpiOperatorManagementRsp( + agsaRoot_t *agRoot, + agsaOperatorMangmenRsp_t *pIomb + ); + +GLOBAL bit32 mpiBistRsp( + agsaRoot_t *agRoot, + agsaEncryptBistRsp_t *pIomb + ); + +GLOBAL bit32 mpiSetOperatorRsp( + agsaRoot_t *agRoot, + agsaSetOperatorRsp_t *pIomb + ); + +GLOBAL bit32 mpiGetOperatorRsp( + agsaRoot_t *agRoot, + agsaGetOperatorRsp_t *pIomb + ); + +GLOBAL bit32 mpiDifEncOffloadRsp( + agsaRoot_t *agRoot, + agsaDifEncOffloadRspV_t *pIomb + ); + +GLOBAL bit32 mpiGetVHistRsp( + agsaRoot_t *agRoot, + agsaGetVHistCapRsp_t *pIomb + ); + + +/*** SAMPICMD.C ***/ +GLOBAL bit32 mpiBuildCmd( + agsaRoot_t *agRoot, + bit32 *payload, + mpiMsgCategory_t category, + bit16 opcode, + bit16 size, + bit32 queueNum + ); + + +GLOBAL bit32 mpiVHistCapCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 Channel, + bit32 NumBitLo, + bit32 NumBitHi, + bit32 PcieAddrLo, + bit32 PcieAddrHi, + bit32 ByteCount ); + +GLOBAL bit32 mpiEchoCmd( + agsaRoot_t *agRoot, + bit32 queueNum, + agsaContext_t *agContext, + void *echoPayload + ); + +GLOBAL bit32 mpiGetPhyProfileCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 Operation, + bit32 PhyId, + void *agCB + ); + +GLOBAL bit32 mpiSetPhyProfileCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 Operation, + bit32 PhyId, + bit32 length, + void * buffer + ); + +GLOBAL bit32 mpiPhyStartCmd( + agsaRoot_t *agRoot, + bit32 tag, + bit32 phyId, + agsaPhyConfig_t *agPhyConfig, + agsaSASIdentify_t *agSASIdentify, + bit32 queueNum + ); + +GLOBAL bit32 mpiPhyStopCmd( + agsaRoot_t *agRoot, + bit32 tag, + bit32 phyId, + bit32 queueNum + ); + +GLOBAL bit32 mpiSMPCmd( + agsaRoot_t *agRoot, + void *pIomb, + bit16 opcode, + agsaSMPCmd_t *payload, + bit8 inq, + bit8 outq + ); + +GLOBAL bit32 mpiDeregDevHandleCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaDeviceDesc_t *pDevice, + bit32 deviceId, + bit32 portId, + bit32 queueNum + ); + +GLOBAL bit32 mpiGetDeviceHandleCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 portId, + bit32 flags, + bit32 maxDevs, + bit32 queueNum, + bit32 skipCount + ); + +GLOBAL bit32 mpiLocalPhyControlCmd( + agsaRoot_t *agRoot, + bit32 tag, + bit32 phyId, + bit32 operation, + bit32 queueNum + ); + +GLOBAL bit32 mpiGetDeviceInfoCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 deviceid, + bit32 option, + bit32 queueNum + ); + +GLOBAL bit32 mpiDevHandleAcceptCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 ctag, + bit32 deviceId, + bit32 action, + bit32 flag, + bit32 itlnx, + bit32 queueNum + ); + +GLOBAL bit32 mpiPortControlRsp( + agsaRoot_t *agRoot, + agsaPortControlRsp_t *pIomb + ); + +GLOBAL bit32 mpiSMPAbortRsp( + agsaRoot_t *agRoot, + agsaSMPAbortRsp_t *pIomb + ); + +GLOBAL bit32 siGetRegisterDumpGSM( + agsaRoot_t *agRoot, + void *destinationAddress, + bit32 regDumpNum, + bit32 regDumpOffset, + bit32 len + ); + +GLOBAL bit32 mpiNVMReadRegDumpCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 cpuId, + bit32 cOffset, + bit32 addrHi, + bit32 addrLo, + bit32 len + ); + +GLOBAL bit32 mpiDeviceHandleRemoval( + agsaRoot_t *agRoot, + agsaDeviceHandleRemoval_t *pMsg1); + +GLOBAL bit32 mpiGetNVMDCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaNVMDData_t *NVMDInfo, + bit32 queueNum + ); + +GLOBAL bit32 mpiSetNVMDCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaNVMDData_t *NVMDInfo, + bit32 queueNum + ); + +GLOBAL bit32 mpiSetDeviceInfoCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 deviceid, + bit32 option, + bit32 queueNum, + bit32 param, + ossaSetDeviceInfoCB_t agCB + ); + +GLOBAL bit32 mpiSetDeviceStateCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 deviceId, + bit32 nds, + bit32 queueNum + ); + +GLOBAL bit32 mpiGetDeviceStateCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 deviceId, + bit32 queueNum + ); + +GLOBAL bit32 mpiSasReinitializeCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaSASReconfig_t *agSASConfig, + bit32 queueNum + ); + +GLOBAL bit32 mpiSGpioRsp( + agsaRoot_t *agRoot, + agsaSGpioRsp_t *pInIomb + ); + +GLOBAL bit32 mpiPCIeDiagExecuteRsp( + agsaRoot_t *agRoot, + void *pInIomb + ); + +GLOBAL bit32 mpiGetDFEDataRsp( + agsaRoot_t *agRoot, + void *pInIomb + ); + +GLOBAL bit32 mpiGetVisDataRsp( + agsaRoot_t *agRoot, + void *pIomb + ); + +GLOBAL bit32 mpiSetControllerConfigCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaSetControllerConfigCmd_t *agControllerConfig, + bit32 queueNum, + bit8 modePageContext + ); + +GLOBAL bit32 mpiGetControllerConfigCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaGetControllerConfigCmd_t *agControllerConfig, + bit32 queueNum + ); + +GLOBAL bit32 mpiKekManagementCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaKekManagementCmd_t *agKekMgmt, + bit32 queueNum + ); + +GLOBAL bit32 mpiDekManagementCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaDekManagementCmd_t *agDekMgmt, + bit32 queueNum + ); + +GLOBAL bit32 mpiOperatorManagementCmd( + agsaRoot_t *agRoot, + bit32 queueNum, + agsaContext_t *agContext, + agsaOperatorMangmentCmd_t *operatorcode ); + +GLOBAL bit32 mpiEncryptBistCmd( + agsaRoot_t *agRoot, + bit32 queueNum, + agsaContext_t *agContext, + agsaEncryptBist_t *bist ); + +GLOBAL bit32 mpiSetOperatorCmd( + agsaRoot_t *agRoot, + bit32 queueNum, + agsaContext_t *agContext, + agsaSetOperatorCmd_t *operatorcode + ); + +GLOBAL bit32 mpiGetOperatorCmd( + agsaRoot_t *agRoot, + bit32 queueNum, + agsaContext_t *agContext, + agsaGetOperatorCmd_t *operatorcode + ); + +GLOBAL bit32 mpiDIFEncryptionOffloadCmd( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 op, + agsaDifEncPayload_t *agDifEncOffload, + ossaDIFEncryptionOffloadStartCB_t agCB + ); + +bit32 siOurMSIXInterrupt(agsaRoot_t *agRoot,bit32 interruptVectorIndex); +void siDisableMSIXInterrupts(agsaRoot_t *agRoot,bit32 interruptVectorIndex); +void siReenableMSIXInterrupts(agsaRoot_t *agRoot,bit32 interruptVectorIndex); + +bit32 siOurMSIInterrupt(agsaRoot_t *agRoot,bit32 interruptVectorIndex); +void siDisableMSIInterrupts(agsaRoot_t *agRoot,bit32 interruptVectorIndex); +void siReenableMSIInterrupts(agsaRoot_t *agRoot,bit32 interruptVectorIndex); + + +bit32 siOurLegacyInterrupt(agsaRoot_t *agRoot,bit32 interruptVectorIndex); +void siDisableLegacyInterrupts(agsaRoot_t *agRoot,bit32 interruptVectorIndex); +void siReenableLegacyInterrupts(agsaRoot_t *agRoot,bit32 interruptVectorIndex); + +bit32 siOurMSIX_V_Interrupt(agsaRoot_t *agRoot,bit32 interruptVectorIndex); +bit32 siOurMSI_V_Interrupt(agsaRoot_t *agRoot,bit32 interruptVectorIndex); +bit32 siOurLegacy_V_Interrupt(agsaRoot_t *agRoot,bit32 interruptVectorIndex); + +void siDisableMSIX_V_Interrupts(agsaRoot_t *agRoot,bit32 interruptVectorIndex); +void siDisableMSI_V_Interrupts(agsaRoot_t *agRoot,bit32 interruptVectorIndex); +void siDisableLegacy_V_Interrupts(agsaRoot_t *agRoot,bit32 interruptVectorIndex); + +void siReenableMSIX_V_Interrupts(agsaRoot_t *agRoot,bit32 interruptVectorIndex); +void siReenableMSI_V_Interrupts(agsaRoot_t *agRoot,bit32 interruptVectorIndex); +void siReenableLegacy_V_Interrupts(agsaRoot_t *agRoot,bit32 interruptVectorIndex); + + +GLOBAL void siUpdateBarOffsetTable(agsaRoot_t *agRoot, bit32 Spc_Type); + +GLOBAL void siPciCpyMem(agsaRoot_t *agRoot, + bit32 soffset, + const void *dst, + bit32 DWcount, + bit32 busBaseNumber + ); + +GLOBAL void siHalRegWriteExt( + agsaRoot_t *agRoot, + bit32 generic, + bit32 regOffset, + bit32 regValue + ); + +GLOBAL bit32 siHalRegReadExt( agsaRoot_t *agRoot, + bit32 generic, + bit32 regOffset + ); + +#ifdef SA_FW_TIMER_READS_STATUS +bit32 siReadControllerStatus( + agsaRoot_t *agRoot, + bit32 Event, + void * pParm + ); +#endif /* SA_FW_TIMER_READS_STATUS */ + + +#if defined(SALLSDK_DEBUG) +void sidump_hwConfig(agsaHwConfig_t *hwConfig); +void sidump_swConfig(agsaSwConfig_t *swConfig); +void sidump_Q_config( agsaQueueConfig_t *queueConfig ); +#endif +GLOBAL bit32 siGetTableOffset( + agsaRoot_t *agRoot, + bit32 TableOffsetInTable + ); + +GLOBAL bit32 siGetPciBar( + agsaRoot_t *agRoot + ); + +GLOBAL bit32 siScratchDump(agsaRoot_t *agRoot); + +void si_macro_check(agsaRoot_t *agRoot); + +GLOBAL bit32 si_check_V_HDA(agsaRoot_t *agRoot); +GLOBAL bit32 si_check_V_Ready(agsaRoot_t *agRoot); + +GLOBAL void siPCITriger(agsaRoot_t *agRoot); + +GLOBAL void siCheckQs(agsaRoot_t *agRoot); + + +GLOBAL bit32 smIsCfg_V_ANY( agsaRoot_t *agRoot); +GLOBAL bit32 smIS_SPC( agsaRoot_t *agRoot); +GLOBAL bit32 smIS_HIL( agsaRoot_t *agRoot); +GLOBAL bit32 smIS_SPC6V( agsaRoot_t *agRoot); +GLOBAL bit32 smIS_SPC12V( agsaRoot_t *agRoot); +GLOBAL bit32 smIS_SPCV( agsaRoot_t *agRoot); +GLOBAL bit32 smIS_ENCRYPT( agsaRoot_t *agRoot); +GLOBAL bit32 smIS_SPCV_2_IOP( agsaRoot_t *agRoot); +#endif /*__SAPROTO_H__ */ diff --git a/sys/dev/pms/RefTisa/sallsdk/spc/sasata.c b/sys/dev/pms/RefTisa/sallsdk/spc/sasata.c new file mode 100644 index 000000000000..40d829f8d153 --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/spc/sasata.c @@ -0,0 +1,936 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +/*******************************************************************************/ +/*! \file sasata.c + * \brief The file implements the functions to SATA IO + * + */ +/******************************************************************************/ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#ifdef SA_ENABLE_TRACE_FUNCTIONS +#ifdef siTraceFileID +#undef siTraceFileID +#endif +#define siTraceFileID 'M' +#endif + +/******************************************************************************/ +/*! \brief Start SATA command + * + * Start SATA command + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param queueNum + * \param agIORequest + * \param agDevHandle + * \param agRequestType + * \param agSATAReq + * \param agTag + * \param agCB + * + * \return If command is started successfully + * - \e AGSA_RC_SUCCESS command is started successfully + * - \e AGSA_RC_FAILURE command is not started successfully + */ +/*******************************************************************************/ +GLOBAL bit32 saSATAStart( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 queueNum, + agsaDevHandle_t *agDevHandle, + bit32 agRequestType, + agsaSATAInitiatorRequest_t *agSATAReq, + bit8 agTag, + ossaSATACompletedCB_t agCB + ) + +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + mpiICQueue_t *circularQ = agNULL; + agsaDeviceDesc_t *pDevice = agNULL; + agsaPort_t *pPort = agNULL; + agsaIORequestDesc_t *pRequest = agNULL; + void *pMessage = agNULL; + agsaSgl_t *pSgl = agNULL; + bit32 *payload = agNULL; + bit32 deviceIndex = 0; + bit32 ret = AGSA_RC_SUCCESS, retVal = 0; + bit32 AtapDir = 0; + bit32 encryptFlags = 0; + bit16 size = 0; + bit16 opCode = 0; + bit8 inq = 0, outq = 0; + + OSSA_INP_ENTER(agRoot); + smTraceFuncEnter(hpDBG_VERY_LOUD, "8a"); + + SA_DBG3(("saSATAStart: in\n")); + /* sanity check */ + SA_ASSERT((agNULL != agRoot), "(saSATAStart) agRoot is NULL"); + SA_ASSERT((agNULL != agIORequest), "(saSATAStart) agIORequest is NULL"); + SA_ASSERT((agNULL != agDevHandle), "(saSATAStart) agDevHandle is NULL"); + SA_ASSERT((agNULL != agSATAReq), "(saSATAStart) agSATAReq is NULL"); + + /* Assign inbound and outbound queue */ + inq = (bit8)(queueNum & MPI_IB_NUM_MASK); + outq = (bit8)((queueNum & MPI_OB_NUM_MASK) >> MPI_OB_SHIFT); + SA_ASSERT((AGSA_MAX_INBOUND_Q > inq), "The IBQ Number is out of range."); + + /* Find the outgoing port for the device */ + pDevice = (agsaDeviceDesc_t *) (agDevHandle->sdkData); + SA_ASSERT((agNULL != pDevice), "(saSATAStart) pDevice is NULL"); + + pPort = pDevice->pPort; + SA_ASSERT((agNULL != pPort), "(saSATAStart) pPort is NULL"); + + /* SATA DIF is obsolete */ + if (agSATAReq->option & AGSA_SATA_ENABLE_DIF) + { + return AGSA_RC_FAILURE; + } + + /* find deviceID for IOMB */ + deviceIndex = pDevice->DeviceMapIndex; + + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + if ( agNULL != pRequest ) + { + /* If free IOMB avaliable */ + /* Remove the request from free list */ + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + + /* Add the request to the pendingSTARequests list of the device */ + pRequest->valid = agTRUE; + saLlistIOAdd(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + if ((agSATAReq->option & AGSA_SATA_ENABLE_ENCRYPTION) || + (agSATAReq->option & AGSA_SATA_ENABLE_DIF)) + { + opCode = OPC_INB_SATA_DIF_ENC_OPSTART; + size = IOMB_SIZE128; + } + else + { + opCode = OPC_INB_SATA_HOST_OPSTART; + if (agRequestType == AGSA_SATA_PROTOCOL_NON_PKT || + agRequestType == AGSA_SATA_PROTOCOL_H2D_PKT || + agRequestType == AGSA_SATA_PROTOCOL_D2H_PKT) + size = IOMB_SIZE128; + else + size = IOMB_SIZE64; + } + /* If LL IO request entry avaliable */ + /* set up pRequest */ + pRequest->pIORequestContext = agIORequest; + pRequest->pDevice = pDevice; + pRequest->pPort = pPort; + pRequest->requestType = agRequestType; + pRequest->startTick = saRoot->timeTick; + pRequest->completionCB = (ossaSSPCompletedCB_t)agCB; + /* Set request to the sdkData of agIORequest */ + agIORequest->sdkData = pRequest; + + /* save tag and IOrequest pointer to IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedEnter(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + + /* get a free inbound queue entry */ + circularQ = &saRoot->inboundQueue[inq]; + retVal = mpiMsgFreeGet(circularQ, size, &pMessage); + + if (AGSA_RC_FAILURE == retVal) + { +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + /* if not sending return to free list rare */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + pRequest->valid = agFALSE; + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG3(("saSATAStart, error when get free IOMB\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "8a"); + ret = AGSA_RC_FAILURE; + goto ext; + } + + /* return busy if inbound queue is full */ + if (AGSA_RC_BUSY == retVal) + { +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + /* if not sending return to free list rare */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + pRequest->valid = agFALSE; + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("saSATAStart, no more IOMB\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "8a"); + ret = AGSA_RC_BUSY; + goto ext; + } + + } + else /* If no LL IO request entry available */ + { + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saSATAStart, No request from free list\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "8a"); + ret = AGSA_RC_BUSY; + goto ext; + } + + payload = (bit32 *)pMessage; + SA_DBG4(("saSATAStart: Payload offset 0x%X\n", (unsigned int)(payload - (bit32 *)pMessage))); + + + switch ( agRequestType ) + { + case AGSA_SATA_PROTOCOL_FPDMA_READ: + case AGSA_SATA_PROTOCOL_FPDMA_WRITE: + case AGSA_SATA_PROTOCOL_FPDMA_READ_M: + case AGSA_SATA_PROTOCOL_FPDMA_WRITE_M: + pSgl = &(agSATAReq->agSgl); + AtapDir = agRequestType & (AGSA_DIR_MASK | AGSA_SATA_ATAP_MASK); + if (agRequestType & AGSA_MSG) + { + /* set M bit */ + AtapDir |= AGSA_MSG_BIT; + } + break; + case AGSA_SATA_PROTOCOL_DMA_READ: + case AGSA_SATA_PROTOCOL_DMA_WRITE: + case AGSA_SATA_PROTOCOL_DMA_READ_M: + case AGSA_SATA_PROTOCOL_DMA_WRITE_M: + case AGSA_SATA_PROTOCOL_PIO_READ_M: + case AGSA_SATA_PROTOCOL_PIO_WRITE_M: + case AGSA_SATA_PROTOCOL_PIO_READ: + case AGSA_SATA_PROTOCOL_PIO_WRITE: + case AGSA_SATA_PROTOCOL_H2D_PKT: + case AGSA_SATA_PROTOCOL_D2H_PKT: + agTag = 0; /* agTag not valid for these requests */ + pSgl = &(agSATAReq->agSgl); + AtapDir = agRequestType & (AGSA_DIR_MASK | AGSA_SATA_ATAP_MASK); + if (agRequestType & AGSA_MSG) + { + /* set M bit */ + AtapDir |= AGSA_MSG_BIT; + } + break; + + case AGSA_SATA_PROTOCOL_NON_DATA: + case AGSA_SATA_PROTOCOL_NON_DATA_M: + case AGSA_SATA_PROTOCOL_NON_PKT: + agTag = 0; /* agTag not valid for these requests */ + AtapDir = agRequestType & (AGSA_DIR_MASK | AGSA_SATA_ATAP_MASK); + if (agRequestType & AGSA_MSG) + { + /* set M bit */ + AtapDir |= AGSA_MSG_BIT; + } + break; + + case AGSA_SATA_PROTOCOL_SRST_ASSERT: + agTag = 0; /* agTag not valid for these requests */ + AtapDir = AGSA_SATA_ATAP_SRST_ASSERT; + break; + + case AGSA_SATA_PROTOCOL_SRST_DEASSERT: + agTag = 0; /* agTag not valid for these requests */ + AtapDir = AGSA_SATA_ATAP_SRST_DEASSERT; + break; + + case AGSA_SATA_PROTOCOL_DEV_RESET: + case AGSA_SATA_PROTOCOL_DEV_RESET_M: /* TestBase */ + agTag = 0; /* agTag not valid for these requests */ + AtapDir = AGSA_SATA_ATAP_PKT_DEVRESET; + if (agRequestType & AGSA_MSG) + { + /* set M bit */ + AtapDir |= AGSA_MSG_BIT; /* TestBase */ + } + break; + + default: + SA_DBG1(("saSATAStart: (Unknown agRequestType) 0x%X \n",agRequestType)); + SA_ASSERT((0), "saSATAStart: (Unknown agRequestType)"); + + break; + } + + if ((AGSA_SATA_PROTOCOL_SRST_ASSERT == agRequestType) || + (AGSA_SATA_PROTOCOL_SRST_DEASSERT == agRequestType) || + (AGSA_SATA_PROTOCOL_DEV_RESET == agRequestType)) + { + + SA_DBG3(("saSATAStart:AGSA_SATA_PROTOCOL_SRST_DEASSERT AGSA_SATA_PROTOCOL_SRST_ASSERT\n")); + + si_memset((void *)payload, 0, sizeof(agsaSATAStartCmd_t)); + /* build IOMB DW 1 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t, tag), pRequest->HTag); + /* DWORD 2 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,deviceId ), deviceIndex); + /* DWORD 3 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,dataLen ), 0 ); + /* DWORD 4 */ + OSSA_WRITE_LE_32(agRoot, + payload, + OSSA_OFFSET_OF(agsaSATAStartCmd_t,optNCQTagataProt ), + (((agSATAReq->option & SATA_FIS_MASK) << SHIFT24) | + (agTag << SHIFT16) | + AtapDir)); + + si_memcpy((void *)(payload+4), (void *)&agSATAReq->fis.fisRegHostToDev, sizeof(agsaFisRegHostToDevice_t)); + } + else + { + /* build IOMB DW 1 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t, tag), pRequest->HTag); + /* DWORD 2 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,deviceId ), deviceIndex); + /* DWORD 3 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,dataLen ), agSATAReq->dataLength ); + + /* Since we are writing the payload in order, check for any special modes now. */ + if (agSATAReq->option & AGSA_SATA_ENABLE_ENCRYPTION) + { + SA_ASSERT((opCode == OPC_INB_SATA_DIF_ENC_OPSTART), "opcode"); + SA_DBG4(("saSATAStart: 1 Payload offset 0x%X\n", (unsigned int)(payload - (bit32 *)pMessage))); + AtapDir |= AGSA_ENCRYPT_BIT; + } + + if (agSATAReq->option & AGSA_SATA_ENABLE_DIF) + { + SA_ASSERT((opCode == OPC_INB_SATA_DIF_ENC_OPSTART), "opcode"); + AtapDir |= AGSA_DIF_BIT; + } +#ifdef CCBUILD_TEST_EPL + if(agSATAReq->encrypt.enableEncryptionPerLA) + AtapDir |= (1 << SHIFT4); // enable EPL +#endif + /* DWORD 4 */ + OSSA_WRITE_LE_32(agRoot, + payload, + OSSA_OFFSET_OF(agsaSATAStartCmd_t,optNCQTagataProt ), + (((agSATAReq->option & SATA_FIS_MASK) << SHIFT24) | + (agTag << SHIFT16) | + AtapDir)); + + /* DWORD 5 6 7 8 9 */ + si_memcpy((void *)(payload+4), (void *)&agSATAReq->fis.fisRegHostToDev, sizeof(agsaFisRegHostToDevice_t)); + /* DWORD 10 reserved */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,reserved1 ), 0 ); + + /* DWORD 11 reserved */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,reserved2 ), 0 ); + + SA_DBG4(("saSATAStart: 2 Payload offset 0x%X\n", (unsigned int)(payload - (bit32 *)pMessage))); + } + if (agSATAReq->option & AGSA_SATA_ENABLE_ENCRYPTION) + { + /* Write 10 dwords of zeroes as payload, skipping all DIF fields */ + SA_DBG4(("saSATAStart: 2a Payload offset 0x%X\n", (unsigned int)(payload - (bit32 *)pMessage))); + if (opCode == OPC_INB_SATA_DIF_ENC_OPSTART) + { + /* DW 11 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,Res_EPL_DESCL ),0 ); + /* DW 12 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,resSKIPBYTES ),0 ); + /* DW 13 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,Res_DPL_DESCL_NDPLR ),0 ); + /* DW 14 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,Res_EDPL_DESCH ),0 ); + /* DW 15 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,DIF_flags ),0 ); + /* DW 16 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,udt ),0 ); + /* DW 17 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,udtReplacementLo ),0 ); + /* DW 18 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,udtReplacementHi ),0 ); + /* DW 19 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,DIF_seed ),0 ); + } + + if (agSATAReq->option & AGSA_SATA_ENABLE_ENCRYPTION) + { + SA_ASSERT((opCode == OPC_INB_SATA_DIF_ENC_OPSTART), "opcode"); + + SA_DBG4(("saSATAStart: 3 Payload offset 0x%X\n", (unsigned int)(payload - (bit32 *)pMessage))); + /* Configure DWORD 20 */ + encryptFlags = 0; + + if (agSATAReq->encrypt.keyTagCheck == agTRUE) + { + encryptFlags |= AGSA_ENCRYPT_KEY_TAG_BIT; + } + + if( agSATAReq->encrypt.cipherMode == agsaEncryptCipherModeXTS ) + { + encryptFlags |= AGSA_ENCRYPT_XTS_Mode << SHIFT4; + } + + encryptFlags |= agSATAReq->encrypt.dekInfo.dekTable << SHIFT2; + + encryptFlags |= (agSATAReq->encrypt.dekInfo.dekIndex & 0xFFFFFF) << SHIFT8; + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,encryptFlagsLo ),encryptFlags ); + + /* Configure DWORD 21*/ + /* This information is available in the sectorSizeIndex */ + encryptFlags = agSATAReq->encrypt.sectorSizeIndex; + /* + * Set Region0 sectors count + */ + if(agSATAReq->encrypt.enableEncryptionPerLA) + { + encryptFlags |= (agSATAReq->encrypt.EncryptionPerLRegion0SecCount << SHIFT16); + } + + encryptFlags |= (agSATAReq->encrypt.kekIndex) << SHIFT5; + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,encryptFlagsHi ),encryptFlags ); + + /* Configure DWORD 22*/ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,keyTagLo ), agSATAReq->encrypt.keyTag_W0 ); + /* Configure DWORD 23 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,keyTagHi ), agSATAReq->encrypt.keyTag_W1 ); + /* Configure DWORD 24 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,tweakVal_W0 ), agSATAReq->encrypt.tweakVal_W0 ); + /* Configure DWORD 25 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,tweakVal_W1 ), agSATAReq->encrypt.tweakVal_W1 ); + /* Configure DWORD 26 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,tweakVal_W2 ), agSATAReq->encrypt.tweakVal_W2 ); + /* Configure DWORD 27 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,tweakVal_W3 ), agSATAReq->encrypt.tweakVal_W3 ); + } + else + { + /* Write 8 dwords of zeros as payload, skipping all encryption fields */ + if (opCode == OPC_INB_SATA_DIF_ENC_OPSTART) + { + /* Configure DWORD 22*/ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,keyTagLo ), 0 ); + /* Configure DWORD 23 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,keyTagHi ), 0 ); + /* Configure DWORD 24 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,tweakVal_W0 ), 0 ); + /* Configure DWORD 25 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,tweakVal_W1 ), 0 ); + /* Configure DWORD 26 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,tweakVal_W2 ), 0 ); + /* Configure DWORD 27 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,tweakVal_W3 ), 0 ); + } + } + + SA_DBG4(("saSATAStart: 4 Payload offset 0x%X\n", (unsigned int)(payload - (bit32 *)pMessage))); + + /* DWORD 11 13 14*/ + if(agSATAReq->encrypt.enableEncryptionPerLA) + { + /* DWORD 11 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t, Res_EPL_DESCL), + agSATAReq->encrypt.EncryptionPerLAAddrLo); + /* DWORD 13 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t, Res_DPL_DESCL_NDPLR), 0); + /* DWORD 14 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t, Res_EDPL_DESCH), + agSATAReq->encrypt.EncryptionPerLAAddrHi); + } + else + { + /* DWORD 11 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t, Res_EPL_DESCL),0); + /* DW 13 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t, Res_DPL_DESCL_NDPLR), 0); + /* DWORD 14 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,Res_EDPL_DESCH ),0 ); + } + + /* Configure DWORD 28 for encryption*/ + if (pSgl) + { + /* Configure DWORD 28 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,AddrLow0 ), pSgl->sgLower ); + /* Configure DWORD 29 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,AddrHi0 ), pSgl->sgUpper ); + /* Configure DWORD 30 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,Len0 ), pSgl->len ); + /* Configure DWORD 31 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,E0 ), pSgl->extReserved ); + } + else + { + /* Configure DWORD 28 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,AddrLow0 ), 0 ); + /* Configure DWORD 29 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,AddrHi0 ), 0 ); + /* Configure DWORD 30 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,Len0 ), 0 ); + /* Configure DWORD 31 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,E0 ), 0 ); + } + + } + else + { + SA_ASSERT((opCode == OPC_INB_SATA_HOST_OPSTART), "opcode"); + if (pSgl) + { + /* Configure DWORD 12 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,AddrLow0 ), pSgl->sgLower ); + /* Configure DWORD 13 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,AddrHi0 ), pSgl->sgUpper ); + /* Configure DWORD 14 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,Len0 ), pSgl->len ); + /* Configure DWORD 15 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,E0 ), pSgl->extReserved ); + } + else + { + /* Configure DWORD 12 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,AddrLow0 ), 0 ); + /* Configure DWORD 13 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,AddrHi0 ), 0 ); + /* Configure DWORD 14 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,Len0 ), 0 ); + /* Configure DWORD 15 */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,E0 ), 0 ); + } + /* support ATAPI packet command */ + if ((agRequestType == AGSA_SATA_PROTOCOL_NON_PKT || + agRequestType == AGSA_SATA_PROTOCOL_H2D_PKT || + agRequestType == AGSA_SATA_PROTOCOL_D2H_PKT)) + { + /*DWORD 16 - 19 as SCSI CDB for support ATAPI Packet command*/ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,ATAPICDB ), + (bit32)(agSATAReq->scsiCDB[0]|(agSATAReq->scsiCDB[1]<<8)|(agSATAReq->scsiCDB[2]<<16)|(agSATAReq->scsiCDB[3]<<24))); + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,ATAPICDB )+ 4, + (bit32)(agSATAReq->scsiCDB[4]|(agSATAReq->scsiCDB[5]<<8)|(agSATAReq->scsiCDB[6]<<16)|(agSATAReq->scsiCDB[7]<<24))); + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,ATAPICDB )+ 8, + (bit32)(agSATAReq->scsiCDB[8]|(agSATAReq->scsiCDB[9]<<8)|(agSATAReq->scsiCDB[10]<<16)|(agSATAReq->scsiCDB[11]<<24))); + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,ATAPICDB )+ 12, + (bit32)(agSATAReq->scsiCDB[12]|(agSATAReq->scsiCDB[13]<<8)|(agSATAReq->scsiCDB[14]<<16)|(agSATAReq->scsiCDB[15]<<24))); + } + } + + /* send IOMB to SPC */ + ret = mpiMsgProduce(circularQ, + (void *)pMessage, + MPI_CATEGORY_SAS_SATA, + opCode, + outq, + (bit8)circularQ->priority); + +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + +#ifdef SALL_API_TEST + if (AGSA_RC_FAILURE != ret) + { + saRoot->LLCounters.IOCounter.numSataStarted++; + } +#endif + + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "8a"); + +ext: + OSSA_INP_LEAVE(agRoot); + return ret; +} + +/******************************************************************************/ +/*! \brief Abort SATA command + * + * Abort SATA command + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param queueNum inbound/outbound queue number + * \param agIORequest the IO Request descriptor + * \param agIOtoBeAborted + * + * \return If command is aborted successfully + * - \e AGSA_RC_SUCCESS command is aborted successfully + * - \e AGSA_RC_FAILURE command is not aborted successfully + */ +/*******************************************************************************/ +GLOBAL bit32 saSATAAbort( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 queueNum, + agsaDevHandle_t *agDevHandle, + bit32 flag, + void *abortParam, + ossaGenericAbortCB_t agCB + ) +{ + bit32 ret = AGSA_RC_SUCCESS, retVal; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaIORequestDesc_t *pRequestABT = agNULL; + agsaDeviceDesc_t *pDevice = agNULL; + agsaDeviceDesc_t *pDeviceABT = NULL; + agsaPort_t *pPort = agNULL; + mpiICQueue_t *circularQ; + void *pMessage; + agsaSATAAbortCmd_t *payload; + agsaIORequest_t *agIOToBeAborted; + bit8 inq, outq; + bit32 flag_copy = flag; + + + smTraceFuncEnter(hpDBG_VERY_LOUD,"8b"); + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + SA_ASSERT((agNULL != agIORequest), ""); + + SA_DBG3(("saSATAAbort: Aborting request %p ITtoBeAborted %p\n", agIORequest, abortParam)); + + /* Assign inbound and outbound Ring Buffer */ + inq = (bit8)(queueNum & MPI_IB_NUM_MASK); + outq = (bit8)((queueNum & MPI_OB_NUM_MASK) >> MPI_OB_SHIFT); + SA_ASSERT((AGSA_MAX_INBOUND_Q > inq), "The IBQ Number is out of range."); + + if( ABORT_SINGLE == (flag & ABORT_MASK) ) + { + agIOToBeAborted = (agsaIORequest_t *)abortParam; + /* Get LL IORequest entry for saSATAAbort() */ + pRequest = (agsaIORequestDesc_t *) (agIOToBeAborted->sdkData); + if (agNULL == pRequest) + { + /* no pRequest found - can not Abort */ + SA_DBG1(("saSATAAbort: pRequest AGSA_RC_FAILURE\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "8b"); + return AGSA_RC_FAILURE; + } + /* Find the device the request sent to */ + pDevice = pRequest->pDevice; + /* Get LL IORequest entry */ + pRequestABT = (agsaIORequestDesc_t *) (agIOToBeAborted->sdkData); + /* Find the device the request sent to */ + if (agNULL == pRequestABT) + { + /* no pRequestABT - can not find pDeviceABT */ + SA_DBG1(("saSATAAbort: pRequestABT AGSA_RC_FAILURE\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "8b"); + return AGSA_RC_FAILURE; + } + pDeviceABT = pRequestABT->pDevice; + + if (agNULL == pDeviceABT) + { + /* no deviceID - can not build IOMB */ + SA_DBG1(("saSATAAbort: pDeviceABT AGSA_RC_FAILURE\n")); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "8b"); + return AGSA_RC_FAILURE; + } + + if (agNULL != pDevice) + { + /* Find the port the request was sent to */ + pPort = pDevice->pPort; + } + + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + } + else + { + if (ABORT_ALL == (flag & ABORT_MASK)) + { + /* abort all */ + /* Find the outgoing port for the device */ + pDevice = (agsaDeviceDesc_t *) (agDevHandle->sdkData); + pPort = pDevice->pPort; + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + } + else + { + /* only support 00 and 01 for flag */ + SA_DBG1(("saSATAAbort: flag AGSA_RC_FAILURE\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "8b"); + return AGSA_RC_FAILURE; + } + } + + /* If no LL IO request entry avalable */ + if ( agNULL == pRequest ) + { + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saSATAAbort, No request from free list\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "8b"); + return AGSA_RC_BUSY; + } + + /* If free IOMB avaliable */ + /* Remove the request from free list */ + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + + SA_ASSERT((!pRequest->valid), "The pRequest is in use"); + /* Add the request to the pendingIORequests list of the device */ + pRequest->valid = agTRUE; + saLlistIOAdd(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + /* set up pRequest */ + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + pRequest->pIORequestContext = agIORequest; + pRequest->requestType = AGSA_SATA_REQTYPE; + pRequest->pDevice = pDevice; + pRequest->pPort = pPort; + pRequest->completionCB = (void*)agCB; +/* pRequest->abortCompletionCB = agCB; */ + pRequest->startTick = saRoot->timeTick; + + /* Set request to the sdkData of agIORequest */ + agIORequest->sdkData = pRequest; + + /* save tag and IOrequest pointer to IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedEnter(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + + /* If LL IO request entry avaliable */ + /* Get a free inbound queue entry */ + circularQ = &saRoot->inboundQueue[inq]; + retVal = mpiMsgFreeGet(circularQ, IOMB_SIZE64, &pMessage); + + /* if message size is too large return failure */ + if (AGSA_RC_FAILURE == retVal) + { +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + pRequest->valid = agFALSE; + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("saSATAAbort, error when get free IOMB\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'f', "8b"); + return AGSA_RC_FAILURE; + } + + /* return busy if inbound queue is full */ + if (AGSA_RC_BUSY == retVal) + { +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + pRequest->valid = agFALSE; + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("saSATASAbort, no more IOMB\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'g', "8b"); + return AGSA_RC_BUSY; + } + + + /* setup payload */ + payload = (agsaSATAAbortCmd_t*)pMessage; + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAAbortCmd_t, tag), pRequest->HTag); + + if( ABORT_SINGLE == (flag & ABORT_MASK) ) + { + /* If no device */ + if ( agNULL == pDeviceABT ) + { + #ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq); + #endif /* SA_LL_IBQ_PROTECT */ + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + pRequest->valid = agFALSE; + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("saSATAAbort,no device\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'h', "8b"); + return AGSA_RC_FAILURE; + } + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAAbortCmd_t, deviceId), pDeviceABT->DeviceMapIndex); + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAAbortCmd_t, HTagAbort), pRequestABT->HTag); + } + else + { + /* abort all */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAAbortCmd_t, deviceId), pDevice->DeviceMapIndex); + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAAbortCmd_t, HTagAbort), 0); + } + + if(flag & ABORT_TSDK_QUARANTINE) + { + if(smIS_SPCV(agRoot)) + { + flag_copy &= ABORT_SCOPE; + flag_copy |= ABORT_QUARANTINE_SPCV; + } + } + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAAbortCmd_t, abortAll), flag_copy); + + + + SA_DBG1(("saSATAAbort, HTag 0x%x HTagABT 0x%x deviceId 0x%x\n", payload->tag, payload->HTagAbort, payload->deviceId)); + + /* post the IOMB to SPC */ + ret = mpiMsgProduce(circularQ, (void *)pMessage, MPI_CATEGORY_SAS_SATA, OPC_INB_SATA_ABORT, outq, (bit8)circularQ->priority); + +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + +#ifdef SALL_API_TEST + if (AGSA_RC_FAILURE != ret) + { + saRoot->LLCounters.IOCounter.numSataAborted++; + } +#endif + + siCountActiveIORequestsOnDevice( agRoot, payload->deviceId ); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'i', "8b"); + + return ret; +} + +/******************************************************************************/ +/*! \brief Routine to handle for received SATA with data payload event + * + * The handle for received SATA with data payload event + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param pRequest the IO request descriptor + * \param agFirstDword pointer to the first Dword + * \param pResp pointer to the rest of SATA response + * \param lengthResp total length of SATA Response frame + * + * \return -void- + */ +/*******************************************************************************/ +GLOBAL void siEventSATAResponseWtDataRcvd( + agsaRoot_t *agRoot, + agsaIORequestDesc_t *pRequest, + bit32 *agFirstDword, + bit32 *pResp, + bit32 lengthResp + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaDeviceDesc_t *pDevice; +#if defined(SALLSDK_DEBUG) + agsaFrameHandle_t frameHandle; + /* get frame handle */ + frameHandle = (agsaFrameHandle_t)(pResp); +#endif /* SALLSDK_DEBUG */ + + smTraceFuncEnter(hpDBG_VERY_LOUD,"8c"); + + /* If the request is still valid */ + if ( agTRUE == pRequest->valid ) + { + /* get device */ + pDevice = pRequest->pDevice; + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* Delete the request from the pendingIORequests */ + saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + (*(ossaSATACompletedCB_t)(pRequest->completionCB))(agRoot, + pRequest->pIORequestContext, + OSSA_IO_SUCCESS, + agFirstDword, + lengthResp, + (void *)pResp); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest->valid = agFALSE; + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "8c"); + + return; +} + +/******************************************************************************/ +/*! \brief copy a SATA signature to another + * + * copy a SATA signature to another + * + * \param pDstSignature pointer to the destination signature + * \param pSrcSignature pointer to the source signature + * + * \return If they match + * - \e agTRUE match + * - \e agFALSE doesn't match + */ +/*******************************************************************************/ +GLOBAL void siSATASignatureCpy( + bit8 *pDstSignature, + bit8 *pSrcSignature + ) +{ + bit32 i; + + for ( i = 0; i < 5; i ++ ) + { + pDstSignature[i] = pSrcSignature[i]; + } + + return; +} + + + diff --git a/sys/dev/pms/RefTisa/sallsdk/spc/sasmp.c b/sys/dev/pms/RefTisa/sallsdk/spc/sasmp.c new file mode 100644 index 000000000000..1dedc1598d4e --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/spc/sasmp.c @@ -0,0 +1,727 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +/*******************************************************************************/ +/*! \file sasmp.c + * \brief The file implements the functions for SMP request/response + * + */ +/*******************************************************************************/ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#ifdef SA_ENABLE_TRACE_FUNCTIONS +#ifdef siTraceFileID +#undef siTraceFileID +#endif +#define siTraceFileID 'N' +#endif + +/******************************************************************************/ +/*! \brief Start SMP request + * + * Start SMP request + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param queueNum + * \param agIORequest + * \param agDevHandle + * \param agRequestType + * \param agRequestBody + * \param agCB + * Spc - support direct mode direct response + * SpcV - support direct mode direct response + * SpcV - support indirect mode direct response + * SpcV - support indirect mode indirect response + * + * \return If request is started successfully + * - \e AGSA_RC_SUCCESS request is started successfully + * - \e AGSA_RC_BUSY No resource available, try again later + */ +/*******************************************************************************/ +GLOBAL bit32 saSMPStart( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 queueNum, + agsaDevHandle_t *agDevHandle, + bit32 agRequestType, + agsaSASRequestBody_t *agRequestBody, + ossaSMPCompletedCB_t agCB + ) +{ + bit32 ret = AGSA_RC_SUCCESS, retVal; + agsaLLRoot_t *saRoot = agNULL; + mpiICQueue_t *circularQ; + agsaDeviceDesc_t *pDevice; + agsaPort_t *pPort; + agsaIORequestDesc_t *pRequest; + void *pMessage; + bit8 i, inq, outq; + bit8 using_reserved = agFALSE; + bit8 *payload_ptr; + agsaSMPFrame_t *pSMPFrame; + + SA_DBG4(("saSMPStart: start\n")); + + smTraceFuncEnter(hpDBG_VERY_LOUD, "9a"); + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + SA_ASSERT((agNULL != agIORequest), ""); + SA_ASSERT((agNULL != agDevHandle), ""); + SA_ASSERT((agNULL != agRequestBody), ""); + + /* sanity check */ + saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + SA_ASSERT((agNULL != saRoot), ""); + + if(saRoot == agNULL) + { + SA_DBG1(("saSMPStart : saRoot is NULL!!\n")); + return AGSA_RC_FAILURE; + } + + /* Assign inbound and outbound queue number */ + inq = (bit8)(queueNum & MPI_IB_NUM_MASK); + outq = (bit8)((queueNum & MPI_OB_NUM_MASK) >> MPI_OB_SHIFT); + SA_ASSERT((AGSA_MAX_INBOUND_Q > inq), "The IBQ Number is out of range."); + + /* Find the outgoing port for the device */ + if (agNULL == agDevHandle->sdkData) + { + /* Device has been removed */ + SA_DBG1(("saSMPStart, Device has been removed. agDevHandle=%p\n", agDevHandle)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "9a"); + return AGSA_RC_FAILURE; + } + + pDevice = (agsaDeviceDesc_t *) (agDevHandle->sdkData); + + pPort = pDevice->pPort; + + /* Get request from free IO Requests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); /**/ + + /* If no LL IO request entry available */ + if ( agNULL == pRequest ) + { + + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeReservedRequests)); + + if(agNULL != pRequest) + { + using_reserved = agTRUE; + SA_DBG1(("saSMPStart, using saRoot->freeReservedRequests\n")); + } + else + { + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saSMPStart, No request from free list Not using saRoot->freeReservedRequests\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "9a"); + return AGSA_RC_BUSY; + } + } + + /* If free IOMB avaliable */ + /* Remove the request from free list */ + if( using_reserved ) + { + saLlistIORemove(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + + /* Add the request to the pendingSMPRequests list of the device */ + saLlistIOAdd(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + SA_ASSERT((!pRequest->valid), "The pRequest is in use"); + pRequest->valid = agTRUE; + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* set up pRequest */ + pRequest->pIORequestContext = agIORequest; + pRequest->pDevice = pDevice; + pRequest->pPort = pPort; + pRequest->requestType = agRequestType; + pRequest->startTick = saRoot->timeTick; + pRequest->completionCB = (ossaSSPCompletedCB_t)agCB; + + /* Set request to the sdkData of agIORequest */ + agIORequest->sdkData = pRequest; + + /* save tag to IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedEnter(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + + /* If LL IO request entry avaliable */ + /* Get a free inbound queue entry */ + circularQ = &saRoot->inboundQueue[inq]; + retVal = mpiMsgFreeGet(circularQ, IOMB_SIZE64, &pMessage); + + if (AGSA_RC_FAILURE == retVal) + { +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + /* if not sending return to free list rare */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + pRequest->valid = agFALSE; + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("saSMPStart, error when get free IOMB\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "9a"); + return AGSA_RC_FAILURE; + } + + /* return busy if inbound queue is full */ + if (AGSA_RC_BUSY == retVal) + { +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + /* if not sending return to free list rare */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + pRequest->valid = agFALSE; + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("saSMPStart, no more IOMB\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "9a"); + return AGSA_RC_BUSY; + } + + /* Setup SMP Frame */ + pSMPFrame = (agsaSMPFrame_t *) &(agRequestBody->smpFrame); + + SA_DBG2(("saSMPStart:DeviceMapIndex 0x%x portId 0x%x portId 0x%x\n",pDevice->DeviceMapIndex,pPort->portId,pPort->portId)); + +#if defined(SALLSDK_DEBUG) + + SA_DBG2(("saSMPStart: outFrameBuf %p\n",pSMPFrame->outFrameBuf)); + + if(pSMPFrame->outFrameBuf ) + { + SA_DBG2(("saSMPStart: outFrameBuf 0 0x%08X\n",*((bit32*)pSMPFrame->outFrameBuf+0) )); + SA_DBG2(("saSMPStart: outFrameBuf 1 0x%08X\n",*((bit32*)pSMPFrame->outFrameBuf+1) )); + SA_DBG2(("saSMPStart: outFrameBuf 2 0x%08X\n",*((bit32*)pSMPFrame->outFrameBuf+2) )); + SA_DBG2(("saSMPStart: outFrameBuf 3 0x%08X\n",*((bit32*)pSMPFrame->outFrameBuf+3) )); + SA_DBG2(("saSMPStart: outFrameBuf 4 0x%08X\n",*((bit32*)pSMPFrame->outFrameBuf+4) )); + SA_DBG2(("saSMPStart: outFrameBuf 5 0x%08X\n",*((bit32*)pSMPFrame->outFrameBuf+5) )); + SA_DBG2(("saSMPStart: outFrameBuf 6 0x%08X\n",*((bit32*)pSMPFrame->outFrameBuf+6) )); + SA_DBG2(("saSMPStart: outFrameBuf 7 0x%08X\n",*((bit32*)pSMPFrame->outFrameBuf+7) )); + SA_DBG2(("saSMPStart: outFrameBuf 8 0x%08X\n",*((bit32*)pSMPFrame->outFrameBuf+8) )); + SA_DBG2(("saSMPStart: outFrameBuf 9 0x%08X\n",*((bit32*)pSMPFrame->outFrameBuf+9) )); + SA_DBG2(("saSMPStart: outFrameBuf 11 0x%08X\n",*((bit32*)pSMPFrame->outFrameBuf+10) )); + SA_DBG2(("saSMPStart: outFrameBuf 11 0x%08X\n",*((bit32*)pSMPFrame->outFrameBuf+11) )); + } + SA_DBG2(("saSMPStart: outFrameAddrUpper32 0x%08X\n",pSMPFrame->outFrameAddrUpper32)); + SA_DBG2(("saSMPStart: outFrameAddrLower32 0x%08X\n",pSMPFrame->outFrameAddrLower32)); + SA_DBG2(("saSMPStart: outFrameLen 0x%08X\n",pSMPFrame->outFrameLen)); + SA_DBG2(("saSMPStart: inFrameAddrUpper32 0x%08X\n",pSMPFrame->inFrameAddrUpper32)); + SA_DBG2(("saSMPStart: inFrameAddrLower32 0x%08X\n",pSMPFrame->inFrameAddrLower32)); + SA_DBG2(("saSMPStart: inFrameLen 0x%08X\n",pSMPFrame->inFrameLen)); + SA_DBG2(("saSMPStart: expectedRespLen 0x%08X\n",pSMPFrame->expectedRespLen)); + SA_DBG2(("saSMPStart: flag 0x%08X\n",pSMPFrame->flag)); +#endif /* SALLSDK_DEBUG */ + + if(smIS_SPC(agRoot)) + // if(1) + { + agsaSMPCmd_t payload; + switch ( agRequestType ) + { + case AGSA_SMP_INIT_REQ: + { + bit32 IR_IP_OV_res_phyId_DPdLen_res = 0; + /* Prepare the payload of IOMB */ + si_memset(&payload, 0, sizeof(agsaSMPCmd_t)); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPCmd_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPCmd_t, deviceId), pDevice->DeviceMapIndex); + + /* check SMP Response Frame with IR mode */ + /* check if the SMP Response is indirect mode */ + if (0 == pSMPFrame->inFrameLen) + { + /* PHY override not support */ + /* Direct Response mode */ + pRequest->IRmode = DIRECT_MODE; + } + else + { + /* Indirect Response mode */ + pRequest->IRmode = INDIRECT_MODE; + IR_IP_OV_res_phyId_DPdLen_res = 1; + /* check SMP direct payload mode len */ + if (pSMPFrame->outFrameLen > 32) + { +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + /* if not sending return to free list rare */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + pRequest->valid = agFALSE; + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* can not handle SMP frame length > 32 bytes it if IP=0 and IR=1 */ + SA_DBG1(("saSMPStart, outFrameLen > 32 bytes error.\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "9a"); + return AGSA_RC_FAILURE; + } + } + + /* check Direct mode or Indirect mode for IP mode */ + if ( (pSMPFrame->outFrameBuf && + (pSMPFrame->outFrameLen <= AGSA_MAX_SMPPAYLOAD_VIA_SFO)) || + ((pSMPFrame->outFrameBuf == agNULL) && + (pSMPFrame->outFrameLen == 0) ) + ) + { + SA_DBG4(("saSMPStart: DIRECT Request SMP\n")); + + IR_IP_OV_res_phyId_DPdLen_res = (DIRECT_MODE << 1) | IR_IP_OV_res_phyId_DPdLen_res; + + /* Direct payload length */ + IR_IP_OV_res_phyId_DPdLen_res |= (((pSMPFrame->outFrameLen) & 0xff) << SHIFT16); + + /* copy payload - upto 48 bytes */ + si_memcpy(&(payload.SMPCmd[0]),pSMPFrame->outFrameBuf,pSMPFrame->outFrameLen); + for ( i = 0; i < pSMPFrame->outFrameLen / sizeof(bit32)+1; i ++ ) + { + SA_DBG4(("saSMPStart: payload.SMPCmd[%d] %x\n", i, payload.SMPCmd[i])); + } + } + else + { + SA_DBG4(("saSMPStart: INDIRECT Request SMP\n")); + /* use physical address */ + IR_IP_OV_res_phyId_DPdLen_res = (INDIRECT_MODE << 1) | IR_IP_OV_res_phyId_DPdLen_res; + + /* Direct payload length = 0 */ + IR_IP_OV_res_phyId_DPdLen_res = IR_IP_OV_res_phyId_DPdLen_res & 0xff00ffff; + + /* payload */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPCmd_t, SMPCmd[4]), (pSMPFrame->outFrameAddrLower32)); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPCmd_t, SMPCmd[5]), (pSMPFrame->outFrameAddrUpper32)); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPCmd_t, SMPCmd[6]), (pSMPFrame->outFrameLen)); + } + /* Write IR_IP_OV_res_phyId_DPdLen_res field in the payload*/ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPCmd_t, IR_IP_OV_res_phyId_DPdLen_res), IR_IP_OV_res_phyId_DPdLen_res); + + /* check IR bit */ + if (IR_IP_OV_res_phyId_DPdLen_res & INDIRECT_MODE) + { + /* setup indirect response frame address */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPCmd_t, SMPCmd[8]), (pSMPFrame->inFrameAddrLower32)); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPCmd_t, SMPCmd[9]), (pSMPFrame->inFrameAddrUpper32)); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPCmd_t, SMPCmd[10]), (pSMPFrame->inFrameLen)); + } + + /* Build IOMB command and send it to SPC */ + payload_ptr = (bit8 *)&payload; + ret = mpiSMPCmd(agRoot, pMessage, OPC_INB_SMP_REQUEST, (agsaSMPCmd_t *)payload_ptr, inq, outq); + + #ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq); + #endif /* SA_LL_IBQ_PROTECT */ + + break; + } + default: + { + SA_DBG1(("saSMPStart: SPC unknown agRequestType %x\n",agRequestType)); + break; + } + } + +#ifdef SALL_API_TEST + if (ret == AGSA_RC_SUCCESS) + saRoot->LLCounters.IOCounter.numSMPStarted++; +#endif + } + else /* IOMB is different for SPCV SMP */ + { + agsaSMPCmd_V_t vpayload; + + switch ( agRequestType ) + { + case AGSA_SMP_INIT_REQ: + { + bit32 IR_IP_OV_res_phyId_DPdLen_res = 0; + /* Prepare the payload of IOMB */ + si_memset(&vpayload, 0, sizeof(agsaSMPCmd_V_t)); + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t, deviceId), pDevice->DeviceMapIndex); + + /* Request header must be valid regardless of IP bit */ + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,SMPHDR ), *((bit32*)pSMPFrame->outFrameBuf+0) ); + + /* check SMP Response Frame with IR mode */ + /* check if the SMP Response is indirect mode */ + // smpFrameFlagDirectResponse smpFrameFlagDirectPayload + if ( 0 == pSMPFrame->flag && pSMPFrame->outFrameBuf ) + { + /* PHY override not support */ + /* Direct Response mode */ + pRequest->IRmode = DIRECT_MODE; + SA_DBG2(("saSMPStart:V DIRECT Request SMP\n")); + + IR_IP_OV_res_phyId_DPdLen_res = (DIRECT_MODE << 1) | IR_IP_OV_res_phyId_DPdLen_res; + + /* Direct payload length */ + IR_IP_OV_res_phyId_DPdLen_res |= (((pSMPFrame->outFrameLen) & 0xff) << SHIFT16); + /* Write IR_IP_OV_res_phyId_DPdLen_res field in the payload*/ + /* fatal error if missing */ + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t, IR_IP_OV_res_phyId_DPdLen_res), IR_IP_OV_res_phyId_DPdLen_res); + /* fatal error if missing */ + + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,SMP3_0 ), *((bit32*)pSMPFrame->outFrameBuf+1) ); + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,SMP7_4 ), *((bit32*)pSMPFrame->outFrameBuf+2) ); + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,SMP11_8), *((bit32*)pSMPFrame->outFrameBuf+3) ); + + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,IndirL_SMPRF15_12 ), *((bit32*)pSMPFrame->outFrameBuf+4) ); + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,IndirH_or_SMPRF19_16 ), *((bit32*)pSMPFrame->outFrameBuf+5) ); + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,IndirLen_or_SMPRF23_20 ),*((bit32*)pSMPFrame->outFrameBuf+6) ); + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,R_or_SMPRF27_24), *((bit32*)pSMPFrame->outFrameBuf+7) ); + + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,ISRAL_or_SMPRF31_28 ), *((bit32*)pSMPFrame->outFrameBuf+8) ); + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,ISRAH_or_SMPRF35_32 ), *((bit32*)pSMPFrame->outFrameBuf+9) ); + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,ISRL_or_SMPRF39_36 ), *((bit32*)pSMPFrame->outFrameBuf+10) ); + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,R_or_SMPRF43_40 ), *((bit32*)pSMPFrame->outFrameBuf+11) ); + + } + else if (smpFrameFlagIndirectResponse & pSMPFrame->flag && smpFrameFlagIndirectPayload & pSMPFrame->flag) /* */ + { + /* IR IP */ + SA_DBG2(("saSMPStart:V smpFrameFlagIndirectResponse smpFrameFlagIndirectPayload SMP\n")); + + pRequest->IRmode = INDIRECT_MODE; + IR_IP_OV_res_phyId_DPdLen_res = 3; + + /* Indirect payload mode */ + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,IndirL_SMPRF15_12 ), pSMPFrame->outFrameAddrLower32); + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,IndirH_or_SMPRF19_16 ), pSMPFrame->outFrameAddrUpper32); + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,IndirLen_or_SMPRF23_20 ), pSMPFrame->outFrameLen); + /* Indirect Response mode */ + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t, ISRAL_or_SMPRF31_28 ), (pSMPFrame->inFrameAddrLower32)); + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t, ISRAH_or_SMPRF35_32 ), (pSMPFrame->inFrameAddrUpper32)); + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t, ISRL_or_SMPRF39_36 ), (pSMPFrame->inFrameLen)); + } + else if (smpFrameFlagIndirectPayload & pSMPFrame->flag ) /* */ + { + /* IP */ + SA_DBG2(("saSMPStart:V smpFrameFlagIndirectPayload SMP\n")); + pRequest->IRmode = DIRECT_MODE; + IR_IP_OV_res_phyId_DPdLen_res = 2; + + /* Indirect payload mode */ + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,IndirL_SMPRF15_12 ), pSMPFrame->outFrameAddrLower32); + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,IndirH_or_SMPRF19_16 ), pSMPFrame->outFrameAddrUpper32); + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,IndirLen_or_SMPRF23_20 ), pSMPFrame->outFrameLen); + } + else if (smpFrameFlagIndirectResponse & pSMPFrame->flag ) /* */ + { + /* check IR bit */ + /* Indirect Response mode */ + pRequest->IRmode = INDIRECT_MODE; + SA_DBG2(("saSMPStart:V smpFrameFlagIndirectResponse SMP\n")); + /* use physical address */ + IR_IP_OV_res_phyId_DPdLen_res = 1; + /* Direct payload length */ + IR_IP_OV_res_phyId_DPdLen_res |= (((pSMPFrame->outFrameLen) & 0xff) << SHIFT16); + + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,SMP3_0 ), *((bit32*)pSMPFrame->outFrameBuf+1) ); + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,SMP7_4 ), *((bit32*)pSMPFrame->outFrameBuf+2) ); + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,SMP11_8), *((bit32*)pSMPFrame->outFrameBuf+3) ); + + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,IndirL_SMPRF15_12 ), *((bit32*)pSMPFrame->outFrameBuf+4) ); + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,IndirH_or_SMPRF19_16 ), *((bit32*)pSMPFrame->outFrameBuf+5) ); + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,IndirLen_or_SMPRF23_20 ),*((bit32*)pSMPFrame->outFrameBuf+6) ); + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,R_or_SMPRF27_24), *((bit32*)pSMPFrame->outFrameBuf+7) ); + + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t, ISRAL_or_SMPRF31_28 ), (pSMPFrame->inFrameAddrLower32)); + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t, ISRAH_or_SMPRF35_32 ), (pSMPFrame->inFrameAddrUpper32)); + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t, ISRL_or_SMPRF39_36 ), (pSMPFrame->inFrameLen)); + } + IR_IP_OV_res_phyId_DPdLen_res |= (pSMPFrame->flag & 3); + /* fatal error if missing */ + OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t, IR_IP_OV_res_phyId_DPdLen_res), IR_IP_OV_res_phyId_DPdLen_res); + /* fatal error if missing */ + } + /* Build IOMB command and send it to SPCv */ + payload_ptr = (bit8 *)&vpayload; + ret = mpiSMPCmd(agRoot, pMessage, OPC_INB_SMP_REQUEST, (agsaSMPCmd_t *)payload_ptr, inq, outq); + +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + + break; + default: + { + SA_DBG1(("saSMPStart: SPCv unknown agRequestType %x\n",agRequestType)); + break; + } + } + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'f', "9a"); + + /* return */ + return ret; +} + +/******************************************************************************/ +/*! \brief Abort SMP request + * + * Abort SMP request + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param queueNum + * \param agIORequest + * + * \return If request is aborted successfully + * - \e AGSA_RC_SUCCESS request is aborted successfully + * - \e AGSA_RC_FAILURE request is not aborted successfully + */ +/*******************************************************************************/ +GLOBAL bit32 saSMPAbort( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 queueNum, + agsaDevHandle_t *agDevHandle, + bit32 flag, + void *abortParam, + ossaGenericAbortCB_t agCB + ) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaIORequestDesc_t *pRequestABT = NULL; + agsaIORequest_t *agIOToBeAborted; + agsaDeviceDesc_t *pDevice; + agsaSMPAbortCmd_t payload; + bit32 using_reserved = agFALSE; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"9b"); + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + SA_ASSERT((agNULL != agIORequest), ""); + SA_ASSERT((agNULL != agDevHandle), ""); + + SA_DBG3(("saSMPAbort: Aborting request %p\n", agIORequest)); + + if( ABORT_SINGLE == (flag & ABORT_MASK) ) + { + agIOToBeAborted = (agsaIORequest_t *)abortParam; + /* Get LL IORequest entry for saSMPAbort() */ + pRequestABT = (agsaIORequestDesc_t *) (agIOToBeAborted->sdkData); + if (agNULL == pRequestABT) + { + /* The IO to Be Abort is no longer exist - can not Abort */ + SA_DBG1(("saSMPAbort: pRequestABT AGSA_RC_FAILURE\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "9b"); + return AGSA_RC_FAILURE; + } + + /* Find the device the request Abort to */ + pDevice = pRequestABT->pDevice; + + if (agNULL == pDevice) + { + /* no deviceID - can not build IOMB */ + SA_DBG1(("saSMPAbort: pDevice AGSA_RC_FAILURE\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "9b"); + return AGSA_RC_FAILURE; + } + } + else + { + if (ABORT_ALL == (flag & ABORT_MASK)) + { + /* abort All with Device or Port */ + /* Find the outgoing port for the device */ + pDevice = (agsaDeviceDesc_t *) (agDevHandle->sdkData); + if (agNULL == pDevice) + { + /* no deviceID - can not build IOMB */ + SA_DBG1(("saSMPAbort:ABORT_ALL pDevice AGSA_RC_FAILURE\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "9b"); + return AGSA_RC_FAILURE; + } + } + else + { + /* only support 00 and 01 for flag */ + SA_DBG1(("saSMPAbort:flag AGSA_RC_FAILURE\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "9b"); + return AGSA_RC_FAILURE; + } + } + + /* Get LL IORequest entry */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + + /* If no LL IO request entry available */ + if ( agNULL == pRequest ) + { + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeReservedRequests)); /**/ + /* If no LL Control request entry available */ + if(agNULL != pRequest) + { + using_reserved = agTRUE; + SA_DBG1(("saSMPAbort, using saRoot->freeReservedRequests\n")); + } + else + { + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saSMPAbort, No request from free list Not using saRoot->freeReservedRequests\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "9b"); + return AGSA_RC_BUSY; + } + } + + /* If free IOMB avaliable */ + /* Remove the request from free list */ + if( using_reserved ) + { + saLlistIORemove(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + + /* Add the request to the pendingSMPRequests list of the device */ + saLlistIOAdd(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + SA_ASSERT((!pRequest->valid), "The pRequest is in use"); + pRequest->valid = agTRUE; + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* set up pRequest */ + pRequest->pIORequestContext = agIORequest; + pRequest->requestType = AGSA_SMP_REQTYPE; + pRequest->completionCB = (void*)agCB; + pRequest->pDevice = pDevice; + pRequest->startTick = saRoot->timeTick; + + /* Set request to the sdkData of agIORequest */ + agIORequest->sdkData = pRequest; + + /* save tag to IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + + /* setup payload */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPAbortCmd_t, tag), pRequest->HTag); + + if( ABORT_SINGLE == (flag & ABORT_MASK) ) + { + if (agNULL == pRequestABT) + { + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + /* Delete the request from the pendingSMPRequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("saSMPAbort: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saSMPAbort, agNULL == pRequestABT\n")); + /* The IO to Be Abort is no longer exist - can not Abort */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'f', "9b"); + return AGSA_RC_FAILURE; + } + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPAbortCmd_t, HTagAbort), pRequestABT->HTag); + } + else + { + /* abort all */ + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPAbortCmd_t, HTagAbort), 0); + } + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPAbortCmd_t, deviceId), pDevice->DeviceMapIndex); + OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPAbortCmd_t, Scp), flag); + + SA_DBG1(("saSMPAbort, HTag 0x%x HTagABT 0x%x deviceId 0x%x\n", payload.tag, payload.HTagAbort, payload.deviceId)); + + /* build IOMB command and send to SPC */ + ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_SMP_ABORT, IOMB_SIZE64, queueNum); + if (AGSA_RC_SUCCESS != ret) + { + /* remove the request from IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; + saRoot->IOMap[pRequest->HTag].IORequest = agNULL; + saRoot->IOMap[pRequest->HTag].agContext = agNULL; + /* Delete the request from the pendingSMPRequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + /* return the request to free pool */ + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("saSMPAbort: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saSMPAbort, sending IOMB failed\n" )); + } +#ifdef SALL_API_TEST + else + { + saRoot->LLCounters.IOCounter.numSMPAborted++; + } +#endif + + smTraceFuncExit(hpDBG_VERY_LOUD, 'g', "9b"); + + return ret; +} + + + diff --git a/sys/dev/pms/RefTisa/sallsdk/spc/sassp.c b/sys/dev/pms/RefTisa/sallsdk/spc/sassp.c new file mode 100644 index 000000000000..851da8a7fc62 --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/spc/sassp.c @@ -0,0 +1,2169 @@ +/******************************************************************************* +** +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +/*******************************************************************************/ +/*! \file sassp.c + * \brief The file implements the functions for SSP request/response + * + */ +/*******************************************************************************/ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#ifdef SA_ENABLE_TRACE_FUNCTIONS +#ifdef siTraceFileID +#undef siTraceFileID +#endif +#define siTraceFileID 'O' +#endif + +#ifdef LOOPBACK_MPI +extern int loopback; +#endif + +#ifdef SALLSDK_DEBUG +LOCAL void siDumpSSPStartIu( + agsaDevHandle_t *agDevHandle, + bit32 agRequestType, + agsaSASRequestBody_t *agRequestBody + ); +#endif + +#ifdef FAST_IO_TEST +LOCAL bit32 saGetIBQPI(agsaRoot_t *agRoot, + bit32 queueNum) +{ + bit8 inq; + mpiICQueue_t *circularQ; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + + inq = INQ(queueNum); + circularQ = &saRoot->inboundQueue[inq]; + return circularQ->producerIdx; +} + +LOCAL void saSetIBQPI(agsaRoot_t *agRoot, + bit32 queueNum, + bit32 pi) +{ + bit8 inq; + mpiICQueue_t *circularQ; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + + inq = INQ(queueNum); + circularQ = &saRoot->inboundQueue[inq]; + circularQ->producerIdx = pi; +} + +osLOCAL void* +siFastSSPReqAlloc(agsaRoot_t *agRoot) +{ + int idx; + agsaLLRoot_t *saRoot = (agsaLLRoot_t*)(agRoot->sdkData); + saFastRequest_t *fr; + + if (!saRoot->freeFastIdx) + { + SA_DBG1(("saSuperSSPReqAlloc: no memory ERROR\n")); + SA_ASSERT((0), ""); + return 0; + } + + ossaSingleThreadedEnter(agRoot, LL_FAST_IO_LOCK); + saRoot->freeFastIdx--; + idx = saRoot->freeFastIdx; + ossaSingleThreadedLeave(agRoot, LL_FAST_IO_LOCK); + + fr = saRoot->freeFastReq[idx]; + SA_ASSERT((fr), ""); + fr->valid = 1; + + return fr; +} + +LOCAL void +siFastSSPReqFree( + agsaRoot_t *agRoot, + void *freq) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + saFastRequest_t *fr = (saFastRequest_t*)freq; + + SA_DBG2(("siFastSSPReqFree: enter\n")); + SA_ASSERT((fr->valid), ""); + if (saRoot->freeFastIdx >= sizeof(saRoot->freeFastReq) / + sizeof(saRoot->freeFastReq[0])) + { + SA_DBG1(("siFastSSPReqFree: too many handles %d / %d ERROR\n", + saRoot->freeFastIdx, (int)(sizeof(saRoot->freeFastReq) / + sizeof(saRoot->freeFastReq[0])))); + SA_ASSERT((0), ""); + return; + } + ossaSingleThreadedEnter(agRoot, LL_FAST_IO_LOCK); + /* not need if only one entry */ + /* saRoot->freeFastReq[saRoot->freeFastIdx] = freq; */ + saRoot->freeFastIdx++; + ossaSingleThreadedLeave(agRoot, LL_FAST_IO_LOCK); + + fr->valid = 0; + SA_DBG6(("siFastSSPReqFree: leave\n")); +} + +LOCAL bit32 siFastSSPResAlloc( + agsaRoot_t *agRoot, + bit32 queueNum, + bit32 agRequestType, + agsaDeviceDesc_t *pDevice, + agsaIORequestDesc_t **pRequest, + void **pPayload + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t*)(agRoot->sdkData); + mpiICQueue_t *circularQ; + bit8 inq; + bit16 size = IOMB_SIZE64; + bit32 ret = AGSA_RC_SUCCESS, retVal; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2D"); + + SA_DBG4(("Entering function siFastSSPResAlloc:\n")); + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + *pRequest = (agsaIORequestDesc_t*)saLlistIOGetHead(&saRoot->freeIORequests); + + /* If no LL IO request entry available */ + if (agNULL == *pRequest ) + { + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("siFastSSPResAlloc: No request from free list\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2D"); + ret = AGSA_RC_BUSY; + goto ext; + } + + /* Get IO request from free IORequests */ + /* Assign inbound and outbound Buffer */ + inq = INQ(queueNum); + SA_ASSERT((AGSA_MAX_INBOUND_Q > inq), "The IBQ Number is out of range."); + + /* SSP_INI_IO_START_EXT IOMB need at least 80 bytes to support 32 CDB */ + if (agRequestType & AGSA_SSP_EXT_BIT) + { + size = IOMB_SIZE96; + } + /* If LL IO request entry avaliable */ + /* Get a free inbound queue entry */ + circularQ = &saRoot->inboundQueue[inq]; + retVal = mpiMsgFreeGet(circularQ, size, pPayload); + + /* if message size is too large return failure */ + if (AGSA_RC_SUCCESS != retVal) + { + if (AGSA_RC_FAILURE == retVal) + { + SA_DBG1(("siFastSSPResAlloc: error when get free IOMB\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2D"); + } + + /* return busy if inbound queue is full */ + if (AGSA_RC_BUSY == retVal) + { + SA_DBG3(("siFastSSPResAlloc: no more IOMB\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "2D"); + } + ret = retVal; + goto ext; + } + + /* But add it to the pending queue during FastStart */ + /* If free IOMB avaliable */ + /* Remove the request from free list */ + saLlistIORemove(&saRoot->freeIORequests, &(*pRequest)->linkNode); + + /* Add the request to the pendingIORequests list of the device */ + saLlistIOAdd(&pDevice->pendingIORequests, &(*pRequest)->linkNode); + +ext: + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + if (AGSA_RC_SUCCESS == ret) + { + /* save tag and IOrequest pointer to IOMap */ + saRoot->IOMap[(*pRequest)->HTag].Tag = (*pRequest)->HTag; + saRoot->IOMap[(*pRequest)->HTag].IORequest = (void *)*pRequest; + } + + return ret; +} /* siFastSSPResAlloc */ + + +GLOBAL bit32 saFastSSPCancel(void *ioHandle) +{ + agsaRoot_t *agRoot; + agsaLLRoot_t *saRoot; + saFastRequest_t *fr; + bit32 i; + agsaIORequestDesc_t *ior; + + SA_ASSERT((ioHandle), ""); + fr = (saFastRequest_t*)ioHandle; + SA_ASSERT((fr->valid), ""); + agRoot = (agsaRoot_t*)fr->agRoot; + SA_ASSERT((agRoot), ""); + saRoot = (agsaLLRoot_t*)(agRoot->sdkData); + SA_ASSERT((saRoot), ""); + + smTraceFuncEnter(hpDBG_VERY_LOUD,"2E"); + + /* rollback the previously set IBQ PI */ + for (i = 0; i < fr->inqMax - 1; i++) + saSetIBQPI(agRoot, fr->inqList[i], fr->beforePI[fr->inqList[i]]); + + /* free all the previous Fast IO Requests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* at least one entry, no need to check for NULL saLlistIOGetHead() */ + ior = (agsaIORequestDesc_t*)((char*)saLlistIOGetHead(&fr->requests) - + OSSA_OFFSET_OF(agsaIORequestDesc_t, fastLink)); + do + { + agsaDeviceDesc_t *pDevice; + void *tmp; + + pDevice = ior->pDevice; + saLlistIORemove(&pDevice->pendingIORequests, &ior->linkNode); + saLlistIOAdd(&saRoot->freeIORequests, &ior->linkNode); + + tmp = (void*)saLlistGetNext(&fr->requests, &ior->fastLink); + if (!tmp) + { + break; /* end of list */ + } + ior = (agsaIORequestDesc_t*)((char*)tmp - + OSSA_OFFSET_OF(agsaIORequestDesc_t, fastLink)); + } while (1); + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* free the IBQ PI tracking struct */ + siFastSSPReqFree(agRoot, fr); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2E"); + return AGSA_RC_SUCCESS; +} /* saFastSSPCancel */ + +GLOBAL void *saFastSSPPrepare( + void *ioh, + agsaFastCommand_t *fc, + ossaSSPCompletedCB_t cb, + void *cbArg) +{ + bit32 ret = AGSA_RC_SUCCESS; + agsaRoot_t *agRoot; + agsaLLRoot_t *saRoot; + mpiICQueue_t *circularQ; + agsaDeviceDesc_t *pDevice; + agsaSgl_t *pSgl; + bit32 Dir = 0; + bit8 inq, outq; + saFastRequest_t *fr; + void *pMessage; + agsaIORequestDesc_t *pRequest; + bit16 opCode; + bitptr offsetTag; + bitptr offsetDeviceId; + bitptr offsetDataLen; + bitptr offsetDir; + + agRoot = (agsaRoot_t*)fc->agRoot; + smTraceFuncEnter(hpDBG_VERY_LOUD,"2G"); + + OSSA_INP_ENTER(agRoot); + + saRoot = (agsaLLRoot_t*)(agRoot->sdkData); + /* sanity check */ + SA_ASSERT((agNULL != saRoot), ""); + + SA_DBG4(("Entering function saFastSSPPrepare:\n")); + + fr = (saFastRequest_t*)ioh; + if (!fr) + { + int i; + fr = siFastSSPReqAlloc(agRoot); + if (!fr) + { + SA_ASSERT((0), ""); + goto ext; + } + + saLlistIOInitialize(&fr->requests); + for (i = 0; i < AGSA_MAX_INBOUND_Q; i++) + fr->beforePI[i] = (bit32)-1; + + fr->inqMax = 0; + fr->agRoot = agRoot; + ioh = fr; + } + + /* Find the outgoing port for the device */ + pDevice = (agsaDeviceDesc_t*)(((agsaDevHandle_t*)fc->devHandle)->sdkData); + + ret = siFastSSPResAlloc(agRoot, fc->queueNum, fc->agRequestType, + pDevice, &pRequest, &pMessage); + if (ret != AGSA_RC_SUCCESS) + { + SA_ASSERT((0), ""); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2G"); + goto ext; + } + + /* Assign inbound and outbound Buffer */ + inq = INQ(fc->queueNum); + outq = OUQ(fc->queueNum); + circularQ = &saRoot->inboundQueue[inq]; + + SA_DBG3(("saFastSSPPrepare: deviceId %d\n", pDevice->DeviceMapIndex)); + + /* set up pRequest */ + pRequest->valid = agTRUE; + pRequest->pDevice = pDevice; + pRequest->requestType = fc->agRequestType; + + pRequest->completionCB = cb; + pRequest->pIORequestContext = (agsaIORequest_t*)cbArg; + + pSgl = fc->agSgl; + + switch (fc->agRequestType) + { + /* case AGSA_SSP_INIT_NONDATA: */ + case AGSA_SSP_INIT_READ: + case AGSA_SSP_INIT_WRITE: + case AGSA_SSP_INIT_READ_M: + case AGSA_SSP_INIT_WRITE_M: + { + agsaSSPIniIOStartCmd_t *pPayload = (agsaSSPIniIOStartCmd_t *)pMessage; + agsaSSPCmdInfoUnit_t *piu; + + /* SSPIU less equal 28 bytes */ + offsetTag = OSSA_OFFSET_OF(agsaSSPIniIOStartCmd_t, tag); + offsetDeviceId = OSSA_OFFSET_OF(agsaSSPIniIOStartCmd_t, deviceId); + offsetDataLen = OSSA_OFFSET_OF(agsaSSPIniIOStartCmd_t, dataLen); + offsetDir = OSSA_OFFSET_OF(agsaSSPIniIOStartCmd_t, dirMTlr); + + piu = &pPayload->SSPInfoUnit; + + si_memcpy(piu->lun, fc->lun, sizeof(piu->lun)); + si_memcpy(piu->cdb, fc->cdb, sizeof(piu->cdb)); + piu->efb_tp_taskAttribute = fc->taskAttribute; + piu->additionalCdbLen = fc->additionalCdbLen; + + /* Mask DIR for Read/Write command */ + Dir = fc->agRequestType & AGSA_DIR_MASK; + + /* set TLR */ + Dir |= fc->flag & TLR_MASK; + if (fc->agRequestType & AGSA_MSG) + { + /* set M bit */ + Dir |= AGSA_MSG_BIT; + } + + /* Setup SGL */ + if (fc->dataLength) + { + SA_DBG5(("saFastSSPPrepare: agSgl %08x:%08x (%x/%x)\n", + pSgl->sgUpper, pSgl->sgLower, pSgl->len, pSgl->extReserved)); + /* + pPayload->AddrLow0 = pSgl->sgLower; + pPayload->AddrHi0 = pSgl->sgUpper; + pPayload->Len0 = pSgl->len; + pPayload->E0 = pSgl->extReserved; + */ + si_memcpy(&pPayload->AddrLow0, pSgl, sizeof(*pSgl)); + } + else + { + /* no data transfer */ + si_memset(&pPayload->AddrLow0, 0, sizeof(*pSgl)); + } + + opCode = OPC_INB_SSPINIIOSTART; + break; + } + + case AGSA_SSP_INIT_READ_EXT: + case AGSA_SSP_INIT_WRITE_EXT: + case AGSA_SSP_INIT_READ_EXT_M: + case AGSA_SSP_INIT_WRITE_EXT_M: + { + agsaSSPIniExtIOStartCmd_t *pPayload = + (agsaSSPIniExtIOStartCmd_t *)pMessage; + agsaSSPCmdInfoUnitExt_t *piu; + bit32 sspiul; + + /* CDB > 16 bytes */ + offsetTag = OSSA_OFFSET_OF(agsaSSPIniExtIOStartCmd_t, tag); + offsetDeviceId = OSSA_OFFSET_OF(agsaSSPIniExtIOStartCmd_t, deviceId); + offsetDataLen = OSSA_OFFSET_OF(agsaSSPIniExtIOStartCmd_t, dataLen); + offsetDir = OSSA_OFFSET_OF(agsaSSPIniExtIOStartCmd_t, SSPIuLendirMTlr); + + /* dword (bit7-bit2) ==> bytes (bit7-bit0) */ + /* setup standard CDB bytes + additional CDB bytes in length field */ + sspiul = sizeof(agsaSSPCmdInfoUnit_t) + (fc->additionalCdbLen & 0xFC); + + Dir = sspiul << 16; + piu = (agsaSSPCmdInfoUnitExt_t*)pPayload->SSPIu; + + si_memcpy(piu->lun, fc->lun, sizeof(piu->lun)); + si_memcpy(piu->cdb, fc->cdb, MIN(sizeof(piu->cdb), + 16 + fc->additionalCdbLen)); + piu->efb_tp_taskAttribute = fc->taskAttribute; + piu->additionalCdbLen = fc->additionalCdbLen; + + /* Mask DIR for Read/Write command */ + Dir |= fc->agRequestType & AGSA_DIR_MASK; + + /* set TLR */ + Dir |= fc->flag & TLR_MASK; + if (fc->agRequestType & AGSA_MSG) + { + /* set M bit */ + Dir |= AGSA_MSG_BIT; + } + + /* Setup SGL */ + if (fc->dataLength) + { + SA_DBG5(("saSuperSSPSend: Ext mode, agSgl %08x:%08x (%x/%x)\n", + pSgl->sgUpper, pSgl->sgLower, pSgl->len, pSgl->extReserved)); + + si_memcpy((&(pPayload->SSPIu[0]) + sspiul), pSgl, sizeof(*pSgl)); + } + else //? + { + /* no data transfer */ + //pPayload->dataLen = 0; + si_memset((&(pPayload->SSPIu[0]) + sspiul), 0, sizeof(*pSgl)); + } + SA_ASSERT((smIS_SPC(agRoot)), "smIS_SPC"); + opCode = OPC_INB_SSPINIEXTIOSTART; + break; + } + + default: + { + SA_DBG1(("saSuperSSPSend: Unsupported Request IOMB\n")); + ret = AGSA_RC_FAILURE; + SA_ASSERT((0), ""); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2G"); + goto ext; + } + } + + OSSA_WRITE_LE_32(agRoot, pMessage, offsetTag, pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, pMessage, offsetDeviceId, pDevice->DeviceMapIndex); + OSSA_WRITE_LE_32(agRoot, pMessage, offsetDataLen, fc->dataLength); + OSSA_WRITE_LE_32(agRoot, pMessage, offsetDir, Dir); + + if (fr->beforePI[inq] == -1) + { + /* save the new IBQ' PI */ + fr->beforePI[inq] = saGetIBQPI(agRoot, inq); + fr->inqList[fr->inqMax++] = inq; + } + + /* post the IOMB to SPC */ + ret = mpiMsgPrepare(circularQ, (void *)pMessage, MPI_CATEGORY_SAS_SATA, + opCode, outq, 0); + if (AGSA_RC_SUCCESS != ret) + { + SA_ASSERT((0), ""); + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* Remove the request from pendingIORequests list */ + saLlistIORemove(&pDevice->pendingIORequests, &pRequest->linkNode); + + /* Add the request to the free list of the device */ + saLlistIOAdd(&saRoot->freeIORequests, &pRequest->linkNode); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("saFastSSPPrepare: error when post SSP IOMB\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "2G"); + goto ext; + } + + /* Add the request to the pendingFastIORequests list of the device */ + saLlistIOAdd(&fr->requests, &pRequest->fastLink); + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "2G"); + +ext: + if (fr && ret != AGSA_RC_SUCCESS) + { + saFastSSPCancel(fr); + ioh = 0; + } + OSSA_INP_LEAVE(agRoot); + return ioh; +} /* saFastSSPPrepare */ + +GLOBAL bit32 saFastSSPSend(void *ioHandle) +{ + bit8 inq; + agsaRoot_t *agRoot; + agsaLLRoot_t *saRoot; + saFastRequest_t *fr; + bit32 i; + + SA_ASSERT((ioHandle), ""); + fr = (saFastRequest_t*)ioHandle; + agRoot = (agsaRoot_t*)fr->agRoot; + SA_ASSERT((agRoot), ""); + saRoot = (agsaLLRoot_t*)agRoot->sdkData; + SA_ASSERT((saRoot), ""); + + SA_DBG4(("Entering function saFastSSPSend:\n")); + + for (i = 0; i < fr->inqMax; i++) + { + inq = INQ(fr->inqList[i]); + /* FW interrupt */ + mpiIBQMsgSend(&saRoot->inboundQueue[inq]); + } + /* IORequests are freed in siIODone() */ + + siFastSSPReqFree(agRoot, fr); + return AGSA_RC_SUCCESS; +} /* saFastSSPSend */ +#endif + +/******************************************************************************/ +/*! \brief Start SSP request + * + * Start SSP request + * + * \param agRoot handles for this instance of SAS/SATA LLL + * \param queueNum + * \param agIORequest + * \param agDevHandle + * \param agRequestType + * \param agRequestBody + * \param agTMRequest valid for task management + * \param agCB + * + * \return If request is started successfully + * - \e AGSA_RC_SUCCESS request is started successfully + * - \e AGSA_RC_BUSY request is not started successfully + */ +/******************************************************************************/ +GLOBAL bit32 saSSPStart( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 queueNum, + agsaDevHandle_t *agDevHandle, + bit32 agRequestType, + agsaSASRequestBody_t *agRequestBody, + agsaIORequest_t *agTMRequest, + ossaSSPCompletedCB_t agCB) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); +#ifdef LOOPBACK_MPI + mpiOCQueue_t *circularOQ = agNULL; +#endif + mpiICQueue_t *circularQ = agNULL; + agsaDeviceDesc_t *pDevice = agNULL; + agsaPort_t *pPort = agNULL; + agsaIORequestDesc_t *pRequest = agNULL; + agsaSgl_t *pSgl = agNULL; + void *pMessage = agNULL; + bit32 ret = AGSA_RC_SUCCESS, retVal = 0; + bit32 DirDW4 = 0; /* no data and no AutoGR */ + bit32 encryptFlags = 0; + bit16 size = 0; + bit16 opCode = 0; + bit8 inq = 0, outq = 0; + + + OSSA_INP_ENTER(agRoot); + smTraceFuncEnter(hpDBG_VERY_LOUD,"Sa"); + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + SA_ASSERT((agNULL != agIORequest), ""); + SA_ASSERT((agNULL != agDevHandle), ""); + SA_ASSERT((agNULL != agRequestBody), ""); + + DBG_DUMP_SSPSTART_CMDIU(agDevHandle,agRequestType,agRequestBody); + + /* Find the outgoing port for the device */ + pDevice = (agsaDeviceDesc_t *) (agDevHandle->sdkData); + + if(pDevice == agNULL ) + { + SA_ASSERT((pDevice), "pDevice"); + ret = AGSA_RC_FAILURE; + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Sa"); + goto ext; + } + + pPort = pDevice->pPort; + /* Assign inbound and outbound Buffer */ + inq = (bit8)(queueNum & MPI_IB_NUM_MASK); + outq = (bit8)((queueNum & MPI_OB_NUM_MASK) >> MPI_OB_SHIFT); + SA_ASSERT((AGSA_MAX_INBOUND_Q > inq), "The IBQ Number is out of range."); + + SA_DBG3(("saSSPStart: inq %d outq %d deviceId 0x%x\n", inq,outq,pDevice->DeviceMapIndex)); + + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); + + /* If no LL IO request entry available */ + if ( agNULL == pRequest ) + { + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + SA_DBG1(("saSSPStart, No request from free list\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "Sa"); + ret = AGSA_RC_BUSY; + goto ext; + } + /* If LL IO request entry avaliable */ + else + { + /* Remove the request from free list */ + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + /* Add the request to the pendingIORequests list of the device */ + saLlistIOAdd(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_ASSERT((!pRequest->valid), "The pRequest is in use"); + + SA_DBG3(("saSSPStart, request %p\n", pRequest )); + + /* Decode the flag settings in the standard I/O requests to decide what size we need. */ + /* All other requests will be fine with only 64 byte messages. */ + switch ( agRequestType ) + { + case AGSA_SSP_INIT_READ: + case AGSA_SSP_INIT_WRITE: + case AGSA_SSP_INIT_NONDATA: + case AGSA_SSP_INIT_READ_M: + case AGSA_SSP_INIT_WRITE_M: + { + agsaSSPInitiatorRequest_t *pIRequest = &(agRequestBody->sspInitiatorReq); + + if ((pIRequest->flag & AGSA_SAS_ENABLE_ENCRYPTION) || +#ifdef SAFLAG_USE_DIF_ENC_IOMB + (pIRequest->flag & AGSA_SAS_USE_DIF_ENC_OPSTART) || +#endif /* SAFLAG_USE_DIF_ENC_IOMB */ + (pIRequest->flag & AGSA_SAS_ENABLE_DIF) ) + { + opCode = OPC_INB_SSP_DIF_ENC_OPSTART; + size = IOMB_SIZE128; + } + else + { + opCode = OPC_INB_SSPINIIOSTART; + size = IOMB_SIZE64; + } + break; + } + case AGSA_SSP_INIT_READ_EXT: + case AGSA_SSP_INIT_WRITE_EXT: + case AGSA_SSP_INIT_READ_EXT_M: + case AGSA_SSP_INIT_WRITE_EXT_M: + { + agsaSSPInitiatorRequestExt_t *pIRequest = &(agRequestBody->sspInitiatorReqExt); + + if ((pIRequest->flag & AGSA_SAS_ENABLE_ENCRYPTION) || + (pIRequest->flag & AGSA_SAS_ENABLE_DIF) || +#ifdef SAFLAG_USE_DIF_ENC_IOMB + (pIRequest->flag & AGSA_SAS_USE_DIF_ENC_OPSTART) || +#endif /* SAFLAG_USE_DIF_ENC_IOMB */ + (pIRequest->flag & AGSA_SAS_ENABLE_SKIP_MASK)) + { + opCode = OPC_INB_SSP_DIF_ENC_OPSTART; + size = IOMB_SIZE128; + } + else + { + SA_ASSERT((smIS_SPC(agRoot)), "smIS_SPC"); + opCode = OPC_INB_SSPINIEXTIOSTART; + size = IOMB_SIZE96; + } + break; + } + case AGSA_SSP_INIT_READ_INDIRECT: + case AGSA_SSP_INIT_WRITE_INDIRECT: + case AGSA_SSP_INIT_READ_INDIRECT_M: + case AGSA_SSP_INIT_WRITE_INDIRECT_M: + { + SA_DBG3(("saSSPStart: agRequestType 0x%X INDIRECT\n", agRequestType)); + opCode = OPC_INB_SSP_DIF_ENC_OPSTART; + size = IOMB_SIZE128; + break; + } + case (AGSA_SSP_REQTYPE | AGSA_SSP_TASK_MGNT): + case AGSA_SSP_TASK_MGNT_REQ_M: + case AGSA_SSP_TGT_READ_DATA: + case AGSA_SSP_TGT_READ_GOOD_RESP: + case AGSA_SSP_TGT_WRITE_DATA: + case AGSA_SSP_TGT_WRITE_GOOD_RESP: + case AGSA_SSP_TGT_CMD_OR_TASK_RSP: + + SA_DBG3(("saSSPStart: agRequestType 0x%X (was default)\n", agRequestType)); + opCode = OPC_INB_SSPINIIOSTART; + size = IOMB_SIZE64; + break; + default: + SA_DBG1(("saSSPStart: agRequestType UNKNOWN 0x%X\n", agRequestType)); + /* OpCode is not used in this case, but Linux complains if it is not initialized. */ + opCode = OPC_INB_SSPINIIOSTART; + size = IOMB_SIZE64; + break; + } + + /* If free IOMB avaliable, set up pRequest*/ + pRequest->valid = agTRUE; + pRequest->pIORequestContext = agIORequest; + pRequest->pDevice = pDevice; + pRequest->requestType = agRequestType; + pRequest->pPort = pPort; + pRequest->startTick = saRoot->timeTick; + pRequest->completionCB = agCB; + + /* Set request to the sdkData of agIORequest */ + agIORequest->sdkData = pRequest; + + /* save tag and IOrequest pointer to IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedEnter(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + + /* Get a free inbound queue entry */ +#ifdef LOOPBACK_MPI + if (loopback) + { + SA_DBG2(("saSSPStart: did %d ioq %d / %d tag %d\n", pDevice->DeviceMapIndex, inq, outq, pRequest->HTag)); + circularOQ = &saRoot->outboundQueue[outq]; + retVal = mpiMsgFreeGetOQ(circularOQ, size, &pMessage); + } + else +#endif /* LOOPBACK_MPI */ + { + circularQ = &saRoot->inboundQueue[inq]; + retVal = mpiMsgFreeGet(circularQ, size, &pMessage); + } + + /* if message size is too large return failure */ + if (AGSA_RC_FAILURE == retVal) + { +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + /* if not sending return to free list rare */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + pRequest->valid = agFALSE; + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("saSSPStart, error when get free IOMB\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "Sa"); + ret = AGSA_RC_FAILURE; + goto ext; + } + + /* return busy if inbound queue is full */ + if (AGSA_RC_BUSY == retVal) + { +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + /* if not sending return to free list rare */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + pRequest->valid = agFALSE; + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("saSSPStart, no more IOMB\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "Sa"); + ret = AGSA_RC_BUSY; + goto ext; + } + SA_DBG3(("saSSPStart:agRequestType %X\n" ,agRequestType)); + + switch ( agRequestType ) + { + case AGSA_SSP_INIT_READ: + case AGSA_SSP_INIT_WRITE: + case AGSA_SSP_INIT_NONDATA: + case AGSA_SSP_INIT_READ_EXT: + case AGSA_SSP_INIT_WRITE_EXT: + case AGSA_SSP_INIT_READ_M: + case AGSA_SSP_INIT_WRITE_M: + case AGSA_SSP_INIT_READ_EXT_M: + case AGSA_SSP_INIT_WRITE_EXT_M: + case AGSA_SSP_INIT_READ_INDIRECT: + case AGSA_SSP_INIT_WRITE_INDIRECT: + case AGSA_SSP_INIT_READ_INDIRECT_M: + case AGSA_SSP_INIT_WRITE_INDIRECT_M: + { + if (!(agRequestType & AGSA_SSP_EXT_BIT)) + { + agsaSSPInitiatorRequest_t *pIRequest = &(agRequestBody->sspInitiatorReq); + agsaSSPIniIOStartCmd_t *pPayload = (agsaSSPIniIOStartCmd_t *)pMessage; + agsaSSPIniEncryptIOStartCmd_t *pEncryptPayload = (agsaSSPIniEncryptIOStartCmd_t *)pMessage; + + /* Most fields for the SAS IOMB have the same offset regardless of the actual IOMB used. */ + /* Be careful with the scatter/gather lists, encryption and DIF options. */ + +/* if( pIRequest->sspCmdIU.cdb[ 0] == 0x28 || pIRequest->sspCmdIU.cdb[0]== 0x2A) + { + pRequest->requestBlock = ((pIRequest->sspCmdIU.cdb[2] << 24 ) | + (pIRequest->sspCmdIU.cdb[3] << 16 ) | + (pIRequest->sspCmdIU.cdb[4] << 8 ) | + (pIRequest->sspCmdIU.cdb[5] ) ); + } +*/ +#ifdef LOOPBACK_MPI + if (loopback) + { + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPCompletionRsp_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPCompletionRsp_t, status), OSSA_IO_SUCCESS); + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPCompletionRsp_t, param), 0); + //OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPCompletionRsp_t, SSPTag), 0); + } + else +#endif /* LOOPBACK_MPI */ + { + /* SSPIU less equal 28 bytes */ + /* Configure DWORD 1 */ + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPIniIOStartCmd_t, tag), pRequest->HTag); + /* Configure DWORD 2 */ + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPIniIOStartCmd_t, deviceId), pDevice->DeviceMapIndex); + /* Configure DWORD 3 */ + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPIniIOStartCmd_t, dataLen), pIRequest->dataLength); + } + +#ifdef SA_TESTBASE_EXTRA + /* TestBase - Set the host BST entry */ + DirDW4 |= ((UINT32)pIRequest->bstIndex) << 16; +#endif /* SA_TESTBASE_EXTRA */ + + if (!(agRequestType & AGSA_SSP_INDIRECT_BIT)) + { + /* Configure DWORD 5-12 */ + si_memcpy(&pPayload->SSPInfoUnit, &pIRequest->sspCmdIU, sizeof(pPayload->SSPInfoUnit)); + pPayload->dirMTlr = 0; + /* Mask DIR for Read/Write command */ + /* Configure DWORD 4 bit 8-9 */ + DirDW4 |= agRequestType & AGSA_DIR_MASK; + } + else /* AGSA_SSP_INDIRECT_BIT was set */ + { + + agsaSSPInitiatorRequestIndirect_t *pIndRequest = &(agRequestBody->sspInitiatorReqIndirect); + + /* Configure DWORD 5 */ + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPIniEncryptIOStartCmd_t,sspiu_0_3_indcdbalL ),pIndRequest->sspInitiatorReqAddrLower32); + /* Configure DWORD 6 */ + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPIniEncryptIOStartCmd_t,sspiu_4_7_indcdbalH ),pIndRequest->sspInitiatorReqAddrUpper32 ); + /* Configure DWORD 7 */ + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPIniEncryptIOStartCmd_t,sspiu_8_11 ), 0); + /* Configure DWORD 8 */ + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPIniEncryptIOStartCmd_t,sspiu_12_15 ), 0); + /* Configure DWORD 9 */ + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPIniEncryptIOStartCmd_t,sspiu_16_19 ), 0); + /* Configure DWORD 10 */ + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPIniEncryptIOStartCmd_t,sspiu_19_23), 0); + /* Configure DWORD 11 */ + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPIniEncryptIOStartCmd_t,sspiu_24_27 ), 0); + /* Mask DIR for Read/Write command */ + /* Configure DWORD 4 bit 8-9 */ + DirDW4 |= agRequestType & AGSA_DIR_MASK; + /* Configure DWORD 4 bit 24-31 */ + DirDW4 |= ((pIndRequest->sspInitiatorReqLen >> 2) & 0xFF) << SHIFT24; + /* Configure DWORD 4 bit 4 */ + DirDW4 |= 1 << SHIFT3; + } + + /* set TLR */ + DirDW4 |= pIRequest->flag & TLR_MASK; + if (agRequestType & AGSA_MSG) + { + /* set M bit */ + DirDW4 |= AGSA_MSG_BIT; + } + + /* check for skipmask operation */ + if (pIRequest->flag & AGSA_SAS_ENABLE_SKIP_MASK) + { + DirDW4 |= AGSA_SKIP_MASK_BIT; + /* agsaSSPInitiatorRequestIndirect_t skip mask in flag is offset 5 */ + DirDW4 |= (pIRequest->flag & AGSA_SAS_SKIP_MASK_OFFSET) << SHIFT8; + } + + + /* Configure DWORDS 12-14 */ + if( pIRequest->encrypt.enableEncryptionPerLA && pIRequest->dif.enableDIFPerLA) + { + OSSA_WRITE_LE_32(agRoot, pPayload, /* DWORD 12 */ + OSSA_OFFSET_OF(agsaSSPIniEncryptIOStartCmd_t,epl_descL ), + pIRequest->encrypt.EncryptionPerLAAddrLo ); + OSSA_WRITE_LE_32(agRoot, pPayload, /* DWORD 13 */ + OSSA_OFFSET_OF(agsaSSPIniEncryptIOStartCmd_t,dpl_descL ), + pIRequest->dif.DIFPerLAAddrLo ); + + SA_ASSERT(pIRequest->encrypt.EncryptionPerLAAddrHi == pIRequest->dif.DIFPerLAAddrHi, "EPL DPL hi region must be equal"); + + if( pIRequest->encrypt.EncryptionPerLAAddrHi != pIRequest->dif.DIFPerLAAddrHi ) + { + + SA_DBG1(("saSSPStart: EPL DPL hi region must be equal AGSA_RC_FAILURE\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "Sa"); + ret = AGSA_RC_FAILURE; + goto ext; + } + + OSSA_WRITE_LE_32(agRoot, pPayload, /* DWORD 14 */ + OSSA_OFFSET_OF(agsaSSPIniEncryptIOStartCmd_t,edpl_descH ), + pIRequest->encrypt.EncryptionPerLAAddrHi ); + } + else if( pIRequest->encrypt.enableEncryptionPerLA) + { + OSSA_WRITE_LE_32(agRoot, pPayload, /* DWORD 12 */ + OSSA_OFFSET_OF(agsaSSPIniEncryptIOStartCmd_t,epl_descL ), + pIRequest->encrypt.EncryptionPerLAAddrLo ); + OSSA_WRITE_LE_32(agRoot, pPayload, /* DWORD 13 */ + OSSA_OFFSET_OF(agsaSSPIniEncryptIOStartCmd_t,dpl_descL ), + 0); + OSSA_WRITE_LE_32(agRoot, pPayload, /* DWORD 14 */ + OSSA_OFFSET_OF(agsaSSPIniEncryptIOStartCmd_t,edpl_descH ), + pIRequest->encrypt.EncryptionPerLAAddrHi ); + } + else if (pIRequest->dif.enableDIFPerLA) /* configure DIF */ + { + OSSA_WRITE_LE_32(agRoot, pPayload, /* DWORD 12 */ + OSSA_OFFSET_OF(agsaSSPIniEncryptIOStartCmd_t,epl_descL ), + 0); + OSSA_WRITE_LE_32(agRoot, pPayload, /* DWORD 13 */ + OSSA_OFFSET_OF(agsaSSPIniEncryptIOStartCmd_t,dpl_descL ), + pIRequest->dif.DIFPerLAAddrLo ); + OSSA_WRITE_LE_32(agRoot, pPayload, /* DWORD 14 */ + OSSA_OFFSET_OF(agsaSSPIniEncryptIOStartCmd_t,edpl_descH ), + pIRequest->dif.DIFPerLAAddrHi); + } + else /* Not EPL or DPL */ + { + OSSA_WRITE_LE_32(agRoot, pPayload, /* DWORD 12 */ + OSSA_OFFSET_OF(agsaSSPIniEncryptIOStartCmd_t,epl_descL ), + 0); + OSSA_WRITE_LE_32(agRoot, pPayload, /* DWORD 13 */ + OSSA_OFFSET_OF(agsaSSPIniEncryptIOStartCmd_t,dpl_descL ), + 0); + OSSA_WRITE_LE_32(agRoot, pPayload, /* DWORD 14 */ + OSSA_OFFSET_OF(agsaSSPIniEncryptIOStartCmd_t,edpl_descH ), + 0); + } + + if (pIRequest->flag & AGSA_SAS_ENABLE_DIF) + { + bit32 UDTR1_UDTR0_UDT1_UDT0 = 0; + bit32 UDT5_UDT4_UDT3_UDT2 = 0; + bit32 UDTR5_UDTR4_UDTR3_UDTR2 = 0; + + SA_DBG3(("saSSPStart,DIF enableRefBlockCount ref %d enableRefBlockCount %d enableCrc %d enableCrcInversion %d\n", + pIRequest->dif.flags & DIF_FLAG_BITS_UDTR_REF_BLKCOUNT ? 1 : 0, + pIRequest->dif.flags & DIF_FLAG_BITS_UDTR_REF_BLKCOUNT ? 1 : 0, + pIRequest->dif.flags & DIF_FLAG_BITS_CRC_VER ? 1 : 0, + pIRequest->dif.flags & DIF_FLAG_BITS_CRC_INV ? 1 : 0 )); + + SA_DBG3(("saSSPStart,DIF initialIOSeed %X lbSize %X difAction %X\n", + pIRequest->dif.flags & DIF_FLAG_BITS_CRC_SEED ? 1 : 0, + (pIRequest->dif.flags & DIF_FLAG_BITS_BLOCKSIZE_MASK) >> DIF_FLAG_BITS_BLOCKSIZE_SHIFT, + pIRequest->dif.flags & DIF_FLAG_BITS_ACTION )); + + SA_DBG3(("saSSPStart,DIF udtArray %2X %2X %2X %2X %2X %2X\n", + pIRequest->dif.udtArray[0], + pIRequest->dif.udtArray[1], + pIRequest->dif.udtArray[2], + pIRequest->dif.udtArray[3], + pIRequest->dif.udtArray[4], + pIRequest->dif.udtArray[5])); + + SA_DBG3(("saSSPStart,DIF udrtArray %2X %2X %2X %2X %2X %2X\n", + pIRequest->dif.udrtArray[0], + pIRequest->dif.udrtArray[1], + pIRequest->dif.udrtArray[2], + pIRequest->dif.udrtArray[3], + pIRequest->dif.udrtArray[4], + pIRequest->dif.udrtArray[5])); + + SA_DBG3(("saSSPStart,DIF tagUpdateMask %X tagVerifyMask %X DIFPerLAAddrLo %X DIFPerLAAddrHi %X\n", + (pIRequest->dif.flags & DIF_FLAG_BITS_UDTVMASK) >> DIF_FLAG_BITS_UDTV_SHIFT, + (pIRequest->dif.flags & DIF_FLAG_BITS_UDTUPMASK) >> DIF_FLAG_BITS_UDTUPSHIFT, + pIRequest->dif.DIFPerLAAddrLo, + pIRequest->dif.DIFPerLAAddrHi)); + + DirDW4 |= AGSA_DIF_BIT; + + /* DWORD 15 */ + SA_DBG3(("saSSPStart, DW 15 DIF_flags 0x%08X\n", pIRequest->dif.flags )); + + OSSA_WRITE_LE_32(agRoot, pPayload, + OSSA_OFFSET_OF(agsaSSPIniEncryptIOStartCmd_t, DIF_flags), + pIRequest->dif.flags); + + /* Populate the UDT and UDTR bytes as necessary. */ + if ((pIRequest->dif.flags & DIF_FLAG_BITS_ACTION) != AGSA_DIF_INSERT) + { + UDTR1_UDTR0_UDT1_UDT0 = (pIRequest->dif.udtArray[1] << SHIFT8 | + pIRequest->dif.udtArray[0]); + UDT5_UDT4_UDT3_UDT2 = (pIRequest->dif.udtArray[5] << SHIFT24 | + pIRequest->dif.udtArray[4] << SHIFT16 | + pIRequest->dif.udtArray[3] << SHIFT8 | + pIRequest->dif.udtArray[2]); + } + + if ((pIRequest->dif.flags & DIF_FLAG_BITS_ACTION) == AGSA_DIF_INSERT || + (pIRequest->dif.flags & DIF_FLAG_BITS_ACTION) == AGSA_DIF_VERIFY_REPLACE || + (pIRequest->dif.flags & DIF_FLAG_BITS_ACTION) == AGSA_DIF_REPLACE_UDT_REPLACE_CRC) + { + UDTR1_UDTR0_UDT1_UDT0 |= (pIRequest->dif.udrtArray[1] << SHIFT24 | + pIRequest->dif.udrtArray[0] << SHIFT16 ); + UDTR5_UDTR4_UDTR3_UDTR2 = (pIRequest->dif.udrtArray[5] << SHIFT24 | + pIRequest->dif.udrtArray[4] << SHIFT16 | + pIRequest->dif.udrtArray[3] << SHIFT8 | + pIRequest->dif.udrtArray[2]); + } + + /* DWORD 16 is UDT3, UDT2, UDT1 and UDT0 */ + OSSA_WRITE_LE_32(agRoot, pPayload, + OSSA_OFFSET_OF(agsaSSPIniEncryptIOStartCmd_t, udt), + UDTR1_UDTR0_UDT1_UDT0); + + /* DWORD 17 is UDT5, UDT4, UDT3 and UDT2 */ + OSSA_WRITE_LE_32(agRoot, pPayload, + OSSA_OFFSET_OF(agsaSSPIniEncryptIOStartCmd_t, udtReplacementLo), + UDT5_UDT4_UDT3_UDT2); + + /* DWORD 18 is UDTR5, UDTR4, UDTR3 and UDTR2 */ + OSSA_WRITE_LE_32(agRoot, pPayload, + OSSA_OFFSET_OF(agsaSSPIniEncryptIOStartCmd_t, udtReplacementHi), + UDTR5_UDTR4_UDTR3_UDTR2); + + /* DWORD 19 */ + /* Get IOS IOSeed enable bit */ + if( pIRequest->dif.enableDIFPerLA || + (pIRequest->dif.flags & DIF_FLAG_BITS_CUST_APP_TAG) ) + { + OSSA_WRITE_LE_32(agRoot, pPayload, + OSSA_OFFSET_OF(agsaSSPIniEncryptIOStartCmd_t, DIF_seed), + ((pIRequest->dif.DIFPerLARegion0SecCount << SHIFT16) | + (pIRequest->dif.flags & DIF_FLAG_BITS_CRC_SEED ? pIRequest->dif.initialIOSeed : 0 ))); + } + else + { + if (pIRequest->dif.flags & DIF_FLAG_BITS_CRC_SEED) + { + OSSA_WRITE_LE_32(agRoot, pPayload, + OSSA_OFFSET_OF(agsaSSPIniEncryptIOStartCmd_t, DIF_seed), + pIRequest->dif.initialIOSeed ); + } + else + { + OSSA_WRITE_LE_32(agRoot, pPayload, + OSSA_OFFSET_OF(agsaSSPIniEncryptIOStartCmd_t, DIF_seed), 0 ); + } + } + } + + /* configure encryption */ + if (pIRequest->flag & AGSA_SAS_ENABLE_ENCRYPTION) + { + + SA_DBG3(("saSSPStart,ENC dekTable 0x%08X dekIndex 0x%08X\n", + pIRequest->encrypt.dekInfo.dekTable, + pIRequest->encrypt.dekInfo.dekIndex)); + + SA_DBG3(("saSSPStart,ENC kekIndex 0x%08X sectorSizeIndex 0x%08X cipherMode 0x%08X\n", + pIRequest->encrypt.kekIndex, + pIRequest->encrypt.sectorSizeIndex, + pIRequest->encrypt.cipherMode)); + + SA_DBG3(("saSSPStart,ENC keyTag_W0 0x%08X keyTag_W1 0x%08X\n", + pIRequest->encrypt.keyTag_W0, + pIRequest->encrypt.keyTag_W1)); + SA_DBG3(("saSSPStart,ENC tweakVal_W0 0x%08X tweakVal_W1 0x%08X\n", + pIRequest->encrypt.tweakVal_W0, + pIRequest->encrypt.tweakVal_W1)); + SA_DBG3(("saSSPStart,ENC tweakVal_W2 0x%08X tweakVal_W3 0x%08X\n", + pIRequest->encrypt.tweakVal_W2, + pIRequest->encrypt.tweakVal_W3)); + + DirDW4 |= AGSA_ENCRYPT_BIT; + + encryptFlags = 0; + + if (pIRequest->encrypt.keyTagCheck == agTRUE) + { + encryptFlags |= AGSA_ENCRYPT_KEY_TAG_BIT; + } + + if( pIRequest->encrypt.cipherMode == agsaEncryptCipherModeXTS ) + { + encryptFlags |= AGSA_ENCRYPT_XTS_Mode << SHIFT4; + } + + encryptFlags |= pIRequest->encrypt.dekInfo.dekTable << SHIFT2; + + /* Always use encryption for DIF fields, skip SKPD */ + + encryptFlags |= (pIRequest->encrypt.dekInfo.dekIndex & 0xFFFFFF) << SHIFT8; + /* Configure DWORD 20 */ + OSSA_WRITE_LE_32(agRoot, pPayload, + OSSA_OFFSET_OF(agsaSSPIniEncryptIOStartCmd_t, encryptFlagsLo), + encryptFlags); + + encryptFlags = pIRequest->encrypt.sectorSizeIndex; + + encryptFlags |= (pIRequest->encrypt.kekIndex) << SHIFT5; + + encryptFlags |= (pIRequest->encrypt.EncryptionPerLRegion0SecCount) << SHIFT16; + /* Configure DWORD 21 */ + OSSA_WRITE_LE_32(agRoot, pPayload, + OSSA_OFFSET_OF(agsaSSPIniEncryptIOStartCmd_t, encryptFlagsHi), + encryptFlags); + + /* Configure DWORD 22 */ + OSSA_WRITE_LE_32(agRoot, pPayload, + OSSA_OFFSET_OF(agsaSSPIniEncryptIOStartCmd_t, keyTag_W0), + pIRequest->encrypt.keyTag_W0); + /* Configure DWORD 23 */ + OSSA_WRITE_LE_32(agRoot, pPayload, + OSSA_OFFSET_OF(agsaSSPIniEncryptIOStartCmd_t, keyTag_W1), + pIRequest->encrypt.keyTag_W1); + + /* Configure DWORD 24 */ + OSSA_WRITE_LE_32(agRoot, pPayload, + OSSA_OFFSET_OF(agsaSSPIniEncryptIOStartCmd_t, tweakVal_W0), + pIRequest->encrypt.tweakVal_W0); + /* Configure DWORD 25 */ + OSSA_WRITE_LE_32(agRoot, pPayload, + OSSA_OFFSET_OF(agsaSSPIniEncryptIOStartCmd_t, tweakVal_W1), + pIRequest->encrypt.tweakVal_W1); + /* Configure DWORD 26 */ + OSSA_WRITE_LE_32(agRoot, pPayload, + OSSA_OFFSET_OF(agsaSSPIniEncryptIOStartCmd_t, tweakVal_W2), + pIRequest->encrypt.tweakVal_W2); + /* Configure DWORD 27 */ + OSSA_WRITE_LE_32(agRoot, pPayload, + OSSA_OFFSET_OF(agsaSSPIniEncryptIOStartCmd_t, tweakVal_W3), + pIRequest->encrypt.tweakVal_W3); + } + + /* Setup SGL */ + if (pIRequest->dataLength) + { + pSgl = &(pIRequest->agSgl); + + SA_DBG3(("saSSPStart:opCode %X agSgl %08x:%08x (%x/%x)\n",opCode, + pSgl->sgUpper, pSgl->sgLower, pSgl->len, pSgl->extReserved)); + + /* Get DIF PER LA flag */ + DirDW4 |= (pIRequest->dif.enableDIFPerLA ? (1 << SHIFT7) : 0); + DirDW4 |= (pIRequest->encrypt.enableEncryptionPerLA ? ( 1 << SHIFT12 ) : 0); + /* Configure DWORD 4 */ + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPIniIOStartCmd_t, dirMTlr), DirDW4); + + if (opCode == OPC_INB_SSP_DIF_ENC_OPSTART) + { + /* Configure DWORD 28 */ + pEncryptPayload->AddrLow0 = pSgl->sgLower; + /* Configure DWORD 29 */ + pEncryptPayload->AddrHi0 = pSgl->sgUpper; + /* Configure DWORD 30 */ + pEncryptPayload->Len0 = pSgl->len; + /* Configure DWORD 31 */ + pEncryptPayload->E0 = pSgl->extReserved; + } + else + { + pPayload->AddrLow0 = pSgl->sgLower; + pPayload->AddrHi0 = pSgl->sgUpper; + pPayload->Len0 = pSgl->len; + pPayload->E0 = pSgl->extReserved; + } + } + else + { + /* no data transfer */ + /* Configure DWORD 4 */ + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPIniIOStartCmd_t, dirMTlr), DirDW4); + + if (opCode == OPC_INB_SSP_DIF_ENC_OPSTART) + { + pEncryptPayload = (agsaSSPIniEncryptIOStartCmd_t *) pPayload; + + pEncryptPayload->AddrLow0 = 0; + pEncryptPayload->AddrHi0 = 0; + pEncryptPayload->Len0 = 0; + pEncryptPayload->E0 = 0; + } + else + { + pPayload->AddrLow0 = 0; + pPayload->AddrHi0 = 0; + pPayload->Len0 = 0; + pPayload->E0 = 0; + } + } + + /* post the IOMB to SPC */ +#ifdef LOOPBACK_MPI + if (loopback) + ret = mpiMsgProduceOQ(circularOQ, (void *)pMessage, MPI_CATEGORY_SAS_SATA, OPC_OUB_SSP_COMP, outq, (bit8)circularQ->priority); + else +#endif /* LOOPBACK_MPI */ + ret = mpiMsgProduce(circularQ, (void *)pMessage, MPI_CATEGORY_SAS_SATA, opCode, outq, (bit8)circularQ->priority); + if (AGSA_RC_FAILURE == ret) + { + SA_DBG1(("saSSPStart, error when post SSP IOMB\n")); + ret = AGSA_RC_FAILURE; + } + } + else + { + /* additionalCdbLen is not zero and type is Ext - use EXT mode */ + agsaSSPInitiatorRequestExt_t *pIRequest = &(agRequestBody->sspInitiatorReqExt); + agsaSSPIniExtIOStartCmd_t *pPayload = (agsaSSPIniExtIOStartCmd_t *)pMessage; + bit32 sspiul; + + /* + * Most fields for the SAS IOMB have the same offset regardless of the actual IOMB used. + * Be careful with the scatter/gather lists, encryption and DIF options. + */ + /* CDB > 16 bytes */ + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPIniExtIOStartCmd_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPIniExtIOStartCmd_t, deviceId), pDevice->DeviceMapIndex); + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPIniExtIOStartCmd_t, dataLen), pIRequest->dataLength); + /* dword (bit7-bit2) ==> bytes (bit7-bit0) */ + /* setup standard CDB bytes + additional CDB bytes in length field */ + sspiul = sizeof(agsaSSPCmdInfoUnit_t) + + (pIRequest->sspCmdIUExt.additionalCdbLen & 0xFC); + DirDW4 = sspiul << 16; + si_memcpy(&pPayload->SSPIu[0], &pIRequest->sspCmdIUExt, sspiul); + pPayload->SSPIuLendirMTlr = 0; + + /* Mask DIR for Read/Write command */ + DirDW4 |= agRequestType & AGSA_DIR_MASK; + + /* set TLR */ + DirDW4 |= pIRequest->flag & TLR_MASK; + if (agRequestType & AGSA_MSG) + { + /* set M bit */ + DirDW4 |= AGSA_MSG_BIT; + } + + /* check for skipmask operation */ + if (pIRequest->flag & AGSA_SAS_ENABLE_SKIP_MASK) + { + SA_ASSERT(0, "Mode not supported"); + } + + /* configure DIF */ + if (pIRequest->flag & AGSA_SAS_ENABLE_DIF) + { + SA_ASSERT(0, "Mode not supported"); + } + + /* configure encryption */ + if (pIRequest->flag & AGSA_SAS_ENABLE_ENCRYPTION) + { + SA_ASSERT(0, "Mode not supported"); + } + /* Setup SGL */ + if (pIRequest->dataLength) + { + pSgl = &(pIRequest->agSgl); + + SA_DBG3(("saSSPStart: Ext mode, agSgl %08x:%08x (%x/%x)\n", + pSgl->sgUpper, pSgl->sgLower, pSgl->len, pSgl->extReserved)); + + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPIniExtIOStartCmd_t, SSPIuLendirMTlr), DirDW4); + + if (opCode == OPC_INB_SSP_DIF_ENC_OPSTART) + { + si_memcpy((&((agsaSSPIniEncryptIOStartCmd_t *)(pPayload))->AddrLow0), pSgl, sizeof(agsaSgl_t)); + } + else + { + si_memcpy((&(pPayload->SSPIu[0]) + sspiul), pSgl, sizeof(agsaSgl_t)); + } + } + else + { + /* no data transfer */ + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPIniExtIOStartCmd_t, SSPIuLendirMTlr), DirDW4); + pPayload->dataLen = 0; + } + + /* post the IOMB to SPC */ + if (AGSA_RC_FAILURE == mpiMsgProduce(circularQ, (void *)pMessage, MPI_CATEGORY_SAS_SATA, opCode, outq,(bit8)circularQ->priority )) + { + SA_DBG1(("saSSPStart, error when post SSP Ext IOMB\n")); + ret = AGSA_RC_FAILURE; + } + } + break; + } + case AGSA_SSP_TASK_MGNT_REQ: + case AGSA_SSP_TASK_MGNT_REQ_M: + { + agsaIORequestDesc_t *pTMRequestToAbort = agNULL; + agsaSSPIniTMStartCmd_t *pPayload = (agsaSSPIniTMStartCmd_t *)pMessage; + + if (agRequestType & AGSA_MSG) + { + /* set M bit */ + DirDW4 = AGSA_MSG_BIT; + } + + /* set DS and ADS bit */ + DirDW4 |= (agRequestBody->sspTaskMgntReq.tmOption & 0x3) << 3; + + /* Prepare the SSP TASK Management payload */ + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPIniTMStartCmd_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPIniTMStartCmd_t, deviceId), pDevice->DeviceMapIndex); + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPIniTMStartCmd_t, relatedTag), agRequestBody->sspTaskMgntReq.tagOfTaskToBeManaged); + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPIniTMStartCmd_t, TMfunction), agRequestBody->sspTaskMgntReq.taskMgntFunction); + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPIniTMStartCmd_t, dsAdsMReport), DirDW4); + pPayload->lun[0] = agRequestBody->sspTaskMgntReq.lun[0]; + pPayload->lun[1] = agRequestBody->sspTaskMgntReq.lun[1]; + pPayload->lun[2] = agRequestBody->sspTaskMgntReq.lun[2]; + pPayload->lun[3] = agRequestBody->sspTaskMgntReq.lun[3]; + pPayload->lun[4] = agRequestBody->sspTaskMgntReq.lun[4]; + pPayload->lun[5] = agRequestBody->sspTaskMgntReq.lun[5]; + pPayload->lun[6] = agRequestBody->sspTaskMgntReq.lun[6]; + pPayload->lun[7] = agRequestBody->sspTaskMgntReq.lun[7]; + + if (agTMRequest) + { + pTMRequestToAbort = (agsaIORequestDesc_t *)agTMRequest->sdkData; + if (pTMRequestToAbort) + { + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPIniTMStartCmd_t, relatedTag), pTMRequestToAbort->HTag); + } + } + + SA_DBG1(("saSSPStart, HTAG 0x%x TM function 0x%x Tag-to-be-aborted 0x%x deviceId 0x%x\n", + pPayload->tag, pPayload->TMfunction, pPayload->relatedTag, pPayload->deviceId)); + + siDumpActiveIORequests(agRoot, saRoot->swConfig.maxActiveIOs); + + /* post the IOMB to SPC */ + if (AGSA_RC_FAILURE == mpiMsgProduce(circularQ, (void *)pMessage, MPI_CATEGORY_SAS_SATA, OPC_INB_SSPINITMSTART, outq, (bit8)circularQ->priority)) + { + SA_DBG1(("saSSPStart, error when post TM IOMB\n")); + ret = AGSA_RC_FAILURE; + } + + break; + } + case AGSA_SSP_TGT_READ_DATA: + case AGSA_SSP_TGT_READ_GOOD_RESP: + case AGSA_SSP_TGT_WRITE_DATA: + case AGSA_SSP_TGT_WRITE_GOOD_RESP: + { + agsaSSPTargetRequest_t *pTRequest = &(agRequestBody->sspTargetReq); + agsaSSPTgtIOStartCmd_t *pPayload = (agsaSSPTgtIOStartCmd_t *)pMessage; + bit32 DirDW5 = 0; + /* Prepare the SSP TGT IO Start payload */ + /* Configure DWORD 1 */ + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPTgtIOStartCmd_t, tag), pRequest->HTag); + /* Configure DWORD 2 */ + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPTgtIOStartCmd_t, deviceId), pDevice->DeviceMapIndex); + /* Configure DWORD 3 */ + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPTgtIOStartCmd_t, dataLen), pTRequest->dataLength); + /* Configure DWORD 4 */ + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPTgtIOStartCmd_t, dataOffset), pTRequest->offset); + + SA_DBG3(("saSSPStart, sspOption %08X\n", pTRequest->sspOption )); + + /* Mask DIR and AutoGR bits for Read/Write command */ + DirDW5 = (agRequestType & (AGSA_DIR_MASK | AGSA_AUTO_MASK)) | (pTRequest->agTag << 16); + + if (pTRequest->sspOption & SSP_OPTION_DIF ) + { + bit32 UDTR1_UDTR0_UDT1_UDT0 = 0; + bit32 UDT5_UDT4_UDT3_UDT2 = 0; + bit32 UDTR5_UDTR4_UDTR3_UDTR2 = 0; + SA_DBG3(("saSSPStart,tgt DIF enableRefBlockCount ref %d enableRefBlockCount %d enableCrc %d enableCrcInversion %d\n", + pTRequest->dif.flags & DIF_FLAG_BITS_UDTR_REF_BLKCOUNT ? 1 : 0, + pTRequest->dif.flags & DIF_FLAG_BITS_UDTR_REF_BLKCOUNT ? 1 : 0, + pTRequest->dif.flags & DIF_FLAG_BITS_CRC_VER ? 1 : 0, + pTRequest->dif.flags & DIF_FLAG_BITS_CRC_INV ? 1 : 0 )); + + SA_DBG3(("saSSPStart,tgt DIF initialIOSeed %X lbSize %X difAction %X\n", + pTRequest->dif.flags & DIF_FLAG_BITS_CRC_SEED ? 1 : 0, + (pTRequest->dif.flags & DIF_FLAG_BITS_BLOCKSIZE_MASK ) >> DIF_FLAG_BITS_BLOCKSIZE_SHIFT, + pTRequest->dif.flags & DIF_FLAG_BITS_ACTION )); + + SA_DBG3(("saSSPStart,tgt DIF udtArray %2X %2X %2X %2X %2X %2X\n", + pTRequest->dif.udtArray[0], + pTRequest->dif.udtArray[1], + pTRequest->dif.udtArray[2], + pTRequest->dif.udtArray[3], + pTRequest->dif.udtArray[4], + pTRequest->dif.udtArray[5])); + + SA_DBG3(("saSSPStart,tgt DIF udrtArray %2X %2X %2X %2X %2X %2X\n", + pTRequest->dif.udrtArray[0], + pTRequest->dif.udrtArray[1], + pTRequest->dif.udrtArray[2], + pTRequest->dif.udrtArray[3], + pTRequest->dif.udrtArray[4], + pTRequest->dif.udrtArray[5])); + + SA_DBG3(("saSSPStart,tgt DIF tagUpdateMask %X tagVerifyMask %X DIFPerLAAddrLo %X DIFPerLAAddrHi %X\n", + (pTRequest->dif.flags & DIF_FLAG_BITS_UDTVMASK) >> DIF_FLAG_BITS_UDTV_SHIFT, + (pTRequest->dif.flags & DIF_FLAG_BITS_UDTUPMASK) >> DIF_FLAG_BITS_UDTUPSHIFT, + pTRequest->dif.DIFPerLAAddrLo, + pTRequest->dif.DIFPerLAAddrHi)); + + DirDW5 |= AGSA_SSP_TGT_BITS_DEE_DIF; + + + SA_DBG3(("saSSPStart,tgt DW 15 DIF_flags 0x%08X\n", pTRequest->dif.flags )); + + OSSA_WRITE_LE_32(agRoot, pPayload, + OSSA_OFFSET_OF(agsaSSPTgtIOStartCmd_t, DIF_flags), + pTRequest->dif.flags); + + /* Populate the UDT and UDTR bytes as necessary. */ + if ((pTRequest->dif.flags & DIF_FLAG_BITS_ACTION) != AGSA_DIF_INSERT) + { + UDTR1_UDTR0_UDT1_UDT0 = (pTRequest->dif.udtArray[1] << SHIFT8 | + pTRequest->dif.udtArray[0]); + UDT5_UDT4_UDT3_UDT2 = (pTRequest->dif.udtArray[5] << SHIFT24 | + pTRequest->dif.udtArray[4] << SHIFT16 | + pTRequest->dif.udtArray[3] << SHIFT8 | + pTRequest->dif.udtArray[2]); + } + + if ((pTRequest->dif.flags & DIF_FLAG_BITS_ACTION) == AGSA_DIF_INSERT || + (pTRequest->dif.flags & DIF_FLAG_BITS_ACTION) == AGSA_DIF_VERIFY_REPLACE || + (pTRequest->dif.flags & DIF_FLAG_BITS_ACTION) == AGSA_DIF_REPLACE_UDT_REPLACE_CRC) + { + UDTR1_UDTR0_UDT1_UDT0 |= (pTRequest->dif.udrtArray[1] << SHIFT24 | + pTRequest->dif.udrtArray[0] << SHIFT16 ); + UDTR5_UDTR4_UDTR3_UDTR2 = (pTRequest->dif.udrtArray[5] << SHIFT24 | + pTRequest->dif.udrtArray[4] << SHIFT16 | + pTRequest->dif.udrtArray[3] << SHIFT8 | + pTRequest->dif.udrtArray[2]); + } + /* DWORD 8 is UDTR1, UDTR0, UDT1 and UDT0 */ + OSSA_WRITE_LE_32(agRoot, pPayload, + OSSA_OFFSET_OF(agsaSSPTgtIOStartCmd_t, udt), + UDTR1_UDTR0_UDT1_UDT0); + + /* DWORD 9 is UDT5, UDT4, UDT3 and UDT2 */ + OSSA_WRITE_LE_32(agRoot, pPayload, + OSSA_OFFSET_OF(agsaSSPTgtIOStartCmd_t, udtReplacementLo), + UDT5_UDT4_UDT3_UDT2); + + /* DWORD 10 is UDTR5, UDTR4, UDTR3 and UDTR2 */ + OSSA_WRITE_LE_32(agRoot, pPayload, + OSSA_OFFSET_OF(agsaSSPTgtIOStartCmd_t, udtReplacementHi), + UDTR5_UDTR4_UDTR3_UDTR2); + /* DWORD 11 */ + /* Get IOS IOSeed enable bit */ + if( pTRequest->dif.flags & DIF_FLAG_BITS_CUST_APP_TAG) + { + OSSA_WRITE_LE_32(agRoot, pPayload, + OSSA_OFFSET_OF(agsaSSPTgtIOStartCmd_t, DIF_seed), + ((pTRequest->dif.DIFPerLARegion0SecCount << SHIFT16) | + (pTRequest->dif.flags & DIF_FLAG_BITS_CRC_SEED ? pTRequest->dif.initialIOSeed : 0 ))); + } + else + { + /* Get IOS IOSeed enable bit */ + if (pTRequest->dif.flags & DIF_FLAG_BITS_CRC_SEED) + { + OSSA_WRITE_LE_32(agRoot, pPayload, + OSSA_OFFSET_OF(agsaSSPTgtIOStartCmd_t, DIF_seed), + pTRequest->dif.initialIOSeed ); + } + else + { + OSSA_WRITE_LE_32(agRoot, pPayload, + OSSA_OFFSET_OF(agsaSSPTgtIOStartCmd_t, DIF_seed), 0 ); + } + } + } + + /* Mask DIR and AutoGR bits for Read/Write command */ + if(pTRequest->sspOption & SSP_OPTION_AUTO_GOOD_RESPONSE) + { + DirDW5 |= AGSA_SSP_TGT_BITS_AGR; + } + + /* AN, RTE, RDF bits */ + DirDW5 |= (pTRequest->sspOption & SSP_OPTION_BITS) << 2; + + /* ODS */ + if(pTRequest->sspOption & SSP_OPTION_ODS) + { + DirDW5 |= AGSA_SSP_TGT_BITS_ODS; + } + + /* Setup SGL */ + if (pTRequest->dataLength) + { + pSgl = &(pTRequest->agSgl); + + SA_DBG5(("saSSPStart: agSgl %08x:%08x (%x/%x)\n", + pSgl->sgUpper, pSgl->sgLower, pSgl->len, pSgl->extReserved)); + + /* set up dir on the payload */ + /* Configure DWORD 5 */ + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPTgtIOStartCmd_t, INITagAgrDir), DirDW5); + + pPayload->AddrLow0 = pSgl->sgLower; + pPayload->AddrHi0 = pSgl->sgUpper; + pPayload->Len0 = pSgl->len; + pPayload->E0 = pSgl->extReserved; + } + else + { + /* no data transfer */ + /* Configure DWORD 5 */ + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPTgtIOStartCmd_t, INITagAgrDir), DirDW5); + pPayload->AddrLow0 = 0; + pPayload->AddrHi0 = 0; + pPayload->Len0 = 0; + } + /* Configure DWORD 6 */ + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPTgtIOStartCmd_t,reserved ), 0); + + /* Build TGT IO START command and send it to SPC */ + if (AGSA_RC_FAILURE == mpiMsgProduce(circularQ, (void *)pMessage, MPI_CATEGORY_SAS_SATA, OPC_INB_SSPTGTIOSTART, outq, (bit8)circularQ->priority)) + { + SA_DBG1(("saSSPStart, error when post TGT IOMB\n")); + ret = AGSA_RC_FAILURE; + } + + break; + } + case AGSA_SSP_TGT_CMD_OR_TASK_RSP: + { + agsaSSPTargetResponse_t *pTResponse = &(agRequestBody->sspTargetResponse); + agsaSSPTgtRspStartCmd_t *pPayload = (agsaSSPTgtRspStartCmd_t *)pMessage; + bit32 ip, an, ods; + + if (pTResponse->frameBuf && (pTResponse->respBufLength <= AGSA_MAX_SSPPAYLOAD_VIA_SFO)) + { + ip = 1; + si_memcpy(pPayload->reserved, pTResponse->frameBuf, pTResponse->respBufLength); + } + else + { + ip = 0; + /* NOTE: + * 1. reserved field must be ZEROED out. FW depends on it + * 2. trusted interface. indirect response buffer must be valid. + */ + si_memset(pPayload->reserved, 0, sizeof(pPayload->reserved)); + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPTgtRspStartCmd_t, AddrLow0), pTResponse->respBufLower); + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPTgtRspStartCmd_t, AddrHi0), pTResponse->respBufUpper); + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPTgtRspStartCmd_t, Len0), pTResponse->respBufLength); + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPTgtRspStartCmd_t, E0), 0); + } + + /* TLR setting */ + an = (pTResponse->respOption & RESP_OPTION_BITS); + /* ODS */ + ods = (pTResponse->respOption & RESP_OPTION_ODS); + + /* Prepare the SSP TGT RESPONSE Start payload */ + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPTgtRspStartCmd_t, tag), pRequest->HTag); + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPTgtRspStartCmd_t, deviceId), pDevice->DeviceMapIndex); + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPTgtRspStartCmd_t, RspLen), pTResponse->respBufLength); + OSSA_WRITE_LE_32(agRoot, pPayload, OSSA_OFFSET_OF(agsaSSPTgtRspStartCmd_t, INITag_IP_AN), + (pTResponse->agTag << SHIFT16) | ods | (ip << SHIFT10) | (an << SHIFT2)); + + /* Build TGT RESPONSE START command and send it to SPC */ + if (AGSA_RC_FAILURE == mpiMsgProduce(circularQ, (void *)pMessage, MPI_CATEGORY_SAS_SATA, OPC_INB_SSPTGTRSPSTART, outq, (bit8)circularQ->priority)) + { + SA_DBG1(("saSSPStart, error when post TGT RSP IOMB\n")); + ret = AGSA_RC_FAILURE; + } + + break; + } + default: + { + SA_DBG1(("saSSPStart, Unsupported Request IOMB\n")); + ret = AGSA_RC_FAILURE; + break; + } + } + + } /* LL IOrequest available */ + +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + +#ifdef SALL_API_TEST + if (ret == AGSA_RC_SUCCESS) + saRoot->LLCounters.IOCounter.numSSPStarted++; +#endif /*SALL_API_TEST */ + +#ifdef LOOPBACK_MPI + if (loopback) + saRoot->interruptVecIndexBitMap[0] |= (1 << outq); +#endif /* LOOPBACK_MPI */ + /* goto have leave and trace point info */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'f', "Sa"); +ext: + + OSSA_INP_LEAVE(agRoot); + return ret; +} + +/******************************************************************************/ +/*! \brief Abort SSP request + * + * Abort SSP request + * + * \param agRoot handles for this instance of SAS/SATA LLL + * \param queueNum + * \param agIORequest + * \param agIOToBeAborted + * + * \return If request is aborted successfully + * - \e AGSA_RC_SUCCESS request is aborted successfully + * - \e AGSA_RC_FAILURE request is not aborted successfully + */ +/*******************************************************************************/ +GLOBAL bit32 saSSPAbort( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 queueNum, + agsaDevHandle_t *agDevHandle, + bit32 flag, + void *abortParam, + ossaGenericAbortCB_t agCB + ) +{ + bit32 ret = AGSA_RC_SUCCESS, retVal; + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaIORequestDesc_t *pRequest; + agsaIORequestDesc_t *pRequestABT = NULL; + agsaDeviceDesc_t *pDevice = NULL; + agsaDeviceDesc_t *pDeviceABT = NULL; + agsaPort_t *pPort = NULL; + mpiICQueue_t *circularQ; + void *pMessage; + agsaSSPAbortCmd_t *payload; + agsaIORequest_t *agIOToBeAborted; + bit8 inq, outq; + bit32 using_reserved = agFALSE; + bit32 flag_copy = flag; + smTraceFuncEnter(hpDBG_VERY_LOUD,"Sb"); + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + SA_ASSERT((agNULL != agIORequest), ""); + + SA_DBG2(("saSSPAbort: agIORequest %p agDevHandle %p abortParam %p flag 0x%x\n", agIORequest,agDevHandle,abortParam,flag)); + + /* Assign inbound and outbound Buffer */ + inq = (bit8)(queueNum & MPI_IB_NUM_MASK); + outq = (bit8)((queueNum & MPI_OB_NUM_MASK) >> MPI_OB_SHIFT); + SA_ASSERT((AGSA_MAX_INBOUND_Q > inq), "The IBQ Number is out of range."); + +#ifdef SA_PRINTOUT_IN_WINDBG +#ifndef DBG + DbgPrint("saSSPAbort flag %d\n", flag ); +#endif /* DBG */ +#endif /* SA_PRINTOUT_IN_WINDBG */ + + if( ABORT_SINGLE == (flag & ABORT_MASK) ) + { + agIOToBeAborted = (agsaIORequest_t *)abortParam; + /* Get LL IORequest entry for saSSPAbort() */ + pRequest = (agsaIORequestDesc_t *) (agIOToBeAborted->sdkData); + if (agNULL == pRequest) + { + /* no pRequest found - can not Abort */ + SA_DBG1(("saSSPAbort: ABORT_ALL no pRequest\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Sb"); + return AGSA_RC_FAILURE; + } + /* Find the device the request sent to */ + pDevice = pRequest->pDevice; + /* Get LL IORequest entry for IOToBeAborted */ + pRequestABT = (agsaIORequestDesc_t *) (agIOToBeAborted->sdkData); + if (agNULL == pRequestABT) + { + /* The IO to Be Abort is no longer exist */ + SA_DBG1(("saSSPAbort: ABORT_ALL no pRequestABT\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "Sb"); + return AGSA_RC_FAILURE; + } + /* Find the device the request Abort to */ + pDeviceABT = pRequestABT->pDevice; + + if (agNULL == pDeviceABT) + { + /* no deviceID - can not build IOMB */ + SA_DBG1(("saSSPAbort: ABORT_ALL no pRequestABT->deviceID\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "Sb"); + return AGSA_RC_FAILURE; + } + + if (agNULL != pDevice) + { + /* Find the port the request was sent to */ + pPort = pDevice->pPort; + } + else + { + /* no deviceID - can not build IOMB */ + SA_DBG1(("saSSPAbort: ABORT_ALL no deviceID\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "Sb"); + return AGSA_RC_FAILURE; + } + + /* Get request from free IORequests */ + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); /**/ + } + else + { + if (ABORT_ALL == (flag & ABORT_MASK)) + { + /* abort All with Device or Port */ + /* Find the outgoing port for the device */ + if (agDevHandle == agNULL) + { + /* no deviceID - can not build IOMB */ + SA_DBG1(("saSSPAbort: agDevHandle == agNULL!!!\n")); + return AGSA_RC_FAILURE; + } + pDevice = (agsaDeviceDesc_t *) (agDevHandle->sdkData); + if (agNULL == pDevice) + { + /* no deviceID - can not build IOMB */ + SA_DBG1(("saSSPAbort: ABORT_ALL agNULL == pDevice\n")); + return AGSA_RC_FAILURE; + } + pPort = pDevice->pPort; + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); /**/ + } + else + { + /* only support 00, 01 and 02 for flag */ + SA_DBG1(("saSSPAbort: ABORT_ALL type not supported 0x%X\n",flag)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "Sb"); + return AGSA_RC_FAILURE; + } + } + + if ( agNULL == pRequest ) + { + pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeReservedRequests)); + if(agNULL != pRequest) + { + using_reserved = agTRUE; + SA_DBG2(("saSSPAbort: using saRoot->freeReservedRequests\n")); + } + else + { + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + /* If no LL IO request entry available */ + SA_DBG1(("saSSPAbort: No request from free list Not using saRoot->freeReservedRequests\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'f', "Sb"); + return AGSA_RC_BUSY; + } + } + + /* If free IOMB avaliable */ + /* Remove the request from free list */ + if( using_reserved ) + { + saLlistIORemove(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + + /* Add the request to the pendingIORequests list of the device */ + pRequest->valid = agTRUE; + saLlistIOAdd(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + /* set up pRequest */ + pRequest->pIORequestContext = agIORequest; + pRequest->requestType = AGSA_SSP_REQTYPE; + pRequest->pDevice = pDevice; + pRequest->pPort = pPort; + pRequest->completionCB = (void*)agCB; +/* pRequest->abortCompletionCB = agCB;*/ + pRequest->startTick = saRoot->timeTick; + + /* Set request to the sdkData of agIORequest */ + agIORequest->sdkData = pRequest; + + /* save tag and IOrequest pointer to IOMap */ + saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag; + saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest; + + +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedEnter(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + + /* If LL IO request entry avaliable */ + /* Get a free inbound queue entry */ + circularQ = &saRoot->inboundQueue[inq]; + retVal = mpiMsgFreeGet(circularQ, IOMB_SIZE64, &pMessage); + + /* if message size is too large return failure */ + if (AGSA_RC_FAILURE == retVal) + { +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + pRequest->valid = agFALSE; + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("saSSPAbort: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("saSSPAbort: error when get free IOMB\n")); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'g', "Sb"); + return AGSA_RC_FAILURE; + } + + /* return busy if inbound queue is full */ + if (AGSA_RC_BUSY == retVal) + { +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + + ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); + saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); + pRequest->valid = agFALSE; + if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) + { + SA_DBG1(("saSSPAbort: saving pRequest (%p) for later use\n", pRequest)); + saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); + } + else + { + /* return the request to free pool */ + saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); + } + ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); + + SA_DBG1(("saSSPAbort: no more IOMB\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'h', "Sb"); + return AGSA_RC_BUSY; + } + + /* setup payload */ + payload = (agsaSSPAbortCmd_t*)pMessage; + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSSPAbortCmd_t, tag), pRequest->HTag); + + if( ABORT_SINGLE == (flag & ABORT_MASK) ) + { + if ( agNULL == pDeviceABT ) + { + SA_DBG1(("saSSPSAbort: no device\n" )); + smTraceFuncExit(hpDBG_VERY_LOUD, 'i', "Sb"); + return AGSA_RC_FAILURE; + } + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSSPAbortCmd_t, deviceId), pDeviceABT->DeviceMapIndex); + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSSPAbortCmd_t, HTagAbort), pRequestABT->HTag); + } + else + { + /* abort all */ + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSSPAbortCmd_t, deviceId), pDevice->DeviceMapIndex); + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSSPAbortCmd_t, HTagAbort), 0); + } + + if(flag & ABORT_TSDK_QUARANTINE) + { + if(smIS_SPCV(agRoot)) + { + flag_copy &= ABORT_SCOPE; + flag_copy |= ABORT_QUARANTINE_SPCV; + } + } + OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSSPAbortCmd_t, abortAll), flag_copy); + + SA_DBG1(("saSSPAbort: HTag 0x%x HTagABT 0x%x deviceId 0x%x flag 0x%x\n", payload->tag, payload->HTagAbort, payload->deviceId,flag)); + + siCountActiveIORequestsOnDevice( agRoot, payload->deviceId ); + + /* post the IOMB to SPC */ + ret = mpiMsgProduce(circularQ, (void *)pMessage, MPI_CATEGORY_SAS_SATA, OPC_INB_SSP_ABORT, outq, (bit8)circularQ->priority); + +#ifdef SA_LL_IBQ_PROTECT + ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq); +#endif /* SA_LL_IBQ_PROTECT */ + +#ifdef SALL_API_TEST + if (AGSA_RC_SUCCESS == ret) + { + saRoot->LLCounters.IOCounter.numSSPAborted++; + } +#endif + + smTraceFuncExit(hpDBG_VERY_LOUD, 'j', "Sb"); + + return ret; +} + + +#if defined(SALLSDK_DEBUG) +/******************************************************************************/ +/*! \brief + * + * Dump StartSSP information + * + * Debug helper routine + * + * \return -none - + */ +/*******************************************************************************/ +LOCAL void siDumpSSPStartIu( + agsaDevHandle_t *agDevHandle, + bit32 agRequestType, + agsaSASRequestBody_t *agRequestBody + ) + { + switch ( agRequestType ) + { + case AGSA_SSP_INIT_READ: + case AGSA_SSP_INIT_WRITE: + { + agsaSSPInitiatorRequest_t *pIRequest = &(agRequestBody->sspInitiatorReq); + + SA_DBG5(("siDumpSSPStartIu: dev=%p - %s - len=%x - attr=%x - CDB:%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", + agDevHandle, + (agRequestType==AGSA_SSP_INIT_READ)? "AGSA_SSP_INIT_READ" : "AGSA_SSP_INIT_WRITE", + pIRequest->dataLength, + pIRequest->sspCmdIU.efb_tp_taskAttribute, + pIRequest->sspCmdIU.cdb[0], + pIRequest->sspCmdIU.cdb[1], + pIRequest->sspCmdIU.cdb[2], + pIRequest->sspCmdIU.cdb[3], + pIRequest->sspCmdIU.cdb[4], + pIRequest->sspCmdIU.cdb[5], + pIRequest->sspCmdIU.cdb[6], + pIRequest->sspCmdIU.cdb[7], + pIRequest->sspCmdIU.cdb[8], + pIRequest->sspCmdIU.cdb[9] + )); + break; + } + + case AGSA_SSP_INIT_READ_EXT: + case AGSA_SSP_INIT_WRITE_EXT: + { + agsaSSPInitiatorRequestExt_t *pIRequest = &(agRequestBody->sspInitiatorReqExt); + + SA_DBG3(("siDumpSSPStartIu: dev=%p - %s - len=%x - attr=%x - CDB:%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", + agDevHandle, + (agRequestType==AGSA_SSP_INIT_READ_EXT)? "AGSA_SSP_INIT_READ_EXT" : "AGSA_SSP_INIT_WRITE_EXT", + pIRequest->dataLength, + pIRequest->sspCmdIUExt.efb_tp_taskAttribute, + pIRequest->sspCmdIUExt.cdb[0], + pIRequest->sspCmdIUExt.cdb[1], + pIRequest->sspCmdIUExt.cdb[2], + pIRequest->sspCmdIUExt.cdb[3], + pIRequest->sspCmdIUExt.cdb[4], + pIRequest->sspCmdIUExt.cdb[5], + pIRequest->sspCmdIUExt.cdb[6], + pIRequest->sspCmdIUExt.cdb[7], + pIRequest->sspCmdIUExt.cdb[8], + pIRequest->sspCmdIUExt.cdb[9] + )); + break; + } + + case AGSA_SSP_INIT_READ_EXT_M: + case AGSA_SSP_INIT_WRITE_EXT_M: + { + agsaSSPInitiatorRequestExt_t *pIRequest = &(agRequestBody->sspInitiatorReqExt); + + SA_DBG3(("siDumpSSPStartIu: dev=%p - %s - len=%x - attr=%x - CDB:%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", + agDevHandle, + (agRequestType==AGSA_SSP_INIT_READ_EXT_M)? "AGSA_SSP_INIT_READ_EXT_M" : "AGSA_SSP_INIT_WRITE_EXT_M", + pIRequest->dataLength, + pIRequest->sspCmdIUExt.efb_tp_taskAttribute, + pIRequest->sspCmdIUExt.cdb[0], + pIRequest->sspCmdIUExt.cdb[1], + pIRequest->sspCmdIUExt.cdb[2], + pIRequest->sspCmdIUExt.cdb[3], + pIRequest->sspCmdIUExt.cdb[4], + pIRequest->sspCmdIUExt.cdb[5], + pIRequest->sspCmdIUExt.cdb[6], + pIRequest->sspCmdIUExt.cdb[7], + pIRequest->sspCmdIUExt.cdb[8], + pIRequest->sspCmdIUExt.cdb[9] + )); + break; + } + + case AGSA_SSP_INIT_READ_INDIRECT: + case AGSA_SSP_INIT_WRITE_INDIRECT: + case AGSA_SSP_INIT_READ_INDIRECT_M: + case AGSA_SSP_INIT_WRITE_INDIRECT_M: + { + agsaSSPInitiatorRequestIndirect_t *pIRequest = &(agRequestBody->sspInitiatorReqIndirect); + + SA_DBG3(("siDumpSSPStartIu: dev=%p - %s - len=%x - cdblen=%d CDB:U %08x L %08x\n", + agDevHandle, + (agRequestType==AGSA_SSP_INIT_READ_INDIRECT || + agRequestType==AGSA_SSP_INIT_READ_INDIRECT_M) ? "AGSA_SSP_INIT_READ_INDIRECT" : "AGSA_SSP_INIT_WRITE_INDIRECT", + pIRequest->dataLength, + pIRequest->sspInitiatorReqLen, + pIRequest->sspInitiatorReqAddrUpper32, + pIRequest->sspInitiatorReqAddrLower32 )); + break; + } + + + case AGSA_SSP_TASK_MGNT_REQ: + { + agsaSSPScsiTaskMgntReq_t *pTaskCmd =&agRequestBody->sspTaskMgntReq; + /* copy payload */ + + SA_DBG5(("siDumpSSPStartIu: dev=%p - %s - Task Function=%x - Tag to managed=%x", + agDevHandle, + "AGSA_SSP_TASK_MGNT_REQ", + pTaskCmd->taskMgntFunction, + pTaskCmd->tagOfTaskToBeManaged + )); + break; + } + case AGSA_SSP_TGT_READ_DATA: + { + agsaSSPTargetRequest_t *pTRequest = &(agRequestBody->sspTargetReq); + + SA_DBG5(("siDumpSSPStartIu: dev=%p - %s - dmaSize=%x dmaOffset=%x\n", + agDevHandle, + "AGSA_SSP_TGT_READ_DATA", + pTRequest->dataLength, + pTRequest->offset )); + break; + } + case AGSA_SSP_TGT_READ_GOOD_RESP: + { + agsaSSPTargetRequest_t *pTRequest = &(agRequestBody->sspTargetReq); + + SA_DBG5(("siDumpSSPStartIu: dev=%p - %s - dmaSize=%x dmaOffset=%x\n", + agDevHandle, + "AGSA_SSP_TGT_READ_GOOD_RESP", + pTRequest->dataLength, + pTRequest->offset)); + break; + } + case AGSA_SSP_TGT_WRITE_GOOD_RESP: + { + agsaSSPTargetRequest_t *pTRequest = &(agRequestBody->sspTargetReq); + SA_DBG5(("siDumpSSPStartIu: dev=%p - %s - dmaSize=%x dmaOffset=%x\n", + agDevHandle, + "AGSA_SSP_TGT_WRITE_GOOD_RESP", + pTRequest->dataLength, + pTRequest->offset )); + + break; + } + case AGSA_SSP_TGT_WRITE_DATA: + { + agsaSSPTargetRequest_t *pTRequest = &(agRequestBody->sspTargetReq); + + SA_DBG5(("siDumpSSPStartIu: dev=%p - %s - dmaSize=%x dmaOffset=%x\n", + agDevHandle, + "AGSA_SSP_TGT_WRITE_DATA", + pTRequest->dataLength, + pTRequest->offset )); + break; + } + case AGSA_SSP_TGT_CMD_OR_TASK_RSP: + { + agsaSSPTargetResponse_t *pTResponse = &(agRequestBody->sspTargetResponse); + + SA_DBG5(("siDumpSSPStartIu: dev=%p - %s - len=%x PAddr=%08x:%08x Tag=%x\n", + agDevHandle, + "AGSA_SSP_TGT_CMD_OR_TASK_RSP", + pTResponse->respBufLength, + pTResponse->respBufUpper, + pTResponse->respBufLower, + pTResponse->agTag )); + break; + } + + default: + { + SA_DBG1(("siDumpSSPStartIu: dev=%p - %s %X\n", + agDevHandle, + "Unknown SSP cmd type", + agRequestType + )); + break; + } + } + return; +} +#endif /* SALLSDK_DEBUG */ diff --git a/sys/dev/pms/RefTisa/sallsdk/spc/satimer.c b/sys/dev/pms/RefTisa/sallsdk/spc/satimer.c new file mode 100644 index 000000000000..869e81ed2587 --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/spc/satimer.c @@ -0,0 +1,410 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +/*******************************************************************************/ +/*! \file satimer.c + * \brief The file implements the timerTick function + * + */ +/******************************************************************************/ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#ifdef SA_FW_TEST_BUNCH_STARTS +void mpiMsgProduceBunch( agsaLLRoot_t *saRoot); +#endif /* SA_FW_TEST_BUNCH_STARTS */ + +#ifdef SA_ENABLE_TRACE_FUNCTIONS +#ifdef siTraceFileID +#undef siTraceFileID +#endif +#define siTraceFileID 'P' +#endif + +/******************************************************************************/ +/*! \brief TimerTick + * + * TimerTick + * + * \param agRoot handles for this instance of SAS/SATA hardware + * + * \return -void- + */ +/*******************************************************************************/ +GLOBAL void saTimerTick( + agsaRoot_t *agRoot + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaTimerDesc_t *pTimer; + bit32 Event; + void * pParm; + + if(agNULL == saRoot) + { + SA_DBG1(("saTimerTick:agNULL == saRoot \n")); + return; + } + + /* (1) Acquire timer list lock */ + ossaSingleThreadedEnter(agRoot, LL_TIMER_LOCK); + + /* (2) Find the timers are timeout */ + pTimer = (agsaTimerDesc_t *) saLlistGetHead(&(saRoot->validTimers)); + while ( agNULL != pTimer ) + { + /* (2.1) Find the first timer is timeout */ + if ( pTimer->timeoutTick == saRoot->timeTick ) + { + /* (2.1.1) remove the timer from valid timer list */ + saLlistRemove(&(saRoot->validTimers), &(pTimer->linkNode)); + /* (2.1.2) Invalid timer */ + pTimer->valid = agFALSE; + /* (2.1.3) Get timer event and param */ + Event = pTimer->Event; + pParm = pTimer->pParm; + /* (2.1.4) Release timer list lock */ + ossaSingleThreadedLeave(agRoot, LL_TIMER_LOCK); + + /* (2.1.5) Timer Callback */ + pTimer->pfnTimeout(agRoot, Event, pParm); + + /* (2.1.6) Acquire timer list lock again */ + ossaSingleThreadedEnter(agRoot, LL_TIMER_LOCK); + /* (2.1.7) return the timer to free timer list */ + saLlistAdd(&(saRoot->freeTimers), &(pTimer->linkNode)); + } + /* (2.2) the first timer is not timeout */ + else + { + break; + } + pTimer = (agsaTimerDesc_t *) saLlistGetHead(&(saRoot->validTimers)); + } + + /* (3) increment timeTick */ + saRoot->timeTick ++; + + if( saRoot->ResetFailed ) + { + SA_DBG1(("saTimerTick: siChipResetV saRoot->ResetFailed\n")); + } + +#ifdef SA_FW_TEST_BUNCH_STARTS + if (saRoot->BunchStarts_Enable && + saRoot->BunchStarts_Pending) + { + SA_DBG3(("saTimerTick: mpiMsgProduceBunch\n")); + mpiMsgProduceBunch( saRoot); + } +#endif /* SA_FW_TEST_BUNCH_STARTS */ + + +#ifdef SA_FW_TEST_INTERRUPT_REASSERT + + if(1) + { + mpiOCQueue_t *circularQ; + int i; + SA_DBG4(("saTimerTick:SA_FW_TEST_INTERRUPT_REASSERT\n")); + for ( i = 0; i < saRoot->QueueConfig.numOutboundQueues; i++ ) + { + circularQ = &saRoot->outboundQueue[i]; + OSSA_READ_LE_32(circularQ->agRoot, &circularQ->producerIdx, circularQ->piPointer, 0); + if(circularQ->producerIdx != circularQ->consumerIdx) + { + if( saRoot->OldCi[i] == circularQ->consumerIdx && saRoot->OldPi[i] >= circularQ->producerIdx) + { + agsaEchoCmd_t payload; + payload.tag = 0xF0; + payload.payload[0]= 0x0; + if( ++saRoot->OldFlag[i] > 1 ) + { + saRoot->CheckAll++; + } + SA_DBG1(("saTimerTick:Q %d (%d) PI 0x%03x CI 0x%03x (%d) CheckAll %d %d\n",i, + saRoot->OldFlag[i], + circularQ->producerIdx, + circularQ->consumerIdx, + (circularQ->producerIdx > circularQ->consumerIdx ? (circularQ->producerIdx - circularQ->consumerIdx) : (circularQ->numElements - circularQ->consumerIdx ) + circularQ->producerIdx), + saRoot->CheckAll, + saRoot->sysIntsActive )); + + if(smIS64bInt(agRoot)) + { + SA_DBG1(("saTimerTick:CheckAll %d ODR 0x%08X%08X ODMR 0x%08X%08X our Int %x\n", + saRoot->CheckAll, + ossaHwRegReadExt(agRoot, 0, V_Outbound_Doorbell_Set_RegisterU), + ossaHwRegReadExt(agRoot, 0, V_Outbound_Doorbell_Set_Register), + ossaHwRegReadExt(agRoot, 0, V_Outbound_Doorbell_Mask_Set_RegisterU), + ossaHwRegReadExt(agRoot, 0, V_Outbound_Doorbell_Mask_Set_Register), + saRoot->OurInterrupt(agRoot,i) + )); + } + else + { + SA_DBG1(("saTimerTick:CheckAll %d ODR 0x%08X ODMR 0x%08X our Int %x\n", + saRoot->CheckAll, + siHalRegReadExt(agRoot, GEN_MSGU_ODR, V_Outbound_Doorbell_Set_Register), + siHalRegReadExt(agRoot, GEN_MSGU_ODMR, V_Outbound_Doorbell_Mask_Set_Register), + saRoot->OurInterrupt(agRoot,i) + )); + } + + + if( saRoot->CheckAll > 1) + { + saEchoCommand(agRoot,agNULL, ((i << 16) & 0xFFFF0000 ), (void *)&payload); + } + + } + else + { + saRoot->OldFlag[i] = 0; + } + + saRoot->OldPi[i] = circularQ->producerIdx; + saRoot->OldCi[i] = circularQ->consumerIdx; + + } + } + } +#endif /* SA_FW_TEST_INTERRUPT_REASSERT */ + + /* (4) Release timer list lock */ + ossaSingleThreadedLeave(agRoot, LL_TIMER_LOCK); +#ifdef SA_FW_TEST_INTERRUPT_REASSERT + if(saRoot->CheckAll ) + { + int a; + for(a=0; a < 32; a++ ) + { + if (saRoot->interruptVecIndexBitMap[a] & (1 << a)) + { + SA_DBG1(("saTimerTick DI %d\n",a)); + saSystemInterruptsEnable ( agRoot, a ); + + } + } + } +#endif /* SA_FW_TEST_INTERRUPT_REASSERT */ +} + +/******************************************************************************/ +/*! \brief add a timer + * + * add a timer + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param pTimer the pointer to the timer being added + * \param timeout the timeout ticks from now + * \param pfnTimeout callback function when time is out + * \param Event the Event code passed to callback function + * \param pParm the pointer to parameter passed to callback function + * + * \return If the timer is added successfully + * - \e AGSA_RC_SUCCESS timer is added successfully + * - \e AGSA_RC_FAILURE cannot add new timer, run out of resource + */ +/*******************************************************************************/ +GLOBAL agsaTimerDesc_t *siTimerAdd( + agsaRoot_t *agRoot, + bit32 timeout, + agsaCallback_t pfnTimeout, + bit32 Event, + void * pParm + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaTimerDesc_t *pTimer; + agsaTimerDesc_t *pValidTimer; + + smTraceFuncEnter(hpDBG_VERY_LOUD, "Ta"); + /* (1) Acquire timer list lock */ + ossaSingleThreadedEnter(agRoot, LL_TIMER_LOCK); + + /* (2) Get a free timer */ + pTimer = (agsaTimerDesc_t *) saLlistGetHead(&(saRoot->freeTimers)); + + /* (3) If the timer is availble */ + if ( agNULL != pTimer ) + { + saLlistRemove(&(saRoot->freeTimers), &(pTimer->linkNode)); + + /* (3.1) Setup timer */ + saLlinkInitialize(&(pTimer->linkNode)); + /*--------------------------------------** + ** the timeout shall greater than 0 ** + **--------------------------------------*/ + if ( 0 == timeout ) + { + timeout = timeout + 1; + } + pTimer->valid = agTRUE; + pTimer->timeoutTick = saRoot->timeTick + timeout; + pTimer->pfnTimeout = pfnTimeout; + pTimer->Event = Event; + pTimer->pParm = pParm; + + /* (3.2) Add timer the timer to valid timer list */ + pValidTimer = (agsaTimerDesc_t *) saLlistGetHead(&(saRoot->validTimers)); + /* (3.3) for each timer in the valid timer list */ + while ( agNULL != pValidTimer ) + { + /* (3.3.1) If the timeoutTick is not wrapped around */ + if ( pTimer->timeoutTick > saRoot->timeTick ) + { + /* (3.3.1.1) If validTimer wrapped around */ + if ( pValidTimer->timeoutTick < saRoot->timeTick ) + { + saLlistInsert(&(saRoot->validTimers), &(pValidTimer->linkNode), &(pTimer->linkNode)); + break; + } + /* (3.3.1.2) If validTimer is not wrapped around */ + else + { + if ( pValidTimer->timeoutTick > pTimer->timeoutTick ) + { + saLlistInsert(&(saRoot->validTimers), &(pValidTimer->linkNode), &(pTimer->linkNode)); + break; + } + } + } + /* (3.3.2) If the timeoutTick is wrapped around */ + else + { + /* (3.3.2.1) If validTimer is wrapped around */ + if ( pValidTimer->timeoutTick < saRoot->timeTick ) + { + if ( pValidTimer->timeoutTick > pTimer->timeoutTick ) + { + saLlistInsert(&(saRoot->validTimers), &(pValidTimer->linkNode), &(pTimer->linkNode)); + break; + } + } + } + /* (3.3.3) Continue to the next valid timer */ + pValidTimer = (agsaTimerDesc_t *) saLlistGetNext(&(saRoot->validTimers), &(pValidTimer->linkNode)); + } + + /* (3.4) No timers in the validtimer list is greater than this timer */ + if ( agNULL == pValidTimer ) + { + saLlistAdd(&(saRoot->validTimers), &(pTimer->linkNode)); + } + } + + /* (4) Release timer list lock */ + ossaSingleThreadedLeave(agRoot, LL_TIMER_LOCK); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Ta"); + + return pTimer; +} + +/******************************************************************************/ +/*! \brief remove a valid timer + * + * remove a timer + * + * \param agRoot handles for this instance of SAS/SATA hardware + * \param pTimer the timer to be removed + * + * \return -void- + */ +/*******************************************************************************/ +GLOBAL void siTimerRemove( + agsaRoot_t *agRoot, + agsaTimerDesc_t *pTimer + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + + /* (1) Acquire timer list lock */ + smTraceFuncEnter(hpDBG_VERY_LOUD,"Tb"); + ossaSingleThreadedEnter(agRoot, LL_TIMER_LOCK); + + /* (2) If the timer is still valid */ + if ( agTRUE == pTimer->valid ) + { + /* (2.1) remove from the valid timer list */ + saLlistRemove(&(saRoot->validTimers), &(pTimer->linkNode)); + /* (2.2) Invalid the timer */ + pTimer->valid = agFALSE; + /* (2.3) return the timer to the free timer list */ + saLlistAdd(&(saRoot->freeTimers), &(pTimer->linkNode)); + } + /* (3) Release timer list lock */ + ossaSingleThreadedLeave(agRoot, LL_TIMER_LOCK); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Tb"); + + return; +} + +/******************************************************************************/ +/*! \brief remove all valid timer + * + * remove all timer + * + * \param agRoot handles for this instance of SAS/SATA hardware + * + * \return -void- + */ +/*******************************************************************************/ +GLOBAL void siTimerRemoveAll( + agsaRoot_t *agRoot + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + agsaTimerDesc_t *pTimer; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"Tc"); + + /* (1) Acquire timer list lock */ + ossaSingleThreadedEnter(agRoot, LL_TIMER_LOCK); + + /* (2) Get a valid timer */ + pTimer = (agsaTimerDesc_t *) saLlistGetHead(&(saRoot->validTimers)); + + /* (3) If the timer is valid */ + while ( agNULL != pTimer ) + { + /* (3.1) remove from the valid timer list */ + saLlistRemove(&(saRoot->validTimers), &(pTimer->linkNode)); + + /* (3.2) Invalid timer */ + pTimer->valid = agFALSE; + + /* (3.3) return the timer to the free timer list */ + saLlistAdd(&(saRoot->freeTimers), &(pTimer->linkNode)); + + /* (3.4) get next valid timer */ + pTimer = (agsaTimerDesc_t *) saLlistGetHead(&(saRoot->validTimers)); + } + + /* (4) Release timer list lock */ + ossaSingleThreadedLeave(agRoot, LL_TIMER_LOCK); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Tc"); + + return; +} diff --git a/sys/dev/pms/RefTisa/sallsdk/spc/satypes.h b/sys/dev/pms/RefTisa/sallsdk/spc/satypes.h new file mode 100644 index 000000000000..a99571fde99b --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/spc/satypes.h @@ -0,0 +1,369 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/*******************************************************************************/ +/*! \file satypes.h + * \brief The file defines the internal data structure types used by LL layer + * + */ +/*******************************************************************************/ + +#ifndef __SATYPES_H__ + +#define __SATYPES_H__ + +/** \brief the callback function of an timer + * + * the definition of the timer callback function + */ +typedef bit32 (* agsaCallback_t) (agsaRoot_t *agRoot, + bit32 Event, + void *Parm); + +/** \brief the data structure of a timer + * + * use to describe timer + * + */ +typedef struct agsaTimerDesc_s +{ + SALINK linkNode; /**< the link node data structure of the timer */ + bit32 valid; /**< the valid bit of the timer descriptor */ + bit32 timeoutTick; /**< the timeout tick of the timer */ + agsaCallback_t pfnTimeout; /**< the callback function fo the timer */ + bit32 Event; /**< the event paramter of the timer callback function */ + void * pParm; /**< the point to the paramter passed to callback function */ +} agsaTimerDesc_t; + +/** \brief the port + * + * describe port data structure + * + */ +typedef struct agsaPort_s +{ + SALINK linkNode; /**< the link node data structure of the port */ + agsaPortContext_t portContext; /**< the port context of the port */ + SALINK_LIST listSASATADevices; /**< SAS/SATA devices list of the port */ + bit32 phyMap[AGSA_MAX_VALID_PHYS]; /**< Boolean arrar: the Phys included in the port. */ + bit32 status; /**< port state */ + bit32 tobedeleted; /**< mark for deletetion after callback */ + bit32 portId; /** Port Id from SPC */ + bit8 portIdx; /**< the Index of the port */ + bit8 reserved[3]; +} agsaPort_t; + +/** \brief the phy + * + * phy data structure + * + */ +typedef struct agsaPhy_s +{ + agsaPort_t *pPort; /**< pointer to the port includes the phy */ + agsaSASIdentify_t sasIdentify; /**< the SAS identify of the phy */ + agsaContext_t *agContext; /**< agContext for the Phy */ + bit32 status; /**< the status of the phy */ + bit8 phyId; /**< the Id of the phy */ + bit8 linkstatus; /**< the link status of the phy */ + bit8 reserved[2]; +#if defined(SALLSDK_DEBUG) + bit8 remoteSignature[8]; /* the remote signature of the phy is the phy is in native SATA mode */ +#endif +} agsaPhy_t; + +/** \brief the LL defined SAS/SATA device information + * + * LL defined SAS/SATA device information + * + */ +typedef union agsaSASSATADevInfo_s +{ + agsaSASDeviceInfo_t sasDeviceInfo; /**< SAS device information of the device */ + agsaSATADeviceInfo_t sataDeviceInfo; /**< SATA device information of the device */ +} agsaSASSATADevInfo_t; + +/** \brief the LL defined device descriptor + * + * LL defined device descriptor + * + */ +typedef struct agsaDeviceDesc_s +{ + SALINK linkNode; /**< the link node data structure of the device */ + agsaDevHandle_t initiatorDevHandle; /**< the device handle of an initiator device */ + agsaDevHandle_t targetDevHandle; /**< the device handle of a target device */ + SALINK_LIST pendingIORequests; /**< the pending IO requests, for SSP or SATA */ + agsaPort_t *pPort; /**< the port discovered the device */ + bit8 deviceType; /**< the device type */ + bit8 reserved[3]; + bit32 option; + bit32 param; + agsaSASSATADevInfo_t devInfo; /**< SAS/SATA device information */ + bit32 DeviceMapIndex; /**< device index for device handle */ +} agsaDeviceDesc_t; + +/** \brief the LL defined IO request descriptor + * + * LL defined IO Request descriptor + * + */ +typedef struct agsaIORequestDesc_s +{ + SALINK linkNode; /**< the link node data structure of the IO request */ + agsaIORequest_t *pIORequestContext;/**< the IO request context */ + agsaDeviceDesc_t *pDevice; /**< the pointer to the device, to which the request is sent */ + agsaPort_t *pPort; /**< the pointer to the port - using by HW_EVENT_ACK with PHY_DOWN event */ + ossaSSPCompletedCB_t completionCB; /**< completion callback to be called */ + bit32 requestType; /**< the request type */ + bit16 HwAckType; /**< Track HW_acks */ + bit16 SOP; /**< SetPhyProfile page not returned in reply */ + bit32 startTick; /**< start time for this IO */ + bit32 HTag; /**< the host tag to index into the IORequest array */ + bit8 valid; /**< boolean flag: the request is valid */ + bit8 IRmode; /**< indirect smp response mode */ + bit8 modePageContext; /**< request is for security mode change */ + bit8 DeviceInfoCmdOption;/**< */ +#ifdef FAST_IO_TEST + SALINK fastLink; /* Fast I/O's chain */ +#endif +} agsaIORequestDesc_t; + +/** \brief the LL defined SMP Response Frame header and payload + * + * LL defined SMP Response Frame header and payload + * + */ +typedef struct agsaSMPRspFrame_s +{ + agsaSMPFrameHeader_t smpHeader; + bit8 smpPayload[1020]; +} agsaSMPRspFrame_t; + +/** \brief the agsaIOMap_t + * + * data storage for IO Request Mapping + * + */ +typedef struct agsaIOMap_s +{ + bit32 Tag; + agsaIORequestDesc_t *IORequest; + agsaContext_t *agContext; +} agsaIOMap_t; + +/** \brief the agsaPortMap_t + * + * data storage for Port Context Mapping + * + */ +typedef struct agsaPortMap_s +{ + bit32 PortID; + bit32 PortStatus; + void *PortContext; +} agsaPortMap_t; + +/** \brief the agsaDeviceMap_t + * + * data storage for Device Handle Mapping + * + */ +typedef struct agsaDeviceMap_s +{ + bit32 DeviceIdFromFW; + void *DeviceHandle; +} agsaDeviceMap_t; + +#ifdef FAST_IO_TEST +/* interleaved Fast IO's are not allowed */ +#define LL_FAST_IO_SIZE 1 +#endif + +/** \brief the LLRoot + * + * root data structure + * + */ +typedef struct agsaLLRoot_s +{ + agsaMem_t deviceLinkMem; /**< Device Link System Memory */ + SALINK_LIST freeDevicesList; /**< List of free IO device handles */ + + agsaMem_t IORequestMem; /**< IO Request Link System Memory */ + SALINK_LIST freeIORequests; /**< List of free IORequests */ + SALINK_LIST freeReservedRequests; /**< List of reserved IORequests not for normal IO! */ + + agsaMem_t timerLinkMem; /**< Timer Link System Memory */ + SALINK_LIST freeTimers; /**< List of free timers */ + SALINK_LIST validTimers; /**< List of valid timers */ + + agsaPhy_t phys[AGSA_MAX_VALID_PHYS]; /**< Phys */ + + agsaPort_t ports[AGSA_MAX_VALID_PORTS]; /**< Ports */ + SALINK_LIST freePorts; /**< List of free ports */ + SALINK_LIST validPorts; /**< List of valid ports */ + + bit8 phyCount; /**< number of phys */ + bit8 portCount; /**< number of ports */ + bit8 sysIntsActive; /**< whether interrupt is enabled */ + bit8 reserved; /**< reserved */ + + bit32 usecsPerTick; /**< timer tick unit */ + bit32 minStallusecs; /**< shorest available stall */ + bit32 timeTick; /**< the current timer tick */ + bit32 ResetStartTick; /* Reset StartTick */ + bit32 chipStatus; /**< chip status */ + + bit32 interruptVecIndexBitMap[MAX_NUM_VECTOR]; /**< Interrupt Vector Index BitMap */ + bit32 interruptVecIndexBitMap1[MAX_NUM_VECTOR]; /**< Interrupt Vector Index BitMap1 */ + + agsaBarOffset_t SpcBarOffset[60]; + bit32 ChipId; /* Subversion PCI ID */ + + agsaPortMap_t PortMap[AGSA_MAX_VALID_PORTS]; /**< Port Mapping for PortContext */ + agsaDeviceMap_t DeviceMap[MAX_IO_DEVICE_ENTRIES]; /**< Device Map for Device Handle */ + agsaIOMap_t IOMap[MAX_ACTIVE_IO_REQUESTS]; /**< IO MAP for IO Request */ + agsaDevHandle_t *DeviceHandle[MAX_IO_DEVICE_ENTRIES]; /**< used for get device handles */ + agsaDevHandle_t *pDeviceHandle; /**< used for get device handles */ + + agsaMemoryRequirement_t memoryAllocated; /**< SAS LL memory Allocation */ + agsaHwConfig_t hwConfig; /**< copy of hwConfig */ + agsaSwConfig_t swConfig; /**< copy of swConfig */ + agsaQueueConfig_t QueueConfig; /* copy of MPI IBQ/OBQ configuration */ + + mpiConfig_t mpiConfig; /**< MPI Configuration */ + mpiMemReq_t mpiMemoryAllocated; /**< MPI memory */ + mpiICQueue_t inboundQueue[AGSA_MAX_INBOUND_Q]; /**< Outbound queue descriptor array */ + mpiOCQueue_t outboundQueue[AGSA_MAX_OUTBOUND_Q]; /**< Outbound queue descriptor array */ + mpiHostLLConfigDescriptor_t mainConfigTable; /**< LL main Configuration Table */ + + ossaDeviceRegistrationCB_t DeviceRegistrationCB; /**< Device Registration CB */ + ossaDeregisterDeviceHandleCB_t DeviceDeregistrationCB;/**< Device DeRegistration CB */ + + bit32 numInterruptVectors; /**< Number of Interrupt Vectors configured from OS */ + bit32 Use64bit; /**< Only write upper bits if needed */ + + EnadDisabHandler_t DisableInterrupts; /*Interrupt type dependant function pointer to disable interrupts */ + EnadDisabHandler_t ReEnableInterrupts; /*Interrupt type dependant reenable */ + InterruptOurs_t OurInterrupt; /*Interrupt type dependant check for our interrupt */ + +#ifdef SA_FW_TEST_BUNCH_STARTS + /** + * Following variables are needed to handle Bunch Starts (bulk update of PI) + * - saRoot (agsaLLRoot_t): Global Flags, apply to all queues + * 1. BunchStarts_Enable + * 2. BunchStarts_Threshold + * 3. BunchStarts_Pending + * 4. BunchStarts_TimeoutTicks + * + * - Circular Q (mpiICQueue_s): Queue specific flags + * 1. BunchStarts_QPending + * 2. BunchStarts_QPendingTick + */ + bit32 BunchStarts_Enable; // enables/disables whole feature + bit32 BunchStarts_Threshold; // global min number of IOs to bunch per queue. + bit32 BunchStarts_Pending; // global counter collects all Q->BunchStarts_QPending + bit32 BunchStarts_TimeoutTicks; // global time out value beyond which bunched IOs will be started even below BunchStarts_Threshold. +#endif /* SA_FW_TEST_BUNCH_STARTS */ + +#ifdef SA_FW_TIMER_READS_STATUS + spc_GSTableDescriptor_t mpiGSTable; + bit32 MsguTcnt_last; /**< DW3 - MSGU Tick count */ + bit32 IopTcnt_last; /**< DW4 - IOP Tick count */ + bit32 Iop1Tcnt_last; /**< DW4 - IOP Tick count */ + +#endif /* SA_FW_TIMER_READS_STATUS */ + + agsaControllerInfo_t ControllerInfo; + agsaIOErrorEventStats_t IoErrorCount; + agsaIOErrorEventStats_t IoEventCount; + + bit32 ResetFailed; + //bit32 FatalDone; + bit32 ForensicLastOffset; + //bit32 FatalAccumLen; + //bit32 NonFatalForensicLastOffset; + //bit32 FatalCurrentLength; + bit32 FatalForensicStep; + bit32 FatalForensicShiftOffset; + bit32 FatalBarLoc; + +#ifdef HIALEAH_ENCRYPTION + agsaEncryptGeneralPage_t EncGenPage; +#endif /* HIALEAH_ENCRYPTION */ +#ifdef SA_ENABLE_TRACE_FUNCTIONS + bit8 traceBuffLookup[16]; + + bit32 TraceDestination; + bit32 TraceMask; + + bit32 TraceBufferLength; + bit32 CurrentTraceIndexWrapCount; + bit32 CurrentTraceIndex; + bit32 traceLineFeedCnt; + bit8 *TraceBuffer; + bit32 TraceBlockReInit; + +#endif /*SA_ENABLE_TRACE_FUNCTIONS*/ + + bit32 registerDump0[REGISTER_DUMP_BUFF_SIZE/4]; /**< register dump buffer 0 */ + bit32 registerDump1[REGISTER_DUMP_BUFF_SIZE/4]; /**< register dump buffer 1 */ + + bit32 autoDeregDeviceflag[AGSA_MAX_VALID_PORTS]; + +#ifdef SA_FW_TEST_INTERRUPT_REASSERT + bit32 CheckAll; + bit32 OldPi[64]; + bit32 OldCi[64]; + bit32 OldFlag[64]; +#endif /* SA_FW_TEST_INTERRUPT_REASSERT */ + + +#ifdef SALL_API_TEST + agsaLLCountInfo_t LLCounters; +#endif +#ifdef FAST_IO_TEST + void *freeFastReq[LL_FAST_IO_SIZE]; /* saFastRequest_t* */ + int freeFastIdx; +#endif +} agsaLLRoot_t; + +#ifdef FAST_IO_TEST +/* + one struct per all prepared Fast IO's; + freed after all IO's are posted to FW and interrupt is triggered; + maintained for error rollback or cancel functionality +*/ +typedef struct saFastRequest_s +{ + bit32 beforePI[AGSA_MAX_INBOUND_Q]; + bit32 inqList[AGSA_MAX_INBOUND_Q]; + bit32 inqMax; + SALINK_LIST requests; /* List of all Fast IORequests */ + void *agRoot; /* agsaRoot_t * */ + bit8 valid; /* to avoid usage when the struct is freed */ +} saFastRequest_t; +#endif + +#endif /*__SATYPES_H__ */ diff --git a/sys/dev/pms/RefTisa/sallsdk/spc/sautil.c b/sys/dev/pms/RefTisa/sallsdk/spc/sautil.c new file mode 100644 index 000000000000..b9f042573402 --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/spc/sautil.c @@ -0,0 +1,834 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +/*******************************************************************************/ +/*! \file sautil.c + * \brief The file contains general helper routines. + * + * + */ +/******************************************************************************/ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#ifdef SA_TESTBASE_EXTRA +#include +#endif /* SA_TESTBASE_EXTRA */ + + +#ifdef SA_ENABLE_TRACE_FUNCTIONS +#ifdef siTraceFileID +#undef siTraceFileID +#endif +#define siTraceFileID 'S' +#endif + +/******************************************************************************/ +/*! \brief Check for Hex digit + * + * + * \param char value + * + * \return -void- + * + */ +/*******************************************************************************/ +int siIsHexDigit(char a) +{ + return ( (((a) >= 'a') && ((a) <= 'z')) || + (((a) >= 'A') && ((a) <= 'Z')) || + (((a) >= '0') && ((a) <= '9')) || + ( (a) == '*')); +} + +/******************************************************************************/ +/*! \brief memcopy + * + * + * \param char value + * + * \return -void- + * + */ +/*******************************************************************************/ +FORCEINLINE +void* +si_memcpy(void *dst, void *src, bit32 count) +{ +/* + bit32 x; + unsigned char *dst1 = (unsigned char *)dst; + unsigned char *src1 = (unsigned char *)src; + + for (x=0; x < count; x++) + dst1[x] = src1[x]; + + return dst; +*/ + return memcpy(dst, src, count); +} + + +/******************************************************************************/ +/*! \brief memset + * + * + * \param char value + * + * \return -void- + * + */ +/*******************************************************************************/ +FORCEINLINE +void* +si_memset(void *s, int c, bit32 n) +{ +/* + bit32 i; + char *dst = (char *)s; + for (i=0; i < n; i++) + { + dst[i] = (char) c; + } + return (void *)(&dst[i-n]); +*/ + return memset(s, c, n); +} + + +/******************************************************************************/ +/*! \brief siDumpActiveIORequests + * + * + * \param char value + * + * \return -void- + * + */ +/*******************************************************************************/ +GLOBAL void +siDumpActiveIORequests( + agsaRoot_t *agRoot, + bit32 count) +{ + bit32 j, num_found = 0; + agsaIORequestDesc_t *pRequestDesc = agNULL; + agsaLLRoot_t *saRoot = agNULL; + bit32 i; + mpiOCQueue_t *circularQ; + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + SA_ASSERT((agNULL != saRoot), ""); + + + saCountActiveIORequests(agRoot); + // return; + + + if(smIS_SPCV(agRoot)) + { + bit32 sp1; + sp1= ossaHwRegRead(agRoot,V_Scratchpad_1_Register ); + + if(SCRATCH_PAD1_V_ERROR_STATE(sp1)) + { + SA_DBG1(("siDumpActiveIORequests: SCRATCH_PAD1_V_ERROR_STAT 0x%x\n",sp1 )); + } + SA_DBG1(("siDumpActiveIORequests: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegRead(agRoot, V_Scratchpad_0_Register))); + SA_DBG1(("siDumpActiveIORequests: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegRead(agRoot, V_Scratchpad_1_Register))); + SA_DBG1(("siDumpActiveIORequests: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegRead(agRoot, V_Scratchpad_2_Register))); + SA_DBG1(("siDumpActiveIORequests: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, V_Scratchpad_3_Register))); + } + + for ( i = 0; i < saRoot->QueueConfig.numOutboundQueues; i++ ) + { + circularQ = &saRoot->outboundQueue[i]; + OSSA_READ_LE_32(circularQ->agRoot, &circularQ->producerIdx, circularQ->piPointer, 0); + if(circularQ->producerIdx != circularQ->consumerIdx) + { + SA_DBG1(("siDumpActiveIORequests:OBQ%d PI 0x%03x CI 0x%03x\n", i,circularQ->producerIdx, circularQ->consumerIdx )); + } + } + + pRequestDesc = (agsaIORequestDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->IORequestMem), 0); + SA_DBG1(("siDumpActiveIORequests: Current Time: %d ticks (usecpertick=%d)\n", + saRoot->timeTick, saRoot->usecsPerTick)); + + for ( j = 0; j < count; j ++ ) + { + pRequestDesc = (agsaIORequestDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->IORequestMem), j); + + if (pRequestDesc->valid == agTRUE) + { + num_found++; + SA_DBG1(("siDumpActiveIORequests: IO #%4d: %p Tag=%03X Type=%08X Device 0x%X Pending for %d seconds\n", + j, + pRequestDesc->pIORequestContext, + pRequestDesc->HTag, + pRequestDesc->requestType, + pRequestDesc->pDevice ? pRequestDesc->pDevice->DeviceMapIndex : 0, + ((saRoot->timeTick - pRequestDesc->startTick)*saRoot->usecsPerTick)/1000000 )); + + } + } + if(count) + { + SA_DBG1(("siDumpActiveIORequests: %d found active\n",num_found)); + } + +} + +/******************************************************************************/ +/*! \brief saCountActiveIORequests + * + * + * \param char value + * + * \return -void- + * + */ +/*******************************************************************************/ +GLOBAL void +siClearActiveIORequests( + agsaRoot_t *agRoot) +{ + bit32 j; + bit32 num_found = 0; + agsaIORequestDesc_t *pRequestDesc = agNULL; + agsaLLRoot_t *saRoot = agNULL; + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + SA_ASSERT((agNULL != saRoot), ""); + + if(saRoot) + { + pRequestDesc = (agsaIORequestDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->IORequestMem), 0); + + for ( j = 0; j < saRoot->swConfig.maxActiveIOs; j++ ) + { + pRequestDesc = (agsaIORequestDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->IORequestMem), j); + + if (pRequestDesc->valid == agTRUE) + { + num_found++; + pRequestDesc->valid = agFALSE; + } + } + if(num_found) + { + SA_DBG1(("siClearActiveIORequests %d found active\n",num_found)); + } + } + else + { + SA_DBG1(("siClearActiveIORequests saroot NULL\n")); + } + +} + +/******************************************************************************/ +/*! \brief siCountActiveIORequestsOnDevice + * count all active IO's + * + * \param char value + * + * \return -void- + * + */ +/*******************************************************************************/ +GLOBAL void +siClearActiveIORequestsOnDevice( + agsaRoot_t *agRoot, + bit32 device ) +{ + bit32 j, num_found = 0; + agsaIORequestDesc_t *pRequestDesc = agNULL; + agsaLLRoot_t *saRoot = agNULL; + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + SA_ASSERT((agNULL != saRoot), ""); + + pRequestDesc = (agsaIORequestDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->IORequestMem), 0); + + for ( j = 0; j < saRoot->swConfig.maxActiveIOs; j++ ) + { + pRequestDesc = (agsaIORequestDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->IORequestMem), j); + + if (pRequestDesc->valid == agTRUE) + { + if (pRequestDesc->pDevice) + { + if (pRequestDesc->pDevice->DeviceMapIndex == device) + { + num_found++; + pRequestDesc->valid = agFALSE; + } + } + } + } + if(num_found) + { + SA_DBG1(("siClearActiveIORequestsOnDevice 0x%x %d cleared\n",device,num_found)); + } + +} + + + +/******************************************************************************/ +/*! \brief siCountActiveIORequestsOnDevice + * count all active IO's + * + * \param char value + * + * \return -void- + * + */ +/*******************************************************************************/ +GLOBAL void +siCountActiveIORequestsOnDevice( + agsaRoot_t *agRoot, + bit32 device ) +{ + bit32 j, num_found = 0; + agsaIORequestDesc_t *pRequestDesc = agNULL; + agsaLLRoot_t *saRoot = agNULL; + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + SA_ASSERT((agNULL != saRoot), ""); + + pRequestDesc = (agsaIORequestDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->IORequestMem), 0); + + for ( j = 0; j < saRoot->swConfig.maxActiveIOs; j++ ) + { + pRequestDesc = (agsaIORequestDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->IORequestMem), j); + + if (pRequestDesc->valid == agTRUE) + { + if (pRequestDesc->pDevice) + { + if (pRequestDesc->pDevice->DeviceMapIndex == device) + { + num_found++; + if(saRoot->ResetStartTick > pRequestDesc->startTick) + { + SA_DBG2(("siCountActiveIORequestsOnDevice: saRoot->ResetStartTick %d pRequestDesc->startTick %d\n", + saRoot->ResetStartTick, pRequestDesc->startTick)); + } + } + } + } + } + if(num_found) + { + SA_DBG1(("siCountActiveIORequestsOnDevice 0x%x %d found active\n",device,num_found)); + } + +} + + + +/******************************************************************************/ +/*! \brief saCountActiveIORequests + * count all active IO's + * + * \param char value + * + * \return -void- + * + */ +/*******************************************************************************/ +GLOBAL void +saCountActiveIORequests( + agsaRoot_t *agRoot) +{ + bit32 j, num_found = 0; + agsaIORequestDesc_t *pRequestDesc = agNULL; + agsaLLRoot_t *saRoot = agNULL; + + /* sanity check */ + SA_ASSERT((agNULL != agRoot), ""); + if( agRoot == agNULL) + { + return; + } + saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + if( saRoot == agNULL) + { + return; + } + pRequestDesc = (agsaIORequestDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->IORequestMem), 0); + + for ( j = 0; j < saRoot->swConfig.maxActiveIOs; j++ ) + { + pRequestDesc = (agsaIORequestDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->IORequestMem), j); + + if (pRequestDesc->valid == agTRUE) + { + num_found++; + if(saRoot->ResetStartTick > pRequestDesc->startTick) + { + SA_DBG2(("saCountActiveIORequests: saRoot->ResetStartTick %d pRequestDesc->startTick %d\n", + saRoot->ResetStartTick, pRequestDesc->startTick)); + } + } + } + if(num_found) + { + SA_DBG1(("saCountActiveIORequests %d found active\n",num_found)); + } + +} + + +GLOBAL bit32 smIsCfg_V_ANY( agsaRoot_t *agRoot) +{ + + if(smIsCfg_V8008(agRoot) == 1) return 1; + if(smIsCfg_V8009(agRoot) == 1) return 1; + if(smIsCfg_V8018(agRoot) == 1) return 1; + if(smIsCfg_V8019(agRoot) == 1) return 1; + if(smIsCfg_V8088(agRoot) == 1) return 1; + if(smIsCfg_V8089(agRoot) == 1) return 1; + if(smIsCfg_V8070(agRoot) == 1) return 1; + if(smIsCfg_V8071(agRoot) == 1) return 1; + if(smIsCfg_V8072(agRoot) == 1) return 1; + if(smIsCfg_V8073(agRoot) == 1) return 1; + if(smIS_SPCV8074(agRoot) == 1) return 1; + if(smIS_SPCV8075(agRoot) == 1) return 1; + if(smIS_SPCV8076(agRoot) == 1) return 1; + if(smIS_SPCV8077(agRoot) == 1) return 1; + if(smIsCfg_V8025(agRoot) == 1) return 1; + if(smIsCfg_V9015(agRoot) == 1) return 1; + if(smIsCfg_V9060(agRoot) == 1) return 1; + if(smIsCfg_V8006(agRoot) == 1) return 1; + + return 0; +} + +GLOBAL bit32 smIS_SPC( agsaRoot_t *agRoot) +{ + if(smIS_spc8001(agRoot) == 1) return 1; + if(smIS_spc8081(agRoot) == 1) return 1; + if(smIS_SFC_AS_SPC(agRoot) == 1) return 1; + return 0; +} + + +GLOBAL bit32 smIS_HIL( agsaRoot_t *agRoot) /* or delray */ +{ + if(smIS_spc8081(agRoot) == 1) return 1; + if(smIS_ADAP8088(agRoot) == 1) return 1; + if(smIS_ADAP8089(agRoot) == 1) return 1; + if(smIS_SPCV8074(agRoot) == 1) return 1; + if(smIS_SPCV8075(agRoot) == 1) return 1; + if(smIS_SPCV8076(agRoot) == 1) return 1; + if(smIS_SPCV8077(agRoot) == 1) return 1; + return 0; + +} + +GLOBAL bit32 smIS_SPC6V( agsaRoot_t *agRoot) +{ + if(smIS_SPCV8008(agRoot) == 1) return 1; + if(smIS_SPCV8009(agRoot) == 1) return 1; + if(smIS_SPCV8018(agRoot) == 1) return 1; + if(smIS_SPCV8019(agRoot) == 1) return 1; + if(smIS_ADAP8088(agRoot) == 1) return 1; + if(smIS_ADAP8089(agRoot) == 1) return 1; + return 0; +} + +GLOBAL bit32 smIS_SPC12V( agsaRoot_t *agRoot) +{ + if(smIS_SPCV8070(agRoot) == 1) return 1; + if(smIS_SPCV8071(agRoot) == 1) return 1; + if(smIS_SPCV8072(agRoot) == 1) return 1; + if(smIS_SPCV8073(agRoot) == 1) return 1; + if(smIS_SPCV8074(agRoot) == 1) return 1; + if(smIS_SPCV8075(agRoot) == 1) return 1; + if(smIS_SPCV8076(agRoot) == 1) return 1; + if(smIS_SPCV8077(agRoot) == 1) return 1; + if(smIS_SPCV9015(agRoot) == 1) return 1; + if(smIS_SPCV9060(agRoot) == 1) return 1; + if(smIS_SPCV8006(agRoot) == 1) return 1; + return 0; +} + +GLOBAL bit32 smIS_SPCV_2_IOP( agsaRoot_t *agRoot) +{ + if(smIS_SPCV8009(agRoot) == 1) return 1; + if(smIS_SPCV8018(agRoot) == 1) return 1; + if(smIS_SPCV8019(agRoot) == 1) return 1; + if(smIS_SPCV8071(agRoot) == 1) return 1; + if(smIS_SPCV8072(agRoot) == 1) return 1; + if(smIS_SPCV8073(agRoot) == 1) return 1; + if(smIS_SPCV8076(agRoot) == 1) return 1; + if(smIS_SPCV8077(agRoot) == 1) return 1; + if(smIS_ADAP8088(agRoot) == 1) return 1; + if(smIS_ADAP8089(agRoot) == 1) return 1; + if(smIS_SPCV8006(agRoot) == 1) return 1; + return 0; +} + +GLOBAL bit32 smIS_SPCV( agsaRoot_t *agRoot) +{ + if(smIS_SPC6V(agRoot) == 1) return 1; + if(smIS_SPC12V(agRoot) == 1) return 1; + if(smIS_SFC_AS_V(agRoot) == 1 ) return 1; + return 0; +} + +GLOBAL bit32 smIS_ENCRYPT( agsaRoot_t *agRoot) +{ + if(smIS_SPCV8009(agRoot) == 1) return 1; + if(smIS_ADAP8088(agRoot) == 1) return 1; + if(smIS_SPCV8019(agRoot) == 1) return 1; + if(smIS_SPCV8071(agRoot) == 1) return 1; + if(smIS_SPCV8073(agRoot) == 1) return 1; + if(smIS_SPCV8077(agRoot) == 1) return 1; + if(smIS_SPCV9015(agRoot) == 1) return 1; + if(smIS_SPCV9060(agRoot) == 1) return 1; + return 0; +} + + + +#if defined(SALLSDK_DEBUG) + +/******************************************************************************/ +/*! \brief Routine print buffer + * + * + * \param debugLevel verbosity level + * \param header header to print + * \param buffer buffer to print + * \param length length of buffer in bytes + * + * \return -void- + * + */ +/*******************************************************************************/ +GLOBAL void siPrintBuffer( + bit32 debugLevel, + siPrintType type, + char *header, + void *a, + bit32 length + ) +{ + bit32 x, rem; + bit8 *buffer = (bit8 *)a; + bit32 *lPtr; + bit8 temp[16]; + + ossaLogDebugString(gLLDebugLevel, debugLevel, ("%s\n", header)); + + if (type == SA_8) + { + for (x=0; x < length/16; x++) + { + ossaLogDebugString(gLLDebugLevel, debugLevel, + ("%02x %02x %02x %02x %02x %02x %02x %02x - %02x %02x %02x %02x %02x %02x %02x %02x == " + "%c%c%c%c%c%c%c%c - %c%c%c%c%c%c%c%c\n", + *(buffer), + *(buffer+1), + *(buffer+2), + *(buffer+3), + *(buffer+4), + *(buffer+5), + *(buffer+6), + *(buffer+7), + *(buffer+8), + *(buffer+9), + *(buffer+10), + *(buffer+11), + *(buffer+12), + *(buffer+13), + *(buffer+14), + *(buffer+15), + siIsHexDigit(*(buffer)) ? *(buffer) : ' ', + siIsHexDigit(*(buffer+1)) ? *(buffer+1) : ' ', + siIsHexDigit(*(buffer+2)) ? *(buffer+2) : ' ', + siIsHexDigit(*(buffer+3)) ? *(buffer+3) : ' ', + siIsHexDigit(*(buffer+4)) ? *(buffer+4) : ' ', + siIsHexDigit(*(buffer+5)) ? *(buffer+5) : ' ', + siIsHexDigit(*(buffer+6)) ? *(buffer+6) : ' ', + siIsHexDigit(*(buffer+7)) ? *(buffer+7) : ' ', + siIsHexDigit(*(buffer+8)) ? *(buffer+8) : ' ', + siIsHexDigit(*(buffer+9)) ? *(buffer+9) : ' ', + siIsHexDigit(*(buffer+10)) ? *(buffer+10) : ' ', + siIsHexDigit(*(buffer+11)) ? *(buffer+11) : ' ', + siIsHexDigit(*(buffer+12)) ? *(buffer+12) : ' ', + siIsHexDigit(*(buffer+13)) ? *(buffer+13) : ' ', + siIsHexDigit(*(buffer+14)) ? *(buffer+14) : ' ', + siIsHexDigit(*(buffer+15)) ? *(buffer+15) : ' ') + ); + + buffer += 16; + } + + rem = length%16; + if (rem) + { + for (x = 0; x < 16; x++) + { + temp[x] = ' '; + } + + for (x = 0; x < rem; x++) + { + temp[x] = *(buffer+x); + } + + buffer = temp; + + ossaLogDebugString(gLLDebugLevel, debugLevel, + ("%02x %02x %02x %02x %02x %02x %02x %02x - %02x %02x %02x %02x %02x %02x %02x %02x == " + "%c%c%c%c%c%c%c%c - %c%c%c%c%c%c%c%c\n", + *(buffer), + *(buffer+1), + *(buffer+2), + *(buffer+3), + *(buffer+4), + *(buffer+5), + *(buffer+6), + *(buffer+7), + *(buffer+8), + *(buffer+9), + *(buffer+10), + *(buffer+11), + *(buffer+12), + *(buffer+13), + *(buffer+14), + *(buffer+15), + siIsHexDigit(*(buffer)) ? *(buffer) : ' ', + siIsHexDigit(*(buffer+1)) ? *(buffer+1) : ' ', + siIsHexDigit(*(buffer+2)) ? *(buffer+2) : ' ', + siIsHexDigit(*(buffer+3)) ? *(buffer+3) : ' ', + siIsHexDigit(*(buffer+4)) ? *(buffer+4) : ' ', + siIsHexDigit(*(buffer+5)) ? *(buffer+5) : ' ', + siIsHexDigit(*(buffer+6)) ? *(buffer+6) : ' ', + siIsHexDigit(*(buffer+7)) ? *(buffer+7) : ' ', + siIsHexDigit(*(buffer+8)) ? *(buffer+8) : ' ', + siIsHexDigit(*(buffer+9)) ? *(buffer+9) : ' ', + siIsHexDigit(*(buffer+10)) ? *(buffer+10) : ' ', + siIsHexDigit(*(buffer+11)) ? *(buffer+11) : ' ', + siIsHexDigit(*(buffer+12)) ? *(buffer+12) : ' ', + siIsHexDigit(*(buffer+13)) ? *(buffer+13) : ' ', + siIsHexDigit(*(buffer+14)) ? *(buffer+14) : ' ', + siIsHexDigit(*(buffer+15)) ? *(buffer+15) : ' ') + ); + } + } + else + { + bit32 *ltemp = (bit32 *)temp; + lPtr = (bit32 *) a; + + for (x=0; x < length/4; x++) + { + ossaLogDebugString(gLLDebugLevel, debugLevel, + ("%08x %08x %08x %08x\n", + *(lPtr), + *(lPtr+1), + *(lPtr+2), + *(lPtr+3)) + ); + + lPtr += 4; + } + + rem = length%4; + if (rem) + { + for (x = 0; x < 4; x++) + { + ltemp[x] = 0; + } + + for (x = 0; x < rem; x++) + { + ltemp[x] = lPtr[x]; + } + + lPtr = ltemp; + + ossaLogDebugString(gLLDebugLevel, debugLevel, + ("%08x %08x %08x %08x\n", + *(lPtr), + *(lPtr+1), + *(lPtr+2), + *(lPtr+3)) + ); + } + } + +} + + + +void sidump_hwConfig(agsaHwConfig_t *hwConfig) +{ + SA_DBG2(("sidump_hwConfig:hwConfig->hwInterruptCoalescingTimer 0x%x\n",hwConfig->hwInterruptCoalescingTimer )); + SA_DBG2(("sidump_hwConfig:hwConfig->hwInterruptCoalescingControl 0x%x\n",hwConfig->hwInterruptCoalescingControl )); + SA_DBG2(("sidump_hwConfig:hwConfig->intReassertionOption 0x%x\n",hwConfig->intReassertionOption )); + SA_DBG2(("sidump_hwConfig:hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister0 0x%x\n",hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister0 )); + SA_DBG2(("sidump_hwConfig:hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister1 0x%x\n",hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister1 )); + SA_DBG2(("sidump_hwConfig:hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister2 0x%x\n",hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister2 )); + SA_DBG2(("sidump_hwConfig:hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister3 0x%x\n",hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister3 )); + SA_DBG2(("sidump_hwConfig:hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister4 0x%x\n",hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister4 )); + SA_DBG2(("sidump_hwConfig:hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister5 0x%x\n",hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister5 )); + SA_DBG2(("sidump_hwConfig:hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister6 0x%x\n",hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister6 )); + SA_DBG2(("sidump_hwConfig:hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister7 0x%x\n",hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister7 )); + SA_DBG2(("sidump_hwConfig:hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister8 0x%x\n",hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister8 )); + SA_DBG2(("sidump_hwConfig:hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister9 0x%x\n",hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister9 )); + SA_DBG2(("sidump_hwConfig:hwConfig->hwOption 0x%x\n",hwConfig->hwOption )); +} + +void sidump_swConfig(agsaSwConfig_t *swConfig) +{ + SA_DBG2(("sidump_swConfig:swConfig->maxActiveIOs 0x%x\n",swConfig->maxActiveIOs )); + SA_DBG2(("sidump_swConfig:swConfig->numDevHandles 0x%x\n",swConfig->numDevHandles )); + SA_DBG2(("sidump_swConfig:swConfig->smpReqTimeout 0x%x\n",swConfig->smpReqTimeout )); + SA_DBG2(("sidump_swConfig:swConfig->numberOfEventRegClients 0x%x\n",swConfig->numberOfEventRegClients )); + SA_DBG2(("sidump_swConfig:swConfig->sizefEventLog1 0x%x\n",swConfig->sizefEventLog1 )); + SA_DBG2(("sidump_swConfig:swConfig->sizefEventLog2 0x%x\n",swConfig->sizefEventLog2 )); + SA_DBG2(("sidump_swConfig:swConfig->eventLog1Option 0x%x\n",swConfig->eventLog1Option )); + SA_DBG2(("sidump_swConfig:swConfig->eventLog2Option 0x%x\n",swConfig->eventLog2Option )); + SA_DBG2(("sidump_swConfig:swConfig->fatalErrorInterruptEnable 0x%x\n",swConfig->fatalErrorInterruptEnable )); + SA_DBG2(("sidump_swConfig:swConfig->fatalErrorInterruptVector 0x%x\n",swConfig->fatalErrorInterruptVector )); + SA_DBG2(("sidump_swConfig:swConfig->max_MSI_InterruptVectors 0x%x\n",swConfig->max_MSI_InterruptVectors )); + SA_DBG2(("sidump_swConfig:swConfig->max_MSIX_InterruptVectors 0x%x\n",swConfig->max_MSIX_InterruptVectors )); + SA_DBG2(("sidump_swConfig:swConfig->legacyInt_X 0x%x\n",swConfig->legacyInt_X )); + SA_DBG2(("sidump_swConfig:swConfig->hostDirectAccessSupport 0x%x\n",swConfig->hostDirectAccessSupport )); + SA_DBG2(("sidump_swConfig:swConfig->hostDirectAccessMode 0x%x\n",swConfig->hostDirectAccessMode )); + SA_DBG2(("sidump_swConfig:swConfig->param1 0x%x\n",swConfig->param1 )); + SA_DBG2(("sidump_swConfig:swConfig->param2 0x%x\n",swConfig->param2 )); + SA_DBG2(("sidump_swConfig:swConfig->param3 %p\n",swConfig->param3 )); + SA_DBG2(("sidump_swConfig:swConfig->param4 %p\n",swConfig->param4 )); + +} + + +void sidump_Q_config( agsaQueueConfig_t *queueConfig ) +{ + bit32 x; + + SA_DBG2(("sidump_Q_config: queueConfig->generalEventQueue 0x%x\n", queueConfig->generalEventQueue )); + SA_DBG2(("sidump_Q_config: queueConfig->numInboundQueues 0x%x\n", queueConfig->numInboundQueues )); + SA_DBG2(("sidump_Q_config: queueConfig->numOutboundQueues 0x%x\n", queueConfig->numOutboundQueues )); + SA_DBG2(("sidump_Q_config: queueConfig->iqHighPriorityProcessingDepth 0x%x\n", queueConfig->iqHighPriorityProcessingDepth )); + SA_DBG2(("sidump_Q_config: queueConfig->iqNormalPriorityProcessingDepth 0x%x\n", queueConfig->iqNormalPriorityProcessingDepth )); + SA_DBG2(("sidump_Q_config: queueConfig->queueOption 0x%x\n", queueConfig->queueOption )); + SA_DBG2(("sidump_Q_config: queueConfig->tgtDeviceRemovedEventQueue 0x%x\n", queueConfig->tgtDeviceRemovedEventQueue )); + + for(x=0;x < queueConfig->numInboundQueues;x++) + { + SA_DBG2(("sidump_Q_config: queueConfig->inboundQueues[%d].elementCount 0x%x\n",x,queueConfig->inboundQueues[x].elementCount )); + SA_DBG2(("sidump_Q_config: queueConfig->inboundQueues[%d].elementSize 0x%x\n",x,queueConfig->inboundQueues[x].elementSize )); + } + + for(x=0;x < queueConfig->numOutboundQueues;x++) + { + + SA_DBG2(("sidump_Q_config: queueConfig->outboundQueues[%d].elementCount 0x%x\n",x,queueConfig->outboundQueues[x].elementCount )); + SA_DBG2(("sidump_Q_config: queueConfig->outboundQueues[%d].elementSize 0x%x\n",x,queueConfig->outboundQueues[x].elementSize )); + } + +} +#endif + +#ifdef SALL_API_TEST +/******************************************************************************/ +/*! \brief Get Performance IO counters + * + * Start/Abort SAS/SATA discovery + * + * \param agRoot Handles for this instance of SAS/SATA hardware + * \param counters bit map of the counters + * \param LLCountInfo pointer to the LLCounters + * + * \return + * - \e AGSA_RC_SUCCESS + * + */ +/*******************************************************************************/ +GLOBAL bit32 saGetLLCounters( + agsaRoot_t *agRoot, + bit32 counters, + agsaLLCountInfo_t *LLCountInfo + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + bit32 i; + + for (i = 0; i < LL_COUNTERS; i++) + { + if (counters & (1 << i)) + LLCountInfo->arrayIOCounter[i] = saRoot->LLCounters.arrayIOCounter[i]; + } + + return AGSA_RC_SUCCESS; +} + +/******************************************************************************/ +/*! \brief Function for target to remove stale initiator device handle + * + * function is called to ask the LL layer to remove all LL layer and SPC firmware + * internal resources associated with a device handle + * + * \param agRoot Handles for this instance of SAS/SATA hardware + * \param counters Bit map of the IO counters + * + * \return + * - \e AGSA_RC_SUCCESS + * + */ +/*******************************************************************************/ +GLOBAL bit32 saResetLLCounters( + agsaRoot_t *agRoot, + bit32 counters + ) +{ + agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); + bit32 i; + + for (i = 0; i < LL_COUNTERS; i++) + { + if (counters & (1 << i)) + saRoot->LLCounters.arrayIOCounter[i] = 0; + } + + return AGSA_RC_SUCCESS; +} +#endif + diff --git a/sys/dev/pms/RefTisa/sallsdk/spc/spcdefs.h b/sys/dev/pms/RefTisa/sallsdk/spc/spcdefs.h new file mode 100644 index 000000000000..510b989fb959 --- /dev/null +++ b/sys/dev/pms/RefTisa/sallsdk/spc/spcdefs.h @@ -0,0 +1,553 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/*******************************************************************************/ +/*! \file spcdefs.h + * \brief The file defines the MPI Application Programming Interface (API) + * + * The file defines the MPI Application Programming Interfacde (API) + * + */ +/*******************************************************************************/ +#ifndef __SPCDEFS_H__ +#define __SPCDEFS_H__ + +/*******************************************************************************/ +/*******************************************************************************/ +/* CONSTANTS */ +/*******************************************************************************/ +/*******************************************************************************/ +/*******************************************************************************/ +/* MSGU CONFIGURATION TABLE */ +/*******************************************************************************/ +#define SPC_MSGU_CFG_TABLE_UPDATE 0x001 /* Inbound doorbell bit0 */ +#define SPC_MSGU_CFG_TABLE_RESET 0x002 /* Inbound doorbell bit1 */ +#define SPC_MSGU_CFG_TABLE_FREEZE 0x004 /* Inbound doorbell bit2 */ +#define SPC_MSGU_CFG_TABLE_UNFREEZE 0x008 /* Inbound doorbell bit4 */ +#define SPCV_MSGU_CFG_TABLE_TRANSFER_DEBUG_INFO 0x080 /* Inbound doorbell bit7 SPCV */ +#define SPCV_MSGU_HALT_CPUS 0x100 /* Inbound doorbell bit8 SPCV */ + +/***** Notes *****/ +/* The firmware side is using Little Endian (MIPs). */ +/* So anything sending or receiving from FW must be in Little Endian */ +/*******************************************************************************/ +/** \struct mpiMsgHeader_s + * \brief MPI message header + * + * The mpiMsgHeader_s defines the fields in the header of every message + */ +/*******************************************************************************/ +/* This structire defines the fields in the header of every message */ + + +struct mpiMsgHeader_s +{ + bit32 Header; /* Bits [11:0] - Message operation code */ + /* Bits [15:12] - Message Category */ + /* Bits [21:16] - Outboundqueue ID for the operation completion message */ + /* Bits [23:22] - Reserved */ + /* Bits [28:24] - Buffer Count, indicates how many buffer are allocated for the massage */ + /* Bits [30:29] - Reserved */ + /* Bits [31] - Message Valid bit */ +}; + +typedef struct mpiMsgHeader_s mpiMsgHeader_t; + +#define V_BIT 0x1 + +#define V_MASK 0x1 +#define BC_MASK 0x1F +#define OBID_MASK 0x3F +#define CAT_MASK 0x0F +#define OPCODE_MASK 0xFFF +#define HEADER_V_MASK 0x80000000 +#define HEADER_BC_MASK 0x1f000000 + +#ifndef SPC_CONFIG +/*******************************************************************************/ +/** \struct spc_ConfigMainDescriptor_s + * \brief This structure is used to configure main part of Configuration Table + * + * This structure specifies all required attributes to configuration table + */ +/*******************************************************************************/ +/* new MPI configuration main table */ +struct spc_configMainDescriptor_s +{ + bit8 Signature[4]; /**< DW0 signature - Indicate coherent table */ + bit32 InterfaceRev; /**< DW1 Revsion of Interface */ + bit32 FWRevision; /**< DW2 Revsion of FW */ + bit32 MaxOutstandingIO; /**< DW3 Max outstanding IO */ + bit32 MDevMaxSGL; /**< DW4 Maximum SGL elements & Max Devices */ + /* bit0-15 Maximum SGL */ + /* bit16-31 Maximum Devices */ + bit32 ContrlCapFlag; /**< DW5 Controller Capability */ + /* bit0-7 Max number of inbound queue */ + /* bit8-15 Max number of outbound queue */ + /* bit16 high priority of inbound queue is supported */ + /* bit17 reserved */ + /* bit18 interrupt coalescing is supported, SPCV-reserved */ + /* bit19-24 Maximum number of valid phys */ + /* bit25-31 SAS Revision SPecification */ + bit32 GSTOffset; /**< DW6 General Status Table */ + bit32 inboundQueueOffset; /**< DW7 inbound configuration table offset */ + /* bit23-0 inbound queue table offset */ + /* bit31-24 entry size, new in SPCV */ + bit32 outboundQueueOffset; /**< DW8 outbound configuration table offset */ + /* bit23-0 outbound queue table offset */ + /* bit31-24 entry size, new in SPCV */ + bit32 iQNPPD_HPPD_GEvent; /**< DW9 inbound Queue Process depth and General Event */ + /* bit0-7 inbound normal priority process depth */ + /* bit8-15 inbound high priority process depth */ + /* bit16-23 OQ number to receive GENERAL_EVENT Notification */ + /* bit24-31 OQ number to receive DEVICE_HANDLE_REMOVAL Notification */ + bit32 outboundHWEventPID0_3; /**< DWA outbound HW event for PortId 0 to 3, SPCV-reserved */ + /* bit0-7 outbound queue number of SAS_HW event for PhyId 0 */ + /* bit8-15 outbound queue number of SAS_HW event for PhyId 1 */ + /* bit16-23 outbound queue number of SAS_HW event for PhyId 2 */ + /* bit24-31 outbound queue number of SAS_HW event for PhyId 3 */ + bit32 outboundHWEventPID4_7; /**< DWB outbound HW event for PortId 4 to 7, SPCV-reserved */ + /* bit0-7 outbound queue number of SAS_HW event for PhyId 4 */ + /* bit8-15 outbound queue number of SAS_HW event for PhyId 5 */ + /* bit16-23 outbound queue number of SAS_HW event for PhyId 6 */ + /* bit24-31 outbound queue number of SAS_HW event for PhyId 7 */ + bit32 outboundNCQEventPID0_3; /**< DWC outbound NCQ event for PortId 0 to 3, SPCV-reserved */ + /* bit0-7 outbound queue number of SATA_NCQ event for PhyId 0 */ + /* bit8-15 outbound queue number of SATA_NCQ event for PhyId 1 */ + /* bit16-23 outbound queue number of SATA_NCQ event for PhyId 2 */ + /* bit24-31 outbound queue number of SATA_NCQ event for PortId 3 */ + bit32 outboundNCQEventPID4_7; /**< DWD outbound NCQ event for PortId 4 to 7, SPCV-reserved*/ + /* bit0-7 outbound queue number of SATA_NCQ event for PhyId 4 */ + /* bit8-15 outbound queue number of SATA_NCQ event for PhyId 5 */ + /* bit16-23 outbound queue number of SATA_NCQ event for PhyId 6 */ + /* bit24-31 outbound queue number of SATA_NCQ event for PhyId 7 */ + bit32 outboundTargetITNexusEventPID0_3; /**< DWE outbound target ITNexus Event for PortId 0 to 3, SPCV-reserved */ + /* bit0-7 outbound queue number of ITNexus event for PhyId 0 */ + /* bit8-15 outbound queue number of ITNexus event for PhyId 1 */ + /* bit16-23 outbound queue number of ITNexus event for PhyId 2 */ + /* bit24-31 outbound queue number of ITNexus event for PhyId 3 */ + bit32 outboundTargetITNexusEventPID4_7; /**< DWF outbound target ITNexus Event for PortId 4 to 7, SPCV-reserved */ + /* bit0-7 outbound queue number of ITNexus event for PhyId 4 */ + /* bit8-15 outbound queue number of ITNexus event for PhyId 5 */ + /* bit16-23 outbound queue number of ITNexus event for PhyId 6 */ + /* bit24-31 outbound queue number of ITNexus event for PhyId 7 */ + bit32 outboundTargetSSPEventPID0_3; /**< DW10 outbound target SSP event for PordId 0 to 3, SPCV-reserved */ + /* bit0-7 outbound queue number of SSP event for PhyId 0 */ + /* bit8-15 outbound queue number of SSP event for PhyId 1 */ + /* bit16-23 outbound queue number of SSP event for PhyId 2 */ + /* bit24-31 outbound queue number of SSP event for PhyId 3 */ + bit32 outboundTargetSSPEventPID4_7; /**< DW11 outbound target SSP event for PordId 4 to 7, SPCV-reserved */ + /* bit0-7 outbound queue number of SSP event for PhyId 4 */ + /* bit8-15 outbound queue number of SSP event for PhyId 5 */ + /* bit16-23 outbound queue number of SSP event for PhyId 6 */ + /* bit24-31 outbound queue number of SSP event for PhyId 7 */ + bit32 ioAbortDelay; /**< DW12 IO Abort Delay (bit15:0) MPI_TABLE_CHANGE*/ + bit32 custset; /**< DW13 custset */ + bit32 upperEventLogAddress; /**< DW14 Upper physical MSGU Event log address */ + bit32 lowerEventLogAddress; /**< DW15 Lower physical MSGU Event log address */ + bit32 eventLogSize; /**< DW16 Size of MSGU Event log, 0 means log disable */ + bit32 eventLogOption; /**< DW17 Option of MSGU Event log */ + /* bit3-0 log severity, 0x0 Disable Logging */ + /* 0x1 Critical Error */ + /* 0x2 Minor Error */ + /* 0x3 Warning */ + /* 0x4 Information */ + /* 0x5 Debugging */ + /* 0x6 - 0xF Reserved */ + bit32 upperIOPeventLogAddress; /**< DW18 Upper physical IOP Event log address */ + bit32 lowerIOPeventLogAddress; /**< DW19 Lower physical IOP Event log address */ + bit32 IOPeventLogSize; /**< DW1A Size of IOP Event log, 0 means log disable */ + bit32 IOPeventLogOption; /**< DW1B Option of IOP Event log */ + /* bit3-0 log severity, 0x0 Critical Error */ + /* 0x1 Minor Error */ + /* 0x2 Warning */ + /* 0x3 Information */ + /* 0x4 Unknown */ + /* 0x5 - 0xF Reserved */ + bit32 FatalErrorInterrupt; /**< DW1C Fatal Error Interrupt enable and vector */ + /* bit0 Fatal Error Interrupt Enable */ + /* bit1 PI/CI 64bit address */ + /* bit2 SGPIO IOMB support */ + /* bit6-2 Reserved */ + /* bit7 OQ NP/HPriority Path enable */ + /* bit15-8 Fatal Error Interrupt Vector */ + /* bit16 Enable IQ/OQ 64 */ + /* bit17 Interrupt Reassertion Enable */ + /* bit18 Interrupt Reassertion Delay in ms */ + /* bit31-19 Interrupt Reassertion delay, 0-default 1ms */ + bit32 FatalErrorDumpOffset0; /**< DW1D FERDOMS-GU Fatal Error Register Dump Offset for MSGU */ + bit32 FatalErrorDumpLength0; /**< DW1E FERDLMS-GU Fatal Error Register Dump Length for MSGU */ + bit32 FatalErrorDumpOffset1; /**< DW1F FERDO-SSTRUCPCS Fatal Error Register Dump Offset for IOP */ + bit32 FatalErrorDumpLength1; /**< DW20 FERDLSTRUCTTPCS Fatal Error Register Dump Length for IOP */ + bit32 HDAModeFlags; /**< DW21 HDA Mode Flags, SPCV-reserved */ + bit32 analogSetupTblOffset; /**< DW22 SPASTO Phy Calibration Table offset */ + /* bit23-0 phy calib table offset */ + /* bit31-24 entry size */ + bit32 InterruptVecTblOffset; /**< DW23 Interrupt Vector Table MPI_TABLE_CHANG */ + /* bit23-0 interrupt vector table offset */ + /* bit31-24 entry size */ + bit32 phyAttributeTblOffset; /**< DW24 SAS Phy Attribute Table Offset MPI_TABLE_CHANG*/ + /* bit23-0 phy attribute table offset */ + /* bit31-24 entry size */ + bit32 portRecoveryResetTimer; /* Offset 0x25 [31:16] Port recovery timer default that is 0 + used for all SAS ports. Granularity of this timer is 100ms. The host can + change the individual port recovery timer by using the PORT_CONTROL + [15:0] Port reset timer default that is used 3 (i.e 300ms) for all + SAS ports. Granularity of this timer is 100ms. Host can change the + individual port recovery timer by using PORT_CONTROL Command */ + bit32 interruptReassertionDelay; /* Offset 0x26 [23:0] Remind host of outbound completion 0 disabled 100usec per increment */ + + bit32 ilaRevision; /* Offset 0x27 */ +}; + +/* main configuration offset - byte offset */ +#define MAIN_SIGNATURE_OFFSET 0x00 /* DWORD 0x00 (R) */ +#define MAIN_INTERFACE_REVISION 0x04 /* DWORD 0x01 (R) */ +#define MAIN_FW_REVISION 0x08 /* DWORD 0x02 (R) */ +#define MAIN_MAX_OUTSTANDING_IO_OFFSET 0x0C /* DWORD 0x03 (R) */ +#define MAIN_MAX_SGL_OFFSET 0x10 /* DWORD 0x04 (R) */ +#define MAIN_CNTRL_CAP_OFFSET 0x14 /* DWORD 0x05 (R) */ +#define MAIN_GST_OFFSET 0x18 /* DWORD 0x06 (R) */ +#define MAIN_IBQ_OFFSET 0x1C /* DWORD 0x07 (R) */ +#define MAIN_OBQ_OFFSET 0x20 /* DWORD 0x08 (R) */ +#define MAIN_IQNPPD_HPPD_OFFSET 0x24 /* DWORD 0x09 (W) */ +#define MAIN_OB_HW_EVENT_PID03_OFFSET 0x28 /* DWORD 0x0A (W) */ /* reserved for SPCV */ +#define MAIN_OB_HW_EVENT_PID47_OFFSET 0x2C /* DWORD 0x0B (W) */ /* reserved for SPCV */ +#define MAIN_OB_NCQ_EVENT_PID03_OFFSET 0x30 /* DWORD 0x0C (W) */ /* reserved for SPCV */ +#define MAIN_OB_NCQ_EVENT_PID47_OFFSET 0x34 /* DWORD 0x0D (W) */ /* reserved for SPCV */ +#define MAIN_TITNX_EVENT_PID03_OFFSET 0x38 /* DWORD 0x0E (W) */ /* reserved for SPCV */ +#define MAIN_TITNX_EVENT_PID47_OFFSET 0x3C /* DWORD 0x0F (W) */ /* reserved for SPCV */ +#define MAIN_OB_SSP_EVENT_PID03_OFFSET 0x40 /* DWORD 0x10 (W) */ /* reserved for SPCV */ +#define MAIN_OB_SSP_EVENT_PID47_OFFSET 0x44 /* DWORD 0x11 (W) */ /* reserved for SPCV */ +#define MAIN_IO_ABORT_DELAY 0x48 /* DWORD 0x12 (W) */ /* reserved for SPCV */ +#define MAIN_CUSTOMER_SETTING 0x4C /* DWORD 0x13 (W) */ /* reserved for SPCV */ +#define MAIN_EVENT_LOG_ADDR_HI 0x50 /* DWORD 0x14 (W) */ +#define MAIN_EVENT_LOG_ADDR_LO 0x54 /* DWORD 0x15 (W) */ +#define MAIN_EVENT_LOG_BUFF_SIZE 0x58 /* DWORD 0x16 (W) */ +#define MAIN_EVENT_LOG_OPTION 0x5C /* DWORD 0x17 (W) */ +#define MAIN_IOP_EVENT_LOG_ADDR_HI 0x60 /* DWORD 0x18 (W) */ +#define MAIN_IOP_EVENT_LOG_ADDR_LO 0x64 /* DWORD 0x19 (W) */ +#define MAIN_IOP_EVENT_LOG_BUFF_SIZE 0x68 /* DWORD 0x1A (W) */ +#define MAIN_IOP_EVENT_LOG_OPTION 0x6C /* DWORD 0x1B (W) */ +#define MAIN_FATAL_ERROR_INTERRUPT 0x70 /* DWORD 0x1C (W) */ +#define MAIN_FATAL_ERROR_RDUMP0_OFFSET 0x74 /* DWORD 0x1D (R) */ +#define MAIN_FATAL_ERROR_RDUMP0_LENGTH 0x78 /* DWORD 0x1E (R) */ +#define MAIN_FATAL_ERROR_RDUMP1_OFFSET 0x7C /* DWORD 0x1F (R) */ +#define MAIN_FATAL_ERROR_RDUMP1_LENGTH 0x80 /* DWORD 0x20 (R) */ +#define MAIN_HDA_FLAGS_OFFSET 0x84 /* DWORD 0x21 (R) */ /* reserved for SPCV */ +#define MAIN_ANALOG_SETUP_OFFSET 0x88 /* DWORD 0x22 (R) */ +#define MAIN_INT_VEC_TABLE_OFFSET 0x8C /* DWORD 0x23 (W) */ /* for SPCV */ +#define MAIN_PHY_ATTRIBUTE_OFFSET 0x90 /* DWORD 0x24 (W) */ /* for SPCV */ +#define MAIN_PRECTD_PRESETD 0x94 /* DWORD 0x25 (W) */ /* for SPCV */ +#define MAIN_IRAD_RESERVED 0x98 /* DWORD 0x26 (W) */ /* for SPCV */ +#define MAIN_MOQFOT_MOQFOES 0x9C /* DWORD 0x27 (W) */ /* for SPCV */ +#define MAIN_MERRDCTO_MERRDCES 0xA0 /* DWORD 0x28 (W) */ /* for SPCV */ +#define MAIN_ILAT_ILAV_ILASMRN_ILAMRN_ILAMJN 0xA4 /* DWORD 0x29 (W) */ /* for SPCV */ +#define MAIN_INACTIVE_ILA_REVSION 0xA8 /* DWORD 0x2A (W) */ /* for SPCV V 3.02 */ +#define MAIN_SEEPROM_REVSION 0xAC /* DWORD 0x2B (W) */ /* for SPCV V 3.02 */ +#define MAIN_UNKNOWN1 0xB0 /* DWORD 0x2C (W) */ /* for SPCV V 3.03 */ +#define MAIN_UNKNOWN2 0xB4 /* DWORD 0x2D (W) */ /* for SPCV V 3.03 */ +#define MAIN_UNKNOWN3 0xB8 /* DWORD 0x2E (W) */ /* for SPCV V 3.03 */ +#define MAIN_XCBI_REF_TAG_PAT 0xBC /* DWORD 0x2F (W) */ /* for SPCV V 3.03 */ +#define MAIN_AWT_MIDRANGE 0xC0 /* DWORD 0x30 (W) */ /* for SPCV V 3.03 */ + + +typedef struct spc_configMainDescriptor_s spc_configMainDescriptor_t; +#define SPC_CONFIG +#endif + +/* bit to disable end to end crc checking ins SPCv */ +#define MAIN_IO_ABORT_DELAY_END_TO_END_CRC_DISABLE 0x00010000 + +/* bit mask for field Controller Capability in main part */ +#define MAIN_MAX_IB_MASK 0x000000ff /* bit7-0 */ +#define MAIN_MAX_OB_MASK 0x0000ff00 /* bit15-8 */ +#define MAIN_PHY_COUNT_MASK 0x01f80000 /* bit24-19 */ +#define MAIN_QSUPPORT_BITS 0x0007ffff +#define MAIN_SAS_SUPPORT_BITS 0xfe000000 + +/* bit mask for field max sgl in main part */ +#define MAIN_MAX_SGL_BITS 0xFFFF +#define MAIN_MAX_DEV_BITS 0xFFFF0000 + +/* bit mask for HDA flags field */ +#define MAIN_HDA_FLAG_BITS 0x000000FF + +#define FATAL_ERROR_INT_BITS 0xFF +#define INT_REASRT_ENABLE 0x00020000 +#define INT_REASRT_MS_ENABLE 0x00040000 +#define INT_REASRT_DELAY_BITS 0xFFF80000 + +#define MAX_VALID_PHYS 8 +#define IB_QUEUE_CFGSIZE 64 +#define OB_QUEUE_CFGSIZE 64 + +/* inbound queue configuration offset - byte offset */ +#define IB_PROPERITY_OFFSET 0x00 +#define IB_BASE_ADDR_HI_OFFSET 0x04 +#define IB_BASE_ADDR_LO_OFFSET 0x08 +#define IB_CI_BASE_ADDR_HI_OFFSET 0x0C +#define IB_CI_BASE_ADDR_LO_OFFSET 0x10 +#define IB_PIPCI_BAR 0x14 +#define IB_PIPCI_BAR_OFFSET 0x18 +#define IB_RESERVED_OFFSET 0x1C + +/* outbound queue configuration offset - byte offset */ +#define OB_PROPERITY_OFFSET 0x00 +#define OB_BASE_ADDR_HI_OFFSET 0x04 +#define OB_BASE_ADDR_LO_OFFSET 0x08 +#define OB_PI_BASE_ADDR_HI_OFFSET 0x0C +#define OB_PI_BASE_ADDR_LO_OFFSET 0x10 +#define OB_CIPCI_BAR 0x14 +#define OB_CIPCI_BAR_OFFSET 0x18 +#define OB_INTERRUPT_COALES_OFFSET 0x1C +#define OB_DYNAMIC_COALES_OFFSET 0x20 + +#define OB_PROPERTY_INT_ENABLE 0x40000000 + +/* General Status Table offset - byte offset */ +#define GST_GSTLEN_MPIS_OFFSET 0x00 +#define GST_IQ_FREEZE_STATE0_OFFSET 0x04 +#define GST_IQ_FREEZE_STATE1_OFFSET 0x08 +#define GST_MSGUTCNT_OFFSET 0x0C +#define GST_IOPTCNT_OFFSET 0x10 +#define GST_IOP1TCNT_OFFSET 0x14 +#define GST_PHYSTATE_OFFSET 0x18 /* SPCV reserved */ +#define GST_PHYSTATE0_OFFSET 0x18 /* SPCV reserved */ +#define GST_PHYSTATE1_OFFSET 0x1C /* SPCV reserved */ +#define GST_PHYSTATE2_OFFSET 0x20 /* SPCV reserved */ +#define GST_PHYSTATE3_OFFSET 0x24 /* SPCV reserved */ +#define GST_PHYSTATE4_OFFSET 0x28 /* SPCV reserved */ +#define GST_PHYSTATE5_OFFSET 0x2C /* SPCV reserved */ +#define GST_PHYSTATE6_OFFSET 0x30 /* SPCV reserved */ +#define GST_PHYSTATE7_OFFSET 0x34 /* SPCV reserved */ +#define GST_GPIO_PINS_OFFSET 0x38 +#define GST_RERRINFO_OFFSET 0x44 + +/* General Status Table - MPI state */ +#define GST_MPI_STATE_UNINIT 0x00 +#define GST_MPI_STATE_INIT 0x01 +#define GST_MPI_STATE_TERMINATION 0x02 +#define GST_MPI_STATE_ERROR 0x03 +#define GST_MPI_STATE_MASK 0x07 + +#define GST_INF_STATE_BITS 0xfffe0007 + + +/* MPI fatal and non fatal offset mask */ +#define MPI_FATAL_ERROR_TABLE_OFFSET_MASK 0xFFFFFF +#define MPI_FATAL_ERROR_TABLE_SIZE(value) ((0xFF000000 & value) >> SHIFT24) /* for SPCV */ + +/* MPI fatal and non fatal Error dump capture table offset - byte offset */ +#define MPI_FATAL_EDUMP_TABLE_LO_OFFSET 0x00 /* HNFBUFL */ +#define MPI_FATAL_EDUMP_TABLE_HI_OFFSET 0x04 /* HNFBUFH */ +#define MPI_FATAL_EDUMP_TABLE_LENGTH 0x08 /* HNFBLEN */ +#define MPI_FATAL_EDUMP_TABLE_HANDSHAKE 0x0C /* FDDHSHK */ +#define MPI_FATAL_EDUMP_TABLE_STATUS 0x10 /* FDDTSTAT */ +#define MPI_FATAL_EDUMP_TABLE_ACCUM_LEN 0x14 /* ACCDDLEN */ +/* */ +#define MPI_FATAL_EDUMP_HANDSHAKE_RDY 0x1 +#define MPI_FATAL_EDUMP_HANDSHAKE_BUSY 0x0 +/* */ +#define MPI_FATAL_EDUMP_TABLE_STAT_RSVD 0x0 +#define MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED 0x1 +#define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA 0x2 +#define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE 0x3 + +#define IOCTL_ERROR_NO_FATAL_ERROR 0x77 + +/*******************************************************************************/ +/** \struct spc_GSTableDescriptor_s + * \brief This structure is used for SPC MPI General Status Table + * + * This structure specifies all required attributes to Gereral Status Table + */ +/*******************************************************************************/ +struct spc_GSTableDescriptor_s +{ + bit32 GSTLenMPIS; /**< DW0 - GST Length, MPI State */ + /**< bit02-00 MPI state */ + /**< 000 - not initialized, 001 - initialized, + 010 - Configuration termination in progress */ + /**< bit3 - IQ Frozen */ + /**< bit15-04 GST Length */ + /**< bit31-16 MPI-S Initialize Error */ + bit32 IQFreezeState0; /**< DW1 - Inbound Queue Freeze State0 */ + bit32 IQFreezeState1; /**< DW2 - Inbound Qeue Freeze State1 */ + bit32 MsguTcnt; /**< DW3 - MSGU Tick count */ + bit32 IopTcnt; /**< DW4 - IOP Tick count */ + bit32 Iop1Tcnt; /**< DW5 - IOP1 Tick count */ + bit32 PhyState[MAX_VALID_PHYS]; /* SPCV = reserved */ + /**< DW6 to DW 0D - Phy Link state 0 to 7, Phy Start State 0 to 7 */ + /**< bit00 Phy Start state n, 0 not started, 1 started */ + /**< bit01 Phy Link state n, 0 link down, 1 link up */ + /**< bit31-2 Reserved */ + bit32 GPIOpins; /**< DWE - GPIO pins */ + bit32 reserved1; /**< DWF - reserved */ + bit32 reserved2; /**< DW10 - reserved */ + bit32 recoverErrInfo[8]; /**< DW11 to DW18 - Recoverable Error Information */ +}; + +typedef struct spc_GSTableDescriptor_s spc_GSTableDescriptor_t; + +/*******************************************************************************/ +/** \struct spc_SPASTable_s + * \brief SAS Phy Analog Setup Table + * + * The spc_SPASTable_s structure is used to set Phy Calibration + * attributes + */ +/*******************************************************************************/ +struct spc_SPASTable_s +{ + bit32 spaReg0; /* transmitter per port configuration 1 SAS_SATA G1 */ + bit32 spaReg1; /* transmitter per port configuration 2 SAS_SATA G1*/ + bit32 spaReg2; /* transmitter per port configuration 3 SAS_SATA G1*/ + bit32 spaReg3; /* transmitter configuration 1 */ + bit32 spaReg4; /* reveiver per port configuration 1 SAS_SATA G1G2 */ + bit32 spaReg5; /* reveiver per port configuration 2 SAS_SATA G3 */ + bit32 spaReg6; /* reveiver per configuration 1 */ + bit32 spaReg7; /* reveiver per configuration 2 */ + bit32 reserved[2]; /* reserved */ +}; + +typedef struct spc_SPASTable_s spc_SPASTable_t; + +/*******************************************************************************/ +/** \struct spc_inboundQueueDescriptor_s + * \brief This structure is used to configure inbound queues + * + * This structure specifies all required attributes to configure inbound queues + */ +/*******************************************************************************/ +struct spc_inboundQueueDescriptor_s +{ + bit32 elementPriSizeCount; /**< Priority, Size, Count in the queue */ + /**< bit00-15 Count */ + /**< When set to 0, this queue is disabled */ + /**< bit16-29 Size */ + /**< bit30-31 Priority 00:Normal, 01:High Priority */ + bit32 upperBaseAddress; /**< Upper address bits for the queue message buffer pool */ + bit32 lowerBaseAddress; /**< Lower address bits for the queue message buffer pool */ + bit32 ciUpperBaseAddress; /**< Upper physical address for inbound queue CI */ + bit32 ciLowerBaseAddress; /**< Lower physical address for inbound queue CI */ + bit32 PIPCIBar; /**< PCI BAR for PI Offset */ + bit32 PIOffset; /**< Offset address for inbound queue PI */ + bit32 reserved; /**< reserved */ +}; + +typedef struct spc_inboundQueueDescriptor_s spc_inboundQueueDescriptor_t; + +/*******************************************************************************/ +/** \struct spc_outboundQueueDescriptor_s + * \brief This structure is used to configure outbound queues + * + * This structure specifies all required attributes to configure outbound queues + */ +/*******************************************************************************/ +struct spc_outboundQueueDescriptor_s +{ + bit32 elementSizeCount; /**< Size & Count of each element (slot) in the queue) */ + /**< bit00-15 Count */ + /**< When set to 0, this queue is disabled */ + /**< bit16-29 Size */ + /**< bit30 Interrupt enable/disable */ + /**< bit31 reserved */ + bit32 upperBaseAddress; /**< Upper address bits for the queue message buffer pool */ + bit32 lowerBaseAddress; /**< Lower address bits for the queue message buffer pool */ + bit32 piUpperBaseAddress; /**< PI Upper Base Address for outbound queue */ + bit32 piLowerBaseAddress; /**< PI Lower Base Address for outbound queue */ + bit32 CIPCIBar; /**< PCI BAR for CI Offset */ + bit32 CIOffset; /**< Offset address for outbound queue CI */ + bit32 interruptVecCntDelay; /**< Delay in microseconds before the interrupt is asserted */ + /**< if the interrupt threshold has not been reached */ + /**< Number of interrupt events before the interrupt is asserted */ + /**< If set to 0, interrupts for this queue are disable */ + /**< Interrupt vector number for this queue */ + /**< Note that the interrupt type can be MSI or MSI-X */ + /**< depending on the system configuration */ + /**< bit00-15 Delay */ + /**< bit16-23 Count */ + /**< bit24-31 Vector */ + bit32 DInterruptTOPCIOffset; /**< Dynamic Interrupt Coalescing Timeout PCI Bar Offset */ +}; + +typedef struct spc_outboundQueueDescriptor_s spc_outboundQueueDescriptor_t; + +typedef struct InterruptVT_s +{ + bit32 iccict; /**< DW0 - Interrupt Colescing Control and Timer */ + bit32 iraeirad; /**< DW1 - Interrupt Reassertion Enable/Delay */ +} InterruptVT_t; + +typedef struct mpiInterruptVT_s +{ + InterruptVT_t IntVecTble[MAX_NUM_VECTOR << 1]; +} mpiInterruptVT_t; + +#define INT_VT_Coal_CNT_TO 0 +#define INT_VT_Coal_ReAssert_Enab 4 + +typedef struct phyAttrb_s +{ + bit32 phyState; + bit32 phyEventOQ; +} phyAttrb_t; + +typedef struct sasPhyAttribute_s +{ + phyAttrb_t phyAttribute[MAX_VALID_PHYS]; +}sasPhyAttribute_t; + + +#define PHY_STATE 0 +#define PHY_EVENT_OQ 4 + +/*******************************************************************************/ +/** \struct spcMSGUConfig_s + * \brief This structure is used to configure controller's message unit + * + */ +/*******************************************************************************/ +typedef struct fwMSGUConfig_s +{ + spc_configMainDescriptor_t mainConfiguration; /**< main part of Configuration Table */ + spc_GSTableDescriptor_t GeneralStatusTable; /**< MPI general status table */ + spc_inboundQueueDescriptor_t inboundQueue[IB_QUEUE_CFGSIZE]; /**< Inbound queue configuration array */ + spc_outboundQueueDescriptor_t outboundQueue[OB_QUEUE_CFGSIZE]; /**< Outbound queue configuration array */ + agsaPhyAnalogSetupTable_t phyAnalogConfig; + mpiInterruptVT_t interruptVTable; + sasPhyAttribute_t phyAttributeTable; +}fwMSGUConfig_t; + + +typedef void (*EnadDisabHandler_t)( + agsaRoot_t *agRoot, + bit32 interruptVectorIndex + ); + +typedef bit32 (*InterruptOurs_t)( + agsaRoot_t *agRoot, + bit32 interruptVectorIndex + ); +#endif /* __SPC_DEFS__ */ diff --git a/sys/dev/pms/RefTisa/sat/api/sm.h b/sys/dev/pms/RefTisa/sat/api/sm.h new file mode 100644 index 000000000000..e6f8f21623ed --- /dev/null +++ b/sys/dev/pms/RefTisa/sat/api/sm.h @@ -0,0 +1,292 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/******************************************************************************** +** +* sm.h +* +* Abstract: This module defines the contants, enum and #define definition used +* by SAT Moduled (SM). +* +********************************************************************************/ + +#ifndef SM_H +#define SM_H + +/************************************************* + * constants for type field in smMem_t + *************************************************/ +#define SM_CACHED_MEM 0x00 /**< CACHED memory type */ +#define SM_DMA_MEM 0x01 /**< DMA memory type */ +#define SM_CACHED_DMA_MEM 0x02 /**< CACHED DMA memory type */ + +/************************************************* + * constants for API return values + *************************************************/ +typedef enum +{ + SM_RC_SUCCESS, + SM_RC_FAILURE, + SM_RC_BUSY, + SM_RC_NODEVICE, + SM_RC_VERSION_INCOMPATIBLE, + SM_RC_VERSION_UNTESTED, + SM_RC_RSV1, + SM_RC_RSV2, + SM_RC_RSV3, + SM_RC_RSV4, + SM_RC_DEVICE_BUSY, /* must be the same as tiDeviceBusy */ + +} smStatus_t; + +typedef enum +{ + smIOSuccess, + smIOOverRun, + smIOUnderRun, + smIOFailed, + smIODifError, + smIOEncryptError, + smIORetry, /* open retry timeout */ + smIOSTPResourceBusy, /* stp resource busy */ +} smIOStatus_t; + +typedef enum +{ + smDetailBusy, + smDetailNotValid, + smDetailNoLogin, + smDetailAbortLogin, + smDetailAbortReset, + smDetailAborted, + smDetailDifMismatch, + smDetailDifAppTagMismatch, + smDetailDifRefTagMismatch, + smDetailDifCrcMismatch, + smDetailDekKeyCacheMiss, + smDetailCipherModeInvalid, + smDetailDekIVMismatch, + smDetailDekRamInterfaceError, + smDetailDekIndexOutofBounds, + smDetailOtherError +} smIOStatusDetail_t; + +/* + * Data direction for I/O request + */ +typedef enum +{ + smDirectionIn = 0x0000, + smDirectionOut = 0x0001 +}smDataDirection_t; + +/* + * Event types for tdsmEventCB() + * do not change: Needs to be in sync with TISA API + */ +typedef enum +{ + smIntrEventTypeCnxError, + smIntrEventTypeDiscovery, + smIntrEventTypeTransportRecovery, + smIntrEventTypeTaskManagement, + smIntrEventTypeDeviceChange, + smIntrEventTypeLogin, + smIntrEventTypeLocalAbort +} smIntrEventType_t; + +typedef enum +{ + smTMOK, + smTMFailed +} smTMEventStatus_t; + +/* + * Flags in smSuperScsiInitiatorRequest_t + */ +#define SM_SCSI_INITIATOR_DIF 0x00000001 +#define SM_SCSI_INITIATOR_ENCRYPT 0x00000002 + +/* + * Flags in smSuperScsiInitiatorRequest_t + */ +#define SM_SCSI_TARGET_DIF 0x00000001 +#define SM_SCSI_TARGET_MIRROR 0x00000002 +#define SM_SCSI_TARGET_ENCRYPT 0x00000004 + +typedef struct { + void *tdData; + void *smData; +} smContext_t; + + +typedef smContext_t smDeviceHandle_t; + +typedef smContext_t smIORequest_t; + +typedef smContext_t smRoot_t; + +typedef struct +{ + bit8 lun[8]; /* logical unit number */ +} smLUN_t; + +typedef struct{ + smLUN_t lun; + bit32 expDataLength; + bit32 taskAttribute; + bit32 crn; + bit8 cdb[16]; +} smIniScsiCmnd_t; + + + +typedef struct{ + void *virtPtr; + void *osHandle; + bit32 physAddrUpper; + bit32 physAddrLower; + bit32 totalLength; + bit32 numElements; + bit32 singleElementLength; + bit32 alignment; + bit32 type; + bit32 reserved; +} smMem_t; + +#define SM_NUM_MEM_CHUNKS 8 + +typedef struct{ + bit32 count; + smMem_t smMemory[SM_NUM_MEM_CHUNKS]; +} smMemoryRequirement_t; + +typedef struct{ + bit32 lower; + bit32 upper; + bit32 len; + bit32 type; +} smSgl_t; + +/* + * DIF operation + */ +#define DIF_INSERT 0 +#define DIF_VERIFY_FORWARD 1 +#define DIF_VERIFY_DELETE 2 +#define DIF_VERIFY_REPLACE 3 +#define DIF_VERIFY_UDT_REPLACE_CRC 5 +#define DIF_REPLACE_UDT_REPLACE_CRC 7 + +#define DIF_UDT_SIZE 6 + +typedef struct smDif +{ + agBOOLEAN enableDIFPerLA; + bit32 flag; + bit16 initialIOSeed; + bit16 reserved; + bit32 DIFPerLAAddrLo; + bit32 DIFPerLAAddrHi; + bit16 DIFPerLARegion0SecCount; + bit16 DIFPerLANumOfRegions; + bit8 udtArray[DIF_UDT_SIZE]; + bit8 udrtArray[DIF_UDT_SIZE]; +} smDif_t; + +typedef struct smEncryptDek { + bit32 dekTable; + bit32 dekIndex; +} smEncryptDek_t; + +typedef struct smEncrypt { + smEncryptDek_t dekInfo; + bit32 kekIndex; + agBOOLEAN keyTagCheck; + agBOOLEAN enableEncryptionPerLA; + bit32 sectorSizeIndex; + bit32 encryptMode; + bit32 keyTag_W0; + bit32 keyTag_W1; + bit32 tweakVal_W0; + bit32 tweakVal_W1; + bit32 tweakVal_W2; + bit32 tweakVal_W3; + bit32 EncryptionPerLAAddrLo; + bit32 EncryptionPerLAAddrHi; + bit16 EncryptionPerLRegion0SecCount; + bit16 reserved; +} smEncrypt_t; + +typedef struct smScsiInitiatorRequest { + void *sglVirtualAddr; + smIniScsiCmnd_t scsiCmnd; + smSgl_t smSgl1; + smDataDirection_t dataDirection; +} smScsiInitiatorRequest_t; + +typedef struct smSuperScsiInitiatorRequest +{ + void *sglVirtualAddr; + smIniScsiCmnd_t scsiCmnd; + smSgl_t smSgl1; + smDataDirection_t dataDirection; + bit32 flags; /* + bit 0-1: reserved + bit 2: enable encryption + bit 3: enable dif + bit 4-7: reserved + bit 8-23: DIF SKIP Bytes + bit 24-31: Reserved + */ + smDif_t Dif; + smEncrypt_t Encrypt; +} smSuperScsiInitiatorRequest_t; + +typedef struct{ + void *senseData; + bit8 senseLen; +} smSenseData_t; + +typedef struct{ + bit32 maxActiveIOs; + bit32 numDevHandles; +#ifdef SM_DEBUG + bit32 SMDebugLevel; +#endif +} smSwConfig_t; + + +#define smBOOLEAN bit32 + + + + + + + + + + +#endif /* SM_H */ + diff --git a/sys/dev/pms/RefTisa/sat/api/smapi.h b/sys/dev/pms/RefTisa/sat/api/smapi.h new file mode 100644 index 000000000000..7e754ffcb754 --- /dev/null +++ b/sys/dev/pms/RefTisa/sat/api/smapi.h @@ -0,0 +1,122 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/******************************************************************************** +* smapi.h +* +* Abstract: This module contains function prototype of the SAT +* Module (SM) API for initiator. +*******************************************************************************/ + +#ifndef SMAPI_H +#define SMAPI_H + +#include +#include + +osGLOBAL bit32 +smRegisterDevice( + smRoot_t *smRoot, + agsaDevHandle_t *agDevHandle, + smDeviceHandle_t *smDeviceHandle, + agsaDevHandle_t *agExpDevHandle, + bit32 phyID, + bit32 DeviceType + ); + +osGLOBAL bit32 +smDeregisterDevice( + smRoot_t *smRoot, + agsaDevHandle_t *agDevHandle, + smDeviceHandle_t *smDeviceHandle + ); + +osGLOBAL void +smGetRequirements( + smRoot_t *smRoot, + smSwConfig_t *swConfig, + smMemoryRequirement_t *memoryRequirement, + bit32 *usecsPerTick, + bit32 *maxNumLocks + ); + +osGLOBAL bit32 +smIDStart( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle + ); + +osGLOBAL bit32 +smInitialize( + smRoot_t *smRoot, + agsaRoot_t *agRoot, + smMemoryRequirement_t *memoryAllocated, + smSwConfig_t *swConfig, + bit32 usecsPerTick + ); + +osGLOBAL bit32 +smIOAbort( + smRoot_t *smRoot, + smIORequest_t *tasktag + ); + +osGLOBAL bit32 +smIOAbortAll( + smRoot_t *smRoot, + smDeviceHandle_t *smDeviceHandle + ); + +osGLOBAL FORCEINLINE bit32 +smIOStart( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smSCSIRequest, + bit32 interruptContext + ); + +osGLOBAL bit32 +smSuperIOStart( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smSuperScsiInitiatorRequest_t *smSCSIRequest, + bit32 AddrHi, + bit32 AddrLo, + bit32 interruptContext + ); + +osGLOBAL bit32 +smTaskManagement( + smRoot_t *smRoot, + smDeviceHandle_t *smDeviceHandle, + bit32 task, + smLUN_t *lun, + smIORequest_t *taskTag, + smIORequest_t *currentTaskTag + ); + +#endif /* SMAPI_H */ + diff --git a/sys/dev/pms/RefTisa/sat/api/tdsmapi.h b/sys/dev/pms/RefTisa/sat/api/tdsmapi.h new file mode 100644 index 000000000000..7cead29be056 --- /dev/null +++ b/sys/dev/pms/RefTisa/sat/api/tdsmapi.h @@ -0,0 +1,211 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/******************************************************************************** +* tmsmapi.h +* +* Abstract: This module contains function prototype of the SAT +* Module (SM) API callback for initiator. +*******************************************************************************/ + +#ifndef TDSMAPI_H +#define TDSMAPI_H + +osGLOBAL void +tdsmIDCompletedCB( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + bit32 status, + void *IDdata + ); + +osGLOBAL FORCEINLINE void +tdsmIOCompletedCB( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + bit32 status, + bit32 statusDetail, + smSenseData_t *senseData, + bit32 interruptContext + ); +osGLOBAL void +tdsmEventCB( + smRoot_t *smRoot, + smDeviceHandle_t *smDeviceHandle, + smIntrEventType_t eventType, + bit32 eventStatus, + void *parm + ); + +osGLOBAL FORCEINLINE void +tdsmSingleThreadedEnter( + smRoot_t *smRoot, + bit32 syncLockId + ); + +osGLOBAL FORCEINLINE void +tdsmSingleThreadedLeave( + smRoot_t *smRoot, + bit32 syncLockId + ); + +osGLOBAL FORCEINLINE bit8 +tdsmBitScanForward( + smRoot_t *smRoot, + bit32 *Index, + bit32 Mask + ); + +#ifdef LINUX_VERSION_CODE + +osGLOBAL FORCEINLINE sbit32 +tdsmInterlockedIncrement( + smRoot_t *smRoot, + sbit32 volatile *Addend + ); + +osGLOBAL FORCEINLINE sbit32 +tdsmInterlockedDecrement( + smRoot_t *smRoot, + sbit32 volatile *Addend + ); + +osGLOBAL FORCEINLINE sbit32 +tdsmAtomicBitClear( + smRoot_t *smRoot, + sbit32 volatile *Destination, + sbit32 Value + ); + +osGLOBAL FORCEINLINE sbit32 +tdsmAtomicBitSet( + smRoot_t *smRoot, + sbit32 volatile *Destination, + sbit32 Value + ); + +osGLOBAL FORCEINLINE sbit32 +tdsmAtomicExchange( + smRoot_t *smRoot, + sbit32 volatile *Target, + sbit32 Value + ); +#else + +osGLOBAL FORCEINLINE sbit32 +tdsmInterlockedIncrement( + smRoot_t *smRoot, + sbit32 volatile *Addend + ); + +osGLOBAL FORCEINLINE sbit32 +tdsmInterlockedDecrement( + smRoot_t *smRoot, + sbit32 volatile *Addend + ); + +osGLOBAL FORCEINLINE sbit32 +tdsmInterlockedAnd( + smRoot_t *smRoot, + sbit32 volatile *Destination, + sbit32 Value + ); + +osGLOBAL FORCEINLINE sbit32 +tdsmInterlockedOr( + smRoot_t *smRoot, + sbit32 volatile *Destination, + sbit32 Value + ); + +osGLOBAL FORCEINLINE sbit32 +tdsmInterlockedExchange( + smRoot_t *smRoot, + sbit32 volatile *Target, + sbit32 Value + ); + +#endif /*LINUX_VERSION_CODE*/ + +osGLOBAL bit32 +tdsmAllocMemory( + smRoot_t *smRoot, + void **osMemHandle, + void ** virtPtr, + bit32 * physAddrUpper, + bit32 * physAddrLower, + bit32 alignment, + bit32 allocLength, + smBOOLEAN isCacheable + ); + +osGLOBAL bit32 +tdsmFreeMemory( + smRoot_t *smRoot, + void *osDMAHandle, + bit32 allocLength + ); + +osGLOBAL FORCEINLINE bit32 +tdsmRotateQnumber(smRoot_t *smRoot, + smDeviceHandle_t *smDeviceHandle + ); + +osGLOBAL bit32 +tdsmSetDeviceQueueDepth(smRoot_t *smRoot, + smIORequest_t *smIORequest, + bit32 QueueDepth + ); + + +#ifndef tdsmLogDebugString +GLOBAL void tdsmLogDebugString( + smRoot_t *smRoot, + bit32 level, + char *string, + void *ptr1, + void *ptr2, + bit32 value1, + bit32 value2 + ); +#endif + + + +osGLOBAL bit32 tdsmGetTransportParam( + smRoot_t *smRoot, + char *key, + char *subkey1, + char *subkey2, + char *subkey3, + char *subkey4, + char *subkey5, + char *valueName, + char *buffer, + bit32 bufferLen, + bit32 *lenReceived + ); + +#endif /* TDSMAPI_H */ + diff --git a/sys/dev/pms/RefTisa/sat/src/smdefs.h b/sys/dev/pms/RefTisa/sat/src/smdefs.h new file mode 100644 index 000000000000..2e69ffcec9f0 --- /dev/null +++ b/sys/dev/pms/RefTisa/sat/src/smdefs.h @@ -0,0 +1,851 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +#ifndef __SMDEFS_H__ +#define __SMDEFS_H__ + +#include + +/* the index for memory requirement, must be continious */ +#define SM_ROOT_MEM_INDEX 0 /**< the index of dm root memory */ +#define SM_DEVICE_MEM_INDEX 1 /**< the index of Device descriptors memory */ +#define SM_IO_MEM_INDEX 2 /**< the index of IO command descriptors memory */ + + +#define SM_MAX_DEV 256 +#define SM_MAX_IO 1024 + +#define SM_USECS_PER_TICK 1000000 /**< defines the heart beat of the LL layer 10ms */ + +enum sm_locks_e +{ + SM_TIMER_LOCK = 0, + SM_DEVICE_LOCK, + SM_INTERNAL_IO_LOCK, + SM_EXTERNAL_IO_LOCK, + SM_NCQ_TAG_LOCK, + SM_TBD_LOCK, + SM_MAX_LOCKS +}; + +/* ATA device type */ +#define SATA_ATA_DEVICE 0x01 /**< ATA ATA device type */ +#define SATA_ATAPI_DEVICE 0x02 /**< ATA ATAPI device type */ +#define SATA_PM_DEVICE 0x03 /**< ATA PM device type */ +#define SATA_SEMB_DEVICE 0x04 /**< ATA SEMB device type */ +#define SATA_SEMB_WO_SEP_DEVICE 0x05 /**< ATA SEMB without SEP device type */ +#define UNKNOWN_DEVICE 0xFF + +/* + * FIS type + */ +#define PIO_SETUP_DEV_TO_HOST_FIS 0x5F +#define REG_DEV_TO_HOST_FIS 0x34 +#define SET_DEV_BITS_FIS 0xA1 + +/* + * ATA Command code + */ +#define SAT_READ_FPDMA_QUEUED 0x60 +#define SAT_READ_DMA_EXT 0x25 +#define SAT_READ_DMA 0xC8 +#define SAT_WRITE_FPDMA_QUEUED 0x61 +#define SAT_WRITE_DMA_EXT 0x35 +#define SAT_WRITE_DMA_FUA_EXT 0x3D +#define SAT_WRITE_DMA 0xCA +#define SAT_CHECK_POWER_MODE 0xE5 +#define SAT_READ_LOG_EXT 0x2F +#define SAT_READ_VERIFY_SECTORS 0x40 +#define SAT_READ_VERIFY_SECTORS_EXT 0x42 +#define SAT_SMART 0xB0 +#define SAT_SMART_EXEUTE_OFF_LINE_IMMEDIATE 0xD4 +#define SAT_SMART_RETURN_STATUS 0xDA +#define SAT_SMART_READ_LOG 0xD5 +#define SAT_SMART_ENABLE_OPERATIONS 0xD8 +#define SAT_SMART_DISABLE_OPERATIONS 0xD9 +#define SAT_FLUSH_CACHE 0xE7 +#define SAT_FLUSH_CACHE_EXT 0xEA +#define SAT_STANDBY 0xE2 +#define SAT_MEDIA_EJECT 0xED +#define SAT_WRITE_SECTORS 0x30 +#define SAT_WRITE_SECTORS_EXT 0x34 +#define SAT_READ_SECTORS 0x20 +#define SAT_READ_SECTORS_EXT 0x24 +#define SAT_GET_MEDIA_STATUS 0xDA +#define SAT_SET_FEATURES 0xEF +#define SAT_IDENTIFY_DEVICE 0xEC +#define SAT_READ_BUFFER 0xE4 +#define SAT_WRITE_BUFFER 0xE8 + +/* + * ATAPI Command code +*/ +#define SAT_IDENTIFY_PACKET_DEVICE 0xA1 +#define SAT_PACKET 0xA0 +#define SAT_DEVICE_RESET 0x08 +#define SAT_EXECUTE_DEVICE_DIAGNOSTIC 0x90 + + +/* + * ATA Status Register Mask + */ +#define ERR_ATA_STATUS_MASK 0x01 /* Error/check bit */ +#define DRQ_ATA_STATUS_MASK 0x08 /* Data Request bit */ +#define DF_ATA_STATUS_MASK 0x20 /* Device Fault bit */ +#define DRDY_ATA_STATUS_MASK 0x40 /* Device Ready bit */ +#define BSY_ATA_STATUS_MASK 0x80 /* Busy bit */ + +/* + * ATA Error Register Mask + */ +#define NM_ATA_ERROR_MASK 0x02 /* No media present bit */ +#define ABRT_ATA_ERROR_MASK 0x04 /* Command aborted bit */ +#define MCR_ATA_ERROR_MASK 0x08 /* Media change request bit */ +#define IDNF_ATA_ERROR_MASK 0x10 /* Address not found bit */ +#define MC_ATA_ERROR_MASK 0x20 /* Media has changed bit */ +#define UNC_ATA_ERROR_MASK 0x40 /* Uncorrectable data error bit */ +#define ICRC_ATA_ERROR_MASK 0x80 /* Interface CRC error bit */ + + + + +/* + * transfer length and LBA limit 2^28 See identify device data word 61:60 + * ATA spec p125 + * 7 zeros + */ +#define SAT_TR_LBA_LIMIT 0x10000000 + +/* + * transfer length and LBA limit 2^48 See identify device data word 61:60 + * ATA spec p125 + * 12 zeros + */ +#define SAT_EXT_TR_LBA_LIMIT 0x1000000000000 + + +/* + * ATA command type. This is for setting LBA, Sector Count + */ +#define SAT_NON_EXT_TYPE 0 +#define SAT_EXT_TYPE 1 +#define SAT_FP_TYPE 2 + + +/* + * Report LUNs response data. + */ +typedef struct smScsiReportLun_s +{ + bit8 len[4]; + bit32 reserved; + tiLUN_t lunList[1]; +} smScsiReportLun_t; + +/* Inquiry vendor string */ +#define AG_SAT_VENDOR_ID_STRING "ATA " + +/* + * Simple form of SATA Identify Device Data, similar definition is defined by + * LL Layer as agsaSATAIdentifyData_t. + */ +typedef struct satSimpleSATAIdentifyData_s +{ + bit16 word[256]; +} satSimpleSATAIdentifyData_t; + + +/* + * READ LOG EXT page 10h + */ +typedef struct satReadLogExtPage10h_s +{ + bit8 byte[512]; +} satReadLogExtPage10h_t; + +/* + * READ LOG EXT Extended Self-test log + * ATA Table27 p196 + */ +typedef struct satReadLogExtSelfTest_s +{ + bit8 byte[512]; +} satReadLogExtSelfTest_t; + +/* + * SMART READ LOG Self-test log + * ATA Table60 p296 + */ +typedef struct satSmartReadLogSelfTest_s +{ + bit8 byte[512]; +} satSmartReadLogSelfTest_t; + + +/* + * Flag definition for satIntFlag field in smSatInternalIo_t. + */ + +/* Original NCQ I/O already completed, so at the completion of READ LOG EXT + * page 10h, ignore the TAG tranaltion to get the failed I/O + */ +#define AG_SAT_INT_IO_FLAG_ORG_IO_COMPLETED 0x00000001 + +#define INQUIRY_SUPPORTED_VPD_PAGE 0x00 +#define INQUIRY_UNIT_SERIAL_NUMBER_VPD_PAGE 0x80 +#define INQUIRY_DEVICE_IDENTIFICATION_VPD_PAGE 0x83 +#define INQUIRY_ATA_INFORMATION_VPD_PAGE 0x89 +#define INQUIRY_BLOCK_DEVICE_CHARACTERISTICS_VPD_PAGE 0xB1 + +#define MODESENSE_CONTROL_PAGE 0x0A +#define MODESENSE_READ_WRITE_ERROR_RECOVERY_PAGE 0x01 +#define MODESENSE_CACHING 0x08 +#define MODESENSE_INFORMATION_EXCEPTION_CONTROL_PAGE 0x1C +#define MODESENSE_RETURN_ALL_PAGES 0x3F +#define MODESENSE_VENDOR_SPECIFIC_PAGE 0x00 + +#define MODESELECT_CONTROL_PAGE 0x0A +#define MODESELECT_READ_WRITE_ERROR_RECOVERY_PAGE 0x01 +#define MODESELECT_CACHING 0x08 +#define MODESELECT_INFORMATION_EXCEPTION_CONTROL_PAGE 0x1C +#define MODESELECT_RETURN_ALL_PAGES 0x3F +#define MODESELECT_VENDOR_SPECIFIC_PAGE 0x00 + +#define LOGSENSE_SUPPORTED_LOG_PAGES 0x00 +#define LOGSENSE_SELFTEST_RESULTS_PAGE 0x10 +#define LOGSENSE_INFORMATION_EXCEPTIONS_PAGE 0x2F + + +/* + * Bit mask definition + */ +#define SCSI_EVPD_MASK 0x01 +#define SCSI_IMMED_MASK 0x01 +#define SCSI_NACA_MASK 0x04 +#define SCSI_LINK_MASK 0x01 +#define SCSI_PF_MASK 0x10 +#define SCSI_DEVOFFL_MASK 0x02 +#define SCSI_UNITOFFL_MASK 0x01 +#define SCSI_START_MASK 0x01 +#define SCSI_LOEJ_MASK 0x02 +#define SCSI_NM_MASK 0x02 +#define SCSI_FLUSH_CACHE_IMMED_MASK 0x02 +#define SCSI_FUA_NV_MASK 0x02 +#define SCSI_VERIFY_BYTCHK_MASK 0x02 +#define SCSI_FORMAT_UNIT_IMMED_MASK 0x02 +#define SCSI_FORMAT_UNIT_FOV_MASK 0x80 +#define SCSI_FORMAT_UNIT_DCRT_MASK 0x20 +#define SCSI_FORMAT_UNIT_IP_MASK 0x08 +#define SCSI_WRITE_SAME_LBDATA_MASK 0x02 +#define SCSI_WRITE_SAME_PBDATA_MASK 0x04 +#define SCSI_SYNC_CACHE_IMMED_MASK 0x02 +#define SCSI_WRITE_N_VERIFY_BYTCHK_MASK 0x02 +#define SCSI_SEND_DIAGNOSTIC_SELFTEST_MASK 0x04 +#define SCSI_FORMAT_UNIT_DEFECT_LIST_FORMAT_MASK 0x07 +#define SCSI_FORMAT_UNIT_FMTDATA_MASK 0x10 +#define SCSI_FORMAT_UNIT_DCRT_MASK 0x20 +#define SCSI_FORMAT_UNIT_CMPLIST_MASK 0x08 +#define SCSI_FORMAT_UNIT_LONGLIST_MASK 0x20 +#define SCSI_READ10_FUA_MASK 0x08 +#define SCSI_READ12_FUA_MASK 0x08 +#define SCSI_READ16_FUA_MASK 0x08 +#define SCSI_WRITE10_FUA_MASK 0x08 +#define SCSI_WRITE12_FUA_MASK 0x08 +#define SCSI_WRITE16_FUA_MASK 0x08 +#define SCSI_READ_CAPACITY10_PMI_MASK 0x01 +#define SCSI_READ_CAPACITY16_PMI_MASK 0x01 +#define SCSI_MODE_SENSE6_PC_MASK 0xC0 +#define SCSI_MODE_SENSE6_PAGE_CODE_MASK 0x3F +#define SCSI_MODE_SENSE10_PC_MASK 0xC0 +#define SCSI_MODE_SENSE10_LLBAA_MASK 0x10 +#define SCSI_MODE_SENSE10_PAGE_CODE_MASK 0x3F +#define SCSI_SEND_DIAGNOSTIC_TEST_CODE_MASK 0xE0 +#define SCSI_LOG_SENSE_PAGE_CODE_MASK 0x3F +#define SCSI_MODE_SELECT6_PF_MASK 0x10 +#define SCSI_MODE_SELECT6_AWRE_MASK 0x80 +#define SCSI_MODE_SELECT6_RC_MASK 0x10 +#define SCSI_MODE_SELECT6_EER_MASK 0x08 +#define SCSI_MODE_SELECT6_PER_MASK 0x04 +#define SCSI_MODE_SELECT6_DTE_MASK 0x02 +#define SCSI_MODE_SELECT6_DCR_MASK 0x01 +#define SCSI_MODE_SELECT6_WCE_MASK 0x04 +#define SCSI_MODE_SELECT6_DRA_MASK 0x20 +#define SCSI_MODE_SELECT6_PERF_MASK 0x80 +#define SCSI_MODE_SELECT6_TEST_MASK 0x04 +#define SCSI_MODE_SELECT6_DEXCPT_MASK 0x08 +#define SCSI_MODE_SELECT10_PF_MASK 0x10 +#define SCSI_MODE_SELECT10_LONGLBA_MASK 0x01 +#define SCSI_MODE_SELECT10_AWRE_MASK 0x80 +#define SCSI_MODE_SELECT10_RC_MASK 0x10 +#define SCSI_MODE_SELECT10_EER_MASK 0x08 +#define SCSI_MODE_SELECT10_PER_MASK 0x04 +#define SCSI_MODE_SELECT10_DTE_MASK 0x02 +#define SCSI_MODE_SELECT10_DCR_MASK 0x01 +#define SCSI_MODE_SELECT10_WCE_MASK 0x04 +#define SCSI_MODE_SELECT10_DRA_MASK 0x20 +#define SCSI_MODE_SELECT10_PERF_MASK 0x80 +#define SCSI_MODE_SELECT10_TEST_MASK 0x04 +#define SCSI_MODE_SELECT10_DEXCPT_MASK 0x08 +#define SCSI_WRITE_N_VERIFY10_FUA_MASK 0x08 +#define SCSI_REQUEST_SENSE_DESC_MASK 0x01 +#define SCSI_READ_BUFFER_MODE_MASK 0x1F + +#define ATA_REMOVABLE_MEDIA_DEVICE_MASK 0x80 +#define SCSI_REASSIGN_BLOCKS_LONGLIST_MASK 0x01 +#define SCSI_REASSIGN_BLOCKS_LONGLBA_MASK 0x02 + + +#define SENSE_DATA_LENGTH 0x12 /* 18 */ +#define SELFTEST_RESULTS_LOG_PAGE_LENGTH 404 +#define INFORMATION_EXCEPTIONS_LOG_PAGE_LENGTH 11 +#define ZERO_MEDIA_SERIAL_NUMBER_LENGTH 8 + +#define LOG_SENSE_0 0 +#define LOG_SENSE_1 1 +#define LOG_SENSE_2 2 + +#define READ_BUFFER_DATA_MODE 0x02 +#define READ_BUFFER_DESCRIPTOR_MODE 0x03 +#define READ_BUFFER_DESCRIPTOR_MODE_DATA_LEN 0x04 + +#define WRITE_BUFFER_DATA_MODE 0x02 +#define WRITE_BUFFER_DL_MICROCODE_SAVE_MODE 0x05 + +/* bit mask */ +#define BIT0_MASK 0x01 +#define BIT1_MASK 0x02 +#define BIT2_MASK 0x04 +#define BIT3_MASK 0x08 +#define BIT4_MASK 0x10 +#define BIT5_MASK 0x20 +#define BIT6_MASK 0x40 +#define BIT7_MASK 0x80 + +#define MODE_SENSE6_RETURN_ALL_PAGES_LEN 68 +#define MODE_SENSE6_CONTROL_PAGE_LEN 24 +#define MODE_SENSE6_READ_WRITE_ERROR_RECOVERY_PAGE_LEN 24 +#define MODE_SENSE6_CACHING_LEN 32 +#define MODE_SENSE6_INFORMATION_EXCEPTION_CONTROL_PAGE_LEN 24 + + +#define MODE_SENSE10_RETURN_ALL_PAGES_LEN 68 + 4 +#define MODE_SENSE10_CONTROL_PAGE_LEN 24 + 4 +#define MODE_SENSE10_READ_WRITE_ERROR_RECOVERY_PAGE_LEN 24 + 4 +#define MODE_SENSE10_CACHING_LEN 32 + 4 +#define MODE_SENSE10_INFORMATION_EXCEPTION_CONTROL_PAGE_LEN 24 + 4 + +#define MODE_SENSE10_RETURN_ALL_PAGES_LLBAA_LEN 68 + 4 + 8 +#define MODE_SENSE10_CONTROL_PAGE_LLBAA_LEN 24 + 4 + 8 +#define MODE_SENSE10_READ_WRITE_ERROR_RECOVERY_PAGE_LLBAA_LEN 24 + 4 + 8 +#define MODE_SENSE10_CACHING_LLBAA_LEN 32 + 4 + 8 +#define MODE_SENSE10_INFORMATION_EXCEPTION_CONTROL_PAGE_LLBAA_LEN 24 + 4 + 8 + +/***************************************************************************** +** SCSI SENSE KEY VALUES +*****************************************************************************/ + +#define SCSI_SNSKEY_NO_SENSE 0x00 +#define SCSI_SNSKEY_RECOVERED_ERROR 0x01 +#define SCSI_SNSKEY_NOT_READY 0x02 +#define SCSI_SNSKEY_MEDIUM_ERROR 0x03 +#define SCSI_SNSKEY_HARDWARE_ERROR 0x04 +#define SCSI_SNSKEY_ILLEGAL_REQUEST 0x05 +#define SCSI_SNSKEY_UNIT_ATTENTION 0x06 +#define SCSI_SNSKEY_DATA_PROTECT 0x07 +#define SCSI_SNSKEY_ABORTED_COMMAND 0x0B +#define SCSI_SNSKEY_MISCOMPARE 0x0E + +/***************************************************************************** +** SCSI Additional Sense Codes and Qualifiers combo two-bytes +*****************************************************************************/ + +#define SCSI_SNSCODE_NO_ADDITIONAL_INFO 0x0000 +#define SCSI_SNSCODE_LUN_CRC_ERROR_DETECTED 0x0803 +#define SCSI_SNSCODE_INVALID_COMMAND 0x2000 +#define SCSI_SNSCODE_LOGICAL_BLOCK_OUT 0x2100 +#define SCSI_SNSCODE_INVALID_FIELD_IN_CDB 0x2400 +#define SCSI_SNSCODE_LOGICAL_NOT_SUPPORTED 0x2500 +#define SCSI_SNSCODE_POWERON_RESET 0x2900 +#define SCSI_SNSCODE_EVERLAPPED_CMDS 0x4e00 +#define SCSI_SNSCODE_INTERNAL_TARGET_FAILURE 0x4400 +#define SCSI_SNSCODE_MEDIUM_NOT_PRESENT 0x3a00 +#define SCSI_SNSCODE_UNRECOVERED_READ_ERROR 0x1100 +#define SCSI_SNSCODE_RECORD_NOT_FOUND 0x1401 +#define SCSI_SNSCODE_NOT_READY_TO_READY_CHANGE 0x2800 +#define SCSI_SNSCODE_OPERATOR_MEDIUM_REMOVAL_REQUEST 0x5a01 +#define SCSI_SNSCODE_INFORMATION_UNIT_CRC_ERROR 0x4703 +#define SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_FORMAT_IN_PROGRESS 0x0404 +#define SCSI_SNSCODE_HARDWARE_IMPENDING_FAILURE 0x5d10 +#define SCSI_SNSCODE_LOW_POWER_CONDITION_ON 0x5e00 +#define SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_INIT_REQUIRED 0x0402 +#define SCSI_SNSCODE_INVALID_FIELD_PARAMETER_LIST 0x2600 +#define SCSI_SNSCODE_ATA_DEVICE_FAILED_SET_FEATURES 0x4471 +#define SCSI_SNSCODE_ATA_DEVICE_FEATURE_NOT_ENABLED 0x670B +#define SCSI_SNSCODE_LOGICAL_UNIT_FAILED_SELF_TEST 0x3E03 +#define SCSI_SNSCODE_COMMAND_SEQUENCE_ERROR 0x2C00 +#define SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE 0x2100 +#define SCSI_SNSCODE_LOGICAL_UNIT_FAILURE 0x3E01 +#define SCSI_SNSCODE_MEDIA_LOAD_OR_EJECT_FAILED 0x5300 +#define SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_INITIALIZING_COMMAND_REQUIRED 0x0402 +#define SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_CAUSE_NOT_REPORTABLE 0x0400 +#define SCSI_SNSCODE_LOGICAL_UNIT_DOES_NOT_RESPOND_TO_SELECTION 0x0500 +#define SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN 0x4000 +#define SCSI_SNSCODE_COMMANDS_CLEARED_BY_ANOTHER_INITIATOR 0x2F00 +#define SCSI_SNSCODE_WRITE_ERROR_AUTO_REALLOCATION_FAILED 0x0C02 +#define SCSI_SNSCODE_ATA_PASS_THROUGH_INFORMATION_AVAILABLE 0x001D + +/***************************************************************************** +** SCSI Additional Sense Codes and Qualifiers saparate bytes +*****************************************************************************/ + +#define SCSI_ASC_NOTREADY_INIT_CMD_REQ 0x04 +#define SCSI_ASCQ_NOTREADY_INIT_CMD_REQ 0x02 + + +/***************************************************************************** +** Inquiry command fields and response sizes +*****************************************************************************/ +#define SCSIOP_INQUIRY_CMDDT 0x02 +#define SCSIOP_INQUIRY_EVPD 0x01 +#define STANDARD_INQUIRY_SIZE 36 +#define SATA_PAGE83_INQUIRY_WWN_SIZE 16 /* SAT, revision8, Table81, p78, 12 + 4 */ +#define SATA_PAGE83_INQUIRY_NO_WWN_SIZE 76 /* SAT, revision8, Table81, p78, 72 + 4 */ +#define SATA_PAGE89_INQUIRY_SIZE 572 /* SAT, revision8, Table87, p84 */ +#define SATA_PAGE0_INQUIRY_SIZE 9 /* SPC-4, 7.6.9 Table331, p345 */ +#define SATA_PAGE80_INQUIRY_SIZE 24 /* SAT, revision8, Table79, p77 */ +#define SATA_PAGEB1_INQUIRY_SIZE 64 /* SBC-3, revision31, Table193, p273 */ + +/***************************************************************************** +** SCSI Operation Codes (first byte in CDB) +*****************************************************************************/ + + +#define SCSIOPC_TEST_UNIT_READY 0x00 +#define SCSIOPC_INQUIRY 0x12 +#define SCSIOPC_MODE_SENSE_6 0x1A +#define SCSIOPC_MODE_SENSE_10 0x5A +#define SCSIOPC_MODE_SELECT_6 0x15 +#define SCSIOPC_START_STOP_UNIT 0x1B +#define SCSIOPC_READ_CAPACITY_10 0x25 +#define SCSIOPC_READ_CAPACITY_16 0x9E +#define SCSIOPC_READ_6 0x08 +#define SCSIOPC_READ_10 0x28 +#define SCSIOPC_READ_12 0xA8 +#define SCSIOPC_READ_16 0x88 +#define SCSIOPC_WRITE_6 0x0A +#define SCSIOPC_WRITE_10 0x2A +#define SCSIOPC_WRITE_12 0xAA +#define SCSIOPC_WRITE_16 0x8A +#define SCSIOPC_WRITE_VERIFY 0x2E +#define SCSIOPC_VERIFY_10 0x2F +#define SCSIOPC_VERIFY_12 0xAF +#define SCSIOPC_VERIFY_16 0x8F +#define SCSIOPC_REQUEST_SENSE 0x03 +#define SCSIOPC_REPORT_LUN 0xA0 +#define SCSIOPC_FORMAT_UNIT 0x04 +#define SCSIOPC_SEND_DIAGNOSTIC 0x1D +#define SCSIOPC_WRITE_SAME_10 0x41 +#define SCSIOPC_WRITE_SAME_16 0x93 +#define SCSIOPC_READ_BUFFER 0x3C +#define SCSIOPC_WRITE_BUFFER 0x3B + +#define SCSIOPC_LOG_SENSE 0x4D +#define SCSIOPC_LOG_SELECT 0x4C +#define SCSIOPC_MODE_SELECT_6 0x15 +#define SCSIOPC_MODE_SELECT_10 0x55 +#define SCSIOPC_SYNCHRONIZE_CACHE_10 0x35 +#define SCSIOPC_SYNCHRONIZE_CACHE_16 0x91 +#define SCSIOPC_WRITE_AND_VERIFY_10 0x2E +#define SCSIOPC_WRITE_AND_VERIFY_12 0xAE +#define SCSIOPC_WRITE_AND_VERIFY_16 0x8E +#define SCSIOPC_READ_MEDIA_SERIAL_NUMBER 0xAB +#define SCSIOPC_REASSIGN_BLOCKS 0x07 + +#define SCSIOPC_GET_CONFIG 0x46 +#define SCSIOPC_GET_EVENT_STATUS_NOTIFICATION 0x4a +#define SCSIOPC_REPORT_KEY 0xA4 +#define SCSIOPC_SEND_KEY 0xA3 +#define SCSIOPC_READ_DVD_STRUCTURE 0xAD +#define SCSIOPC_TOC 0x43 +#define SCSIOPC_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E +#define SCSIOPC_READ_VERIFY 0x42 +#define SCSIOPC_ATA_PASS_THROUGH12 0xA1 +#define SCSIOPC_ATA_PASS_THROUGH16 0x85 + + +/*! \def MIN(a,b) +* \brief MIN macro +* +* use to find MIN of two values +*/ +#ifndef MIN +#define MIN(a,b) ((a) < (b) ? (a) : (b)) +#endif + +/*! \def MAX(a,b) +* \brief MAX macro +* +* use to find MAX of two values +*/ +#ifndef MAX +#define MAX(a,b) ((a) < (b) ? (b) : (a)) +#endif + +/* for debugging print */ +#if defined(SM_DEBUG) + +/* +* for debugging purposes. +*/ +extern bit32 gSMDebugLevel; + +#define SM_DBG0(format) tdsmLogDebugString(gSMDebugLevel, 0, format) +#define SM_DBG1(format) tdsmLogDebugString(gSMDebugLevel, 1, format) +#define SM_DBG2(format) tdsmLogDebugString(gSMDebugLevel, 2, format) +#define SM_DBG3(format) tdsmLogDebugString(gSMDebugLevel, 3, format) +#define SM_DBG4(format) tdsmLogDebugString(gSMDebugLevel, 4, format) +#define SM_DBG5(format) tdsmLogDebugString(gSMDebugLevel, 5, format) +#define SM_DBG6(format) tdsmLogDebugString(gSMDebugLevel, 6, format) + +#else + +#define SM_DBG0(format) +#define SM_DBG1(format) +#define SM_DBG2(format) +#define SM_DBG3(format) +#define SM_DBG4(format) +#define SM_DBG5(format) +#define SM_DBG6(format) + +#endif /* SM_DEBUG */ + +//#define SM_ASSERT OS_ASSERT +//#define tdsmLogDebugString TIDEBUG_MSG + +/* + * SAT specific structure per SATA drive + */ +#define SAT_NONNCQ_MAX 1 +#define SAT_NCQ_MAX 32 +#define SAT_MAX_INT_IO 16 +#define SAT_APAPI_CMDQ_MAX 2 + +/* Device state */ +#define SAT_DEV_STATE_NORMAL 0 /* Normal */ +#define SAT_DEV_STATE_IN_RECOVERY 1 /* SAT in recovery mode */ +#define SAT_DEV_STATE_FORMAT_IN_PROGRESS 2 /* Format unit in progress */ +#define SAT_DEV_STATE_SMART_THRESHOLD 3 /* SMART Threshold Exceeded Condition*/ +#define SAT_DEV_STATE_LOW_POWER 4 /* Low Power State*/ + +#ifndef agNULL +#define agNULL ((void *)0) +#endif + +#define SM_SET_ESGL_EXTEND(val) \ + ((val) = (val) | 0x80000000) + +#define SM_CLEAR_ESGL_EXTEND(val) \ + ((val) = (val) & 0x7FFFFFFF) + +#ifndef OPEN_RETRY_RETRIES +#define OPEN_RETRY_RETRIES 10 +#endif + +/********************************************************************* +* CPU buffer access macro * +* * +*/ + +#define OSSA_OFFSET_OF(STRUCT_TYPE, FEILD) \ + (bitptr)&(((STRUCT_TYPE *)0)->FEILD) + + +#if defined(SA_CPU_LITTLE_ENDIAN) + +#define OSSA_WRITE_LE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ + (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit16)(VALUE16); + +#define OSSA_WRITE_LE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ + (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit32)(VALUE32); + +#define OSSA_READ_LE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ + (*((bit16 *)ADDR16)) = (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) + +#define OSSA_READ_LE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ + (*((bit32 *)ADDR32)) = (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) + +#define OSSA_WRITE_BE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)((((bit16)VALUE16)>>8)&0xFF); \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)(((bit16)VALUE16)&0xFF); + +#define OSSA_WRITE_BE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)((((bit32)VALUE32)>>24)&0xFF); \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>8)&0xFF); \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)(((bit32)VALUE32)&0xFF); + +#define OSSA_READ_BE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ + (*(bit8 *)(((bit8 *)ADDR16)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ + (*(bit8 *)(((bit8 *)ADDR16))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); + +#define OSSA_READ_BE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ + (*(bit8 *)(((bit8 *)ADDR32)+3)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ + (*(bit8 *)(((bit8 *)ADDR32)+2)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); \ + (*(bit8 *)(((bit8 *)ADDR32)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))); \ + (*(bit8 *)(((bit8 *)ADDR32))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))); + +#define OSSA_WRITE_BYTE_STRING(AGROOT, DEST_ADDR, SRC_ADDR, LEN) \ + si_memcpy(DEST_ADDR, SRC_ADDR, LEN); + + +#elif defined(SA_CPU_BIG_ENDIAN) + +#define OSSA_WRITE_LE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit16)VALUE16)>>8)&0xFF); \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)(((bit16)VALUE16)&0xFF); + +#define OSSA_WRITE_LE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)((((bit32)VALUE32)>>24)&0xFF); \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>8)&0xFF); \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)(((bit32)VALUE32)&0xFF); + +#define OSSA_READ_LE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ + (*(bit8 *)(((bit8 *)ADDR16)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ + (*(bit8 *)(((bit8 *)ADDR16))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); + +#define OSSA_READ_LE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ + (*((bit8 *)(((bit8 *)ADDR32)+3))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ + (*((bit8 *)(((bit8 *)ADDR32)+2))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); \ + (*((bit8 *)(((bit8 *)ADDR32)+1))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))); \ + (*((bit8 *)(((bit8 *)ADDR32)))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))); + +#define OSSA_WRITE_BE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ + (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit16)(VALUE16); + +#define OSSA_WRITE_BE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ + (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit32)(VALUE32); + +#define OSSA_READ_BE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ + (*((bit16 *)ADDR16)) = (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); + +#define OSSA_READ_BE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ + (*((bit32 *)ADDR32)) = (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); + +#define OSSA_WRITE_BYTE_STRING(AGROOT, DEST_ADDR, SRC_ADDR, LEN) \ + si_memcpy(DEST_ADDR, SRC_ADDR, LEN); + +#else + +#error (Host CPU endianess undefined!!) + +#endif + + +#if defined(SA_CPU_LITTLE_ENDIAN) + +#ifndef LEBIT16_TO_BIT16 +#define LEBIT16_TO_BIT16(_x) (_x) +#endif + +#ifndef BIT16_TO_LEBIT16 +#define BIT16_TO_LEBIT16(_x) (_x) +#endif + +#ifndef BIT16_TO_BEBIT16 +#define BIT16_TO_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x) +#endif + +#ifndef BEBIT16_TO_BIT16 +#define BEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x) +#endif + +#ifndef LEBIT32_TO_BIT32 +#define LEBIT32_TO_BIT32(_x) (_x) +#endif + +#ifndef BIT32_TO_LEBIT32 +#define BIT32_TO_LEBIT32(_x) (_x) +#endif + + +#ifndef BEBIT32_TO_BIT32 +#define BEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x) +#endif + +#ifndef BIT32_TO_BEBIT32 +#define BIT32_TO_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x) +#endif + +#elif defined(SA_CPU_BIG_ENDIAN) + +#ifndef LEBIT16_TO_BIT16 +#define LEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x) +#endif + +#ifndef BIT16_TO_LEBIT16 +#define BIT16_TO_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x) +#endif + +#ifndef BIT16_TO_BEBIT16 +#define BIT16_TO_BEBIT16(_x) (_x) +#endif + +#ifndef BEBIT16_TO_BIT16 +#define BEBIT16_TO_BIT16(_x) (_x) +#endif + +#ifndef LEBIT32_TO_BIT32 +#define LEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x) +#endif + +#ifndef BIT32_TO_LEBIT32 +#define BIT32_TO_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x) +#endif + +#ifndef BEBIT32_TO_BIT32 +#define BEBIT32_TO_BIT32(_x) (_x) +#endif + +#ifndef BIT32_TO_BEBIT32 +#define BIT32_TO_BEBIT32(_x) (_x) +#endif + +#else + +#error No definition of SA_CPU_BIG_ENDIAN or SA_CPU_LITTLE_ENDIAN + +#endif + + +/* + * Task Management task used in tiINITaskManagement() + * + * 1 SM_ABORT TASK - aborts the task identified by the Referenced Task Tag field. + * 2 SM_ABORT TASK SET - aborts all Tasks issued by this initiator on the Logical Unit + * 3 SM_CLEAR ACA - clears the Auto Contingent Allegiance condition. + * 4 SM_CLEAR TASK SET - Aborts all Tasks (from all initiators) for the Logical Unit. + * 5 SM_LOGICAL UNIT RESET + * 6 SM_TARGET WARM RESET - iSCSI only + * 7 SM_TARGET_COLD_RESET - iSCSI only + * 8 SM_TASK_REASSIGN - iSCSI only + * 9 SM_QUERY_TASK - SAS only + */ + +#define SM_ABORT_TASK 1 +#define SM_ABORT_TASK_SET 2 +#define SM_CLEAR_ACA 3 +#define SM_CLEAR_TASK_SET 4 +#define SM_LOGICAL_UNIT_RESET 5 +#define SM_TARGET_WARM_RESET 6 /* iSCSI only */ +#define SM_TARGET_COLD_RESET 7 /* iSCSI only */ +#define SM_TASK_REASSIGN 8 /* iSCSI only */ +#define SM_QUERY_TASK 9 /* SAS only */ + +/* SMP PHY CONTROL OPERATION */ +#define SMP_PHY_CONTROL_NOP 0x00 +#define SMP_PHY_CONTROL_LINK_RESET 0x01 +#define SMP_PHY_CONTROL_HARD_RESET 0x02 +#define SMP_PHY_CONTROL_DISABLE 0x03 +#define SMP_PHY_CONTROL_CLEAR_ERROR_LOG 0x05 +#define SMP_PHY_CONTROL_CLEAR_AFFILIATION 0x06 +#define SMP_PHY_CONTROL_XMIT_SATA_PS_SIGNAL 0x07 + +/**************************************************************** + * Phy Control request + ****************************************************************/ +typedef struct smpReqPhyControl_s +{ + bit8 reserved1[4]; + bit8 reserved2; + bit8 phyIdentifier; + bit8 phyOperation; + bit8 updatePartialPathwayTOValue; + /* b7-1 : reserved */ + /* b0 : update partial pathway timeout value */ + bit8 reserved3[20]; + bit8 programmedMinPhysicalLinkRate; + /* b7-4 : programmed Minimum Physical Link Rate*/ + /* b3-0 : reserved */ + bit8 programmedMaxPhysicalLinkRate; + /* b7-4 : programmed Maximum Physical Link Rate*/ + /* b3-0 : reserved */ + bit8 reserved4[2]; + bit8 partialPathwayTOValue; + /* b7-4 : reserved */ + /* b3-0 : partial Pathway TO Value */ + bit8 reserved5[3]; +} smpReqPhyControl_t; + + +typedef struct smSMPFrameHeader_s +{ + bit8 smpFrameType; /* The first byte of SMP frame represents the SMP FRAME TYPE */ + bit8 smpFunction; /* The second byte of the SMP frame represents the SMP FUNCTION */ + bit8 smpFunctionResult; /* The third byte of SMP frame represents FUNCTION RESULT of the SMP response. */ + bit8 smpReserved; /* reserved */ +} smSMPFrameHeader_t; + +/* SMP direct payload size limit: IOMB direct payload size = 48 */ +#define SMP_DIRECT_PAYLOAD_LIMIT 44 + +#define SMP_REQUEST 0x40 +#define SMP_RESPONSE 0x41 + +#define SMP_PHY_CONTROL 0x91 + +/* SMP function results */ +#define SMP_FUNCTION_ACCEPTED 0x00 + +/* bit8 array[4] -> bit32 */ +#define SM_GET_SAS_ADDRESSLO(sasAddressLo) \ + DMA_BEBIT32_TO_BIT32(*(bit32 *)sasAddressLo) + +#define SM_GET_SAS_ADDRESSHI(sasAddressHi) \ + DMA_BEBIT32_TO_BIT32(*(bit32 *)sasAddressHi) + +/* SATA sector size 512 bytes = 0x200 bytes */ +#define SATA_SECTOR_SIZE 0x200 +/* TL limit in sector */ +/* for SAT_READ/WRITE_DMA and SAT_READ/WRITE_SECTORS ATA command */ +#define NON_BIT48_ADDRESS_TL_LIMIT 0x100 +/* for SAT_READ/WRITE_DMA_EXT and SAT_READ/WRITE_SECTORS_EXT and SAT_READ/WRITE_FPDMA_QUEUEDATA command */ +#define BIT48_ADDRESS_TL_LIMIT 0xFFFF + +#define VEN_DEV_SPC 0x800111f8 +#define VEN_DEV_SPCv 0x800811f8 +#define VEN_DEV_SPCve 0x800911f8 +#define VEN_DEV_SPCvplus 0x801811f8 +#define VEN_DEV_SPCveplus 0x801911f8 + +#define SMIsSPC(agr) (VEN_DEV_SPC == ossaHwRegReadConfig32(agr,0 ) ? 1 : 0) /* returns true config space read is SPC */ +#define SMIsSPCv(agr) (VEN_DEV_SPCv == ossaHwRegReadConfig32(agr,0 ) ? 1 : 0) /* returns true config space read is SPCv */ +#define SMIsSPCve(agr) (VEN_DEV_SPCve == ossaHwRegReadConfig32(agr,0 ) ? 1 : 0) /* returns true config space read is SPCve */ +#define SMIsSPCvplus(agr) (VEN_DEV_SPCvplus == ossaHwRegReadConfig32(agr,0 ) ? 1 : 0) /* returns true config space read is SPCv+ */ +#define SMIsSPCveplus(agr) (VEN_DEV_SPCveplus == ossaHwRegReadConfig32(agr,0 ) ? 1 : 0) /* returns true config space read is SPCve+ */ + +#define DEFAULT_KEY_BUFFER_SIZE 64 + + +#endif /* __SMDEFS_H__ */ + diff --git a/sys/dev/pms/RefTisa/sat/src/sminit.c b/sys/dev/pms/RefTisa/sat/src/sminit.c new file mode 100644 index 000000000000..49a2f68124df --- /dev/null +++ b/sys/dev/pms/RefTisa/sat/src/sminit.c @@ -0,0 +1,503 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#include +#include + +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#ifdef SM_DEBUG +bit32 gSMDebugLevel = 1; +#endif +smRoot_t *gsmRoot = agNULL; + +/* start smapi defined APIS */ +osGLOBAL void +smGetRequirements( + smRoot_t *smRoot, + smSwConfig_t *swConfig, + smMemoryRequirement_t *memoryRequirement, + bit32 *usecsPerTick, + bit32 *maxNumLocks + ) +{ + bit32 memoryReqCount = 0; + bit32 i; + bit32 max_dev = SM_MAX_DEV; + char *buffer; + bit32 buffLen; + bit32 lenRecv = 0; + static char tmpBuffer[DEFAULT_KEY_BUFFER_SIZE]; + char *pLastUsedChar = agNULL; + char globalStr[] = "Global"; + char iniParmsStr[] = "InitiatorParms"; + SM_DBG2(("smGetRequirements: start\n")); + + /* sanity check */ + SM_ASSERT((agNULL != swConfig), ""); + SM_ASSERT((agNULL != memoryRequirement), ""); + SM_ASSERT((agNULL != usecsPerTick), ""); + SM_ASSERT((agNULL != maxNumLocks), ""); + + /* memory requirement for smRoot, CACHE memory */ + memoryRequirement->smMemory[SM_ROOT_MEM_INDEX].singleElementLength = sizeof(smIntRoot_t); + memoryRequirement->smMemory[SM_ROOT_MEM_INDEX].numElements = 1; + memoryRequirement->smMemory[SM_ROOT_MEM_INDEX].totalLength = + (memoryRequirement->smMemory[SM_ROOT_MEM_INDEX].singleElementLength) * (memoryRequirement->smMemory[SM_ROOT_MEM_INDEX].numElements); + memoryRequirement->smMemory[SM_ROOT_MEM_INDEX].alignment = 4; + memoryRequirement->smMemory[SM_ROOT_MEM_INDEX].type = SM_CACHED_MEM; + memoryReqCount++; + + /* reading the configurable parameter of MaxTargets */ + buffer = tmpBuffer; + buffLen = sizeof(tmpBuffer); + sm_memset(buffer, 0, buffLen); + lenRecv = 0; + if ((tdsmGetTransportParam( + smRoot, + globalStr, + iniParmsStr, + agNULL, + agNULL, + agNULL, + agNULL, + "MaxTargets", + buffer, + buffLen, + &lenRecv + ) == SM_RC_SUCCESS) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + max_dev = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + max_dev = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + SM_DBG3(("smGetRequirements: max_expander %d\n", max_dev)); + /* memory requirement for Device Links, CACHE memory */ + memoryRequirement->smMemory[SM_DEVICE_MEM_INDEX].singleElementLength = sizeof(smDeviceData_t); + memoryRequirement->smMemory[SM_DEVICE_MEM_INDEX].numElements = max_dev; + memoryRequirement->smMemory[SM_DEVICE_MEM_INDEX].totalLength = + (memoryRequirement->smMemory[SM_DEVICE_MEM_INDEX].singleElementLength) * (memoryRequirement->smMemory[SM_DEVICE_MEM_INDEX].numElements); + memoryRequirement->smMemory[SM_DEVICE_MEM_INDEX].alignment = 4; + memoryRequirement->smMemory[SM_DEVICE_MEM_INDEX].type = SM_CACHED_MEM; + memoryReqCount++; + + /* memory requirement for IO inks, CACHE memory */ + memoryRequirement->smMemory[SM_IO_MEM_INDEX].singleElementLength = sizeof(smIORequestBody_t); + memoryRequirement->smMemory[SM_IO_MEM_INDEX].numElements = SM_MAX_IO; + memoryRequirement->smMemory[SM_IO_MEM_INDEX].totalLength = + (memoryRequirement->smMemory[SM_IO_MEM_INDEX].singleElementLength) * (memoryRequirement->smMemory[SM_IO_MEM_INDEX].numElements); + memoryRequirement->smMemory[SM_IO_MEM_INDEX].alignment = 4; + memoryRequirement->smMemory[SM_IO_MEM_INDEX].type = SM_CACHED_MEM; + memoryReqCount++; + + /* for debugging */ + for (i=0;i< memoryReqCount;i++) + { + SM_DBG3(("smGetRequirements: index %d numElements %d totalLength %d singleElementLength %d alignment %d\n", i + , memoryRequirement->smMemory[i].numElements, memoryRequirement->smMemory[i].totalLength, + memoryRequirement->smMemory[i].singleElementLength,memoryRequirement->smMemory[i].alignment )); + } + /* set up memory requirement count */ + memoryRequirement->count = memoryReqCount; + + /* requirement for locks */ + *maxNumLocks = SM_MAX_LOCKS; + + /* setup the time tick */ + *usecsPerTick = SM_USECS_PER_TICK; + + /* set up the number of active IOs */ + swConfig->maxActiveIOs = SM_MAX_IO; + + /* set up the number of device handles */ + swConfig->numDevHandles = SM_MAX_DEV; + + + return; +} + +osGLOBAL bit32 +smInitialize( + smRoot_t *smRoot, + agsaRoot_t *agRoot, + smMemoryRequirement_t *memoryAllocated, + smSwConfig_t *swConfig, + bit32 usecsPerTick + ) +{ + smIntRoot_t *smIntRoot; + smDeviceData_t *smDevice; + smIORequestBody_t *smIORequest; + smIntContext_t *smAllShared; + bit32 i; + bit32 max_dev = SM_MAX_DEV; + char *buffer; + bit32 buffLen; + bit32 lenRecv = 0; + static char tmpBuffer[DEFAULT_KEY_BUFFER_SIZE]; + char *pLastUsedChar = agNULL; + char globalStr[] = "Global"; + char iniParmsStr[] = "InitiatorParms"; + + SM_DBG2(("smInitialize: start\n")); + + /* sanity check */ + SM_ASSERT((agNULL != smRoot), ""); + SM_ASSERT((agNULL != agRoot), ""); + SM_ASSERT((agNULL != memoryAllocated), ""); + SM_ASSERT((agNULL != swConfig), ""); + SM_ASSERT((SM_ROOT_MEM_INDEX < memoryAllocated->count), ""); + SM_ASSERT((SM_DEVICE_MEM_INDEX < memoryAllocated->count), ""); + SM_ASSERT((SM_IO_MEM_INDEX < memoryAllocated->count), ""); + + /* Check the memory allocated */ + for ( i = 0; i < memoryAllocated->count; i ++ ) + { + /* If memory allocatation failed */ + if (memoryAllocated->smMemory[i].singleElementLength && + memoryAllocated->smMemory[i].numElements) + { + if ( (0 != memoryAllocated->smMemory[i].numElements) + && (0 == memoryAllocated->smMemory[i].totalLength) ) + { + /* return failure */ + SM_DBG1(("smInitialize: Memory[%d] singleElementLength = 0x%x numElements = 0x%x NOT allocated!!!\n", + i, + memoryAllocated->smMemory[i].singleElementLength, + memoryAllocated->smMemory[i].numElements)); + return SM_RC_FAILURE; + } + } + } + + /* for debugging */ + for ( i = 0; i < memoryAllocated->count; i ++ ) + { + SM_DBG3(("smInitialize: index %d virtPtr %p osHandle%p\n",i, memoryAllocated->smMemory[i].virtPtr, memoryAllocated->smMemory[i].osHandle)); + SM_DBG3(("smInitialize: index %d phyAddrUpper 0x%x phyAddrLower 0x%x totalLength %d numElements %d\n", i, + memoryAllocated->smMemory[i].physAddrUpper, + memoryAllocated->smMemory[i].physAddrLower, + memoryAllocated->smMemory[i].totalLength, + memoryAllocated->smMemory[i].numElements)); + SM_DBG3(("smInitialize: index %d singleElementLength 0x%x alignment 0x%x type %d reserved %d\n", i, + memoryAllocated->smMemory[i].singleElementLength, + memoryAllocated->smMemory[i].alignment, + memoryAllocated->smMemory[i].type, + memoryAllocated->smMemory[i].reserved)); + } + + /* SM's internal root */ + smIntRoot = (smIntRoot_t *) (memoryAllocated->smMemory[SM_ROOT_MEM_INDEX].virtPtr); + smRoot->smData = (void *) smIntRoot; + + smAllShared = (smIntContext_t *)&(smIntRoot->smAllShared); + /**< Initialize the TDM data part of the interrupt context */ + smAllShared->smRootOsData.smRoot = smRoot; + smAllShared->smRootOsData.smAllShared = (void *) smAllShared; + gsmRoot = smRoot; + smAllShared->FCA = agTRUE; + + /* Devices */ + smDevice = (smDeviceData_t *) (memoryAllocated->smMemory[SM_DEVICE_MEM_INDEX].virtPtr); + smAllShared->DeviceMem = (smDeviceData_t *)smDevice; + + /* IOs */ + smIORequest = (smIORequestBody_t *) (memoryAllocated->smMemory[SM_IO_MEM_INDEX].virtPtr); + smAllShared->IOMem = (smIORequestBody_t *)smIORequest; + + smAllShared->agRoot = agRoot; + + smAllShared->usecsPerTick = usecsPerTick; + + /**< initializes timers */ + smInitTimers(smRoot); + + /**< initializes devices */ + buffer = tmpBuffer; + buffLen = sizeof(tmpBuffer); + sm_memset(buffer, 0, buffLen); + lenRecv = 0; + if ((tdsmGetTransportParam( + smRoot, + globalStr, + iniParmsStr, + agNULL, + agNULL, + agNULL, + agNULL, + "MaxTargets", + buffer, + buffLen, + &lenRecv + ) == SM_RC_SUCCESS) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + max_dev = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + max_dev = osti_strtoul (buffer, &pLastUsedChar, 10); + } + SM_DBG1(("smInitialize: MaxTargets %d\n", max_dev)); + } + + smDeviceDataInit(smRoot, max_dev); + + /**< initializes IOs */ + smIOInit(smRoot); + +#ifdef SM_DEBUG + gSMDebugLevel = swConfig->SMDebugLevel; +#endif + + return SM_RC_SUCCESS; +} + +osGLOBAL void +smInitTimers( + smRoot_t *smRoot + ) +{ + smIntRoot_t *smIntRoot = (smIntRoot_t *)smRoot->smData; + smIntContext_t *smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + + SM_DBG2(("smInitTimers: start\n")); + + /* initialize the timerlist */ + SMLIST_INIT_HDR(&(smAllShared->timerlist)); + + return; +} + +osGLOBAL void +smDeviceDataReInit( + smRoot_t *smRoot, + smDeviceData_t *oneDeviceData + ) +{ + int j=0; + smSatInternalIo_t *satIntIO; + + SM_DBG2(("smDeviceDataReInit: start \n")); + + if (oneDeviceData->satPendingIO != 0) + { + SM_DBG1(("smDeviceDataReInit: did %d\n", oneDeviceData->id)); + SM_DBG1(("smDeviceDataReInit: satPendingIO %d satNCQMaxIO %d!!!\n", oneDeviceData->satPendingIO, oneDeviceData->satNCQMaxIO )); + SM_DBG1(("smDeviceDataReInit: satPendingNCQIO %d satPendingNONNCQIO %d!!!\n", oneDeviceData->satPendingNCQIO, oneDeviceData->satPendingNONNCQIO)); + } + +// oneDeviceData->smRoot = agNULL; + oneDeviceData->agDevHandle = agNULL; + oneDeviceData->valid = agFALSE; + oneDeviceData->SMAbortAll = agFALSE; + oneDeviceData->smDevHandle = agNULL; + oneDeviceData->directlyAttached = agFALSE; + oneDeviceData->agExpDevHandle = agNULL; + oneDeviceData->phyID = 0xFF; + oneDeviceData->SMNumOfFCA = 0; + + /* default */ + oneDeviceData->satDriveState = SAT_DEV_STATE_NORMAL; + oneDeviceData->satNCQMaxIO =SAT_NCQ_MAX; + oneDeviceData->satPendingIO = 0; + oneDeviceData->satPendingNCQIO = 0; + oneDeviceData->satPendingNONNCQIO = 0; + oneDeviceData->IDDeviceValid = agFALSE; + oneDeviceData->freeSATAFDMATagBitmap = 0; + oneDeviceData->NumOfFCA = 0; + oneDeviceData->NumOfIDRetries = 0; + oneDeviceData->ID_Retries = 0; + oneDeviceData->OSAbortAll = agFALSE; + + sm_memset(oneDeviceData->satMaxLBA, 0, sizeof(oneDeviceData->satMaxLBA)); + sm_memset(&(oneDeviceData->satIdentifyData), 0xFF, sizeof(agsaSATAIdentifyData_t)); + + oneDeviceData->satSaDeviceData = oneDeviceData; + + satIntIO = (smSatInternalIo_t *)&(oneDeviceData->satIntIo[0]); + for (j = 0; j < SAT_MAX_INT_IO; j++) + { + SM_DBG2(("tdsaDeviceDataReInit: in loop of internal io free, id %d\n", satIntIO->id)); + smsatFreeIntIoResource(smRoot, oneDeviceData, satIntIO); + satIntIO = satIntIO + 1; + } + + return; +} +osGLOBAL void +smDeviceDataInit( + smRoot_t *smRoot, + bit32 max_dev + ) +{ + smIntRoot_t *smIntRoot = (smIntRoot_t *)smRoot->smData; + smIntContext_t *smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + smDeviceData_t *smDeviceData = (smDeviceData_t *)smAllShared->DeviceMem; + int i,j; + smSatInternalIo_t *satIntIO; + + SM_DBG2(("smDeviceDataInit: start \n")); + + SMLIST_INIT_HDR(&(smAllShared->MainDeviceList)); + SMLIST_INIT_HDR(&(smAllShared->FreeDeviceList)); + + for(i=0;i<(int)max_dev;i++) + { + SMLIST_INIT_ELEMENT(&(smDeviceData[i].FreeLink)); + SMLIST_INIT_ELEMENT(&(smDeviceData[i].MainLink)); + smDeviceData[i].id = i; + smDeviceData[i].smRoot = agNULL; + smDeviceData[i].agDevHandle = agNULL; + smDeviceData[i].valid = agFALSE; + smDeviceData[i].SMAbortAll = agFALSE; + smDeviceData[i].smDevHandle = agNULL; + smDeviceData[i].directlyAttached = agFALSE; + smDeviceData[i].agExpDevHandle = agNULL; + smDeviceData[i].phyID = 0xFF; + smDeviceData[i].SMNumOfFCA = 0; + + + SMLIST_INIT_HDR(&(smDeviceData[i].satIoLinkList)); + SMLIST_INIT_HDR(&(smDeviceData[i].satFreeIntIoLinkList)); + SMLIST_INIT_HDR(&(smDeviceData[i].satActiveIntIoLinkList)); + + /* default */ + smDeviceData[i].satDriveState = SAT_DEV_STATE_NORMAL; + smDeviceData[i].satNCQMaxIO =SAT_NCQ_MAX; + smDeviceData[i].satPendingIO = 0; + smDeviceData[i].satPendingNCQIO = 0; + smDeviceData[i].satPendingNONNCQIO = 0; + smDeviceData[i].IDDeviceValid = agFALSE; + smDeviceData[i].freeSATAFDMATagBitmap = 0; + smDeviceData[i].NumOfFCA = 0; + smDeviceData[i].NumOfIDRetries = 0; + smDeviceData[i].ID_Retries = 0; + smDeviceData[i].OSAbortAll = agFALSE; + smInitTimerRequest(smRoot, &(smDeviceData[i].SATAIDDeviceTimer)); + + sm_memset(&(smDeviceData[i].satIdentifyData), 0xFF, sizeof(agsaSATAIdentifyData_t)); + sm_memset(smDeviceData[i].satMaxLBA, 0, sizeof(smDeviceData[i].satMaxLBA)); + + smDeviceData[i].satSaDeviceData = &smDeviceData[i]; + +#if 1 + satIntIO = &smDeviceData[i].satIntIo[0]; + for (j = 0; j < SAT_MAX_INT_IO; j++) + { + SMLIST_INIT_ELEMENT (&satIntIO->satIntIoLink); + SMLIST_ENQUEUE_AT_TAIL (&satIntIO->satIntIoLink, + &smDeviceData[i].satFreeIntIoLinkList); + satIntIO->satOrgSmIORequest = agNULL; + satIntIO->id = j; + satIntIO = satIntIO + 1; + } +#endif + + /* some other variables */ + SMLIST_ENQUEUE_AT_TAIL(&(smDeviceData[i].FreeLink), &(smAllShared->FreeDeviceList)); + } + + return; +} + +osGLOBAL void +smIOInit( + smRoot_t *smRoot + ) +{ + smIntRoot_t *smIntRoot = (smIntRoot_t *)smRoot->smData; + smIntContext_t *smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + smIORequestBody_t *smIOCommand = (smIORequestBody_t *)smAllShared->IOMem; + int i = 0; + + SM_DBG3(("smIOInit: start\n")); + + SMLIST_INIT_HDR(&(smAllShared->freeIOList)); + SMLIST_INIT_HDR(&(smAllShared->mainIOList)); + + for(i=0;ifreeIOList)); + } + + return; +} + +FORCEINLINE void +smIOReInit( + smRoot_t *smRoot, + smIORequestBody_t *smIORequestBody + ) +{ + SM_DBG3(("smIOReInit: start\n")); + smIORequestBody->InUse = agTRUE; + smIORequestBody->ioStarted = agFALSE; + smIORequestBody->ioCompleted = agFALSE; + smIORequestBody->reTries = 0; + smIORequestBody->smDevHandle = agNULL; + smIORequestBody->smIORequest = agNULL; + smIORequestBody->smIOToBeAbortedRequest = agNULL; + smIORequestBody->transport.SATA.satIOContext.satOrgIOContext = agNULL; + /*sm_memset(&(smIORequestBody->transport.SATA.agSATARequestBody), 0, sizeof(agsaSATAInitiatorRequest_t));*/ + return; +} + +/* end smapi defined APIS */ + diff --git a/sys/dev/pms/RefTisa/sat/src/smlist.h b/sys/dev/pms/RefTisa/sat/src/smlist.h new file mode 100644 index 000000000000..1f5608824fff --- /dev/null +++ b/sys/dev/pms/RefTisa/sat/src/smlist.h @@ -0,0 +1,161 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ + +#ifndef __SMLIST_H__ +#define __SMLIST_H__ + +typedef struct smList_s smList_t; + +struct smList_s { + smList_t *flink; + smList_t *blink; +}; + +#define SMLIST_INIT_HDR(hdr) \ + do { \ + ((smList_t *)(hdr))->flink = (smList_t *)(hdr); \ + ((smList_t *)(hdr))->blink = (smList_t *)(hdr); \ + } while (0) + +#define SMLIST_INIT_ELEMENT(hdr) \ + do { \ + ((smList_t *)(hdr))->flink = (smList_t *)agNULL; \ + ((smList_t *)(hdr))->blink = (smList_t *)agNULL; \ + } while (0) + +#define SMLIST_ENQUEUE_AT_HEAD(toAddHdr,listHdr) \ + do { \ + ((smList_t *)(toAddHdr))->flink = ((smList_t *)(listHdr))->flink; \ + ((smList_t *)(toAddHdr))->blink = (smList_t *)(listHdr) ; \ + ((smList_t *)(listHdr))->flink->blink = (smList_t *)(toAddHdr); \ + ((smList_t *)(listHdr))->flink = (smList_t *)(toAddHdr); \ + } while (0) + +#define SMLIST_ENQUEUE_AT_TAIL(toAddHdr,listHdr) \ + do { \ + ((smList_t *)(toAddHdr))->flink = (smList_t *)(listHdr); \ + ((smList_t *)(toAddHdr))->blink = ((smList_t *)(listHdr))->blink; \ + ((smList_t *)(listHdr))->blink->flink = (smList_t *)(toAddHdr); \ + ((smList_t *)(listHdr))->blink = (smList_t *)(toAddHdr); \ + } while (0) + +#define SMLIST_EMPTY(listHdr) \ + (((smList_t *)(listHdr))->flink == ((smList_t *)(listHdr))) + +#define SMLIST_NOT_EMPTY(listHdr) \ + (!SMLIST_EMPTY(listHdr)) + +#define SMLIST_DEQUEUE_THIS(hdr) \ + do { \ + ((smList_t *)(hdr))->blink->flink = ((smList_t *)(hdr))->flink; \ + ((smList_t *)(hdr))->flink->blink = ((smList_t *)(hdr))->blink; \ + ((smList_t *)(hdr))->flink = ((smList_t *)(hdr))->blink = agNULL; \ + } while (0) + +#define SMLIST_DEQUEUE_FROM_HEAD_FAST(atHeadHdr,listHdr) \ + do { \ + *((smList_t **)(atHeadHdr)) = ((smList_t *)(listHdr))->flink; \ + (*((smList_t **)(atHeadHdr)))->flink->blink = (smList_t *)(listHdr); \ + ((smList_t *)(listHdr))->flink = (*(smList_t **)(atHeadHdr))->flink; \ + } while (0) + +#define SMLIST_DEQUEUE_FROM_HEAD(atHeadHdr,listHdr) \ +do { \ + if (SMLIST_NOT_EMPTY((listHdr))) \ + { \ + SMLIST_DEQUEUE_FROM_HEAD_FAST(atHeadHdr,listHdr); \ + } \ + else \ + { \ + (*((smList_t **)(atHeadHdr))) = (smList_t *)agNULL; \ + } \ +} while (0) + +#define SMLIST_DEQUEUE_FROM_TAIL_FAST(atTailHdr,listHdr) \ + do { \ + (*((smList_t **)(atTailHdr))) = ((smList_t *)(listHdr))->blink; \ + (*((smList_t **)(atTailHdr)))->blink->flink = (smList_t *)(listHdr); \ + ((smList_t *)(listHdr))->blink = (*((smList_t **)(atTailHdr)))->blink; \ + } while (0) + +#define SMLIST_DEQUEUE_FROM_TAIL(atTailHdr,listHdr) \ + do { \ + if (SMLIST_NOT_EMPTY((listHdr))) \ + { \ + SMLIST_DEQUEUE_FROM_TAIL_FAST(atTailHdr,listHdr); \ + } \ + else \ + { \ + (*((smList_t **)(atTailHdr))) = (smList_t *)agNULL; \ + } \ + } while (0) + +#define SMLIST_ENQUEUE_LIST_AT_TAIL_FAST(toAddListHdr, listHdr) \ + do { \ + ((smList_t *)toAddListHdr)->blink->flink = ((smList_t *)listHdr); \ + ((smList_t *)toAddListHdr)->flink->blink = ((smList_t *)listHdr)->blink; \ + ((smList_t *)listHdr)->blink->flink = ((smList_t *)toAddListHdr)->flink; \ + ((smList_t *)listHdr)->blink = ((smList_t *)toAddListHdr)->blink; \ + SMLIST_INIT_HDR(toAddListHdr); \ + } while (0) + +#define SMLIST_ENQUEUE_LIST_AT_TAIL(toAddListHdr, listHdr) \ + do { \ + if (SMLIST_NOT_EMPTY(toAddListHdr)) \ + { \ + SMLIST_ENQUEUE_LIST_AT_TAIL_FAST(toAddListHdr, listHdr); \ + } \ + } while (0) + +#define SMLIST_ENQUEUE_LIST_AT_HEAD_FAST(toAddListHdr, listHdr) \ + do { \ + ((smList_t *)toAddListHdr)->blink->flink = ((smList_t *)listHdr)->flink; \ + ((smList_t *)toAddListHdr)->flink->blink = ((smList_t *)listHdr); \ + ((smList_t *)listHdr)->flink->blink = ((smList_t *)toAddListHdr)->blink; \ + ((smList_t *)listHdr)->flink = ((smList_t *)toAddListHdr)->flink; \ + SMLIST_INIT_HDR(toAddListHdr); \ + } while (0) + +#define SMLIST_ENQUEUE_LIST_AT_HEAD(toAddListHdr, listHdr) \ + do { \ + if (SMLIST_NOT_EMPTY(toAddListHdr)) \ + { \ + SMLIST_ENQUEUE_LIST_AT_HEAD_FAST(toAddListHdr, listHdr); \ + } \ + } while (0) + +#define TD_FIELD_OFFSET(baseType,fieldName) \ + ((bit32)((bitptr)(&(((baseType *)0)->fieldName)))) + +#define SMLIST_OBJECT_BASE(baseType,fieldName,fieldPtr) \ + (void *)fieldPtr == (void *)0 ? (baseType *)0 : \ + ((baseType *)((bit8 *)(fieldPtr) - ((bitptr)(&(((baseType *)0)->fieldName))))) + + + + +#endif /* __SMLIST_H__ */ + + + diff --git a/sys/dev/pms/RefTisa/sat/src/smmisc.c b/sys/dev/pms/RefTisa/sat/src/smmisc.c new file mode 100644 index 000000000000..7104cbdd9bda --- /dev/null +++ b/sys/dev/pms/RefTisa/sat/src/smmisc.c @@ -0,0 +1,116 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#include +#include + +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +FORCEINLINE void* +sm_memset(void *s, int c, bit32 n) +{ +/* bit32 i; + + char *dst = (char *)s; + for (i=0; i < n; i++) + { + dst[i] = (char) c; + } + return (void *)(&dst[i-n]); +*/ + return memset(s, c, n); +} + +FORCEINLINE void* +sm_memcpy(void *dst, const void *src, bit32 count) +{ +/* + bit32 x; + unsigned char *dst1 = (unsigned char *)dst; + unsigned char *src1 = (unsigned char *)src; + + for (x=0; x < count; x++) + dst1[x] = src1[x]; + + return dst; +*/ + return memcpy(dst, src, count); +} + +osGLOBAL char +*sm_strncpy(char *dst, const char *src, bit32 len) +{ +/* char *ret = dst; + do { + if (!len--) + return ret; + } while ((*dst++ = *src++)); + while (len--) + *dst++ = 0; + return ret; +*/ return strncpy(dst, src, len); +} + +/** hexidecimal dump */ +osGLOBAL void +smhexdump(const char *ptitle, bit8 *pbuf, size_t len) +{ + size_t i; + SM_DBG1(("%s - smhexdump(len=%d):\n", ptitle, (int)len)); + if (!pbuf) + { + SM_DBG1(("pbuf is NULL\n")); + return; + } + for (i = 0; i < len; ) + { + if (len - i > 4) + { + SM_DBG1((" 0x%02x, 0x%02x, 0x%02x, 0x%02x,\n", pbuf[i], pbuf[i+1], pbuf[i+2], pbuf[i+3])); + i += 4; + } + else + { + SM_DBG1((" 0x%02x,", pbuf[i])); + i++; + } + } + SM_DBG1(("\n")); +} + + diff --git a/sys/dev/pms/RefTisa/sat/src/smproto.h b/sys/dev/pms/RefTisa/sat/src/smproto.h new file mode 100644 index 000000000000..28701ba704ba --- /dev/null +++ b/sys/dev/pms/RefTisa/sat/src/smproto.h @@ -0,0 +1,1792 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +#ifndef __SMPROTO_H__ +#define __SMPROTO_H__ + +#include + +/***************** start of util ****************************************/ +osGLOBAL FORCEINLINE void* +sm_memset(void *s, int c, bit32 n); + +osGLOBAL FORCEINLINE void * +sm_memcpy(void *dst, const void *src, bit32 count); + +osGLOBAL char +*sm_strncpy(char *dst, const char *src, bit32 len); + + +osGLOBAL void +smhexdump(const char *ptitle, bit8 *pbuf, size_t len); +/***************** end of util ****************************************/ + +/***************** start of timer fns ****************************************/ +osGLOBAL void +smTimerTick(smRoot_t *smRoot ); + +osGLOBAL void +smInitTimerRequest( + smRoot_t *smRoot, + smTimerRequest_t *timerRequest + ); +osGLOBAL void +smSetTimerRequest( + smRoot_t *smRoot, + smTimerRequest_t *timerRequest, + bit32 timeout, + smTimerCBFunc_t CBFunc, + void *timerData1, + void *timerData2, + void *timerData3 + ); + +osGLOBAL void +smAddTimer( + smRoot_t *smRoot, + smList_t *timerListHdr, + smTimerRequest_t *timerRequest + ); + +osGLOBAL void +smKillTimer( + smRoot_t *smRoot, + smTimerRequest_t *timerRequest + ); + +osGLOBAL void +smProcessTimers( + smRoot_t *smRoot + ); + + +/***************** end of timer fns ****************************************/ + +osGLOBAL void +smInitTimers( + smRoot_t *smRoot + ); + +osGLOBAL void +smDeviceDataInit( + smRoot_t *smRoot, + bit32 max_dev + ); + +osGLOBAL void +smIOInit( + smRoot_t *smRoot + ); + +osGLOBAL FORCEINLINE void +smIOReInit( + smRoot_t *smRoot, + smIORequestBody_t *smIORequestBody + ); + +osGLOBAL void +smDeviceDataReInit( + smRoot_t *smRoot, + smDeviceData_t *oneDeviceData + ); + +osGLOBAL void +smEnqueueIO( + smRoot_t *smRoot, + smSatIOContext_t *satIOContext + ); + +osGLOBAL FORCEINLINE void +smsatFreeIntIoResource( + smRoot_t *smRoot, + smDeviceData_t *satDevData, + smSatInternalIo_t *satIntIo + ); + +osGLOBAL smSatInternalIo_t * +smsatAllocIntIoResource( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceData_t *satDevData, + bit32 dmaAllocLength, + smSatInternalIo_t *satIntIo); + + + +osGLOBAL smDeviceData_t * +smAddToSharedcontext( + smRoot_t *smRoot, + agsaDevHandle_t *agDevHandle, + smDeviceHandle_t *smDeviceHandle, + agsaDevHandle_t *agExpDevHandle, + bit32 phyID + ); + +osGLOBAL bit32 +smRemoveFromSharedcontext( + smRoot_t *smRoot, + agsaDevHandle_t *agDevHandle, + smDeviceHandle_t *smDeviceHandle + ); + +osGLOBAL smDeviceData_t * +smFindInSharedcontext( + smRoot_t *smRoot, + agsaDevHandle_t *agDevHandle + ); + +osGLOBAL bit32 +smsatLogSenseAllocate( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smSCSIRequest, + smSatIOContext_t *satIOContext, + bit32 payloadSize, + bit32 flag + ); + +osGLOBAL bit32 +smsatIDSubStart( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smSCSIRequest, + smSatIOContext_t *satIOContext + ); + + +osGLOBAL bit32 +smsatIDStart( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smSCSIRequest, + smSatIOContext_t *satIOContext + ); + + +osGLOBAL FORCEINLINE bit32 +smsatIOStart( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smSCSIRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL void +smsatSetSensePayload( + smScsiRspSense_t *pSense, + bit8 SnsKey, + bit32 SnsInfo, + bit16 SnsCode, + smSatIOContext_t *satIOContext + ); + +osGLOBAL void +smsatSetDeferredSensePayload( + smScsiRspSense_t *pSense, + bit8 SnsKey, + bit32 SnsInfo, + bit16 SnsCode, + smSatIOContext_t *satIOContext + ); + +osGLOBAL FORCEINLINE bit32 +smsatIOPrepareSGL( + smRoot_t *smRoot, + smIORequestBody_t *smIORequestBody, + smSgl_t *smSgl1, + void *sglVirtualAddr + ); +osGLOBAL FORCEINLINE void +smsatBitSet(smRoot_t *smRoot,bit8 *data, bit32 index); + +osGLOBAL FORCEINLINE void +smsatBitClear(smRoot_t *smRoot,bit8 *data, bit32 index); + +osGLOBAL FORCEINLINE BOOLEAN +smsatBitTest(smRoot_t *smRoot,bit8 *data, bit32 index); + +osGLOBAL FORCEINLINE bit32 +smsatTagAlloc( + smRoot_t *smRoot, + smDeviceData_t *pSatDevData, + bit8 *pTag + ); + +osGLOBAL FORCEINLINE bit32 +smsatTagRelease( + smRoot_t *smRoot, + smDeviceData_t *pSatDevData, + bit8 tag + ); + +osGLOBAL FORCEINLINE void +smsatDecrementPendingIO( + smRoot_t *smRoot, + smIntContext_t *smAllShared, + smSatIOContext_t *satIOContext + ); + +osGLOBAL smSatIOContext_t * +smsatPrepareNewIO( + smSatInternalIo_t *satNewIntIo, + smIORequest_t *smOrgIORequest, + smDeviceData_t *satDevData, + smIniScsiCmnd_t *scsiCmnd, + smSatIOContext_t *satOrgIOContext + ); + +osGLOBAL void +smsatSetDevInfo( + smDeviceData_t *oneDeviceData, + agsaSATAIdentifyData_t *SATAIdData + ); + +osGLOBAL void +smsatInquiryStandard( + bit8 *pInquiry, + agsaSATAIdentifyData_t *pSATAIdData, + smIniScsiCmnd_t *scsiCmnd + ); + +osGLOBAL void +smsatInquiryPage0( + bit8 *pInquiry, + agsaSATAIdentifyData_t *pSATAIdData + ); + +osGLOBAL void +smsatInquiryPage83( + bit8 *pInquiry, + agsaSATAIdentifyData_t *pSATAIdData, + smDeviceData_t *oneDeviceData + ); + + +osGLOBAL void +smsatInquiryPage89( + bit8 *pInquiry, + agsaSATAIdentifyData_t *pSATAIdData, + smDeviceData_t *oneDeviceData, + bit32 len + ); + +osGLOBAL void +smsatInquiryPage80( + bit8 *pInquiry, + agsaSATAIdentifyData_t *pSATAIdData + ); + +osGLOBAL void +smsatInquiryPageB1( + bit8 *pInquiry, + agsaSATAIdentifyData_t *pSATAIdData + ); + +osGLOBAL void +smsatDefaultTranslation( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smSatIOContext_t *satIOContext, + smScsiRspSense_t *pSense, + bit8 ataStatus, + bit8 ataError, + bit32 interruptContext + ); + +osGLOBAL bit32 +smPhyControlSend( + smRoot_t *smRoot, + smDeviceData_t *oneDeviceData, + bit8 phyOp, + smIORequest_t *CurrentTaskTag, + bit32 queueNumber + ); + +osGLOBAL bit32 +smsatTaskManagement( + smRoot_t *smRoot, + smDeviceHandle_t *smDeviceHandle, + bit32 task, + smLUN_t *lun, + smIORequest_t *taskTag, + smIORequest_t *currentTaskTag, + smIORequestBody_t *smIORequestBody + ); + +osGLOBAL bit32 +smsatTmAbortTask( + smRoot_t *smRoot, + smIORequest_t *currentTaskTag, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *tiScsiRequest, + smSatIOContext_t *satIOContext, + smIORequest_t *taskTag); + +osGLOBAL bit32 +smsatStartCheckPowerMode( + smRoot_t *smRoot, + smIORequest_t *currentTaskTag, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); +osGLOBAL bit32 +smsatStartResetDevice( + smRoot_t *smRoot, + smIORequest_t *currentTaskTag, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); +osGLOBAL void +smsatAbort( + smRoot_t *smRoot, + agsaRoot_t *agRoot, + smSatIOContext_t *satIOContext + ); + +osGLOBAL smIORequestBody_t * +smDequeueIO(smRoot_t *smRoot); + +osGLOBAL bit32 +smsatDecodeSATADeviceType(bit8 * pSignature); + +/******************************** beginning of start ******************************************************/ + +/*! \brief SAT implementation for ATAPI Packet Command. + * + * SAT implementation for ATAPI Packet and send FIS request to LL layer. + * + * \param smRoot: Pointer to TISA initiator driver/port instance. + * \param smIORequest: Pointer to TISA I/O request context for this I/O. + * \param smDeviceHandle: Pointer to TISA device handle for this I/O. + * \param smScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param smSatIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e smIOSuccess: I/O request successfully initiated. + * - \e smIOBusy: No resources available, try again later. + * - \e smIOIONoDevice: Invalid device handle. + * - \e smIOError: Other errors. + */ +/*****************************************************************************/ +osGLOBAL bit32 +smsatPacket( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL void +smsatPacketCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ); +/*****************************************************************************/ +/*! \brief SAT implementation for smsatExecuteDeviceDiagnostic. + * + * This function creates Execute Device Diagnostic fis and sends the request to LL layer + * + * \param smRoot: Pointer to TISA initiator driver/port instance. + * \param smIORequest: Pointer to TISA I/O request context for this I/O. + * \param smDeviceHandle: Pointer to TISA device handle for this I/O. + * \param smScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param smSatIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e smIOSuccess: I/O request successfully initiated. + * - \e smIOBusy: No resources available, try again later. + * - \e smIOIONoDevice: Invalid device handle. + * - \e smIOError: Other errors. + + */ +/*****************************************************************************/ +osGLOBAL bit32 +smsatExecuteDeviceDiagnostic( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL void +smsatExecuteDeviceDiagnosticCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ); +/* set feature for auto activate */ +osGLOBAL bit32 +smsatSetFeaturesAA( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); +osGLOBAL void +smsatSetFeaturesAACB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ); + +/*****************************************************************************/ +/*! \brief SAT implementation for satSetFeatures. + * + * This function creates SetFeatures fis and sends the request to LL layer + * + * \param smRoot: Pointer to TISA initiator driver/port instance. + * \param smIORequest: Pointer to TISA I/O request context for this I/O. + * \param smDeviceHandle: Pointer to TISA device handle for this I/O. + * \param smScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param smSatIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e smIOSuccess: I/O request successfully initiated. + * - \e smIOBusy: No resources available, try again later. + * - \e smIOIONoDevice: Invalid device handle. + * - \e smIOError: Other errors. + */ +/*****************************************************************************/ +osGLOBAL bit32 +smsatSetFeaturesPIO( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); +osGLOBAL void +smsatSetFeaturesPIOCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ); + +osGLOBAL bit32 +smsatSetFeaturesDMA( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL void +smsatSetFeaturesDMACB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ); + +osGLOBAL bit32 +smsatSetFeaturesReadLookAhead( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL void +smsatSetFeaturesReadLookAheadCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ); + +osGLOBAL bit32 +smsatSetFeaturesVolatileWriteCache( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL void +smsatSetFeaturesVolatileWriteCacheCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ); + +osGLOBAL void +smsatSMARTEnablePassCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); + +osGLOBAL void +smsatSMARTRStatusPassCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ); +osGLOBAL void +smsatSMARTReadLogCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ); + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI REQUEST SENSE to ATAPI device. + * + * SAT implementation for SCSI REQUEST SENSE. + * + * \param smRoot: Pointer to TISA initiator driver/port instance. + * \param smIORequest: Pointer to TISA I/O request context for this I/O. + * \param smDeviceHandle: Pointer to TISA device handle for this I/O. + * \param smScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param smSatIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e smIOSuccess: I/O request successfully initiated. + * - \e smIOBusy: No resources available, try again later. + * - \e smIOIONoDevice: Invalid device handle. + * - \e smIOError: Other errors. + */ +/*****************************************************************************/ +osGLOBAL bit32 +smsatRequestSenseForATAPI( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL void +smsatRequestSenseForATAPICB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ); + +/*****************************************************************************/ +/*! \brief SAT implementation for smsatDeviceReset. + * + * This function creates DEVICE RESET fis and sends the request to LL layer + * + * \param smRoot: Pointer to TISA initiator driver/port instance. + * \param smIORequest: Pointer to TISA I/O request context for this I/O. + * \param smDeviceHandle: Pointer to TISA device handle for this I/O. + * \param smScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param smSatIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e smIOSuccess: I/O request successfully initiated. + * - \e smIOBusy: No resources available, try again later. + * - \e smIONoDevice: Invalid device handle. + * - \e smIOError: Other errors. + */ +/*****************************************************************************/ +osGLOBAL bit32 +smsatDeviceReset( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL void +smsatDeviceResetCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ); + + +osGLOBAL void +smsatTranslateATAPIErrorsToSCSIErrors( + bit8 bCommand, + bit8 bATAStatus, + bit8 bATAError, + bit8 *pSenseKey, + bit16 *pSenseCodeInfo + ); + +GLOBAL void +smsatTranslateATAErrorsToSCSIErrors( + bit8 bATAStatus, + bit8 bATAError, + bit8 *pSenseKey, + bit16 *pSenseCodeInfo + ); + +/*****************************************************************************/ + +osGLOBAL bit32 +smsatRead6( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL FORCEINLINE bit32 +smsatRead10( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatRead12( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatRead16( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatWrite6( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL FORCEINLINE bit32 +smsatWrite10( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatWrite12( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatWrite16( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatVerify10( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatVerify12( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatVerify16( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatTestUnitReady( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatInquiry( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatRequestSense( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatModeSense6( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatModeSense10( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatReadCapacity10( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatReadCapacity16( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatReportLun( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatFormatUnit( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatSendDiagnostic( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatStartStopUnit( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatWriteSame10( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatWriteSame16( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatLogSense( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatModeSelect6( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + + +osGLOBAL bit32 +smsatModeSelect10( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatSynchronizeCache10( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatSynchronizeCache16( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatWriteAndVerify10( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatWriteAndVerify12( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatWriteAndVerify16( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatReadMediaSerialNumber( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatReadBuffer( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatWriteBuffer( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatReassignBlocks( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatPassthrough( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL FORCEINLINE bit32 +smsataLLIOStart( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); +osGLOBAL bit32 +smsatTestUnitReady_1( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); +osGLOBAL bit32 +smsatStartIDDev( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatSendIDDev( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatRequestSense_1( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatSMARTEnable( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatLogSense_2( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatLogSense_3( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatRead_1( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatWrite_1( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatNonChainedWriteNVerify_Verify( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatChainedWriteNVerify_Start_Verify( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatChainedWriteNVerify_Write( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatChainedWriteNVerify_Verify( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); +osGLOBAL bit32 +smsatChainedVerify( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatWriteSame10_1( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext, + bit32 lba + ); + +osGLOBAL bit32 +smsatWriteSame10_2( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext, + bit32 lba + ); + +osGLOBAL bit32 +smsatWriteSame10_3( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext, + bit32 lba + ); + +osGLOBAL bit32 +smsatStartStopUnit_1( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatSendDiagnostic_1( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatSendDiagnostic_2( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatModeSelect6n10_1( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatLogSense_1( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatReassignBlocks_2( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext, + bit8 *LBA + ); + +osGLOBAL bit32 +smsatReassignBlocks_1( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext, + smSatIOContext_t *satOrgIOContext + ); + +osGLOBAL bit32 +smsatSendReadLogExt( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatCheckPowerMode( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatResetDevice( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL bit32 +smsatDeResetDevice( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); +/******************************** beginning of completion ******************************************************/ +osGLOBAL FORCEINLINE void +smllSATACompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + void *agFirstDword, + bit32 agIOInfoLen, + void *agParam + ); + + +osGLOBAL FORCEINLINE void +smsatNonChainedDataIOCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ); + +osGLOBAL FORCEINLINE void +smsatChainedDataIOCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ); + +osGLOBAL void +smsatNonChainedVerifyCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); + +osGLOBAL void +smsatChainedVerifyCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); + +osGLOBAL void +smsatTestUnitReadyCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); +osGLOBAL void +smsatRequestSenseCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ); + +osGLOBAL void +smsatSendDiagnosticCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); + +osGLOBAL void +smsatStartStopUnitCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); + + +osGLOBAL void +smsatWriteSame10CB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); + + +osGLOBAL void +smsatLogSenseCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioCotext + ); + +osGLOBAL void +smsatSMARTEnableCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); + +osGLOBAL void +smsatModeSelect6n10CB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); + +osGLOBAL void +smsatSynchronizeCache10n16CB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); + +osGLOBAL void +smsatNonChainedWriteNVerifyCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ); + +osGLOBAL void +smsatChainedWriteNVerifyCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ); + +osGLOBAL void +smsatReadMediaSerialNumberCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); + +osGLOBAL void +smsatReadBufferCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); + +osGLOBAL void +smsatWriteBufferCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); + +osGLOBAL void +smsatReassignBlocksCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); + +osGLOBAL void +smsatProcessAbnormalCompletion( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + smSatIOContext_t *satIOContext + ); + +osGLOBAL void +smsatDelayedProcessAbnormalCompletion( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + smSatIOContext_t *satIOContext + ); + +osGLOBAL void +smsatIOCompleted( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + agsaFisHeader_t *agFirstDword, + bit32 respFisLen, + agsaFrameHandle_t agFrameHandle, + smSatIOContext_t *satIOContext, + bit32 interruptContext + ); + +osGLOBAL void +smsatEncryptionHandler( + smRoot_t *smRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo, + bit32 interruptContext + ); + +osGLOBAL void +smsatDifHandler( + smRoot_t *smRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo, + bit32 interruptContext + ); + +osGLOBAL void +smsatProcessAbort( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL void +smsatNonDataIOCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ); + +osGLOBAL void +smsatInquiryCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ); + + +osGLOBAL void +smsatInquiryIntCB( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ); + +osGLOBAL void +smsatVerify10CB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ); + +osGLOBAL void +smsatReadLogExtCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ); + + +osGLOBAL void +smsatIDStartCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ); + +osGLOBAL void +smSMPCompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle + ); + +osGLOBAL void +smSMPCompletedCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle + ); + +osGLOBAL void +smPhyControlRespRcvd( + smRoot_t *smRoot, + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + smDeviceData_t *oneDeviceData, + smSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle, + smIORequest_t *CurrentTaskTag + ); + +osGLOBAL void +smsatCheckPowerModeCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); + +osGLOBAL void +smsatCheckPowerModePassCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); + +osGLOBAL void +smsatIDDataPassCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); + +osGLOBAL void +smsatResetDeviceCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); + +osGLOBAL void +smsatDeResetDeviceCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); +osGLOBAL void +smaSATAAbortCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 flag, + bit32 status + ); + +osGLOBAL void +smLocalPhyControlCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 phyId, + bit32 phyOperation, + bit32 status, + void *parm + ); +/******************************** end of completion ***********************************************************/ + +/******************************** start of utils ***********************************************************/ +osGLOBAL bit32 smsatComputeCDB10LBA(smSatIOContext_t *satIOContext); +osGLOBAL bit32 smsatComputeCDB10TL(smSatIOContext_t *satIOContext); +osGLOBAL bit32 smsatComputeCDB12LBA(smSatIOContext_t *satIOContext); +osGLOBAL bit32 smsatComputeCDB12TL(smSatIOContext_t *satIOContext); +osGLOBAL bit32 smsatComputeCDB16LBA(smSatIOContext_t *satIOContext); +osGLOBAL bit32 smsatComputeCDB16TL(smSatIOContext_t *satIOContext); +osGLOBAL FORCEINLINE bit32 smsatComputeLoopNum(bit32 a, bit32 b); +osGLOBAL FORCEINLINE bit32 smsatCheckLimit(bit8 *lba, bit8 *tl, int flag, smDeviceData_t *pSatDevData); + +osGLOBAL void +smsatSplitSGL( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext, + bit32 split, + bit32 tl, + bit32 flag + ); + +osGLOBAL void +smsatPrintSgl( + smRoot_t *smRoot, + agsaEsgl_t *agEsgl, + bit32 idx + ); +/******************************** end of utils ***********************************************************/ + + +osGLOBAL void +smsatPassthroughCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ); + + +#endif /* __SMPROTO_H__ */ + diff --git a/sys/dev/pms/RefTisa/sat/src/smsat.c b/sys/dev/pms/RefTisa/sat/src/smsat.c new file mode 100644 index 000000000000..8b6aaeb2131b --- /dev/null +++ b/sys/dev/pms/RefTisa/sat/src/smsat.c @@ -0,0 +1,20820 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#include +#include + +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +/* start smapi defined APIs */ +osGLOBAL bit32 +smRegisterDevice( + smRoot_t *smRoot, + agsaDevHandle_t *agDevHandle, + smDeviceHandle_t *smDeviceHandle, + agsaDevHandle_t *agExpDevHandle, + bit32 phyID, + bit32 DeviceType + ) +{ + smDeviceData_t *oneDeviceData = agNULL; + + SM_DBG2(("smRegisterDevice: start\n")); + + if (smDeviceHandle == agNULL) + { + SM_DBG1(("smRegisterDevice: smDeviceHandle is NULL!!!\n")); + return SM_RC_FAILURE; + } + + if (agDevHandle == agNULL) + { + SM_DBG1(("smRegisterDevice: agDevHandle is NULL!!!\n")); + return SM_RC_FAILURE; + } + + oneDeviceData = smAddToSharedcontext(smRoot, agDevHandle, smDeviceHandle, agExpDevHandle, phyID); + if (oneDeviceData != agNULL) + { + oneDeviceData->satDeviceType = DeviceType; + return SM_RC_SUCCESS; + } + else + { + return SM_RC_FAILURE; + } + +} + +osGLOBAL bit32 +smDeregisterDevice( + smRoot_t *smRoot, + agsaDevHandle_t *agDevHandle, + smDeviceHandle_t *smDeviceHandle + ) +{ + bit32 status = SM_RC_FAILURE; + + SM_DBG2(("smDeregisterDevice: start\n")); + + if (smDeviceHandle == agNULL) + { + SM_DBG1(("smDeregisterDevice: smDeviceHandle is NULL!!!\n")); + return SM_RC_FAILURE; + } + + if (agDevHandle == agNULL) + { + SM_DBG1(("smDeregisterDevice: agDevHandle is NULL!!!\n")); + return SM_RC_FAILURE; + } + + status = smRemoveFromSharedcontext(smRoot, agDevHandle, smDeviceHandle); + + return status; +} + +osGLOBAL bit32 +smIOAbort( + smRoot_t *smRoot, + smIORequest_t *tasktag + ) + +{ + smIntRoot_t *smIntRoot = (smIntRoot_t *)smRoot->smData; + smIntContext_t *smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + agsaRoot_t *agRoot; + smIORequestBody_t *smIORequestBody = agNULL; + smIORequestBody_t *smIONewRequestBody = agNULL; + agsaIORequest_t *agIORequest = agNULL; /* IO to be aborted */ + bit32 status = SM_RC_FAILURE; + agsaIORequest_t *agAbortIORequest; /* abort IO itself */ + smIORequestBody_t *smAbortIORequestBody; +#if 1 + bit32 PhysUpper32; + bit32 PhysLower32; + bit32 memAllocStatus; + void *osMemHandle; +#endif + smSatIOContext_t *satIOContext; + smSatInternalIo_t *satIntIo; + smSatIOContext_t *satAbortIOContext; + + SM_DBG1(("smIOAbort: start\n")); + SM_DBG2(("smIOAbort: tasktag %p\n", tasktag)); + /* + alloc smIORequestBody for abort itself + call saSATAAbort() + */ + + agRoot = smAllShared->agRoot; + smIORequestBody = (smIORequestBody_t *)tasktag->smData; + + if (smIORequestBody == agNULL) + { + SM_DBG1(("smIOAbort: smIORequestBody is NULL!!!\n")); + return SM_RC_FAILURE; + } + + /* needs to distinguish internally generated or externally generated */ + satIOContext = &(smIORequestBody->transport.SATA.satIOContext); + satIntIo = satIOContext->satIntIoContext; + if (satIntIo == agNULL) + { + SM_DBG2(("smIOAbort: External, OS generated\n")); + agIORequest = &(smIORequestBody->agIORequest); + } + else + { + SM_DBG2(("smIOAbort: Internal, SM generated\n")); + smIONewRequestBody = (smIORequestBody_t *)satIntIo->satIntRequestBody; + agIORequest = &(smIONewRequestBody->agIORequest); + } + + /* + allocate smAbortIORequestBody for abort request itself + */ + +#if 1 + /* allocating agIORequest for abort itself */ + memAllocStatus = tdsmAllocMemory( + smRoot, + &osMemHandle, + (void **)&smAbortIORequestBody, + &PhysUpper32, + &PhysLower32, + 8, + sizeof(smIORequestBody_t), + agTRUE + ); + if (memAllocStatus != SM_RC_SUCCESS) + { + /* let os process IO */ + SM_DBG1(("smIOAbort: tdsmAllocMemory failed...!!!\n")); + return SM_RC_FAILURE; + } + + if (smAbortIORequestBody == agNULL) + { + /* let os process IO */ + SM_DBG1(("smIOAbort: tdsmAllocMemory returned NULL smAbortIORequestBody!!!\n")); + return SM_RC_FAILURE; + } + + smIOReInit(smRoot, smAbortIORequestBody); + + /* setup task management structure */ + smAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle = osMemHandle; + satAbortIOContext = &(smAbortIORequestBody->transport.SATA.satIOContext); + satAbortIOContext->smRequestBody = smAbortIORequestBody; + + smAbortIORequestBody->smDevHandle = smIORequestBody->smDevHandle; + + /* initialize agIORequest */ + agAbortIORequest = &(smAbortIORequestBody->agIORequest); + agAbortIORequest->osData = (void *) smAbortIORequestBody; + agAbortIORequest->sdkData = agNULL; /* LL takes care of this */ + + /* remember IO to be aborted */ + smAbortIORequestBody->smIOToBeAbortedRequest = tasktag; + + status = saSATAAbort(agRoot, agAbortIORequest, 0, agNULL, 0, agIORequest, smaSATAAbortCB); + + SM_DBG2(("smIOAbort: return status=0x%x\n", status)); + +#endif /* 1 */ + + + if (status == AGSA_RC_SUCCESS) + { + return SM_RC_SUCCESS; + } + else + { + SM_DBG1(("smIOAbort: failed to call saSATAAbort, status=%d!!!\n", status)); + tdsmFreeMemory(smRoot, + smAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(smIORequestBody_t) + ); + return SM_RC_FAILURE; + } +} + +osGLOBAL bit32 +smIOAbortAll( + smRoot_t *smRoot, + smDeviceHandle_t *smDeviceHandle + ) +{ + smIntRoot_t *smIntRoot = (smIntRoot_t *)smRoot->smData; + smIntContext_t *smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + agsaRoot_t *agRoot; + bit32 status = SM_RC_FAILURE; + agsaIORequest_t *agAbortIORequest; + smIORequestBody_t *smAbortIORequestBody; + smSatIOContext_t *satAbortIOContext; + smDeviceData_t *oneDeviceData = agNULL; + agsaDevHandle_t *agDevHandle; + + bit32 PhysUpper32; + bit32 PhysLower32; + bit32 memAllocStatus; + void *osMemHandle; + + + SM_DBG2(("smIOAbortAll: start\n")); + + agRoot = smAllShared->agRoot; + + if (smDeviceHandle == agNULL) + { + SM_DBG1(("smIOAbortAll: smDeviceHandle is NULL!!!\n")); + return SM_RC_FAILURE; + } + + oneDeviceData = (smDeviceData_t *)smDeviceHandle->smData; + if (oneDeviceData == agNULL) + { + SM_DBG1(("smIOAbortAll: oneDeviceData is NULL!!!\n")); + return SM_RC_FAILURE; + } + if (oneDeviceData->valid == agFALSE) + { + SM_DBG1(("smIOAbortAll: oneDeviceData is not valid, did %d !!!\n", oneDeviceData->id)); + return SM_RC_FAILURE; + } + + agDevHandle = oneDeviceData->agDevHandle; + if (agDevHandle == agNULL) + { + SM_DBG1(("smIOAbortAll: agDevHandle is NULL!!!\n")); + return SM_RC_FAILURE; + } +/* + smAbortIORequestBody = smDequeueIO(smRoot); + if (smAbortIORequestBody == agNULL) + { + SM_DBG1(("smIOAbortAll: empty freeIOList!!!\n")); + return SM_RC_FAILURE; + } +*/ + /* allocating agIORequest for abort itself */ + memAllocStatus = tdsmAllocMemory( + smRoot, + &osMemHandle, + (void **)&smAbortIORequestBody, + &PhysUpper32, + &PhysLower32, + 8, + sizeof(smIORequestBody_t), + agTRUE + ); + if (memAllocStatus != SM_RC_SUCCESS) + { + /* let os process IO */ + SM_DBG1(("smIOAbortAll: tdsmAllocMemory failed...!!!\n")); + return SM_RC_FAILURE; + } + + if (smAbortIORequestBody == agNULL) + { + /* let os process IO */ + SM_DBG1(("smIOAbortAll: tdsmAllocMemory returned NULL smAbortIORequestBody!!!\n")); + return SM_RC_FAILURE; + } + + smIOReInit(smRoot, smAbortIORequestBody); + + /* setup task management structure */ + smAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle = osMemHandle; + + satAbortIOContext = &(smAbortIORequestBody->transport.SATA.satIOContext); + satAbortIOContext->smRequestBody = smAbortIORequestBody; + smAbortIORequestBody->smDevHandle = smDeviceHandle; + + /* initialize agIORequest */ + agAbortIORequest = &(smAbortIORequestBody->agIORequest); + agAbortIORequest->osData = (void *) smAbortIORequestBody; + agAbortIORequest->sdkData = agNULL; /* LL takes care of this */ + + oneDeviceData->OSAbortAll = agTRUE; + /* abort all */ + status = saSATAAbort(agRoot, agAbortIORequest, tdsmRotateQnumber(smRoot, smDeviceHandle), agDevHandle, 1, agNULL, smaSATAAbortCB); + if (status != AGSA_RC_SUCCESS) + { + SM_DBG1(("smIOAbortAll: failed to call saSATAAbort, status=%d!!!\n", status)); + tdsmFreeMemory(smRoot, + smAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(smIORequestBody_t) + ); + } + + return status; +} + +osGLOBAL bit32 +smSuperIOStart( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smSuperScsiInitiatorRequest_t *smSCSIRequest, + bit32 AddrHi, + bit32 AddrLo, + bit32 interruptContext + ) +{ + smDeviceData_t *oneDeviceData = agNULL; + smIORequestBody_t *smIORequestBody = agNULL; + smSatIOContext_t *satIOContext = agNULL; + bit32 status = SM_RC_FAILURE; + + SM_DBG2(("smSuperIOStart: start\n")); + + oneDeviceData = (smDeviceData_t *)smDeviceHandle->smData; + if (oneDeviceData == agNULL) + { + SM_DBG1(("smSuperIOStart: oneDeviceData is NULL!!!\n")); + return SM_RC_FAILURE; + } + if (oneDeviceData->valid == agFALSE) + { + SM_DBG1(("smSuperIOStart: oneDeviceData is not valid, did %d !!!\n", oneDeviceData->id)); + return SM_RC_FAILURE; + } + smIORequestBody = (smIORequestBody_t*)smIORequest->smData;//smDequeueIO(smRoot); + + if (smIORequestBody == agNULL) + { + SM_DBG1(("smSuperIOStart: smIORequestBody is NULL!!!\n")); + return SM_RC_FAILURE; + } + + smIOReInit(smRoot, smIORequestBody); + + SM_DBG3(("smSuperIOStart: io ID %d!!!\n", smIORequestBody->id )); + + oneDeviceData->sasAddressHi = AddrHi; + oneDeviceData->sasAddressLo = AddrLo; + + smIORequestBody->smIORequest = smIORequest; + smIORequestBody->smDevHandle = smDeviceHandle; + + satIOContext = &(smIORequestBody->transport.SATA.satIOContext); + + /* + * Need to initialize all the fields within satIOContext except + * reqType and satCompleteCB which will be set later in SM. + */ + smIORequestBody->transport.SATA.smSenseData.senseData = agNULL; + smIORequestBody->transport.SATA.smSenseData.senseLen = 0; + satIOContext->pSatDevData = oneDeviceData; + satIOContext->pFis = + &smIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev; + satIOContext->pScsiCmnd = &smSCSIRequest->scsiCmnd; + satIOContext->pSense = &smIORequestBody->transport.SATA.sensePayload; + satIOContext->pSmSenseData = &smIORequestBody->transport.SATA.smSenseData; + satIOContext->pSmSenseData->senseData = satIOContext->pSense; + /* satIOContext->pSense = (scsiRspSense_t *)satIOContext->pSmSenseData->senseData; */ + satIOContext->smRequestBody = smIORequestBody; + satIOContext->interruptContext = interruptContext; + satIOContext->psmDeviceHandle = smDeviceHandle; + satIOContext->smScsiXchg = smSCSIRequest; + satIOContext->superIOFlag = agTRUE; +// satIOContext->superIOFlag = agFALSE; + + satIOContext->satIntIoContext = agNULL; + satIOContext->satOrgIOContext = agNULL; + /* satIOContext->tiIORequest = tiIORequest; */ + + /* save context if we need to abort later */ + /*smIORequest->smData = smIORequestBody;*/ + + /* followings are used only for internal IO */ + satIOContext->currentLBA = 0; + satIOContext->OrgTL = 0; + + status = smsatIOStart(smRoot, smIORequest, smDeviceHandle, (smScsiInitiatorRequest_t *)smSCSIRequest, satIOContext); + + return status; +} + +/* +osGLOBAL bit32 +tiINIIOStart( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + void *tiRequestBody, + bit32 interruptContext + ) + +GLOBAL bit32 satIOStart( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + smSatIOContext_t *satIOContext + ) +smIOStart( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smSCSIRequest, + smIORequestBody_t *smRequestBody, + bit32 interruptContext + ) + + +*/ +FORCEINLINE bit32 +smIOStart( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smSCSIRequest, + bit32 interruptContext + ) +{ + smDeviceData_t *oneDeviceData = agNULL; + smIORequestBody_t *smIORequestBody = agNULL; + smSatIOContext_t *satIOContext = agNULL; + bit32 status = SM_RC_FAILURE; + + SM_DBG2(("smIOStart: start\n")); + + oneDeviceData = (smDeviceData_t *)smDeviceHandle->smData; + if (oneDeviceData == agNULL) + { + SM_DBG1(("smIOStart: oneDeviceData is NULL!!!\n")); + return SM_RC_FAILURE; + } + if (oneDeviceData->valid == agFALSE) + { + SM_DBG1(("smIOStart: oneDeviceData is not valid, did %d !!!\n", oneDeviceData->id)); + return SM_RC_FAILURE; + } + smIORequestBody = (smIORequestBody_t*)smIORequest->smData;//smDequeueIO(smRoot); + + if (smIORequestBody == agNULL) + { + SM_DBG1(("smIOStart: smIORequestBody is NULL!!!\n")); + return SM_RC_FAILURE; + } + + smIOReInit(smRoot, smIORequestBody); + + SM_DBG3(("smIOStart: io ID %d!!!\n", smIORequestBody->id )); + + smIORequestBody->smIORequest = smIORequest; + smIORequestBody->smDevHandle = smDeviceHandle; + + satIOContext = &(smIORequestBody->transport.SATA.satIOContext); + + /* + * Need to initialize all the fields within satIOContext except + * reqType and satCompleteCB which will be set later in SM. + */ + smIORequestBody->transport.SATA.smSenseData.senseData = agNULL; + smIORequestBody->transport.SATA.smSenseData.senseLen = 0; + satIOContext->pSatDevData = oneDeviceData; + satIOContext->pFis = + &smIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev; + satIOContext->pScsiCmnd = &smSCSIRequest->scsiCmnd; + satIOContext->pSense = &smIORequestBody->transport.SATA.sensePayload; + satIOContext->pSmSenseData = &smIORequestBody->transport.SATA.smSenseData; + satIOContext->pSmSenseData->senseData = satIOContext->pSense; + /* satIOContext->pSense = (scsiRspSense_t *)satIOContext->pSmSenseData->senseData; */ + satIOContext->smRequestBody = smIORequestBody; + satIOContext->interruptContext = interruptContext; + satIOContext->psmDeviceHandle = smDeviceHandle; + satIOContext->smScsiXchg = smSCSIRequest; + satIOContext->superIOFlag = agFALSE; + + satIOContext->satIntIoContext = agNULL; + satIOContext->satOrgIOContext = agNULL; + satIOContext->currentLBA = 0; + satIOContext->OrgTL = 0; + + status = smsatIOStart(smRoot, smIORequest, smDeviceHandle, smSCSIRequest, satIOContext); + + return status; + +} + + + +osGLOBAL bit32 +smTaskManagement( + smRoot_t *smRoot, + smDeviceHandle_t *smDeviceHandle, + bit32 task, + smLUN_t *lun, + smIORequest_t *taskTag, /* io to be aborted */ + smIORequest_t *currentTaskTag /* task management */ + ) +{ + smIntRoot_t *smIntRoot = (smIntRoot_t *)smRoot->smData; + smIntContext_t *smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + agsaRoot_t *agRoot = smAllShared->agRoot; + smDeviceData_t *oneDeviceData = agNULL; + smIORequestBody_t *smIORequestBody = agNULL; + bit32 status; + agsaContext_t *agContext = agNULL; + smSatIOContext_t *satIOContext; + + SM_DBG1(("smTaskManagement: start\n")); + oneDeviceData = (smDeviceData_t *)smDeviceHandle->smData; + + if (task == SM_LOGICAL_UNIT_RESET || task == SM_TARGET_WARM_RESET || task == SM_ABORT_TASK) + { + if (task == AG_LOGICAL_UNIT_RESET) + { + if ( (lun->lun[0] | lun->lun[1] | lun->lun[2] | lun->lun[3] | + lun->lun[4] | lun->lun[5] | lun->lun[6] | lun->lun[7] ) != 0 ) + { + SM_DBG1(("smTaskManagement: *** REJECT *** LUN not zero, did %d!!!\n", + oneDeviceData->id)); + return SM_RC_FAILURE; + } + } + + oneDeviceData->satDriveState = SAT_DEV_STATE_IN_RECOVERY; + oneDeviceData->satAbortAfterReset = agFALSE; + + saSetDeviceState(agRoot, + agNULL, + tdsmRotateQnumber(smRoot, smDeviceHandle), + oneDeviceData->agDevHandle, + SA_DS_IN_RECOVERY + ); + + if (oneDeviceData->directlyAttached == agFALSE) + { + /* expander attached */ + SM_DBG1(("smTaskManagement: LUN reset or device reset expander attached!!!\n")); + status = smPhyControlSend(smRoot, + oneDeviceData, + SMP_PHY_CONTROL_HARD_RESET, + currentTaskTag, + tdsmRotateQnumber(smRoot, smDeviceHandle) + ); + return status; + } + else + { + SM_DBG1(("smTaskManagement: LUN reset or device reset directly attached\n")); + + smIORequestBody = (smIORequestBody_t*)currentTaskTag->smData;//smDequeueIO(smRoot); + + if (smIORequestBody == agNULL) + { + SM_DBG1(("smTaskManagement: smIORequestBody is NULL!!!\n")); + return SM_RC_FAILURE; + } + + smIOReInit(smRoot, smIORequestBody); + + satIOContext = &(smIORequestBody->transport.SATA.satIOContext); + satIOContext->smRequestBody = smIORequestBody; + smIORequestBody->smDevHandle = smDeviceHandle; + + agContext = &(oneDeviceData->agDeviceResetContext); + agContext->osData = currentTaskTag; + + status = saLocalPhyControl(agRoot, + agContext, + tdsmRotateQnumber(smRoot, smDeviceHandle) &0xFFFF, + oneDeviceData->phyID, + AGSA_PHY_HARD_RESET, + smLocalPhyControlCB + ); + + if ( status == AGSA_RC_SUCCESS) + { + return SM_RC_SUCCESS; + } + else if (status == AGSA_RC_BUSY) + { + return SM_RC_BUSY; + } + else if (status == AGSA_RC_FAILURE) + { + return SM_RC_FAILURE; + } + else + { + SM_DBG1(("smTaskManagement: unknown status %d\n",status)); + return SM_RC_FAILURE; + } + } + } + else + { + /* smsatsmTaskManagement() which is satTM() */ + smIORequestBody = (smIORequestBody_t*)currentTaskTag->smData;//smDequeueIO(smRoot); + + if (smIORequestBody == agNULL) + { + SM_DBG1(("smTaskManagement: smIORequestBody is NULL!!!\n")); + return SM_RC_FAILURE; + } + + smIOReInit(smRoot, smIORequestBody); + /*currentTaskTag->smData = smIORequestBody;*/ + + status = smsatTaskManagement(smRoot, + smDeviceHandle, + task, + lun, + taskTag, + currentTaskTag, + smIORequestBody + ); + + return status; + } + return SM_RC_SUCCESS; +} + + + +/********************************************************* end smapi defined APIS */ +/* counterpart is + smEnqueueIO(smRoot_t *smRoot, + smSatIOContext_t *satIOContext) +*/ +osGLOBAL smIORequestBody_t * +smDequeueIO(smRoot_t *smRoot) +{ + smIntRoot_t *smIntRoot = (smIntRoot_t *)smRoot->smData; + smIntContext_t *smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + smIORequestBody_t *smIORequestBody = agNULL; + smList_t *IOListList; + + SM_DBG2(("smDequeueIO: start\n")); + + tdsmSingleThreadedEnter(smRoot, SM_EXTERNAL_IO_LOCK); + if (SMLIST_EMPTY(&(smAllShared->freeIOList))) + { + SM_DBG1(("smDequeueIO: empty freeIOList!!!\n")); + tdsmSingleThreadedLeave(smRoot, SM_EXTERNAL_IO_LOCK); + return agNULL; + } + + SMLIST_DEQUEUE_FROM_HEAD(&IOListList, &(smAllShared->freeIOList)); + smIORequestBody = SMLIST_OBJECT_BASE(smIORequestBody_t, satIoBodyLink, IOListList); + SMLIST_DEQUEUE_THIS(&(smIORequestBody->satIoBodyLink)); + SMLIST_ENQUEUE_AT_TAIL(&(smIORequestBody->satIoBodyLink), &(smAllShared->mainIOList)); + tdsmSingleThreadedLeave(smRoot, SM_EXTERNAL_IO_LOCK); + + if (smIORequestBody->InUse == agTRUE) + { + SM_DBG1(("smDequeueIO: wrong. already in USE ID %d!!!!\n", smIORequestBody->id)); + } + smIOReInit(smRoot, smIORequestBody); + + + SM_DBG2(("smDequeueIO: io ID %d!\n", smIORequestBody->id)); + + /* debugging */ + if (smIORequestBody->satIoBodyLink.flink == agNULL) + { + SM_DBG1(("smDequeueIO: io ID %d, flink is NULL!!!\n", smIORequestBody->id)); + } + if (smIORequestBody->satIoBodyLink.blink == agNULL) + { + SM_DBG1(("smDequeueIO: io ID %d, blink is NULL!!!\n", smIORequestBody->id)); + } + + return smIORequestBody; +} + +//start here +//compare with ossaSATAAbortCB() +//qqq1 +osGLOBAL void +smsatAbort( + smRoot_t *smRoot, + agsaRoot_t *agRoot, + smSatIOContext_t *satIOContext + ) +{ + smIORequestBody_t *smIORequestBody = agNULL; /* abort itself */ + smIORequestBody_t *smToBeAbortedIORequestBody; /* io to be aborted */ + agsaIORequest_t *agToBeAbortedIORequest; /* io to be aborted */ + agsaIORequest_t *agAbortIORequest; /* abort io itself */ + smSatIOContext_t *satAbortIOContext; + bit32 PhysUpper32; + bit32 PhysLower32; + bit32 memAllocStatus; + void *osMemHandle; + + + SM_DBG2(("smsatAbort: start\n")); + + if (satIOContext == agNULL) + { + SM_DBG1(("smsatAbort: satIOContext is NULL, wrong!!!\n")); + return; + } + + smToBeAbortedIORequestBody = (smIORequestBody_t *)satIOContext->smRequestBody; + agToBeAbortedIORequest = (agsaIORequest_t *)&(smToBeAbortedIORequestBody->agIORequest); + /* + smIORequestBody = smDequeueIO(smRoot); + + if (smIORequestBody == agNULL) + { + SM_DBG1(("smsatAbort: empty freeIOList!!!\n")); + return; + } + */ + /* allocating agIORequest for abort itself */ + memAllocStatus = tdsmAllocMemory( + smRoot, + &osMemHandle, + (void **)&smIORequestBody, + &PhysUpper32, + &PhysLower32, + 8, + sizeof(smIORequestBody_t), + agTRUE + ); + if (memAllocStatus != tiSuccess) + { + /* let os process IO */ + SM_DBG1(("smsatAbort: ostiAllocMemory failed...\n")); + return; + } + + if (smIORequestBody == agNULL) + { + /* let os process IO */ + SM_DBG1(("smsatAbort: ostiAllocMemory returned NULL smIORequestBody\n")); + return; + } + smIOReInit(smRoot, smIORequestBody); + + smIORequestBody->IOType.InitiatorTMIO.osMemHandle = osMemHandle; + smIORequestBody->smDevHandle = smToBeAbortedIORequestBody->smDevHandle; + /* initialize agIORequest */ + satAbortIOContext = &(smIORequestBody->transport.SATA.satIOContext); + satAbortIOContext->smRequestBody = smIORequestBody; + + agAbortIORequest = &(smIORequestBody->agIORequest); + agAbortIORequest->osData = (void *) smIORequestBody; + agAbortIORequest->sdkData = agNULL; /* LL takes care of this */ + + /* + * Issue abort + */ + saSATAAbort( agRoot, agAbortIORequest, 0, agNULL, 0, agToBeAbortedIORequest, smaSATAAbortCB); + + + SM_DBG1(("satAbort: end!!!\n")); + + return; +} + +osGLOBAL bit32 +smsatStartCheckPowerMode( + smRoot_t *smRoot, + smIORequest_t *currentTaskTag, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + smSatInternalIo_t *satIntIo = agNULL; + smDeviceData_t *oneDeviceData = agNULL; + smSatIOContext_t *satNewIOContext; + bit32 status; + + SM_DBG1(("smsatStartCheckPowerMode: start\n")); + + oneDeviceData = satIOContext->pSatDevData; + + SM_DBG6(("smsatStartCheckPowerMode: before alloc\n")); + + /* allocate any fis for seting SRT bit in device control */ + satIntIo = smsatAllocIntIoResource( smRoot, + currentTaskTag, + oneDeviceData, + 0, + satIntIo); + + SM_DBG6(("smsatStartCheckPowerMode: before after\n")); + + if (satIntIo == agNULL) + { + SM_DBG1(("smsatStartCheckPowerMode: can't alloacate!!!\n")); + /*smEnqueueIO(smRoot, satIOContext);*/ + return SM_RC_FAILURE; + } + + satNewIOContext = smsatPrepareNewIO(satIntIo, + currentTaskTag, + oneDeviceData, + agNULL, + satIOContext); + + SM_DBG6(("smsatStartCheckPowerMode: TD satIOContext %p \n", satIOContext)); + SM_DBG6(("smsatStartCheckPowerMode: SM satNewIOContext %p \n", satNewIOContext)); + SM_DBG6(("smsatStartCheckPowerMode: TD smScsiXchg %p \n", satIOContext->smScsiXchg)); + SM_DBG6(("smsatStartCheckPowerMode: SM smScsiXchg %p \n", satNewIOContext->smScsiXchg)); + + + + SM_DBG2(("smsatStartCheckPowerMode: satNewIOContext %p \n", satNewIOContext)); + + status = smsatCheckPowerMode(smRoot, + &satIntIo->satIntSmIORequest, /* New smIORequest */ + smDeviceHandle, + satNewIOContext->smScsiXchg, /* New tiScsiInitiatorRequest_t *smScsiRequest, */ + satNewIOContext); + + if (status != SM_RC_SUCCESS) + { + SM_DBG1(("smsatStartCheckPowerMode: failed in sending!!!\n")); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + return SM_RC_FAILURE; + } + + + SM_DBG6(("smsatStartCheckPowerMode: end\n")); + + return status; +} + +osGLOBAL bit32 +smsatStartResetDevice( + smRoot_t *smRoot, + smIORequest_t *currentTaskTag, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + smSatInternalIo_t *satIntIo = agNULL; + smDeviceData_t *oneDeviceData = agNULL; + smSatIOContext_t *satNewIOContext; + bit32 status; + + SM_DBG1(("smsatStartResetDevice: start\n")); + + oneDeviceData = satIOContext->pSatDevData; + + SM_DBG6(("smsatStartResetDevice: before alloc\n")); + + /* allocate any fis for seting SRT bit in device control */ + satIntIo = smsatAllocIntIoResource( smRoot, + currentTaskTag, + oneDeviceData, + 0, + satIntIo); + + SM_DBG6(("smsatStartResetDevice: before after\n")); + + if (satIntIo == agNULL) + { + SM_DBG1(("smsatStartResetDevice: can't alloacate!!!\n")); + /*smEnqueueIO(smRoot, satIOContext);*/ + return SM_RC_FAILURE; + } + + satNewIOContext = smsatPrepareNewIO(satIntIo, + currentTaskTag, + oneDeviceData, + agNULL, + satIOContext); + + SM_DBG6(("smsatStartResetDevice: TD satIOContext %p \n", satIOContext)); + SM_DBG6(("smsatStartResetDevice: SM satNewIOContext %p \n", satNewIOContext)); + SM_DBG6(("smsatStartResetDevice: TD smScsiXchg %p \n", satIOContext->smScsiXchg)); + SM_DBG6(("smsatStartResetDevice: SM smScsiXchg %p \n", satNewIOContext->smScsiXchg)); + + + + SM_DBG6(("smsatStartResetDevice: satNewIOContext %p \n", satNewIOContext)); + + if (oneDeviceData->satDeviceType == SATA_ATAPI_DEVICE) + { + /*if ATAPI device, send DEVICE RESET command to ATAPI device*/ + status = smsatDeviceReset(smRoot, + &satIntIo->satIntSmIORequest, /* New smIORequest */ + smDeviceHandle, + satNewIOContext->smScsiXchg, /* New smScsiInitiatorRequest_t *smScsiRequest, NULL */ + satNewIOContext); + } + else + { + status = smsatResetDevice(smRoot, + &satIntIo->satIntSmIORequest, /* New smIORequest */ + smDeviceHandle, + satNewIOContext->smScsiXchg, /* New smScsiInitiatorRequest_t *smScsiRequest, NULL */ + satNewIOContext); + } + + if (status != SM_RC_SUCCESS) + { + SM_DBG1(("smsatStartResetDevice: failed in sending!!!\n")); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + return SM_RC_FAILURE; + } + + + SM_DBG6(("smsatStartResetDevice: end\n")); + + return status; +} + +osGLOBAL bit32 +smsatTmAbortTask( + smRoot_t *smRoot, + smIORequest_t *currentTaskTag, /* task management */ + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, /* NULL */ + smSatIOContext_t *satIOContext, /* task management */ + smIORequest_t *taskTag) /* io to be aborted */ +{ + smDeviceData_t *oneDeviceData = agNULL; + smSatIOContext_t *satTempIOContext = agNULL; + smList_t *elementHdr; + bit32 found = agFALSE; + smIORequestBody_t *smIORequestBody = agNULL; + smIORequest_t *smIOReq = agNULL; + bit32 status; + + SM_DBG1(("smsatTmAbortTask: start\n")); + + oneDeviceData = (smDeviceData_t *)smDeviceHandle->smData; + + /* + * Check that the only pending I/O matches taskTag. If not return tiError. + */ + tdsmSingleThreadedEnter(smRoot, SM_EXTERNAL_IO_LOCK); + + elementHdr = oneDeviceData->satIoLinkList.flink; + + while (elementHdr != &oneDeviceData->satIoLinkList) + { + satTempIOContext = SMLIST_OBJECT_BASE( smSatIOContext_t, + satIoContextLink, + elementHdr ); + + if ( satTempIOContext != agNULL) + { + smIORequestBody = (smIORequestBody_t *) satTempIOContext->smRequestBody; + smIOReq = smIORequestBody->smIORequest; + } + + elementHdr = elementHdr->flink; /* for the next while loop */ + + /* + * Check if the tag matches + */ + if ( smIOReq == taskTag) + { + found = agTRUE; + satIOContext->satToBeAbortedIOContext = satTempIOContext; + SM_DBG1(("smsatTmAbortTask: found matching tag.\n")); + + break; + + } /* if matching tag */ + + } /* while loop */ + + tdsmSingleThreadedLeave(smRoot, SM_EXTERNAL_IO_LOCK); + + if (found == agFALSE ) + { + SM_DBG1(("smsatTmAbortTask: *** REJECT *** no match!!!\n")); + + /*smEnqueueIO(smRoot, satIOContext);*/ + /* clean up TD layer's smIORequestBody */ + if (smIORequestBody) + { + if (smIORequestBody->IOType.InitiatorTMIO.osMemHandle != agNULL) + { + tdsmFreeMemory( + smRoot, + smIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(smIORequestBody_t) + ); + } + } + else + { + SM_DBG1(("smsatTmAbortTask: smIORequestBody is NULL!!!\n")); + } + + return SM_RC_FAILURE; + } + + if (satTempIOContext == agNULL) + { + SM_DBG1(("smsatTmAbortTask: satTempIOContext is NULL!!!\n")); + return SM_RC_FAILURE; + } + + /* + * Save smIORequest, will be returned at device reset completion to return + * the TM completion. + */ + oneDeviceData->satTmTaskTag = currentTaskTag; + + /* + * Set flag to indicate device in recovery mode. + */ + oneDeviceData->satDriveState = SAT_DEV_STATE_IN_RECOVERY; + + + /* + * Issue SATA device reset or check power mode.. Set flag to to automatically abort + * at the completion of SATA device reset. + * SAT r09 p25 + */ + oneDeviceData->satAbortAfterReset = agTRUE; + + if ( (satTempIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_WRITE) || + (satTempIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_READ) + ) + { + SM_DBG1(("smsatTmAbortTask: calling satStartCheckPowerMode!!!\n")); + /* send check power mode */ + status = smsatStartCheckPowerMode( + smRoot, + currentTaskTag, /* currentTaskTag */ + smDeviceHandle, + smScsiRequest, /* NULL */ + satIOContext + ); + } + else + { + SM_DBG1(("smsatTmAbortTask: calling satStartResetDevice!!!\n")); + /* send AGSA_SATA_PROTOCOL_SRST_ASSERT */ + status = smsatStartResetDevice( + smRoot, + currentTaskTag, /* currentTaskTag */ + smDeviceHandle, + smScsiRequest, /* NULL */ + satIOContext + ); + } + return status; +} + +/* satTM() */ +osGLOBAL bit32 +smsatTaskManagement( + smRoot_t *smRoot, + smDeviceHandle_t *smDeviceHandle, + bit32 task, + smLUN_t *lun, + smIORequest_t *taskTag, /* io to be aborted */ + smIORequest_t *currentTaskTag, /* task management */ + smIORequestBody_t *smIORequestBody + ) +{ + smSatIOContext_t *satIOContext = agNULL; + smDeviceData_t *oneDeviceData = agNULL; + bit32 status; + + SM_DBG1(("smsatTaskManagement: start\n")); + oneDeviceData = (smDeviceData_t *)smDeviceHandle->smData; + + satIOContext = &(smIORequestBody->transport.SATA.satIOContext); + + satIOContext->pSatDevData = oneDeviceData; + satIOContext->pFis = + &(smIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev); + + + satIOContext->smRequestBody = smIORequestBody; + satIOContext->psmDeviceHandle = smDeviceHandle; + satIOContext->satIntIoContext = agNULL; + satIOContext->satOrgIOContext = agNULL; + + /* followings are used only for internal IO */ + satIOContext->currentLBA = 0; + satIOContext->OrgTL = 0; + + /* saving task in satIOContext */ + satIOContext->TMF = task; + + satIOContext->satToBeAbortedIOContext = agNULL; + + if (task == AG_ABORT_TASK) + { + status = smsatTmAbortTask( smRoot, + currentTaskTag, + smDeviceHandle, + agNULL, + satIOContext, + taskTag); + + return status; + } + else + { + SM_DBG1(("smsatTaskManagement: UNSUPPORTED TM task=0x%x!!!\n", task )); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + return SM_RC_FAILURE; + } + + return SM_RC_SUCCESS; +} + + +osGLOBAL bit32 +smPhyControlSend( + smRoot_t *smRoot, + smDeviceData_t *oneDeviceData, /* sata disk itself */ + bit8 phyOp, + smIORequest_t *CurrentTaskTag, + bit32 queueNumber + ) +{ + smIntRoot_t *smIntRoot = (smIntRoot_t *)smRoot->smData; + smIntContext_t *smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + agsaRoot_t *agRoot = smAllShared->agRoot; + agsaDevHandle_t *agExpDevHandle; + smpReqPhyControl_t smpPhyControlReq; + void *osMemHandle; + bit32 PhysUpper32; + bit32 PhysLower32; + bit32 memAllocStatus; + bit32 expectedRspLen = 0; + smSMPRequestBody_t *smSMPRequestBody; + agsaSASRequestBody_t *agSASRequestBody; + agsaSMPFrame_t *agSMPFrame; + agsaIORequest_t *agIORequest; +// agsaDevHandle_t *agDevHandle; + smSMPFrameHeader_t smSMPFrameHeader; + bit32 status; + bit8 *pSmpBody; /* smp payload itself w/o first 4 bytes(header) */ + bit32 smpBodySize; /* smp payload size w/o first 4 bytes(header) */ + bit32 agRequestType; + + SM_DBG2(("smPhyControlSend: start\n")); + + agExpDevHandle = oneDeviceData->agExpDevHandle; + + if (agExpDevHandle == agNULL) + { + SM_DBG1(("smPhyControlSend: agExpDevHandle is NULL!!!\n")); + return SM_RC_FAILURE; + } + + SM_DBG5(("smPhyControlSend: phyID %d\n", oneDeviceData->phyID)); + + sm_memset(&smpPhyControlReq, 0, sizeof(smpReqPhyControl_t)); + + /* fill in SMP payload */ + smpPhyControlReq.phyIdentifier = (bit8)oneDeviceData->phyID; + smpPhyControlReq.phyOperation = phyOp; + + /* allocate smp and send it */ + memAllocStatus = tdsmAllocMemory( + smRoot, + &osMemHandle, + (void **)&smSMPRequestBody, + &PhysUpper32, + &PhysLower32, + 8, + sizeof(smSMPRequestBody_t), + agTRUE + ); + + if (memAllocStatus != SM_RC_SUCCESS) + { + SM_DBG1(("smPhyControlSend: tdsmAllocMemory failed...!!!\n")); + return SM_RC_FAILURE; + } + + if (smSMPRequestBody == agNULL) + { + SM_DBG1(("smPhyControlSend: tdsmAllocMemory returned NULL smSMPRequestBody!!!\n")); + return SM_RC_FAILURE; + } + + /* saves mem handle for freeing later */ + smSMPRequestBody->osMemHandle = osMemHandle; + + /* saves oneDeviceData */ + smSMPRequestBody->smDeviceData = oneDeviceData; /* sata disk */ + + /* saves oneDeviceData */ + smSMPRequestBody->smDevHandle = oneDeviceData->smDevHandle; + +// agDevHandle = oneDeviceData->agDevHandle; + + /* save the callback funtion */ + smSMPRequestBody->SMPCompletionFunc = smSMPCompleted; /* in satcb.c */ + + /* for simulate warm target reset */ + smSMPRequestBody->CurrentTaskTag = CurrentTaskTag; + + if (CurrentTaskTag != agNULL) + { + CurrentTaskTag->smData = smSMPRequestBody; + } + + /* initializes the number of SMP retries */ + smSMPRequestBody->retries = 0; + +#ifdef TD_INTERNAL_DEBUG /* debugging */ + SM_DBG4(("smPhyControlSend: SMPRequestbody %p\n", smSMPRequestBody)); + SM_DBG4(("smPhyControlSend: callback fn %p\n", smSMPRequestBody->SMPCompletionFunc)); +#endif + + agIORequest = &(smSMPRequestBody->agIORequest); + agIORequest->osData = (void *) smSMPRequestBody; + agIORequest->sdkData = agNULL; /* SALL takes care of this */ + + + agSASRequestBody = &(smSMPRequestBody->agSASRequestBody); + agSMPFrame = &(agSASRequestBody->smpFrame); + + SM_DBG3(("smPhyControlSend: agIORequest %p\n", agIORequest)); + SM_DBG3(("smPhyControlSend: SMPRequestbody %p\n", smSMPRequestBody)); + + expectedRspLen = 4; + + pSmpBody = (bit8 *)&smpPhyControlReq; + smpBodySize = sizeof(smpReqPhyControl_t); + agRequestType = AGSA_SMP_INIT_REQ; + + if (SMIsSPC(agRoot)) + { + if ( (smpBodySize + 4) <= SMP_DIRECT_PAYLOAD_LIMIT) /* 48 */ + { + SM_DBG3(("smPhyControlSend: DIRECT smp payload\n")); + sm_memset(&smSMPFrameHeader, 0, sizeof(smSMPFrameHeader_t)); + sm_memset(smSMPRequestBody->smpPayload, 0, SMP_DIRECT_PAYLOAD_LIMIT); + + /* SMP header */ + smSMPFrameHeader.smpFrameType = SMP_REQUEST; /* SMP request */ + smSMPFrameHeader.smpFunction = (bit8)SMP_PHY_CONTROL; + smSMPFrameHeader.smpFunctionResult = 0; + smSMPFrameHeader.smpReserved = 0; + + sm_memcpy(smSMPRequestBody->smpPayload, &smSMPFrameHeader, 4); + sm_memcpy((smSMPRequestBody->smpPayload)+4, pSmpBody, smpBodySize); + + /* direct SMP payload eg) REPORT_GENERAL, DISCOVER etc */ + agSMPFrame->outFrameBuf = smSMPRequestBody->smpPayload; + agSMPFrame->outFrameLen = smpBodySize + 4; /* without last 4 byte crc */ + /* to specify DIRECT SMP response */ + agSMPFrame->inFrameLen = 0; + + /* temporary solution for T2D Combo*/ +#if defined (INITIATOR_DRIVER) && defined (TARGET_DRIVER) + /* force smp repsonse to be direct */ + agSMPFrame->expectedRespLen = 0; +#else + agSMPFrame->expectedRespLen = expectedRspLen; +#endif + // smhexdump("smPhyControlSend", (bit8*)agSMPFrame->outFrameBuf, agSMPFrame->outFrameLen); + // smhexdump("smPhyControlSend new", (bit8*)smSMPRequestBody->smpPayload, agSMPFrame->outFrameLen); + // smhexdump("smPhyControlSend - smSMPRequestBody", (bit8*)smSMPRequestBody, sizeof(smSMPRequestBody_t)); + } + else + { + SM_DBG1(("smPhyControlSend: INDIRECT smp payload, not supported!!!\n")); + tdsmFreeMemory( + smRoot, + osMemHandle, + sizeof(smSMPRequestBody_t) + ); + + return SM_RC_FAILURE; + } + } + else /* SPCv controller */ + { + /* only direct mode for both request and response */ + SM_DBG3(("smPhyControlSend: DIRECT smp payload\n")); + agSMPFrame->flag = 0; + sm_memset(&smSMPFrameHeader, 0, sizeof(smSMPFrameHeader_t)); + sm_memset(smSMPRequestBody->smpPayload, 0, SMP_DIRECT_PAYLOAD_LIMIT); + + /* SMP header */ + smSMPFrameHeader.smpFrameType = SMP_REQUEST; /* SMP request */ + smSMPFrameHeader.smpFunction = (bit8)SMP_PHY_CONTROL; + smSMPFrameHeader.smpFunctionResult = 0; + smSMPFrameHeader.smpReserved = 0; + + sm_memcpy(smSMPRequestBody->smpPayload, &smSMPFrameHeader, 4); + sm_memcpy((smSMPRequestBody->smpPayload)+4, pSmpBody, smpBodySize); + + /* direct SMP payload eg) REPORT_GENERAL, DISCOVER etc */ + agSMPFrame->outFrameBuf = smSMPRequestBody->smpPayload; + agSMPFrame->outFrameLen = smpBodySize + 4; /* without last 4 byte crc */ + /* to specify DIRECT SMP response */ + agSMPFrame->inFrameLen = 0; + + /* temporary solution for T2D Combo*/ +#if defined (INITIATOR_DRIVER) && defined (TARGET_DRIVER) + /* force smp repsonse to be direct */ + agSMPFrame->expectedRespLen = 0; +#else + agSMPFrame->expectedRespLen = expectedRspLen; +#endif +// smhexdump("smPhyControlSend", (bit8*)agSMPFrame->outFrameBuf, agSMPFrame->outFrameLen); +// smhexdump("smPhyControlSend new", (bit8*)smSMPRequestBody->smpPayload, agSMPFrame->outFrameLen); +// smhexdump("smPhyControlSend - smSMPRequestBody", (bit8*)smSMPRequestBody, sizeof(smSMPRequestBody_t)); + } + + status = saSMPStart( + agRoot, + agIORequest, + queueNumber, + agExpDevHandle, + agRequestType, + agSASRequestBody, + &smSMPCompletedCB + ); + + if (status == AGSA_RC_SUCCESS) + { + return SM_RC_SUCCESS; + } + else if (status == AGSA_RC_BUSY) + { + SM_DBG1(("smPhyControlSend: saSMPStart is busy!!!\n")); + tdsmFreeMemory( + smRoot, + osMemHandle, + sizeof(smSMPRequestBody_t) + ); + + return SM_RC_BUSY; + } + else /* AGSA_RC_FAILURE */ + { + SM_DBG1(("smPhyControlSend: saSMPStart is failed. status %d!!!\n", status)); + tdsmFreeMemory( + smRoot, + osMemHandle, + sizeof(smSMPRequestBody_t) + ); + + return SM_RC_FAILURE; + } +} + +/* free IO which are internally completed within SM + counterpart is + osGLOBAL smIORequestBody_t * + smDequeueIO(smRoot_t *smRoot) +*/ +osGLOBAL void +smEnqueueIO( + smRoot_t *smRoot, + smSatIOContext_t *satIOContext + ) +{ + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + + SM_DBG3(("smEnqueueIO: start\n")); + smIORequestBody = (smIORequestBody_t *)satIOContext->smRequestBody; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + + /* enque back to smAllShared->freeIOList */ + if (satIOContext->satIntIoContext == agNULL) + { + SM_DBG2(("smEnqueueIO: external command!!!, io ID %d!!!\n", smIORequestBody->id)); + /* debugging only */ + if (smIORequestBody->satIoBodyLink.flink == agNULL) + { + SM_DBG1(("smEnqueueIO: external command!!!, io ID %d, flink is NULL!!!\n", smIORequestBody->id)); + } + if (smIORequestBody->satIoBodyLink.blink == agNULL) + { + SM_DBG1(("smEnqueueIO: external command!!!, io ID %d, blink is NULL!!!\n", smIORequestBody->id)); + } + } + else + { + SM_DBG2(("smEnqueueIO: internal command!!!, io ID %d!!!\n", smIORequestBody->id)); + /* debugging only */ + if (smIORequestBody->satIoBodyLink.flink == agNULL) + { + SM_DBG1(("smEnqueueIO: internal command!!!, io ID %d, flink is NULL!!!\n", smIORequestBody->id)); + } + if (smIORequestBody->satIoBodyLink.blink == agNULL) + { + SM_DBG1(("smEnqueueIO: internal command!!!, io ID %d, blink is NULL!!!\n", smIORequestBody->id)); + } + } + + if (smIORequestBody->smIORequest == agNULL) + { + SM_DBG1(("smEnqueueIO: smIORequest is NULL, io ID %d!!!\n", smIORequestBody->id)); + } + + if (smIORequestBody->InUse == agTRUE) + { + smIORequestBody->InUse = agFALSE; + tdsmSingleThreadedEnter(smRoot, SM_EXTERNAL_IO_LOCK); + SMLIST_DEQUEUE_THIS(&(smIORequestBody->satIoBodyLink)); + SMLIST_ENQUEUE_AT_TAIL(&(smIORequestBody->satIoBodyLink), &(smAllShared->freeIOList)); + tdsmSingleThreadedLeave(smRoot, SM_EXTERNAL_IO_LOCK); + } + else + { + SM_DBG2(("smEnqueueIO: check!!!, io ID %d!!!\n", smIORequestBody->id)); + } + + + return; +} + +FORCEINLINE void +smsatFreeIntIoResource( + smRoot_t *smRoot, + smDeviceData_t *satDevData, + smSatInternalIo_t *satIntIo + ) +{ + SM_DBG3(("smsatFreeIntIoResource: start\n")); + + if (satIntIo == agNULL) + { + SM_DBG2(("smsatFreeIntIoResource: allowed call\n")); + return; + } + + /* sets the original smIOrequest to agNULL for internally generated ATA cmnd */ + satIntIo->satOrgSmIORequest = agNULL; + + /* + * Free DMA memory if previosly alocated + */ + if (satIntIo->satIntSmScsiXchg.scsiCmnd.expDataLength != 0) + { + SM_DBG3(("smsatFreeIntIoResource: DMA len %d\n", satIntIo->satIntDmaMem.totalLength)); + SM_DBG3(("smsatFreeIntIoResource: pointer %p\n", satIntIo->satIntDmaMem.osHandle)); + + tdsmFreeMemory( smRoot, + satIntIo->satIntDmaMem.osHandle, + satIntIo->satIntDmaMem.totalLength); + satIntIo->satIntSmScsiXchg.scsiCmnd.expDataLength = 0; + } + + if (satIntIo->satIntReqBodyMem.totalLength != 0) + { + SM_DBG3(("smsatFreeIntIoResource: req body len %d\n", satIntIo->satIntReqBodyMem.totalLength)); + /* + * Free mem allocated for Req body + */ + tdsmFreeMemory( smRoot, + satIntIo->satIntReqBodyMem.osHandle, + satIntIo->satIntReqBodyMem.totalLength); + + satIntIo->satIntReqBodyMem.totalLength = 0; + } + + SM_DBG3(("smsatFreeIntIoResource: satDevData %p satIntIo id %d\n", satDevData, satIntIo->id)); + /* + * Return satIntIo to the free list + */ + tdsmSingleThreadedEnter(smRoot, SM_INTERNAL_IO_LOCK); + SMLIST_DEQUEUE_THIS (&(satIntIo->satIntIoLink)); + SMLIST_ENQUEUE_AT_TAIL (&(satIntIo->satIntIoLink), &(satDevData->satFreeIntIoLinkList)); + tdsmSingleThreadedLeave(smRoot, SM_INTERNAL_IO_LOCK); + + return; +} +//start here +osGLOBAL smSatInternalIo_t * +smsatAllocIntIoResource( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceData_t *satDevData, + bit32 dmaAllocLength, + smSatInternalIo_t *satIntIo) +{ + smList_t *smList = agNULL; + bit32 memAllocStatus; + + SM_DBG3(("smsatAllocIntIoResource: start\n")); + SM_DBG3(("smsatAllocIntIoResource: satIntIo %p\n", satIntIo)); + if (satDevData == agNULL) + { + SM_DBG1(("smsatAllocIntIoResource: ***** ASSERT satDevData is null!!!\n")); + return agNULL; + } + + tdsmSingleThreadedEnter(smRoot, SM_INTERNAL_IO_LOCK); + if (!SMLIST_EMPTY(&(satDevData->satFreeIntIoLinkList))) + { + SMLIST_DEQUEUE_FROM_HEAD(&smList, &(satDevData->satFreeIntIoLinkList)); + } + else + { + tdsmSingleThreadedLeave(smRoot, SM_INTERNAL_IO_LOCK); + SM_DBG1(("smsatAllocIntIoResource() no more internal free link!!!\n")); + return agNULL; + } + + if (smList == agNULL) + { + tdsmSingleThreadedLeave(smRoot, SM_INTERNAL_IO_LOCK); + SM_DBG1(("smsatAllocIntIoResource() FAIL to alloc satIntIo!!!\n")); + return agNULL; + } + + satIntIo = SMLIST_OBJECT_BASE( smSatInternalIo_t, satIntIoLink, smList); + SM_DBG3(("smsatAllocIntIoResource: satDevData %p satIntIo id %d\n", satDevData, satIntIo->id)); + + /* Put in active list */ + SMLIST_DEQUEUE_THIS (&(satIntIo->satIntIoLink)); + SMLIST_ENQUEUE_AT_TAIL (&(satIntIo->satIntIoLink), &(satDevData->satActiveIntIoLinkList)); + tdsmSingleThreadedLeave(smRoot, SM_INTERNAL_IO_LOCK); + +#ifdef REMOVED + /* Put in active list */ + tdsmSingleThreadedEnter(smRoot, SM_INTERNAL_IO_LOCK); + SMLIST_DEQUEUE_THIS (smList); + SMLIST_ENQUEUE_AT_TAIL (smList, &(satDevData->satActiveIntIoLinkList)); + tdsmSingleThreadedLeave(smRoot, SM_INTERNAL_IO_LOCK); + + satIntIo = SMLIST_OBJECT_BASE( smSatInternalIo_t, satIntIoLink, smList); + SM_DBG3(("smsatAllocIntIoResource: satDevData %p satIntIo id %d\n", satDevData, satIntIo->id)); +#endif + + /* + typedef struct + { + tdList_t satIntIoLink; + smIORequest_t satIntSmIORequest; + void *satIntRequestBody; + smScsiInitiatorRequest_t satIntSmScsiXchg; + smMem_t satIntDmaMem; + smMem_t satIntReqBodyMem; + bit32 satIntFlag; + } smSatInternalIo_t; + */ + + /* + * Allocate mem for Request Body + */ + satIntIo->satIntReqBodyMem.totalLength = sizeof(smIORequestBody_t); + + memAllocStatus = tdsmAllocMemory( smRoot, + &satIntIo->satIntReqBodyMem.osHandle, + (void **)&satIntIo->satIntRequestBody, + &satIntIo->satIntReqBodyMem.physAddrUpper, + &satIntIo->satIntReqBodyMem.physAddrLower, + 8, + satIntIo->satIntReqBodyMem.totalLength, + agTRUE ); + + if (memAllocStatus != SM_RC_SUCCESS) + { + SM_DBG1(("smsatAllocIntIoResource() FAIL to alloc mem for Req Body!!!\n")); + /* + * Return satIntIo to the free list + */ + tdsmSingleThreadedEnter(smRoot, SM_INTERNAL_IO_LOCK); + SMLIST_DEQUEUE_THIS (&satIntIo->satIntIoLink); + SMLIST_ENQUEUE_AT_HEAD(&satIntIo->satIntIoLink, &satDevData->satFreeIntIoLinkList); + tdsmSingleThreadedLeave(smRoot, SM_INTERNAL_IO_LOCK); + + return agNULL; + } + + /* + * Allocate DMA memory if required + */ + if (dmaAllocLength != 0) + { + satIntIo->satIntDmaMem.totalLength = dmaAllocLength; + + memAllocStatus = tdsmAllocMemory( smRoot, + &satIntIo->satIntDmaMem.osHandle, + (void **)&satIntIo->satIntDmaMem.virtPtr, + &satIntIo->satIntDmaMem.physAddrUpper, + &satIntIo->satIntDmaMem.physAddrLower, + 8, + satIntIo->satIntDmaMem.totalLength, + agFALSE); + SM_DBG3(("smsatAllocIntIoResource: len %d \n", satIntIo->satIntDmaMem.totalLength)); + SM_DBG3(("smsatAllocIntIoResource: pointer %p \n", satIntIo->satIntDmaMem.osHandle)); + + if (memAllocStatus != SM_RC_SUCCESS) + { + SM_DBG1(("smsatAllocIntIoResource() FAIL to alloc mem for DMA mem!!!\n")); + /* + * Return satIntIo to the free list + */ + tdsmSingleThreadedEnter(smRoot, SM_INTERNAL_IO_LOCK); + SMLIST_DEQUEUE_THIS (&satIntIo->satIntIoLink); + SMLIST_ENQUEUE_AT_HEAD(&satIntIo->satIntIoLink, &satDevData->satFreeIntIoLinkList); + tdsmSingleThreadedLeave(smRoot, SM_INTERNAL_IO_LOCK); + + /* + * Free mem allocated for Req body + */ + tdsmFreeMemory( smRoot, + satIntIo->satIntReqBodyMem.osHandle, + satIntIo->satIntReqBodyMem.totalLength); + + return agNULL; + } + } + + /* + typedef struct + { + smList_t satIntIoLink; + smIORequest_t satIntSmIORequest; + void *satIntRequestBody; + smScsiInitiatorRequest_t satIntSmScsiXchg; + smMem_t satIntDmaMem; + smMem_t satIntReqBodyMem; + bit32 satIntFlag; + } smSatInternalIo_t; + */ + + /* + * Initialize satIntSmIORequest field + */ + satIntIo->satIntSmIORequest.tdData = agNULL; /* Not used for internal SAT I/O */ + satIntIo->satIntSmIORequest.smData = satIntIo->satIntRequestBody; + + /* + * saves the original smIOrequest + */ + satIntIo->satOrgSmIORequest = smIORequest; + /* + typedef struct tiIniScsiCmnd + { + tiLUN_t lun; + bit32 expDataLength; + bit32 taskAttribute; + bit32 crn; + bit8 cdb[16]; + } tiIniScsiCmnd_t; + + typedef struct tiScsiInitiatorExchange + { + void *sglVirtualAddr; + tiIniScsiCmnd_t scsiCmnd; + tiSgl_t agSgl1; + tiSgl_t agSgl2; + tiDataDirection_t dataDirection; + } tiScsiInitiatorRequest_t; + + */ + + /* + * Initialize satIntSmScsiXchg. Since the internal SAT request is NOT + * originated from SCSI request, only the following fields are initialized: + * - sglVirtualAddr if DMA transfer is involved + * - agSgl1 if DMA transfer is involved + * - expDataLength in scsiCmnd since this field is read by smsataLLIOStart() + */ + if (dmaAllocLength != 0) + { + satIntIo->satIntSmScsiXchg.sglVirtualAddr = satIntIo->satIntDmaMem.virtPtr; + + OSSA_WRITE_LE_32(agNULL, &satIntIo->satIntSmScsiXchg.smSgl1.len, 0, + satIntIo->satIntDmaMem.totalLength); + satIntIo->satIntSmScsiXchg.smSgl1.lower = satIntIo->satIntDmaMem.physAddrLower; + satIntIo->satIntSmScsiXchg.smSgl1.upper = satIntIo->satIntDmaMem.physAddrUpper; + satIntIo->satIntSmScsiXchg.smSgl1.type = tiSgl; + + satIntIo->satIntSmScsiXchg.scsiCmnd.expDataLength = satIntIo->satIntDmaMem.totalLength; + } + else + { + satIntIo->satIntSmScsiXchg.sglVirtualAddr = agNULL; + + satIntIo->satIntSmScsiXchg.smSgl1.len = 0; + satIntIo->satIntSmScsiXchg.smSgl1.lower = 0; + satIntIo->satIntSmScsiXchg.smSgl1.upper = 0; + satIntIo->satIntSmScsiXchg.smSgl1.type = tiSgl; + + satIntIo->satIntSmScsiXchg.scsiCmnd.expDataLength = 0; + } + + SM_DBG5(("smsatAllocIntIoResource: satIntIo->satIntSmScsiXchg.agSgl1.len %d\n", satIntIo->satIntSmScsiXchg.smSgl1.len)); + + SM_DBG5(("smsatAllocIntIoResource: satIntIo->satIntSmScsiXchg.agSgl1.upper %d\n", satIntIo->satIntSmScsiXchg.smSgl1.upper)); + + SM_DBG5(("smsatAllocIntIoResource: satIntIo->satIntSmScsiXchg.agSgl1.lower %d\n", satIntIo->satIntSmScsiXchg.smSgl1.lower)); + + SM_DBG5(("smsatAllocIntIoResource: satIntIo->satIntSmScsiXchg.agSgl1.type %d\n", satIntIo->satIntSmScsiXchg.smSgl1.type)); + SM_DBG5(("smsatAllocIntIoResource: return satIntIo %p\n", satIntIo)); + return satIntIo; +} + +osGLOBAL smDeviceData_t * +smAddToSharedcontext( + smRoot_t *smRoot, + agsaDevHandle_t *agDevHandle, + smDeviceHandle_t *smDeviceHandle, + agsaDevHandle_t *agExpDevHandle, + bit32 phyID + ) +{ + smIntRoot_t *smIntRoot = (smIntRoot_t *)smRoot->smData; + smIntContext_t *smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + smDeviceData_t *oneDeviceData = agNULL; + smList_t *DeviceListList; + bit32 new_device = agTRUE; + + SM_DBG2(("smAddToSharedcontext: start\n")); + + /* find a device's existence */ + DeviceListList = smAllShared->MainDeviceList.flink; + while (DeviceListList != &(smAllShared->MainDeviceList)) + { + oneDeviceData = SMLIST_OBJECT_BASE(smDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + SM_DBG1(("smAddToSharedcontext: oneDeviceData is NULL!!!\n")); + return agNULL; + } + if (oneDeviceData->agDevHandle == agDevHandle) + { + SM_DBG2(("smAddToSharedcontext: did %d\n", oneDeviceData->id)); + new_device = agFALSE; + break; + } + DeviceListList = DeviceListList->flink; + } + + /* new device */ + if (new_device == agTRUE) + { + SM_DBG2(("smAddToSharedcontext: new device\n")); + tdsmSingleThreadedEnter(smRoot, SM_DEVICE_LOCK); + if (SMLIST_EMPTY(&(smAllShared->FreeDeviceList))) + { + tdsmSingleThreadedLeave(smRoot, SM_DEVICE_LOCK); + SM_DBG1(("smAddToSharedcontext: empty DeviceData FreeLink!!!\n")); + smDeviceHandle->smData = agNULL; + return agNULL; + } + + SMLIST_DEQUEUE_FROM_HEAD(&DeviceListList, &(smAllShared->FreeDeviceList)); + tdsmSingleThreadedLeave(smRoot, SM_DEVICE_LOCK); + oneDeviceData = SMLIST_OBJECT_BASE(smDeviceData_t, FreeLink, DeviceListList); + oneDeviceData->smRoot = smRoot; + oneDeviceData->agDevHandle = agDevHandle; + oneDeviceData->valid = agTRUE; + smDeviceHandle->smData = oneDeviceData; + oneDeviceData->smDevHandle = smDeviceHandle; + if (agExpDevHandle == agNULL) + { + oneDeviceData->directlyAttached = agTRUE; + } + else + { + oneDeviceData->directlyAttached = agFALSE; + } + oneDeviceData->agExpDevHandle = agExpDevHandle; + oneDeviceData->phyID = phyID; + oneDeviceData->satPendingIO = 0; + oneDeviceData->satPendingNCQIO = 0; + oneDeviceData->satPendingNONNCQIO = 0; + /* add the devicedata to the portcontext */ + tdsmSingleThreadedEnter(smRoot, SM_DEVICE_LOCK); + SMLIST_ENQUEUE_AT_TAIL(&(oneDeviceData->MainLink), &(smAllShared->MainDeviceList)); + tdsmSingleThreadedLeave(smRoot, SM_DEVICE_LOCK); + SM_DBG2(("smAddToSharedcontext: new case did %d\n", oneDeviceData->id)); + } + else + { + SM_DBG2(("smAddToSharedcontext: old device\n")); + oneDeviceData->smRoot = smRoot; + oneDeviceData->agDevHandle = agDevHandle; + oneDeviceData->valid = agTRUE; + smDeviceHandle->smData = oneDeviceData; + oneDeviceData->smDevHandle = smDeviceHandle; + if (agExpDevHandle == agNULL) + { + oneDeviceData->directlyAttached = agTRUE; + } + else + { + oneDeviceData->directlyAttached = agFALSE; + } + oneDeviceData->agExpDevHandle = agExpDevHandle; + oneDeviceData->phyID = phyID; + oneDeviceData->satPendingIO = 0; + oneDeviceData->satPendingNCQIO = 0; + oneDeviceData->satPendingNONNCQIO = 0; + SM_DBG2(("smAddToSharedcontext: old case did %d\n", oneDeviceData->id)); + } + + return oneDeviceData; +} + +osGLOBAL bit32 +smRemoveFromSharedcontext( + smRoot_t *smRoot, + agsaDevHandle_t *agDevHandle, + smDeviceHandle_t *smDeviceHandle + ) +{ + smIntRoot_t *smIntRoot = (smIntRoot_t *)smRoot->smData; + smIntContext_t *smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + smDeviceData_t *oneDeviceData = agNULL; + + SM_DBG2(("smRemoveFromSharedcontext: start\n")); + + //due to device all and completion + //smDeviceHandle->smData = agNULL; + + /* find oneDeviceData from MainLink */ + oneDeviceData = smFindInSharedcontext(smRoot, agDevHandle); + + if (oneDeviceData == agNULL) + { + return SM_RC_FAILURE; + } + else + { + if (oneDeviceData->valid == agTRUE) + { + smDeviceDataReInit(smRoot, oneDeviceData); + tdsmSingleThreadedEnter(smRoot, SM_DEVICE_LOCK); + SMLIST_DEQUEUE_THIS(&(oneDeviceData->MainLink)); + SMLIST_ENQUEUE_AT_TAIL(&(oneDeviceData->FreeLink), &(smAllShared->FreeDeviceList)); + tdsmSingleThreadedLeave(smRoot, SM_DEVICE_LOCK); + return SM_RC_SUCCESS; + } + else + { + SM_DBG1(("smRemoveFromSharedcontext: did %d bad case!!!\n", oneDeviceData->id)); + return SM_RC_FAILURE; + } + } + +} + +osGLOBAL smDeviceData_t * +smFindInSharedcontext( + smRoot_t *smRoot, + agsaDevHandle_t *agDevHandle + ) +{ + smIntRoot_t *smIntRoot = (smIntRoot_t *)smRoot->smData; + smIntContext_t *smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + smDeviceData_t *oneDeviceData = agNULL; + smList_t *DeviceListList; + + SM_DBG2(("smFindInSharedcontext: start\n")); + + tdsmSingleThreadedEnter(smRoot, SM_DEVICE_LOCK); + if (SMLIST_EMPTY(&(smAllShared->MainDeviceList))) + { + SM_DBG1(("smFindInSharedcontext: empty MainDeviceList!!!\n")); + tdsmSingleThreadedLeave(smRoot, SM_DEVICE_LOCK); + return agNULL; + } + else + { + tdsmSingleThreadedLeave(smRoot, SM_DEVICE_LOCK); + } + + DeviceListList = smAllShared->MainDeviceList.flink; + while (DeviceListList != &(smAllShared->MainDeviceList)) + { + oneDeviceData = SMLIST_OBJECT_BASE(smDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + SM_DBG1(("smFindInSharedcontext: oneDeviceData is NULL!!!\n")); + return agNULL; + } + if ((oneDeviceData->agDevHandle == agDevHandle) && + (oneDeviceData->valid == agTRUE) + ) + { + SM_DBG2(("smFindInSharedcontext: found, did %d\n", oneDeviceData->id)); + return oneDeviceData; + } + DeviceListList = DeviceListList->flink; + } + SM_DBG2(("smFindInSharedcontext: not found\n")); + return agNULL; +} + +osGLOBAL smSatIOContext_t * +smsatPrepareNewIO( + smSatInternalIo_t *satNewIntIo, + smIORequest_t *smOrgIORequest, + smDeviceData_t *satDevData, + smIniScsiCmnd_t *scsiCmnd, + smSatIOContext_t *satOrgIOContext + ) +{ + smSatIOContext_t *satNewIOContext; + smIORequestBody_t *smNewIORequestBody; + + SM_DBG3(("smsatPrepareNewIO: start\n")); + + /* the one to be used; good 8/2/07 */ + satNewIntIo->satOrgSmIORequest = smOrgIORequest; /* this is already done in + smsatAllocIntIoResource() */ + + smNewIORequestBody = (smIORequestBody_t *)satNewIntIo->satIntRequestBody; + satNewIOContext = &(smNewIORequestBody->transport.SATA.satIOContext); + + satNewIOContext->pSatDevData = satDevData; + satNewIOContext->pFis = &(smNewIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev); + satNewIOContext->pScsiCmnd = &(satNewIntIo->satIntSmScsiXchg.scsiCmnd); + if (scsiCmnd != agNULL) + { + /* saves only CBD; not scsi command for LBA and number of blocks */ + sm_memcpy(satNewIOContext->pScsiCmnd->cdb, scsiCmnd->cdb, 16); + } + satNewIOContext->pSense = &(smNewIORequestBody->transport.SATA.sensePayload); + satNewIOContext->pSmSenseData = &(smNewIORequestBody->transport.SATA.smSenseData); + satNewIOContext->pSmSenseData->senseData = satNewIOContext->pSense; + satNewIOContext->smRequestBody = satNewIntIo->satIntRequestBody; + satNewIOContext->interruptContext = satNewIOContext->interruptContext; + satNewIOContext->satIntIoContext = satNewIntIo; + satNewIOContext->psmDeviceHandle = satOrgIOContext->psmDeviceHandle; + satNewIOContext->satOrgIOContext = satOrgIOContext; + /* saves tiScsiXchg; only for writesame10() */ + satNewIOContext->smScsiXchg = satOrgIOContext->smScsiXchg; + + return satNewIOContext; +} + + +osGLOBAL void +smsatSetDevInfo( + smDeviceData_t *oneDeviceData, + agsaSATAIdentifyData_t *SATAIdData + ) +{ + SM_DBG3(("smsatSetDevInfo: start\n")); + + oneDeviceData->satDriveState = SAT_DEV_STATE_NORMAL; + oneDeviceData->satFormatState = agFALSE; + oneDeviceData->satDeviceFaultState = agFALSE; + oneDeviceData->satTmTaskTag = agNULL; + oneDeviceData->satAbortAfterReset = agFALSE; + oneDeviceData->satAbortCalled = agFALSE; + oneDeviceData->satSectorDone = 0; + + /* Qeueu depth, Word 75 */ + oneDeviceData->satNCQMaxIO = SATAIdData->queueDepth + 1; + SM_DBG3(("smsatSetDevInfo: max queue depth %d\n",oneDeviceData->satNCQMaxIO)); + + /* Support NCQ, if Word 76 bit 8 is set */ + if (SATAIdData->sataCapabilities & 0x100) + { + SM_DBG3(("smsatSetDevInfo: device supports NCQ\n")); + oneDeviceData->satNCQ = agTRUE; + } + else + { + SM_DBG3(("smsatSetDevInfo: no NCQ\n")); + oneDeviceData->satNCQ = agFALSE; + } + + /* Support 48 bit addressing, if Word 83 bit 10 and Word 86 bit 10 are set */ + if ((SATAIdData->commandSetSupported1 & 0x400) && + (SATAIdData->commandSetFeatureEnabled1 & 0x400) ) + { + SM_DBG3(("smsatSetDevInfo: support 48 bit addressing\n")); + oneDeviceData->sat48BitSupport = agTRUE; + } + else + { + SM_DBG3(("smsatSetDevInfo: NO 48 bit addressing\n")); + oneDeviceData->sat48BitSupport = agFALSE; + } + + /* Support SMART Self Test, word84 bit 1 */ + if (SATAIdData->commandSetFeatureSupportedExt & 0x02) + { + SM_DBG3(("smsatSetDevInfo: SMART self-test supported \n")); + oneDeviceData->satSMARTSelfTest = agTRUE; + } + else + { + SM_DBG3(("smsatSetDevInfo: no SMART self-test suppored\n")); + oneDeviceData->satSMARTSelfTest = agFALSE; + } + + /* Support SMART feature set, word82 bit 0 */ + if (SATAIdData->commandSetSupported & 0x01) + { + SM_DBG3(("smsatSetDevInfo: SMART feature set supported \n")); + oneDeviceData->satSMARTFeatureSet = agTRUE; + } + else + { + SM_DBG3(("smsatSetDevInfo: no SMART feature set suppored\n")); + oneDeviceData->satSMARTFeatureSet = agFALSE; + } + + /* Support SMART enabled, word85 bit 0 */ + if (SATAIdData->commandSetFeatureEnabled & 0x01) + { + SM_DBG3(("smsatSetDevInfo: SMART enabled \n")); + oneDeviceData->satSMARTEnabled = agTRUE; + } + else + { + SM_DBG3(("smsatSetDevInfo: no SMART enabled\n")); + oneDeviceData->satSMARTEnabled = agFALSE; + } + + oneDeviceData->satVerifyState = 0; + + /* Removable Media feature set support, word82 bit 2 */ + if (SATAIdData->commandSetSupported & 0x4) + { + SM_DBG3(("smsatSetDevInfo: Removable Media supported \n")); + oneDeviceData->satRemovableMedia = agTRUE; + } + else + { + SM_DBG3(("smsatSetDevInfo: no Removable Media suppored\n")); + oneDeviceData->satRemovableMedia = agFALSE; + } + + /* Removable Media feature set enabled, word 85, bit 2 */ + if (SATAIdData->commandSetFeatureEnabled & 0x4) + { + SM_DBG3(("smsatSetDevInfo: Removable Media enabled\n")); + oneDeviceData->satRemovableMediaEnabled = agTRUE; + } + else + { + SM_DBG3(("smsatSetDevInfo: no Removable Media enabled\n")); + oneDeviceData->satRemovableMediaEnabled = agFALSE; + } + + /* DMA Support, word49 bit8 */ + if (SATAIdData->dma_lba_iod_ios_stimer & 0x100) + { + SM_DBG3(("smsatSetDevInfo: DMA supported \n")); + oneDeviceData->satDMASupport = agTRUE; + } + else + { + SM_DBG3(("smsatSetDevInfo: no DMA suppored\n")); + oneDeviceData->satDMASupport = agFALSE; + } + + /* Support DMADIR, if Word 62 bit 8 is set */ + if (SATAIdData->word62_74[0] & 0x8000) + { + SM_DBG3(("satSetDevInfo: DMADIR enabled\n")); + oneDeviceData->satDMADIRSupport = agTRUE; + } + else + { + SM_DBG3(("satSetDevInfo: DMADIR disabled\n")); + oneDeviceData->satDMADIRSupport = agFALSE; + } + + /* DMA Enabled, word88 bit0-6, bit8-14*/ + /* 0x7F7F = 0111 1111 0111 1111*/ + if (SATAIdData->ultraDMAModes & 0x7F7F) + { + SM_DBG3(("smsatSetDevInfo: DMA enabled \n")); + oneDeviceData->satDMAEnabled = agTRUE; + if (SATAIdData->ultraDMAModes & 0x40) + { + oneDeviceData->satUltraDMAMode = 6; + } + else if (SATAIdData->ultraDMAModes & 0x20) + { + oneDeviceData->satUltraDMAMode = 5; + } + else if (SATAIdData->ultraDMAModes & 0x10) + { + oneDeviceData->satUltraDMAMode = 4; + } + else if (SATAIdData->ultraDMAModes & 0x08) + { + oneDeviceData->satUltraDMAMode = 3; + } + else if (SATAIdData->ultraDMAModes & 0x04) + { + oneDeviceData->satUltraDMAMode = 2; + } + else if (SATAIdData->ultraDMAModes & 0x01) + { + oneDeviceData->satUltraDMAMode = 1; + } + } + else + { + SM_DBG3(("smsatSetDevInfo: no DMA enabled\n")); + oneDeviceData->satDMAEnabled = agFALSE; + oneDeviceData->satUltraDMAMode = 0; + } + + /* + setting MaxUserAddrSectors: max user addressable setctors + word60 - 61, should be 0x 0F FF FF FF + */ + oneDeviceData->satMaxUserAddrSectors + = (SATAIdData->numOfUserAddressableSectorsHi << (8*2) ) + + SATAIdData->numOfUserAddressableSectorsLo; + SM_DBG3(("smsatSetDevInfo: MaxUserAddrSectors 0x%x decimal %d\n", oneDeviceData->satMaxUserAddrSectors, oneDeviceData->satMaxUserAddrSectors)); + + /* Read Look-ahead is supported */ + if (SATAIdData->commandSetSupported & 0x40) + { + SM_DBG3(("smsatSetDevInfo: Read Look-ahead is supported\n")); + oneDeviceData->satReadLookAheadSupport= agTRUE; + } + else + { + SM_DBG3(("smsatSetDevInfo: Read Look-ahead is not supported\n")); + oneDeviceData->satReadLookAheadSupport= agFALSE; + } + + /* Volatile Write Cache is supported */ + if (SATAIdData->commandSetSupported & 0x20) + { + SM_DBG3(("smsatSetDevInfo: Volatile Write Cache is supported\n")); + oneDeviceData->satVolatileWriteCacheSupport = agTRUE; + } + else + { + SM_DBG3(("smsatSetDevInfo: Volatile Write Cache is not supported\n")); + oneDeviceData->satVolatileWriteCacheSupport = agFALSE; + } + + /* write cache enabled for caching mode page SAT Table 67 p69, word85 bit5 */ + if (SATAIdData->commandSetFeatureEnabled & 0x20) + { + SM_DBG3(("smsatSetDevInfo: write cache enabled\n")); + oneDeviceData->satWriteCacheEnabled = agTRUE; + } + else + { + SM_DBG3(("smsatSetDevInfo: no write cache enabled\n")); + oneDeviceData->satWriteCacheEnabled = agFALSE; + } + + /* look ahead enabled for caching mode page SAT Table 67 p69, word85 bit6 */ + if (SATAIdData->commandSetFeatureEnabled & 0x40) + { + SM_DBG3(("smsatSetDevInfo: look ahead enabled\n")); + oneDeviceData->satLookAheadEnabled = agTRUE; + } + else + { + SM_DBG3(("smsatSetDevInfo: no look ahead enabled\n")); + oneDeviceData->satLookAheadEnabled = agFALSE; + } + + /* Support WWN, if Word 87 bit 8 is set */ + if (SATAIdData->commandSetFeatureDefault & 0x100) + { + SM_DBG3(("smsatSetDevInfo: device supports WWN\n")); + oneDeviceData->satWWNSupport = agTRUE; + } + else + { + SM_DBG3(("smsatSetDevInfo: no WWN\n")); + oneDeviceData->satWWNSupport = agFALSE; + } + + /* Support DMA Setup Auto-Activate, if Word 78 bit 2 is set */ + if (SATAIdData->sataFeaturesSupported & 0x4) + { + SM_DBG3(("smsatSetDevInfo: device supports DMA Setup Auto-Activate\n")); + oneDeviceData->satDMASetupAA = agTRUE; + } + else + { + SM_DBG3(("smsatSetDevInfo: no DMA Setup Auto-Activate\n")); + oneDeviceData->satDMASetupAA = agFALSE; + } + + /* Support NCQ Queue Management Command, if Word 77 bit 5 is set */ + if (SATAIdData->word77 & 0x10) + { + SM_DBG3(("smsatSetDevInfo: device supports NCQ Queue Management Command\n")); + oneDeviceData->satNCQQMgntCmd = agTRUE; + } + else + { + SM_DBG3(("smsatSetDevInfo: no NCQ Queue Management Command\n")); + oneDeviceData->satNCQQMgntCmd = agFALSE; + } + return; +} + + +osGLOBAL void +smsatInquiryStandard( + bit8 *pInquiry, + agsaSATAIdentifyData_t *pSATAIdData, + smIniScsiCmnd_t *scsiCmnd + ) +{ + smLUN_t *pLun; + pLun = &scsiCmnd->lun; + + /* + Assumption: Basic Task Mangement is supported + -> BQUE 1 and CMDQUE 0, SPC-4, Table96, p147 + */ + /* + See SPC-4, 6.4.2, p 143 + and SAT revision 8, 8.1.2, p 28 + */ + SM_DBG5(("smsatInquiryStandard: start\n")); + + if (pInquiry == agNULL) + { + SM_DBG1(("smsatInquiryStandard: pInquiry is NULL, wrong\n")); + return; + } + else + { + SM_DBG5(("smsatInquiryStandard: pInquiry is NOT NULL\n")); + } + /* + * Reject all other LUN other than LUN 0. + */ + if ( ((pLun->lun[0] | pLun->lun[1] | pLun->lun[2] | pLun->lun[3] | + pLun->lun[4] | pLun->lun[5] | pLun->lun[6] | pLun->lun[7] ) != 0) ) + { + /* SAT Spec Table 8, p27, footnote 'a' */ + pInquiry[0] = 0x7F; + + } + else + { + pInquiry[0] = 0x00; + } + + if (pSATAIdData->rm_ataDevice & ATA_REMOVABLE_MEDIA_DEVICE_MASK ) + { + pInquiry[1] = 0x80; + } + else + { + pInquiry[1] = 0x00; + } + pInquiry[2] = 0x05; /* SPC-3 */ + pInquiry[3] = 0x12; /* set HiSup 1; resp data format set to 2 */ + pInquiry[4] = 0x1F; /* 35 - 4 = 31; Additional length */ + pInquiry[5] = 0x00; + /* The following two are for task management. SAT Rev8, p20 */ + if (pSATAIdData->sataCapabilities & 0x100) + { + /* NCQ supported; multiple outstanding SCSI IO are supported */ + pInquiry[6] = 0x00; /* BQUE bit is not set */ + pInquiry[7] = 0x02; /* CMDQUE bit is set */ + } + else + { + pInquiry[6] = 0x80; /* BQUE bit is set */ + pInquiry[7] = 0x00; /* CMDQUE bit is not set */ + } + /* + * Vendor ID. + */ + sm_strncpy((char*)&pInquiry[8], AG_SAT_VENDOR_ID_STRING, 8); /* 8 bytes */ + + /* + * Product ID + */ + /* when flipped by LL */ + pInquiry[16] = pSATAIdData->modelNumber[1]; + pInquiry[17] = pSATAIdData->modelNumber[0]; + pInquiry[18] = pSATAIdData->modelNumber[3]; + pInquiry[19] = pSATAIdData->modelNumber[2]; + pInquiry[20] = pSATAIdData->modelNumber[5]; + pInquiry[21] = pSATAIdData->modelNumber[4]; + pInquiry[22] = pSATAIdData->modelNumber[7]; + pInquiry[23] = pSATAIdData->modelNumber[6]; + pInquiry[24] = pSATAIdData->modelNumber[9]; + pInquiry[25] = pSATAIdData->modelNumber[8]; + pInquiry[26] = pSATAIdData->modelNumber[11]; + pInquiry[27] = pSATAIdData->modelNumber[10]; + pInquiry[28] = pSATAIdData->modelNumber[13]; + pInquiry[29] = pSATAIdData->modelNumber[12]; + pInquiry[30] = pSATAIdData->modelNumber[15]; + pInquiry[31] = pSATAIdData->modelNumber[14]; + + /* when flipped */ + /* + * Product Revision level. + */ + + /* + * If the IDENTIFY DEVICE data received in words 25 and 26 from the ATA + * device are ASCII spaces (20h), do this translation. + */ + if ( (pSATAIdData->firmwareVersion[4] == 0x20 ) && + (pSATAIdData->firmwareVersion[5] == 0x20 ) && + (pSATAIdData->firmwareVersion[6] == 0x20 ) && + (pSATAIdData->firmwareVersion[7] == 0x20 ) + ) + { + pInquiry[32] = pSATAIdData->firmwareVersion[1]; + pInquiry[33] = pSATAIdData->firmwareVersion[0]; + pInquiry[34] = pSATAIdData->firmwareVersion[3]; + pInquiry[35] = pSATAIdData->firmwareVersion[2]; + } + else + { + pInquiry[32] = pSATAIdData->firmwareVersion[5]; + pInquiry[33] = pSATAIdData->firmwareVersion[4]; + pInquiry[34] = pSATAIdData->firmwareVersion[7]; + pInquiry[35] = pSATAIdData->firmwareVersion[6]; + } + + +#ifdef REMOVED + /* + * Product ID + */ + /* when flipped by LL */ + pInquiry[16] = pSATAIdData->modelNumber[0]; + pInquiry[17] = pSATAIdData->modelNumber[1]; + pInquiry[18] = pSATAIdData->modelNumber[2]; + pInquiry[19] = pSATAIdData->modelNumber[3]; + pInquiry[20] = pSATAIdData->modelNumber[4]; + pInquiry[21] = pSATAIdData->modelNumber[5]; + pInquiry[22] = pSATAIdData->modelNumber[6]; + pInquiry[23] = pSATAIdData->modelNumber[7]; + pInquiry[24] = pSATAIdData->modelNumber[8]; + pInquiry[25] = pSATAIdData->modelNumber[9]; + pInquiry[26] = pSATAIdData->modelNumber[10]; + pInquiry[27] = pSATAIdData->modelNumber[11]; + pInquiry[28] = pSATAIdData->modelNumber[12]; + pInquiry[29] = pSATAIdData->modelNumber[13]; + pInquiry[30] = pSATAIdData->modelNumber[14]; + pInquiry[31] = pSATAIdData->modelNumber[15]; + + /* when flipped */ + /* + * Product Revision level. + */ + + /* + * If the IDENTIFY DEVICE data received in words 25 and 26 from the ATA + * device are ASCII spaces (20h), do this translation. + */ + if ( (pSATAIdData->firmwareVersion[4] == 0x20 ) && + (pSATAIdData->firmwareVersion[5] == 0x20 ) && + (pSATAIdData->firmwareVersion[6] == 0x20 ) && + (pSATAIdData->firmwareVersion[7] == 0x20 ) + ) + { + pInquiry[32] = pSATAIdData->firmwareVersion[0]; + pInquiry[33] = pSATAIdData->firmwareVersion[1]; + pInquiry[34] = pSATAIdData->firmwareVersion[2]; + pInquiry[35] = pSATAIdData->firmwareVersion[3]; + } + else + { + pInquiry[32] = pSATAIdData->firmwareVersion[4]; + pInquiry[33] = pSATAIdData->firmwareVersion[5]; + pInquiry[34] = pSATAIdData->firmwareVersion[6]; + pInquiry[35] = pSATAIdData->firmwareVersion[7]; + } +#endif + + SM_DBG5(("smsatInquiryStandard: end\n")); + + return; +} + +osGLOBAL void +smsatInquiryPage0( + bit8 *pInquiry, + agsaSATAIdentifyData_t *pSATAIdData + ) +{ + SM_DBG5(("smsatInquiryPage0: start\n")); + + /* + See SPC-4, 7.6.9, p 345 + and SAT revision 8, 10.3.2, p 77 + */ + pInquiry[0] = 0x00; + pInquiry[1] = 0x00; /* page code */ + pInquiry[2] = 0x00; /* reserved */ + pInquiry[3] = 8 - 3; /* last index(in this case, 6) - 3; page length */ + + /* supported vpd page list */ + pInquiry[4] = 0x00; /* page 0x00 supported */ + pInquiry[5] = 0x80; /* page 0x80 supported */ + pInquiry[6] = 0x83; /* page 0x83 supported */ + pInquiry[7] = 0x89; /* page 0x89 supported */ + pInquiry[8] = 0xB1; /* page 0xB1 supported */ + + return; +} + +osGLOBAL void +smsatInquiryPage83( + bit8 *pInquiry, + agsaSATAIdentifyData_t *pSATAIdData, + smDeviceData_t *oneDeviceData + ) +{ + satSimpleSATAIdentifyData_t *pSimpleData; + + /* + * When translating the fields, in some cases using the simple form of SATA + * Identify Device Data is easier. So we define it here. + * Both pSimpleData and pSATAIdData points to the same data. + */ + pSimpleData = ( satSimpleSATAIdentifyData_t *)pSATAIdData; + + SM_DBG5(("smsatInquiryPage83: start\n")); + + pInquiry[0] = 0x00; + pInquiry[1] = 0x83; /* page code */ + pInquiry[2] = 0; /* Reserved */ + /* + * If the ATA device returns word 87 bit 8 set to one in its IDENTIFY DEVICE + * data indicating that it supports the WORLD WIDE NAME field + * (i.e., words 108-111), the SATL shall include an identification descriptor + * containing a logical unit name. + */ + if ( oneDeviceData->satWWNSupport) + { +#ifndef PMC_FREEBSD + /* Fill in SAT Rev8 Table85 */ + /* + * Logical unit name derived from the world wide name. + */ + pInquiry[3] = 12; /* 15-3; page length, no addition ID descriptor assumed*/ + + /* + * Identifier descriptor + */ + pInquiry[4] = 0x01; /* Code set: binary codes */ + pInquiry[5] = 0x03; /* Identifier type : NAA */ + pInquiry[6] = 0x00; /* Reserved */ + pInquiry[7] = 0x08; /* Identifier length */ + + /* Bit 4-7 NAA field, bit 0-3 MSB of IEEE Company ID */ + pInquiry[8] = (bit8)((pSATAIdData->namingAuthority) >> 8); + pInquiry[9] = (bit8)((pSATAIdData->namingAuthority) & 0xFF); /* IEEE Company ID */ + pInquiry[10] = (bit8)((pSATAIdData->namingAuthority1) >> 8); /* IEEE Company ID */ + /* Bit 4-7 LSB of IEEE Company ID, bit 0-3 MSB of Vendor Specific ID */ + pInquiry[11] = (bit8)((pSATAIdData->namingAuthority1) & 0xFF); + pInquiry[12] = (bit8)((pSATAIdData->uniqueID_bit16_31) >> 8); /* Vendor Specific ID */ + pInquiry[13] = (bit8)((pSATAIdData->uniqueID_bit16_31) & 0xFF); /* Vendor Specific ID */ + pInquiry[14] = (bit8)((pSATAIdData->uniqueID_bit0_15) >> 8); /* Vendor Specific ID */ + pInquiry[15] = (bit8)((pSATAIdData->uniqueID_bit0_15) & 0xFF); /* Vendor Specific ID */ + +#else + + /* For FreeBSD */ + + /* Fill in SAT Rev8 Table85 */ + /* + * Logical unit name derived from the world wide name. + */ + pInquiry[3] = 24; /* 35-3; page length, no addition ID descriptor assumed*/ + /* + * Identifier descriptor + */ + pInquiry[4] = 0x01; /* Code set: binary codes; this is proto_codeset in FreeBSD */ + pInquiry[5] = 0x03; /* Identifier type : NAA ; this is id_type in FreeBSD*/ + pInquiry[6] = 0x00; /* Reserved */ + pInquiry[7] = 0x08; /* Identifier length */ + + /* Bit 4-7 NAA field, bit 0-3 MSB of IEEE Company ID */ + pInquiry[8] = (bit8)((pSATAIdData->namingAuthority) >> 8); + pInquiry[9] = (bit8)((pSATAIdData->namingAuthority) & 0xFF); /* IEEE Company ID */ + pInquiry[10] = (bit8)((pSATAIdData->namingAuthority1) >> 8); /* IEEE Company ID */ + /* Bit 4-7 LSB of IEEE Company ID, bit 0-3 MSB of Vendor Specific ID */ + pInquiry[11] = (bit8)((pSATAIdData->namingAuthority1) & 0xFF); + pInquiry[12] = (bit8)((pSATAIdData->uniqueID_bit16_31) >> 8); /* Vendor Specific ID */ + pInquiry[13] = (bit8)((pSATAIdData->uniqueID_bit16_31) & 0xFF); /* Vendor Specific ID */ + pInquiry[14] = (bit8)((pSATAIdData->uniqueID_bit0_15) >> 8); /* Vendor Specific ID */ + pInquiry[15] = (bit8)((pSATAIdData->uniqueID_bit0_15) & 0xFF); /* Vendor Specific ID */ + + pInquiry[16] = 0x61; /* Code set: binary codes; this is proto_codeset in FreeBSD; SCSI_PROTO_SAS and SVPD_ID_CODESET_BINARY */ + pInquiry[17] = 0x93; /* Identifier type : NAA ; this is id_type in FreeBSD; PIV set, ASSOCIATION is 01b and NAA (3h) */ + pInquiry[18] = 0x00; /* Reserved */ + pInquiry[19] = 0x08; /* Identifier length */ + + SM_DBG5(("smsatInquiryPage83: sasAddressHi 0x%08x\n", oneDeviceData->sasAddressHi)); + SM_DBG5(("smsatInquiryPage83: sasAddressLo 0x%08x\n", oneDeviceData->sasAddressLo)); + + /* SAS address of SATA */ + pInquiry[20] = ((oneDeviceData->sasAddressHi) & 0xFF000000 ) >> 24; + pInquiry[21] = ((oneDeviceData->sasAddressHi) & 0xFF0000 ) >> 16; + pInquiry[22] = ((oneDeviceData->sasAddressHi) & 0xFF00 ) >> 8; + pInquiry[23] = (oneDeviceData->sasAddressHi) & 0xFF; + pInquiry[24] = ((oneDeviceData->sasAddressLo) & 0xFF000000 ) >> 24; + pInquiry[25] = ((oneDeviceData->sasAddressLo) & 0xFF0000 ) >> 16; + pInquiry[26] = ((oneDeviceData->sasAddressLo) & 0xFF00 ) >> 8; + pInquiry[27] = (oneDeviceData->sasAddressLo) & 0xFF; +#endif + } + else + { +#ifndef PMC_FREEBSD + /* Fill in SAT Rev8 Table86 */ + /* + * Logical unit name derived from the model number and serial number. + */ + pInquiry[3] = 72; /* 75 - 3; page length */ + + /* + * Identifier descriptor + */ + pInquiry[4] = 0x02; /* Code set: ASCII codes */ + pInquiry[5] = 0x01; /* Identifier type : T10 vendor ID based */ + pInquiry[6] = 0x00; /* Reserved */ + pInquiry[7] = 0x44; /* 0x44, 68 Identifier length */ + + /* Byte 8 to 15 is the vendor id string 'ATA '. */ + sm_strncpy((char *)&pInquiry[8], AG_SAT_VENDOR_ID_STRING, 8); + + + /* + * Byte 16 to 75 is vendor specific id + */ + pInquiry[16] = (bit8)((pSimpleData->word[27]) >> 8); + pInquiry[17] = (bit8)((pSimpleData->word[27]) & 0x00ff); + pInquiry[18] = (bit8)((pSimpleData->word[28]) >> 8); + pInquiry[19] = (bit8)((pSimpleData->word[28]) & 0x00ff); + pInquiry[20] = (bit8)((pSimpleData->word[29]) >> 8); + pInquiry[21] = (bit8)((pSimpleData->word[29]) & 0x00ff); + pInquiry[22] = (bit8)((pSimpleData->word[30]) >> 8); + pInquiry[23] = (bit8)((pSimpleData->word[30]) & 0x00ff); + pInquiry[24] = (bit8)((pSimpleData->word[31]) >> 8); + pInquiry[25] = (bit8)((pSimpleData->word[31]) & 0x00ff); + pInquiry[26] = (bit8)((pSimpleData->word[32]) >> 8); + pInquiry[27] = (bit8)((pSimpleData->word[32]) & 0x00ff); + pInquiry[28] = (bit8)((pSimpleData->word[33]) >> 8); + pInquiry[29] = (bit8)((pSimpleData->word[33]) & 0x00ff); + pInquiry[30] = (bit8)((pSimpleData->word[34]) >> 8); + pInquiry[31] = (bit8)((pSimpleData->word[34]) & 0x00ff); + pInquiry[32] = (bit8)((pSimpleData->word[35]) >> 8); + pInquiry[33] = (bit8)((pSimpleData->word[35]) & 0x00ff); + pInquiry[34] = (bit8)((pSimpleData->word[36]) >> 8); + pInquiry[35] = (bit8)((pSimpleData->word[36]) & 0x00ff); + pInquiry[36] = (bit8)((pSimpleData->word[37]) >> 8); + pInquiry[37] = (bit8)((pSimpleData->word[37]) & 0x00ff); + pInquiry[38] = (bit8)((pSimpleData->word[38]) >> 8); + pInquiry[39] = (bit8)((pSimpleData->word[38]) & 0x00ff); + pInquiry[40] = (bit8)((pSimpleData->word[39]) >> 8); + pInquiry[41] = (bit8)((pSimpleData->word[39]) & 0x00ff); + pInquiry[42] = (bit8)((pSimpleData->word[40]) >> 8); + pInquiry[43] = (bit8)((pSimpleData->word[40]) & 0x00ff); + pInquiry[44] = (bit8)((pSimpleData->word[41]) >> 8); + pInquiry[45] = (bit8)((pSimpleData->word[41]) & 0x00ff); + pInquiry[46] = (bit8)((pSimpleData->word[42]) >> 8); + pInquiry[47] = (bit8)((pSimpleData->word[42]) & 0x00ff); + pInquiry[48] = (bit8)((pSimpleData->word[43]) >> 8); + pInquiry[49] = (bit8)((pSimpleData->word[43]) & 0x00ff); + pInquiry[50] = (bit8)((pSimpleData->word[44]) >> 8); + pInquiry[51] = (bit8)((pSimpleData->word[44]) & 0x00ff); + pInquiry[52] = (bit8)((pSimpleData->word[45]) >> 8); + pInquiry[53] = (bit8)((pSimpleData->word[45]) & 0x00ff); + pInquiry[54] = (bit8)((pSimpleData->word[46]) >> 8); + pInquiry[55] = (bit8)((pSimpleData->word[46]) & 0x00ff); + + pInquiry[56] = (bit8)((pSimpleData->word[10]) >> 8); + pInquiry[57] = (bit8)((pSimpleData->word[10]) & 0x00ff); + pInquiry[58] = (bit8)((pSimpleData->word[11]) >> 8); + pInquiry[59] = (bit8)((pSimpleData->word[11]) & 0x00ff); + pInquiry[60] = (bit8)((pSimpleData->word[12]) >> 8); + pInquiry[61] = (bit8)((pSimpleData->word[12]) & 0x00ff); + pInquiry[62] = (bit8)((pSimpleData->word[13]) >> 8); + pInquiry[63] = (bit8)((pSimpleData->word[13]) & 0x00ff); + pInquiry[64] = (bit8)((pSimpleData->word[14]) >> 8); + pInquiry[65] = (bit8)((pSimpleData->word[14]) & 0x00ff); + pInquiry[66] = (bit8)((pSimpleData->word[15]) >> 8); + pInquiry[67] = (bit8)((pSimpleData->word[15]) & 0x00ff); + pInquiry[68] = (bit8)((pSimpleData->word[16]) >> 8); + pInquiry[69] = (bit8)((pSimpleData->word[16]) & 0x00ff); + pInquiry[70] = (bit8)((pSimpleData->word[17]) >> 8); + pInquiry[71] = (bit8)((pSimpleData->word[17]) & 0x00ff); + pInquiry[72] = (bit8)((pSimpleData->word[18]) >> 8); + pInquiry[73] = (bit8)((pSimpleData->word[18]) & 0x00ff); + pInquiry[74] = (bit8)((pSimpleData->word[19]) >> 8); + pInquiry[75] = (bit8)((pSimpleData->word[19]) & 0x00ff); +#else + /* for the FreeBSD */ + /* Fill in SAT Rev8 Table86 */ + /* + * Logical unit name derived from the model number and serial number. + */ + pInquiry[3] = 84; /* 87 - 3; page length */ + + /* + * Identifier descriptor + */ + pInquiry[4] = 0x02; /* Code set: ASCII codes */ + pInquiry[5] = 0x01; /* Identifier type : T10 vendor ID based */ + pInquiry[6] = 0x00; /* Reserved */ + pInquiry[7] = 0x44; /* 0x44, 68 Identifier length */ + + /* Byte 8 to 15 is the vendor id string 'ATA '. */ + sm_strncpy((char *)&pInquiry[8], AG_SAT_VENDOR_ID_STRING, 8); + + + /* + * Byte 16 to 75 is vendor specific id + */ + pInquiry[16] = (bit8)((pSimpleData->word[27]) >> 8); + pInquiry[17] = (bit8)((pSimpleData->word[27]) & 0x00ff); + pInquiry[18] = (bit8)((pSimpleData->word[28]) >> 8); + pInquiry[19] = (bit8)((pSimpleData->word[28]) & 0x00ff); + pInquiry[20] = (bit8)((pSimpleData->word[29]) >> 8); + pInquiry[21] = (bit8)((pSimpleData->word[29]) & 0x00ff); + pInquiry[22] = (bit8)((pSimpleData->word[30]) >> 8); + pInquiry[23] = (bit8)((pSimpleData->word[30]) & 0x00ff); + pInquiry[24] = (bit8)((pSimpleData->word[31]) >> 8); + pInquiry[25] = (bit8)((pSimpleData->word[31]) & 0x00ff); + pInquiry[26] = (bit8)((pSimpleData->word[32]) >> 8); + pInquiry[27] = (bit8)((pSimpleData->word[32]) & 0x00ff); + pInquiry[28] = (bit8)((pSimpleData->word[33]) >> 8); + pInquiry[29] = (bit8)((pSimpleData->word[33]) & 0x00ff); + pInquiry[30] = (bit8)((pSimpleData->word[34]) >> 8); + pInquiry[31] = (bit8)((pSimpleData->word[34]) & 0x00ff); + pInquiry[32] = (bit8)((pSimpleData->word[35]) >> 8); + pInquiry[33] = (bit8)((pSimpleData->word[35]) & 0x00ff); + pInquiry[34] = (bit8)((pSimpleData->word[36]) >> 8); + pInquiry[35] = (bit8)((pSimpleData->word[36]) & 0x00ff); + pInquiry[36] = (bit8)((pSimpleData->word[37]) >> 8); + pInquiry[37] = (bit8)((pSimpleData->word[37]) & 0x00ff); + pInquiry[38] = (bit8)((pSimpleData->word[38]) >> 8); + pInquiry[39] = (bit8)((pSimpleData->word[38]) & 0x00ff); + pInquiry[40] = (bit8)((pSimpleData->word[39]) >> 8); + pInquiry[41] = (bit8)((pSimpleData->word[39]) & 0x00ff); + pInquiry[42] = (bit8)((pSimpleData->word[40]) >> 8); + pInquiry[43] = (bit8)((pSimpleData->word[40]) & 0x00ff); + pInquiry[44] = (bit8)((pSimpleData->word[41]) >> 8); + pInquiry[45] = (bit8)((pSimpleData->word[41]) & 0x00ff); + pInquiry[46] = (bit8)((pSimpleData->word[42]) >> 8); + pInquiry[47] = (bit8)((pSimpleData->word[42]) & 0x00ff); + pInquiry[48] = (bit8)((pSimpleData->word[43]) >> 8); + pInquiry[49] = (bit8)((pSimpleData->word[43]) & 0x00ff); + pInquiry[50] = (bit8)((pSimpleData->word[44]) >> 8); + pInquiry[51] = (bit8)((pSimpleData->word[44]) & 0x00ff); + pInquiry[52] = (bit8)((pSimpleData->word[45]) >> 8); + pInquiry[53] = (bit8)((pSimpleData->word[45]) & 0x00ff); + pInquiry[54] = (bit8)((pSimpleData->word[46]) >> 8); + pInquiry[55] = (bit8)((pSimpleData->word[46]) & 0x00ff); + + pInquiry[56] = (bit8)((pSimpleData->word[10]) >> 8); + pInquiry[57] = (bit8)((pSimpleData->word[10]) & 0x00ff); + pInquiry[58] = (bit8)((pSimpleData->word[11]) >> 8); + pInquiry[59] = (bit8)((pSimpleData->word[11]) & 0x00ff); + pInquiry[60] = (bit8)((pSimpleData->word[12]) >> 8); + pInquiry[61] = (bit8)((pSimpleData->word[12]) & 0x00ff); + pInquiry[62] = (bit8)((pSimpleData->word[13]) >> 8); + pInquiry[63] = (bit8)((pSimpleData->word[13]) & 0x00ff); + pInquiry[64] = (bit8)((pSimpleData->word[14]) >> 8); + pInquiry[65] = (bit8)((pSimpleData->word[14]) & 0x00ff); + pInquiry[66] = (bit8)((pSimpleData->word[15]) >> 8); + pInquiry[67] = (bit8)((pSimpleData->word[15]) & 0x00ff); + pInquiry[68] = (bit8)((pSimpleData->word[16]) >> 8); + pInquiry[69] = (bit8)((pSimpleData->word[16]) & 0x00ff); + pInquiry[70] = (bit8)((pSimpleData->word[17]) >> 8); + pInquiry[71] = (bit8)((pSimpleData->word[17]) & 0x00ff); + pInquiry[72] = (bit8)((pSimpleData->word[18]) >> 8); + pInquiry[73] = (bit8)((pSimpleData->word[18]) & 0x00ff); + pInquiry[74] = (bit8)((pSimpleData->word[19]) >> 8); + pInquiry[75] = (bit8)((pSimpleData->word[19]) & 0x00ff); + + pInquiry[76] = 0x61; /* Code set: binary codes; this is proto_codeset in FreeBSD; SCSI_PROTO_SAS and SVPD_ID_CODESET_BINARY */ + pInquiry[77] = 0x93; /* Identifier type : NAA ; this is id_type in FreeBSD; PIV set, ASSOCIATION is 01b and NAA (3h) */ + pInquiry[78] = 0x00; /* Reserved */ + pInquiry[79] = 0x08; /* Identifier length */ + + SM_DBG5(("smsatInquiryPage83: NO WWN sasAddressHi 0x%08x\n", oneDeviceData->sasAddressHi)); + SM_DBG5(("smsatInquiryPage83: No WWN sasAddressLo 0x%08x\n", oneDeviceData->sasAddressLo)); + + /* SAS address of SATA */ + pInquiry[80] = ((oneDeviceData->sasAddressHi) & 0xFF000000 ) >> 24; + pInquiry[81] = ((oneDeviceData->sasAddressHi) & 0xFF0000 ) >> 16; + pInquiry[82] = ((oneDeviceData->sasAddressHi) & 0xFF00 ) >> 8; + pInquiry[83] = (oneDeviceData->sasAddressHi) & 0xFF; + pInquiry[84] = ((oneDeviceData->sasAddressLo) & 0xFF000000 ) >> 24; + pInquiry[85] = ((oneDeviceData->sasAddressLo) & 0xFF0000 ) >> 16; + pInquiry[86] = ((oneDeviceData->sasAddressLo) & 0xFF00 ) >> 8; + pInquiry[87] = (oneDeviceData->sasAddressLo) & 0xFF; + +#endif + } + + return; +} + +osGLOBAL void +smsatInquiryPage89( + bit8 *pInquiry, + agsaSATAIdentifyData_t *pSATAIdData, + smDeviceData_t *oneDeviceData, + bit32 len + ) +{ + /* + SAT revision 8, 10.3.5, p 83 + */ + satSimpleSATAIdentifyData_t *pSimpleData; + + /* + * When translating the fields, in some cases using the simple form of SATA + * Identify Device Data is easier. So we define it here. + * Both pSimpleData and pSATAIdData points to the same data. + */ + pSimpleData = ( satSimpleSATAIdentifyData_t *)pSATAIdData; + + SM_DBG5(("smsatInquiryPage89: start\n")); + + pInquiry[0] = 0x00; /* Peripheral Qualifier and Peripheral Device Type */ + pInquiry[1] = 0x89; /* page code */ + + /* Page length 0x238 */ + pInquiry[2] = 0x02; + pInquiry[3] = 0x38; + + pInquiry[4] = 0x0; /* reserved */ + pInquiry[5] = 0x0; /* reserved */ + pInquiry[6] = 0x0; /* reserved */ + pInquiry[7] = 0x0; /* reserved */ + + /* SAT Vendor Identification */ + sm_strncpy((char*)&pInquiry[8], "PMC-SIERRA", 8); /* 8 bytes */ + + /* SAT Product Idetification */ + sm_strncpy((char*)&pInquiry[16], "Tachyon-SPC ", 16); /* 16 bytes */ + + /* SAT Product Revision Level */ + sm_strncpy((char*)&pInquiry[32], "01", 4); /* 4 bytes */ + + /* Signature, SAT revision8, Table88, p85 */ + + + pInquiry[36] = 0x34; /* FIS type */ + if (oneDeviceData->satDeviceType == SATA_ATA_DEVICE) + { + /* interrupt assume to be 0 */ + pInquiry[37] = (bit8)((oneDeviceData->satPMField) >> (4 * 7)); /* first four bits of PM field */ + } + else + { + /* interrupt assume to be 1 */ + pInquiry[37] = (bit8)(0x40 + (bit8)(((oneDeviceData->satPMField) >> (4 * 7)))); /* first four bits of PM field */ + } + pInquiry[38] = 0; + pInquiry[39] = 0; + + if (oneDeviceData->satDeviceType == SATA_ATA_DEVICE) + { + pInquiry[40] = 0x01; /* LBA Low */ + pInquiry[41] = 0x00; /* LBA Mid */ + pInquiry[42] = 0x00; /* LBA High */ + pInquiry[43] = 0x00; /* Device */ + pInquiry[44] = 0x00; /* LBA Low Exp */ + pInquiry[45] = 0x00; /* LBA Mid Exp */ + pInquiry[46] = 0x00; /* LBA High Exp */ + pInquiry[47] = 0x00; /* Reserved */ + pInquiry[48] = 0x01; /* Sector Count */ + pInquiry[49] = 0x00; /* Sector Count Exp */ + } + else + { + pInquiry[40] = 0x01; /* LBA Low */ + pInquiry[41] = 0x00; /* LBA Mid */ + pInquiry[42] = 0x00; /* LBA High */ + pInquiry[43] = 0x00; /* Device */ + pInquiry[44] = 0x00; /* LBA Low Exp */ + pInquiry[45] = 0x00; /* LBA Mid Exp */ + pInquiry[46] = 0x00; /* LBA High Exp */ + pInquiry[47] = 0x00; /* Reserved */ + pInquiry[48] = 0x01; /* Sector Count */ + pInquiry[49] = 0x00; /* Sector Count Exp */ + } + + /* Reserved */ + pInquiry[50] = 0x00; + pInquiry[51] = 0x00; + pInquiry[52] = 0x00; + pInquiry[53] = 0x00; + pInquiry[54] = 0x00; + pInquiry[55] = 0x00; + + /* Command Code */ + if (oneDeviceData->satDeviceType == SATA_ATA_DEVICE) + { + pInquiry[56] = 0xEC; /* IDENTIFY DEVICE */ + } + else + { + pInquiry[56] = 0xA1; /* IDENTIFY PACKET DEVICE */ + } + /* Reserved */ + pInquiry[57] = 0x0; + pInquiry[58] = 0x0; + pInquiry[59] = 0x0; + + /* check the length; len is assumed to be at least 60 */ + if (len < SATA_PAGE89_INQUIRY_SIZE) + { + /* Identify Device */ + sm_memcpy(&pInquiry[60], pSimpleData, MIN((len - 60), sizeof(satSimpleSATAIdentifyData_t))); + } + else + { + /* Identify Device */ + sm_memcpy(&pInquiry[60], pSimpleData, sizeof(satSimpleSATAIdentifyData_t)); + } + + return; +} + +osGLOBAL void +smsatInquiryPage80( + bit8 *pInquiry, + agsaSATAIdentifyData_t *pSATAIdData + ) +{ + SM_DBG5(("smsatInquiryPage89: start\n")); + /* + See SPC-4, 7.6.9, p 345 + and SAT revision 8, 10.3.3, p 77 + */ + pInquiry[0] = 0x00; + pInquiry[1] = 0x80; /* page code */ + pInquiry[2] = 0x00; /* reserved */ + pInquiry[3] = 0x14; /* page length */ + + /* product serial number */ + pInquiry[4] = pSATAIdData->serialNumber[1]; + pInquiry[5] = pSATAIdData->serialNumber[0]; + pInquiry[6] = pSATAIdData->serialNumber[3]; + pInquiry[7] = pSATAIdData->serialNumber[2]; + pInquiry[8] = pSATAIdData->serialNumber[5]; + pInquiry[9] = pSATAIdData->serialNumber[4]; + pInquiry[10] = pSATAIdData->serialNumber[7]; + pInquiry[11] = pSATAIdData->serialNumber[6]; + pInquiry[12] = pSATAIdData->serialNumber[9]; + pInquiry[13] = pSATAIdData->serialNumber[8]; + pInquiry[14] = pSATAIdData->serialNumber[11]; + pInquiry[15] = pSATAIdData->serialNumber[10]; + pInquiry[16] = pSATAIdData->serialNumber[13]; + pInquiry[17] = pSATAIdData->serialNumber[12]; + pInquiry[18] = pSATAIdData->serialNumber[15]; + pInquiry[19] = pSATAIdData->serialNumber[14]; + pInquiry[20] = pSATAIdData->serialNumber[17]; + pInquiry[21] = pSATAIdData->serialNumber[16]; + pInquiry[22] = pSATAIdData->serialNumber[19]; + pInquiry[23] = pSATAIdData->serialNumber[18]; + + return; +} + +osGLOBAL void +smsatInquiryPageB1( + bit8 *pInquiry, + agsaSATAIdentifyData_t *pSATAIdData + ) +{ + bit32 i; + satSimpleSATAIdentifyData_t *pSimpleData; + + SM_DBG5(("smsatInquiryPageB1: start\n")); + + pSimpleData = ( satSimpleSATAIdentifyData_t *)pSATAIdData; + /* + See SBC-3, revision31, Table193, p273 + and SAT-3 revision 3, 10.3.6, p141 + */ + pInquiry[0] = 0x00; /* Peripheral Qualifier and Peripheral Device Type */ + pInquiry[1] = 0xB1; /* page code */ + + /* page length */ + pInquiry[2] = 0x0; + pInquiry[3] = 0x3C; + + /* medium rotation rate */ + pInquiry[4] = (bit8) ((pSimpleData->word[217]) >> 8); + pInquiry[5] = (bit8) ((pSimpleData->word[217]) & 0xFF); + + /* reserved */ + pInquiry[6] = 0x0; + + /* nominal form factor bits 3:0 */ + pInquiry[7] = (bit8) ((pSimpleData->word[168]) & 0xF); + + + /* reserved */ + for (i=8;i<64;i++) + { + pInquiry[i] = 0x0; + } + return; +} + +osGLOBAL void +smsatDefaultTranslation( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smSatIOContext_t *satIOContext, + smScsiRspSense_t *pSense, + bit8 ataStatus, + bit8 ataError, + bit32 interruptContext + ) +{ + SM_DBG5(("smsatDefaultTranslation: start\n")); + /* + * Check for device fault case + */ + if ( ataStatus & DF_ATA_STATUS_MASK ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_HARDWARE_ERROR, + 0, + SCSI_SNSCODE_INTERNAL_TARGET_FAILURE, + satIOContext); + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + interruptContext ); + return; + } + + /* + * If status error bit it set, need to check the error register + */ + if ( ataStatus & ERR_ATA_STATUS_MASK ) + { + if ( ataError & NM_ATA_ERROR_MASK ) + { + SM_DBG1(("smsatDefaultTranslation: NM_ATA_ERROR ataError= 0x%x, smIORequest=%p!!!\n", + ataError, smIORequest)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NOT_READY, + 0, + SCSI_SNSCODE_MEDIUM_NOT_PRESENT, + satIOContext); + } + + else if (ataError & UNC_ATA_ERROR_MASK) + { + SM_DBG1(("smsatDefaultTranslation: UNC_ATA_ERROR ataError= 0x%x, smIORequest=%p!!!\n", + ataError, smIORequest)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_MEDIUM_ERROR, + 0, + SCSI_SNSCODE_UNRECOVERED_READ_ERROR, + satIOContext); + } + + else if (ataError & IDNF_ATA_ERROR_MASK) + { + SM_DBG1(("smsatDefaultTranslation: IDNF_ATA_ERROR ataError= 0x%x, smIORequest=%p!!!\n", + ataError, smIORequest)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_MEDIUM_ERROR, + 0, + SCSI_SNSCODE_RECORD_NOT_FOUND, + satIOContext); + } + + else if (ataError & MC_ATA_ERROR_MASK) + { + SM_DBG1(("smsatDefaultTranslation: MC_ATA_ERROR ataError= 0x%x, smIORequest=%p!!!\n", + ataError, smIORequest)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_UNIT_ATTENTION, + 0, + SCSI_SNSCODE_NOT_READY_TO_READY_CHANGE, + satIOContext); + } + + else if (ataError & MCR_ATA_ERROR_MASK) + { + SM_DBG1(("smsatDefaultTranslation: MCR_ATA_ERROR ataError= 0x%x, smIORequest=%p!!!\n", + ataError, smIORequest)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_UNIT_ATTENTION, + 0, + SCSI_SNSCODE_OPERATOR_MEDIUM_REMOVAL_REQUEST, + satIOContext); + } + + else if (ataError & ICRC_ATA_ERROR_MASK) + { + SM_DBG1(("smsatDefaultTranslation: ICRC_ATA_ERROR ataError= 0x%x, smIORequest=%p!!!\n", + ataError, smIORequest)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_INFORMATION_UNIT_CRC_ERROR, + satIOContext); + } + + else if (ataError & ABRT_ATA_ERROR_MASK) + { + SM_DBG1(("smsatDefaultTranslation: ABRT_ATA_ERROR ataError= 0x%x, smIORequest=%p!!!\n", + ataError, smIORequest)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satIOContext); + } + + else + { + SM_DBG1(("smsatDefaultTranslation: **** UNEXPECTED ATA_ERROR **** ataError= 0x%x, smIORequest=%p!!!\n", + ataError, smIORequest)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_HARDWARE_ERROR, + 0, + SCSI_SNSCODE_INTERNAL_TARGET_FAILURE, + satIOContext); + } + + /* Send the completion response now */ + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + interruptContext ); + return; + + + } + + else /* (ataStatus & ERR_ATA_STATUS_MASK ) is false */ + { + /* This case should never happen */ + SM_DBG1(("smsatDefaultTranslation: *** UNEXPECTED ATA status 0x%x *** smIORequest=%p!!!\n", + ataStatus, smIORequest)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_HARDWARE_ERROR, + 0, + SCSI_SNSCODE_INTERNAL_TARGET_FAILURE, + satIOContext); + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + interruptContext ); + return; + + } + + return; +} + +osGLOBAL bit32 +smIDStart( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle + ) +{ + smDeviceData_t *oneDeviceData = agNULL; + smIORequestBody_t *smIORequestBody = agNULL; + smSatIOContext_t *satIOContext = agNULL; + bit32 status = SM_RC_FAILURE; + + SM_DBG2(("smIDStart: start, smIORequest %p\n", smIORequest)); + + oneDeviceData = (smDeviceData_t *)smDeviceHandle->smData; + if (oneDeviceData == agNULL) + { + SM_DBG1(("smIDStart: oneDeviceData is NULL!!!\n")); + return SM_RC_FAILURE; + } + if (oneDeviceData->valid == agFALSE) + { + SM_DBG1(("smIDStart: oneDeviceData is not valid, did %d !!!\n", oneDeviceData->id)); + return SM_RC_FAILURE; + } + + smIORequestBody = (smIORequestBody_t*)smIORequest->smData;//smDequeueIO(smRoot); + + if (smIORequestBody == agNULL) + { + SM_DBG1(("smIDStart: smIORequestBody is NULL!!!\n")); + return SM_RC_FAILURE; + } + + smIOReInit(smRoot, smIORequestBody); + + SM_DBG3(("smIDStart: io ID %d!!!\n", smIORequestBody->id )); + + smIORequestBody->smIORequest = smIORequest; + smIORequestBody->smDevHandle = smDeviceHandle; + satIOContext = &(smIORequestBody->transport.SATA.satIOContext); + + /* setting up satIOContext */ + satIOContext->pSatDevData = oneDeviceData; + satIOContext->pFis = &(smIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev); + satIOContext->smRequestBody = smIORequestBody; + satIOContext->psmDeviceHandle = smDeviceHandle; + satIOContext->smScsiXchg = agNULL; + + /*smIORequest->smData = smIORequestBody;*/ + SM_DBG3(("smIDStart: smIORequestBody %p smIORequestBody->smIORequest %p!!!\n", smIORequestBody, smIORequestBody->smIORequest)); + SM_DBG1(("smIDStart: did %d\n", oneDeviceData->id)); + + status = smsatIDSubStart( smRoot, + smIORequest, + smDeviceHandle, + agNULL, + satIOContext); + + if (status != SM_RC_SUCCESS) + { + SM_DBG1(("smIDStart: smsatIDSubStart failure %d!!!\n", status)); + /*smEnqueueIO(smRoot, satIOContext);*/ + } + SM_DBG2(("smIDStart: exit\n")); + + return status; +} + +/* + SM generated IO, needs to call smsatAllocIntIoResource() + allocating using smsatAllocIntIoResource +*/ +osGLOBAL bit32 +smsatIDSubStart( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smSCSIRequest, /* agNULL */ + smSatIOContext_t *satIOContext + ) +{ + smSatInternalIo_t *satIntIo = agNULL; + smDeviceData_t *satDevData = agNULL; + smIORequestBody_t *smIORequestBody; + smSatIOContext_t *satNewIOContext; + bit32 status; + SM_DBG2(("smsatIDSubStart: start\n")); + + satDevData = satIOContext->pSatDevData; + + /* allocate identify device command */ + satIntIo = smsatAllocIntIoResource( smRoot, + smIORequest, + satDevData, + sizeof(agsaSATAIdentifyData_t), /* 512; size of identify device data */ + satIntIo); + + if (satIntIo == agNULL) + { + SM_DBG1(("smsatIDSubStart: can't alloacate!!!\n")); + return SM_RC_FAILURE; + } + + satIOContext->satIntIoContext = satIntIo; + + /* fill in fields */ + /* real ttttttthe one worked and the same; 5/21/07/ */ + satIntIo->satOrgSmIORequest = smIORequest; /* changed */ + smIORequestBody = satIntIo->satIntRequestBody; + satNewIOContext = &(smIORequestBody->transport.SATA.satIOContext); + + satNewIOContext->pSatDevData = satDevData; + satNewIOContext->pFis = &(smIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev); + satNewIOContext->pScsiCmnd = &(satIntIo->satIntSmScsiXchg.scsiCmnd); + satNewIOContext->pSense = &(smIORequestBody->transport.SATA.sensePayload); + satNewIOContext->pSmSenseData = &(smIORequestBody->transport.SATA.smSenseData); + satNewIOContext->smRequestBody = satIntIo->satIntRequestBody; /* key fix */ + // satNewIOContext->interruptContext = tiInterruptContext; + satNewIOContext->satIntIoContext = satIntIo; + + satNewIOContext->psmDeviceHandle = smDeviceHandle; + satNewIOContext->satOrgIOContext = satIOContext; /* changed */ + + /* this is valid only for TD layer generated (not triggered by OS at all) IO */ + satNewIOContext->smScsiXchg = &(satIntIo->satIntSmScsiXchg); + + + SM_DBG6(("smsatIDSubStart: SM satIOContext %p \n", satIOContext)); + SM_DBG6(("smsatIDSubStart: SM satNewIOContext %p \n", satNewIOContext)); + SM_DBG6(("smsatIDSubStart: SM tiScsiXchg %p \n", satIOContext->smScsiXchg)); + SM_DBG6(("smsatIDSubStart: SM tiScsiXchg %p \n", satNewIOContext->smScsiXchg)); + + + + SM_DBG3(("smsatIDSubStart: satNewIOContext %p smIORequestBody %p\n", satNewIOContext, smIORequestBody)); + + status = smsatIDStart(smRoot, + &satIntIo->satIntSmIORequest, /* New smIORequest */ + smDeviceHandle, + satNewIOContext->smScsiXchg, /* New smScsiInitiatorRequest_t *smScsiRequest, */ + satNewIOContext); + + if (status != SM_RC_SUCCESS) + { + SM_DBG1(("smsatIDSubStart: failed in sending %d!!!\n", status)); + + smsatFreeIntIoResource( smRoot, + satDevData, + satIntIo); + + return SM_RC_FAILURE; + } + + + SM_DBG2(("smsatIDSubStart: end\n")); + + return status; + +} + + +osGLOBAL bit32 +smsatIDStart( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smSCSIRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status; + bit32 agRequestType; + smDeviceData_t *pSatDevData; + agsaFisRegHostToDevice_t *fis; +#ifdef SM_INTERNAL_DEBUG + smIORequestBody_t *smIORequestBody; + smSatInternalIo_t *satIntIoContext; +#endif + + pSatDevData = satIOContext->pSatDevData; + fis = satIOContext->pFis; + SM_DBG2(("smsatIDStart: start\n")); +#ifdef SM_INTERNAL_DEBUG + satIntIoContext = satIOContext->satIntIoContext; + smIORequestBody = satIntIoContext->satIntRequestBody; +#endif + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + if (pSatDevData->satDeviceType == SATA_ATAPI_DEVICE) + { + SM_DBG2(("smsatIDStart: IDENTIFY_PACKET_DEVICE\n")); + fis->h.command = SAT_IDENTIFY_PACKET_DEVICE; /* 0x40 */ + } + else + { + SM_DBG2(("smsatIDStart: IDENTIFY_DEVICE\n")); + fis->h.command = SAT_IDENTIFY_DEVICE; /* 0xEC */ + } + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.device = 0; /* FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatIDStartCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + +#ifdef SM_INTERNAL_DEBUG + smhexdump("smsatIDStart", (bit8 *)satIOContext->pFis, sizeof(agsaFisRegHostToDevice_t)); + smhexdump("smsatIDStart LL", (bit8 *)&(smIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev), sizeof(agsaFisRegHostToDevice_t)); +#endif + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + + SM_DBG2(("smsatIDStart: end status %d\n", status)); + + return status; +} + + +osGLOBAL FORCEINLINE bit32 +smsatIOStart( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smSCSIRequest, + smSatIOContext_t *satIOContext + ) +{ + smDeviceData_t *pSatDevData = satIOContext->pSatDevData; + smScsiRspSense_t *pSense = satIOContext->pSense; + smIniScsiCmnd_t *scsiCmnd = &smSCSIRequest->scsiCmnd; + smLUN_t *pLun = &scsiCmnd->lun; + smSatInternalIo_t *pSatIntIo = agNULL; + bit32 status = SM_RC_FAILURE; + + SM_DBG2(("smsatIOStart: start\n")); + + /* + * Reject all other LUN other than LUN 0. + */ + if ( ((pLun->lun[0] | pLun->lun[1] | pLun->lun[2] | pLun->lun[3] | + pLun->lun[4] | pLun->lun[5] | pLun->lun[6] | pLun->lun[7] ) != 0) && + (scsiCmnd->cdb[0] != SCSIOPC_INQUIRY) + ) + { + SM_DBG1(("smsatIOStart: *** REJECT *** LUN not zero, cdb[0]=0x%x did %d !!!\n", + scsiCmnd->cdb[0], pSatDevData->id)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_NOT_SUPPORTED, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + return SM_RC_SUCCESS; + } + + SM_DBG2(("smsatIOStart: satPendingIO %d satNCQMaxIO %d\n",pSatDevData->satPendingIO, pSatDevData->satNCQMaxIO )); + + /* this may happen after tiCOMReset until OS sends inquiry */ + if (pSatDevData->IDDeviceValid == agFALSE && (scsiCmnd->cdb[0] != SCSIOPC_INQUIRY)) + { + SM_DBG1(("smsatIOStart: invalid identify device data did %d !!!\n", pSatDevData->id)); + SM_DBG1(("smsatIOStart: satPendingIO %d satNCQMaxIO %d\n", pSatDevData->satPendingIO, pSatDevData->satNCQMaxIO )); + SM_DBG1(("smsatIOStart: satPendingNCQIO %d satPendingNONNCQIO %d\n", pSatDevData->satPendingNCQIO, pSatDevData->satPendingNONNCQIO)); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + return SM_RC_NODEVICE; + } + + /* + * Check if we need to return BUSY, i.e. recovery in progress + */ + if (pSatDevData->satDriveState == SAT_DEV_STATE_IN_RECOVERY) + { + SM_DBG1(("smsatIOStart: IN RECOVERY STATE cdb[0]=0x%x did=%d !!!\n", + scsiCmnd->cdb[0], pSatDevData->id)); + SM_DBG2(("smsatIOStart: device %p satPendingIO %d satNCQMaxIO %d\n", pSatDevData, pSatDevData->satPendingIO, pSatDevData->satNCQMaxIO )); + SM_DBG2(("smsatIOStart: device %p satPendingNCQIO %d satPendingNONNCQIO %d\n",pSatDevData, pSatDevData->satPendingNCQIO, pSatDevData->satPendingNONNCQIO)); + + /*smEnqueueIO(smRoot, satIOContext);*/ + +// return SM_RC_FAILURE; + return SM_RC_DEVICE_BUSY; + } + + if (pSatDevData->satDeviceType == SATA_ATAPI_DEVICE) + { + if (scsiCmnd->cdb[0] == SCSIOPC_REPORT_LUN) + { + return smsatReportLun(smRoot, smIORequest, smDeviceHandle, smSCSIRequest, satIOContext); + } + else + { + return smsatPacket(smRoot, smIORequest, smDeviceHandle, smSCSIRequest, satIOContext); + } + } + else + { + /* Parse CDB */ + switch(scsiCmnd->cdb[0]) + { + case SCSIOPC_READ_10: + status = smsatRead10( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + break; + + case SCSIOPC_WRITE_10: + status = smsatWrite10( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + break; + + case SCSIOPC_READ_6: + status = smsatRead6( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + break; + + case SCSIOPC_READ_12: + SM_DBG5(("smsatIOStart: SCSIOPC_READ_12\n")); + status = smsatRead12( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + break; + + case SCSIOPC_READ_16: + status = smsatRead16( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + break; + + case SCSIOPC_WRITE_6: + status = smsatWrite6( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + break; + + case SCSIOPC_WRITE_12: + SM_DBG5(("smsatIOStart: SCSIOPC_WRITE_12 \n")); + status = smsatWrite12( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + break; + + case SCSIOPC_WRITE_16: + SM_DBG5(("smsatIOStart: SCSIOPC_WRITE_16 \n")); + status = smsatWrite16( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + break; + + case SCSIOPC_VERIFY_10: + status = smsatVerify10( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + break; + + case SCSIOPC_VERIFY_12: + SM_DBG5(("smsatIOStart: SCSIOPC_VERIFY_12\n")); + status = smsatVerify12( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + break; + + case SCSIOPC_VERIFY_16: + SM_DBG5(("smsatIOStart: SCSIOPC_VERIFY_16\n")); + status = smsatVerify16( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + break; + + case SCSIOPC_TEST_UNIT_READY: + status = smsatTestUnitReady( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + break; + + case SCSIOPC_INQUIRY: + status = smsatInquiry( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + break; + + case SCSIOPC_REQUEST_SENSE: + status = smsatRequestSense( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + break; + + case SCSIOPC_MODE_SENSE_6: + status = smsatModeSense6( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + break; + + case SCSIOPC_MODE_SENSE_10: + status = smsatModeSense10( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + break; + + case SCSIOPC_READ_CAPACITY_10: + status = smsatReadCapacity10( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + break; + + case SCSIOPC_READ_CAPACITY_16: + status = smsatReadCapacity16( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + break; + + + case SCSIOPC_REPORT_LUN: + status = smsatReportLun( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + break; + + case SCSIOPC_FORMAT_UNIT: + SM_DBG5(("smsatIOStart: SCSIOPC_FORMAT_UNIT\n")); + status = smsatFormatUnit( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + break; + + case SCSIOPC_SEND_DIAGNOSTIC: + SM_DBG5(("smsatIOStart: SCSIOPC_SEND_DIAGNOSTIC\n")); + status = smsatSendDiagnostic( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + break; + + case SCSIOPC_START_STOP_UNIT: + SM_DBG5(("smsatIOStart: SCSIOPC_START_STOP_UNIT\n")); + status = smsatStartStopUnit( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + break; + + case SCSIOPC_WRITE_SAME_10: + SM_DBG5(("smsatIOStart: SCSIOPC_WRITE_SAME_10\n")); + status = smsatWriteSame10( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + break; + + case SCSIOPC_WRITE_SAME_16: /* no support due to transfer length(sector count) */ + SM_DBG5(("smsatIOStart: SCSIOPC_WRITE_SAME_16\n")); + status = smsatWriteSame16( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + break; + + case SCSIOPC_LOG_SENSE: + SM_DBG5(("smsatIOStart: SCSIOPC_LOG_SENSE\n")); + status = smsatLogSense( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + break; + + case SCSIOPC_MODE_SELECT_6: + SM_DBG5(("smsatIOStart: SCSIOPC_MODE_SELECT_6\n")); + status = smsatModeSelect6( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + break; + + case SCSIOPC_MODE_SELECT_10: + SM_DBG5(("smsatIOStart: SCSIOPC_MODE_SELECT_10\n")); + status = smsatModeSelect10( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + break; + + case SCSIOPC_SYNCHRONIZE_CACHE_10: /* on error what to return, sharing CB with + satSynchronizeCache16 */ + SM_DBG5(("smsatIOStart: SCSIOPC_SYNCHRONIZE_CACHE_10\n")); + status = smsatSynchronizeCache10( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + break; + + case SCSIOPC_SYNCHRONIZE_CACHE_16:/* on error what to return, sharing CB with + satSynchronizeCache16 */ + + SM_DBG5(("smsatIOStart: SCSIOPC_SYNCHRONIZE_CACHE_16\n")); + status = smsatSynchronizeCache16( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + break; + + case SCSIOPC_WRITE_AND_VERIFY_10: /* single write and multiple writes */ + SM_DBG5(("smsatIOStart: SCSIOPC_WRITE_AND_VERIFY_10\n")); + status = smsatWriteAndVerify10( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + break; + + case SCSIOPC_WRITE_AND_VERIFY_12: + SM_DBG5(("smsatIOStart: SCSIOPC_WRITE_AND_VERIFY_12\n")); + status = smsatWriteAndVerify12( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + break; + + case SCSIOPC_WRITE_AND_VERIFY_16: + SM_DBG5(("smsatIOStart: SCSIOPC_WRITE_AND_VERIFY_16\n")); + status = smsatWriteAndVerify16( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + + break; + + case SCSIOPC_READ_MEDIA_SERIAL_NUMBER: + SM_DBG5(("smsatIOStart: SCSIOPC_READ_MEDIA_SERIAL_NUMBER\n")); + status = smsatReadMediaSerialNumber( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + + break; + + case SCSIOPC_READ_BUFFER: + SM_DBG5(("smsatIOStart: SCSIOPC_READ_BUFFER\n")); + status = smsatReadBuffer( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + + break; + + case SCSIOPC_WRITE_BUFFER: + SM_DBG5(("smsatIOStart: SCSIOPC_WRITE_BUFFER\n")); + status = smsatWriteBuffer( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + + break; + + case SCSIOPC_REASSIGN_BLOCKS: + SM_DBG5(("smsatIOStart: SCSIOPC_REASSIGN_BLOCKS\n")); + status = smsatReassignBlocks( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + + break; + + case SCSIOPC_ATA_PASS_THROUGH12: /* fall through */ + case SCSIOPC_ATA_PASS_THROUGH16: + SM_DBG5(("smsatIOStart: SCSIOPC_ATA_PASS_THROUGH\n")); + status = smsatPassthrough( smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + satIOContext); + break; + + default: + /* Not implemented SCSI cmd, set up error response */ + SM_DBG1(("smsatIOStart: unsupported SCSI cdb[0]=0x%x did=%d !!!\n", + scsiCmnd->cdb[0], pSatDevData->id)); + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_COMMAND, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + status = SM_RC_SUCCESS; + + break; + + } /* end switch */ + } + + if (status == SM_RC_BUSY || status == SM_RC_DEVICE_BUSY) + { + SM_DBG1(("smsatIOStart: BUSY did %d!!!\n", pSatDevData->id)); + SM_DBG2(("smsatIOStart: LL is busy or target queue is full\n")); + SM_DBG2(("smsatIOStart: device %p satPendingIO %d satNCQMaxIO %d\n",pSatDevData, pSatDevData->satPendingIO, pSatDevData->satNCQMaxIO )); + SM_DBG2(("smsatIOStart: device %p satPendingNCQIO %d satPendingNONNCQIO %d\n",pSatDevData, pSatDevData->satPendingNCQIO, pSatDevData->satPendingNONNCQIO)); + pSatIntIo = satIOContext->satIntIoContext; + + /*smEnqueueIO(smRoot, satIOContext);*/ + + /* interal structure free */ + smsatFreeIntIoResource( smRoot, + pSatDevData, + pSatIntIo); + } + + return status; +} + +osGLOBAL void +smsatSetSensePayload( + smScsiRspSense_t *pSense, + bit8 SnsKey, + bit32 SnsInfo, + bit16 SnsCode, + smSatIOContext_t *satIOContext) +{ + /* for fixed format sense data, SPC-4, p37 */ + bit32 i; + bit32 senseLength; + bit8 tmp = 0; + + SM_DBG2(("smsatSetSensePayload: start\n")); + + senseLength = sizeof(smScsiRspSense_t); + + /* zero out the data area */ + for (i=0;i< senseLength;i++) + { + ((bit8*)pSense)[i] = 0; + } + + /* + * SCSI Sense Data part of response data + */ + pSense->snsRespCode = 0x70; /* 0xC0 == vendor specific */ + /* 0x70 == standard current error */ + pSense->senseKey = SnsKey; + /* + * Put sense info in scsi order format + */ + pSense->info[0] = (bit8)((SnsInfo >> 24) & 0xff); + pSense->info[1] = (bit8)((SnsInfo >> 16) & 0xff); + pSense->info[2] = (bit8)((SnsInfo >> 8) & 0xff); + pSense->info[3] = (bit8)((SnsInfo) & 0xff); + pSense->addSenseLen = 11; /* fixed size of sense data = 18 */ + pSense->addSenseCode = (bit8)((SnsCode >> 8) & 0xFF); + pSense->senseQual = (bit8)(SnsCode & 0xFF); + /* + * Set pointer in scsi status + */ + switch(SnsKey) + { + /* + * set illegal request sense key specific error in cdb, no bit pointer + */ + case SCSI_SNSKEY_ILLEGAL_REQUEST: + pSense->skeySpecific[0] = 0xC8; + break; + + default: + break; + } + /* setting sense data length */ + if (satIOContext != agNULL) + { + satIOContext->pSmSenseData->senseLen = 18; + } + else + { + SM_DBG1(("smsatSetSensePayload: satIOContext is NULL!!!\n")); + } + + /* Only for SCSI_SNSCODE_ATA_PASS_THROUGH_INFORMATION_AVAILABLE */ + if (SnsCode == SCSI_SNSCODE_ATA_PASS_THROUGH_INFORMATION_AVAILABLE) + { + /* filling in COMMAND-SPECIFIC INFORMATION */ + tmp = satIOContext->extend << 7 | satIOContext->Sector_Cnt_Upper_Nonzero << 6 | satIOContext->LBA_Upper_Nonzero << 5; + SM_DBG3(("smsatSetSensePayload: extend 0x%x Sector_Cnt_Upper_Nonzero 0x%x LBA_Upper_Nonzero 0x%x\n", + satIOContext->extend, satIOContext->Sector_Cnt_Upper_Nonzero, satIOContext->LBA_Upper_Nonzero)); + SM_DBG3(("smsatSetSensePayload: tmp 0x%x\n", tmp)); + pSense->cmdSpecific[0] = tmp; + pSense->cmdSpecific[1] = satIOContext->LBAHigh07; + pSense->cmdSpecific[2] = satIOContext->LBAMid07; + pSense->cmdSpecific[3] = satIOContext->LBALow07; +// smhexdump("smsatSetSensePayload: cmdSpecific",(bit8 *)pSense->cmdSpecific, 4); +// smhexdump("smsatSetSensePayload: info",(bit8 *)pSense->info, 4); + + } + return; +} + +/***************************************************************************** +*! \brief smsatDecodeSATADeviceType +* +* This routine decodes ATA signature +* +* \param pSignature: ATA signature +* +* +* \return: +* TRUE if ATA signature +* FALSE otherwise +* +*****************************************************************************/ +/* + ATA p65 + PM p65 + SATAII p79, p80 + */ +GLOBAL bit32 +smsatDecodeSATADeviceType( + bit8 *pSignature + ) +{ + bit32 deviceType = UNKNOWN_DEVICE; + + if ( (pSignature)[0] == 0x01 && (pSignature)[1] == 0x01 + && (pSignature)[2] == 0x00 && (pSignature)[3] == 0x00 + && (pSignature)[4] == 0xA0 ) /* this is the signature of a Hitachi SATA HDD*/ + { + deviceType = SATA_ATA_DEVICE; + } + else if ( (pSignature)[0] == 0x01 && (pSignature)[1] == 0x01 + && (pSignature)[2] == 0x00 && (pSignature)[3] == 0x00 + && (pSignature)[4] == 0x00 ) + { + deviceType = SATA_ATA_DEVICE; + } + else if ( (pSignature)[0] == 0x01 && (pSignature)[1] == 0x01 + && (pSignature)[2] == 0x14 && (pSignature)[3] == 0xEB + && ( (pSignature)[4] == 0x00 || (pSignature)[4] == 0x10) ) + { + deviceType = SATA_ATAPI_DEVICE; + } + else if ( (pSignature)[0] == 0x01 && (pSignature)[1] == 0x01 + && (pSignature)[2] == 0x69 && (pSignature)[3] == 0x96 + && (pSignature)[4] == 0x00 ) + { + deviceType = SATA_PM_DEVICE; + } + else if ( (pSignature)[0] == 0x01 && (pSignature)[1] == 0x01 + && (pSignature)[2] == 0x3C && (pSignature)[3] == 0xC3 + && (pSignature)[4] == 0x00 ) + { + deviceType = SATA_SEMB_DEVICE; + } + else if ( (pSignature)[0] == 0xFF && (pSignature)[1] == 0xFF + && (pSignature)[2] == 0xFF && (pSignature)[3] == 0xFF + && (pSignature)[4] == 0xFF ) + { + deviceType = SATA_SEMB_WO_SEP_DEVICE; + } + + return deviceType; +} + + +/*****************************************************************************/ +/*! \brief SAT implementation for ATAPI Packet Command. + * + * SAT implementation for ATAPI Packet and send FIS request to LL layer. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param smSatIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e smIOSuccess: I/O request successfully initiated. + * - \e smIOBusy: No resources available, try again later. + * - \e smIONoDevice: Invalid device handle. + * - \e smIOError: Other errors. + */ +/*****************************************************************************/ +osGLOBAL bit32 +smsatPacket( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_D2H_PKT; + smDeviceData_t *pSatDevData; + smIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &smScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + SM_DBG3(("smsatPacket: start, SCSI CDB is 0x%X %X %X %X %X %X %X %X %X %X %X %X\n", + scsiCmnd->cdb[0],scsiCmnd->cdb[1],scsiCmnd->cdb[2],scsiCmnd->cdb[3], + scsiCmnd->cdb[4],scsiCmnd->cdb[5],scsiCmnd->cdb[6],scsiCmnd->cdb[7], + scsiCmnd->cdb[8],scsiCmnd->cdb[9],scsiCmnd->cdb[10],scsiCmnd->cdb[11])); + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set 1*/ + fis->h.command = SAT_PACKET; /* 0xA0 */ + if (pSatDevData->satDMADIRSupport) /* DMADIR enabled*/ + { + fis->h.features = (smScsiRequest->dataDirection == smDirectionIn)? 0x04 : 0; /* 1 for D2H, 0 for H2D */ + } + else + { + fis->h.features = 0; /* FIS reserve */ + } + + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /*DMA transfer mode*/ + fis->h.features |= 0x01; + } + else + { + /*PIO transfer mode*/ + fis->h.features |= 0x0; + } + /* Byte count low and byte count high */ + if ( scsiCmnd->expDataLength > 0xFFFF ) + { + fis->d.lbaMid = 0xFF; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0xFF; /* FIS LBA (23:16) */ + } + else + { + fis->d.lbaMid = (bit8)scsiCmnd->expDataLength; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = (bit8)(scsiCmnd->expDataLength>>8); /* FIS LBA (23:16) */ + } + + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.device = 0; /* FIS LBA (27:24) and FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + satIOContext->ATACmd = SAT_PACKET; + + if (smScsiRequest->dataDirection == smDirectionIn) + { + agRequestType = AGSA_SATA_PROTOCOL_D2H_PKT; + } + else + { + agRequestType = AGSA_SATA_PROTOCOL_H2D_PKT; + } + + satIOContext->satCompleteCB = &smsatPacketCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart(smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + SM_DBG3(("smsatPacket: return\n")); + return (status); +} + +/*****************************************************************************/ +/*! \brief SAT implementation for smsatSetFeaturePIO. + * + * This function creates Set Features fis and sends the request to LL layer + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param smSatIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e smIOSuccess: I/O request successfully initiated. + * - \e smIOBusy: No resources available, try again later. + * - \e smIONoDevice: Invalid device handle. + * - \e smIOError: Other errors. + */ +/*****************************************************************************/ +osGLOBAL bit32 +smsatSetFeaturesPIO( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status = SM_RC_FAILURE; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; + + fis = satIOContext->pFis; + SM_DBG2(("smsatSetFeaturesPIO: start\n")); + /* + * Send the Set Features command. + */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_SET_FEATURES; /* 0xEF */ + fis->h.features = 0x03; /* set transfer mode */ + fis->d.lbaLow = 0; + fis->d.lbaMid = 0; + fis->d.lbaHigh = 0; + fis->d.device = 0; + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + fis->d.sectorCount = 0x0C; /*enable PIO transfer mode */ + satIOContext->satCompleteCB = &smsatSetFeaturesPIOCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + SM_DBG2(("smsatSetFeaturesPIO: return\n")); + /* debugging code */ + if (smIORequest->tdData == smIORequest->smData) + { + SM_DBG1(("smsatSetFeaturesPIO: incorrect smIORequest\n")); + } + + return status; +} +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI REQUEST SENSE to ATAPI device. + * + * SAT implementation for SCSI REQUEST SENSE. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param smSatIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e smIOSuccess: I/O request successfully initiated. + * - \e smIOBusy: No resources available, try again later. + * - \e smIONoDevice: Invalid device handle. + * - \e smIOError: Other errors. + */ +/*****************************************************************************/ +osGLOBAL bit32 +smsatRequestSenseForATAPI( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_D2H_PKT; + smDeviceData_t *pSatDevData; + smIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &smScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + scsiCmnd->cdb[0] = SCSIOPC_REQUEST_SENSE; + scsiCmnd->cdb[1] = 0; + scsiCmnd->cdb[2] = 0; + scsiCmnd->cdb[3] = 0; + scsiCmnd->cdb[4] = (bit8)scsiCmnd->expDataLength; + scsiCmnd->cdb[5] = 0; + SM_DBG3(("smsatRequestSenseForATAPI: start, SCSI CDB is 0x%X %X %X %X %X %X %X %X %X %X %X %X\n", + scsiCmnd->cdb[0],scsiCmnd->cdb[1],scsiCmnd->cdb[2],scsiCmnd->cdb[3], + scsiCmnd->cdb[4],scsiCmnd->cdb[5],scsiCmnd->cdb[6],scsiCmnd->cdb[7], + scsiCmnd->cdb[8],scsiCmnd->cdb[9],scsiCmnd->cdb[10],scsiCmnd->cdb[11])); + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set 1*/ + fis->h.command = SAT_PACKET; /* 0xA0 */ + if (pSatDevData->satDMADIRSupport) /* DMADIR enabled*/ + { + fis->h.features = (smScsiRequest->dataDirection == smDirectionIn)? 0x04 : 0; /* 1 for D2H, 0 for H2D */ + } + else + { + fis->h.features = 0; /* FIS reserve */ + } + + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + fis->h.features |= 0x01; + } + else + { + fis->h.features |= 0x0; + } + + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = (bit8)scsiCmnd->expDataLength; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = (bit8)(scsiCmnd->expDataLength>>8); /* FIS LBA (23:16) */ + fis->d.device = 0; /* FIS LBA (27:24) and FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + satIOContext->ATACmd = SAT_PACKET; + + agRequestType = AGSA_SATA_PROTOCOL_D2H_PKT; + + + satIOContext->satCompleteCB = &smsatRequestSenseForATAPICB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + SM_DBG3(("smsatRequestSenseForATAPI: return\n")); + return (status); +} +/*****************************************************************************/ +/*! \brief SAT implementation for smsatDeviceReset. + * + * This function creates DEVICE RESET fis and sends the request to LL layer + * + * \param smRoot: Pointer to TISA initiator driver/port instance. + * \param smIORequest: Pointer to TISA I/O request context for this I/O. + * \param smDeviceHandle: Pointer to TISA device handle for this I/O. + * \param smScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param smSatIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e smIOSuccess: I/O request successfully initiated. + * - \e smIOBusy: No resources available, try again later. + * - \e smIONoDevice: Invalid device handle. + * - \e smIOError: Other errors. + */ +/*****************************************************************************/ +osGLOBAL bit32 +smsatDeviceReset( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; + + fis = satIOContext->pFis; + SM_DBG3(("smsatDeviceReset: start\n")); + /* + * Send the Execute Device Diagnostic command. + */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_DEVICE_RESET; /* 0x08 */ + fis->h.features = 0; + fis->d.lbaLow = 0; + fis->d.lbaMid = 0; + fis->d.lbaHigh = 0; + fis->d.device = 0; + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DEV_RESET; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatDeviceResetCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + SM_DBG3(("smsatDeviceReset: return\n")); + + return status; +} + + +/*****************************************************************************/ +/*! \brief SAT implementation for smsatExecuteDeviceDiagnostic. + * + * This function creates Execute Device Diagnostic fis and sends the request to LL layer + * + * \param smRoot: Pointer to TISA initiator driver/port instance. + * \param smIORequest: Pointer to TISA I/O request context for this I/O. + * \param smDeviceHandle: Pointer to TISA device handle for this I/O. + * \param smScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param smSatIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e smIOSuccess: I/O request successfully initiated. + * - \e smIOBusy: No resources available, try again later. + * - \e smIONoDevice: Invalid device handle. + * - \e smIOError: Other errors. + */ +/*****************************************************************************/ +osGLOBAL bit32 +smsatExecuteDeviceDiagnostic( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; + + fis = satIOContext->pFis; + SM_DBG3(("smsatExecuteDeviceDiagnostic: start\n")); + /* + * Send the Execute Device Diagnostic command. + */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_EXECUTE_DEVICE_DIAGNOSTIC; /* 0x90 */ + fis->h.features = 0; + fis->d.lbaLow = 0; + fis->d.lbaMid = 0; + fis->d.lbaHigh = 0; + fis->d.device = 0; + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatExecuteDeviceDiagnosticCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + SM_DBG3(("smsatExecuteDeviceDiagnostic: return\n")); + + return status; +} + + +osGLOBAL void +smsatSetDeferredSensePayload( + smScsiRspSense_t *pSense, + bit8 SnsKey, + bit32 SnsInfo, + bit16 SnsCode, + smSatIOContext_t *satIOContext + ) +{ + SM_DBG2(("smsatSetDeferredSensePayload: start\n")); + return; +} + + +GLOBAL bit32 +smsatRead6( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_DMA_READ; + smDeviceData_t *pSatDevData; + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 lba = 0; + bit16 tl = 0; + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &smScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + SM_DBG2(("smsatRead6: start\n")); + + /* no FUA checking since read6 */ + + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[5] & SCSI_NACA_MASK) || (scsiCmnd->cdb[5] & SCSI_LINK_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatRead6: return control!!!\n")); + return SM_RC_SUCCESS; + } + + /* cbd6; computing LBA and transfer length */ + lba = (((scsiCmnd->cdb[1]) & 0x1f) << (8*2)) + + (scsiCmnd->cdb[2] << 8) + scsiCmnd->cdb[3]; + tl = scsiCmnd->cdb[4]; + + /* Table 34, 9.1, p 46 */ + /* + note: As of 2/10/2006, no support for DMA QUEUED + */ + + /* + Table 34, 9.1, p 46, b + When no 48-bit addressing support or NCQ, if LBA is beyond (2^28 - 1), + return check condition + */ + if (pSatDevData->satNCQ != agTRUE && + pSatDevData->sat48BitSupport != agTRUE + ) + { + if (lba > SAT_TR_LBA_LIMIT - 1) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatRead6: return LBA out of range!!!\n")); + return SM_RC_SUCCESS; + } + } + + /* case 1 and 2 */ + if (lba + tl <= SAT_TR_LBA_LIMIT) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 2 */ + /* READ DMA*/ + SM_DBG5(("smsatRead6: case 2\n")); + + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_DMA; /* 0xC8 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = (bit8)((scsiCmnd->cdb[1]) & 0x1f); /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + if (tl == 0) + { + /* temporary fix */ + fis->d.sectorCount = 0xff; /* FIS sector count (7:0) */ + } + else + { + fis->d.sectorCount = scsiCmnd->cdb[4]; /* FIS sector count (7:0) */ + } + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_READ; + } + else + { + /* case 1 */ + /* READ SECTORS for easier implemetation */ + SM_DBG5(("smsatRead6: case 1\n")); + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_SECTORS; /* 0x20 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = (bit8)((scsiCmnd->cdb[1]) & 0x1f); /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + if (tl == 0) + { + /* temporary fix */ + fis->d.sectorCount = 0xff; /* FIS sector count (7:0) */ + } + else + { + fis->d.sectorCount = scsiCmnd->cdb[4]; /* FIS sector count (7:0) */ + } + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + + } + } + + /* case 3 and 4 */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 3 */ + /* READ DMA EXT only */ + SM_DBG5(("smsatRead6: case 3\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_DMA_EXT; /* 0x25 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = (bit8)((scsiCmnd->cdb[1]) & 0x1f); /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = 0; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + if (tl == 0) + { + /* sector count is 256, 0x100*/ + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0x01; /* FIS sector count (15:8) */ + } + else + { + fis->d.sectorCount = scsiCmnd->cdb[4]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + } + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_READ; + } + else + { + /* case 4 */ + /* READ SECTORS EXT for easier implemetation */ + SM_DBG5(("smsatRead6: case 4\n")); + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_SECTORS_EXT; /* 0x24 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = (bit8)((scsiCmnd->cdb[1]) & 0x1f); /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = 0; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + if (tl == 0) + { + /* sector count is 256, 0x100*/ + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0x01; /* FIS sector count (15:8) */ + } + else + { + fis->d.sectorCount = scsiCmnd->cdb[4]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + } + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + } + } + + /* case 5 */ + if (pSatDevData->satNCQ == agTRUE) + { + /* READ FPDMA QUEUED */ + if (pSatDevData->sat48BitSupport != agTRUE) + { + /* sanity check */ + SM_DBG1(("smsatRead6: case 5 !!! error NCQ but 28 bit address support!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + SM_DBG5(("smsatRead6: case 5\n")); + + /* Support 48-bit FPDMA addressing, use READ FPDMA QUEUE command */ + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_FPDMA_QUEUED; /* 0x60 */ + fis->d.lbaLow = scsiCmnd->cdb[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = (bit8)((scsiCmnd->cdb[1]) & 0x1f); /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS FUA clear */ + fis->d.lbaLowExp = 0; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + if (tl == 0) + { + /* sector count is 256, 0x100*/ + fis->h.features = 0; /* FIS sector count (7:0) */ + fis->d.featuresExp = 0x01; /* FIS sector count (15:8) */ + } + else + { + fis->h.features = scsiCmnd->cdb[4]; /* FIS sector count (7:0) */ + fis->d.featuresExp = 0; /* FIS sector count (15:8) */ + } + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_READ; + } + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatNonChainedDataIOCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + return (status); + +} + +osGLOBAL FORCEINLINE bit32 +smsatRead10( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + smDeviceData_t *pSatDevData = satIOContext->pSatDevData; + smScsiRspSense_t *pSense = satIOContext->pSense; + smIniScsiCmnd_t *scsiCmnd = &smScsiRequest->scsiCmnd; + agsaFisRegHostToDevice_t *fis = satIOContext->pFis; + + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_DMA_READ; + bit32 lba = 0; + bit32 tl = 0; + bit32 LoopNum = 1; + bit8 LBA[8]; + bit8 TL[8]; + bit32 AllChk = agFALSE; /* lba, lba+tl check against ATA limit and Disk capacity */ + + SM_DBG2(("smsatRead10: start\n")); + SM_DBG2(("smsatRead10: pSatDevData did=%d\n", pSatDevData->id)); + // smhexdump("smsatRead10", (bit8 *)scsiCmnd->cdb, 10); + + /* checking FUA_NV */ + if (scsiCmnd->cdb[1] & SCSI_FUA_NV_MASK) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatRead10: return FUA_NV!!!\n")); + return SM_RC_SUCCESS; + + } + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[9] & SCSI_NACA_MASK) || (scsiCmnd->cdb[9] & SCSI_LINK_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatRead10: return control!!!\n")); + return SM_RC_SUCCESS; + } + /* + sm_memset(LBA, 0, sizeof(LBA)); + sm_memset(TL, 0, sizeof(TL)); + */ + /* do not use memcpy due to indexing in LBA and TL */ + LBA[0] = 0; /* MSB */ + LBA[1] = 0; + LBA[2] = 0; + LBA[3] = 0; + LBA[4] = scsiCmnd->cdb[2]; + LBA[5] = scsiCmnd->cdb[3]; + LBA[6] = scsiCmnd->cdb[4]; + LBA[7] = scsiCmnd->cdb[5]; /* LSB */ + + TL[0] = 0; + TL[1] = 0; + TL[2] = 0; + TL[3] = 0; + TL[4] = 0; + TL[5] = 0; + TL[6] = scsiCmnd->cdb[7]; + TL[7] = scsiCmnd->cdb[8]; /* LSB */ + + + /* cbd10; computing LBA and transfer length */ + lba = (scsiCmnd->cdb[2] << 24) + (scsiCmnd->cdb[3] << 16) + + (scsiCmnd->cdb[4] << 8) + scsiCmnd->cdb[5]; + tl = (scsiCmnd->cdb[7] << 8) + scsiCmnd->cdb[8]; + + + SM_DBG5(("smsatRead10: lba %d functioned lba %d\n", lba, smsatComputeCDB10LBA(satIOContext))); + SM_DBG5(("smsatRead10: lba 0x%x functioned lba 0x%x\n", lba, smsatComputeCDB10LBA(satIOContext))); + SM_DBG5(("smsatRead10: tl %d functioned tl %d\n", tl, smsatComputeCDB10TL(satIOContext))); + + /* Table 34, 9.1, p 46 */ + /* + note: As of 2/10/2006, no support for DMA QUEUED + */ + + /* + Table 34, 9.1, p 46, b + When no 48-bit addressing support or NCQ, if LBA is beyond (2^28 - 1), + return check condition + */ + + if (pSatDevData->satNCQ != agTRUE && + pSatDevData->sat48BitSupport != agTRUE + ) + { + AllChk = smsatCheckLimit(LBA, TL, agFALSE, pSatDevData); + if (AllChk) + { + SM_DBG1(("smsatRead10: return LBA out of range, not EXT!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + return SM_RC_SUCCESS; + } + } + else + { + AllChk = smsatCheckLimit(LBA, TL, agTRUE, pSatDevData); + if (AllChk) + { + SM_DBG1(("smsatRead10: return LBA out of range, EXT!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + return SM_RC_SUCCESS; + } + } + /* case 5 */ + if (pSatDevData->satNCQ == agTRUE) + { + /* READ FPDMA QUEUED */ + if (pSatDevData->sat48BitSupport != agTRUE) + { + SM_DBG1(("smsatRead10: case 5 !!! error NCQ but 28 bit address support!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + + SM_DBG6(("smsatRead10: case 5\n")); + + /* Support 48-bit FPDMA addressing, use READ FPDMA QUEUE command */ + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_FPDMA_QUEUED; /* 0x60 */ + fis->h.features = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + + /* Check FUA bit */ + if (scsiCmnd->cdb[1] & SCSI_READ10_FUA_MASK) + fis->d.device = 0xC0; /* FIS FUA set */ + else + fis->d.device = 0x40; /* FIS FUA clear */ + + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = scsiCmnd->cdb[7]; /* FIS sector count (15:8) */ + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_READ; + satIOContext->ATACmd = SAT_READ_FPDMA_QUEUED; + } + else if (pSatDevData->sat48BitSupport == agTRUE) /* case 3 and 4 */ + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 3 */ + /* READ DMA EXT */ + SM_DBG5(("smsatRead10: case 3\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_DMA_EXT; /* 0x25 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[7]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_READ; + satIOContext->ATACmd = SAT_READ_DMA_EXT; + + } + else + { + /* case 4 */ + /* READ MULTIPLE EXT or READ SECTOR(S) EXT or READ VERIFY SECTOR(S) EXT*/ + /* READ SECTORS EXT for easier implemetation */ + SM_DBG5(("smsatRead10: case 4\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + /* Check FUA bit */ + if (scsiCmnd->cdb[1] & SCSI_READ10_FUA_MASK) + { + + /* for now, no support for FUA */ + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + + fis->h.command = SAT_READ_SECTORS_EXT; /* 0x24 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[7]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + satIOContext->ATACmd = SAT_READ_SECTORS_EXT; + } + } + else/* case 1 and 2 */ + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 2 */ + /* READ DMA*/ + /* in case that we can't fit the transfer length, we need to make it fit by sending multiple ATA cmnds */ + SM_DBG5(("smsatRead10: case 2\n")); + + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_DMA; /* 0xC8 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = + (bit8)((0x4 << 4) | (scsiCmnd->cdb[2] & 0xF)); /* FIS LBA (27:24) and FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + + agRequestType = AGSA_SATA_PROTOCOL_DMA_READ; + satIOContext->ATACmd = SAT_READ_DMA; + } + else + { + /* case 1 */ + /* READ MULTIPLE or READ SECTOR(S) */ + /* READ SECTORS for easier implemetation */ + /* in case that we can't fit the transfer length, we need to make it fit by sending multiple ATA cmnds */ + SM_DBG5(("smsatRead10: case 1\n")); + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_SECTORS; /* 0x20 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = + (bit8)((0x4 << 4) | (scsiCmnd->cdb[2] & 0xF)); /* FIS LBA (27:24) and FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + satIOContext->ATACmd = SAT_READ_SECTORS; + } + } + // smhexdump("satRead10 final fis", (bit8 *)fis, sizeof(agsaFisRegHostToDevice_t)); + + /* saves the current LBA and orginal TL */ + satIOContext->currentLBA = lba; + satIOContext->OrgTL = tl; + + /* + computing number of loop and remainder for tl + 0xFF in case not ext + 0xFFFF in case EXT + */ + if (fis->h.command == SAT_READ_SECTORS || fis->h.command == SAT_READ_DMA) + { + LoopNum = smsatComputeLoopNum(tl, 0x100); + } + else + { + /* SAT_READ_FPDMA_QUEUED */ + /* SAT_READ_SECTORS_EXT, SAT_READ_DMA_EXT */ + LoopNum = smsatComputeLoopNum(tl, 0xFFFF); + } + + satIOContext->LoopNum = LoopNum; + + /* Initialize CB for SATA completion. + */ + if (LoopNum == 1) + { + SM_DBG5(("smsatRead10: NON CHAINED data\n")); + satIOContext->satCompleteCB = &smsatNonChainedDataIOCB; + } + else + { + SM_DBG2(("smsatRead10: CHAINED data!!!\n")); + + /* re-setting tl */ + if (fis->h.command == SAT_READ_SECTORS || fis->h.command == SAT_READ_DMA) + { + fis->d.sectorCount = 0x0; + smsatSplitSGL(smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext, + NON_BIT48_ADDRESS_TL_LIMIT*SATA_SECTOR_SIZE, /* 0x100 * 0x200 */ + (satIOContext->OrgTL)*SATA_SECTOR_SIZE, + agTRUE); + } + else if (fis->h.command == SAT_READ_SECTORS_EXT || fis->h.command == SAT_READ_DMA_EXT) + { + /* SAT_READ_SECTORS_EXT, SAT_READ_DMA_EXT */ + fis->d.sectorCount = 0xFF; + fis->d.sectorCountExp = 0xFF; + smsatSplitSGL(smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext, + BIT48_ADDRESS_TL_LIMIT*SATA_SECTOR_SIZE, /* 0xFFFF * 0x200 */ + (satIOContext->OrgTL)*SATA_SECTOR_SIZE, + agTRUE); + } + else + { + /* SAT_READ_FPDMA_QUEUED */ + fis->h.features = 0xFF; + fis->d.featuresExp = 0xFF; + smsatSplitSGL(smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext, + BIT48_ADDRESS_TL_LIMIT*SATA_SECTOR_SIZE, /* 0xFFFF * 0x200 */ + (satIOContext->OrgTL)*SATA_SECTOR_SIZE, + agTRUE); + } + + /* chained data */ + satIOContext->satCompleteCB = &smsatChainedDataIOCB; + + } + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + SM_DBG5(("smsatRead10: return\n")); + return (status); + +} + +osGLOBAL bit32 +smsatRead12( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_DMA_READ; + smDeviceData_t *pSatDevData; + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 lba = 0; + bit32 tl = 0; + bit32 LoopNum = 1; + bit8 LBA[8]; + bit8 TL[8]; + bit32 AllChk = agFALSE; /* lba, lba+tl check against ATA limit and Disk capacity */ + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &smScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + SM_DBG5(("smsatRead12: start\n")); + + /* checking FUA_NV */ + if (scsiCmnd->cdb[1] & SCSI_FUA_NV_MASK) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatRead12: return FUA_NV!!!\n")); + return SM_RC_SUCCESS; + + } + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[11] & SCSI_NACA_MASK) || (scsiCmnd->cdb[11] & SCSI_LINK_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatRead12: return control!!!\n")); + return SM_RC_SUCCESS; + } + + sm_memset(LBA, 0, sizeof(LBA)); + sm_memset(TL, 0, sizeof(TL)); + + /* do not use memcpy due to indexing in LBA and TL */ + LBA[0] = 0; /* MSB */ + LBA[1] = 0; + LBA[2] = 0; + LBA[3] = 0; + LBA[4] = scsiCmnd->cdb[2]; + LBA[5] = scsiCmnd->cdb[3]; + LBA[6] = scsiCmnd->cdb[4]; + LBA[7] = scsiCmnd->cdb[5]; /* LSB */ + + TL[0] = 0; /* MSB */ + TL[1] = 0; + TL[2] = 0; + TL[3] = 0; + TL[4] = scsiCmnd->cdb[6]; + TL[5] = scsiCmnd->cdb[7]; + TL[6] = scsiCmnd->cdb[8]; + TL[7] = scsiCmnd->cdb[9]; /* LSB */ + + + lba = smsatComputeCDB12LBA(satIOContext); + tl = smsatComputeCDB12TL(satIOContext); + + /* Table 34, 9.1, p 46 */ + /* + note: As of 2/10/2006, no support for DMA QUEUED + */ + + /* + Table 34, 9.1, p 46, b + When no 48-bit addressing support or NCQ, if LBA is beyond (2^28 - 1), + return check condition + */ + if (pSatDevData->satNCQ != agTRUE && + pSatDevData->sat48BitSupport != agTRUE + ) + { + + AllChk = smsatCheckLimit(LBA, TL, agFALSE, pSatDevData); + if (AllChk) + { + SM_DBG1(("smsatRead12: return LBA out of range, not EXT!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + return SM_RC_SUCCESS; + } + } + else + { + AllChk = smsatCheckLimit(LBA, TL, agTRUE, pSatDevData); + if (AllChk) + { + SM_DBG1(("smsatRead12: return LBA out of range, EXT!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + return SM_RC_SUCCESS; + } + } + + /* case 1 and 2 */ + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 2 */ + /* READ DMA*/ + /* in case that we can't fit the transfer length, + we need to make it fit by sending multiple ATA cmnds */ + SM_DBG5(("smsatRead12: case 2\n")); + + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_DMA; /* 0xC8 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = + (bit8)((0x4 << 4) | (scsiCmnd->cdb[2] & 0xF)); /* FIS LBA (27:24) and FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[9]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + + agRequestType = AGSA_SATA_PROTOCOL_DMA_READ; + satIOContext->ATACmd = SAT_READ_DMA; + } + else + { + /* case 1 */ + /* READ MULTIPLE or READ SECTOR(S) */ + /* READ SECTORS for easier implemetation */ + /* can't fit the transfer length but need to make it fit by sending multiple*/ + SM_DBG5(("smsatRead12: case 1\n")); + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_SECTORS; /* 0x20 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = + (bit8)((0x4 << 4) | (scsiCmnd->cdb[2] & 0xF)); /* FIS LBA (27:24) and FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[9]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + satIOContext->ATACmd = SAT_READ_SECTORS; + } + + /* case 3 and 4 */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 3 */ + /* READ DMA EXT */ + SM_DBG5(("smsatRead12: case 3\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_DMA_EXT; /* 0x25 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[9]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[8]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_READ; + satIOContext->ATACmd = SAT_READ_DMA_EXT; + + } + else + { + /* case 4 */ + /* READ MULTIPLE EXT or READ SECTOR(S) EXT or READ VERIFY SECTOR(S) EXT*/ + /* READ SECTORS EXT for easier implemetation */ + SM_DBG5(("smsatRead12: case 4\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + /* Check FUA bit */ + if (scsiCmnd->cdb[1] & SCSI_READ12_FUA_MASK) + { + + /* for now, no support for FUA */ + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + + fis->h.command = SAT_READ_SECTORS_EXT; /* 0x24 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[9]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[8]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + satIOContext->ATACmd = SAT_READ_SECTORS_EXT; + } + } + + /* case 5 */ + if (pSatDevData->satNCQ == agTRUE) + { + /* READ FPDMA QUEUED */ + if (pSatDevData->sat48BitSupport != agTRUE) + { + SM_DBG1(("smsatRead12: case 5 !!! error NCQ but 28 bit address support!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + + SM_DBG6(("smsatRead12: case 5\n")); + + /* Support 48-bit FPDMA addressing, use READ FPDMA QUEUE command */ + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_FPDMA_QUEUED; /* 0x60 */ + fis->h.features = scsiCmnd->cdb[9]; /* FIS sector count (7:0) */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + + /* Check FUA bit */ + if (scsiCmnd->cdb[1] & SCSI_READ12_FUA_MASK) + fis->d.device = 0xC0; /* FIS FUA set */ + else + fis->d.device = 0x40; /* FIS FUA clear */ + + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = scsiCmnd->cdb[8]; /* FIS sector count (15:8) */ + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_READ; + satIOContext->ATACmd = SAT_READ_FPDMA_QUEUED; + } + + /* saves the current LBA and orginal TL */ + satIOContext->currentLBA = lba; + satIOContext->OrgTL = tl; + + /* + computing number of loop and remainder for tl + 0xFF in case not ext + 0xFFFF in case EXT + */ + if (fis->h.command == SAT_READ_SECTORS || fis->h.command == SAT_READ_DMA) + { + LoopNum = smsatComputeLoopNum(tl, 0xFF); + } + else if (fis->h.command == SAT_READ_SECTORS_EXT || fis->h.command == SAT_READ_DMA_EXT) + { + /* SAT_READ_SECTORS_EXT, SAT_READ_DMA_EXT */ + LoopNum = smsatComputeLoopNum(tl, 0xFFFF); + } + else + { + /* SAT_READ_FPDMA_QUEUEDK */ + LoopNum = smsatComputeLoopNum(tl, 0xFFFF); + } + + satIOContext->LoopNum = LoopNum; + + if (LoopNum == 1) + { + SM_DBG5(("smsatRead12: NON CHAINED data\n")); + satIOContext->satCompleteCB = &smsatNonChainedDataIOCB; + } + else + { + SM_DBG1(("smsatRead12: CHAINED data\n")); + /* re-setting tl */ + if (fis->h.command == SAT_READ_SECTORS || fis->h.command == SAT_READ_DMA) + { + fis->d.sectorCount = 0xFF; + } + else if (fis->h.command == SAT_READ_SECTORS_EXT || fis->h.command == SAT_READ_DMA_EXT) + { + /* SAT_READ_SECTORS_EXT, SAT_READ_DMA_EXT */ + fis->d.sectorCount = 0xFF; + fis->d.sectorCountExp = 0xFF; + } + else + { + /* SAT_READ_FPDMA_QUEUED */ + fis->h.features = 0xFF; + fis->d.featuresExp = 0xFF; + } + + /* chained data */ + satIOContext->satCompleteCB = &smsatChainedDataIOCB; + } + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + SM_DBG5(("smsatRead12: return\n")); + return (status); +} + +osGLOBAL bit32 +smsatRead16( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_DMA_READ; + smDeviceData_t *pSatDevData; + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 lba = 0; + bit32 tl = 0; + bit32 LoopNum = 1; + bit8 LBA[8]; + bit8 TL[8]; + bit32 AllChk = agFALSE; /* lba, lba+tl check against ATA limit and Disk capacity */ +// bit32 limitExtChk = agFALSE; /* lba limit check for bit48 addressing check */ + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &smScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + SM_DBG5(("smsatRead16: start\n")); + + /* checking FUA_NV */ + if (scsiCmnd->cdb[1] & SCSI_FUA_NV_MASK) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatRead16: return FUA_NV!!!\n")); + return SM_RC_SUCCESS; + + } + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[15] & SCSI_NACA_MASK) || (scsiCmnd->cdb[15] & SCSI_LINK_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatRead16: return control!!!\n")); + return SM_RC_SUCCESS; + } + + + sm_memset(LBA, 0, sizeof(LBA)); + sm_memset(TL, 0, sizeof(TL)); + + + /* do not use memcpy due to indexing in LBA and TL */ + LBA[0] = scsiCmnd->cdb[2]; /* MSB */ + LBA[1] = scsiCmnd->cdb[3]; + LBA[2] = scsiCmnd->cdb[4]; + LBA[3] = scsiCmnd->cdb[5]; + LBA[4] = scsiCmnd->cdb[6]; + LBA[5] = scsiCmnd->cdb[7]; + LBA[6] = scsiCmnd->cdb[8]; + LBA[7] = scsiCmnd->cdb[9]; /* LSB */ + + TL[0] = 0; + TL[1] = 0; + TL[2] = 0; + TL[3] = 0; + TL[4] = scsiCmnd->cdb[10]; /* MSB */ + TL[5] = scsiCmnd->cdb[11]; + TL[6] = scsiCmnd->cdb[12]; + TL[7] = scsiCmnd->cdb[13]; /* LSB */ + + + + + lba = smsatComputeCDB16LBA(satIOContext); + tl = smsatComputeCDB16TL(satIOContext); + + + /* Table 34, 9.1, p 46 */ + /* + note: As of 2/10/2006, no support for DMA QUEUED + */ + + /* + Table 34, 9.1, p 46, b + When no 48-bit addressing support or NCQ, if LBA is beyond (2^28 - 1), + return check condition + */ + if (pSatDevData->satNCQ != agTRUE && + pSatDevData->sat48BitSupport != agTRUE + ) + { + AllChk = smsatCheckLimit(LBA, TL, agFALSE, pSatDevData); + if (AllChk) + { + SM_DBG1(("smsatRead16: return LBA out of range, not EXT!!!\n")); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + return SM_RC_SUCCESS; + } + } + else + { +// rangeChk = smsatAddNComparebit64(LBA, TL); + + AllChk = smsatCheckLimit(LBA, TL, agTRUE, pSatDevData); + + + if (AllChk) + { + SM_DBG1(("smsatRead16: return LBA out of range, EXT!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + return SM_RC_SUCCESS; + } + } + + /* case 1 and 2 */ + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 2 */ + /* READ DMA*/ + /* in case that we can't fit the transfer length, + we need to make it fit by sending multiple ATA cmnds */ + SM_DBG5(("smsatRead16: case 2\n")); + + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_DMA; /* 0xC8 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[9]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[8]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[7]; /* FIS LBA (23:16) */ + fis->d.device = + (bit8)((0x4 << 4) | (scsiCmnd->cdb[6] & 0xF)); /* FIS LBA (27:24) and FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[13]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + + agRequestType = AGSA_SATA_PROTOCOL_DMA_READ; + satIOContext->ATACmd = SAT_READ_DMA; + } + else + { + /* case 1 */ + /* READ MULTIPLE or READ SECTOR(S) */ + /* READ SECTORS for easier implemetation */ + /* can't fit the transfer length but need to make it fit by sending multiple*/ + SM_DBG5(("smsatRead16: case 1\n")); + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_SECTORS; /* 0x20 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[9]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[8]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[7]; /* FIS LBA (23:16) */ + fis->d.device = + (bit8)((0x4 << 4) | (scsiCmnd->cdb[6] & 0xF)); /* FIS LBA (27:24) and FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[13]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + satIOContext->ATACmd = SAT_READ_SECTORS; + } + + /* case 3 and 4 */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 3 */ + /* READ DMA EXT */ + SM_DBG5(("smsatRead16: case 3\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_DMA_EXT; /* 0x25 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[9]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[8]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[7]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[6]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = scsiCmnd->cdb[5]; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = scsiCmnd->cdb[4]; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[13]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[12]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_READ; + satIOContext->ATACmd = SAT_READ_DMA_EXT; + + } + else + { + /* case 4 */ + /* READ MULTIPLE EXT or READ SECTOR(S) EXT or READ VERIFY SECTOR(S) EXT*/ + /* READ SECTORS EXT for easier implemetation */ + SM_DBG5(("smsatRead16: case 4\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + /* Check FUA bit */ + if (scsiCmnd->cdb[1] & SCSI_READ16_FUA_MASK) + { + /* for now, no support for FUA */ + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + + fis->h.command = SAT_READ_SECTORS_EXT; /* 0x24 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[9]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[8]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[7]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[6]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = scsiCmnd->cdb[5]; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = scsiCmnd->cdb[4]; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[13]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[12]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + satIOContext->ATACmd = SAT_READ_SECTORS_EXT; + } + } + + + /* case 5 */ + if (pSatDevData->satNCQ == agTRUE) + { + /* READ FPDMA QUEUED */ + if (pSatDevData->sat48BitSupport != agTRUE) + { + SM_DBG1(("smsatRead16: case 5 !!! error NCQ but 28 bit address support!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + + SM_DBG6(("smsatRead16: case 5\n")); + + /* Support 48-bit FPDMA addressing, use READ FPDMA QUEUE command */ + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_FPDMA_QUEUED; /* 0x60 */ + fis->h.features = scsiCmnd->cdb[13]; /* FIS sector count (7:0) */ + fis->d.lbaLow = scsiCmnd->cdb[9]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[8]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[7]; /* FIS LBA (23:16) */ + + /* Check FUA bit */ + if (scsiCmnd->cdb[1] & SCSI_READ16_FUA_MASK) + fis->d.device = 0xC0; /* FIS FUA set */ + else + fis->d.device = 0x40; /* FIS FUA clear */ + + fis->d.lbaLowExp = scsiCmnd->cdb[6]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = scsiCmnd->cdb[5]; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = scsiCmnd->cdb[4]; /* FIS LBA (47:40) */ + fis->d.featuresExp = scsiCmnd->cdb[12]; /* FIS sector count (15:8) */ + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_READ; + satIOContext->ATACmd = SAT_READ_FPDMA_QUEUED; + } + + /* saves the current LBA and orginal TL */ + satIOContext->currentLBA = lba; + satIOContext->OrgTL = tl; + + /* + computing number of loop and remainder for tl + 0xFF in case not ext + 0xFFFF in case EXT + */ + if (fis->h.command == SAT_READ_SECTORS || fis->h.command == SAT_READ_DMA) + { + LoopNum = smsatComputeLoopNum(tl, 0xFF); + } + else if (fis->h.command == SAT_READ_SECTORS_EXT || fis->h.command == SAT_READ_DMA_EXT) + { + /* SAT_READ_SECTORS_EXT, SAT_READ_DMA_EXT */ + LoopNum = smsatComputeLoopNum(tl, 0xFFFF); + } + else + { + /* SAT_READ_FPDMA_QUEUEDK */ + LoopNum = smsatComputeLoopNum(tl, 0xFFFF); + } + satIOContext->LoopNum = LoopNum; + + if (LoopNum == 1) + { + SM_DBG5(("smsatRead16: NON CHAINED data\n")); + satIOContext->satCompleteCB = &smsatNonChainedDataIOCB; + } + else + { + SM_DBG1(("smsatRead16: CHAINED data!!!\n")); + /* re-setting tl */ + if (fis->h.command == SAT_READ_SECTORS || fis->h.command == SAT_READ_DMA) + { + fis->d.sectorCount = 0xFF; + } + else if (fis->h.command == SAT_READ_SECTORS_EXT || fis->h.command == SAT_READ_DMA_EXT) + { + /* SAT_READ_SECTORS_EXT, SAT_READ_DMA_EXT */ + fis->d.sectorCount = 0xFF; + fis->d.sectorCountExp = 0xFF; + } + else + { + /* SAT_READ_FPDMA_QUEUED */ + fis->h.features = 0xFF; + fis->d.featuresExp = 0xFF; + } + + /* chained data */ + satIOContext->satCompleteCB = &smsatChainedDataIOCB; + } + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + SM_DBG5(("smsatRead16: return\n")); + return (status); + +} + +osGLOBAL bit32 +smsatWrite6( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + smDeviceData_t *pSatDevData; + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 lba = 0; + bit16 tl = 0; + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &smScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + SM_DBG5(("smsatWrite6: start\n")); + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[5] & SCSI_NACA_MASK) || (scsiCmnd->cdb[5] & SCSI_LINK_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatWrite6: return control!!!\n")); + return SM_RC_SUCCESS; + } + + + /* cbd6; computing LBA and transfer length */ + lba = (((scsiCmnd->cdb[1]) & 0x1f) << (8*2)) + + (scsiCmnd->cdb[2] << 8) + scsiCmnd->cdb[3]; + tl = scsiCmnd->cdb[4]; + + + /* Table 34, 9.1, p 46 */ + /* + note: As of 2/10/2006, no support for DMA QUEUED + */ + + /* + Table 34, 9.1, p 46, b + When no 48-bit addressing support or NCQ, if LBA is beyond (2^28 - 1), + return check condition + */ + if (pSatDevData->satNCQ != agTRUE && + pSatDevData->sat48BitSupport != agTRUE + ) + { + if (lba > SAT_TR_LBA_LIMIT - 1) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatWrite6: return LBA out of range!!!\n")); + return SM_RC_SUCCESS; + } + } + + /* case 1 and 2 */ + if (lba + tl <= SAT_TR_LBA_LIMIT) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 2 */ + /* WRITE DMA*/ + SM_DBG5(("smsatWrite6: case 2\n")); + + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_DMA; /* 0xCA */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = (bit8)((scsiCmnd->cdb[1]) & 0x1f); /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + if (tl == 0) + { + /* temporary fix */ + fis->d.sectorCount = 0xff; /* FIS sector count (7:0) */ + } + else + { + fis->d.sectorCount = scsiCmnd->cdb[4]; /* FIS sector count (7:0) */ + } + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + } + else + { + /* case 1 */ + /* WRITE SECTORS for easier implemetation */ + SM_DBG5(("smsatWrite6: case 1\n")); + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_SECTORS; /* 0xCA */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = (bit8)((scsiCmnd->cdb[1]) & 0x1f); /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + if (tl == 0) + { + /* temporary fix */ + fis->d.sectorCount = 0xff; /* FIS sector count (7:0) */ + } + else + { + fis->d.sectorCount = scsiCmnd->cdb[4]; /* FIS sector count (7:0) */ + } + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + + } + } + + /* case 3 and 4 */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 3 */ + /* WRITE DMA EXT only */ + SM_DBG5(("smsatWrite6: case 3\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_DMA_EXT; /* 0x35 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = (bit8)((scsiCmnd->cdb[1]) & 0x1f); /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = 0; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + if (tl == 0) + { + /* sector count is 256, 0x100*/ + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0x01; /* FIS sector count (15:8) */ + } + else + { + fis->d.sectorCount = scsiCmnd->cdb[4]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + } + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + } + else + { + /* case 4 */ + /* WRITE SECTORS EXT for easier implemetation */ + SM_DBG5(("smsatWrite6: case 4\n")); + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_SECTORS_EXT; /* 0x34 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = (bit8)((scsiCmnd->cdb[1]) & 0x1f); /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = 0; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + if (tl == 0) + { + /* sector count is 256, 0x100*/ + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0x01; /* FIS sector count (15:8) */ + } + else + { + fis->d.sectorCount = scsiCmnd->cdb[4]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + } + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + } + } + + /* case 5 */ + if (pSatDevData->satNCQ == agTRUE) + { + /* WRITE FPDMA QUEUED */ + if (pSatDevData->sat48BitSupport != agTRUE) + { + /* sanity check */ + SM_DBG5(("smsatWrite6: case 5 !!! error NCQ but 28 bit address support!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + SM_DBG5(("smsatWrite6: case 5\n")); + + /* Support 48-bit FPDMA addressing, use WRITE FPDMA QUEUE command */ + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_FPDMA_QUEUED; /* 0x61 */ + fis->d.lbaLow = scsiCmnd->cdb[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = (bit8)((scsiCmnd->cdb[1]) & 0x1f); /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS FUA clear */ + fis->d.lbaLowExp = 0; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + if (tl == 0) + { + /* sector count is 256, 0x100*/ + fis->h.features = 0; /* FIS sector count (7:0) */ + fis->d.featuresExp = 0x01; /* FIS sector count (15:8) */ + } + else + { + fis->h.features = scsiCmnd->cdb[4]; /* FIS sector count (7:0) */ + fis->d.featuresExp = 0; /* FIS sector count (15:8) */ + } + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_WRITE; + } + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatNonChainedDataIOCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + return (status); +} + +osGLOBAL FORCEINLINE bit32 +smsatWrite10( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + smDeviceData_t *pSatDevData = satIOContext->pSatDevData; + smScsiRspSense_t *pSense = satIOContext->pSense; + smIniScsiCmnd_t *scsiCmnd = &smScsiRequest->scsiCmnd; + agsaFisRegHostToDevice_t *fis = satIOContext->pFis; + bit32 status = SM_RC_FAILURE; + bit32 agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + bit32 lba = 0; + bit32 tl = 0; + bit32 LoopNum = 1; + bit32 AllChk = agFALSE; /* lba, lba+tl check against ATA limit and Disk capacity */ + bit8 LBA[8]; + bit8 TL[8]; + + SM_DBG2(("smsatWrite10: start\n")); + + /* checking FUA_NV */ + if (scsiCmnd->cdb[1] & SCSI_FUA_NV_MASK) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatWrite10: return FUA_NV!!!\n")); + return SM_RC_SUCCESS; + + } + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[9] & SCSI_NACA_MASK) || (scsiCmnd->cdb[9] & SCSI_LINK_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatWrite10: return control!!!\n")); + return SM_RC_SUCCESS; + } +/* + sm_memset(LBA, 0, sizeof(LBA)); + sm_memset(TL, 0, sizeof(TL)); +*/ + /* do not use memcpy due to indexing in LBA and TL */ + LBA[0] = 0; /* MSB */ + LBA[1] = 0; + LBA[2] = 0; + LBA[3] = 0; + LBA[4] = scsiCmnd->cdb[2]; + LBA[5] = scsiCmnd->cdb[3]; + LBA[6] = scsiCmnd->cdb[4]; + LBA[7] = scsiCmnd->cdb[5]; /* LSB */ + + TL[0] = 0; + TL[1] = 0; + TL[2] = 0; + TL[3] = 0; + TL[4] = 0; + TL[5] = 0; + TL[6] = scsiCmnd->cdb[7]; + TL[7] = scsiCmnd->cdb[8]; /* LSB */ + + + + /* cbd10; computing LBA and transfer length */ + lba = (scsiCmnd->cdb[2] << (24)) + (scsiCmnd->cdb[3] << (16)) + + (scsiCmnd->cdb[4] << 8) + scsiCmnd->cdb[5]; + tl = (scsiCmnd->cdb[7] << 8) + scsiCmnd->cdb[8]; + + SM_DBG5(("smsatWrite10: lba %d functioned lba %d\n", lba, smsatComputeCDB10LBA(satIOContext))); + SM_DBG5(("smsatWrite10: tl %d functioned tl %d\n", tl, smsatComputeCDB10TL(satIOContext))); + + /* Table 34, 9.1, p 46 */ + /* + note: As of 2/10/2006, no support for DMA QUEUED + */ + + /* + Table 34, 9.1, p 46, b + When no 48-bit addressing support or NCQ, if LBA is beyond (2^28 - 1), + return check condition + */ + if (pSatDevData->satNCQ != agTRUE && + pSatDevData->sat48BitSupport != agTRUE + ) + { + AllChk = smsatCheckLimit(LBA, TL, agFALSE, pSatDevData); + if (AllChk) + { + SM_DBG1(("smsatWrite10: return LBA out of range, not EXT!!!\n")); + SM_DBG1(("smsatWrite10: cdb 0x%x 0x%x 0x%x 0x%x!!!\n",scsiCmnd->cdb[2], scsiCmnd->cdb[3], + scsiCmnd->cdb[4], scsiCmnd->cdb[5])); + SM_DBG1(("smsatWrite10: lba 0x%x SAT_TR_LBA_LIMIT 0x%x!!!\n", lba, SAT_TR_LBA_LIMIT)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + return SM_RC_SUCCESS; + } + } + else + { + AllChk = smsatCheckLimit(LBA, TL, agTRUE, pSatDevData); + if (AllChk) + { + SM_DBG1(("smsatWrite10: return LBA out of range, EXT!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + return SM_RC_SUCCESS; + } + + } + + /* case 5 */ + if (pSatDevData->satNCQ == agTRUE) + { + /* WRITE FPDMA QUEUED */ + if (pSatDevData->sat48BitSupport != agTRUE) + { + SM_DBG1(("smsatWrite10: case 5 !!! error NCQ but 28 bit address support!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + SM_DBG6(("smsatWrite10: case 5\n")); + + /* Support 48-bit FPDMA addressing, use WRITE FPDMA QUEUE command */ + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_FPDMA_QUEUED; /* 0x61 */ + fis->h.features = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + + /* Check FUA bit */ + if (scsiCmnd->cdb[1] & SCSI_WRITE10_FUA_MASK) + fis->d.device = 0xC0; /* FIS FUA set */ + else + fis->d.device = 0x40; /* FIS FUA clear */ + + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = scsiCmnd->cdb[7]; /* FIS sector count (15:8) */ + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_FPDMA_QUEUED; + } + /* case 3 and 4 */ + else if (pSatDevData->sat48BitSupport == agTRUE) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 3 */ + /* WRITE DMA EXT or WRITE DMA FUA EXT */ + SM_DBG5(("smsatWrite10: case 3\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + /* SAT_WRITE_DMA_FUA_EXT is optional and we don't support it */ + fis->h.command = SAT_WRITE_DMA_EXT; /* 0x35 */ + satIOContext->ATACmd = SAT_WRITE_DMA_EXT; + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[7]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + } + else + { + /* case 4 */ + /* WRITE MULTIPLE EXT or WRITE MULTIPLE FUA EXT or WRITE SECTOR(S) EXT */ + /* WRITE SECTORS EXT for easier implemetation */ + SM_DBG5(("smsatWrite10: case 4\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_SECTORS_EXT; /* 0x34 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[7]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + satIOContext->ATACmd = SAT_WRITE_SECTORS_EXT; + } + } + else /* case 1 and 2 */ + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 2 */ + /* WRITE DMA*/ + /* can't fit the transfer length */ + SM_DBG5(("smsatWrite10: case 2\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_DMA; /* 0xCA */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (scsiCmnd->cdb[2] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_DMA; + } + else + { + /* case 1 */ + /* WRITE MULTIPLE or WRITE SECTOR(S) */ + /* WRITE SECTORS for easier implemetation */ + /* can't fit the transfer length */ + SM_DBG5(("smsatWrite10: case 1\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_SECTORS; /* 0x30 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (scsiCmnd->cdb[2] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + satIOContext->ATACmd = SAT_WRITE_SECTORS; + } + } + + // smhexdump("satWrite10 final fis", (bit8 *)fis, sizeof(agsaFisRegHostToDevice_t)); + + satIOContext->currentLBA = lba; + satIOContext->OrgTL = tl; + + /* + computing number of loop and remainder for tl + 0xFF in case not ext + 0xFFFF in case EXT + */ + if (fis->h.command == SAT_WRITE_SECTORS || fis->h.command == SAT_WRITE_DMA) + { + LoopNum = smsatComputeLoopNum(tl, 0x100); + } + else + { + /* SAT_WRITE_FPDMA_QUEUEDK */ + /* SAT_READ_SECTORS_EXT, SAT_READ_DMA_EXT */ + LoopNum = smsatComputeLoopNum(tl, 0xFFFF); + } + + satIOContext->LoopNum = LoopNum; + + + if (LoopNum == 1) + { + SM_DBG5(("smsatWrite10: NON CHAINED data\n")); + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatNonChainedDataIOCB; + } + else + { + SM_DBG2(("smsatWrite10: CHAINED data!!!\n")); + /* re-setting tl */ + if (fis->h.command == SAT_WRITE_SECTORS || fis->h.command == SAT_WRITE_DMA) + { + fis->d.sectorCount = 0x0; + smsatSplitSGL(smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext, + NON_BIT48_ADDRESS_TL_LIMIT*SATA_SECTOR_SIZE, /* 0x100 * 0x200 */ + (satIOContext->OrgTL)*SATA_SECTOR_SIZE, + agTRUE); + } + else if (fis->h.command == SAT_WRITE_SECTORS_EXT || + fis->h.command == SAT_WRITE_DMA_EXT || + fis->h.command == SAT_WRITE_DMA_FUA_EXT + ) + { + fis->d.sectorCount = 0xFF; + fis->d.sectorCountExp = 0xFF; + smsatSplitSGL(smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext, + BIT48_ADDRESS_TL_LIMIT*SATA_SECTOR_SIZE, /* 0xFFFF * 0x200 */ + (satIOContext->OrgTL)*SATA_SECTOR_SIZE, + agTRUE); + } + else + { + /* SAT_WRITE_FPDMA_QUEUED */ + fis->h.features = 0xFF; + fis->d.featuresExp = 0xFF; + smsatSplitSGL(smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext, + BIT48_ADDRESS_TL_LIMIT*SATA_SECTOR_SIZE, /* 0xFFFF * 0x200 */ + (satIOContext->OrgTL)*SATA_SECTOR_SIZE, + agTRUE); + } + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatChainedDataIOCB; + } + + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + return (status); +} + +osGLOBAL bit32 +smsatWrite12( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + smDeviceData_t *pSatDevData; + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 lba = 0; + bit32 tl = 0; + bit32 LoopNum = 1; + bit8 LBA[8]; + bit8 TL[8]; + bit32 AllChk = agFALSE; /* lba, lba+tl check against ATA limit and Disk capacity */ + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &smScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + SM_DBG5(("smsatWrite12: start\n")); + + /* checking FUA_NV */ + if (scsiCmnd->cdb[1] & SCSI_FUA_NV_MASK) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatWrite12: return FUA_NV!!!\n")); + return SM_RC_SUCCESS; + + } + + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[11] & SCSI_NACA_MASK) || (scsiCmnd->cdb[11] & SCSI_LINK_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatWrite10: return control!!!\n")); + return SM_RC_SUCCESS; + } + + + sm_memset(LBA, 0, sizeof(LBA)); + sm_memset(TL, 0, sizeof(TL)); + + /* do not use memcpy due to indexing in LBA and TL */ + LBA[0] = 0; /* MSB */ + LBA[1] = 0; + LBA[2] = 0; + LBA[3] = 0; + LBA[4] = scsiCmnd->cdb[2]; + LBA[5] = scsiCmnd->cdb[3]; + LBA[6] = scsiCmnd->cdb[4]; + LBA[7] = scsiCmnd->cdb[5]; /* LSB */ + + TL[0] = 0; /* MSB */ + TL[1] = 0; + TL[2] = 0; + TL[3] = 0; + TL[4] = scsiCmnd->cdb[6]; + TL[5] = scsiCmnd->cdb[7]; + TL[6] = scsiCmnd->cdb[8]; + TL[7] = scsiCmnd->cdb[9]; /* LSB */ + + + lba = smsatComputeCDB12LBA(satIOContext); + tl = smsatComputeCDB12TL(satIOContext); + + + /* Table 34, 9.1, p 46 */ + /* + note: As of 2/10/2006, no support for DMA QUEUED + */ + + /* + Table 34, 9.1, p 46, b + When no 48-bit addressing support or NCQ, if LBA is beyond (2^28 - 1), + return check condition + */ + if (pSatDevData->satNCQ != agTRUE && + pSatDevData->sat48BitSupport != agTRUE + ) + { + AllChk = smsatCheckLimit(LBA, TL, agFALSE, pSatDevData); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + + + if (AllChk) + { + SM_DBG1(("smsatWrite12: return LBA out of range, not EXT!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + return SM_RC_SUCCESS; + } + } + else + { + AllChk = smsatCheckLimit(LBA, TL, agTRUE, pSatDevData); + if (AllChk) + { + SM_DBG1(("smsatWrite12: return LBA out of range, EXT!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + } + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 2 */ + /* WRITE DMA*/ + /* In case that we can't fit the transfer length, we loop */ + SM_DBG5(("smsatWrite10: case 2\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_DMA; /* 0xCA */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (scsiCmnd->cdb[2] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[9]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_DMA; + } + else + { + /* case 1 */ + /* WRITE MULTIPLE or WRITE SECTOR(S) */ + /* WRITE SECTORS for easier implemetation */ + /* In case that we can't fit the transfer length, we loop */ + SM_DBG5(("smsatWrite10: case 1\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_SECTORS; /* 0x30 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (scsiCmnd->cdb[2] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[9]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + satIOContext->ATACmd = SAT_WRITE_SECTORS; + } + + /* case 3 and 4 */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 3 */ + /* WRITE DMA EXT or WRITE DMA FUA EXT */ + SM_DBG5(("smsatWrite10: case 3\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + /* SAT_WRITE_DMA_FUA_EXT is optional and we don't support it */ + fis->h.command = SAT_WRITE_DMA_EXT; /* 0x35 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[9]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[8]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_DMA_EXT; + } + else + { + /* case 4 */ + /* WRITE MULTIPLE EXT or WRITE MULTIPLE FUA EXT or WRITE SECTOR(S) EXT */ + /* WRITE SECTORS EXT for easier implemetation */ + SM_DBG5(("smsatWrite10: case 4\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_SECTORS_EXT; /* 0x34 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[9]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[8]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + satIOContext->ATACmd = SAT_WRITE_SECTORS_EXT; + } + } + + /* case 5 */ + if (pSatDevData->satNCQ == agTRUE) + { + /* WRITE FPDMA QUEUED */ + if (pSatDevData->sat48BitSupport != agTRUE) + { + SM_DBG5(("smsatWrite10: case 5 !!! error NCQ but 28 bit address support!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + SM_DBG6(("smsatWrite10: case 5\n")); + + /* Support 48-bit FPDMA addressing, use WRITE FPDMA QUEUE command */ + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_FPDMA_QUEUED; /* 0x61 */ + fis->h.features = scsiCmnd->cdb[9]; /* FIS sector count (7:0) */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + + /* Check FUA bit */ + if (scsiCmnd->cdb[1] & SCSI_WRITE12_FUA_MASK) + fis->d.device = 0xC0; /* FIS FUA set */ + else + fis->d.device = 0x40; /* FIS FUA clear */ + + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = scsiCmnd->cdb[8]; /* FIS sector count (15:8) */ + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_FPDMA_QUEUED; + } + + satIOContext->currentLBA = lba; + satIOContext->OrgTL = tl; + + /* + computing number of loop and remainder for tl + 0xFF in case not ext + 0xFFFF in case EXT + */ + if (fis->h.command == SAT_WRITE_SECTORS || fis->h.command == SAT_WRITE_DMA) + { + LoopNum = smsatComputeLoopNum(tl, 0xFF); + } + else if (fis->h.command == SAT_WRITE_SECTORS_EXT || + fis->h.command == SAT_WRITE_DMA_EXT || + fis->h.command == SAT_WRITE_DMA_FUA_EXT + ) + { + /* SAT_READ_SECTORS_EXT, SAT_READ_DMA_EXT */ + LoopNum = smsatComputeLoopNum(tl, 0xFFFF); + } + else + { + /* SAT_WRITE_FPDMA_QUEUEDK */ + LoopNum = smsatComputeLoopNum(tl, 0xFFFF); + } + + satIOContext->LoopNum = LoopNum; + + + if (LoopNum == 1) + { + SM_DBG5(("smsatWrite10: NON CHAINED data\n")); + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatNonChainedDataIOCB; + } + else + { + SM_DBG1(("smsatWrite10: CHAINED data\n")); + /* re-setting tl */ + if (fis->h.command == SAT_WRITE_SECTORS || fis->h.command == SAT_WRITE_DMA) + { + fis->d.sectorCount = 0xFF; + } + else if (fis->h.command == SAT_WRITE_SECTORS_EXT || + fis->h.command == SAT_WRITE_DMA_EXT || + fis->h.command == SAT_WRITE_DMA_FUA_EXT + ) + { + fis->d.sectorCount = 0xFF; + fis->d.sectorCountExp = 0xFF; + } + else + { + /* SAT_WRITE_FPDMA_QUEUED */ + fis->h.features = 0xFF; + fis->d.featuresExp = 0xFF; + } + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatChainedDataIOCB; + } + + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + return (status); +} + +osGLOBAL bit32 +smsatWrite16( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + smDeviceData_t *pSatDevData; + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 lba = 0; + bit32 tl = 0; + bit32 LoopNum = 1; + bit8 LBA[8]; + bit8 TL[8]; + bit32 AllChk = agFALSE; /* lba, lba+tl check against ATA limit and Disk capacity */ + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &smScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + SM_DBG5(("smsatWrite16: start\n")); + + /* checking FUA_NV */ + if (scsiCmnd->cdb[1] & SCSI_FUA_NV_MASK) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatWrite16: return FUA_NV!!!\n")); + return SM_RC_SUCCESS; + + } + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[15] & SCSI_NACA_MASK) || (scsiCmnd->cdb[15] & SCSI_LINK_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatWrite16: return control!!!\n")); + return SM_RC_SUCCESS; + } + + + sm_memset(LBA, 0, sizeof(LBA)); + sm_memset(TL, 0, sizeof(TL)); + + + /* do not use memcpy due to indexing in LBA and TL */ + LBA[0] = scsiCmnd->cdb[2]; /* MSB */ + LBA[1] = scsiCmnd->cdb[3]; + LBA[2] = scsiCmnd->cdb[4]; + LBA[3] = scsiCmnd->cdb[5]; + LBA[4] = scsiCmnd->cdb[6]; + LBA[5] = scsiCmnd->cdb[7]; + LBA[6] = scsiCmnd->cdb[8]; + LBA[7] = scsiCmnd->cdb[9]; /* LSB */ + + TL[0] = 0; + TL[1] = 0; + TL[2] = 0; + TL[3] = 0; + TL[4] = scsiCmnd->cdb[10]; /* MSB */ + TL[5] = scsiCmnd->cdb[11]; + TL[6] = scsiCmnd->cdb[12]; + TL[7] = scsiCmnd->cdb[13]; /* LSB */ + + + + lba = smsatComputeCDB16LBA(satIOContext); + tl = smsatComputeCDB16TL(satIOContext); + + + + /* Table 34, 9.1, p 46 */ + /* + note: As of 2/10/2006, no support for DMA QUEUED + */ + + /* + Table 34, 9.1, p 46, b + When no 48-bit addressing support or NCQ, if LBA is beyond (2^28 - 1), + return check condition + */ + if (pSatDevData->satNCQ != agTRUE && + pSatDevData->sat48BitSupport != agTRUE + ) + { + AllChk = smsatCheckLimit(LBA, TL, agFALSE, pSatDevData); + if (AllChk) + { + SM_DBG1(("smsatWrite16: return LBA out of range, not EXT!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + return SM_RC_SUCCESS; + } + } + else + { + AllChk = smsatCheckLimit(LBA, TL, agTRUE, pSatDevData); + if (AllChk) + { + SM_DBG1(("smsatWrite16: return LBA out of range, EXT!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + return SM_RC_SUCCESS; + } + } + + /* case 1 and 2 */ + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 2 */ + /* WRITE DMA*/ + /* In case that we can't fit the transfer length, we loop */ + SM_DBG5(("smsatWrite16: case 2\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_DMA; /* 0xCA */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[9]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[8]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[7]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (scsiCmnd->cdb[6] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[13]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_DMA; + } + else + { + /* case 1 */ + /* WRITE MULTIPLE or WRITE SECTOR(S) */ + /* WRITE SECTORS for easier implemetation */ + /* In case that we can't fit the transfer length, we loop */ + SM_DBG5(("smsatWrite16: case 1\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_SECTORS; /* 0x30 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[9]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[8]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[7]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (scsiCmnd->cdb[6] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[13]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + satIOContext->ATACmd = SAT_WRITE_SECTORS; + } + + /* case 3 and 4 */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 3 */ + /* WRITE DMA EXT or WRITE DMA FUA EXT */ + SM_DBG5(("smsatWrite16: case 3\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + /* SAT_WRITE_DMA_FUA_EXT is optional and we don't support it */ + fis->h.command = SAT_WRITE_DMA_EXT; /* 0x35 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[9]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[8]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[7]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[6]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = scsiCmnd->cdb[5]; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = scsiCmnd->cdb[4]; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[13]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[12]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_DMA_EXT; + } + else + { + /* case 4 */ + /* WRITE MULTIPLE EXT or WRITE MULTIPLE FUA EXT or WRITE SECTOR(S) EXT */ + /* WRITE SECTORS EXT for easier implemetation */ + SM_DBG5(("smsatWrite16: case 4\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_SECTORS_EXT; /* 0x34 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[9]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[8]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[7]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[6]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = scsiCmnd->cdb[5]; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = scsiCmnd->cdb[4]; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[13]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[12]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + satIOContext->ATACmd = SAT_WRITE_SECTORS_EXT; + } + } + + /* case 5 */ + if (pSatDevData->satNCQ == agTRUE) + { + /* WRITE FPDMA QUEUED */ + if (pSatDevData->sat48BitSupport != agTRUE) + { + SM_DBG5(("smsatWrite16: case 5 !!! error NCQ but 28 bit address support!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + SM_DBG6(("smsatWrite16: case 5\n")); + + /* Support 48-bit FPDMA addressing, use WRITE FPDMA QUEUE command */ + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_FPDMA_QUEUED; /* 0x61 */ + fis->h.features = scsiCmnd->cdb[13]; /* FIS sector count (7:0) */ + fis->d.lbaLow = scsiCmnd->cdb[9]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[8]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[7]; /* FIS LBA (23:16) */ + + /* Check FUA bit */ + if (scsiCmnd->cdb[1] & SCSI_WRITE16_FUA_MASK) + fis->d.device = 0xC0; /* FIS FUA set */ + else + fis->d.device = 0x40; /* FIS FUA clear */ + + fis->d.lbaLowExp = scsiCmnd->cdb[6]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = scsiCmnd->cdb[5]; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = scsiCmnd->cdb[4]; /* FIS LBA (47:40) */ + fis->d.featuresExp = scsiCmnd->cdb[12]; /* FIS sector count (15:8) */ + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_FPDMA_QUEUED; + } + + satIOContext->currentLBA = lba; + satIOContext->OrgTL = tl; + + /* + computing number of loop and remainder for tl + 0xFF in case not ext + 0xFFFF in case EXT + */ + if (fis->h.command == SAT_WRITE_SECTORS || fis->h.command == SAT_WRITE_DMA) + { + LoopNum = smsatComputeLoopNum(tl, 0xFF); + } + else if (fis->h.command == SAT_WRITE_SECTORS_EXT || + fis->h.command == SAT_WRITE_DMA_EXT || + fis->h.command == SAT_WRITE_DMA_FUA_EXT + ) + { + /* SAT_READ_SECTORS_EXT, SAT_READ_DMA_EXT */ + LoopNum = smsatComputeLoopNum(tl, 0xFFFF); + } + else + { + /* SAT_WRITE_FPDMA_QUEUEDK */ + LoopNum = smsatComputeLoopNum(tl, 0xFFFF); + } + + satIOContext->LoopNum = LoopNum; + + + if (LoopNum == 1) + { + SM_DBG5(("smsatWrite16: NON CHAINED data\n")); + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatNonChainedDataIOCB; + } + else + { + SM_DBG1(("smsatWrite16: CHAINED data!!!\n")); + /* re-setting tl */ + if (fis->h.command == SAT_WRITE_SECTORS || fis->h.command == SAT_WRITE_DMA) + { + fis->d.sectorCount = 0xFF; + } + else if (fis->h.command == SAT_WRITE_SECTORS_EXT || + fis->h.command == SAT_WRITE_DMA_EXT || + fis->h.command == SAT_WRITE_DMA_FUA_EXT + ) + { + fis->d.sectorCount = 0xFF; + fis->d.sectorCountExp = 0xFF; + } + else + { + /* SAT_WRITE_FPDMA_QUEUED */ + fis->h.features = 0xFF; + fis->d.featuresExp = 0xFF; + } + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatChainedDataIOCB; + } + + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + return (status); +} + + +osGLOBAL bit32 +smsatVerify10( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + /* + For simple implementation, + no byte comparison supported as of 4/5/06 + */ + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + smDeviceData_t *pSatDevData; + agsaFisRegHostToDevice_t *fis; + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + bit32 lba = 0; + bit32 tl = 0; + bit32 LoopNum = 1; + bit8 LBA[8]; + bit8 TL[8]; + bit32 AllChk = agFALSE; /* lba, lba+tl check against ATA limit and Disk capacity */ + + pSense = satIOContext->pSense; + scsiCmnd = &smScsiRequest->scsiCmnd; + pSatDevData = satIOContext->pSatDevData; + fis = satIOContext->pFis; + SM_DBG5(("smsatVerify10: start\n")); + /* checking BYTCHK */ + if (scsiCmnd->cdb[1] & SCSI_VERIFY_BYTCHK_MASK) + { + /* + should do the byte check + but not supported in this version + */ + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + /*smEnqueueIO(smRoot, satIOContext);*/ + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatVerify10: no byte checking!!!\n")); + return SM_RC_SUCCESS; + } + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[9] & SCSI_NACA_MASK) || (scsiCmnd->cdb[9] & SCSI_LINK_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatVerify10: return control!!!\n")); + return SM_RC_SUCCESS; + } + + + sm_memset(LBA, 0, sizeof(LBA)); + sm_memset(TL, 0, sizeof(TL)); + + /* do not use memcpy due to indexing in LBA and TL */ + LBA[0] = 0; /* MSB */ + LBA[1] = 0; + LBA[2] = 0; + LBA[3] = 0; + LBA[4] = scsiCmnd->cdb[2]; + LBA[5] = scsiCmnd->cdb[3]; + LBA[6] = scsiCmnd->cdb[4]; + LBA[7] = scsiCmnd->cdb[5]; /* LSB */ + + TL[0] = 0; + TL[1] = 0; + TL[2] = 0; + TL[3] = 0; + TL[4] = 0; + TL[5] = 0; + TL[6] = scsiCmnd->cdb[7]; + TL[7] = scsiCmnd->cdb[8]; /* LSB */ + + + /* cbd10; computing LBA and transfer length */ + lba = (scsiCmnd->cdb[2] << (8*3)) + (scsiCmnd->cdb[3] << (8*2)) + + (scsiCmnd->cdb[4] << 8) + scsiCmnd->cdb[5]; + tl = (scsiCmnd->cdb[7] << 8) + scsiCmnd->cdb[8]; + + if (pSatDevData->satNCQ != agTRUE && + pSatDevData->sat48BitSupport != agTRUE + ) + { + AllChk = smsatCheckLimit(LBA, TL, agFALSE, pSatDevData); + if (AllChk) + { + SM_DBG1(("smsatVerify10: return LBA out of range, not EXT!!!\n")); + SM_DBG1(("smsatVerify10: cdb 0x%x 0x%x 0x%x 0x%x!!!\n",scsiCmnd->cdb[2], scsiCmnd->cdb[3], + scsiCmnd->cdb[4], scsiCmnd->cdb[5])); + SM_DBG1(("smsatVerify10: lba 0x%x SAT_TR_LBA_LIMIT 0x%x!!!\n", lba, SAT_TR_LBA_LIMIT)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + return SM_RC_SUCCESS; + } + } + else + { + AllChk = smsatCheckLimit(LBA, TL, agTRUE, pSatDevData); + if (AllChk) + { + SM_DBG1(("smsatVerify10: return LBA out of range, EXT!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + return SM_RC_SUCCESS; + } + } + + if (pSatDevData->sat48BitSupport == agTRUE) + { + SM_DBG5(("smsatVerify10: SAT_READ_VERIFY_SECTORS_EXT\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_READ_VERIFY_SECTORS_EXT;/* 0x42 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set 01000000 */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[7]; /* FIS sector count (15:8) */ + + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + satIOContext->ATACmd = SAT_READ_VERIFY_SECTORS_EXT; + } + else + { + SM_DBG5(("smsatVerify10: SAT_READ_VERIFY_SECTORS\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS; /* 0x40 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (scsiCmnd->cdb[2] & 0xF)); + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + satIOContext->ATACmd = SAT_READ_VERIFY_SECTORS; + + } + + satIOContext->currentLBA = lba; + satIOContext->OrgTL = tl; + + /* + computing number of loop and remainder for tl + 0xFF in case not ext + 0xFFFF in case EXT + */ + if (fis->h.command == SAT_READ_VERIFY_SECTORS) + { + LoopNum = smsatComputeLoopNum(tl, 0xFF); + } + else if (fis->h.command == SAT_READ_VERIFY_SECTORS_EXT) + { + /* SAT_READ_SECTORS_EXT, SAT_READ_DMA_EXT */ + LoopNum = smsatComputeLoopNum(tl, 0xFFFF); + } + else + { + SM_DBG1(("smsatVerify10: error case 1!!!\n")); + LoopNum = 1; + } + + satIOContext->LoopNum = LoopNum; + + if (LoopNum == 1) + { + SM_DBG5(("smsatVerify10: NON CHAINED data\n")); + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatNonChainedVerifyCB; + } + else + { + SM_DBG1(("smsatVerify10: CHAINED data!!!\n")); + /* re-setting tl */ + if (fis->h.command == SAT_READ_VERIFY_SECTORS) + { + fis->d.sectorCount = 0xFF; + } + else if (fis->h.command == SAT_READ_VERIFY_SECTORS_EXT) + { + fis->d.sectorCount = 0xFF; + fis->d.sectorCountExp = 0xFF; + } + else + { + SM_DBG1(("smsatVerify10: error case 2!!!\n")); + } + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatChainedVerifyCB; + } + + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + return (status); +} + +osGLOBAL bit32 +smsatVerify12( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + /* + For simple implementation, + no byte comparison supported as of 4/5/06 + */ + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + smDeviceData_t *pSatDevData; + agsaFisRegHostToDevice_t *fis; + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + bit32 lba = 0; + bit32 tl = 0; + bit32 LoopNum = 1; + bit8 LBA[8]; + bit8 TL[8]; + bit32 AllChk = agFALSE; /* lba, lba+tl check against ATA limit and Disk capacity */ + + pSense = satIOContext->pSense; + scsiCmnd = &smScsiRequest->scsiCmnd; + pSatDevData = satIOContext->pSatDevData; + fis = satIOContext->pFis; + SM_DBG5(("smsatVerify12: start\n")); + /* checking BYTCHK */ + if (scsiCmnd->cdb[1] & SCSI_VERIFY_BYTCHK_MASK) + { + /* + should do the byte check + but not supported in this version + */ + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatVerify12: no byte checking!!!\n")); + return SM_RC_SUCCESS; + } + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[11] & SCSI_NACA_MASK) || (scsiCmnd->cdb[11] & SCSI_LINK_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatVerify12: return control!!!\n")); + return SM_RC_SUCCESS; + } + + sm_memset(LBA, 0, sizeof(LBA)); + sm_memset(TL, 0, sizeof(TL)); + + /* do not use memcpy due to indexing in LBA and TL */ + LBA[0] = 0; /* MSB */ + LBA[1] = 0; + LBA[2] = 0; + LBA[3] = 0; + LBA[4] = scsiCmnd->cdb[2]; + LBA[5] = scsiCmnd->cdb[3]; + LBA[6] = scsiCmnd->cdb[4]; + LBA[7] = scsiCmnd->cdb[5]; /* LSB */ + + TL[0] = 0; /* MSB */ + TL[1] = 0; + TL[2] = 0; + TL[3] = 0; + TL[4] = scsiCmnd->cdb[6]; + TL[5] = scsiCmnd->cdb[7]; + TL[6] = scsiCmnd->cdb[8]; + TL[7] = scsiCmnd->cdb[9]; /* LSB */ + + + lba = smsatComputeCDB12LBA(satIOContext); + tl = smsatComputeCDB12TL(satIOContext); + + if (pSatDevData->satNCQ != agTRUE && + pSatDevData->sat48BitSupport != agTRUE + ) + { + AllChk = smsatCheckLimit(LBA, TL, agFALSE, pSatDevData); + if (AllChk) + { + SM_DBG1(("smsatVerify12: return LBA out of range, not EXT!!!\n")); + SM_DBG1(("smsatVerify12: cdb 0x%x 0x%x 0x%x 0x%x!!!\n",scsiCmnd->cdb[2], scsiCmnd->cdb[3], + scsiCmnd->cdb[4], scsiCmnd->cdb[5])); + SM_DBG1(("smsatVerify12: lba 0x%x SAT_TR_LBA_LIMIT 0x%x!!!\n", lba, SAT_TR_LBA_LIMIT)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + return SM_RC_SUCCESS; + } + } + else + { + AllChk = smsatCheckLimit(LBA, TL, agTRUE, pSatDevData); + if (AllChk) + { + SM_DBG1(("smsatVerify12: return LBA out of range, EXT!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + return SM_RC_SUCCESS; + } + } + + if (pSatDevData->sat48BitSupport == agTRUE) + { + SM_DBG5(("smsatVerify12: SAT_READ_VERIFY_SECTORS_EXT\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_READ_VERIFY_SECTORS_EXT;/* 0x42 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set 01000000 */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[9]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[8]; /* FIS sector count (15:8) */ + + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + satIOContext->ATACmd = SAT_READ_VERIFY_SECTORS_EXT; + } + else + { + SM_DBG5(("smsatVerify12: SAT_READ_VERIFY_SECTORS\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS; /* 0x40 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (scsiCmnd->cdb[2] & 0xF)); + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[9]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + satIOContext->ATACmd = SAT_READ_VERIFY_SECTORS; + + } + + satIOContext->currentLBA = lba; + satIOContext->OrgTL = tl; + + /* + computing number of loop and remainder for tl + 0xFF in case not ext + 0xFFFF in case EXT + */ + if (fis->h.command == SAT_READ_VERIFY_SECTORS) + { + LoopNum = smsatComputeLoopNum(tl, 0xFF); + } + else if (fis->h.command == SAT_READ_VERIFY_SECTORS_EXT) + { + /* SAT_READ_SECTORS_EXT, SAT_READ_DMA_EXT */ + LoopNum = smsatComputeLoopNum(tl, 0xFFFF); + } + else + { + SM_DBG1(("smsatVerify12: error case 1!!!\n")); + LoopNum = 1; + } + + satIOContext->LoopNum = LoopNum; + + if (LoopNum == 1) + { + SM_DBG5(("smsatVerify12: NON CHAINED data\n")); + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatNonChainedVerifyCB; + } + else + { + SM_DBG1(("smsatVerify12: CHAINED data!!!\n")); + /* re-setting tl */ + if (fis->h.command == SAT_READ_VERIFY_SECTORS) + { + fis->d.sectorCount = 0xFF; + } + else if (fis->h.command == SAT_READ_VERIFY_SECTORS_EXT) + { + fis->d.sectorCount = 0xFF; + fis->d.sectorCountExp = 0xFF; + } + else + { + SM_DBG1(("smsatVerify12: error case 2!!!\n")); + } + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatChainedVerifyCB; + } + + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + return (status); +} + +osGLOBAL bit32 +smsatVerify16( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + /* + For simple implementation, + no byte comparison supported as of 4/5/06 + */ + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + smDeviceData_t *pSatDevData; + agsaFisRegHostToDevice_t *fis; + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + bit32 lba = 0; + bit32 tl = 0; + bit32 LoopNum = 1; + bit8 LBA[8]; + bit8 TL[8]; + bit32 AllChk = agFALSE; /* lba, lba+tl check against ATA limit and Disk capacity */ + + pSense = satIOContext->pSense; + scsiCmnd = &smScsiRequest->scsiCmnd; + pSatDevData = satIOContext->pSatDevData; + fis = satIOContext->pFis; + SM_DBG5(("smsatVerify16: start\n")); + /* checking BYTCHK */ + if (scsiCmnd->cdb[1] & SCSI_VERIFY_BYTCHK_MASK) + { + /* + should do the byte check + but not supported in this version + */ + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + /*smEnqueueIO(smRoot, satIOContext);*/ + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + SM_DBG1(("smsatVerify16: no byte checking!!!\n")); + return SM_RC_SUCCESS; + } + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[15] & SCSI_NACA_MASK) || (scsiCmnd->cdb[15] & SCSI_LINK_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + /*smEnqueueIO(smRoot, satIOContext);*/ + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + SM_DBG1(("smsatVerify16: return control!!!\n")); + return SM_RC_SUCCESS; + } + sm_memset(LBA, 0, sizeof(LBA)); + sm_memset(TL, 0, sizeof(TL)); + + /* do not use memcpy due to indexing in LBA and TL */ + LBA[0] = scsiCmnd->cdb[2]; /* MSB */ + LBA[1] = scsiCmnd->cdb[3]; + LBA[2] = scsiCmnd->cdb[4]; + LBA[3] = scsiCmnd->cdb[5]; + LBA[4] = scsiCmnd->cdb[6]; + LBA[5] = scsiCmnd->cdb[7]; + LBA[6] = scsiCmnd->cdb[8]; + LBA[7] = scsiCmnd->cdb[9]; /* LSB */ + + TL[0] = 0; + TL[1] = 0; + TL[2] = 0; + TL[3] = 0; + TL[4] = scsiCmnd->cdb[10]; /* MSB */ + TL[5] = scsiCmnd->cdb[11]; + TL[6] = scsiCmnd->cdb[12]; + TL[7] = scsiCmnd->cdb[13]; /* LSB */ + lba = smsatComputeCDB16LBA(satIOContext); + tl = smsatComputeCDB16TL(satIOContext); + + if (pSatDevData->satNCQ != agTRUE && + pSatDevData->sat48BitSupport != agTRUE + ) + { + AllChk = smsatCheckLimit(LBA, TL, agFALSE, pSatDevData); + if (AllChk) + { + SM_DBG1(("smsatVerify16: return LBA out of range, not EXT!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + /*smEnqueueIO(smRoot, satIOContext);*/ + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + } + else + { + AllChk = smsatCheckLimit(LBA, TL, agTRUE, pSatDevData); + if (AllChk) + { + SM_DBG1(("smsatVerify16: return LBA out of range, EXT!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + /*smEnqueueIO(smRoot, satIOContext);*/ + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + } + + if (pSatDevData->sat48BitSupport == agTRUE) + { + SM_DBG5(("smsatVerify16: SAT_READ_VERIFY_SECTORS_EXT\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS_EXT;/* 0x42 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[9]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[8]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[7]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set 01000000 */ + fis->d.lbaLowExp = scsiCmnd->cdb[6]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = scsiCmnd->cdb[5]; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = scsiCmnd->cdb[4]; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[13]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[12]; /* FIS sector count (15:8) */ + + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + satIOContext->ATACmd = SAT_READ_VERIFY_SECTORS_EXT; + } + else + { + SM_DBG5(("smsatVerify16: SAT_READ_VERIFY_SECTORS\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS; /* 0x40 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[9]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[8]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[7]; /* FIS LBA (23:16) */ + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (scsiCmnd->cdb[6] & 0xF)); + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[13]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + satIOContext->ATACmd = SAT_READ_VERIFY_SECTORS; + + } + + satIOContext->currentLBA = lba; + satIOContext->OrgTL = tl; + + /* + computing number of loop and remainder for tl + 0xFF in case not ext + 0xFFFF in case EXT + */ + if (fis->h.command == SAT_READ_VERIFY_SECTORS) + { + LoopNum = smsatComputeLoopNum(tl, 0xFF); + } + else if (fis->h.command == SAT_READ_VERIFY_SECTORS_EXT) + { + /* SAT_READ_SECTORS_EXT, SAT_READ_DMA_EXT */ + LoopNum = smsatComputeLoopNum(tl, 0xFFFF); + } + else + { + SM_DBG1(("smsatVerify16: error case 1!!!\n")); + LoopNum = 1; + } + + satIOContext->LoopNum = LoopNum; + + if (LoopNum == 1) + { + SM_DBG5(("smsatVerify16: NON CHAINED data\n")); + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatNonChainedVerifyCB; + } + else + { + SM_DBG1(("smsatVerify16: CHAINED data!!!\n")); + /* re-setting tl */ + if (fis->h.command == SAT_READ_VERIFY_SECTORS) + { + fis->d.sectorCount = 0xFF; + } + else if (fis->h.command == SAT_READ_VERIFY_SECTORS_EXT) + { + fis->d.sectorCount = 0xFF; + fis->d.sectorCountExp = 0xFF; + } + else + { + SM_DBG1(("smsatVerify16: error case 2!!!\n")); + } + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatChainedVerifyCB; + } + + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + return (status); +} + +osGLOBAL bit32 +smsatTestUnitReady( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status; + bit32 agRequestType; + smDeviceData_t *pSatDevData; + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &smScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + SM_DBG5(("smsatTestUnitReady: start\n")); + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[5] & SCSI_NACA_MASK) || (scsiCmnd->cdb[5] & SCSI_LINK_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatTestUnitReady: return control!!!\n")); + return SM_RC_SUCCESS; + } + + /* SAT revision 8, 8.11.2, p42*/ + if (pSatDevData->satStopState == agTRUE) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NOT_READY, + 0, + SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_INITIALIZING_COMMAND_REQUIRED, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + SM_DBG1(("smsatTestUnitReady: stop state!!!\n")); + return SM_RC_SUCCESS; + } + + /* + * Check if format is in progress + */ + if (pSatDevData->satDriveState == SAT_DEV_STATE_FORMAT_IN_PROGRESS) + { + SM_DBG1(("smsatTestUnitReady: FORMAT_IN_PROGRESS!!!\n")); + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NOT_READY, + 0, + SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_FORMAT_IN_PROGRESS, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + SM_DBG1(("smsatTestUnitReady: format in progress!!!\n")); + return SM_RC_SUCCESS; + } + + /* + check previously issued ATA command + */ + if (pSatDevData->satPendingIO != 0) + { + if (pSatDevData->satDeviceFaultState == agTRUE) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_HARDWARE_ERROR, + 0, + SCSI_SNSCODE_LOGICAL_UNIT_FAILURE, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + SM_DBG1(("smsatTestUnitReady: previous command ended in error!!!\n")); + return SM_RC_SUCCESS; + } + } + + /* + check removalbe media feature set + */ + if(pSatDevData->satRemovableMedia && pSatDevData->satRemovableMediaEnabled) + { + SM_DBG5(("smsatTestUnitReady: sending get media status cmnd\n")); + /* send GET MEDIA STATUS command */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_GET_MEDIA_STATUS; /* 0xDA */ + fis->h.features = 0; /* FIS features NA */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.device = 0; /* FIS DEV is discared in SATA */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatTestUnitReadyCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + return (status); + } + /* + number 6) in SAT p42 + send ATA CHECK POWER MODE + */ + SM_DBG5(("smsatTestUnitReady: sending check power mode cmnd\n")); + status = smsatTestUnitReady_1( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + return (status); +} + +osGLOBAL bit32 +smsatTestUnitReady_1( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + /* + sends SAT_CHECK_POWER_MODE as a part of TESTUNITREADY + internally generated - no directly corresponding scsi + called in satIOCompleted as a part of satTestUnitReady(), SAT, revision8, 8.11.2, p42 + */ + bit32 status; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; + + fis = satIOContext->pFis; + SM_DBG5(("smsatTestUnitReady_1: start\n")); + /* + * Send the ATA CHECK POWER MODE command. + */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_CHECK_POWER_MODE; /* 0xE5 */ + fis->h.features = 0; + fis->d.lbaLow = 0; + fis->d.lbaMid = 0; + fis->d.lbaHigh = 0; + fis->d.device = 0; + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatTestUnitReadyCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + SM_DBG5(("smsatTestUnitReady_1: return\n")); + + return status; +} + +osGLOBAL bit32 +smsatInquiry( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + /* + CMDDT bit is obsolete in SPC-3 and this is assumed in SAT revision 8 + */ + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + smDeviceData_t *pSatDevData; + bit32 status; + + pSense = satIOContext->pSense; + scsiCmnd = &smScsiRequest->scsiCmnd; + pSatDevData = satIOContext->pSatDevData; + SM_DBG5(("smsatInquiry: start\n")); + SM_DBG5(("smsatInquiry: pSatDevData did %d\n", pSatDevData->id)); + //smhexdump("smsatInquiry", (bit8 *)scsiCmnd->cdb, 6); + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[5] & SCSI_NACA_MASK) || (scsiCmnd->cdb[5] & SCSI_LINK_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + /*smEnqueueIO(smRoot, satIOContext);*/ + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + SM_DBG1(("smsatInquiry: return control!!!\n")); + return SM_RC_SUCCESS; + } + + /* checking EVPD and Allocation Length */ + /* SPC-4 spec 6.4 p141 */ + /* EVPD bit == 0 && PAGE CODE != 0 */ + if ( !(scsiCmnd->cdb[1] & SCSI_EVPD_MASK) && + (scsiCmnd->cdb[2] != 0) + ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + /*smEnqueueIO(smRoot, satIOContext);*/ + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + SM_DBG1(("smsatInquiry: return EVPD and PAGE CODE!!!\n")); + return SM_RC_SUCCESS; + } + SM_DBG6(("smsatInquiry: allocation length 0x%x %d\n", ((scsiCmnd->cdb[3]) << 8) + scsiCmnd->cdb[4], ((scsiCmnd->cdb[3]) << 8) + scsiCmnd->cdb[4])); + /* convert OS IO to TD internal IO */ + if ( pSatDevData->IDDeviceValid == agFALSE) + { + status = smsatStartIDDev( + smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext + ); + SM_DBG6(("smsatInquiry: end status %d\n", status)); + return status; + } + else + { + SM_DBG6(("smsatInquiry: calling satInquiryIntCB\n")); + smsatInquiryIntCB( + smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext + ); + /*smEnqueueIO(smRoot, satIOContext);*/ + return SM_RC_SUCCESS; + } +} + + +osGLOBAL bit32 +smsatStartIDDev( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + smSatInternalIo_t *satIntIo = agNULL; + smDeviceData_t *satDevData = agNULL; + smIORequestBody_t *smIORequestBody; + smSatIOContext_t *satNewIOContext; + bit32 status; + + SM_DBG5(("smsatStartIDDev: start\n")); + + satDevData = satIOContext->pSatDevData; + + SM_DBG6(("smsatStartIDDev: before alloc\n")); + + /* allocate identify device command */ + satIntIo = smsatAllocIntIoResource( smRoot, + smIORequest, + satDevData, + sizeof(agsaSATAIdentifyData_t), /* 512; size of identify device data */ + satIntIo); + + SM_DBG6(("smsatStartIDDev: before after\n")); + + if (satIntIo == agNULL) + { + SM_DBG1(("smsatStartIDDev: can't alloacate!!!\n")); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + return SM_RC_FAILURE; + } + + satIntIo->satOrgSmIORequest = smIORequest; /* changed */ + smIORequestBody = satIntIo->satIntRequestBody; + satNewIOContext = &(smIORequestBody->transport.SATA.satIOContext); + + satNewIOContext->pSatDevData = satDevData; + satNewIOContext->pFis = &(smIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev); + satNewIOContext->pScsiCmnd = &(satIntIo->satIntSmScsiXchg.scsiCmnd); + satNewIOContext->pSense = &(smIORequestBody->transport.SATA.sensePayload); + satNewIOContext->pSmSenseData = &(smIORequestBody->transport.SATA.smSenseData); + satNewIOContext->smRequestBody = satIntIo->satIntRequestBody; /* key fix */ + satNewIOContext->interruptContext = tiInterruptContext; + satNewIOContext->satIntIoContext = satIntIo; + + satNewIOContext->psmDeviceHandle = agNULL; + satNewIOContext->satOrgIOContext = satIOContext; /* changed */ + + /* this is valid only for TD layer generated (not triggered by OS at all) IO */ + satNewIOContext->smScsiXchg = &(satIntIo->satIntSmScsiXchg); + + + SM_DBG6(("smsatStartIDDev: OS satIOContext %p \n", satIOContext)); + SM_DBG6(("smsatStartIDDev: TD satNewIOContext %p \n", satNewIOContext)); + SM_DBG6(("smsatStartIDDev: OS tiScsiXchg %p \n", satIOContext->smScsiXchg)); + SM_DBG6(("smsatStartIDDev: TD tiScsiXchg %p \n", satNewIOContext->smScsiXchg)); + + + + SM_DBG1(("smsatStartIDDev: satNewIOContext %p smIORequestBody %p!!!\n", satNewIOContext, smIORequestBody)); + + status = smsatSendIDDev( smRoot, + &satIntIo->satIntSmIORequest, /* New smIORequest */ + smDeviceHandle, + satNewIOContext->smScsiXchg, /* New tiScsiInitiatorRequest_t *tiScsiRequest, */ + satNewIOContext); + + if (status != SM_RC_SUCCESS) + { + SM_DBG1(("smsatStartIDDev: failed in sending!!!\n")); + + smsatFreeIntIoResource( smRoot, + satDevData, + satIntIo); + /*smEnqueueIO(smRoot, satIOContext);*/ + + return SM_RC_FAILURE; + } + + + SM_DBG6(("smsatStartIDDev: end\n")); + + return status; +} + +osGLOBAL bit32 +smsatSendIDDev( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status; + bit32 agRequestType; + smDeviceData_t *pSatDevData; + agsaFisRegHostToDevice_t *fis; +#ifdef SM_INTERNAL_DEBUG + smIORequestBody_t *smIORequestBody; + smSatInternalIo_t *satIntIoContext; +#endif + + pSatDevData = satIOContext->pSatDevData; + fis = satIOContext->pFis; + SM_DBG6(("smsatSendIDDev: start\n")); + SM_DBG6(("smsatSendIDDev: did %d\n", pSatDevData->id)); +#ifdef SM_INTERNAL_DEBUG + satIntIoContext = satIOContext->satIntIoContext; + smIORequestBody = satIntIoContext->satIntRequestBody; +#endif + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + if (pSatDevData->satDeviceType == SATA_ATAPI_DEVICE) + fis->h.command = SAT_IDENTIFY_PACKET_DEVICE; /* 0x40 */ + else + fis->h.command = SAT_IDENTIFY_DEVICE; /* 0xEC */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.device = 0; /* FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatInquiryCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + +#ifdef SM_INTERNAL_DEBUG + smhexdump("smsatSendIDDev", (bit8 *)satIOContext->pFis, sizeof(agsaFisRegHostToDevice_t)); + smhexdump("smsatSendIDDev LL", (bit8 *)&(smIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev), sizeof(agsaFisRegHostToDevice_t)); +#endif + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + SM_DBG6(("smsatSendIDDev: end status %d\n", status)); + return status; +} + +osGLOBAL bit32 +smsatRequestSense( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + /* + SAT Rev 8 p38, Table25 + sending SMART RETURN STATUS + Checking SMART Treshold Exceeded Condition is done in satRequestSenseCB() + Only fixed format sense data is support. In other words, we don't support DESC bit is set + in Request Sense + */ + bit32 status; + bit32 agRequestType; + smScsiRspSense_t *pSense; + smDeviceData_t *pSatDevData; + smIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + smIORequestBody_t *smIORequestBody; + smSatInternalIo_t *satIntIo = agNULL; + smSatIOContext_t *satIOContext2; + bit8 *pDataBuffer = agNULL; + bit32 allocationLen = 0; + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &smScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + pDataBuffer = (bit8 *) smScsiRequest->sglVirtualAddr; + allocationLen = scsiCmnd->cdb[4]; + allocationLen = MIN(allocationLen, scsiCmnd->expDataLength); + SM_DBG5(("smsatRequestSense: start\n")); + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[5] & SCSI_NACA_MASK) || (scsiCmnd->cdb[5] & SCSI_LINK_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + sm_memcpy(pDataBuffer, pSense, MIN(SENSE_DATA_LENGTH, allocationLen)); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatRequestSense: return control!!!\n")); + return SM_RC_SUCCESS; + } + + /* + Only fixed format sense data is support. In other words, we don't support DESC bit is set + in Request Sense + */ + if ( scsiCmnd->cdb[1] & ATA_REMOVABLE_MEDIA_DEVICE_MASK ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + sm_memcpy(pDataBuffer, pSense, MIN(SENSE_DATA_LENGTH, allocationLen)); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatRequestSense: DESC bit is set, which we don't support!!!\n")); + return SM_RC_SUCCESS; + } + + + if (pSatDevData->satSMARTEnabled == agTRUE) + { + /* sends SMART RETURN STATUS */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_SMART; /* 0xB0 */ + fis->h.features = SAT_SMART_RETURN_STATUS; /* FIS features */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaLowExp = 0; /* FIS LBA (31:24) */ + fis->d.lbaMid = 0x4F; /* FIS LBA (15:8 ) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHigh = 0xC2; /* FIS LBA (23:16) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.device = 0; /* FIS DEV is discared in SATA */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved4 = 0; + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatRequestSenseCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + SM_DBG4(("smsatRequestSense: if return, status %d\n", status)); + return (status); + } + else + { + /*allocate iocontext for xmitting xmit SAT_CHECK_POWER_MODE + then call satRequestSense2 */ + + SM_DBG4(("smsatRequestSense: before satIntIo %p\n", satIntIo)); + /* allocate iocontext */ + satIntIo = smsatAllocIntIoResource( smRoot, + smIORequest, /* original request */ + pSatDevData, + smScsiRequest->scsiCmnd.expDataLength, + satIntIo); + + SM_DBG4(("smsatRequestSense: after satIntIo %p\n", satIntIo)); + + if (satIntIo == agNULL) + { + /* failed during sending SMART RETURN STATUS */ + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_HARDWARE_IMPENDING_FAILURE, + satIOContext); + sm_memcpy(pDataBuffer, pSense, MIN(SENSE_DATA_LENGTH, allocationLen)); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext ); + + SM_DBG1(("smsatRequestSense: else fail 1!!!\n")); + return SM_RC_SUCCESS; + } /* end of memory allocation failure */ + + + /* + * Need to initialize all the fields within satIOContext except + * reqType and satCompleteCB which will be set depending on cmd. + */ + + if (satIntIo == agNULL) + { + SM_DBG4(("smsatRequestSense: satIntIo is NULL\n")); + } + else + { + SM_DBG4(("smsatRequestSense: satIntIo is NOT NULL\n")); + } + /* use this --- tttttthe one the same */ + + + satIntIo->satOrgSmIORequest = smIORequest; + smIORequestBody = (smIORequestBody_t *)satIntIo->satIntRequestBody; + satIOContext2 = &(smIORequestBody->transport.SATA.satIOContext); + + satIOContext2->pSatDevData = pSatDevData; + satIOContext2->pFis = &(smIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev); + satIOContext2->pScsiCmnd = &(satIntIo->satIntSmScsiXchg.scsiCmnd); + satIOContext2->pSense = &(smIORequestBody->transport.SATA.sensePayload); + satIOContext2->pSmSenseData = &(smIORequestBody->transport.SATA.smSenseData); + satIOContext2->pSmSenseData->senseData = satIOContext2->pSense; + satIOContext2->smRequestBody = satIntIo->satIntRequestBody; + satIOContext2->interruptContext = satIOContext->interruptContext; + satIOContext2->satIntIoContext = satIntIo; + satIOContext2->psmDeviceHandle = smDeviceHandle; + satIOContext2->satOrgIOContext = satIOContext; + + SM_DBG4(("smsatRequestSense: satIntIo->satIntSmScsiXchg.agSgl1.len %d\n", satIntIo->satIntSmScsiXchg.smSgl1.len)); + + SM_DBG4(("smsatRequestSense: satIntIo->satIntSmScsiXchg.agSgl1.upper %d\n", satIntIo->satIntSmScsiXchg.smSgl1.upper)); + + SM_DBG4(("smsatRequestSense: satIntIo->satIntSmScsiXchg.agSgl1.lower %d\n", satIntIo->satIntSmScsiXchg.smSgl1.lower)); + + SM_DBG4(("smsatRequestSense: satIntIo->satIntSmScsiXchg.agSgl1.type %d\n", satIntIo->satIntSmScsiXchg.smSgl1.type)); + + status = smsatRequestSense_1( smRoot, + &(satIntIo->satIntSmIORequest), + smDeviceHandle, + &(satIntIo->satIntSmScsiXchg), + satIOContext2); + + if (status != SM_RC_SUCCESS) + { + smsatFreeIntIoResource( smRoot, + pSatDevData, + satIntIo); + + /* failed during sending SMART RETURN STATUS */ + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_HARDWARE_IMPENDING_FAILURE, + satIOContext); + sm_memcpy(pDataBuffer, pSense, MIN(SENSE_DATA_LENGTH, allocationLen)); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + agNULL, + satIOContext->interruptContext ); + + SM_DBG1(("smsatRequestSense: else fail 2!!!\n")); + return SM_RC_SUCCESS; + } + SM_DBG4(("smsatRequestSense: else return success\n")); + return SM_RC_SUCCESS; + } +} + +osGLOBAL bit32 +smsatRequestSense_1( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + /* + sends SAT_CHECK_POWER_MODE + */ + bit32 status; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; + + fis = satIOContext->pFis; + SM_DBG5(("smsatRequestSense_1: start\n")); + /* + * Send the ATA CHECK POWER MODE command. + */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_CHECK_POWER_MODE; /* 0xE5 */ + fis->h.features = 0; + fis->d.lbaLow = 0; + fis->d.lbaMid = 0; + fis->d.lbaHigh = 0; + fis->d.device = 0; + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatRequestSenseCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + + SM_DBG4(("smsatRequestSense_1: smSgl1.len %d\n", smScsiRequest->smSgl1.len)); + + SM_DBG4(("smsatRequestSense_1: smSgl1.upper %d\n", smScsiRequest->smSgl1.upper)); + + SM_DBG4(("smsatRequestSense_1: smSgl1.lower %d\n", smScsiRequest->smSgl1.lower)); + + SM_DBG4(("smsatRequestSense_1: smSgl1.type %d\n", smScsiRequest->smSgl1.type)); + + // smhexdump("smsatRequestSense_1", (bit8 *)fis, sizeof(agsaFisRegHostToDevice_t)); + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + + + return status; +} + +osGLOBAL bit32 +smsatModeSense6( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + smScsiRspSense_t *pSense; + bit32 allocationLen; + smIniScsiCmnd_t *scsiCmnd; + bit32 pageSupported; + bit8 page; + bit8 *pModeSense; /* Mode Sense data buffer */ + smDeviceData_t *pSatDevData; + bit8 PC; + bit8 AllPages[MODE_SENSE6_RETURN_ALL_PAGES_LEN]; + bit8 Control[MODE_SENSE6_CONTROL_PAGE_LEN]; + bit8 RWErrorRecovery[MODE_SENSE6_READ_WRITE_ERROR_RECOVERY_PAGE_LEN]; + bit8 Caching[MODE_SENSE6_CACHING_LEN]; + bit8 InfoExceptionCtrl[MODE_SENSE6_INFORMATION_EXCEPTION_CONTROL_PAGE_LEN]; + bit8 lenRead = 0; + + + pSense = satIOContext->pSense; + scsiCmnd = &smScsiRequest->scsiCmnd; + pModeSense = (bit8 *) smScsiRequest->sglVirtualAddr; + pSatDevData = satIOContext->pSatDevData; + + //smhexdump("smsatModeSense6", (bit8 *)scsiCmnd->cdb, 6); + SM_DBG5(("smsatModeSense6: start\n")); + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[5] & SCSI_NACA_MASK) || (scsiCmnd->cdb[5] & SCSI_LINK_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + /*smEnqueueIO(smRoot, satIOContext);*/ + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + SM_DBG1(("smsatModeSense6: return control!!!\n")); + return SM_RC_SUCCESS; + } + /* checking PC(Page Control) + SAT revion 8, 8.5.3 p33 and 10.1.2, p66 + */ + PC = (bit8)((scsiCmnd->cdb[2]) & SCSI_MODE_SENSE6_PC_MASK); + if (PC != 0) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + /*smEnqueueIO(smRoot, satIOContext);*/ + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + SM_DBG1(("smsatModeSense6: return due to PC value pc 0x%x!!!\n", PC >> 6)); + return SM_RC_SUCCESS; + } + /* reading PAGE CODE */ + page = (bit8)((scsiCmnd->cdb[2]) & SCSI_MODE_SENSE6_PAGE_CODE_MASK); + + + SM_DBG5(("smsatModeSense6: page=0x%x\n", page)); + + allocationLen = scsiCmnd->cdb[4]; + allocationLen = MIN(allocationLen, scsiCmnd->expDataLength); + /* + Based on page code value, returns a corresponding mode page + note: no support for subpage + */ + switch(page) + { + case MODESENSE_RETURN_ALL_PAGES: + case MODESENSE_CONTROL_PAGE: /* control */ + case MODESENSE_READ_WRITE_ERROR_RECOVERY_PAGE: /* Read-Write Error Recovery */ + case MODESENSE_CACHING: /* caching */ + case MODESENSE_INFORMATION_EXCEPTION_CONTROL_PAGE: /* informational exceptions control*/ + pageSupported = agTRUE; + break; + case MODESENSE_VENDOR_SPECIFIC_PAGE: /* vendor specific */ + default: + pageSupported = agFALSE; + break; + } + + if (pageSupported == agFALSE) + { + + SM_DBG1(("smsatModeSense6 *** ERROR *** not supported page 0x%x did %d!!!\n", + page, pSatDevData->id)); + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_COMMAND, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + + switch(page) + { + case MODESENSE_RETURN_ALL_PAGES: + lenRead = (bit8)MIN(allocationLen, MODE_SENSE6_RETURN_ALL_PAGES_LEN); + break; + case MODESENSE_CONTROL_PAGE: /* control */ + lenRead = (bit8)MIN(allocationLen, MODE_SENSE6_CONTROL_PAGE_LEN); + break; + case MODESENSE_READ_WRITE_ERROR_RECOVERY_PAGE: /* Read-Write Error Recovery */ + lenRead = (bit8)MIN(allocationLen, MODE_SENSE6_READ_WRITE_ERROR_RECOVERY_PAGE_LEN); + break; + case MODESENSE_CACHING: /* caching */ + lenRead = (bit8)MIN(allocationLen, MODE_SENSE6_CACHING_LEN); + break; + case MODESENSE_INFORMATION_EXCEPTION_CONTROL_PAGE: /* informational exceptions control*/ + lenRead = (bit8)MIN(allocationLen, MODE_SENSE6_INFORMATION_EXCEPTION_CONTROL_PAGE_LEN); + break; + default: + SM_DBG1(("smsatModeSense6: default error page %d!!!\n", page)); + break; + } + + if (page == MODESENSE_RETURN_ALL_PAGES) + { + SM_DBG5(("smsatModeSense6: MODESENSE_RETURN_ALL_PAGES\n")); + AllPages[0] = (bit8)(lenRead - 1); + AllPages[1] = 0x00; /* default medium type (currently mounted medium type) */ + AllPages[2] = 0x00; /* no write-protect, no support for DPO-FUA */ + AllPages[3] = 0x08; /* block descriptor length */ + + /* + * Fill-up direct-access device block-descriptor, SAT, Table 19 + */ + + /* density code */ + AllPages[4] = 0x04; /* density-code : reserved for direct-access */ + /* number of blocks */ + AllPages[5] = 0x00; /* unspecified */ + AllPages[6] = 0x00; /* unspecified */ + AllPages[7] = 0x00; /* unspecified */ + /* reserved */ + AllPages[8] = 0x00; /* reserved */ + /* Block size */ + AllPages[9] = 0x00; + AllPages[10] = 0x02; /* Block size is always 512 bytes */ + AllPages[11] = 0x00; + + /* MODESENSE_READ_WRITE_ERROR_RECOVERY_PAGE */ + AllPages[12] = 0x01; /* page code */ + AllPages[13] = 0x0A; /* page length */ + AllPages[14] = 0x40; /* ARRE is set */ + AllPages[15] = 0x00; + AllPages[16] = 0x00; + AllPages[17] = 0x00; + AllPages[18] = 0x00; + AllPages[19] = 0x00; + AllPages[20] = 0x00; + AllPages[21] = 0x00; + AllPages[22] = 0x00; + AllPages[23] = 0x00; + /* MODESENSE_CACHING */ + AllPages[24] = 0x08; /* page code */ + AllPages[25] = 0x12; /* page length */ + if (pSatDevData->satWriteCacheEnabled == agTRUE) + { + AllPages[26] = 0x04;/* WCE bit is set */ + } + else + { + AllPages[26] = 0x00;/* WCE bit is NOT set */ + } + + AllPages[27] = 0x00; + AllPages[28] = 0x00; + AllPages[29] = 0x00; + AllPages[30] = 0x00; + AllPages[31] = 0x00; + AllPages[32] = 0x00; + AllPages[33] = 0x00; + AllPages[34] = 0x00; + AllPages[35] = 0x00; + if (pSatDevData->satLookAheadEnabled == agTRUE) + { + AllPages[36] = 0x00;/* DRA bit is NOT set */ + } + else + { + AllPages[36] = 0x20;/* DRA bit is set */ + } + AllPages[37] = 0x00; + AllPages[38] = 0x00; + AllPages[39] = 0x00; + AllPages[40] = 0x00; + AllPages[41] = 0x00; + AllPages[42] = 0x00; + AllPages[43] = 0x00; + /* MODESENSE_CONTROL_PAGE */ + AllPages[44] = 0x0A; /* page code */ + AllPages[45] = 0x0A; /* page length */ + AllPages[46] = 0x02; /* only GLTSD bit is set */ + if (pSatDevData->satNCQ == agTRUE) + { + AllPages[47] = 0x12; /* Queue Alogorithm modifier 1b and QErr 01b*/ + } + else + { + AllPages[47] = 0x02; /* Queue Alogorithm modifier 0b and QErr 01b */ + } + AllPages[48] = 0x00; + AllPages[49] = 0x00; + AllPages[50] = 0x00; /* obsolete */ + AllPages[51] = 0x00; /* obsolete */ + AllPages[52] = 0xFF; /* Busy Timeout Period */ + AllPages[53] = 0xFF; /* Busy Timeout Period */ + AllPages[54] = 0x00; /* we don't support non-000b value for the self-test code */ + AllPages[55] = 0x00; /* we don't support non-000b value for the self-test code */ + /* MODESENSE_INFORMATION_EXCEPTION_CONTROL_PAGE */ + AllPages[56] = 0x1C; /* page code */ + AllPages[57] = 0x0A; /* page length */ + if (pSatDevData->satSMARTEnabled == agTRUE) + { + AllPages[58] = 0x00;/* DEXCPT bit is NOT set */ + } + else + { + AllPages[58] = 0x08;/* DEXCPT bit is set */ + } + AllPages[59] = 0x00; /* We don't support MRIE */ + AllPages[60] = 0x00; /* Interval timer vendor-specific */ + AllPages[61] = 0x00; + AllPages[62] = 0x00; + AllPages[63] = 0x00; + AllPages[64] = 0x00; /* REPORT-COUNT */ + AllPages[65] = 0x00; + AllPages[66] = 0x00; + AllPages[67] = 0x00; + + sm_memcpy(pModeSense, &AllPages, lenRead); + } + else if (page == MODESENSE_CONTROL_PAGE) + { + SM_DBG5(("smsatModeSense6: MODESENSE_CONTROL_PAGE\n")); + Control[0] = MODE_SENSE6_CONTROL_PAGE_LEN - 1; + Control[1] = 0x00; /* default medium type (currently mounted medium type) */ + Control[2] = 0x00; /* no write-protect, no support for DPO-FUA */ + Control[3] = 0x08; /* block descriptor length */ + /* + * Fill-up direct-access device block-descriptor, SAT, Table 19 + */ + + /* density code */ + Control[4] = 0x04; /* density-code : reserved for direct-access */ + /* number of blocks */ + Control[5] = 0x00; /* unspecified */ + Control[6] = 0x00; /* unspecified */ + Control[7] = 0x00; /* unspecified */ + /* reserved */ + Control[8] = 0x00; /* reserved */ + /* Block size */ + Control[9] = 0x00; + Control[10] = 0x02; /* Block size is always 512 bytes */ + Control[11] = 0x00; + /* + * Fill-up control mode page, SAT, Table 65 + */ + Control[12] = 0x0A; /* page code */ + Control[13] = 0x0A; /* page length */ + Control[14] = 0x02; /* only GLTSD bit is set */ + if (pSatDevData->satNCQ == agTRUE) + { + Control[15] = 0x12; /* Queue Alogorithm modifier 1b and QErr 01b*/ + } + else + { + Control[15] = 0x02; /* Queue Alogorithm modifier 0b and QErr 01b */ + } + Control[16] = 0x00; + Control[17] = 0x00; + Control[18] = 0x00; /* obsolete */ + Control[19] = 0x00; /* obsolete */ + Control[20] = 0xFF; /* Busy Timeout Period */ + Control[21] = 0xFF; /* Busy Timeout Period */ + Control[22] = 0x00; /* we don't support non-000b value for the self-test code */ + Control[23] = 0x00; /* we don't support non-000b value for the self-test code */ + + sm_memcpy(pModeSense, &Control, lenRead); + + } + else if (page == MODESENSE_READ_WRITE_ERROR_RECOVERY_PAGE) + { + SM_DBG5(("smsatModeSense6: MODESENSE_READ_WRITE_ERROR_RECOVERY_PAGE\n")); + RWErrorRecovery[0] = MODE_SENSE6_READ_WRITE_ERROR_RECOVERY_PAGE_LEN - 1; + RWErrorRecovery[1] = 0x00; /* default medium type (currently mounted medium type) */ + RWErrorRecovery[2] = 0x00; /* no write-protect, no support for DPO-FUA */ + RWErrorRecovery[3] = 0x08; /* block descriptor length */ + /* + * Fill-up direct-access device block-descriptor, SAT, Table 19 + */ + + /* density code */ + RWErrorRecovery[4] = 0x04; /* density-code : reserved for direct-access */ + /* number of blocks */ + RWErrorRecovery[5] = 0x00; /* unspecified */ + RWErrorRecovery[6] = 0x00; /* unspecified */ + RWErrorRecovery[7] = 0x00; /* unspecified */ + /* reserved */ + RWErrorRecovery[8] = 0x00; /* reserved */ + /* Block size */ + RWErrorRecovery[9] = 0x00; + RWErrorRecovery[10] = 0x02; /* Block size is always 512 bytes */ + RWErrorRecovery[11] = 0x00; + /* + * Fill-up Read-Write Error Recovery mode page, SAT, Table 66 + */ + RWErrorRecovery[12] = 0x01; /* page code */ + RWErrorRecovery[13] = 0x0A; /* page length */ + RWErrorRecovery[14] = 0x40; /* ARRE is set */ + RWErrorRecovery[15] = 0x00; + RWErrorRecovery[16] = 0x00; + RWErrorRecovery[17] = 0x00; + RWErrorRecovery[18] = 0x00; + RWErrorRecovery[19] = 0x00; + RWErrorRecovery[20] = 0x00; + RWErrorRecovery[21] = 0x00; + RWErrorRecovery[22] = 0x00; + RWErrorRecovery[23] = 0x00; + + sm_memcpy(pModeSense, &RWErrorRecovery, lenRead); + + } + else if (page == MODESENSE_CACHING) + { + SM_DBG5(("smsatModeSense6: MODESENSE_CACHING\n")); + /* special case */ + if (allocationLen == 4 && page == MODESENSE_CACHING) + { + SM_DBG5(("smsatModeSense6: linux 2.6.8.24 support\n")); + + Caching[0] = 0x20 - 1; /* 32 - 1 */ + Caching[1] = 0x00; /* default medium type (currently mounted medium type) */ + Caching[2] = 0x00; /* no write-protect, no support for DPO-FUA */ + Caching[3] = 0x08; /* block descriptor length */ + + sm_memcpy(pModeSense, &Caching, 4); + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + return SM_RC_SUCCESS; + } + Caching[0] = MODE_SENSE6_CACHING_LEN - 1; + Caching[1] = 0x00; /* default medium type (currently mounted medium type) */ + Caching[2] = 0x00; /* no write-protect, no support for DPO-FUA */ + Caching[3] = 0x08; /* block descriptor length */ + /* + * Fill-up direct-access device block-descriptor, SAT, Table 19 + */ + + /* density code */ + Caching[4] = 0x04; /* density-code : reserved for direct-access */ + /* number of blocks */ + Caching[5] = 0x00; /* unspecified */ + Caching[6] = 0x00; /* unspecified */ + Caching[7] = 0x00; /* unspecified */ + /* reserved */ + Caching[8] = 0x00; /* reserved */ + /* Block size */ + Caching[9] = 0x00; + Caching[10] = 0x02; /* Block size is always 512 bytes */ + Caching[11] = 0x00; + /* + * Fill-up Caching mode page, SAT, Table 67 + */ + /* length 20 */ + Caching[12] = 0x08; /* page code */ + Caching[13] = 0x12; /* page length */ + if (pSatDevData->satWriteCacheEnabled == agTRUE) + { + Caching[14] = 0x04;/* WCE bit is set */ + } + else + { + Caching[14] = 0x00;/* WCE bit is NOT set */ + } + + Caching[15] = 0x00; + Caching[16] = 0x00; + Caching[17] = 0x00; + Caching[18] = 0x00; + Caching[19] = 0x00; + Caching[20] = 0x00; + Caching[21] = 0x00; + Caching[22] = 0x00; + Caching[23] = 0x00; + if (pSatDevData->satLookAheadEnabled == agTRUE) + { + Caching[24] = 0x00;/* DRA bit is NOT set */ + } + else + { + Caching[24] = 0x20;/* DRA bit is set */ + } + Caching[25] = 0x00; + Caching[26] = 0x00; + Caching[27] = 0x00; + Caching[28] = 0x00; + Caching[29] = 0x00; + Caching[30] = 0x00; + Caching[31] = 0x00; + + sm_memcpy(pModeSense, &Caching, lenRead); + + } + else if (page == MODESENSE_INFORMATION_EXCEPTION_CONTROL_PAGE) + { + SM_DBG5(("smsatModeSense6: MODESENSE_INFORMATION_EXCEPTION_CONTROL_PAGE\n")); + InfoExceptionCtrl[0] = MODE_SENSE6_INFORMATION_EXCEPTION_CONTROL_PAGE_LEN - 1; + InfoExceptionCtrl[1] = 0x00; /* default medium type (currently mounted medium type) */ + InfoExceptionCtrl[2] = 0x00; /* no write-protect, no support for DPO-FUA */ + InfoExceptionCtrl[3] = 0x08; /* block descriptor length */ + /* + * Fill-up direct-access device block-descriptor, SAT, Table 19 + */ + + /* density code */ + InfoExceptionCtrl[4] = 0x04; /* density-code : reserved for direct-access */ + /* number of blocks */ + InfoExceptionCtrl[5] = 0x00; /* unspecified */ + InfoExceptionCtrl[6] = 0x00; /* unspecified */ + InfoExceptionCtrl[7] = 0x00; /* unspecified */ + /* reserved */ + InfoExceptionCtrl[8] = 0x00; /* reserved */ + /* Block size */ + InfoExceptionCtrl[9] = 0x00; + InfoExceptionCtrl[10] = 0x02; /* Block size is always 512 bytes */ + InfoExceptionCtrl[11] = 0x00; + /* + * Fill-up informational-exceptions control mode page, SAT, Table 68 + */ + InfoExceptionCtrl[12] = 0x1C; /* page code */ + InfoExceptionCtrl[13] = 0x0A; /* page length */ + if (pSatDevData->satSMARTEnabled == agTRUE) + { + InfoExceptionCtrl[14] = 0x00;/* DEXCPT bit is NOT set */ + } + else + { + InfoExceptionCtrl[14] = 0x08;/* DEXCPT bit is set */ + } + InfoExceptionCtrl[15] = 0x00; /* We don't support MRIE */ + InfoExceptionCtrl[16] = 0x00; /* Interval timer vendor-specific */ + InfoExceptionCtrl[17] = 0x00; + InfoExceptionCtrl[18] = 0x00; + InfoExceptionCtrl[19] = 0x00; + InfoExceptionCtrl[20] = 0x00; /* REPORT-COUNT */ + InfoExceptionCtrl[21] = 0x00; + InfoExceptionCtrl[22] = 0x00; + InfoExceptionCtrl[23] = 0x00; + sm_memcpy(pModeSense, &InfoExceptionCtrl, lenRead); + + } + else + { + /* Error */ + SM_DBG1(("smsatModeSense6: Error page %d!!!\n", page)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_COMMAND, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + + /* there can be only underrun not overrun in error case */ + if (allocationLen > lenRead) + { + SM_DBG6(("smsatModeSense6 reporting underrun lenRead=0x%x allocationLen=0x%x\n", lenRead, allocationLen)); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOUnderRun, + allocationLen - lenRead, + agNULL, + satIOContext->interruptContext ); + + + } + else + { + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + } + + return SM_RC_SUCCESS; + +} + +osGLOBAL bit32 +smsatModeSense10( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + smScsiRspSense_t *pSense; + bit32 allocationLen; + smIniScsiCmnd_t *scsiCmnd; + bit32 pageSupported; + bit8 page; + bit8 *pModeSense; /* Mode Sense data buffer */ + smDeviceData_t *pSatDevData; + bit8 PC; /* page control */ + bit8 LLBAA; /* Long LBA Accepted */ + bit32 index; + bit8 AllPages[MODE_SENSE10_RETURN_ALL_PAGES_LLBAA_LEN]; + bit8 Control[MODE_SENSE10_CONTROL_PAGE_LLBAA_LEN]; + bit8 RWErrorRecovery[MODE_SENSE10_READ_WRITE_ERROR_RECOVERY_PAGE_LLBAA_LEN]; + bit8 Caching[MODE_SENSE10_CACHING_LLBAA_LEN]; + bit8 InfoExceptionCtrl[MODE_SENSE10_INFORMATION_EXCEPTION_CONTROL_PAGE_LLBAA_LEN]; + bit8 lenRead = 0; + + pSense = satIOContext->pSense; + scsiCmnd = &smScsiRequest->scsiCmnd; + pModeSense = (bit8 *) smScsiRequest->sglVirtualAddr; + pSatDevData = satIOContext->pSatDevData; + SM_DBG5(("smsatModeSense10: start\n")); + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[9] & SCSI_NACA_MASK) || (scsiCmnd->cdb[9] & SCSI_LINK_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatModeSense10: return control!!!\n")); + return SM_RC_SUCCESS; + } + + /* checking PC(Page Control) + SAT revion 8, 8.5.3 p33 and 10.1.2, p66 + */ + PC = (bit8)((scsiCmnd->cdb[2]) & SCSI_MODE_SENSE10_PC_MASK); + if (PC != 0) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatModeSense10: return due to PC value pc 0x%x!!!\n", PC)); + return SM_RC_SUCCESS; + } + + /* finding LLBAA bit */ + LLBAA = (bit8)((scsiCmnd->cdb[1]) & SCSI_MODE_SENSE10_LLBAA_MASK); + + /* reading PAGE CODE */ + page = (bit8)((scsiCmnd->cdb[2]) & SCSI_MODE_SENSE10_PAGE_CODE_MASK); + SM_DBG5(("smsatModeSense10: page=0x%x, did %d\n", page, pSatDevData->id)); + allocationLen = (scsiCmnd->cdb[7] << 8) + scsiCmnd->cdb[8]; + allocationLen = MIN(allocationLen, scsiCmnd->expDataLength); + + /* + Based on page code value, returns a corresponding mode page + note: no support for subpage + */ + switch(page) + { + case MODESENSE_RETURN_ALL_PAGES: /* return all pages */ + case MODESENSE_CONTROL_PAGE: /* control */ + case MODESENSE_READ_WRITE_ERROR_RECOVERY_PAGE: /* Read-Write Error Recovery */ + case MODESENSE_CACHING: /* caching */ + case MODESENSE_INFORMATION_EXCEPTION_CONTROL_PAGE: /* informational exceptions control*/ + pageSupported = agTRUE; + break; + case MODESENSE_VENDOR_SPECIFIC_PAGE: /* vendor specific */ + default: + pageSupported = agFALSE; + break; + } + if (pageSupported == agFALSE) + { + SM_DBG1(("smsatModeSense10 *** ERROR *** not supported page 0x%x did %d!!!\n", page, pSatDevData->id)); + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_COMMAND, + satIOContext); + /*smEnqueueIO(smRoot, satIOContext);*/ + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + switch(page) + { + case MODESENSE_RETURN_ALL_PAGES: + if (LLBAA) + { + lenRead = (bit8)MIN(allocationLen, MODE_SENSE10_RETURN_ALL_PAGES_LLBAA_LEN); + } + else + { + lenRead = (bit8)MIN(allocationLen, MODE_SENSE10_RETURN_ALL_PAGES_LEN); + } + break; + case MODESENSE_CONTROL_PAGE: /* control */ + if (LLBAA) + { + lenRead = (bit8)MIN(allocationLen, MODE_SENSE10_CONTROL_PAGE_LLBAA_LEN); + } + else + { + lenRead = (bit8)MIN(allocationLen, MODE_SENSE10_CONTROL_PAGE_LEN); + } + break; + case MODESENSE_READ_WRITE_ERROR_RECOVERY_PAGE: /* Read-Write Error Recovery */ + if (LLBAA) + { + lenRead = (bit8)MIN(allocationLen, MODE_SENSE10_READ_WRITE_ERROR_RECOVERY_PAGE_LLBAA_LEN); + } + else + { + lenRead = (bit8)MIN(allocationLen, MODE_SENSE10_READ_WRITE_ERROR_RECOVERY_PAGE_LEN); + } + break; + case MODESENSE_CACHING: /* caching */ + if (LLBAA) + { + lenRead = (bit8)MIN(allocationLen, MODE_SENSE10_CACHING_LLBAA_LEN); + } + else + { + lenRead = (bit8)MIN(allocationLen, MODE_SENSE10_CACHING_LEN); + } + break; + case MODESENSE_INFORMATION_EXCEPTION_CONTROL_PAGE: /* informational exceptions control*/ + if (LLBAA) + { + lenRead = (bit8)MIN(allocationLen, MODE_SENSE10_INFORMATION_EXCEPTION_CONTROL_PAGE_LLBAA_LEN); + } + else + { + lenRead = (bit8)MIN(allocationLen, MODE_SENSE10_INFORMATION_EXCEPTION_CONTROL_PAGE_LEN); + } + break; + default: + SM_DBG1(("smsatModeSense10: default error page %d!!!\n", page)); + break; + } + + if (page == MODESENSE_RETURN_ALL_PAGES) + { + SM_DBG5(("smsatModeSense10: MODESENSE_RETURN_ALL_PAGES\n")); + AllPages[0] = 0; + AllPages[1] = (bit8)(lenRead - 2); + AllPages[2] = 0x00; /* medium type: default medium type (currently mounted medium type) */ + AllPages[3] = 0x00; /* device-specific param: no write-protect, no support for DPO-FUA */ + if (LLBAA) + { + AllPages[4] = 0x00; /* reserved and LONGLBA */ + AllPages[4] = (bit8)(AllPages[4] | 0x1); /* LONGLBA is set */ + } + else + { + AllPages[4] = 0x00; /* reserved and LONGLBA: LONGLBA is not set */ + } + AllPages[5] = 0x00; /* reserved */ + AllPages[6] = 0x00; /* block descriptot length */ + if (LLBAA) + { + AllPages[7] = 0x10; /* block descriptor length: LONGLBA is set. So, length is 16 */ + } + else + { + AllPages[7] = 0x08; /* block descriptor length: LONGLBA is NOT set. So, length is 8 */ + } + + /* + * Fill-up direct-access device block-descriptor, SAT, Table 19 + */ + + if (LLBAA) + { + /* density code */ + AllPages[8] = 0x04; /* density-code : reserved for direct-access */ + /* number of blocks */ + AllPages[9] = 0x00; /* unspecified */ + AllPages[10] = 0x00; /* unspecified */ + AllPages[11] = 0x00; /* unspecified */ + AllPages[12] = 0x00; /* unspecified */ + AllPages[13] = 0x00; /* unspecified */ + AllPages[14] = 0x00; /* unspecified */ + AllPages[15] = 0x00; /* unspecified */ + /* reserved */ + AllPages[16] = 0x00; /* reserved */ + AllPages[17] = 0x00; /* reserved */ + AllPages[18] = 0x00; /* reserved */ + AllPages[19] = 0x00; /* reserved */ + /* Block size */ + AllPages[20] = 0x00; + AllPages[21] = 0x00; + AllPages[22] = 0x02; /* Block size is always 512 bytes */ + AllPages[23] = 0x00; + } + else + { + /* density code */ + AllPages[8] = 0x04; /* density-code : reserved for direct-access */ + /* number of blocks */ + AllPages[9] = 0x00; /* unspecified */ + AllPages[10] = 0x00; /* unspecified */ + AllPages[11] = 0x00; /* unspecified */ + /* reserved */ + AllPages[12] = 0x00; /* reserved */ + /* Block size */ + AllPages[13] = 0x00; + AllPages[14] = 0x02; /* Block size is always 512 bytes */ + AllPages[15] = 0x00; + } + + if (LLBAA) + { + index = 24; + } + else + { + index = 16; + } + /* MODESENSE_READ_WRITE_ERROR_RECOVERY_PAGE */ + AllPages[index+0] = 0x01; /* page code */ + AllPages[index+1] = 0x0A; /* page length */ + AllPages[index+2] = 0x40; /* ARRE is set */ + AllPages[index+3] = 0x00; + AllPages[index+4] = 0x00; + AllPages[index+5] = 0x00; + AllPages[index+6] = 0x00; + AllPages[index+7] = 0x00; + AllPages[index+8] = 0x00; + AllPages[index+9] = 0x00; + AllPages[index+10] = 0x00; + AllPages[index+11] = 0x00; + + /* MODESENSE_CACHING */ + /* + * Fill-up Caching mode page, SAT, Table 67 + */ + /* length 20 */ + AllPages[index+12] = 0x08; /* page code */ + AllPages[index+13] = 0x12; /* page length */ + if (pSatDevData->satWriteCacheEnabled == agTRUE) + { + AllPages[index+14] = 0x04;/* WCE bit is set */ + } + else + { + AllPages[index+14] = 0x00;/* WCE bit is NOT set */ + } + + AllPages[index+15] = 0x00; + AllPages[index+16] = 0x00; + AllPages[index+17] = 0x00; + AllPages[index+18] = 0x00; + AllPages[index+19] = 0x00; + AllPages[index+20] = 0x00; + AllPages[index+21] = 0x00; + AllPages[index+22] = 0x00; + AllPages[index+23] = 0x00; + if (pSatDevData->satLookAheadEnabled == agTRUE) + { + AllPages[index+24] = 0x00;/* DRA bit is NOT set */ + } + else + { + AllPages[index+24] = 0x20;/* DRA bit is set */ + } + AllPages[index+25] = 0x00; + AllPages[index+26] = 0x00; + AllPages[index+27] = 0x00; + AllPages[index+28] = 0x00; + AllPages[index+29] = 0x00; + AllPages[index+30] = 0x00; + AllPages[index+31] = 0x00; + + /* MODESENSE_CONTROL_PAGE */ + /* + * Fill-up control mode page, SAT, Table 65 + */ + AllPages[index+32] = 0x0A; /* page code */ + AllPages[index+33] = 0x0A; /* page length */ + AllPages[index+34] = 0x02; /* only GLTSD bit is set */ + if (pSatDevData->satNCQ == agTRUE) + { + AllPages[index+35] = 0x12; /* Queue Alogorithm modifier 1b and QErr 01b*/ + } + else + { + AllPages[index+35] = 0x02; /* Queue Alogorithm modifier 0b and QErr 01b */ + } + AllPages[index+36] = 0x00; + AllPages[index+37] = 0x00; + AllPages[index+38] = 0x00; /* obsolete */ + AllPages[index+39] = 0x00; /* obsolete */ + AllPages[index+40] = 0xFF; /* Busy Timeout Period */ + AllPages[index+41] = 0xFF; /* Busy Timeout Period */ + AllPages[index+42] = 0x00; /* we don't support non-000b value for the self-test code */ + AllPages[index+43] = 0x00; /* we don't support non-000b value for the self-test code */ + + /* MODESENSE_INFORMATION_EXCEPTION_CONTROL_PAGE */ + /* + * Fill-up informational-exceptions control mode page, SAT, Table 68 + */ + AllPages[index+44] = 0x1C; /* page code */ + AllPages[index+45] = 0x0A; /* page length */ + if (pSatDevData->satSMARTEnabled == agTRUE) + { + AllPages[index+46] = 0x00;/* DEXCPT bit is NOT set */ + } + else + { + AllPages[index+46] = 0x08;/* DEXCPT bit is set */ + } + AllPages[index+47] = 0x00; /* We don't support MRIE */ + AllPages[index+48] = 0x00; /* Interval timer vendor-specific */ + AllPages[index+49] = 0x00; + AllPages[index+50] = 0x00; + AllPages[index+51] = 0x00; + AllPages[index+52] = 0x00; /* REPORT-COUNT */ + AllPages[index+53] = 0x00; + AllPages[index+54] = 0x00; + AllPages[index+55] = 0x00; + + sm_memcpy(pModeSense, &AllPages, lenRead); + } + else if (page == MODESENSE_CONTROL_PAGE) + { + SM_DBG5(("smsatModeSense10: MODESENSE_CONTROL_PAGE\n")); + Control[0] = 0; + Control[1] = (bit8)(lenRead - 2); + Control[2] = 0x00; /* medium type: default medium type (currently mounted medium type) */ + Control[3] = 0x00; /* device-specific param: no write-protect, no support for DPO-FUA */ + if (LLBAA) + { + Control[4] = 0x00; /* reserved and LONGLBA */ + Control[4] = (bit8)(Control[4] | 0x1); /* LONGLBA is set */ + } + else + { + Control[4] = 0x00; /* reserved and LONGLBA: LONGLBA is not set */ + } + Control[5] = 0x00; /* reserved */ + Control[6] = 0x00; /* block descriptot length */ + if (LLBAA) + { + Control[7] = 0x10; /* block descriptor length: LONGLBA is set. So, length is 16 */ + } + else + { + Control[7] = 0x08; /* block descriptor length: LONGLBA is NOT set. So, length is 8 */ + } + + /* + * Fill-up direct-access device block-descriptor, SAT, Table 19 + */ + + if (LLBAA) + { + /* density code */ + Control[8] = 0x04; /* density-code : reserved for direct-access */ + /* number of blocks */ + Control[9] = 0x00; /* unspecified */ + Control[10] = 0x00; /* unspecified */ + Control[11] = 0x00; /* unspecified */ + Control[12] = 0x00; /* unspecified */ + Control[13] = 0x00; /* unspecified */ + Control[14] = 0x00; /* unspecified */ + Control[15] = 0x00; /* unspecified */ + /* reserved */ + Control[16] = 0x00; /* reserved */ + Control[17] = 0x00; /* reserved */ + Control[18] = 0x00; /* reserved */ + Control[19] = 0x00; /* reserved */ + /* Block size */ + Control[20] = 0x00; + Control[21] = 0x00; + Control[22] = 0x02; /* Block size is always 512 bytes */ + Control[23] = 0x00; + } + else + { + /* density code */ + Control[8] = 0x04; /* density-code : reserved for direct-access */ + /* number of blocks */ + Control[9] = 0x00; /* unspecified */ + Control[10] = 0x00; /* unspecified */ + Control[11] = 0x00; /* unspecified */ + /* reserved */ + Control[12] = 0x00; /* reserved */ + /* Block size */ + Control[13] = 0x00; + Control[14] = 0x02; /* Block size is always 512 bytes */ + Control[15] = 0x00; + } + + if (LLBAA) + { + index = 24; + } + else + { + index = 16; + } + /* + * Fill-up control mode page, SAT, Table 65 + */ + Control[index+0] = 0x0A; /* page code */ + Control[index+1] = 0x0A; /* page length */ + Control[index+2] = 0x02; /* only GLTSD bit is set */ + if (pSatDevData->satNCQ == agTRUE) + { + Control[index+3] = 0x12; /* Queue Alogorithm modifier 1b and QErr 01b*/ + } + else + { + Control[index+3] = 0x02; /* Queue Alogorithm modifier 0b and QErr 01b */ + } + Control[index+4] = 0x00; + Control[index+5] = 0x00; + Control[index+6] = 0x00; /* obsolete */ + Control[index+7] = 0x00; /* obsolete */ + Control[index+8] = 0xFF; /* Busy Timeout Period */ + Control[index+9] = 0xFF; /* Busy Timeout Period */ + Control[index+10] = 0x00; /* we don't support non-000b value for the self-test code */ + Control[index+11] = 0x00; /* we don't support non-000b value for the self-test code */ + + sm_memcpy(pModeSense, &Control, lenRead); + } + else if (page == MODESENSE_READ_WRITE_ERROR_RECOVERY_PAGE) + { + SM_DBG5(("smsatModeSense10: MODESENSE_READ_WRITE_ERROR_RECOVERY_PAGE\n")); + RWErrorRecovery[0] = 0; + RWErrorRecovery[1] = (bit8)(lenRead - 2); + RWErrorRecovery[2] = 0x00; /* medium type: default medium type (currently mounted medium type) */ + RWErrorRecovery[3] = 0x00; /* device-specific param: no write-protect, no support for DPO-FUA */ + if (LLBAA) + { + RWErrorRecovery[4] = 0x00; /* reserved and LONGLBA */ + RWErrorRecovery[4] = (bit8)(RWErrorRecovery[4] | 0x1); /* LONGLBA is set */ + } + else + { + RWErrorRecovery[4] = 0x00; /* reserved and LONGLBA: LONGLBA is not set */ + } + RWErrorRecovery[5] = 0x00; /* reserved */ + RWErrorRecovery[6] = 0x00; /* block descriptot length */ + if (LLBAA) + { + RWErrorRecovery[7] = 0x10; /* block descriptor length: LONGLBA is set. So, length is 16 */ + } + else + { + RWErrorRecovery[7] = 0x08; /* block descriptor length: LONGLBA is NOT set. So, length is 8 */ + } + + /* + * Fill-up direct-access device block-descriptor, SAT, Table 19 + */ + + if (LLBAA) + { + /* density code */ + RWErrorRecovery[8] = 0x04; /* density-code : reserved for direct-access */ + /* number of blocks */ + RWErrorRecovery[9] = 0x00; /* unspecified */ + RWErrorRecovery[10] = 0x00; /* unspecified */ + RWErrorRecovery[11] = 0x00; /* unspecified */ + RWErrorRecovery[12] = 0x00; /* unspecified */ + RWErrorRecovery[13] = 0x00; /* unspecified */ + RWErrorRecovery[14] = 0x00; /* unspecified */ + RWErrorRecovery[15] = 0x00; /* unspecified */ + /* reserved */ + RWErrorRecovery[16] = 0x00; /* reserved */ + RWErrorRecovery[17] = 0x00; /* reserved */ + RWErrorRecovery[18] = 0x00; /* reserved */ + RWErrorRecovery[19] = 0x00; /* reserved */ + /* Block size */ + RWErrorRecovery[20] = 0x00; + RWErrorRecovery[21] = 0x00; + RWErrorRecovery[22] = 0x02; /* Block size is always 512 bytes */ + RWErrorRecovery[23] = 0x00; + } + else + { + /* density code */ + RWErrorRecovery[8] = 0x04; /* density-code : reserved for direct-access */ + /* number of blocks */ + RWErrorRecovery[9] = 0x00; /* unspecified */ + RWErrorRecovery[10] = 0x00; /* unspecified */ + RWErrorRecovery[11] = 0x00; /* unspecified */ + /* reserved */ + RWErrorRecovery[12] = 0x00; /* reserved */ + /* Block size */ + RWErrorRecovery[13] = 0x00; + RWErrorRecovery[14] = 0x02; /* Block size is always 512 bytes */ + RWErrorRecovery[15] = 0x00; + } + + if (LLBAA) + { + index = 24; + } + else + { + index = 16; + } + /* + * Fill-up Read-Write Error Recovery mode page, SAT, Table 66 + */ + RWErrorRecovery[index+0] = 0x01; /* page code */ + RWErrorRecovery[index+1] = 0x0A; /* page length */ + RWErrorRecovery[index+2] = 0x40; /* ARRE is set */ + RWErrorRecovery[index+3] = 0x00; + RWErrorRecovery[index+4] = 0x00; + RWErrorRecovery[index+5] = 0x00; + RWErrorRecovery[index+6] = 0x00; + RWErrorRecovery[index+7] = 0x00; + RWErrorRecovery[index+8] = 0x00; + RWErrorRecovery[index+9] = 0x00; + RWErrorRecovery[index+10] = 0x00; + RWErrorRecovery[index+11] = 0x00; + + sm_memcpy(pModeSense, &RWErrorRecovery, lenRead); + } + else if (page == MODESENSE_CACHING) + { + SM_DBG5(("smsatModeSense10: MODESENSE_CACHING\n")); + Caching[0] = 0; + Caching[1] = (bit8)(lenRead - 2); + Caching[2] = 0x00; /* medium type: default medium type (currently mounted medium type) */ + Caching[3] = 0x00; /* device-specific param: no write-protect, no support for DPO-FUA */ + if (LLBAA) + { + Caching[4] = 0x00; /* reserved and LONGLBA */ + Caching[4] = (bit8)(Caching[4] | 0x1); /* LONGLBA is set */ + } + else + { + Caching[4] = 0x00; /* reserved and LONGLBA: LONGLBA is not set */ + } + Caching[5] = 0x00; /* reserved */ + Caching[6] = 0x00; /* block descriptot length */ + if (LLBAA) + { + Caching[7] = 0x10; /* block descriptor length: LONGLBA is set. So, length is 16 */ + } + else + { + Caching[7] = 0x08; /* block descriptor length: LONGLBA is NOT set. So, length is 8 */ + } + + /* + * Fill-up direct-access device block-descriptor, SAT, Table 19 + */ + + if (LLBAA) + { + /* density code */ + Caching[8] = 0x04; /* density-code : reserved for direct-access */ + /* number of blocks */ + Caching[9] = 0x00; /* unspecified */ + Caching[10] = 0x00; /* unspecified */ + Caching[11] = 0x00; /* unspecified */ + Caching[12] = 0x00; /* unspecified */ + Caching[13] = 0x00; /* unspecified */ + Caching[14] = 0x00; /* unspecified */ + Caching[15] = 0x00; /* unspecified */ + /* reserved */ + Caching[16] = 0x00; /* reserved */ + Caching[17] = 0x00; /* reserved */ + Caching[18] = 0x00; /* reserved */ + Caching[19] = 0x00; /* reserved */ + /* Block size */ + Caching[20] = 0x00; + Caching[21] = 0x00; + Caching[22] = 0x02; /* Block size is always 512 bytes */ + Caching[23] = 0x00; + } + else + { + /* density code */ + Caching[8] = 0x04; /* density-code : reserved for direct-access */ + /* number of blocks */ + Caching[9] = 0x00; /* unspecified */ + Caching[10] = 0x00; /* unspecified */ + Caching[11] = 0x00; /* unspecified */ + /* reserved */ + Caching[12] = 0x00; /* reserved */ + /* Block size */ + Caching[13] = 0x00; + Caching[14] = 0x02; /* Block size is always 512 bytes */ + Caching[15] = 0x00; + } + + if (LLBAA) + { + index = 24; + } + else + { + index = 16; + } + /* + * Fill-up Caching mode page, SAT, Table 67 + */ + /* length 20 */ + Caching[index+0] = 0x08; /* page code */ + Caching[index+1] = 0x12; /* page length */ + if (pSatDevData->satWriteCacheEnabled == agTRUE) + { + Caching[index+2] = 0x04;/* WCE bit is set */ + } + else + { + Caching[index+2] = 0x00;/* WCE bit is NOT set */ + } + + Caching[index+3] = 0x00; + Caching[index+4] = 0x00; + Caching[index+5] = 0x00; + Caching[index+6] = 0x00; + Caching[index+7] = 0x00; + Caching[index+8] = 0x00; + Caching[index+9] = 0x00; + Caching[index+10] = 0x00; + Caching[index+11] = 0x00; + if (pSatDevData->satLookAheadEnabled == agTRUE) + { + Caching[index+12] = 0x00;/* DRA bit is NOT set */ + } + else + { + Caching[index+12] = 0x20;/* DRA bit is set */ + } + Caching[index+13] = 0x00; + Caching[index+14] = 0x00; + Caching[index+15] = 0x00; + Caching[index+16] = 0x00; + Caching[index+17] = 0x00; + Caching[index+18] = 0x00; + Caching[index+19] = 0x00; + sm_memcpy(pModeSense, &Caching, lenRead); + + } + else if (page == MODESENSE_INFORMATION_EXCEPTION_CONTROL_PAGE) + { + SM_DBG5(("smsatModeSense10: MODESENSE_INFORMATION_EXCEPTION_CONTROL_PAGE\n")); + InfoExceptionCtrl[0] = 0; + InfoExceptionCtrl[1] = (bit8)(lenRead - 2); + InfoExceptionCtrl[2] = 0x00; /* medium type: default medium type (currently mounted medium type) */ + InfoExceptionCtrl[3] = 0x00; /* device-specific param: no write-protect, no support for DPO-FUA */ + if (LLBAA) + { + InfoExceptionCtrl[4] = 0x00; /* reserved and LONGLBA */ + InfoExceptionCtrl[4] = (bit8)(InfoExceptionCtrl[4] | 0x1); /* LONGLBA is set */ + } + else + { + InfoExceptionCtrl[4] = 0x00; /* reserved and LONGLBA: LONGLBA is not set */ + } + InfoExceptionCtrl[5] = 0x00; /* reserved */ + InfoExceptionCtrl[6] = 0x00; /* block descriptot length */ + if (LLBAA) + { + InfoExceptionCtrl[7] = 0x10; /* block descriptor length: LONGLBA is set. So, length is 16 */ + } + else + { + InfoExceptionCtrl[7] = 0x08; /* block descriptor length: LONGLBA is NOT set. So, length is 8 */ + } + + /* + * Fill-up direct-access device block-descriptor, SAT, Table 19 + */ + + if (LLBAA) + { + /* density code */ + InfoExceptionCtrl[8] = 0x04; /* density-code : reserved for direct-access */ + /* number of blocks */ + InfoExceptionCtrl[9] = 0x00; /* unspecified */ + InfoExceptionCtrl[10] = 0x00; /* unspecified */ + InfoExceptionCtrl[11] = 0x00; /* unspecified */ + InfoExceptionCtrl[12] = 0x00; /* unspecified */ + InfoExceptionCtrl[13] = 0x00; /* unspecified */ + InfoExceptionCtrl[14] = 0x00; /* unspecified */ + InfoExceptionCtrl[15] = 0x00; /* unspecified */ + /* reserved */ + InfoExceptionCtrl[16] = 0x00; /* reserved */ + InfoExceptionCtrl[17] = 0x00; /* reserved */ + InfoExceptionCtrl[18] = 0x00; /* reserved */ + InfoExceptionCtrl[19] = 0x00; /* reserved */ + /* Block size */ + InfoExceptionCtrl[20] = 0x00; + InfoExceptionCtrl[21] = 0x00; + InfoExceptionCtrl[22] = 0x02; /* Block size is always 512 bytes */ + InfoExceptionCtrl[23] = 0x00; + } + else + { + /* density code */ + InfoExceptionCtrl[8] = 0x04; /* density-code : reserved for direct-access */ + /* number of blocks */ + InfoExceptionCtrl[9] = 0x00; /* unspecified */ + InfoExceptionCtrl[10] = 0x00; /* unspecified */ + InfoExceptionCtrl[11] = 0x00; /* unspecified */ + /* reserved */ + InfoExceptionCtrl[12] = 0x00; /* reserved */ + /* Block size */ + InfoExceptionCtrl[13] = 0x00; + InfoExceptionCtrl[14] = 0x02; /* Block size is always 512 bytes */ + InfoExceptionCtrl[15] = 0x00; + } + + if (LLBAA) + { + index = 24; + } + else + { + index = 16; + } + /* + * Fill-up informational-exceptions control mode page, SAT, Table 68 + */ + InfoExceptionCtrl[index+0] = 0x1C; /* page code */ + InfoExceptionCtrl[index+1] = 0x0A; /* page length */ + if (pSatDevData->satSMARTEnabled == agTRUE) + { + InfoExceptionCtrl[index+2] = 0x00;/* DEXCPT bit is NOT set */ + } + else + { + InfoExceptionCtrl[index+2] = 0x08;/* DEXCPT bit is set */ + } + InfoExceptionCtrl[index+3] = 0x00; /* We don't support MRIE */ + InfoExceptionCtrl[index+4] = 0x00; /* Interval timer vendor-specific */ + InfoExceptionCtrl[index+5] = 0x00; + InfoExceptionCtrl[index+6] = 0x00; + InfoExceptionCtrl[index+7] = 0x00; + InfoExceptionCtrl[index+8] = 0x00; /* REPORT-COUNT */ + InfoExceptionCtrl[index+9] = 0x00; + InfoExceptionCtrl[index+10] = 0x00; + InfoExceptionCtrl[index+11] = 0x00; + sm_memcpy(pModeSense, &InfoExceptionCtrl, lenRead); + + } + else + { + /* Error */ + SM_DBG1(("smsatModeSense10: Error page %d!!!\n", page)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_COMMAND, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + + if (allocationLen > lenRead) + { + SM_DBG1(("smsatModeSense10: reporting underrun lenRead=0x%x allocationLen=0x%x smIORequest=%p\n", lenRead, allocationLen, smIORequest)); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOUnderRun, + allocationLen - lenRead, + agNULL, + satIOContext->interruptContext ); + + + } + else + { + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + } + + return SM_RC_SUCCESS; +} + +osGLOBAL bit32 +smsatReadCapacity10( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + bit8 dataBuffer[8] = {0}; + bit32 allocationLen; + bit8 *pVirtAddr = agNULL; + smDeviceData_t *pSatDevData; + agsaSATAIdentifyData_t *pSATAIdData; + bit32 lastLba; + bit32 word117_118; + bit32 word117; + bit32 word118; + + pSense = satIOContext->pSense; + pVirtAddr = (bit8 *) smScsiRequest->sglVirtualAddr; + scsiCmnd = &smScsiRequest->scsiCmnd; + pSatDevData = satIOContext->pSatDevData; + pSATAIdData = &pSatDevData->satIdentifyData; + allocationLen = scsiCmnd->expDataLength; + + SM_DBG5(("smsatReadCapacity10: start\n")); + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[9] & SCSI_NACA_MASK) || (scsiCmnd->cdb[9] & SCSI_LINK_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatReadCapacity10: return control!!!\n")); + return SM_RC_SUCCESS; + } + + + /* + * If Logical block address is not set to zero, return error + */ + if ((scsiCmnd->cdb[2] || scsiCmnd->cdb[3] || scsiCmnd->cdb[4] || scsiCmnd->cdb[5])) + { + SM_DBG1(("smsatReadCapacity10: *** ERROR *** logical address non zero, did %d!!!\n", + pSatDevData->id)); + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + + } + + /* + * If PMI bit is not zero, return error + */ + if ( ((scsiCmnd->cdb[8]) & SCSI_READ_CAPACITY10_PMI_MASK) != 0 ) + { + SM_DBG1(("smsatReadCapacity10: *** ERROR *** PMI is not zero, did %d\n", + pSatDevData->id)); + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + + } + + /* + filling in Read Capacity parameter data + saved identify device has been already flipped + See ATA spec p125 and p136 and SBC spec p54 + */ + /* + * If 48-bit addressing is supported, set capacity information from Identify + * Device Word 100-103. + */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + /* + * Setting RETURNED LOGICAL BLOCK ADDRESS in READ CAPACITY(10) response data: + * SBC-2 specifies that if the capacity exceeded the 4-byte RETURNED LOGICAL + * BLOCK ADDRESS in READ CAPACITY(10) parameter data, the the RETURNED LOGICAL + * BLOCK ADDRESS should be set to 0xFFFFFFFF so the application client would + * then issue a READ CAPACITY(16) command. + */ + /* ATA Identify Device information word 100 - 103 */ + if ( (pSATAIdData->maxLBA32_47 != 0 ) || (pSATAIdData->maxLBA48_63 != 0)) + { + dataBuffer[0] = 0xFF; /* MSB number of block */ + dataBuffer[1] = 0xFF; + dataBuffer[2] = 0xFF; + dataBuffer[3] = 0xFF; /* LSB number of block */ + SM_DBG1(("smsatReadCapacity10: returns 0xFFFFFFFF!!!\n")); + } + else /* Fit the Readcapacity10 4-bytes response length */ + { + lastLba = (((pSATAIdData->maxLBA16_31) << 16) ) | + (pSATAIdData->maxLBA0_15); + lastLba = lastLba - 1; /* LBA starts from zero */ + + /* + for testing + lastLba = lastLba - (512*10) - 1; + */ + + + dataBuffer[0] = (bit8)((lastLba >> 24) & 0xFF); /* MSB */ + dataBuffer[1] = (bit8)((lastLba >> 16) & 0xFF); + dataBuffer[2] = (bit8)((lastLba >> 8) & 0xFF); + dataBuffer[3] = (bit8)((lastLba ) & 0xFF); /* LSB */ + + SM_DBG3(("smsatReadCapacity10: lastLba is 0x%x %d\n", lastLba, lastLba)); + SM_DBG3(("smsatReadCapacity10: LBA 0 is 0x%x %d\n", dataBuffer[0], dataBuffer[0])); + SM_DBG3(("smsatReadCapacity10: LBA 1 is 0x%x %d\n", dataBuffer[1], dataBuffer[1])); + SM_DBG3(("smsatReadCapacity10: LBA 2 is 0x%x %d\n", dataBuffer[2], dataBuffer[2])); + SM_DBG3(("smsatReadCapacity10: LBA 3 is 0x%x %d\n", dataBuffer[3], dataBuffer[3])); + + } + } + + /* + * For 28-bit addressing, set capacity information from Identify + * Device Word 60-61. + */ + else + { + /* ATA Identify Device information word 60 - 61 */ + lastLba = (((pSATAIdData->numOfUserAddressableSectorsHi) << 16) ) | + (pSATAIdData->numOfUserAddressableSectorsLo); + lastLba = lastLba - 1; /* LBA starts from zero */ + + dataBuffer[0] = (bit8)((lastLba >> 24) & 0xFF); /* MSB */ + dataBuffer[1] = (bit8)((lastLba >> 16) & 0xFF); + dataBuffer[2] = (bit8)((lastLba >> 8) & 0xFF); + dataBuffer[3] = (bit8)((lastLba ) & 0xFF); /* LSB */ + } + /* SAT Rev 8d */ + if (((pSATAIdData->word104_107[2]) & 0x1000) == 0) + { + SM_DBG5(("smsatReadCapacity10: Default Block Length is 512\n")); + /* + * Set the block size, fixed at 512 bytes. + */ + dataBuffer[4] = 0x00; /* MSB block size in bytes */ + dataBuffer[5] = 0x00; + dataBuffer[6] = 0x02; + dataBuffer[7] = 0x00; /* LSB block size in bytes */ + } + else + { + word118 = pSATAIdData->word112_126[6]; + word117 = pSATAIdData->word112_126[5]; + + word117_118 = (word118 << 16) + word117; + word117_118 = word117_118 * 2; + dataBuffer[4] = (bit8)((word117_118 >> 24) & 0xFF); /* MSB block size in bytes */ + dataBuffer[5] = (bit8)((word117_118 >> 16) & 0xFF); + dataBuffer[6] = (bit8)((word117_118 >> 8) & 0xFF); + dataBuffer[7] = (bit8)(word117_118 & 0xFF); /* LSB block size in bytes */ + + SM_DBG1(("smsatReadCapacity10: Nondefault word118 %d 0x%x !!!\n", word118, word118)); + SM_DBG1(("smsatReadCapacity10: Nondefault word117 %d 0x%x !!!\n", word117, word117)); + SM_DBG1(("smsatReadCapacity10: Nondefault Block Length is %d 0x%x !!!\n",word117_118, word117_118)); + + } + + /* fill in MAX LBA, which is used in satSendDiagnostic_1() */ + pSatDevData->satMaxLBA[0] = 0; /* MSB */ + pSatDevData->satMaxLBA[1] = 0; + pSatDevData->satMaxLBA[2] = 0; + pSatDevData->satMaxLBA[3] = 0; + pSatDevData->satMaxLBA[4] = dataBuffer[0]; + pSatDevData->satMaxLBA[5] = dataBuffer[1]; + pSatDevData->satMaxLBA[6] = dataBuffer[2]; + pSatDevData->satMaxLBA[7] = dataBuffer[3]; /* LSB */ + + + SM_DBG4(("smsatReadCapacity10: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x , did %d\n", + dataBuffer[0], dataBuffer[1], dataBuffer[2], dataBuffer[3], + dataBuffer[4], dataBuffer[5], dataBuffer[6], dataBuffer[7], + pSatDevData->id)); + + sm_memcpy(pVirtAddr, dataBuffer, MIN(allocationLen, 8)); + + /* + * Send the completion response now. + */ + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + return SM_RC_SUCCESS; +} + +osGLOBAL bit32 +smsatReadCapacity16( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + bit8 dataBuffer[32] = {0}; + bit8 *pVirtAddr = agNULL; + smDeviceData_t *pSatDevData; + agsaSATAIdentifyData_t *pSATAIdData; + bit32 lastLbaLo; + bit32 allocationLen; + bit32 readCapacityLen = 32; + bit32 i = 0; + + pSense = satIOContext->pSense; + pVirtAddr = (bit8 *) smScsiRequest->sglVirtualAddr; + scsiCmnd = &smScsiRequest->scsiCmnd; + pSatDevData = satIOContext->pSatDevData; + pSATAIdData = &pSatDevData->satIdentifyData; + + SM_DBG5(("smsatReadCapacity16: start\n")); + + /* Find the buffer size allocated by Initiator */ + allocationLen = (((bit32)scsiCmnd->cdb[10]) << 24) | + (((bit32)scsiCmnd->cdb[11]) << 16) | + (((bit32)scsiCmnd->cdb[12]) << 8 ) | + (((bit32)scsiCmnd->cdb[13]) ); + allocationLen = MIN(allocationLen, scsiCmnd->expDataLength); + +#ifdef REMOVED + if (allocationLen < readCapacityLen) + { + SM_DBG1(("smsatReadCapacity16: *** ERROR *** insufficient len=0x%x readCapacityLen=0x%x!!!\n", allocationLen, readCapacityLen)); + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + + } +#endif + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[15] & SCSI_NACA_MASK) || (scsiCmnd->cdb[15] & SCSI_LINK_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatReadCapacity16: return control!!!\n")); + return SM_RC_SUCCESS; + } + + /* + * If Logical blcok address is not set to zero, return error + */ + if ((scsiCmnd->cdb[2] || scsiCmnd->cdb[3] || scsiCmnd->cdb[4] || scsiCmnd->cdb[5]) || + (scsiCmnd->cdb[6] || scsiCmnd->cdb[7] || scsiCmnd->cdb[8] || scsiCmnd->cdb[9]) ) + { + SM_DBG1(("smsatReadCapacity16: *** ERROR *** logical address non zero, did %d\n", + pSatDevData->id)); + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + + } + + /* + * If PMI bit is not zero, return error + */ + if ( ((scsiCmnd->cdb[14]) & SCSI_READ_CAPACITY16_PMI_MASK) != 0 ) + { + SM_DBG1(("smsatReadCapacity16: *** ERROR *** PMI is not zero, did %d\n", + pSatDevData->id)); + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + + } + + /* + filling in Read Capacity parameter data + */ + + /* + * If 48-bit addressing is supported, set capacity information from Identify + * Device Word 100-103. + */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + dataBuffer[0] = (bit8)(((pSATAIdData->maxLBA48_63) >> 8) & 0xff); /* MSB */ + dataBuffer[1] = (bit8)((pSATAIdData->maxLBA48_63) & 0xff); + dataBuffer[2] = (bit8)(((pSATAIdData->maxLBA32_47) >> 8) & 0xff); + dataBuffer[3] = (bit8)((pSATAIdData->maxLBA32_47) & 0xff); + + lastLbaLo = (((pSATAIdData->maxLBA16_31) << 16) ) | (pSATAIdData->maxLBA0_15); + lastLbaLo = lastLbaLo - 1; /* LBA starts from zero */ + + dataBuffer[4] = (bit8)((lastLbaLo >> 24) & 0xFF); + dataBuffer[5] = (bit8)((lastLbaLo >> 16) & 0xFF); + dataBuffer[6] = (bit8)((lastLbaLo >> 8) & 0xFF); + dataBuffer[7] = (bit8)((lastLbaLo ) & 0xFF); /* LSB */ + + } + + /* + * For 28-bit addressing, set capacity information from Identify + * Device Word 60-61. + */ + else + { + dataBuffer[0] = 0; /* MSB */ + dataBuffer[1] = 0; + dataBuffer[2] = 0; + dataBuffer[3] = 0; + + lastLbaLo = (((pSATAIdData->numOfUserAddressableSectorsHi) << 16) ) | + (pSATAIdData->numOfUserAddressableSectorsLo); + lastLbaLo = lastLbaLo - 1; /* LBA starts from zero */ + + dataBuffer[4] = (bit8)((lastLbaLo >> 24) & 0xFF); + dataBuffer[5] = (bit8)((lastLbaLo >> 16) & 0xFF); + dataBuffer[6] = (bit8)((lastLbaLo >> 8) & 0xFF); + dataBuffer[7] = (bit8)((lastLbaLo ) & 0xFF); /* LSB */ + + } + + /* + * Set the block size, fixed at 512 bytes. + */ + dataBuffer[8] = 0x00; /* MSB block size in bytes */ + dataBuffer[9] = 0x00; + dataBuffer[10] = 0x02; + dataBuffer[11] = 0x00; /* LSB block size in bytes */ + + + /* fill in MAX LBA, which is used in satSendDiagnostic_1() */ + pSatDevData->satMaxLBA[0] = dataBuffer[0]; /* MSB */ + pSatDevData->satMaxLBA[1] = dataBuffer[1]; + pSatDevData->satMaxLBA[2] = dataBuffer[2]; + pSatDevData->satMaxLBA[3] = dataBuffer[3]; + pSatDevData->satMaxLBA[4] = dataBuffer[4]; + pSatDevData->satMaxLBA[5] = dataBuffer[5]; + pSatDevData->satMaxLBA[6] = dataBuffer[6]; + pSatDevData->satMaxLBA[7] = dataBuffer[7]; /* LSB */ + + SM_DBG5(("smsatReadCapacity16: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x , did %d\n", + dataBuffer[0], dataBuffer[1], dataBuffer[2], dataBuffer[3], + dataBuffer[4], dataBuffer[5], dataBuffer[6], dataBuffer[7], + dataBuffer[8], dataBuffer[9], dataBuffer[10], dataBuffer[11], + pSatDevData->id)); + + if (allocationLen > 0xC) /* 0xc = 12 */ + { + for(i=12;i<=31;i++) + { + dataBuffer[i] = 0x00; + } + } + + sm_memcpy(pVirtAddr, dataBuffer, MIN(allocationLen, readCapacityLen)); + /* + * Send the completion response now. + */ + if (allocationLen > readCapacityLen) + { + /* underrun */ + SM_DBG1(("smsatReadCapacity16: reporting underrun readCapacityLen=0x%x allocationLen=0x%x !!!\n", readCapacityLen, allocationLen)); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOUnderRun, + allocationLen - readCapacityLen, + agNULL, + satIOContext->interruptContext ); + + + } + else + { + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + } + return SM_RC_SUCCESS; +} + +osGLOBAL bit32 +smsatReportLun( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + smScsiRspSense_t *pSense; + bit8 dataBuffer[16] = {0}; + bit32 allocationLen; + bit32 reportLunLen; + smScsiReportLun_t *pReportLun; + smIniScsiCmnd_t *scsiCmnd; +#ifdef TD_DEBUG_ENABLE + smDeviceData_t *pSatDevData; +#endif + + pSense = satIOContext->pSense; + pReportLun = (smScsiReportLun_t *) dataBuffer; + scsiCmnd = &smScsiRequest->scsiCmnd; +#ifdef TD_DEBUG_ENABLE + pSatDevData = satIOContext->pSatDevData; +#endif + SM_DBG5(("smsatReportLun: start\n")); +// smhexdump("smsatReportLun: cdb", (bit8 *)scsiCmnd, 16); + /* Find the buffer size allocated by Initiator */ + allocationLen = (((bit32)scsiCmnd->cdb[6]) << 24) | + (((bit32)scsiCmnd->cdb[7]) << 16) | + (((bit32)scsiCmnd->cdb[8]) << 8 ) | + (((bit32)scsiCmnd->cdb[9]) ); + allocationLen = MIN(allocationLen, scsiCmnd->expDataLength); + reportLunLen = 16; /* 8 byte header and 8 bytes of LUN0 */ + if (allocationLen < reportLunLen) + { + SM_DBG1(("smsatReportLun: *** ERROR *** insufficient len=0x%x did %d\n", + reportLunLen, pSatDevData->id)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + /*smEnqueueIO(smRoot, satIOContext);*/ + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + /* Set length to one entry */ + pReportLun->len[0] = 0; + pReportLun->len[1] = 0; + pReportLun->len[2] = 0; + pReportLun->len[3] = sizeof (tiLUN_t); + pReportLun->reserved = 0; + /* Set to LUN 0: + * - address method to 0x00: Peripheral device addressing method, + * - bus identifier to 0 + */ + pReportLun->lunList[0].lun[0] = 0; + pReportLun->lunList[0].lun[1] = 0; + pReportLun->lunList[0].lun[2] = 0; + pReportLun->lunList[0].lun[3] = 0; + pReportLun->lunList[0].lun[4] = 0; + pReportLun->lunList[0].lun[5] = 0; + pReportLun->lunList[0].lun[6] = 0; + pReportLun->lunList[0].lun[7] = 0; + + sm_memcpy(smScsiRequest->sglVirtualAddr, dataBuffer, MIN(allocationLen, reportLunLen)); + if (allocationLen > reportLunLen) + { + /* underrun */ + SM_DBG1(("smsatReportLun: reporting underrun reportLunLen=0x%x allocationLen=0x%x !!!\n", reportLunLen, allocationLen)); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOUnderRun, + allocationLen - reportLunLen, + agNULL, + satIOContext->interruptContext ); + + + } + else + { + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + } + return SM_RC_SUCCESS; +} + +osGLOBAL bit32 +smsatFormatUnit( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + /* + note: we don't support media certification in this version and IP bit + satDevData->satFormatState will be agFalse since SAT does not actually sends + any ATA command + */ + + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + bit32 index = 0; + + pSense = satIOContext->pSense; + scsiCmnd = &smScsiRequest->scsiCmnd; + SM_DBG5(("smsatFormatUnit: start\n")); + /* + checking opcode + 1. FMTDATA bit == 0(no defect list header) + 2. FMTDATA bit == 1 and DCRT bit == 1(defect list header is provided + with DCRT bit set) + */ + if ( ((scsiCmnd->cdb[1] & SCSI_FORMAT_UNIT_FMTDATA_MASK) == 0) || + ((scsiCmnd->cdb[1] & SCSI_FORMAT_UNIT_FMTDATA_MASK) && + (scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_DCRT_MASK)) + ) + { + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + + SM_DBG1(("smsatFormatUnit: return opcode!!!\n")); + return SM_RC_SUCCESS; + } + + /* + checking DEFECT LIST FORMAT and defect list length + */ + if ( (((scsiCmnd->cdb[1] & SCSI_FORMAT_UNIT_DEFECT_LIST_FORMAT_MASK) == 0x00) || + ((scsiCmnd->cdb[1] & SCSI_FORMAT_UNIT_DEFECT_LIST_FORMAT_MASK) == 0x06)) ) + { + /* short parameter header */ + if ((scsiCmnd->cdb[2] & SCSI_FORMAT_UNIT_LONGLIST_MASK) == 0x00) + { + index = 8; + } + /* long parameter header */ + if ((scsiCmnd->cdb[2] & SCSI_FORMAT_UNIT_LONGLIST_MASK) == 0x01) + { + index = 10; + } + /* defect list length */ + if ((scsiCmnd->cdb[index] != 0) || (scsiCmnd->cdb[index+1] != 0)) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatFormatUnit: return defect list format!!!\n")); + return SM_RC_SUCCESS; + } + } + + if ( (scsiCmnd->cdb[1] & SCSI_FORMAT_UNIT_FMTDATA_MASK) && + (scsiCmnd->cdb[1] & SCSI_FORMAT_UNIT_CMPLIST_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatFormatUnit: return cmplist!!!\n")); + return SM_RC_SUCCESS; + + } + + if ( (scsiCmnd->cdb[5] & SCSI_NACA_MASK) || (scsiCmnd->cdb[5] & SCSI_LINK_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatFormatUnit: return control!!!\n")); + return SM_RC_SUCCESS; + } + + /* defect list header filed, if exists, SAT rev8, Table 37, p48 */ + if (scsiCmnd->cdb[1] & SCSI_FORMAT_UNIT_FMTDATA_MASK) + { + /* case 1,2,3 */ + /* IMMED 1; FOV 0; FOV 1, DCRT 1, IP 0 */ + if ( (scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_IMMED_MASK) || + ( !(scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_FOV_MASK)) || + ( (scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_FOV_MASK) && + (scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_DCRT_MASK) && + !(scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_IP_MASK)) + ) + { + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + + SM_DBG5(("smsatFormatUnit: return defect list case 1\n")); + return SM_RC_SUCCESS; + } + /* case 4,5,6 */ + /* + 1. IMMED 0, FOV 1, DCRT 0, IP 0 + 2. IMMED 0, FOV 1, DCRT 0, IP 1 + 3. IMMED 0, FOV 1, DCRT 1, IP 1 + */ + + if ( ( !(scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_IMMED_MASK) && + (scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_FOV_MASK) && + !(scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_DCRT_MASK) && + !(scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_IP_MASK) ) + || + ( !(scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_IMMED_MASK) && + (scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_FOV_MASK) && + !(scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_DCRT_MASK) && + (scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_IP_MASK) ) + || + ( !(scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_IMMED_MASK) && + (scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_FOV_MASK) && + (scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_DCRT_MASK) && + (scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_IP_MASK) ) + ) + { + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_PARAMETER_LIST, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG5(("smsatFormatUnit: return defect list case 2\n")); + return SM_RC_SUCCESS; + + } + } + + + /* + * Send the completion response now. + */ + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + + SM_DBG5(("smsatFormatUnit: return last\n")); + return SM_RC_SUCCESS; +} + +osGLOBAL bit32 +smsatSendDiagnostic( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status; + bit32 agRequestType; + smDeviceData_t *pSatDevData; + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 parmLen; + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &smScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + SM_DBG5(("smsatSendDiagnostic: start\n")); + + /* reset satVerifyState */ + pSatDevData->satVerifyState = 0; + /* no pending diagnostic in background */ + pSatDevData->satBGPendingDiag = agFALSE; + + /* table 27, 8.10 p39 SAT Rev8 */ + /* + 1. checking PF == 1 + 2. checking DEVOFFL == 1 + 3. checking UNITOFFL == 1 + 4. checking PARAMETER LIST LENGTH != 0 + + */ + if ( (scsiCmnd->cdb[1] & SCSI_PF_MASK) || + (scsiCmnd->cdb[1] & SCSI_DEVOFFL_MASK) || + (scsiCmnd->cdb[1] & SCSI_UNITOFFL_MASK) || + ( (scsiCmnd->cdb[3] != 0) || (scsiCmnd->cdb[4] != 0) ) + ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatSendDiagnostic: return PF, DEVOFFL, UNITOFFL, PARAM LIST!!!\n")); + return SM_RC_SUCCESS; + } + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[5] & SCSI_NACA_MASK) || (scsiCmnd->cdb[5] & SCSI_LINK_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatSendDiagnostic: return control!!!\n")); + return SM_RC_SUCCESS; + } + + parmLen = (scsiCmnd->cdb[3] << 8) + scsiCmnd->cdb[4]; + + /* checking SELFTEST bit*/ + /* table 29, 8.10.3, p41 SAT Rev8 */ + /* case 1 */ + if ( !(scsiCmnd->cdb[1] & SCSI_SEND_DIAGNOSTIC_SELFTEST_MASK) && + (pSatDevData->satSMARTSelfTest == agFALSE) + ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatSendDiagnostic: return Table 29 case 1!!!\n")); + return SM_RC_SUCCESS; + } + + /* case 2 */ + if ( !(scsiCmnd->cdb[1] & SCSI_SEND_DIAGNOSTIC_SELFTEST_MASK) && + (pSatDevData->satSMARTSelfTest == agTRUE) && + (pSatDevData->satSMARTEnabled == agFALSE) + ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_ATA_DEVICE_FEATURE_NOT_ENABLED, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG5(("smsatSendDiagnostic: return Table 29 case 2\n")); + return SM_RC_SUCCESS; + } + /* + case 3 + see SELF TEST CODE later + */ + + + + /* case 4 */ + + /* + sends three ATA verify commands + + */ + if ( ((scsiCmnd->cdb[1] & SCSI_SEND_DIAGNOSTIC_SELFTEST_MASK) && + (pSatDevData->satSMARTSelfTest == agFALSE)) + || + ((scsiCmnd->cdb[1] & SCSI_SEND_DIAGNOSTIC_SELFTEST_MASK) && + (pSatDevData->satSMARTSelfTest == agTRUE) && + (pSatDevData->satSMARTEnabled == agFALSE)) + ) + { + /* + sector count 1, LBA 0 + sector count 1, LBA MAX + sector count 1, LBA random + */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + /* sends READ VERIFY SECTOR(S) EXT*/ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS_EXT;/* 0x42 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.device = 0x40; /* 01000000 */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + } + else + { + /* READ VERIFY SECTOR(S)*/ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS;/* 0x40 */ + fis->h.features = 0; /* FIS features NA */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.device = 0x40; /* 01000000 */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + } + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatSendDiagnosticCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + + SM_DBG5(("smsatSendDiagnostic: return Table 29 case 4\n")); + return (status); + } + /* case 5 */ + if ( (scsiCmnd->cdb[1] & SCSI_SEND_DIAGNOSTIC_SELFTEST_MASK) && + (pSatDevData->satSMARTSelfTest == agTRUE) && + (pSatDevData->satSMARTEnabled == agTRUE) + ) + { + /* sends SMART EXECUTE OFF-LINE IMMEDIATE */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_SMART; /* 0xB0 */ + fis->h.features = SAT_SMART_EXEUTE_OFF_LINE_IMMEDIATE; /* FIS features NA */ + fis->d.lbaLow = 0x81; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0x4F; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0xC2; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.device = 0; /* FIS DEV is discared in SATA */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatSendDiagnosticCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + + SM_DBG5(("smsatSendDiagnostic: return Table 29 case 5\n")); + return (status); + } + + + + + /* SAT rev8 Table29 p41 case 3*/ + /* checking SELF TEST CODE*/ + if ( !(scsiCmnd->cdb[1] & SCSI_SEND_DIAGNOSTIC_SELFTEST_MASK) && + (pSatDevData->satSMARTSelfTest == agTRUE) && + (pSatDevData->satSMARTEnabled == agTRUE) + ) + { + /* SAT rev8 Table28 p40 */ + /* finding self-test code */ + switch ((scsiCmnd->cdb[1] & SCSI_SEND_DIAGNOSTIC_TEST_CODE_MASK) >> 5) + { + case 1: + pSatDevData->satBGPendingDiag = agTRUE; + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext ); + /* sends SMART EXECUTE OFF-LINE IMMEDIATE */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_SMART; /* 0x40 */ + fis->h.features = SAT_SMART_EXEUTE_OFF_LINE_IMMEDIATE; /* FIS features NA */ + fis->d.lbaLow = 0x01; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0x4F; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0xC2; /* FIS LBA (23:16) */ + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.device = 0; /* FIS DEV is discared in SATA */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatSendDiagnosticCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + + SM_DBG5(("smsatSendDiagnostic: return Table 28 case 1\n")); + return (status); + case 2: + pSatDevData->satBGPendingDiag = agTRUE; + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext ); + + + /* issuing SMART EXECUTE OFF-LINE IMMEDIATE */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_SMART; /* 0x40 */ + fis->h.features = SAT_SMART_EXEUTE_OFF_LINE_IMMEDIATE; /* FIS features NA */ + fis->d.lbaLow = 0x02; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0x4F; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0xC2; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.device = 0; /* FIS DEV is discared in SATA */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatSendDiagnosticCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + + SM_DBG5(("smsatSendDiagnostic: return Table 28 case 2\n")); + return (status); + case 4: + + if (parmLen != 0) + { + /* check condition */ + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatSendDiagnostic: case 4, non zero ParmLen %d!!!\n", parmLen)); + return SM_RC_SUCCESS; + } + if (pSatDevData->satBGPendingDiag == agTRUE) + { + /* sends SMART EXECUTE OFF-LINE IMMEDIATE abort */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_SMART; /* 0x40 */ + fis->h.features = SAT_SMART_EXEUTE_OFF_LINE_IMMEDIATE; /* FIS features NA */ + fis->d.lbaLow = 0x7F; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0x4F; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0xC2; /* FIS LBA (23:16) */ + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.device = 0; /* FIS DEV is discared in SATA */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatSendDiagnosticCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + + SM_DBG5(("smsatSendDiagnostic: send SAT_SMART_EXEUTE_OFF_LINE_IMMEDIATE case 3\n")); + SM_DBG5(("smsatSendDiagnostic: Table 28 case 4\n")); + return (status); + } + else + { + /* check condition */ + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatSendDiagnostic: case 4, no pending diagnostic in background!!!\n")); + SM_DBG5(("smsatSendDiagnostic: Table 28 case 4\n")); + return SM_RC_SUCCESS; + } + break; + case 5: + /* issuing SMART EXECUTE OFF-LINE IMMEDIATE */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_SMART; /* 0x40 */ + fis->h.features = SAT_SMART_EXEUTE_OFF_LINE_IMMEDIATE; /* FIS features NA */ + fis->d.lbaLow = 0x81; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0x4F; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0xC2; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.device = 0; /* FIS DEV is discared in SATA */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatSendDiagnosticCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + + SM_DBG5(("smsatSendDiagnostic: return Table 28 case 5\n")); + return (status); + case 6: + /* issuing SMART EXECUTE OFF-LINE IMMEDIATE */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_SMART; /* 0x40 */ + fis->h.features = SAT_SMART_EXEUTE_OFF_LINE_IMMEDIATE; /* FIS features NA */ + fis->d.lbaLow = 0x82; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0x4F; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0xC2; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.device = 0; /* FIS DEV is discared in SATA */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatSendDiagnosticCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + + SM_DBG5(("smsatSendDiagnostic: return Table 28 case 6\n")); + return (status); + case 0: + case 3: /* fall through */ + case 7: /* fall through */ + default: + break; + }/* switch */ + + /* returns the results of default self-testing, which is good */ + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext ); + + SM_DBG5(("smsatSendDiagnostic: return Table 28 case 0,3,7 and default\n")); + return SM_RC_SUCCESS; + } + + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext ); + + + SM_DBG5(("smsatSendDiagnostic: return last\n")); + return SM_RC_SUCCESS; + +} + +osGLOBAL bit32 +smsatStartStopUnit( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status; + bit32 agRequestType; + smDeviceData_t *pSatDevData; + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &smScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + SM_DBG5(("smsatStartStopUnit: start\n")); + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[5] & SCSI_NACA_MASK) || (scsiCmnd->cdb[5] & SCSI_LINK_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatStartStopUnit: return control!!!\n")); + return SM_RC_SUCCESS; + } + + /* Spec p55, Table 48 checking START and LOEJ bit */ + /* case 1 */ + if ( !(scsiCmnd->cdb[4] & SCSI_START_MASK) && !(scsiCmnd->cdb[4] & SCSI_LOEJ_MASK) ) + { + if ( (scsiCmnd->cdb[1] & SCSI_IMMED_MASK) ) + { + /* immed bit , SAT rev 8, 9.11.2.1 p 54*/ + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext ); + SM_DBG5(("smsatStartStopUnit: return table48 case 1-1\n")); + return SM_RC_SUCCESS; + } + /* sends FLUSH CACHE or FLUSH CACHE EXT */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + /* FLUSH CACHE EXT */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_FLUSH_CACHE_EXT; /* 0xEA */ + fis->h.features = 0; /* FIS reserve */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaLowExp = 0; /* FIS LBA (31:24) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.device = 0; /* FIS DEV is discared in SATA */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved4 = 0; + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + } + else + { + /* FLUSH CACHE */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_FLUSH_CACHE; /* 0xE7 */ + fis->h.features = 0; /* FIS features NA */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.device = 0; /* FIS DEV is discared in SATA */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved4 = 0; + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + } + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatStartStopUnitCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + + SM_DBG5(("smsatStartStopUnit: return table48 case 1\n")); + return (status); + } + /* case 2 */ + else if ( (scsiCmnd->cdb[4] & SCSI_START_MASK) && !(scsiCmnd->cdb[4] & SCSI_LOEJ_MASK) ) + { + /* immed bit , SAT rev 8, 9.11.2.1 p 54*/ + if ( (scsiCmnd->cdb[1] & SCSI_IMMED_MASK) ) + { + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext ); + + SM_DBG5(("smsatStartStopUnit: return table48 case 2 1\n")); + return SM_RC_SUCCESS; + } + /* + sends READ_VERIFY_SECTORS(_EXT) + sector count 1, any LBA between zero to Maximum + */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + /* READ VERIFY SECTOR(S) EXT*/ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_READ_VERIFY_SECTORS_EXT;/* 0x42 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = 0x01; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0x00; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0x00; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0x00; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0x00; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0x00; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.device = 0x40; /* 01000000 */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + } + else + { + /* READ VERIFY SECTOR(S)*/ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_READ_VERIFY_SECTORS;/* 0x40 */ + fis->h.features = 0; /* FIS features NA */ + fis->d.lbaLow = 0x01; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0x00; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0x00; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.device = 0x40; /* 01000000 */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + } + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatStartStopUnitCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + SM_DBG5(("smsatStartStopUnit: return table48 case 2 2\n")); + return status; + } + /* case 3 */ + else if ( !(scsiCmnd->cdb[4] & SCSI_START_MASK) && (scsiCmnd->cdb[4] & SCSI_LOEJ_MASK) ) + { + if(pSatDevData->satRemovableMedia && pSatDevData->satRemovableMediaEnabled) + { + /* support for removal media */ + /* immed bit , SAT rev 8, 9.11.2.1 p 54*/ + if ( (scsiCmnd->cdb[1] & SCSI_IMMED_MASK) ) + { + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext ); + + SM_DBG5(("smsatStartStopUnit: return table48 case 3 1\n")); + return SM_RC_SUCCESS; + } + /* + sends MEDIA EJECT + */ + /* Media Eject fis */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_MEDIA_EJECT; /* 0xED */ + fis->h.features = 0; /* FIS features NA */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + /* sector count zero */ + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.device = 0; /* FIS DEV is discared in SATA */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved4 = 0; + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatStartStopUnitCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + return status; + } + else + { + /* no support for removal media */ + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG5(("smsatStartStopUnit: return Table 29 case 3 2\n")); + return SM_RC_SUCCESS; + } + + } + /* case 4 */ + else /* ( (scsiCmnd->cdb[4] & SCSI_START_MASK) && (scsiCmnd->cdb[4] & SCSI_LOEJ_MASK) ) */ + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG5(("smsatStartStopUnit: return Table 29 case 4\n")); + return SM_RC_SUCCESS; + } +} + +osGLOBAL bit32 +smsatWriteSame10( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + smDeviceData_t *pSatDevData; + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 lba = 0; + bit32 tl = 0; + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &smScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + SM_DBG5(("smsatWriteSame10: start\n")); + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[9] & SCSI_NACA_MASK) || (scsiCmnd->cdb[9] & SCSI_LINK_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatWriteSame10: return control!!!\n")); + return SM_RC_SUCCESS; + } + + + /* checking LBDATA and PBDATA */ + /* case 1 */ + if ( !(scsiCmnd->cdb[1] & SCSI_WRITE_SAME_LBDATA_MASK) && + !(scsiCmnd->cdb[1] & SCSI_WRITE_SAME_PBDATA_MASK)) + { + SM_DBG5(("smsatWriteSame10: case 1\n")); + /* spec 9.26.2, Table 62, p64, case 1*/ + /* + normal case + just like write in 9.17.1 + */ + + if ( pSatDevData->sat48BitSupport != agTRUE ) + { + /* + writeSame10 but no support for 48 bit addressing + -> problem in transfer length. Therefore, return check condition + */ + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatWriteSame10: return internal checking!!!\n")); + return SM_RC_SUCCESS; + } + + /* cdb10; computing LBA and transfer length */ + lba = (scsiCmnd->cdb[2] << (8*3)) + (scsiCmnd->cdb[3] << (8*2)) + + (scsiCmnd->cdb[4] << 8) + scsiCmnd->cdb[5]; + tl = (scsiCmnd->cdb[7] << 8) + scsiCmnd->cdb[8]; + + + /* Table 34, 9.1, p 46 */ + /* + note: As of 2/10/2006, no support for DMA QUEUED + */ + + /* + Table 34, 9.1, p 46, b (footnote) + When no 48-bit addressing support or NCQ, if LBA is beyond (2^28 - 1), + return check condition + */ + if (pSatDevData->satNCQ != agTRUE && + pSatDevData->sat48BitSupport != agTRUE + ) + { + if (lba > SAT_TR_LBA_LIMIT - 1) /* SAT_TR_LBA_LIMIT is 2^28, 0x10000000 */ + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatWriteSame10: return LBA out of range!!!\n")); + return SM_RC_SUCCESS; + } + } + + + if (lba + tl <= SAT_TR_LBA_LIMIT) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 2 */ + /* WRITE DMA */ + /* can't fit the transfer length since WRITE DMA has 1 byte for sector count */ + SM_DBG1(("smsatWriteSame10: case 1-2 !!! error due to writesame10!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + else + { + /* case 1 */ + /* WRITE MULTIPLE or WRITE SECTOR(S) */ + /* WRITE SECTORS is chosen for easier implemetation */ + /* can't fit the transfer length since WRITE DMA has 1 byte for sector count */ + SM_DBG1(("smsatWriteSame10: case 1-1 !!! error due to writesame10!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + } /* end of case 1 and 2 */ + + /* case 3 and 4 */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 3 */ + /* WRITE DMA EXT or WRITE DMA FUA EXT */ + /* WRITE DMA EXT is chosen since WRITE SAME does not have FUA bit */ + SM_DBG5(("smsatWriteSame10: case 1-3\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_WRITE_DMA_EXT; /* 0x35 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + if (tl == 0) + { + /* error check + ATA spec, p125, 6.17.29 + pSatDevData->satMaxUserAddrSectors should be 0x0FFFFFFF + and allowed value is 0x0FFFFFFF - 1 + */ + if (pSatDevData->satMaxUserAddrSectors > 0x0FFFFFFF) + { + SM_DBG1(("smsatWriteSame10: case 3 !!! warning can't fit sectors!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + } + /* one sector at a time */ + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + } + else + { + /* case 4 */ + /* WRITE MULTIPLE EXT or WRITE MULTIPLE FUA EXT or WRITE SECTOR(S) EXT */ + /* WRITE SECTORS EXT is chosen for easier implemetation */ + SM_DBG5(("smsatWriteSame10: case 1-4\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_WRITE_SECTORS_EXT; /* 0x34 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + if (tl == 0) + { + /* error check + ATA spec, p125, 6.17.29 + pSatDevData->satMaxUserAddrSectors should be 0x0FFFFFFF + and allowed value is 0x0FFFFFFF - 1 + */ + if (pSatDevData->satMaxUserAddrSectors > 0x0FFFFFFF) + { + SM_DBG1(("smsatWriteSame10: case 4 !!! warning can't fit sectors!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + } + /* one sector at a time */ + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + } + } + + /* case 5 */ + if (pSatDevData->satNCQ == agTRUE) + { + /* WRITE FPDMA QUEUED */ + if (pSatDevData->sat48BitSupport != agTRUE) + { + SM_DBG1(("smsatWriteSame10: case 1-5 !!! error NCQ but 28 bit address support!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + SM_DBG5(("smsatWriteSame10: case 1-5\n")); + + /* Support 48-bit FPDMA addressing, use WRITE FPDMA QUEUE command */ + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_FPDMA_QUEUED; /* 0x61 */ + + if (tl == 0) + { + /* error check + ATA spec, p125, 6.17.29 + pSatDevData->satMaxUserAddrSectors should be 0x0FFFFFFF + and allowed value is 0x0FFFFFFF - 1 + */ + if (pSatDevData->satMaxUserAddrSectors > 0x0FFFFFFF) + { + SM_DBG1(("smsatWriteSame10: case 4 !!! warning can't fit sectors!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + } + /* one sector at a time */ + fis->h.features = 1; /* FIS sector count (7:0) */ + fis->d.featuresExp = 0; /* FIS sector count (15:8) */ + + + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + + /* NO FUA bit in the WRITE SAME 10 */ + fis->d.device = 0x40; /* FIS FUA clear */ + + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_WRITE; + } + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatWriteSame10CB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + return (status); + + + } /* end of case 1 */ + else if ( !(scsiCmnd->cdb[1] & SCSI_WRITE_SAME_LBDATA_MASK) && + (scsiCmnd->cdb[1] & SCSI_WRITE_SAME_PBDATA_MASK)) + { + /* spec 9.26.2, Table 62, p64, case 2*/ + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG5(("smsatWriteSame10: return Table 62 case 2\n")); + return SM_RC_SUCCESS; + } + else if ( (scsiCmnd->cdb[1] & SCSI_WRITE_SAME_LBDATA_MASK) && + !(scsiCmnd->cdb[1] & SCSI_WRITE_SAME_PBDATA_MASK)) + { + SM_DBG5(("smsatWriteSame10: Table 62 case 3\n")); + + } + else /* ( (scsiCmnd->cdb[1] & SCSI_WRITE_SAME_LBDATA_MASK) && + (scsiCmnd->cdb[1] & SCSI_WRITE_SAME_PBDATA_MASK)) */ + { + + /* spec 9.26.2, Table 62, p64, case 4*/ + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG5(("smsatWriteSame10: return Table 62 case 4\n")); + return SM_RC_SUCCESS; + } + + + return SM_RC_SUCCESS; +} + +osGLOBAL bit32 +smsatWriteSame16( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + smScsiRspSense_t *pSense; + + pSense = satIOContext->pSense; + + SM_DBG5(("smsatWriteSame16: start\n")); + + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + SM_DBG1(("smsatWriteSame16: return internal checking!!!\n")); + return SM_RC_SUCCESS; +} + +osGLOBAL bit32 +smsatLogSense( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status; + bit32 agRequestType; + smDeviceData_t *pSatDevData; + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit8 *pLogPage; /* Log Page data buffer */ + bit32 flag = 0; + bit16 AllocLen = 0; /* allocation length */ + bit8 AllLogPages[8]; + bit16 lenRead = 0; + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &smScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + pLogPage = (bit8 *) smScsiRequest->sglVirtualAddr; + + SM_DBG5(("smsatLogSense: start\n")); + + sm_memset(&AllLogPages, 0, 8); + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[9] & SCSI_NACA_MASK) || (scsiCmnd->cdb[9] & SCSI_LINK_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatLogSense: return control!!!\n")); + return SM_RC_SUCCESS; + } + + + AllocLen = ((scsiCmnd->cdb[7] << 8) + scsiCmnd->cdb[8]); + AllocLen = MIN(AllocLen, scsiCmnd->expDataLength); + + /* checking PC (Page Control) */ + /* nothing */ + + /* special cases */ + if (AllocLen == 4) + { + SM_DBG1(("smsatLogSense: AllocLen is 4!!!\n")); + switch (scsiCmnd->cdb[2] & SCSI_LOG_SENSE_PAGE_CODE_MASK) + { + case LOGSENSE_SUPPORTED_LOG_PAGES: + SM_DBG5(("smsatLogSense: case LOGSENSE_SUPPORTED_LOG_PAGES\n")); + + if (pSatDevData->satSMARTFeatureSet == agTRUE) + { + /* add informational exception log */ + flag = 1; + if (pSatDevData->satSMARTSelfTest == agTRUE) + { + /* add Self-Test results log page */ + flag = 2; + } + } + else + { + /* only supported, no informational exception log, no Self-Test results log page */ + flag = 0; + } + lenRead = 4; + AllLogPages[0] = LOGSENSE_SUPPORTED_LOG_PAGES; /* page code */ + AllLogPages[1] = 0; /* reserved */ + switch (flag) + { + case 0: + /* only supported */ + AllLogPages[2] = 0; /* page length */ + AllLogPages[3] = 1; /* page length */ + break; + case 1: + /* supported and informational exception log */ + AllLogPages[2] = 0; /* page length */ + AllLogPages[3] = 2; /* page length */ + break; + case 2: + /* supported and informational exception log */ + AllLogPages[2] = 0; /* page length */ + AllLogPages[3] = 3; /* page length */ + break; + default: + SM_DBG1(("smsatLogSense: error unallowed flag value %d!!!\n", flag)); + break; + } + sm_memcpy(pLogPage, &AllLogPages, lenRead); + break; + case LOGSENSE_SELFTEST_RESULTS_PAGE: + SM_DBG5(("smsatLogSense: case LOGSENSE_SUPPORTED_LOG_PAGES\n")); + lenRead = 4; + AllLogPages[0] = LOGSENSE_SELFTEST_RESULTS_PAGE; /* page code */ + AllLogPages[1] = 0; /* reserved */ + /* page length = SELFTEST_RESULTS_LOG_PAGE_LENGTH - 1 - 3 = 400 = 0x190 */ + AllLogPages[2] = 0x01; + AllLogPages[3] = 0x90; /* page length */ + sm_memcpy(pLogPage, &AllLogPages, lenRead); + + break; + case LOGSENSE_INFORMATION_EXCEPTIONS_PAGE: + SM_DBG5(("smsatLogSense: case LOGSENSE_SUPPORTED_LOG_PAGES\n")); + lenRead = 4; + AllLogPages[0] = LOGSENSE_INFORMATION_EXCEPTIONS_PAGE; /* page code */ + AllLogPages[1] = 0; /* reserved */ + AllLogPages[2] = 0; /* page length */ + AllLogPages[3] = INFORMATION_EXCEPTIONS_LOG_PAGE_LENGTH - 1 - 3; /* page length */ + sm_memcpy(pLogPage, &AllLogPages, lenRead); + break; + default: + SM_DBG1(("smsatLogSense: default Page Code 0x%x!!!\n", scsiCmnd->cdb[2] & SCSI_LOG_SENSE_PAGE_CODE_MASK)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + return SM_RC_SUCCESS; + + } /* if */ + + /* SAT rev8 Table 11 p30*/ + /* checking Page Code */ + switch (scsiCmnd->cdb[2] & SCSI_LOG_SENSE_PAGE_CODE_MASK) + { + case LOGSENSE_SUPPORTED_LOG_PAGES: + SM_DBG5(("smsatLogSense: case 1\n")); + + if (pSatDevData->satSMARTFeatureSet == agTRUE) + { + /* add informational exception log */ + flag = 1; + if (pSatDevData->satSMARTSelfTest == agTRUE) + { + /* add Self-Test results log page */ + flag = 2; + } + } + else + { + /* only supported, no informational exception log, no Self-Test results log page */ + flag = 0; + } + AllLogPages[0] = 0; /* page code */ + AllLogPages[1] = 0; /* reserved */ + switch (flag) + { + case 0: + /* only supported */ + AllLogPages[2] = 0; /* page length */ + AllLogPages[3] = 1; /* page length */ + AllLogPages[4] = 0x00; /* supported page list */ + lenRead = (bit8)(MIN(AllocLen, 5)); + break; + case 1: + /* supported and informational exception log */ + AllLogPages[2] = 0; /* page length */ + AllLogPages[3] = 2; /* page length */ + AllLogPages[4] = 0x00; /* supported page list */ + AllLogPages[5] = 0x10; /* supported page list */ + lenRead = (bit8)(MIN(AllocLen, 6)); + break; + case 2: + /* supported and informational exception log */ + AllLogPages[2] = 0; /* page length */ + AllLogPages[3] = 3; /* page length */ + AllLogPages[4] = 0x00; /* supported page list */ + AllLogPages[5] = 0x10; /* supported page list */ + AllLogPages[6] = 0x2F; /* supported page list */ + lenRead = (bit8)(MIN(AllocLen, 7)); + break; + default: + SM_DBG1(("smsatLogSense: error unallowed flag value %d!!!\n", flag)); + break; + } + + sm_memcpy(pLogPage, &AllLogPages, lenRead); + /* comparing allocation length to Log Page byte size */ + /* SPC-4, 4.3.4.6, p28 */ + if (AllocLen > lenRead ) + { + SM_DBG1(("smsatLogSense: reporting underrun lenRead=0x%x AllocLen=0x%x!!!\n", lenRead, AllocLen)); + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOUnderRun, + AllocLen - lenRead, + agNULL, + satIOContext->interruptContext ); + } + else + { + /*smEnqueueIO(smRoot, satIOContext);*/ + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + } + break; + case LOGSENSE_SELFTEST_RESULTS_PAGE: + SM_DBG5(("smsatLogSense: case 2\n")); + /* checking SMART self-test */ + if (pSatDevData->satSMARTSelfTest == agFALSE) + { + SM_DBG5(("smsatLogSense: case 2 no SMART Self Test\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + } + else + { + /* if satSMARTEnabled is false, send SMART_ENABLE_OPERATIONS */ + if (pSatDevData->satSMARTEnabled == agFALSE) + { + SM_DBG5(("smsatLogSense: case 2 calling satSMARTEnable\n")); + status = smsatLogSenseAllocate(smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext, + 0, + LOG_SENSE_0 + ); + + return status; + + } + else + { + /* SAT Rev 8, 10.2.4 p74 */ + if ( pSatDevData->sat48BitSupport == agTRUE ) + { + SM_DBG5(("smsatLogSense: case 2-1 sends READ LOG EXT\n")); + status = smsatLogSenseAllocate(smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext, + 512, + LOG_SENSE_1 + ); + + return status; + } + else + { + SM_DBG5(("smsatLogSense: case 2-2 sends SMART READ LOG\n")); + status = smsatLogSenseAllocate(smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext, + 512, + LOG_SENSE_2 + ); + + return status; + } + } + } + break; + case LOGSENSE_INFORMATION_EXCEPTIONS_PAGE: + SM_DBG5(("smsatLogSense: case 3\n")); + /* checking SMART feature set */ + if (pSatDevData->satSMARTFeatureSet == agFALSE) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + } + else + { + /* checking SMART feature enabled */ + if (pSatDevData->satSMARTEnabled == agFALSE) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_ATA_DEVICE_FEATURE_NOT_ENABLED, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + } + else + { + /* SAT Rev 8, 10.2.3 p72 */ + SM_DBG5(("smsatLogSense: case 3 sends SMART RETURN STATUS\n")); + + /* sends SMART RETURN STATUS */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_SMART; /* 0xB0 */ + fis->h.features = SAT_SMART_RETURN_STATUS;/* FIS features */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaLowExp = 0; /* FIS LBA (31:24) */ + fis->d.lbaMid = 0x4F; /* FIS LBA (15:8 ) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHigh = 0xC2; /* FIS LBA (23:16) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.device = 0; /* FIS DEV is discared in SATA */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved4 = 0; + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatLogSenseCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + + return status; + } + } + break; + default: + SM_DBG1(("smsatLogSense: default Page Code 0x%x!!!\n", scsiCmnd->cdb[2] & SCSI_LOG_SENSE_PAGE_CODE_MASK)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + break; + } /* end switch */ + + return SM_RC_SUCCESS; +} + +osGLOBAL bit32 +smsatLogSenseAllocate( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smSCSIRequest, + smSatIOContext_t *satIOContext, + bit32 payloadSize, + bit32 flag + ) +{ + smDeviceData_t *pSatDevData; + smIORequestBody_t *smIORequestBody; + smSatInternalIo_t *satIntIo = agNULL; + smSatIOContext_t *satIOContext2; + bit32 status; + + SM_DBG5(("smsatLogSenseAllocate: start\n")); + + pSatDevData = satIOContext->pSatDevData; + + /* create internal satIOContext */ + satIntIo = smsatAllocIntIoResource( smRoot, + smIORequest, /* original request */ + pSatDevData, + payloadSize, + satIntIo); + + if (satIntIo == agNULL) + { + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + satIOContext->interruptContext ); + + SM_DBG1(("smsatLogSenseAllocate: fail in allocation!!!\n")); + return SM_RC_SUCCESS; + } /* end of memory allocation failure */ + + satIntIo->satOrgSmIORequest = smIORequest; + smIORequestBody = (smIORequestBody_t *)satIntIo->satIntRequestBody; + satIOContext2 = &(smIORequestBody->transport.SATA.satIOContext); + + satIOContext2->pSatDevData = pSatDevData; + satIOContext2->pFis = &(smIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev); + satIOContext2->pScsiCmnd = &(satIntIo->satIntSmScsiXchg.scsiCmnd); + satIOContext2->pSense = &(smIORequestBody->transport.SATA.sensePayload); + satIOContext2->pSmSenseData = &(smIORequestBody->transport.SATA.smSenseData); + satIOContext2->pSmSenseData->senseData = satIOContext2->pSense; + satIOContext2->smRequestBody = satIntIo->satIntRequestBody; + satIOContext2->interruptContext = satIOContext->interruptContext; + satIOContext2->satIntIoContext = satIntIo; + satIOContext2->psmDeviceHandle = smDeviceHandle; + satIOContext2->satOrgIOContext = satIOContext; + + if (flag == LOG_SENSE_0) + { + /* SAT_SMART_ENABLE_OPERATIONS */ + status = smsatSMARTEnable( smRoot, + &(satIntIo->satIntSmIORequest), + smDeviceHandle, + &(satIntIo->satIntSmScsiXchg), + satIOContext2); + } + else if (flag == LOG_SENSE_1) + { + /* SAT_READ_LOG_EXT */ + status = smsatLogSense_2( smRoot, + &(satIntIo->satIntSmIORequest), + smDeviceHandle, + &(satIntIo->satIntSmScsiXchg), + satIOContext2); + } + else + { + /* SAT_SMART_READ_LOG */ + /* SAT_READ_LOG_EXT */ + status = smsatLogSense_3( smRoot, + &(satIntIo->satIntSmIORequest), + smDeviceHandle, + &(satIntIo->satIntSmScsiXchg), + satIOContext2); + + } + if (status != SM_RC_SUCCESS) + { + smsatFreeIntIoResource( smRoot, + pSatDevData, + satIntIo); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + + + return SM_RC_SUCCESS; +} + +osGLOBAL bit32 +smsatSMARTEnable( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; + + fis = satIOContext->pFis; + SM_DBG5(("smsatSMARTEnable: start\n")); + /* + * Send the SAT_SMART_ENABLE_OPERATIONS command. + */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_SMART; /* 0xB0 */ + fis->h.features = SAT_SMART_ENABLE_OPERATIONS; + fis->d.lbaLow = 0; + fis->d.lbaMid = 0x4F; + fis->d.lbaHigh = 0xC2; + fis->d.device = 0; + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatSMARTEnableCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + + return status; +} + +osGLOBAL bit32 +smsatLogSense_2( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; + + fis = satIOContext->pFis; + SM_DBG5(("smsatLogSense_2: start\n")); + + /* sends READ LOG EXT */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_READ_LOG_EXT; /* 0x2F */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = 0x07; /* 0x07 */ + fis->d.lbaMid = 0; /* */ + fis->d.lbaHigh = 0; /* */ + fis->d.device = 0; /* */ + fis->d.lbaLowExp = 0; /* */ + fis->d.lbaMidExp = 0; /* */ + fis->d.lbaHighExp = 0; /* */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 0x01; /* 1 sector counts */ + fis->d.sectorCountExp = 0x00; /* 1 sector counts */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatLogSenseCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + return status; +} + +osGLOBAL bit32 +smsatLogSense_3( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; + + fis = satIOContext->pFis; + SM_DBG5(("smsatLogSense_3: start\n")); + /* sends READ LOG EXT */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_SMART; /* 0x2F */ + fis->h.features = SAT_SMART_READ_LOG; /* 0xd5 */ + fis->d.lbaLow = 0x06; /* 0x06 */ + fis->d.lbaMid = 0x4F; /* 0x4f */ + fis->d.lbaHigh = 0xC2; /* 0xc2 */ + fis->d.device = 0; /* */ + fis->d.lbaLowExp = 0; /* */ + fis->d.lbaMidExp = 0; /* */ + fis->d.lbaHighExp = 0; /* */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 0x01; /* 1 sector counts */ + fis->d.sectorCountExp = 0x00; /* 1 sector counts */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatLogSenseCB; + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + return status; +} + + +osGLOBAL bit32 +smsatModeSelect6( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status; + bit32 agRequestType; + smDeviceData_t *pSatDevData; + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit8 *pLogPage; /* Log Page data buffer */ + bit32 StartingIndex = 0; + bit8 PageCode = 0; + bit32 chkCnd = agFALSE; + bit32 parameterListLen = 0; + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &smScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + pLogPage = (bit8 *) smScsiRequest->sglVirtualAddr; + + SM_DBG5(("smsatModeSelect6: start\n")); + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[5] & SCSI_NACA_MASK) || (scsiCmnd->cdb[5] & SCSI_LINK_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatModeSelect6: return control!!!\n")); + return SM_RC_SUCCESS; + } + + /* checking PF bit */ + if ( !(scsiCmnd->cdb[1] & SCSI_MODE_SELECT6_PF_MASK)) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatModeSelect6: PF bit check!!!\n")); + return SM_RC_SUCCESS; + } + + parameterListLen = scsiCmnd->cdb[4]; + parameterListLen = MIN(parameterListLen, scsiCmnd->expDataLength); + if ((0 == parameterListLen) || (agNULL == pLogPage)) + { + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + return SM_RC_SUCCESS; + } + + /* checking Block Descriptor Length on Mode parameter header(6)*/ + if (pLogPage[3] == 8) + { + /* mode parameter block descriptor exists */ + PageCode = (bit8)(pLogPage[12] & 0x3F); /* page code and index is 4 + 8 */ + StartingIndex = 12; + } + else if (pLogPage[3] == 0) + { + /* mode parameter block descriptor does not exist */ + PageCode = (bit8)(pLogPage[4] & 0x3F); /* page code and index is 4 + 0 */ + StartingIndex = 4; + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + return SM_RC_SUCCESS; + } + else + { + SM_DBG1(("smsatModeSelect6: return mode parameter block descriptor 0x%x!!!\n", pLogPage[3])); + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + + + + switch (PageCode) /* page code */ + { + case MODESELECT_CONTROL_PAGE: + SM_DBG1(("smsatModeSelect6: Control mode page!!!\n")); + + if ( pLogPage[StartingIndex+1] != 0x0A || + pLogPage[StartingIndex+2] != 0x02 || + (pSatDevData->satNCQ == agTRUE && pLogPage[StartingIndex+3] != 0x12) || + (pSatDevData->satNCQ == agFALSE && pLogPage[StartingIndex+3] != 0x02) || + (pLogPage[StartingIndex+4] & BIT3_MASK) != 0x00 || /* SWP bit */ + (pLogPage[StartingIndex+4] & BIT4_MASK) != 0x00 || /* UA_INTLCK_CTRL */ + (pLogPage[StartingIndex+4] & BIT5_MASK) != 0x00 || /* UA_INTLCK_CTRL */ + + (pLogPage[StartingIndex+5] & BIT0_MASK) != 0x00 || /* AUTOLOAD MODE */ + (pLogPage[StartingIndex+5] & BIT1_MASK) != 0x00 || /* AUTOLOAD MODE */ + (pLogPage[StartingIndex+5] & BIT2_MASK) != 0x00 || /* AUTOLOAD MODE */ + (pLogPage[StartingIndex+5] & BIT6_MASK) != 0x00 || /* TAS bit */ + + pLogPage[StartingIndex+8] != 0xFF || + pLogPage[StartingIndex+9] != 0xFF || + pLogPage[StartingIndex+10] != 0x00 || + pLogPage[StartingIndex+11] != 0x00 + ) + { + chkCnd = agTRUE; + } + if (chkCnd == agTRUE) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatModeSelect6: unexpected values!!!\n")); + } + else + { + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + } + return SM_RC_SUCCESS; + break; + case MODESELECT_READ_WRITE_ERROR_RECOVERY_PAGE: + SM_DBG1(("smsatModeSelect6: Read-Write Error Recovery mode page!!!\n")); + + if ( (pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT6_AWRE_MASK) || + (pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT6_RC_MASK) || + (pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT6_EER_MASK) || + (pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT6_PER_MASK) || + (pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT6_DTE_MASK) || + (pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT6_DCR_MASK) || + (pLogPage[StartingIndex + 10]) || + (pLogPage[StartingIndex + 11]) + ) + { + SM_DBG5(("smsatModeSelect6: return check condition\n")); + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_PARAMETER_LIST, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + else + { + SM_DBG5(("smsatModeSelect6: return GOOD \n")); + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + return SM_RC_SUCCESS; + } + + break; + case MODESELECT_CACHING: + /* SAT rev8 Table67, p69*/ + SM_DBG5(("smsatModeSelect6: Caching mode page\n")); + if ( (pLogPage[StartingIndex + 2] & 0xFB) || /* 1111 1011 */ + (pLogPage[StartingIndex + 3]) || + (pLogPage[StartingIndex + 4]) || + (pLogPage[StartingIndex + 5]) || + (pLogPage[StartingIndex + 6]) || + (pLogPage[StartingIndex + 7]) || + (pLogPage[StartingIndex + 8]) || + (pLogPage[StartingIndex + 9]) || + (pLogPage[StartingIndex + 10]) || + (pLogPage[StartingIndex + 11]) || + + (pLogPage[StartingIndex + 12] & 0xC1) || /* 1100 0001 */ + (pLogPage[StartingIndex + 13]) || + (pLogPage[StartingIndex + 14]) || + (pLogPage[StartingIndex + 15]) + ) + { + SM_DBG1(("smsatModeSelect6: return check condition!!!\n")); + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_PARAMETER_LIST, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + + } + else + { + /* sends ATA SET FEATURES based on WCE bit */ + if ( !(pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT6_WCE_MASK) ) + { + SM_DBG5(("smsatModeSelect6: disable write cache\n")); + /* sends SET FEATURES */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_SET_FEATURES; /* 0xEF */ + fis->h.features = 0x82; /* disable write cache */ + fis->d.lbaLow = 0; /* */ + fis->d.lbaMid = 0; /* */ + fis->d.lbaHigh = 0; /* */ + fis->d.device = 0; /* */ + fis->d.lbaLowExp = 0; /* */ + fis->d.lbaMidExp = 0; /* */ + fis->d.lbaHighExp = 0; /* */ + fis->d.featuresExp = 0; /* */ + fis->d.sectorCount = 0; /* */ + fis->d.sectorCountExp = 0; /* */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatModeSelect6n10CB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + return status; + } + else + { + SM_DBG5(("smsatModeSelect6: enable write cache\n")); + /* sends SET FEATURES */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_SET_FEATURES; /* 0xEF */ + fis->h.features = 0x02; /* enable write cache */ + fis->d.lbaLow = 0; /* */ + fis->d.lbaMid = 0; /* */ + fis->d.lbaHigh = 0; /* */ + fis->d.device = 0; /* */ + fis->d.lbaLowExp = 0; /* */ + fis->d.lbaMidExp = 0; /* */ + fis->d.lbaHighExp = 0; /* */ + fis->d.featuresExp = 0; /* */ + fis->d.sectorCount = 0; /* */ + fis->d.sectorCountExp = 0; /* */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatModeSelect6n10CB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + return status; + + } + } + break; + case MODESELECT_INFORMATION_EXCEPTION_CONTROL_PAGE: + SM_DBG5(("smsatModeSelect6: Informational Exception Control mode page\n")); + + if ( (pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT6_PERF_MASK) || + (pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT6_TEST_MASK) + ) + { + SM_DBG1(("smsatModeSelect6: return check condition!!! \n")); + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_PARAMETER_LIST, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + else + { + /* sends either ATA SMART ENABLE/DISABLE OPERATIONS based on DEXCPT bit */ + if ( !(pLogPage[StartingIndex + 2] & 0x08) ) + { + SM_DBG5(("smsatModeSelect6: enable information exceptions reporting\n")); + /* sends SMART ENABLE OPERATIONS */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_SMART; /* 0xB0 */ + fis->h.features = SAT_SMART_ENABLE_OPERATIONS; /* enable */ + fis->d.lbaLow = 0; /* */ + fis->d.lbaMid = 0x4F; /* 0x4F */ + fis->d.lbaHigh = 0xC2; /* 0xC2 */ + fis->d.device = 0; /* */ + fis->d.lbaLowExp = 0; /* */ + fis->d.lbaMidExp = 0; /* */ + fis->d.lbaHighExp = 0; /* */ + fis->d.featuresExp = 0; /* */ + fis->d.sectorCount = 0; /* */ + fis->d.sectorCountExp = 0; /* */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatModeSelect6n10CB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + return status; + } + else + { + SM_DBG5(("smsatModeSelect6: disable information exceptions reporting\n")); + /* sends SMART DISABLE OPERATIONS */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_SMART; /* 0xB0 */ + fis->h.features = SAT_SMART_DISABLE_OPERATIONS; /* disable */ + fis->d.lbaLow = 0; /* */ + fis->d.lbaMid = 0x4F; /* 0x4F */ + fis->d.lbaHigh = 0xC2; /* 0xC2 */ + fis->d.device = 0; /* */ + fis->d.lbaLowExp = 0; /* */ + fis->d.lbaMidExp = 0; /* */ + fis->d.lbaHighExp = 0; /* */ + fis->d.featuresExp = 0; /* */ + fis->d.sectorCount = 0; /* */ + fis->d.sectorCountExp = 0; /* */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatModeSelect6n10CB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + return status; + + } + } + break; + default: + SM_DBG1(("smsatModeSelect6: Error unknown page code 0x%x!!!\n", pLogPage[12])); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } +} + + +osGLOBAL bit32 +smsatModeSelect10( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status; + bit32 agRequestType; + smDeviceData_t *pSatDevData; + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit8 *pLogPage; /* Log Page data buffer */ + bit16 BlkDescLen = 0; /* Block Descriptor Length */ + bit32 StartingIndex = 0; + bit8 PageCode = 0; + bit32 chkCnd = agFALSE; + bit32 parameterListLen = 0; + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &smScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + pLogPage = (bit8 *) smScsiRequest->sglVirtualAddr; + + SM_DBG5(("smsatModeSelect10: start\n")); + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[9] & SCSI_NACA_MASK) || (scsiCmnd->cdb[9] & SCSI_LINK_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatModeSelect10: return control!!!\n")); + return SM_RC_SUCCESS; + } + + /* checking PF bit */ + if ( !(scsiCmnd->cdb[1] & SCSI_MODE_SELECT10_PF_MASK)) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatModeSelect10: PF bit check!!!\n")); + return SM_RC_SUCCESS; + } + + parameterListLen = ((scsiCmnd->cdb[7]) << 8) + scsiCmnd->cdb[8]; + parameterListLen = MIN(parameterListLen, scsiCmnd->expDataLength); + if ((0 == parameterListLen) || (agNULL == pLogPage)) + { + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + return SM_RC_SUCCESS; + } + + BlkDescLen = (bit8)((pLogPage[6] << 8) + pLogPage[7]); + + /* checking Block Descriptor Length on Mode parameter header(10) and LONGLBA bit*/ + if ( (BlkDescLen == 8) && !(pLogPage[4] & SCSI_MODE_SELECT10_LONGLBA_MASK) ) + { + /* mode parameter block descriptor exists and length is 8 byte */ + PageCode = (bit8)(pLogPage[16] & 0x3F); /* page code and index is 8 + 8 */ + StartingIndex = 16; + } + else if ( (BlkDescLen == 16) && (pLogPage[4] & SCSI_MODE_SELECT10_LONGLBA_MASK) ) + { + /* mode parameter block descriptor exists and length is 16 byte */ + PageCode = (bit8)(pLogPage[24] & 0x3F); /* page code and index is 8 + 16 */ + StartingIndex = 24; + } + else if (BlkDescLen == 0) + { + PageCode = (bit8)(pLogPage[8] & 0x3F); /* page code and index is 8 + 0 */ + StartingIndex = 8; + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + return SM_RC_SUCCESS; + } + else + { + SM_DBG1(("smsatModeSelect10: return mode parameter block descriptor 0x%x!!!\n", BlkDescLen)); + /* no more than one mode parameter block descriptor shall be supported */ + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + /* + for debugging only + */ + if (StartingIndex == 8) + { + smhexdump("startingindex 8", (bit8 *)pLogPage, 8); + } + else if(StartingIndex == 16) + { + if (PageCode == MODESELECT_CACHING) + { + smhexdump("startingindex 16", (bit8 *)pLogPage, 16+20); + } + else + { + smhexdump("startingindex 16", (bit8 *)pLogPage, 16+12); + } + } + else + { + if (PageCode == MODESELECT_CACHING) + { + smhexdump("startingindex 24", (bit8 *)pLogPage, 24+20); + } + else + { + smhexdump("startingindex 24", (bit8 *)pLogPage, 24+12); + } + } + switch (PageCode) /* page code */ + { + case MODESELECT_CONTROL_PAGE: + SM_DBG5(("smsatModeSelect10: Control mode page\n")); + /* + compare pLogPage to expected value (SAT Table 65, p67) + If not match, return check condition + */ + if ( pLogPage[StartingIndex+1] != 0x0A || + pLogPage[StartingIndex+2] != 0x02 || + (pSatDevData->satNCQ == agTRUE && pLogPage[StartingIndex+3] != 0x12) || + (pSatDevData->satNCQ == agFALSE && pLogPage[StartingIndex+3] != 0x02) || + (pLogPage[StartingIndex+4] & BIT3_MASK) != 0x00 || /* SWP bit */ + (pLogPage[StartingIndex+4] & BIT4_MASK) != 0x00 || /* UA_INTLCK_CTRL */ + (pLogPage[StartingIndex+4] & BIT5_MASK) != 0x00 || /* UA_INTLCK_CTRL */ + + (pLogPage[StartingIndex+5] & BIT0_MASK) != 0x00 || /* AUTOLOAD MODE */ + (pLogPage[StartingIndex+5] & BIT1_MASK) != 0x00 || /* AUTOLOAD MODE */ + (pLogPage[StartingIndex+5] & BIT2_MASK) != 0x00 || /* AUTOLOAD MODE */ + (pLogPage[StartingIndex+5] & BIT6_MASK) != 0x00 || /* TAS bit */ + + pLogPage[StartingIndex+8] != 0xFF || + pLogPage[StartingIndex+9] != 0xFF || + pLogPage[StartingIndex+10] != 0x00 || + pLogPage[StartingIndex+11] != 0x00 + ) + { + chkCnd = agTRUE; + } + if (chkCnd == agTRUE) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatModeSelect10: unexpected values!!!\n")); + } + else + { + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + } + return SM_RC_SUCCESS; + break; + case MODESELECT_READ_WRITE_ERROR_RECOVERY_PAGE: + SM_DBG5(("smsatModeSelect10: Read-Write Error Recovery mode page\n")); + + if ( (pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT10_AWRE_MASK) || + (pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT10_RC_MASK) || + (pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT10_EER_MASK) || + (pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT10_PER_MASK) || + (pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT10_DTE_MASK) || + (pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT10_DCR_MASK) || + (pLogPage[StartingIndex + 10]) || + (pLogPage[StartingIndex + 11]) + ) + { + SM_DBG1(("smsatModeSelect10: return check condition!!!\n")); + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_PARAMETER_LIST, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + else + { + SM_DBG2(("smsatModeSelect10: return GOOD \n")); + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + return SM_RC_SUCCESS; + } + + break; + case MODESELECT_CACHING: + /* SAT rev8 Table67, p69*/ + SM_DBG5(("smsatModeSelect10: Caching mode page\n")); + if ( (pLogPage[StartingIndex + 2] & 0xFB) || /* 1111 1011 */ + (pLogPage[StartingIndex + 3]) || + (pLogPage[StartingIndex + 4]) || + (pLogPage[StartingIndex + 5]) || + (pLogPage[StartingIndex + 6]) || + (pLogPage[StartingIndex + 7]) || + (pLogPage[StartingIndex + 8]) || + (pLogPage[StartingIndex + 9]) || + (pLogPage[StartingIndex + 10]) || + (pLogPage[StartingIndex + 11]) || + + (pLogPage[StartingIndex + 12] & 0xC1) || /* 1100 0001 */ + (pLogPage[StartingIndex + 13]) || + (pLogPage[StartingIndex + 14]) || + (pLogPage[StartingIndex + 15]) + ) + { + SM_DBG1(("smsatModeSelect10: return check condition!!!\n")); + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_PARAMETER_LIST, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + + } + else + { + /* sends ATA SET FEATURES based on WCE bit */ + if ( !(pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT10_WCE_MASK) ) + { + SM_DBG5(("smsatModeSelect10: disable write cache\n")); + /* sends SET FEATURES */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_SET_FEATURES; /* 0xEF */ + fis->h.features = 0x82; /* disable write cache */ + fis->d.lbaLow = 0; /* */ + fis->d.lbaMid = 0; /* */ + fis->d.lbaHigh = 0; /* */ + fis->d.device = 0; /* */ + fis->d.lbaLowExp = 0; /* */ + fis->d.lbaMidExp = 0; /* */ + fis->d.lbaHighExp = 0; /* */ + fis->d.featuresExp = 0; /* */ + fis->d.sectorCount = 0; /* */ + fis->d.sectorCountExp = 0; /* */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatModeSelect6n10CB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + return status; + } + else + { + SM_DBG5(("smsatModeSelect10: enable write cache\n")); + /* sends SET FEATURES */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_SET_FEATURES; /* 0xEF */ + fis->h.features = 0x02; /* enable write cache */ + fis->d.lbaLow = 0; /* */ + fis->d.lbaMid = 0; /* */ + fis->d.lbaHigh = 0; /* */ + fis->d.device = 0; /* */ + fis->d.lbaLowExp = 0; /* */ + fis->d.lbaMidExp = 0; /* */ + fis->d.lbaHighExp = 0; /* */ + fis->d.featuresExp = 0; /* */ + fis->d.sectorCount = 0; /* */ + fis->d.sectorCountExp = 0; /* */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatModeSelect6n10CB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + return status; + + } + } + break; + case MODESELECT_INFORMATION_EXCEPTION_CONTROL_PAGE: + SM_DBG5(("smsatModeSelect10: Informational Exception Control mode page\n")); + + if ( (pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT10_PERF_MASK) || + (pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT10_TEST_MASK) + ) + { + SM_DBG1(("smsatModeSelect10: return check condition!!!\n")); + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_PARAMETER_LIST, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + else + { + /* sends either ATA SMART ENABLE/DISABLE OPERATIONS based on DEXCPT bit */ + if ( !(pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT10_DEXCPT_MASK) ) + { + SM_DBG5(("smsatModeSelect10: enable information exceptions reporting\n")); + /* sends SMART ENABLE OPERATIONS */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_SMART; /* 0xB0 */ + fis->h.features = SAT_SMART_ENABLE_OPERATIONS; /* enable */ + fis->d.lbaLow = 0; /* */ + fis->d.lbaMid = 0x4F; /* 0x4F */ + fis->d.lbaHigh = 0xC2; /* 0xC2 */ + fis->d.device = 0; /* */ + fis->d.lbaLowExp = 0; /* */ + fis->d.lbaMidExp = 0; /* */ + fis->d.lbaHighExp = 0; /* */ + fis->d.featuresExp = 0; /* */ + fis->d.sectorCount = 0; /* */ + fis->d.sectorCountExp = 0; /* */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatModeSelect6n10CB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + return status; + } + else + { + SM_DBG5(("smsatModeSelect10: disable information exceptions reporting\n")); + /* sends SMART DISABLE OPERATIONS */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_SMART; /* 0xB0 */ + fis->h.features = SAT_SMART_DISABLE_OPERATIONS; /* disable */ + fis->d.lbaLow = 0; /* */ + fis->d.lbaMid = 0x4F; /* 0x4F */ + fis->d.lbaHigh = 0xC2; /* 0xC2 */ + fis->d.device = 0; /* */ + fis->d.lbaLowExp = 0; /* */ + fis->d.lbaMidExp = 0; /* */ + fis->d.lbaHighExp = 0; /* */ + fis->d.featuresExp = 0; /* */ + fis->d.sectorCount = 0; /* */ + fis->d.sectorCountExp = 0; /* */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatModeSelect6n10CB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + return status; + + } + } + break; + default: + SM_DBG1(("smsatModeSelect10: Error unknown page code 0x%x!!!\n", pLogPage[12])); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } +} + +osGLOBAL bit32 +smsatSynchronizeCache10( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status; + bit32 agRequestType; + smDeviceData_t *pSatDevData; + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &smScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + SM_DBG5(("smsatSynchronizeCache10: start\n")); + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[9] & SCSI_NACA_MASK) || (scsiCmnd->cdb[9] & SCSI_LINK_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatSynchronizeCache10: return control!!!\n")); + return SM_RC_SUCCESS; + } + + /* checking IMMED bit */ + if (scsiCmnd->cdb[1] & SCSI_SYNC_CACHE_IMMED_MASK) + { + SM_DBG1(("smsatSynchronizeCache10: GOOD status due to IMMED bit!!!\n")); + + /* return GOOD status first here */ + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + } + + /* sends FLUSH CACHE or FLUSH CACHE EXT */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + SM_DBG5(("smsatSynchronizeCache10: sends FLUSH CACHE EXT\n")); + /* FLUSH CACHE EXT */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_FLUSH_CACHE_EXT; /* 0xEA */ + fis->h.features = 0; /* FIS reserve */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaLowExp = 0; /* FIS LBA (31:24) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.device = 0; /* FIS DEV is discared in SATA */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved4 = 0; + fis->d.reserved5 = 0; + + } + else + { + SM_DBG5(("smsatSynchronizeCache10: sends FLUSH CACHE\n")); + /* FLUSH CACHE */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_FLUSH_CACHE; /* 0xE7 */ + fis->h.features = 0; /* FIS features NA */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.device = 0; /* FIS DEV is discared in SATA */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved4 = 0; + fis->d.reserved5 = 0; + + } + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatSynchronizeCache10n16CB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + + return (status); +} + +osGLOBAL bit32 +smsatSynchronizeCache16( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status; + bit32 agRequestType; + smDeviceData_t *pSatDevData; + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &smScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + SM_DBG5(("smsatSynchronizeCache10: start\n")); + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[15] & SCSI_NACA_MASK) || (scsiCmnd->cdb[15] & SCSI_LINK_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatSynchronizeCache10: return control!!!\n")); + return SM_RC_SUCCESS; + } + + + /* checking IMMED bit */ + if (scsiCmnd->cdb[1] & SCSI_SYNC_CACHE_IMMED_MASK) + { + SM_DBG1(("smsatSynchronizeCache10: GOOD status due to IMMED bit!!!\n")); + + /* return GOOD status first here */ + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + } + + /* sends FLUSH CACHE or FLUSH CACHE EXT */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + SM_DBG5(("smsatSynchronizeCache10: sends FLUSH CACHE EXT\n")); + /* FLUSH CACHE EXT */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_FLUSH_CACHE_EXT; /* 0xEA */ + fis->h.features = 0; /* FIS reserve */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaLowExp = 0; /* FIS LBA (31:24) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.device = 0; /* FIS DEV is discared in SATA */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved4 = 0; + fis->d.reserved5 = 0; + + } + else + { + SM_DBG5(("smsatSynchronizeCache10: sends FLUSH CACHE\n")); + /* FLUSH CACHE */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_FLUSH_CACHE; /* 0xE7 */ + fis->h.features = 0; /* FIS features NA */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.device = 0; /* FIS DEV is discared in SATA */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved4 = 0; + fis->d.reserved5 = 0; + + } + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatSynchronizeCache10n16CB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + + return (status); +} + +osGLOBAL bit32 +smsatWriteAndVerify10( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + /* + combination of write10 and verify10 + */ + + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + smDeviceData_t *pSatDevData; + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 lba = 0; + bit32 tl = 0; + bit32 LoopNum = 1; + bit8 LBA[8]; + bit8 TL[8]; + bit32 AllChk = agFALSE; /* lba, lba+tl check against ATA limit and Disk capacity */ + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &smScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + SM_DBG5(("smsatWriteAndVerify10: start\n")); + + /* checking BYTCHK bit */ + if (scsiCmnd->cdb[1] & SCSI_WRITE_N_VERIFY_BYTCHK_MASK) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatWriteAndVerify10: BYTCHK bit checking!!!\n")); + return SM_RC_SUCCESS; + } + + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[9] & SCSI_NACA_MASK) || (scsiCmnd->cdb[9] & SCSI_LINK_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatWriteAndVerify10: return control!!!\n")); + return SM_RC_SUCCESS; + } + + sm_memset(LBA, 0, sizeof(LBA)); + sm_memset(TL, 0, sizeof(TL)); + + /* do not use memcpy due to indexing in LBA and TL */ + LBA[0] = 0; /* MSB */ + LBA[1] = 0; + LBA[2] = 0; + LBA[3] = 0; + LBA[4] = scsiCmnd->cdb[2]; + LBA[5] = scsiCmnd->cdb[3]; + LBA[6] = scsiCmnd->cdb[4]; + LBA[7] = scsiCmnd->cdb[5]; /* LSB */ + + TL[0] = 0; + TL[1] = 0; + TL[2] = 0; + TL[3] = 0; + TL[4] = 0; + TL[5] = 0; + TL[6] = scsiCmnd->cdb[7]; + TL[7] = scsiCmnd->cdb[8]; /* LSB */ + + + /* cbd10; computing LBA and transfer length */ + lba = (scsiCmnd->cdb[2] << (8*3)) + (scsiCmnd->cdb[3] << (8*2)) + + (scsiCmnd->cdb[4] << 8) + scsiCmnd->cdb[5]; + tl = (scsiCmnd->cdb[7] << 8) + scsiCmnd->cdb[8]; + + + /* Table 34, 9.1, p 46 */ + /* + note: As of 2/10/2006, no support for DMA QUEUED + */ + + /* + Table 34, 9.1, p 46, b + When no 48-bit addressing support or NCQ, if LBA is beyond (2^28 - 1), + return check condition + */ + if (pSatDevData->satNCQ != agTRUE && + pSatDevData->sat48BitSupport != agTRUE + ) + { + AllChk = smsatCheckLimit(LBA, TL, agFALSE, pSatDevData); + if (AllChk) + { + SM_DBG1(("smsatWriteAndVerify10: return LBA out of range!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + return SM_RC_SUCCESS; + } + } + else + { + AllChk = smsatCheckLimit(LBA, TL, agTRUE, pSatDevData); + if (AllChk) + { + SM_DBG1(("smsatWriteAndVerify10: return LBA out of range, EXT!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + return SM_RC_SUCCESS; + } + } + + + /* case 1 and 2 */ + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 2 */ + /* WRITE DMA*/ + /* can't fit the transfer length */ + SM_DBG5(("smsatWriteAndVerify10: case 2\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_DMA; /* 0xCA */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (scsiCmnd->cdb[2] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_DMA; + } + else + { + /* case 1 */ + /* WRITE MULTIPLE or WRITE SECTOR(S) */ + /* WRITE SECTORS for easier implemetation */ + /* can't fit the transfer length */ + SM_DBG5(("smsatWriteAndVerify10: case 1\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_SECTORS; /* 0x30 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (scsiCmnd->cdb[2] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + satIOContext->ATACmd = SAT_WRITE_SECTORS; + + } + + /* case 3 and 4 */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 3 */ + /* WRITE DMA EXT or WRITE DMA FUA EXT */ + SM_DBG5(("smsatWriteAndVerify10: case 3\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + /* SAT_WRITE_DMA_FUA_EXT is optional and we don't support it */ + fis->h.command = SAT_WRITE_DMA_EXT; /* 0x35 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[7]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_DMA_EXT; + } + else + { + /* case 4 */ + /* WRITE MULTIPLE EXT or WRITE MULTIPLE FUA EXT or WRITE SECTOR(S) EXT */ + /* WRITE SECTORS EXT for easier implemetation */ + SM_DBG5(("smsatWriteAndVerify10: case 4\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_SECTORS_EXT; /* 0x34 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[7]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + satIOContext->ATACmd = SAT_WRITE_SECTORS_EXT; + } + } + /* case 5 */ + if (pSatDevData->satNCQ == agTRUE) + { + /* WRITE FPDMA QUEUED */ + if (pSatDevData->sat48BitSupport != agTRUE) + { + SM_DBG1(("smsatWriteAndVerify10: case 5 !!! error NCQ but 28 bit address support!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + SM_DBG5(("smsatWriteAndVerify10: case 5\n")); + + /* Support 48-bit FPDMA addressing, use WRITE FPDMA QUEUE command */ + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_FPDMA_QUEUED; /* 0x61 */ + fis->h.features = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + + /* Check FUA bit */ + if (scsiCmnd->cdb[1] & SCSI_WRITE_N_VERIFY10_FUA_MASK) + fis->d.device = 0xC0; /* FIS FUA set */ + else + fis->d.device = 0x40; /* FIS FUA clear */ + + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = scsiCmnd->cdb[7]; /* FIS sector count (15:8) */ + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_FPDMA_QUEUED; + } + + satIOContext->currentLBA = lba; + satIOContext->OrgTL = tl; + + /* + computing number of loop and remainder for tl + 0xFF in case not ext + 0xFFFF in case EXT + */ + if (fis->h.command == SAT_WRITE_SECTORS || fis->h.command == SAT_WRITE_DMA) + { + LoopNum = smsatComputeLoopNum(tl, 0xFF); + } + else if (fis->h.command == SAT_WRITE_SECTORS_EXT || + fis->h.command == SAT_WRITE_DMA_EXT || + fis->h.command == SAT_WRITE_DMA_FUA_EXT + ) + { + /* SAT_READ_SECTORS_EXT, SAT_READ_DMA_EXT */ + LoopNum = smsatComputeLoopNum(tl, 0xFFFF); + } + else + { + /* SAT_WRITE_FPDMA_QUEUED */ + LoopNum = smsatComputeLoopNum(tl, 0xFFFF); + } + + satIOContext->LoopNum = LoopNum; + + + if (LoopNum == 1) + { + SM_DBG5(("smsatWriteAndVerify10: NON CHAINED data\n")); + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatNonChainedWriteNVerifyCB; + } + else + { + SM_DBG1(("smsatWriteAndVerify10: CHAINED data!!!\n")); + /* re-setting tl */ + if (fis->h.command == SAT_WRITE_SECTORS || fis->h.command == SAT_WRITE_DMA) + { + fis->d.sectorCount = 0xFF; + } + else if (fis->h.command == SAT_WRITE_SECTORS_EXT || + fis->h.command == SAT_WRITE_DMA_EXT || + fis->h.command == SAT_WRITE_DMA_FUA_EXT + ) + { + fis->d.sectorCount = 0xFF; + fis->d.sectorCountExp = 0xFF; + } + else + { + /* SAT_WRITE_FPDMA_QUEUED */ + fis->h.features = 0xFF; + fis->d.featuresExp = 0xFF; + } + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatChainedWriteNVerifyCB; + } + + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + return (status); + +} + +osGLOBAL bit32 +smsatWriteAndVerify12( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + /* + combination of write12 and verify12 + temp: since write12 is not support (due to internal checking), no support + */ + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + smDeviceData_t *pSatDevData; + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 lba = 0; + bit32 tl = 0; + bit32 LoopNum = 1; + bit8 LBA[8]; + bit8 TL[8]; + bit32 AllChk = agFALSE; /* lba, lba+tl check against ATA limit and Disk capacity */ + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &smScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + SM_DBG5(("smsatWriteAndVerify12: start\n")); + + /* checking BYTCHK bit */ + if (scsiCmnd->cdb[1] & SCSI_WRITE_N_VERIFY_BYTCHK_MASK) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatWriteAndVerify12: BYTCHK bit checking!!!\n")); + return SM_RC_SUCCESS; + } + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[11] & SCSI_NACA_MASK) || (scsiCmnd->cdb[11] & SCSI_LINK_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatWriteAndVerify12: return control!!!\n")); + return SM_RC_SUCCESS; + } + + sm_memset(LBA, 0, sizeof(LBA)); + sm_memset(TL, 0, sizeof(TL)); + + /* do not use memcpy due to indexing in LBA and TL */ + LBA[0] = 0; /* MSB */ + LBA[1] = 0; + LBA[2] = 0; + LBA[3] = 0; + LBA[4] = scsiCmnd->cdb[2]; + LBA[5] = scsiCmnd->cdb[3]; + LBA[6] = scsiCmnd->cdb[4]; + LBA[7] = scsiCmnd->cdb[5]; /* LSB */ + + TL[0] = 0; /* MSB */ + TL[1] = 0; + TL[2] = 0; + TL[3] = 0; + TL[4] = scsiCmnd->cdb[6]; + TL[5] = scsiCmnd->cdb[7]; + TL[6] = scsiCmnd->cdb[8]; + TL[7] = scsiCmnd->cdb[9]; /* LSB */ + + + lba = smsatComputeCDB12LBA(satIOContext); + tl = smsatComputeCDB12TL(satIOContext); + + + /* Table 34, 9.1, p 46 */ + /* + note: As of 2/10/2006, no support for DMA QUEUED + */ + + /* + Table 34, 9.1, p 46, b + When no 48-bit addressing support or NCQ, if LBA is beyond (2^28 - 1), + return check condition + */ + if (pSatDevData->satNCQ != agTRUE && + pSatDevData->sat48BitSupport != agTRUE + ) + { + AllChk = smsatCheckLimit(LBA, TL, agFALSE, pSatDevData); + if (AllChk) + { + + /*smEnqueueIO(smRoot, satIOContext);*/ + + + SM_DBG1(("smsatWriteAndVerify12: return LBA out of range, not EXT!!!\n")); + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + return SM_RC_SUCCESS; + } + } + else + { + AllChk = smsatCheckLimit(LBA, TL, agTRUE, pSatDevData); + if (AllChk) + { + SM_DBG1(("smsatWriteAndVerify12: return LBA out of range, EXT!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + } + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 2 */ + /* WRITE DMA*/ + /* In case that we can't fit the transfer length, we loop */ + SM_DBG5(("smsatWriteAndVerify12: case 2\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_DMA; /* 0xCA */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (scsiCmnd->cdb[2] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[9]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_DMA; + } + else + { + /* case 1 */ + /* WRITE MULTIPLE or WRITE SECTOR(S) */ + /* WRITE SECTORS for easier implemetation */ + /* In case that we can't fit the transfer length, we loop */ + SM_DBG5(("smsatWriteAndVerify12: case 1\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_SECTORS; /* 0x30 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (scsiCmnd->cdb[2] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[9]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + satIOContext->ATACmd = SAT_WRITE_SECTORS; + } + + /* case 3 and 4 */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 3 */ + /* WRITE DMA EXT or WRITE DMA FUA EXT */ + SM_DBG5(("smsatWriteAndVerify12: case 3\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + /* SAT_WRITE_DMA_FUA_EXT is optional and we don't support it */ + fis->h.command = SAT_WRITE_DMA_EXT; /* 0x35 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[9]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[8]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_DMA_EXT; + } + else + { + /* case 4 */ + /* WRITE MULTIPLE EXT or WRITE MULTIPLE FUA EXT or WRITE SECTOR(S) EXT */ + /* WRITE SECTORS EXT for easier implemetation */ + SM_DBG5(("smsatWriteAndVerify12: case 4\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_SECTORS_EXT; /* 0x34 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[9]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[8]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + satIOContext->ATACmd = SAT_WRITE_SECTORS_EXT; + } + } + + /* case 5 */ + if (pSatDevData->satNCQ == agTRUE) + { + /* WRITE FPDMA QUEUED */ + if (pSatDevData->sat48BitSupport != agTRUE) + { + SM_DBG1(("smsatWriteAndVerify12: case 5 !!! error NCQ but 28 bit address support!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + SM_DBG6(("smsatWriteAndVerify12: case 5\n")); + + /* Support 48-bit FPDMA addressing, use WRITE FPDMA QUEUE command */ + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_FPDMA_QUEUED; /* 0x61 */ + fis->h.features = scsiCmnd->cdb[9]; /* FIS sector count (7:0) */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + + /* Check FUA bit */ + if (scsiCmnd->cdb[1] & SCSI_WRITE12_FUA_MASK) + fis->d.device = 0xC0; /* FIS FUA set */ + else + fis->d.device = 0x40; /* FIS FUA clear */ + + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = scsiCmnd->cdb[8]; /* FIS sector count (15:8) */ + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_FPDMA_QUEUED; + } + + satIOContext->currentLBA = lba; +// satIOContext->OrgLBA = lba; + satIOContext->OrgTL = tl; + + /* + computing number of loop and remainder for tl + 0xFF in case not ext + 0xFFFF in case EXT + */ + if (fis->h.command == SAT_WRITE_SECTORS || fis->h.command == SAT_WRITE_DMA) + { + LoopNum = smsatComputeLoopNum(tl, 0xFF); + } + else if (fis->h.command == SAT_WRITE_SECTORS_EXT || + fis->h.command == SAT_WRITE_DMA_EXT || + fis->h.command == SAT_WRITE_DMA_FUA_EXT + ) + { + /* SAT_READ_SECTORS_EXT, SAT_READ_DMA_EXT */ + LoopNum = smsatComputeLoopNum(tl, 0xFFFF); + } + else + { + /* SAT_WRITE_FPDMA_QUEUEDK */ + LoopNum = smsatComputeLoopNum(tl, 0xFFFF); + } + + satIOContext->LoopNum = LoopNum; + satIOContext->LoopNum2 = LoopNum; + + + if (LoopNum == 1) + { + SM_DBG5(("smsatWriteAndVerify12: NON CHAINED data\n")); + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatNonChainedWriteNVerifyCB; + } + else + { + SM_DBG1(("smsatWriteAndVerify12: CHAINED data!!!\n")); + /* re-setting tl */ + if (fis->h.command == SAT_WRITE_SECTORS || fis->h.command == SAT_WRITE_DMA) + { + fis->d.sectorCount = 0xFF; + } + else if (fis->h.command == SAT_WRITE_SECTORS_EXT || + fis->h.command == SAT_WRITE_DMA_EXT || + fis->h.command == SAT_WRITE_DMA_FUA_EXT + ) + { + fis->d.sectorCount = 0xFF; + fis->d.sectorCountExp = 0xFF; + } + else + { + /* SAT_WRITE_FPDMA_QUEUED */ + fis->h.features = 0xFF; + fis->d.featuresExp = 0xFF; + } + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatChainedWriteNVerifyCB; + } + + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + return (status); +} + +osGLOBAL bit32 +smsatWriteAndVerify16( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + /* + combination of write16 and verify16 + since write16 has 8 bytes LBA -> problem ATA LBA(upto 6 bytes), no support + */ + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + smDeviceData_t *pSatDevData; + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 lba = 0; + bit32 tl = 0; + bit32 LoopNum = 1; + bit8 LBA[8]; + bit8 TL[8]; + bit32 AllChk = agFALSE; /* lba, lba+tl check against ATA limit and Disk capacity */ + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &smScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + SM_DBG5(("smsatWriteAndVerify16: start\n")); + + /* checking BYTCHK bit */ + if (scsiCmnd->cdb[1] & SCSI_WRITE_N_VERIFY_BYTCHK_MASK) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatWriteAndVerify16: BYTCHK bit checking!!!\n")); + return SM_RC_SUCCESS; + } + + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[15] & SCSI_NACA_MASK) || (scsiCmnd->cdb[15] & SCSI_LINK_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatWriteAndVerify16: return control!!!\n")); + return SM_RC_SUCCESS; + } + + sm_memset(LBA, 0, sizeof(LBA)); + sm_memset(TL, 0, sizeof(TL)); + + + /* do not use memcpy due to indexing in LBA and TL */ + LBA[0] = scsiCmnd->cdb[2]; /* MSB */ + LBA[1] = scsiCmnd->cdb[3]; + LBA[2] = scsiCmnd->cdb[4]; + LBA[3] = scsiCmnd->cdb[5]; + LBA[4] = scsiCmnd->cdb[6]; + LBA[5] = scsiCmnd->cdb[7]; + LBA[6] = scsiCmnd->cdb[8]; + LBA[7] = scsiCmnd->cdb[9]; /* LSB */ + + TL[0] = 0; + TL[1] = 0; + TL[2] = 0; + TL[3] = 0; + TL[4] = scsiCmnd->cdb[10]; /* MSB */ + TL[5] = scsiCmnd->cdb[11]; + TL[6] = scsiCmnd->cdb[12]; + TL[7] = scsiCmnd->cdb[13]; /* LSB */ + + + + lba = smsatComputeCDB16LBA(satIOContext); + tl = smsatComputeCDB16TL(satIOContext); + + + /* Table 34, 9.1, p 46 */ + /* + note: As of 2/10/2006, no support for DMA QUEUED + */ + + /* + Table 34, 9.1, p 46, b + When no 48-bit addressing support or NCQ, if LBA is beyond (2^28 - 1), + return check condition + */ + if (pSatDevData->satNCQ != agTRUE && + pSatDevData->sat48BitSupport != agTRUE + ) + { + AllChk = smsatCheckLimit(LBA, TL, agFALSE, pSatDevData); + if (AllChk) + { + SM_DBG1(("smsatWriteAndVerify16: return LBA out of range, not EXT!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + return SM_RC_SUCCESS; + } + } + else + { + AllChk = smsatCheckLimit(LBA, TL, agTRUE, pSatDevData); + if (AllChk) + { + SM_DBG1(("smsatWriteAndVerify16: return LBA out of range, EXT!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + return SM_RC_SUCCESS; + } + } + + + /* case 1 and 2 */ + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 2 */ + /* WRITE DMA*/ + /* In case that we can't fit the transfer length, we loop */ + SM_DBG5(("smsatWriteAndVerify16: case 2\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_DMA; /* 0xCA */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[9]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[8]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[7]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (scsiCmnd->cdb[6] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[13]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_DMA; + } + else + { + /* case 1 */ + /* WRITE MULTIPLE or WRITE SECTOR(S) */ + /* WRITE SECTORS for easier implemetation */ + /* In case that we can't fit the transfer length, we loop */ + SM_DBG5(("smsatWriteAndVerify16: case 1\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_SECTORS; /* 0x30 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[9]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[8]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[7]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (scsiCmnd->cdb[6] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[13]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + satIOContext->ATACmd = SAT_WRITE_SECTORS; + } + + /* case 3 and 4 */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 3 */ + /* WRITE DMA EXT or WRITE DMA FUA EXT */ + SM_DBG5(("smsatWriteAndVerify16: case 3\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + /* SAT_WRITE_DMA_FUA_EXT is optional and we don't support it */ + fis->h.command = SAT_WRITE_DMA_EXT; /* 0x35 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[9]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[8]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[7]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[6]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = scsiCmnd->cdb[5]; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = scsiCmnd->cdb[4]; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[13]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[12]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_DMA_EXT; + } + else + { + /* case 4 */ + /* WRITE MULTIPLE EXT or WRITE MULTIPLE FUA EXT or WRITE SECTOR(S) EXT */ + /* WRITE SECTORS EXT for easier implemetation */ + SM_DBG5(("smsatWriteAndVerify16: case 4\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_SECTORS_EXT; /* 0x34 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[9]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[8]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[7]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[6]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = scsiCmnd->cdb[5]; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = scsiCmnd->cdb[4]; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[13]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[12]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + satIOContext->ATACmd = SAT_WRITE_SECTORS_EXT; + } + } + + /* case 5 */ + if (pSatDevData->satNCQ == agTRUE) + { + /* WRITE FPDMA QUEUED */ + if (pSatDevData->sat48BitSupport != agTRUE) + { + SM_DBG1(("smsatWriteAndVerify16: case 5 !!! error NCQ but 28 bit address support!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + SM_DBG6(("smsatWriteAndVerify16: case 5\n")); + + /* Support 48-bit FPDMA addressing, use WRITE FPDMA QUEUE command */ + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_FPDMA_QUEUED; /* 0x61 */ + fis->h.features = scsiCmnd->cdb[13]; /* FIS sector count (7:0) */ + fis->d.lbaLow = scsiCmnd->cdb[9]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[8]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[7]; /* FIS LBA (23:16) */ + + /* Check FUA bit */ + if (scsiCmnd->cdb[1] & SCSI_WRITE16_FUA_MASK) + fis->d.device = 0xC0; /* FIS FUA set */ + else + fis->d.device = 0x40; /* FIS FUA clear */ + + fis->d.lbaLowExp = scsiCmnd->cdb[6]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = scsiCmnd->cdb[5]; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = scsiCmnd->cdb[4]; /* FIS LBA (47:40) */ + fis->d.featuresExp = scsiCmnd->cdb[12]; /* FIS sector count (15:8) */ + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_FPDMA_QUEUED; + } + + satIOContext->currentLBA = lba; + satIOContext->OrgTL = tl; + + /* + computing number of loop and remainder for tl + 0xFF in case not ext + 0xFFFF in case EXT + */ + if (fis->h.command == SAT_WRITE_SECTORS || fis->h.command == SAT_WRITE_DMA) + { + LoopNum = smsatComputeLoopNum(tl, 0xFF); + } + else if (fis->h.command == SAT_WRITE_SECTORS_EXT || + fis->h.command == SAT_WRITE_DMA_EXT || + fis->h.command == SAT_WRITE_DMA_FUA_EXT + ) + { + /* SAT_READ_SECTORS_EXT, SAT_READ_DMA_EXT */ + LoopNum = smsatComputeLoopNum(tl, 0xFFFF); + } + else + { + /* SAT_WRITE_FPDMA_QUEUEDK */ + LoopNum = smsatComputeLoopNum(tl, 0xFFFF); + } + + satIOContext->LoopNum = LoopNum; + + + if (LoopNum == 1) + { + SM_DBG5(("smsatWriteAndVerify16: NON CHAINED data\n")); + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatNonChainedWriteNVerifyCB; + } + else + { + SM_DBG1(("smsatWriteAndVerify16: CHAINED data!!!\n")); + /* re-setting tl */ + if (fis->h.command == SAT_WRITE_SECTORS || fis->h.command == SAT_WRITE_DMA) + { + fis->d.sectorCount = 0xFF; + } + else if (fis->h.command == SAT_WRITE_SECTORS_EXT || + fis->h.command == SAT_WRITE_DMA_EXT || + fis->h.command == SAT_WRITE_DMA_FUA_EXT + ) + { + fis->d.sectorCount = 0xFF; + fis->d.sectorCountExp = 0xFF; + } + else + { + /* SAT_WRITE_FPDMA_QUEUED */ + fis->h.features = 0xFF; + fis->d.featuresExp = 0xFF; + } + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatChainedWriteNVerifyCB; + } + + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + return (status); +} + +osGLOBAL bit32 +smsatReadMediaSerialNumber( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + smDeviceData_t *pSatDevData; + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + agsaSATAIdentifyData_t *pSATAIdData; + bit8 *pSerialNumber; + bit8 MediaSerialNumber[64] = {0}; + bit32 allocationLen = 0; + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &smScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + pSATAIdData = &(pSatDevData->satIdentifyData); + pSerialNumber = (bit8 *) smScsiRequest->sglVirtualAddr; + + SM_DBG5(("smsatReadMediaSerialNumber: start\n")); + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[11] & SCSI_NACA_MASK) || (scsiCmnd->cdb[11] & SCSI_LINK_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatReadMediaSerialNumber: return control!!!\n")); + return SM_RC_SUCCESS; + } + + allocationLen = (((bit32)scsiCmnd->cdb[6]) << 24) | + (((bit32)scsiCmnd->cdb[7]) << 16) | + (((bit32)scsiCmnd->cdb[8]) << 8 ) | + (((bit32)scsiCmnd->cdb[9])); + allocationLen = MIN(allocationLen, scsiCmnd->expDataLength); + if (allocationLen == 4) + { + if (pSATAIdData->commandSetFeatureDefault & 0x4) + { + SM_DBG1(("smsatReadMediaSerialNumber: Media serial number returning only length!!!\n")); + /* SPC-3 6.16 p192; filling in length */ + MediaSerialNumber[0] = 0; + MediaSerialNumber[1] = 0; + MediaSerialNumber[2] = 0; + MediaSerialNumber[3] = 0x3C; + } + else + { + /* 1 sector - 4 = 512 - 4 to avoid underflow; 0x1fc*/ + MediaSerialNumber[0] = 0; + MediaSerialNumber[1] = 0; + MediaSerialNumber[2] = 0x1; + MediaSerialNumber[3] = 0xfc; + } + + sm_memcpy(pSerialNumber, MediaSerialNumber, 4); + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + + return SM_RC_SUCCESS; + } + + if ( pSatDevData->IDDeviceValid == agTRUE) + { + if (pSATAIdData->commandSetFeatureDefault & 0x4) + { + /* word87 bit2 Media serial number is valid */ + /* read word 176 to 205; length is 2*30 = 60 = 0x3C*/ +#ifdef LOG_ENABLE + smhexdump("ID smsatReadMediaSerialNumber", (bit8*)pSATAIdData->currentMediaSerialNumber, 2*30); +#endif + /* SPC-3 6.16 p192; filling in length */ + MediaSerialNumber[0] = 0; + MediaSerialNumber[1] = 0; + MediaSerialNumber[2] = 0; + MediaSerialNumber[3] = 0x3C; + sm_memcpy(&MediaSerialNumber[4], (void *)pSATAIdData->currentMediaSerialNumber, 60); +#ifdef LOG_ENABLE + smhexdump("smsatReadMediaSerialNumber", (bit8*)MediaSerialNumber, 2*30 + 4); +#endif + sm_memcpy(pSerialNumber, MediaSerialNumber, MIN(allocationLen, 64)); + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + return SM_RC_SUCCESS; + + + } + else + { + /* word87 bit2 Media serial number is NOT valid */ + SM_DBG1(("smsatReadMediaSerialNumber: Media serial number is NOT valid!!!\n")); + + if (pSatDevData->sat48BitSupport == agTRUE) + { + /* READ VERIFY SECTORS EXT */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_SECTORS_EXT; /* 0x24 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = 0; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + } + else + { + /* READ VERIFY SECTORS */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_SECTORS; /* 0x20 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA (27:24) and FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + } + satIOContext->satCompleteCB = &smsatReadMediaSerialNumberCB; + satIOContext->reqType = agRequestType; /* Save it */ + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + return status; + } + } + else + { + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + satIOContext->interruptContext); + + return SM_RC_SUCCESS; + + } +} + +osGLOBAL bit32 +smsatReadBuffer( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status = SM_RC_SUCCESS; + bit32 agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 bufferOffset; + bit32 tl; + bit8 mode; + bit8 bufferID; + bit8 *pBuff; + + pSense = satIOContext->pSense; + scsiCmnd = &smScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + pBuff = (bit8 *) smScsiRequest->sglVirtualAddr; + + SM_DBG5(("smsatReadBuffer: start\n")); + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[9] & SCSI_NACA_MASK) || (scsiCmnd->cdb[9] & SCSI_LINK_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatReadBuffer: return control!!!\n")); + return SM_RC_SUCCESS; + } + + bufferOffset = (scsiCmnd->cdb[3] << (8*2)) + (scsiCmnd->cdb[4] << 8) + scsiCmnd->cdb[5]; + tl = (scsiCmnd->cdb[6] << (8*2)) + (scsiCmnd->cdb[7] << 8) + scsiCmnd->cdb[8]; + + mode = (bit8)(scsiCmnd->cdb[1] & SCSI_READ_BUFFER_MODE_MASK); + bufferID = scsiCmnd->cdb[2]; + + if (mode == READ_BUFFER_DATA_MODE) /* 2 */ + { + if (bufferID == 0 && bufferOffset == 0 && tl == 512) + { + /* send ATA READ BUFFER */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_BUFFER; /* 0xE4 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA (27:24) and FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + + satIOContext->satCompleteCB = &smsatReadBufferCB; + + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + return status; + } + + if (bufferID == 0 && bufferOffset == 0 && tl != 512) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatReadBuffer: allocation length is not 512; it is %d!!!\n", tl)); + return SM_RC_SUCCESS; + } + + if (bufferID == 0 && bufferOffset != 0) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatReadBuffer: buffer offset is not 0; it is %d!!!\n", bufferOffset)); + return SM_RC_SUCCESS; + } + /* all other cases unsupported */ + SM_DBG1(("smsatReadBuffer: unsupported case 1!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_COMMAND, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + return SM_RC_SUCCESS; + + } + else if (mode == READ_BUFFER_DESCRIPTOR_MODE) /* 3 */ + { + if (tl < READ_BUFFER_DESCRIPTOR_MODE_DATA_LEN) /* 4 */ + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatReadBuffer: tl < 4; tl is %d!!!\n", tl)); + return SM_RC_SUCCESS; + } + if (bufferID == 0) + { + /* SPC-4, 6.15.5, p189; SAT-2 Rev00, 8.7.2.3, p41*/ + pBuff[0] = 0xFF; + pBuff[1] = 0x00; + pBuff[2] = 0x02; + pBuff[3] = 0x00; + if (READ_BUFFER_DESCRIPTOR_MODE_DATA_LEN < tl) + { + /* underrrun */ + SM_DBG1(("smsatReadBuffer: underrun tl %d data %d!!!\n", tl, READ_BUFFER_DESCRIPTOR_MODE_DATA_LEN)); + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOUnderRun, + tl - READ_BUFFER_DESCRIPTOR_MODE_DATA_LEN, + agNULL, + satIOContext->interruptContext ); + + return SM_RC_SUCCESS; + } + else + { + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + return SM_RC_SUCCESS; + } + } + else + { + /* We don't support other than bufferID 0 */ + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_COMMAND, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + return SM_RC_SUCCESS; + } + } + else + { + /* We don't support any other mode */ + SM_DBG1(("smsatReadBuffer: unsupported mode %d!!!\n", mode)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_COMMAND, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + return SM_RC_SUCCESS; + } +} + +osGLOBAL bit32 +smsatWriteBuffer( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ +#ifdef NOT_YET + bit32 agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; +#endif + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; +#ifdef NOT_YET + agsaFisRegHostToDevice_t *fis; +#endif + bit32 bufferOffset; + bit32 parmLen; + bit8 mode; + bit8 bufferID; + bit8 *pBuff; + + pSense = satIOContext->pSense; + scsiCmnd = &smScsiRequest->scsiCmnd; +#ifdef NOT_YET + fis = satIOContext->pFis; +#endif + pBuff = (bit8 *) smScsiRequest->sglVirtualAddr; + + SM_DBG5(("smsatWriteBuffer: start\n")); + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[9] & SCSI_NACA_MASK) || (scsiCmnd->cdb[9] & SCSI_LINK_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatWriteBuffer: return control!!!\n")); + return SM_RC_SUCCESS; + } + + bufferOffset = (scsiCmnd->cdb[3] << (8*2)) + (scsiCmnd->cdb[4] << 8) + scsiCmnd->cdb[5]; + parmLen = (scsiCmnd->cdb[6] << (8*2)) + (scsiCmnd->cdb[7] << 8) + scsiCmnd->cdb[8]; + + mode = (bit8)(scsiCmnd->cdb[1] & SCSI_READ_BUFFER_MODE_MASK); + bufferID = scsiCmnd->cdb[2]; + + /* for debugging only */ + smhexdump("smsatWriteBuffer pBuff", (bit8 *)pBuff, 24); + + if (mode == WRITE_BUFFER_DATA_MODE) /* 2 */ + { + if (bufferID == 0 && bufferOffset == 0 && parmLen == 512) + { + SM_DBG1(("smsatWriteBuffer: sending ATA WRITE BUFFER!!!\n")); + /* send ATA WRITE BUFFER */ +#ifdef NOT_YET + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_BUFFER; /* 0xE8 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA (27:24) and FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + + satIOContext->satCompleteCB = &smsatWriteBufferCB; + + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + return status; +#endif + /* temp */ + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + return SM_RC_SUCCESS; + } + if ( (bufferID == 0 && bufferOffset != 0) || + (bufferID == 0 && parmLen != 512) + ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatWriteBuffer: wrong buffer offset %d or parameter length parmLen %d!!!\n", bufferOffset, parmLen)); + return SM_RC_SUCCESS; + } + + /* all other cases unsupported */ + SM_DBG1(("smsatWriteBuffer: unsupported case 1!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_COMMAND, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + return SM_RC_SUCCESS; + + } + else if (mode == WRITE_BUFFER_DL_MICROCODE_SAVE_MODE) /* 5 */ + { + /* temporary */ + SM_DBG1(("smsatWriteBuffer: not yet supported mode %d!!!\n", mode)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_COMMAND, + satIOContext); + + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + return SM_RC_SUCCESS; + } + else + { + /* We don't support any other mode */ + SM_DBG1(("smsatWriteBuffer: unsupported mode %d!!!\n", mode)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_COMMAND, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + return SM_RC_SUCCESS; + } + +} + +osGLOBAL bit32 +smsatReassignBlocks( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + /* + assumes all LBA fits in ATA command; no boundary condition is checked here yet + */ + bit32 status; + bit32 agRequestType; + smDeviceData_t *pSatDevData; + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit8 *pParmList; /* Log Page data buffer */ + bit8 LongLBA; + bit8 LongList; + bit32 defectListLen; + bit8 LBA[8]; + bit32 startingIndex; + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &smScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + pParmList = (bit8 *) smScsiRequest->sglVirtualAddr; + + SM_DBG5(("smsatReassignBlocks: start\n")); + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[5] & SCSI_NACA_MASK) || (scsiCmnd->cdb[5] & SCSI_LINK_MASK) ) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatReassignBlocks: return control!!!\n")); + return SM_RC_SUCCESS; + } + + sm_memset(satIOContext->LBA, 0, 8); + satIOContext->ParmIndex = 0; + satIOContext->ParmLen = 0; + + LongList = (bit8)(scsiCmnd->cdb[1] & SCSI_REASSIGN_BLOCKS_LONGLIST_MASK); + LongLBA = (bit8)(scsiCmnd->cdb[1] & SCSI_REASSIGN_BLOCKS_LONGLBA_MASK); + sm_memset(LBA, 0, sizeof(LBA)); + + if (LongList == 0) + { + defectListLen = (pParmList[2] << 8) + pParmList[3]; + } + else + { + defectListLen = (pParmList[0] << (8*3)) + (pParmList[1] << (8*2)) + + (pParmList[2] << 8) + pParmList[3]; + } + /* SBC 5.16.2, p61*/ + satIOContext->ParmLen = defectListLen + 4 /* header size */; + + startingIndex = 4; + + if (LongLBA == 0) + { + LBA[4] = pParmList[startingIndex]; /* MSB */ + LBA[5] = pParmList[startingIndex+1]; + LBA[6] = pParmList[startingIndex+2]; + LBA[7] = pParmList[startingIndex+3]; /* LSB */ + startingIndex = startingIndex + 4; + } + else + { + LBA[0] = pParmList[startingIndex]; /* MSB */ + LBA[1] = pParmList[startingIndex+1]; + LBA[2] = pParmList[startingIndex+2]; + LBA[3] = pParmList[startingIndex+3]; + LBA[4] = pParmList[startingIndex+4]; + LBA[5] = pParmList[startingIndex+5]; + LBA[6] = pParmList[startingIndex+6]; + LBA[7] = pParmList[startingIndex+7]; /* LSB */ + startingIndex = startingIndex + 8; + } + + smhexdump("smsatReassignBlocks Parameter list", (bit8 *)pParmList, 4 + defectListLen); + + if (pSatDevData->sat48BitSupport == agTRUE) + { + /* sends READ VERIFY SECTOR(S) EXT*/ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS_EXT;/* 0x42 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[7]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[6]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[5]; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = LBA[4]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = LBA[3]; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = LBA[2]; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.device = 0x40; /* 01000000 */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + } + else + { + /* READ VERIFY SECTOR(S)*/ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS;/* 0x40 */ + fis->h.features = 0; /* FIS features NA */ + fis->d.lbaLow = LBA[7]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[6]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[5]; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.device = (bit8)((0x4 << 4) | (LBA[4] & 0xF)); + /* DEV and LBA 27:24 */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + } + + sm_memcpy(satIOContext->LBA, LBA, 8); + satIOContext->ParmIndex = startingIndex; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatReassignBlocksCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + return status; +} + +osGLOBAL bit32 +smsatRead_1( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + /* + Assumption: error check on lba and tl has been done in satRead*() + lba = lba + tl; + */ + bit32 status; + smSatIOContext_t *satOrgIOContext = agNULL; + smIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 agRequestType = AGSA_SATA_PROTOCOL_DMA_READ; + bit32 lba = 0; + bit32 DenomTL = 0xFF; + bit32 Remainder = 0; + bit8 LBA[4]; /* 0 MSB, 3 LSB */ + + SM_DBG2(("smsatRead_1: start\n")); + + fis = satIOContext->pFis; + satOrgIOContext = satIOContext->satOrgIOContext; + scsiCmnd = satOrgIOContext->pScsiCmnd; + + sm_memset(LBA,0, sizeof(LBA)); + + switch (satOrgIOContext->ATACmd) + { + case SAT_READ_DMA: + DenomTL = 0x100; + break; + case SAT_READ_SECTORS: + DenomTL = 0x100; + break; + case SAT_READ_DMA_EXT: + DenomTL = 0xFFFF; + break; + case SAT_READ_SECTORS_EXT: + DenomTL = 0xFFFF; + break; + case SAT_READ_FPDMA_QUEUED: + DenomTL = 0xFFFF; + break; + default: + SM_DBG1(("smsatRead_1: error incorrect ata command 0x%x!!!\n", satIOContext->ATACmd)); + return SM_RC_FAILURE; + break; + } + + Remainder = satOrgIOContext->OrgTL % DenomTL; + satOrgIOContext->currentLBA = satOrgIOContext->currentLBA + DenomTL; + lba = satOrgIOContext->currentLBA; + + LBA[0] = (bit8)((lba & 0xFF000000) >> (8 * 3)); + LBA[1] = (bit8)((lba & 0xFF0000) >> (8 * 2)); + LBA[2] = (bit8)((lba & 0xFF00) >> 8); + LBA[3] = (bit8)(lba & 0xFF); + + switch (satOrgIOContext->ATACmd) + { + case SAT_READ_DMA: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_DMA; /* 0xC8 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + fis->d.device = + (bit8)((0x4 << 4) | (LBA[0] & 0xF)); /* FIS LBA (27:24) and FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->d.sectorCount = (bit8)Remainder; /* FIS sector count (7:0) */ + } + else + { + fis->d.sectorCount = 0x0; /* FIS sector count (7:0) */ + } + + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_READ; + + break; + case SAT_READ_SECTORS: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_SECTORS; /* 0x20 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + fis->d.device = + (bit8)((0x4 << 4) | (LBA[0] & 0xF)); /* FIS LBA (27:24) and FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->d.sectorCount = (bit8)Remainder; /* FIS sector count (7:0) */ + } + else + { + fis->d.sectorCount = 0x0; /* FIS sector count (7:0) */ + } + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + + break; + case SAT_READ_DMA_EXT: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_DMA_EXT; /* 0x25 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = LBA[0]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->d.sectorCount = (bit8)(Remainder & 0xFF); /* FIS sector count (7:0) */ + fis->d.sectorCountExp = (bit8)((Remainder & 0xFF00) >> 8); /* FIS sector count (15:8) */ + + } + else + { + fis->d.sectorCount = 0xFF; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0xFF; /* FIS sector count (15:8) */ + } + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_READ; + + break; + case SAT_READ_SECTORS_EXT: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_SECTORS_EXT; /* 0x24 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = LBA[0]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->d.sectorCount = (bit8)(Remainder & 0xFF); /* FIS sector count (7:0) */ + fis->d.sectorCountExp = (bit8)((Remainder & 0xFF00) >> 8); /* FIS sector count (15:8) */ + } + else + { + fis->d.sectorCount = 0xFF; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0xFF; /* FIS sector count (15:8) */ + } + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + break; + case SAT_READ_FPDMA_QUEUED: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_FPDMA_QUEUED; /* 0x60 */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + + /* Check FUA bit */ + if (scsiCmnd->cdb[1] & SCSI_READ10_FUA_MASK) + fis->d.device = 0xC0; /* FIS FUA set */ + else + fis->d.device = 0x40; /* FIS FUA clear */ + + fis->d.lbaLowExp = LBA[0]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->h.features = (bit8)(Remainder & 0xFF); /* FIS sector count (7:0) */ + fis->d.featuresExp = (bit8)((Remainder & 0xFF00) >> 8); /* FIS sector count (15:8) */ + } + else + { + fis->h.features = 0xFF; /* FIS sector count (7:0) */ + fis->d.featuresExp = 0xFF; /* FIS sector count (15:8) */ + } + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_READ; + break; + default: + SM_DBG1(("smsatRead_1: error incorrect ata command 0x%x!!!\n", satIOContext->ATACmd)); + return SM_RC_FAILURE; + break; + } + + /* Initialize CB for SATA completion. + */ + /* chained data */ + satIOContext->satCompleteCB = &smsatChainedDataIOCB; + + if (satOrgIOContext->ATACmd == SAT_READ_DMA || satOrgIOContext->ATACmd == SAT_READ_SECTORS) + { + smsatSplitSGL(smRoot, + smIORequest, + smDeviceHandle, + (smScsiInitiatorRequest_t *)satOrgIOContext->smScsiXchg, + satOrgIOContext, + NON_BIT48_ADDRESS_TL_LIMIT * SATA_SECTOR_SIZE, /* 0x100 * 0x200*/ + (satOrgIOContext->OrgTL) * SATA_SECTOR_SIZE, + agFALSE); + } + else + { + smsatSplitSGL(smRoot, + smIORequest, + smDeviceHandle, + (smScsiInitiatorRequest_t *)satOrgIOContext->smScsiXchg, + satOrgIOContext, + BIT48_ADDRESS_TL_LIMIT * SATA_SECTOR_SIZE, /* 0xFFFF * 0x200*/ + (satOrgIOContext->OrgTL) * SATA_SECTOR_SIZE, + agFALSE); + } + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + (smScsiInitiatorRequest_t *)satOrgIOContext->smScsiXchg, //smScsiRequest, + satIOContext); + + SM_DBG5(("smsatRead_1: return\n")); + return (status); +} + +osGLOBAL bit32 +smsatWrite_1( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + /* + Assumption: error check on lba and tl has been done in satWrite*() + lba = lba + tl; + */ + bit32 status; + smSatIOContext_t *satOrgIOContext = agNULL; + smIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + bit32 lba = 0; + bit32 DenomTL = 0xFF; + bit32 Remainder = 0; + bit8 LBA[4]; /* 0 MSB, 3 LSB */ + + SM_DBG2(("smsatWrite_1: start\n")); + + fis = satIOContext->pFis; + satOrgIOContext = satIOContext->satOrgIOContext; + scsiCmnd = satOrgIOContext->pScsiCmnd; + + sm_memset(LBA,0, sizeof(LBA)); + + switch (satOrgIOContext->ATACmd) + { + case SAT_WRITE_DMA: + DenomTL = 0x100; + break; + case SAT_WRITE_SECTORS: + DenomTL = 0x100; + break; + case SAT_WRITE_DMA_EXT: + DenomTL = 0xFFFF; + break; + case SAT_WRITE_DMA_FUA_EXT: + DenomTL = 0xFFFF; + break; + case SAT_WRITE_SECTORS_EXT: + DenomTL = 0xFFFF; + break; + case SAT_WRITE_FPDMA_QUEUED: + DenomTL = 0xFFFF; + break; + default: + SM_DBG1(("smsatWrite_1: error incorrect ata command 0x%x!!!\n", satIOContext->ATACmd)); + return SM_RC_FAILURE; + break; + } + + Remainder = satOrgIOContext->OrgTL % DenomTL; + satOrgIOContext->currentLBA = satOrgIOContext->currentLBA + DenomTL; + lba = satOrgIOContext->currentLBA; + + + LBA[0] = (bit8)((lba & 0xFF000000) >> (8 * 3)); + LBA[1] = (bit8)((lba & 0xFF0000) >> (8 * 2)); + LBA[2] = (bit8)((lba & 0xFF00) >> 8); + LBA[3] = (bit8)(lba & 0xFF); + + switch (satOrgIOContext->ATACmd) + { + case SAT_WRITE_DMA: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_DMA; /* 0xCA */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (LBA[0] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->d.sectorCount = (bit8)Remainder; /* FIS sector count (7:0) */ + } + else + { + fis->d.sectorCount = 0x0; /* FIS sector count (7:0) */ + } + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + + break; + case SAT_WRITE_SECTORS: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_SECTORS; /* 0x30 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (LBA[0] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->d.sectorCount = (bit8)Remainder; /* FIS sector count (7:0) */ + } + else + { + fis->d.sectorCount = 0x0; /* FIS sector count (7:0) */ + } + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + + break; + case SAT_WRITE_DMA_EXT: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_DMA_EXT; /* 0x3D */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = LBA[0]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->d.sectorCount = (bit8)(Remainder & 0xFF); /* FIS sector count (7:0) */ + fis->d.sectorCountExp = (bit8)((Remainder & 0xFF00) >> 8); /* FIS sector count (15:8) */ + } + else + { + fis->d.sectorCount = 0xFF; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0xFF; /* FIS sector count (15:8) */ + } + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + + break; + case SAT_WRITE_SECTORS_EXT: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_SECTORS_EXT; /* 0x34 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = LBA[0]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->d.sectorCount = (bit8)(Remainder & 0xFF); /* FIS sector count (7:0) */ + fis->d.sectorCountExp = (bit8)((Remainder & 0xFF00) >> 8); /* FIS sector count (15:8) */ + } + else + { + fis->d.sectorCount = 0xFF; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0xFF; /* FIS sector count (15:8) */ + } + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + + break; + case SAT_WRITE_FPDMA_QUEUED: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_FPDMA_QUEUED; /* 0x61 */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + + /* Check FUA bit */ + if (scsiCmnd->cdb[1] & SCSI_WRITE10_FUA_MASK) + fis->d.device = 0xC0; /* FIS FUA set */ + else + fis->d.device = 0x40; /* FIS FUA clear */ + + fis->d.lbaLowExp = LBA[0];; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->h.features = (bit8)(Remainder & 0xFF); /* FIS sector count (7:0) */ + fis->d.featuresExp = (bit8)((Remainder & 0xFF00) >> 8); /* FIS sector count (15:8) */ + } + else + { + fis->h.features = 0xFF; /* FIS sector count (7:0) */ + fis->d.featuresExp = 0xFF; /* FIS sector count (15:8) */ + } + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_WRITE; + break; + + default: + SM_DBG1(("smsatWrite_1: error incorrect ata command 0x%x!!!\n", satIOContext->ATACmd)); + return SM_RC_FAILURE; + break; + } + + /* Initialize CB for SATA completion. + */ + /* chained data */ + satIOContext->satCompleteCB = &smsatChainedDataIOCB; + + if (satOrgIOContext->ATACmd == SAT_WRITE_DMA || satOrgIOContext->ATACmd == SAT_WRITE_SECTORS) + { + smsatSplitSGL(smRoot, + smIORequest, + smDeviceHandle, + (smScsiInitiatorRequest_t *)satOrgIOContext->smScsiXchg, + satOrgIOContext, + NON_BIT48_ADDRESS_TL_LIMIT * SATA_SECTOR_SIZE, /* 0x100 * 0x200*/ + (satOrgIOContext->OrgTL) * SATA_SECTOR_SIZE, + agFALSE); + } + else + { + smsatSplitSGL(smRoot, + smIORequest, + smDeviceHandle, + (smScsiInitiatorRequest_t *)satOrgIOContext->smScsiXchg, + satOrgIOContext, + BIT48_ADDRESS_TL_LIMIT * SATA_SECTOR_SIZE, /* 0xFFFF * 0x200*/ + (satOrgIOContext->OrgTL) * SATA_SECTOR_SIZE, + agFALSE); + } + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + (smScsiInitiatorRequest_t *)satOrgIOContext->smScsiXchg, //smScsiRequest, + satIOContext); + + SM_DBG5(("smsatWrite_1: return\n")); + return (status); +} + +osGLOBAL bit32 +smsatPassthrough( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + smDeviceData_t *pSatDevData; + agsaFisRegHostToDevice_t *fis; + bit32 status; + bit32 agRequestType; + smAtaPassThroughHdr_t ataPassThroughHdr; + + + pSense = satIOContext->pSense; + scsiCmnd = &smScsiRequest->scsiCmnd; + pSatDevData = satIOContext->pSatDevData; + fis = satIOContext->pFis; + + SM_DBG1(("smsatPassthrough: START!!!\n")); + + osti_memset(&ataPassThroughHdr, 0 , sizeof(smAtaPassThroughHdr_t)); + + ataPassThroughHdr.opc = scsiCmnd->cdb[0]; + ataPassThroughHdr.mulCount = scsiCmnd->cdb[1] >> 5; + ataPassThroughHdr.proto = (scsiCmnd->cdb[1] >> 1) & 0x0F; + ataPassThroughHdr.extend = scsiCmnd->cdb[1] & 1; + ataPassThroughHdr.offline = scsiCmnd->cdb[2] >> 6; + ataPassThroughHdr.ckCond = (scsiCmnd->cdb[2] >> 5) & 1; + ataPassThroughHdr.tType = (scsiCmnd->cdb[2] >> 4) & 1; + ataPassThroughHdr.tDir = (scsiCmnd->cdb[2] >> 3) & 1; + ataPassThroughHdr.byteBlock = (scsiCmnd->cdb[2] >> 2) & 1; + ataPassThroughHdr.tlength = scsiCmnd->cdb[2] & 0x3; + + switch(ataPassThroughHdr.proto) + { + case 0: + case 9: + agRequestType = AGSA_SATA_PROTOCOL_DEV_RESET; //Device Reset + break; + case 1: + agRequestType = AGSA_SATA_PROTOCOL_SRST_ASSERT; //Software reset + break; + case 3: + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; //Non Data mode + break; + case 4: + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; //IO_Data_In mode + break; + case 5: + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; //PIO_Data_out + break; + case 6: + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; //DMA READ and WRITE + break; + case 8: + agRequestType = AGSA_SATA_ATAP_EXECDEVDIAG; //device diagnostic + break; + case 12: + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_WRITE; //FPDMA Read and Write + break; + default: + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; //Default Non Data Mode + break; + } + + + if((ataPassThroughHdr.tlength == 0) && (agRequestType != AGSA_SATA_PROTOCOL_NON_DATA)) + { + SM_DBG1(("smsatPassthrough SCSI_SNSCODE_INVALID_FIELD_IN_CDB\n")); + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + return SM_RC_SUCCESS; + } + + if(scsiCmnd->cdb[0] == 0xA1) + { + SM_DBG1(("smsatPassthrough A1h: COMMAND: %x FEATURE: %x \n",scsiCmnd->cdb[9],scsiCmnd->cdb[3])); + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.features = scsiCmnd->cdb[3]; + fis->d.sectorCount = scsiCmnd->cdb[4]; /* 0x01 FIS sector count (7:0) */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* Reading LBA FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[6]; + fis->d.lbaHigh = scsiCmnd->cdb[7]; + fis->d.device = scsiCmnd->cdb[8]; + fis->h.command = scsiCmnd->cdb[9]; + fis->d.featuresExp = 0; + fis->d.sectorCountExp = 0; + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + /* Initialize CB for SATA completion*/ + satIOContext->satCompleteCB = &smsatPassthroughCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + + satIOContext->reqType = agRequestType; + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + return status; + + } + else if(scsiCmnd->cdb[0] == 0x85) + { + SM_DBG1(("smsatPassthrough 85h: COMMAND: %x FEATURE: %x \n",scsiCmnd->cdb[14],scsiCmnd->cdb[4])); + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + if(1 == ataPassThroughHdr.extend) + { + fis->d.featuresExp = scsiCmnd->cdb[3]; + fis->d.sectorCountExp = scsiCmnd->cdb[5]; + fis->d.lbaMidExp = scsiCmnd->cdb[9]; + fis->d.lbaHighExp = scsiCmnd->cdb[11]; + fis->d.lbaLowExp = scsiCmnd->cdb[7]; + } + fis->h.features = scsiCmnd->cdb[4]; + fis->d.sectorCount = scsiCmnd->cdb[6]; + fis->d.lbaLow = scsiCmnd->cdb[8]; + fis->d.lbaMid = scsiCmnd->cdb[10]; + fis->d.lbaHigh = scsiCmnd->cdb[12]; + fis->d.device = scsiCmnd->cdb[13]; + fis->h.command = scsiCmnd->cdb[14]; + fis->d.reserved4 = 0; + fis->d.control = 0; + fis->d.reserved5 = 0; + + + /* Initialize CB for SATA completion. + */ + + satIOContext->satCompleteCB = &smsatPassthroughCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + return status; + + } + else + { + SM_DBG1(("smsatPassthrough : INVALD PASSTHROUGH!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatPassthrough : return control!!!\n")); + + return SM_RC_SUCCESS; + } +} + +osGLOBAL bit32 +smsatNonChainedWriteNVerify_Verify( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + smDeviceData_t *pSatDevData; + smIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &smScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + SM_DBG5(("smsatNonChainedWriteNVerify_Verify: start\n")); + if (pSatDevData->sat48BitSupport == agTRUE) + { + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_READ_VERIFY_SECTORS_EXT;/* 0x42 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set 01000000 */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[7]; /* FIS sector count (15:8) */ + + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatNonChainedWriteNVerifyCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + + SM_DBG1(("smsatNonChainedWriteNVerify_Verify: return status %d!!!\n", status)); + return (status); + } + else + { + /* can't fit in SAT_READ_VERIFY_SECTORS becasue of Sector Count and LBA */ + SM_DBG1(("smsatNonChainedWriteNVerify_Verify: can't fit in SAT_READ_VERIFY_SECTORS!!!\n")); + return SM_RC_FAILURE; + } +} + +osGLOBAL bit32 +smsatChainedWriteNVerify_Start_Verify( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + /* + deal with transfer length; others have been handled previously at this point; + no LBA check; no range check; + */ + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + smDeviceData_t *pSatDevData; + smIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 lba = 0; + bit32 tl = 0; + bit32 LoopNum = 1; + bit8 LBA[4]; + bit8 TL[4]; + + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &smScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + SM_DBG5(("smsatChainedWriteNVerify_Start_Verify: start\n")); + sm_memset(LBA, 0, sizeof(LBA)); + sm_memset(TL, 0, sizeof(TL)); + /* do not use memcpy due to indexing in LBA and TL */ + LBA[0] = scsiCmnd->cdb[2]; /* MSB */ + LBA[1] = scsiCmnd->cdb[3]; + LBA[2] = scsiCmnd->cdb[4]; + LBA[3] = scsiCmnd->cdb[5]; /* LSB */ + TL[0] = scsiCmnd->cdb[6]; /* MSB */ + TL[1] = scsiCmnd->cdb[7]; + TL[2] = scsiCmnd->cdb[7]; + TL[3] = scsiCmnd->cdb[8]; /* LSB */ + lba = smsatComputeCDB12LBA(satIOContext); + tl = smsatComputeCDB12TL(satIOContext); + if (pSatDevData->sat48BitSupport == agTRUE) + { + SM_DBG5(("smsatChainedWriteNVerify_Start_Verify: SAT_READ_VERIFY_SECTORS_EXT\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_READ_VERIFY_SECTORS_EXT;/* 0x42 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set 01000000 */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[7]; /* FIS sector count (15:8) */ + + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + satIOContext->ATACmd = SAT_READ_VERIFY_SECTORS_EXT; + } + else + { + SM_DBG5(("smsatChainedWriteNVerify_Start_Verify: SAT_READ_VERIFY_SECTORS\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS; /* 0x40 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (scsiCmnd->cdb[2] & 0xF)); + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + satIOContext->ATACmd = SAT_READ_VERIFY_SECTORS; + + } + + satIOContext->currentLBA = lba; + satIOContext->OrgTL = tl; + + /* + computing number of loop and remainder for tl + 0xFF in case not ext + 0xFFFF in case EXT + */ + if (fis->h.command == SAT_READ_VERIFY_SECTORS) + { + LoopNum = smsatComputeLoopNum(tl, 0xFF); + } + else if (fis->h.command == SAT_READ_VERIFY_SECTORS_EXT) + { + /* SAT_READ_SECTORS_EXT, SAT_READ_DMA_EXT */ + LoopNum = smsatComputeLoopNum(tl, 0xFFFF); + } + else + { + SM_DBG1(("smsatChainedWriteNVerify_Start_Verify: error case 1!!!\n")); + LoopNum = 1; + } + + satIOContext->LoopNum = LoopNum; + + if (LoopNum == 1) + { + SM_DBG5(("smsatChainedWriteNVerify_Start_Verify: NON CHAINED data\n")); + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatNonChainedWriteNVerifyCB; + } + else + { + SM_DBG1(("smsatChainedWriteNVerify_Start_Verify: CHAINED data!!!\n")); + /* re-setting tl */ + if (fis->h.command == SAT_READ_VERIFY_SECTORS) + { + fis->d.sectorCount = 0xFF; + } + else if (fis->h.command == SAT_READ_VERIFY_SECTORS_EXT) + { + fis->d.sectorCount = 0xFF; + fis->d.sectorCountExp = 0xFF; + } + else + { + SM_DBG1(("smsatChainedWriteNVerify_Start_Verify: error case 2!!!\n")); + } + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatChainedWriteNVerifyCB; + } + + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + return (status); + + +} + +osGLOBAL bit32 +smsatChainedWriteNVerify_Write( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + /* + Assumption: error check on lba and tl has been done in satWrite*() + lba = lba + tl; + */ + bit32 status; + smSatIOContext_t *satOrgIOContext = agNULL; + smIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + bit32 lba = 0; + bit32 DenomTL = 0xFF; + bit32 Remainder = 0; + bit8 LBA[4]; /* 0 MSB, 3 LSB */ + + SM_DBG1(("smsatChainedWriteNVerify_Write: start\n")); + + fis = satIOContext->pFis; + satOrgIOContext = satIOContext->satOrgIOContext; + scsiCmnd = satOrgIOContext->pScsiCmnd; + + + sm_memset(LBA,0, sizeof(LBA)); + + switch (satOrgIOContext->ATACmd) + { + case SAT_WRITE_DMA: + DenomTL = 0xFF; + break; + case SAT_WRITE_SECTORS: + DenomTL = 0xFF; + break; + case SAT_WRITE_DMA_EXT: + DenomTL = 0xFFFF; + break; + case SAT_WRITE_DMA_FUA_EXT: + DenomTL = 0xFFFF; + break; + case SAT_WRITE_SECTORS_EXT: + DenomTL = 0xFFFF; + break; + case SAT_WRITE_FPDMA_QUEUED: + DenomTL = 0xFFFF; + break; + default: + SM_DBG1(("satChainedWriteNVerify_Write: error incorrect ata command 0x%x!!!\n", satIOContext->ATACmd)); + return SM_RC_FAILURE; + break; + } + + Remainder = satOrgIOContext->OrgTL % DenomTL; + satOrgIOContext->currentLBA = satOrgIOContext->currentLBA + DenomTL; + lba = satOrgIOContext->currentLBA; + + LBA[0] = (bit8)((lba & 0xF000) >> (8 * 3)); /* MSB */ + LBA[1] = (bit8)((lba & 0xF00) >> (8 * 2)); + LBA[2] = (bit8)((lba & 0xF0) >> 8); + LBA[3] = (bit8)(lba & 0xF); /* LSB */ + + switch (satOrgIOContext->ATACmd) + { + case SAT_WRITE_DMA: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_DMA; /* 0xCA */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (LBA[0] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->d.sectorCount = (bit8)Remainder; /* FIS sector count (7:0) */ + } + else + { + fis->d.sectorCount = 0xFF; /* FIS sector count (7:0) */ + } + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + + break; + case SAT_WRITE_SECTORS: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_SECTORS; /* 0x30 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (LBA[0] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->d.sectorCount = (bit8)Remainder; /* FIS sector count (7:0) */ + } + else + { + fis->d.sectorCount = 0xFF; /* FIS sector count (7:0) */ + } + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + + break; + case SAT_WRITE_DMA_EXT: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_DMA_EXT; /* 0x3D */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = LBA[0]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->d.sectorCount = (bit8)(Remainder & 0xFF); /* FIS sector count (7:0) */ + fis->d.sectorCountExp = (bit8)((Remainder & 0xFF00) >> 8); /* FIS sector count (15:8) */ + } + else + { + fis->d.sectorCount = 0xFF; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0xFF; /* FIS sector count (15:8) */ + } + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + + break; + case SAT_WRITE_SECTORS_EXT: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_SECTORS_EXT; /* 0x34 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = LBA[0]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->d.sectorCount = (bit8)(Remainder & 0xFF); /* FIS sector count (7:0) */ + fis->d.sectorCountExp = (bit8)((Remainder & 0xFF00) >> 8); /* FIS sector count (15:8) */ + } + else + { + fis->d.sectorCount = 0xFF; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0xFF; /* FIS sector count (15:8) */ + } + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + + break; + case SAT_WRITE_FPDMA_QUEUED: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_FPDMA_QUEUED; /* 0x61 */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + + /* Check FUA bit */ + if (scsiCmnd->cdb[1] & SCSI_WRITE10_FUA_MASK) + fis->d.device = 0xC0; /* FIS FUA set */ + else + fis->d.device = 0x40; /* FIS FUA clear */ + + fis->d.lbaLowExp = LBA[0];; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->h.features = (bit8)(Remainder & 0xFF); /* FIS sector count (7:0) */ + fis->d.featuresExp = (bit8)((Remainder & 0xFF00) >> 8); /* FIS sector count (15:8) */ + } + else + { + fis->h.features = 0xFF; /* FIS sector count (7:0) */ + fis->d.featuresExp = 0xFF; /* FIS sector count (15:8) */ + } + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_WRITE; + break; + + default: + SM_DBG1(("satChainedWriteNVerify_Write: error incorrect ata command 0x%x!!!\n", satIOContext->ATACmd)); + return SM_RC_FAILURE; + break; + } + + /* Initialize CB for SATA completion. + */ + /* chained data */ + satIOContext->satCompleteCB = &smsatChainedWriteNVerifyCB; + + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + SM_DBG5(("satChainedWriteNVerify_Write: return\n")); + return (status); +} + +osGLOBAL bit32 +smsatChainedWriteNVerify_Verify( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status; + smSatIOContext_t *satOrgIOContext = agNULL; + agsaFisRegHostToDevice_t *fis; + bit32 agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + bit32 lba = 0; + bit32 DenomTL = 0xFF; + bit32 Remainder = 0; + bit8 LBA[4]; /* 0 MSB, 3 LSB */ + + SM_DBG2(("smsatChainedWriteNVerify_Verify: start\n")); + fis = satIOContext->pFis; + satOrgIOContext = satIOContext->satOrgIOContext; + sm_memset(LBA,0, sizeof(LBA)); + switch (satOrgIOContext->ATACmd) + { + case SAT_READ_VERIFY_SECTORS: + DenomTL = 0xFF; + break; + case SAT_READ_VERIFY_SECTORS_EXT: + DenomTL = 0xFFFF; + break; + default: + SM_DBG1(("smsatChainedWriteNVerify_Verify: error incorrect ata command 0x%x!!!\n", satIOContext->ATACmd)); + return SM_RC_FAILURE; + break; + } + + Remainder = satOrgIOContext->OrgTL % DenomTL; + satOrgIOContext->currentLBA = satOrgIOContext->currentLBA + DenomTL; + lba = satOrgIOContext->currentLBA; + + LBA[0] = (bit8)((lba & 0xF000) >> (8 * 3)); /* MSB */ + LBA[1] = (bit8)((lba & 0xF00) >> (8 * 2)); + LBA[2] = (bit8)((lba & 0xF0) >> 8); + LBA[3] = (bit8)(lba & 0xF); /* LSB */ + + switch (satOrgIOContext->ATACmd) + { + case SAT_READ_VERIFY_SECTORS: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS; /* 0x40 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (LBA[0] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->d.sectorCount = (bit8)Remainder; /* FIS sector count (7:0) */ + } + else + { + fis->d.sectorCount = 0xFF; /* FIS sector count (7:0) */ + } + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + break; + case SAT_READ_VERIFY_SECTORS_EXT: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS_EXT; /* 0x42 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = LBA[0]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->d.sectorCount = (bit8)(Remainder & 0xFF); /* FIS sector count (7:0) */ + fis->d.sectorCountExp = (bit8)((Remainder & 0xFF00) >> 8); /* FIS sector count (15:8) */ + } + else + { + fis->d.sectorCount = 0xFF; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0xFF; /* FIS sector count (15:8) */ + } + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + break; + + default: + SM_DBG1(("smsatChainedWriteNVerify_Verify: error incorrect ata command 0x%x!!!\n", satIOContext->ATACmd)); + return SM_RC_FAILURE; + break; + } + + /* Initialize CB for SATA completion. + */ + /* chained data */ + satIOContext->satCompleteCB = &smsatChainedWriteNVerifyCB; + + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + SM_DBG5(("smsatChainedWriteNVerify_Verify: return\n")); + return (status); +} + +osGLOBAL bit32 +smsatChainedVerify( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status; + smSatIOContext_t *satOrgIOContext = agNULL; + agsaFisRegHostToDevice_t *fis; + bit32 agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + bit32 lba = 0; + bit32 DenomTL = 0xFF; + bit32 Remainder = 0; + bit8 LBA[4]; /* 0 MSB, 3 LSB */ + + SM_DBG2(("smsatChainedVerify: start\n")); + fis = satIOContext->pFis; + satOrgIOContext = satIOContext->satOrgIOContext; + sm_memset(LBA,0, sizeof(LBA)); + switch (satOrgIOContext->ATACmd) + { + case SAT_READ_VERIFY_SECTORS: + DenomTL = 0xFF; + break; + case SAT_READ_VERIFY_SECTORS_EXT: + DenomTL = 0xFFFF; + break; + default: + SM_DBG1(("satChainedVerify: error incorrect ata command 0x%x!!!\n", satIOContext->ATACmd)); + return tiError; + break; + } + + Remainder = satOrgIOContext->OrgTL % DenomTL; + satOrgIOContext->currentLBA = satOrgIOContext->currentLBA + DenomTL; + lba = satOrgIOContext->currentLBA; + + LBA[0] = (bit8)((lba & 0xF000) >> (8 * 3)); /* MSB */ + LBA[1] = (bit8)((lba & 0xF00) >> (8 * 2)); + LBA[2] = (bit8)((lba & 0xF0) >> 8); + LBA[3] = (bit8)(lba & 0xF); /* LSB */ + + switch (satOrgIOContext->ATACmd) + { + case SAT_READ_VERIFY_SECTORS: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS; /* 0x40 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (LBA[0] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->d.sectorCount = (bit8)Remainder; /* FIS sector count (7:0) */ + } + else + { + fis->d.sectorCount = 0xFF; /* FIS sector count (7:0) */ + } + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + break; + case SAT_READ_VERIFY_SECTORS_EXT: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS_EXT; /* 0x42 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = LBA[0]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->d.sectorCount = (bit8)(Remainder & 0xFF); /* FIS sector count (7:0) */ + fis->d.sectorCountExp = (bit8)((Remainder & 0xFF00) >> 8); /* FIS sector count (15:8) */ + } + else + { + fis->d.sectorCount = 0xFF; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0xFF; /* FIS sector count (15:8) */ + } + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + break; + + default: + SM_DBG1(("satChainedVerify: error incorrect ata command 0x%x!!!\n", satIOContext->ATACmd)); + return tiError; + break; + } + + /* Initialize CB for SATA completion. + */ + /* chained data */ + satIOContext->satCompleteCB = &smsatChainedVerifyCB; + + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + SM_DBG5(("satChainedVerify: return\n")); + return (status); +} + +osGLOBAL bit32 +smsatWriteSame10_1( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext, + bit32 lba + ) +{ + /* + sends SAT_WRITE_DMA_EXT + */ + + bit32 status; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; + bit8 lba1, lba2 ,lba3, lba4; + + SM_DBG5(("smsatWriteSame10_1: start\n")); + fis = satIOContext->pFis; + /* MSB */ + lba1 = (bit8)((lba & 0xFF000000) >> (8*3)); + lba2 = (bit8)((lba & 0x00FF0000) >> (8*2)); + lba3 = (bit8)((lba & 0x0000FF00) >> (8*1)); + /* LSB */ + lba4 = (bit8)(lba & 0x000000FF); + /* SAT_WRITE_DMA_EXT */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_DMA_EXT; /* 0x35 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = lba4; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = lba3; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = lba2; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = lba1; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + /* one sector at a time */ + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatWriteSame10CB; + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + SM_DBG5(("smsatWriteSame10_1 return status %d\n", status)); + return status; +} + + +osGLOBAL bit32 +smsatWriteSame10_2( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext, + bit32 lba + ) +{ + /* + sends SAT_WRITE_SECTORS_EXT + */ + + bit32 status; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; + bit8 lba1, lba2 ,lba3, lba4; + + SM_DBG5(("smsatWriteSame10_2: start\n")); + fis = satIOContext->pFis; + /* MSB */ + lba1 = (bit8)((lba & 0xFF000000) >> (8*3)); + lba2 = (bit8)((lba & 0x00FF0000) >> (8*2)); + lba3 = (bit8)((lba & 0x0000FF00) >> (8*1)); + /* LSB */ + lba4 = (bit8)(lba & 0x000000FF); + /* SAT_WRITE_SECTORS_EXT */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_SECTORS_EXT; /* 0x34 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = lba4; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = lba3; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = lba2; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = lba1; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + /* one sector at a time */ + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatWriteSame10CB; + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + SM_DBG5(("smsatWriteSame10_2 return status %d\n", status)); + return status; +} + + +osGLOBAL bit32 +smsatWriteSame10_3( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext, + bit32 lba + ) +{ + /* + sends SAT_WRITE_FPDMA_QUEUED + */ + + bit32 status; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; + bit8 lba1, lba2 ,lba3, lba4; + + SM_DBG5(("smsatWriteSame10_3: start\n")); + fis = satIOContext->pFis; + /* MSB */ + lba1 = (bit8)((lba & 0xFF000000) >> (8*3)); + lba2 = (bit8)((lba & 0x00FF0000) >> (8*2)); + lba3 = (bit8)((lba & 0x0000FF00) >> (8*1)); + /* LSB */ + lba4 = (bit8)(lba & 0x000000FF); + + /* SAT_WRITE_FPDMA_QUEUED */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_FPDMA_QUEUED; /* 0x61 */ + + + /* one sector at a time */ + fis->h.features = 1; /* FIS sector count (7:0) */ + fis->d.featuresExp = 0; /* FIS sector count (15:8) */ + + fis->d.lbaLow = lba4; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = lba3; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = lba2; /* FIS LBA (23:16) */ + /* NO FUA bit in the WRITE SAME 10 */ + fis->d.device = 0x40; /* FIS FUA clear */ + fis->d.lbaLowExp = lba1; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_WRITE; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatWriteSame10CB; + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + SM_DBG5(("smsatWriteSame10_3 return status %d\n", status)); + return status; +} + +osGLOBAL bit32 +smsatStartStopUnit_1( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + /* + SAT Rev 8, Table 48, 9.11.3 p55 + sends STANDBY + */ + bit32 status; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; + + SM_DBG5(("smsatStartStopUnit_1: start\n")); + fis = satIOContext->pFis; + /* STANDBY */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_STANDBY; /* 0xE2 */ + fis->h.features = 0; /* FIS features NA */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.device = 0; /* 0 */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatStartStopUnitCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + SM_DBG5(("smsatStartStopUnit_1 return status %d\n", status)); + return status; +} + +osGLOBAL bit32 +smsatSendDiagnostic_1( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + /* + SAT Rev9, Table29, p41 + send 2nd SAT_READ_VERIFY_SECTORS(_EXT) + */ + bit32 status; + bit32 agRequestType; + smDeviceData_t *pSatDevData; + agsaFisRegHostToDevice_t *fis; + + SM_DBG5(("smsatSendDiagnostic_1: start\n")); + pSatDevData = satIOContext->pSatDevData; + fis = satIOContext->pFis; + /* + sector count 1, LBA MAX + */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + /* sends READ VERIFY SECTOR(S) EXT*/ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS_EXT;/* 0x42 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = pSatDevData->satMaxLBA[7]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = pSatDevData->satMaxLBA[6]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = pSatDevData->satMaxLBA[5]; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = pSatDevData->satMaxLBA[4]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = pSatDevData->satMaxLBA[3]; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = pSatDevData->satMaxLBA[2]; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.device = 0x40; /* 01000000 */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + } + else + { + /* READ VERIFY SECTOR(S)*/ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS;/* 0x40 */ + fis->h.features = 0; /* FIS features NA */ + fis->d.lbaLow = pSatDevData->satMaxLBA[7]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = pSatDevData->satMaxLBA[6]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = pSatDevData->satMaxLBA[5]; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.device = (bit8)((0x4 << 4) | (pSatDevData->satMaxLBA[4] & 0xF)); + /* DEV and LBA 27:24 */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + } + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatSendDiagnosticCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + + return status; +} + +osGLOBAL bit32 +smsatSendDiagnostic_2( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + /* + SAT Rev9, Table29, p41 + send 3rd SAT_READ_VERIFY_SECTORS(_EXT) + */ + bit32 status; + bit32 agRequestType; + smDeviceData_t *pSatDevData; + agsaFisRegHostToDevice_t *fis; + + SM_DBG5(("smsatSendDiagnostic_2: start\n")); + + pSatDevData = satIOContext->pSatDevData; + fis = satIOContext->pFis; + /* + sector count 1, LBA Random + */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + /* sends READ VERIFY SECTOR(S) EXT*/ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS_EXT;/* 0x42 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = 0x7F; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.device = 0x40; /* 01000000 */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + } + else + { + /* READ VERIFY SECTOR(S)*/ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS;/* 0x40 */ + fis->h.features = 0; /* FIS features NA */ + fis->d.lbaLow = 0x7F; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.device = 0x40; /* FIS LBA mode set 01000000 */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + } + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatSendDiagnosticCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + + return status; +} + +osGLOBAL bit32 +smsatModeSelect6n10_1( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + /* sends either ATA SET FEATURES based on DRA bit */ + bit32 status; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; + bit8 *pLogPage; /* Log Page data buffer */ + bit32 StartingIndex = 0; + + fis = satIOContext->pFis; + pLogPage = (bit8 *) smScsiRequest->sglVirtualAddr; + SM_DBG5(("smsatModeSelect6n10_1: start\n")); + + if (pLogPage[3] == 8) + { + /* mode parameter block descriptor exists */ + StartingIndex = 12; + } + else + { + /* mode parameter block descriptor does not exist */ + StartingIndex = 4; + } + + /* sends ATA SET FEATURES based on DRA bit */ + if ( !(pLogPage[StartingIndex + 12] & SCSI_MODE_SELECT6_DRA_MASK) ) + { + SM_DBG5(("smsatModeSelect6n10_1: enable read look-ahead feature\n")); + /* sends SET FEATURES */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_SET_FEATURES; /* 0xEF */ + fis->h.features = 0xAA; /* enable read look-ahead */ + fis->d.lbaLow = 0; /* */ + fis->d.lbaMid = 0; /* */ + fis->d.lbaHigh = 0; /* */ + fis->d.device = 0; /* */ + fis->d.lbaLowExp = 0; /* */ + fis->d.lbaMidExp = 0; /* */ + fis->d.lbaHighExp = 0; /* */ + fis->d.featuresExp = 0; /* */ + fis->d.sectorCount = 0; /* */ + fis->d.sectorCountExp = 0; /* */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatModeSelect6n10CB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + return status; + } + else + { + SM_DBG5(("smsatModeSelect6n10_1: disable read look-ahead feature\n")); + /* sends SET FEATURES */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_SET_FEATURES; /* 0xEF */ + fis->h.features = 0x55; /* disable read look-ahead */ + fis->d.lbaLow = 0; /* */ + fis->d.lbaMid = 0; /* */ + fis->d.lbaHigh = 0; /* */ + fis->d.device = 0; /* */ + fis->d.lbaLowExp = 0; /* */ + fis->d.lbaMidExp = 0; /* */ + fis->d.lbaHighExp = 0; /* */ + fis->d.featuresExp = 0; /* */ + fis->d.sectorCount = 0; /* */ + fis->d.sectorCountExp = 0; /* */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatModeSelect6n10CB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + return status; + } +} + + +osGLOBAL bit32 +smsatLogSense_1( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status; + bit32 agRequestType; + smDeviceData_t *pSatDevData; + agsaFisRegHostToDevice_t *fis; + + pSatDevData = satIOContext->pSatDevData; + fis = satIOContext->pFis; + + SM_DBG5(("smsatLogSense_1: start\n")); + + /* SAT Rev 8, 10.2.4 p74 */ + if ( pSatDevData->sat48BitSupport == agTRUE ) + { + SM_DBG5(("smsatLogSense_1: case 2-1 sends READ LOG EXT\n")); + /* sends READ LOG EXT */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_READ_LOG_EXT; /* 0x2F */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = 0x07; /* 0x07 */ + fis->d.lbaMid = 0; /* */ + fis->d.lbaHigh = 0; /* */ + fis->d.device = 0; /* */ + fis->d.lbaLowExp = 0; /* */ + fis->d.lbaMidExp = 0; /* */ + fis->d.lbaHighExp = 0; /* */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 0x01; /* 1 sector counts */ + fis->d.sectorCountExp = 0x00; /* 1 sector counts */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatLogSenseCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + return status; + + } + else + { + SM_DBG5(("smsatLogSense_1: case 2-2 sends SMART READ LOG\n")); + /* sends SMART READ LOG */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_SMART; /* 0x2F */ + fis->h.features = SAT_SMART_READ_LOG; /* 0xd5 */ + fis->d.lbaLow = 0x06; /* 0x06 */ + fis->d.lbaMid = 0x00; /* 0x4f */ + fis->d.lbaHigh = 0x00; /* 0xc2 */ + fis->d.device = 0; /* */ + fis->d.lbaLowExp = 0; /* */ + fis->d.lbaMidExp = 0; /* */ + fis->d.lbaHighExp = 0; /* */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 0x01; /* */ + fis->d.sectorCountExp = 0x00; /* */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatLogSenseCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + return status; + + } +} + +osGLOBAL bit32 +smsatReassignBlocks_2( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext, + bit8 *LBA + ) +{ + /* + assumes all LBA fits in ATA command; no boundary condition is checked here yet + tiScsiRequest is TD generated for writing + */ + bit32 status; + bit32 agRequestType; + smDeviceData_t *pSatDevData; + smScsiRspSense_t *pSense; + agsaFisRegHostToDevice_t *fis; + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + fis = satIOContext->pFis; + SM_DBG5(("smsatReassignBlocks_2: start\n")); + + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 2 */ + /* WRITE DMA*/ + /* can't fit the transfer length */ + SM_DBG5(("smsatReassignBlocks_2: case 2\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_DMA; /* 0xCA */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[7]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[6]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[5]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (LBA[4] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_DMA; + } + else + { + /* case 1 */ + /* WRITE MULTIPLE or WRITE SECTOR(S) */ + /* WRITE SECTORS for easier implemetation */ + /* can't fit the transfer length */ + SM_DBG5(("smsatReassignBlocks_2: case 1\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_SECTORS; /* 0x30 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[7]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[6]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[7]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (LBA[4] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + satIOContext->ATACmd = SAT_WRITE_SECTORS; + } + + /* case 3 and 4 */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 3 */ + /* WRITE DMA EXT or WRITE DMA FUA EXT */ + SM_DBG5(("smsatReassignBlocks_2: case 3\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + /* SAT_WRITE_DMA_FUA_EXT is optional and we don't support it */ + fis->h.command = SAT_WRITE_DMA_EXT; /* 0x35 */ + satIOContext->ATACmd = SAT_WRITE_DMA_EXT; + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[7]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[6]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[5]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = LBA[4]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = LBA[3]; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = LBA[2]; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + } + else + { + /* case 4 */ + /* WRITE MULTIPLE EXT or WRITE MULTIPLE FUA EXT or WRITE SECTOR(S) EXT */ + /* WRITE SECTORS EXT for easier implemetation */ + SM_DBG5(("smsatReassignBlocks_2: case 4\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_SECTORS_EXT; /* 0x34 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[7]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[6]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[5]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = LBA[4]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = LBA[3]; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = LBA[2]; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + satIOContext->ATACmd = SAT_WRITE_SECTORS_EXT; + } + } + /* case 5 */ + if (pSatDevData->satNCQ == agTRUE) + { + /* WRITE FPDMA QUEUED */ + if (pSatDevData->sat48BitSupport != agTRUE) + { + SM_DBG5(("smsatReassignBlocks_2: case 5 !!! error NCQ but 28 bit address support \n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_HARDWARE_ERROR, + 0, + SCSI_SNSCODE_WRITE_ERROR_AUTO_REALLOCATION_FAILED, + satIOContext); + + /*smEnqueueIO(smRoot, satIOContext);*/ + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + return SM_RC_SUCCESS; + } + SM_DBG6(("satWrite10: case 5\n")); + + /* Support 48-bit FPDMA addressing, use WRITE FPDMA QUEUE command */ + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_FPDMA_QUEUED; /* 0x61 */ + fis->h.features = 1; /* FIS sector count (7:0) */ + fis->d.lbaLow = LBA[7]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[6]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[5]; /* FIS LBA (23:16) */ + + /* Check FUA bit */ + fis->d.device = 0x40; /* FIS FUA clear */ + + fis->d.lbaLowExp = LBA[4]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = LBA[3]; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = LBA[2]; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS sector count (15:8) */ + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_FPDMA_QUEUED; + } + + satIOContext->satCompleteCB = &smsatReassignBlocksCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + /* not the original, should be the TD generated one */ + smScsiRequest, + satIOContext); + return (status); +} + +osGLOBAL bit32 +smsatReassignBlocks_1( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext, + smSatIOContext_t *satOrgIOContext + ) +{ + /* + assumes all LBA fits in ATA command; no boundary condition is checked here yet + tiScsiRequest is OS generated; needs for accessing parameter list + */ + bit32 agRequestType; + smDeviceData_t *pSatDevData; + smIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit8 *pParmList; /* Log Page data buffer */ + bit8 LongLBA; + bit8 LBA[8]; + bit32 startingIndex; + + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &smScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + pParmList = (bit8 *) smScsiRequest->sglVirtualAddr; + SM_DBG5(("smsatReassignBlocks_1: start\n")); + LongLBA = (bit8)(scsiCmnd->cdb[1] & SCSI_REASSIGN_BLOCKS_LONGLBA_MASK); + sm_memset(LBA, 0, sizeof(LBA)); + startingIndex = satOrgIOContext->ParmIndex; + if (LongLBA == 0) + { + LBA[4] = pParmList[startingIndex]; + LBA[5] = pParmList[startingIndex+1]; + LBA[6] = pParmList[startingIndex+2]; + LBA[7] = pParmList[startingIndex+3]; + startingIndex = startingIndex + 4; + } + else + { + LBA[0] = pParmList[startingIndex]; + LBA[1] = pParmList[startingIndex+1]; + LBA[2] = pParmList[startingIndex+2]; + LBA[3] = pParmList[startingIndex+3]; + LBA[4] = pParmList[startingIndex+4]; + LBA[5] = pParmList[startingIndex+5]; + LBA[6] = pParmList[startingIndex+6]; + LBA[7] = pParmList[startingIndex+7]; + startingIndex = startingIndex + 8; + } + + if (pSatDevData->sat48BitSupport == agTRUE) + { + /* sends READ VERIFY SECTOR(S) EXT*/ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS_EXT;/* 0x42 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[7]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[6]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[5]; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = LBA[4]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = LBA[3]; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = LBA[2]; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.device = 0x40; /* 01000000 */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + } + else + { + /* READ VERIFY SECTOR(S)*/ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS;/* 0x40 */ + fis->h.features = 0; /* FIS features NA */ + fis->d.lbaLow = LBA[7]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[6]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[5]; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.device = (bit8)((0x4 << 4) | (LBA[4] & 0xF)); + /* DEV and LBA 27:24 */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + } + + sm_memcpy(satOrgIOContext->LBA, LBA, 8); + satOrgIOContext->ParmIndex = startingIndex; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatReassignBlocksCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + return SM_RC_SUCCESS; +} + +osGLOBAL bit32 +smsatSendReadLogExt( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; + + fis = satIOContext->pFis; + SM_DBG1(("smsatSendReadLogExt: start\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_LOG_EXT; /* 0x2F */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = 0x10; /* Page number */ + fis->d.lbaMid = 0; /* */ + fis->d.lbaHigh = 0; /* */ + fis->d.device = 0; /* DEV is ignored in SATA */ + fis->d.lbaLowExp = 0; /* */ + fis->d.lbaMidExp = 0; /* */ + fis->d.lbaHighExp = 0; /* */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 0x01; /* 1 sector counts*/ + fis->d.sectorCountExp = 0x00; /* 1 sector counts */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatReadLogExtCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + SM_DBG1(("smsatSendReadLogExt: end status %d!!!\n", status)); + + return (status); +} + +osGLOBAL bit32 +smsatCheckPowerMode( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + /* + sends SAT_CHECK_POWER_MODE as a part of ABORT TASKMANGEMENT for NCQ commands + internally generated - no directly corresponding scsi + */ + bit32 status; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; + + fis = satIOContext->pFis; + SM_DBG1(("smsatCheckPowerMode: start\n")); + /* + * Send the ATA CHECK POWER MODE command. + */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_CHECK_POWER_MODE; /* 0xE5 */ + fis->h.features = 0; + fis->d.lbaLow = 0; + fis->d.lbaMid = 0; + fis->d.lbaHigh = 0; + fis->d.device = 0; + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatCheckPowerModeCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + SM_DBG5(("smsatCheckPowerMode: return\n")); + + return status; +} + +osGLOBAL bit32 +smsatResetDevice( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, /* NULL */ + smSatIOContext_t *satIOContext + ) +{ + bit32 status; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; +#ifdef TD_DEBUG_ENABLE + smIORequestBody_t *smIORequestBody; + smSatInternalIo_t *satIntIoContext; +#endif + + fis = satIOContext->pFis; + SM_DBG1(("smsatResetDevice: start\n")); +#ifdef TD_DEBUG_ENABLE + satIntIoContext = satIOContext->satIntIoContext; + smIORequestBody = satIntIoContext->satIntRequestBody; +#endif + SM_DBG5(("smsatResetDevice: satIOContext %p smIORequestBody %p\n", satIOContext, smIORequestBody)); + /* any fis should work */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0; /* C Bit is not set */ + fis->h.command = 0; /* any command */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.device = 0; /* FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0x4; /* SRST bit is set */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_SRST_ASSERT; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatResetDeviceCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + +#ifdef SM_INTERNAL_DEBUG + smhexdump("smsatResetDevice", (bit8 *)satIOContext->pFis, sizeof(agsaFisRegHostToDevice_t)); +#ifdef TD_DEBUG_ENABLE + smhexdump("smsatResetDevice LL", (bit8 *)&(smIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev), sizeof(agsaFisRegHostToDevice_t)); +#endif +#endif + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + SM_DBG6(("smsatResetDevice: end status %d\n", status)); + return status; +} + +osGLOBAL bit32 +smsatDeResetDevice( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; +#ifdef TD_DEBUG_ENABLE + smIORequestBody_t *smIORequestBody; + smSatInternalIo_t *satIntIoContext; +#endif + + fis = satIOContext->pFis; + SM_DBG1(("smsatDeResetDevice: start\n")); +#ifdef TD_DEBUG_ENABLE + satIntIoContext = satIOContext->satIntIoContext; + smIORequestBody = satIntIoContext->satIntRequestBody; +#endif + SM_DBG5(("smsatDeResetDevice: satIOContext %p smIORequestBody %p\n", satIOContext, smIORequestBody)); + /* any fis should work */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0; /* C Bit is not set */ + fis->h.command = 0; /* any command */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.device = 0; /* FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* SRST bit is not set */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_SRST_DEASSERT; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatDeResetDeviceCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + +#ifdef SM_INTERNAL_DEBUG + smhexdump("smsatDeResetDevice", (bit8 *)satIOContext->pFis, sizeof(agsaFisRegHostToDevice_t)); +#ifdef TD_DEBUG_ENABLE + smhexdump("smsatDeResetDevice LL", (bit8 *)&(smIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev), sizeof(agsaFisRegHostToDevice_t)); +#endif +#endif + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + SM_DBG6(("smsatDeResetDevice: end status %d\n", status)); + return status; +} + +/* set feature for auto activate */ +osGLOBAL bit32 +smsatSetFeaturesAA( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status = SM_RC_FAILURE; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; + + fis = satIOContext->pFis; + SM_DBG2(("smsatSetFeaturesAA: start\n")); + /* + * Send the Set Features command. + * See SATA II 1.0a spec + */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_SET_FEATURES; /* 0xEF */ + fis->h.features = 0x10; /* enable SATA feature */ + fis->d.lbaLow = 0; + fis->d.lbaMid = 0; + fis->d.lbaHigh = 0; + fis->d.device = 0; + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0x02; /* DMA Setup FIS Auto-Activate */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatSetFeaturesAACB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + /* debugging code */ + if (smIORequest->tdData == smIORequest->smData) + { + SM_DBG1(("smsatSetFeaturesAA: incorrect smIORequest\n")); + } + SM_DBG2(("smsatSetFeatures: return\n")); + return status; +} + + +/* set feature for DMA transfer mode*/ +osGLOBAL bit32 +smsatSetFeaturesDMA( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status = SM_RC_FAILURE; + bit32 agRequestType; + smDeviceData_t *pSatDevData; + agsaFisRegHostToDevice_t *fis; + + pSatDevData = satIOContext->pSatDevData; + fis = satIOContext->pFis; + SM_DBG2(("smsatSetFeaturesDMA: start\n")); + /* + * Send the Set Features command. + * See SATA II 1.0a spec + */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_SET_FEATURES; /* 0xEF */ + fis->h.features = 0x03; /* enable ATA transfer mode */ + fis->d.lbaLow = 0; + fis->d.lbaMid = 0; + fis->d.lbaHigh = 0; + fis->d.device = 0; + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0x40 |(bit8)pSatDevData->satUltraDMAMode; /* enable Ultra DMA mode */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatSetFeaturesDMACB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + /* debugging code */ + if (smIORequest->tdData == smIORequest->smData) + { + SM_DBG1(("smsatSetFeaturesDMA: incorrect smIORequest\n")); + } + + SM_DBG2(("smsatSetFeaturesDMA: return\n")); + + return status; +} + +/* set feature for Read Look Ahead*/ +osGLOBAL bit32 +smsatSetFeaturesReadLookAhead( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status = SM_RC_FAILURE; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; + + fis = satIOContext->pFis; + SM_DBG2(("smsatSetFeaturesReadLookAhead: start\n")); + /* + * Send the Set Features command. + * See SATA II 1.0a spec + */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_SET_FEATURES; /* 0xEF */ + fis->h.features = 0xAA; /* Enable read look-ahead feature */ + fis->d.lbaLow = 0; + fis->d.lbaMid = 0; + fis->d.lbaHigh = 0; + fis->d.device = 0; + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatSetFeaturesReadLookAheadCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + + /* debugging code */ + if (smIORequest->tdData == smIORequest->smData) + { + SM_DBG1(("smsatSetFeaturesReadLookAhead: incorrect smIORequest\n")); + } + + SM_DBG2(("smsatSetFeaturesReadLookAhead: return\n")); + + return status; +} + +/* set feature for Volatile Write Cache*/ +osGLOBAL bit32 +smsatSetFeaturesVolatileWriteCache( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + bit32 status = SM_RC_FAILURE; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; + + fis = satIOContext->pFis; + SM_DBG2(("smsatSetFeaturesVolatileWriteCache: start\n")); + /* + * Send the Set Features command. + * See SATA II 1.0a spec + */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_SET_FEATURES; /* 0xEF */ + fis->h.features = 0x02; /* Enable Volatile Write Cache feature */ + fis->d.lbaLow = 0; + fis->d.lbaMid = 0; + fis->d.lbaHigh = 0; + fis->d.device = 0; + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &smsatSetFeaturesVolatileWriteCacheCB; + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = smsataLLIOStart( smRoot, + smIORequest, + smDeviceHandle, + smScsiRequest, + satIOContext); + /* debugging code */ + if (smIORequest->tdData == smIORequest->smData) + { + SM_DBG1(("smsatSetFeaturesVolatileWriteCache: incorrect smIORequest\n")); + } + SM_DBG2(("smsatSetFeaturesVolatileWriteCache: return\n")); + + return status; +} + + + +/******************************** start of utils ***********************************************************/ +osGLOBAL FORCEINLINE void +smsatBitSet(smRoot_t *smRoot, bit8 *data, bit32 index) +{ + data[index>>3] |= (1 << (index&7)); +} + +osGLOBAL FORCEINLINE void +smsatBitClear(smRoot_t *smRoot, bit8 *data, bit32 index) +{ + data[index>>3] &= ~(1 << (index&7)); +} + +osGLOBAL FORCEINLINE BOOLEAN +smsatBitTest(smRoot_t *smRoot, bit8 *data, bit32 index) +{ + return ( (BOOLEAN)((data[index>>3] & (1 << (index&7)) ) ? 1: 0)); +} + + +FORCEINLINE bit32 +smsatTagAlloc( + smRoot_t *smRoot, + smDeviceData_t *pSatDevData, + bit8 *pTag + ) +{ + bit32 retCode = agFALSE; + bit32 i; + + tdsmSingleThreadedEnter(smRoot, SM_NCQ_TAG_LOCK); + +#ifdef CCFLAG_OPTIMIZE_SAT_LOCK + + if (tdsmBitScanForward(smRoot, &i, ~(pSatDevData->freeSATAFDMATagBitmap))) + { + smsatBitSet(smRoot, (bit8*)&pSatDevData->freeSATAFDMATagBitmap, i); + *pTag = (bit8)i; + retCode = agTRUE; + } + +#else + + for ( i = 0; i < pSatDevData->satNCQMaxIO; i ++ ) + { + if ( 0 == smsatBitTest(smRoot, (bit8 *)&pSatDevData->freeSATAFDMATagBitmap, i) ) + { + smsatBitSet(smRoot, (bit8*)&pSatDevData->freeSATAFDMATagBitmap, i); + *pTag = (bit8) i; + retCode = agTRUE; + break; + } + } + +#endif + + tdsmSingleThreadedLeave(smRoot, SM_NCQ_TAG_LOCK); + + return retCode; +} + +FORCEINLINE bit32 +smsatTagRelease( + smRoot_t *smRoot, + smDeviceData_t *pSatDevData, + bit8 tag + ) +{ + bit32 retCode = agFALSE; + + if ( tag < pSatDevData->satNCQMaxIO ) + { + tdsmSingleThreadedEnter(smRoot, SM_NCQ_TAG_LOCK); + smsatBitClear(smRoot, (bit8 *)&pSatDevData->freeSATAFDMATagBitmap, (bit32)tag); + tdsmSingleThreadedLeave(smRoot, SM_NCQ_TAG_LOCK); + /*tdsmInterlockedAnd(smRoot, (volatile LONG *)(&pSatDevData->freeSATAFDMATagBitmap), ~(1 << (tag&31)));*/ + retCode = agTRUE; + } + else + { + SM_DBG1(("smsatTagRelease: tag %d >= satNCQMaxIO %d!!!!\n", tag, pSatDevData->satNCQMaxIO)); + } + return retCode; +} + + + +osGLOBAL bit32 +smsatComputeCDB10LBA(smSatIOContext_t *satIOContext) +{ + smIniScsiCmnd_t *scsiCmnd; + smScsiInitiatorRequest_t *smScsiRequest; + bit32 lba = 0; + + SM_DBG5(("smsatComputeCDB10LBA: start\n")); + smScsiRequest = satIOContext->smScsiXchg; + scsiCmnd = &(smScsiRequest->scsiCmnd); + + lba = (scsiCmnd->cdb[2] << (8*3)) + (scsiCmnd->cdb[3] << (8*2)) + + (scsiCmnd->cdb[4] << 8) + scsiCmnd->cdb[5]; + + return lba; +} + +osGLOBAL bit32 +smsatComputeCDB10TL(smSatIOContext_t *satIOContext) +{ + + smIniScsiCmnd_t *scsiCmnd; + smScsiInitiatorRequest_t *smScsiRequest; + bit32 tl = 0; + + SM_DBG5(("smsatComputeCDB10TL: start\n")); + smScsiRequest = satIOContext->smScsiXchg; + scsiCmnd = &(smScsiRequest->scsiCmnd); + + tl = (scsiCmnd->cdb[7] << 8) + scsiCmnd->cdb[8]; + return tl; +} + +osGLOBAL bit32 +smsatComputeCDB12LBA(smSatIOContext_t *satIOContext) +{ + smIniScsiCmnd_t *scsiCmnd; + smScsiInitiatorRequest_t *smScsiRequest; + bit32 lba = 0; + + SM_DBG5(("smsatComputeCDB12LBA: start\n")); + smScsiRequest = satIOContext->smScsiXchg; + scsiCmnd = &(smScsiRequest->scsiCmnd); + + lba = (scsiCmnd->cdb[2] << (8*3)) + (scsiCmnd->cdb[3] << (8*2)) + + (scsiCmnd->cdb[4] << 8) + scsiCmnd->cdb[5]; + + return lba; +} + +osGLOBAL bit32 +smsatComputeCDB12TL(smSatIOContext_t *satIOContext) +{ + + smIniScsiCmnd_t *scsiCmnd; + smScsiInitiatorRequest_t *smScsiRequest; + bit32 tl = 0; + + SM_DBG5(("smsatComputeCDB12TL: start\n")); + smScsiRequest = satIOContext->smScsiXchg; + scsiCmnd = &(smScsiRequest->scsiCmnd); + + tl = (scsiCmnd->cdb[6] << (8*3)) + (scsiCmnd->cdb[7] << (8*2)) + + (scsiCmnd->cdb[8] << 8) + scsiCmnd->cdb[9]; + return tl; +} + +/* + CBD16 has bit64 LBA + But it has to be less than (2^28 - 1) + Therefore, use last four bytes to compute LBA is OK +*/ +osGLOBAL bit32 +smsatComputeCDB16LBA(smSatIOContext_t *satIOContext) +{ + smIniScsiCmnd_t *scsiCmnd; + smScsiInitiatorRequest_t *smScsiRequest; + bit32 lba = 0; + + SM_DBG5(("smsatComputeCDB16LBA: start\n")); + smScsiRequest = satIOContext->smScsiXchg; + scsiCmnd = &(smScsiRequest->scsiCmnd); + + lba = (scsiCmnd->cdb[6] << (8*3)) + (scsiCmnd->cdb[7] << (8*2)) + + (scsiCmnd->cdb[8] << 8) + scsiCmnd->cdb[9]; + + return lba; +} + +osGLOBAL bit32 +smsatComputeCDB16TL(smSatIOContext_t *satIOContext) +{ + + smIniScsiCmnd_t *scsiCmnd; + smScsiInitiatorRequest_t *smScsiRequest; + bit32 tl = 0; + + SM_DBG5(("smsatComputeCDB16TL: start\n")); + smScsiRequest = satIOContext->smScsiXchg; + scsiCmnd = &(smScsiRequest->scsiCmnd); + + tl = (scsiCmnd->cdb[10] << (8*3)) + (scsiCmnd->cdb[11] << (8*2)) + + (scsiCmnd->cdb[12] << 8) + scsiCmnd->cdb[13]; + return tl; +} + +/* + (tl, denom) + tl can be upto bit32 because CDB16 has bit32 tl + Therefore, fine + either (tl, 0xFF) or (tl, 0xFFFF) +*/ +osGLOBAL FORCEINLINE bit32 +smsatComputeLoopNum(bit32 a, bit32 b) +{ + bit32 LoopNum = 0; + + SM_DBG5(("smsatComputeLoopNum: start\n")); + + if (a < b || a == 0) + { + LoopNum = 1; + } + else + { + if (a == b || a == 0) + { + LoopNum = a/b; + } + else + { + LoopNum = a/b + 1; + } + } + + return LoopNum; +} + +/* + Generic new function for checking + LBA itself, LBA+TL < SAT_TR_LBA_LIMIT or SAT_EXT_TR_LBA_LIMIT + and LBA+TL < Read Capacity Limit + flag: false - not 48BitSupport; true - 48BitSupport + returns TRUE when over the limit + +*/ +osGLOBAL FORCEINLINE bit32 +smsatCheckLimit(bit8 *lba, bit8 *tl, int flag, smDeviceData_t *pSatDevData) +{ + bit32 lbaCheck = agFALSE; + int i; + bit8 limit[8]; + bit32 rangeCheck = agFALSE; + bit16 ans[8]; // 0 MSB, 8 LSB + bit8 final_ans[9]; // 0 MSB, 9 LSB + bit8 Bit28max[8]; + bit8 Bit48max[8]; + bit32 ReadCapCheck = agFALSE; + bit32 ret; + + bit8 final_satMaxLBA[9]; + bit8 oneTL[8]; + bit8 temp_satMaxLBA[8]; // 0 MSB, 8 LSB + /* + check LBA + */ + if (flag == agFALSE) + { + /* limit is 0xF FF FF = 2^28 - 1 */ + limit[0] = 0x0; /* MSB */ + limit[1] = 0x0; + limit[2] = 0x0; + limit[3] = 0x0; + limit[4] = 0xF; + limit[5] = 0xFF; + limit[6] = 0xFF; + limit[7] = 0xFF; /* LSB */ + } + else + { + /* limit is 0xF FF FF = 2^48 - 1 */ + limit[0] = 0x0; /* MSB */ + limit[1] = 0x0; + limit[2] = 0xFF; + limit[3] = 0xFF; + limit[4] = 0xFF; + limit[5] = 0xFF; + limit[6] = 0xFF; + limit[7] = 0xFF; /* LSB */ + } + //compare lba to limit + for(i=0;i<8;i++) + { + if (lba[i] > limit[i]) + { + SM_DBG1(("smsatCheckLimit: LBA check True at %d\n", i)); + lbaCheck = agTRUE; + break; + } + else if (lba[i] < limit[i]) + { + SM_DBG5(("smsatCheckLimit: LBA check False at %d\n", i)); + lbaCheck = agFALSE; + break; + } + else + { + continue; + } + } + + if (lbaCheck == agTRUE) + { + SM_DBG1(("smsatCheckLimit: return LBA check True\n")); + return agTRUE; + } + + /* + check LBA+TL < SAT_TR_LBA_LIMIT or SAT_EXT_TR_LBA_LIMIT + */ + sm_memset(ans, 0, sizeof(ans)); + sm_memset(final_ans, 0, sizeof(final_ans)); + + // adding from LSB to MSB + for(i=7;i>=0;i--) + { + ans[i] = (bit16)(lba[i] + tl[i]); + if (i != 7) + { + ans[i] = (bit16)(ans[i] + ((ans[i+1] & 0xFF00) >> 8)); + } + } + + /* + filling in the final answer + */ + final_ans[0] = (bit8)(((ans[0] & 0xFF00) >> 8)); + + for(i=1;i<=8;i++) + { + final_ans[i] = (bit8)(ans[i-1] & 0xFF); + } + + + if (flag == agFALSE) + { + sm_memset(Bit28max, 0, sizeof(Bit28max)); + Bit28max[4] = 0x10; // max =0x1000 0000 + + //compare final_ans to max + if (final_ans[0] != 0 || final_ans[1] != 0 || final_ans[2] != 0 + || final_ans[3] != 0 || final_ans[4] != 0) + { + SM_DBG1(("smsatCheckLimit: before 28Bit addressing TRUE\n")); + rangeCheck = agTRUE; + } + else + { + for(i=5;i<=8;i++) + { + if (final_ans[i] > Bit28max[i-1]) + { + SM_DBG1(("smsatCheckLimit: 28Bit addressing TRUE at %d\n", i)); + rangeCheck = agTRUE; + break; + } + else if (final_ans[i] < Bit28max[i-1]) + { + SM_DBG5(("smsatCheckLimit: 28Bit addressing FALSE at %d\n", i)); + rangeCheck = agFALSE; + break; + } + else + { + continue; + } + } + } + } + else + { + sm_memset(Bit48max, 0, sizeof(Bit48max)); + Bit48max[1] = 0x1; //max = 0x1 0000 0000 0000 + + //compare final_ans to max + if (final_ans[0] != 0 || final_ans[1] != 0) + { + SM_DBG1(("smsatCheckLimit: before 48Bit addressing TRUE\n")); + rangeCheck = agTRUE; + } + else + { + for(i=2;i<=8;i++) + { + if (final_ans[i] > Bit48max[i-1]) + { + SM_DBG1(("smsatCheckLimit: 48Bit addressing TRUE at %d\n", i)); + rangeCheck = agTRUE; + break; + } + else if (final_ans[i] < Bit48max[i-1]) + { + SM_DBG5(("smsatCheckLimit: 48Bit addressing FALSE at %d\n", i)); + rangeCheck = agFALSE; + break; + } + else + { + continue; + } + } + } + } + if (rangeCheck == agTRUE) + { + SM_DBG1(("smsatCheckLimit: return rangeCheck True\n")); + return agTRUE; + } + + /* + LBA+TL < Read Capacity Limit + */ + sm_memset(temp_satMaxLBA, 0, sizeof(temp_satMaxLBA)); + sm_memset(oneTL, 0, sizeof(oneTL)); + sm_memset(final_satMaxLBA, 0, sizeof(final_satMaxLBA)); + sm_memset(ans, 0, sizeof(ans)); + + sm_memcpy(&temp_satMaxLBA, &pSatDevData->satMaxLBA, sizeof(temp_satMaxLBA)); + oneTL[7] = 1; + + // adding temp_satMaxLBA to oneTL + for(i=7;i>=0;i--) + { + ans[i] = (bit16)(temp_satMaxLBA[i] + oneTL[i]); + if (i != 7) + { + ans[i] = (bit16)(ans[i] + ((ans[i+1] & 0xFF00) >> 8)); + } + } + + /* + filling in the final answer + */ + final_satMaxLBA[0] = (bit8)(((ans[0] & 0xFF00) >> 8)); + + for(i=1;i<=8;i++) + { + final_satMaxLBA[i] = (bit8)(ans[i-1] & 0xFF); + } + if ( pSatDevData->ReadCapacity == 10) + { + for (i=0;i<=8;i++) + { + if (final_ans[i] > final_satMaxLBA[i]) + { + SM_DBG1(("smsatCheckLimit: Read Capacity 10 TRUE at %d\n", i)); + ReadCapCheck = agTRUE; + break; + } + else if (final_ans[i] < final_satMaxLBA[i]) + { + SM_DBG5(("smsatCheckLimit: Read Capacity 10 FALSE at %d\n", i)); + ReadCapCheck = agFALSE; + break; + } + else + { + continue; + } + } + if ( ReadCapCheck) + { + SM_DBG1(("smsatCheckLimit: after Read Capacity 10 TRUE\n")); + } + else + { + SM_DBG5(("smsatCheckLimit: after Read Capacity 10 FALSE\n")); + } + } + else if ( pSatDevData->ReadCapacity == 16) + { + for (i=0;i<=8;i++) + { + if (final_ans[i] > final_satMaxLBA[i]) + { + SM_DBG1(("smsatCheckLimit: Read Capacity 16 TRUE at %d\n", i)); + ReadCapCheck = agTRUE; + break; + } + else if (final_ans[i] < final_satMaxLBA[i]) + { + SM_DBG5(("smsatCheckLimit: Read Capacity 16 FALSE at %d\n", i)); + ReadCapCheck = agFALSE; + break; + } + else + { + continue; + } + } + if ( ReadCapCheck) + { + SM_DBG1(("smsatCheckLimit: after Read Capacity 16 TRUE\n")); + } + else + { + SM_DBG5(("smsatCheckLimit: after Read Capacity 16 FALSE\n")); + } + } + else + { + SM_DBG5(("smsatCheckLimit: unknown pSatDevData->ReadCapacity %d\n", pSatDevData->ReadCapacity)); + } + + if (ReadCapCheck == agTRUE) + { + SM_DBG1(("smsatCheckLimit: return ReadCapCheck True\n")); + return agTRUE; + } + + + ret = (lbaCheck | rangeCheck | ReadCapCheck); + if (ret == agTRUE) + { + SM_DBG1(("smsatCheckLimit: final check TRUE\n")); + } + else + { + SM_DBG5(("smsatCheckLimit: final check FALSE\n")); + } + return ret; +} + + + +osGLOBAL void +smsatPrintSgl( + smRoot_t *smRoot, + agsaEsgl_t *agEsgl, + bit32 idx + ) +{ + bit32 i=0; +#ifdef TD_DEBUG_ENABLE + agsaSgl_t *agSgl; +#endif + + for (i=0;idescriptor[i]); +#endif + SM_DBG3(("smsatPrintSgl: agSgl %d upperAddr 0x%08x lowerAddr 0x%08x len 0x%08x ext 0x%08x\n", + i, agSgl->sgUpper, agSgl->sgLower, agSgl->len, agSgl->extReserved)); + } + + return; +} + + +osGLOBAL void +smsatSplitSGL( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext, + bit32 split, /*in sector number, depeding on IO value */ + bit32 tl, /* in sector number */ + bit32 flag + ) +{ + agsaSgl_t *agSgl; + agsaEsgl_t *agEsgl; + bit32 i=0; + smIniScsiCmnd_t *scsiCmnd; + bit32 totalLen=0; /* in bytes */ + bit32 splitLen=0; /* in bytes */ + bit32 splitDiffByte = 0; /* in bytes */ + bit32 splitDiffExtra = 0; /* in bytes */ + bit32 splitIdx = 0; + bit32 UpperAddr, LowerAddr; + bit32 tmpLowerAddr; + void *sglVirtualAddr; + void *sglSplitVirtualAddr; + + scsiCmnd = &smScsiRequest->scsiCmnd; + SM_DBG3(("smsatSplitSGL: start\n")); + + if (smScsiRequest->smSgl1.type == 0x80000000) /* esgl */ + { + if (flag == agFALSE) + { + SM_DBG3(("smsatSplitSGL: Not first time\n")); + SM_DBG3(("smsatSplitSGL: UpperAddr 0x%08x LowerAddr 0x%08x\n", satIOContext->UpperAddr, satIOContext->LowerAddr)); + SM_DBG3(("smsatSplitSGL: SplitIdx %d AdjustBytes 0x%08x\n", satIOContext->SplitIdx, satIOContext->AdjustBytes)); + + sglVirtualAddr = smScsiRequest->sglVirtualAddr; + + agEsgl = (agsaEsgl_t *)smScsiRequest->sglVirtualAddr; + + sglSplitVirtualAddr = &(agEsgl->descriptor[satIOContext->SplitIdx]); + + agEsgl = (agsaEsgl_t *)sglSplitVirtualAddr; + + if (agEsgl == agNULL) + { + SM_DBG1(("smsatSplitSGL: error!\n")); + return; + } + /* first sgl ajustment */ + agSgl = &(agEsgl->descriptor[0]); + agSgl->sgUpper = satIOContext->UpperAddr; + agSgl->sgLower = satIOContext->LowerAddr; + agSgl->len = satIOContext->AdjustBytes; + sm_memcpy(sglVirtualAddr, sglSplitVirtualAddr, (satIOContext->EsglLen) * sizeof(agsaSgl_t)); + agEsgl = (agsaEsgl_t *)smScsiRequest->sglVirtualAddr; + smsatPrintSgl(smRoot, (agsaEsgl_t *)sglVirtualAddr, satIOContext->EsglLen); + } + else + { + /* first time */ + SM_DBG3(("smsatSplitSGL: first time\n")); + satIOContext->EsglLen = smScsiRequest->smSgl1.len; + agEsgl = (agsaEsgl_t *)smScsiRequest->sglVirtualAddr; + if (agEsgl == agNULL) + { + return; + } + smsatPrintSgl(smRoot, agEsgl, satIOContext->EsglLen); + } + + if (tl > split) + { + /* split */ + SM_DBG3(("smsatSplitSGL: split case\n")); + i = 0; + while (1) + { + agSgl = &(agEsgl->descriptor[i]); + splitLen = splitLen + agSgl->len; + if (splitLen >= split) + { + splitDiffExtra = splitLen - split; + splitDiffByte = agSgl->len - splitDiffExtra; + splitIdx = i; + break; + } + i++; + } + SM_DBG3(("smsatSplitSGL: splitIdx %d\n", splitIdx)); + SM_DBG3(("smsatSplitSGL: splitDiffByte 0x%8x\n", splitDiffByte)); + SM_DBG3(("smsatSplitSGL: splitDiffExtra 0x%8x \n", splitDiffExtra)); + + + agSgl = &(agEsgl->descriptor[splitIdx]); + UpperAddr = agSgl->sgUpper; + LowerAddr = agSgl->sgLower; + tmpLowerAddr = LowerAddr + splitDiffByte; + if (tmpLowerAddr < LowerAddr) + { + UpperAddr = UpperAddr + 1; + } + SM_DBG3(("smsatSplitSGL: UpperAddr 0x%08x tmpLowerAddr 0x%08x\n", UpperAddr, tmpLowerAddr)); + agSgl->len = splitDiffByte; + /* Esgl len adjustment */ + smScsiRequest->smSgl1.len = splitIdx; + /* expected data lent adjustment */ + scsiCmnd->expDataLength = 0x20000; + /* remeber for the next round */ + satIOContext->UpperAddr = UpperAddr; + satIOContext->LowerAddr = tmpLowerAddr; + satIOContext->SplitIdx = splitIdx; + satIOContext->AdjustBytes = splitDiffExtra; + satIOContext->EsglLen = satIOContext->EsglLen - smScsiRequest->smSgl1.len; + satIOContext->OrgTL = satIOContext->OrgTL - 0x100; +// smsatPrintSgl(smRoot, agEsgl, satIOContext->EsglLen); + + } + else + { + /* no split */ + SM_DBG3(("smsatSplitSGL: no split case\n")); + /* Esgl len adjustment */ + smScsiRequest->smSgl1.len = satIOContext->EsglLen; + for (i=0;i< smScsiRequest->smSgl1.len;i++) + { + agSgl = &(agEsgl->descriptor[i]); + totalLen = totalLen + (agSgl->len); + } + /* expected data lent adjustment */ + scsiCmnd->expDataLength = totalLen; +// smsatPrintSgl(smRoot, agEsgl, satIOContext->EsglLen); + } + } + else + { + SM_DBG1(("not exntened esgl\n")); + + } + + return; +} + + +/******************************** end of utils ***********************************************************/ + + + diff --git a/sys/dev/pms/RefTisa/sat/src/smsatcb.c b/sys/dev/pms/RefTisa/sat/src/smsatcb.c new file mode 100644 index 000000000000..99894c84ab1f --- /dev/null +++ b/sys/dev/pms/RefTisa/sat/src/smsatcb.c @@ -0,0 +1,13769 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#include +#include + +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +extern smRoot_t *gsmRoot; + +/******************************** completion ***********************************************************/ + +FORCEINLINE void +smllSATACompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + void *agFirstDword, + bit32 agIOInfoLen, + void *agParam + ) +{ + smRoot_t *smRoot = agNULL; +// smIntRoot_t *smIntRoot = agNULL; +// smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smSatIOContext_t *satIOContext; + smDeviceData_t *pSatDevData; + smDeviceHandle_t *smDeviceHandle = agNULL; + smDeviceData_t *oneDeviceData = agNULL; + + SM_DBG2(("smllSATACompleted: start\n")); + + if (agIORequest == agNULL) + { + SM_DBG1(("smllSATACompleted: agIORequest is NULL!!!\n")); + return; + } + + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + + if (smIORequestBody == agNULL) + { + SM_DBG1(("smllSATACompleted: smIORequestBody is NULL!!!\n")); + return; + } + + /* for debugging */ + if (smIORequestBody->ioCompleted == agTRUE) + { + smDeviceHandle = smIORequestBody->smDevHandle; + if (smDeviceHandle == agNULL) + { + SM_DBG1(("smllSATACompleted: smDeviceHandle is NULL!!!\n")); + return; + } + oneDeviceData = (smDeviceData_t *)smDeviceHandle->smData; + SM_DBG1(("smllSATACompleted: Error!!!!!! double completion!!!, ID %d!!!\n", smIORequestBody->id)); + if (oneDeviceData == agNULL) + { + SM_DBG1(("smllSATACompleted: oneDeviceData is NULL!!!\n")); + return; + } + SM_DBG1(("smllSATACompleted: did %d!!!\n", oneDeviceData->id)); + return; + } + + smIORequestBody->ioCompleted = agTRUE; + satIOContext = &(smIORequestBody->transport.SATA.satIOContext); + + if (satIOContext == agNULL) + { + SM_DBG1(("smllSATACompleted: satIOContext is NULL!!!\n")); + return; + } + + pSatDevData = satIOContext->pSatDevData; + + if (pSatDevData == agNULL) + { + SM_DBG1(("smllSATACompleted: pSatDevData is NULL loc 1, wrong!!!\n")); + if (satIOContext->satIntIoContext == agNULL) + { + SM_DBG1(("smllSATACompleted: external command!!!\n")); + } + else + { + SM_DBG1(("smllSATACompleted: internal command!!!\n")); + } + return; + } + + smDeviceHandle = smIORequestBody->smDevHandle; + + if (smDeviceHandle == agNULL) + { + SM_DBG1(("smllSATACompleted: smDeviceHandle is NULL!!!!\n")); + return; + } + + oneDeviceData = (smDeviceData_t *)smDeviceHandle->smData; + + if (oneDeviceData != pSatDevData) + { + SM_DBG1(("smllSATACompleted: diff device handle!!!\n")); + if (satIOContext->satIntIoContext == agNULL) + { + SM_DBG1(("smllSATACompleted: external command!!!\n")); + } + else + { + SM_DBG1(("smllSATACompleted: internal command!!!\n")); + } + return; + } + + if (oneDeviceData == agNULL) + { + SM_DBG1(("smllSATACompleted: oneDeviceData is NULL!!!!\n")); + if (satIOContext->satIntIoContext == agNULL) + { + SM_DBG1(("smllSATACompleted: external command!!!\n")); + } + else + { + SM_DBG1(("smllSATACompleted: internal command!!!\n")); + } + return; + } + + smRoot = oneDeviceData->smRoot; + + /* release tag value for SATA */ + if ( (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_WRITE) || + (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_READ) ) + { + smsatTagRelease(smRoot, pSatDevData, satIOContext->sataTag); + SM_DBG3(("smllSATACompleted: ncq tag 0x%x\n",satIOContext->sataTag)); + } + + /* just for debugging */ + if (agIOStatus == OSSA_IO_DS_NON_OPERATIONAL) + { + SM_DBG1(("smllSATACompleted: agIOStatus is OSSA_IO_DS_NON_OPERATIONAL!!!\n")); + } + if (agIOStatus == OSSA_IO_DS_IN_RECOVERY) + { + SM_DBG1(("smllSATACompleted: agIOStatus is OSSA_IO_DS_IN_RECOVERY!!!\n")); + } + if (agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS) + { + SM_DBG1(("smllSATACompleted: agIOStatus is OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS!!!\n")); + } + + satIOContext->satCompleteCB( agRoot, + agIORequest, + agIOStatus, + agFirstDword, + agIOInfoLen, + agParam, + satIOContext); + + + + return; +} +/***************************************************************************** +*! \brief smsatPacketCB +* +* This routine is a callback function called from smllSATACompleted(). +* This CB routine deals with normal Packet command I/O SATA request. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to smSatIOContext_t. +* +* \return: none +* +*****************************************************************************/ + +osGLOBAL void +smsatPacketCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smIORequestBody_t *smOrgIORequestBody; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatIOContext_t *satNewIOContext; + smSatInternalIo_t *satIntIo; + smSatInternalIo_t *satNewIntIo = agNULL; + smDeviceData_t *oneDeviceData; + bit32 interruptContext; + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + smIORequest_t *smOrgIORequest; +// bit32 ataStatus = 0; +// bit32 ataError; + + bit32 status = SM_RC_SUCCESS; +// agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; +// bit32 dataLength; + bit8 bSenseKey = 0; + bit16 bSenseCodeInfo = 0; + + SM_DBG3(("smsatPacketCB: start\n")); + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + if (satIOContext == agNULL) + { + SM_DBG1(("smsatPacketCB: satIOContext is NULL\n")); + return; + } + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + interruptContext = satIOContext->interruptContext; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + + if (satIntIo == agNULL) + { + SM_DBG5(("smsatPacketCB: External smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + smOrgIORequest = smIORequestBody->smIORequest; + pSense = satIOContext->pSense; + scsiCmnd = satIOContext->pScsiCmnd; + } + else + { + SM_DBG5(("smsatPacketCB: Internal smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + smOrgIORequest = (smIORequest_t *)smOrgIORequestBody->smIORequest; + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + + /* interal structure free */ + smsatFreeIntIoResource( smRoot, oneDeviceData, satIntIo); + if( agIOStatus == OSSA_IO_SUCCESS && agIOInfoLen == 0 && agFirstDword == agNULL) + { + SM_DBG3(("smsatPacketCB: First, agIOStatus == OSSA_IO_SUCCESS, agFirstDword == agNULL, agIOInfoLen = %d\n", agIOInfoLen)); + tdsmIOCompletedCB(smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + interruptContext); + } + else if (agIOStatus == OSSA_IO_SUCCESS && !(agIOInfoLen == 0 && agFirstDword == agNULL)) + { + SM_DBG2(("smsatPacketCB: Second, agIOStatus == OSSA_IO_SUCCESS , agFirstDword %p agIOInfoLen = %d\n", agFirstDword, agIOInfoLen)); + /*The SCSI command status is error, need to send REQUEST SENSE for getting more sense information*/ + satNewIntIo = smsatAllocIntIoResource( smRoot, + smOrgIORequest, + oneDeviceData, + SENSE_DATA_LENGTH, + satNewIntIo); + if (satNewIntIo == agNULL) + { + /* memory allocation failure */ + /* just translate the ATAPI error register to sense information */ + smsatTranslateATAPIErrorsToSCSIErrors( + scsiCmnd->cdb[0], + agFirstDword->D2H.status, + agFirstDword->D2H.error, + &bSenseKey, + &bSenseCodeInfo + ); + smsatSetSensePayload(pSense, bSenseKey, 0, bSenseCodeInfo, satOrgIOContext); + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + interruptContext); + SM_DBG1(("smsatPacketCB: momory allocation fails\n")); + return; + } /* end memory allocation */ + + satNewIOContext = smsatPrepareNewIO(satNewIntIo, + smOrgIORequest, + oneDeviceData, + scsiCmnd, + satOrgIOContext + ); + /* sends request sense to ATAPI device for acquiring sense information */ + status = smsatRequestSenseForATAPI(smRoot, + &satNewIntIo->satIntSmIORequest, + satNewIOContext->psmDeviceHandle, + &satNewIntIo->satIntSmScsiXchg, + satNewIOContext + ); + if (status != SM_RC_SUCCESS) + { + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satNewIntIo); + /* just translate the ATAPI error register to sense information */ + smsatTranslateATAPIErrorsToSCSIErrors( + scsiCmnd->cdb[0], + agFirstDword->D2H.status, + agFirstDword->D2H.error, + &bSenseKey, + &bSenseCodeInfo + ); + smsatSetSensePayload(pSense, bSenseKey, 0, bSenseCodeInfo, satOrgIOContext); + tdsmIOCompletedCB(smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + interruptContext); + SM_DBG1(("smsatPacketCB: failed to call satRequestSenseForATAPI()\n")); + } + } + else if (agIOStatus != OSSA_IO_SUCCESS ) + { + SM_DBG2(("smsatPacketCB: agIOStatus != OSSA_IO_SUCCESS, status %d\n", agIOStatus)); + smsatProcessAbnormalCompletion( + agRoot, + agIORequest, + agIOStatus, + agFirstDword, + agIOInfoLen, + agParam, + satIOContext); + } + else + { + SM_DBG1(("smsatPacketCB: Unknown error \n")); + tdsmIOCompletedCB(smRoot, + smOrgIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + } +} +/***************************************************************************** +*! \brief smsatRequestSenseForATAPICB +* +* This routine is a callback function called from smllSATACompleted(). +* This CB routine deals with normal non-chained data I/O SATA request. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to smSatIOContext_t. +* +* \return: none +* +*****************************************************************************/ +osGLOBAL void +smsatRequestSenseForATAPICB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smIORequestBody_t *smOrgIORequestBody; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; +// smSatIOContext_t *satNewIOContext; + smSatInternalIo_t *satIntIo; +// smSatInternalIo_t *satNewIntIo = agNULL; + smDeviceData_t *oneDeviceData; + bit32 interruptContext; + bit8 dataLength; + smIniScsiCmnd_t *scsiCmnd; + smIORequest_t *smOrgIORequest; + + SM_DBG3(("smsatRequestSenseForATAPICB: start\n")); + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + if (satIOContext == agNULL) + { + SM_DBG1(("smsatRequestSenseForATAPICB: satIOContext is NULL\n")); + return; + } + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + interruptContext = satIOContext->interruptContext; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + if (satIntIo == agNULL) + { + SM_DBG5(("smsatRequestSenseForATAPICB: External smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + smOrgIORequest = smIORequestBody->smIORequest; + scsiCmnd = satIOContext->pScsiCmnd; + } + else + { + SM_DBG5(("smsatRequestSenseForATAPICB: Internal smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + smOrgIORequest = (smIORequest_t *)smOrgIORequestBody->smIORequest; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + if ( (agIOStatus == OSSA_IO_SUCCESS && agIOInfoLen == 0 && agFirstDword == agNULL)) + { + /* copy the request sense buffer to original IO buffer*/ + if (satIntIo) + { + sm_memcpy(satOrgIOContext->pSmSenseData->senseData, satIntIo->satIntDmaMem.virtPtr, SENSE_DATA_LENGTH); + } + satOrgIOContext->pSmSenseData->senseLen = SENSE_DATA_LENGTH; + /* interal structure free */ + smsatFreeIntIoResource( smRoot, oneDeviceData, satIntIo); + + /* notify the OS to complete this SRB */ + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + interruptContext); + } + else if (agIOStatus == OSSA_IO_UNDERFLOW ) + { + /* copy the request sense buffer to original IO buffer*/ + SM_DBG1(("smsatRequestSenseForATAPICB: OSSA_IO_UNDERFLOW agIOInfoLen = %d\n", agIOInfoLen)); + dataLength = (bit8)(scsiCmnd->expDataLength - agIOInfoLen); + if (satIntIo) + { + sm_memcpy(satOrgIOContext->pSmSenseData->senseData, satIntIo->satIntDmaMem.virtPtr, dataLength); + } + satOrgIOContext->pSmSenseData->senseLen = dataLength; + /* interal structure free */ + smsatFreeIntIoResource( smRoot, oneDeviceData, satIntIo); + + /* notify the OS to complete this SRB */ + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + interruptContext); + } + else + { + SM_DBG1(("smsatRequestSenseForATAPICB: failed, agIOStatus error = 0x%x agIOInfoLen = %d\n", agIOStatus, agIOInfoLen)); + /* interal structure free */ + smsatFreeIntIoResource( smRoot, oneDeviceData, satIntIo); + + /* notify the OS to complete this SRB */ + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + } + SM_DBG3(("smsatRequestSenseForATAPICB: end\n")); +} + +/***************************************************************************** +*! \brief smsatSetFeaturesPIOCB +* +* This routine is a callback function called from smllSATACompleted(). +* This CB routine deals with normal non-chained data I/O SATA request. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to smSatIOContext_t. +* +* \return: none +* +*****************************************************************************/ +osGLOBAL void +smsatSetFeaturesPIOCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smIORequestBody_t *smOrgIORequestBody = agNULL; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatIOContext_t *satNewIOContext; + smSatInternalIo_t *satIntIo; + smSatInternalIo_t *satNewIntIo = agNULL; + smDeviceData_t *oneDeviceData; + smIniScsiCmnd_t *scsiCmnd; + smIORequest_t *smOrgIORequest; + smDeviceHandle_t *smDeviceHandle; + bit32 status = SM_RC_FAILURE; + smIORequest_t *smIORequest; + + SM_DBG2(("smsatSetFeaturesPIOCB: start\n")); + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + if (satIOContext == agNULL) + { + SM_DBG1(("smsatSetFeaturesPIOCB: satIOContext is NULL\n")); + return; + } + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + smDeviceHandle = satIOContext->psmDeviceHandle; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + if (satIntIo == agNULL) + { + SM_DBG2(("smsatSetFeaturesPIOCB: External smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + smOrgIORequest = smIORequestBody->smIORequest; + scsiCmnd = satIOContext->pScsiCmnd; + } + else + { + SM_DBG2(("smsatSetFeaturesPIOCB: Internal smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + smOrgIORequest = (smIORequest_t *)smOrgIORequestBody->smIORequest; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + smIORequest = smOrgIORequestBody->smIORequest; + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + /* interal structure free */ + smsatFreeIntIoResource(smRoot, + oneDeviceData, + satIntIo); + if (smIORequest->tdData == smIORequest->smData) + { + SM_DBG1(("smsatSetFeaturesPIOCB: the same tdData and smData error!\n")); + } + /* check the agIOStatus */ + if (agIOStatus == OSSA_IO_ABORTED || + agIOStatus == OSSA_IO_NO_DEVICE || + agIOStatus == OSSA_IO_PORT_IN_RESET || + agIOStatus == OSSA_IO_DS_NON_OPERATIONAL || + agIOStatus == OSSA_IO_DS_IN_RECOVERY || + agIOStatus == OSSA_IO_DS_IN_ERROR || + agIOStatus == OSSA_IO_DS_INVALID + ) + { + SM_DBG1(("smsatSetFeaturesPIOCB: error status 0x%x\n", agIOStatus)); + SM_DBG1(("smsatSetFeaturesPIOCB: did %d!!!\n", oneDeviceData->id)); + tdsmIDCompletedCB(smRoot, smIORequest, smDeviceHandle, smIOSuccess, &(oneDeviceData->satIdentifyData)); + return; + } + /*if the ATAPI device support DMA, then enble this feature*/ + if (oneDeviceData->satDMASupport) + { + satNewIntIo = smsatAllocIntIoResource(smRoot, + smOrgIORequest, + oneDeviceData, + 0, + satNewIntIo); + if (satNewIntIo == agNULL) + { + SM_DBG1(("smsatSetFeaturesPIOCB: memory allocation fails\n")); + /*Complete this identify packet device IO */ + tdsmIDCompletedCB(smRoot, smIORequest, smDeviceHandle, smIOSuccess, &(oneDeviceData->satIdentifyData)); + return; + } /* end memory allocation */ + + satNewIOContext = smsatPrepareNewIO(satNewIntIo, + smOrgIORequest, + oneDeviceData, + scsiCmnd, + satOrgIOContext + ); + /* sends another ATA SET FEATURES based on DMA bit */ + status = smsatSetFeaturesDMA(smRoot, + &satNewIntIo->satIntSmIORequest, + satNewIOContext->psmDeviceHandle, + &satNewIntIo->satIntSmScsiXchg, + satNewIOContext + ); + if (status != SM_RC_SUCCESS) + { + smsatFreeIntIoResource(smRoot, oneDeviceData, satNewIntIo); + SM_DBG2(("satSetFeaturesPIOCB: failed to call smsatSetFeatures()\n")); + /*Complete this identify packet device IO */ + tdsmIDCompletedCB(smRoot, smIORequest, smDeviceHandle, smIOSuccess, &(oneDeviceData->satIdentifyData)); + } + } + else + { + /*Complete this identify packet device IO */ + tdsmIDCompletedCB(smRoot, smIORequest, smDeviceHandle, smIOSuccess, &(oneDeviceData->satIdentifyData)); + } + SM_DBG2(("smsatSetFeaturesPIOCB: exit, agIOStatus 0x%x\n", agIOStatus)); +} + +/***************************************************************************** +*! \brief smsatDeviceResetCB +* +* This routine is a callback function called from smllSATACompleted(). +* This CB routine deals with normal non-chained data I/O SATA request. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to smSatIOContext_t. +* +* \return: none +* +*****************************************************************************/ +osGLOBAL void +smsatDeviceResetCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; +// smSatIOContext_t *satNewIOContext; + smSatInternalIo_t *satIntIo; +// smSatInternalIo_t *satNewIntIo = agNULL; + smDeviceData_t *oneDeviceData; +#ifdef TD_DEBUG_ENABLE + agsaFisPioSetupHeader_t *satPIOSetupHeader = agNULL; + bit32 ataStatus = 0; + bit32 ataError; +#endif +// bit32 status; + bit32 AbortTM = agFALSE; + smDeviceHandle_t *smDeviceHandle; + + SM_DBG1(("smsatDeviceResetCB: start\n")); + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + smDeviceHandle = oneDeviceData->smDevHandle; + if (satIntIo == agNULL) + { + SM_DBG6(("smsatDeviceResetCB: External, OS generated\n")); + satOrgIOContext = satIOContext; + } + else + { + SM_DBG6(("smsatDeviceResetCB: Internal, TD generated\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + SM_DBG6(("smsatDeviceResetCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + SM_DBG6(("smsatDeviceResetCB: satOrgIOContext is NOT NULL\n")); + } + } + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatDeviceResetCB: wrong. agFirstDword is NULL when error, status %d!!!\n", agIOStatus)); + /* TM completed */ + tdsmEventCB( smRoot, + smDeviceHandle, + smIntrEventTypeTaskManagement, + smTMFailed, + oneDeviceData->satTmTaskTag); + oneDeviceData->satTmTaskTag = agNULL; + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + if (agIOStatus == OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_BREAK || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_UNKNOWN_ERROR || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY + ) + { + SM_DBG1(("smsatDeviceResetCB: OSSA_IO_OPEN_CNX_ERROR!!!\n")); + /* TM completed */ + tdsmEventCB( smRoot, + smDeviceHandle, + smIntrEventTypeTaskManagement, + smTMFailed, + oneDeviceData->satTmTaskTag); + oneDeviceData->satTmTaskTag = agNULL; + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + if (agIOStatus != OSSA_IO_SUCCESS) + { +#ifdef TD_DEBUG_ENABLE + /* only agsaFisPioSetup_t is expected */ + satPIOSetupHeader = (agsaFisPioSetupHeader_t *)&(agFirstDword->PioSetup); + ataStatus = satPIOSetupHeader->status; /* ATA Status register */ + ataError = satPIOSetupHeader->error; /* ATA Eror register */ +#endif + SM_DBG1(("smsatDeviceResetCB: ataStatus 0x%x ataError 0x%x!!!\n", ataStatus, ataError)); + /* TM completed */ + tdsmEventCB( smRoot, + smDeviceHandle, + smIntrEventTypeTaskManagement, + smTMFailed, + oneDeviceData->satTmTaskTag); + oneDeviceData->satTmTaskTag = agNULL; + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + /*success */ + if (satOrgIOContext->TMF == AG_ABORT_TASK) + { + AbortTM = agTRUE; + } + if (AbortTM == agTRUE) + { + SM_DBG1(("smsatDeviceResetCB: calling satAbort!!!\n")); + smsatAbort(smRoot, agRoot, satOrgIOContext->satToBeAbortedIOContext); + } + oneDeviceData->satTmTaskTag = agNULL; + oneDeviceData->satDriveState = SAT_DEV_STATE_NORMAL; + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + SM_DBG1(("smsatDeviceResetCB: satPendingIO %d satNCQMaxIO %d!!!\n", oneDeviceData->satPendingIO, oneDeviceData->satNCQMaxIO )); + SM_DBG1(("smsatDeviceResetCB: satPendingNCQIO %d satPendingNONNCQIO %d!!!\n", oneDeviceData->satPendingNCQIO, oneDeviceData->satPendingNONNCQIO)); + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + /* TM completed */ + tdsmEventCB( smRoot, + smDeviceHandle, + smIntrEventTypeTaskManagement, + smTMOK, + oneDeviceData->satTmTaskTag); + + + SM_DBG3(("smsatDeviceResetCB: return\n")); +} + + +/***************************************************************************** +*! \brief smsatExecuteDeviceDiagnosticCB +* +* This routine is a callback function called from smllSATACompleted(). +* This CB routine deals with normal non-chained data I/O SATA request. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to smSatIOContext_t. +* +* \return: none +* +*****************************************************************************/ +osGLOBAL void +smsatExecuteDeviceDiagnosticCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; +// smSatIOContext_t *satNewIOContext; + smSatInternalIo_t *satIntIo; +// smSatInternalIo_t *satNewIntIo = agNULL; + smDeviceData_t *oneDeviceData; + + SM_DBG6(("smsatSetFeaturesDMACB: start\n")); + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + if (satIntIo == agNULL) + { + SM_DBG5(("smsatExecuteDeviceDiagnosticCB: External smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + } + else + { + SM_DBG5(("smsatExecuteDeviceDiagnosticCB: Internal smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + SM_DBG5(("smsatExecuteDeviceDiagnosticCB: satOrgIOContext is NULL\n")); + } + else + { + SM_DBG5(("smsatExecuteDeviceDiagnosticCB: satOrgIOContext is NOT NULL\n")); + } + } + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + /* interal structure free */ + smsatFreeIntIoResource(smRoot,oneDeviceData, satIntIo); +} + +GLOBAL void +smsatTranslateATAPIErrorsToSCSIErrors( + bit8 bCommand, + bit8 bATAStatus, + bit8 bATAError, + bit8 *pSenseKey, + bit16 *pSenseCodeInfo + ) +{ + if (pSenseKey == agNULL || pSenseCodeInfo == agNULL) + { + SM_DBG1(("TranslateATAErrorsToSCSIErros: pSenseKey == agNULL || pSenseCodeInfo == agNULL\n")); + return; + } + if (bATAStatus & ERR_ATA_STATUS_MASK ) + { + if(bATAError & NM_ATA_ERROR_MASK) + { + *pSenseKey = SCSI_SNSKEY_NOT_READY; + *pSenseCodeInfo = 0x3a00; + } + else if(bATAError & ABRT_ATA_ERROR_MASK) + { + *pSenseKey = SCSI_SNSKEY_ABORTED_COMMAND; + *pSenseCodeInfo = 0; + } + else if(bATAError & MCR_ATA_ERROR_MASK) + { + *pSenseKey = SCSI_SNSKEY_UNIT_ATTENTION; + *pSenseCodeInfo = 0x5a01; + } + else if(bATAError & IDNF_ATA_ERROR_MASK) + { + *pSenseKey = SCSI_SNSKEY_MEDIUM_ERROR; + *pSenseCodeInfo = 0x1401; + } + else if(bATAError & MC_ATA_ERROR_MASK) + { + *pSenseKey = SCSI_SNSKEY_UNIT_ATTENTION; + *pSenseCodeInfo = 0x2800; + } + else if(bATAError & UNC_ATA_ERROR_MASK) + { + /*READ*/ + *pSenseKey = SCSI_SNSKEY_MEDIUM_ERROR; + *pSenseCodeInfo = 0x1100; + + /*add WRITE here */ + } + else if(bATAError & ICRC_ATA_ERROR_MASK) + { + *pSenseKey = SCSI_SNSKEY_ABORTED_COMMAND; + *pSenseCodeInfo = 0x4703; + } + } + else if((bATAStatus & DF_ATA_STATUS_MASK)) + { + *pSenseKey = SCSI_SNSKEY_HARDWARE_ERROR; + *pSenseCodeInfo = 0x4400; + } + else + { + SM_DBG1(("unhandled ata error: bATAStatus = 0x%x, bATAError = 0x%x\n", bATAStatus, bATAError)); + } +} + +GLOBAL void +smsatTranslateATAErrorsToSCSIErrors( + bit8 bATAStatus, + bit8 bATAError, + bit8 *pSenseKey, + bit16 *pSenseCodeInfo + ) +{ + + SM_DBG1(("TranslateATAErrorsToSCSIErros: bATAStatus=%d bATAError= %d \n",bATAStatus,bATAError)); + + if (pSenseKey == agNULL || pSenseCodeInfo == agNULL) + { + SM_DBG1(("TranslateATAErrorsToSCSIErros: pSenseKey == agNULL || pSenseCodeInfo == agNULL\n")); + return; + } + + if (bATAStatus & ERR_ATA_STATUS_MASK) + { + if(bATAError & NM_ATA_ERROR_MASK) + { + *pSenseKey = SCSI_SNSKEY_NOT_READY; + *pSenseCodeInfo = SCSI_SNSCODE_MEDIUM_NOT_PRESENT; + } + else if(bATAError & UNC_ATA_ERROR_MASK) + { + *pSenseKey = SCSI_SNSKEY_MEDIUM_ERROR; + *pSenseCodeInfo = SCSI_SNSCODE_UNRECOVERED_READ_ERROR; + } + else if(bATAError & IDNF_ATA_ERROR_MASK) + { + *pSenseKey = SCSI_SNSKEY_ILLEGAL_REQUEST; + *pSenseCodeInfo = SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; + } + else if(bATAError & ABRT_ATA_ERROR_MASK) + { + *pSenseKey = SCSI_SNSKEY_ABORTED_COMMAND; + *pSenseCodeInfo = SCSI_SNSCODE_NO_ADDITIONAL_INFO; + } + else if(bATAError & MC_ATA_ERROR_MASK) + { + *pSenseKey = SCSI_SNSKEY_UNIT_ATTENTION; + *pSenseCodeInfo = SCSI_SNSCODE_NOT_READY_TO_READY_CHANGE; + } + else if(bATAError & MCR_ATA_ERROR_MASK) + { + *pSenseKey = SCSI_SNSKEY_UNIT_ATTENTION; + *pSenseCodeInfo = SCSI_SNSCODE_OPERATOR_MEDIUM_REMOVAL_REQUEST; + } + else if(bATAError & ICRC_ATA_ERROR_MASK) + { + *pSenseKey = SCSI_SNSKEY_ABORTED_COMMAND; + *pSenseCodeInfo = SCSI_SNSCODE_INFORMATION_UNIT_CRC_ERROR; + } + else + { + *pSenseKey = SCSI_SNSKEY_NO_SENSE; + *pSenseCodeInfo = SCSI_SNSCODE_NO_ADDITIONAL_INFO; + + } + } + else if (bATAStatus & DF_ATA_STATUS_MASK) /* INTERNAL TARGET FAILURE */ + { + *pSenseKey = SCSI_SNSKEY_HARDWARE_ERROR; + *pSenseCodeInfo = SCSI_SNSCODE_INTERNAL_TARGET_FAILURE; + } + + +} + + +FORCEINLINE void +smsatNonChainedDataIOCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + smIORequestBody_t *smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + smSatIOContext_t *satIOContext = (smSatIOContext_t *) ioContext; + smSatInternalIo_t *SatIntIo = satIOContext->satIntIoContext; + smDeviceData_t *oneDeviceData = satIOContext->pSatDevData; + smRoot_t *smRoot = oneDeviceData->smRoot; + smIntRoot_t *smIntRoot = (smIntRoot_t *)smRoot->smData; + smIntContext_t *smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + bit32 interruptContext = satIOContext->interruptContext; + + SM_DBG2(("smsatNonChainedDataIOCB: start\n")); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + + /* interal structure free */ + smsatFreeIntIoResource( smRoot, + oneDeviceData, + SatIntIo); + + /* Process completion */ + if( (agIOStatus == OSSA_IO_SUCCESS) && (agIOInfoLen == 0)) + { + SM_DBG5(("smsatNonChainedDataIOCB: success\n")); + SM_DBG5(("smsatNonChainedDataIOCB: success agIORequest %p\n", agIORequest)); + /* + * Command was completed OK, this is the normal path. + * Now call the OS-App Specific layer about this completion. + */ + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + interruptContext); + } + else + { + SM_DBG1(("smsatNonChainedDataIOCB: calling smsatProcessAbnormalCompletion!!!\n")); + /* More checking needed */ + smsatProcessAbnormalCompletion( agRoot, + agIORequest, + agIOStatus, + agFirstDword, + agIOInfoLen, + agParam, + satIOContext); + } + + return; +} + +FORCEINLINE void +smsatChainedDataIOCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smIORequestBody_t *smOrgIORequestBody; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatIOContext_t *satNewIOContext; + smSatInternalIo_t *satIntIo; + smSatInternalIo_t *satNewIntIo = agNULL; +// smDeviceData_t *satDevData; + smDeviceData_t *oneDeviceData; + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + smIORequest_t *smOrgIORequest; + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + bit32 status = tiError; + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + bit32 dataLength; + + SM_DBG6(("smsatChainedDataIOCB: start\n")); + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + if (satIOContext == agNULL) + { + SM_DBG1(("smsatChainedDataIOCB: satIOContext is NULL\n")); + return; + } + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + if (satIntIo == agNULL) + { + SM_DBG5(("smsatChainedDataIOCB: External smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + smOrgIORequest = smIORequestBody->smIORequest; + pSense = satIOContext->pSense; + scsiCmnd = satIOContext->pScsiCmnd; + } + else + { + SM_DBG5(("smsatChainedDataIOCB: Internal smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + smOrgIORequest = (smIORequest_t *)smOrgIORequestBody->smIORequest; + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatChainedDataIOCB: wrong. agFirstDword is NULL when error, status %d!!!\n", agIOStatus)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + /* + checking IO status, FIS type and error status + */ + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* agsaFisPioSetup_t or agsaFisRegDeviceToHost_t or agsaFisSetDevBits_t for read + agsaFisRegDeviceToHost_t or agsaFisSetDevBits_t for write + first, assumed to be Reg Device to Host FIS + This is OK to just find fis type + */ + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + /* for debugging */ + if( (statDevToHostFisHeader->fisType != PIO_SETUP_DEV_TO_HOST_FIS) && + (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) && + (statDevToHostFisHeader->fisType != SET_DEV_BITS_FIS) + ) + { + SM_DBG1(("smsatChainedDataIOCB: FAILED, Wrong FIS type 0x%x!!!\n", statDevToHostFisHeader->fisType)); + } + + /* for debugging */ + if ( (ataStatus & ERR_ATA_STATUS_MASK) || + (ataStatus & DF_ATA_STATUS_MASK) + ) + { + SM_DBG1(("smsatChainedDataIOCB: FAILED, error status and command 0x%x!!!\n", hostToDevFis->h.command)); + } + + /* the function below handles abort case */ + smsatDelayedProcessAbnormalCompletion(agRoot, + agIORequest, + agIOStatus, + agFirstDword, + agIOInfoLen, + agParam, + satIOContext); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } /* end of error */ + + switch (hostToDevFis->h.command) + { + case SAT_READ_DMA: /* fall through */ + case SAT_READ_SECTORS: /* fall through */ + case SAT_READ_DMA_EXT: /* fall through */ + case SAT_READ_SECTORS_EXT: /* fall through */ + case SAT_READ_FPDMA_QUEUED: /* fall through */ + case SAT_WRITE_DMA: /* fall through */ + case SAT_WRITE_SECTORS:/* fall through */ + case SAT_WRITE_DMA_FUA_EXT: /* fall through */ + case SAT_WRITE_DMA_EXT: /* fall through */ + case SAT_WRITE_SECTORS_EXT: /* fall through */ + case SAT_WRITE_FPDMA_QUEUED: + + SM_DBG5(("smsatChainedDataIOCB: READ/WRITE success case\n")); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + /* done with internally genereated SAT_SMART_RETURN_STATUS */ + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + /* let's loop till TL */ + + /* lba = lba + tl + loopnum--; + if (loopnum == 0) done + */ + (satOrgIOContext->LoopNum)--; + if (satOrgIOContext->LoopNum == 0) + { + /* done with read */ + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + return; + } + + /* don't need to allocate payload memory here. Use the one allocated by OS layer */ + dataLength = 0; + + satNewIntIo = smsatAllocIntIoResource( smRoot, + smOrgIORequest, + oneDeviceData, + dataLength, + satNewIntIo); + if (satNewIntIo == agNULL) + { + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOFailed, + smDetailOtherError, + agNULL, + satOrgIOContext->interruptContext ); + + SM_DBG1(("smsatChainedDataIOCB: momory allocation fails!!!\n")); + return; + } /* end of memory allocation failure */ + + /* + * Need to initialize all the fields within satIOContext + */ + + satNewIOContext = smsatPrepareNewIO( + satNewIntIo, + smOrgIORequest, + oneDeviceData, + scsiCmnd, + satOrgIOContext + ); + + /* sending another ATA command */ + switch (scsiCmnd->cdb[0]) + { + case SCSIOPC_READ_6: + /* no loop should occur with READ6 since it fits in one ATA command */ + break; + case SCSIOPC_READ_10: /* fall through */ + case SCSIOPC_READ_12: /* fall through */ + case SCSIOPC_READ_16: /* fall through */ + status = smsatRead_1( smRoot, + &satNewIntIo->satIntSmIORequest, + satNewIOContext->psmDeviceHandle, + &satNewIntIo->satIntSmScsiXchg, + satNewIOContext); + break; + case SCSIOPC_WRITE_6: + /* no loop should occur with WRITE6 since it fits in one ATA command */ + break; + case SCSIOPC_WRITE_10: /* fall through */ + case SCSIOPC_WRITE_12: /* fall through */ + case SCSIOPC_WRITE_16: /* fall through */ + status = smsatWrite_1( smRoot, + &satNewIntIo->satIntSmIORequest, + satNewIOContext->psmDeviceHandle, + &satNewIntIo->satIntSmScsiXchg, + satNewIOContext); + break; + default: + SM_DBG1(("smsatChainedDataIOCB: success but default case scsi cmd 0x%x ata cmd 0x%x!!!\n",scsiCmnd->cdb[0], hostToDevFis->h.command)); + status = tiError; + break; + } + + + + if (status != SM_RC_SUCCESS) + { + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satNewIntIo); + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOFailed, + smDetailOtherError, + agNULL, + satOrgIOContext->interruptContext ); + SM_DBG1(("smsatChainedDataIOCB: calling satRead10_1 fails!!!\n")); + return; + } + + break; + + + default: + SM_DBG1(("smsatChainedDataIOCB: success but default case command 0x%x!!!\n",hostToDevFis->h.command)); + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOFailed, + smDetailOtherError, + agNULL, + satOrgIOContext->interruptContext ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + break; + } + + + return; +} + +osGLOBAL void +smsatNonChainedVerifyCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ) +{ + +// tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; +// tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; +// tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; +// tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smIORequestBody_t *smOrgIORequestBody; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatInternalIo_t *satIntIo; +// satDeviceData_t *satDevData; + smDeviceData_t *oneDeviceData; + smScsiRspSense_t *pSense; + smIORequest_t *smOrgIORequest; + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + + SM_DBG2(("smsatNonChainedVerifyCB: start\n")); + SM_DBG5(("smsatNonChainedVerifyCB: agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate smIOContext */ + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + if (satIntIo == agNULL) + { + SM_DBG4(("smsatNonChainedVerifyCB: External smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + smOrgIORequest = smIORequestBody->smIORequest; + pSense = satIOContext->pSense; + } + else + { + SM_DBG4(("smsatNonChainedVerifyCB: Internal smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + SM_DBG4(("smsatNonChainedVerifyCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + SM_DBG4(("smsatNonChainedVerifyCB: satOrgIOContext is NOT NULL\n")); + } + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + smOrgIORequest = (smIORequest_t *)smOrgIORequestBody->smIORequest; + pSense = satOrgIOContext->pSense; + } + + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatNonChainedVerifyCB: wrong. agFirstDword is NULL when error, status %d!!!\n", agIOStatus)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* only agsaFisRegDeviceToHost_t is expected */ + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + } + + if( agIOStatus != OSSA_IO_SUCCESS) + { + if ( (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) || + ((ataStatus & ERR_ATA_STATUS_MASK) || (ataStatus & DF_ATA_STATUS_MASK)) + ) + { + /* for debugging */ + if( agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatNonChainedVerifyCB: FAILED, NOT IO_SUCCESS!!!\n")); + } + else if (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) + { + SM_DBG1(("smsatNonChainedVerifyCB: FAILED, Wrong FIS type 0x%x!!!\n",statDevToHostFisHeader->fisType)); + } + else if ( (ataStatus & ERR_ATA_STATUS_MASK) || + (ataStatus & DF_ATA_STATUS_MASK) + ) + { + SM_DBG1(("smsatNonChainedVerifyCB: FAILED, FAILED, error status!!!\n")); + } + + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + smsatProcessAbort(smRoot, + smOrgIORequest, + satOrgIOContext + ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + /* for debugging */ + switch (hostToDevFis->h.command) + { + case SAT_READ_VERIFY_SECTORS: + SM_DBG1(("smsatNonChainedVerifyCB: SAT_READ_VERIFY_SECTORS!!!\n")); + break; + case SAT_READ_VERIFY_SECTORS_EXT: + SM_DBG1(("smsatNonChainedVerifyCB: SAT_READ_VERIFY_SECTORS_EXT!!!\n")); + break; + default: + SM_DBG1(("smsatNonChainedVerifyCB: error default case command 0x%x!!!\n", hostToDevFis->h.command)); + break; + } + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } /* end error checking */ + } + + /* process success from this point on */ + switch (hostToDevFis->h.command) + { + case SAT_READ_VERIFY_SECTORS: /* fall through */ + case SAT_READ_VERIFY_SECTORS_EXT: + SM_DBG5(("smsatNonChainedVerifyCB: SAT_WRITE_DMA_EXT success \n")); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext); + break; + default: + SM_DBG1(("smsatNonChainedVerifyCB: success but error default case command 0x%x!!!\n", hostToDevFis->h.command)); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + break; + } + + return; +} + +osGLOBAL void +smsatChainedVerifyCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ) +{ + + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smIORequestBody_t *smOrgIORequestBody; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatIOContext_t *satNewIOContext; + smSatInternalIo_t *satIntIo; + smSatInternalIo_t *satNewIntIo = agNULL; + smDeviceData_t *oneDeviceData; + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + smIORequest_t *smOrgIORequest; + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + bit32 status = tiError; + bit32 dataLength; + + SM_DBG2(("smsatChainedVerifyCB: start\n")); + SM_DBG5(("smsatChainedVerifyCB: agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate smIOContext */ + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + + if (satIntIo == agNULL) + { + SM_DBG4(("smsatChainedVerifyCB: External smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + smOrgIORequest = smIORequestBody->smIORequest; + pSense = satIOContext->pSense; + scsiCmnd = satIOContext->pScsiCmnd; + } + else + { + SM_DBG4(("smsatChainedVerifyCB: Internal smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + SM_DBG4(("smsatChainedVerifyCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + SM_DBG4(("smsatChainedVerifyCB: satOrgIOContext is NOT NULL\n")); + } + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + smOrgIORequest = (smIORequest_t *)smOrgIORequestBody->smIORequest; + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatChainedVerifyCB: wrong. agFirstDword is NULL when error, status %d!!!\n", agIOStatus)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* only agsaFisRegDeviceToHost_t is expected */ + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + } + + if( agIOStatus != OSSA_IO_SUCCESS) + { + if ( (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) || + ((ataStatus & ERR_ATA_STATUS_MASK) || (ataStatus & DF_ATA_STATUS_MASK)) + ) + { + /* for debugging */ + if( agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatChainedVerifyCB: FAILED, NOT IO_SUCCESS!!!\n")); + } + else if (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) + { + SM_DBG1(("smsatChainedVerifyCB: FAILED, Wrong FIS type 0x%x!!!\n",statDevToHostFisHeader->fisType)); + } + else if ( (ataStatus & ERR_ATA_STATUS_MASK) || + (ataStatus & DF_ATA_STATUS_MASK) + ) + { + SM_DBG1(("smsatChainedVerifyCB: FAILED, FAILED, error status!!!\n")); + } + + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + smsatProcessAbort(smRoot, + smOrgIORequest, + satOrgIOContext + ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + /* for debugging */ + switch (hostToDevFis->h.command) + { + case SAT_READ_VERIFY_SECTORS: + SM_DBG1(("smsatChainedVerifyCB: SAT_READ_VERIFY_SECTORS!!!\n")); + break; + case SAT_READ_VERIFY_SECTORS_EXT: + SM_DBG1(("smsatChainedVerifyCB: SAT_READ_VERIFY_SECTORS_EXT!!!\n")); + break; + default: + SM_DBG1(("smsatChainedVerifyCB: error default case command 0x%x!!!\n", hostToDevFis->h.command)); + break; + } + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } /* end error checking */ + } + + /* process success from this point on */ + switch (hostToDevFis->h.command) + { + case SAT_READ_VERIFY_SECTORS: /* fall through */ + case SAT_READ_VERIFY_SECTORS_EXT: + SM_DBG5(("smsatChainedVerifyCB: SAT_WRITE_DMA_EXT success \n")); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + /* let's loop till TL */ + + /* lba = lba + tl + loopnum--; + if (loopnum == 0) done + */ + (satOrgIOContext->LoopNum)--; + if (satOrgIOContext->LoopNum == 0) + { + /* + done with write and verify + */ + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + return; + } + + if (satOrgIOContext->superIOFlag) + { + dataLength = ((tiSuperScsiInitiatorRequest_t *) satOrgIOContext->smScsiXchg)->scsiCmnd.expDataLength; + } + else + { + dataLength = ((tiScsiInitiatorRequest_t *) satOrgIOContext->smScsiXchg)->scsiCmnd.expDataLength; + } + + satNewIntIo = smsatAllocIntIoResource( smRoot, + smOrgIORequest, + oneDeviceData, + dataLength, + satNewIntIo); + if (satNewIntIo == agNULL) + { + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOFailed, + smDetailOtherError, + agNULL, + satOrgIOContext->interruptContext ); + + SM_DBG1(("smsatChainedVerifyCB: momory allocation fails!!!\n")); + return; + } /* end of memory allocation failure */ + + /* + * Need to initialize all the fields within satIOContext + */ + + satNewIOContext = smsatPrepareNewIO( + satNewIntIo, + smOrgIORequest, + oneDeviceData, + scsiCmnd, + satOrgIOContext + ); + status = smsatChainedVerify(smRoot, + &satNewIntIo->satIntSmIORequest, + satNewIOContext->psmDeviceHandle, + &satNewIntIo->satIntSmScsiXchg, + satNewIOContext); + + if (status != SM_RC_SUCCESS) + { + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satNewIntIo); + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOFailed, + smDetailOtherError, + agNULL, + satOrgIOContext->interruptContext ); + SM_DBG1(("smsatChainedVerifyCB: calling satChainedVerify fails!!!\n")); + return; + } + + break; + default: + SM_DBG1(("smsatChainedVerifyCB: success but error default case command 0x%x!!!\n", hostToDevFis->h.command)); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + break; + } + return; +} + + +osGLOBAL void +smsatTestUnitReadyCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ) +{ + /* + In the process of TestUnitReady + Process SAT_GET_MEDIA_STATUS + Process SAT_CHECK_POWER_MODE + */ +// tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; +// tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; +// tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; +// tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smIORequestBody_t *smOrgIORequestBody; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatIOContext_t *satNewIOContext; + smSatInternalIo_t *satIntIo; + smSatInternalIo_t *satNewIntIo = agNULL; +// satDeviceData_t *satDevData; + smDeviceData_t *oneDeviceData; + + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + smIORequest_t *smOrgIORequest; + + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + bit32 ataError; + + bit32 status; + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + + SM_DBG2(("smsatTestUnitReadyCB: start\n")); + SM_DBG6(("smsatTestUnitReadyCB: agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate smIOContext */ + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + + if (satIntIo == agNULL) + { + SM_DBG5(("smsatTestUnitReadyCB: no internal smSatInternalIo_t satIntIoContext\n")); + pSense = satIOContext->pSense; + scsiCmnd = satIOContext->pScsiCmnd; + satOrgIOContext = satIOContext; + smOrgIORequest = smIORequestBody->smIORequest; + } + else + { + SM_DBG5(("smsatTestUnitReadyCB: yes internal smSatInternalIo_t satIntIoContext\n")); + + /* orginal smIOContext */ + smOrgIORequest = (smIORequest_t *)satIOContext->satIntIoContext->satOrgSmIORequest; + smOrgIORequestBody = (smIORequestBody_t *)smOrgIORequest->tdData; + satOrgIOContext = &(smOrgIORequestBody->transport.SATA.satIOContext); + + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + + if (agIOStatus == OSSA_IO_ABORTED) + { + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOFailed, + smDetailAborted, + agNULL, + satIOContext->interruptContext); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + return; + } + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatTestUnitReadyCB: agFirstDword is NULL when error, status %d!!!\n", agIOStatus)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NOT_READY, + 0, + SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_CAUSE_NOT_REPORTABLE, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + return; + } + /* + HW checks an error for us and the results is agIOStatus + */ + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* only agsaFisRegDeviceToHost_t is expected */ + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + ataError = statDevToHostFisHeader->error; /* ATA Eror register */ + if (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) + { + SM_DBG1(("smsatTestUnitReadyCB: FAILED, Wrong FIS type 0x%x!!!\n",statDevToHostFisHeader->fisType)); + } + else if ( (ataStatus & ERR_ATA_STATUS_MASK) || + (ataStatus & DF_ATA_STATUS_MASK) + ) + { + SM_DBG1(("smsatTestUnitReadyCB: FAILED, FAILED, error status!!!\n")); + } + + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + smsatProcessAbort(smRoot, + smOrgIORequest, + satOrgIOContext + ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + switch (hostToDevFis->h.command) + { + case SAT_GET_MEDIA_STATUS: + SM_DBG1(("smsatTestUnitReadyCB: SAT_GET_MEDIA_STATUS failed!!! \n")); + + /* checking NM bit */ + if (ataError & SCSI_NM_MASK) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NOT_READY, + 0, + SCSI_SNSCODE_MEDIUM_NOT_PRESENT, + satOrgIOContext); + } + else + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NOT_READY, + 0, + SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_CAUSE_NOT_REPORTABLE, + satOrgIOContext); + } + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + break; + case SAT_CHECK_POWER_MODE: + SM_DBG1(("smsatTestUnitReadyCB: SAT_CHECK_POWER_MODE failed!!! \n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NOT_READY, + 0, + SCSI_SNSCODE_LOGICAL_UNIT_DOES_NOT_RESPOND_TO_SELECTION, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + break; + default: + SM_DBG1(("smsatTestUnitReadyCB: default failed command %d!!!\n", hostToDevFis->h.command)); + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NOT_READY, + 0, + SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_CAUSE_NOT_REPORTABLE, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + break; + + } + return; + }/* end error */ + + /* ATA command completes sucessfully */ + switch (hostToDevFis->h.command) + { + case SAT_GET_MEDIA_STATUS: + + SM_DBG5(("smsatTestUnitReadyCB: SAT_GET_MEDIA_STATUS success\n")); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + satNewIntIo = smsatAllocIntIoResource( smRoot, + smOrgIORequest, + oneDeviceData, + 0, + satNewIntIo); + if (satNewIntIo == agNULL) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NOT_READY, + 0, + SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_CAUSE_NOT_REPORTABLE, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + SM_DBG1(("smsatTestUnitReadyCB: momory allocation fails!!!\n")); + return; + } + + /* + * Need to initialize all the fields within satIOContext + */ + + satNewIOContext = smsatPrepareNewIO( + satNewIntIo, + smOrgIORequest, + oneDeviceData, + scsiCmnd, + satOrgIOContext + ); + + /* sends SAT_CHECK_POWER_MODE */ + status = smsatTestUnitReady_1( smRoot, + &satNewIntIo->satIntSmIORequest, + satNewIOContext->psmDeviceHandle, + &satNewIntIo->satIntSmScsiXchg, + satNewIOContext); + + if (status != SM_RC_SUCCESS) + { + /* sending SAT_CHECK_POWER_MODE fails */ + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satNewIntIo); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NOT_READY, + 0, + SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_CAUSE_NOT_REPORTABLE, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + SM_DBG1(("smsatTestUnitReadyCB: calling satTestUnitReady_1 fails!!!\n")); + return; + } + + break; + case SAT_CHECK_POWER_MODE: + SM_DBG5(("smsatTestUnitReadyCB: SAT_CHECK_POWER_MODE success\n")); + + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + /* returns good status */ + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + + break; + default: + SM_DBG1(("smsatTestUnitReadyCB: default success command %d!!!\n", hostToDevFis->h.command)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NOT_READY, + 0, + SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_CAUSE_NOT_REPORTABLE, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + break; + } + + return; +} + +osGLOBAL void +smsatRequestSenseCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + /* ATA Vol 1, p299 SAT_SMART_RETURN_STATUS */ + /* + if threshold exceeds, return SCSI_SNSCODE_HARDWARE_IMPENDING_FAILURE + else call satRequestSense_1 to send CHECK_POWER_MODE + */ + +// tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; +// tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; +// tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; +// tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smIORequestBody_t *smOrgIORequestBody; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatIOContext_t *satNewIOContext; + smSatInternalIo_t *satIntIo; + smSatInternalIo_t *satNewIntIo = agNULL; +// satDeviceData_t *satDevData; + smDeviceData_t *oneDeviceData; + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + smIORequest_t *smOrgIORequest; + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + bit32 status; + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + agsaFisRegD2HData_t statDevToHostFisData; + bit32 allocationLen = 0; + bit32 dataLength; + bit8 *pDataBuffer = agNULL; + + SM_DBG2(("smsatRequestSenseCB: start\n")); + SM_DBG4(("smsatRequestSenseCB:agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate smIOContext */ + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + + /*ttttttthe one */ + if (satIntIo == agNULL) + { + SM_DBG4(("smsatRequestSenseCB: External smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + smOrgIORequest = smIORequestBody->smIORequest; + if (satOrgIOContext->superIOFlag) + { + pDataBuffer = (bit8 *)(((tiSuperScsiInitiatorRequest_t *)satOrgIOContext->smScsiXchg)->sglVirtualAddr);//satOrgIOContext->pSense; + } + else + { + pDataBuffer = (bit8 *)(((tiScsiInitiatorRequest_t *) satOrgIOContext->smScsiXchg)->sglVirtualAddr);//satOrgIOContext->pSense; + + } + scsiCmnd = satOrgIOContext->pScsiCmnd; + pSense = satOrgIOContext->pSense; + } + else + { + SM_DBG4(("smsatRequestSenseCB: Internal smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + SM_DBG4(("smsatRequestSenseCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + SM_DBG4(("smsatRequestSenseCB: satOrgIOContext is NOT NULL\n")); + } + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + smOrgIORequest = (smIORequest_t *)smOrgIORequestBody->smIORequest; + + if (satOrgIOContext->superIOFlag) + { + pDataBuffer = (bit8 *)(((tiSuperScsiInitiatorRequest_t *)satOrgIOContext->smScsiXchg)->sglVirtualAddr);//satOrgIOContext->pSense; + } + else + { + pDataBuffer = (bit8 *)(((tiScsiInitiatorRequest_t *) satOrgIOContext->smScsiXchg)->sglVirtualAddr);//satOrgIOContext->pSense; + + } + scsiCmnd = satOrgIOContext->pScsiCmnd; + pSense = satOrgIOContext->pSense; + } + + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + + SM_DBG4(("smsatRequestSenseCB: fis command 0x%x\n", hostToDevFis->h.command)); + + allocationLen = scsiCmnd->cdb[4]; + allocationLen = MIN(allocationLen, scsiCmnd->expDataLength); + SM_DBG1(("smsatRequestSenseCB: allocationLen in CDB %d 0x%x!!!\n", allocationLen,allocationLen)); + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatRequestSenseCB: wrong. agFirstDword is NULL when error, status %d!!!\n", agIOStatus)); + tdsmIOCompletedCB( + smRoot, + smOrgIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + return; + } + + /* + checking IO status, FIS type and error status + */ + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* only agsaFisRegDeviceToHost_t is expected */ + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + + /* for debugging */ + if( statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) + { + if (hostToDevFis->h.command == SAT_SMART && hostToDevFis->h.features == SAT_SMART_RETURN_STATUS) + { + SM_DBG1(("smsatRequestSenseCB: FAILED, Wrong FIS type 0x%x and SAT_SMART_RETURN_STATU!!!\n", statDevToHostFisHeader->fisType)); + } + else + { + SM_DBG1(("smsatRequestSenseCB: FAILED, Wrong FIS type 0x%x and SAT_CHECK_POWER_MODE!!!\n",statDevToHostFisHeader->fisType)); + } + } + + /* for debugging */ + if ( (ataStatus & ERR_ATA_STATUS_MASK) || + (ataStatus & DF_ATA_STATUS_MASK) + ) + { + if (hostToDevFis->h.command == SAT_SMART && hostToDevFis->h.features == SAT_SMART_RETURN_STATUS) + { + SM_DBG1(("smsatRequestSenseCB: FAILED, error status and SAT_SMART_RETURN_STATU!!!\n")); + } + else + { + SM_DBG1(("smsatRequestSenseCB: FAILED, error status and SAT_CHECK_POWER_MODE!!!\n")); + } + } + + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + smsatProcessAbort(smRoot, + smOrgIORequest, + satOrgIOContext + ); + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + if (hostToDevFis->h.command == SAT_SMART && hostToDevFis->h.features == SAT_SMART_RETURN_STATUS) + { + /* report using the original tiIOrequst */ + /* failed during sending SMART RETURN STATUS */ + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_HARDWARE_IMPENDING_FAILURE, + satOrgIOContext); + sm_memcpy(pDataBuffer, pSense, MIN(SENSE_DATA_LENGTH, allocationLen)); + if (SENSE_DATA_LENGTH < allocationLen) + { + /* underrun */ + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == satIntIo->satOrgSmIORequest */ + smIOUnderRun, + allocationLen - SENSE_DATA_LENGTH, + agNULL, + satOrgIOContext->interruptContext ); + } + else + { + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + } + } + else + { + /* report using the original tiIOrequst */ + /* failed during sending SAT_CHECK_POWER_MODE */ + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_LOW_POWER_CONDITION_ON, + satOrgIOContext); + sm_memcpy(pDataBuffer, pSense, MIN(SENSE_DATA_LENGTH, allocationLen)); + + if (SENSE_DATA_LENGTH < allocationLen) + { + /* underrun */ + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == satIntIo->satOrgSmIORequest */ + smIOUnderRun, + allocationLen - SENSE_DATA_LENGTH, + agNULL, + satOrgIOContext->interruptContext ); + } + else + { + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + } + } + + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + saFrameReadBlock(agRoot, agParam, 0, &statDevToHostFisData, sizeof(agsaFisRegD2HData_t)); + + switch (hostToDevFis->h.command) + { + case SAT_SMART: + SM_DBG4(("smsatRequestSenseCB: SAT_SMART_RETURN_STATUS case\n")); + if (statDevToHostFisData.lbaMid == 0xF4 || statDevToHostFisData.lbaHigh == 0x2C) + { + /* threshold exceeds */ + SM_DBG1(("smsatRequestSenseCB: threshold exceeds!!!\n")); + + + /* report using the original tiIOrequst */ + /* failed during sending SMART RETURN STATUS */ + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_HARDWARE_IMPENDING_FAILURE, + satOrgIOContext); + sm_memcpy(pDataBuffer, pSense, MIN(SENSE_DATA_LENGTH, allocationLen)); + + if (SENSE_DATA_LENGTH < allocationLen) + { + /* underrun */ + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOUnderRun, + allocationLen - SENSE_DATA_LENGTH, + agNULL, + satOrgIOContext->interruptContext ); + } + else + { + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + } + + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + /* done with internally genereated SAT_SMART_RETURN_STATUS */ + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + /* at this point, successful SMART_RETURN_STATUS + xmit SAT_CHECK_POWER_MODE + */ + if (satOrgIOContext->superIOFlag) + { + dataLength = ((tiSuperScsiInitiatorRequest_t *) satOrgIOContext->smScsiXchg)->scsiCmnd.expDataLength; + } + else + { + dataLength = ((tiScsiInitiatorRequest_t *) satOrgIOContext->smScsiXchg)->scsiCmnd.expDataLength; + } + + satNewIntIo = smsatAllocIntIoResource( smRoot, + smOrgIORequest, + oneDeviceData, + dataLength, + satNewIntIo); + if (satNewIntIo == agNULL) + { + /* failed as a part of sending SMART RETURN STATUS */ + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_HARDWARE_IMPENDING_FAILURE, + satOrgIOContext); + sm_memcpy(pDataBuffer, pSense, MIN(SENSE_DATA_LENGTH, allocationLen)); + + if (SENSE_DATA_LENGTH < allocationLen) + { + /* underrun */ + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOUnderRun, + allocationLen - SENSE_DATA_LENGTH, + agNULL, + satOrgIOContext->interruptContext ); + } + else + { + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + } + + SM_DBG1(("smsatRequestSenseCB: momory allocation fails!!!\n")); + return; + } /* end of memory allocation failure */ + + + /* + * Need to initialize all the fields within satIOContext + */ + + satNewIOContext = smsatPrepareNewIO( + satNewIntIo, + smOrgIORequest, + oneDeviceData, + scsiCmnd, + satOrgIOContext + ); + + /* sending SAT_CHECK_POWER_MODE */ + status = smsatRequestSense_1( smRoot, + &satNewIntIo->satIntSmIORequest, + satNewIOContext->psmDeviceHandle, + &satNewIntIo->satIntSmScsiXchg, + satNewIOContext); + + if (status != SM_RC_SUCCESS) + { + /* sending SAT_CHECK_POWER_MODE fails */ + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satNewIntIo); + + /* failed during sending SAT_CHECK_POWER_MODE */ + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_LOW_POWER_CONDITION_ON, + satOrgIOContext); + sm_memcpy(pDataBuffer, pSense, MIN(SENSE_DATA_LENGTH, allocationLen)); + + if (SENSE_DATA_LENGTH < allocationLen) + { + /* underrun */ + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOUnderRun, + allocationLen - SENSE_DATA_LENGTH, + agNULL, + satOrgIOContext->interruptContext ); + } + else + { + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + } + + SM_DBG1(("smsatRequestSenseCB: calling satRequestSense_1 fails!!!\n")); + return; + } + + break; + case SAT_CHECK_POWER_MODE: + SM_DBG4(("smsatRequestSenseCB: SAT_CHECK_POWER_MODE case\n")); + + /* check ATA STANDBY state */ + if (statDevToHostFisData.sectorCount == 0x00) + { + /* in STANDBY */ + SM_DBG1(("smsatRequestSenseCB: in standby!!!\n")); + + + /* report using the original tiIOrequst */ + /* failed during sending SAT_CHECK_POWER_MODE */ + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_LOW_POWER_CONDITION_ON, + satOrgIOContext); + sm_memcpy(pDataBuffer, pSense, MIN(SENSE_DATA_LENGTH, allocationLen)); + + if (SENSE_DATA_LENGTH < allocationLen) + { + /* underrun */ + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOUnderRun, + allocationLen - SENSE_DATA_LENGTH, + agNULL, + satOrgIOContext->interruptContext ); + } + else + { + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + } + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + /* done with internnaly generated SAT_CHECK_POWER_MODE */ + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + if (oneDeviceData->satFormatState == agTRUE) + { + SM_DBG1(("smsatRequestSenseCB: in format!!!\n")); + + + /* report using the original tiIOrequst */ + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NOT_READY, + 0, + SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_FORMAT_IN_PROGRESS, + satOrgIOContext); + sm_memcpy(pDataBuffer, pSense, MIN(SENSE_DATA_LENGTH, allocationLen)); + + if (SENSE_DATA_LENGTH < allocationLen) + { + /* underrun */ + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOUnderRun, + allocationLen - SENSE_DATA_LENGTH, + agNULL, + satOrgIOContext->interruptContext ); + } + else + { + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + } + + return; + } + + /* normal: returns good status for requestsense */ + /* report using the original tiIOrequst */ + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + sm_memcpy(pDataBuffer, pSense, MIN(SENSE_DATA_LENGTH, allocationLen)); + SM_DBG4(("smsatRequestSenseCB: returning good status for requestsense\n")); + if (SENSE_DATA_LENGTH < allocationLen) + { + /* underrun */ + SM_DBG6(("smsatRequestSenseCB reporting underrun lenNeeded=0x%x lenReceived=0x%x smIORequest=%p\n", + SENSE_DATA_LENGTH, allocationLen, smOrgIORequest)); + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOUnderRun, + allocationLen - SENSE_DATA_LENGTH, + agNULL, + satOrgIOContext->interruptContext ); + + } + else + { + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + } + + break; + default: + SM_DBG1(("smsatRequestSenseCB: success but error default case command 0x%x!!!\n", hostToDevFis->h.command)); + /* pSense here is a part of satOrgIOContext */ + pSense = satOrgIOContext->pSmSenseData->senseData; + satOrgIOContext->pSmSenseData->senseLen = SENSE_DATA_LENGTH; + /* unspecified case, return no sense and no addition info */ + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + sm_memcpy(pDataBuffer, pSense, MIN(SENSE_DATA_LENGTH, allocationLen)); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + break; + } /* switch */ + + return; + +} + +osGLOBAL void +smsatSendDiagnosticCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ) +{ + /* + In the process of SendDiagnotic + Process READ VERIFY SECTOR(S) EXT two time + Process SMART ECECUTE OFF-LINE IMMEDIATE + */ +// tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; +// tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; +// tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; +// tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smIORequestBody_t *smOrgIORequestBody; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatIOContext_t *satNewIOContext; + smSatInternalIo_t *satIntIo; + smSatInternalIo_t *satNewIntIo = agNULL; +// satDeviceData_t *satDevData; + smDeviceData_t *oneDeviceData; + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + smIORequest_t *smOrgIORequest; + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + + bit32 status; + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + + SM_DBG2(("smsatSendDiagnosticCB: start\n")); + SM_DBG5(("smsatSendDiagnosticCB:agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate smIOContext */ + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + + if (satIntIo == agNULL) + { + SM_DBG4(("smsatSendDiagnosticCB: External smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + smOrgIORequest = smIORequestBody->smIORequest; + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + else + { + SM_DBG4(("smsatSendDiagnosticCB: Internal smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + SM_DBG4(("smsatSendDiagnosticCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + SM_DBG4(("smsatSendDiagnosticCB: satOrgIOContext is NOT NULL\n")); + } + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + smOrgIORequest = (smIORequest_t *)smOrgIORequestBody->smIORequest; + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatSendDiagnosticCB: wrong. agFirstDword is NULL when error, status %d!!!\n", agIOStatus)); + oneDeviceData->satVerifyState = 0; + oneDeviceData->satBGPendingDiag = agFALSE; + + if (hostToDevFis->d.lbaLow != 0x01 && hostToDevFis->d.lbaLow != 0x02) + { + /* no completion for background send diagnotic. It is done in satSendDiagnostic() */ + tdsmIOCompletedCB( + smRoot, + smOrgIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + } + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + + } + + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* only agsaFisRegDeviceToHost_t is expected */ + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + } + + SM_DBG5(("smsatSendDiagnosticCB: fis command 0x%x\n", hostToDevFis->h.command)); + + if( agIOStatus != OSSA_IO_SUCCESS) + { + /* + checking IO status, FIS type and error status + */ + oneDeviceData->satVerifyState = 0; + oneDeviceData->satBGPendingDiag = agFALSE; + + if( (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) || + ((ataStatus & ERR_ATA_STATUS_MASK) || (ataStatus & DF_ATA_STATUS_MASK)) + ) + { + + /* for debugging */ + if( agIOStatus != OSSA_IO_SUCCESS) + { + if ( hostToDevFis->h.command == SAT_READ_VERIFY_SECTORS_EXT ) + { + SM_DBG1(("smsatSendDiagnosticCB: FAILED, NOT IO_SUCCESS and SAT_READ_VERIFY_SECTORS(_EXT)!!!\n")); + } + else + { + SM_DBG1(("smsatSendDiagnosticCB: FAILED, NOT IO_SUCCESS and SAT_SMART_EXEUTE_OFF_LINE_IMMEDIATE!!!\n")); + } + } + + /* for debugging */ + if( statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) + { + if ( hostToDevFis->h.command == SAT_READ_VERIFY_SECTORS_EXT ) + { + SM_DBG1(("smsatSendDiagnosticCB: FAILED, Wrong FIS type 0x%x and SAT_READ_VERIFY_SECTORS(_EXT)!!!\n", statDevToHostFisHeader->fisType)); + } + else + { + SM_DBG1(("smsatSendDiagnosticCB: FAILED, Wrong FIS type 0x%x and SAT_SMART_EXEUTE_OFF_LINE_IMMEDIATE!!!\n",statDevToHostFisHeader->fisType)); + } + } + + /* for debugging */ + if ( (ataStatus & ERR_ATA_STATUS_MASK) || + (ataStatus & DF_ATA_STATUS_MASK) + ) + { + if ( hostToDevFis->h.command == SAT_READ_VERIFY_SECTORS_EXT ) + { + SM_DBG1(("smsatSendDiagnosticCB: FAILED, error status and SAT_READ_VERIFY_SECTORS(_EXT)!!!\n")); + } + else + { + SM_DBG1(("smsatSendDiagnosticCB: FAILED, error status and SAT_SMART_EXEUTE_OFF_LINE_IMMEDIATE!!!\n")); + } + } + + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + smsatProcessAbort(smRoot, + smOrgIORequest, + satOrgIOContext + ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + if ( (hostToDevFis->h.command == SAT_READ_VERIFY_SECTORS) || + (hostToDevFis->h.command == SAT_READ_VERIFY_SECTORS_EXT) ) + { + /* report using the original tiIOrequst */ + /* failed during sending SAT_READ_VERIFY_SECTORS(_EXT) */ + smsatSetSensePayload( pSense, + SCSI_SNSKEY_HARDWARE_ERROR, + 0, + SCSI_SNSCODE_LOGICAL_UNIT_FAILED_SELF_TEST, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + else + { + /* report using the original tiIOrequst */ + /* failed during sending SAT_SMART_EXEUTE_OFF_LINE_IMMEDIATE */ + smsatSetSensePayload( pSense, + SCSI_SNSKEY_HARDWARE_ERROR, + 0, + SCSI_SNSCODE_LOGICAL_UNIT_FAILED_SELF_TEST, + satOrgIOContext); + + if (hostToDevFis->d.lbaLow != 0x01 && hostToDevFis->d.lbaLow != 0x02) + { + /* no completion for background send diagnotic. It is done in satSendDiagnostic() */ + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + } + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + } + } + + /* processing success case */ + switch (hostToDevFis->h.command) + { + case SAT_READ_VERIFY_SECTORS: /* fall through */ + case SAT_READ_VERIFY_SECTORS_EXT: + SM_DBG5(("smsatSendDiagnosticCB: SAT_READ_VERIFY_SECTORS(_EXT) case\n")); + tdsmSingleThreadedEnter(smRoot, SM_EXTERNAL_IO_LOCK); + oneDeviceData->satVerifyState++; + tdsmSingleThreadedLeave(smRoot, SM_EXTERNAL_IO_LOCK); + SM_DBG5(("smsatSendDiagnosticCB: satVerifyState %d\n",oneDeviceData->satVerifyState)); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + /* done with internally genereated AT_READ_VERIFY_SECTORS(_EXT) */ + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + if (oneDeviceData->satVerifyState == 3) + { + /* reset satVerifyState */ + oneDeviceData->satVerifyState = 0; + /* return GOOD status */ + SM_DBG5(("smsatSendDiagnosticCB: return GOOD status\n")); + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + return; + } + else + { + /* prepare SAT_READ_VERIFY_SECTORS(_EXT) */ + satNewIntIo = smsatAllocIntIoResource( smRoot, + smOrgIORequest, + oneDeviceData, + 0, + satNewIntIo); + if (satNewIntIo == agNULL) + { + /* reset satVerifyState */ + oneDeviceData->satVerifyState = 0; + + /* failed as a part of sending SAT_READ_VERIFY_SECTORS(_EXT) */ + smsatSetSensePayload( pSense, + SCSI_SNSKEY_HARDWARE_ERROR, + 0, + SCSI_SNSCODE_LOGICAL_UNIT_FAILED_SELF_TEST, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + SM_DBG1(("smsatSendDiagnosticCB: momory allocation fails!!!\n")); + return; + } /* end of memory allocation failure */ + + /* + * Need to initialize all the fields within satIOContext + */ + + satNewIOContext = smsatPrepareNewIO( + satNewIntIo, + smOrgIORequest, + oneDeviceData, + scsiCmnd, + satOrgIOContext + ); + + if (oneDeviceData->satVerifyState == 1) + { + /* sending SAT_CHECK_POWER_MODE */ + status = smsatSendDiagnostic_1( smRoot, + &satNewIntIo->satIntSmIORequest, + satNewIOContext->psmDeviceHandle, + &satNewIntIo->satIntSmScsiXchg, + satNewIOContext); + } + else + { + /* oneDeviceData->satVerifyState == 2 */ + status = smsatSendDiagnostic_2( smRoot, + &satNewIntIo->satIntSmIORequest, + satNewIOContext->psmDeviceHandle, + &satNewIntIo->satIntSmScsiXchg, + satNewIOContext); + } + + if (status != SM_RC_SUCCESS) + { + /* sending SAT_READ_VERIFY_SECTORS(_EXT) fails */ + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satNewIntIo); + + /* failed during sending SAT_READ_VERIFY_SECTORS(_EXT) */ + smsatSetSensePayload( pSense, + SCSI_SNSKEY_HARDWARE_ERROR, + 0, + SCSI_SNSCODE_LOGICAL_UNIT_FAILED_SELF_TEST, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + /* reset satVerifyState */ + oneDeviceData->satVerifyState = 0; + SM_DBG1(("smsatSendDiagnosticCB: calling satSendDiagnostic_1 or _2 fails!!!\n")); + return; + } + } /* oneDeviceData->satVerifyState == 1 or 2 */ + + break; + case SAT_SMART: + if (hostToDevFis->h.features == SAT_SMART_EXEUTE_OFF_LINE_IMMEDIATE) + { + SM_DBG5(("smsatSendDiagnosticCB: SAT_SMART_EXEUTE_OFF_LINE_IMMEDIATE case\n")); + + oneDeviceData->satBGPendingDiag = agFALSE; + + if (hostToDevFis->d.lbaLow == 0x01 || hostToDevFis->d.lbaLow == 0x02) + { + /* for background send diagnostic, no completion here. It is done already. */ + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + /* done with AT_SMART_EXEUTE_OFF_LINE_IMMEDIATE */ + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + SM_DBG5(("smsatSendDiagnosticCB: returning but no IOCompleted\n")); + } + else + { + SM_DBG5(("smsatSendDiagnosticCB: returning good status for senddiagnostic\n")); + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + /* done with AT_SMART_EXEUTE_OFF_LINE_IMMEDIATE */ + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + } + } + break; + default: + SM_DBG1(("smsatSendDiagnosticCB: success but error default case command 0x%x!!!\n", hostToDevFis->h.command)); + /* unspecified case, return no sense and no addition info */ + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + break; + } + return; + +} + +osGLOBAL void +smsatStartStopUnitCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ) +{ + /* + In the process of StartStopUnit + Process FLUSH CACHE (EXT) + Process STANDBY + Process READ VERIFY SECTOR(S) EXT + Process MEDIA EJECT + */ +// tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; +// tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; +// tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; +// tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smIORequestBody_t *smOrgIORequestBody; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatIOContext_t *satNewIOContext; + smSatInternalIo_t *satIntIo; + smSatInternalIo_t *satNewIntIo = agNULL; +// satDeviceData_t *satDevData; + smDeviceData_t *oneDeviceData; + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + smIORequest_t *smOrgIORequest; + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + bit32 status; + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + + SM_DBG2(("smsatStartStopUnitCB: start\n")); + SM_DBG5(("smsatStartStopUnitCB:agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate smIOContext */ + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + if (satIntIo == agNULL) + { + SM_DBG4(("smsatStartStopUnitCB: External smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + smOrgIORequest = smIORequestBody->smIORequest; + pSense = satIOContext->pSense; + scsiCmnd = satIOContext->pScsiCmnd; + } + else + { + SM_DBG4(("smsatStartStopUnitCB: Internal smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + SM_DBG4(("smsatStartStopUnitCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + SM_DBG4(("smsatStartStopUnitCB: satOrgIOContext is NOT NULL\n")); + } + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + smOrgIORequest = (smIORequest_t *)smOrgIORequestBody->smIORequest; + + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatStartStopUnitCB: wrong. agFirstDword is NULL when error, status %d!!!\n", agIOStatus)); + + /* IMMED == 0 */ + if (!( scsiCmnd->cdb[1] & SCSI_IMMED_MASK)) + { + SM_DBG1(("smsatStartStopUnitCB: immed bit 0!!!\n")); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_COMMAND_SEQUENCE_ERROR, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + } + /* IMMED == 1 */ + if ( scsiCmnd->cdb[1] & SCSI_IMMED_MASK) + { + SM_DBG1(("smsatStartStopUnitCB: immed bit 1!!!\n")); + smsatSetDeferredSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_COMMAND_SEQUENCE_ERROR, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + } + + + + return; + } + + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* only agsaFisRegDeviceToHost_t is expected */ + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + } + /* + checking IO status, FIS type and error status + */ + if( agIOStatus != OSSA_IO_SUCCESS) + { + if( (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) || + ((ataStatus & ERR_ATA_STATUS_MASK) || (ataStatus & DF_ATA_STATUS_MASK)) + ) + { + /* for debugging */ + if( agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatStartStopUnitCB: FAILED, NOT IO_SUCCESS!!!\n")); + } + else if (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) + { + SM_DBG1(("smsatStartStopUnitCB: FAILED, Wrong FIS type 0x%x!!!\n",statDevToHostFisHeader->fisType)); + } + else if ( (ataStatus & ERR_ATA_STATUS_MASK) || + (ataStatus & DF_ATA_STATUS_MASK) + ) + { + SM_DBG1(("smsatStartStopUnitCB: FAILED, FAILED, error status!!!\n")); + } + + + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + smsatProcessAbort(smRoot, + smOrgIORequest, + satOrgIOContext + ); + + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + switch (hostToDevFis->h.command) + { + case SAT_FLUSH_CACHE: /* fall through */ + case SAT_FLUSH_CACHE_EXT: + SM_DBG1(("smsatStartStopUnitCB: SAT_FLUSH_CACHE(_EXT)!!!\n")); + /* check immed bit in scsi command */ + /* IMMED == 0 */ + if (!( scsiCmnd->cdb[1] & SCSI_IMMED_MASK)) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_COMMAND_SEQUENCE_ERROR, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + } + /* IMMED == 1 */ + if ( scsiCmnd->cdb[1] & SCSI_IMMED_MASK) + { + smsatSetDeferredSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_COMMAND_SEQUENCE_ERROR, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + } + break; + case SAT_STANDBY: + SM_DBG5(("smsatStartStopUnitCB: SAT_STANDBY\n")); + /* check immed bit in scsi command */ + /* IMMED == 0 */ + if (!( scsiCmnd->cdb[1] & SCSI_IMMED_MASK)) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_COMMAND_SEQUENCE_ERROR, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + } + /* IMMED == 1 */ + if ( scsiCmnd->cdb[1] & SCSI_IMMED_MASK) + { + smsatSetDeferredSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_COMMAND_SEQUENCE_ERROR, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + } + break; + case SAT_READ_VERIFY_SECTORS: /* fall through */ + case SAT_READ_VERIFY_SECTORS_EXT: + SM_DBG5(("smsatStartStopUnitCB: SAT_READ_VERIFY_SECTORS(_EXT)\n")); + /* IMMED == 0 */ + if (!( scsiCmnd->cdb[1] & SCSI_IMMED_MASK)) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_COMMAND_SEQUENCE_ERROR, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + } + /* IMMED == 1 */ + if ( scsiCmnd->cdb[1] & SCSI_IMMED_MASK) + { + smsatSetDeferredSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_COMMAND_SEQUENCE_ERROR, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + } + break; + case SAT_MEDIA_EJECT: + SM_DBG5(("smsatStartStopUnitCB: SAT_MEDIA_EJECT\n")); + /* IMMED == 0 */ + if (!( scsiCmnd->cdb[1] & SCSI_IMMED_MASK)) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_MEDIA_LOAD_OR_EJECT_FAILED, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + } + /* IMMED == 1 */ + if ( scsiCmnd->cdb[1] & SCSI_IMMED_MASK) + { + smsatSetDeferredSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_MEDIA_LOAD_OR_EJECT_FAILED, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + } + break; + default: + /* unspecified case, return no sense and no addition info */ + SM_DBG5(("smsatStartStopUnitCB: default command %d\n", hostToDevFis->h.command)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + break; + } /* switch */ + + return; + } /* error check */ + } + + /* ATA command completes sucessfully */ + switch (hostToDevFis->h.command) + { + case SAT_FLUSH_CACHE: /* fall through */ + case SAT_FLUSH_CACHE_EXT: + SM_DBG5(("smsatStartStopUnitCB: SAT_READ_VERIFY_SECTORS(_EXT) success case\n")); + + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + /* done with SAT_FLUSH_CACHE(_EXT) */ + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + /* at this point, successful SAT_READ_VERIFY_SECTORS(_EXT) + send SAT_SATNDBY + */ + satNewIntIo = smsatAllocIntIoResource( smRoot, + smOrgIORequest, + oneDeviceData, + 0, + satNewIntIo); + if (satNewIntIo == agNULL) + { + /* IMMED == 0 */ + if (!( scsiCmnd->cdb[1] & SCSI_IMMED_MASK)) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_COMMAND_SEQUENCE_ERROR, + satOrgIOContext); + } + else /* IMMED == 1 */ + { + smsatSetDeferredSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_COMMAND_SEQUENCE_ERROR, + satOrgIOContext); + } + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + SM_DBG1(("smsatStartStopUnitCB: momory allocation fails!!!\n")); + return; + } /* end of memory allocation failure */ + + /* + * Need to initialize all the fields within satIOContext + */ + + satNewIOContext = smsatPrepareNewIO( + satNewIntIo, + smOrgIORequest, + oneDeviceData, + scsiCmnd, + satOrgIOContext + ); + + /* sending SAT_STANDBY */ + status = smsatStartStopUnit_1( smRoot, + &satNewIntIo->satIntSmIORequest, + satNewIOContext->psmDeviceHandle, + &satNewIntIo->satIntSmScsiXchg, + satNewIOContext); + + if (status != SM_RC_SUCCESS) + { + /* sending SAT_CHECK_POWER_MODE fails */ + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satNewIntIo); + + /* IMMED == 0 */ + if (!( scsiCmnd->cdb[1] & SCSI_IMMED_MASK)) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_COMMAND_SEQUENCE_ERROR, + satOrgIOContext); + } + else /* IMMED == 1 */ + { + smsatSetDeferredSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_COMMAND_SEQUENCE_ERROR, + satOrgIOContext); + } + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + SM_DBG1(("smsatStartStopUnitCB: calling satStartStopUnit_1 fails!!!\n")); + return; + } + break; + case SAT_STANDBY: + SM_DBG5(("smsatStartStopUnitCB: SAT_STANDBY success case\n")); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + /* done with SAT_STANDBY */ + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + /* + if immed == 0, return good status + */ + /* IMMED == 0 */ + if (!( scsiCmnd->cdb[1] & SCSI_IMMED_MASK)) + { + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + } + oneDeviceData->satStopState = agTRUE; + break; + case SAT_READ_VERIFY_SECTORS: /* fall through */ + case SAT_READ_VERIFY_SECTORS_EXT: + SM_DBG5(("smsatStartStopUnitCB: SAT_READ_VERIFY_SECTORS(_EXT) success case\n")); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + /* done with SAT_READ_VERIFY_SECTORS(_EXT) */ + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + /* + if immed == 0, return good status + */ + if (!( scsiCmnd->cdb[1] & SCSI_IMMED_MASK)) + { + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + } + /* + if immed == 0, return good status + */ + /* + don't forget to check and set driver state; Active power state + */ + oneDeviceData->satStopState = agFALSE; + break; + case SAT_MEDIA_EJECT: + SM_DBG5(("smsatStartStopUnitCB: SAT_MEDIA_EJECT success case\n")); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + /* done with SAT_READ_VERIFY_SECTORS(_EXT) */ + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + /* + if immed == 0, return good status + */ + if (!( scsiCmnd->cdb[1] & SCSI_IMMED_MASK)) + { + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + } + break; + default: + SM_DBG1(("smsatStartStopUnitCB:success but error default case command 0x%x!!!\n", hostToDevFis->h.command)); + + /* unspecified case, return no sense and no addition info */ + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + break; + } + return; + +} + +osGLOBAL void +smsatWriteSame10CB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ) +{ + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smIORequestBody_t *smOrgIORequestBody; + smIORequestBody_t *smNewIORequestBody; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatIOContext_t *satNewIOContext; + smSatInternalIo_t *satIntIo; + smSatInternalIo_t *satNewIntIo = agNULL; + smDeviceData_t *oneDeviceData; + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + smIORequest_t *smOrgIORequest; + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + bit32 status; + bit32 sectorcount = 0; + bit32 lba = 0, tl = 0; + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + agsaFisSetDevBitsHeader_t *statSetDevBitFisHeader = agNULL; + + SM_DBG2(("smsatWriteSame10CB: start\n")); + SM_DBG5(("smsatWriteSame10CB: agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate smIOContext */ + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + + if (satIntIo == agNULL) + { + SM_DBG4(("smsatWriteSame10CB: External smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + smOrgIORequest = smIORequestBody->smIORequest; + pSense = satIOContext->pSense; + scsiCmnd = satIOContext->pScsiCmnd; + } + else + { + SM_DBG4(("smsatWriteSame10CB: Internal smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + SM_DBG4(("smsatWriteSame10CB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + SM_DBG4(("smsatWriteSame10CB: satOrgIOContext is NOT NULL\n")); + } + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + smOrgIORequest = (smIORequest_t *)smOrgIORequestBody->smIORequest; + + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + + + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatWriteSame10CB: wrong. agFirstDword is NULL when error, status %d!!!\n", agIOStatus)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* FP, DMA and PIO write */ + /* First, assumed to be Reg Device to Host FIS */ + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + } + + if (agIOStatus != OSSA_IO_SUCCESS) + { + if (statDevToHostFisHeader->fisType == SET_DEV_BITS_FIS) + { + statSetDevBitFisHeader = (agsaFisSetDevBitsHeader_t *)&(agFirstDword->D2H); + + /* Get ATA Status register */ + ataStatus = (statSetDevBitFisHeader->statusHi_Lo & 0x70); /* bits 4,5,6 */ + ataStatus = ataStatus | (statSetDevBitFisHeader->statusHi_Lo & 0x07); /* bits 0,1,2 */ + } + } + + if( agIOStatus != OSSA_IO_SUCCESS) + { + /* + checking IO status, FIS type and error status + FIS type should be either REG_DEV_TO_HOST_FIS or SET_DEV_BITS_FIS + */ + if ( ((statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) && + (statDevToHostFisHeader->fisType != SET_DEV_BITS_FIS)) || + ((ataStatus & ERR_ATA_STATUS_MASK) || (ataStatus & DF_ATA_STATUS_MASK)) + ) + { + /* for debugging */ + if( agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatWriteSame10CB: FAILED, NOT IO_SUCCESS!!!\n")); + } + else if (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) + { + SM_DBG1(("smsatWriteSame10CB: FAILED, Wrong FIS type 0x%x!!!\n",statDevToHostFisHeader->fisType)); + } + else if (statDevToHostFisHeader->fisType != SET_DEV_BITS_FIS) + { + SM_DBG1(("smsatWriteSame10CB: FAILED, Wrong FIS type 0x%x!!!\n",statDevToHostFisHeader->fisType)); + } + else if ( (ataStatus & ERR_ATA_STATUS_MASK) || + (ataStatus & DF_ATA_STATUS_MASK) + ) + { + SM_DBG1(("smsatWriteSame10CB: FAILED, FAILED, error status!!!\n")); + } + + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + smsatProcessAbort(smRoot, + smOrgIORequest, + satOrgIOContext + ); + + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + /* for debugging */ + switch (hostToDevFis->h.command) + { + case SAT_WRITE_DMA_EXT: + SM_DBG1(("smsatWriteSame10CB: SAT_WRITE_DMA_EXT!!!\n")); + break; + case SAT_WRITE_SECTORS_EXT: + SM_DBG1(("smsatWriteSame10CB: SAT_WRITE_SECTORS_EXT!!!\n")); + break; + case SAT_WRITE_FPDMA_QUEUED: + SM_DBG1(("smsatWriteSame10CB: SAT_WRITE_FPDMA_QUEUED!!!\n")); + break; + default: + SM_DBG1(("smsatWriteSame10CB: error default case command 0x%x!!!\n", hostToDevFis->h.command)); + break; + } + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } /* end error */ + } + + /* process success from this point on */ + /* + note: inefficient implementation until a single block can be manipulated + */ + + if (hostToDevFis->h.command == SAT_WRITE_DMA_EXT) + { + SM_DBG5(("smsatWriteSame10CB: SAT_WRITE_DMA_EXT success\n")); + } + else if (hostToDevFis->h.command == SAT_WRITE_SECTORS_EXT) + { + SM_DBG5(("smsatWriteSame10CB: SAT_WRITE_SECTORS_EXT success\n")); + } + else if (hostToDevFis->h.command == SAT_WRITE_FPDMA_QUEUED) + { + SM_DBG5(("smsatWriteSame10CB: SAT_WRITE_FPDMA_QUEUED success\n")); + } + else + { + SM_DBG1(("smsatWriteSame10CB: error case command 0x%x success!!!\n", hostToDevFis->h.command)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + /* free */ + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + /* + increment LBA by one, keeping the same sector count(1) + sends another ATA command with the changed parameters + */ + + tdsmSingleThreadedEnter(smRoot, SM_EXTERNAL_IO_LOCK); + oneDeviceData->satSectorDone++; + tdsmSingleThreadedLeave(smRoot, SM_EXTERNAL_IO_LOCK); + + SM_DBG1(("smsatWriteSame10CB: sectordone %d!!!\n", oneDeviceData->satSectorDone)); + + lba = (scsiCmnd->cdb[2] << (8*3)) + (scsiCmnd->cdb[3] << (8*2)) + + (scsiCmnd->cdb[4] << 8) + scsiCmnd->cdb[5]; + tl = (scsiCmnd->cdb[7] << 8) + scsiCmnd->cdb[8]; + + SM_DBG5(("smsatWriteSame10CB: lba 0x%x tl 0x%x\n", lba, tl)); + + if (tl == 0) + { + /* (oneDeviceData->satMaxUserAddrSectors - 1) - lba*/ + sectorcount = (0x0FFFFFFF - 1) - lba; + } + else + { + sectorcount = tl; + } + + if (sectorcount <= 0) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + SM_DBG1(("smsatWriteSame10CB: incorrect sectorcount 0x%x!!!\n", sectorcount)); + return; + } + + if (sectorcount == oneDeviceData->satSectorDone) + { + /* + done with writesame + */ + SM_DBG1(("smsatWriteSame10CB: return writesame done!!!\n")); + oneDeviceData->satSectorDone = 0; + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + } + else + { + /* sends another ATA command */ + if (hostToDevFis->h.command == SAT_WRITE_DMA_EXT) + { + SM_DBG1(("smsatWriteSame10CB: sends another SAT_WRITE_DMA_EXT!!!\n")); + } + else if (hostToDevFis->h.command == SAT_WRITE_SECTORS_EXT) + { + SM_DBG1(("smsatWriteSame10CB: sends another SAT_WRITE_SECTORS_EXT!!!\n")); + } + else if (hostToDevFis->h.command == SAT_WRITE_FPDMA_QUEUED) + { + SM_DBG1(("smsatWriteSame10CB: sends another SAT_WRITE_FPDMA_QUEUED!!!\n")); + } + + satNewIntIo = smsatAllocIntIoResource( smRoot, + smOrgIORequest, + oneDeviceData, + 0, + satNewIntIo); + if (satNewIntIo == agNULL) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + SM_DBG1(("smsatWriteSame10CB: momory allocation fails!!!\n")); + return; + } /* end memory allocation */ + + /* the one to be used */ + smNewIORequestBody = satNewIntIo->satIntRequestBody; + satNewIOContext = &smNewIORequestBody->transport.SATA.satIOContext; + + satNewIOContext->pSatDevData = oneDeviceData; + satNewIOContext->pFis = &smNewIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev; + satNewIOContext->pScsiCmnd = &satNewIntIo->satIntSmScsiXchg.scsiCmnd; + /* saves scsi command for LBA and number of blocks */ + sm_memcpy(satNewIOContext->pScsiCmnd, scsiCmnd, sizeof(smIniScsiCmnd_t)); + satNewIOContext->pSense = &smNewIORequestBody->transport.SATA.sensePayload; + satNewIOContext->pSmSenseData = &smNewIORequestBody->transport.SATA.smSenseData; + satNewIOContext->pSmSenseData->senseData = satNewIOContext->pSense; + satNewIOContext->smRequestBody = satNewIntIo->satIntRequestBody; + satNewIOContext->interruptContext = satNewIOContext->interruptContext; + satNewIOContext->satIntIoContext = satNewIntIo; + satNewIOContext->psmDeviceHandle = satIOContext->psmDeviceHandle; + /* saves smScsiXchg; only for writesame10() */ + satNewIOContext->smScsiXchg = satOrgIOContext->smScsiXchg; + + if (hostToDevFis->h.command == SAT_WRITE_DMA_EXT) + { + status = smsatWriteSame10_1( smRoot, + &satNewIntIo->satIntSmIORequest, + satNewIOContext->psmDeviceHandle, + &satNewIntIo->satIntSmScsiXchg, + satNewIOContext, + lba + oneDeviceData->satSectorDone + ); + } + else if (hostToDevFis->h.command == SAT_WRITE_SECTORS_EXT) + { + status = smsatWriteSame10_2( smRoot, + &satNewIntIo->satIntSmIORequest, + satNewIOContext->psmDeviceHandle, + &satNewIntIo->satIntSmScsiXchg, + satNewIOContext, + lba + oneDeviceData->satSectorDone + ); + } + else if (hostToDevFis->h.command == SAT_WRITE_FPDMA_QUEUED) + { + status = smsatWriteSame10_3( smRoot, + &satNewIntIo->satIntSmIORequest, + satNewIOContext->psmDeviceHandle, + &satNewIntIo->satIntSmScsiXchg, + satNewIOContext, + lba + oneDeviceData->satSectorDone + ); + } + else + { + status = tiError; + SM_DBG1(("smsatWriteSame10CB: sucess but error in command 0x%x!!!\n", hostToDevFis->h.command)); + } + + if (status != SM_RC_SUCCESS) + { + /* sending ATA command fails */ + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satNewIntIo); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + SM_DBG1(("smsatWriteSame10CB:calling satWriteSame10_1 fails!!!\n")); + return; + } /* end send fails */ + + } /* end sends another ATA command */ + + return; + +} + +osGLOBAL void +smsatLogSenseCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smIORequestBody_t *smOrgIORequestBody; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatInternalIo_t *satIntIo; +// satDeviceData_t *satDevData; + smDeviceData_t *oneDeviceData; + + smScsiRspSense_t *pSense; + smIORequest_t *smOrgIORequest; + + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + smScsiInitiatorRequest_t *smScsiRequest; /* tiScsiXchg */ + smScsiInitiatorRequest_t *smOrgScsiRequest; /* tiScsiXchg */ + satReadLogExtSelfTest_t *virtAddr1; + satSmartReadLogSelfTest_t *virtAddr2; + bit8 *pLogPage; + bit8 LogPage[SELFTEST_RESULTS_LOG_PAGE_LENGTH]; + bit8 SelfTestExecutionStatus = 0; + bit32 i = 0; + + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + agsaFisRegD2HData_t statDevToHostFisData; + smIniScsiCmnd_t *scsiCmnd; + bit32 allocationLen = 0; + + SM_DBG2(("smsatLogSenseCB: start\n")); + SM_DBG5(("smsatLogSenseCB:agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate smIOContext */ + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + if (satIOContext == agNULL) + { + SM_DBG1(("smsatLogSenseCB: satIOContext is NULL\n")); + return; + } + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + + if (satIntIo == agNULL) + { + SM_DBG4(("smsatLogSenseCB: External smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + smOrgIORequest = smIORequestBody->smIORequest; + pSense = satOrgIOContext->pSense; + smOrgScsiRequest = satOrgIOContext->smScsiXchg; + /* SCSI command response payload to OS layer */ + pLogPage = (bit8 *) smOrgScsiRequest->sglVirtualAddr; + /* ATA command response payload */ + smScsiRequest = satOrgIOContext->smScsiXchg; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + else + { + SM_DBG4(("smsatLogSenseCB: Internal smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + smOrgIORequest = (smIORequest_t *)smOrgIORequestBody->smIORequest; + + pSense = satOrgIOContext->pSense; + smOrgScsiRequest = satOrgIOContext->smScsiXchg; + /* SCSI command response payload to OS layer */ + pLogPage = (bit8 *) smOrgScsiRequest->sglVirtualAddr; + /* ATA command response payload */ + smScsiRequest = (smScsiInitiatorRequest_t *)&(satIntIo->satIntSmScsiXchg); + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatLogSenseCB: wrong. agFirstDword is NULL when error, status %d!!!\n", agIOStatus)); + tdsmIOCompletedCB( + smRoot, + smOrgIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* non-data and pio read -> device to host and pio setup fis are expected */ + /* + first, assumed to be Reg Device to Host FIS + This is OK to just find fis type + */ + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + } + + if( agIOStatus != OSSA_IO_SUCCESS) + { + if ( ((statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) && + (statDevToHostFisHeader->fisType != PIO_SETUP_DEV_TO_HOST_FIS)) || + ((ataStatus & ERR_ATA_STATUS_MASK) || (ataStatus & DF_ATA_STATUS_MASK)) + ) + { + /* for debugging */ + if( agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatLogSenseCB: FAILED, NOT IO_SUCCESS!!!\n")); + } + else if (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) + { + SM_DBG1(("smsatLogSenseCB: FAILED, Wrong FIS type 0x%x!!!\n",statDevToHostFisHeader->fisType)); + } + else if (statDevToHostFisHeader->fisType != PIO_SETUP_DEV_TO_HOST_FIS) + { + SM_DBG1(("smsatLogSenseCB: FAILED, Wrong FIS type 0x%x!!!\n",statDevToHostFisHeader->fisType)); + } + else if ( (ataStatus & ERR_ATA_STATUS_MASK) || + (ataStatus & DF_ATA_STATUS_MASK) + ) + { + SM_DBG1(("smsatLogSenseCB: FAILED, FAILED, error status!!!\n")); + } + + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + smsatProcessAbort(smRoot, + smOrgIORequest, + satOrgIOContext + ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + /* for debugging */ + if (hostToDevFis->h.command == SAT_READ_LOG_EXT) + { + SM_DBG1(("smsatLogSenseCB: SAT_READ_LOG_EXT failed!!!\n")); + } + else if (hostToDevFis->h.command == SAT_SMART) + { + if (hostToDevFis->h.features == SAT_SMART_READ_LOG) + { + SM_DBG1(("smsatLogSenseCB: SAT_SMART_READ_LOG failed!!!\n")); + } + else if (hostToDevFis->h.features == SAT_SMART_RETURN_STATUS) + { + SM_DBG1(("smsatLogSenseCB: SAT_SMART_RETURN_STATUS failed!!!\n")); + } + else + { + SM_DBG1(("smsatLogSenseCB: error unknown command 0x%x feature 0x%x!!!\n", hostToDevFis->h.command, hostToDevFis->h.features)); + } + } + else + { + SM_DBG1(("smsatLogSenseCB: error default case command 0x%x!!!\n", hostToDevFis->h.command)); + } + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + + } /* error checking */ + } + + /* prcessing the success case */ + saFrameReadBlock(agRoot, agParam, 0, &statDevToHostFisData, sizeof(agsaFisRegD2HData_t)); + + allocationLen = (scsiCmnd->cdb[7] << 8) + scsiCmnd->cdb[8]; + allocationLen = MIN(allocationLen, scsiCmnd->expDataLength); + SM_DBG5(("smsatLogSenseCB: allocationLen in CDB %d 0x%x\n", allocationLen,allocationLen)); + + + if (hostToDevFis->h.command == SAT_READ_LOG_EXT) + { + SM_DBG5(("smsatLogSenseCB: SAT_READ_LOG_EXT success\n")); + + /* process log data and sends it to upper */ + + /* ATA: Extended Self-Test Log */ + virtAddr1 = (satReadLogExtSelfTest_t *)(smScsiRequest->sglVirtualAddr); + /* + ATA/ATAPI VOLII, p197, 287 + self-test execution status (4 bits); ((virtAddr1->byte[5] & 0xF0) >> 4) + */ + SelfTestExecutionStatus = (bit8)(((virtAddr1->byte[5] & 0xF0) >> 4)); + + /* fills in the log page from ATA log page */ + /* SPC-4, 7.2.10, Table 216, 217, p 259 - 260 */ + LogPage[0] = 0x10; /* page code */ + LogPage[1] = 0; + LogPage[2] = 0x01; /* 0x190, page length */ + LogPage[3] = 0x90; + + /* SPC-4, Table 217 */ + LogPage[4] = 0; /* Parameter Code */ + LogPage[5] = 0x01; /* Parameter Code, unspecfied but ... */ + LogPage[6] = 3; /* unspecified but ... */ + LogPage[7] = 0x10; /* Parameter Length */ + LogPage[8] = (bit8)(0 | ((virtAddr1->byte[5] & 0xF0) >> 4)); /* Self Test Code and Self-Test Result */ + LogPage[9] = 0; /* self test number */ + LogPage[10] = virtAddr1->byte[7]; /* time stamp, MSB */ + LogPage[11] = virtAddr1->byte[6]; /* time stamp, LSB */ + + LogPage[12] = 0; /* address of first failure MSB*/ + LogPage[13] = 0; /* address of first failure */ + LogPage[14] = virtAddr1->byte[14]; /* address of first failure */ + LogPage[15] = virtAddr1->byte[13]; /* address of first failure */ + LogPage[16] = virtAddr1->byte[12]; /* address of first failure */ + LogPage[17] = virtAddr1->byte[11]; /* address of first failure */ + LogPage[18] = virtAddr1->byte[10]; /* address of first failure */ + LogPage[19] = virtAddr1->byte[9]; /* address of first failure LSB */ + + /* SAT rev8 Table75, p 76 */ + switch (SelfTestExecutionStatus) + { + case 0: + LogPage[20] = 0 | SCSI_SNSKEY_NO_SENSE; + LogPage[21] = (SCSI_SNSCODE_NO_ADDITIONAL_INFO >> 8) & 0xFF; + LogPage[22] = SCSI_SNSCODE_NO_ADDITIONAL_INFO & 0xFF; + break; + case 1: + LogPage[20] = 0 | SCSI_SNSKEY_ABORTED_COMMAND; + LogPage[21] = (SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN >> 8) & 0xFF; + LogPage[22] = 0x81; + break; + case 2: + LogPage[20] = 0 | SCSI_SNSKEY_ABORTED_COMMAND; + LogPage[21] = (SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN >> 8) & 0xFF; + LogPage[22] = 0x82; + break; + case 3: + LogPage[20] = 0 | SCSI_SNSKEY_ABORTED_COMMAND; + LogPage[21] = (SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN >> 8) & 0xFF; + LogPage[22] = 0x83; + break; + case 4: + LogPage[20] = 0 | SCSI_SNSKEY_HARDWARE_ERROR; + LogPage[21] = (SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN >> 8) & 0xFF; + LogPage[22] = 0x84; + break; + case 5: + LogPage[20] = 0 | SCSI_SNSKEY_HARDWARE_ERROR; + LogPage[21] = (SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN >> 8) & 0xFF; + LogPage[22] = 0x85; + break; + case 6: + LogPage[20] = 0 | SCSI_SNSKEY_HARDWARE_ERROR; + LogPage[21] = (SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN >> 8) & 0xFF; + LogPage[22] = 0x86; + break; + case 7: + LogPage[20] = 0 | SCSI_SNSKEY_MEDIUM_ERROR; + LogPage[21] = (SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN >> 8) & 0xFF; + LogPage[22] = 0x87; + break; + case 8: + LogPage[20] = 0 | SCSI_SNSKEY_HARDWARE_ERROR; + LogPage[21] = (SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN >> 8) & 0xFF; + LogPage[22] = 0x88; + break; + case 9: /* fall through */ + case 10:/* fall through */ + case 11:/* fall through */ + case 12:/* fall through */ + case 13:/* fall through */ + case 14: + LogPage[20] = 0 | SCSI_SNSKEY_NO_SENSE; + LogPage[21] = (SCSI_SNSCODE_NO_ADDITIONAL_INFO >> 8) & 0xFF; + LogPage[22] = SCSI_SNSCODE_NO_ADDITIONAL_INFO & 0xFF; + break; + case 15: + LogPage[20] = 0 | SCSI_SNSKEY_NO_SENSE; + LogPage[21] = (SCSI_SNSCODE_NO_ADDITIONAL_INFO >> 8) & 0xFF; + LogPage[22] = SCSI_SNSCODE_NO_ADDITIONAL_INFO & 0xFF; + break; + default: + SM_DBG1(("smsatLogSenseCB: Error, incorrect SelfTestExecutionStatus 0x%x!!!\n", SelfTestExecutionStatus)); + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + return; + } + + LogPage[23] = 0; /* vendor specific */ + + /* the rest of Self-test results log */ + /* 403 is from SPC-4, 7.2.10, Table 216, p 259*/ + for (i=24;i<=403;i++) + { + LogPage[i] = 0; /* vendor specific */ + } + + sm_memcpy(pLogPage, LogPage, MIN(allocationLen, SELFTEST_RESULTS_LOG_PAGE_LENGTH)); + if (SELFTEST_RESULTS_LOG_PAGE_LENGTH < allocationLen) + { + SM_DBG6(("smsatLogSenseCB: 1st underrun allocationLen %d len %d \n", allocationLen, SELFTEST_RESULTS_LOG_PAGE_LENGTH)); + + /* underrun */ + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == satIntIo->satOrgSmIORequest */ + smIOUnderRun, + allocationLen - SELFTEST_RESULTS_LOG_PAGE_LENGTH, + agNULL, + satOrgIOContext->interruptContext ); + + } + else + { + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext); + } + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + return; + } + else if (hostToDevFis->h.command == SAT_SMART) + { + if (hostToDevFis->h.features == SAT_SMART_READ_LOG) + { + SM_DBG5(("smsatLogSenseCB: SAT_SMART_READ_LOG success\n")); + /* process log data and sends it to upper */ + + /* ATA: Extended Self-Test Log */ + virtAddr2 = (satSmartReadLogSelfTest_t *)(smScsiRequest->sglVirtualAddr); + /* + SPC-4, p197, 287 + self-test execution status (4 bits); ((virtAddr2->byte[3] & 0xF0) >> 4) + */ + SelfTestExecutionStatus = (bit8)(((virtAddr2->byte[3] & 0xF0) >> 4)); + + /* fills in the log page from ATA log page */ + /* SPC-4, 7.2.10, Table 216, 217, p 259 - 260 */ + LogPage[0] = 0x10; /* page code */ + LogPage[1] = 0; + LogPage[2] = 0x01; /* 0x190, page length */ + LogPage[3] = 0x90; /* 0x190, page length */ + + /* SPC-4, Table 217 */ + LogPage[4] = 0; /* Parameter Code */ + LogPage[5] = 0x01; /* Parameter Code unspecfied but ... */ + LogPage[6] = 3; /* unspecified but ... */ + LogPage[7] = 0x10; /* Parameter Length */ + LogPage[8] = (bit8)(0 | ((virtAddr2->byte[3] & 0xF0) >> 4)); /* Self Test Code and Self-Test Result */ + LogPage[9] = 0; /* self test number */ + LogPage[10] = virtAddr2->byte[5]; /* time stamp, MSB */ + LogPage[11] = virtAddr2->byte[4]; /* time stamp, LSB */ + + LogPage[12] = 0; /* address of first failure MSB*/ + LogPage[13] = 0; /* address of first failure */ + LogPage[14] = 0; /* address of first failure */ + LogPage[15] = 0; /* address of first failure */ + LogPage[16] = virtAddr2->byte[10]; /* address of first failure */ + LogPage[17] = virtAddr2->byte[9]; /* address of first failure */ + LogPage[18] = virtAddr2->byte[8]; /* address of first failure */ + LogPage[19] = virtAddr2->byte[7]; /* address of first failure LSB */ + + /* SAT rev8 Table75, p 76 */ + switch (SelfTestExecutionStatus) + { + case 0: + LogPage[20] = 0 | SCSI_SNSKEY_NO_SENSE; + LogPage[21] = (SCSI_SNSCODE_NO_ADDITIONAL_INFO >> 8) & 0xFF; + LogPage[22] = SCSI_SNSCODE_NO_ADDITIONAL_INFO & 0xFF; + break; + case 1: + LogPage[20] = 0 | SCSI_SNSKEY_ABORTED_COMMAND; + LogPage[21] = (SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN >> 8) & 0xFF; + LogPage[22] = 0x81; + break; + case 2: + LogPage[20] = 0 | SCSI_SNSKEY_ABORTED_COMMAND; + LogPage[21] = (SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN >> 8) & 0xFF; + LogPage[22] = 0x82; + break; + case 3: + LogPage[20] = 0 | SCSI_SNSKEY_ABORTED_COMMAND; + LogPage[21] = (SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN >> 8) & 0xFF; + LogPage[22] = 0x83; + break; + case 4: + LogPage[20] = 0 | SCSI_SNSKEY_HARDWARE_ERROR; + LogPage[21] = (SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN >> 8) & 0xFF; + LogPage[22] = 0x84; + break; + case 5: + LogPage[20] = 0 | SCSI_SNSKEY_HARDWARE_ERROR; + LogPage[21] = (SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN >> 8) & 0xFF; + LogPage[22] = 0x85; + break; + case 6: + LogPage[20] = 0 | SCSI_SNSKEY_HARDWARE_ERROR; + LogPage[21] = (SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN >> 8) & 0xFF; + LogPage[22] = 0x86; + break; + case 7: + LogPage[20] = 0 | SCSI_SNSKEY_MEDIUM_ERROR; + LogPage[21] = (SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN >> 8) & 0xFF; + LogPage[22] = 0x87; + break; + case 8: + LogPage[20] = 0 | SCSI_SNSKEY_HARDWARE_ERROR; + LogPage[21] = (SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN >> 8) & 0xFF; + LogPage[22] = 0x88; + break; + case 9: /* fall through */ + case 10:/* fall through */ + case 11:/* fall through */ + case 12:/* fall through */ + case 13:/* fall through */ + case 14: + /* unspecified */ + LogPage[20] = 0 | SCSI_SNSKEY_NO_SENSE; + LogPage[21] = (SCSI_SNSCODE_NO_ADDITIONAL_INFO >> 8) & 0xFF; + LogPage[22] = SCSI_SNSCODE_NO_ADDITIONAL_INFO & 0xFF; + break; + case 15: + LogPage[20] = 0 | SCSI_SNSKEY_NO_SENSE; + LogPage[21] = (SCSI_SNSCODE_NO_ADDITIONAL_INFO >> 8) & 0xFF; + LogPage[22] = SCSI_SNSCODE_NO_ADDITIONAL_INFO & 0xFF; + break; + default: + SM_DBG1(("smsatLogSenseCB: Error, incorrect SelfTestExecutionStatus 0x%x!!!\n", SelfTestExecutionStatus)); + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + return; + } + + LogPage[23] = 0; /* vendor specific */ + + /* the rest of Self-test results log */ + /* 403 is from SPC-4, 7.2.10, Table 216, p 259*/ + for (i=24;i<=403;i++) + { + LogPage[i] = 0; /* vendor specific */ + } + + sm_memcpy(pLogPage, LogPage, MIN(allocationLen, SELFTEST_RESULTS_LOG_PAGE_LENGTH)); + if (SELFTEST_RESULTS_LOG_PAGE_LENGTH < allocationLen) + { + SM_DBG6(("smsatLogSenseCB: 2nd underrun allocationLen %d len %d \n", allocationLen, SELFTEST_RESULTS_LOG_PAGE_LENGTH)); + + /* underrun */ + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == satIntIo->satOrgSmIORequest */ + smIOUnderRun, + allocationLen - SELFTEST_RESULTS_LOG_PAGE_LENGTH, + agNULL, + satOrgIOContext->interruptContext ); + + } + else + { + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext); + } + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + return; + } + else if (hostToDevFis->h.features == SAT_SMART_RETURN_STATUS) + { + SM_DBG5(("smsatLogSenseCB: SAT_SMART_RETURN_STATUS success\n")); + + /* fills in the log page from ATA output */ + /* SPC-4, 7.2.5, Table 209, 211, p 255 */ + LogPage[0] = 0x2F; /* page code unspecified */ + LogPage[1] = 0; /* reserved */ + LogPage[2] = 0; /* page length */ + LogPage[3] = 0x07; /* page length */ + + /* + SPC-4, 7.2.5, Table 211, p 255 + no vendor specific field + */ + LogPage[4] = 0; /* Parameter Code */ + LogPage[5] = 0; /* Parameter Code unspecfied but to do: */ + LogPage[6] = 0; /* unspecified */ + LogPage[7] = 0x03; /* Parameter length, unspecified */ + + /* SAT rev8, 10.2.3.1 Table 72, p 73 */ + if (statDevToHostFisData.lbaMid == 0x4F || statDevToHostFisData.lbaHigh == 0xC2) + { + LogPage[8] = 0; /* Sense code */ + LogPage[9] = 0; /* Sense code qualifier */ + } + else if (statDevToHostFisData.lbaMid == 0xF4 || statDevToHostFisData.lbaHigh == 0x2C) + { + LogPage[8] = 0x5D; /* Sense code */ + LogPage[9] = 0x10; /* Sense code qualifier */ + } + + /* Assumption: No support for SCT */ + LogPage[10] = 0xFF; /* Most Recent Temperature Reading */ + + sm_memcpy(pLogPage, LogPage, MIN(allocationLen, INFORMATION_EXCEPTIONS_LOG_PAGE_LENGTH)); + if (INFORMATION_EXCEPTIONS_LOG_PAGE_LENGTH < allocationLen) + { + SM_DBG6(("smsatLogSenseCB: 3rd underrun allocationLen %d len %d \n", allocationLen, INFORMATION_EXCEPTIONS_LOG_PAGE_LENGTH)); + + /* underrun */ + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == satIntIo->satOrgSmIORequest */ + smIOUnderRun, + allocationLen - INFORMATION_EXCEPTIONS_LOG_PAGE_LENGTH, + agNULL, + satOrgIOContext->interruptContext ); + + } + else + { + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext); + } + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + + return; + } + else + { + SM_DBG1(("smsatLogSenseCB: error unknown command success 0x%x feature 0x%x!!!\n", hostToDevFis->h.command, hostToDevFis->h.features)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + return; + } + } + else + { + SM_DBG1(("smsatLogSenseCB: error unknown command success 0x%x!!!\n", hostToDevFis->h.command)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + return; + } + + return; +} + +osGLOBAL void +smsatSMARTEnableCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ) +{ +// tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; +// tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; +// tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; +// tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smIORequestBody_t *smOrgIORequestBody; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatIOContext_t *satNewIOContext; + smSatInternalIo_t *satIntIo; + smSatInternalIo_t *satNewIntIo = agNULL; +// satDeviceData_t *satDevData; + smDeviceData_t *oneDeviceData; + smIniScsiCmnd_t *scsiCmnd; + smIORequest_t *smOrgIORequest; + bit32 status; + + SM_DBG2(("smsatSMARTEnableCB: start\n")); + SM_DBG4(("smsatSMARTEnableCB:agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate tiIOContext */ + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + /*ttttttthe one */ + if (satIntIo == agNULL) + { + SM_DBG4(("smsatSMARTEnableCB: External smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + smOrgIORequest = smIORequestBody->smIORequest; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + else + { + SM_DBG4(("smsatSMARTEnableCB: Internal smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + SM_DBG4(("smsatSMARTEnableCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + SM_DBG4(("smsatSMARTEnableCB: satOrgIOContext is NOT NULL\n")); + } + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + smOrgIORequest = (smIORequest_t *)smOrgIORequestBody->smIORequest; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatSMARTEnableCB: wrong. agFirstDword is NULL when error, status %d!!!\n", agIOStatus)); + tdsmIOCompletedCB( + smRoot, + smOrgIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + /* + checking IO status, FIS type and error status + */ + if (agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatSMARTEnableCB: not success status, status %d!!!\n", agIOStatus)); + tdsmIOCompletedCB( + smRoot, + smOrgIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + /* process success case */ + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + satNewIntIo = smsatAllocIntIoResource( smRoot, + smOrgIORequest, + oneDeviceData, + 512, + satNewIntIo); + if (satNewIntIo == agNULL) + { + tdsmIOCompletedCB( + smRoot, + smOrgIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + return; + } + satNewIOContext = smsatPrepareNewIO( + satNewIntIo, + smOrgIORequest, + oneDeviceData, + scsiCmnd, + satOrgIOContext + ); + status = smsatLogSense_1(smRoot, + &satNewIntIo->satIntSmIORequest, + satNewIOContext->psmDeviceHandle, + &satNewIntIo->satIntSmScsiXchg, + satNewIOContext); + if (status != SM_RC_SUCCESS) + { + /* sending SAT_CHECK_POWER_MODE fails */ + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satNewIntIo); + tdsmIOCompletedCB( + smRoot, + smOrgIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + return; + } + return; +} + +osGLOBAL void +smsatModeSelect6n10CB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ) +{ + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smIORequestBody_t *smOrgIORequestBody; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatIOContext_t *satNewIOContext; + smSatInternalIo_t *satIntIo; + smSatInternalIo_t *satNewIntIo = agNULL; +// satDeviceData_t *satDevData; + smDeviceData_t *oneDeviceData; + + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + smIORequest_t *smOrgIORequest; + + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + bit32 status; + smScsiInitiatorRequest_t *smScsiRequest; /* smScsiXchg */ + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + + SM_DBG2(("smsatModeSelect6n10CB: start\n")); + SM_DBG5(("smsatModeSelect6n10CB: agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate smIOContext */ + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + + if (satIntIo == agNULL) + { + SM_DBG4(("smsatModeSelect6n10CB: External smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + smOrgIORequest = smIORequestBody->smIORequest; + smScsiRequest = satOrgIOContext->smScsiXchg; + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + else + { + SM_DBG4(("smsatModeSelect6n10CB: Internal smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + SM_DBG4(("smsatModeSelect6n10CB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + SM_DBG4(("smsatModeSelect6n10CB: satOrgIOContext is NOT NULL\n")); + } + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + smOrgIORequest = (smIORequest_t *)smOrgIORequestBody->smIORequest; + + smScsiRequest = satOrgIOContext->smScsiXchg; + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatModeSelect6n10CB: wrong. agFirstDword is NULL when error, status %d!!!\n", agIOStatus)); + tdsmIOCompletedCB( + smRoot, + smOrgIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* only agsaFisRegDeviceToHost_t is expected */ + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + } + + if (agIOStatus != OSSA_IO_SUCCESS) + { + if ( (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) || + ((ataStatus & ERR_ATA_STATUS_MASK) || (ataStatus & DF_ATA_STATUS_MASK)) + ) + { + /* for debugging */ + if( agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatModeSelect6n10CB: FAILED, NOT IO_SUCCESS!!!\n")); + } + else if (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) + { + SM_DBG1(("smsatModeSelect6n10CB: FAILED, Wrong FIS type 0x%x!!!\n",statDevToHostFisHeader->fisType)); + } + else if ( (ataStatus & ERR_ATA_STATUS_MASK) || + (ataStatus & DF_ATA_STATUS_MASK) + ) + { + SM_DBG1(("smsatModeSelect6n10CB: FAILED, FAILED, error status!!!\n")); + } + + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + smsatProcessAbort(smRoot, + smOrgIORequest, + satOrgIOContext + ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + /* for debugging */ + if (hostToDevFis->h.command == SAT_SET_FEATURES) + { + if ((hostToDevFis->h.features == 0x82) || (hostToDevFis->h.features == 0x02)) + { + SM_DBG1(("smsatModeSelect6n10CB: 1 SAT_SET_FEATURES failed, feature 0x%x!!!\n", hostToDevFis->h.features)); + } + else if ((hostToDevFis->h.features == 0xAA) || (hostToDevFis->h.features == 0x55)) + { + SM_DBG1(("smsatModeSelect6n10CB: 2 SAT_SET_FEATURES failed, feature 0x%x!!!\n", hostToDevFis->h.features)); + } + else + { + SM_DBG1(("smsatModeSelect6n10CB: error unknown command 0x%x feature 0x%x!!!\n", hostToDevFis->h.command, hostToDevFis->h.features)); + } + } + else if (hostToDevFis->h.command == SAT_SMART) + { + if ((hostToDevFis->h.features == SAT_SMART_ENABLE_OPERATIONS) || (hostToDevFis->h.features == SAT_SMART_DISABLE_OPERATIONS)) + { + SM_DBG1(("smsatModeSelect6n10CB: SAT_SMART_ENABLE/DISABLE_OPERATIONS failed, feature 0x%x!!!\n", hostToDevFis->h.features)); + } + else + { + SM_DBG1(("smsatModeSelect6n10CB: error unknown command 0x%x feature 0x%x!!!\n", hostToDevFis->h.command, hostToDevFis->h.features)); + } + } + else + { + SM_DBG1(("smsatModeSelect6n10CB: error default case command 0x%x!!!\n", hostToDevFis->h.command)); + } + + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } /* error checking */ + } + + + /* prcessing the success case */ + + + if (hostToDevFis->h.command == SAT_SET_FEATURES) + { + if ((hostToDevFis->h.features == 0x82) || (hostToDevFis->h.features == 0x02)) + { + SM_DBG5(("smsatModeSelect6n10CB: 1 SAT_SET_FEATURES success, feature 0x%x\n", hostToDevFis->h.features)); + if (hostToDevFis->h.features == 0x02) + { + /* enable write cache */ + oneDeviceData->satWriteCacheEnabled = agTRUE; + } + else + { + /* disable write cache */ + oneDeviceData->satWriteCacheEnabled = agFALSE; + } + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + satNewIntIo = smsatAllocIntIoResource( smRoot, + smOrgIORequest, + oneDeviceData, + 0, + satNewIntIo); + if (satNewIntIo == agNULL) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + SM_DBG1(("smsatModeSelect6n10CB: momory allocation fails!!!\n")); + return; + } /* end memory allocation */ + + satNewIOContext = smsatPrepareNewIO( + satNewIntIo, + smOrgIORequest, + oneDeviceData, + scsiCmnd, + satOrgIOContext + ); + /* sends either ATA SET FEATURES based on DRA bit */ + status = smsatModeSelect6n10_1( smRoot, + &satNewIntIo->satIntSmIORequest, + satNewIOContext->psmDeviceHandle, + smScsiRequest, /* orginal from OS layer */ + satNewIOContext + ); + + if (status != SM_RC_SUCCESS) + { + /* sending ATA command fails */ + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satNewIntIo); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + SM_DBG1(("smsatModeSelect6n10CB: calling satModeSelect6_1 fails!!!\n")); + return; + } /* end send fails */ + return; + } + else if ((hostToDevFis->h.features == 0xAA) || (hostToDevFis->h.features == 0x55)) + { + SM_DBG5(("smsatModeSelect6n10CB: 2 SAT_SET_FEATURES success, feature 0x%x\n", hostToDevFis->h.features)); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + /* return stat_good */ + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + return; + } + else + { + SM_DBG1(("smsatModeSelect6n10CB: error unknown command success 0x%x feature 0x%x!!!\n", hostToDevFis->h.command, hostToDevFis->h.features)); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + return; + } + } + else if (hostToDevFis->h.command == SAT_SMART ) + { + if ((hostToDevFis->h.features == SAT_SMART_ENABLE_OPERATIONS) || (hostToDevFis->h.features == SAT_SMART_DISABLE_OPERATIONS)) + { + SM_DBG5(("smsatModeSelect6n10CB: SAT_SMART_ENABLE/DISABLE_OPERATIONS success, feature 0x%x\n", hostToDevFis->h.features)); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + /* return stat_good */ + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + return; + } + else + { + SM_DBG1(("smsatModeSelect6n10CB: error unknown command failed 0x%x feature 0x%x!!!\n", hostToDevFis->h.command, hostToDevFis->h.features)); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + return; + } + } + + else + { + SM_DBG1(("smsatModeSelect6n10CB: error default case command success 0x%x!!!\n", hostToDevFis->h.command)); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + return; + } + + return; + +} + +osGLOBAL void +smsatSynchronizeCache10n16CB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ) +{ + /* + In the process of SynchronizeCache10 and SynchronizeCache16 + Process SAT_FLUSH_CACHE_EXT + Process SAT_FLUSH_CACHE + */ + + + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smIORequestBody_t *smOrgIORequestBody; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatInternalIo_t *satIntIo; + smDeviceData_t *oneDeviceData; + + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + smIORequest_t *smOrgIORequest; + + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + + SM_DBG2(("smsatSynchronizeCache10n16CB: start\n")); + SM_DBG5(("smsatSynchronizeCache10n16CB:agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate smIOContext */ + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + + /* SPC: Self-Test Result Log page */ + if (satIntIo == agNULL) + { + SM_DBG4(("smsatSynchronizeCache10n16CB: External smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + smOrgIORequest = smIORequestBody->smIORequest; + pSense = satIOContext->pSense; + scsiCmnd = satIOContext->pScsiCmnd; + } + else + { + SM_DBG4(("smsatSynchronizeCache10n16CB: Internal smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + SM_DBG4(("smsatSynchronizeCache10n16CB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + SM_DBG4(("smsatSynchronizeCache10n16CB: satOrgIOContext is NOT NULL\n")); + } + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + smOrgIORequest = (smIORequest_t *)smOrgIORequestBody->smIORequest; + + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatSynchronizeCache10n16CB: wrong. agFirstDword is NULL when error, status %d!!!\n", agIOStatus)); + + tdsmIOCompletedCB( + smRoot, + smOrgIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + if( agIOStatus != OSSA_IO_SUCCESS) + { + /* only agsaFisRegDeviceToHost_t is expected */ + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + } + + if( agIOStatus != OSSA_IO_SUCCESS) + { + if ( (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) || + ((ataStatus & ERR_ATA_STATUS_MASK) || (ataStatus & DF_ATA_STATUS_MASK)) + ) + { + /* for debugging */ + if( agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatSynchronizeCache10n16CB: FAILED, NOT IO_SUCCESS!!!\n")); + } + else if (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) + { + SM_DBG1(("smsatSynchronizeCache10n16CB: FAILED, Wrong FIS type 0x%x!!!\n",statDevToHostFisHeader->fisType)); + } + else if ( (ataStatus & ERR_ATA_STATUS_MASK) || + (ataStatus & DF_ATA_STATUS_MASK) + ) + { + SM_DBG1(("smsatSynchronizeCache10n16CB: FAILED, FAILED, error status!!!\n")); + } + + + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + smsatProcessAbort(smRoot, + smOrgIORequest, + satOrgIOContext + ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + switch (hostToDevFis->h.command) + { + case SAT_FLUSH_CACHE: + SM_DBG1(("smsatSynchronizeCache10n16CB: SAT_FLUSH_CACHE failed!!!\n")); + /* checking IMMED bit */ + if (scsiCmnd->cdb[1] & SCSI_FLUSH_CACHE_IMMED_MASK) + { + smsatSetDeferredSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + } + else + { + smsatSetDeferredSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + } + + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + break; + case SAT_FLUSH_CACHE_EXT: + SM_DBG1(("smsatSynchronizeCache10n16CB: SAT_FLUSH_CACHE_EXT failed!!!\n")); + /* checking IMMED bit */ + if (scsiCmnd->cdb[1] & SCSI_FLUSH_CACHE_IMMED_MASK) + { + smsatSetDeferredSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + } + else + { + smsatSetDeferredSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + } + + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + break; + default: + SM_DBG1(("smsatSynchronizeCache10n16CB: error unknown command 0x%x!!!\n", hostToDevFis->h.command)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + break; + } + + return; + } /* end of error checking */ + } + + /* prcessing the success case */ + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + + switch (hostToDevFis->h.command) + { + case SAT_FLUSH_CACHE: + SM_DBG5(("smsatSynchronizeCache10n16CB: SAT_FLUSH_CACHE success\n")); + + /* checking IMMED bit */ + if ( !(scsiCmnd->cdb[1] & SCSI_FLUSH_CACHE_IMMED_MASK)) + { + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + return; + } + + + break; + case SAT_FLUSH_CACHE_EXT: + SM_DBG5(("smsatSynchronizeCache10n16CB: SAT_FLUSH_CACHE_EXT success\n")); + + /* checking IMMED bit */ + if ( !(scsiCmnd->cdb[1] & SCSI_FLUSH_CACHE_IMMED_MASK)) + { + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + return; + } + + break; + default: + SM_DBG5(("smsatSynchronizeCache10n16CB: error unknown command 0x%x\n", hostToDevFis->h.command)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + return; + break; + } + + return; +} + +//qqqqqqqq +osGLOBAL void +smsatNonChainedWriteNVerifyCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + /* + In the process of WriteAndVerify10 + Process SAT_WRITE_DMA_FUA_EXT + Process SAT_WRITE_DMA_EXT + Process SAT_WRITE_SECTORS_EXT + Process SAT_WRITE_FPDMA_QUEUED + Process SAT_READ_VERIFY_SECTORS + Process SAT_READ_VERIFY_SECTORS_EXT + chained command + */ + + + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smIORequestBody_t *smOrgIORequestBody; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatIOContext_t *satNewIOContext; + smSatInternalIo_t *satIntIo; + smSatInternalIo_t *satNewIntIo = agNULL; +// satDeviceData_t *satDevData; + smDeviceData_t *oneDeviceData; + + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + smIORequest_t *smOrgIORequest; + + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + bit32 status; + smScsiInitiatorRequest_t *smScsiRequest; /* smScsiXchg */ + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + agsaFisSetDevBitsHeader_t *statSetDevBitFisHeader = agNULL; + + /* internally generate smIOContext */ + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + + /* SPC: Self-Test Result Log page */ + smScsiRequest = satIOContext->smScsiXchg; + + SM_DBG2(("smsatNonChainedWriteNVerifyCB: start\n")); + SM_DBG5(("smsatNonChainedWriteNVerifyCB: start agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + + if (satIntIo == agNULL) + { + SM_DBG4(("smsatNonChainedWriteNVerifyCB: External smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + smOrgIORequest = smIORequestBody->smIORequest; + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + else + { + SM_DBG4(("smsatNonChainedWriteNVerifyCB: Internal smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + SM_DBG4(("smsatNonChainedWriteNVerifyCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + SM_DBG4(("smsatNonChainedWriteNVerifyCB: satOrgIOContext is NOT NULL\n")); + } + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + smOrgIORequest = (smIORequest_t *)smOrgIORequestBody->smIORequest; + + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatNonChainedWriteNVerifyCB: wrong. agFirstDword is NULL when error, status %d!!!\n", agIOStatus)); + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* + FIS type should be either REG_DEV_TO_HOST_FIS or SET_DEV_BITS_FIS + */ + /* First, assumed to be Reg Device to Host FIS */ + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + } + + if (agIOStatus != OSSA_IO_SUCCESS) + { + if (statDevToHostFisHeader->fisType == SET_DEV_BITS_FIS) + { + statSetDevBitFisHeader = (agsaFisSetDevBitsHeader_t *)&(agFirstDword->D2H); + + /* Get ATA Status register */ + ataStatus = (statSetDevBitFisHeader->statusHi_Lo & 0x70); /* bits 4,5,6 */ + ataStatus = ataStatus | (statSetDevBitFisHeader->statusHi_Lo & 0x07); /* bits 0,1,2 */ + } + } + + + if( agIOStatus != OSSA_IO_SUCCESS) + { + /* + checking IO status, FIS type and error status + FIS type should be either REG_DEV_TO_HOST_FIS or SET_DEV_BITS_FIS + Both have fisType in the same location + */ + if ( ((statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) && + (statDevToHostFisHeader->fisType != SET_DEV_BITS_FIS)) || + ((ataStatus & ERR_ATA_STATUS_MASK) || (ataStatus & DF_ATA_STATUS_MASK)) + ) + { + /* for debugging */ + if( agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatNonChainedWriteNVerifyCB: FAILED, NOT IO_SUCCESS!!!\n")); + } + else if (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) + { + SM_DBG1(("smsatNonChainedWriteNVerifyCB: FAILED, Wrong FIS type 0x%x!!!\n",statDevToHostFisHeader->fisType)); + } + else if (statDevToHostFisHeader->fisType != SET_DEV_BITS_FIS) + { + SM_DBG1(("smsatNonChainedWriteNVerifyCB: FAILED, Wrong FIS type 0x%x!!!\n",statDevToHostFisHeader->fisType)); + } + else if ( (ataStatus & ERR_ATA_STATUS_MASK) || + (ataStatus & DF_ATA_STATUS_MASK) + ) + { + SM_DBG1(("smsatNonChainedWriteNVerifyCB: FAILED, FAILED, error status!!!\n")); + } + + + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + smsatProcessAbort(smRoot, + smOrgIORequest, + satOrgIOContext + ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + /* for debugging */ + switch (hostToDevFis->h.command) + { + case SAT_WRITE_DMA_FUA_EXT: + SM_DBG1(("smsatNonChainedWriteNVerifyCB: SAT_WRITE_DMA_FUA_EXT!!!\n")); + break; + case SAT_WRITE_DMA_EXT: + SM_DBG1(("smsatNonChainedWriteNVerifyCB: SAT_WRITE_DMA_EXT!!!\n")); + break; + case SAT_WRITE_SECTORS_EXT: + SM_DBG1(("smsatNonChainedWriteNVerifyCB: SAT_WRITE_SECTORS_EXT!!!\n")); + break; + case SAT_WRITE_FPDMA_QUEUED: + SM_DBG1(("smsatNonChainedWriteNVerifyCB: SAT_WRITE_FPDMA_QUEUED!!!\n")); + break; + case SAT_READ_VERIFY_SECTORS: + SM_DBG1(("smsatNonChainedWriteNVerifyCB: SAT_READ_VERIFY_SECTORS!!!\n")); + break; + case SAT_READ_VERIFY_SECTORS_EXT: + SM_DBG1(("smsatNonChainedWriteNVerifyCB: SAT_READ_VERIFY_SECTORS_EXT!!!\n")); + break; + default: + SM_DBG1(("smsatNonChainedWriteNVerifyCB: error default case command 0x%x!!!\n", hostToDevFis->h.command)); + break; + } + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } /* end error checking */ + } + + /* process success from this point on */ + + switch (hostToDevFis->h.command) + { + case SAT_WRITE_DMA_FUA_EXT: + SM_DBG5(("smsatNonChainedWriteNVerifyCB: SAT_WRITE_DMA_FUA_EXT success\n")); + break; + case SAT_WRITE_DMA_EXT: + SM_DBG5(("smsatNonChainedWriteNVerifyCB: SAT_WRITE_DMA_EXT success\n")); + break; + case SAT_WRITE_SECTORS_EXT: + SM_DBG5(("smsatNonChainedWriteNVerifyCB: SAT_WRITE_SECTORS_EXT succes\n")); + + break; + case SAT_WRITE_FPDMA_QUEUED: + SM_DBG5(("smsatNonChainedWriteNVerifyCB: SAT_WRITE_FPDMA_QUEUED succes\n")); + break; + case SAT_READ_VERIFY_SECTORS: + SM_DBG5(("smsatNonChainedWriteNVerifyCB: SAT_READ_VERIFY_SECTORS succes\n")); + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + /* free */ + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + /* return stat_good */ + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + return; + break; + case SAT_READ_VERIFY_SECTORS_EXT: + SM_DBG5(("smsatNonChainedWriteNVerifyCB: SAT_READ_VERIFY_SECTORS_EXT succes\n")); + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + /* free */ + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + /* return stat_good */ + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + return; + break; + default: + SM_DBG1(("smsatNonChainedWriteNVerifyCB: error default case command 0x%x success!!!\n", hostToDevFis->h.command)); + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + break; + } + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + /* free */ + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + satNewIntIo = smsatAllocIntIoResource( smRoot, + smOrgIORequest, + oneDeviceData, + 0, + satNewIntIo); + if (satNewIntIo == agNULL) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + SM_DBG1(("smsatNonChainedWriteNVerifyCB: momory allocation fails!!!\n")); + return; + } /* end memory allocation */ + + satNewIOContext = smsatPrepareNewIO(satNewIntIo, + smOrgIORequest, + oneDeviceData, + scsiCmnd, + satOrgIOContext + ); + + /* sends ATA verify command(READ_VERIFY_SECTORS or READ_VERIFY_SECTORS_EXT) */ + status = smsatNonChainedWriteNVerify_Verify(smRoot, + &satNewIntIo->satIntSmIORequest, + satNewIOContext->psmDeviceHandle, + smScsiRequest, /* orginal from OS layer */ + satNewIOContext + ); + + + if (status != SM_RC_SUCCESS) + { + /* sending ATA command fails */ + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satNewIntIo); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + SM_DBG1(("smsatNonChainedWriteNVerifyCB: calling satWriteAndVerify10_1 fails!!!\n")); + return; + } /* end send fails */ + + return; + +} + +osGLOBAL void +smsatChainedWriteNVerifyCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + /* + send write in loop + then, send verify in loop + */ + + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; +// tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; +// tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; +// tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; +// tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + smIORequestBody_t *smIORequestBody; + smIORequestBody_t *smOrgIORequestBody; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatIOContext_t *satNewIOContext; + smSatInternalIo_t *satIntIo; + smSatInternalIo_t *satNewIntIo = agNULL; +// satDeviceData_t *satDevData; + smDeviceData_t *oneDeviceData; + + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + smIORequest_t *smOrgIORequest; + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + bit32 dataLength; + bit32 status = tiError; + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + SM_DBG2(("smsatChainedWriteNVerifyCB: start\n")); + SM_DBG6(("smsatChainedWriteNVerifyCB: agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", + agIORequest, agIOStatus, agIOInfoLen)); + + if (satIntIo == agNULL) + { + SM_DBG5(("smsatChainedWriteNVerifyCB: External smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + smOrgIORequest = smIORequestBody->smIORequest; + pSense = satIOContext->pSense; + scsiCmnd = satIOContext->pScsiCmnd; + } + else + { + SM_DBG5(("smsatChainedWriteNVerifyCB: Internal smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + SM_DBG5(("smsatChainedWriteNVerifyCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + SM_DBG5(("smsatChainedWriteNVerifyCB: satOrgIOContext is NOT NULL\n")); + } + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + smOrgIORequest = (smIORequest_t *)smOrgIORequestBody->smIORequest; + + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatChainedWriteNVerifyCB: wrong. agFirstDword is NULL when error, status %d!!!\n", agIOStatus)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + /* + checking IO status, FIS type and error status + */ + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* agsaFisPioSetup_t or agsaFisRegDeviceToHost_t or agsaFisSetDevBits_t for read + agsaFisRegDeviceToHost_t or agsaFisSetDevBits_t for write + first, assumed to be Reg Device to Host FIS + This is OK to just find fis type + */ + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + /* for debugging */ + if( (statDevToHostFisHeader->fisType != PIO_SETUP_DEV_TO_HOST_FIS) && + (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) && + (statDevToHostFisHeader->fisType != SET_DEV_BITS_FIS) + ) + { + SM_DBG1(("smsatChainedWriteNVerifyCB: FAILED, Wrong FIS type 0x%x!!!\n", statDevToHostFisHeader->fisType)); + } + + /* for debugging */ + if ( (ataStatus & ERR_ATA_STATUS_MASK) || + (ataStatus & DF_ATA_STATUS_MASK) + ) + { + SM_DBG1(("smsatChainedWriteNVerifyCB: FAILED, error status and command 0x%x!!!\n", hostToDevFis->h.command)); + } + + /* the function below handles abort case */ + smsatDelayedProcessAbnormalCompletion(agRoot, + agIORequest, + agIOStatus, + agFirstDword, + agIOInfoLen, + agParam, + satIOContext); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } /* end of error */ + + /* process the success case */ + switch (hostToDevFis->h.command) + { + case SAT_WRITE_DMA: /* fall through */ + case SAT_WRITE_SECTORS:/* fall through */ +// case SAT_WRITE_DMA_FUA_EXT: /* fall through */ + case SAT_WRITE_DMA_EXT: /* fall through */ + case SAT_WRITE_SECTORS_EXT: /* fall through */ + case SAT_WRITE_FPDMA_QUEUED: + + SM_DBG5(("smsatChainedWriteNVerifyCB: WRITE success case\n")); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + /* done with internally genereated SAT_SMART_RETURN_STATUS */ + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + /* let's loop till TL */ + + /* lba = lba + tl + loopnum--; + if (loopnum == 0) done + */ + (satOrgIOContext->LoopNum)--; + + if (satOrgIOContext->superIOFlag) + { + dataLength = ((tiSuperScsiInitiatorRequest_t *) satOrgIOContext->smScsiXchg)->scsiCmnd.expDataLength; + } + else + { + dataLength = ((tiScsiInitiatorRequest_t *) satOrgIOContext->smScsiXchg)->scsiCmnd.expDataLength; + } + + satNewIntIo = smsatAllocIntIoResource( smRoot, + smOrgIORequest, + oneDeviceData, + dataLength, + satNewIntIo); + if (satNewIntIo == agNULL) + { + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOFailed, + smDetailOtherError, + agNULL, + satOrgIOContext->interruptContext ); + + SM_DBG1(("smsatChainedWriteNVerifyCB: momory allocation fails!!!\n")); + return; + } /* end of memory allocation failure */ + + /* + * Need to initialize all the fields within satIOContext + */ + + satNewIOContext = smsatPrepareNewIO( + satNewIntIo, + smOrgIORequest, + oneDeviceData, + scsiCmnd, + satOrgIOContext + ); + + if (satOrgIOContext->LoopNum == 0) + { + /* + done with write + start with verify + */ + satOrgIOContext->LoopNum = satOrgIOContext->LoopNum2; + status = smsatChainedWriteNVerify_Start_Verify(smRoot, + &satNewIntIo->satIntSmIORequest, + satNewIOContext->psmDeviceHandle, + &satNewIntIo->satIntSmScsiXchg, + satNewIOContext); + } + else + { + status = smsatChainedWriteNVerify_Write(smRoot, + &satNewIntIo->satIntSmIORequest, + satNewIOContext->psmDeviceHandle, + &satNewIntIo->satIntSmScsiXchg, + satNewIOContext); + } + + if (status != SM_RC_SUCCESS) + { + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satNewIntIo); + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOFailed, + smDetailOtherError, + agNULL, + satOrgIOContext->interruptContext ); + SM_DBG1(("smsatChainedWriteNVerifyCB: calling satChainedWriteNVerify_Write fails!!!\n")); + return; + } + + break; + + case SAT_READ_VERIFY_SECTORS: /* fall through */ + case SAT_READ_VERIFY_SECTORS_EXT: + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + /* done with internally genereated SAT_SMART_RETURN_STATUS */ + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + /* let's loop till TL */ + + /* lba = lba + tl + loopnum--; + if (loopnum == 0) done + */ + (satOrgIOContext->LoopNum)--; + if (satOrgIOContext->LoopNum == 0) + { + /* + done with write and verify + */ + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + return; + } + + if (satOrgIOContext->superIOFlag) + { + dataLength = ((tiSuperScsiInitiatorRequest_t *) satOrgIOContext->smScsiXchg)->scsiCmnd.expDataLength; + } + else + { + dataLength = ((tiScsiInitiatorRequest_t *) satOrgIOContext->smScsiXchg)->scsiCmnd.expDataLength; + } + + satNewIntIo = smsatAllocIntIoResource( smRoot, + smOrgIORequest, + oneDeviceData, + dataLength, + satNewIntIo); + if (satNewIntIo == agNULL) + { + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOFailed, + smDetailOtherError, + agNULL, + satOrgIOContext->interruptContext ); + + SM_DBG1(("smsatChainedWriteNVerifyCB: momory allocation fails!!!\n")); + return; + } /* end of memory allocation failure */ + + /* + * Need to initialize all the fields within satIOContext + */ + + satNewIOContext = smsatPrepareNewIO( + satNewIntIo, + smOrgIORequest, + oneDeviceData, + scsiCmnd, + satOrgIOContext + ); + status = smsatChainedWriteNVerify_Verify(smRoot, + &satNewIntIo->satIntSmIORequest, + satNewIOContext->psmDeviceHandle, + &satNewIntIo->satIntSmScsiXchg, + satNewIOContext); + + if (status != SM_RC_SUCCESS) + { + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satNewIntIo); + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOFailed, + smDetailOtherError, + agNULL, + satOrgIOContext->interruptContext ); + SM_DBG1(("smsatChainedWriteNVerifyCB: calling satChainedWriteNVerify_Verify fails!!!\n")); + return; + } + + break; + + default: + SM_DBG1(("smsatChainedWriteNVerifyCB: success but default case command 0x%x!!!\n",hostToDevFis->h.command)); + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOFailed, + smDetailOtherError, + agNULL, + satOrgIOContext->interruptContext ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + break; + } + + + return; +} + +osGLOBAL void +smsatReadMediaSerialNumberCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ) +{ +// tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; +// tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; +// tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; +// tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smIORequestBody_t *smOrgIORequestBody; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatInternalIo_t *satIntIo; +// satDeviceData_t *satDevData; + smDeviceData_t *oneDeviceData; + + smScsiRspSense_t *pSense; + smIORequest_t *smOrgIORequest; + + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + smScsiInitiatorRequest_t *smOrgScsiRequest; /* tiScsiXchg */ + bit8 *pMediaSerialNumber; + bit8 MediaSerialNumber[ZERO_MEDIA_SERIAL_NUMBER_LENGTH] = {0}; + smIniScsiCmnd_t *scsiCmnd; + bit32 allocationLen = 0; + + SM_DBG2(("smsatReadMediaSerialNumberCB: start\n")); + SM_DBG4(("smsatReadMediaSerialNumberCB:agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate tiIOContext */ + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + + if (satIntIo == agNULL) + { + SM_DBG4(("smsatReadMediaSerialNumberCB: External smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + smOrgIORequest = smIORequestBody->smIORequest; + pSense = satOrgIOContext->pSense; + smOrgScsiRequest = satOrgIOContext->smScsiXchg; + /* SCSI command response payload to OS layer */ + pMediaSerialNumber = (bit8 *) smOrgScsiRequest->sglVirtualAddr; + /* ATA command response payload */ + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + else + { + SM_DBG4(("smsatReadMediaSerialNumberCB: Internal smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + SM_DBG4(("smsatReadMediaSerialNumberCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + SM_DBG4(("smsatReadMediaSerialNumberCB: satOrgIOContext is NOT NULL\n")); + } + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + smOrgIORequest = (smIORequest_t *)smOrgIORequestBody->smIORequest; + + pSense = satOrgIOContext->pSense; + smOrgScsiRequest = satOrgIOContext->smScsiXchg; + /* SCSI command response payload to OS layer */ + pMediaSerialNumber = (bit8 *) smOrgScsiRequest->sglVirtualAddr; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatReadMediaSerialNumberCB: wrong. agFirstDword is NULL when error, status %d!!!\n", agIOStatus)); + tdsmIOCompletedCB( + smRoot, + smOrgIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + if( agIOStatus != OSSA_IO_SUCCESS) + { + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + smsatProcessAbort(smRoot, + smOrgIORequest, + satOrgIOContext + ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NOT_READY, + 0, + SCSI_SNSCODE_MEDIUM_NOT_PRESENT, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + /* process success case */ + allocationLen = (scsiCmnd->cdb[6] << (8*3)) + (scsiCmnd->cdb[7] << (8*2)) + + (scsiCmnd->cdb[8] << 8) + scsiCmnd->cdb[9]; + allocationLen = MIN(allocationLen, scsiCmnd->expDataLength); + SM_DBG5(("smsatReadMediaSerialNumberCB: allocationLen in CDB %d 0x%x\n", allocationLen,allocationLen)); + + if (hostToDevFis->h.command == SAT_READ_SECTORS || + hostToDevFis->h.command == SAT_READ_SECTORS_EXT + ) + { + MediaSerialNumber[0] = 0; + MediaSerialNumber[1] = 0; + MediaSerialNumber[2] = 0; + MediaSerialNumber[3] = 4; + MediaSerialNumber[4] = 0; + MediaSerialNumber[5] = 0; + MediaSerialNumber[6] = 0; + MediaSerialNumber[7] = 0; + + sm_memcpy(pMediaSerialNumber, MediaSerialNumber, MIN(allocationLen, ZERO_MEDIA_SERIAL_NUMBER_LENGTH)); + if (ZERO_MEDIA_SERIAL_NUMBER_LENGTH < allocationLen) + { + SM_DBG1(("smsatReadMediaSerialNumberCB: 1st underrun allocationLen %d len %d !!!\n", allocationLen, ZERO_MEDIA_SERIAL_NUMBER_LENGTH)); + + /* underrun */ + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == satIntIo->satOrgSmIORequest */ + smIOUnderRun, + allocationLen - ZERO_MEDIA_SERIAL_NUMBER_LENGTH, + agNULL, + satOrgIOContext->interruptContext ); + + } + else + { + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext); + } + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + else + { + SM_DBG1(("smsatReadMediaSerialNumberCB: error unknown command success 0x%x!!!\n", hostToDevFis->h.command)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + return; + } + return; +} + +osGLOBAL void +smsatReadBufferCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ) +{ + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smIORequestBody_t *smOrgIORequestBody; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatInternalIo_t *satIntIo; + smDeviceData_t *oneDeviceData; + smScsiRspSense_t *pSense; + smIORequest_t *smOrgIORequest; + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + + + SM_DBG2(("smsatReadBufferCB: start\n")); + SM_DBG4(("smsatReadBufferCB:agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + /* internally generate tiIOContext */ + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + if (satIntIo == agNULL) + { + SM_DBG4(("smsatReadBufferCB: External smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + smOrgIORequest = smIORequestBody->smIORequest; + pSense = satOrgIOContext->pSense; + } + else + { + SM_DBG4(("smsatReadBufferCB: Internal smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + SM_DBG4(("smsatReadBufferCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + SM_DBG4(("smsatReadBufferCB: satOrgIOContext is NOT NULL\n")); + } + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + smOrgIORequest = (smIORequest_t *)smOrgIORequestBody->smIORequest; + pSense = satOrgIOContext->pSense; + } + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatReadBufferCB: wrong. agFirstDword is NULL when error, status %d!!!\n", agIOStatus)); + tdsmIOCompletedCB( + smRoot, + smOrgIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + if( agIOStatus != OSSA_IO_SUCCESS) + { + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + smsatProcessAbort(smRoot, + smOrgIORequest, + satOrgIOContext + ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NOT_READY, + 0, + SCSI_SNSCODE_MEDIUM_NOT_PRESENT, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + /* process success case */ + if (hostToDevFis->h.command == SAT_READ_BUFFER ) + { + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext); + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + else + { + SM_DBG1(("smsatReadBufferCB: error unknown command success 0x%x!!!\n", hostToDevFis->h.command)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + return; + } + + return; +} + +osGLOBAL void +smsatWriteBufferCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ) +{ + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smIORequestBody_t *smOrgIORequestBody; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatInternalIo_t *satIntIo; + smDeviceData_t *oneDeviceData; + smScsiRspSense_t *pSense; + smIORequest_t *smOrgIORequest; + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + + + SM_DBG2(("smsatWriteBufferCB: start\n")); + SM_DBG4(("smsatWriteBufferCB:agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + /* internally generate tiIOContext */ + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + if (satIntIo == agNULL) + { + SM_DBG4(("smsatWriteBufferCB: External smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + smOrgIORequest = smIORequestBody->smIORequest; + pSense = satOrgIOContext->pSense; + /* SCSI command response payload to OS layer */ +// pMediaSerialNumber = (bit8 *) s,OrgScsiRequest->sglVirtualAddr; + } + else + { + SM_DBG4(("smsatWriteBufferCB: Internal smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + SM_DBG4(("smsatWriteBufferCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + SM_DBG4(("smsatWriteBufferCB: satOrgIOContext is NOT NULL\n")); + } + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + smOrgIORequest = (smIORequest_t *)smOrgIORequestBody->smIORequest; + pSense = satOrgIOContext->pSense; + } + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatWriteBufferCB: wrong. agFirstDword is NULL when error, status %d!!!\n", agIOStatus)); + tdsmIOCompletedCB( + smRoot, + smOrgIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + if( agIOStatus != OSSA_IO_SUCCESS) + { + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + smsatProcessAbort(smRoot, + smOrgIORequest, + satOrgIOContext + ); + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NOT_READY, + 0, + SCSI_SNSCODE_MEDIUM_NOT_PRESENT, + satOrgIOContext); + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + /* process success case */ + if (hostToDevFis->h.command == SAT_WRITE_BUFFER ) + { + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext); + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + else + { + SM_DBG1(("smsatWriteBufferCB: error unknown command success 0x%x!!!\n", hostToDevFis->h.command)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + return; +} + +osGLOBAL void +smsatReassignBlocksCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ) +{ + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smIORequestBody_t *smOrgIORequestBody; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatIOContext_t *satNewIOContext; + smSatInternalIo_t *satIntIo; + smSatInternalIo_t *satNewIntIo = agNULL; + smDeviceData_t *oneDeviceData; + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + smIORequest_t *smOrgIORequest; + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + bit32 status; + smScsiInitiatorRequest_t *smScsiRequest; /* smScsiXchg */ + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + + SM_DBG2(("smsatReassignBlocksCB: start\n")); + SM_DBG5(("smsatReassignBlocksCB: agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate tiIOContext */ + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + if (satIntIo == agNULL) + { + SM_DBG4(("smsatReassignBlocksCB: External smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + smOrgIORequest = smIORequestBody->smIORequest; + smScsiRequest = satOrgIOContext->smScsiXchg; + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + else + { + SM_DBG4(("smsatReassignBlocksCB: Internal smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + SM_DBG4(("smsatReassignBlocksCB: satOrgIOContext is NULL, Wrong\n")); + return; + } + else + { + SM_DBG4(("smsatReassignBlocksCB: satOrgIOContext is NOT NULL, Wrong\n")); + } + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + smOrgIORequest = (smIORequest_t *)smOrgIORequestBody->smIORequest; + smScsiRequest = satOrgIOContext->smScsiXchg; + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatReassignBlocksCB: wrong. agFirstDword is NULL when error, status %d!!!\n", agIOStatus)); + tdsmIOCompletedCB( + smRoot, + smOrgIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* only agsaFisRegDeviceToHost_t is expected */ + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + } + if (agIOStatus != OSSA_IO_SUCCESS) + { + if ( (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) || + ((ataStatus & ERR_ATA_STATUS_MASK) || (ataStatus & DF_ATA_STATUS_MASK)) + ) + { + /* for debugging */ + if( agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatReassignBlocksCB FAILED, NOT IO_SUCCESS!!!\n")); + } + else if (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) + { + SM_DBG1(("smsatReassignBlocksCB FAILED, Wrong FIS type 0x%x!!!\n",statDevToHostFisHeader->fisType)); + } + else if ( (ataStatus & ERR_ATA_STATUS_MASK) || + (ataStatus & DF_ATA_STATUS_MASK) + ) + { + SM_DBG1(("smsatReassignBlocksCB FAILED, FAILED, error status!!!\n")); + } + + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + smsatProcessAbort(smRoot, + smOrgIORequest, + satOrgIOContext + ); + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + /* for debugging */ + if (hostToDevFis->h.command == SAT_READ_VERIFY_SECTORS || + hostToDevFis->h.command == SAT_READ_VERIFY_SECTORS_EXT + ) + { + SM_DBG1(("smsatReassignBlocksCB SAT_READ_VERIFY_SECTORS(_EXT) failed!!!\n")); + /* Verify failed; send Write with same LBA */ + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + satNewIntIo = smsatAllocIntIoResource( smRoot, + smOrgIORequest, + oneDeviceData, + 512, /* writing 1 sector */ + satNewIntIo); + if (satNewIntIo == agNULL) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_HARDWARE_ERROR, + 0, + SCSI_SNSCODE_WRITE_ERROR_AUTO_REALLOCATION_FAILED, + satOrgIOContext); + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + SM_DBG1(("smsatReassignBlocksCB: momory allocation fails!!!\n")); + return; + } /* end memory allocation */ + satNewIOContext = smsatPrepareNewIO( + satNewIntIo, + smOrgIORequest, + oneDeviceData, + scsiCmnd, + satOrgIOContext + ); + /* send Write with same LBA */ + status = smsatReassignBlocks_2( + smRoot, + &satNewIntIo->satIntSmIORequest, + satNewIOContext->psmDeviceHandle, + &satNewIntIo->satIntSmScsiXchg, + satNewIOContext, + satOrgIOContext->LBA + ); + + if (status != SM_RC_SUCCESS) + { + /* sending ATA command fails */ + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satNewIntIo); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_HARDWARE_ERROR, + 0, + SCSI_SNSCODE_WRITE_ERROR_AUTO_REALLOCATION_FAILED, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + SM_DBG1(("smsatReassignBlocksCB calling fail 1!!!\n")); + return; + } /* end send fails */ + + return; + } + else if (hostToDevFis->h.command == SAT_WRITE_DMA || + hostToDevFis->h.command == SAT_WRITE_SECTORS || + hostToDevFis->h.command == SAT_WRITE_DMA_EXT || + hostToDevFis->h.command == SAT_WRITE_SECTORS_EXT || + hostToDevFis->h.command == SAT_WRITE_FPDMA_QUEUED + ) + { + SM_DBG1(("smsatReassignBlocksCB SAT_WRITE failed!!!\n")); + /* fall through */ + } + else + { + SM_DBG1(("smsatReassignBlocksCB error default case unexpected command 0x%x!!!\n", hostToDevFis->h.command)); + } + + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_HARDWARE_ERROR, + 0, + SCSI_SNSCODE_WRITE_ERROR_AUTO_REALLOCATION_FAILED, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } /* error checking */ + } + + + /* prcessing the success case */ + if (hostToDevFis->h.command == SAT_READ_VERIFY_SECTORS || + hostToDevFis->h.command == SAT_READ_VERIFY_SECTORS_EXT || + hostToDevFis->h.command == SAT_WRITE_DMA || + hostToDevFis->h.command == SAT_WRITE_SECTORS || + hostToDevFis->h.command == SAT_WRITE_DMA_EXT || + hostToDevFis->h.command == SAT_WRITE_SECTORS_EXT || + hostToDevFis->h.command == SAT_WRITE_FPDMA_QUEUED + ) + { + /* next LBA; verify */ + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + if (satOrgIOContext->ParmIndex >= satOrgIOContext->ParmLen) + { + SM_DBG5(("smsatReassignBlocksCB: GOOD status\n")); + /* return stat_good */ + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + return; + } + else + { + SM_DBG5(("smsatReassignBlocksCB: processing next LBA\n")); + satNewIntIo = smsatAllocIntIoResource( smRoot, + smOrgIORequest, + oneDeviceData, + 0, + satNewIntIo); + if (satNewIntIo == agNULL) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_HARDWARE_ERROR, + 0, + SCSI_SNSCODE_WRITE_ERROR_AUTO_REALLOCATION_FAILED, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + SM_DBG1(("smsatReassignBlocksCB: momory allocation fails!!!\n")); + return; + } /* end memory allocation */ + + satNewIOContext = smsatPrepareNewIO( + satNewIntIo, + smOrgIORequest, + oneDeviceData, + scsiCmnd, + satOrgIOContext + ); + + /* send Verify with the next LBA */ + status = smsatReassignBlocks_1( + smRoot, + &satNewIntIo->satIntSmIORequest, + satNewIOContext->psmDeviceHandle, + smScsiRequest, /* orginal from OS layer */ + satNewIOContext, + satOrgIOContext + ); + + if (status != SM_RC_SUCCESS) + { + /* sending ATA command fails */ + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satNewIntIo); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_HARDWARE_ERROR, + 0, + SCSI_SNSCODE_WRITE_ERROR_AUTO_REALLOCATION_FAILED, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + SM_DBG1(("smsatReassignBlocksCB calling satModeSelect6_1 fails!!!\n")); + return; + } /* end send fails */ + } /* else */ + return; + + } + else if (hostToDevFis->h.command == SAT_WRITE_DMA || + hostToDevFis->h.command == SAT_WRITE_SECTORS || + hostToDevFis->h.command == SAT_WRITE_DMA_EXT || + hostToDevFis->h.command == SAT_WRITE_SECTORS_EXT || + hostToDevFis->h.command == SAT_WRITE_FPDMA_QUEUED + ) + { + /* next LBA; verify */ + } + else + { + SM_DBG1(("smsatReassignBlocksCB error unknown command success 0x%x !!!\n", hostToDevFis->h.command)); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_HARDWARE_ERROR, + 0, + SCSI_SNSCODE_WRITE_ERROR_AUTO_REALLOCATION_FAILED, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + return; + } + return; +} + + +osGLOBAL FORCEINLINE void +smsatDecrementPendingIO( + smRoot_t *smRoot, + smIntContext_t *smAllShared, + smSatIOContext_t *satIOContext + ) +{ +#ifdef CCFLAG_OPTIMIZE_SAT_LOCK + bit32 volatile satPendingNCQIO = 0; + bit32 volatile satPendingNONNCQIO = 0; + bit32 volatile satPendingIO = 0; +#endif /* CCFLAG_OPTIMIZE_SAT_LOCK */ + smDeviceData_t *oneDeviceData = satIOContext->pSatDevData; + smSatInternalIo_t *satIntIo = satIOContext->satIntIoContext; + smSatIOContext_t *satOrgIOContext = satIOContext->satOrgIOContext; +#ifdef TD_DEBUG_ENABLE + smIORequestBody_t *smIORequestBody = agNULL; + smIORequestBody = (smIORequestBody_t *)satIOContext->smRequestBody; +#endif + + SM_DBG3(("smsatDecrementPendingIO: start\n")); + +#ifdef CCFLAG_OPTIMIZE_SAT_LOCK + if ( (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_WRITE) || + (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_READ) ) + { + tdsmInterlockedDecrement(smRoot,&oneDeviceData->satPendingNCQIO); + } + else + { + tdsmInterlockedDecrement(smRoot,&oneDeviceData->satPendingNONNCQIO); + } + tdsmInterlockedDecrement(smRoot,&oneDeviceData->satPendingIO); + /* temp */ + tdsmInterlockedExchange(smRoot, &satPendingNCQIO, oneDeviceData->satPendingNCQIO); + tdsmInterlockedExchange(smRoot, &satPendingNONNCQIO, oneDeviceData->satPendingNONNCQIO); + tdsmInterlockedExchange(smRoot, &satPendingIO, oneDeviceData->satPendingIO); + if (satPendingNCQIO == -1) + { + SM_DBG1(("smsatDecrementPendingIO: satPendingNCQIO adjustment!!!\n")); + oneDeviceData->satPendingNCQIO = 0; + } + if (satPendingNONNCQIO == -1) + { + SM_DBG1(("smsatDecrementPendingIO: satPendingNONNCQIO adjustment!!!\n")); + oneDeviceData->satPendingNONNCQIO = 0; + } + if (satPendingIO == -1) + { + SM_DBG1(("smsatDecrementPendingIO: satPendingIO adjustment!!!\n")); + oneDeviceData->satPendingIO = 0; + } + +#else + + if ( (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_WRITE) || + (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_READ) ) + { + tdsmSingleThreadedEnter(smRoot, SM_EXTERNAL_IO_LOCK); + oneDeviceData->satPendingNCQIO--; + oneDeviceData->satPendingIO--; + SMLIST_DEQUEUE_THIS (&satIOContext->satIoContextLink); + /* temp */ + if (oneDeviceData->satPendingNCQIO == -1) + { + SM_DBG1(("smsatDecrementPendingIO: satPendingNCQIO adjustment!!!\n")); + oneDeviceData->satPendingNCQIO = 0; + } + if (oneDeviceData->satPendingIO == -1) + { + SM_DBG1(("smsatDecrementPendingIO: satPendingIO adjustment!!!\n")); + oneDeviceData->satPendingIO = 0; + } + tdsmSingleThreadedLeave(smRoot, SM_EXTERNAL_IO_LOCK); + } + else + { + tdsmSingleThreadedEnter(smRoot, SM_EXTERNAL_IO_LOCK); + oneDeviceData->satPendingNONNCQIO--; + oneDeviceData->satPendingIO--; + SMLIST_DEQUEUE_THIS (&satIOContext->satIoContextLink); + /* temp */ + if (oneDeviceData->satPendingNONNCQIO == -1) + { + SM_DBG1(("smsatDecrementPendingIO: satPendingNONNCQIO adjustment!!!\n")); + oneDeviceData->satPendingNONNCQIO = 0; + } + if (oneDeviceData->satPendingIO == -1) + { + SM_DBG1(("smsatDecrementPendingIO: satPendingIO adjustment!!!\n")); + oneDeviceData->satPendingIO = 0; + } + tdsmSingleThreadedLeave(smRoot, SM_EXTERNAL_IO_LOCK); + } + +#endif /* CCFLAG_OPTIMIZE_SAT_LOCK */ + + if (satIntIo == agNULL) + { + SM_DBG3(("smsatDecrementPendingIO: external command!!!\n")); + /*smEnqueueIO(smRoot, satIOContext);*/ + } + else + { + SM_DBG3(("smsatDecrementPendingIO: internal command!!!\n")); + if (satOrgIOContext == agNULL) + { + /* No smEnqueueIO since only alloc used */ + SM_DBG3(("smsatDecrementPendingIO: internal only command!!!, ID %d!!!\n", smIORequestBody->id)); + return; + } + else + { + /* smDequeueIO used */ + /*smEnqueueIO(smRoot, satOrgIOContext);*/ + } + } + + return; +} + + +osGLOBAL void +smsatProcessAbnormalCompletion( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + smSatIOContext_t *satIOContext + ) +{ + + smRoot_t *smRoot = agNULL; +// tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; +// tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 interruptContext; + smIORequestBody_t *smIORequestBody; +// satDeviceData_t *pSatDevData; + smDeviceHandle_t *smDeviceHandle; + smDeviceData_t *oneDeviceData = agNULL; + agsaDevHandle_t *agDevHandle = agNULL; + + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + oneDeviceData = satIOContext->pSatDevData; + if (oneDeviceData == agNULL) + { + SM_DBG1(("smsatProcessAbnormalCompletion: oneDeviceData is NULL\n")); + return; + } + smDeviceHandle = satIOContext->psmDeviceHandle; + smRoot = oneDeviceData->smRoot; + interruptContext = satIOContext->interruptContext; + + SM_DBG5(("smsatProcessAbnormalCompletion: start\n")); + + /* Get into the detail */ + switch(agIOStatus) + { + case OSSA_IO_SUCCESS: + SM_DBG1(("smsatProcessAbnormalCompletion: agIOStatus = OSSA_IO_SUCCESS agIOInfoLen 0x%x calling smsatIOCompleted!!!\n", agIOInfoLen)); + /* + * At this point agIOInfoLen should be non-zero and there is valid FIS + * to read. Pass this info to the SAT layer in order to do the ATA status + * to SCSI status translation. + */ + smsatIOCompleted( smRoot, + smIORequestBody->smIORequest, + agFirstDword, + agIOInfoLen, + agParam, + satIOContext, + interruptContext); + break; + + + case OSSA_IO_ABORTED: + SM_DBG1(("smsatProcessAbnormalCompletion: agIOStatus = OSSA_IO_ABORTED!!!\n")); + + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailAborted, + agNULL, + interruptContext); + +#ifdef REMOVED + if ( oneDeviceData->satTmTaskTag != agNULL ) + { + SM_DBG1(("smsatProcessAbnormalCompletion: TM callback!!!\n")); + if (smDeviceHandle == agNULL) + { + SM_DBG1(("smsatProcessAbnormalCompletion: wrong, smDeviceHandle is NULL!!!\n")); + } + /* TM completed */ + tdsmEventCB( smRoot, + smDeviceHandle, + smIntrEventTypeTaskManagement, + smTMOK, + oneDeviceData->satTmTaskTag); + /* + * Reset flag + */ + oneDeviceData->satTmTaskTag = agNULL; + } +#endif + + /* + * Check if we are in recovery mode and need to update the recovery flag + */ + if ((oneDeviceData->satDriveState == SAT_DEV_STATE_IN_RECOVERY ) && + (oneDeviceData->satPendingIO == 0 )) + { + oneDeviceData->satDriveState = SAT_DEV_STATE_NORMAL; + SM_DBG1(("smsatProcessAbnormalCompletion: STATE NORMAL!!!\n")); + } + + SM_DBG1(("smsatProcessAbnormalCompletion: did %d satDriveState %d!!!\n", oneDeviceData->id, oneDeviceData->satDriveState)); + SM_DBG1(("smsatProcessAbnormalCompletion: satPendingIO %d satNCQMaxIO %d!!!\n", oneDeviceData->satPendingIO, oneDeviceData->satNCQMaxIO )); + SM_DBG1(("smsatProcessAbnormalCompletion: satPendingNCQIO %d satPendingNONNCQIO %d!!!\n", oneDeviceData->satPendingNCQIO, oneDeviceData->satPendingNONNCQIO)); + + break; +#ifdef REMOVED + case OSSA_IO_OVERFLOW: + SM_DBG1(("smsatProcessAbnormalCompletion: agIOStatus = OSSA_IO_OVERFLOW!!!\n")); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOOverRun, + agIOInfoLen, + agNULL, + interruptContext); + break; +#endif + case OSSA_IO_UNDERFLOW: + SM_DBG1(("smsatProcessAbnormalCompletion: agIOStatus = OSSA_IO_UNDERFLOW!!!\n")); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOUnderRun, + agIOInfoLen, + agNULL, + interruptContext); + break; + + + case OSSA_IO_FAILED: + SM_DBG1(("smsatProcessAbnormalCompletion: agIOStatus = OSSA_IO_FAILED!!!\n")); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + break; + + case OSSA_IO_ABORT_RESET: + SM_DBG1(("smsatProcessAbnormalCompletion: agIOStatus = OSSA_IO_ABORT_RESET!!!\n")); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailAbortReset, + agNULL, + interruptContext); + /* + * Check if we are in recovery mode and need to update the recovery flag + */ + if ((oneDeviceData->satDriveState == SAT_DEV_STATE_IN_RECOVERY ) && + (oneDeviceData->satPendingIO == 0 )) + { + oneDeviceData->satDriveState = SAT_DEV_STATE_NORMAL; + SM_DBG1(("smsatProcessAbnormalCompletion: STATE NORMAL!!!\n")); + } + + SM_DBG1(("smsatProcessAbnormalCompletion: satDriveState %d!!!\n", oneDeviceData->satDriveState)); + SM_DBG1(("smsatProcessAbnormalCompletion: satPendingIO %d satNCQMaxIO %d!!!\n", oneDeviceData->satPendingIO, oneDeviceData->satNCQMaxIO )); + SM_DBG1(("smsatProcessAbnormalCompletion: satPendingNCQIO %d satPendingNONNCQIO %d!!!\n", oneDeviceData->satPendingNCQIO, oneDeviceData->satPendingNONNCQIO)); + + break; + +#ifdef REMOVED + case OSSA_IO_NOT_VALID: + SM_DBG1(("smsatProcessAbnormalCompletion: agIOStatus = OSSA_IO_NOT_VALID!!!\n")); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailNotValid, + agNULL, + interruptContext); + break; +#endif + + case OSSA_IO_NO_DEVICE: + SM_DBG1(("smsatProcessAbnormalCompletion: agIOStatus = OSSA_IO_NO_DEVICE!!!\n")); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailNoLogin, + agNULL, + interruptContext); + break; + +#ifdef REMOVED /* removed from spec */ + case OSSA_IO_ILLEGAL_PARAMETER: + SM_DBG1(("smsatProcessAbnormalCompletion: agIOStatus = OSSA_IO_ILLEGAL_PARAMETER!!!\n")); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + break; + + case OSSA_IO_LINK_FAILURE: + SM_DBG1(("smsatProcessAbnormalCompletion: agIOStatus = OSSA_IO_LINK_FAILURE!!!\n")); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + break; + + case OSSA_IO_PROG_ERROR: + SM_DBG1(("smsatProcessAbnormalCompletion: agIOStatus = OSSA_IO_PROG_ERROR!!!\n")); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + break; +#endif + case OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: /* fall through */ + case OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION: /* fall through */ + case OSSA_IO_OPEN_CNX_ERROR_BREAK: /* fall through */ + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: /* fall through */ + case OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION: /* fall through */ + case OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: /* fall through */ + case OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION: /* fall through */ + case OSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED: /* fall through */ +#ifdef REMOVED /* removed from spec */ + case OSSA_IO_OPEN_CNX_ERROR_UNKNOWN_ERROR: /* fall through */ +#endif + SM_DBG1(("smsatProcessAbnormalCompletion: agIOStatus = OSSA_IO_OPEN_CNX_ERROR_* 0x%x!!!\n", agIOStatus)); + if (smDeviceHandle == agNULL) + { + SM_DBG1(("smsatProcessAbnormalCompletion: wrong, smDeviceHandle is NULL!!!\n")); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + return; + } + if (oneDeviceData == agNULL) + { + SM_DBG1(("smsatProcessAbnormalCompletion: wrong, oneDeviceData is NULL!!!\n")); + } + else + { + SM_DBG1(("smsatProcessAbnormalCompletion: did %d!!!\n", oneDeviceData->id)); + } + + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + break; + case OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: + SM_DBG1(("smsatProcessAbnormalCompletion: agIOStatus = OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY!!!\n")); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailBusy, + agNULL, + interruptContext); + break; +#ifdef REMOVED + case OSSA_IO_XFER_ERROR_BREAK: /* fall throuth */ +#endif + + case OSSA_IO_XFER_ERROR_PHY_NOT_READY: /* fall throuth */ + case OSSA_IO_XFER_ERROR_NAK_RECEIVED: /* fall throuth */ + +#ifdef REMOVED + case OSSA_IO_XFER_ERROR_ACK_NAK_TIMEOUT: /* fall throuth */ + case OSSA_IO_XFER_ERROR_PEER_ABORTED: /* fall throuth */ +#endif + case OSSA_IO_XFER_ERROR_DMA: /* fall throuth */ +#ifdef REMOVED + case OSSA_IO_XFER_ERROR_RX_FRAME: /* fall throuth */ + case OSSA_IO_XFER_ERROR_CREDIT_TIMEOUT: /* fall throuth */ + case OSSA_IO_XFER_ERROR_SATA: /* fall throuth */ +#endif + case OSSA_IO_XFER_ERROR_SATA_LINK_TIMEOUT: /* fall throuth */ + case OSSA_IO_XFER_ERROR_ABORTED_DUE_TO_SRST: /* fall throuth */ + case OSSA_IO_XFER_ERROR_REJECTED_NCQ_MODE: /* fall throuth */ +#ifdef REMOVED + case OSSA_IO_XFER_ERR_EOB_DATA_OVERRUN: + case OSSA_IO_XFER_ERROR_ABORTED_NCQ_MODE: /* fall throuth */ + case OSSA_IO_XFER_ERROR_DISRUPTED_PHY_DOWN: /* fall throuth */ + case OSSA_IO_XFER_ERROR_OFFSET_MISMATCH: /* fall throuth */ + case OSSA_IO_XFER_ERROR_XFER_ZERO_DATA_LEN: /* fall throuth */ +#endif + SM_DBG1(("smsatProcessAbnormalCompletion: agIOStatus = OSSA_IO_XFER_ERROR_* 0x%x!!!\n", agIOStatus)); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + break; +#ifdef REMOVED + case OSSA_IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT: /* fall throuth */ + case OSSA_IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK: /* fall throuth */ + case OSSA_IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK: /* fall throuth */ + SM_DBG1(("smsatProcessAbnormalCompletion: agIOStatus = OSSA_IO_XFER_ERROR_CMD_ISSUE_* 0x%x!!!\n", agIOStatus)); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + break; + case OSSA_IO_XFER_PIO_SETUP_ERROR: + SM_DBG1(("smsatProcessAbnormalCompletion: agIOStatus = OSSA_IO_XFER_PIO_SETUP_ERROR!!!\n")); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + break; +#endif + case OSSA_IO_DS_IN_ERROR: + SM_DBG1(("smsatProcessAbnormalCompletion: agIOStatus = OSSA_IO_DS_IN_ERROR!!!\n")); + if (smDeviceHandle == agNULL) + { + SM_DBG1(("smsatProcessAbnormalCompletion: wrong, smDeviceHandle is NULL!!!\n")); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + return; + } + if (oneDeviceData == agNULL) + { + SM_DBG1(("smsatProcessAbnormalCompletion: wrong, oneDeviceData is NULL!!!\n")); + } + else + { + SM_DBG1(("smsatProcessAbnormalCompletion: did %d!!!\n", oneDeviceData->id)); + } + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + break; + case OSSA_IO_DS_NON_OPERATIONAL: + SM_DBG1(("smsatProcessAbnormalCompletion: agIOStatus = OSSA_IO_DS_NON_OPERATIONAL!!!\n")); + if (smDeviceHandle == agNULL) + { + SM_DBG1(("smsatProcessAbnormalCompletion: wrong, smDeviceHandle is NULL!!!\n")); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + return; + } + if (oneDeviceData == agNULL) + { + SM_DBG1(("smsatProcessAbnormalCompletion: wrong, oneDeviceData is NULL!!!\n")); + } + else + { + SM_DBG1(("smsatProcessAbnormalCompletion: did %d!!!\n", oneDeviceData->id)); + agDevHandle = oneDeviceData->agDevHandle; + if (oneDeviceData->valid == agTRUE) + { + saSetDeviceState(agRoot, agNULL, tdsmRotateQnumber(smRoot, smDeviceHandle), agDevHandle, SA_DS_OPERATIONAL); + } + } + + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + break; + + case OSSA_IO_PORT_IN_RESET: + case OSSA_IO_DS_IN_RECOVERY: + SM_DBG1(("smsatProcessAbnormalCompletion: OSSA_IO_DS_IN_RECOVERY or OSSA_IO_PORT_IN_RESET status %x\n", agIOStatus)); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + break; + + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: + SM_DBG1(("smsatProcessAbnormalCompletion: SSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_XX status %x\n", agIOStatus)); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + break; + + case OSSA_MPI_IO_RQE_BUSY_FULL: + case OSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE: + case OSSA_MPI_ERR_ATAPI_DEVICE_BUSY: + SM_DBG1(("smsatProcessAbnormalCompletion: agIOStatus = OSSA_MPI_%x!!!\n", agIOStatus)); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailBusy, + agNULL, + interruptContext); + break; + + case OSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS: /* fall through */ +#ifdef REMOVED + case OSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH: +#endif + case OSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID: /* fall through */ + case OSSA_IO_XFR_ERROR_DEK_IV_MISMATCH: /* fall through */ + case OSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR: /* fall through */ + case OSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS: + case OSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE: + + SM_DBG1(("smsatProcessAbnormalCompletion: agIOStatus = ENCRYPTION ERROR 0x%x!!!\n", agIOStatus)); + smsatEncryptionHandler(smRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + 0, + interruptContext); + break; + +#ifdef REMOVED + case OSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH: /* fall through */ + case OSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH: /* fall through */ + case OSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH: + SM_DBG1(("smsatProcessAbnormalCompletion: agIOStatus = DIF ERROR 0x%x!!!\n", agIOStatus)); + smsatDifHandler(smRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + 0, + interruptContext); + break; +#endif + + default: + SM_DBG1(("smsatProcessAbnormalCompletion: agIOStatus = unknown 0x%x!!!\n", agIOStatus)); + if (oneDeviceData != agNULL) + { + SM_DBG1(("smsatProcessAbnormalCompletion: did %d!!!\n", oneDeviceData->id)); + } + else + { + SM_DBG1(("smsatProcessAbnormalCompletion: oneDeviceData is NULL!!!\n")); + } + + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + break; + + } /* switch */ + + return; +} + +osGLOBAL void +smsatDelayedProcessAbnormalCompletion( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + smSatIOContext_t *satIOContext + ) +{ + smRoot_t *smRoot = agNULL; +// tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; +// tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; +// bit32 interruptContext = osData->IntContext; + bit32 interruptContext; + smIORequestBody_t *smIORequestBody; +// satDeviceData_t *pSatDevData; + smDeviceHandle_t *smDeviceHandle; + smDeviceData_t *oneDeviceData = agNULL; + agsaDevHandle_t *agDevHandle = agNULL; + + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + oneDeviceData = satIOContext->pSatDevData; + if (oneDeviceData == agNULL) + { + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: oneDeviceData is NULL\n")); + return; + } + smDeviceHandle = satIOContext->psmDeviceHandle; + smRoot = oneDeviceData->smRoot; + interruptContext = satIOContext->interruptContext; + + SM_DBG5(("smsatDelayedProcessAbnormalCompletion: start\n")); + + /* Get into the detail */ + switch(agIOStatus) + { + case OSSA_IO_SUCCESS: + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: agIOStatus = OSSA_IO_SUCCESS calling smsatIOCompleted!!!\n")); + /* do nothing */ + break; + + + case OSSA_IO_ABORTED: + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: agIOStatus = OSSA_IO_ABORTED!!!\n")); + + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailAborted, + agNULL, + interruptContext); + + if ( oneDeviceData->satTmTaskTag != agNULL ) + { + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: TM callback!!!\n")); + if (smDeviceHandle == agNULL) + { + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: wrong, smDeviceHandle is NULL!!!\n")); + } + else + { + /* TM completed */ + tdsmEventCB( smRoot, + smDeviceHandle, + smIntrEventTypeTaskManagement, + smTMOK, + oneDeviceData->satTmTaskTag); + /* + * Reset flag + */ + oneDeviceData->satTmTaskTag = agNULL; + } + } + + /* + * Check if we are in recovery mode and need to update the recovery flag + */ + if ((oneDeviceData->satDriveState == SAT_DEV_STATE_IN_RECOVERY ) && + (oneDeviceData->satPendingIO == 0 )) + { + oneDeviceData->satDriveState = SAT_DEV_STATE_NORMAL; + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: STATE NORMAL.!!!\n")); + } + + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: satDriveState %d!!!\n", oneDeviceData->satDriveState)); + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: satPendingIO %d satNCQMaxIO %d!!!\n", oneDeviceData->satPendingIO, oneDeviceData->satNCQMaxIO )); + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: satPendingNCQIO %d satPendingNONNCQIO %d!!!\n", oneDeviceData->satPendingNCQIO, oneDeviceData->satPendingNONNCQIO)); + + break; +#ifdef REMOVED + case OSSA_IO_OVERFLOW: + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: agIOStatus = OSSA_IO_OVERFLOW!!!\n")); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOOverRun, + agIOInfoLen, + agNULL, + interruptContext); + break; +#endif + case OSSA_IO_UNDERFLOW: + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: agIOStatus = OSSA_IO_UNDERFLOW!!!\n")); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOUnderRun, + agIOInfoLen, + agNULL, + interruptContext); + break; + + + case OSSA_IO_FAILED: + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: agIOStatus = OSSA_IO_FAILED!!!\n")); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + break; + + case OSSA_IO_ABORT_RESET: + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: agIOStatus = OSSA_IO_ABORT_RESET!!!\n")); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailAbortReset, + agNULL, + interruptContext); + /* + * Check if we are in recovery mode and need to update the recovery flag + */ + if ((oneDeviceData->satDriveState == SAT_DEV_STATE_IN_RECOVERY ) && + (oneDeviceData->satPendingIO == 0 )) + { + oneDeviceData->satDriveState = SAT_DEV_STATE_NORMAL; + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: STATE NORMAL.!!!\n")); + } + + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: satDriveState %d!!!\n", oneDeviceData->satDriveState)); + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: satPendingIO %d satNCQMaxIO %d!!!\n", oneDeviceData->satPendingIO, oneDeviceData->satNCQMaxIO )); + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: satPendingNCQIO %d satPendingNONNCQIO %d!!!\n", oneDeviceData->satPendingNCQIO, oneDeviceData->satPendingNONNCQIO)); + + break; + +#ifdef REMOVED + case OSSA_IO_NOT_VALID: + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: agIOStatus = OSSA_IO_NOT_VALID!!!\n")); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailNotValid, + agNULL, + interruptContext); + break; +#endif + + case OSSA_IO_NO_DEVICE: + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: agIOStatus = OSSA_IO_NO_DEVICE!!!\n")); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailNoLogin, + agNULL, + interruptContext); + break; + +#ifdef REMOVED /* removed from spec */ + case OSSA_IO_ILLEGAL_PARAMETER: + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: agIOStatus = OSSA_IO_ILLEGAL_PARAMETER!!!\n")); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + break; + + case OSSA_IO_LINK_FAILURE: + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: agIOStatus = OSSA_IO_LINK_FAILURE!!!\n")); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + break; + + case OSSA_IO_PROG_ERROR: + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: agIOStatus = OSSA_IO_PROG_ERROR!!!\n")); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + break; +#endif + case OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: /* fall through */ + case OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION: /* fall through */ + case OSSA_IO_OPEN_CNX_ERROR_BREAK: /* fall through */ + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: /* fall through */ + case OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION: /* fall through */ + case OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: /* fall through */ + case OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION: /* fall through */ + case OSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED: /* fall through */ +#ifdef REMOVED /* removed from spec */ + case OSSA_IO_OPEN_CNX_ERROR_UNKNOWN_ERROR: /* fall through */ +#endif + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: agIOStatus = OSSA_IO_OPEN_CNX_ERROR_* 0x%x!!!\n", agIOStatus)); + if (smDeviceHandle == agNULL) + { + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: wrong, smDeviceHandle is NULL!!!\n")); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + return; + } + if (oneDeviceData == agNULL) + { + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: wrong, oneDeviceData is NULL!!!\n")); + } + else + { + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: did %d!!!\n", oneDeviceData->id)); + } + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + break; + + case OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: agIOStatus = OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY!!!\n")); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailBusy, + agNULL, + interruptContext); + break; +#ifdef REMOVED + case OSSA_IO_XFER_ERROR_BREAK: /* fall throuth */ +#endif + + case OSSA_IO_XFER_ERROR_PHY_NOT_READY: /* fall throuth */ + case OSSA_IO_XFER_ERROR_NAK_RECEIVED: /* fall throuth */ + +#ifdef REMOVED + case OSSA_IO_XFER_ERROR_ACK_NAK_TIMEOUT: /* fall throuth */ + case OSSA_IO_XFER_ERROR_PEER_ABORTED: /* fall throuth */ +#endif + + case OSSA_IO_XFER_ERROR_DMA: /* fall throuth */ + +#ifdef REMOVED + case OSSA_IO_XFER_ERROR_RX_FRAME: /* fall throuth */ + case OSSA_IO_XFER_ERROR_CREDIT_TIMEOUT: /* fall throuth */ + case OSSA_IO_XFER_ERROR_SATA: /* fall throuth */ +#endif + case OSSA_IO_XFER_ERROR_SATA_LINK_TIMEOUT: /* fall throuth */ + case OSSA_IO_XFER_ERROR_ABORTED_DUE_TO_SRST: /* fall throuth */ + case OSSA_IO_XFER_ERROR_REJECTED_NCQ_MODE: /* fall throuth */ +#ifdef REMOVED + case OSSA_IO_XFER_ERROR_ABORTED_NCQ_MODE: /* fall throuth */ + case OSSA_IO_XFER_ERROR_DISRUPTED_PHY_DOWN: /* fall throuth */ + case OSSA_IO_XFER_ERROR_OFFSET_MISMATCH: /* fall throuth */ + case OSSA_IO_XFER_ERROR_XFER_ZERO_DATA_LEN: /* fall throuth */ +#endif + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: agIOStatus = OSSA_IO_XFER_ERROR_* 0x%x!!!\n", agIOStatus)); + + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + break; +#ifdef REMOVED + case OSSA_IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT: /* fall throuth */ + case OSSA_IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK: /* fall throuth */ + case OSSA_IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK: /* fall throuth */ + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: agIOStatus = OSSA_IO_XFER_ERROR_CMD_ISSUE_* 0x%x!!!\n", agIOStatus)); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + break; + case OSSA_IO_XFER_PIO_SETUP_ERROR: + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: agIOStatus = OSSA_IO_XFER_PIO_SETUP_ERROR!!!\n")); + if (smDeviceHandle == agNULL) + { + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: wrong, smDeviceHandle is NULL!!!\n")); + } + if (oneDeviceData == agNULL) + { + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: wrong, oneDeviceData is NULL!!!\n")); + } + else + { + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: did %d!!!\n", oneDeviceData->id)); + } + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + break; +#endif + case OSSA_IO_DS_IN_ERROR: + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: agIOStatus = OSSA_IO_DS_IN_ERROR!!!\n")); + if (smDeviceHandle == agNULL) + { + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: wrong, smDeviceHandle is NULL!!!\n")); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + return; + } + if (oneDeviceData == agNULL) + { + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: wrong, oneDeviceData is NULL!!!\n")); + } + else + { + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: did %d!!!\n", oneDeviceData->id)); + } + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + break; + case OSSA_IO_DS_NON_OPERATIONAL: + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: agIOStatus = OSSA_IO_DS_NON_OPERATIONAL!!!\n")); + if (smDeviceHandle == agNULL) + { + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: wrong, smDeviceHandle is NULL!!!\n")); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + return; + } + if (oneDeviceData == agNULL) + { + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: wrong, oneDeviceData is NULL!!!\n")); + } + else + { + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: did %d!!!\n", oneDeviceData->id)); + agDevHandle = oneDeviceData->agDevHandle; + if (oneDeviceData->valid == agTRUE) + { + saSetDeviceState(agRoot, agNULL, tdsmRotateQnumber(smRoot, smDeviceHandle), agDevHandle, SA_DS_OPERATIONAL); + } + } + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + break; + + case OSSA_IO_PORT_IN_RESET: + case OSSA_IO_DS_IN_RECOVERY: + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: OSSA_IO_DS_IN_RECOVERY or OSSA_IO_PORT_IN_RESET status %x\n", agIOStatus)); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + break; + + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: SSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_XX status %x\n", agIOStatus)); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + break; + case OSSA_IO_DS_INVALID: + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: OSSA_IO_DS_INVALID status %x\n", agIOStatus)); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + break; + + case OSSA_MPI_IO_RQE_BUSY_FULL: + case OSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE: + case OSSA_MPI_ERR_ATAPI_DEVICE_BUSY: + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: agIOStatus = OSSA_MPI_%x!!!\n", agIOStatus)); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailBusy, + agNULL, + interruptContext); + break; + + case OSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS: /* fall through */ +#ifdef REMOVED + case OSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH: +#endif + case OSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID: /* fall through */ + case OSSA_IO_XFR_ERROR_DEK_IV_MISMATCH: /* fall through */ + case OSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR: /* fall through */ + case OSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS: + case OSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE: + + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: agIOStatus = ENCRYPTION ERROR 0x%x!!!\n", agIOStatus)); + smsatEncryptionHandler(smRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + 0, + interruptContext); + break; + +#ifdef REMOVED + case OSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH: /* fall through */ + case OSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH: /* fall through */ + case OSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH: + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: agIOStatus = DIF ERROR 0x%x!!!\n", agIOStatus)); + smsatDifHandler(smRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + 0, + interruptContext); + break; +#endif + + default: + SM_DBG1(("smsatDelayedProcessAbnormalCompletion: agIOStatus = unknown!!!\n")); + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + break; + + } /* switch */ + return; +} + +osGLOBAL void +smsatIDStartCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + /* + In the process of SAT_IDENTIFY_DEVICE during discovery + */ +// tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; +// tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; +// tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; +// tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smIORequestBody_t *smOrgIORequestBody = agNULL; + smDeviceHandle_t *smDeviceHandle; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatIOContext_t *satNewIOContext; + smSatInternalIo_t *satIntIo; + smSatInternalIo_t *satNewIntIo = agNULL; + smDeviceData_t *oneDeviceData; + smIORequest_t *smOrgIORequest = agNULL; +// agsaFisRegD2HData_t *deviceToHostFisData = agNULL; +// bit8 signature[8]; +#ifdef TD_DEBUG_ENABLE + agsaFisPioSetupHeader_t *satPIOSetupHeader = agNULL; + bit32 ataStatus = 0; + bit32 ataError; +#endif + agsaSATAIdentifyData_t *pSATAIdData; + bit16 *tmpptr, tmpptr_tmp; + bit32 x; + void *sglVirtualAddr; + bit32 status = 0; +// tdsaPortContext_t *onePortContext = agNULL; +// tiPortalContext_t *tiPortalContext = agNULL; +// bit32 retry_status; + smIORequest_t *smIORequest; + agsaDevHandle_t *agDevHandle = agNULL; + + SM_DBG1(("smsatIDStartCB: start\n")); + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + smDeviceHandle = satIOContext->psmDeviceHandle; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + SM_DBG1(("smsatIDStartCB: did %d\n", oneDeviceData->id)); +// onePortContext = oneDeviceData->tdPortContext; +// tiPortalContext= onePortContext->tiPortalContext; + oneDeviceData->IDDeviceValid = agFALSE; + if (satIntIo == agNULL) + { + SM_DBG1(("smsatIDStartCB: External, OS generated!!!\n")); + SM_DBG1(("smsatIDStartCB: Not possible case!!!\n")); + satOrgIOContext = satIOContext; + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + else + { + SM_DBG3(("smsatIDStartCB: Internal, SM generated\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + SM_DBG5(("smsatIDStartCB: satOrgIOContext is NULL\n")); + } + else + { + SM_DBG5(("smsatIDStartCB: satOrgIOContext is NOT NULL\n")); + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + if (smOrgIORequestBody == agNULL) + { + SM_DBG1(("smsatIDStartCB: smOrgIORequestBody is NULL!!!\n")); + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource(smRoot, oneDeviceData, satIntIo); + return; + } + } + sglVirtualAddr = satIntIo->satIntSmScsiXchg.sglVirtualAddr; + } + smOrgIORequest = smIORequestBody->smIORequest; + smIORequest = smOrgIORequestBody->smIORequest; + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + + + if ( agIOStatus == OSSA_IO_XFER_OPEN_RETRY_TIMEOUT || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED || + agIOStatus == OSSA_IO_DS_NON_OPERATIONAL ) + { + SM_DBG1(("smsatIDStartCB: OPEN_RETRY_TIMEOUT or STP_RESOURCES_BUSY or OPEN_RETRY_BACKOFF_THRESHOLD_REACHED or OSSA_IO_DS_NON_OPERATIONAL!!! 0x%x\n", agIOStatus)); + SM_DBG1(("smsatIDStartCB: did %d!!!\n", oneDeviceData->id)); + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + SM_DBG2(("smsatIDStartCB: smOrgIORequestBody %p smIORequest %p\n", smOrgIORequestBody, smIORequest)); + SM_DBG2(("smsatIDStartCB: smOrgIORequestBody->id %d\n", smOrgIORequestBody->id)); + if (agIOStatus == OSSA_IO_XFER_OPEN_RETRY_TIMEOUT) + { + tdsmIDCompletedCB(smRoot, smIORequest, smDeviceHandle, smIORetry, &(oneDeviceData->satIdentifyData)); + } + else if ( agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED || + agIOStatus == OSSA_IO_DS_NON_OPERATIONAL ) + { + /* set device to operational */ + agDevHandle = oneDeviceData->agDevHandle; + if (oneDeviceData->valid == agTRUE) + { + saSetDeviceState(agRoot, agNULL, tdsmRotateQnumber(smRoot, smDeviceHandle), agDevHandle, SA_DS_OPERATIONAL); + } + tdsmIDCompletedCB(smRoot, smIORequest, smDeviceHandle, smIORetry, &(oneDeviceData->satIdentifyData)); + } + else + { + tdsmIDCompletedCB(smRoot, smIORequest, smDeviceHandle, smIOSTPResourceBusy, &(oneDeviceData->satIdentifyData)); + } + return; + } + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatIDStartCB: agFirstDword is NULL when error, status %d!!!\n", agIOStatus)); + SM_DBG1(("smsatIDStartCB: did %d!!!\n", oneDeviceData->id)); + SM_DBG1(("smsatIDStartCB: before pending IO %d NCQ pending IO %d NONNCQ pending IO %d\n", + oneDeviceData->satPendingIO, oneDeviceData->satPendingNCQIO, oneDeviceData->satPendingNONNCQIO)); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + SM_DBG1(("smsatIDStartCB: after pending IO %d NCQ pending IO %d NONNCQ pending IO %d\n", + oneDeviceData->satPendingIO, oneDeviceData->satPendingNCQIO, oneDeviceData->satPendingNONNCQIO)); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + SM_DBG2(("smsatIDStartCB: smOrgIORequestBody %p smIORequest %p\n", smOrgIORequestBody, smIORequest)); + SM_DBG2(("smsatIDStartCB: smOrgIORequestBody->id %d\n", smOrgIORequestBody->id)); + tdsmIDCompletedCB(smRoot, smIORequest, smDeviceHandle, smIOFailed, &(oneDeviceData->satIdentifyData)); + return; + } + + if (agIOStatus == OSSA_IO_ABORTED || + agIOStatus == OSSA_IO_UNDERFLOW || + agIOStatus == OSSA_IO_XFER_ERROR_BREAK || + agIOStatus == OSSA_IO_XFER_ERROR_PHY_NOT_READY || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_BREAK || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION || + agIOStatus == OSSA_IO_XFER_ERROR_NAK_RECEIVED || + agIOStatus == OSSA_IO_XFER_ERROR_DMA || + agIOStatus == OSSA_IO_XFER_ERROR_SATA_LINK_TIMEOUT || + agIOStatus == OSSA_IO_XFER_ERROR_REJECTED_NCQ_MODE || + agIOStatus == OSSA_IO_NO_DEVICE || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION || + agIOStatus == OSSA_IO_PORT_IN_RESET || + agIOStatus == OSSA_IO_DS_NON_OPERATIONAL || + agIOStatus == OSSA_IO_DS_IN_RECOVERY || + agIOStatus == OSSA_IO_DS_IN_ERROR || + agIOStatus == OSSA_IO_DS_INVALID + ) + { + SM_DBG1(("smsatIDStartCB: OSSA_IO_OPEN_CNX_ERROR 0x%x!!!\n", agIOStatus)); + SM_DBG1(("smsatIDStartCB: did %d!!!\n", oneDeviceData->id)); + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + + SM_DBG2(("smsatIDStartCB: smOrgIORequestBody %p smIORequest %p\n", smOrgIORequestBody, smIORequest)); + SM_DBG2(("smsatIDStartCB: smOrgIORequestBody->id %d\n", smOrgIORequestBody->id)); + tdsmIDCompletedCB(smRoot, smIORequest, smDeviceHandle, smIOFailed, &(oneDeviceData->satIdentifyData)); + return; + } + + if ( agIOStatus != OSSA_IO_SUCCESS || + (agIOStatus == OSSA_IO_SUCCESS && agFirstDword != agNULL && agIOInfoLen != 0) + ) + { +#ifdef TD_DEBUG_ENABLE + /* only agsaFisPioSetup_t is expected */ + satPIOSetupHeader = (agsaFisPioSetupHeader_t *)&(agFirstDword->PioSetup); + ataStatus = satPIOSetupHeader->status; /* ATA Status register */ + ataError = satPIOSetupHeader->error; /* ATA Eror register */ +#endif + SM_DBG1(("smsatIDStartCB: ataStatus 0x%x ataError 0x%x!!!\n", ataStatus, ataError)); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + SM_DBG2(("smsatIDStartCB: smOrgIORequestBody %p smIORequest %p\n", smOrgIORequestBody, smIORequest)); + SM_DBG2(("smsatIDStartCB: smOrgIORequestBody->id %d\n", smOrgIORequestBody->id)); + + { + tdsmIDCompletedCB(smRoot, smIORequest, smDeviceHandle, smIOFailed, &(oneDeviceData->satIdentifyData)); + } + return; + } + + + /* success */ + SM_DBG3(("smsatIDStartCB: Success\n")); + SM_DBG3(("smsatIDStartCB: Success did %d\n", oneDeviceData->id)); + + /* Convert to host endian */ + tmpptr = (bit16*)sglVirtualAddr; + for (x=0; x < sizeof(agsaSATAIdentifyData_t)/sizeof(bit16); x++) + { + OSSA_READ_LE_16(AGROOT, &tmpptr_tmp, tmpptr, 0); + *tmpptr = tmpptr_tmp; + tmpptr++; + } + + pSATAIdData = (agsaSATAIdentifyData_t *)sglVirtualAddr; + //smhexdump("satAddSATAIDDevCB before", (bit8 *)pSATAIdData, sizeof(agsaSATAIdentifyData_t)); + + SM_DBG5(("smsatIDStartCB: OS satOrgIOContext %p \n", satOrgIOContext)); + SM_DBG5(("smsatIDStartCB: TD satIOContext %p \n", satIOContext)); + SM_DBG5(("smsatIDStartCB: OS tiScsiXchg %p \n", satOrgIOContext->smScsiXchg)); + SM_DBG5(("smsatIDStartCB: TD tiScsiXchg %p \n", satIOContext->smScsiXchg)); + + + /* copy ID Dev data to oneDeviceData */ + oneDeviceData->satIdentifyData = *pSATAIdData; + oneDeviceData->IDDeviceValid = agTRUE; + +#ifdef SM_INTERNAL_DEBUG + smhexdump("smsatIDStartCB ID Dev data",(bit8 *)pSATAIdData, sizeof(agsaSATAIdentifyData_t)); + smhexdump("smsatIDStartCB Device ID Dev data",(bit8 *)&oneDeviceData->satIdentifyData, sizeof(agsaSATAIdentifyData_t)); +#endif + + /* set oneDeviceData fields from IndentifyData */ + smsatSetDevInfo(oneDeviceData,pSATAIdData); + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + if (smIORequest->tdData == smIORequest->smData) + { + SM_DBG1(("smsatIDStartCB: the same tdData and smData error!\n")); + } + + /* send the Set Feature ATA command to SATA device for enbling PIO and DMA transfer mode*/ + satNewIntIo = smsatAllocIntIoResource( smRoot, + smOrgIORequest, + oneDeviceData, + 0, + satNewIntIo); + + if (satNewIntIo == agNULL) + { + SM_DBG1(("smsatIDStartCB: momory allocation fails\n")); + tdsmIDCompletedCB(smRoot, smIORequest, smDeviceHandle, smIOFailed, &(oneDeviceData->satIdentifyData)); + return; + } /* end memory allocation */ + + satNewIOContext = smsatPrepareNewIO(satNewIntIo, + smOrgIORequest, + oneDeviceData, + agNULL, + satOrgIOContext + ); + /*enable PIO mode*/ + status = smsatSetFeaturesPIO(smRoot, + &satNewIntIo->satIntSmIORequest, + satNewIOContext->psmDeviceHandle, + &satNewIntIo->satIntSmScsiXchg, /* orginal from OS layer */ + satNewIOContext + ); + + if (status != SM_RC_SUCCESS) + { + smsatFreeIntIoResource(smRoot, + oneDeviceData, + satNewIntIo); + /* clean up TD layer's IORequestBody */ + tdsmIDCompletedCB(smRoot, smIORequest, smDeviceHandle, smIOFailed, &(oneDeviceData->satIdentifyData)); + } + + SM_DBG2(("smsatIDStartCB: End device id %d\n", oneDeviceData->id)); + return; +} + + +osGLOBAL void +smsatIOCompleted( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + agsaFisHeader_t *agFirstDword, + bit32 respFisLen, + agsaFrameHandle_t agFrameHandle, + smSatIOContext_t *satIOContext, + bit32 interruptContext + ) +{ +// satDeviceData_t *pSatDevData; + smDeviceData_t *oneDeviceData; + smScsiRspSense_t *pSense; +#ifdef TD_DEBUG_ENABLE + smIniScsiCmnd_t *pScsiCmnd; +#endif + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + bit32 ataError; + smSatInternalIo_t *satIntIo = agNULL; + bit32 status; +// agsaRoot_t *agRoot; +// agsaDevHandle_t *agDevHandle; + smDeviceHandle_t *smDeviceHandle; + smSatIOContext_t *satIOContext2; + smIORequestBody_t *smIORequestBody; + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + agsaFisSetDevBitsHeader_t *statSetDevBitFisHeader = agNULL; + smIORequest_t smIORequestTMP; + + pSense = satIOContext->pSense; + oneDeviceData = satIOContext->pSatDevData; +#ifdef TD_DEBUG_ENABLE + pScsiCmnd = satIOContext->pScsiCmnd; +#endif + hostToDevFis = satIOContext->pFis; + + +// agRoot = ((tdsaDeviceData_t *)(pSatDevData->satSaDeviceData))->agRoot; +// agDevHandle = ((tdsaDeviceData_t *)(pSatDevData->satSaDeviceData))->agDevHandle; +// tiDeviceHandle = &((tdsaDeviceData_t *)(pSatDevData->satSaDeviceData))->tiDeviceHandle; + smDeviceHandle = satIOContext->psmDeviceHandle; + /* + * Find out the type of response FIS: + * Set Device Bit FIS or Reg Device To Host FIS. + */ + + /* First assume it is Reg Device to Host FIS */ + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + ataError = statDevToHostFisHeader->error; /* ATA Eror register */ + + SM_DBG5(("smsatIOCompleted: start\n")); + + /* for debugging */ + SM_DBG1(("smsatIOCompleted: H to D command 0x%x!!!\n", hostToDevFis->h.command)); + SM_DBG1(("smsatIOCompleted: D to H fistype 0x%x!!!\n", statDevToHostFisHeader->fisType)); + + + if (statDevToHostFisHeader->fisType == SET_DEV_BITS_FIS) + { + /* It is Set Device Bits FIS */ + statSetDevBitFisHeader = (agsaFisSetDevBitsHeader_t *)&(agFirstDword->D2H); + /* Get ATA Status register */ + ataStatus = (statSetDevBitFisHeader->statusHi_Lo & 0x70); /* bits 4,5,6 */ + ataStatus = ataStatus | (statSetDevBitFisHeader->statusHi_Lo & 0x07); /* bits 0,1,2 */ + + /* ATA Eror register */ + ataError = statSetDevBitFisHeader->error; + + statDevToHostFisHeader = agNULL; + } + + else if (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) + { + SM_DBG1(("smsatIOCompleted: *** UNEXPECTED RESP FIS TYPE 0x%x *** smIORequest=%p!!!\n", + statDevToHostFisHeader->fisType, smIORequest)); + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_HARDWARE_ERROR, + 0, + SCSI_SNSCODE_INTERNAL_TARGET_FAILURE, + satIOContext); + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + interruptContext ); + return; + + } + + if ( ataStatus & DF_ATA_STATUS_MASK ) + { + oneDeviceData->satDeviceFaultState = agTRUE; + } + else + { + oneDeviceData->satDeviceFaultState = agFALSE; + } + + SM_DBG5(("smsatIOCompleted: smIORequest=%p CDB=0x%x ATA CMD =0x%x\n", + smIORequest, pScsiCmnd->cdb[0], hostToDevFis->h.command)); + + /* + * Decide which ATA command is the translation needed + */ + switch(hostToDevFis->h.command) + { + case SAT_READ_FPDMA_QUEUED: + case SAT_WRITE_FPDMA_QUEUED: + + /************************************************************************ + * + * !!!! See Section 13.5.2.4 of SATA 2.5 specs. !!!! + * !!!! If the NCQ error ends up here, it means that the device sent !!!! + * !!!! Set Device Bit FIS (which has SActive register) instead of !!!! + * !!!! Register Device To Host FIS (which does not have SActive !!!! + * !!!! register). The callback ossaSATAEvent() deals with the case !!!! + * !!!! where Register Device To Host FIS was sent by the device. !!!! + * + * For NCQ we need to issue READ LOG EXT command with log page 10h + * to get the error and to allow other I/Os to continue. + * + * Here is the basic flow or sequence of error recovery, note that due + * to the SATA HW assist that we have, this sequence is slighly different + * from the one described in SATA 2.5: + * + * 1. Set SATA device flag to indicate error condition and returning busy + * for all new request. + * return SM_RC_SUCCESS; + + * 2. Because the HW/LL layer received Set Device Bit FIS, it can get the + * tag or I/O context for NCQ request, SATL would translate the ATA error + * to SCSI status and return the original NCQ I/O with the appopriate + * SCSI status. + * + * 3. Prepare READ LOG EXT page 10h command. Set flag to indicate that + * the failed I/O has been returned to the OS Layer. Send command. + * + * 4. When the device receives READ LOG EXT page 10h request all other + * pending I/O are implicitly aborted. No completion (aborted) status + * will be sent to the host for these aborted commands. + * + * 5. SATL receives the completion for READ LOG EXT command in + * smsatReadLogExtCB(). Steps 6,7,8,9 below are the step 1,2,3,4 in + * smsatReadLogExtCB(). + * + * 6. Check flag that indicates whether the failed I/O has been returned + * to the OS Layer. If not, search the I/O context in device data + * looking for a matched tag. Then return the completion of the failed + * NCQ command with the appopriate/trasnlated SCSI status. + * + * 7. Issue abort to LL layer to all other pending I/Os for the same SATA + * drive. + * + * 8. Free resource allocated for the internally generated READ LOG EXT. + * + * 9. At the completion of abort, in the context of ossaSATACompleted(), + * return the I/O with error status to the OS-App Specific layer. + * When all I/O aborts are completed, clear SATA device flag to + * indicate ready to process new request. + * + ***********************************************************************/ + + SM_DBG1(("smsatIOCompleted: NCQ ERROR smIORequest=%p ataStatus=0x%x ataError=0x%x!!!\n", + smIORequest, ataStatus, ataError )); + + /* Set flag to indicate we are in recovery */ + oneDeviceData->satDriveState = SAT_DEV_STATE_IN_RECOVERY; + + /* Return the failed NCQ I/O to OS-Apps Specifiic layer */ + smsatDefaultTranslation( smRoot, + smIORequest, + satIOContext, + pSense, + (bit8)ataStatus, + (bit8)ataError, + interruptContext ); + + /* + * Allocate resource for READ LOG EXT page 10h + */ + satIntIo = smsatAllocIntIoResource( smRoot, + &(smIORequestTMP), /* anything but NULL */ + oneDeviceData, + sizeof (satReadLogExtPage10h_t), + satIntIo); + + /* + * If we cannot allocate resource for READ LOG EXT 10 in order to do + * the normal NCQ recovery, we will do SATA device reset. + */ + if (satIntIo == agNULL) + { + SM_DBG1(("smsatIOCompleted: can't send RLE due to resource lack!!!\n")); + + /* Abort I/O after completion of device reset */ + oneDeviceData->satAbortAfterReset = agTRUE; +#ifdef NOT_YET + /* needs further investigation */ + /* no report to OS layer */ + satSubTM(smRoot, + smDeviceHandle, + SM_INTERNAL_TM_RESET, + agNULL, + agNULL, + agNULL, + agFALSE); +#endif + + + SM_DBG1(("smsatIOCompleted: calling saSATADeviceReset 1!!!\n")); + return; + } + + + /* + * Set flag to indicate that the failed I/O has been returned to the + * OS-App specific Layer. + */ + satIntIo->satIntFlag = AG_SAT_INT_IO_FLAG_ORG_IO_COMPLETED; + + /* compare to satPrepareNewIO() */ + /* Send READ LOG EXIT page 10h command */ + + /* + * Need to initialize all the fields within satIOContext except + * reqType and satCompleteCB which will be set depending on cmd. + */ + + smIORequestBody = (smIORequestBody_t *)satIntIo->satIntRequestBody; + satIOContext2 = &(smIORequestBody->transport.SATA.satIOContext); + + satIOContext2->pSatDevData = oneDeviceData; + satIOContext2->pFis = &(smIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev); + satIOContext2->pScsiCmnd = &(satIntIo->satIntSmScsiXchg.scsiCmnd); + satIOContext2->pSense = &(smIORequestBody->transport.SATA.sensePayload); + satIOContext2->pSmSenseData = &(smIORequestBody->transport.SATA.smSenseData); + satIOContext2->pSmSenseData->senseData = satIOContext2->pSense; + + satIOContext2->smRequestBody = satIntIo->satIntRequestBody; + satIOContext2->interruptContext = interruptContext; + satIOContext2->satIntIoContext = satIntIo; + + satIOContext2->psmDeviceHandle = smDeviceHandle; + satIOContext2->satOrgIOContext = agNULL; + satIOContext2->smScsiXchg = agNULL; + + status = smsatSendReadLogExt( smRoot, + &satIntIo->satIntSmIORequest, + smDeviceHandle, + &satIntIo->satIntSmScsiXchg, + satIOContext2); + + if (status != SM_RC_SUCCESS) + { + SM_DBG1(("smsatIOCompleted: can't send RLE due to LL api failure!!!\n")); + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + /* Abort I/O after completion of device reset */ + oneDeviceData->satAbortAfterReset = agTRUE; +#ifdef NOT_YET + /* needs further investigation */ + /* no report to OS layer */ + satSubTM(smRoot, + smDeviceHandle, + SM_INTERNAL_TM_RESET, + agNULL, + agNULL, + agNULL, + agFALSE); +#endif + + SM_DBG1(("smsatIOCompleted: calling saSATADeviceReset 2!!!\n")); + return; + } + + break; + + case SAT_READ_DMA_EXT: + /* fall through */ + /* Use default status/error translation */ + + case SAT_READ_DMA: + /* fall through */ + /* Use default status/error translation */ + + default: + smsatDefaultTranslation( smRoot, + smIORequest, + satIOContext, + pSense, + (bit8)ataStatus, + (bit8)ataError, + interruptContext ); + break; + + } /* end switch */ + return; +} + + +osGLOBAL void +smsatEncryptionHandler( + smRoot_t *smRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo, + bit32 interruptContext + ) +{ + smIORequestBody_t *smIORequestBody; + bit32 errorDetail = smDetailOtherError; + + SM_DBG1(("smsatEncryptionHandler: start\n")); + SM_DBG1(("smsatEncryptionHandler: agIOStatus 0x%x\n", agIOStatus)); + + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + + switch (agIOStatus) + { + case OSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS: + SM_DBG1(("smsatEncryptionHandler: OSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS\n")); + errorDetail = smDetailDekKeyCacheMiss; + break; + case OSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID: + SM_DBG1(("smsatEncryptionHandler: OSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID\n")); + errorDetail = smDetailCipherModeInvalid; + break; + case OSSA_IO_XFR_ERROR_DEK_IV_MISMATCH: + SM_DBG1(("smsatEncryptionHandler: OSSA_IO_XFR_ERROR_DEK_IV_MISMATCH\n")); + errorDetail = smDetailDekIVMismatch; + break; + case OSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR: + SM_DBG1(("smsatEncryptionHandler: OSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR\n")); + errorDetail = smDetailDekRamInterfaceError; + break; + case OSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS: + SM_DBG1(("smsatEncryptionHandler: OSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS\n")); + errorDetail = smDetailDekIndexOutofBounds; + break; + case OSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE: + SM_DBG1(("smsatEncryptionHandler:OSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE\n")); + errorDetail = smDetailOtherError; + break; + default: + SM_DBG1(("smsatEncryptionHandler: other error!!! 0x%x\n", agIOStatus)); + errorDetail = smDetailOtherError; + break; + } + + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOEncryptError, + errorDetail, + agNULL, + interruptContext + ); + return; +} + +osGLOBAL void +smsatDifHandler( + smRoot_t *smRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo, + bit32 interruptContext + ) +{ + smIORequestBody_t *smIORequestBody; + bit32 errorDetail = smDetailOtherError; +#ifdef TD_DEBUG_ENABLE + agsaDifDetails_t *DifDetail; +#endif + + SM_DBG1(("smsatDifHandler: start\n")); + SM_DBG1(("smsatDifHandler: agIOStatus 0x%x\n", agIOStatus)); + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; +#ifdef TD_DEBUG_ENABLE + DifDetail = (agsaDifDetails_t *)agParam; +#endif + + switch (agIOStatus) + { + case OSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH: + SM_DBG1(("smsatDifHandler: OSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH\n")); + errorDetail = smDetailDifAppTagMismatch; + break; + case OSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH: + SM_DBG1(("smsatDifHandler: OSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH\n")); + errorDetail = smDetailDifRefTagMismatch; + break; + case OSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH: + SM_DBG1(("smsatDifHandler: OSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH\n")); + errorDetail = smDetailDifCrcMismatch; + break; + default: + SM_DBG1(("smsatDifHandler: other error!!! 0x%x\n", agIOStatus)); + errorDetail = smDetailOtherError; + break; + } + + SM_DBG1(("smsatDifHandler: DIF detail UpperLBA 0x%08x LowerLBA 0x%08x\n", DifDetail->UpperLBA, DifDetail->LowerLBA)); + + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIODifError, + errorDetail, + agNULL, + interruptContext + ); + return; +} + +osGLOBAL void +smsatProcessAbort( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smSatIOContext_t *satIOContext + ) +{ + smDeviceData_t *oneDeviceData; +#ifdef REMOVED + smDeviceHandle_t *smDeviceHandle; +#endif + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + + SM_DBG5(("smsatProcessAbort: start\n")); + + oneDeviceData = satIOContext->pSatDevData; +#ifdef REMOVED + smDeviceHandle = satIOContext->psmDeviceHandle; +#endif + hostToDevFis = satIOContext->pFis; + + if ( (hostToDevFis->h.command == SAT_SMART && hostToDevFis->h.features == SAT_SMART_EXEUTE_OFF_LINE_IMMEDIATE) && + (hostToDevFis->d.lbaLow != 0x01 && hostToDevFis->d.lbaLow != 0x02) + ) + { + /* no completion for send diagnotic in background. It is done in satSendDiagnostic() */ + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOFailed, + smDetailAborted, + agNULL, + satIOContext->interruptContext); + } + + if ( oneDeviceData->satTmTaskTag != agNULL ) + { + SM_DBG1(("smsatProcessAbort: TM callback!!!\n")); +#ifdef REMOVED + /* TM completed */ + tdsmEventCB( smRoot, + smDeviceHandle, + smIntrEventTypeTaskManagement, + smTMOK, + oneDeviceData->satTmTaskTag); +#endif + /* + * Reset flag + */ + oneDeviceData->satTmTaskTag = agNULL; + } + + /* + * Check if we are in recovery mode and need to update the recovery flag + */ + if ((oneDeviceData->satDriveState == SAT_DEV_STATE_IN_RECOVERY ) && + (oneDeviceData->satPendingIO == 0 )) + { + oneDeviceData->satDriveState = SAT_DEV_STATE_NORMAL; + SM_DBG1(("smsatProcessAbort: STATE NORMAL.!!!\n")); + } + SM_DBG1(("smsatProcessAbort: satDriveState %d!!!\n", oneDeviceData->satDriveState)); + SM_DBG1(("smsatProcessAbort: satPendingIO %d satNCQMaxIO %d!!!\n", oneDeviceData->satPendingIO, oneDeviceData->satNCQMaxIO )); + SM_DBG1(("smsatProcessAbort: satPendingNCQIO %d satPendingNONNCQIO %d!!!\n", oneDeviceData->satPendingNCQIO, oneDeviceData->satPendingNONNCQIO)); + + return; +} + + +osGLOBAL void +smsatNonDataIOCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + bit32 interruptContext; + smSatIOContext_t *satIOContext; + smDeviceData_t *oneDeviceData; + + SM_DBG2(("smsatNonDataIOCB: start\n")); + SM_DBG5(("satNonDataIOCB: agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", + agIORequest, agIOStatus, agIOInfoLen)); + + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + oneDeviceData = satIOContext->pSatDevData; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + interruptContext = satIOContext->interruptContext; + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + + /* Process completion */ + if( (agIOStatus == OSSA_IO_SUCCESS) && (agIOInfoLen==0)) + { + + SM_DBG1(("satNonDataIOCB: *** ERROR*** agIORequest=%p agIOStatus=0x%x agIOInfoLen %d!!!\n", + agIORequest, agIOStatus, agIOInfoLen)); + + tdsmIOCompletedCB( smRoot, + smIORequestBody->smIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + interruptContext); + } + else + { + /* More checking needed, for non-data IO this should be the normal case */ + smsatProcessAbnormalCompletion( agRoot, + agIORequest, + agIOStatus, + agFirstDword, + agIOInfoLen, + agParam, + satIOContext); + } + return; +} + +osGLOBAL void +smsatInquiryCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + /* + In the process of Inquiry + Process SAT_IDENTIFY_DEVICE + */ +// tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; +// tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; +// tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; +// tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smIORequestBody_t *smOrgIORequestBody; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatInternalIo_t *satIntIo; +// satDeviceData_t *satDevData; + smDeviceData_t *oneDeviceData; + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; + smIORequest_t *smOrgIORequest; +#ifdef TD_DEBUG_ENABLE + agsaFisPioSetupHeader_t *satPIOSetupHeader = agNULL; + bit32 ataStatus = 0; + bit32 ataError; +#endif + smScsiInitiatorRequest_t *smScsiRequest; /* TD's smScsiXchg */ + smScsiInitiatorRequest_t *smOrgScsiRequest; /* OS's smScsiXchg */ + agsaSATAIdentifyData_t *pSATAIdData; + bit8 *pInquiry; + bit8 page = 0xFF; + bit16 *tmpptr,tmpptr_tmp; + bit32 x; + bit32 lenReceived = 0; + bit32 allocationLen = 0; + bit32 lenNeeded = 0; + bit8 dataBuffer[SATA_PAGE89_INQUIRY_SIZE] = {0}; + + + SM_DBG6(("smsatInquiryCB: start\n")); + SM_DBG6(("smsatInquiryCB: agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + smScsiRequest = satIOContext->smScsiXchg; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + + if (satIntIo == agNULL) + { + SM_DBG6(("smsatInquiryCB: External, OS generated\n")); + pSense = satIOContext->pSense; + scsiCmnd = satIOContext->pScsiCmnd; + satOrgIOContext = satIOContext; + smOrgIORequest = smIORequestBody->smIORequest; + } + else + { + SM_DBG6(("smsatInquiryCB: Internal, TD generated\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + SM_DBG1(("smsatInquiryCB: satOrgIOContext is NULL, wrong!!!\n")); + return; + } + else + { + SM_DBG6(("smsatInquiryCB: satOrgIOContext is NOT NULL\n")); + } + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + smOrgIORequest = (smIORequest_t *)smOrgIORequestBody->smIORequest; + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + + smOrgScsiRequest = satOrgIOContext->smScsiXchg; + pInquiry = dataBuffer; + + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + + SM_DBG3(("smsatInquiryCB: did %d\n", oneDeviceData->id)); + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatInquiryCB: agFirstDword is NULL when error, status %d!!!\n", agIOStatus)); + if (agIOStatus == OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY) + { + SM_DBG1(("smsatInquiryCB: OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY!!!\n")); + /* should NOT be retried */ + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOFailed, + smDetailNoLogin, + agNULL, + satOrgIOContext->interruptContext + ); + } + else + { + SM_DBG1(("smsatInquiryCB: NOT OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY!!!\n")); + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOFailed, + smDetailNoLogin, + agNULL, + satOrgIOContext->interruptContext + ); + } + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + if (agIOStatus == OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_BREAK || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_UNKNOWN_ERROR || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY + ) + { + SM_DBG1(("smsatInquiryCB: OSSA_IO_OPEN_CNX_ERROR!!!\n")); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOFailed, + smDetailNoLogin, + agNULL, + satOrgIOContext->interruptContext + ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + if ( agIOStatus != OSSA_IO_SUCCESS || + (agIOStatus == OSSA_IO_SUCCESS && agFirstDword != agNULL && agIOInfoLen != 0) + ) + { +#ifdef TD_DEBUG_ENABLE + /* only agsaFisPioSetup_t is expected */ + satPIOSetupHeader = (agsaFisPioSetupHeader_t *)&(agFirstDword->PioSetup); + ataStatus = satPIOSetupHeader->status; /* ATA Status register */ + ataError = satPIOSetupHeader->error; /* ATA Eror register */ +#endif + SM_DBG1(("smsatInquiryCB: ataStatus 0x%x ataError 0x%x!!!\n", ataStatus, ataError)); + + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + smsatProcessAbort(smRoot, + smOrgIORequest, + satOrgIOContext + ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + /* success */ + + + /* Convert to host endian */ + tmpptr = (bit16*)(smScsiRequest->sglVirtualAddr); + for (x=0; x < sizeof(agsaSATAIdentifyData_t)/sizeof(bit16); x++) + { + OSSA_READ_LE_16(AGROOT, &tmpptr_tmp, tmpptr, 0); + *tmpptr = tmpptr_tmp; + tmpptr++; + /*Print tmpptr_tmp here for debugging purpose*/ + } + + pSATAIdData = (agsaSATAIdentifyData_t *)(smScsiRequest->sglVirtualAddr); + + SM_DBG5(("smsatInquiryCB: OS satOrgIOContext %p \n", satOrgIOContext)); + SM_DBG5(("smsatInquiryCB: TD satIOContext %p \n", satIOContext)); + SM_DBG5(("smsatInquiryCB: OS smScsiXchg %p \n", satOrgIOContext->smScsiXchg)); + SM_DBG5(("smsatInquiryCB: TD smScsiXchg %p \n", satIOContext->smScsiXchg)); + + /* copy ID Dev data to oneDeviceData */ + oneDeviceData->satIdentifyData = *pSATAIdData; + oneDeviceData->IDDeviceValid = agTRUE; +#ifdef SM_INTERNAL_DEBUG + smhexdump("smsatInquiryCB ID Dev data",(bit8 *)pSATAIdData, sizeof(agsaSATAIdentifyData_t)); + smhexdump("smsatInquiryCB Device ID Dev data",(bit8 *)&oneDeviceData->satIdentifyData, sizeof(agsaSATAIdentifyData_t)); +#endif +// smhexdump("smsatInquiryCB Device ID Dev data",(bit8 *)&oneDeviceData->satIdentifyData, sizeof(agsaSATAIdentifyData_t)); + + /* set oneDeviceData fields from IndentifyData */ + smsatSetDevInfo(oneDeviceData,pSATAIdData); + + allocationLen = ((scsiCmnd->cdb[3]) << 8) + scsiCmnd->cdb[4]; + allocationLen = MIN(allocationLen, scsiCmnd->expDataLength); + + /* SPC-4, spec 6.4 p 141 */ + /* EVPD bit == 0 */ + if (!(scsiCmnd->cdb[1] & SCSI_EVPD_MASK)) + { + /* Returns the standard INQUIRY data */ + lenNeeded = STANDARD_INQUIRY_SIZE; + + + smsatInquiryStandard(pInquiry, pSATAIdData, scsiCmnd); + //smhexdump("smsatInquiryCB ***standard***", (bit8 *)pInquiry, 36); + + } + else + { + /* EVPD bit != 0 && PAGE CODE != 0 */ + /* returns the pages of vital product data information */ + + /* we must support page 00h, 83h and 89h */ + page = scsiCmnd->cdb[2]; + if ((page != INQUIRY_SUPPORTED_VPD_PAGE) && + (page != INQUIRY_DEVICE_IDENTIFICATION_VPD_PAGE) && + (page != INQUIRY_ATA_INFORMATION_VPD_PAGE) && + (page != INQUIRY_BLOCK_DEVICE_CHARACTERISTICS_VPD_PAGE)) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + SM_DBG1(("smsatInquiryCB: invalid PAGE CODE 0x%x!!!\n", page)); + return; + } + + /* checking length */ + switch (page) + { + case INQUIRY_SUPPORTED_VPD_PAGE: + lenNeeded = SATA_PAGE0_INQUIRY_SIZE; /* 9 */ + break; + case INQUIRY_DEVICE_IDENTIFICATION_VPD_PAGE: + if (oneDeviceData->satWWNSupport) + { + lenNeeded = SATA_PAGE83_INQUIRY_WWN_SIZE; /* 16 */ + } + else + { + lenNeeded = SATA_PAGE83_INQUIRY_NO_WWN_SIZE; /* 76 */ + } + break; + case INQUIRY_ATA_INFORMATION_VPD_PAGE: + lenNeeded = SATA_PAGE89_INQUIRY_SIZE; /* 572 */ + break; + case INQUIRY_BLOCK_DEVICE_CHARACTERISTICS_VPD_PAGE: + lenNeeded = SATA_PAGEB1_INQUIRY_SIZE; /* 64 */ + break; + default: + SM_DBG1(("smsatInquiryCB: wrong!!! invalid PAGE CODE 0x%x!!!\n", page)); + break; + } + + + /* + * Fill in the Inquiry data depending on what Inquiry data we are returning. + */ + switch (page) + { + case INQUIRY_SUPPORTED_VPD_PAGE: + smsatInquiryPage0(pInquiry, pSATAIdData); + break; + case INQUIRY_DEVICE_IDENTIFICATION_VPD_PAGE: + smsatInquiryPage83(pInquiry, pSATAIdData, oneDeviceData); + break; + case INQUIRY_ATA_INFORMATION_VPD_PAGE: + smsatInquiryPage89(pInquiry, pSATAIdData, oneDeviceData, lenReceived); + break; + case INQUIRY_BLOCK_DEVICE_CHARACTERISTICS_VPD_PAGE: + smsatInquiryPageB1(pInquiry, pSATAIdData); + break; + default: + SM_DBG1(("smsatInquiryCB: wrong!!! invalidinvalid PAGE CODE 0x%x!!!\n", page)); + break; + } + } /* else */ + + SM_DBG6(("smsatInquiryCB: calling tdsmIOCompletedCB\n")); + + /* if this is a standard Inquiry command, notify Stoport to set the device queue depth to max NCQ */ + if ( (oneDeviceData->satNCQ == agTRUE) && + ((scsiCmnd->cdb[1] & 0x01) == 0)) + { + if (tdsmSetDeviceQueueDepth(smRoot, + smOrgIORequest, + oneDeviceData->satNCQMaxIO-1 + ) == agFALSE) + { + SM_DBG1(("smsatInquiryCB: failed to call tdsmSetDeviceQueueDepth()!!! Q=%d\n", oneDeviceData->satNCQMaxIO)); + } + } + + sm_memcpy(smOrgScsiRequest->sglVirtualAddr, dataBuffer, MIN(allocationLen, lenNeeded)); + if (allocationLen > lenNeeded) + { + SM_DBG6(("smsatInquiryCB reporting underrun lenNeeded=0x%x allocationLen=0x%x smIORequest=%p\n", + lenNeeded, allocationLen, smOrgIORequest)); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOUnderRun, + allocationLen - lenNeeded, + agNULL, + satOrgIOContext->interruptContext ); + } + else + { + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext); + } + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + SM_DBG5(("smsatInquiryCB: device %p pending IO %d\n", oneDeviceData, oneDeviceData->satPendingIO)); + SM_DBG6(("smsatInquiryCB: end\n")); + return; +} + +osGLOBAL void +smsatInquiryIntCB( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + smScsiRspSense_t *pSense; + smIniScsiCmnd_t *scsiCmnd; +// satDeviceData_t *satDevData; + smDeviceData_t *oneDeviceData; + agsaSATAIdentifyData_t *pSATAIdData; + + bit8 *pInquiry; + bit8 page = 0xFF; + bit32 lenReceived = 0; + bit32 allocationLen = 0; + bit32 lenNeeded = 0; + bit8 dataBuffer[SATA_PAGE89_INQUIRY_SIZE] = {0}; + + SM_DBG6(("smsatInquiryIntCB: start\n")); + + pSense = satIOContext->pSense; + scsiCmnd = &smScsiRequest->scsiCmnd; + pInquiry = dataBuffer; + oneDeviceData = satIOContext->pSatDevData; + pSATAIdData = &oneDeviceData->satIdentifyData; + + allocationLen = ((scsiCmnd->cdb[3]) << 8) + scsiCmnd->cdb[4]; + allocationLen = MIN(allocationLen, scsiCmnd->expDataLength); + + /* SPC-4, spec 6.4 p 141 */ + /* EVPD bit == 0 */ + if (!(scsiCmnd->cdb[1] & SCSI_EVPD_MASK)) + { + /* Returns the standard INQUIRY data */ + lenNeeded = STANDARD_INQUIRY_SIZE; + + smsatInquiryStandard(pInquiry, pSATAIdData, scsiCmnd); + //smhexdump("satInquiryIntCB ***standard***", (bit8 *)pInquiry, 36); + + } + else + { + /* EVPD bit != 0 && PAGE CODE != 0 */ + /* returns the pages of vital product data information */ + + /* we must support page 00h, 83h and 89h */ + page = scsiCmnd->cdb[2]; + if ((page != INQUIRY_SUPPORTED_VPD_PAGE) && + (page != INQUIRY_DEVICE_IDENTIFICATION_VPD_PAGE) && + (page != INQUIRY_ATA_INFORMATION_VPD_PAGE) && + (page != INQUIRY_UNIT_SERIAL_NUMBER_VPD_PAGE) && + (page != INQUIRY_BLOCK_DEVICE_CHARACTERISTICS_VPD_PAGE)) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satIOContext->interruptContext ); + + SM_DBG1(("smsatInquiryIntCB: invalid PAGE CODE 0x%x!!!\n", page)); + return; + } + + /* checking length */ + switch (page) + { + case INQUIRY_SUPPORTED_VPD_PAGE: + lenNeeded = SATA_PAGE0_INQUIRY_SIZE; /* 36 */ + break; + case INQUIRY_DEVICE_IDENTIFICATION_VPD_PAGE: + if (oneDeviceData->satWWNSupport) + { + lenNeeded = SATA_PAGE83_INQUIRY_WWN_SIZE; /* 16 */ + } + else + { + lenNeeded = SATA_PAGE83_INQUIRY_NO_WWN_SIZE; /* 76 */ + } + break; + case INQUIRY_ATA_INFORMATION_VPD_PAGE: + lenNeeded = SATA_PAGE89_INQUIRY_SIZE; /* 572 */ + break; + case INQUIRY_UNIT_SERIAL_NUMBER_VPD_PAGE: + lenNeeded = SATA_PAGE80_INQUIRY_SIZE; /* 24 */ + break; + case INQUIRY_BLOCK_DEVICE_CHARACTERISTICS_VPD_PAGE: + lenNeeded = SATA_PAGEB1_INQUIRY_SIZE; /* 64 */ + break; + default: + SM_DBG1(("smsatInquiryIntCB: wrong!!! invalidinvalid PAGE CODE 0x%x!!!\n", page)); + break; + } + + + /* + * Fill in the Inquiry data depending on what Inquiry data we are returning. + */ + switch (page) + { + case INQUIRY_SUPPORTED_VPD_PAGE: + smsatInquiryPage0(pInquiry, pSATAIdData); + break; + case INQUIRY_DEVICE_IDENTIFICATION_VPD_PAGE: + smsatInquiryPage83(pInquiry, pSATAIdData, oneDeviceData); + break; + case INQUIRY_ATA_INFORMATION_VPD_PAGE: + smsatInquiryPage89(pInquiry, pSATAIdData, oneDeviceData, lenReceived); + break; + case INQUIRY_UNIT_SERIAL_NUMBER_VPD_PAGE: + smsatInquiryPage80(pInquiry, pSATAIdData); + break; + case INQUIRY_BLOCK_DEVICE_CHARACTERISTICS_VPD_PAGE: + smsatInquiryPageB1(pInquiry, pSATAIdData); + break; + default: + SM_DBG1(("smsatInquiryIntCB: wrong!!! invalidinvalid PAGE CODE 0x%x!!!\n", page)); + break; + } + } /* else */ + + SM_DBG6(("smsatInquiryIntCB: calling tdsmIOCompletedCB\n")); + + /* if this is a standard Inquiry command, notify Stoport to set the device queue depth to max NCQ */ + if ( (oneDeviceData->satNCQ == agTRUE) && + ((scsiCmnd->cdb[1] & 0x01) == 0)) + { + if (tdsmSetDeviceQueueDepth(smRoot, + smIORequest, + oneDeviceData->satNCQMaxIO-1 + ) == agFALSE) + { + SM_DBG1(("smsatInquiryIntCB: failed to call tdsmSetDeviceQueueDepth()!!! Q=%d\n", oneDeviceData->satNCQMaxIO)); + } + } + + sm_memcpy(smScsiRequest->sglVirtualAddr, dataBuffer, MIN(allocationLen, lenNeeded)); + if (allocationLen > lenNeeded) + { + SM_DBG6(("smsatInquiryIntCB reporting underrun lenNeeded=0x%x allocationLen=0x%x smIORequest=%p\n", + lenNeeded, allocationLen, smIORequest)); + + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOUnderRun, + allocationLen - lenNeeded, + agNULL, + satIOContext->interruptContext ); + } + else + { + tdsmIOCompletedCB( smRoot, + smIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + } + + SM_DBG5(("smsatInquiryIntCB: device %p pending IO %d\n", oneDeviceData, oneDeviceData->satPendingIO)); + SM_DBG6(("smsatInquiryIntCB: end\n")); + return; + +} + +osGLOBAL void +smsatVerify10CB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smIORequestBody_t *smOrgIORequestBody; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatInternalIo_t *satIntIo; + smDeviceData_t *oneDeviceData; + + smScsiRspSense_t *pSense; + smIORequest_t *smOrgIORequest; + + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + + SM_DBG5(("smsatVerify10CB: start\n")); + SM_DBG5(("smsatVerify10CB: agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate smIOContext */ + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + + if (satIntIo == agNULL) + { + SM_DBG4(("smsatVerify10CB: External smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + smOrgIORequest = smIORequestBody->smIORequest; + pSense = satIOContext->pSense; + } + else + { + SM_DBG4(("smsatVerify10CB: Internal smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + SM_DBG4(("smsatVerify10CB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + SM_DBG4(("smsatVerify10CB: satOrgIOContext is NOT NULL\n")); + } + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + smOrgIORequest = (smIORequest_t *)smOrgIORequestBody->smIORequest; + pSense = satOrgIOContext->pSense; + } + + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatVerify10CB: wrong. agFirstDword is NULL when error, status %d!!!\n", agIOStatus)); + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* only agsaFisRegDeviceToHost_t is expected */ + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + } + + if( agIOStatus != OSSA_IO_SUCCESS) + { + if ( (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) || + ((ataStatus & ERR_ATA_STATUS_MASK) || (ataStatus & DF_ATA_STATUS_MASK)) + ) + { + /* for debugging */ + if( agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatVerify10CB: FAILED, NOT IO_SUCCESS!!!\n")); + } + else if (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) + { + SM_DBG1(("smsatVerify10CB: FAILED, Wrong FIS type 0x%x!!!\n",statDevToHostFisHeader->fisType)); + } + else if ( (ataStatus & ERR_ATA_STATUS_MASK) || + (ataStatus & DF_ATA_STATUS_MASK) + ) + { + SM_DBG1(("smsatVerify10CB: FAILED, FAILED, error status!!!\n")); + } + + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + smsatProcessAbort(smRoot, + smOrgIORequest, + satOrgIOContext + ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + /* for debugging */ + switch (hostToDevFis->h.command) + { + case SAT_READ_VERIFY_SECTORS_EXT: + SM_DBG1(("smsatVerify10CB: SAT_READ_VERIFY_SECTORS_EXT!!!\n")); + break; + default: + SM_DBG1(("smsatVerify10CB: error default case command 0x%x!!!\n", hostToDevFis->h.command)); + break; + } + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } /* end error checking */ + } + + /* process success from this point on */ + switch (hostToDevFis->h.command) + { + case SAT_READ_VERIFY_SECTORS_EXT: + SM_DBG5(("smsatVerify10CB: SAT_WRITE_DMA_EXT success \n")); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext); + break; + default: + SM_DBG1(("smsatVerify10CB: success but error default case command 0x%x!!!\n", hostToDevFis->h.command)); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + smsatSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, /* == &satIntIo->satOrgSmIORequest */ + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + break; + } + + return; +} + +osGLOBAL void +smsatReadLogExtCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smSatIOContext_t *satReadLogExtIOContext; + smSatIOContext_t *satIOContext; + smSatInternalIo_t *satIntIo; + smDeviceData_t *oneDeviceData; + agsaIORequest_t *agAbortIORequest; + smIORequestBody_t *smAbortIORequestBody; + bit32 PhysUpper32; + bit32 PhysLower32; + bit32 memAllocStatus; + void *osMemHandle; + smDeviceHandle_t *smDeviceHandle; + + SM_DBG5(("smsatReadLogExtCB: start\n")); + SM_DBG1(("smsatReadLogExtCB: agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", + agIORequest, agIOStatus, agIOInfoLen)); + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satReadLogExtIOContext = (smSatIOContext_t *) ioContext; + satIntIo = satReadLogExtIOContext->satIntIoContext; + oneDeviceData = satReadLogExtIOContext->pSatDevData; + smDeviceHandle = satReadLogExtIOContext->psmDeviceHandle; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + SM_DBG1(("smsatReadLogExtCB: did %d!!!\n", oneDeviceData->id)); + SM_DBG1(("smsatReadLogExtCB: smIORequestBody ID %d!!!\n", smIORequestBody->id)); + SM_DBG1(("smsatReadLogExtCB: smIORequestBody ioCompleted %d ioStarted %d\n", smIORequestBody->ioCompleted, smIORequestBody->ioStarted)); + smsatDecrementPendingIO(smRoot, smAllShared, satReadLogExtIOContext); + + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + + /* + * If READ LOG EXT failed, we issue device reset. + */ + if ( agIOStatus != OSSA_IO_SUCCESS || + (agIOStatus == OSSA_IO_SUCCESS && agFirstDword != agNULL && agIOInfoLen != 0) + ) + { + SM_DBG1(("smsatReadLogExtCB: FAILED.!!!\n")); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + /* Abort I/O after completion of device reset */ + oneDeviceData->satAbortAfterReset = agTRUE; +#ifdef NOT_YET + /* needs to investigate this case */ + /* no report to OS layer */ + satSubTM(smRoot, + satReadLogExtIOContext->ptiDeviceHandle, + TD_INTERNAL_TM_RESET, + agNULL, + agNULL, + agNULL, + agFALSE); +#endif + return; + } + + + /*************************************************************************** + * The following steps take place when READ LOG EXT successfully completed. + ***************************************************************************/ + + /************************************************************************ + * + * 1. Issue abort to LL layer to all other pending I/Os for the same SATA + * drive. + * + * 2. Free resource allocated for the internally generated READ LOG EXT. + * + * 3. At the completion of abort, in the context of ossaSATACompleted(), + * return the I/O with error status to the OS-App Specific layer. + * When all I/O aborts are completed, clear SATA device flag to + * indicate ready to process new request. + * + ***********************************************************************/ + + /* + * Issue abort to LL layer to all other pending I/Os for the same SATA drive + */ + /* + replace the single IO abort with device abort + */ + + SM_DBG1(("smsatReadLogExtCB: issuing saSATAAbort. Device Abort!!!\n")); + oneDeviceData->SMAbortAll = agTRUE; + /* + smAbortIORequestBody = smDequeueIO(smRoot); + + if (smAbortIORequestBody == agNULL) + { + SM_DBG1(("smsatReadLogExtCB: empty freeIOList!!!\n")); + return; + } + */ + /* allocating agIORequest for abort itself */ + memAllocStatus = tdsmAllocMemory( + smRoot, + &osMemHandle, + (void **)&smAbortIORequestBody, + &PhysUpper32, + &PhysLower32, + 8, + sizeof(smIORequestBody_t), + agTRUE + ); + + if (memAllocStatus != tiSuccess) + { + /* let os process IO */ + SM_DBG1(("smsatReadLogExtCB: ostiAllocMemory failed...\n")); + return; + } + + if (smAbortIORequestBody == agNULL) + { + /* let os process IO */ + SM_DBG1(("smsatReadLogExtCB: ostiAllocMemory returned NULL smAbortIORequestBody\n")); + return; + } + smIOReInit(smRoot, smAbortIORequestBody); + /* setup task management structure */ + smAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle = osMemHandle; + smAbortIORequestBody->smDevHandle = smDeviceHandle; + /* setup task management structure */ +// smAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle = osMemHandle; + satIOContext = &(smAbortIORequestBody->transport.SATA.satIOContext); + satIOContext->smRequestBody = smAbortIORequestBody; + + /* initialize agIORequest */ + agAbortIORequest = &(smAbortIORequestBody->agIORequest); + agAbortIORequest->osData = (void *) smAbortIORequestBody; + agAbortIORequest->sdkData = agNULL; /* LL takes care of this */ + + /* + * Issue abort (device abort all) + */ + saSATAAbort( agRoot, agAbortIORequest, tdsmRotateQnumber(smRoot, smDeviceHandle), oneDeviceData->agDevHandle, 1, agNULL, smaSATAAbortCB); + + /* + * Free resource allocated for the internally generated READ LOG EXT. + */ + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + /* + * Sequence of recovery continue at some other context: + * At the completion of abort, in the context of ossaSATACompleted(), + * return the I/O with error status to the OS-App Specific layer. + * When all I/O aborts are completed, clear SATA device flag to + * indicate ready to process new request. + */ + + oneDeviceData->satDriveState = SAT_DEV_STATE_NORMAL; + + SM_DBG1(("smsatReadLogExtCB: end return!!!\n")); + return; +} + +osGLOBAL void +ossaSATAEvent( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + agsaPortContext_t *agPortContext, + agsaDevHandle_t *agDevHandle, + bit32 event, + bit32 agIOInfoLen, + void *agParam + ) +{ + smRoot_t *smRoot = gsmRoot; + smIntRoot_t *smIntRoot = (smIntRoot_t *)smRoot->smData; + smIntContext_t *smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + smDeviceHandle_t *smDeviceHandle = agNULL; + smDeviceData_t *oneDeviceData = agNULL; + smList_t *DeviceListList; + bit32 found = agFALSE; + smIORequestBody_t *smIORequestBody = agNULL; + smSatInternalIo_t *satIntIo = agNULL; + smSatIOContext_t *satIOContext2; + smIORequest_t smIORequestTMP; + bit32 status; +#ifdef REMOVED + agsaDifDetails_t agDifDetails; + bit8 framePayload[256]; + bit16 frameOffset = 0; + bit16 frameLen = 0; +#endif + + SM_DBG1(("ossaSATAEvent: start\n")); + if (event == OSSA_IO_XFER_ERROR_ABORTED_NCQ_MODE) + { + /* agIORequest is invalid, search for smDeviceHandle from smAllShared using agDevHandle */ + /* find a device's existence */ + DeviceListList = smAllShared->MainDeviceList.flink; + while (DeviceListList != &(smAllShared->MainDeviceList)) + { + oneDeviceData = SMLIST_OBJECT_BASE(smDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + SM_DBG1(("ossaSATAEvent: oneDeviceData is NULL!!!\n")); + return; + } + if (oneDeviceData->agDevHandle == agDevHandle) + { + SM_DBG2(("ossaSATAEvent: did %d\n", oneDeviceData->id)); + found = agTRUE; + break; + } + DeviceListList = DeviceListList->flink; + } + if (found == agFALSE) + { + SM_DBG2(("ossaSATAEvent: not found!!!\n")); + return; + } + if (oneDeviceData->valid == agFALSE) + { + SM_DBG2(("ossaSATAEvent: oneDeviceData is not valid did %d!!!\n", oneDeviceData->id)); + return; + } + /************************************************************************** + * + * !!!! See Section 13.5.2.4 of SATA 2.5 specs. !!!! + * !!!! If the NCQ error ends up here, it means that the device sent !!!! + * !!!! Register Device To Host FIS (which does not have SActive !!!! + * !!!! register) instead of Set Device Bit FIS (which has SActive !!!! + * !!!! register). The routine osSatIOCompleted() deals with the case !!!! + * !!!! where Set Device Bit FIS was sent by the device. !!!! + * + * For NCQ we need to issue READ LOG EXT command with log page 10h + * to get the error and to allow other I/Os to continue. + * + * Here is the basic flow or sequence of error recovery, this sequence is + * similar to the one described in SATA 2.5: + * + * 1. Set SATA device flag to indicate error condition and returning busy + * for all new request. + * + * 2. Prepare READ LOG EXT page 10h command. Set flag to indicate that + * the failed I/O has NOT been returned to the OS Layer. Send command. + * + * 3. When the device receives READ LOG EXT page 10h request all other + * pending I/O are implicitly aborted. No completion (aborted) status + * will be sent to the host for these aborted commands. + * + * 4. SATL receives the completion for READ LOG EXT command in + * smsatReadLogExtCB(). Steps 5,6,7,8 below are the step 1,2,3,4 in + * smsatReadLogExtCB(). + * + * 5. Check flag that indicates whether the failed I/O has been returned + * to the OS Layer. If not, search the I/O context in device data + * looking for a matched tag. Then return the completion of the failed + * NCQ command with the appopriate/trasnlated SCSI status. + * + * 6. Issue abort to LL layer to all other pending I/Os for the same SATA + * drive. + * + * 7. Free resource allocated for the internally generated READ LOG EXT. + * + * 8. At the completion of abort, in the context of ossaSATACompleted(), + * return the I/O with error status to the OS-App Specific layer. + * When all I/O aborts are completed, clear SATA device flag to + * indicate ready to process new request. + * + *************************************************************************/ + + smDeviceHandle = oneDeviceData->smDevHandle; + SM_DBG1(("ossaSATAEvent: did %d!!!\n", oneDeviceData->id)); + + if (oneDeviceData->satDriveState == SAT_DEV_STATE_NORMAL) + { + SM_DBG1(("ossaSATAEvent: NCQ ERROR did %d!!!\n", oneDeviceData->id )); + + /* Set flag to indicate we are in recovery */ + oneDeviceData->satDriveState = SAT_DEV_STATE_IN_RECOVERY; + + /* + * Allocate resource for READ LOG EXIT page 10h + */ + satIntIo = smsatAllocIntIoResource( smRoot, + &(smIORequestTMP), /* anything but NULL */ + oneDeviceData, + sizeof (satReadLogExtPage10h_t), + satIntIo); + + /* + * If we cannot allocate resource to do the normal NCQ recovery, we + * will do SATA device reset. + */ + if (satIntIo == agNULL) + { + /* Abort I/O after completion of device reset */ + oneDeviceData->satAbortAfterReset = agTRUE; + SM_DBG1(("ossaSATAEvent: can't send RLE due to resource lack!!!\n")); + +#ifdef NOT_YET + /* needs to investigate this case */ + /* no report to OS layer */ + smsatSubTM(smRoot, + smDeviceHandle, + TD_INTERNAL_TM_RESET, + agNULL, + agNULL, + agNULL, + agFALSE); +#endif + + return; + } + + + /* + * Clear flag to indicate that the failed I/O has NOT been returned to the + * OS-App specific Layer. + */ + satIntIo->satIntFlag = 0; + + /* compare to satPrepareNewIO() */ + /* Send READ LOG EXIT page 10h command */ + + /* + * Need to initialize all the fields within satIOContext except + * reqType and satCompleteCB which will be set depending on cmd. + */ + + smIORequestBody = (smIORequestBody_t *)satIntIo->satIntRequestBody; + satIOContext2 = &(smIORequestBody->transport.SATA.satIOContext); + + satIOContext2->pSatDevData = oneDeviceData; + satIOContext2->pFis = &(smIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev); + satIOContext2->pScsiCmnd = &(satIntIo->satIntSmScsiXchg.scsiCmnd); + satIOContext2->pSense = &(smIORequestBody->transport.SATA.sensePayload); + satIOContext2->pSmSenseData = &(smIORequestBody->transport.SATA.smSenseData); + satIOContext2->pSmSenseData->senseData = satIOContext2->pSense; + + satIOContext2->smRequestBody = satIntIo->satIntRequestBody; + //not used +// satIOContext2->interruptContext = interruptContext; + satIOContext2->satIntIoContext = satIntIo; + + satIOContext2->psmDeviceHandle = smDeviceHandle; + satIOContext2->satOrgIOContext = agNULL; + satIOContext2->smScsiXchg = agNULL; + + SM_DBG1(("ossaSATAEvent: smIORequestBody ID %d!!!\n", smIORequestBody->id)); + SM_DBG1(("ossaSATAEvent: smIORequestBody ioCompleted %d ioStarted %d\n", smIORequestBody->ioCompleted, smIORequestBody->ioStarted)); + status = smsatSendReadLogExt( smRoot, + &satIntIo->satIntSmIORequest, + smDeviceHandle, + &satIntIo->satIntSmScsiXchg, + satIOContext2); + + if (status != SM_RC_SUCCESS) + { + SM_DBG1(("ossaSATAEvent: can't send RLE due to LL api failure!!!\n")); + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + /* Abort I/O after completion of device reset */ + oneDeviceData->satAbortAfterReset = agTRUE; +#ifdef NOT_YET + /* needs to investigate this case */ + /* no report to OS layer */ + smsatSubTM(smRoot, + smDeviceHandle, + TD_INTERNAL_TM_RESET, + agNULL, + agNULL, + agNULL, + agFALSE); +#endif + + return; + } + } + else + { + SM_DBG1(("ossaSATAEvent: NCQ ERROR but recovery in progress!!!\n")); + } + } + else if (event == OSSA_IO_XFER_CMD_FRAME_ISSUED) + { + SM_DBG1(("ossaSATAEvent: OSSA_IO_XFER_CMD_FRAME_ISSUED\n")); + } + else if (event == OSSA_IO_XFER_PIO_SETUP_ERROR) + { + SM_DBG1(("ossaSATAEvent: OSSA_IO_XFER_PIO_SETUP_ERROR\n")); + } + else if (event == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED) + { + SM_DBG1(("ossaSATAEvent: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED\n")); + } + else if (event == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO) + { + SM_DBG1(("ossaSATAEvent: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO\n")); + } + else if (event == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST) + { + SM_DBG1(("ossaSATAEvent: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST\n")); + } + else if (event == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE) + { + SM_DBG1(("ossaSATAEvent: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE\n")); + } + else if (event == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED) + { + SM_DBG1(("ossaSATAEvent: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED\n")); + } + else if (event == OSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH) + { + SM_DBG1(("ossaSATAEvent: OSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH\n")); + } +#ifdef REMOVED + else if (event == OSSA_IO_XFR_ERROR_DIF_MISMATCH || event == OSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH || + event == OSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH || event == OSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH ) + { + SM_DBG1(("ossaSATAEvent: DIF related, event 0x%x\n", event)); + /* process DIF detail information */ + SM_DBG2(("ossaSATAEvent: agIOInfoLen %d\n", agIOInfoLen)); + if (agParam == agNULL) + { + SM_DBG2(("ossaSATAEvent: agParam is NULL!!!\n")); + return; + } + if (agIOInfoLen < sizeof(agsaDifDetails_t)) + { + SM_DBG2(("ossaSATAEvent: wrong agIOInfoLen!!! agIOInfoLen %d sizeof(agsaDifDetails_t) %d\n", agIOInfoLen, (int)sizeof(agsaDifDetails_t))); + return; + } + /* reads agsaDifDetails_t */ + saFrameReadBlock(agRoot, agParam, 0, &agDifDetails, sizeof(agsaDifDetails_t)); + frameOffset = (agDifDetails.ErrBoffsetEDataLen & 0xFFFF); + frameLen = (agDifDetails.ErrBoffsetEDataLen & 0xFFFF0000) >> 16; + + SM_DBG2(("ossaSATAEvent: UpperLBA 0x%08x LowerLBA 0x%08x\n", agDifDetails.UpperLBA, agDifDetails.LowerLBA)); + SM_DBG2(("ossaSATAEvent: SASAddrHI 0x%08x SASAddrLO 0x%08x\n", + SM_GET_SAS_ADDRESSHI(agDifDetails.sasAddressHi), SM_GET_SAS_ADDRESSLO(agDifDetails.sasAddressLo))); + SM_DBG2(("ossaSATAEvent: DIF error mask 0x%x Device ID 0x%x\n", + (agDifDetails.DIFErrDevID) & 0xFF, (agDifDetails.DIFErrDevID & 0xFFFF0000) >> 16)); + if (frameLen != 0 && frameLen <= 256) + { + saFrameReadBlock(agRoot, agParam, sizeof(agsaDifDetails_t), framePayload, frameLen); + smhexdump("ossaSATAEvent frame", framePayload, frameLen); + } + } +#endif + else if (event == OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY) + { + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + if (smIORequestBody == agNULL) + { + SM_DBG1(("ossaSATAEvent: smIORequestBody is NULL!!!\n")); + return; + } + smDeviceHandle = smIORequestBody->smDevHandle; + if (smDeviceHandle == agNULL) + { + SM_DBG1(("ossaSATAEvent: smDeviceHandle is NULL!!!\n")); + return; + } + oneDeviceData = (smDeviceData_t *)smDeviceHandle->smData; + if (oneDeviceData == agNULL) + { + SM_DBG1(("ossaSATAEvent: oneDeviceData is NULL!!!\n")); + return; + } + SM_DBG1(("ossaSATAEvent: ERROR event %d did=%d\n", event, oneDeviceData->id)); + + + if (smAllShared->FCA) + { + if (oneDeviceData->SMNumOfFCA <= 0) /* does SMP HARD RESET only upto one time */ + { + SM_DBG1(("ossaSATAEvent: OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY; sending HARD_RESET\n")); + oneDeviceData->SMNumOfFCA++; + smPhyControlSend(smRoot, + oneDeviceData, + SMP_PHY_CONTROL_HARD_RESET, + agNULL, + tdsmRotateQnumber(smRoot, smDeviceHandle) + ); + } + else + { + /* given up after one time of SMP HARD RESET; */ + SM_DBG1(("ossaSATAEvent: OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY; but giving up sending HARD_RESET!!!\n")); + } + } + } + else if (event == OSSA_IO_XFER_ERROR_NAK_RECEIVED) + { + SM_DBG1(("ossaSATAEvent: OSSA_IO_XFER_ERROR_NAK_RECEIVED\n")); + } + else if (event == OSSA_IO_XFER_ERROR_DMA_ACTIVATE_TIMEOUT) + { + SM_DBG1(("ossaSATAEvent: OSSA_IO_XFER_ERROR_DMA_ACTIVATE_TIMEOUT\n")); + } + else + { + SM_DBG1(("ossaSATAEvent: other event 0x%x\n", event)); + } + + return; +} + +osGLOBAL void +smSMPCompletedCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle + ) +{ + smSMPRequestBody_t *smSMPRequestBody = (smSMPRequestBody_t *) agIORequest->osData; + + SM_DBG2(("smSMPCompletedCB: start\n")); + + if (smSMPRequestBody == agNULL) + { + SM_DBG1(("smSMPCompletedCB: smSMPRequestBody is NULL!!!\n")); + return; + } + + if (smSMPRequestBody->SMPCompletionFunc == agNULL) + { + SM_DBG1(("smSMPCompletedCB: smSMPRequestBody->SMPCompletionFunc is NULL!!!\n")); + return; + } + + /* calling smSMPCompleted */ + smSMPRequestBody->SMPCompletionFunc( + agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agFrameHandle + ); + return; +} + +osGLOBAL void +smSMPCompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle + ) +{ + smRoot_t *smRoot = gsmRoot; + smSMPRequestBody_t *smSMPRequestBody = (smSMPRequestBody_t *) agIORequest->osData; + smDeviceData_t *oneDeviceData; + smDeviceHandle_t *smDeviceHandle; + smIORequest_t *CurrentTaskTag; + bit8 smpHeader[4]; + smSMPFrameHeader_t *smSMPFrameHeader; + agsaDevHandle_t *agDevHandle = agNULL; + + SM_DBG2(("smSMPCompleted: start\n")); + + if (smSMPRequestBody == agNULL) + { + SM_DBG1(("smSMPCompleted: smSMPRequestBody is NULL, wrong!!!\n")); + return; + } + + CurrentTaskTag = smSMPRequestBody->CurrentTaskTag; + oneDeviceData = smSMPRequestBody->smDeviceData; + smDeviceHandle = smSMPRequestBody->smDevHandle; + if (smDeviceHandle == agNULL) + { + SM_DBG2(("smSMPCompleted: smDeviceHandle is NULL, wrong!!!\n")); + return; + } + + if (oneDeviceData == agNULL) + { + SM_DBG2(("smSMPCompleted: oneDeviceData is NULL, wrong!!!\n")); + return; + } + agDevHandle = oneDeviceData->agExpDevHandle; + if (agIOStatus == OSSA_IO_SUCCESS) + { + saFrameReadBlock(agRoot, agFrameHandle, 0, smpHeader, 4); + smSMPFrameHeader = (smSMPFrameHeader_t *)smpHeader; + if (smSMPFrameHeader->smpFunction == SMP_PHY_CONTROL) + { + SM_DBG3(("smSMPCompleted: phy control\n")); + if (agIOInfoLen != 4 && + smSMPFrameHeader->smpFunctionResult == SMP_FUNCTION_ACCEPTED) /*zero length is expected */ + { + SM_DBG1(("smSMPCompleted: mismatch len agIOInfoLen 0x%x 0x%x!!!\n", agIOInfoLen, 4)); + tdsmFreeMemory( + smRoot, + smSMPRequestBody->osMemHandle, + sizeof(smSMPRequestBody_t) + ); + if (CurrentTaskTag != agNULL) + { + tdsmEventCB(smRoot, + smDeviceHandle, + smIntrEventTypeTaskManagement, + smTMFailed, + CurrentTaskTag); + } + + return; + } + smPhyControlRespRcvd(smRoot, + agRoot, + agIORequest, + oneDeviceData, + smSMPFrameHeader, + agFrameHandle, + CurrentTaskTag + ); + } + else + { + /* unknown SMP function */ + SM_DBG2(("smSMPCompleted: unknown smSMPFrameHeader %d!!!\n", smSMPFrameHeader->smpFunction)); + tdsmFreeMemory( + smRoot, + smSMPRequestBody->osMemHandle, + sizeof(smSMPRequestBody_t) + ); + if (CurrentTaskTag != agNULL) + { + tdsmEventCB(smRoot, + smDeviceHandle, + smIntrEventTypeTaskManagement, + smTMFailed, + CurrentTaskTag); + } + return; + } + } + else + { + SM_DBG2(("smSMPCompleted: failed agIOStatus %d!!!\n", agIOStatus)); + if (agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED || + agIOStatus == OSSA_IO_DS_NON_OPERATIONAL + ) + { + SM_DBG1(("smSMPCompleted: setting back to operational\n")); + if (agDevHandle != agNULL) + { + saSetDeviceState(agRoot, agNULL, tdsmRotateQnumber(smRoot, smDeviceHandle), agDevHandle, SA_DS_OPERATIONAL); + } + else + { + SM_DBG1(("smSMPCompleted: agDevHandle is NULL\n")); + } + } + tdsmFreeMemory( + smRoot, + smSMPRequestBody->osMemHandle, + sizeof(smSMPRequestBody_t) + ); + if (CurrentTaskTag != agNULL) + { + tdsmEventCB(smRoot, + smDeviceHandle, + smIntrEventTypeTaskManagement, + smTMFailed, + CurrentTaskTag); + } + return; + } + + tdsmFreeMemory( + smRoot, + smSMPRequestBody->osMemHandle, + sizeof(smSMPRequestBody_t) + ); + return; +} + +osGLOBAL void +smPhyControlRespRcvd( + smRoot_t *smRoot, + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + smDeviceData_t *oneDeviceData, /* sata disk */ + smSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle, + smIORequest_t *CurrentTaskTag + ) +{ + smDeviceData_t *TargetDeviceData = agNULL; + agsaDevHandle_t *agDevHandle = agNULL; + smSMPRequestBody_t *smSMPRequestBody; + smDeviceHandle_t *smDeviceHandle; + + SM_DBG2(("smPhyControlRespRcvd: start\n")); + + if (CurrentTaskTag == agNULL ) + { + SM_DBG1(("smPhyControlRespRcvd: CurrentTaskTag is NULL; allowed\n")); + return; + } + + smSMPRequestBody = (smSMPRequestBody_t *)CurrentTaskTag->smData; + if (smSMPRequestBody == agNULL) + { + SM_DBG1(("smPhyControlRespRcvd: smSMPRequestBody is NULL!!!\n")); + return; + } + + smDeviceHandle = smSMPRequestBody->smDevHandle; + if (smDeviceHandle == agNULL) + { + SM_DBG2(("smPhyControlRespRcvd: smDeviceHandle is NULL!!!\n")); + return; + } + + TargetDeviceData = smSMPRequestBody->smDeviceData; + if (oneDeviceData != TargetDeviceData) + { + SM_DBG1(("smPhyControlRespRcvd: oneDeviceData != TargetDeviceData!!!\n")); + return; + } + + agDevHandle = TargetDeviceData->agDevHandle; + + + if (frameHeader->smpFunctionResult == SMP_FUNCTION_ACCEPTED) + { + SM_DBG2(("smPhyControlRespRcvd: SMP success\n")); + SM_DBG1(("smPhyControlRespRcvd: callback to TD layer with success\n")); + TargetDeviceData->satDriveState = SAT_DEV_STATE_NORMAL; + saSetDeviceState(agRoot, agNULL, tdsmRotateQnumber(smRoot, smDeviceHandle), agDevHandle, SA_DS_OPERATIONAL); + + tdsmEventCB(smRoot, + smDeviceHandle, + smIntrEventTypeTaskManagement, + smTMOK, + CurrentTaskTag); + } + else + { + SM_DBG1(("smPhyControlRespRcvd: SMP failure; result %d!!!\n", frameHeader->smpFunctionResult)); + tdsmEventCB(smRoot, + smDeviceHandle, + smIntrEventTypeTaskManagement, + smTMFailed, + CurrentTaskTag); + } + return; +} + +osGLOBAL void +smsatCheckPowerModeCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ) +{ + /* callback for satDeResetDevice */ +// tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; +// tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; +// tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; +// tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatInternalIo_t *satIntIo; +// satDeviceData_t *satDevData; + smDeviceData_t *oneDeviceData; +#ifdef TD_DEBUG_ENABLE + bit32 ataStatus = 0; + bit32 ataError; + agsaFisPioSetupHeader_t *satPIOSetupHeader = agNULL; +#endif + bit32 AbortTM = agFALSE; + smDeviceHandle_t *smDeviceHandle; + + SM_DBG1(("smsatCheckPowerModeCB: start\n")); + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + smDeviceHandle = oneDeviceData->smDevHandle; + if (satIntIo == agNULL) + { + SM_DBG6(("smsatCheckPowerModeCB: External, OS generated\n")); + satOrgIOContext = satIOContext; + } + else + { + SM_DBG6(("smsatCheckPowerModeCB: Internal, TD generated\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + SM_DBG6(("smsatCheckPowerModeCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + SM_DBG6(("smsatCheckPowerModeCB: satOrgIOContext is NOT NULL\n")); + } + } + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatCheckPowerModeCB: wrong. agFirstDword is NULL when error, status %d!!!\n", agIOStatus)); + /* TM completed */ + tdsmEventCB( smRoot, + smDeviceHandle, + smIntrEventTypeTaskManagement, + smTMFailed, + oneDeviceData->satTmTaskTag); + + oneDeviceData->satTmTaskTag = agNULL; + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + if (agIOStatus == OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_BREAK || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_UNKNOWN_ERROR || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY + ) + { + SM_DBG1(("smsatCheckPowerModeCB: OSSA_IO_OPEN_CNX_ERROR!!!\n")); + /* TM completed */ + tdsmEventCB( smRoot, + smDeviceHandle, + smIntrEventTypeTaskManagement, + smTMFailed, + oneDeviceData->satTmTaskTag); + oneDeviceData->satTmTaskTag = agNULL; + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* only agsaFisPioSetup_t is expected */ +#ifdef TD_DEBUG_ENABLE + satPIOSetupHeader = (agsaFisPioSetupHeader_t *)&(agFirstDword->PioSetup); + ataStatus = satPIOSetupHeader->status; /* ATA Status register */ + ataError = satPIOSetupHeader->error; /* ATA Eror register */ +#endif + SM_DBG1(("smsatCheckPowerModeCB: ataStatus 0x%x ataError 0x%x!!!\n", ataStatus, ataError)); + /* TM completed */ + tdsmEventCB( smRoot, + smDeviceHandle, + smIntrEventTypeTaskManagement, + smTMFailed, + oneDeviceData->satTmTaskTag); + oneDeviceData->satTmTaskTag = agNULL; + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + /* success */ + SM_DBG1(("smsatCheckPowerModeCB: success!!!\n")); + SM_DBG1(("smsatCheckPowerModeCB: TMF %d!!!\n", satOrgIOContext->TMF)); + + if (satOrgIOContext->TMF == AG_ABORT_TASK) + { + AbortTM = agTRUE; + } + if (AbortTM == agTRUE) + { + SM_DBG1(("smsatCheckPowerModeCB: calling local satAbort!!!\n")); + smsatAbort(smRoot, agRoot, satOrgIOContext->satToBeAbortedIOContext); + } + oneDeviceData->satTmTaskTag = agNULL; + oneDeviceData->satDriveState = SAT_DEV_STATE_NORMAL; + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + SM_DBG1(("smsatCheckPowerModeCB: satPendingIO %d satNCQMaxIO %d!!!\n", oneDeviceData->satPendingIO, oneDeviceData->satNCQMaxIO )); + SM_DBG1(("smsatCheckPowerModeCB: satPendingNCQIO %d satPendingNONNCQIO %d!!!\n", oneDeviceData->satPendingNCQIO, oneDeviceData->satPendingNONNCQIO)); + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + /* TM completed */ + tdsmEventCB( smRoot, + smDeviceHandle, + smIntrEventTypeTaskManagement, + smTMOK, + oneDeviceData->satTmTaskTag); + SM_DBG5(("smsatCheckPowerModeCB: device %p pending IO %d\n", oneDeviceData, oneDeviceData->satPendingIO)); + SM_DBG2(("smsatCheckPowerModeCB: end\n")); + return; +} + +osGLOBAL void +smsatCheckPowerModePassCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ) + +{ + + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatInternalIo_t *satIntIo; + smIORequest_t *smOrgIORequest; + smIORequestBody_t *smOrgIORequestBody; +// satDeviceData_t *satDevData; + smDeviceData_t *oneDeviceData; +#ifdef TD_DEBUG_ENABLE + bit32 ataStatus = 0; + bit32 ataError; + agsaFisPioSetupHeader_t *satPIOSetupHeader = agNULL; +#endif + + smScsiRspSense_t *pSense; + bit8 bSenseKey = 0; + bit16 bSenseCodeInfo = 0; + + SM_DBG1(("smsatCheckPowerModePassCB: start\n")); + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + + if (satIntIo == agNULL) + { + SM_DBG6(("smsatCheckPowerModePassCB: External, OS generated\n")); + satOrgIOContext = satIOContext; + smOrgIORequest = smIORequestBody->smIORequest; + pSense = satOrgIOContext->pSense; + } + else + { + SM_DBG6(("smsatCheckPowerModePassCB: Internal, TD generated\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + smOrgIORequest = (smIORequest_t *)smOrgIORequestBody->smIORequest; + pSense = satOrgIOContext->pSense; + if (satOrgIOContext == agNULL) + { + SM_DBG6(("smsatCheckPowerModePassCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + SM_DBG6(("smsatCheckPowerModePassCB: satOrgIOContext is NOT NULL\n")); + } + } + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatCheckPowerModePassCB: wrong. agFirstDword is NULL when error, status %d!!!\n", agIOStatus)); + + tdsmIOCompletedCB( + smRoot, + smOrgIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + + } + + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* only agsaFisPioSetup_t is expected */ +#ifdef TD_DEBUG_ENABLE + satPIOSetupHeader = (agsaFisPioSetupHeader_t *)&(agFirstDword->PioSetup); + ataStatus = satPIOSetupHeader->status; /* ATA Status register */ + ataError = satPIOSetupHeader->error; /* ATA Eror register */ +#endif + SM_DBG1(("smsatCheckPowerModePassCB: ataStatus 0x%x ataError 0x%x!!!\n", ataStatus, ataError)); + + + if (agIOStatus == OSSA_IO_ABORTED) + { + smsatProcessAbort(smRoot, + smOrgIORequest, + satOrgIOContext + ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + smsatTranslateATAErrorsToSCSIErrors( + agFirstDword->D2H.status, + agFirstDword->D2H.error, + &bSenseKey, + &bSenseCodeInfo + ); + smsatSetSensePayload(pSense, bSenseKey, 0, bSenseCodeInfo, satOrgIOContext); + tdsmIOCompletedCB(smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + + } + /* success */ + SM_DBG1(("smsatCheckPowerModePassCB: success!!!\n")); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext); + + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + + return; +} + +osGLOBAL void +smsatIDDataPassCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ) +{ + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatInternalIo_t *satIntIo; + smIORequest_t *smOrgIORequest; + smIORequestBody_t *smOrgIORequestBody; +// satDeviceData_t *satDevData; + smDeviceData_t *oneDeviceData; +#ifdef TD_DEBUG_ENABLE + bit32 ataStatus = 0; + bit32 ataError; + agsaFisPioSetupHeader_t *satPIOSetupHeader = agNULL; +#endif + + smScsiRspSense_t *pSense; + bit8 bSenseKey = 0; + bit16 bSenseCodeInfo = 0; + + SM_DBG3(("smsatIDDataPassCB: start\n")); + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + + if (satIntIo == agNULL) + { + SM_DBG6(("smsatIDDataPassCB: External, OS generated\n")); + satOrgIOContext = satIOContext; + smOrgIORequest = smIORequestBody->smIORequest; + pSense = satOrgIOContext->pSense; + } + else + { + SM_DBG6(("smsatIDDataPassCB: Internal, TD generated\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + smOrgIORequest = (smIORequest_t *)smOrgIORequestBody->smIORequest; + pSense = satOrgIOContext->pSense; + if (satOrgIOContext == agNULL) + { + SM_DBG6(("smsatIDDataPassCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + SM_DBG6(("smsatIDDataPassCB: satOrgIOContext is NOT NULL\n")); + } + } + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatIDDataPassCB: wrong. agFirstDword is NULL when error, status %d!!!\n", agIOStatus)); + + tdsmIOCompletedCB( + smRoot, + smOrgIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + + } + + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* only agsaFisPioSetup_t is expected */ +#ifdef TD_DEBUG_ENABLE + satPIOSetupHeader = (agsaFisPioSetupHeader_t *)&(agFirstDword->PioSetup); + ataStatus = satPIOSetupHeader->status; /* ATA Status register */ + ataError = satPIOSetupHeader->error; /* ATA Eror register */ +#endif + SM_DBG1(("smsatIDDataPassCB: ataStatus 0x%x ataError 0x%x!!!\n", ataStatus, ataError)); + + + if (agIOStatus == OSSA_IO_ABORTED) + { + smsatProcessAbort(smRoot, + smOrgIORequest, + satOrgIOContext + ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + smsatTranslateATAErrorsToSCSIErrors( + agFirstDword->D2H.status, + agFirstDword->D2H.error, + &bSenseKey, + &bSenseCodeInfo + ); + smsatSetSensePayload(pSense, bSenseKey, 0, bSenseCodeInfo, satOrgIOContext); + tdsmIOCompletedCB(smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + + } + /* success */ + SM_DBG3(("smsatIDDataPassCB: success!!!\n")); + + SM_DBG3(("smsatIDDataPassCB: extend 0x%x ck_cond 0x%x sectorCnt07 0x%x\n", satOrgIOContext->extend, + satIOContext->ck_cond, satOrgIOContext->sectorCnt07)); + SM_DBG3(("smsatIDDataPassCB: LBAHigh07 0x%x LBAMid07 0x%x LBALow07 0x%x\n", satOrgIOContext->LBAHigh07, + satOrgIOContext->LBAMid07, satOrgIOContext->LBALow07)); + + if (satIOContext->ck_cond) + { + smsatSetSensePayload( pSense, + SCSI_SNSKEY_RECOVERED_ERROR, + satOrgIOContext->sectorCnt07, + SCSI_SNSCODE_ATA_PASS_THROUGH_INFORMATION_AVAILABLE, + satIOContext); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + } + else + { + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext); + } + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + + return; +} + +osGLOBAL void +smsatResetDeviceCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ) +{ + /* callback for satResetDevice */ +// tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; +// tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; +// tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; +// tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smIORequestBody_t *smOrgIORequestBody; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatIOContext_t *satNewIOContext; + smSatInternalIo_t *satIntIo; + smSatInternalIo_t *satNewIntIo = agNULL; +// satDeviceData_t *satDevData; + smDeviceData_t *oneDeviceData; + smIORequest_t *smOrgIORequest; +#ifdef TD_DEBUG_ENABLE + bit32 ataStatus = 0; + bit32 ataError; + agsaFisPioSetupHeader_t *satPIOSetupHeader = agNULL; +#endif + bit32 status; + smDeviceHandle_t *smDeviceHandle; + + SM_DBG1(("smsatResetDeviceCB: start\n")); + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + smDeviceHandle = oneDeviceData->smDevHandle; + + if (satIntIo == agNULL) + { + SM_DBG6(("smsatResetDeviceCB: External, OS generated\n")); + satOrgIOContext = satIOContext; + smOrgIORequest = smIORequestBody->smIORequest; + } + else + { + SM_DBG6(("smsatResetDeviceCB: Internal, TD generated\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + SM_DBG6(("smsatResetDeviceCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + SM_DBG6(("smsatResetDeviceCB: satOrgIOContext is NOT NULL\n")); + } + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + smOrgIORequest = (smIORequest_t *)smOrgIORequestBody->smIORequest; + } + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatResetDeviceCB: wrong. agFirstDword is NULL when error, status %d!!!\n", agIOStatus)); + /* TM completed */ + tdsmEventCB( smRoot, + smDeviceHandle, + smIntrEventTypeTaskManagement, + smTMFailed, + oneDeviceData->satTmTaskTag); + oneDeviceData->satTmTaskTag = agNULL; + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + if (agIOStatus == OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_BREAK || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_UNKNOWN_ERROR || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY + ) + { + SM_DBG1(("smsatResetDeviceCB: OSSA_IO_OPEN_CNX_ERROR!!!\n")); + /* TM completed */ + tdsmEventCB( smRoot, + smDeviceHandle, + smIntrEventTypeTaskManagement, + smTMFailed, + oneDeviceData->satTmTaskTag); + + oneDeviceData->satTmTaskTag = agNULL; + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* only agsaFisPioSetup_t is expected */ +#ifdef TD_DEBUG_ENABLE + satPIOSetupHeader = (agsaFisPioSetupHeader_t *)&(agFirstDword->PioSetup); + ataStatus = satPIOSetupHeader->status; /* ATA Status register */ + ataError = satPIOSetupHeader->error; /* ATA Eror register */ +#endif + SM_DBG1(("smsatResetDeviceCB: ataStatus 0x%x ataError 0x%x!!!\n", ataStatus, ataError)); + /* TM completed */ + tdsmEventCB( smRoot, + smDeviceHandle, + smIntrEventTypeTaskManagement, + smTMFailed, + oneDeviceData->satTmTaskTag); + + oneDeviceData->satTmTaskTag = agNULL; + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + /* success */ + satNewIntIo = smsatAllocIntIoResource( smRoot, + smOrgIORequest, + oneDeviceData, + 0, + satNewIntIo); + if (satNewIntIo == agNULL) + { + oneDeviceData->satTmTaskTag = agNULL; + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + /* memory allocation failure */ + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + /* TM completed */ + tdsmEventCB( smRoot, + smDeviceHandle, + smIntrEventTypeTaskManagement, + smTMFailed, + oneDeviceData->satTmTaskTag); + SM_DBG1(("smsatResetDeviceCB: momory allocation fails!!!\n")); + return; + } /* end of memory allocation failure */ + /* + * Need to initialize all the fields within satIOContext + */ + satNewIOContext = smsatPrepareNewIO( + satNewIntIo, + smOrgIORequest, + oneDeviceData, + agNULL, + satOrgIOContext + ); + /* send AGSA_SATA_PROTOCOL_SRST_DEASSERT */ + status = smsatDeResetDevice(smRoot, + smOrgIORequest, + satOrgIOContext->psmDeviceHandle, + agNULL, + satNewIOContext + ); + if (status != SM_RC_SUCCESS) + { + /* TM completed */ + tdsmEventCB( smRoot, + smDeviceHandle, + smIntrEventTypeTaskManagement, + smTMFailed, + oneDeviceData->satTmTaskTag); + /* sending AGSA_SATA_PROTOCOL_SRST_DEASSERT fails */ + oneDeviceData->satTmTaskTag = agNULL; + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satNewIntIo); + return; + } +// oneDeviceData->satTmTaskTag = agNULL; + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + SM_DBG5(("smsatResetDeviceCB: device %p pending IO %d\n", oneDeviceData, oneDeviceData->satPendingIO)); + SM_DBG6(("smsatResetDeviceCB: end\n")); + return; +} + +osGLOBAL void +smsatDeResetDeviceCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ) +{ + /* callback for satDeResetDevice */ +// tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; +// tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; +// tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; +// tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatInternalIo_t *satIntIo; +// satDeviceData_t *satDevData; + smDeviceData_t *oneDeviceData; +#ifdef TD_DEBUG_ENABLE + bit32 ataStatus = 0; + bit32 ataError; + agsaFisPioSetupHeader_t *satPIOSetupHeader = agNULL; +#endif + bit32 AbortTM = agFALSE; + smDeviceHandle_t *smDeviceHandle; + + SM_DBG1(("smsatDeResetDeviceCB: start!!!\n")); + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + smDeviceHandle = oneDeviceData->smDevHandle; + if (satIntIo == agNULL) + { + SM_DBG6(("smsatDeResetDeviceCB: External, OS generated\n")); + satOrgIOContext = satIOContext; + } + else + { + SM_DBG6(("smsatDeResetDeviceCB: Internal, TD generated\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + SM_DBG6(("smsatDeResetDeviceCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + SM_DBG6(("smsatDeResetDeviceCB: satOrgIOContext is NOT NULL\n")); + } + } + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatDeResetDeviceCB: wrong. agFirstDword is NULL when error, status %d!!!\n", agIOStatus)); + /* TM completed */ + tdsmEventCB( smRoot, + smDeviceHandle, + smIntrEventTypeTaskManagement, + smTMFailed, + oneDeviceData->satTmTaskTag); + oneDeviceData->satTmTaskTag = agNULL; + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + if (agIOStatus == OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_BREAK || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_UNKNOWN_ERROR || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY + ) + { + SM_DBG1(("smsatDeResetDeviceCB: OSSA_IO_OPEN_CNX_ERROR!!!\n")); + + /* TM completed */ + tdsmEventCB( smRoot, + smDeviceHandle, + smIntrEventTypeTaskManagement, + smTMFailed, + oneDeviceData->satTmTaskTag); + oneDeviceData->satTmTaskTag = agNULL; + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* only agsaFisPioSetup_t is expected */ +#ifdef TD_DEBUG_ENABLE + satPIOSetupHeader = (agsaFisPioSetupHeader_t *)&(agFirstDword->PioSetup); + ataStatus = satPIOSetupHeader->status; /* ATA Status register */ + ataError = satPIOSetupHeader->error; /* ATA Eror register */ +#endif + SM_DBG1(("smsatDeResetDeviceCB: ataStatus 0x%x ataError 0x%x!!!\n", ataStatus, ataError)); + /* TM completed */ + tdsmEventCB( smRoot, + smDeviceHandle, + smIntrEventTypeTaskManagement, + smTMFailed, + oneDeviceData->satTmTaskTag); + oneDeviceData->satTmTaskTag = agNULL; + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + /* success */ + SM_DBG1(("smsatDeResetDeviceCB: success !!!\n")); + SM_DBG1(("smsatDeResetDeviceCB: TMF %d!!!\n", satOrgIOContext->TMF)); + + if (satOrgIOContext->TMF == AG_ABORT_TASK) + { + AbortTM = agTRUE; + } + if (AbortTM == agTRUE) + { + SM_DBG1(("smsatDeResetDeviceCB: calling satAbort!!!\n")); + smsatAbort(smRoot, agRoot, satOrgIOContext->satToBeAbortedIOContext); + } + oneDeviceData->satTmTaskTag = agNULL; + oneDeviceData->satDriveState = SAT_DEV_STATE_NORMAL; + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + SM_DBG1(("smsatDeResetDeviceCB: satPendingIO %d satNCQMaxIO %d!!!\n", oneDeviceData->satPendingIO, oneDeviceData->satNCQMaxIO )); + SM_DBG1(("smsatDeResetDeviceCB: satPendingNCQIO %d satPendingNONNCQIO %d!!!\n", oneDeviceData->satPendingNCQIO, oneDeviceData->satPendingNONNCQIO)); + smsatFreeIntIoResource( smRoot, oneDeviceData, satIntIo ); + + /* TM completed */ + tdsmEventCB( smRoot, + smDeviceHandle, + smIntrEventTypeTaskManagement, + smTMOK, + oneDeviceData->satTmTaskTag); + SM_DBG5(("smsatDeResetDeviceCB: device %p pending IO %d\n", oneDeviceData, oneDeviceData->satPendingIO)); + SM_DBG6(("smsatDeResetDeviceCB: end\n")); + return; +} + +osGLOBAL void +smaSATAAbortCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 flag, + bit32 status + ) +{ + smRoot_t *smRoot = gsmRoot; + smIORequestBody_t *smIORequestBody = agNULL; + smSatIOContext_t *satIOContext; + smDeviceHandle_t *smDeviceHandle; + smDeviceData_t *oneDeviceData = agNULL; + + SM_DBG1(("smaSATAAbortCB: start\n")); + + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + if (smIORequestBody == agNULL) + { + SM_DBG1(("smaSATAAbortCB: smIORequestBody is NULL!!! \n")); + return; + } + + satIOContext = &(smIORequestBody->transport.SATA.satIOContext); + if (satIOContext == agNULL) + { + SM_DBG1(("smaSATAAbortCB: satIOContext is NULL!!! \n")); + if (smIORequestBody->IOType.InitiatorTMIO.osMemHandle != agNULL) + { + tdsmFreeMemory(smRoot, + smIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(smIORequestBody_t) + ); + } + return; + } + + smDeviceHandle = smIORequestBody->smDevHandle; + if (smDeviceHandle == agNULL) + { + SM_DBG1(("smaSATAAbortCB: smDeviceHandle is NULL!!!\n")); + if (smIORequestBody->IOType.InitiatorTMIO.osMemHandle != agNULL) + { + tdsmFreeMemory(smRoot, + smIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(smIORequestBody_t) + ); + } + return; + } + + oneDeviceData = (smDeviceData_t *)smDeviceHandle->smData; + if (oneDeviceData == agNULL) + { + SM_DBG1(("smaSATAAbortCB: oneDeviceData is NULL!!!\n")); + if (smIORequestBody->IOType.InitiatorTMIO.osMemHandle != agNULL) + { + tdsmFreeMemory(smRoot, + smIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(smIORequestBody_t) + ); + } + + return; + } + + if (flag == 2) + { + /* abort per port */ + SM_DBG1(("smaSATAAbortCB: abort per port, not yet!!!\n")); + } + else if (flag == 1) + { + SM_DBG1(("smaSATAAbortCB: abort all!!!\n")); + if (oneDeviceData->OSAbortAll == agTRUE) + { + oneDeviceData->OSAbortAll = agFALSE; +#if 0 + ostiInitiatorEvent( tiRoot, + agNULL, + tiDeviceHandle, + tiIntrEventTypeLocalAbort, + tiAbortOK, + agNULL); +#endif +#if 1 + tdsmEventCB( smRoot, + smDeviceHandle, + smIntrEventTypeLocalAbort, + smTMOK, + agNULL); +#endif + + } + if (smIORequestBody->IOType.InitiatorTMIO.osMemHandle != agNULL) + { + tdsmFreeMemory(smRoot, + smIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(smIORequestBody_t) + ); + } + } + else if (flag == 0) + { + SM_DBG1(("smaSATAAbortCB: abort one\n")); + if (status == OSSA_IO_SUCCESS) + { + SM_DBG1(("smaSATAAbortCB: OSSA_IO_SUCCESS\n")); + } + else if (status == OSSA_IO_NOT_VALID) + { + SM_DBG1(("smaSATAAbortCB: OSSA_IO_NOT_VALID\n")); + } + else if (status == OSSA_IO_NO_DEVICE) + { + SM_DBG1(("smaSATAAbortCB: OSSA_IO_NO_DEVICE\n")); + } + else if (status == OSSA_IO_ABORT_IN_PROGRESS) + { + SM_DBG1(("smaSATAAbortCB: OSSA_IO_ABORT_IN_PROGRESS\n")); + } +#ifdef REMOVED + else if (status == OSSA_IO_ABORT_DELAYED) + { + SM_DBG1(("smaSATAAbortCB: OSSA_IO_ABORT_DELAYED\n")); + } +#endif + else + { + SM_DBG1(("smaSATAAbortCB: unspecified status 0x%x\n", status )); + } + if (smIORequestBody->IOType.InitiatorTMIO.osMemHandle != agNULL) + { + tdsmFreeMemory(smRoot, + smIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(smIORequestBody_t) + ); + } + } + else + { + SM_DBG1(("smaSATAAbortCB: wrong flag %d\n", flag)); + } + + return; +} + +osGLOBAL void +smLocalPhyControlCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 phyId, + bit32 phyOperation, + bit32 status, + void *parm + ) +{ + smRoot_t *smRoot = gsmRoot; + smIORequestBody_t *smIORequestBody = agNULL; + smDeviceHandle_t *smDeviceHandle; + smDeviceData_t *oneDeviceData = agNULL; + smIORequest_t *currentTaskTag; + agsaDevHandle_t *agDevHandle = agNULL; + + SM_DBG1(("smLocalPhyControlCB: start phyId 0x%x phyOperation 0x%x status 0x%x\n",phyId,phyOperation,status)); + + if (agContext == agNULL) + { + SM_DBG1(("smLocalPhyControlCB: agContext is NULL!!!\n")); + return; + } + currentTaskTag = (smIORequest_t *)agContext->osData; + if (currentTaskTag == agNULL) + { + SM_DBG1(("smLocalPhyControlCB: currentTaskTag is NULL!!!\n")); + return; + } + smIORequestBody = (smIORequestBody_t *)currentTaskTag->smData; + if (smIORequestBody == agNULL) + { + SM_DBG1(("smLocalPhyControlCB: smIORequestBody is NULL!!!\n")); + return; + } + smDeviceHandle = smIORequestBody->smDevHandle; + if (smDeviceHandle == agNULL) + { + SM_DBG1(("smLocalPhyControlCB: smDeviceHandle is NULL!!!\n")); + return; + } + oneDeviceData = (smDeviceData_t *)smDeviceHandle->smData; + if (oneDeviceData == agNULL) + { + SM_DBG1(("smLocalPhyControlCB: oneDeviceData is NULL!!!\n")); + return; + } + switch (phyOperation) + { + case AGSA_PHY_LINK_RESET: /* fall through */ + case AGSA_PHY_HARD_RESET: + if (status == OSSA_SUCCESS) + { + SM_DBG2(("smLocalPhyControlCB: callback to TD layer with success\n")); + agDevHandle = oneDeviceData->agDevHandle; + SM_DBG2(("smLocalPhyControlCB: satPendingIO %d satNCQMaxIO %d\n", oneDeviceData->satPendingIO, oneDeviceData->satNCQMaxIO )); + SM_DBG1(("smLocalPhyControlCB: satPendingNCQIO %d satPendingNONNCQIO %d\n", oneDeviceData->satPendingNCQIO, oneDeviceData->satPendingNONNCQIO)); + oneDeviceData->satDriveState = SAT_DEV_STATE_NORMAL; +#ifdef REMOVED + saSetDeviceState(agRoot, + agNULL, + tdsmRotateQnumber(smRoot, smDeviceHandle), + agDevHandle, + SA_DS_OPERATIONAL + ); + /* TM completed */ + tdsmEventCB( smRoot, + smDeviceHandle, + smIntrEventTypeTaskManagement, + smTMOK, + currentTaskTag); +#endif + } + else + { + SM_DBG1(("smLocalPhyControlCB: callback to TD layer with failure!!!\n")); + /* TM completed */ + tdsmEventCB( smRoot, + smDeviceHandle, + smIntrEventTypeTaskManagement, + smTMFailed, + currentTaskTag); + } + break; + default: + SM_DBG1(("ossaLocalPhyControlCB: error default case. phyOperation is %d!!!\n", phyOperation)); + /* TM completed */ + tdsmEventCB( smRoot, + smDeviceHandle, + smIntrEventTypeTaskManagement, + smTMFailed, + currentTaskTag); + break; + } + return; +} + +osGLOBAL void +smsatSetFeaturesAACB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smIORequestBody_t *smOrgIORequestBody = agNULL; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatInternalIo_t *satIntIo; + smDeviceData_t *oneDeviceData; + smIORequest_t *smOrgIORequest; + smDeviceHandle_t *smDeviceHandle; + smIORequest_t *smIORequest; + bit32 ataStatus = 0; + bit32 ataError = 0; + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + + SM_DBG2(("smsatSetFeaturesAACB: start\n")); + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + if (satIOContext == agNULL) + { + SM_DBG1(("smsatSetFeaturesAACB: satIOContext is NULL\n")); + return; + } + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + smDeviceHandle = satIOContext->psmDeviceHandle; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + if (satIntIo == agNULL) + { + SM_DBG5(("smsatSetFeaturesAACB: External smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + smOrgIORequest = smIORequestBody->smIORequest; + smIORequest = smOrgIORequest; + } + else + { + SM_DBG5(("smsatSetFeaturesAACB: Internal smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + smOrgIORequest = (smIORequest_t *)smOrgIORequestBody->smIORequest; + } + smIORequest = smOrgIORequestBody->smIORequest; + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatSetFeaturesAACB: fail, case 1 agFirstDword is NULL when error, status %d!!!\n", agIOStatus)); + } + if (agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatSetFeaturesAACB: fail, case 2 status %d!!!\n", agIOStatus)); + } + if (agIOInfoLen != 0 && agIOStatus == OSSA_IO_SUCCESS) + { + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + ataError = statDevToHostFisHeader->error; /* ATA Eror register */ + if ((ataStatus & ERR_ATA_STATUS_MASK) || (ataStatus & DF_ATA_STATUS_MASK)) + { + SM_DBG1(("smsatSetFeaturesAACB: fail, case 3 ataStatus %d ataError %d!!!\n", ataStatus, ataError)); + } + if (ataError != 0) + { + SM_DBG1(("smsatSetFeaturesAACB: fail, case 4 ataStatus %d ataError %d!!!\n", ataStatus, ataError)); + } + } + /* interal structure free */ + smsatFreeIntIoResource(smRoot,oneDeviceData, satIntIo); + if (smIORequest->tdData == smIORequest->smData) + { + SM_DBG1(("smsatSetFeaturesAACB: the same tdData and smData error!\n")); + } + /*Complete this identify device IO */ + tdsmIDCompletedCB(smRoot, smIORequest, smDeviceHandle, smIOSuccess, &(oneDeviceData->satIdentifyData)); + SM_DBG2(("smsatSetFeaturesAACB: end\n")); +} + +/***************************************************************************** +*! \brief smsatSetFeaturesDMACB +* +* This routine is a callback function called from smllSATACompleted(). +* This CB routine deals with normal non-chained data I/O SATA request. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to smSatIOContext_t. +* +* \return: none +* +*****************************************************************************/ +osGLOBAL void +smsatSetFeaturesDMACB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smIORequestBody_t *smOrgIORequestBody = agNULL; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatIOContext_t *satNewIOContext; + smSatInternalIo_t *satIntIo; + smSatInternalIo_t *satNewIntIo = agNULL; + smDeviceData_t *oneDeviceData; + smIniScsiCmnd_t *scsiCmnd; + smIORequest_t *smOrgIORequest; + smDeviceHandle_t *smDeviceHandle; + bit32 status = SM_RC_FAILURE; + smIORequest_t *smIORequest; + + SM_DBG2(("smsatSetFeaturesDMACB: start\n")); + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + if (satIOContext == agNULL) + { + SM_DBG1(("smsatSetFeaturesDMACB: satIOContext is NULL\n")); + return; + } + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + smDeviceHandle = satIOContext->psmDeviceHandle; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + if (satIntIo == agNULL) + { + SM_DBG2(("smsatSetFeaturesDMACB: External smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + smOrgIORequest = smIORequestBody->smIORequest; + scsiCmnd = satIOContext->pScsiCmnd; + } + else + { + SM_DBG2(("smsatSetFeaturesDMACB: Internal smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + smOrgIORequest = (smIORequest_t *)smOrgIORequestBody->smIORequest; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + smIORequest = smOrgIORequestBody->smIORequest; + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + + oneDeviceData->satDMAEnabled = agTRUE; + /* interal structure free */ + smsatFreeIntIoResource(smRoot, + oneDeviceData, + satIntIo); + + if (smIORequest->tdData == smIORequest->smData) + { + SM_DBG1(("smsatSetFeaturesDMACB: the same tdData and smData error!\n")); + } + SM_DBG2(("smsatSetFeaturesDMACB: agIOStatus 0x%x\n", agIOStatus)); + /* check the agIOStatus */ + if (agIOStatus == OSSA_IO_ABORTED || + agIOStatus == OSSA_IO_NO_DEVICE || + agIOStatus == OSSA_IO_PORT_IN_RESET || + agIOStatus == OSSA_IO_DS_NON_OPERATIONAL || + agIOStatus == OSSA_IO_DS_IN_RECOVERY || + agIOStatus == OSSA_IO_DS_IN_ERROR || + agIOStatus == OSSA_IO_DS_INVALID + ) + { + SM_DBG1(("smsatSetFeaturesDMACB: error status 0x%x\n", agIOStatus)); + SM_DBG1(("smsatSetFeaturesDMACB: did %d!!!\n", oneDeviceData->id)); + tdsmIDCompletedCB(smRoot, smIORequest, smDeviceHandle, smIOSuccess, &(oneDeviceData->satIdentifyData)); + return; + } + if (oneDeviceData->satDeviceType == SATA_ATAPI_DEVICE) + { + /*if ATAPI device, only need to enable PIO and DMA transfer mode, then complete this identify device command */ + tdsmIDCompletedCB(smRoot, smIORequest, smDeviceHandle, smIOSuccess, &(oneDeviceData->satIdentifyData)); + return; + } + + /* enble read look-ahead feature*/ + if (oneDeviceData->satReadLookAheadSupport == agTRUE) + { + satNewIntIo = smsatAllocIntIoResource(smRoot, + smOrgIORequest, + oneDeviceData, + 0, + satNewIntIo); + if (satNewIntIo == agNULL) + { + SM_DBG1(("smsatSetFeaturesDMACB: memory allocation fails\n")); + /*Complete this identify packet device IO */ + tdsmIDCompletedCB(smRoot, smIORequest, smDeviceHandle, smIOSuccess, &(oneDeviceData->satIdentifyData)); + return; + } /* end memory allocation */ + + satNewIOContext = smsatPrepareNewIO(satNewIntIo, + smOrgIORequest, + oneDeviceData, + scsiCmnd, + satOrgIOContext + ); + /* sends SET FEATURES command to enable Read Look-Ahead */ + status = smsatSetFeaturesReadLookAhead(smRoot, + &satNewIntIo->satIntSmIORequest, + satNewIOContext->psmDeviceHandle, + &satNewIntIo->satIntSmScsiXchg, + satNewIOContext + ); + if (status != SM_RC_SUCCESS) + { + smsatFreeIntIoResource(smRoot, oneDeviceData, satNewIntIo); + SM_DBG1(("smsatSetFeaturesDMACB: failed to call smsatSetFeatures()\n")); + /*Complete this identify device IO */ + tdsmIDCompletedCB(smRoot, smIORequest, smDeviceHandle, smIOSuccess, &(oneDeviceData->satIdentifyData)); + } + SM_DBG2(("smsatSetFeaturesDMACB: end\n")); + return; + } + /* enble Volatile Write Cache feature*/ + if (oneDeviceData->satVolatileWriteCacheSupport == agTRUE) + { + satNewIntIo = smsatAllocIntIoResource(smRoot, + smOrgIORequest, + oneDeviceData, + 0, + satNewIntIo); + if (satNewIntIo == agNULL) + { + SM_DBG1(("smsatSetFeaturesDMACB: memory allocation fails\n")); + /*Complete this identify packet device IO */ + tdsmIDCompletedCB(smRoot, smIORequest, smDeviceHandle, smIOSuccess, &(oneDeviceData->satIdentifyData)); + return; + } /* end memory allocation */ + satNewIOContext = smsatPrepareNewIO(satNewIntIo, + smOrgIORequest, + oneDeviceData, + scsiCmnd, + satOrgIOContext + ); + /* sends SET FEATURES command to enable Volatile Write Cache */ + status = smsatSetFeaturesVolatileWriteCache(smRoot, + &satNewIntIo->satIntSmIORequest, + satNewIOContext->psmDeviceHandle, + &satNewIntIo->satIntSmScsiXchg, + satNewIOContext + ); + if (status != SM_RC_SUCCESS) + { + smsatFreeIntIoResource(smRoot, oneDeviceData, satNewIntIo); + SM_DBG1(("smsatSetFeaturesDMACB: failed to call smsatSetFeatures()\n")); + /*Complete this identify device IO */ + tdsmIDCompletedCB(smRoot, smIORequest, smDeviceHandle, smIOSuccess, &(oneDeviceData->satIdentifyData)); + } + SM_DBG2(("smsatSetFeaturesDMACB: end\n")); + return; + } + /* turn on DMA Setup FIS auto-activate by sending set feature FIS */ + if (oneDeviceData->satNCQ == agTRUE && oneDeviceData->satDMASetupAA == agTRUE) + { + satNewIntIo = smsatAllocIntIoResource( smRoot, + smOrgIORequest, + oneDeviceData, + 0, + satNewIntIo); + + if (satNewIntIo == agNULL) + { + SM_DBG1(("smsatSetFeaturesDMACB: momory allocation fails; can't send set feature\n")); + tdsmIDCompletedCB(smRoot, smIORequest, smDeviceHandle, smIOSuccess, &(oneDeviceData->satIdentifyData)); + return; + } /* end memory allocation */ + satNewIOContext = smsatPrepareNewIO(satNewIntIo, + smOrgIORequest, + oneDeviceData, + agNULL, + satOrgIOContext + ); + /* send the Set Feature ATA command to SATA device for enable DMA Setup FIS auto-activate */ + status = smsatSetFeaturesAA(smRoot, + &satNewIntIo->satIntSmIORequest, + satNewIOContext->psmDeviceHandle, + &satNewIntIo->satIntSmScsiXchg, /* orginal from OS layer */ + satNewIOContext); + if (status != SM_RC_SUCCESS) + { + SM_DBG1(("smsatSetFeaturesDMACB: failed to send set feature!!!\n")); + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satNewIntIo); + tdsmIDCompletedCB(smRoot, smIORequest, smDeviceHandle, smIOFailed, &(oneDeviceData->satIdentifyData)); + } + } + else + { + /*Complete this identify device IO */ + tdsmIDCompletedCB(smRoot, smIORequest, smDeviceHandle, smIOSuccess, &(oneDeviceData->satIdentifyData)); + } + SM_DBG2(("smsatSetFeaturesDMACB: end\n")); +} + +/***************************************************************************** +*! \brief smsatSetFeaturesReadLookAheadCB +* +* This routine is a callback function called from smllSATACompleted(). +* This CB routine deals with normal non-chained data I/O SATA request. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to smSatIOContext_t. +* +* \return: none +* +*****************************************************************************/ +osGLOBAL void +smsatSetFeaturesReadLookAheadCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smIORequestBody_t *smOrgIORequestBody = agNULL; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatIOContext_t *satNewIOContext; + smSatInternalIo_t *satIntIo; + smSatInternalIo_t *satNewIntIo = agNULL; + smDeviceData_t *oneDeviceData; + smIniScsiCmnd_t *scsiCmnd; + smIORequest_t *smOrgIORequest; + smDeviceHandle_t *smDeviceHandle; + bit32 status = SM_RC_FAILURE; + smIORequest_t *smIORequest; + + SM_DBG2(("smsatSetFeaturesReadLookAheadCB: start\n")); + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + if (satIOContext == agNULL) + { + SM_DBG1(("smsatSetFeaturesReadLookAheadCB: satIOContext is NULL\n")); + return; + } + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + smDeviceHandle = satIOContext->psmDeviceHandle; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + + if (satIntIo == agNULL) + { + SM_DBG2(("smsatSetFeaturesReadLookAheadCB: External smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + smOrgIORequest = smIORequestBody->smIORequest; + scsiCmnd = satIOContext->pScsiCmnd; + } + else + { + SM_DBG2(("smsatSetFeaturesReadLookAheadCB: Internal smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + smOrgIORequest = (smIORequest_t *)smOrgIORequestBody->smIORequest; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + smIORequest = smOrgIORequestBody->smIORequest; + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + + oneDeviceData->satLookAheadEnabled = agTRUE; + + /* interal structure free */ + smsatFreeIntIoResource(smRoot, + oneDeviceData, + satIntIo); + + /* check the agIOStatus */ + if (agIOStatus == OSSA_IO_ABORTED || + agIOStatus == OSSA_IO_NO_DEVICE || + agIOStatus == OSSA_IO_PORT_IN_RESET || + agIOStatus == OSSA_IO_DS_NON_OPERATIONAL || + agIOStatus == OSSA_IO_DS_IN_RECOVERY || + agIOStatus == OSSA_IO_DS_IN_ERROR || + agIOStatus == OSSA_IO_DS_INVALID + ) + { + SM_DBG1(("smsatSetFeaturesReadLookAheadCB: error status 0x%x\n", agIOStatus)); + SM_DBG1(("smsatSetFeaturesReadLookAheadCB: did %d!!!\n", oneDeviceData->id)); + tdsmIDCompletedCB(smRoot, smIORequest, smDeviceHandle, smIOSuccess, &(oneDeviceData->satIdentifyData)); + return; + } + + + + /* enble Volatile Write Cache feature*/ + if (oneDeviceData->satVolatileWriteCacheSupport == agTRUE) + { + satNewIntIo = smsatAllocIntIoResource(smRoot, + smOrgIORequest, + oneDeviceData, + 0, + satNewIntIo); + if (satNewIntIo == agNULL) + { + SM_DBG1(("smsatSetFeaturesReadLookAheadCB: memory allocation fails\n")); + /*Complete this identify packet device IO */ + tdsmIDCompletedCB(smRoot, smIORequest, smDeviceHandle, smIOSuccess, &(oneDeviceData->satIdentifyData)); + return; + } /* end memory allocation */ + + satNewIOContext = smsatPrepareNewIO(satNewIntIo, + smOrgIORequest, + oneDeviceData, + scsiCmnd, + satOrgIOContext + ); + /* sends SET FEATURES command to enable Volatile Write Cache */ + status = smsatSetFeaturesVolatileWriteCache(smRoot, + &satNewIntIo->satIntSmIORequest, + satNewIOContext->psmDeviceHandle, + &satNewIntIo->satIntSmScsiXchg, + satNewIOContext + ); + if (status != SM_RC_SUCCESS) + { + smsatFreeIntIoResource(smRoot, oneDeviceData, satNewIntIo); + SM_DBG1(("smsatSetFeaturesReadLookAheadCB: failed to call smsatSetFeatures()\n")); + /*Complete this identify device IO */ + tdsmIDCompletedCB(smRoot, smIORequest, smDeviceHandle, smIOSuccess, &(oneDeviceData->satIdentifyData)); + } + SM_DBG2(("smsatSetFeaturesReadLookAheadCB: end\n")); + + return; + } + + /* turn on DMA Setup FIS auto-activate by sending set feature FIS */ + if (oneDeviceData->satNCQ == agTRUE && oneDeviceData->satDMASetupAA == agTRUE) + { + satNewIntIo = smsatAllocIntIoResource( smRoot, + smOrgIORequest, + oneDeviceData, + 0, + satNewIntIo); + + if (satNewIntIo == agNULL) + { + SM_DBG1(("smsatSetFeaturesReadLookAheadCB: momory allocation fails; can't send set feature\n")); + tdsmIDCompletedCB(smRoot, smIORequest, smDeviceHandle, smIOSuccess, &(oneDeviceData->satIdentifyData)); + return; + } /* end memory allocation */ + + satNewIOContext = smsatPrepareNewIO(satNewIntIo, + smOrgIORequest, + oneDeviceData, + agNULL, + satOrgIOContext + ); + /* send the Set Feature ATA command to SATA device for enable DMA Setup FIS auto-activate */ + status = smsatSetFeaturesAA(smRoot, + &satNewIntIo->satIntSmIORequest, + satNewIOContext->psmDeviceHandle, + &satNewIntIo->satIntSmScsiXchg, /* orginal from OS layer */ + satNewIOContext); + + if (status != SM_RC_SUCCESS) + { + SM_DBG1(("smsatSetFeaturesReadLookAheadCB: failed to send set feature!!!\n")); + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satNewIntIo); + /* clean up TD layer's IORequestBody */ + tdsmIDCompletedCB(smRoot, smIORequest, smDeviceHandle, smIOFailed, &(oneDeviceData->satIdentifyData)); + } + } + else + { + /*Complete this identify device IO */ + tdsmIDCompletedCB(smRoot, smIORequest, smDeviceHandle, smIOSuccess, &(oneDeviceData->satIdentifyData)); + } + SM_DBG2(("smsatSetFeaturesReadLookAheadCB: end\n")); +} +/***************************************************************************** +*! \brief smsatSetFeaturesVolatileWriteCacheCB +* +* This routine is a callback function called from smllSATACompleted(). +* This CB routine deals with normal non-chained data I/O SATA request. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to smSatIOContext_t. +* +* \return: none +* +*****************************************************************************/ +osGLOBAL void +smsatSetFeaturesVolatileWriteCacheCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smIORequestBody_t *smOrgIORequestBody = agNULL; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatIOContext_t *satNewIOContext; + smSatInternalIo_t *satIntIo; + smSatInternalIo_t *satNewIntIo = agNULL; + smDeviceData_t *oneDeviceData; + smIORequest_t *smOrgIORequest; + smDeviceHandle_t *smDeviceHandle; + smIORequest_t *smIORequest; + bit32 ataStatus = 0; + bit32 ataError = 0; + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + bit32 status = SM_RC_FAILURE; + + SM_DBG2(("smsatSetFeaturesVolatileWriteCacheCB: start\n")); + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + if (satIOContext == agNULL) + { + SM_DBG1(("smsatSetFeaturesVolatileWriteCacheCB: satIOContext is NULL\n")); + return; + } + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + smDeviceHandle = satIOContext->psmDeviceHandle; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + if (satIntIo == agNULL) + { + SM_DBG5(("smsatSetFeaturesVolatileWriteCacheCB: External smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + smOrgIORequest = smIORequestBody->smIORequest; + smIORequest = smOrgIORequest; + } + else + { + SM_DBG5(("smsatSetFeaturesVolatileWriteCacheCB: Internal smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + smOrgIORequest = (smIORequest_t *)smOrgIORequestBody->smIORequest; + } + smIORequest = smOrgIORequestBody->smIORequest; + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatSetFeaturesVolatileWriteCacheCB: fail, case 1 agFirstDword is NULL when error, status %d!!!\n", agIOStatus)); + } + if (agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatSetFeaturesVolatileWriteCacheCB: fail, case 2 status %d!!!\n", agIOStatus)); + } + if (agIOInfoLen != 0 && agIOStatus == OSSA_IO_SUCCESS) + { + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + ataError = statDevToHostFisHeader->error; /* ATA Eror register */ + if ((ataStatus & ERR_ATA_STATUS_MASK) || (ataStatus & DF_ATA_STATUS_MASK)) + { + SM_DBG1(("smsatSetFeaturesVolatileWriteCacheCB: fail, case 3 ataStatus %d ataError %d!!!\n", ataStatus, ataError)); + } + if (ataError != 0) + { + SM_DBG1(("smsatSetFeaturesVolatileWriteCacheCB: fail, case 4 ataStatus %d ataError %d!!!\n", ataStatus, ataError)); + } + } + + oneDeviceData->satWriteCacheEnabled = agTRUE; + + /* interal structure free */ + smsatFreeIntIoResource(smRoot,oneDeviceData, satIntIo); + /* check the agIOStatus */ + if (agIOStatus == OSSA_IO_ABORTED || + agIOStatus == OSSA_IO_NO_DEVICE || + agIOStatus == OSSA_IO_PORT_IN_RESET || + agIOStatus == OSSA_IO_DS_NON_OPERATIONAL || + agIOStatus == OSSA_IO_DS_IN_RECOVERY || + agIOStatus == OSSA_IO_DS_IN_ERROR || + agIOStatus == OSSA_IO_DS_INVALID + ) + { + SM_DBG1(("smsatSetFeaturesVolatileWriteCacheCB: error status 0x%x\n", agIOStatus)); + SM_DBG1(("smsatSetFeaturesVolatileWriteCacheCB: did %d!!!\n", oneDeviceData->id)); + tdsmIDCompletedCB(smRoot, smIORequest, smDeviceHandle, smIOSuccess, &(oneDeviceData->satIdentifyData)); + return; + } + /* turn on DMA Setup FIS auto-activate by sending set feature FIS */ + if (oneDeviceData->satNCQ == agTRUE && oneDeviceData->satDMASetupAA == agTRUE) + { + satNewIntIo = smsatAllocIntIoResource( smRoot, + smOrgIORequest, + oneDeviceData, + 0, + satNewIntIo); + if (satNewIntIo == agNULL) + { + SM_DBG1(("smsatSetFeaturesVolatileWriteCacheCB: momory allocation fails; can't send set feature\n")); + tdsmIDCompletedCB(smRoot, smIORequest, smDeviceHandle, smIOSuccess, &(oneDeviceData->satIdentifyData)); + return; + } /* end memory allocation */ + satNewIOContext = smsatPrepareNewIO(satNewIntIo, + smOrgIORequest, + oneDeviceData, + agNULL, + satOrgIOContext + ); + /* send the Set Feature ATA command to SATA device for enable DMA Setup FIS auto-activate */ + status = smsatSetFeaturesAA(smRoot, + &satNewIntIo->satIntSmIORequest, + satNewIOContext->psmDeviceHandle, + &satNewIntIo->satIntSmScsiXchg, /* orginal from OS layer */ + satNewIOContext); + if (status != SM_RC_SUCCESS) + { + SM_DBG1(("smsatSetFeaturesVolatileWriteCacheCB: failed to send set feature!!!\n")); + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satNewIntIo); + /* clean up TD layer's IORequestBody */ + tdsmIDCompletedCB(smRoot, smIORequest, smDeviceHandle, smIOFailed, &(oneDeviceData->satIdentifyData)); + } + } + else + { + /*Complete this identify device IO */ + tdsmIDCompletedCB(smRoot, smIORequest, smDeviceHandle, smIOSuccess, &(oneDeviceData->satIdentifyData)); + } + SM_DBG2(("smsatSetFeaturesVolatileWriteCacheCB: end\n")); +} + + +osGLOBAL void +smsatSMARTEnablePassCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ) + { + + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smIORequestBody_t *smOrgIORequestBody; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + //smSatIOContext_t *satNewIOContext; + smSatInternalIo_t *satIntIo; + //smSatInternalIo_t *satNewIntIo = agNULL; +// satDeviceData_t *satDevData; + smDeviceData_t *oneDeviceData; + smIniScsiCmnd_t *scsiCmnd; + smIORequest_t *smOrgIORequest; + //bit32 status; + smScsiRspSense_t *pSense; + bit8 bSenseKey = 0; + bit16 bSenseCodeInfo = 0; + + + SM_DBG2(("smsatSMARTEnablePassCB: start\n")); + SM_DBG4(("smsatSMARTEnablePassCB:agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate tiIOContext */ + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + /*ttttttthe one */ + if (satIntIo == agNULL) + { + SM_DBG4(("smsatSMARTEnablePassCB: External smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + smOrgIORequest = smIORequestBody->smIORequest; + scsiCmnd = satOrgIOContext->pScsiCmnd; + pSense = satOrgIOContext->pSense; + } + else + { + SM_DBG4(("smsatSMARTEnablePassCB: Internal smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + SM_DBG4(("smsatSMARTEnablePassCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + SM_DBG4(("smsatSMARTEnablePassCB: satOrgIOContext is NOT NULL\n")); + } + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + smOrgIORequest = (smIORequest_t *)smOrgIORequestBody->smIORequest; + scsiCmnd = satOrgIOContext->pScsiCmnd; + pSense = satOrgIOContext->pSense; + } + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatSMARTEnablePassCB: wrong. agFirstDword is NULL when error, status %d!!!\n", agIOStatus)); + tdsmIOCompletedCB( + smRoot, + smOrgIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + /* + checking IO status, FIS type and error status + */ + if (agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatSMARTEnablePassCB: not success status, status %d!!!\n", agIOStatus)); + if (agIOStatus == OSSA_IO_ABORTED) + { + smsatProcessAbort(smRoot, + smOrgIORequest, + satOrgIOContext + ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + smsatTranslateATAErrorsToSCSIErrors( + agFirstDword->D2H.status, + agFirstDword->D2H.error, + &bSenseKey, + &bSenseCodeInfo + ); + smsatSetSensePayload(pSense, bSenseKey, 0, bSenseCodeInfo, satOrgIOContext); + tdsmIOCompletedCB(smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + return; + } + /* process success case */ + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + SM_DBG1(("smsatSMARTEnablePassCB:success status, status %d!!!\n", agIOStatus)); + tdsmIOCompletedCB( + smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext + ); + + + + return; +} + +osGLOBAL void +smsatSMARTRStatusPassCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) + +{ + + + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smIORequestBody_t *smOrgIORequestBody; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatInternalIo_t *satIntIo; +// satDeviceData_t *satDevData; + smDeviceData_t *oneDeviceData; + + smScsiRspSense_t *pSense; + smIORequest_t *smOrgIORequest; + + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + smScsiInitiatorRequest_t *smScsiRequest; /* tiScsiXchg */ + smScsiInitiatorRequest_t *smOrgScsiRequest; /* tiScsiXchg */ + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; +// agsaFisRegD2HData_t statDevToHostFisData; + smIniScsiCmnd_t *scsiCmnd; + bit8 bSenseKey = 0; + bit16 bSenseCodeInfo = 0; + + + SM_DBG2(("smsatSMARTRStatusPassCB: start\n")); + SM_DBG5(("smsatSMARTRStatusPassCB:agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate smIOContext */ + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + + if (satIntIo == agNULL) + { + SM_DBG4(("smsatSMARTRStatusPassCB: External smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + smOrgIORequest = smIORequestBody->smIORequest; + pSense = satOrgIOContext->pSense; + smOrgScsiRequest = satOrgIOContext->smScsiXchg; + /* ATA command response payload */ + smScsiRequest = satOrgIOContext->smScsiXchg; + scsiCmnd = satOrgIOContext->pScsiCmnd; + SM_DBG1((" 0x%02x, 0x%02x, 0x%02x, 0x%02x,\n", scsiCmnd->cdb[0], scsiCmnd->cdb[1],scsiCmnd->cdb[2], scsiCmnd->cdb[3])); + SM_DBG1((" 0x%02x, 0x%02x, 0x%02x, 0x%02x,\n", scsiCmnd->cdb[4], scsiCmnd->cdb[5],scsiCmnd->cdb[6], scsiCmnd->cdb[7])); + SM_DBG1((" 0x%02x, 0x%02x, 0x%02x, 0x%02x,\n", scsiCmnd->cdb[8], scsiCmnd->cdb[9],scsiCmnd->cdb[10], scsiCmnd->cdb[11])); + + + } + else + { + SM_DBG4(("smsatSMARTRStatusPassCB: Internal smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + SM_DBG4(("smsatSMARTRStatusPassCB: satOrgIOContext is NULL\n")); + + return; + + } + else + { + SM_DBG4(("smsatSMARTRStatusPassCB: satOrgIOContext is NOT NULL\n")); + } + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + smOrgIORequest = (smIORequest_t *)smOrgIORequestBody->smIORequest; + + smOrgScsiRequest = satOrgIOContext->smScsiXchg; + /* ATA command response payload */ + smScsiRequest = (smScsiInitiatorRequest_t *)&(satIntIo->satIntSmScsiXchg); + scsiCmnd = satOrgIOContext->pScsiCmnd; + pSense = satOrgIOContext->pSense; + } + + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatSMARTRStatusPassCB: wrong. agFirstDword is NULL when error, status %d!!!\n", agIOStatus)); + tdsmIOCompletedCB( + smRoot, + smOrgIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + if( agIOStatus != OSSA_IO_SUCCESS) + { + + /* non-data -> device to host fis are expected */ + + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + + if ( (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) || + ((ataStatus & ERR_ATA_STATUS_MASK) || (ataStatus & DF_ATA_STATUS_MASK)) + ) + { + /* for debugging */ + if( agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatSMARTRStatusPassCB: FAILED, NOT IO_SUCCESS!!!\n")); + } + else if (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) + { + SM_DBG1(("smsatSMARTRStatusPassCB: FAILED, Wrong FIS type 0x%x!!!\n",statDevToHostFisHeader->fisType)); + } + else if ( (ataStatus & ERR_ATA_STATUS_MASK) || + (ataStatus & DF_ATA_STATUS_MASK) + ) + { + SM_DBG1(("smsatSMARTRStatusPassCB: FAILED, FAILED, error status!!!\n")); + } + + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + smsatProcessAbort(smRoot, + smOrgIORequest, + satOrgIOContext + ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + smsatTranslateATAErrorsToSCSIErrors( + agFirstDword->D2H.status, + agFirstDword->D2H.error, + &bSenseKey, + &bSenseCodeInfo + ); + smsatSetSensePayload(pSense, bSenseKey, 0, bSenseCodeInfo, satOrgIOContext); + tdsmIOCompletedCB(smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + + } /* error checking */ + } + + /* prcessing the success case */ + SM_DBG5(("smsatSMARTRStatusPassCB: SAT_SMART_RETURN_STATUS success\n")); + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext); + + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + + return; +} + +osGLOBAL void +smsatSMARTReadLogCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smIORequestBody_t *smOrgIORequestBody; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatInternalIo_t *satIntIo; +// satDeviceData_t *satDevData; + smDeviceData_t *oneDeviceData; + + smScsiRspSense_t *pSense; + smIORequest_t *smOrgIORequest; + + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + smScsiInitiatorRequest_t *smScsiRequest; /* tiScsiXchg */ + smScsiInitiatorRequest_t *smOrgScsiRequest; /* tiScsiXchg */ +// satReadLogExtSelfTest_t *virtAddr1; +// satSmartReadLogSelfTest_t *virtAddr2; + //bit8 *pLogPage; +// bit8 SelfTestExecutionStatus = 0; +// bit32 i = 0; + + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; +// agsaFisRegD2HData_t statDevToHostFisData; + smIniScsiCmnd_t *scsiCmnd; +// bit32 lenReceived = 0; + bit8 bSenseKey = 0; + bit16 bSenseCodeInfo = 0; + + SM_DBG2(("smsatSMARTReadLogCB: start\n")); + SM_DBG5(("smsatSMARTReadLogCB:agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate smIOContext */ + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + + if (satIntIo == agNULL) + { + SM_DBG4(("smsatSMARTReadLogCB: External smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + smOrgIORequest = smIORequestBody->smIORequest; + pSense = satOrgIOContext->pSense; + smOrgScsiRequest = satOrgIOContext->smScsiXchg; + + /* ATA command response payload */ + smScsiRequest = satOrgIOContext->smScsiXchg; + scsiCmnd = satOrgIOContext->pScsiCmnd; + + + } + else + { + SM_DBG4(("smsatSMARTReadLogCB: Internal smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + SM_DBG4(("smsatSMARTReadLogCB: satOrgIOContext is NULL\n")); + + return; + + } + else + { + SM_DBG4(("smsatSMARTReadLogCB: satOrgIOContext is NOT NULL\n")); + } + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + smOrgIORequest = (smIORequest_t *)smOrgIORequestBody->smIORequest; + + pSense = satOrgIOContext->pSense; + smOrgScsiRequest = satOrgIOContext->smScsiXchg; + + /* ATA command response payload */ + smScsiRequest = (smScsiInitiatorRequest_t *)&(satIntIo->satIntSmScsiXchg); + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatSMARTReadLogCB: wrong. agFirstDword is NULL when error, status %d!!!\n", agIOStatus)); + tdsmIOCompletedCB( + smRoot, + smOrgIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + //for Debuggings + if(agFirstDword != NULL) + { + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + SM_DBG1(("smsatSMARTReadLogCB: statDevToHostFisHeader->status, status %d!!!\n", statDevToHostFisHeader->status)); + } + if ((agIOStatus != OSSA_IO_SUCCESS) && (agFirstDword != NULL)) + { + /* non-data and pio read -> device to host and pio setup fis are expected */ + /* + first, assumed to be Reg Device to Host FIS + This is OK to just find fis type + */ + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + } + + if( agIOStatus != OSSA_IO_SUCCESS) + { + if ( ((statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) && + (statDevToHostFisHeader->fisType != PIO_SETUP_DEV_TO_HOST_FIS)) || + ((ataStatus & ERR_ATA_STATUS_MASK) || (ataStatus & DF_ATA_STATUS_MASK)) + ) + { + /* for debugging */ + if( agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatSMARTReadLogCB: FAILED, NOT IO_SUCCESS!!!\n")); + } + else if (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) + { + SM_DBG1(("smsatSMARTReadLogCB: FAILED, Wrong FIS type 0x%x!!!\n",statDevToHostFisHeader->fisType)); + } + else if (statDevToHostFisHeader->fisType != PIO_SETUP_DEV_TO_HOST_FIS) + { + SM_DBG1(("smsatSMARTReadLogCB: FAILED, Wrong FIS type 0x%x!!!\n",statDevToHostFisHeader->fisType)); + } + else if ( (ataStatus & ERR_ATA_STATUS_MASK) || + (ataStatus & DF_ATA_STATUS_MASK) + ) + { + SM_DBG1(("smsatSMARTReadLogCB: FAILED, FAILED, error status!!!\n")); + } + + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + smsatProcessAbort(smRoot, + smOrgIORequest, + satOrgIOContext + ); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + /* for debugging */ + + if (hostToDevFis->h.command == SAT_SMART) + { + if (hostToDevFis->h.features == SAT_SMART_READ_LOG) + { + SM_DBG1(("smsatSMARTReadLogCB: SAT_SMART_READ_LOG failed!!!\n")); + } + else + { + SM_DBG1(("smsatSMARTReadLogCB: error unknown command 0x%x feature 0x%x!!!\n", hostToDevFis->h.command, hostToDevFis->h.features)); + } + } + else + { + SM_DBG1(("smsatSMARTReadLogCB: error default case command 0x%x!!!\n", hostToDevFis->h.command)); + } + + smsatTranslateATAErrorsToSCSIErrors( + agFirstDword->D2H.status, + agFirstDword->D2H.error, + &bSenseKey, + &bSenseCodeInfo + ); + smsatSetSensePayload(pSense, bSenseKey, 0, bSenseCodeInfo, satOrgIOContext); + tdsmIOCompletedCB(smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + + } /* error checking */ + } + + /* prcessing the success case */ + + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + return; +} + +osGLOBAL void +smsatPassthroughCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + smRoot_t *smRoot = agNULL; + smIntRoot_t *smIntRoot = agNULL; + smIntContext_t *smAllShared = agNULL; + smIORequestBody_t *smIORequestBody; + smIORequestBody_t *smOrgIORequestBody; + smSatIOContext_t *satIOContext; + smSatIOContext_t *satOrgIOContext; + smSatInternalIo_t *satIntIo; + smDeviceData_t *oneDeviceData; + smScsiRspSense_t *pSense; + smIORequest_t *smOrgIORequest; + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + smScsiInitiatorRequest_t *smScsiRequest; /* tiScsiXchg */ + smScsiInitiatorRequest_t *smOrgScsiRequest; /* tiScsiXchg */ + + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + smIniScsiCmnd_t *scsiCmnd; + bit8 bSenseKey = 0; + bit16 bSenseCodeInfo = 0; + + SM_DBG2(("smsatPassthroughCB: start\n")); + SM_DBG5(("smsatPassthroughCB:agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate smIOContext */ + smIORequestBody = (smIORequestBody_t *)agIORequest->osData; + satIOContext = (smSatIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + oneDeviceData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + smRoot = oneDeviceData->smRoot; + smIntRoot = (smIntRoot_t *)smRoot->smData; + smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + + if (satIntIo == agNULL) + { + SM_DBG4(("smsatPassthroughCB: External smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + smOrgIORequest = smIORequestBody->smIORequest; + pSense = satOrgIOContext->pSense; + smOrgScsiRequest = satOrgIOContext->smScsiXchg; + + /* ATA command response payload */ + smScsiRequest = satOrgIOContext->smScsiXchg; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + else + { + SM_DBG4(("smsatPassthroughCB: Internal smSatInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + SM_DBG4(("smsatPassthroughCB: satOrgIOContext is NULL\n")); + return; + } + else + { + SM_DBG4(("smsatPassthroughCB: satOrgIOContext is NOT NULL\n")); + } + smOrgIORequestBody = (smIORequestBody_t *)satOrgIOContext->smRequestBody; + smOrgIORequest = (smIORequest_t *)smOrgIORequestBody->smIORequest; + + pSense = satOrgIOContext->pSense; + smOrgScsiRequest = satOrgIOContext->smScsiXchg; + + /* ATA command response payload */ + smScsiRequest = (smScsiInitiatorRequest_t *)&(satIntIo->satIntSmScsiXchg); + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + + smIORequestBody->ioCompleted = agTRUE; + smIORequestBody->ioStarted = agFALSE; + + + if (agIOStatus == OSSA_IO_UNDERFLOW) + { + SM_DBG1(("smsatPassthroughCB: IO_UNDERFLOW, status %d!!!\n", agIOStatus)); + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOUnderRun, + agIOInfoLen, + agNULL, + satOrgIOContext->interruptContext + ); + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatPassthroughCB: wrong. agFirstDword is NULL when error, status %d!!!\n", agIOStatus)); + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOFailed, + smDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + //for Debuggings + + if ((agIOStatus != OSSA_IO_SUCCESS) && (agFirstDword != NULL)) + { + /* non-data and pio read -> device to host and pio setup fis are expected */ + /* + first, assumed to be Reg Device to Host FIS + This is OK to just find fis type + */ + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + } + if( agIOStatus != OSSA_IO_SUCCESS) + { + if ( ((statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) && + (statDevToHostFisHeader->fisType != PIO_SETUP_DEV_TO_HOST_FIS)) || + ((ataStatus & ERR_ATA_STATUS_MASK) || (ataStatus & DF_ATA_STATUS_MASK)) + ) + { + /* for debugging */ + if( agIOStatus != OSSA_IO_SUCCESS) + { + SM_DBG1(("smsatPassthroughCB: FAILED, NOT IO_SUCCESS!!!\n")); + } + else if (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) + { + SM_DBG1(("smsatPassthroughCB: FAILED, Wrong FIS type 0x%x!!!\n",statDevToHostFisHeader->fisType)); + } + else if (statDevToHostFisHeader->fisType != PIO_SETUP_DEV_TO_HOST_FIS) + { + SM_DBG1(("smsatPassthroughCB: FAILED, Wrong FIS type 0x%x!!!\n",statDevToHostFisHeader->fisType)); + } + else if ( (ataStatus & ERR_ATA_STATUS_MASK) || + (ataStatus & DF_ATA_STATUS_MASK) + ) + { + SM_DBG1(("smsatPassthroughCB: FAILED, FAILED, error status!!!\n")); + } + + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + smsatProcessAbort( smRoot, + smOrgIORequest, + satOrgIOContext); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + + smsatTranslateATAErrorsToSCSIErrors( agFirstDword->D2H.status, + agFirstDword->D2H.error, + &bSenseKey, + &bSenseCodeInfo + ); + smsatSetSensePayload(pSense, bSenseKey, 0, bSenseCodeInfo, satOrgIOContext); + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + + } /* error checking */ + } + + /* prcessing the success case */ + if(agFirstDword != NULL) + { + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + SM_DBG1(("smsatPassthroughCB: statDevToHostFisHeader->status, status %d!!!\n", statDevToHostFisHeader->status)); + smsatTranslateATAErrorsToSCSIErrors( agFirstDword->D2H.status, + agFirstDword->D2H.error, + &bSenseKey, + &bSenseCodeInfo); + smsatSetSensePayload(pSense, bSenseKey, 0, bSenseCodeInfo, satOrgIOContext); + if(agFirstDword->D2H.status & 0x01) + { + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pSmSenseData, + satOrgIOContext->interruptContext ); + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + return; + } + } + + tdsmIOCompletedCB( smRoot, + smOrgIORequest, + smIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext); + + smsatDecrementPendingIO(smRoot, smAllShared, satIOContext); + + smsatFreeIntIoResource( smRoot, + oneDeviceData, + satIntIo); + + return; +} + diff --git a/sys/dev/pms/RefTisa/sat/src/smsathw.c b/sys/dev/pms/RefTisa/sat/src/smsathw.c new file mode 100644 index 000000000000..b32e25e0a179 --- /dev/null +++ b/sys/dev/pms/RefTisa/sat/src/smsathw.c @@ -0,0 +1,530 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#include +#include + +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +/* + * This table is used to map LL Layer saSATAStart() status to TISA status. + */ + + +FORCEINLINE bit32 +smsataLLIOStart( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smScsiRequest, + smSatIOContext_t *satIOContext + ) +{ + smDeviceData_t *oneDeviceData = (smDeviceData_t *)smDeviceHandle->smData; + smIntRoot_t *smIntRoot = (smIntRoot_t *) smRoot->smData; + smIntContext_t *smAllShared = (smIntContext_t *)&(smIntRoot->smAllShared); + smIORequestBody_t *smIORequestBody = (smIORequestBody_t *)satIOContext->smRequestBody; + smDeviceData_t *pSatDevData = satIOContext->pSatDevData; + smSatInternalIo_t *satIntIo = satIOContext->satIntIoContext; + agsaRoot_t *agRoot = smAllShared->agRoot; + agsaIORequest_t *agIORequest = &(smIORequestBody->agIORequest); + agsaDevHandle_t *agDevHandle = oneDeviceData->agDevHandle; + agsaSATAInitiatorRequest_t *agSATAReq = &(smIORequestBody->transport.SATA.agSATARequestBody); + bit32 RLERecovery = agFALSE; + bit32 status = SM_RC_FAILURE; + bit32 nQNumber = 0; + /* + * If this is a super I/O request, check for optional settings. + * Be careful. Use the superRequest pointer for all references + * in this block of code. + */ + agSATAReq->option = 0; + if (satIOContext->superIOFlag) + { + smSuperScsiInitiatorRequest_t *superRequest = (smSuperScsiInitiatorRequest_t *) smScsiRequest; + + if (superRequest->flags & SM_SCSI_INITIATOR_ENCRYPT) + { + /* Copy all of the relevant encrypt information */ + agSATAReq->option |= AGSA_SATA_ENABLE_ENCRYPTION; + sm_memcpy(&agSATAReq->encrypt, &superRequest->Encrypt, sizeof(agsaEncrypt_t)); + } + { + /* initialize expDataLength */ + if (satIOContext->reqType == AGSA_SATA_PROTOCOL_NON_DATA || + satIOContext->reqType == AGSA_SATA_PROTOCOL_SRST_ASSERT || + satIOContext->reqType == AGSA_SATA_PROTOCOL_SRST_DEASSERT ) + { + smIORequestBody->IOType.InitiatorRegIO.expDataLength = 0; + } + else + { + smIORequestBody->IOType.InitiatorRegIO.expDataLength = smScsiRequest->scsiCmnd.expDataLength; + } + + agSATAReq->dataLength = smIORequestBody->IOType.InitiatorRegIO.expDataLength; + } + } + else + { + /* initialize expDataLength */ + if (satIOContext->reqType == AGSA_SATA_PROTOCOL_NON_DATA || + satIOContext->reqType == AGSA_SATA_PROTOCOL_SRST_ASSERT || + satIOContext->reqType == AGSA_SATA_PROTOCOL_SRST_DEASSERT ) + { + smIORequestBody->IOType.InitiatorRegIO.expDataLength = 0; + } + else + { + smIORequestBody->IOType.InitiatorRegIO.expDataLength = smScsiRequest->scsiCmnd.expDataLength; + } + + agSATAReq->dataLength = smIORequestBody->IOType.InitiatorRegIO.expDataLength; + } + + if ( (pSatDevData->satDriveState == SAT_DEV_STATE_IN_RECOVERY) && + (satIOContext->pFis->h.command == SAT_READ_LOG_EXT) ) + { + RLERecovery = agTRUE; + } + + /* check max io, be sure to free */ + if ( (pSatDevData->satDriveState != SAT_DEV_STATE_IN_RECOVERY) || + (RLERecovery == agTRUE) ) + { + if (RLERecovery == agFALSE) /* RLE is not checked against pending IO's */ + { +#ifdef CCFLAG_OPTIMIZE_SAT_LOCK + bit32 volatile satPendingNCQIO = 0; + bit32 volatile satPendingNONNCQIO = 0; + bit32 volatile satPendingIO = 0; + + tdsmInterlockedExchange(smRoot, &satPendingNCQIO, pSatDevData->satPendingNCQIO); + tdsmInterlockedExchange(smRoot, &satPendingNONNCQIO, pSatDevData->satPendingNONNCQIO); + tdsmInterlockedExchange(smRoot, &satPendingIO, pSatDevData->satPendingIO); +#endif + + if ( (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_WRITE) || + (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_READ) ) + { + #ifdef CCFLAG_OPTIMIZE_SAT_LOCK + if ( satPendingNCQIO >= pSatDevData->satNCQMaxIO || + satPendingNONNCQIO != 0) + { + SM_DBG1(("smsataLLIOStart: 1st busy did %d!!!\n", pSatDevData->id)); + SM_DBG1(("smsataLLIOStart: 1st busy NCQ. NCQ Pending 0x%x NONNCQ Pending 0x%x All Pending 0x%x!!!\n", satPendingNCQIO, + satPendingNONNCQIO, satPendingIO)); + /* free resource */ + smsatFreeIntIoResource( smRoot, + pSatDevData, + satIntIo); + return SM_RC_DEVICE_BUSY; + } + #else + tdsmSingleThreadedEnter(smRoot, SM_EXTERNAL_IO_LOCK); + if (pSatDevData->satPendingNCQIO >= pSatDevData->satNCQMaxIO || + pSatDevData->satPendingNONNCQIO != 0) + { + SM_DBG1(("smsataLLIOStart: 1st busy did %d!!!\n", pSatDevData->id)); + SM_DBG1(("smsataLLIOStart: 1st busy NCQ. NCQ Pending 0x%x NONNCQ Pending 0x%x All Pending 0x%x!!!\n", pSatDevData->satPendingNCQIO, + pSatDevData->satPendingNONNCQIO, pSatDevData->satPendingIO)); + tdsmSingleThreadedLeave(smRoot, SM_EXTERNAL_IO_LOCK); + /* free resource */ + smsatFreeIntIoResource( smRoot, + pSatDevData, + satIntIo); + return SM_RC_DEVICE_BUSY; + } + tdsmSingleThreadedLeave(smRoot, SM_EXTERNAL_IO_LOCK); + #endif + + } + else if ( (satIOContext->reqType == AGSA_SATA_PROTOCOL_D2H_PKT) || + (satIOContext->reqType == AGSA_SATA_PROTOCOL_H2D_PKT) || + (satIOContext->reqType == AGSA_SATA_PROTOCOL_NON_PKT) ) + { + sm_memcpy(agSATAReq->scsiCDB, smScsiRequest->scsiCmnd.cdb, 16); + #ifdef CCFLAG_OPTIMIZE_SAT_LOCK + if ( satPendingNONNCQIO >= SAT_APAPI_CMDQ_MAX || + satPendingNCQIO != 0) + { + SM_DBG1(("smsataLLIOStart: ATAPI busy did %d!!!\n", pSatDevData->id)); + SM_DBG1(("smsataLLIOStart: ATAPI busy NON-NCQ. NCQ Pending 0x%x NON-NCQ Pending 0x%x All Pending 0x%x!!!\n", satPendingNCQIO, + satPendingNONNCQIO, satPendingIO)); + /* free resource */ + smsatFreeIntIoResource( smRoot, + pSatDevData, + satIntIo); + return SM_RC_DEVICE_BUSY; + } + #else + tdsmSingleThreadedEnter(smRoot, SM_EXTERNAL_IO_LOCK); + if ( pSatDevData->satPendingNONNCQIO >= SAT_APAPI_CMDQ_MAX || + pSatDevData->satPendingNCQIO != 0) + { + SM_DBG1(("smsataLLIOStart: ATAPI busy did %d!!!\n", pSatDevData->id)); + SM_DBG1(("smsataLLIOStart: ATAPI busy NON-NCQ. NCQ Pending 0x%x NON-NCQ Pending 0x%x All Pending 0x%x!!!\n", pSatDevData->satPendingNCQIO, + pSatDevData->satPendingNONNCQIO, pSatDevData->satPendingIO)); + tdsmSingleThreadedLeave(smRoot, SM_EXTERNAL_IO_LOCK); + /* free resource */ + smsatFreeIntIoResource( smRoot, + pSatDevData, + satIntIo); + return SM_RC_DEVICE_BUSY; + } + tdsmSingleThreadedLeave(smRoot, SM_EXTERNAL_IO_LOCK); + #endif + + } + else + { +#ifdef CCFLAG_OPTIMIZE_SAT_LOCK + if ( satPendingNONNCQIO >= SAT_NONNCQ_MAX || + satPendingNCQIO != 0) + { + SM_DBG1(("smsataLLIOStart: 2nd busy did %d!!!\n", pSatDevData->id)); + SM_DBG1(("smsataLLIOStart: 2nd busy NCQ. NCQ Pending 0x%x NONNCQ Pending 0x%x All Pending 0x%x!!!\n", satPendingNCQIO, + satPendingNONNCQIO, satPendingIO)); + /* free resource */ + smsatFreeIntIoResource( smRoot, + pSatDevData, + satIntIo); + return SM_RC_DEVICE_BUSY; + } +#else + tdsmSingleThreadedEnter(smRoot, SM_EXTERNAL_IO_LOCK); + if (pSatDevData->satPendingNONNCQIO >= SAT_NONNCQ_MAX || + pSatDevData->satPendingNCQIO != 0) + { + SM_DBG1(("smsataLLIOStart: 2nd busy did %d!!!\n", pSatDevData->id)); + SM_DBG1(("smsataLLIOStart: 2nd busy NCQ. NCQ Pending 0x%x NONNCQ Pending 0x%x All Pending 0x%x!!!\n", pSatDevData->satPendingNCQIO, + pSatDevData->satPendingNONNCQIO, pSatDevData->satPendingIO)); + tdsmSingleThreadedLeave(smRoot, SM_EXTERNAL_IO_LOCK); + /* free resource */ + smsatFreeIntIoResource( smRoot, + pSatDevData, + satIntIo); + return SM_RC_DEVICE_BUSY; + } + tdsmSingleThreadedLeave(smRoot, SM_EXTERNAL_IO_LOCK); +#endif + } + } /* RLE */ + /* for internal SATA command only */ + if (satIOContext->satOrgIOContext != agNULL) + { + /* Initialize tiIORequest */ + smIORequestBody->smIORequest = smIORequest; + if (smIORequest == agNULL) + { + SM_DBG1(("smsataLLIOStart: 1 check!!!\n")); + } + } + /* Initialize tiDevhandle */ + smIORequestBody->smDevHandle = smDeviceHandle; + + /* Initializes Scatter Gather and ESGL */ + status = smsatIOPrepareSGL( smRoot, + smIORequestBody, + &smScsiRequest->smSgl1, + smScsiRequest->sglVirtualAddr ); + + if (status != SM_RC_SUCCESS) + { + SM_DBG1(("smsataLLIOStart: can't get SGL!!!\n")); + /* free resource */ + smsatFreeIntIoResource( smRoot, + pSatDevData, + satIntIo); + return status; + } + + /* Initialize LL Layer agIORequest */ + agIORequest->osData = (void *) smIORequestBody; + agIORequest->sdkData = agNULL; /* SA takes care of this */ + + smIORequestBody->ioStarted = agTRUE; + smIORequestBody->ioCompleted = agFALSE; + + /* assign tag value for SATA */ + if ( (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_WRITE) || + (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_READ) ) + { + if (agFALSE == smsatTagAlloc(smRoot, pSatDevData, &satIOContext->sataTag)) + { + SM_DBG1(("smsataLLIOStart: No more NCQ tag!!!\n")); + smIORequestBody->ioStarted = agFALSE; + smIORequestBody->ioCompleted = agTRUE; + return SM_RC_DEVICE_BUSY; + } + SM_DBG3(("smsataLLIOStart: ncq tag 0x%x\n",satIOContext->sataTag)); + } + else + { + satIOContext->sataTag = 0xFF; + } + } + else /* AGSA_SATA_PROTOCOL_SRST_ASSERT or AGSA_SATA_PROTOCOL_SRST_DEASSERT + or SAT_CHECK_POWER_MODE as ABORT */ + { + agsaSgl_t *agSgl; + + /* for internal SATA command only */ + if (satIOContext->satOrgIOContext != agNULL) + { + /* Initialize tiIORequest */ + smIORequestBody->smIORequest = smIORequest; + if (smIORequest == agNULL) + { + SM_DBG1(("smsataLLIOStart: 2 check!!!\n")); + } + } + /* Initialize tiDevhandle */ + smIORequestBody->smDevHandle = smDeviceHandle; + + + smIORequestBody->IOType.InitiatorRegIO.expDataLength = 0; + /* SGL for SATA request */ + agSgl = &(smIORequestBody->transport.SATA.agSATARequestBody.agSgl); + agSgl->len = 0; + + agSgl->sgUpper = 0; + agSgl->sgLower = 0; + agSgl->len = 0; + SM_CLEAR_ESGL_EXTEND(agSgl->extReserved); + + /* Initialize LL Layer agIORequest */ + agIORequest = &(smIORequestBody->agIORequest); + agIORequest->osData = (void *) smIORequestBody; + agIORequest->sdkData = agNULL; /* SA takes care of this */ + + smIORequestBody->ioStarted = agTRUE; + smIORequestBody->ioCompleted = agFALSE; + + /* setting the data length */ + agSATAReq->dataLength = 0; + + } + + + smIORequestBody->reTries = 0; + +#ifdef TD_INTERNAL_DEBUG + smhexdump("smsataLLIOStart", (bit8 *)satIOContext->pFis, sizeof(agsaFisRegHostToDevice_t)); + smhexdump("smsataLLIOStart LL", (bit8 *)&agSATAReq->fis.fisRegHostToDev, + sizeof(agsaFisRegHostToDevice_t)); +#endif + + SM_DBG6(("smsataLLIOStart: agDevHandle %p\n", agDevHandle)); + + /* to get better IO performance, rotate the OBQ number on main IO path */ + if (smScsiRequest == agNULL) + { + nQNumber = 0; + } + else + { + switch (smScsiRequest->scsiCmnd.cdb[0]) + { + case SCSIOPC_READ_10: + case SCSIOPC_WRITE_10: + case SCSIOPC_READ_6: + case SCSIOPC_WRITE_6: + case SCSIOPC_READ_12: + case SCSIOPC_WRITE_12: + case SCSIOPC_READ_16: + case SCSIOPC_WRITE_16: + nQNumber = tdsmRotateQnumber(smRoot, smDeviceHandle); + break; + + default: + nQNumber = 0; + break; + } + } + + SM_DBG3(("sataLLIOStart: Lock in\n")); + +#ifdef CCFLAG_OPTIMIZE_SAT_LOCK + if ( (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_WRITE) || + (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_READ) ) + { + tdsmInterlockedIncrement(smRoot,&pSatDevData->satPendingNCQIO); + } + else + { + tdsmInterlockedIncrement(smRoot,&pSatDevData->satPendingNONNCQIO); + } + tdsmInterlockedIncrement(smRoot,&pSatDevData->satPendingIO); +#else + tdsmSingleThreadedEnter(smRoot, SM_EXTERNAL_IO_LOCK); + if ( (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_WRITE) || + (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_READ) ) + { + pSatDevData->satPendingNCQIO++; + } + else + { + pSatDevData->satPendingNONNCQIO++; + } + pSatDevData->satPendingIO++; + + SMLIST_INIT_ELEMENT (&satIOContext->satIoContextLink); + SMLIST_ENQUEUE_AT_TAIL (&satIOContext->satIoContextLink, &pSatDevData->satIoLinkList); + tdsmSingleThreadedLeave(smRoot, SM_EXTERNAL_IO_LOCK); +#endif + /* post SATA command to low level MPI */ + status = saSATAStart( agRoot, + agIORequest, + nQNumber, + agDevHandle, + satIOContext->reqType, + agSATAReq, + satIOContext->sataTag, + smllSATACompleted + ); + + if (status != AGSA_RC_SUCCESS) + { + if (status == AGSA_RC_BUSY) + { + SM_DBG1(("smsataLLIOStart: saSATAStart busy!!!\n")); + status = SM_RC_BUSY; + } + else + { + SM_DBG1(("smsataLLIOStart: saSATAStart failed!!!\n")); + status = SM_RC_FAILURE; + } + + if ( (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_WRITE) || + (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_READ) ) + { + smsatTagRelease(smRoot, pSatDevData, satIOContext->sataTag); + } + +#ifdef CCFLAG_OPTIMIZE_SAT_LOCK + if ( (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_WRITE) || + (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_READ) ) + { + tdsmInterlockedDecrement(smRoot,&oneDeviceData->satPendingNCQIO); + } + else + { + tdsmInterlockedDecrement(smRoot,&oneDeviceData->satPendingNONNCQIO); + } + tdsmInterlockedDecrement(smRoot,&oneDeviceData->satPendingIO); +#else + if ( (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_WRITE) || + (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_READ) ) + { + tdsmSingleThreadedEnter(smRoot, SM_EXTERNAL_IO_LOCK); + oneDeviceData->satPendingNCQIO--; + oneDeviceData->satPendingIO--; + SMLIST_DEQUEUE_THIS (&satIOContext->satIoContextLink); + tdsmSingleThreadedLeave(smRoot, SM_EXTERNAL_IO_LOCK); + } + else + { + tdsmSingleThreadedEnter(smRoot, SM_EXTERNAL_IO_LOCK); + oneDeviceData->satPendingNONNCQIO--; + oneDeviceData->satPendingIO--; + SMLIST_DEQUEUE_THIS (&satIOContext->satIoContextLink); + tdsmSingleThreadedLeave(smRoot, SM_EXTERNAL_IO_LOCK); + } +#endif /* CCFLAG_OPTIMIZE_SAT_LOCK */ + + /* Free the ESGL pages associated with this I/O */ + smIORequestBody->ioStarted = agFALSE; + smIORequestBody->ioCompleted = agTRUE; + return (status); + } + + return SM_RC_SUCCESS; +} + + +osGLOBAL FORCEINLINE bit32 +smsatIOPrepareSGL( + smRoot_t *smRoot, + smIORequestBody_t *smIORequestBody, + smSgl_t *smSgl1, + void *sglVirtualAddr + ) +{ + agsaSgl_t *agSgl; + + /* Uppper should be zero-out */ + SM_DBG5(("smsatIOPrepareSGL: start\n")); + + SM_DBG5(("smsatIOPrepareSGL: smSgl1->upper %d smSgl1->lower %d smSgl1->len %d\n", + smSgl1->upper, smSgl1->lower, smSgl1->len)); + SM_DBG5(("smsatIOPrepareSGL: smSgl1->type %d\n", smSgl1->type)); + + /* SGL for SATA request */ + agSgl = &(smIORequestBody->transport.SATA.agSATARequestBody.agSgl); + agSgl->len = 0; + + if (smSgl1 == agNULL) + { + SM_DBG1(("smsatIOPrepareSGL: Error smSgl1 is NULL!!!\n")); + return tiError; + } + + if (smIORequestBody->IOType.InitiatorRegIO.expDataLength == 0) + { + SM_DBG3(("smsatIOPrepareSGL: expDataLength is 0\n")); + agSgl->sgUpper = 0; + agSgl->sgLower = 0; + agSgl->len = 0; + SM_CLEAR_ESGL_EXTEND(agSgl->extReserved); + return SM_RC_SUCCESS; + } + + agSgl->sgUpper = smSgl1->upper; + agSgl->sgLower = smSgl1->lower; + agSgl->len = smSgl1->len; + agSgl->extReserved = smSgl1->type; + + return SM_RC_SUCCESS; + +} + + + + diff --git a/sys/dev/pms/RefTisa/sat/src/smtimer.c b/sys/dev/pms/RefTisa/sat/src/smtimer.c new file mode 100644 index 000000000000..ce6edd2e4a46 --- /dev/null +++ b/sys/dev/pms/RefTisa/sat/src/smtimer.c @@ -0,0 +1,161 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#include +#include + +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +osGLOBAL void +smTimerTick(smRoot_t *smRoot ) +{ + SM_DBG6(("smTimerTick: start\n")); + + smProcessTimers(smRoot); + + return; +} + +osGLOBAL void +smInitTimerRequest( + smRoot_t *smRoot, + smTimerRequest_t *timerRequest + ) +{ + timerRequest->timeout = 0; + timerRequest->timerCBFunc = agNULL; + timerRequest->timerData1 = agNULL; + timerRequest->timerData2 = agNULL; + timerRequest->timerData3 = agNULL; + SMLIST_INIT_ELEMENT((&timerRequest->timerLink)); +} + +osGLOBAL void +smSetTimerRequest( + smRoot_t *smRoot, + smTimerRequest_t *timerRequest, + bit32 timeout, + smTimerCBFunc_t CBFunc, + void *timerData1, + void *timerData2, + void *timerData3 + ) +{ + timerRequest->timeout = timeout; + timerRequest->timerCBFunc = CBFunc; + timerRequest->timerData1 = timerData1; + timerRequest->timerData2 = timerData2; + timerRequest->timerData3 = timerData3; +} + +osGLOBAL void +smAddTimer( + smRoot_t *smRoot, + smList_t *timerListHdr, + smTimerRequest_t *timerRequest + ) +{ + tdsmSingleThreadedEnter(smRoot, SM_TIMER_LOCK); + SMLIST_ENQUEUE_AT_TAIL(&(timerRequest->timerLink), timerListHdr); + timerRequest->timerRunning = agTRUE; + tdsmSingleThreadedLeave(smRoot, SM_TIMER_LOCK); +} + +osGLOBAL void +smKillTimer( + smRoot_t *smRoot, + smTimerRequest_t *timerRequest + ) +{ + tdsmSingleThreadedEnter(smRoot, SM_TIMER_LOCK); + timerRequest->timerRunning = agFALSE; + SMLIST_DEQUEUE_THIS(&(timerRequest->timerLink)); + tdsmSingleThreadedLeave(smRoot, SM_TIMER_LOCK); +} + +osGLOBAL void +smProcessTimers( + smRoot_t *smRoot + ) +{ + smIntRoot_t *smIntRoot = (smIntRoot_t *)smRoot->smData; + smIntContext_t *smAllShared = (smIntContext_t *)&smIntRoot->smAllShared; + smTimerRequest_t *timerRequest_to_process = agNULL; + smList_t *timerlist_to_process, *nexttimerlist = agNULL; + + + timerlist_to_process = &smAllShared->timerlist; + + timerlist_to_process = timerlist_to_process->flink; + + while ((timerlist_to_process != agNULL) && (timerlist_to_process != &smAllShared->timerlist)) + { + nexttimerlist = timerlist_to_process->flink; + + tdsmSingleThreadedEnter(smRoot, SM_TIMER_LOCK); + timerRequest_to_process = SMLIST_OBJECT_BASE(smTimerRequest_t, timerLink, timerlist_to_process); + tdsmSingleThreadedLeave(smRoot, SM_TIMER_LOCK); + + if (timerRequest_to_process == agNULL) + { + SM_DBG1(("smProcessTimers: timerRequest_to_process is NULL! Error!!!\n")); + return; + } + + timerRequest_to_process->timeout--; + + if (timerRequest_to_process->timeout == 0) + { + timerRequest_to_process->timerRunning = agFALSE; + + tdsmSingleThreadedEnter(smRoot, SM_TIMER_LOCK); + SMLIST_DEQUEUE_THIS(timerlist_to_process); + tdsmSingleThreadedLeave(smRoot, SM_TIMER_LOCK); + /* calling call back function */ + (timerRequest_to_process->timerCBFunc)(smRoot, + timerRequest_to_process->timerData1, + timerRequest_to_process->timerData2, + timerRequest_to_process->timerData3 + ); + } + timerlist_to_process = nexttimerlist; + } + + return; +} + diff --git a/sys/dev/pms/RefTisa/sat/src/smtypes.h b/sys/dev/pms/RefTisa/sat/src/smtypes.h new file mode 100644 index 000000000000..ee07b1ce2cf1 --- /dev/null +++ b/sys/dev/pms/RefTisa/sat/src/smtypes.h @@ -0,0 +1,359 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +#ifndef __SMTYPES_H__ +#define __SMTYPES_H__ + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include + +/* + * SAT specific structure per SATA drive + */ +#define SAT_NONNCQ_MAX 1 +#define SAT_NCQ_MAX 32 +#define SAT_MAX_INT_IO 16 +#define SAT_APAPI_CMDQ_MAX 2 + +/* SMP direct payload size limit: IOMB direct payload size = 48 */ +#define SMP_DIRECT_PAYLOAD_LIMIT 44 + +/* timer functions ; both I and T */ +typedef void (*smTimerCBFunc_t)(smRoot_t *smRoot, void *timerData1, void *timerData2, void *timerData3); + + +/** \brief data structure for timer request + * Timer requests are enqueued and dequeued using smList_t + * and have a callback function + */ +typedef struct smTimerRequest_s { + /* the number of ticks */ + bit32 timeout; + void *timerData1; + void *timerData2; + void *timerData3; + smTimerCBFunc_t timerCBFunc; + smList_t timerLink; + bit32 timerRunning; +} smTimerRequest_t; + + + +typedef struct smSatInternalIo_s +{ + smList_t satIntIoLink; + smIORequest_t satIntSmIORequest; /* old satIntTiIORequest */ + void *satIntRequestBody; /* maps to smIOrequestBody */ + smScsiInitiatorRequest_t satIntSmScsiXchg; /* old satIntTiScsiXchg*/ + smMem_t satIntDmaMem; + smMem_t satIntReqBodyMem; + bit32 satIntFlag; + smIORequest_t *satOrgSmIORequest; /* old satOrgTiIORequest */ + bit32 id; +} smSatInternalIo_t; + + + +typedef struct smDeviceData_s { + smList_t FreeLink; /* free dev list */ + smList_t MainLink; /* main(in use) dev list */ + bit32 id; /* for debugging only */ + smRoot_t *smRoot; + agsaDevHandle_t *agDevHandle; + bit32 valid; /* valid or registered */ + smTimerRequest_t SATAIDDeviceTimer; /* ID Device Data timer for SATA device */ + bit32 SMAbortAll; /* flag for abortall case */ + smDeviceHandle_t *smDevHandle; + bit32 directlyAttached; + agsaDevHandle_t *agExpDevHandle; /* expander a device is attached to if expander attached */ + bit32 phyID; + agsaContext_t agDeviceResetContext; /* used in saLocalPhyControl() */ + bit32 SMNumOfFCA; + + /* from satDeviceData_t */ + smList_t satIoLinkList; /* Normal I/O from TISA */ + smList_t satFreeIntIoLinkList; /* SAT internal I/O free list */ + smList_t satActiveIntIoLinkList; /* SAT internal I/O active list */ + smSatInternalIo_t satIntIo[SAT_MAX_INT_IO]; /* Internal I/O resource */ + agsaSATAIdentifyData_t satIdentifyData; /* Copy of SATA Id Dev data */ + bit32 satNCQ; /* Flag for NCQ support */ + bit32 sat48BitSupport; /* Flag for 48-bit addressing */ + bit32 satSMARTSelfTest; /* Flag for SMART self test */ + bit32 satSMARTFeatureSet; /* Flag for SMART feature set */ + bit32 satSMARTEnabled; /* Flag for SMART enabled */ + bit32 satRemovableMedia; /* Flag for Removable Media */ + bit32 satRemovableMediaEnabled; /* Flag for Removable Media Enabled */ + bit32 satDMASupport; /* Flag for DMA Support */ + bit32 satDMAEnabled; /* Flag for DMA Enabled */ + bit32 satUltraDMAMode; /* Ultra DMA mode value */ + bit32 satDMADIRSupport; /* Flag for DMA direction */ + bit32 satReadLookAheadSupport; /* Flag for Read Look Ahead */ + bit32 satVolatileWriteCacheSupport; /* Flag for Volatile Write Cache support*/ + bit32 satWWNSupport; /* Flag for DMA Enabled */ + bit32 satDMASetupAA; /* Flag for DMA Setup Auto-Activate */ + bit32 satNCQQMgntCmd; /* Flag for NCQ Queue Management Command */ + bit32 volatile satPendingIO; /* Number of pending I/O */ + bit32 volatile satPendingNCQIO; /* Number of pending NCQ I/O */ + bit32 volatile satPendingNONNCQIO; /* Number of pending NON NCW I/O*/ + bit32 satNCQMaxIO; /* Max NCQ I/O in SAT or drive */ + bit32 satDriveState; /* State of SAT/drive */ + bit32 satAbortAfterReset; /* Flag: abort after SATA reset */ + bit32 satAbortCalled; /* Flag: abort called indication*/ + bit32 satVerifyState; /* Flag: Read Vrf state for diag*/ + bit32 satMaxUserAddrSectors; /* max user addressable setctors*/ + bit32 satWriteCacheEnabled; /* Flag for write cache enabled */ + bit32 satLookAheadEnabled; /* Flag for look ahead enabled */ + bit32 satDeviceFaultState; /* State of DF */ + bit32 satStopState; /* State of Start and Stop */ + bit32 satFormatState; /* State of format */ + bit32 satPMField; /* PM field, first 4 bits */ + bit8 satSignature[8]; /* Signature */ + bit32 satDeviceType; /* ATA device type */ + bit32 satSectorDone; /* Number of Sector done by Cmnd*/ + bit32 freeSATAFDMATagBitmap; /* SATA NCQ tag bit map */ + bit32 IDDeviceValid; /* ID DeviceData valid bit */ + bit8 satMaxLBA[8]; /* MAXLBA is from read capacity */ + bit32 satBGPendingDiag; /* Pending Diagnostic in backgound */ + bit32 NumOfFCA; /* number of SMP HARD RESET on this device */ + bit32 NumOfIDRetries; /* number of SMP HARD RESET after ID retries */ + smIORequest_t *satTmTaskTag; /* TM Task Tag */ + void *satSaDeviceData; /* Pointer back to sa dev data */ + bit32 ID_Retries; /* identify device data retries */ + bit32 OSAbortAll; /* OS calls abort all */ + bit32 ReadCapacity; /* Read Capacity Type; 10, 16 */ + bit32 sasAddressLo; /**< HOST SAS address lower part */ + bit32 sasAddressHi; /**< HOST SAS address higher part */ + +} smDeviceData_t; + +typedef struct smAtaPassThroughHdr_s +{ + bit8 opc; + bit8 mulCount : 3; + bit8 proto : 4; + bit8 extend : 1; + bit8 offline : 2; + bit8 ckCond : 1; + bit8 tType : 1; + bit8 tDir : 1; + bit8 byteBlock : 1; + bit8 tlength : 2; + +}smAtaPassThroughHdr_t; + +/* + * SCSI Sense Data + */ +typedef struct +{ + bit8 snsRespCode; + bit8 snsSegment; + bit8 senseKey; /* sense key */ + bit8 info[4]; + bit8 addSenseLen; /* 11 always */ + bit8 cmdSpecific[4]; + bit8 addSenseCode; /* additional sense code */ + bit8 senseQual; /* additional sense code qualifier */ + bit8 fru; + bit8 skeySpecific[3]; +} smScsiRspSense_t; + + +/* + * SATA SAT specific function pointer for SATA completion for SAT commands. + */ +typedef void (*smSatCompleteCbPtr_t )( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *satIOContext + ); + +/* for SMP only */ +typedef void (*smSMPCompleted_t)( + agsaRoot_t *, + agsaIORequest_t *, + bit32 , + bit32 , + agsaFrameHandle_t + ); + + +/* + * SATA SAT specific function for I/O context + */ +typedef struct smSatIOContext_s +{ + smList_t satIoContextLink; + smDeviceData_t *pSatDevData; + agsaFisRegHostToDevice_t *pFis; + smIniScsiCmnd_t *pScsiCmnd; + smScsiRspSense_t *pSense; + smSenseData_t *pSmSenseData; /* old pTiSenseData */ + void *smRequestBody; /* smIORequestBody_t; old tiRequestBody*/ + void *smScsiXchg; /* for writesame10(); old tiScsiXchg */ + bit32 reqType; + bit32 interruptContext; + smSatCompleteCbPtr_t satCompleteCB; + smSatInternalIo_t *satIntIoContext; /* SATM generated IOs */ + smDeviceHandle_t *psmDeviceHandle; /* old ptiDeviceHandle */ + bit8 sataTag; + bit8 superIOFlag;/* Flag indicating type for smScsiXchg */ + bit8 reserved1; /* Padding for allignment */ + bit8 reserved2; /* Padding for allignment */ + bit32 currentLBA; /* current LBA for read and write */ + bit32 ATACmd; /* ATA command */ + bit32 OrgTL; /* original tranfer length(tl) */ + bit32 LoopNum; /* denominator tl */ + bit32 LoopNum2; /* denominator tl */ + bit8 LBA[8]; /* for reassign blocks; current LBA */ + bit32 ParmIndex; /* for reassign blocks;current idx in defective LBA LIST */ + bit32 ParmLen; /* for reassign blocks; defective LBA list length */ + bit32 NotifyOS; /* only for task management */ + bit32 TMF; /* task management function */ + struct smSatIOContext_s *satToBeAbortedIOContext; + struct smSatIOContext_s *satOrgIOContext; + bit32 UpperAddr; + bit32 LowerAddr; + bit32 SplitIdx; + bit32 AdjustBytes; + bit32 EsglLen; + /* For the SAT Passthrough */ + bit8 ck_cond; + bit8 extend; + bit8 sectorCnt07; + bit8 LBAHigh07; + bit8 LBAMid07; + bit8 LBALow07; + bit8 Sector_Cnt_Upper_Nonzero; + bit8 LBA_Upper_Nonzero; + bit32 pid; /* port id; used to protect double completion */ + bit32 id; /* for debugging */ +} smSatIOContext_t; + +typedef struct smIORequestBody_s { + smList_t satIoBodyLink; + smDeviceHandle_t *smDevHandle; + smIORequest_t *smIORequest; + agsaIORequest_t agIORequest; + smIORequest_t *smIOToBeAbortedRequest; /* IO to be aborted; old tiIOToBeAbortedRequest */ + bit32 id; + bit32 InUse; + union { + struct { + agsaSATAInitiatorRequest_t agSATARequestBody; + smScsiRspSense_t sensePayload; + smSenseData_t smSenseData; /* old tiSenseData */ + smSatIOContext_t satIOContext; + } SATA; + } transport; + bit32 ioStarted; + bit32 ioCompleted; + bit32 reTries; + union { + struct { + bit32 expDataLength; + smSgl_t smSgl1; /* old tiSgl1 */ + smSgl_t smSgl2; /* old tiSgl2 */ + void *sglVirtualAddr; + } InitiatorRegIO; /* regular IO */ + struct { + void *osMemHandle; + smIORequest_t *CurrentTaskTag; + smIORequest_t *TaskTag; + } InitiatorTMIO; /* task management */ + } IOType; + +} smIORequestBody_t; + +typedef struct smSMPRequestBody_s { + smSMPCompleted_t SMPCompletionFunc;/* must be the second */ + + smDeviceHandle_t *smDevHandle; /* not used for SM generated SMP */ + agsaIORequest_t agIORequest; + agsaSASRequestBody_t agSASRequestBody; + void *osMemHandle; + smDeviceData_t *smDeviceData; + smIORequest_t *CurrentTaskTag; /* SMP is used for simulate target reset */ +// tdsaPortContext_t *tdPortContext; /* portcontext where SMP is sent from */ + bit8 smpPayload[SMP_DIRECT_PAYLOAD_LIMIT]; /* for smp retries; + only for direct SMP */ + bit32 retries; /* number of retries */ + +} smSMPRequestBody_t; + + +typedef struct smRootOsData_s { + smRoot_t *smRoot; /**< Pointer back to smRoot */ + void *smAllShared; /**< Pointer to smIntContext_t */ + void *smIni; /**< Pointer to SAS/SATA initiator */ +} smRootOsData_t; + +typedef struct smIntContext_s { + /**< agsaRoot_t->osData points to this */ + struct smRootOsData_s smRootOsData; + + bit32 usecsPerTick; + agsaRoot_t *agRoot; + + /**< software-related initialization params used in saInitialize() */ + smSwConfig_t SwConfig; + + /**< timers used commonly in SAS/SATA */ + smList_t timerlist; + + /**< pointer to Device memory */ + smDeviceData_t *DeviceMem; + smList_t FreeDeviceList; + smList_t MainDeviceList; + + /**< pointer to IO memory */ + smIORequestBody_t *IOMem; + smList_t freeIOList; + smList_t mainIOList; + bit32 FCA; +} smIntContext_t; + +typedef struct smIntRoot_s +{ + /**<< common data structure for SAS/SATA */ + smIntContext_t smAllShared; +} smIntRoot_t; + + +#endif /* __SMTYPES_H__ */ + diff --git a/sys/dev/pms/RefTisa/tisa/api/ostiapi.h b/sys/dev/pms/RefTisa/tisa/api/ostiapi.h new file mode 100644 index 000000000000..00c3f4677a0b --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/api/ostiapi.h @@ -0,0 +1,487 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/******************************************************************************** +** +** Version Control Information: +** +** +*******************************************************************************/ +/******************************************************************************** +** +** ostiapi.h +** +** Abstract: This module contains function prototype of the Transport +** Independent (TIAPI) OS Callback interface. +** +********************************************************************************/ + +#ifndef OSTIAPI_H + +#define OSTIAPI_H + +/* + * Definition for return status is defined in tiStatus_t in TIDEFS.H + */ + +/***************************************************************************** + * Initiator/Target Shared Callbacks + *****************************************************************************/ + +osGLOBAL bit32 ostiGetTransportParam( + tiRoot_t *tiRoot, + char *key, + char *subkey1, + char *subkey2, + char *subkey3, + char *subkey4, + char *subkey5, + char *valueName, + char *buffer, + bit32 bufferLen, + bit32 *lenReceived + ); + +osGLOBAL void ostiPortEvent( + tiRoot_t *tiRoot, + tiPortEvent_t eventType, + bit32 status, + void *pParm + ); + +osGLOBAL bit32 ostiTimeStamp( tiRoot_t *tiRoot); +osGLOBAL bit64 ostiTimeStamp64( tiRoot_t *tiRoot); + +osGLOBAL FORCEINLINE bit32 ostiChipConfigReadBit32( + tiRoot_t *tiRoot, + bit32 chipConfigOffset + ); + +osGLOBAL FORCEINLINE void ostiChipConfigWriteBit32( + tiRoot_t *tiRoot, + bit32 chipConfigOffset, + bit32 chipConfigValue + ); + +osGLOBAL FORCEINLINE bit32 ostiChipReadBit32( + tiRoot_t *tiRoot, + bit32 chipOffset + ); + +osGLOBAL FORCEINLINE void ostiChipWriteBit32( + tiRoot_t *tiRoot, + bit32 chipOffset, + bit32 chipValue + ); + +osGLOBAL FORCEINLINE bit8 ostiChipReadBit8( + tiRoot_t *tiRoot, + bit32 chipOffset + ); + +osGLOBAL FORCEINLINE void ostiChipWriteBit8( + tiRoot_t *tiRoot, + bit32 chipOffset, + bit8 chipValue + ); + +osGLOBAL void ostiFlashReadBlock( + tiRoot_t *tiRoot, + bit32 flashOffset, + void *buffer, + bit32 bufferLen + ); + +osGLOBAL FORCEINLINE +tiDeviceHandle_t* +ostiGetDevHandleFromSasAddr( + tiRoot_t *root, + unsigned char *sas_addr +); + +osGLOBAL FORCEINLINE void ostidisableEncryption(tiRoot_t *root); + +osGLOBAL FORCEINLINE void ostiSingleThreadedEnter( + tiRoot_t *tiRoot, + bit32 queueId + ); + +osGLOBAL FORCEINLINE void ostiSingleThreadedLeave( + tiRoot_t *tiRoot, + bit32 queueId + ); + + +osGLOBAL bit32 ostiNumOfLUNIOCTLreq(tiRoot_t *root, + void *param1, + void *param2, + void **tiRequestBody, + tiIORequest_t **tiIORequest + ); + +#ifdef PERF_COUNT +osGLOBAL void ostiEnter(tiRoot_t *ptiRoot, bit32 layer, int io); +osGLOBAL void ostiLeave(tiRoot_t *ptiRoot, bit32 layer, int io); +#define OSTI_INP_ENTER(root) ostiEnter(root, 2, 0) +#define OSTI_INP_LEAVE(root) ostiLeave(root, 2, 0) +#define OSTI_OUT_ENTER(root) ostiEnter(root, 2, 1) +#define OSTI_OUT_LEAVE(root) ostiLeave(root, 2, 1) +#else +#define OSTI_INP_ENTER(root) +#define OSTI_INP_LEAVE(root) +#define OSTI_OUT_ENTER(root) +#define OSTI_OUT_LEAVE(root) +#endif + +osGLOBAL void ostiStallThread( + tiRoot_t *tiRoot, + bit32 microseconds + ); + +osGLOBAL FORCEINLINE bit8 +ostiBitScanForward( + tiRoot_t *root, + bit32 *Index, + bit32 Mask + ); + +#ifdef LINUX_VERSION_CODE + +osGLOBAL sbit32 +ostiAtomicIncrement( + tiRoot_t *root, + sbit32 volatile *Addend + ); + +osGLOBAL sbit32 +ostiAtomicDecrement( + tiRoot_t *root, + sbit32 volatile *Addend + ); + + +osGLOBAL sbit32 +ostiAtomicBitClear( + tiRoot_t *root, + sbit32 volatile *Destination, + sbit32 Value + ); + +osGLOBAL sbit32 +ostiAtomicBitSet( + tiRoot_t *root, + sbit32 volatile *Destination, + sbit32 Value + ); + +osGLOBAL sbit32 +ostiAtomicExchange( + tiRoot_t *root, + sbit32 volatile *Target, + sbit32 Value + ); + +#else + +osGLOBAL FORCEINLINE sbit32 +ostiInterlockedIncrement( + tiRoot_t *root, + sbit32 volatile *Addend + ); + +osGLOBAL FORCEINLINE sbit32 +ostiInterlockedDecrement( + tiRoot_t *root, + sbit32 volatile *Addend + ); + + +osGLOBAL FORCEINLINE sbit32 +ostiInterlockedAnd( + tiRoot_t *root, + sbit32 volatile *Destination, + sbit32 Value + ); + +osGLOBAL FORCEINLINE sbit32 +ostiInterlockedOr( + tiRoot_t *root, + sbit32 volatile *Destination, + sbit32 Value + ); + +osGLOBAL FORCEINLINE sbit32 +ostiInterlockedExchange( + tiRoot_t *root, + sbit32 volatile *Target, + sbit32 Value + ); +#endif /*LINUX_VERSION_CODE*/ + +osGLOBAL bit32 ostiAllocMemory( + tiRoot_t *tiRoot, + void **osMemHandle, + void ** virtPtr, + bit32 * physAddrUpper, + bit32 * physAddrLower, + bit32 alignment, + bit32 allocLength, + agBOOLEAN isCacheable + ); + +osGLOBAL bit32 ostiFreeMemory( + tiRoot_t *tiRoot, + void *osDMAHandle, + bit32 allocLength + ); + +osGLOBAL FORCEINLINE void ostiCacheFlush( + tiRoot_t *tiRoot, + void *osMemHandle, + void *virtPtr, + bit32 length + ); + +osGLOBAL FORCEINLINE void ostiCacheInvalidate( + tiRoot_t *tiRoot, + void *osMemHandle, + void *virtPtr, + bit32 length + ); + +osGLOBAL FORCEINLINE void ostiCachePreFlush( + tiRoot_t *tiRoot, + void *osMemHandle, + void *virtPtr, + bit32 length + ); + +/* + * The following two functions are for SAS/SATA + */ +osGLOBAL void +ostiInterruptEnable( + tiRoot_t *ptiRoot, + bit32 channelNum + ); + +osGLOBAL void +ostiInterruptDisable( + tiRoot_t *ptiRoot, + bit32 channelNum + ); + +osGLOBAL FORCEINLINE bit32 +ostiChipReadBit32Ext( + tiRoot_t *tiRoot, + bit32 busBaseNumber, + bit32 chipOffset + ); + +osGLOBAL FORCEINLINE void +ostiChipWriteBit32Ext( + tiRoot_t *tiRoot, + bit32 busBaseNumber, + bit32 chipOffset, + bit32 chipValue + ); + + +/***************************************************************************** + * Initiator specific Callbacks + *****************************************************************************/ + +/* + * Initiator specific IO Completion + */ +osGLOBAL void ostiInitiatorIOCompleted( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiIOStatus_t status, + bit32 statusDetail, + tiSenseData_t *senseData, + bit32 context + ); + +osGLOBAL tiDeviceHandle_t* +ostiMapToDevHandle(tiRoot_t *root, + bit8 pathId, + bit8 targetId, + bit8 LUN + ); +osGLOBAL bit32 ostiSendResetDeviceIoctl(tiRoot_t *root, + void *pccb, + bit8 pathId, + bit8 targetId, + bit8 lun, + unsigned long resetType + ); + +osGLOBAL void +ostiGetSenseKeyCount(tiRoot_t *root, + bit32 fIsClear, + void *SenseKeyCount, + bit32 length + ); + +osGLOBAL void +ostiGetSCSIStatusCount(tiRoot_t *root, + bit32 fIsClear, + void *ScsiStatusCount, + bit32 length + ); + +osGLOBAL bit32 +ostiSetDeviceQueueDepth(tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + bit32 QueueDepth + ); + + +#ifdef FAST_IO_TEST +typedef void (*ostiFastSSPCb_t)(tiRoot_t *ptiRoot, + void *arg, + tiIOStatus_t IOStatus, + bit32 statusDetail); + +void osti_FastIOCb(tiRoot_t *ptiRoot, + void *arg, + tiIOStatus_t IOStatus, + bit32 statusDetail); +#endif + +osGLOBAL void +ostiInitiatorSMPCompleted(tiRoot_t *tiRoot, + tiIORequest_t *tiSMPRequest, + tiSMPStatus_t smpStatus, + bit32 tiSMPInfoLen, + void *tiFrameHandle, + bit32 context); +/* + * Initiator specific event + */ +osGLOBAL void ostiInitiatorEvent ( + tiRoot_t *tiRoot, + tiPortalContext_t *portalContext, + tiDeviceHandle_t *tiDeviceHandle, + tiIntrEventType_t eventType, + bit32 eventStatus, + void *parm + ); + + +/* + * PMC-Sierra IOCTL semaphoring + */ +osGLOBAL void ostiIOCTLClearSignal ( + tiRoot_t *tiRoot, + void **agParam1, + void **agParam2, + void **agParam3 + ); + +osGLOBAL void ostiIOCTLWaitForSignal ( + tiRoot_t *tigRoot, + void *agParam1, + void *agParam2, + void *agParam3 + ); + +osGLOBAL void ostiIOCTLSetSignal ( + tiRoot_t *tiRoot, + void *agParam1, + void *agParam2, + void *agParam3 + ); + +osGLOBAL void ostiIOCTLWaitForComplete ( + tiRoot_t *tigRoot, + void *agParam1, + void *agParam2, + void *agParam3 + ); + +osGLOBAL void ostiIOCTLComplete ( + tiRoot_t *tiRoot, + void *agParam1, + void *agParam2, + void *agParam3 + ); + +/***************************************************************************** + * Target specific Callbacks + *****************************************************************************/ + +osGLOBAL void ostiProcessScsiReq( + tiRoot_t *tiRoot, + tiTargetScsiCmnd_t *tiTgtScsiCmnd, + void *agFrameHandle, + bit32 immDataLength, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle); + +osGLOBAL void ostiNextDataPhase( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest); + +osGLOBAL void ostiTaskManagement ( + tiRoot_t *tiRoot, + bit32 task, + bit8 *scsiLun, + tiIORequest_t *refTiIORequest, + tiIORequest_t *tiTMRequest, + tiDeviceHandle_t *tiDeviceHandle); + +osGLOBAL void ostiTargetIOCompleted( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiIOStatus_t status + ); + +osGLOBAL bit32 ostiTargetEvent ( + tiRoot_t *tiRoot, + tiPortalContext_t *portalContext, + tiDeviceHandle_t *tiDeviceHandle, + tiTgtEventType_t eventType, + bit32 eventStatus, + void *parm + ); + +osGLOBAL void ostiTargetIOError( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiIOStatus_t status, + bit32 statusDetail + ); + +osGLOBAL void ostiTargetTmCompleted( + tiRoot_t *tiRoot, + tiIORequest_t *tiTmRequest, + tiIOStatus_t status, + bit32 statusDetail + ); + +osGLOBAL void ostiPCI_TRIGGER( tiRoot_t *tiRoot ); + + +#endif /* OSTIAPI_H */ diff --git a/sys/dev/pms/RefTisa/tisa/api/tiapi.h b/sys/dev/pms/RefTisa/tisa/api/tiapi.h new file mode 100644 index 000000000000..10550d2cc047 --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/api/tiapi.h @@ -0,0 +1,586 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/******************************************************************************** +* tiapi.h +* +* Abstract: This module contains function prototype of the Transport +* Independent API (TIAPI) Layer for both initiator and target. +** Version Control Information: +** +** +*******************************************************************************/ + + +#ifndef TIAPI_H +#define TIAPI_H + +#include +#include + +/***************************************************************************** + * INITIATOR/TARGET SHARED APIs + *****************************************************************************/ + +osGLOBAL void tiCOMGetResource ( + tiRoot_t *tiRoot, + tiLoLevelResource_t *loResource, + tiInitiatorResource_t *initiatorResource, + tiTargetResource_t *targetResource, + tiTdSharedMem_t *tdSharedMem + ); + +osGLOBAL bit32 tiCOMInit( + tiRoot_t *tiRoot, + tiLoLevelResource_t *loResource, + tiInitiatorResource_t *initiatorResource, + tiTargetResource_t *targetResource, + tiTdSharedMem_t *tdSharedMem + ); + +osGLOBAL bit32 tiCOMPortInit( + tiRoot_t *tiRoot, + bit32 sysIntsActive + ); + +osGLOBAL bit32 tiCOMPortStart( + tiRoot_t *tiRoot, + bit32 portID, + tiPortalContext_t *portalContext, + bit32 option + ); + +osGLOBAL void tiCOMShutDown( tiRoot_t *tiRoot); + +osGLOBAL bit32 tiCOMPortStop( + tiRoot_t *tiRoot, + tiPortalContext_t *portalContext + ); + +osGLOBAL void tiCOMReset ( + tiRoot_t *tiRoot, + bit32 option + ); + +osGLOBAL bit32 +tdsaGetNumOfLUNIOCTL( + tiRoot_t *tiRoot, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2, + void *agParam3 + ); + +osGLOBAL void ostiNumOfLUNIOCTLRsp( + tiRoot_t *tiRoot, + bit32 status + ); +osGLOBAL bit32 +tiNumOfLunIOCTLreq( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + void *tiRequestBody, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2 + ); + + +osGLOBAL FORCEINLINE bit32 tiCOMInterruptHandler( + tiRoot_t *tiRoot, + bit32 channelNum + ); + +osGLOBAL FORCEINLINE bit32 tiCOMDelayedInterruptHandler ( + tiRoot_t *tiRoot, + bit32 channelNum, + bit32 count, + bit32 context + ); + +osGLOBAL bit32 tiCOMLegacyInterruptHandler( + tiRoot_t *tiRoot, + bit32 channelNum + ); + + +osGLOBAL void tiCOMLegacyDelayedInterruptHandler( + tiRoot_t *tiRoot, + bit32 channelNum, + bit32 count, + bit32 context + ); +osGLOBAL void tiCOMTimerTick( tiRoot_t *tiRoot ); + +osGLOBAL void tiCOMSystemInterruptsActive ( + tiRoot_t *tiRoot , + bit32 sysIntsActive + ); + + +osGLOBAL FORCEINLINE void +tiCOMInterruptEnable( + tiRoot_t * tiRoot, + bit32 channelNum); + +osGLOBAL void tiCOMFrameReadBlock( + tiRoot_t *tiRoot, + void *agFrame, + bit32 FrameOffset, + void *FrameBuffer, + bit32 FrameBufLen ); +osGLOBAL bit32 tiCOMEncryptGetInfo( + tiRoot_t *tiRoot); + +osGLOBAL bit32 tiCOMEncryptSetMode( + tiRoot_t *tiRoot, + bit32 securityCipherMode + ); + +osGLOBAL bit32 tiCOMSetControllerConfig ( + tiRoot_t *tiRoot, + bit32 modePage, + bit32 length, + void *buffer, + void *context + ); + +osGLOBAL bit32 tiCOMGetControllerConfig( + tiRoot_t *tiRoot, + bit32 modePage, + bit32 flag, + void *context + ); + + +osGLOBAL bit32 tiCOMEncryptDekAdd( + tiRoot_t *tiRoot, + bit32 kekIndex, + bit32 dekTableSelect, + bit32 dekAddrHi, + bit32 dekAddrLo, + bit32 dekIndex, + bit32 dekNumberOfEntries, + bit32 dekBlobFormat, + bit32 dekTableKeyEntrySize + ); + +osGLOBAL bit32 tiCOMEncryptDekInvalidate( + tiRoot_t *tiRoot, + bit32 dekTable, + bit32 dekIndex + ); + + +osGLOBAL bit32 tiCOMEncryptKekAdd( + tiRoot_t *tiRoot, + bit32 kekIndex, + bit32 wrapperKekIndex, + bit32 blobFormat, + tiEncryptKekBlob_t *encryptKekBlob + ); + +osGLOBAL tiDeviceHandle_t * +tiINIGetExpDeviceHandleBySasAddress( + tiRoot_t * tiRoot, + tiPortalContext_t * tiPortalContext, + bit32 sas_addr_hi, + bit32 sas_addr_lo, + bit32 maxDevs + ); + + +#ifdef HIALEAH_ENCRYPTION +osGLOBAL bit32 tiCOMEncryptHilSet(tiRoot_t *tiRoot ); +#endif /* HIALEAH_ENCRYPTION */ + +osGLOBAL bit32 tiCOMEncryptKekStore( + tiRoot_t *tiRoot, + bit32 kekIndex + ); + +osGLOBAL bit32 tiCOMEncryptKekLoad( + tiRoot_t *tiRoot, + bit32 kekIndex + ); + +osGLOBAL bit32 tiCOMEncryptSelfTest( + tiRoot_t *tiRoot, + bit32 type, + bit32 length, + void *TestDescriptor + ); + +osGLOBAL bit32 tiCOMSetOperator( + tiRoot_t *tiRoot, + bit32 flag, + void *cert + ); + +osGLOBAL bit32 tiCOMGetOperator( + tiRoot_t *tiRoot, + bit32 option, + bit32 AddrHi, + bit32 AddrLo + ); + +osGLOBAL bit32 tiCOMOperatorManagement( + tiRoot_t *tiRoot, + bit32 flag, + bit8 role, + tiID_t *idString, + tiEncryptKekBlob_t *kekBlob + ); + +/* + * PMC-Sierra Management IOCTL module + */ +osGLOBAL bit32 tiCOMMgntIOCTL( + tiRoot_t *tiRoot, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2, + void *agParam3 + ); + +osGLOBAL void ostiCOMMgntIOCTLRsp( + tiRoot_t *tiRoot, + bit32 status + ); + +osGLOBAL void ostiRegDumpIOCTLRsp( + tiRoot_t *tiRoot, + bit32 status + ); + +osGLOBAL void ostiSetNVMDIOCTLRsp( + tiRoot_t *tiRoot, + bit32 status + ); + +osGLOBAL void ostiGetPhyProfileIOCTLRsp( + tiRoot_t *tiRoot, + bit32 status + ); + +osGLOBAL void ostiGetNVMDIOCTLRsp( + tiRoot_t *tiRoot, + bit32 status + ); +osGLOBAL bit32 tiCOMGetPortInfo( + tiRoot_t *tiRoot, + tiPortalContext_t *portalContext, + tiPortInfo_t *tiPortInfo + ); + +osGLOBAL void ostiSendSMPIOCTLRsp( + tiRoot_t *tiRoot, + bit32 status + ); + +osGLOBAL void ostiGenEventIOCTLRsp( + tiRoot_t *tiRoot, + bit32 status + ); + +osGLOBAL void +ostiGetDeviceInfoIOCTLRsp( + tiRoot_t *tiRoot, + bit32 status, + void *param + ); + +osGLOBAL void +ostiGetIoErrorStatsIOCTLRsp( + tiRoot_t *tiRoot, + bit32 status, + void *param + ); + +osGLOBAL void +ostiGetIoEventStatsIOCTLRsp( + tiRoot_t *tiRoot, + bit32 status, + void *param + ); + +osGLOBAL void +ostiGetForensicDataIOCTLRsp( + tiRoot_t *tiRoot, + bit32 status, + void *param + ); + + +#ifdef SPC_ENABLE_PROFILE +osGLOBAL void ostiFWProfileIOCTLRsp( + tiRoot_t *tiRoot, + bit32 status, + bit32 len + ); +#endif + +/***************************************************************************** + * INITIATOR SPECIFIC APIs + *****************************************************************************/ + +/* + * Session management module. + */ +osGLOBAL bit32 tiINIGetExpander( + tiRoot_t * tiRoot, + tiPortalContext_t * tiPortalContext, + tiDeviceHandle_t * tiDev, + tiDeviceHandle_t ** tiExp + ); +osGLOBAL bit32 tiINIGetDeviceHandles( + tiRoot_t *tiRoot, + tiPortalContext_t *portalContext, + tiDeviceHandle_t *agDev[], + bit32 maxDevs + ); + +osGLOBAL bit32 tiINIGetDeviceHandlesForWinIOCTL( + tiRoot_t *tiRoot, + tiPortalContext_t *portalContext, + tiDeviceHandle_t *agDev[], + bit32 maxDevs + ); + +osGLOBAL void tiIniGetDirectSataSasAddr(tiRoot_t * tiRoot, bit32 phyId, bit8 **sasAddressHi, bit8 **sasAddressLo); +osGLOBAL bit32 tiINIDiscoverTargets( + tiRoot_t *tiRoot, + tiPortalContext_t *portalContext, + bit32 option + ); + +osGLOBAL bit32 tiINILogin( + tiRoot_t *tiRoot, + tiDeviceHandle_t *tiDeviceHandle + ); + +osGLOBAL bit32 tiINILogout( + tiRoot_t *tiRoot, + tiDeviceHandle_t *tiDeviceHandle + ); + +osGLOBAL bit32 tiINIGetDeviceInfo( + tiRoot_t *tiRoot, + tiDeviceHandle_t *tiDeviceHandle, + tiDeviceInfo_t *tiDeviceInfo); + +/* + * Transport recovery module. + */ +osGLOBAL void tiINITransportRecovery( + tiRoot_t *tiRoot, + tiDeviceHandle_t *tiDeviceHandle + ); + +osGLOBAL bit32 tiINITaskManagement ( + tiRoot_t *tiRoot, + tiDeviceHandle_t *tiDeviceHandle, + bit32 task, + tiLUN_t *lun, + tiIORequest_t *taskTag, + tiIORequest_t *currentTaskTag + ); +osGLOBAL bit32 tiINISMPStart( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiSMPFrame_t *tiScsiRequest, + void *tiSMPBody, + bit32 interruptContext + ); +/* + * I/O module. + */ +osGLOBAL bit32 tiINIIOStart( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + void *tiRequestBody, + bit32 interruptContext + ); + +osGLOBAL void tiINIDebugDumpIO( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest + ); + +osGLOBAL bit32 tiINIIOStartDif( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + void *tiRequestBody, + bit32 interruptContext, + tiDif_t *difOption + ); +osGLOBAL bit32 tiINISuperIOStart ( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiSuperScsiInitiatorRequest_t *tiScsiRequest, + void *tiRequestBody, + bit32 interruptContext + ); + +#ifdef FAST_IO_TEST +osGLOBAL void *tiINIFastIOPrepare( + tiRoot_t *tiRoot, + void *ioHandle, + agsaFastCommand_t *fc); + +osGLOBAL void* +tiINIFastIOPrepare2( + tiRoot_t *tiRoot, + void *ioHandle, + agsaFastCommand_t *fc, + void *pMessage, + void *pRequest); + +osGLOBAL bit32 tiINIFastIOSend(void *ioHandle); +osGLOBAL bit32 tiINIFastIOCancel(void *ioHandle); +#endif + +osGLOBAL bit32 tiCOMEncryptGetMode(tiRoot_t *tiRoot); +osGLOBAL bit32 tiCOMEncryptSetOn_Off(tiRoot_t *tiRoot, bit32 On); + +osGLOBAL bit32 tiInitDevEncrypt( + tiRoot_t *tiRoot, + void *tideviceptr ); + +osGLOBAL bit32 tiTGTSuperIOStart ( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiSuperScsiTargetRequest_t *tiScsiRequest + ); + +osGLOBAL void tiINITimerTick( + tiRoot_t *tiRoot + ); + + +osGLOBAL bit32 tiINIIOAbort( + tiRoot_t *tiRoot, + tiIORequest_t *taskTag + ); + +osGLOBAL bit32 tiINIIOAbortAll( + tiRoot_t *tiRoot, + tiDeviceHandle_t *tiDeviceHandle + ); +/* + * Event Logging module + */ +osGLOBAL bit32 tiINIReportErrorToEventLog( + tiRoot_t *tiRoot, + tiEVTData_t *agEventData + ); + + +/***************************************************************************** + * TARGET SPECIFIC APIs + *****************************************************************************/ + +osGLOBAL void tiTGTTimerTick( + tiRoot_t *tiRoot + ); + +osGLOBAL void *tiTGTSenseBufferGet( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + bit32 length + ); + +osGLOBAL void tiTGTSetResp( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + bit32 dataSentLength, + bit8 ScsiStatus, + bit32 senseLength + ); + +osGLOBAL bit32 tiTGTIOStart ( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + bit32 dataOffset, + bit32 dataLength, + tiSgl_t *dataSGL, + void *sglVirtualAddr + ); + +osGLOBAL bit32 tiTGTIOStartMirror ( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + bit32 dataOffset, + bit32 dataLength, + tiSgl_t *dataSGL, + void *sglVirtualAddr, + tiSgl_t *dataSGLMirror, + void *sglVirtualAddrMirror + ); + +osGLOBAL bit32 tiTGTIOStartDif ( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + bit32 dataOffset, + bit32 dataLength, + tiSgl_t *dataSGL, + void *sglVirtualAddr, + tiDif_t *difOption + ); + + +osGLOBAL bit32 tiTGTGetDeviceHandles( + tiRoot_t *tiRoot, + tiPortalContext_t *portalContext, + tiDeviceHandle_t *agDev[], + bit32 maxDevs + ); + +osGLOBAL bit32 tiTGTGetDeviceInfo( + tiRoot_t *tiRoot, + tiDeviceHandle_t *tiDeviceHandle, + tiDeviceInfo_t *tiDeviceInfo); + +osGLOBAL bit32 tiTGTIOAbort( + tiRoot_t *tiRoot, + tiIORequest_t *taskTag + ); + +osGLOBAL bit32 tiTGTSendTmResp ( + tiRoot_t *tiRoot, + tiIORequest_t *tiTMRequest, + bit32 status + ); + +void tiPCI_TRIGGER( tiRoot_t *tiRoot); + +void tiComCountActiveIORequests( tiRoot_t *tiRoot); + +#endif /* TIAPI_H */ diff --git a/sys/dev/pms/RefTisa/tisa/api/tidefs.h b/sys/dev/pms/RefTisa/tisa/api/tidefs.h new file mode 100644 index 000000000000..2e3dad2c98a9 --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/api/tidefs.h @@ -0,0 +1,610 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/******************************************************************************** +** +** Version Control Information: +** +** +*******************************************************************************/ +/******************************************************************************** +** +* tidefs.h +* +* Abstract: This module contains enum and #define definition used +* by Transport Independent API (TIAPI) Layer. +* +********************************************************************************/ + +#ifndef TIDEFS_H + +#define TIDEFS_H + +#include +#include +#include + +/***************************************************************************** + * INITIATOR/TARGET SHARED DEFINES AND ENUMS + *****************************************************************************/ + +/* + * Option mask parameter for tiCOMPortStart() + */ +#define PORTAL_ADD_MASK 0x00000001 + +/* + * Maximum memory descriptor for Low-Level layer. + */ +#define MAX_LL_LAYER_MEM_DESCRIPTORS 64 + + +/* + * TI API function return types + */ +typedef enum +{ + tiSuccess, + tiError, + tiBusy, + tiIONoDevice, + tiMemoryTooLarge, + tiMemoryNotAvail, + tiInvalidHandle, + tiNotSupported, + tiReject, + tiIncorrectLun, + tiDeviceBusy, +} tiStatus_t; + +/* + * Type of memory, OR-ed the bit fields. + */ + +/* Bit 0-1, cached or dma-uncached dma-cached */ + +#define TI_DMA_MEM 0x00000000 /* uncached DMA capable memory */ +#define TI_CACHED_MEM 0x00000001 /* cached non-DMA capable memory */ +#define TI_CACHED_DMA_MEM 0x00000002 /* cached DMA capable memory */ +#define TI_DMA_MEM_CHIP 0x00000003 /* Internal HW/chip memory */ + +/* Bit2-3: location of memory */ +#define TI_LOC_HOST 0x00000000 /* default, allocated from host */ +#define TI_LOC_ON_CHIP 0x00000004 /* memory is from on-chip RAM */ +#define TI_LOC_ON_CARD 0x00000008 /* memory is from on-card RAM */ + +/* Type of SGL list + * + */ +typedef enum +{ + tiSgl=0, + tiSglList=0x80000000, + tiExtHdr +}tiSglType_t; + +/* + * Type of mutex semaphoring/synchronization + */ +typedef enum +{ + tiSingleMutexLockPerPort, + tiOneMutexLockPerQueue +}tiMutexType_t; + +/* + * Context (interrupt or non-interrupt) + */ +typedef enum +{ + tiInterruptContext, + tiNonInterruptContext +}tiIntContextType_t; + +/* + * Port Event type. + */ +typedef enum +{ + tiPortPanic, + tiPortResetComplete, + tiPortNameServerDown, + tiPortLinkDown, + tiPortLinkUp, + tiPortStarted, + tiPortStopped, + tiPortShutdown, + tiPortDiscoveryReady, + tiPortResetNeeded, + tiEncryptOperation, + tiModePageOperation +} tiPortEvent_t; + +/* + * tiEncryptOperation Event types + */ +typedef enum +{ + tiEncryptGetInfo, + tiEncryptSetMode, + tiEncryptKekAdd, + tiEncryptDekInvalidate, + tiEncryptKekStore, + tiEncryptKekLoad, + tiEncryptAttribRegUpdate, + tiEncryptDekAdd, + /* new */ + tiEncryptOperatorManagement, + tiEncryptSelfTest, + tiEncryptSetOperator, + tiEncryptGetOperator +} tiEncryptOp_t; + +/* + * ostiPortEvent() status values for tiCOMOperatorManagement() + */ +typedef enum +{ + tiOMNotSupported, + tiOMIllegalParam, + tiOMKENUnwrapFail, + tiOMNvramOpFailure, +} tiOperatorManagementStatus_t; + +/* + * ostiInitiatorIOCompleted() and ostiTargetIOError() status values + */ +typedef enum +{ + tiIOSuccess, + tiIOOverRun, + tiIOUnderRun, + tiIOFailed, + tiIODifError, + tiIOEncryptError, +} tiIOStatus_t; + +/* + * ostiInitiatorIOCompleted() and ostiTargetIOError() statusDetail values + */ +typedef enum +{ + tiSMPSuccess, + tiSMPAborted, + tiSMPFailed, +} tiSMPStatus_t; + +typedef enum +{ + tiDetailBusy, + tiDetailNotValid, + tiDetailNoLogin, + tiDetailAbortLogin, + tiDetailAbortReset, + tiDetailAborted, + tiDetailDifMismatch, + tiDetailDifAppTagMismatch, + tiDetailDifRefTagMismatch, + tiDetailDifCrcMismatch, + tiDetailDekKeyCacheMiss, + tiDetailCipherModeInvalid, + tiDetailDekIVMismatch, + tiDetailDekRamInterfaceError, + tiDetailDekIndexOutofBounds, + tiDetailOtherError, + tiDetailOtherErrorNoRetry, +} tiIOStatusDetail_t; + +/* + * IOCTL Status Codes + */ +#define IOCTL_ERR_STATUS_OK 0x00 +#define IOCTL_ERR_STATUS_MORE_DATA 0x01 +#define IOCTL_ERR_STATUS_NO_MORE_DATA 0x02 +#define IOCTL_ERR_STATUS_INVALID_CODE 0x03 +#define IOCTL_ERR_STATUS_INVALID_DEVICE 0x04 +#define IOCTL_ERR_STATUS_NOT_RESPONDING 0x05 +#define IOCTL_ERR_STATUS_INTERNAL_ERROR 0x06 +#define IOCTL_ERR_STATUS_NOT_SUPPORTED 0x07 +#define IOCTL_ERR_FW_EVENTLOG_DISABLED 0x08 +#define IOCTL_MJ_FATAL_ERROR_SOFT_RESET_TRIG 0x72 +#define IOCTL_MJ_FATAL_ERR_CHK_SEND_TRUE 0x77 +#define IOCTL_MJ_FATAL_ERR_CHK_SEND_FALSE 0x76 +#define IOCTL_ERROR_NO_FATAL_ERROR 0x77 + +#define ADAPTER_WWN_START_OFFSET 0x804 +#define ADAPTER_WWN_END_OFFSET 0x80b +#define ADAPTER_WWN_SPC_START_OFFSET 0x704 +#define ADAPTER_WWN_SPC_END_OFFSET 0x70b + +/* + * IOCTL Return Codes + */ +#define IOCTL_CALL_SUCCESS 0x00 +#define IOCTL_CALL_FAIL 0x01 +#define IOCTL_CALL_PENDING 0x02 +#define IOCTL_CALL_INVALID_CODE 0x03 +#define IOCTL_CALL_INVALID_DEVICE 0x04 +#define IOCTL_CALL_TIMEOUT 0x08 + +/* + * DIF operation + */ +#define DIF_INSERT 0 +#define DIF_VERIFY_FORWARD 1 +#define DIF_VERIFY_DELETE 2 +#define DIF_VERIFY_REPLACE 3 + +#define DIF_UDT_SIZE 6 + +/* + * Login state in tiDeviceInfo_t + */ +#define INI_LGN_STATE_FREE 0x00000000 +#define INI_LGN_STATE_LOGIN 0x00000001 +#define INI_LGN_STATE_FAIL 0x00000002 +#define INI_LGN_STATE_OTHERS 0x0000000F + +/* + * SecurityCipherMode in tiEncryptInfo_t and tiCOMEncryptSetMode() + */ +#define TI_ENCRYPT_SEC_MODE_FACT_INIT 0x00000000 +#define TI_ENCRYPT_SEC_MODE_A 0x40000000 +#define TI_ENCRYPT_SEC_MODE_B 0x80000000 +#define TI_ENCRYPT_ATTRIB_ALLOW_SMF 0x00000200 +#define TI_ENCRYPT_ATTRIB_AUTH_REQ 0x00000100 +#define TI_ENCRYPT_ATTRIB_CIPHER_XTS 0x00000002 +#define TI_ENCRYPT_ATTRIB_CIPHER_ECB 0x00000001 + +/* + * Status in tiEncryptInfo_t + */ +#define TI_ENCRYPT_STATUS_NO_NVRAM 0x00000001 +#define TI_ENCRYPT_STATUS_NVRAM_ERROR 0x00000002 +#define TI_ENCRYPT_STATUS_ENGINE_ERROR 0x00000004 + +/* + * EncryptMode in tiEncrypt_t + */ +#define TI_ENCRYPT_MODE_XTS_AES 0x00400000 +#define TI_ENCRYPT_MODE_ECB_AES 0x00000000 + +/* + * Encrypt blob types + */ +#define TI_PLAINTEXT 0 +#define TI_ENCRYPTED_KEK_PMCA 1 +#define TI_ENCRYPTED_KEK_PMCB 2 + +/* + * Encrypt DEK table key entry sizes + */ +#define TI_DEK_TABLE_KEY_SIZE16 0 +#define TI_DEK_TABLE_KEY_SIZE24 1 +#define TI_DEK_TABLE_KEY_SIZE32 2 +#define TI_DEK_TABLE_KEY_SIZE40 3 +#define TI_DEK_TABLE_KEY_SIZE48 4 +#define TI_DEK_TABLE_KEY_SIZE56 5 +#define TI_DEK_TABLE_KEY_SIZE64 6 +#define TI_DEK_TABLE_KEY_SIZE72 7 +#define TI_DEK_TABLE_KEY_SIZE80 8 + +/* KEK blob size and DEK blob size and host DEK table entry number */ +#define TI_KEK_BLOB_SIZE 48 +#define TI_KEK_MAX_TABLE_ENTRIES 8 + +#define TI_DEK_MAX_TABLES 2 +#define TI_DEK_MAX_TABLE_ENTRIES (1024*4) + +#define TI_DEK_BLOB_SIZE 80 + + +/************************************************************ +* tiHWEventMode_t page operation definitions +************************************************************/ +#define tiModePageGet 1 +#define tiModePageSet 2 + +/* controller configuration page code */ +#define TI_SAS_PROTOCOL_TIMER_CONFIG_PAGE 0x04 +#define TI_INTERRUPT_CONFIGURATION_PAGE 0x05 +#define TI_ENCRYPTION_GENERAL_CONFIG_PAGE 0x20 +#define TI_ENCRYPTION_DEK_CONFIG_PAGE 0x21 +#define TI_ENCRYPTION_CONTROL_PARM_PAGE 0x22 +#define TI_ENCRYPTION_HMAC_CONFIG_PAGE 0x23 + + +/* encryption self test type */ +#define TI_ENCRYPTION_TEST_TYPE_BIST 0x01 +#define TI_ENCRYPTION_TEST_TYPE_HMAC 0x02 + +/* SHA algorithm type */ +#define TI_SHA_ALG_1 0x04 +#define TI_SHA_ALG_256 0x08 +#define TI_SHA_ALG_224 0x10 +#define TI_SHA_ALG_512 0x20 +#define TI_SHA_ALG_384 0x40 + +#define TI_SHA_1_DIGEST_SIZE 20 +#define TI_SHA_256_DIGEST_SIZE 32 +#define TI_SHA_224_DIGEST_SIZE 28 +#define TI_SHA_512_DIGEST_SIZE 64 +#define TI_SHA_384_DIGEST_SIZE 48 + + +/***************************************************************************** + * INITIATOR SPECIFIC DEFINES AND ENUMS + *****************************************************************************/ + +/* + * ostiInitiatorIOCompleted() statusDetail contains SCSI status, + * when status passed in ostiInitiatorIOCompleted() is tiIOSuccess. + */ +#define SCSI_STAT_GOOD 0x00 +#define SCSI_STAT_CHECK_CONDITION 0x02 +#define SCSI_STAT_CONDITION_MET 0x04 +#define SCSI_STAT_BUSY 0x08 +#define SCSI_STAT_INTERMEDIATE 0x10 +#define SCSI_STAT_INTER_CONDIT_MET 0x14 +#define SCSI_STAT_RESV_CONFLICT 0x18 +#define SCSI_STAT_COMMANDTERMINATED 0x22 +#define SCSI_STAT_TASK_SET_FULL 0x28 +#define SCSI_STAT_ACA_ACTIVE 0x30 +#define SCSI_STAT_TASK_ABORTED 0x40 + +/* +01: soft error +02: not ready +03: medium error +04: hardware error +05: illegal request +06: unit attention +0b: abort command +*/ +#define SCSI_SENSE_KEY_NO_SENSE 0x00 +#define SCSI_SENSE_KEY_RECOVERED_ERROR 0x01 +#define SCSI_SENSE_KEY_NOT_READY 0x02 +#define SCSI_SENSE_KEY_MEDIUM_ERROR 0x03 +#define SCSI_SENSE_KEY_HARDWARE_ERROR 0x04 +#define SCSI_SENSE_KEY_ILLEGAL_REQUEST 0x05 +#define SCSI_SENSE_KEY_UNIT_ATTENTION 0x06 +#define SCSI_SENSE_KEY_DATA_PROTECT 0x07 +#define SCSI_SENSE_KEY_BLANK_CHECK 0x08 +#define SCSI_SENSE_KEY_UNIQUE 0x09 +#define SCSI_SENSE_KEY_COPY_ABORTED 0x0A +#define SCSI_SENSE_KEY_ABORTED_COMMAND 0x0B +#define SCSI_SENSE_KEY_EQUAL 0x0C +#define SCSI_SENSE_KEY_VOL_OVERFLOW 0x0D +#define SCSI_SENSE_KEY_MISCOMPARE 0x0E +#define SCSI_SENSE_KEY_RESERVED 0x0F + + + + +/* + * Reset option in tiCOMReset() + */ +typedef enum +{ + tiSoftReset, + tiHardReset, + tiAutoReset +} tiReset_t; + +/* + * Bit 0 Mask for the persistent option in tiINIDiscoverTargets() + */ +#define NORMAL_ASSIGN_MASK 0x00000000 +#define FORCE_PERSISTENT_ASSIGN_MASK 0x00000001 + +/* + * Bit 1 Mask for the auto login option in tiINIDiscoverTargets() + */ +#define AUTO_LOGIN_MASK 0x00000000 +#define NO_AUTO_LOGIN_MASK 0x00000002 + + +/* + * Task Management task used in tiINITaskManagement() + * + * 1 AG_ABORT TASK - aborts the task identified by the Referenced Task Tag field. + * 2 AG_ABORT TASK SET - aborts all Tasks issued by this initiator on the Logical Unit + * 3 AG_CLEAR ACA - clears the Auto Contingent Allegiance condition. + * 4 AG_CLEAR TASK SET - Aborts all Tasks (from all initiators) for the Logical Unit. + * 5 AG_LOGICAL UNIT RESET + * 6 AG_TARGET WARM RESET - iSCSI only + * 7 AG_TARGET_COLD_RESET - iSCSI only + * 8 AG_TASK_REASSIGN - iSCSI only + * 9 AG_QUERY_TASK - SAS only + */ + +#define AG_ABORT_TASK 1 +#define AG_ABORT_TASK_SET 2 +#define AG_CLEAR_ACA 3 +#define AG_CLEAR_TASK_SET 4 +#define AG_LOGICAL_UNIT_RESET 5 +#define AG_TARGET_WARM_RESET 6 /* iSCSI only */ +#define AG_TARGET_COLD_RESET 7 /* iSCSI only */ +#define AG_TASK_REASSIGN 8 /* iSCSI only */ +#define AG_QUERY_TASK 9 /* SAS only */ + + +/* + * Event types for ostiInitiatorEvent() + */ +typedef enum +{ + tiIntrEventTypeCnxError, + tiIntrEventTypeDiscovery, + tiIntrEventTypeTransportRecovery, + tiIntrEventTypeTaskManagement, + tiIntrEventTypeDeviceChange, + tiIntrEventTypeLogin, + tiIntrEventTypeLocalAbort +} tiIntrEventType_t; + +/* + * Event status for ostiInitiatorEvent() + */ +typedef enum +{ + tiCnxUp, + tiCnxDown +} tiCnxEventStatus_t; + +typedef enum +{ + tiDiscOK, + tiDiscFailed +} tiDiscEventStatus_t; + +typedef enum +{ + tiLoginOK, + tiLoginFailed, + tiLogoutOK, + tiLogoutFailed +} tiLoginEventStatus_t; + +typedef enum +{ + tiRecOK, + tiRecFailed, + tiRecStarted +} tiRecEventStatus_t; + +typedef enum +{ + tiTMOK, + tiTMFailed +} tiTMEventStatus_t; + +typedef enum +{ + tiDeviceRemoval, + tiDeviceArrival, + tiDeviceLoginReceived +} tiDevEventStatus_t; + +typedef enum +{ + tiAbortOK, + tiAbortFailed, + tiAbortDelayed, + tiAbortInProgress +} tiAbortEventStatus_t; + +/* + * SCSI SAM-2 Task Attribute + */ +#define TASK_UNTAGGED 0 /* Untagged */ +#define TASK_SIMPLE 1 /* Simple */ +#define TASK_ORDERED 2 /* Ordered */ +#define TASK_HEAD_OF_QUEUE 3 /* Head of Queue */ +#define TASK_ACA 4 /* ACA */ + +/* + * Data direction for I/O request + */ +typedef enum +{ + tiDirectionIn = 0x0000, + tiDirectionOut = 0x0001 +}tiDataDirection_t; + +/* + * NVRAM error subEvents for encryption + */ +typedef enum +{ + tiNVRAMSuccess = 0x0000, + tiNVRAMWriteFail = 0x0001, + tiNVRAMReadFail = 0x0002, + tiNVRAMNotFound = 0x0003, + tiNVRAMAccessTimeout = 0x0004 +}tiEncryptSubEvent_t; + +/* Event Logging */ + +/* Event Severity Codes */ +#define IOCTL_EVT_SEV_OFF 0x00 +#define IOCTL_EVT_SEV_ALWAYS_ON 0x01 +#define IOCTL_EVT_SEV_ERROR 0x02 +#define IOCTL_EVT_SEV_WARNING 0x03 +#define IOCTL_EVT_SEV_INFORMATIONAL 0x04 +#define IOCTL_EVT_SEV_DEBUG_L1 0x05 +#define IOCTL_EVT_SEV_DEBUG_L2 0x06 +#define IOCTL_EVT_SEV_DEBUG_L3 0x07 + +/* Event Source */ +#define IOCTL_EVT_SRC_HW 0xF0000000 +#define IOCTL_EVT_SRC_ITSDK 0x0F000000 +#define IOCTL_EVT_SRC_FW 0x00F00000 +#define IOCTL_EVT_SRC_TD_LAYER 0x000F0000 +#define IOCTL_EVT_SRC_TARGET 0x0000F000 +#define IOCTL_EVT_SRC_OSLAYER 0x00000F00 +#define IOCTL_EVT_SRC_RESERVED 0x000000F0 +#define IOCTL_EVT_SRC_RESERVED1 0x0000000F +/* Event Shifter */ +#define IOCTL_EVT_SRC_HW_SHIFTER 28 +#define IOCTL_EVT_SRC_ITSDK_SHIFTER 24 +#define IOCTL_EVT_SRC_FW_SHIFTER 20 +#define IOCTL_EVT_SRC_COMMON_LAYER_SHIFTER 16 +#define IOCTL_EVT_SRC_TARGET_SHIFTER 12 +#define IOCTL_EVT_SRC_OSLAYER_SHIFTER 8 +#define IOCTL_EVT_SRC_RESERVED_SHIFTER 4 +#define IOCTL_EVT_SRC_RESERVED1_SHIFTER 0 + +#define EVENTLOG_MAX_MSG_LEN 110 + +#define EVENT_ID_MAX 0xffffffff + +#define DISCOVERY_IN_PROGRESS 0xFFFFFFFF + +#define TI_SSP_INDIRECT_CDB_SIZE 64 +/* + * Flags in tiSuperScsiInitiatorRequest_t + */ +#define TI_SCSI_INITIATOR_DIF 0x00000001 +#define TI_SCSI_INITIATOR_ENCRYPT 0x00000002 +#define TI_SCSI_INITIATOR_INDIRECT_CDB 0x00000004 +/***************************************************************************** + * TARGET SPECIFIC DEFINES AND ENUMS + *****************************************************************************/ + +/* + * Event types for ostiTargetEvent() + */ +typedef enum +{ + tiTgtEventTypeCnxError, + tiTgtEventTypeDeviceChange +} tiTgtEventType_t; + +/* + * Flags in tiSuperScsiTargetRequest_t + */ +#define TI_SCSI_TARGET_DIF 0x00000001 +#define TI_SCSI_TARGET_MIRROR 0x00000002 +#define TI_SCSI_TARGET_ENCRYPT 0x00000004 +#endif /* TIDEFS_H */ diff --git a/sys/dev/pms/RefTisa/tisa/api/tiglobal.h b/sys/dev/pms/RefTisa/tisa/api/tiglobal.h new file mode 100644 index 000000000000..bc07967dd27a --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/api/tiglobal.h @@ -0,0 +1,66 @@ +/******************************************************************************* + *Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* + ********************************************************************************/ +/******************************************************************************** + ** + ** tiglobal.h + ** + ** Abstract: + ** + ********************************************************************************/ + + +#ifndef TIGLOBAL_H +#define TIGLOBAL_H + +#include +#include +#include + +#ifndef TIDEBUG_MSG +#define TIDEBUG_MSG(mask, val, format) +#endif + +extern bit32 gTiDebugLevel; + +#define TI_DBG0(a) TIDEBUG_MSG0(a) /* always print */ + +#define TI_DBG1(a) TIDEBUG_MSG(gTiDebugLevel,1, a ) +#define TI_DBG2(a) TIDEBUG_MSG(gTiDebugLevel,2, a ) +#define TI_DBG3(a) TIDEBUG_MSG(gTiDebugLevel,3, a ) +#define TI_DBG4(a) TIDEBUG_MSG(gTiDebugLevel,4, a ) +#define TI_DBG5(a) TIDEBUG_MSG(gTiDebugLevel,5, a ) /* OsDebugLevel 4 */ +#define TI_DBG6(a) TIDEBUG_MSG(gTiDebugLevel,6, a ) +#define TI_DBG7(a) + +extern bit32 gTiDebugMask; +#define TI_BIT1(a) TIDEBUG_MSG(gTiDebugMask,0x00000001, a ) +#define TI_BIT2(a) TIDEBUG_MSG(gTiDebugMask,0x00000002, a ) +#define TI_BIT3(a) TIDEBUG_MSG(gTiDebugMask,0x00000004, a ) +#define TI_BIT4(a) TIDEBUG_MSG(gTiDebugMask,0x00000008, a ) +#define TI_BIT5(a) TIDEBUG_MSG(gTiDebugMask,0x00000010, a ) +#define TI_BIT6(a) TIDEBUG_MSG(gTiDebugMask,0x00000020, a ) + + + +#endif /* TIGLOBAL_H */ diff --git a/sys/dev/pms/RefTisa/tisa/api/tiscsi.h b/sys/dev/pms/RefTisa/tisa/api/tiscsi.h new file mode 100644 index 000000000000..9963924f2339 --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/api/tiscsi.h @@ -0,0 +1,61 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/******************************************************************************** +** +** Version Control Information: +** +** +*******************************************************************************/ +/******************************************************************************** +** +** tiscsi.h +** +** Abstract: This module contains SCSI related data structure definition. +** +********************************************************************************/ + +#ifndef TISCSI_H +#define TISCSI_H + + +/* + * SCSI Sense Data + */ +typedef struct +{ + bit8 snsRespCode; + bit8 snsSegment; + bit8 senseKey; /* sense key */ + bit8 info[4]; + bit8 addSenseLen; /* 11 always */ + bit8 cmdSpecific[4]; + bit8 addSenseCode; /* additional sense code */ + bit8 senseQual; /* additional sense code qualifier */ + bit8 fru; + bit8 skeySpecific[3]; +} scsiRspSense_t; + + + +#endif /* TISCSI_H */ diff --git a/sys/dev/pms/RefTisa/tisa/api/titypes.h b/sys/dev/pms/RefTisa/tisa/api/titypes.h new file mode 100644 index 000000000000..01ea864d4b67 --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/api/titypes.h @@ -0,0 +1,636 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/******************************************************************************** +** +** Version Control Information: +** +** +*******************************************************************************/ +/******************************************************************************** +** +** titypes.h +** +** Abstract: This module contains data structure definition used +** by the Transport Independent API (TIAPI) Layer. +** +********************************************************************************/ + +#include + +#ifndef TITYPES_H +#define TITYPES_H + +/***************************************************************************** + * SHARED TYPES + *****************************************************************************/ + +typedef struct tiPortalContext +{ + void *osData; + void *tdData; +} tiPortalContext_t; + +typedef struct tiDeviceHandle +{ + void *osData; + void *tdData; +} tiDeviceHandle_t; + +typedef struct tiRoot +{ + void *osData; + void *tdData; +} tiRoot_t; + +typedef struct tiMem +{ + void *virtPtr; + void *osHandle; + bit32 physAddrUpper; + bit32 physAddrLower; + bit32 totalLength; + bit32 numElements; + bit32 singleElementLength; + bit32 alignment; + bit32 type; + bit32 reserved; +} tiMem_t; + +typedef struct tiLoLevelMem +{ + bit32 count; + tiMem_t mem[MAX_LL_LAYER_MEM_DESCRIPTORS]; +} tiLoLevelMem_t; + +typedef struct tiLoLevelOption +{ + bit32 usecsPerTick; + bit32 numOfQueuesPerPort; + bit32 mutexLockUsage; + bit32 pciFunctionNumber; + bit32 maxPortContext; + bit32 maxNumOSLocks; + agBOOLEAN encryption; + bit32 maxInterruptVectors; + bit32 flag; + bit32 max_MSI_InterruptVectors; +#ifdef SA_ENABLE_PCI_TRIGGER + bit32 PCI_trigger; +#endif /* SA_ENABLE_PCI_TRIGGER */ + +} tiLoLevelOption_t; + +typedef struct tiLoLevelResource +{ + tiLoLevelOption_t loLevelOption; + tiLoLevelMem_t loLevelMem; +} tiLoLevelResource_t; + +typedef struct tiTdSharedMem +{ + tiMem_t tdSharedCachedMem1; +} tiTdSharedMem_t; + +typedef struct tiIORequest +{ + void *osData; + void *tdData; +} tiIORequest_t; + +typedef struct tiSgl_s +{ + bit32 lower; + bit32 upper; + bit32 len; + bit32 type; +} tiSgl_t; + +typedef struct tiSenseData +{ + void *senseData; + bit8 senseLen; +} tiSenseData_t; + +typedef struct tiIOCTLPayload +{ + bit32 Signature; + bit16 MajorFunction; + bit16 MinorFunction; + bit16 Length; + bit16 Status; + bit32 Reserved; /* required for 64 bit alignment */ + bit8 FunctionSpecificArea[1]; +}tiIOCTLPayload_t; + + +typedef struct tiIOCTLPayload_wwn +{ + bit32 Signature; + bit16 MajorFunction; + bit16 MinorFunction; + bit16 Length; + bit16 Status; + bit32 Reserved; /* required for 64 bit alignment */ + bit8 FunctionSpecificArea[8]; +}tiIOCTLPayload_wwn_t; + +typedef struct tiPortInfo +{ + char *name; + char *address; + char *localName; + char *remoteName; + bit32 localNameLen; + bit32 remoteNameLen; +} tiPortInfo_t; + +typedef struct tiDif_s +{ + agBOOLEAN enableDIFPerLA; + bit32 flags; + bit16 initialIOSeed; + bit16 reserved; + bit32 DIFPerLAAddrLo; + bit32 DIFPerLAAddrHi; + bit16 DIFPerLARegion0SecCount; + bit16 DIFPerLANumOfRegions; + bit8 udtArray[DIF_UDT_SIZE]; + bit8 udtrArray[DIF_UDT_SIZE]; +} tiDif_t; + +#define DIF_INSERT 0 +#define DIF_VERIFY_FORWARD 1 +#define DIF_VERIFY_DELETE 2 +#define DIF_VERIFY_REPLACE 3 +#define DIF_VERIFY_UDT_REPLACE_CRC 5 +#define DIF_REPLACE_UDT_REPLACE_CRC 7 + +#define DIF_BLOCK_SIZE_512 0x00 +#define DIF_BLOCK_SIZE_520 0x01 +#define DIF_BLOCK_SIZE_4096 0x02 +#define DIF_BLOCK_SIZE_4160 0x03 + +#define DIF_ACTION_FLAG_MASK 0x00000007 /* 0 - 2 */ +#define DIF_CRC_VERIFICATION 0x00000008 /* 3 */ +#define DIF_CRC_INVERSION 0x00000010 /* 4 */ +#define DIF_CRC_IO_SEED 0x00000020 /* 5 */ +#define DIF_UDT_REF_BLOCK_COUNT 0x00000040 /* 6 */ +#define DIF_UDT_APP_BLOCK_COUNT 0x00000080 /* 7 */ +#define DIF_UDTR_REF_BLOCK_COUNT 0x00000100 /* 8 */ +#define DIF_UDTR_APP_BLOCK_COUNT 0x00000200 /* 9 */ +#define DIF_CUST_APP_TAG 0x00000C00 /* 10 - 11 */ +#define DIF_FLAG_RESERVED 0x0000F000 /* 12 - 15 */ +#define DIF_DATA_BLOCK_SIZE_MASK 0x000F0000 /* 16 - 19 */ +#define DIF_DATA_BLOCK_SIZE_SHIFT 16 +#define DIF_TAG_VERIFY_MASK 0x03F00000 /* 20 - 25 */ +#define DIF_TAG_UPDATE_MASK 0xFC000000 /* 26 - 31 */ + + +#define NORMAL_BLOCK_SIZE_512 512 +#define NORMAL_BLOCK_SIZE_4K 4096 + +#define DIF_PHY_BLOCK_SIZE_512 512 +#define DIF_PHY_BLOCK_SIZE_520 520 +#define DIF_PHY_BLOCK_SIZE_4096 4096 +#define DIF_PHY_BLOCK_SIZE_4160 4160 + +#define DIF_LOGIC_BLOCK_SIZE_520 520 +#define DIF_LOGIC_BLOCK_SIZE_528 528 +#define DIF_LOGIC_BLOCK_SIZE_4104 4104 +#define DIF_LOGIC_BLOCK_SIZE_4168 4168 + + + + +typedef struct tiDetailedDeviceInfo +{ + bit8 devType_S_Rate; + /* Bit 6-7: reserved + Bit 4-5: Two bits flag to specify a SAS or SATA (STP) device: + 00: SATA or STP device + 01: SSP or SMP device + 10: Direct SATA device + Bit 0-3: Connection Rate field when opening the device. + Code Description: + 00h: Device has not been registered + 08h: 1,5 Gbps + 09h: 3,0 Gbps + 0ah: 6.0 Gbps + All others Reserved + */ + bit8 reserved1; + bit16 reserved2; +} tiDetailedDeviceInfo_t; + +typedef struct tiDeviceInfo +{ + char *localName; + char *localAddress; + char *remoteName; + char *remoteAddress; + bit16 osAddress1; + bit16 osAddress2; + bit32 loginState; + tiDetailedDeviceInfo_t info; +} tiDeviceInfo_t; + + +#define KEK_BLOB_SIZE 48 +#define KEK_AUTH_SIZE 40 +#define KEK_MAX_TABLE_ENTRIES 8 + +#define DEK_MAX_TABLES 2 +#define DEK_MAX_TABLE_ENTRIES (1024*4) + +#define DEK_BLOB_SIZE_07 72 +#define DEK_BLOB_SIZE_08 80 + +#define OPERATOR_ROLE_ID_SIZE 1024 + +#define HMAC_SECRET_KEY_SIZE 72 + +typedef struct tiEncryptKekBlob +{ + bit8 kekBlob[KEK_BLOB_SIZE]; +} tiEncryptKekBlob_t; + +typedef struct tiEncryptDekBlob +{ + bit8 dekBlob[DEK_BLOB_SIZE_08]; +} tiEncryptDekBlob_t; + +typedef struct DEK_Table_s { + tiEncryptDekBlob_t Dek[DEK_MAX_TABLE_ENTRIES]; +}tiDEK_Table_t; + +typedef struct DEK_Tables_s { + tiDEK_Table_t DekTable[DEK_MAX_TABLES]; +} tiDEK_Tables_t; + +/*sTSDK 4.38 */ +#define OPR_MGMT_ID_STRING_SIZE 31 + +typedef struct tiID_s { + bit8 ID[OPR_MGMT_ID_STRING_SIZE]; +} tiID_t; + +typedef struct tiEncryptInfo +{ + bit32 securityCipherMode; + bit32 status; + bit32 sectorSize[6]; +} tiEncryptInfo_t; + +typedef struct tiEncryptPort +{ + bit32 encryptEvent; + bit32 subEvent; + void *pData; +} tiEncryptPort_t; + +typedef struct tiEncryptDek +{ + bit32 dekTable; + bit32 dekIndex; +} tiEncryptDek_t; + +typedef struct tiEncrypt +{ + tiEncryptDek_t dekInfo; + bit32 kekIndex; + agBOOLEAN keyTagCheck; + agBOOLEAN enableEncryptionPerLA; + bit32 sectorSizeIndex; + bit32 encryptMode; + bit32 keyTag_W0; + bit32 keyTag_W1; + bit32 tweakVal_W0; + bit32 tweakVal_W1; + bit32 tweakVal_W2; + bit32 tweakVal_W3; + bit32 EncryptionPerLAAddrLo; + bit32 EncryptionPerLAAddrHi; + bit16 EncryptionPerLRegion0SecCount; + bit16 reserved; +} tiEncrypt_t; + +typedef struct tiHWEventMode_s +{ + bit32 modePageOperation; + bit32 status; + bit32 modePageLen; + void *modePage; + void *context; +} tiHWEventMode_t; + +/***************************************************************************** + * INITIATOR TYPES + *****************************************************************************/ + +typedef struct tiInitiatorMem +{ + bit32 count; + tiMem_t tdCachedMem[6]; +} tiInitiatorMem_t; + +typedef struct tiInitiatorOption +{ + bit32 usecsPerTick; + bit32 pageSize; + tiMem_t dynamicDmaMem; + tiMem_t dynamicCachedMem; + bit32 ioRequestBodySize; +} tiInitiatorOption_t; + + +typedef struct tiInitiatorResource +{ + tiInitiatorOption_t initiatorOption; + tiInitiatorMem_t initiatorMem; +} tiInitiatorResource_t; + +typedef struct tiLUN +{ + bit8 lun[8]; +} tiLUN_t; + +typedef struct tiIniScsiCmnd +{ + tiLUN_t lun; + bit32 expDataLength; + bit32 taskAttribute; + bit32 crn; + bit8 cdb[16]; +} tiIniScsiCmnd_t; + +typedef struct tiScsiInitiatorRequest +{ + void *sglVirtualAddr; + tiIniScsiCmnd_t scsiCmnd; + tiSgl_t agSgl1; + tiDataDirection_t dataDirection; +} tiScsiInitiatorRequest_t; + +/* This is the standard request body for I/O that requires DIF or encryption. */ +typedef struct tiSuperScsiInitiatorRequest +{ + void *sglVirtualAddr; + tiIniScsiCmnd_t scsiCmnd; + tiSgl_t agSgl1; + tiDataDirection_t dataDirection; + bit32 flags; +#ifdef CCBUILD_INDIRECT_CDB + bit32 IndCDBLowAddr; /* The low physical address of indirect CDB buffer in host memory */ + bit32 IndCDBHighAddr; /* The high physical address of indirect CDB buffer in host memory */ + bit32 IndCDBLength; /* Indirect CDB length */ + void *IndCDBBuffer; /* Indirect SSPIU buffer */ +#endif + tiDif_t Dif; + tiEncrypt_t Encrypt; +} tiSuperScsiInitiatorRequest_t; + +typedef struct tiSMPFrame +{ + void *outFrameBuf; + bit32 outFrameAddrUpper32; + bit32 outFrameAddrLower32; + bit32 outFrameLen; + bit32 inFrameAddrUpper32; + bit32 inFrameAddrLower32; + bit32 inFrameLen; + bit32 expectedRespLen; + bit32 flag; +} tiSMPFrame_t; +typedef struct tiEVTData +{ + bit32 SequenceNo; + bit32 TimeStamp; + bit32 Source; + bit32 Code; + bit8 Reserved; + bit8 BinaryDataLength; + bit8 DataAndMessage[EVENTLOG_MAX_MSG_LEN]; +} tiEVTData_t; + +typedef bit32 (*IsrHandler_t)( + tiRoot_t *tiRoot, + bit32 channelNum + ); +typedef void (*DeferedHandler_t)( + tiRoot_t *tiRoot, + bit32 channelNum, + bit32 count, + bit32 context + ); + +/***************************************************************************** + * TARGET TYPES + *****************************************************************************/ + +typedef struct tiTargetMem { + bit32 count; + tiMem_t tdMem[10]; +} tiTargetMem_t; + +typedef struct tiTargetOption { + bit32 usecsPerTick; + bit32 pageSize; + bit32 numLgns; + bit32 numSessions; + bit32 numXchgs; + tiMem_t dynamicDmaMem; + tiMem_t dynamicCachedMem; +} tiTargetOption_t; + +typedef struct +{ + tiTargetOption_t targetOption; + tiTargetMem_t targetMem; +} tiTargetResource_t; + +typedef struct +{ + bit8 *reqCDB; + bit8 *scsiLun; + bit32 taskAttribute; + bit32 taskId; + bit32 crn; +} tiTargetScsiCmnd_t; + +typedef struct tiSuperScsiTargetRequest +{ + bit32 flags; + tiDif_t Dif; + tiEncrypt_t Encrypt; + tiSgl_t agSgl; + void *sglVirtualAddr; + tiSgl_t agSglMirror; + void *sglVirtualAddrMirror; + bit32 Offset; + bit32 DataLength; +} tiSuperScsiTargetRequest_t; + +/* SPCv controller mode page definitions */ +typedef struct tiEncryptGeneralPage_s { + bit32 pageCode; /* 0x20 */ + bit32 numberOfDeks; +} tiEncryptGeneralPage_t; + +#define TD_ENC_CONFIG_PAGE_KEK_NUMBER 0x0000FF00 +#define TD_ENC_CONFIG_PAGE_KEK_SHIFT 8 + +typedef struct tiEncryptDekConfigPage +{ + bit32 pageCode; /* 0x21 */ + bit32 table0AddrLo; + bit32 table0AddrHi; + bit32 table0Entries; + bit32 table0Config; + bit32 table1AddrLo; + bit32 table1AddrHi; + bit32 table1Entries; + bit32 table1Config; +} tiEncryptDekConfigPage_t; + +#define TD_ENC_DEK_CONFIG_PAGE_DEK_TABLE_NUMBER 0xF0000000 +#define TD_ENC_DEK_CONFIG_PAGE_DEK_CACHE_WAYS 0x0F000000 +#define TD_ENC_DEK_CONFIG_PAGE_DPR 0x00000200 +#define TD_ENC_DEK_CONFIG_PAGE_DER 0x00000100 +#define TD_ENC_DEK_CONFIG_PAGE_DEK_CACHE_SHIFT 24 +#define TD_ENC_DEK_CONFIG_PAGE_DEK_TABLE_SHIFT 28 +#define TD_ENC_DEK_CONFIG_PAGE_DEK_HDP_SHIFT 8 + + +/* CCS (Current Crypto Services) and NOPR (Number of Operators) are valid only in GET_CONTROLLER_CONFIG */ +/* NAR, CORCAP and USRCAP are valid only when AUT==1 */ +typedef struct tiEncryptControlParamPage_s { + bit32 PageCode; /* 0x22 */ + bit32 CORCAP; /* Crypto Officer Role Capabilities */ + bit32 USRCAP; /* User Role Capabilities */ + bit32 CCS; /* Current Crypto Services */ + bit32 NOPR; /* Number of Operators */ +} tiEncryptControlParamPage_t; + +typedef struct tiEncryptHMACConfigPage_s +{ + bit32 PageCode; + bit32 CustomerTag; + bit32 KeyAddrLo; + bit32 KeyAddrHi; +} tiEncryptHMACConfigPage_t; + +typedef struct tiInterruptConfigPage_s { + bit32 pageCode; /* 0x05 */ + bit32 vectorMask; + bit32 reserved; + bit32 ICTC0; + bit32 ICTC1; + bit32 ICTC2; + bit32 ICTC3; + bit32 ICTC4; + bit32 ICTC5; + bit32 ICTC6; + bit32 ICTC7; +} tiInterruptConfigPage_t; + +/* brief data structure for SAS protocol timer configuration page. */ +typedef struct tiSASProtocolTimerConfigurationPage_s{ + bit32 pageCode; /* 0x04 */ + bit32 MST_MSI; + bit32 STP_SSP_MCT_TMO; + bit32 STP_FRM_TMO; + bit32 STP_IDLE_TMO; + bit32 OPNRJT_RTRY_INTVL; + bit32 Data_Cmd_OPNRJT_RTRY_TMO; + bit32 Data_Cmd_OPNRJT_RTRY_THR; +} tiSASProtocolTimerConfigurationPage_t; + +/*sTSDK 4.19 */ + +/* The command is for an operator to login to/logout from SPCve. */ +/* Only when all IOs are quiesced, can an operator logout. */ +typedef struct tiOperatorCommandSet_s { + bit32 OPRIDX_PIN_ACS; /* Access type (ACS) [4 bits] */ + /* KEYopr pinned in the KEK RAM (PIN) [1 bit] */ + /* KEYopr Index in the KEK RAM (OPRIDX) [8 bits] */ + bit8 cert[40]; /* Operator Certificate (CERT) [40 bytes] */ + bit32 reserved[3]; /* reserved */ +} tiOperatorCommandSet_t; + +#define FIPS_SELFTEST_MAX_MSG_LEN (128*1024) +#define FIPS_SELFTEST_MAX_DIGEST_SIZE 64 + +typedef struct tiEncryptSelfTestDescriptor_s { + bit32 AESNTC_AESPTC; /* AES Negative/Positive Test Case Bit Map */ + bit32 KWPNTC_PKWPPTC; /* Key Wrap Negative/Positive Test Case Bit Map */ + bit32 HMACNTC_HMACPTC; /* HMAC Negative Test Case Bit Map */ +} tiEncryptSelfTestDescriptor_t; + +typedef struct tiEncryptSelfTestResult_s{ + bit32 AESNTCS_AESPTCS; /* AES Negative/Positive Test Case Status */ + bit32 KWPNTCS_PKWPPTCS; /* Key Wrap Negative/Positive Test Case Status */ + bit32 HMACNTCS_HMACPTCS; /* HMAC Negative Test Case Status */ +} tiEncryptSelfTestResult_t; + +/* + Tell SPCve controller the underlying SHA algorithm, where to fetch the message, + the size of the message, where to store the digest, where to fetch the secret key and the size of the key. +*/ +typedef struct tiEncryptHMACTestDescriptor_s +{ + bit32 Tlen_SHAAlgo; + bit32 MsgAddrLo; + bit32 MsgAddrHi; + bit32 MsgLen; + bit32 DigestAddrLo; + bit32 DigestAddrHi; + bit32 KeyAddrLo; + bit32 KeyAddrHi; + bit32 KeyLen; +} tiEncryptHMACTestDescriptor_t; + +typedef struct tiEncryptHMACTestResult_s +{ + bit32 Tlen_SHAAlgo; + bit32 Reserved[12]; +} tiEncryptHMACTestResult_t; + +typedef struct tiEncryptSHATestDescriptor_s +{ + bit32 Dword0; + bit32 MsgAddrLo; + bit32 MsgAddrHi; + bit32 MsgLen; + bit32 DigestAddrLo; + bit32 DigestAddrHi; +} tiEncryptSHATestDescriptor_t; + +typedef struct tiEncryptSHATestResult_s +{ + bit32 Dword0; + bit32 Dword[12]; +} tiEncryptSHATestResult_t; + + +#endif /* TITYPES_H */ diff --git a/sys/dev/pms/RefTisa/tisa/sassata/common/ossa.h b/sys/dev/pms/RefTisa/tisa/sassata/common/ossa.h new file mode 100644 index 000000000000..9de1837a2c25 --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/common/ossa.h @@ -0,0 +1,87 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/*******************************************************************************/ +/** \file + * + * The file defines the declaration of OS types + * + */ + +#ifndef __OS_SA_H__ +#define __OS_SA_H__ + +#define DEBUG_LEVEL OSSA_DEBUG_LEVEL_1 +#define ossaLogDebugString TIDEBUG_MSG +#define ossaAssert OS_ASSERT + +#define tddmLogDebugString TIDEBUG_MSG +#define DM_ASSERT OS_ASSERT + +#define tdsmLogDebugString TIDEBUG_MSG +#define SM_ASSERT OS_ASSERT + +#ifdef NOT_YET /* no longer valid */ +#define ossaLogDebugString(agRoot, level, string, ptr1, ptr2, value1, value2) \ + do { \ + if ( level <= DEBUG_LEVEL ) \ + { \ + printk("%s:", __FUNCTION__); \ + if ( agNULL != string ) \ + { \ + printk("%s:", string); \ + } \ + if ( agNULL != ptr1 ) \ + { \ + printk("ptr1=%p,", ptr1); \ + } \ + if ( agNULL != ptr2 ) \ + { \ + printk("ptr2=%p,", ptr2); \ + } \ + if ( OSSA_DEBUG_PRINT_INVALID_NUMBER != value1 ) \ + { \ + printk("value1=0x%08x ", value1); \ + } \ + if ( OSSA_DEBUG_PRINT_INVALID_NUMBER != value2 ) \ + { \ + printk("value2=0x%08x ", value2); \ + } \ + printk("\n"); \ + } \ + } while (0); + +#ifndef ossaAssert +#define ossaAssert(agRoot, expr, message) \ + do { \ + if (agFALSE == (expr)) \ + { \ + printk("ossaAssert: %s", (message)); \ + printk(" - file %s, line %d\n", __FILE__, __LINE__); \ + } \ + } while (0); +#endif +#endif /* 0 */ +#include +#include +#endif /* __OS_SA_H__ */ diff --git a/sys/dev/pms/RefTisa/tisa/sassata/common/ossacmnapi.c b/sys/dev/pms/RefTisa/tisa/sassata/common/ossacmnapi.c new file mode 100644 index 000000000000..591db4c02602 --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/common/ossacmnapi.c @@ -0,0 +1,9093 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +/*******************************************************************************/ +/** \file + * + * + * + * This file contains CB functions used by lower layer in SAS/SATA TD layer + * + */ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#ifdef FDS_SM +#include +#include +#include +#endif + +#ifdef FDS_DM +#include +#include +#include +#endif + +#include +#include +#include + +#ifdef INITIATOR_DRIVER +#include +#include +#include +#endif + +#ifdef TARGET_DRIVER +#include +#include +#include +#endif + +#include +#include + +#ifdef ECHO_TESTING +/* temporary to test saEchoCommand() */ +extern bit8 gEcho; +#endif + +#if defined(SALLSDK_DEBUG) +extern bit32 gLLDebugLevel; +#endif + + +#include + +#ifdef SA_ENABLE_TRACE_FUNCTIONS + +#ifdef siTraceFileID +#undef siTraceFileID +#endif +#define siTraceFileID 'R' +#endif +/* + functions that are common to SAS and SATA +*/ + +FORCEINLINE +void ossaCacheInvalidate( + agsaRoot_t *agRoot, + void *osMemHandle, + void *virtPtr, + bit32 length + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + + TI_DBG6(("ossaCacheInvalidate: start\n")); + ostiCacheInvalidate(tiRoot, osMemHandle, virtPtr, length); + return; +} + +FORCEINLINE +void ossaCacheFlush( + agsaRoot_t *agRoot, + void *osMemHandle, + void *virtPtr, + bit32 length + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + + TI_DBG6(("ossaCacheFlush: start\n")); + ostiCacheFlush(tiRoot, osMemHandle, virtPtr, length); + return; +} + +FORCEINLINE +void ossaCachePreFlush( + agsaRoot_t *agRoot, + void *osMemHandle, + void *virtPtr, + bit32 length + ) + +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + + TI_DBG6(("ossaCachePreFlush: start\n")); + ostiCachePreFlush(tiRoot, osMemHandle, virtPtr, length); + return; +} + +/***************************************************************************** +*! \brief ossaDeviceHandleAccept +* +* Purpose: This function is called by lower layer to inform TD layer of +* a new SAS device arrival. Used only at the target +* +* +* \param agRoot Pointer to chip/driver Instance. +* \param agDevHandle Pointer to the device handle of the device +* \param agDevInfo Pointer to the device info structure +* \param agPortContext Pointer to a port context +* +* \return: +* OSSA_RC_REJECT A device is accpeted +* OSSA_RC_ACCEPT A device is rejected +* +* \note - For details, refer to SAS/SATA Low-Level API Specification +* +*****************************************************************************/ +osGLOBAL bit32 ossaDeviceHandleAccept( + agsaRoot_t *agRoot, + agsaDevHandle_t *agDevHandle, + agsaSASDeviceInfo_t *agDevInfo, + agsaPortContext_t *agPortContext, + bit32 *hostAssignedDeviceId + ) +{ +#ifdef TARGET_DRIVER + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + + tdsaPortContext_t *onePortContext = agNULL; + tiPortalContext_t *tiPortalContext = agNULL; + tdsaDeviceData_t *oneDeviceData = agNULL; + tiDeviceHandle_t *tiDeviceHandle = agNULL; + tdsaSASSubID_t agSASSubID; + bit32 option; + bit32 param; + /* + at target only + by default TD layer accpets all devices + */ + /* + at this point, + by LINK_UP event tdsaPortContext should have been created + */ + smTraceFuncEnter(hpDBG_VERY_LOUD, "Y0"); + TI_DBG1(("ossaDeviceHandleAccept: start hostAssignedDeviceId 0x%X\n",*hostAssignedDeviceId)); + + + if (agPortContext == agNULL) + { + TI_DBG1(("ossaDeviceHandleAccept: NULL agsaPortContext; wrong\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Y0"); + return OSSA_RC_REJECT; + } + + + onePortContext = (tdsaPortContext_t *)agPortContext->osData; + + if (onePortContext == agNULL) + { + TI_DBG1(("ossaDeviceHandleAccept: NULL oneportcontext; wrong\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "Y0"); + return OSSA_RC_REJECT; + } + + tiPortalContext = (tiPortalContext_t *)onePortContext->tiPortalContext; + + if (tiPortalContext == agNULL) + { + TI_DBG1(("ossaDeviceHandleAccept: NULL tiPortalContext; wrong\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "Y0"); + return OSSA_RC_REJECT; + } + + /* + add the device to device list + cf) OSSA_DISCOVER_FOUND_DEVICE + */ + TI_DBG4(("ossaDeviceHandleAccept: sasAddressHi 0x%08x\n", SA_DEVINFO_GET_SAS_ADDRESSHI(&agDevInfo->commonDevInfo))); + TI_DBG4(("ossaDeviceHandleAccept: sasAddressLo 0x%08x\n", SA_DEVINFO_GET_SAS_ADDRESSLO(&agDevInfo->commonDevInfo))); + TI_DBG4(("ossaDeviceHandleAccept: device type 0x%x\n", DEVINFO_GET_DEVICETTYPE(&agDevInfo->commonDevInfo))); + TI_DBG4(("ossaDeviceHandleAccept: phys %d\n", agDevInfo->numOfPhys)); + TI_DBG4(("ossaDeviceHandleAccept: pid %d\n", onePortContext->id)); + + if (DEVINFO_GET_DEVICETTYPE(&agDevInfo->commonDevInfo) == SAS_END_DEVICE) + { + TI_DBG4(("ossaDeviceHandleAccept: SAS_END_DEVICE\n")); + } + else if (DEVINFO_GET_DEVICETTYPE(&agDevInfo->commonDevInfo) == SAS_EDGE_EXPANDER_DEVICE) + { + TI_DBG4(("ossaDeviceHandleAccept: SAS_EDGE_EXPANDER_DEVICE\n")); + } + else /* SAS_FANOUT_EXPANDER_DEVICE */ + { + TI_DBG4(("ossaDeviceHandleAccept: SAS_FANOUT_EXPANDER_DEVICE\n")); + } + agSASSubID.sasAddressHi = SA_DEVINFO_GET_SAS_ADDRESSHI(&agDevInfo->commonDevInfo); + agSASSubID.sasAddressLo = SA_DEVINFO_GET_SAS_ADDRESSLO(&agDevInfo->commonDevInfo); + agSASSubID.initiator_ssp_stp_smp = agDevInfo->initiator_ssp_stp_smp; + agSASSubID.target_ssp_stp_smp = agDevInfo->target_ssp_stp_smp; + + + tdssAddSASToSharedcontext( + onePortContext, + agRoot, + agDevHandle, + &agSASSubID, + agTRUE, + 0xFF, + TD_OPERATION_TARGET + ); + + /* at this point devicedata for new device exists */ + oneDeviceData = (tdsaDeviceData_t *)agDevHandle->osData; + + if (oneDeviceData == agNULL) + { + TI_DBG1(("ossaDeviceHandleAccept: NULL oneDeviceData; wrong\n")); + return OSSA_RC_REJECT; + } + + oneDeviceData->registered = agTRUE; + + tiDeviceHandle = &(oneDeviceData->tiDeviceHandle); + + if (tiDeviceHandle == agNULL) + { + TI_DBG1(("ossaDeviceHandleAccept: NULL tiDeviceHandle; wrong\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "Y0"); + return OSSA_RC_REJECT; + } + + /* setting MCN in agsaDeviceInfo_t*/ + agDevInfo->commonDevInfo.flag = agDevInfo->commonDevInfo.flag | (tdsaAllShared->MCN << 16); + /* increment RegisteredDevNums */ + onePortContext->RegisteredDevNums++; + + *hostAssignedDeviceId |= 0xBEEF0000; + + TI_DBG1(("ossaDeviceHandleAccept: Now hostAssignedDeviceId 0x%X\n", *hostAssignedDeviceId)); + + + /* no login in SAS */ + /* + osGLOBAL bit32 ostiTargetEvent ( + tiRoot_t *tiRoot, + tiPortalContext_t *portalContext, + tiDeviceHandle_t *tiDeviceHandle, + tiTgtEventType_t eventType, + bit32 eventStatus, + void *parm + ); + */ + + ostiTargetEvent( + tiRoot, + tiPortalContext, + tiDeviceHandle, + tiTgtEventTypeDeviceChange, + tiDeviceArrival, + agNULL + ); + /* set MCN and initiator role bit using saSetDeviceInfo */ + option = 24; /* setting MCN and initiator role 1 1000b*/ + param = (1 << 18) | (tdsaAllShared->MCN << 24); + TI_DBG1(("ossaDeviceHandleAccept: option 0x%x param 0x%x MCN 0x%x\n", option, param, tdsaAllShared->MCN)); + saSetDeviceInfo(agRoot, agNULL, 0, agDevHandle, option, param, ossaSetDeviceInfoCB); + smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "Y0"); + return OSSA_RC_ACCEPT; +#endif + +#ifdef INITIATOR_DRIVER + /* this function is not used in case of Initiator */ + return OSSA_RC_ACCEPT; +#endif +} + +#ifdef INITIATOR_DRIVER +/***************************************************************************** +*! \brief ossaDiscoverSasCB +* +* Purpose: This function is called by lower layer to inform TD layer of +* SAS discovery results +* +* +* \param agRoot Pointer to chip/driver Instance. +* \param agPortContext Pointer to the port context of TD and Lower layer +* \param event event type +* \param pParm1 Pointer to data associated with event +* \param pParm2 Pointer to data associated with event +* +* \return: none +* +* \note - For details, refer to SAS/SATA Low-Level API Specification +* +*****************************************************************************/ +osGLOBAL void ossaDiscoverSasCB(agsaRoot_t *agRoot, + agsaPortContext_t *agPortContext, + bit32 event, + void *pParm1, + void *pParm2 + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)osData->tdsaAllShared; + + tdsaPortContext_t *onePortContext = agNULL; + tdsaDeviceData_t *oneDeviceData = agNULL; + + agsaDevHandle_t *agDevHandle = agNULL; + agsaSASDeviceInfo_t *agDeviceInfo = agNULL; + tiPortalContext_t *tiPortalContext = agNULL; + tdList_t *DeviceListList; + tdsaSASSubID_t agSASSubID; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"Y1"); + TI_DBG2(("ossaDiscoverSasCB: start\n")); + + if (agPortContext == agNULL) + { + TI_DBG1(("ossaDiscoverSasCB: NULL agsaPortContext; wrong\n")); + return; + } + + onePortContext = (tdsaPortContext_t *)agPortContext->osData; + tiPortalContext = (tiPortalContext_t *)onePortContext->tiPortalContext; + + switch ( event ) + { + case OSSA_DISCOVER_STARTED: + { + TI_DBG3(("ossaDiscoverSasCB: STARTED pid %d\n", onePortContext->id)); + /* + invalidate all devices in current device list + */ + DeviceListList = tdsaAllShared->MainDeviceList.flink; + while (DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + TI_DBG3(("ossaDiscoverSasCB: loop did %d\n", oneDeviceData->id)); + TI_DBG3(("ossaDiscoverSasCB: loop sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG6(("ossaDiscoverSasCB: loop sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + if (oneDeviceData->tdPortContext == onePortContext) + { + TI_DBG3(("ossaDiscoverSasCB: did %d is invalidated \n", oneDeviceData->id)); + /* temporary solution: only for sata direct attached */ + } + DeviceListList = DeviceListList->flink; + } + onePortContext->DiscoveryState = ITD_DSTATE_STARTED; + break; + } + + case OSSA_DISCOVER_FOUND_DEVICE: + { + TI_DBG4(("ossaDiscoverSasCB: $$$$$ FOUND_DEVICE pid %d\n", onePortContext->id)); + agDevHandle = (agsaDevHandle_t *)pParm1; + agDeviceInfo = (agsaSASDeviceInfo_t *)pParm2; + TI_DBG5(("ossaDiscoverSasCB: sasAddressHi 0x%08x\n", SA_DEVINFO_GET_SAS_ADDRESSHI(&agDeviceInfo->commonDevInfo))); + TI_DBG5(("ossaDiscoverSasCB: sasAddressLo 0x%08x\n", SA_DEVINFO_GET_SAS_ADDRESSLO(&agDeviceInfo->commonDevInfo))); + TI_DBG5(("ossaDiscoverSasCB: device type 0x%x\n", DEVINFO_GET_DEVICETTYPE(&agDeviceInfo->commonDevInfo))); + + TI_DBG6(("ossaDiscoverSasCB: phys %d\n", agDeviceInfo->numOfPhys)); + TI_DBG4(("ossaDiscoverSasCB: pid %d\n", onePortContext->id)); + + + /* Add only target devices; do not add expander device */ + if (DEVINFO_GET_DEVICETTYPE(&agDeviceInfo->commonDevInfo) == SAS_END_DEVICE) + { + agSASSubID.sasAddressHi = SA_DEVINFO_GET_SAS_ADDRESSHI(&agDeviceInfo->commonDevInfo); + agSASSubID.sasAddressLo = SA_DEVINFO_GET_SAS_ADDRESSLO(&agDeviceInfo->commonDevInfo); + agSASSubID.initiator_ssp_stp_smp = agDeviceInfo->initiator_ssp_stp_smp; + agSASSubID.target_ssp_stp_smp = agDeviceInfo->target_ssp_stp_smp; + + TI_DBG2(("ossaDiscoverSasCB: adding ....\n")); + + tdssAddSASToSharedcontext( + onePortContext, + agRoot, + agDevHandle, + &agSASSubID, + agTRUE, + agDeviceInfo->phyIdentifier, + TD_OPERATION_INITIATOR + ); + ostiInitiatorEvent( + tiRoot, + tiPortalContext, + agNULL, + tiIntrEventTypeDeviceChange, + tiDeviceArrival, + agNULL + ); + } + else + { + TI_DBG5(("ossaDiscoverSasCB: $$$$$ not end device. not adding....\n")); + } + + + break; + } + + case OSSA_DISCOVER_REMOVED_DEVICE: + { + TI_DBG3(("ossaDiscoverSasCB: REMOVED_DEVICE\n")); + agDevHandle = (agsaDevHandle_t *)pParm1; + agDeviceInfo = (agsaSASDeviceInfo_t *)pParm2; + oneDeviceData = (tdsaDeviceData_t *) agDevHandle->osData; + + TI_DBG6(("ossaDiscoverSasCB: sasAddressHi 0x%08x\n", + SA_DEVINFO_GET_SAS_ADDRESSHI(&agDeviceInfo->commonDevInfo))); + TI_DBG6(("ossaDiscoverSasCB: sasAddressLo 0x%08x\n", + SA_DEVINFO_GET_SAS_ADDRESSLO(&agDeviceInfo->commonDevInfo))); + TI_DBG6(("ossaDiscoverSasCB: phys %d\n", agDeviceInfo->numOfPhys)); + TI_DBG6(("ossaDiscoverSasCB: onePortContext->id %d\n", onePortContext->id)); + + if (oneDeviceData == agNULL) + { + TI_DBG1(("ossaDiscoverSasCB: Wrong. DevHandle->osData is NULL but is being removed\n")); + } + else + { + tdssRemoveSASFromSharedcontext(onePortContext, + oneDeviceData, + agRoot); + agDevHandle->osData = agNULL; + ostiInitiatorEvent( + tiRoot, + tiPortalContext, + agNULL, + tiIntrEventTypeDeviceChange, + tiDeviceRemoval, + agNULL + ); + } + + break; + } + case OSSA_DISCOVER_COMPLETE: + { + TI_DBG2(("ossaDiscoverSasCB: SAS COMPLETE pid %d\n", onePortContext->id)); + /* + note: + SAS discovery must be called before SATA discovery + "onePortContext->DiscoveryState = ITD_DSTATE_COMPLETED" is + in ossaDiscoverSataCB not in ossaDiscoverSasCB when SATA_ENABLE + */ +#ifndef SATA_ENABLE + onePortContext->DiscoveryState = ITD_DSTATE_COMPLETED; + TI_DBG6(("ossaDiscoverSasCB: COMPLETE pid %d\n", onePortContext->id)); +#endif + +#ifdef SATA_ENABLE + TI_DBG2(("ossaDiscoverSasCB: calling SATA discovery\n")); + + /* Continue with SATA discovery */ + saDiscover(agRoot, agPortContext, AG_SA_DISCOVERY_TYPE_SATA, + onePortContext->discoveryOptions); + +#else /* SATA not enable */ + +#ifdef TD_INTERNAL_DEBUG /* for debugging */ + /* dump device list */ + DeviceListList = tdsaAllShared->MainPortContextList.flink; + + while (DeviceListList != &(tdsaAllShared->MainPortContextList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + TI_DBG2(("ossaDiscoverSasCB: did %d valid %d\n", oneDeviceData->id, oneDeviceData->valid)); + TI_DBG2(("ossaDiscoverSasCB: device AddrHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG2(("ossaDiscoverSasCB: device AddrLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + DeviceListList = DeviceListList->flink; + } +#endif + + /* letting OS layer know discovery has been successfully complete */ + ostiInitiatorEvent( + tiRoot, + tiPortalContext, + agNULL, + tiIntrEventTypeDiscovery, + tiDiscOK, + agNULL + ); +#endif /* SATA_ENABLE */ + + break; + } + case OSSA_DISCOVER_ABORT: + { + TI_DBG3(("ossaDiscoverSasCB: ABORT\n")); + /* letting OS layer know discovery has not been successfully complete */ + ostiInitiatorEvent( + tiRoot, + tiPortalContext, + agNULL, + tiIntrEventTypeDiscovery, + tiDiscFailed, + agNULL + ); + break; + } + case OSSA_DISCOVER_ABORT_ERROR_1: + { + TI_DBG3(("ossaDiscoverSasCB: ERROR 1\n")); + /* letting OS layer know discovery has not been successfully complete */ + ostiInitiatorEvent( + tiRoot, + tiPortalContext, + agNULL, + tiIntrEventTypeDiscovery, + tiDiscFailed, + agNULL + ); + break; + } + + case OSSA_DISCOVER_ABORT_ERROR_2: + { + TI_DBG3(("ossaDiscoverSasCB: ERROR 2\n")); + /* letting OS layer know discovery has not been successfully complete */ + ostiInitiatorEvent( + tiRoot, + tiPortalContext, + agNULL, + tiIntrEventTypeDiscovery, + tiDiscFailed, + agNULL + ); + break; + } + + case OSSA_DISCOVER_ABORT_ERROR_3: + { + TI_DBG3(("ossaDiscoverSasCB: ERROR 3\n")); + /* letting OS layer know discovery has not been successfully complete */ + ostiInitiatorEvent( + tiRoot, + tiPortalContext, + agNULL, + tiIntrEventTypeDiscovery, + tiDiscFailed, + agNULL + ); + break; + } + case OSSA_DISCOVER_ABORT_ERROR_4: + { + TI_DBG3(("ossaDiscoverSasCB: ERROR 4\n")); + /* letting OS layer know discovery has not been successfully complete */ + ostiInitiatorEvent( + tiRoot, + tiPortalContext, + agNULL, + tiIntrEventTypeDiscovery, + tiDiscFailed, + agNULL + ); + break; + } + case OSSA_DISCOVER_ABORT_ERROR_5: + { + TI_DBG3(("ossaDiscoverSasCB: ERROR 5\n")); + /* letting OS layer know discovery has not been successfully complete */ + ostiInitiatorEvent( + tiRoot, + tiPortalContext, + agNULL, + tiIntrEventTypeDiscovery, + tiDiscFailed, + agNULL + ); + break; + } + case OSSA_DISCOVER_ABORT_ERROR_6: + { + TI_DBG3(("ossaDiscoverSasCB: ERROR 6\n")); + /* letting OS layer know discovery has not been successfully complete */ + ostiInitiatorEvent( + tiRoot, + tiPortalContext, + agNULL, + tiIntrEventTypeDiscovery, + tiDiscFailed, + agNULL + ); + break; + } + case OSSA_DISCOVER_ABORT_ERROR_7: + { + TI_DBG3(("ossaDiscoverSasCB: ERROR 7\n")); + /* letting OS layer know discovery has not been successfully complete */ + ostiInitiatorEvent( + tiRoot, + tiPortalContext, + agNULL, + tiIntrEventTypeDiscovery, + tiDiscFailed, + agNULL + ); + break; + } + case OSSA_DISCOVER_ABORT_ERROR_8: + { + TI_DBG3(("ossaDiscoverSasCB: ERROR 8\n")); + /* letting OS layer know discovery has not been successfully complete */ + ostiInitiatorEvent( + tiRoot, + tiPortalContext, + agNULL, + tiIntrEventTypeDiscovery, + tiDiscFailed, + agNULL + ); + break; + } + case OSSA_DISCOVER_ABORT_ERROR_9: + { + TI_DBG3(("ossaDiscoverSasCB: ERROR 9\n")); + /* letting OS layer know discovery has not been successfully complete */ + ostiInitiatorEvent( + tiRoot, + tiPortalContext, + agNULL, + tiIntrEventTypeDiscovery, + tiDiscFailed, + agNULL + ); + break; + } + default: + TI_DBG3(("ossaDiscoverSasCB: ERROR default event 0x%x\n", event)); + /* letting OS layer know discovery has not been successfully complete */ + ostiInitiatorEvent( + tiRoot, + tiPortalContext, + agNULL, + tiIntrEventTypeDiscovery, + tiDiscFailed, + agNULL + ); + break; + } /* end of switch */ + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Y1"); + return; +} +#endif // #ifdef INITIATOR_DRIVER + +osGLOBAL void ossaLogTrace0( + agsaRoot_t *agRoot, + bit32 traceCode + ) +{ + return; +} + +osGLOBAL void ossaLogTrace1( + agsaRoot_t *agRoot, + bit32 traceCode, + bit32 value1 + ) +{ + return; +} + +osGLOBAL void ossaLogTrace2( + agsaRoot_t *agRoot, + bit32 traceCode, + bit32 value1, + bit32 value2 + ) +{ + return; +} + +osGLOBAL void ossaLogTrace3( + agsaRoot_t *agRoot, + bit32 traceCode, + bit32 value1, + bit32 value2, + bit32 value3 + ) +{ + return; +} + + +osGLOBAL void +ossaLogTrace4( + agsaRoot_t *agRoot, + bit32 traceCode, + bit32 value1, + bit32 value2, + bit32 value3, + bit32 value4 + ) +{ + return; +} + + +/***************************************************************************** +*! \brief ossaHwCB +* +* Purpose: This function is called by lower layer to inform TD layer of +* HW related results +* +* \param agRoot Pointer to chip/driver Instance. +* \param agPortContext Pointer to the port context of TD and Lower layer +* \param event event type +* \param eventParm1 event-specific parameter +* \param eventParm2 event-specific parameter +* \param eventParm3 event-specific parameter of pointer type +* +* \return: none +* +* \note - For details, refer to SAS/SATA Low-Level API Specification +* +*****************************************************************************/ +osGLOBAL void ossaHwCB( + agsaRoot_t *agRoot, + agsaPortContext_t *agPortContext, + bit32 event, + bit32 eventParm1, + void *eventParm2, + void *eventParm3 + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)osData->tdsaAllShared; + tdList_t *PortContextList = agNULL; + tdsaPortContext_t *onePortContext = agNULL; + agsaDevHandle_t *agDevHandle = agNULL; + agsaSASIdentify_t *IDframe = agNULL; + int i = 0; +#ifdef INITIATOR_DRIVER + tdsaSASSubID_t agSASSubID; +#endif + bit32 PhyID; + bit32 PhyStatus; + bit32 LinkRate; + bit32 PortState; + bit32 HwAckSatus = AGSA_RC_SUCCESS; + +// #ifdef INITIATOR_DRIVER +#ifdef INITIATOR_DRIVER + agsaFisRegDeviceToHost_t *RegD2H = agNULL; + tdsaDeviceData_t *oneDeviceData = agNULL; + tdList_t *DeviceListList; +#endif +#ifdef REMOVED + bit32 found = agFALSE; +#endif + agsaHWEventEncrypt_t *pEncryptCBData; + agsaEncryptInfo_t *pEncryptInfo; + agsaHWEventMode_t *pModeEvent; + tiEncryptPort_t encryptEventData; + tiEncryptInfo_t encryptInfo; + bit32 *pModePage; + bit32 securityMode; + bit32 cipherMode; + bit32 encryptStatus; + bit32 securitySetModeStatus; + bit32 securityModeStatus; + +// #endif /* INITIATOR_DRIVER */ + agsaPhyErrCountersPage_t *agPhyErrCountersPage; + agsaEventSource_t eventSource; + +#ifdef FDS_DM + dmRoot_t *dmRoot = &(tdsaAllShared->dmRoot); + dmPortContext_t *dmPortContext = agNULL; + bit32 status = DM_RC_FAILURE; + dmPortInfo_t dmPortInfo; +// bit32 discStatus = dmDiscInProgress; +#endif + + smTraceFuncEnter(hpDBG_VERY_LOUD,"Y2"); + + TI_DBG2(("ossaHwCB: agPortContext %p event 0x%x eventParm1 0x%x eventParm2 %p eventParm3 %p\n", + agPortContext,event,eventParm1,eventParm2,eventParm3 )); + + switch ( event ) + { + case OSSA_HW_EVENT_SAS_PHY_UP: + { + PhyID = TD_GET_PHY_ID(eventParm1); + LinkRate = TD_GET_LINK_RATE(eventParm1); + PortState = TD_GET_PORT_STATE(eventParm1); + agDevHandle = agNULL; + IDframe = (agsaSASIdentify_t *)eventParm3; + + + TI_DBG2(("ossaHwCB: Phy%d SAS link Up\n", PhyID)); + + if (agPortContext == agNULL) + { + TI_DBG1(("ossaHwCB: agPortContext null, wrong\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Y2"); + return; + } + if (agDevHandle == agNULL) + { + TI_DBG3(("ossaHwCB: agDevHandle null by design change\n")); + } + + if (IDframe == agNULL) + { + TI_DBG1(("ossaHwCB: IDframe null, wrong\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "Y2"); + return; + } + /* debugging only */ + if (LinkRate == 0x01) + { + TI_DBG1(("ossaHwCB: SAS Link Rate is 1.5 Gbps PhyID %d\n",PhyID)); + } + if (LinkRate == 0x02) + { + TI_DBG1(("ossaHwCB: SAS Link Rate is 3.0 Gbps PhyID %d\n",PhyID)); + } + if (LinkRate == 0x04) + { + TI_DBG1(("ossaHwCB: SAS Link Rate is 6.0 Gbps PhyID %d\n",PhyID)); + } + if (LinkRate == 0x08) + { + TI_DBG1(("ossaHwCB: SAS Link Rate is 12.0 Gbps PhyID %d\n",PhyID)); + } + + if (PortState == OSSA_PORT_INVALID) + { + TI_DBG1(("ossaHwCB: Wrong port state with SAS link up\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "Y2"); + return; + } + + if ( agPortContext->osData == agNULL) + {/* if */ + TI_DBG6 (("ossaHwCB: PhyID %d tdsaAllShared %p\n", PhyID, tdsaAllShared)); + if (tdsaAllShared->Ports[PhyID].tiPortalContext == agNULL) + { + TI_DBG6(("ossaHwCB: NULL portalcontext\n")); + } + else + { + TI_DBG6(("ossaHwCB: NOT NULL portalcontext\n")); + } + + if (IDframe == agNULL) + { + TI_DBG1(("ossaHwCB: IDFrame is NULL; SATA !!!!\n")); + } + else + { + TI_DBG3(("ossaHwCB: IDframe->sasAddressHi 0x%08x \n", + SA_IDFRM_GET_SAS_ADDRESSHI(IDframe))); + TI_DBG3(("ossaHwCB: IDframe->sasAddressLo 0x%08x \n", + SA_IDFRM_GET_SAS_ADDRESSLO(IDframe))); + + } + /* + setting tdsaPortContext fields + take the head from the FreeLink of tdsaPortContext_t + then modify it + then put it in MainLink of tdsaPortContext_t + */ + tdsaSingleThreadedEnter(tiRoot, TD_PORT_LOCK); + if (TDLIST_NOT_EMPTY(&(tdsaAllShared->FreePortContextList))) + { + TDLIST_DEQUEUE_FROM_HEAD(&PortContextList, &(tdsaAllShared->FreePortContextList)); + tdsaSingleThreadedLeave(tiRoot, TD_PORT_LOCK); + onePortContext = TDLIST_OBJECT_BASE(tdsaPortContext_t, FreeLink, PortContextList); + TI_DBG2(("ossaHwCB: pid %d\n", onePortContext->id)); + TI_DBG6(("ossaHwCB: onePortContext %p\n", onePortContext)); + if (onePortContext == agNULL) + { + TI_DBG1(("ossaHwCB: onePortContext is NULL in allocation, wrong!\n")); + return; + } + + /* sets fields of tdsaportcontext */ +#ifdef INITIATOR_DRIVER + onePortContext->DiscoveryState = ITD_DSTATE_NOT_STARTED; + onePortContext->discoveryOptions = AG_SA_DISCOVERY_OPTION_FULL_START; +#endif + onePortContext->PhyIDList[PhyID] = agTRUE; + if (IDframe == agNULL) + { + onePortContext->sasRemoteAddressHi = 0xFFFFFFFF; + onePortContext->sasRemoteAddressLo = 0xFFFFFFFF; + onePortContext->directAttatchedSAS = agTRUE; + } + else + { + onePortContext->sasRemoteAddressHi = SA_IDFRM_GET_SAS_ADDRESSHI(IDframe); + onePortContext->sasRemoteAddressLo = SA_IDFRM_GET_SAS_ADDRESSLO(IDframe); + /* Create ID frame and storing ID frame */ + osti_memcpy(&onePortContext->sasIDframe, IDframe, sizeof(agsaSASIdentify_t)); + tdhexdump("ossaHWCB: sasIDframe", (bit8 *)(&onePortContext->sasIDframe), sizeof(agsaSASIdentify_t)); + if (SA_IDFRM_GET_DEVICETTYPE(IDframe) == SAS_END_DEVICE) + { + onePortContext->directAttatchedSAS = agTRUE; + } +#ifdef FDS_DM + if (SA_IDFRM_GET_DEVICETTYPE(IDframe) == SAS_EDGE_EXPANDER_DEVICE || + SA_IDFRM_GET_DEVICETTYPE(IDframe) == SAS_FANOUT_EXPANDER_DEVICE + ) + { + onePortContext->UseDM = agTRUE; + } +#endif + } + + onePortContext->sasLocalAddressHi = SA_IDFRM_GET_SAS_ADDRESSHI(&tdsaAllShared->Ports[PhyID].SASID); + onePortContext->sasLocalAddressLo = SA_IDFRM_GET_SAS_ADDRESSLO(&tdsaAllShared->Ports[PhyID].SASID); + onePortContext->tiPortalContext = tdsaAllShared->Ports[PhyID].tiPortalContext; + onePortContext->agRoot = agRoot; + onePortContext->agPortContext = agPortContext; + tdsaAllShared->Ports[PhyID].portContext = onePortContext; + agPortContext->osData = onePortContext; + onePortContext->valid = agTRUE; + if (LinkRate == 0x01) + { + onePortContext->LinkRate = SAS_CONNECTION_RATE_1_5G; + } + else if (LinkRate == 0x02) + { + onePortContext->LinkRate = SAS_CONNECTION_RATE_3_0G; + } + else if (LinkRate == 0x04) + { + onePortContext->LinkRate = SAS_CONNECTION_RATE_6_0G; + } + else /* (LinkRate == 0x08) */ + { + onePortContext->LinkRate = SAS_CONNECTION_RATE_12_0G; + } + + tdsaSingleThreadedEnter(tiRoot, TD_PORT_LOCK); + TDLIST_ENQUEUE_AT_TAIL(&(onePortContext->MainLink), &(tdsaAllShared->MainPortContextList)); + tdsaSingleThreadedLeave(tiRoot, TD_PORT_LOCK); +#ifdef FDS_DM + dmPortContext = &(onePortContext->dmPortContext); + dmPortContext->tdData = onePortContext; + /* set up dmPortInfo_t */ + PORTINFO_PUT_SAS_REMOTE_ADDRESSLO(&dmPortInfo, onePortContext->sasRemoteAddressLo); + PORTINFO_PUT_SAS_REMOTE_ADDRESSHI(&dmPortInfo, onePortContext->sasRemoteAddressHi); + PORTINFO_PUT_SAS_LOCAL_ADDRESSLO(&dmPortInfo, onePortContext->sasLocalAddressLo); + PORTINFO_PUT_SAS_LOCAL_ADDRESSHI(&dmPortInfo, onePortContext->sasLocalAddressHi); + + TI_DBG2(("ossaHwCB: phy %d hi 0x%x lo 0x%x\n", PhyID, + SA_IDFRM_GET_SAS_ADDRESSHI(&(tdsaAllShared->Ports[PhyID].SASID)), + SA_IDFRM_GET_SAS_ADDRESSLO(&(tdsaAllShared->Ports[PhyID].SASID)))); + TI_DBG2(("ossaHwCB: LocalAddrHi 0x%08x LocaAddrLo 0x%08x\n", onePortContext->sasLocalAddressHi, onePortContext->sasLocalAddressLo)); + + dmPortInfo.flag = onePortContext->LinkRate; + + if (onePortContext->UseDM == agTRUE) + { + TI_DBG1(("ossaHwCB: calling dmCreatePort\n")); + status = dmCreatePort(dmRoot, dmPortContext, &dmPortInfo); + if (status != DM_RC_SUCCESS) + { + TI_DBG1(("ossaHwCB: dmCreatePort failed!!! 0x%x\n", status)); + } + } +#endif + + } + else + { + tdsaSingleThreadedLeave(tiRoot, TD_PORT_LOCK); + TI_DBG1(("\nossaHwCB: Attention!!! no more free PortContext.\n")); + } +#ifdef TD_INTERNAL_DEBUG /* for debugging only */ + + print_tdlist_flink(&(tdsaPortContext->FreeLink), 1, 1); + print_tdlist_flink(&(tdsaPortContext->MainLink), 1, 2); + print_tdlist_flink(&(tdsaDeviceData->FreeLink), 2, 1); + print_tdlist_flink(&(tdsaDeviceData->MainLink), 2, 2); +#endif + +#ifdef TD_INTERNAL_DEBUG /* for debugging */ + PortContextList = tdsaPortContext->MainLink.flink; + while (PortContextList != &(tdsaPortContext->MainLink)) + { + twoPortContext = TDLIST_OBJECT_BASE(tdsaPortContext_t, MainLink, PortContextList); + TI_DBG6(("ossaHwCB: in while portContext ID %d\n", twoPortContext->id)); + TI_DBG6(("ossaHwCB: in while PortContext %p\n", twoPortContext)); + PortContextList = PortContextList->flink; + } +#endif + /* add agDevHandle */ + if (SA_IDFRM_GET_DEVICETTYPE(IDframe) != SAS_NO_DEVICE) + { +#ifdef INITIATOR_DRIVER + agSASSubID.sasAddressHi = SA_IDFRM_GET_SAS_ADDRESSHI(IDframe); + agSASSubID.sasAddressLo = SA_IDFRM_GET_SAS_ADDRESSLO(IDframe); + agSASSubID.initiator_ssp_stp_smp = IDframe->initiator_ssp_stp_smp; + agSASSubID.target_ssp_stp_smp = IDframe->target_ssp_stp_smp; +#endif + + TI_DBG2(("ossaHwCB: adding ....\n")); + /* uses only SASIDframe not agsaSASDeviceInfo_t */ +#ifdef INITIATOR_DRIVER + tdssAddSASToSharedcontext( + onePortContext, + agRoot, + agDevHandle, /* agNULL */ + &agSASSubID, + agTRUE, + (bit8)PhyID, + TD_OPERATION_INITIATOR + ); +#endif + +#ifdef FDS_DM + if (SA_IDFRM_GET_DEVICETTYPE(IDframe) == SAS_END_DEVICE && + SA_IDFRM_IS_SSP_TARGET(IDframe) ) + { + TI_DBG2(("ossaHwCB: NOTIFY_ENABLE_SPINUP PhyID %d \n", PhyID)); + + for (i=0;iPorts[PhyID].tiPortalContext + ); +#endif + } + else + { + TI_DBG5(("ossaHwCB: $$$$$ not end device. not adding....\n")); + } + + saPortControl(agRoot, /* AGSA_PORT_SET_PORT_RECOVERY_TIME */ + agNULL, + 0, + agPortContext, + AGSA_PORT_SET_PORT_RECOVERY_TIME, + tdsaAllShared->portTMO, //PORT_RECOVERY_TIMEOUT + 0 + ); + /* setting SAS PORT RESET TMO and SATA PORT RESET TMO*/ + if (tIsSPCV12G(agRoot)) + { + saPortControl(agRoot, /* AGSA_PORT_SET_PORT_RESET_TIME */ + agNULL, + 0, + agPortContext, + AGSA_PORT_SET_PORT_RESET_TIME, + SAS_12G_PORT_RESET_TMO, // 800 ms + 0 + ); + } + else + { + saPortControl(agRoot, /* AGSA_PORT_SET_PORT_RESET_TIME */ + agNULL, + 0, + agPortContext, + AGSA_PORT_SET_PORT_RESET_TIME, + SAS_PORT_RESET_TMO, // 300 ms + 0 + ); + } + } + else + { + /* + an existing portcontext + to be tested + */ + + TI_DBG2(("ossaHwCB: SAS existing portcontext returned\n")); + + onePortContext = (tdsaPortContext_t *)agPortContext->osData; + if (onePortContext == agNULL) + { + TI_DBG1(("ossaHwCB: onePortContext is NULL, wrong!\n")); + return; + } + if (onePortContext->valid == agFALSE) + { + /* port has been invalidated; needs to be allocated */ + TI_DBG2(("ossaHwCB: SAS allocating port context\n")); + + tdsaSingleThreadedEnter(tiRoot, TD_PORT_LOCK); + if (TDLIST_NOT_EMPTY(&(tdsaAllShared->FreePortContextList))) + { + TDLIST_DEQUEUE_FROM_HEAD(&PortContextList, &(tdsaAllShared->FreePortContextList)); + tdsaSingleThreadedLeave(tiRoot, TD_PORT_LOCK); + onePortContext = TDLIST_OBJECT_BASE(tdsaPortContext_t, FreeLink, PortContextList); + TI_DBG2(("ossaHwCB: allocating pid %d\n", onePortContext->id)); + TI_DBG6(("ossaHwCB: allocating onePortContext %p\n", onePortContext)); + if (onePortContext == agNULL) + { + TI_DBG1(("ossaHwCB: onePortContext is NULL in allocation, wrong!\n")); + return; + } + /* sets fields of tdsaportcontext */ +#ifdef INITIATOR_DRIVER + onePortContext->DiscoveryState = ITD_DSTATE_NOT_STARTED; + onePortContext->discoveryOptions = AG_SA_DISCOVERY_OPTION_FULL_START; +#endif + onePortContext->PhyIDList[PhyID] = agTRUE; + if (IDframe == agNULL) + { + onePortContext->sasRemoteAddressHi = 0xFFFFFFFF; + onePortContext->sasRemoteAddressLo = 0xFFFFFFFF; + onePortContext->directAttatchedSAS = agTRUE; + } + else + { + onePortContext->sasRemoteAddressHi = SA_IDFRM_GET_SAS_ADDRESSHI(IDframe); + onePortContext->sasRemoteAddressLo = SA_IDFRM_GET_SAS_ADDRESSLO(IDframe); + /* Create ID frame and storing ID frame */ + osti_memcpy(&onePortContext->sasIDframe, IDframe, sizeof(agsaSASIdentify_t)); + tdhexdump("ossaHWCB: sasIDframe", (bit8 *)(&onePortContext->sasIDframe), sizeof(agsaSASIdentify_t)); + if (SA_IDFRM_GET_DEVICETTYPE(IDframe) == SAS_END_DEVICE) + { + onePortContext->directAttatchedSAS = agTRUE; + } + } + + onePortContext->sasLocalAddressHi = SA_IDFRM_GET_SAS_ADDRESSHI(&tdsaAllShared->Ports[PhyID].SASID); + onePortContext->sasLocalAddressLo = SA_IDFRM_GET_SAS_ADDRESSLO(&tdsaAllShared->Ports[PhyID].SASID); + onePortContext->tiPortalContext = tdsaAllShared->Ports[PhyID].tiPortalContext; + onePortContext->agRoot = agRoot; + onePortContext->agPortContext = agPortContext; + tdsaAllShared->Ports[PhyID].portContext = onePortContext; + agPortContext->osData = onePortContext; + onePortContext->valid = agTRUE; + if (LinkRate == 0x01) + { + onePortContext->LinkRate = SAS_CONNECTION_RATE_1_5G; + } + else if (LinkRate == 0x02) + { + onePortContext->LinkRate = SAS_CONNECTION_RATE_3_0G; + } + else if (LinkRate == 0x04) + { + onePortContext->LinkRate = SAS_CONNECTION_RATE_6_0G; + } + else /* (LinkRate == 0x08) */ + { + onePortContext->LinkRate = SAS_CONNECTION_RATE_12_0G; + } + tdsaSingleThreadedEnter(tiRoot, TD_PORT_LOCK); + TDLIST_ENQUEUE_AT_TAIL(&(onePortContext->MainLink), &(tdsaAllShared->MainPortContextList)); + tdsaSingleThreadedLeave(tiRoot, TD_PORT_LOCK); + } + else + { + tdsaSingleThreadedLeave(tiRoot, TD_PORT_LOCK); + TI_DBG1(("\nossaHwCB: Attention!!! no more free PortContext.\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "Y2"); + return; + } + } /* invalidated port */ + else + { + /* already alloacated */ + TI_DBG2(("ossaHwCB: SAS already allocated port context\n")); + if (TDLIST_EMPTY(&(tdsaAllShared->MainPortContextList))) + { + TI_DBG1(("ossaHwCB: wrong!!! null tdsaPortContext list\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "Y2"); + return; + } + if (onePortContext == agNULL) + { + TI_DBG1(("ossaHwCB: wrong !!! No corressponding tdsaPortContext\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'f', "Y2"); + return; + } + + TI_DBG2(("ossaHwCB: existing pid %d\n", onePortContext->id)); + if (tdsaAllShared->Ports[PhyID].portContext == agNULL) + { + TI_DBG1(("ossaHwCB: existing allshared pid is NULL\n")); + } + else + { + TI_DBG2(("ossaHwCB: existing allshared pid %d\n", tdsaAllShared->Ports[PhyID].portContext->id)); + } + /* updates PhyID belong to a port */ + onePortContext->PhyIDList[PhyID] = agTRUE; +#ifdef FDS_DM + if (SA_IDFRM_GET_DEVICETTYPE(IDframe) == SAS_END_DEVICE && + SA_IDFRM_IS_SSP_TARGET(IDframe) ) + { + TI_DBG2(("ossaHwCB: NOTIFY_ENABLE_SPINUP PhyID %d \n", PhyID)); + + for (i=0;iSeenLinkUp = agTRUE; + } /* else, old portcontext */ + + break; + } +#ifdef INITIATOR_DRIVER + case OSSA_HW_EVENT_SATA_PHY_UP: + { + PhyID = TD_GET_PHY_ID(eventParm1); + LinkRate = TD_GET_LINK_RATE(eventParm1); + PortState = TD_GET_PORT_STATE(eventParm1); + agDevHandle = agNULL; + RegD2H = ( agsaFisRegDeviceToHost_t *)eventParm3; + + TI_DBG2(("ossaHwCB: Phy%d SATA link Up\n", PhyID)); + + if (agDevHandle == agNULL) + { + TI_DBG3(("ossaHwCB: agDevHandle null by design change\n")); + } + + if (RegD2H == agNULL) + { + TI_DBG1(("ossaHwCB: RegD2H null, wrong\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'g', "Y2"); + return; + } + + + TI_DBG2(("ossaHwCB: agDevHandle %p\n", agDevHandle)); + tdhexdump("ossaHWCB RegD2H", (bit8 *)RegD2H, sizeof(agsaFisRegDeviceToHost_t)); + TI_DBG2(("ossaHwCB: Sector Count %d\n", RegD2H->d.sectorCount)); + TI_DBG2(("ossaHwCB: LBA LOW %d\n", RegD2H->d.lbaLow)); + TI_DBG2(("ossaHwCB: LBA MID %d\n", RegD2H->d.lbaMid)); + TI_DBG2(("ossaHwCB: LBA HIGH %d\n", RegD2H->d.lbaHigh)); + TI_DBG2(("ossaHwCB: DEVICE %d\n", RegD2H->d.device)); + + /* debugging only */ + if (LinkRate == 0x01) + { + TI_DBG1(("ossaHwCB: SATA Link Rate is 1.5 Gbps PhyID %d\n",PhyID)); + } + if (LinkRate == 0x02) + { + TI_DBG1(("ossaHwCB: SATA Link Rate is 3.0 Gbps PhyID %d\n",PhyID)); + } + if (LinkRate == 0x04) + { + TI_DBG1(("ossaHwCB: SATA Link Rate is 6.0 Gbps PhyID %d\n",PhyID)); + } + if (LinkRate == 0x08) + { + TI_DBG1(("ossaHwCB: SATA Link Rate is 12.0 Gbps PhyID %d\n",PhyID)); + } + + if (PortState == OSSA_PORT_INVALID) + { + TI_DBG1(("ossaHwCB: Wrong port state with SATA link up\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'h', "Y2"); + return; + } + + if ( agPortContext->osData == agNULL) + {/* if */ + TI_DBG6 (("ossaHwCB: PhyID %d tdsaAllShared %p\n", PhyID, tdsaAllShared)); + tdsaSingleThreadedEnter(tiRoot, TD_PORT_LOCK); + if (TDLIST_NOT_EMPTY(&(tdsaAllShared->FreePortContextList))) + { + TDLIST_DEQUEUE_FROM_HEAD(&PortContextList, &(tdsaAllShared->FreePortContextList)); + tdsaSingleThreadedLeave(tiRoot, TD_PORT_LOCK); + onePortContext = TDLIST_OBJECT_BASE(tdsaPortContext_t, FreeLink, PortContextList); + TI_DBG2(("ossaHwCB: pid %d\n", onePortContext->id)); + TI_DBG6(("ossaHwCB: onePortContext %p\n", onePortContext)); + if (onePortContext == agNULL) + { + TI_DBG1(("ossaHwCB: onePortContext is NULL in allocation, wrong!\n")); + return; + } + + /* sets fields of tdsaportcontext */ + onePortContext->DiscoveryState = ITD_DSTATE_NOT_STARTED; + onePortContext->discoveryOptions = AG_SA_DISCOVERY_OPTION_FULL_START; + onePortContext->PhyIDList[PhyID] = agTRUE; + /* NO sas address for SATA */ + onePortContext->sasRemoteAddressHi = 0xFFFFFFFF; + onePortContext->sasRemoteAddressLo = 0xFFFFFFFF; + /* copying the signature */ + onePortContext->remoteSignature[0] = RegD2H->d.sectorCount; + onePortContext->remoteSignature[1] = RegD2H->d.lbaLow; + onePortContext->remoteSignature[2] = RegD2H->d.lbaMid; + onePortContext->remoteSignature[3] = RegD2H->d.lbaHigh; + onePortContext->remoteSignature[4] = RegD2H->d.device; + + onePortContext->sasLocalAddressHi = SA_IDFRM_GET_SAS_ADDRESSHI(&tdsaAllShared->Ports[PhyID].SASID); + onePortContext->sasLocalAddressLo = SA_IDFRM_GET_SAS_ADDRESSLO(&tdsaAllShared->Ports[PhyID].SASID); + onePortContext->tiPortalContext = tdsaAllShared->Ports[PhyID].tiPortalContext; + onePortContext->agRoot = agRoot; + onePortContext->agPortContext = agPortContext; + tdsaAllShared->Ports[PhyID].portContext = onePortContext; + agPortContext->osData = onePortContext; + onePortContext->nativeSATAMode = agTRUE; + onePortContext->valid = agTRUE; + if (LinkRate == 0x01) + { + onePortContext->LinkRate = SAS_CONNECTION_RATE_1_5G; + } + else if (LinkRate == 0x02) + { + onePortContext->LinkRate = SAS_CONNECTION_RATE_3_0G; + } + else if (LinkRate == 0x04) + { + onePortContext->LinkRate = SAS_CONNECTION_RATE_6_0G; + } + else /* (LinkRate == 0x08) */ + { + onePortContext->LinkRate = SAS_CONNECTION_RATE_12_0G; + } + + tdsaSingleThreadedEnter(tiRoot, TD_PORT_LOCK); + TDLIST_ENQUEUE_AT_TAIL(&(onePortContext->MainLink), &(tdsaAllShared->MainPortContextList)); + tdsaSingleThreadedLeave(tiRoot, TD_PORT_LOCK); + } + else + { + tdsaSingleThreadedLeave(tiRoot, TD_PORT_LOCK); + TI_DBG1(("\nossaHwCB: Attention!!! no more free PortContext.\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'i', "Y2"); + return; + } +#ifdef SATA_ENABLE + /* tdssAddSATAToSharedcontext() sends identify device data to find out the uniqueness of + target. In identify device data CB fn (satAddSATAIDDevCB()), + tiPortLinkUp and tiPortDiscoveryReady happen + */ + tdssAddSATAToSharedcontext( + onePortContext, + agRoot, + agDevHandle, /* agNULL */ + agNULL, + agTRUE, + (bit8)PhyID + ); +#endif + /* setting SAS PORT RESET TMO and SATA PORT RESET TMO*/ + saPortControl(agRoot, /* AGSA_PORT_SET_PORT_RESET_TIME */ + agNULL, + 0, + agPortContext, + AGSA_PORT_SET_PORT_RESET_TIME, + 0, + SATA_PORT_RESET_TMO // 8000 ms + ); + + } + else + { + /* + an existing portcontext + to be tested + */ + + TI_DBG1(("ossaHwCB: SATA existing portcontext returned. need testing\n")); + onePortContext = (tdsaPortContext_t *)agPortContext->osData; + /* for debugging only */ + if (onePortContext->valid == agFALSE) + { + /* port has been invalidated; needs to be allocated */ + TI_DBG2(("ossaHwCB: SATA allocating port context\n")); + } + else + { + /* already alloacated */ + TI_DBG1(("ossaHwCB: Wrong!!! SATA already allocated port context\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'j', "Y2"); + return; + } + + tdsaSingleThreadedEnter(tiRoot, TD_PORT_LOCK); + if (TDLIST_NOT_EMPTY(&(tdsaAllShared->FreePortContextList))) + { + TDLIST_DEQUEUE_FROM_HEAD(&PortContextList, &(tdsaAllShared->FreePortContextList)); + tdsaSingleThreadedLeave(tiRoot, TD_PORT_LOCK); + onePortContext = TDLIST_OBJECT_BASE(tdsaPortContext_t, FreeLink, PortContextList); + TI_DBG2(("ossaHwCB: pid %d\n", onePortContext->id)); + TI_DBG6(("ossaHwCB: onePortContext %p\n", onePortContext)); + if (onePortContext == agNULL) + { + TI_DBG1(("ossaHwCB: onePortContext is NULL in allocation, wrong!\n")); + return; + } + + /* sets fields of tdsaportcontext */ + onePortContext->DiscoveryState = ITD_DSTATE_NOT_STARTED; + onePortContext->discoveryOptions = AG_SA_DISCOVERY_OPTION_FULL_START; + onePortContext->PhyIDList[PhyID] = agTRUE; + /* NO sas address for SATA */ + onePortContext->sasRemoteAddressHi = 0xFFFFFFFF; + onePortContext->sasRemoteAddressLo = 0xFFFFFFFF; + /* copying the signature */ + onePortContext->remoteSignature[0] = RegD2H->d.sectorCount; + onePortContext->remoteSignature[1] = RegD2H->d.lbaLow; + onePortContext->remoteSignature[2] = RegD2H->d.lbaMid; + onePortContext->remoteSignature[3] = RegD2H->d.lbaHigh; + onePortContext->remoteSignature[4] = RegD2H->d.device; + + onePortContext->sasLocalAddressHi = SA_IDFRM_GET_SAS_ADDRESSHI(&tdsaAllShared->Ports[PhyID].SASID); + onePortContext->sasLocalAddressLo = SA_IDFRM_GET_SAS_ADDRESSLO(&tdsaAllShared->Ports[PhyID].SASID); + onePortContext->tiPortalContext = tdsaAllShared->Ports[PhyID].tiPortalContext; + onePortContext->agRoot = agRoot; + onePortContext->agPortContext = agPortContext; + tdsaAllShared->Ports[PhyID].portContext = onePortContext; + agPortContext->osData = onePortContext; + onePortContext->nativeSATAMode = agTRUE; + onePortContext->valid = agTRUE; + if (LinkRate == 0x01) + { + onePortContext->LinkRate = SAS_CONNECTION_RATE_1_5G; + } + else if (LinkRate == 0x02) + { + onePortContext->LinkRate = SAS_CONNECTION_RATE_3_0G; + } + else if (LinkRate == 0x04) + { + onePortContext->LinkRate = SAS_CONNECTION_RATE_6_0G; + } + else /* (LinkRate == 0x08) */ + { + onePortContext->LinkRate = SAS_CONNECTION_RATE_12_0G; + } + + tdsaSingleThreadedEnter(tiRoot, TD_PORT_LOCK); + TDLIST_ENQUEUE_AT_TAIL(&(onePortContext->MainLink), &(tdsaAllShared->MainPortContextList)); + tdsaSingleThreadedLeave(tiRoot, TD_PORT_LOCK); + } + else + { + tdsaSingleThreadedLeave(tiRoot, TD_PORT_LOCK); + TI_DBG1(("\nossaHwCB: Attention!!! no more free PortContext.\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'k', "Y2"); + return; + } + + + /*hotplug */ +#ifdef SATA_ENABLE + tdssAddSATAToSharedcontext( + onePortContext, + agRoot, + agDevHandle, /* agNULL */ + agNULL, + agTRUE, + (bit8)PhyID + ); +#endif + /* end hotplug */ + } + + break; + } +#endif + case OSSA_HW_EVENT_SATA_SPINUP_HOLD: + { + PhyID = TD_GET_PHY_ID(eventParm1); + + TI_DBG2(("ossaHwCB: spinup hold PhyID %d\n", PhyID)); + break; + } + + case OSSA_HW_EVENT_PHY_DOWN: + { + bit32 AllPhyDown = agTRUE; + + /* 4/15/08 spec */ + PhyID = TD_GET_PHY_ID(eventParm1); + LinkRate = TD_GET_LINK_RATE(eventParm1); + PortState = TD_GET_PORT_STATE(eventParm1); + + + TI_DBG2(("ossaHwCB: Phy%d link Down\n", PhyID)); + + if (agPortContext == agNULL) + { + TI_DBG1(("ossaHwCB: agPortContext null, wrong\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'l', "Y2"); + return; + } + + if ( agPortContext->osData == agNULL) + { /* if */ + /* PortContext must exit at this point */ + TI_DBG1(("ossaHwCB: NULL portalcontext. Error. Can't be NULL\n")); + } + else + { + TI_DBG3(("ossaHwCB: NOT NULL portalcontext\n")); + onePortContext = (tdsaPortContext_t *)agPortContext->osData; + if (onePortContext == agNULL) + { + TI_DBG1(("ossaHwCB: wrong !!! No corressponding tdsaPortContext\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'm', "Y2"); + return; + } + onePortContext->PhyIDList[PhyID] = agFALSE; + for(i=0;iPhyIDList[i] == agTRUE) + { + TI_DBG3(("ossaHwCB: Phy %d is still up\n", i)); + AllPhyDown = agFALSE; + break; + } + } + + /* last phy belong to the portcontext */ + if (AllPhyDown == agTRUE) + { +#ifdef NOT_YET + TI_DBG1(("ossaHwCB: calling tiPortLinkDown\n")); + ostiPortEvent ( + tiRoot, + tiPortLinkDown, + tiSuccess, + (void *)onePortContext->tiPortalContext + ); +#endif + } + + if (PortState == OSSA_PORT_VALID) + { + /* do nothing */ + /* no ack for every phy down */ +#ifdef FDS_DM + /* update MCN for all devices belong to this port */ + tdsaUpdateMCN(dmRoot, onePortContext); +#endif + } + else if (PortState == OSSA_PORT_LOSTCOMM) + { + /* + 1. Mark the port as invalid and stop the io for that port and its device + No ack here. Otherwise, port will be released by FW. + */ + TI_DBG2(("ossaHwCB: phy Down and OSSA_PORT_LOSTCOMM\n")); + /* save eventSource related information in tdsaAllShared */ + tdsaAllShared->eventSource[PhyID].EventValid = agTRUE; + tdsaAllShared->eventSource[PhyID].Source.agPortContext = agPortContext; + tdsaAllShared->eventSource[PhyID].Source.event = OSSA_HW_EVENT_PHY_DOWN; + /* phy ID */ + tdsaAllShared->eventSource[PhyID].Source.param = PhyID; + /* phy ID */ + onePortContext->eventPhyID = PhyID; + /* to stop IO's */ + onePortContext->valid = agFALSE; + break; + } + else if (PortState == OSSA_PORT_IN_RESET) + { + TI_DBG2(("ossaHwCB: phy Down and OSSA_PORT_IN_RESET\n")); + /* save eventSource related information in tdsaAllShared */ + tdsaAllShared->eventSource[PhyID].EventValid = agTRUE; + tdsaAllShared->eventSource[PhyID].Source.agPortContext = agPortContext; + tdsaAllShared->eventSource[PhyID].Source.event = OSSA_HW_EVENT_PHY_DOWN; + /* phy ID */ + tdsaAllShared->eventSource[PhyID].Source.param = PhyID; + /* phy ID */ + onePortContext->eventPhyID = PhyID; + /* to stop IO's */ + onePortContext->valid = agFALSE; + break; + } + else if (PortState == OSSA_PORT_INVALID) + { + TI_DBG1(("ossaHwCB: Last phy Down and port invalid OSSA_PORT_INVALID\n")); + /* + invalidate port + then, saHwEventAck() in ossaDeregisterDeviceHandleCB() + */ + + /* save eventSource related information in tdsaAllShared */ + tdsaAllShared->eventSource[PhyID].EventValid = agTRUE; + tdsaAllShared->eventSource[PhyID].Source.agPortContext = agPortContext; + tdsaAllShared->eventSource[PhyID].Source.event = OSSA_HW_EVENT_PHY_DOWN; + /* phy ID */ + tdsaAllShared->eventSource[PhyID].Source.param = PhyID; + /* phy ID */ + onePortContext->eventPhyID = PhyID; + + onePortContext->valid = agFALSE; + + TI_DBG2(("ossaHwCB: pid %d\n", onePortContext->id)); +#ifdef INITIATOR_DRIVER + /* notifying link down (all links belonging to a port are down) */ + ostiPortEvent( + tiRoot, + tiPortStopped, + tiSuccess, + (void *)onePortContext->tiPortalContext + ); +#endif + +#ifdef TARGET_DRIVER + ostiPortEvent( + tiRoot, + tiPortLinkDown, + tiSuccess, + (void *)onePortContext->tiPortalContext + ); + +#endif + +#ifdef INITIATOR_DRIVER + tdssReportRemovals(agRoot, + onePortContext, + agFALSE + ); +#endif +#ifdef TARGET_DRIVER + ttdssReportRemovals(agRoot, + onePortContext, + agFALSE + ); + +#endif + + /* find a PhyID and reset for portContext in tdssSASShared */ + for(i=0;iPhyIDList[i] == agTRUE) + { + tdsaAllShared->Ports[i].portContext = agNULL; + } + } + /* portcontext is removed from MainLink to FreeLink in tdssReportRemovals or + ossaDeregisterDeviceHandleCB + */ + }/* OSSA_PORT_INVALID */ + else + { + /* other newly defined port state */ + /* do nothing */ + TI_DBG2(("ossaHwCB: portstate 0x%x\n", PortState)); + } + } /* big else */ + break; + } + case OSSA_HW_EVENT_PHY_START_STATUS: + { + PhyID = TD_GET_PHY_ID(eventParm1); + PhyStatus = TD_GET_PHY_STATUS(eventParm1); + + TI_DBG6(("ossaHwCB: OSSA_HW_EVENT_PHY_START_STATUS\n")); + if (PhyStatus == 0x00) + { + TI_DBG6(("ossaHwCB: OSSA_HW_EVENT_PHY_START_STATUS, SUCCESS\n")); + } + else if (PhyStatus == 0x01) + { + TI_DBG1(("ossaHwCB: OSSA_HW_EVENT_PHY_START_STATUS, INVALID_PHY\n")); + } + else if (PhyStatus == 0x02) + { + TI_DBG1(("ossaHwCB: OSSA_HW_EVENT_PHY_START_STATUS, PHY_NOT_DISABLED\n")); + } + else + { + TI_DBG1(("ossaHwCB: OSSA_HW_EVENT_PHY_START_STATUS, OTHER_FAILURE %d\n", PhyStatus)); + } + break; + } + case OSSA_HW_EVENT_PHY_STOP_STATUS: + { + agsaContext_t *agContext; + PhyID = TD_GET_PHY_ID(eventParm1); + PhyStatus = TD_GET_PHY_STATUS(eventParm1); + PortState = TD_GET_PORT_STATE(eventParm1); + + TI_DBG2(("ossaHwCB: OSSA_HW_EVENT_PHY_STOP_STATUS\n")); + if (PhyStatus == 0x00) + { + TI_DBG1(("ossaHwCB: OSSA_HW_EVENT_PHY_STOP_STATUS, SUCCESS\n")); + agContext = (agsaContext_t *)eventParm2; + onePortContext = (tdsaPortContext_t *)agContext->osData;; + if (onePortContext == agNULL) + { + TI_DBG1(("ossaHwCB: onePortContext is null, wrong!!!\n")); + return; + } + onePortContext->PhyIDList[PhyID] = agFALSE; + if (PortState == OSSA_PORT_INVALID) /* invalid port */ + { + TI_DBG1(("ossaHwCB: OSSA_PORT_INVALID\n")); + tdsaAllShared->eventSource[PhyID].EventValid = NO_ACK; + onePortContext->eventPhyID = PhyID; + onePortContext->valid = agFALSE; + + TI_DBG2(("ossaHwCB: pid %d\n", onePortContext->id)); +#ifdef INITIATOR_DRIVER + /* notifying link down (all links belonging to a port are down) */ + ostiPortEvent( + tiRoot, + tiPortStopped, + tiSuccess, + (void *)onePortContext->tiPortalContext + ); +#endif + +#ifdef TARGET_DRIVER + ostiPortEvent( + tiRoot, + tiPortLinkDown, + tiSuccess, + (void *)onePortContext->tiPortalContext + ); + +#endif + +#ifdef INITIATOR_DRIVER + tdssReportRemovals(agRoot, + onePortContext, + agFALSE + ); +#endif +#ifdef TARGET_DRIVER + ttdssReportRemovals(agRoot, + onePortContext, + agFALSE + ); + +#endif + + /* find a PhyID and reset for portContext in tdssSASShared */ + for(i=0;iPhyIDList[i] == agTRUE) + { + tdsaAllShared->Ports[i].portContext = agNULL; + } + } + /* portcontext is removed from MainLink to FreeLink in tdssReportRemovals or + ossaDeregisterDeviceHandleCB + */ + } /* invalid port */ + } + else if (PhyStatus == 0x01) + { + TI_DBG1(("ossaHwCB: OSSA_HW_EVENT_PHY_STOP_STATUS, INVALID_PHY\n")); + } + else if (PhyStatus == 0x02) + { + TI_DBG1(("ossaHwCB: OSSA_HW_EVENT_PHY_STOP_STATUS, DEVICES_ATTACHED\n")); + } + else if (PhyStatus == 0x03) + { + TI_DBG1(("ossaHwCB: OSSA_HW_EVENT_PHY_STOP_STATUS, OTHER_FAILURE\n")); + } + else if (PhyStatus == 0x04) + { + TI_DBG1(("ossaHwCB: OSSA_HW_EVENT_PHY_STOP_STATUS, PHY_NOT_DISABLED\n")); + } + else + { + TI_DBG1(("ossaHwCB: OSSA_HW_EVENT_PHY_STOP_STATUS, Unknown %d\n", PhyStatus)); + } + break; + } + + case OSSA_HW_EVENT_RESET_START: + { + bit32 new_status = TD_GET_RESET_STATUS(eventParm1); + TI_DBG2(("ossaHwCB: RESET_START, status %d\n", new_status)); + if (new_status == OSSA_SUCCESS) + { + tdsaAllShared->flags.resetInProgress = agTRUE; + TI_DBG2(("ossaHwCB: RESET_START, SUCCESS\n")); + } + else if (new_status == OSSA_FAILURE) + { + TI_DBG1(("ossaHwCB: RESET_START, FAILURE\n")); + } + else + { + TI_DBG1(("ossaHwCB: RESET_START, PENDING\n")); + } + break; + } + + case OSSA_HW_EVENT_RESET_COMPLETE: + { + bit32 new_status = TD_GET_RESET_STATUS(eventParm1); +#ifdef SOFT_RESET_TEST + DbgPrint("Reset Complete\n"); +#endif + TI_DBG1(("ossaHwCB: OSSA_HW_EVENT_RESET_COMPLETE, status %d\n", new_status)); + if (new_status == OSSA_SUCCESS) + { + /* remove all portcontext and devices */ +#ifdef INITIATOR_DRIVER + tdssRemoveSASSATAFromSharedcontextByReset(agRoot); +#endif + tdsaAllShared->flags.resetInProgress = agFALSE; + /* + a callback notifying reset completion + */ + ostiPortEvent( + tiRoot, + tiPortResetComplete, + tiSuccess, + agNULL + ); + } + else + { + /* + a callback notifying reset completion + */ + tdsaAllShared->flags.resetInProgress = agFALSE; + ostiPortEvent( + tiRoot, + tiPortResetComplete, + tiError, + agNULL + ); + + } + break; + } + + case OSSA_HW_EVENT_PHY_ERR_INBOUND_CRC: + { + PhyID = TD_GET_PHY_ID(eventParm1); + PortState = TD_GET_PORT_STATE(eventParm1); + agPhyErrCountersPage = (agsaPhyErrCountersPage_t *)eventParm2; + + TI_DBG1(("ossaHwCB: OSSA_HW_EVENT_PHY_ERR_INBOUND_CRC from PhyID %d; to be tested\n", PhyID)); + + if (PortState == OSSA_PORT_INVALID) + { + TI_DBG1(("ossaHwCB: Wrong port state with OSSA_HW_EVENT_PHY_ERR_INBOUND_CRC\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'n', "Y2"); + return; + } + + if (agPhyErrCountersPage != agNULL) + { + TI_DBG2(("ossaHwCB: OSSA_HW_EVENT_PHY_ERR_INBOUND_CRC from PhyID %d\n", PhyID)); + TI_DBG1(("ossaHwCB: iDw %d rDE %d cV %d lS %d rP %d iCRC %d\n", + agPhyErrCountersPage->invalidDword, + agPhyErrCountersPage->runningDisparityError, + agPhyErrCountersPage->codeViolation, + agPhyErrCountersPage->lossOfDwordSynch, + agPhyErrCountersPage->phyResetProblem, + agPhyErrCountersPage->inboundCRCError )); + } + else + { + TI_DBG1(("ossaHwCB: OSSA_HW_EVENT_PHY_ERR_INBOUND_CRC: Error!!! eventParm2 is NULL\n")); + } + + /* saHwEventAck() */ + eventSource.agPortContext = agPortContext; + eventSource.event = OSSA_HW_EVENT_PHY_ERR_INBOUND_CRC; + /* phy ID */ + eventSource.param = PhyID; + HwAckSatus = saHwEventAck( + agRoot, + agNULL, /* agContext */ + 0, + &eventSource, /* agsaEventSource_t */ + 0, + 0 + ); + if ( HwAckSatus != AGSA_RC_SUCCESS) + { + TI_DBG1(("ossaHwCB: failing in saHwEventAck; status %d\n", HwAckSatus)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'o', "Y2"); + return; + } + break; + } +#ifdef REMOVED + case OSSA_HW_EVENT_PORT_INVALID: + { + TI_DBG1(("ossaHwCB: PORT_INVALID\n")); + + if ( agPortContext == agNULL) + { + TI_DBG1(("ossaHwCB: agPortContext is NULL, wrong.\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'p', "Y2"); + return; + } + if ( agPortContext->osData != agNULL) + { + TI_DBG1(("ossaHwCB: NOT NULL osDATA\n")); + /* + put the old portcontext back to free list + */ + onePortContext = (tdsaPortContext_t *)agPortContext->osData; + TI_DBG1(("ossaHwCB: pid %d\n", onePortContext->id)); + +#ifdef INITIATOR_DRIVER + /* notifying link down (all links belonging to a port are down) */ + ostiPortEvent ( + tiRoot, + tiPortStopped, + tiSuccess, + (void *)onePortContext->tiPortalContext + + ); +#endif /* INITIATOR_DRIVER */ +#ifdef TARGET_DRIVER + ostiPortEvent( + tiRoot, + tiPortLinkDown, + tiSuccess, + (void *)onePortContext->tiPortalContext + ); + +#endif /*TARGET_DRIVER */ + + /* find the device belonging to the port and remove it from the device list */ + //tdssRemoveSASSATAFromSharedcontext(agRoot, tdsaDeviceData, onePortContext); + + +#ifdef INITIATOR_DRIVER + /* reset the fields of portcontext */ + onePortContext->DiscoveryState = ITD_DSTATE_NOT_STARTED; + tdssReportRemovals(agRoot, + onePortContext, + agFALSE + ); + + onePortContext->discoveryOptions = AG_SA_DISCOVERY_OPTION_FULL_START; + onePortContext->DiscoveryRdyGiven = agFALSE; + onePortContext->SeenLinkUp = agFALSE; + +#endif /* INITIATOR_DRIVER */ + + + + /* for hotplug */ + + /* find a PhyID and reset for portContext in tdssSASShared */ + for(i=0;iPhyIDList[i] == agTRUE) + { + tdsaAllShared->Ports[i].portContext = agNULL; + } + } + + /* reset PhyIDList in portcontext */ + for(i=0;iPhyIDList[i] = agFALSE; + } + +// onePortContext->tiPortalContext = agNULL; +// onePortContext->agRoot = agNULL; + onePortContext->agPortContext = agNULL; + onePortContext->valid = agFALSE; + + TI_DBG4(("ossaHwCB: pid %d count %d\n", onePortContext->id, onePortContext->Count)); + + /* resets the number of devices in onePortContext */ + onePortContext->Count = 0; + onePortContext->discovery.pendingSMP = 0; + onePortContext->discovery.SeenBC = agFALSE; + + + /* + put all devices belonging to the onePortContext + back to the free link + */ + + tdsaSingleThreadedEnter(tiRoot, TD_PORT_LOCK); + TDLIST_DEQUEUE_THIS(&(onePortContext->MainLink)); + TDLIST_ENQUEUE_AT_TAIL(&(onePortContext->FreeLink), &(tdsaPortContext->FreeLink)); + tdsaSingleThreadedLeave(tiRoot, TD_PORT_LOCK); + } + else + { + TI_DBG1(("ossaHwCB: NULL osDATA: wrong\n")); + } + TI_DBG6(("ossaHwCB: PORT_INVALID end\n")); + break; + } +#endif /* REMOVED */ + + case OSSA_HW_EVENT_BROADCAST_CHANGE: + { + PhyID = TD_GET_PHY_ID(eventParm1); + PortState = TD_GET_PORT_STATE(eventParm1); + TI_DBG1(("ossaHwCB: BROADCAST_CHANGE from PhyID %d\n", PhyID)); + + if (PortState == OSSA_PORT_INVALID) + { + TI_DBG1(("ossaHwCB: Wrong port state with BROADCAST_CHANGE\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'q', "Y2"); + return; + } + /* saHwEventAck() */ + eventSource.agPortContext = agPortContext; + eventSource.event = OSSA_HW_EVENT_BROADCAST_CHANGE; + /* phy ID */ + eventSource.param = PhyID; + HwAckSatus = saHwEventAck( + agRoot, + agNULL, /* agContext */ + 0, + &eventSource, /* agsaEventSource_t */ + 0, + 0 + ); + TI_DBG4(("ossaHwCB: calling saHwEventAck\n")); + + if ( HwAckSatus != AGSA_RC_SUCCESS) + { + TI_DBG1(("ossaHwCB: failing in saHwEventAck; status %d\n", HwAckSatus)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'r', "Y2"); + return; + } + if (tIsSPC12SATA(agRoot)) + { + TI_DBG1(("ossaHwCB: BROADCAST_CHANGE received for SATA Controller\n")); + break; + } + /* + * incremental discovery is to be tested and debugged further + */ + + /* just for testing discovery abort */ +#ifdef FDS_DM_NO + if (agPortContext == agNULL) + { + /* this case happens when broadcase is received first before the link up */ + TI_DBG2(("ossaHwCB: agPortContext is NULL. Do nothing.\n")); + } + else if ( agPortContext->osData != agNULL) + { + dmRoot = &(tdsaAllShared->dmRoot); + onePortContext = (tdsaPortContext_t *)agPortContext->osData; + dmPortContext = &(onePortContext->dmPortContext); + + dmQueryDiscovery(dmRoot, dmPortContext); +// dmDiscover(dmRoot, dmPortContext, DM_DISCOVERY_OPTION_ABORT); + +#if 1 + if (onePortContext->DMDiscoveryState == dmDiscInProgress) + { + dmDiscover(dmRoot, dmPortContext, DM_DISCOVERY_OPTION_ABORT); + } +#endif /* 1 */ + + TI_DBG2(("ossaHwCB: portcontext pid %d\n", onePortContext->id)); + if (onePortContext->DMDiscoveryState == dmDiscCompleted || + onePortContext->DMDiscoveryState == dmDiscAborted || + onePortContext->DMDiscoveryState == dmDiscAbortInvalid ) + { + TI_DBG1(("ossaHwCB: BROADCAST_CHANGE; calling dmNotifyBC and does incremental discovery\n")); + dmNotifyBC(dmRoot, dmPortContext, OSSA_HW_EVENT_BROADCAST_CHANGE); + dmDiscover(dmRoot, dmPortContext, DM_DISCOVERY_OPTION_INCREMENTAL_START); + + } + else + { + TI_DBG2(("ossaHwCB: pid %d BROADCAST_CHANGE; updating SeenBC. calling dmNotifyBC\n", onePortContext->id)); + dmNotifyBC(dmRoot, dmPortContext, OSSA_HW_EVENT_BROADCAST_CHANGE); + } + } + else + { + TI_DBG1(("ossaHwCB: BROADCAST_CHANGE NULL osDATA wrong !!! \n")); + } + + +#endif /* FDS_DM_NO */ + +#ifdef FDS_DM + if (agPortContext == agNULL) + { + /* this case happens when broadcase is received first before the link up */ + TI_DBG2(("ossaHwCB: agPortContext is NULL. Do nothing.\n")); + } + else if ( agPortContext->osData != agNULL) + { + dmRoot = &(tdsaAllShared->dmRoot); + onePortContext = (tdsaPortContext_t *)agPortContext->osData; + dmPortContext = &(onePortContext->dmPortContext); + + dmQueryDiscovery(dmRoot, dmPortContext); + + TI_DBG2(("ossaHwCB: portcontext pid %d\n", onePortContext->id)); + if (onePortContext->DMDiscoveryState == dmDiscCompleted || + onePortContext->DMDiscoveryState == dmDiscAborted || + onePortContext->DMDiscoveryState == dmDiscAbortInvalid ) + { + TI_DBG1(("ossaHwCB: BROADCAST_CHANGE; calling dmNotifyBC and does incremental discovery, pid %d\n", onePortContext->id)); + onePortContext->DiscoveryState = ITD_DSTATE_STARTED; + dmNotifyBC(dmRoot, dmPortContext, OSSA_HW_EVENT_BROADCAST_CHANGE); + dmDiscover(dmRoot, dmPortContext, DM_DISCOVERY_OPTION_INCREMENTAL_START); + + } + else if (onePortContext->DMDiscoveryState == dmDiscFailed ) + { + TI_DBG1(("ossaHwCB: dmDiscFailed; pid %d BROADCAST_CHANGE; updating SeenBC. calling dmNotifyBC\n", onePortContext->id)); + onePortContext->DiscFailNSeenBC = agTRUE; + dmNotifyBC(dmRoot, dmPortContext, OSSA_HW_EVENT_BROADCAST_CHANGE); + } + else + { + TI_DBG2(("ossaHwCB: pid %d BROADCAST_CHANGE; updating SeenBC. calling dmNotifyBC\n", onePortContext->id)); + dmNotifyBC(dmRoot, dmPortContext, OSSA_HW_EVENT_BROADCAST_CHANGE); + } + } + else + { + TI_DBG1(("ossaHwCB: BROADCAST_CHANGE NULL osDATA wrong !!! \n")); + } +#endif /* FDS_DM */ + +#ifdef FDS_DM_WORKED + if (agPortContext == agNULL) + { + /* this case happens when broadcase is received first before the link up */ + TI_DBG2(("ossaHwCB: agPortContext is NULL. Do nothing.\n")); + } + else if ( agPortContext->osData != agNULL) + { + onePortContext = (tdsaPortContext_t *)agPortContext->osData; + TI_DBG2(("ossaHwCB: calling dmNotifyBC\n")); + dmRoot = &(tdsaAllShared->dmRoot); + dmPortContext = &(onePortContext->dmPortContext); + dmNotifyBC(dmRoot, dmPortContext, OSSA_HW_EVENT_BROADCAST_CHANGE); + } +#endif /* FDS_DM_WORKED */ + +#ifndef FDS_DM +#ifdef INITIATOR_DRIVER + if (agPortContext == agNULL) + { + /* this case happens when broadcase is received first before the link up */ + TI_DBG2(("ossaHwCB: agPortContext is NULL. Do nothing.\n")); + } + else if ( agPortContext->osData != agNULL) + { + onePortContext = (tdsaPortContext_t *)agPortContext->osData; + TI_DBG2(("ossaHwCB: portcontext pid %d\n", onePortContext->id)); + if (onePortContext->DiscoveryState == ITD_DSTATE_COMPLETED) + { + TI_DBG1(("ossaHwCB: BROADCAST_CHANGE; does incremental discovery\n")); + onePortContext->DiscoveryState = ITD_DSTATE_NOT_STARTED; + onePortContext->discoveryOptions = AG_SA_DISCOVERY_OPTION_INCREMENTAL_START; + /* processed broadcast change */ + onePortContext->discovery.SeenBC = agFALSE; +#ifdef TD_DISCOVER + if (tdsaAllShared->ResetInDiscovery != 0 && + onePortContext->discovery.ResetTriggerred == agTRUE) + { + TI_DBG2(("ossaHwCB: tdsaBCTimer\n")); + tdsaBCTimer(tiRoot, onePortContext); + } + else + { + tdsaDiscover( + tiRoot, + onePortContext, + TDSA_DISCOVERY_TYPE_SAS, + TDSA_DISCOVERY_OPTION_INCREMENTAL_START + ); + } +#else + saDiscover(agRoot, + agPortContext, + AG_SA_DISCOVERY_TYPE_SAS, + onePortContext->discoveryOptions); +#endif + } + else + { + TI_DBG2(("ossaHwCB: pid %d BROADCAST_CHANGE; updating SeenBC. Do nothing.\n", onePortContext->id)); + onePortContext->discovery.SeenBC = agTRUE; + } + } + else + { + TI_DBG1(("ossaHwCB: BROADCAST_CHANGE NULL osDATA wrong !!! \n")); + } +#endif +#endif /* ifndef FDS_DM */ + + break; + } + + case OSSA_HW_EVENT_PORT_RECOVERY_TIMER_TMO: + { + PhyID = TD_GET_PHY_ID(eventParm1); + PortState = TD_GET_PORT_STATE(eventParm1); + + /* + 1. tear town the portcontext just like link down last phy down + 2. ack + port state must be invalid + */ + + TI_DBG2(("ossaHwCB: OSSA_HW_EVENT_PORT_RECOVERY_TIMER_TMO\n")); + + if (PortState == OSSA_PORT_VALID) + { + TI_DBG1(("ossaHwCB: Wrong port state\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 's', "Y2"); + return; + } + + TD_ASSERT(agPortContext, "agPortContext"); + if ( agPortContext->osData == agNULL) + { /* if */ + /* PortContext must exit at this point */ + TI_DBG1(("ossaHwCB: NULL portalcontext. Error. Can't be NULL\n")); + } + else + { + onePortContext = (tdsaPortContext_t *)agPortContext->osData; + onePortContext->valid = agFALSE; + + TI_DBG1(("ossaHwCB: tiPortStopped pid %d\n", onePortContext->id)); +#ifdef INITIATOR_DRIVER + /* notifying link down (all links belonging to a port are down) */ + ostiPortEvent( + tiRoot, + tiPortStopped, + tiSuccess, + (void *)onePortContext->tiPortalContext + ); +#endif + +#ifdef TARGET_DRIVER + ostiPortEvent( + tiRoot, + tiPortLinkDown, + tiSuccess, + (void *)onePortContext->tiPortalContext + ); + +#endif + +#ifdef INITIATOR_DRIVER + tdssReportRemovals(agRoot, + onePortContext, + agFALSE + ); +#endif +#ifdef TARGET_DRIVER + ttdssReportRemovals(agRoot, + onePortContext, + agFALSE + ); + +#endif + /* find a PhyID and reset for portContext in tdssSASShared */ + for(i=0;iPhyIDList[i] == agTRUE) + { + tdsaAllShared->Ports[i].portContext = agNULL; + } + } + /* portcontext is removed from MainLink to FreeLink in tdssReportRemovals or + ossaDeregisterDeviceHandleCB + */ + } + + break; + } + + case OSSA_HW_EVENT_PORT_RESET_TIMER_TMO: + { + /* + clean up + */ + PhyID = TD_GET_PHY_ID(eventParm1); + PortState = TD_GET_PORT_STATE(eventParm1); + + TI_DBG2(("ossaHwCB: OSSA_HW_EVENT_PORT_RESET_TIMER_TMO\n")); + + if (PortState == OSSA_PORT_VALID) + { + TI_DBG1(("ossaHwCB: Wrong port state\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 't', "Y2"); + return; + } + + if (agPortContext == agNULL) + { + TI_DBG1(("ossaHwCB: agPortContext is NULL, error\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'u', "Y2"); + return; + } + + if ( agPortContext->osData == agNULL) + { /* if */ + /* PortContext must exit at this point */ + TI_DBG1(("ossaHwCB: NULL portalcontext. Error. Can't be NULL\n")); + } + else + { + onePortContext = (tdsaPortContext_t *)agPortContext->osData; + onePortContext->valid = agFALSE; + + TI_DBG1(("ossaHwCB: pid %d tiPortStopped\n", onePortContext->id)); + +#ifdef INITIATOR_DRIVER + /* notifying link down (all links belonging to a port are down) */ + ostiPortEvent( + tiRoot, + tiPortStopped, + tiSuccess, + (void *)onePortContext->tiPortalContext + ); +#endif + +#ifdef TARGET_DRIVER + ostiPortEvent( + tiRoot, + tiPortLinkDown, + tiSuccess, + (void *)onePortContext->tiPortalContext + ); + +#endif + +#ifdef INITIATOR_DRIVER + tdssReportRemovals(agRoot, + onePortContext, + agFALSE + ); +#endif +#ifdef TARGET_DRIVER + ttdssReportRemovals(agRoot, + onePortContext, + agFALSE + ); + +#endif + /* find a PhyID and reset for portContext in tdssSASShared */ + for(i=0;iPhyIDList[i] == agTRUE) + { + tdsaAllShared->Ports[i].portContext = agNULL; + } + } + /* portcontext is removed from MainLink to FreeLink in tdssReportRemovals or + ossaDeregisterDeviceHandleCB + */ + } + + break; + } + + case OSSA_HW_EVENT_PORT_RESET_COMPLETE: + { +#ifdef INITIATOR_DRIVER + tiIORequest_t *currentTaskTag = agNULL; +#endif + +#ifdef REMOVED + smRoot_t *smRoot = &(tdsaAllShared->smRoot); +#endif + + PhyID = TD_GET_PHY_ID(eventParm1); + PortState = TD_GET_PORT_STATE(eventParm1); + IDframe = (agsaSASIdentify_t *)eventParm3; + + /* completes for Lun Reset and Target reset for directly attached SATA */ + /* completes for Target reset for directly attached SAS */ + + TI_DBG1(("ossaHwCB: OSSA_HW_EVENT_PORT_RESET_COMPLETE, phyID %d\n", PhyID)); + + /* error check */ + if (PortState == OSSA_PORT_INVALID) + { + TI_DBG1(("ossaHwCB: Wrong port state\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'v', "Y2"); + return; + } + + if (agPortContext == agNULL) + { + TI_DBG1(("ossaHwCB: agPortContext null, wrong\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'w', "Y2"); + return; + } + if ( agPortContext->osData == agNULL) + { + TI_DBG1(("ossaHwCB: agPortContext->osData null, wrong\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'x', "Y2"); + return; + } + + /* find a corresponding portcontext */ + onePortContext = (tdsaPortContext_t *)agPortContext->osData; + + if (onePortContext == agNULL) + { + TI_DBG1(("ossaHwCB: oneportContext is NULL; wrong??????\n")); + } + else + { + TI_DBG1(("ossaHwCB: oneportContext %p pid %d\n", onePortContext, onePortContext->id)); + onePortContext->valid = agTRUE; +#ifdef INITIATOR_DRIVER +#ifdef REMOVED + if (tdsaAllShared->ResetInDiscovery != 0) + { + DeviceListList = tdsaAllShared->MainDeviceList.flink; + while (DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData->tdPortContext != onePortContext) + { + DeviceListList = DeviceListList->flink; + } + else + { + found = agTRUE; + break; + } + } /* while */ + if (found == agTRUE) + { + /* applied to only SATA devices */ + if (DEVICE_IS_SATA_DEVICE(oneDeviceData) || DEVICE_IS_STP_TARGET(oneDeviceData)) + { + #ifdef FDS_SM + tdIDStart(tiRoot, agRoot, smRoot, oneDeviceData, onePortContext); + #else + tdssRetrySATAID(tiRoot, oneDeviceData); + #endif + } + } + else + { + TI_DBG1(("ossaHwCB: no onedevicedata found!\n")); + } + } +#endif + /* completed TM */ + DeviceListList = tdsaAllShared->MainDeviceList.flink; + while (DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + if ( oneDeviceData == agNULL) + { + TI_DBG1(("ossaHwCB: oneDeviceData is NULL!!!\n")); + return; + } + + if ( (oneDeviceData->tdPortContext == onePortContext) && + (oneDeviceData->directlyAttached == agTRUE) && + (oneDeviceData->phyID == PhyID) ) + { + TI_DBG1(("ossaHwCB: found the onePortContext and oneDeviceData!!\n")); + + currentTaskTag = (tiIORequest_t *)oneDeviceData->agDeviceResetContext.osData; + if (currentTaskTag != agNULL ) + { + /* applied to only SATA devices */ + if (DEVICE_IS_SATA_DEVICE(oneDeviceData)) + { + tdIORequestBody_t *SMTMtdIORequestBody = agNULL; + SMTMtdIORequestBody = (tdIORequestBody_t *)currentTaskTag->tdData; + if (SMTMtdIORequestBody != agNULL) + { + /* free the SMTMtdIORequestBody memory allocated in tiINITaskManagement function */ + ostiFreeMemory( + tiRoot, + SMTMtdIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + else + { + TI_DBG1(("ossaHwCB: SATA device but SMTMtdIORequestBody is NULL!!!\n")); + } + } + /* set device state to DS_OPERATIONAL */ + saSetDeviceState(agRoot, + agNULL, + tdsaRotateQnumber(tiRoot, oneDeviceData), + oneDeviceData->agDevHandle, + SA_DS_OPERATIONAL + ); + /* notify OS layer to complete the TMF IO */ + ostiInitiatorEvent(tiRoot, + agNULL, + agNULL, + tiIntrEventTypeTaskManagement, + tiTMOK, + currentTaskTag + ); + + } + else + { + TI_DBG1(("ossaHwCB: currentTaskTag is NULL!!!\n")); + } + + break; + } + else + { + DeviceListList = DeviceListList->flink; + } + } +#endif + } + break; + } + case OSSA_HW_EVENT_BROADCAST_ASYNCH_EVENT: + { + PhyID = TD_GET_PHY_ID(eventParm1); + PortState = TD_GET_PORT_STATE(eventParm1); + + TI_DBG2(("ossaHwCB: OSSA_HW_EVENT_BROADCAST_ASYNCH_EVENT\n")); + if (tIsSPC12SATA(agRoot)) + { + TI_DBG1(("ossaHwCB: BROADCAST_ASYNCH_EVENT received for SATA Controller\n")); + break; + } + if (agPortContext == agNULL) + { + TI_DBG1(("ossaHwCB: Error!!! agPortContext is NULL %d\n", PhyID)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'y', "Y2"); + return; + } + onePortContext = (tdsaPortContext_t *)agPortContext->osData; + if (onePortContext == agNULL) + { + TI_DBG1(("ossaHwCB: Error!!! onePortContext is NULL %d\n", PhyID)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'z', "Y2"); + return; + } + + if (onePortContext->tiPortalContext != agNULL) + { +#if 0 + ostiInitiatorEvent( + tiRoot, + onePortContext->tiPortalContext, + agNULL, + tiIntrEventTypeDeviceChange, + OSSA_HW_EVENT_BROADCAST_ASYNCH_EVENT, + agNULL + ); +#endif + } + else + { + TI_DBG1(("ossaHwCB: Error!!! onePortContext->tiPortalContext is NULL\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'A', "Y2"); + return; + } + + break; + } + + case OSSA_HW_EVENT_PORT_RECOVER: + { + + PhyID = TD_GET_PHY_ID(eventParm1); + if (agPortContext == agNULL) + { + TI_DBG1(("ossaHwCB: Error!!! agPortContext is NULL %d\n", PhyID)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'B', "Y2"); + return; + } + + LinkRate = TD_GET_LINK_RATE(eventParm1); + PortState = TD_GET_PORT_STATE(eventParm1); + agDevHandle = agNULL; + IDframe = (agsaSASIdentify_t *)eventParm3; + + /* + 1. this is like link up + 2. handle the phyID + 3. no trigger discovery (broadcast change will do this later) + port state must be valid + */ + + TI_DBG2(("ossaHwCB: OSSA_HW_EVENT_PORT_RECOVER, phyID %d\n", PhyID)); + + if (PortState == OSSA_PORT_INVALID) + { + TI_DBG1(("ossaHwCB: Wrong port state\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'C', "Y2"); + return; + } + if ( agPortContext->osData == agNULL) + { /* if */ + /* PortContext must exit at this point */ + TI_DBG1(("ossaHwCB: NULL portalcontext. Error. Can't be NULL\n")); + } + else + { + onePortContext = (tdsaPortContext_t *)agPortContext->osData; + TI_DBG2(("ossaHwCB: pid %d\n", onePortContext->id)); + onePortContext->PhyIDList[PhyID] = agTRUE; + onePortContext->valid = agTRUE; + tdsaAllShared->Ports[PhyID].portContext = onePortContext; + onePortContext->tiPortalContext = tdsaAllShared->Ports[PhyID].tiPortalContext; + onePortContext->PortRecoverPhyID = PhyID; + if (LinkRate == 0x01) + { + onePortContext->LinkRate = SAS_CONNECTION_RATE_1_5G; + } + else if (LinkRate == 0x02) + { + onePortContext->LinkRate = SAS_CONNECTION_RATE_3_0G; + } + else if (LinkRate == 0x04) + { + onePortContext->LinkRate = SAS_CONNECTION_RATE_6_0G; + } + else /* (LinkRate == 0x08) */ + { + onePortContext->LinkRate = SAS_CONNECTION_RATE_12_0G; + } + + if (SA_IDFRM_GET_DEVICETTYPE(&onePortContext->sasIDframe) == SAS_END_DEVICE && + SA_IDFRM_IS_SSP_TARGET(&onePortContext->sasIDframe) ) + { + TI_DBG2(("ossaHwCB: OSSA_HW_EVENT_PORT_RECOVER, sending spinup on phyID %d\n", PhyID)); + for (i=0;iTransient == agTRUE && onePortContext->RegisteredDevNums == 0) + { + TI_DBG2(("ossaHwCB: OSSA_HW_EVENT_PORT_RECOVER transient period")); + if (SA_IDFRM_GET_DEVICETTYPE(IDframe) != SAS_NO_DEVICE) + { +#ifdef INITIATOR_DRIVER + agSASSubID.sasAddressHi = SA_IDFRM_GET_SAS_ADDRESSHI(IDframe); + agSASSubID.sasAddressLo = SA_IDFRM_GET_SAS_ADDRESSLO(IDframe); + agSASSubID.initiator_ssp_stp_smp = IDframe->initiator_ssp_stp_smp; + agSASSubID.target_ssp_stp_smp = IDframe->target_ssp_stp_smp; + tdssAddSASToSharedcontext( + onePortContext, + agRoot, + agDevHandle, /* agNULL */ + &agSASSubID, + agTRUE, + (bit8)PhyID, + TD_OPERATION_INITIATOR + ); +#endif + } + onePortContext->Transient = agFALSE; + } + + + + + } + break; + } + + case OSSA_HW_EVENT_BROADCAST_SES: + { + PhyID = TD_GET_PHY_ID(eventParm1); + PortState = TD_GET_PORT_STATE(eventParm1); + + TI_DBG2(("ossaHwCB: BROADCAST_SES from PhyID %d; to be tested\n", PhyID)); + if (tIsSPC12SATA(agRoot)) + { + TI_DBG1(("ossaHwCB: BROADCAST_SES received for SATA Controller\n")); + break; + } + if (PortState == OSSA_PORT_INVALID) + { + TI_DBG1(("ossaHwCB: Wrong port state with BROADCAST_SES\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'D', "Y2"); + return; + } + + /* + let os layer read payload + */ + break; + } + case OSSA_HW_EVENT_BROADCAST_EXP: + { + PhyID = TD_GET_PHY_ID(eventParm1); + PortState = TD_GET_PORT_STATE(eventParm1); + + TI_DBG2(("ossaHwCB: BROADCAST_EXP from PhyID %d; to be tested\n", PhyID)); + if (tIsSPC12SATA(agRoot)) + { + TI_DBG1(("ossaHwCB: BROADCAST_EXP received for SATA Controller\n")); + break; + } + + if (PortState == OSSA_PORT_INVALID) + { + TI_DBG1(("ossaHwCB: Wrong port state with BROADCAST_EXP\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'E', "Y2"); + return; + } + /* to-do: + let os layer read payload + */ + break; + } + + case OSSA_HW_EVENT_HARD_RESET_RECEIVED: + { + PhyID = TD_GET_PHY_ID(eventParm1); + PortState = TD_GET_PORT_STATE(eventParm1); + + TI_DBG2(("ossaHwCB: HARD_RESET_RECEIVED from PhyID %d\n", PhyID)); + + if (PortState == OSSA_PORT_VALID && tiIS_SPC(agRoot)) + { + TI_DBG1(("ossaHwCB: calling saPortControl and OSSA_PORT_VALID\n")); + saPortControl(agRoot, agNULL, 0, agPortContext, AGSA_PORT_HARD_RESET, 0,0); + } + else if (PortState == OSSA_PORT_3RDPARTY_RESET && (tIsSPCV12or6G(agRoot)) ) + { + TI_DBG1(("ossaHwCB: calling saPortControl and OSSA_PORT_3RDPARTY_RESET\n")); + saPortControl(agRoot, agNULL, 0, agPortContext, AGSA_PORT_HARD_RESET, 0,0); + } + else /* PortState == OSSA_PORT_INVALID */ + { + TI_DBG1(("ossaHwCB: Error. Port state is invalid\n")); +#ifdef REMOVED + TI_DBG1(("ossaHwCB: calling saLocalPhyControl on phyID %d\n", PhyID)); + saLocalPhyControl(agRoot, agNULL, 0, PhyID, AGSA_PHY_LINK_RESET, agNULL); +#endif + } + + break; + } + + case OSSA_HW_EVENT_MALFUNCTION: + { +#ifdef TD_DEBUG_ENABLE + agsaFatalErrorInfo_t *FatalError = (agsaFatalErrorInfo_t *)eventParm2; +#endif + TI_DBG1(("ossaHwCB: OSSA_HW_EVENT_MALFUNCTION \n")); + TI_DBG1(("ossaHwCB: errorInfo0 %8X errorInfo1 %8X\n", FatalError->errorInfo0, FatalError->errorInfo1)); + TI_DBG1(("ossaHwCB: errorInfo2 %8X errorInfo3 %8X\n", FatalError->errorInfo2, FatalError->errorInfo3)); + TI_DBG1(("ossaHwCB: regDumpBusBaseNum0 %8X regDumpOffset0 %8X regDumpLen0 %8X\n", FatalError->regDumpBusBaseNum0, FatalError->regDumpOffset0, FatalError->regDumpLen0)); + TI_DBG1(("ossaHwCB: regDumpBusBaseNum1 %8X regDumpOffset1 %8X regDumpLen1 %8X\n", FatalError->regDumpBusBaseNum1, FatalError->regDumpOffset1, FatalError->regDumpLen1)); + + + if (eventParm1 == agTRUE) + { + TI_DBG1(("ossaHwCB: fatal error\n")); + /* port panic */ + ostiPortEvent ( + tiRoot, + tiPortPanic, + 0, + agNULL + ); + } + else + { + TI_DBG1(("ossaHwCB: non-fatal error \n")); + } + break; + } + + case OSSA_HW_EVENT_ID_FRAME_TIMEOUT: + { + PhyID = TD_GET_PHY_ID(eventParm1); + PortState = TD_GET_PORT_STATE(eventParm1); + + TI_DBG2(("ossaHwCB: OSSA_HW_EVENT_ID_FRAME_TIMEOUT from PhyID %d\n", PhyID)); + + if (PortState == OSSA_PORT_INVALID) + { + TI_DBG1(("ossaHwCB: Wrong port state with OSSA_HW_EVENT_ID_FRAME_TIMEOUT\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'F', "Y2"); + return; + } + break; + } + + case OSSA_HW_EVENT_PHY_ERR_INVALID_DWORD: + { + PhyID = TD_GET_PHY_ID(eventParm1); + PortState = TD_GET_PORT_STATE(eventParm1); + agPhyErrCountersPage = (agsaPhyErrCountersPage_t *)eventParm2; + TI_DBG2(("ossaHwCB: OSSA_HW_EVENT_PHY_ERR_INVALID_DWORD\n")); + + if (PortState == OSSA_PORT_INVALID) + { + TI_DBG1(("ossaHwCB: Wrong port state with OSSA_HW_EVENT_PHY_ERR_INVALID_DWORD\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'G', "Y2"); + return; + } + + if (agPhyErrCountersPage != agNULL) + { + TI_DBG1(("ossaHwCB: OSSA_HW_EVENT_PHY_ERR_INVALID_DWORD from PhyID %d\n", PhyID)); + TI_DBG1(("ossaHwCB: invalidDword %d\n", agPhyErrCountersPage->invalidDword)); + } + else + { + TI_DBG1(("ossaHwCB: OSSA_HW_EVENT_PHY_ERR_INVALID_DWORD: Error!!! eventParm2 is NULL\n")); + } + + /* saHwEventAck() */ + eventSource.agPortContext = agPortContext; + eventSource.event = OSSA_HW_EVENT_PHY_ERR_INVALID_DWORD; + /* phy ID */ + eventSource.param = PhyID; + HwAckSatus = saHwEventAck( + agRoot, + agNULL, /* agContext */ + 0, + &eventSource, /* agsaEventSource_t */ + 0, + 0 + ); + if ( HwAckSatus != AGSA_RC_SUCCESS) + { + TI_DBG1(("ossaHwCB: failing in saHwEventAck; status %d\n", HwAckSatus)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'H', "Y2"); + return; + } + + break; + } + + case OSSA_HW_EVENT_PHY_ERR_DISPARITY_ERROR: + { + PhyID = TD_GET_PHY_ID(eventParm1); + PortState = TD_GET_PORT_STATE(eventParm1); + agPhyErrCountersPage = (agsaPhyErrCountersPage_t *)eventParm2; + TI_DBG1(("ossaHwCB: OSSA_HW_EVENT_PHY_ERR_DISPARITY_ERROR\n")); + + if (PortState == OSSA_PORT_INVALID) + { + TI_DBG1(("ossaHwCB: Wrong port state with OSSA_HW_EVENT_PHY_ERR_DISPARITY_ERROR\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'I', "Y2"); + return; + } + + if (agPhyErrCountersPage != agNULL) + { + TI_DBG1(("ossaHwCB: OSSA_HW_EVENT_PHY_ERR_DISPARITY_ERROR from PhyID %d\n", PhyID)); + TI_DBG1(("ossaHwCB: runningDisparityError %d\n", agPhyErrCountersPage->runningDisparityError)); + } + else + { + TI_DBG1(("ossaHwCB: OSSA_HW_EVENT_PHY_ERR_DISPARITY_ERROR: Error!!! eventParm2 is NULL\n")); + } + + /* saHwEventAck() */ + eventSource.agPortContext = agPortContext; + eventSource.event = OSSA_HW_EVENT_PHY_ERR_DISPARITY_ERROR; + /* phy ID */ + eventSource.param = PhyID; + HwAckSatus = saHwEventAck( + agRoot, + agNULL, /* agContext */ + 0, + &eventSource, /* agsaEventSource_t */ + 0, + 0 + ); + if ( HwAckSatus != AGSA_RC_SUCCESS) + { + TI_DBG1(("ossaHwCB: failing in saHwEventAck; status %d\n", HwAckSatus)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'J', "Y2"); + return; + } + + break; + } + + case OSSA_HW_EVENT_PHY_ERR_CODE_VIOLATION: + { + PhyID = TD_GET_PHY_ID(eventParm1); + PortState = TD_GET_PORT_STATE(eventParm1); + agPhyErrCountersPage = (agsaPhyErrCountersPage_t *)eventParm2; + TI_DBG2(("ossaHwCB: OSSA_HW_EVENT_PHY_ERR_CODE_VIOLATION\n")); + + if (PortState == OSSA_PORT_INVALID) + { + TI_DBG1(("ossaHwCB: Wrong port state with OSSA_HW_EVENT_PHY_ERR_CODE_VIOLATION\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'K', "Y2"); + return; + } + + if (agPhyErrCountersPage != agNULL) + { + TI_DBG1(("ossaHwCB: OSSA_HW_EVENT_PHY_ERR_CODE_VIOLATION from PhyID %d\n", PhyID)); + TI_DBG1(("ossaHwCB: codeViolation %d\n", agPhyErrCountersPage->codeViolation)); + } + else + { + TI_DBG1(("ossaHwCB: OSSA_HW_EVENT_PHY_ERR_CODE_VIOLATION: Error!!! eventParm2 is NULL\n")); + } + + /* saHwEventAck() */ + eventSource.agPortContext = agPortContext; + eventSource.event = OSSA_HW_EVENT_PHY_ERR_CODE_VIOLATION; + /* phy ID */ + eventSource.param = PhyID; + HwAckSatus = saHwEventAck( + agRoot, + agNULL, /* agContext */ + 0, + &eventSource, /* agsaEventSource_t */ + 0, + 0 + ); + if ( HwAckSatus != AGSA_RC_SUCCESS) + { + TI_DBG1(("ossaHwCB: failing in saHwEventAck; status %d\n", HwAckSatus)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'L', "Y2"); + return; + } + + break; + } + +#ifdef REMOVED + case OSSA_HW_EVENT_LINK_ERR_CODE_VIOLATION1: + { + PhyID = eventParm1 & 0xFF; + agPhyErrCountersPage = (agsaPhyErrCountersPage_t *)eventParm2; + + if (agPhyErrCountersPage != agNULL) + { + TI_DBG1(("ossaHwCB: OSSA_HW_EVENT_LINK_ERR_CODE_VIOLATION1 from PhyID %d\n", PhyID)); + TI_DBG1(("ossaHwCB: invalidDword %d\n", agPhyErrCountersPage->invalidDword)); + TI_DBG1(("ossaHwCB: runningDisparityError %d\n", agPhyErrCountersPage->runningDisparityError)); + TI_DBG1(("ossaHwCB: codeViolation %d\n", agPhyErrCountersPage->codeViolation)); + TI_DBG1(("ossaHwCB: lostOfDwordSynch %d\n", agPhyErrCountersPage->lossOfDwordSynch)); + TI_DBG1(("ossaHwCB: phyResetProblem %d\n", agPhyErrCountersPage->phyResetProblem)); + TI_DBG1(("ossaHwCB: inboundCRCError %d\n", agPhyErrCountersPage->inboundCRCError)); + } + else + { + TI_DBG1(("ossaHwCB: OSSA_HW_EVENT_LINK_ERR_CODE_VIOLATION1: Error!!! eventParm2 is NULL\n")); + } + break; + } +#endif /* REMOVED */ + + case OSSA_HW_EVENT_PHY_ERR_LOSS_OF_DWORD_SYNCH: + { + PhyID = TD_GET_PHY_ID(eventParm1); + PortState = TD_GET_PORT_STATE(eventParm1); + agPhyErrCountersPage = (agsaPhyErrCountersPage_t *)eventParm2; + TI_DBG2(("ossaHwCB: OSSA_HW_EVENT_PHY_ERR_LOSS_OF_DWORD_SYNCH\n")); + + if (PortState == OSSA_PORT_INVALID) + { + TI_DBG1(("ossaHwCB: Wrong port state with OSSA_HW_EVENT_PHY_ERR_LOSS_OF_DWORD_SYNCH\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'M', "Y2"); + return; + } + + if (agPhyErrCountersPage != agNULL) + { + TI_DBG1(("ossaHwCB: OSSA_HW_EVENT_PHY_ERR_LOSS_OF_DWORD_SYNCH from PhyID %d\n", PhyID)); + TI_DBG1(("ossaHwCB: lostOfDwordSynch %d\n", agPhyErrCountersPage->lossOfDwordSynch)); + } + else + { + TI_DBG1(("ossaHwCB: OSSA_HW_EVENT_PHY_ERR_LOSS_OF_DWORD_SYNCH: Error!!! eventParm2 is NULL\n")); + } + + /* saHwEventAck() */ + eventSource.agPortContext = agPortContext; + eventSource.event = OSSA_HW_EVENT_PHY_ERR_LOSS_OF_DWORD_SYNCH; + /* phy ID */ + eventSource.param = PhyID; + HwAckSatus = saHwEventAck( + agRoot, + agNULL, /* agContext */ + 0, + &eventSource, /* agsaEventSource_t */ + 0, + 0 + ); + if ( HwAckSatus != AGSA_RC_SUCCESS) + { + TI_DBG1(("ossaHwCB: failing in saHwEventAck; status %d\n", HwAckSatus)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'N', "Y2"); + return; + } + + break; + } + + case OSSA_HW_EVENT_PHY_ERR_PHY_RESET_FAILED: + { + PhyID = TD_GET_PHY_ID(eventParm1); + PortState = TD_GET_PORT_STATE(eventParm1); + agPhyErrCountersPage = (agsaPhyErrCountersPage_t *)eventParm2; + + TI_DBG2(("ossaHwCB: OSSA_HW_EVENT_PHY_ERR_PHY_RESET_FAILED\n")); + + if (PortState == OSSA_PORT_INVALID) + { + TI_DBG1(("ossaHwCB: Wrong port state with OSSA_HW_EVENT_PHY_ERR_PHY_RESET_FAILED\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'O', "Y2"); + return; + } + + if (agPhyErrCountersPage != agNULL) + { + TI_DBG1(("ossaHwCB: OSSA_HW_EVENT_PHY_ERR_PHY_RESET_FAILED from PhyID %d\n", PhyID)); + TI_DBG1(("ossaHwCB: phyResetProblem %d\n", agPhyErrCountersPage->phyResetProblem)); + } + else + { + TI_DBG1(("ossaHwCB: OSSA_HW_EVENT_PHY_ERR_PHY_RESET_FAILED: Error!!! eventParm2 is NULL\n")); + } + + /* saHwEventAck() */ + eventSource.agPortContext = agPortContext; + eventSource.event = OSSA_HW_EVENT_PHY_ERR_PHY_RESET_FAILED; + /* phy ID */ + eventSource.param = PhyID; + HwAckSatus = saHwEventAck( + agRoot, + agNULL, /* agContext */ + 0, + &eventSource, /* agsaEventSource_t */ + 0, + 0 + ); + if ( HwAckSatus != AGSA_RC_SUCCESS) + { + TI_DBG1(("ossaHwCB: failing in saHwEventAck; status %d\n", HwAckSatus)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'P', "Y2"); + return; + } + + break; + } + +// #ifdef INITIATOR_DRIVER + case OSSA_HW_EVENT_ENCRYPTION: + { + pEncryptCBData = (agsaHWEventEncrypt_t *) eventParm2; + TI_DBG1(("ossaHwCB: OSSA_HW_EVENT_ENCRYPTION: encryptOperation 0x%x\n",pEncryptCBData->encryptOperation)); + TI_DBG1(("ossaHwCB: event 0x%x eventParm1 0x%x eventParm2 %p eventParm3 %p\n",event,eventParm1,eventParm2,eventParm3)); + + /* + * All events and status need to be translated from + * SAS specific values to TISA specific values. This + * is effectively a NOP, but the OS layer won't want to + * look for SAS values. + */ + if (pEncryptCBData->encryptOperation == OSSA_HW_ENCRYPT_KEK_UPDATE_AND_STORE) + { + TI_DBG1(("ossaHwCB: OSSA_HW_ENCRYPT_KEK_UPDATE_AND_STORE\n")); + encryptEventData.encryptEvent = tiEncryptKekStore; + } + else if (pEncryptCBData->encryptOperation == OSSA_HW_ENCRYPT_KEK_UPDATE) + { + TI_DBG1(("ossaHwCB:OSSA_HW_ENCRYPT_KEK_UPDATE \n")); + encryptEventData.encryptEvent = tiEncryptKekAdd; + } + else if (pEncryptCBData->encryptOperation == OSSA_HW_ENCRYPT_KEK_INVALIDTE) + { + TI_DBG1(("ossaHwCB:OSSA_HW_ENCRYPT_KEK_INVALIDTE \n")); + /* none */ + } + else if (pEncryptCBData->encryptOperation == OSSA_HW_ENCRYPT_DEK_UPDATE) + { + TI_DBG1(("ossaHwCB: OSSA_HW_ENCRYPT_DEK_UPDATE\n")); + encryptEventData.encryptEvent = tiEncryptDekAdd; + } + else if (pEncryptCBData->encryptOperation == OSSA_HW_ENCRYPT_DEK_INVALIDTE) + { + TI_DBG1(("ossaHwCB: OSSA_HW_ENCRYPT_DEK_INVALIDTE\n")); + encryptEventData.encryptEvent = tiEncryptDekInvalidate; + } + else if (pEncryptCBData->encryptOperation == OSSA_HW_ENCRYPT_OPERATOR_MANAGEMENT) + { + TI_DBG1(("ossaHwCB: OSSA_HW_ENCRYPT_OPERATOR_MANAGEMENT\n")); + encryptEventData.encryptEvent = tiEncryptOperatorManagement; + } + else if (pEncryptCBData->encryptOperation == OSSA_HW_ENCRYPT_TEST_EXECUTE) + { + TI_DBG1(("ossaHwCB: OSSA_HW_ENCRYPT_TEST_EXECUTE\n")); + encryptEventData.encryptEvent = tiEncryptSelfTest; + encryptEventData.subEvent = pEncryptCBData->eq; + } + else + { + TI_DBG1(("ossaHwCB: unknown encryptOperation 0x%x\n",pEncryptCBData->encryptOperation)); + } + + if (pEncryptCBData->status != OSSA_SUCCESS) + { + encryptStatus = tiError; + + /* prints out status and error qualifier */ + TI_DBG1(("ossaHwCB: encrypt response status 0x%x error qualifier 0x%x\n", pEncryptCBData->status, pEncryptCBData->eq)); + } + else + { + encryptStatus = tiSuccess; + } + + if (pEncryptCBData->encryptOperation == OSSA_HW_ENCRYPT_KEK_UPDATE_AND_STORE || + pEncryptCBData->encryptOperation == OSSA_HW_ENCRYPT_KEK_UPDATE ) + { + /* returning new KEK index */ + encryptEventData.pData = pEncryptCBData->handle; + } + else + { + /* returning current KEK index or DEK index */ + encryptEventData.pData = pEncryptCBData->param; + } + + ostiPortEvent(tiRoot, + tiEncryptOperation, + encryptStatus, + &encryptEventData); + break; + } + case OSSA_HW_EVENT_SECURITY_MODE: + { + securitySetModeStatus = eventParm1; + pEncryptInfo = (agsaEncryptInfo_t *) eventParm2; + + TI_DBG1(("ossaHwCB: OSSA_HW_EVENT_SECURITY_MODE\n")); + if (securitySetModeStatus == OSSA_SUCCESS) + { + securityModeStatus = tiSuccess; + } + else + { + securityModeStatus = tiError; + } + + encryptEventData.encryptEvent = tiEncryptSetMode; + /* process status to fill in subevent */ + /* See PM 4.26.12.6 */ + TI_DBG1(("ossaHwCB: pEncryptInfo->status 0x%x\n", pEncryptInfo->status)); + if ( pEncryptInfo->status == OSSA_SUCCESS) + { + encryptEventData.subEvent = tiNVRAMSuccess; + } + else if (pEncryptInfo->status == 0x24) + { + encryptEventData.subEvent = tiNVRAMNotFound; + } + else if (pEncryptInfo->status == 0x05 || pEncryptInfo->status == 0x20 || pEncryptInfo->status == 0x21) + { + encryptEventData.subEvent = tiNVRAMAccessTimeout; + } + else + { + encryptEventData.subEvent = tiNVRAMWriteFail; + } + + encryptEventData.pData = agNULL; + ostiPortEvent(tiRoot, + tiEncryptOperation, + securityModeStatus, + &encryptEventData); + + break; + } + case OSSA_HW_EVENT_MODE: + { + pModeEvent = (agsaHWEventMode_t *) eventParm2; + pModePage = (bit32 *) pModeEvent->modePage; + + TI_DBG1(("ossaHwCB: OSSA_HW_EVENT_MODE modePageOperation 0x%x status 0x%x modePageLen 0x%x\n", + pModeEvent->modePageOperation, pModeEvent->status, pModeEvent->modePageLen)); + + if (pModeEvent->modePageOperation == agsaModePageSet) + { + TI_DBG1(("ossaHwCB: OSSA_HW_EVENT_MODE page code 0x%x error qualifier 0x%x\n", (eventParm1 & 0xFF), (eventParm1 >> 16))); + ostiPortEvent(tiRoot, + tiModePageOperation, + pModeEvent->status, + eventParm2); + } + else if (pModeEvent->modePageOperation == agsaModePageGet) + { + TI_DBG1(("ossaHwCB: OSSA_HW_EVENT_MODE error qualifier 0x%x\n", eventParm1)); + switch ((*pModePage) & 0xFF) + { + case AGSA_ENCRYPTION_GENERAL_CONFIG_PAGE: + TI_DBG1(("ossaHwCB: AGSA_ENCRYPTION_GENERAL_CONFIG_PAGE 0x%x %p\n", pModeEvent->status,eventParm2)); + TI_DBG1(("ossaHwCB:modePageOperation 0x%x status 0x%x modePageLen 0x%x modePage %p context %p\n", + pModeEvent->modePageOperation, + pModeEvent->status, + pModeEvent->modePageLen, + pModeEvent->modePage, + pModeEvent->context)); + ostiPortEvent(tiRoot, + tiModePageOperation, + pModeEvent->status, + eventParm2); + break; + case AGSA_ENCRYPTION_DEK_CONFIG_PAGE: + TI_DBG1(("ossaHwCB: AGSA_ENCRYPTION_DEK_CONFIG_PAGE 0x%x %p\n", pModeEvent->status,eventParm2)); + ostiPortEvent(tiRoot, + tiModePageOperation, + pModeEvent->status, + eventParm2); + break; + case AGSA_ENCRYPTION_HMAC_CONFIG_PAGE: + TI_DBG1(("ossaHwCB: AGSA_ENCRYPTION_HMAC_CONFIG_PAGE 0x%x %p\n", pModeEvent->status,eventParm2)); + ostiPortEvent(tiRoot, + tiModePageOperation, + pModeEvent->status, + eventParm2); + break; + case AGSA_ENCRYPTION_CONTROL_PARM_PAGE: + TI_DBG1(("ossaHwCB: AGSA_ENCRYPTION_CONTROL_PARM_PAGE 0x%x %p\n", pModeEvent->status,eventParm2)); + /* + * This page is directly related to tiCOMEncryptGetInfo() and + * will be translated into a tiEncrytOperation for the OS layer. + */ + + /* Fill out tiEncryptInfo_t */ + securityMode = *pModePage & 0x0F00 >> 8; + cipherMode = *pModePage & 0xF000 >> 12; + + if (securityMode == agsaEncryptSMA) + { + encryptInfo.securityCipherMode = TI_ENCRYPT_SEC_MODE_A; + } + else if (securityMode == agsaEncryptSMB) + { + encryptInfo.securityCipherMode = TI_ENCRYPT_SEC_MODE_B; + } + else + { + encryptInfo.securityCipherMode = TI_ENCRYPT_SEC_MODE_FACT_INIT; + } + + if (cipherMode == agsaEncryptCipherModeECB) + { + encryptInfo.securityCipherMode |= TI_ENCRYPT_ATTRIB_CIPHER_ECB; + } + + if (cipherMode == agsaEncryptCipherModeXTS) + { + encryptInfo.securityCipherMode |= TI_ENCRYPT_ATTRIB_CIPHER_XTS; + } + + /* How will subEvents be tracked? */ + encryptInfo.status = 0; + + encryptInfo.sectorSize[0] = 512; /* DIF is allowed on 512 BPS SATA drives */ + encryptInfo.sectorSize[1] = 520; + encryptInfo.sectorSize[2] = 528; + encryptInfo.sectorSize[3] = 4104; + encryptInfo.sectorSize[4] = 4168; + encryptInfo.sectorSize[5] = 4232; + + encryptEventData.encryptEvent = tiEncryptGetInfo; + encryptEventData.subEvent = 0; + encryptEventData.pData = &encryptInfo; + + ostiPortEvent(tiRoot, + tiEncryptOperation, + pModeEvent->status, + &encryptEventData); + break; + case AGSA_SAS_PROTOCOL_TIMER_CONFIG_PAGE: + TI_DBG1(("ossaHwCB: AGSA_SAS_PROTOCOL_TIMER_CONFIG_PAGE 0x%x %p\n", pModeEvent->status,eventParm2)); + +#ifdef IOCTL_INTERRUPT_TIME_CONFIG + ostiPortEvent(tiRoot, + tiModePageOperation, + pModeEvent->status, + eventParm2 + ); +#endif /* IOCTL_INTERRUPT_TIME_CONFIG */ + + /*ostiPortEvent(tiRoot, + tiModePageOperation, + pModeEvent->status, + &encryptEventData);*/ + break; + case AGSA_INTERRUPT_CONFIGURATION_PAGE: + TI_DBG1(("ossaHwCB: AGSA_INTERRUPT_CONFIGURATION_PAGE 0x%x %p\n", pModeEvent->status,eventParm2)); + +#ifdef IOCTL_INTERRUPT_TIME_CONFIG + ostiPortEvent(tiRoot, + tiModePageOperation, + pModeEvent->status, + eventParm2 + ); +#endif /* IOCTL_INTERRUPT_TIME_CONFIG */ + + break; + default: + TI_DBG1(("ossaHwCB: Unknown Mode Event %x\n", *pModePage)); + break; + } + + } + else + { + TI_DBG1(("ossaHwCB: Unknown modePageOperation %x\n", pModeEvent->modePageOperation)); + } + break; + } + +// #endif /* INITIATOR_DRIVER */ + +#ifdef REMOVED + case OSSA_HW_EVENT_PHY_UNRECOVERABLE_ERROR: + { + PhyID = TD_GET_PHY_ID(eventParm1); + PortState = TD_GET_PORT_STATE(eventParm1); + + TI_DBG1(("ossaHwCB: OSSA_HW_EVENT_PHY_UNRECOVERABLE_ERROR\n")); + + if (PortState == OSSA_PORT_INVALID) + { + TI_DBG1(("ossaHwCB: INVALID port state\n")); + } + else + { + TI_DBG1(("ossaHwCB: VALID port state\n")); + } + break; + } +#endif /* REMOVED */ + case OSSA_HW_EVENT_OPEN_RETRY_BACKOFF_THR_ADJUSTED: + { + TI_DBG1(("ossaHwCB: OSSA_HW_EVENT_OPEN_RETRY_BACKOFF_THR_ADJUSTED\n")); + break; + } + + default: + { + TI_DBG1(("ossaHwCB: default error (0x%X)!!!!!\n",event)); + break; + } + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'R', "Y2"); + return; +} + +osGLOBAL void ossaPortControlCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaPortContext_t *agPortContext, + bit32 portOperation, + bit32 status) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaPortContext_t *onePortContext = agNULL; + + TI_DBG6(("ossaPortControlCB: start\n")); + + smTraceFuncEnter(hpDBG_VERY_LOUD,"Y3"); + if (portOperation == AGSA_PORT_SET_SMP_PHY_WIDTH) + { + TI_DBG1(("ossaPortControlCB: portOperation AGSA_PORT_SET_SMP_PHY_WIDTH\n")); + } + else if (portOperation == AGSA_PORT_SET_PORT_RECOVERY_TIME) + { + TI_DBG1(("ossaPortControlCB: portOperation AGSA_PORT_SET_PORT_RECOVERY_TIME\n")); + } + else if (portOperation == AGSA_PORT_IO_ABORT) + { + TI_DBG1(("ossaPortControlCB: portOperation AGSA_PORT_IO_ABORT\n")); + /* code is here because disocvery failed + deregister all targets. Then, later call discovery if broacast is seen in ossaDeregisterDeviceHandleCB. + */ + onePortContext = (tdsaPortContext_t *)agPortContext->osData; + if (onePortContext == agNULL) + { + TI_DBG1(("ossaPortControlCB: onePortContext is NULL\n")); + return; + } + /* qqqqq deregister all devices */ + tdsaDeregisterDevicesInPort(tiRoot, onePortContext); + + } + else if (portOperation == AGSA_PORT_SET_PORT_RESET_TIME) + { + TI_DBG1(("ossaPortControlCB: portOperation AGSA_PORT_SET_PORT_RESET_TIME\n")); + } + else if (portOperation == AGSA_PORT_HARD_RESET) + { + TI_DBG1(("ossaPortControlCB: portOperation AGSA_PORT_HARD_RESET\n")); + } + else if (portOperation == AGSA_PORT_CLEAN_UP) + { + TI_DBG1(("ossaPortControlCB: portOperation AGSA_PORT_CLEAN_UP\n")); + } + else if (portOperation == AGSA_STOP_PORT_RECOVERY_TIMER) + { + TI_DBG1(("ossaPortControlCB: portOperation AGSA_STOP_PORT_RECOVERY_TIMER\n")); + } + else + { + TI_DBG1(("ossaPortControlCB: undefined portOperation %d\n", portOperation)); + } + + TI_DBG1(("ossaPortControlCB: status %d\n", status)); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Y3"); + return; +} + +/***************************************************************************** +*! \brief ossaHwRegRead +* +* Purpose: This routine is called to read a 32-bit value from the PCI +* registers of the controller +* +* \param agRoot: Pointer to chip/driver Instance. +* \param regOffset: Byte offset to chip register from which to read a 32-bit +* value. +* +* \return: 32-bit value. +* +* \note - The scope is shared target and initiator. +* +*****************************************************************************/ +FORCEINLINE +bit32 +ossaHwRegRead(agsaRoot_t *agRoot, + bit32 regOffset + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *) (agRoot->osData); + bit32 return_value; + + + return_value = ostiChipReadBit32 ( + osData->tiRoot, + regOffset + ); + if( agNULL != agRoot->sdkData ) + { + smTrace(hpDBG_REGISTERS,"RR",regOffset); + /* TP:RR regOffset */ + smTrace(hpDBG_REGISTERS,"RV",return_value); + /* TP:RV value read */ + } + + return(return_value); + +} + +/***************************************************************************** +*! \brief ossaHwRegWrite +* +* Purpose: This routine is called to write a 32-bit value to the PCI +* registers of the controller. +* +* \param agRoot: Pointer to chip/driver Instance. +* \param regOffset: Byte offset to chip register to which chipIOValue is +* written. +* \param regValue: 32-bit value to write at chipIOOffset in host byte order. +* +* \return: None. +* +* \note - The scope is shared target and initiator. +* +*****************************************************************************/ +FORCEINLINE +void +ossaHwRegWrite(agsaRoot_t *agRoot, + bit32 regOffset, + bit32 regValue + ) +{ + + tdsaRootOsData_t *osData = (tdsaRootOsData_t *) (agRoot->osData); + if( agNULL != agRoot->sdkData ) + { + smTrace(hpDBG_REGISTERS,"RW",regOffset); + /* TP:RW regOffset */ + smTrace(hpDBG_REGISTERS,"VW",regValue); + /* TP:VW value written */ + } + + ostiChipWriteBit32 ( + osData->tiRoot, + regOffset, + regValue + ); + return; +} + +/***************************************************************************** +*! \brief ossaHwRegReadExt +* +* Purpose: This routine is called to read a 32-bit value from a bus-specific +* mapped registers of the controller +* +* \param agRoot: Pointer to chip/driver Instance. +* \param regOffset: Byte offset to chip register from which to read a 32-bit +* value. +* +* \return: 32-bit value. +* +* \note - The scope is shared target and initiator. +* +*****************************************************************************/ +FORCEINLINE +bit32 +ossaHwRegReadExt( + agsaRoot_t *agRoot, + bit32 busBaseNumber, + bit32 regOffset + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *) (agRoot->osData); + + bit32 return_value; + + return_value = ostiChipReadBit32Ext( + osData->tiRoot, + busBaseNumber, + regOffset + ); + + /* TI_DBG4(("#_R: 0x%x:0x%x=0x%x\n",busBaseNumber,regOffset,return_value)); */ + + if( agNULL != agRoot->sdkData ) + { + smTrace(hpDBG_REGISTERS,"EB",busBaseNumber); + /* TP:EB EX read busBaseNumber */ + smTrace(hpDBG_REGISTERS,"EO",regOffset); + /* TP:EO regOffset */ + smTrace(hpDBG_REGISTERS,"ER",return_value); + /* TP:ER value read */ + } + return(return_value); +} + +void ossaPCI_TRIGGER(agsaRoot_t *agRoot ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *) (agRoot->osData); + ostiPCI_TRIGGER(osData->tiRoot); + +} + + + +/***************************************************************************** +*! \brief ossaHwRegWriteExt +* +* Purpose: This routine is called to write a 32-bit value to a bus specific +* mapped registers of the controller. +* +* \param agRoot: Pointer to chip/driver Instance. +* \param regOffset: Byte offset to chip register to which chipIOValue is +* written. +* \param regValue: 32-bit value to write at chipIOOffset in host byte order. +* +* \return: None. +* +* \note - The scope is shared target and initiator. +* +*****************************************************************************/ +FORCEINLINE +void +ossaHwRegWriteExt( + agsaRoot_t *agRoot, + bit32 busBaseNumber, + bit32 regOffset, + bit32 regValue + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *) (agRoot->osData); + ostiChipWriteBit32Ext( + osData->tiRoot, + busBaseNumber, + regOffset, + regValue + ); + + /* TI_DBG4(("#_W: 0x%x:0x%x=0x%x\n",busBaseNumber,regOffset,regValue)); */ + + if( agNULL != agRoot->sdkData ) + { + smTrace(hpDBG_REGISTERS,"Eb",busBaseNumber); + /* TP:Eb Ex Write busBaseNumber */ + smTrace(hpDBG_REGISTERS,"Eo",regOffset); + /* TP:Eo regOffset */ + smTrace(hpDBG_REGISTERS,"Ew",regValue); + /* TP:Ew value written regValue*/ + } + return; +} + + +osGLOBAL bit32 ossaHwRegReadConfig32( + agsaRoot_t *agRoot, + bit32 regOffset + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *) (agRoot->osData); + bit32 to_ret; + to_ret= ostiChipConfigReadBit32( osData->tiRoot, regOffset); + TI_DBG4(("ossaHwRegReadConfig32: regOffset 0x%x returns 0x%x\n",regOffset,to_ret)); + return(to_ret); +} + + + + +#ifdef TD_INT_COALESCE +void +ossaIntCoalesceInitCB( + agsaRoot_t *agRoot, + agsaIntCoalesceContext_t *agIntCoContext, + bit32 status + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)osData->tdsaAllShared; + tiIntCoalesceContext_t *tiIntCoalesceCxt; + tdsaIntCoalesceContext_t *tdsaIntCoalCxt; + tdsaIntCoalesceContext_t *tdsaIntCoalCxtHead + = (tdsaIntCoalesceContext_t *)tdsaAllShared->IntCoalesce;; + bit32 tiStatus; + + TI_DBG2(("ossaIntCoalesceInitCB: start\n")); + + tdsaIntCoalCxt = (tdsaIntCoalesceContext_t *)agIntCoContext->osData; + tiIntCoalesceCxt = tdsaIntCoalCxt->tiIntCoalesceCxt; + switch (status) + { + case AGSA_RC_SUCCESS: + tiStatus = tiSuccess; + break; + case AGSA_RC_BUSY: + tiStatus = tiBusy; + break; + case AGSA_RC_FAILURE: + tiStatus = tiError; + break; + default: + TI_DBG1(("ossaIntCoalesceInitCB: unknown status %d\n", status)); + tiStatus = tiError; + break; + } + + TI_DBG2(("ossaIntCoalesceInitCB: status %d\n", tiStatus)); + + /* enqueue tdsaIntCoalCxt to freelink */ + tdsaIntCoalCxt->tiIntCoalesceCxt = agNULL; + TI_DBG2(("ossaIntCoalesceInitCB: id %d\n", tdsaIntCoalCxt->id)); + + tdsaSingleThreadedEnter(tiRoot, TD_INTCOAL_LOCK); + TDLIST_DEQUEUE_THIS(&(tdsaIntCoalCxt->MainLink)); + TDLIST_ENQUEUE_AT_TAIL(&(tdsaIntCoalCxt->FreeLink), &(tdsaIntCoalCxtHead->FreeLink)); + tdsaSingleThreadedLeave(tiRoot, TD_INTCOAL_LOCK); + +#ifdef OS_INT_COALESCE + ostiInitiatorIntCoalesceInitCB(tiRoot, + tiIntCoalesceCxt, + tiStatus); +#endif + + TI_DBG2(("ossaIntCoalesceInitCB: return end\n")); + + return; +} +#endif /* TD_INT_COALESCE */ + +/*****************************************************************************/ +/*! \brief ossaSingleThreadedEnter + * + * + * Purpose: This routine is called to ensure that only a single thread of + * the given port instance executes code in the region protected by + * this function. + * + * + * \param agRoot: Pointer to chip/driver Instance. + * \param syncLockId to be explained. + * + * + * \return None. + * + * \note - The scope is shared target and initiator. + * + */ +/*****************************************************************************/ +FORCEINLINE +void ossaSingleThreadedEnter( + agsaRoot_t *agRoot, + bit32 syncLockId + ) +{ + tdsaRootOsData_t *pOsData = agNULL; + tiRoot_t *ptiRoot = agNULL; + tdsaContext_t *tdsaAllShared = agNULL; + + TD_ASSERT(agRoot, "agRoot"); + pOsData = (tdsaRootOsData_t *) (agRoot->osData); + TD_ASSERT(pOsData, "pOsData"); + ptiRoot = pOsData->tiRoot; + TD_ASSERT(ptiRoot, "ptiRoot"); + + tdsaAllShared = (tdsaContext_t *)pOsData->tdsaAllShared; + TD_ASSERT(tdsaAllShared, "tdsaAllShared"); + + ostiSingleThreadedEnter(ptiRoot, syncLockId + tdsaAllShared->MaxNumOSLocks); + return; +} + +/*****************************************************************************/ +/*! \brief ossaSingleThreadedLeave + * + * + * Purpose: This routine is called to leave a critical region of code + * previously protected by a call to osSingleThreadedEnter() + * + * + * \param agRoot: Pointer to chip/driver Instance. + * \param syncLockId to be explained. + * + * + * \return None. + * + * \note - The scope is shared target and initiator. + * + */ +/*****************************************************************************/ +FORCEINLINE +void ossaSingleThreadedLeave( + agsaRoot_t *agRoot, + bit32 syncLockId + ) +{ + tdsaRootOsData_t *pOsData = agNULL; + tiRoot_t *ptiRoot = agNULL; + tdsaContext_t *tdsaAllShared = agNULL; + + TD_ASSERT(agRoot, "agRoot"); + pOsData = (tdsaRootOsData_t *) (agRoot->osData); + TD_ASSERT(pOsData, "pOsData"); + ptiRoot = pOsData->tiRoot; + TD_ASSERT(ptiRoot, "ptiRoot"); + + tdsaAllShared = (tdsaContext_t *)pOsData->tdsaAllShared; + TD_ASSERT(tdsaAllShared, "tdsaAllShared"); + + ostiSingleThreadedLeave(ptiRoot, syncLockId + tdsaAllShared->MaxNumOSLocks); + return; +} + +#ifdef PERF_COUNT +osGLOBAL void ossaEnter(agsaRoot_t *agRoot, int io) +{ + ostiEnter(((tdsaRootOsData_t*)(agRoot->osData))->tiRoot, 0, io); + return; +} + +osGLOBAL void ossaLeave(agsaRoot_t *agRoot, int io) +{ + ostiLeave(((tdsaRootOsData_t*)(agRoot->osData))->tiRoot, 0, io); + return; +} +#endif + + +osGLOBAL void +ossaSSPIoctlCompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit16 sspTag, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdIORequestBody_t *tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + agsaSASRequestBody_t *agSASRequestBody = agNULL; + agsaSSPInitiatorRequest_t *agSSPFrame = agNULL; + bit8 scsiOpcode = 0; + + agSASRequestBody = &(tdIORequestBody->transport.SAS.agSASRequestBody); + agSSPFrame = &(agSASRequestBody->sspInitiatorReq); + scsiOpcode = agSSPFrame->sspCmdIU.cdb[0]; + + TI_DBG2(("ossaSSPIoctlCompleted: start\n")); + + if (agIOStatus == OSSA_SUCCESS) + { + TI_DBG2(("ossaSSPIoctlCompleted: Success status\n")); + } + else + { + TI_DBG1(("ossaSSPIoctlCompleted: Status 0x%x\n", agIOStatus)); + } + switch(scsiOpcode) + { + case REPORT_LUN_OPCODE: + ostiNumOfLUNIOCTLRsp(tiRoot, agIOStatus); + break; + + default: + TI_DBG1(("ossaSSPIoctlCompleted: Unsupported SCSI command Response 0x%x\n",scsiOpcode)); + break; + } + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Yi"); + return; + +} + +osGLOBAL void +ossaSMPIoctlCompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + TI_DBG2(("ossaSMPIoctlCompleted: start\n")); + + if (agIOStatus == OSSA_SUCCESS) + { + TI_DBG2(("ossaSMPIoctlCompleted: Success status\n")); + } + else + { + TI_DBG1(("ossaSMPIoctlCompleted: Status 0x%x\n", agIOStatus)); + } + + ostiSendSMPIOCTLRsp(tiRoot, agIOStatus); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Yi"); + return; + +} + + +/*****************************************************************************/ +/*! \brief ossaSMPCompleted + * + * + * Purpose: This routine is called by lower layer to indicate the completion of + * SMP request + * + * \param agRoot: Pointer to chip/driver Instance. + * \param agIORequest Pointer to SMP request handle + * \param agIOStatus Status + * \param agFrameHeader:Pointer to SMP frame header. + * \param agIOInfoLen IO information length assoicated with the IO + * \param agFrameHandle A Handle used to refer to the response frame + * + * + * \return None. + * + * \note - The scope is shared target and initiator. + * For details, refer to SAS/SATA Low-Level API Specification + */ +/*****************************************************************************/ +osGLOBAL void ossaSMPCompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle + ) +{ +#ifdef PASSTHROUGH + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdPassthroughCmndBody_t *tdPTCmndBody = (tdPassthroughCmndBody_t *)agIORequest->osData; + bit32 tiStatus = tiPassthroughError; + bit8 SMPframe[agIOInfoLen + sizeof(agsaSMPFrameHeader_t)]; + bit8 SMPpayload[agIOInfoLen]; + + TI_DBG2(("ossaSMPCompleted: start and passthrough\n")); +#else /* not PASSTHROUGH */ + + tdssSMPRequestBody_t *pSMPRequestBody = (tdssSMPRequestBody_t *) agIORequest->osData; + TI_DBG4(("ossaSMPCompleted: start\n")); +#endif /* end not PASSTHROUGH */ + + TDSA_OUT_ENTER((tiRoot_t *)((tdsaRootOsData_t *)agRoot->osData)->tiRoot); + smTraceFuncEnter(hpDBG_VERY_LOUD,"Y4"); + +#ifdef PASSTHROUGH + if (tdPTCmndBody == agNULL) + { + TI_DBG1(("ossaSMPCompleted: tdPTCmndBody is NULL \n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Y4"); + goto ext; + } + + if (tdPTCmndBody->EventCB == agNULL) + { + TI_DBG1(("ossaSMPCompleted: tdPTCmndBody->EventCB is NULL \n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "Y4"); + goto ext; + } + + if (agIOStatus == OSSA_IO_SUCCESS) + { + tiStatus = tiPassthroughSuccess; + } + else if (agIOStatus == OSSA_IO_ABORTED) + { + tiStatus = tiPassthroughAborted; + } + else + { + tiStatus = tiPassthroughError; + } + + osti_memset(SMPpayload, 0, agIOInfoLen); + osti_memset(SMPframe, 0, agIOInfoLen + sizeof(agsaSMPFrameHeader_t)); + + /* combine the header and payload */ + saFrameReadBlock(agRoot, agFrameHandle, 0, &SMPpayload, agIOInfoLen); + osti_memcpy(SMPframe, agFrameHeader, sizeof(agsaSMPFrameHeader_t)); + osti_memcpy(SMPframe+sizeof(agsaSMPFrameHeader_t), SMPpayload, agIOInfoLen); + + tdPTCmndBody->EventCB(tiRoot, + tdPTCmndBody->tiPassthroughRequest, + tiStatus, + SMPframe, + agIOInfoLen + sizeof(agsaSMPFrameHeader_t) + ); + + +#else /* not PASSTHROUGH */ + + /* + At initiator, passing SMP to TD layer, itdssSMPCompleted(), which does nothing. + At target, passing SMP to TD layer, ttdsaSMPCompleted() + */ + /* + how to use agFrameHandle, when saFrameReadBlock() is used + */ + + /* SPC can't be SMP target */ + + TI_DBG4(("ossaSMPCompleted: start\n")); + + if (pSMPRequestBody == agNULL) + { + TI_DBG1(("ossaSMPCompleted: pSMPRequestBody is NULL \n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "Y4"); + goto ext; + } + + if (pSMPRequestBody->SMPCompletionFunc == agNULL) + { + TI_DBG1(("ossaSMPCompleted: pSMPRequestBody->SMPCompletionFunc is NULL \n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "Y4"); + goto ext; + } +#ifdef TD_INTERNAL_DEBUG /* debugging */ + TI_DBG4(("ossaSMPCompleted: agIOrequest %p\n", agIORequest->osData)); + TI_DBG4(("ossaSMPCompleted: sizeof(tdIORequestBody_t) %d 0x%x\n", sizeof(tdIORequestBody_t), + sizeof(tdIORequestBody_t))); + TI_DBG4(("ossaSMPCompleted: SMPRequestbody %p\n", pSMPRequestBody)); + TI_DBG4(("ossaSMPCompleted: calling callback fn\n")); + TI_DBG4(("ossaSMPCompleted: callback fn %p\n",pSMPRequestBody->SMPCompletionFunc)); +#endif /* TD_INTERNAL_DEBUG */ + /* + if initiator, calling itdssSMPCompleted() in itdcb.c + if target, calling ttdsaSMPCompleted() in ttdsmp.c + */ + pSMPRequestBody->SMPCompletionFunc( + agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agFrameHandle + ); + +#endif /* Not PASSTHROUGH */ + + smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "Y4"); +ext: + TDSA_OUT_LEAVE((tiRoot_t *)((tdsaRootOsData_t *)agRoot->osData)->tiRoot); + return; +} + +osGLOBAL void +ossaSMPReqReceived( + agsaRoot_t *agRoot, + agsaDevHandle_t *agDevHandle, + agsaFrameHandle_t agFrameHandle, + bit32 agIOInfoLen, + bit32 phyId + ) +{ + smTraceFuncEnter(hpDBG_VERY_LOUD,"Y5"); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Y5"); + return; +} + +/*****************************************************************************/ +/*! \brief ossaSMPCAMCompleted + * + * + * Purpose: This routine is called by lower layer to indicate the completion of + * SMP request + * + * \param agRoot: Pointer to chip/driver Instance. + * \param agIORequest Pointer to SMP request handle + * \param agIOStatus Status + * \param agIOInfoLen IO information length assoicated with the IO + * \param agFrameHandle A Handle used to refer to the response frame + * + * + * \return None. + * + * \note - The scope is shared target and initiator. + * For details, refer to SAS/SATA Low-Level API Specification + */ +/*****************************************************************************/ +osGLOBAL void ossaSMPCAMCompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdIORequestBody_t *tdSMPRequestBody = agNULL; + bit32 context = osData->IntContext; + tiSMPStatus_t status; + bit32 PhysUpper32; + bit32 PhysLower32; + bit32 memAllocStatus; + void *osMemHandle; + bit32 *SMPpayload; + TI_DBG2(("ossaSMPCAMCompleted: start\n")); + TI_DBG2(("ossaSMPCAMCompleted: agIOInfoLen %d\n", agIOInfoLen)); + if (!agIORequest->osData) + { + TD_ASSERT((0), "ossaSMPCAMCompleted agIORequest->osData"); + goto ext; + } + tdSMPRequestBody = (tdIORequestBody_t *)agIORequest->osData; + if (tdSMPRequestBody->tiIORequest->osData == agNULL) + { + TI_DBG1(("ossaSMPCAMCompleted: tdIORequestBody->tiIORequest->osData is null, wrong\n")); + goto ext; + } + /* allocating agIORequest for SMP Payload itself */ + memAllocStatus = ostiAllocMemory( + tiRoot, + &osMemHandle, + (void **)&SMPpayload, + &PhysUpper32, + &PhysLower32, + 8, + agIOInfoLen, + agTRUE + ); + if (memAllocStatus != tiSuccess) + { + /* let os process IO */ + TI_DBG1(("ossaSMPCAMCompleted: ostiAllocMemory failed...\n")); + goto ext; + } + if (SMPpayload == agNULL) + { + TI_DBG1(("ossaSMPCAMCompleted: ostiAllocMemory returned NULL SMPpayload\n")); + goto ext; + } + if (agIOStatus == OSSA_IO_SUCCESS) + { + TI_DBG1(("ossaSMPCAMCompleted: Success status\n")); + osti_memset(SMPpayload, 0, agIOInfoLen); + TI_DBG1(("ossaSMPCAMCompleted: after memset\n")); + saFrameReadBlock(agRoot, agFrameHandle, 0, SMPpayload, agIOInfoLen); + TI_DBG1(("ossaSMPCAMCompleted: after read \n")); + status = tiSMPSuccess; + } + else if (agIOStatus == OSSA_IO_ABORTED) + { + TI_DBG1(("ossaSMPCAMCompleted: SMP Aborted status\n")); + status = tiSMPAborted; + TI_DBG1(("ossaSMPCAMCompleted: failed status=%d\n", status)); + //failed to send smp command, we need to free the memory + ostiFreeMemory( + tiRoot, + osMemHandle, + agIOInfoLen + ); + } + else + { + TI_DBG1(("ossaSMPCAMCompleted: SMP failed status\n")); + status = tiSMPFailed; + TI_DBG1(("ossaSMPCAMCompleted: failed status=%d\n", status)); + //failed to send smp command, we need to free the memory + ostiFreeMemory( + tiRoot, + osMemHandle, + agIOInfoLen + ); + } + ostiInitiatorSMPCompleted(tiRoot, + tdSMPRequestBody->tiIORequest, + status, + agIOInfoLen, + SMPpayload, + context + ); + ext: + TDSA_OUT_LEAVE((tiRoot_t*)((tdsaRootOsData_t*)agRoot->osData)->tiRoot); + return; +} +#ifdef REMOVED +#ifdef TARGET_DRIVER +/*****************************************************************************/ +/*! \brief ossaSMPReqReceived + * + * + * Purpose: This routine is called by lower layer to indicate the reception of + * SMP request + * + * \param agRoot: Pointer to chip/driver Instance. + * \param agDevHandle Pointer to the device handle of the device + * \param agFrameHandle A Handle used to refer to the response frame + * + * + * \return None. + * + * \note - The scope is target only + * For details, refer to SAS/SATA Low-Level API Specification + */ +/*****************************************************************************/ +osGLOBAL void ossaSMPReqReceived( + agsaRoot_t *agRoot, + agsaDevHandle_t *agDevHandle, + agsaFrameHandle_t agFrameHandle, + bit32 agFrameLength, + bit32 phyId + ) +{ + bit8 smpHeader[4]; + agsaSMPFrameHeader_t *agFrameHeader; +#ifdef PASSTHROUGH + /* call the registered function(parameter in tiTGTPassthroughCmndRegister() by target */ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + ttdsaTgt_t *Target = (ttdsaTgt_t *)osData->ttdsaTgt; + + bit8 SMPframe[agIOInfoLen + sizeof(agsaSMPFrameHeader_t)]; + bit8 SMPpayload[agIOInfoLen]; + + TI_DBG2(("ossaSMPReqReceived: start and passthrough\n")); + osti_memset(SMPpayload, 0, agIOInfoLen); + osti_memset(SMPframe, 0, agIOInfoLen + sizeof(agsaSMPFrameHeader_t)); + /* combine smp header and payload */ + saFrameReadBlock(agRoot, agFrameHandle, 0, &SMPpayload, agIOInfoLen); + osti_memcpy(SMPframe, agFrameHeader, sizeof(agsaSMPFrameHeader_t)); + osti_memcpy(SMPframe+sizeof(agsaSMPFrameHeader_t), SMPpayload, agIOInfoLen); + + Target->PasthroughCB( + tiRoot, + tiSASATA, + tiSMP, + tiSMPResponse, + SMPframe, + agIOInfoLen + sizeof(agsaSMPFrameHeader_t), + phyId + ); + +#else + + /* + agDevHandle_t->osData points to tdssDeviceData_t + */ + tdsaDeviceData_t *pDeviceData = (tdsaDeviceData_t *) agDevHandle->osData; + + saFrameReadBlock(agRoot, agFrameHandle, 0, smpHeader, 4); + agFrameHeader = (agsaSMPFrameHeader_t *)smpHeader; + TI_DBG4(("ossaSMPReqReceived: start\n")); + + /* tdtypes.h, calling ttdsaSMPReqReceived in ttdsmp.c */ + pDeviceData->pJumpTable->pSMPReqReceived ( + agRoot, + agDevHandle, + agFrameHeader, + agFrameHandle, + agFrameLength, + phyId + ); +#endif + return; +} +#endif +#endif + +/*****************************************************************************/ +/*! \brief ossaSSPCompleted + * + * + * Purpose: This routine is called by lower layer to indicate the completion of + * SSP request + * + * \param agRoot: Pointer to chip/driver Instance. + * \param agIORequest Pointer to SMP request handle + * \param agIOStatus Status + * \param agIOInfoLen IO information length assoicated with the IO + * \param agFrameHandle A Handle used to refer to the response frame + * + * + * \return None. + * + * \note - The scope is shared target and initiator. + * For details, refer to SAS/SATA Low-Level API Specification + */ +/*****************************************************************************/ +FORCEINLINE +void ossaSSPCompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit16 sspTag, + bit32 agOtherInfo + ) +{ + tdIORequestBody_t *pIORequestBody; +#ifdef TD_DEBUG_ENABLE + tiDeviceHandle_t *tiDeviceHandle = agNULL; + tdsaDeviceData_t *oneDeviceData = agNULL; +#endif + + TDSA_OUT_ENTER((tiRoot_t*)((tdsaRootOsData_t*)agRoot->osData)->tiRoot); + smTraceFuncEnter(hpDBG_VERY_LOUD,"2L"); + + if(!agIORequest->osData) + { + TD_ASSERT((0), "ossaSSPCompleted agIORequest->osData"); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2L"); + goto ext; + } + pIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + + TI_DBG4(("ossaSSPCompleted: start\n")); + + if (pIORequestBody == agNULL) + { + TI_DBG1(("ossaSSPCompleted: pIORequestBody is NULL \n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2L"); + goto ext; + } + if (pIORequestBody->IOCompletionFunc == agNULL) + { +#ifdef TD_DEBUG_ENABLE + tiDeviceHandle = pIORequestBody->tiDevHandle; + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; +#endif + TI_DBG1(("ossaSSPCompleted: IOCompletionFunc is NULL \n")); + TI_DBG1(("ossaSSPCompleted: did %d \n", oneDeviceData->id)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "2L"); + goto ext; + } + + /* + if initiator, calling itdssIOCompleted() in itdcb.c + if initiator, calling itdssTaskCompleted in itdcb.c + if target, calling ttdsaIOCompleted() in ttdio.c + */ + pIORequestBody->IOCompletionFunc( + agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo + ); + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "2L"); +ext: + TDSA_OUT_LEAVE((tiRoot_t*)((tdsaRootOsData_t*)agRoot->osData)->tiRoot); + return; +} + +#ifdef FAST_IO_TEST +GLOBAL void ossaFastSSPCompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *cbArg, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit16 sspTag, + bit32 agOtherInfo + ) +{ + agsaFastCBBuf_t *safb = (agsaFastCBBuf_t*)cbArg; + tdsaRootOsData_t *osData = (tdsaRootOsData_t*)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t*)osData->tiRoot; + bit32 scsi_status; + bit32 data_status; + bit32 respLen; + bit8 respData[128]; + bit32 senseLen; + agsaSSPResponseInfoUnit_t agSSPRespIU; + + TDSA_OUT_ENTER((tiRoot_t*)((tdsaRootOsData_t*)agRoot->osData)->tiRoot); + smTraceFuncEnter(hpDBG_VERY_LOUD,"Y6"); + + TI_DBG4(("ossaSSPCompleted: start\n")); + + if (safb->cb == agNULL || safb->cbArg == agNULL) + { + TI_DBG1(("ossaFastSSPCompleted: pIORequestBody is NULL \n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Y6"); + TD_ASSERT((0), ""); + goto ext; + } + + switch (agIOStatus) + { + case OSSA_IO_SUCCESS: + + /* ~ itdssIOSuccessHandler */ + if ((agIOInfoLen < sizeof(agsaSSPResponseInfoUnit_t))) + { + ((ostiFastSSPCb_t)safb->cb)(tiRoot, safb->cbArg, OSSA_IO_SUCCESS, 0); + break; + } + + /* reads agsaSSPResponseInfoUnit_t */ + saFrameReadBlock(agRoot, agParam, 0, &agSSPRespIU, + sizeof(agsaSSPResponseInfoUnit_t)); + + data_status = SA_SSPRESP_GET_DATAPRES(&agSSPRespIU); + scsi_status = agSSPRespIU.status; + + TI_DBG1(("itdssIOSuccessHandler: scsi_status %d\n", scsi_status)); + + /* endianess is invovled here */ + senseLen = SA_SSPRESP_GET_SENSEDATALEN(&agSSPRespIU); + respLen = SA_SSPRESP_GET_RESPONSEDATALEN(&agSSPRespIU); + TI_DBG2(("itdssIOSuccessHandler: scsi status=0x%x, senselen=0x%x resplen " + "0x%x\n", scsi_status, senseLen, respLen)); + + if (agIOInfoLen < sizeof(agsaSSPResponseInfoUnit_t) + senseLen + respLen) + { + ((ostiFastSSPCb_t)safb->cb)(tiRoot, safb->cbArg, tiIOFailed, + tiDetailOtherError); + break; + } + + /* reads response data */ + saFrameReadBlock(agRoot, agParam, sizeof(agsaSSPResponseInfoUnit_t), + respData, respLen); + /* reads sense data */ + saFrameReadBlock(agRoot, agParam, sizeof(agsaSSPResponseInfoUnit_t) + + respLen, safb->pSenseData, senseLen); + + if (data_status == 0) + { + /* NO_DATA */ + TI_DBG2(("ossaFastSSPCompleted: no data\n")); + ((ostiFastSSPCb_t)safb->cb)(tiRoot, safb->cbArg, tiIOSuccess, + scsi_status); + break; + } + + if (data_status == 1) + { + /* RESPONSE_DATA */ + TI_DBG1(("ossaFastSSPCompleted: response data \n")); + ((ostiFastSSPCb_t)safb->cb)(tiRoot, safb->cbArg, tiIOSuccess, 0); + break; + } + + if (data_status == 2) + { + tiSenseData_t senseData; + + /* SENSE_DATA */ + TI_DBG2(("itdssIOSuccessHandler: sense data \n")); + + senseData.senseData = safb->pSenseData; + senseData.senseLen = MIN(*(safb->senseLen), senseLen); + + /* when ASC = 0x04 - Log Unit Not Ready, + and ASCQ = 0x11 - Enable Spinup Required: + call saLocalPhyControl to notify spinup */ + if (((char*)safb->pSenseData)[12] == 0x04 && + ((char*)safb->pSenseData)[13] == 0x11) + { + int i; + + TI_DBG2(("ossaFastSSPCompleted: sending notfify spinup\n")); + + if (((tdsaDeviceData_t*)safb->oneDeviceData)->directlyAttached == + agTRUE) + { + for (i = 0; i < TD_MAX_NUM_NOTIFY_SPINUP; i++) + { + saLocalPhyControl(agRoot, agNULL, 0, + ((tdsaDeviceData_t*)safb->oneDeviceData)->phyID, + AGSA_PHY_NOTIFY_ENABLE_SPINUP, + agNULL); + } + } + } + + if (*(safb->senseLen) > senseData.senseLen) + *(safb->senseLen) = senseData.senseLen; +// memcpy((void *)safb->pSenseData, senseData.senseData, safb->senseLen); + + ((ostiFastSSPCb_t)safb->cb)(tiRoot, safb->cbArg, tiIOSuccess, + scsi_status); + break; + } + + if (data_status == 3) + { + /* RESERVED */ + TI_DBG1(("ossaFastSSPCompleted: reserved wrong!!!\n")); + + ((ostiFastSSPCb_t)safb->cb)(tiRoot, safb->cbArg, tiIOFailed, + scsi_status); + break; + } + break; +#ifdef REMOVED + case OSSA_IO_OVERFLOW: + ((ostiFastSSPCb_t)safb->cb)(tiRoot, safb->cbArg, tiIOOverRun, + agIOInfoLen); + break; +#endif /* REMOVED */ + case OSSA_IO_UNDERFLOW: + ((ostiFastSSPCb_t)safb->cb)(tiRoot, safb->cbArg, tiIOUnderRun, + agIOInfoLen); + break; + + case OSSA_IO_ABORTED: + ((ostiFastSSPCb_t)safb->cb)(tiRoot, safb->cbArg, tiIOFailed, + tiDetailAborted); + break; + case OSSA_IO_ABORT_RESET: + ((ostiFastSSPCb_t)safb->cb)(tiRoot, safb->cbArg, tiIOFailed, + tiDetailAbortReset); + break; + case OSSA_IO_NO_DEVICE: + ((ostiFastSSPCb_t)safb->cb)(tiRoot, safb->cbArg, tiIOFailed, + tiDetailNoLogin); + break; + case OSSA_IO_DS_NON_OPERATIONAL: + { + + tdsaDeviceData_t *oneDeviceData; + + oneDeviceData = (tdsaDeviceData_t*)safb->oneDeviceData; + if (oneDeviceData->valid == agTRUE && + oneDeviceData->registered == agTRUE && + oneDeviceData->tdPortContext != agNULL) + { + saSetDeviceState(oneDeviceData->agRoot, agNULL, tdsaRotateQnumber(tiRoot, oneDeviceData), + oneDeviceData->agDevHandle, SA_DS_OPERATIONAL); + } + /* fall through */ + } + + default: + ((ostiFastSSPCb_t)safb->cb)(tiRoot, safb->cbArg, tiIOFailed, + tiDetailOtherError); + break; + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "Y6"); + +ext: + TDSA_OUT_LEAVE((tiRoot_t*)((tdsaRootOsData_t*)agRoot->osData)->tiRoot); + return; +} /* ossaFastSSPCompleted */ +#endif + +/*****************************************************************************/ +/*! \brief ossaSSPReqReceived + * + * + * Purpose: This routine is called by lower layer to indicate the reception of + * SMP request + * + * \param agRoot: Pointer to chip/driver Instance. + * \param agDevHandle Pointer to the device handle of the device + * \param agFrameHandle A Handle used to refer to the response frame + * \param agInitiatorTag the initiator tag + * \param agFrameType SSP frame type + * + * \return none. + * + * \note - The scope is target only + * For details, refer to SAS/SATA Low-Level API Specification + */ +/*****************************************************************************/ +osGLOBAL void ossaSSPReqReceived( + agsaRoot_t *agRoot, + agsaDevHandle_t *agDevHandle, + agsaFrameHandle_t agFrameHandle, + bit16 agInitiatorTag, + bit32 parameter, + bit32 agFrameLen + ) +{ + /* + at target only + uses jumptable, not callback + */ + /* + agDevHandle_t->osData points to tdssDeviceData_t + */ + tdsaDeviceData_t *pDeviceData = (tdsaDeviceData_t *) agDevHandle->osData; + smTraceFuncEnter(hpDBG_VERY_LOUD,"Y7"); + + /* tdtypes.h, calling ttdsaSSPReqReceived() in ttdio.c */ + pDeviceData->pJumpTable->pSSPReqReceived ( + agRoot, + agDevHandle, + agFrameHandle, + agInitiatorTag, + parameter, + agFrameLen + ); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Y7"); + return; +} +/*****************************************************************************/ +/*! \brief ossaStallThread + * + * + * Purpose: This routine is called to stall this thread for a number of + * microseconds. + * + * + * \param agRoot: Pointer to chip/driver Instance. + * \param microseconds: Micro second to stall. + * + * + * \return None. + * + * \note - The scope is shared target and initiator. + * + */ +/*****************************************************************************/ +osGLOBAL void ossaStallThread(agsaRoot_t *agRoot, + bit32 microseconds + ) +{ + tdsaRootOsData_t *pOsData = (tdsaRootOsData_t *) (agRoot->osData); + + ostiStallThread ( + pOsData->tiRoot, + microseconds + ); + return; +} + + +/***************************************************************************** +*! \brief ossaSSPEvent +* +* This routine is called to notify the OS Layer of an event associated with +* SAS port or SAS device +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest Pointer to IO request +* \param event: event type +* \param agIOInfoLen: not in use +* \param agFrameHandle: not in use +* +* \return: none +* +*****************************************************************************/ +/* in case of CMD ACK_NAK timeout, send query task */ +osGLOBAL void ossaSSPEvent( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + agsaPortContext_t *agPortContext, + agsaDevHandle_t *agDevHandle, + bit32 event, + bit16 sspTag, + bit32 agIOInfoLen, + void *agParam + ) +{ +#ifdef INITIATOR_DRIVER + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + /* bit32 intContext = osData->IntContext; */ + void *osMemHandle; + tdIORequestBody_t *TMtdIORequestBody; + bit32 PhysUpper32; + bit32 PhysLower32; + bit32 memAllocStatus; + bit32 agRequestType; + agsaIORequest_t *agTMIORequest = agNULL; /* task management itself */ + agsaSASRequestBody_t *agSASRequestBody = agNULL; + agsaSSPScsiTaskMgntReq_t *agSSPTaskMgntRequest; + bit32 saStatus; + bit32 agIORequestType; /* type of IO recevied */ + tiIORequest_t *taskTag; /* being task managed one */ + tdIORequestBody_t *tdIORequestBody; +#endif + +#ifdef REMOVED + tiDeviceHandle_t *tiDeviceHandle; + tdsaDeviceData_t *oneDeviceData = agNULL; + tdIORequestBody_t *tdAbortIORequestBody; +#endif + agsaDifDetails_t agDifDetails; + bit8 framePayload[256]; +#ifdef REMOVED + bit16 frameOffset = 0; +#endif + bit16 frameLen = 0; + + TI_DBG6(("ossaSSPEvent: start\n")); + smTraceFuncEnter(hpDBG_VERY_LOUD,"Y9"); + + + + if (event == OSSA_IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT || + event == OSSA_IO_XFER_ERROR_BREAK || + event == OSSA_IO_XFER_ERROR_PHY_NOT_READY + ) + { + + /* IO being task managed(the original IO) depending on event */ +#ifdef INITIATOR_DRIVER + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + taskTag = tdIORequestBody->tiIORequest; +#endif +#ifdef REMOVED + tiDeviceHandle = tdIORequestBody->tiDevHandle; + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; +#endif + +#ifdef INITIATOR_DRIVER + agIORequestType = tdIORequestBody->agRequestType; + + /* error checking; only command is expected here */ + if (agIORequestType == AGSA_REQ_TYPE_UNKNOWN) + { + TI_DBG1(("ossaSSPEvent: incorrect frame 0x%x. Should be command\n", agIORequestType)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Y9"); + return; + } + + /* Allocate memory for query task management */ + memAllocStatus = ostiAllocMemory( + tiRoot, + &osMemHandle, + (void **)&TMtdIORequestBody, + &PhysUpper32, + &PhysLower32, + 8, + sizeof(tdIORequestBody_t), + agTRUE + ); + + if (memAllocStatus != tiSuccess) + { + /* let os process IO */ + TI_DBG1(("ossaSSPEvent: ostiAllocMemory failed...\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "Y9"); + return; + } + + if (TMtdIORequestBody == agNULL) + { + /* let os process IO */ + TI_DBG1(("ossaSSPEvent: ostiAllocMemory returned NULL TMIORequestBody\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "Y9"); + return; + } + + /* setup task management structure */ + TMtdIORequestBody->IOType.InitiatorTMIO.osMemHandle = osMemHandle; + /* TD generates Query Task not OS layer */ + TMtdIORequestBody->IOType.InitiatorTMIO.CurrentTaskTag = agNULL; + TMtdIORequestBody->IOType.InitiatorTMIO.TaskTag = taskTag; + + /* initialize callback function */ + TMtdIORequestBody->IOCompletionFunc = itdssQueryTaskCompleted; + + /* initialize tiDevhandle */ + TMtdIORequestBody->tiDevHandle = tdIORequestBody->tiDevHandle; + + + /* initialize agIORequest */ + agTMIORequest = &(TMtdIORequestBody->agIORequest); + agTMIORequest->osData = (void *) TMtdIORequestBody; + agTMIORequest->sdkData = agNULL; /* LL takes care of this */ + + /* request type */ + agRequestType = AGSA_SSP_TASK_MGNT_REQ; + TMtdIORequestBody->agRequestType = AGSA_SSP_TASK_MGNT_REQ; + + /* + initialize + tdIORequestBody_t tdIORequestBody -> agSASRequestBody + */ + agSASRequestBody = &(TMtdIORequestBody->transport.SAS.agSASRequestBody); + agSSPTaskMgntRequest = &(agSASRequestBody->sspTaskMgntReq); + + /* fill up LUN field */ + osti_memset(agSSPTaskMgntRequest->lun, 0, 8); + + /* sets taskMgntFunction field */ + agSSPTaskMgntRequest->taskMgntFunction = AGSA_QUERY_TASK; + /* debugging */ + if (TMtdIORequestBody->IOCompletionFunc == agNULL) + { + TI_DBG1(("ossaSSPEvent: Error !!! IOCompletionFunc is NULL\n")); + } + /* send query task management */ + saStatus = saSSPStart(agRoot, + agTMIORequest, + 0, + agDevHandle, + agRequestType, + agSASRequestBody, + agIORequest, + &ossaSSPCompleted); + + if (saStatus != AGSA_RC_SUCCESS) + { + /* free up allocated memory */ + ostiFreeMemory( + tiRoot, + TMtdIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + TI_DBG1(("ossaSSPEvent: saSSPStart failed\n")); + return; + } +#endif + } +#ifdef REMOVED + else if (event == OSSA_IO_ABORTED) + { + TI_DBG2(("ossaSSPEvent: OSSA_IO_ABORTED\n")); + /* clean up TD layer's IORequestBody */ + tdAbortIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + + } + else if (event == OSSA_IO_NOT_VALID) + { + TI_DBG1(("ossaSSPEvent: OSSA_IO_NOT_VALID\n")); + tdAbortIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + + + } +#endif + else if (event == OSSA_IO_XFER_CMD_FRAME_ISSUED) + { + TI_DBG2(("ossaSSPEvent: OSSA_IO_XFER_CMD_FRAME_ISSUED\n")); + } + else if (event == OSSA_IO_XFER_ERROR_OFFSET_MISMATCH) + { + TI_DBG1(("ossaSSPEvent: OSSA_IO_XFER_ERROR_OFFSET_MISMATCH\n")); + } + else if (event == OSSA_IO_OVERFLOW) + { + TI_DBG1(("ossaSSPEvent: OSSA_IO_OVERFLOW\n")); + /* + ??? can't call; missing agIOInfoLen + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOOverRun, + agIOInfoLen, + agNULL, + intContext + ); + + */ + + } + else if (event == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED) + { + TI_DBG1(("ossaSSPEvent: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED\n")); + } + else if (event == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO) + { + TI_DBG1(("ossaSSPEvent: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO\n")); + } + else if (event == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST) + { + TI_DBG1(("ossaSSPEvent: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST\n")); + } + else if (event == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE) + { + TI_DBG1(("ossaSSPEvent: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE\n")); + } + else if (event == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED) + { + TI_DBG1(("ossaSSPEvent: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED\n")); + } + else if (event == OSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH) + { + TI_DBG1(("ossaSSPEvent: OSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH\n")); + } + else if (event == OSSA_IO_XFER_ERROR_XFER_RDY_OVERRUN) + { + TI_DBG1(("ossaSSPEvent: OSSA_IO_XFER_ERROR_XFER_RDY_OVERRUN\n")); + } + else if (event == OSSA_IO_XFR_ERROR_DIF_MISMATCH || + event == OSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH || + event == OSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH || + event == OSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH ) + { + TI_DBG1(("ossaSSPEvent: DIF related, event 0x%x\n", event)); + /* process DIF detail information */ + TI_DBG2(("ossaSSPEvent: agIOInfoLen %d\n", agIOInfoLen)); + if (agParam == agNULL) + { + TI_DBG2(("ossaSSPEvent: agParam is NULL!!!\n")); + return; + } + if (agIOInfoLen < sizeof(agsaDifDetails_t)) + { + TI_DBG2(("ossaSSPEvent: wrong agIOInfoLen!!! agIOInfoLen %d sizeof(agsaDifDetails_t) %d\n", agIOInfoLen, (int)sizeof(agsaDifDetails_t))); + return; + } + /* reads agsaDifDetails_t */ + saFrameReadBlock(agRoot, agParam, 0, &agDifDetails, sizeof(agsaDifDetails_t)); +#ifdef REMOVED + frameOffset = (agDifDetails.ErrBoffsetEDataLen & 0xFFFF); +#endif + frameLen = (bit16)((agDifDetails.ErrBoffsetEDataLen & 0xFFFF0000) >> 16); + + TI_DBG2(("ossaSSPEvent: UpperLBA 0x%08x LowerLBA 0x%08x\n", agDifDetails.UpperLBA, agDifDetails.LowerLBA)); + TI_DBG2(("ossaSSPEvent: SASAddrHI 0x%08x SASAddrLO 0x%08x\n", + TD_GET_SAS_ADDRESSHI(agDifDetails.sasAddressHi), TD_GET_SAS_ADDRESSLO(agDifDetails.sasAddressLo))); + TI_DBG2(("ossaSSPEvent: DIF error mask 0x%x Device ID 0x%x\n", + (agDifDetails.DIFErrDevID) & 0xFF, (agDifDetails.DIFErrDevID & 0xFFFF0000) >> 16)); + if (frameLen != 0 && frameLen <= 256) + { + saFrameReadBlock(agRoot, agParam, sizeof(agsaDifDetails_t), framePayload, frameLen); + tdhexdump("ossaSSPEvent frame", framePayload, frameLen); + } + } + else + { + TI_DBG1(("ossaSSPEvent: other event 0x%x\n", event)); + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "Y9"); + return; +} + +#ifdef FDS_SM +osGLOBAL void ossaSATAIDAbortCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 flag, + bit32 status) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdIORequestBody_t *tdAbortIORequestBody; + + TI_DBG1(("ossaSATAIDAbortCB: start flag %d status %d\n", flag, status)); + + tdAbortIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + /* + triggered by tdIDStartTimerCB + */ + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; +} +#endif + +#ifdef INITIATOR_DRIVER +osGLOBAL void ossaSSPAbortCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 flag, + bit32 status) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdIORequestBody_t *tdAbortIORequestBody = agNULL; + tdsaDeviceData_t *oneDeviceData = agNULL; + tiDeviceHandle_t *tiDeviceHandle = agNULL; + tiIORequest_t *taskTag = agNULL; + + TI_DBG2(("ossaSSPAbortCB: start\n")); + smTraceFuncEnter(hpDBG_VERY_LOUD,"Ya"); + + tdAbortIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + if (tdAbortIORequestBody == agNULL) + { + TI_DBG1(("ossaSSPAbortCB: tdAbortIORequestBody is NULL warning!!!!\n")); + return; + } + + if (flag == 2) + { + /* abort per port */ + TI_DBG1(("ossaSSPAbortCB: abort per port\n")); + } + else if (flag == 1) + { + TI_DBG2(("ossaSSPAbortCB: abort all\n")); + + tiDeviceHandle = (tiDeviceHandle_t *)tdAbortIORequestBody->tiDevHandle; + if (tiDeviceHandle == agNULL) + { + TI_DBG1(("ossaSSPAbortCB: tiDeviceHandle is NULL warning!!!!\n")); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; + } + + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + if (oneDeviceData == agNULL) + { + TI_DBG1(("ossaSSPAbortCB: oneDeviceData is NULL warning!!!!\n")); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; + } + + if (status == OSSA_IO_SUCCESS) + { + TI_DBG2(("ossaSSPAbortCB: OSSA_IO_SUCCESS\n")); + /* clean up TD layer's IORequestBody */ + if (oneDeviceData->OSAbortAll == agTRUE) + { + oneDeviceData->OSAbortAll = agFALSE; + ostiInitiatorEvent( tiRoot, + agNULL, + tiDeviceHandle, + tiIntrEventTypeLocalAbort, + tiAbortOK, + agNULL); + } + else + { + TI_DBG2(("ossaSSPAbortCB: calling saDeregisterDeviceHandle\n")); + saDeregisterDeviceHandle(agRoot, agNULL, oneDeviceData->agDevHandle, tdsaRotateQnumber(tiRoot, oneDeviceData)); + } + TI_DBG2(("ossaSSPAbortCB: did %d\n", oneDeviceData->id)); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + + } + else if (status == OSSA_IO_NOT_VALID) + { + TI_DBG1(("ossaSSPAbortCB: OSSA_IO_NOT_VALID\n")); + /* clean up TD layer's IORequestBody */ + if (oneDeviceData->OSAbortAll == agTRUE) + { + oneDeviceData->OSAbortAll = agFALSE; + ostiInitiatorEvent( tiRoot, + agNULL, + tiDeviceHandle, + tiIntrEventTypeLocalAbort, + tiAbortFailed, + agNULL ); + } + else + { + TI_DBG2(("ossaSSPAbortCB: calling saDeregisterDeviceHandle\n")); + saDeregisterDeviceHandle(agRoot, agNULL, oneDeviceData->agDevHandle, tdsaRotateQnumber(tiRoot, oneDeviceData)); + } + TI_DBG2(("ossaSSPAbortCB: did %d\n", oneDeviceData->id)); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + else if (status == OSSA_IO_NO_DEVICE) + { + TI_DBG1(("ossaSSPAbortCB: OSSA_IO_NO_DEVICE\n")); + /* clean up TD layer's IORequestBody */ + if (oneDeviceData->OSAbortAll == agTRUE) + { + oneDeviceData->OSAbortAll = agFALSE; + ostiInitiatorEvent( tiRoot, + agNULL, + tiDeviceHandle, + tiIntrEventTypeLocalAbort, + tiAbortInProgress, + agNULL ); + } + else + { + TI_DBG2(("ossaSSPAbortCB: calling saDeregisterDeviceHandle\n")); + saDeregisterDeviceHandle(agRoot, agNULL, oneDeviceData->agDevHandle, tdsaRotateQnumber(tiRoot, oneDeviceData)); + } + TI_DBG2(("ossaSSPAbortCB: did %d\n", oneDeviceData->id)); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + else if (status == OSSA_IO_ABORT_IN_PROGRESS) + { + TI_DBG1(("ossaSSPAbortCB: OSSA_IO_ABORT_IN_PROGRESS\n")); + /* clean up TD layer's IORequestBody */ + if (oneDeviceData->OSAbortAll == agTRUE) + { + oneDeviceData->OSAbortAll = agFALSE; + ostiInitiatorEvent( tiRoot, + agNULL, + tiDeviceHandle, + tiIntrEventTypeLocalAbort, + tiAbortInProgress, + agNULL ); + } + else + { + TI_DBG2(("ossaSSPAbortCB: calling saDeregisterDeviceHandle\n")); + saDeregisterDeviceHandle(agRoot, agNULL, oneDeviceData->agDevHandle, tdsaRotateQnumber(tiRoot, oneDeviceData)); + } + TI_DBG2(("ossaSSPAbortCB: did %d\n", oneDeviceData->id)); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } +#ifdef REMOVED + else if (status == OSSA_IO_ABORT_DELAYED) + { + TI_DBG1(("ossaSSPAbortCB: OSSA_IO_ABORT_DELAYED\n")); + /* clean up TD layer's IORequestBody */ + if (oneDeviceData->OSAbortAll == agTRUE) + { + oneDeviceData->OSAbortAll = agFALSE; + ostiInitiatorEvent( tiRoot, + agNULL, + tiDeviceHandle, + tiIntrEventTypeLocalAbort, + tiAbortDelayed, + agNULL ); + } + else + { + TI_DBG2(("ossaSSPAbortCB: calling saDeregisterDeviceHandle\n")); + saDeregisterDeviceHandle(agRoot, agNULL, oneDeviceData->agDevHandle, tdsaRotateQnumber(tiRoot, oneDeviceData)); + } + TI_DBG2(("ossaSSPAbortCB: did %d\n", oneDeviceData->id)); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } +#endif + else + { + TI_DBG1(("ossaSSPAbortCB: other status %d\n", status)); + /* clean up TD layer's IORequestBody */ + if (oneDeviceData->OSAbortAll == agTRUE) + { + oneDeviceData->OSAbortAll = agFALSE; + ostiInitiatorEvent( tiRoot, + agNULL, + tiDeviceHandle, + tiIntrEventTypeLocalAbort, + tiAbortInProgress, + agNULL ); + } + else + { + TI_DBG2(("ossaSSPAbortCB: calling saDeregisterDeviceHandle\n")); + saDeregisterDeviceHandle(agRoot, agNULL, oneDeviceData->agDevHandle, tdsaRotateQnumber(tiRoot, oneDeviceData)); + } + TI_DBG2(("ossaSSPAbortCB: did %d\n", oneDeviceData->id)); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + } + else if (flag == 0) + { + TI_DBG2(("ossaSSPAbortCB: abort one\n")); + taskTag = tdAbortIORequestBody->tiIOToBeAbortedRequest; + + if ( taskTag == agNULL) + { + TI_DBG1(("ossaSSPAbortCB: taskTag is NULL; triggered by itdssQueryTaskCompleted\n")); + } + if (status == OSSA_IO_SUCCESS) + { + TI_DBG2(("ossaSSPAbortCB: OSSA_IO_SUCCESS\n")); + if (taskTag != agNULL) + { + ostiInitiatorEvent( tiRoot, + agNULL, + agNULL, + tiIntrEventTypeLocalAbort, + tiAbortOK, + taskTag ); + } + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + + } + else if (status == OSSA_IO_NOT_VALID) + { + TI_DBG1(("ossaSSPAbortCB: OSSA_IO_NOT_VALID\n")); + + if (taskTag != agNULL) + { + ostiInitiatorEvent( tiRoot, + agNULL, + agNULL, + tiIntrEventTypeLocalAbort, + tiAbortFailed, + taskTag ); + } + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + else if (status == OSSA_IO_NO_DEVICE) + { + TI_DBG1(("ossaSSPAbortCB: OSSA_IO_NO_DEVICE\n")); + + if (taskTag != agNULL) + { + ostiInitiatorEvent( tiRoot, + agNULL, + agNULL, + tiIntrEventTypeLocalAbort, + tiAbortInProgress, + taskTag ); + } + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + else if (status == OSSA_IO_ABORT_IN_PROGRESS) + { + TI_DBG1(("ossaSSPAbortCB: OSSA_IO_ABORT_IN_PROGRESS\n")); + + if (taskTag != agNULL) + { + ostiInitiatorEvent( tiRoot, + agNULL, + agNULL, + tiIntrEventTypeLocalAbort, + tiAbortInProgress, + taskTag ); + } + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } +#ifdef REMOVED + else if (status == OSSA_IO_ABORT_DELAYED) + { + TI_DBG1(("ossaSSPAbortCB: OSSA_IO_ABORT_DELAYED\n")); + + if (taskTag != agNULL) + { + ostiInitiatorEvent( tiRoot, + agNULL, + agNULL, + tiIntrEventTypeLocalAbort, + tiAbortDelayed, + taskTag ); + } + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } +#endif + else + { + TI_DBG1(("ossaSSPAbortCB: other status %d\n", status)); + + if (taskTag != agNULL) + { + ostiInitiatorEvent( tiRoot, + agNULL, + agNULL, + tiIntrEventTypeLocalAbort, + tiAbortFailed, + taskTag ); + } + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + } + else + { + TI_DBG1(("ossaSSPAbortCB: wrong flag %d\n", flag)); + } + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Ya"); + return; + +} +#endif + + +#ifdef TARGET_DRIVER +osGLOBAL void ossaSSPAbortCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 flag, + bit32 status) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdIORequestBody_t *tdAbortIORequestBody; + tdsaDeviceData_t *oneDeviceData; + tiDeviceHandle_t *tiDeviceHandle; + + TI_DBG3(("ossaSSPAbortCB: start\n")); + tdAbortIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + if (flag == 2) + { + /* abort per port */ + TI_DBG2(("ossaSSPAbortCB: abort per port\n")); + } + else if (flag == 1) + { + TI_DBG2(("ossaSSPAbortCB: abort all\n")); + tiDeviceHandle = (tiDeviceHandle_t *)tdAbortIORequestBody->tiDevHandle; + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + if (status == OSSA_IO_SUCCESS) + { + TI_DBG2(("ossaSSPAbortCB: OSSA_IO_SUCCESS\n")); + /* clean up TD layer's IORequestBody */ + TI_DBG3(("ossaSSPAbortCB: calling saDeregisterDeviceHandle\n")); + saDeregisterDeviceHandle(agRoot, agNULL, oneDeviceData->agDevHandle, tdsaRotateQnumber(tiRoot, oneDeviceData)); + TI_DBG2(("ossaSSPAbortCB: did %d\n", oneDeviceData->id)); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + + } + else if (status == OSSA_IO_NOT_VALID) + { + TI_DBG1(("ossaSSPAbortCB: OSSA_IO_NOT_VALID\n")); + /* clean up TD layer's IORequestBody */ + TI_DBG2(("ossaSSPAbortCB: calling saDeregisterDeviceHandle\n")); + saDeregisterDeviceHandle(agRoot, agNULL, oneDeviceData->agDevHandle, tdsaRotateQnumber(tiRoot, oneDeviceData)); + TI_DBG2(("ossaSSPAbortCB: did %d\n", oneDeviceData->id)); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + else if (status == OSSA_IO_NO_DEVICE) + { + TI_DBG1(("ossaSSPAbortCB: OSSA_IO_NO_DEVICE\n")); + /* clean up TD layer's IORequestBody */ + TI_DBG2(("ossaSSPAbortCB: calling saDeregisterDeviceHandle\n")); + saDeregisterDeviceHandle(agRoot, agNULL, oneDeviceData->agDevHandle, tdsaRotateQnumber(tiRoot, oneDeviceData)); + TI_DBG2(("ossaSSPAbortCB: did %d\n", oneDeviceData->id)); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + else if (status == OSSA_IO_ABORT_IN_PROGRESS) + { + TI_DBG1(("ossaSSPAbortCB: OSSA_IO_ABORT_IN_PROGRESS\n")); + /* clean up TD layer's IORequestBody */ + TI_DBG2(("ossaSSPAbortCB: calling saDeregisterDeviceHandle\n")); + saDeregisterDeviceHandle(agRoot, agNULL, oneDeviceData->agDevHandle, tdsaRotateQnumber(tiRoot, oneDeviceData)); + TI_DBG2(("ossaSSPAbortCB: did %d\n", oneDeviceData->id)); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } +#ifdef REMOVED + else if (status == OSSA_IO_ABORT_DELAYED) + { + TI_DBG1(("ossaSSPAbortCB: OSSA_IO_ABORT_DELAYED\n")); + /* clean up TD layer's IORequestBody */ + TI_DBG2(("ossaSSPAbortCB: calling saDeregisterDeviceHandle\n")); + saDeregisterDeviceHandle(agRoot, agNULL, oneDeviceData->agDevHandle, tdsaRotateQnumber(tiRoot, oneDeviceData)); + TI_DBG2(("ossaSSPAbortCB: did %d\n", oneDeviceData->id)); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } +#endif + else + { + TI_DBG1(("ossaSSPAbortCB: other status %d\n", status)); + /* clean up TD layer's IORequestBody */ + TI_DBG2(("ossaSSPAbortCB: calling saDeregisterDeviceHandle\n")); + saDeregisterDeviceHandle(agRoot, agNULL, oneDeviceData->agDevHandle, tdsaRotateQnumber(tiRoot, oneDeviceData)); + TI_DBG1(("ossaSSPAbortCB: did %d\n", oneDeviceData->id)); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + } + else if (flag == 0) + { + TI_DBG2(("ossaSSPAbortCB: abort one\n")); + if (status == OSSA_IO_SUCCESS) + { + TI_DBG2(("ossaSSPAbortCB: OSSA_IO_SUCCESS\n")); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + + } + else if (status == OSSA_IO_NOT_VALID) + { + TI_DBG1(("ossaSSPAbortCB: OSSA_IO_NOT_VALID\n")); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + else if (status == OSSA_IO_NO_DEVICE) + { + TI_DBG1(("ossaSSPAbortCB: OSSA_IO_NO_DEVICE\n")); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + else if (status == OSSA_IO_ABORT_IN_PROGRESS) + { + TI_DBG1(("ossaSSPAbortCB: OSSA_IO_ABORT_IN_PROGRESS\n")); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } +#ifdef REMOVED + else if (status == OSSA_IO_ABORT_DELAYED) + { + TI_DBG1(("ossaSSPAbortCB: OSSA_IO_ABORT_DELAYED\n")); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } +#endif + else + { + TI_DBG1(("ossaSSPAbortCB: other status %d\n", status)); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + } + else + { + TI_DBG1(("ossaSSPAbortCB: wrong flag %d\n", flag)); + } + + return; + +} +#endif + + +/*****************************************************************************/ +/*! \brief ossaLocalPhyControlCB + * + * + * Purpose: This routine is called by lower layer to indicate the status of + * phy operations + * + * \param agRoot: Pointer to chip/driver Instance. + * \param phyId Phy id + * \param phyOperation Operation to be done on the phy + * \param status Phy operation specific completion status + * \param parm Additional parameter, phy operation and status specific + * + * + * \return None. + * + */ +/*****************************************************************************/ +osGLOBAL void ossaLocalPhyControlCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 phyId, + bit32 phyOperation, + bit32 status, + void *parm + ) +{ +#ifdef REMVOED + agsaPhyErrCounters_t *agPhyErrCounters; +#endif +#ifdef INITIATOR_DRIVER + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tiIORequest_t *currentTaskTag; + tdsaDeviceData_t *TargetDeviceData; + satDeviceData_t *pSatDevData; + agsaDevHandle_t *agDevHandle = agNULL; + agsaContext_t *agContextDevice; +#endif + + smTraceFuncEnter(hpDBG_VERY_LOUD,"Yb"); + TI_DBG3(("ossaLocalPhyControlCB: start phyID %d\n", phyId)); + TI_DBG3(("ossaLocalPhyControlCB: phyOperation %d status 0x%x\n", phyOperation, status)); + switch (phyOperation) + { + case AGSA_PHY_LINK_RESET: /* fall through */ + case AGSA_PHY_HARD_RESET: + if (phyOperation == AGSA_PHY_LINK_RESET) + { + TI_DBG1(("ossaLocalPhyControlCB: AGSA_PHY_LINK_RESET, status 0x%x\n", status)); + } + else + { + TI_DBG1(("ossaLocalPhyControlCB: AGSA_PHY_HARD_RESET, status 0x%x\n", status)); + } +#ifdef INITIATOR_DRIVER + if (agContext != agNULL) + { + currentTaskTag = (tiIORequest_t *)agContext->osData; + if (status == OSSA_SUCCESS) + { + if (currentTaskTag != agNULL) + { + TI_DBG2(("ossaLocalPhyControlCB: callback to OS layer with success\n")); + TargetDeviceData = (tdsaDeviceData_t *)currentTaskTag->tdData; + pSatDevData = (satDeviceData_t *)&(TargetDeviceData->satDevData); + agDevHandle = TargetDeviceData->agDevHandle; + TI_DBG2(("ossaLocalPhyControlCB: satPendingIO %d satNCQMaxIO %d\n", pSatDevData->satPendingIO, pSatDevData->satNCQMaxIO )); + TI_DBG2(("ossaLocalPhyControlCB: satPendingNCQIO %d satPendingNONNCQIO %d\n", pSatDevData->satPendingNCQIO, pSatDevData->satPendingNONNCQIO)); + pSatDevData->satDriveState = SAT_DEV_STATE_NORMAL; + + if (TargetDeviceData->TRflag == agTRUE) + { + saSetDeviceState(agRoot, agNULL, tdsaRotateQnumber(tiRoot, TargetDeviceData), agDevHandle, SA_DS_OPERATIONAL); + TargetDeviceData->TRflag = agFALSE; + ostiInitiatorEvent(tiRoot, + TargetDeviceData->tdPortContext->tiPortalContext, + &(TargetDeviceData->tiDeviceHandle), + tiIntrEventTypeTransportRecovery, + tiRecOK, + agNULL + ); + } + else + { + agDevHandle = TargetDeviceData->agDevHandle; + if (agDevHandle == agNULL) + { + TI_DBG1(("ossaLocalPhyControlCB: wrong, agDevHandle is NULL\n")); + } + /* move this to OSSA_HW_EVENT_PORT_RESET_COMPLETE in ossaHwCB() */ + agContextDevice = &(TargetDeviceData->agDeviceResetContext); + agContextDevice->osData = currentTaskTag; + +#ifdef REMOVED + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMOK, + currentTaskTag ); +#endif + } + } + } + else + { + if (currentTaskTag != agNULL) + { + TI_DBG1(("ossaLocalPhyControlCB: callback to OS layer with failure\n")); + TargetDeviceData = (tdsaDeviceData_t *)currentTaskTag->tdData; + pSatDevData = (satDeviceData_t *)&(TargetDeviceData->satDevData); + TI_DBG1(("ossaLocalPhyControlCB: satPendingIO %d satNCQMaxIO %d\n", pSatDevData->satPendingIO, pSatDevData->satNCQMaxIO )); + TI_DBG1(("ossaLocalPhyControlCB: satPendingNCQIO %d satPendingNONNCQIO %d\n", pSatDevData->satPendingNCQIO, pSatDevData->satPendingNONNCQIO)); + if (TargetDeviceData->TRflag == agTRUE) + { + TargetDeviceData->TRflag = agFALSE; + ostiInitiatorEvent(tiRoot, + TargetDeviceData->tdPortContext->tiPortalContext, + &(TargetDeviceData->tiDeviceHandle), + tiIntrEventTypeTransportRecovery, + tiRecFailed , + agNULL + ); + } + else + { + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMFailed, + currentTaskTag ); + } + } + } + } +#endif + break; +#ifdef REMOVED + case AGSA_PHY_GET_ERROR_COUNTS: + + TI_DBG2(("ossaLocalPhyControlCB: AGSA_PHY_GET_ERROR_COUNTS, status 0x%x\n", status)); + if(parm !=agNULL ) + { + agPhyErrCounters = (agsaPhyErrCounters_t *)parm; + TI_DBG2(("ossaLocalPhyControlCB: invalidDword %d\n", agPhyErrCounters->invalidDword)); + TI_DBG2(("ossaLocalPhyControlCB: runningDisparityError %d\n", agPhyErrCounters->runningDisparityError)); + TI_DBG2(("ossaLocalPhyControlCB: lostOfDwordSynch %d\n", agPhyErrCounters->lossOfDwordSynch)); + TI_DBG2(("ossaLocalPhyControlCB: phyResetProblem %d\n", agPhyErrCounters->phyResetProblem)); + TI_DBG2(("ossaLocalPhyControlCB: elasticityBufferOverflow %d\n", agPhyErrCounters->elasticityBufferOverflow)); + TI_DBG2(("ossaLocalPhyControlCB: receivedErrorPrimitive %d\n", agPhyErrCounters->receivedErrorPrimitive)); + } + break; + case AGSA_PHY_CLEAR_ERROR_COUNTS: + TI_DBG2(("ossaLocalPhyControlCB: AGSA_PHY_CLEAR_ERROR_COUNTS, status 0x%x\n", status)); + break; +#endif + case AGSA_PHY_NOTIFY_ENABLE_SPINUP: + TI_DBG2(("ossaLocalPhyControlCB: AGSA_PHY_NOTIFY_ENABLE_SPINUP, status 0x%x\n", status)); + break; + case AGSA_PHY_BROADCAST_ASYNCH_EVENT: + TI_DBG2(("ossaLocalPhyControlCB: AGSA_PHY_BROADCAST_ASYNCH_EVENT, status 0x%x\n", status)); + if (tIsSPC12SATA(agRoot)) + { + TI_DBG1(("ossaLocalPhyControlCB: BROADCAST_ASYNCH_EVENT received for SATA Controller\n")); + break; + } + break; + case AGSA_PHY_COMINIT_OOB : + TI_DBG2(("ossaLocalPhyControlCB: AGSA_PHY_COMINIT_OOB, status 0x%x\n", status)); + break; + default: + TI_DBG1(("ossaLocalPhyControlCB: UNKNOWN default case. phyOperation %d status 0x%x\n", phyOperation, status)); + break; + } + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Yb"); + return; +} + +GLOBAL void ossaGetPhyProfileCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + bit32 ppc, + bit32 phyID, + void *parm ) +{ + + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; +#ifdef CCFLAGS_PHYCONTROL_COUNTS + agsaPhyAnalogSettingsPage_t *analog; +#endif /* CCFLAGS_PHYCONTROL_COUNTS */ + tdPhyCount_t *PhyBlob = agNULL; + + agsaPhyBWCountersPage_t *agBWCounters; + agsaPhyErrCountersPage_t *agPhyErrCounters; + TI_DBG1(("ossaGetPhyProfileCB: agContext %p parm %p\n", agContext, parm)); +/* + if( tdsaAllShared->tdFWControlEx.inProgress ) + { + tdsaAllShared->tdFWControlEx.inProgress = 0; + PhyBlob = (tdPhyCount_t *)tdsaAllShared->tdFWControlEx.usrAddr; + } +*/ + switch(ppc) + { + case AGSA_SAS_PHY_BW_COUNTERS_PAGE: + TI_DBG1(("ossaGetPhyProfileCB: AGSA_SAS_PHY_BW_COUNTERS_PAGE, status 0x%x phyID %d\n", status, phyID)); + if(parm !=agNULL ) + { + agBWCounters = (agsaPhyBWCountersPage_t *)parm; + TI_DBG1(("ossaGetPhyProfileCB: RX %d TX %d\n", agBWCounters->RXBWCounter,agBWCounters->TXBWCounter)); + if(PhyBlob !=agNULL ) + { + PhyBlob->InvalidDword = 0; + PhyBlob->runningDisparityError = 0; + PhyBlob->codeViolation = 0; + PhyBlob->phyResetProblem = 0; + PhyBlob->inboundCRCError = 0; + PhyBlob->BW_rx = agBWCounters->RXBWCounter; + PhyBlob->BW_tx = agBWCounters->TXBWCounter; + } + + } + break; + case AGSA_SAS_PHY_ERR_COUNTERS_PAGE: + if( tdsaAllShared->tdFWControlEx.inProgress ) + { + tdsaAllShared->tdFWControlEx.inProgress = 0; + PhyBlob = (tdPhyCount_t *)tdsaAllShared->tdFWControlEx.usrAddr; + } + TI_DBG1(("ossaGetPhyProfileCB: AGSA_SAS_PHY_ERR_COUNTERS_PAGE, status 0x%x phyID %d\n", status, phyID)); + if(parm !=agNULL ) + { + agPhyErrCounters = (agsaPhyErrCountersPage_t *)parm; + if(PhyBlob !=agNULL ) + { + + PhyBlob->InvalidDword = agPhyErrCounters->invalidDword; + PhyBlob->runningDisparityError = agPhyErrCounters->runningDisparityError; + PhyBlob->LossOfSyncDW = agPhyErrCounters->lossOfDwordSynch; + PhyBlob->codeViolation = agPhyErrCounters->codeViolation; + PhyBlob->phyResetProblem = agPhyErrCounters->phyResetProblem; + PhyBlob->inboundCRCError = agPhyErrCounters->inboundCRCError; + PhyBlob->BW_rx = 0; + PhyBlob->BW_tx = 0; + + TI_DBG2(("ossaGetPhyProfileCB: invalidDword %d\n", agPhyErrCounters->invalidDword)); + TI_DBG2(("ossaGetPhyProfileCB: runningDisparityError %d\n", agPhyErrCounters->runningDisparityError)); + TI_DBG2(("ossaGetPhyProfileCB: lostOfDwordSynch %d\n", agPhyErrCounters->lossOfDwordSynch)); + TI_DBG2(("ossaGetPhyProfileCB: phyResetProblem %d\n", agPhyErrCounters->phyResetProblem)); + TI_DBG2(("ossaGetPhyProfileCB: inboundCRCError %d\n", agPhyErrCounters->inboundCRCError)); + } + } + break; + case AGSA_SAS_PHY_ERR_COUNTERS_CLR_PAGE: + TI_DBG1(("ossaGetPhyProfileCB: AGSA_SAS_PHY_ERR_COUNTERS_CLR_PAGE status 0x%x phyID %d\n", status, phyID)); + break; + case AGSA_SAS_PHY_ANALOG_SETTINGS_PAGE: + TI_DBG1(("ossaGetPhyProfileCB:AGSA_SAS_PHY_ANALOG_SETTINGS_PAGE status 0x%x phyID %d\n", status, phyID)); +#ifdef CCFLAGS_PHYCONTROL_COUNTS + if(parm !=agNULL ) + { + analog = (agsaPhyAnalogSettingsPage_t *)parm; + TI_DBG1(("ossaGetPhyProfileCB: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", + analog->Dword0, analog->Dword1, analog->Dword2, analog->Dword3, analog->Dword4, + analog->Dword5, analog->Dword6, analog->Dword7, analog->Dword8, analog->Dword9)); + tdsaAllShared->analog[phyID].spaRegister0 = analog->Dword0; + tdsaAllShared->analog[phyID].spaRegister1 = analog->Dword1; + tdsaAllShared->analog[phyID].spaRegister2 = analog->Dword2; + tdsaAllShared->analog[phyID].spaRegister3 = analog->Dword3; + tdsaAllShared->analog[phyID].spaRegister4 = analog->Dword4; + saSetPhyProfile( agRoot,agContext,tdsaRotateQnumber(tiRoot, agNULL), AGSA_SAS_PHY_ANALOG_SETTINGS_PAGE,sizeof(agsaPhyAnalogSetupRegisters_t),&tdsaAllShared->analog[phyID],phyID); + } +#endif /* CCFLAGS_PHYCONTROL_COUNTS */ + break; + case AGSA_SAS_PHY_OPEN_REJECT_RETRY_BACKOFF_THRESHOLD_PAGE: + { + TI_DBG1(("ossaGetPhyProfileCB:AGSA_SAS_PHY_OPEN_REJECT_RETRY_BACKOFF_THRESHOLD_PAGE status 0x%x phyID %d\n", status, phyID)); + if( parm !=agNULL ) + { +#ifdef TD_DEBUG_ENABLE + agsaSASPhyOpenRejectRetryBackOffThresholdPage_t *Backoff = + (agsaSASPhyOpenRejectRetryBackOffThresholdPage_t *)parm; +#endif + TI_DBG2(("ossaGetPhyProfileCB: DW0 0x%X DW1 0x%X DW2 0x%X DW3 0x%X\n", + Backoff->Dword0,Backoff->Dword1, + Backoff->Dword2,Backoff->Dword3)); + } + break; + } + + case AGSA_SAS_PHY_GENERAL_STATUS_PAGE: + { + agsaSASPhyGeneralStatusPage_t * GenStatus = NULL; + + TI_DBG1(("ossaGetPhyProfileCB: AGSA_SAS_PHY_GENERAL_STATUS_PAGE status 0x%x phyID %d\n", + status, phyID)); + if( parm !=agNULL ) + { + GenStatus= + (agsaSASPhyGeneralStatusPage_t *)parm; + TI_DBG2(("ossaGetPhyProfileCB: " + "AGSA_SAS_PHY_GENERAL_STATUS_PAGE status %d DW0 0x%x DW1 0x%x\n", + status, GenStatus->Dword0, GenStatus->Dword1)); + } + ostiGetPhyGeneralStatusRsp(tiRoot, GenStatus, phyID); +// break; + return ; + } + + default: + TI_DBG1(("ossaGetPhyProfileCB: UNKNOWN default case. phyOperation %d status 0x%x\n", ppc, status)); + break; + + } + + ostiGetPhyProfileIOCTLRsp(tiRoot, status); + +} + + +GLOBAL void ossaSetPhyProfileCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + bit32 ppc, + bit32 phyID, + void *parm ) +{ + TI_DBG1(("ossaSetPhyProfileCB:agContext %p status 0x%x ppc %d phyID %d parm %p\n",agContext, status, ppc, phyID,parm)); +} + + +/*****************************************************************************/ +/*! \brief ossaGetDeviceHandlesCB + * + * + * Purpose: This routine is called by lower layer to corresponding to + * saGetDeviceHandles() + * + * \param agRoot: Pointer to chip/driver Instance. + * \param agContext: Context of the get device handle request originally passed into + * saGetDeviceHandles(). + * \param agPortContext:Pointer to this instance of a port context + * \param agDev: Array containing pointers to the device handles + + * \param validDevs Number of valid device handles + * + * + * \return None. + * + * \note - The scope is shared target and initiator. + * For details, refer to SAS/SATA Low-Level API Specification + */ +/*****************************************************************************/ +osGLOBAL void ossaGetDeviceHandlesCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaPortContext_t *agPortContext, + agsaDevHandle_t *agDev[], + bit32 validDevs + ) +{ + TI_DBG2(("ossaGetDeviceHandlesCB: start\n")); + TI_DBG2(("ossaGetDeviceHandlesCB: validDevs %d\n", validDevs)); + smTraceFuncEnter(hpDBG_VERY_LOUD,"Yc"); +#ifdef TO_DO + for (i = 0 ; i < validDevs ; i++) + { + agDev[i]; + } +#endif + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Yc"); + return; +} + +/*****************************************************************************/ +/*! \brief ossaGetDeviceInfoCB + * + * + * Purpose: This routine is called by lower layer to corresponding to + * saGetDeviceInfo() + * + * \param agRoot: Pointer to chip/driver Instance. + * \param agDevHandle: Handle of the device + * \param status: status + * \param agInfo: Pointer to the structure that describes device information + * + * + * \return None. + * + * \note - The scope is shared target and initiator. + * For details, refer to SAS/SATA Low-Level API Specification + */ +/*****************************************************************************/ +osGLOBAL void ossaGetDeviceInfoCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaDevHandle_t *agDevHandle, + bit32 status, + void *agInfo + ) +{ + +#ifdef TD_DEBUG_ENABLE + agsaDeviceInfo_t *agDeviceInfo; + agsaSASDeviceInfo_t *agSASDeviceInfo; + agsaSATADeviceInfo_t *agSATADeviceInfo; +#endif + smTraceFuncEnter(hpDBG_VERY_LOUD,"Yd"); + + TI_DBG1(("ossaGetDeviceInfoCB: start agContext %p\n",agContext)); + switch (status) + { + case OSSA_DEV_INFO_INVALID_HANDLE: + TI_DBG1(("ossaGetDeviceInfoCB: OSSA_DEV_INFO_INVALID_HANDLE\n")); + /*ostiGetDeviceInfoIOCTLRsp(tiRoot, status, agNULL);*/ + break; + case OSSA_DEV_INFO_NO_EXTENDED_INFO: +#ifdef TD_DEBUG_ENABLE + agDeviceInfo = (agsaDeviceInfo_t *)agInfo; +#endif + TI_DBG1(("ossaGetDeviceInfoCB: OSSA_DEV_INFO_NO_EXTENDED_INFO\n")); + TI_DBG1(("ossaGetDeviceInfoCB: sasAddressHi 0x%08x\n", SA_DEVINFO_GET_SAS_ADDRESSHI(agDeviceInfo))); + TI_DBG1(("ossaGetDeviceInfoCB: sasAddressLo 0x%08x\n", SA_DEVINFO_GET_SAS_ADDRESSLO(agDeviceInfo))); + TI_DBG1(("ossaGetDeviceInfoCB: devType_S_Rate 0x%08x\n", agDeviceInfo->devType_S_Rate)); + TI_DBG1(("ossaGetDeviceInfoCB: firstBurstSize 0x%08x\n", agDeviceInfo->firstBurstSize)); + + /*ostiPortEvent (tiRoot, tiGetDevInfo, tiSuccess,(void *)agContext );*/ + /*ostiGetDeviceInfoIOCTLRsp(tiRoot, status, agDeviceInfo);*/ + break; + case OSSA_DEV_INFO_SAS_EXTENDED_INFO: +#ifdef TD_DEBUG_ENABLE + agSASDeviceInfo = (agsaSASDeviceInfo_t *)agInfo; +#endif + TI_DBG2(("ossaGetDeviceInfoCB: OSSA_DEV_INFO_SAS_EXTENDED_INFO\n")); + TI_DBG2(("ossaGetDeviceInfoCB: sasAddressHi 0x%08x\n", SA_DEVINFO_GET_SAS_ADDRESSHI(&agSASDeviceInfo->commonDevInfo))); + TI_DBG2(("ossaGetDeviceInfoCB: sasAddressLo 0x%08x\n", SA_DEVINFO_GET_SAS_ADDRESSLO(&agSASDeviceInfo->commonDevInfo))); + TI_DBG2(("ossaGetDeviceInfoCB: initiator_ssp_stp_smp %d\n", agSASDeviceInfo->initiator_ssp_stp_smp)); + TI_DBG2(("ossaGetDeviceInfoCB: target_ssp_stp_smp %d\n", agSASDeviceInfo->target_ssp_stp_smp)); + TI_DBG2(("ossaGetDeviceInfoCB: numOfPhys %d\n", agSASDeviceInfo->numOfPhys)); + TI_DBG2(("ossaGetDeviceInfoCB: phyIdentifier %d\n", agSASDeviceInfo->phyIdentifier)); + + break; + case OSSA_DEV_INFO_SATA_EXTENDED_INFO: +#ifdef TD_DEBUG_ENABLE + agSATADeviceInfo = (agsaSATADeviceInfo_t *)agInfo; +#endif + TI_DBG2(("ossaGetDeviceInfoCB: OSSA_DEV_INFO_SATA_EXTENDED_INFO\n")); + TI_DBG2(("ossaGetDeviceInfoCB: sasAddressHi 0x%08x\n", SA_DEVINFO_GET_SAS_ADDRESSHI(&agSATADeviceInfo->commonDevInfo))); + TI_DBG2(("ossaGetDeviceInfoCB: sasAddressLo 0x%08x\n", SA_DEVINFO_GET_SAS_ADDRESSLO(&agSATADeviceInfo->commonDevInfo))); + TI_DBG2(("ossaGetDeviceInfoCB: connection %d\n", agSATADeviceInfo->connection)); + TI_DBG2(("ossaGetDeviceInfoCB: portMultiplierField %d\n", agSATADeviceInfo->portMultiplierField)); + TI_DBG2(("ossaGetDeviceInfoCB: stpPhyIdentifier %d\n", agSATADeviceInfo->stpPhyIdentifier)); +#ifdef TD_DEBUG_ENABLE + tdhexdump("ossaGetDeviceInfoCB: signature", (bit8 *)agSATADeviceInfo->signature, 8); +#endif + break; + default: + TI_DBG2(("ossaGetDeviceInfoCB: error default case, status is %d\n", status)); + break; + } + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Yd"); + return; +} + +/*****************************************************************************/ +/*! \brief ossaDeviceRegistrationCB + * + * + * Purpose: This routine is called by lower layer to corresponding to + * saRegisterNewDevice() + * + * \param agRoot: Pointer to chip/driver Instance. + * \param agContext: Context of the get device handle request originally + * passed into saRegisterNewDevice(). + * \param status: status + * \param agDevHandle: Pointer to the assigned device handle for the + * registered device. + * + * + * \return None. + * + */ +/*****************************************************************************/ +osGLOBAL void ossaDeviceRegistrationCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + agsaDevHandle_t *agDevHandle, + bit32 deviceID + ) +{ +#ifdef INITIATOR_DRIVER + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + bit32 Indenom = tdsaAllShared->QueueConfig.numInboundQueues; + bit32 Outdenom = tdsaAllShared->QueueConfig.numOutboundQueues; + tdsaDeviceData_t *oneDeviceData = (tdsaDeviceData_t *)agContext->osData; + tdsaPortContext_t *onePortContext = oneDeviceData->tdPortContext; + tiPortalContext_t *tiPortalContext = onePortContext->tiPortalContext; +#ifdef FDS_DM + dmRoot_t *dmRoot = &(tdsaAllShared->dmRoot); + dmPortContext_t *dmPortContext = &(onePortContext->dmPortContext); + dmDeviceInfo_t dmDeviceInfo; + bit32 DMstatus = DM_RC_FAILURE; + bit16 ext = 0; + bit32 expanderType = 1; +#endif + +#if defined(FDS_DM) && !defined(FDS_SM) + bit32 IDstatus; +#endif + +#ifdef FDS_SM + smRoot_t *smRoot = &(tdsaAllShared->smRoot); + bit32 SMstatus = SM_RC_FAILURE; +#endif + smTraceFuncEnter(hpDBG_VERY_LOUD,"Ye"); + TI_DBG3(("ossaDeviceRegistrationCB: start status 0x%x\n",status)); + TI_DBG3(("ossaDeviceRegistrationCB: device AddrHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG3(("ossaDeviceRegistrationCB: device AddrLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + TI_DBG3(("ossaDeviceRegistrationCB: did 0x%x\n", oneDeviceData->id)); + TI_DBG3(("ossaDeviceRegistrationCB: deviceID 0x%x\n", deviceID)); + TI_DBG3(("ossaDeviceRegistrationCB: agDevHandle %p %p %p\n",agDevHandle,agDevHandle->osData,agDevHandle->sdkData )); + + /* transient period caused by tdssReportRemovals(), device was in the middle + of registration but port is invalidated + */ + if (oneDeviceData->valid == agFALSE && oneDeviceData->valid2 == agFALSE + && oneDeviceData->DeviceType == TD_DEFAULT_DEVICE) + { + if (status == OSSA_SUCCESS) + { + TI_DBG2(("ossaDeviceRegistrationCB: transient, calling saDeregisterDeviceHandle, did %d\n", oneDeviceData->id)); + oneDeviceData->agDevHandle = agDevHandle; + agDevHandle->osData = oneDeviceData; + if (DEVICE_IS_SATA_DEVICE(oneDeviceData) || DEVICE_IS_STP_TARGET(oneDeviceData)) + { + if (oneDeviceData->satDevData.IDDeviceValid == agFALSE) + { + saDeregisterDeviceHandle(agRoot, agNULL, oneDeviceData->agDevHandle, 0); + } + else + { + saDeregisterDeviceHandle(agRoot, agNULL, oneDeviceData->agDevHandle, tdsaRotateQnumber(tiRoot, oneDeviceData)); + } + } + else + { + saDeregisterDeviceHandle(agRoot, agNULL, oneDeviceData->agDevHandle, tdsaRotateQnumber(tiRoot, oneDeviceData)); + } + } + else if (status == OSSA_FAILURE_PORT_NOT_VALID_STATE || status == OSSA_ERR_PORT_STATE_NOT_VALID) + { + /* do nothing */ + TI_DBG2(("ossaDeviceRegistrationCB: transient, do nothing did %d\n", oneDeviceData->id)); + } + return; + } + + if (agDevHandle == agNULL) + { + TI_DBG3(("ossaDeviceRegistrationCB: agDevHandle is NULL\n")); + } + else + { + TI_DBG3(("ossaDeviceRegistrationCB: agDevHandle is NOT NULL\n")); + } + + switch (status) + { + case OSSA_SUCCESS: + TI_DBG3(("ossaDeviceRegistrationCB: success\n")); + TI_DBG2(("ossaDeviceRegistrationCB: Success did %d FW did 0x%x\n", oneDeviceData->id, deviceID)); + TI_DBG2(("ossaDeviceRegistrationCB: Success pid %d\n", onePortContext->id)); + if (agDevHandle == agNULL) + { + TI_DBG1(("ossaDeviceRegistrationCB: agDevHandle is NULL, wrong!\n")); + return; + } + oneDeviceData->agDevHandle = agDevHandle; + agDevHandle->osData = oneDeviceData; + oneDeviceData->registered = agTRUE; + oneDeviceData->InQID = oneDeviceData->id % Indenom; + oneDeviceData->OutQID = oneDeviceData->id % Outdenom; + onePortContext->RegisteredDevNums++; + + TI_DBG3(("ossaDeviceRegistrationCB: direct %d STP target %d target_ssp_stp_smp %d\n", oneDeviceData->directlyAttached, DEVICE_IS_STP_TARGET(oneDeviceData), oneDeviceData->target_ssp_stp_smp)); + TI_DBG3(("ossaDeviceRegistrationCB: pid %d registeredNumDevice %d\n", onePortContext->id, onePortContext->RegisteredDevNums)); + TI_DBG3(("ossaDeviceRegistrationCB: pid %d Count %d\n", onePortContext->id, onePortContext->Count)); + +#ifdef FDS_DM + /* if device is an expander, register it to DM */ + if (onePortContext->valid == agTRUE) + { + if (DEVICE_IS_SMP_TARGET(oneDeviceData)) + { + TI_DBG1(("ossaDeviceRegistrationCB: calling dmRegisterDevice\n")); + TI_DBG1(("ossaDeviceRegistrationCB: device AddrHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG1(("ossaDeviceRegistrationCB: device AddrLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + /* set up dmDeviceInfo */ + osti_memset(&dmDeviceInfo, 0, sizeof(dmDeviceInfo_t)); + DEVINFO_PUT_SAS_ADDRESSLO(&dmDeviceInfo, oneDeviceData->SASAddressID.sasAddressLo); + DEVINFO_PUT_SAS_ADDRESSHI(&dmDeviceInfo, oneDeviceData->SASAddressID.sasAddressHi); + dmDeviceInfo.initiator_ssp_stp_smp = oneDeviceData->initiator_ssp_stp_smp; + dmDeviceInfo.target_ssp_stp_smp = oneDeviceData->target_ssp_stp_smp; + dmDeviceInfo.devType_S_Rate = oneDeviceData->agDeviceInfo.devType_S_Rate; + if (oneDeviceData->directlyAttached == agTRUE) + { + /* setting SMP bit */ + ext = (bit16)(ext | 0x100); + expanderType = SA_IDFRM_GET_DEVICETTYPE(&onePortContext->sasIDframe); + ext = (bit16)( ext | (expanderType << 9)); + /* setting MCN field to 0xF */ + ext = (bit16)(ext | (bit16)(0xF << 11)); + TI_DBG1(("ossaDeviceRegistrationCB: directlyAttached ext 0x%x\n", ext)); + dmDeviceInfo.ext = ext; + } + DMstatus = dmRegisterDevice(dmRoot, dmPortContext, &dmDeviceInfo, oneDeviceData->agDevHandle); + if (DMstatus != DM_RC_SUCCESS) + { + TI_DBG1(("ossaDeviceRegistrationCB: dmRegisterDevice failed!!! 0x%x\n", DMstatus)); + } + } + } +#endif /* FDS_DM */ +#ifdef FDS_SM + /* if device is SATA, register it to SM */ + if (onePortContext->valid == agTRUE) + { + if (DEVICE_IS_SATA_DEVICE(oneDeviceData) || DEVICE_IS_STP_TARGET(oneDeviceData)) + { + TI_DBG1(("ossaDeviceRegistrationCB: calling smRegisterDevice\n")); + if (oneDeviceData->directlyAttached == agTRUE) + { + SMstatus = smRegisterDevice(smRoot, + agDevHandle, + &(oneDeviceData->smDeviceHandle), + agNULL, + (bit32)oneDeviceData->phyID, + oneDeviceData->satDevData.satDeviceType); + } + else + { + if (oneDeviceData->ExpDevice == agNULL) + { + TI_DBG1(("ossaDeviceRegistrationCB: oneDeviceData->ExpDevice NULL!!!\n")); + return; + } + if (oneDeviceData->ExpDevice->agDevHandle == agNULL) + { + TI_DBG1(("ossaDeviceRegistrationCB: oneDeviceData->ExpDevice->agDevHandle NULL!!!\n")); + } + SMstatus = smRegisterDevice(smRoot, + agDevHandle, + &(oneDeviceData->smDeviceHandle), + oneDeviceData->ExpDevice->agDevHandle, + (bit32)oneDeviceData->phyID, + oneDeviceData->satDevData.satDeviceType); + } + if (SMstatus != SM_RC_SUCCESS) + { + TI_DBG1(("ossaDeviceRegistrationCB: smRegisterDevice failed!!! 0x%x\n", DMstatus)); + } + } + } +#endif /* FDS_SM */ + /* special case for directly attached targets */ + if (oneDeviceData->directlyAttached == agTRUE) + { + TI_DBG3(("ossaDeviceRegistrationCB: directly attached did %d\n", oneDeviceData->id)); + if (oneDeviceData->DeviceType == TD_SAS_DEVICE) + { + TI_DBG3(("ossaDeviceRegistrationCB: SAS target\n")); + if (onePortContext->valid == agTRUE) + { + if (onePortContext->PortRecoverPhyID != 0xFF) + { + oneDeviceData->phyID = (bit8)onePortContext->PortRecoverPhyID; + onePortContext->PortRecoverPhyID = 0xFF; + TI_DBG3(("ossaDeviceRegistrationCB: PortRecoverPhyID %d\n", oneDeviceData->phyID)); + } + /* link up and discovery ready event */ + if (onePortContext->DiscoveryRdyGiven == agFALSE) + { + TI_DBG2(("ossaDeviceRegistrationCB: link up and discovery ready\n")); + TI_DBG3(("ossaDeviceRegistrationCB: phyID %d pid %d\n", oneDeviceData->phyID, onePortContext->id)); + TI_DBG3(("ossaDeviceRegistrationCB: tiPortalContext %p\n", tdsaAllShared->Ports[oneDeviceData->phyID].tiPortalContext)); + TI_DBG3(("ossaDeviceRegistrationCB: onePortContext->tiPortalContext %p\n", onePortContext->tiPortalContext)); + onePortContext->DiscoveryRdyGiven = agTRUE; + if (onePortContext->DiscoveryState != ITD_DSTATE_NOT_STARTED) + { + TI_DBG1(("ossaDeviceRegistrationCB: wrong discovery state 0x%x\n", onePortContext->DiscoveryState)); + } + /* notifying link up */ + ostiPortEvent ( + tiRoot, + tiPortLinkUp, + tiSuccess, + (void *)onePortContext->tiPortalContext + ); +#ifdef INITIATOR_DRIVER + /* triggers discovery */ + ostiPortEvent( + tiRoot, + tiPortDiscoveryReady, + tiSuccess, + (void *)onePortContext->tiPortalContext + ); +#endif + } + } + else + { + TI_DBG2(("ossaDeviceRegistrationCB: abort call\n")); + /* abort all followed by deregistration of sas target */ + tdsaAbortAll(tiRoot, agRoot, oneDeviceData); + } + } + else + { + TI_DBG2(("ossaDeviceRegistrationCB: SATA target\n")); + if (onePortContext->valid == agTRUE) + { + if (oneDeviceData->satDevData.IDDeviceValid == agFALSE) + { +#ifdef FDS_SM + /* send identify device data */ + tdIDStart(tiRoot, agRoot, smRoot, oneDeviceData, onePortContext); + +#else + /* send identify device data */ + tdssSubAddSATAToSharedcontext(tiRoot, oneDeviceData); +#endif + } + } + else + { + TI_DBG2(("ossaDeviceRegistrationCB: abort call\n")); + /* abort all followed by deregistration of sas target */ + tdsaAbortAll(tiRoot, agRoot, oneDeviceData); + } + } + } + else /* behind the expander */ + { +#if defined(FDS_DM) && defined(FDS_SM) + /* send ID to SATA targets + needs go allocate tdIORequestBody_t for smIORequest + */ + + if ( (DEVICE_IS_SATA_DEVICE(oneDeviceData) || DEVICE_IS_STP_TARGET(oneDeviceData)) + && + oneDeviceData->satDevData.IDDeviceValid == agFALSE) + { + tdIDStart(tiRoot, agRoot, smRoot, oneDeviceData, onePortContext); + } + +#elif defined(FDS_DM) /* worked with DM */ + if ( (DEVICE_IS_SATA_DEVICE(oneDeviceData) || DEVICE_IS_STP_TARGET(oneDeviceData)) + && + oneDeviceData->satDevData.IDDeviceValid == agFALSE) + { + IDstatus = tdsaDiscoveryStartIDDev(tiRoot, + agNULL, + &(oneDeviceData->tiDeviceHandle), + agNULL, + oneDeviceData); + + if (IDstatus != tiSuccess) + { + /* identify device data is not valid */ + TI_DBG1(("ossaDeviceRegistrationCB: fail or busy %d\n", IDstatus)); + oneDeviceData->satDevData.IDDeviceValid = agFALSE; + } + } +#endif + + + } + /* after discovery is finished */ + if (onePortContext->DiscoveryState == ITD_DSTATE_COMPLETED) + { + TI_DBG2(("ossaDeviceRegistrationCB: calling new device arrival\n")); + if (DEVICE_IS_SSP_TARGET(oneDeviceData)) + { + /* in case registration is finished after discovery is finished */ +#ifdef AGTIAPI_CTL + if (tdsaAllShared->SASConnectTimeLimit) + tdsaCTLSet(tiRoot, onePortContext, tiIntrEventTypeDeviceChange, + tiDeviceArrival); + else +#endif + ostiInitiatorEvent( + tiRoot, + tiPortalContext, + agNULL, + tiIntrEventTypeDeviceChange, + tiDeviceArrival, + agNULL + ); + } + else if ( (DEVICE_IS_SATA_DEVICE(oneDeviceData) || DEVICE_IS_STP_TARGET(oneDeviceData)) + && + oneDeviceData->satDevData.IDDeviceValid == agTRUE ) + { + /* in case registration is finished after discovery is finished */ + ostiInitiatorEvent( + tiRoot, + tiPortalContext, + agNULL, + tiIntrEventTypeDeviceChange, + tiDeviceArrival, + agNULL + ); + } + } + break; + case OSSA_FAILURE_OUT_OF_RESOURCE: /* fall through */ + case OSSA_ERR_DEVICE_HANDLE_UNAVAILABLE: + TI_DBG1(("ossaDeviceRegistrationCB: OSSA_FAILURE_OUT_OF_RESOURCE or OSSA_ERR_DEVICE_HANDLE_UNAVAILABLE\n")); + oneDeviceData->registered = agFALSE; + break; + case OSSA_FAILURE_DEVICE_ALREADY_REGISTERED: /* fall through */ + case OSSA_ERR_DEVICE_ALREADY_REGISTERED: + /* do nothing */ + TI_DBG1(("ossaDeviceRegistrationCB: OSSA_FAILURE_DEVICE_ALREADY_REGISTERED or OSSA_ERR_DEVICE_ALREADY_REGISTERED\n")); + break; + case OSSA_FAILURE_INVALID_PHY_ID: /* fall through */ + case OSSA_ERR_PHY_ID_INVALID: + TI_DBG1(("ossaDeviceRegistrationCB: OSSA_FAILURE_INVALID_PHY_ID or OSSA_ERR_PHY_ID_INVALID\n")); + oneDeviceData->registered = agFALSE; + break; + case OSSA_FAILURE_PHY_ID_ALREADY_REGISTERED: /* fall through */ + case OSSA_ERR_PHY_ID_ALREADY_REGISTERED: + /* do nothing */ + TI_DBG1(("ossaDeviceRegistrationCB: OSSA_FAILURE_PHY_ID_ALREADY_REGISTERED or OSSA_ERR_PHY_ID_ALREADY_REGISTERED\n")); + break; + case OSSA_FAILURE_PORT_ID_OUT_OF_RANGE: /* fall through */ + case OSSA_ERR_PORT_INVALID: + TI_DBG1(("ossaDeviceRegistrationCB: OSSA_FAILURE_PORT_ID_OUT_OF_RANGE or OSSA_ERR_PORT_INVALID\n")); + oneDeviceData->registered = agFALSE; + break; + case OSSA_FAILURE_PORT_NOT_VALID_STATE: /* fall through */ + case OSSA_ERR_PORT_STATE_NOT_VALID: + TI_DBG1(("ossaDeviceRegistrationCB: OSSA_FAILURE_PORT_NOT_VALID_STATE or OSSA_ERR_PORT_STATE_NOT_VALID\n")); + TI_DBG2(("ossaDeviceRegistrationCB: did %d pid %d\n", oneDeviceData->id, onePortContext->id)); + oneDeviceData->registered = agFALSE; + /* transient period between link up and link down/port recovery */ + onePortContext->Transient = agTRUE; + if (onePortContext->valid == agTRUE && (oneDeviceData->valid == agTRUE || oneDeviceData->valid2 == agTRUE)) + { + TI_DBG1(("ossaDeviceRegistrationCB: retries regisration\n")); +#ifdef REMOVED + //temp; setting MCN to tdsaAllShared->MCN + oneDeviceData->agDeviceInfo.flag = oneDeviceData->agDeviceInfo.flag | (tdsaAllShared->MCN << 16); + //end temp +#endif + saRegisterNewDevice( /* ossaDeviceRegistrationCB */ + agRoot, + &oneDeviceData->agContext, + 0, + &oneDeviceData->agDeviceInfo, + onePortContext->agPortContext, + 0 + ); + } + else if (oneDeviceData->directlyAttached == agTRUE && DEVICE_IS_SATA_DEVICE(oneDeviceData)) + { + TI_DBG1(("ossaDeviceRegistrationCB: directly attached SATA, put back into free list\n")); + tdsaDeviceDataReInit(tiRoot, oneDeviceData); + tdsaSingleThreadedEnter(tiRoot, TD_DEVICE_LOCK); + TDLIST_ENQUEUE_AT_TAIL(&(oneDeviceData->FreeLink), &(tdsaAllShared->FreeDeviceList)); + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + } + break; + case OSSA_FAILURE_DEVICE_TYPE_NOT_VALID: /* fall through */ + case OSSA_ERR_DEVICE_TYPE_NOT_VALID: + TI_DBG1(("ossaDeviceRegistrationCB: OSSA_FAILURE_DEVICE_TYPE_NOT_VALID or OSSA_ERR_DEVICE_TYPE_NOT_VALID\n")); + oneDeviceData->registered = agFALSE; + break; + default: + TI_DBG1(("ossaDeviceRegistrationCB: wrong. default status is %d\n", status)); + break; + + + } + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Ye"); + return; +#endif +} + +/*****************************************************************************/ +/*! \brief ossaDeregisterDeviceHandleCB + * + * + * Purpose: This routine is called by lower layer to corresponding to + * saDeregisterDeviceHandle() + * + * \param agRoot: Pointer to chip/driver Instance. + * \param agDevHandle: Pointer to the assigned device handle for the + * registered device. + * \param status: status + * + * + * \return None. + * + */ +/*****************************************************************************/ +osGLOBAL void ossaDeregisterDeviceHandleCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaDevHandle_t *agDevHandle, + bit32 status + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdsaDeviceData_t *oneDeviceData = agNULL; + tdsaPortContext_t *onePortContext = agNULL; + agsaEventSource_t *eventSource; + bit32 HwAckSatus; + bit32 PhyID; +#ifdef FDS_DM + dmRoot_t *dmRoot = &(tdsaAllShared->dmRoot); + dmPortContext_t *dmPortContext = agNULL; + dmPortInfo_t dmPortInfo; + bit32 DMstatus = DM_RC_FAILURE; +#endif +#ifdef FDS_SM + smRoot_t *smRoot = &(tdsaAllShared->smRoot); +#endif + + TI_DBG3(("ossaDeregisterDeviceHandleCB: start\n")); + smTraceFuncEnter(hpDBG_VERY_LOUD,"Yf"); + + if (status == OSSA_ERR_DEVICE_HANDLE_INVALID) + { + /* there is no device handle to process */ + TI_DBG2(("ossaDeregisterDeviceHandleCB: OSSA_ERR_DEVICE_HANDLE_INVALID\n")); + return; + } + + oneDeviceData = (tdsaDeviceData_t *)agDevHandle->osData; + onePortContext = oneDeviceData->tdPortContext; +#ifdef FDS_DM + dmPortContext = &(onePortContext->dmPortContext); +#endif + + if (oneDeviceData->valid == agFALSE && oneDeviceData->valid2 == agFALSE && + oneDeviceData->DeviceType == TD_DEFAULT_DEVICE && onePortContext->valid == agTRUE) + { + TI_DBG2(("ossaDeregisterDeviceHandleCB: transient did %d\n", oneDeviceData->id)); + return; + } + + if (onePortContext != agNULL) + { + TI_DBG2(("ossaDeregisterDeviceHandleCB: pid %d registeredNumDevice %d\n", onePortContext->id, onePortContext->RegisteredDevNums)); + } + + switch (status) + { + case OSSA_SUCCESS: + TI_DBG3(("ossaDeregisterDeviceHandleCB: Success\n")); + if (onePortContext == agNULL) + { + TI_DBG1(("ossaDeregisterDeviceHandleCB: onePortContext is NULL, wrong!\n")); + return; + } + /* port is going down */ + if (onePortContext->valid == agFALSE) + { + if (!(oneDeviceData->valid == agFALSE && oneDeviceData->valid2 == agFALSE && oneDeviceData->DeviceType == TD_DEFAULT_DEVICE)) + { + /* remove oneDevice from MainLink */ + TI_DBG2(("ossaDeregisterDeviceHandleCB: delete from MainLink\n")); +#ifdef FDS_SM + if (DEVICE_IS_SATA_DEVICE(oneDeviceData) || DEVICE_IS_STP_TARGET(oneDeviceData)) + { + TI_DBG1(("ossaDeregisterDeviceHandleCB: did %d calling smDeregisterDevice\n", oneDeviceData->id)); + smDeregisterDevice(smRoot, oneDeviceData->agDevHandle, &(oneDeviceData->smDeviceHandle)); + } +#endif + tdsaDeviceDataReInit(tiRoot, oneDeviceData); + osti_memset(&(oneDeviceData->satDevData.satIdentifyData), 0xFF, sizeof(agsaSATAIdentifyData_t)); + + tdsaSingleThreadedEnter(tiRoot, TD_DEVICE_LOCK); + TDLIST_DEQUEUE_THIS(&(oneDeviceData->MainLink)); + TDLIST_ENQUEUE_AT_TAIL(&(oneDeviceData->FreeLink), &(tdsaAllShared->FreeDeviceList)); + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + } + /* for portcontext */ + PhyID = onePortContext->eventPhyID; + TI_DBG3(("ossaDeregisterDeviceHandleCB: PhyID %d\n", PhyID)); + onePortContext->RegisteredDevNums--; + /* + check if valid in tdsaAllShared and the last registered device in a portcontext; + if so, call saHwEventAck() + */ + if (tdsaAllShared->eventSource[PhyID].EventValid == agTRUE && + onePortContext->RegisteredDevNums == 0 && + PhyID != 0xFF + ) + { + TI_DBG2(("ossaDeregisterDeviceHandleCB: calling saHwEventAck\n")); + eventSource = &(tdsaAllShared->eventSource[PhyID].Source); + HwAckSatus = saHwEventAck( + agRoot, + agNULL, /* agContext */ + 0, + eventSource, /* agsaEventSource_t */ + 0, + 0 + ); + if ( HwAckSatus != AGSA_RC_SUCCESS) + { + TI_DBG1(("ossaDeregisterDeviceHandleCB: failing in saHwEventAck; status %d\n", HwAckSatus)); + } + + /* toggle */ + tdsaAllShared->eventSource[PhyID].EventValid = agFALSE; + +#ifdef FDS_DM + if (onePortContext->UseDM == agTRUE) + { + TI_DBG1(("ossaDeregisterDeviceHandleCB: calling dmDestroyPort\n")); + /* setup dmPortInfo */ + PORTINFO_PUT_SAS_REMOTE_ADDRESSLO(&dmPortInfo, onePortContext->sasRemoteAddressLo); + PORTINFO_PUT_SAS_REMOTE_ADDRESSHI(&dmPortInfo, onePortContext->sasRemoteAddressHi); + PORTINFO_PUT_SAS_LOCAL_ADDRESSLO(&dmPortInfo, onePortContext->sasLocalAddressLo); + PORTINFO_PUT_SAS_LOCAL_ADDRESSHI(&dmPortInfo, onePortContext->sasLocalAddressHi); + DMstatus = dmDestroyPort(dmRoot, dmPortContext, &dmPortInfo); + if (DMstatus != DM_RC_SUCCESS) + { + TI_DBG1(("ossaDeregisterDeviceHandleCB: dmDestroyPort failed!!! 0x%x\n", DMstatus)); + } + } +#endif + tdsaPortContextReInit(tiRoot, onePortContext); + /* + put all devices belonging to the onePortContext + back to the free link + */ + + tdsaSingleThreadedEnter(tiRoot, TD_PORT_LOCK); + TDLIST_DEQUEUE_THIS(&(onePortContext->MainLink)); + TDLIST_ENQUEUE_AT_TAIL(&(onePortContext->FreeLink), &(tdsaAllShared->FreePortContextList)); + tdsaSingleThreadedLeave(tiRoot, TD_PORT_LOCK); + } + else if (tdsaAllShared->eventSource[PhyID].EventValid == NO_ACK && + onePortContext->RegisteredDevNums == 0 + ) + { + TI_DBG2(("ossaDeregisterDeviceHandleCB: NO ACK case\n")); +#ifdef FDS_DM + if (onePortContext->UseDM == agTRUE) + { + TI_DBG1(("ossaDeregisterDeviceHandleCB: calling dmDestroyPort\n")); + /* setup dmPortInfo */ + PORTINFO_PUT_SAS_REMOTE_ADDRESSLO(&dmPortInfo, onePortContext->sasRemoteAddressLo); + PORTINFO_PUT_SAS_REMOTE_ADDRESSHI(&dmPortInfo, onePortContext->sasRemoteAddressHi); + PORTINFO_PUT_SAS_LOCAL_ADDRESSLO(&dmPortInfo, onePortContext->sasLocalAddressLo); + PORTINFO_PUT_SAS_LOCAL_ADDRESSHI(&dmPortInfo, onePortContext->sasLocalAddressHi); + DMstatus = dmDestroyPort(dmRoot, dmPortContext, &dmPortInfo); + if (DMstatus != DM_RC_SUCCESS) + { + TI_DBG1(("ossaDeregisterDeviceHandleCB: dmDestroyPort failed!!! 0x%x\n", DMstatus)); + } + } +#endif + tdsaPortContextReInit(tiRoot, onePortContext); + /* + put all devices belonging to the onePortContext + back to the free link + */ + + tdsaSingleThreadedEnter(tiRoot, TD_PORT_LOCK); + TDLIST_DEQUEUE_THIS(&(onePortContext->MainLink)); + TDLIST_ENQUEUE_AT_TAIL(&(onePortContext->FreeLink), &(tdsaAllShared->FreePortContextList)); + tdsaSingleThreadedLeave(tiRoot, TD_PORT_LOCK); + } + else + { + if (PhyID < TD_MAX_NUM_PHYS) + { + TI_DBG3(("ossaDeregisterDeviceHandleCB: pid %d eventvalid %d registeredNumDevice %d\n", onePortContext->id, tdsaAllShared->eventSource[PhyID].EventValid , onePortContext->RegisteredDevNums)); + } + else + { + TI_DBG3(("ossaDeregisterDeviceHandleCB: pid %d registeredNumDevice %d wrong phyid %d\n", onePortContext->id, onePortContext->RegisteredDevNums, PhyID)); + } + } + } + else + { + PhyID = onePortContext->eventPhyID; + TI_DBG3(("ossaDeregisterDeviceHandleCB: PhyID %d\n", PhyID)); + onePortContext->RegisteredDevNums--; +#ifdef FDS_SM + oneDeviceData->satDevData.IDDeviceValid = agFALSE; + if (DEVICE_IS_SATA_DEVICE(oneDeviceData) || DEVICE_IS_STP_TARGET(oneDeviceData)) + { + smDeregisterDevice(smRoot, oneDeviceData->agDevHandle, &(oneDeviceData->smDeviceHandle)); + } +#endif + /* + check if valid in tdsaAllShared and the last registered device in a portcontext; + if so, call saHwEventAck() + */ + if (tdsaAllShared->eventSource[PhyID].EventValid == agTRUE && + onePortContext->RegisteredDevNums == 0 && + PhyID != 0xFF + ) + { + TI_DBG2(("ossaDeregisterDeviceHandleCB: calling saHwEventAck\n")); + eventSource = &(tdsaAllShared->eventSource[PhyID].Source); + HwAckSatus = saHwEventAck( + agRoot, + agNULL, /* agContext */ + 0, + eventSource, /* agsaEventSource_t */ + 0, + 0 + ); + if ( HwAckSatus != AGSA_RC_SUCCESS) + { + TI_DBG1(("ossaDeregisterDeviceHandleCB: failing in saHwEventAck; status %d\n", HwAckSatus)); + } + + /* toggle */ + tdsaAllShared->eventSource[PhyID].EventValid = agFALSE; + } +#ifdef INITIATOR_DRIVER + else if (onePortContext->RegisteredDevNums == 1) + { + TI_DBG1(("ossaDeregisterDeviceHandleCB: all devices have been deregistered except directly attached EXP\n")); + /* qqqqq If broadcast has been seen, call incremental discovery*/ + if (onePortContext->DiscFailNSeenBC == agTRUE) + { + TI_DBG1(("ossaDeregisterDeviceHandleCB: calling dmDiscover, incremental, pid %d\n", onePortContext->id)); + dmDiscover(dmRoot, dmPortContext, DM_DISCOVERY_OPTION_INCREMENTAL_START); + onePortContext->DiscFailNSeenBC = agFALSE; + } + else + { + TI_DBG1(("ossaDeregisterDeviceHandleCB: not calling dmDiscover\n")); + /* qqqqq needs to change discovery state to onePortContext->DMDiscoveryState == dmDiscCompleted + in dmQueryDiscovery + change the discovery state from dmDiscFailed to dmDiscCompleted + */ + dmResetFailedDiscovery(dmRoot, dmPortContext); + + } + } +#endif + else + { + if (PhyID < TD_MAX_NUM_PHYS) + { + TI_DBG3(("ossaDeregisterDeviceHandleCB: pid %d eventvalid %d registeredNumDevice %d\n", onePortContext->id, tdsaAllShared->eventSource[PhyID].EventValid , onePortContext->RegisteredDevNums)); + } + else + { + TI_DBG3(("ossaDeregisterDeviceHandleCB: pid %d registeredNumDevice %d wrong phyid %d\n", onePortContext->id, onePortContext->RegisteredDevNums, PhyID)); + } + } + } + break; + case OSSA_INVALID_HANDLE: + TI_DBG1(("ossaDeregisterDeviceHandleCB: OSSA_INVALID_HANDLE\n")); + break; +#ifdef REMOVED + case OSSA_FAILURE_DEVICE_DIRECT_ATTACH: + TI_DBG1(("ossaDeregisterDeviceHandleCB: OSSA_FAILURE_DEVICE_DIRECT_ATTACH\n")); + break; +#endif + case OSSA_ERR_DEVICE_HANDLE_INVALID: + TI_DBG1(("ossaDeregisterDeviceHandleCB: OSSA_ERR_DEVICE_HANDLE_INVALID\n")); + break; + case OSSA_ERR_DEVICE_BUSY: + TI_DBG1(("ossaDeregisterDeviceHandleCB: OSSA_ERR_DEVICE_BUSY\n")); + break; + default: + TI_DBG1(("ossaDeregisterDeviceHandleCB: unknown status 0x%x\n", status)); + break; + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Yf"); + return; +} + +/*****************************************************************************/ +/*! \brief ossaDeviceHandleRemovedEvent + * + * + * Purpose: This routine is called by lower layer to notify the device removal + * + * + * \param agRoot: Pointer to chip/driver Instance. + * \param agDevHandle: Pointer to the assigned device handle for the + * registered device. + * \param agPortContext:Pointer to this instance of port context. + * + * + * \return None. + * + */ +/*****************************************************************************/ +osGLOBAL void ossaDeviceHandleRemovedEvent ( + agsaRoot_t *agRoot, + agsaDevHandle_t *agDevHandle, + agsaPortContext_t *agPortContext + ) +{ +#ifdef NOT_YET + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; +#endif + tdsaPortContext_t *onePortContext = agNULL; + tdsaDeviceData_t *oneDeviceData = (tdsaDeviceData_t *)agDevHandle->osData; + + smTraceFuncEnter(hpDBG_VERY_LOUD,"Yg"); + TI_DBG2(("ossaDeviceHandleRemovedEvent: start\n")); + if (oneDeviceData == agNULL) + { + TI_DBG1(("ossaDeviceHandleRemovedEvent: Wrong! oneDeviceData is NULL\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Yg"); + return; + } + TI_DBG2(("ossaDeviceHandleRemovedEvent: did %d\n", oneDeviceData->id)); + oneDeviceData->registered = agFALSE; + onePortContext = (tdsaPortContext_t *)agPortContext->osData; + if (onePortContext == agNULL) + { + TI_DBG1(("ossaDeviceHandleRemovedEvent: Wrong! onePortContext is NULL\n")); + smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "Yg"); + return; + } + TI_DBG2(("ossaDeviceHandleRemovedEvent: pid %d\n", onePortContext->id)); + onePortContext->RegisteredDevNums--; +#ifdef NOT_YET + ostiInitiatorEvent( + tiRoot, + onePortContext->tiPortalContext, + agNULL, + tiIntrEventTypeDeviceChange, + tiDeviceRemoval, + agNULL + ); +#endif + + smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "Yg"); + return; +} + +#ifdef SPC_ENABLE_PROFILE +/*****************************************************************************/ +/*! \brief ossaFwProfileCB + * + * + * Purpose: This routine is called by lower layer to corresponding to + * saFwProfile() + * + * \param agRoot: Pointer to chip/driver Instance. + * \param agContext: Context of the operation originally passed + * into saFwProfile() + * \param status: status + * + * + * \return None. + * + */ +/*****************************************************************************/ +osGLOBAL void ossaFwProfileCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + bit32 len) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + + TI_DBG2(("ossaFwProfileCB: start\n")); + + switch (status) + { + case AGSA_RC_SUCCESS: + { + TI_DBG2(("ossaFwProfileCB: SUCCESS\n")); + break; + } + case AGSA_RC_FAILURE: + { + TI_DBG1(("ossaFwProfileCB: FAIL\n")); + break; + } + default: + { + TI_DBG1(("ossaFwProfileCB: !!! default, status %d\n", status)); + break; + } + } + + ostiFWProfileIOCTLRsp(tiRoot, status, len); + return; +} +#endif +/*****************************************************************************/ +/*! \brief ossaFwFlashUpdateCB + * + * + * Purpose: This routine is called by lower layer to corresponding to + * saFwFlashUpdate() + * + * \param agRoot: Pointer to chip/driver Instance. + * \param agContext: Context of the operation originally passed + * into saFwFlashUpdate() + * \param status: status + * + * + * \return None. + * + */ +/*****************************************************************************/ +osGLOBAL void ossaFwFlashUpdateCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + + TI_DBG2(("ossaFwFlashUpdateCB: start\n")); + + smTraceFuncEnter(hpDBG_VERY_LOUD,"Yh"); + switch (status) + { + case OSSA_FLASH_UPDATE_COMPLETE_PENDING_REBOOT: + { + TI_DBG2(("ossaFwFlashUpdateCB: OSSA_FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n")); + break; + } + case OSSA_FLASH_UPDATE_IN_PROGRESS: + { + TI_DBG2(("ossaFwFlashUpdateCB: OSSA_FLASH_UPDATE_IN_PROGRESS\n")); + break; + } + case OSSA_FLASH_UPDATE_HDR_ERR: + { + TI_DBG1(("ossaFwFlashUpdateCB: OSSA_FLASH_UPDATE_HDR_ERR\n")); + break; + } + case OSSA_FLASH_UPDATE_OFFSET_ERR: + { + TI_DBG1(("ossaFwFlashUpdateCB: OSSA_FLASH_UPDATE_OFFSET_ERR\n")); + break; + } + case OSSA_FLASH_UPDATE_CRC_ERR: + { + TI_DBG1(("ossaFwFlashUpdateCB: OSSA_FLASH_UPDATE_CRC_ERR\n")); + break; + } + case OSSA_FLASH_UPDATE_LENGTH_ERR: + { + TI_DBG1(("ossaFwFlashUpdateCB: OSSA_FLASH_UPDATE_LENGTH_ERR\n")); + break; + } + case OSSA_FLASH_UPDATE_HW_ERR: + { + TI_DBG1(("ossaFwFlashUpdateCB: OSSA_FLASH_UPDATE_HW_ERR\n")); + break; + } + case OSSA_FLASH_UPDATE_DNLD_NOT_SUPPORTED: + { + TI_DBG1(("ossaFwFlashUpdateCB: OSSA_FLASH_UPDATE_DNLD_NOT_SUPPORTED\n")); + break; + } + case OSSA_FLASH_UPDATE_DISABLED: + { + TI_DBG1(("ossaFwFlashUpdateCB: OSSA_FLASH_UPDATE_DISABLED\n")); + break; + } + case OSSA_FLASH_FWDNLD_DEVICE_UNSUPPORT: + { + TI_DBG1(("ossaFwFlashUpdateCB: OSSA_FLASH_FWDNLD_DEVICE_UNSUPPORT\n")); + break; + } + case OSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE: + { + TI_DBG1(("ossaFwFlashUpdateCB: OSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE\n")); + break; + } + case OSSA_FLASH_UPDATE_HMAC_ERR: + { + TI_DBG1(("ossaFwFlashUpdateCB: OSSA_FLASH_UPDATE_HMAC_ERR\n")); + break; + } + + default: + { + TI_DBG1(("ossaFwFlashUpdateCB: !!! default, status 0x%X\n", status)); + break; + } + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Yh"); + ostiCOMMgntIOCTLRsp(tiRoot, status); + return; + +} + + +GLOBAL void ossaFlashExtExecuteCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + bit32 command, + agsaFlashExtResponse_t *agFlashExtRsp) +{ + TI_DBG1(("ossaFlashExtExecuteCB: command 0x%X status 0x%X\n",command, status)); + +} + + + +/*****************************************************************************/ +/*! \brief ossaGetNVMDResponseCB + * + * + * Purpose: This routine is called by lower layer to corresponding to + * saGetNVMDCommand() + * + * \param agRoot: Pointer to chip/driver Instance. + * \param agContext: Context of the operation originally passed + * into saGetVPDCommand() + * \param status: status + * \param indirectPayload: The value passed in agsaNVMDData_t when + * calling saGetNVMDCommand() + * \param agInfoLen: the length of VPD information + * \param agFrameHandle: handler of VPD information + * + * + * \return None. + * + */ +/*****************************************************************************/ +osGLOBAL void ossaGetNVMDResponseCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + bit8 indirectPayload, + bit32 agInfoLen, + agsaFrameHandle_t agFrameHandle +) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + TI_DBG2(("ossaGetNVMDResponseCB: start\n")); + TI_DBG2(("ossaGetNVMDResponseCB: agInfoLen %d\n", agInfoLen)); + smTraceFuncEnter(hpDBG_VERY_LOUD,"Yi"); + + if (status == OSSA_SUCCESS) + { + TI_DBG2(("ossaGetNVMDResponseCB: Success status\n")); + if (indirectPayload == 0 && agInfoLen != 0) + { + TI_DBG2(("ossaGetNVMDResponseCB: direct\n")); + tdhexdump("ossaGetNVMDResponseCB", (bit8 *)agFrameHandle, agInfoLen); + } + } + else + { + TI_DBG1(("ossaGetNVMDResponseCB: Status 0x%x\n", status)); + } + + if (indirectPayload == 0) + { + TI_DBG2(("ossaGetNVMDResponseCB: direct\n")); + } + else + { + TI_DBG2(("ossaGetNVMDResponseCB: indirect\n")); + } + + ostiGetNVMDIOCTLRsp(tiRoot, status); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Yi"); + return; +} + + +/*****************************************************************************/ +/*! \brief ossaSetNVMDResponseCB + * + * + * Purpose: This routine is called by lower layer to corresponding to + * saSetNVMDCommand() + * + * \param agRoot: Pointer to chip/driver Instance. + * \param agContext: Context of the operation originally passed + * into saSetVPDCommand() + * \param status: status + * + * + * \return None. + * + */ +/*****************************************************************************/ +osGLOBAL void ossaSetNVMDResponseCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + TI_DBG2(("ossaSetNVMDResponseCB: start\n")); + smTraceFuncEnter(hpDBG_VERY_LOUD,"Yj"); + if (status == OSSA_SUCCESS) + { + TI_DBG2(("ossaSetNVMDResponseCB: success\n")); + } + else + { + TI_DBG1(("ossaSetNVMDResponseCB: fail or undefined staus %d\n", status)); + } + ostiSetNVMDIOCTLRsp(tiRoot, status); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Yj"); + return; +} + + +#ifdef REMOVED +/*****************************************************************************/ +/*! \brief ossaGetVPDResponseCB + * + * + * Purpose: This routine is called by lower layer to corresponding to + * saGetVPDCommand() + * + * \param agRoot: Pointer to chip/driver Instance. + * \param agContext: Context of the operation originally passed + * into saGetVPDCommand() + * \param status: status + * \param agInfoLen: the length of VPD information + * \param agFrameHandle:handler of VPD information + * + * + * \return None. + * + */ +/*****************************************************************************/ +osGLOBAL void ossaGetVPDResponseCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + bit8 indirectMode, + bit32 agInfoLen, + agsaFrameHandle_t agFrameHandle + ) +{ + bit8 VPDData[48]; + + TI_DBG2(("ossaGetVPDResponseCB: start\n")); + + smTraceFuncEnter(hpDBG_VERY_LOUD,"Yk"); + if (status == OSSA_SUCCESS) + { + TI_DBG2(("ossaGetVPDResponseCB: agInfoLen %d\n", agInfoLen)); + osti_memset(VPDData, 0, 48); + /* We can read only in case of Direct */ + saFrameReadBlock(agRoot, agFrameHandle, 0, VPDData, agInfoLen); + tdhexdump("ossaGetVPDResponseCB", (bit8 *)VPDData, agInfoLen); + /* + callback osti.... + */ + } + else + { + TI_DBG1(("ossaGetVPDResponseCB: fail or undefined staus %d\n", status)); + } + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Yk"); + return; +} + + +/*****************************************************************************/ +/*! \brief ossaSetVPDResponseCB + * + * + * Purpose: This routine is called by lower layer to corresponding to + * saSetVPDCommand() + * + * \param agRoot: Pointer to chip/driver Instance. + * \param agContext: Context of the operation originally passed + * into saSetVPDCommand() + * \param status: status + * + * + * \return None. + * + */ +/*****************************************************************************/ +osGLOBAL void ossaSetVPDResponseCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + + TI_DBG2(("ossaSetVPDResponseCB: start\n")); + smTraceFuncEnter(hpDBG_VERY_LOUD,"Yl"); + + if (status == OSSA_SUCCESS) + { + TI_DBG2(("ossaSetVPDResponseCB: success\n")); + ostiCOMMgntVPDSetIOCTLRsp(tiRoot, 0); + /* + callback osti..... + */ + +#ifdef VPD_TESTING + /* temporary to test saSetVPDCommand() and saGetVPDCommand */ + tdsaVPDGet(tiRoot); +#endif + + } + else + { + TI_DBG1(("ossaSetVPDResponseCB: fail or undefined staus %d\n", status)); + } + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Yl"); + return; +} +#endif + +/*****************************************************************************/ +/*! \brief ossaEchoCB + * + * + * Purpose: This routine is called by lower layer to corresponding to + * saEchoCommand() + * + * \param agRoot: Pointer to chip/driver Instance. + * \param agContext: Context of the operation originally passed + * into saEchoCommand() + * \param echoPayload: Pointer to the echo payload + * + * + * \return None. + * + */ +/*****************************************************************************/ +osGLOBAL void ossaEchoCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + void *echoPayload + ) +{ +#ifdef ECHO_TESTING + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit8 payload[56]; +#endif + + TI_DBG2(("ossaEchoCB: start\n")); + smTraceFuncEnter(hpDBG_VERY_LOUD,"Ym"); + + /* dumping received echo payload is 56 bytes */ + tdhexdump("ossaEchoCB: echoPayload", (bit8 *)(echoPayload), 56); + +#ifdef ECHO_TESTING + /* temporary to test saEchoCommand() */ + + /* new echo payload */ + osti_memset(payload,0, sizeof(payload)); + + payload[0] = gEcho; + payload[55] = gEcho; + + TI_DBG2(("ossaEchoCB: gEcho %d\n", gEcho)); + + saEchoCommand(agRoot, agNULL, tdsaRotateQnumber(tiRoot, agNULL), (void *)&payload); + + if (gEcho == 0xFF) + { + gEcho = 0; + } + else + { + gEcho++; + } +#endif + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Ym"); + return; +} + +/*****************************************************************************/ +/*! \brief ossaGpioResponseCB + * + * + * Purpose: This routine is called by lower layer to corresponding to + * saGpioEventSetup(), saGpioPinSetup(), saGpioRead(), or + * saGpioWrite() + * + * \param agRoot: Pointer to chip/driver Instance. + * \param agContext: Context of the operation originally passed + * in. + * \param status: GPIO operation completion status + * \param gpioReadValue: a bit map containing the corresponding + * value for each GPIO pin. + * \param gpioPinSetupInfo: Pointer to agsaGpioPinSetupInfo_t structure + * describing the GPIO pin setup + * \param gpioEventSetupInfo Pointer to agsaGpioEventSetupInfo_t structure + * describing the GPIO event setups + * + * + * \return None. + * + */ +/*****************************************************************************/ +osGLOBAL void ossaGpioResponseCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + bit32 gpioReadValue, + agsaGpioPinSetupInfo_t *gpioPinSetupInfo, + agsaGpioEventSetupInfo_t *gpioEventSetupInfo + ) +{ + TI_DBG2(("ossaGpioResponseCB: start\n")); + smTraceFuncEnter(hpDBG_VERY_LOUD,"Yn"); + if (status == OSSA_SUCCESS) + { + TI_DBG2(("ossaGpioResponseCB: Success\n")); + /* printing gpioReadValue, agsaGpioPinSetupInfo_t and agsaGpioEventSetupInfo_t */ + TI_DBG2(("ossaGpioResponseCB: gpioReadValue 0x%x\n", gpioReadValue)); + TI_DBG2(("ossaGpioResponseCB: PinSetupInfo gpioInputEnabled 0x%x\n", gpioPinSetupInfo->gpioInputEnabled)); + TI_DBG2(("ossaGpioResponseCB: PinSetupInfo gpioTypePart1 0x%x\n", gpioPinSetupInfo->gpioTypePart1)); + TI_DBG2(("ossaGpioResponseCB: PinSetupInfo gpioTypePart2 0x%x\n", gpioPinSetupInfo->gpioTypePart2)); + TI_DBG2(("ossaGpioResponseCB: EventSetupInfo gpioEventLevel 0x%x\n", gpioEventSetupInfo->gpioEventLevel)); + TI_DBG2(("ossaGpioResponseCB: EventSetupInfo gpioEventRisingEdge 0x%x\n", gpioEventSetupInfo->gpioEventRisingEdge)); + TI_DBG2(("ossaGpioResponseCB: EventSetupInfo gpioEventFallingEdge 0x%x\n", gpioEventSetupInfo->gpioEventFallingEdge)); + } + else + { + TI_DBG1(("ossaGpioResponseCB: Failure\n")); + } + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Yn"); + return; +} + +/*****************************************************************************/ +/*! \brief ossaGpioEvent + * + * + * Purpose: This routine is called by lower layer to corresponding to + * saGpioEventSetup(), saGpioPinSetup(), saGpioRead(), or + * saGpioWrite() + * + * \param agRoot: Pointer to chip/driver Instance. + * \param gpioEvent: a bit map that indicates which GPIO + * input pins have generated the event. + * + * + * \return None. + * + */ +/*****************************************************************************/ +osGLOBAL void ossaGpioEvent( + agsaRoot_t *agRoot, + bit32 gpioEvent + ) +{ + TI_DBG2(("ossaGpioEvent: start\n")); + TI_DBG2(("ossaGpioEvent: gpioEvent 0x%x\n", gpioEvent)); + smTraceFuncEnter(hpDBG_VERY_LOUD,"Yo"); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Yo"); + return; +} + + +/*****************************************************************************/ +/*! \brief ossaSASDiagExecuteCB + * + * + * Purpose: This routine is called by lower layer to corresponding to + * saSASDiagExecute() + * + * \param agRoot: Pointer to chip/driver Instance. + * \param agContext: Context of the operation originally passed + * in. + * \param status: Diagnostic operation completion status + * \param command: SAS diagnostic command field in agsaSASDiagExecute_t + * structure passed in saSASDiagExecute(). + * \param reportData: Report Diagnostic Data + * + * + * \return None. + * + */ +/*****************************************************************************/ +osGLOBAL void ossaSASDiagExecuteCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + bit32 command, + bit32 reportData) +{ + smTraceFuncEnter(hpDBG_VERY_LOUD,"Yq"); + TI_DBG2(("ossaSASDiagExecuteCB: start\n")); + TI_DBG2(("ossaSASDiagExecuteCB: status %d\n", status)); + TI_DBG2(("ossaSASDiagExecuteCB: command %d\n", command)); + TI_DBG2(("ossaSASDiagExecuteCB: reportData %d\n", reportData)); + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Yq"); + return; + +} + + +/*****************************************************************************/ +/*! \brief ossaSASDiagStartEndCB + * + * + * Purpose: This routine is called by lower layer to corresponding to + * saSASDiagExecute() + * + * \param agRoot: Pointer to chip/driver Instance. + * \param agContext: Context of the operation originally passed + * in. + * \param status: Diagnostic operation completion status + * + * + * \return None. + * + */ +/*****************************************************************************/ +osGLOBAL void ossaSASDiagStartEndCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status) +{ + TI_DBG2(("ossaSASDiagStartEndCB: start\n")); + TI_DBG2(("ossaSASDiagStartEndCB: status %d\n", status)); + smTraceFuncEnter(hpDBG_VERY_LOUD,"Yr"); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Yr"); + return; +} + +/*****************************************************************************/ +/*! \brief ossaReconfigSASParamsCB + * + * + * Purpose: This routine is called by lower layer to corresponding to + * saReconfigSASParams() + * + * \param agRoot: Pointer to chip/driver Instance. + * \param agContext: Context of the operation originally passed + * in saReconfigSASParams(). + * \param status: saReconfigSASParams() completion status + * \param agSASConfig: Pointer to the data structure agsaSASReconfig_t + * + * + * \return None. + * + */ +/*****************************************************************************/ +osGLOBAL void ossaReconfigSASParamsCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + agsaSASReconfig_t *agSASConfig) +{ + TI_DBG2(("ossaReconfigSASParamsCB: status %d\n", status)); + return; +} + +GLOBAL void ossaPCIeDiagExecuteCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + bit32 command, + agsaPCIeDiagResponse_t *resp ) +{ + TI_DBG2(("ossaPCIeDiagExecuteCB: status %d\n", status)); + TI_DBG2(("ossaPCIeDiagExecuteCB: ERR_BLKH 0x%X\n",resp->ERR_BLKH )); + TI_DBG2(("ossaPCIeDiagExecuteCB: ERR_BLKL 0x%X\n",resp->ERR_BLKL )); + TI_DBG2(("ossaPCIeDiagExecuteCB: DWord8 0x%X\n",resp->DWord8 )); + TI_DBG2(("ossaPCIeDiagExecuteCB: DWord9 0x%X\n",resp->DWord9 )); + TI_DBG2(("ossaPCIeDiagExecuteCB: DWord10 0x%X\n",resp->DWord10 )); + TI_DBG2(("ossaPCIeDiagExecuteCB: DWord11 0x%X\n",resp->DWord11 )); + TI_DBG2(("ossaPCIeDiagExecuteCB: DIF_ERR 0x%X\n",resp->DIF_ERR )); + + return; +} + + +#ifndef BIOS +GLOBAL void ossaSGpioCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaSGpioReqResponse_t *pSgpioResponse + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + + TI_DBG2(("ossaSGpioCB: smpFrameType: 0x%02x \n", pSgpioResponse->smpFrameType)); + // printf("SS:ossaSGpioCB: smpFrameType: 0x%02x \n", pSgpioResponse->smpFrameType); + TI_DBG2(("ossaSGpioCB: function: 0x%02x \n", pSgpioResponse->function)); + TI_DBG2(("ossaSGpioCB: functionResult: 0x%02x \n", pSgpioResponse->functionResult)); + //printf("SS:ossaSGpioCB: functionResult: 0x%02x \n", pSgpioResponse->functionResult); + + tdhexdump("ossaSGpioCB Response", (bit8 *)pSgpioResponse, sizeof(agsaSGpioReqResponse_t)); + ostiSgpioIoctlRsp(tiRoot, pSgpioResponse); +} + +#endif /* BIOS */ + +/*****************************************************************************/ +/*! \brief ossaLogDebugString + * + * + * Purpose: This routine is called by lower layer to log. + * + * \param agRoot: Pointer to chip/driver Instance. + * \param level: Detail of information desired. + * \param string: Pointer to the character string. + * \param ptr1: First pointer value. + * \param ptr2: Second pointer value. + * \param value1: First 32-bit value related to the specific information. + * \param value2: Second 32-bit value related to the specific information. + * + * \return None. + * + */ +/*****************************************************************************/ +GLOBAL void ossaLogDebugString( + agsaRoot_t *agRoot, + bit32 level, + char *string, + void *ptr1, + void *ptr2, + bit32 value1, + bit32 value2 + ) +{ +#if defined(SALLSDK_DEBUG) + TIDEBUG_MSG(gLLDebugLevel, level, ("%s %p %p %d %d\n", string, ptr1, ptr2, value1, value2)); +#endif + return; +} + +/*****************************************************************************/ +/*! \brief ossaHwEventAckCB + * + * + * Purpose: This routine is called by lower layer to corresponding to + * saHwEventAck(() + * + * \param agRoot: Pointer to chip/driver Instance. + * \param agContext: Context of the operation originally passed + * in. + * \param status: Status + * + * + * \return None. + * + */ +/*****************************************************************************/ +GLOBAL void ossaHwEventAckCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status + ) +{ + TI_DBG3(("ossaHwEventAckCB: start\n")); + smTraceFuncEnter(hpDBG_VERY_LOUD,"Ys"); + if (status == tiSuccess) + { + TI_DBG3(("ossaHwEventAckCB: SUCCESS status\n")); + } + else + { + TI_DBG1(("ossaHwEventAckCB: FAIL status 0x%X\n", status)); + TI_DBG1(("ossaHwEventAckCB: invalid event status bit0 %d\n", status & 0x01)); + TI_DBG1(("ossaHwEventAckCB: invalid phyid status bit1 %d\n", (status & 0x02) >> 1 )); + TI_DBG1(("ossaHwEventAckCB: invalid portcontext status bit2 %d\n", (status & 0x04) >> 2)); + TI_DBG1(("ossaHwEventAckCB: invalid param0 status bit3 %d\n", (status & 0x08) >> 3)); + } + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Ys"); + return; +} + +/*****************************************************************************/ +/*! \brief ossaGetTimeStampCB + * + * + * Purpose: This routine is called by lower layer to corresponding to + * saGetTimeStamp() + * + * \param agRoot: Pointer to chip/driver Instance. + * \param agContext: Context of the operation originally passed + * in. + * \param timeStampLower: The controller lower 32-bit of internal time + * stamp associated with event log. + * \param timeStampUpper: The controller upper 32-bit of internal time + * stamp associated with event log. + * + * + * \return None. + * + */ +/*****************************************************************************/ +GLOBAL void ossaGetTimeStampCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 timeStampLower, + bit32 timeStampUpper + ) +{ + smTraceFuncEnter(hpDBG_VERY_LOUD,"Yt"); + TI_DBG4(("ossaGetTimeStampCB: start\n")); + TI_DBG4(("ossaGetTimeStampCB: timeStampUpper 0x%x timeStampLower 0x%x\n", timeStampUpper, timeStampLower)); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Yt"); + return; +} + + +/*****************************************************************************/ +/*! \brief ossaSMPAbortCB + * + * + * Purpose: This routine is called by lower layer to corresponding to + * saSMPAbort() + * + * \param agRoot: Pointer to chip/driver Instance. + * \param agIORequest: This is the agIORequest parameter passed in + * saSMPAbort() + * \param status: Status of abort + * + * \return None. + * + */ +/*****************************************************************************/ +GLOBAL void ossaSMPAbortCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 flag, + bit32 status) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdIORequestBody_t *tdAbortIORequestBody = agNULL; + tdsaDeviceData_t *oneDeviceData = agNULL; + tiDeviceHandle_t *tiDeviceHandle = agNULL; + + TI_DBG4(("ossaSMPAbortCB: start\n")); + TI_DBG4(("ossaSMPAbortCB: flag %d\n", flag)); + TI_DBG4(("ossaSMPAbortCB: status %d\n", status)); + smTraceFuncEnter(hpDBG_VERY_LOUD,"Yu"); + + tdAbortIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + if (tdAbortIORequestBody == agNULL) + { + TI_DBG1(("ossaSMPAbortCB: tdAbortIORequestBody is NULL warning!!!!\n")); + return; + } + + if (flag == 2) + { + /* abort per port */ + TI_DBG2(("ossaSMPAbortCB: abort per port\n")); + } + else if (flag == 1) + { + TI_DBG2(("ossaSMPAbortCB: abort all\n")); + + tiDeviceHandle = (tiDeviceHandle_t *)tdAbortIORequestBody->tiDevHandle; + if (tiDeviceHandle == agNULL) + { + TI_DBG1(("ossaSMPAbortCB: tiDeviceHandle is NULL warning!!!!\n")); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; + } + + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + if (oneDeviceData == agNULL) + { + TI_DBG1(("ossaSMPAbortCB: oneDeviceData is NULL warning!!!!\n")); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; + } + + if (status == OSSA_IO_SUCCESS) + { + TI_DBG2(("ossaSMPAbortCB: OSSA_IO_SUCCESS\n")); + /* clean up TD layer's IORequestBody */ + TI_DBG3(("ossaSMPAbortCB: calling saDeregisterDeviceHandle\n")); + saDeregisterDeviceHandle(agRoot, agNULL, oneDeviceData->agDevHandle, tdsaRotateQnumber(tiRoot, oneDeviceData)); + TI_DBG2(("ossaSMPAbortCB: did %d\n", oneDeviceData->id)); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + + } + else if (status == OSSA_IO_NOT_VALID) + { + TI_DBG1(("ossaSMPAbortCB: OSSA_IO_NOT_VALID\n")); + /* clean up TD layer's IORequestBody */ + TI_DBG1(("ossaSMPAbortCB: calling saDeregisterDeviceHandle\n")); + saDeregisterDeviceHandle(agRoot, agNULL, oneDeviceData->agDevHandle, tdsaRotateQnumber(tiRoot, oneDeviceData)); + TI_DBG1(("ossaSMPAbortCB: did %d\n", oneDeviceData->id)); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + else if (status == OSSA_IO_NO_DEVICE) + { + TI_DBG1(("ossaSMPAbortCB: OSSA_IO_NO_DEVICE\n")); + /* clean up TD layer's IORequestBody */ + TI_DBG1(("ossaSMPAbortCB: calling saDeregisterDeviceHandle\n")); + saDeregisterDeviceHandle(agRoot, agNULL, oneDeviceData->agDevHandle, tdsaRotateQnumber(tiRoot, oneDeviceData)); + TI_DBG1(("ossaSMPAbortCB: did %d\n", oneDeviceData->id)); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + else if (status == OSSA_IO_ABORT_IN_PROGRESS) + { + TI_DBG1(("ossaSMPAbortCB: OSSA_IO_ABORT_IN_PROGRESS\n")); + /* clean up TD layer's IORequestBody */ + TI_DBG1(("ossaSMPAbortCB: calling saDeregisterDeviceHandle\n")); + saDeregisterDeviceHandle(agRoot, agNULL, oneDeviceData->agDevHandle, tdsaRotateQnumber(tiRoot, oneDeviceData)); + TI_DBG1(("ossaSMPAbortCB: did %d\n", oneDeviceData->id)); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } +#ifdef REMOVED + else if (status == OSSA_IO_ABORT_DELAYED) + { + TI_DBG1(("ossaSMPAbortCB: OSSA_IO_ABORT_DELAYED\n")); + /* clean up TD layer's IORequestBody */ + TI_DBG1(("ossaSMPAbortCB: calling saDeregisterDeviceHandle\n")); + saDeregisterDeviceHandle(agRoot, agNULL, oneDeviceData->agDevHandle, tdsaRotateQnumber(tiRoot, oneDeviceData)); + TI_DBG1(("ossaSMPAbortCB: did %d\n", oneDeviceData->id)); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } +#endif + else + { + TI_DBG1(("ossaSMPAbortCB: other status %d\n", status)); + /* clean up TD layer's IORequestBody */ + TI_DBG1(("ossaSMPAbortCB: calling saDeregisterDeviceHandle\n")); + saDeregisterDeviceHandle(agRoot, agNULL, oneDeviceData->agDevHandle, tdsaRotateQnumber(tiRoot, oneDeviceData)); + TI_DBG1(("ossaSMPAbortCB: did %d\n", oneDeviceData->id)); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + } + else if (flag == 0) + { + TI_DBG2(("ossaSMPAbortCB: abort one\n")); + if (status == OSSA_IO_SUCCESS) + { + TI_DBG2(("ossaSMPAbortCB: OSSA_IO_SUCCESS\n")); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + + } + else if (status == OSSA_IO_NOT_VALID) + { + TI_DBG1(("ossaSMPAbortCB: OSSA_IO_NOT_VALID\n")); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + else if (status == OSSA_IO_NO_DEVICE) + { + TI_DBG1(("ossaSMPAbortCB: OSSA_IO_NO_DEVICE\n")); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + else if (status == OSSA_IO_ABORT_IN_PROGRESS) + { + TI_DBG1(("ossaSMPAbortCB: OSSA_IO_ABORT_IN_PROGRESS\n")); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } +#ifdef REMOVED + else if (status == OSSA_IO_ABORT_DELAYED) + { + TI_DBG1(("ossaSMPAbortCB: OSSA_IO_ABORT_DELAYED\n")); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } +#endif + else + { + TI_DBG1(("ossaSMPAbortCB: other status %d\n", status)); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + } + else + { + TI_DBG1(("ossaSMPAbortCB: wrong flag %d\n", flag)); + } + + + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Yu"); + return; +} + +/*****************************************************************************/ +/*! \brief ossaGeneralEvent + * + * + * Purpose: This is the event notification for debugging purposes sent to + * inform the OS layer of some general error related to a specific + * inbound operation. + * + * \param agRoot: Pointer to chip/driver Instance. + * \param status: Status associated with this event + * \param msg: Pointer to controller specific command + * massage that caused the error + * + * \return None. + * + */ +/*****************************************************************************/ +GLOBAL void ossaGeneralEvent( + agsaRoot_t *agRoot, + bit32 status, + agsaContext_t *agContext, + bit32 *msg) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + + TI_DBG1(("ossaGeneralEvent: start\n")); + TI_DBG1(("ossaGeneralEvent: status %d\n", status)); + + if(msg) + { + TI_DBG1(("ossaGeneralEvent: *msg %X\n", *msg)); + } + + smTraceFuncEnter(hpDBG_VERY_LOUD,"Yv"); + ostiGenEventIOCTLRsp(tiRoot, status); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Yv"); + return; +} + +GLOBAL void ossaGetForensicDataCB ( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + agsaForensicData_t *forensicData) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + + ostiGetForensicDataIOCTLRsp(tiRoot, status, forensicData); + return; +} + + +#ifdef INITIATOR_DRIVER + +GLOBAL void ossaGetIOErrorStatsCB ( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + agsaIOErrorEventStats_t *stats) + +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + + ostiGetIoErrorStatsIOCTLRsp(tiRoot, status, stats); +} +#else +GLOBAL void ossaGetIOErrorStatsCB ( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + agsaIOErrorEventStats_t *stats) + +{ + +} + +#endif + +GLOBAL void ossaGetIOEventStatsCB ( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + agsaIOErrorEventStats_t *stats) + +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + + ostiGetIoEventStatsIOCTLRsp(tiRoot, status, stats); +} + + +/*****************************************************************************/ +/*! \brief ossaGetRegisterDumpCB + * + * + * Purpose: ossaGetRegisterDumpCB() is the response callback function + * called by the LL Layer to indicate a response to + * saGetRegisterDump() + * + * \param agRoot: Pointer to chip/driver Instance. + * \param agContext: Context of the operation originally + * passed into saGetRegisterDump() + * \param status: status + * + * \return None. + * + */ +/*****************************************************************************/ +GLOBAL void ossaGetRegisterDumpCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status +) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + + TI_DBG4(("ossaGetRegisterDumpCB: start\n")); + TI_DBG4(("ossaGetRegisterDumpCB: status %d\n", status)); + smTraceFuncEnter(hpDBG_VERY_LOUD,"Yw"); + + ostiRegDumpIOCTLRsp(tiRoot, status); + smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Yw"); + return; +} + +/*****************************************************************************/ +/*! \brief ossaSetDeviceStateCB + * + * + * Purpose: ossaSetDeviceStateCB() is the response callback function + * called by the LL Layer to indicate a response to + * saSetDeviceState() + * + * \param agRoot: Pointer to chip/driver Instance. + * \param agContext: Context of the operation originally + * passed into saGetRegisterDump() + * \param agDevHandle Pointer to the device handle of the device + * \param status: status + * \param newDeviceState: newly set device status + * \param previousDeviceState: old device status + * + * \return None. + * + */ +/*****************************************************************************/ +GLOBAL void ossaSetDeviceStateCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaDevHandle_t *agDevHandle, + bit32 status, + bit32 newDeviceState, + bit32 previousDeviceState + ) +{ + tdsaDeviceData_t *oneDeviceData = agNULL; + + TI_DBG2(("ossaSetDeviceStateCB: start\n")); + TI_DBG2(("ossaSetDeviceStateCB: status %d\n", status)); + TI_DBG2(("ossaSetDeviceStateCB: newDeviceState %d\n", newDeviceState)); + TI_DBG2(("ossaSetDeviceStateCB: previousDeviceState %d\n", previousDeviceState)); + + if (agDevHandle == agNULL) + { + TI_DBG4(("ossaSetDeviceStateCB: agDevHandle is NULL\n")); + return; + } + + oneDeviceData = (tdsaDeviceData_t *)agDevHandle->osData; + + if (oneDeviceData == agNULL) + { + TI_DBG1(("ossaSetDeviceStateCB: wrong; oneDeviceData is NULL\n")); + } + else + { + TI_DBG2(("ossaSetDeviceStateCB: did %d\n", oneDeviceData->id)); + } + + return; +} + +/*****************************************************************************/ +/*! \brief ossaGetDeviceStateCB + * + * + * Purpose: ossaGetDeviceStateCB() is the response callback function + * called by the LL Layer to indicate a response to + * saGetDeviceState() + * + * \param agRoot: Pointer to chip/driver Instance. + * \param agContext: Context of the operation originally + * passed into saGetRegisterDump() + * \param agDevHandle Pointer to the device handle of the device + * \param status: status + * \param deviceState: device status + * + * \return None. + * + */ +/*****************************************************************************/ +GLOBAL void ossaGetDeviceStateCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaDevHandle_t *agDevHandle, + bit32 status, + bit32 deviceState + ) +{ + TI_DBG4(("ossaGetDeviceStateCB: start\n")); + TI_DBG4(("ossaGetDeviceStateCB: status %d\n", status)); + TI_DBG4(("ossaGetDeviceStateCB: deviceState %d\n", deviceState)); + + return; +} + +#ifdef INITIATOR_DRIVER +/*****************************************************************************/ +/*! \brief ossaIniSetDeviceInfoCB + * + * + * Purpose: ossaIniSetDeviceInfoCB() is the response callback function + * called by the LL Layer to indicate a response to + * saSetDeviceInfo() + * + * \param agRoot: Pointer to chip/driver Instance. + * \param agContext: Context of the operation originally + * passed into saSetDeviceInfo() + * \param agDevHandle Pointer to the device handle of the device + * \param status: status + * \param option: option parameter passed in saSetDeviceInfo() + * \param param: param parameter passed in saSetDeviceInfo() + * + * \return None. + * + */ +/*****************************************************************************/ +osGLOBAL void +ossaIniSetDeviceInfoCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaDevHandle_t *agDevHandle, + bit32 status, + bit32 option, + bit32 param + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + itdsaIni_t *Initiator = (itdsaIni_t *)tdsaAllShared->itdsaIni; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody = agNULL; + agsaIORequest_t *agIORequest = agNULL; + bit32 saStatus = AGSA_RC_FAILURE; + bit8 devType_S_Rate; + tdsaDeviceData_t *oneDeviceData = agNULL; + + TI_DBG4(("ossaIniSetDeviceInfoCB: start\n")); + TI_DBG4(("ossaIniSetDeviceInfoCB: status 0x%x\n", status)); + TI_DBG4(("ossaIniSetDeviceInfoCB: option 0x%x\n", option)); + TI_DBG4(("ossaIniSetDeviceInfoCB: param 0x%x\n", param)); + + if (status != OSSA_SUCCESS) + { + TI_DBG1(("ossaIniSetDeviceInfoCB: status %d\n", status)); + TI_DBG1(("ossaIniSetDeviceInfoCB: option 0x%x\n", option)); + TI_DBG1(("ossaIniSetDeviceInfoCB: param 0x%x\n", param)); + if (option == 32) /* set connection rate */ + { + TI_DBG1(("ossaIniSetDeviceInfoCB: IO failure\n")); + agIORequest = (agsaIORequest_t *)agContext->osData; + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + ostiInitiatorIOCompleted( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + } + } + if (agDevHandle == agNULL) + { + TI_DBG4(("ossaIniSetDeviceInfoCB: agDevHandle is NULL\n")); + return; + } + oneDeviceData = (tdsaDeviceData_t *)agDevHandle->osData; + if (oneDeviceData == agNULL) + { + TI_DBG1(("ossaIniSetDeviceInfoCB: wrong; oneDeviceData is NULL\n")); + return; + } + else + { + TI_DBG4(("ossaIniSetDeviceInfoCB: did %d\n", oneDeviceData->id)); + } + + /* retry IOs */ + if (option == 32) /* set connection rate */ + { + TI_DBG1(("ossaIniSetDeviceInfoCB: set connection rate option\n")); + agIORequest = (agsaIORequest_t *)agContext->osData; + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + devType_S_Rate = oneDeviceData->agDeviceInfo.devType_S_Rate; + devType_S_Rate = (devType_S_Rate & 0xF0) | (param >> 28); + oneDeviceData->agDeviceInfo.devType_S_Rate = devType_S_Rate; + TI_DBG1(("ossaIniSetDeviceInfoCB: new rate is 0x%x\n", DEVINFO_GET_LINKRATE(&oneDeviceData->agDeviceInfo))); + if (oneDeviceData->valid == agTRUE && oneDeviceData->registered == agTRUE && + oneDeviceData->tdPortContext != agNULL ) + { + saStatus = saSSPStart(agRoot, + agIORequest, + tdsaRotateQnumber(tiRoot, oneDeviceData), + agDevHandle, + tdIORequestBody->agRequestType, + &(tdIORequestBody->transport.SAS.agSASRequestBody), + agNULL, + &ossaSSPCompleted); + if (saStatus == AGSA_RC_SUCCESS) + { + TI_DBG1(("ossaIniSetDeviceInfoCB: retried\n")); + Initiator->NumIOsActive++; + tdIORequestBody->ioStarted = agTRUE; + tdIORequestBody->ioCompleted = agFALSE; + return; + } + else + { + TI_DBG1(("ossaIniSetDeviceInfoCB: retry failed\n")); + tdIORequestBody->ioStarted = agFALSE; + tdIORequestBody->ioCompleted = agTRUE; + ostiInitiatorIOCompleted( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + } + } + } + return; +} +#endif +/*****************************************************************************/ +/*! \brief ossaSetDeviceInfoCB + * + * + * Purpose: ossaSetDeviceInfoCB() is the response callback function + * called by the LL Layer to indicate a response to + * saSetDeviceInfo() + * + * \param agRoot: Pointer to chip/driver Instance. + * \param agContext: Context of the operation originally + * passed into saSetDeviceInfo() + * \param agDevHandle Pointer to the device handle of the device + * \param status: status + * \param option: option parameter passed in saSetDeviceInfo() + * \param param: param parameter passed in saSetDeviceInfo() + * + * \return None. + * + */ +/*****************************************************************************/ +GLOBAL void ossaSetDeviceInfoCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaDevHandle_t *agDevHandle, + bit32 status, + bit32 option, + bit32 param + ) +{ + tdsaDeviceData_t *oneDeviceData = agNULL; + + TI_DBG4(("ossaSetDeviceInfoCB: start\n")); + TI_DBG4(("ossaSetDeviceInfoCB: status 0x%x\n", status)); + TI_DBG4(("ossaSetDeviceInfoCB: option 0x%x\n", option)); + TI_DBG4(("ossaSetDeviceInfoCB: param 0x%x\n", param)); + + if (status != OSSA_SUCCESS) + { + TI_DBG1(("ossaSetDeviceInfoCB: status %d\n", status)); + TI_DBG1(("ossaSetDeviceInfoCB: option 0x%x\n", option)); + TI_DBG1(("ossaSetDeviceInfoCB: param 0x%x\n", param)); + } + + if (agDevHandle == agNULL) + { + TI_DBG4(("ossaSetDeviceInfoCB: agDevHandle is NULL\n")); + return; + } + + oneDeviceData = (tdsaDeviceData_t *)agDevHandle->osData; + + if (oneDeviceData == agNULL) + { + TI_DBG1(("ossaSetDeviceInfoCB: wrong; oneDeviceData is NULL\n")); + } + else + { + TI_DBG4(("ossaSetDeviceInfoCB: did %d\n", oneDeviceData->id)); + } + + return; +} + +/*****************************************************************************/ +/*! \brief ossaGetDFEDataCB + * + * + * Purpose: ossaGetDFEDataCB() is the response callback function + * called by the LL Layer to indicate a response to + * saGetDFEData() + * + * \param agRoot: Pointer to chip/driver Instance. + * \param agContext: Context of the operation originally + * passed into saGetDFEData() + * \param status: status + * \param agInfoLen: length in bytes of DFE data captured and transferred + * + * \return None. + * + */ +/*****************************************************************************/ +GLOBAL void ossaGetDFEDataCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + bit32 agInfoLen) +{ + TI_DBG1(("ossaGetDFEDataCB: start\n")); + TI_DBG1(("ossaGetDFEDataCB: status 0x%x agInfoLen 0x%x\n", status, agInfoLen)); + return; +} + +/*****************************************************************************/ +/*! \brief ossaVhistCaptureCB + * + * + * Purpose: ossaVhistCaptureCB() is the response callback function + * called by the LL Layer to indicate a response to + * saGetDFEData() + * + * \param agRoot: Pointer to chip/driver Instance. + * \param agContext: Context of the operation originally + * passed into () + * \param status: status + * \param len: length in bytes of Vis data captured and transferred + * + * \return None. + * + */ +/*****************************************************************************/ + +void ossaVhistCaptureCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + bit32 len) +{ + TI_DBG1(("ossaVhistCaptureCB: start\n")); + TI_DBG1(("ossaVhistCaptureCB: status 0x%x agInfoLen 0x%x\n", status,len )); + return; +} + +GLOBAL void ossaOperatorManagementCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + bit32 eq + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tiEncryptPort_t encryptEventData; + + TI_DBG1(("ossaOperatorManagementCB: status 0x%x eq 0x%x\n", status, eq)); + + osti_memset(&encryptEventData, 0, sizeof(tiEncryptPort_t)); + encryptEventData.encryptEvent = tiEncryptOperatorManagement; + encryptEventData.subEvent = eq; + encryptEventData.pData = agNULL; + + ostiPortEvent(tiRoot, + tiEncryptOperation, + status, + &encryptEventData); +} + +GLOBAL void ossaEncryptSelftestExecuteCB ( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + bit32 type, + bit32 length, + void *TestResult + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tiEncryptPort_t encryptEventData; + + TI_DBG1(("ossaEncryptSelftestExecuteCB: status 0x%x type 0x%x length 0x%x\n", status, type, length)); + + osti_memset(&encryptEventData, 0, sizeof(tiEncryptPort_t)); + encryptEventData.encryptEvent = tiEncryptSelfTest; + encryptEventData.subEvent = type; + encryptEventData.pData = (void*)TestResult; + + ostiPortEvent(tiRoot, + tiEncryptOperation, + status, + &encryptEventData); +} + +GLOBAL void ossaGetOperatorCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + bit32 option, + bit32 num, + bit32 role, + agsaID_t *id + ) +{ + + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tiEncryptPort_t encryptEventData; + + TI_DBG1(("ossaGetOperatorCB: status 0x%x option 0x%x num 0x%x role 0x%x\n", + status, option, num, role)); + TI_DBG1(("ossaGetOperatorCB: agContext %p id %p\n",agContext,id)); + osti_memset(&encryptEventData, 0, sizeof(tiEncryptPort_t)); + encryptEventData.encryptEvent = tiEncryptGetOperator; + encryptEventData.subEvent = option; + encryptEventData.pData = agNULL; + + switch(status) + { + case OSSA_IO_SUCCESS: + TI_DBG1(("ossaGetOperatorCB: OSSA_IO_SUCCESS option 0x%x\n", option)); + if(option == 1) + { + TI_DBG2(("ossaGetOperatorCB: 0x%02x 0x%02x 0x%02x 0x%02x\n",id->ID[0], id->ID[1], id->ID[2], id->ID[3])); + TI_DBG2(("ossaGetOperatorCB: 0x%02x 0x%02x 0x%02x 0x%02x\n",id->ID[4], id->ID[5], id->ID[6], id->ID[7])); + TI_DBG2(("ossaGetOperatorCB: 0x%02x 0x%02x 0x%02x 0x%02x\n",id->ID[8], id->ID[9], id->ID[10],id->ID[11])); + TI_DBG2(("ossaGetOperatorCB: 0x%02x 0x%02x 0x%02x 0x%02x\n",id->ID[12],id->ID[13],id->ID[14],id->ID[15])); + TI_DBG2(("ossaGetOperatorCB: 0x%02x 0x%02x 0x%02x 0x%02x\n",id->ID[16],id->ID[17],id->ID[18],id->ID[19])); + TI_DBG2(("ossaGetOperatorCB: 0x%02x 0x%02x 0x%02x 0x%02x\n",id->ID[20],id->ID[21],id->ID[22],id->ID[23])); + TI_DBG2(("ossaGetOperatorCB: 0x%02x 0x%02x 0x%02x 0x%02x\n",id->ID[24],id->ID[25],id->ID[26],id->ID[27])); + TI_DBG2(("ossaGetOperatorCB: 0x%02x 0x%02x 0x%02x\n", id->ID[28],id->ID[29],id->ID[30])); + }else if(option == 2) + { + TI_DBG1(("ossaGetOperatorCB: number operators 0x%02x\n", num )); + } + + encryptEventData.pData = id; + break; + case OSSA_MPI_ENC_ERR_UNSUPPORTED_OPTION: + TI_DBG1(("ossaGetOperatorCB: OSSA_MPI_ENC_ERR_UNSUPPORTED_OPTION 0x%x\n",option)); + break; + case OSSA_MPI_ENC_ERR_ID_TRANSFER_FAILURE: + TI_DBG1(("ossaGetOperatorCB: OSSA_MPI_ENC_ERR_ID_TRANSFER_FAILURE 0x%x\n",option)); + break; + default: + TI_DBG1(("ossaGetOperatorCB: Unknown status 0x%x\n",status)); + } + ostiPortEvent(tiRoot, + tiEncryptOperation, + status, + &encryptEventData); + +} + +GLOBAL void ossaSetOperatorCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + bit32 eq + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tiEncryptPort_t encryptEventData; + + TI_DBG1(("ossaSetOperatorCB: agContext %p status 0x%x eq 0x%x\n",agContext, status, eq)); + + osti_memset(&encryptEventData, 0, sizeof(tiEncryptPort_t)); + encryptEventData.encryptEvent = tiEncryptSetOperator; + encryptEventData.subEvent = 0; + switch(status) + { + case OSSA_IO_SUCCESS: + TI_DBG1(("ossaSetOperatorCB: OSSA_IO_SUCCESS\n")); + encryptEventData.pData = agNULL; + break; + case OSSA_MPI_ENC_ERR_CONTROLLER_NOT_IDLE: + TI_DBG1(("ossaSetOperatorCB: OSSA_MPI_ENC_ERR_CONTROLLER_NOT_IDLE\n")); + break; + case OSSA_MPI_ENC_OPERATOR_AUTH_FAILURE: + TI_DBG1(("ossaSetOperatorCB: OSSA_MPI_ENC_OPERATOR_AUTH_FAILURE error qualifier 0x%x\n",eq)); + break; + case OSSA_MPI_ENC_OPERATOR_OPERATOR_ALREADY_LOGGED_IN: + TI_DBG1(("ossaSetOperatorCB: OSSA_MPI_ENC_OPERATOR_OPERATOR_ALREADY_LOGGED_IN\n")); + break; + case OSSA_MPI_ENC_OPERATOR_ILLEGAL_PARAMETER: + TI_DBG1(("ossaSetOperatorCB: OSSA_MPI_ENC_OPERATOR_ILLEGAL_PARAMETER\n")); + break; + case OSSA_MPI_ENC_ERR_UNSUPPORTED_OPTION: + TI_DBG1(("ossaSetOperatorCB: OSSA_MPI_ENC_ERR_UNSUPPORTED_OPTION\n")); + break; + case OSSA_MPI_ENC_ERR_ID_TRANSFER_FAILURE: + TI_DBG1(("ossaSetOperatorCB: OSSA_MPI_ENC_ERR_ID_TRANSFER_FAILURE\n")); + break; + default: + TI_DBG1(("ossaGetOperatorCB: Unknown status 0x%x\n",status)); + } + ostiPortEvent(tiRoot, + tiEncryptOperation, + status, + &encryptEventData); +} + +GLOBAL void ossaDIFEncryptionOffloadStartCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + agsaOffloadDifDetails_t *agsaOffloadDifDetails) +{ + TI_DBG1(("ossaDIFEncryptionOffloadStartCB: start\n")); + TI_DBG1(("ossaDIFEncryptionOffloadStartCB: status 0x%x agsaOffloadDifDetails=%p\n", status, agsaOffloadDifDetails)); + return; +} + +GLOBAL bit32 ossaTimeStamp( agsaRoot_t *agRoot ) +{ + tdsaRootOsData_t *osData= agNULL; + tiRoot_t *tiRoot= agNULL; + if(agRoot) + { + osData = (tdsaRootOsData_t *)agRoot->osData; + } + if(osData) + { + tiRoot = (tiRoot_t *)osData->tiRoot; + } + return(ostiTimeStamp(tiRoot)); +} + +GLOBAL bit64 ossaTimeStamp64( agsaRoot_t *agRoot) +{ + tdsaRootOsData_t *osData= agNULL; + tiRoot_t *tiRoot= agNULL; + if(agRoot) + { + osData = (tdsaRootOsData_t *)agRoot->osData; + } + if(osData) + { + tiRoot = (tiRoot_t *)osData->tiRoot; + } + return(ostiTimeStamp64(tiRoot)); +} + +#ifdef FDS_SM +osGLOBAL void +tdIDStartTimer(tiRoot_t *tiRoot, + smIORequest_t *smIORequest, + tdsaDeviceData_t *oneDeviceData + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + itdsaIni_t *Initiator = (itdsaIni_t *)tdsaAllShared->itdsaIni; + + TI_DBG1(("tdIDStartTimer: start\n")); + + tdsaSingleThreadedEnter(tiRoot, TD_TIMER_LOCK); + if (oneDeviceData->tdIDTimer.timerRunning == agTRUE) + { + tdsaSingleThreadedLeave(tiRoot, TD_TIMER_LOCK); + tdsaKillTimer( + tiRoot, + &oneDeviceData->tdIDTimer + ); + } + else + { + tdsaSingleThreadedLeave(tiRoot, TD_TIMER_LOCK); + } + + tdsaSetTimerRequest( + tiRoot, + &oneDeviceData->tdIDTimer, + SATA_ID_DEVICE_DATA_TIMER_VALUE/Initiator->OperatingOption.UsecsPerTick, + tdIDStartTimerCB, + smIORequest, + oneDeviceData, + agNULL + ); + + tdsaAddTimer( + tiRoot, + &Initiator->timerlist, + &oneDeviceData->tdIDTimer + ); + TI_DBG1(("tdIDStartTimer: end\n")); + return; +} + +osGLOBAL void +tdIDStartTimerCB( + tiRoot_t * tiRoot, + void * timerData1, + void * timerData2, + void * timerData3 + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + smIORequest_t *smIORequest; + tdsaDeviceData_t *oneDeviceData; + smRoot_t *smRoot; + tdIORequestBody_t *tdIORequestBody; + smDeviceHandle_t *smDeviceHandle; + tdsaPortContext_t *onePortContext; +#ifdef REMOVED + agsaRoot_t *agRoot; + bit32 IDstatus; +//#endif +//#ifdef REMOVED + agsaIORequest_t *agAbortIORequest = agNULL; + tdIORequestBody_t *tdAbortIORequestBody = agNULL; + bit32 PhysUpper32; + bit32 PhysLower32; + bit32 memAllocStatus; + void *osMemHandle; +#endif // REMOVED +#ifdef TD_DEBUG_ENABLE + bit32 status = AGSA_RC_FAILURE; +#endif + + TI_DBG1(("tdIDStartTimerCB start\n")); + smIORequest = (smIORequest_t *)timerData1; + oneDeviceData = (tdsaDeviceData_t *)timerData2; + smRoot = &(tdsaAllShared->smRoot); +#ifdef REMOVED + agRoot = oneDeviceData->agRoot; +#endif // REMOVED + + if (smIORequest == agNULL) + { + TI_DBG1(("tdIDStartTimerCB: smIORequest == agNULL !!!!!!\n")); + return; + } + + if (oneDeviceData == agNULL) + { + TI_DBG1(("tdIDStartTimerCB: oneDeviceData == agNULL !!!!!!\n")); + return; + } + + if (oneDeviceData->satDevData.IDPending == agFALSE || oneDeviceData->satDevData.IDDeviceValid == agTRUE) + { + /*the Identify Device command already normally completed, just return*/ + return; + } + + tdIORequestBody = (tdIORequestBody_t *)smIORequest->tdData; + smDeviceHandle = (smDeviceHandle_t *)&(oneDeviceData->smDeviceHandle); + onePortContext = oneDeviceData->tdPortContext; + if (tdIORequestBody == agNULL) + { + TI_DBG1(("tdIDStartTimerCB: tdIORequestBody == agNULL !!!!!!\n")); + return; + } + + if (smDeviceHandle == agNULL) + { + TI_DBG1(("tdIDStartTimerCB: smDeviceHandle == agNULL !!!!!!\n")); + return; + } + + if (onePortContext == agNULL) + { + TI_DBG1(("tdIDStartTimerCB: onePortContext == agNULL !!!!!!\n")); + return; + } + + TI_DBG1(("tdIDStartTimerCB: did %d\n", oneDeviceData->id)); + /* + 1. smIOabort() + 2. in tdsmIDCompletedCB(), retry + */ + if (oneDeviceData->valid == agFALSE) + { + TI_DBG1(("tdIDStartTimerCB: invalid device\n")); + return; + } +#ifdef TD_DEBUG_ENABLE + status = smIOAbort( smRoot, smIORequest ); +#else + smIOAbort( smRoot, smIORequest ); +#endif + +#ifdef REMOVED + /* allocating agIORequest for abort itself */ + memAllocStatus = ostiAllocMemory( + tiRoot, + &osMemHandle, + (void **)&tdAbortIORequestBody, + &PhysUpper32, + &PhysLower32, + 8, + sizeof(tdIORequestBody_t), + agTRUE + ); + if (memAllocStatus != tiSuccess) + { + /* let os process IO */ + TI_DBG1(("tdIDStartTimerCB: ostiAllocMemory failed...; can't retry ID data \n")); + return; + } + if (tdAbortIORequestBody == agNULL) + { + /* let os process IO */ + TI_DBG1(("tdIDStartTimerCB: ostiAllocMemory returned NULL tdAbortIORequestBody; can't retry ID data\n")); + return; + } + /* setup task management structure */ + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle = osMemHandle; + /* setting callback but not used later */ + tdAbortIORequestBody->IOCompletionFunc = agNULL; + //tdAbortIORequestBody->IOCompletionFunc = itdssIOAbortedHandler; + tdAbortIORequestBody->tiDevHandle = (tiDeviceHandle_t *)&(oneDeviceData->tiDeviceHandle); + /* initialize agIORequest */ + agAbortIORequest = &(tdAbortIORequestBody->agIORequest); + agAbortIORequest->osData = (void *) tdAbortIORequestBody; + agAbortIORequest->sdkData = agNULL; /* LL takes care of this */ +//#endif +//#ifdef REMOVED + status = saSATAAbort(agRoot, + agAbortIORequest, + 0, + oneDeviceData->agDevHandle, + 1, /* abort all */ + agNULL, + ossaSATAIDAbortCB + ); + status = saSATAAbort(agRoot, + agAbortIORequest, + 0, + oneDeviceData->agDevHandle, + 0, /* abort one */ + agIORequest, + ossaSATAIDAbortCB + ); +//#endif +//#ifdef REMOVED + if (status != AGSA_RC_SUCCESS) + { + TI_DBG1(("tdIDStartTimerCB: saSATAAbort failed; can't retry ID data\n")); + } + if (oneDeviceData->satDevData.IDDeviceValid == agTRUE) + { + TI_DBG1(("tdIDStartTimerCB: IDDeviceValid is valid, no need to retry\n")); + return; + } + if (tdIORequestBody->reTries <= SM_RETRIES) + { + tdIORequestBody->tiIORequest = agNULL; /* not in use */ + tdIORequestBody->pid = onePortContext->id; + smIORequest->tdData = tdIORequestBody; + smIORequest->smData = &tdIORequestBody->smIORequestBody; + smDeviceHandle->tdData = oneDeviceData; + IDstatus = smIDStart(smRoot, smIORequest, smDeviceHandle ); + if (IDstatus == SM_RC_SUCCESS) + { + TI_DBG1(("tdIDStartTimerCB: being retried!!!\n")); + tdIORequestBody->reTries++; + tdIORequestBody->ioCompleted = agFALSE; + tdIORequestBody->ioStarted = agTRUE; + tdIDStartTimer(tiRoot, smIORequest, oneDeviceData); + } + else + { + /* identify device data is not valid */ + TI_DBG1(("tdIDStartTimerCB: smIDStart fail or busy %d!!!\n", IDstatus)); + tdIORequestBody->reTries = 0; + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + ostiFreeMemory( tiRoot, + tdIORequestBody->osMemHandle, + sizeof(tdIORequestBody_t) + ); + oneDeviceData->satDevData.IDDeviceValid = agFALSE; + smReportRemoval(tiRoot, agRoot, oneDeviceData, onePortContext); + return; + } + } + else + { + /* give up */ + TI_DBG1(("tdIDStartTimerCB: retries are over!!!\n")); + if (oneDeviceData->tdIDTimer.timerRunning == agTRUE) + { + tdsaKillTimer( tiRoot, &oneDeviceData->tdIDTimer ); + } + tdIORequestBody->reTries = 0; + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + ostiFreeMemory( + tiRoot, + tdIORequestBody->osMemHandle, + sizeof(tdIORequestBody_t) + ); + oneDeviceData->satDevData.IDDeviceValid = agFALSE; + + if (oneDeviceData->SMNumOfID <= 0) /* does SMP HARD RESET only upto one time */ + { + TI_DBG1(("tdIDStartTimerCB: fail; sending HARD_RESET\n")); + oneDeviceData->SMNumOfID++; + if (oneDeviceData->directlyAttached == agTRUE) + { + saLocalPhyControl(agRoot, agNULL, 0, oneDeviceData->phyID, AGSA_PHY_HARD_RESET, agNULL); + } + else + { + tdsaPhyControlSend(tiRoot, + oneDeviceData, + SMP_PHY_CONTROL_HARD_RESET, + agNULL); + } + } + else + { + /* given up after one time of SMP HARD RESET; */ + TI_DBG1(("tdIDStartTimerCB: fail; but giving up sending HARD_RESET!!!\n")); + if (oneDeviceData->directlyAttached == agTRUE) + { + smReportRemovalDirect(tiRoot, agRoot, oneDeviceData); + } + else + { + smReportRemoval(tiRoot, agRoot, oneDeviceData, onePortContext); + } + } + } +#endif // REMOVED + + TI_DBG1(("tdIDStartTimerCB: end, smIOAbort status %d\n", status)); + return; +} +#endif // FDS_SM + + +#if defined(FDS_DM) && defined(FDS_SM) +//start here +GLOBAL void +tdIDStart( + tiRoot_t *tiRoot, + agsaRoot_t *agRoot, + smRoot_t *smRoot, + tdsaDeviceData_t *oneDeviceData, + tdsaPortContext_t *onePortContext + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + bit32 SMstatus = SM_RC_FAILURE; + tdIORequestBody_t *tdIORequestBody; + smIORequest_t *smIORequest; + smDeviceHandle_t *smDeviceHandle; + bit32 PhysUpper32; + bit32 PhysLower32; + bit32 memAllocStatus; + void *osMemHandle; + + + TI_DBG1(("tdIDStart: start, did %d\n",oneDeviceData->id)); + + if ( (DEVICE_IS_SATA_DEVICE(oneDeviceData)|| DEVICE_IS_STP_TARGET(oneDeviceData)) + && + oneDeviceData->satDevData.IDDeviceValid == agFALSE + && + oneDeviceData->satDevData.IDPending == agFALSE + ) + { + TI_DBG2(("tdIDStart: in loop, did %d\n", oneDeviceData->id)); + /* allocating tdIORequestBody */ + memAllocStatus = ostiAllocMemory( + tiRoot, + &osMemHandle, + (void **)&tdIORequestBody, + &PhysUpper32, + &PhysLower32, + 8, + sizeof(tdIORequestBody_t), + agTRUE + ); + if (memAllocStatus != tiSuccess || tdIORequestBody == agNULL) + { + /* let os process IO */ + TI_DBG1(("tdIDStart: ostiAllocMemory failed... or ostiAllocMemory returned NULL tdIORequestBody!!!\n")); + oneDeviceData->satDevData.IDDeviceValid = agFALSE; + if (oneDeviceData->directlyAttached == agTRUE) + { + /* notifying link up */ + ostiPortEvent( + tiRoot, + tiPortLinkUp, + tiSuccess, + (void *)onePortContext->tiPortalContext + ); +#ifdef INITIATOR_DRIVER + /* triggers discovery */ + ostiPortEvent( + tiRoot, + tiPortDiscoveryReady, + tiSuccess, + (void *) onePortContext->tiPortalContext + ); +#endif + } + } + else + { + /* initialize */ + osti_memset(tdIORequestBody, 0, sizeof(tdIORequestBody_t)); + + tdIORequestBody->osMemHandle = osMemHandle; + TI_DBG2(("tdIDStart: tdIORequestBody %p tdIORequestBody->osMemHandle %p\n", tdIORequestBody, tdIORequestBody->osMemHandle)); + + /* not in use */ + tdIORequestBody->IOCompletionFunc = agNULL; + tdIORequestBody->tiDevHandle = agNULL; + + tdIORequestBody->tiIORequest = agNULL; /* not in use */ + tdIORequestBody->pid = onePortContext->id; + tdIORequestBody->reTries = 0; + smIORequest = (smIORequest_t *)&(tdIORequestBody->smIORequest); + smIORequest->tdData = tdIORequestBody; + smIORequest->smData = &tdIORequestBody->smIORequestBody; + + smDeviceHandle = (smDeviceHandle_t *)&(oneDeviceData->smDeviceHandle); + smDeviceHandle->tdData = oneDeviceData; + + TI_DBG2(("tdIDStart: smIORequest %p\n", smIORequest)); + + SMstatus = smIDStart(smRoot, + smIORequest, + &(oneDeviceData->smDeviceHandle) + ); + + if (SMstatus == SM_RC_SUCCESS) + { + if (oneDeviceData->directlyAttached == agTRUE) + { + TI_DBG2(("tdIDStart: successfully sent identify device data\n")); + + /* Add the devicedata to the mainlink */ + tdsaSingleThreadedEnter(tiRoot, TD_DEVICE_LOCK); + TDLIST_ENQUEUE_AT_TAIL(&(oneDeviceData->MainLink), &(tdsaAllShared->MainDeviceList)); + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + TI_DBG6(("tdIDStart: one case did %d \n", oneDeviceData->id)); + } + oneDeviceData->satDevData.IDPending = agTRUE; + /* start a timer */ + tdIDStartTimer(tiRoot, smIORequest, oneDeviceData); + } + else + { + /* failed to send */ + TI_DBG1(("tdIDStart: smIDStart fail or busy %d\n", SMstatus)); + + /* free up allocated memory */ + ostiFreeMemory( + tiRoot, + tdIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + + oneDeviceData->satDevData.IDDeviceValid = agFALSE; + if (oneDeviceData->directlyAttached == agTRUE) + { + TI_DBG1(("tdIDStart: failed in sending identify device data\n")); + /* put onedevicedata back to free list */ + tdsaSingleThreadedEnter(tiRoot, TD_DEVICE_LOCK); + TDLIST_ENQUEUE_AT_TAIL(&(oneDeviceData->FreeLink), &(tdsaAllShared->FreeDeviceList)); + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + /* notifying link up */ + ostiPortEvent( + tiRoot, + tiPortLinkUp, + tiSuccess, + (void *)onePortContext->tiPortalContext + ); +#ifdef INITIATOR_DRIVER + /* triggers discovery */ + ostiPortEvent( + tiRoot, + tiPortDiscoveryReady, + tiSuccess, + (void *) onePortContext->tiPortalContext + ); +#endif + } + else + { + smReportRemoval(tiRoot, agRoot, oneDeviceData, onePortContext); + } + } + } + } + TI_DBG1(("tdIDStart: exit\n")); + return; +} + +#endif + +#ifdef SALLSDK_OS_IOMB_LOG_ENABLE +GLOBAL void ossaLogIomb(agsaRoot_t *agRoot, + bit32 queueNum, + agBOOLEAN isInbound, + void *pMsg, + bit32 msgLength) +{ + return; +} +#endif /* SALLSDK_OS_IOMB_LOG_ENABLE */ + +#ifndef SATA_ENABLE +/* + * These callback routines are defined in ossasat.c which are included in the + * compilation if SATA_ENABLED is defined. + */ + +/***************************************************************************** +*! \brief ossaDiscoverSataCB +* +* Purpose: This function is called by lower layer to inform TD layer of +* STP/SATA discovery results +* +* +* \param agRoot Pointer to chip/driver Instance. +* \param agPortContext Pointer to the port context of TD and Lower layer +* \param event event type +* \param pParm1 Pointer to data associated with event +* \param pParm2 Pointer to data associated with event +* +* \return: none +* +* \note - For details, refer to SAS/SATA Low-Level API Specification +* +*****************************************************************************/ + +osGLOBAL void ossaDiscoverSataCB( agsaRoot_t *agRoot, + agsaPortContext_t *agPortContext, + bit32 event, + void *pParm1, + void *pParm2 + ) +{ + return; +} + + +/***************************************************************************** +*! \brief ossaSATACompleted +* +* This routine is called to complete a SATA request previously issued to the +* LL Layer in saSATAStart() +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* +* \return: none +* +*****************************************************************************/ +GLOBAL void ossaSATACompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + void *agFirstDword, + bit32 agIOInfoLen, + void *agParam + ) +{ + return; +} + + +/***************************************************************************** +*! \brief ossaSATAEvent +* +* This routine is called to notify the OS Layer of an event associated with +* SATA port or SATA device +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agPortContext Pointer to the port context of TD and Lower layer +* \param agDevHandle: Pointer to a device handle +* \param event: event type +* +* \return: none +* +*****************************************************************************/ +osGLOBAL void ossaSATAEvent( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + agsaPortContext_t *agPortContext, + agsaDevHandle_t *agDevHandle, + bit32 event, + bit32 agIOInfoLen, + void *agParam + ) +{ + return; +} + + +/***************************************************************************** +*! \brief ossaSATADeviceResetCB +* +* This routine is called to complete a SATA device reset request previously +* issued to the LL Layer in saSATADeviceReset(). +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agDevHandle: Pointer to a device handle +* \param resetStatus: Reset status: +* OSSA_SUCCESS: The reset operation completed successfully. +* OSSA_FAILURE: The reset operation failed. +* \param resetparm: Pointer to the Device-To-Host FIS received from the device. +* +* \return: none +* +*****************************************************************************/ +osGLOBAL void ossaSATADeviceResetCB( + agsaRoot_t *agRoot, + agsaDevHandle_t *agDevHandle, + bit32 resetStatus, + void *resetparm) +{ + + return; + +} + +/***************************************************************************** +*! \brief ossaDiscoverSasCB +* +* Purpose: This function is called by lower layer to inform TD layer of +* SAS discovery results +* +* +* \param agRoot Pointer to chip/driver Instance. +* \param agPortContext Pointer to the port context of TD and Lower layer +* \param event event type +* \param pParm1 Pointer to data associated with event +* \param pParm2 Pointer to data associated with event +* +* \return: none +* +* \note - For details, refer to SAS/SATA Low-Level API Specification +* +*****************************************************************************/ +osGLOBAL void ossaDiscoverSasCB(agsaRoot_t *agRoot, + agsaPortContext_t *agPortContext, + bit32 event, + void *pParm1, + void *pParm2 + ) +{ + return; +} +#endif + diff --git a/sys/dev/pms/RefTisa/tisa/sassata/common/tddefs.h b/sys/dev/pms/RefTisa/tisa/sassata/common/tddefs.h new file mode 100644 index 000000000000..91aadb32414f --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/common/tddefs.h @@ -0,0 +1,1309 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/*******************************************************************************/ +/** \file + * + * The file contains defines and data structures for SAS/SATA TD layer + * + */ + +#ifndef __TDDEFS_H__ +#define __TDDEFS_H__ + + + +#ifndef agTRUE +#define agTRUE 1 +#endif + +#ifndef agFALSE +#define agFALSE 0 +#endif + +#ifndef agNULL +#define agNULL ((void *)0) +#endif + +#ifndef IN +#define IN +#endif + +#ifndef OUT +#define OUT +#endif + +#ifndef IN_OUT +#define IN_OUT +#endif + +#ifndef os_bit8 +#define os_bit8 bit8 +#endif + +#ifndef os_bit16 +#define os_bit16 bit16 +#endif + +#ifndef os_bit32 +#define os_bit32 bit32 +#endif + +#ifndef OFF +#define OFF 0 +#endif + +#ifndef ON +#define ON 1 +#endif + +#ifndef MIN +#define MIN(a,b) ((a) < (b) ? (a) : (b)) +#endif + +#ifndef MAX +#define MAX(a,b) ((a) < (b) ? (b) : (a)) +#endif + +#define TD_OPERATION_INITIATOR 0x1 +#define TD_OPERATION_TARGET 0x2 + +/* indices for mem_t structures */ +#define DEK_MEM_INDEX_1 15 +#define DEK_MEM_INDEX_2 16 + +/* some useful macros */ +#ifndef AG_ALIGNSIZE +#define AG_ALIGNSIZE(count, alignment) (bit32) ( (bitptr)(count)+(bitptr)(alignment) ) +#endif + +#define DEFAULT_KEY_BUFFER_SIZE 64 + +/**< the default maximum number of phys */ +#ifdef FPGA_CARD + +#define TD_MAX_NUM_PHYS 2 + +#else +#define TD_MAX_NUM_PHYS 16 +#define TD_MAX_CARD_NUM 20 +#endif + +#define TD_CARD_ID_FREE 0 +#define TD_CARD_ID_ALLOC 1 +#define TD_CARD_ID_LEN 128 + +/**< the maximum number of port context */ +/* should be the number of phyical phys in chip + 1 */ +#define TD_MAX_PORT_CONTEXT 16 +/**< the maximum number of target device */ +/* For Initiator and Target + this is initial value for MaxTargets in the configuration(adj) file */ +#define DEFAULT_MAX_DEV 256 +/* the maximum number of interrupt coalesce context */ +#define TD_MAX_INT_COALESCE 512 + +#if (defined(__FreeBSD__)) +#define MAX_OUTSTANDING_IO_PER_LUN 64 +#else +#define MAX_OUTSTANDING_IO_PER_LUN 254 //64 +#endif + +/* default values */ +#define DEFAULT_MAX_ACTIVE_IOS 128 +#define DEFAULT_NUM_REG_CLIENTS 256 +#define DEFAULT_NUM_INBOUND_QUEUE 1 +#define DEFAULT_NUM_OUTBOUND_QUEUE 1 +#define DEFAULT_INBOUND_QUEUE_SIZE 512 +#define DEFAULT_INBOUND_QUEUE_ELE_SIZE 128 +#define DEFAULT_OUTBOUND_QUEUE_SIZE 512 +#define DEFAULT_OUTBOUND_QUEUE_ELE_SIZE 128 +#define DEFAULT_OUTBOUND_QUEUE_INTERRUPT_DELAY 0 +#define DEFAULT_OUTBOUND_QUEUE_INTERRUPT_COUNT 1 +#define DEFAULT_OUTBOUND_INTERRUPT_ENABLE 1 +#define DEFAULT_INBOUND_QUEUE_PRIORITY 0 +#define DEFAULT_QUEUE_OPTION 0 +#define DEFAULT_FW_MAX_PORTS 8 + + + +/* SAS device type definition. SAS spec(r.7) p206 */ +#define SAS_NO_DEVICE 0 +#define SAS_END_DEVICE 1 +#define SAS_EDGE_EXPANDER_DEVICE 2 +#define SAS_FANOUT_EXPANDER_DEVICE 3 + +/* routing attributes */ +#define SAS_ROUTING_DIRECT 0x00 +#define SAS_ROUTING_SUBTRACTIVE 0x01 +#define SAS_ROUTING_TABLE 0x02 + +#define SAS_CONNECTION_RATE_1_5G 0x08 +#define SAS_CONNECTION_RATE_3_0G 0x09 +#define SAS_CONNECTION_RATE_6_0G 0x0A +#define SAS_CONNECTION_RATE_12_0G 0x0B + +/**< defines the maximum number of expanders */ +#define TD_MAX_EXPANDER_PHYS 256 +/**< the maximum number of expanders at TD */ +#define TD_MAX_EXPANDER 128 + +/***************************************************************************** +** SCSI Operation Codes (first byte in CDB) +*****************************************************************************/ + + +#define SCSIOPC_TEST_UNIT_READY 0x00 +#define SCSIOPC_INQUIRY 0x12 +#define SCSIOPC_MODE_SENSE_6 0x1A +#define SCSIOPC_MODE_SENSE_10 0x5A +#define SCSIOPC_MODE_SELECT_6 0x15 +#define SCSIOPC_START_STOP_UNIT 0x1B +#define SCSIOPC_READ_CAPACITY_10 0x25 +#define SCSIOPC_READ_CAPACITY_16 0x9E +#define SCSIOPC_READ_6 0x08 +#define SCSIOPC_READ_10 0x28 +#define SCSIOPC_READ_12 0xA8 +#define SCSIOPC_READ_16 0x88 +#define SCSIOPC_WRITE_6 0x0A +#define SCSIOPC_WRITE_10 0x2A +#define SCSIOPC_WRITE_12 0xAA +#define SCSIOPC_WRITE_16 0x8A +#define SCSIOPC_WRITE_VERIFY 0x2E +#define SCSIOPC_VERIFY_10 0x2F +#define SCSIOPC_VERIFY_12 0xAF +#define SCSIOPC_VERIFY_16 0x8F +#define SCSIOPC_REQUEST_SENSE 0x03 +#define SCSIOPC_REPORT_LUN 0xA0 +#define SCSIOPC_FORMAT_UNIT 0x04 +#define SCSIOPC_SEND_DIAGNOSTIC 0x1D +#define SCSIOPC_WRITE_SAME_10 0x41 +#define SCSIOPC_WRITE_SAME_16 0x93 +#define SCSIOPC_READ_BUFFER 0x3C +#define SCSIOPC_WRITE_BUFFER 0x3B + +#define SCSIOPC_GET_CONFIG 0x46 +#define SCSIOPC_GET_EVENT_STATUS_NOTIFICATION 0x4a +#define SCSIOPC_REPORT_KEY 0xA4 +#define SCSIOPC_SEND_KEY 0xA3 +#define SCSIOPC_READ_DVD_STRUCTURE 0xAD +#define SCSIOPC_TOC 0x43 +#define SCSIOPC_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E +#define SCSIOPC_READ_VERIFY 0x42 + +#define SCSIOPC_LOG_SENSE 0x4D +#define SCSIOPC_LOG_SELECT 0x4C +#define SCSIOPC_MODE_SELECT_6 0x15 +#define SCSIOPC_MODE_SELECT_10 0x55 +#define SCSIOPC_SYNCHRONIZE_CACHE_10 0x35 +#define SCSIOPC_SYNCHRONIZE_CACHE_16 0x91 +#define SCSIOPC_WRITE_AND_VERIFY_10 0x2E +#define SCSIOPC_WRITE_AND_VERIFY_12 0xAE +#define SCSIOPC_WRITE_AND_VERIFY_16 0x8E +#define SCSIOPC_READ_MEDIA_SERIAL_NUMBER 0xAB +#define SCSIOPC_REASSIGN_BLOCKS 0x07 + + + + + +/***************************************************************************** +** SCSI GENERIC 6 BYTE CDB +*****************************************************************************/ +typedef struct CBD6_s { + bit8 opcode; + bit8 rsv; /* not 100% correct */ + bit8 lba[2]; /* not 100% correct */ + bit8 len; + bit8 control; +} CDB6_t; + + + +/***************************************************************************** +** SCSI GENERIC 10 BYTE CDB +*****************************************************************************/ +typedef struct CBD10_s { + bit8 opcode; + bit8 rsv_service; + bit8 lba[4]; + bit8 rsv; + bit8 len[2]; + bit8 control; +} CDB10_t; + +/***************************************************************************** +** SCSI GENERIC 12 BYTE CDB +*****************************************************************************/ +typedef struct CBD12_s { + bit8 opcode; + bit8 rsv_service; + bit8 lba[4]; + bit8 len[4]; + bit8 rsv; + bit8 control; +} CDB12_t; + + +/***************************************************************************** +** SCSI GENERIC 16 BYTE CDB +*****************************************************************************/ +typedef struct CBD16_s { + bit8 opcode; + bit8 rsv_service; + bit8 lba[4]; + bit8 add_cdb[4]; + bit8 len[4]; + bit8 rsv; + bit8 control; +} CDB16_t; + +#define BLOCK_BYTE_LENGTH 512 + +/***************************************************************************** +** SCSI STATUS BYTES +*****************************************************************************/ + +#define SCSI_STATUS_GOOD 0x00 +#define SCSI_STATUS_CHECK_CONDITION 0x02 +#define SCSI_STATUS_BUSY 0x08 +#define SCSI_STATUS_COMMAND_TERMINATED 0x22 +#define SCSI_STATUS_TASK_SET_FULL 0x28 + +/***************************************************************************** +** SAS TM Function data present see SAS spec p311 Table 109 (Revision 7) +*****************************************************************************/ +#define NO_DATA 0 +#define RESPONSE_DATA 1 +#define SENSE_DATA 2 + +/* 4 bytes, SAS spec p312 Table 110 (Revision 7) */ +#define RESPONSE_DATA_LEN 4 + +#define SAS_CMND 0 +#define SAS_TM 1 + +/* SMP frame type */ +#define SMP_REQUEST 0x40 +#define SMP_RESPONSE 0x41 + +#define SMP_INITIATOR 0x01 +#define SMP_TARGET 0x02 + +/* default SMP timeout: 0xFFFF is the Maximum Allowed */ +#define DEFAULT_SMP_TIMEOUT 0xFFFF + +/* SMP direct payload size limit: IOMB direct payload size = 48 */ +#define SMP_DIRECT_PAYLOAD_LIMIT 44 + +/* SMP function */ +#define SMP_REPORT_GENERAL 0x00 +#define SMP_REPORT_MANUFACTURE_INFORMATION 0x01 +#define SMP_READ_GPIO_REGISTER 0x02 +#define SMP_DISCOVER 0x10 +#define SMP_REPORT_PHY_ERROR_LOG 0x11 +#define SMP_REPORT_PHY_SATA 0x12 +#define SMP_REPORT_ROUTING_INFORMATION 0x13 +#define SMP_WRITE_GPIO_REGISTER 0x82 +#define SMP_CONFIGURE_ROUTING_INFORMATION 0x90 +#define SMP_PHY_CONTROL 0x91 +#define SMP_PHY_TEST_FUNCTION 0x92 +#define SMP_PMC_SPECIFIC 0xC0 + + +/* SMP function results */ +#define SMP_FUNCTION_ACCEPTED 0x00 +#define UNKNOWN_SMP_FUNCTION 0x01 +#define SMP_FUNCTION_FAILED 0x02 +#define INVALID_REQUEST_FRAME_LENGTH 0x03 +#define INVALID_EXPANDER_CHANGE_COUNT 0x04 +#define SMP_FN_BUSY 0x05 +#define INCOMPLETE_DESCRIPTOR_LIST 0x06 +#define PHY_DOES_NOT_EXIST 0x10 +#define INDEX_DOES_NOT_EXIST 0x11 +#define PHY_DOES_NOT_SUPPORT_SATA 0x12 +#define UNKNOWN_PHY_OPERATION 0x13 +#define UNKNOWN_PHY_TEST_FUNCTION 0x14 +#define PHY_TEST_FUNCTION_IN_PROGRESS 0x15 +#define PHY_VACANT 0x16 +#define UNKNOWN_PHY_EVENT_SOURCE 0x17 +#define UNKNOWN_DESCRIPTOT_TYPE 0x18 +#define UNKNOWN_PHY_FILETER 0x19 +#define AFFILIATION_VIOLATION 0x1A +#define SMP_ZONE_VIOLATION 0x20 +#define NO_MANAGEMENT_ACCESS_RIGHTS 0x21 +#define UNKNOWN_ENABLE_DISABLE_ZONING_VALUE 0x22 +#define ZONE_LOCK_VIOLATION 0x23 +#define NOT_ACTIVATED 0x24 +#define ZONE_GROUP_OUT_OF_RANGE 0x25 +#define NO_PHYSICAL_PRESENCE 0x26 +#define SAVING_NOT_SUPPORTED 0x27 +#define SOURCE_ZONE_GROUP_DOES_NOT_EXIST 0x28 +#define DISABLED_PASSWORD_NOT_SUPPORTED 0x29 + +/* SMP PHY CONTROL OPERATION */ +#define SMP_PHY_CONTROL_NOP 0x00 +#define SMP_PHY_CONTROL_LINK_RESET 0x01 +#define SMP_PHY_CONTROL_HARD_RESET 0x02 +#define SMP_PHY_CONTROL_DISABLE 0x03 +#define SMP_PHY_CONTROL_CLEAR_ERROR_LOG 0x05 +#define SMP_PHY_CONTROL_CLEAR_AFFILIATION 0x06 +#define SMP_PHY_CONTROL_XMIT_SATA_PS_SIGNAL 0x07 + + +#define IT_NEXUS_TIMEOUT 0x7D0 /* 2000 ms; old value was 0xFFFF */ + +#define PORT_RECOVERY_TIMEOUT ((IT_NEXUS_TIMEOUT/100) + 30) /* 5000 ms; in 100ms; should be large than IT_NEXUS_TIMEOUT */ + +#define STP_IDLE_TIME 5 /* 5 us; the defaulf of the controller */ + +#define SET_ESGL_EXTEND(val) \ + ((val) = (val) | 0x80000000) + +#define CLEAR_ESGL_EXTEND(val) \ + ((val) = (val) & 0x7FFFFFFF) + +#define DEVINFO_GET_SAS_ADDRESSLO(devInfo) \ + DMA_BEBIT32_TO_BIT32(*(bit32 *)(devInfo)->sasAddressLo) + +#define DEVINFO_GET_SAS_ADDRESSHI(devInfo) \ + DMA_BEBIT32_TO_BIT32(*(bit32 *)(devInfo)->sasAddressHi) + +/* this macro is based on SAS spec, not sTSDK 0xC0 */ +#define DEVINFO_GET_DEVICETTYPE(devInfo) \ + (((devInfo)->devType_S_Rate & 0xC0) >> 6) + +#define DEVINFO_GET_LINKRATE(devInfo) \ + ((devInfo)->devType_S_Rate & 0x0F) + +#define DEVINFO_GET_EXT_MCN(devInfo) \ + (((devInfo)->ext & 0x7800) >> 11) + + +#define DEVINFO_PUT_SMPTO(devInfo, smpto) \ + ((devInfo)->smpTimeout) = smpto + +#define DEVINFO_PUT_ITNEXUSTO(devInfo, itnexusto) \ + ((devInfo)->it_NexusTimeout) = itnexusto + +#define DEVINFO_PUT_FBS(devInfo, fbs) \ + ((devInfo)->firstBurstSize) = fbs + +#define DEVINFO_PUT_FLAG(devInfo, tlr) \ + ((devInfo)->flag) = tlr + +#define DEVINFO_PUT_DEV_S_RATE(devInfo, dev_s_rate) \ + ((devInfo)->devType_S_Rate) = dev_s_rate + +#define DEVINFO_PUT_SAS_ADDRESSLO(devInfo, src32) \ + *(bit32 *)((devInfo)->sasAddressLo) = BIT32_TO_DMA_BEBIT32(src32) + +#define DEVINFO_PUT_SAS_ADDRESSHI(devInfo, src32) \ + *(bit32 *)((devInfo)->sasAddressHi) = BIT32_TO_DMA_BEBIT32(src32) + +#define DEVICE_SSP_BIT 0x8 /* SSP Initiator port */ +#define DEVICE_STP_BIT 0x4 /* STP Initiator port */ +#define DEVICE_SMP_BIT 0x2 /* SMP Initiator port */ +#define DEVICE_SATA_BIT 0x1 /* SATA device, valid in the discovery response only */ + +#define DEVICE_IS_SSP_INITIATOR(DeviceData) \ + (((DeviceData)->initiator_ssp_stp_smp & DEVICE_SSP_BIT) == DEVICE_SSP_BIT) + +#define DEVICE_IS_STP_INITIATOR(DeviceData) \ + (((DeviceData)->initiator_ssp_stp_smp & DEVICE_STP_BIT) == DEVICE_STP_BIT) + +#define DEVICE_IS_SMP_INITIATOR(DeviceData) \ + (((DeviceData)->initiator_ssp_stp_smp & DEVICE_SMP_BIT) == DEVICE_SMP_BIT) + +#define DEVICE_IS_SSP_TARGET(DeviceData) \ + (((DeviceData)->target_ssp_stp_smp & DEVICE_SSP_BIT) == DEVICE_SSP_BIT) + +#define DEVICE_IS_STP_TARGET(DeviceData) \ + (((DeviceData)->target_ssp_stp_smp & DEVICE_STP_BIT) == DEVICE_STP_BIT) + +#define DEVICE_IS_SMP_TARGET(DeviceData) \ + (((DeviceData)->target_ssp_stp_smp & DEVICE_SMP_BIT) == DEVICE_SMP_BIT) + +#define DEVICE_IS_SATA_DEVICE(DeviceData) \ + (((DeviceData)->target_ssp_stp_smp & DEVICE_SATA_BIT) == DEVICE_SATA_BIT) + + + + +/* Negotiated Phyical Link Rate +#define Phy_ENABLED_UNKNOWN +*/ +/* old SMP header definition */ +typedef struct tdssSMPFrameHeader_s +{ + bit8 smpFrameType; /* The first byte of SMP frame represents the SMP FRAME TYPE */ + bit8 smpFunction; /* The second byte of the SMP frame represents the SMP FUNCTION */ + bit8 smpFunctionResult; /* The third byte of SMP frame represents FUNCTION RESULT of the SMP response. */ + bit8 smpReserved; /* reserved */ +} tdssSMPFrameHeader_t; + +/**************************************************************** + * report general request + ****************************************************************/ +#ifdef FOR_COMPLETENESS +typedef struct smpReqReportGeneral_s +{ + /* nothing. some compiler disallowed structure with no member */ +} smpReqReportGeneral_t; +#endif + +/**************************************************************** + * report general response + ****************************************************************/ +#define REPORT_GENERAL_CONFIGURING_BIT 0x2 +#define REPORT_GENERAL_CONFIGURABLE_BIT 0x1 + +typedef struct smpRespReportGeneral_s +{ + bit8 expanderChangeCount16[2]; + bit8 expanderRouteIndexes16[2]; + bit8 reserved1; + bit8 numOfPhys; + bit8 configuring_configurable; + /* B7-2 : reserved */ + /* B1 : configuring */ + /* B0 : configurable */ + bit8 reserved4[17]; +} smpRespReportGeneral_t; + +#define REPORT_GENERAL_IS_CONFIGURING(pResp) \ + (((pResp)->configuring_configurable & REPORT_GENERAL_CONFIGURING_BIT) == \ + REPORT_GENERAL_CONFIGURING_BIT) + +#define REPORT_GENERAL_IS_CONFIGURABLE(pResp) \ + (((pResp)->configuring_configurable & REPORT_GENERAL_CONFIGURABLE_BIT) == \ + REPORT_GENERAL_CONFIGURABLE_BIT) + +#define REPORT_GENERAL_GET_ROUTEINDEXES(pResp) \ + DMA_BEBIT16_TO_BIT16(*(bit16 *)((pResp)->expanderRouteIndexes16)) + + +/**************************************************************** + * report manufacturer info response + ****************************************************************/ +typedef struct smpRespReportManufactureInfo_s +{ + bit8 reserved1[8]; + bit8 vendorIdentification[8]; + bit8 productIdentification[16]; + bit8 productRevisionLevel[4]; + bit8 vendorSpecific[20]; +} smpRespReportManufactureInfo_t; + +/**************************************************************** + * discover request + ****************************************************************/ +typedef struct smpReqDiscover_s +{ + bit32 reserved1; + bit8 reserved2; + bit8 phyIdentifier; + bit8 ignored; + bit8 reserved3; +} smpReqDiscover_t; + +/**************************************************************** + * discover response + ****************************************************************/ +typedef struct smpRespDiscover_s +{ + bit8 reserved1[4]; + bit8 reserved2; + bit8 phyIdentifier; + bit8 reserved3[2]; + bit8 attachedDeviceType; + /* B7 : reserved */ + /* B6-4 : attachedDeviceType */ + /* B3-0 : reserved */ + bit8 negotiatedPhyLinkRate; + /* B7-4 : reserved */ + /* B3-0 : negotiatedPhyLinkRate */ + bit8 attached_Ssp_Stp_Smp_Sata_Initiator; + /* B7-4 : reserved */ + /* B3 : attachedSspInitiator */ + /* B2 : attachedStpInitiator */ + /* B1 : attachedSmpInitiator */ + /* B0 : attachedSataHost */ + bit8 attached_SataPS_Ssp_Stp_Smp_Sata_Target; + /* B7 : attachedSataPortSelector */ + /* B6-4 : reserved */ + /* B3 : attachedSspTarget */ + /* B2 : attachedStpTarget */ + /* B1 : attachedSmpTarget */ + /* B0 : attachedSatadevice */ + bit8 sasAddressHi[4]; + bit8 sasAddressLo[4]; + bit8 attachedSasAddressHi[4]; + bit8 attachedSasAddressLo[4]; + bit8 attachedPhyIdentifier; + bit8 reserved9[7]; + bit8 programmedAndHardware_MinPhyLinkRate; + /* B7-4 : programmedMinPhyLinkRate */ + /* B3-0 : hardwareMinPhyLinkRate */ + bit8 programmedAndHardware_MaxPhyLinkRate; + /* B7-4 : programmedMaxPhyLinkRate */ + /* B3-0 : hardwareMaxPhyLinkRate */ + bit8 phyChangeCount; + bit8 virtualPhy_partialPathwayTimeout; + /* B7 : virtualPhy*/ + /* B6-4 : reserved */ + /* B3-0 : partialPathwayTimeout */ + bit8 routingAttribute; + /* B7-4 : reserved */ + /* B3-0 : routingAttribute */ + bit8 reserved13[5]; + bit8 vendorSpecific[2]; +} smpRespDiscover_t; + +#define DISCRSP_SSP_BIT 0x08 +#define DISCRSP_STP_BIT 0x04 +#define DISCRSP_SMP_BIT 0x02 +#define DISCRSP_SATA_BIT 0x01 + +#define DISCRSP_SATA_PS_BIT 0x80 + +#define DISCRSP_GET_ATTACHED_DEVTYPE(pResp) \ + (((pResp)->attachedDeviceType & 0x70) >> 4) +#define DISCRSP_GET_LINKRATE(pResp) \ + ((bit8)((pResp)->negotiatedPhyLinkRate & 0x0F)) + +#define DISCRSP_IS_SSP_INITIATOR(pResp) \ + (((pResp)->attached_Ssp_Stp_Smp_Sata_Initiator & DISCRSP_SSP_BIT) == DISCRSP_SSP_BIT) +#define DISCRSP_IS_STP_INITIATOR(pResp) \ + (((pResp)->attached_Ssp_Stp_Smp_Sata_Initiator & DISCRSP_STP_BIT) == DISCRSP_STP_BIT) +#define DISCRSP_IS_SMP_INITIATOR(pResp) \ + (((pResp)->attached_Ssp_Stp_Smp_Sata_Initiator & DISCRSP_SMP_BIT) == DISCRSP_SMP_BIT) +#define DISCRSP_IS_SATA_HOST(pResp) \ + (((pResp)->attached_Ssp_Stp_Smp_Sata_Initiator & DISCRSP_SATA_BIT) == DISCRSP_SATA_BIT) + +#define DISCRSP_IS_SSP_TARGET(pResp) \ + (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & DISCRSP_SSP_BIT) == DISCRSP_SSP_BIT) +#define DISCRSP_IS_STP_TARGET(pResp) \ + (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & DISCRSP_STP_BIT) == DISCRSP_STP_BIT) +#define DISCRSP_IS_SMP_TARGET(pResp) \ + (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & DISCRSP_SMP_BIT) == DISCRSP_SMP_BIT) +#define DISCRSP_IS_SATA_DEVICE(pResp) \ + (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & DISCRSP_SATA_BIT) == DISCRSP_SATA_BIT) +#define DISCRSP_IS_SATA_PORTSELECTOR(pResp) \ + (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & DISCRSP_SATA_PS_BIT) == DISCRSP_SATA_PS_BIT) + +#define DISCRSP_GET_SAS_ADDRESSHI(pResp) \ + DMA_BEBIT32_TO_BIT32(*(bit32 *)(pResp)->sasAddressHi) +#define DISCRSP_GET_SAS_ADDRESSLO(pResp) \ + DMA_BEBIT32_TO_BIT32(*(bit32 *)(pResp)->sasAddressLo) + +#define DISCRSP_GET_ATTACHED_SAS_ADDRESSHI(pResp) \ + DMA_BEBIT32_TO_BIT32(*(bit32 *)(pResp)->attachedSasAddressHi) +#define DISCRSP_GET_ATTACHED_SAS_ADDRESSLO(pResp) \ + DMA_BEBIT32_TO_BIT32(*(bit32 *)(pResp)->attachedSasAddressLo) + +#define DISCRSP_VIRTUALPHY_BIT 0x80 +#define DISCRSP_IS_VIRTUALPHY(pResp) \ + (((pResp)->virtualPhy_partialPathwayTimeout & DISCRSP_VIRTUALPHY_BIT) == DISCRSP_VIRTUALPHY_BIT) + +#define DISCRSP_GET_ROUTINGATTRIB(pResp) \ + ((bit8)((pResp)->routingAttribute & 0x0F)) + +/**************************************************************** + * report route table request + ****************************************************************/ +typedef struct smpReqReportRouteTable_s +{ + bit8 reserved1[2]; + bit8 expanderRouteIndex16[20]; + bit8 reserved2; + bit8 phyIdentifier; + bit8 reserved3[2]; +} smpReqReportRouteTable_t; + +/**************************************************************** + * report route response + ****************************************************************/ +typedef struct smpRespReportRouteTable_s +{ + bit8 reserved1[2]; + bit8 expanderRouteIndex16[2]; + bit8 reserved2; + bit8 phyIdentifier; + bit8 reserved3[2]; + bit8 disabled; + /* B7 : expander route entry disabled */ + /* B6-0 : reserved */ + bit8 reserved5[3]; + bit8 routedSasAddressHi32[4]; + bit8 routedSasAddressLo32[4]; + bit8 reserved6[16]; +} smpRespReportRouteTable_t; + +/**************************************************************** + * configure route information request + ****************************************************************/ +typedef struct smpReqConfigureRouteInformation_s +{ + bit8 reserved1[2]; + bit8 expanderRouteIndex[2]; + bit8 reserved2; + bit8 phyIdentifier; + bit8 reserved3[2]; + bit8 disabledBit_reserved4; + bit8 reserved5[3]; + bit8 routedSasAddressHi[4]; + bit8 routedSasAddressLo[4]; + bit8 reserved6[16]; +} smpReqConfigureRouteInformation_t; + +/**************************************************************** + * configure route response + ****************************************************************/ +#ifdef FOR_COMPLETENESS +typedef struct smpRespConfigureRouteInformation_s +{ + /* nothing. some compiler disallowed structure with no member */ +} smpRespConfigureRouteInformation_t; +#endif + +/**************************************************************** + * report Phy Sata request + ****************************************************************/ +typedef struct smpReqReportPhySata_s +{ + bit8 reserved1[4]; + bit8 reserved2; + bit8 phyIdentifier; + bit8 reserved3[2]; +} smpReqReportPhySata_t; + +/**************************************************************** + * report Phy Sata response + ****************************************************************/ +typedef struct smpRespReportPhySata_s +{ + bit8 reserved1[4]; + bit8 reserved2; + bit8 phyIdentifier; + bit8 reserved3; + bit8 affiliations_sup_valid; + /* b7-2 : reserved */ + /* b1 : Affiliations supported */ + /* b0 : Affiliation valid */ + bit8 reserved5[4]; + bit8 stpSasAddressHi[4]; + bit8 stpSasAddressLo[4]; + bit8 regDevToHostFis[20]; + bit8 reserved6[4]; + bit8 affiliatedStpInitiatorSasAddressHi[4]; + bit8 affiliatedStpInitiatorSasAddressLo[4]; +} smpRespReportPhySata_t; + + +/**************************************************************** + * Phy Control request + ****************************************************************/ +typedef struct smpReqPhyControl_s +{ + bit8 reserved1[4]; + bit8 reserved2; + bit8 phyIdentifier; + bit8 phyOperation; + bit8 updatePartialPathwayTOValue; + /* b7-1 : reserved */ + /* b0 : update partial pathway timeout value */ + bit8 reserved3[20]; + bit8 programmedMinPhysicalLinkRate; + /* b7-4 : programmed Minimum Physical Link Rate*/ + /* b3-0 : reserved */ + bit8 programmedMaxPhysicalLinkRate; + /* b7-4 : programmed Maximum Physical Link Rate*/ + /* b3-0 : reserved */ + bit8 reserved4[2]; + bit8 partialPathwayTOValue; + /* b7-4 : reserved */ + /* b3-0 : partial Pathway TO Value */ + bit8 reserved5[3]; +} smpReqPhyControl_t; + +/**************************************************************** + * Phy Control response + ****************************************************************/ +#ifdef FOR_COMPLETENESS +typedef struct smpRespPhyControl_s +{ + /* nothing. some compiler disallowed structure with no member */ +} smpRespPhyControl_t; +#endif + + +/***************************************************************************** +** SCSI SENSE KEY VALUES +*****************************************************************************/ + +#define SCSI_SNSKEY_NO_SENSE 0x00 +#define SCSI_SNSKEY_RECOVERED_ERROR 0x01 +#define SCSI_SNSKEY_NOT_READY 0x02 +#define SCSI_SNSKEY_MEDIUM_ERROR 0x03 +#define SCSI_SNSKEY_HARDWARE_ERROR 0x04 +#define SCSI_SNSKEY_ILLEGAL_REQUEST 0x05 +#define SCSI_SNSKEY_UNIT_ATTENTION 0x06 +#define SCSI_SNSKEY_DATA_PROTECT 0x07 +#define SCSI_SNSKEY_ABORTED_COMMAND 0x0B +#define SCSI_SNSKEY_MISCOMPARE 0x0E + +/***************************************************************************** +** SCSI Additional Sense Codes and Qualifiers combo two-bytes +*****************************************************************************/ + +#define SCSI_SNSCODE_NO_ADDITIONAL_INFO 0x0000 +#define SCSI_SNSCODE_LUN_CRC_ERROR_DETECTED 0x0803 +#define SCSI_SNSCODE_INVALID_COMMAND 0x2000 +#define SCSI_SNSCODE_LOGICAL_BLOCK_OUT 0x2100 +#define SCSI_SNSCODE_INVALID_FIELD_IN_CDB 0x2400 +#define SCSI_SNSCODE_LOGICAL_NOT_SUPPORTED 0x2500 +#define SCSI_SNSCODE_POWERON_RESET 0x2900 +#define SCSI_SNSCODE_EVERLAPPED_CMDS 0x4e00 +#define SCSI_SNSCODE_INTERNAL_TARGET_FAILURE 0x4400 +#define SCSI_SNSCODE_MEDIUM_NOT_PRESENT 0x3a00 +#define SCSI_SNSCODE_UNRECOVERED_READ_ERROR 0x1100 +#define SCSI_SNSCODE_RECORD_NOT_FOUND 0x1401 +#define SCSI_SNSCODE_NOT_READY_TO_READY_CHANGE 0x2800 +#define SCSI_SNSCODE_OPERATOR_MEDIUM_REMOVAL_REQUEST 0x5a01 +#define SCSI_SNSCODE_INFORMATION_UNIT_CRC_ERROR 0x4703 +#define SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_FORMAT_IN_PROGRESS 0x0404 +#define SCSI_SNSCODE_HARDWARE_IMPENDING_FAILURE 0x5d10 +#define SCSI_SNSCODE_LOW_POWER_CONDITION_ON 0x5e00 +#define SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_INIT_REQUIRED 0x0402 +#define SCSI_SNSCODE_INVALID_FIELD_PARAMETER_LIST 0x2600 +#define SCSI_SNSCODE_ATA_DEVICE_FAILED_SET_FEATURES 0x4471 +#define SCSI_SNSCODE_ATA_DEVICE_FEATURE_NOT_ENABLED 0x670B +#define SCSI_SNSCODE_LOGICAL_UNIT_FAILED_SELF_TEST 0x3E03 +#define SCSI_SNSCODE_COMMAND_SEQUENCE_ERROR 0x2C00 +#define SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE 0x2100 +#define SCSI_SNSCODE_LOGICAL_UNIT_FAILURE 0x3E01 +#define SCSI_SNSCODE_MEDIA_LOAD_OR_EJECT_FAILED 0x5300 +#define SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_INITIALIZING_COMMAND_REQUIRED 0x0402 +#define SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_CAUSE_NOT_REPORTABLE 0x0400 +#define SCSI_SNSCODE_LOGICAL_UNIT_DOES_NOT_RESPOND_TO_SELECTION 0x0500 +#define SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN 0x4000 +#define SCSI_SNSCODE_COMMANDS_CLEARED_BY_ANOTHER_INITIATOR 0x2F00 +#define SCSI_SNSCODE_WRITE_ERROR_AUTO_REALLOCATION_FAILED 0x0C02 +/***************************************************************************** +** SCSI Additional Sense Codes and Qualifiers saparate bytes +*****************************************************************************/ + +#define SCSI_ASC_NOTREADY_INIT_CMD_REQ 0x04 +#define SCSI_ASCQ_NOTREADY_INIT_CMD_REQ 0x02 + + +/***************************************************************************** +** Inquiry command fields and response sizes +*****************************************************************************/ +#define SCSIOP_INQUIRY_CMDDT 0x02 +#define SCSIOP_INQUIRY_EVPD 0x01 +#define STANDARD_INQUIRY_SIZE 36 +#define SATA_PAGE83_INQUIRY_WWN_SIZE 16 /* SAT, revision8, Table81, p78, 12 + 4 */ +#define SATA_PAGE83_INQUIRY_NO_WWN_SIZE 76 /* SAT, revision8, Table81, p78, 72 + 4 */ +#define SATA_PAGE89_INQUIRY_SIZE 572 /* SAT, revision8, Table87, p84 */ +#define SATA_PAGE0_INQUIRY_SIZE 8 /* SPC-4, 7.6.9 Table331, p345 */ +#define SATA_PAGE80_INQUIRY_SIZE 24 /* SAT, revision8, Table79, p77 */ + + +/* not sure here */ +/* define byte swap macro */ +#define AGSA_FLIP_2_BYTES(_x) ((bit16)(((((bit16)(_x))&0x00FF)<<8)| \ + ((((bit16)(_x))&0xFF00)>>8))) + +#define AGSA_FLIP_4_BYTES(_x) ((bit32)(((((bit32)(_x))&0x000000FF)<<24)| \ + ((((bit32)(_x))&0x0000FF00)<<8)| \ + ((((bit32)(_x))&0x00FF0000)>>8)| \ + ((((bit32)(_x))&0xFF000000)>>24))) + + +/********************************************************************* +** BUFFER CONVERTION MACROS +*********************************************************************/ + +/********************************************************************* +* CPU buffer access macro * +* * +*/ + +#define OSSA_OFFSET_OF(STRUCT_TYPE, FEILD) \ + (bitptr)&(((STRUCT_TYPE *)0)->FEILD) + + +#if defined(SA_CPU_LITTLE_ENDIAN) + +#define OSSA_WRITE_LE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ + (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit16)(VALUE16); + +#define OSSA_WRITE_LE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ + (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit32)(VALUE32); + +#define OSSA_READ_LE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ + (*((bit16 *)ADDR16)) = (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) + +#define OSSA_READ_LE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ + (*((bit32 *)ADDR32)) = (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) + +#define OSSA_WRITE_BE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)((((bit16)VALUE16)>>8)&0xFF); \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)(((bit16)VALUE16)&0xFF); + +#define OSSA_WRITE_BE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)((((bit32)VALUE32)>>24)&0xFF); \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>8)&0xFF); \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)(((bit32)VALUE32)&0xFF); + +#define OSSA_READ_BE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ + (*(bit8 *)(((bit8 *)ADDR16)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ + (*(bit8 *)(((bit8 *)ADDR16))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); + +#define OSSA_READ_BE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ + (*(bit8 *)(((bit8 *)ADDR32)+3)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ + (*(bit8 *)(((bit8 *)ADDR32)+2)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); \ + (*(bit8 *)(((bit8 *)ADDR32)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))); \ + (*(bit8 *)(((bit8 *)ADDR32))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))); + +#define OSSA_WRITE_BYTE_STRING(AGROOT, DEST_ADDR, SRC_ADDR, LEN) \ + si_memcpy(DEST_ADDR, SRC_ADDR, LEN); + + +#elif defined(SA_CPU_BIG_ENDIAN) + +#define OSSA_WRITE_LE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit16)VALUE16)>>8)&0xFF); \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)(((bit16)VALUE16)&0xFF); + +#define OSSA_WRITE_LE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)((((bit32)VALUE32)>>24)&0xFF); \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>8)&0xFF); \ + (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)(((bit32)VALUE32)&0xFF); + +#define OSSA_READ_LE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ + (*(bit8 *)(((bit8 *)ADDR16)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ + (*(bit8 *)(((bit8 *)ADDR16))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); + +#define OSSA_READ_LE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ + (*((bit8 *)(((bit8 *)ADDR32)+3))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ + (*((bit8 *)(((bit8 *)ADDR32)+2))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); \ + (*((bit8 *)(((bit8 *)ADDR32)+1))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))); \ + (*((bit8 *)(((bit8 *)ADDR32)))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))); + +#define OSSA_WRITE_BE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ + (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit16)(VALUE16); + +#define OSSA_WRITE_BE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ + (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit32)(VALUE32); + +#define OSSA_READ_BE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ + (*((bit16 *)ADDR16)) = (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); + +#define OSSA_READ_BE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ + (*((bit32 *)ADDR32)) = (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); + +#define OSSA_WRITE_BYTE_STRING(AGROOT, DEST_ADDR, SRC_ADDR, LEN) \ + si_memcpy(DEST_ADDR, SRC_ADDR, LEN); + +#else + +#error (Host CPU endianess undefined!!) + +#endif + + +#if defined(SA_CPU_LITTLE_ENDIAN) + +#ifndef LEBIT16_TO_BIT16 +#define LEBIT16_TO_BIT16(_x) (_x) +#endif + +#ifndef BIT16_TO_LEBIT16 +#define BIT16_TO_LEBIT16(_x) (_x) +#endif + +#ifndef BIT16_TO_BEBIT16 +#define BIT16_TO_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x) +#endif + +#ifndef BEBIT16_TO_BIT16 +#define BEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x) +#endif + +#ifndef LEBIT32_TO_BIT32 +#define LEBIT32_TO_BIT32(_x) (_x) +#endif + +#ifndef BIT32_TO_LEBIT32 +#define BIT32_TO_LEBIT32(_x) (_x) +#endif + + +#ifndef BEBIT32_TO_BIT32 +#define BEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x) +#endif + +#ifndef BIT32_TO_BEBIT32 +#define BIT32_TO_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x) +#endif + +#elif defined(SA_CPU_BIG_ENDIAN) + +#ifndef LEBIT16_TO_BIT16 +#define LEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x) +#endif + +#ifndef BIT16_TO_LEBIT16 +#define BIT16_TO_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x) +#endif + +#ifndef BIT16_TO_BEBIT16 +#define BIT16_TO_BEBIT16(_x) (_x) +#endif + +#ifndef BEBIT16_TO_BIT16 +#define BEBIT16_TO_BIT16(_x) (_x) +#endif + +#ifndef LEBIT32_TO_BIT32 +#define LEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x) +#endif + +#ifndef BIT32_TO_LEBIT32 +#define BIT32_TO_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x) +#endif + +#ifndef BEBIT32_TO_BIT32 +#define BEBIT32_TO_BIT32(_x) (_x) +#endif + +#ifndef BIT32_TO_BEBIT32 +#define BIT32_TO_BEBIT32(_x) (_x) +#endif + +#else + +#error No definition of SA_CPU_BIG_ENDIAN or SA_CPU_LITTLE_ENDIAN + +#endif + + +#define TargetUnknown 0 +#define TargetRead 1 +#define TargetWrite 2 + + +#define CDB_GRP_MASK 0xE0 /* 1110 0000 */ +#define CDB_6BYTE 0x00 +#define CDB_10BYTE1 0x20 +#define CDB_10BYTE2 0x40 +#define CDB_12BYTE 0xA0 +#define CDB_16BYTE 0x80 + +/* ATA device type */ +#define SATA_ATA_DEVICE 0x01 /**< ATA ATA device type */ +#define SATA_ATAPI_DEVICE 0x02 /**< ATA ATAPI device type */ +#define SATA_PM_DEVICE 0x03 /**< ATA PM device type */ +#define SATA_SEMB_DEVICE 0x04 /**< ATA SEMB device type */ +#define SATA_SEMB_WO_SEP_DEVICE 0x05 /**< ATA SEMB without SEP device type */ +#define UNKNOWN_DEVICE 0xFF + +/**************************************************************** + * SATA Specification related defines * + ****************************************************************/ +#define SATA_MAX_QUEUED_COMMANDS 32 +#define SATA_MAX_PM_PORTS 15 + + +/* PMC IOCTL signature */ +#define PMC_IOCTL_SIGNATURE 0x1234 + + + +/* + * FIS type + */ +#define PIO_SETUP_DEV_TO_HOST_FIS 0x5F +#define REG_DEV_TO_HOST_FIS 0x34 +#define SET_DEV_BITS_FIS 0xA1 + +#define TD_ASSERT OS_ASSERT + +#ifdef TD_DISCOVER +#define TDSA_DISCOVERY_OPTION_FULL_START 0 +#define TDSA_DISCOVERY_OPTION_INCREMENTAL_START 1 +#define TDSA_DISCOVERY_OPTION_ABORT 2 + +#define TDSA_DISCOVERY_TYPE_SAS 0 +#define TDSA_DISCOVERY_TYPE_SATA 1 + + +#define DISCOVERY_TIMER_VALUE (2 * 1000 * 1000) /* 2 seconds */ +#define DISCOVERY_RETRIES 3 +#define CONFIGURE_ROUTE_TIMER_VALUE (1 * 1000 * 1000) /* 1 seconds */ +#define DEVICE_REGISTRATION_TIMER_VALUE (2 * 1000 * 1000) /* 2 seconds */ +#define SMP_RETRIES 5 +#define SMP_BUSY_TIMER_VALUE (1 * 1000 * 1000) /* 1 second */ +#define SMP_BUSY_RETRIES 5 +#define SATA_ID_DEVICE_DATA_TIMER_VALUE (3 * 1000 * 1000) /* 3 second */ +#define SATA_ID_DEVICE_DATA_RETRIES 3 +#define BC_TIMER_VALUE (5 * 1000 * 1000 ) /* 5 second */ +#define SMP_TIMER_VALUE (10 * 1000 * 1000) /* 10 second */ + +#endif +#define STP_DEVICE_TYPE 0 /* SATA behind expander 00*/ +#define SAS_DEVICE_TYPE 1 /* SSP or SMP 01 */ +#define SATA_DEVICE_TYPE 2 /* direct SATA 10 */ + +#define ATAPI_DEVICE_FLAG 0x200000 /* ATAPI device flag*/ + +#define TD_INTERNAL_TM_RESET 0xFF + +/* in terms of Kbytes*/ +#define HOST_EVENT_LOG_SIZE 128 +#define DEFAULT_EVENT_LOG_OPTION 3 + +/* Device state */ +#define SAT_DEV_STATE_NORMAL 0 /* Normal */ +#define SAT_DEV_STATE_IN_RECOVERY 1 /* SAT in recovery mode */ +#define SAT_DEV_STATE_FORMAT_IN_PROGRESS 2 /* Format unit in progress */ +#define SAT_DEV_STATE_SMART_THRESHOLD 3 /* SMART Threshold Exceeded Condition*/ +#define SAT_DEV_STATE_LOW_POWER 4 /* Low Power State*/ + +#define TD_GET_PHY_ID(input) (input & 0x0F) +#define TD_GET_PHY_NUMS(input) ((input & 0xF0) >> 4) +#define TD_GET_LINK_RATE(input) ((input & 0xFF00) >> 8) +#define TD_GET_PORT_STATE(input) ((input & 0xF0000) >> 16) +#define TD_GET_PHY_STATUS(input) ((input & 0xFF00) >> 8) +#define TD_GET_RESET_STATUS(input) ((input & 0xFF00) >> 8) + +#define TD_MAX_NUM_NOTIFY_SPINUP 20 + +#define SPC_VPD_SIGNATURE 0xFEDCBA98 + +#define TD_GET_FRAME_TYPE(input) (input & 0xFF) +#define TD_GET_TLR(input) ((input & 0x300) >> 8) + +/* PORT RESET TMO is in 100ms */ +#define SAS_PORT_RESET_TMO 3 /* 300 ms */ +#define SATA_PORT_RESET_TMO 80 /* 8000 ms = 8 sec */ +#define SAS_12G_PORT_RESET_TMO 8 /* 800 ms */ + +/* task attribute based on sTSDK API */ +#define TD_TASK_SIMPLE 0x0 /* Simple */ +#define TD_TASK_ORDERED 0x2 /* Ordered */ +#define TD_TASK_HEAD_OF_QUEUE 0x1 /* Head of Queue */ +#define TD_TASK_ACA 0x4 /* ACA */ + +/* compiler flag for direct smp */ +#define DIRECT_SMP +//#undef DIRECT_SMP + +#define CONFIGURE_FW_MAX_PORTS 0x20000000 + +#define NO_ACK 0xFFFF + +#define OPEN_RETRY_RETRIES 10 + +#ifdef AGTIAPI_CTL +/* scsi command/page */ +#define MODE_SELECT 0x15 +#define PAGE_FORMAT 0x10 +#define DR_MODE_PG_SZ 16 +#define DR_MODE_PG_CODE 0x02 +#define DR_MODE_PG_LENGTH 0x0e +#endif /* AGTIAPI_CTL */ + +enum td_locks_e +{ + /* for tdsaAllShared->FreeDeviceList, tdsaAllShared->MainDeviceList, + oneDeviceData->MainLink, oneDeviceData->FreeLink */ + TD_DEVICE_LOCK, + /* for tdsaAllShared->FreePortContextList, tdsaAllShared->MainPortContextList, + onePortContext->MainLink, onePortContext->FreeLink */ + TD_PORT_LOCK, + /* for onePortContext->discovery.discoveringExpanderList, + onePortContext->discovery.UpdiscoveringExpanderList, + tdsaAllShared->freeExpanderList */ + TD_DISC_LOCK, + /* for onePortContext->discovery.DiscoverySMPTimer, + oneDeviceData->SATAIDDeviceTimer, discovery->discoveryTimer, + discovery->SMPBusyTimer, discovery->BCTimer, + discovery->deviceRegistrationTimer, discovery->configureRouteTimer, + tdsaAllShared->itdsaIni->timerlist, tdsaAllShared->timerlist */ + TD_TIMER_LOCK, +#ifdef INITIATOR_DRIVER + /* for tdsaAllShared->pEsglAllInfo->freelist + tdsaAllShared->pEsglAllInfo->NumFreeEsglPages + tdsaAllShared->pEsglPageInfo->tdlist */ + TD_ESGL_LOCK, + /* for satIOContext->pSatDevData->satVerifyState, + satIOContext->pSatDevData->satSectorDone, + satIOContext->pSatDevData->satPendingNCQIO, + satIOContext->pSatDevData->satPendingIO, + satIOContext->pSatDevData->satPendingNONNCQIO, + satIOContext->pSatDevData->satFreeIntIoLinkList, + satIOContext->pSatDevData->satActiveIntIoLinkList, + satIOContext->pSatDevData->freeSATAFDMATagBitmap, + satIOContext->satIoContextLink, + oneDeviceData->satDevData.satIoLinkList */ + TD_SATA_LOCK, +#ifdef TD_INT_COALESCE + /* for tdsaIntCoalCxt->FreeLink, tdsaIntCoalCxt->MainLink, + tdsaIntCoalCxtHead->FreeLink, tdsaIntCoalCxtHead->MainLink */ + TD_INTCOAL_LOCK, +#endif +#endif +#ifdef TARGET_DRIVER + /* for tdsaAllShared->ttdsaTgt->ttdsaXchgData.xchgFreeList, + tdsaAllShared->ttdsaTgt->ttdsaXchgData.xchgBusyList */ + TD_TGT_LOCK, +#endif + TD_MAX_LOCKS +}; + +#define TD_GET_SAS_ADDRESSLO(sasAddressLo) \ + DMA_BEBIT32_TO_BIT32(*(bit32 *)sasAddressLo) + +#define TD_GET_SAS_ADDRESSHI(sasAddressHi) \ + DMA_BEBIT32_TO_BIT32(*(bit32 *)sasAddressHi) + +#define TD_XFER_RDY_PRIORTY_DEVICE_FLAG (1 << 22) + + +#ifdef FDS_DM +/* bit32 -> bit8 array[4] */ +#define PORTINFO_PUT_SAS_LOCAL_ADDRESSLO(portInfo, src32) \ + *(bit32 *)((portInfo)->sasLocalAddressLo) = BIT32_TO_DMA_BEBIT32(src32) + +#define PORTINFO_PUT_SAS_LOCAL_ADDRESSHI(portInfo, src32) \ + *(bit32 *)((portInfo)->sasLocalAddressHi) = BIT32_TO_DMA_BEBIT32(src32) +/* bit32 -> bit8 array[4] */ +#define PORTINFO_PUT_SAS_REMOTE_ADDRESSLO(portInfo, src32) \ + *(bit32 *)((portInfo)->sasRemoteAddressLo) = BIT32_TO_DMA_BEBIT32(src32) +#define PORTINFO_PUT_SAS_REMOTE_ADDRESSHI(portInfo, src32) \ + *(bit32 *)((portInfo)->sasRemoteAddressHi) = BIT32_TO_DMA_BEBIT32(src32) +#endif /* FDS_DM */ + +#ifdef FDS_SM +/* this applies to ID data and all other SATA IOs */ +#define SM_RETRIES 10 +#endif + +#define TI_TIROOT_TO_tdsaRoot(t_r) (((tdsaRoot_t *)((tiRoot_t *)t_r)->tdData) ) + +#define TI_TIROOT_TO_tdsaAllShared(t_r1) (tdsaContext_t *)&(t_r1->tdsaAllShared) + +#define TI_TIROOT_TO_agroot(t_r2) (agsaRoot_t *)&((t_r2)->agRootNonInt) + + +#define TI_TIROOT_TO_AGROOT(t_root) (TI_TIROOT_TO_agroot(TI_TIROOT_TO_tdsaAllShared(TI_TIROOT_TO_tdsaRoot(t_root)) )) + +#define TI_VEN_DEV_SPC 0x80010000 +#define TI_VEN_DEV_SPCADAP 0x80810000 +#define TI_VEN_DEV_SPCv 0x80080000 +#define TI_VEN_DEV_SPCve 0x80090000 +#define TI_VEN_DEV_SPCvplus 0x80180000 +#define TI_VEN_DEV_SPCveplus 0x80190000 +#define TI_VEN_DEV_SPCADAPvplus 0x80880000 +#define TI_VEN_DEV_SPCADAPveplus 0x80890000 + +#define TI_VEN_DEV_SPC12Gv 0x80700000 +#define TI_VEN_DEV_SPC12Gve 0x80710000 +#define TI_VEN_DEV_SPC12Gvplus 0x80720000 +#define TI_VEN_DEV_SPC12Gveplus 0x80730000 +#define TI_VEN_DEV_9015 0x90150000 +#define TI_VEN_DEV_SPC12ADP 0x80740000 /* 8 ports KBP added*/ +#define TI_VEN_DEV_SPC12ADPP 0x80760000 /* 16 ports */ +#define TI_VEN_DEV_SPC12SATA 0x80060000 /* SATA HBA */ +#define TI_VEN_DEV_9060 0x90600000 + +#define tIsSPC(agr) (TI_VEN_DEV_SPC == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC */ +#define tIsSPCHIL(agr) (TI_VEN_DEV_SPCADAP == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC */ +#define tIsSPCv(agr) (TI_VEN_DEV_SPCv == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCv */ +#define tIsSPCve(agr) (TI_VEN_DEV_SPCve == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCve */ +#define tIsSPCvplus(agr) (TI_VEN_DEV_SPCvplus == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCv+ */ +#define tIsSPCveplus(agr) (TI_VEN_DEV_SPCveplus == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCve+ */ +#define tIsSPCADAPvplus(agr) (TI_VEN_DEV_SPCADAPvplus == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCv+ */ +#define tIsSPCADAPveplus(agr) (TI_VEN_DEV_SPCADAPveplus == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCve+ */ + +#define tIsSPC12Gv(agr) (TI_VEN_DEV_SPC12Gv == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12Gv */ +#define tIsSPC12Gve(agr) (TI_VEN_DEV_SPC12Gve == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12Gve */ +#define tIsSPC12Gvplus(agr) (TI_VEN_DEV_SPC12Gvplus == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12Gv+ */ +#define tIsSPC12Gveplus(agr) (TI_VEN_DEV_SPC12Gveplus == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12Gve+ */ +#define tIsSPC9015(agr) (TI_VEN_DEV_9015 == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12Gve+ */ +#define tIsSPC9060(agr) (TI_VEN_DEV_9060 == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12Gve+ */ +#define tIsSPC12ADP(agr) (TI_VEN_DEV_SPC12ADP == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) +#define tIsSPC12ADPP(agr) (TI_VEN_DEV_SPC12ADPP == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) +#define tIsSPC12SATA(agr) (TI_VEN_DEV_SPC12SATA == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) + +#define tiIS_SPC(agr) (( tIsSPC((agr)) == 1) ? 1 : \ + ( tIsSPCHIL((agr)) == 1) ? 1 : 0 ) + +#define tiIS_HIL(agr) ((tIsSPCHIL ((agr)) == 1) ? 1 : \ + (tIsSPCADAPvplus((agr)) == 1) ? 1 : \ + (tIsSPCADAPveplus((agr)) == 1) ? 1 : 0 ) + +#define tiIS_SPC6V(agr) ((tIsSPCv((agr)) == 1) ? 1 : \ + (tIsSPCve((agr)) == 1) ? 1 : \ + (tIsSPCvplus((agr)) == 1) ? 1 : \ + (tIsSPCveplus((agr)) == 1) ? 1 : \ + (tIsSPCADAPvplus((agr)) == 1) ? 1 : \ + (tIsSPCADAPveplus((agr)) == 1) ? 1 : 0 ) + +#define tIsSPCV12G(agr) ((tIsSPC12Gv(agr) == 1) ? 1 : \ + (tIsSPC12Gve(agr) == 1) ? 1 : \ + (tIsSPC12Gvplus(agr)== 1) ? 1 : \ + (tIsSPC12Gveplus(agr)== 1) ? 1 : \ + (tIsSPC9015(agr)== 1) ? 1 : \ + (tIsSPC12ADP(agr)== 1) ? 1 : \ + (tIsSPC12ADPP(agr)== 1) ? 1 : \ + (tIsSPC12SATA(agr) == 1) ? 1 : \ + (tIsSPC9060(agr) == 1) ? 1 : 0) + +#define tiIS_8PHY(agr) ((tIsSPCv((agr)) == 1) ? 1 : \ + (tIsSPCve((agr)) == 1) ? 1 : \ + (tIsSPC12Gv((agr)) == 1) ? 1 : \ + (tIsSPC12Gve((agr)) == 1) ? 1 : \ + (tIsSPC12ADP(agr) == 1) ? 1 : 0 ) + +#define tiIS_16PHY(agr) ((tIsSPCvplus((agr)) == 1) ? 1 : \ + (tIsSPCveplus((agr)) == 1) ? 1 : \ + (tIsSPCADAPvplus((agr)) == 1) ? 1 : \ + (tIsSPCADAPveplus((agr)) == 1) ? 1 : \ + (tIsSPC12ADPP(agr) == 1) ? 1 : \ + (tIsSPC12SATA(agr) == 1) ? 1 : 0 ) + +#define tiIS_SPC_ENC(agr)((tIsSPCve((agr)) == 1) ? 1 : \ + (tIsSPCveplus((agr)) == 1) ? 1 : \ + (tIsSPCADAPveplus((agr)) == 1) ? 1 : 0 ) + +#define tIsSPCV12or6G(agr) ((tiIS_SPC6V(agr) == 1) ? 1 : \ + (tIsSPCV12G(agr) == 1) ? 1 : 0) + +#endif /* __TDDEFS_H__ */ diff --git a/sys/dev/pms/RefTisa/tisa/sassata/common/tddmcmnapi.c b/sys/dev/pms/RefTisa/tisa/sassata/common/tddmcmnapi.c new file mode 100644 index 000000000000..55f903242293 --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/common/tddmcmnapi.c @@ -0,0 +1,1300 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#include +#include + +#include +#include +#include +/* for TIDEBUG_MSG */ +#include + +#ifdef FDS_DM + +#include +#include +#include + +#ifdef FDS_SM +#include +#include +#endif + +#ifdef INITIATOR_DRIVER +#include +#endif + +#include +#include +#include + +#if defined(DM_DEBUG) +extern bit32 gDMDebugLevel; +#endif + +osGLOBAL bit32 +tddmRotateQnumber( + dmRoot_t *dmRoot, + agsaDevHandle_t *agDevHandle + ) +{ + tdsaRoot_t *tdsaRoot; + tdsaContext_t *tdsaAllShared; + tiRoot_t *tiRoot; + tdsaDeviceData_t *oneDeviceData = agNULL; + TI_DBG1(("tddmRotateQnumber: start\n")); + if (agDevHandle == agNULL) + { + TI_DBG1(("tddmRotateQnumber: agDevHandle is NULL!!!\n")); + return 0; + } + oneDeviceData = (tdsaDeviceData_t *)agDevHandle->osData; + if (oneDeviceData == agNULL) + { + TI_DBG1(("tddmRotateQnumber: oneDeviceData is NULL!!!\n")); + return 0; + } + tdsaRoot = (tdsaRoot_t *)dmRoot->tdData; + if (tdsaRoot == agNULL) + { + TI_DBG1(("tddmRotateQnumber: tdsaRoot is NULL\n")); + return 0; + } + tdsaAllShared = &(tdsaRoot->tdsaAllShared); + if (tdsaAllShared == agNULL) + { + TI_DBG1(("tddmRotateQnumber: tdsaAllShared is NULL\n")); + return 0; + } + tiRoot = tdsaAllShared->agRootOsDataForInt.tiRoot; + if (tiRoot == agNULL) + { + TI_DBG1(("tddmRotateQnumber: tiRoot is NULL\n")); + return 0; + } + return tdsaRotateQnumber(tiRoot, oneDeviceData); +} +osGLOBAL bit32 +tdsaFindLocalMCN( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext + ) +{ + bit32 i, localMCN = 0; + + TI_DBG2(("tdsaFindLocalMCN: start\n")); + + if (onePortContext->valid == agFALSE) + { + TI_DBG1(("tdsaFindLocalMCN: invalid portcontext id %d\n", onePortContext->id)); + return 0; + } + + for(i=0;iPhyIDList[i] == agTRUE) + { + localMCN++; + } + } + + return localMCN; +} + + +/* + on success, + ostiInitiatorEvent( + tiRoot, + onePortContext->tiPortalContext, + agNULL, + tiIntrEventTypeDiscovery, + tiDiscOK, + agNULL + ); +else + remove(de-register) all devices + ostiInitiatorEvent( + tiRoot, + onePortContext->tiPortalContext, + agNULL, + tiIntrEventTypeDiscovery, + tiDiscFailed, + agNULL + ); + + + dmRoot->tdData is tdsaRoot_t (just like current TD layer) + dmPortContext->tdData is tdsaPortContext_t + +*/ +osGLOBAL void +tddmDiscoverCB( + dmRoot_t *dmRoot, + dmPortContext_t *dmPortContext, + bit32 eventStatus + ) +{ + tdsaRoot_t *tdsaRoot; + tdsaContext_t *tdsaAllShared; + tiRoot_t *tiRoot; + tdsaPortContext_t *onePortContext; + agsaRoot_t *agRoot; + agsaPortContext_t *agPortContext; + + TI_DBG1(("tddmDiscoverCB: start\n")); + tdsaRoot = (tdsaRoot_t *)dmRoot->tdData; + if (tdsaRoot == agNULL) + { + TI_DBG1(("tddmDiscoverCB: tdsaRoot is NULL\n")); + return; + } + + tdsaAllShared = &(tdsaRoot->tdsaAllShared); + if (tdsaAllShared == agNULL) + { + TI_DBG1(("tddmDiscoverCB: tdsaAllShared is NULL\n")); + return; + } + + tiRoot = tdsaAllShared->agRootOsDataForInt.tiRoot; + if (tiRoot == agNULL) + { + TI_DBG1(("tddmDiscoverCB: tiRoot is NULL\n")); + return; + } + + onePortContext = (tdsaPortContext_t *)dmPortContext->tdData; + if (onePortContext == agNULL) + { + TI_DBG1(("tddmDiscoverCB: onePortContext is NULL\n")); + return; + } + + TI_DBG2(("tddmDiscoverCB: localMCN 0x%x\n", tdsaFindLocalMCN(tiRoot, onePortContext))); + + if (eventStatus == dmDiscCompleted) + { + TI_DBG1(("tddmDiscoverCB: dmDiscCompleted\n")); + onePortContext->DiscoveryState = ITD_DSTATE_COMPLETED; + onePortContext->DMDiscoveryState = dmDiscCompleted; + TI_DBG1(("tddmDiscoverCB: pid %d tiPortalContext %p\n", onePortContext->id, onePortContext->tiPortalContext)); + + /* update onePortContext->UpdateMCN = agFALSE */ + if ( onePortContext->UpdateMCN == agTRUE) + { + TI_DBG2(("tddmDiscoverCB: calling tdsaUpdateMCN\n")); + onePortContext->UpdateMCN = agFALSE; + tdsaUpdateMCN(dmRoot, onePortContext); + } + + ostiInitiatorEvent( + tiRoot, + onePortContext->tiPortalContext, + agNULL, + tiIntrEventTypeDiscovery, + tiDiscOK, + agNULL + ); + } + else if (eventStatus == dmDiscFailed ) + { + TI_DBG1(("tddmDiscoverCB: dmDiscFailed \n")); + onePortContext->DiscoveryState = ITD_DSTATE_COMPLETED; + onePortContext->DMDiscoveryState = dmDiscFailed; + TI_DBG1(("tddmDiscoverCB: pid %d tiPortalContext %p\n", onePortContext->id, onePortContext->tiPortalContext)); + agRoot = &(tdsaAllShared->agRootNonInt); + if (agRoot == agNULL) + { + TI_DBG1(("tddmDiscoverCB: agRoot is NULL\n")); + return; + } + agPortContext = onePortContext->agPortContext; + if (agPortContext == agNULL) + { + TI_DBG1(("tddmDiscoverCB: agPortContext is NULL\n")); + return; + } + /* + invalidate all devices in this port + */ + tddmInvalidateDevicesInPort(tiRoot, onePortContext); + + saPortControl(agRoot, + agNULL, + 0, + agPortContext, + AGSA_PORT_IO_ABORT, + 0 /*quarantine */, + 0 /* unused */); + + + ostiInitiatorEvent( + tiRoot, + onePortContext->tiPortalContext, + agNULL, + tiIntrEventTypeDiscovery, + tiDiscFailed, + agNULL + ); + } + else if (eventStatus == dmDiscAborted ) + { + TI_DBG1(("tddmDiscoverCB: dmDiscAborted \n")); + onePortContext->DMDiscoveryState = dmDiscAborted; + } + else if (eventStatus == dmDiscAbortFailed ) + { + TI_DBG1(("tddmDiscoverCB: dmDiscAbortFailed \n")); + onePortContext->DMDiscoveryState = dmDiscAbortFailed; + } + else if (eventStatus == dmDiscAbortInvalid ) + { + TI_DBG1(("tddmDiscoverCB: dmDiscAbortInvalid \n")); + onePortContext->DMDiscoveryState = dmDiscAbortInvalid; + } + else if (eventStatus == dmDiscAbortInProgress ) + { + TI_DBG1(("tddmDiscoverCB: dmDiscAbortInProgress \n")); + onePortContext->DMDiscoveryState = dmDiscAbortInProgress; + } + else + { + TI_DBG1(("tddmDiscoverCB: undefined eventStatus 0x%x\n", eventStatus)); + onePortContext->DMDiscoveryState = dmDiscFailed; + } + + return; +} + + +osGLOBAL void +tddmQueryDiscoveryCB( + dmRoot_t *dmRoot, + dmPortContext_t *dmPortContext, + bit32 discType, + bit32 discState + ) +{ + tdsaPortContext_t *onePortContext = agNULL; + + TI_DBG2(("tddmQueryDiscoveryCB: start\n")); + onePortContext = (tdsaPortContext_t *)dmPortContext->tdData; + if (onePortContext == agNULL) + { + TI_DBG1(("tddmQueryDiscoveryCB: onePortContext is NULL\n")); + return; + } + TI_DBG2(("tddmQueryDiscoveryCB: discType %d discState %d\n", discType, discState)); + + onePortContext->DMDiscoveryState = discState; + return; +} + +osGLOBAL void +tddmInvalidateDevicesInPort( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdsaDeviceData_t *oneDeviceData = agNULL; + tdList_t *DeviceListList; + + TI_DBG1(("tddmInvalidateDevicesInPort: start\n")); + + /* find a device's existence */ + DeviceListList = tdsaAllShared->MainDeviceList.flink; + while (DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + TI_DBG1(("tddmInvalidateDevicesInPort: oneDeviceData is NULL!!!\n")); + return; + } + if ((oneDeviceData->registered == agTRUE) && + (oneDeviceData->tdPortContext == onePortContext) + ) + { + + TI_DBG3(("tddmInvalidateDevicesInPort: Found pid %d did %d\n", onePortContext->id, oneDeviceData->id)); + if (oneDeviceData->SASAddressID.sasAddressHi == onePortContext->sasRemoteAddressHi && + oneDeviceData->SASAddressID.sasAddressLo == onePortContext->sasRemoteAddressLo + ) + { + TI_DBG1(("tddmInvalidateDevicesInPort: keeping\n")); + oneDeviceData->valid = agTRUE; + oneDeviceData->valid2 = agFALSE; + } + else if (oneDeviceData->valid == agTRUE) + { + oneDeviceData->valid = agFALSE; + oneDeviceData->valid2 = agFALSE; + oneDeviceData->registered = agFALSE; + } + } + DeviceListList = DeviceListList->flink; + } + + TI_DBG3(("tddmInvalidateDevicesInPort: end\n")); + + return; +} + +osGLOBAL bit32 +tddmNewSASorNot( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaSASSubID_t *agSASSubID + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdsaDeviceData_t *oneDeviceData = agNULL; + tdList_t *DeviceListList; + bit32 ret = agTRUE; + + TI_DBG3(("tddmNewSASorNot: start\n")); + + /* find a device's existence */ + DeviceListList = tdsaAllShared->MainDeviceList.flink; + while (DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + TI_DBG1(("tddmNewSASorNot: oneDeviceData is NULL!!!\n")); + return agFALSE; + } + if ((oneDeviceData->SASAddressID.sasAddressHi == agSASSubID->sasAddressHi) && + (oneDeviceData->SASAddressID.sasAddressLo == agSASSubID->sasAddressLo) && + (oneDeviceData->registered == agTRUE) && + (oneDeviceData->tdPortContext == onePortContext) + ) + { + TI_DBG3(("tddmNewSASorNot: Found pid %d did %d\n", onePortContext->id, oneDeviceData->id)); + ret = agFALSE; + break; + } + DeviceListList = DeviceListList->flink; + } + + + + TI_DBG3(("tddmNewSASorNot: end\n")); + + return ret; +} + +osGLOBAL tdsaDeviceData_t * +tddmPortSASDeviceFind( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + bit32 sasAddrLo, + bit32 sasAddrHi + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdsaDeviceData_t *oneDeviceData, *RetDeviceData=agNULL; + tdList_t *DeviceListList; + + TI_DBG2(("tddmPortSASDeviceFind: start\n")); + + TD_ASSERT((agNULL != tiRoot), ""); + TD_ASSERT((agNULL != onePortContext), ""); + + tdsaSingleThreadedEnter(tiRoot, TD_DEVICE_LOCK); + + /* find a device's existence */ + DeviceListList = tdsaAllShared->MainDeviceList.flink; + while (DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + TI_DBG1(("tddmPortSASDeviceFind: oneDeviceData is NULL!!!\n")); + return agNULL; + } + if ((oneDeviceData->SASAddressID.sasAddressHi == sasAddrHi) && + (oneDeviceData->SASAddressID.sasAddressLo == sasAddrLo) && + (oneDeviceData->valid == agTRUE) && + (oneDeviceData->tdPortContext == onePortContext) + ) + { + TI_DBG2(("tddmPortSASDeviceFind: Found pid %d did %d\n", onePortContext->id, oneDeviceData->id)); + TI_DBG2(("tddmPortSASDeviceFind: sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG2(("tddmPortSASDeviceFind: sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + RetDeviceData = oneDeviceData; + break; + } + DeviceListList = DeviceListList->flink; + } + + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + + return RetDeviceData; +} + +/* not in use yet */ +osGLOBAL tdsaDeviceData_t * +tddmAddToSharedcontext( + agsaRoot_t *agRoot, + tdsaPortContext_t *onePortContext, + tdsaSASSubID_t *agSASSubID, + tdsaDeviceData_t *oneExpDeviceData, + bit8 phyID + ) +{ + tdsaDeviceData_t *oneDeviceData = agNULL; + tdList_t *DeviceListList; + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + bit32 new_device = agTRUE; + + TI_DBG1(("tddmAddToSharedcontext: start\n")); + + TI_DBG1(("tddmAddToSharedcontext: oneportContext ID %d\n", onePortContext->id)); + /* find a device's existence */ + DeviceListList = tdsaAllShared->MainDeviceList.flink; + while (DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + TI_DBG1(("tddmAddToSharedcontext: oneDeviceData is NULL!!!\n")); + return agNULL; + } + if ((oneDeviceData->SASAddressID.sasAddressHi == agSASSubID->sasAddressHi) && + (oneDeviceData->SASAddressID.sasAddressLo == agSASSubID->sasAddressLo) && + (oneDeviceData->tdPortContext == onePortContext) + ) + { + TI_DBG1(("tddmAddToSharedcontext: pid %dtddmAddToSharedcontext did %d\n", onePortContext->id, oneDeviceData->id)); + new_device = agFALSE; + break; + } + DeviceListList = DeviceListList->flink; + } + + /* new device */ + if (new_device == agTRUE) + { + TI_DBG1(("tddmAddToSharedcontext: new device\n")); + tdsaSingleThreadedEnter(tiRoot, TD_DEVICE_LOCK); + if (!TDLIST_NOT_EMPTY(&(tdsaAllShared->FreeDeviceList))) + { + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + TI_DBG1(("tddmAddToSharedcontext: empty DeviceData FreeLink\n")); + return agNULL; + } + + TDLIST_DEQUEUE_FROM_HEAD(&DeviceListList, &(tdsaAllShared->FreeDeviceList)); + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, FreeLink, DeviceListList); + + TI_DBG1(("tddmAddToSharedcontext: oneDeviceData %p did %d\n", oneDeviceData, oneDeviceData->id)); + + onePortContext->Count++; + oneDeviceData->agRoot = agRoot; + /* saving sas address */ + oneDeviceData->SASAddressID.sasAddressLo = agSASSubID->sasAddressLo; + oneDeviceData->SASAddressID.sasAddressHi = agSASSubID->sasAddressHi; + oneDeviceData->initiator_ssp_stp_smp = agSASSubID->initiator_ssp_stp_smp; + oneDeviceData->target_ssp_stp_smp = agSASSubID->target_ssp_stp_smp; + oneDeviceData->tdPortContext = onePortContext; + /* handles both SAS target and STP-target, SATA-device */ + if (!DEVICE_IS_SATA_DEVICE(oneDeviceData) && !DEVICE_IS_STP_TARGET(oneDeviceData)) + { + oneDeviceData->DeviceType = TD_SAS_DEVICE; + } + else + { + oneDeviceData->DeviceType = TD_SATA_DEVICE; + } + + oneDeviceData->ExpDevice = oneExpDeviceData; + /* set phyID only when it has initial value of 0xFF */ + if (oneDeviceData->phyID == 0xFF) + { + oneDeviceData->phyID = phyID; + } + + oneDeviceData->valid = agTRUE; + + /* add the devicedata to the portcontext */ + tdsaSingleThreadedEnter(tiRoot, TD_DEVICE_LOCK); + TDLIST_ENQUEUE_AT_TAIL(&(oneDeviceData->MainLink), &(tdsaAllShared->MainDeviceList)); + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + TI_DBG1(("tddmAddToSharedcontext: one case pid %d did %d \n", onePortContext->id, oneDeviceData->id)); + TI_DBG1(("tddmAddToSharedcontext: new case pid %d did %d phyID %d\n", onePortContext->id, oneDeviceData->id, oneDeviceData->phyID)); + } + else /* old device */ + { + TI_DBG1(("tddmAddToSharedcontext: old device\n")); + TI_DBG1(("tddmAddToSharedcontext: oneDeviceData %p did %d\n", oneDeviceData, oneDeviceData->id)); + + oneDeviceData->agRoot = agRoot; + /* saving sas address */ + oneDeviceData->SASAddressID.sasAddressLo = agSASSubID->sasAddressLo; + oneDeviceData->SASAddressID.sasAddressHi = agSASSubID->sasAddressHi; + oneDeviceData->initiator_ssp_stp_smp = agSASSubID->initiator_ssp_stp_smp; + oneDeviceData->target_ssp_stp_smp = agSASSubID->target_ssp_stp_smp; + oneDeviceData->tdPortContext = onePortContext; + /* handles both SAS target and STP-target, SATA-device */ + if (!DEVICE_IS_SATA_DEVICE(oneDeviceData) && !DEVICE_IS_STP_TARGET(oneDeviceData)) + { + oneDeviceData->DeviceType = TD_SAS_DEVICE; + } + else + { + oneDeviceData->DeviceType = TD_SATA_DEVICE; + } + + oneDeviceData->ExpDevice = oneExpDeviceData; + /* set phyID only when it has initial value of 0xFF */ + if (oneDeviceData->phyID == 0xFF) + { + oneDeviceData->phyID = phyID; + } + + oneDeviceData->valid = agTRUE; + TI_DBG1(("tddmAddToSharedcontext: old case pid %d did %d phyID %d\n", onePortContext->id, oneDeviceData->id, oneDeviceData->phyID)); + + } + return oneDeviceData; + +} + + +/* + calls saRegisterNewDevice() + in ossaDeviceRegistrationCB(), if an expander, register to DM +#define DEVICE_IS_SMP_TARGET(DeviceData) \ + (((DeviceData)->target_ssp_stp_smp & DEVICE_SMP_BIT) == DEVICE_SMP_BIT) +*/ +osGLOBAL tdsaDeviceData_t * +tddmPortDeviceAdd( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + dmDeviceInfo_t *dmDeviceInfo, + tdsaDeviceData_t *oneExpDeviceData + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdsaDeviceData_t *oneDeviceData = agNULL; + tdsaSASSubID_t agSASSubID; + bit8 phyID; + + TI_DBG2(("tddmPortDeviceAdd: start\n")); + + + agSASSubID.sasAddressHi = TD_GET_SAS_ADDRESSHI(dmDeviceInfo->sasAddressHi); + agSASSubID.sasAddressLo = TD_GET_SAS_ADDRESSLO(dmDeviceInfo->sasAddressLo); + agSASSubID.initiator_ssp_stp_smp = dmDeviceInfo->initiator_ssp_stp_smp; + agSASSubID.target_ssp_stp_smp = dmDeviceInfo->target_ssp_stp_smp; + phyID = (dmDeviceInfo->ext) & 0xFF; + + /* old device and already registered to LL; added by link-up event */ + if ( agFALSE == tdssNewSASorNot( + onePortContext->agRoot, + onePortContext, + &agSASSubID + ) + ) + { + /* old device and already registered to LL; added by link-up event */ + TI_DBG2(("tddmPortDeviceAdd: OLD qqqq initiator_ssp_stp_smp %d target_ssp_stp_smp %d\n", agSASSubID.initiator_ssp_stp_smp, agSASSubID.target_ssp_stp_smp)); + /* find the old device */ + oneDeviceData = tdssNewAddSASToSharedcontext( + onePortContext->agRoot, + onePortContext, + &agSASSubID, + oneExpDeviceData, + phyID + ); + + if (oneDeviceData == agNULL) + { + TI_DBG1(("tddmPortDeviceAdd: no more device!!! oneDeviceData is null\n")); + } + + /* If a device is allocated */ + if ( oneDeviceData != agNULL ) + { + + TI_DBG2(("tddmPortDeviceAdd: sasAddressHi 0x%08x\n", agSASSubID.sasAddressHi)); + TI_DBG2(("tddmPortDeviceAdd: sasAddressLo 0x%08x\n", agSASSubID.sasAddressLo)); + TI_DBG2(("tddmPortDeviceAdd: phyID 0x%x\n", phyID)); + + /* copy dmDeviceInfo to oneDeviceData->agDeviceInfo except ext field */ + oneDeviceData->agDeviceInfo.smpTimeout = dmDeviceInfo->smpTimeout; + oneDeviceData->agDeviceInfo.it_NexusTimeout = dmDeviceInfo->it_NexusTimeout; + oneDeviceData->agDeviceInfo.firstBurstSize = dmDeviceInfo->firstBurstSize; + oneDeviceData->agDeviceInfo.devType_S_Rate = dmDeviceInfo->devType_S_Rate; + osti_memcpy(&(oneDeviceData->agDeviceInfo.sasAddressHi), &(dmDeviceInfo->sasAddressHi), 4); + osti_memcpy(&(oneDeviceData->agDeviceInfo.sasAddressLo), &(dmDeviceInfo->sasAddressLo), 4); + if (dmDeviceInfo->sataDeviceType == SATA_ATAPI_DEVICE) + { + oneDeviceData->agDeviceInfo.flag |= ATAPI_DEVICE_FLAG; + } + + oneDeviceData->satDevData.satDeviceType = dmDeviceInfo->sataDeviceType; + + + + oneDeviceData->agContext.osData = oneDeviceData; + oneDeviceData->agContext.sdkData = agNULL; + + } + return oneDeviceData; + } /* old device */ + + /* new device */ + + TI_DBG2(("tddmPortDeviceAdd: NEW qqqq initiator_ssp_stp_smp %d target_ssp_stp_smp %d\n", agSASSubID.initiator_ssp_stp_smp, agSASSubID.target_ssp_stp_smp)); + + /* allocate a new device and set the valid bit */ + oneDeviceData = tdssNewAddSASToSharedcontext( + onePortContext->agRoot, + onePortContext, + &agSASSubID, + oneExpDeviceData, + phyID + ); + + if (oneDeviceData == agNULL) + { + TI_DBG1(("tddmPortDeviceAdd: no more device!!! oneDeviceData is null\n")); + } + + /* If a device is allocated */ + if ( oneDeviceData != agNULL ) + { + + TI_DBG2(("tddmPortDeviceAdd: sasAddressHi 0x%08x\n", agSASSubID.sasAddressHi)); + TI_DBG2(("tddmPortDeviceAdd: sasAddressLo 0x%08x\n", agSASSubID.sasAddressLo)); + TI_DBG2(("tddmPortDeviceAdd: phyID 0x%x\n", phyID)); + + /* copy dmDeviceInfo to oneDeviceData->agDeviceInfo except ext field */ + oneDeviceData->agDeviceInfo.smpTimeout = dmDeviceInfo->smpTimeout; + oneDeviceData->agDeviceInfo.it_NexusTimeout = dmDeviceInfo->it_NexusTimeout; + oneDeviceData->agDeviceInfo.firstBurstSize = dmDeviceInfo->firstBurstSize; + oneDeviceData->agDeviceInfo.devType_S_Rate = dmDeviceInfo->devType_S_Rate; + osti_memcpy(&(oneDeviceData->agDeviceInfo.sasAddressHi), &(dmDeviceInfo->sasAddressHi), 4); + osti_memcpy(&(oneDeviceData->agDeviceInfo.sasAddressLo), &(dmDeviceInfo->sasAddressLo), 4); + + oneDeviceData->satDevData.satDeviceType = dmDeviceInfo->sataDeviceType; + if (dmDeviceInfo->sataDeviceType == SATA_ATAPI_DEVICE) + { + oneDeviceData->agDeviceInfo.flag |= ATAPI_DEVICE_FLAG; + } + + oneDeviceData->agContext.osData = oneDeviceData; + oneDeviceData->agContext.sdkData = agNULL; + + TI_DBG2(("tddmPortDeviceAdd: did %d\n", oneDeviceData->id)); + + /* don't add and register initiator for T2D */ + if ( (((oneDeviceData->initiator_ssp_stp_smp & DEVICE_SSP_BIT) == DEVICE_SSP_BIT) && + ((oneDeviceData->target_ssp_stp_smp & DEVICE_SSP_BIT) != DEVICE_SSP_BIT)) + || + (((oneDeviceData->initiator_ssp_stp_smp & DEVICE_STP_BIT) == DEVICE_STP_BIT) && + ((oneDeviceData->target_ssp_stp_smp & DEVICE_SSP_BIT) != DEVICE_SSP_BIT)) + ) + { + TI_DBG1(("tddmPortDeviceAdd: initiator. no add and registration\n")); + TI_DBG1(("tddmPortDeviceAdd: sasAddressHi 0x%08x\n", agSASSubID.sasAddressHi)); + TI_DBG1(("tddmPortDeviceAdd: sasAddressLo 0x%08x\n", agSASSubID.sasAddressLo)); + + } + else + { + if (oneDeviceData->registered == agFALSE) + { +#ifdef REMOVED + //temp; setting MCN to tdsaAllShared->MCN + oneDeviceData->agDeviceInfo.flag = oneDeviceData->agDeviceInfo.flag | (tdsaAllShared->MCN << 16); + //end temp +#endif + if( tdsaAllShared->sflag ) + { + if( ! DEVICE_IS_SMP_TARGET(oneDeviceData)) + { + TI_DBG1(("tddmPortDeviceAdd: saRegisterNewDevice sflag %d\n", tdsaAllShared->sflag)); + oneDeviceData->agDeviceInfo.flag = oneDeviceData->agDeviceInfo.flag | TD_XFER_RDY_PRIORTY_DEVICE_FLAG; + } + } + saRegisterNewDevice( /* tddmPortDeviceAdd */ + onePortContext->agRoot, + &oneDeviceData->agContext, + 0, + &oneDeviceData->agDeviceInfo, + onePortContext->agPortContext, + 0 + ); + } + } + } + + return oneDeviceData; +} + + +/* + each call, add the device to the device list + typedef struct{ + bit16 smpTimeout; + bit16 it_NexusTimeout; + bit16 firstBurstSize; + bit8 flag; + bit8 devType_S_Rate; + bit8 sasAddressHi[4]; + bit8 sasAddressLo[4]; +} dmDeviceInfo_t; + + find oneExpDeviceData (expander device data) from dmExpDeviceInfo and + pass it to tddmPortDeviceAdd() + start here - change spec from bit32 to void + + phyID = ((dmDeviceInfo->flag) & 0xFC) >> 2; + Initiators are not registered +*/ +//start here +osGLOBAL void +tddmReportDevice( + dmRoot_t *dmRoot, + dmPortContext_t *dmPortContext, + dmDeviceInfo_t *dmDeviceInfo, /* device */ + dmDeviceInfo_t *dmExpDeviceInfo, /* expander the device is attached to */ + bit32 flag + + ) +{ + agsaRoot_t *agRoot; + tdsaRoot_t *tdsaRoot; + tdsaContext_t *tdsaAllShared; + tiRoot_t *tiRoot; + tdsaDeviceData_t *oneExpDeviceData = agNULL; + bit32 sasAddressHi, sasAddressLo; + tdsaPortContext_t *onePortContext; + tdsaDeviceData_t *oneDeviceData = agNULL; + bit32 localMCN = 0, finalMCN = 0; + bit32 devMCN = 1; + bit32 DLR = 0xA; + bit32 option; + bit32 param; + +#ifdef FDS_SM + smRoot_t *smRoot; +#endif + + TI_DBG2(("tddmReportDevice: start\n")); + tdsaRoot = (tdsaRoot_t *)dmRoot->tdData; + if (tdsaRoot == agNULL) + { + TI_DBG1(("tddmReportDevice: tdsaRoot is NULL\n")); + return; + } + + tdsaAllShared = &(tdsaRoot->tdsaAllShared); + if (tdsaAllShared == agNULL) + { + TI_DBG1(("tddmReportDevice: tdsaAllShared is NULL\n")); + return; + } + + tiRoot = tdsaAllShared->agRootOsDataForInt.tiRoot; + if (tiRoot == agNULL) + { + TI_DBG1(("tddmReportDevice: tiRoot is NULL\n")); + return; + } + + onePortContext = (tdsaPortContext_t *)dmPortContext->tdData; + if (onePortContext == agNULL) + { + TI_DBG1(("tddmReportDevice: onePortContext is NULL\n")); + return; + } + +#ifdef FDS_SM + smRoot = &(tdsaAllShared->smRoot); +#endif + + TI_DBG2(("tddmReportDevice: device addrHi 0x%08x addrLo 0x%08x\n", + TD_GET_SAS_ADDRESSHI(dmDeviceInfo->sasAddressHi), TD_GET_SAS_ADDRESSHI(dmDeviceInfo->sasAddressLo))); + + if (dmExpDeviceInfo != agNULL) + { + TI_DBG2(("tddmReportDevice: attached expander addrHi 0x%08x addrLo 0x%08x\n", + TD_GET_SAS_ADDRESSHI(dmExpDeviceInfo->sasAddressHi), TD_GET_SAS_ADDRESSLO(dmExpDeviceInfo->sasAddressLo))); + } + else + { + TI_DBG2(("tddmReportDevice: No attached expander\n")); + } + + /* initiators only (e.g. SPC or SPCv) are discarded */ + if ( (dmDeviceInfo->target_ssp_stp_smp == 0) && + ( DEVICE_IS_SSP_INITIATOR(dmDeviceInfo) || DEVICE_IS_STP_INITIATOR(dmDeviceInfo) || DEVICE_IS_SMP_INITIATOR(dmDeviceInfo)) + ) + { + TI_DBG3(("tddmReportDevice: Initiators are not added\n")); + TI_DBG3(("tddmReportDevice: device addrHi 0x%08x addrLo 0x%08x\n", + TD_GET_SAS_ADDRESSHI(dmDeviceInfo->sasAddressHi), TD_GET_SAS_ADDRESSHI(dmDeviceInfo->sasAddressLo))); + return; + } + + if (flag == dmDeviceArrival) + { + TI_DBG2(("tddmReportDevice: arrival\n")); + if (dmExpDeviceInfo != agNULL) + { + sasAddressHi = TD_GET_SAS_ADDRESSHI(dmExpDeviceInfo->sasAddressHi); + sasAddressLo = TD_GET_SAS_ADDRESSLO(dmExpDeviceInfo->sasAddressLo); + + oneExpDeviceData = tddmPortSASDeviceFind(tiRoot, onePortContext, sasAddressLo, sasAddressHi); + } + + tddmPortDeviceAdd(tiRoot, onePortContext, dmDeviceInfo, oneExpDeviceData); + + } + else if (flag == dmDeviceRemoval) + { + TI_DBG2(("tddmReportDevice: removal\n")); + sasAddressHi = TD_GET_SAS_ADDRESSHI(dmDeviceInfo->sasAddressHi); + sasAddressLo = TD_GET_SAS_ADDRESSLO(dmDeviceInfo->sasAddressLo); + oneDeviceData = tddmPortSASDeviceFind(tiRoot, onePortContext, sasAddressLo, sasAddressHi); + if (oneDeviceData == agNULL) + { + TI_DBG2(("tddmReportDevice: oneDeviceData is NULL!!!\n")); + } + else + { + /* invalidate device */ + TI_DBG2(("tddmReportDevice: invalidating\n")); + TI_DBG2(("tddmReportDevice: agDevHandle %p\n", oneDeviceData->agDevHandle)); + if ( oneDeviceData->agDevHandle != agNULL) + { + TI_DBG2(("tddmReportDevice: agDevHandle->sdkData %p\n", oneDeviceData->agDevHandle->sdkData)); + } + else + { + TI_DBG2(("tddmReportDevice: agDevHandle->sdkData is NULL\n")); + } + oneDeviceData->valid = agFALSE; +//to do; to be tested + agRoot = oneDeviceData->agRoot; + if ( (oneDeviceData->registered == agTRUE) && + ( DEVICE_IS_SSP_TARGET(oneDeviceData) || DEVICE_IS_STP_TARGET(oneDeviceData) + || DEVICE_IS_SATA_DEVICE(oneDeviceData) || DEVICE_IS_SMP_TARGET(oneDeviceData) ) + ) + { + if ( !( DEVICE_IS_SMP_TARGET(oneDeviceData) && oneDeviceData->directlyAttached == agTRUE)) + { + tdsaAbortAll(tiRoot, agRoot, oneDeviceData); + oneDeviceData->registered = agFALSE; + } + else + { + TI_DBG2(("tddmReportDevice: keeping\n")); + oneDeviceData->registered = agTRUE; + } + } + else if (oneDeviceData->registered == agTRUE) + { + if ( oneDeviceData->agDevHandle == agNULL) + { + TI_DBG1(("tddmReportDevice: agDevHandle->sdkData is NULL. Error!!! \n")); + } + saDeregisterDeviceHandle(agRoot, agNULL, oneDeviceData->agDevHandle, tdsaRotateQnumber(tiRoot, oneDeviceData)); + oneDeviceData->registered = agFALSE; + } +//to do remove +#ifdef FDS_SM_WRONG + if (DEVICE_IS_SATA_DEVICE(oneDeviceData)) + { + TI_DBG2(("tddmReportDevice: smDeregisterDevice\n")); + smDeregisterDevice(smRoot, agNULL, oneDeviceData->agDevHandle, &(oneDeviceData->smDeviceHandle)); + oneDeviceData->satDevData.IDDeviceValid = agFALSE; + } +#endif + } + } + else if (flag == dmDeviceNoChange) + { + TI_DBG2(("tddmReportDevice: no change; do nothing \n")); +#ifdef FDS_SM + sasAddressHi = TD_GET_SAS_ADDRESSHI(dmDeviceInfo->sasAddressHi); + sasAddressLo = TD_GET_SAS_ADDRESSLO(dmDeviceInfo->sasAddressLo); + oneDeviceData = tddmPortSASDeviceFind(tiRoot, onePortContext, sasAddressLo, sasAddressHi); + if (oneDeviceData == agNULL) + { + TI_DBG2(("tddmReportDevice: oneDeviceData is NULL!!!\n")); + } + else + { + agRoot = oneDeviceData->agRoot; + if ( (DEVICE_IS_SATA_DEVICE(oneDeviceData) || DEVICE_IS_STP_TARGET(oneDeviceData)) + && + oneDeviceData->satDevData.IDDeviceValid == agFALSE) + { + tdIDStart(tiRoot, agRoot, smRoot, oneDeviceData, onePortContext); + } + } +#endif + } + else if (flag == dmDeviceMCNChange) + { + TI_DBG2(("tddmReportDevice: dmDeviceMCNChange \n")); + localMCN = tdsaFindLocalMCN(tiRoot, onePortContext); + devMCN = DEVINFO_GET_EXT_MCN(dmDeviceInfo); + TI_DBG2(("tddmReportDevice: devMCN 0x%08x localMCN 0x%08x\n", devMCN, localMCN)); + + sasAddressHi = TD_GET_SAS_ADDRESSHI(dmDeviceInfo->sasAddressHi); + sasAddressLo = TD_GET_SAS_ADDRESSLO(dmDeviceInfo->sasAddressLo); + oneDeviceData = tddmPortSASDeviceFind(tiRoot, onePortContext, sasAddressLo, sasAddressHi); + if (oneDeviceData == agNULL) + { + TI_DBG1(("tddmReportDevice: oneDeviceData is NULL!!!\n")); + } + else + { + agRoot = oneDeviceData->agRoot; + oneDeviceData->devMCN = devMCN; + TI_DBG2(("tddmReportDevice: sasAddrHi 0x%08x sasAddrLo 0x%08x\n", sasAddressHi, sasAddressLo)); + if (oneDeviceData->directlyAttached == agTRUE) + { + finalMCN = localMCN; + TI_DBG2(("tddmReportDevice: directlyAttached, Final MCN 0x%08x\n", finalMCN)); + } + else + { + finalMCN = MIN(devMCN, localMCN); + TI_DBG2(("tddmReportDevice: Not directlyAttached, Final MCN 0x%08x\n", finalMCN)); + } + if ( oneDeviceData->registered == agTRUE) + { + /* saSetDeviceInfo to change MCN, using finalMCN */ + option = 8; /* setting only MCN 1000b */ + param = finalMCN << 24; + TI_DBG2(("tddmReportDevice: option 0x%x param 0x%x MCN 0x%x\n", option, param, finalMCN)); + saSetDeviceInfo(agRoot, agNULL, 0, oneDeviceData->agDevHandle, option, param, ossaSetDeviceInfoCB); + } + else + { + TI_DBG1(("tddmReportDevice: oneDeviceData is not yet registered !!!\n")); + } + oneDeviceData->finalMCN = finalMCN; + } + } + else if (flag == dmDeviceRateChange) + { + TI_DBG1(("tddmReportDevice: dmDeviceRateChange \n")); + sasAddressHi = TD_GET_SAS_ADDRESSHI(dmDeviceInfo->sasAddressHi); + sasAddressLo = TD_GET_SAS_ADDRESSLO(dmDeviceInfo->sasAddressLo); + oneDeviceData = tddmPortSASDeviceFind(tiRoot, onePortContext, sasAddressLo, sasAddressHi); + if (oneDeviceData == agNULL) + { + TI_DBG1(("tddmReportDevice: oneDeviceData is NULL!!!\n")); + } + else + { + agRoot = oneDeviceData->agRoot; + if ( oneDeviceData->registered == agTRUE) + { + option = 0x20; /* bit 5 */ + DLR = DEVINFO_GET_LINKRATE(dmDeviceInfo); + param = DLR << 28; + TI_DBG1(("tddmReportDevice: option 0x%x param 0x%x DLR 0x%x\n", option, param, DLR)); + saSetDeviceInfo(agRoot, agNULL, 0, oneDeviceData->agDevHandle, option, param, ossaSetDeviceInfoCB); + + } + else + { + TI_DBG1(("tddmReportDevice: oneDeviceData is not yet registered !!!\n")); + } + + } + } + else + { + TI_DBG1(("tddmReportDevice: unknown flag 0x%x, wrong\n", flag)); + } + + return; +} + +osGLOBAL void +tdsaUpdateMCN( + dmRoot_t *dmRoot, + tdsaPortContext_t *onePortContext + ) +{ + tdsaRoot_t *tdsaRoot; + tdsaContext_t *tdsaAllShared; + tiRoot_t *tiRoot; + tdsaDeviceData_t *oneDeviceData = agNULL; + tdList_t *DeviceListList; + bit32 localMCN = 0, finalMCN = 0; + bit32 devMCN = 1; + bit32 option; + bit32 param; + + TI_DBG3(("tdsaUpdateMCN: start\n")); + tdsaRoot = (tdsaRoot_t *)dmRoot->tdData; + if (tdsaRoot == agNULL) + { + TI_DBG1(("tdsaUpdateMCN: tdsaRoot is NULL\n")); + return; + } + + tdsaAllShared = &(tdsaRoot->tdsaAllShared); + if (tdsaAllShared == agNULL) + { + TI_DBG1(("tdsaUpdateMCN: tdsaAllShared is NULL\n")); + return; + } + + tiRoot = tdsaAllShared->agRootOsDataForInt.tiRoot; + if (tiRoot == agNULL) + { + TI_DBG1(("tdsaUpdateMCN: tiRoot is NULL\n")); + return; + } + + if (onePortContext->valid == agFALSE) + { + TI_DBG1(("tdsaUpdateMCN: onePortContext is invalid\n")); + return; + } + + TI_DBG3(("tdsaUpdateMCN: pid %d\n", onePortContext->id)); + + localMCN = tdsaFindLocalMCN(tiRoot, onePortContext); + + if (TDLIST_EMPTY(&(tdsaAllShared->MainDeviceList))) + { + TI_DBG1(("tdsaUpdateMCN: empty device list\n")); + return; + } + + /* update directly and behind expander device */ + DeviceListList = tdsaAllShared->MainDeviceList.flink; + while (DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + TI_DBG1(("tdsaUpdateMCN: oneDeviceData is NULL!!!\n")); + return; + } + TI_DBG3(("tdsaUpdateMCN: loop did %d\n", oneDeviceData->id)); + TI_DBG3(("tdsaUpdateMCN: sasAddrHi 0x%08x sasAddrLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi, oneDeviceData->SASAddressID.sasAddressLo)); + devMCN = oneDeviceData->devMCN; + if ( oneDeviceData->tdPortContext == onePortContext) + { + if (oneDeviceData->valid == agTRUE && oneDeviceData->registered == agTRUE && oneDeviceData->directlyAttached == agTRUE) + { + TI_DBG3(("tdsaUpdateMCN: found directly attached\n")); + finalMCN = localMCN; + TI_DBG3(("tdsaUpdateMCN: devMCN 0x%08x localMCN 0x%08x\n", devMCN, localMCN)); + TI_DBG3(("tdsaUpdateMCN: finalMCN 0x%08x\n", finalMCN)); + if (oneDeviceData->finalMCN != finalMCN) + { + /* saSetDeviceInfo using finalMCN */ + option = 8; /* setting only MCN 1000b */ + param = finalMCN << 24; + TI_DBG3(("tdsaUpdateMCN: option 0x%x param 0x%x MCN 0x%x\n", option, param, finalMCN)); + saSetDeviceInfo(oneDeviceData->agRoot, agNULL, 0, oneDeviceData->agDevHandle, option, param, ossaSetDeviceInfoCB); + oneDeviceData->finalMCN = finalMCN; + } + + } + else if (oneDeviceData->valid == agTRUE && oneDeviceData->registered == agTRUE && oneDeviceData->directlyAttached == agFALSE) + { + TI_DBG3(("tdsaUpdateMCN: found behind expander device\n")); + finalMCN = MIN(localMCN, devMCN); + TI_DBG3(("tdsaUpdateMCN: devMCN 0x%08x localMCN 0x%08x\n", devMCN, localMCN)); + TI_DBG3(("tdsaUpdateMCN: finalMCN 0x%08x\n", finalMCN)); + if (oneDeviceData->finalMCN != finalMCN) + { + /* saSetDeviceInfo using finalMCN */ + option = 8; /* setting only MCN 1000b */ + param = finalMCN << 24; + TI_DBG3(("tdsaUpdateMCN: option 0x%x param 0x%x MCN 0x%x\n", option, param, finalMCN)); + saSetDeviceInfo(oneDeviceData->agRoot, agNULL, 0, oneDeviceData->agDevHandle, option, param, ossaSetDeviceInfoCB); + oneDeviceData->finalMCN = finalMCN; + } + + } + DeviceListList = DeviceListList->flink; + } + else + { + if (oneDeviceData->tdPortContext != agNULL) + { + TI_DBG3(("tdsaUpdateMCN: different portcontext; oneDeviceData->tdPortContext pid %d oneportcontext pid %d\n", oneDeviceData->tdPortContext->id, onePortContext->id)); + } + else + { + TI_DBG3(("tdsaUpdateMCN: different portcontext; oneDeviceData->tdPortContext pid NULL oneportcontext pid %d\n", onePortContext->id)); + } + DeviceListList = DeviceListList->flink; + } + } /* while */ + + return; +} + +osGLOBAL bit8 +tddmSATADeviceTypeDecode(bit8 * pSignature) +{ + return (bit8)tdssSATADeviceTypeDecode(pSignature); +} + + +osGLOBAL void +tddmSingleThreadedEnter( + dmRoot_t *dmRoot, + bit32 syncLockId + ) +{ + tdsaRoot_t *tdsaRoot; + tdsaContext_t *tdsaAllShared; + tiRoot_t *tiRoot; + bit32 offset = 0; + + TI_DBG7(("tddmSingleThreadedEnter: start\n")); + + tdsaRoot = (tdsaRoot_t *)dmRoot->tdData; + if (tdsaRoot == agNULL) + { + TI_DBG1(("tddmSingleThreadedEnter: tdsaRoot is NULL\n")); + return; + } + + tdsaAllShared = &(tdsaRoot->tdsaAllShared); + if (tdsaAllShared == agNULL) + { + TI_DBG1(("tddmSingleThreadedEnter: tdsaAllShared is NULL\n")); + return; + } + + tiRoot = tdsaAllShared->agRootOsDataForInt.tiRoot; + if (tiRoot == agNULL) + { + TI_DBG1(("tddmSingleThreadedEnter: tiRoot is NULL\n")); + return; + } + offset = tdsaAllShared->MaxNumLLLocks + tdsaAllShared->MaxNumOSLocks + TD_MAX_LOCKS; + + ostiSingleThreadedEnter(tiRoot, syncLockId + offset); + return; +} + +osGLOBAL void +tddmSingleThreadedLeave( + dmRoot_t *dmRoot, + bit32 syncLockId + ) +{ + tdsaRoot_t *tdsaRoot; + tdsaContext_t *tdsaAllShared; + tiRoot_t *tiRoot; + bit32 offset = 0; + + TI_DBG7(("tddmSingleThreadedLeave: start\n")); + + tdsaRoot = (tdsaRoot_t *)dmRoot->tdData; + if (tdsaRoot == agNULL) + { + TI_DBG1(("tddmSingleThreadedLeave: tdsaRoot is NULL\n")); + return; + } + + tdsaAllShared = &(tdsaRoot->tdsaAllShared); + if (tdsaAllShared == agNULL) + { + TI_DBG1(("tddmSingleThreadedLeave: tdsaAllShared is NULL\n")); + return; + } + + tiRoot = tdsaAllShared->agRootOsDataForInt.tiRoot; + if (tiRoot == agNULL) + { + TI_DBG1(("tddmSingleThreadedLeave: tiRoot is NULL\n")); + return; + } + offset = tdsaAllShared->MaxNumLLLocks + tdsaAllShared->MaxNumOSLocks + TD_MAX_LOCKS; + + ostiSingleThreadedLeave(tiRoot, syncLockId + offset); + + return; +} + +osGLOBAL bit32 tddmGetTransportParam( + dmRoot_t *dmRoot, + char *key, + char *subkey1, + char *subkey2, + char *subkey3, + char *subkey4, + char *subkey5, + char *valueName, + char *buffer, + bit32 bufferLen, + bit32 *lenReceived + ) +{ + bit32 ret = tiError; + + TI_DBG7(("tddmGetTransportParam: start\n")); + ret = ostiGetTransportParam(agNULL, + key, + subkey1, + subkey2, + subkey3, + subkey4, + subkey5, + valueName, + buffer, + bufferLen, + lenReceived + ); + + return ret; +} + +#endif /* FDS_DM */ + diff --git a/sys/dev/pms/RefTisa/tisa/sassata/common/tdesgl.c b/sys/dev/pms/RefTisa/tisa/sassata/common/tdesgl.c new file mode 100644 index 000000000000..3b7fc05c8f0a --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/common/tdesgl.c @@ -0,0 +1,543 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +** +********************************************************************************/ +/*******************************************************************************/ +/** \file + * + * + * This file contains ESGL realted functions + * + */ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#ifdef FDS_SM +#include +#include +#include +#endif + +#ifdef FDS_DM +#include +#include +#include +#endif + +#include +#include +#include + +#ifdef INITIATOR_DRIVER +#include +#include +#include +#endif + +#ifdef TARGET_DRIVER +#include +#include +#include +#endif + +#include +#include + +/* no more esgl related functions */ +#ifdef REMOVED +/***************************************************************************** +*! \brief tdsaEsglInit +* +* Purpose: This function initializes the linked list of ESGL pool +* +* \param tiRoot: Pointer to root data structure. +* +* \return: None +* +* \note +* +*****************************************************************************/ +osGLOBAL void +tdsaEsglInit( + tiRoot_t *tiRoot + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *)tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdsaEsglAllInfo_t *pEsglAllInfo = (tdsaEsglAllInfo_t *)&(tdsaAllShared->EsglAllInfo); + tdsaEsglPagePool_t *pEsglPagePool; + + bit32 pageno; + bit32 PagePhysAddrUpper; + bit32 PagePhysAddrLower; + bit32 prev_PagePhysAddrLower; + tdsaEsglPageInfo_t *pEsglPageInfo; + void *PageVirtAddr; + bit32 PageSizeInBytes; + + /* for memory index requirement */ + agsaRoot_t agRoot; + bit32 maxSALocks = 0; + bit32 usecsPerTick = 0; + agsaSwConfig_t SwConfig; + agsaMemoryRequirement_t memRequirement; + agsaQueueConfig_t *QueueConfig; + bit32 i; + + TI_DBG6(("tdsaEsglInit: start\n")); + + tdsaGetSwConfigParams(tiRoot); + QueueConfig = &tdsaAllShared->QueueConfig; + + for(i=0;inumInboundQueues;i++) + { + QueueConfig->inboundQueues[i].elementCount = tdsaAllShared->InboundQueueSize; + QueueConfig->inboundQueues[i].elementSize = tdsaAllShared->InboundQueueEleSize; + QueueConfig->inboundQueues[i].priority = tdsaAllShared->InboundQueuePriority[i]; + QueueConfig->inboundQueues[i].reserved = 0; + } + for(i=0;inumOutboundQueues;i++) + { + QueueConfig->outboundQueues[i].elementCount = tdsaAllShared->OutboundQueueSize; + QueueConfig->outboundQueues[i].elementSize = tdsaAllShared->OutboundQueueEleSize; + QueueConfig->outboundQueues[i].interruptDelay = tdsaAllShared->OutboundQueueInterruptDelay[i]; /* default 0; no interrupt delay */ + QueueConfig->outboundQueues[i].interruptCount = tdsaAllShared->OutboundQueueInterruptCount[i]; /* default 1*/ + QueueConfig->outboundQueues[i].interruptVectorIndex = 0; + } + + /* + hardcoded Queue numbers + */ + QueueConfig->sasHwEventQueue = 0; + QueueConfig->sataNCQErrorEventQueue = 0; + SwConfig.sizefEventLog1 = HOST_EVENT_LOG_SIZE; + SwConfig.sizefEventLog2 = HOST_EVENT_LOG_SIZE; + SwConfig.eventLog1Option = 0; + SwConfig.eventLog2Option = 0; + SwConfig.fatalErrorInterrtuptEnable = 1; + SwConfig.fatalErrorInterruptVector = 1; + SwConfig.reserved = 0; + + + SwConfig.param3 = (void *)&(tdsaAllShared->QueueConfig); + /* to find out memRequirement */ + saGetRequirements(&agRoot, &SwConfig, &memRequirement, &usecsPerTick, &maxSALocks); + + /* initializes tdsaEsglAllInfo_t */ + pEsglAllInfo->physAddrUpper = tdsaAllShared->loResource.loLevelMem.mem[memRequirement.count].physAddrUpper; + pEsglAllInfo->physAddrLower = tdsaAllShared->loResource.loLevelMem.mem[memRequirement.count].physAddrLower; + pEsglAllInfo->virtPtr = tdsaAllShared->loResource.loLevelMem.mem[memRequirement.count].virtPtr; + pEsglAllInfo->NumEsglPages = tdsaAllShared->loResource.loLevelMem.mem[memRequirement.count].numElements; /* NUM_ESGL_PAGES; number of esgl pages; configurable */ + pEsglAllInfo->EsglPageSize = tdsaAllShared->loResource.loLevelMem.mem[memRequirement.count].singleElementLength; /* sizeof(agsaEsgl_t) */ + pEsglAllInfo->NumFreeEsglPages = pEsglAllInfo->NumEsglPages; + pEsglPagePool = pEsglAllInfo->EsglPagePool; + + TI_DBG6(("tdsaEsglInit: pEsglPagePool %p\n", pEsglPagePool)); + TI_DBG6(("tdsaEsglInit: tdsaAllShared->loResource.loLevelMem.mem[18].singleElementLength %d\n", tdsaAllShared->loResource.loLevelMem.mem[18].singleElementLength)); + TI_DBG6(("tdsaEsglInit: NumEsglPage %d EsglPageSize %d\n", pEsglAllInfo->NumEsglPages, pEsglAllInfo->EsglPageSize)); /* ?, 128 */ + TI_DBG6(("tdsaEsglInit: NumFreeEsglPages %d\n", pEsglAllInfo->NumFreeEsglPages)); + /* initialize the linked lists */ + TDLIST_INIT_HDR(&pEsglAllInfo->freelist); + + + PageVirtAddr = pEsglAllInfo->virtPtr; + PagePhysAddrUpper = pEsglAllInfo->physAddrUpper; + PagePhysAddrLower = pEsglAllInfo->physAddrLower; + PageSizeInBytes = pEsglAllInfo->EsglPageSize; + + TI_DBG6(("tdsaEsglInit: PageSizeInBytes 0x%x\n", PageSizeInBytes)); + for (pageno = 0 ; pageno < pEsglAllInfo->NumEsglPages ; pageno++) + { + pEsglPageInfo = &(pEsglPagePool->EsglPages[pageno]); + OSSA_WRITE_LE_32(agRoot, pEsglPageInfo, OSSA_OFFSET_OF(pEsglPageInfo, physAddressUpper), PagePhysAddrUpper); + OSSA_WRITE_LE_32(agRoot, pEsglPageInfo, OSSA_OFFSET_OF(pEsglPageInfo, physAddressLower), PagePhysAddrLower); + pEsglPageInfo->len = PageSizeInBytes; + /* for debugging onlye*/ + pEsglPageInfo->id = pageno+123; + pEsglPageInfo->agEsgl = (agsaEsgl_t *)PageVirtAddr; + + /* for debugging only */ + TI_DBG6(("tdsaEsglInit: index %d upper 0x%8x lower 0x%8x PageVirtAddr %p\n", pageno, PagePhysAddrUpper, PagePhysAddrLower, PageVirtAddr)); + + + /* updates addresses */ + prev_PagePhysAddrLower = PagePhysAddrLower; + PagePhysAddrLower += pEsglAllInfo->EsglPageSize; + /* if lower wraps around, increment upper */ + if (PagePhysAddrLower <= prev_PagePhysAddrLower) + { + PagePhysAddrUpper++; + } + + if (pageno == pEsglAllInfo->NumEsglPages - 1) /* last page */ + { + pEsglPageInfo->agEsgl->descriptor[MAX_ESGL_ENTRIES-1].len = 0; + /* set bit31 to zero */ + CLEAR_ESGL_EXTEND(pEsglPageInfo->agEsgl->descriptor[MAX_ESGL_ENTRIES-1].extReserved); + } + else + { + /* first and so on */ + pEsglPageInfo->agEsgl->descriptor[MAX_ESGL_ENTRIES-1].sgLower = PagePhysAddrLower; + pEsglPageInfo->agEsgl->descriptor[MAX_ESGL_ENTRIES-1].sgUpper = PagePhysAddrUpper; + pEsglPageInfo->agEsgl->descriptor[MAX_ESGL_ENTRIES-1].len = PageSizeInBytes; /* sizeof (agsaEsgl_t)*/ + /* set bit31 to one */ + SET_ESGL_EXTEND(pEsglPageInfo->agEsgl->descriptor[MAX_ESGL_ENTRIES-1].extReserved); + } + + TDLIST_INIT_ELEMENT(&pEsglPageInfo->tdlist); + tdsaSingleThreadedEnter(tiRoot, TD_ESGL_LOCK); + TDLIST_ENQUEUE_AT_TAIL(&pEsglPageInfo->tdlist, &pEsglAllInfo->freelist); + tdsaSingleThreadedLeave(tiRoot, TD_ESGL_LOCK); + + PageVirtAddr = (bit8 *)PageVirtAddr + PageSizeInBytes; + } /* end for */ + + + +#ifdef TD_INTERNAL_DEBUG /* for debugging only, for keep now */ + for (pageno = 0 ; pageno < pEsglAllInfo->NumEsglPages ; pageno++) + { + TI_DBG6(("tdsaEsglInit: index %d EsglPages %p\n", pageno, &pEsglPagePool->EsglPages[pageno])); + TI_DBG6(("tdsaEsglInit: nextupper 0x%8x nextlower 0x%8x\n", pEsglPagePool->EsglPages[pageno].agEsgl->nextPageUpper, pEsglPagePool->EsglPages[pageno].agEsgl->nextPageLower)); + } + TI_DBG6(("tdsaEsglInit: tdsaEsglPageInfo_t size %d 0x%x\n", sizeof(tdsaEsglPageInfo_t), sizeof(tdsaEsglPageInfo_t))); + TI_DBG6(("tdsaEsglInit: sizeof(SASG_DESCRIPTOR) %d 0x%x\n", sizeof(SASG_DESCRIPTOR), sizeof(SASG_DESCRIPTOR))); +#endif + + return; +} + + +/***************************************************************************** +*! \brief tdsaGetEsglPages +* +* Purpose: This function prepares linked list of ESGL pages from +* the given scatter-gather list. +* +* \param tiRoot: Pointer to root data structure. +* \param EsglListHdr: pointer to list header where the list needs to be stored. +* \param ptiSgl: Pointer to scatter-gather list. +* \param virtSgl: virtual pointer to scatter-gather list. +* +* \return None +* +* \note - +* 1. If we are out of ESGL pages, then no pages will be added to the list +* pointed to by EsglListHdr. The list should be empty before calling +* this function, so that after returning from this function, the +* function can check for the emptyness of the list and find out if +* any pages were added or not. +* +*****************************************************************************/ +osGLOBAL void +tdsaGetEsglPages( + tiRoot_t *tiRoot, + tdList_t *EsglListHdr, + tiSgl_t *ptiSgl, + tiSgl_t *virtSgl + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + + tdsaEsglAllInfo_t *pEsglAllInfo = &(tdsaAllShared->EsglAllInfo); + bit32 numSgElements = ptiSgl->len; + bit32 numEntriesPerPage = MAX_ESGL_ENTRIES; + bit32 numPagesRequired = ((numSgElements - 1) / numEntriesPerPage) + 1; + bit32 i, j; + tdList_t *tdlist_to_fill; + tdsaEsglPageInfo_t *page_to_fill; + tiSgl_t *tmp_tiSgl = (tiSgl_t *)virtSgl; + agsaSgl_t *pDesc; + agsaEsgl_t *agEsgl, *PrevagEsgl = agNULL; + + TI_DBG6(("tdsaGetEsglPages: start\n")); + TI_DBG6(("tdsaGetEsglPages: pEsglPagePool %p\n", pEsglAllInfo->EsglPagePool)); + TI_DBG6(("tdsaGetEsglPages: &(pEsglAllInfo->freelist) %p\n", &pEsglAllInfo->freelist)); + TI_DBG6(("tdsaGetEsglPages: numSgElements %d numEntriesPerPage %d\n", numSgElements, numEntriesPerPage)); /* ?, 10 */ + TI_DBG6(("tdsaGetEsglPages: numPagesRequired %d NumFreeEsglPages %d\n", numPagesRequired, pEsglAllInfo->NumFreeEsglPages)); /* 1, 2 */ + TI_DBG6(("tdsaGetEsglPages: free Pages %d\n", pEsglAllInfo->NumFreeEsglPages)); + + if (numPagesRequired > pEsglAllInfo->NumFreeEsglPages) + { + TI_DBG1(("tdsaGetEsglPages:don't have enough freepages. required %d free %d\n", numPagesRequired, pEsglAllInfo->NumFreeEsglPages)); + return; + } + tdsaSingleThreadedEnter(tiRoot, TD_ESGL_LOCK); + pEsglAllInfo->NumFreeEsglPages -= numPagesRequired; + tdsaSingleThreadedLeave(tiRoot, TD_ESGL_LOCK); + + + +#ifdef TD_INTERNAL_DEBUG /* for debugging only */ + for (i=0; i < 2; i++) + { + /* remove one page from freelist */ + tdsaSingleThreadedEnter(tiRoot, TD_ESGL_LOCK); + TDLIST_DEQUEUE_FROM_HEAD(&tdlist_to_fill, &pEsglAllInfo->freelist); + tdsaSingleThreadedLeave(tiRoot, TD_ESGL_LOCK); + + /* get the pointer to the page from list pointer */ + page_to_fill = TDLIST_OBJECT_BASE(tdsaEsglPageInfo_t, tdlist, tdlist_to_fill); + /* for debugging */ + TI_DBG6(("tdsaGetEsglPages:page ID %d\n", page_to_fill->id)); + agEsgl = page_to_fill->agEsgl; + + pDesc = (SASG_DESCRIPTOR *)agEsgl; + + for (j=0; j sgLower, pDesc->sgUpper)); + TI_DBG6(("tdsaGetEsglPages: len %d\n", pDesc->len)); + pDesc++; + } + TI_DBG6(("tdsaGetEsglPages: next lower %d next upper %d\n", agEsgl->nextPageLower, agEsgl->nextPageUpper)); + + } +#endif /* for debugging only */ + + for (i = 0 ; i < numPagesRequired; i++) + { + /* remove one page from freelist */ + tdsaSingleThreadedEnter(tiRoot, TD_ESGL_LOCK); + TDLIST_DEQUEUE_FROM_HEAD(&tdlist_to_fill, &pEsglAllInfo->freelist); + tdsaSingleThreadedLeave(tiRoot, TD_ESGL_LOCK); + + /* get the pointer to the page from list pointer */ + page_to_fill = TDLIST_OBJECT_BASE(tdsaEsglPageInfo_t, tdlist, tdlist_to_fill); + /* for debugging */ + TI_DBG6(("tdsaGetEsglPages:page ID %d\n", page_to_fill->id)); + + agEsgl = page_to_fill->agEsgl; + pDesc = (agsaSgl_t *)agEsgl; + + /* + adjust next page's address in the followings so that + the last entry must be (0,0,0) + */ + if (i == numPagesRequired - 1) /* only one page of last page */ + { + for (j=0; j < numSgElements; j++) + { + OSSA_WRITE_LE_32(agRoot, pDesc, OSSA_OFFSET_OF(pDesc, sgLower), tmp_tiSgl->lower); + OSSA_WRITE_LE_32(agRoot, pDesc, OSSA_OFFSET_OF(pDesc, sgUpper), tmp_tiSgl->upper); + OSSA_WRITE_LE_32(agRoot, pDesc, OSSA_OFFSET_OF(pDesc, len), tmp_tiSgl->len); + CLEAR_ESGL_EXTEND(pDesc->extReserved); + pDesc++; + tmp_tiSgl++; + } + for (j=numSgElements; j < numEntriesPerPage; j++) + { + /* left over(unused) in the page */ + pDesc->sgLower = 0x0; + pDesc->sgUpper = 0x0; + pDesc->len = 0x0; + CLEAR_ESGL_EXTEND(pDesc->extReserved); + pDesc++; + } + } + else + { + /* in case of muliple pages, first and later, except one page only or last page */ + for (j=0; j lower); + OSSA_WRITE_LE_32(agRoot, pDesc, OSSA_OFFSET_OF(pDesc, sgUpper), tmp_tiSgl->upper); + OSSA_WRITE_LE_32(agRoot, pDesc, OSSA_OFFSET_OF(pDesc, len), tmp_tiSgl->len); + CLEAR_ESGL_EXTEND(pDesc->extReserved); + pDesc++; + tmp_tiSgl++; + } + numSgElements -= (numEntriesPerPage - 1); + } + if (PrevagEsgl != agNULL) + { + /* subsequent pages (second or later pages) */ + PrevagEsgl->descriptor[MAX_ESGL_ENTRIES-1].sgLower = page_to_fill->physAddressLower; + PrevagEsgl->descriptor[MAX_ESGL_ENTRIES-1].sgUpper = page_to_fill->physAddressUpper; + PrevagEsgl->descriptor[MAX_ESGL_ENTRIES-1].len = numSgElements; + /* set bit31 to one */ + SET_ESGL_EXTEND(PrevagEsgl->descriptor[MAX_ESGL_ENTRIES-1].extReserved); + } + PrevagEsgl = agEsgl; + /* put ESGL onto the EsglListHdr */ + tdsaSingleThreadedEnter(tiRoot, TD_ESGL_LOCK); + TDLIST_ENQUEUE_AT_TAIL(tdlist_to_fill, EsglListHdr); + tdsaSingleThreadedLeave(tiRoot, TD_ESGL_LOCK); + + + } /* end for */ + return; +} + + +/***************************************************************************** +*! \brief tdsaFreeEsglPages +* +* Purpose: This function frees the ESGL pages pointed to by EsglListHdr +* and puts them back onto the free list. +* +* \param tiRoot: Pointer to root data structure. +* \param EsglListHdr: pointer to list header where the pages to be freed +* are stored. +* +* \return: None +* +* \note - +* 1. This function removes all the pages from the list until the list +* empty and chains them at the end of the free list. +*****************************************************************************/ +osGLOBAL void +tdsaFreeEsglPages( + tiRoot_t *tiRoot, + tdList_t *EsglListHdr + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdsaEsglAllInfo_t *pEsglAllInfo = (tdsaEsglAllInfo_t *)&(tdsaAllShared->EsglAllInfo); + tdList_t *tdlist_to_free; + + TI_DBG6(("tdsaFreeEsglPages: start\n")); + if (tiRoot == agNULL) + { + TI_DBG1(("tdsaFreeEsglPages: tiRoot is NULL\n")); + return; + } + + if (EsglListHdr == agNULL) + { + TI_DBG1(("tdsaFreeEsglPages: EsglListHdr is NULL\n")); + return; + } + + TI_DBG6(("tdsaFreeEsglPages: EsglListHdr %p\n", EsglListHdr)); + tdsaSingleThreadedEnter(tiRoot, TD_ESGL_LOCK); + while (TDLIST_NOT_EMPTY(EsglListHdr)) + { + TDLIST_DEQUEUE_FROM_HEAD(&tdlist_to_free, EsglListHdr); + TDLIST_ENQUEUE_AT_TAIL(tdlist_to_free, &pEsglAllInfo->freelist); + pEsglAllInfo->NumFreeEsglPages++; + } + tdsaSingleThreadedLeave(tiRoot, TD_ESGL_LOCK); + TI_DBG6(("tdsaFreeEsglPages: NumFreeEsglPages %d\n", pEsglAllInfo->NumFreeEsglPages)); + return; +} + + +/***************************************************************************** +*! \brief tdsaGetEsglPagesInfo +* +* Purpose: This function gets the information about the size of ESGL pages +* and number pages to be configured. +* +* \param tiRoot: Pointer to root data structure. +* \param pPageSize: pointer to bit32 where pagesize information is to be +* stored +* \param pNumPages: Pointer to bit32 where number of pages information is +* to be stored +* +* \return: None +* +* \note - +* +*****************************************************************************/ +osGLOBAL void +tdsaGetEsglPagesInfo( + tiRoot_t *tiRoot, + bit32 *pPageSize, + bit32 *pNumPages + ) +{ + char *buffer; + bit32 buffLen; + bit32 lenRecv = 0; + char *pLastUsedChar = agNULL; + char globalStr[] = "Global"; + char SwParmsStr[] = "ESGLParms"; + char tmpBuffer[DEFAULT_KEY_BUFFER_SIZE]; + /* default value, defined in tdsatypes.h */ + bit32 NumEsglPages = NUM_ESGL_PAGES; + TI_DBG6(("tdsaGetEsglPagesInfo: start \n")); + + /* + calls ostiGetTransportParam which parses the configuration file to get + parameters. + */ + + buffer = tmpBuffer; + buffLen = sizeof(tmpBuffer); + + osti_memset(buffer, 0, buffLen); + + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "NumESGLPg", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + + NumEsglPages = osti_strtoul(buffer, &pLastUsedChar, 10); + } + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + TI_DBG6(("tdsaGetEsglPagesInfo: esgl page number %d\n",NumEsglPages)); + *pPageSize = ESGL_PAGES_SIZE;/* sizeof(agsaEsgl_t); defined in tdsatypes.h */ + *pNumPages = NumEsglPages; + + return; +} +#endif + + + + + + + + diff --git a/sys/dev/pms/RefTisa/tisa/sassata/common/tdhw.c b/sys/dev/pms/RefTisa/tisa/sassata/common/tdhw.c new file mode 100644 index 000000000000..059b1afe7ee2 --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/common/tdhw.c @@ -0,0 +1,95 @@ +/******************************************************************************* +** +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +/*******************************************************************************/ +/** \file + * + * This file contains hardware related functions + * + */ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#ifdef FDS_SM +#include +#include +#include +#endif + +#ifdef FDS_DM +#include +#include +#include +#endif + +#include +#include +#include + +#ifdef INITIATOR_DRIVER +#include +#include +#include +#endif + +#ifdef TARGET_DRIVER +#include +#include +#include +#endif + +#include +#include + +/***************************************************************************** +*! \biref tdsaReadHardwareInfo +* +* Purpose: This function reads the hardware information. This includes, +* PCI DeviceID, PCI VendorID, PCI Chip Revision, PCI Function +* Number. +* +* \param tiRoot: Pointer to driver/port instance. +* +* \return: None +* \note - just a place holder for now +*****************************************************************************/ +osGLOBAL void +tdsaReadHardwareInfo( + tiRoot_t *tiRoot + ) +{ + return; +} diff --git a/sys/dev/pms/RefTisa/tisa/sassata/common/tdinit.c b/sys/dev/pms/RefTisa/tisa/sassata/common/tdinit.c new file mode 100644 index 000000000000..89ac376caaff --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/common/tdinit.c @@ -0,0 +1,3496 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + + +********************************************************************************/ +/*******************************************************************************/ +/** \file + * + * This file contains the SAS/SATA TD layer initialization functions + * + */ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#ifdef FDS_SM +#include +#include +#include +#endif + +#ifdef FDS_DM +#include +#include +#include +#endif + +#include +#include +#include + +#ifdef INITIATOR_DRIVER +#include +#include +#include +#endif + +#ifdef TARGET_DRIVER +#include +#include +#include +#endif + +#include +#include + +LOCAL bit32 tdsaGetCardID(tiRoot_t * tiRoot); + + +bit32 tdCardIDList[TD_MAX_CARD_NUM] = { + TD_CARD_ID_FREE , TD_CARD_ID_FREE , + TD_CARD_ID_FREE , TD_CARD_ID_FREE , + TD_CARD_ID_FREE , TD_CARD_ID_FREE , + TD_CARD_ID_FREE , TD_CARD_ID_FREE , + TD_CARD_ID_FREE , TD_CARD_ID_FREE , + TD_CARD_ID_FREE , TD_CARD_ID_FREE , + TD_CARD_ID_FREE , TD_CARD_ID_FREE , + TD_CARD_ID_FREE , TD_CARD_ID_FREE , + TD_CARD_ID_FREE , TD_CARD_ID_FREE , + TD_CARD_ID_FREE , TD_CARD_ID_FREE +}; + +/***************************************************************************** +* +* tdsaGetCardID +* +* Purpose: +* +* Parameters: +* +* tiRoot: Pointer to driver/port instance. +* +* Return: +* tiSuccess : CardIDString was successfully read +* tiError : CardIDString reading failed +* +*****************************************************************************/ +bit32 tdsaGetCardID(tiRoot_t * tiRoot) +{ + bit32 i; + bit32 RetVal = 0xFFFFFFFF; + + for (i = 0 ; i < TD_MAX_CARD_NUM ; i++) + { + if (tdCardIDList[i] == TD_CARD_ID_FREE) + { + tdCardIDList[i] = TD_CARD_ID_ALLOC; + RetVal = i; + break; + } + } + + return RetVal; + +} /* tdsaGetCardID() */ + +/***************************************************************************** +* +* tdsaFreeCardID +* +* Purpose: +* +* Parameters: +* +* tiRoot: Pointer to driver/port instance. +* +* Return: +* tiSuccess : CardIDString was successfully read +* tiError : CardIDString reading failed +* +*****************************************************************************/ +osGLOBAL void +tdsaFreeCardID(tiRoot_t *tiRoot, bit32 CardID) +{ + OS_ASSERT(CardID < TD_MAX_CARD_NUM, "Invalid CardID\n"); + + tdCardIDList[CardID] = TD_CARD_ID_FREE; + + return; + +} /* tdFreeCardID() */ + +/***************************************************************************** +* +* tdsaGetCardIDString +* +* Purpose: +* +* Parameters: +* +* tiRoot: Pointer to driver/port instance. +* +* Return: +* tiSuccess : CardIDString was successfully read +* tiError : CardIDString reading failed +* +*****************************************************************************/ +bit32 tdsaGetCardIDString(tiRoot_t *tiRoot) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&(tdsaRoot->tdsaAllShared); + bit32 ret = tiError; + bit32 thisCardID = tdsaGetCardID(tiRoot); + char CardNum[10]; + + TI_DBG3(("tdsaGetCardIDString: start\n")); + + TI_DBG3(("tdsaGetCardIDString: thisCardID 0x%x\n", thisCardID)); + + + if (thisCardID == 0xFFFFFFFF) + { + TI_DBG1(("tdGetCardIDString: No more CardIDs available\n")); + ret = tiError; + } + else + { + tdsaAllShared->CardID = thisCardID; + osti_sprintf(CardNum,"CardNum%d", thisCardID); + TI_DBG3(("tdsaGetCardIDString: CardNum is %s\n", CardNum)); + osti_strcpy(tdsaAllShared->CardIDString, CardNum); + TI_DBG3(("tdsaGetCardIDString: tdsaAllShared->CardIDString is %s\n", tdsaAllShared->CardIDString)); + ret = tiSuccess; + + } + return ret; +} +/***************************************************************************** +*! \brief tiCOMGetResource +* +* Purpose: This function is called to determine the Transport +* Dependent Layer internal resource requirement. +* This function will internally call the initiator specific, +* target specific and shared TD resource requirement calls. +* +* \param tiRoot: Pointer to driver/port instance. +* \param loResource: Pointer to low level TSDK resource requirement. +* \param initiatorResource: Pointer to initiator functionality memory and +* option requirement. +* \param targetResource: Pointer to target functionality memory and +* option requirement. +* \param tdSharedMem: Pointer to cached memory required by the +* target/initiator shared functionality. +* +* \return None +* +* \note - This function only return the memory requirement in the tiMem_t +* structure in loResource, initiatorResource, targetResource +* and tdSharedMem. It does not allocate memory, so the address +* fields in tiMem_t are not used. +* +*****************************************************************************/ +osGLOBAL void +tiCOMGetResource( + tiRoot_t *tiRoot, + tiLoLevelResource_t *loResource, + tiInitiatorResource_t *initiatorResource, + tiTargetResource_t *targetResource, + tiTdSharedMem_t *tdSharedMem + ) +{ + TI_DBG6(("tiCOMGetResource start\n")); + TI_DBG6(("tiCOMGetResource: loResource %p\n", loResource)); + + if(loResource != agNULL) + { + tdsaLoLevelGetResource(tiRoot, loResource); + } + if(tdSharedMem != agNULL) + { + tdsaSharedMemCalculate(tiRoot, loResource, tdSharedMem); + } + +#ifdef INITIATOR_DRIVER + /* initiator */ + if(initiatorResource != agNULL) + { + itdssGetResource(tiRoot, initiatorResource); + /* + * for the time being set the initiator usecsPerTick + * same as lolevel usecsPerTick + */ + if (loResource == agNULL) + { + TI_DBG1(("tiCOMGetResource: loResource is NULL, wrong\n")); + return; + } + } +#endif + +#ifdef TARGET_DRIVER + /* target */ + if(targetResource != agNULL) + { + ttdssGetResource(tiRoot, targetResource); + } +#endif + + return; +} + + +/***************************************************************************** +*! \brief tiCOMInit +* +* Purpose: This function is called to initialize Transport Dependent Layer. +* This function will internally call the initiator specific, +* target specific and shared TD initialization calls. +* +* \param tiRoot: Pointer to target driver/port instance. +* \param loResource: Pointer to low level TSDK resource requirement. +* \param initiatorResource: Pointer to initiator functionality memory and +* option requirement. +* \param targetResource: Pointer to target functionality memory and +* option requirement. +* \param tdSharedMem: Pointer to cached memory required by the +* target/initiator shared functionality. +* +* \return: tiSuccess - if successful +* tiError - if failed +* +*****************************************************************************/ +osGLOBAL bit32 +tiCOMInit( + tiRoot_t *tiRoot, + tiLoLevelResource_t *loResource, + tiInitiatorResource_t *initiatorResource, + tiTargetResource_t *targetResource, + tiTdSharedMem_t *tdSharedMem ) +{ + tdsaRoot_t *tdsaRoot; + tdsaPortContext_t *tdsaPortContext; + tdsaDeviceData_t *tdsaDeviceData; + +#ifdef TD_INT_COALESCE + tdsaIntCoalesceContext_t *tdsaIntCoalCxt; +#endif + +#ifdef TD_DISCOVER + tdsaExpander_t *tdsaExpander; +#endif + + bit32 status = tiSuccess; + void *IniAddr = agNULL; + void *TgtAddr = agNULL; + tdsaContext_t *tdsaAllShared; +#if defined(TD_INT_COALESCE) || defined(TD_DISCOVER) || defined(TD_INTERNAL_DEBUG) + bit32 MaxTargets; +#endif +#ifdef TD_INTERNAL_DEBUG /* for debugging only */ + tdsaEsglAllInfo_t *pEsglAllInfo; + tdList_t *tdlist_to_fill; + tdsaEsglPageInfo_t *page_to_fill; +#endif + bit32 i; +#ifdef FDS_DM + dmSwConfig_t dmSwConfig; + static dmMemoryRequirement_t dmMemRequirement; + bit32 dmUsecsPerTick = 0; + bit32 dmMaxNumLocks = 0; +#endif + #ifdef FDS_SM + smSwConfig_t smSwConfig; + static smMemoryRequirement_t smMemRequirement; + bit32 smUsecsPerTick = 0; + bit32 smMaxNumLocks = 0; +#endif + + + /* for memory analysis */ + TI_DBG6(("ticominit: tdsaroot\n")); + TI_DBG6(("ticominit: tdsaRoot_t %d\n", (int)sizeof(tdsaRoot_t))); + TI_DBG6(("ticominit: tdsaEsglAllInfo_t %d\n", (int)sizeof(tdsaEsglAllInfo_t))); + TI_DBG6(("ticominit: portcontext\n")); + TI_DBG6(("ticominit: tdsaPortContext_t %d\n", (int)sizeof(tdsaPortContext_t))); + TI_DBG6(("ticominit: device data\n")); + TI_DBG6(("ticominit: tdsaDeviceData_t %d\n", (int)sizeof(tdsaDeviceData_t))); + TI_DBG6(("ticominit: agsaSASDeviceInfo_t %d\n", (int)sizeof(agsaSASDeviceInfo_t))); + TI_DBG6(("ticominit: satDeviceData_t %d\n", (int)sizeof(satDeviceData_t))); + TI_DBG6(("ticominit: agsaSATAIdentifyData_t %d\n", (int)sizeof(agsaSATAIdentifyData_t))); + + TI_DBG6(("ticominit: IO request body\n")); + TI_DBG6(("ticominit: tdIORequestBody_t %d\n", (int)sizeof(tdIORequestBody_t))); + TI_DBG6(("ticominit: tdssIOCompleted_t %d\n", (int)sizeof(tdssIOCompleted_t))); + TI_DBG6(("ticominit: agsaIORequest_t %d\n", (int)sizeof(agsaIORequest_t))); + + TI_DBG6(("ticominit: FOR SAS\n")); + TI_DBG6(("ticominit: agsaSASRequestBody_t %d\n", (int)sizeof(agsaSASRequestBody_t))); + TI_DBG6(("ticominit: FOR SATA\n")); + TI_DBG6(("ticominit: agsaSATAInitiatorRequest_t %d\n", (int)sizeof(agsaSATAInitiatorRequest_t))); + TI_DBG6(("ticominit: scsiRspSense_t %d\n", (int)sizeof(scsiRspSense_t))); + TI_DBG6(("ticominit: tiSenseData_t %d\n", (int)sizeof(tiSenseData_t))); + TI_DBG6(("ticominit: satIOContext_t %d\n", (int)sizeof(satIOContext_t))); + TI_DBG6(("ticominit: satInternalIo_t %d\n", (int)sizeof(satInternalIo_t))); + + + /************************************************************************* + * TD SHARED AREA + *************************************************************************/ + + TI_DBG6(("ticominit: start\n")); + + +#if defined(TD_INT_COALESCE) && defined(TD_DISCOVER) + + /* Let's start from the tdsaRoot */ + tdsaRoot = tdSharedMem->tdSharedCachedMem1.virtPtr; + tdsaPortContext = (tdsaPortContext_t *)((bitptr)tdSharedMem->tdSharedCachedMem1.virtPtr + sizeof(tdsaRoot_t)); + tdsaDeviceData = (tdsaDeviceData_t *)((bitptr)tdsaPortContext + (sizeof(tdsaPortContext_t) * TD_MAX_PORT_CONTEXT)); + + /* the following fn fills in MaxTargets */ + tdssGetMaxTargetsParams(tiRoot, &MaxTargets); + TI_DBG6(("tiCOMInit: MaxTargets %d\n", MaxTargets)); + + tdsaIntCoalCxt = + (tdsaIntCoalesceContext_t *)((bitptr)tdsaDeviceData + + (sizeof(tdsaDeviceData_t) * MaxTargets)); + + tdsaExpander = + (tdsaExpander_t *)((bitptr)tdsaIntCoalCxt + + (sizeof(tdsaIntCoalesceContext_t) * TD_MAX_INT_COALESCE)); + + +#elif defined(TD_INT_COALESCE) + + + + /* Let's start from the tdsaRoot */ + tdsaRoot = tdSharedMem->tdSharedCachedMem1.virtPtr; + tdsaPortContext = (tdsaPortContext_t *)((bitptr)tdSharedMem->tdSharedCachedMem1.virtPtr + sizeof(tdsaRoot_t)); + tdsaDeviceData = (tdsaDeviceData_t *)((bitptr)tdsaPortContext + (sizeof(tdsaPortContext_t) * TD_MAX_PORT_CONTEXT)); + + /* the following fn fills in MaxTargets */ + tdssGetMaxTargetsParams(tiRoot, &MaxTargets); + TI_DBG6(("tiCOMInit: MaxTargets %d\n", MaxTargets)); + + tdsaIntCoalCxt = + (tdsaIntCoalesceContext_t *)((bitptr)tdsaDeviceData + + (sizeof(tdsaDeviceData_t) * MaxTargets)); + + +#elif defined(TD_DISCOVER) + + + /* Let's start from the tdsaRoot */ + tdsaRoot = tdSharedMem->tdSharedCachedMem1.virtPtr; + tdsaPortContext = (tdsaPortContext_t *)((bitptr)tdSharedMem->tdSharedCachedMem1.virtPtr + sizeof(tdsaRoot_t)); + tdsaDeviceData = (tdsaDeviceData_t *)((bitptr)tdsaPortContext + (sizeof(tdsaPortContext_t) * TD_MAX_PORT_CONTEXT)); + + /* the following fn fills in MaxTargets */ + tdssGetMaxTargetsParams(tiRoot, &MaxTargets); + TI_DBG6(("tiCOMInit: MaxTargets %d\n", MaxTargets)); + + tdsaExpander = + (tdsaExpander_t *)((bitptr)tdsaDeviceData + + (sizeof(tdsaDeviceData_t) * MaxTargets)); + + + +#else + + /* Let's start from the tdsaRoot */ + tdsaRoot = tdSharedMem->tdSharedCachedMem1.virtPtr; + tdsaPortContext = (tdsaPortContext_t *)((bitptr)tdSharedMem->tdSharedCachedMem1.virtPtr + sizeof(tdsaRoot_t)); + tdsaDeviceData = (tdsaDeviceData_t *)((bitptr)tdsaPortContext + (sizeof(tdsaPortContext_t) * TD_MAX_PORT_CONTEXT)); + +#endif + + TI_DBG6(("tiCOMInit: ******* tdsaRoot %p tdsaPortContext %p tdsaDeviceData %p\n", tdsaRoot, tdsaPortContext, tdsaDeviceData)); + + + tiRoot->tdData = tdsaRoot; + tdsaAllShared = &(tdsaRoot->tdsaAllShared); + + +#ifdef INITIATOR_DRIVER + /**< Initialize initiator; itdssIni_t itself */ + if(initiatorResource) + { + IniAddr = initiatorResource->initiatorMem.tdCachedMem[0].virtPtr; + tdsaRoot->itdsaIni = IniAddr; + tdsaRoot->itdsaIni->tdsaAllShared = tdsaAllShared; + tdsaAllShared->itdsaIni = tdsaRoot->itdsaIni; + } +#endif + +#ifdef TARGET_DRIVER + /**< Initialize target; ttdssTgt_t itself */ + if(targetResource) + { + TgtAddr = targetResource->targetMem.tdMem[0].virtPtr; + tdsaRoot->ttdsaTgt = TgtAddr; + tdsaRoot->ttdsaTgt->tdsaAllShared = tdsaAllShared; + tdsaAllShared->ttdsaTgt = tdsaRoot->ttdsaTgt; + } +#endif /* target driver */ + + TI_DBG5(("tiCOMInit: IniAddr %p TgtAddr %p\n", IniAddr, TgtAddr)); + + TI_DBG3(("tiCOMInit: tdsaRoot %p tdsaAllShared %p \n",tdsaRoot, tdsaAllShared)); + + /**< Initialize the OS data part of the interrupt context agRoot */ + tdsaAllShared->agRootOsDataForInt.tiRoot = tiRoot; + tdsaAllShared->agRootOsDataForInt.tdsaAllShared = (void *) tdsaAllShared; + tdsaAllShared->agRootOsDataForInt.itdsaIni = (void *) IniAddr; + tdsaAllShared->agRootOsDataForInt.ttdsaTgt = (void *) TgtAddr; + /* for sata */ + tdsaAllShared->agRootOsDataForInt.tdstHost = agNULL; + tdsaAllShared->agRootOsDataForInt.tdstDevice = agNULL; + + /* tiInterruptContext is an enum value */ + tdsaAllShared->agRootOsDataForInt.IntContext = tiInterruptContext; + /* queueId or lockid in TD layer; LL maxlock + 1 since TD uses only one lock */ + + /* agsaRoot_t */ + tdsaAllShared->agRootInt.osData = + (void *) &(tdsaAllShared->agRootOsDataForInt); + tdsaAllShared->agRootInt.sdkData = agNULL; + + /**< Initialize the OS data part of the non-interrupt context agRoot */ + tdsaAllShared->agRootOsDataForNonInt.tiRoot = tiRoot; + tdsaAllShared->agRootOsDataForNonInt.tdsaAllShared = (void *) tdsaAllShared; + tdsaAllShared->agRootOsDataForNonInt.itdsaIni = (void *) IniAddr; + tdsaAllShared->agRootOsDataForNonInt.ttdsaTgt = (void *) TgtAddr; + /* for sata */ + tdsaAllShared->agRootOsDataForNonInt.tdstHost = agNULL; + tdsaAllShared->agRootOsDataForNonInt.tdstDevice = agNULL; + + tdsaAllShared->agRootOsDataForNonInt.IntContext = tiNonInterruptContext; + /* queueId or lockid in TD layer; LL maxlock + 1 since TD uses only one lock */ + + /* agsaRoot_t */ + tdsaAllShared->agRootNonInt.osData = + (void *) &(tdsaAllShared->agRootOsDataForNonInt); + tdsaAllShared->agRootNonInt.sdkData = agNULL; + + tdsaAllShared->loResource = *loResource; + + tdsaAllShared->PortContextMem = tdsaPortContext; + tdsaAllShared->DeviceMem = tdsaDeviceData; + + tdsaAllShared->IBQnumber = 0; + tdsaAllShared->OBQnumber = 0; + +#ifdef TD_INT_COALESCE + tdsaAllShared->IntCoalesce = tdsaIntCoalCxt; +#endif + +#ifdef TD_DISCOVER + tdsaAllShared->ExpanderHead = tdsaExpander; +#endif + + tdsaAllShared->MaxNumLocks = loResource->loLevelOption.numOfQueuesPerPort; + + tdsaAllShared->MaxNumOSLocks = loResource->loLevelOption.maxNumOSLocks; + +#if defined(FDS_DM) && defined(FDS_SM) + dmGetRequirements(agNULL, + &dmSwConfig, + &dmMemRequirement, + &dmUsecsPerTick, + &dmMaxNumLocks + ); + + tdsaAllShared->MaxNumDMLocks = dmMaxNumLocks; + TI_DBG2(("tiCOMInit: DM MaxNumDMLocks 0x%x\n", tdsaAllShared->MaxNumDMLocks)); + + smGetRequirements(agNULL, + &smSwConfig, + &smMemRequirement, + &smUsecsPerTick, + &smMaxNumLocks + ); + + tdsaAllShared->MaxNumSMLocks = smMaxNumLocks; + TI_DBG2(("tiCOMInit: SM MaxNumSMLocks 0x%x\n", tdsaAllShared->MaxNumSMLocks)); + + tdsaAllShared->MaxNumLLLocks = tdsaAllShared->MaxNumLocks - TD_MAX_LOCKS - tdsaAllShared->MaxNumDMLocks - tdsaAllShared->MaxNumSMLocks; + TI_DBG2(("tiCOMInit: LL MaxNumLLLocks 0x%x\n", tdsaAllShared->MaxNumLLLocks)); + +#elif defined(FDS_DM) + dmGetRequirements(agNULL, + &dmSwConfig, + &dmMemRequirement, + &dmUsecsPerTick, + &dmMaxNumLocks + ); + + tdsaAllShared->MaxNumDMLocks = dmMaxNumLocks; + TI_DBG2(("tiCOMInit: DM MaxNumDMLocks 0x%x\n", tdsaAllShared->MaxNumDMLocks)); + + tdsaAllShared->MaxNumLLLocks = tdsaAllShared->MaxNumLocks - TD_MAX_LOCKS - tdsaAllShared->MaxNumDMLocks; + TI_DBG2(("tiCOMInit: LL MaxNumLLLocks 0x%x\n", tdsaAllShared->MaxNumLLLocks)); +#elif defined(FDS_SM) + smGetRequirements(agNULL, + &smSwConfig, + &smMemRequirement, + &smUsecsPerTick, + &smMaxNumLocks + ); + + tdsaAllShared->MaxNumSMLocks = smMaxNumLocks; + TI_DBG2(("tiCOMInit: SM MaxNumSMLocks 0x%x\n", tdsaAllShared->MaxNumSMLocks)); + + tdsaAllShared->MaxNumLLLocks = tdsaAllShared->MaxNumLocks - TD_MAX_LOCKS - tdsaAllShared->MaxNumSMLocks; + TI_DBG2(("tiCOMInit: LL MaxNumLLLocks 0x%x\n", tdsaAllShared->MaxNumLLLocks)); +#else + tdsaAllShared->MaxNumLLLocks = tdsaAllShared->MaxNumLocks - TD_MAX_LOCKS; + TI_DBG2(("tiCOMInit: LL MaxNumLLLocks 0x%x\n", tdsaAllShared->MaxNumLLLocks)); +#endif + +#ifdef TBD + tdsaAllShared->MaxNumLLLocks = loResource->loLevelOption.numOfQueuesPerPort - TD_MAX_LOCKS; +#endif + + tdsaAllShared->resetCount = 0; + + /* used for saHwEventAck() and ossaDeregisterDeviceHandleCB() */ +// tdsaAllShared->EventValid = agFALSE; + for(i=0; ieventSource[i].EventValid = agFALSE; + tdsaAllShared->eventSource[i].Source.agPortContext = agNULL; + tdsaAllShared->eventSource[i].Source.event = 0; + /* phy ID */ + tdsaAllShared->eventSource[i].Source.param = 0xFF; + } + + +#ifdef TD_INTERNAL_DEBUG /* for debugging only */ + pEsglAllInfo = (tdsaEsglAllInfo_t *)&(tdsaAllShared->EsglAllInfo); +#endif + + /* initialize CardIDString */ + osti_strcpy(tdsaAllShared->CardIDString,""); + + +#ifdef FDS_DM + tdsaAllShared->dmRoot.tdData = tdsaRoot; +#endif + +#ifdef FDS_SM + tdsaAllShared->smRoot.tdData = tdsaRoot; +#endif + + /* get card ID */ + if (tdsaGetCardIDString(tiRoot) == tiError) + { + TI_DBG1(("tdsaGetCardIDString() failed\n")); + return tiError; + } + + /**< initializes jumptable */ + tdsaJumpTableInit(tiRoot); + + /**< initializes tdsaPortStartInfo_s including flags */ + tdssInitSASPortStartInfo(tiRoot); + + /* resets all the relevant flags */ + tdsaResetComMemFlags(tiRoot); + + /**< initializes timers */ + tdsaInitTimers(tiRoot); + + TI_DBG6(("ticominit: ******* before tdsaRoot %p tdsaPortContext %p tdsaDeviceData %p\n", tdsaRoot, tdsaPortContext, tdsaDeviceData)); + + + /**< initializes tdsaPortContext_t */ + tdsaPortContextInit(tiRoot); + + /**< initializes devicelist in tdsaPortContext_t */ + tdsaDeviceDataInit(tiRoot); + +#ifdef TD_INT_COALESCE + tdsaIntCoalCxtInit(tiRoot); +#endif + +#ifdef TD_DISCOVER + tdsaExpanderInit(tiRoot); +#endif + + tdsaQueueConfigInit(tiRoot); + +#ifdef TD_INTERNAL_DEBUG /* for debugging only */ + TI_DBG6(("ticominit: temp 1\n")); + TDLIST_DEQUEUE_FROM_HEAD(&tdlist_to_fill, &pEsglAllInfo->freelist); + /* get the pointer to the page from list pointer */ + page_to_fill = TDLIST_OBJECT_BASE(tdsaEsglPageInfo_t, tdlist, tdlist_to_fill); + TI_DBG6(("ticominit: pageinfo ID %d\n", page_to_fill->id)); + /* this does not work */ + TDLIST_ENQUEUE_AT_HEAD(tdlist_to_fill, &pEsglAllInfo->freelist); + + TI_DBG6(("ticominit: devide\n")); + TDLIST_DEQUEUE_FROM_HEAD(&tdlist_to_fill, &pEsglAllInfo->freelist); + /* get the pointer to the page from list pointer */ + page_to_fill = TDLIST_OBJECT_BASE(tdsaEsglPageInfo_t, tdlist, tdlist_to_fill); + TDINIT_PRINT("ticominit: second pageinfo ID %d\n", page_to_fill->id); + + TDLIST_ENQUEUE_AT_HEAD(tdlist_to_fill, &pEsglAllInfo->freelist); + +#endif + + +#ifdef INITIATOR_DRIVER + if(initiatorResource != agNULL) + { + tdsaAllShared->currentOperation |= TD_OPERATION_INITIATOR; + TI_DBG5(("tiCOMInit: calling itdssInit\n")); + status = itdssInit(tiRoot, initiatorResource, tdSharedMem); + + if(status != tiSuccess) + { + TI_DBG1(("tiCOMInit: itdInit FAILED\n")); + return status; + } + } +#endif + +#ifdef TARGET_DRIVER + if(targetResource != agNULL) + { + tdsaAllShared->currentOperation |= TD_OPERATION_TARGET; + TI_DBG5 (("tiCOMInit: calling ttdssInit\n")); + status = ttdssInit(tiRoot, targetResource, tdSharedMem); + + if(status != tiSuccess) + { + TI_DBG1(("tiCOMInit: ttdInit FAILED\n")); + return status; + } + } +#endif + + return status; +} + +/***************************************************************************** +*! \brief tdsaLoLevelGetResource +* +* Purpose: This function is called to determine the Transport +* Dependent Layer internal resource requirement used by the +* lower layer TSDK. +* +* \param tiRoot: Pointer to driver/port instance. +* \param loResource: Pointer to low level TSDK resource requirement. +* +* \return: None +* +* \note - currenlty mem[0] - mem[18] are being used +* +*****************************************************************************/ +/* + this calls ostiGetTransportParam which parses the configuration file to get + parameters. +*/ +osGLOBAL void +tdsaLoLevelGetResource( + tiRoot_t * tiRoot, + tiLoLevelResource_t * loResource) +{ + agsaRoot_t agRoot; + bit32 usecsPerTick = 0; + agsaSwConfig_t SwConfig; + static agsaQueueConfig_t QueueConfig; + static agsaMemoryRequirement_t memRequirement; + bit32 maxQueueSets = 0; + bit32 maxNumOSLocks = 0; + bit32 i; + + char *buffer; + bit32 buffLen; + bit32 lenRecv = 0; + char *pLastUsedChar = agNULL; + char globalStr[] = "Global"; + char iniParmsStr[] = "InitiatorParms"; + char SwParmsStr[] = "SWParms"; + char OBQueueProps[] = "OBQueueProps"; + char IBQueueProps[] = "IBQueueProps"; + + static char IBQueueSize[30]; + static char OBQueueSize[30]; + static char IBQueueEleSize[30]; + static char OBQueueEleSize[30]; + + static char OBQueueInterruptCount[30]; + static char OBQueueInterruptDelay[30]; + static char OBQueueInterruptEnable[30]; + static char IBQueuePriority[30]; + + + static char tmpBuffer[DEFAULT_KEY_BUFFER_SIZE]; + static bit32 InboundQueueSize[AGSA_MAX_OUTBOUND_Q]; + static bit32 OutboundQueueSize[AGSA_MAX_OUTBOUND_Q]; + static bit32 InboundQueueEleSize[AGSA_MAX_OUTBOUND_Q]; + static bit32 OutboundQueueEleSize[AGSA_MAX_OUTBOUND_Q]; + static bit32 InboundQueuePriority[AGSA_MAX_INBOUND_Q]; + static bit32 OutboundQueueInterruptDelay[AGSA_MAX_OUTBOUND_Q]; + static bit32 OutboundQueueInterruptCount[AGSA_MAX_OUTBOUND_Q]; + static bit32 OutboundQueueInterruptEnable[AGSA_MAX_OUTBOUND_Q]; + static bit32 cardID = 0; + char CardNum[10]; + +#ifdef FDS_DM + dmRoot_t dmRoot; + dmSwConfig_t dmSwConfig; + static dmMemoryRequirement_t dmMemRequirement; + bit32 dmUsecsPerTick = 0; + bit32 dmMaxNumLocks = 0; +#endif + +#ifdef FDS_SM + smRoot_t smRoot; + smSwConfig_t smSwConfig; + static smMemoryRequirement_t smMemRequirement; + bit32 smUsecsPerTick = 0; + bit32 smMaxNumLocks = 0; +#endif + + TI_DBG1(("tdsaLoLevelGetResource: start \n")); + TI_DBG6(("tdsaLoLevelGetResource: loResource %p\n", loResource)); + + osti_memset(&agRoot, 0, sizeof(agsaRoot_t)); + osti_memset(&QueueConfig, 0, sizeof(QueueConfig)); + osti_memset(&memRequirement, 0, sizeof(memRequirement)); + osti_memset(InboundQueueSize, 0, sizeof(InboundQueueSize)); + osti_memset(OutboundQueueSize, 0, sizeof(OutboundQueueSize)); + osti_memset(InboundQueueEleSize, 0, sizeof(InboundQueueEleSize)); + osti_memset(OutboundQueueEleSize, 0, sizeof(OutboundQueueEleSize)); + + memRequirement.count = 0; + + /* default values which are overwritten later */ + /* The followings are default values */ + SwConfig.maxActiveIOs = DEFAULT_MAX_ACTIVE_IOS; + SwConfig.numDevHandles = DEFAULT_MAX_DEV; + SwConfig.smpReqTimeout = DEFAULT_SMP_TIMEOUT; /* DEFAULT_VALUE; */ + SwConfig.numberOfEventRegClients = DEFAULT_NUM_REG_CLIENTS; + SwConfig.sizefEventLog1 = HOST_EVENT_LOG_SIZE; /* in KBytes */ + SwConfig.sizefEventLog2 = HOST_EVENT_LOG_SIZE; /* in KBytes */ + SwConfig.eventLog1Option = DEFAULT_EVENT_LOG_OPTION; + SwConfig.eventLog2Option = DEFAULT_EVENT_LOG_OPTION; + SwConfig.fatalErrorInterruptEnable = 1; + SwConfig.fatalErrorInterruptVector = 0; /* Was 1 */ + SwConfig.hostDirectAccessSupport = 0; + SwConfig.hostDirectAccessMode = 0; + SwConfig.FWConfig = 0; + SwConfig.enableDIF = agFALSE; + SwConfig.enableEncryption = agFALSE; + +#ifdef SA_CONFIG_MDFD_REGISTRY + SwConfig.disableMDF = agFALSE; +#endif /*SA_CONFIG_MDFD_REGISTRY*/ + +#if defined(SALLSDK_DEBUG) + SwConfig.sallDebugLevel = 1; /* DEFAULT_VALUE; */ +#endif + + +#ifdef SA_ENABLE_PCI_TRIGGER + SwConfig.PCI_trigger = 0; /* DEFAULT_VALUE; */ + #endif /* SA_ENABLE_PCI_TRIGGER */ + +#ifdef FDS_DM + /* defaults */ + dmMemRequirement.count = 0; + dmSwConfig.numDevHandles = DEFAULT_MAX_DEV; +#ifdef DM_DEBUG + dmSwConfig.DMDebugLevel = 1; +#endif +#endif + +#ifdef FDS_SM + /* defaults */ + smMemRequirement.count = 0; + smSwConfig.maxActiveIOs = DEFAULT_MAX_ACTIVE_IOS; + smSwConfig.numDevHandles = DEFAULT_MAX_DEV; +#ifdef SM_DEBUG + smSwConfig.SMDebugLevel = 1; +#endif +#endif + + buffer = tmpBuffer; + buffLen = sizeof(tmpBuffer); + + /* param3 points to QueueConfig; tdsaAllShared does not exit at this point yet */ + SwConfig.param3 = (void *)&QueueConfig; + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + globalStr, + iniParmsStr, + agNULL, + agNULL, + agNULL, + agNULL, + "MaxTargets", + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + SwConfig.numDevHandles = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + SwConfig.numDevHandles = osti_strtoul (buffer, &pLastUsedChar, 10); + } + TI_DBG2(("tdsaLoLevelGetResource: MaxTargets %d\n", SwConfig.numDevHandles)); + } + + + /* + * read the NumInboundQueue parameter + */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + QueueConfig.numInboundQueues = DEFAULT_NUM_INBOUND_QUEUE; /* default 1 Inbound queue */ + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "NumInboundQueues", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + QueueConfig.numInboundQueues = (bit16) osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + QueueConfig.numInboundQueues = (bit16) osti_strtoul (buffer, &pLastUsedChar, 10); + } + + if (QueueConfig.numInboundQueues > AGSA_MAX_INBOUND_Q) + { + QueueConfig.numInboundQueues = AGSA_MAX_INBOUND_Q; + } + } + + /* + * read the NumOutboundQueue parameter + */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + QueueConfig.numOutboundQueues = DEFAULT_NUM_OUTBOUND_QUEUE; /* default 1 Outbound queue */ + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "NumOutboundQueues", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + QueueConfig.numOutboundQueues = (bit16) osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + QueueConfig.numOutboundQueues = (bit16) osti_strtoul (buffer, &pLastUsedChar, 10); + } + + if (QueueConfig.numOutboundQueues > AGSA_MAX_OUTBOUND_Q) + { + QueueConfig.numOutboundQueues = AGSA_MAX_OUTBOUND_Q; + } + } + + /* + * read the MaxActiveIO parameter + */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "MaxActiveIO", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + SwConfig.maxActiveIOs = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + SwConfig.maxActiveIOs = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + + + + /* + * read the SMPTO parameter (SMP Timeout) + */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "SMPTO", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + SwConfig.smpReqTimeout = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + SwConfig.smpReqTimeout = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + + /* + * read the NumRegClients parameter + */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "NumRegClients", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + SwConfig.numberOfEventRegClients = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + SwConfig.numberOfEventRegClients = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + +#if defined(SALLSDK_DEBUG) + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "LLDebugLevel", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + SwConfig.sallDebugLevel = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + SwConfig.sallDebugLevel = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } +#endif + + +#if defined(DM_DEBUG) + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "DMDebugLevel", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + dmSwConfig.DMDebugLevel = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + dmSwConfig.DMDebugLevel = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } +#endif + +#if defined(SM_DEBUG) + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "SMDebugLevel", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + smSwConfig.SMDebugLevel = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + smSwConfig.SMDebugLevel = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } +#endif + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + for (i=0;iloLevelOption.maxNumOSLocks; + /* + MAX_LL_LAYER_MEM_DESCRIPTORS is 24. see tidefs.h and tiLoLevelMem_t + in titypes.h + */ +#if defined (FDS_DM) && defined (FDS_SM) + /* for LL */ + TI_DBG1(("tdsaLoLevelGetResource:MAX_LL_LAYER_MEM_DESCRIPTORS %d\n", MAX_LL_LAYER_MEM_DESCRIPTORS)); + for(i=0;iloLevelMem.mem[i].numElements = 0; + loResource->loLevelMem.mem[i].totalLength = 0; + loResource->loLevelMem.mem[i].singleElementLength = 0; + loResource->loLevelMem.mem[i].alignment = 0; + loResource->loLevelMem.mem[i].type = 0; + loResource->loLevelMem.mem[i].reserved = 0; + loResource->loLevelMem.mem[i].virtPtr = agNULL; + loResource->loLevelMem.mem[i].osHandle = agNULL; + loResource->loLevelMem.mem[i].physAddrUpper = 0; + loResource->loLevelMem.mem[i].physAddrLower = 0; + } + + TI_DBG1(("tdsaLoLevelGetResource:memRequirement.count %d\n", memRequirement.count)); + /* using the returned value from saGetRequirements */ + for (i=0;i< memRequirement.count;i++) + { + /* hardcoded values for now */ + loResource->loLevelMem.mem[i].numElements = memRequirement.agMemory[i].numElements; + loResource->loLevelMem.mem[i].totalLength = memRequirement.agMemory[i].totalLength; + loResource->loLevelMem.mem[i].singleElementLength = memRequirement.agMemory[i].singleElementLength; + loResource->loLevelMem.mem[i].alignment = memRequirement.agMemory[i].alignment; + TI_DBG2(("tdsaLoLevelGetResource: index %d numElements %d totalLength %d singleElementLength %d alignment %d\n", i, loResource->loLevelMem.mem[i].numElements, loResource->loLevelMem.mem[i].totalLength, loResource->loLevelMem.mem[i].singleElementLength,loResource->loLevelMem.mem[i].alignment )); + if ( AGSA_DMA_MEM == memRequirement.agMemory[i].type ) + { + loResource->loLevelMem.mem[i].type = TI_DMA_MEM; + TI_DBG6(("tdsaLoLevelGetResource: index %d TI_DMA_MEM\n", i)); + + } + else if ( AGSA_CACHED_MEM == memRequirement.agMemory[i].type ) + { + loResource->loLevelMem.mem[i].type = TI_CACHED_MEM; + TI_DBG6(("tdsaLoLevelGetResource: index %d TI_CACHED_MEM\n", i)); + } + else if ( AGSA_CACHED_DMA_MEM == memRequirement.agMemory[i].type ) + { + loResource->loLevelMem.mem[i].type = TI_CACHED_DMA_MEM; + TI_DBG6(("tdsaLoLevelGetResource: index %d TI_CACHED_DMA_MEM\n", i)); + } + } + + /* for DM */ + TI_DBG1(("tdsaLoLevelGetResource:dmMemRequirement.count %d\n", dmMemRequirement.count)); + /* using the returned value from dmGetRequirements */ + for (i=memRequirement.count;i< (memRequirement.count + dmMemRequirement.count);i++) + { + /* hardcoded values for now */ + loResource->loLevelMem.mem[i].numElements = dmMemRequirement.dmMemory[i-memRequirement.count].numElements; + loResource->loLevelMem.mem[i].totalLength = dmMemRequirement.dmMemory[i-memRequirement.count].totalLength; + loResource->loLevelMem.mem[i].singleElementLength = dmMemRequirement.dmMemory[i-memRequirement.count].singleElementLength; + loResource->loLevelMem.mem[i].alignment = dmMemRequirement.dmMemory[i-memRequirement.count].alignment; + TI_DBG2(("tdsaLoLevelGetResource: index %d numElements %d totalLength %d singleElementLength %d alignment %d\n", i, loResource->loLevelMem.mem[i].numElements, loResource->loLevelMem.mem[i].totalLength, loResource->loLevelMem.mem[i].singleElementLength,loResource->loLevelMem.mem[i].alignment )); + if ( AGSA_DMA_MEM == dmMemRequirement.dmMemory[i-memRequirement.count].type ) + { + loResource->loLevelMem.mem[i].type = TI_DMA_MEM; + TI_DBG6(("tdsaLoLevelGetResource: index %d TI_DMA_MEM\n", i)); + + } + else if ( AGSA_CACHED_MEM == dmMemRequirement.dmMemory[i-memRequirement.count].type ) + { + loResource->loLevelMem.mem[i].type = TI_CACHED_MEM; + TI_DBG6(("tdsaLoLevelGetResource: index %d TI_CACHED_MEM\n", i)); + } + else if ( AGSA_CACHED_DMA_MEM == dmMemRequirement.dmMemory[i-memRequirement.count].type ) + { + loResource->loLevelMem.mem[i].type = TI_CACHED_DMA_MEM; + TI_DBG6(("tdsaLoLevelGetResource: index %d TI_CACHED_DMA_MEM\n", i)); + } + } + + /* for SM */ + TI_DBG1(("tdsaLoLevelGetResource:smMemRequirement.count %d\n", smMemRequirement.count)); + /* using the returned value from dmGetRequirements */ + for (i=(memRequirement.count + dmMemRequirement.count);i< (memRequirement.count + dmMemRequirement.count + smMemRequirement.count);i++) + { + /* hardcoded values for now */ + loResource->loLevelMem.mem[i].numElements = smMemRequirement.smMemory[i-memRequirement.count-dmMemRequirement.count].numElements; + loResource->loLevelMem.mem[i].totalLength = smMemRequirement.smMemory[i-memRequirement.count-dmMemRequirement.count].totalLength; + loResource->loLevelMem.mem[i].singleElementLength = smMemRequirement.smMemory[i-memRequirement.count-dmMemRequirement.count].singleElementLength; + loResource->loLevelMem.mem[i].alignment = smMemRequirement.smMemory[i-memRequirement.count-dmMemRequirement.count].alignment; + TI_DBG2(("tdsaLoLevelGetResource: index %d numElements %d totalLength %d singleElementLength %d alignment %d\n", i, loResource->loLevelMem.mem[i].numElements, loResource->loLevelMem.mem[i].totalLength, loResource->loLevelMem.mem[i].singleElementLength,loResource->loLevelMem.mem[i].alignment )); + if ( AGSA_DMA_MEM == smMemRequirement.smMemory[i-memRequirement.count-dmMemRequirement.count].type ) + { + loResource->loLevelMem.mem[i].type = TI_DMA_MEM; + TI_DBG6(("tdsaLoLevelGetResource: index %d TI_DMA_MEM\n", i)); + + } + else if ( AGSA_CACHED_MEM == smMemRequirement.smMemory[i-memRequirement.count-dmMemRequirement.count].type ) + { + loResource->loLevelMem.mem[i].type = TI_CACHED_MEM; + TI_DBG6(("tdsaLoLevelGetResource: index %d TI_CACHED_MEM\n", i)); + } + else if ( AGSA_CACHED_DMA_MEM == smMemRequirement.smMemory[i-memRequirement.count-dmMemRequirement.count].type ) + { + loResource->loLevelMem.mem[i].type = TI_CACHED_DMA_MEM; + TI_DBG6(("tdsaLoLevelGetResource: index %d TI_CACHED_DMA_MEM\n", i)); + } + } + + /* sets the low level options */ + loResource->loLevelOption.usecsPerTick = MIN(MIN(usecsPerTick, dmUsecsPerTick), smUsecsPerTick); + loResource->loLevelOption.numOfQueuesPerPort = maxQueueSets + dmMaxNumLocks + smMaxNumLocks + TD_MAX_LOCKS + maxNumOSLocks; + loResource->loLevelOption.mutexLockUsage = tiOneMutexLockPerQueue; + /* no more ESGL */ + loResource->loLevelMem.count = memRequirement.count + dmMemRequirement.count + smMemRequirement.count; + /* setting interrupt requirements */ + loResource->loLevelOption.maxInterruptVectors = SwConfig.max_MSIX_InterruptVectors; + loResource->loLevelOption.max_MSI_InterruptVectors = SwConfig.max_MSI_InterruptVectors; + loResource->loLevelOption.flag = SwConfig.legacyInt_X; + TI_DBG2(("tdsaLoLevelGetResource: asking maxInterruptVectors(MSIX) %d \n", loResource->loLevelOption.maxInterruptVectors)); + TI_DBG2(("tdsaLoLevelGetResource: asking max_MSI_InterruptVectors %d \n", loResource->loLevelOption.max_MSI_InterruptVectors)); + TI_DBG2(("tdsaLoLevelGetResource: asking flag - legacyInt_X %d \n", loResource->loLevelOption.flag)); + +// TI_DBG6(("tdsaLoLevelGetResource: index %d numElements %d totalLength %d singleElementLength %d alignment %d\n",memRequirement.count, loResource->loLevelMem.mem[memRequirement.count].numElements,loResource->loLevelMem.mem[memRequirement.count].totalLength, loResource->loLevelMem.mem[memRequirement.count].singleElementLength,loResource->loLevelMem.mem[memRequirement.count].alignment )); + TI_DBG6(("tdsaLoLevelGetResource: total memRequirement count %d TI_DMA_MEM\n", loResource->loLevelMem.count)); + +#elif defined(FDS_DM) + TI_DBG1(("tdsaLoLevelGetResource:MAX_LL_LAYER_MEM_DESCRIPTORS %d\n", MAX_LL_LAYER_MEM_DESCRIPTORS)); + for(i=0;iloLevelMem.mem[i].numElements = 0; + loResource->loLevelMem.mem[i].totalLength = 0; + loResource->loLevelMem.mem[i].singleElementLength = 0; + loResource->loLevelMem.mem[i].alignment = 0; + loResource->loLevelMem.mem[i].type = 0; + loResource->loLevelMem.mem[i].reserved = 0; + loResource->loLevelMem.mem[i].virtPtr = agNULL; + loResource->loLevelMem.mem[i].osHandle = agNULL; + loResource->loLevelMem.mem[i].physAddrUpper = 0; + loResource->loLevelMem.mem[i].physAddrLower = 0; + } + + TI_DBG1(("tdsaLoLevelGetResource:memRequirement.count %d\n", memRequirement.count)); + /* using the returned value from saGetRequirements */ + for (i=0;i< memRequirement.count;i++) + { + /* hardcoded values for now */ + loResource->loLevelMem.mem[i].numElements = memRequirement.agMemory[i].numElements; + loResource->loLevelMem.mem[i].totalLength = memRequirement.agMemory[i].totalLength; + loResource->loLevelMem.mem[i].singleElementLength = memRequirement.agMemory[i].singleElementLength; + loResource->loLevelMem.mem[i].alignment = memRequirement.agMemory[i].alignment; + TI_DBG2(("tdsaLoLevelGetResource: index %d numElements %d totalLength %d singleElementLength %d alignment %d\n", i, loResource->loLevelMem.mem[i].numElements, loResource->loLevelMem.mem[i].totalLength, loResource->loLevelMem.mem[i].singleElementLength,loResource->loLevelMem.mem[i].alignment )); + if ( AGSA_DMA_MEM == memRequirement.agMemory[i].type ) + { + loResource->loLevelMem.mem[i].type = TI_DMA_MEM; + TI_DBG6(("tdsaLoLevelGetResource: index %d TI_DMA_MEM\n", i)); + + } + else if ( AGSA_CACHED_MEM == memRequirement.agMemory[i].type ) + { + loResource->loLevelMem.mem[i].type = TI_CACHED_MEM; + TI_DBG6(("tdsaLoLevelGetResource: index %d TI_CACHED_MEM\n", i)); + } + else if ( AGSA_CACHED_DMA_MEM == memRequirement.agMemory[i].type ) + { + loResource->loLevelMem.mem[i].type = TI_CACHED_DMA_MEM; + TI_DBG6(("tdsaLoLevelGetResource: index %d TI_CACHED_DMA_MEM\n", i)); + } + } + + TI_DBG1(("tdsaLoLevelGetResource:dmMemRequirement.count %d\n", dmMemRequirement.count)); + /* using the returned value from dmGetRequirements */ + for (i=memRequirement.count;i< (memRequirement.count + dmMemRequirement.count);i++) + { + /* hardcoded values for now */ + loResource->loLevelMem.mem[i].numElements = dmMemRequirement.dmMemory[i-memRequirement.count].numElements; + loResource->loLevelMem.mem[i].totalLength = dmMemRequirement.dmMemory[i-memRequirement.count].totalLength; + loResource->loLevelMem.mem[i].singleElementLength = dmMemRequirement.dmMemory[i-memRequirement.count].singleElementLength; + loResource->loLevelMem.mem[i].alignment = dmMemRequirement.dmMemory[i-memRequirement.count].alignment; + TI_DBG2(("tdsaLoLevelGetResource: index %d numElements %d totalLength %d singleElementLength %d alignment %d\n", i, loResource->loLevelMem.mem[i].numElements, loResource->loLevelMem.mem[i].totalLength, loResource->loLevelMem.mem[i].singleElementLength,loResource->loLevelMem.mem[i].alignment )); + if ( AGSA_DMA_MEM == dmMemRequirement.dmMemory[i-memRequirement.count].type ) + { + loResource->loLevelMem.mem[i].type = TI_DMA_MEM; + TI_DBG6(("tdsaLoLevelGetResource: index %d TI_DMA_MEM\n", i)); + + } + else if ( AGSA_CACHED_MEM == dmMemRequirement.dmMemory[i-memRequirement.count].type ) + { + loResource->loLevelMem.mem[i].type = TI_CACHED_MEM; + TI_DBG6(("tdsaLoLevelGetResource: index %d TI_CACHED_MEM\n", i)); + } + else if ( AGSA_CACHED_DMA_MEM == dmMemRequirement.dmMemory[i-memRequirement.count].type ) + { + loResource->loLevelMem.mem[i].type = TI_CACHED_DMA_MEM; + TI_DBG6(("tdsaLoLevelGetResource: index %d TI_CACHED_DMA_MEM\n", i)); + } + } + + + + /* sets the low level options */ + loResource->loLevelOption.usecsPerTick = MIN(usecsPerTick, dmUsecsPerTick); + loResource->loLevelOption.numOfQueuesPerPort = maxQueueSets + dmMaxNumLocks + TD_MAX_LOCKS + maxNumOSLocks; + loResource->loLevelOption.mutexLockUsage = tiOneMutexLockPerQueue; + /* no more ESGL */ + loResource->loLevelMem.count = memRequirement.count + dmMemRequirement.count; + /* setting interrupt requirements */ + loResource->loLevelOption.maxInterruptVectors = SwConfig.max_MSIX_InterruptVectors; + loResource->loLevelOption.max_MSI_InterruptVectors = SwConfig.max_MSI_InterruptVectors; + loResource->loLevelOption.flag = SwConfig.legacyInt_X; + TI_DBG2(("tdsaLoLevelGetResource: asking maxInterruptVectors(MSIX) %d \n", loResource->loLevelOption.maxInterruptVectors)); + TI_DBG2(("tdsaLoLevelGetResource: asking max_MSI_InterruptVectors %d \n", loResource->loLevelOption.max_MSI_InterruptVectors)); + TI_DBG2(("tdsaLoLevelGetResource: asking flag - legacyInt_X %d \n", loResource->loLevelOption.flag)); + +// TI_DBG6(("tdsaLoLevelGetResource: index %d numElements %d totalLength %d singleElementLength %d alignment %d\n",memRequirement.count, loResource->loLevelMem.mem[memRequirement.count].numElements,loResource->loLevelMem.mem[memRequirement.count].totalLength, loResource->loLevelMem.mem[memRequirement.count].singleElementLength,loResource->loLevelMem.mem[memRequirement.count].alignment )); + TI_DBG6(("tdsaLoLevelGetResource: total memRequirement count %d TI_DMA_MEM\n", loResource->loLevelMem.count)); + +#elif defined(FDS_SM) + TI_DBG1(("tdsaLoLevelGetResource:MAX_LL_LAYER_MEM_DESCRIPTORS %d\n", MAX_LL_LAYER_MEM_DESCRIPTORS)); + for(i=0;iloLevelMem.mem[i].numElements = 0; + loResource->loLevelMem.mem[i].totalLength = 0; + loResource->loLevelMem.mem[i].singleElementLength = 0; + loResource->loLevelMem.mem[i].alignment = 0; + loResource->loLevelMem.mem[i].type = 0; + loResource->loLevelMem.mem[i].reserved = 0; + loResource->loLevelMem.mem[i].virtPtr = agNULL; + loResource->loLevelMem.mem[i].osHandle = agNULL; + loResource->loLevelMem.mem[i].physAddrUpper = 0; + loResource->loLevelMem.mem[i].physAddrLower = 0; + } + + TI_DBG1(("tdsaLoLevelGetResource:memRequirement.count %d\n", memRequirement.count)); + /* using the returned value from saGetRequirements */ + for (i=0;i< memRequirement.count;i++) + { + /* hardcoded values for now */ + loResource->loLevelMem.mem[i].numElements = memRequirement.agMemory[i].numElements; + loResource->loLevelMem.mem[i].totalLength = memRequirement.agMemory[i].totalLength; + loResource->loLevelMem.mem[i].singleElementLength = memRequirement.agMemory[i].singleElementLength; + loResource->loLevelMem.mem[i].alignment = memRequirement.agMemory[i].alignment; + TI_DBG6(("tdsaLoLevelGetResource: index %d numElements %d totalLength %d singleElementLength %d alignment %d\n", i, loResource->loLevelMem.mem[i].numElements, loResource->loLevelMem.mem[i].totalLength, loResource->loLevelMem.mem[i].singleElementLength,loResource->loLevelMem.mem[i].alignment )); + if ( AGSA_DMA_MEM == memRequirement.agMemory[i].type ) + { + loResource->loLevelMem.mem[i].type = TI_DMA_MEM; + TI_DBG6(("tdsaLoLevelGetResource: index %d TI_DMA_MEM\n", i)); + + } + else if ( AGSA_CACHED_MEM == memRequirement.agMemory[i].type ) + { + loResource->loLevelMem.mem[i].type = TI_CACHED_MEM; + TI_DBG6(("tdsaLoLevelGetResource: index %d TI_CACHED_MEM\n", i)); + } + else if ( AGSA_CACHED_DMA_MEM == memRequirement.agMemory[i].type ) + { + loResource->loLevelMem.mem[i].type = TI_CACHED_DMA_MEM; + TI_DBG6(("tdsaLoLevelGetResource: index %d TI_CACHED_DMA_MEM\n", i)); + } + } + + TI_DBG1(("tdsaLoLevelGetResource:smMemRequirement.count %d\n", smMemRequirement.count)); + /* using the returned value from smGetRequirements */ + for (i=memRequirement.count;i< (memRequirement.count + smMemRequirement.count);i++) + { + /* hardcoded values for now */ + loResource->loLevelMem.mem[i].numElements = smMemRequirement.smMemory[i-memRequirement.count].numElements; + loResource->loLevelMem.mem[i].totalLength = smMemRequirement.smMemory[i-memRequirement.count].totalLength; + loResource->loLevelMem.mem[i].singleElementLength = smMemRequirement.smMemory[i-memRequirement.count].singleElementLength; + loResource->loLevelMem.mem[i].alignment = smMemRequirement.smMemory[i-memRequirement.count].alignment; + TI_DBG6(("tdsaLoLevelGetResource: index %d numElements %d totalLength %d singleElementLength %d alignment %d\n", i, loResource->loLevelMem.mem[i].numElements, loResource->loLevelMem.mem[i].totalLength, loResource->loLevelMem.mem[i].singleElementLength,loResource->loLevelMem.mem[i].alignment )); + if ( AGSA_DMA_MEM == smMemRequirement.smMemory[i-memRequirement.count].type ) + { + loResource->loLevelMem.mem[i].type = TI_DMA_MEM; + TI_DBG6(("tdsaLoLevelGetResource: index %d TI_DMA_MEM\n", i)); + + } + else if ( AGSA_CACHED_MEM == smMemRequirement.smMemory[i-memRequirement.count].type ) + { + loResource->loLevelMem.mem[i].type = TI_CACHED_MEM; + TI_DBG6(("tdsaLoLevelGetResource: index %d TI_CACHED_MEM\n", i)); + } + else if ( AGSA_CACHED_DMA_MEM == smMemRequirement.smMemory[i-memRequirement.count].type ) + { + loResource->loLevelMem.mem[i].type = TI_CACHED_DMA_MEM; + TI_DBG6(("tdsaLoLevelGetResource: index %d TI_CACHED_DMA_MEM\n", i)); + } + } + + + + /* sets the low level options */ + loResource->loLevelOption.usecsPerTick = MIN(usecsPerTick, smUsecsPerTick); + loResource->loLevelOption.numOfQueuesPerPort = maxQueueSets + smMaxNumLocks + TD_MAX_LOCKS + maxNumOSLocks; + loResource->loLevelOption.mutexLockUsage = tiOneMutexLockPerQueue; + /* no more ESGL */ + loResource->loLevelMem.count = memRequirement.count + smMemRequirement.count; + /* setting interrupt requirements */ + loResource->loLevelOption.maxInterruptVectors = SwConfig.max_MSIX_InterruptVectors; + loResource->loLevelOption.max_MSI_InterruptVectors = SwConfig.max_MSI_InterruptVectors; + loResource->loLevelOption.flag = SwConfig.legacyInt_X; + TI_DBG2(("tdsaLoLevelGetResource: asking maxInterruptVectors(MSIX) %d \n", loResource->loLevelOption.maxInterruptVectors)); + TI_DBG2(("tdsaLoLevelGetResource: asking max_MSI_InterruptVectors %d \n", loResource->loLevelOption.max_MSI_InterruptVectors)); + TI_DBG2(("tdsaLoLevelGetResource: asking flag - legacyInt_X %d \n", loResource->loLevelOption.flag)); + +// TI_DBG6(("tdsaLoLevelGetResource: index %d numElements %d totalLength %d singleElementLength %d alignment %d\n",memRequirement.count, loResource->loLevelMem.mem[memRequirement.count].numElements,loResource->loLevelMem.mem[memRequirement.count].totalLength, loResource->loLevelMem.mem[memRequirement.count].singleElementLength,loResource->loLevelMem.mem[memRequirement.count].alignment )); + TI_DBG6(("tdsaLoLevelGetResource: total memRequirement count %d TI_DMA_MEM\n", loResource->loLevelMem.count)); + + +#else + TI_DBG6(("tdsaLoLevelGetResource:MAX_LL_LAYER_MEM_DESCRIPTORS %d\n", MAX_LL_LAYER_MEM_DESCRIPTORS)); + for(i=0;iloLevelMem.mem[i].numElements = 0; + loResource->loLevelMem.mem[i].totalLength = 0; + loResource->loLevelMem.mem[i].singleElementLength = 0; + loResource->loLevelMem.mem[i].alignment = 0; + loResource->loLevelMem.mem[i].type = 0; + loResource->loLevelMem.mem[i].reserved = 0; + loResource->loLevelMem.mem[i].virtPtr = agNULL; + loResource->loLevelMem.mem[i].osHandle = agNULL; + loResource->loLevelMem.mem[i].physAddrUpper = 0; + loResource->loLevelMem.mem[i].physAddrLower = 0; + } + + /* using the returned value from saGetRequirements */ + for (i=0;i< memRequirement.count;i++) + { + /* hardcoded values for now */ + loResource->loLevelMem.mem[i].numElements = memRequirement.agMemory[i].numElements; + loResource->loLevelMem.mem[i].totalLength = memRequirement.agMemory[i].totalLength; + loResource->loLevelMem.mem[i].singleElementLength = memRequirement.agMemory[i].singleElementLength; + loResource->loLevelMem.mem[i].alignment = memRequirement.agMemory[i].alignment; + TI_DBG6(("tdsaLoLevelGetResource: index %d numElements %d totalLength %d singleElementLength %d alignment %d\n", i, loResource->loLevelMem.mem[i].numElements, loResource->loLevelMem.mem[i].totalLength, loResource->loLevelMem.mem[i].singleElementLength,loResource->loLevelMem.mem[i].alignment )); + if ( AGSA_DMA_MEM == memRequirement.agMemory[i].type ) + { + loResource->loLevelMem.mem[i].type = TI_DMA_MEM; + TI_DBG6(("tdsaLoLevelGetResource: index %d TI_DMA_MEM\n", i)); + + } + else if ( AGSA_CACHED_MEM == memRequirement.agMemory[i].type ) + { + loResource->loLevelMem.mem[i].type = TI_CACHED_MEM; + TI_DBG6(("tdsaLoLevelGetResource: index %d TI_CACHED_MEM\n", i)); + } + else if ( AGSA_CACHED_DMA_MEM == memRequirement.agMemory[i].type ) + { + loResource->loLevelMem.mem[i].type = TI_CACHED_DMA_MEM; + TI_DBG6(("tdsaLoLevelGetResource: index %d TI_CACHED_DMA_MEM\n", i)); + } + } + + + + /* sets the low level options */ + loResource->loLevelOption.usecsPerTick = usecsPerTick; + loResource->loLevelOption.numOfQueuesPerPort = maxQueueSets + TD_MAX_LOCKS + maxNumOSLocks; + loResource->loLevelOption.mutexLockUsage = tiOneMutexLockPerQueue; + /* no more ESGL */ + loResource->loLevelMem.count = memRequirement.count; + /* setting interrupt requirements */ + loResource->loLevelOption.maxInterruptVectors = SwConfig.max_MSIX_InterruptVectors; + loResource->loLevelOption.max_MSI_InterruptVectors = SwConfig.max_MSI_InterruptVectors; + loResource->loLevelOption.flag = SwConfig.legacyInt_X; + TI_DBG2(("tdsaLoLevelGetResource: asking maxInterruptVectors(MSIX) %d \n", loResource->loLevelOption.maxInterruptVectors)); + TI_DBG2(("tdsaLoLevelGetResource: asking max_MSI_InterruptVectors %d \n", loResource->loLevelOption.max_MSI_InterruptVectors)); + TI_DBG2(("tdsaLoLevelGetResource: asking flag - legacyInt_X %d \n", loResource->loLevelOption.flag)); + + TI_DBG6(("tdsaLoLevelGetResource: index %d numElements %d totalLength %d singleElementLength %d alignment %d\n",memRequirement.count, loResource->loLevelMem.mem[memRequirement.count].numElements,loResource->loLevelMem.mem[memRequirement.count].totalLength, loResource->loLevelMem.mem[memRequirement.count].singleElementLength,loResource->loLevelMem.mem[memRequirement.count].alignment )); + TI_DBG6(("tdsaLoLevelGetResource: memRequirement.count %d TI_DMA_MEM\n", memRequirement.count)); +#endif + + + + return; +} + +/***************************************************************************** +*! \brief tdsaSharedMemCalculate +* +* Purpose: This function is called to determine the Transport +* Dependent Layer internal resource requirement +* for shared memory between target and initiator +* functionality. +* +* \param tiRoot: Pointer to driver/port instance. +* \param tdSharedMem: Pointer to shared memory structure +* +* \return: None +* +* \note - The shared memory is composed of like the followings +* sizeof(tdsaRoot_t) +* + sizeof(tdsaPortContext_t) * TD_MAX_PORT_CONTEXT +* + sizeof(tdsaDeviceData_t) * MaxTargets +* + sizeof(tdsaEsglPageInfo_t) * NumEsglPages +* +*****************************************************************************/ +osGLOBAL void +tdsaSharedMemCalculate( + tiRoot_t * tiRoot, + tiLoLevelResource_t * loResource, + tiTdSharedMem_t * tdSharedMem + ) +{ + bit32 MaxTargets; + + /* the following fn fills in MaxTargets */ + tdssGetMaxTargetsParams(tiRoot, &MaxTargets); + TI_DBG6(("tdsaSharedMemCalculate: MaxTargets %d\n", MaxTargets)); + + /* + * Cached mem for the shared TD Layer functionality + */ + tdSharedMem->tdSharedCachedMem1.singleElementLength = + sizeof(tdsaRoot_t) + (sizeof(tdsaPortContext_t) * TD_MAX_PORT_CONTEXT) + + (sizeof(tdsaDeviceData_t) * MaxTargets); + +#ifdef TD_INT_COALESCE + /* adding TD interrupt coalesce data structure to the shared TD layer */ + /* TD_MAX_INT_COALESCE is defined to be 512 */ + tdSharedMem->tdSharedCachedMem1.singleElementLength += + sizeof(tdsaIntCoalesceContext_t) * TD_MAX_INT_COALESCE; +#endif + +#ifdef TD_DISCOVER + /* adding expander data strutures */ + tdSharedMem->tdSharedCachedMem1.singleElementLength += + sizeof(tdsaExpander_t) * MaxTargets; +#endif + + tdSharedMem->tdSharedCachedMem1.numElements = 1; + + tdSharedMem->tdSharedCachedMem1.totalLength = + tdSharedMem->tdSharedCachedMem1.singleElementLength * + tdSharedMem->tdSharedCachedMem1.numElements; + + tdSharedMem->tdSharedCachedMem1.alignment = 8; + + tdSharedMem->tdSharedCachedMem1.type = TI_CACHED_MEM; + + tdSharedMem->tdSharedCachedMem1.virtPtr = agNULL; + tdSharedMem->tdSharedCachedMem1.osHandle = agNULL; + tdSharedMem->tdSharedCachedMem1.physAddrUpper = 0; + tdSharedMem->tdSharedCachedMem1.physAddrLower = 0; + tdSharedMem->tdSharedCachedMem1.reserved = 0; + + return; +} + + +/***************************************************************************** +*! \biref tdResetComMemFlags +* +* Purpose: This function is called to reset all the flags for the port +* +* \param tiRoot: Pointer to driver/port instance. +* +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +tdsaResetComMemFlags( + tiRoot_t *tiRoot + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *)tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; +#ifdef TD_DEBUG_ENABLE + tdsaPortContext_t *tdsaPortContext = (tdsaPortContext_t *)tdsaAllShared->PortContextMem; + TI_DBG6(("tdsaResetComMemFlags: start\n")); + TI_DBG6(("tdsaResetComMemFlag:: ******* tdsaRoot %p \n", tdsaRoot)); + TI_DBG6(("tdsaResetComMemFlag:: ******* tdsaPortContext %p \n",tdsaPortContext)); +#endif + + tdsaAllShared->flags.sysIntsActive = agFALSE; + tdsaAllShared->flags.resetInProgress = agFALSE; + + return; +} + +/***************************************************************************** +*! \biref tdssInitSASPortStartInfo +* +* Purpose: This function sets information related to staring a port +* +* \param tiRoot: Pointer to driver/port instance. +* +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +tdssInitSASPortStartInfo( + tiRoot_t *tiRoot + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *)tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + int i; +#ifdef TD_DEBUG_ENABLE + tdsaPortContext_t *tdsaPortContext = (tdsaPortContext_t *)tdsaAllShared->PortContextMem; + TI_DBG6(("tdssInitSASPortStartInfo: start\n")); + + TI_DBG6(("tdssInitSASPortStartInfo: ******* tdsaRoot %p \n", tdsaRoot)); + TI_DBG6(("tdssInitSASPortStartInfo: ******* tdsaPortContext %p \n",tdsaPortContext)); +#endif + + for(i=0;iPorts[i].tiPortalContext = agNULL; + tdsaAllShared->Ports[i].portContext = agNULL; + tdsaAllShared->Ports[i].SASID.sasAddressHi[0] = 0; + tdsaAllShared->Ports[i].SASID.sasAddressHi[1] = 0; + tdsaAllShared->Ports[i].SASID.sasAddressHi[2] = 0; + tdsaAllShared->Ports[i].SASID.sasAddressHi[3] = 0; + tdsaAllShared->Ports[i].SASID.sasAddressLo[0] = 0; + tdsaAllShared->Ports[i].SASID.sasAddressLo[1] = 0; + tdsaAllShared->Ports[i].SASID.sasAddressLo[2] = 0; + tdsaAllShared->Ports[i].SASID.sasAddressLo[3] = 0; + tdsaAllShared->Ports[i].SASID.phyIdentifier = (bit8) i; + /* continue .... */ + + tdsaAllShared->Ports[i].flags.portStarted = agFALSE; + tdsaAllShared->Ports[i].flags.portInitialized = agFALSE; + tdsaAllShared->Ports[i].flags.portReadyForDiscoverySent = agFALSE; + tdsaAllShared->Ports[i].flags.portStoppedByOSLayer = agFALSE; + tdsaAllShared->Ports[i].flags.failPortInit = agFALSE; + } + + return; +} + + +/***************************************************************************** +*! \brief tdsaInitTimers +* +* Purpose: This function is called to initialize the timers +* for initiator +* +* \param tiRoot: pointer to the driver instance +* +* \return: None +* +* \note: +* +*****************************************************************************/ + +osGLOBAL void +tdsaInitTimers( + tiRoot_t *tiRoot + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *)tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; +#ifdef TD_DEBUG_ENABLE + tdsaPortContext_t *tdsaPortContext = (tdsaPortContext_t *)tdsaAllShared->PortContextMem; + + TI_DBG6(("tdsaInitTimers: start \n")); + TI_DBG6(("tdsaInitTimers: ******* tdsaRoot %p \n", tdsaRoot)); + TI_DBG6(("tdsaInitTimers: ******* tdsaPortContext %p \n",tdsaPortContext)); +#endif + + /* initialize the timerlist */ + TDLIST_INIT_HDR(&(tdsaAllShared->timerlist)); + + return; +} + + +/***************************************************************************** +*! \brief tdsaJumpTableInit +* +* Purpose: This function initializes SAS related callback functions +* +* \param tiRoot: pointer to the driver instance +* +* \return: None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaJumpTableInit( + tiRoot_t *tiRoot + ) +{ + + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *)tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; +#ifdef TD_DEBUG_ENABLE + tdsaPortContext_t *tdsaPortContext = (tdsaPortContext_t *)tdsaAllShared->PortContextMem; + + TI_DBG6(("tdsaJumpTableInit: start \n")); + TI_DBG6(("tdsaJumpTableInit:: ******* tdsaRoot %p \n", tdsaRoot)); + TI_DBG6(("tdsaJumpTableInit:: ******* tdsaPortContext %p \n",tdsaPortContext)); +#endif + + /* tdtype.h */ + /* + For combo, + pSSPIOCompleted, pSMPCompleted; use callback + pSSPReqReceive, pSMPReqReceived; use jumptable + */ + +#ifdef INITIATOR_DRIVER + tdsaAllShared->tdJumpTable.pSSPIOCompleted = agNULL; /* initiator */ + tdsaAllShared->tdJumpTable.pSMPCompleted =agNULL; /* initiator */ +#endif +#ifdef TARGET_DRIVER + tdsaAllShared->tdJumpTable.pSSPIOCompleted = agNULL; + tdsaAllShared->tdJumpTable.pSSPReqReceived = &ttdsaSSPReqReceived; + tdsaAllShared->tdJumpTable.pSMPReqReceived = &ttdsaSMPReqReceived; + tdsaAllShared->tdJumpTable.pSMPCompleted =agNULL; +#endif + tdsaAllShared->tdJumpTable.pGetSGLChunk = agNULL; + return; + +} + + +/***************************************************************************** +*! \brief tdsaPortContextInit +* +* Purpose: This function initializes port contexts. +* +* \param tiRoot: pointer to the driver instance +* +* \return: None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaPortContextInit( + tiRoot_t *tiRoot + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdsaPortContext_t *tdsaPortContext = (tdsaPortContext_t *)tdsaAllShared->PortContextMem; + int i = 0; + int j = 0; + + TI_DBG6(("tdsaPortContextInit: start\n")); + TI_DBG6(("tdsaPortContextInit: ******* sizeof(tdsaPortContext) %d %x\n", (int)sizeof(tdsaPortContext_t), (unsigned int)sizeof(tdsaPortContext_t))); + TI_DBG6(("tdsaPortContextInit: ******* tdsaRoot %p \n", tdsaRoot)); + TI_DBG6(("tdsaPortContextInit: ******* tdsaPortContext %p \n",tdsaPortContext)); + TI_DBG6(("tdsaPortContextInit: ******* tdsaPortContext+1 %p \n",tdsaPortContext + 1)); + TI_DBG6(("tdsaPortContextInit: ******* &tdsaPortContext[0] %p &tdsaPortContext[1] %p\n", &(tdsaPortContext[0]), &(tdsaPortContext[1]))); + + TDLIST_INIT_HDR(&(tdsaAllShared->MainPortContextList)); + TDLIST_INIT_HDR(&(tdsaAllShared->FreePortContextList)); + + for(i=0;iFreePortContextList)); + } + +#ifdef TD_INTERNAL_DEBUG /* for debugging only */ + for(i=0;idiscovery); + + onePortContext->discovery.type = TDSA_DISCOVERY_OPTION_FULL_START; + onePortContext->discovery.retries = 0; + onePortContext->discovery.configureRouteRetries = 0; + onePortContext->discovery.deviceRetistrationRetries = 0; + onePortContext->discovery.pendingSMP = 0; + onePortContext->discovery.SeenBC = agFALSE; + onePortContext->discovery.forcedOK = agFALSE; + onePortContext->discovery.SMPRetries = 0; + onePortContext->discovery.ResetTriggerred = agFALSE; + /* free expander lists */ + tdsaFreeAllExp(tiRoot, onePortContext); + /* kill the discovery-related timers if they are running */ + if (discovery->discoveryTimer.timerRunning == agTRUE) + { + tdsaKillTimer( + tiRoot, + &discovery->discoveryTimer + ); + } + if (discovery->configureRouteTimer.timerRunning == agTRUE) + { + tdsaKillTimer( + tiRoot, + &discovery->configureRouteTimer + ); + } + if (discovery->deviceRegistrationTimer.timerRunning == agTRUE) + { + tdsaKillTimer( + tiRoot, + &discovery->deviceRegistrationTimer + ); + } + if (discovery->BCTimer.timerRunning == agTRUE) + { + tdsaKillTimer( + tiRoot, + &discovery->BCTimer + ); + } + if (discovery->SMPBusyTimer.timerRunning == agTRUE) + { + tdsaKillTimer( + tiRoot, + &discovery->SMPBusyTimer + ); + } + if (discovery->DiscoverySMPTimer.timerRunning == agTRUE) + { + tdsaKillTimer( + tiRoot, + &discovery->DiscoverySMPTimer + ); + } +#endif + +#ifdef INITIATOR_DRIVER + onePortContext->DiscoveryState = ITD_DSTATE_NOT_STARTED; + onePortContext->nativeSATAMode = agFALSE; + onePortContext->directAttatchedSAS = agFALSE; + onePortContext->DiscoveryRdyGiven = agFALSE; + onePortContext->SeenLinkUp = agFALSE; +#endif + onePortContext->agPortContext->osData = agNULL; + onePortContext->agPortContext = agNULL; + onePortContext->tiPortalContext = agNULL; + onePortContext->agRoot = agNULL; + onePortContext->LinkRate = 0; + onePortContext->Count = 0; + onePortContext->valid = agFALSE; + for (j=0;jPhyIDList[j] = agFALSE; + } + onePortContext->RegisteredDevNums = 0; + onePortContext->eventPhyID = 0xFF; + onePortContext->Transient = agFALSE; + onePortContext->PortRecoverPhyID = 0xFF; + onePortContext->DiscFailNSeenBC = agFALSE; + +#ifdef FDS_DM + onePortContext->dmPortContext.tdData = onePortContext; + onePortContext->DMDiscoveryState = dmDiscCompleted; + onePortContext->UseDM = agFALSE; + onePortContext->UpdateMCN = agFALSE; +#endif + return; +} + +/***************************************************************************** +*! \brief tdsaDeviceDataInit +* +* Purpose: This function initializes devices +* +* \param tiRoot: pointer to the driver instance +* +* \return: None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaDeviceDataInit( + tiRoot_t *tiRoot + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; +#ifdef TD_DEBUG_ENABLE + tdsaPortContext_t *tdsaPortContext = (tdsaPortContext_t *)tdsaAllShared->PortContextMem; +#endif + tdsaDeviceData_t *tdsaDeviceData = + (tdsaDeviceData_t *)tdsaAllShared->DeviceMem; + int i; +#ifdef SATA_ENABLE + bit32 j; + satInternalIo_t *satIntIO; +#endif + bit32 MaxTargets; + + TI_DBG6(("tdsaDeviceDataInit: start\n")); + TI_DBG6(("tdsaDeviceDataInit: ******* tdsaPortContext %p \n",tdsaPortContext)); + TI_DBG6(("tdsaDeviceDataInit: ******* tdsaDeviceData %p\n", tdsaDeviceData)); + TI_DBG6(("tdsaDeviceDataInit: ******* tdsaDeviceData+1 %p\n", tdsaDeviceData+1)); + TI_DBG6(("tdsaDeviceDataInit: ******* &tdsaDeviceData[0] %p &tdsaDeviceData[1] %p\n", &(tdsaDeviceData[0]), &(tdsaDeviceData[1]))); + + /* the following fn fills in MaxTargets */ + tdssGetMaxTargetsParams(tiRoot, &MaxTargets); + TI_DBG6(("tdsaDeviceDataInit: MaxTargets %d\n", MaxTargets)); + + TDLIST_INIT_HDR(&(tdsaAllShared->MainDeviceList)); + TDLIST_INIT_HDR(&(tdsaAllShared->FreeDeviceList)); + + for(i=0;i<(int)MaxTargets;i++) + { + TDLIST_INIT_ELEMENT(&(tdsaDeviceData[i].FreeLink)); + TDLIST_INIT_ELEMENT(&(tdsaDeviceData[i].MainLink)); + TDLIST_INIT_ELEMENT(&(tdsaDeviceData[i].IncDisLink)); + tdsaDeviceData[i].id = i; + tdsaDeviceData[i].InQID = 0; + tdsaDeviceData[i].OutQID = 0; + tdsaDeviceData[i].DeviceType = TD_DEFAULT_DEVICE; + tdsaDeviceData[i].agRoot = agNULL; + tdsaDeviceData[i].agDevHandle = agNULL; + + tdsaDeviceData[i].pJumpTable = &(tdsaAllShared->tdJumpTable); + tdsaDeviceData[i].tiDeviceHandle.osData = agNULL; + tdsaDeviceData[i].tiDeviceHandle.tdData = &(tdsaDeviceData[i]); + tdsaDeviceData[i].tdPortContext = agNULL; + tdsaDeviceData[i].tdExpander = agNULL; + tdsaDeviceData[i].ExpDevice = agNULL; + tdsaDeviceData[i].phyID = 0xFF; + tdsaDeviceData[i].SASAddressID.sasAddressHi = 0; + tdsaDeviceData[i].SASAddressID.sasAddressLo = 0; + tdsaDeviceData[i].valid = agFALSE; + tdsaDeviceData[i].valid2 = agFALSE; + tdsaDeviceData[i].processed = agFALSE; + tdsaDeviceData[i].initiator_ssp_stp_smp = 0; + tdsaDeviceData[i].target_ssp_stp_smp = 0; + tdsaDeviceData[i].numOfPhys = 0; + tdsaDeviceData[i].registered = agFALSE; + tdsaDeviceData[i].directlyAttached = agFALSE; + tdsaDeviceData[i].SASSpecDeviceType = 0xFF; + tdsaDeviceData[i].IOStart = 0; + tdsaDeviceData[i].IOResponse = 0; + tdsaDeviceData[i].agDeviceResetContext.osData = agNULL; + tdsaDeviceData[i].agDeviceResetContext.sdkData = agNULL; + tdsaDeviceData[i].TRflag = agFALSE; + tdsaDeviceData[i].ResetCnt = 0; + tdsaDeviceData[i].OSAbortAll = agFALSE; + +#ifdef FDS_DM + tdsaDeviceData[i].devMCN = 1; + tdsaDeviceData[i].finalMCN = 1; +#endif + +#ifdef FDS_SM + tdsaDeviceData[i].SMNumOfFCA = 0; + tdsaDeviceData[i].SMNumOfID = 0; +#endif + +#ifdef SATA_ENABLE + TDLIST_INIT_HDR(&(tdsaDeviceData[i].satDevData.satIoLinkList)); + TDLIST_INIT_HDR(&(tdsaDeviceData[i].satDevData.satFreeIntIoLinkList)); + TDLIST_INIT_HDR(&(tdsaDeviceData[i].satDevData.satActiveIntIoLinkList)); + + /* default */ + tdsaDeviceData[i].satDevData.satDriveState = SAT_DEV_STATE_NORMAL; + tdsaDeviceData[i].satDevData.satNCQMaxIO =SAT_NCQ_MAX; + tdsaDeviceData[i].satDevData.satPendingIO = 0; + tdsaDeviceData[i].satDevData.satPendingNCQIO = 0; + tdsaDeviceData[i].satDevData.satPendingNONNCQIO = 0; + tdsaDeviceData[i].satDevData.IDDeviceValid = agFALSE; + tdsaDeviceData[i].satDevData.freeSATAFDMATagBitmap = 0; + tdsaDeviceData[i].satDevData.NumOfFCA = 0; + tdsaDeviceData[i].satDevData.NumOfIDRetries = 0; + tdsaDeviceData[i].satDevData.ID_Retries = 0; + tdsaDeviceData[i].satDevData.IDPending = agFALSE; + tdsaInitTimerRequest(tiRoot, &(tdsaDeviceData[i].SATAIDDeviceTimer)); +#ifdef FDS_SM + tdsaInitTimerRequest(tiRoot, &(tdsaDeviceData[i].tdIDTimer)); +#endif + osti_memset(tdsaDeviceData[i].satDevData.satMaxLBA, 0, sizeof(tdsaDeviceData[i].satDevData.satMaxLBA)); + + tdsaDeviceData[i].satDevData.satSaDeviceData = &tdsaDeviceData[i]; + satIntIO = &tdsaDeviceData[i].satDevData.satIntIo[0]; + for (j = 0; j < SAT_MAX_INT_IO; j++) + { + TDLIST_INIT_ELEMENT (&satIntIO->satIntIoLink); + TDLIST_ENQUEUE_AT_TAIL (&satIntIO->satIntIoLink, + &tdsaDeviceData[i].satDevData.satFreeIntIoLinkList); + satIntIO->satOrgTiIORequest = agNULL; + satIntIO->id = j; + satIntIO = satIntIO + 1; + } +#endif + /* some other variables */ + TDLIST_ENQUEUE_AT_TAIL(&(tdsaDeviceData[i].FreeLink), &(tdsaAllShared->FreeDeviceList)); + } + +#ifdef TD_INTERNAL_DEBUG /* for debugging only */ + for(i=0;itdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; +#ifdef SATA_ENABLE + int j=0; + satInternalIo_t *satIntIO; +#endif + + TI_DBG3(("tdsaDeviceDataReInit: start\n")); + + oneDeviceData->InQID = 0; + oneDeviceData->OutQID = 0; + oneDeviceData->DeviceType = TD_DEFAULT_DEVICE; + oneDeviceData->agDevHandle = agNULL; + + oneDeviceData->pJumpTable = &(tdsaAllShared->tdJumpTable); + oneDeviceData->tiDeviceHandle.osData = agNULL; + oneDeviceData->tiDeviceHandle.tdData = oneDeviceData; + oneDeviceData->tdPortContext = agNULL; + oneDeviceData->tdExpander = agNULL; + oneDeviceData->ExpDevice = agNULL; + oneDeviceData->phyID = 0xFF; + oneDeviceData->SASAddressID.sasAddressHi = 0; + oneDeviceData->SASAddressID.sasAddressLo = 0; + oneDeviceData->valid = agFALSE; + oneDeviceData->valid2 = agFALSE; + oneDeviceData->processed = agFALSE; + oneDeviceData->initiator_ssp_stp_smp = 0; + oneDeviceData->target_ssp_stp_smp = 0; + oneDeviceData->numOfPhys = 0; + oneDeviceData->registered = agFALSE; + oneDeviceData->directlyAttached = agFALSE; + oneDeviceData->SASSpecDeviceType = 0xFF; + oneDeviceData->IOStart = 0; + oneDeviceData->IOResponse = 0; + oneDeviceData->agDeviceResetContext.osData = agNULL; + oneDeviceData->agDeviceResetContext.sdkData = agNULL; + oneDeviceData->TRflag = agFALSE; + oneDeviceData->ResetCnt = 0; + oneDeviceData->OSAbortAll = agFALSE; + +#ifdef FDS_DM + oneDeviceData->devMCN = 1; + oneDeviceData->finalMCN = 1; +#endif + +#ifdef FDS_SM + oneDeviceData->SMNumOfFCA = 0; + oneDeviceData->SMNumOfID = 0; + if (oneDeviceData->tdIDTimer.timerRunning == agTRUE) + { + tdsaKillTimer( + tiRoot, + &oneDeviceData->tdIDTimer + ); + } +#endif + +#ifdef SATA_ENABLE + /* default */ + oneDeviceData->satDevData.satDriveState = SAT_DEV_STATE_NORMAL; + oneDeviceData->satDevData.satNCQMaxIO =SAT_NCQ_MAX; + oneDeviceData->satDevData.satPendingIO = 0; + oneDeviceData->satDevData.satPendingNCQIO = 0; + oneDeviceData->satDevData.satPendingNONNCQIO = 0; + oneDeviceData->satDevData.IDDeviceValid = agFALSE; + oneDeviceData->satDevData.freeSATAFDMATagBitmap = 0; + oneDeviceData->satDevData.NumOfFCA = 0; + oneDeviceData->satDevData.NumOfIDRetries = 0; + oneDeviceData->satDevData.ID_Retries = 0; + oneDeviceData->satDevData.IDPending = agFALSE; + + osti_memset(oneDeviceData->satDevData.satMaxLBA, 0, sizeof(oneDeviceData->satDevData.satMaxLBA)); + osti_memset(&(oneDeviceData->satDevData.satIdentifyData), 0xFF, sizeof(agsaSATAIdentifyData_t)); + + oneDeviceData->satDevData.satSaDeviceData = oneDeviceData; + + satIntIO = (satInternalIo_t *)&(oneDeviceData->satDevData.satIntIo[0]); + for (j = 0; j < SAT_MAX_INT_IO; j++) + { + TI_DBG3(("tdsaDeviceDataReInit: in loop of internal io free, id %d\n", satIntIO->id)); + satFreeIntIoResource(tiRoot, &(oneDeviceData->satDevData), satIntIO); + satIntIO = satIntIO + 1; + } +#endif + return; +} + +#ifdef TD_INT_COALESCE +/***************************************************************************** +*! \brief tdsaIntCoalCxtInit( +* +* Purpose: This function initializes interrupt coalesce contexts. +* +* \param tiRoot: pointer to the driver instance +* +* \return: None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaIntCoalCxtInit( + tiRoot_t *tiRoot + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdsaPortContext_t *tdsaPortContext = (tdsaPortContext_t *)tdsaAllShared->PortContext; + tdsaDeviceData_t *tdsaDeviceData = (tdsaDeviceData_t *)tdsaAllShared->DeviceDataHead; + tdsaIntCoalesceContext_t *tdsaIntCoalCxt = (tdsaIntCoalesceContext_t *)tdsaAllShared->IntCoalesce; + int i = 0; + int j = 0; + bit32 MaxTargets; + + TI_DBG2(("tdsaIntCoalCxtInit: start\n")); + TI_DBG6(("tdsaIntCoalCxtInit: ******* sizeof(tdsaPortContext) %d 0x%x\n", sizeof(tdsaPortContext_t), sizeof(tdsaPortContext_t))); + TI_DBG6(("tdsaIntCoalCxtInit: ******* sizeof(tdsaIntCoalCxt) %d 0x%x\n", sizeof(tdsaDeviceData_t), sizeof(tdsaDeviceData_t))); + TI_DBG6(("tdsaIntCoalCxtInit: ******* sizeof(tdsaIntCoalCxt) %d 0x%x\n", sizeof(tdsaIntCoalesceContext_t), sizeof(tdsaIntCoalesceContext_t))); + TI_DBG6(("tdsaIntCoalCxtInit: ******* tdsaRoot %p \n", tdsaRoot)); + TI_DBG6(("tdsaIntCoalCxtInit: ******* tdsaPortContext %p \n",tdsaPortContext)); + TI_DBG6(("tdsaDeviceDataInit: ******* tdsaDeviceData %p\n", tdsaDeviceData)); + TI_DBG6(("tdsaIntCoalCxtInit: ******* tdsaIntCoalCxt+1 %p \n", tdsaIntCoalCxt + 1)); + TI_DBG6(("tdsaIntCoalCxtInit: ******* &tdsaIntCoalCxt[0] %p &tdsaIntCoalCxt[1] %p\n", &(tdsaIntCoalCxt[0]), &(tdsaIntCoalCxt[1]))); + + /* for debug */ + TI_DBG6(("tdsaIntCoalCxtInit: TD_MAX_PORT_CONTEXT %d\n", TD_MAX_PORT_CONTEXT)); + /* the following fn fills in MaxTargets */ + tdssGetMaxTargetsParams(tiRoot, &MaxTargets); + TI_DBG6(("tdsaIntCoalCxtInit: MaxTargets %d\n", MaxTargets)); + + TI_DBG6(("tdsaIntCoalCxtInit: portcontext in sum 0x%x\n", sizeof(tdsaPortContext_t) * TD_MAX_PORT_CONTEXT)); + TI_DBG6(("tdsaIntCoalCxtInit: devicedata in sum 0x%x\n", sizeof(tdsaDeviceData_t) * MaxTargets)); + + /* + tdsaIntCoalCx[0] is just head, not an element + */ + TDLIST_INIT_HDR(&(tdsaIntCoalCxt[0].MainLink)); + TDLIST_INIT_HDR(&(tdsaIntCoalCxt[0].FreeLink)); + + tdsaIntCoalCxt[0].tdsaAllShared = tdsaAllShared; + tdsaIntCoalCxt[0].tiIntCoalesceCxt = agNULL; + tdsaIntCoalCxt[0].id = 0; + + + for(i=1;itdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + + tdsaExpander_t *tdsaExpander = + (tdsaExpander_t *)tdsaAllShared->ExpanderHead; + bit32 MaxTargets; + + + int i; + + TI_DBG6(("tdsaExpanderInit: start\n")); + tdssGetMaxTargetsParams(tiRoot, &MaxTargets); + TI_DBG6(("tdsaExpanderInit: MaxTargets %d\n", MaxTargets)); + + // TDLIST_INIT_HDR(&(tdsaAllShared->discoveringExpanderList)); + TDLIST_INIT_HDR(&(tdsaAllShared->freeExpanderList)); + + for(i=0;i<(int)MaxTargets;i++) + { + TDLIST_INIT_ELEMENT(&(tdsaExpander[i].linkNode)); + TDLIST_INIT_ELEMENT(&(tdsaExpander[i].upNode)); + /* initialize expander fields */ + tdsaExpander[i].tdDevice = agNULL; + tdsaExpander[i].tdUpStreamExpander = agNULL; + tdsaExpander[i].tdDeviceToProcess = agNULL; + tdsaExpander[i].tdCurrentDownStreamExpander = agNULL; + tdsaExpander[i].hasUpStreamDevice = agFALSE; + tdsaExpander[i].numOfUpStreamPhys = 0; + tdsaExpander[i].currentUpStreamPhyIndex = 0; + tdsaExpander[i].numOfDownStreamPhys = 0; + tdsaExpander[i].currentDownStreamPhyIndex = 0; + tdsaExpander[i].discoveringPhyId = 0; + tdsaExpander[i].underDiscovering = agFALSE; + tdsaExpander[i].id = i; + tdsaExpander[i].tdReturnginExpander = agNULL; + tdsaExpander[i].discoverSMPAllowed = agTRUE; + osti_memset( &(tdsaExpander[i].currentIndex), 0, sizeof(tdsaExpander[i].currentIndex)); + osti_memset( &(tdsaExpander[i].upStreamPhys), 0, sizeof(tdsaExpander[i].upStreamPhys)); + osti_memset( &(tdsaExpander[i].downStreamPhys), 0, sizeof(tdsaExpander[i].downStreamPhys)); + osti_memset( &(tdsaExpander[i].routingAttribute), 0, sizeof(tdsaExpander[i].routingAttribute)); + tdsaExpander[i].configSASAddrTableIndex = 0; + osti_memset( &(tdsaExpander[i].configSASAddressHiTable), 0, sizeof(tdsaExpander[i].configSASAddressHiTable)); + osti_memset( &(tdsaExpander[i].configSASAddressLoTable), 0, sizeof(tdsaExpander[i].configSASAddressLoTable)); + + + TDLIST_ENQUEUE_AT_TAIL(&(tdsaExpander[i].linkNode), &(tdsaAllShared->freeExpanderList)); + } + return; +} + +osGLOBAL void +tdsaQueueConfigInit( + tiRoot_t *tiRoot + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *)tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + + /* for memory index requirement */ + agsaQueueConfig_t *QueueConfig; + bit32 i; + + TI_DBG2(("tdsaQueueConfigInit: start\n")); + tdsaGetSwConfigParams(tiRoot); + QueueConfig = &tdsaAllShared->QueueConfig; + + for(i=0;inumInboundQueues;i++) + { + QueueConfig->inboundQueues[i].elementCount = tdsaAllShared->InboundQueueSize[i]; + QueueConfig->inboundQueues[i].elementSize = tdsaAllShared->InboundQueueEleSize[i]; + QueueConfig->inboundQueues[i].priority = tdsaAllShared->InboundQueuePriority[i]; + QueueConfig->inboundQueues[i].reserved = 0; + } + for(i=0;inumOutboundQueues;i++) + { + QueueConfig->outboundQueues[i].elementCount = tdsaAllShared->OutboundQueueSize[i]; + QueueConfig->outboundQueues[i].elementSize = tdsaAllShared->OutboundQueueEleSize[i]; + QueueConfig->outboundQueues[i].interruptDelay = tdsaAllShared->OutboundQueueInterruptDelay[i]; /* default 0; no interrupt delay */ + QueueConfig->outboundQueues[i].interruptCount = tdsaAllShared->OutboundQueueInterruptCount[i]; /* default 1*/ + QueueConfig->outboundQueues[i].interruptEnable = tdsaAllShared->OutboundQueueInterruptEnable[i]; /* default 1*/ + QueueConfig->outboundQueues[i].interruptVectorIndex = 0; + } + /* default */ + for (i=0;i<8;i++) + { + QueueConfig->sasHwEventQueue[i] = 0; + QueueConfig->sataNCQErrorEventQueue[i] = 0; + } + +#ifdef TARGET_DRIVER + for (i=0;i<8;i++) + { + QueueConfig->tgtITNexusEventQueue[i] = 0; + QueueConfig->tgtSSPEventQueue[i] = 0; + QueueConfig->tgtSMPEventQueue[i] = 0; + } +#endif + QueueConfig->iqNormalPriorityProcessingDepth = 0; + QueueConfig->iqHighPriorityProcessingDepth = 0; + QueueConfig->generalEventQueue = 0; + + return; +} + +/***************************************************************************** +*! \brief tdssGetMaxTargetsParams +* +* Purpose: This function is called to get default parameters from the +* OS Specific area. This function is called in the context of +* tiCOMGetResource() and tiCOMInit(). +* +* +* \param tiRoot: Pointer to initiator driver/port instance. +* \param option: Pointer to bit32 where the max target number is saved +* +* \return: None +* +* \note - +* +*****************************************************************************/ +osGLOBAL void +tdssGetMaxTargetsParams( + tiRoot_t *tiRoot, + bit32 *pMaxTargets + ) +{ + char *key = agNULL; + char *subkey1 = agNULL; + char *subkey2 = agNULL; + char *buffer; + bit32 buffLen; + bit32 lenRecv = 0; + char *pLastUsedChar = agNULL; + char tmpBuffer[DEFAULT_KEY_BUFFER_SIZE]; + char globalStr[] = "Global"; + char iniParmsStr[] = "InitiatorParms"; + bit32 MaxTargets; + + TI_DBG6(("tdssGetMaxTargetsParams: start\n")); + + *pMaxTargets = DEFAULT_MAX_DEV; + + /* to remove compiler warnings */ + pLastUsedChar = pLastUsedChar; + lenRecv = lenRecv; + subkey2 = subkey2; + subkey1 = subkey1; + key = key; + buffer = &tmpBuffer[0]; + buffLen = sizeof (tmpBuffer); + + osti_memset(buffer, 0, buffLen); + + /* defaults are overwritten in the following */ + /* Get MaxTargets */ + if ((ostiGetTransportParam( + tiRoot, + globalStr, + iniParmsStr, + agNULL, + agNULL, + agNULL, + agNULL, + "MaxTargets", + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + MaxTargets = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + MaxTargets = osti_strtoul (buffer, &pLastUsedChar, 10); + } + *pMaxTargets = MaxTargets; + TI_DBG2(("tdssGetMaxTargetsParams: MaxTargets %d\n", MaxTargets )); + } + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + return; +} + +/* temporary to distinguish SAS and SATA mode */ +osGLOBAL void +tdssGetSATAOnlyModeParams( + tiRoot_t *tiRoot, + bit32 *pSATAOnlyMode + ) +{ + char *key = agNULL; + char *subkey1 = agNULL; + char *subkey2 = agNULL; + char *buffer; + bit32 buffLen; + bit32 lenRecv = 0; + char *pLastUsedChar = agNULL; + char tmpBuffer[DEFAULT_KEY_BUFFER_SIZE]; + char globalStr[] = "Global"; + char iniParmsStr[] = "InitiatorParms"; + bit32 SATAOnlyMode; + + TI_DBG6(("tdssGetSATAOnlyModeParams: start\n")); + + *pSATAOnlyMode = agFALSE; /* default SAS and SATA */ + + /* to remove compiler warnings */ + pLastUsedChar = pLastUsedChar; + lenRecv = lenRecv; + subkey2 = subkey2; + subkey1 = subkey1; + key = key; + buffer = &tmpBuffer[0]; + buffLen = sizeof (tmpBuffer); + + osti_memset(buffer, 0, buffLen); + + /* defaults are overwritten in the following */ + /* Get SATAOnlyMode */ + if ((ostiGetTransportParam( + tiRoot, + globalStr, + iniParmsStr, + agNULL, + agNULL, + agNULL, + agNULL, + "SATAOnlyMode", + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + SATAOnlyMode = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + SATAOnlyMode = osti_strtoul (buffer, &pLastUsedChar, 10); + } + *pSATAOnlyMode = SATAOnlyMode; + } + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + return; +} + + diff --git a/sys/dev/pms/RefTisa/tisa/sassata/common/tdint.c b/sys/dev/pms/RefTisa/tisa/sassata/common/tdint.c new file mode 100644 index 000000000000..44bbe0fa1aae --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/common/tdint.c @@ -0,0 +1,263 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +/*******************************************************************************/ +/** \file + * + * + * This file contains interrupt related functions in the SAS/SATA TD layer + * + */ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#ifdef FDS_SM +#include +#include +#include +#endif + +#ifdef FDS_DM +#include +#include +#include +#endif + +#include +#include +#include + +#ifdef INITIATOR_DRIVER +#include +#include +#include +#endif + +#ifdef TARGET_DRIVER +#include +#include +#include +#endif + +#include +#include + +/***************************************************************************** +*! \biref tiCOMInterruptHandler +* +* Purpose: This function is called to service the hardware interrupt of the +* hardware. +* +* \param tiRoot: Pointer to initiator specific root data structure for this +* instance of the driver. +* +* \param channelNum: The zero-base channel number of the controller. +* 0xFFFFFFFF indicates that the OS-App Specific layer does +* not provide the channel number. The TD/LL Layer needs to +* discover of any of its own channels that are causing the +* interrupt. +* +* \return None +* +* \note - The only thing that this API will do is to acknowledge and mask +* the necessary hardware interrupt register. The actual processing +* of the interrupt handler is done in tiCOMDelayedInterruptHandler(). +* +*****************************************************************************/ +FORCEINLINE bit32 +tiCOMInterruptHandler( + tiRoot_t * tiRoot, + bit32 channelNum) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&(tdsaRoot->tdsaAllShared); + agsaRoot_t *agRoot = &(tdsaAllShared->agRootNonInt); + bit32 interruptPending = agFALSE; + + interruptPending = saInterruptHandler(agRoot, channelNum); + + return interruptPending; + +} /* tiCOMInterruptHandler() */ + + +/***************************************************************************** +*! \brief tiCOMDelayedInterruptHandler +* +* Purpose: This function is called to process the task associated with the +* interrupt handler. The task that this handler needs to do includes: +* completion of I/O, login event, error event, etc +* +* \param tiRoot: Pointer to initiator specific root data structure for +* this instance of the driver. +* \param channelNum: The zero-base channel number of the controller. +* 0xFFFFFFFF indicates that the OS-App Specific layer does +* not provide the channel number. The TD/LL Layer needs to +* discover of any of its own channels that are causing the +* interrupt. +* \param count: Count on how many items (such as IO completion) need to +* be processed in this context. +* \param interruptContext: The thread/process context within which this +* function is called. +* +* tiInterruptContext: this function is called within an +* interrupt context. +* tiNonInterruptContext: this function is called outside an +* interrupt context. +* \return None +* +*****************************************************************************/ +FORCEINLINE +bit32 +tiCOMDelayedInterruptHandler( + tiRoot_t *tiRoot, + bit32 channelNum, + bit32 count, + bit32 context + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&(tdsaRoot->tdsaAllShared); + agsaRoot_t *agRoot = agNULL; + bit32 completed = 0; + + TDSA_OUT_ENTER(tiRoot); + + if(context == tiInterruptContext) + { + agRoot = &(tdsaAllShared->agRootInt); + } + else + { + agRoot = &(tdsaAllShared->agRootNonInt); + } + + completed = saDelayedInterruptHandler(agRoot, channelNum, count); + + if(completed == 0) + { + TI_DBG3(("tiCOMDelayedInterruptHandler: processedMsgCount zero\n")); + } + + + TDSA_OUT_LEAVE(tiRoot); + + return(completed); +} /* tiCOMDelayedInterruptHandler() */ + + +/***************************************************************************** +*! \brief tiCOMSystemInterruptsActive +* +* Purpose: This function is called to indicate whether interrupts are +* active or not from this point in time. +* +* \param tiRoot: Pointer to initiator specific root data structure for +* this instance of the driver. +* \param sysIntsActive: Boolean value either true or false +* +* \return None +* +*****************************************************************************/ +osGLOBAL void +tiCOMSystemInterruptsActive( + tiRoot_t * tiRoot, + bit32 sysIntsActive + ) +{ + + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&(tdsaRoot->tdsaAllShared); + agsaRoot_t *agRoot; + agRoot = &(tdsaAllShared->agRootNonInt); + +#ifdef SPC_POLLINGMODE + if(sysIntsActive) return; +#endif /* SPC_POLLINGMODE */ + + tdsaAllShared->flags.sysIntsActive = sysIntsActive; + + TI_DBG6(("tiCOMSystemInterruptsActive: start\n")); + /* enable low level interrupts */ + if(agRoot->sdkData != agNULL) + { + saSystemInterruptsActive( + agRoot, + (agBOOLEAN) tdsaAllShared->flags.sysIntsActive + ); + } + + TI_DBG6(("tiCOMSystemInterruptsActive: end\n")); +} /* tiCOMSystemInterruptsActive */ + + +osGLOBAL void +tiComCountActiveIORequests( + tiRoot_t * tiRoot + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&(tdsaRoot->tdsaAllShared); + agsaRoot_t *agRoot; + agRoot = &(tdsaAllShared->agRootNonInt); + saCountActiveIORequests(agRoot ); +} + +/***************************************************************************** +*! \brief tiCOMInterruptEnable +* +* Purpose: This function is called to enable an interrupts on the specified channel +* active or not from this point in time. +* +* \param tiRoot: Pointer to initiator specific root data structure for +* this instance of the driver. +* \param : channelNum vector number for MSIX Zero for legacy interrupt +* +* \return None +* +*****************************************************************************/ +osGLOBAL FORCEINLINE +void +tiCOMInterruptEnable( + tiRoot_t * tiRoot, + bit32 channelNum) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&(tdsaRoot->tdsaAllShared); + agsaRoot_t *agRoot; + agRoot = &(tdsaAllShared->agRootNonInt); + + saSystemInterruptsEnable(agRoot, channelNum); +} diff --git a/sys/dev/pms/RefTisa/tisa/sassata/common/tdioctl.c b/sys/dev/pms/RefTisa/tisa/sassata/common/tdioctl.c new file mode 100644 index 000000000000..f1926806bfde --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/common/tdioctl.c @@ -0,0 +1,3682 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +/*******************************************************************************/ +/** \file + * + * + * This file contains Management IOCTL APIs + * + */ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#ifdef FDS_SM +#include +#include +#include +#endif + +#ifdef FDS_DM +#include +#include +#include +#endif + +#include +#include +#include +#include + +#ifdef INITIATOR_DRIVER +#include +#include +#include +#endif + +#ifdef TARGET_DRIVER +#include +#include +#include +#endif + +#include +#include +#include + +#include +#include +#include +#include +#include + + +#define agFieldOffset(baseType,fieldName) \ + /*lint -e545 */ \ + ((bit32)((bitptr)(&(((baseType *)0)->fieldName)))) \ + +#ifdef SA_LL_API_TEST +osGLOBAL bit32 tdLlApiTestIoctl(tiRoot_t *tiRoot, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2, + void *agParam3); +#endif /* SA_LL_API_TEST */ + + +extern bit32 volatile sgpioResponseSet; + +#ifdef SPC_ENABLE_PROFILE +/***************************************************************************** +* +* tdipFWProfileIoctl +* +* Purpose: This routine is called to process the FW Profile IOCTL function. +* This function is used for both target and initiator. +* +* Parameters: +* tiRoot: Pointer to driver instance +* agIOCTLPayload: Pointer to the IOCTL payload. +* agParam1: Pointer to pass context handle for IOCTL DMA operation +* agParam2: Pointer to pass context handle for IOCTL DMA operation +* agParam3: Pointer to pass context handle for IOCTL DMA operation +* +* Return: +* +* IOCTL_CALL_SUCCESS The requested operation completed successfully. +* IOCTL_CALL_FAIL Fail to complete the IOCTL request. +* Detail error code is function specific and +* defined by the specific IOCTL function. +* IOCTL_CALL_INVALID_CODE This IOCTL function is not recognized. +* +* +*****************************************************************************/ +osGLOBAL bit32 tdipFWProfileIoctl( + tiRoot_t *tiRoot, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2, + void *agParam3 + ) +{ + + bit32 status = IOCTL_CALL_SUCCESS; + bit32 bufAddrUpper = 0; + bit32 bufAddrLower = 0; + tdFWProfile_t *fwProfile; + + void *osMemHandle = agNULL; + void *buffer = agNULL; + agsaFwProfile_t fwProfileInfo = {0}; + + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + agsaRoot_t *agRoot = &tdsaAllShared->agRootInt; + + fwProfile = (tdFWProfile_t *)&agIOCTLPayload->FunctionSpecificArea[0]; + + + fwProfileInfo.processor = fwProfile->processor; + fwProfileInfo.cmd = fwProfile->cmd; + fwProfileInfo.len = fwProfile->len; + fwProfileInfo.tcid = fwProfile->tcid; + if(fwProfile->cmd == START_CODE_PROFILE) + { + fwProfileInfo.codeStartAdd = fwProfile->codeStartAdd; + fwProfileInfo.codeEndAdd = fwProfile->codeEndAdd; + } + if((fwProfile->cmd == STOP_TIMER_PROFILE) || (fwProfile->cmd == STOP_CODE_PROFILE)) + { + if(fwProfile->len != 0) + { + if(ostiAllocMemory( tiRoot, + &osMemHandle, + (void **)&buffer, + &bufAddrUpper, + &bufAddrLower, + 8, + fwProfile->len, + agFALSE)) + { + return IOCTL_CALL_FAIL; + } + osti_memset((void *)buffer, 0, fwProfile->len); + } + fwProfileInfo.agSgl.sgLower = bufAddrLower; + fwProfileInfo.agSgl.sgUpper = bufAddrUpper; + fwProfileInfo.agSgl.len = fwProfile->len; + fwProfileInfo.agSgl.extReserved = 0; + tdsaAllShared->tdFWProfileEx.buffer = osMemHandle; + tdsaAllShared->tdFWProfileEx.virtAddr = buffer; + tdsaAllShared->tdFWProfileEx.len = fwProfile->len; + } + tdsaAllShared->tdFWProfileEx.tdFWProfile = fwProfile; + tdsaAllShared->tdFWProfileEx.param1 = agParam1; + tdsaAllShared->tdFWProfileEx.param2 = agParam2; + tdsaAllShared->tdFWProfileEx.payload = agIOCTLPayload; + tdsaAllShared->tdFWProfileEx.inProgress = 1; + status = saFwProfile(agRoot, + agNULL, + 0, + &fwProfileInfo + ); + if(status) + { + if((fwProfile->cmd == STOP_TIMER_PROFILE) || (fwProfile->cmd == STOP_CODE_PROFILE)) + ostiFreeMemory(tiRoot, osMemHandle, fwProfile->len); + status = IOCTL_CALL_FAIL; + } + else + status = IOCTL_CALL_PENDING; + return status; +} + + +#endif + +/***************************************************************************** +* +* tdipFWControlIoctl +* +* Purpose: This routine is called to process the FW control IOCTL function. +* This function is used for both target and initiator. +* +* Parameters: +* tiRoot: Pointer to driver instance +* agIOCTLPayload: Pointer to the IOCTL payload. +* agParam1: Pointer to pass context handle for IOCTL DMA operation +* agParam2: Pointer to pass context handle for IOCTL DMA operation +* agParam3: Pointer to pass context handle for IOCTL DMA operation +* +* Return: +* +* IOCTL_CALL_SUCCESS The requested operation completed successfully. +* IOCTL_CALL_FAIL Fail to complete the IOCTL request. +* Detail error code is function specific and +* defined by the specific IOCTL function. +* IOCTL_CALL_PENDING This request is asynchronous and completed +* in some other context. +* IOCTL_CALL_INVALID_CODE This IOCTL function is not recognized. +* +* +*****************************************************************************/ +osGLOBAL bit32 tdipFWControlIoctl( + tiRoot_t *tiRoot, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2, + void *agParam3 + ) { + + bit32 status = IOCTL_CALL_PENDING; + bit32 bufAddrUpper = 0; + bit32 bufAddrLower = 0; + tdFWControl_t *fwControl; + void *osMemHandle = agNULL; + void *buffer = agNULL; + agsaUpdateFwFlash_t flashUpdateInfo; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + agsaRoot_t *agRoot = &tdsaAllShared->agRootInt; + + if( agIOCTLPayload->Length < + ( agFieldOffset(tiIOCTLPayload_t, FunctionSpecificArea) + + sizeof(tdFWControl_t) ) ) { + agIOCTLPayload->Status = IOCTL_ERR_STATUS_INTERNAL_ERROR; + status = IOCTL_CALL_FAIL; + return status; + } + fwControl = (tdFWControl_t *)&agIOCTLPayload->FunctionSpecificArea[0]; + + if(fwControl->len != 0) + { + if(ostiAllocMemory( tiRoot, + &osMemHandle, + (void **)&buffer, + &bufAddrUpper, + &bufAddrLower, + 8, + fwControl->len, + agFALSE) ) + return IOCTL_CALL_FAIL; + } + osti_memset( (void *)buffer, 0, fwControl->len ); + osti_memcpy( (void *)buffer, + fwControl->buffer, + fwControl->len ); + flashUpdateInfo.agSgl.sgLower = bufAddrLower; + flashUpdateInfo.agSgl.sgUpper = bufAddrUpper; + flashUpdateInfo.agSgl.len = fwControl->len; + flashUpdateInfo.agSgl.extReserved = 0; + flashUpdateInfo.currentImageOffset = fwControl->offset; + flashUpdateInfo.currentImageLen = fwControl->len; + flashUpdateInfo.totalImageLen = fwControl->size; + switch (agIOCTLPayload->MinorFunction) + { + case IOCTL_MN_FW_DOWNLOAD_DATA: + { + TI_DBG6(("tdipFWControlIoctl: calling saFwFlashUpdate\n")); + tdsaAllShared->tdFWControlEx.tdFWControl = fwControl; + tdsaAllShared->tdFWControlEx.buffer = osMemHandle; + tdsaAllShared->tdFWControlEx.param1 = agParam1; + tdsaAllShared->tdFWControlEx.param2 = agParam2; + tdsaAllShared->tdFWControlEx.payload = agIOCTLPayload; + tdsaAllShared->tdFWControlEx.inProgress = 1; + status = saFwFlashUpdate( agRoot, + agNULL, + 0, + &flashUpdateInfo ); + if(status) { + status = IOCTL_CALL_FAIL; + fwControl->retcode = IOCTL_CALL_TIMEOUT; + } + else { + status = IOCTL_CALL_PENDING; + } + break; + } + default: + status = IOCTL_CALL_INVALID_CODE; + TI_DBG1( ("tdipFWControlIoctl: ERROR: Wrong IOCTL code %d\n", + agIOCTLPayload->MinorFunction) ); + ostiFreeMemory(tiRoot, osMemHandle, fwControl->len); + return status; + } /* end IOCTL switch */ + return status; +} /* tdipFWControlIoctl */ + + +/***************************************************************************** +* +* tiCOMMgntIOCTL +* +* Purpose: This routine is a TISA API for processing the PMC specific +* IOCTL function. +* +* Each IOCTL function is identified by the IOCTL header +* specified in the data payload as the following: +* Field Description +* ----- ----------- +* Signature PMC IOCTL signature. +* #define PMC_IOCTL_SIGNATURE 0x1234 +* MajorFunction Major function number. +* MinorFunction Minor function number. +* Length Length of this structure in bytes. +* Status Return status for this IOCTL function. +* FunctionSpecificArea Variable length function specific area. +* +* Parameters: +* tiRoot: Pointer to driver instance +* agIOCTLPayload: Pointer to the IOCTL payload. +* agParam1: Pointer to pass context handle for IOCTL DMA operation +* agParam2: Pointer to pass context handle for IOCTL DMA operation +* agParam3: Pointer to pass context handle for IOCTL DMA operation +* +* Return: +* +* IOCTL_CALL_SUCCESS The requested operation completed successfully. +* IOCTL_CALL_FAIL Fail to complete the IOCTL request. +* Detail error code is function specific and +* defined by the specific IOCTL function. +* IOCTL_CALL_PENDING This request is asynchronous and completed +* in some other context. +* IOCTL_CALL_INVALID_CODE This IOCTL function is not recognized. +* IOCTL_CALL_INVALID_DEVICE Invalid target or destination device. +* +* Note: +* Used ostiAllocMemory() OS layer callback function to allocate memory +* for DMA operaion. Then use ostiFreeMemory() to deallocate the memory. +* +*****************************************************************************/ +osGLOBAL bit32 +tiCOMMgntIOCTL( + tiRoot_t *tiRoot, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2, + void *agParam3 + ) +{ + bit32 status = IOCTL_CALL_INVALID_CODE; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + agsaRoot_t *agRoot = &(tdsaAllShared->agRootNonInt); + bit32 EventLogLength = 0; + bit32 EventLogOption; + bit32 ReadLength = 0; + bit32 Offset = 0; + bit32 RequestLength = 0; /* user request on how much data to pass to application */ + agsaContext_t *agContext = NULL; + bit8 *loc = 0; + + TI_DBG3(("tiCOMMgntIOCTL: start\n")); + + TI_DBG3(("tiCOMMgntIOCTL: tiRoot %p agIOCTLPayload %p agParam1 %p agParam2 %p agParam3 %p\n", + tiRoot,agIOCTLPayload,agParam1,agParam2,agParam3 )); + + TI_DBG3(("tiCOMMgntIOCTL: Signature %X\ntiCOMMgntIOCTL: MajorFunction 0x%X\ntiCOMMgntIOCTL: MinorFunction 0x%X\ntiCOMMgntIOCTL: Length 0x%X\ntiCOMMgntIOCTL: Status 0x%X\ntiCOMMgntIOCTL: Reserved 0x%X\ntiCOMMgntIOCTL: FunctionSpecificArea 0x%X\n", + agIOCTLPayload->Signature, + agIOCTLPayload->MajorFunction, + agIOCTLPayload->MinorFunction, + agIOCTLPayload->Length, + agIOCTLPayload->Status, + agIOCTLPayload->Reserved, + agIOCTLPayload->FunctionSpecificArea[0] )); + + /* PMC IOCTL signatures matched ? */ + if(agIOCTLPayload->Signature != PMC_IOCTL_SIGNATURE) + { + TI_DBG1(("tiCOMMgntIOCTL:agIOCTLPayload->Signature %x IOCTL_CALL_INVALID_CODE\n",agIOCTLPayload->Signature )); + status = IOCTL_CALL_INVALID_CODE; + return (status); + } + + switch (agIOCTLPayload->MajorFunction) + { +//TODO: make the card identification more robust. For now - just to keep going with FW download +#ifdef IOCTL_INTERRUPT_TIME_CONFIG + case IOCTL_MJ_CARD_PARAMETER: + { + switch( agIOCTLPayload->MinorFunction ) + { + case IOCTL_MN_CARD_GET_INTERRUPT_CONFIG: + { + agsaInterruptConfigPage_t *pInterruptConfig = (agsaInterruptConfigPage_t *)&agIOCTLPayload->FunctionSpecificArea[0]; + status = saGetControllerConfig(agRoot, + 0, + AGSA_INTERRUPT_CONFIGURATION_PAGE, + pInterruptConfig->vectorMask0, + pInterruptConfig->vectorMask1, + agParam2); + if(status == AGSA_RC_SUCCESS) { + status = IOCTL_CALL_PENDING; + agIOCTLPayload->Status = IOCTL_ERR_STATUS_OK; + } else { + agIOCTLPayload->Status = IOCTL_ERR_STATUS_INTERNAL_ERROR; + } + break; + } + case IOCTL_MN_CARD_GET_TIMER_CONFIG: + status = saGetControllerConfig(agRoot, 0, AGSA_SAS_PROTOCOL_TIMER_CONFIG_PAGE, 0, 0, agParam2); + if(status == AGSA_RC_SUCCESS) { + status = IOCTL_CALL_PENDING; + agIOCTLPayload->Status = IOCTL_ERR_STATUS_OK; + } else { + agIOCTLPayload->Status = IOCTL_ERR_STATUS_INTERNAL_ERROR; + } + break; + } + break; + } +#endif /* IOCTL_INTERRUPT_TIME_CONFIG */ + case IOCTL_MJ_INI_DRIVER_IDENTIFY: + { + status=IOCTL_CALL_SUCCESS; + break; + } + case IOCTL_MJ_GET_DEVICE_LUN: + status = tdsaGetNumOfLUNIOCTL(tiRoot,agIOCTLPayload, agParam1, agParam2, agParam3); + if(status == IOCTL_CALL_SUCCESS) + { + status = IOCTL_CALL_PENDING; + } + break; +case IOCTL_MJ_SMP_REQUEST: + status = tdsaSendSMPIoctl(tiRoot, agIOCTLPayload, + agParam1,agParam2,agParam3); + break; + + case IOCTL_MJ_FW_CONTROL: + { + //ostiIOCTLClearSignal (tiRoot, &agParam1, &agParam2, &agParam3); + status = tdipFWControlIoctl( tiRoot, agIOCTLPayload, + agParam1, agParam2, agParam3); + + break; + } +//#ifdef EVENT_LOG_INFO_TESTING + /* Reserved field in tiIOCTLPayload_t is used as offset */ + case IOCTL_MJ_GET_EVENT_LOG1: + { + switch (agIOCTLPayload->MinorFunction) + { + case IOCTL_MN_FW_GET_TRACE_BUFFER: + { + agsaControllerEventLog_t EventLog; + saGetControllerEventLogInfo(agRoot, &EventLog); + TI_DBG6(("tiCOMMgntIOCTL: IOCTL_MJ_GET_EVENT_LOG1 Length %d\n", agIOCTLPayload->Length)); + RequestLength = agIOCTLPayload->Length; + Offset = agIOCTLPayload->Reserved; + EventLogLength = EventLog.eventLog1.totalLength; + EventLogOption = EventLog.eventLog1Option; + if (EventLogLength <= Offset) + { + TI_DBG1(("tiCOMMgntIOCTL: 1 out of range Requestlength %d Offset %d event log length %d\n", RequestLength, Offset, EventLogLength)); + // out of range + agIOCTLPayload->Status = IOCTL_ERR_STATUS_NO_MORE_DATA; + agIOCTLPayload->Length = 0; + if(EventLogOption == 0) + { + agIOCTLPayload->Status = IOCTL_ERR_FW_EVENTLOG_DISABLED; + } + status=IOCTL_CALL_SUCCESS; + return status; + } + ReadLength = MIN(EventLogLength - Offset, RequestLength); + loc = (bit8 *)EventLog.eventLog1.virtPtr + Offset; + osti_memcpy(&(agIOCTLPayload->FunctionSpecificArea), loc, ReadLength); + // tdhexdump("IOCTL_MJ_GET_EVENT_LOG1 first 32bytes", (bit8 *)&(agIOCTLPayload->FunctionSpecificArea), 32); + agIOCTLPayload->Status = IOCTL_ERR_STATUS_OK; + agIOCTLPayload->Length = (bit16)ReadLength; + status=IOCTL_CALL_SUCCESS; + break; + } + case IOCTL_MN_FW_GET_EVENT_FLASH_LOG1: + { + TI_DBG6(("tiCOMMgntIOCTL: IOCTL_MN_FW_GET_EVENT_FLASH_LOG1\n")); + status = tdsaRegDumpGetIoctl(tiRoot, agIOCTLPayload, agParam1, agParam2, agParam3); + break; + } + } + break; + } + + case IOCTL_MJ_GET_EVENT_LOG2: + { + switch (agIOCTLPayload->MinorFunction) + { + case IOCTL_MN_FW_GET_TRACE_BUFFER: + { + agsaControllerEventLog_t EventLog; + saGetControllerEventLogInfo(agRoot, &EventLog); + TI_DBG6(("tiCOMMgntIOCTL: IOCTL_MJ_GET_EVENT_LOG2 Length %d\n", agIOCTLPayload->Length)); + RequestLength = agIOCTLPayload->Length; + Offset = agIOCTLPayload->Reserved; + EventLogLength = EventLog.eventLog2.totalLength; + EventLogOption = EventLog.eventLog2Option; + if (EventLogLength <= Offset) + { + TI_DBG1(("tiCOMMgntIOCTL: 2 out of range Requestlength %d Offset %d event log length %d\n", RequestLength, Offset, EventLogLength)); + /* out of range */ + agIOCTLPayload->Status = IOCTL_ERR_STATUS_NO_MORE_DATA; + agIOCTLPayload->Length = 0; + if(EventLogOption == 0) + { + agIOCTLPayload->Status = IOCTL_ERR_FW_EVENTLOG_DISABLED; + } + status=IOCTL_CALL_SUCCESS; + return status; + } + ReadLength = MIN(EventLogLength - Offset, RequestLength); + loc = (bit8 *)EventLog.eventLog2.virtPtr + Offset; + osti_memcpy(&(agIOCTLPayload->FunctionSpecificArea), loc, ReadLength); + // tdhexdump("IOCTL_MJ_GET_EVENT_LOG2 first 32bytes", (bit8 *)&(agIOCTLPayload->FunctionSpecificArea), 32); + agIOCTLPayload->Status = IOCTL_ERR_STATUS_OK; + agIOCTLPayload->Length = (bit16)ReadLength; + status=IOCTL_CALL_SUCCESS; + break; + } + case IOCTL_MN_FW_GET_EVENT_FLASH_LOG2: + { + TI_DBG6(("tiCOMMgntIOCTL: IOCTL_MN_FW_GET_EVENT_FLASH_LOG2\n")); + status = tdsaRegDumpGetIoctl(tiRoot, agIOCTLPayload, agParam1, agParam2, agParam3); + break; + } + } + break; + } + + + case IOCTL_MJ_FW_INFO: + { + agsaControllerInfo_t ControllerInfo; + saGetControllerInfo(agRoot, &ControllerInfo); + TI_DBG1(("tiCOMMgntIOCTL: IOCTL_MJ_FW_INFO Length %d\n", agIOCTLPayload->Length)); + RequestLength = agIOCTLPayload->Length; + Offset = agIOCTLPayload->Reserved; + if (RequestLength == 0) + { + TI_DBG1(("tiCOMMgntIOCTL: IOCTL_MJ_FW_INFO: No more Data!\n")); + /* out of range */ + agIOCTLPayload->Status = IOCTL_ERR_STATUS_NO_MORE_DATA; + agIOCTLPayload->Length = 0; + status=IOCTL_CALL_SUCCESS; + return status; + } + + osti_memcpy((bit8*)&(agIOCTLPayload->FunctionSpecificArea), (bit8*)&ControllerInfo, sizeof(agsaControllerInfo_t)); + + TI_DBG1(("tiCOMMgntIOCTL:IOCTL_MJ_FW_INFO ControllerInfo signature 0x%X\n",ControllerInfo.signature)); + TI_DBG1(("tiCOMMgntIOCTL:IOCTL_MJ_FW_INFO ControllerInfo PCILinkRate 0x%X\n",ControllerInfo.PCILinkRate)); + TI_DBG1(("tiCOMMgntIOCTL:IOCTL_MJ_FW_INFO ControllerInfo PCIWidth 0x%X\n",ControllerInfo.PCIWidth)); + agIOCTLPayload->Status = IOCTL_ERR_STATUS_OK; + status=IOCTL_CALL_SUCCESS; + break; + + } + + case IOCTL_MJ_GET_FW_REV: + { + agsaControllerInfo_t ControllerInfo; + saGetControllerInfo(agRoot, &ControllerInfo); + TI_DBG3(("tiCOMMgntIOCTL: IOCTL_MJ_GET_FW_REV Length %d\n", agIOCTLPayload->Length)); + RequestLength = agIOCTLPayload->Length; + Offset = agIOCTLPayload->Reserved; + if (RequestLength == 0) + { + TI_DBG1(("tiCOMMgntIOCTL: IOCTL_MJ_GET_FW_REV: No more Data!\n")); + /* out of range */ + agIOCTLPayload->Status = IOCTL_ERR_STATUS_NO_MORE_DATA; + agIOCTLPayload->Length = 0; + status=IOCTL_CALL_SUCCESS; + return status; + } + + osti_memcpy((bit8*)&(agIOCTLPayload->FunctionSpecificArea), (bit8*)&ControllerInfo.fwRevision, sizeof(bit32)); + loc = (bit8 *)&(agIOCTLPayload->FunctionSpecificArea)+ sizeof(bit32); + osti_memcpy(loc, (bit8*)&ControllerInfo.sdkRevision, sizeof(bit32)); + + agIOCTLPayload->Status = IOCTL_ERR_STATUS_OK; + status=IOCTL_CALL_SUCCESS; + break; + + } + +#ifdef SPC_ENABLE_PROFILE + case IOCTL_MJ_FW_PROFILE: + { + TI_DBG6(("tiCOMMgntIOCTL: IOCTL_MJ_FW_PROFILE\n")); + status = tdipFWProfileIoctl( tiRoot, agIOCTLPayload, + agParam1, agParam2, agParam3); + break; + } +#endif /* SPC_ENABLE_PROFILE */ + + case IOCTL_MJ_GET_CORE_DUMP: + { + TI_DBG6(("tiCOMMgntIOCTL: IOCTL_MJ_GET_CORE_DUMP\n")); + if (tiIS_SPC(agRoot)) + { + status = tdsaRegDumpGetIoctl(tiRoot, agIOCTLPayload, agParam1, agParam2, agParam3); + } + else + { + agIOCTLPayload->Status = IOCTL_ERR_STATUS_NOT_SUPPORTED; + status = IOCTL_CALL_SUCCESS; + } + break; + } +//#endif + case IOCTL_MJ_NVMD_SET: + { + bit8 nvmDev; + TI_DBG6(("tiCOMMgntIOCTL: IOCTL_MJ_NVMD_SET\n")); + nvmDev = (bit8) agIOCTLPayload->Status; + agIOCTLPayload->Status = 0; + status = tdsaNVMDSetIoctl(tiRoot, agIOCTLPayload, agParam1, agParam2, &nvmDev); + break; + } +#if 0 +case IOCTL_MJ_GPIO: + { + bit32 sVid =0; + TI_DBG6(("tiCOMMgntIOCTL: IOCTL_MJ_GPIO\n")); + + /* Get Subsystem vendor */ + sVid = ostiChipConfigReadBit32(tiRoot,0x2C); + sVid = sVid & 0xFFFF; + + /* GPIO is only intended for chip down design + * therefore it's only applies to 8H/SPCv product family + */ + if(sVid == 0x9005) + return IOCTL_CALL_INVALID_DEVICE; + + status = tdsaGpioSetup(tiRoot, agContext, agIOCTLPayload, agParam1, agParam2); + if(status == IOCTL_CALL_SUCCESS) + status = IOCTL_CALL_PENDING; /* Wait for response from the Controller */ + else + return status; + + break; + } +#endif + + case IOCTL_MJ_SGPIO: + { + TI_DBG6(("tiCOMMgntIOCTL: IOCTL_MJ_SGPIO\n")); + status = tdsaSGpioIoctlSetup(tiRoot, agContext, agIOCTLPayload, agParam1, agParam2); + break; + } + + case IOCTL_MJ_NVMD_GET: + { + bit8 nvmDev; + TI_DBG3(("tiCOMMgntIOCTL: IOCTL_MJ_NVMD_GET\n")); + nvmDev = (bit8) agIOCTLPayload->Status; + agIOCTLPayload->Status = 0; + status = tdsaNVMDGetIoctl(tiRoot, agIOCTLPayload, agParam1, agParam2, &nvmDev); + break; + } + + case IOCTL_MJ_GET_FORENSIC_DATA: + { + TI_DBG3(("tiCOMMgntIOCTL: IOCTL_MJ_GET_FORENSIC_DATA\n")); + status = tdsaForensicDataGetIoctl(tiRoot, agIOCTLPayload, agParam1, agParam2, agParam3); + break; + } + case IOCTL_MJ_GET_DEVICE_INFO: + { + TI_DBG3(("tiCOMMgntIOCTL: IOCTL_MJ_GET_DEVICE_INFO\n")); + status = tdsaDeviceInfoGetIoctl(tiRoot, agIOCTLPayload, agParam1, agParam2, agParam3); + break; + } + + case IOCTL_MJ_GET_IO_ERROR_STATISTIC: + { + TI_DBG3(("tiCOMMgntIOCTL: IOCTL_MJ_GET_IO_ERROR_STATISTIC\n")); + status = tdsaIoErrorStatisticGetIoctl(tiRoot, agIOCTLPayload, agParam1, agParam2, agParam3); + break; + } + + case IOCTL_MJ_GET_IO_EVENT_STATISTIC: + { + TI_DBG3(("tiCOMMgntIOCTL: IOCTL_MJ_GET_IO_EVENT_STATISTIC\n")); + status = tdsaIoEventStatisticGetIoctl(tiRoot, agIOCTLPayload, agParam1, agParam2, agParam3); + break; + } + + case IOCTL_MJ_SEND_BIST: + { + TI_DBG1(("tiCOMMgntIOCTL: IOCTL_MJ_SEND_BIST\n")); + status = tdsaSendBISTIoctl(tiRoot, agIOCTLPayload, agParam1, agParam2, agParam3); + break; + } + +#if 0 + case IOCTL_MJ_SET_OR_GET_REGISTER: + { + TI_DBG3(("tiCOMMgntIOCTL: IOCTL_MJ_SET_OR_GET_REGISTER\n")); + status = tdsaRegisterIoctl(tiRoot, agIOCTLPayload, agParam1, agParam2, agParam3); + break; + } + +#endif + case IOCTL_MJ_PHY_DETAILS: + { + PhyDetails_t *PhyDetails = (PhyDetails_t*)&agIOCTLPayload->FunctionSpecificArea; + agsaRoot_t *agRoot = &(tdsaAllShared->agRootNonInt); + agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); + bit8 *sasAddressHi; + bit8 *sasAddressLo; + bit8 sas_dev_type; + int i = 0; + + tiIniGetDirectSataSasAddr(tiRoot, i , &sasAddressHi, &sasAddressLo); + for( i = 0; i < saRoot->phyCount ; i++) + { + PhyDetails[i].attached_phy = saRoot->phys[i].sasIdentify.phyIdentifier; + /* deice types + * SAS + * 0x01 - Sas end device + * 0x02 - Expander device + * SATA + * 0x11 - Sata + * NO DEVICE 0x00 + */ + sas_dev_type = (saRoot->phys[i].sasIdentify.deviceType_addressFrameType & 0x70 ) >> 4 ; + if ((saRoot->phys[i].status == 1) && (sas_dev_type == 0)){ //status 1 - Phy Up + //Sata phy + PhyDetails[i].attached_dev_type = SAS_PHY_SATA_DEVICE;//0x11 for sata end device + osti_memcpy(&PhyDetails[i].attached_sasAddressHi, tdsaAllShared->Ports[i].SASID.sasAddressHi, sizeof(bit32)); + osti_memcpy(&PhyDetails[i].attached_sasAddressLo, tdsaAllShared->Ports[i].SASID.sasAddressLo, sizeof(bit32)); + PhyDetails[i].attached_sasAddressLo[3] += i + 16; + } + else { + PhyDetails[i].attached_dev_type = sas_dev_type; + osti_memcpy(&PhyDetails[i].attached_sasAddressHi, saRoot->phys[i].sasIdentify.sasAddressHi, sizeof(bit32)); + osti_memcpy(&PhyDetails[i].attached_sasAddressLo, saRoot->phys[i].sasIdentify.sasAddressLo, sizeof(bit32)); + } + osti_memcpy(&PhyDetails[i].sasAddressLo,&(tdsaAllShared->Ports[i].SASID.sasAddressLo), sizeof(bit32)); + osti_memcpy(&PhyDetails[i].sasAddressHi,&(tdsaAllShared->Ports[i].SASID.sasAddressHi), sizeof(bit32)); + } + +// osti_memcpy(&agIoctlPayload->FunctionSpecificArea,&PhyInfo, sizeof(agsaSGpioReqResponse_t)); +// printk("Ioctl success\n"); + return IOCTL_CALL_SUCCESS; + } + + case IOCTL_MJ_PHY_GENERAL_STATUS: + { + agsaPhyGeneralState_t *PhyData=NULL; + bit32 ret = AGSA_RC_FAILURE; + PhyData = (agsaPhyGeneralState_t*) &agIOCTLPayload->FunctionSpecificArea[0]; + + PhyData->Reserved2 = 0; + /* Validate the length */ + if (agIOCTLPayload->Length < sizeof(agsaPhyGeneralState_t)) + { + status = IOCTL_CALL_FAIL; + break; + } + + tdsaAllShared->tdFWControlEx.param1 = agParam1; + tdsaAllShared->tdFWControlEx.param2 = agParam2; + tdsaAllShared->tdFWControlEx.payload = agIOCTLPayload; + tdsaAllShared->tdFWControlEx.inProgress = 1; + //tdsaAllShared->tdFWControlEx.usrAddr = PhyData; + + ret = tdsaGetPhyGeneralStatusIoctl(tiRoot,PhyData); + if(ret == AGSA_RC_FAILURE) + { + status = IOCTL_CALL_FAIL; + tdsaAllShared->tdFWControlEx.payload = NULL; + tdsaAllShared->tdFWControlEx.inProgress = 0; + break; + } + else if(ret == IOCTL_ERR_STATUS_NOT_SUPPORTED) + { + + agIOCTLPayload->Status = IOCTL_ERR_STATUS_NOT_SUPPORTED; + status = IOCTL_CALL_SUCCESS; + break; + } + + //status = IOCTL_CALL_PENDING; + status = IOCTL_CALL_PENDING; + } + + break; +#if 1 + case IOCTL_MJ_GET_PHY_PROFILE: + { + TI_DBG1(("tiCOMMgntIOCTL: IOCTL_MJ_GET_PHY_PROFILE %p %p %p\n",agParam1,agParam2,agParam3)); + status = tdsaPhyProfileIoctl(tiRoot, agIOCTLPayload, agParam1, agParam2, agParam3); + break; + } +#endif + case IOCTL_MJ_LL_TRACING: + { + void * stu = &agIOCTLPayload->FunctionSpecificArea[0]; + switch(agIOCTLPayload->MinorFunction) + { + + case IOCTL_MN_LL_RESET_TRACE_INDEX: + { + +#ifdef SA_ENABLE_TRACE_FUNCTIONS + TSTMTID_TRACE_BUFFER_RESET *llist = (TSTMTID_TRACE_BUFFER_RESET *)stu; + hpTraceBufferParms_t BufferParms; + TI_DBG5(("tdReturnIOCTL_Info: hpIOCTL_ResetTraceIndex\n")); + + BufferParms.TraceCompiled = 0; + BufferParms.TraceWrap = 0; + BufferParms.CurrentTraceIndexWrapCount = 0; + BufferParms.BufferSize = 0; + BufferParms.CurrentIndex = 0; + BufferParms.pTrace = NULL; + BufferParms.pTraceIndexWrapCount = NULL; + BufferParms.pTraceMask = NULL; + BufferParms.pCurrentTraceIndex = NULL; + + smTraceGetInfo(agRoot,&BufferParms); + TI_DBG5(("tdReturnIOCTL_Info: pTrace %p\n",BufferParms.pTrace)); + TI_DBG5(("tdReturnIOCTL_Info: pCurrentTraceIndex %p %X\n",BufferParms.pCurrentTraceIndex,*BufferParms.pCurrentTraceIndex)); + TI_DBG5(("tdReturnIOCTL_Info: pTraceIndexWrapCount %p %X\n",BufferParms.pTraceIndexWrapCount,*BufferParms.pTraceIndexWrapCount)); + TI_DBG5(("tdReturnIOCTL_Info: pTraceMask %p %X\n",BufferParms.pTraceMask,*BufferParms.pTraceMask)); + + if( llist->Flag != 0) + { + if( llist->TraceMask != *BufferParms.pTraceMask) + { + smTraceSetMask(agRoot, llist->TraceMask ); + } + } + if( llist->Reset) + { + + *BufferParms.pCurrentTraceIndex = 0; + smResetTraceBuffer(agRoot); + + *BufferParms.pCurrentTraceIndex = 0; + *BufferParms.pTraceIndexWrapCount =0; + llist->TraceMask = *BufferParms.pTraceMask; + } +#endif /* SA_ENABLE_TRACE_FUNCTIONS */ + agIOCTLPayload->Status = IOCTL_ERR_STATUS_OK; + status = IOCTL_CALL_SUCCESS; + + } + break; + + case IOCTL_MN_LL_GET_TRACE_BUFFER_INFO: + { + hpTraceBufferParms_t BufferParms; + TSTMTID_TRACE_BUFFER_INFO *llist = (TSTMTID_TRACE_BUFFER_INFO *)stu; + TI_DBG5(("tdReturnIOCTL_Info: hpIOCTL_GetTraceBufferInfo\n")); + + + BufferParms.TraceCompiled = 0; + BufferParms.TraceWrap = 0; + BufferParms.CurrentTraceIndexWrapCount = 0; + BufferParms.BufferSize = 0; + BufferParms.CurrentIndex = 0; + BufferParms.pTrace = NULL; + BufferParms.pTraceMask = NULL; +#ifdef SA_ENABLE_TRACE_FUNCTIONS + smTraceGetInfo(agRoot,&BufferParms); +#endif /* SA_ENABLE_TRACE_FUNCTIONS not enabled */ + llist->TraceCompiled = BufferParms.TraceCompiled; + llist->BufferSize = BufferParms.BufferSize; + llist->CurrentIndex = BufferParms.CurrentIndex ; + llist->CurrentTraceIndexWrapCount = BufferParms.CurrentTraceIndexWrapCount; + llist->TraceWrap = BufferParms.TraceWrap; + if(BufferParms.pTraceMask != NULL) + { + llist->TraceMask = *BufferParms.pTraceMask; + } + agIOCTLPayload->Status = IOCTL_ERR_STATUS_OK; + status = IOCTL_CALL_SUCCESS; + } + break; + + case IOCTL_MN_LL_GET_TRACE_BUFFER: + { +#ifdef SA_ENABLE_TRACE_FUNCTIONS + TSTMTID_TRACE_BUFFER_FETCH *llist = (TSTMTID_TRACE_BUFFER_FETCH *)stu; + + hpTraceBufferParms_t BufferParms; + bit32 c= 0; + + BufferParms.TraceCompiled = 0; + BufferParms.TraceWrap = 0; + BufferParms.CurrentTraceIndexWrapCount = 0; + BufferParms.BufferSize = 0; + BufferParms.CurrentIndex = 0; + BufferParms.pTrace = NULL; + smTraceGetInfo(agRoot,&BufferParms); + + TI_DBG6(("tdReturnIOCTL_Info: hpIOCTL_GetTraceBuffer\n")); + + if(llist->LowFence != LowFence32Bits) + { + break; + } + if(llist->HighFence != HighFence32Bits) + { + break; + } + + if(llist->BufferOffsetBegin + FetchBufferSIZE > BufferParms.BufferSize ) + { + } + + for ( c=0; c < FetchBufferSIZE;c++) + { + llist->Data[c] = *(BufferParms.pTrace+( c + llist->BufferOffsetBegin)); + } +#endif /* SA_ENABLE_TRACE_FUNCTIONS not enabled */ + } + agIOCTLPayload->Status = IOCTL_ERR_STATUS_OK; + status = IOCTL_CALL_SUCCESS; + break; + } + break; + } + +#ifdef SA_LL_API_TEST + case IOCTL_MJ_LL_API_TEST: + { + status = tdLlApiTestIoctl( tiRoot, agIOCTLPayload, + agParam1,agParam2,agParam3 ); + break; + } + +#endif /* SA_LL_API_TEST */ + + case IOCTL_MJ_MODE_CTL_PAGE: + { + /* The SPCv controller has some options accessed via mode pages */ + tiEncryptDekConfigPage_t *pModePage= (tiEncryptDekConfigPage_t *) &agIOCTLPayload->FunctionSpecificArea[0]; + bit32 pageLength = 0; + bit32 pageCode; + bit32 modeOperation; + + pageCode = pModePage->pageCode & 0xFF; + modeOperation = *(bit32 *) agParam2; + + switch(modeOperation) + { + + case tiModePageSet: + switch (pageCode) + { + case TI_ENCRYPTION_DEK_CONFIG_PAGE: + pageLength = sizeof(tiEncryptDekConfigPage_t); + break; + + case TI_ENCRYPTION_CONTROL_PARM_PAGE: + pageLength = sizeof(tiEncryptControlParamPage_t); + break; + + case TI_ENCRYPTION_GENERAL_CONFIG_PAGE: + /* Pages are currently unsupported */ + pageLength = 0; + break; + } + + status = saSetControllerConfig(agRoot, 0, pageCode, pageLength, pModePage, (agsaContext_t *)agIOCTLPayload); + break; + + case tiModePageGet: + status = saGetControllerConfig(agRoot, 0, pageCode, 0, 0, (agsaContext_t *)agIOCTLPayload); + break; + + default: + agIOCTLPayload->Status = IOCTL_ERR_STATUS_NOT_SUPPORTED; + } + } + break; +#ifdef PHY_RESTART_TEST + case IOCTL_MJ_PORT_START: + { + bit32 portID, tiStatus; + bit32 *data = (bit32*) &agIOCTLPayload->FunctionSpecificArea[0]; + portID = *data; + + tiStatus = tiCOMPortStart(tiRoot, portID, tdsaAllShared->Ports[portID].tiPortalContext, 0); + + if (tiStatus == tiSuccess) + { + agIOCTLPayload->Status = IOCTL_ERR_STATUS_OK; + } + else + { + agIOCTLPayload->Status = IOCTL_ERR_STATUS_INTERNAL_ERROR; + } + status = IOCTL_CALL_SUCCESS; + break; + } + + case IOCTL_MJ_PORT_STOP: + { + bit32 portID, tiStatus; + bit32 *data = (bit32*) &agIOCTLPayload->FunctionSpecificArea[0]; + portID = *data; + + tiStatus = tiCOMPortStop(tiRoot, tdsaAllShared->Ports[portID].tiPortalContext); + if (tiStatus == tiSuccess) + { + agIOCTLPayload->Status = IOCTL_ERR_STATUS_OK; + } + else + { + agIOCTLPayload->Status = IOCTL_ERR_STATUS_INTERNAL_ERROR; + } + + status = IOCTL_CALL_SUCCESS; + break; + } +#endif + case IOCTL_MJ_SEND_TMF: + switch(agIOCTLPayload->MinorFunction) + { + case IOCTL_MN_TMF_DEVICE_RESET: + status = tdsaSendTMFIoctl(tiRoot, agIOCTLPayload, agParam1, agParam2, AG_TARGET_WARM_RESET); + break; + case IOCTL_MN_TMF_LUN_RESET: + status = tdsaSendTMFIoctl(tiRoot, agIOCTLPayload, agParam1, agParam2, AG_LOGICAL_UNIT_RESET); + break; + } + break; + case IOCTL_MJ_GET_DRIVER_VERSION: + osti_sprintf(agIOCTLPayload->FunctionSpecificArea, "%s", AGTIAPI_DRIVER_VERSION); + agIOCTLPayload->Status = IOCTL_ERR_STATUS_OK; + status=IOCTL_CALL_SUCCESS; + break; + default: + agIOCTLPayload->Status = IOCTL_ERR_STATUS_NOT_SUPPORTED; + break; + } + + return status; +} + +#if 0 +/***************************************************************************** +* +* tdsaGpioSetup +* +* Purpose: This routine is called to set Gpio parameters to the controller. +* +* Parameters: +* tiRoot: Pointer to driver instance +* agsaContext_t : +* tiIOCTLPayload_t : ioctl header with payload gpio info +* agParam1,agParam2 : Generic parameters +* +* Return: status +* +* +*****************************************************************************/ +osGLOBAL bit32 +tdsaGpioSetup( + tiRoot_t *tiRoot, + agsaContext_t *agContext, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2 + ) +{ + + tdsaTimerRequest_t *osIoctlTimer; + agsaGpioEventSetupInfo_t *gpioEventSetupInfo; + agsaGpioWriteSetupInfo_t *gpioWriteSetupInfo; + agsaGpioPinSetupInfo_t *gpioPinSetupInfo; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + agsaRoot_t *agRoot = &(tdsaAllShared->agRootInt); + bit32 status = IOCTL_CALL_SUCCESS; + + TI_DBG3(("tdsaGpioSetup: start\n")); + + if(tiRoot == agNULL || agIOCTLPayload == agNULL ) + return IOCTL_CALL_FAIL; + + osIoctlTimer = &tdsaAllShared->osIoctlTimer; + tdsaInitTimerRequest(tiRoot, osIoctlTimer); + tdIoctlStartTimer(tiRoot, osIoctlTimer); /* Start the timout handler for both ioctl and controller response */ + tdsaAllShared->tdFWControlEx.virtAddr = (bit8 *)osIoctlTimer; + + tdsaAllShared->tdFWControlEx.usrAddr = (bit8 *)&agIOCTLPayload->FunctionSpecificArea[0]; + tdsaAllShared->tdFWControlEx.param1 = agParam1; + tdsaAllShared->tdFWControlEx.param2 = agParam2; + tdsaAllShared->tdFWControlEx.payload = agIOCTLPayload; + tdsaAllShared->tdFWControlEx.inProgress = 1; + + switch (agIOCTLPayload->MinorFunction) + { + + case IOCTL_MN_GPIO_PINSETUP: + { + TI_DBG3(("tdsaGpioSetup: IOCTL_MN_GPIO_PINSETUP\n")); + gpioPinSetupInfo =(agsaGpioPinSetupInfo_t *)&agIOCTLPayload->FunctionSpecificArea[0]; + status = saGpioPinSetup(agRoot, agContext, 0, gpioPinSetupInfo); + + break; + } + case IOCTL_MN_GPIO_EVENTSETUP: + { + TI_DBG3(("tdsaGpioSetup: IOCTL_MN_GPIO_EVENTSETUP\n")); + gpioEventSetupInfo = (agsaGpioEventSetupInfo_t *)&agIOCTLPayload->FunctionSpecificArea[0]; + status = saGpioEventSetup(agRoot, agContext, 0, gpioEventSetupInfo); + + break; + } + + case IOCTL_MN_GPIO_READ: + { + TI_DBG3(("tdsaGpioSetup: IOCTL_MN_GPIO_READ\n")); + status = saGpioRead(agRoot, agContext, 0); + + break; + } + + case IOCTL_MN_GPIO_WRITE: + { + TI_DBG3(("tdsaGpioSetup: IOCTL_MN_GPIO_WRITE\n")); + gpioWriteSetupInfo = (agsaGpioWriteSetupInfo_t *)&agIOCTLPayload->FunctionSpecificArea[0]; + status = saGpioWrite(agRoot, agContext, 0, gpioWriteSetupInfo->gpioWritemask, gpioWriteSetupInfo->gpioWriteVal); + + break; + } + + default : + return status; + } + + if(status != AGSA_RC_SUCCESS) + { + status = IOCTL_CALL_FAIL; + agIOCTLPayload->Status = IOCTL_ERR_STATUS_INTERNAL_ERROR; + + tdsaSingleThreadedEnter(tiRoot, TD_TIMER_LOCK); + if (osIoctlTimer->timerRunning == agTRUE) + { + tdsaSingleThreadedLeave(tiRoot, TD_TIMER_LOCK); + tdsaKillTimer(tiRoot, osIoctlTimer); + + }else{ + tdsaSingleThreadedLeave(tiRoot, TD_TIMER_LOCK); + } + } + + TI_DBG3(("tdsaGpioPinSetup: End\n")); + return status; + +} +#endif + +/***************************************************************************** +* +* ostiGetGpioIOCTLRsp +* +* Purpose: This routine is called for Get Gpio IOCTL reaponse has been received. +* +* Parameters: +* tiRoot: Pointer to driver instance +* payloadRsp: Pointer to the FW download IOMB's payload. +* +* Return: none +* +* +*****************************************************************************/ + +osGLOBAL void ostiGetGpioIOCTLRsp( + tiRoot_t *tiRoot, + bit32 status, + bit32 gpioReadValue, + agsaGpioPinSetupInfo_t *gpioPinSetupInfo, + agsaGpioEventSetupInfo_t *gpioEventSetupInfo + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tiIOCTLPayload_t *agIoctlPayload ; + agsaGpioReadInfo_t *gpioReadInfo; + + tdsaTimerRequest_t *osIoctlTimer; + osIoctlTimer = (tdsaTimerRequest_t *)tdsaAllShared->tdFWControlEx.virtAddr; + + TI_DBG2(("ostiGetGpioIOCTLRsp: start, status = %d \n", status)); + + agIoctlPayload = (tiIOCTLPayload_t *)(tdsaAllShared->tdFWControlEx.payload); + + if(agIoctlPayload == agNULL){ + return; + } + + agIoctlPayload->Status =(bit16) status; + + if( (status != IOCTL_CALL_TIMEOUT) && (osIoctlTimer != NULL)) + { + tdsaSingleThreadedEnter(tiRoot, TD_TIMER_LOCK); + if (osIoctlTimer->timerRunning == agTRUE) + { + tdsaSingleThreadedLeave(tiRoot, TD_TIMER_LOCK); + tdsaKillTimer(tiRoot, osIoctlTimer); + + }else{ + tdsaSingleThreadedLeave(tiRoot, TD_TIMER_LOCK); + } + }else { + tdsaAllShared->tdFWControlEx.inProgress = 0; + agIoctlPayload->Status = (bit16)status; + ostiIOCTLSetSignal(tiRoot, tdsaAllShared->tdFWControlEx.param1, + tdsaAllShared->tdFWControlEx.param2, NULL); + return; + } + + if(status == SUCCESS) + TI_DBG3((" ostiGetGpioIOCTLRsp:Got GPIO response from OUTBuf")); + else { + tdsaAllShared->tdFWControlEx.inProgress = 0; + ostiIOCTLSetSignal(tiRoot, tdsaAllShared->tdFWControlEx.param1, + tdsaAllShared->tdFWControlEx.param2, NULL); + return; + } + + switch (agIoctlPayload->MinorFunction) + { + + case IOCTL_MN_GPIO_PINSETUP: + { + TI_DBG3((" ostiGetGpioIOCTLRsp:Got GPIO response for IOCTL_MN_GPIO_PINSETUP")); + + break; + } + case IOCTL_MN_GPIO_EVENTSETUP: + { + TI_DBG3((" ostiGetGpioIOCTLRsp:Got GPIO response for IOCTL_MN_GPIO_EVENTSETUP")); + + break; + } + + case IOCTL_MN_GPIO_WRITE: + { + TI_DBG3((" ostiGetGpioIOCTLRsp:Got GPIO response for IOCTL_MN_GPIO_WRITE")); + + break; + } + + case IOCTL_MN_GPIO_READ: + { + gpioReadInfo = ( agsaGpioReadInfo_t *)tdsaAllShared->tdFWControlEx.usrAddr; + + gpioReadInfo->gpioReadValue = gpioReadValue; + gpioReadInfo->gpioInputEnabled = gpioPinSetupInfo->gpioInputEnabled ; /* GPIOIE */ + gpioReadInfo->gpioEventLevelChangePart1 = gpioPinSetupInfo->gpioTypePart1; /* GPIEVCHANGE (pins 11-0) */ + gpioReadInfo->gpioEventLevelChangePart2 = gpioPinSetupInfo->gpioTypePart2; /* GPIEVCHANGE (pins 23-20) */ + gpioReadInfo->gpioEventRisingEdgePart1 = 0xFFF & gpioEventSetupInfo->gpioEventRisingEdge; /* GPIEVRISE (pins 11-0) */ + gpioReadInfo->gpioEventRisingEdgePart2 = 0x00F00000 & (gpioEventSetupInfo->gpioEventRisingEdge); /* GPIEVRISE (pins 23-20) */ + gpioReadInfo->gpioEventFallingEdgePart1 = 0xFFF & gpioEventSetupInfo->gpioEventFallingEdge; /* GPIEVALL (pins 11-0) */ + gpioReadInfo->gpioEventFallingEdgePart2 = 0x00F00000 & gpioEventSetupInfo->gpioEventFallingEdge; /* GPIEVALL (pins 23-20 */ + + break; + } + + default : + break; + } + + if(tdsaAllShared->tdFWControlEx.inProgress) + { + tdsaAllShared->tdFWControlEx.inProgress = 0; + ostiIOCTLSetSignal(tiRoot, tdsaAllShared->tdFWControlEx.param1, + tdsaAllShared->tdFWControlEx.param2, NULL); + } + TI_DBG2(("ostiGetGpioIOCTLRsp: end \n")); + + return ; +} + +/***************************************************************************** +* +* tdsaSGpioIoctlSetup +* +* Purpose: This routine is called to send SGPIO request to the controller. +* +* Parameters: +* tiRoot: Pointer to driver instance +* agsaContext_t: Context for this request +* tiIOCTLPayload_t: ioctl header with payload sgpio info +* agParam1,agParam2: Generic parameters +* +* Return: status +* +* +*****************************************************************************/ +osGLOBAL bit32 +tdsaSGpioIoctlSetup( + tiRoot_t *tiRoot, + agsaContext_t *agContext, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2 + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + agsaRoot_t *agRoot = &(tdsaAllShared->agRootInt); + bit32 status = IOCTL_CALL_FAIL; + agsaSGpioReqResponse_t *pSGpioReq = (agsaSGpioReqResponse_t *)&agIOCTLPayload->FunctionSpecificArea[0]; + + TI_DBG3(("tdsaSGpioIoctlSetup: start\n")); + + agIOCTLPayload->Status = IOCTL_ERR_STATUS_INTERNAL_ERROR; + + do + { + if (tiRoot == agNULL || agIOCTLPayload == agNULL) + { + break; + } + + /* Validate the length */ + if (agIOCTLPayload->Length < sizeof(agsaSGpioReqResponse_t)) + { + TI_DBG3(("Invalid length\n")); + break; + } + + /* Validate the SMP Frame Type, Function and Register Type fields */ + if ((pSGpioReq->smpFrameType != SMP_REQUEST) || \ + ((pSGpioReq->function != SMP_READ_GPIO_REGISTER) && (pSGpioReq->function != SMP_WRITE_GPIO_REGISTER)) || \ + (pSGpioReq->registerType > AGSA_SGPIO_GENERAL_PURPOSE_TRANSMIT_REG)) + { + TI_DBG4(("Invalid Parameter\n")); + break; + } + + /* Specific validation for configuration register type */ + if (AGSA_SGPIO_CONFIG_REG == pSGpioReq->registerType) + { + if ((pSGpioReq->registerIndex > 0x01) || \ + ((0x00 == pSGpioReq->registerIndex) && (pSGpioReq->registerCount > 0x02)) || \ + ((0x01 == pSGpioReq->registerIndex) && (pSGpioReq->registerCount > 0x01))) + { + break; + } + } + + /* Use FW control place in shared structure to keep the necessary information */ + tdsaAllShared->tdFWControlEx.param1 = agParam1; + tdsaAllShared->tdFWControlEx.param2 = agParam2; + tdsaAllShared->tdFWControlEx.payload = agIOCTLPayload; + tdsaAllShared->tdFWControlEx.inProgress = 1; + + status = saSgpio(agRoot, agContext, 0, pSGpioReq); + if (status != AGSA_RC_SUCCESS) + { + break; + } + + status = IOCTL_CALL_PENDING; + + } while (0); + + TI_DBG3(("tdsaGpioPinSetup: End\n")); + return status; +} + +/***************************************************************************** +* +* ostiSgpioIoctlRsp +* +* Purpose: This routine is called when a SGPIO IOCTL response is received. +* +* Parameters: +* tiRoot: Pointer to driver instance +* pSgpioResponse: Pointer to the SGPIO response +* +* Return: none +* +* +*****************************************************************************/ +osGLOBAL void ostiSgpioIoctlRsp( + tiRoot_t *tiRoot, + agsaSGpioReqResponse_t *pSgpioResponse + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tiIOCTLPayload_t *agIoctlPayload = agNULL; + + TI_DBG3(("ostiSgpioIoctlRsp: start\n")); + + if (tdsaAllShared->tdFWControlEx.inProgress) + { + agIoctlPayload = (tiIOCTLPayload_t *)(tdsaAllShared->tdFWControlEx.payload); + if (agIoctlPayload) + { + tdsaAllShared->tdFWControlEx.payload = NULL; + osti_memcpy(&agIoctlPayload->FunctionSpecificArea[0], pSgpioResponse, sizeof(agsaSGpioReqResponse_t)); + agIoctlPayload->Status = IOCTL_ERR_STATUS_OK; + sgpioResponseSet = 1; + } + tdsaAllShared->sgpioResponseSet = 1; //Sunitha:Check if needed? + + ostiIOCTLSetSignal(tiRoot, tdsaAllShared->tdFWControlEx.param1, + tdsaAllShared->tdFWControlEx.param2, agNULL); + + tdsaAllShared->tdFWControlEx.inProgress = 0; + } + + TI_DBG3(("ostiSgpioIoctlRsp: end\n")); +} +/***************************************************************************** +* +* ostiCOMMgntIOCTLRsp +* +* Purpose: This routine is called when FW control IOCTL reaponse has been received. +* This function is used for both target and initiator. +* +* Parameters: +* tiRoot: Pointer to driver instance +* payloadRsp: Pointer to the FW download IOMB's payload. +* +* Return: none +* +* +* +*****************************************************************************/ + +osGLOBAL void ostiCOMMgntIOCTLRsp( + tiRoot_t *tiRoot, + bit32 status + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + + TI_DBG1(("ostiCOMMgntIOCTLRsp: status 0x%x\n",status)); + (tdsaAllShared->tdFWControlEx.tdFWControl)->retcode = status; + + ostiFreeMemory(tiRoot, + tdsaAllShared->tdFWControlEx.buffer, + tdsaAllShared->tdFWControlEx.tdFWControl->len); + + ostiIOCTLSetSignal(tiRoot, + tdsaAllShared->tdFWControlEx.param1, + tdsaAllShared->tdFWControlEx.param2, + NULL); +} + + +/***************************************************************************** +* +* ostiRegDumpIOCTLRsp +* +* Purpose: This routine is called when Register Dump from flash IOCTL reaponse has been received. +* This function is used for both target and initiator. +* +* Parameters: +* tiRoot: Pointer to driver instance +* payloadRsp: Pointer to the FW download IOMB's payload. +* +* Return: none +* +* +* +*****************************************************************************/ + +osGLOBAL void ostiRegDumpIOCTLRsp( + tiRoot_t *tiRoot, + bit32 status + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + + TI_DBG1(("ostiRegDumpIOCTLRsp: start\n")); +// (tdsaAllShared->tdFWControlEx.tdFWControl)->retcode = status; + osti_memcpy((void *)(tdsaAllShared->tdFWControlEx.usrAddr), + (void *)(tdsaAllShared->tdFWControlEx.virtAddr), + tdsaAllShared->tdFWControlEx.len); + + ostiFreeMemory(tiRoot, + tdsaAllShared->tdFWControlEx.buffer, + tdsaAllShared->tdFWControlEx.len); + + ostiIOCTLSetSignal(tiRoot, + tdsaAllShared->tdFWControlEx.param1, + tdsaAllShared->tdFWControlEx.param2, + NULL); +} + +/***************************************************************************** +* +* ostiSetNVMDIOCTLRsp +* +* Purpose: This routine is called for Set NVMD IOCTL reaponse has been received. +* This function is used for both target and initiator. +* +* Parameters: +* tiRoot: Pointer to driver instance +* payloadRsp: Pointer to the FW download IOMB's payload. +* +* Return: none +* +* +* +*****************************************************************************/ + +osGLOBAL void ostiSetNVMDIOCTLRsp( + tiRoot_t *tiRoot, + bit32 status + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tiIOCTLPayload_t *agIOCTLPayload; + + if(status) + { + agIOCTLPayload = (tiIOCTLPayload_t *)(tdsaAllShared->tdFWControlEx.payload); + agIOCTLPayload->Status = (bit16)status; + } + + TI_DBG1(("ostiSetNVMDIOCTLRsp: start, status = %d\n", status)); +// (tdsaAllShared->tdFWControlEx.tdFWControl)->retcode = status; + ostiFreeMemory(tiRoot, + tdsaAllShared->tdFWControlEx.buffer, + tdsaAllShared->tdFWControlEx.len); + + ostiIOCTLSetSignal(tiRoot, + tdsaAllShared->tdFWControlEx.param1, + tdsaAllShared->tdFWControlEx.param2, + NULL); +} +#ifdef SPC_ENABLE_PROFILE +/***************************************************************************** +* +* ostiFWProfileIOCTLRsp +* +* Purpose: This routine is called for Fw Profile IOCTL reaponse has been received. +* This function is used for both target and initiator. +* +* Parameters: +* tiRoot: Pointer to driver instance +* status: +* +* Return: none +* +* +* +*****************************************************************************/ + +osGLOBAL void ostiFWProfileIOCTLRsp( + tiRoot_t *tiRoot, + bit32 status, + bit32 len) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdFWProfile_t *fwProfile; + + TI_DBG1(("ostiFWProfileIOCTLRsp: start\n")); + fwProfile = (tdFWProfile_t *)tdsaAllShared->tdFWProfileEx.tdFWProfile; + // (tdsaAllShared->tdFWControlEx.tdFWControl)->retcode = status; + if (status == AGSA_RC_SUCCESS) + { + if((fwProfile->cmd == STOP_TIMER_PROFILE) || (fwProfile->cmd == STOP_CODE_PROFILE)) + { + osti_memcpy((void *)(fwProfile->buffer), + (void *)(tdsaAllShared->tdFWProfileEx.virtAddr), + len); + + ostiFreeMemory(tiRoot, + tdsaAllShared->tdFWProfileEx.buffer, + tdsaAllShared->tdFWProfileEx.len); + } + } + fwProfile->status = status; + fwProfile->len = len; + ostiIOCTLSetSignal(tiRoot, + tdsaAllShared->tdFWProfileEx.param1, + tdsaAllShared->tdFWProfileEx.param2, + NULL); +} +#endif +/***************************************************************************** +* +* ostiGetNVMDIOCTLRsp +* +* Purpose: This routine is called for Get NVMD IOCTL reaponse has been received. +* This function is used for both target and initiator. +* +* Parameters: +* tiRoot: Pointer to driver instance +* payloadRsp: Pointer to the FW download IOMB's payload. +* +* Return: none +* +* +* +*****************************************************************************/ + +osGLOBAL void ostiGetNVMDIOCTLRsp( + tiRoot_t *tiRoot, + bit32 status + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tiIOCTLPayload_t *agIOCTLPayload; + + if(status) + { + agIOCTLPayload = (tiIOCTLPayload_t *)(tdsaAllShared->tdFWControlEx.payload); + agIOCTLPayload->Status = (bit16)status; + } + + TI_DBG1(("ostiGetNVMDIOCTLRsp: start, status = %d\n", status)); + tdsaAllShared->NvmdResponseSet = 1; + + if(tdsaAllShared->tdFWControlEx.param1 != agNULL) + { + osti_memcpy((void *)(tdsaAllShared->tdFWControlEx.usrAddr), + (void *)(tdsaAllShared->tdFWControlEx.virtAddr), + tdsaAllShared->tdFWControlEx.len); + + ostiFreeMemory(tiRoot, + tdsaAllShared->tdFWControlEx.buffer, + tdsaAllShared->tdFWControlEx.len); + + ostiIOCTLSetSignal(tiRoot, + tdsaAllShared->tdFWControlEx.param1, + tdsaAllShared->tdFWControlEx.param2, + NULL); + } +} + + +/***************************************************************************** +* +* ostiGetPhyProfileIOCTLRsp +* +* Purpose: This routine is called for phy response has been received. +* This function is used for both target and initiator. +* +* Parameters: +* tiRoot: Pointer to driver instance +* payloadRsp: Pointer to the IOMB's payload. +* +* Return: none +* +* +* +*****************************************************************************/ + +osGLOBAL void ostiGetPhyProfileIOCTLRsp( + tiRoot_t *tiRoot, + bit32 status + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tiIOCTLPayload_t *agIOCTLPayload; + tdPhyCount_t *PhyBlob = agNULL; + if(status) + { + agIOCTLPayload = (tiIOCTLPayload_t *)(tdsaAllShared->tdFWControlEx.payload); + agIOCTLPayload->Status = (bit16)status; + + PhyBlob = (tdPhyCount_t*)&agIOCTLPayload->FunctionSpecificArea[0]; + if(PhyBlob) + { +// PhyBlob->Phy |= 0x800; + if(PhyBlob->phyResetProblem == 0 ) + { + PhyBlob->phyResetProblem = -1; + } + TI_DBG1(("ostiGetPhyProfileIOCTLRsp: PhyBlob->Phy 0x%x\n",PhyBlob->Phy)); + TI_DBG1(("ostiGetPhyProfileIOCTLRsp: PhyBlob->BW_rx 0x%x\n",PhyBlob->BW_rx)); + TI_DBG1(("ostiGetPhyProfileIOCTLRsp: PhyBlob->BW_tx 0x%x\n",PhyBlob->BW_tx)); + TI_DBG1(("ostiGetPhyProfileIOCTLRsp: PhyBlob->InvalidDword 0x%x\n",PhyBlob->InvalidDword)); + TI_DBG1(("ostiGetPhyProfileIOCTLRsp: PhyBlob->runningDisparityError 0x%x\n",PhyBlob->runningDisparityError)); + TI_DBG1(("ostiGetPhyProfileIOCTLRsp: PhyBlob->codeViolation 0x%x\n",PhyBlob->codeViolation)); + TI_DBG1(("ostiGetPhyProfileIOCTLRsp: PhyBlob->phyResetProblem 0x%x\n",PhyBlob->phyResetProblem)); + TI_DBG1(("ostiGetPhyProfileIOCTLRsp: PhyBlob->inboundCRCError 0x%x\n",PhyBlob->inboundCRCError)); + + } + + + } + + TI_DBG1(("ostiGetPhyProfileIOCTLRsp: start, status = %d\n", status)); + TI_DBG1(("ostiGetPhyProfileIOCTLRsp: start, len = %d %p %p\n", tdsaAllShared->tdFWControlEx.len,tdsaAllShared->tdFWControlEx.usrAddr,tdsaAllShared->tdFWControlEx.virtAddr)); + +// osti_memcpy((void *)(tdsaAllShared->tdFWControlEx.usrAddr), +// (void *)(tdsaAllShared->tdFWControlEx.virtAddr), +// tdsaAllShared->tdFWControlEx.len); + + ostiFreeMemory(tiRoot, + tdsaAllShared->tdFWControlEx.buffer, + tdsaAllShared->tdFWControlEx.len); + + ostiIOCTLSetSignal(tiRoot, + tdsaAllShared->tdFWControlEx.param1, + tdsaAllShared->tdFWControlEx.param2, + NULL); +} + + +/***************************************************************************** +* +* ostiGenEventIOCTLRsp +* +* Purpose: This routine is called when General Event happened while waiting for IOCTL response. +* This function is used for both target and initiator. +* +* Parameters: +* tiRoot: Pointer to driver instance +* payloadRsp: Pointer to the FW download IOMB's payload. +* +* Return: none +* +* +* +*****************************************************************************/ + +osGLOBAL void ostiGenEventIOCTLRsp( + tiRoot_t *tiRoot, + bit32 status + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tiIOCTLPayload_t *agIOCTLPayload; + + TI_DBG1(("ostiGenEventIOCTLRsp: start\n")); + + if(tdsaAllShared->tdFWControlEx.inProgress) /*Free only if our IOCTL is in progress*/ + { + agIOCTLPayload = (tiIOCTLPayload_t *)(tdsaAllShared->tdFWControlEx.payload); + agIOCTLPayload->Status = IOCTL_ERR_STATUS_INTERNAL_ERROR; + (tdsaAllShared->tdFWControlEx.tdFWControl)->retcode = IOCTL_ERR_STATUS_INTERNAL_ERROR; + + ostiFreeMemory(tiRoot, + tdsaAllShared->tdFWControlEx.buffer, + tdsaAllShared->tdFWControlEx.len); + + ostiIOCTLSetSignal(tiRoot, + tdsaAllShared->tdFWControlEx.param1, + tdsaAllShared->tdFWControlEx.param2, + NULL); + tdsaAllShared->tdFWControlEx.inProgress = 0; + } +#ifdef SPC_ENABLE_PROFILE + if(tdsaAllShared->tdFWProfileEx.inProgress) + { + agIOCTLPayload = (tiIOCTLPayload_t *)(tdsaAllShared->tdFWProfileEx.payload); + agIOCTLPayload->Status = IOCTL_ERR_STATUS_INTERNAL_ERROR; + if(tdsaAllShared->tdFWProfileEx.virtAddr != NULL) /*Free only if our IOCTL is in progress*/ + { + ostiFreeMemory(tiRoot, + tdsaAllShared->tdFWProfileEx.buffer, + tdsaAllShared->tdFWProfileEx.len); + tdsaAllShared->tdFWProfileEx.virtAddr = NULL; + } + ostiIOCTLSetSignal(tiRoot, + tdsaAllShared->tdFWProfileEx.param1, + tdsaAllShared->tdFWProfileEx.param2, + NULL); + tdsaAllShared->tdFWProfileEx.inProgress = 0; + + } +#endif /*SPC_ENABLE_PROFILE*/ + +} + +osGLOBAL void +ostiGetDeviceInfoIOCTLRsp( + tiRoot_t *tiRoot, + bit32 status, + void *param + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tiIOCTLPayload_t *agIOCTLPayload = agNULL; + tdDeviceInfoPayload_t *pTDDeviceInfo = agNULL; + agsaDeviceInfo_t *pSADeviceInfo = agNULL; + + TI_DBG1(("ostiGetDeviceInfoIOCTLRsp: start\n")); + + agIOCTLPayload = (tiIOCTLPayload_t *)(tdsaAllShared->tdFWControlEx.payload); + pSADeviceInfo = (agsaDeviceInfo_t*)param; + pTDDeviceInfo = (tdDeviceInfoPayload_t*)agIOCTLPayload->FunctionSpecificArea; + + if (pSADeviceInfo != agNULL) + { + /* fill the device information in IOCTL payload */ + osti_memcpy(&pTDDeviceInfo->devInfo.sasAddressHi, pSADeviceInfo->sasAddressHi, sizeof(bit32)); + osti_memcpy(&pTDDeviceInfo->devInfo.sasAddressLo, pSADeviceInfo->sasAddressLo, sizeof(bit32)); + + pTDDeviceInfo->devInfo.sasAddressHi = DMA_BEBIT32_TO_BIT32(pTDDeviceInfo->devInfo.sasAddressHi); + pTDDeviceInfo->devInfo.sasAddressLo = DMA_BEBIT32_TO_BIT32(pTDDeviceInfo->devInfo.sasAddressLo); + + pTDDeviceInfo->devInfo.deviceType = (pSADeviceInfo->devType_S_Rate & 0x30) >> 4; + pTDDeviceInfo->devInfo.linkRate = pSADeviceInfo->devType_S_Rate & 0x0F; + + agIOCTLPayload->Status = IOCTL_ERR_STATUS_OK; + } + else + { + agIOCTLPayload->Status = IOCTL_ERR_STATUS_INVALID_DEVICE; + } + + if(tdsaAllShared->tdFWControlEx.inProgress) /*Free only if our IOCTL is in progress*/ + { + ostiIOCTLSetSignal(tiRoot, + tdsaAllShared->tdFWControlEx.param1, + tdsaAllShared->tdFWControlEx.param2, + NULL); + tdsaAllShared->tdFWControlEx.inProgress = 0; + } +} + + +#ifdef INITIATOR_DRIVER +osGLOBAL void +ostiGetIoErrorStatsIOCTLRsp( + tiRoot_t *tiRoot, + bit32 status, + void *param + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + itdsaIni_t *Initiator = (itdsaIni_t *)tdsaAllShared->itdsaIni; + tiIOCTLPayload_t *agIOCTLPayload = agNULL; + tdIoErrorStatisticPayload_t *pIoErrorPayload = agNULL; + agsaIOErrorEventStats_t *pIoErrorCount = agNULL; + + OS_ASSERT(sizeof(agsaIOErrorEventStats_t) == sizeof(tdIoErrorEventStatisticIOCTL_t), "agsaIOErrorEventStats_t tdIoErrorEventStatisticIOCTL_t\n"); + TI_DBG1(("ostiGetIoErrorStatsIOCTLRsp: start\n")); + + agIOCTLPayload = (tiIOCTLPayload_t *)(tdsaAllShared->tdFWControlEx.payload); + pIoErrorPayload = (tdIoErrorStatisticPayload_t*)agIOCTLPayload->FunctionSpecificArea; + pIoErrorCount = (agsaIOErrorEventStats_t*)param; + + osti_memcpy(&pIoErrorPayload->IoError, pIoErrorCount, sizeof(agsaIOErrorEventStats_t)); + /*copy SCSI status and sense key count from OS layer to TD layer*/ + osti_memcpy(&pIoErrorPayload->ScsiStatusCounter, &Initiator->ScsiStatusCounts, sizeof(tdSCSIStatusCount_t)); + osti_memcpy(&pIoErrorPayload->SenseKeyCounter, &Initiator->SenseKeyCounter, sizeof(tdSenseKeyCount_t)); + if (pIoErrorPayload->flag) + { + osti_memset(&Initiator->ScsiStatusCounts, 0,sizeof(tdSCSIStatusCount_t) ); + osti_memset(&Initiator->SenseKeyCounter, 0,sizeof(tdSenseKeyCount_t) ); + } + + agIOCTLPayload->Status = IOCTL_ERR_STATUS_OK; +} +#endif /* INITIATOR_DRIVER */ + +osGLOBAL void +ostiGetIoEventStatsIOCTLRsp( + tiRoot_t *tiRoot, + bit32 status, + void *param + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tiIOCTLPayload_t *agIOCTLPayload = agNULL; + tdIoEventStatisticPayload_t *pIoEventPayload = agNULL; + agsaIOErrorEventStats_t *pIoEventCount = agNULL; + + TI_DBG1(("ostiGetIoEventStatsIOCTLRsp: start\n")); + + agIOCTLPayload = (tiIOCTLPayload_t *)(tdsaAllShared->tdFWControlEx.payload); + pIoEventPayload = (tdIoEventStatisticPayload_t*)agIOCTLPayload->FunctionSpecificArea; + pIoEventCount = (agsaIOErrorEventStats_t*)param; + + osti_memcpy(&pIoEventPayload->IoEvent, pIoEventCount, sizeof(agsaIOErrorEventStats_t)); + + agIOCTLPayload->Status = IOCTL_ERR_STATUS_OK; +} + +osGLOBAL void +ostiGetForensicDataIOCTLRsp( + tiRoot_t *tiRoot, + bit32 status, + void *param + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tiIOCTLPayload_t *agIOCTLPayload = agNULL; + tdForensicDataPayload_t *pForensicDataPayload = agNULL; + agsaForensicData_t *pForensicData = agNULL; + + TI_DBG3(("ostiGetForensicDataIOCTLRsp: start, status = %d\n", status)); + + agIOCTLPayload = (tiIOCTLPayload_t *)(tdsaAllShared->tdFWControlEx.payload); + pForensicDataPayload = (tdForensicDataPayload_t*)agIOCTLPayload->FunctionSpecificArea; + pForensicData = (agsaForensicData_t*)param; + + if (agNULL == agIOCTLPayload) + { + return; + } + + if (FORENSIC_DATA_TYPE_CHECK_FATAL == pForensicData->DataType) + { + agIOCTLPayload->Status = (bit16)status; + return; + } + + if (status == AGSA_RC_SUCCESS) + { + switch (pForensicData->DataType) + { + case FORENSIC_DATA_TYPE_NON_FATAL: + case FORENSIC_DATA_TYPE_FATAL: + pForensicDataPayload->dataBuffer.directOffset = pForensicData->BufferType.dataBuf.directOffset; + pForensicDataPayload->dataBuffer.readLen = pForensicData->BufferType.dataBuf.readLen; + break; + case FORENSIC_DATA_TYPE_GSM_SPACE: + pForensicDataPayload->gsmBuffer.directOffset = pForensicData->BufferType.gsmBuf.directOffset; + pForensicDataPayload->gsmBuffer.readLen = pForensicData->BufferType.gsmBuf.readLen; + break; + + case FORENSIC_DATA_TYPE_QUEUE: + break; + + default: + TI_DBG1(("ostiGetForensicDataIOCTLRsp: forensic data type error %d\n", pForensicData->DataType)); + break; + } + agIOCTLPayload->Status = IOCTL_ERR_STATUS_OK; + } + else if(status == IOCTL_ERROR_NO_FATAL_ERROR) + { + agIOCTLPayload->Status = (bit16)status; + } + else + { + agIOCTLPayload->Status = IOCTL_ERR_STATUS_INTERNAL_ERROR; + } + + /*Free only if our IOCTL is in progress*/ + if(tdsaAllShared->tdFWControlEx.inProgress) + { + TI_DBG3(("ostiGetForensicDataIOCTLRsp: Waiting for the signal \n")); + ostiIOCTLSetSignal(tiRoot, + tdsaAllShared->tdFWControlEx.param1, + tdsaAllShared->tdFWControlEx.param2, + NULL); + TI_DBG3(("ostiGetForensicDataIOCTLRsp: Signal wait completed \n")); + tdsaAllShared->tdFWControlEx.inProgress = 0; + } +} + +/***************************************************************************** +* +* tdsaRegDumpGetIoctl +* +* Purpose: This routine is called to get Register Dump information. +* This function is used for both target and initiator. +* +* Parameters: +* tiRoot: Pointer to driver instance +* agIOCTLPayload: Pointer to the IOCTL payload. +* agParam1: Pointer to pass context handle for IOCTL DMA operation +* agParam2: Pointer to pass context handle for IOCTL DMA operation +* agParam3: Pointer to pass context handle for IOCTL DMA operation +* +* Return: +* +* IOCTL_CALL_SUCCESS The requested operation completed successfully. +* IOCTL_CALL_FAIL Fail to complete the IOCTL request. +* Detail error code is function specific and +* defined by the specific IOCTL function. +* IOCTL_CALL_PENDING This request is asynchronous and completed +* in some other context. +* IOCTL_CALL_INVALID_CODE This IOCTL function is not recognized. +* +* +*****************************************************************************/ +osGLOBAL bit32 +tdsaRegDumpGetIoctl( + tiRoot_t *tiRoot, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2, + void *agParam3 + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + agsaRoot_t *agRoot = &(tdsaAllShared->agRootInt); +// agsaControllerStatus_t RegDump; + bit32 Offset = 0; + bit32 RequestLength = 0; /* user request on how much data to pass to application */ + agsaRegDumpInfo_t regDumpInfo; + void *buffer = agNULL; + void *osMemHandle = agNULL; + bit32 status = IOCTL_CALL_SUCCESS; + bit32 CoreDumpLength = 16384; /* change it once data is available */ + bit32 EventLogOffset = 65536; + + ///saGetControllerStatus(agRoot, &RegDump); + /* length of FSA as provided by application */ + RequestLength = agIOCTLPayload->Length; +/// FunctionSpecificOffset = 0; /* Offset into the FunctionSpecificArea of payload */ + /* offset into core dump that was passed from application */ + Offset = agIOCTLPayload->Reserved; + + if((CoreDumpLength <= Offset)&& + (agIOCTLPayload->MinorFunction != IOCTL_MN_FW_GET_EVENT_FLASH_LOG1)&& + (agIOCTLPayload->MinorFunction != IOCTL_MN_FW_GET_EVENT_FLASH_LOG2)) + { + agIOCTLPayload->Status = IOCTL_ERR_STATUS_NO_MORE_DATA; + agIOCTLPayload->Length = 0; + status=IOCTL_CALL_SUCCESS; + return status; + } + regDumpInfo.regDumpOffset = Offset; + agIOCTLPayload->Status = IOCTL_ERR_STATUS_OK; + /* dump either aap1 or iop registers */ + switch(agIOCTLPayload->MinorFunction){ + + /*Coredump*/ + case IOCTL_MN_FW_GET_CORE_DUMP_AAP1: + //CoreDumpBAROffset = RegDump.fatalErrorInfo.regDumpOffset0; /* get this from mpi config table */ + //CoreDumpLength = RegDump.fatalErrorInfo.regDumpLen0; + /*changes for added Call back*/ + tdsaAllShared->tdFWControlEx.param1 = agParam1; + tdsaAllShared->tdFWControlEx.param2 = agParam2; + regDumpInfo.regDumpSrc = 0; + regDumpInfo.regDumpNum = 0; + regDumpInfo.directLen = RequestLength; + regDumpInfo.directData = &agIOCTLPayload->FunctionSpecificArea[0]; + /*changes for added Call back*/ + //status = IOCTL_CALL_SUCCESS; + tdsaAllShared->tdFWControlEx.inProgress = 1; + status = IOCTL_CALL_PENDING; + break; + case IOCTL_MN_FW_GET_CORE_DUMP_IOP: + //CoreDumpBAROffset = RegDump.fatalErrorInfo.regDumpOffset1; /* get this from mpi config table */ + //CoreDumpLength = RegDump.fatalErrorInfo.regDumpLen1; + /*changes for added Call back*/ + tdsaAllShared->tdFWControlEx.param1 = agParam1; + tdsaAllShared->tdFWControlEx.param2 = agParam2; + regDumpInfo.regDumpSrc = 0; + regDumpInfo.regDumpNum = 1; + regDumpInfo.directLen = RequestLength; + regDumpInfo.directData = &agIOCTLPayload->FunctionSpecificArea[0]; + /*changes for added Call back*/ + //status = IOCTL_CALL_SUCCESS; + tdsaAllShared->tdFWControlEx.inProgress = 1; + status = IOCTL_CALL_PENDING; + break; + case IOCTL_MN_FW_GET_CORE_DUMP_FLASH_AAP1: + regDumpInfo.regDumpSrc = 1; + regDumpInfo.regDumpNum = 0; + if(RequestLength != 0) + { + if(ostiAllocMemory( tiRoot, + &osMemHandle, + (void **)&buffer, + &(regDumpInfo.indirectAddrUpper32), + &(regDumpInfo.indirectAddrLower32), + 8, + RequestLength, + agFALSE)) + return IOCTL_CALL_FAIL; + } + osti_memset((void *)buffer, 0, RequestLength); + regDumpInfo.indirectLen = RequestLength; + + // use FW control place in shared structure to keep the neccesary information + tdsaAllShared->tdFWControlEx.buffer = osMemHandle; + tdsaAllShared->tdFWControlEx.virtAddr = buffer; + tdsaAllShared->tdFWControlEx.usrAddr = (bit8*)&agIOCTLPayload->FunctionSpecificArea[0]; + tdsaAllShared->tdFWControlEx.len = RequestLength; + tdsaAllShared->tdFWControlEx.param1 = agParam1; + tdsaAllShared->tdFWControlEx.param2 = agParam2; + tdsaAllShared->tdFWControlEx.payload = agIOCTLPayload; + tdsaAllShared->tdFWControlEx.inProgress = 1; + status = IOCTL_CALL_PENDING; + break; + case IOCTL_MN_FW_GET_CORE_DUMP_FLASH_IOP: + regDumpInfo.regDumpSrc = 1; + regDumpInfo.regDumpNum = 1; + if(RequestLength != 0) + { + if(ostiAllocMemory( tiRoot, + &osMemHandle, + (void **)&buffer, + &(regDumpInfo.indirectAddrUpper32), + &(regDumpInfo.indirectAddrLower32), + 8, + RequestLength, + agFALSE)) + return IOCTL_CALL_FAIL; + } + osti_memset((void *)buffer, 0, RequestLength); + regDumpInfo.indirectLen = RequestLength; + + // use FW control place in shared structure to keep the neccesary information + tdsaAllShared->tdFWControlEx.buffer = osMemHandle; + tdsaAllShared->tdFWControlEx.virtAddr = buffer; + tdsaAllShared->tdFWControlEx.usrAddr = (bit8*)&agIOCTLPayload->FunctionSpecificArea[0]; + tdsaAllShared->tdFWControlEx.len = RequestLength; + tdsaAllShared->tdFWControlEx.param1 = agParam1; + tdsaAllShared->tdFWControlEx.param2 = agParam2; + tdsaAllShared->tdFWControlEx.payload = agIOCTLPayload; + tdsaAllShared->tdFWControlEx.inProgress = 1; + status = IOCTL_CALL_PENDING; + break; + /*EventLog from Flash*/ + case IOCTL_MN_FW_GET_EVENT_FLASH_LOG1: //aap1 Eventlog + if(CoreDumpLength + EventLogOffset <= Offset) + { + agIOCTLPayload->Status = IOCTL_ERR_STATUS_NO_MORE_DATA; + agIOCTLPayload->Length = 0; + status=IOCTL_CALL_SUCCESS; + return status; + } + regDumpInfo.regDumpSrc = 1; + regDumpInfo.regDumpNum = 0; + if(RequestLength != 0) + { + if(ostiAllocMemory( tiRoot, + &osMemHandle, + (void **)&buffer, + &(regDumpInfo.indirectAddrUpper32), + &(regDumpInfo.indirectAddrLower32), + 8, + RequestLength, + agFALSE)) + return IOCTL_CALL_FAIL; + } + osti_memset((void *)buffer, 0, RequestLength); + regDumpInfo.indirectLen = RequestLength; + + // use FW control place in shared structure to keep the neccesary information + tdsaAllShared->tdFWControlEx.buffer = osMemHandle; + tdsaAllShared->tdFWControlEx.virtAddr = buffer; + tdsaAllShared->tdFWControlEx.usrAddr = (bit8*)&agIOCTLPayload->FunctionSpecificArea[0]; + tdsaAllShared->tdFWControlEx.len = RequestLength; + tdsaAllShared->tdFWControlEx.param1 = agParam1; + tdsaAllShared->tdFWControlEx.param2 = agParam2; + tdsaAllShared->tdFWControlEx.payload = agIOCTLPayload; + tdsaAllShared->tdFWControlEx.inProgress = 1; + status = IOCTL_CALL_PENDING; + break; + case IOCTL_MN_FW_GET_EVENT_FLASH_LOG2: //iop Eventlog + if(CoreDumpLength + EventLogOffset <= Offset) + { + agIOCTLPayload->Status = IOCTL_ERR_STATUS_NO_MORE_DATA; + agIOCTLPayload->Length = 0; + status=IOCTL_CALL_SUCCESS; + return status; + } + regDumpInfo.regDumpSrc = 1; + regDumpInfo.regDumpNum = 1; + if(RequestLength != 0) + { + if(ostiAllocMemory( tiRoot, + &osMemHandle, + (void **)&buffer, + &(regDumpInfo.indirectAddrUpper32), + &(regDumpInfo.indirectAddrLower32), + 8, + RequestLength, + agFALSE)) + return IOCTL_CALL_FAIL; + } + osti_memset((void *)buffer, 0, RequestLength); + regDumpInfo.indirectLen = RequestLength; + + // use FW control place in shared structure to keep the neccesary information + tdsaAllShared->tdFWControlEx.buffer = osMemHandle; + tdsaAllShared->tdFWControlEx.virtAddr = buffer; + tdsaAllShared->tdFWControlEx.usrAddr = (bit8*)&agIOCTLPayload->FunctionSpecificArea[0]; + tdsaAllShared->tdFWControlEx.len = RequestLength; + tdsaAllShared->tdFWControlEx.param1 = agParam1; + tdsaAllShared->tdFWControlEx.param2 = agParam2; + tdsaAllShared->tdFWControlEx.payload = agIOCTLPayload; + tdsaAllShared->tdFWControlEx.inProgress = 1; + status = IOCTL_CALL_PENDING; + break; + default: + status = IOCTL_CALL_INVALID_CODE; + TI_DBG1(("tiCOMMgntIOCTL: ERROR: Wrong IOCTL code %d\n", agIOCTLPayload->MinorFunction)); + break; + } + if(saGetRegisterDump(agRoot, agNULL, 0, ®DumpInfo) != AGSA_RC_SUCCESS) + { + status = IOCTL_CALL_FAIL; + agIOCTLPayload->Status = IOCTL_ERR_STATUS_INTERNAL_ERROR; + } + + return status; +} + +osGLOBAL void +ostiCOMMgntVPDSetIOCTLRsp( + tiRoot_t *tiRoot, + bit32 status + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; +// agsaRoot_t *agRoot = &(tdsaAllShared->agRootInt); + + TI_DBG1(("ostiCOMMgntVPDSetIOCTLRsp: start\n")); + (tdsaAllShared->tdFWControlEx.tdFWControl)->retcode = status; + + ostiFreeMemory(tiRoot, + tdsaAllShared->tdFWControlEx.buffer, + tdsaAllShared->tdFWControlEx.len); + + ostiIOCTLSetSignal(tiRoot, tdsaAllShared->tdFWControlEx.param1, + tdsaAllShared->tdFWControlEx.param2, + NULL); +} + +/***************************************************************************** +* +* tdsaNVMDSetIoctl +* +* Purpose: This routine is called to set Config. SEEPROM information. +* This function is used for both target and initiator. +* +* Parameters: +* tiRoot: Pointer to driver instance +* agIOCTLPayload: Pointer to the IOCTL payload. +* agParam1: Pointer to pass context handle for IOCTL DMA operation +* agParam2: Pointer to pass context handle for IOCTL DMA operation +* agParam3: Pointer to pass context handle for IOCTL DMA operation +* +* Return: +* +* IOCTL_CALL_SUCCESS The requested operation completed successfully. +* IOCTL_CALL_FAIL Fail to complete the IOCTL request. +* Detail error code is function specific and +* defined by the specific IOCTL function. +* IOCTL_CALL_PENDING This request is asynchronous and completed +* in some other context. +* IOCTL_CALL_INVALID_CODE This IOCTL function is not recognized. +* +* +*****************************************************************************/ +osGLOBAL bit32 +tdsaNVMDSetIoctl( + tiRoot_t *tiRoot, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2, + void *agParam3 + ) +{ + bit32 RequestLength = 0; + bit32 bufAddrUpper = 0; + bit32 bufAddrLower = 0; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + agsaRoot_t *agRoot = &(tdsaAllShared->agRootInt); + void *buffer = agNULL; + void *osMemHandle = agNULL; + bit32 status = IOCTL_CALL_SUCCESS; + agsaNVMDData_t nvmdInfo; + + + TI_DBG2(("tdsaNVMDSetIoctl: start\n")); + + RequestLength = agIOCTLPayload->Length; + + osti_memset(&nvmdInfo, 0, sizeof(agsaNVMDData_t)); + + switch(agIOCTLPayload->MinorFunction) + { + case IOCTL_MN_NVMD_SET_CONFIG: + + //nvmdInfo.NVMDevice = 1; + nvmdInfo.NVMDevice = *((bit8*)agParam3); + nvmdInfo.signature = 0xFEDCBA98; + nvmdInfo.dataOffsetAddress = agIOCTLPayload->Reserved; + nvmdInfo.indirectPayload = 1; + nvmdInfo.indirectLen = RequestLength; + + if (nvmdInfo.NVMDevice == 0) { + nvmdInfo.TWIDeviceAddress = 0xa0; + nvmdInfo.TWIBusNumber = 0; + nvmdInfo.TWIDevicePageSize = 0; + nvmdInfo.TWIDeviceAddressSize = 1; + } + + if(RequestLength != 0) + { + if(ostiAllocMemory( tiRoot, + &osMemHandle, + (void **)&buffer, + &bufAddrUpper, + &bufAddrLower, + 8, + RequestLength, + agFALSE)) + return IOCTL_CALL_FAIL; + } + else + { + return IOCTL_CALL_FAIL; + } + + osti_memset((void *)buffer, 0, RequestLength); + + osti_memcpy((void *)buffer, + agIOCTLPayload->FunctionSpecificArea, + RequestLength); + + nvmdInfo.indirectAddrLower32 = bufAddrLower; + nvmdInfo.indirectAddrUpper32 = bufAddrUpper; + // use FW control place in shared structure to keep the neccesary information + tdsaAllShared->tdFWControlEx.buffer = osMemHandle; + tdsaAllShared->tdFWControlEx.virtAddr = buffer; + tdsaAllShared->tdFWControlEx.usrAddr = (bit8*)&agIOCTLPayload->FunctionSpecificArea[0]; + tdsaAllShared->tdFWControlEx.len = RequestLength; + tdsaAllShared->tdFWControlEx.param1 = agParam1; + tdsaAllShared->tdFWControlEx.param2 = agParam2; + tdsaAllShared->tdFWControlEx.payload = agIOCTLPayload; + tdsaAllShared->tdFWControlEx.inProgress = 1; + status = IOCTL_CALL_PENDING; + break; + default: + status = IOCTL_CALL_INVALID_CODE; + TI_DBG1(("tdsaNVMDSetIoctl: ERROR: Wrong IOCTL code %d\n", agIOCTLPayload->MinorFunction)); + break; + } + + if(saSetNVMDCommand(agRoot, agNULL, 0, &nvmdInfo) != AGSA_RC_SUCCESS) + { + status = IOCTL_CALL_FAIL; + agIOCTLPayload->Status = IOCTL_ERR_STATUS_INTERNAL_ERROR; + } + + return status; + +} + +/***************************************************************************** +* +* tdsaNVMDGetIoctl +* +* Purpose: This routine is called to get Config. SEEPROM information. +* This function is used for both target and initiator. +* +* Parameters: +* tiRoot: Pointer to driver instance +* agIOCTLPayload: Pointer to the IOCTL payload. +* agParam1: Pointer to pass context handle for IOCTL DMA operation +* agParam2: Pointer to pass context handle for IOCTL DMA operation +* agParam3: Pointer to pass context handle for IOCTL DMA operation +* +* Return: +* +* IOCTL_CALL_SUCCESS The requested operation completed successfully. +* IOCTL_CALL_FAIL Fail to complete the IOCTL request. +* Detail error code is function specific and +* defined by the specific IOCTL function. +* IOCTL_CALL_PENDING This request is asynchronous and completed +* in some other context. +* IOCTL_CALL_INVALID_CODE This IOCTL function is not recognized. +* +* +*****************************************************************************/ +osGLOBAL bit32 +tdsaNVMDGetIoctl( + tiRoot_t *tiRoot, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2, + void *agParam3 + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + agsaRoot_t *agRoot = &(tdsaAllShared->agRootInt); + void *buffer = agNULL; + void *osMemHandle = agNULL; + bit32 status = IOCTL_CALL_SUCCESS; + agsaNVMDData_t nvmdInfo; + bit32 Offset = 0; + bit32 RequestLength = 0; + bit32 ostiMemoryStatus = 0; + bit32 i,j; + bit8* seepromBuffer; + bit8* phySettingsBuffer; + + + TI_DBG2(("tdsaNVMDGetIoctl: start\n")); + + RequestLength = agIOCTLPayload->Length; + Offset = agIOCTLPayload->Reserved; + + osti_memset(&nvmdInfo, 0, sizeof(agsaNVMDData_t)); + /* This condition is not valid for direct read so commenting */ + /*if(!tiIS_SPC(agRoot)) { + if( RequestLength <= Offset ) //4096-max seeprom size + { + agIOCTLPayload->Status = IOCTL_ERR_STATUS_NO_MORE_DATA; + agIOCTLPayload->Length = 0; + status=IOCTL_CALL_SUCCESS; + return status; + } + }*/ + + agIOCTLPayload->Status = IOCTL_ERR_STATUS_OK; + + switch(agIOCTLPayload->MinorFunction) + { + case IOCTL_MN_NVMD_GET_CONFIG: + + // nvmdInfo.NVMDevice = 1; + nvmdInfo.NVMDevice = *((bit8*)agParam3); + nvmdInfo.signature = 0xFEDCBA98; + nvmdInfo.dataOffsetAddress = Offset; + nvmdInfo.indirectPayload = 1; + nvmdInfo.indirectLen = RequestLength; + + if (nvmdInfo.NVMDevice == 0) { + nvmdInfo.TWIDeviceAddress = 0xa0; + nvmdInfo.TWIBusNumber = 0; + nvmdInfo.TWIDevicePageSize = 0; + nvmdInfo.TWIDeviceAddressSize = 1; + } + + if(RequestLength != 0) + { + ostiMemoryStatus = ostiAllocMemory( tiRoot, + &osMemHandle, + (void **)&buffer, + &(nvmdInfo.indirectAddrUpper32), + &(nvmdInfo.indirectAddrLower32), + 8, + RequestLength, + agFALSE); + if((ostiMemoryStatus != tiSuccess) && (buffer == agNULL)) + return IOCTL_CALL_FAIL; + } + else + { + return IOCTL_CALL_FAIL; + } + osti_memset((void *)buffer, 0, RequestLength); + + // use FW control place in shared structure to keep the neccesary information + tdsaAllShared->tdFWControlEx.buffer = osMemHandle; + tdsaAllShared->tdFWControlEx.virtAddr = buffer; + tdsaAllShared->tdFWControlEx.usrAddr = (bit8*)&agIOCTLPayload->FunctionSpecificArea[0]; + tdsaAllShared->tdFWControlEx.len = RequestLength; + tdsaAllShared->tdFWControlEx.param1 = agParam1; + tdsaAllShared->tdFWControlEx.param2 = agParam2; + tdsaAllShared->tdFWControlEx.payload = agIOCTLPayload; + tdsaAllShared->tdFWControlEx.inProgress = 1; + status = IOCTL_CALL_PENDING; + break; + default: + status = IOCTL_CALL_INVALID_CODE; + TI_DBG1(("tiCOMMgntIOCTL: ERROR: Wrong IOCTL code %d\n", agIOCTLPayload->MinorFunction)); + break; + } + tdsaAllShared->NvmdResponseSet = 0; + + if(saGetNVMDCommand(agRoot, agNULL, 0, &nvmdInfo) != AGSA_RC_SUCCESS) + { + status = IOCTL_CALL_FAIL; + agIOCTLPayload->Status = IOCTL_ERR_STATUS_INTERNAL_ERROR; + return status; + } + /* Copy the SAS address */ + if(agParam1 == agNULL) + + { + while(!tdsaAllShared->NvmdResponseSet) + { + // tiCOMDelayedInterruptHandler(tiRoot, 0, 1, tiNonInterruptContext); + } + if(nvmdInfo.NVMDevice == 4 || nvmdInfo.NVMDevice == 1) + { + seepromBuffer = buffer; + /*Get Initiator SAS address*/ + + if(tiIS_SPC(agRoot)) + { + for(j=0,i=ADAPTER_WWN_SPC_START_OFFSET; i<= ADAPTER_WWN_SPC_END_OFFSET; i++,j++) + agIOCTLPayload->FunctionSpecificArea[j] = seepromBuffer[i]; + } + else + { + for(j=0,i=ADAPTER_WWN_START_OFFSET; i<= ADAPTER_WWN_END_OFFSET; i++,j++) + agIOCTLPayload->FunctionSpecificArea[j] = seepromBuffer[i]; + } + } + /* Copy the Phy settings */ + else if(nvmdInfo.NVMDevice == 6) + { + phySettingsBuffer = buffer; + for(i=0; iFunctionSpecificArea[i] = phySettingsBuffer[i]; + } + tdsaAllShared->NvmdResponseSet = 0; + ostiFreeMemory(tiRoot, tdsaAllShared->tdFWControlEx.buffer, tdsaAllShared->tdFWControlEx.len); + + } + return status; + +} + +/***************************************************************************** +* +* tdsaDeviceInfoGetIoctl +* +* Purpose: This routine is called to get the specified device information. +* +* Parameters: +* tiRoot: Pointer to driver instance +* agIOCTLPayload: Pointer to the IOCTL payload. +* agParam1: Pointer to pass context handle for IOCTL DMA operation +* agParam2: Pointer to pass context handle for IOCTL DMA operation +* agParam3: Pointer to pass context handle for IOCTL DMA operation +* +* Return: +* +* IOCTL_CALL_SUCCESS The requested operation completed successfully. +* IOCTL_CALL_FAIL Fail to complete the IOCTL request. +* Detail error code is function specific and +* defined by the specific IOCTL function. +* IOCTL_CALL_PENDING This request is asynchronous and completed +* in some other context. +* IOCTL_CALL_INVALID_CODE This IOCTL function is not recognized. +* +* +*****************************************************************************/ +osGLOBAL bit32 +tdsaDeviceInfoGetIoctl( + tiRoot_t *tiRoot, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2, + void *agParam3 + ) +{ + tdsaDeviceData_t *oneDeviceData = agNULL; + tiDeviceHandle_t *tiDeviceHandle = agNULL; + tdDeviceInfoPayload_t *pDeviceInfo = agNULL; + /*agsaDevHandle_t *agDevHandle = agNULL;*/ + bit32 status = IOCTL_CALL_SUCCESS; + + pDeviceInfo = (tdDeviceInfoPayload_t*)agIOCTLPayload->FunctionSpecificArea; + + TI_DBG3(("tdsaDeviceInfoGetIoctl: %d:%3d:%d %p %p %p\n", + (bit8)pDeviceInfo->PathId, + (bit8)pDeviceInfo->TargetId, + (bit8)pDeviceInfo->Lun, + agParam1, + agParam2, + agParam3)); + + tiDeviceHandle = ostiMapToDevHandle(tiRoot, + (bit8)pDeviceInfo->PathId, + (bit8)pDeviceInfo->TargetId, + (bit8)pDeviceInfo->Lun + ); + + if (tiDeviceHandle == agNULL) + { + TI_DBG1(("tdsaDeviceInfoGetIoctl: tiDeviceHandle is NULL !!!! SCSI address = %d:%3d:%d\n", + pDeviceInfo->PathId, pDeviceInfo->TargetId, pDeviceInfo->Lun)); + agIOCTLPayload->Status = IOCTL_ERR_STATUS_INVALID_DEVICE; + status = IOCTL_CALL_FAIL; + return status; + } + + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + if(oneDeviceData == agNULL) + { + TI_DBG1(("tdsaDeviceInfoGetIoctl: tiDeviceHandle=%p DeviceData is NULL!!! SCSI address = %d:%3d:%d\n", + tiDeviceHandle, pDeviceInfo->PathId, pDeviceInfo->TargetId, pDeviceInfo->Lun)); + agIOCTLPayload->Status = IOCTL_ERR_STATUS_INVALID_DEVICE; + status = IOCTL_CALL_FAIL; + return status; + } + + /* for hotplug */ + if (oneDeviceData->valid != agTRUE || oneDeviceData->registered != agTRUE || + oneDeviceData->tdPortContext == agNULL ) + { + TI_DBG1(("tdsaDeviceInfoGetIoctl: tiDeviceHandle=%p did %d DeviceData was removed!!! SCSI address = %d:%3d:%d\n", + tiDeviceHandle, oneDeviceData->id, pDeviceInfo->PathId, pDeviceInfo->TargetId, pDeviceInfo->Lun)); + agIOCTLPayload->Status = IOCTL_ERR_STATUS_INVALID_DEVICE; + status = IOCTL_CALL_FAIL; + return status; + } + + /* fill the device information in IOCTL payload */ + pDeviceInfo->devInfo.phyId = oneDeviceData->phyID; + osti_memcpy(&pDeviceInfo->devInfo.sasAddressHi, oneDeviceData->agDeviceInfo.sasAddressHi, sizeof(bit32)); + osti_memcpy(&pDeviceInfo->devInfo.sasAddressLo, oneDeviceData->agDeviceInfo.sasAddressLo, sizeof(bit32)); + + pDeviceInfo->devInfo.sasAddressHi = DMA_BEBIT32_TO_BIT32(pDeviceInfo->devInfo.sasAddressHi); + pDeviceInfo->devInfo.sasAddressLo = DMA_BEBIT32_TO_BIT32(pDeviceInfo->devInfo.sasAddressLo); + + pDeviceInfo->devInfo.deviceType = (oneDeviceData->agDeviceInfo.devType_S_Rate & 0x30) >> 4; + pDeviceInfo->devInfo.linkRate = oneDeviceData->agDeviceInfo.devType_S_Rate & 0x0F; + + agIOCTLPayload->Status = IOCTL_ERR_STATUS_OK; + + TI_DBG3(("tdsaDeviceInfoGetIoctl:IOCTL_CALL_SUCCESS\n")); + + /*saGetDeviceInfo(agRoot, agNULL, 0, 0, agDevHandle);*/ + + status = IOCTL_CALL_SUCCESS; + + return status; +} +/***************************************************************************** +* +* tdsaIoErrorStatisticGetIoctl +* +* Purpose: This routine is called to get the IO error statistic. +* +* Parameters: +* tiRoot: Pointer to driver instance +* agIOCTLPayload: Pointer to the IOCTL payload. +* agParam1: Pointer to pass context handle for IOCTL DMA operation +* agParam2: Pointer to pass context handle for IOCTL DMA operation +* agParam3: Pointer to pass context handle for IOCTL DMA operation +* +* Return: +* +* IOCTL_CALL_SUCCESS The requested operation completed successfully. +* IOCTL_CALL_FAIL Fail to complete the IOCTL request. +* Detail error code is function specific and +* defined by the specific IOCTL function. +* IOCTL_CALL_PENDING This request is asynchronous and completed +* in some other context. +* IOCTL_CALL_INVALID_CODE This IOCTL function is not recognized. +* +* +*****************************************************************************/ +osGLOBAL bit32 +tdsaIoErrorStatisticGetIoctl( + tiRoot_t *tiRoot, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2, + void *agParam3 + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + agsaRoot_t *agRoot = &(tdsaAllShared->agRootInt); + tdIoErrorStatisticPayload_t *pIoErrorPayload = agNULL; + bit32 status = IOCTL_CALL_SUCCESS; + + pIoErrorPayload = (tdIoErrorStatisticPayload_t*)agIOCTLPayload->FunctionSpecificArea; + + tdsaAllShared->tdFWControlEx.buffer = agNULL; + tdsaAllShared->tdFWControlEx.virtAddr = agNULL; + tdsaAllShared->tdFWControlEx.usrAddr = (bit8*)&agIOCTLPayload->FunctionSpecificArea[0]; + tdsaAllShared->tdFWControlEx.len = 0; + tdsaAllShared->tdFWControlEx.param1 = agParam1; + tdsaAllShared->tdFWControlEx.param2 = agParam2; + tdsaAllShared->tdFWControlEx.payload = agIOCTLPayload; + tdsaAllShared->tdFWControlEx.inProgress = 0; + + saGetIOErrorStats(agRoot, agNULL, pIoErrorPayload->flag); + + return status; +} + +/***************************************************************************** +* +* tdsaIoEventStatisticGetIoctl +* +* Purpose: This routine is called to get the IO event statistic. +* +* Parameters: +* tiRoot: Pointer to driver instance +* agIOCTLPayload: Pointer to the IOCTL payload. +* agParam1: Pointer to pass context handle for IOCTL DMA operation +* agParam2: Pointer to pass context handle for IOCTL DMA operation +* agParam3: Pointer to pass context handle for IOCTL DMA operation +* +* Return: +* +* IOCTL_CALL_SUCCESS The requested operation completed successfully. +* IOCTL_CALL_FAIL Fail to complete the IOCTL request. +* Detail error code is function specific and +* defined by the specific IOCTL function. +* IOCTL_CALL_PENDING This request is asynchronous and completed +* in some other context. +* IOCTL_CALL_INVALID_CODE This IOCTL function is not recognized. +* +* +*****************************************************************************/ +osGLOBAL bit32 +tdsaIoEventStatisticGetIoctl( + tiRoot_t *tiRoot, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2, + void *agParam3 + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + agsaRoot_t *agRoot = &(tdsaAllShared->agRootInt); + tdIoEventStatisticPayload_t *pIoEventPayload = agNULL; + bit32 status = IOCTL_CALL_SUCCESS; + + pIoEventPayload = (tdIoEventStatisticPayload_t*)agIOCTLPayload->FunctionSpecificArea; + + tdsaAllShared->tdFWControlEx.buffer = agNULL; + tdsaAllShared->tdFWControlEx.virtAddr = agNULL; + tdsaAllShared->tdFWControlEx.usrAddr = (bit8*)&agIOCTLPayload->FunctionSpecificArea[0]; + tdsaAllShared->tdFWControlEx.len = 0; + tdsaAllShared->tdFWControlEx.param1 = agParam1; + tdsaAllShared->tdFWControlEx.param2 = agParam2; + tdsaAllShared->tdFWControlEx.payload = agIOCTLPayload; + tdsaAllShared->tdFWControlEx.inProgress = 0; + + saGetIOEventStats(agRoot, agNULL, pIoEventPayload->flag); + + return status; +} + +/***************************************************************************** +* +* tdsaRegisterIoctl +* +* Purpose: This routine is called to get Forensic Data. +* +* Parameters: +* tiRoot: Pointer to driver instance +* agIOCTLPayload: Pointer to the IOCTL payload. +* agParam1: Pointer to pass context handle for IOCTL DMA operation +* agParam2: Pointer to pass context handle for IOCTL DMA operation +* agParam3: Pointer to pass context handle for IOCTL DMA operation +* +* Return: +* +* IOCTL_CALL_SUCCESS The requested operation completed successfully. +* IOCTL_CALL_FAIL Fail to complete the IOCTL request. +* Detail error code is function specific and +* defined by the specific IOCTL function. +* IOCTL_CALL_PENDING This request is asynchronous and completed +* in some other context. +* IOCTL_CALL_INVALID_CODE This IOCTL function is not recognized. +* +* +*****************************************************************************/ +osGLOBAL bit32 +tdsaRegisterIoctl( + tiRoot_t *tiRoot, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2, + void *agParam3 + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; +// agsaRoot_t *agRoot = &(tdsaAllShared->agRootInt); + tdRegisterPayload_t *pRegisterPayload = agNULL; + bit32 status = IOCTL_CALL_SUCCESS; + + pRegisterPayload = (tdRegisterPayload_t*)agIOCTLPayload->FunctionSpecificArea; + + tdsaAllShared->tdFWControlEx.buffer = agNULL; + tdsaAllShared->tdFWControlEx.virtAddr = agNULL; + tdsaAllShared->tdFWControlEx.usrAddr = (bit8*)&agIOCTLPayload->FunctionSpecificArea[0]; + tdsaAllShared->tdFWControlEx.len = 0; + tdsaAllShared->tdFWControlEx.param1 = agParam1; + tdsaAllShared->tdFWControlEx.param2 = agParam2; + tdsaAllShared->tdFWControlEx.payload = agIOCTLPayload; + tdsaAllShared->tdFWControlEx.inProgress = 0; + + TI_DBG1(("tdsaRegisterIoctl: Flag %d RegAddr 0x%x RegValue 0x%x\n", + pRegisterPayload->flag, pRegisterPayload->RegAddr, pRegisterPayload->RegValue)); + + if (pRegisterPayload->flag) + { + /* set register */ + ostiChipWriteBit32Ext(tiRoot, 0, pRegisterPayload->RegAddr, pRegisterPayload->RegValue); + } + else + { + /* get register */ + pRegisterPayload->RegValue = ostiChipReadBit32Ext(tiRoot, 0, pRegisterPayload->RegAddr); + } + agIOCTLPayload->Status = IOCTL_ERR_STATUS_OK; + return status; +} + +osGLOBAL bit32 +tdsaGetPhyGeneralStatusIoctl( + tiRoot_t *tiRoot, + agsaPhyGeneralState_t *PhyData + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + agsaRoot_t *agRoot = &(tdsaAllShared->agRootNonInt); +// agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); +// bit8 totalValidPhys; + bit32 status = AGSA_RC_SUCCESS; + bit32 i = 0; + agsaControllerInfo_t ControllerInfo; + saGetControllerInfo(agRoot,&ControllerInfo); + + TI_DBG3(("tdsaGetPhyGeneralStatusIoctl: start\n")); + do + { + if(tIsSPC(agRoot)||tIsSPCHIL(agRoot)) + { + status = IOCTL_ERR_STATUS_NOT_SUPPORTED; + break; + } + + PhyData->Reserved1 = ControllerInfo.phyCount; + for(i=0;iReserved1;i++) + { + status = saGetPhyProfile( agRoot,agNULL,tdsaRotateQnumber(tiRoot, agNULL), AGSA_SAS_PHY_GENERAL_STATUS_PAGE,i); + if(status == AGSA_RC_FAILURE) + { + break; + } + } + }while(0); + TI_DBG3(("tdsaGetPhyGeneralStatusIoctl: End\n")); + return status; +} +/***************************************************************************** +* +* ostiGetPhyGeneralStatusRsp +* +* Purpose: This routine is called when a PhyStatus IOCTL response is received. +* +* Parameters: +* tiRoot: Pointer to driver instance +* agsaSASPhyGeneralStatusPage_t: Status of the phy. +* bit32: phyID +* +* Return: none +* +* +*****************************************************************************/ +osGLOBAL void ostiGetPhyGeneralStatusRsp( + tiRoot_t *tiRoot, + agsaSASPhyGeneralStatusPage_t *GenStatus, + bit32 phyID + ) +{ + + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tiIOCTLPayload_t *agIoctlPayload = agNULL; + agsaPhyGeneralState_t *pSetPhyStatusRes = agNULL; + + + TI_DBG1(("ostiGetPhyGeneralStatusRsp: start\n")); + + if (tdsaAllShared->tdFWControlEx.inProgress) + { + agIoctlPayload = (tiIOCTLPayload_t *)(tdsaAllShared->tdFWControlEx.payload); + if ((agIoctlPayload) && (PMC_IOCTL_SIGNATURE == agIoctlPayload->Signature)&& + (IOCTL_MJ_PHY_GENERAL_STATUS == agIoctlPayload->MajorFunction)) + { + pSetPhyStatusRes = (agsaPhyGeneralState_t*) &agIoctlPayload->FunctionSpecificArea[0]; + osti_memcpy(&pSetPhyStatusRes->PhyGenData[phyID], GenStatus, sizeof(agsaSASPhyGeneralStatusPage_t)); + pSetPhyStatusRes->Reserved2++; + if(pSetPhyStatusRes->Reserved1 == pSetPhyStatusRes->Reserved2) + { + tdsaAllShared->tdFWControlEx.payload = NULL; + ostiIOCTLSetSignal(tiRoot, tdsaAllShared->tdFWControlEx.param1, + tdsaAllShared->tdFWControlEx.param2, agNULL); + tdsaAllShared->tdFWControlEx.inProgress = 0; + agIoctlPayload->Status = IOCTL_ERR_STATUS_OK; + + } + } + } + + TI_DBG1(("ostiGetPhyGeneralStatusRsp: end\n")); +} + + +osGLOBAL bit32 +tdsaPhyProfileIoctl( + tiRoot_t *tiRoot, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2, + void *agParam3 + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + agsaRoot_t *agRoot = &(tdsaAllShared->agRootInt); + void *buffer = agNULL; + void *osMemHandle = agNULL; + bit32 status = IOCTL_CALL_SUCCESS; + bit32 retcode = AGSA_RC_FAILURE; + bit32 RequestLength= agIOCTLPayload->Length; + bit32 bufAddrUpper = 0; + bit32 bufAddrLower = 0; + + tdPhyCount_t *PhyBlob = (tdPhyCount_t*)&agIOCTLPayload->FunctionSpecificArea[0]; + + + if(ostiAllocMemory( tiRoot, + &osMemHandle, + (void **)&buffer, + &bufAddrUpper, + &bufAddrLower, + RequestLength, + RequestLength, + agTRUE)) + return IOCTL_CALL_FAIL; + + + tdsaAllShared->tdFWControlEx.buffer = osMemHandle; + tdsaAllShared->tdFWControlEx.virtAddr = buffer; + tdsaAllShared->tdFWControlEx.usrAddr = (bit8*)&agIOCTLPayload->FunctionSpecificArea[0]; + tdsaAllShared->tdFWControlEx.len = 32; + tdsaAllShared->tdFWControlEx.param1 = agParam1; + tdsaAllShared->tdFWControlEx.param2 = agParam2; + tdsaAllShared->tdFWControlEx.payload = agIOCTLPayload; + tdsaAllShared->tdFWControlEx.inProgress = 1; + + TI_DBG1(("tdsaPhyProfileIoctl: MinorFunction %d\n",agIOCTLPayload->MinorFunction)); +// PhyBlob->Phy |= 0x100; + + if( tiIS_SPC(agRoot) ) + { + TI_DBG1(("tdsaPhyProfileIoctl: SPC operation 0x%x PHY %d\n",agIOCTLPayload->MinorFunction,PhyBlob->Phy)); + retcode = saLocalPhyControl(agRoot,agNULL,0 ,PhyBlob->Phy ,agIOCTLPayload->MinorFunction , agNULL); + if(retcode == AGSA_RC_SUCCESS) + { + status = IOCTL_CALL_PENDING; + } + } + else + { + TI_DBG1(("tdsaPhyProfileIoctl: SPCv operation 0x%x PHY %d\n",agIOCTLPayload->MinorFunction,PhyBlob->Phy)); + retcode = saGetPhyProfile( agRoot,agNULL,0,agIOCTLPayload->MinorFunction , PhyBlob->Phy); + + if(retcode == AGSA_RC_SUCCESS) + { + status = IOCTL_CALL_PENDING; + } + + } + + TI_DBG2(("tdsaPhyProfileIoctl: after\n")); + + + return status; +} + +/***************************************************************************** +* +* tdsaForensicDataGetIoctl +* +* Purpose: This routine is called to get Forensic Data. +* +* Parameters: +* tiRoot: Pointer to driver instance +* agIOCTLPayload: Pointer to the IOCTL payload. +* agParam1: Pointer to pass context handle for IOCTL DMA operation +* agParam2: Pointer to pass context handle for IOCTL DMA operation +* agParam3: Pointer to pass context handle for IOCTL DMA operation +* +* Return: +* +* IOCTL_CALL_SUCCESS The requested operation completed successfully. +* IOCTL_CALL_FAIL Fail to complete the IOCTL request. +* Detail error code is function specific and +* defined by the specific IOCTL function. +* IOCTL_CALL_PENDING This request is asynchronous and completed +* in some other context. +* IOCTL_CALL_INVALID_CODE This IOCTL function is not recognized. +* +* +*****************************************************************************/ +osGLOBAL bit32 +tdsaForensicDataGetIoctl( + tiRoot_t *tiRoot, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2, + void *agParam3 + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + agsaRoot_t *agRoot = &(tdsaAllShared->agRootInt); + tdForensicDataPayload_t *pForensicDataPayload = agNULL; + agsaForensicData_t ForensicData; + bit32 status = IOCTL_CALL_SUCCESS; + + pForensicDataPayload = (tdForensicDataPayload_t*)agIOCTLPayload->FunctionSpecificArea; + + tdsaAllShared->tdFWControlEx.buffer = agNULL; + tdsaAllShared->tdFWControlEx.virtAddr = agNULL; + tdsaAllShared->tdFWControlEx.usrAddr = (bit8*)&agIOCTLPayload->FunctionSpecificArea[0]; + tdsaAllShared->tdFWControlEx.len = 0; + tdsaAllShared->tdFWControlEx.param1 = agParam1; + tdsaAllShared->tdFWControlEx.param2 = agParam2; + tdsaAllShared->tdFWControlEx.payload = agIOCTLPayload; + tdsaAllShared->tdFWControlEx.inProgress = 0; + + osti_memset(&ForensicData, 0, sizeof(agsaForensicData_t)); + + ForensicData.DataType = pForensicDataPayload->DataType; + + switch (ForensicData.DataType) + { + case FORENSIC_DATA_TYPE_NON_FATAL: + case FORENSIC_DATA_TYPE_FATAL: + ForensicData.BufferType.dataBuf.directLen = pForensicDataPayload->dataBuffer.directLen; + ForensicData.BufferType.dataBuf.directOffset = pForensicDataPayload->dataBuffer.directOffset; + ForensicData.BufferType.dataBuf.readLen = pForensicDataPayload->dataBuffer.readLen; + ForensicData.BufferType.dataBuf.directData = (void*)pForensicDataPayload->dataBuffer.directData; + break; + case FORENSIC_DATA_TYPE_GSM_SPACE: + ForensicData.BufferType.gsmBuf.directLen = pForensicDataPayload->gsmBuffer.directLen; + ForensicData.BufferType.gsmBuf.directOffset = pForensicDataPayload->gsmBuffer.directOffset; + ForensicData.BufferType.dataBuf.readLen = pForensicDataPayload->gsmBuffer.readLen; + ForensicData.BufferType.gsmBuf.directData = (void*)pForensicDataPayload->gsmBuffer.directData; + break; + + case FORENSIC_DATA_TYPE_IB_QUEUE: + ForensicData.BufferType.queueBuf.directLen = pForensicDataPayload->queueBuffer.directLen; + //ForensicData.BufferType.queueBuf.queueType = pForensicDataPayload->queueBuffer.queueType; + ForensicData.BufferType.queueBuf.queueType = FORENSIC_DATA_TYPE_IB_QUEUE; + ForensicData.BufferType.queueBuf.queueIndex = pForensicDataPayload->queueBuffer.queueIndex; + ForensicData.BufferType.queueBuf.directData = (void*)pForensicDataPayload->queueBuffer.directData; + break; + case FORENSIC_DATA_TYPE_OB_QUEUE: + ForensicData.BufferType.queueBuf.directLen = pForensicDataPayload->queueBuffer.directLen; + ForensicData.BufferType.queueBuf.queueType = FORENSIC_DATA_TYPE_OB_QUEUE; + ForensicData.BufferType.queueBuf.queueIndex = pForensicDataPayload->queueBuffer.queueIndex; + ForensicData.BufferType.queueBuf.directData = (void*)pForensicDataPayload->queueBuffer.directData; + break; + + default: + TI_DBG1(("tdsaGetForensicDataIoctl: forensic data type error %d\n", pForensicDataPayload->DataType)); + status = IOCTL_CALL_INVALID_CODE; + return status; + } + + if ( saGetForensicData(agRoot, agNULL, &ForensicData) != AGSA_RC_SUCCESS ) + { + status = IOCTL_CALL_FAIL; + } + + return status; +} + +osGLOBAL bit32 +tdsaSendSMPIoctl( + tiRoot_t *tiRoot, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2, + void *agParam3 + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + agsaRoot_t *agRoot = &(tdsaAllShared->agRootInt); + void *reqBuffer = agNULL; + void *respBuffer = agNULL; + void *osMemHandle = agNULL; + bit32 status = IOCTL_CALL_SUCCESS; +// bit32 Offset = 0; +// bit32 RequestLength = 0; + bit32 ostiMemoryStatus = 0; + smp_pass_through_req_t *smp_pass_through_req; + + tiDeviceHandle_t *devHandle; + agsaSMPFrame_t agSMPFrame; + tdsaDeviceData_t *oneDeviceData = agNULL; + bit32 i; + + TI_DBG2(("tdsaSendSMPIoctl: start\n")); + + smp_pass_through_req = (smp_pass_through_req_t*)agIOCTLPayload->FunctionSpecificArea; + + for(i=0;i<8;i++) + TI_DBG2(("SAS Address[%d]:%x",i,smp_pass_through_req->exp_sas_addr[i])); + TI_DBG2(("SAS Request Length:%d",smp_pass_through_req->smp_req_len)); + TI_DBG2(("SAS Response Length:%d",smp_pass_through_req->smp_resp_len)); + for(i=0;ismp_req_len;i++) + TI_DBG2(("SAS request + %d:%x",i,smp_pass_through_req->smp_req_resp[i])); + + devHandle = ostiGetDevHandleFromSasAddr(tiRoot, smp_pass_through_req->exp_sas_addr); + if(devHandle == NULL) + { + status = IOCTL_CALL_FAIL; + agIOCTLPayload->Status = IOCTL_ERR_STATUS_INTERNAL_ERROR; + return status; + } + + + + //agIOCTLPayload->Status = IOCTL_ERR_STATUS_OK; + agIOCTLPayload->Status = IOCTL_ERR_STATUS_NOT_RESPONDING; + + + + if((ostiMemoryStatus != tiSuccess) && (reqBuffer == agNULL )) + return IOCTL_CALL_FAIL; + + + tdsaAllShared->tdFWControlEx.param3 = osMemHandle; + + + agSMPFrame.outFrameBuf = smp_pass_through_req->smp_req_resp; + agSMPFrame.expectedRespLen = smp_pass_through_req->smp_resp_len; + agSMPFrame.inFrameLen = smp_pass_through_req->smp_resp_len - 4; + + if(!(smp_pass_through_req->smp_req_len - 8) && !tiIS_SPC(agRoot)) + { + agSMPFrame.flag = 1; // Direct request Indirect response + agSMPFrame.outFrameLen = smp_pass_through_req->smp_req_len - 4; //Exclude header + } + else + { + + agSMPFrame.flag = 3; //Indirect request and Indirect response + ostiMemoryStatus = ostiAllocMemory( tiRoot, + &osMemHandle, + (void **)&reqBuffer, + &(agSMPFrame.outFrameAddrUpper32), + &(agSMPFrame.outFrameAddrLower32), + 8, + smp_pass_through_req->smp_req_len, + agFALSE); + tdsaAllShared->tdFWControlEx.param3 = osMemHandle; + if(tiIS_SPC(agRoot)) + { + agSMPFrame.outFrameLen = smp_pass_through_req->smp_req_len - 4; //Exclude crc + osti_memcpy((void *)reqBuffer, (void *)(smp_pass_through_req->smp_req_resp), smp_pass_through_req->smp_req_len); + } + else + { + agSMPFrame.outFrameLen = smp_pass_through_req->smp_req_len - 8; //Exclude header and crc + osti_memcpy((void *)reqBuffer, (void *)(smp_pass_through_req->smp_req_resp + 4), smp_pass_through_req->smp_req_len - 4); + } + } + + ostiMemoryStatus = ostiAllocMemory( tiRoot, + &osMemHandle, + (void **)&respBuffer, + &(agSMPFrame.inFrameAddrUpper32), + &(agSMPFrame.inFrameAddrLower32), + 8, + smp_pass_through_req->smp_resp_len + 4, + agFALSE); + if((ostiMemoryStatus != tiSuccess) && (respBuffer == agNULL )) + return IOCTL_CALL_FAIL; + + + osti_memset((void *)respBuffer, 0, smp_pass_through_req->smp_resp_len); + + // use FW control place in shared structure to keep the neccesary information + tdsaAllShared->tdFWControlEx.buffer = osMemHandle; + tdsaAllShared->tdFWControlEx.virtAddr = respBuffer; + tdsaAllShared->tdFWControlEx.usrAddr = (bit8*)smp_pass_through_req->smp_req_resp + smp_pass_through_req->smp_req_len; + tdsaAllShared->tdFWControlEx.len = smp_pass_through_req->smp_resp_len; + tdsaAllShared->tdFWControlEx.param1 = agParam1; + tdsaAllShared->tdFWControlEx.param2 = agParam2; + tdsaAllShared->tdFWControlEx.payload = agIOCTLPayload; + tdsaAllShared->tdFWControlEx.inProgress = 1; + status = IOCTL_CALL_PENDING; + + oneDeviceData = (tdsaDeviceData_t *)devHandle->tdData; + if(saSendSMPIoctl(agRoot, oneDeviceData->agDevHandle, 0, &agSMPFrame, &ossaSMPIoctlCompleted) != AGSA_RC_SUCCESS) + { + status = IOCTL_CALL_FAIL; + agIOCTLPayload->Status = IOCTL_ERR_STATUS_INTERNAL_ERROR; + } + return status; +} + +osGLOBAL void ostiSendSMPIOCTLRsp( + tiRoot_t *tiRoot, + bit32 status + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tiIOCTLPayload_t *agIOCTLPayload; + + agIOCTLPayload = (tiIOCTLPayload_t *)(tdsaAllShared->tdFWControlEx.payload); + agIOCTLPayload->Status = (bit16)status; + + TI_DBG1(("ostiSendSMPIOCTLRsp: start, status = %d\n", status)); + +// if(tdsaAllShared->tdFWControlEx.param1 != agNULL) +// { + osti_memcpy((void *)(tdsaAllShared->tdFWControlEx.usrAddr), + (void *)(tdsaAllShared->tdFWControlEx.virtAddr), + tdsaAllShared->tdFWControlEx.len); +// } + ostiFreeMemory(tiRoot, + tdsaAllShared->tdFWControlEx.buffer, + tdsaAllShared->tdFWControlEx.len); + ostiFreeMemory(tiRoot, + tdsaAllShared->tdFWControlEx.param3, + tdsaAllShared->tdFWControlEx.len); + //if(tdsaAllShared->tdFWControlEx.param1 != agNULL) +// { + ostiIOCTLComplete(tiRoot, + tdsaAllShared->tdFWControlEx.param1, + tdsaAllShared->tdFWControlEx.param2, + NULL); +// } +} + + + + +/***************************************************************************** +* +* tdsaSendBISTIoctl +* +* Purpose: This routine is called to get Forensic Data. +* +* Parameters: +* tiRoot: Pointer to driver instance +* agIOCTLPayload: Pointer to the IOCTL payload. +* agParam1: Pointer to pass context handle for IOCTL DMA operation +* agParam2: Pointer to pass context handle for IOCTL DMA operation +* agParam3: Pointer to pass context handle for IOCTL DMA operation +* +* Return: +* +* IOCTL_CALL_SUCCESS The requested operation completed successfully. +* IOCTL_CALL_FAIL Fail to complete the IOCTL request. +* Detail error code is function specific and +* defined by the specific IOCTL function. +* IOCTL_CALL_PENDING This request is asynchronous and completed +* in some other context. +* IOCTL_CALL_INVALID_CODE This IOCTL function is not recognized. +* +* +*****************************************************************************/ +osGLOBAL bit32 +tdsaSendBISTIoctl( + tiRoot_t *tiRoot, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2, + void *agParam3 + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + agsaRoot_t *agRoot = &(tdsaAllShared->agRootInt); + tdBistPayload_t *pBistPayload; +// bit32 length = 0; +// bit32 status = IOCTL_CALL_SUCCESS; + bit32 status = IOCTL_CALL_FAIL; + + pBistPayload = (tdBistPayload_t*)agIOCTLPayload->FunctionSpecificArea; + + tdsaAllShared->tdFWControlEx.buffer = agNULL; + tdsaAllShared->tdFWControlEx.virtAddr = agNULL; + tdsaAllShared->tdFWControlEx.usrAddr = (bit8*)&agIOCTLPayload->FunctionSpecificArea[0]; + tdsaAllShared->tdFWControlEx.len = 0; + tdsaAllShared->tdFWControlEx.param1 = agParam1; + tdsaAllShared->tdFWControlEx.param2 = agParam2; + tdsaAllShared->tdFWControlEx.payload = agIOCTLPayload; + tdsaAllShared->tdFWControlEx.inProgress = 0; + + TI_DBG1(("tdsaSendBISTIoctl: Type %d Length %d Data %p\n", + pBistPayload->testType, + pBistPayload->testLength, + pBistPayload->testData )); + + + // pBistPayload->testtype = AGSA_BIST_TEST; + + if( pBistPayload->testType == AGSA_BIST_TEST) + { + if( pBistPayload->testLength != sizeof(agsaEncryptSelfTestBitMap_t)) + { + return status; + } + } + else if( pBistPayload->testType == AGSA_SHA_TEST) + { + if( pBistPayload->testLength != sizeof(agsaEncryptSHATestDescriptor_t) ) + { + return status; + } + } + else if( pBistPayload->testType == AGSA_HMAC_TEST ) + { + if( pBistPayload->testLength != sizeof(agsaEncryptHMACTestDescriptor_t)) + { + return status; + } + } + +/* +GLOBAL bit32 saEncryptSelftestExecute( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 queueNum, + bit32 type, + bit32 length, + void *TestDescriptor); + +*/ + if ( saEncryptSelftestExecute(agRoot, + agNULL, + 0, + pBistPayload->testType, + pBistPayload->testLength, + pBistPayload->testData ) != AGSA_RC_SUCCESS ) + { + status = IOCTL_CALL_FAIL; + } + + return status; +} + + +osGLOBAL bit32 +tdsaSendTMFIoctl( tiRoot_t *tiRoot, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2, + unsigned long resetType + ) +{ + bit32 status; + tmf_pass_through_req_t *tmf_req = (tmf_pass_through_req_t*)agIOCTLPayload->FunctionSpecificArea; +#if !(defined(__FreeBSD__)) + status = ostiSendResetDeviceIoctl(tiRoot, agParam2, tmf_req->pathId, tmf_req->targetId, tmf_req->lun, resetType); +#endif + TI_DBG3(("Status returned from ostiSendResetDeviceIoctl is %d\n",status)); + if(status != IOCTL_CALL_SUCCESS) + { + agIOCTLPayload->Status = status; + return status; + } + status = IOCTL_CALL_SUCCESS; + return status; +} + + +#ifdef VPD_TESTING +/* temporary to test saSetVPDCommand() and saGetVPDCommand */ +osGLOBAL bit32 +tdsaVPDSet( + tiRoot_t *tiRoot + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + agsaRoot_t *agRoot = &(tdsaAllShared->agRootInt); + bit32 status = IOCTL_CALL_SUCCESS; + agsaVPD_t VPDInfo; + bit32 ret = AGSA_RC_SUCCESS; + + bit32 bufAddrUpper = 0; + bit32 bufAddrLower = 0; + tdVPDControl_t *VPDControl; + + void *osMemHandle = agNULL; + void *buffer; + bit32 timeCount=0; + bit8 ioctlErr=0; + bit8 VPDPayload[32]; + bit8 i; + TI_DBG2(("tdsaVPDSet: start\n")); + + for(i=0;itdFWControlEx.buffer = osMemHandle; + tdsaAllShared->tdFWControlEx.param1 = agParam1; + tdsaAllShared->tdFWControlEx.param2 = agParam2; + + /* for testing only */ + tdsaAllShared->addrUpper = bufAddrUpper; + tdsaAllShared->addrLower = bufAddrLower; + + ret = saSetVPDCommand(agRoot, agNULL, 0, &VPDInfo); + + if (ret == AGSA_RC_SUCCESS) + { + status = tiSuccess; + } + else + { + status = tiError; + } + + ostiFreeMemory(tiRoot, osMemHandle, sizeof(VPDPayload)); + return status; +} + +/* temporary to test saSetVPDCommand() and saGetVPDCommand */ +osGLOBAL bit32 +tdsaVPDGet(tiRoot_t *tiRoot) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + agsaRoot_t *agRoot = &(tdsaAllShared->agRootInt); + bit32 status = IOCTL_CALL_SUCCESS; + agsaVPD_t VPDInfo; + bit32 ret = AGSA_RC_SUCCESS; + + + TI_DBG2(("tdsaVPDGet: start\n")); + + osti_memset(&VPDInfo, 0, sizeof(agsaVPD_t)); + + /* direct mode worked */ + VPDInfo.indirectMode = 0; /* direct mode */ + VPDInfo.VPDDevice = 1; /* SEEPROM-1*/ + VPDInfo.directLen = 32; + VPDInfo.VPDOffset = 0; + VPDInfo.directData = agNULL; + VPDInfo.indirectAddrUpper32 = 0; + VPDInfo.indirectAddrLower32 = 0; + VPDInfo.indirectLen = 0; + + +#ifdef NOT_YET /* worked; can't read VPD in ossaGetVPDResponseCB() because of indirect */ + VPDInfo.indirectMode = 1; /* direct mode */ + VPDInfo.VPDDevice = 1; /* SEEPROM-1*/ + VPDInfo.directLen = 0; + VPDInfo.VPDOffset = 0; + VPDInfo.directData = agNULL; + VPDInfo.indirectAddrUpper32 = tdsaAllShared->addrUpper; + VPDInfo.indirectAddrLower32 = tdsaAllShared->addrLower; + VPDInfo.indirectLen = 32; +#endif + ret = saGetVPDCommand(agRoot, agNULL, 0, &VPDInfo); + + if (ret == AGSA_RC_SUCCESS) + { + status = tiSuccess; + } + else + { + status = tiError; + } + return status; +} +#endif +/***************************************************************************** +* +* tdsaGetNumOfLUNIOCTL +* +* Purpose: This routine is called to send Report LUN SSP command request. +* +* Parameters: +* tiRoot: Pointer to driver instance +* tiIOCTLPayload_t: Status of the Controller Reset. +* agParam1: Void pointer to device extension +* agParam2: Void pointer to SRB +* agParam3: NULL +* +* Return: status +* +* +*****************************************************************************/ +osGLOBAL bit32 +tdsaGetNumOfLUNIOCTL( + tiRoot_t *tiRoot, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2, + void *agParam3 + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + agsaRoot_t *agRoot = &(tdsaAllShared->agRootInt); + tdDeviceLUNInfoIOCTL_t *pDeviceLUNInfo = agNULL; + tiDeviceHandle_t *devHandle = agNULL; + void *tiRequestBody = agNULL; + tiIORequest_t *tiIORequest = agNULL; + bit32 status = IOCTL_CALL_SUCCESS; + + TI_DBG2(("tdsaGetNumOfLUNIOCTL: Start\n")); + do + { + pDeviceLUNInfo = (tdDeviceLUNInfoIOCTL_t*)agIOCTLPayload->FunctionSpecificArea; + + if (agIOCTLPayload->Length < sizeof(tdDeviceLUNInfoIOCTL_t)) + { + status = IOCTL_CALL_FAIL; + break; + } + if(!pDeviceLUNInfo->tiDeviceHandle) + { + status = IOCTL_CALL_FAIL; + agIOCTLPayload->Status = IOCTL_ERR_STATUS_INTERNAL_ERROR; + break; + } + devHandle = (tiDeviceHandle_t*)pDeviceLUNInfo->tiDeviceHandle; + agIOCTLPayload->Status = IOCTL_ERR_STATUS_OK; + + status = ostiNumOfLUNIOCTLreq(tiRoot,agParam1,agParam2,&tiRequestBody,&tiIORequest); + + + if(status != AGSA_RC_SUCCESS) + { + agIOCTLPayload->Status = IOCTL_ERR_STATUS_INTERNAL_ERROR; + break; + } + status = tiNumOfLunIOCTLreq(tiRoot,tiIORequest,devHandle,tiRequestBody,agIOCTLPayload,agParam1,agParam2); + + if(status != AGSA_RC_SUCCESS) + { + agIOCTLPayload->Status = IOCTL_ERR_STATUS_INTERNAL_ERROR; + break; + } +// ostiIOCTLWaitForSignal (tiRoot, agParam1, agParam2, agParam3); + + }while(0); + TI_DBG2(("tdsaGetNumOfLUNIOCTL: End\n")); + return status; +} + + +/***************************************************************************** +* +* ostiNumOfLUNIOCTLRsp +* +* Purpose: This routine is called when a Report LUN SSP command response id recieved. +* +* Parameters: +* tiRoot: Pointer to driver instance +* bit32 status +* +* Return: none +* +* +*****************************************************************************/ +osGLOBAL void ostiNumOfLUNIOCTLRsp( + tiRoot_t *tiRoot, + bit32 status + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tiIOCTLPayload_t *agIOCTLPayload; + tdDeviceLUNInfoIOCTL_t *pDeviceLUNInfo = NULL; + bit32 count = 0; + bit32 numOfLUN =0; + + TI_DBG1(("ostiNumOfLUNIOCTLRsp: start, status = %d\n", status)); + + if(tdsaAllShared->tdFWControlEx.inProgress == 1) + { + agIOCTLPayload = (tiIOCTLPayload_t *)(tdsaAllShared->tdFWControlEx.payload); + if ((agIOCTLPayload) && (PMC_IOCTL_SIGNATURE == agIOCTLPayload->Signature)&& + (IOCTL_MJ_GET_DEVICE_LUN == agIOCTLPayload->MajorFunction)) + { + agIOCTLPayload->Status = (bit16)status; + pDeviceLUNInfo = (tdDeviceLUNInfoIOCTL_t*)agIOCTLPayload->FunctionSpecificArea; + numOfLUN = ((tdsaAllShared->tdFWControlEx.virtAddr[0] << 24)|(tdsaAllShared->tdFWControlEx.virtAddr[1] << 16)|\ + (tdsaAllShared->tdFWControlEx.virtAddr[2] << 8)|(tdsaAllShared->tdFWControlEx.virtAddr[3])); + numOfLUN = numOfLUN/8; + pDeviceLUNInfo->numOfLun = numOfLUN; +// ostiFreeMemory(tiRoot, +// tdsaAllShared->tdFWControlEx.virtAddr, +// tdsaAllShared->tdFWControlEx.len); + // if(tdsaAllShared->tdFWControlEx.param1 != agNULL) + // { + ostiIOCTLSetSignal(tiRoot, + tdsaAllShared->tdFWControlEx.param1, + tdsaAllShared->tdFWControlEx.param2, + NULL); + tdsaAllShared->tdFWControlEx.payload = NULL; + // } + + tdsaAllShared->tdFWControlEx.inProgress = 0; + } + } + TI_DBG1(("ostiNumOfLUNIOCTLRsp: End\n")); +} + diff --git a/sys/dev/pms/RefTisa/tisa/sassata/common/tdioctl.h b/sys/dev/pms/RefTisa/tisa/sassata/common/tdioctl.h new file mode 100644 index 000000000000..8c1b42facf88 --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/common/tdioctl.h @@ -0,0 +1,687 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +*******************************************************************************/ +/***************************************************************************** +* +* tdioctl.h +* +* Abstract: This module contains data structure definition used +* by the Transport Dependent (TD) Layer IOCTL. +* +* +* Notes: +* +* +** MODIFICATION HISTORY ****************************************************** +* +* NAME DATE DESCRIPTION +* ---- ---- ----------- +* IWN 12/11/02 Initial creation. +* +* +*****************************************************************************/ + + +#ifndef TD_IOCTL_H + +#define TD_IOCTL_H + +//#include "global.h" + +/* + * PMC-Sierra IOCTL signature + */ +#define PMC_SIERRA_SIGNATURE 0x1234 +#define PMC_SIERRA_IOCTL_SIGNATURE "PMC-STRG" + +/* + * Major function code of IOCTL functions, common to target and initiator. + */ +#define IOCTL_MJ_CARD_PARAMETER 0x01 +#define IOCTL_MJ_FW_CONTROL 0x02 +#define IOCTL_MJ_NVMD_GET 0x03 +#define IOCTL_MJ_NVMD_SET 0x04 +#define IOCTL_MJ_GET_EVENT_LOG1 0x05 +#define IOCTL_MJ_GET_EVENT_LOG2 0x06 +#define IOCTL_MJ_GET_CORE_DUMP 0x07 +#define IOCTL_MJ_LL_TRACING 0x08 +#define IOCTL_MJ_FW_PROFILE 0x09 +#define IOCTL_MJ_MNID 0x0A +#define IOCTL_MJ_ENCRYPTION_CTL 0x0B + +#define IOCTL_MJ_FW_INFO 0x0C + +#define IOCTL_MJ_LL_API_TEST 0x11 +#define IOCTL_MJ_CHECK_DPMC_EVENT 0x16 +#define IOCTL_MJ_GET_FW_REV 0x1A +#define IOCTL_MJ_GET_DEVICE_INFO 0x1B +#define IOCTL_MJ_GET_IO_ERROR_STATISTIC 0x1C +#define IOCTL_MJ_GET_IO_EVENT_STATISTIC 0x1D +#define IOCTL_MJ_GET_FORENSIC_DATA 0x1E +#define IOCTL_MJ_GET_DEVICE_LIST 0x1F +#define IOCTL_MJ_SMP_REQUEST 0x6D +#define IOCTL_MJ_GET_DEVICE_LUN 0x7A1 +#define IOCTL_MJ_PHY_GENERAL_STATUS 0x7A6 +#define IOCTL_MJ_PHY_DETAILS 0x7A7 +#define IOCTL_MJ_SEND_BIST 0x20 +#define IOCTL_MJ_CHECK_FATAL_ERROR 0x70 +#define IOCTL_MJ_FATAL_ERROR_DUMP_COMPLETE 0x71 +#define IOCTL_MJ_GPIO 0x41 +#define IOCTL_MJ_SGPIO 0x42 +#define IOCTL_MJ_SEND_TMF 0x6E +#define IOCTL_MJ_FATAL_ERROR_SOFT_RESET_TRIG 0x72 +#define IOCTL_MJ_FATAL_ERR_CHK_RET_FALSE 0x76 +#define IOCTL_MJ_FATAL_ERR_CHK_SEND_FALSE 0x76 +#define IOCTL_MJ_FATAL_ERR_CHK_SEND_TRUE 0x77 + + +/* + * Major function code of IOCTL functions, specific to initiator. + */ +#define IOCTL_MJ_INI_ISCSI_DISCOVERY 0x21 +#define IOCTL_MJ_INI_SESSION_CONTROL 0x22 +#define IOCTL_MJ_INI_SNIA_IMA 0x23 +#define IOCTL_MJ_INI_SCSI 0x24 +#define IOCTL_MJ_INI_WMI 0x25 +#define IOCTL_MJ_INI_DRIVER_EVENT_LOG 0x26 +#define IOCTL_MJ_INI_PERSISTENT_BINDING 0x27 +#define IOCTL_MJ_INI_DRIVER_IDENTIFY 0x28 + +/* temp */ +#define IOCTL_MJ_PORT_STOP 0x29 +#define IOCTL_MJ_PORT_START 0x30 + +/* SPCv controller configuration page commands */ +#define IOCTL_MJ_MODE_CTL_PAGE 0x40 + +#define IOCTL_MJ_SET_OR_GET_REGISTER 0x41 + +#define IOCTL_MJ_GET_PHY_PROFILE 0x44 +#define IOCTL_MJ_SET_PHY_PROFILE 0x43 + +#define IOCTL_MJ_GET_DRIVER_VERSION 0x101 + +#define IOCTL_MN_PHY_PROFILE_COUNTERS 0x01 +#define IOCTL_MN_PHY_PROFILE_COUNTERS_CLR 0x02 +#define IOCTL_MN_PHY_PROFILE_BW_COUNTERS 0x03 +#define IOCTL_MN_PHY_PROFILE_ANALOG_SETTINGS 0x04 + +/* + * Minor functions for Card parameter IOCTL functions. + */ +#define IOCTL_MN_CARD_GET_VPD_INFO 0x01 +#define IOCTL_MN_CARD_GET_PORTSTART_INFO 0x02 +#define IOCTL_MN_CARD_GET_INTERRUPT_CONFIG 0x03 +#define IOCTL_MN_CARD_GET_PHY_ANALOGSETTING 0x04 +#define IOCTL_MN_CARD_GET_TIMER_CONFIG 0x05 +#define IOCTL_MN_CARD_GET_TYPE_FATAL_DUMP 0x06 + +/* + * Minor functions for FW control IOCTL functions. + */ + +/* Send FW data requests. + */ +#define IOCTL_MN_FW_DOWNLOAD_DATA 0x01 + +/* Send the request for burning the new firmware. + */ +#define IOCTL_MN_FW_DOWNLOAD_BURN 0x02 + +/* Poll for the flash burn phases. Sequences of poll function calls are + * needed following the IOCTL_MN_FW_DOWNLOAD_BURN, IOCTL_MN_FW_BURN_OSPD + * and IOCTL_MN_FW_ROLL_BACK_FW functions. + */ +#define IOCTL_MN_FW_BURN_POLL 0x03 + +/* Instruct the FW to roll back FW to prior revision. + */ +#define IOCTL_MN_FW_ROLL_BACK_FW 0x04 + +/* Instruct the FW to return the current firmware revision number. + */ +#define IOCTL_MN_FW_VERSION 0x05 + +/* Retrieve the maximum size of the OS Persistent Data stored on the card. + */ +#define IOCTL_MN_FW_GET_OSPD_SIZE 0x06 + +/* Retrieve the OS Persistent Data from the card. + */ +#define IOCTL_MN_FW_GET_OSPD 0x07 + +/* Send a new OS Persistent Data to the card and burn in flash. + */ +#define IOCTL_MN_FW_BURN_OSPD 0x08 + +/* Retrieve the trace buffer from the card FW. Only available on the debug + * version of the FW. + */ +#define IOCTL_MN_FW_GET_TRACE_BUFFER 0x0f + +#define IOCTL_MN_NVMD_GET_CONFIG 0x0A +#define IOCTL_MN_NVMD_SET_CONFIG 0x0B + +#define IOCTL_MN_FW_GET_CORE_DUMP_AAP1 0x0C +#define IOCTL_MN_FW_GET_CORE_DUMP_IOP 0x0D +#define IOCTL_MN_FW_GET_CORE_DUMP_FLASH_AAP1 0x12 +#define IOCTL_MN_FW_GET_CORE_DUMP_FLASH_IOP 0x13 + +#define IOCTL_MN_LL_RESET_TRACE_INDEX 0x0e +#define IOCTL_MN_LL_GET_TRACE_BUFFER_INFO 0x0f +#define IOCTL_MN_LL_GET_TRACE_BUFFER 0x10 + +#define IOCTL_MN_ENCRYPTION_GET_INFO 0x13 +#define IOCTL_MN_ENCRYPTION_SET_MODE 0x14 +#define IOCTL_MN_ENCRYPTION_KEK_ADD 0x15 +#define IOCTL_MN_ENCRYPTION_DEK_ADD 0x16 +#define IOCTL_MN_ENCRYPTION_DEK_INVALID 0x17 +#define IOCTL_MN_ENCRYPTION_KEK_NVRAM 0x18 +#define IOCTL_MN_ENCRYPTION_DEK_ASSIGN 0x19 +#define IOCTL_MN_ENCRYPTION_LUN_QUERY 0x1A +#define IOCTL_MN_ENCRYPTION_KEK_LOAD_NVRAM 0x1B +#define IOCTL_MN_ENCRYPTION_ERROR_QUERY 0x1C +#define IOCTL_MN_ENCRYPTION_DEK_TABLE_INIT 0x1D +#define IOCTL_MN_ENCRYPT_LUN_VERIFY 0x1E +#define IOCTL_MN_ENCRYPT_OPERATOR_MGMT 0x1F +#define IOCTL_MN_ENCRYPT_SET_DEK_CONFIG_PAGE 0x21 +#define IOCTL_MN_ENCRYPT_SET_CONTROL_PAGE 0x22 +#define IOCTL_MN_ENCRYPT_SET_OPERATOR_CMD 0x23 +#define IOCTL_MN_ENCRYPT_TEST_EXECUTE 0x24 +#define IOCTL_MN_ENCRYPT_SET_HMAC_CONFIG_PAGE 0x25 +#define IOCTL_MN_ENCRYPT_GET_OPERATOR_CMD 0x26 +#define IOCTL_MN_ENCRYPT_RESCAN 0x27 +#ifdef SOFT_RESET_TEST +#define IOCTL_MN_SOFT_RESET 0x28 +#endif +/* SPCv configuration pages */ +#define IOCTL_MN_MODE_SENSE 0x30 +#define IOCTL_MN_MODE_SELECT 0x31 + +#define IOCTL_MN_TISA_TEST_ENCRYPT_DEK_DUMP 0x51 + +#define IOCTL_MN_FW_GET_EVENT_FLASH_LOG1 0x5A +#define IOCTL_MN_FW_GET_EVENT_FLASH_LOG2 0x6A +#define IOCTL_MN_GET_EVENT_LOG1 0x5B +#define IOCTL_MN_GET_EVENT_LOG2 0x6B + +#define IOCTL_MN_GPIO_PINSETUP 0x01 +#define IOCTL_MN_GPIO_EVENTSETUP 0x02 +#define IOCTL_MN_GPIO_READ 0x03 +#define IOCTL_MN_GPIO_WRITE 0x04 + +#define IOCTL_MN_TMF_DEVICE_RESET 0x6F +#define IOCTL_MN_TMF_LUN_RESET 0x70 +typedef struct tdFWControl +{ + bit32 retcode; /* ret code (status) = (bit32)oscmCtrlEvnt_e */ + bit32 phase; /* ret code phase = (bit32)agcmCtrlFwPhase_e */ + bit32 phaseCmplt; /* percent complete for the current update phase */ + bit32 version; /* Hex encoded firmware version number */ + bit32 offset; /* Used for downloading firmware */ + bit32 len; /* len of buffer */ + bit32 size; /* Used in OS VPD and Trace get size operations. */ + bit32 reserved; /* padding required for 64 bit alignment */ + bit8 buffer[1]; /* Start of buffer */ +} tdFWControl_t; + + +typedef struct tdFWControlEx +{ + tdFWControl_t *tdFWControl; + bit8 *buffer; // keep buffer pointer to be freed when the responce comes + bit8 *virtAddr; /* keep virtual address of the data */ + bit8 *usrAddr; /* keep virtual address of the user data */ + bit32 len; /* len of buffer */ + void *payload; /* pointer to IOCTL Payload */ + bit8 inProgress; /* if 1 - the IOCTL request is in progress */ + void *param1; + void *param2; + void *param3; +} tdFWControlEx_t; + +/************************************************************/ +//This flag and datastructure are specific for fw profiling, Now defined as +// compiler flag +//#define SPC_ENABLE_PROFILE + +#ifdef SPC_ENABLE_PROFILE +typedef struct tdFWProfile +{ + bit32 status; + bit32 tcid; + bit32 processor; /* processor name "iop/aap1" */ + bit32 cmd; /* cmd to fw */ + bit32 len; /* len of buffer */ + bit32 codeStartAdd; + bit32 codeEndAdd; + bit32 reserved; /* padding required for 64 bit alignment */ + bit8 buffer[1]; /* Start of buffer */ +} tdFWProfile_t; + +/************************************************/ +/**Definations for FW profile*/ +#define FW_PROFILE_PROCESSOR_ID_IOP 0x00 +#define FW_PROFILE_PROCESSOR_ID_AAP1 0x02 +/* definitions for sub operation */ +#define START_TIMER_PROFILE 0x01 +#define START_CODE_PROFILE 0x02 +#define STOP_TIMER_PROFILE 0x81 +#define STOP_CODE_PROFILE 0x82 +/************************************************/ + +typedef struct tdFWProfileEx +{ + tdFWProfile_t *tdFWProfile; + bit8 *buffer; // keep buffer pointer to be freed when the responce comes + bit8 *virtAddr; /* keep virtual address of the data */ + bit8 *usrAddr; /* keep virtual address of the user data */ + bit32 len; /* len of buffer */ + void *payload; /* pointer to IOCTL Payload */ + bit8 inProgress; /* if 1 - the IOCTL request is in progress */ + void *param1; + void *param2; + void *param3; +} tdFWProfileEx_t; +#endif +/************************************************************/ +typedef struct tdVPDControl +{ + bit32 retcode; /* ret code (status) */ + bit32 phase; /* ret code phase */ + bit32 phaseCmplt; /* percent complete for the current update phase */ + bit32 version; /* Hex encoded firmware version number */ + bit32 offset; /* Used for downloading firmware */ + bit32 len; /* len of buffer */ + bit32 size; /* Used in OS VPD and Trace get size operations. */ + bit8 deviceID; /* padding required for 64 bit alignment */ + bit8 reserved1; + bit16 reserved2; + bit32 signature; + bit8 buffer[1]; /* Start of buffer */ +} tdVPDControl_t; + +typedef struct tdDeviceInfoIOCTL_s +{ + bit8 deviceType; // TD_SATA_DEVICE or TD_SAS_DEVICE + bit8 linkRate; // 0x08: 1.5 Gbit/s; 0x09: 3.0; 0x0A: 6.0 Gbit/s. + bit8 phyId; + bit8 reserved; + bit32 sasAddressHi; // SAS address high + bit32 sasAddressLo; // SAS address low + bit32 up_sasAddressHi; // upstream SAS address high + bit32 up_sasAddressLo; // upstream SAS address low + bit32 ishost; + bit32 isEncryption; // is encryption enabled + bit32 isDIF; // is DIF enabled + unsigned long DeviceHandle; + bit32 host_num; + bit32 channel; + bit32 id; + bit32 lun; +}tdDeviceInfoIOCTL_t; + +/* Payload of IOCTL dump device list at OS layer */ +typedef struct tdDeviceInfoPayload_s +{ + bit32 PathId; + bit32 TargetId; + bit32 Lun; + bit32 Reserved; /* Had better aligned to 64-bit. */ + + /* output */ + tdDeviceInfoIOCTL_t devInfo; +}tdDeviceInfoPayload_t; + +typedef struct tdDeviceListPayload_s +{ + bit32 realDeviceCount;// the real device out in the array, returned by driver + bit32 deviceLength; // the length of tdDeviceInfoIOCTL_t array + bit8 pDeviceInfo[1]; // point to tdDeviceInfoIOCTL_t array +}tdDeviceListPayload_t; + +// Payload of IO error and event statistic IOCTL. +typedef struct tdIoErrorEventStatisticIOCTL_s +{ + bit32 agOSSA_IO_COMPLETED_ERROR_SCSI_STATUS; + bit32 agOSSA_IO_ABORTED; + bit32 agOSSA_IO_OVERFLOW; + bit32 agOSSA_IO_UNDERFLOW; + bit32 agOSSA_IO_FAILED; + bit32 agOSSA_IO_ABORT_RESET; + bit32 agOSSA_IO_NOT_VALID; + bit32 agOSSA_IO_NO_DEVICE; + bit32 agOSSA_IO_ILLEGAL_PARAMETER; + bit32 agOSSA_IO_LINK_FAILURE; + bit32 agOSSA_IO_PROG_ERROR; + bit32 agOSSA_IO_DIF_IN_ERROR; + bit32 agOSSA_IO_DIF_OUT_ERROR; + bit32 agOSSA_IO_ERROR_HW_TIMEOUT; + bit32 agOSSA_IO_XFER_ERROR_BREAK; + bit32 agOSSA_IO_XFER_ERROR_PHY_NOT_READY; + bit32 agOSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED; + bit32 agOSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION; + bit32 agOSSA_IO_OPEN_CNX_ERROR_BREAK; + bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS; + bit32 agOSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION; + bit32 agOSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED; + bit32 agOSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY; + bit32 agOSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION; + bit32 agOSSA_IO_OPEN_CNX_ERROR_UNKNOWN_ERROR; + bit32 agOSSA_IO_XFER_ERROR_NAK_RECEIVED; + bit32 agOSSA_IO_XFER_ERROR_ACK_NAK_TIMEOUT; + bit32 agOSSA_IO_XFER_ERROR_PEER_ABORTED; + bit32 agOSSA_IO_XFER_ERROR_RX_FRAME; + bit32 agOSSA_IO_XFER_ERROR_DMA; + bit32 agOSSA_IO_XFER_ERROR_CREDIT_TIMEOUT; + bit32 agOSSA_IO_XFER_ERROR_SATA_LINK_TIMEOUT; + bit32 agOSSA_IO_XFER_ERROR_SATA; + bit32 agOSSA_IO_XFER_ERROR_ABORTED_DUE_TO_SRST; + bit32 agOSSA_IO_XFER_ERROR_REJECTED_NCQ_MODE; + bit32 agOSSA_IO_XFER_ERROR_ABORTED_NCQ_MODE; + bit32 agOSSA_IO_XFER_OPEN_RETRY_TIMEOUT; + bit32 agOSSA_IO_XFER_SMP_RESP_CONNECTION_ERROR; + bit32 agOSSA_IO_XFER_ERROR_UNEXPECTED_PHASE; + bit32 agOSSA_IO_XFER_ERROR_XFER_RDY_OVERRUN; + bit32 agOSSA_IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED; + bit32 agOSSA_IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT; + bit32 agOSSA_IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK; + bit32 agOSSA_IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK; + bit32 agOSSA_IO_XFER_ERROR_OFFSET_MISMATCH; + bit32 agOSSA_IO_XFER_ERROR_XFER_ZERO_DATA_LEN; + bit32 agOSSA_IO_XFER_CMD_FRAME_ISSUED; + bit32 agOSSA_IO_ERROR_INTERNAL_SMP_RESOURCE; + bit32 agOSSA_IO_PORT_IN_RESET; + bit32 agOSSA_IO_DS_NON_OPERATIONAL; + bit32 agOSSA_IO_DS_IN_RECOVERY; + bit32 agOSSA_IO_TM_TAG_NOT_FOUND; + bit32 agOSSA_IO_XFER_PIO_SETUP_ERROR; + bit32 agOSSA_IO_SSP_EXT_IU_ZERO_LEN_ERROR; + bit32 agOSSA_IO_DS_IN_ERROR; + bit32 agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY; + bit32 agOSSA_IO_ABORT_IN_PROGRESS; + bit32 agOSSA_IO_ABORT_DELAYED; + bit32 agOSSA_IO_INVALID_LENGTH; + bit32 agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT; + bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED; + bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO; + bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST; + bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE; + bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED; + bit32 agOSSA_IO_DS_INVALID; + bit32 agOSSA_IO_XFER_READ_COMPL_ERR; + bit32 agOSSA_IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR; + bit32 agOSSA_IO_XFR_ERROR_INTERNAL_CRC_ERROR; + bit32 agOSSA_MPI_IO_RQE_BUSY_FULL; + bit32 agOSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE; + bit32 agOSSA_MPI_ERR_ATAPI_DEVICE_BUSY; + bit32 agOSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS; + bit32 agOSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH; + bit32 agOSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID; + bit32 agOSSA_IO_XFR_ERROR_DEK_IV_MISMATCH; + bit32 agOSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR; + bit32 agOSSA_IO_XFR_ERROR_INTERNAL_RAM; + bit32 agOSSA_IO_XFR_ERROR_DIF_MISMATCH; + bit32 agOSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH; + bit32 agOSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH; + bit32 agOSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH; + bit32 agOSSA_IO_XFR_ERROR_INVALID_SSP_RSP_FRAME; + bit32 agOSSA_IO_XFER_ERR_EOB_DATA_OVERRUN; + bit32 agOSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS; + bit32 agOSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED; + bit32 agOSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE; + bit32 agOSSA_IO_XFER_ERROR_DIF_INTERNAL_ERROR; + bit32 agOSSA_MPI_ERR_OFFLOAD_DIF_OR_ENC_NOT_ENABLED; + bit32 agOSSA_IO_UNKNOWN_ERROR; + +} tdIoErrorEventStatisticIOCTL_t; + +/* +01: soft error +02: not ready +03: medium error +04: hardware error +05: illegal request +06: unit attention +0b: abort command +*/ +typedef struct tdSenseKeyCount_s{ + bit32 SoftError; + bit32 MediumNotReady; + bit32 MediumError; + bit32 HardwareError; + bit32 IllegalRequest; + bit32 UnitAttention; + bit32 AbortCommand; + bit32 OtherKeyType; +}tdSenseKeyCount_t; + +/* +Code Status Command completed Service response +00h GOOD Yes COMMAND COMPLETE +02h CHECK CONDITION Yes COMMAND COMPLETE +04h CONDITION MET Yes COMMAND COMPLETE +08h BUSY Yes COMMAND COMPLETE +10h Obsolete +14h Obsolete +18h RESERVATION CONFLICT Yes COMMAND COMPLETE +22h Obsolete +28h TASK SET FULL Yes COMMAND COMPLETE +30h ACA ACTIVE Yes COMMAND COMPLETE +40h TASK ABORTED Yes COMMAND COMPLETE +*/ +typedef struct tdSCSIStatusCount_s{ + bit32 GoodStatus; + bit32 CheckCondition; + bit32 ConditionMet; + bit32 BusyStatus; + bit32 ResvConflict; + bit32 TaskSetFull; + bit32 AcaActive; + bit32 TaskAborted; + bit32 ObsoleteStatus; +}tdSCSIStatusCount_t; + +/* Payload of Io Error Statistic IOCTL. */ +typedef struct tdIoErrorStatisticPayload_s +{ + bit32 flag; + bit32 Reserved; /* Had better aligned to 64-bit. */ + + /* output */ + tdIoErrorEventStatisticIOCTL_t IoError; + tdSCSIStatusCount_t ScsiStatusCounter; + tdSenseKeyCount_t SenseKeyCounter; +} tdIoErrorStatisticPayload_t; + +/* Payload of Io Error Statistic IOCTL. */ +typedef struct tdIoEventStatisticPayload_s +{ + bit32 flag; + bit32 Reserved; /* Had better aligned to 64-bit. */ + + /* output */ + tdIoErrorEventStatisticIOCTL_t IoEvent; +} tdIoEventStatisticPayload_t; + +/* Payload of Register IOCTL. */ +typedef struct tdRegisterPayload_s +{ + bit32 flag; + bit32 busNum; + bit32 RegAddr; /* Register address */ + bit32 RegValue; /* Register value */ + +} tdRegisterPayload_t; + + +#define FORENSIC_DATA_TYPE_GSM_SPACE 1 +#define FORENSIC_DATA_TYPE_QUEUE 2 +#define FORENSIC_DATA_TYPE_FATAL 3 +#define FORENSIC_DATA_TYPE_NON_FATAL 4 +#define FORENSIC_DATA_TYPE_IB_QUEUE 5 +#define FORENSIC_DATA_TYPE_OB_QUEUE 6 +#define FORENSIC_DATA_TYPE_CHECK_FATAL 0x70 + +#define FORENSIC_Q_TYPE_INBOUND 1 +#define FORENSIC_Q_TYPE_OUTBOUND 2 + +/* get forensic data IOCTL payload */ +typedef struct tdForensicDataPayload_s +{ + bit32 DataType; + union + { + struct + { + bit32 directLen; + bit32 directOffset; + bit32 readLen; + bit8 directData[1]; + } gsmBuffer; + + struct + { + bit16 queueType; + bit16 queueIndex; + bit32 directLen; + bit8 directData[1]; + } queueBuffer; + + struct + { + bit32 directLen; + bit32 directOffset; + bit32 readLen; + bit8 directData[1]; + } dataBuffer; + }; +}tdForensicDataPayload_t; + +typedef struct tdBistPayload_s +{ + bit32 testType; + bit32 testLength; + bit32 testData[29]; +}tdBistPayload_t; + +typedef struct _TSTMTID_CARD_LOCATION_INFO +{ + bit32 CardNo; + bit32 Bus; + bit32 Slot; + bit32 Device; + bit32 Function; + bit32 IOLower; + bit32 IO_Upper; + bit32 VidDid; + bit32 PhyMem; + bit32 Flag; + +} TSTMTID_CARD_LOCATION_INFO; + +typedef struct _TSTMTID_TRACE_BUFFER_INFO +{ + bit32 CardNo; + bit32 TraceCompiled; + bit32 BufferSize; + bit32 CurrentIndex; + bit32 TraceWrap; + bit32 CurrentTraceIndexWrapCount; + bit32 TraceMask; + bit32 Flag; + +} TSTMTID_TRACE_BUFFER_INFO; + +#define FetchBufferSIZE 32 +#define LowFence32Bits 0xFCFD1234 +#define HighFence32Bits 0x5678ABDC + +typedef struct _TSTMTID_TRACE_BUFFER_FETCH +{ + bit32 CardNo; + bit32 BufferOffsetBegin; + bit32 LowFence; + bit8 Data[FetchBufferSIZE]; + bit32 HighFence; + bit32 Flag; + +} TSTMTID_TRACE_BUFFER_FETCH; + + +typedef struct _TSTMTID_TRACE_BUFFER_RESET +{ + bit32 CardNo; + bit32 Reset; + bit32 TraceMask; + bit32 Flag; + +} TSTMTID_TRACE_BUFFER_RESET; + + + +typedef struct tdPhyCount_s{ + bit32 Phy; + bit32 BW_tx; + bit32 BW_rx; + bit32 InvalidDword; + bit32 runningDisparityError; + bit32 codeViolation; + bit32 LossOfSyncDW; + bit32 phyResetProblem; + bit32 inboundCRCError; +}tdPhyCount_t; + + +typedef struct _PHY_GENERAL_STATE +{ + bit32 Dword0; + bit32 Dword1; + +}GetPhyGenState_t; +typedef struct agsaPhyGeneralState_s +{ + GetPhyGenState_t PhyGenData[16]; + bit32 Reserved1; + bit32 Reserved2; +} agsaPhyGeneralState_t; + +typedef struct _PHY_DETAILS_ +{ + bit8 sasAddressLo[4]; + bit8 sasAddressHi[4]; + bit8 attached_sasAddressLo[4]; + bit8 attached_sasAddressHi[4]; + bit8 attached_phy; + bit8 attached_dev_type ; +}PhyDetails_t; + +enum SAS_SATA_DEVICE_TYPE { + SAS_PHY_NO_DEVICE , + SAS_PHY_END_DEVICE, + SAS_PHY_EXPANDER_DEVICE, + SAS_PHY_SATA_DEVICE = 0x11, +}; +#define PHY_SETTINGS_LEN 1024 + +#endif /* TD_IOCTL_H */ diff --git a/sys/dev/pms/RefTisa/tisa/sassata/common/tdlist.h b/sys/dev/pms/RefTisa/tisa/sassata/common/tdlist.h new file mode 100644 index 000000000000..e304dcfeb239 --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/common/tdlist.h @@ -0,0 +1,168 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/*******************************************************************************/ +/** \file + * + * The file defines list data structures for SAS/SATA TD layer + * + */ + +#ifndef __TDLIST_H__ +#define __TDLIST_H__ + + +typedef struct tdList_s tdList_t; + +struct tdList_s { + tdList_t *flink; + tdList_t *blink; +}; + +#define TDLIST_NEXT_ENTRY(ptr, type, member) \ + container_of((ptr)->flink, type, member) + +#define TDLIST_INIT_HDR(hdr) \ + do { \ + ((tdList_t *)(hdr))->flink = (tdList_t *)(hdr); \ + ((tdList_t *)(hdr))->blink = (tdList_t *)(hdr); \ + } while (0) + +#define TDLIST_INIT_ELEMENT(hdr) \ + do { \ + ((tdList_t *)(hdr))->flink = (tdList_t *)agNULL; \ + ((tdList_t *)(hdr))->blink = (tdList_t *)agNULL; \ + } while (0) + +#define TDLIST_ENQUEUE_AT_HEAD(toAddHdr,listHdr) \ + do { \ + ((tdList_t *)(toAddHdr))->flink = ((tdList_t *)(listHdr))->flink; \ + ((tdList_t *)(toAddHdr))->blink = (tdList_t *)(listHdr) ; \ + ((tdList_t *)(listHdr))->flink->blink = (tdList_t *)(toAddHdr); \ + ((tdList_t *)(listHdr))->flink = (tdList_t *)(toAddHdr); \ + } while (0) + +#define TDLIST_ENQUEUE_AT_TAIL(toAddHdr,listHdr) \ + do { \ + ((tdList_t *)(toAddHdr))->flink = (tdList_t *)(listHdr); \ + ((tdList_t *)(toAddHdr))->blink = ((tdList_t *)(listHdr))->blink; \ + ((tdList_t *)(listHdr))->blink->flink = (tdList_t *)(toAddHdr); \ + ((tdList_t *)(listHdr))->blink = (tdList_t *)(toAddHdr); \ + } while (0) + +#define TDLIST_EMPTY(listHdr) \ + (((tdList_t *)(listHdr))->flink == ((tdList_t *)(listHdr))) + +#define TDLIST_NOT_EMPTY(listHdr) \ + (!TDLIST_EMPTY(listHdr)) + +#define TDLIST_DEQUEUE_THIS(hdr) \ + do { \ + ((tdList_t *)(hdr))->blink->flink = ((tdList_t *)(hdr))->flink; \ + ((tdList_t *)(hdr))->flink->blink = ((tdList_t *)(hdr))->blink; \ + ((tdList_t *)(hdr))->flink = ((tdList_t *)(hdr))->blink = agNULL; \ + } while (0) + +#define TDLIST_DEQUEUE_FROM_HEAD_FAST(atHeadHdr,listHdr) \ + do { \ + *((tdList_t **)(atHeadHdr)) = ((tdList_t *)(listHdr))->flink; \ + (*((tdList_t **)(atHeadHdr)))->flink->blink = (tdList_t *)(listHdr); \ + ((tdList_t *)(listHdr))->flink = (*(tdList_t **)(atHeadHdr))->flink; \ + } while (0) + +#define TDLIST_DEQUEUE_FROM_HEAD(atHeadHdr,listHdr) \ +do { \ + if (TDLIST_NOT_EMPTY((listHdr))) \ + { \ + TDLIST_DEQUEUE_FROM_HEAD_FAST(atHeadHdr,listHdr); \ + } \ + else \ + { \ + (*((tdList_t **)(atHeadHdr))) = (tdList_t *)agNULL; \ + } \ +} while (0) + +#define TDLIST_DEQUEUE_FROM_TAIL_FAST(atTailHdr,listHdr) \ + do { \ + (*((tdList_t **)(atTailHdr))) = ((tdList_t *)(listHdr))->blink; \ + (*((tdList_t **)(atTailHdr)))->blink->flink = (tdList_t *)(listHdr); \ + ((tdList_t *)(listHdr))->blink = (*((tdList_t **)(atTailHdr)))->blink; \ + } while (0) + +#define TDLIST_DEQUEUE_FROM_TAIL(atTailHdr,listHdr) \ + do { \ + if (TDLIST_NOT_EMPTY((listHdr))) \ + { \ + TDLIST_DEQUEUE_FROM_TAIL_FAST(atTailHdr,listHdr); \ + } \ + else \ + { \ + (*((tdList_t **)(atTailHdr))) = (tdList_t *)agNULL; \ + } \ + } while (0) + +#define TDLIST_ENQUEUE_LIST_AT_TAIL_FAST(toAddListHdr, listHdr) \ + do { \ + ((tdList_t *)toAddListHdr)->blink->flink = ((tdList_t *)listHdr); \ + ((tdList_t *)toAddListHdr)->flink->blink = ((tdList_t *)listHdr)->blink; \ + ((tdList_t *)listHdr)->blink->flink = ((tdList_t *)toAddListHdr)->flink; \ + ((tdList_t *)listHdr)->blink = ((tdList_t *)toAddListHdr)->blink; \ + TDLIST_INIT_HDR(toAddListHdr); \ + } while (0) + +#define TDLIST_ENQUEUE_LIST_AT_TAIL(toAddListHdr, listHdr) \ + do { \ + if (TDLIST_NOT_EMPTY(toAddListHdr)) \ + { \ + TDLIST_ENQUEUE_LIST_AT_TAIL_FAST(toAddListHdr, listHdr); \ + } \ + } while (0) + +#define TDLIST_ENQUEUE_LIST_AT_HEAD_FAST(toAddListHdr, listHdr) \ + do { \ + ((tdList_t *)toAddListHdr)->blink->flink = ((tdList_t *)listHdr)->flink; \ + ((tdList_t *)toAddListHdr)->flink->blink = ((tdList_t *)listHdr); \ + ((tdList_t *)listHdr)->flink->blink = ((tdList_t *)toAddListHdr)->blink; \ + ((tdList_t *)listHdr)->flink = ((tdList_t *)toAddListHdr)->flink; \ + TDLIST_INIT_HDR(toAddListHdr); \ + } while (0) + +#define TDLIST_ENQUEUE_LIST_AT_HEAD(toAddListHdr, listHdr) \ + do { \ + if (TDLIST_NOT_EMPTY(toAddListHdr)) \ + { \ + TDLIST_ENQUEUE_LIST_AT_HEAD_FAST(toAddListHdr, listHdr); \ + } \ + } while (0) + +#define TD_FIELD_OFFSET(baseType,fieldName) \ + ((bit32)((bitptr)(&(((baseType *)0)->fieldName)))) + +#define TDLIST_OBJECT_BASE(baseType,fieldName,fieldPtr) \ + (void *)fieldPtr == (void *)0 ? (baseType *)0 : \ + ((baseType *)((bit8 *)(fieldPtr) - ((bitptr)(&(((baseType *)0)->fieldName))))) + + + +#endif /* __TDLIST_H__ */ + diff --git a/sys/dev/pms/RefTisa/tisa/sassata/common/tdmisc.c b/sys/dev/pms/RefTisa/tisa/sassata/common/tdmisc.c new file mode 100644 index 000000000000..302a1163758a --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/common/tdmisc.c @@ -0,0 +1,2901 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +/*******************************************************************************/ +/** \file + * + * + * This file contains TB misc. functions + * + */ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#ifdef FDS_SM +#include +#include +#include +#endif + +#ifdef FDS_DM +#include +#include +#include +#endif + +#include +#include +#include + +#ifdef INITIATOR_DRIVER +#include +#include +#include +#endif + +#ifdef TARGET_DRIVER +#include +#include +#include +#endif + +#include +#include + +/***************************************************************************** +*! \brief tiINIIOAbort +* +* Purpose: This function is called to abort an I/O request previously started +* by a call to tiINIIOStart() or tiINIIOStartDif() . +* +* \param tiRoot: Pointer to initiator driver/port instance. +* \param taskTag: Pointer to the associated task to be aborted +* +* \return: +* +* tiSuccess: I/O request successfully initiated. +* tiBusy: No resources available, try again later. +* tiIONoDevice: Invalid device handle. +* tiError: Other errors that prevent the I/O request to be +* started. +* +*****************************************************************************/ +#ifdef INITIATOR_DRIVER /*TBD: INITIATOR SPECIFIC API in tiapi.h (TP)*/ +osGLOBAL bit32 +tiINIIOAbort( + tiRoot_t *tiRoot, + tiIORequest_t *taskTag + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + agsaRoot_t *agRoot = agNULL; + tdIORequestBody_t *tdIORequestBody = agNULL; + agsaIORequest_t *agIORequest = agNULL; + bit32 sasStatus = AGSA_RC_FAILURE; + tdsaDeviceData_t *oneDeviceData; + bit32 status= tiError; + agsaIORequest_t *agAbortIORequest; + tdIORequestBody_t *tdAbortIORequestBody; + bit32 PhysUpper32; + bit32 PhysLower32; + bit32 memAllocStatus; + void *osMemHandle; + agsaDevHandle_t *agDevHandle = agNULL; +#ifdef FDS_SM + smRoot_t *smRoot; + tdIORequestBody_t *ToBeAbortedtdIORequestBody; + smIORequest_t *ToBeAborted = agNULL; +#endif + TI_DBG2(("tiINIIOAbort: start\n")); + + if(taskTag == agNULL) + { + TI_DBG1(("tiINIIOAbort: taskTag is NULL\n")); + return tiError; + } + + agRoot = &(tdsaAllShared->agRootNonInt); + tdIORequestBody = (tdIORequestBody_t *)taskTag->tdData; + agIORequest = &(tdIORequestBody->agIORequest); + oneDeviceData = tdIORequestBody->tiDevHandle->tdData; + + if(oneDeviceData == agNULL) + { + TI_DBG1(("tiINIIOAbort: DeviceData is NULL\n")); + return tiSuccess; + } + + agDevHandle = oneDeviceData->agDevHandle; + + TI_DBG2(("tiINIIOAbort: did %d\n", oneDeviceData->id)); + + /* for hotplug */ + if (oneDeviceData->valid != agTRUE || oneDeviceData->registered != agTRUE || + oneDeviceData->tdPortContext == agNULL ) + { + TI_DBG1(("tiINIIOAbort: NO Device did %d\n", oneDeviceData->id )); + TI_DBG1(("tiINIIOAbort: device AddrHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG1(("tiINIIOAbort: device AddrLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + return tiError; + } + + /* allocating agIORequest for abort itself */ + memAllocStatus = ostiAllocMemory( + tiRoot, + &osMemHandle, + (void **)&tdAbortIORequestBody, + &PhysUpper32, + &PhysLower32, + 8, + sizeof(tdIORequestBody_t), + agTRUE + ); + if (memAllocStatus != tiSuccess) + { + /* let os process IO */ + TI_DBG1(("tiINIIOAbort: ostiAllocMemory failed...\n")); + return tiError; + } + + if (tdAbortIORequestBody == agNULL) + { + /* let os process IO */ + TI_DBG1(("tiINIIOAbort: ostiAllocMemory returned NULL tdAbortIORequestBody\n")); + return tiError; + } + + /* setup task management structure */ + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle = osMemHandle; + /* setting callback */ + tdAbortIORequestBody->IOCompletionFunc = itdssIOAbortedHandler; + tdAbortIORequestBody->tiDevHandle = tdIORequestBody->tiDevHandle; + + /* initialize agIORequest */ + agAbortIORequest = &(tdAbortIORequestBody->agIORequest); + agAbortIORequest->osData = (void *) tdAbortIORequestBody; + agAbortIORequest->sdkData = agNULL; /* LL takes care of this */ + + /* remember IO to be aborted */ + tdAbortIORequestBody->tiIOToBeAbortedRequest = taskTag; + + if (oneDeviceData->DeviceType == TD_SAS_DEVICE) + { + sasStatus = saSSPAbort(agRoot, + agAbortIORequest, + tdsaRotateQnumber(tiRoot, oneDeviceData), + agDevHandle, + 0/* flag */, + agIORequest, + agNULL); + + if (sasStatus == AGSA_RC_SUCCESS) + { + return tiSuccess; + } + else + { + return tiError; + } + } + + else if (oneDeviceData->DeviceType == TD_SATA_DEVICE) + { + TI_DBG2(("tiINIIOAbort: calling satIOAbort() oneDeviceData=%p\n", oneDeviceData)); +#ifdef FDS_SM + smRoot = &(tdsaAllShared->smRoot); + if ( taskTag != agNULL) + { + ToBeAbortedtdIORequestBody = (tdIORequestBody_t *)taskTag->tdData; + ToBeAborted = &(ToBeAbortedtdIORequestBody->smIORequest); + status = smIOAbort(smRoot, ToBeAborted); + return status; + } + else + { + TI_DBG1(("tiINIIOAbort: taskTag is NULL!!!\n")); + return tiError; + } + +#else + +#ifdef SATA_ENABLE + status = satIOAbort(tiRoot, taskTag ); +#endif + + return status; +#endif /* else FDS_SM */ + } + + else + { + return tiError; + } + +} + +osGLOBAL bit32 +tiINIIOAbortAll( + tiRoot_t *tiRoot, + tiDeviceHandle_t *tiDeviceHandle + ) +{ + agsaRoot_t *agRoot = agNULL; + tdsaDeviceData_t *oneDeviceData = agNULL; + bit32 status = tiError; +#ifdef FDS_SM + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + smRoot_t *smRoot = &(tdsaAllShared->smRoot); + smDeviceHandle_t *smDeviceHandle; +#endif + + TI_DBG1(("tiINIIOAbortAll: start\n")); + + if (tiDeviceHandle == agNULL) + { + TI_DBG1(("tiINIIOAbortAll: tiDeviceHandle is NULL!!!\n")); + return tiError; + } + + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + + if (oneDeviceData == agNULL) + { + TI_DBG1(("tiINIIOAbortAll: oneDeviceData is NULL!!!\n")); + return tiError; + } + + /* for hotplug */ + if (oneDeviceData->valid != agTRUE || oneDeviceData->registered != agTRUE || + oneDeviceData->tdPortContext == agNULL ) + { + TI_DBG1(("tiINIIOAbortAll: NO Device did %d\n", oneDeviceData->id )); + TI_DBG1(("tiINIIOAbortAll: device AddrHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG1(("tiINIIOAbortAll: device AddrLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + return tiError; + } + + agRoot = oneDeviceData->agRoot; + + if (agRoot == agNULL) + { + TI_DBG1(("tiINIIOAbortAll: agRoot is NULL!!!\n")); + return tiError; + } + + /* this is processed in ossaSSPAbortCB, ossaSATAAbortCB, ossaSMPAbortCB */ + if (oneDeviceData->OSAbortAll == agTRUE) + { + TI_DBG1(("tiINIIOAbortAll: already pending!!!\n")); + return tiBusy; + } + else + { + oneDeviceData->OSAbortAll = agTRUE; + } + +#ifdef FDS_SM + if ( DEVICE_IS_SSP_TARGET(oneDeviceData) || DEVICE_IS_SMP_TARGET(oneDeviceData)) + { + status = tdsaAbortAll(tiRoot, agRoot, oneDeviceData); + } + else if (DEVICE_IS_SATA_DEVICE(oneDeviceData) || + DEVICE_IS_STP_TARGET(oneDeviceData) + ) + { + TI_DBG2(("tiINIIOAbortAll: calling smIOAbortAll\n")); + smDeviceHandle = (smDeviceHandle_t *)&(oneDeviceData->smDeviceHandle); + smDeviceHandle->tdData = oneDeviceData; + status = smIOAbortAll(smRoot, smDeviceHandle); + } + else + { + TI_DBG1(("tiINIIOAbortAll: unknow device type!!! 0x%x\n", oneDeviceData->target_ssp_stp_smp)); + status = AGSA_RC_FAILURE; + } +#else + status = tdsaAbortAll(tiRoot, agRoot, oneDeviceData); +#endif + + return status; + +} +#endif /* INITIATOR_DRIVER */ + +/***************************************************************************** +*! \brief tdsaAbortAll +* +* Purpose: This function is called to abort an all pending I/O request on a +* device +* +* \param tiRoot: Pointer to initiator driver/port instance. +* \param agRoot: Pointer to chip/driver Instance. +* \param oneDeviceData: Pointer to the device +* +* \return: +* +* None +* +*****************************************************************************/ +osGLOBAL bit32 +tdsaAbortAll( + tiRoot_t *tiRoot, + agsaRoot_t *agRoot, + tdsaDeviceData_t *oneDeviceData + ) +{ + agsaIORequest_t *agAbortIORequest = agNULL; + tdIORequestBody_t *tdAbortIORequestBody = agNULL; + bit32 PhysUpper32; + bit32 PhysLower32; + bit32 memAllocStatus; + void *osMemHandle; + bit32 status = AGSA_RC_FAILURE; + + TI_DBG1(("tdsaAbortAll: did %d\n", oneDeviceData->id)); + + /* allocating agIORequest for abort itself */ + memAllocStatus = ostiAllocMemory( + tiRoot, + &osMemHandle, + (void **)&tdAbortIORequestBody, + &PhysUpper32, + &PhysLower32, + 8, + sizeof(tdIORequestBody_t), + agTRUE + ); + if (memAllocStatus != tiSuccess) + { + /* let os process IO */ + TI_DBG1(("tdsaAbortAll: ostiAllocMemory failed...\n")); + return tiError; + } + + if (tdAbortIORequestBody == agNULL) + { + /* let os process IO */ + TI_DBG1(("tdsaAbortAll: ostiAllocMemory returned NULL tdAbortIORequestBody\n")); + return tiError; + } + + /* setup task management structure */ + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle = osMemHandle; + /* setting callback but not used later */ + tdAbortIORequestBody->IOCompletionFunc = agNULL; + //tdAbortIORequestBody->IOCompletionFunc = itdssIOAbortedHandler; + + tdAbortIORequestBody->tiDevHandle = (tiDeviceHandle_t *)&(oneDeviceData->tiDeviceHandle); + + /* initialize agIORequest */ + agAbortIORequest = &(tdAbortIORequestBody->agIORequest); + agAbortIORequest->osData = (void *) tdAbortIORequestBody; + agAbortIORequest->sdkData = agNULL; /* LL takes care of this */ + + if ( DEVICE_IS_SSP_TARGET(oneDeviceData)) + { + /* SSPAbort */ + status = saSSPAbort(agRoot, + agAbortIORequest, + tdsaRotateQnumber(tiRoot, oneDeviceData), //0, + oneDeviceData->agDevHandle, + 1, /* abort all */ + agNULL, + agNULL + ); + } + else if (DEVICE_IS_SATA_DEVICE(oneDeviceData) || + DEVICE_IS_STP_TARGET(oneDeviceData) + ) + { + /* SATAAbort*/ + if (oneDeviceData->satDevData.IDDeviceValid == agFALSE) + { + TI_DBG2(("tdsaAbortAll: saSATAAbort\n")); + status = saSATAAbort(agRoot, + agAbortIORequest, + 0, + oneDeviceData->agDevHandle, + 1, /* abort all */ + agNULL, + agNULL + ); + } + else + { + TI_DBG2(("tdsaAbortAll: saSATAAbort IDDeviceValid\n")); + status = saSATAAbort(agRoot, + agAbortIORequest, + tdsaRotateQnumber(tiRoot, oneDeviceData), //0, + oneDeviceData->agDevHandle, + 1, /* abort all */ + agNULL, + agNULL + ); + } + } + else if (DEVICE_IS_SMP_TARGET(oneDeviceData)) + { + /* SMPAbort*/ + TI_DBG2(("tdsaAbortAll: saSMPAbort \n")); + status = saSMPAbort(agRoot, + agAbortIORequest, + tdsaRotateQnumber(tiRoot, oneDeviceData), //0, + oneDeviceData->agDevHandle, + 1, /* abort all */ + agNULL, + agNULL + ); + } + else + { + TI_DBG1(("tdsaAbortAll: unknown device type!!! 0x%x\n", oneDeviceData->target_ssp_stp_smp)); + status = AGSA_RC_FAILURE; + } + + if (status == AGSA_RC_SUCCESS) + { + return tiSuccess; + } + else + { + TI_DBG1(("tdsaAbortAll: failed status=%d\n", status)); + //failed to send abort command, we need to free the memory + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + return tiError; + } + +} + + + +/***************************************************************************** +*! \brief tiCOMReset +* +* Purpose: This function is called to trigger soft or hard reset +* +* \param tiRoot: Pointer to initiator driver/port instance. +* \param option: Options +* +* \return: +* +* None +* +*****************************************************************************/ +osGLOBAL void +tiCOMReset( + tiRoot_t *tiRoot, + bit32 option + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + agsaRoot_t *agRoot = agNULL; + + +#ifdef TI_GETFOR_ONRESET + agsaControllerStatus_t controllerStatus; + agsaForensicData_t forensicData; + bit32 once = 1; + bit32 status; +#endif /* TI_GETFOR_ONRESET */ + + TI_DBG1(("tiCOMReset: start option 0x%x\n",option)); + tdsaAllShared->resetCount++; + TI_DBG2(("tiCOMReset: reset count %d\n", tdsaAllShared->resetCount)); + + agRoot = &(tdsaAllShared->agRootNonInt); + + if (tdsaAllShared->flags.resetInProgress == agTRUE) + { + TI_DBG1(("tiCOMReset : Reset is already in progress : \n")); + + /* don't do anything : just return */ + return; + } + + tdsaAllShared->flags.resetInProgress = agTRUE; + +#ifdef TI_GETFOR_ONRESET + saGetControllerStatus(agRoot, &controllerStatus); + if(controllerStatus.fatalErrorInfo.errorInfo1) + { + + bit8 * DirectData = (bit8 * )tdsaAllShared->FatalErrorData; + forensicData.DataType = TYPE_FATAL; + forensicData.dataBuf.directLen = (8 * 1024); + forensicData.dataBuf.directOffset = 0; /* current offset */ + forensicData.dataBuf.readLen = 0; /* Data read */ + getmoreData: + forensicData.dataBuf.directData = DirectData; + status = saGetForensicData( agRoot, agNULL, &forensicData); + TI_DBG1(("tiCOMReset:status %d readLen 0x%x directLen 0x%x directOffset 0x%x\n", + status, + forensicData.dataBuf.readLen, + forensicData.dataBuf.directLen, + forensicData.dataBuf.directOffset)); + + if( forensicData.dataBuf.readLen == forensicData.dataBuf.directLen && !status && once) + { + DirectData += forensicData.dataBuf.readLen; + goto getmoreData; + } + TI_DBG1(("tiCOMReset:saGetForensicData type %d read 0x%x bytes\n", forensicData.DataType, forensicData.dataBuf.directOffset )); + } + +#endif /* TI_GETFOR_ONRESET */ + if (option == tiSoftReset) + { + /* soft reset */ + TI_DBG6(("tiCOMReset: soft reset\n")); + saHwReset(agRoot, AGSA_SOFT_RESET, 0); + return; + } + else + { + saHwReset(agRoot, AGSA_SOFT_RESET, 0); +#ifdef NOT_YET + /* hard reset */ + saHwReset(agRoot, AGSA_CHIP_RESET, 0); +#endif + } + return; +} + + +/*****************************************************************************/ +/*! \biref tiINIReportErrorToEventLog + * + * Purpose: This function is called to report errors that needs to be logged + * into event log. + * + * \param tiRoot: Pointer to initiator specific root data structure for this + * instance of the driver. + * \param agEventData: Event data structure. + * + * \return None. + * + */ +/*****************************************************************************/ +#ifdef INITIATOR_DRIVER +osGLOBAL bit32 +tiINIReportErrorToEventLog( + tiRoot_t *tiRoot, + tiEVTData_t *agEventData + ) +{ + TI_DBG6(("tiINIReportErrorToEventLog: start\n")); + return tiError; +} +#endif /* INITIATOR_DRIVER */ + +/*****************************************************************************/ +/*! \brief ossaReenableInterrupts + * + * + * Purpose: This routine is called to enable interrupt + * + * + * \param agRoot: Pointer to chip/driver Instance. + * \param outboundChannelNum: Zero-base channel number + * + * + * \return None. + * + * \note - The scope is shared target and initiator. + * + */ +/*****************************************************************************/ +#ifndef ossaReenableInterrupts +osGLOBAL void +ossaReenableInterrupts( + agsaRoot_t *agRoot, + bit32 outboundChannelNum + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *) (agRoot->osData); + + ostiInterruptEnable( + osData->tiRoot, + outboundChannelNum + ); + return; +} + +#endif + + + + +/* +1. initiator + send task management + call saSSPAbort() + +2. Target + call saSSPAbort() + +*/ + +/***************************************************************************** +*! \brief tiINITaskManagement +* +* Purpose: This routine is called to explicitly ask the Transport Dependent +* Layer to issue a Task Management command to a device. +* +* \param tiRoot: Pointer to driver instance +* \param tiDeviveHandle: Pointer to the device handle for this session. +* \param task: SAM-2 task management request. +* \param lun: Pointer to the SCSI-3 LUN information +* when applicable. Set to zero when not applicable. +* \param taskTag: Pointer to the associated task where the task +* management command is to be applied. Set to agNULL +* if not applicable for the specific Task Management +* task. +* \param currentTaskTag: The current context or task tag for this task. This +* task tag will be passed back in ostiInitiatorEvent() +* when this task management is completed. +* +* \return: +* tiSuccess TM request successfully initiated. +* tiBusy No resources available, try again later. +* tiIONoDevice Invalid device handle. +* tiError Other errors that prevent the TM request to be started. +* +*****************************************************************************/ +/* + warm reset->smp phy control(hard reset) or saLocalPhyControl(AGSA_PHY_HARD_RESET) + +*/ +#ifdef INITIATOR_DRIVER +osGLOBAL bit32 +tiINITaskManagement ( + tiRoot_t *tiRoot, + tiDeviceHandle_t *tiDeviceHandle, + bit32 task, + tiLUN_t *lun, + tiIORequest_t *taskTag, /* being aborted one */ + tiIORequest_t *currentTaskTag /* task management itself */ + ) +{ + + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + itdsaIni_t *Initiator = (itdsaIni_t *)tdsaAllShared->itdsaIni; + agsaRoot_t *agRoot = agNULL; + bit32 tiStatus = tiError; + bit32 notImplemented = agFALSE; + tdsaDeviceData_t *oneDeviceData = agNULL; + void *osMemHandle; + tdIORequestBody_t *TMtdIORequestBody; + bit32 PhysUpper32; + bit32 PhysLower32; + bit32 memAllocStatus; + bit32 agRequestType; + agsaIORequest_t *agIORequest = agNULL; /* task management itself */ + agsaIORequest_t *agTMRequest = agNULL; /* IO being task managed */ + agsaDevHandle_t *agDevHandle = agNULL; + agsaSASRequestBody_t *agSASRequestBody = agNULL; + agsaSSPScsiTaskMgntReq_t *agSSPTaskMgntRequest; + bit32 saStatus; + tdIORequestBody_t *tdIORequestBody; +#ifdef FDS_SM + smRoot_t *smRoot; + smDeviceHandle_t *smDeviceHandle; + smIORequest_t *ToBeAborted = agNULL; + smIORequest_t *TaskManagement; + tdIORequestBody_t *ToBeAbortedtdIORequestBody; + tdIORequestBody_t *SMTMtdIORequestBody; + void *SMosMemHandle; + bit32 SMPhysUpper32; + bit32 SMPhysLower32; + bit32 SMmemAllocStatus; +#endif + + TI_DBG2(("tiINITaskManagement: start\n")); + + /* just for testing only */ +#ifdef REMOVED +//start temp + if(tiDeviceHandle == agNULL) + { + TI_DBG1(("tiINITaskManagement: tiDeviceHandle is NULL\n")); + return tiError; + } + + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + if(oneDeviceData == agNULL) + { + TI_DBG1(("tiINITaskManagement: tiDeviceHandle=%p DeviceData is NULL\n", tiDeviceHandle)); + return tiError; + } + TI_DBG1(("tiINITaskManagement: did %d\n", oneDeviceData->id )); + return tiError; +//end temp + +// just for testing + if (task == AG_LOGICAL_UNIT_RESET) + { + TI_DBG1(("tiINITaskManagement: failing LUN RESET for testing\n")); + return tiError; + } + +#endif + + switch(task) + { + case AG_ABORT_TASK: + TI_DBG6(("tiINITaskManagement: ABORT_TASK\n")); + break; + case AG_ABORT_TASK_SET: + TI_DBG6(("tiINITaskManagement: ABORT_TASK_SET\n")); + break; + case AG_CLEAR_ACA: + TI_DBG6(("tiINITaskManagement: CLEAR_ACA\n")); + break; + case AG_CLEAR_TASK_SET: + TI_DBG6(("tiINITaskManagement: CLEAR_TASK_SET\n")); + break; + case AG_LOGICAL_UNIT_RESET: + TI_DBG6(("tiINITaskManagement: LOGICAL_UNIT_RESET\n")); + break; + case AG_TARGET_WARM_RESET: + TI_DBG6(("tiINITaskManagement: TARGET_WARM_RESET\n")); + break; + case AG_QUERY_TASK: + TI_DBG6(("tiINITaskManagement: QUERY_TASK\n")); + break; + default: + TI_DBG1(("tiINITaskManagement: notImplemented 0x%0x !!!\n",task)); + notImplemented = agTRUE; + break; + } + + if (notImplemented) + { + TI_DBG1(("tiINITaskManagement: not implemented 0x%0x !!!\n",task)); + return tiStatus; + } + + if(tiDeviceHandle == agNULL) + { + TI_DBG1(("tiINITaskManagement: tiDeviceHandle is NULL\n")); + return tiError; + } + + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + if(oneDeviceData == agNULL) + { + TI_DBG1(("tiINITaskManagement: tiDeviceHandle=%p DeviceData is NULL\n", tiDeviceHandle)); + return tiIONoDevice; + } + + /* for hotplug */ + if (oneDeviceData->valid != agTRUE || oneDeviceData->registered != agTRUE || + oneDeviceData->tdPortContext == agNULL ) + { + TI_DBG1(("tiINITaskManagement: NO Device did %d Addr 0x%08x:0x%08x\n", oneDeviceData->id , oneDeviceData->SASAddressID.sasAddressHi, oneDeviceData->SASAddressID.sasAddressLo)); + return tiIONoDevice; + } + + /* 1. call tiINIOAbort() + 2. call tdssTaskXmit() + */ + + if (oneDeviceData->DeviceType == TD_SAS_DEVICE) + { + agRoot = oneDeviceData->agRoot; + agDevHandle = oneDeviceData->agDevHandle; + TI_DBG1(("tiINITaskManagement: SAS Device\n")); + + /* + WARM_RESET is experimental code. + Needs more testing and debugging + */ + if (task == AG_TARGET_WARM_RESET) + { + agsaContext_t *agContext; + tdsaDeviceData_t *tdsaDeviceData; + + tdsaDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + currentTaskTag->tdData = tdsaDeviceData; + agContext = &(tdsaDeviceData->agDeviceResetContext); + agContext->osData = currentTaskTag; + + TI_DBG2(("tiINITaskManagement: did %d device reset for SAS\n", oneDeviceData->id)); + saSetDeviceState(agRoot, agNULL, tdsaRotateQnumber(tiRoot, oneDeviceData), agDevHandle, SA_DS_IN_RECOVERY); + + /* warm reset by saLocalPhyControl or SMP PHY control */ + if (oneDeviceData->directlyAttached == agTRUE) + { + TI_DBG2(("tiINITaskManagement: device reset directly attached\n")); + saLocalPhyControl(agRoot, + agContext, + tdsaRotateQnumber(tiRoot, oneDeviceData), + oneDeviceData->phyID, + AGSA_PHY_HARD_RESET, + agNULL + ); + return tiSuccess; + } + else + { + TI_DBG2(("tiINITaskManagement: device reset expander attached\n")); + saStatus = tdsaPhyControlSend(tiRoot, + oneDeviceData, + SMP_PHY_CONTROL_HARD_RESET, + currentTaskTag, + tdsaRotateQnumber(tiRoot, oneDeviceData) + ); + return saStatus; + } + } + else + { + /* task management */ + TI_DBG6(("tiINITaskManagement: making task management frame \n")); + /* 1. create task management frame + 2. sends it using "saSSPStart()" + */ + /* Allocate memory for task management */ + memAllocStatus = ostiAllocMemory( + tiRoot, + &osMemHandle, + (void **)&TMtdIORequestBody, + &PhysUpper32, + &PhysLower32, + 8, + sizeof(tdIORequestBody_t), + agTRUE + ); + + if (memAllocStatus != tiSuccess) + { + TI_DBG1(("tiINITaskManagement: ostiAllocMemory failed...\n")); + return tiError; + } + + if (TMtdIORequestBody == agNULL) + { + TI_DBG1(("tiINITaskManagement: ostiAllocMemory returned NULL TMIORequestBody\n")); + return tiError; + } + + /* initialize */ + osti_memset(TMtdIORequestBody, 0, sizeof(tdIORequestBody_t)); + + /* setup task management structure */ + TMtdIORequestBody->IOType.InitiatorTMIO.osMemHandle = osMemHandle; + TMtdIORequestBody->IOType.InitiatorTMIO.CurrentTaskTag = currentTaskTag; + TMtdIORequestBody->IOType.InitiatorTMIO.TaskTag = taskTag; + + /* let's initialize tdIOrequestBody */ + /* initialize jump table */ + + /* direct callback for task management */ + TMtdIORequestBody->IOCompletionFunc = itdssTaskCompleted; + /* to be removed */ + /* TMtdIORequestBody->IOCompletionFunc = itdssIOCompleted; */ + + /* initialize tiDevhandle */ + TMtdIORequestBody->tiDevHandle = tiDeviceHandle; + + /* initialize tiIORequest */ + TMtdIORequestBody->tiIORequest = currentTaskTag; + /* save context if we need to abort later */ + currentTaskTag->tdData = TMtdIORequestBody; + + /* initialize agIORequest */ + agIORequest = &(TMtdIORequestBody->agIORequest); + agIORequest->osData = (void *) TMtdIORequestBody; + agIORequest->sdkData = agNULL; /* SA takes care of this */ + + /* request type */ + agRequestType = AGSA_SSP_TASK_MGNT_REQ; + TMtdIORequestBody->agRequestType = AGSA_SSP_TASK_MGNT_REQ; + /* + initialize + tdIORequestBody_t tdIORequestBody -> agSASRequestBody + */ + agSASRequestBody = &(TMtdIORequestBody->transport.SAS.agSASRequestBody); + agSSPTaskMgntRequest = &(agSASRequestBody->sspTaskMgntReq); + + TI_DBG2(("tiINITaskManagement: did %d LUN reset for SAS\n", oneDeviceData->id)); + /* fill up LUN field */ + if (lun == agNULL) + { + osti_memset(agSSPTaskMgntRequest->lun, 0, 8); + } + else + { + osti_memcpy(agSSPTaskMgntRequest->lun, lun->lun, 8); + } + + /* default: unconditionally set device state to SA_DS_IN_RECOVERY + bit1 (DS) bit0 (ADS) + bit1: 1 bit0: 0 + */ + agSSPTaskMgntRequest->tmOption = 2; + + /* sets taskMgntFunction field */ + switch(task) + { + case AG_ABORT_TASK: + agSSPTaskMgntRequest->taskMgntFunction = AGSA_ABORT_TASK; + /* For abort task management, unconditionally set device state to SA_DS_IN_RECOVERY + and if can't find, set device state to SA_DS_IN_RECOVERY + bit1 (DS) bit0 (ADS) + bit1: 1; bit0: 1 + */ + agSSPTaskMgntRequest->tmOption = 3; + break; + case AG_ABORT_TASK_SET: + agSSPTaskMgntRequest->taskMgntFunction = AGSA_ABORT_TASK_SET; + break; + case AG_CLEAR_ACA: + agSSPTaskMgntRequest->taskMgntFunction = AGSA_CLEAR_ACA; + break; + case AG_CLEAR_TASK_SET: + agSSPTaskMgntRequest->taskMgntFunction = AGSA_CLEAR_TASK_SET; + break; + case AG_LOGICAL_UNIT_RESET: + agSSPTaskMgntRequest->taskMgntFunction = AGSA_LOGICAL_UNIT_RESET; + break; + case AG_QUERY_TASK: + agSSPTaskMgntRequest->taskMgntFunction = AGSA_QUERY_TASK; + break; + default: + TI_DBG1(("tiINITaskManagement: notImplemented task\n")); + break; + } + + if (task == AGSA_ABORT_TASK || task == AGSA_QUERY_TASK) + { + /* set agTMRequest, which is IO being task managed */ + tdIORequestBody = (tdIORequestBody_t *)taskTag->tdData; + if (tdIORequestBody == agNULL) + { + /* to be aborted IO has been completed. */ + /* free up allocated memory */ + TI_DBG1(("tiINITaskManagement: IO has been completed\n")); + ostiFreeMemory( + tiRoot, + osMemHandle, + sizeof(tdIORequestBody_t) + ); + return tiIONoDevice; + } + else + { + agTMRequest = &(tdIORequestBody->agIORequest); + } + } + else + { + /* + For LUN RESET, WARM_RESET, ABORT_TASK_SET, CLEAR_ACA and CLEAR_TASK_SET + no tag to be managed. + Therefore, set it to zero. + */ + agSSPTaskMgntRequest->tagOfTaskToBeManaged = 0; + agTMRequest = agNULL; + + } + + TDLIST_INIT_HDR(&TMtdIORequestBody->EsglPageList); + /* debuggging */ + if (TMtdIORequestBody->IOCompletionFunc == agNULL) + { + TI_DBG1(("tiINITaskManagement: Error!!!!! IOCompletionFunc is NULL\n")); + } + saStatus = saSSPStart(agRoot, + agIORequest, /* task management itself */ + tdsaRotateQnumber(tiRoot, oneDeviceData), + agDevHandle, + agRequestType, + agSASRequestBody, /* task management itself */ + agTMRequest, /* io to be aborted if exits */ + &ossaSSPCompleted); + + + if (saStatus == AGSA_RC_SUCCESS) + { + Initiator->NumIOsActive++; + tiStatus = tiSuccess; + } + else + { + TI_DBG1(("tiINITaskManagement: saSSPStart failed 0x%x\n",saStatus)); + /* free up allocated memory */ + ostiFreeMemory( + tiRoot, + TMtdIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + if (saStatus == AGSA_RC_FAILURE) + { + tiStatus = tiError; + } + else + { + /* AGSA_RC_BUSY */ + tiStatus = tiBusy; + } + } + } + } /* end of sas device */ + +#ifdef FDS_SM + else if (oneDeviceData->DeviceType == TD_SATA_DEVICE) + { + agsaContext_t *agContext = agNULL; + + /* save the task tag in tdsaDeviceData_t structure, for handling PORT_RESET_COMPLETE hw event */ + agContext = &(oneDeviceData->agDeviceResetContext); + agContext->osData = currentTaskTag; + +#ifdef REMOVED + /* for directly attached SATA, do localphycontrol for LUN and target reset, not smTaskManagement*/ + if (oneDeviceData->directlyAttached == agTRUE && + (task == AG_LOGICAL_UNIT_RESET || task == AG_TARGET_WARM_RESET)) + { + agRoot = oneDeviceData->agRoot; + agDevHandle = oneDeviceData->agDevHandle; + + currentTaskTag->tdData = oneDeviceData; + + if (task == AG_LOGICAL_UNIT_RESET) + { + if ( (lun->lun[0] | lun->lun[1] | lun->lun[2] | lun->lun[3] | + lun->lun[4] | lun->lun[5] | lun->lun[6] | lun->lun[7] ) != 0 ) + { + TI_DBG1(("tiINITaskManagement: *** REJECT *** LUN not zero, tiDeviceHandle=%p\n", + tiDeviceHandle)); + return tiError; + } + } + saSetDeviceState(agRoot, agNULL, tdsaRotateQnumber(tiRoot, oneDeviceData), agDevHandle, SA_DS_IN_RECOVERY); + tiStatus = saLocalPhyControl(agRoot, agContext, tdsaRotateQnumber(tiRoot, oneDeviceData), oneDeviceData->phyID, AGSA_PHY_HARD_RESET, agNULL); + } + else +#endif + { + smRoot = &(tdsaAllShared->smRoot); + smDeviceHandle = &(oneDeviceData->smDeviceHandle); + TI_DBG1(("tiINITaskManagement: FDS_SM SATA Device\n")); + + if ( taskTag != agNULL) + { + ToBeAbortedtdIORequestBody = (tdIORequestBody_t *)taskTag->tdData; + ToBeAborted = &(ToBeAbortedtdIORequestBody->smIORequest); + } + SMmemAllocStatus = ostiAllocMemory( + tiRoot, + &SMosMemHandle, + (void **)&SMTMtdIORequestBody, + &SMPhysUpper32, + &SMPhysLower32, + 8, + sizeof(tdIORequestBody_t), + agTRUE + ); + if (SMmemAllocStatus != tiSuccess) + { + TI_DBG1(("tiINITaskManagement: ostiAllocMemory failed... loc 2\n")); + return tiError; + } + + if (SMTMtdIORequestBody == agNULL) + { + TI_DBG1(("tiINITaskManagement: ostiAllocMemory returned NULL TMIORequestBody loc 2\n")); + return tiError; + } + + /* initialize */ + osti_memset(SMTMtdIORequestBody, 0, sizeof(tdIORequestBody_t)); + + /* setup task management structure */ + SMTMtdIORequestBody->IOType.InitiatorTMIO.osMemHandle = SMosMemHandle; + SMTMtdIORequestBody->IOType.InitiatorTMIO.CurrentTaskTag = currentTaskTag; + SMTMtdIORequestBody->IOType.InitiatorTMIO.TaskTag = taskTag; + + /* initialize tiDevhandle */ + SMTMtdIORequestBody->tiDevHandle = tiDeviceHandle; + + /* initialize tiIORequest */ + SMTMtdIORequestBody->tiIORequest = currentTaskTag; + /* save context if we need to abort later */ + currentTaskTag->tdData = SMTMtdIORequestBody; + + TaskManagement = &(SMTMtdIORequestBody->smIORequest); + + TaskManagement->tdData = SMTMtdIORequestBody; + TaskManagement->smData = &SMTMtdIORequestBody->smIORequestBody; + + tiStatus = smTaskManagement(smRoot, + smDeviceHandle, + task, + (smLUN_t*)lun, + ToBeAborted, + TaskManagement + ); + if (tiStatus != SM_RC_SUCCESS) + { + TI_DBG1(("tiINITaskManagement: smTaskManagement failed... loc 2\n")); + /* free up allocated memory */ + ostiFreeMemory( + tiRoot, + SMTMtdIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + } /* else */ + } +#else + else if (oneDeviceData->DeviceType == TD_SATA_DEVICE) + { + agRoot = oneDeviceData->agRoot; + agDevHandle = oneDeviceData->agDevHandle; + TI_DBG1(("tiINITaskManagement: not FDS_SM SATA Device\n")); + /* + WARM_RESET is experimental + Needs more testing and debugging + Soft reset for SATA as LUN RESET tends not to work. + Let's do hard reset + */ + if (task == AG_LOGICAL_UNIT_RESET || task == AG_TARGET_WARM_RESET) + { + + agsaContext_t *agContext; + satDeviceData_t *satDevData; + tdsaDeviceData_t *tdsaDeviceData; + + TI_DBG2(("tiINITaskManagement: did %d LUN reset or device reset for SATA\n", oneDeviceData->id)); + tdsaDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + satDevData = &tdsaDeviceData->satDevData; + currentTaskTag->tdData = tdsaDeviceData; + agContext = &(tdsaDeviceData->agDeviceResetContext); + agContext->osData = currentTaskTag; + + + if (task == AG_LOGICAL_UNIT_RESET) + { + if ( (lun->lun[0] | lun->lun[1] | lun->lun[2] | lun->lun[3] | + lun->lun[4] | lun->lun[5] | lun->lun[6] | lun->lun[7] ) != 0 ) + { + TI_DBG1(("tiINITaskManagement: *** REJECT *** LUN not zero, tiDeviceHandle=%p\n", + tiDeviceHandle)); + return tiError; + } + + /* + * Check if there is other TM request pending + */ + if (satDevData->satTmTaskTag != agNULL) + { + TI_DBG1(("tiINITaskManagement: *** REJECT *** other TM pending, tiDeviceHandle=%p\n", + tiDeviceHandle)); + return tiError; + } + } + satDevData->satDriveState = SAT_DEV_STATE_IN_RECOVERY; + satDevData->satAbortAfterReset = agFALSE; + + saSetDeviceState(agRoot, agNULL, tdsaRotateQnumber(tiRoot, oneDeviceData), agDevHandle, SA_DS_IN_RECOVERY); + + /* + warm reset by saLocalPhyControl or SMP PHY control + */ + if (oneDeviceData->directlyAttached == agTRUE) + { + TI_DBG1(("tiINITaskManagement: LUN reset or device reset directly attached\n")); + saLocalPhyControl(agRoot, agContext, tdsaRotateQnumber(tiRoot, oneDeviceData), oneDeviceData->phyID, AGSA_PHY_HARD_RESET, agNULL); + return tiSuccess; + } + else + { + TI_DBG1(("tiINITaskManagement: LUN reset or device reset expander attached\n")); + saStatus = tdsaPhyControlSend(tiRoot, + oneDeviceData, + SMP_PHY_CONTROL_HARD_RESET, + currentTaskTag, + tdsaRotateQnumber(tiRoot, oneDeviceData) + ); + return saStatus; + } + } + else + { + TI_DBG2(("tiINITaskManagement: calling satTM().\n")); + /* allocation tdIORequestBody and pass it to satTM() */ + memAllocStatus = ostiAllocMemory( + tiRoot, + &osMemHandle, + (void **)&TMtdIORequestBody, + &PhysUpper32, + &PhysLower32, + 8, + sizeof(tdIORequestBody_t), + agTRUE + ); + + if (memAllocStatus != tiSuccess) + { + TI_DBG1(("tiINITaskManagement: ostiAllocMemory failed... loc 2\n")); + return tiError; + } + + if (TMtdIORequestBody == agNULL) + { + TI_DBG1(("tiINITaskManagement: ostiAllocMemory returned NULL TMIORequestBody loc 2\n")); + return tiError; + + } + + /* initialize */ + osti_memset(TMtdIORequestBody, 0, sizeof(tdIORequestBody_t)); + + /* setup task management structure */ + TMtdIORequestBody->IOType.InitiatorTMIO.osMemHandle = osMemHandle; + TMtdIORequestBody->IOType.InitiatorTMIO.CurrentTaskTag = currentTaskTag; + TMtdIORequestBody->IOType.InitiatorTMIO.TaskTag = taskTag; + + /* initialize tiDevhandle */ + TMtdIORequestBody->tiDevHandle = tiDeviceHandle; + + /* initialize tiIORequest */ + TMtdIORequestBody->tiIORequest = currentTaskTag; + /* save context if we need to abort later */ + currentTaskTag->tdData = TMtdIORequestBody; + + /* initialize agIORequest */ + agIORequest = &(TMtdIORequestBody->agIORequest); + agIORequest->osData = (void *) TMtdIORequestBody; + agIORequest->sdkData = agNULL; /* SA takes care of this */ + + +#ifdef SATA_ENABLE + tiStatus = satTM( tiRoot, + tiDeviceHandle, + task, + lun, + taskTag, + currentTaskTag, + TMtdIORequestBody, + agTRUE + ); +#endif + } + } +#endif /* FDS_SM else*/ + + return tiStatus; +} +#endif /* INITIATOR_DRIVER */ + +#ifdef PASSTHROUGH +osGLOBAL bit32 +tiCOMPassthroughCmndStart( + tiRoot_t *tiRoot, + tiPassthroughRequest_t *tiPassthroughRequest, + tiDeviceHandle_t *tiDeviceHandle, + tiPassthroughCmnd_t *tiPassthroughCmnd, + void *tiPassthroughBody, + tiPortalContext_t *tiportalContext, + ostiPassthroughCmndEvent_t agEventCB + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdsaDeviceData_t *oneDeviceData; + agsaRoot_t *agRoot = agNULL; + agsaIORequest_t *agIORequest = agNULL; + agsaDevHandle_t *agDevHandle = agNULL; + bit32 agRequestType; + agsaSASRequestBody_t *agSASRequestBody = agNULL; + + tdPassthroughCmndBody_t *tdPTCmndBody; + tdssSMPRequestBody_t *tdssSMPRequestBody; + agsaSMPFrame_t *agSMPFrame; + agsaSSPVSFrame_t *agSSPVendorFrame; /* RMC */ + bit32 SMPFn, SMPFnResult, SMPFrameLen; + bit32 tiStatus = tiError; + bit32 saStatus = AGSA_RC_FAILURE; + tdsaPortStartInfo_t *tdsaPortStartInfo; + tdsaPortContext_t *tdsaPortContext; + + TI_DBG2(("tiCOMPassthroughCmndStart: start\n")); + + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + + TI_DBG6(("tiCOMPassthroughCmndStart: onedevicedata %p\n", oneDeviceData)); + + + tdPTCmndBody = (tdPassthroughCmndBody_t *)tiPassthroughBody; + + + if (tiPassthroughCmnd->passthroughCmnd != tiSMPCmnd || + tiPassthroughCmnd->passthroughCmnd != tiRMCCmnd) + { + return tiNotSupported; + } + + + if (oneDeviceData == agNULL && tiPassthroughCmnd->passthroughCmnd != tiSMPCmnd) + { + TI_DBG1(("tiCOMPassthroughCmndStart: tiDeviceHandle=%p DeviceData is NULL\n", tiDeviceHandle )); + return tiIONoDevice; + } + + /* starting IO with SAS device */ + if (oneDeviceData->DeviceType == TD_SAS_DEVICE) + { + if (tiPassthroughCmnd->passthroughCmnd == tiSMPCmnd) + { + TI_DBG2(("tiCOMPassthroughCmndStart: SMP\n")); + if (oneDeviceData == agNULL) + { + tdsaPortStartInfo = (tdsaPortStartInfo_t *)tiportalContext->tdData; + tdsaPortContext = tdsaPortStartInfo->portContext; + agRoot = tdsaPortContext->agRoot; + } + else + { + agRoot = oneDeviceData->agRoot; + agDevHandle = oneDeviceData->agDevHandle; + } + + + tdssSMPRequestBody = &(tdPTCmndBody->protocol.SMP.SMPBody); + agSASRequestBody = &(tdssSMPRequestBody->agSASRequestBody); + agSMPFrame = &(agSASRequestBody->smpFrame); + + /* saves callback function */ + tdPTCmndBody->EventCB = agEventCB; + + /* initialize command type */ + tdPTCmndBody->tiPassthroughCmndType = tiSMPCmnd; + + /* initialize tipassthroughrequest */ + tdPTCmndBody->tiPassthroughRequest = tiPassthroughRequest; + tiPassthroughRequest->tdData = tdPTCmndBody; + + /* initialize tiDevhandle */ + tdPTCmndBody->tiDevHandle = tiDeviceHandle; + + /* fill in SMP header */ + agSMPFrame->frameHeader.smpFrameType + = tiPassthroughCmnd->protocol.SMP.SMPHeader.smpFrameType; + agSMPFrame->frameHeader.smpFunction + = tiPassthroughCmnd->protocol.SMP.SMPHeader.smpFunction; + agSMPFrame->frameHeader.smpFunctionResult + = tiPassthroughCmnd->protocol.SMP.SMPHeader.smpFunctionResult; + agSMPFrame->frameHeader.smpReserved + = tiPassthroughCmnd->protocol.SMP.SMPHeader.smpReserved; + + if (tiPassthroughCmnd->protocol.SMP.IT == SMP_INITIATOR) + { + agRequestType = AGSA_SMP_INIT_REQ; + } + else + { + agRequestType = AGSA_SMP_TGT_RESPONSE; + /* this is only for SMP target */ + agSMPFrame->phyId = tiPassthroughCmnd->protocol.SMP.phyID; + } + + /* fill in payload */ + /* assumption: SMP payload is in tisgl1 */ + agSMPFrame->frameAddrUpper32 = tiPassthroughCmnd->tiSgl.upper; + agSMPFrame->frameAddrLower32 = tiPassthroughCmnd->tiSgl.lower; + + /* This length excluding SMP header (4 bytes) and CRC field */ + agSMPFrame->frameLen = tiPassthroughCmnd->tiSgl.len; + + /* initialize agIORequest */ + /* + Compare: + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + */ + agIORequest = &(tdssSMPRequestBody->agIORequest); + agIORequest->osData = (void *) tdPTCmndBody; + agIORequest->sdkData = agNULL; /* LL takes care of this */ + + + + /* not work yet because of high priority q */ + saStatus = saSMPStart( + agRoot, + agIORequest, + agDevHandle, + agRequestType, + agSASRequestBody, + &ossaSMPCompleted + ); + + if (saStatus == AGSA_RC_SUCCESS) + { + tiStatus = tiSuccess; + } + else if (saStatus == AGSA_RC_FAILURE) + { + TI_DBG1(("tiCOMPassthroughCmndStart: saSMPStart failed\n")); + tiStatus = tiError; + } + else + { + /* AGSA_RC_BUSY */ + TI_DBG1(("tiCOMPassthroughCmndStart: saSMPStart busy\n")); + tiStatus = tiBusy; + } + return tiStatus; + + +#ifdef TO_DO + /* fill in SMP header */ + if (tdPTCmndBody->protocol.SMP.IT == SMP_INITIATOR) + { + agSMPFrame->frameHeader.smpFrameType = SMP_REQUEST; /* SMP REQUEST */ + agRequestType = AGSA_SMP_INIT_REQ; + } + else + { + /* SMP target */ + agSMPFrame->frameHeader.smpFrameType = SMP_RESPONSE; /* SMP RESPONSE */ + agRequestType = AGSA_SMP_TGT_RESPONSE; + switch (tdPTCmndBody->protocol.SMP.SMPFnResult) + { + case tiSMPFunctionAccepted: + SMPFnResult = SMP_FUNCTION_ACCEPTED; + break; + case tiUnknownSMPFunction: + SMPFnResult = UNKNOWN_SMP_FUNCTION; + break; + case tiSMPFunctionFailed: + SMPFnResult = SMP_FUNCTION_FAILED; + break; + case tiInvalidRequestFrameLength: + SMPFnResult = INVALID_REQUEST_FRAME_LENGTH; + break; + case tiPhyDoesNotExist: + SMPFnResult =PHY_DOES_NOT_EXIST; + break; + case tiIndexDoesNotExist: + SMPFnResult = INDEX_DOES_NOT_EXIST; + break; + case tiPhyDoesNotSupportSATA: + SMPFnResult = PHY_DOES_NOT_SUPPORT_SATA; + break; + case tiUnknownPhyOperation: + SMPFnResult = UNKNOWN_PHY_OPERATION; + break; + case tiUnknownPhyTestFunction: + SMPFnResult = UNKNOWN_PHY_TEST_FUNCTION; + break; + case tiPhyTestFunctionInProgress: + SMPFnResult = PHY_TEST_FUNCTION_IN_PROGRESS; + break; + case tiPhyVacant: + SMPFnResult = PHY_VACANT; + break; + + default: + TI_DBG1(("tiCOMPassthroughCmndStart: unknown SMP function result %d\n", tdPTCmndBody->protocol.SMP.SMPFnResult)); + return tiError; + } + agSMPFrame->frameHeader.smpFunctionResult = SMPFnResult; + } + + /* common */ + switch (tdPTCmndBody->protocol.SMP.SMPFn) + { + case tiGeneral: + SMPFn = SMP_REPORT_GENERAL; + if (tdPTCmndBody->protocol.SMP.IT == SMP_INITIATOR) + { + SMPFrameLen = 0; + } + else + { + SMPFrameLen = sizeof(smpRespReportGeneral_t); + } + break; + + case tiManufacturerInfo: + SMPFn = SMP_REPORT_MANUFACTURE_INFORMATION; + if (tdPTCmndBody->protocol.SMP.IT == SMP_INITIATOR) + { + SMPFrameLen = 0; + } + else + { + SMPFrameLen = sizeof(smpRespReportManufactureInfo_t); + } + break; + + case tiDiscover: + SMPFn = SMP_DISCOVER; + if (tdPTCmndBody->protocol.SMP.IT == SMP_INITIATOR) + { + SMPFrameLen = sizeof(smpReqDiscover_t); + } + else + { + SMPFrameLen = sizeof(smpRespDiscover_t); + } + break; + + case tiReportPhyErrLog: + SMPFn = SMP_REPORT_PHY_ERROR_LOG; + if (tdPTCmndBody->protocol.SMP.IT == SMP_INITIATOR) + { + SMPFrameLen = 8; + } + else + { + SMPFrameLen = 24; + } + break; + + case tiReportPhySATA: + SMPFn = SMP_REPORT_PHY_SATA; + if (tdPTCmndBody->protocol.SMP.IT == SMP_INITIATOR) + { + SMPFrameLen = sizeof(SmpReqReportPhySata_t); + } + else + { + SMPFrameLen = sizeof(SmpRespReportPhySata_t); + } + break; + + case tiReportRteInfo: + SMPFn = SMP_REPORT_ROUTING_INFORMATION; + if (tdPTCmndBody->protocol.SMP.IT == SMP_INITIATOR) + { + SMPFrameLen = sizeof(SmpReqReportRouteTable_t); + } + else + { + SMPFrameLen = sizeof(SmpRespReportRouteTable_t); + } + break; + + case tiConfigureRteInfo: + SMPFn = SMP_CONFIGURE_ROUTING_INFORMATION;; + if (tdPTCmndBody->protocol.SMP.IT == SMP_INITIATOR) + { + SMPFrameLen = sizeof(SmpReqConfigureRouteInformation_t); + } + else + { + SMPFrameLen = 0; + } + break; + + case tiPhyCtrl: + SMPFn = SMP_PHY_CONTROL; + if (tdPTCmndBody->protocol.SMP.IT == SMP_INITIATOR) + { + SMPFrameLen = sizeof(SmpReqPhyControl_t); + } + else + { + SMPFrameLen = 0; + } + break; + + case tiPhyTestFn: + SMPFn = SMP_PHY_TEST_FUNCTION; + if (tdPTCmndBody->protocol.SMP.IT == SMP_INITIATOR) + { + SMPFrameLen = 36; + } + else + { + SMPFrameLen = 0; + } + break; + + case tiPMC: + SMPFn = SMP_PMC_SPECIFIC; + if (tdPTCmndBody->protocol.SMP.IT == SMP_INITIATOR) + { + SMPFrameLen = 0; + } + else + { + SMPFrameLen = 0; + } + break; + + + default: + TI_DBG1(("tiCOMPassthroughCmndStart: unknown SMP function %d\n", tdPTCmndBody->protocol.SMP.SMPFn)); + return tiError; + } + agSMPFrame->frameHeader.smpFunction = SMPFn; + + + /* assumption: SMP payload is in tisgl1 */ + agSMPFrame->frameAddrUpper32 = tdPTCmndBody->tiSgl.upper; + agSMPFrame->frameAddrLower32 = tdPTCmndBody->tiSgl.lower; + + /* This length excluding SMP header (4 bytes) and CRC field */ + agSMPFrame->frameLen = SMPFrameLen; + + + + + + +#endif + + + } + else if (tiPassthroughCmnd->passthroughCmnd == tiRMCCmnd) + { + TI_DBG2(("tiCOMPassthroughCmndStart: RMC\n")); + } + else + { + TI_DBG1(("tiCOMPassthroughCmndStart: unknown protocol %d\n", tiPassthroughCmnd->passthroughCmnd)); + } + + + } + else if (oneDeviceData->DeviceType == TD_SATA_DEVICE) + { + TI_DBG1(("tiCOMPassthroughCmndStart: error !!! no SATA support\n")); + return tiError; + } + else + { + TI_DBG1(("tiCOMPassthroughCmndStart: error !!! unknown devietype %d\n", oneDeviceData->DeviceType)); + return tiError; + + } + + return tiSuccess; +} + + +osGLOBAL bit32 +tiCOMPassthroughCmndAbort( + tiRoot_t *tiRoot, + tiPassthroughRequest_t *taskTag + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + agsaRoot_t *agRoot = agNULL; + tdPassthroughCmndBody_t *tdPTCmndBody = agNULL; + tdssSMPRequestBody_t *tdssSMPRequestBody = agNULL; + agsaIORequest_t *agIORequest = agNULL; + bit32 saStatus, tiStatus = tiError; + + TI_DBG2(("tiCOMPassthroughCmndAbort: start\n")); + + agRoot = &(tdsaAllShared->agRootNonInt); + tdPTCmndBody = (tdPassthroughCmndBody_t *)taskTag->tdData; + + if (tdPTCmndBody->tiPassthroughCmndType == tiSMPCmnd) + { + tdssSMPRequestBody = &(tdPTCmndBody->protocol.SMP.SMPBody); + agIORequest = &(tdssSMPRequestBody->agIORequest); + + saStatus = saSMPAbort(agRoot, agIORequest); + + if (saStatus == AGSA_RC_SUCCESS) + { + tiStatus = tiSuccess; + } + else if (saStatus == AGSA_RC_FAILURE) + { + TI_DBG1(("tiCOMPassthroughCmndAbort: saSMPAbort failed\n")); + tiStatus = tiError; + } + else + { + /* AGSA_RC_BUSY */ + TI_DBG1(("tiCOMPassthroughCmndAbort: saSMPAbort busy\n")); + tiStatus = tiBusy; + } + return tiStatus; + } + else if (tdPTCmndBody->tiPassthroughCmndType == tiRMCCmnd) + { + TI_DBG1(("tiCOMPassthroughCmndAbort: RMC passthrough command type, not yet\n")); + + } + else + { + TI_DBG1(("tiCOMPassthroughCmndAbort: unknown passthrough command type %d\n", tdPTCmndBody->tiPassthroughCmndType)); + return tiStatus; + } + + +} + +osGLOBAL bit32 +tiINIPassthroughCmndRemoteAbort( + tiRoot_t *tiRoot, + tiDeviceHandle_t *tiDeviceHandle, + tiPassthroughRequest_t *taskTag, + tiPassthroughRequest_t *currentTaskTag, + tiPortalContext_t *tiportalContext + ) +{ + TI_DBG2(("tiINIPassthroughCmndRemoteAbort: start\n")); + /* + for SMP, nothing. Can't abot remotely + */ + return tiSuccess; +} +#endif /* PASSTHROUGH */ + + +/***************************************************************************** +*! \brief tiCOMShutDown +* +* Purpose: This function is called to shutdown the initiator and/or target +* operation. Following the completion of this call, the state is +* equivalent to the state prior to tiCOMInit() +* +* \param tiRoot: Pointer to root data structure. +* +* \return None +* +* +*****************************************************************************/ +osGLOBAL void +tiCOMShutDown( tiRoot_t *tiRoot) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + +// #define TI_GETFOR_ONSHUTDOWN +#ifdef TI_GETFOR_ONSHUTDOWN + agsaForensicData_t forensicData; + bit32 once = 1; + bit32 status; +#endif /* TI_GETFOR_ONSHUTDOWN */ + + agsaRoot_t *agRoot = agNULL; + + TI_DBG1(("tiCOMShutDown: start\n")); + + + agRoot = &(tdsaAllShared->agRootNonInt); + /* + 1. free up cardID + 2. call saHwShutdown() + 3. tdInitEsgl(tiRoot); + 4. tdsaResetComMemFlags(tiRoot) + 5. ostiPortEvent() + */ + + tdsaFreeCardID(tiRoot, tdsaAllShared->CardID); + +#ifdef TI_GETFOR_ONSHUTDOWN + forensicData.DataType = TYPE_NON_FATAL; + forensicData.dataBuf.directLen = (8 * 1024); + forensicData.dataBuf.directOffset = 0; /* current offset */ + forensicData.dataBuf.directData = agNULL; + forensicData.dataBuf.readLen = 0; /* Data read */ + + getmoreData: + status = saGetForensicData( agRoot, agNULL, &forensicData); + + TI_DBG1(("tiCOMShutDown:readLen 0x%x directLen 0x%x directOffset 0x%x\n", + forensicData.dataBuf.readLen, + forensicData.dataBuf.directLen, + forensicData.dataBuf.directOffset)); + if( forensicData.dataBuf.readLen == forensicData.dataBuf.directLen && !status && once) + { + goto getmoreData; + } + + TI_DBG1(("tiCOMShutDown:saGetForensicData type %d read 0x%x bytes\n", forensicData.DataType, forensicData.dataBuf.directOffset )); +#endif /* TI_GETFOR_ONSHUTDOWN */ + + saHwShutdown(agRoot); + + /* resets all the relevant flags */ + tdsaResetComMemFlags(tiRoot); + + /* + * send an event to the oslayer + */ + ostiPortEvent ( + tiRoot, + tiPortShutdown, + tiSuccess, + agNULL + ); + + return; +} + +#ifdef INITIATOR_DRIVER +osGLOBAL void +tiINITimerTick( tiRoot_t *tiRoot ) +{ + /* + no timer is used in SAS TD layer. + Therefore, this function is null. + */ + // TI_DBG2(("tiINITimerTick: start\n")); + /*itdsaProcessTimers(tiRoot);*/ + return; +} +#endif + +/*****************************************************************************/ +/*! \brief ossaDisableInterrupts + * + * + * Purpose: This routine is called to disable interrupt + * + * + * \param agRoot: Pointer to chip/driver Instance. + * \param outboundChannelNum: Zero-base channel number + * + * + * \return None. + * + * \note - The scope is shared target and initiator. + * + */ +/*****************************************************************************/ +#ifndef ossaDisableInterrupts +osGLOBAL void +ossaDisableInterrupts( + agsaRoot_t *agRoot, + bit32 outboundChannelNum + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *) (agRoot->osData); + + ostiInterruptDisable( + osData->tiRoot, + outboundChannelNum + ); + return; +} + +#endif + + +osGLOBAL void +tiCOMFrameReadBlock( + tiRoot_t *tiRoot, + void *agFrame, + bit32 FrameOffset, + void *FrameBuffer, + bit32 FrameBufLen ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + agsaRoot_t *agRoot = agNULL; + + TI_DBG6(("tiCOMFrameReadBlock: start\n")); + + + agRoot = &(tdsaAllShared->agRootNonInt); + + + TI_DBG6(("tiCOMFrameReadBlock: start\n")); + + saFrameReadBlock(agRoot, agFrame, FrameOffset, FrameBuffer, FrameBufLen); + + return; +} + + + +/***************************************************************************** +*! \brief tiINITransportRecovery +* +* Purpose: This routine is called to explicitly ask the Transport Dependent +* Layer to initiate the recovery for the transport/protocol specific +* error for a specific device connection. +* +* \param tiRoot: Pointer to driver instance +* \param tiDeviveHandle: Pointer to the device handle for this session. +* +* \return: None +* +* +*****************************************************************************/ +#ifdef INITIATOR_DRIVER +osGLOBAL void +tiINITransportRecovery ( + tiRoot_t *tiRoot, + tiDeviceHandle_t *tiDeviceHandle + ) +{ + agsaRoot_t *agRoot = agNULL; + tdsaDeviceData_t *oneDeviceData = agNULL; + tdsaPortContext_t *onePortContext = agNULL; + tiPortalContext_t *tiPortalContext = agNULL; + tiIORequest_t *currentTaskTag; + agsaDevHandle_t *agDevHandle = agNULL; + + TI_DBG1(("tiINITransportRecovery: start\n")); + + if (tiDeviceHandle == agNULL) + { + TI_DBG1(("tiINITransportRecovery: tiDeviceHandle is NULL\n")); + + return; + } + + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + + if (oneDeviceData == agNULL) + { + TI_DBG1(("tiINITransportRecovery: oneDeviceData is NULL\n")); + return; + } + + /* for hotplug */ + if (oneDeviceData->valid != agTRUE || oneDeviceData->registered != agTRUE || + oneDeviceData->tdPortContext == agNULL ) + { + TI_DBG1(("tiINITransportRecovery: NO Device did %d\n", oneDeviceData->id )); + TI_DBG1(("tiINITransportRecovery: device AddrHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG1(("tiINITransportRecovery: device AddrLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + return; + } + + onePortContext = oneDeviceData->tdPortContext; + + if (onePortContext == agNULL) + { + TI_DBG1(("tiINITransportRecovery: onePortContext is NULL\n")); + return; + } + + tiPortalContext = onePortContext->tiPortalContext; + currentTaskTag = &(oneDeviceData->TransportRecoveryIO); + currentTaskTag->osData = agNULL; + agRoot = oneDeviceData->agRoot; + agDevHandle = oneDeviceData->agDevHandle; + + if (oneDeviceData->DeviceType == TD_SAS_DEVICE) + { + agsaContext_t *agContext; + currentTaskTag->tdData = oneDeviceData; + agContext = &(oneDeviceData->agDeviceResetContext); + agContext->osData = currentTaskTag; + oneDeviceData->TRflag = agTRUE; + + TI_DBG2(("tiINITransportRecovery: SAS device\n")); + saSetDeviceState(agRoot, agNULL, tdsaRotateQnumber(tiRoot, oneDeviceData), agDevHandle, SA_DS_IN_RECOVERY); + + if (oneDeviceData->directlyAttached == agTRUE) + { + TI_DBG2(("tiINITransportRecovery: saLocalPhyControl\n")); + saLocalPhyControl(agRoot, agContext, tdsaRotateQnumber(tiRoot, oneDeviceData), oneDeviceData->phyID, AGSA_PHY_HARD_RESET, agNULL); + ostiInitiatorEvent(tiRoot, + tiPortalContext, + tiDeviceHandle, + tiIntrEventTypeTransportRecovery, + tiRecStarted, + agNULL + ); + + return; + } + else + { + TI_DBG2(("tiINITransportRecovery: device reset expander attached\n")); + tdsaPhyControlSend(tiRoot, + oneDeviceData, + SMP_PHY_CONTROL_HARD_RESET, + currentTaskTag, + tdsaRotateQnumber(tiRoot, oneDeviceData) + ); + ostiInitiatorEvent(tiRoot, + tiPortalContext, + tiDeviceHandle, + tiIntrEventTypeTransportRecovery, + tiRecStarted, + agNULL + ); + return; + } + } + else if (oneDeviceData->DeviceType == TD_SATA_DEVICE) + { + agsaContext_t *agContext; + currentTaskTag->tdData = oneDeviceData; + agContext = &(oneDeviceData->agDeviceResetContext); + agContext->osData = currentTaskTag; + oneDeviceData->TRflag = agTRUE; + + TI_DBG2(("tiINITransportRecovery: SATA device\n")); + saSetDeviceState(agRoot, agNULL, tdsaRotateQnumber(tiRoot, oneDeviceData), agDevHandle, SA_DS_IN_RECOVERY); + + if (oneDeviceData->directlyAttached == agTRUE) + { + TI_DBG2(("tiINITransportRecovery: saLocalPhyControl\n")); + saLocalPhyControl(agRoot, agContext, tdsaRotateQnumber(tiRoot, oneDeviceData), oneDeviceData->phyID, AGSA_PHY_LINK_RESET, agNULL); + ostiInitiatorEvent(tiRoot, + tiPortalContext, + tiDeviceHandle, + tiIntrEventTypeTransportRecovery, + tiRecStarted, + agNULL + ); + + return; + } + else + { + TI_DBG2(("tiINITransportRecovery: device reset expander attached\n")); + tdsaPhyControlSend(tiRoot, + oneDeviceData, + SMP_PHY_CONTROL_LINK_RESET, + currentTaskTag, + tdsaRotateQnumber(tiRoot, oneDeviceData) + ); + ostiInitiatorEvent(tiRoot, + tiPortalContext, + tiDeviceHandle, + tiIntrEventTypeTransportRecovery, + tiRecStarted, + agNULL + ); + return; + } + } + else + { + TI_DBG1(("tiINITransportRecovery: wrong device type %d\n", oneDeviceData->DeviceType)); + } + + + return; +} +#endif + +#if defined (INITIATOR_DRIVER) && defined (TARGET_DRIVER) +/***************************************************************************** +*! \brief tdsaPhyControlSend +* +* Purpose: This function sends Phy Control to a device. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param oneDeviceData: Pointer to the device data. +* \param phyId: Phy Identifier. +* \param queueNumber: bits 0-15: inbound queue number. +* bits 16-31: outbound queue number. +* +* \return: +* Status +* +* \note: +* +*****************************************************************************/ +/* phyop of interest +SMP_PHY_CONTROL_HARD_RESET or SMP_PHY_CONTROL_CLEAR_AFFILIATION +if CurrentTaskTag == agNULL, clear affiliation +if CurrentTaskTag != agNULL, PHY_CONTROL (device reset) + +*/ +osGLOBAL bit32 +tdsaPhyControlSend( + tiRoot_t *tiRoot, + tdsaDeviceData_t *oneDeviceData, /* taget disk */ + bit8 phyOp, + tiIORequest_t *CurrentTaskTag, + bit32 queueNumber + ) +{ + return 0; +} +#endif + +#ifdef TARGET_DRIVER +/***************************************************************************** +*! \brief tdsaPhyControlSend +* +* Purpose: This function sends Phy Control to a device. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param oneDeviceData: Pointer to the device data. +* \param phyId: Phy Identifier. +* \param queueNumber: bits 0-15: inbound queue number. +* bits 16-31: outbound queue number. +* +* \return: +* Status +* +* \note: +* +*****************************************************************************/ +/* phyop of interest +SMP_PHY_CONTROL_HARD_RESET or SMP_PHY_CONTROL_CLEAR_AFFILIATION +if CurrentTaskTag == agNULL, clear affiliation +if CurrentTaskTag != agNULL, PHY_CONTROL (device reset) + +*/ +osGLOBAL bit32 +tdsaPhyControlSend( + tiRoot_t *tiRoot, + tdsaDeviceData_t *oneDeviceData, /* taget disk */ + bit8 phyOp, + tiIORequest_t *CurrentTaskTag, + bit32 queueNumber + ) +{ + return 0; +} +#endif + + +#ifdef INITIATOR_DRIVER +/***************************************************************************** +*! \brief tdsaPhyControlSend +* +* Purpose: This function sends Phy Control to a device. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param oneDeviceData: Pointer to the device data. +* \param phyId: Phy Identifier. +* \param queueNumber: bits 0-15: inbound queue number. +* bits 16-31: outbound queue number. +* +* \return: +* Status +* +* \note: +* +*****************************************************************************/ +/* phyop of interest +SMP_PHY_CONTROL_HARD_RESET or SMP_PHY_CONTROL_CLEAR_AFFILIATION +if CurrentTaskTag == agNULL, clear affiliation +if CurrentTaskTag != agNULL, PHY_CONTROL (device reset) + +*/ +osGLOBAL bit32 +tdsaPhyControlSend( + tiRoot_t *tiRoot, + tdsaDeviceData_t *oneDeviceData, /* taget disk */ + bit8 phyOp, + tiIORequest_t *CurrentTaskTag, + bit32 queueNumber + ) +{ + agsaRoot_t *agRoot; + tdsaDeviceData_t *oneExpDeviceData; + tdsaPortContext_t *onePortContext; + smpReqPhyControl_t smpPhyControlReq; + bit8 phyID; + bit32 status; + + TI_DBG3(("tdsaPhyControlSend: start\n")); + + agRoot = oneDeviceData->agRoot; + onePortContext = oneDeviceData->tdPortContext; + oneExpDeviceData = oneDeviceData->ExpDevice; + phyID = oneDeviceData->phyID; + + if (oneDeviceData->directlyAttached == agTRUE) + { + TI_DBG1(("tdsaPhyControlSend: Error!!! deivce is directly attached\n")); + return AGSA_RC_FAILURE; + } + if (onePortContext == agNULL) + { + TI_DBG1(("tdsaPhyControlSend: Error!!! portcontext is NULL\n")); + return AGSA_RC_FAILURE; + } + + if (oneExpDeviceData == agNULL) + { + TI_DBG1(("tdsaPhyControlSend: Error!!! expander is NULL\n")); + return AGSA_RC_FAILURE; + } + + if (phyOp == SMP_PHY_CONTROL_HARD_RESET) + { + TI_DBG3(("tdsaPhyControlSend: SMP_PHY_CONTROL_HARD_RESET\n")); + } + if (phyOp == SMP_PHY_CONTROL_LINK_RESET) + { + TI_DBG3(("tdsaPhyControlSend: SMP_PHY_CONTROL_LINK_RESET\n")); + } + if (phyOp == SMP_PHY_CONTROL_CLEAR_AFFILIATION) + { + TI_DBG3(("tdsaPhyControlSend: SMP_PHY_CONTROL_CLEAR_AFFILIATION\n")); + } + TI_DBG3(("tdsaPhyControlSend: target device AddrHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG3(("tdsaPhyControlSend: target device AddrLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + TI_DBG3(("tdsaPhyControlSend: expander AddrHi 0x%08x\n", oneExpDeviceData->SASAddressID.sasAddressHi)); + TI_DBG3(("tdsaPhyControlSend: expander AddrLo 0x%08x\n", oneExpDeviceData->SASAddressID.sasAddressLo)); + TI_DBG3(("tdsaPhyControlSend: did %d expander did %d phyid %d\n", oneDeviceData->id, oneExpDeviceData->id, phyID)); + + + osti_memset(&smpPhyControlReq, 0, sizeof(smpReqPhyControl_t)); + + /* fill in SMP payload */ + smpPhyControlReq.phyIdentifier = phyID; + smpPhyControlReq.phyOperation = phyOp; + + status = tdSMPStart( + tiRoot, + agRoot, + oneExpDeviceData, + SMP_PHY_CONTROL, + (bit8 *)&smpPhyControlReq, + sizeof(smpReqPhyControl_t), + AGSA_SMP_INIT_REQ, + CurrentTaskTag, + queueNumber + ); + return status; +} +#endif + +/***************************************************************************** +*! \brief tdsaPhyControlFailureRespRcvd +* +* Purpose: This function processes the failure of Phy Control response. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param agRoot: Pointer to chip/driver Instance. +* \param oneDeviceData: Pointer to the device data. +* \param frameHeader: Pointer to SMP frame header. +* \param frameHandle: A Handle used to refer to the response frame +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaPhyControlFailureRespRcvd( + tiRoot_t *tiRoot, + agsaRoot_t *agRoot, + tdsaDeviceData_t *oneDeviceData, + tdssSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle, + tiIORequest_t *CurrentTaskTag + ) +{ +#if defined(INITIATOR_DRIVER) || defined(TD_DEBUG_ENABLE) + tdsaDeviceData_t *TargetDeviceData = agNULL; +#endif +#ifdef TD_DEBUG_ENABLE + satDeviceData_t *pSatDevData = agNULL; +#endif +// agsaDevHandle_t *agDevHandle = agNULL; + + TI_DBG1(("tdsaPhyControlFailureRespRcvd: start\n")); + + TI_DBG3(("tdsaPhyControlFailureRespRcvd: expander device AddrHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG3(("tdsaPhyControlFailureRespRcvd: expander device AddrLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + + if (CurrentTaskTag != agNULL ) + { + /* This was set in tiINITaskmanagement() */ +#if defined(INITIATOR_DRIVER) || defined(TD_DEBUG_ENABLE) + TargetDeviceData = (tdsaDeviceData_t *)CurrentTaskTag->tdData; +#endif +#ifdef TD_DEBUG_ENABLE + pSatDevData = (satDeviceData_t *)&(TargetDeviceData->satDevData); +#endif +// agDevHandle = TargetDeviceData->agDevHandle; + TI_DBG2(("tdsaPhyControlFailureRespRcvd: target AddrHi 0x%08x\n", TargetDeviceData->SASAddressID.sasAddressHi)); + TI_DBG2(("tdsaPhyControlFailureRespRcvd: target AddrLo 0x%08x\n", TargetDeviceData->SASAddressID.sasAddressLo)); + +#ifdef TD_DEBUG_ENABLE + TI_DBG2(("tdsaPhyControlFailureRespRcvd: satPendingIO %d satNCQMaxIO %d\n", pSatDevData->satPendingIO, pSatDevData->satNCQMaxIO )); + TI_DBG2(("tdsaPhyControlFailureRespRcvd: satPendingNCQIO %d satPendingNONNCQIO %d\n", pSatDevData->satPendingNCQIO, pSatDevData->satPendingNONNCQIO)); +#endif + } + +#ifdef INITIATOR_DRIVER + if (CurrentTaskTag != agNULL ) + { + TI_DBG1(("tdsaPhyControlRespRcvd: callback to OS layer with failure\n")); + if (TargetDeviceData->TRflag == agTRUE) + { + TargetDeviceData->TRflag = agFALSE; + ostiInitiatorEvent(tiRoot, + TargetDeviceData->tdPortContext->tiPortalContext, + &(TargetDeviceData->tiDeviceHandle), + tiIntrEventTypeTransportRecovery, + tiRecFailed , + agNULL + ); + } + else + { + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMFailed, + CurrentTaskTag ); + } + } +#endif + return; +} +/***************************************************************************** +*! \brief tdsaPhyControlRespRcvd +* +* Purpose: This function processes Phy Control response. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param agRoot: Pointer to chip/driver Instance. +* \param oneDeviceData: Pointer to the device data. +* \param frameHeader: Pointer to SMP frame header. +* \param frameHandle: A Handle used to refer to the response frame +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaPhyControlRespRcvd( + tiRoot_t *tiRoot, + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + tdsaDeviceData_t *oneDeviceData, + tdssSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle, + tiIORequest_t *CurrentTaskTag + ) +{ +#if defined(INITIATOR_DRIVER) || defined(TD_DEBUG_ENABLE) + tdsaDeviceData_t *TargetDeviceData = agNULL; +#endif +#ifdef INITIATOR_DRIVER + satDeviceData_t *pSatDevData = agNULL; + agsaDevHandle_t *agDevHandle = agNULL; +#endif + + TI_DBG3(("tdsaPhyControlRespRcvd: start\n")); + + TI_DBG3(("tdsaPhyControlRespRcvd: expander device AddrHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG3(("tdsaPhyControlRespRcvd: expander device AddrLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + + if (CurrentTaskTag != agNULL ) + { + /* This was set in tiINITaskmanagement() */ +#if defined(INITIATOR_DRIVER) || defined(TD_DEBUG_ENABLE) + TargetDeviceData = (tdsaDeviceData_t *)CurrentTaskTag->tdData; +#endif +#ifdef INITIATOR_DRIVER + pSatDevData = (satDeviceData_t *)&(TargetDeviceData->satDevData); + agDevHandle = TargetDeviceData->agDevHandle; +#endif + TI_DBG2(("tdsaPhyControlRespRcvd: target AddrHi 0x%08x\n", TargetDeviceData->SASAddressID.sasAddressHi)); + TI_DBG2(("tdsaPhyControlRespRcvd: target AddrLo 0x%08x\n", TargetDeviceData->SASAddressID.sasAddressLo)); + +#ifdef INITIATOR_DRIVER + TI_DBG2(("tdsaPhyControlRespRcvd: satPendingIO %d satNCQMaxIO %d\n", pSatDevData->satPendingIO, pSatDevData->satNCQMaxIO )); + TI_DBG2(("tdsaPhyControlRespRcvd: satPendingNCQIO %d satPendingNONNCQIO %d\n", pSatDevData->satPendingNCQIO, pSatDevData->satPendingNONNCQIO)); +#endif + } + +#ifdef INITIATOR_DRIVER + /* no payload */ + if (frameHeader->smpFunctionResult == SMP_FUNCTION_ACCEPTED) + { + TI_DBG3(("tdsaPhyControlRespRcvd: SMP success\n")); + + /* warm reset or clear affiliation is done + call ostiInitiatorEvent() + */ + if (CurrentTaskTag != agNULL ) + { + TI_DBG3(("tdsaPhyControlRespRcvd: callback to OS layer with success\n")); + pSatDevData->satDriveState = SAT_DEV_STATE_NORMAL; + saSetDeviceState(agRoot, agNULL, tdsaRotateQnumber(tiRoot, TargetDeviceData), agDevHandle, SA_DS_OPERATIONAL); + + if (TargetDeviceData->TRflag == agTRUE) + { + TargetDeviceData->TRflag = agFALSE; + ostiInitiatorEvent(tiRoot, + TargetDeviceData->tdPortContext->tiPortalContext, + &(TargetDeviceData->tiDeviceHandle), + tiIntrEventTypeTransportRecovery, + tiRecOK, + agNULL + ); + } + else + { + agDevHandle = TargetDeviceData->agDevHandle; + if (agDevHandle == agNULL) + { + TI_DBG1(("tdsaPhyControlRespRcvd: wrong, agDevHandle is NULL\n")); + } + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMOK, + CurrentTaskTag ); + } + } + + } + else + { + TI_DBG1(("tdsaPhyControlRespRcvd: SMP failure; result %d\n", frameHeader->smpFunctionResult)); + /* warm reset or clear affiliation is done + */ + if (CurrentTaskTag != agNULL ) + { + TI_DBG1(("tdsaPhyControlRespRcvd: callback to OS layer with failure\n")); + if (TargetDeviceData->TRflag == agTRUE) + { + TargetDeviceData->TRflag = agFALSE; + ostiInitiatorEvent(tiRoot, + TargetDeviceData->tdPortContext->tiPortalContext, + &(TargetDeviceData->tiDeviceHandle), + tiIntrEventTypeTransportRecovery, + tiRecFailed , + agNULL + ); + } + else + { + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMFailed, + CurrentTaskTag ); + } + } + + } +#endif + return; +} + + +#ifdef TARGET_DRIVER +/***************************************************************************** +*! \brief ttdsaAbortAll +* +* Purpose: This function is called to abort an all pending I/O request on a +* device +* +* \param tiRoot: Pointer to initiator driver/port instance. +* \param agRoot: Pointer to chip/driver Instance. +* \param oneDeviceData: Pointer to the device +* +* \return: +* +* None +* +*****************************************************************************/ +/* + for abort itself, + should we allocate tdAbortIORequestBody or get one from ttdsaXchg_t? + Currently, we allocate tdAbortIORequestBody. +*/ +osGLOBAL void +ttdsaAbortAll( + tiRoot_t *tiRoot, + agsaRoot_t *agRoot, + tdsaDeviceData_t *oneDeviceData + ) +{ + agsaIORequest_t *agAbortIORequest = agNULL; + tdIORequestBody_t *tdAbortIORequestBody = agNULL; + bit32 PhysUpper32; + bit32 PhysLower32; + bit32 memAllocStatus; + void *osMemHandle; + + TI_DBG3(("tdsaAbortAll: start\n")); + + TI_DBG3(("tdsaAbortAll: did %d\n", oneDeviceData->id)); + + + /* allocating agIORequest for abort itself */ + memAllocStatus = ostiAllocMemory( + tiRoot, + &osMemHandle, + (void **)&tdAbortIORequestBody, + &PhysUpper32, + &PhysLower32, + 8, + sizeof(tdIORequestBody_t), + agTRUE + ); + if (memAllocStatus != tiSuccess) + { + /* let os process IO */ + TI_DBG1(("tdsaAbortAll: ostiAllocMemory failed...\n")); + return; + } + + if (tdAbortIORequestBody == agNULL) + { + /* let os process IO */ + TI_DBG1(("tdsaAbortAll: ostiAllocMemory returned NULL tdAbortIORequestBody\n")); + return; + } + + /* setup task management structure */ + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle = osMemHandle; + /* setting callback */ + /* not needed; it is already set to be ossaSSPAbortCB() */ + tdAbortIORequestBody->IOCompletionFunc = ttdssIOAbortedHandler; + + tdAbortIORequestBody->tiDevHandle = (tiDeviceHandle_t *)&(oneDeviceData->tiDeviceHandle); + + /* initialize agIORequest */ + agAbortIORequest = &(tdAbortIORequestBody->agIORequest); + agAbortIORequest->osData = (void *) tdAbortIORequestBody; + agAbortIORequest->sdkData = agNULL; /* LL takes care of this */ + + /* SSPAbort */ + saSSPAbort(agRoot, + agAbortIORequest, + 0, + oneDeviceData->agDevHandle, + 1, /* abort all */ + agNULL, + agNULL + ); + return; +} +#endif /* TARGET_DRIVER */ + + +osGLOBAL void +tdsaDeregisterDevicesInPort( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdsaDeviceData_t *oneDeviceData = agNULL; + tdList_t *DeviceListList; + agsaRoot_t *agRoot = agNULL; + + agRoot = &(tdsaAllShared->agRootNonInt); + + TI_DBG1(("tdsaDeregisterDevicesInPort: start\n")); + + /* find a device's existence */ + DeviceListList = tdsaAllShared->MainDeviceList.flink; + while (DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + TI_DBG1(("tdsaDeregisterDevicesInPort: oneDeviceData is NULL!!!\n")); + return; + } + if (oneDeviceData->tdPortContext == onePortContext) + { + TI_DBG3(("tdsaDeregisterDevicesInPort: Found pid %d did %d\n", onePortContext->id, oneDeviceData->id)); + if ( !( DEVICE_IS_SMP_TARGET(oneDeviceData) && oneDeviceData->directlyAttached == agTRUE)) + { + saDeregisterDeviceHandle(agRoot, agNULL, oneDeviceData->agDevHandle, tdsaRotateQnumber(tiRoot, oneDeviceData)); + } + else + { + TI_DBG1(("tdsaDeregisterDevicesInPort: keeping\n")); + oneDeviceData->registered = agTRUE; + } + } + DeviceListList = DeviceListList->flink; + } + + TI_DBG3(("tdsaDeregisterDevicesInPort: end\n")); + + return; +} + +/******************** for debugging only ***************************/ +osGLOBAL void +tdsaPrintSwConfig( + agsaSwConfig_t *SwConfig + ) +{ + if (SwConfig == agNULL) + { + TI_DBG6(("tdsaPrintSwConfig: SwConfig is NULL\n")); + return; + } + else + { + TI_DBG6(("SwConfig->maxActiveIOs %d\n", SwConfig->maxActiveIOs)); + TI_DBG6(("SwConfig->smpReqTimeout %d\n", SwConfig->smpReqTimeout)); + } + + return; + +} + +osGLOBAL void +tdsaPrintHwConfig( + agsaHwConfig_t *HwConfig + ) +{ + if (HwConfig == agNULL) + { + TI_DBG6(("tdsaPrintHwConfig: HwConfig is NULL\n")); + return; + } + else + { + TI_DBG6(("HwConfig->phyCount %d\n", HwConfig->phyCount)); + } + return; +} + +osGLOBAL void +tdssPrintSASIdentify( + agsaSASIdentify_t *id + ) +{ + if (id == agNULL) + { + TI_DBG1(("tdsaPrintSASIdentify: ID is NULL\n")); + return; + } + else + { + TI_DBG6(("SASID->sspTargetPort %d\n", SA_IDFRM_IS_SSP_TARGET(id)?1:0)); + TI_DBG6(("SASID->stpTargetPort %d\n", SA_IDFRM_IS_STP_TARGET(id)?1:0)); + TI_DBG6(("SASID->smpTargetPort %d\n", SA_IDFRM_IS_SMP_TARGET(id)?1:0)); + TI_DBG6(("SASID->sspInitiatorPort %d\n", SA_IDFRM_IS_SSP_INITIATOR(id)?1:0)); + TI_DBG6(("SASID->stpInitiatorPort %d\n", SA_IDFRM_IS_STP_INITIATOR(id)?1:0)); + TI_DBG6(("SASID->smpInitiatorPort %d\n", SA_IDFRM_IS_SMP_INITIATOR(id)?1:0)); + TI_DBG6(("SASID->deviceType %d\n", SA_IDFRM_GET_DEVICETTYPE(id))); + TI_DBG6(("SASID->sasAddressHi 0x%x\n", SA_IDFRM_GET_SAS_ADDRESSHI(id))); + TI_DBG6(("SASID->sasAddressLo 0x%x\n", SA_IDFRM_GET_SAS_ADDRESSLO(id))); + TI_DBG6(("SASID->phyIdentifier 0x%x\n", id->phyIdentifier)); + + } + + return; +} + +osGLOBAL void +tdsaInitTimerHandler( + tiRoot_t *tiRoot, + void *timerData + ) +{ + + TI_DBG6(("tdsaInitTimerHandler: start\n")); + return; +} + +/* + type: 1 portcontext 2 devicedata + flag: 1 FreeLink 2 MainLink +*/ + +osGLOBAL void +print_tdlist_flink(tdList_t *hdr, int type, int flag) +{ + tdList_t *hdr_tmp1 = NULL; +#ifdef TD_DEBUG_ENABLE + tdsaPortContext_t *ele1; +#endif +#ifdef REMOVED + tdsaDeviceData_t *ele2; +#endif + hdr_tmp1 = hdr; + + if (type == 1 && flag == 1) + { + TI_DBG6(("PortContext and FreeLink\n")); + } + else if (type != 1 && flag == 1) + { + TI_DBG6(("DeviceData and FreeLink\n")); + } + else if (type == 1 && flag != 1) + { + TI_DBG6(("PortContext and MainLink\n")); + } + else + { + TI_DBG6(("DeviceData and MainLink\n")); + } + if (type == 1) + { + do + { + /* data structure type variable = (data structure type, file name, header of the tdList) */ + if (flag == 1) + { +#ifdef TD_DEBUG_ENABLE + ele1 = TDLIST_OBJECT_BASE(tdsaPortContext_t, FreeLink, hdr_tmp1); +#endif + } + else + { +#ifdef TD_DEBUG_ENABLE + ele1 = TDLIST_OBJECT_BASE(tdsaPortContext_t, MainLink, hdr_tmp1); +#endif + } + TI_DBG6(("flist ele %d\n", ele1->id)); + TI_DBG6(("flist ele %p\n", ele1)); + hdr_tmp1 = hdr_tmp1->flink; + } while (hdr_tmp1 != hdr); + } + else + { + do + { + /* data structure type variable = (data structure type, file name, header of the tdList) */ +#ifdef REMOVED + if (flag == 1) + { + ele2 = TDLIST_OBJECT_BASE(tdsaDeviceData_t, FreeLink, hdr_tmp1); + } + else + { + ele2 = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, hdr_tmp1); + } + TI_DBG6(("flist ele %d\n", ele2->id)); + TI_DBG6(("flist ele %p\n", ele2)); +#endif + hdr_tmp1 = hdr_tmp1->flink; + } while (hdr_tmp1 != hdr); + } + TI_DBG6(("\n")); +} + +/* not verified yet. 6/15/2005 */ +osGLOBAL void +print_tdlist_blink(tdList_t *hdr, int flag) +{ + tdList_t *hdr_tmp1 = NULL; +#ifdef REMOVED + tdsaPortContext_t *ele1; +#endif + hdr_tmp1 = hdr; + + do + { + /* data structure type variable = (data structure type, file name, header of the tdList) */ +#ifdef REMOVED + if (flag == 1) + { + ele1 = TDLIST_OBJECT_BASE(tdsaPortContext_t, FreeLink, hdr_tmp1); + } + else + { + ele1 = TDLIST_OBJECT_BASE(tdsaPortContext_t, MainLink, hdr_tmp1); + } + TI_DBG6(("blist ele %d\n", ele1->id)); +#endif + + hdr_tmp1 = hdr_tmp1->blink; + } while (hdr_tmp1 != hdr); +} + + +/** hexidecimal dump */ +void tdhexdump(const char *ptitle, bit8 *pbuf, int len) +{ + int i; + TI_DBG2(("%s - hexdump(len=%d):\n", ptitle, (int)len)); + if (!pbuf) + { + TI_DBG1(("pbuf is NULL\n")); + return; + } + for (i = 0; i < len; ) + { + if (len - i > 4) + { + TI_DBG2((" 0x%02x, 0x%02x, 0x%02x, 0x%02x,\n", pbuf[i], pbuf[i+1], pbuf[i+2], pbuf[i+3])); + i += 4; + } + else + { + TI_DBG2((" 0x%02x,", pbuf[i])); + i++; + } + } + TI_DBG2(("\n")); +} + +void +tdsaSingleThreadedEnter(tiRoot_t *ptiRoot, bit32 queueId) +{ + tdsaRoot_t * tiroot = agNULL; + bit32 offset = 0; + TD_ASSERT(ptiRoot,"ptiRoot"); + tiroot = ptiRoot->tdData; + + offset = tiroot->tdsaAllShared.MaxNumLLLocks + tiroot->tdsaAllShared.MaxNumOSLocks; + + ostiSingleThreadedEnter(ptiRoot, queueId + offset); +} + +void +tdsaSingleThreadedLeave(tiRoot_t *ptiRoot, bit32 queueId) +{ + tdsaRoot_t * tiroot = agNULL; + bit32 offset = 0; + + TD_ASSERT(ptiRoot,"ptiRoot"); + tiroot = ptiRoot->tdData; + + offset = tiroot->tdsaAllShared.MaxNumLLLocks + tiroot->tdsaAllShared.MaxNumOSLocks; + + ostiSingleThreadedLeave(ptiRoot, queueId + offset); +} + +#ifdef PERF_COUNT +void +tdsaEnter(tiRoot_t *ptiRoot, int io) +{ + ostiEnter(ptiRoot, 1, io); +} + +void +tdsaLeave(tiRoot_t *ptiRoot, int io) +{ + ostiLeave(ptiRoot, 1, io); +} +#endif + diff --git a/sys/dev/pms/RefTisa/tisa/sassata/common/tdport.c b/sys/dev/pms/RefTisa/tisa/sassata/common/tdport.c new file mode 100644 index 000000000000..9a0a21cec0fa --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/common/tdport.c @@ -0,0 +1,8044 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +/*******************************************************************************/ +/** \file + * + * tdport.c + * This file contains port realted functions such as tiCOMPortStart() + * + */ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#ifdef FDS_SM +#include +#include +#include +#endif + +#ifdef FDS_DM +#include +#include +#include +#endif + +#include +#include +#include + +#ifdef INITIATOR_DRIVER +#include +#include +#include +#endif + +#ifdef TARGET_DRIVER +#include +#include +#include +#endif + +#include +#include + +#ifndef TURN_OFF_HDA +#include /* SPC HDA */ +#include +#include +#include + +#include /* SPCv HDA */ +#include + +#include /* Ila common to SPCv SPCvp versions */ + +#include /* SPCv 12g HDA */ +#include +#include /* Ila 12g SPCv SPCvp versions */ + +#endif /* TURN_OFF_HDA */ + + +bit32 gSSC_Disable = 0; +bit32 volatile sgpioResponseSet = 0; + +#ifdef ECHO_TESTING +/* temporary to test saEchoCommand() */ +bit8 gEcho; +#endif +bit32 tiCOMConfigureSgpio( + tiRoot_t *tiRoot, + bit8 enableSgpio + ); + + +/***************************************************************************** +*! \brief tdsaGetSwConfigParams +* +* Purpose: This function reads software configuration parameters from the +* configuration file +* +* \param tiRoot: Pointer to driver/port instance. +* +* \return: None +* +* \note - +* +*****************************************************************************/ +osGLOBAL void +tdsaGetSwConfigParams( + tiRoot_t *tiRoot + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&(tdsaRoot->tdsaAllShared); + agsaSwConfig_t *SwConfig; + agsaQueueConfig_t *QueueConfig; + char *buffer; + bit32 buffLen; + bit32 lenRecv = 0; + char *pLastUsedChar = agNULL; + char tmpBuffer[DEFAULT_KEY_BUFFER_SIZE]; + char globalStr[] = "Global"; + char iniParmsStr[] = "InitiatorParms"; + char SwParmsStr[] = "SWParms"; + char OBQueueProps[] = "OBQueueProps"; + char IBQueueProps[] = "IBQueueProps"; + char IBQueueSize[40]; + char OBQueueSize[40]; + char IBQueueEleSize[40]; + char OBQueueEleSize[40]; + char OBQueueInterruptCount[40]; + char OBQueueInterruptDelay[40]; + char OBQueueInterruptEnable[40]; + char IBQueuePriority[40]; + char *cardNum = tdsaAllShared->CardIDString; + bit32 i; + bit32 enableDIF; + bit32 enableEncryption; +#ifdef SA_CONFIG_MDFD_REGISTRY + bit32 disableMDF; +#endif + +#ifdef FDS_DM + dmSwConfig_t *dmSwConfig; +#endif +#ifdef FDS_SM + smSwConfig_t *smSwConfig; +#endif + + TI_DBG6(("tdsaGetSwConfigParams: start\n")); + TI_DBG6(("tdsaGetSwConfigParams: tdsaRoot %p tdsaAllShared %p \n",tdsaRoot, tdsaAllShared)); + + buffer = tmpBuffer; + buffLen = sizeof(tmpBuffer); + + osti_memset(buffer, 0, buffLen); + + /* the followings are the default values */ + SwConfig = (agsaSwConfig_t *)&(tdsaAllShared->SwConfig); + QueueConfig = (agsaQueueConfig_t *)&(tdsaAllShared->QueueConfig); + +#ifdef FDS_DM + dmSwConfig = (dmSwConfig_t *)&(tdsaAllShared->dmSwConfig); +#endif +#ifdef FDS_SM + smSwConfig = (smSwConfig_t *)&(tdsaAllShared->smSwConfig); +#endif + + /* + just default values + and are overwritten later by the configuration file contents + */ + SwConfig->numDevHandles = DEFAULT_MAX_DEV; + + SwConfig->maxActiveIOs = DEFAULT_MAX_ACTIVE_IOS; + SwConfig->smpReqTimeout = DEFAULT_SMP_TIMEOUT; /* DEFAULT_VALUE; */ + SwConfig->numberOfEventRegClients = DEFAULT_NUM_REG_CLIENTS; + SwConfig->sizefEventLog1 = HOST_EVENT_LOG_SIZE; + SwConfig->sizefEventLog2 = HOST_EVENT_LOG_SIZE; + SwConfig->eventLog1Option = DEFAULT_EVENT_LOG_OPTION; + SwConfig->eventLog2Option = DEFAULT_EVENT_LOG_OPTION; + SwConfig->fatalErrorInterruptEnable = 1; + SwConfig->fatalErrorInterruptVector = 0; /* Was 1 */ + SwConfig->hostDirectAccessSupport = 0; + SwConfig->hostDirectAccessMode = 0; + SwConfig->FWConfig = 0; + SwConfig->enableDIF = agFALSE; + SwConfig->enableEncryption = agFALSE; + +#ifdef SA_CONFIG_MDFD_REGISTRY + SwConfig->disableMDF = agFALSE; +#endif + + SwConfig->param1 = tdsaAllShared->tdDeviceIdVendId; + SwConfig->param2 = tdsaAllShared->tdSubVendorId; + + +#if defined(SALLSDK_DEBUG) + SwConfig->sallDebugLevel = 1; /* DEFAULT_VALUE; */ +#endif +#if defined(DM_DEBUG) + dmSwConfig->DMDebugLevel = 1; /* DEFAULT_VALUE; */ +#endif +#if defined(SM_DEBUG) + smSwConfig->SMDebugLevel = 1; /* DEFAULT_VALUE; */ +#endif + + tdsaAllShared->portTMO = PORT_RECOVERY_TIMEOUT; /* default 5 sec */ + tdsaAllShared->stp_idle_time = STP_IDLE_TIME; /* default 5 us */ + tdsaAllShared->itNexusTimeout = IT_NEXUS_TIMEOUT; /* default 2000 ms */ + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + globalStr, + iniParmsStr, + agNULL, + agNULL, + agNULL, + agNULL, + "MaxTargets", + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + SwConfig->numDevHandles = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + SwConfig->numDevHandles = osti_strtoul (buffer, &pLastUsedChar, 10); + } + TI_DBG2(("tdsaGetSwConfigParams: MaxTargets %d\n",SwConfig->numDevHandles )); + } + + /* + * read the NumInboundQueue parameter + */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + QueueConfig->numInboundQueues = DEFAULT_NUM_INBOUND_QUEUE; /* default 1 Inbound queue */ + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "NumInboundQueues", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + QueueConfig->numInboundQueues = (bit16) osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + QueueConfig->numInboundQueues = (bit16) osti_strtoul (buffer, &pLastUsedChar, 10); + } + + if (QueueConfig->numInboundQueues > AGSA_MAX_INBOUND_Q) + { + QueueConfig->numInboundQueues = AGSA_MAX_INBOUND_Q; + } + } + + /* + * read the NumOutboundQueue parameter + */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + QueueConfig->numOutboundQueues = DEFAULT_NUM_OUTBOUND_QUEUE; /* default 1 Outbound queue */ + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "NumOutboundQueues", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + QueueConfig->numOutboundQueues = (bit16) osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + QueueConfig->numOutboundQueues = (bit16) osti_strtoul (buffer, &pLastUsedChar, 10); + } + + if (QueueConfig->numOutboundQueues > AGSA_MAX_OUTBOUND_Q) + { + QueueConfig->numOutboundQueues = AGSA_MAX_OUTBOUND_Q; + } + } + + /* + * read the outbound queue option + */ + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + tdsaAllShared->QueueOption = DEFAULT_QUEUE_OPTION; /* default 0 Outbound queue element */ + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "QueueOption", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->QueueOption = (bit16) osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->QueueOption = (bit16) osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + + /* + * read the MaxActiveIO parameter + */ + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "MaxActiveIO", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + SwConfig->maxActiveIOs = osti_strtoul (buffer, &pLastUsedChar, 0); + TI_DBG6(("tdsaGetSwConfigParams: maxactiveio 1 !!!\n")); + } + else + { + SwConfig->maxActiveIOs = osti_strtoul (buffer, &pLastUsedChar, 10); + TI_DBG6(("tdsaGetSwConfigParams: maxactiveio 2 !!!\n")); + } + TI_DBG6(("tdsaGetSwConfigParams: maxactiveio 3 !!!\n")); + } + + + + /* + * read the SMPTO parameter (SMP Timeout) + */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "SMPTO", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + SwConfig->smpReqTimeout = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + SwConfig->smpReqTimeout = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + + + /* + * read the NumRegClients parameter (SMP Timeout) + */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "NumRegClients", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + SwConfig->numberOfEventRegClients = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + SwConfig->numberOfEventRegClients = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + +#if defined(SALLSDK_DEBUG) + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "LLDebugLevel", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + SwConfig->sallDebugLevel = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + SwConfig->sallDebugLevel = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } +#endif + +#if defined(DM_DEBUG) + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "DMDebugLevel", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + dmSwConfig->DMDebugLevel = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + dmSwConfig->DMDebugLevel = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } +#endif + +#if defined(SM_DEBUG) + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "SMDebugLevel", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + smSwConfig->SMDebugLevel = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + smSwConfig->SMDebugLevel = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } +#endif + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + for (i=0;inumInboundQueues;i++) + { + osti_sprintf(IBQueueSize,"IBQueueNumElements%d", i); + osti_sprintf(IBQueueEleSize,"IBQueueElementSize%d", i); + osti_sprintf(IBQueuePriority,"IBQueuePriority%d", i); + + /* + * read the IBQueueSize + */ + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + tdsaAllShared->InboundQueueSize[i] = DEFAULT_INBOUND_QUEUE_SIZE; /* default 256 Inbound queue size */ + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + IBQueueProps,/* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + IBQueueSize, /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->InboundQueueSize[i] = (bit16) osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->InboundQueueSize[i] = (bit16) osti_strtoul (buffer, &pLastUsedChar, 10); + TI_DBG6(("tdsaGetSwConfigParams: queue number %d IB queue size %d\n", i, tdsaAllShared->InboundQueueSize[i])); + } + } + + + /* + * read the IBQueueEleSize + */ + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + tdsaAllShared->InboundQueueEleSize[i] = DEFAULT_INBOUND_QUEUE_ELE_SIZE; /* default 128 Inbound queue element */ + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + IBQueueProps,/* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + IBQueueEleSize, /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->InboundQueueEleSize[i] = (bit16) osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->InboundQueueEleSize[i] = (bit16) osti_strtoul (buffer, &pLastUsedChar, 10); + TI_DBG6(("tdsaGetSwConfigParams: queue number %d IB queue ele size %d\n", i, tdsaAllShared->InboundQueueEleSize[i])); + } + } + + /* + * read the IBQueuePriority + */ + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + tdsaAllShared->InboundQueuePriority[i] = DEFAULT_INBOUND_QUEUE_PRIORITY; /* default 0 Inbound queue priority */ + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + IBQueueProps,/* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + IBQueuePriority, /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->InboundQueuePriority[i] = (bit16) osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->InboundQueuePriority[i] = (bit16) osti_strtoul (buffer, &pLastUsedChar, 10); + TI_DBG6(("tdsaGetSwConfigParams: queue number %d priority %d\n", i, tdsaAllShared->InboundQueuePriority[i])); + } + } + + /**********************************************/ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + }/* end of loop */ + + + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + for (i=0;inumOutboundQueues;i++) + { + osti_sprintf(OBQueueSize,"OBQueueNumElements%d", i); + osti_sprintf(OBQueueEleSize,"OBQueueElementSize%d", i); + osti_sprintf(OBQueueInterruptDelay,"OBQueueInterruptDelay%d", i); + osti_sprintf(OBQueueInterruptCount,"OBQueueInterruptCount%d", i); + osti_sprintf(OBQueueInterruptEnable,"OBQueueInterruptEnable%d", i); + + /* + * read the OBQueueSize + */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + + tdsaAllShared->OutboundQueueSize[i] = DEFAULT_OUTBOUND_QUEUE_SIZE; /* default 256 Outbound queue size */ + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + OBQueueProps, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + OBQueueSize, /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->OutboundQueueSize[i] = (bit16) osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->OutboundQueueSize[i] = (bit16) osti_strtoul (buffer, &pLastUsedChar, 10); + TI_DBG6(("tdsaGetSwConfigParams: queue number %d OB queue size %d\n", i, tdsaAllShared->OutboundQueueSize[i])); + + } + } + + + /* + * read the OBQueueEleSize + */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + + tdsaAllShared->OutboundQueueEleSize[i] = DEFAULT_OUTBOUND_QUEUE_ELE_SIZE; /* default 128 Outbound queue element */ + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + OBQueueProps, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + OBQueueEleSize, /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->OutboundQueueEleSize[i] = (bit16) osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->OutboundQueueEleSize[i] = (bit16) osti_strtoul (buffer, &pLastUsedChar, 10); + TI_DBG6(("tdsaGetSwConfigParams: queue number %d OB queue ele size %d\n", i, tdsaAllShared->OutboundQueueEleSize[i])); + + } + } + + + /* + * read the OBQueueInterruptDelay + */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + + tdsaAllShared->OutboundQueueInterruptDelay[i] = DEFAULT_OUTBOUND_QUEUE_INTERRUPT_DELAY; /* default 1 Outbound interrupt delay */ + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + OBQueueProps, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + OBQueueInterruptDelay, /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->OutboundQueueInterruptDelay[i] = (bit16) osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->OutboundQueueInterruptDelay[i] = (bit16) osti_strtoul (buffer, &pLastUsedChar, 10); + TI_DBG6(("tdsaGetSwConfigParams: queue number %d interrupt delay %d\n", i, tdsaAllShared->OutboundQueueInterruptDelay[i])); + + } + } + + /* + * read the OBQueueInterruptCount + */ + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + tdsaAllShared->OutboundQueueInterruptCount[i] = DEFAULT_OUTBOUND_QUEUE_INTERRUPT_COUNT; /* default 1 Outbound interrupt count */ + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + OBQueueProps, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + OBQueueInterruptCount, /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->OutboundQueueInterruptCount[i] = (bit16) osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->OutboundQueueInterruptCount[i] = (bit16) osti_strtoul (buffer, &pLastUsedChar, 10); + TI_DBG6(("tdsaGetSwConfigParams: queue number %d interrupt count %d\n", i, tdsaAllShared->OutboundQueueInterruptCount[i])); + } + } + + + /* + * read the OBQueueInterruptEnable + */ + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + tdsaAllShared->OutboundQueueInterruptEnable[i] = DEFAULT_OUTBOUND_INTERRUPT_ENABLE; /* default 1 Outbound interrupt is enabled */ + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + OBQueueProps, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + OBQueueInterruptEnable, /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->OutboundQueueInterruptEnable[i] = (bit16) osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->OutboundQueueInterruptEnable[i] = (bit16) osti_strtoul (buffer, &pLastUsedChar, 10); + TI_DBG6(("tdsaGetSwConfigParams: queue number %d interrupt enable %d\n", i, tdsaAllShared->OutboundQueueInterruptEnable[i])); + } + } + + /**********************************************/ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + }/* end of loop */ + + + + /********************READ CARD SPECIFIC *******************************************************/ + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + for (i=0;inumInboundQueues;i++) + { + osti_sprintf(IBQueueSize,"IBQueueNumElements%d", i); + osti_sprintf(IBQueueEleSize,"IBQueueElementSize%d", i); + osti_sprintf(IBQueuePriority,"IBQueuePriority%d", i); + + /* + * read the IBQueueSize + */ + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + cardNum, /* key */ + SwParmsStr, /* subkey1 */ + IBQueueProps,/* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + IBQueueSize, /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->InboundQueueSize[i] = (bit16) osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->InboundQueueSize[i] = (bit16) osti_strtoul (buffer, &pLastUsedChar, 10); + TI_DBG6(("tdsaGetSwConfigParams: queue number %d IB queue size %d\n", i, tdsaAllShared->InboundQueueSize[i])); + } + } + + /* + * read the IBQueueEleSize + */ + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + cardNum, /* key */ + SwParmsStr, /* subkey1 */ + IBQueueProps,/* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + IBQueueEleSize, /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->InboundQueueEleSize[i] = (bit16) osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->InboundQueueEleSize[i] = (bit16) osti_strtoul (buffer, &pLastUsedChar, 10); + TI_DBG6(("tdsaGetSwConfigParams: queue number %d IB queue ele size %d\n", i, tdsaAllShared->InboundQueueEleSize[i])); + } + } + + /* + * read the IBQueuePriority + */ + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + cardNum, /* key */ + SwParmsStr, /* subkey1 */ + IBQueueProps,/* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + IBQueuePriority, /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->InboundQueuePriority[i] = (bit16) osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->InboundQueuePriority[i] = (bit16) osti_strtoul (buffer, &pLastUsedChar, 10); + TI_DBG6(("tdsaGetSwConfigParams: card number %s queue number %d priority %d\n", cardNum, i, tdsaAllShared->InboundQueuePriority[i])); + } + } + + /**********************************************/ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + }/* end of loop */ + + + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + for (i=0;inumOutboundQueues;i++) + { + osti_sprintf(OBQueueSize,"OBQueueNumElements%d", i); + osti_sprintf(OBQueueEleSize,"OBQueueElementSize%d", i); + osti_sprintf(OBQueueInterruptDelay,"OBQueueInterruptDelay%d", i); + osti_sprintf(OBQueueInterruptCount,"OBQueueInterruptCount%d", i); + osti_sprintf(OBQueueInterruptEnable,"OBQueueInterruptEnable%d", i); + + /* + * read the OBQueueSize + */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + cardNum, /* key */ + SwParmsStr, /* subkey1 */ + OBQueueProps, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + OBQueueSize, /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->OutboundQueueSize[i] = (bit16) osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->OutboundQueueSize[i] = (bit16) osti_strtoul (buffer, &pLastUsedChar, 10); + TI_DBG6(("tdsaGetSwConfigParams: queue number %d OB queue size %d\n", i, tdsaAllShared->OutboundQueueSize[i])); + + } + } + + /* + * read the OBQueueEleSize + */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + + if ((ostiGetTransportParam( + tiRoot, + cardNum, /* key */ + SwParmsStr, /* subkey1 */ + OBQueueProps, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + OBQueueEleSize, /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->OutboundQueueEleSize[i] = (bit16) osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->OutboundQueueEleSize[i] = (bit16) osti_strtoul (buffer, &pLastUsedChar, 10); + TI_DBG6(("tdsaGetSwConfigParams: queue number %d OB queue ele size %d\n", i, tdsaAllShared->OutboundQueueEleSize[i])); + + } + } + + /* + * read the OBQueueInterruptDelay + */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + + if ((ostiGetTransportParam( + tiRoot, + cardNum, /* key */ + SwParmsStr, /* subkey1 */ + OBQueueProps, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + OBQueueInterruptDelay, /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->OutboundQueueInterruptDelay[i] = (bit16) osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->OutboundQueueInterruptDelay[i] = (bit16) osti_strtoul (buffer, &pLastUsedChar, 10); + TI_DBG6(("tdsaGetSwConfigParams: card number %s queue number %d interrupt delay %d\n", cardNum, i, tdsaAllShared->OutboundQueueInterruptDelay[i])); + + } + } + + /* + * read the OBQueueInterruptCount + */ + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + cardNum, /* key */ + SwParmsStr, /* subkey1 */ + OBQueueProps, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + OBQueueInterruptCount, /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->OutboundQueueInterruptCount[i] = (bit16) osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->OutboundQueueInterruptCount[i] = (bit16) osti_strtoul (buffer, &pLastUsedChar, 10); + TI_DBG6(("tdsaGetSwConfigParams: card number %s queue number %d interrupt count %d\n", cardNum, i, tdsaAllShared->OutboundQueueInterruptCount[i])); + } + } + + + /* + * read the OBQueueInterruptEnable + */ + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + cardNum, /* key */ + SwParmsStr, /* subkey1 */ + OBQueueProps, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + OBQueueInterruptEnable, /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->OutboundQueueInterruptEnable[i] = (bit16) osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->OutboundQueueInterruptEnable[i] = (bit16) osti_strtoul (buffer, &pLastUsedChar, 10); + TI_DBG6(("tdsaGetSwConfigParams: card number %s queue number %d interrupt enable %d\n", cardNum, i, tdsaAllShared->OutboundQueueInterruptEnable[i])); + } + } + + + /**********************************************/ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + }/* end of loop */ + + /* process event log related parameters */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "EventLogSize1", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + SwConfig->sizefEventLog1 = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + SwConfig->sizefEventLog1 = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "EventLogOption1", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + SwConfig->eventLog1Option = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + SwConfig->eventLog1Option = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "EventLogSize2", /* valueName *//* IOP size in K dWords */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + SwConfig->sizefEventLog2 = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + SwConfig->sizefEventLog2 = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "EventLogOption2", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + SwConfig->eventLog2Option = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + SwConfig->eventLog2Option = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + /* end of event log related parameters */ + + /* + HDA parameters + */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "HDASupport", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + SwConfig->hostDirectAccessSupport = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + SwConfig->hostDirectAccessSupport = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "HDAMode", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + SwConfig->hostDirectAccessMode = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + SwConfig->hostDirectAccessMode = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + /* the end of HDA parameters */ + + /* FW configuration */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "FWConfig", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + SwConfig->FWConfig = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + SwConfig->FWConfig = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + /* The end of FW configuration */ + + /* IQ Normal priority and High priority */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + IBQueueProps,/* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "IQNQDepth", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + QueueConfig->iqNormalPriorityProcessingDepth = (bit8) osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + QueueConfig->iqNormalPriorityProcessingDepth = (bit8) osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + IBQueueProps,/* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "IQHQDepth", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + QueueConfig->iqHighPriorityProcessingDepth = (bit8) osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + QueueConfig->iqHighPriorityProcessingDepth = (bit8) osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + /* End IQ Normal priority and High priority */ + + /* Start port timeout value */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL,/* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "PortTMO", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->portTMO = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->portTMO = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + /* End port timeout value */ + +#ifdef SA_ENABLE_TRACE_FUNCTIONS + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "TraceDestination", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + SwConfig->TraceDestination = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + SwConfig->TraceDestination = osti_strtoul (buffer, &pLastUsedChar, 10); + } + TI_DBG2(("tdsaGetSwConfigParams: SwConfig->TraceDestination %d\n",SwConfig->TraceDestination)); + } + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "TraceMask", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + SwConfig->TraceMask = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + SwConfig->TraceMask = osti_strtoul (buffer, &pLastUsedChar, 10); + } + TI_DBG2(("tdsaGetSwConfigParams: SwConfig->TraceMask %d %X\n",SwConfig->TraceMask,SwConfig->TraceMask)); + } +#endif /*# SA_ENABLE_TRACE_FUNCTIONS */ + +#ifdef AGTIAPI_CTL + /* + * read the SAS Connection Time Limit parameter + */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + tdsaAllShared->SASConnectTimeLimit = 0; + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "SASCTL", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + tdsaAllShared->SASConnectTimeLimit = osti_strtoul (buffer, &pLastUsedChar, 0); + else + tdsaAllShared->SASConnectTimeLimit = osti_strtoul (buffer, &pLastUsedChar, 10); + } +#endif + + /* Start FCA value */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + tdsaAllShared->FCA = 1; /* No FCA by default */ + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + "InitiatorParms", /* subkey1 */ + agNULL,/* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "FCA", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->FCA = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->FCA = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + /* End FCA value */ + + /* Start ResetInDiscovery value */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + tdsaAllShared->ResetInDiscovery = 0; /* No ResetInDiscovery by default */ + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + "InitiatorParms", /* subkey1 */ + agNULL,/* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "ResetInDiscovery", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->ResetInDiscovery = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->ResetInDiscovery = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + /* End ResetInDiscovery value */ + + /* Start MCN value */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + tdsaAllShared->MCN = 1; /* default MCN */ + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL,/* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "MCN", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->MCN = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->MCN = osti_strtoul (buffer, &pLastUsedChar, 10); + } + TI_DBG6(("tdsaGetSwConfigParams: MCN %d\n", tdsaAllShared->MCN)); + } + /* End MCN value */ + + /* Start sflag value */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + tdsaAllShared->sflag = 0; /* default sflag */ + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "Sflag", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->sflag = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->sflag = osti_strtoul (buffer, &pLastUsedChar, 10); + } + TI_DBG1(("tdsaGetSwConfigParams: sflag %d\n", tdsaAllShared->sflag)); + } + /* End sflag value */ + + /* Start enable DIF */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL,/* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "enableDIF", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + enableDIF = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + enableDIF = osti_strtoul (buffer, &pLastUsedChar, 10); + } + TI_DBG6(("tdsaGetSwConfigParams: enableDIF %d\n", enableDIF)); + if (enableDIF) + { + SwConfig->enableDIF = agTRUE; + } + else + { + SwConfig->enableDIF = agFALSE; + } + TI_DBG6(("tdsaGetSwConfigParams: SwConfig->enableDIF %d\n", SwConfig->enableDIF)); + } + /* End enable DIF */ + + + /* Start enable Encryption */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL,/* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "enableEncryption", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + enableEncryption = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + enableEncryption = osti_strtoul (buffer, &pLastUsedChar, 10); + } + TI_DBG6(("tdsaGetSwConfigParams: enableEncryption %d\n", enableEncryption)); + if (enableEncryption) + { + SwConfig->enableEncryption = agTRUE; + } + else + { + SwConfig->enableEncryption = agFALSE; + } + TI_DBG6(("tdsaGetSwConfigParams: SwConfig->enableEncryption %d\n", SwConfig->enableEncryption)); + } + /* End enable Encryption */ + + /* Start allow connection rate change */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + tdsaAllShared->RateAdjust = 0; /* No rate adjust by default */ + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL,/* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "RateAdjust", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->RateAdjust = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->RateAdjust = osti_strtoul (buffer, &pLastUsedChar, 10); + } + TI_DBG6(("tdsaGetSwConfigParams: tdsaAllShared->RateAdjust %d\n", tdsaAllShared->RateAdjust)); + } + /* End allow connection rate change */ + + +#ifdef SA_CONFIG_MDFD_REGISTRY + /* Start disable MDF */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL,/* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "disableMDF", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + disableMDF = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + disableMDF = osti_strtoul (buffer, &pLastUsedChar, 10); + } + TI_DBG6(("tdsaGetSwConfigParams: disableMDF %d\n", disableMDF)); + if (disableMDF) + { + SwConfig->disableMDF = agTRUE; + } + else + { + SwConfig->disableMDF = agFALSE; + } + TI_DBG6(("tdsaGetSwConfigParams: SwConfig->disableMDF %d\n", SwConfig->disableMDF)); + } + /* End disable MDF */ +#endif /*SA_CONFIG_MDFD_REGISTRY*/ + + /* Start IT_NEXUS_TIMEOUT */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL,/* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "IT_NEXUS_TIMEOUT", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->itNexusTimeout = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->itNexusTimeout = osti_strtoul (buffer, &pLastUsedChar, 10); + } + TI_DBG1(("tdsaGetSwConfigParams: tdsaAllShared->itNexusTimeout %d\n", tdsaAllShared->itNexusTimeout)); + } + /* End IT_NEXUS_TIMEOUT */ + + /* Start stp idle time */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL,/* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "STPIdleTime", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->stp_idle_time = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->stp_idle_time = osti_strtoul (buffer, &pLastUsedChar, 10); + } + TI_DBG2(("tdsaGetSwConfigParams: STPIdleTime %d\n", tdsaAllShared->stp_idle_time)); + } + /* End stp idle time */ + + /* Start STP_MCT_TMO */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + tdsaAllShared->STP_MCT_TMO = 32; + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL,/* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "SAS_STP_MCT_TMO", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->STP_MCT_TMO = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->STP_MCT_TMO = osti_strtoul (buffer, &pLastUsedChar, 10); + } + TI_DBG2(("tdsaGetSwConfigParams: STP_MCT_TMO %d\n", tdsaAllShared->STP_MCT_TMO)); + } + /* End STP_MCT_TMO */ + + /* Start SSP_MCT_TMO */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + tdsaAllShared->SSP_MCT_TMO = 32; + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL,/* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "SAS_SSP_MCT_TMO", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->SSP_MCT_TMO = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->SSP_MCT_TMO = osti_strtoul (buffer, &pLastUsedChar, 10); + } + TI_DBG2(("tdsaGetSwConfigParams: SSP_MCT_TMO %d\n", tdsaAllShared->SSP_MCT_TMO)); + } + /* End SSP_MCT_TMO */ + + + /* Start MAX_OPEN_TIME */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + tdsaAllShared->MAX_OPEN_TIME = 5; + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL,/* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "SAS_MAX_OPEN_TIME", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->MAX_OPEN_TIME = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->MAX_OPEN_TIME = osti_strtoul (buffer, &pLastUsedChar, 10); + } + TI_DBG2(("tdsaGetSwConfigParams: MAX_OPEN_TIME %d\n", tdsaAllShared->MAX_OPEN_TIME)); + } + /* End MAX_OPEN_TIME */ + + + /* Start SMP_MAX_CONN_TIMER */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + tdsaAllShared->SMP_MAX_CONN_TIMER = 0xFF; + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL,/* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "SAS_SMP_MAX_CONN_TIMER", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->SMP_MAX_CONN_TIMER = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->SMP_MAX_CONN_TIMER = osti_strtoul (buffer, &pLastUsedChar, 10); + } + TI_DBG2(("tdsaGetSwConfigParams: SMP_MAX_CONN_TIMER %d\n", tdsaAllShared->SMP_MAX_CONN_TIMER)); + } + /* End SMP_MAX_CONN_TIMER */ + + /* Start STP_FRM_TMO */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + tdsaAllShared->STP_FRM_TMO = 0; + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL,/* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "SAS_STP_FRM_TMO", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->STP_FRM_TMO = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->STP_FRM_TMO = osti_strtoul (buffer, &pLastUsedChar, 10); + } + TI_DBG2(("tdsaGetSwConfigParams: STP_FRM_TMO %d\n", tdsaAllShared->STP_FRM_TMO)); + } + /* End STP_FRM_TMO */ + + /* Start MFD_OPNRJT_RTRY_INTVL */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + tdsaAllShared->MFD = 1; /* disabled by default */ + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL,/* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "SAS_MFD", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->MFD = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->MFD = osti_strtoul (buffer, &pLastUsedChar, 10); + } + TI_DBG2(("tdsaGetSwConfigParams: MFD %d\n", tdsaAllShared->MFD)); + } + /* End MFD_OPNRJT_RTRY_INTVL */ + + /* Start MFD_OPNRJT_RTRY_INTVL */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + tdsaAllShared->OPNRJT_RTRY_INTVL = 2; + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL,/* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "SAS_OPNRJT_RTRY_INTVL", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->OPNRJT_RTRY_INTVL = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->OPNRJT_RTRY_INTVL = osti_strtoul (buffer, &pLastUsedChar, 10); + } + TI_DBG2(("tdsaGetSwConfigParams: OPNRJT_RTRY_INTVL %d\n", tdsaAllShared->OPNRJT_RTRY_INTVL)); + } + /* End MFD_OPNRJT_RTRY_INTVL */ + + /* Start DOPNRJT_RTRY_TMO */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + tdsaAllShared->DOPNRJT_RTRY_TMO = 128; + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL,/* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "SAS_DOPNRJT_RTRY_TMO", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->DOPNRJT_RTRY_TMO = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->DOPNRJT_RTRY_TMO = osti_strtoul (buffer, &pLastUsedChar, 10); + } + TI_DBG2(("tdsaGetSwConfigParams: DOPNRJT_RTRY_TMO %d\n", tdsaAllShared->DOPNRJT_RTRY_TMO)); + } + /* End DOPNRJT_RTRY_TMO */ + + /* Start COPNRJT_RTRY_TMO */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; +// tdsaAllShared->COPNRJT_RTRY_TMO = 32; + tdsaAllShared->COPNRJT_RTRY_TMO = 128; + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL,/* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "SAS_COPNRJT_RTRY_TMO", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->COPNRJT_RTRY_TMO = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->COPNRJT_RTRY_TMO = osti_strtoul (buffer, &pLastUsedChar, 10); + } + TI_DBG2(("tdsaGetSwConfigParams: COPNRJT_RTRY_TMO %d\n", tdsaAllShared->COPNRJT_RTRY_TMO)); + } + /* End COPNRJT_RTRY_TMO */ + + /* Start DOPNRJT_RTRY_THR */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; +// tdsaAllShared->DOPNRJT_RTRY_THR = 16; /* FW default */ + /* + Making ORR bigger than IT NEXUS LOSS which is 2000000us = 2 second. + Assuming a bigger value 3 second, 3000000/128 = 23437.5 where 128 is tdsaAllShared->DOPNRJT_RTRY_TMO + */ + tdsaAllShared->DOPNRJT_RTRY_THR = 23438; + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL,/* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "SAS_DOPNRJT_RTRY_THR", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->DOPNRJT_RTRY_THR = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->DOPNRJT_RTRY_THR = osti_strtoul (buffer, &pLastUsedChar, 10); + } + TI_DBG2(("tdsaGetSwConfigParams: DOPNRJT_RTRY_THR %d\n", tdsaAllShared->DOPNRJT_RTRY_THR)); + } + /* End DOPNRJT_RTRY_THR */ + + /* Start COPNRJT_RTRY_THR */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; +// tdsaAllShared->COPNRJT_RTRY_THR = 1024; /* FW default */ + /* + Making ORR bigger than IT NEXUS LOSS which is 2000000us = 2 second. + Assuming a bigger value 3 second, 3000000/128 = 23437.5 where 128 is tdsaAllShared->COPNRJT_RTRY_TMO + */ + tdsaAllShared->COPNRJT_RTRY_THR = 23438; + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL,/* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "SAS_COPNRJT_RTRY_THR", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->COPNRJT_RTRY_THR = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->COPNRJT_RTRY_THR = osti_strtoul (buffer, &pLastUsedChar, 10); + } + TI_DBG2(("tdsaGetSwConfigParams: COPNRJT_RTRY_THR %d\n", tdsaAllShared->COPNRJT_RTRY_THR)); + } + /* End COPNRJT_RTRY_THR */ + + /* Start MAX_AIP */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + tdsaAllShared->MAX_AIP = 0x200000; + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL,/* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "SAS_MAX_AIP", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->MAX_AIP = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->MAX_AIP = osti_strtoul (buffer, &pLastUsedChar, 10); + } + TI_DBG2(("tdsaGetSwConfigParams: MAX_AIP %d\n", tdsaAllShared->MAX_AIP)); + } + /* End MAX_AIP */ + + /***********************************************************************/ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + + /* + typedef struct agsaMPIContext_s + { + bit32 MPITableType; + bit32 offset; + bit32 value; + } agsaMPIContext_t; + */ + + { + bit32 MpiContextvalue = 0; + SwConfig->mpiContextTable = agNULL; + SwConfig->mpiContextTablelen = 0; + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "MpiContext", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + + if (osti_strncmp(buffer, "0x", 2) == 0) + { + MpiContextvalue = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + MpiContextvalue = osti_strtoul (buffer, &pLastUsedChar, 10); + } + + + if (MpiContextvalue == 0) + { + SwConfig->mpiContextTable = agNULL; + SwConfig->mpiContextTablelen = 0; + } + else + { + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *)tiRoot->tdData; + if(agNULL != tdsaRoot) + { + tdsaRoot->tdsaAllShared.MpiOverride.MPITableType = 0xFF; + tdsaRoot->tdsaAllShared.MpiOverride.offset = 0; + tdsaRoot->tdsaAllShared.MpiOverride.value = 0; + + SwConfig->mpiContextTable = &(tdsaRoot->tdsaAllShared.MpiOverride); + SwConfig->mpiContextTablelen = sizeof(agsaMPIContext_t); + } + + TI_DBG1(("tdsaGetSwConfigParams: MpiContext %p Len %d\n", SwConfig->mpiContextTable, SwConfig->mpiContextTablelen)); + + } + } + + if(SwConfig->mpiContextTable != agNULL ) + { + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *)tiRoot->tdData; + if(agNULL != tdsaRoot) + { + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "MpiTableType", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaRoot->tdsaAllShared.MpiOverride.MPITableType = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaRoot->tdsaAllShared.MpiOverride.MPITableType = osti_strtoul (buffer, &pLastUsedChar, 10); + } + TI_DBG1(("tdsaGetSwConfigParams: MpiOverride.MPITableType 0x%X\n",tdsaRoot->tdsaAllShared.MpiOverride.MPITableType )); + } + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "MpiTableOffset", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaRoot->tdsaAllShared.MpiOverride.offset = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaRoot->tdsaAllShared.MpiOverride.offset = osti_strtoul (buffer, &pLastUsedChar, 10); + } + + TI_DBG1(("tdsaGetSwConfigParams: MpiOverride.offset 0x%X\n",tdsaRoot->tdsaAllShared.MpiOverride.offset )); + } + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "MpiTableValue", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaRoot->tdsaAllShared.MpiOverride.value = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaRoot->tdsaAllShared.MpiOverride.value = osti_strtoul (buffer, &pLastUsedChar, 10); + } + TI_DBG1(("tdsaGetSwConfigParams: MpiOverride.value 0x%X\n",tdsaRoot->tdsaAllShared.MpiOverride.value )); + } + } + } + } + /***********************************************************************/ + +#ifdef SA_ENABLE_PCI_TRIGGER + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + SwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "PciTrigger", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + + if (osti_strncmp(buffer, "0x", 2) == 0) + { + SwConfig->PCI_trigger = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + SwConfig->PCI_trigger = osti_strtoul (buffer, &pLastUsedChar, 10); + } + TI_DBG1(("tdsaGetSwConfigParams: PciTrigger %d\n",SwConfig->PCI_trigger)); + } +#endif /* SA_ENABLE_PCI_TRIGGER */ + + + TI_DBG6(("tdsaGetSwConfigParams: $$$$$$$$$$$$$$$$$ merge $$$$$$$$$$$$$\n")); +#if defined(SALLSDK_DEBUG) + TI_DBG2(("tdsaGetSwConfigParams: SwConfig->sallDebugLevel %d\n", SwConfig->sallDebugLevel)); +#endif + +#ifdef SA_ENABLE_PCI_TRIGGER + TI_DBG1(("tdsaGetSwConfigParams: SwConfig->PCI_trigger 0x%x 0x%x\n",SwConfig->PCI_trigger, tdsaRoot->itdsaIni->tdsaAllShared->SwConfig.PCI_trigger)); +#endif /* SA_ENABLE_PCI_TRIGGER */ + + +#ifdef AGTIAPI_CTL + TI_DBG6(("tdsaLoLevelGetResource: SASConnectTimeLimit 0x%x\n", + tdsaAllShared->SASConnectTimeLimit)); +#endif + + return; +} + +/***************************************************************************** +*! \brief tdsaParseLinkRateMode +* +* Purpose: This function parses link rate and mode. +* +* \param LinkRate: Link rate specified by user. +* \param Mode: Link rate specified by user. +* +* \return: +* Value combined with Linkrate and Mode +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaParseLinkRateMode( + tiRoot_t *tiRoot, + bit32 index, + bit32 LinkRateRead, + bit32 ModeRead, + bit32 OpticalModeRead, + bit32 LinkRate, + bit32 Mode, + bit32 OpticalMode + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&(tdsaRoot->tdsaAllShared); + + TI_DBG3(("tdsaParseLinkRateMode: index 0x%X\n",index)); + TI_DBG3(("tdsaParseLinkRateMode: LinkRateRead 0x%X LinkRate 0x%X\n",LinkRateRead,LinkRate)); + TI_DBG3(("tdsaParseLinkRateMode: ModeRead 0x%X Mode 0x%X\n",ModeRead,Mode)); + TI_DBG3(("tdsaParseLinkRateMode: OpticalModeRead 0x%X OpticalMode 0x%X\n",OpticalModeRead,OpticalMode)); + + + if (LinkRateRead == agTRUE) + { + /* link rate */ + if (LinkRate & 0x1) + { + tdsaAllShared->Ports[index].agPhyConfig.phyProperties = tdsaAllShared->Ports[index].agPhyConfig.phyProperties | 0x1; + } + if (LinkRate & 0x2) + { + tdsaAllShared->Ports[index].agPhyConfig.phyProperties = tdsaAllShared->Ports[index].agPhyConfig.phyProperties | 0x2; + } + if (LinkRate & 0x4) + { + tdsaAllShared->Ports[index].agPhyConfig.phyProperties = tdsaAllShared->Ports[index].agPhyConfig.phyProperties | 0x4; + } + if (LinkRate & 0x8) + { + tdsaAllShared->Ports[index].agPhyConfig.phyProperties = tdsaAllShared->Ports[index].agPhyConfig.phyProperties | 0x8; + } + if (LinkRate == 0 || LinkRate > 0xF ) + { + /* not allowed, set the rate to default 1.5 G */ + tdsaAllShared->Ports[index].agPhyConfig.phyProperties = 0; + tdsaAllShared->Ports[index].agPhyConfig.phyProperties = tdsaAllShared->Ports[index].agPhyConfig.phyProperties | 0x1; + TI_DBG1(("tdsaParseLinkRateMode: LinkRate == 0 || LinkRate >= 0x%x\n",tdsaAllShared->Ports[index].agPhyConfig.phyProperties)); + } + TI_DBG2(("tdsaParseLinkRateMode:A index 0x%x LinkRate 0x%x Mode 0x%x\n",index,LinkRate,Mode)); + + } + + if ( ModeRead == agTRUE) + { + /* mode */ + if (Mode & 0x1) + { + tdsaAllShared->Ports[index].agPhyConfig.phyProperties = tdsaAllShared->Ports[index].agPhyConfig.phyProperties | 0x10; + } + if (Mode & 0x2) + { + tdsaAllShared->Ports[index].agPhyConfig.phyProperties = tdsaAllShared->Ports[index].agPhyConfig.phyProperties | 0x20; + } + if (Mode == 0 || Mode >= 4 ) + { + /* not allowed, set the mode to default SAS/SATA */ + tdsaAllShared->Ports[index].agPhyConfig.phyProperties = tdsaAllShared->Ports[index].agPhyConfig.phyProperties & 0xf; + tdsaAllShared->Ports[index].agPhyConfig.phyProperties = tdsaAllShared->Ports[index].agPhyConfig.phyProperties | 0x30; + } + TI_DBG2(("tdsaParseLinkRateMode:1 index 0x%x Mode 0x%x\n",index,tdsaAllShared->Ports[index].agPhyConfig.phyProperties)); + } + + if ( OpticalModeRead == agTRUE) + { + /* setting bit20 */ + agsaRoot_t *agRoot = &tdsaAllShared->agRootInt; + + if (OpticalMode == 0) + { + TI_DBG1(("tdsaParseLinkRateMode: OpticalMode 0 phy %d phyProperties 0x%x\n",index,tdsaAllShared->Ports[index].agPhyConfig.phyProperties)); + } + else if(OpticalMode == 1) + { + if(tIsSPCV12or6G(agRoot)) + { + TI_DBG1(("tdsaParseLinkRateMode: OpticalMode 1 phy %d phyProperties 0x%x\n",index,tdsaAllShared->Ports[index].agPhyConfig.phyProperties)); + tdsaAllShared->Ports[index].agPhyConfig.phyProperties = tdsaAllShared->Ports[index].agPhyConfig.phyProperties | (1 << 22); + } + else + { + tdsaAllShared->Ports[index].agPhyConfig.phyProperties = tdsaAllShared->Ports[index].agPhyConfig.phyProperties | (1 << 22); + tdsaAllShared->Ports[index].agPhyConfig.phyProperties &= 0xFFFFFFF0; + tdsaAllShared->Ports[index].agPhyConfig.phyProperties |= 0x4; + } + } + else if(OpticalMode == 2 ) + { + if(tIsSPCV12or6G(agRoot)) + { + TI_DBG1(("tdsaParseLinkRateMode: OpticalMode 2 phy %d phyProperties 0x%x\n",index,tdsaAllShared->Ports[index].agPhyConfig.phyProperties)); + tdsaAllShared->Ports[index].agPhyConfig.phyProperties = tdsaAllShared->Ports[index].agPhyConfig.phyProperties | (1 << 20); + } + else + { + TD_ASSERT(0, "SPC optical mode 2"); + } + + TI_DBG1(("tdsaParseLinkRateMode: OpticalMode %d phy %d phyProperties 0x%x\n",OpticalMode,index,tdsaAllShared->Ports[index].agPhyConfig.phyProperties)); + } + else + { + TI_DBG1(("tdsaParseLinkRateMode: OpticalMode unknown %d phy %d phyProperties 0x%x\n",OpticalMode,index,tdsaAllShared->Ports[index].agPhyConfig.phyProperties)); + } + } + else + { + TI_DBG1(("tdsaParseLinkRateMode: OpticalMode off phy %d phyProperties 0x%x\n",index,tdsaAllShared->Ports[index].agPhyConfig.phyProperties)); + } + + TI_DBG1(("tdsaParseLinkRateMode: phy %d phyProperties 0x%x\n",index,tdsaAllShared->Ports[index].agPhyConfig.phyProperties)); + + + return; +} + + +/***************************************************************************** +*! \brief tdsaGetHwConfigParams +* +* Purpose: This function reads hardware configuration parameters from the +* configuration file +* +* \param tiRoot: Pointer to driver/port instance. +* +* \return: None +* +* \note - +* +*****************************************************************************/ +osGLOBAL void +tdsaGetHwConfigParams( + tiRoot_t *tiRoot + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&(tdsaRoot->tdsaAllShared); + agsaHwConfig_t *HwConfig; + char *buffer; + bit32 buffLen; + bit32 lenRecv = 0; + char *pLastUsedChar = agNULL; + char tmpBuffer[DEFAULT_KEY_BUFFER_SIZE]; + char globalStr[] = "Global"; + char HwParmsStr[] = "HWParms"; + char phyReg[10]; + int i,j; + agsaPhyAnalogSetupTable_t *phyRegTable; + + TI_DBG6(("tdsaGetHwConfigParams: start\n")); + TI_DBG6(("tdsaGetHwConfigParams: tdsaRoot %p tdsaAllShared %p \n",tdsaRoot, tdsaAllShared)); + + buffer = tmpBuffer; + buffLen = sizeof(tmpBuffer); + + osti_memset(buffer, 0, buffLen); + + HwConfig = (agsaHwConfig_t *)&(tdsaAllShared->HwConfig); + phyRegTable = (agsaPhyAnalogSetupTable_t *)&(HwConfig->phyAnalogConfig); + + osti_memset(HwConfig, 0, sizeof(agsaHwConfig_t)); + + /* + just default values + and are overwritten later by the configuration file contents + turning off hw control interrupt coalescing + */ + tdsaAllShared->FWMaxPorts = DEFAULT_FW_MAX_PORTS; /* 8, applicable only to SPC not to SPCv */ + HwConfig->phyCount = TD_MAX_NUM_PHYS; + HwConfig->hwInterruptCoalescingTimer = 1; + HwConfig->hwInterruptCoalescingControl = 0; + tdsaAllShared->phyCalibration = 0; + HwConfig->hwOption = 0; /* default: PI/CI addresses are 32-bit */ + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + HwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "HwIntCoalTimer", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + HwConfig->hwInterruptCoalescingTimer = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + HwConfig->hwInterruptCoalescingTimer = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + HwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "HwIntCoalControl", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + HwConfig->hwInterruptCoalescingControl = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + HwConfig->hwInterruptCoalescingControl = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + + /* For hwInterruptCoalescingTimer, 0 disables interrrupt, not allowed */ + if (HwConfig->hwInterruptCoalescingControl == 1 && HwConfig->hwInterruptCoalescingTimer == 0) + { + HwConfig->hwInterruptCoalescingTimer = 1; + } + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + /* interrupt reassetion field*/ + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + HwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "IntReassertionOpt", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + HwConfig->intReassertionOption = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + HwConfig->intReassertionOption = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + /* interrupt reassetion field*/ + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + HwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "HwOption", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + HwConfig->hwOption = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + HwConfig->hwOption = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + /* interrupt reassetion field*/ + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + HwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "MaxFWPorts", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->FWMaxPorts = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->FWMaxPorts = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + HwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + "phyCalibration", /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->phyCalibration = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->phyCalibration = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + + /* phy calibration */ + for (i=0;iphyAnalogSetupRegisters[i].spaRegister0 = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + phyRegTable->phyAnalogSetupRegisters[i].spaRegister0 = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + } + else if (j == 1) + { + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + HwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + phyReg, /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + phyRegTable->phyAnalogSetupRegisters[i].spaRegister1 = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + phyRegTable->phyAnalogSetupRegisters[i].spaRegister1 = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + } + else if (j == 2) + { + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + HwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + phyReg, /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + phyRegTable->phyAnalogSetupRegisters[i].spaRegister2 = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + phyRegTable->phyAnalogSetupRegisters[i].spaRegister2 = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + } + else if (j == 3) + { + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + HwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + phyReg, /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + phyRegTable->phyAnalogSetupRegisters[i].spaRegister3 = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + phyRegTable->phyAnalogSetupRegisters[i].spaRegister3 = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + } + else if (j == 4) + { + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + HwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + phyReg, /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + phyRegTable->phyAnalogSetupRegisters[i].spaRegister4 = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + phyRegTable->phyAnalogSetupRegisters[i].spaRegister4 = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + } + else if (j == 5) + { + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + HwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + phyReg, /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + phyRegTable->phyAnalogSetupRegisters[i].spaRegister5 = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + phyRegTable->phyAnalogSetupRegisters[i].spaRegister5 = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + } + else if (j == 6) + { + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + HwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + phyReg, /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + phyRegTable->phyAnalogSetupRegisters[i].spaRegister6 = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + phyRegTable->phyAnalogSetupRegisters[i].spaRegister6 = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + } + else if (j == 7) + { + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + HwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + phyReg, /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + phyRegTable->phyAnalogSetupRegisters[i].spaRegister7 = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + phyRegTable->phyAnalogSetupRegisters[i].spaRegister7 = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + } + else if (j == 8) + { + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + HwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + phyReg, /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + phyRegTable->phyAnalogSetupRegisters[i].spaRegister8 = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + phyRegTable->phyAnalogSetupRegisters[i].spaRegister8 = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + } + else if (j == 9) + { + if ((ostiGetTransportParam( + tiRoot, + globalStr, /* key */ + HwParmsStr, /* subkey1 */ + agNULL, /* subkey2 */ + agNULL, + agNULL, + agNULL, /* subkey5 */ + phyReg, /* valueName */ + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + phyRegTable->phyAnalogSetupRegisters[i].spaRegister9 = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + phyRegTable->phyAnalogSetupRegisters[i].spaRegister9 = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + } + + } /* inner loop */ + } /* outer loop */ + return; +} +/***************************************************************************** +*! \brief tdsaGetCardPhyParams +* +* Purpose: This function reads phy-related configuration parameters from the +* configuration file +* +* \param tiRoot: Pointer to driver/port instance. +* +* \return: None +* +* \note - just a place holder for now +* +*****************************************************************************/ +osGLOBAL void +tdsaGetCardPhyParams( + tiRoot_t *tiRoot + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&(tdsaRoot->tdsaAllShared); + agsaRoot_t *agRoot = &tdsaAllShared->agRootInt; + char *buffer; + bit32 buffLen; + bit32 lenRecv = 0; + char *pLastUsedChar = agNULL; + char tmpBuffer[DEFAULT_KEY_BUFFER_SIZE]; + char *globalStr = tdsaAllShared->CardIDString; + char phyParmsStr[12]; + int i; + bit32 LinkRate = 15, Mode = 3, OpticalMode = 0; //VG + bit32 LinkRateRead = agTRUE, ModeRead = agFALSE, OpticalModeRead = agFALSE; + bit32 flag = agFALSE; /* true only for PM8008 or PM8009 (SPCv and SPCve) controller */ + + TI_DBG6(("tdsaGetCardPhyParams: start \n")); + TI_DBG6(("tdsaGetCardPhyParams: tdsaRoot %p tdsaAllShared %p \n", tdsaRoot,tdsaAllShared)); + + if (tiIS_8PHY(agRoot)) + { + TI_DBG6(("tdsaGetCardPhyParams: SPCv or SPCve \n")); + flag = agTRUE; + } + TI_DBG6(("tdsaGetCardPhyParams: flag %d\n", flag)); + +#ifdef REMOVED +#ifdef FPGA_CARD + for (i=0;iPorts[i].SASID.sasAddressHi, 0, 0x01020304); + OSSA_WRITE_BE_32(agRoot, tdsaAllShared->Ports[i].SASID.sasAddressLo, 0, 0x05060708); + /* 1.5G only, SAS/SATA, no spin-up control */ + tdsaAllShared->Ports[i].agPhyConfig.phyProperties = 0x31; /* 49 */ + } +#else +#ifdef INITIATOR_DRIVER + /* ASIC */ + for (i=0;iPorts[i].SASID.sasAddressHi, 0, 0x01020304); + OSSA_WRITE_BE_32(agRoot, tdsaAllShared->Ports[i].SASID.sasAddressLo, 0, 0x05060708); + /* 1.5G/3G , SAS/SATA, no spin-up control */ + tdsaAllShared->Ports[i].agPhyConfig.phyProperties = 0x37; /* 55 */ + TI_DBG6(("tdsaGetCardPhyParams: phy %d hi 0x%x lo 0x%x\n", i, SA_IDFRM_GET_SAS_ADDRESSHI(&(tdsaAllShared->Ports[i].SASID)), SA_IDFRM_GET_SAS_ADDRESSLO(&(tdsaAllShared->Ports[i].SASID)))); + } +#endif + +#ifdef TARGET_DRIVER + /* ASIC */ + for (i=0;iPorts[i].SASID.sasAddressHi, 0, 0x01020304); + OSSA_WRITE_BE_32(agRoot, tdsaAllShared->Ports[i].SASID.sasAddressLo, 0, 0x05050500+i); + /* 1.5G/3G , SAS/SATA, no spin-up control */ + tdsaAllShared->Ports[i].agPhyConfig.phyProperties = 0x37; /* 55 */ + TI_DBG6(("tdsaGetCardPhyParams: phy %d hi 0x%x lo 0x%x\n", i, SA_IDFRM_GET_SAS_ADDRESSHI(&(tdsaAllShared->Ports[i].SASID)), SA_IDFRM_GET_SAS_ADDRESSLO(&(tdsaAllShared->Ports[i].SASID)))); + } +#endif + +#endif +#endif /* REMOVED */ + + + buffer = tmpBuffer; + buffLen = sizeof(tmpBuffer); + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + for (i=0;i= 4) + { + osti_sprintf(phyParmsStr,"PhyParms%d", i+4); + } + else + { + osti_sprintf(phyParmsStr,"PhyParms%d", i); + } + } + + TI_DBG6(("tdsaGetCardPhyParams: i %d PhyParms %s\n", i, phyParmsStr)); + + TI_DBG2(("tdsaGetCardPhyParams: phy %d phyProperties %d\n", i, tdsaAllShared->Ports[i].agPhyConfig.phyProperties)); + + + if ((ostiGetTransportParam ( + tiRoot, + globalStr, + phyParmsStr, + agNULL, + agNULL, + agNULL, + agNULL, + "AddrHi", + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + OSSA_WRITE_BE_32(agRoot, tdsaAllShared->Ports[i].SASID.sasAddressHi, 0, osti_strtoul(buffer, &pLastUsedChar, 0)); + TI_DBG6(("tdsaGetCardPhyParams: phy %d hi 0x%x \n", i, SA_IDFRM_GET_SAS_ADDRESSHI(&(tdsaAllShared->Ports[i].SASID)))); + } + else + { + OSSA_WRITE_BE_32(agRoot, tdsaAllShared->Ports[i].SASID.sasAddressHi, 0, osti_strtoul(buffer, &pLastUsedChar, 10)); + TI_DBG6(("tdsaGetCardPhyParams: phy %d hi %d \n", i, SA_IDFRM_GET_SAS_ADDRESSHI(&(tdsaAllShared->Ports[i].SASID)))); + } + } + + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam ( + tiRoot, + globalStr, + phyParmsStr, + agNULL, + agNULL, + agNULL, + agNULL, + "AddrLow", + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + OSSA_WRITE_BE_32(agRoot, tdsaAllShared->Ports[i].SASID.sasAddressLo, 0, osti_strtoul(buffer, &pLastUsedChar, 0)); + TI_DBG6(("tdsaGetCardPhyParams: phy %d lo 0x%x\n", i, SA_IDFRM_GET_SAS_ADDRESSLO(&(tdsaAllShared->Ports[i].SASID)))); + } + else + { + OSSA_WRITE_BE_32(agRoot, tdsaAllShared->Ports[i].SASID.sasAddressLo, 0, osti_strtoul(buffer, &pLastUsedChar, 10)); + TI_DBG6(("tdsaGetCardPhyParams: phy %d lo %d\n", i, SA_IDFRM_GET_SAS_ADDRESSLO(&(tdsaAllShared->Ports[i].SASID)))); + } + } + TI_DBG6(("tdsaGetCardPhyParams: loop phy %d hi 0x%x lo 0x%x\n", i, SA_IDFRM_GET_SAS_ADDRESSHI(&(tdsaAllShared->Ports[i].SASID)), SA_IDFRM_GET_SAS_ADDRESSLO(&(tdsaAllShared->Ports[i].SASID)))); + + /* phy properties */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; +/* + if ((ostiGetTransportParam ( + tiRoot, + globalStr, + phyParmsStr, + agNULL, + agNULL, + agNULL, + agNULL, + "LinkRate", + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + LinkRateRead = agTRUE; + if (osti_strncmp(buffer, "0x", 2) == 0) + { + LinkRate = osti_strtoul(buffer, &pLastUsedChar, 0); + TI_DBG6(("tdsaGetCardPhyParams: phy %d linkrate 0x%x \n", i, LinkRate)); + } + else + { + LinkRate = osti_strtoul(buffer, &pLastUsedChar, 10); + TI_DBG6(("tdsaGetCardPhyParams: phy %d linkrate %d \n", i, LinkRate)); + } + } + + TI_DBG2(("tdsaGetCardPhyParams: phy %d linkrate %d \n", i, LinkRate)); +*/ + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam ( + tiRoot, + globalStr, + phyParmsStr, + agNULL, + agNULL, + agNULL, + agNULL, + "Mode", + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + ModeRead = agTRUE; + if (osti_strncmp(buffer, "0x", 2) == 0) + { + Mode = osti_strtoul(buffer, &pLastUsedChar, 0); + TI_DBG6(("tdsaGetCardPhyParams: phy %d Mode 0x%x \n", i, Mode)); + } + else + { + Mode = osti_strtoul(buffer, &pLastUsedChar, 10); + TI_DBG6(("tdsaGetCardPhyParams: phy %d Mode %d \n", i, Mode)); + } + } + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam ( + tiRoot, + globalStr, + phyParmsStr, + agNULL, + agNULL, + agNULL, + agNULL, + "OpticalMode", + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + OpticalModeRead = agTRUE; + if (osti_strncmp(buffer, "0x", 2) == 0) + { + OpticalMode = osti_strtoul(buffer, &pLastUsedChar, 0); + TI_DBG6(("tdsaGetCardPhyParams: phy %d OpticalMode 0x%x \n", i, OpticalMode)); + } + else + { + OpticalMode = osti_strtoul(buffer, &pLastUsedChar, 10); + TI_DBG6(("tdsaGetCardPhyParams: phy %d OpticalMode %d \n", i, OpticalMode)); + } + } + + tdsaParseLinkRateMode(tiRoot, i, LinkRateRead, ModeRead, OpticalModeRead, LinkRate, Mode, OpticalMode); + + TI_DBG2(("tdsaGetCardPhyParams: phy %d phyProperties %d\n", i, tdsaAllShared->Ports[i].agPhyConfig.phyProperties)); + + + /**********************************************/ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + LinkRateRead = agTRUE;//VG + ModeRead = agFALSE; + OpticalModeRead = agFALSE; + + } /* end for */ + return; +} + + + + + +/***************************************************************************** +*! \brief tdsaGetGlobalPhyParams +* +* Purpose: This function reads phy-related configuration parameters from the +* configuration file +* +* \param tiRoot: Pointer to driver/port instance. +* +* \return: None +* +* \note - just a place holder for now +* +*****************************************************************************/ +osGLOBAL void +tdsaGetGlobalPhyParams( + tiRoot_t *tiRoot + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&(tdsaRoot->tdsaAllShared); + agsaRoot_t *agRoot = &tdsaAllShared->agRootInt; + char *buffer; + bit32 buffLen; + bit32 lenRecv = 0; + char *pLastUsedChar = agNULL; + char tmpBuffer[DEFAULT_KEY_BUFFER_SIZE]; + char globalStr[] = "Global"; + char phyParmsStr[12]; + int i; + bit32 LinkRate = 15/*7*/, Mode = 3, OpticalMode = 0; + bit32 LinkRateRead = agFALSE, ModeRead = agFALSE, OpticalModeRead = agFALSE; + bit32 flag = agFALSE; /* true only for PM8008 or PM8009 (SPCv and SPCve) controller */ + + TI_DBG6(("tdsaGetGlobalPhyParams: start \n")); + TI_DBG6(("tdsaGetGlobalPhyParams: tdsaRoot %p tdsaAllShared %p \n", tdsaRoot,tdsaAllShared)); + + if (tiIS_8PHY(agRoot) ) + { + TI_DBG6(("tdsaGetGlobalPhyParams: SPCv or SPCve \n")); + flag = agTRUE; + } + + TI_DBG6(("tdsaGetGlobalPhyParams: flag %d\n", flag)); + +#ifdef FPGA_CARD + for (i=0;iPorts[i].SASID.sasAddressHi, 0, 0x01020304); + OSSA_WRITE_BE_32(agRoot, tdsaAllShared->Ports[i].SASID.sasAddressLo, 0, 0x05060708); + /* 1.5G only, SAS/SATA, no spin-up control */ + tdsaAllShared->Ports[i].agPhyConfig.phyProperties = 0x31; /* 49 */ + } +#else + /* ASIC */ +#ifdef INITIATOR_DRIVER + for (i=0;iPorts[i].SASID.sasAddressHi, 0, 0x01020304); + OSSA_WRITE_BE_32(agRoot, tdsaAllShared->Ports[i].SASID.sasAddressLo, 0, 0x05060708); + } + else + { + OSSA_WRITE_BE_32(agRoot, tdsaAllShared->Ports[i].SASID.sasAddressHi, 0, 0x01010101); + OSSA_WRITE_BE_32(agRoot, tdsaAllShared->Ports[i].SASID.sasAddressLo, 0, 0x02020202); + } + } + else /* SPCv or SPCve */ + { + if (0 <= i && i <= 3) + { + OSSA_WRITE_BE_32(agRoot, tdsaAllShared->Ports[i].SASID.sasAddressHi, 0, 0x01020304); + OSSA_WRITE_BE_32(agRoot, tdsaAllShared->Ports[i].SASID.sasAddressLo, 0, 0x05060708); + } + else if (4 <= i && i <= 7) + { + OSSA_WRITE_BE_32(agRoot, tdsaAllShared->Ports[i].SASID.sasAddressHi, 0, 0x01020304); + OSSA_WRITE_BE_32(agRoot, tdsaAllShared->Ports[i].SASID.sasAddressLo, 0, 0x02020202); + } + else /* don't care */ + { + OSSA_WRITE_BE_32(agRoot, tdsaAllShared->Ports[i].SASID.sasAddressHi, 0, 0x01010101); + OSSA_WRITE_BE_32(agRoot, tdsaAllShared->Ports[i].SASID.sasAddressLo, 0, 0x0f0f0f0f); + } + + } + /* 1.5G/3G , SAS/SATA, no spin-up control */ + tdsaAllShared->Ports[i].agPhyConfig.phyProperties = 0x31; /* 55 */ + TI_DBG6(("tdsaGetGlobalPhyParams: phy %d hi 0x%x lo 0x%x\n", i, SA_IDFRM_GET_SAS_ADDRESSHI(&(tdsaAllShared->Ports[i].SASID)), SA_IDFRM_GET_SAS_ADDRESSLO(&(tdsaAllShared->Ports[i].SASID)))); + + } +#endif +#ifdef TARGET_DRIVER + for (i=0;iPorts[i].SASID.sasAddressHi, 0, 0x01020304); + OSSA_WRITE_BE_32(agRoot, tdsaAllShared->Ports[i].SASID.sasAddressLo, 0, 0x05050500+i); + } + else + { + OSSA_WRITE_BE_32(agRoot, tdsaAllShared->Ports[i].SASID.sasAddressHi, 0, 0x01020304); + OSSA_WRITE_BE_32(agRoot, tdsaAllShared->Ports[i].SASID.sasAddressLo, 0, 0x06060600+i); + } + } + else if (tiIS_16PHY(agRoot)) + { + if (0 <= i && i <= 7) + { + OSSA_WRITE_BE_32(agRoot, tdsaAllShared->Ports[i].SASID.sasAddressHi, 0, 0x01020304); + OSSA_WRITE_BE_32(agRoot, tdsaAllShared->Ports[i].SASID.sasAddressLo, 0, 0x05050500+i); + } + else + { + OSSA_WRITE_BE_32(agRoot, tdsaAllShared->Ports[i].SASID.sasAddressHi, 0, 0x01020304); + OSSA_WRITE_BE_32(agRoot, tdsaAllShared->Ports[i].SASID.sasAddressLo, 0, 0x06060600+i); + } + } + else + { + if (0 <= i && i <= 3) + { + OSSA_WRITE_BE_32(agRoot, tdsaAllShared->Ports[i].SASID.sasAddressHi, 0, 0x01020304); + OSSA_WRITE_BE_32(agRoot, tdsaAllShared->Ports[i].SASID.sasAddressLo, 0, 0x05050500+i); + } + else if (4 <= i && i <= 7) + { + OSSA_WRITE_BE_32(agRoot, tdsaAllShared->Ports[i].SASID.sasAddressHi, 0, 0x01020304); + OSSA_WRITE_BE_32(agRoot, tdsaAllShared->Ports[i].SASID.sasAddressLo, 0, 0x06060600+i); + } + else /* don't care */ + { + OSSA_WRITE_BE_32(agRoot, tdsaAllShared->Ports[i].SASID.sasAddressHi, 0, 0x01020304); + OSSA_WRITE_BE_32(agRoot, tdsaAllShared->Ports[i].SASID.sasAddressLo, 0, 0x0f0f0f0f+i); + } + } + /* 1.5G/3G , SAS/SATA, no spin-up control */ + tdsaAllShared->Ports[i].agPhyConfig.phyProperties = 0x31; /* 49 The default is 1.5G and will be changed based on the registry value */ + TI_DBG6(("tdsaGetGlobalPhyParams: phy %d hi 0x%x lo 0x%x\n", i, SA_IDFRM_GET_SAS_ADDRESSHI(&(tdsaAllShared->Ports[i].SASID)), SA_IDFRM_GET_SAS_ADDRESSLO(&(tdsaAllShared->Ports[i].SASID)))); + + } +#endif +#endif + + + buffer = tmpBuffer; + buffLen = sizeof(tmpBuffer); + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + /* needs to read Phy's id frame */ + for (i=0;i= 4) + { + osti_sprintf(phyParmsStr,"PhyParms%d", i+4); + } + else + { + osti_sprintf(phyParmsStr,"PhyParms%d", i); + } + } + + TI_DBG6(("tdsaGetGlobalPhyParams: i %d PhyParms %s\n", i, phyParmsStr)); + + + if ((ostiGetTransportParam ( + tiRoot, + globalStr, + phyParmsStr, + agNULL, + agNULL, + agNULL, + agNULL, + "AddrHi", + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + OSSA_WRITE_BE_32(agRoot, tdsaAllShared->Ports[i].SASID.sasAddressHi, 0, osti_strtoul(buffer, &pLastUsedChar, 0)); + TI_DBG6(("tdsaGetGlobalPhyParams: phy %d hi 0x%x \n", i, SA_IDFRM_GET_SAS_ADDRESSHI(&(tdsaAllShared->Ports[i].SASID)))); + } + else + { + OSSA_WRITE_BE_32(agRoot, tdsaAllShared->Ports[i].SASID.sasAddressHi, 0, osti_strtoul(buffer, &pLastUsedChar, 10)); + TI_DBG6(("tdsaGetGlobalPhyParams: phy %d hi %d \n", i, SA_IDFRM_GET_SAS_ADDRESSHI(&(tdsaAllShared->Ports[i].SASID)))); + + } + } + + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam ( + tiRoot, + globalStr, + phyParmsStr, + agNULL, + agNULL, + agNULL, + agNULL, + "AddrLow", + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + OSSA_WRITE_BE_32(agRoot, tdsaAllShared->Ports[i].SASID.sasAddressLo, 0, osti_strtoul(buffer, &pLastUsedChar, 0)); + TI_DBG6(("tdsaGetGlobalPhyParams: phy %d lo 0x%x\n", i, SA_IDFRM_GET_SAS_ADDRESSLO(&(tdsaAllShared->Ports[i].SASID)))); + } + else + { + OSSA_WRITE_BE_32(agRoot, tdsaAllShared->Ports[i].SASID.sasAddressLo, 0, osti_strtoul(buffer, &pLastUsedChar, 10)); + TI_DBG6(("tdsaGetGlobalPhyParams: phy %d lo %d\n", i, SA_IDFRM_GET_SAS_ADDRESSLO(&(tdsaAllShared->Ports[i].SASID)))); + + } + } + TI_DBG6(("tdsaGetGlobalPhyParams: loop phy %d hi 0x%x lo 0x%x\n", i, SA_IDFRM_GET_SAS_ADDRESSHI(&(tdsaAllShared->Ports[i].SASID)), SA_IDFRM_GET_SAS_ADDRESSLO(&(tdsaAllShared->Ports[i].SASID)))); + + /* phy properties */ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; +/* + if ((ostiGetTransportParam ( + tiRoot, + globalStr, + phyParmsStr, + agNULL, + agNULL, + agNULL, + agNULL, + "LinkRate", + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + LinkRateRead = agTRUE; + if (osti_strncmp(buffer, "0x", 2) == 0) + { + LinkRate = osti_strtoul(buffer, &pLastUsedChar, 0); + TI_DBG2(("tdsaGetGlobalPhyParams: phy %d linkrate 0x%x \n", i, LinkRate)); + } + else + { + LinkRate = osti_strtoul(buffer, &pLastUsedChar, 10); + TI_DBG2(("tdsaGetGlobalPhyParams: phy %d linkrate %d \n", i, LinkRate)); + } + } +*/ + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam ( + tiRoot, + globalStr, + phyParmsStr, + agNULL, + agNULL, + agNULL, + agNULL, + "Mode", + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + ModeRead = agTRUE; + if (osti_strncmp(buffer, "0x", 2) == 0) + { + Mode = osti_strtoul(buffer, &pLastUsedChar, 0); + TI_DBG2(("tdsaGetGlobalPhyParams: phy %d Mode 0x%x \n", i, Mode)); + } + else + { + Mode = osti_strtoul(buffer, &pLastUsedChar, 10); + TI_DBG2(("tdsaGetGlobalPhyParams: phy %d Mode %d \n", i, Mode)); + } + } + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + if ((ostiGetTransportParam ( + tiRoot, + globalStr, + phyParmsStr, + agNULL, + agNULL, + agNULL, + agNULL, + "OpticalMode", + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + OpticalModeRead = agTRUE; + if (osti_strncmp(buffer, "0x", 2) == 0) + { + OpticalMode = osti_strtoul(buffer, &pLastUsedChar, 0); + TI_DBG2(("tdsaGetGlobalPhyParams: phy %d OpticalMode 0x%x \n", i, OpticalMode)); + } + else + { + OpticalMode = osti_strtoul(buffer, &pLastUsedChar, 10); + TI_DBG2(("tdsaGetGlobalPhyParams: phy %d OpticalMode %d \n", i, OpticalMode)); + } + } + + TI_DBG2(("tdsaGetGlobalPhyParams:A phy %d phyProperties %d\n", i, tdsaAllShared->Ports[i].agPhyConfig.phyProperties)); + tdsaParseLinkRateMode(tiRoot, i, LinkRateRead, ModeRead, OpticalModeRead, LinkRate, Mode, OpticalMode); + + TI_DBG2(("tdsaGetGlobalPhyParams:B phy %d phyProperties %d\n", i, tdsaAllShared->Ports[i].agPhyConfig.phyProperties)); + + + + /**********************************************/ + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + /* restore default */ + LinkRate = 15; + Mode = 3; + OpticalMode = 0; + LinkRateRead = agTRUE;//VG + ModeRead = agFALSE; + OpticalModeRead = agFALSE; + + + } /* end for */ + + return; +} + +/***************************************************************************** +*! \brief tdsaGetPortParams +* +* Purpose: This function reads port-related configuration parameters from the +* configuration file +* +* \param tiRoot: Pointer to driver/port instance. +* +* \return: None +* +* \note - just a place holder for now +* +*****************************************************************************/ +osGLOBAL void +tdsaGetPortParams( + tiRoot_t *tiRoot + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&(tdsaRoot->tdsaAllShared); + + + char *buffer; + bit32 buffLen; + bit32 lenRecv = 0; + char *pLastUsedChar = agNULL; + char tmpBuffer[DEFAULT_KEY_BUFFER_SIZE]; + char globalStr[] = "Global"; + char portParmsStr[] = "PortParms"; + + TI_DBG6(("tdsaGetPortParams: start \n")); + TI_DBG6(("tdsaGetPortParams: tdsaRoot %p tdsaAllShared %p \n", tdsaRoot,tdsaAllShared)); + + buffer = tmpBuffer; + buffLen = sizeof(tmpBuffer); + osti_memset(buffer, 0, buffLen); + + if ((ostiGetTransportParam ( + tiRoot, + globalStr, + portParmsStr, + agNULL, + agNULL, + agNULL, + agNULL, + "InterruptDelay", + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaAllShared->currentInterruptDelay = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaAllShared->currentInterruptDelay = osti_strtoul (buffer, &pLastUsedChar, 10); + } + TI_DBG6(("tdsaGetPortParams: in \n")); + } + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + TI_DBG6(("tdsaGetPortParams: out \n")); + + /* and more .... */ + + + return; +} + +#ifdef FW_EVT_LOG_TST +void saLogDump(agsaRoot_t *agRoot, + U32 *eventLogSize, + U32 **eventLogAddress); + +void tiLogDump(tiRoot_t *tiRoot, U32 *size, U32 **addr) +{ + tdsaRoot_t *tdsaRoot; + tdsaContext_t *tdsaAllShared; + + tdsaRoot = (tdsaRoot_t*)tiRoot->tdData; + tdsaAllShared = (tdsaContext_t*)&(tdsaRoot->tdsaAllShared); + saLogDump(&tdsaAllShared->agRootNonInt, size, addr); +} +#endif + + + +/***************************************************************************** +*! \brief tiCOMPortInit +* +* Purpose: This function is called to initialize the port hardware. +* This call could only be called until after the successful +* completion tiCOMInit(). +* +* \param tiRoot: Pointer to root data structure. +* \param sysIntsActive: system interrupt flag +* +* \return: +* tiSuccess: Successful. +* Others: Fail. +* +* \note - +* +*****************************************************************************/ +osGLOBAL bit32 +tiCOMPortInit( + tiRoot_t *tiRoot, + bit32 sysIntsActive + ) +{ + tdsaRoot_t *tdsaRoot; + tdsaContext_t *tdsaAllShared; + agsaRoot_t *agRoot; + tiLoLevelResource_t *loResource; + bit32 status = tiError; + bit32 i; + + agsaQueueConfig_t *QueueConfig; + +#ifdef CONTROLLER_STATUS_TESTING + static agsaControllerStatus_t agcontrollerStatus; +#endif /* CONTROLLER_STATUS_TESTING */ + +#ifdef CONTROLLER_INFO_TESTING + static agsaControllerInfo_t agcontrollerInfo; +#endif /* CONTROLLER_INFO_TESTING */ + +#ifdef CONTROLLER_ENCRYPT_TESTING + static agsaEncryptInfo_t agsaEncryptInfo; +#endif /* CONTROLLER_INFO_TESTING */ + + static agsaMemoryRequirement_t agMemoryRequirement; +#ifdef ECHO_TESTING + /* temp */ + static bit8 payload[56]; +#endif + +#if defined(FDS_DM) || defined(FDS_SM) + static agsaMemoryRequirement_t memRequirement; + bit32 maxQueueSets = 0; + bit32 LLMemCount = 0; + bit32 usecsPerTick = 0; + static agsaSwConfig_t tmpLLSwConfig; +#endif + +#ifdef FDS_DM + static dmRoot_t *dmRoot = agNULL; +#ifdef FDS_SM + static dmSwConfig_t dmSwConfig; +#endif + static dmMemoryRequirement_t dmMemRequirement; + bit32 DMMemCount = 0; +#endif + +#if defined(FDS_DM) && defined(FDS_SM) + bit32 dmUsecsPerTick = 0; + bit32 dmMaxNumLocks = 0; +#endif + +#ifdef FDS_SM + smRoot_t *smRoot = agNULL; +// smSwConfig_t smSwConfig; + static smMemoryRequirement_t smMemRequirement; + bit32 SMMemCount = 0; +#endif + +#ifndef TURN_OFF_HDA + static agsaFwImg_t HDAImg; +#endif /* TURN_OFF_HDA */ + + TI_DBG3(("tiCOMPortInit: start\n")); + TI_DBG6(("tiCOMPortInit: sizeof agsaMemoryRequirement_t %d\n", (int)sizeof(agsaMemoryRequirement_t))); + + tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaAllShared = (tdsaContext_t *)&(tdsaRoot->tdsaAllShared); + + osti_memset(&agMemoryRequirement, 0, sizeof(agsaMemoryRequirement_t)); + /* + * don't do anything if reset is in progress + */ + if (tdsaAllShared->flags.resetInProgress == agTRUE) + { + TI_DBG1(("tiCOMPortInit: resetinProgress error\n")); + return tiError; + } + + loResource = &(tdsaAllShared->loResource); + + agRoot = &(tdsaAllShared->agRootNonInt); + tdsaAllShared->flags.sysIntsActive = sysIntsActive; + + /* + gets port-related parameters; not in use for now + tdsaGetPortParams(tiRoot); + */ + + /* call these before agroot is created for testing */ + + +#ifdef CONTROLLER_STATUS_TESTING + TI_DBG1(("tiCOMPortInit: saGetControllerStatus returns 0x%X\n",saGetControllerStatus(agRoot,&agcontrollerStatus ) )); +#endif /* CONTROLLER_INFO_TESTING */ + +#ifdef CONTROLLER_INFO_TESTING + TI_DBG1(("tiCOMPortInit: saGetControllerInfo returns 0x%X\n",saGetControllerInfo(agRoot,&agcontrollerInfo ) )); +#endif /* CONTROLLER_INFO_TESTING */ + +#ifdef CONTROLLER_ENCRYPT_TESTING + TI_DBG1(("tiCOMPortInit: saEncryptGetMode returns 0x%X\n",saEncryptGetMode(agRoot,agNULL, &agsaEncryptInfo ) )); +#endif /* CONTROLLER_INFO_TESTING */ + + + tdsaGetSwConfigParams(tiRoot); + tdsaPrintSwConfig(&(tdsaAllShared->SwConfig)); + + /* setting interrupt requirements */ + tdsaAllShared->SwConfig.max_MSIX_InterruptVectors = loResource->loLevelOption.maxInterruptVectors; + tdsaAllShared->SwConfig.max_MSI_InterruptVectors = loResource->loLevelOption.max_MSI_InterruptVectors; + tdsaAllShared->SwConfig.legacyInt_X = loResource->loLevelOption.flag; + TI_DBG2(("tiCOMPortInit: got max_MSIX_InterruptVectors %d \n", tdsaAllShared->SwConfig.max_MSIX_InterruptVectors)); + TI_DBG2(("tiCOMPortInit: got max_MSI_InterruptVectors %d \n", tdsaAllShared->SwConfig.max_MSI_InterruptVectors)); + TI_DBG2(("tiCOMPortInit: got flag - legacyInt_X %d \n", tdsaAllShared->SwConfig.legacyInt_X)); + + /* error checking for interrupt types */ + if ( + ((tdsaAllShared->SwConfig.max_MSIX_InterruptVectors == 0) && + (tdsaAllShared->SwConfig.max_MSI_InterruptVectors == 0) && + (tdsaAllShared->SwConfig.legacyInt_X == 0)) + || + ((tdsaAllShared->SwConfig.max_MSIX_InterruptVectors != 0) && + (tdsaAllShared->SwConfig.max_MSI_InterruptVectors == 0) && + (tdsaAllShared->SwConfig.legacyInt_X == 0)) + || + ((tdsaAllShared->SwConfig.max_MSIX_InterruptVectors == 0) && + (tdsaAllShared->SwConfig.max_MSI_InterruptVectors != 0) && + (tdsaAllShared->SwConfig.legacyInt_X == 0)) + || + ((tdsaAllShared->SwConfig.max_MSIX_InterruptVectors == 0) && + (tdsaAllShared->SwConfig.max_MSI_InterruptVectors == 0) && + (tdsaAllShared->SwConfig.legacyInt_X != 0)) + ) + { + /* do nothing */ + } + else + { + TI_DBG1(("tiCOMPortInit: incorrect interrupt\n")); + return tiError; + } + + QueueConfig = &tdsaAllShared->QueueConfig; + + for(i=0;inumInboundQueues;i++) + { + QueueConfig->inboundQueues[i].elementCount = tdsaAllShared->InboundQueueSize[i]; + QueueConfig->inboundQueues[i].elementSize = tdsaAllShared->InboundQueueEleSize[i]; + QueueConfig->inboundQueues[i].priority = tdsaAllShared->InboundQueuePriority[i]; + QueueConfig->inboundQueues[i].reserved = 0; + TI_DBG6(("tiCOMPortInit: InboundQueuePriroity %d \n", tdsaAllShared->InboundQueuePriority[i])); + } + for(i=0;inumOutboundQueues;i++) + { + QueueConfig->outboundQueues[i].elementCount = tdsaAllShared->OutboundQueueSize[i]; + QueueConfig->outboundQueues[i].elementSize = tdsaAllShared->OutboundQueueEleSize[i]; + QueueConfig->outboundQueues[i].interruptDelay = tdsaAllShared->OutboundQueueInterruptDelay[i]; /* default 0; no interrupt delay */ + QueueConfig->outboundQueues[i].interruptCount = tdsaAllShared->OutboundQueueInterruptCount[i]; /* default 1 */ + QueueConfig->outboundQueues[i].interruptEnable = tdsaAllShared->OutboundQueueInterruptEnable[i]; /* default 1 */ + QueueConfig->outboundQueues[i].interruptVectorIndex = 0; + if (tdsaAllShared->SwConfig.max_MSIX_InterruptVectors != 0) + { + QueueConfig->outboundQueues[i].interruptVectorIndex = i % tdsaAllShared->SwConfig.max_MSIX_InterruptVectors; + } + else if (tdsaAllShared->SwConfig.max_MSI_InterruptVectors != 0) + { + QueueConfig->outboundQueues[i].interruptVectorIndex = i % tdsaAllShared->SwConfig.max_MSI_InterruptVectors; + } + else + { + QueueConfig->outboundQueues[i].interruptVectorIndex = 0; + } + TI_DBG6(("tiCOMPortInit: OutboundQueueInterruptDelay %d OutboundQueueInterruptCount %d OutboundQueueInterruptEnable %d\n", tdsaAllShared->OutboundQueueInterruptDelay[i], tdsaAllShared->OutboundQueueInterruptCount[i], tdsaAllShared->OutboundQueueInterruptEnable[i])); + + } + /* queue option */ + QueueConfig->queueOption = tdsaAllShared->QueueOption; + + tdsaAllShared->SwConfig.param3 = (void *)QueueConfig; + tdsaAllShared->SwConfig.stallUsec = 10; + + /* finds a first high priority queue for SMP */ + tdsaAllShared->SMPQNum = 0; /* default */ + for(i=0;inumInboundQueues;i++) + { + if (QueueConfig->inboundQueues[i].priority != DEFAULT_INBOUND_QUEUE_PRIORITY) /* 0 */ + { + tdsaAllShared->SMPQNum = i; + break; + } + } + + tdsaGetHwConfigParams(tiRoot); + + tdsaPrintHwConfig(&(tdsaAllShared->HwConfig)); + +#ifdef TARGET_DRIVER + /* target, not yet */ + if (tdsaAllShared->currentOperation & TD_OPERATION_TARGET) + { + ttdssGetTargetParams(tiRoot); + } +#endif + +#if defined(FDS_DM) && defined(FDS_SM) + /* + needs to call saGetRequirements() to find out agMemoryRequirement.count requested by LL + */ + osti_memcpy(&tmpLLSwConfig, &(tdsaAllShared->SwConfig), sizeof(agsaSwConfig_t)); + + saGetRequirements(agRoot, + &tmpLLSwConfig, + &memRequirement, + &usecsPerTick, + &maxQueueSets + ); + TI_DBG1(("tiCOMPortInit: usecsPerTick %d\n", usecsPerTick)); + + TI_DBG1(("tiCOMPortInit: LL memRequirement.count %d\n", memRequirement.count)); + TI_DBG1(("tiCOMPortInit: loResource->loLevelMem.count %d\n", loResource->loLevelMem.count)); + LLMemCount = memRequirement.count; + + /* + needs to call dmGetRequirements() to find out dmMemoryRequirement.count requested by DM + */ + + dmGetRequirements(dmRoot, + &dmSwConfig, + &dmMemRequirement, + &dmUsecsPerTick, + &dmMaxNumLocks + ); + + TI_DBG1(("tiCOMPortInit: DM dmmemRequirement.count %d\n", dmMemRequirement.count)); + TI_DBG1(("tiCOMPortInit: loResource->loLevelMem.count %d\n", loResource->loLevelMem.count)); + + DMMemCount = dmMemRequirement.count; + SMMemCount = loResource->loLevelMem.count - LLMemCount - DMMemCount; + agMemoryRequirement.count = LLMemCount; + + TI_DBG1(("tiCOMPortInit: SMMemCount %d\n", SMMemCount)); + + +#elif defined(FDS_DM) + /* + needs to call saGetRequirements() to find out agMemoryRequirement.count requested by LL + */ + osti_memcpy(&tmpLLSwConfig, &(tdsaAllShared->SwConfig), sizeof(agsaSwConfig_t)); + + saGetRequirements(agRoot, + &tmpLLSwConfig, + &memRequirement, + &usecsPerTick, + &maxQueueSets + ); + + TI_DBG1(("tiCOMPortInit: memRequirement.count %d\n", memRequirement.count)); + TI_DBG1(("tiCOMPortInit: loResource->loLevelMem.count %d\n", loResource->loLevelMem.count)); + + LLMemCount = memRequirement.count; + DMMemCount = loResource->loLevelMem.count - LLMemCount; + + agMemoryRequirement.count = LLMemCount; + +#elif defined(FDS_SM) + osti_memcpy(&tmpLLSwConfig, &(tdsaAllShared->SwConfig), sizeof(agsaSwConfig_t)); + + saGetRequirements(agRoot, + &tmpLLSwConfig, + &memRequirement, + &usecsPerTick, + &maxQueueSets + ); + + TI_DBG1(("tiCOMPortInit: memRequirement.count %d\n", memRequirement.count)); + TI_DBG1(("tiCOMPortInit: loResource->loLevelMem.count %d\n", loResource->loLevelMem.count)); + + LLMemCount = memRequirement.count; + SMMemCount = loResource->loLevelMem.count - LLMemCount; + + agMemoryRequirement.count = LLMemCount; + +#else + + agMemoryRequirement.count = loResource->loLevelMem.count; + +#endif + +#if defined(FDS_DM) && defined(FDS_SM) + /* for debugging */ + for(i=0;i<(int)(LLMemCount + DMMemCount + SMMemCount);i++) + { + TI_DBG2(("tiCOMPortInit: index %d phyAddrUpper 0x%x phyAddrLower 0x%x totalLength %d alignment %d\n", i, loResource->loLevelMem.mem[i].physAddrUpper, loResource->loLevelMem.mem[i].physAddrLower, loResource->loLevelMem.mem[i].totalLength, loResource->loLevelMem.mem[i].alignment)); + TI_DBG2(("tiCOMPortInit: index %d virtPtr %p\n",i, loResource->loLevelMem.mem[i].virtPtr)); + } +#endif + + /* initialize */ + TI_DBG6(("tiCOMPortInit: AGSA_NUM_MEM_CHUNKS %d\n", AGSA_NUM_MEM_CHUNKS)); + for(i=0;iloLevelMem.mem[i].virtPtr; + agMemoryRequirement.agMemory[i].osHandle = loResource->loLevelMem.mem[i].osHandle; + agMemoryRequirement.agMemory[i].phyAddrUpper = loResource->loLevelMem.mem[i].physAddrUpper; + agMemoryRequirement.agMemory[i].phyAddrLower = loResource->loLevelMem.mem[i].physAddrLower; + agMemoryRequirement.agMemory[i].totalLength = loResource->loLevelMem.mem[i].totalLength; + agMemoryRequirement.agMemory[i].numElements = loResource->loLevelMem.mem[i].numElements; + agMemoryRequirement.agMemory[i].singleElementLength = loResource->loLevelMem.mem[i].singleElementLength; + agMemoryRequirement.agMemory[i].alignment = loResource->loLevelMem.mem[i].alignment; + if (loResource->loLevelMem.mem[i].type == TI_DMA_MEM) + { + agMemoryRequirement.agMemory[i].type = AGSA_DMA_MEM; + } + else if (loResource->loLevelMem.mem[i].type == TI_CACHED_MEM) + { + agMemoryRequirement.agMemory[i].type = AGSA_CACHED_MEM; + + } + else if (loResource->loLevelMem.mem[i].type == TI_CACHED_DMA_MEM) + { + agMemoryRequirement.agMemory[i].type = AGSA_CACHED_DMA_MEM; + } + + agMemoryRequirement.agMemory[i].reserved = loResource->loLevelMem.mem[i].reserved; + TI_DBG2(("tiCOMPortInit: index %d virtPtr %p osHandle %p\n",i, loResource->loLevelMem.mem[i].virtPtr, loResource->loLevelMem.mem[i].osHandle)); + TI_DBG2(("tiCOMPortInit: index %d phyAddrUpper 0x%x phyAddrLower 0x%x totalLength %d numElements %d\n", i, + loResource->loLevelMem.mem[i].physAddrUpper, + loResource->loLevelMem.mem[i].physAddrLower, + loResource->loLevelMem.mem[i].totalLength, + loResource->loLevelMem.mem[i].numElements)); + TI_DBG2(("tiCOMPortInit: index %d singleElementLength 0x%x alignment 0x%x type %d reserved %d\n", i, + loResource->loLevelMem.mem[i].singleElementLength, + loResource->loLevelMem.mem[i].alignment, + loResource->loLevelMem.mem[i].type, + loResource->loLevelMem.mem[i].reserved)); + + } + osti_memset(&(tdsaAllShared->tdFWControlEx), 0, sizeof(tdFWControlEx_t)); + + /* + * Note: Be sure to call this only once since sallsdk does initialization only once + * saInitialize(IN, IN, IN, IN, IN); + */ + + TI_DBG1(("tiCOMPortInit: tdsaAllShared->tdDeviceIdVendId %x\n",tdsaAllShared->tdDeviceIdVendId)); + TI_DBG1(("tiCOMPortInit: tdsaAllShared->tdSubVendorId= SUB_VEN_ID %x\n",tdsaAllShared->tdSubVendorId)); + + TI_DBG1(("tiCOMPortInit: swConfig->param1 hwDEVICE_ID_VENDID %x\n", tdsaAllShared->SwConfig.param1 )); + TI_DBG1(("tiCOMPortInit: swConfig->param2 hwSVID %x\n", tdsaAllShared->SwConfig.param2)); + + /* + 1. Read hostDirectAccessSupport + 2. If set, read HDA images based on chip ID + */ + + t_MacroCheck(agRoot); + +#ifndef TURN_OFF_HDA + if (tdsaAllShared->SwConfig.hostDirectAccessSupport != 0) + { + osti_memset(&HDAImg, 0, sizeof(HDAImg)); + if (tiIS_SPC(agRoot)) + { + TI_DBG1(("tiCOMPortInit: SPC HDA\n")); + HDAImg.aap1Img = (bit8*)(&aap1array); + HDAImg.aap1Len = sizeof( aap1array); + HDAImg.iopImg = (bit8*)(&ioparray); + HDAImg.iopLen = sizeof( ioparray); + HDAImg.istrImg = (bit8*)(&istrarray); + HDAImg.istrLen = sizeof( istrarray); + + HDAImg.ilaImg = (bit8*)(&ilaarray); + HDAImg.ilaLen = sizeof(ilaarray); + } + else if (tiIS_SPC6V(agRoot)) + { + TI_DBG1(("tiCOMPortInit: SPCv HDA\n")); + HDAImg.aap1Img = (bit8*)(&spcv_aap1array); + HDAImg.aap1Len = sizeof( spcv_aap1array); + HDAImg.iopImg = (bit8*)(&spcv_ioparray); + HDAImg.iopLen = sizeof( spcv_ioparray); + + HDAImg.ilaImg = (bit8*)(&spcv_ilaarray); + HDAImg.ilaLen = sizeof(spcv_ilaarray); + } + else if (tIsSPCV12G(agRoot)) + { + TI_DBG1(("tiCOMPortInit: SPCv12G HDA\n")); + HDAImg.aap1Img = (bit8*)(&spcv12g_raaearray); + HDAImg.aap1Len = sizeof( spcv12g_raaearray); + HDAImg.iopImg = (bit8*)(&spcv12g_ioparray); + HDAImg.iopLen = sizeof( spcv12g_ioparray); + + HDAImg.ilaImg = (bit8*)(&spcv12g_ilaarray); + HDAImg.ilaLen = sizeof(spcv12g_ilaarray); + } + else + { + TI_DBG1(("tiCOMPortInit: HDA Mode Unknown chip type 0x%08x\n",ossaHwRegReadConfig32(agRoot,0 ))); + return tiError; + } + TI_DBG1(("tiCOMPortInit: HDA aap1Len 0x%08x iopLen 0x%08x ilaLen 0x%08x\n",HDAImg.aap1Len,HDAImg.iopLen,HDAImg.ilaLen )); + tdsaAllShared->SwConfig.param4 = &(HDAImg); + } + else + { + TI_DBG1(("tiCOMPortInit: HDA off\n")); + tdsaAllShared->SwConfig.param4 = agNULL; + } +#endif /* TURN_OFF_HDA */ + + if (tiIS_SPC(agRoot)) + { + /* FW config is only for SPC */ + tdsaAllShared->SwConfig.FWConfig = 0; + /* default port recovery timer 0x32 = 50 = 5000ms and port reset timer 3 (300 ms)*/ + tdsaAllShared->SwConfig.PortRecoveryResetTimer = 0x30032; + TI_DBG1(("tiCOMPortInit:only for SPC FWConfig set\n")); + } + + tdsaAllShared->SwConfig.fatalErrorInterruptVector = loResource->loLevelOption.maxInterruptVectors > 31 ? 31 : loResource->loLevelOption.maxInterruptVectors -1; + + TI_DBG1(("tiCOMPortInit: SwConfig->FWConfig 0x%x\n", tdsaAllShared->SwConfig.FWConfig)); + TI_DBG1(("tiCOMPortInit: SwConfig->fatalErrorInterruptVector 0x%x\n", tdsaAllShared->SwConfig.fatalErrorInterruptVector)); + TI_DBG1(("tiCOMPortInit: loResource->loLevelOption.usecsPerTick %d\n", loResource->loLevelOption.usecsPerTick)); + + status = saInitialize(agRoot, + &agMemoryRequirement, + &(tdsaAllShared->HwConfig), + /* &temp_HwConfig, */ + &(tdsaAllShared->SwConfig), + loResource->loLevelOption.usecsPerTick); + + TI_DBG6(("tiCOMPortInit: loResource->loLevelOption.usecsPerTick %d 0x%x\n", loResource->loLevelOption.usecsPerTick, loResource->loLevelOption.usecsPerTick)); + + /*TI_DBG6(("tiCOMPortInit: tdsaAllShared->SwConfig.enableDIF %d\n", tdsaAllShared->SwConfig.enableDIF)); */ + /*TI_DBG6(("tiCOMPortInit: tdsaAllShared->SwConfig.enableEncryption %d\n", tdsaAllShared->SwConfig.enableEncryption)); */ + + if(status == AGSA_RC_FAILURE ) + { + TI_DBG1(("tiCOMPortInit: saInitialize AGSA_RC_FAILURE, status 0x%x\n", status)); + return tiError; + } + + if( status == AGSA_RC_VERSION_INCOMPATIBLE) + { + TI_DBG1(("tiCOMPortInit: saInitialize AGSA_RC_VERSION_INCOMPATIBLE, status 0x%x\n", status)); + return tiError; + } + + /* let's make sdkData same for Int and Non-int agRoots */ + tdsaAllShared->agRootInt.sdkData = tdsaAllShared->agRootNonInt.sdkData; + + + /* mark the port as initialized */ + for(i=0;iPorts[i].flags.portInitialized = agTRUE; + } + +#ifdef INITIATOR_DRIVER //ini. only in stsdkll spec (TP) + /* register device registration callback function */ + TI_DBG6(("tiCOMPortInit: calling saRegisterEventCallback for device registration\n")); + status = saRegisterEventCallback(agRoot, OSSA_EVENT_SOURCE_DEVICE_HANDLE_ADDED, (void *)ossaDeviceRegistrationCB); + if (status == AGSA_RC_FAILURE) + { + TI_DBG6(("tiCOMPortInit: saRegisterEventCallback Device Register failed\n")); + } + else + { + TI_DBG6(("tiCOMPortInit: saRegisterEventCallback Device Register succeeded\n")); + } +#endif + + /* register device deregistration callback function */ + TI_DBG6(("tiCOMPortInit: calling saRegisterEventCallback for device de-registration\n")); + status = saRegisterEventCallback(agRoot, OSSA_EVENT_SOURCE_DEVICE_HANDLE_REMOVED, (void *)ossaDeregisterDeviceHandleCB); + if (status == AGSA_RC_FAILURE) + { + TI_DBG6(("tiCOMPortInit: saRegisterEventCallback Device Deregister failed\n")); + } + else + { + TI_DBG6(("tiCOMPortInit: saRegisterEventCallback Device Deregister succeeded\n")); + } + +#ifdef ECHO_TESTING + /* temporary to test saEchoCommand() */ + /* + send echo + */ + payload[0] = gEcho; + payload[55] = gEcho; + TI_DBG2(("tiCOMPortInit: calling saEchoCommand gEcho %d\n", gEcho)); + saEchoCommand(agRoot, agNULL, tdsaRotateQnumber(tiRoot, agNULL), (void *)&payload); + gEcho++; +#endif + +#ifdef CONTROLLER_STATUS_TESTING + TI_DBG1(("tiCOMPortInit: saGetControllerStatus returns 0x%X\n",saGetControllerStatus(agRoot,&agcontrollerStatus ) )); +#endif /* CONTROLLER_INFO_TESTING */ + +#ifdef CONTROLLER_INFO_TESTING + TI_DBG1(("tiCOMPortInit: saGetControllerInfo returns 0x%X\n",saGetControllerInfo(agRoot,&agcontrollerInfo ) )); +#endif /* CONTROLLER_INFO_TESTING */ + +#ifdef CONTROLLER_ENCRYPT_TESTING + TI_DBG1(("tiCOMPortInit: saEncryptGetMode returns 0x%X\n",saEncryptGetMode(agRoot,agNULL,&agsaEncryptInfo ) )); +#endif /* CONTROLLER_INFO_TESTING */ + + +#ifdef VPD_TESTING + /* temporary to test saSetVPDCommand() and saGetVPDCommand */ + tdsaVPDSet(tiRoot); +#endif /* VPD_TESTING */ + +#if defined(FDS_DM) && defined(FDS_SM) + /* initialize DM then SM */ + /* DM */ + dmRoot = &(tdsaAllShared->dmRoot); + osti_memset(&dmMemRequirement, 0, sizeof(dmMemoryRequirement_t)); + + dmMemRequirement.count = DMMemCount; + + for(i=LLMemCount;i<(int)(LLMemCount + DMMemCount);i++) + { + TI_DBG2(("tiCOMPortInit: DM copying loResource.loLevelMem to agsaMemoryRequirement_t index %d\n", i)); + dmMemRequirement.dmMemory[i-LLMemCount].virtPtr = loResource->loLevelMem.mem[i].virtPtr; + dmMemRequirement.dmMemory[i-LLMemCount].osHandle = loResource->loLevelMem.mem[i].osHandle; + dmMemRequirement.dmMemory[i-LLMemCount].physAddrUpper = loResource->loLevelMem.mem[i].physAddrUpper; + dmMemRequirement.dmMemory[i-LLMemCount].physAddrLower = loResource->loLevelMem.mem[i].physAddrLower; + dmMemRequirement.dmMemory[i-LLMemCount].totalLength = loResource->loLevelMem.mem[i].totalLength; + dmMemRequirement.dmMemory[i-LLMemCount].numElements = loResource->loLevelMem.mem[i].numElements; + dmMemRequirement.dmMemory[i-LLMemCount].singleElementLength = loResource->loLevelMem.mem[i].singleElementLength; + dmMemRequirement.dmMemory[i-LLMemCount].alignment = loResource->loLevelMem.mem[i].alignment; + dmMemRequirement.dmMemory[i-LLMemCount].type = loResource->loLevelMem.mem[i].type; + dmMemRequirement.dmMemory[i-LLMemCount].reserved = loResource->loLevelMem.mem[i].reserved; + TI_DBG2(("tiCOMPortInit: index %d virtPtr %p osHandle %p\n",i, loResource->loLevelMem.mem[i].virtPtr, loResource->loLevelMem.mem[i].osHandle)); + TI_DBG2(("tiCOMPortInit: index %d phyAddrUpper 0x%x phyAddrLower 0x%x totalLength %d numElements %d\n", i, + loResource->loLevelMem.mem[i].physAddrUpper, + loResource->loLevelMem.mem[i].physAddrLower, + loResource->loLevelMem.mem[i].totalLength, + loResource->loLevelMem.mem[i].numElements)); + TI_DBG2(("tiCOMPortInit: index %d singleElementLength 0x%x alignment 0x%x type %d reserved %d\n", i, + loResource->loLevelMem.mem[i].singleElementLength, + loResource->loLevelMem.mem[i].alignment, + loResource->loLevelMem.mem[i].type, + loResource->loLevelMem.mem[i].reserved)); + + } + + status = dmInitialize(dmRoot, + agRoot, + &dmMemRequirement, + &(tdsaAllShared->dmSwConfig), //&dmSwConfig, /* start here */ + loResource->loLevelOption.usecsPerTick); + + if(status == DM_RC_FAILURE || status == DM_RC_VERSION_INCOMPATIBLE) + { + TI_DBG1(("tiCOMPortInit: dmInitialize FAILED, status 0x%x\n", status)); + return tiError; + } + + /* SM */ + smRoot = &(tdsaAllShared->smRoot); + osti_memset(&smMemRequirement, 0, sizeof(smMemoryRequirement_t)); + + smMemRequirement.count = SMMemCount; + + for(i=(LLMemCount + DMMemCount);i<(int)(LLMemCount + DMMemCount + SMMemCount);i++) + { + TI_DBG1(("tiCOMPortInit: SM copying loResource.loLevelMem to agsaMemoryRequirement_t index %d\n", i)); + smMemRequirement.smMemory[i-LLMemCount-DMMemCount].virtPtr = loResource->loLevelMem.mem[i].virtPtr; + smMemRequirement.smMemory[i-LLMemCount-DMMemCount].osHandle = loResource->loLevelMem.mem[i].osHandle; + smMemRequirement.smMemory[i-LLMemCount-DMMemCount].physAddrUpper = loResource->loLevelMem.mem[i].physAddrUpper; + smMemRequirement.smMemory[i-LLMemCount-DMMemCount].physAddrLower = loResource->loLevelMem.mem[i].physAddrLower; + smMemRequirement.smMemory[i-LLMemCount-DMMemCount].totalLength = loResource->loLevelMem.mem[i].totalLength; + smMemRequirement.smMemory[i-LLMemCount-DMMemCount].numElements = loResource->loLevelMem.mem[i].numElements; + smMemRequirement.smMemory[i-LLMemCount-DMMemCount].singleElementLength = loResource->loLevelMem.mem[i].singleElementLength; + smMemRequirement.smMemory[i-LLMemCount-DMMemCount].alignment = loResource->loLevelMem.mem[i].alignment; + smMemRequirement.smMemory[i-LLMemCount-DMMemCount].type = loResource->loLevelMem.mem[i].type; + smMemRequirement.smMemory[i-LLMemCount-DMMemCount].reserved = loResource->loLevelMem.mem[i].reserved; + TI_DBG2(("tiCOMPortInit: index %d virtPtr %p osHandle %p\n",i, loResource->loLevelMem.mem[i].virtPtr, loResource->loLevelMem.mem[i].osHandle)); + TI_DBG2(("tiCOMPortInit: index %d phyAddrUpper 0x%x phyAddrLower 0x%x totalLength %d numElements %d\n", i, + loResource->loLevelMem.mem[i].physAddrUpper, + loResource->loLevelMem.mem[i].physAddrLower, + loResource->loLevelMem.mem[i].totalLength, + loResource->loLevelMem.mem[i].numElements)); + TI_DBG2(("tiCOMPortInit: index %d singleElementLength 0x%x alignment 0x%x type %d reserved %d\n", i, + loResource->loLevelMem.mem[i].singleElementLength, + loResource->loLevelMem.mem[i].alignment, + loResource->loLevelMem.mem[i].type, + loResource->loLevelMem.mem[i].reserved)); + + } + + status = smInitialize(smRoot, + agRoot, + &smMemRequirement, + &(tdsaAllShared->smSwConfig), //&smSwConfig, /* start here */ + loResource->loLevelOption.usecsPerTick); + + if(status == SM_RC_FAILURE || status == SM_RC_VERSION_INCOMPATIBLE) + { + TI_DBG1(("tiCOMPortInit: smInitialize FAILED, status 0x%x\n", status)); + return tiError; + } + +#elif defined(FDS_DM) + dmRoot = &(tdsaAllShared->dmRoot); + osti_memset(&dmMemRequirement, 0, sizeof(dmMemoryRequirement_t)); + + dmMemRequirement.count = DMMemCount; + + for(i=LLMemCount;i<(int)(LLMemCount + DMMemCount);i++) + { + TI_DBG6(("tiCOMPortInit: copying loResource.loLevelMem to agsaMemoryRequirement_t index %d\n", i)); + dmMemRequirement.dmMemory[i-LLMemCount].virtPtr = loResource->loLevelMem.mem[i].virtPtr; + dmMemRequirement.dmMemory[i-LLMemCount].osHandle = loResource->loLevelMem.mem[i].osHandle; + dmMemRequirement.dmMemory[i-LLMemCount].physAddrUpper = loResource->loLevelMem.mem[i].physAddrUpper; + dmMemRequirement.dmMemory[i-LLMemCount].physAddrLower = loResource->loLevelMem.mem[i].physAddrLower; + dmMemRequirement.dmMemory[i-LLMemCount].totalLength = loResource->loLevelMem.mem[i].totalLength; + dmMemRequirement.dmMemory[i-LLMemCount].numElements = loResource->loLevelMem.mem[i].numElements; + dmMemRequirement.dmMemory[i-LLMemCount].singleElementLength = loResource->loLevelMem.mem[i].singleElementLength; + dmMemRequirement.dmMemory[i-LLMemCount].alignment = loResource->loLevelMem.mem[i].alignment; + dmMemRequirement.dmMemory[i-LLMemCount].type = loResource->loLevelMem.mem[i].type; + dmMemRequirement.dmMemory[i-LLMemCount].reserved = loResource->loLevelMem.mem[i].reserved; + TI_DBG6(("tiCOMPortInit: index %d phyAddrUpper 0x%x phyAddrLower 0x%x totalLength %d alignment %d\n", i, loResource->loLevelMem.mem[i].physAddrUpper, loResource->loLevelMem.mem[i].physAddrLower, loResource->loLevelMem.mem[i].totalLength, loResource->loLevelMem.mem[i].alignment)); + TI_DBG6(("tiCOMPortInit: index %d virtPtr %p\n",i, loResource->loLevelMem.mem[i].virtPtr)); + + } + + status = dmInitialize(dmRoot, + agRoot, + &dmMemRequirement, + &(tdsaAllShared->dmSwConfig), //&dmSwConfig, /* start here */ + loResource->loLevelOption.usecsPerTick); + + if(status == DM_RC_FAILURE || status == DM_RC_VERSION_INCOMPATIBLE) + { + TI_DBG1(("tiCOMPortInit: dmInitialize FAILED, status 0x%x\n", status)); + return tiError; + } + +#elif defined(FDS_SM) + smRoot = &(tdsaAllShared->smRoot); + osti_memset(&smMemRequirement, 0, sizeof(smMemoryRequirement_t)); + + smMemRequirement.count = SMMemCount; + + for(i=LLMemCount;i<(int)(LLMemCount + SMMemCount);i++) + { + TI_DBG6(("tiCOMPortInit: copying loResource.loLevelMem to agsaMemoryRequirement_t index %d\n", i)); + smMemRequirement.smMemory[i-LLMemCount].virtPtr = loResource->loLevelMem.mem[i].virtPtr; + smMemRequirement.smMemory[i-LLMemCount].osHandle = loResource->loLevelMem.mem[i].osHandle; + smMemRequirement.smMemory[i-LLMemCount].physAddrUpper = loResource->loLevelMem.mem[i].physAddrUpper; + smMemRequirement.smMemory[i-LLMemCount].physAddrLower = loResource->loLevelMem.mem[i].physAddrLower; + smMemRequirement.smMemory[i-LLMemCount].totalLength = loResource->loLevelMem.mem[i].totalLength; + smMemRequirement.smMemory[i-LLMemCount].numElements = loResource->loLevelMem.mem[i].numElements; + smMemRequirement.smMemory[i-LLMemCount].singleElementLength = loResource->loLevelMem.mem[i].singleElementLength; + smMemRequirement.smMemory[i-LLMemCount].alignment = loResource->loLevelMem.mem[i].alignment; + smMemRequirement.smMemory[i-LLMemCount].type = loResource->loLevelMem.mem[i].type; + smMemRequirement.smMemory[i-LLMemCount].reserved = loResource->loLevelMem.mem[i].reserved; + TI_DBG6(("tiCOMPortInit: index %d phyAddrUpper 0x%x phyAddrLower 0x%x totalLength %d alignment %d\n", i, loResource->loLevelMem.mem[i].physAddrUpper, loResource->loLevelMem.mem[i].physAddrLower, loResource->loLevelMem.mem[i].totalLength, loResource->loLevelMem.mem[i].alignment)); + TI_DBG6(("tiCOMPortInit: index %d virtPtr %p\n",i, loResource->loLevelMem.mem[i].virtPtr)); + + } + + status = smInitialize(smRoot, + agRoot, + &smMemRequirement, + &(tdsaAllShared->smSwConfig), //&smSwConfig, /* start here */ + loResource->loLevelOption.usecsPerTick); + + if(status == SM_RC_FAILURE || status == SM_RC_VERSION_INCOMPATIBLE) + { + TI_DBG1(("tiCOMPortInit: smInitialize FAILED, status 0x%x\n", status)); + return tiError; + } +#else + /* nothing */ +#endif /* FDS_DM && FDS_SM */ + + /* call these again after agroot is created for testing */ +#ifdef CONTROLLER_STATUS_TESTING + TI_DBG1(("tiCOMPortInit:again saGetControllerStatus returns 0x%X\n",saGetControllerStatus(agRoot,&agcontrollerStatus ) )); +#endif /* CONTROLLER_INFO_TESTING */ + +#ifdef CONTROLLER_INFO_TESTING + TI_DBG1(("tiCOMPortInit:again saGetControllerInfo returns 0x%X\n",saGetControllerInfo(agRoot,&agcontrollerInfo ) )); +#endif /* CONTROLLER_INFO_TESTING */ + +#ifdef CONTROLLER_ENCRYPT_TESTING + TI_DBG1(("tiCOMPortInit:again saEncryptGetMode returns 0x%X\n",saEncryptGetMode(agRoot,agNULL,&agsaEncryptInfo ) )); +#endif /* CONTROLLER_INFO_TESTING */ + +/* Enable SGPIO */ + if (tiSuccess == tiCOMConfigureSgpio(tiRoot, agTRUE)) + { + TI_DBG2(("tiCOMPortInit: Successfully sent request to enable SGPIO\n")); + } + else + { + TI_DBG1(("tiCOMPortInit: Failed to enable SGPIO\n")); + } + + return tiSuccess; +} + +/***************************************************************************** +*! \brief SendSgpioRequest +* +* Purpose: This function is used to send SGPIO request during initialization +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param regType: Register Type +* \param regIndex: Register Index +* \param regCount: Register Count +* \param writeData: Part of the request +* +* \return: +* tiSuccess on success +* Other status on failure +* +*****************************************************************************/ +static bit32 SendSgpioRequest( + tiRoot_t *tiRoot, + bit8 regType, + bit8 regIndex, + bit8 regCount, + bit32 *writeData + ) +{ + static bit32 buffer[128] = {0}; + bit32 status = tiError; + bit32 retVal = IOCTL_CALL_FAIL; + tiIOCTLPayload_t *agIOCTLPayload = (tiIOCTLPayload_t *) buffer; + agsaSGpioReqResponse_t *pSGpioReq = (agsaSGpioReqResponse_t *) &agIOCTLPayload->FunctionSpecificArea[0]; + agsaSGpioReqResponse_t *pSgpioResponse = (agsaSGpioReqResponse_t *) &agIOCTLPayload->FunctionSpecificArea[0]; + + do{ + + /* Frame the Ioctl payload */ + agIOCTLPayload->MajorFunction = IOCTL_MJ_SGPIO; + agIOCTLPayload->Length = sizeof(agsaSGpioReqResponse_t); + + /* Frame the SGPIO request */ + pSGpioReq->smpFrameType = SMP_REQUEST; + pSGpioReq->function = AGSA_WRITE_SGPIO_REGISTER; + pSGpioReq->registerType = regType; + pSGpioReq->registerIndex = regIndex; + pSGpioReq->registerCount = regCount; + memcpy(pSGpioReq->readWriteData, writeData, regCount * 4); + + /* Send the SGPIO request */ + sgpioResponseSet = 0; + retVal = tdsaSGpioIoctlSetup(tiRoot, agNULL, agIOCTLPayload, agNULL, agNULL); + if (retVal != IOCTL_CALL_PENDING) + { + break; + } + /* Waiting for SGPIO Response */ + while(!sgpioResponseSet) + { + tiCOMDelayedInterruptHandler(tiRoot, 0, 1, tiNonInterruptContext); + } + sgpioResponseSet = 0; + /* Check the ioctl result */ + if(agIOCTLPayload->Status != IOCTL_ERR_STATUS_OK) + { + break; + } + /* Check the sgpio function result */ + if(pSgpioResponse->functionResult != 0x00) + { + break; + } + + status = tiSuccess; + + }while(0); + + return status; +} + +/***************************************************************************** +*! \brief tiCOMConfigureSgpio +* +* Purpose: This function is used to configure SGPIO during initialization +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param enableSgpio: Enable / Disable SGPIO +* +* \return: +* tiSuccess on success +* Other status on failure +* +*****************************************************************************/ +bit32 tiCOMConfigureSgpio( + tiRoot_t *tiRoot, + bit8 enableSgpio + ) +{ + bit32 status = tiError; + bit32 i; + bit8 regCount; + bit32 writeData[OSSA_SGPIO_MAX_READ_DATA_COUNT] = {0}; + agsaSGpioCfg0_t *pCfg0 = (agsaSGpioCfg0_t *) &writeData[0]; + agsaSGpioCfg1_t *pCfg1 = (agsaSGpioCfg1_t *) &writeData[1]; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *) &tdsaRoot->tdsaAllShared; + bit32 phyCount = tdsaAllShared->phyCount; + + if (enableSgpio) + { + /* Configure both CFG[0] and CFG[1] */ + regCount = 2; + + /* Enable SGPIO */ + pCfg0->gpioEnable = 1; + + /* The following are the default values for CFG[1] suggested by SFF-8485 spec */ + /* Maximum Activity ON: 2 */ + /* Forced Activity OFF: 1 */ + pCfg1->maxActOn = 2; + pCfg1->forceActOff = 1; + } + else + { + /* Configure CFG[0] only */ + regCount = 1; + + /* Disable SGPIO */ + pCfg0->gpioEnable = 0; + } + + status = SendSgpioRequest(tiRoot, AGSA_SGPIO_CONFIG_REG, 0, regCount, writeData); + if((tiSuccess == status) && (enableSgpio)) + { + /* Write default values to transmit registers */ + /* RegisterCount = Number of phys present in HBA / 4 */ + regCount = phyCount / 4; + for(i = 0; i < regCount; i++) + { + /* Following are the default values specified in SFF-8485 spec */ + /* Activity: 5 */ + /* Locate: 0 */ + /* Error: 0 */ + writeData[i] = 0xA0A0A0A0; + } + status = SendSgpioRequest(tiRoot, AGSA_SGPIO_DRIVE_BY_DRIVE_TRANSMIT_REG, 0, regCount, writeData); + } + + return status; +} + + +/***************************************************************************** +*! \brief tiCOMPortStart +* +* Purpose: This function is called to bring the port hardware online. This +* call could only be called until after the successful completion +* tiCOMPortInit(). +* +* \param tiRoot: Pointer to root data structure. +* \param portID: A ID for this portal to be used by the TD Layer +* to get the portal configuration information. +* \param portalContext: Pointer to the context for this portal. +* \param option: An option for starting a port +* +* \return: +* tiSuccess: Successful. +* Others: Fail. +* +* \note - +* If sas or sata initiator, this will be called 8 (the number of phys) times. +* If both sas and sata initiator, this will be called 16 times +* +*****************************************************************************/ +/* portID is used as PhyID + Should return always tiSuccess. PortStarted is returned in ossaHwCB() +*/ +osGLOBAL bit32 +tiCOMPortStart( + tiRoot_t * tiRoot, + bit32 portID, + tiPortalContext_t * portalContext, + bit32 option + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + agsaRoot_t *agRoot = &tdsaAllShared->agRootInt; + agsaSASProtocolTimerConfigurationPage_t SASConfigPage; + bit32 status = AGSA_RC_FAILURE; + static bit32 IsSendSASConfigPage = agFALSE; + + + TI_DBG3(("tiCOMPortStart: start portID %d\n", portID)); + + /* + * return error if reset is in progress + */ + if (tdsaAllShared->flags.resetInProgress == agTRUE) + { + TI_DBG1(("tiCOMPortStart: reset error\n")); + return tiError; + } + + /* + * + * port is not initialized, return error + */ + if (tdsaAllShared->Ports[portID].flags.portInitialized == agFALSE) + { + TI_DBG1(("tiCOMPortStart: not intialized error\n")); + return tiError; + } + + /* portal has been started. */ + if (portalContext->tdData != NULL) + { + if (tdsaAllShared->Ports[portID].flags.portStarted == agTRUE) + { + TI_DBG3 (("tiCOMPortStart : Cannot start port again: Port has already been started\n")); + ostiPortEvent ( + tiRoot, + tiPortStarted, + tiSuccess, + (void *) tdsaAllShared->Ports[portID].tiPortalContext + ); + return tiSuccess; + } + } + + portalContext->tdData = &(tdsaAllShared->Ports[portID]); + TI_DBG4 (("tiCOMPortStart : saving portalconext portID %d tdsaAllShared %p\n", portID, tdsaAllShared)); + /* saving tiportalContext_t */ + tdsaAllShared->Ports[portID].tiPortalContext = portalContext; + TI_DBG4(("tiCOMPortStart : portID/phyID %d tiPortalContext %p\n", portID, tdsaAllShared->Ports[portID].tiPortalContext)); + + /* + where is "tdsaAllShared->Ports[0].portContext" set? + in ossaHWCB + */ + if (tdsaAllShared->Ports[portID].flags.portStarted == agTRUE) + { + TI_DBG1(("tiCOMPortStart: port already has been started \n")); + return tiSuccess; + } + + + /* + hardcode sasID frame. It should be read by ostigettransportparams later from configuration file + */ +#ifdef INITIATOR_DRIVER + + tdsaAllShared->Ports[portID].SASID.target_ssp_stp_smp = 0; + tdsaAllShared->Ports[portID].SASID.initiator_ssp_stp_smp + = SA_IDFRM_SSP_BIT | SA_IDFRM_STP_BIT | SA_IDFRM_SMP_BIT; + tdsaAllShared->Ports[portID].SASID.deviceType_addressFrameType = AGSA_DEV_TYPE_END_DEVICE; + + tdsaAllShared->Ports[portID].SASID.phyIdentifier = (bit8)portID; + +#endif + +#ifdef TARGET_DRIVER + + tdsaAllShared->Ports[portID].SASID.target_ssp_stp_smp = SA_IDFRM_SSP_BIT; + tdsaAllShared->Ports[portID].SASID.initiator_ssp_stp_smp = 0; + tdsaAllShared->Ports[portID].SASID.deviceType_addressFrameType = AGSA_DEV_TYPE_END_DEVICE; + tdsaAllShared->Ports[portID].SASID.phyIdentifier = (bit8)portID; + +#endif + +#if defined (INITIATOR_DRIVER) && defined (TARGET_DRIVER) + + /* for combo testing */ + tdsaAllShared->Ports[portID].SASID.target_ssp_stp_smp = SA_IDFRM_SSP_BIT; + tdsaAllShared->Ports[portID].SASID.initiator_ssp_stp_smp + = SA_IDFRM_SSP_BIT | SA_IDFRM_STP_BIT | SA_IDFRM_SMP_BIT; + tdsaAllShared->Ports[portID].SASID.deviceType_addressFrameType = AGSA_DEV_TYPE_END_DEVICE; + + tdsaAllShared->Ports[portID].SASID.phyIdentifier = (bit8)portID; + +#endif + + + TI_DBG6(("tiCOMPortStart: before pid %d\n", portID)); + tdssPrintSASIdentify(&(tdsaAllShared->Ports[portID].SASID)); + + TI_DBG6(("tiCOMPortStart: sysIntsActive %s\n", + (tdsaAllShared->flags.sysIntsActive == agTRUE) ? "agTRUE" : "agFALSE")); + + /* Read global configuration first then card-specific configuration */ + + /* the following must be processed only once */ + if ( tdsaAllShared->first_process == agFALSE) + { + tdsaGetGlobalPhyParams(tiRoot); + tdsaGetCardPhyParams(tiRoot); + tdsaAllShared->first_process = agTRUE; + } + + TI_DBG6(("tiCOMPortStart: after pid %d\n", portID)); + tdssPrintSASIdentify(&(tdsaAllShared->Ports[portID].SASID)); + + /* + Phy Calibration + */ + if (tdsaAllShared->phyCalibration) + { + /* Change default phy calibration */ + tdsaAllShared->Ports[portID].agPhyConfig.phyProperties = + (tdsaAllShared->Ports[portID].agPhyConfig.phyProperties) | 0x80; + /* Setting index of phy calibration table index + portID is used as phy calibration table index + */ + tdsaAllShared->Ports[portID].agPhyConfig.phyProperties = + (tdsaAllShared->Ports[portID].agPhyConfig.phyProperties) | (portID << 8); + } + TI_DBG2(("tiCOMPortStart: tdsaAllShared->Ports[0x%x].agPhyConfig.phyProperties 0x%x\n", + portID, tdsaAllShared->Ports[portID].agPhyConfig.phyProperties)); + + + if(gSSC_Disable) + { + tdsaAllShared->Ports[portID].agPhyConfig.phyProperties = tdsaAllShared->Ports[portID].agPhyConfig.phyProperties | 0x40000; + TI_DBG1(("tiCOMPortStart:gSSC_Disable tdsaAllShared->Ports[portID].agPhyConfig.phyProperties 0x%x\n", tdsaAllShared->Ports[portID].agPhyConfig.phyProperties)); + + } + + if(tIsSPCV12or6G(agRoot) && !IsSendSASConfigPage) /* Not SPC */ + { + /* call saSetControllerConfig() to set STP_IDLE_TIME; All others are the defaults */ + osti_memset(&SASConfigPage, 0, sizeof(agsaSASProtocolTimerConfigurationPage_t)); + SASConfigPage.pageCode = AGSA_SAS_PROTOCOL_TIMER_CONFIG_PAGE; + SASConfigPage.MST_MSI = 3 << 15; /* enables both MCT for SSP target and initiator */ + SASConfigPage.STP_SSP_MCT_TMO = (tdsaAllShared->STP_MCT_TMO << 16) | tdsaAllShared->SSP_MCT_TMO; /* default of 3200 us for STP and SSP maximum connection time */ + SASConfigPage.STP_FRM_TMO = (tdsaAllShared->MAX_OPEN_TIME << 24) | (tdsaAllShared->SMP_MAX_CONN_TIMER << 16) | tdsaAllShared->STP_FRM_TMO; /* MAX_OPEN_TIME, SMP_MAX_CONN_TIMER, STP frame timeout */ + SASConfigPage.STP_IDLE_TMO = tdsaAllShared->stp_idle_time; + if (SASConfigPage.STP_IDLE_TMO > 0x3FFFFFF) + { + SASConfigPage.STP_IDLE_TMO = 0x3FFFFFF; + } + SASConfigPage.OPNRJT_RTRY_INTVL = (tdsaAllShared->MFD << 16) | tdsaAllShared->OPNRJT_RTRY_INTVL; /* Multi Data Fetach enabled and 2 us for Open Reject Retry interval */ + SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO = (tdsaAllShared->DOPNRJT_RTRY_TMO << 16) | tdsaAllShared->COPNRJT_RTRY_TMO; /* 128 us for ORR Timeout for DATA phase and 32 us for ORR Timeout for command phase */ + SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR = (tdsaAllShared->DOPNRJT_RTRY_THR << 16) | tdsaAllShared->COPNRJT_RTRY_THR; /* 16 for ORR backoff threshold for DATA phase and 1024 for ORR backoff threshold for command phase */ + SASConfigPage.MAX_AIP = tdsaAllShared->MAX_AIP; /* MAX AIP. Default is 0x200000 */ + + TI_DBG1(("tiCOMPortStart: saSetControllerConfig SASConfigPage.pageCode 0x%08x\n",SASConfigPage.pageCode)); + TI_DBG1(("tiCOMPortStart: saSetControllerConfig SASConfigPage.MST_MSI 0x%08x\n",SASConfigPage.MST_MSI)); + TI_DBG1(("tiCOMPortStart: saSetControllerConfig SASConfigPage.STP_SSP_MCT_TMO 0x%08x\n",SASConfigPage.STP_SSP_MCT_TMO)); + TI_DBG1(("tiCOMPortStart: saSetControllerConfig SASConfigPage.STP_FRM_TMO 0x%08x\n",SASConfigPage.STP_FRM_TMO)); + TI_DBG1(("tiCOMPortStart: saSetControllerConfig SASConfigPage.STP_IDLE_TMO 0x%08x\n",SASConfigPage.STP_IDLE_TMO)); + TI_DBG1(("tiCOMPortStart: saSetControllerConfig SASConfigPage.OPNRJT_RTRY_INTVL 0x%08x\n",SASConfigPage.OPNRJT_RTRY_INTVL)); + TI_DBG1(("tiCOMPortStart: saSetControllerConfig SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO 0x%08x\n",SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO)); + TI_DBG1(("tiCOMPortStart: saSetControllerConfig SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR 0x%08x\n",SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR)); + TI_DBG1(("tiCOMPortStart: saSetControllerConfig SASConfigPage.MAX_AIP 0x%08x\n",SASConfigPage.MAX_AIP)); + + status = saSetControllerConfig(agRoot, + 0, + AGSA_SAS_PROTOCOL_TIMER_CONFIG_PAGE, + sizeof(agsaSASProtocolTimerConfigurationPage_t), + &SASConfigPage, + agNULL); + if (status != AGSA_RC_SUCCESS) + { + TI_DBG1(("tiCOMPortStart: calling saSetControllerConfig() failed\n")); + } + else + { + TI_DBG2(("tiCOMPortStart: calling saSetControllerConfig() is OK\n")); + } + IsSendSASConfigPage = agTRUE; + } + else + { + TI_DBG1(("tiCOMPortStart: saSetControllerConfig not called tIsSPCV12or6G %d IsSendSASConfigPage %d\n",tIsSPCV12or6G(agRoot),IsSendSASConfigPage)); + } + + /* maps portID to phyID */ + status = saPhyStart(agRoot, + agNULL, + 0, + portID, + &(tdsaAllShared->Ports[portID].agPhyConfig), + &(tdsaAllShared->Ports[portID].SASID) + ); + + TI_DBG6(("tiCOMPortStart: saPhyStart status %d\n", status)); + + if (status == AGSA_RC_SUCCESS) + { + TI_DBG3(("tiCOMPortStart : calling portstarted\n")); + ostiPortEvent( + tiRoot, + tiPortStarted, + tiSuccess, + (void *) tdsaAllShared->Ports[portID].tiPortalContext + ); + return tiSuccess; + } + else + { + TI_DBG3(("tiCOMPortStart : cant' start port\n")); + return tiError; + } + +} + +/***************************************************************************** +*! \brief tiCOMPortStop +* +* Purpose: This function is called to bring the port hardware down. +* +* \param tiRoot: Pointer to root data structure. +* \param portalContext: Pointer to the context for this portal. +* +* \return: +* tiSuccess: Successful. +* Others: Fail. +* +* \note - +* +*****************************************************************************/ +osGLOBAL bit32 +tiCOMPortStop ( + tiRoot_t *tiRoot, + tiPortalContext_t *portalContext + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdList_t *PortContextList; + tdsaPortContext_t *onePortContext = agNULL; + agsaRoot_t *agRoot = agNULL; + bit32 i; + bit32 found = agFALSE; + +#ifdef CONTROLLER_STATUS_TESTING + agsaControllerStatus_t agcontrollerStatus; +#endif /* CONTROLLER_STATUS_TESTING */ + + + TI_DBG3(("tiCOMPortStop: start\n")); + /* + find the portcontext + find phys belonging to that portcotext + call saPhyStop for all those phys + call saPhyStop() + remove the portcontext from the portcontext list + */ + + agRoot = &(tdsaAllShared->agRootNonInt); + +#ifdef CONTROLLER_STATUS_TESTING + TI_DBG1(("tiCOMPortStop: saGetControllerStatus returns 0x%X\n",saGetControllerStatus(agRoot,&agcontrollerStatus ) )); +#endif /* CONTROLLER_INFO_TESTING */ + + if (TDLIST_EMPTY(&(tdsaAllShared->MainPortContextList))) + { + TI_DBG1(("tiCOMPortStop: empty tdsaPortContext\n")); + return tiError; + } + + /* find a right portcontext */ + PortContextList = tdsaAllShared->MainPortContextList.flink; + while (PortContextList != &(tdsaAllShared->MainPortContextList)) + { + onePortContext = TDLIST_OBJECT_BASE(tdsaPortContext_t, MainLink, PortContextList); + if (onePortContext == agNULL) + { + TI_DBG1(("tiCOMPortStop: onePortContext is NULL!!!\n")); + return tiError; + } + if (onePortContext->tiPortalContext == portalContext) + { + TI_DBG6(("tiCOMPortStop: found; oneportContext ID %d\n", onePortContext->id)); + found = agTRUE; + break; + } + PortContextList = PortContextList->flink; + } + + if (found == agFALSE) + { + TI_DBG1(("tiCOMPortStop: No corressponding tdsaPortContext\n")); + return tiError; + } + +#ifdef INITIATOR_DRIVER + /* reset the fields of portcontext */ + onePortContext->DiscoveryState = ITD_DSTATE_NOT_STARTED; + onePortContext->discoveryOptions = AG_SA_DISCOVERY_OPTION_FULL_START; +#endif /* INITIATOR_DRIVER */ + + onePortContext->Count = 0; + onePortContext->agContext.osData = onePortContext; + for(i=0;iPhyIDList[i] == agTRUE) + { + tdsaAllShared->Ports[i].portContext = agNULL; +#ifdef CCFLAGS_PHYCONTROL_COUNTS + if( tiIS_SPC(agRoot) ) + { + + saLocalPhyControl(agRoot,&onePortContext->agContext,0 , i, AGSA_PHY_GET_ERROR_COUNTS, agNULL); + saLocalPhyControl(agRoot,&onePortContext->agContext,0 , i, AGSA_PHY_CLEAR_ERROR_COUNTS, agNULL); + saLocalPhyControl(agRoot,&onePortContext->agContext,0 , i, AGSA_PHY_GET_BW_COUNTS, agNULL); + } + else + { + TI_DBG1(("\ntiCOMPortStop: CCFLAGS_PHYCONTROL_COUNTS PHY %d\n",i)); + saGetPhyProfile( agRoot,&onePortContext->agContext,0, AGSA_SAS_PHY_ERR_COUNTERS_PAGE, i); + saGetPhyProfile( agRoot,&onePortContext->agContext,0, AGSA_SAS_PHY_BW_COUNTERS_PAGE,i); + saGetPhyProfile( agRoot,&onePortContext->agContext,0, AGSA_SAS_PHY_ANALOG_SETTINGS_PAGE,i); + saGetPhyProfile( agRoot,&onePortContext->agContext,0, AGSA_SAS_PHY_GENERAL_STATUS_PAGE,i); + saGetPhyProfile( agRoot,&onePortContext->agContext,0, AGSA_SAS_PHY_ERR_COUNTERS_CLR_PAGE,i); + + TI_DBG1(("tiCOMPortStop: CCFLAGS_PHYCONTROL_COUNTS PHY %d\n",i)); + + } + +#endif /* CCFLAGS_PHYCONTROL_COUNTS */ + saPhyStop(agRoot, &onePortContext->agContext, 0, i); + } + } + + return tiSuccess; +} + + +/***************************************************************************** +*! \brief tiCOMGetPortInfo +* +* Purpose: This function is called to return information about the specific +* port instant +* +* +* \param tiRoot: Pointer to driver/port instance. +* \param portalContext Pointer to the context for this portal. +* \param tiPortInfo: Pointer to port information structure. +* +* \Return: tiSuccess +* +*****************************************************************************/ +/* + can't find tdsaportcontext in this function + since discovery has not been called by OS layer yet + Therefore, hardcoded value are being returned for now +*/ +osGLOBAL bit32 tiCOMGetPortInfo( + tiRoot_t *tiRoot, + tiPortalContext_t *portalContext, + tiPortInfo_t *tiPortInfo + ) + +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdList_t *PortContextList; + tdsaPortContext_t *onePortContext = agNULL; + bit32 found = agFALSE; + static bit8 localname[68], remotename[68]; + + TI_DBG6(("tiCOMGetPortInfo: start\n")); + + + tdsaSingleThreadedEnter(tiRoot, TD_PORT_LOCK); + if (TDLIST_EMPTY(&(tdsaAllShared->MainPortContextList))) + { + tdsaSingleThreadedLeave(tiRoot, TD_PORT_LOCK); + TI_DBG1(("tiCOMGetPortInfo: No tdsaPortContext\n")); + return tiError; + } + else + { + tdsaSingleThreadedLeave(tiRoot, TD_PORT_LOCK); + } + + /* find a corresponding portcontext */ + PortContextList = tdsaAllShared->MainPortContextList.flink; + while (PortContextList != &(tdsaAllShared->MainPortContextList)) + { + onePortContext = TDLIST_OBJECT_BASE(tdsaPortContext_t, MainLink, PortContextList); + TI_DBG3(("tiCOMGetPortInfo: oneportContext pid %d\n", onePortContext->id)); + if (onePortContext->tiPortalContext == portalContext && onePortContext->valid == agTRUE) + { + TI_DBG3(("tiCOMGetPortInfo: found; oneportContext pid %d\n", onePortContext->id)); + found = agTRUE; + break; + } + PortContextList = PortContextList->flink; + } + + if (found == agFALSE) + { + TI_DBG1(("tiCOMGetPortInfo: First, No corresponding tdsaPortContext\n")); + return tiError; + } + + if (onePortContext == agNULL) + { + TI_DBG1(("tiCOMGetPortInfo: Second, No corressponding tdsaPortContext\n")); + return tiError; + } + + osti_memset(localname, 0, sizeof(localname)); + osti_memset(remotename, 0, sizeof(remotename)); + + /* + Parse the type of port then fill in the information + */ + if ( onePortContext->sasRemoteAddressHi == 0xFFFFFFFF && onePortContext->sasRemoteAddressLo == 0xFFFFFFFF) + { + /* directly attached SATA port */ + osti_memcpy(localname, &(onePortContext->sasLocalAddressHi), 4); + osti_memcpy(&(localname[4]), &(onePortContext->sasLocalAddressLo), 4); + tiPortInfo->localNameLen = 8; + /* information is from SATA ID device data. remoteName is serial number, firmware version, model number */ + osti_memcpy(remotename, onePortContext->remoteName, 68); + tiPortInfo->remoteNameLen = 68; + } + else + { + /* copy hi address and low address */ + osti_memcpy(localname, &(onePortContext->sasLocalAddressHi), 4); + osti_memcpy(&(localname[4]), &(onePortContext->sasLocalAddressLo), 4); + tiPortInfo->localNameLen = 8; + osti_memcpy(remotename, &(onePortContext->sasRemoteAddressHi), 4); + osti_memcpy(&(remotename[4]), &(onePortContext->sasRemoteAddressLo), 4); + tiPortInfo->remoteNameLen = 8; + } + + tiPortInfo->localName = (char *)&localname; + tiPortInfo->remoteName = (char *)&remotename; + + + return tiSuccess; + +} + +/***************************************************************************** +* +* tiCOMSetControllerConfig +* +* Purpose: This function is called to set the controller's advanced configuration. +* The status is reported via ostiPortEvent(). +* +* Parameters: +* +* tiRoot: Pointer to driver/port instance. +* +* Return: +* tiSuccess: The setting controller configuration was started. +* tiError: The setting controller configuration was not started. +* +*****************************************************************************/ +osGLOBAL bit32 tiCOMSetControllerConfig ( + tiRoot_t *tiRoot, + bit32 modePage, + bit32 length, + void *buffer, + void *context) +{ + agsaRoot_t *agRoot; + bit32 returnCode = AGSA_RC_BUSY; + bit32 tiStatus = tiSuccess; + tdsaRoot_t *tdsaRoot ; + tdsaContext_t *tdsaAllShared ; + + TD_ASSERT(tiRoot, "tiRoot"); + tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + TD_ASSERT(tdsaRoot, "tdsaRoot"); + + tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + TD_ASSERT(tdsaAllShared, "tdsaAllShared"); + agRoot = &(tdsaAllShared->agRootNonInt); + TD_ASSERT(agRoot, "agRoot"); + + agRoot = &(tdsaAllShared->agRootNonInt); + + TI_DBG1(("tiCOMSetControllerConfig:\n" )); + + /*do some sanity checking */ + if ( ((modePage == TI_INTERRUPT_CONFIGURATION_PAGE) && (length != sizeof(tiInterruptConfigPage_t ))) || + ((modePage == TI_ENCRYPTION_GENERAL_CONFIG_PAGE) && (length != sizeof(tiEncryptGeneralPage_t ))) || + ((modePage == TI_ENCRYPTION_DEK_CONFIG_PAGE) && (length != sizeof(tiEncryptDekConfigPage_t))) || + ((modePage == TI_ENCRYPTION_CONTROL_PARM_PAGE) && (length != sizeof(tiEncryptControlParamPage_t ))) || + ((modePage == TI_ENCRYPTION_HMAC_CONFIG_PAGE) && (length != sizeof(tiEncryptHMACConfigPage_t ))) || + ((modePage == TI_SAS_PROTOCOL_TIMER_CONFIG_PAGE) && (length != sizeof(tiSASProtocolTimerConfigurationPage_t ))) ) + { + tiStatus = tiError; + } + else + { + returnCode = saSetControllerConfig(agRoot, 0, modePage, length, buffer, context); + + if (returnCode == AGSA_RC_SUCCESS) + { + tiStatus = tiSuccess; + } + else if (returnCode == AGSA_RC_BUSY) + { + tiStatus = tiBusy; + } + else + { + tiStatus = tiError; + } + } + return(tiStatus); +} + +/***************************************************************************** +* +* tiCOMGetControllerConfig +* +* Purpose: This function is called to get the controller's advanced configuration. +* The status is reported via ostiPortEvent(). +* +* Parameters: +* +* tiRoot: Pointer to driver/port instance. +* flag: Interrupt Vector Mask +* This parameter is valid only when modePage is set to TI_INTERRUPT_CONFIGURATION_PAGE. +* When the modePage field is set to TI_INTERRUPT_CONFIGURATION_PAGE, +* this field contains a bitmap of interrupt vectors for which interrupt coalescing parameters are retrieved. +* Return: +* tiSuccess: The controller configuration retrival was started. +* tiError: The controller configuration retrival was not started. +* +*****************************************************************************/ +osGLOBAL bit32 tiCOMGetControllerConfig ( + tiRoot_t *tiRoot, + bit32 modePage, + bit32 flag, + void *context) + +{ + agsaRoot_t *agRoot; + bit32 returnCode = AGSA_RC_BUSY; + bit32 tiStatus = tiSuccess; + tdsaRoot_t *tdsaRoot ; + tdsaContext_t *tdsaAllShared ; + + TD_ASSERT(tiRoot, "tiRoot"); + tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + TD_ASSERT(tdsaRoot, "tdsaRoot"); + + tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + TD_ASSERT(tdsaAllShared, "tdsaAllShared"); + agRoot = &(tdsaAllShared->agRootNonInt); + TD_ASSERT(agRoot, "agRoot"); + + agRoot = &(tdsaAllShared->agRootNonInt); + + TI_DBG1(("tiCOMGetControllerConfig: modePage 0x%x context %p\n",modePage,context )); + + returnCode = saGetControllerConfig(agRoot, 0, modePage, flag, 0, context); + + if (returnCode == AGSA_RC_SUCCESS) + { + tiStatus = tiSuccess; + TI_DBG1(("tiCOMGetControllerConfig:modePage 0x%x tiSuccess\n",modePage )); + } + else if (returnCode == AGSA_RC_BUSY) + { + tiStatus = tiBusy; + TI_DBG1(("tiCOMGetControllerConfig:modePage 0x%x tiBusy\n",modePage )); + } + else + { + tiStatus = tiError; + TI_DBG1(("tiCOMGetControllerConfig:modePage 0x%x tiError\n",modePage )); + } + + return(tiStatus); +} + +/***************************************************************************** +* +* tiCOMEncryptGetInfo +* +* Purpose: This function is called to return information about the encryption +* engine for the specified port. +* +* Parameters: +* +* tiRoot: Pointer to driver/port instance. +* +* Return: +* tiSuccess The request is being processed +* tiNotSupported Encryption is not supported +* +*****************************************************************************/ +osGLOBAL bit32 tiCOMEncryptGetInfo(tiRoot_t *tiRoot) +{ + tiEncryptInfo_t tiEncryptInfo; + agsaEncryptInfo_t agsaEncryptInfo; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + agsaRoot_t *agRoot; + tiEncryptPort_t tiEncryptPort; + bit32 returnCode; + bit32 tiStatus; + + agRoot = &(tdsaAllShared->agRootNonInt); + + returnCode = saEncryptGetMode(agRoot,agNULL, &agsaEncryptInfo); + TI_DBG1(("tiCOMEncryptGetInfo: returnCode 0x%x\n", returnCode)); + + if (returnCode == AGSA_RC_SUCCESS) + { + tiStatus = tiSuccess; + + /* + * The data encoded in the agsaEncryptInfo must be converted + * to match the fields of the tiEncryptInfo structure. + * + * No sector information is currently available. + */ + osti_memset(&tiEncryptInfo, 0x0, sizeof(tiEncryptInfo_t)); + + /* cipher mode */ + if (agsaEncryptInfo.encryptionCipherMode == agsaEncryptCipherModeXTS) + { + tiEncryptInfo.securityCipherMode = TI_ENCRYPT_ATTRIB_CIPHER_XTS; + } + /* security mode */ + if (agsaEncryptInfo.encryptionSecurityMode == agsaEncryptSMF) + { + tiEncryptInfo.securityCipherMode |= TI_ENCRYPT_SEC_MODE_FACT_INIT; + } + else if (agsaEncryptInfo.encryptionSecurityMode == agsaEncryptSMA) + { + tiEncryptInfo.securityCipherMode |= TI_ENCRYPT_SEC_MODE_A; + } + else if (agsaEncryptInfo.encryptionSecurityMode == agsaEncryptSMB) + { + tiEncryptInfo.securityCipherMode |= TI_ENCRYPT_SEC_MODE_B; + } + + tiEncryptInfo.status = agsaEncryptInfo.status; + + tiEncryptPort.pData = &tiEncryptInfo; + + /* The low level returns synchronously, so fake a port event now.*/ + tiEncryptPort.encryptEvent = tiEncryptGetInfo; + tiEncryptPort.subEvent = 0; + + ostiPortEvent(tiRoot,tiEncryptOperation,tiStatus,&tiEncryptPort); + } + else + { + if (returnCode == AGSA_RC_NOT_SUPPORTED) + { + tiStatus = tiNotSupported; + TI_DBG1(("tiCOMEncryptGetInfo: tiNotSupported\n")); + } + else + { + TI_DBG1(("tiCOMEncryptGetInfo: tiError returnCode 0x%x\n",returnCode)); + tiStatus = tiError; + } + + tiEncryptPort.pData = NULL; + } + + return(tiStatus); +} + +/***************************************************************************** +* +* tiCOMEncryptSetMode +* +* Purpose: This function is called to set the encryption security and cipher modes +* for the encryption engine. +* +* Parameters: +* +* tiRoot: Pointer to driver/port instance. +* +* Return: +* tiSuccess The request is being processed +* tiError The encryption engine is not in factory init mode or multiple +* security modes were specified. +* +*****************************************************************************/ + +osGLOBAL bit32 tiCOMEncryptSetMode(tiRoot_t *tiRoot, + bit32 securityCipherMode) +{ + bit32 returnCode; + bit32 tiStatus; + agsaEncryptInfo_t mode; + agsaEncryptInfo_t *pmode = &mode; + + tdsaRoot_t *tdsaRoot ; + tdsaContext_t *tdsaAllShared; + agsaRoot_t *agRoot; + + TD_ASSERT(tiRoot, "tiRoot"); + tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + TD_ASSERT(tdsaRoot, "tdsaRoot"); + + tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + TD_ASSERT(tdsaAllShared, "tdsaAllShared"); + agRoot = &(tdsaAllShared->agRootNonInt); + TD_ASSERT(agRoot, "agRoot"); + + pmode->encryptionSecurityMode = 0; + pmode->encryptionCipherMode = 0; + pmode->status = 0; + + TI_DBG1(("tiCOMEncryptSetMode:\n")); + + + if(( securityCipherMode & TI_ENCRYPT_SEC_MODE_A ) == TI_ENCRYPT_SEC_MODE_A) + { + pmode->encryptionSecurityMode = agsaEncryptSMA; + } + + if(( securityCipherMode & TI_ENCRYPT_SEC_MODE_B ) == TI_ENCRYPT_SEC_MODE_B) + { + pmode->encryptionSecurityMode = agsaEncryptSMB; + } + + if( (securityCipherMode & TI_ENCRYPT_ATTRIB_CIPHER_XTS) == TI_ENCRYPT_ATTRIB_CIPHER_XTS) + { + pmode->encryptionCipherMode |= agsaEncryptCipherModeXTS; + } + + /* ECB is not supported in SPCv */ + if(( securityCipherMode & TI_ENCRYPT_ATTRIB_CIPHER_ECB) == TI_ENCRYPT_ATTRIB_CIPHER_ECB) + { + return tiError; + } + + returnCode = saEncryptSetMode(agRoot,agNULL, 0, pmode ); + + if (returnCode == AGSA_RC_SUCCESS) + { + tiStatus = tiSuccess; + } + else if (returnCode == AGSA_RC_BUSY) + { + TI_DBG1(("tiCOMEncryptSetMode:tiBusy\n")); + tiStatus = tiBusy; + } + else + { + TI_DBG1(("tiCOMEncryptSetMode:tiError\n")); + tiStatus = tiError; + } + + return(tiStatus); +} + +/***************************************************************************** +* +* tiCOMEncryptDekAdd +* +* Purpose: This function is called to add a DEK to the controller cache. +* +* Parameters: +* +* tiRoot: Pointer to driver/port instance. +* kekIndext: Index of the KEK table +* dekTableSelect: Number of the DEK table receiving a new entry +* dekAddrHi: Upper 32-bits of the DEK table physical address +* dekAddrLo: Lower 32-bits of the DEK table physical address +* dekIndex: Number of the first entry in the DEK table that will inserted in the cache +* dekNumberOfEntries: Number of entries to be inserted in the cache +* dekBlobFormat: Specifies the DEK blob format +* dekTableKeyEntrySize: Encoded value for DEK Entry Size in the DEK Table +* +* Return: +* tiSuccess The request is being processed +* tiError An invalid parameter was specified +* +*****************************************************************************/ +osGLOBAL bit32 tiCOMEncryptDekAdd(tiRoot_t *tiRoot, + bit32 kekIndex, + bit32 dekTableSelect, + bit32 dekAddrHi, + bit32 dekAddrLo, + bit32 dekIndex, + bit32 dekNumberOfEntries, + bit32 dekBlobFormat, + bit32 dekTableKeyEntrySize + + ) +{ + agsaRoot_t *agRoot; + bit32 returnCode; + bit32 tiStatus; + tdsaRoot_t *tdsaRoot ; + tdsaContext_t *tdsaAllShared ; + + TD_ASSERT(tiRoot, "tiRoot"); + tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + TD_ASSERT(tdsaRoot, "tdsaRoot"); + + tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + TD_ASSERT(tdsaAllShared, "tdsaAllShared"); + agRoot = &(tdsaAllShared->agRootNonInt); + TD_ASSERT(agRoot, "agRoot"); + + + agRoot = &(tdsaAllShared->agRootNonInt); + + + TI_DBG1(("tiCOMEncryptDekAdd:\n" )); + + returnCode = saEncryptDekCacheUpdate(agRoot, + agNULL, + 0, + kekIndex, + dekTableSelect, + dekAddrHi, + dekAddrLo, + dekIndex, + dekNumberOfEntries, + dekBlobFormat, + dekTableKeyEntrySize + ); + + if (returnCode == AGSA_RC_SUCCESS) + { + tiStatus = tiSuccess; + } + else if (returnCode == AGSA_RC_BUSY) + { + tiStatus = tiBusy; + } + else + { + tiStatus = tiError; + } + + return(tiStatus); +} + +/***************************************************************************** +* +* tiCOMEncryptDekInvalidate +* +* Purpose: This function is called to remove a DEK entry from the hardware cache. +* +* Parameters: +* +* tiRoot: Pointer to driver/port instance. +* dekTable DEK table that will be affected +* dekIndex: DEK table entry that will be affected. The value 0xfffffff clears the cache. +* +* Return: +* tiSuccess The request is being processed +* tiError An invalid parameter was specified +* tiBusy An operation is already in progress +* +*****************************************************************************/ + +osGLOBAL bit32 tiCOMEncryptDekInvalidate(tiRoot_t *tiRoot, + bit32 dekTable, + bit32 dekIndex) +{ + + tdsaRoot_t *tdsaRoot; + tdsaContext_t *tdsaAllShared; + + agsaRoot_t *agRoot; + tiEncryptPort_t tiEncryptPort; + tiEncryptDek_t tiEncryptDek; + bit32 returnCode; + bit32 tiStatus; + + TD_ASSERT(tiRoot, "tiRoot"); + tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + TD_ASSERT(tdsaRoot, "tdsaRoot"); + + tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + TD_ASSERT(tdsaAllShared, "tdsaAllShared"); + agRoot = &(tdsaAllShared->agRootNonInt); + TD_ASSERT(agRoot, "agRoot"); + + TI_DBG1(("tiCOMEncryptDekInvalidate:dekTable 0x%x dekIndex 0x%x\n", dekTable, dekIndex)); + + returnCode = saEncryptDekCacheInvalidate(agRoot, agNULL, 0, dekTable, dekIndex); + + if (returnCode == AGSA_RC_SUCCESS) + { + tiStatus = tiSuccess; + } + else + { + if (returnCode == AGSA_RC_NOT_SUPPORTED) + { + tiStatus = tiNotSupported; + } + else if (returnCode == AGSA_RC_BUSY) + { + tiStatus = tiBusy; + } + else + { + tiStatus = tiError; + } + + tiEncryptDek.dekTable = dekTable; + tiEncryptDek.dekIndex = dekIndex; + + tiEncryptPort.encryptEvent = tiEncryptDekInvalidate; + tiEncryptPort.subEvent = 0; + tiEncryptPort.pData = (void *) &tiEncryptDek; + + ostiPortEvent(tiRoot,tiEncryptOperation,tiStatus,&tiEncryptPort); + } + + return(tiStatus); +} + +/***************************************************************************** +* +* tiCOMEncryptKekAdd +* +* Purpose: This function is called to add a KEK in the register specified by +* the index parameter. +* +* Parameters: +* +* tiRoot: Pointer to driver/port instance. +* kekIndex: KEK table entry that will be affected +* wrapperKekIndex KEK table entry that encrypt the KEK blob +* encryptKekBlob KEK blob that will be added +* +* Return: +* tiSuccess The request is being processed +* tiError An invalid parameter was specified +* tiBusy A KEK operation is already in progress +* +*****************************************************************************/ + +osGLOBAL bit32 tiCOMEncryptKekAdd(tiRoot_t *tiRoot, + bit32 kekIndex, + bit32 wrapperKekIndex, + bit32 blobFormat, + tiEncryptKekBlob_t *encryptKekBlob) +{ + tdsaRoot_t *tdsaRoot; + tdsaContext_t *tdsaAllShared; + agsaRoot_t *agRoot; + + bit32 returnCode= AGSA_RC_BUSY; + bit32 tiStatus= tiError; + + tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + + agRoot = &(tdsaAllShared->agRootNonInt); + + TI_DBG1(("tiCOMEncryptDekInvalidate: kekIndex 0x%x wrapperKekIndex 0x%x\n", kekIndex , wrapperKekIndex)); + + returnCode = saEncryptKekUpdate(agRoot, + agNULL, + 0, + AGSA_ENCRYPT_STORE_NVRAM, + kekIndex, + wrapperKekIndex, + blobFormat, + (agsaEncryptKekBlob_t *) encryptKekBlob); + + if (returnCode == AGSA_RC_SUCCESS) + { + tiStatus = tiSuccess; + } + else if (returnCode == AGSA_RC_BUSY) + { + tiStatus = tiBusy; + } + else + { + tiStatus = tiError; + } + + return(tiStatus); +} +#ifdef HIALEAH_ENCRYPTION + +osGLOBAL bit32 tiCOMEncryptHilSet(tiRoot_t *tiRoot ) +{ + tdsaRoot_t *tdsaRoot; + tdsaContext_t *tdsaAllShared; + agsaRoot_t *agRoot; + agsaEncryptInfo_t agsaEncryptInfo; + + bit32 returnCode= tiBusy; + bit32 tiStatus= tiError; + + tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + + agRoot = &(tdsaAllShared->agRootNonInt); + + + returnCode = saEncryptGetMode(agRoot,agNULL, &agsaEncryptInfo); + TI_DBG1(("tiCOMEncryptHilSet: saEncryptGetMode returnCode 0x%x agsaEncryptInfo status 0x%x Smode 0x%x CMode 0x%x\n", + returnCode, + agsaEncryptInfo.status, + agsaEncryptInfo.encryptionSecurityMode, + agsaEncryptInfo.encryptionCipherMode )); + + if (returnCode == AGSA_RC_FAILURE) + { + TI_DBG1(("tiCOMEncryptHilSet:agsaEncryptInfo.status 0x%x\n",agsaEncryptInfo.status )); + if(agsaEncryptInfo.status == 0x81) + { + TI_DBG1(("tiCOMEncryptHilSet: status 0x80 KEY CARD MISMATCH agsaEncryptInfo.status 0x%x\n",agsaEncryptInfo.status )); + returnCode = saEncryptHilUpdate(agRoot, + agNULL, + 0 ); + if (returnCode == AGSA_RC_SUCCESS) + { + TI_DBG1(("tiCOMEncryptHilSet:AGSA_RC_SUCCESS\n")); + } + } + else if(agsaEncryptInfo.status == 0x80) + { + ostidisableEncryption(tiRoot); + TI_DBG1(("tiCOMEncryptHilSet: status 0x80 KEY CARD MISSING agsaEncryptInfo.status 0x%x\n",agsaEncryptInfo.status )); + returnCode = AGSA_RC_SUCCESS; + } + else + { + TI_DBG1(("tiCOMEncryptHilSet: not status 0x81 agsaEncryptInfo.status 0x%x\n",agsaEncryptInfo.status )); + returnCode = AGSA_RC_FAILURE; + } + } + + if (returnCode == AGSA_RC_SUCCESS) + { + tiStatus = tiSuccess; + } + else if (returnCode == AGSA_RC_BUSY) + { + TI_DBG1(("tiCOMEncryptHilSet:AGSA_RC_BUSY\n")); + tiStatus = tiBusy; + } + else + { + TI_DBG1(("tiCOMEncryptHilSet:tiError\n")); + tiStatus = tiError; + } + + return(tiStatus); +} +#endif /* HIALEAH_ENCRYPTION */ + +/***************************************************************************** +* +* tiCOMEncryptKekStore +* +* Purpose: This function is called to store a KEK in NVRAM. If -1 is specified +* as the KEK index, then all KEKs will be stored. +* +* Parameters: +* +* tiRoot: Pointer to driver/port instance. +* kekIndex: The KEK to be stored in NVRAM +* +* Return: +* tiSuccess The request is being processed +* tiError An invalid parameter was specified +* tiBusy A KEK operation is already in progress +* +*****************************************************************************/ + +osGLOBAL bit32 tiCOMEncryptKekStore(tiRoot_t *tiRoot, + bit32 kekIndex) +{ +#ifdef NOT_YET + tdsaRoot_t *tdsaRoot; + tdsaContext_t *tdsaAllShared; + agsaRoot_t *agRoot; +#endif +/* + bit32 returnCode= AGSA_RC_BUSY; +*/ + bit32 tiStatus = tiError; + +#ifdef NOT_YET + tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + + agRoot = &(tdsaAllShared->agRootNonInt); +#endif + + TI_DBG1(("tiCOMEncryptKekStore: Needs code !!!! kekIndex 0x%x\n", kekIndex )); +/* + returnCode = fcEncryptKekStore(agRoot, kekIndex); + + if (returnCode == AGSA_RC_SUCCESS) + { + tiStatus = tiSuccess; + } + else if (returnCode == AGSA_RC_BUSY) + { + tiStatus = tiBusy; + } + else + { + tiStatus; + } +*/ + return(tiStatus); +} + +/***************************************************************************** +* +* tiCOMEncryptKekLoad +* +* Purpose: This function is called to load a KEK from NVRAM. If -1 is specified +* as the KEK index, then all KEKs will be loaded. +* +* Parameters: +* +* tiRoot: Pointer to driver/port instance. +* kekIndex: The KEK to be loaded in NVRAM +* +* Return: +* tiSuccess The request is being processed +* tiError An invalid parameter was specified +* tiBusy A KEK operation is already in progress +* +*****************************************************************************/ + +osGLOBAL bit32 tiCOMEncryptKekLoad(tiRoot_t *tiRoot, + bit32 kekIndex) +{ +#ifdef NOT_YET + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + agsaRoot_t *agRoot; + //bit32 returnCode; +#endif + bit32 tiStatus = tiError; + +#ifdef NOT_YET + agRoot = &(tdsaAllShared->agRootNonInt); +#endif +/* + returnCode = fcEncryptKekLoad(agRoot, kekIndex); + + if (returnCode == AGSA_RC_SUCCESS) + { + tiStatus = tiSuccess; + } + else if (returnCode == AGSA_RC_BUSY) + { + tiStatus = tiBusy; + } + else + { + tiStatus = tiError; + } +*/ + return(tiStatus); +} + +/***************************************************************************** +* +* tiCOMEncryptSelfTest +* +* Purpose: This function starts the encryption self test. For the encryption self test, IOs must be quiesced. +* The completion of this function is via ostiPortEvent(). +* +* Parameters: +* +* tiRoot: Pointer to driver/port instance. +* type: Types of test + 0x1: tiBISTTest + 0x2: tiHMACTest + Others are reserved. +* length: + Size of the test descriptor in bytes, e.g., + Sizeof(tiEncryptSelfTestDescriptor_t) + Sizeof(tiEncryptHMACTestDescriptor_t) +* TestDescriptor address of the test descriptor structure. +* +* Return: +* tiSuccess The request is being processed +* tiError An invalid parameter was specified +* tiBusy A encrytion operation is already in progress +* +*****************************************************************************/ +osGLOBAL bit32 tiCOMEncryptSelfTest( + tiRoot_t *tiRoot, + bit32 type, + bit32 length, + void *TestDescriptor + ) +{ + tdsaRoot_t *tdsaRoot = agNULL; + tdsaContext_t *tdsaAllShared = agNULL; + agsaRoot_t *agRoot = agNULL; + + bit32 returnCode = AGSA_RC_BUSY; + bit32 tiStatus = tiError; + + tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + TD_ASSERT(tdsaRoot != agNULL, "tdsaRoot is NULL !!!"); + + tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + TD_ASSERT(tdsaAllShared != agNULL, "tdsaAllShared is NULL !!!"); + + agRoot = &(tdsaAllShared->agRootNonInt); + TD_ASSERT(agRoot != agNULL, "agRoot is NULL !!!"); + + TI_DBG1(("tiCOMEncryptSelfTest: type = 0x%x length = 0x%x\n", type, length)); + + /*do some sanity checking */ + if ( ((type == TI_ENCRYPTION_TEST_TYPE_BIST) && (length != sizeof(tiEncryptSelfTestDescriptor_t ))) || + ((type == TI_ENCRYPTION_TEST_TYPE_HMAC) && (length != sizeof(tiEncryptHMACTestDescriptor_t))) ) + { + TI_DBG1(("tiCOMEncryptSelfTest: type or length error, type 0x%x length 0x%x\n", type, length)); + tiStatus = tiError; + } + else + { + returnCode = saEncryptSelftestExecute(agRoot, + agNULL, + 0, + type, + length, + TestDescriptor + ); + + if (returnCode == AGSA_RC_SUCCESS) + { + tiStatus = tiSuccess; + } + else if (returnCode == AGSA_RC_BUSY) + { + tiStatus = tiBusy; + } + else + { + tiStatus = tiError; + } + } + + return(tiStatus); +} + +/***************************************************************************** +* +* tiCOMSetOperator +* +* Purpose: This function is called to login to or logout out from the controller by an operator. + The status is reported via ostiPortEvent(). +* +* Parameters: +* +* tiRoot: Pointer to driver/port instance. +* flag: operator flag. + Bits 0-3: Access type (ACS) + 0x1: Login + 0x2: Logout + All others are reserved. + Bit 4: KEYopr pinned in the KEK table (PIN) + 0: Not pinned. Operator ID table will be searched during authentication. + 1: Pinned. OPRIDX is referenced to unwrap the certificate. + Bits 5-7: Reserved + Bits 8-15: KEKopr Index in the KEK Table (OPRIDX). If KEKopr is pinned in the KEK table, OPRIDX is to reference the KEK for authentication + Bits 16-31: Reserved. + + cert: The pointer to the operator's certificate. The size of the certificate is 40 bytes. +* +* Return: +* tiSuccess Log in or log out was started. +* tiError Log in or log out was not started. +* tiBusy A operator management operation is already in progress +* +*****************************************************************************/ +osGLOBAL bit32 tiCOMSetOperator( + tiRoot_t *tiRoot, + bit32 flag, + void *cert + ) +{ + tdsaRoot_t *tdsaRoot = agNULL; + tdsaContext_t *tdsaAllShared = agNULL; + agsaRoot_t *agRoot = agNULL; + + bit32 returnCode = AGSA_RC_FAILURE; + bit32 tiStatus = tiError; + + tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + TD_ASSERT(tdsaRoot != agNULL, "tdsaRoot is NULL !!!"); + + tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + TD_ASSERT(tdsaAllShared != agNULL, "tdsaAllShared is NULL !!!"); + + agRoot = &(tdsaAllShared->agRootNonInt); + TD_ASSERT(agRoot != agNULL, "agRoot is NULL !!!"); + + TI_DBG1(("tiCOMSetOperator: flag = 0x%x \n", flag)); + + returnCode = saSetOperator(agRoot, + agNULL, + 0, + flag, + cert); + + if (returnCode == AGSA_RC_SUCCESS) + { + tiStatus = tiSuccess; + } + else if (returnCode == AGSA_RC_BUSY) + { + tiStatus = tiBusy; + } + else + { + tiStatus = tiError; + } + + return(tiStatus); +} + +/***************************************************************************** +* +* tiCOMGetOperator +* +* Purpose: This function is used to retrieve the role and ID of the current operator or all operators. + The status is reported via ostiPortEvent(). +* +* Parameters: +* +* tiRoot: Pointer to driver/port instance. +* option: Types of get operations + 0x1: Current operator only + 0x2: All operators + All others are reserved. + AddrHi Upper 32-bit host physical address to store operator certificates. + This field is used only when option is 0x2 + AddrLo Lower 32-bit host physical address to store operator certificates. + This field is used only when option is 0x2 +* +* Return: +* tiSuccess The operation was started.. +* tiError The operation was not started. +* tiBusy A operator management operation is already in progress +* +*****************************************************************************/ +osGLOBAL bit32 tiCOMGetOperator( + tiRoot_t *tiRoot, + bit32 option, + bit32 AddrHi, + bit32 AddrLo + ) +{ + tdsaRoot_t *tdsaRoot = agNULL; + tdsaContext_t *tdsaAllShared = agNULL; + agsaRoot_t *agRoot = agNULL; + + bit32 returnCode = AGSA_RC_FAILURE; + bit32 tiStatus = tiError; + + tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + TD_ASSERT(tdsaRoot != agNULL, "tdsaRoot is NULL !!!"); + + tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + TD_ASSERT(tdsaAllShared != agNULL, "tdsaAllShared is NULL !!!"); + + agRoot = &(tdsaAllShared->agRootNonInt); + TD_ASSERT(agRoot != agNULL, "agRoot is NULL !!!"); + + TI_DBG1(("tiCOMGetOperator: option = 0x%x \n", option)); + + returnCode = saGetOperator(agRoot, + agNULL, + 0, + option, + AddrHi, + AddrLo); + + if (returnCode == AGSA_RC_SUCCESS) + { + tiStatus = tiSuccess; + } + else if (returnCode == AGSA_RC_BUSY) + { + tiStatus = tiBusy; + } + else + { + tiStatus = tiError; + } + + return(tiStatus); +} + +/***************************************************************************** +* +* tiCOMOperationManagement +* +* Purpose: this function is used to manage operators, e.g. adding or deleting an operator.. +* +* Parameters: +* +* tiRoot: Pointer to driver/port instance. +* flag: operation flag. + Bits 0-7: Operator Management Operation(OMO) + 0: Add an operator. + 1: Delete an operator. + 2: Delete all operators. + Others are reserved. + Bit 8: Pinned to KEK RAM (PKR) + 0: Operator's KEK is stored in the operator ID table(OID_TLB) only. + 1: Operator's KEK is pinned to the internal KEK RAM (1 of the 16 entries) and is also stored in OID_TLB. + Bits 9-10: KEKopr blob format (KBF) + 00b: Reserved. + 01b: AGSA_ENCRYPTED_KEK_PMCA. + 10b: AGSA_ENCRYPTED_KEK_PMCB. + 11b: Reserved. + Bits 11-15: Reserved + Bits 16-23: KEKauth Index in the KEK Table (AUTIDX) + Bits 24-31: KEKopr Index in the KEK Table (OPRIDX). This field is valid only when PKR is 1. + + role Role + 01b: Crypto officer role. + 10b: User role. + All others are reserved. + +* idString: Pointer to the tiID_t structure describing the ID string +* kekBlob Pointer to the tiEncryptKekBlob_t structure describing KBLOB. +* +* Return: +* tiSuccess The request is being processed +* tiError An invalid parameter was specified +* tiBusy A operator management operation is already in progress +* +*****************************************************************************/ +osGLOBAL bit32 tiCOMOperatorManagement( + tiRoot_t *tiRoot, + bit32 flag, + bit8 role, + tiID_t *idString, + tiEncryptKekBlob_t *kekBlob + ) +{ + tdsaRoot_t *tdsaRoot = agNULL; + tdsaContext_t *tdsaAllShared = agNULL; + agsaRoot_t *agRoot = agNULL; + + bit32 returnCode = AGSA_RC_BUSY; + bit32 tiStatus = tiError; + + tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + TD_ASSERT(tdsaRoot != agNULL, "tdsaRoot is NULL !!!"); + + tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + TD_ASSERT(tdsaAllShared != agNULL, "tdsaAllShared is NULL !!!"); + + agRoot = &(tdsaAllShared->agRootNonInt); + TD_ASSERT(agRoot != agNULL, "agRoot is NULL !!!"); + + TI_DBG1(("tiCOMOperatorManagement: flag = 0x%x role = 0x%x\n", flag, role)); + + returnCode = saOperatorManagement(agRoot, + agNULL, + 0, + flag, + role, + (agsaID_t*)idString, + (agsaEncryptKekBlob_t *)kekBlob + ); + + if (returnCode == AGSA_RC_SUCCESS) + { + tiStatus = tiSuccess; + } + else if (returnCode == AGSA_RC_BUSY) + { + tiStatus = tiBusy; + } + else + { + tiStatus = tiError; + } + + return(tiStatus); +} + +/***************************************************************************** +*! \brief tdssRemoveSASSATAFromSharedcontext +* +* Purpose: This function removes all discovered devices belonging to +* a given portcontext from device list +* +* +* \param agRoot Pointer to the root data structure of +* TD and Lower layer +* \param tsddPortContext_Instance Pointer to the target port context +* +* \Return: none +* +*****************************************************************************/ +#ifdef INITIATOR_DRIVER /*TBD: added to compile tgt_drv. (TP)*/ +osGLOBAL void +tdssRemoveSASSATAFromSharedcontext( + agsaRoot_t *agRoot, + tdsaPortContext_t *PortContext_Instance + ) +{ + tdsaDeviceData_t *oneDeviceData = agNULL; + tdList_t *DeviceListList; + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + + TI_DBG1(("tdssRemoveSASSATAFromSharedcontext: start\n")); + TI_DBG1(("tdssRemoveSASSATAFromSharedcontext: pid %d\n", PortContext_Instance->id)); + + /* find oneDeviceData belonging to the portcontext */ + DeviceListList = tdsaAllShared->MainDeviceList.flink; + while (DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + TI_DBG1(("tdssRemoveSASSATAFromSharedcontext: oneDeviceData is NULL!!!\n")); + return; + } + if (oneDeviceData->tdPortContext == PortContext_Instance) + { + TI_DBG1(("tdssRemoveSASSATAFromSharedcontext: pid %d did %d\n", PortContext_Instance->id, oneDeviceData->id)); + TI_DBG1(("tdssRemoveSASSATAFromSharedcontext: sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG1(("tdssRemoveSASSATAFromSharedcontext: sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + + /* reset valid bit */ + oneDeviceData->valid = agFALSE; + oneDeviceData->valid2 = agFALSE; + oneDeviceData->registered = agFALSE; + /* notify only reported devices to OS layer*/ + if ( DEVICE_IS_SSP_TARGET(oneDeviceData) || + DEVICE_IS_STP_TARGET(oneDeviceData) || + DEVICE_IS_SATA_DEVICE(oneDeviceData) + ) + { + ostiInitiatorEvent( + tiRoot, + PortContext_Instance->tiPortalContext, + &(oneDeviceData->tiDeviceHandle), + tiIntrEventTypeDeviceChange, + tiDeviceRemoval, + agNULL + ); + } + DeviceListList = DeviceListList->flink; + /* to-do: deregister */ +#ifdef REMOVED /* don't remove device from the device list. May screw up ordering */ + TDLIST_DEQUEUE_THIS(&(oneDeviceData->MainLink)); + TDLIST_ENQUEUE_AT_TAIL(&(oneDeviceData->FreeLink), &(tdsaAllShared->FreeDeviceList)); +#endif + } + else + { + TI_DBG6(("tdssRemoveSASSATAFromSharedcontext: move to the next\n")); + DeviceListList = DeviceListList->flink; + } + } /* while */ + + return; +} + +/***************************************************************************** +*! \brief tdssRemoveSASSATAFromSharedcontextByReset +* +* Purpose: This function removes all ports and discovered devices +* +* +* \param agRoot Pointer to the root data structure of +* TD and Lower layer +* +* \Return: none +* +*****************************************************************************/ +osGLOBAL void +tdssRemoveSASSATAFromSharedcontextByReset( + agsaRoot_t *agRoot + ) +{ + tdsaPortContext_t *onePortContext = agNULL; + tdsaDeviceData_t *oneDeviceData = agNULL; + tdList_t *PortContextList; + tdList_t *DeviceListList; + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; +#ifdef FDS_DM + dmRoot_t *dmRoot = agNULL; + dmPortContext_t *dmPortContext = agNULL; + dmPortInfo_t dmPortInfo; +#endif +#ifdef FDS_SM + smRoot_t *smRoot = &(tdsaAllShared->smRoot); + smDeviceHandle_t *smDeviceHandle = agNULL; + agsaDevHandle_t *agDevHandle = agNULL; +#endif + + TI_DBG1(("tdssRemoveSASSATAFromSharedcontextByReset: start\n")); + +#ifdef FDS_DM + dmRoot = &(tdsaAllShared->dmRoot); +#endif + /* looping throuhg all portcontext */ + PortContextList = tdsaAllShared->MainPortContextList.flink; + while (PortContextList != &(tdsaAllShared->MainPortContextList)) + { + onePortContext = TDLIST_OBJECT_BASE(tdsaPortContext_t, MainLink, PortContextList); + if (onePortContext == agNULL) + { + TI_DBG1(("tdssRemoveSASSATAFromSharedcontextByReset: onePortContext is NULL!!!\n")); + return; + } + TI_DBG1(("tdssRemoveSASSATAFromSharedcontextByReset: oneportContext pid %d\n", onePortContext->id)); + TI_DBG3(("tdssRemoveSASSATAFromSharedcontextByReset: sasAddressHi 0x%08x\n", onePortContext->sasLocalAddressHi)); + TI_DBG3(("tdssRemoveSASSATAFromSharedcontextByReset: sasAddressLo 0x%08x\n", onePortContext->sasLocalAddressLo)); +#ifdef FDS_DM + if (onePortContext->UseDM == agTRUE) + { + dmPortContext = &(onePortContext->dmPortContext); + dmDestroyPort(dmRoot, dmPortContext, &dmPortInfo); + } +#endif + + tdsaPortContextReInit(tiRoot, onePortContext); + + PortContextList = PortContextList->flink; + tdsaSingleThreadedEnter(tiRoot, TD_PORT_LOCK); + TDLIST_DEQUEUE_THIS(&(onePortContext->MainLink)); + TDLIST_ENQUEUE_AT_TAIL(&(onePortContext->FreeLink), &(tdsaAllShared->FreePortContextList)); + tdsaSingleThreadedLeave(tiRoot, TD_PORT_LOCK); + } + + /* reinitialize the device data belonging to this portcontext */ + DeviceListList = tdsaAllShared->MainDeviceList.flink; + while (DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + TI_DBG1(("tdssRemoveSASSATAFromSharedcontextByReset: oneDeviceData is NULL!!!\n")); + return; + } + + TI_DBG1(("tdssRemoveSASSATAFromSharedcontextByReset: did %d\n", oneDeviceData->id)); + TI_DBG1(("tdssRemoveSASSATAFromSharedcontextByReset: sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG1(("tdssRemoveSASSATAFromSharedcontextByReset: sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + +#ifdef FDS_SM + agDevHandle = oneDeviceData->agDevHandle; + smDeviceHandle = (smDeviceHandle_t *)&(oneDeviceData->smDeviceHandle); + smDeregisterDevice(smRoot, agDevHandle, smDeviceHandle); +#endif + + tdsaDeviceDataReInit(tiRoot, oneDeviceData); + + DeviceListList = DeviceListList->flink; + tdsaSingleThreadedEnter(tiRoot, TD_DEVICE_LOCK); + osti_memset(&(oneDeviceData->satDevData.satIdentifyData), 0xFF, sizeof(agsaSATAIdentifyData_t)); + TDLIST_DEQUEUE_THIS(&(oneDeviceData->MainLink)); + TDLIST_ENQUEUE_AT_TAIL(&(oneDeviceData->FreeLink), &(tdsaAllShared->FreeDeviceList)); + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + /* no dequeue from Mainlink for consistant ordering of devices */ + } + + + return; +} + +#endif + + +/***************************************************************************** +*! \brief tdssAddSASToSharedcontext +* +* Purpose: This function adds a discovered device to a device list of +* a shared context +* +* \param tsddPortContext_Instance Pointer to the target port context +* \param agRoot Pointer to the root data structure of +* TD and Lower layer +* \param agDevHandle Pointer to a device handle +* +* \Return: none +* +*****************************************************************************/ +osGLOBAL void +tdssAddSASToSharedcontext( + tdsaPortContext_t *tdsaPortContext_Instance, + agsaRoot_t *agRoot, + agsaDevHandle_t *agDevHandle, /* this is NULL */ + tdsaSASSubID_t *agSASSubID, + bit32 registered, /* no longer in use */ + bit8 phyID, + bit32 flag + ) +{ + + tdsaPortContext_t *onePortContext = agNULL; + tdList_t *PortContextList; + tdsaDeviceData_t *oneDeviceData = agNULL; + tdList_t *DeviceListList; + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + bit32 new_device = agTRUE; + bit32 Indenom = tdsaAllShared->QueueConfig.numInboundQueues; + bit32 Outdenom = tdsaAllShared->QueueConfig.numOutboundQueues; + bit8 dev_s_rate = 0; + bit8 sasorsata = 1; + bit8 connectionRate; + bit32 found = agFALSE; + + TI_DBG3(("tdssAddSASToSharedcontext: start\n")); + /* + find a right portcontext + then, get devicedata from FreeLink in DeviceList + then, do pointer operations + then, add the devicedata to the portcontext + */ + + /* find a right portcontext */ + PortContextList = tdsaAllShared->MainPortContextList.flink; + while (PortContextList != &(tdsaAllShared->MainPortContextList)) + { + onePortContext = TDLIST_OBJECT_BASE(tdsaPortContext_t, MainLink, PortContextList); + if (onePortContext == tdsaPortContext_Instance) + { + TI_DBG3(("tdssAddSASToSharedContext: found; oneportContext ID %d\n", onePortContext->id)); + found = agTRUE; + break; + } + PortContextList = PortContextList->flink; + } + + if (found == agTRUE) + { + TI_DBG3(("tdssAddSASToSharedcontext: found pid %d\n", onePortContext->id)); + } + else + { + TI_DBG1(("tdssAddSASToSharedcontext: Error!!! no portcontext found!!!\n")); + return; + } + + /* find a device's existence */ + DeviceListList = tdsaAllShared->MainDeviceList.flink; + while (DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + TI_DBG1(("tdssAddSASToSharedcontext: oneDeviceData is NULL!!!\n")); + return; + } + if ((oneDeviceData->SASAddressID.sasAddressHi == agSASSubID->sasAddressHi) && + (oneDeviceData->SASAddressID.sasAddressLo == agSASSubID->sasAddressLo) && + (oneDeviceData->tdPortContext == onePortContext) + ) + { + TI_DBG1(("tdssAddSASToSharedcontext: pid %d did %d\n", onePortContext->id, oneDeviceData->id)); + new_device = agFALSE; + break; + } + DeviceListList = DeviceListList->flink; + } + + /* new device */ + if (new_device == agTRUE) + { + TI_DBG3(("tdssAddSASToSharedcontext: new device\n")); + + tdsaSingleThreadedEnter(tiRoot, TD_DEVICE_LOCK); + if (!TDLIST_NOT_EMPTY(&(tdsaAllShared->FreeDeviceList))) + { + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + TI_DBG1(("tdssAddSASToSharedContext: empty DeviceData FreeLink\n")); + return; + } + + TDLIST_DEQUEUE_FROM_HEAD(&DeviceListList, &(tdsaAllShared->FreeDeviceList)); + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, FreeLink, DeviceListList); + + TI_DBG3(("tdssAddSASToSharedcontext: oneDeviceData %p\n", oneDeviceData)); + + onePortContext->Count++; + oneDeviceData->DeviceType = TD_SAS_DEVICE; + oneDeviceData->agRoot = agRoot; + + if (flag == TD_OPERATION_TARGET) + { + oneDeviceData->agDevHandle = agDevHandle; + agDevHandle->osData = oneDeviceData; /* TD layer */ + } + + /* saving sas address */ + oneDeviceData->SASAddressID.sasAddressLo = agSASSubID->sasAddressLo; + oneDeviceData->SASAddressID.sasAddressHi = agSASSubID->sasAddressHi; + oneDeviceData->initiator_ssp_stp_smp = agSASSubID->initiator_ssp_stp_smp; + oneDeviceData->target_ssp_stp_smp = agSASSubID->target_ssp_stp_smp; + + oneDeviceData->tdPortContext = onePortContext; + oneDeviceData->valid = agTRUE; + + /* new */ + oneDeviceData->directlyAttached = agTRUE; + /* parse sasIDframe to fill in agDeviceInfo */ + DEVINFO_PUT_SMPTO(&oneDeviceData->agDeviceInfo, DEFAULT_SMP_TIMEOUT); + DEVINFO_PUT_ITNEXUSTO(&oneDeviceData->agDeviceInfo, (bit16)tdsaAllShared->itNexusTimeout); + DEVINFO_PUT_FBS(&oneDeviceData->agDeviceInfo, 0); + /* enable TLR */ + DEVINFO_PUT_FLAG(&oneDeviceData->agDeviceInfo, 1); + + sasorsata = SAS_DEVICE_TYPE; /* SAS target (SAS disk or expander) */ + connectionRate = onePortContext->LinkRate; + dev_s_rate = (bit8)(dev_s_rate | (sasorsata << 4)); + dev_s_rate = (bit8)(dev_s_rate | connectionRate); + DEVINFO_PUT_DEV_S_RATE(&oneDeviceData->agDeviceInfo, dev_s_rate); + + + DEVINFO_PUT_SAS_ADDRESSLO( + &oneDeviceData->agDeviceInfo, + agSASSubID->sasAddressLo + ); + DEVINFO_PUT_SAS_ADDRESSHI( + &oneDeviceData->agDeviceInfo, + agSASSubID->sasAddressHi + ); + + oneDeviceData->agContext.osData = oneDeviceData; + oneDeviceData->agContext.sdkData = agNULL; + + if (flag == TD_OPERATION_INITIATOR) + { + if (oneDeviceData->registered == agFALSE ) + { + if( tdsaAllShared->sflag ) + { + if( ! DEVICE_IS_SMP_TARGET(oneDeviceData)) + { + TI_DBG1(("tdssAddSASToSharedcontext: First, saRegisterNewDevice sflag %d\n", tdsaAllShared->sflag)); + oneDeviceData->agDeviceInfo.flag = oneDeviceData->agDeviceInfo.flag | TD_XFER_RDY_PRIORTY_DEVICE_FLAG; + } + } + + saRegisterNewDevice( /* tdssAddSASToSharedcontext */ + agRoot, + &oneDeviceData->agContext, + 0, + &oneDeviceData->agDeviceInfo, + onePortContext->agPortContext, + 0 + ); + } + } + oneDeviceData->phyID = phyID; + oneDeviceData->InQID = oneDeviceData->id % Indenom; + +#ifdef TARGET_DRIVER + { + bit32 localId = oneDeviceData->id; + localId += 1; + oneDeviceData->OutQID = localId % Outdenom; + TI_DBG1(("tdssAddSASToSharedcontext: OutQID %d\n", oneDeviceData->OutQID)); /* tdsaRotateQnumber for tgt*/ + + } +#endif /* TARGET_DRIVER */ + + TI_DBG4(("tdssAddSASToSharedcontext: SSP target %d STP target %d SATA device %d\n", DEVICE_IS_SSP_TARGET(oneDeviceData), DEVICE_IS_STP_TARGET(oneDeviceData), DEVICE_IS_SATA_DEVICE(oneDeviceData))); + /* add the devicedata to the portcontext */ + tdsaSingleThreadedEnter(tiRoot, TD_DEVICE_LOCK); + TDLIST_ENQUEUE_AT_TAIL(&(oneDeviceData->MainLink), &(tdsaAllShared->MainDeviceList)); + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + TI_DBG4(("tdssAddSASToSharedContext: one case pid %d did %d \n", onePortContext->id, oneDeviceData->id)); + TI_DBG4(("tdssAddSASToSharedContext: new case pid %d did %d phyID %d\n", onePortContext->id, oneDeviceData->id, oneDeviceData->phyID)); + + } + else /* old device */ + { + TI_DBG3(("tdssAddSASToSharedcontext: old device\n")); + TI_DBG3(("tdssAddSASToSharedcontext: oneDeviceData %p\n", oneDeviceData)); + + oneDeviceData->DeviceType = TD_SAS_DEVICE; + oneDeviceData->agRoot = agRoot; + + if (flag == TD_OPERATION_TARGET) + { + oneDeviceData->agDevHandle = agDevHandle; + agDevHandle->osData = oneDeviceData; /* TD layer */ + } + + /* saving sas address */ + oneDeviceData->SASAddressID.sasAddressLo = agSASSubID->sasAddressLo; + oneDeviceData->SASAddressID.sasAddressHi = agSASSubID->sasAddressHi; + oneDeviceData->initiator_ssp_stp_smp = agSASSubID->initiator_ssp_stp_smp; + oneDeviceData->target_ssp_stp_smp = agSASSubID->target_ssp_stp_smp; + + + oneDeviceData->tdPortContext = onePortContext; + oneDeviceData->valid = agTRUE; + + oneDeviceData->directlyAttached = agTRUE; + /* new */ + if (oneDeviceData->registered == agFALSE) + { + TI_DBG1(("tdssAddSASToSharedcontext: registering\n")); + /* parse sasIDframe to fill in agDeviceInfo */ + DEVINFO_PUT_SMPTO(&oneDeviceData->agDeviceInfo, DEFAULT_SMP_TIMEOUT); + DEVINFO_PUT_ITNEXUSTO(&oneDeviceData->agDeviceInfo, (bit16)tdsaAllShared->itNexusTimeout); + DEVINFO_PUT_FBS(&oneDeviceData->agDeviceInfo, 0); + DEVINFO_PUT_FLAG(&oneDeviceData->agDeviceInfo, 1); + + sasorsata = SAS_DEVICE_TYPE; /* SAS target (SAS disk or expander) */ + connectionRate = onePortContext->LinkRate; + dev_s_rate = (bit8)(dev_s_rate | (sasorsata << 4)); + dev_s_rate = (bit8)(dev_s_rate | connectionRate); + DEVINFO_PUT_DEV_S_RATE(&oneDeviceData->agDeviceInfo, dev_s_rate); + + + DEVINFO_PUT_SAS_ADDRESSLO( + &oneDeviceData->agDeviceInfo, + agSASSubID->sasAddressLo + ); + DEVINFO_PUT_SAS_ADDRESSHI( + &oneDeviceData->agDeviceInfo, + agSASSubID->sasAddressHi + ); + + oneDeviceData->agContext.osData = oneDeviceData; + oneDeviceData->agContext.sdkData = agNULL; + + if (flag == TD_OPERATION_INITIATOR) + { + if( tdsaAllShared->sflag ) + { + if( ! DEVICE_IS_SMP_TARGET(oneDeviceData)) + { + TI_DBG1(("tdssAddSASToSharedcontext: Second, saRegisterNewDevice sflag %d\n", tdsaAllShared->sflag)); + oneDeviceData->agDeviceInfo.flag = oneDeviceData->agDeviceInfo.flag | TD_XFER_RDY_PRIORTY_DEVICE_FLAG; + } + } + saRegisterNewDevice( /* tdssAddSASToSharedcontext */ + agRoot, + &oneDeviceData->agContext, + 0, + &oneDeviceData->agDeviceInfo, + onePortContext->agPortContext, + 0 + ); + } + } + + + + + + + oneDeviceData->phyID = phyID; + oneDeviceData->InQID = oneDeviceData->id % Indenom; + oneDeviceData->OutQID = oneDeviceData->id % Outdenom; + + TI_DBG1(("tdssAddSASToSharedcontext: A OutQID %d\n", oneDeviceData->OutQID)); + TI_DBG4(("tdssAddSASToSharedcontext: SSP target %d STP target %d SATA device %d\n", DEVICE_IS_SSP_TARGET(oneDeviceData), DEVICE_IS_STP_TARGET(oneDeviceData), DEVICE_IS_SATA_DEVICE(oneDeviceData))); + TI_DBG4(("tdssAddSASToSharedContext: old case pid %d did %d phyID %d\n", onePortContext->id, oneDeviceData->id, oneDeviceData->phyID)); + } + + return; +} + + + + +/***************************************************************************** +*! \brief tdssRemoveDevicedataFromSharedcontext +* +* Purpose: This function removes a discovered device from a device list of +* a port context +* +* \param tsddPortContext_Ins Pointer to the target port context +* \param tdsaDeviceData_Ins Pointer to the target device +* \param agRoot Pointer to the root data structure of +* TD and Lower layer + +* +* \Return: none +* +*****************************************************************************/ +osGLOBAL void +tdssRemoveSASFromSharedcontext( + tdsaPortContext_t *tdsaPortContext_Ins, + tdsaDeviceData_t *tdsaDeviceData_Ins, + agsaRoot_t *agRoot + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdsaPortContext_t *onePortContext = agNULL; + tdList_t *PortContextList; + tdsaDeviceData_t *oneDeviceData = agNULL; + tdList_t *DeviceListList; + bit32 found = agTRUE; + + TI_DBG3(("tdssRemoveSASFromSharedcontext: start\n")); + /* find a right portcontext */ + PortContextList = tdsaAllShared->MainPortContextList.flink; + while (PortContextList != &(tdsaAllShared->MainPortContextList)) + { + onePortContext = TDLIST_OBJECT_BASE(tdsaPortContext_t, MainLink, PortContextList); + if (onePortContext == agNULL) + { + TI_DBG1(("tdssRemoveDevicedataFromSharedcontext: onePortContext is NULL!!!\n")); + return; + } + if (onePortContext == tdsaPortContext_Ins) + { + TI_DBG4(("tdssRemoveDevicedataFromSharedcontext: found; oneportContext ID %d\n", onePortContext->id)); + break; + } + PortContextList = PortContextList->flink; + } + + /* find a device's existence */ + DeviceListList = tdsaAllShared->MainDeviceList.flink; + while (DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + TI_DBG1(("tdssRemoveDevicedataFromSharedcontext: oneDeviceData is NULL!!!\n")); + return; + } + if ((oneDeviceData->SASAddressID.sasAddressHi + == SA_DEVINFO_GET_SAS_ADDRESSHI(&tdsaDeviceData_Ins->agDeviceInfo)) + && + (oneDeviceData->SASAddressID.sasAddressLo == + SA_DEVINFO_GET_SAS_ADDRESSLO(&tdsaDeviceData_Ins->agDeviceInfo))) + { + TI_DBG4(("tdssRemoveDevicedataFromSharedcontext: pid %d did %d\n", onePortContext->id, oneDeviceData->id)); + found = agFALSE; + break; + } + DeviceListList = DeviceListList->flink; + } + + if (found == agFALSE) + { + TI_DBG6(("tdssRemoveDevicedataFromSharedcontext: can't find the right devicedata in MainLink\n")); + return; + } + + /* remove it and put it back to FreeLink of Devicedata */ + TI_DBG6(("tdssRemoveDevicedataFromSharedcontext: removing ... pid %d did %d\n", onePortContext->id, oneDeviceData->id)); + + /* invalidate the device but keep it on the list for persistency */ + oneDeviceData->valid = agFALSE; + + return; +} + +/***************************************************************************** +*! \brief tdssRemoveAllDevicedataFromPortcontext +* +* Purpose: This function removes all discovered devices from a device list of +* a port context +* +* \param tdsaDeviceData Pointer to a device header +* +* \Return: none +* +*****************************************************************************/ +osGLOBAL void +tdssRemoveAllDevicelistFromPortcontext( + tdsaPortContext_t *PortContext_Ins, + agsaRoot_t *agRoot + ) +{ + + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdsaDeviceData_t *oneDeviceData = agNULL; + tdList_t *DeviceListList; + + TI_DBG6(("tdssRemoveAllDevicedataFromPortcontext: start\n")); + + /* + loop through device list and find the matching portcontext. Then invalidate the + matching devices + */ + DeviceListList = tdsaAllShared->MainDeviceList.flink; + while (DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + TI_DBG1(("tdssRemoveAllDevicelistFromPortcontext: oneDeviceData is NULL!!!\n")); + return; + } + if (oneDeviceData->tdPortContext == PortContext_Ins) + { + TI_DBG4(("tdssRemoveAllDevicelistFromPortcontext: pid %d did %d\n", PortContext_Ins->id, oneDeviceData->id)); + PortContext_Ins->Count--; + oneDeviceData->valid = agFALSE; + } + DeviceListList = DeviceListList->flink; + } + + return; +} + + +#ifdef INITIATOR_DRIVER +#ifdef TD_DISCOVER +/***************************************************************************** +*! \brief tdssNewAddSASToSharedcontext +* +* Purpose: This function adds a discovered SAS device to a device list of +* a shared context. Used only in discovery. +* +* \param agRoot Pointer to chip/driver Instance. +* \param onePortContext Pointer to the target port context +* \param agSASSubID Pointer to the SAS identification. +* +* \Return: +* Pointer to the device data +* +*****************************************************************************/ +osGLOBAL tdsaDeviceData_t * +tdssNewAddSASToSharedcontext( + agsaRoot_t *agRoot, + tdsaPortContext_t *onePortContext, + tdsaSASSubID_t *agSASSubID, + tdsaDeviceData_t *oneExpDeviceData, + bit8 phyID + ) +{ + tdsaDeviceData_t *oneDeviceData = agNULL; + tdList_t *DeviceListList; + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + bit32 new_device = agTRUE; + + TI_DBG3(("tdssNewAddSASToSharedcontext: start\n")); + /* + find a right portcontext + then, get devicedata from FreeLink in DeviceList + then, do pointer operations + then, add the devicedata to the portcontext + */ + + + TI_DBG3(("tdssNewAddSASToSharedcontext: oneportContext ID %d\n", onePortContext->id)); + /* find a device's existence */ + DeviceListList = tdsaAllShared->MainDeviceList.flink; + while (DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + TI_DBG1(("tdssNewAddSASToSharedcontext: oneDeviceData is NULL!!!\n")); + return agNULL; + } + if ((oneDeviceData->SASAddressID.sasAddressHi == agSASSubID->sasAddressHi) && + (oneDeviceData->SASAddressID.sasAddressLo == agSASSubID->sasAddressLo) && + (oneDeviceData->tdPortContext == onePortContext) + ) + { + TI_DBG3(("tdssNewAddSASToSharedcontext: pid %d did %d\n", onePortContext->id, oneDeviceData->id)); + new_device = agFALSE; + break; + } + DeviceListList = DeviceListList->flink; + } + + /* new device */ + if (new_device == agTRUE) + { + TI_DBG3(("tdssNewAddSASToSharedcontext: new device\n")); + tdsaSingleThreadedEnter(tiRoot, TD_DEVICE_LOCK); + if (!TDLIST_NOT_EMPTY(&(tdsaAllShared->FreeDeviceList))) + { + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + TI_DBG1(("tdssNewAddSASToSharedcontext: empty DeviceData FreeLink\n")); + return agNULL; + } + + TDLIST_DEQUEUE_FROM_HEAD(&DeviceListList, &(tdsaAllShared->FreeDeviceList)); + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, FreeLink, DeviceListList); + + TI_DBG3(("tdssNewAddSASToSharedcontext: oneDeviceData %p did %d\n", oneDeviceData, oneDeviceData->id)); + + onePortContext->Count++; + oneDeviceData->agRoot = agRoot; + /* saving sas address */ + oneDeviceData->SASAddressID.sasAddressLo = agSASSubID->sasAddressLo; + oneDeviceData->SASAddressID.sasAddressHi = agSASSubID->sasAddressHi; + oneDeviceData->initiator_ssp_stp_smp = agSASSubID->initiator_ssp_stp_smp; + oneDeviceData->target_ssp_stp_smp = agSASSubID->target_ssp_stp_smp; + oneDeviceData->tdPortContext = onePortContext; + /* handles both SAS target and STP-target, SATA-device */ + if (!DEVICE_IS_SATA_DEVICE(oneDeviceData) && !DEVICE_IS_STP_TARGET(oneDeviceData)) + { + oneDeviceData->DeviceType = TD_SAS_DEVICE; + } + else + { + oneDeviceData->DeviceType = TD_SATA_DEVICE; + } + + oneDeviceData->ExpDevice = oneExpDeviceData; + /* set phyID only when it has initial value of 0xFF */ + if (oneDeviceData->phyID == 0xFF) + { + oneDeviceData->phyID = phyID; + } +#ifdef FDS_DM + oneDeviceData->valid = agTRUE; +#else + + /* incremental discovery */ + /* add device to incremental-related link. Report using this link + when incremental discovery is done */ + if (onePortContext->discovery.type == TDSA_DISCOVERY_OPTION_INCREMENTAL_START) + { + TI_DBG3(("tdssNewAddSASToSharedcontext: incremental discovery\n")); + TI_DBG3(("tdssNewAddSASToSharedcontext: sasAddrHi 0x%08x \n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG3(("tdssNewAddSASToSharedcontext: sasAddrLo 0x%08x \n", oneDeviceData->SASAddressID.sasAddressLo)); + oneDeviceData->valid2 = agTRUE; + } + else + { + TI_DBG3(("tdssNewAddSASToSharedcontext: full discovery\n")); + TI_DBG3(("tdssNewAddSASToSharedcontext: sasAddrHi 0x%08x \n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG3(("tdssNewAddSASToSharedcontext: sasAddrLo 0x%08x \n", oneDeviceData->SASAddressID.sasAddressLo)); + oneDeviceData->valid = agTRUE; + } +#endif + /* add the devicedata to the portcontext */ + tdsaSingleThreadedEnter(tiRoot, TD_DEVICE_LOCK); + TDLIST_ENQUEUE_AT_TAIL(&(oneDeviceData->MainLink), &(tdsaAllShared->MainDeviceList)); + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + TI_DBG4(("tdssNewAddSASToSharedcontext: one case pid %d did %d \n", onePortContext->id, oneDeviceData->id)); + TI_DBG4(("tdssNewAddSASToSharedcontext: new case pid %d did %d phyID %d\n", onePortContext->id, oneDeviceData->id, oneDeviceData->phyID)); + } + else /* old device */ + { + TI_DBG3(("tdssNewAddSASToSharedcontext: old device\n")); + TI_DBG3(("tdssNewAddSASToSharedcontext: oneDeviceData %p did %d\n", oneDeviceData, oneDeviceData->id)); + + oneDeviceData->agRoot = agRoot; + /* saving sas address */ + oneDeviceData->SASAddressID.sasAddressLo = agSASSubID->sasAddressLo; + oneDeviceData->SASAddressID.sasAddressHi = agSASSubID->sasAddressHi; + oneDeviceData->initiator_ssp_stp_smp = agSASSubID->initiator_ssp_stp_smp; + oneDeviceData->target_ssp_stp_smp = agSASSubID->target_ssp_stp_smp; + oneDeviceData->tdPortContext = onePortContext; + /* handles both SAS target and STP-target, SATA-device */ + if (!DEVICE_IS_SATA_DEVICE(oneDeviceData) && !DEVICE_IS_STP_TARGET(oneDeviceData)) + { + oneDeviceData->DeviceType = TD_SAS_DEVICE; + } + else + { + oneDeviceData->DeviceType = TD_SATA_DEVICE; + } + + oneDeviceData->ExpDevice = oneExpDeviceData; + /* set phyID only when it has initial value of 0xFF */ + if (oneDeviceData->phyID == 0xFF) + { + oneDeviceData->phyID = phyID; + } + +#ifdef FDS_DM + oneDeviceData->valid = agTRUE; +#else + if (onePortContext->discovery.type == TDSA_DISCOVERY_OPTION_INCREMENTAL_START) + { + TI_DBG3(("tdssNewAddSASToSharedcontext: incremental discovery\n")); + TI_DBG3(("tdssNewAddSASToSharedcontext: sasAddrHi 0x%08x \n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG3(("tdssNewAddSASToSharedcontext: sasAddrLo 0x%08x \n", oneDeviceData->SASAddressID.sasAddressLo)); + oneDeviceData->valid2 = agTRUE; + } + else + { + TI_DBG3(("tdssNewAddSASToSharedcontext: full discovery\n")); + TI_DBG3(("tdssNewAddSASToSharedcontext: sasAddrHi 0x%08x \n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG3(("tdssNewAddSASToSharedcontext: sasAddrLo 0x%08x \n", oneDeviceData->SASAddressID.sasAddressLo)); + oneDeviceData->valid = agTRUE; + } +#endif + TI_DBG4(("tdssNewAddSASToSharedcontext: old case pid %d did %d phyID %d\n", onePortContext->id, oneDeviceData->id, oneDeviceData->phyID)); + + } + return oneDeviceData; +} + +/***************************************************************************** +*! \brief tdsaFindRegNValid +* +* Purpose: This function finds a device which is registered and valid in +* the device list. Used only in incremental discovery. +* +* \param agRoot Pointer to chip/driver Instance. +* \param onePortContext Pointer to the target port context +* \param tdsaDeviceData Pointer to a device list header +* \param agSASSubID Pointer to the SAS identification. +* +* \Return: +* Pointer to the device data +* +*****************************************************************************/ +osGLOBAL tdsaDeviceData_t * +tdsaFindRegNValid( + agsaRoot_t *agRoot, + tdsaPortContext_t *onePortContext, + tdsaSASSubID_t *agSASSubID + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdsaDeviceData_t *oneDeviceData = agNULL; + tdList_t *DeviceListList; + bit32 found = agFALSE; + + TI_DBG3(("tdsaFindRegNValid: start\n")); + + /* find a device's existence */ + DeviceListList = tdsaAllShared->MainDeviceList.flink; + if (onePortContext->discovery.type == TDSA_DISCOVERY_OPTION_FULL_START) + { + TI_DBG3(("tdsaFindRegNValid: Full discovery\n")); + while (DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + TI_DBG1(("tdsaFindRegNValid: oneDeviceData is NULL!!!\n")); + return agNULL; + } + if ((oneDeviceData->SASAddressID.sasAddressHi == agSASSubID->sasAddressHi) && + (oneDeviceData->SASAddressID.sasAddressLo == agSASSubID->sasAddressLo) && + (oneDeviceData->registered == agTRUE) && + (oneDeviceData->valid == agTRUE) && + (oneDeviceData->tdPortContext == onePortContext) + ) + { + TI_DBG3(("tdsaFindRegNValid: Found pid %d did %d\n", onePortContext->id, oneDeviceData->id)); + TI_DBG3(("tdsaFindRegNValid: sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG3(("tdsaFindRegNValid: sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + found = agTRUE; + break; + } + DeviceListList = DeviceListList->flink; + } + } + else + { + /* incremental discovery */ + TI_DBG3(("tdsaFindRegNValid: Incremental discovery\n")); + while (DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + TI_DBG1(("tdsaFindRegNValid: oneDeviceData is NULL!!!\n")); + return agNULL; + } + if ((oneDeviceData->SASAddressID.sasAddressHi == agSASSubID->sasAddressHi) && + (oneDeviceData->SASAddressID.sasAddressLo == agSASSubID->sasAddressLo) && + (oneDeviceData->registered == agTRUE) && + (oneDeviceData->valid2 == agTRUE) && + (oneDeviceData->tdPortContext == onePortContext) + ) + { + TI_DBG3(("tdsaFindRegNValid: Found pid %d did %d\n", onePortContext->id, oneDeviceData->id)); + TI_DBG3(("tdsaFindRegNValid: sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG3(("tdsaFindRegNValid: sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + found = agTRUE; + break; + } + DeviceListList = DeviceListList->flink; + } + } + + + + if (found == agFALSE) + { + TI_DBG3(("tdsaFindRegNValid: end returning NULL\n")); + return agNULL; + } + else + { + TI_DBG3(("tdsaFindRegNValid: end returning NOT NULL\n")); + return oneDeviceData; + } + +} + +//registered to LL or not +/***************************************************************************** +*! \brief tdssNewSASorNot +* +* Purpose: This function finds whether a device is registered or not +* +* \param agRoot Pointer to chip/driver Instance. +* \param onePortContext Pointer to the target port context +* \param agSASSubID Pointer to the SAS identification. +* +* \Return: +* agTRUE Device is not registered (New device). +* agFALSE Device is registered (Old device). +* +*****************************************************************************/ +bit32 +tdssNewSASorNot( + agsaRoot_t *agRoot, + tdsaPortContext_t *onePortContext, + tdsaSASSubID_t *agSASSubID + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdsaDeviceData_t *oneDeviceData = agNULL; + tdList_t *DeviceListList; + bit32 ret = agTRUE; + + TI_DBG3(("tdssNewSASorNot: start\n")); + + /* find a device's existence */ + DeviceListList = tdsaAllShared->MainDeviceList.flink; + while (DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + if ((oneDeviceData->SASAddressID.sasAddressHi == agSASSubID->sasAddressHi) && + (oneDeviceData->SASAddressID.sasAddressLo == agSASSubID->sasAddressLo) && + (oneDeviceData->registered == agTRUE) && + (oneDeviceData->tdPortContext == onePortContext) + ) + { + TI_DBG3(("tdssNewSASorNot: Found pid %d did %d\n", onePortContext->id, oneDeviceData->id)); + ret = agFALSE; + break; + } + DeviceListList = DeviceListList->flink; + } + + + + TI_DBG3(("tdssNewSASorNot: end\n")); + + return ret; +} + + + +/***************************************************************************** +*! \brief tdssSASDiscoveringExpanderAlloc +* +* Purpose: This function allocates an expander from the pre-allocated memory +* pool. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* \param oneDeviceData: Pointer to the device data. +* +* \return: +* Pointer to expander on success +* agNULL on failure +* +* \note: +* +*****************************************************************************/ +osGLOBAL tdsaExpander_t * +tdssSASDiscoveringExpanderAlloc( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaDeviceData_t *oneDeviceData + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdsaExpander_t *oneExpander = agNULL; + tdList_t *ExpanderList; + + /* + move the expander from freeExpanderList + and ground the expander by TDLIST_DEQUEUE_THIS + */ + + + TI_DBG3(("tdssSASDiscoveringExpanderAlloc: start\n")); + TI_DBG3(("tdssSASDiscoveringExpanderAlloc: did %d\n", oneDeviceData->id)); + TI_DBG3(("tdssSASDiscoveringExpanderAlloc: sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG3(("tdssSASDiscoveringExpanderAlloc: sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + + if (onePortContext->valid == agFALSE) + { + TI_DBG1(("tdssSASDiscoveringExpanderAlloc: aborting discovery\n")); + tdsaSASDiscoverAbort(tiRoot, onePortContext); + return agNULL; + } + + tdsaDumpAllFreeExp(tiRoot); + + if (TDLIST_EMPTY(&(tdsaAllShared->freeExpanderList))) + { + TI_DBG1(("tdssSASDiscoveringExpanderAlloc: no free expanders\n")); + return agNULL; + } + + tdsaSingleThreadedEnter(tiRoot, TD_DISC_LOCK); + TDLIST_DEQUEUE_FROM_HEAD(&ExpanderList, &(tdsaAllShared->freeExpanderList)); + tdsaSingleThreadedLeave(tiRoot, TD_DISC_LOCK); + // oneExpander = TDLIST_OBJECT_BASE(tdsaContext_t, freeExpanderList, ExpanderList); + oneExpander = TDLIST_OBJECT_BASE(tdsaExpander_t, linkNode, ExpanderList); + + if (oneExpander != agNULL) + { + TI_DBG3(("tdssSASDiscoveringExpanderAlloc: expander id %d\n", oneExpander->id)); + + tdsaSingleThreadedEnter(tiRoot, TD_DISC_LOCK); + TDLIST_DEQUEUE_THIS(&(oneExpander->linkNode)); + tdsaSingleThreadedLeave(tiRoot, TD_DISC_LOCK); + + oneExpander->tdDevice = oneDeviceData; + oneExpander->tdUpStreamExpander = agNULL; + oneExpander->tdCurrentDownStreamExpander = agNULL; + oneExpander->tdReturnginExpander = agNULL; + oneExpander->hasUpStreamDevice = agFALSE; + oneExpander->numOfUpStreamPhys = 0; + oneExpander->currentUpStreamPhyIndex = 0; + oneExpander->discoveringPhyId = 0; + oneExpander->underDiscovering = agFALSE; + osti_memset( &(oneExpander->currentIndex), 0, sizeof(oneExpander->currentIndex)); + + oneDeviceData->tdExpander = oneExpander; + } + + return oneExpander; +} + +/***************************************************************************** +*! \brief tdssSASDiscoveringExpanderAdd +* +* Purpose: This function adds an expander to the expander list. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* \param oneExpander: Pointer to the expander data. +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdssSASDiscoveringExpanderAdd( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaExpander_t *oneExpander + ) +{ +#ifdef TD_INTERNAL_DEBUG + tdList_t *ExpanderList; + tdsaExpander_t *tempExpander; +#endif + + /* move the expander to discoveringExpanderList */ + + TI_DBG3(("tdssSASDiscoveringExpanderAdd: start\n")); + TI_DBG3(("tdssSASDiscoveringExpanderAdd: expander id %d\n", oneExpander->id)); + TI_DBG3(("tdssSASDiscoveringExpanderAdd: exp addrHi 0x%08x\n", oneExpander->tdDevice->SASAddressID.sasAddressHi)); + TI_DBG3(("tdssSASDiscoveringExpanderAdd: exp addrLo 0x%08x\n", oneExpander->tdDevice->SASAddressID.sasAddressLo)); + + if (onePortContext->valid == agFALSE) + { + TI_DBG1(("tdssSASDiscoveringExpanderAdd: aborting discovery\n")); + tdsaSASDiscoverAbort(tiRoot, onePortContext); + return; + } + + + if (onePortContext->discovery.status == DISCOVERY_UP_STREAM) + { + TI_DBG3(("tdssSASDiscoveringExpanderAdd: UPSTREAM\n")); + } + else if (onePortContext->discovery.status == DISCOVERY_DOWN_STREAM) + { + TI_DBG3(("tdssSASDiscoveringExpanderAdd: DOWNSTREAM\n")); + } + else + { + TI_DBG3(("tdssSASDiscoveringExpanderAdd: status %d\n", onePortContext->discovery.status)); + } + + TI_DBG3(("tdssSASDiscoveringExpanderAdd: BEFORE\n")); + tdsaDumpAllExp(tiRoot, onePortContext, oneExpander); + + + if ( oneExpander->underDiscovering == agFALSE) + { + TI_DBG3(("tdssSASDiscoveringExpanderAdd: ADDED \n")); + + oneExpander->underDiscovering = agTRUE; + tdsaSingleThreadedEnter(tiRoot, TD_DISC_LOCK); + TDLIST_ENQUEUE_AT_TAIL(&(oneExpander->linkNode), &(onePortContext->discovery.discoveringExpanderList)); + tdsaSingleThreadedLeave(tiRoot, TD_DISC_LOCK); + } + + TI_DBG3(("tdssSASDiscoveringExpanderAdd: AFTER\n")); + tdsaDumpAllExp(tiRoot, onePortContext, oneExpander); + +#ifdef TD_INTERNAL_DEBUG + /* debugging */ + if (TDLIST_EMPTY(&(onePortContext->discovery.discoveringExpanderList))) + { + TI_DBG3(("tdssSASDiscoveringExpanderAdd: empty discoveringExpanderList\n")); + return; + } + ExpanderList = onePortContext->discovery.discoveringExpanderList.flink; + while (ExpanderList != &(onePortContext->discovery.discoveringExpanderList)) + { + tempExpander = TDLIST_OBJECT_BASE(tdsaExpander_t, linkNode, ExpanderList); + TI_DBG3(("tdssSASDiscoveringExpanderAdd: expander id %d\n", tempExpander->id)); + ExpanderList = ExpanderList->flink; + } +#endif + + return; +} + +/* temp */ +osGLOBAL bit32 +tdssSASFindDiscoveringExpander( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaExpander_t *oneExpander + ) +{ + tdList_t *ExpanderList; + tdsaExpander_t *tempExpander; + tdsaPortContext_t *tmpOnePortContext = onePortContext; + bit32 ret = agFALSE; + + TI_DBG3(("tdssSASFindDiscoveringExpander: exp addrHi 0x%08x\n", oneExpander->tdDevice->SASAddressID.sasAddressHi)); + TI_DBG3(("tdssSASFindDiscoveringExpander: exp addrLo 0x%08x\n", oneExpander->tdDevice->SASAddressID.sasAddressLo)); + + if (TDLIST_EMPTY(&(tmpOnePortContext->discovery.discoveringExpanderList))) + { + TI_DBG1(("tdssSASFindDiscoveringExpander: empty discoveringExpanderList\n")); + return ret; + } + ExpanderList = tmpOnePortContext->discovery.discoveringExpanderList.flink; + while (ExpanderList != &(tmpOnePortContext->discovery.discoveringExpanderList)) + { + tempExpander = TDLIST_OBJECT_BASE(tdsaExpander_t, linkNode, ExpanderList); + if (tempExpander == oneExpander) + { + TI_DBG3(("tdssSASFindDiscoveringExpander: match!!! expander id %d\n", tempExpander->id)); + TI_DBG3(("tdssSASFindDiscoveringExpander: exp addrHi 0x%08x\n", tempExpander->tdDevice->SASAddressID.sasAddressHi)); + TI_DBG3(("tdssSASFindDiscoveringExpander: exp addrLo 0x%08x\n", tempExpander->tdDevice->SASAddressID.sasAddressLo)); + ret = agTRUE; + break; + } + + ExpanderList = ExpanderList->flink; + } + + + return ret; + +} +/* to be tested */ +/* move the expander to freeExpanderList */ +/***************************************************************************** +*! \brief tdssSASDiscoveringExpanderRemove +* +* Purpose: This function removes an expander from the expander list. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* \param oneExpander: Pointer to the expander data. +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdssSASDiscoveringExpanderRemove( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaExpander_t *oneExpander + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; +#ifdef TD_INTERNAL_DEBUG + tdList_t *ExpanderList; + tdsaExpander_t *tempExpander; +#endif + + TI_DBG3(("tdssSASDiscoveringExpanderRemove: start\n")); + TI_DBG3(("tdssSASDiscoveringExpanderRemove: expander id %d\n", oneExpander->id)); + TI_DBG3(("tdssSASDiscoveringExpanderRemove: exp addrHi 0x%08x\n", oneExpander->tdDevice->SASAddressID.sasAddressHi)); + TI_DBG3(("tdssSASDiscoveringExpanderRemove: exp addrLo 0x%08x\n", oneExpander->tdDevice->SASAddressID.sasAddressLo)); + + + TI_DBG3(("tdssSASDiscoveringExpanderRemove: BEFORE\n")); + tdsaDumpAllExp(tiRoot, onePortContext, oneExpander); + tdsaDumpAllUpExp(tiRoot, onePortContext, oneExpander); + tdsaDumpAllFreeExp(tiRoot); + +#ifdef TD_INTERNAL_DEBUG + /* debugging */ + TI_DBG3(("tdssSASDiscoveringExpanderRemove: BEFORE\n")); + if (TDLIST_EMPTY(&(onePortContext->discovery.discoveringExpanderList))) + { + TI_DBG3(("tdssSASDiscoveringExpanderRemove: empty discoveringExpanderList\n")); + } + ExpanderList = onePortContext->discovery.discoveringExpanderList.flink; + while (ExpanderList != &(onePortContext->discovery.discoveringExpanderList)) + { + tempExpander = TDLIST_OBJECT_BASE(tdsaExpander_t, linkNode, ExpanderList); + TI_DBG3(("tdssSASDiscoveringExpanderRemove: expander id %d\n", tempExpander->id)); + ExpanderList = ExpanderList->flink; + } +#endif + + // if is temporary till smp problem is fixed + if (tdssSASFindDiscoveringExpander(tiRoot, onePortContext, oneExpander) == agTRUE) + { + oneExpander->underDiscovering = agFALSE; + oneExpander->discoveringPhyId = 0; + tdsaSingleThreadedEnter(tiRoot, TD_DISC_LOCK); + TDLIST_DEQUEUE_THIS(&(oneExpander->linkNode)); + + if (onePortContext->discovery.status == DISCOVERY_UP_STREAM) + { + TI_DBG3(("tdssSASDiscoveringExpanderRemove: DISCOVERY_UP_STREAM\n")); + TDLIST_ENQUEUE_AT_TAIL(&(oneExpander->upNode), &(onePortContext->discovery.UpdiscoveringExpanderList)); + onePortContext->discovery.NumOfUpExp++; + } + else + { + TI_DBG3(("tdssSASDiscoveringExpanderRemove: Status %d\n", onePortContext->discovery.status)); + TDLIST_ENQUEUE_AT_TAIL(&(oneExpander->linkNode), &(tdsaAllShared->freeExpanderList)); + } + + tdsaSingleThreadedLeave(tiRoot, TD_DISC_LOCK); + } //end temp if + else + { + TI_DBG1(("tdssSASDiscoveringExpanderRemove: !!! problem !!!\n")); + } + + TI_DBG3(("tdssSASDiscoveringExpanderRemove: AFTER\n")); + tdsaDumpAllExp(tiRoot, onePortContext, oneExpander); + tdsaDumpAllUpExp(tiRoot, onePortContext, oneExpander); + + tdsaDumpAllFreeExp(tiRoot); + +#ifdef TD_INTERNAL_DEBUG + /* debugging */ + TI_DBG3(("tdssSASDiscoveringExpanderRemove: AFTER\n")); + if (TDLIST_EMPTY(&(onePortContext->discovery.discoveringExpanderList))) + { + TI_DBG3(("tdssSASDiscoveringExpanderRemove: empty discoveringExpanderList\n")); + } + ExpanderList = onePortContext->discovery.discoveringExpanderList.flink; + while (ExpanderList != &(onePortContext->discovery.discoveringExpanderList)) + { + tempExpander = TDLIST_OBJECT_BASE(tdsaExpander_t, linkNode, ExpanderList); + TI_DBG3(("tdssSASDiscoveringExpanderRemove: expander id %d\n", tempExpander->id)); + ExpanderList = ExpanderList->flink; + } +#endif + + return; +} + +#ifdef SATA_ENABLE + +/***************************************************************************** +*! \brief tdssNewAddSATAToSharedcontext +* +* Purpose: This function adds a discovered SATA device to a device list of +* a shared context. Used only in discovery. +* +* \param tiRoot Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param agRoot Pointer to chip/driver Instance. +* \param onePortContext Pointer to the target port context +* \param tdsaDeviceData Pointer to a device list header +* \param agSATADeviceInfo Pointer to the SATA device information. +* \param Signature Pointer to SATA signature +* \param pm Port multiplier +* \param pmField Port multiplier field +* \param connectionRate Connection rate +* +* \Return: +* Pointer to the device data +* +*****************************************************************************/ +osGLOBAL tdsaDeviceData_t * +tdssNewAddSATAToSharedcontext(tiRoot_t *tiRoot, + agsaRoot_t *agRoot, + tdsaPortContext_t *onePortContext, + agsaSATADeviceInfo_t *agSATADeviceInfo, + bit8 *Signature, + bit8 pm, + bit8 pmField, + bit32 connectionRate, + tdsaDeviceData_t *oneExpDeviceData, + bit8 phyID + ) +{ + tdsaDeviceData_t *oneDeviceData = agNULL; + tdList_t *DeviceListList; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + int new_device = agTRUE; + + TI_DBG5(("tdssNewAddSATAToSharedcontext: start\n")); + + + + TI_DBG5(("tdssNewAddSATAToSharedcontext: oneportContext ID %d\n", onePortContext->id)); + + +#ifdef RPM_SOC + /* Find a device's existence */ + DeviceListList = tdsaAllShared->MainDeviceList.flink; + while (DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + + if ((osti_memcmp (((char *)&oneDeviceData->satDevData.satIdentifyData), + ((char *)&agSATADeviceInfo->sataIdentifyData), + sizeof(agsaSATAIdentifyData_t)) == 0)) + { + TI_DBG5(("tdssNewAddSATAToSharedcontext: pid %d did %d\n", + onePortContext->id, oneDeviceData->id)); + new_device = agFALSE; + break; + } + DeviceListList = DeviceListList->flink; + } +#else + + +#endif + + /* New device */ + if (new_device == agTRUE) + { + TI_DBG5(("tdssNewAddSATAToSharedcontext: new device\n")); + + tdsaSingleThreadedEnter(tiRoot, TD_DEVICE_LOCK); + if (!TDLIST_NOT_EMPTY(&(tdsaAllShared->FreeDeviceList))) + { + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + TI_DBG1(("tdssNewAddSATAToSharedcontext: ERROR empty DeviceData FreeLink\n")); + return oneDeviceData; + } + + TDLIST_DEQUEUE_FROM_HEAD(&DeviceListList, &(tdsaAllShared->FreeDeviceList)); + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, FreeLink, DeviceListList); + + onePortContext->Count++; + oneDeviceData->DeviceType = TD_SATA_DEVICE; + oneDeviceData->agRoot = agRoot; + TI_DBG5(("tdssNewAddSATAToSharedcontext: oneDeviceData %p\n", oneDeviceData)); + TI_DBG5(("tdssNewAddSATAToSharedcontext: pSatDevData=%p\n", &oneDeviceData->satDevData)); + + + /* saving PortMultiplier(PM) field */ + oneDeviceData->satDevData.satPMField = pmField; + + /* saving signature */ + osti_memcpy(&(oneDeviceData->satDevData.satSignature), Signature, 8); + + /* + saving device type + ATA device type; here should be either ATA_ATA_DEVICE or ATA_ATAPI_DEVICE + */ + oneDeviceData->satDevData.satDeviceType = tdssSATADeviceTypeDecode(agSATADeviceInfo->signature); + TI_DBG3(("tdssNewAddSATAToSharedcontext: device type %d\n", oneDeviceData->satDevData.satDeviceType)); + +#ifdef RPM_SOC_REMOVED + /* print device signature - Word8 */ + TI_DBG3(("tdssNewAddSATAToSharedcontext: Word8 %x signature: %x %x %x %x %x %x %x %x\n", + agSATADeviceInfo->sataIdentifyData.word1_9[7], + agSATADeviceInfo->signature[0], agSATADeviceInfo->signature[1], + agSATADeviceInfo->signature[2], agSATADeviceInfo->signature[3], + agSATADeviceInfo->signature[4], agSATADeviceInfo->signature[5], + agSATADeviceInfo->signature[6], agSATADeviceInfo->signature[7] )); +#endif + + + + oneDeviceData->tdPortContext = onePortContext; + oneDeviceData->valid = agTRUE; + + oneDeviceData->ExpDevice = oneExpDeviceData; + oneDeviceData->phyID = phyID; + + /* Add the devicedata to the portcontext */ + tdsaSingleThreadedEnter(tiRoot, TD_DEVICE_LOCK); + TDLIST_ENQUEUE_AT_TAIL(&(oneDeviceData->MainLink), &(tdsaAllShared->MainDeviceList)); + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + TI_DBG5(("tdssNewAddSATAToSharedcontext: one case pid %d did %d \n", + onePortContext->id, oneDeviceData->id)); + } + else /* old device */ + { + TI_DBG5(("tdssNewAddSATAToSharedcontext: old device\n")); + + onePortContext->Count++; + + oneDeviceData->DeviceType = TD_SATA_DEVICE; + oneDeviceData->agRoot = agRoot; + + oneDeviceData->tdPortContext = onePortContext; + oneDeviceData->valid = agTRUE; + + oneDeviceData->ExpDevice = oneExpDeviceData; + oneDeviceData->phyID = phyID; + + } + + return oneDeviceData; + +} +#endif /* SATA_ENABLE */ +#endif /* TD_DISCOVER */ +#endif /* INITIATOR_DRIVER */ + +#ifdef TARGET_DRIVER +/***************************************************************************** +*! \brief tdssReportRemovals +* +* Purpose: This function goes through device list and removes all devices +* belong to the portcontext. This function also deregiters those +* devices. This function is called in case of incremental discovery +* failure. +* +* \param agRoot : Pointer to chip/driver Instance. +* \param onePortContext: Pointer to the portal context instance. +* \param oneDeviceData: Pointer to the device data. +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +ttdssReportRemovals( + agsaRoot_t *agRoot, + tdsaPortContext_t *onePortContext, + bit32 flag + ) +{ + tdsaDeviceData_t *oneDeviceData = agNULL; + tdList_t *DeviceListList; + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + bit32 removed = agFALSE; + agsaEventSource_t *eventSource; + bit32 PhyID; + bit32 HwAckSatus; + tdsaDeviceData_t *tmpDeviceData = agNULL; + + TI_DBG1(("ttdssReportRemovals: start\n")); + /* in case nothing was registered */ + PhyID = onePortContext->eventPhyID; + if (tdsaAllShared->eventSource[PhyID].EventValid == agTRUE && + onePortContext->RegisteredDevNums == 0 && + PhyID != 0xFF + ) + { + TI_DBG1(("ttdssReportRemovals: calling saHwEventAck\n")); + eventSource = &(tdsaAllShared->eventSource[PhyID].Source); + HwAckSatus = saHwEventAck( + agRoot, + agNULL, /* agContext */ + 0, + eventSource, /* agsaEventSource_t */ + 0, + 0 + ); + if ( HwAckSatus != AGSA_RC_SUCCESS) + { + TI_DBG1(("ttdssReportRemovals: failing in saHwEventAck; status %d\n", HwAckSatus)); + } + + /* toggle */ + tdsaAllShared->eventSource[PhyID].EventValid = agFALSE; + if (onePortContext->valid == agFALSE) + { + tdsaPortContextReInit(tiRoot, onePortContext); + /* + put all devices belonging to the onePortContext + back to the free link + */ + tdsaSingleThreadedEnter(tiRoot, TD_PORT_LOCK); + TDLIST_DEQUEUE_THIS(&(onePortContext->MainLink)); + TDLIST_ENQUEUE_AT_TAIL(&(onePortContext->FreeLink), &(tdsaAllShared->FreePortContextList)); + tdsaSingleThreadedLeave(tiRoot, TD_PORT_LOCK); + } + } + else + { + if (TDLIST_EMPTY(&(tdsaAllShared->MainDeviceList))) + { + TI_DBG1(("ttdssReportRemovals: empty device list\n")); + return; + } + + DeviceListList = tdsaAllShared->MainDeviceList.flink; + while (DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + if( oneDeviceData == agNULL ) + { + break; + } + TI_DBG1(("ttdssReportRemovals: loop did %d\n", oneDeviceData->id)); + TI_DBG1(("ttdssReportRemovals: sasAddrHi 0x%08x sasAddrLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi, oneDeviceData->SASAddressID.sasAddressLo)); + TI_DBG1(("ttdssReportRemovals: valid %d valid2 %d\n", oneDeviceData->valid, oneDeviceData->valid2)); + TI_DBG1(("ttdssReportRemovals: directlyAttached %d registered %d\n", oneDeviceData->directlyAttached, oneDeviceData->registered)); + if ( oneDeviceData->tdPortContext == onePortContext) + { + TI_DBG1(("ttdssReportRemovals: right portcontext pid %d\n", onePortContext->id)); + if (oneDeviceData->valid == agTRUE && oneDeviceData->registered == agTRUE) + { + TI_DBG1(("ttdssReportRemovals: removing\n")); + + /* notify only reported devices to OS layer*/ + removed = agTRUE; + + /* all targets except expanders */ + TI_DBG1(("ttdssReportRemovals: calling tdsaAbortAll\n")); + TI_DBG1(("ttdssReportRemovals: did %d\n", oneDeviceData->id)); + TI_DBG1(("ttdssReportRemovals: sasAddrHi 0x%08x sasAddrLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi, oneDeviceData->SASAddressID.sasAddressLo)); + tmpDeviceData = oneDeviceData; + ttdsaAbortAll(tiRoot, agRoot, oneDeviceData); + + + /* reset valid bit */ + oneDeviceData->valid = agFALSE; + oneDeviceData->valid2 = agFALSE; + oneDeviceData->registered = agFALSE; + } + /* called by port invalid case */ + if (flag == agTRUE) + { + oneDeviceData->tdPortContext = agNULL; + } +#ifdef REMOVED /* removed */ + /* directly attached SATA -> always remove it */ + if (oneDeviceData->DeviceType == TD_SATA_DEVICE && + oneDeviceData->directlyAttached == agTRUE) + { + TI_DBG1(("ttdssReportRemovals: device did %d\n", oneDeviceData->id)); + tdsaSingleThreadedEnter(tiRoot, TD_DEVICE_LOCK); + TDLIST_DEQUEUE_THIS(&(oneDeviceData->MainLink)); + TDLIST_ENQUEUE_AT_TAIL(&(oneDeviceData->FreeLink), &(tdsaAllShared->FreeDeviceLis)); + DeviceListList = tdsaAllShared->MainDeviceList.flink; + if (TDLIST_EMPTY(&(tdsaAllShared->MainDeviceList))) + { + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + break; + } + else + { + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + } + } + else + { + DeviceListList = DeviceListList->flink; + } +#endif /* REMOVED */ + DeviceListList = DeviceListList->flink; + } + else + { + if (oneDeviceData->tdPortContext != agNULL) + { + TI_DBG1(("ttdssReportRemovals: different portcontext; oneDeviceData->tdPortContext pid %d oneportcontext pid %d\n", oneDeviceData->tdPortContext->id, onePortContext->id)); + } + else + { + TI_DBG1(("ttdssReportRemovals: different portcontext; oneDeviceData->tdPortContext pid NULL oneportcontext pid %d\n", onePortContext->id)); + } + DeviceListList = DeviceListList->flink; + } + } + + if (removed == agTRUE) + { + TI_DBG1(("ttdssReportRemovals: removed at the end\n")); + ostiTargetEvent( + tiRoot, + onePortContext->tiPortalContext, + &(tmpDeviceData->tiDeviceHandle), + tiTgtEventTypeDeviceChange, + tiDeviceRemoval, + agNULL + ); + } + } /* big else */ + return; +} +#endif /* TARGET_DRIVER */ + + +/***************************************************************************** +*! \brief tdsaRotateQnumber +* +* Purpose: This function generates inbound queue number. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* +* \return: +* Queue number +* +* \note: +* +*****************************************************************************/ +FORCEINLINE bit32 +tdsaRotateQnumber(tiRoot_t *tiRoot, + tdsaDeviceData_t *oneDeviceData ) +{ + bit32 ret = 0; + + TI_DBG6(("tdsaRotateQnumber: start\n")); + if (oneDeviceData == agNULL) + { + return 0; + } + ret = (oneDeviceData->OutQID << 16) | oneDeviceData->InQID; + return ret; +} + +osGLOBAL bit32 +tdsaRotateQnumber1(tiRoot_t *tiRoot, + tdsaDeviceData_t *oneDeviceData ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; +// static int Last_Q; +// bit32 denom = tdsaAllShared->QueueConfig.numOutboundQueues; + bit32 ret = 0; + if (oneDeviceData == agNULL) + { +// Last_Q= 0; + return 0; + } + +/* alway use highest Q number */ + ret = ((tdsaAllShared->QueueConfig.numOutboundQueues-1) << 16) | (tdsaAllShared->QueueConfig.numInboundQueues-1); + + return(ret); +} + +#ifdef REMOVED +osGLOBAL bit32 +tdsaRotateQnumber(tiRoot_t *tiRoot, + tdsaDeviceData_t *oneDeviceData ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + bit32 denom = tdsaAllShared->QueueConfig.numInboundQueues; + bit32 ret = 0; + + /* inbound queue number */ + tdsaAllShared->IBQnumber++; + if (tdsaAllShared->IBQnumber % denom == 0) /* % Qnumber*/ + { + tdsaAllShared->IBQnumber = 0; + } + TI_DBG6(("tdsaRotateQnumber: IBQnumber %d\n", tdsaAllShared->IBQnumber)); + + + /* outbound queue number */ + tdsaAllShared->OBQnumber++; + denom = tdsaAllShared->QueueConfig.numOutboundQueues; + if (tdsaAllShared->OBQnumber % denom == 0) /* % Qnumber*/ + { + tdsaAllShared->OBQnumber = 0; + } + TI_DBG6(("tdsaRotateQnumber: OBQnumber %d\n", tdsaAllShared->OBQnumber)); + + ret = (tdsaAllShared->OBQnumber << 16) | tdsaAllShared->IBQnumber; + return ret; +} +#endif + + +void t_MacroCheck( agsaRoot_t *agRoot) +{ + TI_DBG1(("t_MacroCheck:tIsSPC %d\n",tIsSPC(agRoot))); + TI_DBG1(("t_MacroCheck:tIsSPCHIL %d\n",tIsSPCHIL(agRoot))); + TI_DBG1(("t_MacroCheck:tIsSPCv %d\n",tIsSPCv(agRoot))); + TI_DBG1(("t_MacroCheck:tIsSPCve %d\n",tIsSPCve(agRoot))); + TI_DBG1(("t_MacroCheck:tIsSPCvplus %d\n",tIsSPCvplus(agRoot))); + TI_DBG1(("t_MacroCheck:tIsSPCveplus %d\n",tIsSPCveplus(agRoot))); + TI_DBG1(("t_MacroCheck:tIsSPCADAPvplus %d\n",tIsSPCADAPvplus(agRoot))); + TI_DBG1(("t_MacroCheck:tIsSPCADAPveplus %d\n",tIsSPCADAPveplus(agRoot))); + TI_DBG1(("t_MacroCheck:tIsSPC12Gv %d\n",tIsSPC12Gv(agRoot))); + TI_DBG1(("t_MacroCheck:tIsSPC12Gve %d\n",tIsSPC12Gve(agRoot))); + TI_DBG1(("t_MacroCheck:tIsSPC12Gvplus %d\n",tIsSPC12Gvplus(agRoot))); + TI_DBG1(("t_MacroCheck:tIsSPC12Gveplus %d\n",tIsSPC12Gveplus(agRoot))); + TI_DBG1(("t_MacroCheck:tiIS_SPC %d\n",tiIS_SPC(agRoot) )); + TI_DBG1(("t_MacroCheck:tiIS_HIL %d\n",tiIS_HIL(agRoot) )); + TI_DBG1(("t_MacroCheck:tiIS_SPC6V %d\n",tiIS_SPC6V(agRoot) )); + TI_DBG1(("t_MacroCheck:tiIS_SPC_ENC %d\n",tiIS_SPC_ENC(agRoot) )); + TI_DBG1(("t_MacroCheck:tIsSPCV12G %d\n",tIsSPCV12G(agRoot) )); +} diff --git a/sys/dev/pms/RefTisa/tisa/sassata/common/tdproto.h b/sys/dev/pms/RefTisa/tisa/sassata/common/tdproto.h new file mode 100644 index 000000000000..50c770651d28 --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/common/tdproto.h @@ -0,0 +1,2269 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/*******************************************************************************/ +/** \file + * + * function definitions used in SAS/SATA TD layer + * + */ + +#ifndef __TDPROTO_H__ +#define __TDPROTO_H__ + +#ifdef FDS_DM +#include +#endif + +/***************************************************************************** +* +* SA SHARED PROTOTYPES +* +*****************************************************************************/ + +osGLOBAL void +tdsaQueueConfigInit( + tiRoot_t *tiRoot + ); + +osGLOBAL void +tdsaEsglInit( + tiRoot_t *tiRoot + ); + +osGLOBAL void +tdsaResetComMemFlags( + tiRoot_t *tiRoot + ); + + +osGLOBAL void +tdsaInitTimerRequest( + tiRoot_t *tiRoot, + tdsaTimerRequest_t *timerRequest + ); + +osGLOBAL void +tdsaSetTimerRequest( + tiRoot_t *tiRoot, + tdsaTimerRequest_t *timerRequest, + bit32 timeout, + tdsaTimerCBFunc_t CBFunc, + void *timerData1, + void *timerData2, + void *timerData3 + ); + +osGLOBAL void +tdsaAddTimer ( + tiRoot_t *tiRoot, + tdList_t *timerListHdr, + tdsaTimerRequest_t *timerRequest + ); + +osGLOBAL void +tdsaKillTimer( + tiRoot_t *tiRoot, + tdsaTimerRequest_t *timerRequest + ); + + + + + +osGLOBAL void +tdsaLoLevelGetResource ( + tiRoot_t * tiRoot, + tiLoLevelResource_t * loResource + ); + +osGLOBAL void +tdsaSharedMemCalculate ( + tiRoot_t * tiRoot, + tiLoLevelResource_t * loResource, + tiTdSharedMem_t * tdSharedMem + ); + +osGLOBAL void +tdsaGetEsglPagesInfo( + tiRoot_t *tiRoot, + bit32 *PageSize, + bit32 *NumPages + ); + +osGLOBAL void +tdsaGetPortParams( + tiRoot_t *tiRoot + ); + + + +osGLOBAL void +tdsaGetSwConfigParams( + tiRoot_t *tiRoot + ); + +osGLOBAL void +tdsaGetHwConfigParams( + tiRoot_t *tiRoot + ); + +osGLOBAL void +tdsaGetCardPhyParams( + tiRoot_t *tiRoot + ); + + +osGLOBAL void +tdsaGetGlobalPhyParams( + tiRoot_t *tiRoot + ); + +osGLOBAL bit32 +tdsaGetCardIDString( + tiRoot_t *tiRoot + ); + +osGLOBAL void +tdsaParseLinkRateMode( + tiRoot_t *tiRoot, + bit32 index, + bit32 LinkRateRead, + bit32 ModeRead, + bit32 OpticalModeRead, + bit32 LinkRate, + bit32 Mode, + bit32 OpticalMode + ); + +osGLOBAL void +tdsaInitTimers( + tiRoot_t *tiRoot + ); + +osGLOBAL void +tdsaProcessTimers( + tiRoot_t *tiRoot + ); + +osGLOBAL void +tdsaInitTimerHandler( + tiRoot_t *tiRoot, + void *timerData + ); + +osGLOBAL void +tdsaGetEsglPages( + tiRoot_t *tiRoot, + tdList_t *EsglListHdr, + tiSgl_t *ptiSgl, + tiSgl_t *virtSgl + ); + +osGLOBAL void +tdsaFreeEsglPages( + tiRoot_t *tiRoot, + tdList_t *EsglListHdr + ); + +osGLOBAL void +tdssGetMaxTargetsParams( + tiRoot_t *tiRoot, + bit32 *pMaxTargets + ); + +osGLOBAL void +tdssGetSATAOnlyModeParams( + tiRoot_t *tiRoot, + bit32 *pMaxTargets + ); + +osGLOBAL bit32 +tdipFWControlIoctl( + tiRoot_t *tiRoot, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2, + void *agParam3 + ); + +osGLOBAL bit32 +tdsaVPDGetIoctl( + tiRoot_t *tiRoot, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2, + void *agParam3 + ); + +osGLOBAL bit32 +tdsaVPDSetIoctl( + tiRoot_t *tiRoot, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2, + void *agParam3 + ); + +osGLOBAL void +ostiCOMMgntVPDSetIOCTLRsp( + tiRoot_t *tiRoot, + bit32 status + ); + +osGLOBAL void +tdsaFreeCardID(tiRoot_t *tiRoot, + bit32 CardID + ); + + +osGLOBAL bit32 +tdsaAbortAll( + tiRoot_t *tiRoot, + agsaRoot_t *agRoot, + tdsaDeviceData_t *oneDeviceData + ); + +osGLOBAL bit32 +tdsaFindLocalMCN( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext + ); + +osGLOBAL bit32 +tdsaRegDumpGetIoctl( + tiRoot_t *tiRoot, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2, + void *agParam3 + ); + +osGLOBAL bit32 +tdsaNVMDSetIoctl( + tiRoot_t *tiRoot, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2, + void *agParam3 + ); + +osGLOBAL bit32 +tdsaNVMDGetIoctl( + tiRoot_t *tiRoot, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2, + void *agParam3 + ); + +osGLOBAL void ostiGetGpioIOCTLRsp( + tiRoot_t *tiRoot, + bit32 status, + bit32 gpioReadValue, + agsaGpioPinSetupInfo_t *gpioPinSetupInfo, + agsaGpioEventSetupInfo_t *gpioEventSetupInfo + ); + +osGLOBAL bit32 +tdsaGpioSetup( + tiRoot_t *tiRoot, + agsaContext_t *agContext, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2 + ); + + +osGLOBAL bit32 +tdsaSGpioIoctlSetup( + tiRoot_t *tiRoot, + agsaContext_t *agContext, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2 + ); + +osGLOBAL void ostiSgpioIoctlRsp( + tiRoot_t *tiRoot, + agsaSGpioReqResponse_t *pSgpioResponse + ); +osGLOBAL bit32 +tdsaDeviceInfoGetIoctl( + tiRoot_t *tiRoot, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2, + void *agParam3 + ); + +osGLOBAL bit32 +tdsaIoErrorStatisticGetIoctl( + tiRoot_t *tiRoot, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2, + void *agParam3 + ); + +osGLOBAL bit32 +tdsaIoEventStatisticGetIoctl( + tiRoot_t *tiRoot, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2, + void *agParam3 + ); + +osGLOBAL bit32 +tdsaForensicDataGetIoctl( + tiRoot_t *tiRoot, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2, + void *agParam3 + ); + +osGLOBAL bit32 +tdsaSendSMPIoctl( + tiRoot_t *tiRoot, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2, + void *agParam3 + ); + +osGLOBAL bit32 +tdsaSendBISTIoctl( + tiRoot_t *tiRoot, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2, + void *agParam3 + ); + +osGLOBAL bit32 +tdsaSendTMFIoctl( + tiRoot_t *tiRoot, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2, + unsigned long resetType + ); + + +osGLOBAL bit32 +tdsaRegisterIoctl( + tiRoot_t *tiRoot, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2, + void *agParam3 + ); + +osGLOBAL bit32 +tdsaGetPhyGeneralStatusIoctl( + tiRoot_t *tiRoot, + agsaPhyGeneralState_t *PhyData + ); + +osGLOBAL void ostiGetPhyGeneralStatusRsp( + tiRoot_t *tiRoot, + agsaSASPhyGeneralStatusPage_t *GenStatus, + bit32 phyID + ); + + +osGLOBAL bit32 +tdsaPhyProfileIoctl( + tiRoot_t *tiRoot, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2, + void *agParam3 + ); + +osGLOBAL void +tdsaDeregisterDevicesInPort( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext + ); + +#ifdef VPD_TESTING +osGLOBAL bit32 +tdsaVPDGet( + tiRoot_t *tiRoot + ); + +osGLOBAL bit32 +tdsaVPDSet( + tiRoot_t *tiRoot + ); + +#endif + +/***************************************************************************** +* +* SAS SHARED PROTOTYPES +* +*****************************************************************************/ +osGLOBAL void +tdsaJumpTableInit( + tiRoot_t *tiRoot + ); + +osGLOBAL void +tdsaPortContextInit( + tiRoot_t *tiRoot + ); + +osGLOBAL void +tdsaPortContextReInit( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext + ); + +osGLOBAL void +tdsaDeviceDataInit( + tiRoot_t *tiRoot + ); + +osGLOBAL void +tdsaDeviceDataReInit( + tiRoot_t *tiRoot, + tdsaDeviceData_t *oneDeviceData + ); + +#ifdef TD_INT_COALESCE +osGLOBAL void +tdsaIntCoalCxtInit( + tiRoot_t *tiRoot + ); +#endif + +osGLOBAL FORCEINLINE bit32 +tdsaRotateQnumber(tiRoot_t *tiRoot, + tdsaDeviceData_t *oneDeviceData); + +osGLOBAL bit32 +tdsaRotateQnumber1(tiRoot_t *tiRoot, + tdsaDeviceData_t *oneDeviceData ); +osGLOBAL void +tdssRemoveSASSATAFromSharedcontext( + agsaRoot_t *agRoot, + tdsaPortContext_t *PortContext_Instance + ); +osGLOBAL void +tdssRemoveSASSATAFromSharedcontextByReset( + agsaRoot_t *agRoot + ); +osGLOBAL bit32 +tdssSASFindDiscoveringExpander( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaExpander_t *oneExpander + ); + +osGLOBAL void +tdssAddSASToSharedcontext( + tdsaPortContext_t *tdsaPortContext_Instance, + agsaRoot_t *agRoot, + agsaDevHandle_t *agDevHandle, + tdsaSASSubID_t *agSASSubID, + bit32 registered, + bit8 phyID, + bit32 flag + ); + +osGLOBAL void +tdssRemoveSASFromSharedcontext( + tdsaPortContext_t *tdsaPortContext_Ins, + tdsaDeviceData_t *tdsaDeviceData_ins, + agsaRoot_t *agRoot + ); + +osGLOBAL void +tdssRemoveAllDevicelistFromPortcontext( + tdsaPortContext_t *PortContext_Ins, + agsaRoot_t *agRoot + ); + +osGLOBAL void +tdssAddSATAToSharedcontext( tdsaPortContext_t *tdsaPortContext_Instance, + agsaRoot_t *agRoot, + agsaDevHandle_t *agDevHandle, + agsaSATADeviceInfo_t *agSATADeviceInfo, + bit32 registered, + bit8 phyID + ); + +osGLOBAL void +tdssSubAddSATAToSharedcontext( tiRoot_t *tiRoot, + tdsaDeviceData_t *oneDeviceData + ); + +osGLOBAL void +tdssRetrySATAID( tiRoot_t *tiRoot, + tdsaDeviceData_t *oneDeviceData + ); + +osGLOBAL void +tdssInitSASPortStartInfo( + tiRoot_t *tiRoot + ); +#ifndef ossaDeviceRegistrationCB +osGLOBAL void +ossaDeviceRegistrationCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + bit32 status, + agsaDevHandle_t *agDevHandle, + bit32 deviceID); +#endif + +#ifndef ossaDeregisterDeviceHandleCB +osGLOBAL void +ossaDeregisterDeviceHandleCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaDevHandle_t *agDevHandle, + bit32 status + ); +#endif + +#ifdef INITIATOR_DRIVER +/***************************************************************************** +* +* SAS Initiator only PROTOTYPES +* +*****************************************************************************/ +osGLOBAL bit32 +itdssInit( + tiRoot_t *tiRoot, + tiInitiatorResource_t *initiatorResource, + tiTdSharedMem_t *tdSharedMem + ); + +osGLOBAL void +itdssInitTimers ( + tiRoot_t *tiRoot + ); + +osGLOBAL FORCEINLINE void +itdssIOCompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); + +osGLOBAL void +itdssTaskCompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); + +osGLOBAL void +itdssQueryTaskCompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); + +osGLOBAL void +itdssSMPCompleted ( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle + ); + +osGLOBAL void +ossaSMPCAMCompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle + ); + +osGLOBAL void +itdssIOSuccessHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); +osGLOBAL void +itdssIOAbortedHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); + +#ifdef REMOVED +osGLOBAL void +itdssIOOverFlowHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam + ); +#endif + +osGLOBAL void +itdssIOUnderFlowHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); + +osGLOBAL void +itdssIOFailedHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); + +osGLOBAL void +itdssIOAbortResetHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); +osGLOBAL void +itdssIONotValidHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); + +osGLOBAL void +itdssIONoDeviceHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); + +#ifdef REMOVED /* removed from spec */ +osGLOBAL void +itdssIllegalParameterHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam + ); +#endif + +osGLOBAL void +itdssLinkFailureHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); +osGLOBAL void +itdssProgErrorHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); +osGLOBAL void +itdssXferErrorBreakHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); +osGLOBAL void +itdssXferErrorPhyNotReadyHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); +osGLOBAL void +itdssOpenCnxErrorProtocolNotSupprotedHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); +osGLOBAL void +itdssOpenCnxErrorZoneViolationHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); +osGLOBAL void +itdssOpenCnxErrorBreakHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); +osGLOBAL void +itdssOpenCnxErrorITNexusLossHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); +osGLOBAL void +itdssOpenCnxErrorBadDestinationHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); +osGLOBAL void +itdssOpenCnxErrorConnectionRateNotSupportedHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); + +osGLOBAL void +itdssOpenCnxErrorSTPResourceBusyHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); +osGLOBAL void +itdssOpenCnxErrorWrongDestinationHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); +osGLOBAL void +itdssOpenCnxErrorUnknownErrorHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); +osGLOBAL void +itdssXferErrorNAKReceivedHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); +osGLOBAL void +itdssXferErrorACKNAKTimeoutHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); +osGLOBAL void +itdssXferErrorPeerAbortedHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); +osGLOBAL void +itdssXferErrorRxFrameHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); +osGLOBAL void +itdssXferErrorDMAHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); +osGLOBAL void +itdssXferErrorCreditTimeoutHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); + +osGLOBAL void +itdssXferErrorCMDIssueACKNAKTimeoutHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); +osGLOBAL void +itdssXferErrorCMDIssueBreakBeforeACKNAKHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); +osGLOBAL void +itdssXferErrorCMDIssuePhyDownBeforeACKNAKHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); +osGLOBAL void +itdssXferErrorDisruptedPhyDownHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); +osGLOBAL void +itdssXferErrorOffsetMismatchHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); +osGLOBAL void +itdssXferErrorXferZeroDataLenHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); + +osGLOBAL void +itdssXferOpenRetryTimeoutHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); + +osGLOBAL void +itdssPortInResetHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); + +osGLOBAL void +itdssDsNonOperationalHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); +osGLOBAL void +itdssDsInRecoveryHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); +osGLOBAL void +itdssTmTagNotFoundHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); +osGLOBAL void +itdssSSPExtIUZeroLenHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); +osGLOBAL void +itdssXferErrorUnexpectedPhaseHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); + +#ifdef REMOVED +osGLOBAL void +itdssIOUnderFlowWithChkConditionHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam + ); +#endif + +osGLOBAL void +itdssEncryptionHandler ( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); + +osGLOBAL void +itdssXferOpenRetryBackoffThresholdReachedHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); + +osGLOBAL void +itdssOpenCnxErrorItNexusLossOpenTmoHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); +osGLOBAL void +itdssOpenCnxErrorItNexusLossNoDestHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); +osGLOBAL void +itdssOpenCnxErrorItNexusLossOpenCollideHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); +osGLOBAL void +itdssOpenCnxErrorItNexusLossOpenPathwayBlockedHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); +osGLOBAL void +itdssDifHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); + +osGLOBAL void +itdssIOResourceUnavailableHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); + +osGLOBAL void +itdssIORQEBusyFullHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); + +osGLOBAL void +itdssXferErrorInvalidSSPRspFrameHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); + +osGLOBAL void +itdssXferErrorEOBDataOverrunHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); + +osGLOBAL void +itdssOpenCnxErrorOpenPreemptedHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); + +/* default handler */ +osGLOBAL void +itdssIODefaultHandler ( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); +osGLOBAL void +itdssIOForDebugging1Completed( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); + +osGLOBAL void +itdssIOForDebugging2Completed( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); + +osGLOBAL void +itdssIOForDebugging3Completed( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); + +osGLOBAL void +itdssInitDiscoveryModule ( + tiRoot_t *tiRoot + ); + +osGLOBAL void +itdssGetResource ( + tiRoot_t *tiRoot, + tiInitiatorResource_t *initiatorResource + ); + + +osGLOBAL void +itdssGetOperatingOptionParams( + tiRoot_t *tiRoot, + itdssOperatingOption_t *OperatingOption + ); + + +osGLOBAL FORCEINLINE bit32 +itdssIOPrepareSGL( + tiRoot_t *tiRoot, + tdIORequestBody_t *IORequestBody, + tiSgl_t *tiSgl1, + void *sglVirtualAddr + ); + +#ifdef FDS_SM +osGLOBAL void +smReportRemoval( + tiRoot_t *tiRoot, + agsaRoot_t *agRoot, + tdsaDeviceData_t *oneDeviceData, + tdsaPortContext_t *onePortContext + ); +osGLOBAL void +smReportRemovalDirect( + tiRoot_t *tiRoot, + agsaRoot_t *agRoot, + tdsaDeviceData_t *oneDeviceData + ); +osGLOBAL void +smHandleDirect( + tiRoot_t *tiRoot, + agsaRoot_t *agRoot, + tdsaDeviceData_t *oneDeviceData, + void *IDdata + ); + +osGLOBAL void +ossaSATAIDAbortCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 flag, + bit32 status + ); + +osGLOBAL void +ossaIniSetDeviceInfoCB( + agsaRoot_t *agRoot, + agsaContext_t *agContext, + agsaDevHandle_t *agDevHandle, + bit32 status, + bit32 option, + bit32 param + ); + +#endif /* FDS_SM */ + +#endif /* INITIATOR_DRIVER */ + +#ifdef TARGET_DRIVER +/***************************************************************************** +* +* SAS Target only PROTOTYPES (ttdproto.h) +* +*****************************************************************************/ +osGLOBAL bit32 +ttdssInit( + tiRoot_t *tiRoot, + tiTargetResource_t *targetResource, + tiTdSharedMem_t *tdSharedMem + ); + +osGLOBAL void +ttdssGetResource ( + tiRoot_t *tiRoot, + tiTargetResource_t *targetResource + ); + +osGLOBAL void +ttdssGetTargetParams( + tiRoot_t *tiRoot + ); + +osGLOBAL void +ttdssGetOperatingOptionParams( + tiRoot_t *tiRoot, + ttdssOperatingOption_t *OperatingOption + ); + +osGLOBAL agBOOLEAN +ttdsaXchgInit( + tiRoot_t *tiRoot, + ttdsaXchgData_t *ttdsaXchgData, + tiTargetMem_t *tgtMem, + bit32 maxNumXchgs + ); + +osGLOBAL void +ttdsaXchgLinkInit( + tiRoot_t *tiRoot, + ttdsaXchg_t *ttdsaXchg + ); + + +osGLOBAL void +ttdsaXchgFreeStruct( + tiRoot_t *tiRoot, + ttdsaXchg_t *ttdsaXchg + ); +osGLOBAL void +ttdsaSSPReqReceived( + agsaRoot_t *agRoot, + agsaDevHandle_t *agDevHandle, + agsaFrameHandle_t agFrameHandle, + bit32 agInitiatorTag, + bit32 parameter, + bit32 agFrameLen + ); + +osGLOBAL ttdsaXchg_t +*ttdsaXchgGetStruct( + agsaRoot_t *agRoot + ); +osGLOBAL void +ttdsaDumpallXchg(tiRoot_t *tiRoot); + +osGLOBAL void +tdsaProcessCDB( + agsaSSPCmdInfoUnit_t *cmdIU, + ttdsaXchg_t *ttdsaXchg + ); + +osGLOBAL bit32 +ttdssIOPrepareSGL( + tiRoot_t *tiRoot, + tdIORequestBody_t *tdIORequestBody, + tiSgl_t *tiSgl1, + tiSgl_t *tiSgl2, + void *sglVirtualAddr); + +osGLOBAL void +ttdsaIOCompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + bit32 agOtherInfo + ); + +osGLOBAL void +ttdsaTMProcess( + tiRoot_t *tiRoot, + ttdsaXchg_t *ttdsaXchg + ); + +osGLOBAL void +ttdsaSMPReqReceived( + agsaRoot_t *agRoot, + agsaDevHandle_t *agDevHandle, + agsaSMPFrameHeader_t *agFrameHeader, + agsaFrameHandle_t agFrameHandle, + bit32 agFrameLength, + bit32 phyId + ); +osGLOBAL void +ttdsaSMPCompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + //agsaSMPFrameHeader_t *agFrameHeader, (TP) + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle + ); +osGLOBAL bit32 +ttdsaSendResp( + agsaRoot_t *agRoot, + ttdsaXchg_t *ttdsaXchg + ); + +osGLOBAL void +ttdssReportRemovals( + agsaRoot_t *agRoot, + tdsaPortContext_t *onePortContext, + bit32 flag + ); + + +osGLOBAL void +ttdsaAbortAll( + tiRoot_t *tiRoot, + agsaRoot_t *agRoot, + tdsaDeviceData_t *oneDeviceData + ); + +osGLOBAL void +ttdssIOAbortedHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); + +#endif /* TARGET_DRIVER */ + + + +/***************************************************************************** +* +* For debugging only +* +*****************************************************************************/ +osGLOBAL void +tdsaPrintSwConfig( + agsaSwConfig_t *SwConfig + ); + +osGLOBAL void +tdsaPrintHwConfig( + agsaHwConfig_t *HwConfig + ); +osGLOBAL void +tdssPrintSASIdentify( + agsaSASIdentify_t *id + ); +osGLOBAL void +print_tdlist_flink(tdList_t *hdr, int type, int flag); + +osGLOBAL void +print_tdlist_blink(tdList_t *hdr, int flag); + +osGLOBAL void +tdhexdump(const char *ptitle, bit8 *pbuf, int len); + + +/***************************************************************************** +* +* SAT only PROTOTYPE +* +*****************************************************************************/ + +#ifdef SATA_ENABLE + +/***************************************************************************** + *! \brief satIOStart + * + * This routine is called to initiate a new SCSI request to SATL. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return: + * + * \e tiSuccess: I/O request successfully initiated. + * \e tiBusy: No resources available, try again later. + * \e tiIONoDevice: Invalid device handle. + * \e tiError: Other errors that prevent the I/O request to be started. + * + * + *****************************************************************************/ + +GLOBAL bit32 satIOStart( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext + ); + +/***************************************************************************** + *! \brief satIOAbort + * + * This routine is called to initiate a I/O abort to SATL. + * This routine is independent of HW/LL API. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param taskTag: Pointer to TISA I/O request context/tag to be aborted. + * + * \return: + * + * \e tiSuccess: I/O request successfully initiated. + * \e tiBusy: No resources available, try again later. + * \e tiError: Other errors that prevent the I/O request to be started. + * + * + *****************************************************************************/ + +GLOBAL bit32 satIOAbort( + tiRoot_t *tiRoot, + tiIORequest_t *taskTag ); + + +/***************************************************************************** + *! \brief satTM + * + * This routine is called to initiate a TM request to SATL. + * This routine is independent of HW/LL API. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param task: SAM-3 task management request. + * \param lun: Pointer to LUN. + * \param taskTag: Pointer to the associated task where the TM + * command is to be applied. + * \param currentTaskTag: Pointer to tag/context for this TM request. + * + * \return: + * + * \e tiSuccess: I/O request successfully initiated. + * \e tiBusy: No resources available, try again later. + * \e tiIONoDevice: Invalid device handle. + * \e tiError: Other errors that prevent the I/O request to be started. + * + * + *****************************************************************************/ + +osGLOBAL bit32 satTM( + tiRoot_t *tiRoot, + tiDeviceHandle_t *tiDeviceHandle, + bit32 task, + tiLUN_t *lun, + tiIORequest_t *taskTag, + tiIORequest_t *currentTaskTag, + tdIORequestBody_t *tiRequestBody, + bit32 NotifyOS + ); + + +#endif /* SAT only */ + +#ifdef INITIATOR_DRIVER +#ifdef TD_DISCOVER + +osGLOBAL void +tdsaExpanderInit( + tiRoot_t *tiRoot + ); + +osGLOBAL bit32 +tdsaDiscover( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + bit32 type, + bit32 option + ); + +osGLOBAL bit32 +tdsaSASFullDiscover( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext + ); + +osGLOBAL bit32 +tdsaSATAFullDiscover( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext + ); +osGLOBAL bit32 +tdsaSASIncrementalDiscover( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext + ); + +osGLOBAL bit32 +tdsaSATAIncrementalDiscover( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext + ); + +osGLOBAL void +tdsaSASUpStreamDiscoverStart( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaDeviceData_t *oneDeviceData + ); + +osGLOBAL void +tdsaSASUpStreamDiscovering( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaDeviceData_t *oneDeviceData + ); + + +osGLOBAL void +tdsaSASDownStreamDiscoverStart( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaDeviceData_t *oneDeviceData + ); + +osGLOBAL void +tdsaSASDownStreamDiscovering( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaDeviceData_t *oneDeviceData + ); + +osGLOBAL void +tdsaSASDiscoverDone( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + bit32 flag + ); + +osGLOBAL void +tdsaSATADiscoverDone( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + bit32 flag + ); + +osGLOBAL void +tdsaAckBC( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext + ); + +osGLOBAL void +tdsaDiscoveryResetProcessed( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext + ); + + + +osGLOBAL void +tdsaSASUpStreamDiscoverExpanderPhy( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaExpander_t *oneExpander, + smpRespDiscover_t *pDiscoverResp + ); +osGLOBAL tdsaExpander_t * +tdsaFindUpStreamConfigurableExp(tiRoot_t *tiRoot, + tdsaExpander_t *oneExpander); + +osGLOBAL void +tdsaSASDownStreamDiscoverExpanderPhy( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaExpander_t *oneExpander, + smpRespDiscover_t *pDiscoverResp + ); +osGLOBAL void +tdsaSASUpStreamDiscoverExpanderPhySkip( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaExpander_t *oneExpander + ); +osGLOBAL tdsaExpander_t * +tdsaFindDownStreamConfigurableExp(tiRoot_t *tiRoot, + tdsaExpander_t *oneExpander); + +osGLOBAL void +tdsaSASDownStreamDiscoverExpanderPhySkip( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaExpander_t *oneExpander + ); +osGLOBAL void +tdsaDiscoveringStpSATADevice( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaDeviceData_t *oneDeviceData + ); + + +osGLOBAL void +tdsaSASExpanderUpStreamPhyAdd( + tiRoot_t *tiRoot, + tdsaExpander_t *oneExpander, + bit8 phyId + ); + +osGLOBAL void +tdsaSASExpanderDownStreamPhyAdd( + tiRoot_t *tiRoot, + tdsaExpander_t *oneExpander, + bit8 phyId + ); +osGLOBAL bit16 +tdsaFindCurrentDownStreamPhyIndex( + tiRoot_t *tiRoot, + tdsaExpander_t *oneExpander + ); + +osGLOBAL tdsaDeviceData_t * +tdsaPortSASDeviceFind( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + bit32 sasAddrLo, + bit32 sasAddrHi + ); + +GLOBAL tdsaDeviceData_t * +tdsaPortSASDeviceAdd( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + agsaSASIdentify_t sasIdentify, + bit32 sasInitiator, + bit8 connectionRate, + bit32 itNexusTimeout, + bit32 firstBurstSize, + bit32 deviceType, + tdsaDeviceData_t *oneExpDeviceData, + bit8 phyID + ); + + + + + +/* in tdport.c */ +osGLOBAL tdsaDeviceData_t * +tdssNewAddSASToSharedcontext( + agsaRoot_t *agRoot, + tdsaPortContext_t *onePortContext, + tdsaSASSubID_t *agSASSubID, + tdsaDeviceData_t *oneExpDeviceData, + bit8 phyID + ); +osGLOBAL void +tdsaResetValidDeviceData( + agsaRoot_t *agRoot, + tdsaPortContext_t *onePortContext + ); + + +osGLOBAL void +tdssReportChanges( + agsaRoot_t *agRoot, + tdsaPortContext_t *onePortContext ); + +osGLOBAL void +tdssReportRemovals( + agsaRoot_t *agRoot, + tdsaPortContext_t *onePortContext, + bit32 flag + ); +osGLOBAL void +tdssInternalRemovals( + agsaRoot_t *agRoot, + tdsaPortContext_t *onePortContext + ); +osGLOBAL void +tdssDiscoveryErrorRemovals( + agsaRoot_t *agRoot, + tdsaPortContext_t *onePortContext + ); + +osGLOBAL void +tdsaSASDiscoverAbort( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext + ); + + +osGLOBAL tdsaDeviceData_t * +tdsaFindRegNValid( + agsaRoot_t *agRoot, + tdsaPortContext_t *onePortContext, + tdsaSASSubID_t *agSASSubID + ); +bit32 +tdssNewSASorNot( + agsaRoot_t *agRoot, + tdsaPortContext_t *onePortContext, + tdsaSASSubID_t *agSASSubID + ); + + +osGLOBAL tdsaExpander_t * +tdssSASDiscoveringExpanderAlloc( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaDeviceData_t *oneDeviceData + ); + +osGLOBAL void +tdssSASDiscoveringExpanderAdd( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaExpander_t *oneExpander + ); + +osGLOBAL void +tdssSASDiscoveringExpanderRemove( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaExpander_t *oneExpander + ); + +GLOBAL bit32 +tdssSATADeviceTypeDecode( + bit8 *pSignature + ); + + +GLOBAL tdsaDeviceData_t * +tdsaPortSATADeviceAdd( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaDeviceData_t *oneSTPBridge, + bit8 *Signature, + bit8 pm, + bit8 pmField, + bit8 connectionRate, + tdsaDeviceData_t *oneExpDeviceData, + bit8 phyID + ); + +/* in tdport.c */ +osGLOBAL tdsaDeviceData_t * +tdssNewAddSATAToSharedcontext(tiRoot_t *tiRoot, + agsaRoot_t *agRoot, + tdsaPortContext_t *onePortContext, + agsaSATADeviceInfo_t *agSATADeviceInfo, + bit8 *Signature, + bit8 pm, + bit8 pmField, + bit32 connectionRate, + tdsaDeviceData_t *oneExpDeviceData, + bit8 phyID + ); + +osGLOBAL tdsaDeviceData_t * +tdsaFindRightDevice( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaDeviceData_t *tdsaDeviceData + ); +GLOBAL void +ossaIDCDiscoverCompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + void *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle + ); + +osGLOBAL bit8 +tdsaFindLocalLinkRate( + tiRoot_t *tiRoot, + tdsaPortStartInfo_t *tdsaPortStartInfo + ); + +/* SMP related */ + +osGLOBAL bit32 +tdSMPStart( + tiRoot_t *tiRoot, + agsaRoot_t *agRoot, + tdsaDeviceData_t *oneDeviceData, + bit32 functionCode, + bit8 *pSmpBody, + bit32 smpBodySize, + bit32 agRequestType, + tiIORequest_t *CurrentTaskTag, + bit32 queueNumber + ); +//temp for testing +osGLOBAL void +tdsaReportManInfoSend( + tiRoot_t *tiRoot, + tdsaDeviceData_t *oneDeviceData + ); + +osGLOBAL void +tdsaReportManInfoRespRcvd( + tiRoot_t *tiRoot, + agsaRoot_t *agRoot, + tdsaDeviceData_t *oneDeviceData, + tdssSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ); + +//end temp for testing + +osGLOBAL void +tdsaReportGeneralSend( + tiRoot_t *tiRoot, + tdsaDeviceData_t *oneDeviceData + ); + +osGLOBAL void +tdsaReportGeneralRespRcvd( + tiRoot_t *tiRoot, + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + tdsaDeviceData_t *oneDeviceData, + tdssSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ); +osGLOBAL void +tdsaDiscoverSend( + tiRoot_t *tiRoot, + tdsaDeviceData_t *oneDeviceData + ); + +osGLOBAL void +tdsaDiscoverRespRcvd( + tiRoot_t *tiRoot, + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + tdsaDeviceData_t *oneDeviceData, + tdssSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ); + + +osGLOBAL void +tdsaReportPhySataSend( + tiRoot_t *tiRoot, + tdsaDeviceData_t *oneDeviceData, + bit8 phyId + ); + + + +osGLOBAL void +tdsaReportPhySataRcvd( + tiRoot_t *tiRoot, + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + tdsaDeviceData_t *oneDeviceData, + tdssSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ); + +osGLOBAL bit32 +tdsaSASRoutingEntryAdd( + tiRoot_t *tiRoot, + tdsaExpander_t *oneExpander, + bit32 phyId, + bit32 configSASAddressHi, + bit32 configSASAddressLo + ); + + +osGLOBAL void +tdsaConfigRoutingInfoRespRcvd( + tiRoot_t *tiRoot, + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + tdsaDeviceData_t *oneDeviceData, + tdssSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ); + +osGLOBAL bit32 +tdsaPhyControlSend( + tiRoot_t *tiRoot, + tdsaDeviceData_t *oneDeviceData, + bit8 phyOp, + tiIORequest_t *CurrentTaskTag, + bit32 queueNumber + ); + +osGLOBAL void +tdsaPhyControlRespRcvd( + tiRoot_t *tiRoot, + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + tdsaDeviceData_t *oneDeviceData, + tdssSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle, + tiIORequest_t *CurrentTaskTag + ); + +osGLOBAL void +tdsaPhyControlFailureRespRcvd( + tiRoot_t *tiRoot, + agsaRoot_t *agRoot, + tdsaDeviceData_t *oneDeviceData, + tdssSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle, + tiIORequest_t *CurrentTaskTag + ); + + +osGLOBAL void +tdsaDumpAllExp( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaExpander_t *oneExpander + ); +osGLOBAL void +tdsaDumpAllUpExp( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaExpander_t *oneExpander + ); +osGLOBAL void +tdsaCleanAllExp( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext + ); +osGLOBAL void +tdsaFreeAllExp( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext + ); +osGLOBAL void +tdsaDumpAllFreeExp( + tiRoot_t *tiRoot + ); + +osGLOBAL void +tdsaDiscoveryTimer(tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaDeviceData_t *oneDeviceData + ); + +osGLOBAL void +tdsaDiscoveryTimerCB( + tiRoot_t * tiRoot, + void * timerData1, + void * timerData2, + void * timerData3 + ); + +osGLOBAL void +tdsaConfigureRouteTimer(tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaExpander_t *oneExpander, + smpRespDiscover_t *ptdSMPDiscoverResp + ); + +osGLOBAL void +tdsaConfigureRouteTimerCB( + tiRoot_t * tiRoot, + void * timerData1, + void * timerData2, + void * timerData3 + ); + +osGLOBAL void +tdsaDeviceRegistrationTimer(tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaDeviceData_t *oneDeviceData + ); + +osGLOBAL void +tdsaDeviceRegistrationTimerCB( + tiRoot_t * tiRoot, + void * timerData1, + void * timerData2, + void * timerData3 + ); + +osGLOBAL void +tdsaSMPBusyTimer(tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaDeviceData_t *oneDeviceData, + tdssSMPRequestBody_t *tdSMPRequestBody + ); + +osGLOBAL void +tdsaSMPBusyTimerCB( + tiRoot_t * tiRoot, + void * timerData1, + void * timerData2, + void * timerData3 + ); + +osGLOBAL void +tdsaSATAIDDeviceTimer(tiRoot_t *tiRoot, + tdsaDeviceData_t *oneDeviceData + ); +#ifdef FDS_SM +osGLOBAL void +tdIDStartTimer(tiRoot_t *tiRoot, + smIORequest_t *smIORequest, + tdsaDeviceData_t *oneDeviceData + ); +osGLOBAL void +tdIDStartTimerCB( + tiRoot_t * tiRoot, + void * timerData1, + void * timerData2, + void * timerData3 + ); +#endif +osGLOBAL void +tdsaBCTimer(tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext + ); + +osGLOBAL void +tdsaBCTimerCB( + tiRoot_t * tiRoot, + void * timerData1, + void * timerData2, + void * timerData3 + ); + +osGLOBAL void +tdsaSATAIDDeviceTimerCB( + tiRoot_t * tiRoot, + void * timerData1, + void * timerData2, + void * timerData3 + ); + +osGLOBAL void +tdsaDiscoverySMPTimer(tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + bit32 functionCode, + tdssSMPRequestBody_t *tdSMPRequestBody + ); + +osGLOBAL void +tdsaDiscoverySMPTimerCB( + tiRoot_t * tiRoot, + void * timerData1, + void * timerData2, + void * timerData3 + ); + +osGLOBAL void +dumpRoutingAttributes( + tiRoot_t *tiRoot, + tdsaExpander_t *oneExpander, + bit8 phyID + ); + +osGLOBAL bit32 +tdsaDuplicateConfigSASAddr( + tiRoot_t *tiRoot, + tdsaExpander_t *oneExpander, + bit32 configSASAddressHi, + bit32 configSASAddressLo + ); + +osGLOBAL tdsaExpander_t * +tdsaFindConfigurableExp( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaExpander_t *oneExpander + ); + +GLOBAL bit32 +tdsaDiscoveryStartIDDev( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + tdsaDeviceData_t *oneDeviceData + ); + +GLOBAL void satFreeIntIoResource( + tiRoot_t *tiRoot, + satDeviceData_t *satDevData, + satInternalIo_t *satIntIo); +osGLOBAL void +tddmDeregisterDevicesInPort( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext + ); + +#ifdef AGTIAPI_CTL +osGLOBAL void +tdsaCTLSet( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tiIntrEventType_t eventType, + bit32 eventStatus); + +STATIC void +tdsaCTLNextDevice( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdIORequest_t *tdIORequest, + tdList_t *DeviceList); + +STATIC int +tdsaCTLModeSelect( + tiRoot_t *tiRoot, + tiDeviceHandle_t *tiDeviceHandle, + tdIORequest_t *tdIORequest); + +STATIC void +tdsaCTLIOCompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit16 sspTag, + bit32 agOtherInfo); +#endif /* AGTIAPI_CTL */ + +#endif /* TD_DISCOVER */ +#endif /* INITIATOR_DRIVER */ + +#ifdef FDS_DM +/********** For DM *******/ +osGLOBAL tdsaDeviceData_t * +tddmPortDeviceAdd( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + dmDeviceInfo_t *dmDeviceInfo, + tdsaDeviceData_t *oneExpDeviceData + ); + +osGLOBAL void +tddmInvalidateDevicesInPort( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext + ); + +osGLOBAL bit32 +tddmNewSASorNot( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaSASSubID_t *agSASSubID + ); + +osGLOBAL tdsaDeviceData_t * +tddmPortSASDeviceFind( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + bit32 sasAddrLo, + bit32 sasAddrHi + ); + +osGLOBAL tdsaDeviceData_t * +tddmAddToSharedcontext( + agsaRoot_t *agRoot, + tdsaPortContext_t *onePortContext, + tdsaSASSubID_t *agSASSubID, + tdsaDeviceData_t *oneExpDeviceData, + bit8 phyID + ); + +osGLOBAL void +tdsaUpdateMCN( + dmRoot_t *dmRoot, + tdsaPortContext_t *onePortContext + ); +#endif + +GLOBAL void +tdsaSingleThreadedEnter(tiRoot_t *ptiRoot, bit32 queueId); + +GLOBAL void +tdsaSingleThreadedLeave(tiRoot_t *ptiRoot, bit32 queueId); + +#ifdef PERF_COUNT +GLOBAL void +tdsaEnter(tiRoot_t *ptiRoot, int io); + +GLOBAL void +tdsaLeave(tiRoot_t *ptiRoot, int io); + +#define TDSA_INP_ENTER(root) tdsaEnter(root, 0) +#define TDSA_INP_LEAVE(root) tdsaLeave(root, 0) +#define TDSA_OUT_ENTER(root) tdsaEnter(root, 1) +#define TDSA_OUT_LEAVE(root) tdsaLeave(root, 1) +#else +#define TDSA_INP_ENTER(root) +#define TDSA_INP_LEAVE(root) +#define TDSA_OUT_ENTER(root) +#define TDSA_OUT_LEAVE(root) +#endif + +#if defined(FDS_DM) && defined(FDS_SM) +GLOBAL void +tdIDStart( + tiRoot_t *tiRoot, + agsaRoot_t *agRoot, + smRoot_t *smRoot, + tdsaDeviceData_t *oneDeviceData, + tdsaPortContext_t *onePortContext + ); +#endif + +void t_MacroCheck( agsaRoot_t *agRoot); + +#endif /* __TDPROTO_H__ */ diff --git a/sys/dev/pms/RefTisa/tisa/sassata/common/tdsatypes.h b/sys/dev/pms/RefTisa/tisa/sassata/common/tdsatypes.h new file mode 100644 index 000000000000..9f56775f06b8 --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/common/tdsatypes.h @@ -0,0 +1,387 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/*******************************************************************************/ +/** \file + * + * + * The file defines data structures for SAS/SATA TD layer + * + */ + +#ifndef __TDSATYPES_H +#define __TDSATYPES_H + +#define ESGL_PAGES_SIZE sizeof(agsaEsgl_t) /** the esgl page size */ +#define NUM_ESGL_PAGES 0 /* old value 512 */ /**< the default number of esgl pages */ + + +/**< target device type */ +#define TD_DEFAULT_DEVICE 0 +#define TD_SAS_DEVICE 1 +#define TD_SATA_DEVICE 2 + +#include + + +/** \brief data structure for SATA Host + * + * to be developed + * + */ +typedef struct itdstHost_s +{ + int i; +} itdstHost_t; + +/** \brief data structure for SATA Device + * + * to be developed + * + */ +typedef struct ttdstDevice_s +{ + int i; +} ttdstDevice_t; + +#ifdef INITIATOR_DRIVER +typedef struct itdsaIni_s { + /**< point to the shared structure bothe SAS and SATA */ + struct tdsaContext_s *tdsaAllShared; + itdssOperatingOption_t OperatingOption; + tdSCSIStatusCount_t ScsiStatusCounts; + tdSenseKeyCount_t SenseKeyCounter; + bit32 NumIOsActive; + /* the list of initiator timer; upon expiration timer CB fn is called + eg) itdProcessTimers() + */ + tdList_t timerlist; +} itdsaIni_t; +#endif + +struct ttdsaXchgAllocFreeInfoList_s; + +#ifdef TARGET_DRIVER +typedef struct ttdsaTgt_s { + /* point to the shared across SAS and SATA */ + struct tdsaContext_s *tdsaAllShared; + ttdssOperatingOption_t OperatingOption; + tiTargetOption_t tiOperatingOption; + ttdsaXchgData_t ttdsaXchgData; +#ifdef PASSTHROUGH + /* registered passthrough CB */ + ostiProcessPassthroughCmnd_t PasthroughCB; +#endif +} ttdsaTgt_t; +#endif + + +/** \brief data structure for SATA Device + * + * not in use yet. just a place holderto be develped + * + */ +typedef struct tdHardwareInfo_s { + bit16 DeviceID; + bit16 VendorID; + bit8 ChipRev; + bit32 PciFunctionNumber; + bit32 FlashRomPresent; +} tdHardwareInfo_t; + + +/** \brief data structure for ESLG page + * + * This data structure describes the ESGL page maintained in TD layer. + * One important field is agEsgl which is pointer to assaEsgl_t data structure, + * which describes ESGL used in lower layer. + * Memory for this data structure is allocated using tiTdSharedMem_t data + * structure. However, Memory for agsaEsgl_t data structure is allocated using + * tiLoLevelResource_t. + * + */ +typedef struct tdsaEsglPageInfo_s { + tdList_t tdlist; /**< pointers to next and previous pages */ + bit32 physAddressUpper; /**< upper physical address of the page */ + bit32 physAddressLower; /**< lower physical address of the page */ + bit32 len; + agsaEsgl_t *agEsgl; + bit32 id; /**< for debugging only */ +} tdsaEsglPageInfo_t; + +/** \brief data structure for ESLG page pool + * + * This data structure describes the pool of esgl pages + * + */ +typedef struct tdsaEsglPagePool_s { + tdsaEsglPageInfo_t EsglPages[1]; /**< variable size array */ +} tdsaEsglPagePool_t; + + +/** \brief data structure for ESGL pool information + * + * This data structure maintains information about ESGL pool. For example, this + * data structure maintains the number of free and total ESGL pages and uses + * tdList_t data structure for listing of ESGL pages. + * + */ +typedef struct tdsaEsglAllInfo_s { + /* + used in tdGetEsglPages() + */ + tdList_t mainlist; /* not used */ + tdList_t freelist; + bit32 NumEsglPages; + bit32 NumFreeEsglPages; + bit32 EsglPageSize; + bit32 physAddrUpper; + bit32 physAddrLower; + void *virtPtr; + tdsaEsglPagePool_t *EsglPagePool; +} tdsaEsglAllInfo_t; + +typedef struct smp_pass_through_req +{ + bit8 exp_sas_addr[8]; //Storing the 16 digit expander SAS-address + bit32 smp_req_len; //Length of the request frame + bit32 smp_resp_len; //Length of the response frame + bit8 smp_req_resp[1]; //Pointer to the request-response frame +}smp_pass_through_req_t; + +#ifdef TD_INT_COALESCE +typedef struct tdsaIntCoalesceContext_s { + tdList_t MainLink; /* free */ + tdList_t FreeLink; /* in use */ + struct tdsaContext_s *tdsaAllShared; +#ifdef OS_INT_COALESCE + tiIntCoalesceContext_t *tiIntCoalesceCxt; +#endif + agsaIntCoalesceContext_t agIntCoalCxt; + /* for debug */ + bit32 id; + +} tdsaIntCoalesceContext_t; +#endif + +typedef struct tdsaHwEventSource_s { + bit32 EventValid; + agsaEventSource_t Source; +} tdsaHwEventSource_t; + +/** \brief data structure for SAS/SATA context at TD layer + * + * This data structure is used for both SAS and SATA. + * In addition, this is the data structure used mainly to communicate with + * lower layer. + * + */ +typedef struct tdsaContext_s { + bit32 currentOperation; + + /**< agsaRoot_t->osData points to this */ + struct tdsaRootOsData_s agRootOsDataForInt; /* for interrupt */ + struct tdsaRootOsData_s agRootOsDataForNonInt; /* for non-interrupt */ + + agsaRoot_t agRootInt; /* for interrupt */ + agsaRoot_t agRootNonInt; /* for non-interrupt */ + + /* flags values commonly used for both SAS and SATA */ + struct tdsaComMemFlags_s flags; + + + /**< software-related initialization params used in saInitialize() */ + agsaSwConfig_t SwConfig; + + /**< Queue-related initialization params used in saInitialize() */ + agsaQueueConfig_t QueueConfig; + + /**< hardware-related initialization params used in saInitialize() */ + agsaHwConfig_t HwConfig; + + + /**< Copy of TI low level resoure */ + tiLoLevelResource_t loResource; + + /* information of ESGL pages allocated + tdsaEsglAllInfo_t EsglAllInfo; + */ + + /* hardware information; just place holder + tdHardwareInfo_t hwInfo; + */ + + bit32 currentInterruptDelay; + + /**< timers used commonly in SAS/SATA */ + tdList_t timerlist; + /***********************************************************************/ + /* used to be in tdssContext_t tdssSASShared;*/ + struct itdsaIni_s *itdsaIni; /* Initiator; */ + struct ttdsaTgt_s *ttdsaTgt; /* Target */ + /**< pointer to PortContext memory; */ + tdsaPortContext_t *PortContextMem; + /**< pointer to Device memory */ + tdsaDeviceData_t *DeviceMem; + + tdList_t FreePortContextList; + tdList_t MainPortContextList; + tdList_t FreeDeviceList; + tdList_t MainDeviceList; + + /**< actual storage for jump table */ + tdsaJumpTable_t tdJumpTable; + /**< Local SAS port start information such as ID addr */ + tdsaPortStartInfo_t Ports[TD_MAX_NUM_PHYS]; + /***********************************************************************/ + /**< storage for FW download contents */ + tdFWControlEx_t tdFWControlEx; +#ifdef SPC_ENABLE_PROFILE + tdFWProfileEx_t tdFWProfileEx; +#endif +#ifdef TD_INT_COALESCE + tdsaIntCoalesceContext_t *IntCoalesce; +#endif + + /* first time a card is processed set this true */ + bit32 first_process; + + /* expander list */ + tdsaExpander_t *ExpanderHead; + // tdList_t discoveringExpanderList; + tdList_t freeExpanderList; + bit32 phyCount; + bit32 IBQnumber; + bit32 OBQnumber; + bit32 InboundQueueSize[AGSA_MAX_OUTBOUND_Q]; + bit32 InboundQueueEleSize[AGSA_MAX_OUTBOUND_Q]; + bit32 OutboundQueueSize[AGSA_MAX_OUTBOUND_Q]; + bit32 OutboundQueueEleSize[AGSA_MAX_OUTBOUND_Q]; + bit32 OutboundQueueInterruptDelay[AGSA_MAX_OUTBOUND_Q]; + bit32 OutboundQueueInterruptCount[AGSA_MAX_OUTBOUND_Q]; + bit32 OutboundQueueInterruptEnable[AGSA_MAX_OUTBOUND_Q]; + bit32 InboundQueuePriority[AGSA_MAX_INBOUND_Q]; + bit32 QueueOption; + bit32 tdDeviceIdVendId; + bit32 tdSubVendorId; + /* instance number */ + bit8 CardIDString[TD_CARD_ID_LEN]; + bit32 CardID; +#ifdef VPD_TESTING + /* temp; for testing VPD indirect */ + bit32 addrUpper; + bit32 addrLower; +#endif + + bit32 resetCount; + tdsaHwEventSource_t eventSource[TD_MAX_NUM_PHYS]; + bit32 portTMO; /* in 100ms */ + bit32 phyCalibration; /* enables or disables phy calibration */ + bit32 FCA; /* force to clear affiliation by sending SMP HARD RESET */ + bit32 SMPQNum; /* first high priority queue number for SMP */ + bit32 ResetInDiscovery; /* hard/link reset in discovery */ + bit32 FWMaxPorts; + bit32 IDRetry; /* SATA ID failurs are retired */ + bit32 RateAdjust; /* allow retry open with lower connection rate */ +#ifdef AGTIAPI_CTL + bit16 SASConnectTimeLimit; /* used by tdsaCTLSet() */ +#endif + bit32 MaxNumOSLocks; /* max number of OS layer locks */ + bit32 MaxNumLLLocks; /* max num of LL locks */ + bit32 MaxNumLocks; /* max num of locks for layers and modules (LL, TDM, SATM, DM) */ +#ifdef FDS_DM + bit32 MaxNumDMLocks; /* max num of DM locks */ + dmRoot_t dmRoot; /* discovery root */ + dmSwConfig_t dmSwConfig; +#endif +#ifdef FDS_SM + bit32 MaxNumSMLocks; /* max num of SM locks */ + smRoot_t smRoot; /* SATM root */ + smSwConfig_t smSwConfig; +#endif + bit32 MCN; /* temp; only for testing and to be set by registry or adj file */ + bit32 sflag; /* Sflag bit */ +#ifdef CCFLAGS_PHYCONTROL_COUNTS + agsaPhyAnalogSetupRegisters_t analog[TD_MAX_NUM_PHYS]; +#endif /* CCFLAGS_PHYCONTROL_COUNTS */ + bit32 stp_idle_time; /* stp idle time for agsaSASProtocolTimerConfigurationPage_t; set by registry or adj file */ + bit32 STP_MCT_TMO; /* for agsaSASProtocolTimerConfigurationPage_t; set by registry or adj file */ + bit32 SSP_MCT_TMO; /* for agsaSASProtocolTimerConfigurationPage_t; set by registry or adj file */ + bit32 MAX_OPEN_TIME; /* for agsaSASProtocolTimerConfigurationPage_t; set by registry or adj file */ + bit32 SMP_MAX_CONN_TIMER; /* for agsaSASProtocolTimerConfigurationPage_t; set by registry or adj file */ + bit32 STP_FRM_TMO; /* for agsaSASProtocolTimerConfigurationPage_t; set by registry or adj file */ + bit32 MFD; /* for agsaSASProtocolTimerConfigurationPage_t; set by registry or adj file */ + bit32 OPNRJT_RTRY_INTVL; /* for agsaSASProtocolTimerConfigurationPage_t; set by registry or adj file */ + bit32 DOPNRJT_RTRY_TMO; /* for agsaSASProtocolTimerConfigurationPage_t; set by registry or adj file */ + bit32 COPNRJT_RTRY_TMO; /* for agsaSASProtocolTimerConfigurationPage_t; set by registry or adj file */ + bit32 DOPNRJT_RTRY_THR; /* for agsaSASProtocolTimerConfigurationPage_t; set by registry or adj file */ + bit32 COPNRJT_RTRY_THR; /* for agsaSASProtocolTimerConfigurationPage_t; set by registry or adj file */ + bit32 itNexusTimeout; /* set by registry */ + bit32 MAX_AIP; /* for agsaSASProtocolTimerConfigurationPage_t; set by registry or adj file */ + agsaMPIContext_t MpiOverride; +#ifdef TI_GETFOR_ONRESET + bit8 FatalErrorData[(5 * (1024 * 1024))]; +#endif /* TI_GETFOR_ONRESET */ + bit32 sgpioResponseSet; /*Used to sync between SGPIO Req and Resp */ + volatile NvmdResponseSet; +} tdsaContext_t; + +#ifdef FAST_IO_TEST +#define CMDS_PER_IO_IOPS 1 +#define CMDS_PER_IO_DUP 1 //4 +#endif + +/** \brief the root data structure for TD layer + * + * This data structure is the main data structure used in communicating + * with OS layer. For example, tiRoot_t->tdData points to this data structure + * From this data structure, SATA host/Device and SAS initiator/target are found. + * + */ +typedef struct tdsaRoot_s +{ + /**<< common data structure for SAS/SATA */ + tdsaContext_t tdsaAllShared; + bit32 autoGoodRSP; +#ifdef INITIATOR_DRIVER + itdsaIni_t *itdsaIni; /**< SAS/SATA initiator */ +#endif +#ifdef TARGET_DRIVER + ttdsaTgt_t *ttdsaTgt; /**< SAS/SATA target */ +#endif +} tdsaRoot_t; + +typedef struct tmf_pass_through_req +{ + bit8 pathId; + bit8 targetId; + bit8 lun; +}tmf_pass_through_req_t; + +/* Context Field accessors */ +#define TD_GET_TIROOT(sa_root) (((tdsaRootOsData_t *)(sa_root)->osData)->tiRoot) +#define TD_GET_TDROOT(ti_root) ((tdsaRoot_t *)(ti_root)->tdData) +#define TD_GET_TICONTEXT(ti_root) ((tdsaContext_t *)&TD_GET_TDROOT(ti_root)->tdsaAllShared) +#define TD_GET_TIINI_CONTEXT(ti_root) ((itdsaIni_t *)TD_GET_TICONTEXT(ti_root)->itdsaIni) +#define TD_GET_TITGT_CONTEXT(ti_root) ((ttdsaTgt_t *)TD_GET_TICONTEXT(ti_root)->ttdsaTgt) +#endif /* __TDSATYPES_H */ diff --git a/sys/dev/pms/RefTisa/tisa/sassata/common/tdsmcmnapi.c b/sys/dev/pms/RefTisa/tisa/sassata/common/tdsmcmnapi.c new file mode 100644 index 000000000000..8c32b8191779 --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/common/tdsmcmnapi.c @@ -0,0 +1,1410 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#include +#include + +#include +#include +#include +/* for TIDEBUG_MSG */ +#include + +#ifdef FDS_SM + +#include +#include +#include + +#ifdef FDS_DM +#include +#endif + +#ifdef INITIATOR_DRIVER +#include +#endif + +#include +#include +#include + +#if defined(SM_DEBUG) +extern bit32 gSMDebugLevel; +#endif + +osGLOBAL void +smReportRemovalDirect( + tiRoot_t *tiRoot, + agsaRoot_t *agRoot, + tdsaDeviceData_t *oneDeviceData + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + bit8 PhyID; + + TI_DBG2(("smReportRemovalDirect: start\n")); + + PhyID = oneDeviceData->phyID; + + tdsaAbortAll(tiRoot, agRoot, oneDeviceData); + oneDeviceData->valid = agFALSE; + oneDeviceData->valid2 = agFALSE; + /* put onedevicedata back to free list */ + osti_memset(&(oneDeviceData->satDevData.satIdentifyData), 0xFF, sizeof(agsaSATAIdentifyData_t)); + TDLIST_DEQUEUE_THIS(&(oneDeviceData->MainLink)); + TDLIST_ENQUEUE_AT_TAIL(&(oneDeviceData->FreeLink), &(tdsaAllShared->FreeDeviceList)); + + /* notifying link up */ + ostiPortEvent ( + tiRoot, + tiPortLinkUp, + tiSuccess, + (void *)tdsaAllShared->Ports[PhyID].tiPortalContext + ); +#ifdef INITIATOR_DRIVER + /* triggers discovery */ + ostiPortEvent( + tiRoot, + tiPortDiscoveryReady, + tiSuccess, + (void *) tdsaAllShared->Ports[PhyID].tiPortalContext + ); +#endif + return; +} + +osGLOBAL void +smReportRemoval( + tiRoot_t *tiRoot, + agsaRoot_t *agRoot, + tdsaDeviceData_t *oneDeviceData, + tdsaPortContext_t *onePortContext + ) +{ + TI_DBG2(("smReportRemoval: start\n")); + + if (oneDeviceData->registered == agTRUE) + { + /* + 1. remove this device + 2. device removal event + */ + tdsaAbortAll(tiRoot, agRoot, oneDeviceData); + oneDeviceData->valid = agFALSE; + oneDeviceData->valid2 = agFALSE; + oneDeviceData->registered = agFALSE; + ostiInitiatorEvent( + tiRoot, + onePortContext->tiPortalContext, + agNULL, + tiIntrEventTypeDeviceChange, + tiDeviceRemoval, + agNULL + ); + } + + return; +} +osGLOBAL void +smHandleDirect( + tiRoot_t *tiRoot, + agsaRoot_t *agRoot, + tdsaDeviceData_t *oneDeviceData, + void *IDdata + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + agsaSATAIdentifyData_t *pSATAIdData; + tdList_t *DeviceListList; + tdsaDeviceData_t *tmpOneDeviceData = agNULL; + int new_device = agTRUE; + bit8 PhyID; + + TI_DBG2(("smHandleDirect: start\n")); + PhyID = oneDeviceData->phyID; + + pSATAIdData = (agsaSATAIdentifyData_t *)IDdata; + //tdhexdump("satAddSATAIDDevCB after", (bit8 *)pSATAIdData, sizeof(agsaSATAIdentifyData_t)); + + /* compare idenitfy device data to the exiting list */ + DeviceListList = tdsaAllShared->MainDeviceList.flink; + while (DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + tmpOneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + if (tmpOneDeviceData == agNULL) + { + TI_DBG1(("smHandleDirect: tmpOneDeviceData is NULL!!!\n")); + return; + } + TI_DBG1(("smHandleDirect: LOOP tmpOneDeviceData %p did %d\n", tmpOneDeviceData, tmpOneDeviceData->id)); + //tdhexdump("smHandleDirect LOOP", (bit8 *)&tmpOneDeviceData->satDevData.satIdentifyData, sizeof(agsaSATAIdentifyData_t)); + + /* what is unique ID for sata device -> response of identify devicedata; not really + Let's compare serial number, firmware version, model number + */ + if ( tmpOneDeviceData->DeviceType == TD_SATA_DEVICE && + (osti_memcmp (tmpOneDeviceData->satDevData.satIdentifyData.serialNumber, + pSATAIdData->serialNumber, + 20) == 0) && + (osti_memcmp (tmpOneDeviceData->satDevData.satIdentifyData.firmwareVersion, + pSATAIdData->firmwareVersion, + 8) == 0) && + (osti_memcmp (tmpOneDeviceData->satDevData.satIdentifyData.modelNumber, + pSATAIdData->modelNumber, + 40) == 0) + ) + { + TI_DBG2(("smHandleDirect: did %d\n", tmpOneDeviceData->id)); + new_device = agFALSE; + break; + } + DeviceListList = DeviceListList->flink; + } + + + if (new_device == agFALSE) + { + TI_DBG2(("smHandleDirect: old device data\n")); + tmpOneDeviceData->valid = agTRUE; + tmpOneDeviceData->valid2 = agTRUE; + /* save data field from new device data */ + tmpOneDeviceData->agRoot = agRoot; + tmpOneDeviceData->agDevHandle = oneDeviceData->agDevHandle; + tmpOneDeviceData->agDevHandle->osData = tmpOneDeviceData; /* TD layer */ + tmpOneDeviceData->tdPortContext = oneDeviceData->tdPortContext; + tmpOneDeviceData->phyID = oneDeviceData->phyID; + + /* + one SATA directly attached device per phy; + Therefore, deregister then register + */ + saDeregisterDeviceHandle(agRoot, agNULL, oneDeviceData->agDevHandle, tdsaRotateQnumber(tiRoot, oneDeviceData)); + + if (tmpOneDeviceData->registered == agFALSE) + { + TI_DBG2(("smHandleDirect: re-registering old device data\n")); + /* already has old information; just register it again */ + saRegisterNewDevice( /* smHandleDirect */ + agRoot, + &tmpOneDeviceData->agContext, + 0,/*tdsaRotateQnumber(tiRoot, tmpOneDeviceData),*/ + &tmpOneDeviceData->agDeviceInfo, + tmpOneDeviceData->tdPortContext->agPortContext, + 0 + ); + } + +// tdsaAbortAll(tiRoot, agRoot, oneDeviceData); + /* put tmpOneDeviceData back to free list */ + osti_memset(&(oneDeviceData->satDevData.satIdentifyData), 0xFF, sizeof(agsaSATAIdentifyData_t)); + TDLIST_DEQUEUE_THIS(&(oneDeviceData->MainLink)); + TDLIST_ENQUEUE_AT_TAIL(&(oneDeviceData->FreeLink), &(tdsaAllShared->FreeDeviceList)); + + TI_DBG2(("smHandleDirect: pid %d\n", tdsaAllShared->Ports[PhyID].portContext->id)); + /* notifying link up */ + ostiPortEvent ( + tiRoot, + tiPortLinkUp, + tiSuccess, + (void *)tdsaAllShared->Ports[PhyID].tiPortalContext + ); + + +#ifdef INITIATOR_DRIVER + /* triggers discovery */ + ostiPortEvent( + tiRoot, + tiPortDiscoveryReady, + tiSuccess, + (void *) tdsaAllShared->Ports[PhyID].tiPortalContext + ); +#endif + return; + } + + TI_DBG2(("smHandleDirect: new device data\n")); + oneDeviceData->satDevData.satIdentifyData = *pSATAIdData; + /* notifying link up */ + ostiPortEvent ( + tiRoot, + tiPortLinkUp, + tiSuccess, + (void *)tdsaAllShared->Ports[PhyID].tiPortalContext + ); +#ifdef INITIATOR_DRIVER + /* triggers discovery */ + ostiPortEvent( + tiRoot, + tiPortDiscoveryReady, + tiSuccess, + (void *) tdsaAllShared->Ports[PhyID].tiPortalContext + ); +#endif + + return; +} + +/* + combine satAddSATAIDDevCB(expander) and satAddSATAIDDevCB(directly attached) +*/ +osGLOBAL void +tdsmIDCompletedCB( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + bit32 status, + void *IDdata + ) +{ + tdsaRoot_t *tdsaRoot; + tdsaContext_t *tdsaAllShared; + tiRoot_t *tiRoot; + agsaRoot_t *agRoot; + tdIORequestBody_t *tdIORequestBody; + tdsaDeviceData_t *oneDeviceData; + tdsaPortContext_t *onePortContext; + tiPortalContext_t *tiPortalContext; + bit32 pid = 0xff; + bit32 IDstatus; + agsaSATAIdentifyData_t *pSATAIdData; + + TI_DBG2(("tdsmIDCompletedCB: start\n")); + + tdsaRoot = (tdsaRoot_t *)smRoot->tdData; + tdsaAllShared = &(tdsaRoot->tdsaAllShared); + tiRoot = tdsaAllShared->agRootOsDataForInt.tiRoot; + tdIORequestBody = (tdIORequestBody_t *)smIORequest->tdData; + + if (smDeviceHandle == agNULL) + { + TI_DBG1(("tdsmIDCompletedCB: smDeviceHandle is NULL !!!!\n")); + ostiFreeMemory( + tiRoot, + tdIORequestBody->osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; + } + + oneDeviceData = (tdsaDeviceData_t *)smDeviceHandle->tdData; + onePortContext = oneDeviceData->tdPortContext; + agRoot = oneDeviceData->agRoot; + pid = tdIORequestBody->pid; + + +// oneDeviceData->satDevData.IDDeviceValid = agFALSE; + oneDeviceData->satDevData.IDPending = agFALSE; + + TI_DBG2(("tdsmIDCompletedCB: tdIORequestBody %p tdIORequestBody->osMemHandle %p\n", tdIORequestBody, tdIORequestBody->osMemHandle)); + + tdsaSingleThreadedEnter(tiRoot, TD_TIMER_LOCK); + + if (oneDeviceData->tdIDTimer.timerRunning == agTRUE) + { + tdsaSingleThreadedLeave(tiRoot, TD_TIMER_LOCK); + tdsaKillTimer( + tiRoot, + &oneDeviceData->tdIDTimer + ); + } + else + { + tdsaSingleThreadedLeave(tiRoot, TD_TIMER_LOCK); + } + + if (onePortContext == agNULL) + { + TI_DBG1(("tdsmIDCompletedCB: onePortContext is NULL!!!\n")); + ostiFreeMemory( + tiRoot, + tdIORequestBody->osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; + } + + /* check port id */ + if (pid != onePortContext->id) + { + TI_DBG1(("tdsmIDCompletedCB: not matching pid; pid %d onePortContext->id %d!!!\n", pid, onePortContext->id)); + if (oneDeviceData->directlyAttached == agTRUE) + { + smReportRemovalDirect(tiRoot, agRoot, oneDeviceData); + } + else + { + smReportRemoval(tiRoot, agRoot, oneDeviceData, onePortContext); + } + ostiFreeMemory( + tiRoot, + tdIORequestBody->osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; + } + + tiPortalContext= onePortContext->tiPortalContext; + + if (tiPortalContext == agNULL) + { + TI_DBG1(("tdsmIDCompletedCB: tiPortalContext is NULL!!!\n")); + if (oneDeviceData->directlyAttached == agTRUE) + { + smReportRemovalDirect(tiRoot, agRoot, oneDeviceData); + } + else + { + smReportRemoval(tiRoot, agRoot, oneDeviceData, onePortContext); + } + ostiFreeMemory( + tiRoot, + tdIORequestBody->osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; + } + + if (agRoot == agNULL) + { + TI_DBG1(("tdsmIDCompletedCB: agRoot is NULL!!!\n")); + ostiFreeMemory( + tiRoot, + tdIORequestBody->osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; + } + + if (status == smIOSuccess) + { + TI_DBG2(("tdsmIDCompletedCB: smIOSuccess\n")); + + oneDeviceData->satDevData.IDDeviceValid = agTRUE; + if (oneDeviceData->directlyAttached == agTRUE) + { + TI_DBG2(("tdsmIDCompletedCB: directlyAttached\n")); + pSATAIdData = (agsaSATAIdentifyData_t *)IDdata; + smHandleDirect(tiRoot, agRoot, oneDeviceData, IDdata); + /* filling in */ + osti_memcpy(onePortContext->remoteName, pSATAIdData->serialNumber, 20); + osti_memcpy(&(onePortContext->remoteName[20]), pSATAIdData->firmwareVersion, 8); + osti_memcpy(&(onePortContext->remoteName[28]), pSATAIdData->modelNumber, 40); + } + else /* expander attached */ + { + + TI_DBG2(("tdsmIDCompletedCB: expander attached\n")); + + if (onePortContext->DiscoveryState == ITD_DSTATE_COMPLETED) + { + TI_DBG1(("tdsmIDCompletedCB: ID completed after discovery is done; tiDeviceArrival\n")); + /* ID data completed after discovery is completed */ + ostiInitiatorEvent( + tiRoot, + tiPortalContext, + agNULL, + tiIntrEventTypeDeviceChange, + tiDeviceArrival, + agNULL + ); + } + } + TI_DBG2(("tdsmIDCompletedCB: tdIORequestBody %p tdIORequestBody->osMemHandle %p\n", tdIORequestBody, tdIORequestBody->osMemHandle)); + ostiFreeMemory( + tiRoot, + tdIORequestBody->osMemHandle, + sizeof(tdIORequestBody_t) + ); + + } + else if ( status == smIORetry) + { + TI_DBG1(("tdsmIDCompletedCB: smIORetry!!!\n")); + if ( !(oneDeviceData->valid == agTRUE && oneDeviceData->registered == agTRUE && + oneDeviceData->tdPortContext != agNULL) + ) + { + TI_DBG1(("tdsmIDCompletedCB: smIORetry but device is not valid!!!\n")); + tdIORequestBody->reTries = 0; + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + ostiFreeMemory( + tiRoot, + tdIORequestBody->osMemHandle, + sizeof(tdIORequestBody_t) + ); + oneDeviceData->satDevData.IDDeviceValid = agFALSE; + return; + } + + if (tdIORequestBody->reTries <= SM_RETRIES) + { + tdIORequestBody->tiIORequest = agNULL; /* not in use */ + tdIORequestBody->pid = onePortContext->id; + smIORequest->tdData = tdIORequestBody; + smIORequest->smData = &tdIORequestBody->smIORequestBody; + + smDeviceHandle->tdData = oneDeviceData; + + oneDeviceData->satDevData.IDDeviceValid = agFALSE; + + IDstatus = smIDStart(smRoot, + smIORequest, + smDeviceHandle + ); + if (IDstatus != SM_RC_SUCCESS) + { + /* identify device data is not valid */ + TI_DBG1(("tdsmIDCompletedCB: smIDStart fail or busy %d!!!\n", IDstatus)); + tdIORequestBody->reTries = 0; + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + ostiFreeMemory( + tiRoot, + tdIORequestBody->osMemHandle, + sizeof(tdIORequestBody_t) + ); + smReportRemoval(tiRoot, agRoot, oneDeviceData, onePortContext); + return; + } + tdIORequestBody->reTries++; + tdIORequestBody->ioCompleted = agFALSE; + tdIORequestBody->ioStarted = agTRUE; + oneDeviceData->satDevData.IDPending = agTRUE; + /* start a timer */ + tdIDStartTimer(tiRoot, smIORequest, oneDeviceData); + TI_DBG1(("tdsmIDCompletedCB: being retried!!!\n")); + } + else + { + /* give up */ + TI_DBG1(("tdsmIDCompletedCB: retries are over!!!\n")); + tdIORequestBody->reTries = 0; + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + ostiFreeMemory( + tiRoot, + tdIORequestBody->osMemHandle, + sizeof(tdIORequestBody_t) + ); + oneDeviceData->satDevData.IDDeviceValid = agFALSE; + /* SATA device is not usable; remove it */ + smReportRemoval(tiRoot, agRoot, oneDeviceData, onePortContext); + } + } + else if ( status == smIOSTPResourceBusy) + { + /* decides to send smp hard reset or not */ + TI_DBG1(("tdsmIDCompletedCB: smIOSTPResourceBusy\n")); + ostiFreeMemory( + tiRoot, + tdIORequestBody->osMemHandle, + sizeof(tdIORequestBody_t) + ); + oneDeviceData->satDevData.IDDeviceValid = agFALSE; + if (tdsaAllShared->FCA) + { + if (oneDeviceData->SMNumOfFCA <= 0) /* does SMP HARD RESET only upto one time */ + { + TI_DBG1(("tdsmIDCompletedCB: OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY; sending HARD_RESET\n")); + oneDeviceData->SMNumOfFCA++; + tdsaPhyControlSend(tiRoot, + oneDeviceData, + SMP_PHY_CONTROL_HARD_RESET, + agNULL, + tdsaRotateQnumber(tiRoot, oneDeviceData) + ); + } + else + { + /* given up after one time of SMP HARD RESET; */ + TI_DBG1(("tdsmIDCompletedCB: OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY; but giving up sending HARD_RESET!!!\n")); + smReportRemoval(tiRoot, agRoot, oneDeviceData, onePortContext); + } + } + else + { + /* do nothing */ + } + } + else + { + TI_DBG1(("tdsmIDCompletedCB: smIDStart fail, status 0x%x!!!\n", status)); + TI_DBG1(("tdsmIDCompletedCB: did %d!!!\n", oneDeviceData->id)); + if ( !(oneDeviceData->valid == agTRUE && oneDeviceData->registered == agTRUE && + oneDeviceData->tdPortContext != agNULL) + ) + { + TI_DBG1(("tdsmIDCompletedCB: fail but device is not valid!!!\n")); + tdIORequestBody->reTries = 0; + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + ostiFreeMemory( + tiRoot, + tdIORequestBody->osMemHandle, + sizeof(tdIORequestBody_t) + ); + oneDeviceData->satDevData.IDDeviceValid = agFALSE; + return; + } + tdsaAllShared->IDRetry = agTRUE; + if (tdsaAllShared->IDRetry) + { + if (tdIORequestBody->reTries <= SM_RETRIES) + { + tdIORequestBody->tiIORequest = agNULL; /* not in use */ + tdIORequestBody->pid = onePortContext->id; + smIORequest->tdData = tdIORequestBody; + smIORequest->smData = &tdIORequestBody->smIORequestBody; + + smDeviceHandle->tdData = oneDeviceData; + IDstatus = smIDStart(smRoot, + smIORequest, + smDeviceHandle + ); + if (IDstatus != SM_RC_SUCCESS) + { + /* identify device data is not valid */ + TI_DBG1(("tdsmIDCompletedCB: smIDStart fail or busy %d!!!\n", IDstatus)); + tdIORequestBody->reTries = 0; + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + ostiFreeMemory( + tiRoot, + tdIORequestBody->osMemHandle, + sizeof(tdIORequestBody_t) + ); + oneDeviceData->satDevData.IDDeviceValid = agFALSE; + if (oneDeviceData->directlyAttached == agTRUE) + { + smReportRemovalDirect(tiRoot, agRoot, oneDeviceData); + } + else + { + smReportRemoval(tiRoot, agRoot, oneDeviceData, onePortContext); + } + return; + } + tdIORequestBody->reTries++; + tdIORequestBody->ioCompleted = agFALSE; + tdIORequestBody->ioStarted = agTRUE; + oneDeviceData->satDevData.IDPending = agTRUE; + /* start a timer */ + tdIDStartTimer(tiRoot, smIORequest, oneDeviceData); + TI_DBG1(("tdsmIDCompletedCB: being retried!!!\n")); + } + else + { + /* give up */ + TI_DBG1(("tdsmIDCompletedCB: retries are over; sending hard reset!!!\n")); + tdIORequestBody->reTries = 0; + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + ostiFreeMemory( + tiRoot, + tdIORequestBody->osMemHandle, + sizeof(tdIORequestBody_t) + ); + oneDeviceData->satDevData.IDDeviceValid = agFALSE; + + if (oneDeviceData->SMNumOfID <= 0) /* does SMP HARD RESET only upto one time */ + { + TI_DBG1(("tdsmIDCompletedCB: fail; sending HARD_RESET\n")); + oneDeviceData->SMNumOfID++; + if (oneDeviceData->directlyAttached == agTRUE) + { + saLocalPhyControl(agRoot, agNULL, tdsaRotateQnumber(tiRoot, oneDeviceData), oneDeviceData->phyID, AGSA_PHY_HARD_RESET, agNULL); + } + else + { + tdsaPhyControlSend(tiRoot, + oneDeviceData, + SMP_PHY_CONTROL_HARD_RESET, + agNULL, + tdsaRotateQnumber(tiRoot, oneDeviceData) + ); + } + } + else + { + /* given up after one time of SMP HARD RESET; */ + TI_DBG1(("tdsmIDCompletedCB: fail; but giving up sending HARD_RESET!!!\n")); + if (oneDeviceData->directlyAttached == agTRUE) + { + smReportRemovalDirect(tiRoot, agRoot, oneDeviceData); + } + else + { + smReportRemoval(tiRoot, agRoot, oneDeviceData, onePortContext); + } + } + } + } + else + { + /* do nothing */ + } + + + } + + + return; +} + +FORCEINLINE void +tdsmIOCompletedCB( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + bit32 status, + bit32 statusDetail, + smSenseData_t *senseData, + bit32 interruptContext + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *)smRoot->tdData; + tdsaContext_t *tdsaAllShared = &(tdsaRoot->tdsaAllShared); + tiRoot_t *tiRoot = tdsaAllShared->agRootOsDataForInt.tiRoot; + tdIORequestBody_t *tdIORequestBody = (tdIORequestBody_t *)smIORequest->tdData; + tiIORequest_t *tiIORequest = tdIORequestBody->tiIORequest; + + tdsaDeviceData_t *oneDeviceData; + tiDeviceHandle_t *tiDeviceHandle; + smDeviceHandle_t *smDeviceHandle; + smScsiInitiatorRequest_t *smSCSIRequest; + smSuperScsiInitiatorRequest_t *smSuperSCSIRequest; + + bit32 SMStatus = SM_RC_FAILURE; + + + TI_DBG5(("tdsmIOCompletedCB: start\n")); + + if (status == smIOSuccess) + { + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + status, + statusDetail, + (tiSenseData_t *)senseData, + interruptContext); + } + else if (status == smIORetry) + { + TI_DBG1(("tdsmIOCompletedCB: smIORetry!!!\n")); + smIORequest = (smIORequest_t *)&(tdIORequestBody->smIORequest); + tiDeviceHandle = tdIORequestBody->tiDevHandle; + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + + if (! (oneDeviceData->valid == agTRUE && oneDeviceData->registered == agTRUE && + oneDeviceData->tdPortContext != agNULL) + ) + { + TI_DBG1(("tdsmIOCompletedCB: smIORetry but device is not valid!!!\n")); + tdIORequestBody->reTries = 0; + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + status, + statusDetail, + (tiSenseData_t *)senseData, + interruptContext); + return; + } + if (tdIORequestBody->reTries <= SM_RETRIES) + { + smDeviceHandle = (smDeviceHandle_t *)&(oneDeviceData->smDeviceHandle); + if (tdIORequestBody->superIOFlag == agTRUE) + { + smSuperSCSIRequest = (smSuperScsiInitiatorRequest_t *)&(tdIORequestBody->SM.smSuperSCSIRequest); + SMStatus = smSuperIOStart(smRoot, + smIORequest, + smDeviceHandle, + smSuperSCSIRequest, + oneDeviceData->SASAddressID.sasAddressHi, + oneDeviceData->SASAddressID.sasAddressLo, + interruptContext); + } + else + { + smSCSIRequest = (smScsiInitiatorRequest_t *)&(tdIORequestBody->SM.smSCSIRequest); + SMStatus = smIOStart(smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + interruptContext); + } + + + if (SMStatus != SM_RC_SUCCESS) + { + TI_DBG1(("tdsmIOCompletedCB: smIDStart fail or busy %d!!!\n", SMStatus)); + tdIORequestBody->reTries = 0; + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + status, + statusDetail, + (tiSenseData_t *)senseData, + interruptContext); + return; + } + else + { + TI_DBG1(("tdsmIOCompletedCB: being retried!!!\n")); + tdIORequestBody->reTries++; + tdIORequestBody->ioCompleted = agFALSE; + tdIORequestBody->ioStarted = agTRUE; + } + } + else + { + /* give up; complete IO */ + TI_DBG1(("tdsmIOCompletedCB: retries are over!!!\n")); + tdIORequestBody->reTries = 0; + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + status, + statusDetail, + (tiSenseData_t *)senseData, + interruptContext); + return; + } + + } + else if ( status == smIOSTPResourceBusy) + { + /* decides to send smp hard reset or not */ + TI_DBG1(("tdsmIOCompletedCB: smIOSTPResourceBusy\n")); + if (tdsaAllShared->FCA) + { + smIORequest = (smIORequest_t *)&(tdIORequestBody->smIORequest); + tiDeviceHandle = tdIORequestBody->tiDevHandle; + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + if (oneDeviceData->SMNumOfFCA <= 0) /* does SMP HARD RESET only upto one time */ + { + TI_DBG1(("tdsmIOCompletedCB: OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY; sending HARD_RESET\n")); + oneDeviceData->SMNumOfFCA++; + tdsaPhyControlSend(tiRoot, + oneDeviceData, + SMP_PHY_CONTROL_HARD_RESET, + agNULL, + tdsaRotateQnumber(tiRoot, oneDeviceData) + ); + } + else + { + /* given up after one time of SMP HARD RESET; */ + TI_DBG1(("tdsmIOCompletedCB: OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY; but giving up sending HARD_RESET!!!\n")); + } + } + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + status, + statusDetail, + (tiSenseData_t *)senseData, + interruptContext); + return; + } + else + { + if (statusDetail == smDetailAborted) + { + tiDeviceHandle = tdIORequestBody->tiDevHandle; + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + TI_DBG1(("tdsmIOCompletedCB: agIOStatus = OSSA_IO_ABORTED did %d\n", oneDeviceData->id)); + } + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + status, + statusDetail, + (tiSenseData_t *)senseData, + interruptContext); + } + + return; +} + +/* completion of taskmanagement +osGLOBAL void ostiInitiatorEvent ( + tiRoot_t *tiRoot, + tiPortalContext_t *portalContext, + tiDeviceHandle_t *tiDeviceHandle, + tiIntrEventType_t eventType, + bit32 eventStatus, + void *parm + ); + +*/ +//qqq1 +osGLOBAL void +tdsmEventCB( + smRoot_t *smRoot, + smDeviceHandle_t *smDeviceHandle, + smIntrEventType_t eventType, + bit32 eventStatus, + void *parm + ) +{ + tdsaRoot_t *tdsaRoot; + tdsaContext_t *tdsaAllShared; + tiRoot_t *tiRoot; + tdIORequestBody_t *tdIORequestBody; + smIORequest_t *SMcurrentTaskTag; + tiIORequest_t *currentTaskTag; + tdsaDeviceData_t *oneDeviceData; + void *osMemHandle; + tdsaPortContext_t *onePortContext; + tiPortalContext_t *tiportalContext; + tiDeviceHandle_t *tiDeviceHandle; + + /* be sure to free using tdIORequestBody->->IOType.InitiatorTMIO.osMemHandle but how??? + parm = pSatDevData->satTmTaskTag (currentTaskTag in tiINITaskManagement) + In this case, parm is smIORequest_t + */ + + TI_DBG2(("tdsmEventCB: start\n")); + + tdsaRoot = (tdsaRoot_t *)smRoot->tdData; + tdsaAllShared = &(tdsaRoot->tdsaAllShared); + tiRoot = tdsaAllShared->agRootOsDataForInt.tiRoot; + + + if (eventType == smIntrEventTypeLocalAbort) + { + oneDeviceData = (tdsaDeviceData_t *)smDeviceHandle->tdData; + if (oneDeviceData == agNULL) + { + TI_DBG1(("tdsmEventCB: oneDeviceData is NULL\n")); + return; + } + else + { + tiDeviceHandle = &(oneDeviceData->tiDeviceHandle); + if (oneDeviceData->OSAbortAll == agTRUE) + { + oneDeviceData->OSAbortAll = agFALSE; + ostiInitiatorEvent( tiRoot, + agNULL, + tiDeviceHandle, + tiIntrEventTypeLocalAbort, + tiAbortOK, + agNULL); + } + } + } + else + { + + SMcurrentTaskTag = (smIORequest_t *)parm; + if (SMcurrentTaskTag == agNULL) + { + TI_DBG1(("tdsmEventCB: SMcurrentTaskTag is NULL!!!\n")); + return; + } + + tdIORequestBody = (tdIORequestBody_t *)SMcurrentTaskTag->tdData; + if (tdIORequestBody == agNULL) + { + TI_DBG1(("tdsmEventCB: tdIORequestBody is NULL!!!\n")); + return; + } + + osMemHandle = tdIORequestBody->IOType.InitiatorTMIO.osMemHandle; + currentTaskTag = tdIORequestBody->IOType.InitiatorTMIO.CurrentTaskTag; + + + oneDeviceData = (tdsaDeviceData_t *)smDeviceHandle->tdData; + if (oneDeviceData == agNULL) + { + TI_DBG1(("tdsmEventCB: oneDeviceData is NULL!!!\n")); + return; + } + + tiDeviceHandle = &(oneDeviceData->tiDeviceHandle); + onePortContext = oneDeviceData->tdPortContext; + if (onePortContext == agNULL) + { + TI_DBG1(("tdsmEventCB: onePortContext is NULL!!!\n")); + return; + } + tiportalContext = onePortContext->tiPortalContext; + + /* free tdIORequestBody */ + ostiFreeMemory( + tiRoot, + osMemHandle, + sizeof(tdIORequestBody_t) + ); + + + TI_DBG2(("tdsmEventCB: calling ostiInitiatorEvent\n")); + ostiInitiatorEvent( + tiRoot, + tiportalContext, + tiDeviceHandle, + eventType, + eventStatus, + (void *)currentTaskTag + ); + + + /* completion of taskmanagement + osGLOBAL void ostiInitiatorEvent ( + tiRoot_t *tiRoot, + tiPortalContext_t *portalContext, + tiDeviceHandle_t *tiDeviceHandle, + tiIntrEventType_t eventType, + bit32 eventStatus, + void *parm + ); + + + ostiFreeAlloc() + */ + + } + + return; +} + + +FORCEINLINE void +tdsmSingleThreadedEnter( + smRoot_t *smRoot, + bit32 syncLockId + ) +{ + tdsaRoot_t *tdsaRoot; + tdsaContext_t *tdsaAllShared; + tiRoot_t *tiRoot; + bit32 offset = 0; + + TI_DBG7(("tdsmSingleThreadedEnter: start\n")); + + tdsaRoot = (tdsaRoot_t *)smRoot->tdData; + if (tdsaRoot == agNULL) + { + TI_DBG1(("tdsmSingleThreadedEnter: tdsaRoot is NULL\n")); + return; + } + + tdsaAllShared = &(tdsaRoot->tdsaAllShared); + if (tdsaAllShared == agNULL) + { + TI_DBG1(("tdsmSingleThreadedEnter: tdsaAllShared is NULL\n")); + return; + } + + tiRoot = tdsaAllShared->agRootOsDataForInt.tiRoot; + if (tiRoot == agNULL) + { + TI_DBG1(("tdsmSingleThreadedEnter: tiRoot is NULL\n")); + return; + } + + offset = tdsaAllShared->MaxNumLLLocks + tdsaAllShared->MaxNumOSLocks + TD_MAX_LOCKS + tdsaAllShared->MaxNumDMLocks; + + ostiSingleThreadedEnter(tiRoot, syncLockId + offset); + + return; +} + +FORCEINLINE void +tdsmSingleThreadedLeave( + smRoot_t *smRoot, + bit32 syncLockId + ) +{ + tdsaRoot_t *tdsaRoot; + tdsaContext_t *tdsaAllShared; + tiRoot_t *tiRoot; + bit32 offset = 0; + + TI_DBG7(("tdsmSingleThreadedLeave: start\n")); + + tdsaRoot = (tdsaRoot_t *)smRoot->tdData; + if (tdsaRoot == agNULL) + { + TI_DBG1(("tdsmSingleThreadedLeave: tdsaRoot is NULL\n")); + return; + } + + tdsaAllShared = &(tdsaRoot->tdsaAllShared); + if (tdsaAllShared == agNULL) + { + TI_DBG1(("tdsmSingleThreadedLeave: tdsaAllShared is NULL\n")); + return; + } + + tiRoot = tdsaAllShared->agRootOsDataForInt.tiRoot; + if (tiRoot == agNULL) + { + TI_DBG1(("tdsmSingleThreadedLeave: tiRoot is NULL\n")); + return; + } + offset = tdsaAllShared->MaxNumLLLocks + tdsaAllShared->MaxNumOSLocks + TD_MAX_LOCKS + tdsaAllShared->MaxNumDMLocks; + + ostiSingleThreadedLeave(tiRoot, syncLockId + offset); + + return; +} + +osGLOBAL FORCEINLINE bit8 +tdsmBitScanForward( + smRoot_t *smRoot, + bit32 *Index, + bit32 Mask + ) +{ + return ostiBitScanForward(agNULL, Index, Mask); +} + +#ifdef LINUX_VERSION_CODE + +osGLOBAL FORCEINLINE sbit32 +tdsmInterlockedIncrement( + smRoot_t *smRoot, + sbit32 volatile *Addend + ) +{ + return ostiAtomicIncrement(agNULL, Addend); +} + +osGLOBAL FORCEINLINE sbit32 +tdsmInterlockedDecrement( + smRoot_t *smRoot, + sbit32 volatile *Addend + ) +{ + return ostiAtomicDecrement(agNULL, Addend); +} + + + +osGLOBAL FORCEINLINE sbit32 +tdsmAtomicBitClear( + smRoot_t *smRoot, + sbit32 volatile *Destination, + sbit32 Value + ) +{ + return ostiAtomicBitClear(agNULL, Destination, Value); +} + +osGLOBAL FORCEINLINE sbit32 +tdsmAtomicBitSet( + smRoot_t *smRoot, + sbit32 volatile *Destination, + sbit32 Value + ) +{ + return ostiAtomicBitSet(agNULL, Destination, Value); +} + +osGLOBAL FORCEINLINE sbit32 +tdsmAtomicExchange( + smRoot_t *smRoot, + sbit32 volatile *Target, + sbit32 Value + ) +{ + return ostiAtomicExchange(agNULL, Target, Value); +} + +#else + +osGLOBAL FORCEINLINE sbit32 +tdsmInterlockedIncrement( + smRoot_t *smRoot, + sbit32 volatile *Addend + ) +{ + return ostiInterlockedIncrement(agNULL, Addend); +} + +osGLOBAL FORCEINLINE sbit32 +tdsmInterlockedDecrement( + smRoot_t *smRoot, + sbit32 volatile *Addend + ) +{ + return ostiInterlockedDecrement(agNULL, Addend); +} + + + +osGLOBAL FORCEINLINE sbit32 +tdsmInterlockedAnd( + smRoot_t *smRoot, + sbit32 volatile *Destination, + sbit32 Value + ) +{ + + return ostiInterlockedAnd(agNULL, Destination, Value); +} + +osGLOBAL FORCEINLINE sbit32 +tdsmInterlockedOr( + smRoot_t *smRoot, + sbit32 volatile *Destination, + sbit32 Value + ) +{ + return ostiInterlockedOr(agNULL, Destination, Value); +} + +osGLOBAL FORCEINLINE sbit32 +tdsmInterlockedExchange( + smRoot_t *smRoot, + sbit32 volatile *Target, + sbit32 Value + ) +{ + return ostiInterlockedExchange(agNULL, Target, Value); +} + +#endif /*LINUX_VERSION_CODE*/ + +osGLOBAL bit32 +tdsmAllocMemory( + smRoot_t *smRoot, + void **osMemHandle, + void ** virtPtr, + bit32 * physAddrUpper, + bit32 * physAddrLower, + bit32 alignment, + bit32 allocLength, + smBOOLEAN isCacheable + ) +{ + tdsaRoot_t *tdsaRoot; + tdsaContext_t *tdsaAllShared; + tiRoot_t *tiRoot; + bit32 status; + + TI_DBG5(("tdsmAllocMemory: start\n")); + + tdsaRoot = (tdsaRoot_t *)smRoot->tdData; + if (tdsaRoot == agNULL) + { + TI_DBG1(("tdsmAllocMemory: tdsaRoot is NULL\n")); + return SM_RC_FAILURE; + } + + tdsaAllShared = &(tdsaRoot->tdsaAllShared); + if (tdsaAllShared == agNULL) + { + TI_DBG1(("tdsmAllocMemory: tdsaAllShared is NULL\n")); + return SM_RC_FAILURE; + } + + tiRoot = tdsaAllShared->agRootOsDataForInt.tiRoot; + if (tiRoot == agNULL) + { + TI_DBG1(("tdsmAllocMemory: tiRoot is NULL\n")); + return SM_RC_FAILURE; + } + + status = ostiAllocMemory(tiRoot, + osMemHandle, + virtPtr, + physAddrUpper, + physAddrLower, + alignment, + allocLength, + isCacheable); + + if (status == tiSuccess) + { + return SM_RC_SUCCESS; + } + else + { + return SM_RC_FAILURE; + } + +} + +osGLOBAL bit32 +tdsmFreeMemory( + smRoot_t *smRoot, + void *osDMAHandle, + bit32 allocLength + ) +{ + tdsaRoot_t *tdsaRoot; + tdsaContext_t *tdsaAllShared; + tiRoot_t *tiRoot; + bit32 status; + + TI_DBG5(("tdsmFreeMemory: start\n")); + + tdsaRoot = (tdsaRoot_t *)smRoot->tdData; + if (tdsaRoot == agNULL) + { + TI_DBG1(("tdsmFreeMemory: tdsaRoot is NULL\n")); + return SM_RC_FAILURE; + } + + tdsaAllShared = &(tdsaRoot->tdsaAllShared); + if (tdsaAllShared == agNULL) + { + TI_DBG1(("tdsmFreeMemory: tdsaAllShared is NULL\n")); + return SM_RC_FAILURE; + } + + tiRoot = tdsaAllShared->agRootOsDataForInt.tiRoot; + if (tiRoot == agNULL) + { + TI_DBG1(("tdsmFreeMemory: tiRoot is NULL\n")); + return SM_RC_FAILURE; + } + + status = ostiFreeMemory(tiRoot, + osDMAHandle, + allocLength); + + if (status == tiSuccess) + { + return SM_RC_SUCCESS; + } + else + { + return SM_RC_FAILURE; + } +} + +FORCEINLINE bit32 +tdsmRotateQnumber(smRoot_t *smRoot, + smDeviceHandle_t *smDeviceHandle + ) +{ + tdsaRoot_t *tdsaRoot; + tdsaContext_t *tdsaAllShared; + tiRoot_t *tiRoot; + tdsaDeviceData_t *oneDeviceData; + bit32 ret = 0; + + tdsaRoot = (tdsaRoot_t *)smRoot->tdData; + tdsaAllShared = &(tdsaRoot->tdsaAllShared); + tiRoot = tdsaAllShared->agRootOsDataForInt.tiRoot; + + + TI_DBG6(("tdsmRotateQnumber: start\n")); + + if (smDeviceHandle == agNULL) + { + TI_DBG1(("tdsmRotateQnumber: smDeviceHandle is NULL !!!!\n")); + return ret; + } + oneDeviceData = (tdsaDeviceData_t *)smDeviceHandle->tdData; + if (oneDeviceData == agNULL) + { + TI_DBG1(("tdsmRotateQnumber: oneDeviceData is NULL !!!!\n")); + return ret; + } + return tdsaRotateQnumber(tiRoot, oneDeviceData); +} + +osGLOBAL bit32 +tdsmSetDeviceQueueDepth(smRoot_t *smRoot, + smIORequest_t *smIORequest, + bit32 QueueDepth + ) +{ + tdsaRoot_t *tdsaRoot = agNULL; + tdsaContext_t *tdsaAllShared = agNULL; + tiRoot_t *tiRoot = agNULL; + tdIORequestBody_t *tdIORequestBody = (tdIORequestBody_t *)smIORequest->tdData; + tiIORequest_t *tiIORequest = tdIORequestBody->tiIORequest; + + + TI_DBG5(("tdsmSetDeviceQueueDepth: start\n")); + + tdsaRoot = (tdsaRoot_t *)smRoot->tdData; + if (tdsaRoot == agNULL) + { + TI_DBG1(("tdsmSetDeviceQueueDepth: tdsaRoot is NULL\n")); + return SM_RC_FAILURE; + } + + tdsaAllShared = &(tdsaRoot->tdsaAllShared); + if (tdsaAllShared == agNULL) + { + TI_DBG1(("tdsmSetDeviceQueueDepth: tdsaAllShared is NULL\n")); + return SM_RC_FAILURE; + } + + tiRoot = tdsaAllShared->agRootOsDataForInt.tiRoot; + if (tiRoot == agNULL) + { + TI_DBG1(("tdsmFreeMemory: tiRoot is NULL\n")); + return SM_RC_FAILURE; + } + + return ostiSetDeviceQueueDepth(tiRoot, tiIORequest, QueueDepth); +} + +osGLOBAL bit32 tdsmGetTransportParam( + smRoot_t *smRoot, + char *key, + char *subkey1, + char *subkey2, + char *subkey3, + char *subkey4, + char *subkey5, + char *valueName, + char *buffer, + bit32 bufferLen, + bit32 *lenReceived + ) +{ + bit32 ret = tiError; + + TI_DBG7(("tdsmGetTransportParam: start\n")); + ret = ostiGetTransportParam(agNULL, + key, + subkey1, + subkey2, + subkey3, + subkey4, + subkey5, + valueName, + buffer, + bufferLen, + lenReceived + ); + return ret; +} +#endif /* FDS_SM */ + diff --git a/sys/dev/pms/RefTisa/tisa/sassata/common/tdtimers.c b/sys/dev/pms/RefTisa/tisa/sassata/common/tdtimers.c new file mode 100644 index 000000000000..86d1fec61a6d --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/common/tdtimers.c @@ -0,0 +1,302 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +/*******************************************************************************/ +/** \file + * + * This file contains timer functions in TD layer + * + */ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#ifdef FDS_SM +#include +#include +#include +#endif + +#ifdef FDS_DM +#include +#include +#include +#endif + +#include +#include +#include + +#ifdef INITIATOR_DRIVER +#include +#include +#include +#endif + +#ifdef TARGET_DRIVER +#include +#include +#include +#endif + +#include +#include + +/***************************************************************************** +*! \brief tiCOMTimerTick +* +* Purpose: This function is called to every usecsPerTick interval +* +* \param tiRoot: Pointer to initiator specific root data structure for this +* instance of the driver. +* +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +tiCOMTimerTick ( + tiRoot_t * tiRoot + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *)(tiRoot->tdData); + agsaRoot_t *agRoot = &tdsaRoot->tdsaAllShared.agRootNonInt; +#ifdef FDS_DM + dmRoot_t *dmRoot = &tdsaRoot->tdsaAllShared.dmRoot; +#endif + +#ifdef FDS_SM_NOT_YET + smRoot_t *smRoot = &tdsaRoot->tdsaAllShared.smRoot; +#endif + /* checking the lower layer */ + saTimerTick(agRoot); + +#ifdef FDS_DM + /* checking the DM */ + dmTimerTick(dmRoot); +#endif + +#ifdef FDS_SM_NOT_YET + /* checking the SM */ + smTimerTick(smRoot); +#endif + + /* + timers for discovery + checking tdsaRoot_t timers + */ + + tdsaProcessTimers(tiRoot); + +} + +/***************************************************************************** +*! \brief tdsaInitTimerRequest +* +* Purpose: This function initiallizes timer request +* +* \param tiRoot: Pointer to initiator specific root data structure +* for this instance of the driver. +* \param timerrequest Pointer to timer request +* +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +tdsaInitTimerRequest( + tiRoot_t *tiRoot, + tdsaTimerRequest_t *timerRequest + ) +{ + timerRequest->timeout = 0; + timerRequest->timerCBFunc = agNULL; + timerRequest->timerData1 = agNULL; + timerRequest->timerData2 = agNULL; + timerRequest->timerData3 = agNULL; + TDLIST_INIT_ELEMENT((&timerRequest->timerLink)); +} + +/***************************************************************************** +*! \brief tdsaSetTimerRequest +* +* Purpose: This function sets timer request +* +* \param tiRoot: Pointer to initiator specific root data structure +* for this instance of the driver. +* \param timerrequest Pointer to timer request +* \param timeout timeout value +* \param CBFunc timer CB function +* \param timerData1 Data associated with the timer +* \param timerData2 Data associated with the timer +* \param timerData3 Data associated with the timer +* +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +tdsaSetTimerRequest( + tiRoot_t *tiRoot, + tdsaTimerRequest_t *timerRequest, + bit32 timeout, + tdsaTimerCBFunc_t CBFunc, + void *timerData1, + void *timerData2, + void *timerData3 + ) +{ + timerRequest->timeout = timeout; + timerRequest->timerCBFunc = CBFunc; + timerRequest->timerData1 = timerData1; + timerRequest->timerData2 = timerData2; + timerRequest->timerData3 = timerData3; +} + +/***************************************************************************** +*! \brief tdsaAddTimer +* +* Purpose: This function adds timer request to timer list +* +* \param tiRoot: Pointer to initiator specific root data structure +* for this instance of the driver. +* \param timerListHdr Pointer to the timer list +* \param timerrequest Pointer to timer request +* +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +tdsaAddTimer( + tiRoot_t *tiRoot, + tdList_t *timerListHdr, + tdsaTimerRequest_t *timerRequest + ) +{ + tdsaSingleThreadedEnter(tiRoot, TD_TIMER_LOCK); + TDLIST_ENQUEUE_AT_TAIL(&(timerRequest->timerLink), timerListHdr); + timerRequest->timerRunning = agTRUE; + tdsaSingleThreadedLeave(tiRoot, TD_TIMER_LOCK); +} + +/***************************************************************************** +*! \brief tdsaKillTimer +* +* Purpose: This function kills timer request. +* +* \param tiRoot: Pointer to initiator specific root data structure +* for this instance of the driver. +* \param timerrequest Pointer to timer request +* +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +tdsaKillTimer( + tiRoot_t *tiRoot, + tdsaTimerRequest_t *timerRequest + ) +{ + tdsaSingleThreadedEnter(tiRoot, TD_TIMER_LOCK); + timerRequest->timerRunning = agFALSE; + TDLIST_DEQUEUE_THIS(&(timerRequest->timerLink)); + tdsaSingleThreadedLeave(tiRoot, TD_TIMER_LOCK); +} + +/***************************************************************************** +*! \brief tdsaProcessTimers +* +* Purpose: This function processes timer request. +* +* \param tiRoot: Pointer to initiator specific root data structure +* for this instance of the driver. +* +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +tdsaProcessTimers( + tiRoot_t *tiRoot + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *)(tiRoot->tdData); + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdsaTimerRequest_t *timerRequest_to_process = agNULL; + tdList_t *timerlist_to_process, *nexttimerlist = agNULL; + + + timerlist_to_process = &tdsaAllShared->timerlist; + + timerlist_to_process = timerlist_to_process->flink; + + while ((timerlist_to_process != agNULL) && (timerlist_to_process != &tdsaAllShared->timerlist)) + { + nexttimerlist = timerlist_to_process->flink; + + tdsaSingleThreadedEnter(tiRoot, TD_TIMER_LOCK); + timerRequest_to_process = TDLIST_OBJECT_BASE(tdsaTimerRequest_t, timerLink, timerlist_to_process); + tdsaSingleThreadedLeave(tiRoot, TD_TIMER_LOCK); + + if (timerRequest_to_process == agNULL) + { + TI_DBG1(("tdsaProcessTimers: timerRequest_to_process is NULL! Error!!!\n")); + return; + } + + timerRequest_to_process->timeout--; + + if (timerRequest_to_process->timeout == 0) + { + tdsaSingleThreadedEnter(tiRoot, TD_TIMER_LOCK); + if (timerRequest_to_process->timerRunning == agTRUE) + { + timerRequest_to_process->timerRunning = agFALSE; + TDLIST_DEQUEUE_THIS(timerlist_to_process); + } + tdsaSingleThreadedLeave(tiRoot, TD_TIMER_LOCK); + /* calling call back function */ + (timerRequest_to_process->timerCBFunc)(tiRoot, + timerRequest_to_process->timerData1, + timerRequest_to_process->timerData2, + timerRequest_to_process->timerData3 + ); + } + timerlist_to_process = nexttimerlist; + } + return; +} + diff --git a/sys/dev/pms/RefTisa/tisa/sassata/common/tdutil.h b/sys/dev/pms/RefTisa/tisa/sassata/common/tdutil.h new file mode 100644 index 000000000000..6cba0fae6b8a --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/common/tdutil.h @@ -0,0 +1,105 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/*******************************************************************************/ +/** \file + * + * The file defines utilities for SAS/SATA TD layer + * + */ + +#ifndef __TDUTIL_H__ +#define __TDUTIL_H__ + +#include +#include +#include +#include +#include + + +#define HEXDIGIT2CHAR(x) (((x) < 10) ? ('0' + (x)) : ('A' + ((x) - 10))) +/***************************************************************************** +*! \brief tdDecimal2String +* +* Purpose: This function converts a given number into a decimal string. +* +* \param s: string to be generated +* \param num: number to be converted +* +* \return None +* +* \note - string s should be large enough to store decimal string of +* num and a '\0' character +* +*****************************************************************************/ +void +tdDecimal2String( + char *s, + bit32 num + ); + +void +tdHexToString ( + char *String, + bit32 Value1, + bit32 Value2, + bit32 Strlength + ); + +bit8 tdStr2Bit8 (char *buffer); + +bit32 tdStr2ALPA (char *buffer); + +void tdStr2WWN (char *buffer, bit8 * NodeName); + +void tdWWN2Str (char *buffer, bit8 * NodeName); + +/***************************************************************************** +*! \brief tdNextPowerOf2 +* +* Purpose: This function is called to calculate the next power of 2 +* value of given value. +* +* +* \param Value: The value for which next power of 2 is requested +* +* \return: The next power of 2 value of given Value +* +*****************************************************************************/ +bit32 +tdNextPowerOf2 ( + bit32 Value + ); + +osGLOBAL agBOOLEAN +tdListElementOnList( + tdList_t *toFindHdr, + tdList_t *listHdr + ); + + +#endif /* __TDUTIL_H__ */ + + + diff --git a/sys/dev/pms/RefTisa/tisa/sassata/common/wcs.h b/sys/dev/pms/RefTisa/tisa/sassata/common/wcs.h new file mode 100644 index 000000000000..167b1a0688ff --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/common/wcs.h @@ -0,0 +1,8305 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/*******************************************************************************/ +/** \file + * + * This file contains wcs code + * + */ + +/* wcsImage */ +bit32 oldwcsImage[] = +{ + 0x011, // 00000 = 0 - PHY_RESET_START + 0x0ca, // 0x001 = 1 - JUMP_IF_PHY_READY + 0x009, // 0x002 = 2 - + 0x0ba, // 0x003 = 3 - JUMP_IF_HARD_RESET_PRIMITIVE + 0x010, // 0x004 = 4 - + 0x0bb, // 0x005 = 5 - JUMP_IF_IDENTIFY_FRAME_RECEIVED + 0x01e, // 0x006 = 6 - + 0x0ff, // 0x007 = 7 - JUMP + 0x001, // 0x008 = 8 - + 0x010, // 0x009 = 9 - SEND_ID_FRAME + 0x0ba, // 0x00a = 10 - JUMP_IF_HARD_RESET_PRIMITIVE + 0x010, // 0x00b = 11 - + 0x0bb, // 0x00c = 12 - JUMP_IF_IDENTIFY_FRAME_RECEIVED + 0x023, // 0x00d = 13 - + 0x0ff, // 0x00e = 14 - JUMP + 0x00a, // 0x00f = 15 - + 0x033, // 0x010 = 16 - SOFT_RESET + 0x011, // 0x011 = 17 - PHY_RESET_START + 0x0ca, // 0x012 = 18 - JUMP_IF_PHY_READY + 0x016, // 0x013 = 19 - + 0x0bb, // 0x014 = 20 - JUMP_IF_IDENTIFY_FRAME_RECEIVED + 0x01b, // 0x015 = 21 - + 0x010, // 0x016 = 22 - SEND_ID_FRAME + 0x0bb, // 0x017 = 23 - JUMP_IF_IDENTIFY_FRAME_RECEIVED + 0x023, // 0x018 = 24 - + 0x0ff, // 0x019 = 25 - JUMP + 0x017, // 0x01a = 26 - + 0x010, // 0x01b = 27 - SEND_ID_FRAME + 0x0ff, // 0x01c = 28 - JUMP + 0x023, // 0x01d = 29 - + 0x0ca, // 0x01e = 30 - JUMP_IF_PHY_READY + 0x022, // 0x01f = 31 - + 0x0ff, // 0x020 = 32 - JUMP + 0x01e, // 0x021 = 33 - + 0x010, // 0x022 = 34 - SEND_ID_FRAME + 0x000, // 0x023 = 35 - NO_OP + 0x000, // 0x024 = 36 - NO_OP + 0x000, // 0x025 = 37 - NO_OP + 0x000, // 0x026 = 38 - NO_OP + 0x000, // 0x027 = 39 - NO_OP + 0x000, // 0x028 = 40 - NO_OP + 0x0ff, // 0x029 = 41 - JUMP + 0x0ff, // 0x02a = 42 - + 0x01b, // 0x02b = 43 - START_IT_NEXUS_LOSS_TIMER_SFO + 0x017, // 0x02c = 44 - PATHWAY_BLOCKED_CNT_SFO_RESET + 0x013, // 0x02d = 45 - START_ARB_WAIT_TIMER_SFO + 0x001, // 0x02e = 46 - OPEN_REQUEST_SFO + 0x000, // 0x02f = 47 - NO_OP + 0x000, // 0x030 = 48 - NO_OP + 0x000, // 0x031 = 49 - NO_OP + 0x000, // 0x032 = 50 - NO_OP + 0x000, // 0x033 = 51 - NO_OP + 0x091, // 0x034 = 52 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_ACCEPT + 0x056, // 0x035 = 53 - + 0x097, // 0x036 = 54 - JUMP_IF_OPEN_STATUS_EQUAL_RATE_NOT_SUPPORTED + 0x059, // 0x037 = 55 - + 0x09b, // 0x038 = 56 - JUMP_IF_OPEN_STATUS_EQUAL_PROTOCOL_NOT_SUPPORTED + 0x05c, // 0x039 = 57 - + 0x09d, // 0x03a = 58 - JUMP_IF_OPEN_STATUS_EQUAL_WRONG_DESTINATION + 0x05f, // 0x03b = 59 - + 0x096, // 0x03c = 60 - JUMP_IF_OPEN_STATUS_EQUAL_BREAK_RECEIVED + 0x062, // 0x03d = 61 - + 0x095, // 0x03e = 62 - JUMP_IF_OPEN_STATUS_EQUAL_BAD_DESTINATION + 0x065, // 0x03f = 63 - + 0x0a1, // 0x040 = 64 - JUMP_IF_IT_NEXUS_LOSS_TIMEOUT_SFO + 0x068, // 0x041 = 65 - + 0x09c, // 0x042 = 66 - JUMP_IF_OPEN_STATUS_EQUAL_STP_RESOURCE_BUSY + 0x02b, // 0x043 = 67 - + 0x098, // 0x044 = 68 - JUMP_IF_OPEN_STATUS_EQUAL_NO_DESTINATION + 0x0ff, // 0x045 = 69 - + 0x099, // 0x046 = 70 - JUMP_IF_OPEN_STATUS_EQUAL_PATHWAY_BLOCKED + 0x06b, // 0x047 = 71 - + 0x09a, // 0x048 = 72 - JUMP_IF_OPEN_STATUS_EQUAL_RETRY + 0x02e, // 0x049 = 73 - + 0x094, // 0x04a = 74 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_TIMEOUT + 0x02e, // 0x04b = 75 - + 0x0a7, // 0x04c = 76 - JUMP_IF_CONNECTION_OPEN_SLAVE_FLAG_SET + 0x114, // 0x04d = 77 - + 0x092, // 0x04e = 78 - JUMP_IF_OPEN_STATUS_EQUAL_OCSM_BUSY + 0x02e, // 0x04f = 79 - + 0x0ca, // 0x050 = 80 - JUMP_IF_PHY_READY + 0x034, // 0x051 = 81 - + 0x031, // 0x052 = 82 - SET_OPEN_STATUS_PHY_NOT_RDY_SFO + 0x033, // 0x053 = 83 - SOFT_RESET + 0x0ff, // 0x054 = 84 - JUMP + 0x001, // 0x055 = 85 - + 0x021, // 0x056 = 86 - SET_OPEN_STATUS_NORMAL_SFO + 0x0ff, // 0x057 = 87 - JUMP + 0x06e, // 0x058 = 88 - + 0x025, // 0x059 = 89 - SET_OPEN_STATUS_BAD_RATE_SFO + 0x0ff, // 0x05a = 90 - JUMP + 0x0ff, // 0x05b = 91 - + 0x026, // 0x05c = 92 - SET_OPEN_STATUS_BAD_PROTOCOL_SFO + 0x0ff, // 0x05d = 93 - JUMP + 0x0ff, // 0x05e = 94 - + 0x028, // 0x05f = 95 - SET_OPEN_STATUS_WRONG_DEST_SFO + 0x0ff, // 0x060 = 96 - JUMP + 0x0ff, // 0x061 = 97 - + 0x024, // 0x062 = 98 - SET_OPEN_STATUS_BREAK_SFO + 0x0ff, // 0x063 = 99 - JUMP + 0x0ff, // 0x064 = 100 - + 0x023, // 0x065 = 101 - SET_OPEN_STATUS_BAD_DEST_SFO + 0x0ff, // 0x066 = 102 - JUMP + 0x0ff, // 0x067 = 103 - + 0x022, // 0x068 = 104 - SET_OPEN_STATUS_IT_NEXUS_LOSS_SFO + 0x0ff, // 0x069 = 105 - JUMP + 0x0ff, // 0x06a = 106 - + 0x019, // 0x06b = 107 - PATHWAY_BLOCKED_CNT_SFO_INC + 0x0ff, // 0x06c = 108 - JUMP + 0x02e, // 0x06d = 109 - + 0x000, // 0x06e = 110 - NO_OP + 0x0aa, // 0x06f = 111 - JUMP_IF_SFO_TRANSMISSION_STATUS_EQUAL_GOOD + 0x08e, // 0x070 = 112 - + 0x0ab, // 0x071 = 113 - JUMP_IF_SFO_TRANSMISSION_STATUS_EQUAL_NAK + 0x080, // 0x072 = 114 - + 0x0ac, // 0x073 = 115 - JUMP_IF_SFO_TRANSMISSION_STATUS_EQUAL_ACK_NAK_TIMEOUT + 0x083, // 0x074 = 116 - + 0x0ad, // 0x075 = 117 - JUMP_IF_SFO_TRANSMISSION_STATUS_EQUAL_BREAK + 0x083, // 0x076 = 118 - + 0x0af, // 0x077 = 119 - JUMP_IF_SFO_TRANSMISSION_STATUS_EQUAL_CREDIT_TIMEOUT + 0x087, // 0x078 = 120 - + 0x0ae, // 0x079 = 121 - JUMP_IF_SFO_TRANSMISSION_STATUS_EQUAL_UNEXPECTED_CLOSE + 0x080, // 0x07a = 122 - + 0x0ca, // 0x07b = 123 - JUMP_IF_PHY_READY + 0x06f, // 0x07c = 124 - + 0x033, // 0x07d = 125 - SOFT_RESET + 0x0ff, // 0x07e = 126 - JUMP + 0x001, // 0x07f = 127 - + 0x006, // 0x080 = 128 - CLOSE_NORMAL + 0x0ff, // 0x081 = 129 - JUMP + 0x08b, // 0x082 = 130 - + 0x009, // 0x083 = 131 - CLOSE_BREAK + 0x034, // 0x084 = 132 - ADVANCE_SFO + 0x0ff, // 0x085 = 133 - JUMP + 0x0ff, // 0x086 = 134 - + 0x009, // 0x087 = 135 - CLOSE_BREAK + 0x034, // 0x088 = 136 - ADVANCE_SFO + 0x0ff, // 0x089 = 137 - JUMP + 0x0ff, // 0x08a = 138 - + 0x034, // 0x08b = 139 - ADVANCE_SFO + 0x0ff, // 0x08c = 140 - JUMP + 0x12d, // 0x08d = 141 - + 0x034, // 0x08e = 142 - ADVANCE_SFO + 0x0ff, // 0x08f = 143 - JUMP + 0x0ff, // 0x090 = 144 - + 0x01c, // 0x091 = 145 - START_IT_NEXUS_LOSS_TIMER_DOC + 0x018, // 0x092 = 146 - PATHWAY_BLOCKED_CNT_DOC_RESET + 0x014, // 0x093 = 147 - START_ARB_WAIT_TIMER_DOC + 0x002, // 0x094 = 148 - OPEN_REQUEST_DOC + 0x000, // 0x095 = 149 - NO_OP + 0x000, // 0x096 = 150 - NO_OP + 0x000, // 0x097 = 151 - NO_OP + 0x000, // 0x098 = 152 - NO_OP + 0x000, // 0x099 = 153 - NO_OP + 0x091, // 0x09a = 154 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_ACCEPT + 0x0bc, // 0x09b = 155 - + 0x097, // 0x09c = 156 - JUMP_IF_OPEN_STATUS_EQUAL_RATE_NOT_SUPPORTED + 0x0bf, // 0x09d = 157 - + 0x09b, // 0x09e = 158 - JUMP_IF_OPEN_STATUS_EQUAL_PROTOCOL_NOT_SUPPORTED + 0x0c2, // 0x09f = 159 - + 0x09d, // 0x0a0 = 160 - JUMP_IF_OPEN_STATUS_EQUAL_WRONG_DESTINATION + 0x0c5, // 0x0a1 = 161 - + 0x096, // 0x0a2 = 162 - JUMP_IF_OPEN_STATUS_EQUAL_BREAK_RECEIVED + 0x0c8, // 0x0a3 = 163 - + 0x095, // 0x0a4 = 164 - JUMP_IF_OPEN_STATUS_EQUAL_BAD_DESTINATION + 0x0cb, // 0x0a5 = 165 - + 0x0a2, // 0x0a6 = 166 - JUMP_IF_IT_NEXUS_LOSS_TIMEOUT_DOC + 0x0ce, // 0x0a7 = 167 - + 0x09c, // 0x0a8 = 168 - JUMP_IF_OPEN_STATUS_EQUAL_STP_RESOURCE_BUSY + 0x091, // 0x0a9 = 169 - + 0x098, // 0x0aa = 170 - JUMP_IF_OPEN_STATUS_EQUAL_NO_DESTINATION + 0x0ff, // 0x0ab = 171 - + 0x099, // 0x0ac = 172 - JUMP_IF_OPEN_STATUS_EQUAL_PATHWAY_BLOCKED + 0x0d1, // 0x0ad = 173 - + 0x09a, // 0x0ae = 174 - JUMP_IF_OPEN_STATUS_EQUAL_RETRY + 0x094, // 0x0af = 175 - + 0x094, // 0x0b0 = 176 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_TIMEOUT + 0x094, // 0x0b1 = 177 - + 0x0a7, // 0x0b2 = 178 - JUMP_IF_CONNECTION_OPEN_SLAVE_FLAG_SET + 0x122, // 0x0b3 = 179 - + 0x092, // 0x0b4 = 180 - JUMP_IF_OPEN_STATUS_EQUAL_OCSM_BUSY + 0x094, // 0x0b5 = 181 - + 0x0ca, // 0x0b6 = 182 - JUMP_IF_PHY_READY + 0x09a, // 0x0b7 = 183 - + 0x032, // 0x0b8 = 184 - SET_OPEN_STATUS_PHY_NOT_RDY_DOC + 0x033, // 0x0b9 = 185 - SOFT_RESET + 0x0ff, // 0x0ba = 186 - JUMP + 0x001, // 0x0bb = 187 - + 0x029, // 0x0bc = 188 - SET_OPEN_STATUS_NORMAL_DOC + 0x0ff, // 0x0bd = 189 - JUMP + 0x0d4, // 0x0be = 190 - + 0x02d, // 0x0bf = 191 - SET_OPEN_STATUS_BAD_RATE_DOC + 0x0ff, // 0x0c0 = 192 - JUMP + 0x0ff, // 0x0c1 = 193 - + 0x02e, // 0x0c2 = 194 - SET_OPEN_STATUS_BAD_PROTOCOL_DOC + 0x0ff, // 0x0c3 = 195 - JUMP + 0x0ff, // 0x0c4 = 196 - + 0x030, // 0x0c5 = 197 - SET_OPEN_STATUS_WRONG_DEST_DOC + 0x0ff, // 0x0c6 = 198 - JUMP + 0x0ff, // 0x0c7 = 199 - + 0x02c, // 0x0c8 = 200 - SET_OPEN_STATUS_BREAK_DOC + 0x0ff, // 0x0c9 = 201 - JUMP + 0x0ff, // 0x0ca = 202 - + 0x02b, // 0x0cb = 203 - SET_OPEN_STATUS_BAD_DEST_DOC + 0x0ff, // 0x0cc = 204 - JUMP + 0x0ff, // 0x0cd = 205 - + 0x02a, // 0x0ce = 206 - SET_OPEN_STATUS_IT_NEXUS_LOSS_DOC + 0x0ff, // 0x0cf = 207 - JUMP + 0x0ff, // 0x0d0 = 208 - + 0x01a, // 0x0d1 = 209 - PATHWAY_BLOCKED_CNT_DOC_INC + 0x0ff, // 0x0d2 = 210 - JUMP + 0x094, // 0x0d3 = 211 - + 0x000, // 0x0d4 = 212 - NO_OP + 0x0b1, // 0x0d5 = 213 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_GOOD + 0x0fc, // 0x0d6 = 214 - + 0x0b2, // 0x0d7 = 215 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_NAK + 0x0ee, // 0x0d8 = 216 - + 0x0b3, // 0x0d9 = 217 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_ACK_NAK_TIMEOUT + 0x0f1, // 0x0da = 218 - + 0x0b4, // 0x0db = 219 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_BREAK + 0x0f1, // 0x0dc = 220 - + 0x0b6, // 0x0dd = 221 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_CREDIT_TIMEOUT + 0x0f5, // 0x0de = 222 - + 0x0b5, // 0x0df = 223 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_UNEXPECTED_CLOSE + 0x0ee, // 0x0e0 = 224 - + 0x0ca, // 0x0e1 = 225 - JUMP_IF_PHY_READY + 0x0e6, // 0x0e2 = 226 - + 0x033, // 0x0e3 = 227 - SOFT_RESET + 0x0ff, // 0x0e4 = 228 - JUMP + 0x001, // 0x0e5 = 229 - + 0x0b7, // 0x0e6 = 230 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_CREDIT_BLOCKED + 0x0ee, // 0x0e7 = 231 - + 0x0b8, // 0x0e8 = 232 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_MAX_BURST_SIZE + 0x0ee, // 0x0e9 = 233 - + 0x0b9, // 0x0ea = 234 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_MAX_CONNECTION_TIME + 0x0ee, // 0x0eb = 235 - + 0x0ff, // 0x0ec = 236 - JUMP + 0x0d5, // 0x0ed = 237 - + 0x006, // 0x0ee = 238 - CLOSE_NORMAL + 0x0ff, // 0x0ef = 239 - JUMP + 0x0f9, // 0x0f0 = 240 - + 0x009, // 0x0f1 = 241 - CLOSE_BREAK + 0x035, // 0x0f2 = 242 - ADVANCE_DOC + 0x0ff, // 0x0f3 = 243 - JUMP + 0x0ff, // 0x0f4 = 244 - + 0x009, // 0x0f5 = 245 - CLOSE_BREAK + 0x035, // 0x0f6 = 246 - ADVANCE_DOC + 0x0ff, // 0x0f7 = 247 - JUMP + 0x0ff, // 0x0f8 = 248 - + 0x035, // 0x0f9 = 249 - ADVANCE_DOC + 0x0ff, // 0x0fa = 250 - JUMP + 0x12d, // 0x0fb = 251 - + 0x035, // 0x0fc = 252 - ADVANCE_DOC + 0x0ff, // 0x0fd = 253 - JUMP + 0x0ff, // 0x0fe = 254 - + 0x0a9, // 0x0ff = 255 - JUMP_IF_SFO_REQ + 0x10a, // 0x100 = 256 - + 0x0b0, // 0x101 = 257 - JUMP_IF_DOC_REQ + 0x118, // 0x102 = 258 - + 0x0a8, // 0x103 = 259 - JUMP_IF_CONNECTION_ACTIVE_SET + 0x126, // 0x104 = 260 - + 0x0ca, // 0x105 = 261 - JUMP_IF_PHY_READY + 0x0ff, // 0x106 = 262 - + 0x033, // 0x107 = 263 - SOFT_RESET + 0x0ff, // 0x108 = 264 - JUMP + 0x001, // 0x109 = 265 - + 0x0ca, // 0x10a = 266 - JUMP_IF_PHY_READY + 0x110, // 0x10b = 267 - + 0x031, // 0x10c = 268 - SET_OPEN_STATUS_PHY_NOT_RDY_SFO + 0x033, // 0x10d = 269 - SOFT_RESET + 0x0ff, // 0x10e = 270 - JUMP + 0x001, // 0x10f = 271 - + 0x0a8, // 0x110 = 272 - JUMP_IF_CONNECTION_ACTIVE_SET + 0x114, // 0x111 = 273 - + 0x0ff, // 0x112 = 274 - JUMP + 0x02b, // 0x113 = 275 - + 0x0a3, // 0x114 = 276 - JUMP_IF_CONNECTION_PROFILE_OPEN_EQUAL_SFO + 0x056, // 0x115 = 277 - + 0x0ff, // 0x116 = 278 - JUMP + 0x101, // 0x117 = 279 - + 0x0ca, // 0x118 = 280 - JUMP_IF_PHY_READY + 0x11e, // 0x119 = 281 - + 0x032, // 0x11a = 282 - SET_OPEN_STATUS_PHY_NOT_RDY_DOC + 0x033, // 0x11b = 283 - SOFT_RESET + 0x0ff, // 0x11c = 284 - JUMP + 0x001, // 0x11d = 285 - + 0x0a8, // 0x11e = 286 - JUMP_IF_CONNECTION_ACTIVE_SET + 0x122, // 0x11f = 287 - + 0x0ff, // 0x120 = 288 - JUMP + 0x091, // 0x121 = 289 - + 0x0a4, // 0x122 = 290 - JUMP_IF_CONNECTION_PROFILE_OPEN_EQUAL_DOC + 0x0bc, // 0x123 = 291 - + 0x0ff, // 0x124 = 292 - JUMP + 0x103, // 0x125 = 293 - + 0x0a6, // 0x126 = 294 - JUMP_IF_CONNECTION_OPEN_MASTER_FLAG_SET + 0x12a, // 0x127 = 295 - + 0x0ff, // 0x128 = 296 - JUMP + 0x143, // 0x129 = 297 - + 0x006, // 0x12a = 298 - CLOSE_NORMAL + 0x0ff, // 0x12b = 299 - JUMP + 0x12d, // 0x12c = 300 - + 0x000, // 0x12d = 301 - NO_OP + 0x000, // 0x12e = 302 - NO_OP + 0x000, // 0x12f = 303 - NO_OP + 0x000, // 0x130 = 304 - NO_OP + 0x000, // 0x131 = 305 - NO_OP + 0x09e, // 0x132 = 306 - JUMP_IF_CLOSE_STATUS_EQUAL_NORMAL + 0x0ff, // 0x133 = 307 - + 0x0c8, // 0x134 = 308 - JUMP_IF_BREAK_RECEIVED + 0x13b, // 0x135 = 309 - + 0x0ca, // 0x136 = 310 - JUMP_IF_PHY_READY + 0x12d, // 0x137 = 311 - + 0x033, // 0x138 = 312 - SOFT_RESET + 0x0ff, // 0x139 = 313 - JUMP + 0x001, // 0x13a = 314 - + 0x009, // 0x13b = 315 - CLOSE_BREAK + 0x0c8, // 0x13c = 316 - JUMP_IF_BREAK_RECEIVED + 0x0ff, // 0x13d = 317 - + 0x0ca, // 0x13e = 318 - JUMP_IF_PHY_READY + 0x13c, // 0x13f = 319 - + 0x033, // 0x140 = 320 - SOFT_RESET + 0x0ff, // 0x141 = 321 - JUMP + 0x001, // 0x142 = 322 - + 0x0c8, // 0x143 = 323 - JUMP_IF_BREAK_RECEIVED + 0x14c, // 0x144 = 324 - + 0x0c9, // 0x145 = 325 - JUMP_IF_DONE_NORMAL_RECEIVED + 0x154, // 0x146 = 326 - + 0x0ca, // 0x147 = 327 - JUMP_IF_PHY_READY + 0x0ff, // 0x148 = 328 - + 0x033, // 0x149 = 329 - SOFT_RESET + 0x0ff, // 0x14a = 330 - JUMP + 0x0ff, // 0x14b = 331 - + 0x009, // 0x14c = 332 - CLOSE_BREAK + 0x0c8, // 0x14d = 333 - JUMP_IF_BREAK_RECEIVED + 0x0ff, // 0x14e = 334 - + 0x0ca, // 0x14f = 335 - JUMP_IF_PHY_READY + 0x14d, // 0x150 = 336 - + 0x033, // 0x151 = 337 - SOFT_RESET + 0x0ff, // 0x152 = 338 - JUMP + 0x001, // 0x153 = 339 - + 0x006, // 0x154 = 340 - CLOSE_NORMAL + 0x000, // 0x155 = 341 - NO_OP + 0x000, // 0x156 = 342 - NO_OP + 0x000, // 0x157 = 343 - NO_OP + 0x000, // 0x158 = 344 - NO_OP + 0x000, // 0x159 = 345 - NO_OP + 0x09e, // 0x15a = 346 - JUMP_IF_CLOSE_STATUS_EQUAL_NORMAL + 0x0ff, // 0x15b = 347 - + 0x0ca, // 0x15c = 348 - JUMP_IF_PHY_READY + 0x15a, // 0x15d = 349 - + 0x033, // 0x15e = 350 - SOFT_RESET + 0x0ff, // 0x15f = 351 - JUMP + 0x001, // 0x160 = 352 - + 0x000, // 0x161 = 353 - NO_OP + 0x000, // 0x162 = 354 - NO_OP + 0x000, // 0x163 = 355 - NO_OP + 0x000, // 0x164 = 356 - NO_OP + 0x000, // 0x165 = 357 - NO_OP + 0x000, // 0x166 = 358 - NO_OP + 0x000, // 0x167 = 359 - NO_OP + 0x000, // 0x168 = 360 - NO_OP + 0x000, // 0x169 = 361 - NO_OP + 0x000, // 0x16a = 362 - NO_OP + 0x000, // 0x16b = 363 - NO_OP + 0x000, // 0x16c = 364 - NO_OP + 0x000, // 0x16d = 365 - NO_OP + 0x000, // 0x16e = 366 - NO_OP + 0x000, // 0x16f = 367 - NO_OP + 0x000, // 0x170 = 368 - NO_OP + 0x000, // 0x171 = 369 - NO_OP + 0x000, // 0x172 = 370 - NO_OP + 0x000, // 0x173 = 371 - NO_OP + 0x000, // 0x174 = 372 - NO_OP + 0x000, // 0x175 = 373 - NO_OP + 0x000, // 0x176 = 374 - NO_OP + 0x000, // 0x177 = 375 - NO_OP + 0x000, // 0x178 = 376 - NO_OP + 0x000, // 0x179 = 377 - NO_OP + 0x000, // 0x17a = 378 - NO_OP + 0x000, // 0x17b = 379 - NO_OP + 0x000, // 0x17c = 380 - NO_OP + 0x000, // 0x17d = 381 - NO_OP + 0x000, // 0x17e = 382 - NO_OP + 0x000, // 0x17f = 383 - NO_OP + 0x000, // 0x180 = 384 - NO_OP + 0x000, // 0x181 = 385 - NO_OP + 0x000, // 0x182 = 386 - NO_OP + 0x000, // 0x183 = 387 - NO_OP + 0x000, // 0x184 = 388 - NO_OP + 0x000, // 0x185 = 389 - NO_OP + 0x000, // 0x186 = 390 - NO_OP + 0x000, // 0x187 = 391 - NO_OP + 0x000, // 0x188 = 392 - NO_OP + 0x000, // 0x189 = 393 - NO_OP + 0x000, // 0x18a = 394 - NO_OP + 0x000, // 0x18b = 395 - NO_OP + 0x000, // 0x18c = 396 - NO_OP + 0x000, // 0x18d = 397 - NO_OP + 0x000, // 0x18e = 398 - NO_OP + 0x000, // 0x18f = 399 - NO_OP + 0x000, // 0x190 = 400 - NO_OP + 0x000, // 0x191 = 401 - NO_OP + 0x000, // 0x192 = 402 - NO_OP + 0x000, // 0x193 = 403 - NO_OP + 0x000, // 0x194 = 404 - NO_OP + 0x000, // 0x195 = 405 - NO_OP + 0x000, // 0x196 = 406 - NO_OP + 0x000, // 0x197 = 407 - NO_OP + 0x000, // 0x198 = 408 - NO_OP + 0x000, // 0x199 = 409 - NO_OP + 0x000, // 0x19a = 410 - NO_OP + 0x000, // 0x19b = 411 - NO_OP + 0x000, // 0x19c = 412 - NO_OP + 0x000, // 0x19d = 413 - NO_OP + 0x000, // 0x19e = 414 - NO_OP + 0x000, // 0x19f = 415 - NO_OP + 0x000, // 0x1a0 = 416 - NO_OP + 0x000, // 0x1a1 = 417 - NO_OP + 0x000, // 0x1a2 = 418 - NO_OP + 0x000, // 0x1a3 = 419 - NO_OP + 0x000, // 0x1a4 = 420 - NO_OP + 0x000, // 0x1a5 = 421 - NO_OP + 0x000, // 0x1a6 = 422 - NO_OP + 0x000, // 0x1a7 = 423 - NO_OP + 0x000, // 0x1a8 = 424 - NO_OP + 0x000, // 0x1a9 = 425 - NO_OP + 0x000, // 0x1aa = 426 - NO_OP + 0x000, // 0x1ab = 427 - NO_OP + 0x000, // 0x1ac = 428 - NO_OP + 0x000, // 0x1ad = 429 - NO_OP + 0x000, // 0x1ae = 430 - NO_OP + 0x000, // 0x1af = 431 - NO_OP + 0x000, // 0x1b0 = 432 - NO_OP + 0x000, // 0x1b1 = 433 - NO_OP + 0x000, // 0x1b2 = 434 - NO_OP + 0x000, // 0x1b3 = 435 - NO_OP + 0x000, // 0x1b4 = 436 - NO_OP + 0x000, // 0x1b5 = 437 - NO_OP + 0x000, // 0x1b6 = 438 - NO_OP + 0x000, // 0x1b7 = 439 - NO_OP + 0x000, // 0x1b8 = 440 - NO_OP + 0x000, // 0x1b9 = 441 - NO_OP + 0x000, // 0x1ba = 442 - NO_OP + 0x000, // 0x1bb = 443 - NO_OP + 0x000, // 0x1bc = 444 - NO_OP + 0x000, // 0x1bd = 445 - NO_OP + 0x000, // 0x1be = 446 - NO_OP + 0x000, // 0x1bf = 447 - NO_OP + 0x000, // 0x1c0 = 448 - NO_OP + 0x000, // 0x1c1 = 449 - NO_OP + 0x000, // 0x1c2 = 450 - NO_OP + 0x000, // 0x1c3 = 451 - NO_OP + 0x000, // 0x1c4 = 452 - NO_OP + 0x000, // 0x1c5 = 453 - NO_OP + 0x000, // 0x1c6 = 454 - NO_OP + 0x000, // 0x1c7 = 455 - NO_OP + 0x000, // 0x1c8 = 456 - NO_OP + 0x000, // 0x1c9 = 457 - NO_OP + 0x000, // 0x1ca = 458 - NO_OP + 0x000, // 0x1cb = 459 - NO_OP + 0x000, // 0x1cc = 460 - NO_OP + 0x000, // 0x1cd = 461 - NO_OP + 0x000, // 0x1ce = 462 - NO_OP + 0x000, // 0x1cf = 463 - NO_OP + 0x000, // 0x1d0 = 464 - NO_OP + 0x000, // 0x1d1 = 465 - NO_OP + 0x000, // 0x1d2 = 466 - NO_OP + 0x000, // 0x1d3 = 467 - NO_OP + 0x000, // 0x1d4 = 468 - NO_OP + 0x000, // 0x1d5 = 469 - NO_OP + 0x000, // 0x1d6 = 470 - NO_OP + 0x000, // 0x1d7 = 471 - NO_OP + 0x000, // 0x1d8 = 472 - NO_OP + 0x000, // 0x1d9 = 473 - NO_OP + 0x000, // 0x1da = 474 - NO_OP + 0x000, // 0x1db = 475 - NO_OP + 0x000, // 0x1dc = 476 - NO_OP + 0x000, // 0x1dd = 477 - NO_OP + 0x000, // 0x1de = 478 - NO_OP + 0x000, // 0x1df = 479 - NO_OP + 0x000, // 0x1e0 = 480 - NO_OP + 0x000, // 0x1e1 = 481 - NO_OP + 0x000, // 0x1e2 = 482 - NO_OP + 0x000, // 0x1e3 = 483 - NO_OP + 0x000, // 0x1e4 = 484 - NO_OP + 0x000, // 0x1e5 = 485 - NO_OP + 0x000, // 0x1e6 = 486 - NO_OP + 0x000, // 0x1e7 = 487 - NO_OP + 0x000, // 0x1e8 = 488 - NO_OP + 0x000, // 0x1e9 = 489 - NO_OP + 0x000, // 0x1ea = 490 - NO_OP + 0x000, // 0x1eb = 491 - NO_OP + 0x000, // 0x1ec = 492 - NO_OP + 0x000, // 0x1ed = 493 - NO_OP + 0x000, // 0x1ee = 494 - NO_OP + 0x000, // 0x1ef = 495 - NO_OP + 0x000, // 0x1f0 = 496 - NO_OP + 0x000, // 0x1f1 = 497 - NO_OP + 0x000, // 0x1f2 = 498 - NO_OP + 0x000, // 0x1f3 = 499 - NO_OP + 0x000, // 0x1f4 = 500 - NO_OP + 0x000, // 0x1f5 = 501 - NO_OP + 0x000, // 0x1f6 = 502 - NO_OP + 0x000, // 0x1f7 = 503 - NO_OP + 0x000, // 0x1f8 = 504 - NO_OP + 0x000, // 0x1f9 = 505 - NO_OP + 0x000, // 0x1fa = 506 - NO_OP + 0x000, // 0x1fb = 507 - NO_OP + 0x000, // 0x1fc = 508 - NO_OP + 0x000, // 0x1fd = 509 - NO_OP + 0x000, // 0x1fe = 510 - NO_OP + 0x000, // 0x1ff = 511 - NO_OP +}; + +/* as of 6/27 */ +bit32 wcsImage0627[] = +{ + 0x011, // 00000 = 0 - PHY_RESET_START + 0x0ca, // 0x001 = 1 - JUMP_IF_PHY_READY + 0x009, // 0x002 = 2 - + 0x0ba, // 0x003 = 3 - JUMP_IF_HARD_RESET_PRIMITIVE + 0x010, // 0x004 = 4 - + 0x0bb, // 0x005 = 5 - JUMP_IF_IDENTIFY_FRAME_RECEIVED + 0x01e, // 0x006 = 6 - + 0x0ff, // 0x007 = 7 - JUMP + 0x001, // 0x008 = 8 - + 0x010, // 0x009 = 9 - SEND_ID_FRAME + 0x0ba, // 0x00a = 10 - JUMP_IF_HARD_RESET_PRIMITIVE + 0x010, // 0x00b = 11 - + 0x0bb, // 0x00c = 12 - JUMP_IF_IDENTIFY_FRAME_RECEIVED + 0x023, // 0x00d = 13 - + 0x0ff, // 0x00e = 14 - JUMP + 0x00a, // 0x00f = 15 - + 0x033, // 0x010 = 16 - SOFT_RESET + 0x011, // 0x011 = 17 - PHY_RESET_START + 0x0ca, // 0x012 = 18 - JUMP_IF_PHY_READY + 0x016, // 0x013 = 19 - + 0x0bb, // 0x014 = 20 - JUMP_IF_IDENTIFY_FRAME_RECEIVED + 0x01b, // 0x015 = 21 - + 0x010, // 0x016 = 22 - SEND_ID_FRAME + 0x0bb, // 0x017 = 23 - JUMP_IF_IDENTIFY_FRAME_RECEIVED + 0x023, // 0x018 = 24 - + 0x0ff, // 0x019 = 25 - JUMP + 0x017, // 0x01a = 26 - + 0x010, // 0x01b = 27 - SEND_ID_FRAME + 0x0ff, // 0x01c = 28 - JUMP + 0x023, // 0x01d = 29 - + 0x0ca, // 0x01e = 30 - JUMP_IF_PHY_READY + 0x022, // 0x01f = 31 - + 0x0ff, // 0x020 = 32 - JUMP + 0x01e, // 0x021 = 33 - + 0x010, // 0x022 = 34 - SEND_ID_FRAME + 0x000, // 0x023 = 35 - NO_OP + 0x000, // 0x024 = 36 - NO_OP + 0x000, // 0x025 = 37 - NO_OP + 0x000, // 0x026 = 38 - NO_OP + 0x000, // 0x027 = 39 - NO_OP + 0x000, // 0x028 = 40 - NO_OP + 0x0ff, // 0x029 = 41 - JUMP + 0x10d, // 0x02a = 42 - + 0x01b, // 0x02b = 43 - START_IT_NEXUS_LOSS_TIMER_SFO + 0x017, // 0x02c = 44 - PATHWAY_BLOCKED_CNT_SFO_RESET + 0x013, // 0x02d = 45 - START_ARB_WAIT_TIMER_SFO + 0x001, // 0x02e = 46 - OPEN_REQUEST_SFO + 0x000, // 0x02f = 47 - NO_OP + 0x000, // 0x030 = 48 - NO_OP + 0x000, // 0x031 = 49 - NO_OP + 0x000, // 0x032 = 50 - NO_OP + 0x000, // 0x033 = 51 - NO_OP + 0x091, // 0x034 = 52 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_ACCEPT + 0x056, // 0x035 = 53 - + 0x097, // 0x036 = 54 - JUMP_IF_OPEN_STATUS_EQUAL_RATE_NOT_SUPPORTED + 0x059, // 0x037 = 55 - + 0x09b, // 0x038 = 56 - JUMP_IF_OPEN_STATUS_EQUAL_PROTOCOL_NOT_SUPPORTED + 0x05c, // 0x039 = 57 - + 0x09d, // 0x03a = 58 - JUMP_IF_OPEN_STATUS_EQUAL_WRONG_DESTINATION + 0x05f, // 0x03b = 59 - + 0x096, // 0x03c = 60 - JUMP_IF_OPEN_STATUS_EQUAL_BREAK_RECEIVED + 0x062, // 0x03d = 61 - + 0x095, // 0x03e = 62 - JUMP_IF_OPEN_STATUS_EQUAL_BAD_DESTINATION + 0x065, // 0x03f = 63 - + 0x0a1, // 0x040 = 64 - JUMP_IF_IT_NEXUS_LOSS_TIMEOUT_SFO + 0x068, // 0x041 = 65 - + 0x09c, // 0x042 = 66 - JUMP_IF_OPEN_STATUS_EQUAL_STP_RESOURCE_BUSY + 0x02b, // 0x043 = 67 - + 0x098, // 0x044 = 68 - JUMP_IF_OPEN_STATUS_EQUAL_NO_DESTINATION + 0x10d, // 0x045 = 69 - + 0x099, // 0x046 = 70 - JUMP_IF_OPEN_STATUS_EQUAL_PATHWAY_BLOCKED + 0x06b, // 0x047 = 71 - + 0x09a, // 0x048 = 72 - JUMP_IF_OPEN_STATUS_EQUAL_RETRY + 0x02e, // 0x049 = 73 - + 0x094, // 0x04a = 74 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_TIMEOUT + 0x02e, // 0x04b = 75 - + 0x0a7, // 0x04c = 76 - JUMP_IF_CONNECTION_OPEN_SLAVE_FLAG_SET + 0x122, // 0x04d = 77 - + 0x092, // 0x04e = 78 - JUMP_IF_OPEN_STATUS_EQUAL_OCSM_BUSY + 0x02e, // 0x04f = 79 - + 0x0ca, // 0x050 = 80 - JUMP_IF_PHY_READY + 0x034, // 0x051 = 81 - + 0x031, // 0x052 = 82 - SET_OPEN_STATUS_PHY_NOT_RDY_SFO + 0x033, // 0x053 = 83 - SOFT_RESET + 0x0ff, // 0x054 = 84 - JUMP + 0x001, // 0x055 = 85 - + 0x021, // 0x056 = 86 - SET_OPEN_STATUS_NORMAL_SFO + 0x0ff, // 0x057 = 87 - JUMP + 0x06e, // 0x058 = 88 - + 0x025, // 0x059 = 89 - SET_OPEN_STATUS_BAD_RATE_SFO + 0x0ff, // 0x05a = 90 - JUMP + 0x10d, // 0x05b = 91 - + 0x026, // 0x05c = 92 - SET_OPEN_STATUS_BAD_PROTOCOL_SFO + 0x0ff, // 0x05d = 93 - JUMP + 0x10d, // 0x05e = 94 - + 0x028, // 0x05f = 95 - SET_OPEN_STATUS_WRONG_DEST_SFO + 0x0ff, // 0x060 = 96 - JUMP + 0x10d, // 0x061 = 97 - + 0x024, // 0x062 = 98 - SET_OPEN_STATUS_BREAK_SFO + 0x0ff, // 0x063 = 99 - JUMP + 0x10d, // 0x064 = 100 - + 0x023, // 0x065 = 101 - SET_OPEN_STATUS_BAD_DEST_SFO + 0x0ff, // 0x066 = 102 - JUMP + 0x10d, // 0x067 = 103 - + 0x022, // 0x068 = 104 - SET_OPEN_STATUS_IT_NEXUS_LOSS_SFO + 0x0ff, // 0x069 = 105 - JUMP + 0x10d, // 0x06a = 106 - + 0x019, // 0x06b = 107 - PATHWAY_BLOCKED_CNT_SFO_INC + 0x0ff, // 0x06c = 108 - JUMP + 0x02e, // 0x06d = 109 - + 0x000, // 0x06e = 110 - NO_OP + 0x0aa, // 0x06f = 111 - JUMP_IF_SFO_TRANSMISSION_STATUS_EQUAL_GOOD + 0x082, // 0x070 = 112 - + 0x0ab, // 0x071 = 113 - JUMP_IF_SFO_TRANSMISSION_STATUS_EQUAL_NAK + 0x086, // 0x072 = 114 - + 0x0ac, // 0x073 = 115 - JUMP_IF_SFO_TRANSMISSION_STATUS_EQUAL_ACK_NAK_TIMEOUT + 0x089, // 0x074 = 116 - + 0x0ad, // 0x075 = 117 - JUMP_IF_SFO_TRANSMISSION_STATUS_EQUAL_BREAK + 0x08f, // 0x076 = 118 - + 0x0af, // 0x077 = 119 - JUMP_IF_SFO_TRANSMISSION_STATUS_EQUAL_CREDIT_TIMEOUT + 0x08c, // 0x078 = 120 - + 0x0ae, // 0x079 = 121 - JUMP_IF_SFO_TRANSMISSION_STATUS_EQUAL_UNEXPECTED_CLOSE + 0x086, // 0x07a = 122 - + 0x0d2, // 0x07b = 123 - JUMP_IF_SFO_TRANSMISSION_STATUS_EQUAL_SMP_ERR + 0x095, // 0x07c = 124 - + 0x0ca, // 0x07d = 125 - JUMP_IF_PHY_READY + 0x06f, // 0x07e = 126 - + 0x033, // 0x07f = 127 - SOFT_RESET + 0x0ff, // 0x080 = 128 - JUMP + 0x001, // 0x081 = 129 - + 0x0d0, // 0x082 = 130 - JUMP_IF_SMP_PROTOCOL + 0x086, // 0x083 = 131 - + 0x0ff, // 0x084 = 132 - JUMP + 0x092, // 0x085 = 133 - + 0x006, // 0x086 = 134 - CLOSE_NORMAL + 0x0ff, // 0x087 = 135 - JUMP + 0x08f, // 0x088 = 136 - + 0x007, // 0x089 = 137 - CLOSE_ACK_NAK_TIMEOUT + 0x0ff, // 0x08a = 138 - JUMP + 0x08f, // 0x08b = 139 - + 0x008, // 0x08c = 140 - CLOSE_CREDIT_TIMEOUT + 0x0ff, // 0x08d = 141 - JUMP + 0x08f, // 0x08e = 142 - + 0x034, // 0x08f = 143 - ADVANCE_SFO + 0x0ff, // 0x090 = 144 - JUMP + 0x141, // 0x091 = 145 - + 0x034, // 0x092 = 146 - ADVANCE_SFO + 0x0ff, // 0x093 = 147 - JUMP + 0x10d, // 0x094 = 148 - + 0x034, // 0x095 = 149 - ADVANCE_SFO + 0x0ff, // 0x096 = 150 - JUMP + 0x14f, // 0x097 = 151 - + 0x01c, // 0x098 = 152 - START_IT_NEXUS_LOSS_TIMER_DOC + 0x018, // 0x099 = 153 - PATHWAY_BLOCKED_CNT_DOC_RESET + 0x014, // 0x09a = 154 - START_ARB_WAIT_TIMER_DOC + 0x002, // 0x09b = 155 - OPEN_REQUEST_DOC + 0x000, // 0x09c = 156 - NO_OP + 0x000, // 0x09d = 157 - NO_OP + 0x000, // 0x09e = 158 - NO_OP + 0x000, // 0x09f = 159 - NO_OP + 0x000, // 0x0a0 = 160 - NO_OP + 0x091, // 0x0a1 = 161 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_ACCEPT + 0x0c3, // 0x0a2 = 162 - + 0x097, // 0x0a3 = 163 - JUMP_IF_OPEN_STATUS_EQUAL_RATE_NOT_SUPPORTED + 0x0c6, // 0x0a4 = 164 - + 0x09b, // 0x0a5 = 165 - JUMP_IF_OPEN_STATUS_EQUAL_PROTOCOL_NOT_SUPPORTED + 0x0c9, // 0x0a6 = 166 - + 0x09d, // 0x0a7 = 167 - JUMP_IF_OPEN_STATUS_EQUAL_WRONG_DESTINATION + 0x0cc, // 0x0a8 = 168 - + 0x096, // 0x0a9 = 169 - JUMP_IF_OPEN_STATUS_EQUAL_BREAK_RECEIVED + 0x0cf, // 0x0aa = 170 - + 0x095, // 0x0ab = 171 - JUMP_IF_OPEN_STATUS_EQUAL_BAD_DESTINATION + 0x0d2, // 0x0ac = 172 - + 0x0a2, // 0x0ad = 173 - JUMP_IF_IT_NEXUS_LOSS_TIMEOUT_DOC + 0x0d5, // 0x0ae = 174 - + 0x09c, // 0x0af = 175 - JUMP_IF_OPEN_STATUS_EQUAL_STP_RESOURCE_BUSY + 0x098, // 0x0b0 = 176 - + 0x098, // 0x0b1 = 177 - JUMP_IF_OPEN_STATUS_EQUAL_NO_DESTINATION + 0x10d, // 0x0b2 = 178 - + 0x099, // 0x0b3 = 179 - JUMP_IF_OPEN_STATUS_EQUAL_PATHWAY_BLOCKED + 0x0d8, // 0x0b4 = 180 - + 0x09a, // 0x0b5 = 181 - JUMP_IF_OPEN_STATUS_EQUAL_RETRY + 0x09b, // 0x0b6 = 182 - + 0x094, // 0x0b7 = 183 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_TIMEOUT + 0x09b, // 0x0b8 = 184 - + 0x0a7, // 0x0b9 = 185 - JUMP_IF_CONNECTION_OPEN_SLAVE_FLAG_SET + 0x130, // 0x0ba = 186 - + 0x092, // 0x0bb = 187 - JUMP_IF_OPEN_STATUS_EQUAL_OCSM_BUSY + 0x09b, // 0x0bc = 188 - + 0x0ca, // 0x0bd = 189 - JUMP_IF_PHY_READY + 0x0a1, // 0x0be = 190 - + 0x032, // 0x0bf = 191 - SET_OPEN_STATUS_PHY_NOT_RDY_DOC + 0x033, // 0x0c0 = 192 - SOFT_RESET + 0x0ff, // 0x0c1 = 193 - JUMP + 0x001, // 0x0c2 = 194 - + 0x029, // 0x0c3 = 195 - SET_OPEN_STATUS_NORMAL_DOC + 0x0ff, // 0x0c4 = 196 - JUMP + 0x0db, // 0x0c5 = 197 - + 0x02d, // 0x0c6 = 198 - SET_OPEN_STATUS_BAD_RATE_DOC + 0x0ff, // 0x0c7 = 199 - JUMP + 0x10d, // 0x0c8 = 200 - + 0x02e, // 0x0c9 = 201 - SET_OPEN_STATUS_BAD_PROTOCOL_DOC + 0x0ff, // 0x0ca = 202 - JUMP + 0x10d, // 0x0cb = 203 - + 0x030, // 0x0cc = 204 - SET_OPEN_STATUS_WRONG_DEST_DOC + 0x0ff, // 0x0cd = 205 - JUMP + 0x10d, // 0x0ce = 206 - + 0x02c, // 0x0cf = 207 - SET_OPEN_STATUS_BREAK_DOC + 0x0ff, // 0x0d0 = 208 - JUMP + 0x10d, // 0x0d1 = 209 - + 0x02b, // 0x0d2 = 210 - SET_OPEN_STATUS_BAD_DEST_DOC + 0x0ff, // 0x0d3 = 211 - JUMP + 0x10d, // 0x0d4 = 212 - + 0x02a, // 0x0d5 = 213 - SET_OPEN_STATUS_IT_NEXUS_LOSS_DOC + 0x0ff, // 0x0d6 = 214 - JUMP + 0x10d, // 0x0d7 = 215 - + 0x01a, // 0x0d8 = 216 - PATHWAY_BLOCKED_CNT_DOC_INC + 0x0ff, // 0x0d9 = 217 - JUMP + 0x09b, // 0x0da = 218 - + 0x000, // 0x0db = 219 - NO_OP + 0x0b1, // 0x0dc = 220 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_GOOD + 0x0ef, // 0x0dd = 221 - + 0x0b2, // 0x0de = 222 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_NAK + 0x0fb, // 0x0df = 223 - + 0x0b3, // 0x0e0 = 224 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_ACK_NAK_TIMEOUT + 0x0fe, // 0x0e1 = 225 - + 0x0b4, // 0x0e2 = 226 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_BREAK + 0x104, // 0x0e3 = 227 - + 0x0b6, // 0x0e4 = 228 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_CREDIT_TIMEOUT + 0x101, // 0x0e5 = 229 - + 0x0b5, // 0x0e6 = 230 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_UNEXPECTED_CLOSE + 0x0fb, // 0x0e7 = 231 - + 0x0d3, // 0x0e8 = 232 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_SMP_ERR + 0x10a, // 0x0e9 = 233 - + 0x0ca, // 0x0ea = 234 - JUMP_IF_PHY_READY + 0x0f3, // 0x0eb = 235 - + 0x033, // 0x0ec = 236 - SOFT_RESET + 0x0ff, // 0x0ed = 237 - JUMP + 0x001, // 0x0ee = 238 - + 0x0d0, // 0x0ef = 239 - JUMP_IF_SMP_PROTOCOL + 0x0fb, // 0x0f0 = 240 - + 0x0ff, // 0x0f1 = 241 - JUMP + 0x107, // 0x0f2 = 242 - + 0x0b7, // 0x0f3 = 243 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_CREDIT_BLOCKED + 0x0fb, // 0x0f4 = 244 - + 0x0b8, // 0x0f5 = 245 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_MAX_BURST_SIZE + 0x0fb, // 0x0f6 = 246 - + 0x0b9, // 0x0f7 = 247 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_MAX_CONNECTION_TIME + 0x0fb, // 0x0f8 = 248 - + 0x0ff, // 0x0f9 = 249 - JUMP + 0x0dc, // 0x0fa = 250 - + 0x006, // 0x0fb = 251 - CLOSE_NORMAL + 0x0ff, // 0x0fc = 252 - JUMP + 0x104, // 0x0fd = 253 - + 0x007, // 0x0fe = 254 - CLOSE_ACK_NAK_TIMEOUT + 0x0ff, // 0x0ff = 255 - JUMP + 0x104, // 0x100 = 256 - + 0x008, // 0x101 = 257 - CLOSE_CREDIT_TIMEOUT + 0x0ff, // 0x102 = 258 - JUMP + 0x104, // 0x103 = 259 - + 0x035, // 0x104 = 260 - ADVANCE_DOC + 0x0ff, // 0x105 = 261 - JUMP + 0x141, // 0x106 = 262 - + 0x035, // 0x107 = 263 - ADVANCE_DOC + 0x0ff, // 0x108 = 264 - JUMP + 0x10d, // 0x109 = 265 - + 0x035, // 0x10a = 266 - ADVANCE_DOC + 0x0ff, // 0x10b = 267 - JUMP + 0x14f, // 0x10c = 268 - + 0x0a9, // 0x10d = 269 - JUMP_IF_SFO_REQ + 0x118, // 0x10e = 270 - + 0x0b0, // 0x10f = 271 - JUMP_IF_DOC_REQ + 0x126, // 0x110 = 272 - + 0x0a8, // 0x111 = 273 - JUMP_IF_CONNECTION_ACTIVE_SET + 0x134, // 0x112 = 274 - + 0x0ca, // 0x113 = 275 - JUMP_IF_PHY_READY + 0x10d, // 0x114 = 276 - + 0x033, // 0x115 = 277 - SOFT_RESET + 0x0ff, // 0x116 = 278 - JUMP + 0x001, // 0x117 = 279 - + 0x0ca, // 0x118 = 280 - JUMP_IF_PHY_READY + 0x11e, // 0x119 = 281 - + 0x031, // 0x11a = 282 - SET_OPEN_STATUS_PHY_NOT_RDY_SFO + 0x033, // 0x11b = 283 - SOFT_RESET + 0x0ff, // 0x11c = 284 - JUMP + 0x001, // 0x11d = 285 - + 0x0a8, // 0x11e = 286 - JUMP_IF_CONNECTION_ACTIVE_SET + 0x122, // 0x11f = 287 - + 0x0ff, // 0x120 = 288 - JUMP + 0x02b, // 0x121 = 289 - + 0x0a3, // 0x122 = 290 - JUMP_IF_CONNECTION_PROFILE_OPEN_EQUAL_SFO + 0x056, // 0x123 = 291 - + 0x0ff, // 0x124 = 292 - JUMP + 0x10f, // 0x125 = 293 - + 0x0ca, // 0x126 = 294 - JUMP_IF_PHY_READY + 0x12c, // 0x127 = 295 - + 0x032, // 0x128 = 296 - SET_OPEN_STATUS_PHY_NOT_RDY_DOC + 0x033, // 0x129 = 297 - SOFT_RESET + 0x0ff, // 0x12a = 298 - JUMP + 0x001, // 0x12b = 299 - + 0x0a8, // 0x12c = 300 - JUMP_IF_CONNECTION_ACTIVE_SET + 0x130, // 0x12d = 301 - + 0x0ff, // 0x12e = 302 - JUMP + 0x098, // 0x12f = 303 - + 0x0a4, // 0x130 = 304 - JUMP_IF_CONNECTION_PROFILE_OPEN_EQUAL_DOC + 0x0c3, // 0x131 = 305 - + 0x0ff, // 0x132 = 306 - JUMP + 0x111, // 0x133 = 307 - + 0x0d0, // 0x134 = 308 - JUMP_IF_SMP_PROTOCOL + 0x13d, // 0x135 = 309 - + 0x0a6, // 0x136 = 310 - JUMP_IF_CONNECTION_OPEN_MASTER_FLAG_SET + 0x13a, // 0x137 = 311 - + 0x0ff, // 0x138 = 312 - JUMP + 0x157, // 0x139 = 313 - + 0x006, // 0x13a = 314 - CLOSE_NORMAL + 0x0ff, // 0x13b = 315 - JUMP + 0x141, // 0x13c = 316 - + 0x0d1, // 0x13d = 317 - JUMP_IF_SMP_FRAME_ERR_RECEIVED + 0x160, // 0x13e = 318 - + 0x0ff, // 0x13f = 319 - JUMP + 0x10d, // 0x140 = 320 - + 0x000, // 0x141 = 321 - NO_OP + 0x000, // 0x142 = 322 - NO_OP + 0x000, // 0x143 = 323 - NO_OP + 0x000, // 0x144 = 324 - NO_OP + 0x000, // 0x145 = 325 - NO_OP + 0x09e, // 0x146 = 326 - JUMP_IF_CLOSE_STATUS_EQUAL_NORMAL + 0x10d, // 0x147 = 327 - + 0x0c8, // 0x148 = 328 - JUMP_IF_BREAK_RECEIVED + 0x14f, // 0x149 = 329 - + 0x0ca, // 0x14a = 330 - JUMP_IF_PHY_READY + 0x141, // 0x14b = 331 - + 0x033, // 0x14c = 332 - SOFT_RESET + 0x0ff, // 0x14d = 333 - JUMP + 0x001, // 0x14e = 334 - + 0x009, // 0x14f = 335 - CLOSE_BREAK + 0x0c8, // 0x150 = 336 - JUMP_IF_BREAK_RECEIVED + 0x10d, // 0x151 = 337 - + 0x0ca, // 0x152 = 338 - JUMP_IF_PHY_READY + 0x150, // 0x153 = 339 - + 0x033, // 0x154 = 340 - SOFT_RESET + 0x0ff, // 0x155 = 341 - JUMP + 0x001, // 0x156 = 342 - + 0x0c8, // 0x157 = 343 - JUMP_IF_BREAK_RECEIVED + 0x160, // 0x158 = 344 - + 0x0c9, // 0x159 = 345 - JUMP_IF_DONE_NORMAL_RECEIVED + 0x168, // 0x15a = 346 - + 0x0ca, // 0x15b = 347 - JUMP_IF_PHY_READY + 0x10d, // 0x15c = 348 - + 0x033, // 0x15d = 349 - SOFT_RESET + 0x0ff, // 0x15e = 350 - JUMP + 0x10d, // 0x15f = 351 - + 0x009, // 0x160 = 352 - CLOSE_BREAK + 0x0c8, // 0x161 = 353 - JUMP_IF_BREAK_RECEIVED + 0x10d, // 0x162 = 354 - + 0x0ca, // 0x163 = 355 - JUMP_IF_PHY_READY + 0x161, // 0x164 = 356 - + 0x033, // 0x165 = 357 - SOFT_RESET + 0x0ff, // 0x166 = 358 - JUMP + 0x001, // 0x167 = 359 - + 0x006, // 0x168 = 360 - CLOSE_NORMAL + 0x000, // 0x169 = 361 - NO_OP + 0x000, // 0x16a = 362 - NO_OP + 0x000, // 0x16b = 363 - NO_OP + 0x000, // 0x16c = 364 - NO_OP + 0x000, // 0x16d = 365 - NO_OP + 0x09e, // 0x16e = 366 - JUMP_IF_CLOSE_STATUS_EQUAL_NORMAL + 0x10d, // 0x16f = 367 - + 0x0ca, // 0x170 = 368 - JUMP_IF_PHY_READY + 0x16e, // 0x171 = 369 - + 0x033, // 0x172 = 370 - SOFT_RESET + 0x0ff, // 0x173 = 371 - JUMP + 0x001, // 0x174 = 372 - + 0x000, // 0x175 = 373 - NO_OP + 0x000, // 0x176 = 374 - NO_OP + 0x000, // 0x177 = 375 - NO_OP + 0x000, // 0x178 = 376 - NO_OP + 0x000, // 0x179 = 377 - NO_OP + 0x000, // 0x17a = 378 - NO_OP + 0x000, // 0x17b = 379 - NO_OP + 0x000, // 0x17c = 380 - NO_OP + 0x000, // 0x17d = 381 - NO_OP + 0x000, // 0x17e = 382 - NO_OP + 0x000, // 0x17f = 383 - NO_OP + 0x000, // 0x180 = 384 - NO_OP + 0x000, // 0x181 = 385 - NO_OP + 0x000, // 0x182 = 386 - NO_OP + 0x000, // 0x183 = 387 - NO_OP + 0x000, // 0x184 = 388 - NO_OP + 0x000, // 0x185 = 389 - NO_OP + 0x000, // 0x186 = 390 - NO_OP + 0x000, // 0x187 = 391 - NO_OP + 0x000, // 0x188 = 392 - NO_OP + 0x000, // 0x189 = 393 - NO_OP + 0x000, // 0x18a = 394 - NO_OP + 0x000, // 0x18b = 395 - NO_OP + 0x000, // 0x18c = 396 - NO_OP + 0x000, // 0x18d = 397 - NO_OP + 0x000, // 0x18e = 398 - NO_OP + 0x000, // 0x18f = 399 - NO_OP + 0x000, // 0x190 = 400 - NO_OP + 0x000, // 0x191 = 401 - NO_OP + 0x000, // 0x192 = 402 - NO_OP + 0x000, // 0x193 = 403 - NO_OP + 0x000, // 0x194 = 404 - NO_OP + 0x000, // 0x195 = 405 - NO_OP + 0x000, // 0x196 = 406 - NO_OP + 0x000, // 0x197 = 407 - NO_OP + 0x000, // 0x198 = 408 - NO_OP + 0x000, // 0x199 = 409 - NO_OP + 0x000, // 0x19a = 410 - NO_OP + 0x000, // 0x19b = 411 - NO_OP + 0x000, // 0x19c = 412 - NO_OP + 0x000, // 0x19d = 413 - NO_OP + 0x000, // 0x19e = 414 - NO_OP + 0x000, // 0x19f = 415 - NO_OP + 0x000, // 0x1a0 = 416 - NO_OP + 0x000, // 0x1a1 = 417 - NO_OP + 0x000, // 0x1a2 = 418 - NO_OP + 0x000, // 0x1a3 = 419 - NO_OP + 0x000, // 0x1a4 = 420 - NO_OP + 0x000, // 0x1a5 = 421 - NO_OP + 0x000, // 0x1a6 = 422 - NO_OP + 0x000, // 0x1a7 = 423 - NO_OP + 0x000, // 0x1a8 = 424 - NO_OP + 0x000, // 0x1a9 = 425 - NO_OP + 0x000, // 0x1aa = 426 - NO_OP + 0x000, // 0x1ab = 427 - NO_OP + 0x000, // 0x1ac = 428 - NO_OP + 0x000, // 0x1ad = 429 - NO_OP + 0x000, // 0x1ae = 430 - NO_OP + 0x000, // 0x1af = 431 - NO_OP + 0x000, // 0x1b0 = 432 - NO_OP + 0x000, // 0x1b1 = 433 - NO_OP + 0x000, // 0x1b2 = 434 - NO_OP + 0x000, // 0x1b3 = 435 - NO_OP + 0x000, // 0x1b4 = 436 - NO_OP + 0x000, // 0x1b5 = 437 - NO_OP + 0x000, // 0x1b6 = 438 - NO_OP + 0x000, // 0x1b7 = 439 - NO_OP + 0x000, // 0x1b8 = 440 - NO_OP + 0x000, // 0x1b9 = 441 - NO_OP + 0x000, // 0x1ba = 442 - NO_OP + 0x000, // 0x1bb = 443 - NO_OP + 0x000, // 0x1bc = 444 - NO_OP + 0x000, // 0x1bd = 445 - NO_OP + 0x000, // 0x1be = 446 - NO_OP + 0x000, // 0x1bf = 447 - NO_OP + 0x000, // 0x1c0 = 448 - NO_OP + 0x000, // 0x1c1 = 449 - NO_OP + 0x000, // 0x1c2 = 450 - NO_OP + 0x000, // 0x1c3 = 451 - NO_OP + 0x000, // 0x1c4 = 452 - NO_OP + 0x000, // 0x1c5 = 453 - NO_OP + 0x000, // 0x1c6 = 454 - NO_OP + 0x000, // 0x1c7 = 455 - NO_OP + 0x000, // 0x1c8 = 456 - NO_OP + 0x000, // 0x1c9 = 457 - NO_OP + 0x000, // 0x1ca = 458 - NO_OP + 0x000, // 0x1cb = 459 - NO_OP + 0x000, // 0x1cc = 460 - NO_OP + 0x000, // 0x1cd = 461 - NO_OP + 0x000, // 0x1ce = 462 - NO_OP + 0x000, // 0x1cf = 463 - NO_OP + 0x000, // 0x1d0 = 464 - NO_OP + 0x000, // 0x1d1 = 465 - NO_OP + 0x000, // 0x1d2 = 466 - NO_OP + 0x000, // 0x1d3 = 467 - NO_OP + 0x000, // 0x1d4 = 468 - NO_OP + 0x000, // 0x1d5 = 469 - NO_OP + 0x000, // 0x1d6 = 470 - NO_OP + 0x000, // 0x1d7 = 471 - NO_OP + 0x000, // 0x1d8 = 472 - NO_OP + 0x000, // 0x1d9 = 473 - NO_OP + 0x000, // 0x1da = 474 - NO_OP + 0x000, // 0x1db = 475 - NO_OP + 0x000, // 0x1dc = 476 - NO_OP + 0x000, // 0x1dd = 477 - NO_OP + 0x000, // 0x1de = 478 - NO_OP + 0x000, // 0x1df = 479 - NO_OP + 0x000, // 0x1e0 = 480 - NO_OP + 0x000, // 0x1e1 = 481 - NO_OP + 0x000, // 0x1e2 = 482 - NO_OP + 0x000, // 0x1e3 = 483 - NO_OP + 0x000, // 0x1e4 = 484 - NO_OP + 0x000, // 0x1e5 = 485 - NO_OP + 0x000, // 0x1e6 = 486 - NO_OP + 0x000, // 0x1e7 = 487 - NO_OP + 0x000, // 0x1e8 = 488 - NO_OP + 0x000, // 0x1e9 = 489 - NO_OP + 0x000, // 0x1ea = 490 - NO_OP + 0x000, // 0x1eb = 491 - NO_OP + 0x000, // 0x1ec = 492 - NO_OP + 0x000, // 0x1ed = 493 - NO_OP + 0x000, // 0x1ee = 494 - NO_OP + 0x000, // 0x1ef = 495 - NO_OP + 0x000, // 0x1f0 = 496 - NO_OP + 0x000, // 0x1f1 = 497 - NO_OP + 0x000, // 0x1f2 = 498 - NO_OP + 0x000, // 0x1f3 = 499 - NO_OP + 0x000, // 0x1f4 = 500 - NO_OP + 0x000, // 0x1f5 = 501 - NO_OP + 0x000, // 0x1f6 = 502 - NO_OP + 0x000, // 0x1f7 = 503 - NO_OP + 0x000, // 0x1f8 = 504 - NO_OP + 0x000, // 0x1f9 = 505 - NO_OP + 0x000, // 0x1fa = 506 - NO_OP + 0x000, // 0x1fb = 507 - NO_OP + 0x000, // 0x1fc = 508 - NO_OP + 0x000, // 0x1fd = 509 - NO_OP + 0x000, // 0x1fe = 510 - NO_OP + 0x000, // 0x1ff = 511 - NO_OP +}; + +/* as of 8/18/2005 */ +bit32 wcsImage0818[] = +{ + 0x011, // 00000 = 0 - PHY_RESET_START + 0x0ca, // 0x001 = 1 - JUMP_IF_PHY_READY + 0x009, // 0x002 = 2 - + 0x0ba, // 0x003 = 3 - JUMP_IF_HARD_RESET_PRIMITIVE + 0x010, // 0x004 = 4 - + 0x0bb, // 0x005 = 5 - JUMP_IF_IDENTIFY_FRAME_RECEIVED + 0x01e, // 0x006 = 6 - + 0x0ff, // 0x007 = 7 - JUMP + 0x001, // 0x008 = 8 - + 0x010, // 0x009 = 9 - SEND_ID_FRAME + 0x0ba, // 0x00a = 10 - JUMP_IF_HARD_RESET_PRIMITIVE + 0x010, // 0x00b = 11 - + 0x0bb, // 0x00c = 12 - JUMP_IF_IDENTIFY_FRAME_RECEIVED + 0x023, // 0x00d = 13 - + 0x0ff, // 0x00e = 14 - JUMP + 0x00a, // 0x00f = 15 - + 0x033, // 0x010 = 16 - SOFT_RESET + 0x011, // 0x011 = 17 - PHY_RESET_START + 0x0ca, // 0x012 = 18 - JUMP_IF_PHY_READY + 0x016, // 0x013 = 19 - + 0x0bb, // 0x014 = 20 - JUMP_IF_IDENTIFY_FRAME_RECEIVED + 0x01b, // 0x015 = 21 - + 0x010, // 0x016 = 22 - SEND_ID_FRAME + 0x0bb, // 0x017 = 23 - JUMP_IF_IDENTIFY_FRAME_RECEIVED + 0x023, // 0x018 = 24 - + 0x0ff, // 0x019 = 25 - JUMP + 0x017, // 0x01a = 26 - + 0x010, // 0x01b = 27 - SEND_ID_FRAME + 0x0ff, // 0x01c = 28 - JUMP + 0x023, // 0x01d = 29 - + 0x0ca, // 0x01e = 30 - JUMP_IF_PHY_READY + 0x022, // 0x01f = 31 - + 0x0ff, // 0x020 = 32 - JUMP + 0x01e, // 0x021 = 33 - + 0x010, // 0x022 = 34 - SEND_ID_FRAME + 0x000, // 0x023 = 35 - NO_OP + 0x000, // 0x024 = 36 - NO_OP + 0x000, // 0x025 = 37 - NO_OP + 0x000, // 0x026 = 38 - NO_OP + 0x000, // 0x027 = 39 - NO_OP + 0x000, // 0x028 = 40 - NO_OP + 0x0ff, // 0x029 = 41 - JUMP + 0x10d, // 0x02a = 42 - + 0x01b, // 0x02b = 43 - START_IT_NEXUS_LOSS_TIMER_SFO + 0x017, // 0x02c = 44 - PATHWAY_BLOCKED_CNT_SFO_RESET + 0x013, // 0x02d = 45 - START_ARB_WAIT_TIMER_SFO + 0x001, // 0x02e = 46 - OPEN_REQUEST_SFO + 0x000, // 0x02f = 47 - NO_OP + 0x000, // 0x030 = 48 - NO_OP + 0x000, // 0x031 = 49 - NO_OP + 0x000, // 0x032 = 50 - NO_OP + 0x000, // 0x033 = 51 - NO_OP + 0x091, // 0x034 = 52 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_ACCEPT + 0x056, // 0x035 = 53 - + 0x097, // 0x036 = 54 - JUMP_IF_OPEN_STATUS_EQUAL_RATE_NOT_SUPPORTED + 0x059, // 0x037 = 55 - + 0x09b, // 0x038 = 56 - JUMP_IF_OPEN_STATUS_EQUAL_PROTOCOL_NOT_SUPPORTED + 0x05c, // 0x039 = 57 - + 0x09d, // 0x03a = 58 - JUMP_IF_OPEN_STATUS_EQUAL_WRONG_DESTINATION + 0x05f, // 0x03b = 59 - + 0x096, // 0x03c = 60 - JUMP_IF_OPEN_STATUS_EQUAL_BREAK_RECEIVED + 0x062, // 0x03d = 61 - + 0x095, // 0x03e = 62 - JUMP_IF_OPEN_STATUS_EQUAL_BAD_DESTINATION + 0x065, // 0x03f = 63 - + 0x0a1, // 0x040 = 64 - JUMP_IF_IT_NEXUS_LOSS_TIMEOUT_SFO + 0x068, // 0x041 = 65 - + 0x09c, // 0x042 = 66 - JUMP_IF_OPEN_STATUS_EQUAL_STP_RESOURCE_BUSY + 0x02b, // 0x043 = 67 - + 0x098, // 0x044 = 68 - JUMP_IF_OPEN_STATUS_EQUAL_NO_DESTINATION + 0x10d, // 0x045 = 69 - + 0x099, // 0x046 = 70 - JUMP_IF_OPEN_STATUS_EQUAL_PATHWAY_BLOCKED + 0x06b, // 0x047 = 71 - + 0x09a, // 0x048 = 72 - JUMP_IF_OPEN_STATUS_EQUAL_RETRY + 0x02e, // 0x049 = 73 - + 0x094, // 0x04a = 74 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_TIMEOUT + 0x02e, // 0x04b = 75 - + 0x0a7, // 0x04c = 76 - JUMP_IF_CONNECTION_OPEN_SLAVE_FLAG_SET + 0x122, // 0x04d = 77 - + 0x092, // 0x04e = 78 - JUMP_IF_OPEN_STATUS_EQUAL_OCSM_BUSY + 0x02e, // 0x04f = 79 - + 0x0ca, // 0x050 = 80 - JUMP_IF_PHY_READY + 0x034, // 0x051 = 81 - + 0x031, // 0x052 = 82 - SET_OPEN_STATUS_PHY_NOT_RDY_SFO + 0x033, // 0x053 = 83 - SOFT_RESET + 0x0ff, // 0x054 = 84 - JUMP + 0x001, // 0x055 = 85 - + 0x021, // 0x056 = 86 - SET_OPEN_STATUS_NORMAL_SFO + 0x0ff, // 0x057 = 87 - JUMP + 0x06e, // 0x058 = 88 - + 0x025, // 0x059 = 89 - SET_OPEN_STATUS_BAD_RATE_SFO + 0x0ff, // 0x05a = 90 - JUMP + 0x10d, // 0x05b = 91 - + 0x026, // 0x05c = 92 - SET_OPEN_STATUS_BAD_PROTOCOL_SFO + 0x0ff, // 0x05d = 93 - JUMP + 0x10d, // 0x05e = 94 - + 0x028, // 0x05f = 95 - SET_OPEN_STATUS_WRONG_DEST_SFO + 0x0ff, // 0x060 = 96 - JUMP + 0x10d, // 0x061 = 97 - + 0x024, // 0x062 = 98 - SET_OPEN_STATUS_BREAK_SFO + 0x0ff, // 0x063 = 99 - JUMP + 0x10d, // 0x064 = 100 - + 0x023, // 0x065 = 101 - SET_OPEN_STATUS_BAD_DEST_SFO + 0x0ff, // 0x066 = 102 - JUMP + 0x10d, // 0x067 = 103 - + 0x022, // 0x068 = 104 - SET_OPEN_STATUS_IT_NEXUS_LOSS_SFO + 0x0ff, // 0x069 = 105 - JUMP + 0x10d, // 0x06a = 106 - + 0x019, // 0x06b = 107 - PATHWAY_BLOCKED_CNT_SFO_INC + 0x0ff, // 0x06c = 108 - JUMP + 0x02e, // 0x06d = 109 - + 0x000, // 0x06e = 110 - NO_OP + 0x0aa, // 0x06f = 111 - JUMP_IF_SFO_TRANSMISSION_STATUS_EQUAL_GOOD + 0x082, // 0x070 = 112 - + 0x0ab, // 0x071 = 113 - JUMP_IF_SFO_TRANSMISSION_STATUS_EQUAL_NAK + 0x086, // 0x072 = 114 - + 0x0ac, // 0x073 = 115 - JUMP_IF_SFO_TRANSMISSION_STATUS_EQUAL_ACK_NAK_TIMEOUT + 0x089, // 0x074 = 116 - + 0x0ad, // 0x075 = 117 - JUMP_IF_SFO_TRANSMISSION_STATUS_EQUAL_BREAK + 0x08f, // 0x076 = 118 - + 0x0af, // 0x077 = 119 - JUMP_IF_SFO_TRANSMISSION_STATUS_EQUAL_CREDIT_TIMEOUT + 0x08c, // 0x078 = 120 - + 0x0ae, // 0x079 = 121 - JUMP_IF_SFO_TRANSMISSION_STATUS_EQUAL_UNEXPECTED_CLOSE + 0x086, // 0x07a = 122 - + 0x0d2, // 0x07b = 123 - JUMP_IF_SFO_TRANSMISSION_STATUS_EQUAL_SMP_ERR + 0x095, // 0x07c = 124 - + 0x0ca, // 0x07d = 125 - JUMP_IF_PHY_READY + 0x06f, // 0x07e = 126 - + 0x033, // 0x07f = 127 - SOFT_RESET + 0x0ff, // 0x080 = 128 - JUMP + 0x001, // 0x081 = 129 - + 0x0d0, // 0x082 = 130 - JUMP_IF_SMP_PROTOCOL + 0x086, // 0x083 = 131 - + 0x0ff, // 0x084 = 132 - JUMP + 0x092, // 0x085 = 133 - + 0x006, // 0x086 = 134 - CLOSE_NORMAL + 0x0ff, // 0x087 = 135 - JUMP + 0x08f, // 0x088 = 136 - + 0x007, // 0x089 = 137 - CLOSE_ACK_NAK_TIMEOUT + 0x0ff, // 0x08a = 138 - JUMP + 0x08f, // 0x08b = 139 - + 0x008, // 0x08c = 140 - CLOSE_CREDIT_TIMEOUT + 0x0ff, // 0x08d = 141 - JUMP + 0x08f, // 0x08e = 142 - + 0x034, // 0x08f = 143 - ADVANCE_SFO + 0x0ff, // 0x090 = 144 - JUMP + 0x14c, // 0x091 = 145 - + 0x034, // 0x092 = 146 - ADVANCE_SFO + 0x0ff, // 0x093 = 147 - JUMP + 0x10d, // 0x094 = 148 - + 0x034, // 0x095 = 149 - ADVANCE_SFO + 0x0ff, // 0x096 = 150 - JUMP + 0x15a, // 0x097 = 151 - + 0x01c, // 0x098 = 152 - START_IT_NEXUS_LOSS_TIMER_DOC + 0x018, // 0x099 = 153 - PATHWAY_BLOCKED_CNT_DOC_RESET + 0x014, // 0x09a = 154 - START_ARB_WAIT_TIMER_DOC + 0x002, // 0x09b = 155 - OPEN_REQUEST_DOC + 0x000, // 0x09c = 156 - NO_OP + 0x000, // 0x09d = 157 - NO_OP + 0x000, // 0x09e = 158 - NO_OP + 0x000, // 0x09f = 159 - NO_OP + 0x000, // 0x0a0 = 160 - NO_OP + 0x091, // 0x0a1 = 161 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_ACCEPT + 0x0c3, // 0x0a2 = 162 - + 0x097, // 0x0a3 = 163 - JUMP_IF_OPEN_STATUS_EQUAL_RATE_NOT_SUPPORTED + 0x0c6, // 0x0a4 = 164 - + 0x09b, // 0x0a5 = 165 - JUMP_IF_OPEN_STATUS_EQUAL_PROTOCOL_NOT_SUPPORTED + 0x0c9, // 0x0a6 = 166 - + 0x09d, // 0x0a7 = 167 - JUMP_IF_OPEN_STATUS_EQUAL_WRONG_DESTINATION + 0x0cc, // 0x0a8 = 168 - + 0x096, // 0x0a9 = 169 - JUMP_IF_OPEN_STATUS_EQUAL_BREAK_RECEIVED + 0x0cf, // 0x0aa = 170 - + 0x095, // 0x0ab = 171 - JUMP_IF_OPEN_STATUS_EQUAL_BAD_DESTINATION + 0x0d2, // 0x0ac = 172 - + 0x0a2, // 0x0ad = 173 - JUMP_IF_IT_NEXUS_LOSS_TIMEOUT_DOC + 0x0d5, // 0x0ae = 174 - + 0x09c, // 0x0af = 175 - JUMP_IF_OPEN_STATUS_EQUAL_STP_RESOURCE_BUSY + 0x098, // 0x0b0 = 176 - + 0x098, // 0x0b1 = 177 - JUMP_IF_OPEN_STATUS_EQUAL_NO_DESTINATION + 0x10d, // 0x0b2 = 178 - + 0x099, // 0x0b3 = 179 - JUMP_IF_OPEN_STATUS_EQUAL_PATHWAY_BLOCKED + 0x0d8, // 0x0b4 = 180 - + 0x09a, // 0x0b5 = 181 - JUMP_IF_OPEN_STATUS_EQUAL_RETRY + 0x09b, // 0x0b6 = 182 - + 0x094, // 0x0b7 = 183 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_TIMEOUT + 0x09b, // 0x0b8 = 184 - + 0x0a7, // 0x0b9 = 185 - JUMP_IF_CONNECTION_OPEN_SLAVE_FLAG_SET + 0x134, // 0x0ba = 186 - + 0x092, // 0x0bb = 187 - JUMP_IF_OPEN_STATUS_EQUAL_OCSM_BUSY + 0x09b, // 0x0bc = 188 - + 0x0ca, // 0x0bd = 189 - JUMP_IF_PHY_READY + 0x0a1, // 0x0be = 190 - + 0x032, // 0x0bf = 191 - SET_OPEN_STATUS_PHY_NOT_RDY_DOC + 0x033, // 0x0c0 = 192 - SOFT_RESET + 0x0ff, // 0x0c1 = 193 - JUMP + 0x001, // 0x0c2 = 194 - + 0x029, // 0x0c3 = 195 - SET_OPEN_STATUS_NORMAL_DOC + 0x0ff, // 0x0c4 = 196 - JUMP + 0x0db, // 0x0c5 = 197 - + 0x02d, // 0x0c6 = 198 - SET_OPEN_STATUS_BAD_RATE_DOC + 0x0ff, // 0x0c7 = 199 - JUMP + 0x10d, // 0x0c8 = 200 - + 0x02e, // 0x0c9 = 201 - SET_OPEN_STATUS_BAD_PROTOCOL_DOC + 0x0ff, // 0x0ca = 202 - JUMP + 0x10d, // 0x0cb = 203 - + 0x030, // 0x0cc = 204 - SET_OPEN_STATUS_WRONG_DEST_DOC + 0x0ff, // 0x0cd = 205 - JUMP + 0x10d, // 0x0ce = 206 - + 0x02c, // 0x0cf = 207 - SET_OPEN_STATUS_BREAK_DOC + 0x0ff, // 0x0d0 = 208 - JUMP + 0x10d, // 0x0d1 = 209 - + 0x02b, // 0x0d2 = 210 - SET_OPEN_STATUS_BAD_DEST_DOC + 0x0ff, // 0x0d3 = 211 - JUMP + 0x10d, // 0x0d4 = 212 - + 0x02a, // 0x0d5 = 213 - SET_OPEN_STATUS_IT_NEXUS_LOSS_DOC + 0x0ff, // 0x0d6 = 214 - JUMP + 0x10d, // 0x0d7 = 215 - + 0x01a, // 0x0d8 = 216 - PATHWAY_BLOCKED_CNT_DOC_INC + 0x0ff, // 0x0d9 = 217 - JUMP + 0x09b, // 0x0da = 218 - + 0x000, // 0x0db = 219 - NO_OP + 0x0b1, // 0x0dc = 220 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_GOOD + 0x0ef, // 0x0dd = 221 - + 0x0b2, // 0x0de = 222 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_NAK + 0x0fb, // 0x0df = 223 - + 0x0b3, // 0x0e0 = 224 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_ACK_NAK_TIMEOUT + 0x0fe, // 0x0e1 = 225 - + 0x0b4, // 0x0e2 = 226 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_BREAK + 0x104, // 0x0e3 = 227 - + 0x0b6, // 0x0e4 = 228 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_CREDIT_TIMEOUT + 0x101, // 0x0e5 = 229 - + 0x0b5, // 0x0e6 = 230 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_UNEXPECTED_CLOSE + 0x0fb, // 0x0e7 = 231 - + 0x0d3, // 0x0e8 = 232 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_SMP_ERR + 0x10a, // 0x0e9 = 233 - + 0x0ca, // 0x0ea = 234 - JUMP_IF_PHY_READY + 0x0f3, // 0x0eb = 235 - + 0x033, // 0x0ec = 236 - SOFT_RESET + 0x0ff, // 0x0ed = 237 - JUMP + 0x001, // 0x0ee = 238 - + 0x0d0, // 0x0ef = 239 - JUMP_IF_SMP_PROTOCOL + 0x0fb, // 0x0f0 = 240 - + 0x0ff, // 0x0f1 = 241 - JUMP + 0x107, // 0x0f2 = 242 - + 0x0b7, // 0x0f3 = 243 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_CREDIT_BLOCKED + 0x0fb, // 0x0f4 = 244 - + 0x0b8, // 0x0f5 = 245 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_MAX_BURST_SIZE + 0x0fb, // 0x0f6 = 246 - + 0x0b9, // 0x0f7 = 247 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_MAX_CONNECTION_TIME + 0x0fb, // 0x0f8 = 248 - + 0x0ff, // 0x0f9 = 249 - JUMP + 0x0dc, // 0x0fa = 250 - + 0x006, // 0x0fb = 251 - CLOSE_NORMAL + 0x0ff, // 0x0fc = 252 - JUMP + 0x104, // 0x0fd = 253 - + 0x007, // 0x0fe = 254 - CLOSE_ACK_NAK_TIMEOUT + 0x0ff, // 0x0ff = 255 - JUMP + 0x104, // 0x100 = 256 - + 0x008, // 0x101 = 257 - CLOSE_CREDIT_TIMEOUT + 0x0ff, // 0x102 = 258 - JUMP + 0x104, // 0x103 = 259 - + 0x035, // 0x104 = 260 - ADVANCE_DOC + 0x0ff, // 0x105 = 261 - JUMP + 0x14c, // 0x106 = 262 - + 0x035, // 0x107 = 263 - ADVANCE_DOC + 0x0ff, // 0x108 = 264 - JUMP + 0x10d, // 0x109 = 265 - + 0x035, // 0x10a = 266 - ADVANCE_DOC + 0x0ff, // 0x10b = 267 - JUMP + 0x15a, // 0x10c = 268 - + 0x0a9, // 0x10d = 269 - JUMP_IF_SFO_REQ + 0x118, // 0x10e = 270 - + 0x0b0, // 0x10f = 271 - JUMP_IF_DOC_REQ + 0x12a, // 0x110 = 272 - + 0x0a8, // 0x111 = 273 - JUMP_IF_CONNECTION_ACTIVE_SET + 0x13c, // 0x112 = 274 - + 0x0ca, // 0x113 = 275 - JUMP_IF_PHY_READY + 0x10d, // 0x114 = 276 - + 0x033, // 0x115 = 277 - SOFT_RESET + 0x0ff, // 0x116 = 278 - JUMP + 0x001, // 0x117 = 279 - + 0x0ca, // 0x118 = 280 - JUMP_IF_PHY_READY + 0x11e, // 0x119 = 281 - + 0x031, // 0x11a = 282 - SET_OPEN_STATUS_PHY_NOT_RDY_SFO + 0x033, // 0x11b = 283 - SOFT_RESET + 0x0ff, // 0x11c = 284 - JUMP + 0x001, // 0x11d = 285 - + 0x0a8, // 0x11e = 286 - JUMP_IF_CONNECTION_ACTIVE_SET + 0x122, // 0x11f = 287 - + 0x0ff, // 0x120 = 288 - JUMP + 0x02b, // 0x121 = 289 - + 0x0a3, // 0x122 = 290 - JUMP_IF_CONNECTION_PROFILE_OPEN_EQUAL_SFO + 0x126, // 0x123 = 291 - + 0x0ff, // 0x124 = 292 - JUMP + 0x10f, // 0x125 = 293 - + 0x0c8, // 0x126 = 294 - JUMP_IF_BREAK_RECEIVED + 0x15a, // 0x127 = 295 - + 0x0ff, // 0x128 = 296 - JUMP + 0x056, // 0x129 = 297 - + 0x0ca, // 0x12a = 298 - JUMP_IF_PHY_READY + 0x130, // 0x12b = 299 - + 0x032, // 0x12c = 300 - SET_OPEN_STATUS_PHY_NOT_RDY_DOC + 0x033, // 0x12d = 301 - SOFT_RESET + 0x0ff, // 0x12e = 302 - JUMP + 0x001, // 0x12f = 303 - + 0x0a8, // 0x130 = 304 - JUMP_IF_CONNECTION_ACTIVE_SET + 0x134, // 0x131 = 305 - + 0x0ff, // 0x132 = 306 - JUMP + 0x098, // 0x133 = 307 - + 0x0a4, // 0x134 = 308 - JUMP_IF_CONNECTION_PROFILE_OPEN_EQUAL_DOC + 0x138, // 0x135 = 309 - + 0x0ff, // 0x136 = 310 - JUMP + 0x111, // 0x137 = 311 - + 0x0c8, // 0x138 = 312 - JUMP_IF_BREAK_RECEIVED + 0x15a, // 0x139 = 313 - + 0x0ff, // 0x13a = 314 - JUMP + 0x0c3, // 0x13b = 315 - + 0x0d0, // 0x13c = 316 - JUMP_IF_SMP_PROTOCOL + 0x145, // 0x13d = 317 - + 0x0a6, // 0x13e = 318 - JUMP_IF_CONNECTION_OPEN_MASTER_FLAG_SET + 0x142, // 0x13f = 319 - + 0x0ff, // 0x140 = 320 - JUMP + 0x15f, // 0x141 = 321 - + 0x006, // 0x142 = 322 - CLOSE_NORMAL + 0x0ff, // 0x143 = 323 - JUMP + 0x14c, // 0x144 = 324 - + 0x0d1, // 0x145 = 325 - JUMP_IF_SMP_FRAME_ERR_RECEIVED + 0x168, // 0x146 = 326 - + 0x0ff, // 0x147 = 327 - JUMP + 0x10d, // 0x148 = 328 - + 0x0c8, // 0x149 = 329 - JUMP_IF_BREAK_RECEIVED + 0x15a, // 0x14a = 330 - + 0x006, // 0x14b = 331 - CLOSE_NORMAL + 0x000, // 0x14c = 332 - NO_OP + 0x000, // 0x14d = 333 - NO_OP + 0x000, // 0x14e = 334 - NO_OP + 0x000, // 0x14f = 335 - NO_OP + 0x000, // 0x150 = 336 - NO_OP + 0x0cd, // 0x151 = 337 - JUMP_IF_CLOSE_STATUS_EQUAL_ANY + 0x10d, // 0x152 = 338 - + 0x0c8, // 0x153 = 339 - JUMP_IF_BREAK_RECEIVED + 0x15a, // 0x154 = 340 - + 0x0ca, // 0x155 = 341 - JUMP_IF_PHY_READY + 0x14c, // 0x156 = 342 - + 0x033, // 0x157 = 343 - SOFT_RESET + 0x0ff, // 0x158 = 344 - JUMP + 0x001, // 0x159 = 345 - + 0x009, // 0x15a = 346 - CLOSE_BREAK + 0x0a8, // 0x15b = 347 - JUMP_IF_CONNECTION_ACTIVE_SET + 0x15b, // 0x15c = 348 - + 0x0ff, // 0x15d = 349 - JUMP + 0x10d, // 0x15e = 350 - + 0x0c8, // 0x15f = 351 - JUMP_IF_BREAK_RECEIVED + 0x168, // 0x160 = 352 - + 0x0ce, // 0x161 = 353 - JUMP_IF_ANY_DONE_RECEIVED + 0x16d, // 0x162 = 354 - + 0x0ca, // 0x163 = 355 - JUMP_IF_PHY_READY + 0x10d, // 0x164 = 356 - + 0x033, // 0x165 = 357 - SOFT_RESET + 0x0ff, // 0x166 = 358 - JUMP + 0x10d, // 0x167 = 359 - + 0x009, // 0x168 = 360 - CLOSE_BREAK + 0x0a8, // 0x169 = 361 - JUMP_IF_CONNECTION_ACTIVE_SET + 0x169, // 0x16a = 362 - + 0x0ff, // 0x16b = 363 - JUMP + 0x10d, // 0x16c = 364 - + 0x006, // 0x16d = 365 - CLOSE_NORMAL + 0x000, // 0x16e = 366 - NO_OP + 0x000, // 0x16f = 367 - NO_OP + 0x000, // 0x170 = 368 - NO_OP + 0x000, // 0x171 = 369 - NO_OP + 0x000, // 0x172 = 370 - NO_OP + 0x0cd, // 0x173 = 371 - JUMP_IF_CLOSE_STATUS_EQUAL_ANY + 0x10d, // 0x174 = 372 - + 0x0c8, // 0x175 = 373 - JUMP_IF_BREAK_RECEIVED + 0x168, // 0x176 = 374 - + 0x0ca, // 0x177 = 375 - JUMP_IF_PHY_READY + 0x173, // 0x178 = 376 - + 0x033, // 0x179 = 377 - SOFT_RESET + 0x0ff, // 0x17a = 378 - JUMP + 0x001, // 0x17b = 379 - + 0x000, // 0x17c = 380 - NO_OP + 0x000, // 0x17d = 381 - NO_OP + 0x000, // 0x17e = 382 - NO_OP + 0x000, // 0x17f = 383 - NO_OP + 0x000, // 0x180 = 384 - NO_OP + 0x000, // 0x181 = 385 - NO_OP + 0x000, // 0x182 = 386 - NO_OP + 0x000, // 0x183 = 387 - NO_OP + 0x000, // 0x184 = 388 - NO_OP + 0x000, // 0x185 = 389 - NO_OP + 0x000, // 0x186 = 390 - NO_OP + 0x000, // 0x187 = 391 - NO_OP + 0x000, // 0x188 = 392 - NO_OP + 0x000, // 0x189 = 393 - NO_OP + 0x000, // 0x18a = 394 - NO_OP + 0x000, // 0x18b = 395 - NO_OP + 0x000, // 0x18c = 396 - NO_OP + 0x000, // 0x18d = 397 - NO_OP + 0x000, // 0x18e = 398 - NO_OP + 0x000, // 0x18f = 399 - NO_OP + 0x000, // 0x190 = 400 - NO_OP + 0x000, // 0x191 = 401 - NO_OP + 0x000, // 0x192 = 402 - NO_OP + 0x000, // 0x193 = 403 - NO_OP + 0x000, // 0x194 = 404 - NO_OP + 0x000, // 0x195 = 405 - NO_OP + 0x000, // 0x196 = 406 - NO_OP + 0x000, // 0x197 = 407 - NO_OP + 0x000, // 0x198 = 408 - NO_OP + 0x000, // 0x199 = 409 - NO_OP + 0x000, // 0x19a = 410 - NO_OP + 0x000, // 0x19b = 411 - NO_OP + 0x000, // 0x19c = 412 - NO_OP + 0x000, // 0x19d = 413 - NO_OP + 0x000, // 0x19e = 414 - NO_OP + 0x000, // 0x19f = 415 - NO_OP + 0x000, // 0x1a0 = 416 - NO_OP + 0x000, // 0x1a1 = 417 - NO_OP + 0x000, // 0x1a2 = 418 - NO_OP + 0x000, // 0x1a3 = 419 - NO_OP + 0x000, // 0x1a4 = 420 - NO_OP + 0x000, // 0x1a5 = 421 - NO_OP + 0x000, // 0x1a6 = 422 - NO_OP + 0x000, // 0x1a7 = 423 - NO_OP + 0x000, // 0x1a8 = 424 - NO_OP + 0x000, // 0x1a9 = 425 - NO_OP + 0x000, // 0x1aa = 426 - NO_OP + 0x000, // 0x1ab = 427 - NO_OP + 0x000, // 0x1ac = 428 - NO_OP + 0x000, // 0x1ad = 429 - NO_OP + 0x000, // 0x1ae = 430 - NO_OP + 0x000, // 0x1af = 431 - NO_OP + 0x000, // 0x1b0 = 432 - NO_OP + 0x000, // 0x1b1 = 433 - NO_OP + 0x000, // 0x1b2 = 434 - NO_OP + 0x000, // 0x1b3 = 435 - NO_OP + 0x000, // 0x1b4 = 436 - NO_OP + 0x000, // 0x1b5 = 437 - NO_OP + 0x000, // 0x1b6 = 438 - NO_OP + 0x000, // 0x1b7 = 439 - NO_OP + 0x000, // 0x1b8 = 440 - NO_OP + 0x000, // 0x1b9 = 441 - NO_OP + 0x000, // 0x1ba = 442 - NO_OP + 0x000, // 0x1bb = 443 - NO_OP + 0x000, // 0x1bc = 444 - NO_OP + 0x000, // 0x1bd = 445 - NO_OP + 0x000, // 0x1be = 446 - NO_OP + 0x000, // 0x1bf = 447 - NO_OP + 0x000, // 0x1c0 = 448 - NO_OP + 0x000, // 0x1c1 = 449 - NO_OP + 0x000, // 0x1c2 = 450 - NO_OP + 0x000, // 0x1c3 = 451 - NO_OP + 0x000, // 0x1c4 = 452 - NO_OP + 0x000, // 0x1c5 = 453 - NO_OP + 0x000, // 0x1c6 = 454 - NO_OP + 0x000, // 0x1c7 = 455 - NO_OP + 0x000, // 0x1c8 = 456 - NO_OP + 0x000, // 0x1c9 = 457 - NO_OP + 0x000, // 0x1ca = 458 - NO_OP + 0x000, // 0x1cb = 459 - NO_OP + 0x000, // 0x1cc = 460 - NO_OP + 0x000, // 0x1cd = 461 - NO_OP + 0x000, // 0x1ce = 462 - NO_OP + 0x000, // 0x1cf = 463 - NO_OP + 0x000, // 0x1d0 = 464 - NO_OP + 0x000, // 0x1d1 = 465 - NO_OP + 0x000, // 0x1d2 = 466 - NO_OP + 0x000, // 0x1d3 = 467 - NO_OP + 0x000, // 0x1d4 = 468 - NO_OP + 0x000, // 0x1d5 = 469 - NO_OP + 0x000, // 0x1d6 = 470 - NO_OP + 0x000, // 0x1d7 = 471 - NO_OP + 0x000, // 0x1d8 = 472 - NO_OP + 0x000, // 0x1d9 = 473 - NO_OP + 0x000, // 0x1da = 474 - NO_OP + 0x000, // 0x1db = 475 - NO_OP + 0x000, // 0x1dc = 476 - NO_OP + 0x000, // 0x1dd = 477 - NO_OP + 0x000, // 0x1de = 478 - NO_OP + 0x000, // 0x1df = 479 - NO_OP + 0x000, // 0x1e0 = 480 - NO_OP + 0x000, // 0x1e1 = 481 - NO_OP + 0x000, // 0x1e2 = 482 - NO_OP + 0x000, // 0x1e3 = 483 - NO_OP + 0x000, // 0x1e4 = 484 - NO_OP + 0x000, // 0x1e5 = 485 - NO_OP + 0x000, // 0x1e6 = 486 - NO_OP + 0x000, // 0x1e7 = 487 - NO_OP + 0x000, // 0x1e8 = 488 - NO_OP + 0x000, // 0x1e9 = 489 - NO_OP + 0x000, // 0x1ea = 490 - NO_OP + 0x000, // 0x1eb = 491 - NO_OP + 0x000, // 0x1ec = 492 - NO_OP + 0x000, // 0x1ed = 493 - NO_OP + 0x000, // 0x1ee = 494 - NO_OP + 0x000, // 0x1ef = 495 - NO_OP + 0x000, // 0x1f0 = 496 - NO_OP + 0x000, // 0x1f1 = 497 - NO_OP + 0x000, // 0x1f2 = 498 - NO_OP + 0x000, // 0x1f3 = 499 - NO_OP + 0x000, // 0x1f4 = 500 - NO_OP + 0x000, // 0x1f5 = 501 - NO_OP + 0x000, // 0x1f6 = 502 - NO_OP + 0x000, // 0x1f7 = 503 - NO_OP + 0x000, // 0x1f8 = 504 - NO_OP + 0x000, // 0x1f9 = 505 - NO_OP + 0x000, // 0x1fa = 506 - NO_OP + 0x000, // 0x1fb = 507 - NO_OP + 0x000, // 0x1fc = 508 - NO_OP + 0x000, // 0x1fd = 509 - NO_OP + 0x000, // 0x1fe = 510 - NO_OP + 0x000, // 0x1ff = 511 - NO_OP +}; +/* 8/24/05 not worked */ +bit32 wcsImage0824[] = +{ +0x011, // 00000 = 0 - PHY_RESET_START +0x0ca, // 0x001 = 1 - JUMP_IF_PHY_READY +0x009, // 0x002 = 2 - +0x0ba, // 0x003 = 3 - JUMP_IF_HARD_RESET_PRIMITIVE +0x010, // 0x004 = 4 - +0x0bb, // 0x005 = 5 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x01e, // 0x006 = 6 - +0x0ff, // 0x007 = 7 - JUMP +0x001, // 0x008 = 8 - +0x010, // 0x009 = 9 - SEND_ID_FRAME +0x0ba, // 0x00a = 10 - JUMP_IF_HARD_RESET_PRIMITIVE +0x010, // 0x00b = 11 - +0x0bb, // 0x00c = 12 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x023, // 0x00d = 13 - +0x0ff, // 0x00e = 14 - JUMP +0x00a, // 0x00f = 15 - +0x033, // 0x010 = 16 - SOFT_RESET +0x011, // 0x011 = 17 - PHY_RESET_START +0x0ca, // 0x012 = 18 - JUMP_IF_PHY_READY +0x016, // 0x013 = 19 - +0x0bb, // 0x014 = 20 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x01b, // 0x015 = 21 - +0x010, // 0x016 = 22 - SEND_ID_FRAME +0x0bb, // 0x017 = 23 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x023, // 0x018 = 24 - +0x0ff, // 0x019 = 25 - JUMP +0x017, // 0x01a = 26 - +0x010, // 0x01b = 27 - SEND_ID_FRAME +0x0ff, // 0x01c = 28 - JUMP +0x023, // 0x01d = 29 - +0x0ca, // 0x01e = 30 - JUMP_IF_PHY_READY +0x022, // 0x01f = 31 - +0x0ff, // 0x020 = 32 - JUMP +0x01e, // 0x021 = 33 - +0x010, // 0x022 = 34 - SEND_ID_FRAME +0x000, // 0x023 = 35 - NO_OP +0x000, // 0x024 = 36 - NO_OP +0x000, // 0x025 = 37 - NO_OP +0x000, // 0x026 = 38 - NO_OP +0x000, // 0x027 = 39 - NO_OP +0x000, // 0x028 = 40 - NO_OP +0x0ff, // 0x029 = 41 - JUMP +0x11b, // 0x02a = 42 - +0x01b, // 0x02b = 43 - START_IT_NEXUS_LOSS_TIMER_SFO +0x017, // 0x02c = 44 - PATHWAY_BLOCKED_CNT_SFO_RESET +0x015, // 0x02d = 45 - NO_OP +0x07f, // 0x02e = 46 - NO_OP +0x001, // 0x02f = 47 - OPEN_REQUEST_SFO +0x000, // 0x030 = 48 - NO_OP +0x000, // 0x031 = 49 - NO_OP +0x000, // 0x032 = 50 - NO_OP +0x000, // 0x033 = 51 - NO_OP +0x000, // 0x034 = 52 - NO_OP +0x091, // 0x035 = 53 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_ACCEPT +0x057, // 0x036 = 54 - +0x097, // 0x037 = 55 - JUMP_IF_OPEN_STATUS_EQUAL_RATE_NOT_SUPPORTED +0x05a, // 0x038 = 56 - +0x09b, // 0x039 = 57 - JUMP_IF_OPEN_STATUS_EQUAL_PROTOCOL_NOT_SUPPORTED +0x05d, // 0x03a = 58 - +0x09d, // 0x03b = 59 - JUMP_IF_OPEN_STATUS_EQUAL_WRONG_DESTINATION +0x060, // 0x03c = 60 - +0x096, // 0x03d = 61 - JUMP_IF_OPEN_STATUS_EQUAL_BREAK_RECEIVED +0x063, // 0x03e = 62 - +0x095, // 0x03f = 63 - JUMP_IF_OPEN_STATUS_EQUAL_BAD_DESTINATION +0x066, // 0x040 = 64 - +0x0a1, // 0x041 = 65 - JUMP_IF_IT_NEXUS_LOSS_TIMEOUT_SFO +0x069, // 0x042 = 66 - +0x09c, // 0x043 = 67 - JUMP_IF_OPEN_STATUS_EQUAL_STP_RESOURCE_BUSY +0x02b, // 0x044 = 68 - +0x098, // 0x045 = 69 - JUMP_IF_OPEN_STATUS_EQUAL_NO_DESTINATION +0x11b, // 0x046 = 70 - +0x099, // 0x047 = 71 - JUMP_IF_OPEN_STATUS_EQUAL_PATHWAY_BLOCKED +0x06c, // 0x048 = 72 - +0x09a, // 0x049 = 73 - JUMP_IF_OPEN_STATUS_EQUAL_RETRY +0x02f, // 0x04a = 74 - +0x094, // 0x04b = 75 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_TIMEOUT +0x02f, // 0x04c = 76 - +0x0a7, // 0x04d = 77 - JUMP_IF_CONNECTION_OPEN_SLAVE_FLAG_SET +0x130, // 0x04e = 78 - +0x092, // 0x04f = 79 - JUMP_IF_OPEN_STATUS_EQUAL_OCSM_BUSY +0x02f, // 0x050 = 80 - +0x0ca, // 0x051 = 81 - JUMP_IF_PHY_READY +0x035, // 0x052 = 82 - +0x031, // 0x053 = 83 - SET_OPEN_STATUS_PHY_NOT_RDY_SFO +0x033, // 0x054 = 84 - SOFT_RESET +0x0ff, // 0x055 = 85 - JUMP +0x001, // 0x056 = 86 - +0x021, // 0x057 = 87 - SET_OPEN_STATUS_NORMAL_SFO +0x0ff, // 0x058 = 88 - JUMP +0x06f, // 0x059 = 89 - +0x025, // 0x05a = 90 - SET_OPEN_STATUS_BAD_RATE_SFO +0x0ff, // 0x05b = 91 - JUMP +0x11b, // 0x05c = 92 - +0x026, // 0x05d = 93 - SET_OPEN_STATUS_BAD_PROTOCOL_SFO +0x0ff, // 0x05e = 94 - JUMP +0x11b, // 0x05f = 95 - +0x028, // 0x060 = 96 - SET_OPEN_STATUS_WRONG_DEST_SFO +0x0ff, // 0x061 = 97 - JUMP +0x11b, // 0x062 = 98 - +0x024, // 0x063 = 99 - SET_OPEN_STATUS_BREAK_SFO +0x0ff, // 0x064 = 100 - JUMP +0x11b, // 0x065 = 101 - +0x023, // 0x066 = 102 - SET_OPEN_STATUS_BAD_DEST_SFO +0x0ff, // 0x067 = 103 - JUMP +0x11b, // 0x068 = 104 - +0x022, // 0x069 = 105 - SET_OPEN_STATUS_IT_NEXUS_LOSS_SFO +0x0ff, // 0x06a = 106 - JUMP +0x11b, // 0x06b = 107 - +0x019, // 0x06c = 108 - PATHWAY_BLOCKED_CNT_SFO_INC +0x0ff, // 0x06d = 109 - JUMP +0x02f, // 0x06e = 110 - +0x000, // 0x06f = 111 - NO_OP +0x0d4, // 0x070 = 112 - JUMP_IF_RX_BUFFER_FULL_TIMEOUT +0x09b, // 0x071 = 113 - +0x0aa, // 0x072 = 114 - JUMP_IF_SFO_TRANSMISSION_STATUS_EQUAL_GOOD +0x085, // 0x073 = 115 - +0x0ab, // 0x074 = 116 - JUMP_IF_SFO_TRANSMISSION_STATUS_EQUAL_NAK +0x089, // 0x075 = 117 - +0x0ac, // 0x076 = 118 - JUMP_IF_SFO_TRANSMISSION_STATUS_EQUAL_ACK_NAK_TIMEOUT +0x08c, // 0x077 = 119 - +0x0ad, // 0x078 = 120 - JUMP_IF_SFO_TRANSMISSION_STATUS_EQUAL_BREAK +0x092, // 0x079 = 121 - +0x0af, // 0x07a = 122 - JUMP_IF_SFO_TRANSMISSION_STATUS_EQUAL_CREDIT_TIMEOUT +0x08f, // 0x07b = 123 - +0x0ae, // 0x07c = 124 - JUMP_IF_SFO_TRANSMISSION_STATUS_EQUAL_UNEXPECTED_CLOSE +0x089, // 0x07d = 125 - +0x0d2, // 0x07e = 126 - JUMP_IF_SFO_TRANSMISSION_STATUS_EQUAL_SMP_ERR +0x098, // 0x07f = 127 - +0x0ca, // 0x080 = 128 - JUMP_IF_PHY_READY +0x070, // 0x081 = 129 - +0x033, // 0x082 = 130 - SOFT_RESET +0x0ff, // 0x083 = 131 - JUMP +0x001, // 0x084 = 132 - +0x0d0, // 0x085 = 133 - JUMP_IF_SMP_PROTOCOL +0x089, // 0x086 = 134 - +0x0ff, // 0x087 = 135 - JUMP +0x095, // 0x088 = 136 - +0x006, // 0x089 = 137 - CLOSE_NORMAL +0x0ff, // 0x08a = 138 - JUMP +0x092, // 0x08b = 139 - +0x007, // 0x08c = 140 - CLOSE_ACK_NAK_TIMEOUT +0x0ff, // 0x08d = 141 - JUMP +0x092, // 0x08e = 142 - +0x008, // 0x08f = 143 - CLOSE_CREDIT_TIMEOUT +0x0ff, // 0x090 = 144 - JUMP +0x092, // 0x091 = 145 - +0x034, // 0x092 = 146 - ADVANCE_SFO +0x0ff, // 0x093 = 147 - JUMP +0x15f, // 0x094 = 148 - +0x034, // 0x095 = 149 - ADVANCE_SFO +0x0ff, // 0x096 = 150 - JUMP +0x11b, // 0x097 = 151 - +0x034, // 0x098 = 152 - ADVANCE_SFO +0x0ff, // 0x099 = 153 - JUMP +0x16f, // 0x09a = 154 - +0x037, // 0x09b = 155 - SEND_CREDIT_BLOCK +0x0ff, // 0x09c = 156 - JUMP +0x072, // 0x09d = 157 - +0x01c, // 0x09e = 158 - START_IT_NEXUS_LOSS_TIMER_DOC +0x018, // 0x09f = 159 - PATHWAY_BLOCKED_CNT_DOC_RESET +0x016, // 0x0a0 = 160 - NO_OP +0x07f, // 0x0a1 = 161 - NO_OP +0x002, // 0x0a2 = 162 - OPEN_REQUEST_DOC +0x000, // 0x0a3 = 163 - NO_OP +0x000, // 0x0a4 = 164 - NO_OP +0x000, // 0x0a5 = 165 - NO_OP +0x000, // 0x0a6 = 166 - NO_OP +0x000, // 0x0a7 = 167 - NO_OP +0x091, // 0x0a8 = 168 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_ACCEPT +0x0ca, // 0x0a9 = 169 - +0x097, // 0x0aa = 170 - JUMP_IF_OPEN_STATUS_EQUAL_RATE_NOT_SUPPORTED +0x0cd, // 0x0ab = 171 - +0x09b, // 0x0ac = 172 - JUMP_IF_OPEN_STATUS_EQUAL_PROTOCOL_NOT_SUPPORTED +0x0d0, // 0x0ad = 173 - +0x09d, // 0x0ae = 174 - JUMP_IF_OPEN_STATUS_EQUAL_WRONG_DESTINATION +0x0d3, // 0x0af = 175 - +0x096, // 0x0b0 = 176 - JUMP_IF_OPEN_STATUS_EQUAL_BREAK_RECEIVED +0x0d6, // 0x0b1 = 177 - +0x095, // 0x0b2 = 178 - JUMP_IF_OPEN_STATUS_EQUAL_BAD_DESTINATION +0x0d9, // 0x0b3 = 179 - +0x0a2, // 0x0b4 = 180 - JUMP_IF_IT_NEXUS_LOSS_TIMEOUT_DOC +0x0dc, // 0x0b5 = 181 - +0x09c, // 0x0b6 = 182 - JUMP_IF_OPEN_STATUS_EQUAL_STP_RESOURCE_BUSY +0x09e, // 0x0b7 = 183 - +0x098, // 0x0b8 = 184 - JUMP_IF_OPEN_STATUS_EQUAL_NO_DESTINATION +0x11b, // 0x0b9 = 185 - +0x099, // 0x0ba = 186 - JUMP_IF_OPEN_STATUS_EQUAL_PATHWAY_BLOCKED +0x0df, // 0x0bb = 187 - +0x09a, // 0x0bc = 188 - JUMP_IF_OPEN_STATUS_EQUAL_RETRY +0x0a2, // 0x0bd = 189 - +0x094, // 0x0be = 190 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_TIMEOUT +0x0a2, // 0x0bf = 191 - +0x0a7, // 0x0c0 = 192 - JUMP_IF_CONNECTION_OPEN_SLAVE_FLAG_SET +0x142, // 0x0c1 = 193 - +0x092, // 0x0c2 = 194 - JUMP_IF_OPEN_STATUS_EQUAL_OCSM_BUSY +0x0a2, // 0x0c3 = 195 - +0x0ca, // 0x0c4 = 196 - JUMP_IF_PHY_READY +0x0a8, // 0x0c5 = 197 - +0x032, // 0x0c6 = 198 - SET_OPEN_STATUS_PHY_NOT_RDY_DOC +0x033, // 0x0c7 = 199 - SOFT_RESET +0x0ff, // 0x0c8 = 200 - JUMP +0x001, // 0x0c9 = 201 - +0x029, // 0x0ca = 202 - SET_OPEN_STATUS_NORMAL_DOC +0x0ff, // 0x0cb = 203 - JUMP +0x0e2, // 0x0cc = 204 - +0x02d, // 0x0cd = 205 - SET_OPEN_STATUS_BAD_RATE_DOC +0x0ff, // 0x0ce = 206 - JUMP +0x11b, // 0x0cf = 207 - +0x02e, // 0x0d0 = 208 - SET_OPEN_STATUS_BAD_PROTOCOL_DOC +0x0ff, // 0x0d1 = 209 - JUMP +0x11b, // 0x0d2 = 210 - +0x030, // 0x0d3 = 211 - SET_OPEN_STATUS_WRONG_DEST_DOC +0x0ff, // 0x0d4 = 212 - JUMP +0x11b, // 0x0d5 = 213 - +0x02c, // 0x0d6 = 214 - SET_OPEN_STATUS_BREAK_DOC +0x0ff, // 0x0d7 = 215 - JUMP +0x11b, // 0x0d8 = 216 - +0x02b, // 0x0d9 = 217 - SET_OPEN_STATUS_BAD_DEST_DOC +0x0ff, // 0x0da = 218 - JUMP +0x11b, // 0x0db = 219 - +0x02a, // 0x0dc = 220 - SET_OPEN_STATUS_IT_NEXUS_LOSS_DOC +0x0ff, // 0x0dd = 221 - JUMP +0x11b, // 0x0de = 222 - +0x01a, // 0x0df = 223 - PATHWAY_BLOCKED_CNT_DOC_INC +0x0ff, // 0x0e0 = 224 - JUMP +0x0a2, // 0x0e1 = 225 - +0x000, // 0x0e2 = 226 - NO_OP +0x0d4, // 0x0e3 = 227 - JUMP_IF_RX_BUFFER_FULL_TIMEOUT +0x118, // 0x0e4 = 228 - +0x0b1, // 0x0e5 = 229 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_GOOD +0x0fa, // 0x0e6 = 230 - +0x0b2, // 0x0e7 = 231 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_NAK +0x106, // 0x0e8 = 232 - +0x0b3, // 0x0e9 = 233 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_ACK_NAK_TIMEOUT +0x109, // 0x0ea = 234 - +0x0b4, // 0x0eb = 235 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_BREAK +0x10f, // 0x0ec = 236 - +0x0b6, // 0x0ed = 237 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_CREDIT_TIMEOUT +0x10c, // 0x0ee = 238 - +0x0b5, // 0x0ef = 239 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_UNEXPECTED_CLOSE +0x106, // 0x0f0 = 240 - +0x0d3, // 0x0f1 = 241 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_SMP_ERR +0x115, // 0x0f2 = 242 - +0x0d5, // 0x0f3 = 243 - JUMP_IF_DOC_CLOSE_REQ +0x15c, // 0x0f4 = 244 - +0x0ca, // 0x0f5 = 245 - JUMP_IF_PHY_READY +0x0fe, // 0x0f6 = 246 - +0x033, // 0x0f7 = 247 - SOFT_RESET +0x0ff, // 0x0f8 = 248 - JUMP +0x001, // 0x0f9 = 249 - +0x0d0, // 0x0fa = 250 - JUMP_IF_SMP_PROTOCOL +0x106, // 0x0fb = 251 - +0x0ff, // 0x0fc = 252 - JUMP +0x112, // 0x0fd = 253 - +0x0b7, // 0x0fe = 254 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_CREDIT_BLOCKED +0x106, // 0x0ff = 255 - +0x0b8, // 0x100 = 256 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_MAX_BURST_SIZE +0x106, // 0x101 = 257 - +0x0b9, // 0x102 = 258 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_MAX_CONNECTION_TIME +0x106, // 0x103 = 259 - +0x0ff, // 0x104 = 260 - JUMP +0x0e3, // 0x105 = 261 - +0x006, // 0x106 = 262 - CLOSE_NORMAL +0x0ff, // 0x107 = 263 - JUMP +0x10f, // 0x108 = 264 - +0x007, // 0x109 = 265 - CLOSE_ACK_NAK_TIMEOUT +0x0ff, // 0x10a = 266 - JUMP +0x10f, // 0x10b = 267 - +0x008, // 0x10c = 268 - CLOSE_CREDIT_TIMEOUT +0x0ff, // 0x10d = 269 - JUMP +0x10f, // 0x10e = 270 - +0x035, // 0x10f = 271 - ADVANCE_DOC +0x0ff, // 0x110 = 272 - JUMP +0x15f, // 0x111 = 273 - +0x035, // 0x112 = 274 - ADVANCE_DOC +0x0ff, // 0x113 = 275 - JUMP +0x11b, // 0x114 = 276 - +0x035, // 0x115 = 277 - ADVANCE_DOC +0x0ff, // 0x116 = 278 - JUMP +0x16f, // 0x117 = 279 - +0x037, // 0x118 = 280 - SEND_CREDIT_BLOCK +0x0ff, // 0x119 = 281 - JUMP +0x0e5, // 0x11a = 282 - +0x0a9, // 0x11b = 283 - JUMP_IF_SFO_REQ +0x126, // 0x11c = 284 - +0x0b0, // 0x11d = 285 - JUMP_IF_DOC_REQ +0x138, // 0x11e = 286 - +0x0a8, // 0x11f = 287 - JUMP_IF_CONNECTION_ACTIVE_SET +0x14a, // 0x120 = 288 - +0x0ca, // 0x121 = 289 - JUMP_IF_PHY_READY +0x11b, // 0x122 = 290 - +0x033, // 0x123 = 291 - SOFT_RESET +0x0ff, // 0x124 = 292 - JUMP +0x001, // 0x125 = 293 - +0x0ca, // 0x126 = 294 - JUMP_IF_PHY_READY +0x12c, // 0x127 = 295 - +0x031, // 0x128 = 296 - SET_OPEN_STATUS_PHY_NOT_RDY_SFO +0x033, // 0x129 = 297 - SOFT_RESET +0x0ff, // 0x12a = 298 - JUMP +0x001, // 0x12b = 299 - +0x0a8, // 0x12c = 300 - JUMP_IF_CONNECTION_ACTIVE_SET +0x130, // 0x12d = 301 - +0x0ff, // 0x12e = 302 - JUMP +0x02b, // 0x12f = 303 - +0x0a3, // 0x130 = 304 - JUMP_IF_CONNECTION_PROFILE_OPEN_EQUAL_SFO +0x134, // 0x131 = 305 - +0x0ff, // 0x132 = 306 - JUMP +0x11d, // 0x133 = 307 - +0x0c8, // 0x134 = 308 - JUMP_IF_BREAK_RECEIVED +0x16f, // 0x135 = 309 - +0x0ff, // 0x136 = 310 - JUMP +0x057, // 0x137 = 311 - +0x0ca, // 0x138 = 312 - JUMP_IF_PHY_READY +0x13e, // 0x139 = 313 - +0x032, // 0x13a = 314 - SET_OPEN_STATUS_PHY_NOT_RDY_DOC +0x033, // 0x13b = 315 - SOFT_RESET +0x0ff, // 0x13c = 316 - JUMP +0x001, // 0x13d = 317 - +0x0a8, // 0x13e = 318 - JUMP_IF_CONNECTION_ACTIVE_SET +0x142, // 0x13f = 319 - +0x0ff, // 0x140 = 320 - JUMP +0x09e, // 0x141 = 321 - +0x0a4, // 0x142 = 322 - JUMP_IF_CONNECTION_PROFILE_OPEN_EQUAL_DOC +0x146, // 0x143 = 323 - +0x0ff, // 0x144 = 324 - JUMP +0x11f, // 0x145 = 325 - +0x0c8, // 0x146 = 326 - JUMP_IF_BREAK_RECEIVED +0x16f, // 0x147 = 327 - +0x0ff, // 0x148 = 328 - JUMP +0x0ca, // 0x149 = 329 - +0x0d0, // 0x14a = 330 - JUMP_IF_SMP_PROTOCOL +0x155, // 0x14b = 331 - +0x0d4, // 0x14c = 332 - JUMP_IF_RX_BUFFER_FULL_TIMEOUT +0x159, // 0x14d = 333 - +0x0a6, // 0x14e = 334 - JUMP_IF_CONNECTION_OPEN_MASTER_FLAG_SET +0x152, // 0x14f = 335 - +0x0ff, // 0x150 = 336 - JUMP +0x177, // 0x151 = 337 - +0x006, // 0x152 = 338 - CLOSE_NORMAL +0x0ff, // 0x153 = 339 - JUMP +0x15f, // 0x154 = 340 - +0x0d1, // 0x155 = 341 - JUMP_IF_SMP_FRAME_ERR_RECEIVED +0x180, // 0x156 = 342 - +0x0ff, // 0x157 = 343 - JUMP +0x11b, // 0x158 = 344 - +0x037, // 0x159 = 345 - SEND_CREDIT_BLOCK +0x0ff, // 0x15a = 346 - JUMP +0x14e, // 0x15b = 347 - +0x0c8, // 0x15c = 348 - JUMP_IF_BREAK_RECEIVED +0x16f, // 0x15d = 349 - +0x006, // 0x15e = 350 - CLOSE_NORMAL +0x000, // 0x15f = 351 - NO_OP +0x000, // 0x160 = 352 - NO_OP +0x000, // 0x161 = 353 - NO_OP +0x000, // 0x162 = 354 - NO_OP +0x000, // 0x163 = 355 - NO_OP +0x0d4, // 0x164 = 356 - JUMP_IF_RX_BUFFER_FULL_TIMEOUT +0x174, // 0x165 = 357 - +0x0cd, // 0x166 = 358 - JUMP_IF_CLOSE_STATUS_EQUAL_ANY +0x11b, // 0x167 = 359 - +0x0c8, // 0x168 = 360 - JUMP_IF_BREAK_RECEIVED +0x16f, // 0x169 = 361 - +0x0ca, // 0x16a = 362 - JUMP_IF_PHY_READY +0x15f, // 0x16b = 363 - +0x033, // 0x16c = 364 - SOFT_RESET +0x0ff, // 0x16d = 365 - JUMP +0x001, // 0x16e = 366 - +0x009, // 0x16f = 367 - CLOSE_BREAK +0x0a8, // 0x170 = 368 - JUMP_IF_CONNECTION_ACTIVE_SET +0x170, // 0x171 = 369 - +0x0ff, // 0x172 = 370 - JUMP +0x11b, // 0x173 = 371 - +0x037, // 0x174 = 372 - SEND_CREDIT_BLOCK +0x0ff, // 0x175 = 373 - JUMP +0x166, // 0x176 = 374 - +0x0c8, // 0x177 = 375 - JUMP_IF_BREAK_RECEIVED +0x180, // 0x178 = 376 - +0x0ce, // 0x179 = 377 - JUMP_IF_ANY_DONE_RECEIVED +0x185, // 0x17a = 378 - +0x0ca, // 0x17b = 379 - JUMP_IF_PHY_READY +0x11b, // 0x17c = 380 - +0x033, // 0x17d = 381 - SOFT_RESET +0x0ff, // 0x17e = 382 - JUMP +0x11b, // 0x17f = 383 - +0x009, // 0x180 = 384 - CLOSE_BREAK +0x0a8, // 0x181 = 385 - JUMP_IF_CONNECTION_ACTIVE_SET +0x181, // 0x182 = 386 - +0x0ff, // 0x183 = 387 - JUMP +0x11b, // 0x184 = 388 - +0x006, // 0x185 = 389 - CLOSE_NORMAL +0x000, // 0x186 = 390 - NO_OP +0x000, // 0x187 = 391 - NO_OP +0x000, // 0x188 = 392 - NO_OP +0x000, // 0x189 = 393 - NO_OP +0x000, // 0x18a = 394 - NO_OP +0x0cd, // 0x18b = 395 - JUMP_IF_CLOSE_STATUS_EQUAL_ANY +0x11b, // 0x18c = 396 - +0x0d4, // 0x18d = 397 - JUMP_IF_RX_BUFFER_FULL_TIMEOUT +0x196, // 0x18e = 398 - +0x0c8, // 0x18f = 399 - JUMP_IF_BREAK_RECEIVED +0x180, // 0x190 = 400 - +0x0ca, // 0x191 = 401 - JUMP_IF_PHY_READY +0x18b, // 0x192 = 402 - +0x033, // 0x193 = 403 - SOFT_RESET +0x0ff, // 0x194 = 404 - JUMP +0x001, // 0x195 = 405 - +0x037, // 0x196 = 406 - SEND_CREDIT_BLOCK +0x0ff, // 0x197 = 407 - JUMP +0x18f, // 0x198 = 408 - +0x000, // 0x199 = 409 - NO_OP +0x000, // 0x19a = 410 - NO_OP +0x000, // 0x19b = 411 - NO_OP +0x000, // 0x19c = 412 - NO_OP +0x000, // 0x19d = 413 - NO_OP +0x000, // 0x19e = 414 - NO_OP +0x000, // 0x19f = 415 - NO_OP +0x000, // 0x1a0 = 416 - NO_OP +0x000, // 0x1a1 = 417 - NO_OP +0x000, // 0x1a2 = 418 - NO_OP +0x000, // 0x1a3 = 419 - NO_OP +0x000, // 0x1a4 = 420 - NO_OP +0x000, // 0x1a5 = 421 - NO_OP +0x000, // 0x1a6 = 422 - NO_OP +0x000, // 0x1a7 = 423 - NO_OP +0x000, // 0x1a8 = 424 - NO_OP +0x000, // 0x1a9 = 425 - NO_OP +0x000, // 0x1aa = 426 - NO_OP +0x000, // 0x1ab = 427 - NO_OP +0x000, // 0x1ac = 428 - NO_OP +0x000, // 0x1ad = 429 - NO_OP +0x000, // 0x1ae = 430 - NO_OP +0x000, // 0x1af = 431 - NO_OP +0x000, // 0x1b0 = 432 - NO_OP +0x000, // 0x1b1 = 433 - NO_OP +0x000, // 0x1b2 = 434 - NO_OP +0x000, // 0x1b3 = 435 - NO_OP +0x000, // 0x1b4 = 436 - NO_OP +0x000, // 0x1b5 = 437 - NO_OP +0x000, // 0x1b6 = 438 - NO_OP +0x000, // 0x1b7 = 439 - NO_OP +0x000, // 0x1b8 = 440 - NO_OP +0x000, // 0x1b9 = 441 - NO_OP +0x000, // 0x1ba = 442 - NO_OP +0x000, // 0x1bb = 443 - NO_OP +0x000, // 0x1bc = 444 - NO_OP +0x000, // 0x1bd = 445 - NO_OP +0x000, // 0x1be = 446 - NO_OP +0x000, // 0x1bf = 447 - NO_OP +0x000, // 0x1c0 = 448 - NO_OP +0x000, // 0x1c1 = 449 - NO_OP +0x000, // 0x1c2 = 450 - NO_OP +0x000, // 0x1c3 = 451 - NO_OP +0x000, // 0x1c4 = 452 - NO_OP +0x000, // 0x1c5 = 453 - NO_OP +0x000, // 0x1c6 = 454 - NO_OP +0x000, // 0x1c7 = 455 - NO_OP +0x000, // 0x1c8 = 456 - NO_OP +0x000, // 0x1c9 = 457 - NO_OP +0x000, // 0x1ca = 458 - NO_OP +0x000, // 0x1cb = 459 - NO_OP +0x000, // 0x1cc = 460 - NO_OP +0x000, // 0x1cd = 461 - NO_OP +0x000, // 0x1ce = 462 - NO_OP +0x000, // 0x1cf = 463 - NO_OP +0x000, // 0x1d0 = 464 - NO_OP +0x000, // 0x1d1 = 465 - NO_OP +0x000, // 0x1d2 = 466 - NO_OP +0x000, // 0x1d3 = 467 - NO_OP +0x000, // 0x1d4 = 468 - NO_OP +0x000, // 0x1d5 = 469 - NO_OP +0x000, // 0x1d6 = 470 - NO_OP +0x000, // 0x1d7 = 471 - NO_OP +0x000, // 0x1d8 = 472 - NO_OP +0x000, // 0x1d9 = 473 - NO_OP +0x000, // 0x1da = 474 - NO_OP +0x000, // 0x1db = 475 - NO_OP +0x000, // 0x1dc = 476 - NO_OP +0x000, // 0x1dd = 477 - NO_OP +0x000, // 0x1de = 478 - NO_OP +0x000, // 0x1df = 479 - NO_OP +0x000, // 0x1e0 = 480 - NO_OP +0x000, // 0x1e1 = 481 - NO_OP +0x000, // 0x1e2 = 482 - NO_OP +0x000, // 0x1e3 = 483 - NO_OP +0x000, // 0x1e4 = 484 - NO_OP +0x000, // 0x1e5 = 485 - NO_OP +0x000, // 0x1e6 = 486 - NO_OP +0x000, // 0x1e7 = 487 - NO_OP +0x000, // 0x1e8 = 488 - NO_OP +0x000, // 0x1e9 = 489 - NO_OP +0x000, // 0x1ea = 490 - NO_OP +0x000, // 0x1eb = 491 - NO_OP +0x000, // 0x1ec = 492 - NO_OP +0x000, // 0x1ed = 493 - NO_OP +0x000, // 0x1ee = 494 - NO_OP +0x000, // 0x1ef = 495 - NO_OP +0x000, // 0x1f0 = 496 - NO_OP +0x000, // 0x1f1 = 497 - NO_OP +0x000, // 0x1f2 = 498 - NO_OP +0x000, // 0x1f3 = 499 - NO_OP +0x000, // 0x1f4 = 500 - NO_OP +0x000, // 0x1f5 = 501 - NO_OP +0x000, // 0x1f6 = 502 - NO_OP +0x000, // 0x1f7 = 503 - NO_OP +0x000, // 0x1f8 = 504 - NO_OP +0x000, // 0x1f9 = 505 - NO_OP +0x000, // 0x1fa = 506 - NO_OP +0x000, // 0x1fb = 507 - NO_OP +0x000, // 0x1fc = 508 - NO_OP +0x000, // 0x1fd = 509 - NO_OP +0x000, // 0x1fe = 510 - NO_OP +0x000, // 0x1ff = 511 - NO_OP +}; + + +/* as of 8/23/05 and worked, used for Houston demo, bitmap0822 */ +bit32 wcsImage0822[] = +{ +0x011, // 00000 = 0 - PHY_RESET_START +0x0ca, // 0x001 = 1 - JUMP_IF_PHY_READY +0x009, // 0x002 = 2 - +0x0ba, // 0x003 = 3 - JUMP_IF_HARD_RESET_PRIMITIVE +0x010, // 0x004 = 4 - +0x0bb, // 0x005 = 5 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x01e, // 0x006 = 6 - +0x0ff, // 0x007 = 7 - JUMP +0x001, // 0x008 = 8 - +0x010, // 0x009 = 9 - SEND_ID_FRAME +0x0ba, // 0x00a = 10 - JUMP_IF_HARD_RESET_PRIMITIVE +0x010, // 0x00b = 11 - +0x0bb, // 0x00c = 12 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x023, // 0x00d = 13 - +0x0ff, // 0x00e = 14 - JUMP +0x00a, // 0x00f = 15 - +0x033, // 0x010 = 16 - SOFT_RESET +0x011, // 0x011 = 17 - PHY_RESET_START +0x0ca, // 0x012 = 18 - JUMP_IF_PHY_READY +0x016, // 0x013 = 19 - +0x0bb, // 0x014 = 20 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x01b, // 0x015 = 21 - +0x010, // 0x016 = 22 - SEND_ID_FRAME +0x0bb, // 0x017 = 23 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x023, // 0x018 = 24 - +0x0ff, // 0x019 = 25 - JUMP +0x017, // 0x01a = 26 - +0x010, // 0x01b = 27 - SEND_ID_FRAME +0x0ff, // 0x01c = 28 - JUMP +0x023, // 0x01d = 29 - +0x0ca, // 0x01e = 30 - JUMP_IF_PHY_READY +0x022, // 0x01f = 31 - +0x0ff, // 0x020 = 32 - JUMP +0x01e, // 0x021 = 33 - +0x010, // 0x022 = 34 - SEND_ID_FRAME +0x000, // 0x023 = 35 - NO_OP +0x000, // 0x024 = 36 - NO_OP +0x000, // 0x025 = 37 - NO_OP +0x000, // 0x026 = 38 - NO_OP +0x000, // 0x027 = 39 - NO_OP +0x000, // 0x028 = 40 - NO_OP +0x0ff, // 0x029 = 41 - JUMP +0x112, // 0x02a = 42 - +0x01b, // 0x02b = 43 - START_IT_NEXUS_LOSS_TIMER_SFO +0x017, // 0x02c = 44 - PATHWAY_BLOCKED_CNT_SFO_RESET +0x013, // 0x02d = 45 - START_ARB_WAIT_TIMER_SFO +0x001, // 0x02e = 46 - OPEN_REQUEST_SFO +0x000, // 0x02f = 47 - NO_OP +0x000, // 0x030 = 48 - NO_OP +0x000, // 0x031 = 49 - NO_OP +0x000, // 0x032 = 50 - NO_OP +0x000, // 0x033 = 51 - NO_OP +0x091, // 0x034 = 52 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_ACCEPT +0x056, // 0x035 = 53 - +0x097, // 0x036 = 54 - JUMP_IF_OPEN_STATUS_EQUAL_RATE_NOT_SUPPORTED +0x059, // 0x037 = 55 - +0x09b, // 0x038 = 56 - JUMP_IF_OPEN_STATUS_EQUAL_PROTOCOL_NOT_SUPPORTED +0x05c, // 0x039 = 57 - +0x09d, // 0x03a = 58 - JUMP_IF_OPEN_STATUS_EQUAL_WRONG_DESTINATION +0x05f, // 0x03b = 59 - +0x096, // 0x03c = 60 - JUMP_IF_OPEN_STATUS_EQUAL_BREAK_RECEIVED +0x062, // 0x03d = 61 - +0x095, // 0x03e = 62 - JUMP_IF_OPEN_STATUS_EQUAL_BAD_DESTINATION +0x065, // 0x03f = 63 - +0x0a1, // 0x040 = 64 - JUMP_IF_IT_NEXUS_LOSS_TIMEOUT_SFO +0x068, // 0x041 = 65 - +0x09c, // 0x042 = 66 - JUMP_IF_OPEN_STATUS_EQUAL_STP_RESOURCE_BUSY +0x02b, // 0x043 = 67 - +0x098, // 0x044 = 68 - JUMP_IF_OPEN_STATUS_EQUAL_NO_DESTINATION +0x112, // 0x045 = 69 - +0x099, // 0x046 = 70 - JUMP_IF_OPEN_STATUS_EQUAL_PATHWAY_BLOCKED +0x06b, // 0x047 = 71 - +0x09a, // 0x048 = 72 - JUMP_IF_OPEN_STATUS_EQUAL_RETRY +0x02e, // 0x049 = 73 - +0x094, // 0x04a = 74 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_TIMEOUT +0x02e, // 0x04b = 75 - +0x0a7, // 0x04c = 76 - JUMP_IF_CONNECTION_OPEN_SLAVE_FLAG_SET +0x127, // 0x04d = 77 - +0x092, // 0x04e = 78 - JUMP_IF_OPEN_STATUS_EQUAL_OCSM_BUSY +0x02e, // 0x04f = 79 - +0x0ca, // 0x050 = 80 - JUMP_IF_PHY_READY +0x034, // 0x051 = 81 - +0x031, // 0x052 = 82 - SET_OPEN_STATUS_PHY_NOT_RDY_SFO +0x033, // 0x053 = 83 - SOFT_RESET +0x0ff, // 0x054 = 84 - JUMP +0x001, // 0x055 = 85 - +0x021, // 0x056 = 86 - SET_OPEN_STATUS_NORMAL_SFO +0x0ff, // 0x057 = 87 - JUMP +0x06e, // 0x058 = 88 - +0x025, // 0x059 = 89 - SET_OPEN_STATUS_BAD_RATE_SFO +0x0ff, // 0x05a = 90 - JUMP +0x112, // 0x05b = 91 - +0x026, // 0x05c = 92 - SET_OPEN_STATUS_BAD_PROTOCOL_SFO +0x0ff, // 0x05d = 93 - JUMP +0x112, // 0x05e = 94 - +0x028, // 0x05f = 95 - SET_OPEN_STATUS_WRONG_DEST_SFO +0x0ff, // 0x060 = 96 - JUMP +0x112, // 0x061 = 97 - +0x024, // 0x062 = 98 - SET_OPEN_STATUS_BREAK_SFO +0x0ff, // 0x063 = 99 - JUMP +0x112, // 0x064 = 100 - +0x023, // 0x065 = 101 - SET_OPEN_STATUS_BAD_DEST_SFO +0x0ff, // 0x066 = 102 - JUMP +0x112, // 0x067 = 103 - +0x022, // 0x068 = 104 - SET_OPEN_STATUS_IT_NEXUS_LOSS_SFO +0x0ff, // 0x069 = 105 - JUMP +0x112, // 0x06a = 106 - +0x019, // 0x06b = 107 - PATHWAY_BLOCKED_CNT_SFO_INC +0x0ff, // 0x06c = 108 - JUMP +0x02e, // 0x06d = 109 - +0x000, // 0x06e = 110 - NO_OP +0x0d4, // 0x06f = 111 - JUMP_IF_RX_BUFFER_FULL_TIMEOUT +0x093, // 0x070 = 112 - +0x0aa, // 0x071 = 113 - JUMP_IF_SFO_TRANSMISSION_STATUS_EQUAL_GOOD +0x084, // 0x072 = 114 - +0x0ab, // 0x073 = 115 - JUMP_IF_SFO_TRANSMISSION_STATUS_EQUAL_NAK +0x084, // 0x074 = 116 - +0x0ac, // 0x075 = 117 - JUMP_IF_SFO_TRANSMISSION_STATUS_EQUAL_ACK_NAK_TIMEOUT +0x087, // 0x076 = 118 - +0x0ad, // 0x077 = 119 - JUMP_IF_SFO_TRANSMISSION_STATUS_EQUAL_BREAK +0x08d, // 0x078 = 120 - +0x0af, // 0x079 = 121 - JUMP_IF_SFO_TRANSMISSION_STATUS_EQUAL_CREDIT_TIMEOUT +0x08a, // 0x07a = 122 - +0x0ae, // 0x07b = 123 - JUMP_IF_SFO_TRANSMISSION_STATUS_EQUAL_UNEXPECTED_CLOSE +0x084, // 0x07c = 124 - +0x0d2, // 0x07d = 125 - JUMP_IF_SFO_TRANSMISSION_STATUS_EQUAL_SMP_ERR +0x090, // 0x07e = 126 - +0x0ca, // 0x07f = 127 - JUMP_IF_PHY_READY +0x06f, // 0x080 = 128 - +0x033, // 0x081 = 129 - SOFT_RESET +0x0ff, // 0x082 = 130 - JUMP +0x001, // 0x083 = 131 - +0x006, // 0x084 = 132 - CLOSE_NORMAL +0x0ff, // 0x085 = 133 - JUMP +0x08d, // 0x086 = 134 - +0x007, // 0x087 = 135 - CLOSE_ACK_NAK_TIMEOUT +0x0ff, // 0x088 = 136 - JUMP +0x08d, // 0x089 = 137 - +0x008, // 0x08a = 138 - CLOSE_CREDIT_TIMEOUT +0x0ff, // 0x08b = 139 - JUMP +0x08d, // 0x08c = 140 - +0x034, // 0x08d = 141 - ADVANCE_SFO +0x0ff, // 0x08e = 142 - JUMP +0x156, // 0x08f = 143 - +0x034, // 0x090 = 144 - ADVANCE_SFO +0x0ff, // 0x091 = 145 - JUMP +0x166, // 0x092 = 146 - +0x037, // 0x093 = 147 - SEND_CREDIT_BLOCK +0x0ff, // 0x094 = 148 - JUMP +0x071, // 0x095 = 149 - +0x01c, // 0x096 = 150 - START_IT_NEXUS_LOSS_TIMER_DOC +0x018, // 0x097 = 151 - PATHWAY_BLOCKED_CNT_DOC_RESET +0x014, // 0x098 = 152 - START_ARB_WAIT_TIMER_DOC +0x002, // 0x099 = 153 - OPEN_REQUEST_DOC +0x000, // 0x09a = 154 - NO_OP +0x000, // 0x09b = 155 - NO_OP +0x000, // 0x09c = 156 - NO_OP +0x000, // 0x09d = 157 - NO_OP +0x000, // 0x09e = 158 - NO_OP +0x091, // 0x09f = 159 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_ACCEPT +0x0c1, // 0x0a0 = 160 - +0x097, // 0x0a1 = 161 - JUMP_IF_OPEN_STATUS_EQUAL_RATE_NOT_SUPPORTED +0x0c4, // 0x0a2 = 162 - +0x09b, // 0x0a3 = 163 - JUMP_IF_OPEN_STATUS_EQUAL_PROTOCOL_NOT_SUPPORTED +0x0c7, // 0x0a4 = 164 - +0x09d, // 0x0a5 = 165 - JUMP_IF_OPEN_STATUS_EQUAL_WRONG_DESTINATION +0x0ca, // 0x0a6 = 166 - +0x096, // 0x0a7 = 167 - JUMP_IF_OPEN_STATUS_EQUAL_BREAK_RECEIVED +0x0cd, // 0x0a8 = 168 - +0x095, // 0x0a9 = 169 - JUMP_IF_OPEN_STATUS_EQUAL_BAD_DESTINATION +0x0d0, // 0x0aa = 170 - +0x0a2, // 0x0ab = 171 - JUMP_IF_IT_NEXUS_LOSS_TIMEOUT_DOC +0x0d3, // 0x0ac = 172 - +0x09c, // 0x0ad = 173 - JUMP_IF_OPEN_STATUS_EQUAL_STP_RESOURCE_BUSY +0x096, // 0x0ae = 174 - +0x098, // 0x0af = 175 - JUMP_IF_OPEN_STATUS_EQUAL_NO_DESTINATION +0x112, // 0x0b0 = 176 - +0x099, // 0x0b1 = 177 - JUMP_IF_OPEN_STATUS_EQUAL_PATHWAY_BLOCKED +0x0d6, // 0x0b2 = 178 - +0x09a, // 0x0b3 = 179 - JUMP_IF_OPEN_STATUS_EQUAL_RETRY +0x099, // 0x0b4 = 180 - +0x094, // 0x0b5 = 181 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_TIMEOUT +0x099, // 0x0b6 = 182 - +0x0a7, // 0x0b7 = 183 - JUMP_IF_CONNECTION_OPEN_SLAVE_FLAG_SET +0x139, // 0x0b8 = 184 - +0x092, // 0x0b9 = 185 - JUMP_IF_OPEN_STATUS_EQUAL_OCSM_BUSY +0x099, // 0x0ba = 186 - +0x0ca, // 0x0bb = 187 - JUMP_IF_PHY_READY +0x09f, // 0x0bc = 188 - +0x032, // 0x0bd = 189 - SET_OPEN_STATUS_PHY_NOT_RDY_DOC +0x033, // 0x0be = 190 - SOFT_RESET +0x0ff, // 0x0bf = 191 - JUMP +0x001, // 0x0c0 = 192 - +0x029, // 0x0c1 = 193 - SET_OPEN_STATUS_NORMAL_DOC +0x0ff, // 0x0c2 = 194 - JUMP +0x0d9, // 0x0c3 = 195 - +0x02d, // 0x0c4 = 196 - SET_OPEN_STATUS_BAD_RATE_DOC +0x0ff, // 0x0c5 = 197 - JUMP +0x112, // 0x0c6 = 198 - +0x02e, // 0x0c7 = 199 - SET_OPEN_STATUS_BAD_PROTOCOL_DOC +0x0ff, // 0x0c8 = 200 - JUMP +0x112, // 0x0c9 = 201 - +0x030, // 0x0ca = 202 - SET_OPEN_STATUS_WRONG_DEST_DOC +0x0ff, // 0x0cb = 203 - JUMP +0x112, // 0x0cc = 204 - +0x02c, // 0x0cd = 205 - SET_OPEN_STATUS_BREAK_DOC +0x0ff, // 0x0ce = 206 - JUMP +0x112, // 0x0cf = 207 - +0x02b, // 0x0d0 = 208 - SET_OPEN_STATUS_BAD_DEST_DOC +0x0ff, // 0x0d1 = 209 - JUMP +0x112, // 0x0d2 = 210 - +0x02a, // 0x0d3 = 211 - SET_OPEN_STATUS_IT_NEXUS_LOSS_DOC +0x0ff, // 0x0d4 = 212 - JUMP +0x112, // 0x0d5 = 213 - +0x01a, // 0x0d6 = 214 - PATHWAY_BLOCKED_CNT_DOC_INC +0x0ff, // 0x0d7 = 215 - JUMP +0x099, // 0x0d8 = 216 - +0x000, // 0x0d9 = 217 - NO_OP +0x0d4, // 0x0da = 218 - JUMP_IF_RX_BUFFER_FULL_TIMEOUT +0x10f, // 0x0db = 219 - +0x0b1, // 0x0dc = 220 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_GOOD +0x0f1, // 0x0dd = 221 - +0x0b2, // 0x0de = 222 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_NAK +0x0fd, // 0x0df = 223 - +0x0b3, // 0x0e0 = 224 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_ACK_NAK_TIMEOUT +0x100, // 0x0e1 = 225 - +0x0b4, // 0x0e2 = 226 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_BREAK +0x106, // 0x0e3 = 227 - +0x0b6, // 0x0e4 = 228 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_CREDIT_TIMEOUT +0x103, // 0x0e5 = 229 - +0x0b5, // 0x0e6 = 230 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_UNEXPECTED_CLOSE +0x0fd, // 0x0e7 = 231 - +0x0d3, // 0x0e8 = 232 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_SMP_ERR +0x10c, // 0x0e9 = 233 - +0x0d5, // 0x0ea = 234 - JUMP_IF_DOC_CLOSE_REQ +0x153, // 0x0eb = 235 - +0x0ca, // 0x0ec = 236 - JUMP_IF_PHY_READY +0x0f5, // 0x0ed = 237 - +0x033, // 0x0ee = 238 - SOFT_RESET +0x0ff, // 0x0ef = 239 - JUMP +0x001, // 0x0f0 = 240 - +0x0d0, // 0x0f1 = 241 - JUMP_IF_SMP_PROTOCOL +0x0fd, // 0x0f2 = 242 - +0x0ff, // 0x0f3 = 243 - JUMP +0x109, // 0x0f4 = 244 - +0x0b7, // 0x0f5 = 245 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_CREDIT_BLOCKED +0x0fd, // 0x0f6 = 246 - +0x0b8, // 0x0f7 = 247 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_MAX_BURST_SIZE +0x0fd, // 0x0f8 = 248 - +0x0b9, // 0x0f9 = 249 - JUMP_IF_DOC_TRANSMISSION_STATUS_EQUAL_MAX_CONNECTION_TIME +0x0fd, // 0x0fa = 250 - +0x0ff, // 0x0fb = 251 - JUMP +0x0da, // 0x0fc = 252 - +0x006, // 0x0fd = 253 - CLOSE_NORMAL +0x0ff, // 0x0fe = 254 - JUMP +0x106, // 0x0ff = 255 - +0x007, // 0x100 = 256 - CLOSE_ACK_NAK_TIMEOUT +0x0ff, // 0x101 = 257 - JUMP +0x106, // 0x102 = 258 - +0x008, // 0x103 = 259 - CLOSE_CREDIT_TIMEOUT +0x0ff, // 0x104 = 260 - JUMP +0x106, // 0x105 = 261 - +0x035, // 0x106 = 262 - ADVANCE_DOC +0x0ff, // 0x107 = 263 - JUMP +0x156, // 0x108 = 264 - +0x035, // 0x109 = 265 - ADVANCE_DOC +0x0ff, // 0x10a = 266 - JUMP +0x112, // 0x10b = 267 - +0x035, // 0x10c = 268 - ADVANCE_DOC +0x0ff, // 0x10d = 269 - JUMP +0x166, // 0x10e = 270 - +0x037, // 0x10f = 271 - SEND_CREDIT_BLOCK +0x0ff, // 0x110 = 272 - JUMP +0x0dc, // 0x111 = 273 - +0x0a9, // 0x112 = 274 - JUMP_IF_SFO_REQ +0x11d, // 0x113 = 275 - +0x0b0, // 0x114 = 276 - JUMP_IF_DOC_REQ +0x12f, // 0x115 = 277 - +0x0a8, // 0x116 = 278 - JUMP_IF_CONNECTION_ACTIVE_SET +0x141, // 0x117 = 279 - +0x0ca, // 0x118 = 280 - JUMP_IF_PHY_READY +0x112, // 0x119 = 281 - +0x033, // 0x11a = 282 - SOFT_RESET +0x0ff, // 0x11b = 283 - JUMP +0x001, // 0x11c = 284 - +0x0ca, // 0x11d = 285 - JUMP_IF_PHY_READY +0x123, // 0x11e = 286 - +0x031, // 0x11f = 287 - SET_OPEN_STATUS_PHY_NOT_RDY_SFO +0x033, // 0x120 = 288 - SOFT_RESET +0x0ff, // 0x121 = 289 - JUMP +0x001, // 0x122 = 290 - +0x0a8, // 0x123 = 291 - JUMP_IF_CONNECTION_ACTIVE_SET +0x127, // 0x124 = 292 - +0x0ff, // 0x125 = 293 - JUMP +0x02b, // 0x126 = 294 - +0x0a3, // 0x127 = 295 - JUMP_IF_CONNECTION_PROFILE_OPEN_EQUAL_SFO +0x12b, // 0x128 = 296 - +0x0ff, // 0x129 = 297 - JUMP +0x114, // 0x12a = 298 - +0x0c8, // 0x12b = 299 - JUMP_IF_BREAK_RECEIVED +0x166, // 0x12c = 300 - +0x0ff, // 0x12d = 301 - JUMP +0x056, // 0x12e = 302 - +0x0ca, // 0x12f = 303 - JUMP_IF_PHY_READY +0x135, // 0x130 = 304 - +0x032, // 0x131 = 305 - SET_OPEN_STATUS_PHY_NOT_RDY_DOC +0x033, // 0x132 = 306 - SOFT_RESET +0x0ff, // 0x133 = 307 - JUMP +0x001, // 0x134 = 308 - +0x0a8, // 0x135 = 309 - JUMP_IF_CONNECTION_ACTIVE_SET +0x139, // 0x136 = 310 - +0x0ff, // 0x137 = 311 - JUMP +0x096, // 0x138 = 312 - +0x0a4, // 0x139 = 313 - JUMP_IF_CONNECTION_PROFILE_OPEN_EQUAL_DOC +0x13d, // 0x13a = 314 - +0x0ff, // 0x13b = 315 - JUMP +0x116, // 0x13c = 316 - +0x0c8, // 0x13d = 317 - JUMP_IF_BREAK_RECEIVED +0x166, // 0x13e = 318 - +0x0ff, // 0x13f = 319 - JUMP +0x0c1, // 0x140 = 320 - +0x0d0, // 0x141 = 321 - JUMP_IF_SMP_PROTOCOL +0x14c, // 0x142 = 322 - +0x0d4, // 0x143 = 323 - JUMP_IF_RX_BUFFER_FULL_TIMEOUT +0x150, // 0x144 = 324 - +0x0a6, // 0x145 = 325 - JUMP_IF_CONNECTION_OPEN_MASTER_FLAG_SET +0x149, // 0x146 = 326 - +0x0ff, // 0x147 = 327 - JUMP +0x16e, // 0x148 = 328 - +0x006, // 0x149 = 329 - CLOSE_NORMAL +0x0ff, // 0x14a = 330 - JUMP +0x156, // 0x14b = 331 - +0x0d1, // 0x14c = 332 - JUMP_IF_SMP_FRAME_ERR_RECEIVED +0x177, // 0x14d = 333 - +0x0ff, // 0x14e = 334 - JUMP +0x112, // 0x14f = 335 - +0x037, // 0x150 = 336 - SEND_CREDIT_BLOCK +0x0ff, // 0x151 = 337 - JUMP +0x145, // 0x152 = 338 - +0x0c8, // 0x153 = 339 - JUMP_IF_BREAK_RECEIVED +0x166, // 0x154 = 340 - +0x006, // 0x155 = 341 - CLOSE_NORMAL +0x000, // 0x156 = 342 - NO_OP +0x000, // 0x157 = 343 - NO_OP +0x000, // 0x158 = 344 - NO_OP +0x000, // 0x159 = 345 - NO_OP +0x000, // 0x15a = 346 - NO_OP +0x0d4, // 0x15b = 347 - JUMP_IF_RX_BUFFER_FULL_TIMEOUT +0x16b, // 0x15c = 348 - +0x0cd, // 0x15d = 349 - JUMP_IF_CLOSE_STATUS_EQUAL_ANY +0x112, // 0x15e = 350 - +0x0c8, // 0x15f = 351 - JUMP_IF_BREAK_RECEIVED +0x166, // 0x160 = 352 - +0x0ca, // 0x161 = 353 - JUMP_IF_PHY_READY +0x156, // 0x162 = 354 - +0x033, // 0x163 = 355 - SOFT_RESET +0x0ff, // 0x164 = 356 - JUMP +0x001, // 0x165 = 357 - +0x009, // 0x166 = 358 - CLOSE_BREAK +0x0a8, // 0x167 = 359 - JUMP_IF_CONNECTION_ACTIVE_SET +0x167, // 0x168 = 360 - +0x0ff, // 0x169 = 361 - JUMP +0x112, // 0x16a = 362 - +0x037, // 0x16b = 363 - SEND_CREDIT_BLOCK +0x0ff, // 0x16c = 364 - JUMP +0x15d, // 0x16d = 365 - +0x0c8, // 0x16e = 366 - JUMP_IF_BREAK_RECEIVED +0x177, // 0x16f = 367 - +0x0ce, // 0x170 = 368 - JUMP_IF_ANY_DONE_RECEIVED +0x17c, // 0x171 = 369 - +0x0ca, // 0x172 = 370 - JUMP_IF_PHY_READY +0x112, // 0x173 = 371 - +0x033, // 0x174 = 372 - SOFT_RESET +0x0ff, // 0x175 = 373 - JUMP +0x112, // 0x176 = 374 - +0x009, // 0x177 = 375 - CLOSE_BREAK +0x0a8, // 0x178 = 376 - JUMP_IF_CONNECTION_ACTIVE_SET +0x178, // 0x179 = 377 - +0x0ff, // 0x17a = 378 - JUMP +0x112, // 0x17b = 379 - +0x006, // 0x17c = 380 - CLOSE_NORMAL +0x000, // 0x17d = 381 - NO_OP +0x000, // 0x17e = 382 - NO_OP +0x000, // 0x17f = 383 - NO_OP +0x000, // 0x180 = 384 - NO_OP +0x000, // 0x181 = 385 - NO_OP +0x0cd, // 0x182 = 386 - JUMP_IF_CLOSE_STATUS_EQUAL_ANY +0x112, // 0x183 = 387 - +0x0d4, // 0x184 = 388 - JUMP_IF_RX_BUFFER_FULL_TIMEOUT +0x18d, // 0x185 = 389 - +0x0c8, // 0x186 = 390 - JUMP_IF_BREAK_RECEIVED +0x177, // 0x187 = 391 - +0x0ca, // 0x188 = 392 - JUMP_IF_PHY_READY +0x182, // 0x189 = 393 - +0x033, // 0x18a = 394 - SOFT_RESET +0x0ff, // 0x18b = 395 - JUMP +0x001, // 0x18c = 396 - +0x037, // 0x18d = 397 - SEND_CREDIT_BLOCK +0x0ff, // 0x18e = 398 - JUMP +0x186, // 0x18f = 399 - +0x000, // 0x190 = 400 - NO_OP +0x000, // 0x191 = 401 - NO_OP +0x000, // 0x192 = 402 - NO_OP +0x000, // 0x193 = 403 - NO_OP +0x000, // 0x194 = 404 - NO_OP +0x000, // 0x195 = 405 - NO_OP +0x000, // 0x196 = 406 - NO_OP +0x000, // 0x197 = 407 - NO_OP +0x000, // 0x198 = 408 - NO_OP +0x000, // 0x199 = 409 - NO_OP +0x000, // 0x19a = 410 - NO_OP +0x000, // 0x19b = 411 - NO_OP +0x000, // 0x19c = 412 - NO_OP +0x000, // 0x19d = 413 - NO_OP +0x000, // 0x19e = 414 - NO_OP +0x000, // 0x19f = 415 - NO_OP +0x000, // 0x1a0 = 416 - NO_OP +0x000, // 0x1a1 = 417 - NO_OP +0x000, // 0x1a2 = 418 - NO_OP +0x000, // 0x1a3 = 419 - NO_OP +0x000, // 0x1a4 = 420 - NO_OP +0x000, // 0x1a5 = 421 - NO_OP +0x000, // 0x1a6 = 422 - NO_OP +0x000, // 0x1a7 = 423 - NO_OP +0x000, // 0x1a8 = 424 - NO_OP +0x000, // 0x1a9 = 425 - NO_OP +0x000, // 0x1aa = 426 - NO_OP +0x000, // 0x1ab = 427 - NO_OP +0x000, // 0x1ac = 428 - NO_OP +0x000, // 0x1ad = 429 - NO_OP +0x000, // 0x1ae = 430 - NO_OP +0x000, // 0x1af = 431 - NO_OP +0x000, // 0x1b0 = 432 - NO_OP +0x000, // 0x1b1 = 433 - NO_OP +0x000, // 0x1b2 = 434 - NO_OP +0x000, // 0x1b3 = 435 - NO_OP +0x000, // 0x1b4 = 436 - NO_OP +0x000, // 0x1b5 = 437 - NO_OP +0x000, // 0x1b6 = 438 - NO_OP +0x000, // 0x1b7 = 439 - NO_OP +0x000, // 0x1b8 = 440 - NO_OP +0x000, // 0x1b9 = 441 - NO_OP +0x000, // 0x1ba = 442 - NO_OP +0x000, // 0x1bb = 443 - NO_OP +0x000, // 0x1bc = 444 - NO_OP +0x000, // 0x1bd = 445 - NO_OP +0x000, // 0x1be = 446 - NO_OP +0x000, // 0x1bf = 447 - NO_OP +0x000, // 0x1c0 = 448 - NO_OP +0x000, // 0x1c1 = 449 - NO_OP +0x000, // 0x1c2 = 450 - NO_OP +0x000, // 0x1c3 = 451 - NO_OP +0x000, // 0x1c4 = 452 - NO_OP +0x000, // 0x1c5 = 453 - NO_OP +0x000, // 0x1c6 = 454 - NO_OP +0x000, // 0x1c7 = 455 - NO_OP +0x000, // 0x1c8 = 456 - NO_OP +0x000, // 0x1c9 = 457 - NO_OP +0x000, // 0x1ca = 458 - NO_OP +0x000, // 0x1cb = 459 - NO_OP +0x000, // 0x1cc = 460 - NO_OP +0x000, // 0x1cd = 461 - NO_OP +0x000, // 0x1ce = 462 - NO_OP +0x000, // 0x1cf = 463 - NO_OP +0x000, // 0x1d0 = 464 - NO_OP +0x000, // 0x1d1 = 465 - NO_OP +0x000, // 0x1d2 = 466 - NO_OP +0x000, // 0x1d3 = 467 - NO_OP +0x000, // 0x1d4 = 468 - NO_OP +0x000, // 0x1d5 = 469 - NO_OP +0x000, // 0x1d6 = 470 - NO_OP +0x000, // 0x1d7 = 471 - NO_OP +0x000, // 0x1d8 = 472 - NO_OP +0x000, // 0x1d9 = 473 - NO_OP +0x000, // 0x1da = 474 - NO_OP +0x000, // 0x1db = 475 - NO_OP +0x000, // 0x1dc = 476 - NO_OP +0x000, // 0x1dd = 477 - NO_OP +0x000, // 0x1de = 478 - NO_OP +0x000, // 0x1df = 479 - NO_OP +0x000, // 0x1e0 = 480 - NO_OP +0x000, // 0x1e1 = 481 - NO_OP +0x000, // 0x1e2 = 482 - NO_OP +0x000, // 0x1e3 = 483 - NO_OP +0x000, // 0x1e4 = 484 - NO_OP +0x000, // 0x1e5 = 485 - NO_OP +0x000, // 0x1e6 = 486 - NO_OP +0x000, // 0x1e7 = 487 - NO_OP +0x000, // 0x1e8 = 488 - NO_OP +0x000, // 0x1e9 = 489 - NO_OP +0x000, // 0x1ea = 490 - NO_OP +0x000, // 0x1eb = 491 - NO_OP +0x000, // 0x1ec = 492 - NO_OP +0x000, // 0x1ed = 493 - NO_OP +0x000, // 0x1ee = 494 - NO_OP +0x000, // 0x1ef = 495 - NO_OP +0x000, // 0x1f0 = 496 - NO_OP +0x000, // 0x1f1 = 497 - NO_OP +0x000, // 0x1f2 = 498 - NO_OP +0x000, // 0x1f3 = 499 - NO_OP +0x000, // 0x1f4 = 500 - NO_OP +0x000, // 0x1f5 = 501 - NO_OP +0x000, // 0x1f6 = 502 - NO_OP +0x000, // 0x1f7 = 503 - NO_OP +0x000, // 0x1f8 = 504 - NO_OP +0x000, // 0x1f9 = 505 - NO_OP +0x000, // 0x1fa = 506 - NO_OP +0x000, // 0x1fb = 507 - NO_OP +0x000, // 0x1fc = 508 - NO_OP +0x000, // 0x1fd = 509 - NO_OP +0x000, // 0x1fe = 510 - NO_OP +0x000, // 0x1ff = 511 - NO_OP +}; + +/* worked with the bitmap both pnr11020.bit(mainly this) and t091505d0.bit, + this has been golden */ +bit32 wcsImage11020[] = +{ +0x00d, // 00000 = 0 - PHY_RESET_START +0x0be, // 0x001 = 1 - JUMP_IF_PHY_READY +0x009, // 0x002 = 2 - +0x0ae, // 0x003 = 3 - JUMP_IF_HARD_RESET_PRIMITIVE +0x010, // 0x004 = 4 - +0x0af, // 0x005 = 5 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x01e, // 0x006 = 6 - +0x0ff, // 0x007 = 7 - JUMP +0x001, // 0x008 = 8 - +0x00c, // 0x009 = 9 - SEND_ID_FRAME +0x0ae, // 0x00a = 10 - JUMP_IF_HARD_RESET_PRIMITIVE +0x010, // 0x00b = 11 - +0x0af, // 0x00c = 12 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x023, // 0x00d = 13 - +0x0ff, // 0x00e = 14 - JUMP +0x00a, // 0x00f = 15 - +0x01c, // 0x010 = 16 - SOFT_RESET +0x00d, // 0x011 = 17 - PHY_RESET_START +0x0be, // 0x012 = 18 - JUMP_IF_PHY_READY +0x016, // 0x013 = 19 - +0x0af, // 0x014 = 20 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x01b, // 0x015 = 21 - +0x00c, // 0x016 = 22 - SEND_ID_FRAME +0x0af, // 0x017 = 23 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x023, // 0x018 = 24 - +0x0ff, // 0x019 = 25 - JUMP +0x017, // 0x01a = 26 - +0x00c, // 0x01b = 27 - SEND_ID_FRAME +0x0ff, // 0x01c = 28 - JUMP +0x023, // 0x01d = 29 - +0x0be, // 0x01e = 30 - JUMP_IF_PHY_READY +0x022, // 0x01f = 31 - +0x0ff, // 0x020 = 32 - JUMP +0x01e, // 0x021 = 33 - +0x00c, // 0x022 = 34 - SEND_ID_FRAME +0x000, // 0x023 = 35 - NO_OP +0x000, // 0x024 = 36 - NO_OP +0x000, // 0x025 = 37 - NO_OP +0x000, // 0x026 = 38 - NO_OP +0x000, // 0x027 = 39 - NO_OP +0x000, // 0x028 = 40 - NO_OP +0x0ff, // 0x029 = 41 - JUMP +0x061, // 0x02a = 42 - +0x000, // 0x02b = 43 - NO_OP +0x0c9, // 0x02c = 44 - JUMP_IF_RX_BUFFER_FULL_TIMEOUT +0x05e, // 0x02d = 45 - +0x0a5, // 0x02e = 46 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_GOOD +0x041, // 0x02f = 47 - +0x0a6, // 0x030 = 48 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_NAK +0x052, // 0x031 = 49 - +0x0a7, // 0x032 = 50 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_ACK_NAK_TIMEOUT +0x055, // 0x033 = 51 - +0x0a8, // 0x034 = 52 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_BREAK +0x052, // 0x035 = 53 - +0x0aa, // 0x036 = 54 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_CREDIT_TIMEOUT +0x058, // 0x037 = 55 - +0x0c5, // 0x038 = 56 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_SMP_ERR +0x05b, // 0x039 = 57 - +0x0ca, // 0x03a = 58 - JUMP_IF_DOC_CLOSE_REQ +0x0a5, // 0x03b = 59 - +0x0be, // 0x03c = 60 - JUMP_IF_PHY_READY +0x04a, // 0x03d = 61 - +0x01c, // 0x03e = 62 - SOFT_RESET +0x0ff, // 0x03f = 63 - JUMP +0x001, // 0x040 = 64 - +0x01d, // 0x041 = 65 - ADVANCE +0x0c3, // 0x042 = 66 - JUMP_IF_SMP_PROTOCOL +0x046, // 0x043 = 67 - +0x0ff, // 0x044 = 68 - JUMP +0x061, // 0x045 = 69 - +0x0a2, // 0x046 = 70 - JUMP_IF_CONNECTION_OPEN_MASTER_FLAG_SET +0x0a5, // 0x047 = 71 - +0x0ff, // 0x048 = 72 - JUMP +0x061, // 0x049 = 73 - +0x0ab, // 0x04a = 74 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_CREDIT_BLOCKED +0x052, // 0x04b = 75 - +0x0ac, // 0x04c = 76 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_MAX_BURST_SIZE +0x052, // 0x04d = 77 - +0x0ad, // 0x04e = 78 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_MAX_CONNECTION_TIME +0x052, // 0x04f = 79 - +0x0ff, // 0x050 = 80 - JUMP +0x02c, // 0x051 = 81 - +0x01d, // 0x052 = 82 - ADVANCE +0x0ff, // 0x053 = 83 - JUMP +0x061, // 0x054 = 84 - +0x01d, // 0x055 = 85 - ADVANCE +0x0ff, // 0x056 = 86 - JUMP +0x0c2, // 0x057 = 87 - +0x01d, // 0x058 = 88 - ADVANCE +0x0ff, // 0x059 = 89 - JUMP +0x0c5, // 0x05a = 90 - +0x01d, // 0x05b = 91 - ADVANCE +0x0ff, // 0x05c = 92 - JUMP +0x0b6, // 0x05d = 93 - +0x022, // 0x05e = 94 - SEND_CREDIT_BLOCK +0x0ff, // 0x05f = 95 - JUMP +0x02e, // 0x060 = 96 - +0x0c8, // 0x061 = 97 - JUMP_IF_HIP_REQ +0x06d, // 0x062 = 98 - +0x0c6, // 0x063 = 99 - JUMP_IF_SFO_REQ +0x07d, // 0x064 = 100 - +0x0c7, // 0x065 = 101 - JUMP_IF_DOC_REQ +0x08d, // 0x066 = 102 - +0x0a3, // 0x067 = 103 - JUMP_IF_CONNECTION_OPEN_SLAVE_FLAG_SET +0x09d, // 0x068 = 104 - +0x0a2, // 0x069 = 105 - JUMP_IF_CONNECTION_OPEN_MASTER_FLAG_SET +0x0a5, // 0x06a = 106 - +0x0ff, // 0x06b = 107 - JUMP +0x061, // 0x06c = 108 - +0x020, // 0x06d = 109 - SELECT_HIP +0x000, // 0x06e = 110 - NO_OP +0x000, // 0x06f = 111 - NO_OP +0x0a4, // 0x070 = 112 - JUMP_IF_CONNECTION_ACTIVE_SET +0x074, // 0x071 = 113 - +0x0ff, // 0x072 = 114 - JUMP +0x0c8, // 0x073 = 115 - +0x0a0, // 0x074 = 116 - JUMP_IF_CONNECTION_PROFILE_OPEN_EQUAL +0x07a, // 0x075 = 117 - +0x0a3, // 0x076 = 118 - JUMP_IF_CONNECTION_OPEN_SLAVE_FLAG_SET +0x09d, // 0x077 = 119 - +0x0ff, // 0x078 = 120 - JUMP +0x0a5, // 0x079 = 121 - +0x013, // 0x07a = 122 - SET_OPEN_STATUS_NORMAL +0x0ff, // 0x07b = 123 - JUMP +0x02b, // 0x07c = 124 - +0x01e, // 0x07d = 125 - SELECT_SFO +0x000, // 0x07e = 126 - NO_OP +0x000, // 0x07f = 127 - NO_OP +0x0a4, // 0x080 = 128 - JUMP_IF_CONNECTION_ACTIVE_SET +0x084, // 0x081 = 129 - +0x0ff, // 0x082 = 130 - JUMP +0x0c8, // 0x083 = 131 - +0x0a0, // 0x084 = 132 - JUMP_IF_CONNECTION_PROFILE_OPEN_EQUAL +0x08a, // 0x085 = 133 - +0x0a3, // 0x086 = 134 - JUMP_IF_CONNECTION_OPEN_SLAVE_FLAG_SET +0x09d, // 0x087 = 135 - +0x0ff, // 0x088 = 136 - JUMP +0x0a5, // 0x089 = 137 - +0x013, // 0x08a = 138 - SET_OPEN_STATUS_NORMAL +0x0ff, // 0x08b = 139 - JUMP +0x02b, // 0x08c = 140 - +0x01f, // 0x08d = 141 - SELECT_DOC +0x000, // 0x08e = 142 - NO_OP +0x000, // 0x08f = 143 - NO_OP +0x0a4, // 0x090 = 144 - JUMP_IF_CONNECTION_ACTIVE_SET +0x094, // 0x091 = 145 - +0x0ff, // 0x092 = 146 - JUMP +0x0c8, // 0x093 = 147 - +0x0a0, // 0x094 = 148 - JUMP_IF_CONNECTION_PROFILE_OPEN_EQUAL +0x09a, // 0x095 = 149 - +0x0a3, // 0x096 = 150 - JUMP_IF_CONNECTION_OPEN_SLAVE_FLAG_SET +0x09d, // 0x097 = 151 - +0x0ff, // 0x098 = 152 - JUMP +0x0a5, // 0x099 = 153 - +0x013, // 0x09a = 154 - SET_OPEN_STATUS_NORMAL +0x0ff, // 0x09b = 155 - JUMP +0x02b, // 0x09c = 156 - +0x0c3, // 0x09d = 157 - JUMP_IF_SMP_PROTOCOL +0x0a1, // 0x09e = 158 - +0x0ff, // 0x09f = 159 - JUMP +0x0a5, // 0x0a0 = 160 - +0x0c4, // 0x0a1 = 161 - JUMP_IF_SMP_FRAME_ERR_RECEIVED +0x0b6, // 0x0a2 = 162 - +0x0ff, // 0x0a3 = 163 - JUMP +0x061, // 0x0a4 = 164 - +0x004, // 0x0a5 = 165 - CLOSE_NORMAL +0x000, // 0x0a6 = 166 - NO_OP +0x000, // 0x0a7 = 167 - NO_OP +0x000, // 0x0a8 = 168 - NO_OP +0x000, // 0x0a9 = 169 - NO_OP +0x0c9, // 0x0aa = 170 - JUMP_IF_RX_BUFFER_FULL_TIMEOUT +0x0b3, // 0x0ab = 171 - +0x0c0, // 0x0ac = 172 - JUMP_IF_CLOSE_STATUS_EQUAL_ANY +0x061, // 0x0ad = 173 - +0x0be, // 0x0ae = 174 - JUMP_IF_PHY_READY +0x0a6, // 0x0af = 175 - +0x01c, // 0x0b0 = 176 - SOFT_RESET +0x0ff, // 0x0b1 = 177 - JUMP +0x001, // 0x0b2 = 178 - +0x022, // 0x0b3 = 179 - SEND_CREDIT_BLOCK +0x0ff, // 0x0b4 = 180 - JUMP +0x0a6, // 0x0b5 = 181 - +0x007, // 0x0b6 = 182 - CLOSE_BREAK +0x000, // 0x0b7 = 183 - NO_OP +0x000, // 0x0b8 = 184 - NO_OP +0x000, // 0x0b9 = 185 - NO_OP +0x000, // 0x0ba = 186 - NO_OP +0x0c0, // 0x0bb = 187 - JUMP_IF_CLOSE_STATUS_EQUAL_ANY +0x061, // 0x0bc = 188 - +0x0be, // 0x0bd = 189 - JUMP_IF_PHY_READY +0x0b7, // 0x0be = 190 - +0x01c, // 0x0bf = 191 - SOFT_RESET +0x0ff, // 0x0c0 = 192 - JUMP +0x001, // 0x0c1 = 193 - +0x005, // 0x0c2 = 194 - CLOSE_ACK_NAK_TIMEOUT +0x0ff, // 0x0c3 = 195 - JUMP +0x0a6, // 0x0c4 = 196 - +0x006, // 0x0c5 = 197 - CLOSE_CREDIT_TIMEOUT +0x0ff, // 0x0c6 = 198 - JUMP +0x0a6, // 0x0c7 = 199 - +0x0b0, // 0x0c8 = 200 - JUMP_IF_FLAG_0_SET +0x0cd, // 0x0c9 = 201 - +0x011, // 0x0ca = 202 - START_IT_NEXUS_LOSS_TIMER +0x00f, // 0x0cb = 203 - PATHWAY_BLOCKED_CNT_RESET +0x00e, // 0x0cc = 204 - START_ARB_WAIT_TIMER +0x001, // 0x0cd = 205 - OPEN_REQUEST +0x000, // 0x0ce = 206 - NO_OP +0x000, // 0x0cf = 207 - NO_OP +0x000, // 0x0d0 = 208 - NO_OP +0x000, // 0x0d1 = 209 - NO_OP +0x090, // 0x0d2 = 210 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_ACCEPT +0x0f8, // 0x0d3 = 211 - +0x095, // 0x0d4 = 212 - JUMP_IF_OPEN_STATUS_EQUAL_RATE_NOT_SUPPORTED +0x0fd, // 0x0d5 = 213 - +0x099, // 0x0d6 = 214 - JUMP_IF_OPEN_STATUS_EQUAL_PROTOCOL_NOT_SUPPORTED +0x100, // 0x0d7 = 215 - +0x09b, // 0x0d8 = 216 - JUMP_IF_OPEN_STATUS_EQUAL_WRONG_DESTINATION +0x103, // 0x0d9 = 217 - +0x094, // 0x0da = 218 - JUMP_IF_OPEN_STATUS_EQUAL_BREAK_RECEIVED +0x0cd, // 0x0db = 219 - +0x093, // 0x0dc = 220 - JUMP_IF_OPEN_STATUS_EQUAL_BAD_DESTINATION +0x106, // 0x0dd = 221 - +0x09f, // 0x0de = 222 - JUMP_IF_IT_NEXUS_LOSS_TIMEOUT +0x109, // 0x0df = 223 - +0x09a, // 0x0e0 = 224 - JUMP_IF_OPEN_STATUS_EQUAL_STP_RESOURCE_BUSY +0x0cd, // 0x0e1 = 225 - +0x096, // 0x0e2 = 226 - JUMP_IF_OPEN_STATUS_EQUAL_NO_DESTINATION +0x106, // 0x0e3 = 227 - +0x097, // 0x0e4 = 228 - JUMP_IF_OPEN_STATUS_EQUAL_PATHWAY_BLOCKED +0x10c, // 0x0e5 = 229 - +0x098, // 0x0e6 = 230 - JUMP_IF_OPEN_STATUS_EQUAL_RETRY +0x0cd, // 0x0e7 = 231 - +0x092, // 0x0e8 = 232 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_TIMEOUT +0x0cd, // 0x0e9 = 233 - +0x0a4, // 0x0ea = 234 - JUMP_IF_CONNECTION_ACTIVE_SET +0x0f2, // 0x0eb = 235 - +0x0be, // 0x0ec = 236 - JUMP_IF_PHY_READY +0x0d2, // 0x0ed = 237 - +0x01b, // 0x0ee = 238 - SET_OPEN_STATUS_PHY_NOT_RDY +0x01c, // 0x0ef = 239 - SOFT_RESET +0x0ff, // 0x0f0 = 240 - JUMP +0x001, // 0x0f1 = 241 - +0x0a0, // 0x0f2 = 242 - JUMP_IF_CONNECTION_PROFILE_OPEN_EQUAL +0x0f8, // 0x0f3 = 243 - +0x000, // 0x0f4 = 244 - NO_OP +0x000, // 0x0f5 = 245 - NO_OP +0x0ff, // 0x0f6 = 246 - JUMP +0x09d, // 0x0f7 = 247 - +0x013, // 0x0f8 = 248 - SET_OPEN_STATUS_NORMAL +0x000, // 0x0f9 = 249 - NO_OP +0x000, // 0x0fa = 250 - NO_OP +0x0ff, // 0x0fb = 251 - JUMP +0x02b, // 0x0fc = 252 - +0x017, // 0x0fd = 253 - SET_OPEN_STATUS_BAD_RATE +0x0ff, // 0x0fe = 254 - JUMP +0x061, // 0x0ff = 255 - +0x018, // 0x100 = 256 - SET_OPEN_STATUS_BAD_PROTOCOL +0x0ff, // 0x101 = 257 - JUMP +0x061, // 0x102 = 258 - +0x01a, // 0x103 = 259 - SET_OPEN_STATUS_WRONG_DEST +0x0ff, // 0x104 = 260 - JUMP +0x061, // 0x105 = 261 - +0x015, // 0x106 = 262 - SET_OPEN_STATUS_BAD_DEST +0x0ff, // 0x107 = 263 - JUMP +0x061, // 0x108 = 264 - +0x014, // 0x109 = 265 - SET_OPEN_STATUS_IT_NEXUS_LOSS +0x0ff, // 0x10a = 266 - JUMP +0x061, // 0x10b = 267 - +0x010, // 0x10c = 268 - PATHWAY_BLOCKED_CNT_INC +0x0ff, // 0x10d = 269 - JUMP +0x0cd, // 0x10e = 270 - +0x000, // 0x10f = 271 - NO_OP +0x000, // 0x110 = 272 - NO_OP +0x000, // 0x111 = 273 - NO_OP +0x000, // 0x112 = 274 - NO_OP +0x000, // 0x113 = 275 - NO_OP +0x000, // 0x114 = 276 - NO_OP +0x000, // 0x115 = 277 - NO_OP +0x000, // 0x116 = 278 - NO_OP +0x000, // 0x117 = 279 - NO_OP +0x000, // 0x118 = 280 - NO_OP +0x000, // 0x119 = 281 - NO_OP +0x000, // 0x11a = 282 - NO_OP +0x000, // 0x11b = 283 - NO_OP +0x000, // 0x11c = 284 - NO_OP +0x000, // 0x11d = 285 - NO_OP +0x000, // 0x11e = 286 - NO_OP +0x000, // 0x11f = 287 - NO_OP +0x000, // 0x120 = 288 - NO_OP +0x000, // 0x121 = 289 - NO_OP +0x000, // 0x122 = 290 - NO_OP +0x000, // 0x123 = 291 - NO_OP +0x000, // 0x124 = 292 - NO_OP +0x000, // 0x125 = 293 - NO_OP +0x000, // 0x126 = 294 - NO_OP +0x000, // 0x127 = 295 - NO_OP +0x000, // 0x128 = 296 - NO_OP +0x000, // 0x129 = 297 - NO_OP +0x000, // 0x12a = 298 - NO_OP +0x000, // 0x12b = 299 - NO_OP +0x000, // 0x12c = 300 - NO_OP +0x000, // 0x12d = 301 - NO_OP +0x000, // 0x12e = 302 - NO_OP +0x000, // 0x12f = 303 - NO_OP +0x000, // 0x130 = 304 - NO_OP +0x000, // 0x131 = 305 - NO_OP +0x000, // 0x132 = 306 - NO_OP +0x000, // 0x133 = 307 - NO_OP +0x000, // 0x134 = 308 - NO_OP +0x000, // 0x135 = 309 - NO_OP +0x000, // 0x136 = 310 - NO_OP +0x000, // 0x137 = 311 - NO_OP +0x000, // 0x138 = 312 - NO_OP +0x000, // 0x139 = 313 - NO_OP +0x000, // 0x13a = 314 - NO_OP +0x000, // 0x13b = 315 - NO_OP +0x000, // 0x13c = 316 - NO_OP +0x000, // 0x13d = 317 - NO_OP +0x000, // 0x13e = 318 - NO_OP +0x000, // 0x13f = 319 - NO_OP +0x000, // 0x140 = 320 - NO_OP +0x000, // 0x141 = 321 - NO_OP +0x000, // 0x142 = 322 - NO_OP +0x000, // 0x143 = 323 - NO_OP +0x000, // 0x144 = 324 - NO_OP +0x000, // 0x145 = 325 - NO_OP +0x000, // 0x146 = 326 - NO_OP +0x000, // 0x147 = 327 - NO_OP +0x000, // 0x148 = 328 - NO_OP +0x000, // 0x149 = 329 - NO_OP +0x000, // 0x14a = 330 - NO_OP +0x000, // 0x14b = 331 - NO_OP +0x000, // 0x14c = 332 - NO_OP +0x000, // 0x14d = 333 - NO_OP +0x000, // 0x14e = 334 - NO_OP +0x000, // 0x14f = 335 - NO_OP +0x000, // 0x150 = 336 - NO_OP +0x000, // 0x151 = 337 - NO_OP +0x000, // 0x152 = 338 - NO_OP +0x000, // 0x153 = 339 - NO_OP +0x000, // 0x154 = 340 - NO_OP +0x000, // 0x155 = 341 - NO_OP +0x000, // 0x156 = 342 - NO_OP +0x000, // 0x157 = 343 - NO_OP +0x000, // 0x158 = 344 - NO_OP +0x000, // 0x159 = 345 - NO_OP +0x000, // 0x15a = 346 - NO_OP +0x000, // 0x15b = 347 - NO_OP +0x000, // 0x15c = 348 - NO_OP +0x000, // 0x15d = 349 - NO_OP +0x000, // 0x15e = 350 - NO_OP +0x000, // 0x15f = 351 - NO_OP +0x000, // 0x160 = 352 - NO_OP +0x000, // 0x161 = 353 - NO_OP +0x000, // 0x162 = 354 - NO_OP +0x000, // 0x163 = 355 - NO_OP +0x000, // 0x164 = 356 - NO_OP +0x000, // 0x165 = 357 - NO_OP +0x000, // 0x166 = 358 - NO_OP +0x000, // 0x167 = 359 - NO_OP +0x000, // 0x168 = 360 - NO_OP +0x000, // 0x169 = 361 - NO_OP +0x000, // 0x16a = 362 - NO_OP +0x000, // 0x16b = 363 - NO_OP +0x000, // 0x16c = 364 - NO_OP +0x000, // 0x16d = 365 - NO_OP +0x000, // 0x16e = 366 - NO_OP +0x000, // 0x16f = 367 - NO_OP +0x000, // 0x170 = 368 - NO_OP +0x000, // 0x171 = 369 - NO_OP +0x000, // 0x172 = 370 - NO_OP +0x000, // 0x173 = 371 - NO_OP +0x000, // 0x174 = 372 - NO_OP +0x000, // 0x175 = 373 - NO_OP +0x000, // 0x176 = 374 - NO_OP +0x000, // 0x177 = 375 - NO_OP +0x000, // 0x178 = 376 - NO_OP +0x000, // 0x179 = 377 - NO_OP +0x000, // 0x17a = 378 - NO_OP +0x000, // 0x17b = 379 - NO_OP +0x000, // 0x17c = 380 - NO_OP +0x000, // 0x17d = 381 - NO_OP +0x000, // 0x17e = 382 - NO_OP +0x000, // 0x17f = 383 - NO_OP +0x000, // 0x180 = 384 - NO_OP +0x000, // 0x181 = 385 - NO_OP +0x000, // 0x182 = 386 - NO_OP +0x000, // 0x183 = 387 - NO_OP +0x000, // 0x184 = 388 - NO_OP +0x000, // 0x185 = 389 - NO_OP +0x000, // 0x186 = 390 - NO_OP +0x000, // 0x187 = 391 - NO_OP +0x000, // 0x188 = 392 - NO_OP +0x000, // 0x189 = 393 - NO_OP +0x000, // 0x18a = 394 - NO_OP +0x000, // 0x18b = 395 - NO_OP +0x000, // 0x18c = 396 - NO_OP +0x000, // 0x18d = 397 - NO_OP +0x000, // 0x18e = 398 - NO_OP +0x000, // 0x18f = 399 - NO_OP +0x000, // 0x190 = 400 - NO_OP +0x000, // 0x191 = 401 - NO_OP +0x000, // 0x192 = 402 - NO_OP +0x000, // 0x193 = 403 - NO_OP +0x000, // 0x194 = 404 - NO_OP +0x000, // 0x195 = 405 - NO_OP +0x000, // 0x196 = 406 - NO_OP +0x000, // 0x197 = 407 - NO_OP +0x000, // 0x198 = 408 - NO_OP +0x000, // 0x199 = 409 - NO_OP +0x000, // 0x19a = 410 - NO_OP +0x000, // 0x19b = 411 - NO_OP +0x000, // 0x19c = 412 - NO_OP +0x000, // 0x19d = 413 - NO_OP +0x000, // 0x19e = 414 - NO_OP +0x000, // 0x19f = 415 - NO_OP +0x000, // 0x1a0 = 416 - NO_OP +0x000, // 0x1a1 = 417 - NO_OP +0x000, // 0x1a2 = 418 - NO_OP +0x000, // 0x1a3 = 419 - NO_OP +0x000, // 0x1a4 = 420 - NO_OP +0x000, // 0x1a5 = 421 - NO_OP +0x000, // 0x1a6 = 422 - NO_OP +0x000, // 0x1a7 = 423 - NO_OP +0x000, // 0x1a8 = 424 - NO_OP +0x000, // 0x1a9 = 425 - NO_OP +0x000, // 0x1aa = 426 - NO_OP +0x000, // 0x1ab = 427 - NO_OP +0x000, // 0x1ac = 428 - NO_OP +0x000, // 0x1ad = 429 - NO_OP +0x000, // 0x1ae = 430 - NO_OP +0x000, // 0x1af = 431 - NO_OP +0x000, // 0x1b0 = 432 - NO_OP +0x000, // 0x1b1 = 433 - NO_OP +0x000, // 0x1b2 = 434 - NO_OP +0x000, // 0x1b3 = 435 - NO_OP +0x000, // 0x1b4 = 436 - NO_OP +0x000, // 0x1b5 = 437 - NO_OP +0x000, // 0x1b6 = 438 - NO_OP +0x000, // 0x1b7 = 439 - NO_OP +0x000, // 0x1b8 = 440 - NO_OP +0x000, // 0x1b9 = 441 - NO_OP +0x000, // 0x1ba = 442 - NO_OP +0x000, // 0x1bb = 443 - NO_OP +0x000, // 0x1bc = 444 - NO_OP +0x000, // 0x1bd = 445 - NO_OP +0x000, // 0x1be = 446 - NO_OP +0x000, // 0x1bf = 447 - NO_OP +0x000, // 0x1c0 = 448 - NO_OP +0x000, // 0x1c1 = 449 - NO_OP +0x000, // 0x1c2 = 450 - NO_OP +0x000, // 0x1c3 = 451 - NO_OP +0x000, // 0x1c4 = 452 - NO_OP +0x000, // 0x1c5 = 453 - NO_OP +0x000, // 0x1c6 = 454 - NO_OP +0x000, // 0x1c7 = 455 - NO_OP +0x000, // 0x1c8 = 456 - NO_OP +0x000, // 0x1c9 = 457 - NO_OP +0x000, // 0x1ca = 458 - NO_OP +0x000, // 0x1cb = 459 - NO_OP +0x000, // 0x1cc = 460 - NO_OP +0x000, // 0x1cd = 461 - NO_OP +0x000, // 0x1ce = 462 - NO_OP +0x000, // 0x1cf = 463 - NO_OP +0x000, // 0x1d0 = 464 - NO_OP +0x000, // 0x1d1 = 465 - NO_OP +0x000, // 0x1d2 = 466 - NO_OP +0x000, // 0x1d3 = 467 - NO_OP +0x000, // 0x1d4 = 468 - NO_OP +0x000, // 0x1d5 = 469 - NO_OP +0x000, // 0x1d6 = 470 - NO_OP +0x000, // 0x1d7 = 471 - NO_OP +0x000, // 0x1d8 = 472 - NO_OP +0x000, // 0x1d9 = 473 - NO_OP +0x000, // 0x1da = 474 - NO_OP +0x000, // 0x1db = 475 - NO_OP +0x000, // 0x1dc = 476 - NO_OP +0x000, // 0x1dd = 477 - NO_OP +0x000, // 0x1de = 478 - NO_OP +0x000, // 0x1df = 479 - NO_OP +0x000, // 0x1e0 = 480 - NO_OP +0x000, // 0x1e1 = 481 - NO_OP +0x000, // 0x1e2 = 482 - NO_OP +0x000, // 0x1e3 = 483 - NO_OP +0x000, // 0x1e4 = 484 - NO_OP +0x000, // 0x1e5 = 485 - NO_OP +0x000, // 0x1e6 = 486 - NO_OP +0x000, // 0x1e7 = 487 - NO_OP +0x000, // 0x1e8 = 488 - NO_OP +0x000, // 0x1e9 = 489 - NO_OP +0x000, // 0x1ea = 490 - NO_OP +0x000, // 0x1eb = 491 - NO_OP +0x000, // 0x1ec = 492 - NO_OP +0x000, // 0x1ed = 493 - NO_OP +0x000, // 0x1ee = 494 - NO_OP +0x000, // 0x1ef = 495 - NO_OP +0x000, // 0x1f0 = 496 - NO_OP +0x000, // 0x1f1 = 497 - NO_OP +0x000, // 0x1f2 = 498 - NO_OP +0x000, // 0x1f3 = 499 - NO_OP +0x000, // 0x1f4 = 500 - NO_OP +0x000, // 0x1f5 = 501 - NO_OP +0x000, // 0x1f6 = 502 - NO_OP +0x000, // 0x1f7 = 503 - NO_OP +0x000, // 0x1f8 = 504 - NO_OP +0x000, // 0x1f9 = 505 - NO_OP +0x000, // 0x1fa = 506 - NO_OP +0x000, // 0x1fb = 507 - NO_OP +0x000, // 0x1fc = 508 - NO_OP +0x000, // 0x1fd = 509 - NO_OP +0x000, // 0x1fe = 510 - NO_OP +0x000, // 0x1ff = 511 - NO_OP +}; + +/* for pnr12220.bit */ +bit32 wcsImage12220[] = +{ + 0x00d, // 00000 = 0 - PHY_RESET_START + 0x0be, // 0x001 = 1 - JUMP_IF_PHY_READY + 0x009, // 0x002 = 2 - + 0x0ae, // 0x003 = 3 - JUMP_IF_HARD_RESET_PRIMITIVE + 0x010, // 0x004 = 4 - + 0x0af, // 0x005 = 5 - JUMP_IF_IDENTIFY_FRAME_RECEIVED + 0x01e, // 0x006 = 6 - + 0x0ff, // 0x007 = 7 - JUMP + 0x001, // 0x008 = 8 - + 0x00c, // 0x009 = 9 - SEND_ID_FRAME + 0x0ae, // 0x00a = 10 - JUMP_IF_HARD_RESET_PRIMITIVE + 0x010, // 0x00b = 11 - + 0x0af, // 0x00c = 12 - JUMP_IF_IDENTIFY_FRAME_RECEIVED + 0x023, // 0x00d = 13 - + 0x0ff, // 0x00e = 14 - JUMP + 0x00a, // 0x00f = 15 - + 0x01c, // 0x010 = 16 - SOFT_RESET + 0x00d, // 0x011 = 17 - PHY_RESET_START + 0x0be, // 0x012 = 18 - JUMP_IF_PHY_READY + 0x016, // 0x013 = 19 - + 0x0af, // 0x014 = 20 - JUMP_IF_IDENTIFY_FRAME_RECEIVED + 0x01b, // 0x015 = 21 - + 0x00c, // 0x016 = 22 - SEND_ID_FRAME + 0x0af, // 0x017 = 23 - JUMP_IF_IDENTIFY_FRAME_RECEIVED + 0x023, // 0x018 = 24 - + 0x0ff, // 0x019 = 25 - JUMP + 0x017, // 0x01a = 26 - + 0x00c, // 0x01b = 27 - SEND_ID_FRAME + 0x0ff, // 0x01c = 28 - JUMP + 0x023, // 0x01d = 29 - + 0x0be, // 0x01e = 30 - JUMP_IF_PHY_READY + 0x022, // 0x01f = 31 - + 0x0ff, // 0x020 = 32 - JUMP + 0x01e, // 0x021 = 33 - + 0x00c, // 0x022 = 34 - SEND_ID_FRAME + 0x000, // 0x023 = 35 - NO_OP + 0x000, // 0x024 = 36 - NO_OP + 0x000, // 0x025 = 37 - NO_OP + 0x000, // 0x026 = 38 - NO_OP + 0x000, // 0x027 = 39 - NO_OP + 0x000, // 0x028 = 40 - NO_OP + 0x0ff, // 0x029 = 41 - JUMP + 0x059, // 0x02a = 42 - + 0x000, // 0x02b = 43 - NO_OP + 0x0c9, // 0x02c = 44 - JUMP_IF_RX_BUFFER_FULL_TIMEOUT + 0x056, // 0x02d = 45 - + 0x0a5, // 0x02e = 46 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_GOOD + 0x041, // 0x02f = 47 - + 0x0a6, // 0x030 = 48 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_NAK + 0x04a, // 0x031 = 49 - + 0x0a7, // 0x032 = 50 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_ACK_NAK_TIMEOUT + 0x04d, // 0x033 = 51 - + 0x0a8, // 0x034 = 52 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_BREAK + 0x053, // 0x035 = 53 - + 0x0aa, // 0x036 = 54 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_CREDIT_TIMEOUT + 0x050, // 0x037 = 55 - + 0x0c5, // 0x038 = 56 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_SMP_ERR + 0x053, // 0x039 = 57 - + 0x0ca, // 0x03a = 58 - JUMP_IF_CLOSE_REQ + 0x08e, // 0x03b = 59 - + 0x0be, // 0x03c = 60 - JUMP_IF_PHY_READY + 0x02c, // 0x03d = 61 - + 0x01c, // 0x03e = 62 - SOFT_RESET + 0x0ff, // 0x03f = 63 - JUMP + 0x001, // 0x040 = 64 - + 0x01d, // 0x041 = 65 - ADVANCE + 0x0c3, // 0x042 = 66 - JUMP_IF_SMP_PROTOCOL + 0x046, // 0x043 = 67 - + 0x0ff, // 0x044 = 68 - JUMP + 0x059, // 0x045 = 69 - + 0x0a2, // 0x046 = 70 - JUMP_IF_CONNECTION_OPEN_MASTER_FLAG_SET + 0x08e, // 0x047 = 71 - + 0x0ff, // 0x048 = 72 - JUMP + 0x059, // 0x049 = 73 - + 0x01d, // 0x04a = 74 - ADVANCE + 0x0ff, // 0x04b = 75 - JUMP + 0x059, // 0x04c = 76 - + 0x01d, // 0x04d = 77 - ADVANCE + 0x0ff, // 0x04e = 78 - JUMP + 0x0ad, // 0x04f = 79 - + 0x01d, // 0x050 = 80 - ADVANCE + 0x0ff, // 0x051 = 81 - JUMP + 0x0b0, // 0x052 = 82 - + 0x01d, // 0x053 = 83 - ADVANCE + 0x0ff, // 0x054 = 84 - JUMP + 0x0a1, // 0x055 = 85 - + 0x022, // 0x056 = 86 - SEND_CREDIT_BLOCK + 0x0ff, // 0x057 = 87 - JUMP + 0x02e, // 0x058 = 88 - + 0x0c8, // 0x059 = 89 - JUMP_IF_HIP_REQ + 0x065, // 0x05a = 90 - + 0x0c6, // 0x05b = 91 - JUMP_IF_SFO_REQ + 0x06a, // 0x05c = 92 - + 0x0c7, // 0x05d = 93 - JUMP_IF_DOC_REQ + 0x06f, // 0x05e = 94 - + 0x0a3, // 0x05f = 95 - JUMP_IF_CONNECTION_OPEN_SLAVE_FLAG_SET + 0x086, // 0x060 = 96 - + 0x0a2, // 0x061 = 97 - JUMP_IF_CONNECTION_OPEN_MASTER_FLAG_SET + 0x08e, // 0x062 = 98 - + 0x0ff, // 0x063 = 99 - JUMP + 0x059, // 0x064 = 100 - + 0x020, // 0x065 = 101 - SELECT_HIP + 0x000, // 0x066 = 102 - NO_OP + 0x000, // 0x067 = 103 - NO_OP + 0x0ff, // 0x068 = 104 - JUMP + 0x072, // 0x069 = 105 - + 0x01e, // 0x06a = 106 - SELECT_SFO + 0x000, // 0x06b = 107 - NO_OP + 0x000, // 0x06c = 108 - NO_OP + 0x0ff, // 0x06d = 109 - JUMP + 0x072, // 0x06e = 110 - + 0x01f, // 0x06f = 111 - SELECT_DOC + 0x000, // 0x070 = 112 - NO_OP + 0x000, // 0x071 = 113 - NO_OP + 0x0a4, // 0x072 = 114 - JUMP_IF_CONNECTION_ACTIVE_SET + 0x076, // 0x073 = 115 - + 0x0ff, // 0x074 = 116 - JUMP + 0x0b3, // 0x075 = 117 - + 0x0a0, // 0x076 = 118 - JUMP_IF_CONNECTION_PROFILE_OPEN_EQUAL + 0x07c, // 0x077 = 119 - + 0x0a3, // 0x078 = 120 - JUMP_IF_CONNECTION_OPEN_SLAVE_FLAG_SET + 0x086, // 0x079 = 121 - + 0x0ff, // 0x07a = 122 - JUMP + 0x08e, // 0x07b = 123 - + 0x0cb, // 0x07c = 124 - JUMP_IF_FREEZE_ACTIVE + 0x081, // 0x07d = 125 - + 0x013, // 0x07e = 126 - SET_OPEN_STATUS_NORMAL + 0x0ff, // 0x07f = 127 - JUMP + 0x02b, // 0x080 = 128 - + 0x024, // 0x081 = 129 - SET_OPEN_STATUS_FREEZE + 0x000, // 0x082 = 130 - NO_OP + 0x000, // 0x083 = 131 - NO_OP + 0x0ff, // 0x084 = 132 - JUMP + 0x059, // 0x085 = 133 - + 0x0c3, // 0x086 = 134 - JUMP_IF_SMP_PROTOCOL + 0x08a, // 0x087 = 135 - + 0x0ff, // 0x088 = 136 - JUMP + 0x08e, // 0x089 = 137 - + 0x0c4, // 0x08a = 138 - JUMP_IF_SMP_FRAME_ERR_RECEIVED + 0x0a1, // 0x08b = 139 - + 0x0ff, // 0x08c = 140 - JUMP + 0x059, // 0x08d = 141 - + 0x004, // 0x08e = 142 - CLOSE_NORMAL + 0x000, // 0x08f = 143 - NO_OP + 0x000, // 0x090 = 144 - NO_OP + 0x000, // 0x091 = 145 - NO_OP + 0x000, // 0x092 = 146 - NO_OP + 0x0c9, // 0x093 = 147 - JUMP_IF_RX_BUFFER_FULL_TIMEOUT + 0x09e, // 0x094 = 148 - + 0x0c0, // 0x095 = 149 - JUMP_IF_CLOSE_STATUS_EQUAL_ANY + 0x059, // 0x096 = 150 - + 0x0bc, // 0x097 = 151 - JUMP_IF_BREAK_RECEIVED + 0x0a1, // 0x098 = 152 - + 0x0be, // 0x099 = 153 - JUMP_IF_PHY_READY + 0x08f, // 0x09a = 154 - + 0x01c, // 0x09b = 155 - SOFT_RESET + 0x0ff, // 0x09c = 156 - JUMP + 0x001, // 0x09d = 157 - + 0x022, // 0x09e = 158 - SEND_CREDIT_BLOCK + 0x0ff, // 0x09f = 159 - JUMP + 0x08f, // 0x0a0 = 160 - + 0x007, // 0x0a1 = 161 - CLOSE_BREAK + 0x000, // 0x0a2 = 162 - NO_OP + 0x000, // 0x0a3 = 163 - NO_OP + 0x000, // 0x0a4 = 164 - NO_OP + 0x000, // 0x0a5 = 165 - NO_OP + 0x0c0, // 0x0a6 = 166 - JUMP_IF_CLOSE_STATUS_EQUAL_ANY + 0x059, // 0x0a7 = 167 - + 0x0be, // 0x0a8 = 168 - JUMP_IF_PHY_READY + 0x0a2, // 0x0a9 = 169 - + 0x01c, // 0x0aa = 170 - SOFT_RESET + 0x0ff, // 0x0ab = 171 - JUMP + 0x001, // 0x0ac = 172 - + 0x005, // 0x0ad = 173 - CLOSE_ACK_NAK_TIMEOUT + 0x0ff, // 0x0ae = 174 - JUMP + 0x08f, // 0x0af = 175 - + 0x006, // 0x0b0 = 176 - CLOSE_CREDIT_TIMEOUT + 0x0ff, // 0x0b1 = 177 - JUMP + 0x08f, // 0x0b2 = 178 - + 0x0cc, // 0x0b3 = 179 - JUMP_IF_RX_BUFFER_FULL + 0x059, // 0x0b4 = 180 - + 0x0b0, // 0x0b5 = 181 - JUMP_IF_FLAG_0_SET + 0x0ba, // 0x0b6 = 182 - + 0x011, // 0x0b7 = 183 - START_IT_NEXUS_LOSS_TIMER + 0x00f, // 0x0b8 = 184 - PATHWAY_BLOCKED_CNT_RESET + 0x00e, // 0x0b9 = 185 - START_ARB_WAIT_TIMER + 0x0cb, // 0x0ba = 186 - JUMP_IF_FREEZE_ACTIVE + 0x0fb, // 0x0bb = 187 - + 0x001, // 0x0bc = 188 - OPEN_REQUEST + 0x000, // 0x0bd = 189 - NO_OP + 0x000, // 0x0be = 190 - NO_OP + 0x000, // 0x0bf = 191 - NO_OP + 0x000, // 0x0c0 = 192 - NO_OP + 0x090, // 0x0c1 = 193 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_ACCEPT + 0x0e7, // 0x0c2 = 194 - + 0x095, // 0x0c3 = 195 - JUMP_IF_OPEN_STATUS_EQUAL_RATE_NOT_SUPPORTED + 0x0ec, // 0x0c4 = 196 - + 0x099, // 0x0c5 = 197 - JUMP_IF_OPEN_STATUS_EQUAL_PROTOCOL_NOT_SUPPORTED + 0x0ef, // 0x0c6 = 198 - + 0x09b, // 0x0c7 = 199 - JUMP_IF_OPEN_STATUS_EQUAL_WRONG_DESTINATION + 0x0f2, // 0x0c8 = 200 - + 0x094, // 0x0c9 = 201 - JUMP_IF_OPEN_STATUS_EQUAL_BREAK_RECEIVED + 0x0ba, // 0x0ca = 202 - + 0x093, // 0x0cb = 203 - JUMP_IF_OPEN_STATUS_EQUAL_BAD_DESTINATION + 0x0f5, // 0x0cc = 204 - + 0x09f, // 0x0cd = 205 - JUMP_IF_IT_NEXUS_LOSS_TIMEOUT + 0x0f8, // 0x0ce = 206 - + 0x09a, // 0x0cf = 207 - JUMP_IF_OPEN_STATUS_EQUAL_STP_RESOURCE_BUSY + 0x0ba, // 0x0d0 = 208 - + 0x096, // 0x0d1 = 209 - JUMP_IF_OPEN_STATUS_EQUAL_NO_DESTINATION + 0x0f5, // 0x0d2 = 210 - + 0x097, // 0x0d3 = 211 - JUMP_IF_OPEN_STATUS_EQUAL_PATHWAY_BLOCKED + 0x100, // 0x0d4 = 212 - + 0x098, // 0x0d5 = 213 - JUMP_IF_OPEN_STATUS_EQUAL_RETRY + 0x0ba, // 0x0d6 = 214 - + 0x092, // 0x0d7 = 215 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_TIMEOUT + 0x0ba, // 0x0d8 = 216 - + 0x0a4, // 0x0d9 = 217 - JUMP_IF_CONNECTION_ACTIVE_SET + 0x0e1, // 0x0da = 218 - + 0x0be, // 0x0db = 219 - JUMP_IF_PHY_READY + 0x0c1, // 0x0dc = 220 - + 0x01b, // 0x0dd = 221 - SET_OPEN_STATUS_PHY_NOT_RDY + 0x01c, // 0x0de = 222 - SOFT_RESET + 0x0ff, // 0x0df = 223 - JUMP + 0x001, // 0x0e0 = 224 - + 0x0a0, // 0x0e1 = 225 - JUMP_IF_CONNECTION_PROFILE_OPEN_EQUAL + 0x0e7, // 0x0e2 = 226 - + 0x000, // 0x0e3 = 227 - NO_OP + 0x000, // 0x0e4 = 228 - NO_OP + 0x0ff, // 0x0e5 = 229 - JUMP + 0x086, // 0x0e6 = 230 - + 0x013, // 0x0e7 = 231 - SET_OPEN_STATUS_NORMAL + 0x000, // 0x0e8 = 232 - NO_OP + 0x000, // 0x0e9 = 233 - NO_OP + 0x0ff, // 0x0ea = 234 - JUMP + 0x02b, // 0x0eb = 235 - + 0x017, // 0x0ec = 236 - SET_OPEN_STATUS_BAD_RATE + 0x0ff, // 0x0ed = 237 - JUMP + 0x0fc, // 0x0ee = 238 - + 0x018, // 0x0ef = 239 - SET_OPEN_STATUS_BAD_PROTOCOL + 0x0ff, // 0x0f0 = 240 - JUMP + 0x0fc, // 0x0f1 = 241 - + 0x01a, // 0x0f2 = 242 - SET_OPEN_STATUS_WRONG_DEST + 0x0ff, // 0x0f3 = 243 - JUMP + 0x0fc, // 0x0f4 = 244 - + 0x015, // 0x0f5 = 245 - SET_OPEN_STATUS_BAD_DEST + 0x0ff, // 0x0f6 = 246 - JUMP + 0x0fc, // 0x0f7 = 247 - + 0x014, // 0x0f8 = 248 - SET_OPEN_STATUS_IT_NEXUS_LOSS + 0x0ff, // 0x0f9 = 249 - JUMP + 0x0fc, // 0x0fa = 250 - + 0x024, // 0x0fb = 251 - SET_OPEN_STATUS_FREEZE + 0x000, // 0x0fc = 252 - NO_OP + 0x000, // 0x0fd = 253 - NO_OP + 0x0ff, // 0x0fe = 254 - JUMP + 0x059, // 0x0ff = 255 - + 0x010, // 0x100 = 256 - PATHWAY_BLOCKED_CNT_INC + 0x0ff, // 0x101 = 257 - JUMP + 0x0ba, // 0x102 = 258 - + 0x000, // 0x103 = 259 - NO_OP + 0x000, // 0x104 = 260 - NO_OP + 0x000, // 0x105 = 261 - NO_OP + 0x000, // 0x106 = 262 - NO_OP + 0x000, // 0x107 = 263 - NO_OP + 0x000, // 0x108 = 264 - NO_OP + 0x000, // 0x109 = 265 - NO_OP + 0x000, // 0x10a = 266 - NO_OP + 0x000, // 0x10b = 267 - NO_OP + 0x000, // 0x10c = 268 - NO_OP + 0x000, // 0x10d = 269 - NO_OP + 0x000, // 0x10e = 270 - NO_OP + 0x000, // 0x10f = 271 - NO_OP + 0x000, // 0x110 = 272 - NO_OP + 0x000, // 0x111 = 273 - NO_OP + 0x000, // 0x112 = 274 - NO_OP + 0x000, // 0x113 = 275 - NO_OP + 0x000, // 0x114 = 276 - NO_OP + 0x000, // 0x115 = 277 - NO_OP + 0x000, // 0x116 = 278 - NO_OP + 0x000, // 0x117 = 279 - NO_OP + 0x000, // 0x118 = 280 - NO_OP + 0x000, // 0x119 = 281 - NO_OP + 0x000, // 0x11a = 282 - NO_OP + 0x000, // 0x11b = 283 - NO_OP + 0x000, // 0x11c = 284 - NO_OP + 0x000, // 0x11d = 285 - NO_OP + 0x000, // 0x11e = 286 - NO_OP + 0x000, // 0x11f = 287 - NO_OP + 0x000, // 0x120 = 288 - NO_OP + 0x000, // 0x121 = 289 - NO_OP + 0x000, // 0x122 = 290 - NO_OP + 0x000, // 0x123 = 291 - NO_OP + 0x000, // 0x124 = 292 - NO_OP + 0x000, // 0x125 = 293 - NO_OP + 0x000, // 0x126 = 294 - NO_OP + 0x000, // 0x127 = 295 - NO_OP + 0x000, // 0x128 = 296 - NO_OP + 0x000, // 0x129 = 297 - NO_OP + 0x000, // 0x12a = 298 - NO_OP + 0x000, // 0x12b = 299 - NO_OP + 0x000, // 0x12c = 300 - NO_OP + 0x000, // 0x12d = 301 - NO_OP + 0x000, // 0x12e = 302 - NO_OP + 0x000, // 0x12f = 303 - NO_OP + 0x000, // 0x130 = 304 - NO_OP + 0x000, // 0x131 = 305 - NO_OP + 0x000, // 0x132 = 306 - NO_OP + 0x000, // 0x133 = 307 - NO_OP + 0x000, // 0x134 = 308 - NO_OP + 0x000, // 0x135 = 309 - NO_OP + 0x000, // 0x136 = 310 - NO_OP + 0x000, // 0x137 = 311 - NO_OP + 0x000, // 0x138 = 312 - NO_OP + 0x000, // 0x139 = 313 - NO_OP + 0x000, // 0x13a = 314 - NO_OP + 0x000, // 0x13b = 315 - NO_OP + 0x000, // 0x13c = 316 - NO_OP + 0x000, // 0x13d = 317 - NO_OP + 0x000, // 0x13e = 318 - NO_OP + 0x000, // 0x13f = 319 - NO_OP + 0x000, // 0x140 = 320 - NO_OP + 0x000, // 0x141 = 321 - NO_OP + 0x000, // 0x142 = 322 - NO_OP + 0x000, // 0x143 = 323 - NO_OP + 0x000, // 0x144 = 324 - NO_OP + 0x000, // 0x145 = 325 - NO_OP + 0x000, // 0x146 = 326 - NO_OP + 0x000, // 0x147 = 327 - NO_OP + 0x000, // 0x148 = 328 - NO_OP + 0x000, // 0x149 = 329 - NO_OP + 0x000, // 0x14a = 330 - NO_OP + 0x000, // 0x14b = 331 - NO_OP + 0x000, // 0x14c = 332 - NO_OP + 0x000, // 0x14d = 333 - NO_OP + 0x000, // 0x14e = 334 - NO_OP + 0x000, // 0x14f = 335 - NO_OP + 0x000, // 0x150 = 336 - NO_OP + 0x000, // 0x151 = 337 - NO_OP + 0x000, // 0x152 = 338 - NO_OP + 0x000, // 0x153 = 339 - NO_OP + 0x000, // 0x154 = 340 - NO_OP + 0x000, // 0x155 = 341 - NO_OP + 0x000, // 0x156 = 342 - NO_OP + 0x000, // 0x157 = 343 - NO_OP + 0x000, // 0x158 = 344 - NO_OP + 0x000, // 0x159 = 345 - NO_OP + 0x000, // 0x15a = 346 - NO_OP + 0x000, // 0x15b = 347 - NO_OP + 0x000, // 0x15c = 348 - NO_OP + 0x000, // 0x15d = 349 - NO_OP + 0x000, // 0x15e = 350 - NO_OP + 0x000, // 0x15f = 351 - NO_OP + 0x000, // 0x160 = 352 - NO_OP + 0x000, // 0x161 = 353 - NO_OP + 0x000, // 0x162 = 354 - NO_OP + 0x000, // 0x163 = 355 - NO_OP + 0x000, // 0x164 = 356 - NO_OP + 0x000, // 0x165 = 357 - NO_OP + 0x000, // 0x166 = 358 - NO_OP + 0x000, // 0x167 = 359 - NO_OP + 0x000, // 0x168 = 360 - NO_OP + 0x000, // 0x169 = 361 - NO_OP + 0x000, // 0x16a = 362 - NO_OP + 0x000, // 0x16b = 363 - NO_OP + 0x000, // 0x16c = 364 - NO_OP + 0x000, // 0x16d = 365 - NO_OP + 0x000, // 0x16e = 366 - NO_OP + 0x000, // 0x16f = 367 - NO_OP + 0x000, // 0x170 = 368 - NO_OP + 0x000, // 0x171 = 369 - NO_OP + 0x000, // 0x172 = 370 - NO_OP + 0x000, // 0x173 = 371 - NO_OP + 0x000, // 0x174 = 372 - NO_OP + 0x000, // 0x175 = 373 - NO_OP + 0x000, // 0x176 = 374 - NO_OP + 0x000, // 0x177 = 375 - NO_OP + 0x000, // 0x178 = 376 - NO_OP + 0x000, // 0x179 = 377 - NO_OP + 0x000, // 0x17a = 378 - NO_OP + 0x000, // 0x17b = 379 - NO_OP + 0x000, // 0x17c = 380 - NO_OP + 0x000, // 0x17d = 381 - NO_OP + 0x000, // 0x17e = 382 - NO_OP + 0x000, // 0x17f = 383 - NO_OP + 0x000, // 0x180 = 384 - NO_OP + 0x000, // 0x181 = 385 - NO_OP + 0x000, // 0x182 = 386 - NO_OP + 0x000, // 0x183 = 387 - NO_OP + 0x000, // 0x184 = 388 - NO_OP + 0x000, // 0x185 = 389 - NO_OP + 0x000, // 0x186 = 390 - NO_OP + 0x000, // 0x187 = 391 - NO_OP + 0x000, // 0x188 = 392 - NO_OP + 0x000, // 0x189 = 393 - NO_OP + 0x000, // 0x18a = 394 - NO_OP + 0x000, // 0x18b = 395 - NO_OP + 0x000, // 0x18c = 396 - NO_OP + 0x000, // 0x18d = 397 - NO_OP + 0x000, // 0x18e = 398 - NO_OP + 0x000, // 0x18f = 399 - NO_OP + 0x000, // 0x190 = 400 - NO_OP + 0x000, // 0x191 = 401 - NO_OP + 0x000, // 0x192 = 402 - NO_OP + 0x000, // 0x193 = 403 - NO_OP + 0x000, // 0x194 = 404 - NO_OP + 0x000, // 0x195 = 405 - NO_OP + 0x000, // 0x196 = 406 - NO_OP + 0x000, // 0x197 = 407 - NO_OP + 0x000, // 0x198 = 408 - NO_OP + 0x000, // 0x199 = 409 - NO_OP + 0x000, // 0x19a = 410 - NO_OP + 0x000, // 0x19b = 411 - NO_OP + 0x000, // 0x19c = 412 - NO_OP + 0x000, // 0x19d = 413 - NO_OP + 0x000, // 0x19e = 414 - NO_OP + 0x000, // 0x19f = 415 - NO_OP + 0x000, // 0x1a0 = 416 - NO_OP + 0x000, // 0x1a1 = 417 - NO_OP + 0x000, // 0x1a2 = 418 - NO_OP + 0x000, // 0x1a3 = 419 - NO_OP + 0x000, // 0x1a4 = 420 - NO_OP + 0x000, // 0x1a5 = 421 - NO_OP + 0x000, // 0x1a6 = 422 - NO_OP + 0x000, // 0x1a7 = 423 - NO_OP + 0x000, // 0x1a8 = 424 - NO_OP + 0x000, // 0x1a9 = 425 - NO_OP + 0x000, // 0x1aa = 426 - NO_OP + 0x000, // 0x1ab = 427 - NO_OP + 0x000, // 0x1ac = 428 - NO_OP + 0x000, // 0x1ad = 429 - NO_OP + 0x000, // 0x1ae = 430 - NO_OP + 0x000, // 0x1af = 431 - NO_OP + 0x000, // 0x1b0 = 432 - NO_OP + 0x000, // 0x1b1 = 433 - NO_OP + 0x000, // 0x1b2 = 434 - NO_OP + 0x000, // 0x1b3 = 435 - NO_OP + 0x000, // 0x1b4 = 436 - NO_OP + 0x000, // 0x1b5 = 437 - NO_OP + 0x000, // 0x1b6 = 438 - NO_OP + 0x000, // 0x1b7 = 439 - NO_OP + 0x000, // 0x1b8 = 440 - NO_OP + 0x000, // 0x1b9 = 441 - NO_OP + 0x000, // 0x1ba = 442 - NO_OP + 0x000, // 0x1bb = 443 - NO_OP + 0x000, // 0x1bc = 444 - NO_OP + 0x000, // 0x1bd = 445 - NO_OP + 0x000, // 0x1be = 446 - NO_OP + 0x000, // 0x1bf = 447 - NO_OP + 0x000, // 0x1c0 = 448 - NO_OP + 0x000, // 0x1c1 = 449 - NO_OP + 0x000, // 0x1c2 = 450 - NO_OP + 0x000, // 0x1c3 = 451 - NO_OP + 0x000, // 0x1c4 = 452 - NO_OP + 0x000, // 0x1c5 = 453 - NO_OP + 0x000, // 0x1c6 = 454 - NO_OP + 0x000, // 0x1c7 = 455 - NO_OP + 0x000, // 0x1c8 = 456 - NO_OP + 0x000, // 0x1c9 = 457 - NO_OP + 0x000, // 0x1ca = 458 - NO_OP + 0x000, // 0x1cb = 459 - NO_OP + 0x000, // 0x1cc = 460 - NO_OP + 0x000, // 0x1cd = 461 - NO_OP + 0x000, // 0x1ce = 462 - NO_OP + 0x000, // 0x1cf = 463 - NO_OP + 0x000, // 0x1d0 = 464 - NO_OP + 0x000, // 0x1d1 = 465 - NO_OP + 0x000, // 0x1d2 = 466 - NO_OP + 0x000, // 0x1d3 = 467 - NO_OP + 0x000, // 0x1d4 = 468 - NO_OP + 0x000, // 0x1d5 = 469 - NO_OP + 0x000, // 0x1d6 = 470 - NO_OP + 0x000, // 0x1d7 = 471 - NO_OP + 0x000, // 0x1d8 = 472 - NO_OP + 0x000, // 0x1d9 = 473 - NO_OP + 0x000, // 0x1da = 474 - NO_OP + 0x000, // 0x1db = 475 - NO_OP + 0x000, // 0x1dc = 476 - NO_OP + 0x000, // 0x1dd = 477 - NO_OP + 0x000, // 0x1de = 478 - NO_OP + 0x000, // 0x1df = 479 - NO_OP + 0x000, // 0x1e0 = 480 - NO_OP + 0x000, // 0x1e1 = 481 - NO_OP + 0x000, // 0x1e2 = 482 - NO_OP + 0x000, // 0x1e3 = 483 - NO_OP + 0x000, // 0x1e4 = 484 - NO_OP + 0x000, // 0x1e5 = 485 - NO_OP + 0x000, // 0x1e6 = 486 - NO_OP + 0x000, // 0x1e7 = 487 - NO_OP + 0x000, // 0x1e8 = 488 - NO_OP + 0x000, // 0x1e9 = 489 - NO_OP + 0x000, // 0x1ea = 490 - NO_OP + 0x000, // 0x1eb = 491 - NO_OP + 0x000, // 0x1ec = 492 - NO_OP + 0x000, // 0x1ed = 493 - NO_OP + 0x000, // 0x1ee = 494 - NO_OP + 0x000, // 0x1ef = 495 - NO_OP + 0x000, // 0x1f0 = 496 - NO_OP + 0x000, // 0x1f1 = 497 - NO_OP + 0x000, // 0x1f2 = 498 - NO_OP + 0x000, // 0x1f3 = 499 - NO_OP + 0x000, // 0x1f4 = 500 - NO_OP + 0x000, // 0x1f5 = 501 - NO_OP + 0x000, // 0x1f6 = 502 - NO_OP + 0x000, // 0x1f7 = 503 - NO_OP + 0x000, // 0x1f8 = 504 - NO_OP + 0x000, // 0x1f9 = 505 - NO_OP + 0x000, // 0x1fa = 506 - NO_OP + 0x000, // 0x1fb = 507 - NO_OP + 0x000, // 0x1fc = 508 - NO_OP + 0x000, // 0x1fd = 509 - NO_OP + 0x000, // 0x1fe = 510 - NO_OP + 0x000 // 0x1ff = 511 - NO_OP +}; + +/* WCS 022406 */ +bit32 wcsImage022406[] = +{ +0x00d, // 00000 = 0 - PHY_RESET_START +0x0be, // 0x001 = 1 - JUMP_IF_PHY_READY +0x009, // 0x002 = 2 - +0x0ae, // 0x003 = 3 - JUMP_IF_HARD_RESET_PRIMITIVE +0x010, // 0x004 = 4 - +0x0af, // 0x005 = 5 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x01e, // 0x006 = 6 - +0x0ff, // 0x007 = 7 - JUMP +0x001, // 0x008 = 8 - +0x00c, // 0x009 = 9 - SEND_ID_FRAME +0x0ae, // 0x00a = 10 - JUMP_IF_HARD_RESET_PRIMITIVE +0x010, // 0x00b = 11 - +0x0af, // 0x00c = 12 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x023, // 0x00d = 13 - +0x0ff, // 0x00e = 14 - JUMP +0x00a, // 0x00f = 15 - +0x01c, // 0x010 = 16 - SOFT_RESET +0x00d, // 0x011 = 17 - PHY_RESET_START +0x0be, // 0x012 = 18 - JUMP_IF_PHY_READY +0x016, // 0x013 = 19 - +0x0af, // 0x014 = 20 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x01b, // 0x015 = 21 - +0x00c, // 0x016 = 22 - SEND_ID_FRAME +0x0af, // 0x017 = 23 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x023, // 0x018 = 24 - +0x0ff, // 0x019 = 25 - JUMP +0x017, // 0x01a = 26 - +0x00c, // 0x01b = 27 - SEND_ID_FRAME +0x0ff, // 0x01c = 28 - JUMP +0x023, // 0x01d = 29 - +0x0be, // 0x01e = 30 - JUMP_IF_PHY_READY +0x022, // 0x01f = 31 - +0x0ff, // 0x020 = 32 - JUMP +0x01e, // 0x021 = 33 - +0x00c, // 0x022 = 34 - SEND_ID_FRAME +0x000, // 0x023 = 35 - NO_OP +0x000, // 0x024 = 36 - NO_OP +0x000, // 0x025 = 37 - NO_OP +0x000, // 0x026 = 38 - NO_OP +0x000, // 0x027 = 39 - NO_OP +0x000, // 0x028 = 40 - NO_OP +0x0ff, // 0x029 = 41 - JUMP +0x055, // 0x02a = 42 - +0x000, // 0x02b = 43 - NO_OP +0x0c9, // 0x02c = 44 - JUMP_IF_RX_BUFFER_FULL_TIMEOUT +0x052, // 0x02d = 45 - +0x0a5, // 0x02e = 46 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_GOOD +0x041, // 0x02f = 47 - +0x0a6, // 0x030 = 48 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_NAK +0x046, // 0x031 = 49 - +0x0a7, // 0x032 = 50 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_ACK_NAK_TIMEOUT +0x049, // 0x033 = 51 - +0x0a8, // 0x034 = 52 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_BREAK +0x04f, // 0x035 = 53 - +0x0aa, // 0x036 = 54 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_CREDIT_TIMEOUT +0x04c, // 0x037 = 55 - +0x0c5, // 0x038 = 56 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_SMP_ERR +0x04f, // 0x039 = 57 - +0x0ca, // 0x03a = 58 - JUMP_IF_CLOSE_REQ +0x08a, // 0x03b = 59 - +0x0be, // 0x03c = 60 - JUMP_IF_PHY_READY +0x02c, // 0x03d = 61 - +0x01c, // 0x03e = 62 - SOFT_RESET +0x0ff, // 0x03f = 63 - JUMP +0x001, // 0x040 = 64 - +0x01d, // 0x041 = 65 - ADVANCE +0x0c3, // 0x042 = 66 - JUMP_IF_SMP_PROTOCOL +0x08a, // 0x043 = 67 - +0x0ff, // 0x044 = 68 - JUMP +0x055, // 0x045 = 69 - +0x01d, // 0x046 = 70 - ADVANCE +0x0ff, // 0x047 = 71 - JUMP +0x055, // 0x048 = 72 - +0x01d, // 0x049 = 73 - ADVANCE +0x0ff, // 0x04a = 74 - JUMP +0x0a9, // 0x04b = 75 - +0x01d, // 0x04c = 76 - ADVANCE +0x0ff, // 0x04d = 77 - JUMP +0x0ac, // 0x04e = 78 - +0x01d, // 0x04f = 79 - ADVANCE +0x0ff, // 0x050 = 80 - JUMP +0x09d, // 0x051 = 81 - +0x022, // 0x052 = 82 - SEND_CREDIT_BLOCK +0x0ff, // 0x053 = 83 - JUMP +0x02e, // 0x054 = 84 - +0x0c8, // 0x055 = 85 - JUMP_IF_HIP_REQ +0x061, // 0x056 = 86 - +0x0c6, // 0x057 = 87 - JUMP_IF_SFO_REQ +0x066, // 0x058 = 88 - +0x0c7, // 0x059 = 89 - JUMP_IF_DOC_REQ +0x06b, // 0x05a = 90 - +0x0a3, // 0x05b = 91 - JUMP_IF_CONNECTION_OPEN_SLAVE_FLAG_SET +0x082, // 0x05c = 92 - +0x0a2, // 0x05d = 93 - JUMP_IF_CONNECTION_OPEN_MASTER_FLAG_SET +0x08a, // 0x05e = 94 - +0x0ff, // 0x05f = 95 - JUMP +0x055, // 0x060 = 96 - +0x020, // 0x061 = 97 - SELECT_HIP +0x000, // 0x062 = 98 - NO_OP +0x000, // 0x063 = 99 - NO_OP +0x0ff, // 0x064 = 100 - JUMP +0x06e, // 0x065 = 101 - +0x01e, // 0x066 = 102 - SELECT_SFO +0x000, // 0x067 = 103 - NO_OP +0x000, // 0x068 = 104 - NO_OP +0x0ff, // 0x069 = 105 - JUMP +0x06e, // 0x06a = 106 - +0x01f, // 0x06b = 107 - SELECT_DOC +0x000, // 0x06c = 108 - NO_OP +0x000, // 0x06d = 109 - NO_OP +0x0a4, // 0x06e = 110 - JUMP_IF_CONNECTION_ACTIVE_SET +0x072, // 0x06f = 111 - +0x0ff, // 0x070 = 112 - JUMP +0x0af, // 0x071 = 113 - +0x0a0, // 0x072 = 114 - JUMP_IF_CONNECTION_PROFILE_OPEN_EQUAL +0x078, // 0x073 = 115 - +0x0a3, // 0x074 = 116 - JUMP_IF_CONNECTION_OPEN_SLAVE_FLAG_SET +0x082, // 0x075 = 117 - +0x0ff, // 0x076 = 118 - JUMP +0x08a, // 0x077 = 119 - +0x0cb, // 0x078 = 120 - JUMP_IF_FREEZE_ACTIVE +0x07d, // 0x079 = 121 - +0x013, // 0x07a = 122 - SET_OPEN_STATUS_NORMAL +0x0ff, // 0x07b = 123 - JUMP +0x02b, // 0x07c = 124 - +0x024, // 0x07d = 125 - SET_OPEN_STATUS_FREEZE +0x000, // 0x07e = 126 - NO_OP +0x000, // 0x07f = 127 - NO_OP +0x0ff, // 0x080 = 128 - JUMP +0x055, // 0x081 = 129 - +0x0c3, // 0x082 = 130 - JUMP_IF_SMP_PROTOCOL +0x086, // 0x083 = 131 - +0x0ff, // 0x084 = 132 - JUMP +0x08a, // 0x085 = 133 - +0x0c4, // 0x086 = 134 - JUMP_IF_SMP_FRAME_ERR_RECEIVED +0x09d, // 0x087 = 135 - +0x0ff, // 0x088 = 136 - JUMP +0x055, // 0x089 = 137 - +0x004, // 0x08a = 138 - CLOSE_NORMAL +0x000, // 0x08b = 139 - NO_OP +0x000, // 0x08c = 140 - NO_OP +0x000, // 0x08d = 141 - NO_OP +0x000, // 0x08e = 142 - NO_OP +0x0c9, // 0x08f = 143 - JUMP_IF_RX_BUFFER_FULL_TIMEOUT +0x09a, // 0x090 = 144 - +0x0c0, // 0x091 = 145 - JUMP_IF_CLOSE_STATUS_EQUAL_ANY +0x055, // 0x092 = 146 - +0x0bc, // 0x093 = 147 - JUMP_IF_BREAK_RECEIVED +0x09d, // 0x094 = 148 - +0x0be, // 0x095 = 149 - JUMP_IF_PHY_READY +0x08b, // 0x096 = 150 - +0x01c, // 0x097 = 151 - SOFT_RESET +0x0ff, // 0x098 = 152 - JUMP +0x001, // 0x099 = 153 - +0x022, // 0x09a = 154 - SEND_CREDIT_BLOCK +0x0ff, // 0x09b = 155 - JUMP +0x08b, // 0x09c = 156 - +0x007, // 0x09d = 157 - CLOSE_BREAK +0x000, // 0x09e = 158 - NO_OP +0x000, // 0x09f = 159 - NO_OP +0x000, // 0x0a0 = 160 - NO_OP +0x000, // 0x0a1 = 161 - NO_OP +0x0c0, // 0x0a2 = 162 - JUMP_IF_CLOSE_STATUS_EQUAL_ANY +0x055, // 0x0a3 = 163 - +0x0be, // 0x0a4 = 164 - JUMP_IF_PHY_READY +0x09e, // 0x0a5 = 165 - +0x01c, // 0x0a6 = 166 - SOFT_RESET +0x0ff, // 0x0a7 = 167 - JUMP +0x001, // 0x0a8 = 168 - +0x005, // 0x0a9 = 169 - CLOSE_ACK_NAK_TIMEOUT +0x0ff, // 0x0aa = 170 - JUMP +0x08b, // 0x0ab = 171 - +0x006, // 0x0ac = 172 - CLOSE_CREDIT_TIMEOUT +0x0ff, // 0x0ad = 173 - JUMP +0x08b, // 0x0ae = 174 - +0x0cc, // 0x0af = 175 - JUMP_IF_RX_BUFFER_FULL +0x055, // 0x0b0 = 176 - +0x0b7, // 0x0b1 = 177 - JUMP_IF_FLAG_7_SET +0x0b6, // 0x0b2 = 178 - +0x011, // 0x0b3 = 179 - START_IT_NEXUS_LOSS_TIMER +0x00f, // 0x0b4 = 180 - PATHWAY_BLOCKED_CNT_RESET +0x00e, // 0x0b5 = 181 - START_ARB_WAIT_TIMER +0x0cb, // 0x0b6 = 182 - JUMP_IF_FREEZE_ACTIVE +0x0f9, // 0x0b7 = 183 - +0x001, // 0x0b8 = 184 - OPEN_REQUEST +0x080, // 0x0b9 = 185 - SET_FLAG +0x080, // 0x0ba = 186 - +0x000, // 0x0bb = 187 - NO_OP +0x000, // 0x0bc = 188 - NO_OP +0x000, // 0x0bd = 189 - NO_OP +0x090, // 0x0be = 190 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_ACCEPT +0x0e4, // 0x0bf = 191 - +0x095, // 0x0c0 = 192 - JUMP_IF_OPEN_STATUS_EQUAL_RATE_NOT_SUPPORTED +0x0ea, // 0x0c1 = 193 - +0x099, // 0x0c2 = 194 - JUMP_IF_OPEN_STATUS_EQUAL_PROTOCOL_NOT_SUPPORTED +0x0ed, // 0x0c3 = 195 - +0x09b, // 0x0c4 = 196 - JUMP_IF_OPEN_STATUS_EQUAL_WRONG_DESTINATION +0x0f0, // 0x0c5 = 197 - +0x094, // 0x0c6 = 198 - JUMP_IF_OPEN_STATUS_EQUAL_BREAK_RECEIVED +0x0b6, // 0x0c7 = 199 - +0x093, // 0x0c8 = 200 - JUMP_IF_OPEN_STATUS_EQUAL_BAD_DESTINATION +0x0f3, // 0x0c9 = 201 - +0x09f, // 0x0ca = 202 - JUMP_IF_IT_NEXUS_LOSS_TIMEOUT +0x0f6, // 0x0cb = 203 - +0x09a, // 0x0cc = 204 - JUMP_IF_OPEN_STATUS_EQUAL_STP_RESOURCE_BUSY +0x0b6, // 0x0cd = 205 - +0x096, // 0x0ce = 206 - JUMP_IF_OPEN_STATUS_EQUAL_NO_DESTINATION +0x0f3, // 0x0cf = 207 - +0x097, // 0x0d0 = 208 - JUMP_IF_OPEN_STATUS_EQUAL_PATHWAY_BLOCKED +0x0fe, // 0x0d1 = 209 - +0x098, // 0x0d2 = 210 - JUMP_IF_OPEN_STATUS_EQUAL_RETRY +0x0b6, // 0x0d3 = 211 - +0x092, // 0x0d4 = 212 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_TIMEOUT +0x0b6, // 0x0d5 = 213 - +0x0a4, // 0x0d6 = 214 - JUMP_IF_CONNECTION_ACTIVE_SET +0x0de, // 0x0d7 = 215 - +0x0be, // 0x0d8 = 216 - JUMP_IF_PHY_READY +0x0be, // 0x0d9 = 217 - +0x01b, // 0x0da = 218 - SET_OPEN_STATUS_PHY_NOT_RDY +0x01c, // 0x0db = 219 - SOFT_RESET +0x0ff, // 0x0dc = 220 - JUMP +0x001, // 0x0dd = 221 - +0x0a0, // 0x0de = 222 - JUMP_IF_CONNECTION_PROFILE_OPEN_EQUAL +0x0e4, // 0x0df = 223 - +0x000, // 0x0e0 = 224 - NO_OP +0x000, // 0x0e1 = 225 - NO_OP +0x0ff, // 0x0e2 = 226 - JUMP +0x082, // 0x0e3 = 227 - +0x013, // 0x0e4 = 228 - SET_OPEN_STATUS_NORMAL +0x081, // 0x0e5 = 229 - CLEAR_FLAG +0x080, // 0x0e6 = 230 - +0x000, // 0x0e7 = 231 - NO_OP +0x0ff, // 0x0e8 = 232 - JUMP +0x02b, // 0x0e9 = 233 - +0x017, // 0x0ea = 234 - SET_OPEN_STATUS_BAD_RATE +0x0ff, // 0x0eb = 235 - JUMP +0x0fa, // 0x0ec = 236 - +0x018, // 0x0ed = 237 - SET_OPEN_STATUS_BAD_PROTOCOL +0x0ff, // 0x0ee = 238 - JUMP +0x0fa, // 0x0ef = 239 - +0x01a, // 0x0f0 = 240 - SET_OPEN_STATUS_WRONG_DEST +0x0ff, // 0x0f1 = 241 - JUMP +0x0fa, // 0x0f2 = 242 - +0x015, // 0x0f3 = 243 - SET_OPEN_STATUS_BAD_DEST +0x0ff, // 0x0f4 = 244 - JUMP +0x0fa, // 0x0f5 = 245 - +0x014, // 0x0f6 = 246 - SET_OPEN_STATUS_IT_NEXUS_LOSS +0x0ff, // 0x0f7 = 247 - JUMP +0x0fa, // 0x0f8 = 248 - +0x024, // 0x0f9 = 249 - SET_OPEN_STATUS_FREEZE +0x000, // 0x0fa = 250 - NO_OP +0x000, // 0x0fb = 251 - NO_OP +0x0ff, // 0x0fc = 252 - JUMP +0x055, // 0x0fd = 253 - +0x010, // 0x0fe = 254 - PATHWAY_BLOCKED_CNT_INC +0x0ff, // 0x0ff = 255 - JUMP +0x0b6, // 0x100 = 256 - +0x000, // 0x101 = 257 - NO_OP +0x000, // 0x102 = 258 - NO_OP +0x000, // 0x103 = 259 - NO_OP +0x000, // 0x104 = 260 - NO_OP +0x000, // 0x105 = 261 - NO_OP +0x000, // 0x106 = 262 - NO_OP +0x000, // 0x107 = 263 - NO_OP +0x000, // 0x108 = 264 - NO_OP +0x000, // 0x109 = 265 - NO_OP +0x000, // 0x10a = 266 - NO_OP +0x000, // 0x10b = 267 - NO_OP +0x000, // 0x10c = 268 - NO_OP +0x000, // 0x10d = 269 - NO_OP +0x000, // 0x10e = 270 - NO_OP +0x000, // 0x10f = 271 - NO_OP +0x000, // 0x110 = 272 - NO_OP +0x000, // 0x111 = 273 - NO_OP +0x000, // 0x112 = 274 - NO_OP +0x000, // 0x113 = 275 - NO_OP +0x000, // 0x114 = 276 - NO_OP +0x000, // 0x115 = 277 - NO_OP +0x000, // 0x116 = 278 - NO_OP +0x000, // 0x117 = 279 - NO_OP +0x000, // 0x118 = 280 - NO_OP +0x000, // 0x119 = 281 - NO_OP +0x000, // 0x11a = 282 - NO_OP +0x000, // 0x11b = 283 - NO_OP +0x000, // 0x11c = 284 - NO_OP +0x000, // 0x11d = 285 - NO_OP +0x000, // 0x11e = 286 - NO_OP +0x000, // 0x11f = 287 - NO_OP +0x000, // 0x120 = 288 - NO_OP +0x000, // 0x121 = 289 - NO_OP +0x000, // 0x122 = 290 - NO_OP +0x000, // 0x123 = 291 - NO_OP +0x000, // 0x124 = 292 - NO_OP +0x000, // 0x125 = 293 - NO_OP +0x000, // 0x126 = 294 - NO_OP +0x000, // 0x127 = 295 - NO_OP +0x000, // 0x128 = 296 - NO_OP +0x000, // 0x129 = 297 - NO_OP +0x000, // 0x12a = 298 - NO_OP +0x000, // 0x12b = 299 - NO_OP +0x000, // 0x12c = 300 - NO_OP +0x000, // 0x12d = 301 - NO_OP +0x000, // 0x12e = 302 - NO_OP +0x000, // 0x12f = 303 - NO_OP +0x000, // 0x130 = 304 - NO_OP +0x000, // 0x131 = 305 - NO_OP +0x000, // 0x132 = 306 - NO_OP +0x000, // 0x133 = 307 - NO_OP +0x000, // 0x134 = 308 - NO_OP +0x000, // 0x135 = 309 - NO_OP +0x000, // 0x136 = 310 - NO_OP +0x000, // 0x137 = 311 - NO_OP +0x000, // 0x138 = 312 - NO_OP +0x000, // 0x139 = 313 - NO_OP +0x000, // 0x13a = 314 - NO_OP +0x000, // 0x13b = 315 - NO_OP +0x000, // 0x13c = 316 - NO_OP +0x000, // 0x13d = 317 - NO_OP +0x000, // 0x13e = 318 - NO_OP +0x000, // 0x13f = 319 - NO_OP +0x000, // 0x140 = 320 - NO_OP +0x000, // 0x141 = 321 - NO_OP +0x000, // 0x142 = 322 - NO_OP +0x000, // 0x143 = 323 - NO_OP +0x000, // 0x144 = 324 - NO_OP +0x000, // 0x145 = 325 - NO_OP +0x000, // 0x146 = 326 - NO_OP +0x000, // 0x147 = 327 - NO_OP +0x000, // 0x148 = 328 - NO_OP +0x000, // 0x149 = 329 - NO_OP +0x000, // 0x14a = 330 - NO_OP +0x000, // 0x14b = 331 - NO_OP +0x000, // 0x14c = 332 - NO_OP +0x000, // 0x14d = 333 - NO_OP +0x000, // 0x14e = 334 - NO_OP +0x000, // 0x14f = 335 - NO_OP +0x000, // 0x150 = 336 - NO_OP +0x000, // 0x151 = 337 - NO_OP +0x000, // 0x152 = 338 - NO_OP +0x000, // 0x153 = 339 - NO_OP +0x000, // 0x154 = 340 - NO_OP +0x000, // 0x155 = 341 - NO_OP +0x000, // 0x156 = 342 - NO_OP +0x000, // 0x157 = 343 - NO_OP +0x000, // 0x158 = 344 - NO_OP +0x000, // 0x159 = 345 - NO_OP +0x000, // 0x15a = 346 - NO_OP +0x000, // 0x15b = 347 - NO_OP +0x000, // 0x15c = 348 - NO_OP +0x000, // 0x15d = 349 - NO_OP +0x000, // 0x15e = 350 - NO_OP +0x000, // 0x15f = 351 - NO_OP +0x000, // 0x160 = 352 - NO_OP +0x000, // 0x161 = 353 - NO_OP +0x000, // 0x162 = 354 - NO_OP +0x000, // 0x163 = 355 - NO_OP +0x000, // 0x164 = 356 - NO_OP +0x000, // 0x165 = 357 - NO_OP +0x000, // 0x166 = 358 - NO_OP +0x000, // 0x167 = 359 - NO_OP +0x000, // 0x168 = 360 - NO_OP +0x000, // 0x169 = 361 - NO_OP +0x000, // 0x16a = 362 - NO_OP +0x000, // 0x16b = 363 - NO_OP +0x000, // 0x16c = 364 - NO_OP +0x000, // 0x16d = 365 - NO_OP +0x000, // 0x16e = 366 - NO_OP +0x000, // 0x16f = 367 - NO_OP +0x000, // 0x170 = 368 - NO_OP +0x000, // 0x171 = 369 - NO_OP +0x000, // 0x172 = 370 - NO_OP +0x000, // 0x173 = 371 - NO_OP +0x000, // 0x174 = 372 - NO_OP +0x000, // 0x175 = 373 - NO_OP +0x000, // 0x176 = 374 - NO_OP +0x000, // 0x177 = 375 - NO_OP +0x000, // 0x178 = 376 - NO_OP +0x000, // 0x179 = 377 - NO_OP +0x000, // 0x17a = 378 - NO_OP +0x000, // 0x17b = 379 - NO_OP +0x000, // 0x17c = 380 - NO_OP +0x000, // 0x17d = 381 - NO_OP +0x000, // 0x17e = 382 - NO_OP +0x000, // 0x17f = 383 - NO_OP +0x000, // 0x180 = 384 - NO_OP +0x000, // 0x181 = 385 - NO_OP +0x000, // 0x182 = 386 - NO_OP +0x000, // 0x183 = 387 - NO_OP +0x000, // 0x184 = 388 - NO_OP +0x000, // 0x185 = 389 - NO_OP +0x000, // 0x186 = 390 - NO_OP +0x000, // 0x187 = 391 - NO_OP +0x000, // 0x188 = 392 - NO_OP +0x000, // 0x189 = 393 - NO_OP +0x000, // 0x18a = 394 - NO_OP +0x000, // 0x18b = 395 - NO_OP +0x000, // 0x18c = 396 - NO_OP +0x000, // 0x18d = 397 - NO_OP +0x000, // 0x18e = 398 - NO_OP +0x000, // 0x18f = 399 - NO_OP +0x000, // 0x190 = 400 - NO_OP +0x000, // 0x191 = 401 - NO_OP +0x000, // 0x192 = 402 - NO_OP +0x000, // 0x193 = 403 - NO_OP +0x000, // 0x194 = 404 - NO_OP +0x000, // 0x195 = 405 - NO_OP +0x000, // 0x196 = 406 - NO_OP +0x000, // 0x197 = 407 - NO_OP +0x000, // 0x198 = 408 - NO_OP +0x000, // 0x199 = 409 - NO_OP +0x000, // 0x19a = 410 - NO_OP +0x000, // 0x19b = 411 - NO_OP +0x000, // 0x19c = 412 - NO_OP +0x000, // 0x19d = 413 - NO_OP +0x000, // 0x19e = 414 - NO_OP +0x000, // 0x19f = 415 - NO_OP +0x000, // 0x1a0 = 416 - NO_OP +0x000, // 0x1a1 = 417 - NO_OP +0x000, // 0x1a2 = 418 - NO_OP +0x000, // 0x1a3 = 419 - NO_OP +0x000, // 0x1a4 = 420 - NO_OP +0x000, // 0x1a5 = 421 - NO_OP +0x000, // 0x1a6 = 422 - NO_OP +0x000, // 0x1a7 = 423 - NO_OP +0x000, // 0x1a8 = 424 - NO_OP +0x000, // 0x1a9 = 425 - NO_OP +0x000, // 0x1aa = 426 - NO_OP +0x000, // 0x1ab = 427 - NO_OP +0x000, // 0x1ac = 428 - NO_OP +0x000, // 0x1ad = 429 - NO_OP +0x000, // 0x1ae = 430 - NO_OP +0x000, // 0x1af = 431 - NO_OP +0x000, // 0x1b0 = 432 - NO_OP +0x000, // 0x1b1 = 433 - NO_OP +0x000, // 0x1b2 = 434 - NO_OP +0x000, // 0x1b3 = 435 - NO_OP +0x000, // 0x1b4 = 436 - NO_OP +0x000, // 0x1b5 = 437 - NO_OP +0x000, // 0x1b6 = 438 - NO_OP +0x000, // 0x1b7 = 439 - NO_OP +0x000, // 0x1b8 = 440 - NO_OP +0x000, // 0x1b9 = 441 - NO_OP +0x000, // 0x1ba = 442 - NO_OP +0x000, // 0x1bb = 443 - NO_OP +0x000, // 0x1bc = 444 - NO_OP +0x000, // 0x1bd = 445 - NO_OP +0x000, // 0x1be = 446 - NO_OP +0x000, // 0x1bf = 447 - NO_OP +0x000, // 0x1c0 = 448 - NO_OP +0x000, // 0x1c1 = 449 - NO_OP +0x000, // 0x1c2 = 450 - NO_OP +0x000, // 0x1c3 = 451 - NO_OP +0x000, // 0x1c4 = 452 - NO_OP +0x000, // 0x1c5 = 453 - NO_OP +0x000, // 0x1c6 = 454 - NO_OP +0x000, // 0x1c7 = 455 - NO_OP +0x000, // 0x1c8 = 456 - NO_OP +0x000, // 0x1c9 = 457 - NO_OP +0x000, // 0x1ca = 458 - NO_OP +0x000, // 0x1cb = 459 - NO_OP +0x000, // 0x1cc = 460 - NO_OP +0x000, // 0x1cd = 461 - NO_OP +0x000, // 0x1ce = 462 - NO_OP +0x000, // 0x1cf = 463 - NO_OP +0x000, // 0x1d0 = 464 - NO_OP +0x000, // 0x1d1 = 465 - NO_OP +0x000, // 0x1d2 = 466 - NO_OP +0x000, // 0x1d3 = 467 - NO_OP +0x000, // 0x1d4 = 468 - NO_OP +0x000, // 0x1d5 = 469 - NO_OP +0x000, // 0x1d6 = 470 - NO_OP +0x000, // 0x1d7 = 471 - NO_OP +0x000, // 0x1d8 = 472 - NO_OP +0x000, // 0x1d9 = 473 - NO_OP +0x000, // 0x1da = 474 - NO_OP +0x000, // 0x1db = 475 - NO_OP +0x000, // 0x1dc = 476 - NO_OP +0x000, // 0x1dd = 477 - NO_OP +0x000, // 0x1de = 478 - NO_OP +0x000, // 0x1df = 479 - NO_OP +0x000, // 0x1e0 = 480 - NO_OP +0x000, // 0x1e1 = 481 - NO_OP +0x000, // 0x1e2 = 482 - NO_OP +0x000, // 0x1e3 = 483 - NO_OP +0x000, // 0x1e4 = 484 - NO_OP +0x000, // 0x1e5 = 485 - NO_OP +0x000, // 0x1e6 = 486 - NO_OP +0x000, // 0x1e7 = 487 - NO_OP +0x000, // 0x1e8 = 488 - NO_OP +0x000, // 0x1e9 = 489 - NO_OP +0x000, // 0x1ea = 490 - NO_OP +0x000, // 0x1eb = 491 - NO_OP +0x000, // 0x1ec = 492 - NO_OP +0x000, // 0x1ed = 493 - NO_OP +0x000, // 0x1ee = 494 - NO_OP +0x000, // 0x1ef = 495 - NO_OP +0x000, // 0x1f0 = 496 - NO_OP +0x000, // 0x1f1 = 497 - NO_OP +0x000, // 0x1f2 = 498 - NO_OP +0x000, // 0x1f3 = 499 - NO_OP +0x000, // 0x1f4 = 500 - NO_OP +0x000, // 0x1f5 = 501 - NO_OP +0x000, // 0x1f6 = 502 - NO_OP +0x000, // 0x1f7 = 503 - NO_OP +0x000, // 0x1f8 = 504 - NO_OP +0x000, // 0x1f9 = 505 - NO_OP +0x000, // 0x1fa = 506 - NO_OP +0x000, // 0x1fb = 507 - NO_OP +0x000, // 0x1fc = 508 - NO_OP +0x000, // 0x1fd = 509 - NO_OP +0x000, // 0x1fe = 510 - NO_OP +0x000, // 0x1ff = 511 - NO_OP +}; + +/* WCS 031606 */ +bit32 wcsImage031606[] = +{ +0x00d, // 00000 = 0 - PHY_RESET_START +0x0be, // 0x001 = 1 - JUMP_IF_PHY_READY +0x009, // 0x002 = 2 - +0x0ae, // 0x003 = 3 - JUMP_IF_HARD_RESET_PRIMITIVE +0x010, // 0x004 = 4 - +0x0af, // 0x005 = 5 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x01e, // 0x006 = 6 - +0x0ff, // 0x007 = 7 - JUMP +0x001, // 0x008 = 8 - +0x00c, // 0x009 = 9 - SEND_ID_FRAME +0x0ae, // 0x00a = 10 - JUMP_IF_HARD_RESET_PRIMITIVE +0x010, // 0x00b = 11 - +0x0af, // 0x00c = 12 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x023, // 0x00d = 13 - +0x0ff, // 0x00e = 14 - JUMP +0x00a, // 0x00f = 15 - +0x01c, // 0x010 = 16 - SOFT_RESET +0x00d, // 0x011 = 17 - PHY_RESET_START +0x0be, // 0x012 = 18 - JUMP_IF_PHY_READY +0x016, // 0x013 = 19 - +0x0af, // 0x014 = 20 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x01b, // 0x015 = 21 - +0x00c, // 0x016 = 22 - SEND_ID_FRAME +0x0af, // 0x017 = 23 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x023, // 0x018 = 24 - +0x0ff, // 0x019 = 25 - JUMP +0x017, // 0x01a = 26 - +0x00c, // 0x01b = 27 - SEND_ID_FRAME +0x0ff, // 0x01c = 28 - JUMP +0x023, // 0x01d = 29 - +0x0be, // 0x01e = 30 - JUMP_IF_PHY_READY +0x022, // 0x01f = 31 - +0x0ff, // 0x020 = 32 - JUMP +0x01e, // 0x021 = 33 - +0x00c, // 0x022 = 34 - SEND_ID_FRAME +0x000, // 0x023 = 35 - NO_OP +0x000, // 0x024 = 36 - NO_OP +0x000, // 0x025 = 37 - NO_OP +0x000, // 0x026 = 38 - NO_OP +0x000, // 0x027 = 39 - NO_OP +0x000, // 0x028 = 40 - NO_OP +0x0ff, // 0x029 = 41 - JUMP +0x05b, // 0x02a = 42 - +0x000, // 0x02b = 43 - NO_OP +0x0c9, // 0x02c = 44 - JUMP_IF_RX_BUFFER_FULL_TIMEOUT +0x058, // 0x02d = 45 - +0x0a5, // 0x02e = 46 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_GOOD +0x041, // 0x02f = 47 - +0x0a6, // 0x030 = 48 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_NAK +0x048, // 0x031 = 49 - +0x0a7, // 0x032 = 50 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_ACK_NAK_TIMEOUT +0x04b, // 0x033 = 51 - +0x0a8, // 0x034 = 52 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_BREAK +0x055, // 0x035 = 53 - +0x0aa, // 0x036 = 54 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_CREDIT_TIMEOUT +0x050, // 0x037 = 55 - +0x0c5, // 0x038 = 56 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_SMP_ERR +0x055, // 0x039 = 57 - +0x0ca, // 0x03a = 58 - JUMP_IF_CLOSE_REQ +0x09c, // 0x03b = 59 - +0x0be, // 0x03c = 60 - JUMP_IF_PHY_READY +0x02c, // 0x03d = 61 - +0x01c, // 0x03e = 62 - SOFT_RESET +0x0ff, // 0x03f = 63 - JUMP +0x001, // 0x040 = 64 - +0x01d, // 0x041 = 65 - ADVANCE +0x0bc, // 0x042 = 66 - JUMP_IF_BREAK_RECEIVED +0x0af, // 0x043 = 67 - +0x0c3, // 0x044 = 68 - JUMP_IF_SMP_PROTOCOL +0x09c, // 0x045 = 69 - +0x0ff, // 0x046 = 70 - JUMP +0x05b, // 0x047 = 71 - +0x01d, // 0x048 = 72 - ADVANCE +0x0ff, // 0x049 = 73 - JUMP +0x05b, // 0x04a = 74 - +0x01d, // 0x04b = 75 - ADVANCE +0x0bc, // 0x04c = 76 - JUMP_IF_BREAK_RECEIVED +0x0af, // 0x04d = 77 - +0x0ff, // 0x04e = 78 - JUMP +0x0bb, // 0x04f = 79 - +0x01d, // 0x050 = 80 - ADVANCE +0x0bc, // 0x051 = 81 - JUMP_IF_BREAK_RECEIVED +0x0af, // 0x052 = 82 - +0x0ff, // 0x053 = 83 - JUMP +0x0be, // 0x054 = 84 - +0x01d, // 0x055 = 85 - ADVANCE +0x0ff, // 0x056 = 86 - JUMP +0x0af, // 0x057 = 87 - +0x022, // 0x058 = 88 - SEND_CREDIT_BLOCK +0x0ff, // 0x059 = 89 - JUMP +0x02e, // 0x05a = 90 - +0x0bc, // 0x05b = 91 - JUMP_IF_BREAK_RECEIVED +0x0af, // 0x05c = 92 - +0x0c8, // 0x05d = 93 - JUMP_IF_HIP_REQ +0x069, // 0x05e = 94 - +0x0c6, // 0x05f = 95 - JUMP_IF_SFO_REQ +0x06e, // 0x060 = 96 - +0x0c7, // 0x061 = 97 - JUMP_IF_DOC_REQ +0x073, // 0x062 = 98 - +0x0a3, // 0x063 = 99 - JUMP_IF_CONNECTION_OPEN_SLAVE_FLAG_SET +0x08a, // 0x064 = 100 - +0x0a2, // 0x065 = 101 - JUMP_IF_CONNECTION_OPEN_MASTER_FLAG_SET +0x09c, // 0x066 = 102 - +0x0ff, // 0x067 = 103 - JUMP +0x05b, // 0x068 = 104 - +0x020, // 0x069 = 105 - SELECT_HIP +0x000, // 0x06a = 106 - NO_OP +0x000, // 0x06b = 107 - NO_OP +0x0ff, // 0x06c = 108 - JUMP +0x076, // 0x06d = 109 - +0x01e, // 0x06e = 110 - SELECT_SFO +0x000, // 0x06f = 111 - NO_OP +0x000, // 0x070 = 112 - NO_OP +0x0ff, // 0x071 = 113 - JUMP +0x076, // 0x072 = 114 - +0x01f, // 0x073 = 115 - SELECT_DOC +0x000, // 0x074 = 116 - NO_OP +0x000, // 0x075 = 117 - NO_OP +0x0a4, // 0x076 = 118 - JUMP_IF_CONNECTION_ACTIVE_SET +0x07a, // 0x077 = 119 - +0x0ff, // 0x078 = 120 - JUMP +0x0c1, // 0x079 = 121 - +0x0a0, // 0x07a = 122 - JUMP_IF_CONNECTION_PROFILE_OPEN_EQUAL +0x080, // 0x07b = 123 - +0x0a3, // 0x07c = 124 - JUMP_IF_CONNECTION_OPEN_SLAVE_FLAG_SET +0x08a, // 0x07d = 125 - +0x0ff, // 0x07e = 126 - JUMP +0x09c, // 0x07f = 127 - +0x0cb, // 0x080 = 128 - JUMP_IF_FREEZE_ACTIVE +0x085, // 0x081 = 129 - +0x013, // 0x082 = 130 - SET_OPEN_STATUS_NORMAL +0x0ff, // 0x083 = 131 - JUMP +0x02b, // 0x084 = 132 - +0x024, // 0x085 = 133 - SET_OPEN_STATUS_FREEZE +0x000, // 0x086 = 134 - NO_OP +0x000, // 0x087 = 135 - NO_OP +0x0ff, // 0x088 = 136 - JUMP +0x05b, // 0x089 = 137 - +0x0c3, // 0x08a = 138 - JUMP_IF_SMP_PROTOCOL +0x092, // 0x08b = 139 - +0x0d2, // 0x08c = 140 - JUMP_IF_STP_CONNECTION_ACTIVE +0x096, // 0x08d = 141 - +0x0d1, // 0x08e = 142 - JUMP_IF_IDLE_TIMER_TIMEOUT +0x09a, // 0x08f = 143 - +0x0ff, // 0x090 = 144 - JUMP +0x05b, // 0x091 = 145 - +0x0c4, // 0x092 = 146 - JUMP_IF_SMP_FRAME_ERR_RECEIVED +0x0af, // 0x093 = 147 - +0x0ff, // 0x094 = 148 - JUMP +0x05b, // 0x095 = 149 - +0x0d1, // 0x096 = 150 - JUMP_IF_IDLE_TIMER_TIMEOUT +0x09a, // 0x097 = 151 - +0x0ff, // 0x098 = 152 - JUMP +0x05b, // 0x099 = 153 - +0x0ff, // 0x09a = 154 - JUMP +0x09c, // 0x09b = 155 - +0x004, // 0x09c = 156 - CLOSE_NORMAL +0x000, // 0x09d = 157 - NO_OP +0x000, // 0x09e = 158 - NO_OP +0x000, // 0x09f = 159 - NO_OP +0x000, // 0x0a0 = 160 - NO_OP +0x0c9, // 0x0a1 = 161 - JUMP_IF_RX_BUFFER_FULL_TIMEOUT +0x0ac, // 0x0a2 = 162 - +0x0c0, // 0x0a3 = 163 - JUMP_IF_CLOSE_STATUS_EQUAL_ANY +0x05b, // 0x0a4 = 164 - +0x0bc, // 0x0a5 = 165 - JUMP_IF_BREAK_RECEIVED +0x0af, // 0x0a6 = 166 - +0x0be, // 0x0a7 = 167 - JUMP_IF_PHY_READY +0x09d, // 0x0a8 = 168 - +0x01c, // 0x0a9 = 169 - SOFT_RESET +0x0ff, // 0x0aa = 170 - JUMP +0x001, // 0x0ab = 171 - +0x022, // 0x0ac = 172 - SEND_CREDIT_BLOCK +0x0ff, // 0x0ad = 173 - JUMP +0x09d, // 0x0ae = 174 - +0x007, // 0x0af = 175 - CLOSE_BREAK +0x000, // 0x0b0 = 176 - NO_OP +0x000, // 0x0b1 = 177 - NO_OP +0x000, // 0x0b2 = 178 - NO_OP +0x000, // 0x0b3 = 179 - NO_OP +0x0c0, // 0x0b4 = 180 - JUMP_IF_CLOSE_STATUS_EQUAL_ANY +0x05b, // 0x0b5 = 181 - +0x0be, // 0x0b6 = 182 - JUMP_IF_PHY_READY +0x0b0, // 0x0b7 = 183 - +0x01c, // 0x0b8 = 184 - SOFT_RESET +0x0ff, // 0x0b9 = 185 - JUMP +0x001, // 0x0ba = 186 - +0x005, // 0x0bb = 187 - CLOSE_ACK_NAK_TIMEOUT +0x0ff, // 0x0bc = 188 - JUMP +0x09d, // 0x0bd = 189 - +0x006, // 0x0be = 190 - CLOSE_CREDIT_TIMEOUT +0x0ff, // 0x0bf = 191 - JUMP +0x09d, // 0x0c0 = 192 - +0x0cc, // 0x0c1 = 193 - JUMP_IF_RX_BUFFER_FULL +0x05b, // 0x0c2 = 194 - +0x0b7, // 0x0c3 = 195 - JUMP_IF_FLAG_7_SET +0x0c8, // 0x0c4 = 196 - +0x011, // 0x0c5 = 197 - START_IT_NEXUS_LOSS_TIMER +0x00f, // 0x0c6 = 198 - PATHWAY_BLOCKED_CNT_RESET +0x00e, // 0x0c7 = 199 - START_ARB_WAIT_TIMER +0x0cb, // 0x0c8 = 200 - JUMP_IF_FREEZE_ACTIVE +0x107, // 0x0c9 = 201 - +0x001, // 0x0ca = 202 - OPEN_REQUEST +0x080, // 0x0cb = 203 - SET_FLAG +0x080, // 0x0cc = 204 - +0x090, // 0x0cd = 205 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_ACCEPT +0x0f3, // 0x0ce = 206 - +0x095, // 0x0cf = 207 - JUMP_IF_OPEN_STATUS_EQUAL_RATE_NOT_SUPPORTED +0x0f8, // 0x0d0 = 208 - +0x099, // 0x0d1 = 209 - JUMP_IF_OPEN_STATUS_EQUAL_PROTOCOL_NOT_SUPPORTED +0x0fb, // 0x0d2 = 210 - +0x09b, // 0x0d3 = 211 - JUMP_IF_OPEN_STATUS_EQUAL_WRONG_DESTINATION +0x0fe, // 0x0d4 = 212 - +0x094, // 0x0d5 = 213 - JUMP_IF_OPEN_STATUS_EQUAL_BREAK_RECEIVED +0x0c8, // 0x0d6 = 214 - +0x093, // 0x0d7 = 215 - JUMP_IF_OPEN_STATUS_EQUAL_BAD_DESTINATION +0x101, // 0x0d8 = 216 - +0x09f, // 0x0d9 = 217 - JUMP_IF_IT_NEXUS_LOSS_TIMEOUT +0x104, // 0x0da = 218 - +0x09a, // 0x0db = 219 - JUMP_IF_OPEN_STATUS_EQUAL_STP_RESOURCE_BUSY +0x0c8, // 0x0dc = 220 - +0x096, // 0x0dd = 221 - JUMP_IF_OPEN_STATUS_EQUAL_NO_DESTINATION +0x101, // 0x0de = 222 - +0x097, // 0x0df = 223 - JUMP_IF_OPEN_STATUS_EQUAL_PATHWAY_BLOCKED +0x10c, // 0x0e0 = 224 - +0x098, // 0x0e1 = 225 - JUMP_IF_OPEN_STATUS_EQUAL_RETRY +0x0c8, // 0x0e2 = 226 - +0x092, // 0x0e3 = 227 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_TIMEOUT +0x0c8, // 0x0e4 = 228 - +0x0a4, // 0x0e5 = 229 - JUMP_IF_CONNECTION_ACTIVE_SET +0x0ed, // 0x0e6 = 230 - +0x0be, // 0x0e7 = 231 - JUMP_IF_PHY_READY +0x0cd, // 0x0e8 = 232 - +0x01b, // 0x0e9 = 233 - SET_OPEN_STATUS_PHY_NOT_RDY +0x01c, // 0x0ea = 234 - SOFT_RESET +0x0ff, // 0x0eb = 235 - JUMP +0x001, // 0x0ec = 236 - +0x0a0, // 0x0ed = 237 - JUMP_IF_CONNECTION_PROFILE_OPEN_EQUAL +0x0f3, // 0x0ee = 238 - +0x000, // 0x0ef = 239 - NO_OP +0x000, // 0x0f0 = 240 - NO_OP +0x0ff, // 0x0f1 = 241 - JUMP +0x05b, // 0x0f2 = 242 - +0x013, // 0x0f3 = 243 - SET_OPEN_STATUS_NORMAL +0x081, // 0x0f4 = 244 - CLEAR_FLAG +0x080, // 0x0f5 = 245 - +0x0ff, // 0x0f6 = 246 - JUMP +0x02b, // 0x0f7 = 247 - +0x017, // 0x0f8 = 248 - SET_OPEN_STATUS_BAD_RATE +0x0ff, // 0x0f9 = 249 - JUMP +0x108, // 0x0fa = 250 - +0x018, // 0x0fb = 251 - SET_OPEN_STATUS_BAD_PROTOCOL +0x0ff, // 0x0fc = 252 - JUMP +0x108, // 0x0fd = 253 - +0x01a, // 0x0fe = 254 - SET_OPEN_STATUS_WRONG_DEST +0x0ff, // 0x0ff = 255 - JUMP +0x108, // 0x100 = 256 - +0x015, // 0x101 = 257 - SET_OPEN_STATUS_BAD_DEST +0x0ff, // 0x102 = 258 - JUMP +0x108, // 0x103 = 259 - +0x014, // 0x104 = 260 - SET_OPEN_STATUS_IT_NEXUS_LOSS +0x0ff, // 0x105 = 261 - JUMP +0x108, // 0x106 = 262 - +0x024, // 0x107 = 263 - SET_OPEN_STATUS_FREEZE +0x000, // 0x108 = 264 - NO_OP +0x000, // 0x109 = 265 - NO_OP +0x0ff, // 0x10a = 266 - JUMP +0x05b, // 0x10b = 267 - +0x010, // 0x10c = 268 - PATHWAY_BLOCKED_CNT_INC +0x0ff, // 0x10d = 269 - JUMP +0x0c8, // 0x10e = 270 - +0x000, // 0x10f = 271 - NO_OP +0x000, // 0x110 = 272 - NO_OP +0x000, // 0x111 = 273 - NO_OP +0x000, // 0x112 = 274 - NO_OP +0x000, // 0x113 = 275 - NO_OP +0x000, // 0x114 = 276 - NO_OP +0x000, // 0x115 = 277 - NO_OP +0x000, // 0x116 = 278 - NO_OP +0x000, // 0x117 = 279 - NO_OP +0x000, // 0x118 = 280 - NO_OP +0x000, // 0x119 = 281 - NO_OP +0x000, // 0x11a = 282 - NO_OP +0x000, // 0x11b = 283 - NO_OP +0x000, // 0x11c = 284 - NO_OP +0x000, // 0x11d = 285 - NO_OP +0x000, // 0x11e = 286 - NO_OP +0x000, // 0x11f = 287 - NO_OP +0x000, // 0x120 = 288 - NO_OP +0x000, // 0x121 = 289 - NO_OP +0x000, // 0x122 = 290 - NO_OP +0x000, // 0x123 = 291 - NO_OP +0x000, // 0x124 = 292 - NO_OP +0x000, // 0x125 = 293 - NO_OP +0x000, // 0x126 = 294 - NO_OP +0x000, // 0x127 = 295 - NO_OP +0x000, // 0x128 = 296 - NO_OP +0x000, // 0x129 = 297 - NO_OP +0x000, // 0x12a = 298 - NO_OP +0x000, // 0x12b = 299 - NO_OP +0x000, // 0x12c = 300 - NO_OP +0x000, // 0x12d = 301 - NO_OP +0x000, // 0x12e = 302 - NO_OP +0x000, // 0x12f = 303 - NO_OP +0x000, // 0x130 = 304 - NO_OP +0x000, // 0x131 = 305 - NO_OP +0x000, // 0x132 = 306 - NO_OP +0x000, // 0x133 = 307 - NO_OP +0x000, // 0x134 = 308 - NO_OP +0x000, // 0x135 = 309 - NO_OP +0x000, // 0x136 = 310 - NO_OP +0x000, // 0x137 = 311 - NO_OP +0x000, // 0x138 = 312 - NO_OP +0x000, // 0x139 = 313 - NO_OP +0x000, // 0x13a = 314 - NO_OP +0x000, // 0x13b = 315 - NO_OP +0x000, // 0x13c = 316 - NO_OP +0x000, // 0x13d = 317 - NO_OP +0x000, // 0x13e = 318 - NO_OP +0x000, // 0x13f = 319 - NO_OP +0x000, // 0x140 = 320 - NO_OP +0x000, // 0x141 = 321 - NO_OP +0x000, // 0x142 = 322 - NO_OP +0x000, // 0x143 = 323 - NO_OP +0x000, // 0x144 = 324 - NO_OP +0x000, // 0x145 = 325 - NO_OP +0x000, // 0x146 = 326 - NO_OP +0x000, // 0x147 = 327 - NO_OP +0x000, // 0x148 = 328 - NO_OP +0x000, // 0x149 = 329 - NO_OP +0x000, // 0x14a = 330 - NO_OP +0x000, // 0x14b = 331 - NO_OP +0x000, // 0x14c = 332 - NO_OP +0x000, // 0x14d = 333 - NO_OP +0x000, // 0x14e = 334 - NO_OP +0x000, // 0x14f = 335 - NO_OP +0x000, // 0x150 = 336 - NO_OP +0x000, // 0x151 = 337 - NO_OP +0x000, // 0x152 = 338 - NO_OP +0x000, // 0x153 = 339 - NO_OP +0x000, // 0x154 = 340 - NO_OP +0x000, // 0x155 = 341 - NO_OP +0x000, // 0x156 = 342 - NO_OP +0x000, // 0x157 = 343 - NO_OP +0x000, // 0x158 = 344 - NO_OP +0x000, // 0x159 = 345 - NO_OP +0x000, // 0x15a = 346 - NO_OP +0x000, // 0x15b = 347 - NO_OP +0x000, // 0x15c = 348 - NO_OP +0x000, // 0x15d = 349 - NO_OP +0x000, // 0x15e = 350 - NO_OP +0x000, // 0x15f = 351 - NO_OP +0x000, // 0x160 = 352 - NO_OP +0x000, // 0x161 = 353 - NO_OP +0x000, // 0x162 = 354 - NO_OP +0x000, // 0x163 = 355 - NO_OP +0x000, // 0x164 = 356 - NO_OP +0x000, // 0x165 = 357 - NO_OP +0x000, // 0x166 = 358 - NO_OP +0x000, // 0x167 = 359 - NO_OP +0x000, // 0x168 = 360 - NO_OP +0x000, // 0x169 = 361 - NO_OP +0x000, // 0x16a = 362 - NO_OP +0x000, // 0x16b = 363 - NO_OP +0x000, // 0x16c = 364 - NO_OP +0x000, // 0x16d = 365 - NO_OP +0x000, // 0x16e = 366 - NO_OP +0x000, // 0x16f = 367 - NO_OP +0x000, // 0x170 = 368 - NO_OP +0x000, // 0x171 = 369 - NO_OP +0x000, // 0x172 = 370 - NO_OP +0x000, // 0x173 = 371 - NO_OP +0x000, // 0x174 = 372 - NO_OP +0x000, // 0x175 = 373 - NO_OP +0x000, // 0x176 = 374 - NO_OP +0x000, // 0x177 = 375 - NO_OP +0x000, // 0x178 = 376 - NO_OP +0x000, // 0x179 = 377 - NO_OP +0x000, // 0x17a = 378 - NO_OP +0x000, // 0x17b = 379 - NO_OP +0x000, // 0x17c = 380 - NO_OP +0x000, // 0x17d = 381 - NO_OP +0x000, // 0x17e = 382 - NO_OP +0x000, // 0x17f = 383 - NO_OP +0x000, // 0x180 = 384 - NO_OP +0x000, // 0x181 = 385 - NO_OP +0x000, // 0x182 = 386 - NO_OP +0x000, // 0x183 = 387 - NO_OP +0x000, // 0x184 = 388 - NO_OP +0x000, // 0x185 = 389 - NO_OP +0x000, // 0x186 = 390 - NO_OP +0x000, // 0x187 = 391 - NO_OP +0x000, // 0x188 = 392 - NO_OP +0x000, // 0x189 = 393 - NO_OP +0x000, // 0x18a = 394 - NO_OP +0x000, // 0x18b = 395 - NO_OP +0x000, // 0x18c = 396 - NO_OP +0x000, // 0x18d = 397 - NO_OP +0x000, // 0x18e = 398 - NO_OP +0x000, // 0x18f = 399 - NO_OP +0x000, // 0x190 = 400 - NO_OP +0x000, // 0x191 = 401 - NO_OP +0x000, // 0x192 = 402 - NO_OP +0x000, // 0x193 = 403 - NO_OP +0x000, // 0x194 = 404 - NO_OP +0x000, // 0x195 = 405 - NO_OP +0x000, // 0x196 = 406 - NO_OP +0x000, // 0x197 = 407 - NO_OP +0x000, // 0x198 = 408 - NO_OP +0x000, // 0x199 = 409 - NO_OP +0x000, // 0x19a = 410 - NO_OP +0x000, // 0x19b = 411 - NO_OP +0x000, // 0x19c = 412 - NO_OP +0x000, // 0x19d = 413 - NO_OP +0x000, // 0x19e = 414 - NO_OP +0x000, // 0x19f = 415 - NO_OP +0x000, // 0x1a0 = 416 - NO_OP +0x000, // 0x1a1 = 417 - NO_OP +0x000, // 0x1a2 = 418 - NO_OP +0x000, // 0x1a3 = 419 - NO_OP +0x000, // 0x1a4 = 420 - NO_OP +0x000, // 0x1a5 = 421 - NO_OP +0x000, // 0x1a6 = 422 - NO_OP +0x000, // 0x1a7 = 423 - NO_OP +0x000, // 0x1a8 = 424 - NO_OP +0x000, // 0x1a9 = 425 - NO_OP +0x000, // 0x1aa = 426 - NO_OP +0x000, // 0x1ab = 427 - NO_OP +0x000, // 0x1ac = 428 - NO_OP +0x000, // 0x1ad = 429 - NO_OP +0x000, // 0x1ae = 430 - NO_OP +0x000, // 0x1af = 431 - NO_OP +0x000, // 0x1b0 = 432 - NO_OP +0x000, // 0x1b1 = 433 - NO_OP +0x000, // 0x1b2 = 434 - NO_OP +0x000, // 0x1b3 = 435 - NO_OP +0x000, // 0x1b4 = 436 - NO_OP +0x000, // 0x1b5 = 437 - NO_OP +0x000, // 0x1b6 = 438 - NO_OP +0x000, // 0x1b7 = 439 - NO_OP +0x000, // 0x1b8 = 440 - NO_OP +0x000, // 0x1b9 = 441 - NO_OP +0x000, // 0x1ba = 442 - NO_OP +0x000, // 0x1bb = 443 - NO_OP +0x000, // 0x1bc = 444 - NO_OP +0x000, // 0x1bd = 445 - NO_OP +0x000, // 0x1be = 446 - NO_OP +0x000, // 0x1bf = 447 - NO_OP +0x000, // 0x1c0 = 448 - NO_OP +0x000, // 0x1c1 = 449 - NO_OP +0x000, // 0x1c2 = 450 - NO_OP +0x000, // 0x1c3 = 451 - NO_OP +0x000, // 0x1c4 = 452 - NO_OP +0x000, // 0x1c5 = 453 - NO_OP +0x000, // 0x1c6 = 454 - NO_OP +0x000, // 0x1c7 = 455 - NO_OP +0x000, // 0x1c8 = 456 - NO_OP +0x000, // 0x1c9 = 457 - NO_OP +0x000, // 0x1ca = 458 - NO_OP +0x000, // 0x1cb = 459 - NO_OP +0x000, // 0x1cc = 460 - NO_OP +0x000, // 0x1cd = 461 - NO_OP +0x000, // 0x1ce = 462 - NO_OP +0x000, // 0x1cf = 463 - NO_OP +0x000, // 0x1d0 = 464 - NO_OP +0x000, // 0x1d1 = 465 - NO_OP +0x000, // 0x1d2 = 466 - NO_OP +0x000, // 0x1d3 = 467 - NO_OP +0x000, // 0x1d4 = 468 - NO_OP +0x000, // 0x1d5 = 469 - NO_OP +0x000, // 0x1d6 = 470 - NO_OP +0x000, // 0x1d7 = 471 - NO_OP +0x000, // 0x1d8 = 472 - NO_OP +0x000, // 0x1d9 = 473 - NO_OP +0x000, // 0x1da = 474 - NO_OP +0x000, // 0x1db = 475 - NO_OP +0x000, // 0x1dc = 476 - NO_OP +0x000, // 0x1dd = 477 - NO_OP +0x000, // 0x1de = 478 - NO_OP +0x000, // 0x1df = 479 - NO_OP +0x000, // 0x1e0 = 480 - NO_OP +0x000, // 0x1e1 = 481 - NO_OP +0x000, // 0x1e2 = 482 - NO_OP +0x000, // 0x1e3 = 483 - NO_OP +0x000, // 0x1e4 = 484 - NO_OP +0x000, // 0x1e5 = 485 - NO_OP +0x000, // 0x1e6 = 486 - NO_OP +0x000, // 0x1e7 = 487 - NO_OP +0x000, // 0x1e8 = 488 - NO_OP +0x000, // 0x1e9 = 489 - NO_OP +0x000, // 0x1ea = 490 - NO_OP +0x000, // 0x1eb = 491 - NO_OP +0x000, // 0x1ec = 492 - NO_OP +0x000, // 0x1ed = 493 - NO_OP +0x000, // 0x1ee = 494 - NO_OP +0x000, // 0x1ef = 495 - NO_OP +0x000, // 0x1f0 = 496 - NO_OP +0x000, // 0x1f1 = 497 - NO_OP +0x000, // 0x1f2 = 498 - NO_OP +0x000, // 0x1f3 = 499 - NO_OP +0x000, // 0x1f4 = 500 - NO_OP +0x000, // 0x1f5 = 501 - NO_OP +0x000, // 0x1f6 = 502 - NO_OP +0x000, // 0x1f7 = 503 - NO_OP +0x000, // 0x1f8 = 504 - NO_OP +0x000, // 0x1f9 = 505 - NO_OP +0x000, // 0x1fa = 506 - NO_OP +0x000, // 0x1fb = 507 - NO_OP +0x000, // 0x1fc = 508 - NO_OP +0x000, // 0x1fd = 509 - NO_OP +0x000, // 0x1fe = 510 - NO_OP +0x000 // 0x1ff = 511 - NO_OP +}; + +/* WCS 032006 */ +bit32 wcsImage032006[] = +{ +0x00d, // 00000 = 0 - PHY_RESET_START +0x0be, // 0x001 = 1 - JUMP_IF_PHY_READY +0x009, // 0x002 = 2 - +0x0ae, // 0x003 = 3 - JUMP_IF_HARD_RESET_PRIMITIVE +0x010, // 0x004 = 4 - +0x0af, // 0x005 = 5 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x01e, // 0x006 = 6 - +0x0ff, // 0x007 = 7 - JUMP +0x001, // 0x008 = 8 - +0x00c, // 0x009 = 9 - SEND_ID_FRAME +0x0ae, // 0x00a = 10 - JUMP_IF_HARD_RESET_PRIMITIVE +0x010, // 0x00b = 11 - +0x0af, // 0x00c = 12 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x023, // 0x00d = 13 - +0x0ff, // 0x00e = 14 - JUMP +0x00a, // 0x00f = 15 - +0x01c, // 0x010 = 16 - SOFT_RESET +0x00d, // 0x011 = 17 - PHY_RESET_START +0x0be, // 0x012 = 18 - JUMP_IF_PHY_READY +0x016, // 0x013 = 19 - +0x0af, // 0x014 = 20 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x01b, // 0x015 = 21 - +0x00c, // 0x016 = 22 - SEND_ID_FRAME +0x0af, // 0x017 = 23 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x023, // 0x018 = 24 - +0x0ff, // 0x019 = 25 - JUMP +0x017, // 0x01a = 26 - +0x00c, // 0x01b = 27 - SEND_ID_FRAME +0x0ff, // 0x01c = 28 - JUMP +0x023, // 0x01d = 29 - +0x0be, // 0x01e = 30 - JUMP_IF_PHY_READY +0x022, // 0x01f = 31 - +0x0ff, // 0x020 = 32 - JUMP +0x01e, // 0x021 = 33 - +0x00c, // 0x022 = 34 - SEND_ID_FRAME +0x000, // 0x023 = 35 - NO_OP +0x000, // 0x024 = 36 - NO_OP +0x000, // 0x025 = 37 - NO_OP +0x000, // 0x026 = 38 - NO_OP +0x000, // 0x027 = 39 - NO_OP +0x000, // 0x028 = 40 - NO_OP +0x0ff, // 0x029 = 41 - JUMP +0x063, // 0x02a = 42 - +0x000, // 0x02b = 43 - NO_OP +0x0c9, // 0x02c = 44 - JUMP_IF_RX_BUFFER_FULL_TIMEOUT +0x058, // 0x02d = 45 - +0x0a5, // 0x02e = 46 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_GOOD +0x041, // 0x02f = 47 - +0x0a6, // 0x030 = 48 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_NAK +0x048, // 0x031 = 49 - +0x0a7, // 0x032 = 50 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_ACK_NAK_TIMEOUT +0x04b, // 0x033 = 51 - +0x0a8, // 0x034 = 52 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_BREAK +0x055, // 0x035 = 53 - +0x0aa, // 0x036 = 54 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_CREDIT_TIMEOUT +0x050, // 0x037 = 55 - +0x0c5, // 0x038 = 56 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_SMP_ERR +0x055, // 0x039 = 57 - +0x0ca, // 0x03a = 58 - JUMP_IF_CLOSE_REQ +0x0a4, // 0x03b = 59 - +0x0be, // 0x03c = 60 - JUMP_IF_PHY_READY +0x02c, // 0x03d = 61 - +0x01c, // 0x03e = 62 - SOFT_RESET +0x0ff, // 0x03f = 63 - JUMP +0x001, // 0x040 = 64 - +0x01d, // 0x041 = 65 - ADVANCE +0x0bc, // 0x042 = 66 - JUMP_IF_BREAK_RECEIVED +0x0b7, // 0x043 = 67 - +0x0c3, // 0x044 = 68 - JUMP_IF_SMP_PROTOCOL +0x0a4, // 0x045 = 69 - +0x0ff, // 0x046 = 70 - JUMP +0x05b, // 0x047 = 71 - +0x01d, // 0x048 = 72 - ADVANCE +0x0ff, // 0x049 = 73 - JUMP +0x05b, // 0x04a = 74 - +0x01d, // 0x04b = 75 - ADVANCE +0x0bc, // 0x04c = 76 - JUMP_IF_BREAK_RECEIVED +0x0b7, // 0x04d = 77 - +0x0ff, // 0x04e = 78 - JUMP +0x0c3, // 0x04f = 79 - +0x01d, // 0x050 = 80 - ADVANCE +0x0bc, // 0x051 = 81 - JUMP_IF_BREAK_RECEIVED +0x0b7, // 0x052 = 82 - +0x0ff, // 0x053 = 83 - JUMP +0x0c6, // 0x054 = 84 - +0x01d, // 0x055 = 85 - ADVANCE +0x0ff, // 0x056 = 86 - JUMP +0x0b7, // 0x057 = 87 - +0x022, // 0x058 = 88 - SEND_CREDIT_BLOCK +0x0ff, // 0x059 = 89 - JUMP +0x02e, // 0x05a = 90 - +0x083, // 0x05b = 91 - TIMER_START +0x002, // 0x05c = 92 - +0x000, // 0x05d = 93 - NO_OP +0x000, // 0x05e = 94 - NO_OP +0x0b8, // 0x05f = 95 - JUMP_IF_TIMER_EXPIRED +0x063, // 0x060 = 96 - +0x0ff, // 0x061 = 97 - JUMP +0x05d, // 0x062 = 98 - +0x0bc, // 0x063 = 99 - JUMP_IF_BREAK_RECEIVED +0x0b7, // 0x064 = 100 - +0x0c8, // 0x065 = 101 - JUMP_IF_HIP_REQ +0x071, // 0x066 = 102 - +0x0c6, // 0x067 = 103 - JUMP_IF_SFO_REQ +0x076, // 0x068 = 104 - +0x0c7, // 0x069 = 105 - JUMP_IF_DOC_REQ +0x07b, // 0x06a = 106 - +0x0a3, // 0x06b = 107 - JUMP_IF_CONNECTION_OPEN_SLAVE_FLAG_SET +0x092, // 0x06c = 108 - +0x0a2, // 0x06d = 109 - JUMP_IF_CONNECTION_OPEN_MASTER_FLAG_SET +0x0a4, // 0x06e = 110 - +0x0ff, // 0x06f = 111 - JUMP +0x063, // 0x070 = 112 - +0x020, // 0x071 = 113 - SELECT_HIP +0x000, // 0x072 = 114 - NO_OP +0x000, // 0x073 = 115 - NO_OP +0x0ff, // 0x074 = 116 - JUMP +0x07e, // 0x075 = 117 - +0x01e, // 0x076 = 118 - SELECT_SFO +0x000, // 0x077 = 119 - NO_OP +0x000, // 0x078 = 120 - NO_OP +0x0ff, // 0x079 = 121 - JUMP +0x07e, // 0x07a = 122 - +0x01f, // 0x07b = 123 - SELECT_DOC +0x000, // 0x07c = 124 - NO_OP +0x000, // 0x07d = 125 - NO_OP +0x0a4, // 0x07e = 126 - JUMP_IF_CONNECTION_ACTIVE_SET +0x082, // 0x07f = 127 - +0x0ff, // 0x080 = 128 - JUMP +0x0c9, // 0x081 = 129 - +0x0a0, // 0x082 = 130 - JUMP_IF_CONNECTION_PROFILE_OPEN_EQUAL +0x088, // 0x083 = 131 - +0x0a3, // 0x084 = 132 - JUMP_IF_CONNECTION_OPEN_SLAVE_FLAG_SET +0x092, // 0x085 = 133 - +0x0ff, // 0x086 = 134 - JUMP +0x0a4, // 0x087 = 135 - +0x0cb, // 0x088 = 136 - JUMP_IF_FREEZE_ACTIVE +0x08d, // 0x089 = 137 - +0x013, // 0x08a = 138 - SET_OPEN_STATUS_NORMAL +0x0ff, // 0x08b = 139 - JUMP +0x02b, // 0x08c = 140 - +0x024, // 0x08d = 141 - SET_OPEN_STATUS_FREEZE +0x000, // 0x08e = 142 - NO_OP +0x000, // 0x08f = 143 - NO_OP +0x0ff, // 0x090 = 144 - JUMP +0x063, // 0x091 = 145 - +0x0c3, // 0x092 = 146 - JUMP_IF_SMP_PROTOCOL +0x09a, // 0x093 = 147 - +0x0d2, // 0x094 = 148 - JUMP_IF_STP_CONNECTION_ACTIVE +0x09e, // 0x095 = 149 - +0x0d1, // 0x096 = 150 - JUMP_IF_IDLE_TIMER_TIMEOUT +0x0a2, // 0x097 = 151 - +0x0ff, // 0x098 = 152 - JUMP +0x063, // 0x099 = 153 - +0x0c4, // 0x09a = 154 - JUMP_IF_SMP_FRAME_ERR_RECEIVED +0x0b7, // 0x09b = 155 - +0x0ff, // 0x09c = 156 - JUMP +0x063, // 0x09d = 157 - +0x0d1, // 0x09e = 158 - JUMP_IF_IDLE_TIMER_TIMEOUT +0x0a2, // 0x09f = 159 - +0x0ff, // 0x0a0 = 160 - JUMP +0x063, // 0x0a1 = 161 - +0x0ff, // 0x0a2 = 162 - JUMP +0x0a4, // 0x0a3 = 163 - +0x004, // 0x0a4 = 164 - CLOSE_NORMAL +0x000, // 0x0a5 = 165 - NO_OP +0x000, // 0x0a6 = 166 - NO_OP +0x000, // 0x0a7 = 167 - NO_OP +0x000, // 0x0a8 = 168 - NO_OP +0x0c9, // 0x0a9 = 169 - JUMP_IF_RX_BUFFER_FULL_TIMEOUT +0x0b4, // 0x0aa = 170 - +0x0c0, // 0x0ab = 171 - JUMP_IF_CLOSE_STATUS_EQUAL_ANY +0x063, // 0x0ac = 172 - +0x0bc, // 0x0ad = 173 - JUMP_IF_BREAK_RECEIVED +0x0b7, // 0x0ae = 174 - +0x0be, // 0x0af = 175 - JUMP_IF_PHY_READY +0x0a5, // 0x0b0 = 176 - +0x01c, // 0x0b1 = 177 - SOFT_RESET +0x0ff, // 0x0b2 = 178 - JUMP +0x001, // 0x0b3 = 179 - +0x022, // 0x0b4 = 180 - SEND_CREDIT_BLOCK +0x0ff, // 0x0b5 = 181 - JUMP +0x0a5, // 0x0b6 = 182 - +0x007, // 0x0b7 = 183 - CLOSE_BREAK +0x000, // 0x0b8 = 184 - NO_OP +0x000, // 0x0b9 = 185 - NO_OP +0x000, // 0x0ba = 186 - NO_OP +0x000, // 0x0bb = 187 - NO_OP +0x0c0, // 0x0bc = 188 - JUMP_IF_CLOSE_STATUS_EQUAL_ANY +0x063, // 0x0bd = 189 - +0x0be, // 0x0be = 190 - JUMP_IF_PHY_READY +0x0b8, // 0x0bf = 191 - +0x01c, // 0x0c0 = 192 - SOFT_RESET +0x0ff, // 0x0c1 = 193 - JUMP +0x001, // 0x0c2 = 194 - +0x005, // 0x0c3 = 195 - CLOSE_ACK_NAK_TIMEOUT +0x0ff, // 0x0c4 = 196 - JUMP +0x0a5, // 0x0c5 = 197 - +0x006, // 0x0c6 = 198 - CLOSE_CREDIT_TIMEOUT +0x0ff, // 0x0c7 = 199 - JUMP +0x0a5, // 0x0c8 = 200 - +0x0cc, // 0x0c9 = 201 - JUMP_IF_RX_BUFFER_FULL +0x063, // 0x0ca = 202 - +0x0b7, // 0x0cb = 203 - JUMP_IF_FLAG_7_SET +0x0d0, // 0x0cc = 204 - +0x011, // 0x0cd = 205 - START_IT_NEXUS_LOSS_TIMER +0x00f, // 0x0ce = 206 - PATHWAY_BLOCKED_CNT_RESET +0x00e, // 0x0cf = 207 - START_ARB_WAIT_TIMER +0x0cb, // 0x0d0 = 208 - JUMP_IF_FREEZE_ACTIVE +0x10f, // 0x0d1 = 209 - +0x001, // 0x0d2 = 210 - OPEN_REQUEST +0x080, // 0x0d3 = 211 - SET_FLAG +0x080, // 0x0d4 = 212 - +0x090, // 0x0d5 = 213 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_ACCEPT +0x0fb, // 0x0d6 = 214 - +0x095, // 0x0d7 = 215 - JUMP_IF_OPEN_STATUS_EQUAL_RATE_NOT_SUPPORTED +0x100, // 0x0d8 = 216 - +0x099, // 0x0d9 = 217 - JUMP_IF_OPEN_STATUS_EQUAL_PROTOCOL_NOT_SUPPORTED +0x103, // 0x0da = 218 - +0x09b, // 0x0db = 219 - JUMP_IF_OPEN_STATUS_EQUAL_WRONG_DESTINATION +0x106, // 0x0dc = 220 - +0x094, // 0x0dd = 221 - JUMP_IF_OPEN_STATUS_EQUAL_BREAK_RECEIVED +0x0d0, // 0x0de = 222 - +0x093, // 0x0df = 223 - JUMP_IF_OPEN_STATUS_EQUAL_BAD_DESTINATION +0x109, // 0x0e0 = 224 - +0x09f, // 0x0e1 = 225 - JUMP_IF_IT_NEXUS_LOSS_TIMEOUT +0x10c, // 0x0e2 = 226 - +0x09a, // 0x0e3 = 227 - JUMP_IF_OPEN_STATUS_EQUAL_STP_RESOURCE_BUSY +0x0d0, // 0x0e4 = 228 - +0x096, // 0x0e5 = 229 - JUMP_IF_OPEN_STATUS_EQUAL_NO_DESTINATION +0x109, // 0x0e6 = 230 - +0x097, // 0x0e7 = 231 - JUMP_IF_OPEN_STATUS_EQUAL_PATHWAY_BLOCKED +0x114, // 0x0e8 = 232 - +0x098, // 0x0e9 = 233 - JUMP_IF_OPEN_STATUS_EQUAL_RETRY +0x0d0, // 0x0ea = 234 - +0x092, // 0x0eb = 235 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_TIMEOUT +0x0d0, // 0x0ec = 236 - +0x0a4, // 0x0ed = 237 - JUMP_IF_CONNECTION_ACTIVE_SET +0x0f5, // 0x0ee = 238 - +0x0be, // 0x0ef = 239 - JUMP_IF_PHY_READY +0x0d5, // 0x0f0 = 240 - +0x01b, // 0x0f1 = 241 - SET_OPEN_STATUS_PHY_NOT_RDY +0x01c, // 0x0f2 = 242 - SOFT_RESET +0x0ff, // 0x0f3 = 243 - JUMP +0x001, // 0x0f4 = 244 - +0x0a0, // 0x0f5 = 245 - JUMP_IF_CONNECTION_PROFILE_OPEN_EQUAL +0x0fb, // 0x0f6 = 246 - +0x000, // 0x0f7 = 247 - NO_OP +0x000, // 0x0f8 = 248 - NO_OP +0x0ff, // 0x0f9 = 249 - JUMP +0x063, // 0x0fa = 250 - +0x013, // 0x0fb = 251 - SET_OPEN_STATUS_NORMAL +0x081, // 0x0fc = 252 - CLEAR_FLAG +0x080, // 0x0fd = 253 - +0x0ff, // 0x0fe = 254 - JUMP +0x02b, // 0x0ff = 255 - +0x017, // 0x100 = 256 - SET_OPEN_STATUS_BAD_RATE +0x0ff, // 0x101 = 257 - JUMP +0x110, // 0x102 = 258 - +0x018, // 0x103 = 259 - SET_OPEN_STATUS_BAD_PROTOCOL +0x0ff, // 0x104 = 260 - JUMP +0x110, // 0x105 = 261 - +0x01a, // 0x106 = 262 - SET_OPEN_STATUS_WRONG_DEST +0x0ff, // 0x107 = 263 - JUMP +0x110, // 0x108 = 264 - +0x015, // 0x109 = 265 - SET_OPEN_STATUS_BAD_DEST +0x0ff, // 0x10a = 266 - JUMP +0x110, // 0x10b = 267 - +0x014, // 0x10c = 268 - SET_OPEN_STATUS_IT_NEXUS_LOSS +0x0ff, // 0x10d = 269 - JUMP +0x110, // 0x10e = 270 - +0x024, // 0x10f = 271 - SET_OPEN_STATUS_FREEZE +0x000, // 0x110 = 272 - NO_OP +0x000, // 0x111 = 273 - NO_OP +0x0ff, // 0x112 = 274 - JUMP +0x063, // 0x113 = 275 - +0x010, // 0x114 = 276 - PATHWAY_BLOCKED_CNT_INC +0x0ff, // 0x115 = 277 - JUMP +0x0d0, // 0x116 = 278 - +0x000, // 0x117 = 279 - NO_OP +0x000, // 0x118 = 280 - NO_OP +0x000, // 0x119 = 281 - NO_OP +0x000, // 0x11a = 282 - NO_OP +0x000, // 0x11b = 283 - NO_OP +0x000, // 0x11c = 284 - NO_OP +0x000, // 0x11d = 285 - NO_OP +0x000, // 0x11e = 286 - NO_OP +0x000, // 0x11f = 287 - NO_OP +0x000, // 0x120 = 288 - NO_OP +0x000, // 0x121 = 289 - NO_OP +0x000, // 0x122 = 290 - NO_OP +0x000, // 0x123 = 291 - NO_OP +0x000, // 0x124 = 292 - NO_OP +0x000, // 0x125 = 293 - NO_OP +0x000, // 0x126 = 294 - NO_OP +0x000, // 0x127 = 295 - NO_OP +0x000, // 0x128 = 296 - NO_OP +0x000, // 0x129 = 297 - NO_OP +0x000, // 0x12a = 298 - NO_OP +0x000, // 0x12b = 299 - NO_OP +0x000, // 0x12c = 300 - NO_OP +0x000, // 0x12d = 301 - NO_OP +0x000, // 0x12e = 302 - NO_OP +0x000, // 0x12f = 303 - NO_OP +0x000, // 0x130 = 304 - NO_OP +0x000, // 0x131 = 305 - NO_OP +0x000, // 0x132 = 306 - NO_OP +0x000, // 0x133 = 307 - NO_OP +0x000, // 0x134 = 308 - NO_OP +0x000, // 0x135 = 309 - NO_OP +0x000, // 0x136 = 310 - NO_OP +0x000, // 0x137 = 311 - NO_OP +0x000, // 0x138 = 312 - NO_OP +0x000, // 0x139 = 313 - NO_OP +0x000, // 0x13a = 314 - NO_OP +0x000, // 0x13b = 315 - NO_OP +0x000, // 0x13c = 316 - NO_OP +0x000, // 0x13d = 317 - NO_OP +0x000, // 0x13e = 318 - NO_OP +0x000, // 0x13f = 319 - NO_OP +0x000, // 0x140 = 320 - NO_OP +0x000, // 0x141 = 321 - NO_OP +0x000, // 0x142 = 322 - NO_OP +0x000, // 0x143 = 323 - NO_OP +0x000, // 0x144 = 324 - NO_OP +0x000, // 0x145 = 325 - NO_OP +0x000, // 0x146 = 326 - NO_OP +0x000, // 0x147 = 327 - NO_OP +0x000, // 0x148 = 328 - NO_OP +0x000, // 0x149 = 329 - NO_OP +0x000, // 0x14a = 330 - NO_OP +0x000, // 0x14b = 331 - NO_OP +0x000, // 0x14c = 332 - NO_OP +0x000, // 0x14d = 333 - NO_OP +0x000, // 0x14e = 334 - NO_OP +0x000, // 0x14f = 335 - NO_OP +0x000, // 0x150 = 336 - NO_OP +0x000, // 0x151 = 337 - NO_OP +0x000, // 0x152 = 338 - NO_OP +0x000, // 0x153 = 339 - NO_OP +0x000, // 0x154 = 340 - NO_OP +0x000, // 0x155 = 341 - NO_OP +0x000, // 0x156 = 342 - NO_OP +0x000, // 0x157 = 343 - NO_OP +0x000, // 0x158 = 344 - NO_OP +0x000, // 0x159 = 345 - NO_OP +0x000, // 0x15a = 346 - NO_OP +0x000, // 0x15b = 347 - NO_OP +0x000, // 0x15c = 348 - NO_OP +0x000, // 0x15d = 349 - NO_OP +0x000, // 0x15e = 350 - NO_OP +0x000, // 0x15f = 351 - NO_OP +0x000, // 0x160 = 352 - NO_OP +0x000, // 0x161 = 353 - NO_OP +0x000, // 0x162 = 354 - NO_OP +0x000, // 0x163 = 355 - NO_OP +0x000, // 0x164 = 356 - NO_OP +0x000, // 0x165 = 357 - NO_OP +0x000, // 0x166 = 358 - NO_OP +0x000, // 0x167 = 359 - NO_OP +0x000, // 0x168 = 360 - NO_OP +0x000, // 0x169 = 361 - NO_OP +0x000, // 0x16a = 362 - NO_OP +0x000, // 0x16b = 363 - NO_OP +0x000, // 0x16c = 364 - NO_OP +0x000, // 0x16d = 365 - NO_OP +0x000, // 0x16e = 366 - NO_OP +0x000, // 0x16f = 367 - NO_OP +0x000, // 0x170 = 368 - NO_OP +0x000, // 0x171 = 369 - NO_OP +0x000, // 0x172 = 370 - NO_OP +0x000, // 0x173 = 371 - NO_OP +0x000, // 0x174 = 372 - NO_OP +0x000, // 0x175 = 373 - NO_OP +0x000, // 0x176 = 374 - NO_OP +0x000, // 0x177 = 375 - NO_OP +0x000, // 0x178 = 376 - NO_OP +0x000, // 0x179 = 377 - NO_OP +0x000, // 0x17a = 378 - NO_OP +0x000, // 0x17b = 379 - NO_OP +0x000, // 0x17c = 380 - NO_OP +0x000, // 0x17d = 381 - NO_OP +0x000, // 0x17e = 382 - NO_OP +0x000, // 0x17f = 383 - NO_OP +0x000, // 0x180 = 384 - NO_OP +0x000, // 0x181 = 385 - NO_OP +0x000, // 0x182 = 386 - NO_OP +0x000, // 0x183 = 387 - NO_OP +0x000, // 0x184 = 388 - NO_OP +0x000, // 0x185 = 389 - NO_OP +0x000, // 0x186 = 390 - NO_OP +0x000, // 0x187 = 391 - NO_OP +0x000, // 0x188 = 392 - NO_OP +0x000, // 0x189 = 393 - NO_OP +0x000, // 0x18a = 394 - NO_OP +0x000, // 0x18b = 395 - NO_OP +0x000, // 0x18c = 396 - NO_OP +0x000, // 0x18d = 397 - NO_OP +0x000, // 0x18e = 398 - NO_OP +0x000, // 0x18f = 399 - NO_OP +0x000, // 0x190 = 400 - NO_OP +0x000, // 0x191 = 401 - NO_OP +0x000, // 0x192 = 402 - NO_OP +0x000, // 0x193 = 403 - NO_OP +0x000, // 0x194 = 404 - NO_OP +0x000, // 0x195 = 405 - NO_OP +0x000, // 0x196 = 406 - NO_OP +0x000, // 0x197 = 407 - NO_OP +0x000, // 0x198 = 408 - NO_OP +0x000, // 0x199 = 409 - NO_OP +0x000, // 0x19a = 410 - NO_OP +0x000, // 0x19b = 411 - NO_OP +0x000, // 0x19c = 412 - NO_OP +0x000, // 0x19d = 413 - NO_OP +0x000, // 0x19e = 414 - NO_OP +0x000, // 0x19f = 415 - NO_OP +0x000, // 0x1a0 = 416 - NO_OP +0x000, // 0x1a1 = 417 - NO_OP +0x000, // 0x1a2 = 418 - NO_OP +0x000, // 0x1a3 = 419 - NO_OP +0x000, // 0x1a4 = 420 - NO_OP +0x000, // 0x1a5 = 421 - NO_OP +0x000, // 0x1a6 = 422 - NO_OP +0x000, // 0x1a7 = 423 - NO_OP +0x000, // 0x1a8 = 424 - NO_OP +0x000, // 0x1a9 = 425 - NO_OP +0x000, // 0x1aa = 426 - NO_OP +0x000, // 0x1ab = 427 - NO_OP +0x000, // 0x1ac = 428 - NO_OP +0x000, // 0x1ad = 429 - NO_OP +0x000, // 0x1ae = 430 - NO_OP +0x000, // 0x1af = 431 - NO_OP +0x000, // 0x1b0 = 432 - NO_OP +0x000, // 0x1b1 = 433 - NO_OP +0x000, // 0x1b2 = 434 - NO_OP +0x000, // 0x1b3 = 435 - NO_OP +0x000, // 0x1b4 = 436 - NO_OP +0x000, // 0x1b5 = 437 - NO_OP +0x000, // 0x1b6 = 438 - NO_OP +0x000, // 0x1b7 = 439 - NO_OP +0x000, // 0x1b8 = 440 - NO_OP +0x000, // 0x1b9 = 441 - NO_OP +0x000, // 0x1ba = 442 - NO_OP +0x000, // 0x1bb = 443 - NO_OP +0x000, // 0x1bc = 444 - NO_OP +0x000, // 0x1bd = 445 - NO_OP +0x000, // 0x1be = 446 - NO_OP +0x000, // 0x1bf = 447 - NO_OP +0x000, // 0x1c0 = 448 - NO_OP +0x000, // 0x1c1 = 449 - NO_OP +0x000, // 0x1c2 = 450 - NO_OP +0x000, // 0x1c3 = 451 - NO_OP +0x000, // 0x1c4 = 452 - NO_OP +0x000, // 0x1c5 = 453 - NO_OP +0x000, // 0x1c6 = 454 - NO_OP +0x000, // 0x1c7 = 455 - NO_OP +0x000, // 0x1c8 = 456 - NO_OP +0x000, // 0x1c9 = 457 - NO_OP +0x000, // 0x1ca = 458 - NO_OP +0x000, // 0x1cb = 459 - NO_OP +0x000, // 0x1cc = 460 - NO_OP +0x000, // 0x1cd = 461 - NO_OP +0x000, // 0x1ce = 462 - NO_OP +0x000, // 0x1cf = 463 - NO_OP +0x000, // 0x1d0 = 464 - NO_OP +0x000, // 0x1d1 = 465 - NO_OP +0x000, // 0x1d2 = 466 - NO_OP +0x000, // 0x1d3 = 467 - NO_OP +0x000, // 0x1d4 = 468 - NO_OP +0x000, // 0x1d5 = 469 - NO_OP +0x000, // 0x1d6 = 470 - NO_OP +0x000, // 0x1d7 = 471 - NO_OP +0x000, // 0x1d8 = 472 - NO_OP +0x000, // 0x1d9 = 473 - NO_OP +0x000, // 0x1da = 474 - NO_OP +0x000, // 0x1db = 475 - NO_OP +0x000, // 0x1dc = 476 - NO_OP +0x000, // 0x1dd = 477 - NO_OP +0x000, // 0x1de = 478 - NO_OP +0x000, // 0x1df = 479 - NO_OP +0x000, // 0x1e0 = 480 - NO_OP +0x000, // 0x1e1 = 481 - NO_OP +0x000, // 0x1e2 = 482 - NO_OP +0x000, // 0x1e3 = 483 - NO_OP +0x000, // 0x1e4 = 484 - NO_OP +0x000, // 0x1e5 = 485 - NO_OP +0x000, // 0x1e6 = 486 - NO_OP +0x000, // 0x1e7 = 487 - NO_OP +0x000, // 0x1e8 = 488 - NO_OP +0x000, // 0x1e9 = 489 - NO_OP +0x000, // 0x1ea = 490 - NO_OP +0x000, // 0x1eb = 491 - NO_OP +0x000, // 0x1ec = 492 - NO_OP +0x000, // 0x1ed = 493 - NO_OP +0x000, // 0x1ee = 494 - NO_OP +0x000, // 0x1ef = 495 - NO_OP +0x000, // 0x1f0 = 496 - NO_OP +0x000, // 0x1f1 = 497 - NO_OP +0x000, // 0x1f2 = 498 - NO_OP +0x000, // 0x1f3 = 499 - NO_OP +0x000, // 0x1f4 = 500 - NO_OP +0x000, // 0x1f5 = 501 - NO_OP +0x000, // 0x1f6 = 502 - NO_OP +0x000, // 0x1f7 = 503 - NO_OP +0x000, // 0x1f8 = 504 - NO_OP +0x000, // 0x1f9 = 505 - NO_OP +0x000, // 0x1fa = 506 - NO_OP +0x000, // 0x1fb = 507 - NO_OP +0x000, // 0x1fc = 508 - NO_OP +0x000, // 0x1fd = 509 - NO_OP +0x000, // 0x1fe = 510 - NO_OP +0x000 // 0x1ff = 511 - NO_OP +}; + + + +/* WCS 20060825 */ +bit32 wcsImage_20060825[] = +{ +0x00d, // 00000 = 0 - PHY_RESET_START +0x00d, // 0x001 = 1 - PHY_RESET_START +0x0be, // 0x002 = 2 - JUMP_IF_PHY_READY +0x00c, // 0x003 = 3 - +0x0ae, // 0x004 = 4 - JUMP_IF_HARD_RESET_PRIMITIVE +0x015, // 0x005 = 5 - +0x0af, // 0x006 = 6 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x026, // 0x007 = 7 - +0x0ce, // 0x008 = 8 - JUMP_IF_IDENTIFY_FRAME_TIMEOUT +0x000, // 0x009 = 9 - +0x0ff, // 0x00a = 10 - JUMP +0x002, // 0x00b = 11 - +0x00c, // 0x00c = 12 - SEND_ID_FRAME +0x0ae, // 0x00d = 13 - JUMP_IF_HARD_RESET_PRIMITIVE +0x015, // 0x00e = 14 - +0x0af, // 0x00f = 15 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x02b, // 0x010 = 16 - +0x0ce, // 0x011 = 17 - JUMP_IF_IDENTIFY_FRAME_TIMEOUT +0x000, // 0x012 = 18 - +0x0ff, // 0x013 = 19 - JUMP +0x00d, // 0x014 = 20 - +0x01c, // 0x015 = 21 - SOFT_RESET +0x00d, // 0x016 = 22 - PHY_RESET_START +0x00d, // 0x017 = 23 - PHY_RESET_START +0x0be, // 0x018 = 24 - JUMP_IF_PHY_READY +0x01c, // 0x019 = 25 - +0x0af, // 0x01a = 26 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x023, // 0x01b = 27 - +0x00c, // 0x01c = 28 - SEND_ID_FRAME +0x0af, // 0x01d = 29 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x02b, // 0x01e = 30 - +0x0ce, // 0x01f = 31 - JUMP_IF_IDENTIFY_FRAME_TIMEOUT +0x000, // 0x020 = 32 - +0x0ff, // 0x021 = 33 - JUMP +0x01d, // 0x022 = 34 - +0x00c, // 0x023 = 35 - SEND_ID_FRAME +0x0ff, // 0x024 = 36 - JUMP +0x02b, // 0x025 = 37 - +0x0be, // 0x026 = 38 - JUMP_IF_PHY_READY +0x02a, // 0x027 = 39 - +0x0ff, // 0x028 = 40 - JUMP +0x026, // 0x029 = 41 - +0x00c, // 0x02a = 42 - SEND_ID_FRAME +0x000, // 0x02b = 43 - NO_OP +0x000, // 0x02c = 44 - NO_OP +0x000, // 0x02d = 45 - NO_OP +0x000, // 0x02e = 46 - NO_OP +0x000, // 0x02f = 47 - NO_OP +0x000, // 0x030 = 48 - NO_OP +0x0ff, // 0x031 = 49 - JUMP +0x06d, // 0x032 = 50 - +0x000, // 0x033 = 51 - NO_OP +0x0c9, // 0x034 = 52 - JUMP_IF_RX_BUFFER_FULL_TIMEOUT +0x062, // 0x035 = 53 - +0x0a5, // 0x036 = 54 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_GOOD +0x04b, // 0x037 = 55 - +0x0a6, // 0x038 = 56 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_NAK +0x052, // 0x039 = 57 - +0x0a7, // 0x03a = 58 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_ACK_NAK_TIMEOUT +0x055, // 0x03b = 59 - +0x0a8, // 0x03c = 60 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_BREAK +0x05f, // 0x03d = 61 - +0x0aa, // 0x03e = 62 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_CREDIT_TIMEOUT +0x05a, // 0x03f = 63 - +0x0c5, // 0x040 = 64 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_SMP_ERR +0x05f, // 0x041 = 65 - +0x0ac, // 0x042 = 66 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_MAX_BURST_SIZE +0x052, // 0x043 = 67 - +0x0ca, // 0x044 = 68 - JUMP_IF_CLOSE_REQ +0x0fc, // 0x045 = 69 - +0x0be, // 0x046 = 70 - JUMP_IF_PHY_READY +0x034, // 0x047 = 71 - +0x01c, // 0x048 = 72 - SOFT_RESET +0x0ff, // 0x049 = 73 - JUMP +0x002, // 0x04a = 74 - +0x01d, // 0x04b = 75 - ADVANCE +0x0bc, // 0x04c = 76 - JUMP_IF_BREAK_RECEIVED +0x10f, // 0x04d = 77 - +0x0c3, // 0x04e = 78 - JUMP_IF_SMP_PROTOCOL +0x0fc, // 0x04f = 79 - +0x0ff, // 0x050 = 80 - JUMP +0x065, // 0x051 = 81 - +0x01d, // 0x052 = 82 - ADVANCE +0x0ff, // 0x053 = 83 - JUMP +0x065, // 0x054 = 84 - +0x01d, // 0x055 = 85 - ADVANCE +0x0bc, // 0x056 = 86 - JUMP_IF_BREAK_RECEIVED +0x10f, // 0x057 = 87 - +0x0ff, // 0x058 = 88 - JUMP +0x11b, // 0x059 = 89 - +0x01d, // 0x05a = 90 - ADVANCE +0x0bc, // 0x05b = 91 - JUMP_IF_BREAK_RECEIVED +0x10f, // 0x05c = 92 - +0x0ff, // 0x05d = 93 - JUMP +0x11e, // 0x05e = 94 - +0x01d, // 0x05f = 95 - ADVANCE +0x0ff, // 0x060 = 96 - JUMP +0x10f, // 0x061 = 97 - +0x022, // 0x062 = 98 - SEND_CREDIT_BLOCK +0x0ff, // 0x063 = 99 - JUMP +0x036, // 0x064 = 100 - +0x083, // 0x065 = 101 - TIMER_START +0x004, // 0x066 = 102 - +0x000, // 0x067 = 103 - NO_OP +0x000, // 0x068 = 104 - NO_OP +0x0b8, // 0x069 = 105 - JUMP_IF_TIMER_EXPIRED +0x06d, // 0x06a = 106 - +0x0ff, // 0x06b = 107 - JUMP +0x067, // 0x06c = 108 - +0x0bc, // 0x06d = 109 - JUMP_IF_BREAK_RECEIVED +0x10f, // 0x06e = 110 - +0x0be, // 0x06f = 111 - JUMP_IF_PHY_READY +0x074, // 0x070 = 112 - +0x01c, // 0x071 = 113 - SOFT_RESET +0x0ff, // 0x072 = 114 - JUMP +0x002, // 0x073 = 115 - +0x0c8, // 0x074 = 116 - JUMP_IF_HIP_REQ +0x086, // 0x075 = 117 - +0x0c6, // 0x076 = 118 - JUMP_IF_SFO_REQ +0x08f, // 0x077 = 119 - +0x0c7, // 0x078 = 120 - JUMP_IF_DOC_REQ +0x09a, // 0x079 = 121 - +0x0a3, // 0x07a = 122 - JUMP_IF_CONNECTION_OPEN_SLAVE_FLAG_SET +0x0db, // 0x07b = 123 - +0x0a2, // 0x07c = 124 - JUMP_IF_CONNECTION_OPEN_MASTER_FLAG_SET +0x0c4, // 0x07d = 125 - +0x0c8, // 0x07e = 126 - JUMP_IF_HIP_REQ +0x0a3, // 0x07f = 127 - +0x0c6, // 0x080 = 128 - JUMP_IF_SFO_REQ +0x0a8, // 0x081 = 129 - +0x0c7, // 0x082 = 130 - JUMP_IF_DOC_REQ +0x0ad, // 0x083 = 131 - +0x0ff, // 0x084 = 132 - JUMP +0x06d, // 0x085 = 133 - +0x028, // 0x086 = 134 - CHECK_HIP +0x000, // 0x087 = 135 - NO_OP +0x000, // 0x088 = 136 - NO_OP +0x000, // 0x089 = 137 - NO_OP +0x000, // 0x08a = 138 - NO_OP +0x0d8, // 0x08b = 139 - JUMP_IF_NXT_CONN_ACTIVE_PROF_EQ +0x0a3, // 0x08c = 140 - +0x0ff, // 0x08d = 141 - JUMP +0x07a, // 0x08e = 142 - +0x029, // 0x08f = 143 - CHECK_SFO +0x000, // 0x090 = 144 - NO_OP +0x000, // 0x091 = 145 - NO_OP +0x000, // 0x092 = 146 - NO_OP +0x000, // 0x093 = 147 - NO_OP +0x0d8, // 0x094 = 148 - JUMP_IF_NXT_CONN_ACTIVE_PROF_EQ +0x0a8, // 0x095 = 149 - +0x0c7, // 0x096 = 150 - JUMP_IF_DOC_REQ +0x09a, // 0x097 = 151 - +0x0ff, // 0x098 = 152 - JUMP +0x07a, // 0x099 = 153 - +0x02a, // 0x09a = 154 - CHECK_DOC +0x000, // 0x09b = 155 - NO_OP +0x000, // 0x09c = 156 - NO_OP +0x000, // 0x09d = 157 - NO_OP +0x000, // 0x09e = 158 - NO_OP +0x0d8, // 0x09f = 159 - JUMP_IF_NXT_CONN_ACTIVE_PROF_EQ +0x0ad, // 0x0a0 = 160 - +0x0ff, // 0x0a1 = 161 - JUMP +0x07a, // 0x0a2 = 162 - +0x020, // 0x0a3 = 163 - SELECT_HIP +0x000, // 0x0a4 = 164 - NO_OP +0x000, // 0x0a5 = 165 - NO_OP +0x0ff, // 0x0a6 = 166 - JUMP +0x0b0, // 0x0a7 = 167 - +0x01e, // 0x0a8 = 168 - SELECT_SFO +0x000, // 0x0a9 = 169 - NO_OP +0x000, // 0x0aa = 170 - NO_OP +0x0ff, // 0x0ab = 171 - JUMP +0x0b0, // 0x0ac = 172 - +0x01f, // 0x0ad = 173 - SELECT_DOC +0x000, // 0x0ae = 174 - NO_OP +0x000, // 0x0af = 175 - NO_OP +0x0a4, // 0x0b0 = 176 - JUMP_IF_CONNECTION_ACTIVE_SET +0x0b4, // 0x0b1 = 177 - +0x0ff, // 0x0b2 = 178 - JUMP +0x121, // 0x0b3 = 179 - +0x0a0, // 0x0b4 = 180 - JUMP_IF_CONNECTION_PROFILE_OPEN_EQUAL +0x0ba, // 0x0b5 = 181 - +0x0a3, // 0x0b6 = 182 - JUMP_IF_CONNECTION_OPEN_SLAVE_FLAG_SET +0x0db, // 0x0b7 = 183 - +0x0ff, // 0x0b8 = 184 - JUMP +0x0fc, // 0x0b9 = 185 - +0x0cb, // 0x0ba = 186 - JUMP_IF_FREEZE_ACTIVE +0x0bf, // 0x0bb = 187 - +0x013, // 0x0bc = 188 - SET_OPEN_STATUS_NORMAL +0x0ff, // 0x0bd = 189 - JUMP +0x033, // 0x0be = 190 - +0x024, // 0x0bf = 191 - SET_OPEN_STATUS_FREEZE +0x000, // 0x0c0 = 192 - NO_OP +0x000, // 0x0c1 = 193 - NO_OP +0x0ff, // 0x0c2 = 194 - JUMP +0x06d, // 0x0c3 = 195 - +0x0d2, // 0x0c4 = 196 - JUMP_IF_STP_CONNECTION_ACTIVE +0x0c8, // 0x0c5 = 197 - +0x0ff, // 0x0c6 = 198 - JUMP +0x0fc, // 0x0c7 = 199 - +0x0d5, // 0x0c8 = 200 - JUMP_IF_CLOSE_RECEIVED +0x0fc, // 0x0c9 = 201 - +0x0d6, // 0x0ca = 202 - JUMP_IF_SYNC_RECEIVED +0x0ce, // 0x0cb = 203 - +0x0ff, // 0x0cc = 204 - JUMP +0x06d, // 0x0cd = 205 - +0x027, // 0x0ce = 206 - SEND_STP_CLOSE_REQ +0x000, // 0x0cf = 207 - NO_OP +0x000, // 0x0d0 = 208 - NO_OP +0x000, // 0x0d1 = 209 - NO_OP +0x000, // 0x0d2 = 210 - NO_OP +0x0d5, // 0x0d3 = 211 - JUMP_IF_CLOSE_RECEIVED +0x0fc, // 0x0d4 = 212 - +0x0bc, // 0x0d5 = 213 - JUMP_IF_BREAK_RECEIVED +0x10f, // 0x0d6 = 214 - +0x0d7, // 0x0d7 = 215 - JUMP_IF_STP_CLOSE_ACK +0x0fc, // 0x0d8 = 216 - +0x0ff, // 0x0d9 = 217 - JUMP +0x0cf, // 0x0da = 218 - +0x0c3, // 0x0db = 219 - JUMP_IF_SMP_PROTOCOL +0x0e3, // 0x0dc = 220 - +0x0d2, // 0x0dd = 221 - JUMP_IF_STP_CONNECTION_ACTIVE +0x0e7, // 0x0de = 222 - +0x0d1, // 0x0df = 223 - JUMP_IF_IDLE_TIMER_TIMEOUT +0x0ed, // 0x0e0 = 224 - +0x0ff, // 0x0e1 = 225 - JUMP +0x06d, // 0x0e2 = 226 - +0x0c4, // 0x0e3 = 227 - JUMP_IF_SMP_FRAME_ERR_RECEIVED +0x10f, // 0x0e4 = 228 - +0x0ff, // 0x0e5 = 229 - JUMP +0x07e, // 0x0e6 = 230 - +0x0d5, // 0x0e7 = 231 - JUMP_IF_CLOSE_RECEIVED +0x0ed, // 0x0e8 = 232 - +0x0d6, // 0x0e9 = 233 - JUMP_IF_SYNC_RECEIVED +0x0ef, // 0x0ea = 234 - +0x0ff, // 0x0eb = 235 - JUMP +0x0e7, // 0x0ec = 236 - +0x0ff, // 0x0ed = 237 - JUMP +0x0fc, // 0x0ee = 238 - +0x027, // 0x0ef = 239 - SEND_STP_CLOSE_REQ +0x000, // 0x0f0 = 240 - NO_OP +0x000, // 0x0f1 = 241 - NO_OP +0x000, // 0x0f2 = 242 - NO_OP +0x000, // 0x0f3 = 243 - NO_OP +0x0d5, // 0x0f4 = 244 - JUMP_IF_CLOSE_RECEIVED +0x0fc, // 0x0f5 = 245 - +0x0bc, // 0x0f6 = 246 - JUMP_IF_BREAK_RECEIVED +0x10f, // 0x0f7 = 247 - +0x0d7, // 0x0f8 = 248 - JUMP_IF_STP_CLOSE_ACK +0x0fc, // 0x0f9 = 249 - +0x0ff, // 0x0fa = 250 - JUMP +0x0f0, // 0x0fb = 251 - +0x004, // 0x0fc = 252 - CLOSE_NORMAL +0x000, // 0x0fd = 253 - NO_OP +0x000, // 0x0fe = 254 - NO_OP +0x000, // 0x0ff = 255 - NO_OP +0x000, // 0x100 = 256 - NO_OP +0x0c9, // 0x101 = 257 - JUMP_IF_RX_BUFFER_FULL_TIMEOUT +0x10c, // 0x102 = 258 - +0x0c0, // 0x103 = 259 - JUMP_IF_CLOSE_STATUS_EQUAL_ANY +0x06d, // 0x104 = 260 - +0x0bc, // 0x105 = 261 - JUMP_IF_BREAK_RECEIVED +0x10f, // 0x106 = 262 - +0x0be, // 0x107 = 263 - JUMP_IF_PHY_READY +0x0fd, // 0x108 = 264 - +0x01c, // 0x109 = 265 - SOFT_RESET +0x0ff, // 0x10a = 266 - JUMP +0x002, // 0x10b = 267 - +0x022, // 0x10c = 268 - SEND_CREDIT_BLOCK +0x0ff, // 0x10d = 269 - JUMP +0x0fd, // 0x10e = 270 - +0x007, // 0x10f = 271 - CLOSE_BREAK +0x000, // 0x110 = 272 - NO_OP +0x000, // 0x111 = 273 - NO_OP +0x000, // 0x112 = 274 - NO_OP +0x000, // 0x113 = 275 - NO_OP +0x0c0, // 0x114 = 276 - JUMP_IF_CLOSE_STATUS_EQUAL_ANY +0x06d, // 0x115 = 277 - +0x0be, // 0x116 = 278 - JUMP_IF_PHY_READY +0x110, // 0x117 = 279 - +0x01c, // 0x118 = 280 - SOFT_RESET +0x0ff, // 0x119 = 281 - JUMP +0x002, // 0x11a = 282 - +0x005, // 0x11b = 283 - CLOSE_ACK_NAK_TIMEOUT +0x0ff, // 0x11c = 284 - JUMP +0x0fd, // 0x11d = 285 - +0x006, // 0x11e = 286 - CLOSE_CREDIT_TIMEOUT +0x0ff, // 0x11f = 287 - JUMP +0x0fd, // 0x120 = 288 - +0x0cc, // 0x121 = 289 - JUMP_IF_RX_BUFFER_FULL +0x06d, // 0x122 = 290 - +0x0b7, // 0x123 = 291 - JUMP_IF_FLAG_7_SET +0x128, // 0x124 = 292 - +0x011, // 0x125 = 293 - START_IT_NEXUS_LOSS_TIMER +0x00f, // 0x126 = 294 - PATHWAY_BLOCKED_CNT_RESET +0x00e, // 0x127 = 295 - START_ARB_WAIT_TIMER +0x0cb, // 0x128 = 296 - JUMP_IF_FREEZE_ACTIVE +0x169, // 0x129 = 297 - +0x001, // 0x12a = 298 - OPEN_REQUEST +0x080, // 0x12b = 299 - SET_FLAG +0x080, // 0x12c = 300 - +0x090, // 0x12d = 301 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_ACCEPT +0x153, // 0x12e = 302 - +0x095, // 0x12f = 303 - JUMP_IF_OPEN_STATUS_EQUAL_RATE_NOT_SUPPORTED +0x158, // 0x130 = 304 - +0x099, // 0x131 = 305 - JUMP_IF_OPEN_STATUS_EQUAL_PROTOCOL_NOT_SUPPORTED +0x15b, // 0x132 = 306 - +0x09b, // 0x133 = 307 - JUMP_IF_OPEN_STATUS_EQUAL_WRONG_DESTINATION +0x15e, // 0x134 = 308 - +0x094, // 0x135 = 309 - JUMP_IF_OPEN_STATUS_EQUAL_BREAK_RECEIVED +0x128, // 0x136 = 310 - +0x093, // 0x137 = 311 - JUMP_IF_OPEN_STATUS_EQUAL_BAD_DESTINATION +0x161, // 0x138 = 312 - +0x09f, // 0x139 = 313 - JUMP_IF_IT_NEXUS_LOSS_TIMEOUT +0x164, // 0x13a = 314 - +0x09a, // 0x13b = 315 - JUMP_IF_OPEN_STATUS_EQUAL_STP_RESOURCE_BUSY +0x128, // 0x13c = 316 - +0x096, // 0x13d = 317 - JUMP_IF_OPEN_STATUS_EQUAL_NO_DESTINATION +0x128, // 0x13e = 318 - +0x097, // 0x13f = 319 - JUMP_IF_OPEN_STATUS_EQUAL_PATHWAY_BLOCKED +0x16e, // 0x140 = 320 - +0x098, // 0x141 = 321 - JUMP_IF_OPEN_STATUS_EQUAL_RETRY +0x128, // 0x142 = 322 - +0x092, // 0x143 = 323 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_TIMEOUT +0x128, // 0x144 = 324 - +0x0a4, // 0x145 = 325 - JUMP_IF_CONNECTION_ACTIVE_SET +0x14d, // 0x146 = 326 - +0x0be, // 0x147 = 327 - JUMP_IF_PHY_READY +0x12d, // 0x148 = 328 - +0x01b, // 0x149 = 329 - SET_OPEN_STATUS_PHY_NOT_RDY +0x01c, // 0x14a = 330 - SOFT_RESET +0x0ff, // 0x14b = 331 - JUMP +0x002, // 0x14c = 332 - +0x0a0, // 0x14d = 333 - JUMP_IF_CONNECTION_PROFILE_OPEN_EQUAL +0x153, // 0x14e = 334 - +0x000, // 0x14f = 335 - NO_OP +0x000, // 0x150 = 336 - NO_OP +0x0ff, // 0x151 = 337 - JUMP +0x06d, // 0x152 = 338 - +0x013, // 0x153 = 339 - SET_OPEN_STATUS_NORMAL +0x081, // 0x154 = 340 - CLEAR_FLAG +0x080, // 0x155 = 341 - +0x0ff, // 0x156 = 342 - JUMP +0x033, // 0x157 = 343 - +0x017, // 0x158 = 344 - SET_OPEN_STATUS_BAD_RATE +0x0ff, // 0x159 = 345 - JUMP +0x16a, // 0x15a = 346 - +0x018, // 0x15b = 347 - SET_OPEN_STATUS_BAD_PROTOCOL +0x0ff, // 0x15c = 348 - JUMP +0x16a, // 0x15d = 349 - +0x01a, // 0x15e = 350 - SET_OPEN_STATUS_WRONG_DEST +0x0ff, // 0x15f = 351 - JUMP +0x16a, // 0x160 = 352 - +0x015, // 0x161 = 353 - SET_OPEN_STATUS_BAD_DEST +0x0ff, // 0x162 = 354 - JUMP +0x16a, // 0x163 = 355 - +0x014, // 0x164 = 356 - SET_OPEN_STATUS_IT_NEXUS_LOSS +0x081, // 0x165 = 357 - CLEAR_FLAG +0x080, // 0x166 = 358 - +0x0ff, // 0x167 = 359 - JUMP +0x16a, // 0x168 = 360 - +0x024, // 0x169 = 361 - SET_OPEN_STATUS_FREEZE +0x000, // 0x16a = 362 - NO_OP +0x000, // 0x16b = 363 - NO_OP +0x0ff, // 0x16c = 364 - JUMP +0x06d, // 0x16d = 365 - +0x010, // 0x16e = 366 - PATHWAY_BLOCKED_CNT_INC +0x0ff, // 0x16f = 367 - JUMP +0x128, // 0x170 = 368 - +0x000, // 0x171 = 369 - NO_OP +0x000, // 0x172 = 370 - NO_OP +0x000, // 0x173 = 371 - NO_OP +0x000, // 0x174 = 372 - NO_OP +0x000, // 0x175 = 373 - NO_OP +0x000, // 0x176 = 374 - NO_OP +0x000, // 0x177 = 375 - NO_OP +0x000, // 0x178 = 376 - NO_OP +0x000, // 0x179 = 377 - NO_OP +0x000, // 0x17a = 378 - NO_OP +0x000, // 0x17b = 379 - NO_OP +0x000, // 0x17c = 380 - NO_OP +0x000, // 0x17d = 381 - NO_OP +0x000, // 0x17e = 382 - NO_OP +0x000, // 0x17f = 383 - NO_OP +0x000, // 0x180 = 384 - NO_OP +0x000, // 0x181 = 385 - NO_OP +0x000, // 0x182 = 386 - NO_OP +0x000, // 0x183 = 387 - NO_OP +0x000, // 0x184 = 388 - NO_OP +0x000, // 0x185 = 389 - NO_OP +0x000, // 0x186 = 390 - NO_OP +0x000, // 0x187 = 391 - NO_OP +0x000, // 0x188 = 392 - NO_OP +0x000, // 0x189 = 393 - NO_OP +0x000, // 0x18a = 394 - NO_OP +0x000, // 0x18b = 395 - NO_OP +0x000, // 0x18c = 396 - NO_OP +0x000, // 0x18d = 397 - NO_OP +0x000, // 0x18e = 398 - NO_OP +0x000, // 0x18f = 399 - NO_OP +0x000, // 0x190 = 400 - NO_OP +0x000, // 0x191 = 401 - NO_OP +0x000, // 0x192 = 402 - NO_OP +0x000, // 0x193 = 403 - NO_OP +0x000, // 0x194 = 404 - NO_OP +0x000, // 0x195 = 405 - NO_OP +0x000, // 0x196 = 406 - NO_OP +0x000, // 0x197 = 407 - NO_OP +0x000, // 0x198 = 408 - NO_OP +0x000, // 0x199 = 409 - NO_OP +0x000, // 0x19a = 410 - NO_OP +0x000, // 0x19b = 411 - NO_OP +0x000, // 0x19c = 412 - NO_OP +0x000, // 0x19d = 413 - NO_OP +0x000, // 0x19e = 414 - NO_OP +0x000, // 0x19f = 415 - NO_OP +0x000, // 0x1a0 = 416 - NO_OP +0x000, // 0x1a1 = 417 - NO_OP +0x000, // 0x1a2 = 418 - NO_OP +0x000, // 0x1a3 = 419 - NO_OP +0x000, // 0x1a4 = 420 - NO_OP +0x000, // 0x1a5 = 421 - NO_OP +0x000, // 0x1a6 = 422 - NO_OP +0x000, // 0x1a7 = 423 - NO_OP +0x000, // 0x1a8 = 424 - NO_OP +0x000, // 0x1a9 = 425 - NO_OP +0x000, // 0x1aa = 426 - NO_OP +0x000, // 0x1ab = 427 - NO_OP +0x000, // 0x1ac = 428 - NO_OP +0x000, // 0x1ad = 429 - NO_OP +0x000, // 0x1ae = 430 - NO_OP +0x000, // 0x1af = 431 - NO_OP +0x000, // 0x1b0 = 432 - NO_OP +0x000, // 0x1b1 = 433 - NO_OP +0x000, // 0x1b2 = 434 - NO_OP +0x000, // 0x1b3 = 435 - NO_OP +0x000, // 0x1b4 = 436 - NO_OP +0x000, // 0x1b5 = 437 - NO_OP +0x000, // 0x1b6 = 438 - NO_OP +0x000, // 0x1b7 = 439 - NO_OP +0x000, // 0x1b8 = 440 - NO_OP +0x000, // 0x1b9 = 441 - NO_OP +0x000, // 0x1ba = 442 - NO_OP +0x000, // 0x1bb = 443 - NO_OP +0x000, // 0x1bc = 444 - NO_OP +0x000, // 0x1bd = 445 - NO_OP +0x000, // 0x1be = 446 - NO_OP +0x000, // 0x1bf = 447 - NO_OP +0x000, // 0x1c0 = 448 - NO_OP +0x000, // 0x1c1 = 449 - NO_OP +0x000, // 0x1c2 = 450 - NO_OP +0x000, // 0x1c3 = 451 - NO_OP +0x000, // 0x1c4 = 452 - NO_OP +0x000, // 0x1c5 = 453 - NO_OP +0x000, // 0x1c6 = 454 - NO_OP +0x000, // 0x1c7 = 455 - NO_OP +0x000, // 0x1c8 = 456 - NO_OP +0x000, // 0x1c9 = 457 - NO_OP +0x000, // 0x1ca = 458 - NO_OP +0x000, // 0x1cb = 459 - NO_OP +0x000, // 0x1cc = 460 - NO_OP +0x000, // 0x1cd = 461 - NO_OP +0x000, // 0x1ce = 462 - NO_OP +0x000, // 0x1cf = 463 - NO_OP +0x000, // 0x1d0 = 464 - NO_OP +0x000, // 0x1d1 = 465 - NO_OP +0x000, // 0x1d2 = 466 - NO_OP +0x000, // 0x1d3 = 467 - NO_OP +0x000, // 0x1d4 = 468 - NO_OP +0x000, // 0x1d5 = 469 - NO_OP +0x000, // 0x1d6 = 470 - NO_OP +0x000, // 0x1d7 = 471 - NO_OP +0x000, // 0x1d8 = 472 - NO_OP +0x000, // 0x1d9 = 473 - NO_OP +0x000, // 0x1da = 474 - NO_OP +0x000, // 0x1db = 475 - NO_OP +0x000, // 0x1dc = 476 - NO_OP +0x000, // 0x1dd = 477 - NO_OP +0x000, // 0x1de = 478 - NO_OP +0x000, // 0x1df = 479 - NO_OP +0x000, // 0x1e0 = 480 - NO_OP +0x000, // 0x1e1 = 481 - NO_OP +0x000, // 0x1e2 = 482 - NO_OP +0x000, // 0x1e3 = 483 - NO_OP +0x000, // 0x1e4 = 484 - NO_OP +0x000, // 0x1e5 = 485 - NO_OP +0x000, // 0x1e6 = 486 - NO_OP +0x000, // 0x1e7 = 487 - NO_OP +0x000, // 0x1e8 = 488 - NO_OP +0x000, // 0x1e9 = 489 - NO_OP +0x000, // 0x1ea = 490 - NO_OP +0x000, // 0x1eb = 491 - NO_OP +0x000, // 0x1ec = 492 - NO_OP +0x000, // 0x1ed = 493 - NO_OP +0x000, // 0x1ee = 494 - NO_OP +0x000, // 0x1ef = 495 - NO_OP +0x000, // 0x1f0 = 496 - NO_OP +0x000, // 0x1f1 = 497 - NO_OP +0x000, // 0x1f2 = 498 - NO_OP +0x000, // 0x1f3 = 499 - NO_OP +0x000, // 0x1f4 = 500 - NO_OP +0x000, // 0x1f5 = 501 - NO_OP +0x000, // 0x1f6 = 502 - NO_OP +0x000, // 0x1f7 = 503 - NO_OP +0x000, // 0x1f8 = 504 - NO_OP +0x000, // 0x1f9 = 505 - NO_OP +0x000, // 0x1fa = 506 - NO_OP +0x000, // 0x1fb = 507 - NO_OP +0x000, // 0x1fc = 508 - NO_OP +0x000, // 0x1fd = 509 - NO_OP +0x000, // 0x1fe = 510 - NO_OP +0x000, // 0x1ff = 511 - NO_OP +}; + +/* wcs with A1302_20 */ +bit32 wcsImage_A1302_20[] = +{ +0x00d, // 00000 = 0 - PHY_RESET_START +0x00d, // 0x001 = 1 - PHY_RESET_START +0x0be, // 0x002 = 2 - JUMP_IF_PHY_READY +0x002, // 0x003 = 3 - +0x0be, // 0x004 = 4 - JUMP_IF_PHY_READY +0x00e, // 0x005 = 5 - +0x0ae, // 0x006 = 6 - JUMP_IF_HARD_RESET_PRIMITIVE +0x024, // 0x007 = 7 - +0x0af, // 0x008 = 8 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x017, // 0x009 = 9 - +0x0ce, // 0x00a = 10 - JUMP_IF_IDENTIFY_FRAME_TIMEOUT +0x000, // 0x00b = 11 - +0x0ff, // 0x00c = 12 - JUMP +0x004, // 0x00d = 13 - +0x00c, // 0x00e = 14 - SEND_ID_FRAME +0x0ae, // 0x00f = 15 - JUMP_IF_HARD_RESET_PRIMITIVE +0x024, // 0x010 = 16 - +0x0af, // 0x011 = 17 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x01c, // 0x012 = 18 - +0x0ce, // 0x013 = 19 - JUMP_IF_IDENTIFY_FRAME_TIMEOUT +0x000, // 0x014 = 20 - +0x0ff, // 0x015 = 21 - JUMP +0x00f, // 0x016 = 22 - +0x0be, // 0x017 = 23 - JUMP_IF_PHY_READY +0x01b, // 0x018 = 24 - +0x0ff, // 0x019 = 25 - JUMP +0x017, // 0x01a = 26 - +0x00c, // 0x01b = 27 - SEND_ID_FRAME +0x000, // 0x01c = 28 - NO_OP +0x000, // 0x01d = 29 - NO_OP +0x000, // 0x01e = 30 - NO_OP +0x000, // 0x01f = 31 - NO_OP +0x000, // 0x020 = 32 - NO_OP +0x000, // 0x021 = 33 - NO_OP +0x0ff, // 0x022 = 34 - JUMP +0x07e, // 0x023 = 35 - +0x01c, // 0x024 = 36 - SOFT_RESET +0x00d, // 0x025 = 37 - PHY_RESET_START +0x00d, // 0x026 = 38 - PHY_RESET_START +0x0be, // 0x027 = 39 - JUMP_IF_PHY_READY +0x027, // 0x028 = 40 - +0x0be, // 0x029 = 41 - JUMP_IF_PHY_READY +0x02f, // 0x02a = 42 - +0x0af, // 0x02b = 43 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x036, // 0x02c = 44 - +0x0ff, // 0x02d = 45 - JUMP +0x029, // 0x02e = 46 - +0x00c, // 0x02f = 47 - SEND_ID_FRAME +0x0af, // 0x030 = 48 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x039, // 0x031 = 49 - +0x0ce, // 0x032 = 50 - JUMP_IF_IDENTIFY_FRAME_TIMEOUT +0x024, // 0x033 = 51 - +0x0ff, // 0x034 = 52 - JUMP +0x030, // 0x035 = 53 - +0x00c, // 0x036 = 54 - SEND_ID_FRAME +0x0ff, // 0x037 = 55 - JUMP +0x039, // 0x038 = 56 - +0x000, // 0x039 = 57 - NO_OP +0x0cb, // 0x03a = 58 - JUMP_IF_FREEZE_ACTIVE +0x03e, // 0x03b = 59 - +0x0ff, // 0x03c = 60 - JUMP +0x03a, // 0x03d = 61 - +0x0cb, // 0x03e = 62 - JUMP_IF_FREEZE_ACTIVE +0x03e, // 0x03f = 63 - +0x0ff, // 0x040 = 64 - JUMP +0x07e, // 0x041 = 65 - +0x000, // 0x042 = 66 - NO_OP +0x0c9, // 0x043 = 67 - JUMP_IF_RX_BUFFER_FULL_TIMEOUT +0x073, // 0x044 = 68 - +0x0a5, // 0x045 = 69 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_GOOD +0x05c, // 0x046 = 70 - +0x0a6, // 0x047 = 71 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_NAK +0x063, // 0x048 = 72 - +0x0a7, // 0x049 = 73 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_ACK_NAK_TIMEOUT +0x066, // 0x04a = 74 - +0x0a8, // 0x04b = 75 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_BREAK +0x070, // 0x04c = 76 - +0x0aa, // 0x04d = 77 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_CREDIT_TIMEOUT +0x06b, // 0x04e = 78 - +0x0c5, // 0x04f = 79 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_SMP_ERR +0x070, // 0x050 = 80 - +0x0ac, // 0x051 = 81 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_MAX_BURST_SIZE +0x063, // 0x052 = 82 - +0x0d9, // 0x053 = 83 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_FREEZE_TIMEOUT +0x070, // 0x054 = 84 - +0x0ca, // 0x055 = 85 - JUMP_IF_CLOSE_REQ +0x10d, // 0x056 = 86 - +0x0be, // 0x057 = 87 - JUMP_IF_PHY_READY +0x043, // 0x058 = 88 - +0x01c, // 0x059 = 89 - SOFT_RESET +0x0ff, // 0x05a = 90 - JUMP +0x004, // 0x05b = 91 - +0x01d, // 0x05c = 92 - ADVANCE +0x0bc, // 0x05d = 93 - JUMP_IF_BREAK_RECEIVED +0x120, // 0x05e = 94 - +0x0c3, // 0x05f = 95 - JUMP_IF_SMP_PROTOCOL +0x10d, // 0x060 = 96 - +0x0ff, // 0x061 = 97 - JUMP +0x076, // 0x062 = 98 - +0x01d, // 0x063 = 99 - ADVANCE +0x0ff, // 0x064 = 100 - JUMP +0x076, // 0x065 = 101 - +0x01d, // 0x066 = 102 - ADVANCE +0x0bc, // 0x067 = 103 - JUMP_IF_BREAK_RECEIVED +0x120, // 0x068 = 104 - +0x0ff, // 0x069 = 105 - JUMP +0x12c, // 0x06a = 106 - +0x01d, // 0x06b = 107 - ADVANCE +0x0bc, // 0x06c = 108 - JUMP_IF_BREAK_RECEIVED +0x120, // 0x06d = 109 - +0x0ff, // 0x06e = 110 - JUMP +0x12f, // 0x06f = 111 - +0x01d, // 0x070 = 112 - ADVANCE +0x0ff, // 0x071 = 113 - JUMP +0x120, // 0x072 = 114 - +0x022, // 0x073 = 115 - SEND_CREDIT_BLOCK +0x0ff, // 0x074 = 116 - JUMP +0x045, // 0x075 = 117 - +0x083, // 0x076 = 118 - TIMER_START +0x004, // 0x077 = 119 - +0x000, // 0x078 = 120 - NO_OP +0x000, // 0x079 = 121 - NO_OP +0x0b8, // 0x07a = 122 - JUMP_IF_TIMER_EXPIRED +0x07e, // 0x07b = 123 - +0x0ff, // 0x07c = 124 - JUMP +0x078, // 0x07d = 125 - +0x0bc, // 0x07e = 126 - JUMP_IF_BREAK_RECEIVED +0x120, // 0x07f = 127 - +0x0be, // 0x080 = 128 - JUMP_IF_PHY_READY +0x085, // 0x081 = 129 - +0x01c, // 0x082 = 130 - SOFT_RESET +0x0ff, // 0x083 = 131 - JUMP +0x004, // 0x084 = 132 - +0x0c8, // 0x085 = 133 - JUMP_IF_HIP_REQ +0x097, // 0x086 = 134 - +0x0c6, // 0x087 = 135 - JUMP_IF_SFO_REQ +0x0a0, // 0x088 = 136 - +0x0c7, // 0x089 = 137 - JUMP_IF_DOC_REQ +0x0ab, // 0x08a = 138 - +0x0a3, // 0x08b = 139 - JUMP_IF_CONNECTION_OPEN_SLAVE_FLAG_SET +0x0ec, // 0x08c = 140 - +0x0a2, // 0x08d = 141 - JUMP_IF_CONNECTION_OPEN_MASTER_FLAG_SET +0x0d5, // 0x08e = 142 - +0x0c8, // 0x08f = 143 - JUMP_IF_HIP_REQ +0x0b4, // 0x090 = 144 - +0x0c6, // 0x091 = 145 - JUMP_IF_SFO_REQ +0x0b9, // 0x092 = 146 - +0x0c7, // 0x093 = 147 - JUMP_IF_DOC_REQ +0x0be, // 0x094 = 148 - +0x0ff, // 0x095 = 149 - JUMP +0x07e, // 0x096 = 150 - +0x028, // 0x097 = 151 - CHECK_HIP +0x000, // 0x098 = 152 - NO_OP +0x000, // 0x099 = 153 - NO_OP +0x000, // 0x09a = 154 - NO_OP +0x000, // 0x09b = 155 - NO_OP +0x0d8, // 0x09c = 156 - JUMP_IF_NXT_CONN_ACTIVE_PROF_EQ +0x0b4, // 0x09d = 157 - +0x0ff, // 0x09e = 158 - JUMP +0x08b, // 0x09f = 159 - +0x029, // 0x0a0 = 160 - CHECK_SFO +0x000, // 0x0a1 = 161 - NO_OP +0x000, // 0x0a2 = 162 - NO_OP +0x000, // 0x0a3 = 163 - NO_OP +0x000, // 0x0a4 = 164 - NO_OP +0x0d8, // 0x0a5 = 165 - JUMP_IF_NXT_CONN_ACTIVE_PROF_EQ +0x0b9, // 0x0a6 = 166 - +0x0c7, // 0x0a7 = 167 - JUMP_IF_DOC_REQ +0x0ab, // 0x0a8 = 168 - +0x0ff, // 0x0a9 = 169 - JUMP +0x08b, // 0x0aa = 170 - +0x02a, // 0x0ab = 171 - CHECK_DOC +0x000, // 0x0ac = 172 - NO_OP +0x000, // 0x0ad = 173 - NO_OP +0x000, // 0x0ae = 174 - NO_OP +0x000, // 0x0af = 175 - NO_OP +0x0d8, // 0x0b0 = 176 - JUMP_IF_NXT_CONN_ACTIVE_PROF_EQ +0x0be, // 0x0b1 = 177 - +0x0ff, // 0x0b2 = 178 - JUMP +0x08b, // 0x0b3 = 179 - +0x020, // 0x0b4 = 180 - SELECT_HIP +0x000, // 0x0b5 = 181 - NO_OP +0x000, // 0x0b6 = 182 - NO_OP +0x0ff, // 0x0b7 = 183 - JUMP +0x0c1, // 0x0b8 = 184 - +0x01e, // 0x0b9 = 185 - SELECT_SFO +0x000, // 0x0ba = 186 - NO_OP +0x000, // 0x0bb = 187 - NO_OP +0x0ff, // 0x0bc = 188 - JUMP +0x0c1, // 0x0bd = 189 - +0x01f, // 0x0be = 190 - SELECT_DOC +0x000, // 0x0bf = 191 - NO_OP +0x000, // 0x0c0 = 192 - NO_OP +0x0a4, // 0x0c1 = 193 - JUMP_IF_CONNECTION_ACTIVE_SET +0x0c5, // 0x0c2 = 194 - +0x0ff, // 0x0c3 = 195 - JUMP +0x132, // 0x0c4 = 196 - +0x0a0, // 0x0c5 = 197 - JUMP_IF_CONNECTION_PROFILE_OPEN_EQUAL +0x0cb, // 0x0c6 = 198 - +0x0a3, // 0x0c7 = 199 - JUMP_IF_CONNECTION_OPEN_SLAVE_FLAG_SET +0x0ec, // 0x0c8 = 200 - +0x0ff, // 0x0c9 = 201 - JUMP +0x10d, // 0x0ca = 202 - +0x0cb, // 0x0cb = 203 - JUMP_IF_FREEZE_ACTIVE +0x0d0, // 0x0cc = 204 - +0x013, // 0x0cd = 205 - SET_OPEN_STATUS_NORMAL +0x0ff, // 0x0ce = 206 - JUMP +0x042, // 0x0cf = 207 - +0x024, // 0x0d0 = 208 - SET_OPEN_STATUS_FREEZE +0x000, // 0x0d1 = 209 - NO_OP +0x000, // 0x0d2 = 210 - NO_OP +0x0ff, // 0x0d3 = 211 - JUMP +0x07e, // 0x0d4 = 212 - +0x0d2, // 0x0d5 = 213 - JUMP_IF_STP_CONNECTION_ACTIVE +0x0d9, // 0x0d6 = 214 - +0x0ff, // 0x0d7 = 215 - JUMP +0x10d, // 0x0d8 = 216 - +0x0d5, // 0x0d9 = 217 - JUMP_IF_CLOSE_RECEIVED +0x10d, // 0x0da = 218 - +0x0d6, // 0x0db = 219 - JUMP_IF_SYNC_RECEIVED +0x0df, // 0x0dc = 220 - +0x0ff, // 0x0dd = 221 - JUMP +0x07e, // 0x0de = 222 - +0x027, // 0x0df = 223 - SEND_STP_CLOSE_REQ +0x000, // 0x0e0 = 224 - NO_OP +0x000, // 0x0e1 = 225 - NO_OP +0x000, // 0x0e2 = 226 - NO_OP +0x000, // 0x0e3 = 227 - NO_OP +0x0d5, // 0x0e4 = 228 - JUMP_IF_CLOSE_RECEIVED +0x10d, // 0x0e5 = 229 - +0x0bc, // 0x0e6 = 230 - JUMP_IF_BREAK_RECEIVED +0x120, // 0x0e7 = 231 - +0x0d7, // 0x0e8 = 232 - JUMP_IF_STP_CLOSE_ACK +0x10d, // 0x0e9 = 233 - +0x0ff, // 0x0ea = 234 - JUMP +0x0e0, // 0x0eb = 235 - +0x0c3, // 0x0ec = 236 - JUMP_IF_SMP_PROTOCOL +0x0f4, // 0x0ed = 237 - +0x0d2, // 0x0ee = 238 - JUMP_IF_STP_CONNECTION_ACTIVE +0x0f8, // 0x0ef = 239 - +0x0d1, // 0x0f0 = 240 - JUMP_IF_IDLE_TIMER_TIMEOUT +0x0fe, // 0x0f1 = 241 - +0x0ff, // 0x0f2 = 242 - JUMP +0x07e, // 0x0f3 = 243 - +0x0c4, // 0x0f4 = 244 - JUMP_IF_SMP_FRAME_ERR_RECEIVED +0x120, // 0x0f5 = 245 - +0x0ff, // 0x0f6 = 246 - JUMP +0x08f, // 0x0f7 = 247 - +0x0d5, // 0x0f8 = 248 - JUMP_IF_CLOSE_RECEIVED +0x0fe, // 0x0f9 = 249 - +0x0d6, // 0x0fa = 250 - JUMP_IF_SYNC_RECEIVED +0x100, // 0x0fb = 251 - +0x0ff, // 0x0fc = 252 - JUMP +0x0f8, // 0x0fd = 253 - +0x0ff, // 0x0fe = 254 - JUMP +0x10d, // 0x0ff = 255 - +0x027, // 0x100 = 256 - SEND_STP_CLOSE_REQ +0x000, // 0x101 = 257 - NO_OP +0x000, // 0x102 = 258 - NO_OP +0x000, // 0x103 = 259 - NO_OP +0x000, // 0x104 = 260 - NO_OP +0x0d5, // 0x105 = 261 - JUMP_IF_CLOSE_RECEIVED +0x10d, // 0x106 = 262 - +0x0bc, // 0x107 = 263 - JUMP_IF_BREAK_RECEIVED +0x120, // 0x108 = 264 - +0x0d7, // 0x109 = 265 - JUMP_IF_STP_CLOSE_ACK +0x10d, // 0x10a = 266 - +0x0ff, // 0x10b = 267 - JUMP +0x101, // 0x10c = 268 - +0x004, // 0x10d = 269 - CLOSE_NORMAL +0x000, // 0x10e = 270 - NO_OP +0x000, // 0x10f = 271 - NO_OP +0x000, // 0x110 = 272 - NO_OP +0x000, // 0x111 = 273 - NO_OP +0x0c9, // 0x112 = 274 - JUMP_IF_RX_BUFFER_FULL_TIMEOUT +0x11d, // 0x113 = 275 - +0x0c0, // 0x114 = 276 - JUMP_IF_CLOSE_STATUS_EQUAL_ANY +0x07e, // 0x115 = 277 - +0x0bc, // 0x116 = 278 - JUMP_IF_BREAK_RECEIVED +0x120, // 0x117 = 279 - +0x0be, // 0x118 = 280 - JUMP_IF_PHY_READY +0x10e, // 0x119 = 281 - +0x01c, // 0x11a = 282 - SOFT_RESET +0x0ff, // 0x11b = 283 - JUMP +0x004, // 0x11c = 284 - +0x022, // 0x11d = 285 - SEND_CREDIT_BLOCK +0x0ff, // 0x11e = 286 - JUMP +0x10e, // 0x11f = 287 - +0x007, // 0x120 = 288 - CLOSE_BREAK +0x000, // 0x121 = 289 - NO_OP +0x000, // 0x122 = 290 - NO_OP +0x000, // 0x123 = 291 - NO_OP +0x000, // 0x124 = 292 - NO_OP +0x0c0, // 0x125 = 293 - JUMP_IF_CLOSE_STATUS_EQUAL_ANY +0x07e, // 0x126 = 294 - +0x0be, // 0x127 = 295 - JUMP_IF_PHY_READY +0x121, // 0x128 = 296 - +0x01c, // 0x129 = 297 - SOFT_RESET +0x0ff, // 0x12a = 298 - JUMP +0x004, // 0x12b = 299 - +0x005, // 0x12c = 300 - CLOSE_ACK_NAK_TIMEOUT +0x0ff, // 0x12d = 301 - JUMP +0x10e, // 0x12e = 302 - +0x006, // 0x12f = 303 - CLOSE_CREDIT_TIMEOUT +0x0ff, // 0x130 = 304 - JUMP +0x10e, // 0x131 = 305 - +0x0cc, // 0x132 = 306 - JUMP_IF_RX_BUFFER_FULL +0x07e, // 0x133 = 307 - +0x0b7, // 0x134 = 308 - JUMP_IF_FLAG_7_SET +0x139, // 0x135 = 309 - +0x011, // 0x136 = 310 - START_IT_NEXUS_LOSS_TIMER +0x00f, // 0x137 = 311 - PATHWAY_BLOCKED_CNT_RESET +0x00e, // 0x138 = 312 - START_ARB_WAIT_TIMER +0x0cb, // 0x139 = 313 - JUMP_IF_FREEZE_ACTIVE +0x17a, // 0x13a = 314 - +0x001, // 0x13b = 315 - OPEN_REQUEST +0x080, // 0x13c = 316 - SET_FLAG +0x080, // 0x13d = 317 - +0x090, // 0x13e = 318 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_ACCEPT +0x164, // 0x13f = 319 - +0x095, // 0x140 = 320 - JUMP_IF_OPEN_STATUS_EQUAL_RATE_NOT_SUPPORTED +0x169, // 0x141 = 321 - +0x099, // 0x142 = 322 - JUMP_IF_OPEN_STATUS_EQUAL_PROTOCOL_NOT_SUPPORTED +0x16c, // 0x143 = 323 - +0x09b, // 0x144 = 324 - JUMP_IF_OPEN_STATUS_EQUAL_WRONG_DESTINATION +0x16f, // 0x145 = 325 - +0x094, // 0x146 = 326 - JUMP_IF_OPEN_STATUS_EQUAL_BREAK_RECEIVED +0x139, // 0x147 = 327 - +0x093, // 0x148 = 328 - JUMP_IF_OPEN_STATUS_EQUAL_BAD_DESTINATION +0x172, // 0x149 = 329 - +0x09f, // 0x14a = 330 - JUMP_IF_IT_NEXUS_LOSS_TIMEOUT +0x175, // 0x14b = 331 - +0x09a, // 0x14c = 332 - JUMP_IF_OPEN_STATUS_EQUAL_STP_RESOURCE_BUSY +0x139, // 0x14d = 333 - +0x096, // 0x14e = 334 - JUMP_IF_OPEN_STATUS_EQUAL_NO_DESTINATION +0x139, // 0x14f = 335 - +0x097, // 0x150 = 336 - JUMP_IF_OPEN_STATUS_EQUAL_PATHWAY_BLOCKED +0x17f, // 0x151 = 337 - +0x098, // 0x152 = 338 - JUMP_IF_OPEN_STATUS_EQUAL_RETRY +0x139, // 0x153 = 339 - +0x092, // 0x154 = 340 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_TIMEOUT +0x139, // 0x155 = 341 - +0x0a4, // 0x156 = 342 - JUMP_IF_CONNECTION_ACTIVE_SET +0x15e, // 0x157 = 343 - +0x0be, // 0x158 = 344 - JUMP_IF_PHY_READY +0x13e, // 0x159 = 345 - +0x01b, // 0x15a = 346 - SET_OPEN_STATUS_PHY_NOT_RDY +0x01c, // 0x15b = 347 - SOFT_RESET +0x0ff, // 0x15c = 348 - JUMP +0x004, // 0x15d = 349 - +0x0a0, // 0x15e = 350 - JUMP_IF_CONNECTION_PROFILE_OPEN_EQUAL +0x164, // 0x15f = 351 - +0x000, // 0x160 = 352 - NO_OP +0x000, // 0x161 = 353 - NO_OP +0x0ff, // 0x162 = 354 - JUMP +0x07e, // 0x163 = 355 - +0x013, // 0x164 = 356 - SET_OPEN_STATUS_NORMAL +0x081, // 0x165 = 357 - CLEAR_FLAG +0x080, // 0x166 = 358 - +0x0ff, // 0x167 = 359 - JUMP +0x042, // 0x168 = 360 - +0x017, // 0x169 = 361 - SET_OPEN_STATUS_BAD_RATE +0x0ff, // 0x16a = 362 - JUMP +0x17b, // 0x16b = 363 - +0x018, // 0x16c = 364 - SET_OPEN_STATUS_BAD_PROTOCOL +0x0ff, // 0x16d = 365 - JUMP +0x17b, // 0x16e = 366 - +0x01a, // 0x16f = 367 - SET_OPEN_STATUS_WRONG_DEST +0x0ff, // 0x170 = 368 - JUMP +0x17b, // 0x171 = 369 - +0x015, // 0x172 = 370 - SET_OPEN_STATUS_BAD_DEST +0x0ff, // 0x173 = 371 - JUMP +0x17b, // 0x174 = 372 - +0x014, // 0x175 = 373 - SET_OPEN_STATUS_IT_NEXUS_LOSS +0x081, // 0x176 = 374 - CLEAR_FLAG +0x080, // 0x177 = 375 - +0x0ff, // 0x178 = 376 - JUMP +0x17b, // 0x179 = 377 - +0x024, // 0x17a = 378 - SET_OPEN_STATUS_FREEZE +0x000, // 0x17b = 379 - NO_OP +0x000, // 0x17c = 380 - NO_OP +0x0ff, // 0x17d = 381 - JUMP +0x07e, // 0x17e = 382 - +0x010, // 0x17f = 383 - PATHWAY_BLOCKED_CNT_INC +0x0ff, // 0x180 = 384 - JUMP +0x139, // 0x181 = 385 - +0x000, // 0x182 = 386 - NO_OP +0x000, // 0x183 = 387 - NO_OP +0x000, // 0x184 = 388 - NO_OP +0x000, // 0x185 = 389 - NO_OP +0x000, // 0x186 = 390 - NO_OP +0x000, // 0x187 = 391 - NO_OP +0x000, // 0x188 = 392 - NO_OP +0x000, // 0x189 = 393 - NO_OP +0x000, // 0x18a = 394 - NO_OP +0x000, // 0x18b = 395 - NO_OP +0x000, // 0x18c = 396 - NO_OP +0x000, // 0x18d = 397 - NO_OP +0x000, // 0x18e = 398 - NO_OP +0x000, // 0x18f = 399 - NO_OP +0x000, // 0x190 = 400 - NO_OP +0x000, // 0x191 = 401 - NO_OP +0x000, // 0x192 = 402 - NO_OP +0x000, // 0x193 = 403 - NO_OP +0x000, // 0x194 = 404 - NO_OP +0x000, // 0x195 = 405 - NO_OP +0x000, // 0x196 = 406 - NO_OP +0x000, // 0x197 = 407 - NO_OP +0x000, // 0x198 = 408 - NO_OP +0x000, // 0x199 = 409 - NO_OP +0x000, // 0x19a = 410 - NO_OP +0x000, // 0x19b = 411 - NO_OP +0x000, // 0x19c = 412 - NO_OP +0x000, // 0x19d = 413 - NO_OP +0x000, // 0x19e = 414 - NO_OP +0x000, // 0x19f = 415 - NO_OP +0x000, // 0x1a0 = 416 - NO_OP +0x000, // 0x1a1 = 417 - NO_OP +0x000, // 0x1a2 = 418 - NO_OP +0x000, // 0x1a3 = 419 - NO_OP +0x000, // 0x1a4 = 420 - NO_OP +0x000, // 0x1a5 = 421 - NO_OP +0x000, // 0x1a6 = 422 - NO_OP +0x000, // 0x1a7 = 423 - NO_OP +0x000, // 0x1a8 = 424 - NO_OP +0x000, // 0x1a9 = 425 - NO_OP +0x000, // 0x1aa = 426 - NO_OP +0x000, // 0x1ab = 427 - NO_OP +0x000, // 0x1ac = 428 - NO_OP +0x000, // 0x1ad = 429 - NO_OP +0x000, // 0x1ae = 430 - NO_OP +0x000, // 0x1af = 431 - NO_OP +0x000, // 0x1b0 = 432 - NO_OP +0x000, // 0x1b1 = 433 - NO_OP +0x000, // 0x1b2 = 434 - NO_OP +0x000, // 0x1b3 = 435 - NO_OP +0x000, // 0x1b4 = 436 - NO_OP +0x000, // 0x1b5 = 437 - NO_OP +0x000, // 0x1b6 = 438 - NO_OP +0x000, // 0x1b7 = 439 - NO_OP +0x000, // 0x1b8 = 440 - NO_OP +0x000, // 0x1b9 = 441 - NO_OP +0x000, // 0x1ba = 442 - NO_OP +0x000, // 0x1bb = 443 - NO_OP +0x000, // 0x1bc = 444 - NO_OP +0x000, // 0x1bd = 445 - NO_OP +0x000, // 0x1be = 446 - NO_OP +0x000, // 0x1bf = 447 - NO_OP +0x000, // 0x1c0 = 448 - NO_OP +0x000, // 0x1c1 = 449 - NO_OP +0x000, // 0x1c2 = 450 - NO_OP +0x000, // 0x1c3 = 451 - NO_OP +0x000, // 0x1c4 = 452 - NO_OP +0x000, // 0x1c5 = 453 - NO_OP +0x000, // 0x1c6 = 454 - NO_OP +0x000, // 0x1c7 = 455 - NO_OP +0x000, // 0x1c8 = 456 - NO_OP +0x000, // 0x1c9 = 457 - NO_OP +0x000, // 0x1ca = 458 - NO_OP +0x000, // 0x1cb = 459 - NO_OP +0x000, // 0x1cc = 460 - NO_OP +0x000, // 0x1cd = 461 - NO_OP +0x000, // 0x1ce = 462 - NO_OP +0x000, // 0x1cf = 463 - NO_OP +0x000, // 0x1d0 = 464 - NO_OP +0x000, // 0x1d1 = 465 - NO_OP +0x000, // 0x1d2 = 466 - NO_OP +0x000, // 0x1d3 = 467 - NO_OP +0x000, // 0x1d4 = 468 - NO_OP +0x000, // 0x1d5 = 469 - NO_OP +0x000, // 0x1d6 = 470 - NO_OP +0x000, // 0x1d7 = 471 - NO_OP +0x000, // 0x1d8 = 472 - NO_OP +0x000, // 0x1d9 = 473 - NO_OP +0x000, // 0x1da = 474 - NO_OP +0x000, // 0x1db = 475 - NO_OP +0x000, // 0x1dc = 476 - NO_OP +0x000, // 0x1dd = 477 - NO_OP +0x000, // 0x1de = 478 - NO_OP +0x000, // 0x1df = 479 - NO_OP +0x000, // 0x1e0 = 480 - NO_OP +0x000, // 0x1e1 = 481 - NO_OP +0x000, // 0x1e2 = 482 - NO_OP +0x000, // 0x1e3 = 483 - NO_OP +0x000, // 0x1e4 = 484 - NO_OP +0x000, // 0x1e5 = 485 - NO_OP +0x000, // 0x1e6 = 486 - NO_OP +0x000, // 0x1e7 = 487 - NO_OP +0x000, // 0x1e8 = 488 - NO_OP +0x000, // 0x1e9 = 489 - NO_OP +0x000, // 0x1ea = 490 - NO_OP +0x000, // 0x1eb = 491 - NO_OP +0x000, // 0x1ec = 492 - NO_OP +0x000, // 0x1ed = 493 - NO_OP +0x000, // 0x1ee = 494 - NO_OP +0x000, // 0x1ef = 495 - NO_OP +0x000, // 0x1f0 = 496 - NO_OP +0x000, // 0x1f1 = 497 - NO_OP +0x000, // 0x1f2 = 498 - NO_OP +0x000, // 0x1f3 = 499 - NO_OP +0x000, // 0x1f4 = 500 - NO_OP +0x000, // 0x1f5 = 501 - NO_OP +0x000, // 0x1f6 = 502 - NO_OP +0x000, // 0x1f7 = 503 - NO_OP +0x000, // 0x1f8 = 504 - NO_OP +0x000, // 0x1f9 = 505 - NO_OP +0x000, // 0x1fa = 506 - NO_OP +0x000, // 0x1fb = 507 - NO_OP +0x000, // 0x1fc = 508 - NO_OP +0x000, // 0x1fd = 509 - NO_OP +0x000, // 0x1fe = 510 - NO_OP +0x000, // 0x1ff = 511 - NO_OP +}; + + +/* wcs with A1304_24 and A1305_28 */ +bit32 wcsImage1304_24[] = +{ +0x00d, // 00000 = 0 - PHY_RESET_START +0x00d, // 0x001 = 1 - PHY_RESET_START +0x0be, // 0x002 = 2 - JUMP_IF_PHY_READY +0x002, // 0x003 = 3 - +0x0be, // 0x004 = 4 - JUMP_IF_PHY_READY +0x00e, // 0x005 = 5 - +0x0ae, // 0x006 = 6 - JUMP_IF_HARD_RESET_PRIMITIVE +0x024, // 0x007 = 7 - +0x0af, // 0x008 = 8 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x017, // 0x009 = 9 - +0x0ce, // 0x00a = 10 - JUMP_IF_IDENTIFY_FRAME_TIMEOUT +0x000, // 0x00b = 11 - +0x0ff, // 0x00c = 12 - JUMP +0x004, // 0x00d = 13 - +0x00c, // 0x00e = 14 - SEND_ID_FRAME +0x0ae, // 0x00f = 15 - JUMP_IF_HARD_RESET_PRIMITIVE +0x024, // 0x010 = 16 - +0x0af, // 0x011 = 17 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x01c, // 0x012 = 18 - +0x0ce, // 0x013 = 19 - JUMP_IF_IDENTIFY_FRAME_TIMEOUT +0x000, // 0x014 = 20 - +0x0ff, // 0x015 = 21 - JUMP +0x00f, // 0x016 = 22 - +0x0be, // 0x017 = 23 - JUMP_IF_PHY_READY +0x01b, // 0x018 = 24 - +0x0ff, // 0x019 = 25 - JUMP +0x017, // 0x01a = 26 - +0x00c, // 0x01b = 27 - SEND_ID_FRAME +0x000, // 0x01c = 28 - NO_OP +0x000, // 0x01d = 29 - NO_OP +0x000, // 0x01e = 30 - NO_OP +0x000, // 0x01f = 31 - NO_OP +0x000, // 0x020 = 32 - NO_OP +0x000, // 0x021 = 33 - NO_OP +0x0ff, // 0x022 = 34 - JUMP +0x09c, // 0x023 = 35 - +0x01c, // 0x024 = 36 - SOFT_RESET +0x00d, // 0x025 = 37 - PHY_RESET_START +0x00d, // 0x026 = 38 - PHY_RESET_START +0x0be, // 0x027 = 39 - JUMP_IF_PHY_READY +0x027, // 0x028 = 40 - +0x0be, // 0x029 = 41 - JUMP_IF_PHY_READY +0x02f, // 0x02a = 42 - +0x0af, // 0x02b = 43 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x036, // 0x02c = 44 - +0x0ff, // 0x02d = 45 - JUMP +0x029, // 0x02e = 46 - +0x00c, // 0x02f = 47 - SEND_ID_FRAME +0x0af, // 0x030 = 48 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x039, // 0x031 = 49 - +0x0ce, // 0x032 = 50 - JUMP_IF_IDENTIFY_FRAME_TIMEOUT +0x024, // 0x033 = 51 - +0x0ff, // 0x034 = 52 - JUMP +0x030, // 0x035 = 53 - +0x00c, // 0x036 = 54 - SEND_ID_FRAME +0x0ff, // 0x037 = 55 - JUMP +0x039, // 0x038 = 56 - +0x000, // 0x039 = 57 - NO_OP +0x0cb, // 0x03a = 58 - JUMP_IF_FREEZE_ACTIVE +0x03e, // 0x03b = 59 - +0x0ff, // 0x03c = 60 - JUMP +0x03a, // 0x03d = 61 - +0x0cb, // 0x03e = 62 - JUMP_IF_FREEZE_ACTIVE +0x03e, // 0x03f = 63 - +0x0ff, // 0x040 = 64 - JUMP +0x09c, // 0x041 = 65 - +0x000, // 0x042 = 66 - NO_OP +0x0c9, // 0x043 = 67 - JUMP_IF_RX_BUFFER_FULL_TIMEOUT +0x073, // 0x044 = 68 - +0x0a5, // 0x045 = 69 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_GOOD +0x05c, // 0x046 = 70 - +0x0a6, // 0x047 = 71 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_NAK +0x063, // 0x048 = 72 - +0x0a7, // 0x049 = 73 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_ACK_NAK_TIMEOUT +0x066, // 0x04a = 74 - +0x0a8, // 0x04b = 75 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_BREAK +0x070, // 0x04c = 76 - +0x0aa, // 0x04d = 77 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_CREDIT_TIMEOUT +0x06b, // 0x04e = 78 - +0x0c5, // 0x04f = 79 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_SMP_ERR +0x070, // 0x050 = 80 - +0x0ac, // 0x051 = 81 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_MAX_BURST_SIZE +0x063, // 0x052 = 82 - +0x0d9, // 0x053 = 83 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_FREEZE_TIMEOUT +0x070, // 0x054 = 84 - +0x0ca, // 0x055 = 85 - JUMP_IF_CLOSE_REQ +0x0f0, // 0x056 = 86 - +0x0be, // 0x057 = 87 - JUMP_IF_PHY_READY +0x043, // 0x058 = 88 - +0x01c, // 0x059 = 89 - SOFT_RESET +0x0ff, // 0x05a = 90 - JUMP +0x004, // 0x05b = 91 - +0x01d, // 0x05c = 92 - ADVANCE +0x0bc, // 0x05d = 93 - JUMP_IF_BREAK_RECEIVED +0x13b, // 0x05e = 94 - +0x0c3, // 0x05f = 95 - JUMP_IF_SMP_PROTOCOL +0x128, // 0x060 = 96 - +0x0ff, // 0x061 = 97 - JUMP +0x076, // 0x062 = 98 - +0x01d, // 0x063 = 99 - ADVANCE +0x0ff, // 0x064 = 100 - JUMP +0x076, // 0x065 = 101 - +0x01d, // 0x066 = 102 - ADVANCE +0x0bc, // 0x067 = 103 - JUMP_IF_BREAK_RECEIVED +0x13b, // 0x068 = 104 - +0x0ff, // 0x069 = 105 - JUMP +0x147, // 0x06a = 106 - +0x01d, // 0x06b = 107 - ADVANCE +0x0bc, // 0x06c = 108 - JUMP_IF_BREAK_RECEIVED +0x13b, // 0x06d = 109 - +0x0ff, // 0x06e = 110 - JUMP +0x14a, // 0x06f = 111 - +0x01d, // 0x070 = 112 - ADVANCE +0x0ff, // 0x071 = 113 - JUMP +0x13b, // 0x072 = 114 - +0x022, // 0x073 = 115 - SEND_CREDIT_BLOCK +0x0ff, // 0x074 = 116 - JUMP +0x045, // 0x075 = 117 - +0x083, // 0x076 = 118 - TIMER_START +0x004, // 0x077 = 119 - +0x0c8, // 0x078 = 120 - JUMP_IF_HIP_REQ +0x082, // 0x079 = 121 - +0x0c6, // 0x07a = 122 - JUMP_IF_SFO_REQ +0x08a, // 0x07b = 123 - +0x0c7, // 0x07c = 124 - JUMP_IF_DOC_REQ +0x094, // 0x07d = 125 - +0x0b8, // 0x07e = 126 - JUMP_IF_TIMER_EXPIRED +0x09c, // 0x07f = 127 - +0x0ff, // 0x080 = 128 - JUMP +0x078, // 0x081 = 129 - +0x028, // 0x082 = 130 - CHECK_HIP +0x000, // 0x083 = 131 - NO_OP +0x000, // 0x084 = 132 - NO_OP +0x000, // 0x085 = 133 - NO_OP +0x0d8, // 0x086 = 134 - JUMP_IF_NXT_CONN_ACTIVE_PROF_EQ +0x0cf, // 0x087 = 135 - +0x0ff, // 0x088 = 136 - JUMP +0x07e, // 0x089 = 137 - +0x029, // 0x08a = 138 - CHECK_SFO +0x000, // 0x08b = 139 - NO_OP +0x000, // 0x08c = 140 - NO_OP +0x000, // 0x08d = 141 - NO_OP +0x0d8, // 0x08e = 142 - JUMP_IF_NXT_CONN_ACTIVE_PROF_EQ +0x0d4, // 0x08f = 143 - +0x0c7, // 0x090 = 144 - JUMP_IF_DOC_REQ +0x094, // 0x091 = 145 - +0x0ff, // 0x092 = 146 - JUMP +0x07e, // 0x093 = 147 - +0x02a, // 0x094 = 148 - CHECK_DOC +0x000, // 0x095 = 149 - NO_OP +0x000, // 0x096 = 150 - NO_OP +0x000, // 0x097 = 151 - NO_OP +0x0d8, // 0x098 = 152 - JUMP_IF_NXT_CONN_ACTIVE_PROF_EQ +0x0d9, // 0x099 = 153 - +0x0ff, // 0x09a = 154 - JUMP +0x07e, // 0x09b = 155 - +0x0bc, // 0x09c = 156 - JUMP_IF_BREAK_RECEIVED +0x13b, // 0x09d = 157 - +0x0be, // 0x09e = 158 - JUMP_IF_PHY_READY +0x0a3, // 0x09f = 159 - +0x01c, // 0x0a0 = 160 - SOFT_RESET +0x0ff, // 0x0a1 = 161 - JUMP +0x004, // 0x0a2 = 162 - +0x0c8, // 0x0a3 = 163 - JUMP_IF_HIP_REQ +0x0b5, // 0x0a4 = 164 - +0x0c6, // 0x0a5 = 165 - JUMP_IF_SFO_REQ +0x0bd, // 0x0a6 = 166 - +0x0c7, // 0x0a7 = 167 - JUMP_IF_DOC_REQ +0x0c7, // 0x0a8 = 168 - +0x0a3, // 0x0a9 = 169 - JUMP_IF_CONNECTION_OPEN_SLAVE_FLAG_SET +0x107, // 0x0aa = 170 - +0x0a2, // 0x0ab = 171 - JUMP_IF_CONNECTION_OPEN_MASTER_FLAG_SET +0x0f0, // 0x0ac = 172 - +0x0c8, // 0x0ad = 173 - JUMP_IF_HIP_REQ +0x0cf, // 0x0ae = 174 - +0x0c6, // 0x0af = 175 - JUMP_IF_SFO_REQ +0x0d4, // 0x0b0 = 176 - +0x0c7, // 0x0b1 = 177 - JUMP_IF_DOC_REQ +0x0d9, // 0x0b2 = 178 - +0x0ff, // 0x0b3 = 179 - JUMP +0x09c, // 0x0b4 = 180 - +0x028, // 0x0b5 = 181 - CHECK_HIP +0x000, // 0x0b6 = 182 - NO_OP +0x000, // 0x0b7 = 183 - NO_OP +0x000, // 0x0b8 = 184 - NO_OP +0x0d8, // 0x0b9 = 185 - JUMP_IF_NXT_CONN_ACTIVE_PROF_EQ +0x0cf, // 0x0ba = 186 - +0x0ff, // 0x0bb = 187 - JUMP +0x0a9, // 0x0bc = 188 - +0x029, // 0x0bd = 189 - CHECK_SFO +0x000, // 0x0be = 190 - NO_OP +0x000, // 0x0bf = 191 - NO_OP +0x000, // 0x0c0 = 192 - NO_OP +0x0d8, // 0x0c1 = 193 - JUMP_IF_NXT_CONN_ACTIVE_PROF_EQ +0x0d4, // 0x0c2 = 194 - +0x0c7, // 0x0c3 = 195 - JUMP_IF_DOC_REQ +0x0c7, // 0x0c4 = 196 - +0x0ff, // 0x0c5 = 197 - JUMP +0x0a9, // 0x0c6 = 198 - +0x02a, // 0x0c7 = 199 - CHECK_DOC +0x000, // 0x0c8 = 200 - NO_OP +0x000, // 0x0c9 = 201 - NO_OP +0x000, // 0x0ca = 202 - NO_OP +0x0d8, // 0x0cb = 203 - JUMP_IF_NXT_CONN_ACTIVE_PROF_EQ +0x0d9, // 0x0cc = 204 - +0x0ff, // 0x0cd = 205 - JUMP +0x0a9, // 0x0ce = 206 - +0x020, // 0x0cf = 207 - SELECT_HIP +0x000, // 0x0d0 = 208 - NO_OP +0x000, // 0x0d1 = 209 - NO_OP +0x0ff, // 0x0d2 = 210 - JUMP +0x0dc, // 0x0d3 = 211 - +0x01e, // 0x0d4 = 212 - SELECT_SFO +0x000, // 0x0d5 = 213 - NO_OP +0x000, // 0x0d6 = 214 - NO_OP +0x0ff, // 0x0d7 = 215 - JUMP +0x0dc, // 0x0d8 = 216 - +0x01f, // 0x0d9 = 217 - SELECT_DOC +0x000, // 0x0da = 218 - NO_OP +0x000, // 0x0db = 219 - NO_OP +0x0a4, // 0x0dc = 220 - JUMP_IF_CONNECTION_ACTIVE_SET +0x0e0, // 0x0dd = 221 - +0x0ff, // 0x0de = 222 - JUMP +0x14d, // 0x0df = 223 - +0x0a0, // 0x0e0 = 224 - JUMP_IF_CONNECTION_PROFILE_OPEN_EQUAL +0x0e6, // 0x0e1 = 225 - +0x0a3, // 0x0e2 = 226 - JUMP_IF_CONNECTION_OPEN_SLAVE_FLAG_SET +0x107, // 0x0e3 = 227 - +0x0ff, // 0x0e4 = 228 - JUMP +0x128, // 0x0e5 = 229 - +0x0cb, // 0x0e6 = 230 - JUMP_IF_FREEZE_ACTIVE +0x0eb, // 0x0e7 = 231 - +0x013, // 0x0e8 = 232 - SET_OPEN_STATUS_NORMAL +0x0ff, // 0x0e9 = 233 - JUMP +0x042, // 0x0ea = 234 - +0x024, // 0x0eb = 235 - SET_OPEN_STATUS_FREEZE +0x000, // 0x0ec = 236 - NO_OP +0x000, // 0x0ed = 237 - NO_OP +0x0ff, // 0x0ee = 238 - JUMP +0x09c, // 0x0ef = 239 - +0x0d2, // 0x0f0 = 240 - JUMP_IF_STP_CONNECTION_ACTIVE +0x0f4, // 0x0f1 = 241 - +0x0ff, // 0x0f2 = 242 - JUMP +0x128, // 0x0f3 = 243 - +0x0d5, // 0x0f4 = 244 - JUMP_IF_CLOSE_RECEIVED +0x128, // 0x0f5 = 245 - +0x0d6, // 0x0f6 = 246 - JUMP_IF_SYNC_RECEIVED +0x0fa, // 0x0f7 = 247 - +0x0ff, // 0x0f8 = 248 - JUMP +0x09c, // 0x0f9 = 249 - +0x027, // 0x0fa = 250 - SEND_STP_CLOSE_REQ +0x000, // 0x0fb = 251 - NO_OP +0x000, // 0x0fc = 252 - NO_OP +0x000, // 0x0fd = 253 - NO_OP +0x000, // 0x0fe = 254 - NO_OP +0x0d5, // 0x0ff = 255 - JUMP_IF_CLOSE_RECEIVED +0x128, // 0x100 = 256 - +0x0bc, // 0x101 = 257 - JUMP_IF_BREAK_RECEIVED +0x13b, // 0x102 = 258 - +0x0d7, // 0x103 = 259 - JUMP_IF_STP_CLOSE_ACK +0x128, // 0x104 = 260 - +0x0ff, // 0x105 = 261 - JUMP +0x0fb, // 0x106 = 262 - +0x0c3, // 0x107 = 263 - JUMP_IF_SMP_PROTOCOL +0x10f, // 0x108 = 264 - +0x0d2, // 0x109 = 265 - JUMP_IF_STP_CONNECTION_ACTIVE +0x113, // 0x10a = 266 - +0x0d1, // 0x10b = 267 - JUMP_IF_IDLE_TIMER_TIMEOUT +0x119, // 0x10c = 268 - +0x0ff, // 0x10d = 269 - JUMP +0x09c, // 0x10e = 270 - +0x0c4, // 0x10f = 271 - JUMP_IF_SMP_FRAME_ERR_RECEIVED +0x13b, // 0x110 = 272 - +0x0ff, // 0x111 = 273 - JUMP +0x0ad, // 0x112 = 274 - +0x0d5, // 0x113 = 275 - JUMP_IF_CLOSE_RECEIVED +0x119, // 0x114 = 276 - +0x0d6, // 0x115 = 277 - JUMP_IF_SYNC_RECEIVED +0x11b, // 0x116 = 278 - +0x0ff, // 0x117 = 279 - JUMP +0x113, // 0x118 = 280 - +0x0ff, // 0x119 = 281 - JUMP +0x128, // 0x11a = 282 - +0x027, // 0x11b = 283 - SEND_STP_CLOSE_REQ +0x000, // 0x11c = 284 - NO_OP +0x000, // 0x11d = 285 - NO_OP +0x000, // 0x11e = 286 - NO_OP +0x000, // 0x11f = 287 - NO_OP +0x0d5, // 0x120 = 288 - JUMP_IF_CLOSE_RECEIVED +0x128, // 0x121 = 289 - +0x0bc, // 0x122 = 290 - JUMP_IF_BREAK_RECEIVED +0x13b, // 0x123 = 291 - +0x0d7, // 0x124 = 292 - JUMP_IF_STP_CLOSE_ACK +0x128, // 0x125 = 293 - +0x0ff, // 0x126 = 294 - JUMP +0x11c, // 0x127 = 295 - +0x004, // 0x128 = 296 - CLOSE_NORMAL +0x000, // 0x129 = 297 - NO_OP +0x000, // 0x12a = 298 - NO_OP +0x000, // 0x12b = 299 - NO_OP +0x000, // 0x12c = 300 - NO_OP +0x0c9, // 0x12d = 301 - JUMP_IF_RX_BUFFER_FULL_TIMEOUT +0x138, // 0x12e = 302 - +0x0c0, // 0x12f = 303 - JUMP_IF_CLOSE_STATUS_EQUAL_ANY +0x09c, // 0x130 = 304 - +0x0bc, // 0x131 = 305 - JUMP_IF_BREAK_RECEIVED +0x13b, // 0x132 = 306 - +0x0be, // 0x133 = 307 - JUMP_IF_PHY_READY +0x129, // 0x134 = 308 - +0x01c, // 0x135 = 309 - SOFT_RESET +0x0ff, // 0x136 = 310 - JUMP +0x004, // 0x137 = 311 - +0x022, // 0x138 = 312 - SEND_CREDIT_BLOCK +0x0ff, // 0x139 = 313 - JUMP +0x129, // 0x13a = 314 - +0x007, // 0x13b = 315 - CLOSE_BREAK +0x000, // 0x13c = 316 - NO_OP +0x000, // 0x13d = 317 - NO_OP +0x000, // 0x13e = 318 - NO_OP +0x000, // 0x13f = 319 - NO_OP +0x0c0, // 0x140 = 320 - JUMP_IF_CLOSE_STATUS_EQUAL_ANY +0x09c, // 0x141 = 321 - +0x0be, // 0x142 = 322 - JUMP_IF_PHY_READY +0x13c, // 0x143 = 323 - +0x01c, // 0x144 = 324 - SOFT_RESET +0x0ff, // 0x145 = 325 - JUMP +0x004, // 0x146 = 326 - +0x005, // 0x147 = 327 - CLOSE_ACK_NAK_TIMEOUT +0x0ff, // 0x148 = 328 - JUMP +0x129, // 0x149 = 329 - +0x006, // 0x14a = 330 - CLOSE_CREDIT_TIMEOUT +0x0ff, // 0x14b = 331 - JUMP +0x129, // 0x14c = 332 - +0x0cc, // 0x14d = 333 - JUMP_IF_RX_BUFFER_FULL +0x09c, // 0x14e = 334 - +0x0b7, // 0x14f = 335 - JUMP_IF_FLAG_7_SET +0x154, // 0x150 = 336 - +0x011, // 0x151 = 337 - START_IT_NEXUS_LOSS_TIMER +0x00f, // 0x152 = 338 - PATHWAY_BLOCKED_CNT_RESET +0x00e, // 0x153 = 339 - START_ARB_WAIT_TIMER +0x0cb, // 0x154 = 340 - JUMP_IF_FREEZE_ACTIVE +0x195, // 0x155 = 341 - +0x001, // 0x156 = 342 - OPEN_REQUEST +0x080, // 0x157 = 343 - SET_FLAG +0x080, // 0x158 = 344 - +0x090, // 0x159 = 345 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_ACCEPT +0x17f, // 0x15a = 346 - +0x095, // 0x15b = 347 - JUMP_IF_OPEN_STATUS_EQUAL_RATE_NOT_SUPPORTED +0x184, // 0x15c = 348 - +0x099, // 0x15d = 349 - JUMP_IF_OPEN_STATUS_EQUAL_PROTOCOL_NOT_SUPPORTED +0x187, // 0x15e = 350 - +0x09b, // 0x15f = 351 - JUMP_IF_OPEN_STATUS_EQUAL_WRONG_DESTINATION +0x18a, // 0x160 = 352 - +0x094, // 0x161 = 353 - JUMP_IF_OPEN_STATUS_EQUAL_BREAK_RECEIVED +0x154, // 0x162 = 354 - +0x093, // 0x163 = 355 - JUMP_IF_OPEN_STATUS_EQUAL_BAD_DESTINATION +0x18d, // 0x164 = 356 - +0x09f, // 0x165 = 357 - JUMP_IF_IT_NEXUS_LOSS_TIMEOUT +0x190, // 0x166 = 358 - +0x09a, // 0x167 = 359 - JUMP_IF_OPEN_STATUS_EQUAL_STP_RESOURCE_BUSY +0x153, // 0x168 = 360 - +0x096, // 0x169 = 361 - JUMP_IF_OPEN_STATUS_EQUAL_NO_DESTINATION +0x154, // 0x16a = 362 - +0x097, // 0x16b = 363 - JUMP_IF_OPEN_STATUS_EQUAL_PATHWAY_BLOCKED +0x19a, // 0x16c = 364 - +0x098, // 0x16d = 365 - JUMP_IF_OPEN_STATUS_EQUAL_RETRY +0x153, // 0x16e = 366 - +0x092, // 0x16f = 367 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_TIMEOUT +0x154, // 0x170 = 368 - +0x0a4, // 0x171 = 369 - JUMP_IF_CONNECTION_ACTIVE_SET +0x179, // 0x172 = 370 - +0x0be, // 0x173 = 371 - JUMP_IF_PHY_READY +0x159, // 0x174 = 372 - +0x01b, // 0x175 = 373 - SET_OPEN_STATUS_PHY_NOT_RDY +0x01c, // 0x176 = 374 - SOFT_RESET +0x0ff, // 0x177 = 375 - JUMP +0x004, // 0x178 = 376 - +0x0a0, // 0x179 = 377 - JUMP_IF_CONNECTION_PROFILE_OPEN_EQUAL +0x17f, // 0x17a = 378 - +0x000, // 0x17b = 379 - NO_OP +0x000, // 0x17c = 380 - NO_OP +0x0ff, // 0x17d = 381 - JUMP +0x09c, // 0x17e = 382 - +0x013, // 0x17f = 383 - SET_OPEN_STATUS_NORMAL +0x081, // 0x180 = 384 - CLEAR_FLAG +0x080, // 0x181 = 385 - +0x0ff, // 0x182 = 386 - JUMP +0x042, // 0x183 = 387 - +0x017, // 0x184 = 388 - SET_OPEN_STATUS_BAD_RATE +0x0ff, // 0x185 = 389 - JUMP +0x196, // 0x186 = 390 - +0x018, // 0x187 = 391 - SET_OPEN_STATUS_BAD_PROTOCOL +0x0ff, // 0x188 = 392 - JUMP +0x196, // 0x189 = 393 - +0x01a, // 0x18a = 394 - SET_OPEN_STATUS_WRONG_DEST +0x0ff, // 0x18b = 395 - JUMP +0x196, // 0x18c = 396 - +0x015, // 0x18d = 397 - SET_OPEN_STATUS_BAD_DEST +0x0ff, // 0x18e = 398 - JUMP +0x196, // 0x18f = 399 - +0x014, // 0x190 = 400 - SET_OPEN_STATUS_IT_NEXUS_LOSS +0x081, // 0x191 = 401 - CLEAR_FLAG +0x080, // 0x192 = 402 - +0x0ff, // 0x193 = 403 - JUMP +0x196, // 0x194 = 404 - +0x024, // 0x195 = 405 - SET_OPEN_STATUS_FREEZE +0x000, // 0x196 = 406 - NO_OP +0x000, // 0x197 = 407 - NO_OP +0x0ff, // 0x198 = 408 - JUMP +0x09c, // 0x199 = 409 - +0x010, // 0x19a = 410 - PATHWAY_BLOCKED_CNT_INC +0x0ff, // 0x19b = 411 - JUMP +0x154, // 0x19c = 412 - +0x000, // 0x19d = 413 - NO_OP +0x000, // 0x19e = 414 - NO_OP +0x000, // 0x19f = 415 - NO_OP +0x000, // 0x1a0 = 416 - NO_OP +0x000, // 0x1a1 = 417 - NO_OP +0x000, // 0x1a2 = 418 - NO_OP +0x000, // 0x1a3 = 419 - NO_OP +0x000, // 0x1a4 = 420 - NO_OP +0x000, // 0x1a5 = 421 - NO_OP +0x000, // 0x1a6 = 422 - NO_OP +0x000, // 0x1a7 = 423 - NO_OP +0x000, // 0x1a8 = 424 - NO_OP +0x000, // 0x1a9 = 425 - NO_OP +0x000, // 0x1aa = 426 - NO_OP +0x000, // 0x1ab = 427 - NO_OP +0x000, // 0x1ac = 428 - NO_OP +0x000, // 0x1ad = 429 - NO_OP +0x000, // 0x1ae = 430 - NO_OP +0x000, // 0x1af = 431 - NO_OP +0x000, // 0x1b0 = 432 - NO_OP +0x000, // 0x1b1 = 433 - NO_OP +0x000, // 0x1b2 = 434 - NO_OP +0x000, // 0x1b3 = 435 - NO_OP +0x000, // 0x1b4 = 436 - NO_OP +0x000, // 0x1b5 = 437 - NO_OP +0x000, // 0x1b6 = 438 - NO_OP +0x000, // 0x1b7 = 439 - NO_OP +0x000, // 0x1b8 = 440 - NO_OP +0x000, // 0x1b9 = 441 - NO_OP +0x000, // 0x1ba = 442 - NO_OP +0x000, // 0x1bb = 443 - NO_OP +0x000, // 0x1bc = 444 - NO_OP +0x000, // 0x1bd = 445 - NO_OP +0x000, // 0x1be = 446 - NO_OP +0x000, // 0x1bf = 447 - NO_OP +0x000, // 0x1c0 = 448 - NO_OP +0x000, // 0x1c1 = 449 - NO_OP +0x000, // 0x1c2 = 450 - NO_OP +0x000, // 0x1c3 = 451 - NO_OP +0x000, // 0x1c4 = 452 - NO_OP +0x000, // 0x1c5 = 453 - NO_OP +0x000, // 0x1c6 = 454 - NO_OP +0x000, // 0x1c7 = 455 - NO_OP +0x000, // 0x1c8 = 456 - NO_OP +0x000, // 0x1c9 = 457 - NO_OP +0x000, // 0x1ca = 458 - NO_OP +0x000, // 0x1cb = 459 - NO_OP +0x000, // 0x1cc = 460 - NO_OP +0x000, // 0x1cd = 461 - NO_OP +0x000, // 0x1ce = 462 - NO_OP +0x000, // 0x1cf = 463 - NO_OP +0x000, // 0x1d0 = 464 - NO_OP +0x000, // 0x1d1 = 465 - NO_OP +0x000, // 0x1d2 = 466 - NO_OP +0x000, // 0x1d3 = 467 - NO_OP +0x000, // 0x1d4 = 468 - NO_OP +0x000, // 0x1d5 = 469 - NO_OP +0x000, // 0x1d6 = 470 - NO_OP +0x000, // 0x1d7 = 471 - NO_OP +0x000, // 0x1d8 = 472 - NO_OP +0x000, // 0x1d9 = 473 - NO_OP +0x000, // 0x1da = 474 - NO_OP +0x000, // 0x1db = 475 - NO_OP +0x000, // 0x1dc = 476 - NO_OP +0x000, // 0x1dd = 477 - NO_OP +0x000, // 0x1de = 478 - NO_OP +0x000, // 0x1df = 479 - NO_OP +0x000, // 0x1e0 = 480 - NO_OP +0x000, // 0x1e1 = 481 - NO_OP +0x000, // 0x1e2 = 482 - NO_OP +0x000, // 0x1e3 = 483 - NO_OP +0x000, // 0x1e4 = 484 - NO_OP +0x000, // 0x1e5 = 485 - NO_OP +0x000, // 0x1e6 = 486 - NO_OP +0x000, // 0x1e7 = 487 - NO_OP +0x000, // 0x1e8 = 488 - NO_OP +0x000, // 0x1e9 = 489 - NO_OP +0x000, // 0x1ea = 490 - NO_OP +0x000, // 0x1eb = 491 - NO_OP +0x000, // 0x1ec = 492 - NO_OP +0x000, // 0x1ed = 493 - NO_OP +0x000, // 0x1ee = 494 - NO_OP +0x000, // 0x1ef = 495 - NO_OP +0x000, // 0x1f0 = 496 - NO_OP +0x000, // 0x1f1 = 497 - NO_OP +0x000, // 0x1f2 = 498 - NO_OP +0x000, // 0x1f3 = 499 - NO_OP +0x000, // 0x1f4 = 500 - NO_OP +0x000, // 0x1f5 = 501 - NO_OP +0x000, // 0x1f6 = 502 - NO_OP +0x000, // 0x1f7 = 503 - NO_OP +0x000, // 0x1f8 = 504 - NO_OP +0x000, // 0x1f9 = 505 - NO_OP +0x000, // 0x1fa = 506 - NO_OP +0x000, // 0x1fb = 507 - NO_OP +0x000, // 0x1fc = 508 - NO_OP +0x000, // 0x1fd = 509 - NO_OP +0x000, // 0x1fe = 510 - NO_OP +0x000, // 0x1ff = 511 - NO_OP +}; + +/* wcs with A1306_02 and A1307_06 */ +bit32 wcsImageA1306_02[] = +{ +0x00d, // 00000 = 0 - PHY_RESET_START +0x00d, // 0x001 = 1 - PHY_RESET_START +0x0be, // 0x002 = 2 - JUMP_IF_PHY_READY +0x002, // 0x003 = 3 - +0x0be, // 0x004 = 4 - JUMP_IF_PHY_READY +0x00e, // 0x005 = 5 - +0x0ae, // 0x006 = 6 - JUMP_IF_HARD_RESET_PRIMITIVE +0x024, // 0x007 = 7 - +0x0af, // 0x008 = 8 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x017, // 0x009 = 9 - +0x0ce, // 0x00a = 10 - JUMP_IF_IDENTIFY_FRAME_TIMEOUT +0x000, // 0x00b = 11 - +0x0ff, // 0x00c = 12 - JUMP +0x004, // 0x00d = 13 - +0x00c, // 0x00e = 14 - SEND_ID_FRAME +0x0ae, // 0x00f = 15 - JUMP_IF_HARD_RESET_PRIMITIVE +0x024, // 0x010 = 16 - +0x0af, // 0x011 = 17 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x01c, // 0x012 = 18 - +0x0ce, // 0x013 = 19 - JUMP_IF_IDENTIFY_FRAME_TIMEOUT +0x000, // 0x014 = 20 - +0x0ff, // 0x015 = 21 - JUMP +0x00f, // 0x016 = 22 - +0x0be, // 0x017 = 23 - JUMP_IF_PHY_READY +0x01b, // 0x018 = 24 - +0x0ff, // 0x019 = 25 - JUMP +0x017, // 0x01a = 26 - +0x00c, // 0x01b = 27 - SEND_ID_FRAME +0x000, // 0x01c = 28 - NO_OP +0x000, // 0x01d = 29 - NO_OP +0x000, // 0x01e = 30 - NO_OP +0x000, // 0x01f = 31 - NO_OP +0x000, // 0x020 = 32 - NO_OP +0x000, // 0x021 = 33 - NO_OP +0x0ff, // 0x022 = 34 - JUMP +0x09c, // 0x023 = 35 - +0x01c, // 0x024 = 36 - SOFT_RESET +0x00d, // 0x025 = 37 - PHY_RESET_START +0x00d, // 0x026 = 38 - PHY_RESET_START +0x0be, // 0x027 = 39 - JUMP_IF_PHY_READY +0x027, // 0x028 = 40 - +0x0be, // 0x029 = 41 - JUMP_IF_PHY_READY +0x02f, // 0x02a = 42 - +0x0af, // 0x02b = 43 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x036, // 0x02c = 44 - +0x0ff, // 0x02d = 45 - JUMP +0x029, // 0x02e = 46 - +0x00c, // 0x02f = 47 - SEND_ID_FRAME +0x0af, // 0x030 = 48 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x039, // 0x031 = 49 - +0x0ce, // 0x032 = 50 - JUMP_IF_IDENTIFY_FRAME_TIMEOUT +0x024, // 0x033 = 51 - +0x0ff, // 0x034 = 52 - JUMP +0x030, // 0x035 = 53 - +0x00c, // 0x036 = 54 - SEND_ID_FRAME +0x0ff, // 0x037 = 55 - JUMP +0x039, // 0x038 = 56 - +0x000, // 0x039 = 57 - NO_OP +0x0cb, // 0x03a = 58 - JUMP_IF_FREEZE_ACTIVE +0x03e, // 0x03b = 59 - +0x0ff, // 0x03c = 60 - JUMP +0x03a, // 0x03d = 61 - +0x0cb, // 0x03e = 62 - JUMP_IF_FREEZE_ACTIVE +0x03e, // 0x03f = 63 - +0x0ff, // 0x040 = 64 - JUMP +0x09c, // 0x041 = 65 - +0x000, // 0x042 = 66 - NO_OP +0x0c9, // 0x043 = 67 - JUMP_IF_RX_BUFFER_FULL_TIMEOUT +0x073, // 0x044 = 68 - +0x0a5, // 0x045 = 69 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_GOOD +0x05c, // 0x046 = 70 - +0x0a6, // 0x047 = 71 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_NAK +0x063, // 0x048 = 72 - +0x0a7, // 0x049 = 73 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_ACK_NAK_TIMEOUT +0x066, // 0x04a = 74 - +0x0a8, // 0x04b = 75 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_BREAK +0x070, // 0x04c = 76 - +0x0aa, // 0x04d = 77 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_CREDIT_TIMEOUT +0x06b, // 0x04e = 78 - +0x0c5, // 0x04f = 79 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_SMP_ERR +0x070, // 0x050 = 80 - +0x0ac, // 0x051 = 81 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_MAX_BURST_SIZE +0x063, // 0x052 = 82 - +0x0d9, // 0x053 = 83 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_FREEZE_TIMEOUT +0x070, // 0x054 = 84 - +0x0ca, // 0x055 = 85 - JUMP_IF_CLOSE_REQ +0x0f0, // 0x056 = 86 - +0x0be, // 0x057 = 87 - JUMP_IF_PHY_READY +0x043, // 0x058 = 88 - +0x01c, // 0x059 = 89 - SOFT_RESET +0x0ff, // 0x05a = 90 - JUMP +0x004, // 0x05b = 91 - +0x01d, // 0x05c = 92 - ADVANCE +0x0bc, // 0x05d = 93 - JUMP_IF_BREAK_RECEIVED +0x13b, // 0x05e = 94 - +0x0c3, // 0x05f = 95 - JUMP_IF_SMP_PROTOCOL +0x128, // 0x060 = 96 - +0x0ff, // 0x061 = 97 - JUMP +0x076, // 0x062 = 98 - +0x01d, // 0x063 = 99 - ADVANCE +0x0ff, // 0x064 = 100 - JUMP +0x076, // 0x065 = 101 - +0x01d, // 0x066 = 102 - ADVANCE +0x0bc, // 0x067 = 103 - JUMP_IF_BREAK_RECEIVED +0x13b, // 0x068 = 104 - +0x0ff, // 0x069 = 105 - JUMP +0x147, // 0x06a = 106 - +0x01d, // 0x06b = 107 - ADVANCE +0x0bc, // 0x06c = 108 - JUMP_IF_BREAK_RECEIVED +0x13b, // 0x06d = 109 - +0x0ff, // 0x06e = 110 - JUMP +0x14a, // 0x06f = 111 - +0x01d, // 0x070 = 112 - ADVANCE +0x0ff, // 0x071 = 113 - JUMP +0x13b, // 0x072 = 114 - +0x022, // 0x073 = 115 - SEND_CREDIT_BLOCK +0x0ff, // 0x074 = 116 - JUMP +0x045, // 0x075 = 117 - +0x083, // 0x076 = 118 - TIMER_START +0x004, // 0x077 = 119 - +0x0c8, // 0x078 = 120 - JUMP_IF_HIP_REQ +0x082, // 0x079 = 121 - +0x0c6, // 0x07a = 122 - JUMP_IF_SFO_REQ +0x08a, // 0x07b = 123 - +0x0c7, // 0x07c = 124 - JUMP_IF_DOC_REQ +0x094, // 0x07d = 125 - +0x0b8, // 0x07e = 126 - JUMP_IF_TIMER_EXPIRED +0x09c, // 0x07f = 127 - +0x0ff, // 0x080 = 128 - JUMP +0x078, // 0x081 = 129 - +0x028, // 0x082 = 130 - CHECK_HIP +0x000, // 0x083 = 131 - NO_OP +0x000, // 0x084 = 132 - NO_OP +0x000, // 0x085 = 133 - NO_OP +0x0d8, // 0x086 = 134 - JUMP_IF_NXT_CONN_ACTIVE_PROF_EQ +0x0cf, // 0x087 = 135 - +0x0ff, // 0x088 = 136 - JUMP +0x07e, // 0x089 = 137 - +0x029, // 0x08a = 138 - CHECK_SFO +0x000, // 0x08b = 139 - NO_OP +0x000, // 0x08c = 140 - NO_OP +0x000, // 0x08d = 141 - NO_OP +0x0d8, // 0x08e = 142 - JUMP_IF_NXT_CONN_ACTIVE_PROF_EQ +0x0d4, // 0x08f = 143 - +0x0c7, // 0x090 = 144 - JUMP_IF_DOC_REQ +0x094, // 0x091 = 145 - +0x0ff, // 0x092 = 146 - JUMP +0x07e, // 0x093 = 147 - +0x02a, // 0x094 = 148 - CHECK_DOC +0x000, // 0x095 = 149 - NO_OP +0x000, // 0x096 = 150 - NO_OP +0x000, // 0x097 = 151 - NO_OP +0x0d8, // 0x098 = 152 - JUMP_IF_NXT_CONN_ACTIVE_PROF_EQ +0x0d9, // 0x099 = 153 - +0x0ff, // 0x09a = 154 - JUMP +0x07e, // 0x09b = 155 - +0x0bc, // 0x09c = 156 - JUMP_IF_BREAK_RECEIVED +0x13b, // 0x09d = 157 - +0x0be, // 0x09e = 158 - JUMP_IF_PHY_READY +0x0a3, // 0x09f = 159 - +0x01c, // 0x0a0 = 160 - SOFT_RESET +0x0ff, // 0x0a1 = 161 - JUMP +0x004, // 0x0a2 = 162 - +0x0c8, // 0x0a3 = 163 - JUMP_IF_HIP_REQ +0x0b5, // 0x0a4 = 164 - +0x0c6, // 0x0a5 = 165 - JUMP_IF_SFO_REQ +0x0bd, // 0x0a6 = 166 - +0x0c7, // 0x0a7 = 167 - JUMP_IF_DOC_REQ +0x0c7, // 0x0a8 = 168 - +0x0a3, // 0x0a9 = 169 - JUMP_IF_CONNECTION_OPEN_SLAVE_FLAG_SET +0x107, // 0x0aa = 170 - +0x0a2, // 0x0ab = 171 - JUMP_IF_CONNECTION_OPEN_MASTER_FLAG_SET +0x0f0, // 0x0ac = 172 - +0x0c8, // 0x0ad = 173 - JUMP_IF_HIP_REQ +0x0cf, // 0x0ae = 174 - +0x0c6, // 0x0af = 175 - JUMP_IF_SFO_REQ +0x0d4, // 0x0b0 = 176 - +0x0c7, // 0x0b1 = 177 - JUMP_IF_DOC_REQ +0x0d9, // 0x0b2 = 178 - +0x0ff, // 0x0b3 = 179 - JUMP +0x09c, // 0x0b4 = 180 - +0x028, // 0x0b5 = 181 - CHECK_HIP +0x000, // 0x0b6 = 182 - NO_OP +0x000, // 0x0b7 = 183 - NO_OP +0x000, // 0x0b8 = 184 - NO_OP +0x0d8, // 0x0b9 = 185 - JUMP_IF_NXT_CONN_ACTIVE_PROF_EQ +0x0cf, // 0x0ba = 186 - +0x0ff, // 0x0bb = 187 - JUMP +0x0a9, // 0x0bc = 188 - +0x029, // 0x0bd = 189 - CHECK_SFO +0x000, // 0x0be = 190 - NO_OP +0x000, // 0x0bf = 191 - NO_OP +0x000, // 0x0c0 = 192 - NO_OP +0x0d8, // 0x0c1 = 193 - JUMP_IF_NXT_CONN_ACTIVE_PROF_EQ +0x0d4, // 0x0c2 = 194 - +0x0c7, // 0x0c3 = 195 - JUMP_IF_DOC_REQ +0x0c7, // 0x0c4 = 196 - +0x0ff, // 0x0c5 = 197 - JUMP +0x0a9, // 0x0c6 = 198 - +0x02a, // 0x0c7 = 199 - CHECK_DOC +0x000, // 0x0c8 = 200 - NO_OP +0x000, // 0x0c9 = 201 - NO_OP +0x000, // 0x0ca = 202 - NO_OP +0x0d8, // 0x0cb = 203 - JUMP_IF_NXT_CONN_ACTIVE_PROF_EQ +0x0d9, // 0x0cc = 204 - +0x0ff, // 0x0cd = 205 - JUMP +0x0a9, // 0x0ce = 206 - +0x020, // 0x0cf = 207 - SELECT_HIP +0x000, // 0x0d0 = 208 - NO_OP +0x000, // 0x0d1 = 209 - NO_OP +0x0ff, // 0x0d2 = 210 - JUMP +0x0dc, // 0x0d3 = 211 - +0x01e, // 0x0d4 = 212 - SELECT_SFO +0x000, // 0x0d5 = 213 - NO_OP +0x000, // 0x0d6 = 214 - NO_OP +0x0ff, // 0x0d7 = 215 - JUMP +0x0dc, // 0x0d8 = 216 - +0x01f, // 0x0d9 = 217 - SELECT_DOC +0x000, // 0x0da = 218 - NO_OP +0x000, // 0x0db = 219 - NO_OP +0x0a4, // 0x0dc = 220 - JUMP_IF_CONNECTION_ACTIVE_SET +0x0e0, // 0x0dd = 221 - +0x0ff, // 0x0de = 222 - JUMP +0x14d, // 0x0df = 223 - +0x0a0, // 0x0e0 = 224 - JUMP_IF_CONNECTION_PROFILE_OPEN_EQUAL +0x0e6, // 0x0e1 = 225 - +0x0a3, // 0x0e2 = 226 - JUMP_IF_CONNECTION_OPEN_SLAVE_FLAG_SET +0x107, // 0x0e3 = 227 - +0x0ff, // 0x0e4 = 228 - JUMP +0x128, // 0x0e5 = 229 - +0x0cb, // 0x0e6 = 230 - JUMP_IF_FREEZE_ACTIVE +0x0eb, // 0x0e7 = 231 - +0x013, // 0x0e8 = 232 - SET_OPEN_STATUS_NORMAL +0x0ff, // 0x0e9 = 233 - JUMP +0x042, // 0x0ea = 234 - +0x024, // 0x0eb = 235 - SET_OPEN_STATUS_FREEZE +0x000, // 0x0ec = 236 - NO_OP +0x000, // 0x0ed = 237 - NO_OP +0x0ff, // 0x0ee = 238 - JUMP +0x09c, // 0x0ef = 239 - +0x0d2, // 0x0f0 = 240 - JUMP_IF_STP_CONNECTION_ACTIVE +0x0f4, // 0x0f1 = 241 - +0x0ff, // 0x0f2 = 242 - JUMP +0x128, // 0x0f3 = 243 - +0x0d5, // 0x0f4 = 244 - JUMP_IF_CLOSE_RECEIVED +0x128, // 0x0f5 = 245 - +0x0d6, // 0x0f6 = 246 - JUMP_IF_SYNC_RECEIVED +0x0fa, // 0x0f7 = 247 - +0x0ff, // 0x0f8 = 248 - JUMP +0x09c, // 0x0f9 = 249 - +0x027, // 0x0fa = 250 - SEND_STP_CLOSE_REQ +0x000, // 0x0fb = 251 - NO_OP +0x000, // 0x0fc = 252 - NO_OP +0x000, // 0x0fd = 253 - NO_OP +0x000, // 0x0fe = 254 - NO_OP +0x0d5, // 0x0ff = 255 - JUMP_IF_CLOSE_RECEIVED +0x128, // 0x100 = 256 - +0x0bc, // 0x101 = 257 - JUMP_IF_BREAK_RECEIVED +0x13b, // 0x102 = 258 - +0x0d7, // 0x103 = 259 - JUMP_IF_STP_CLOSE_ACK +0x128, // 0x104 = 260 - +0x0ff, // 0x105 = 261 - JUMP +0x0fb, // 0x106 = 262 - +0x0c3, // 0x107 = 263 - JUMP_IF_SMP_PROTOCOL +0x10f, // 0x108 = 264 - +0x0d2, // 0x109 = 265 - JUMP_IF_STP_CONNECTION_ACTIVE +0x113, // 0x10a = 266 - +0x0d1, // 0x10b = 267 - JUMP_IF_IDLE_TIMER_TIMEOUT +0x119, // 0x10c = 268 - +0x0ff, // 0x10d = 269 - JUMP +0x09c, // 0x10e = 270 - +0x0c4, // 0x10f = 271 - JUMP_IF_SMP_FRAME_ERR_RECEIVED +0x13b, // 0x110 = 272 - +0x0ff, // 0x111 = 273 - JUMP +0x0ad, // 0x112 = 274 - +0x0d5, // 0x113 = 275 - JUMP_IF_CLOSE_RECEIVED +0x119, // 0x114 = 276 - +0x0d6, // 0x115 = 277 - JUMP_IF_SYNC_RECEIVED +0x11b, // 0x116 = 278 - +0x0ff, // 0x117 = 279 - JUMP +0x113, // 0x118 = 280 - +0x0ff, // 0x119 = 281 - JUMP +0x128, // 0x11a = 282 - +0x027, // 0x11b = 283 - SEND_STP_CLOSE_REQ +0x000, // 0x11c = 284 - NO_OP +0x000, // 0x11d = 285 - NO_OP +0x000, // 0x11e = 286 - NO_OP +0x000, // 0x11f = 287 - NO_OP +0x0d5, // 0x120 = 288 - JUMP_IF_CLOSE_RECEIVED +0x128, // 0x121 = 289 - +0x0bc, // 0x122 = 290 - JUMP_IF_BREAK_RECEIVED +0x13b, // 0x123 = 291 - +0x0d7, // 0x124 = 292 - JUMP_IF_STP_CLOSE_ACK +0x128, // 0x125 = 293 - +0x0ff, // 0x126 = 294 - JUMP +0x11c, // 0x127 = 295 - +0x004, // 0x128 = 296 - CLOSE_NORMAL +0x000, // 0x129 = 297 - NO_OP +0x000, // 0x12a = 298 - NO_OP +0x000, // 0x12b = 299 - NO_OP +0x000, // 0x12c = 300 - NO_OP +0x0c9, // 0x12d = 301 - JUMP_IF_RX_BUFFER_FULL_TIMEOUT +0x138, // 0x12e = 302 - +0x0c0, // 0x12f = 303 - JUMP_IF_CLOSE_STATUS_EQUAL_ANY +0x09c, // 0x130 = 304 - +0x0bc, // 0x131 = 305 - JUMP_IF_BREAK_RECEIVED +0x13b, // 0x132 = 306 - +0x0be, // 0x133 = 307 - JUMP_IF_PHY_READY +0x129, // 0x134 = 308 - +0x01c, // 0x135 = 309 - SOFT_RESET +0x0ff, // 0x136 = 310 - JUMP +0x004, // 0x137 = 311 - +0x022, // 0x138 = 312 - SEND_CREDIT_BLOCK +0x0ff, // 0x139 = 313 - JUMP +0x129, // 0x13a = 314 - +0x007, // 0x13b = 315 - CLOSE_BREAK +0x000, // 0x13c = 316 - NO_OP +0x000, // 0x13d = 317 - NO_OP +0x000, // 0x13e = 318 - NO_OP +0x000, // 0x13f = 319 - NO_OP +0x0c0, // 0x140 = 320 - JUMP_IF_CLOSE_STATUS_EQUAL_ANY +0x09c, // 0x141 = 321 - +0x0be, // 0x142 = 322 - JUMP_IF_PHY_READY +0x13c, // 0x143 = 323 - +0x01c, // 0x144 = 324 - SOFT_RESET +0x0ff, // 0x145 = 325 - JUMP +0x004, // 0x146 = 326 - +0x005, // 0x147 = 327 - CLOSE_ACK_NAK_TIMEOUT +0x0ff, // 0x148 = 328 - JUMP +0x129, // 0x149 = 329 - +0x006, // 0x14a = 330 - CLOSE_CREDIT_TIMEOUT +0x0ff, // 0x14b = 331 - JUMP +0x129, // 0x14c = 332 - +0x0cc, // 0x14d = 333 - JUMP_IF_RX_BUFFER_FULL +0x09c, // 0x14e = 334 - +0x0b7, // 0x14f = 335 - JUMP_IF_FLAG_7_SET +0x154, // 0x150 = 336 - +0x011, // 0x151 = 337 - START_IT_NEXUS_LOSS_TIMER +0x00f, // 0x152 = 338 - PATHWAY_BLOCKED_CNT_RESET +0x00e, // 0x153 = 339 - START_ARB_WAIT_TIMER +0x0cb, // 0x154 = 340 - JUMP_IF_FREEZE_ACTIVE +0x193, // 0x155 = 341 - +0x001, // 0x156 = 342 - OPEN_REQUEST +0x080, // 0x157 = 343 - SET_FLAG +0x080, // 0x158 = 344 - +0x090, // 0x159 = 345 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_ACCEPT +0x17f, // 0x15a = 346 - +0x095, // 0x15b = 347 - JUMP_IF_OPEN_STATUS_EQUAL_RATE_NOT_SUPPORTED +0x184, // 0x15c = 348 - +0x099, // 0x15d = 349 - JUMP_IF_OPEN_STATUS_EQUAL_PROTOCOL_NOT_SUPPORTED +0x187, // 0x15e = 350 - +0x09b, // 0x15f = 351 - JUMP_IF_OPEN_STATUS_EQUAL_WRONG_DESTINATION +0x18a, // 0x160 = 352 - +0x094, // 0x161 = 353 - JUMP_IF_OPEN_STATUS_EQUAL_BREAK_RECEIVED +0x154, // 0x162 = 354 - +0x093, // 0x163 = 355 - JUMP_IF_OPEN_STATUS_EQUAL_BAD_DESTINATION +0x18d, // 0x164 = 356 - +0x09f, // 0x165 = 357 - JUMP_IF_IT_NEXUS_LOSS_TIMEOUT +0x190, // 0x166 = 358 - +0x09a, // 0x167 = 359 - JUMP_IF_OPEN_STATUS_EQUAL_STP_RESOURCE_BUSY +0x153, // 0x168 = 360 - +0x096, // 0x169 = 361 - JUMP_IF_OPEN_STATUS_EQUAL_NO_DESTINATION +0x154, // 0x16a = 362 - +0x097, // 0x16b = 363 - JUMP_IF_OPEN_STATUS_EQUAL_PATHWAY_BLOCKED +0x19a, // 0x16c = 364 - +0x098, // 0x16d = 365 - JUMP_IF_OPEN_STATUS_EQUAL_RETRY +0x153, // 0x16e = 366 - +0x092, // 0x16f = 367 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_TIMEOUT +0x154, // 0x170 = 368 - +0x0a4, // 0x171 = 369 - JUMP_IF_CONNECTION_ACTIVE_SET +0x179, // 0x172 = 370 - +0x0be, // 0x173 = 371 - JUMP_IF_PHY_READY +0x159, // 0x174 = 372 - +0x01b, // 0x175 = 373 - SET_OPEN_STATUS_PHY_NOT_RDY +0x01c, // 0x176 = 374 - SOFT_RESET +0x0ff, // 0x177 = 375 - JUMP +0x004, // 0x178 = 376 - +0x0a0, // 0x179 = 377 - JUMP_IF_CONNECTION_PROFILE_OPEN_EQUAL +0x17f, // 0x17a = 378 - +0x000, // 0x17b = 379 - NO_OP +0x000, // 0x17c = 380 - NO_OP +0x0ff, // 0x17d = 381 - JUMP +0x09c, // 0x17e = 382 - +0x013, // 0x17f = 383 - SET_OPEN_STATUS_NORMAL +0x081, // 0x180 = 384 - CLEAR_FLAG +0x080, // 0x181 = 385 - +0x0ff, // 0x182 = 386 - JUMP +0x042, // 0x183 = 387 - +0x017, // 0x184 = 388 - SET_OPEN_STATUS_BAD_RATE +0x0ff, // 0x185 = 389 - JUMP +0x194, // 0x186 = 390 - +0x018, // 0x187 = 391 - SET_OPEN_STATUS_BAD_PROTOCOL +0x0ff, // 0x188 = 392 - JUMP +0x194, // 0x189 = 393 - +0x01a, // 0x18a = 394 - SET_OPEN_STATUS_WRONG_DEST +0x0ff, // 0x18b = 395 - JUMP +0x194, // 0x18c = 396 - +0x015, // 0x18d = 397 - SET_OPEN_STATUS_BAD_DEST +0x0ff, // 0x18e = 398 - JUMP +0x194, // 0x18f = 399 - +0x014, // 0x190 = 400 - SET_OPEN_STATUS_IT_NEXUS_LOSS +0x0ff, // 0x191 = 401 - JUMP +0x194, // 0x192 = 402 - +0x024, // 0x193 = 403 - SET_OPEN_STATUS_FREEZE +0x000, // 0x194 = 404 - NO_OP +0x000, // 0x195 = 405 - NO_OP +0x081, // 0x196 = 406 - CLEAR_FLAG +0x080, // 0x197 = 407 - +0x0ff, // 0x198 = 408 - JUMP +0x09c, // 0x199 = 409 - +0x010, // 0x19a = 410 - PATHWAY_BLOCKED_CNT_INC +0x0ff, // 0x19b = 411 - JUMP +0x154, // 0x19c = 412 - +0x000, // 0x19d = 413 - NO_OP +0x000, // 0x19e = 414 - NO_OP +0x000, // 0x19f = 415 - NO_OP +0x000, // 0x1a0 = 416 - NO_OP +0x000, // 0x1a1 = 417 - NO_OP +0x000, // 0x1a2 = 418 - NO_OP +0x000, // 0x1a3 = 419 - NO_OP +0x000, // 0x1a4 = 420 - NO_OP +0x000, // 0x1a5 = 421 - NO_OP +0x000, // 0x1a6 = 422 - NO_OP +0x000, // 0x1a7 = 423 - NO_OP +0x000, // 0x1a8 = 424 - NO_OP +0x000, // 0x1a9 = 425 - NO_OP +0x000, // 0x1aa = 426 - NO_OP +0x000, // 0x1ab = 427 - NO_OP +0x000, // 0x1ac = 428 - NO_OP +0x000, // 0x1ad = 429 - NO_OP +0x000, // 0x1ae = 430 - NO_OP +0x000, // 0x1af = 431 - NO_OP +0x000, // 0x1b0 = 432 - NO_OP +0x000, // 0x1b1 = 433 - NO_OP +0x000, // 0x1b2 = 434 - NO_OP +0x000, // 0x1b3 = 435 - NO_OP +0x000, // 0x1b4 = 436 - NO_OP +0x000, // 0x1b5 = 437 - NO_OP +0x000, // 0x1b6 = 438 - NO_OP +0x000, // 0x1b7 = 439 - NO_OP +0x000, // 0x1b8 = 440 - NO_OP +0x000, // 0x1b9 = 441 - NO_OP +0x000, // 0x1ba = 442 - NO_OP +0x000, // 0x1bb = 443 - NO_OP +0x000, // 0x1bc = 444 - NO_OP +0x000, // 0x1bd = 445 - NO_OP +0x000, // 0x1be = 446 - NO_OP +0x000, // 0x1bf = 447 - NO_OP +0x000, // 0x1c0 = 448 - NO_OP +0x000, // 0x1c1 = 449 - NO_OP +0x000, // 0x1c2 = 450 - NO_OP +0x000, // 0x1c3 = 451 - NO_OP +0x000, // 0x1c4 = 452 - NO_OP +0x000, // 0x1c5 = 453 - NO_OP +0x000, // 0x1c6 = 454 - NO_OP +0x000, // 0x1c7 = 455 - NO_OP +0x000, // 0x1c8 = 456 - NO_OP +0x000, // 0x1c9 = 457 - NO_OP +0x000, // 0x1ca = 458 - NO_OP +0x000, // 0x1cb = 459 - NO_OP +0x000, // 0x1cc = 460 - NO_OP +0x000, // 0x1cd = 461 - NO_OP +0x000, // 0x1ce = 462 - NO_OP +0x000, // 0x1cf = 463 - NO_OP +0x000, // 0x1d0 = 464 - NO_OP +0x000, // 0x1d1 = 465 - NO_OP +0x000, // 0x1d2 = 466 - NO_OP +0x000, // 0x1d3 = 467 - NO_OP +0x000, // 0x1d4 = 468 - NO_OP +0x000, // 0x1d5 = 469 - NO_OP +0x000, // 0x1d6 = 470 - NO_OP +0x000, // 0x1d7 = 471 - NO_OP +0x000, // 0x1d8 = 472 - NO_OP +0x000, // 0x1d9 = 473 - NO_OP +0x000, // 0x1da = 474 - NO_OP +0x000, // 0x1db = 475 - NO_OP +0x000, // 0x1dc = 476 - NO_OP +0x000, // 0x1dd = 477 - NO_OP +0x000, // 0x1de = 478 - NO_OP +0x000, // 0x1df = 479 - NO_OP +0x000, // 0x1e0 = 480 - NO_OP +0x000, // 0x1e1 = 481 - NO_OP +0x000, // 0x1e2 = 482 - NO_OP +0x000, // 0x1e3 = 483 - NO_OP +0x000, // 0x1e4 = 484 - NO_OP +0x000, // 0x1e5 = 485 - NO_OP +0x000, // 0x1e6 = 486 - NO_OP +0x000, // 0x1e7 = 487 - NO_OP +0x000, // 0x1e8 = 488 - NO_OP +0x000, // 0x1e9 = 489 - NO_OP +0x000, // 0x1ea = 490 - NO_OP +0x000, // 0x1eb = 491 - NO_OP +0x000, // 0x1ec = 492 - NO_OP +0x000, // 0x1ed = 493 - NO_OP +0x000, // 0x1ee = 494 - NO_OP +0x000, // 0x1ef = 495 - NO_OP +0x000, // 0x1f0 = 496 - NO_OP +0x000, // 0x1f1 = 497 - NO_OP +0x000, // 0x1f2 = 498 - NO_OP +0x000, // 0x1f3 = 499 - NO_OP +0x000, // 0x1f4 = 500 - NO_OP +0x000, // 0x1f5 = 501 - NO_OP +0x000, // 0x1f6 = 502 - NO_OP +0x000, // 0x1f7 = 503 - NO_OP +0x000, // 0x1f8 = 504 - NO_OP +0x000, // 0x1f9 = 505 - NO_OP +0x000, // 0x1fa = 506 - NO_OP +0x000, // 0x1fb = 507 - NO_OP +0x000, // 0x1fc = 508 - NO_OP +0x000, // 0x1fd = 509 - NO_OP +0x000, // 0x1fe = 510 - NO_OP +0x000, // 0x1ff = 511 - NO_OP +}; + +/* for A1307_09 */ +bit32 wcsImageA1307_09[] = +{ +0x00d, // 00000 = 0 - PHY_RESET_START +0x00d, // 0x001 = 1 - PHY_RESET_START +0x0be, // 0x002 = 2 - JUMP_IF_PHY_READY +0x002, // 0x003 = 3 - +0x0be, // 0x004 = 4 - JUMP_IF_PHY_READY +0x00e, // 0x005 = 5 - +0x0ae, // 0x006 = 6 - JUMP_IF_HARD_RESET_PRIMITIVE +0x024, // 0x007 = 7 - +0x0af, // 0x008 = 8 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x017, // 0x009 = 9 - +0x0ce, // 0x00a = 10 - JUMP_IF_IDENTIFY_FRAME_TIMEOUT +0x000, // 0x00b = 11 - +0x0ff, // 0x00c = 12 - JUMP +0x004, // 0x00d = 13 - +0x00c, // 0x00e = 14 - SEND_ID_FRAME +0x0ae, // 0x00f = 15 - JUMP_IF_HARD_RESET_PRIMITIVE +0x024, // 0x010 = 16 - +0x0af, // 0x011 = 17 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x01c, // 0x012 = 18 - +0x0ce, // 0x013 = 19 - JUMP_IF_IDENTIFY_FRAME_TIMEOUT +0x000, // 0x014 = 20 - +0x0ff, // 0x015 = 21 - JUMP +0x00f, // 0x016 = 22 - +0x0be, // 0x017 = 23 - JUMP_IF_PHY_READY +0x01b, // 0x018 = 24 - +0x0ff, // 0x019 = 25 - JUMP +0x017, // 0x01a = 26 - +0x00c, // 0x01b = 27 - SEND_ID_FRAME +0x000, // 0x01c = 28 - NO_OP +0x000, // 0x01d = 29 - NO_OP +0x000, // 0x01e = 30 - NO_OP +0x000, // 0x01f = 31 - NO_OP +0x000, // 0x020 = 32 - NO_OP +0x000, // 0x021 = 33 - NO_OP +0x0ff, // 0x022 = 34 - JUMP +0x09c, // 0x023 = 35 - +0x01c, // 0x024 = 36 - SOFT_RESET +0x00d, // 0x025 = 37 - PHY_RESET_START +0x00d, // 0x026 = 38 - PHY_RESET_START +0x0be, // 0x027 = 39 - JUMP_IF_PHY_READY +0x027, // 0x028 = 40 - +0x0be, // 0x029 = 41 - JUMP_IF_PHY_READY +0x02f, // 0x02a = 42 - +0x0af, // 0x02b = 43 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x036, // 0x02c = 44 - +0x0ff, // 0x02d = 45 - JUMP +0x029, // 0x02e = 46 - +0x00c, // 0x02f = 47 - SEND_ID_FRAME +0x0af, // 0x030 = 48 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x039, // 0x031 = 49 - +0x0ce, // 0x032 = 50 - JUMP_IF_IDENTIFY_FRAME_TIMEOUT +0x024, // 0x033 = 51 - +0x0ff, // 0x034 = 52 - JUMP +0x030, // 0x035 = 53 - +0x00c, // 0x036 = 54 - SEND_ID_FRAME +0x0ff, // 0x037 = 55 - JUMP +0x039, // 0x038 = 56 - +0x000, // 0x039 = 57 - NO_OP +0x0cb, // 0x03a = 58 - JUMP_IF_FREEZE_ACTIVE +0x03e, // 0x03b = 59 - +0x0ff, // 0x03c = 60 - JUMP +0x03a, // 0x03d = 61 - +0x0cb, // 0x03e = 62 - JUMP_IF_FREEZE_ACTIVE +0x03e, // 0x03f = 63 - +0x0ff, // 0x040 = 64 - JUMP +0x09c, // 0x041 = 65 - +0x000, // 0x042 = 66 - NO_OP +0x0c9, // 0x043 = 67 - JUMP_IF_RX_BUFFER_FULL_TIMEOUT +0x073, // 0x044 = 68 - +0x0a5, // 0x045 = 69 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_GOOD +0x05c, // 0x046 = 70 - +0x0a6, // 0x047 = 71 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_NAK +0x063, // 0x048 = 72 - +0x0a7, // 0x049 = 73 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_ACK_NAK_TIMEOUT +0x066, // 0x04a = 74 - +0x0a8, // 0x04b = 75 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_BREAK +0x070, // 0x04c = 76 - +0x0aa, // 0x04d = 77 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_CREDIT_TIMEOUT +0x06b, // 0x04e = 78 - +0x0c5, // 0x04f = 79 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_SMP_ERR +0x070, // 0x050 = 80 - +0x0ac, // 0x051 = 81 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_MAX_BURST_SIZE +0x063, // 0x052 = 82 - +0x0d9, // 0x053 = 83 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_FREEZE_TIMEOUT +0x070, // 0x054 = 84 - +0x0ca, // 0x055 = 85 - JUMP_IF_CLOSE_REQ +0x0f0, // 0x056 = 86 - +0x0be, // 0x057 = 87 - JUMP_IF_PHY_READY +0x043, // 0x058 = 88 - +0x01c, // 0x059 = 89 - SOFT_RESET +0x0ff, // 0x05a = 90 - JUMP +0x004, // 0x05b = 91 - +0x01d, // 0x05c = 92 - ADVANCE +0x0bc, // 0x05d = 93 - JUMP_IF_BREAK_RECEIVED +0x13b, // 0x05e = 94 - +0x0c3, // 0x05f = 95 - JUMP_IF_SMP_PROTOCOL +0x128, // 0x060 = 96 - +0x0ff, // 0x061 = 97 - JUMP +0x076, // 0x062 = 98 - +0x01d, // 0x063 = 99 - ADVANCE +0x0ff, // 0x064 = 100 - JUMP +0x076, // 0x065 = 101 - +0x01d, // 0x066 = 102 - ADVANCE +0x0bc, // 0x067 = 103 - JUMP_IF_BREAK_RECEIVED +0x13b, // 0x068 = 104 - +0x0ff, // 0x069 = 105 - JUMP +0x147, // 0x06a = 106 - +0x01d, // 0x06b = 107 - ADVANCE +0x0bc, // 0x06c = 108 - JUMP_IF_BREAK_RECEIVED +0x13b, // 0x06d = 109 - +0x0ff, // 0x06e = 110 - JUMP +0x14a, // 0x06f = 111 - +0x01d, // 0x070 = 112 - ADVANCE +0x0ff, // 0x071 = 113 - JUMP +0x13b, // 0x072 = 114 - +0x022, // 0x073 = 115 - SEND_CREDIT_BLOCK +0x0ff, // 0x074 = 116 - JUMP +0x045, // 0x075 = 117 - +0x083, // 0x076 = 118 - TIMER_START +0x004, // 0x077 = 119 - +0x0c8, // 0x078 = 120 - JUMP_IF_HIP_REQ +0x082, // 0x079 = 121 - +0x0c6, // 0x07a = 122 - JUMP_IF_SFO_REQ +0x08a, // 0x07b = 123 - +0x0c7, // 0x07c = 124 - JUMP_IF_DOC_REQ +0x094, // 0x07d = 125 - +0x0b8, // 0x07e = 126 - JUMP_IF_TIMER_EXPIRED +0x09c, // 0x07f = 127 - +0x0ff, // 0x080 = 128 - JUMP +0x078, // 0x081 = 129 - +0x028, // 0x082 = 130 - CHECK_HIP +0x000, // 0x083 = 131 - NO_OP +0x000, // 0x084 = 132 - NO_OP +0x000, // 0x085 = 133 - NO_OP +0x0d8, // 0x086 = 134 - JUMP_IF_NXT_CONN_ACTIVE_PROF_EQ +0x0cf, // 0x087 = 135 - +0x0ff, // 0x088 = 136 - JUMP +0x07e, // 0x089 = 137 - +0x029, // 0x08a = 138 - CHECK_SFO +0x000, // 0x08b = 139 - NO_OP +0x000, // 0x08c = 140 - NO_OP +0x000, // 0x08d = 141 - NO_OP +0x0d8, // 0x08e = 142 - JUMP_IF_NXT_CONN_ACTIVE_PROF_EQ +0x0d4, // 0x08f = 143 - +0x0c7, // 0x090 = 144 - JUMP_IF_DOC_REQ +0x094, // 0x091 = 145 - +0x0ff, // 0x092 = 146 - JUMP +0x07e, // 0x093 = 147 - +0x02a, // 0x094 = 148 - CHECK_DOC +0x000, // 0x095 = 149 - NO_OP +0x000, // 0x096 = 150 - NO_OP +0x000, // 0x097 = 151 - NO_OP +0x0d8, // 0x098 = 152 - JUMP_IF_NXT_CONN_ACTIVE_PROF_EQ +0x0d9, // 0x099 = 153 - +0x0ff, // 0x09a = 154 - JUMP +0x07e, // 0x09b = 155 - +0x0bc, // 0x09c = 156 - JUMP_IF_BREAK_RECEIVED +0x13b, // 0x09d = 157 - +0x0be, // 0x09e = 158 - JUMP_IF_PHY_READY +0x0a3, // 0x09f = 159 - +0x01c, // 0x0a0 = 160 - SOFT_RESET +0x0ff, // 0x0a1 = 161 - JUMP +0x004, // 0x0a2 = 162 - +0x0c8, // 0x0a3 = 163 - JUMP_IF_HIP_REQ +0x0b5, // 0x0a4 = 164 - +0x0c6, // 0x0a5 = 165 - JUMP_IF_SFO_REQ +0x0bd, // 0x0a6 = 166 - +0x0c7, // 0x0a7 = 167 - JUMP_IF_DOC_REQ +0x0c7, // 0x0a8 = 168 - +0x0a3, // 0x0a9 = 169 - JUMP_IF_CONNECTION_OPEN_SLAVE_FLAG_SET +0x107, // 0x0aa = 170 - +0x0a2, // 0x0ab = 171 - JUMP_IF_CONNECTION_OPEN_MASTER_FLAG_SET +0x0f0, // 0x0ac = 172 - +0x0c8, // 0x0ad = 173 - JUMP_IF_HIP_REQ +0x0cf, // 0x0ae = 174 - +0x0c6, // 0x0af = 175 - JUMP_IF_SFO_REQ +0x0d4, // 0x0b0 = 176 - +0x0c7, // 0x0b1 = 177 - JUMP_IF_DOC_REQ +0x0d9, // 0x0b2 = 178 - +0x0ff, // 0x0b3 = 179 - JUMP +0x09c, // 0x0b4 = 180 - +0x028, // 0x0b5 = 181 - CHECK_HIP +0x000, // 0x0b6 = 182 - NO_OP +0x000, // 0x0b7 = 183 - NO_OP +0x000, // 0x0b8 = 184 - NO_OP +0x0d8, // 0x0b9 = 185 - JUMP_IF_NXT_CONN_ACTIVE_PROF_EQ +0x0cf, // 0x0ba = 186 - +0x0ff, // 0x0bb = 187 - JUMP +0x0a9, // 0x0bc = 188 - +0x029, // 0x0bd = 189 - CHECK_SFO +0x000, // 0x0be = 190 - NO_OP +0x000, // 0x0bf = 191 - NO_OP +0x000, // 0x0c0 = 192 - NO_OP +0x0d8, // 0x0c1 = 193 - JUMP_IF_NXT_CONN_ACTIVE_PROF_EQ +0x0d4, // 0x0c2 = 194 - +0x0c7, // 0x0c3 = 195 - JUMP_IF_DOC_REQ +0x0c7, // 0x0c4 = 196 - +0x0ff, // 0x0c5 = 197 - JUMP +0x0a9, // 0x0c6 = 198 - +0x02a, // 0x0c7 = 199 - CHECK_DOC +0x000, // 0x0c8 = 200 - NO_OP +0x000, // 0x0c9 = 201 - NO_OP +0x000, // 0x0ca = 202 - NO_OP +0x0d8, // 0x0cb = 203 - JUMP_IF_NXT_CONN_ACTIVE_PROF_EQ +0x0d9, // 0x0cc = 204 - +0x0ff, // 0x0cd = 205 - JUMP +0x0a9, // 0x0ce = 206 - +0x020, // 0x0cf = 207 - SELECT_HIP +0x000, // 0x0d0 = 208 - NO_OP +0x000, // 0x0d1 = 209 - NO_OP +0x0ff, // 0x0d2 = 210 - JUMP +0x0dc, // 0x0d3 = 211 - +0x01e, // 0x0d4 = 212 - SELECT_SFO +0x000, // 0x0d5 = 213 - NO_OP +0x000, // 0x0d6 = 214 - NO_OP +0x0ff, // 0x0d7 = 215 - JUMP +0x0dc, // 0x0d8 = 216 - +0x01f, // 0x0d9 = 217 - SELECT_DOC +0x000, // 0x0da = 218 - NO_OP +0x000, // 0x0db = 219 - NO_OP +0x0a4, // 0x0dc = 220 - JUMP_IF_CONNECTION_ACTIVE_SET +0x0e0, // 0x0dd = 221 - +0x0ff, // 0x0de = 222 - JUMP +0x14d, // 0x0df = 223 - +0x0a0, // 0x0e0 = 224 - JUMP_IF_CONNECTION_PROFILE_OPEN_EQUAL +0x0e6, // 0x0e1 = 225 - +0x0a3, // 0x0e2 = 226 - JUMP_IF_CONNECTION_OPEN_SLAVE_FLAG_SET +0x107, // 0x0e3 = 227 - +0x0ff, // 0x0e4 = 228 - JUMP +0x0f0, // 0x0e5 = 229 - +0x0cb, // 0x0e6 = 230 - JUMP_IF_FREEZE_ACTIVE +0x0eb, // 0x0e7 = 231 - +0x013, // 0x0e8 = 232 - SET_OPEN_STATUS_NORMAL +0x0ff, // 0x0e9 = 233 - JUMP +0x042, // 0x0ea = 234 - +0x024, // 0x0eb = 235 - SET_OPEN_STATUS_FREEZE +0x000, // 0x0ec = 236 - NO_OP +0x000, // 0x0ed = 237 - NO_OP +0x0ff, // 0x0ee = 238 - JUMP +0x09c, // 0x0ef = 239 - +0x0d2, // 0x0f0 = 240 - JUMP_IF_STP_CONNECTION_ACTIVE +0x0f4, // 0x0f1 = 241 - +0x0ff, // 0x0f2 = 242 - JUMP +0x128, // 0x0f3 = 243 - +0x0d5, // 0x0f4 = 244 - JUMP_IF_CLOSE_RECEIVED +0x128, // 0x0f5 = 245 - +0x0d6, // 0x0f6 = 246 - JUMP_IF_SYNC_RECEIVED +0x0fa, // 0x0f7 = 247 - +0x0ff, // 0x0f8 = 248 - JUMP +0x09c, // 0x0f9 = 249 - +0x027, // 0x0fa = 250 - SEND_STP_CLOSE_REQ +0x000, // 0x0fb = 251 - NO_OP +0x000, // 0x0fc = 252 - NO_OP +0x000, // 0x0fd = 253 - NO_OP +0x000, // 0x0fe = 254 - NO_OP +0x0d5, // 0x0ff = 255 - JUMP_IF_CLOSE_RECEIVED +0x128, // 0x100 = 256 - +0x0bc, // 0x101 = 257 - JUMP_IF_BREAK_RECEIVED +0x13b, // 0x102 = 258 - +0x0d7, // 0x103 = 259 - JUMP_IF_STP_CLOSE_ACK +0x128, // 0x104 = 260 - +0x0ff, // 0x105 = 261 - JUMP +0x0fb, // 0x106 = 262 - +0x0c3, // 0x107 = 263 - JUMP_IF_SMP_PROTOCOL +0x10f, // 0x108 = 264 - +0x0d2, // 0x109 = 265 - JUMP_IF_STP_CONNECTION_ACTIVE +0x113, // 0x10a = 266 - +0x0d1, // 0x10b = 267 - JUMP_IF_IDLE_TIMER_TIMEOUT +0x119, // 0x10c = 268 - +0x0ff, // 0x10d = 269 - JUMP +0x09c, // 0x10e = 270 - +0x0c4, // 0x10f = 271 - JUMP_IF_SMP_FRAME_ERR_RECEIVED +0x13b, // 0x110 = 272 - +0x0ff, // 0x111 = 273 - JUMP +0x0ad, // 0x112 = 274 - +0x0d5, // 0x113 = 275 - JUMP_IF_CLOSE_RECEIVED +0x119, // 0x114 = 276 - +0x0d6, // 0x115 = 277 - JUMP_IF_SYNC_RECEIVED +0x11b, // 0x116 = 278 - +0x0ff, // 0x117 = 279 - JUMP +0x113, // 0x118 = 280 - +0x0ff, // 0x119 = 281 - JUMP +0x128, // 0x11a = 282 - +0x027, // 0x11b = 283 - SEND_STP_CLOSE_REQ +0x000, // 0x11c = 284 - NO_OP +0x000, // 0x11d = 285 - NO_OP +0x000, // 0x11e = 286 - NO_OP +0x000, // 0x11f = 287 - NO_OP +0x0d5, // 0x120 = 288 - JUMP_IF_CLOSE_RECEIVED +0x128, // 0x121 = 289 - +0x0bc, // 0x122 = 290 - JUMP_IF_BREAK_RECEIVED +0x13b, // 0x123 = 291 - +0x0d7, // 0x124 = 292 - JUMP_IF_STP_CLOSE_ACK +0x128, // 0x125 = 293 - +0x0ff, // 0x126 = 294 - JUMP +0x11c, // 0x127 = 295 - +0x004, // 0x128 = 296 - CLOSE_NORMAL +0x000, // 0x129 = 297 - NO_OP +0x000, // 0x12a = 298 - NO_OP +0x000, // 0x12b = 299 - NO_OP +0x000, // 0x12c = 300 - NO_OP +0x0c9, // 0x12d = 301 - JUMP_IF_RX_BUFFER_FULL_TIMEOUT +0x138, // 0x12e = 302 - +0x0c0, // 0x12f = 303 - JUMP_IF_CLOSE_STATUS_EQUAL_ANY +0x09c, // 0x130 = 304 - +0x0bc, // 0x131 = 305 - JUMP_IF_BREAK_RECEIVED +0x13b, // 0x132 = 306 - +0x0be, // 0x133 = 307 - JUMP_IF_PHY_READY +0x129, // 0x134 = 308 - +0x01c, // 0x135 = 309 - SOFT_RESET +0x0ff, // 0x136 = 310 - JUMP +0x004, // 0x137 = 311 - +0x022, // 0x138 = 312 - SEND_CREDIT_BLOCK +0x0ff, // 0x139 = 313 - JUMP +0x129, // 0x13a = 314 - +0x007, // 0x13b = 315 - CLOSE_BREAK +0x000, // 0x13c = 316 - NO_OP +0x000, // 0x13d = 317 - NO_OP +0x000, // 0x13e = 318 - NO_OP +0x000, // 0x13f = 319 - NO_OP +0x0c0, // 0x140 = 320 - JUMP_IF_CLOSE_STATUS_EQUAL_ANY +0x09c, // 0x141 = 321 - +0x0be, // 0x142 = 322 - JUMP_IF_PHY_READY +0x13c, // 0x143 = 323 - +0x01c, // 0x144 = 324 - SOFT_RESET +0x0ff, // 0x145 = 325 - JUMP +0x004, // 0x146 = 326 - +0x005, // 0x147 = 327 - CLOSE_ACK_NAK_TIMEOUT +0x0ff, // 0x148 = 328 - JUMP +0x129, // 0x149 = 329 - +0x006, // 0x14a = 330 - CLOSE_CREDIT_TIMEOUT +0x0ff, // 0x14b = 331 - JUMP +0x129, // 0x14c = 332 - +0x0cc, // 0x14d = 333 - JUMP_IF_RX_BUFFER_FULL +0x09c, // 0x14e = 334 - +0x0b7, // 0x14f = 335 - JUMP_IF_FLAG_7_SET +0x154, // 0x150 = 336 - +0x011, // 0x151 = 337 - START_IT_NEXUS_LOSS_TIMER +0x00f, // 0x152 = 338 - PATHWAY_BLOCKED_CNT_RESET +0x00e, // 0x153 = 339 - START_ARB_WAIT_TIMER +0x0cb, // 0x154 = 340 - JUMP_IF_FREEZE_ACTIVE +0x193, // 0x155 = 341 - +0x001, // 0x156 = 342 - OPEN_REQUEST +0x080, // 0x157 = 343 - SET_FLAG +0x080, // 0x158 = 344 - +0x090, // 0x159 = 345 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_ACCEPT +0x17f, // 0x15a = 346 - +0x095, // 0x15b = 347 - JUMP_IF_OPEN_STATUS_EQUAL_RATE_NOT_SUPPORTED +0x184, // 0x15c = 348 - +0x099, // 0x15d = 349 - JUMP_IF_OPEN_STATUS_EQUAL_PROTOCOL_NOT_SUPPORTED +0x187, // 0x15e = 350 - +0x09b, // 0x15f = 351 - JUMP_IF_OPEN_STATUS_EQUAL_WRONG_DESTINATION +0x18a, // 0x160 = 352 - +0x094, // 0x161 = 353 - JUMP_IF_OPEN_STATUS_EQUAL_BREAK_RECEIVED +0x154, // 0x162 = 354 - +0x093, // 0x163 = 355 - JUMP_IF_OPEN_STATUS_EQUAL_BAD_DESTINATION +0x18d, // 0x164 = 356 - +0x09f, // 0x165 = 357 - JUMP_IF_IT_NEXUS_LOSS_TIMEOUT +0x190, // 0x166 = 358 - +0x09a, // 0x167 = 359 - JUMP_IF_OPEN_STATUS_EQUAL_STP_RESOURCE_BUSY +0x153, // 0x168 = 360 - +0x096, // 0x169 = 361 - JUMP_IF_OPEN_STATUS_EQUAL_NO_DESTINATION +0x154, // 0x16a = 362 - +0x097, // 0x16b = 363 - JUMP_IF_OPEN_STATUS_EQUAL_PATHWAY_BLOCKED +0x19a, // 0x16c = 364 - +0x098, // 0x16d = 365 - JUMP_IF_OPEN_STATUS_EQUAL_RETRY +0x153, // 0x16e = 366 - +0x092, // 0x16f = 367 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_TIMEOUT +0x154, // 0x170 = 368 - +0x0a4, // 0x171 = 369 - JUMP_IF_CONNECTION_ACTIVE_SET +0x179, // 0x172 = 370 - +0x0be, // 0x173 = 371 - JUMP_IF_PHY_READY +0x159, // 0x174 = 372 - +0x01b, // 0x175 = 373 - SET_OPEN_STATUS_PHY_NOT_RDY +0x01c, // 0x176 = 374 - SOFT_RESET +0x0ff, // 0x177 = 375 - JUMP +0x004, // 0x178 = 376 - +0x0a0, // 0x179 = 377 - JUMP_IF_CONNECTION_PROFILE_OPEN_EQUAL +0x17f, // 0x17a = 378 - +0x000, // 0x17b = 379 - NO_OP +0x000, // 0x17c = 380 - NO_OP +0x0ff, // 0x17d = 381 - JUMP +0x09c, // 0x17e = 382 - +0x013, // 0x17f = 383 - SET_OPEN_STATUS_NORMAL +0x081, // 0x180 = 384 - CLEAR_FLAG +0x080, // 0x181 = 385 - +0x0ff, // 0x182 = 386 - JUMP +0x042, // 0x183 = 387 - +0x017, // 0x184 = 388 - SET_OPEN_STATUS_BAD_RATE +0x0ff, // 0x185 = 389 - JUMP +0x194, // 0x186 = 390 - +0x018, // 0x187 = 391 - SET_OPEN_STATUS_BAD_PROTOCOL +0x0ff, // 0x188 = 392 - JUMP +0x194, // 0x189 = 393 - +0x01a, // 0x18a = 394 - SET_OPEN_STATUS_WRONG_DEST +0x0ff, // 0x18b = 395 - JUMP +0x194, // 0x18c = 396 - +0x015, // 0x18d = 397 - SET_OPEN_STATUS_BAD_DEST +0x0ff, // 0x18e = 398 - JUMP +0x194, // 0x18f = 399 - +0x014, // 0x190 = 400 - SET_OPEN_STATUS_IT_NEXUS_LOSS +0x0ff, // 0x191 = 401 - JUMP +0x194, // 0x192 = 402 - +0x024, // 0x193 = 403 - SET_OPEN_STATUS_FREEZE +0x000, // 0x194 = 404 - NO_OP +0x000, // 0x195 = 405 - NO_OP +0x081, // 0x196 = 406 - CLEAR_FLAG +0x080, // 0x197 = 407 - +0x0ff, // 0x198 = 408 - JUMP +0x09c, // 0x199 = 409 - +0x010, // 0x19a = 410 - PATHWAY_BLOCKED_CNT_INC +0x0ff, // 0x19b = 411 - JUMP +0x154, // 0x19c = 412 - +0x000, // 0x19d = 413 - NO_OP +0x000, // 0x19e = 414 - NO_OP +0x000, // 0x19f = 415 - NO_OP +0x000, // 0x1a0 = 416 - NO_OP +0x000, // 0x1a1 = 417 - NO_OP +0x000, // 0x1a2 = 418 - NO_OP +0x000, // 0x1a3 = 419 - NO_OP +0x000, // 0x1a4 = 420 - NO_OP +0x000, // 0x1a5 = 421 - NO_OP +0x000, // 0x1a6 = 422 - NO_OP +0x000, // 0x1a7 = 423 - NO_OP +0x000, // 0x1a8 = 424 - NO_OP +0x000, // 0x1a9 = 425 - NO_OP +0x000, // 0x1aa = 426 - NO_OP +0x000, // 0x1ab = 427 - NO_OP +0x000, // 0x1ac = 428 - NO_OP +0x000, // 0x1ad = 429 - NO_OP +0x000, // 0x1ae = 430 - NO_OP +0x000, // 0x1af = 431 - NO_OP +0x000, // 0x1b0 = 432 - NO_OP +0x000, // 0x1b1 = 433 - NO_OP +0x000, // 0x1b2 = 434 - NO_OP +0x000, // 0x1b3 = 435 - NO_OP +0x000, // 0x1b4 = 436 - NO_OP +0x000, // 0x1b5 = 437 - NO_OP +0x000, // 0x1b6 = 438 - NO_OP +0x000, // 0x1b7 = 439 - NO_OP +0x000, // 0x1b8 = 440 - NO_OP +0x000, // 0x1b9 = 441 - NO_OP +0x000, // 0x1ba = 442 - NO_OP +0x000, // 0x1bb = 443 - NO_OP +0x000, // 0x1bc = 444 - NO_OP +0x000, // 0x1bd = 445 - NO_OP +0x000, // 0x1be = 446 - NO_OP +0x000, // 0x1bf = 447 - NO_OP +0x000, // 0x1c0 = 448 - NO_OP +0x000, // 0x1c1 = 449 - NO_OP +0x000, // 0x1c2 = 450 - NO_OP +0x000, // 0x1c3 = 451 - NO_OP +0x000, // 0x1c4 = 452 - NO_OP +0x000, // 0x1c5 = 453 - NO_OP +0x000, // 0x1c6 = 454 - NO_OP +0x000, // 0x1c7 = 455 - NO_OP +0x000, // 0x1c8 = 456 - NO_OP +0x000, // 0x1c9 = 457 - NO_OP +0x000, // 0x1ca = 458 - NO_OP +0x000, // 0x1cb = 459 - NO_OP +0x000, // 0x1cc = 460 - NO_OP +0x000, // 0x1cd = 461 - NO_OP +0x000, // 0x1ce = 462 - NO_OP +0x000, // 0x1cf = 463 - NO_OP +0x000, // 0x1d0 = 464 - NO_OP +0x000, // 0x1d1 = 465 - NO_OP +0x000, // 0x1d2 = 466 - NO_OP +0x000, // 0x1d3 = 467 - NO_OP +0x000, // 0x1d4 = 468 - NO_OP +0x000, // 0x1d5 = 469 - NO_OP +0x000, // 0x1d6 = 470 - NO_OP +0x000, // 0x1d7 = 471 - NO_OP +0x000, // 0x1d8 = 472 - NO_OP +0x000, // 0x1d9 = 473 - NO_OP +0x000, // 0x1da = 474 - NO_OP +0x000, // 0x1db = 475 - NO_OP +0x000, // 0x1dc = 476 - NO_OP +0x000, // 0x1dd = 477 - NO_OP +0x000, // 0x1de = 478 - NO_OP +0x000, // 0x1df = 479 - NO_OP +0x000, // 0x1e0 = 480 - NO_OP +0x000, // 0x1e1 = 481 - NO_OP +0x000, // 0x1e2 = 482 - NO_OP +0x000, // 0x1e3 = 483 - NO_OP +0x000, // 0x1e4 = 484 - NO_OP +0x000, // 0x1e5 = 485 - NO_OP +0x000, // 0x1e6 = 486 - NO_OP +0x000, // 0x1e7 = 487 - NO_OP +0x000, // 0x1e8 = 488 - NO_OP +0x000, // 0x1e9 = 489 - NO_OP +0x000, // 0x1ea = 490 - NO_OP +0x000, // 0x1eb = 491 - NO_OP +0x000, // 0x1ec = 492 - NO_OP +0x000, // 0x1ed = 493 - NO_OP +0x000, // 0x1ee = 494 - NO_OP +0x000, // 0x1ef = 495 - NO_OP +0x000, // 0x1f0 = 496 - NO_OP +0x000, // 0x1f1 = 497 - NO_OP +0x000, // 0x1f2 = 498 - NO_OP +0x000, // 0x1f3 = 499 - NO_OP +0x000, // 0x1f4 = 500 - NO_OP +0x000, // 0x1f5 = 501 - NO_OP +0x000, // 0x1f6 = 502 - NO_OP +0x000, // 0x1f7 = 503 - NO_OP +0x000, // 0x1f8 = 504 - NO_OP +0x000, // 0x1f9 = 505 - NO_OP +0x000, // 0x1fa = 506 - NO_OP +0x000, // 0x1fb = 507 - NO_OP +0x000, // 0x1fc = 508 - NO_OP +0x000, // 0x1fd = 509 - NO_OP +0x000, // 0x1fe = 510 - NO_OP +0x000, // 0x1ff = 511 - NO_OP +}; + +/* for A1407_10, A1410_15, A1412_19, A1415_19*/ +bit32 wcsImage[] = +{ +0x00d, // 00000 = 0 - PHY_RESET_START +0x00d, // 0x001 = 1 - PHY_RESET_START +0x0be, // 0x002 = 2 - JUMP_IF_PHY_READY +0x002, // 0x003 = 3 - +0x0be, // 0x004 = 4 - JUMP_IF_PHY_READY +0x00e, // 0x005 = 5 - +0x0ae, // 0x006 = 6 - JUMP_IF_HARD_RESET_PRIMITIVE +0x024, // 0x007 = 7 - +0x0af, // 0x008 = 8 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x017, // 0x009 = 9 - +0x0ce, // 0x00a = 10 - JUMP_IF_IDENTIFY_FRAME_TIMEOUT +0x000, // 0x00b = 11 - +0x0ff, // 0x00c = 12 - JUMP +0x004, // 0x00d = 13 - +0x00c, // 0x00e = 14 - SEND_ID_FRAME +0x0ae, // 0x00f = 15 - JUMP_IF_HARD_RESET_PRIMITIVE +0x024, // 0x010 = 16 - +0x0af, // 0x011 = 17 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x01c, // 0x012 = 18 - +0x0ce, // 0x013 = 19 - JUMP_IF_IDENTIFY_FRAME_TIMEOUT +0x000, // 0x014 = 20 - +0x0ff, // 0x015 = 21 - JUMP +0x00f, // 0x016 = 22 - +0x0be, // 0x017 = 23 - JUMP_IF_PHY_READY +0x01b, // 0x018 = 24 - +0x0ff, // 0x019 = 25 - JUMP +0x017, // 0x01a = 26 - +0x00c, // 0x01b = 27 - SEND_ID_FRAME +0x000, // 0x01c = 28 - NO_OP +0x000, // 0x01d = 29 - NO_OP +0x000, // 0x01e = 30 - NO_OP +0x000, // 0x01f = 31 - NO_OP +0x000, // 0x020 = 32 - NO_OP +0x000, // 0x021 = 33 - NO_OP +0x0ff, // 0x022 = 34 - JUMP +0x09c, // 0x023 = 35 - +0x01c, // 0x024 = 36 - SOFT_RESET +0x00d, // 0x025 = 37 - PHY_RESET_START +0x00d, // 0x026 = 38 - PHY_RESET_START +0x0be, // 0x027 = 39 - JUMP_IF_PHY_READY +0x027, // 0x028 = 40 - +0x0be, // 0x029 = 41 - JUMP_IF_PHY_READY +0x02f, // 0x02a = 42 - +0x0af, // 0x02b = 43 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x036, // 0x02c = 44 - +0x0ff, // 0x02d = 45 - JUMP +0x029, // 0x02e = 46 - +0x00c, // 0x02f = 47 - SEND_ID_FRAME +0x0af, // 0x030 = 48 - JUMP_IF_IDENTIFY_FRAME_RECEIVED +0x039, // 0x031 = 49 - +0x0ce, // 0x032 = 50 - JUMP_IF_IDENTIFY_FRAME_TIMEOUT +0x024, // 0x033 = 51 - +0x0ff, // 0x034 = 52 - JUMP +0x030, // 0x035 = 53 - +0x00c, // 0x036 = 54 - SEND_ID_FRAME +0x0ff, // 0x037 = 55 - JUMP +0x039, // 0x038 = 56 - +0x000, // 0x039 = 57 - NO_OP +0x0cb, // 0x03a = 58 - JUMP_IF_FREEZE_ACTIVE +0x03e, // 0x03b = 59 - +0x0ff, // 0x03c = 60 - JUMP +0x03a, // 0x03d = 61 - +0x0cb, // 0x03e = 62 - JUMP_IF_FREEZE_ACTIVE +0x03e, // 0x03f = 63 - +0x0ff, // 0x040 = 64 - JUMP +0x09c, // 0x041 = 65 - +0x000, // 0x042 = 66 - NO_OP +0x0c9, // 0x043 = 67 - JUMP_IF_RX_BUFFER_FULL_TIMEOUT +0x073, // 0x044 = 68 - +0x0a5, // 0x045 = 69 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_GOOD +0x05c, // 0x046 = 70 - +0x0a6, // 0x047 = 71 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_NAK +0x063, // 0x048 = 72 - +0x0a7, // 0x049 = 73 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_ACK_NAK_TIMEOUT +0x066, // 0x04a = 74 - +0x0a8, // 0x04b = 75 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_BREAK +0x070, // 0x04c = 76 - +0x0aa, // 0x04d = 77 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_CREDIT_TIMEOUT +0x06b, // 0x04e = 78 - +0x0c5, // 0x04f = 79 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_SMP_ERR +0x070, // 0x050 = 80 - +0x0ac, // 0x051 = 81 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_MAX_BURST_SIZE +0x063, // 0x052 = 82 - +0x0d9, // 0x053 = 83 - JUMP_IF_TRANSMISSION_STATUS_EQUAL_FREEZE_TIMEOUT +0x070, // 0x054 = 84 - +0x0ca, // 0x055 = 85 - JUMP_IF_CLOSE_REQ +0x0f0, // 0x056 = 86 - +0x0be, // 0x057 = 87 - JUMP_IF_PHY_READY +0x043, // 0x058 = 88 - +0x01c, // 0x059 = 89 - SOFT_RESET +0x0ff, // 0x05a = 90 - JUMP +0x004, // 0x05b = 91 - +0x01d, // 0x05c = 92 - ADVANCE +0x0bc, // 0x05d = 93 - JUMP_IF_BREAK_RECEIVED +0x13b, // 0x05e = 94 - +0x0c3, // 0x05f = 95 - JUMP_IF_SMP_PROTOCOL +0x128, // 0x060 = 96 - +0x0ff, // 0x061 = 97 - JUMP +0x076, // 0x062 = 98 - +0x01d, // 0x063 = 99 - ADVANCE +0x0ff, // 0x064 = 100 - JUMP +0x076, // 0x065 = 101 - +0x01d, // 0x066 = 102 - ADVANCE +0x0bc, // 0x067 = 103 - JUMP_IF_BREAK_RECEIVED +0x13b, // 0x068 = 104 - +0x0ff, // 0x069 = 105 - JUMP +0x147, // 0x06a = 106 - +0x01d, // 0x06b = 107 - ADVANCE +0x0bc, // 0x06c = 108 - JUMP_IF_BREAK_RECEIVED +0x13b, // 0x06d = 109 - +0x0ff, // 0x06e = 110 - JUMP +0x14a, // 0x06f = 111 - +0x01d, // 0x070 = 112 - ADVANCE +0x0ff, // 0x071 = 113 - JUMP +0x13b, // 0x072 = 114 - +0x022, // 0x073 = 115 - SEND_CREDIT_BLOCK +0x0ff, // 0x074 = 116 - JUMP +0x045, // 0x075 = 117 - +0x083, // 0x076 = 118 - TIMER_START +0x004, // 0x077 = 119 - +0x0c8, // 0x078 = 120 - JUMP_IF_HIP_REQ +0x082, // 0x079 = 121 - +0x0c6, // 0x07a = 122 - JUMP_IF_SFO_REQ +0x08a, // 0x07b = 123 - +0x0c7, // 0x07c = 124 - JUMP_IF_DOC_REQ +0x094, // 0x07d = 125 - +0x0b8, // 0x07e = 126 - JUMP_IF_TIMER_EXPIRED +0x09c, // 0x07f = 127 - +0x0ff, // 0x080 = 128 - JUMP +0x078, // 0x081 = 129 - +0x028, // 0x082 = 130 - CHECK_HIP +0x000, // 0x083 = 131 - NO_OP +0x000, // 0x084 = 132 - NO_OP +0x000, // 0x085 = 133 - NO_OP +0x0d8, // 0x086 = 134 - JUMP_IF_NXT_CONN_ACTIVE_PROF_EQ +0x0cf, // 0x087 = 135 - +0x0ff, // 0x088 = 136 - JUMP +0x07e, // 0x089 = 137 - +0x029, // 0x08a = 138 - CHECK_SFO +0x000, // 0x08b = 139 - NO_OP +0x000, // 0x08c = 140 - NO_OP +0x000, // 0x08d = 141 - NO_OP +0x0d8, // 0x08e = 142 - JUMP_IF_NXT_CONN_ACTIVE_PROF_EQ +0x0d4, // 0x08f = 143 - +0x0c7, // 0x090 = 144 - JUMP_IF_DOC_REQ +0x094, // 0x091 = 145 - +0x0ff, // 0x092 = 146 - JUMP +0x07e, // 0x093 = 147 - +0x02a, // 0x094 = 148 - CHECK_DOC +0x000, // 0x095 = 149 - NO_OP +0x000, // 0x096 = 150 - NO_OP +0x000, // 0x097 = 151 - NO_OP +0x0d8, // 0x098 = 152 - JUMP_IF_NXT_CONN_ACTIVE_PROF_EQ +0x0d9, // 0x099 = 153 - +0x0ff, // 0x09a = 154 - JUMP +0x07e, // 0x09b = 155 - +0x0bc, // 0x09c = 156 - JUMP_IF_BREAK_RECEIVED +0x13b, // 0x09d = 157 - +0x0be, // 0x09e = 158 - JUMP_IF_PHY_READY +0x0a3, // 0x09f = 159 - +0x01c, // 0x0a0 = 160 - SOFT_RESET +0x0ff, // 0x0a1 = 161 - JUMP +0x004, // 0x0a2 = 162 - +0x0c8, // 0x0a3 = 163 - JUMP_IF_HIP_REQ +0x0b5, // 0x0a4 = 164 - +0x0c6, // 0x0a5 = 165 - JUMP_IF_SFO_REQ +0x0bd, // 0x0a6 = 166 - +0x0c7, // 0x0a7 = 167 - JUMP_IF_DOC_REQ +0x0c7, // 0x0a8 = 168 - +0x0a3, // 0x0a9 = 169 - JUMP_IF_CONNECTION_OPEN_SLAVE_FLAG_SET +0x107, // 0x0aa = 170 - +0x0a2, // 0x0ab = 171 - JUMP_IF_CONNECTION_OPEN_MASTER_FLAG_SET +0x0f0, // 0x0ac = 172 - +0x0c8, // 0x0ad = 173 - JUMP_IF_HIP_REQ +0x0cf, // 0x0ae = 174 - +0x0c6, // 0x0af = 175 - JUMP_IF_SFO_REQ +0x0d4, // 0x0b0 = 176 - +0x0c7, // 0x0b1 = 177 - JUMP_IF_DOC_REQ +0x0d9, // 0x0b2 = 178 - +0x0ff, // 0x0b3 = 179 - JUMP +0x09c, // 0x0b4 = 180 - +0x028, // 0x0b5 = 181 - CHECK_HIP +0x000, // 0x0b6 = 182 - NO_OP +0x000, // 0x0b7 = 183 - NO_OP +0x000, // 0x0b8 = 184 - NO_OP +0x0d8, // 0x0b9 = 185 - JUMP_IF_NXT_CONN_ACTIVE_PROF_EQ +0x0cf, // 0x0ba = 186 - +0x0ff, // 0x0bb = 187 - JUMP +0x0a9, // 0x0bc = 188 - +0x029, // 0x0bd = 189 - CHECK_SFO +0x000, // 0x0be = 190 - NO_OP +0x000, // 0x0bf = 191 - NO_OP +0x000, // 0x0c0 = 192 - NO_OP +0x0d8, // 0x0c1 = 193 - JUMP_IF_NXT_CONN_ACTIVE_PROF_EQ +0x0d4, // 0x0c2 = 194 - +0x0c7, // 0x0c3 = 195 - JUMP_IF_DOC_REQ +0x0c7, // 0x0c4 = 196 - +0x0ff, // 0x0c5 = 197 - JUMP +0x0a9, // 0x0c6 = 198 - +0x02a, // 0x0c7 = 199 - CHECK_DOC +0x000, // 0x0c8 = 200 - NO_OP +0x000, // 0x0c9 = 201 - NO_OP +0x000, // 0x0ca = 202 - NO_OP +0x0d8, // 0x0cb = 203 - JUMP_IF_NXT_CONN_ACTIVE_PROF_EQ +0x0d9, // 0x0cc = 204 - +0x0ff, // 0x0cd = 205 - JUMP +0x0a9, // 0x0ce = 206 - +0x020, // 0x0cf = 207 - SELECT_HIP +0x000, // 0x0d0 = 208 - NO_OP +0x000, // 0x0d1 = 209 - NO_OP +0x0ff, // 0x0d2 = 210 - JUMP +0x0dc, // 0x0d3 = 211 - +0x01e, // 0x0d4 = 212 - SELECT_SFO +0x000, // 0x0d5 = 213 - NO_OP +0x000, // 0x0d6 = 214 - NO_OP +0x0ff, // 0x0d7 = 215 - JUMP +0x0dc, // 0x0d8 = 216 - +0x01f, // 0x0d9 = 217 - SELECT_DOC +0x000, // 0x0da = 218 - NO_OP +0x000, // 0x0db = 219 - NO_OP +0x0a4, // 0x0dc = 220 - JUMP_IF_CONNECTION_ACTIVE_SET +0x0e0, // 0x0dd = 221 - +0x0ff, // 0x0de = 222 - JUMP +0x14d, // 0x0df = 223 - +0x0a0, // 0x0e0 = 224 - JUMP_IF_CONNECTION_PROFILE_OPEN_EQUAL +0x0e6, // 0x0e1 = 225 - +0x0a3, // 0x0e2 = 226 - JUMP_IF_CONNECTION_OPEN_SLAVE_FLAG_SET +0x107, // 0x0e3 = 227 - +0x0ff, // 0x0e4 = 228 - JUMP +0x0f0, // 0x0e5 = 229 - +0x0cb, // 0x0e6 = 230 - JUMP_IF_FREEZE_ACTIVE +0x0eb, // 0x0e7 = 231 - +0x013, // 0x0e8 = 232 - SET_OPEN_STATUS_NORMAL +0x0ff, // 0x0e9 = 233 - JUMP +0x042, // 0x0ea = 234 - +0x024, // 0x0eb = 235 - SET_OPEN_STATUS_FREEZE +0x000, // 0x0ec = 236 - NO_OP +0x000, // 0x0ed = 237 - NO_OP +0x0ff, // 0x0ee = 238 - JUMP +0x09c, // 0x0ef = 239 - +0x0d2, // 0x0f0 = 240 - JUMP_IF_STP_CONNECTION_ACTIVE +0x0f4, // 0x0f1 = 241 - +0x0ff, // 0x0f2 = 242 - JUMP +0x128, // 0x0f3 = 243 - +0x0d5, // 0x0f4 = 244 - JUMP_IF_CLOSE_RECEIVED +0x128, // 0x0f5 = 245 - +0x0d6, // 0x0f6 = 246 - JUMP_IF_SYNC_RECEIVED +0x0fa, // 0x0f7 = 247 - +0x0ff, // 0x0f8 = 248 - JUMP +0x09c, // 0x0f9 = 249 - +0x027, // 0x0fa = 250 - SEND_STP_CLOSE_REQ +0x000, // 0x0fb = 251 - NO_OP +0x000, // 0x0fc = 252 - NO_OP +0x000, // 0x0fd = 253 - NO_OP +0x000, // 0x0fe = 254 - NO_OP +0x0d5, // 0x0ff = 255 - JUMP_IF_CLOSE_RECEIVED +0x128, // 0x100 = 256 - +0x0bc, // 0x101 = 257 - JUMP_IF_BREAK_RECEIVED +0x13b, // 0x102 = 258 - +0x0d7, // 0x103 = 259 - JUMP_IF_STP_CLOSE_ACK +0x128, // 0x104 = 260 - +0x0ff, // 0x105 = 261 - JUMP +0x0fb, // 0x106 = 262 - +0x0c3, // 0x107 = 263 - JUMP_IF_SMP_PROTOCOL +0x10f, // 0x108 = 264 - +0x0d2, // 0x109 = 265 - JUMP_IF_STP_CONNECTION_ACTIVE +0x113, // 0x10a = 266 - +0x0d1, // 0x10b = 267 - JUMP_IF_IDLE_TIMER_TIMEOUT +0x119, // 0x10c = 268 - +0x0ff, // 0x10d = 269 - JUMP +0x09c, // 0x10e = 270 - +0x0c4, // 0x10f = 271 - JUMP_IF_SMP_FRAME_ERR_RECEIVED +0x13b, // 0x110 = 272 - +0x0ff, // 0x111 = 273 - JUMP +0x0ad, // 0x112 = 274 - +0x0d5, // 0x113 = 275 - JUMP_IF_CLOSE_RECEIVED +0x119, // 0x114 = 276 - +0x0d6, // 0x115 = 277 - JUMP_IF_SYNC_RECEIVED +0x11b, // 0x116 = 278 - +0x0ff, // 0x117 = 279 - JUMP +0x113, // 0x118 = 280 - +0x0ff, // 0x119 = 281 - JUMP +0x128, // 0x11a = 282 - +0x027, // 0x11b = 283 - SEND_STP_CLOSE_REQ +0x000, // 0x11c = 284 - NO_OP +0x000, // 0x11d = 285 - NO_OP +0x000, // 0x11e = 286 - NO_OP +0x000, // 0x11f = 287 - NO_OP +0x0d5, // 0x120 = 288 - JUMP_IF_CLOSE_RECEIVED +0x128, // 0x121 = 289 - +0x0bc, // 0x122 = 290 - JUMP_IF_BREAK_RECEIVED +0x13b, // 0x123 = 291 - +0x0d7, // 0x124 = 292 - JUMP_IF_STP_CLOSE_ACK +0x128, // 0x125 = 293 - +0x0ff, // 0x126 = 294 - JUMP +0x11c, // 0x127 = 295 - +0x004, // 0x128 = 296 - CLOSE_NORMAL +0x000, // 0x129 = 297 - NO_OP +0x000, // 0x12a = 298 - NO_OP +0x000, // 0x12b = 299 - NO_OP +0x000, // 0x12c = 300 - NO_OP +0x0c9, // 0x12d = 301 - JUMP_IF_RX_BUFFER_FULL_TIMEOUT +0x138, // 0x12e = 302 - +0x0c0, // 0x12f = 303 - JUMP_IF_CLOSE_STATUS_EQUAL_ANY +0x09c, // 0x130 = 304 - +0x0bc, // 0x131 = 305 - JUMP_IF_BREAK_RECEIVED +0x13b, // 0x132 = 306 - +0x0be, // 0x133 = 307 - JUMP_IF_PHY_READY +0x129, // 0x134 = 308 - +0x01c, // 0x135 = 309 - SOFT_RESET +0x0ff, // 0x136 = 310 - JUMP +0x004, // 0x137 = 311 - +0x022, // 0x138 = 312 - SEND_CREDIT_BLOCK +0x0ff, // 0x139 = 313 - JUMP +0x129, // 0x13a = 314 - +0x007, // 0x13b = 315 - CLOSE_BREAK +0x000, // 0x13c = 316 - NO_OP +0x000, // 0x13d = 317 - NO_OP +0x000, // 0x13e = 318 - NO_OP +0x000, // 0x13f = 319 - NO_OP +0x0c0, // 0x140 = 320 - JUMP_IF_CLOSE_STATUS_EQUAL_ANY +0x09c, // 0x141 = 321 - +0x0be, // 0x142 = 322 - JUMP_IF_PHY_READY +0x13c, // 0x143 = 323 - +0x01c, // 0x144 = 324 - SOFT_RESET +0x0ff, // 0x145 = 325 - JUMP +0x004, // 0x146 = 326 - +0x005, // 0x147 = 327 - CLOSE_ACK_NAK_TIMEOUT +0x0ff, // 0x148 = 328 - JUMP +0x129, // 0x149 = 329 - +0x006, // 0x14a = 330 - CLOSE_CREDIT_TIMEOUT +0x0ff, // 0x14b = 331 - JUMP +0x129, // 0x14c = 332 - +0x0da, // 0x14d = 333 - JUMP_IF_SMP_TARGET +0x189, // 0x14e = 334 - +0x0cc, // 0x14f = 335 - JUMP_IF_RX_BUFFER_FULL +0x09c, // 0x150 = 336 - +0x0b7, // 0x151 = 337 - JUMP_IF_FLAG_7_SET +0x156, // 0x152 = 338 - +0x011, // 0x153 = 339 - START_IT_NEXUS_LOSS_TIMER +0x00f, // 0x154 = 340 - PATHWAY_BLOCKED_CNT_RESET +0x00e, // 0x155 = 341 - START_ARB_WAIT_TIMER +0x0cb, // 0x156 = 342 - JUMP_IF_FREEZE_ACTIVE +0x195, // 0x157 = 343 - +0x001, // 0x158 = 344 - OPEN_REQUEST +0x080, // 0x159 = 345 - SET_FLAG +0x080, // 0x15a = 346 - +0x090, // 0x15b = 347 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_ACCEPT +0x181, // 0x15c = 348 - +0x095, // 0x15d = 349 - JUMP_IF_OPEN_STATUS_EQUAL_RATE_NOT_SUPPORTED +0x186, // 0x15e = 350 - +0x099, // 0x15f = 351 - JUMP_IF_OPEN_STATUS_EQUAL_PROTOCOL_NOT_SUPPORTED +0x189, // 0x160 = 352 - +0x09b, // 0x161 = 353 - JUMP_IF_OPEN_STATUS_EQUAL_WRONG_DESTINATION +0x18c, // 0x162 = 354 - +0x094, // 0x163 = 355 - JUMP_IF_OPEN_STATUS_EQUAL_BREAK_RECEIVED +0x156, // 0x164 = 356 - +0x093, // 0x165 = 357 - JUMP_IF_OPEN_STATUS_EQUAL_BAD_DESTINATION +0x18f, // 0x166 = 358 - +0x09f, // 0x167 = 359 - JUMP_IF_IT_NEXUS_LOSS_TIMEOUT +0x192, // 0x168 = 360 - +0x09a, // 0x169 = 361 - JUMP_IF_OPEN_STATUS_EQUAL_STP_RESOURCE_BUSY +0x155, // 0x16a = 362 - +0x096, // 0x16b = 363 - JUMP_IF_OPEN_STATUS_EQUAL_NO_DESTINATION +0x156, // 0x16c = 364 - +0x097, // 0x16d = 365 - JUMP_IF_OPEN_STATUS_EQUAL_PATHWAY_BLOCKED +0x19c, // 0x16e = 366 - +0x098, // 0x16f = 367 - JUMP_IF_OPEN_STATUS_EQUAL_RETRY +0x155, // 0x170 = 368 - +0x092, // 0x171 = 369 - JUMP_IF_OPEN_STATUS_EQUAL_OPEN_TIMEOUT +0x156, // 0x172 = 370 - +0x0a4, // 0x173 = 371 - JUMP_IF_CONNECTION_ACTIVE_SET +0x17b, // 0x174 = 372 - +0x0be, // 0x175 = 373 - JUMP_IF_PHY_READY +0x15b, // 0x176 = 374 - +0x01b, // 0x177 = 375 - SET_OPEN_STATUS_PHY_NOT_RDY +0x01c, // 0x178 = 376 - SOFT_RESET +0x0ff, // 0x179 = 377 - JUMP +0x004, // 0x17a = 378 - +0x0a0, // 0x17b = 379 - JUMP_IF_CONNECTION_PROFILE_OPEN_EQUAL +0x181, // 0x17c = 380 - +0x000, // 0x17d = 381 - NO_OP +0x000, // 0x17e = 382 - NO_OP +0x0ff, // 0x17f = 383 - JUMP +0x09c, // 0x180 = 384 - +0x013, // 0x181 = 385 - SET_OPEN_STATUS_NORMAL +0x081, // 0x182 = 386 - CLEAR_FLAG +0x080, // 0x183 = 387 - +0x0ff, // 0x184 = 388 - JUMP +0x042, // 0x185 = 389 - +0x017, // 0x186 = 390 - SET_OPEN_STATUS_BAD_RATE +0x0ff, // 0x187 = 391 - JUMP +0x196, // 0x188 = 392 - +0x018, // 0x189 = 393 - SET_OPEN_STATUS_BAD_PROTOCOL +0x0ff, // 0x18a = 394 - JUMP +0x196, // 0x18b = 395 - +0x01a, // 0x18c = 396 - SET_OPEN_STATUS_WRONG_DEST +0x0ff, // 0x18d = 397 - JUMP +0x196, // 0x18e = 398 - +0x015, // 0x18f = 399 - SET_OPEN_STATUS_BAD_DEST +0x0ff, // 0x190 = 400 - JUMP +0x196, // 0x191 = 401 - +0x014, // 0x192 = 402 - SET_OPEN_STATUS_IT_NEXUS_LOSS +0x0ff, // 0x193 = 403 - JUMP +0x196, // 0x194 = 404 - +0x024, // 0x195 = 405 - SET_OPEN_STATUS_FREEZE +0x000, // 0x196 = 406 - NO_OP +0x000, // 0x197 = 407 - NO_OP +0x081, // 0x198 = 408 - CLEAR_FLAG +0x080, // 0x199 = 409 - +0x0ff, // 0x19a = 410 - JUMP +0x09c, // 0x19b = 411 - +0x010, // 0x19c = 412 - PATHWAY_BLOCKED_CNT_INC +0x0ff, // 0x19d = 413 - JUMP +0x156, // 0x19e = 414 - +0x000, // 0x19f = 415 - NO_OP +0x000, // 0x1a0 = 416 - NO_OP +0x000, // 0x1a1 = 417 - NO_OP +0x000, // 0x1a2 = 418 - NO_OP +0x000, // 0x1a3 = 419 - NO_OP +0x000, // 0x1a4 = 420 - NO_OP +0x000, // 0x1a5 = 421 - NO_OP +0x000, // 0x1a6 = 422 - NO_OP +0x000, // 0x1a7 = 423 - NO_OP +0x000, // 0x1a8 = 424 - NO_OP +0x000, // 0x1a9 = 425 - NO_OP +0x000, // 0x1aa = 426 - NO_OP +0x000, // 0x1ab = 427 - NO_OP +0x000, // 0x1ac = 428 - NO_OP +0x000, // 0x1ad = 429 - NO_OP +0x000, // 0x1ae = 430 - NO_OP +0x000, // 0x1af = 431 - NO_OP +0x000, // 0x1b0 = 432 - NO_OP +0x000, // 0x1b1 = 433 - NO_OP +0x000, // 0x1b2 = 434 - NO_OP +0x000, // 0x1b3 = 435 - NO_OP +0x000, // 0x1b4 = 436 - NO_OP +0x000, // 0x1b5 = 437 - NO_OP +0x000, // 0x1b6 = 438 - NO_OP +0x000, // 0x1b7 = 439 - NO_OP +0x000, // 0x1b8 = 440 - NO_OP +0x000, // 0x1b9 = 441 - NO_OP +0x000, // 0x1ba = 442 - NO_OP +0x000, // 0x1bb = 443 - NO_OP +0x000, // 0x1bc = 444 - NO_OP +0x000, // 0x1bd = 445 - NO_OP +0x000, // 0x1be = 446 - NO_OP +0x000, // 0x1bf = 447 - NO_OP +0x000, // 0x1c0 = 448 - NO_OP +0x000, // 0x1c1 = 449 - NO_OP +0x000, // 0x1c2 = 450 - NO_OP +0x000, // 0x1c3 = 451 - NO_OP +0x000, // 0x1c4 = 452 - NO_OP +0x000, // 0x1c5 = 453 - NO_OP +0x000, // 0x1c6 = 454 - NO_OP +0x000, // 0x1c7 = 455 - NO_OP +0x000, // 0x1c8 = 456 - NO_OP +0x000, // 0x1c9 = 457 - NO_OP +0x000, // 0x1ca = 458 - NO_OP +0x000, // 0x1cb = 459 - NO_OP +0x000, // 0x1cc = 460 - NO_OP +0x000, // 0x1cd = 461 - NO_OP +0x000, // 0x1ce = 462 - NO_OP +0x000, // 0x1cf = 463 - NO_OP +0x000, // 0x1d0 = 464 - NO_OP +0x000, // 0x1d1 = 465 - NO_OP +0x000, // 0x1d2 = 466 - NO_OP +0x000, // 0x1d3 = 467 - NO_OP +0x000, // 0x1d4 = 468 - NO_OP +0x000, // 0x1d5 = 469 - NO_OP +0x000, // 0x1d6 = 470 - NO_OP +0x000, // 0x1d7 = 471 - NO_OP +0x000, // 0x1d8 = 472 - NO_OP +0x000, // 0x1d9 = 473 - NO_OP +0x000, // 0x1da = 474 - NO_OP +0x000, // 0x1db = 475 - NO_OP +0x000, // 0x1dc = 476 - NO_OP +0x000, // 0x1dd = 477 - NO_OP +0x000, // 0x1de = 478 - NO_OP +0x000, // 0x1df = 479 - NO_OP +0x000, // 0x1e0 = 480 - NO_OP +0x000, // 0x1e1 = 481 - NO_OP +0x000, // 0x1e2 = 482 - NO_OP +0x000, // 0x1e3 = 483 - NO_OP +0x000, // 0x1e4 = 484 - NO_OP +0x000, // 0x1e5 = 485 - NO_OP +0x000, // 0x1e6 = 486 - NO_OP +0x000, // 0x1e7 = 487 - NO_OP +0x000, // 0x1e8 = 488 - NO_OP +0x000, // 0x1e9 = 489 - NO_OP +0x000, // 0x1ea = 490 - NO_OP +0x000, // 0x1eb = 491 - NO_OP +0x000, // 0x1ec = 492 - NO_OP +0x000, // 0x1ed = 493 - NO_OP +0x000, // 0x1ee = 494 - NO_OP +0x000, // 0x1ef = 495 - NO_OP +0x000, // 0x1f0 = 496 - NO_OP +0x000, // 0x1f1 = 497 - NO_OP +0x000, // 0x1f2 = 498 - NO_OP +0x000, // 0x1f3 = 499 - NO_OP +0x000, // 0x1f4 = 500 - NO_OP +0x000, // 0x1f5 = 501 - NO_OP +0x000, // 0x1f6 = 502 - NO_OP +0x000, // 0x1f7 = 503 - NO_OP +0x000, // 0x1f8 = 504 - NO_OP +0x000, // 0x1f9 = 505 - NO_OP +0x000, // 0x1fa = 506 - NO_OP +0x000, // 0x1fb = 507 - NO_OP +0x000, // 0x1fc = 508 - NO_OP +0x000, // 0x1fd = 509 - NO_OP +0x000, // 0x1fe = 510 - NO_OP +0x000, // 0x1ff = 511 - NO_OP +}; diff --git a/sys/dev/pms/RefTisa/tisa/sassata/sas/common/tdtypes.h b/sys/dev/pms/RefTisa/tisa/sassata/sas/common/tdtypes.h new file mode 100644 index 000000000000..ce93e4a63f7e --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/sas/common/tdtypes.h @@ -0,0 +1,737 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/*******************************************************************************/ +/** \file + * + * The file defines data structures for SAS/SATA TD layer + * + */ +#ifndef __TDTYPES_H__ +#define __TDTYPES_H__ + +#include +#include +#include + +#include +#include +#include + +#ifdef FDS_SM +#include +#include +#endif + +#ifdef FDS_DM +#include +#endif + +#include +#include +#include + + +/* function definitions */ +typedef void (*tdssSSPReqReceived_t) ( + agsaRoot_t *, + agsaDevHandle_t *, + agsaFrameHandle_t, + bit32, + bit32, + bit32 + ); +typedef void (*tdssSMPReqReceived_t) ( + agsaRoot_t *, + agsaDevHandle_t *, + agsaSMPFrameHeader_t *, + agsaFrameHandle_t, + bit32, + bit32 + ); + +typedef bit32 (*tdssGetSGLChunk_t) (agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agChunkOffset, + bit32 *agChunkUpper32, + bit32 *agChunkLower32, + bit32 *agChunkLen); +/* for SSP only */ +typedef void (*tdssIOCompleted_t) (agsaRoot_t *, + agsaIORequest_t *, + bit32, + bit32, + agsaFrameHandle_t, + bit32); +/* for SMP only */ +typedef void (*tdssSMPCompleted_t) ( + agsaRoot_t *, + agsaIORequest_t *, + bit32 , + bit32 , + agsaFrameHandle_t + ); + + +/** \brief data structure for callback function jumptableESLG page + * + * This data structure defines callback fucntions for SSP, SMP and SATA + * This is used for jump table used for instance specific function callback jump + * + */ +typedef struct tdsaJumpTable_s { + /**< function that called to process received SSP frame */ + tdssSSPReqReceived_t pSSPReqReceived; + /**< function that called to process received SSP frame */ + tdssSMPReqReceived_t pSMPReqReceived; + /**< SSP IO completion callback function eg) ossaSSPcompleted() */ + tdssIOCompleted_t pSSPIOCompleted; + /**< SMP IO completion callback function eg) ossaSMPcompleted() */ + tdssSMPCompleted_t pSMPCompleted; + /* callback function for LL getSGL. Simple place holder for now */ + tdssGetSGLChunk_t pGetSGLChunk; +} tdsaJumpTable_t; + +/* timer functions ; both I and T */ +typedef void (*tdsaTimerCBFunc_t)(tiRoot_t *tiRoot, void *timerData1, void *timerData2, void *timerData3); + +/** \brief data structure for timer request + * Timer requests are enqueued and dequeued using tdList_t + * and have a callback function + */ +typedef struct tdsaTimerRequest_s { + /* the number of ticks */ + bit32 timeout; + void *timerData1; + void *timerData2; + void *timerData3; + tdsaTimerCBFunc_t timerCBFunc; + tdList_t timerLink; + bit32 timerRunning; +} tdsaTimerRequest_t; + + +/** \brief data structure for IO request data + * used at target only in ttdtxchg_t structure + * just a place holder for now + */ +typedef struct tdssIORequestData_s { + /* jump table has to be the first */ + tdsaJumpTable_t *pJumpTable; /* this is just a pointer */ +} tdssIORequestData_t; + + + +/** \brief data structure OS root from the view of lower layer. + * TD Layer interrupt/non-interrupt context support structure for agsaRoot_t. + * The osData part of agsaRoot points to this tdsaRootOsData_t structure. + * In other words, agsaRoot_t->osData points to this structure and used for + * both SAS and SATA + */ +typedef struct tdsaRootOsData_s { + tiRoot_t *tiRoot; /**< Pointer back to tiRoot */ + void *tdsaAllShared; /**< Pointer to tdsaContext_t */ + void *itdsaIni; /**< Pointer to SAS/SATA initiator */ + void *ttdsaTgt; /**< Pointer to SAS/SATA target */ + /* for sata */ + void *tdstHost; /**< Pointer to SATA Host */ + void *tdstDevice; /**< Pointer to SATA Device */ + agBOOLEAN IntContext; /**< Interrupt context */ +} tdsaRootOsData_t; + +/** \brief data structure for port/phy related flags + * Some fields are just place holders and not used yet + */ +typedef struct tdssPortFlags_s { + /**< port started flag */ + agBOOLEAN portStarted; + + /**< port initialized flag */ + agBOOLEAN portInitialized; + + agBOOLEAN portReadyForDiscoverySent; + + /**< port stopped by oslayer */ + agBOOLEAN portStoppedByOSLayer; + + /**< fail portinit/start */ + agBOOLEAN failPortInit; + + agBOOLEAN pseudoPortInitDone; + agBOOLEAN pseudoPortStartDone; +} tdssPortFlags_t; + +/** \brief data structure for both SAS/SATA related flags + * Some fields are just place holders and not used yet + * + */ +typedef struct tdsaComMemFlags_s { + /**< current interrupt setting */ + agBOOLEAN sysIntsActive; + + /**< reset in progress */ + agBOOLEAN resetInProgress; + + /**< reset status */ + agBOOLEAN resetFailed; + +} tdsaComMemFlags_t; + + +/* + * SAT related structure + */ +typedef struct satInternalIo_s +{ + tdList_t satIntIoLink; + tiIORequest_t satIntTiIORequest; + void *satIntRequestBody; + tiScsiInitiatorRequest_t satIntTiScsiXchg; + tiMem_t satIntDmaMem; + tiMem_t satIntReqBodyMem; + bit32 satIntFlag; + tiIORequest_t *satOrgTiIORequest; + bit32 id; +} satInternalIo_t; + + + +/* + * SAT specific structure per SATA drive + */ +#define SAT_NONNCQ_MAX 1 +#define SAT_NCQ_MAX 32 +#define SAT_MAX_INT_IO 16 + +typedef struct TDSASAddressID_s +{ + bit32 sasAddressLo; /**< HOST SAS address lower part */ + bit32 sasAddressHi; /**< HOST SAS address higher part */ + bit8 phyIdentifier; /**< PHY IDENTIFIER of the PHY */ +} TDSASAddressID_t; + + +struct tdsaExpander_s; + + +typedef struct tdsaDiscovery_s +{ + tdList_t discoveringExpanderList; + tdList_t UpdiscoveringExpanderList; + // tdList_t freeExpanderList; + bit32 status; + TDSASAddressID_t sasAddressIDDiscoverError; + agsaSATAIdentifyData_t *pSataIdentifyData; + struct tdsaExpander_s *RootExp; /* Root expander of discovery */ + bit32 NumOfUpExp; + bit32 type; /* discovery type: TDSA_DISCOVERY_OPTION_FULL_START + or TDSA_DISCOVERY_OPTION_INCREMENTAL_START*/ + bit32 retries; + bit32 configureRouteRetries; + bit32 deviceRetistrationRetries; + tdsaTimerRequest_t discoveryTimer; + tdsaTimerRequest_t configureRouteTimer; + tdsaTimerRequest_t deviceRegistrationTimer; + tdsaTimerRequest_t BCTimer; /* Broadcast Change timer for ResetTriggerred */ + smpRespDiscover_t SMPDiscoverResp; + bit32 pendingSMP; /* the number of pending SMP for this discovery */ + bit32 SeenBC; /* received Broadcast change */ + bit32 forcedOK; /* report DiscOK when chance is missed */ + tdsaTimerRequest_t SMPBusyTimer; /* SMP retry timer for saSMPStart busy */ + bit32 SMPRetries; /* number of SMP retries when LL returns busy for saSMPStart*/ + bit32 ResetTriggerred; /* Hard/Link reset triggerred by discovery */ + tdsaTimerRequest_t DiscoverySMPTimer; /* discovery-related SMP application Timer */ +} tdsaDiscovery_t; + + +typedef struct +{ + tdList_t satIoLinkList; /* Normal I/O from TISA */ + tdList_t satFreeIntIoLinkList; /* SAT internal I/O free list */ + tdList_t satActiveIntIoLinkList; /* SAT internal I/O active list */ + satInternalIo_t satIntIo[SAT_MAX_INT_IO]; /* Internal I/O resource */ + agsaSATAIdentifyData_t satIdentifyData; /* Copy of SATA Id Dev data */ + bit8 SN_id_limit[25]; /* temporary serial number id info */ + bit32 satNCQ; /* Flag for NCQ support */ + bit32 sat48BitSupport; /* Flag for 48-bit addressing */ + bit32 satSMARTSelfTest; /* Flag for SMART self test */ + bit32 satSMARTFeatureSet; /* Flag for SMART feature set */ + bit32 satSMARTEnabled; /* Flag for SMART enabled */ + bit32 satRemovableMedia; /* Flag for Removable Media */ + bit32 satRemovableMediaEnabled; /* Flag for Removable Media Enabled */ + bit32 satDMASupport; /* Flag for DMA Support */ + bit32 satDMAEnabled; /* Flag for DMA Enabled */ + bit32 satDMADIRSupport; /* Flag in PACKET command for DMA transfer */ + bit32 satWWNSupport; /* Flag for DMA Enabled */ + bit32 satPendingIO; /* Number of pending I/O */ + bit32 satPendingNCQIO; /* Number of pending NCQ I/O */ + bit32 satPendingNONNCQIO; /* Number of pending NON NCW I/O*/ + bit32 satNCQMaxIO; /* Max NCQ I/O in SAT or drive */ + bit32 satDriveState; /* State of SAT/drive */ + bit32 satAbortAfterReset; /* Flag: abort after SATA reset */ + bit32 satAbortCalled; /* Flag: abort called indication*/ + bit32 satVerifyState; /* Flag: Read Vrf state for diag*/ + bit32 satMaxUserAddrSectors; /* max user addressable setctors*/ + bit32 satWriteCacheEnabled; /* Flag for write cache enabled */ + bit32 satLookAheadEnabled; /* Flag for look ahead enabled */ + bit32 satDeviceFaultState; /* State of DF */ + bit32 satStopState; /* State of Start and Stop */ + bit32 satFormatState; /* State of format */ + bit32 satPMField; /* PM field, first 4 bits */ + bit8 satSignature[8]; /* Signature */ + bit32 satDeviceType; /* ATA device type */ + bit32 satSectorDone; /* Number of Sector done by Cmnd*/ + bit32 freeSATAFDMATagBitmap; /* SATA NCQ tag bit map */ + bit32 IDDeviceValid; /* ID DeviceData valid bit */ + bit8 satMaxLBA[8]; /* MAXLBA is from read capacity */ + bit32 satBGPendingDiag; /* Pending Diagnostic in backgound */ + bit32 NumOfFCA; /* number of SMP HARD RESET on this device */ + bit32 NumOfIDRetries; /* number of SMP HARD RESET after ID retries */ + tiIORequest_t *satTmTaskTag; /* TM Task Tag */ + void *satSaDeviceData; /* Pointer back to sa dev data */ + bit32 ID_Retries; /* identify device data retries */ + bit32 IDPending; /* number of pending identify device data */ +} satDeviceData_t; + + +/** \brief data structure for SAS device list + * This structure maintains the device as a list and information about + * the device such as the device type and ID address frame. + * agsaDeviceHandle_t->osData points to this structure. + */ +typedef struct tdsaDeviceData_s { + /* in tdtypes.h */ + tdsaJumpTable_t *pJumpTable; /**< a pointer to callback function jumptable */ + tiDeviceHandle_t tiDeviceHandle; + + tdList_t FreeLink; /* free dev list */ + tdList_t MainLink; /* main(in use) dev list */ + tdList_t IncDisLink; /* Used for incremental Discovery only */ + bit32 id; /* for debugging only */ + bit32 InQID; /* Inbound queue ID */ + bit32 OutQID; /* Outbound queue ID */ + bit8 DeviceType; + /* used in tiINIIOStart() */ + agsaRoot_t *agRoot; + agsaDevHandle_t *agDevHandle; + + /* for SAS; remote device */ + // agsaSASDeviceInfo_t agSASDeviceInfo; + /* device's sas address */ + TDSASAddressID_t SASAddressID; + bit8 initiator_ssp_stp_smp; + bit8 target_ssp_stp_smp; + bit8 numOfPhys; + /* SATA specific data */ + satDeviceData_t satDevData; + + /**< pointer to tdsaPortcontext which the device belongs to */ + struct tdsaPortContext_s *tdPortContext; + /* validity of device */ + bit8 valid; + bit8 valid2; + bit8 processed; /* used in TD discovery */ +#ifdef AGTIAPI_CTL + bit8 discovered; +#endif + agsaDeviceInfo_t agDeviceInfo; + agsaContext_t agContext; /* used in saRegisterNewDevice()*/ + /**< pointer to tdsaExpander if Device is expander */ + struct tdsaExpander_s *tdExpander; + struct tdsaDeviceData_s *ExpDevice; /* Expander device which this device is attached to */ + + bit8 phyID; /* PhyID this device is attached to SPC or expander */ + agsaSASIdentify_t sasIdentify; /* used only in TD discovery */ + bit8 connectionRate; + bit8 registered; + bit8 directlyAttached; + bit8 SASSpecDeviceType; /* 0 - 3; SAS_NO_DEVICE - SAS_FANOUT_EXPANDER_DEVICE */ + bit32 IOStart; + bit32 IOResponse; + agsaContext_t agDeviceResetContext; /* used in saLocalPhyControl() */ + tiIORequest_t TransportRecoveryIO; + bit32 TRflag; /* transport recovery flag; used only for tiINITransportRecovery */ + bit32 ResetCnt; /* number of reset to the device */ + tdsaTimerRequest_t SATAIDDeviceTimer; /* ID Device Data timer for SATA device */ + bit32 OSAbortAll; +#ifdef FDS_DM + bit32 devMCN; /* MCN reported by DM */ + bit32 finalMCN; /* final MCN using devMCN and local MCN */ +#endif +#ifdef FDS_SM + smDeviceHandle_t smDeviceHandle; /* for SATM */ + bit32 SMNumOfFCA; + bit32 SMNumOfID; + tdsaTimerRequest_t tdIDTimer; /* ID Device Data timer for SATA device */ +#endif +} tdsaDeviceData_t; + +/* + this field is used to add or remove SAS device from sharedcontext +*/ +typedef struct tdsaSASSubID_s +{ + bit32 sasAddressHi; + bit32 sasAddressLo; + bit8 initiator_ssp_stp_smp; + bit8 target_ssp_stp_smp; + +} tdsaSASSubID_t; + + +struct tdsaDeviceData_s; +//struct itdssDiscoveryData_s; + +/** \brief data structure for TD port context + * This structure maintains information about the port such as ID address frame + * and the discovery status and the list of devices discovered by this port. + * itdsaIni_t->PortContext[] points to this structure. + * agsaPortContext->osData points to this structure, too. + */ +typedef struct tdsaPortContext_s +{ + /**< current number of devices in this PortContext */ + bit32 Count; + + bit32 DiscoveryState; + + bit32 discoveryOptions; + /* Discovery ready is given? */ + bit32 DiscoveryRdyGiven; + /* Port has received link up */ + bit32 SeenLinkUp; + /* statistics */ + bit32 numAvailableTargets; + /* flag: indicates that discovery is trigggered by tiINIDiscoverTargets */ + bit32 osInitiatedDiscovery; + + bit32 id; /* for debugging only */ + tdList_t FreeLink; /**< free portcontext list */ + tdList_t MainLink; /**< in-use portcontext list */ + /**< SAS address of the remote device */ + bit32 sasRemoteAddressHi; /**< SAS address high part */ + bit32 sasRemoteAddressLo; /**< SAS address low part */ + /**< SAS ID frame of the remote device */ + agsaSASIdentify_t sasIDframe; + + /**< SAS address of the local device*/ + bit32 sasLocalAddressHi; /**< SAS address high part */ + bit32 sasLocalAddressLo; /**< SAS address low part */ + + /**< the list of PhyID belonging to this port */ + bit8 PhyIDList[TD_MAX_NUM_PHYS]; + tiPortalContext_t *tiPortalContext; + /* used in tiINIDiscoverTarget() */ + agsaRoot_t *agRoot; + agsaPortContext_t *agPortContext; + /* maybe needs timers for saPhyStart() */ + + bit8 nativeSATAMode; /* boolean flag: whether the port is in Native SATA mode */ + bit8 remoteSignature[8]; /* the remote signature of the port is the port is in native SATA mode */ + bit8 directAttatchedSAS; /* boolean flag: whether the port connected directly to SAS end device*/ + /* SAS/SATA discovery information such as discoveringExpanderList */ + tdsaDiscovery_t discovery; + bit32 valid; + bit8 LinkRate; + bit32 RegisteredDevNums; /* registered number of devices */ + bit32 eventPhyID; /* used for saHwEventAck() */ + bit32 Transient; /* transient period between link up and link down/port recovery */ + agsaContext_t agContext; /* used in tiCOMPortStop()*/ + bit32 PortRecoverPhyID; /* used to remember PhyID in Port_Recover event; used in ossaDeviceRegistrationCB() */ + bit32 DiscFailNSeenBC; /* used to remember broadcast change after discovery failure */ + bit8 remoteName[68]; +#ifdef FDS_DM + dmPortContext_t dmPortContext; + bit32 DMDiscoveryState; /* DM discovery state returned by tddmDiscoverCB or tddmQueryDiscoveryCB */ + bit32 UseDM; /* set only when the directly attached target is SMP target(expander) */ + bit32 UpdateMCN; /* flag for inidicating update MCN */ +#endif +} tdsaPortContext_t; + +/** \brief data structure for TD port information + * This structure contains information in order to start the port + * The most of fields are filled in by OS layer and there can be up to + * 8 of these structures + * tiPortalContext_t->tdData points to this structure. + */ +typedef struct tdsaPortStartInfo_s { + tiPortalContext_t *tiPortalContext; + tdsaPortContext_t *portContext; /* tdsaportcontext */ + agsaSASIdentify_t SASID; /* SAS ID of the local */ + tdssPortFlags_t flags; + agsaPhyConfig_t agPhyConfig; +} tdsaPortStartInfo_t; +/* + expander data structure +*/ + +#define REPORT_LUN_LEN 16 +#define REPORT_LUN_OPCODE 0xa0 +typedef struct tdDeviceLUNInfo_s +{ + unsigned long tiDeviceHandle; + bit32 numOfLun; +}tdDeviceLUNInfoIOCTL_t; + +typedef struct tdsaExpander_s +{ + tdList_t linkNode; /**< the link node data structure of the expander */ + tdList_t upNode; /**< the link node data structure of the expander */ + tdsaDeviceData_t *tdDevice; /**< the pointer to the device */ + struct tdsaExpander_s *tdUpStreamExpander; /**< the pointer to the upstream expander device */ + bit8 hasUpStreamDevice; + bit8 discoveringPhyId; + bit16 routingIndex; /* maximum routing table index reported by expander */ + bit16 currentIndex[TD_MAX_EXPANDER_PHYS]; /* routing table index in use */ + tdsaDeviceData_t *tdDeviceToProcess; /* on some callbacks, this is a link to the device of interest */ + bit32 configSASAddressHi; + bit32 configSASAddressLo; + struct tdsaExpander_s *tdCurrentDownStreamExpander; + bit8 upStreamPhys[TD_MAX_EXPANDER_PHYS]; + bit16 numOfUpStreamPhys; + bit16 currentUpStreamPhyIndex; + bit32 upStreamSASAddressHi; + bit32 upStreamSASAddressLo; + bit32 underDiscovering; + bit32 configRouteTable: 1; + bit32 configuring: 1; + bit32 configReserved: 30; + bit32 id; /* for debugging */ + struct tdsaExpander_s *tdReturnginExpander; + bit8 downStreamPhys[TD_MAX_EXPANDER_PHYS]; + bit16 numOfDownStreamPhys; + bit16 currentDownStreamPhyIndex; + bit32 discoverSMPAllowed; /* used only for configurable routers */ + bit8 routingAttribute[TD_MAX_EXPANDER_PHYS]; + bit32 configSASAddressHiTable[DEFAULT_MAX_DEV]; + bit32 configSASAddressLoTable[DEFAULT_MAX_DEV]; + bit32 configSASAddrTableIndex; + +} tdsaExpander_t; + +/* + * SATA SAT specific function pointer for SATA completion for SAT commands. + */ +typedef void (*satCompleteCbPtr_t )( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *satIOContext + ); + +/* + * SATA SAT specific function for I/O context + */ +typedef struct satIOContext_s +{ + tdList_t satIoContextLink; + satDeviceData_t *pSatDevData; + agsaFisRegHostToDevice_t *pFis; + tiIniScsiCmnd_t *pScsiCmnd; + scsiRspSense_t *pSense; + tiSenseData_t *pTiSenseData; + void *tiRequestBody; + void *tiScsiXchg; /* for writesame10() */ + bit32 reqType; + bit32 interruptContext; + satCompleteCbPtr_t satCompleteCB; + satInternalIo_t *satIntIoContext; + tiDeviceHandle_t *ptiDeviceHandle; + bit8 sataTag; + bit8 superIOFlag;/* Flag indicating type for tiScsiXchg */ + bit8 reserved1; /* Padding for allignment */ + bit8 reserved2; /* Padding for allignment */ + bit32 currentLBA; /* current LBA for read and write */ + bit32 ATACmd; /* ATA command */ + bit32 OrgTL; /* original tranfer length(tl) */ + bit32 LoopNum; /* denominator tl */ + bit32 LoopNum2; /* denominator tl */ + bit8 LBA[8]; /* for reassign blocks; current LBA */ + bit32 ParmIndex; /* for reassign blocks;current idx in defective LBA LIST */ + bit32 ParmLen; /* for reassign blocks; defective LBA list length */ + bit32 NotifyOS; /* only for task management */ + bit32 TMF; /* task management function */ + struct satIOContext_s *satToBeAbortedIOContext; + struct satIOContext_s *satOrgIOContext; + bit32 pid; /* port id; used to protect double completion */ +} satIOContext_t; + + +/** \brief data structure for SAS SSP IO reuqest body + * This structure contains IO related fields. + * agsaIORequest->osData points to this + */ +typedef struct tdIORequestBody_s { + tdssIOCompleted_t IOCompletionFunc; + tiDeviceHandle_t *tiDevHandle; + tiIORequest_t *tiIORequest; /* for ini */ + agsaIORequest_t agIORequest; /* for command and task and tm response and response */ + tiIORequest_t *tiIOToBeAbortedRequest; /* IO to be aborted */ + agsaContext_t agContext; +#ifdef FDS_SM + smIORequestBody_t smIORequestBody; /*SATA IO request body*/ + smIORequest_t smIORequest; /* for SATM */ + void *osMemHandle; /* for ID data */ + bit32 pid; /* port id for SATA completion */ + bit32 superIOFlag; /* Super IO or not */ + union { + smScsiInitiatorRequest_t smSCSIRequest; + smSuperScsiInitiatorRequest_t smSuperSCSIRequest; + } SM; +#endif + union { + struct { + agsaSASRequestBody_t agSASRequestBody; + // agsaSASRequestBody_t agSASResponseBody; + /* SSP response */ + // agsaSSPResponseInfoUnit_t agSSPRspIU; + } SAS; + struct { + agsaSATAInitiatorRequest_t agSATARequestBody; + scsiRspSense_t sensePayload; + tiSenseData_t tiSenseData; + satIOContext_t satIOContext; + } SATA; + } transport; + bit32 ioStarted; + bit32 ioCompleted; + bit32 reTries; + /**< for ESGL */ + tdList_t EsglPageList; + bit32 agRequestType; + union { + struct { + bit32 expDataLength; + tiSgl_t tiSgl1; + tiSgl_t tiSgl2; + void *sglVirtualAddr; + } InitiatorRegIO; /* regular IO */ + struct { + void *osMemHandle; + tiIORequest_t *CurrentTaskTag; + tiIORequest_t *TaskTag; + } InitiatorTMIO; /* task management */ + + struct { + tiIORequest_t tiIORequest; /* for target */ + + union { + struct { + tiSgl_t tiSgl1; + void * sglVirtualAddr; + } RegIO; + + struct { + tiSgl_t tiSgl1; + void * sglVirtualAddr; + tiSgl_t tiSglMirror; + void * sglMirrorVirtualAddr; + tdList_t EsglMirrorPageList; + } MirrorIO; + + } TargetIOType; + + } TargetIO; /* target regular IO */ + + + } IOType; +} tdIORequestBody_t; + +/** \brief data structure for SAS SMP reuqest body + * This structure contains IO related fields. + * agsaIORequest->osData points to this + * + */ +typedef struct tdssSMPRequestBody_s { + tdIORequestBody_t IORequestBody; /* for combo, must be the first */ + tdssSMPCompleted_t SMPCompletionFunc;/* must be the second */ + + tiDeviceHandle_t *tiDevHandle; /* not used for TD generated SMP */ + agsaIORequest_t agIORequest; + agsaSASRequestBody_t agSASRequestBody; + agsaSATAInitiatorRequest_t agSATARequestBody; + void *osMemHandle; + tdsaDeviceData_t *tdDevice; + tiIORequest_t *CurrentTaskTag; /* SMP is used for simulate target reset */ + tdsaPortContext_t *tdPortContext; /* portcontext where SMP is sent from */ + bit8 smpPayload[SMP_DIRECT_PAYLOAD_LIMIT]; /* for smp retries; + only for direct SMP */ + bit32 retries; /* number of retries */ + bit32 queueNumber; /* number of retries */ + /* for indirect SMP req/rsp */ + void *IndirectSMPReqosMemHandle; + void *IndirectSMPReq; + bit32 IndirectSMPReqLen; + void *IndirectSMPResposMemHandle; + void *IndirectSMPResp; + bit32 IndirectSMPRespLen; + +} tdssSMPRequestBody_t; + +#ifdef AGTIAPI_CTL +typedef struct tdIORequest_s +{ + tiIORequest_t tiIORequest; + tdIORequestBody_t tdIORequestBody; + void *osMemHandle; + + void *osMemHandle2; + bit32 physUpper32; + bit32 physLower32; + void *virtAddr; + + tiIntrEventType_t eventType; + bit32 eventStatus; +} tdIORequest_t; +#endif + +#ifdef PASSTHROUGH +/* this is allocated by OS layer but used in TD layer just like tdIORequestBody */ +typedef struct tdPassthroughCmndBody_s +{ + ostiPassthroughCmndEvent_t EventCB; + tiPassthroughRequest_t *tiPassthroughRequest; + tiDeviceHandle_t *tiDevHandle; + bit32 tiPassthroughCmndType; /* used in local abort */ + union { + struct { +#ifdef TO_DO + tiSMPFunction_t SMPFn; + tiSMPFunctionResult_t SMPFnResult; /* for SMP target only */ + bit32 IT; /* 0: initiator 1: target */ + tiSMPFrameHeader_t SMPHeader; +#endif + tdssSMPRequestBody_t SMPBody; + } SMP; + struct { + tiDataDirection_t dataDirection; + } RMC; + } protocol; +} tdPassthroughCmndBody_t; + +#endif + +#endif /* __TDTYPES_H__ */ diff --git a/sys/dev/pms/RefTisa/tisa/sassata/sas/ini/itdcb.c b/sys/dev/pms/RefTisa/tisa/sassata/sas/ini/itdcb.c new file mode 100644 index 000000000000..8f450371123f --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/sas/ini/itdcb.c @@ -0,0 +1,5350 @@ +/******************************************************************************* +** +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +** +********************************************************************************/ +/*****************************************************************************/ +/** \file + * + * This file contains initiator CB functions + * + */ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#ifdef FDS_SM +#include +#include +#include +#endif + +#ifdef FDS_DM +#include +#include +#include +#endif + +#include +#include +#include + +#ifdef INITIATOR_DRIVER +#include +#include +#include +#endif + +#ifdef TARGET_DRIVER +#include +#include +#include +#endif + +#include +#include + +/***************************************************************************** +*! \brief itdssTaskCompleted +* +* Purpose: This routine is called to complete an task management request +* previously issued to the LL Layer. All task management completes with +* this function except query task management. +* +* \param agRoot: Pointer to driver Instance. +* \param agIORequest: Pointer to the I/O Request data structure for +* this I/O. +* \param agIOStatus: Status of I/O just completed. +* \param agIOInfoLen: Length of the I/O information associated with this +* I/O request +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* \note - This is a initiator specific function called by the jump table. +* +*****************************************************************************/ +osGLOBAL void +itdssTaskCompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tiIORequest_t *taskTag = agNULL, *currentTaskTag = agNULL; + tdIORequestBody_t *tdIORequestBody = agNULL; + tdIORequestBody_t *TMtdIORequestBody = agNULL; + tdIORequestBody_t *AborttdIORequestBody = agNULL; + agsaIORequest_t *agTaskedIORequest; + agsaSSPResponseInfoUnit_t agSSPRespIU; + bit8 respData[128]; + bit32 respLen; +#ifdef TD_DEBUG_ENABLE + bit32 data_status; +#endif + agsaSASRequestBody_t *agSASRequestBody = agNULL; + agsaSSPScsiTaskMgntReq_t *agSSPTaskMgntRequest = agNULL; + agsaIORequest_t *agAbortIORequest; + tdIORequestBody_t *tdAbortIORequestBody; + bit32 PhysUpper32; + bit32 PhysLower32; + bit32 memAllocStatus; + void *osMemHandle; + bit32 abortOrquery = agTRUE; + tiDeviceHandle_t *tiDeviceHandle = agNULL; + tdsaDeviceData_t *oneDeviceData = agNULL; + agsaDevHandle_t *agDevHandle = agNULL; + bit32 status = AGSA_RC_FAILURE; + + TI_DBG2(("itdssTaskCompleted: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + /* check the agIOStatus */ + currentTaskTag = tdIORequestBody->IOType.InitiatorTMIO.CurrentTaskTag; + + if (currentTaskTag == agNULL) + { + TI_DBG1(("itdssTaskCompleted: currentTaskTag is NULL \n")); + /* as the currentTaskTag is agNULL, shall not call ostiInitiatorEvent */ + #if 0 + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMFailed, + currentTaskTag ); + #endif + /* free up allocated memory */ + ostiFreeMemory( + tiRoot, + tdIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; + } + + if (agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("itdssTaskCompleted: agIOStatus failed and tiTMFailed\n")); + if (agIOStatus == OSSA_IO_TM_TAG_NOT_FOUND) + { + TI_DBG1(("itdssTaskCompleted: agIOStatus OSSA_IO_TM_TAG_NOT_FOUND\n")); + } + else + if (agIOStatus == OSSA_IO_ABORTED) + { + TI_DBG1(("itdssTaskCompleted: agIOStatus OSSA_IO_ABORTED\n")); + } + else + { + TI_DBG1(("itdssTaskCompleted: agIOStatus 0x%x\n", agIOStatus)); + } + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMFailed, + currentTaskTag ); + /* free up allocated memory */ + ostiFreeMemory( + tiRoot, + tdIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; + } + + /* parse the task management response */ + /* reads agsaSSPResponseInfoUnit_t */ + saFrameReadBlock(agRoot, agParam, 0, &agSSPRespIU, sizeof(agsaSSPResponseInfoUnit_t)); +#ifdef TD_DEBUG_ENABLE + data_status = SA_SSPRESP_GET_DATAPRES(&agSSPRespIU); +#endif + respLen = SA_SSPRESP_GET_RESPONSEDATALEN(&agSSPRespIU); + TI_DBG6(("itdssTaskCompleted: dataPres %d. should be 1\n", data_status)); + /* reads response data */ + saFrameReadBlock(agRoot, agParam, + sizeof(agsaSSPResponseInfoUnit_t), + respData, respLen); + TI_DBG6(("itdssTaskCompleted: res code %d. should be 0\n", respData[3])); + + taskTag = tdIORequestBody->IOType.InitiatorTMIO.TaskTag; + if (taskTag == agNULL) + { + /* other than Abort Task or Query Task */ + TI_DBG1(("itdssTaskCompleted: taskTag is NULL\n")); + + abortOrquery = agFALSE; + TMtdIORequestBody = (tdIORequestBody_t *)currentTaskTag->tdData; + } + else + { + /* Abort Task or Query Task */ + TI_DBG2(("itdssTaskCompleted: taskTag is NOT NULL\n")); + abortOrquery = agTRUE; + TMtdIORequestBody = (tdIORequestBody_t *)currentTaskTag->tdData; + } + + TI_DBG2(("itdssTaskCompleted: TMtdIORequestBody %p\n", TMtdIORequestBody)); + + if (TMtdIORequestBody == agNULL) + { + TI_DBG1(("itdssTaskCompleted: TMtdIORequestBody is NULL \n")); + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMFailed, + currentTaskTag ); + /* free up allocated memory */ + ostiFreeMemory( + tiRoot, + tdIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; + } + + if (agIOStatus == OSSA_IO_SUCCESS && agIOInfoLen == 0) + { + TI_DBG1(("itdssTaskCompleted: agIOInfoLen is zero, wrong\n")); + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMFailed, + currentTaskTag ); + /* free up allocated memory */ + ostiFreeMemory( + tiRoot, + tdIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; + } + + agSASRequestBody = (agsaSASRequestBody_t *)&(TMtdIORequestBody->transport.SAS.agSASRequestBody); + agSSPTaskMgntRequest = (agsaSSPScsiTaskMgntReq_t *)&(agSASRequestBody->sspTaskMgntReq); + TI_DBG2(("itdssTaskCompleted: agSSPTaskMgntRequest->taskMgntFunction 0x%x\n", agSSPTaskMgntRequest->taskMgntFunction)); + + if ( (agSSPTaskMgntRequest->taskMgntFunction == AGSA_ABORT_TASK || + agSSPTaskMgntRequest->taskMgntFunction == AGSA_QUERY_TASK) && + abortOrquery == agFALSE + ) + { + TI_DBG1(("itdssTaskCompleted: incorrect tasktag, first\n")); + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMFailed, + currentTaskTag ); + /* free up allocated memory */ + ostiFreeMemory( + tiRoot, + tdIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; + } + + if ((agSSPTaskMgntRequest->taskMgntFunction == AGSA_ABORT_TASK_SET || + agSSPTaskMgntRequest->taskMgntFunction == AGSA_CLEAR_TASK_SET || + agSSPTaskMgntRequest->taskMgntFunction == AGSA_LOGICAL_UNIT_RESET || + agSSPTaskMgntRequest->taskMgntFunction == AGSA_CLEAR_ACA ) && + abortOrquery == agTRUE + ) + { + TI_DBG1(("itdssTaskCompleted: incorrect tasktag, second\n")); + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMFailed, + currentTaskTag ); + /* free up allocated memory */ + ostiFreeMemory( + tiRoot, + tdIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; + } + + + if (agSSPTaskMgntRequest->taskMgntFunction == AGSA_ABORT_TASK) + { + TI_DBG2(("itdssTaskCompleted: calling saSSPAbort()\n")); + AborttdIORequestBody = (tdIORequestBody_t *)taskTag->tdData; + if (AborttdIORequestBody == agNULL) + { + TI_DBG1(("itdssTaskCompleted: wrong, AborttdIORequestBody is NULL\n")); + return; + } + + tiDeviceHandle = AborttdIORequestBody->tiDevHandle; + if (tiDeviceHandle == agNULL) + { + TI_DBG1(("itdssTaskCompleted: wrong, tiDeviceHandle is NULL\n")); + return; + } + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + if (oneDeviceData == agNULL) + { + TI_DBG1(("itdssTaskCompleted: wrong, oneDeviceData is NULL\n")); + return; + } + agDevHandle = oneDeviceData->agDevHandle; + if (agDevHandle == agNULL) + { + TI_DBG1(("itdssTaskCompleted: wrong, agDevHandle is NULL\n")); + } + + agTaskedIORequest = (agsaIORequest_t *)&(AborttdIORequestBody->agIORequest); + if (agTaskedIORequest == agNULL) + { + TI_DBG1(("itdssTaskCompleted: agTaskedIORequest is NULL \n")); + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMFailed, + currentTaskTag ); + /* free up allocated memory */ + ostiFreeMemory( + tiRoot, + tdIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; + } + + + /* allocating agIORequest for abort itself */ + memAllocStatus = ostiAllocMemory( + tiRoot, + &osMemHandle, + (void **)&tdAbortIORequestBody, + &PhysUpper32, + &PhysLower32, + 8, + sizeof(tdIORequestBody_t), + agTRUE + ); + if (memAllocStatus != tiSuccess) + { + /* let os process IO */ + TI_DBG1(("itdssTaskCompleted: ostiAllocMemory failed...\n")); + return; + } + + if (tdAbortIORequestBody == agNULL) + { + /* let os process IO */ + TI_DBG1(("itdssTaskCompleted: ostiAllocMemory returned NULL tdAbortIORequestBody\n")); + return; + } + + /* setup task management structure */ + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle = osMemHandle; + tdAbortIORequestBody->tiDevHandle = tiDeviceHandle; + /* setting callback */ + tdAbortIORequestBody->IOCompletionFunc = itdssIOAbortedHandler; + + /* setting to NULL because the local abort is triggered by TD layer */ + tdAbortIORequestBody->tiIOToBeAbortedRequest = agNULL; + /* initialize agIORequest */ + agAbortIORequest = &(tdAbortIORequestBody->agIORequest); + agAbortIORequest->osData = (void *) tdAbortIORequestBody; + agAbortIORequest->sdkData = agNULL; /* LL takes care of this */ + + status = saSSPAbort(agRoot, agAbortIORequest, tdsaRotateQnumber(tiRoot, oneDeviceData), agDevHandle, 0, agTaskedIORequest, agNULL); + if (status != AGSA_RC_SUCCESS) + { + TI_DBG1(("itdssTaskCompleted: saSSPAbort failed agIOInfoLen is zero, wrong\n")); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + } + + /* + parse the response and based on the parse, + set the flag + */ + if (respData[3] == AGSA_TASK_MANAGEMENT_FUNCTION_COMPLETE || + respData[3] == AGSA_TASK_MANAGEMENT_FUNCTION_SUCCEEDED) + { + TI_DBG2(("itdssTaskCompleted: tiTMOK\n")); + tiDeviceHandle = TMtdIORequestBody->tiDevHandle; + if (tiDeviceHandle == agNULL) + { + TI_DBG1(("itdssTaskCompleted: wrong, tiDeviceHandle is NULL\n")); + return; + } + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + if (oneDeviceData == agNULL) + { + TI_DBG1(("itdssTaskCompleted: wrong, oneDeviceData is NULL\n")); + return; + } + agDevHandle = oneDeviceData->agDevHandle; + if (agDevHandle == agNULL) + { + TI_DBG1(("itdssTaskCompleted: wrong, agDevHandle is NULL\n")); + } + TI_DBG2(("itdssTaskCompleted: setting Device state to SA_DS_OPERATIONAL\n")); + + saSetDeviceState(agRoot, agNULL, tdsaRotateQnumber(tiRoot, oneDeviceData), agDevHandle, SA_DS_OPERATIONAL); + + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMOK, + currentTaskTag ); + } + else + { + TI_DBG1(("itdssTaskCompleted: tiTMFailed\n")); + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMFailed, + currentTaskTag ); + + } + + /* free up allocated memory */ + ostiFreeMemory( + tiRoot, + tdIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; +} + +#ifdef INITIATOR_DRIVER + +/***************************************************************************** +*! \brief itdssQueryTaskCompleted +* +* Purpose: This routine is called to complete an query task management request +* previously issued to the LL Layer. +* +* \param agRoot: Pointer to driver Instance. +* \param agIORequest: Pointer to the I/O Request data structure for +* this I/O. +* \param agIOStatus: Status of I/O just completed. +* \param agIOInfoLen: Length of the I/O information associated with this +* I/O request +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* +* \return: None +* +* \note - This is a initiator specific function called by the jump table. +* +*****************************************************************************/ +osGLOBAL void +itdssQueryTaskCompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tiIORequest_t *taskTag = agNULL; + tdIORequestBody_t *tdIORequestBody = agNULL; /* query task */ + tdIORequestBody_t *TMtdIORequestBody = agNULL; /* IO being query tasked */ + agsaIORequest_t *agTaskedIORequest = agNULL; + agsaSSPResponseInfoUnit_t agSSPRespIU; + bit8 respData[128]; + bit32 respLen; +#ifdef TD_DEBUG_ENABLE + bit32 data_status; +#endif + agsaSASRequestBody_t *agSASRequestBody = agNULL; + agsaSSPScsiTaskMgntReq_t *agSSPTaskMgntRequest = agNULL; + bit32 status; + agsaIORequest_t *agAbortIORequest = agNULL; + tdIORequestBody_t *tdAbortIORequestBody = agNULL; + bit32 PhysUpper32; + bit32 PhysLower32; + bit32 memAllocStatus; + void *osMemHandle = agNULL; + tiDeviceHandle_t *tiDeviceHandle = agNULL; + tdsaDeviceData_t *oneDeviceData = agNULL; + agsaDevHandle_t *agDevHandle = agNULL; + + TI_DBG2(("itdssQueryTaskComplted: start\n")); + + /* query task management IORequestBody */ + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + /* OS's tiIORequest for this query taks, which is agNULL */ + //currentTaskTag = tdIORequestBody->IOType.InitiatorTMIO.CurrentTaskTag; + + /* + currentTaskTag is agNULL for query task since it is generated by + TD layer + */ + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* let os process IO */ + TI_DBG1(("itdssQueryTaskComplted: agIOStatus failed and tiTMFailed\n")); + /* free up allocated memory */ + ostiFreeMemory( + tiRoot, + tdIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; + } + /* parse the task management response */ + /* reads agsaSSPResponseInfoUnit_t */ + saFrameReadBlock(agRoot, agParam, 0, &agSSPRespIU, sizeof(agsaSSPResponseInfoUnit_t)); +#ifdef TD_DEBUG_ENABLE + data_status = SA_SSPRESP_GET_DATAPRES(&agSSPRespIU); +#endif + respLen = SA_SSPRESP_GET_RESPONSEDATALEN(&agSSPRespIU); + + TI_DBG6(("itdssQueryTaskCompleted: dataPres %d. should be 1\n", data_status)); + /* reads response data */ + saFrameReadBlock(agRoot, agParam, + sizeof(agsaSSPResponseInfoUnit_t), + respData, respLen); + + TI_DBG6(("itdssQueryTaskCompleted: res code %d. should be 0\n", respData[3])); + + /* IO being query tasked */ + taskTag = tdIORequestBody->IOType.InitiatorTMIO.TaskTag; + if (taskTag == agNULL) + { + TI_DBG1(("itdssQueryTaskComplted: taskTag is NULL \n")); + /* free up allocated memory */ + ostiFreeMemory( + tiRoot, + tdIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; + } + + /* request body of IO being query tasked */ + TMtdIORequestBody = (tdIORequestBody_t *)taskTag->tdData; + if (TMtdIORequestBody == agNULL) + { + TI_DBG1(("itdssQueryTaskComplted: TMtdIORequestBody is NULL \n")); + /* free up allocated memory */ + ostiFreeMemory( + tiRoot, + tdIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; + } + + agTaskedIORequest = &(TMtdIORequestBody->agIORequest); + if (agTaskedIORequest == agNULL) + { + TI_DBG1(("itdssQueryTaskComplted: agTaskedIORequest is NULL \n")); + /* free up allocated memory */ + ostiFreeMemory( + tiRoot, + tdIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; + } + + if (agIOStatus == OSSA_IO_SUCCESS && agIOInfoLen == 0) + { + TI_DBG1(("itdssQueryTaskCompleted: agIOInfoLen is zero, wrong\n")); + /* free up allocated memory */ + ostiFreeMemory( + tiRoot, + tdIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; + } + /* this is query task itself */ + agSASRequestBody = &(tdIORequestBody->transport.SAS.agSASRequestBody); + agSSPTaskMgntRequest = &(agSASRequestBody->sspTaskMgntReq); + if (agSSPTaskMgntRequest->taskMgntFunction == AGSA_QUERY_TASK) + { + /* + process response for query task + For query task, response code must be either + TASK MANAGEMENT FUNCTION COMPLETE or TASK MANAGEMENT FUNCTION SUCCEEDED by + SAM + + 1. If TASK MANAGEMENT FUNCTION SUCCEEDE, do nothing + + 2. If TASK MANAGEMENT FUNCTION COMPLETE and IO is not completed, + retry by saSSPAbort() + */ + if (respData[3] == AGSA_TASK_MANAGEMENT_FUNCTION_SUCCEEDED) + { + /* OK; IO is being process at the target; do nothing */ + } + else if (respData[3] == AGSA_TASK_MANAGEMENT_FUNCTION_COMPLETE) + { + tiDeviceHandle = TMtdIORequestBody->tiDevHandle; + if (tiDeviceHandle == agNULL) + { + TI_DBG1(("itdssQueryTaskCompleted: wrong, tiDeviceHandle is NULL\n")); + /* free up allocated memory */ + ostiFreeMemory( + tiRoot, + tdIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; + } + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + if (oneDeviceData == agNULL) + { + TI_DBG1(("itdssQueryTaskCompleted: wrong, oneDeviceData is NULL\n")); + /* free up allocated memory */ + ostiFreeMemory( + tiRoot, + tdIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + + return; + } + agDevHandle = oneDeviceData->agDevHandle; + if (agDevHandle == agNULL) + { + TI_DBG1(("itdssQueryTaskCompleted: wrong, agDevHandle is NULL\n")); + } + /* if IO is not completed, retry IO by saSSPAbort() */ + if (TMtdIORequestBody->ioCompleted != agTRUE) + { + /* allocating agIORequest for abort itself */ + memAllocStatus = ostiAllocMemory( + tiRoot, + &osMemHandle, + (void **)&tdAbortIORequestBody, + &PhysUpper32, + &PhysLower32, + 8, + sizeof(tdIORequestBody_t), + agTRUE + ); + if (memAllocStatus != tiSuccess) + { + /* let os process IO */ + TI_DBG1(("itdssQueryTaskCompleted: ostiAllocMemory failed...\n")); + /* free up allocated memory */ + ostiFreeMemory( + tiRoot, + tdIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + + return; + } + if (tdAbortIORequestBody == agNULL) + { + /* let os process IO */ + TI_DBG1(("itdssQueryTaskCompleted: ostiAllocMemory returned NULL tdAbortIORequestBody\n")); + /* free up allocated memory */ + ostiFreeMemory( + tiRoot, + tdIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + + return; + } + + /* setup task management structure */ + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle = osMemHandle; + tdAbortIORequestBody->tiDevHandle = tdIORequestBody->tiDevHandle; + tdAbortIORequestBody->tiIOToBeAbortedRequest = agNULL; + + /* setting callback */ + tdAbortIORequestBody->IOCompletionFunc = itdssIOAbortedHandler; + + /* initialize agIORequest */ + agAbortIORequest = &(tdAbortIORequestBody->agIORequest); + agAbortIORequest->osData = (void *) tdAbortIORequestBody; + agAbortIORequest->sdkData = agNULL; /* LL takes care of this */ + + TI_DBG2(("itdssQueryTaskCompleted: issuing saSSPAbort()\n")); + status = saSSPAbort(agRoot, agAbortIORequest, tdsaRotateQnumber(tiRoot, oneDeviceData), agDevHandle, 0, agTaskedIORequest, agNULL); + if (status != AGSA_RC_SUCCESS) + { + TI_DBG1(("itdssQueryTaskCompleted: saSSPAbort failed agIOInfoLen is zero, wrong\n")); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + } + } + else + { + TI_DBG1(("itdssQueryTaskComplted: not expected response 0x%x\n",respData[3])); + } + } + else + { + TI_DBG1(("itdssQueryTaskCompleted: not expected task management fn %d\n",agSSPTaskMgntRequest->taskMgntFunction)); + } + + /* free up allocated memory */ + ostiFreeMemory( + tiRoot, + tdIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; +} +#endif + +/***************************************************************************** +*! \brief itssdosIOCompleted +* +* Purpose: This routine is called to complete an I/O request previously +* issued to the LL Layer in saSSPStart(). +* +* \param agRoot: Pointer to driver Instance. +* \param agIORequest: Pointer to the I/O Request data structure for +* this I/O. +* \param agIOStatus: Status of I/O just completed. +* \param agIOInfoLen: Length of the I/O information associated with this +* I/O request +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* \note - This is a initiator specific function called by the jump table. +* +*****************************************************************************/ +FORCEINLINE void +itdssIOCompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + itdsaIni_t *Initiator = (itdsaIni_t *)osData->itdsaIni; + tdIORequestBody_t *tdIORequestBody = agNULL; + agsaSASRequestBody_t *agSASRequestBody = agNULL; + agsaSSPInitiatorRequest_t *agSSPInitiatorRequest = agNULL; + agsaSSPResponseInfoUnit_t agSSPRespIU; + + bit32 scsi_status = 0; + + tiDeviceHandle_t *tiDeviceHandle = agNULL; + tdsaDeviceData_t *oneDeviceData = agNULL; + + TI_DBG6(("itdssIOCompleted: start\n")); + TI_DBG6(("itdssIOCompleted: agIOInfoLen %d\n", agIOInfoLen)); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + TD_ASSERT((NULL != tdIORequestBody), "itdssIOCompleted:tdIORequestBody NULL"); + if ( NULL == tdIORequestBody ) // handle windows assert case + { + return; + } + Initiator->NumIOsActive--; + +#ifdef DBG + if (tdIORequestBody->ioCompleted == agTRUE) + { +#ifdef TD_DEBUG_ENABLE + tiDeviceHandle = tdIORequestBody->tiDevHandle; + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; +#endif /*TD_DEBUG_ENABLE*/ + TI_DBG1(("itdssIOCompleted: Error!!!!!! double completion\n")); +#ifdef TD_DEBUG_ENABLE + TI_DBG1(("itdssIOCompleted: did %d \n", oneDeviceData->id)); +#endif /*TD_DEBUG_ENABLE*/ + } + + if (Initiator->NumIOsActive == 0) + { + /* so far, no timer assocaicated here */ + TI_DBG6(("itdssIOCompleted: no acitve IO's. Kill timers\n")); + } + + if (tdIORequestBody->tiIORequest->osData == agNULL) + { + TI_DBG1( ("itdssIOCompleted: pos 1; " + "tdIORequestBody->tiIORequest->osData is null, wrong\n") ); + } +#endif /*DBG*/ + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + /* Process completion for debugging, printing cbd */ + agSASRequestBody = &(tdIORequestBody->transport.SAS.agSASRequestBody); + agSSPInitiatorRequest = &(agSASRequestBody->sspInitiatorReq); + + TI_DBG6( ("itdssIOCompleted: CDB 0x%x\n", + agSSPInitiatorRequest->sspCmdIU.cdb[0]) ); + + /* no respsonse or sense data; data has been processed */ + if((agIOStatus == OSSA_IO_SUCCESS) && (agIOInfoLen == 0)) + { + // if this is a standard Inquiry command, notify Stoport to set the + // device queue depth to maximize oustanding IO + if ( (agSSPInitiatorRequest->sspCmdIU.cdb[0] == SCSIOPC_INQUIRY) && + ((agSSPInitiatorRequest->sspCmdIU.cdb[1] & 0x01) == 0)) + { + bit32 qdepth = 32; + tiDeviceHandle = tdIORequestBody->tiDevHandle; + if( tiDeviceHandle ) + { + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + if( oneDeviceData->DeviceType == TD_SAS_DEVICE ) + { + qdepth = MAX_OUTSTANDING_IO_PER_LUN; + } + if( oneDeviceData->DeviceType == TD_SATA_DEVICE ) + { + qdepth = 63; + } + } + + if ( ostiSetDeviceQueueDepth( tiRoot, + tdIORequestBody->tiIORequest, + MAX_OUTSTANDING_IO_PER_LUN ) == agFALSE ) + { + TI_DBG1( ( "itdssIOCompleted: failed to call " + "ostiSetDeviceQueueDepth() Q=%d !!!\n", qdepth ) ); + } + else + { + TI_DBG2(("itdssIOCompleted: set ostiSetDeviceQueueDepth() Q=%d\n",qdepth)); + } + } + // SCSI command was completed OK, this is the normal path. Now call the + // OS Specific module about this completion. + ostiInitiatorIOCompleted( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + agTRUE /* intContext; is not being used */ + ); + return; + } + + else + { + TI_DBG6(("itdssIOCompleted: SUCCESS but data returned \n")); + TI_DBG6( ("itdssIOCompleted: agIOStatus SUCCESS but data returned 0x%x\n", + agIOStatus) ); + if(tdIORequestBody) + { + tiDeviceHandle = tdIORequestBody->tiDevHandle; + if(tiDeviceHandle) + { + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + } + } + + osti_memset(&agSSPRespIU, 0, sizeof(agsaSSPResponseInfoUnit_t)); + + saFrameReadBlock( agRoot, + agParam, + 0, + &agSSPRespIU, + sizeof(agsaSSPResponseInfoUnit_t) ); + scsi_status = agSSPRespIU.status; + + switch (scsi_status) + { + case SCSI_STAT_GOOD: + TI_DBG2( ("itdssIOCompleted: SCSI_STAT_GOOD %d\n", + Initiator->ScsiStatusCounts.GoodStatus) ); + Initiator->ScsiStatusCounts.GoodStatus++; + break; + case SCSI_STAT_CHECK_CONDITION: + TI_DBG1( ("itdssIOCompleted: SCSI_STAT_CHECK_CONDITION %d\n", + Initiator->ScsiStatusCounts.CheckCondition) ); + Initiator->ScsiStatusCounts.CheckCondition++; + break; + case SCSI_STAT_BUSY: + TI_DBG1( ("itdssIOCompleted: SCSI_STAT_BUSY %d\n", + Initiator->ScsiStatusCounts.BusyStatus) ); + Initiator->ScsiStatusCounts.BusyStatus++; + break; + case SCSI_STAT_RESV_CONFLICT: + TI_DBG1( ("itdssIOCompleted: SCSI_STAT_RESV_CONFLICT %d\n", + Initiator->ScsiStatusCounts.ResvConflict) ); + Initiator->ScsiStatusCounts.ResvConflict++; + break; + case SCSI_STAT_TASK_SET_FULL: + Initiator->ScsiStatusCounts.TaskSetFull++; + //agIOStatus = OSSA_IO_FAILED; + //agOtherInfo = tiDetailBusy; + TI_DBG1( ("itdssIOCompleted: SCSI_STAT_TASK_SET_FULL %d\n", + Initiator->ScsiStatusCounts.TaskSetFull) ); + break; + case SCSI_STAT_ACA_ACTIVE: + Initiator->ScsiStatusCounts.AcaActive++; + TI_DBG1( ("itdssIOCompleted: SCSI_STAT_ACA_ACTIVE %d\n", + Initiator->ScsiStatusCounts.AcaActive) ); + break; + case SCSI_STAT_TASK_ABORTED: + Initiator->ScsiStatusCounts.TaskAborted++; + TI_DBG1( ("itdssIOCompleted: SCSI_STAT_TASK_ABORTED %d\n", + Initiator->ScsiStatusCounts.TaskAborted) ); + break; + case SCSI_STAT_CONDITION_MET: + Initiator->ScsiStatusCounts.ConditionMet++; + TI_DBG1( ("itdssIOCompleted: SCSI_STAT_CONDITION_MET %d\n", + Initiator->ScsiStatusCounts.ConditionMet) ); + break; + case SCSI_STAT_INTERMEDIATE: + TI_DBG1( ("itdssIOCompleted: SCSI_STAT_INTERMEDIATE %d\n", + Initiator->ScsiStatusCounts.ObsoleteStatus) ); + Initiator->ScsiStatusCounts.ObsoleteStatus++; + break; + case SCSI_STAT_INTER_CONDIT_MET: + TI_DBG1( ("itdssIOCompleted: SCSI_STAT_INTER_CONDIT_MET %d\n", + Initiator->ScsiStatusCounts.ObsoleteStatus) ); + Initiator->ScsiStatusCounts.ObsoleteStatus++; + break; + case SCSI_STAT_COMMANDTERMINATED: + TI_DBG1( ("itdssIOCompleted: SCSI_STAT_COMMANDTERMINATED %d\n", + Initiator->ScsiStatusCounts.ObsoleteStatus) ); + Initiator->ScsiStatusCounts.ObsoleteStatus++; + break; + default: + Initiator->ScsiStatusCounts.ObsoleteStatus++; + TI_DBG1( ("itdssIOCompleted: Unknown scsi_status %d 0x%x\n", + scsi_status,Initiator->ScsiStatusCounts.ObsoleteStatus) ); + } + + switch (agIOStatus) + { + case OSSA_IO_SUCCESS: + itdssIOSuccessHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_IO_ABORTED: + itdssIOAbortedHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_IO_UNDERFLOW: + itdssIOUnderFlowHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_IO_FAILED: + itdssIOFailedHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_IO_ABORT_RESET: + itdssIOAbortResetHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_IO_NO_DEVICE: + itdssIONoDeviceHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_IO_XFER_ERROR_BREAK: + itdssXferErrorBreakHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_IO_XFER_ERROR_PHY_NOT_READY: + itdssXferErrorPhyNotReadyHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: + itdssOpenCnxErrorProtocolNotSupprotedHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION: + itdssOpenCnxErrorZoneViolationHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_IO_OPEN_CNX_ERROR_BREAK: + itdssOpenCnxErrorBreakHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: + itdssOpenCnxErrorITNexusLossHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION: + itdssOpenCnxErrorBadDestinationHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: + itdssOpenCnxErrorConnectionRateNotSupportedHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION: + itdssOpenCnxErrorWrongDestinationHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_IO_OPEN_CNX_ERROR_UNKNOWN_ERROR: + itdssOpenCnxErrorUnknownErrorHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_IO_XFER_ERROR_NAK_RECEIVED: + itdssXferErrorNAKReceivedHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_IO_XFER_ERROR_ACK_NAK_TIMEOUT: + itdssXferErrorACKNAKTimeoutHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_IO_XFER_ERROR_DMA: + itdssXferErrorDMAHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_IO_XFER_ERROR_OFFSET_MISMATCH: + itdssXferErrorOffsetMismatchHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_IO_XFER_OPEN_RETRY_TIMEOUT: + itdssXferOpenRetryTimeoutHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_IO_PORT_IN_RESET: + itdssPortInResetHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_IO_DS_NON_OPERATIONAL: + itdssDsNonOperationalHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_IO_DS_IN_RECOVERY: + itdssDsInRecoveryHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_IO_TM_TAG_NOT_FOUND: + itdssTmTagNotFoundHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_IO_SSP_EXT_IU_ZERO_LEN_ERROR: + itdssSSPExtIUZeroLenHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_IO_XFER_ERROR_UNEXPECTED_PHASE: + itdssXferErrorUnexpectedPhaseHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; +//new + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: + itdssXferOpenRetryBackoffThresholdReachedHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: + itdssOpenCnxErrorItNexusLossOpenTmoHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: + itdssOpenCnxErrorItNexusLossNoDestHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: + itdssOpenCnxErrorItNexusLossOpenCollideHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: + itdssOpenCnxErrorItNexusLossOpenPathwayBlockedHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + // encryption IO error handling + case OSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS: + case OSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH: + case OSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID: + case OSSA_IO_XFR_ERROR_DEK_IV_MISMATCH: + case OSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR: + case OSSA_IO_XFR_ERROR_INTERNAL_RAM: + case OSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS: + itdssEncryptionHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + + /* DIF IO error handling */ + case OSSA_IO_XFR_ERROR_DIF_MISMATCH: + case OSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH: + case OSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH: + case OSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH: + itdssDifHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE: + itdssIOResourceUnavailableHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_MPI_IO_RQE_BUSY_FULL: + itdssIORQEBusyFullHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_IO_XFR_ERROR_INVALID_SSP_RSP_FRAME: + itdssXferErrorInvalidSSPRspFrameHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_IO_XFER_ERR_EOB_DATA_OVERRUN: + itdssXferErrorEOBDataOverrunHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + case OSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED: + itdssOpenCnxErrorOpenPreemptedHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + default: + TI_DBG1( ("itdssIOCompleted: Unknown agIOStatus 0x%x\n",agIOStatus) ); + itdssIODefaultHandler( agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + agOtherInfo ); + break; + } + } + return; +} + +#ifdef TD_DISCOVER +/***************************************************************************** +*! \brief itdssSMPCompleted +* +* Purpose: This routine is called to complete an SMP request previously +* issued to the LL Layer in saSMPStart(). +* +* \param agRoot: Pointer to driver Instance. +* \param agIORequest: Pointer to the I/O Request data structure for +* this I/O. +* \param agIOStatus: Status of I/O just completed. +* \param agIOInfoLen: Length of the I/O information associated with this +* I/O request +* \param agFrameHandle A Handle used to refer to the response frame +* +* \return: None +* +* \note - This is a initiator specific function called by the jump table. +* +*****************************************************************************/ +osGLOBAL void +itdssSMPCompleted ( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; +#ifdef REMOVED + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&(tdsaRoot->tdsaAllShared); +#endif + tdssSMPRequestBody_t *tdSMPRequestBody; + agsaSASRequestBody_t *agSASRequestBody; + agsaSMPFrame_t *agSMPFrame; + tdsaDeviceData_t *oneDeviceData; + tiIORequest_t *CurrentTaskTag; + tdsaPortContext_t *onePortContext; + tdsaPortContext_t *oldonePortContext; + smpReqPhyControl_t *smpPhyControlReq; + bit8 smpHeader[4]; + tdssSMPFrameHeader_t *tdSMPFrameHeader; + bit8 *tdSMPPayload; + agsaDevHandle_t *agDevHandle; + bit32 status; +#ifndef DIRECT_SMP + tdssSMPFrameHeader_t *tdRequestSMPFrameHeader; + bit8 smpRequestHeader[4]; +#endif + bit8 SMPRequestFunction; + + TI_DBG3(("itdssSMPCompleted: start\n")); + + + tdSMPRequestBody = (tdssSMPRequestBody_t *)agIORequest->osData; + CurrentTaskTag = tdSMPRequestBody->CurrentTaskTag; + + oneDeviceData = tdSMPRequestBody->tdDevice; + onePortContext = oneDeviceData->tdPortContext; + agDevHandle = oneDeviceData->agDevHandle; + + + agSASRequestBody = &(tdSMPRequestBody->agSASRequestBody); + agSMPFrame = &(agSASRequestBody->smpFrame); + +#ifdef DIRECT_SMP + SMPRequestFunction = tdSMPRequestBody->smpPayload[1]; +#else + saFrameReadBlock(agRoot, tdSMPRequestBody->IndirectSMPResp, 0, smpRequestHeader, 4); + tdRequestSMPFrameHeader = (tdssSMPFrameHeader_t *)smpRequestHeader; + SMPRequestFunction = tdRequestSMPFrameHeader->smpFunction; +#endif + + TI_DBG3(("itdssSMPCompleted: agIORequest %p\n", agIORequest)); + TI_DBG3(("itdssSMPCompleted: SMPRequestbody %p\n", tdSMPRequestBody)); + + if (onePortContext != agNULL) + { + TI_DBG3(("itdssSMPCompleted: pid %d\n", onePortContext->id)); + } + else + { + TI_DBG1(("itdssSMPCompleted: Wrong!!! onePortContext is NULL\n")); + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->osMemHandle, + sizeof(tdssSMPRequestBody_t) + ); +#ifndef DIRECT_SMP + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->IndirectSMPReqosMemHandle, + tdSMPRequestBody->IndirectSMPReqLen + ); + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->IndirectSMPResposMemHandle, + tdSMPRequestBody->IndirectSMPRespLen + ); +#endif + return; + } + + oldonePortContext = tdSMPRequestBody->tdPortContext; + if (oldonePortContext != agNULL) + { + TI_DBG3(("itdssSMPCompleted: old pid %d\n", oldonePortContext->id)); + } + else + { + TI_DBG1(("itdssSMPCompleted: Wrong!!! oldonePortContext is NULL\n")); + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->osMemHandle, + sizeof(tdssSMPRequestBody_t) + ); +#ifndef DIRECT_SMP + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->IndirectSMPReqosMemHandle, + tdSMPRequestBody->IndirectSMPReqLen + ); + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->IndirectSMPResposMemHandle, + tdSMPRequestBody->IndirectSMPRespLen + ); +#endif + return; + } + + + /* decrement the number of pending SMP */ + onePortContext->discovery.pendingSMP--; + + /* for port invalid case; + full discovery -> full discovery; incremental discovery -> full discovery + */ + if (onePortContext != oldonePortContext) + { + TI_DBG1(("itdssSMPCompleted: portcontext has changed!!!\n")); + if (SMPRequestFunction == SMP_REPORT_GENERAL || SMPRequestFunction == SMP_DISCOVER || + SMPRequestFunction == SMP_REPORT_PHY_SATA || + SMPRequestFunction == SMP_CONFIGURE_ROUTING_INFORMATION ) + { + /* stop SMP timer */ + if (onePortContext->discovery.DiscoverySMPTimer.timerRunning == agTRUE) + { + tdsaKillTimer( + tiRoot, + &(onePortContext->discovery.DiscoverySMPTimer) + ); + } + if (oldonePortContext->discovery.DiscoverySMPTimer.timerRunning == agTRUE) + { + tdsaKillTimer( + tiRoot, + &(oldonePortContext->discovery.DiscoverySMPTimer) + ); + } + } + + /* clean up expanders data strucures; move to free exp when device is cleaned */ + tdsaCleanAllExp(tiRoot, oldonePortContext); + /* remove devices */ + tdssInternalRemovals(oldonePortContext->agRoot, + oldonePortContext + ); + + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->osMemHandle, + sizeof(tdssSMPRequestBody_t) + ); +#ifndef DIRECT_SMP + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->IndirectSMPReqosMemHandle, + tdSMPRequestBody->IndirectSMPReqLen + ); + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->IndirectSMPResposMemHandle, + tdSMPRequestBody->IndirectSMPRespLen + ); +#endif + return; + } + + if (onePortContext->valid == agFALSE) + { + if (SMPRequestFunction == SMP_REPORT_GENERAL || SMPRequestFunction == SMP_DISCOVER || + SMPRequestFunction == SMP_REPORT_PHY_SATA || + SMPRequestFunction == SMP_CONFIGURE_ROUTING_INFORMATION ) + { + /* stop SMP timer */ + if (onePortContext->discovery.DiscoverySMPTimer.timerRunning == agTRUE) + { + tdsaKillTimer( + tiRoot, + &(onePortContext->discovery.DiscoverySMPTimer) + ); + } + if (oldonePortContext->discovery.DiscoverySMPTimer.timerRunning == agTRUE) + { + tdsaKillTimer( + tiRoot, + &(oldonePortContext->discovery.DiscoverySMPTimer) + ); + } + } + + if (onePortContext->discovery.pendingSMP == 0) + { + TI_DBG1(("itdssSMPCompleted: aborting discovery\n")); + tdsaSASDiscoverAbort(tiRoot, onePortContext); + } + else + { + TI_DBG1(("itdssSMPCompleted: not yet abort; non zero pendingSMP %d\n", onePortContext->discovery.pendingSMP)); + } + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->osMemHandle, + sizeof(tdssSMPRequestBody_t) + ); +#ifndef DIRECT_SMP + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->IndirectSMPReqosMemHandle, + tdSMPRequestBody->IndirectSMPReqLen + ); + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->IndirectSMPResposMemHandle, + tdSMPRequestBody->IndirectSMPRespLen + ); +#endif + return; + } + + + if (SMPRequestFunction == SMP_REPORT_GENERAL || SMPRequestFunction == SMP_DISCOVER || + SMPRequestFunction == SMP_REPORT_PHY_SATA || + SMPRequestFunction == SMP_CONFIGURE_ROUTING_INFORMATION ) + { + /* stop SMP timer */ + if (onePortContext->discovery.DiscoverySMPTimer.timerRunning == agTRUE) + { + tdsaKillTimer( + tiRoot, + &(onePortContext->discovery.DiscoverySMPTimer) + ); + } + if (oldonePortContext->discovery.DiscoverySMPTimer.timerRunning == agTRUE) + { + tdsaKillTimer( + tiRoot, + &(oldonePortContext->discovery.DiscoverySMPTimer) + ); + } + } + + /* the host as of 4/16/08 does not use indirect SMP. So, check only OSSA_IO_SUCCESS status*/ + if (agIOStatus == OSSA_IO_SUCCESS) + { + //tdhexdump("itdssSMPCompleted", (bit8*)agFrameHandle, agIOInfoLen); + /* parsing SMP payload */ +#ifdef DIRECT_SMP + saFrameReadBlock(agRoot, agFrameHandle, 0, smpHeader, 4); +#else + saFrameReadBlock(agRoot, tdSMPRequestBody->IndirectSMPResp, 0, smpHeader, 4); +#endif + tdSMPFrameHeader = (tdssSMPFrameHeader_t *)smpHeader; + + /* SMP function dependent payload */ + switch (tdSMPFrameHeader->smpFunction) + { + case SMP_REPORT_GENERAL: + TI_DBG3(("itdssSMPCompleted: report general\n")); + if (agIOInfoLen != sizeof(smpRespReportGeneral_t) + 4 && + tdSMPFrameHeader->smpFunctionResult == SMP_FUNCTION_ACCEPTED) + { + TI_DBG1(("itdssSMPCompleted: mismatch len agIOInfoLen 0x%x 0x%x\n", agIOInfoLen, (unsigned int)sizeof(smpRespReportGeneral_t) + 4)); + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->osMemHandle, + sizeof(tdssSMPRequestBody_t) + ); +#ifndef DIRECT_SMP + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->IndirectSMPReqosMemHandle, + tdSMPRequestBody->IndirectSMPReqLen + ); + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->IndirectSMPResposMemHandle, + tdSMPRequestBody->IndirectSMPRespLen + ); +#endif + return; + } + tdsaReportGeneralRespRcvd( + tiRoot, + agRoot, + agIORequest, + oneDeviceData, + tdSMPFrameHeader, + agFrameHandle + ); + + break; + case SMP_DISCOVER: + TI_DBG3(("itdssSMPCompleted: discover\n")); + if (agIOInfoLen != sizeof(smpRespDiscover_t) + 4 && + tdSMPFrameHeader->smpFunctionResult == SMP_FUNCTION_ACCEPTED) + { + TI_DBG1(("itdssSMPCompleted: mismatch len agIOInfoLen 0x%x 0x%x\n", agIOInfoLen, (unsigned int)sizeof(smpRespDiscover_t) + 4)); + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->osMemHandle, + sizeof(tdssSMPRequestBody_t) + ); +#ifndef DIRECT_SMP + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->IndirectSMPReqosMemHandle, + tdSMPRequestBody->IndirectSMPReqLen + ); + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->IndirectSMPResposMemHandle, + tdSMPRequestBody->IndirectSMPRespLen + ); +#endif + return; + } + tdsaDiscoverRespRcvd( + tiRoot, + agRoot, + agIORequest, + oneDeviceData, + tdSMPFrameHeader, + agFrameHandle + ); + break; + case SMP_REPORT_PHY_SATA: + TI_DBG3(("itdssSMPCompleted: report phy sata\n")); + if (agIOInfoLen != sizeof(smpRespReportPhySata_t) + 4 && + tdSMPFrameHeader->smpFunctionResult == SMP_FUNCTION_ACCEPTED) + { + TI_DBG1(("itdssSMPCompleted: mismatch len agIOInfoLen 0x%x 0x%x\n", agIOInfoLen, (unsigned int)sizeof(smpRespReportPhySata_t) + 4)); + tdsaSATADiscoverDone(tiRoot, onePortContext, tiError); + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->osMemHandle, + sizeof(tdssSMPRequestBody_t) + ); +#ifndef DIRECT_SMP + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->IndirectSMPReqosMemHandle, + tdSMPRequestBody->IndirectSMPReqLen + ); + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->IndirectSMPResposMemHandle, + tdSMPRequestBody->IndirectSMPRespLen + ); +#endif + return; + } + tdsaReportPhySataRcvd( + tiRoot, + agRoot, + agIORequest, + oneDeviceData, + tdSMPFrameHeader, + agFrameHandle + ); + break; + case SMP_CONFIGURE_ROUTING_INFORMATION: + TI_DBG1(("itdssSMPCompleted: configure routing information\n")); + if (agIOInfoLen != 4 && + tdSMPFrameHeader->smpFunctionResult == SMP_FUNCTION_ACCEPTED) + { + TI_DBG1(("itdssSMPCompleted: mismatch len agIOInfoLen 0x%x 0x%x\n", agIOInfoLen, 4)); + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->osMemHandle, + sizeof(tdssSMPRequestBody_t) + ); +#ifndef DIRECT_SMP + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->IndirectSMPReqosMemHandle, + tdSMPRequestBody->IndirectSMPReqLen + ); + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->IndirectSMPResposMemHandle, + tdSMPRequestBody->IndirectSMPRespLen + ); +#endif + return; + } + tdsaConfigRoutingInfoRespRcvd( + tiRoot, + agRoot, + agIORequest, + oneDeviceData, + tdSMPFrameHeader, + agFrameHandle + ); + + break; + case SMP_PHY_CONTROL: + TI_DBG3(("itdssSMPCompleted: phy control\n")); + if (agIOInfoLen != 4 && + tdSMPFrameHeader->smpFunctionResult == SMP_FUNCTION_ACCEPTED) /*zero length is expected */ + { + TI_DBG1(("itdssSMPCompleted: mismatch len agIOInfoLen 0x%x 0x%x\n", agIOInfoLen, 4)); + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->osMemHandle, + sizeof(tdssSMPRequestBody_t) + ); +#ifndef DIRECT_SMP + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->IndirectSMPReqosMemHandle, + tdSMPRequestBody->IndirectSMPReqLen + ); + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->IndirectSMPResposMemHandle, + tdSMPRequestBody->IndirectSMPRespLen + ); +#endif + return; + } + tdsaPhyControlRespRcvd( + tiRoot, + agRoot, + agIORequest, + oneDeviceData, + tdSMPFrameHeader, + agFrameHandle, + CurrentTaskTag + ); + + break; +#ifdef REMOVED +//temp for testing + case SMP_REPORT_MANUFACTURE_INFORMATION: + TI_DBG1(("itdssSMPCompleted: REPORT_MANUFACTURE_INFORMATION\n")); + if (agIOInfoLen != sizeof(smpRespReportManufactureInfo_t) + 4 && + tdSMPFrameHeader->smpFunctionResult == SMP_FUNCTION_ACCEPTED) /*zero length is expected */ + { + TI_DBG1(("itdssSMPCompleted: mismatch len agIOInfoLen 0x%x 0x%x\n", agIOInfoLen, 4)); + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->osMemHandle, + sizeof(tdssSMPRequestBody_t) + ); +#ifndef DIRECT_SMP + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->IndirectSMPReqosMemHandle, + tdSMPRequestBody->IndirectSMPReqLen + ); + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->IndirectSMPResposMemHandle, + tdSMPRequestBody->IndirectSMPRespLen + ); +#endif + return; + } + tdsaReportManInfoRespRcvd( + tiRoot, + agRoot, + oneDeviceData, + tdSMPFrameHeader, + agFrameHandle + ); + + break; +//end temp for testing +#endif + case SMP_REPORT_ROUTING_INFORMATION: + case SMP_REPORT_PHY_ERROR_LOG: + case SMP_PHY_TEST_FUNCTION: + case SMP_REPORT_MANUFACTURE_INFORMATION: + case SMP_READ_GPIO_REGISTER: + case SMP_WRITE_GPIO_REGISTER: + default: + TI_DBG1(("itdssSMPCompleted: wrong SMP function 0x%x\n", tdSMPFrameHeader->smpFunction)); + TI_DBG1(("itdssSMPCompleted: smpFrameType 0x%x\n", tdSMPFrameHeader->smpFrameType)); + TI_DBG1(("itdssSMPCompleted: smpFunctionResult 0x%x\n", tdSMPFrameHeader->smpFunctionResult)); + TI_DBG1(("itdssSMPCompleted: smpReserved 0x%x\n", tdSMPFrameHeader->smpReserved)); + tdhexdump("itdssSMPCompleted: SMP payload", (bit8 *)agFrameHandle, agIOInfoLen); + break; + } + } + else if (agIOStatus == OSSA_IO_ABORTED || agIOStatus == OSSA_IO_INVALID_LENGTH) + { + /* no retry this case */ + TI_DBG1(("itdssSMPCompleted: OSSA_IO_ABORTED\n")); + } + else if (agIOStatus == OSSA_IO_ERROR_INTERNAL_SMP_RESOURCE) + { + TI_DBG1(("itdssSMPCompleted: OSSA_IO_ERROR_INTERNAL_SMP_RESOURCE\n")); + saFrameReadBlock(agRoot, agFrameHandle, 0, smpHeader, 4); + tdSMPFrameHeader = (tdssSMPFrameHeader_t *)smpHeader; + + status = saSMPStart( + agRoot, + agIORequest, + tdSMPRequestBody->queueNumber, //tdsaAllShared->SMPQNum, //tdsaRotateQnumber(tiRoot, oneDeviceData), + agDevHandle, + AGSA_SMP_INIT_REQ, + agSASRequestBody, + &ossaSMPCompleted + ); + + if (status == AGSA_RC_SUCCESS) + { + /* increment the number of pending SMP */ + onePortContext->discovery.pendingSMP++; + if (SMPRequestFunction == SMP_REPORT_GENERAL || SMPRequestFunction == SMP_DISCOVER || + SMPRequestFunction == SMP_REPORT_PHY_SATA || + SMPRequestFunction == SMP_CONFIGURE_ROUTING_INFORMATION ) + { + /* start discovery-related SMP timer */ + tdsaDiscoverySMPTimer(tiRoot, onePortContext, (bit32)(tdSMPFrameHeader->smpFunction), tdSMPRequestBody); + } + return; + } + else if (status == AGSA_RC_BUSY) + { + if (tdSMPFrameHeader->smpFunction == SMP_REPORT_GENERAL || + tdSMPFrameHeader->smpFunction == SMP_DISCOVER || + tdSMPFrameHeader->smpFunction == SMP_REPORT_PHY_SATA || + tdSMPFrameHeader->smpFunction == SMP_CONFIGURE_ROUTING_INFORMATION ) + { + tdsaSMPBusyTimer(tiRoot, onePortContext, oneDeviceData, tdSMPRequestBody); + } + else if (tdSMPFrameHeader->smpFunction == SMP_PHY_CONTROL) + { + /* For taskmanagement SMP, let's fail task management failure */ + tdsaPhyControlFailureRespRcvd( + tiRoot, + agRoot, + oneDeviceData, + tdSMPFrameHeader, + agFrameHandle, + CurrentTaskTag + ); + } + else + { + } + } + else /* AGSA_RC_FAILURE */ + { + if (tdSMPFrameHeader->smpFunction == SMP_REPORT_GENERAL || + tdSMPFrameHeader->smpFunction == SMP_DISCOVER || + tdSMPFrameHeader->smpFunction == SMP_REPORT_PHY_SATA || + tdSMPFrameHeader->smpFunction == SMP_CONFIGURE_ROUTING_INFORMATION ) + { + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + } + else if (tdSMPFrameHeader->smpFunction == SMP_PHY_CONTROL) + { + /* task management failure */ + tdsaPhyControlFailureRespRcvd( + tiRoot, + agRoot, + oneDeviceData, + tdSMPFrameHeader, + agFrameHandle, + CurrentTaskTag + ); + } + else + { + } + } + } + else + { + if (tdSMPRequestBody->retries < SMP_RETRIES) /* 5 */ + { + /* retry the SMP again */ + TI_DBG1(("itdssSMPCompleted: failed! but retries %d agIOStatus 0x%x %d agIOInfoLen %d\n", + tdSMPRequestBody->retries, agIOStatus, agIOStatus, agIOInfoLen)); + if (agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED || + agIOStatus == OSSA_IO_DS_NON_OPERATIONAL + ) + { + saSetDeviceState(agRoot, agNULL, tdSMPRequestBody->queueNumber, agDevHandle, SA_DS_OPERATIONAL); + } + saSMPStart( + agRoot, + agIORequest, + tdSMPRequestBody->queueNumber, //tdsaAllShared->SMPQNum, //tdsaRotateQnumber(tiRoot, oneDeviceData), + agDevHandle, + AGSA_SMP_INIT_REQ, + agSASRequestBody, + &ossaSMPCompleted + ); + /* increment the number of pending SMP */ + onePortContext->discovery.pendingSMP++; + tdSMPRequestBody->retries++; + return; + } + else + { + tdSMPFrameHeader = (tdssSMPFrameHeader_t *)agSMPFrame->outFrameBuf; + tdSMPPayload = (bit8 *)agSMPFrame->outFrameBuf + 4; + TI_DBG1(("itdssSMPCompleted: failed! no more retry! agIOStatus 0x%x %d\n", agIOStatus, agIOStatus)); + if (agIOStatus == OSSA_IO_DS_NON_OPERATIONAL) + { + TI_DBG1(("itdssSMPCompleted: failed! agIOStatus is OSSA_IO_DS_NON_OPERATIONAL\n")); + } + + if (agIOStatus == OSSA_IO_DS_IN_RECOVERY) + { + TI_DBG1(("itdssSMPCompleted: failed! agIOStatus is OSSA_IO_DS_IN_RECOVERY\n")); + } + + if (tdSMPFrameHeader->smpFunction == SMP_REPORT_GENERAL || + tdSMPFrameHeader->smpFunction == SMP_DISCOVER || + tdSMPFrameHeader->smpFunction == SMP_REPORT_PHY_SATA || + tdSMPFrameHeader->smpFunction == SMP_CONFIGURE_ROUTING_INFORMATION + ) + { + /* discovery failure */ + TI_DBG1(("itdssSMPCompleted: SMP function 0x%x\n", tdSMPFrameHeader->smpFunction)); + TI_DBG1(("itdssSMPCompleted: discover done with error\n")); + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + } + else if (tdSMPFrameHeader->smpFunction == SMP_PHY_CONTROL) + { + TI_DBG1(("itdssSMPCompleted: SMP_PHY_CONTROL\n")); + smpPhyControlReq = (smpReqPhyControl_t *)tdSMPPayload; + if (smpPhyControlReq->phyOperation == SMP_PHY_CONTROL_CLEAR_AFFILIATION) + { + TI_DBG1(("itdssSMPCompleted: discover done with error\n")); + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + } + else if (smpPhyControlReq->phyOperation == SMP_PHY_CONTROL_HARD_RESET || + smpPhyControlReq->phyOperation == SMP_PHY_CONTROL_LINK_RESET ) + { + TI_DBG1(("itdssSMPCompleted: device reset failed\n")); + if (CurrentTaskTag != agNULL ) + { + TI_DBG1(("itdssSMPCompleted: callback to OS layer with failure\n")); + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMFailed, + CurrentTaskTag ); + } + else + { + /* hard reset was not done with this device */ + oneDeviceData->ResetCnt = 0; + } + } + else + { + TI_DBG1(("itdssSMPCompleted: unknown phy operation 0x%x\n", smpPhyControlReq->phyOperation)); + } + } /* SMP_PHY_CONTROL */ + else + { + TI_DBG1(("itdssSMPCompleted: SMP function 0x%x\n", tdSMPFrameHeader->smpFunction)); + } + } /* else */ + } /* outer else */ + + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->osMemHandle, + sizeof(tdssSMPRequestBody_t) + ); +#ifndef DIRECT_SMP + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->IndirectSMPReqosMemHandle, + tdSMPRequestBody->IndirectSMPReqLen + ); + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->IndirectSMPResposMemHandle, + tdSMPRequestBody->IndirectSMPRespLen + ); +#endif + + + return; +} + +#else + +osGLOBAL void +itdssSMPCompleted ( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle + ) +{ + /* pass the payload to OS layer */ + TI_DBG3(("itdssSMPCompleted: start\n")); +} +#endif + + +/***************************************************************************** +*! \brief itdIoSuccessHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_SUCCESS +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssIOSuccessHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + itdsaIni_t *Initiator = (itdsaIni_t *)osData->itdsaIni; + tdIORequestBody_t *tdIORequestBody; + agsaSSPResponseInfoUnit_t agSSPRespIU; + tiSenseData_t senseData; + bit8 senseDataPayload[256]; + bit8 respData[128]; + bit32 scsi_status; + bit32 senseLen; + bit32 respLen; + bit32 data_status; + bit32 i; + tiDeviceHandle_t *tiDeviceHandle = agNULL; + tdsaDeviceData_t *oneDeviceData = agNULL; + + TI_DBG2(("itdssIOSuccessHandler: start\n")); + TI_DBG2(("itdssIOSuccessHandler: agIOInfoLen %d\n", agIOInfoLen)); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + /* + agIOInfoLen must be >= sizeof(agsaSSPResponseInfoUnit_t), which is minimum + date length + */ + if (agIOInfoLen < sizeof(agsaSSPResponseInfoUnit_t)) + { + TI_DBG1(("itdssIOSuccessHandler: First agIOInfoLen does not match!!!\n")); + TI_DBG1(("itdssIOSuccessHandler: First agIOInfoLen 0x%x IU 0x%x\n", agIOInfoLen, (unsigned int)sizeof(agsaSSPResponseInfoUnit_t))); + ostiInitiatorIOCompleted( + tiRoot, + tdIORequestBody->tiIORequest, /* tiIORequest */ + tiIOFailed, + tiDetailOtherError, + agNULL, + agTRUE /* intContext; is not being used */ + ); + return; + } + /* reads agsaSSPResponseInfoUnit_t */ + saFrameReadBlock(agRoot, agParam, 0, &agSSPRespIU, sizeof(agsaSSPResponseInfoUnit_t)); + + data_status = SA_SSPRESP_GET_DATAPRES(&agSSPRespIU); + scsi_status = agSSPRespIU.status; + /* endianess is invovled here */ + senseLen = SA_SSPRESP_GET_SENSEDATALEN(&agSSPRespIU); + respLen = SA_SSPRESP_GET_RESPONSEDATALEN(&agSSPRespIU); + + TI_DBG2(("itdssIOSuccessHandler: dataPres=%x\n", data_status)); + TI_DBG2(("itdssIOSuccessHandler: scsi status=0x%x, senselen=0x%x resplen 0x%x\n", scsi_status, senseLen, respLen)); + + /* + sanity check: do not go beyond of agIOInfoLen. if happens, return error + agIOInfoLen >= sizeof(agsaSSPResponseInfoUnit_t) + senseLen + respLen -> OK + because frame must be divisible by 4, so there can be extra padding + agIOInfoLen < sizeof(agsaSSPResponseInfoUnit_t) + senseLen + respLen -> NOT OK + */ + if (agIOInfoLen < sizeof(agsaSSPResponseInfoUnit_t) + senseLen + respLen) + { + TI_DBG1(("itdssIOSuccessHandler: Second agIOInfoLen does not match!!!\n")); + TI_DBG1(("itdssIOSuccessHandler: Second agIOInfoLen 0x%x IU 0x%x senselen 0x%x resplen 0x%x\n", agIOInfoLen, (unsigned int)sizeof(agsaSSPResponseInfoUnit_t), senseLen, respLen)); + + ostiInitiatorIOCompleted( + tiRoot, + tdIORequestBody->tiIORequest, /* tiIORequest */ + tiIOFailed, + tiDetailOtherError, + agNULL, + agTRUE /* intContext; is not being used */ + ); + return; + } + + /* reads response data */ + saFrameReadBlock(agRoot, agParam, + sizeof(agsaSSPResponseInfoUnit_t), + respData, respLen); + /* reads sense data */ + saFrameReadBlock(agRoot, agParam, + sizeof(agsaSSPResponseInfoUnit_t) + + respLen, + senseDataPayload, senseLen); + + if (data_status == 0) + { + /* NO_DATA */ + TI_DBG1(("itdssIOSuccessHandler: no data scsi_status 0x%x\n",scsi_status)); + + ostiInitiatorIOCompleted( + tiRoot, + tdIORequestBody->tiIORequest, /* tiIORequest */ + tiIOSuccess, + scsi_status, + agNULL, + agTRUE /* intContext; is not being used */ + ); + + return; + } + + if (data_status == 1) + { + /* RESPONSE_DATA */ + TI_DBG1(("itdssIOSuccessHandler: response data \n")); + + ostiInitiatorIOCompleted( + tiRoot, + tdIORequestBody->tiIORequest, /* tiIORequest */ + tiIOSuccess, + 0, + agNULL, + agTRUE /* intContext; is not being used */ + ); + return; + } + + if (data_status == 2) + { + /* SENSE_DATA */ + TI_DBG2(("itdssIOSuccessHandler: sense data \n")); + + senseData.senseData = &senseDataPayload; + senseData.senseLen = MIN(256, senseLen); + /* debugging */ + tdhexdump("ResponseIU I", (bit8 *)&agSSPRespIU, sizeof(agsaSSPResponseInfoUnit_t)); + + tiDeviceHandle = tdIORequestBody->tiDevHandle; + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + TI_DBG1(("sense data Sense Key 0x%2X ASC(Code) 0x%2X ASCQ(Qualifier) 0x%2X, did 0x%x\n",*(senseDataPayload+ 2),*(senseDataPayload + 12),*(senseDataPayload + 13), + oneDeviceData->id)); + tdhexdump("sense data I", (bit8 *)senseDataPayload, senseLen); +// tdhexdump("sense data II", (bit8 *)senseData.senseData, senseData.senseLen); + + if (senseDataPayload[2] == SCSI_SENSE_KEY_RECOVERED_ERROR) + { + Initiator->SenseKeyCounter.SoftError ++; + } + else if (senseDataPayload[2] == SCSI_SENSE_KEY_NOT_READY) + { + Initiator->SenseKeyCounter.MediumNotReady++; + } + else if (senseDataPayload[2] == SCSI_SENSE_KEY_MEDIUM_ERROR) + { + Initiator->SenseKeyCounter.MediumError++; + } + else if (senseDataPayload[2] == SCSI_SENSE_KEY_HARDWARE_ERROR) + { + Initiator->SenseKeyCounter.HardwareError++; + } + else if (senseDataPayload[2] == SCSI_SENSE_KEY_ILLEGAL_REQUEST) + { + Initiator->SenseKeyCounter.IllegalRequest++; + } + else if (senseDataPayload[2] == SCSI_SENSE_KEY_UNIT_ATTENTION) + { + Initiator->SenseKeyCounter.UnitAttention++; + } + else if (senseDataPayload[2] == SCSI_SENSE_KEY_ABORTED_COMMAND) + { + Initiator->SenseKeyCounter.AbortCommand++; + } + else + { + Initiator->SenseKeyCounter.OtherKeyType++; + } + + /* when ASQ and ASCQ 0x04 0x11, does saLocalPhyControl for notify spinup */ + if ((senseDataPayload[12] == 0x04 && senseDataPayload[13] == 0x11)) + { + TI_DBG2(("itdssIOSuccessHandler: sending notfify spinup\n")); + tiDeviceHandle = tdIORequestBody->tiDevHandle; + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + if (oneDeviceData->directlyAttached == agTRUE) + { + for (i=0;iphyID, AGSA_PHY_NOTIFY_ENABLE_SPINUP, agNULL); + } + } + } + ostiInitiatorIOCompleted( + tiRoot, + /* tiIORequest */ + tdIORequestBody->tiIORequest, + tiIOSuccess, + scsi_status, + &senseData, + agTRUE /* intContext; is not being used */ + ); + return; + } + if (data_status == 3) + { + /* RESERVED */ + TI_DBG1(("itdssIOSuccessHandler: reserved wrong!!!\n")); + ostiInitiatorIOCompleted( + tiRoot, + tdIORequestBody->tiIORequest, /* tiIORequest */ + tiIOFailed, + scsi_status, + agNULL, + agTRUE /* intContext; is not being used */ + ); + return; + } + +} + +/***************************************************************************** +*! \brief itdssIOAbortedHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_ABORTED +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +/* see itdosIOCompleted() and itdinit.c and itdIoAbortedHandler in itdio.c*/ +osGLOBAL void +itdssIOAbortedHandler ( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + tiDeviceHandle_t *tiDeviceHandle = agNULL; + tdsaDeviceData_t *oneDeviceData = agNULL; + + TI_DBG2(("itdssIOAbortedHandler: start\n")); + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + if (agIOStatus != OSSA_IO_ABORTED) + { + TI_DBG1(("itdssIOAbortedHandler: incorrect agIOStatus 0x%x\n", agIOStatus)); + } + + if (tdIORequestBody == agNULL) + { + TI_DBG1(("itdssIOAbortedHandler: start\n")); + return; + } + + if (tdIORequestBody != agNULL) + { + tiDeviceHandle = tdIORequestBody->tiDevHandle; + } + if (tiDeviceHandle != agNULL) + { + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + } + if (oneDeviceData != agNULL) + { + TI_DBG2(("itdssIOAbortedHandler: did %d \n", oneDeviceData->id)); + } + else + { + TI_DBG1(("itdssIOAbortedHandler: oneDeviceData is NULL\n")); + } + + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailAborted, + agNULL, + intContext + ); + + return; +} + +#ifdef REMOVED +/***************************************************************************** +*! \brief itdssIOOverFlowHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_OVERFLOW +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssIOOverFlowHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + + TI_DBG2(("itdssIOOverFlowHandler: start\n")); + TI_DBG2(("itdssIOOverFlowHandler: not transferred byte 0x%x\n", agIOInfoLen)); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOOverRun, + agIOInfoLen, + agNULL, + intContext + ); + + return; +} +#endif + + +/***************************************************************************** +*! \brief itdssIOUnderFlowHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_UNDERFLOW +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssIOUnderFlowHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + + TI_DBG6(("itdssIOUnderFlowHandler: start\n")); + TI_DBG6(("itdssIOUnderFlowHandler: agIOInfoLen 0x%x\n", agIOInfoLen)); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOUnderRun, + agIOInfoLen, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssIOFailedHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_FAILED +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssIOFailedHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + + TI_DBG1(("itdssIOFailedHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + return; +} + +/***************************************************************************** +*! \brief itdssIOAbortResetHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_ABORT_RESET +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssIOAbortResetHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG2(("itdssIOAbortResetHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailAbortReset, + agNULL, + intContext + ); + + + return; +} + +/***************************************************************************** +*! \brief itdssIONotValidHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_NOT_VALID +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssIONotValidHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG2(("itdssIONotValidHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailNotValid, + agNULL, + intContext + ); + return; +} + +/***************************************************************************** +*! \brief itdssIONoDeviceHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_NO_DEVICE +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssIONoDeviceHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG2(("itdssIONoDeviceHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailNoLogin, + agNULL, + intContext + ); + return; +} + +#ifdef REMOVED /* to do: removed from spec */ +/***************************************************************************** +*! \brief itdssIllegalParameterHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_ILLEGAL_PARAMETER +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssIllegalParameterHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG2(("itdssIllegalParameterHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} +#endif + +/***************************************************************************** +*! \brief itdssLinkFailureHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_LINK_FAILURE +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssLinkFailureHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG1(("itdssLinkFailureHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssProgErrorHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_PROG_ERROR +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssProgErrorHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG2(("itdssProgErrorHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssXferErrorBreakHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_XFER_ERROR_BREAK +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssXferErrorBreakHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG1(("itdssXferErrorBreakHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssXferErrorPhyNotReadyHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_XFER_ERROR_PHY_NOT_READY +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssXferErrorPhyNotReadyHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG2(("itdssXferErrorPhyNotReadyHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssOpenCnxErrorProtocolNotSupprotedHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssOpenCnxErrorProtocolNotSupprotedHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG2(("itdssOpenCnxErrorProtocolNotSupprotedHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssOpenCnxErrorZoneViolationHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssOpenCnxErrorZoneViolationHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG2(("itdssOpenCnxErrorZoneViolationHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssOpenCnxErrorBreakHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_OPEN_CNX_ERROR_BREAK +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssOpenCnxErrorBreakHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG1(("itdssOpenCnxErrorBreakHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssOpenCnxErrorITNexusLossHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssOpenCnxErrorITNexusLossHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG1(("itdssOpenCnxErrorITNexusLossHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssOpenCnxErrorBadDestinationHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssOpenCnxErrorBadDestinationHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG1(("itdssOpenCnxErrorBadDestinationHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssOpenCnxErrorConnectionRateNotSupportedHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssOpenCnxErrorConnectionRateNotSupportedHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + agsaDevHandle_t *agDevHandle = agNULL; + tiDeviceHandle_t *tiDeviceHandle = agNULL; + tdsaDeviceData_t *oneDeviceData = agNULL; + bit32 ConnRate = SAS_CONNECTION_RATE_12_0G; + agsaContext_t *agContext = agNULL; + TI_DBG1(("itdssOpenCnxErrorConnectionRateNotSupportedHandler: start\n")); + + /* we retry by lowering link rate + retry should be in ossaSetDeviceInfoCB() + */ + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + tiDeviceHandle = tdIORequestBody->tiDevHandle; + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + agDevHandle = oneDeviceData->agDevHandle; + + if (tdsaAllShared->RateAdjust) + { + if (oneDeviceData->valid == agTRUE && oneDeviceData->registered == agTRUE && + oneDeviceData->tdPortContext != agNULL ) + { + ConnRate = DEVINFO_GET_LINKRATE(&oneDeviceData->agDeviceInfo); + if (ConnRate == SAS_CONNECTION_RATE_1_5G) + { + /* no retry; completes IO */ + ostiInitiatorIOCompleted( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + } + else + { + ConnRate = ConnRate - 1; + } + agContext = &(tdIORequestBody->agContext); + agContext->osData = agIORequest; + saSetDeviceInfo(agRoot, agContext, tdsaRotateQnumber(tiRoot, oneDeviceData), agDevHandle, 32, ConnRate << 28, ossaIniSetDeviceInfoCB); + } + } + else + { + ostiInitiatorIOCompleted( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + } + + return; +} + +/***************************************************************************** +*! \brief itdssOpenCnxErrorSTPResourceBusyHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssOpenCnxErrorSTPResourceBusyHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG2(("itdssOpenCnxErrorSTPResourceBusyHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssOpenCnxErrorWrongDestinationHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssOpenCnxErrorWrongDestinationHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG1(("itdssOpenCnxErrorWrongDestinationHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssOpenCnxErrorUnknownErrorHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_OPEN_CNX_ERROR_UNKNOWN_ERROR +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssOpenCnxErrorUnknownErrorHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG1(("itdssOpenCnxErrorUnknownErrorHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssXferErrorNAKReceivedHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_XFER_ERROR_NAK_RECEIVED +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssXferErrorNAKReceivedHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG1(("itdssXferErrorNAKReceivedHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssXferErrorACKNAKTimeoutHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_XFER_ERROR_ACK_NAK_TIMEOUT +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssXferErrorACKNAKTimeoutHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG1(("itdssXferErrorACKNAKTimeoutHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssXferErrorPeerAbortedHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_XFER_ERROR_PEER_ABORTED +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssXferErrorPeerAbortedHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG2(("itdssXferErrorPeerAbortedHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssXferErrorRxFrameHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_XFER_ERROR_RX_FRAME +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssXferErrorRxFrameHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG1(("itdssXferErrorRxFrameHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssXferErrorDMAHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_XFER_ERROR_DMA +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssXferErrorDMAHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG1(("itdssXferErrorDMAHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherErrorNoRetry, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssXferErrorCreditTimeoutHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_XFER_ERROR_CREDIT_TIMEOUT +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssXferErrorCreditTimeoutHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG1(("itdssXferErrorCreditTimeoutHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssXferErrorCMDIssueACKNAKTimeoutHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssXferErrorCMDIssueACKNAKTimeoutHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG1(("itdssXferErrorCMDIssueACKNAKTimeoutHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssXferErrorCMDIssueBreakBeforeACKNAKHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssXferErrorCMDIssueBreakBeforeACKNAKHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG1(("itdssXferErrorCMDIssueBreakBeforeACKNAKHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssXferErrorCMDIssuePhyDownBeforeACKNAKHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssXferErrorCMDIssuePhyDownBeforeACKNAKHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG1(("itdssXferErrorCMDIssuePhyDownBeforeACKNAKHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssXferErrorDisruptedPhyDownHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_XFER_ERROR_DISRUPTED_PHY_DOWN +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssXferErrorDisruptedPhyDownHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG2(("itdssXferErrorDisruptedPhyDownHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssXferErrorOffsetMismatchHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_XFER_ERROR_OFFSET_MISMATCH +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssXferErrorOffsetMismatchHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG1(("itdssXferErrorOffsetMismatchHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssXferErrorXferZeroDataLenHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_XFER_ERROR_XFER_ZERO_DATA_LEN +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssXferErrorXferZeroDataLenHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG2(("itdssXferErrorXferZeroDataLenHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssXferOpenRetryTimeoutHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_XFER_OPEN_RETRY_TIMEOUT +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssXferOpenRetryTimeoutHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + itdsaIni_t *Initiator = (itdsaIni_t *)tdsaAllShared->itdsaIni; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + agsaDevHandle_t *agDevHandle = agNULL; + tiDeviceHandle_t *tiDeviceHandle = agNULL; + tdsaDeviceData_t *oneDeviceData = agNULL; + bit32 saStatus = AGSA_RC_FAILURE; + + TI_DBG2(("itdssXferOpenRetryTimeoutHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + tiDeviceHandle = tdIORequestBody->tiDevHandle; + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + agDevHandle = oneDeviceData->agDevHandle; + + if (oneDeviceData->valid == agTRUE && oneDeviceData->registered == agTRUE && + oneDeviceData->tdPortContext != agNULL ) + { + if (tdIORequestBody->reTries < OPEN_RETRY_RETRIES) /* 10 */ + { + saStatus = saSSPStart(agRoot, + agIORequest, + tdsaRotateQnumber(tiRoot, oneDeviceData), + agDevHandle, + tdIORequestBody->agRequestType, + &(tdIORequestBody->transport.SAS.agSASRequestBody), + agNULL, + &ossaSSPCompleted); + + if (saStatus == AGSA_RC_SUCCESS) + { + TI_DBG2(("itdssXferOpenRetryTimeoutHandler: retried\n")); + Initiator->NumIOsActive++; + tdIORequestBody->ioStarted = agTRUE; + tdIORequestBody->ioCompleted = agFALSE; + tdIORequestBody->reTries++; + return; + } + else + { + TI_DBG1(("itdssXferOpenRetryTimeoutHandler: retry failed\n")); + tdIORequestBody->ioStarted = agFALSE; + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->reTries = 0; + } + } + else + { + TI_DBG1(("itdssXferOpenRetryTimeoutHandler: retry is over and fail\n")); + tdIORequestBody->reTries = 0; + } + } + else + { + TI_DBG1(("itdssXferOpenRetryTimeoutHandler: not valid deivce no retry\n")); + tdIORequestBody->reTries = 0; + } + ostiInitiatorIOCompleted( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + return; +} + +/***************************************************************************** +*! \brief itdssPortInResetHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_PORT_IN_RESET +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssPortInResetHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG2(("itdssPortInResetHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssDsNonOperationalHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_DS_NON_OPERATIONAL +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssDsNonOperationalHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + agsaDevHandle_t *agDevHandle = agNULL; + tiDeviceHandle_t *tiDeviceHandle = agNULL; + tdsaDeviceData_t *oneDeviceData = agNULL; + + + TI_DBG2(("itdssDsNonOperationalHandler: start\n")); + + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + +#if 1 /* TBD */ + /* let's do it only once ????? */ + tiDeviceHandle = tdIORequestBody->tiDevHandle; + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + agDevHandle = oneDeviceData->agDevHandle; + if (oneDeviceData->valid == agTRUE && oneDeviceData->registered == agTRUE && + oneDeviceData->tdPortContext != agNULL ) + { + saSetDeviceState(agRoot, agNULL, tdsaRotateQnumber(tiRoot, oneDeviceData), agDevHandle, SA_DS_OPERATIONAL); + } +#endif + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssDsInRecoveryHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_DS_IN_RECOVERY +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssDsInRecoveryHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG2(("itdssDsInRecoveryHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssTmTagNotFoundHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_TM_TAG_NOT_FOUND +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssTmTagNotFoundHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG2(("itdssTmTagNotFoundHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssSSPExtIUZeroLenHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_SSP_EXT_IU_ZERO_LEN_ERROR +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssSSPExtIUZeroLenHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG2(("itdssSSPExtIUZeroLenHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssXferErrorUnexpectedPhaseHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_XFER_ERROR_UNEXPECTED_PHASE +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssXferErrorUnexpectedPhaseHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG2(("itdssXferErrorUnexpectedPhaseHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} + +#ifdef REMOVED +/***************************************************************************** +*! \brief itdssIOUnderFlowWithChkConditionHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_UNDERFLOW_WITH_CHK_COND +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \return: None +* +* +*****************************************************************************/ +/* + How to report SCSI_STAT_CHECK_CONDITION and tiIOUnderRun simultaneoulsy??? + ostiInitiatorIOCompleted( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + &senseData, + agTRUE + ); + + vs + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOUnderRun, + agIOInfoLen, + agNULL, + intContext + ); + + For now, SCSI_STAT_CHECK_CONDITION is reported until TISA changes (as of 1/6/09) + In other words, this handler is the practically same as itdssIOSuccessHandler() +*/ +osGLOBAL void +itdssIOUnderFlowWithChkConditionHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdIORequestBody_t *tdIORequestBody; + agsaSSPResponseInfoUnit_t agSSPRespIU; + tiSenseData_t senseData; + bit8 senseDataPayload[256]; + bit8 respData[128]; + bit32 scsi_status; + bit32 senseLen; + bit32 respLen; + bit32 data_status; + bit32 i; + tiDeviceHandle_t *tiDeviceHandle = agNULL; + tdsaDeviceData_t *oneDeviceData = agNULL; + + TI_DBG2(("itdssIOUnderFlowWithChkConditionHandler: start\n")); + TI_DBG2(("itdssIOUnderFlowWithChkConditionHandler: agIOInfoLen 0x%x\n", agIOInfoLen)); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + /* + agIOInfoLen must be >= sizeof(agsaSSPResponseInfoUnit_t), which is minimum + date length + */ + if (agIOInfoLen < sizeof(agsaSSPResponseInfoUnit_t)) + { + TI_DBG1(("itdssIOUnderFlowWithChkConditionHandler: First agIOInfoLen does not match!!!\n")); + TI_DBG1(("itdssIOUnderFlowWithChkConditionHandler: First agIOInfoLen 0x%x IU 0x%x\n", agIOInfoLen, (unsigned int)sizeof(agsaSSPResponseInfoUnit_t))); + ostiInitiatorIOCompleted( + tiRoot, + tdIORequestBody->tiIORequest, /* tiIORequest */ + tiIOFailed, + tiDetailOtherError, + agNULL, + agTRUE /* intContext; is not being used */ + ); + return; + } + /* reads agsaSSPResponseInfoUnit_t */ + saFrameReadBlock(agRoot, agParam, 0, &agSSPRespIU, sizeof(agsaSSPResponseInfoUnit_t)); + + data_status = SA_SSPRESP_GET_DATAPRES(&agSSPRespIU); + scsi_status = agSSPRespIU.status; + /* endianess is invovled here */ + senseLen = SA_SSPRESP_GET_SENSEDATALEN(&agSSPRespIU); + respLen = SA_SSPRESP_GET_RESPONSEDATALEN(&agSSPRespIU); + + TI_DBG2(("itdssIOUnderFlowWithChkConditionHandler: dataPres=%x\n", data_status)); + TI_DBG2(("itdssIOUnderFlowWithChkConditionHandler: scsi status=0x%x, senselen=0x%x resplen 0x%x\n", scsi_status, senseLen, respLen)); + + /* + sanity check: do not go beyond of agIOInfoLen. if happens, return error + agIOInfoLen >= sizeof(agsaSSPResponseInfoUnit_t) + senseLen + respLen -> OK + because frame must be divisible by 4, so there can be extra padding + agIOInfoLen < sizeof(agsaSSPResponseInfoUnit_t) + senseLen + respLen -> NOT OK + */ + if (agIOInfoLen < sizeof(agsaSSPResponseInfoUnit_t) + senseLen + respLen) + { + TI_DBG1(("itdssIOUnderFlowWithChkConditionHandler: Second agIOInfoLen does not match!!!\n")); + TI_DBG1(("itdssIOUnderFlowWithChkConditionHandler: Second agIOInfoLen 0x%x IU 0x%x senselen 0x%x resplen 0x%x\n", agIOInfoLen, (unsigned int)sizeof(agsaSSPResponseInfoUnit_t), senseLen, respLen)); + + ostiInitiatorIOCompleted( + tiRoot, + tdIORequestBody->tiIORequest, /* tiIORequest */ + tiIOFailed, + tiDetailOtherError, + agNULL, + agTRUE /* intContext; is not being used */ + ); + return; + } + + /* reads response data */ + saFrameReadBlock(agRoot, agParam, + sizeof(agsaSSPResponseInfoUnit_t), + respData, respLen); + /* reads sense data */ + saFrameReadBlock(agRoot, agParam, + sizeof(agsaSSPResponseInfoUnit_t) + + respLen, + senseDataPayload, senseLen); + + if (data_status == 0) + { + /* NO_DATA */ + TI_DBG2(("itdssIOUnderFlowWithChkConditionHandler: no data\n")); + + ostiInitiatorIOCompleted( + tiRoot, + tdIORequestBody->tiIORequest, /* tiIORequest */ + tiIOSuccess, + scsi_status, + agNULL, + agTRUE /* intContext; is not being used */ + ); + + return; + } + + if (data_status == 1) + { + /* RESPONSE_DATA */ + TI_DBG2(("itdssIOUnderFlowWithChkConditionHandler: response data \n")); + + ostiInitiatorIOCompleted( + tiRoot, + tdIORequestBody->tiIORequest, /* tiIORequest */ + tiIOSuccess, + 0, + agNULL, + agTRUE /* intContext; is not being used */ + ); + return; + } + + if (data_status == 2) + { + /* SENSE_DATA */ + TI_DBG2(("itdssIOUnderFlowWithChkConditionHandler: sense data \n")); + + senseData.senseData = &senseDataPayload; + senseData.senseLen = MIN(256, senseLen); + /* debugging */ + tdhexdump("ResponseIU I", (bit8 *)&agSSPRespIU, sizeof(agsaSSPResponseInfoUnit_t)); + + tdhexdump("sense data I", (bit8 *)senseDataPayload, senseLen); + tdhexdump("sense data II", (bit8 *)senseData.senseData, senseData.senseLen); + + if (senseDataPayload[2] == SCSI_SENSE_KEY_RECOVERED_ERROR) + { + Initiator->SenseKeyCounter.SoftError ++; + } + else if (senseDataPayload[2] == SCSI_SENSE_KEY_NOT_READY) + { + Initiator->SenseKeyCounter.MediumNotReady++; + } + else if (senseDataPayload[2] == SCSI_SENSE_KEY_MEDIUM_ERROR) + { + Initiator->SenseKeyCounter.MediumError++; + } + else if (senseDataPayload[2] == SCSI_SENSE_KEY_HARDWARE_ERROR) + { + Initiator->SenseKeyCounter.HardwareError++; + } + else if (senseDataPayload[2] == SCSI_SENSE_KEY_ILLEGAL_REQUEST) + { + Initiator->SenseKeyCounter.IllegalRequest++; + } + else if (senseDataPayload[2] == SCSI_SENSE_KEY_UNIT_ATTENTION) + { + Initiator->SenseKeyCounter.UnitAttention++; + } + else if (senseDataPayload[2] == SCSI_SENSE_KEY_ABORTED_COMMAND) + { + Initiator->SenseKeyCounter.AbortCommand++; + } + else + { + Initiator->SenseKeyCounter.OtherKeyType++; + } + + /* when ASQ and ASCQ 0x04 0x11, does saLocalPhyControl for notify spinup */ + if ((senseDataPayload[12] == 0x04 && senseDataPayload[13] == 0x11)) + { + TI_DBG2(("itdssIOUnderFlowWithChkConditionHandler: sending notfify spinup\n")); + tiDeviceHandle = tdIORequestBody->tiDevHandle; + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + if (oneDeviceData->directlyAttached == agTRUE) + { + for (i=0;iphyID, AGSA_PHY_NOTIFY_ENABLE_SPINUP, agNULL); + } + } + } + ostiInitiatorIOCompleted( + tiRoot, + /* tiIORequest */ + tdIORequestBody->tiIORequest, + tiIOSuccess, + scsi_status, + &senseData, + agTRUE /* intContext; is not being used */ + ); + return; + } + if (data_status == 3) + { + /* RESERVED */ + TI_DBG1(("itdssIOUnderFlowWithChkConditionHandler: reserved wrong!!!\n")); + ostiInitiatorIOCompleted( + tiRoot, + tdIORequestBody->tiIORequest, /* tiIORequest */ + tiIOFailed, + scsi_status, + agNULL, + agTRUE /* intContext; is not being used */ + ); + return; + } + + + return; +} +#endif + +/***************************************************************************** +*! \brief itdssXferOpenRetryBackoffThresholdReachedHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = +* OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssXferOpenRetryBackoffThresholdReachedHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG2(("itdssXferOpenRetryBackoffThresholdReachedHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssOpenCnxErrorItNexusLossOpenTmoHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssOpenCnxErrorItNexusLossOpenTmoHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG2(("itdssOpenCnxErrorItNexusLossOpenTmoHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssOpenCnxErrorItNexusLossNoDestHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssOpenCnxErrorItNexusLossNoDestHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG2(("itdssOpenCnxErrorItNexusLossNoDestHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssOpenCnxErrorItNexusLossOpenCollideHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssOpenCnxErrorItNexusLossOpenCollideHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG2(("itdssOpenCnxErrorItNexusLossOpenCollideHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssOpenCnxErrorItNexusLossOpenPathwayBlockedHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssOpenCnxErrorItNexusLossOpenPathwayBlockedHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG2(("itdssOpenCnxErrorItNexusLossOpenPathwayBlockedHandler: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + + return; +} + +/***************************************************************************** +*! \brief itdssEncryptionHandler +* +* Purpose: This function processes I/Os completed and returned by SAS lower +* layer with any encryption specific agIOStatus. +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssEncryptionHandler ( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + bit32 errorDetail = tiDetailOtherError; + tdIORequestBody_t *tdIORequestBody; + TI_DBG1(("itdssEncryptionHandler: start\n")); + TI_DBG1(("itdssEncryptionHandler: agIOStatus 0x%x\n", agIOStatus)); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + switch (agIOStatus) + { + case OSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS: + TI_DBG1(("itdssEncryptionHandler: OSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS\n")); + errorDetail = tiDetailDekKeyCacheMiss; + break; + case OSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID: + TI_DBG1(("itdssEncryptionHandler: OSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID\n")); + errorDetail = tiDetailCipherModeInvalid; + break; + case OSSA_IO_XFR_ERROR_DEK_IV_MISMATCH: + TI_DBG1(("itdssEncryptionHandler: OSSA_IO_XFR_ERROR_DEK_IV_MISMATCH\n")); + errorDetail = tiDetailDekIVMismatch; + break; + case OSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR: + TI_DBG1(("itdssEncryptionHandler: OSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR\n")); + errorDetail = tiDetailDekRamInterfaceError; + break; + case OSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS: + TI_DBG1(("itdssEncryptionHandler: OSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS\n")); + errorDetail = tiDetailDekIndexOutofBounds; + break; + case OSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE: + TI_DBG1(("itdssEncryptionHandler: OSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE\n")); + errorDetail = tiDetailOtherError; + break; + default: + TI_DBG1(("itdssEncryptionHandler: other error!!! 0x%x\n", agIOStatus)); + errorDetail = tiDetailOtherError; + break; + } + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOEncryptError, + errorDetail, + agNULL, + intContext + ); + return; +} + +/***************************************************************************** +*! \brief itdssDifHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with any DIF specific agIOStatus +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssDifHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + bit32 errorDetail = tiDetailOtherError; + tdIORequestBody_t *tdIORequestBody; +#ifdef TD_DEBUG_ENABLE + agsaDifDetails_t *DifDetail; +#endif + + TI_DBG1(("itdssDifHandler: start\n")); + TI_DBG1(("itdssDifHandler: agIOStatus 0x%x\n", agIOStatus)); + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; +#ifdef TD_DEBUG_ENABLE + DifDetail = (agsaDifDetails_t *)agParam; +#endif + switch (agIOStatus) + { + case OSSA_IO_XFR_ERROR_DIF_MISMATCH: + errorDetail = tiDetailDifMismatch; + TI_DBG1(("itdssDifHandler: OSSA_IO_XFR_ERROR_DIF_MISMATCH\n")); + break; + case OSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH: + errorDetail = tiDetailDifAppTagMismatch; + TI_DBG1(("itdssDifHandler: OSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH\n")); + break; + case OSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH: + errorDetail = tiDetailDifRefTagMismatch; + TI_DBG1(("itdssDifHandler: OSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH\n")); + break; + case OSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH: + errorDetail = tiDetailDifCrcMismatch; + TI_DBG1(("itdssDifHandler: OSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH\n")); + break; + default: + errorDetail = tiDetailOtherError; + TI_DBG1(("itdssDifHandler: other error!!! 0x%x\n", agIOStatus)); + break; + } + TI_DBG1(("itdssDifHandler: DIF detail UpperLBA 0x%08x LowerLBA 0x%08x\n", DifDetail->UpperLBA, DifDetail->LowerLBA)); + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIODifError, + errorDetail, + agNULL, + intContext + ); + return; +} + +/***************************************************************************** +*! \brief itdssIOResourceUnavailableHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssIOResourceUnavailableHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG2(("itdssIOResourceUnavailableHandler: start\n")); + TI_DBG2(("itdssIOResourceUnavailableHandler: agIOStatus 0x%x\n", agIOStatus)); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailBusy, + agNULL, + intContext + ); + return; +} +/***************************************************************************** +*! \brief itdssIORQEBusyFullHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_MPI_IO_RQE_BUSY_FULL +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssIORQEBusyFullHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG2(("itdssIORQEBusyFullHandler: start\n")); + TI_DBG2(("itdssIORQEBusyFullHandler: agIOStatus 0x%x\n", agIOStatus)); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailBusy, + agNULL, + intContext + ); + return; +} + +/***************************************************************************** +*! \brief itdssXferErrorInvalidSSPRspFrameHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_XFR_ERROR_INVALID_SSP_RSP_FRAME +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssXferErrorInvalidSSPRspFrameHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG2(("itdssXferErrorInvalidSSPRspFrameHandler: start\n")); + TI_DBG2(("itdssXferErrorInvalidSSPRspFrameHandler: agIOStatus 0x%x\n", agIOStatus)); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + return; +} + +/***************************************************************************** +*! \brief itdssXferErrorEOBDataOverrunHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_XFER_ERR_EOB_DATA_OVERRUN +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssXferErrorEOBDataOverrunHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG2(("itdssXferErrorEOBDataOverrunHandler: start\n")); + TI_DBG2(("itdssXferErrorEOBDataOverrunHandler: agIOStatus 0x%x\n", agIOStatus)); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + return; +} + +/***************************************************************************** +*! \brief itdssOpenCnxErrorOpenPreemptedHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = OSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssOpenCnxErrorOpenPreemptedHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG2(("itdssOpenCnxErrorOpenPreemptedHandler: start\n")); + TI_DBG2(("itdssOpenCnxErrorOpenPreemptedHandler: agIOStatus 0x%x\n", agIOStatus)); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + return; +} + +/* default */ +/***************************************************************************** +*! \brief itdssIODefaultHandler +* +* Purpose: This function processes I/Os completed and returned by SAS/SATA lower +* layer with agIOStatus = unspecified +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssIODefaultHandler ( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + TI_DBG2(("itdssIODefaultHandler: start\n")); + TI_DBG2(("itdssIODefaultHandler: agIOStatus 0x%x\n", agIOStatus)); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + intContext + ); + return; +} + +/***************************************************************************** +*! \brief itdssIOForDebugging1Completed +* +* Purpose: This function is only for debugging. This function should NOT be +* called. +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssIOForDebugging1Completed( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + TI_DBG1(("itdssIOForDebugging1Completed: start, error!!! can't be called. \n")); +} + +/***************************************************************************** +*! \brief itdssIOForDebugging2Completed +* +* Purpose: This function is only for debugging. This function should NOT be +* called. +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssIOForDebugging2Completed( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + TI_DBG1(("itdssIOForDebugging2Completed: start, error!!! can't be called. \n")); +} + +/***************************************************************************** +*! \brief itdssIOForDebugging3Completed +* +* Purpose: This function is only for debugging. This function should NOT be +* called. +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \param agOtherInfo Residual count +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdssIOForDebugging3Completed( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + TI_DBG1(("itdssIOForDebugging3Completed: start, error!!! can't be called. \n")); +} + + diff --git a/sys/dev/pms/RefTisa/tisa/sassata/sas/ini/itddefs.h b/sys/dev/pms/RefTisa/tisa/sassata/sas/ini/itddefs.h new file mode 100644 index 000000000000..157903fae9df --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/sas/ini/itddefs.h @@ -0,0 +1,48 @@ +/******************************************************************************* +** +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/*******************************************************************************/ +/** \file + * + * + * #define for SAS intiator in SAS/SATA TD layer + * + */ + + +#ifndef __ITDDEFS_H__ +#define __ITDDEFS_H__ +/* discovery related state */ +#define ITD_DSTATE_NOT_STARTED 0 +#define ITD_DSTATE_STARTED 1 +#define ITD_DSTATE_COMPLETED 2 + +/* SAS/SATA discovery status */ +#define DISCOVERY_NOT_START 0 /**< status indicates discovery not started */ +#define DISCOVERY_UP_STREAM 1 /**< status indicates discover upstream */ +#define DISCOVERY_DOWN_STREAM 2 /**< status indicates discover downstream */ +#define DISCOVERY_CONFIG_ROUTING 3 /**< status indicates discovery config routing table */ +#define DISCOVERY_SAS_DONE 4 /**< status indicates discovery done */ +#define DISCOVERY_REPORT_PHY_SATA 5 /**< status indicates discovery report phy sata */ +#endif /* __ITDDEFS_H__ */ diff --git a/sys/dev/pms/RefTisa/tisa/sassata/sas/ini/itddisc.c b/sys/dev/pms/RefTisa/tisa/sassata/sas/ini/itddisc.c new file mode 100644 index 000000000000..7be19115b6b2 --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/sas/ini/itddisc.c @@ -0,0 +1,8547 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +/*******************************************************************************/ +/** \file + * + * This file contains initiator discover related functions + * + */ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#ifdef FDS_SM +#include +#include +#include +#endif + +#ifdef FDS_DM +#include +#include +#include +#endif + +#include +#include +#include + +#ifdef INITIATOR_DRIVER +#include +#include +#include +#endif + +#ifdef TARGET_DRIVER +#include +#include +#include +#endif + +#include +#include + +/***************************************************************************** +*! \brief tiINIDiscoverTargets +* +* Purpose: This function is called to send a transport dependent discovery +* request. An implicit login will be started following the +* completion of discovery. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param portalContext: Pointer to the portal context instance. +* \param option: This is a bit field option on how the session is to be +* created +* \return: +* tiSuccess Discovery initiated. +* tiBusy Discovery could not be initiated at this time. +* +* \note: +* +*****************************************************************************/ +osGLOBAL bit32 +tiINIDiscoverTargets( + tiRoot_t *tiRoot, + tiPortalContext_t *portalContext, + bit32 option + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdList_t *PortContextList; + tdsaPortContext_t *onePortContext = agNULL; + bit32 found = agFALSE; + +#ifdef FDS_DM + dmRoot_t *dmRoot = &(tdsaAllShared->dmRoot); + dmPortContext_t *dmPortContext = agNULL; +#endif + /* + this function is called after LINK_UP by ossaHWCB() + Therefore, tdsaportcontext is ready at this point + */ + + TI_DBG3(("tiINIDiscoverTargets: start\n")); + + /* find a right tdsaPortContext using tiPortalContext + then, check the status of tdsaPortContext + then, if status is right, start the discovery + */ + + TI_DBG6(("tiINIDiscoverTargets: portalContext %p\n", portalContext)); + tdsaSingleThreadedEnter(tiRoot, TD_PORT_LOCK); + if (TDLIST_EMPTY(&(tdsaAllShared->MainPortContextList))) + { + tdsaSingleThreadedLeave(tiRoot, TD_PORT_LOCK); + TI_DBG1(("tiINIDiscoverTargets: No tdsaPortContext\n")); + return tiError; + } + else + { + tdsaSingleThreadedLeave(tiRoot, TD_PORT_LOCK); + } + + /* find a right portcontext */ + PortContextList = tdsaAllShared->MainPortContextList.flink; + if (PortContextList == agNULL) + { + TI_DBG1(("tiINIDiscoverTargets: PortContextList is NULL\n")); + return tiError; + } + while (PortContextList != &(tdsaAllShared->MainPortContextList)) + { + onePortContext = TDLIST_OBJECT_BASE(tdsaPortContext_t, MainLink, PortContextList); + if (onePortContext == agNULL) + { + TI_DBG1(("tiINIDiscoverTargets: onePortContext is NULL, PortContextList = %p\n", PortContextList)); + return tiError; + } + if (onePortContext->tiPortalContext == portalContext && onePortContext->valid == agTRUE) + { + TI_DBG6(("tiINIDiscoverTargets: found; oneportContext ID %d\n", onePortContext->id)); + found = agTRUE; + break; + } + PortContextList = PortContextList->flink; + } + + if (found == agFALSE) + { + TI_DBG1(("tiINIDiscoverTargets: No corresponding tdsaPortContext\n")); + return tiError; + } + + TI_DBG2(("tiINIDiscoverTargets: pid %d\n", onePortContext->id)); + if (onePortContext->DiscoveryState == ITD_DSTATE_NOT_STARTED) + { + TI_DBG6(("tiINIDiscoverTargets: calling Discovery\n")); + /* start SAS discovery */ +#ifdef FDS_DM + if (onePortContext->UseDM == agTRUE) + { + TI_DBG1(("tiINIDiscoverTargets: calling dmDiscover, pid %d\n", onePortContext->id)); + onePortContext->DiscoveryState = ITD_DSTATE_STARTED; + dmPortContext = &(onePortContext->dmPortContext); + dmDiscover(dmRoot, dmPortContext, DM_DISCOVERY_OPTION_FULL_START); + } + else + { + /* complete discovery */ + onePortContext->DiscoveryState = ITD_DSTATE_COMPLETED; + ostiInitiatorEvent( + tiRoot, + portalContext, + agNULL, + tiIntrEventTypeDiscovery, + tiDiscOK, + agNULL + ); + + return tiSuccess; + } + +#else + +#ifdef TD_DISCOVER + tdsaDiscover( + tiRoot, + onePortContext, + AG_SA_DISCOVERY_TYPE_SAS, + TDSA_DISCOVERY_OPTION_FULL_START + ); +#else + saDiscover(onePortContext->agRoot, onePortContext->agPortContext, AG_SA_DISCOVERY_TYPE_SAS, onePortContext->discoveryOptions); + + + +#endif +#endif /* FDS_DM */ + } + else + { + TI_DBG1(("tiINIDiscoverTargets: Discovery has started or incorrect initialization; state %d pid 0x%x\n", + onePortContext->DiscoveryState, + onePortContext->id)); + return tiError; + } + + return tiSuccess; +} + +/***************************************************************************** +*! \brief tiINIGetDeviceHandles +* +* Purpose: This routine is called to to return the device handles for each +* device currently available. +* +* \param tiRoot: Pointer to driver Instance. +* \param tiPortalContext: Pointer to the portal context instance. +* \param agDev[]: Array to receive pointers to the device handles. +* \param maxDevs: Number of device handles which will fit in array pointed +* by agDev. +* \return: +* Number of device handle slots present (however, only maxDevs +* are copied into tiDev[]) which may be greater than the number of +* handles actually present. In short, returns the number of devices that +* were found. +* +* \note: +* +*****************************************************************************/ +osGLOBAL bit32 +tiINIGetDeviceHandles( + tiRoot_t * tiRoot, + tiPortalContext_t * tiPortalContext, + tiDeviceHandle_t * tiDev[], + bit32 maxDevs + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdList_t *PortContextList; + tdsaPortContext_t *onePortContext = agNULL; + tdsaDeviceData_t *oneDeviceData = agNULL; + tdList_t *DeviceListList; + bit32 i; + bit32 FoundDevices = 0; + bit32 DeviceIndex = 0; + bit32 found = agFALSE; +#ifdef TD_DEBUG_ENABLE + satDeviceData_t *pSatDevData; +#endif +#ifdef FDS_DM + dmRoot_t *dmRoot = &(tdsaAllShared->dmRoot); +#endif + + TI_DBG2(("tiINIGetDeviceHandles: start\n")); + TI_DBG2(("tiINIGetDeviceHandles: tiPortalContext %p\n", tiPortalContext)); + + + if (maxDevs == 0) + { + TI_DBG1(("tiINIGetDeviceHandles: maxDevs is 0\n")); + TI_DBG1(("tiINIGetDeviceHandles: first, returning 0\n")); + /* nullify all device handles */ + for (i = 0 ; i < maxDevs ; i++) + { + tiDev[i] = agNULL; + } + return 0; + } + + tdsaSingleThreadedEnter(tiRoot, TD_PORT_LOCK); + if (TDLIST_EMPTY(&(tdsaAllShared->MainPortContextList))) + { + tdsaSingleThreadedLeave(tiRoot, TD_PORT_LOCK); + TI_DBG1(("tiINIGetDeviceHandles: No available tdsaPortContext\n")); + TI_DBG1(("tiINIGetDeviceHandles: second, returning 0\n")); + /* nullify all device handles */ + for (i = 0 ; i < maxDevs ; i++) + { + tiDev[i] = agNULL; + } + return 0; + } + else + { + tdsaSingleThreadedLeave(tiRoot, TD_PORT_LOCK); + } + /* find a corresponding portcontext */ + PortContextList = tdsaAllShared->MainPortContextList.flink; + while (PortContextList != &(tdsaAllShared->MainPortContextList)) + { + onePortContext = TDLIST_OBJECT_BASE(tdsaPortContext_t, MainLink, PortContextList); + if(onePortContext == agNULL) continue; + + TI_DBG3(("tiINIGetDeviceHandles: oneportContext pid %d\n", onePortContext->id)); + if (onePortContext->tiPortalContext == tiPortalContext && onePortContext->valid == agTRUE) + { + TI_DBG3(("tiINIGetDeviceHandles: found; oneportContext pid %d\n", onePortContext->id)); + found = agTRUE; + break; + } + PortContextList = PortContextList->flink; + } + + if (found == agFALSE) + { + TI_DBG1(("tiINIGetDeviceHandles: First, No corresponding tdsaPortContext\n")); + TI_DBG1(("tiINIGetDeviceHandles: third, returning 0\n")); + /* nullify all device handles */ + for (i = 0 ; i < maxDevs ; i++) + { + tiDev[i] = agNULL; + } + return 0; + } + + if (onePortContext == agNULL) + { + TI_DBG1(("tiINIGetDeviceHandles: Second, No corressponding tdsaPortContext\n")); + TI_DBG1(("tiINIGetDeviceHandles: fourth, returning 0\n")); + /* nullify all device handles */ + for (i = 0 ; i < maxDevs ; i++) + { + tiDev[i] = agNULL; + } + return 0; + } + + if (onePortContext->valid == agFALSE) + { + TI_DBG1(("tiINIGetDeviceHandles: Third, tdsaPortContext is invalid, pid %d\n", onePortContext->id)); + TI_DBG1(("tiINIGetDeviceHandles: fifth, returning 0\n")); + /* nullify all device handles */ + for (i = 0 ; i < maxDevs ; i++) + { + tiDev[i] = agNULL; + } + return 0; + } + + if (onePortContext->DiscoveryState == ITD_DSTATE_COMPLETED && onePortContext->DMDiscoveryState == dmDiscFailed) + { + TI_DBG1(("tiINIGetDeviceHandles: forth, discovery failed, pid %d\n", onePortContext->id)); + TI_DBG1(("tiINIGetDeviceHandles: sixth, returning 0\n")); + /* nullify all device handles */ + for (i = 0 ; i < maxDevs ; i++) + { + tiDev[i] = agNULL; + } + return 0; + } + + if (onePortContext->DiscoveryState != ITD_DSTATE_COMPLETED) + { + TI_DBG1(("tiINIGetDeviceHandles: discovery not completed\n")); + TI_DBG1(("tiINIGetDeviceHandles: sixth, returning DISCOVERY_IN_PROGRESS, pid %d\n", onePortContext->id)); + onePortContext->discovery.forcedOK = agTRUE; + return DISCOVERY_IN_PROGRESS; + } + + TI_DBG2(("tiINIGetDeviceHandles: pid %d\n", onePortContext->id)); + +#ifdef FDS_DM + tdsaUpdateMCN(dmRoot, onePortContext); +#endif + + /* nullify all device handles */ + for (i = 0 ; i < maxDevs ; i++) + { + tiDev[i] = agNULL; + } + + /* + From the device list, returns only valid devices + */ + DeviceListList = tdsaAllShared->MainDeviceList.flink; + + TD_ASSERT(DeviceListList, "DeviceListList NULL"); + if (DeviceListList == agNULL ) + { + TI_DBG1(("tiINIGetDeviceHandles: DeviceListList == agNULL\n")); + TI_DBG1(("tiINIGetDeviceHandles: seventh, returning not found, pid %d\n", onePortContext->id)); + return 0; + } + + while ((DeviceIndex < maxDevs) && + DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); +#ifdef TD_DEBUG_ENABLE + pSatDevData = (satDeviceData_t *)&(oneDeviceData->satDevData); + if (pSatDevData != agNULL) + { + TI_DBG3(("tiINIGetDeviceHandles: device %p satPendingIO %d satNCQMaxIO %d\n",pSatDevData, pSatDevData->satPendingIO, pSatDevData->satNCQMaxIO )); + TI_DBG3(("tiINIGetDeviceHandles: device %p satPendingNCQIO %d satPendingNONNCQIO %d\n",pSatDevData, pSatDevData->satPendingNCQIO, pSatDevData->satPendingNONNCQIO)); + } +#endif + TI_DBG3(("tiINIGetDeviceHandles: pid %d did %d\n", onePortContext->id, oneDeviceData->id)); + TI_DBG3(("tiINIGetDeviceHandles: device AddrHi 0x%08x AddrLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi, oneDeviceData->SASAddressID.sasAddressLo)); + + TI_DBG6(("tiINIGetDeviceHandles: handle %p\n", &(oneDeviceData->tiDeviceHandle))); + if (oneDeviceData->tdPortContext != onePortContext) + { + TI_DBG3(("tiINIGetDeviceHandles: different port\n")); + DeviceListList = DeviceListList->flink; + } + else + { +#ifdef SATA_ENABLE + if ((oneDeviceData->valid == agTRUE) && + (oneDeviceData->registered == agTRUE) && + (oneDeviceData->tdPortContext == onePortContext) && + ( DEVICE_IS_SSP_TARGET(oneDeviceData) || DEVICE_IS_STP_TARGET(oneDeviceData) + || DEVICE_IS_SATA_DEVICE(oneDeviceData) ) + ) +#else + if ((oneDeviceData->valid == agTRUE) && + (oneDeviceData->registered == agTRUE) && + (oneDeviceData->tdPortContext == onePortContext) && + ( DEVICE_IS_SSP_TARGET(oneDeviceData) || DEVICE_IS_STP_TARGET(oneDeviceData) ) + ) +#endif + { + if (DEVICE_IS_SSP_TARGET(oneDeviceData)) + { + TI_DBG2(("tiINIGetDeviceHandles: SSP DeviceIndex %d tiDeviceHandle %p\n", DeviceIndex, &(oneDeviceData->tiDeviceHandle))); + tiDev[DeviceIndex] = &(oneDeviceData->tiDeviceHandle); + FoundDevices++; + } + else if ( (DEVICE_IS_SATA_DEVICE(oneDeviceData) || DEVICE_IS_STP_TARGET(oneDeviceData)) + && + oneDeviceData->satDevData.IDDeviceValid == agTRUE ) + { + TI_DBG2(("tiINIGetDeviceHandles: SATA DeviceIndex %d tiDeviceHandle %p\n", DeviceIndex, &(oneDeviceData->tiDeviceHandle))); + tiDev[DeviceIndex] = &(oneDeviceData->tiDeviceHandle); + FoundDevices++; + } + else + { + TI_DBG3(("tiINIGetDeviceHandles: skip case !!!\n")); + TI_DBG3(("tiINIGetDeviceHandles: valid %d SSP target %d STP target %d SATA device %d\n", oneDeviceData->valid, DEVICE_IS_SSP_TARGET(oneDeviceData), DEVICE_IS_STP_TARGET(oneDeviceData), DEVICE_IS_SATA_DEVICE(oneDeviceData))); + TI_DBG3(("tiINIGetDeviceHandles: oneDeviceData->satDevData.IDDeviceValid %d\n", oneDeviceData->satDevData.IDDeviceValid)); + TI_DBG3(("tiINIGetDeviceHandles: registered %d right port %d \n", oneDeviceData->registered, (oneDeviceData->tdPortContext == onePortContext))); + TI_DBG3(("tiINIGetDeviceHandles: oneDeviceData->tdPortContext %p onePortContext %p\n", oneDeviceData->tdPortContext, onePortContext)); + } + TI_DBG3(("tiINIGetDeviceHandles: valid FoundDevices %d\n", FoundDevices)); + TI_DBG3(("tiINIGetDeviceHandles: agDevHandle %p\n", oneDeviceData->agDevHandle)); + } + else + { + TI_DBG3(("tiINIGetDeviceHandles: valid %d SSP target %d STP target %d SATA device %d\n", oneDeviceData->valid, DEVICE_IS_SSP_TARGET(oneDeviceData), DEVICE_IS_STP_TARGET(oneDeviceData), DEVICE_IS_SATA_DEVICE(oneDeviceData))); + TI_DBG3(("tiINIGetDeviceHandles: registered %d right port %d \n", oneDeviceData->registered, (oneDeviceData->tdPortContext == onePortContext))); + TI_DBG3(("tiINIGetDeviceHandles: oneDeviceData->tdPortContext %p onePortContext %p\n", oneDeviceData->tdPortContext, onePortContext)); + } + DeviceIndex++; + DeviceListList = DeviceListList->flink; + } /* else */ + } + + if (DeviceIndex > maxDevs) + { + TI_DBG1(("tiINIGetDeviceHandles: DeviceIndex(%d) >= maxDevs(%d)\n", DeviceIndex, maxDevs)); + FoundDevices = maxDevs; + } + + TI_DBG1(("tiINIGetDeviceHandles: returning %d found devices, pid %d\n", FoundDevices, onePortContext->id)); + + return FoundDevices; +} + +/***************************************************************************** +*! \brief tiINIGetDeviceHandlesForWinIOCTL +* +* Purpose: This routine is called to to return the device handles for each +* device currently available, this routine is only for Win IOCTL to display SAS topology. +* +* \param tiRoot: Pointer to driver Instance. +* \param tiPortalContext: Pointer to the portal context instance. +* \param agDev[]: Array to receive pointers to the device handles. +* \param maxDevs: Number of device handles which will fit in array pointed +* by agDev. +* \return: +* Number of device handle slots present (however, only maxDevs +* are copied into tiDev[]) which may be greater than the number of +* handles actually present. In short, returns the number of devices that +* were found. +* +* \note: +* +*****************************************************************************/ +osGLOBAL bit32 +tiINIGetDeviceHandlesForWinIOCTL( + tiRoot_t * tiRoot, + tiPortalContext_t * tiPortalContext, + tiDeviceHandle_t * tiDev[], + bit32 maxDevs + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdList_t *PortContextList; + tdsaPortContext_t *onePortContext = agNULL; + tdsaDeviceData_t *oneDeviceData = agNULL; + tdList_t *DeviceListList; + bit32 i; + bit32 FoundDevices = 0; + bit32 DeviceIndex = 0; + bit32 found = agFALSE; +#ifdef TD_DEBUG_ENABLE + satDeviceData_t *pSatDevData; +#endif +#ifdef FDS_DM + dmRoot_t *dmRoot = &(tdsaAllShared->dmRoot); +#endif + + TI_DBG2(("tiINIGetDeviceHandlesForWinIOCTL: start\n")); + TI_DBG2(("tiINIGetDeviceHandlesForWinIOCTL: tiPortalContext %p\n", tiPortalContext)); + + + if (maxDevs == 0) + { + TI_DBG1(("tiINIGetDeviceHandlesForWinIOCTL: maxDevs is 0\n")); + TI_DBG1(("tiINIGetDeviceHandlesForWinIOCTL: first, returning 0\n")); + /* nullify all device handles */ + for (i = 0 ; i < maxDevs ; i++) + { + tiDev[i] = agNULL; + } + return 0; + } + + tdsaSingleThreadedEnter(tiRoot, TD_PORT_LOCK); + if (TDLIST_EMPTY(&(tdsaAllShared->MainPortContextList))) + { + tdsaSingleThreadedLeave(tiRoot, TD_PORT_LOCK); + TI_DBG1(("tiINIGetDeviceHandlesForWinIOCTL: No available tdsaPortContext\n")); + TI_DBG1(("tiINIGetDeviceHandlesForWinIOCTL: second, returning 0\n")); + /* nullify all device handles */ + for (i = 0 ; i < maxDevs ; i++) + { + tiDev[i] = agNULL; + } + return 0; + } + else + { + tdsaSingleThreadedLeave(tiRoot, TD_PORT_LOCK); + } + /* find a corresponding portcontext */ + PortContextList = tdsaAllShared->MainPortContextList.flink; + while (PortContextList != &(tdsaAllShared->MainPortContextList)) + { + onePortContext = TDLIST_OBJECT_BASE(tdsaPortContext_t, MainLink, PortContextList); + if(onePortContext == agNULL) continue; + + TI_DBG3(("tiINIGetDeviceHandlesForWinIOCTL: oneportContext pid %d\n", onePortContext->id)); + if (onePortContext->tiPortalContext == tiPortalContext && onePortContext->valid == agTRUE) + { + TI_DBG3(("tiINIGetDeviceHandlesForWinIOCTL: found; oneportContext pid %d\n", onePortContext->id)); + found = agTRUE; + break; + } + PortContextList = PortContextList->flink; + } + + if (found == agFALSE) + { + TI_DBG1(("tiINIGetDeviceHandlesForWinIOCTL: First, No corresponding tdsaPortContext\n")); + TI_DBG1(("tiINIGetDeviceHandlesForWinIOCTL: third, returning 0\n")); + /* nullify all device handles */ + for (i = 0 ; i < maxDevs ; i++) + { + tiDev[i] = agNULL; + } + return 0; + } + + if (onePortContext == agNULL) + { + TI_DBG1(("tiINIGetDeviceHandlesForWinIOCTL: Second, No corressponding tdsaPortContext\n")); + TI_DBG1(("tiINIGetDeviceHandlesForWinIOCTL: fourth, returning 0\n")); + /* nullify all device handles */ + for (i = 0 ; i < maxDevs ; i++) + { + tiDev[i] = agNULL; + } + return 0; + } + + if (onePortContext->valid == agFALSE) + { + TI_DBG1(("tiINIGetDeviceHandlesForWinIOCTL: Third, tdsaPortContext is invalid, pid %d\n", onePortContext->id)); + TI_DBG1(("tiINIGetDeviceHandlesForWinIOCTL: fifth, returning 0\n")); + /* nullify all device handles */ + for (i = 0 ; i < maxDevs ; i++) + { + tiDev[i] = agNULL; + } + return 0; + } + + if (onePortContext->DiscoveryState == ITD_DSTATE_COMPLETED && onePortContext->DMDiscoveryState == dmDiscFailed) + { + TI_DBG1(("tiINIGetDeviceHandlesForWinIOCTL: forth, discovery failed, pid %d\n", onePortContext->id)); + TI_DBG1(("tiINIGetDeviceHandlesForWinIOCTL: sixth, returning 0\n")); + /* nullify all device handles */ + for (i = 0 ; i < maxDevs ; i++) + { + tiDev[i] = agNULL; + } + return 0; + } + + if (onePortContext->DiscoveryState != ITD_DSTATE_COMPLETED) + { + TI_DBG1(("tiINIGetDeviceHandlesForWinIOCTL: discovery not completed\n")); + TI_DBG1(("tiINIGetDeviceHandlesForWinIOCTL: sixth, returning DISCOVERY_IN_PROGRESS, pid %d\n", onePortContext->id)); + onePortContext->discovery.forcedOK = agTRUE; + return DISCOVERY_IN_PROGRESS; + } + + TI_DBG2(("tiINIGetDeviceHandlesForWinIOCTL: pid %d\n", onePortContext->id)); + +#ifdef FDS_DM + tdsaUpdateMCN(dmRoot, onePortContext); +#endif + + /* nullify all device handles */ + for (i = 0 ; i < maxDevs ; i++) + { + tiDev[i] = agNULL; + } + + /* + From the device list, returns only valid devices + */ + DeviceListList = tdsaAllShared->MainDeviceList.flink; + + TD_ASSERT(DeviceListList, "DeviceListList NULL"); + if (DeviceListList == agNULL ) + { + TI_DBG1(("tiINIGetDeviceHandlesForWinIOCTL: DeviceListList == agNULL\n")); + TI_DBG1(("tiINIGetDeviceHandlesForWinIOCTL: seventh, returning not found, pid %d\n", onePortContext->id)); + return 0; + } + + while ((DeviceIndex < maxDevs) && + DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + if(oneDeviceData == agNULL) + { + TI_DBG3(("tiINIGetDeviceHandles: OneDeviceData is NULL\n")); + return 0; + } +#ifdef TD_DEBUG_ENABLE + pSatDevData = (satDeviceData_t *)&(oneDeviceData->satDevData); + if (pSatDevData != agNULL) + { + TI_DBG3(("tiINIGetDeviceHandlesForWinIOCTL: device %p satPendingIO %d satNCQMaxIO %d\n",pSatDevData, pSatDevData->satPendingIO, pSatDevData->satNCQMaxIO )); + TI_DBG3(("tiINIGetDeviceHandlesForWinIOCTL: device %p satPendingNCQIO %d satPendingNONNCQIO %d\n",pSatDevData, pSatDevData->satPendingNCQIO, pSatDevData->satPendingNONNCQIO)); + } +#endif + TI_DBG3(("tiINIGetDeviceHandlesForWinIOCTL: pid %d did %d\n", onePortContext->id, oneDeviceData->id)); + TI_DBG3(("tiINIGetDeviceHandlesForWinIOCTL: device AddrHi 0x%08x AddrLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi, oneDeviceData->SASAddressID.sasAddressLo)); + + TI_DBG6(("tiINIGetDeviceHandlesForWinIOCTL: handle %p\n", &(oneDeviceData->tiDeviceHandle))); + if (oneDeviceData->tdPortContext != onePortContext) + { + TI_DBG3(("tiINIGetDeviceHandlesForWinIOCTL: different port\n")); + DeviceListList = DeviceListList->flink; + } + else + { +#ifdef SATA_ENABLE + if ((oneDeviceData->valid == agTRUE) && + (oneDeviceData->registered == agTRUE) && + (oneDeviceData->tdPortContext == onePortContext) && + ( DEVICE_IS_SSP_TARGET(oneDeviceData) || DEVICE_IS_STP_TARGET(oneDeviceData) + || DEVICE_IS_SATA_DEVICE(oneDeviceData) || DEVICE_IS_SMP_TARGET(oneDeviceData)) + ) +#else + if ((oneDeviceData->valid == agTRUE) && + (oneDeviceData->registered == agTRUE) && + (oneDeviceData->tdPortContext == onePortContext) && + ( DEVICE_IS_SSP_TARGET(oneDeviceData) || DEVICE_IS_STP_TARGET(oneDeviceData)) + ) +#endif + { + if (DEVICE_IS_SSP_TARGET(oneDeviceData)) + { + TI_DBG2(("tiINIGetDeviceHandlesForWinIOCTL: SSP DeviceIndex %d tiDeviceHandle %p\n", DeviceIndex, &(oneDeviceData->tiDeviceHandle))); + tiDev[DeviceIndex] = &(oneDeviceData->tiDeviceHandle); + DeviceIndex++; + FoundDevices++; + } + else if ( (DEVICE_IS_SATA_DEVICE(oneDeviceData) || DEVICE_IS_STP_TARGET(oneDeviceData)) + && + oneDeviceData->satDevData.IDDeviceValid == agTRUE ) + { + TI_DBG2(("tiINIGetDeviceHandlesForWinIOCTL: SATA DeviceIndex %d tiDeviceHandle %p\n", DeviceIndex, &(oneDeviceData->tiDeviceHandle))); + tiDev[DeviceIndex] = &(oneDeviceData->tiDeviceHandle); + DeviceIndex++; + FoundDevices++; + } + else if (DEVICE_IS_SMP_TARGET(oneDeviceData)) + { + TI_DBG2(("tiINIGetDeviceHandlesForWinIOCTL: SMP DeviceIndex %d tiDeviceHandle %p\n", DeviceIndex, &(oneDeviceData->tiDeviceHandle))); + tiDev[DeviceIndex] = &(oneDeviceData->tiDeviceHandle); + DeviceIndex++; + FoundDevices++; + } + else + { + TI_DBG3(("tiINIGetDeviceHandlesForWinIOCTL: skip case !!!\n")); + TI_DBG3(("tiINIGetDeviceHandlesForWinIOCTL: valid %d SSP target %d STP target %d SATA device %d\n", oneDeviceData->valid, DEVICE_IS_SSP_TARGET(oneDeviceData), DEVICE_IS_STP_TARGET(oneDeviceData), DEVICE_IS_SATA_DEVICE(oneDeviceData))); + TI_DBG3(("tiINIGetDeviceHandlesForWinIOCTL: oneDeviceData->satDevData.IDDeviceValid %d\n", oneDeviceData->satDevData.IDDeviceValid)); + TI_DBG3(("tiINIGetDeviceHandlesForWinIOCTL: registered %d right port %d \n", oneDeviceData->registered, (oneDeviceData->tdPortContext == onePortContext))); + TI_DBG3(("tiINIGetDeviceHandlesForWinIOCTL: oneDeviceData->tdPortContext %p onePortContext %p\n", oneDeviceData->tdPortContext, onePortContext)); + } + TI_DBG3(("tiINIGetDeviceHandlesForWinIOCTL: valid FoundDevices %d\n", FoundDevices)); + TI_DBG3(("tiINIGetDeviceHandlesForWinIOCTL: agDevHandle %p\n", oneDeviceData->agDevHandle)); + } + else + { + TI_DBG3(("tiINIGetDeviceHandlesForWinIOCTL: valid %d SSP target %d STP target %d SATA device %d\n", oneDeviceData->valid, DEVICE_IS_SSP_TARGET(oneDeviceData), DEVICE_IS_STP_TARGET(oneDeviceData), DEVICE_IS_SATA_DEVICE(oneDeviceData))); + TI_DBG3(("tiINIGetDeviceHandlesForWinIOCTL: registered %d right port %d \n", oneDeviceData->registered, (oneDeviceData->tdPortContext == onePortContext))); + TI_DBG3(("tiINIGetDeviceHandlesForWinIOCTL: oneDeviceData->tdPortContext %p onePortContext %p\n", oneDeviceData->tdPortContext, onePortContext)); + } + //DeviceIndex++; + DeviceListList = DeviceListList->flink; + } /* else */ + } + + if (DeviceIndex > maxDevs) + { + TI_DBG1(("tiINIGetDeviceHandlesForWinIOCTL: DeviceIndex(%d) >= maxDevs(%d)\n", DeviceIndex, maxDevs)); + FoundDevices = maxDevs; + } + + TI_DBG1(("tiINIGetDeviceHandlesForWinIOCTL: returning %d found devices, pid %d\n", FoundDevices, onePortContext->id)); + + return FoundDevices; +} + + +/***************************************************************************** +*! \brief tiINIGetDeviceInfo +* +* Purpose: This routine is called by the OS Layer find out +* the name associated with the device and where +* it is mapped (address1 and address2). +* +* \param tiRoot: Pointer to driver Instance. +* \param tiDeviceHandle: device handle associated with the device +* \param tiDeviceInfo: pointer to structure where the information +* needs to be copied. +* \return: +* tiSuccess - successful +* tiInvalidHandle - device handle passed is not a valid handle. +* +* \note: +* +*****************************************************************************/ +osGLOBAL bit32 +tiINIGetDeviceInfo( + tiRoot_t *tiRoot, + tiDeviceHandle_t *tiDeviceHandle, + tiDeviceInfo_t *tiDeviceInfo) +{ + tdsaDeviceData_t *oneDeviceData = agNULL; + satDeviceData_t *pSatDevData = agNULL; + bit8 id_limit[5]; + bit8 SN_id_limit[25]; + agsaRoot_t *agRoot = agNULL; + + TI_DBG6(("tiINIGetDeviceInfo: start \n")); + + if (tiDeviceHandle == agNULL) + { + TI_DBG6(("tiINIGetDeviceInfo: tiDeviceHandle NULL\n")); + return tiInvalidHandle; + } + + if (tiDeviceHandle->tdData == agNULL) + { + TI_DBG6(("tiINIGetDeviceInfo: ^^^^^^^^^ tiDeviceHandle->tdData NULL\n")); + return tiInvalidHandle; + } + else + { + + oneDeviceData = (tdsaDeviceData_t *)(tiDeviceHandle->tdData); + agRoot = oneDeviceData->agRoot; + TI_DBG6(("tiINIGetDeviceInfo: ^^^^^^^^^ tiDeviceHandle->tdData NOT NULL\n")); + } + if (oneDeviceData == agNULL) + { + TI_DBG6(("tiINIGetDeviceInfo: ^^^^^^^^^ oneDeviceData NULL\n")); + return tiInvalidHandle; + } + + + /* filling in the link rate */ + if (oneDeviceData->registered == agTRUE) + { + tiDeviceInfo->info.devType_S_Rate = oneDeviceData->agDeviceInfo.devType_S_Rate; + } + else + { + tiDeviceInfo->info.devType_S_Rate = (bit8)(oneDeviceData->agDeviceInfo.devType_S_Rate & 0x0f); + } + + /* just returning local and remote SAS address; doesn't have a name for SATA device, returns identify device data */ + if (DEVICE_IS_SATA_DEVICE(oneDeviceData) && (oneDeviceData->directlyAttached == agTRUE)) + { + osti_memset(&id_limit, 0, sizeof(id_limit)); + osti_memset(&SN_id_limit, 0, sizeof(SN_id_limit)); + + /* SATA signature 0xABCD */ + id_limit[0] = 0xA; + id_limit[1] = 0xB; + id_limit[2] = 0xC; + id_limit[3] = 0xD; + + pSatDevData = &(oneDeviceData->satDevData); + if (pSatDevData->satNCQ == agTRUE) + { + id_limit[4] = (bit8)pSatDevData->satNCQMaxIO; + } + else + { + /* no NCQ */ + id_limit[4] = 1; + } + + osti_memcpy(&SN_id_limit, &(oneDeviceData->satDevData.satIdentifyData.serialNumber), 20); + osti_memcpy(&(SN_id_limit[20]), &id_limit, 5); + osti_memcpy(oneDeviceData->satDevData.SN_id_limit, SN_id_limit, 25); + /* serialNumber, 20 bytes + ABCD + NCQ LENGTH ; modelNumber, 40 bytes */ +// tiDeviceInfo->remoteName = (char *)&(oneDeviceData->satDevData.satIdentifyData.serialNumber); + tiDeviceInfo->remoteName = (char *)oneDeviceData->satDevData.SN_id_limit; + tiDeviceInfo->remoteAddress = (char *)&(oneDeviceData->satDevData.satIdentifyData.modelNumber); +// TI_DBG1(("tiINIGetDeviceInfo: SATA device remote hi 0x%08x lo 0x%08x\n", oneDeviceData->tdPortContext->sasRemoteAddressHi, oneDeviceData->tdPortContext->sasRemoteAddressLo)); +// tdhexdump("tiINIGetDeviceInfo remotename", (bit8 *)&(oneDeviceData->satDevData.satIdentifyData.serialNumber), 20); +// tdhexdump("tiINIGetDeviceInfo new name", (bit8 *)&(SN_id_limit), sizeof(SN_id_limit)); +// tdhexdump("tiINIGetDeviceInfo remoteaddress", (bit8 *)&(oneDeviceData->satDevData.satIdentifyData.modelNumber),40); + tiDeviceInfo->osAddress1 = 25; + tiDeviceInfo->osAddress2 = 40; + + } + else if (DEVICE_IS_STP_TARGET(oneDeviceData)) + { + /* serialNumber, 20 bytes; modelNumber, 40 bytes */ + tiDeviceInfo->remoteName = (char *)&(oneDeviceData->satDevData.satIdentifyData.serialNumber); + tiDeviceInfo->remoteAddress = (char *)&(oneDeviceData->satDevData.satIdentifyData.modelNumber); +// TI_DBG1(("tiINIGetDeviceInfo: SATA device remote hi 0x%08x lo 0x%08x\n", oneDeviceData->tdPortContext->sasRemoteAddressHi, oneDeviceData->tdPortContext->sasRemoteAddressLo)); +// tdhexdump("tiINIGetDeviceInfo remotename", (bit8 *)&(oneDeviceData->satDevData.satIdentifyData.serialNumber), 20); +// tdhexdump("tiINIGetDeviceInfo remoteaddress", (bit8 *)&(oneDeviceData->satDevData.satIdentifyData.modelNumber),40); + tiDeviceInfo->osAddress1 = 20; + tiDeviceInfo->osAddress2 = 40; + } + else + { + tiDeviceInfo->remoteName = (char *)&(oneDeviceData->SASAddressID.sasAddressHi); + tiDeviceInfo->remoteAddress = (char *)&(oneDeviceData->SASAddressID.sasAddressLo); + TI_DBG1(("tiINIGetDeviceInfo: SAS device remote hi 0x%08x lo 0x%08x\n", oneDeviceData->tdPortContext->sasRemoteAddressHi, oneDeviceData->tdPortContext->sasRemoteAddressLo)); + tiDeviceInfo->osAddress1 = 4; + tiDeviceInfo->osAddress2 = 4; + } + + tiDeviceInfo->localName = (char *)&(oneDeviceData->tdPortContext->sasLocalAddressHi); + tiDeviceInfo->localAddress = (char *)&(oneDeviceData->tdPortContext->sasLocalAddressLo); + + TI_DBG6(("tiINIGetDeviceInfo: local hi 0x%08x lo 0x%08x\n", oneDeviceData->tdPortContext->sasLocalAddressHi, oneDeviceData->tdPortContext->sasLocalAddressLo)); + + if (oneDeviceData->agDevHandle == agNULL) + { + TI_DBG1(("tiINIGetDeviceInfo: Error! oneDeviceData->agDevHandle is NULL")); + return tiError; + } + else + { + saGetDeviceInfo(agRoot, agNULL, 0, 0,oneDeviceData->agDevHandle); + } + + + return tiSuccess; +} + +/***************************************************************************** +*! \brief tiINILogin +* +* Purpose: This function is called to request that the Transport Dependent +* Layer initiates login for a specific target. +* +* \param tiRoot: Pointer to driver Instance. +* \param tiDeviceHandle: Pointer to a target device handle discovered +* following the discovery. +* +* \return: +* tiSuccess Login initiated. +* tiError Login failed. +* tiBusy Login can not be initiated at this time. +* tiNotSupported This API is currently not supported by this +* Transport Layer +* +* +*****************************************************************************/ +osGLOBAL bit32 +tiINILogin( + tiRoot_t *tiRoot, + tiDeviceHandle_t *tiDeviceHandle + ) +{ + TI_DBG6(("tiINILogin: start\n")); + return tiNotSupported; +} + +/***************************************************************************** +*! \brief tiINILogout +* +* Purpose: This function is called to request that the Transport Dependent +* Layer initiates logout for a specific target from the previously +* successful login through tiINILogin() call. +* +* \param tiRoot : Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param tiDeviceHandle: Pointer to a target device handle. +* +* \return: +* tiSuccess Logout initiated. +* tiError Logout failed. +* tiBusy Logout can not be initiated at this time. +* tiNotSupported This API is currently not supported by this +* Transport Layer +* +* +*****************************************************************************/ +osGLOBAL bit32 +tiINILogout( + tiRoot_t *tiRoot, + tiDeviceHandle_t *tiDeviceHandle + ) +{ + TI_DBG6(("tiINILogout: start\n")); + return tiNotSupported; +} +/***************************************************************************** +*! \brief tiINIGetExpander +* +* +* \note: +* +*****************************************************************************/ +osGLOBAL bit32 +tiINIGetExpander( + tiRoot_t * tiRoot, + tiPortalContext_t * tiPortalContext, + tiDeviceHandle_t * tiDev, + tiDeviceHandle_t ** tiExp + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdList_t *PortContextList; + tdsaPortContext_t *onePortContext = agNULL; + tdsaDeviceData_t *oneDeviceData = agNULL; + tdList_t *DeviceListList; + tdsaDeviceData_t *oneTargetDeviceData = agNULL; + tdsaDeviceData_t *oneExpanderDeviceData = agNULL; + bit32 found = agFALSE; + oneTargetDeviceData = (tdsaDeviceData_t *)tiDev->tdData; + if (oneTargetDeviceData == agNULL) + { + TI_DBG1(("tiINIGetExpander: oneTargetDeviceData is NULL\n")); + return tiError; + } + tdsaSingleThreadedEnter(tiRoot, TD_PORT_LOCK); + if (TDLIST_EMPTY(&(tdsaAllShared->MainPortContextList))) + { + tdsaSingleThreadedLeave(tiRoot, TD_PORT_LOCK); + TI_DBG1(("tiINIGetExpander: No available tdsaPortContext\n")); + TI_DBG1(("tiINIGetExpander: second, returning 0\n")); + return tiError; + } + else + { + tdsaSingleThreadedLeave(tiRoot, TD_PORT_LOCK); + } + /* find a corresponding portcontext */ + PortContextList = tdsaAllShared->MainPortContextList.flink; + while (PortContextList != &(tdsaAllShared->MainPortContextList)) + { + onePortContext = TDLIST_OBJECT_BASE(tdsaPortContext_t, MainLink, PortContextList); + TI_DBG3(("tiINIGetExpander: oneportContext pid %d\n", onePortContext->id)); + if (onePortContext->tiPortalContext == tiPortalContext && onePortContext->valid == agTRUE) + { + TI_DBG3(("tiINIGetExpander: found; oneportContext pid %d\n", onePortContext->id)); + found = agTRUE; + break; + } + PortContextList = PortContextList->flink; + } + if (found == agFALSE) + { + TI_DBG1(("tiINIGetExpander: First, No corresponding tdsaPortContext\n")); + TI_DBG1(("tiINIGetExpander: third, returning 0\n")); + return tiError; + } + if (onePortContext == agNULL) + { + TI_DBG1(("tiINIGetExpander: Second, No corressponding tdsaPortContext\n")); + TI_DBG1(("tiINIGetExpander: fourth, returning 0\n")); + return tiError; + } + if (onePortContext->valid == agFALSE) + { + TI_DBG1(("tiINIGetExpander: Third, tdsaPortContext is invalid, pid %d\n", onePortContext->id)); + TI_DBG1(("tiINIGetExpander: fifth, returning 0\n")); + return tiError; + } + DeviceListList = tdsaAllShared->MainDeviceList.flink; + while ( DeviceListList != &(tdsaAllShared->MainDeviceList) ) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData->tdPortContext != onePortContext) + { + TI_DBG3(("tiINIGetExpander: different port\n")); + DeviceListList = DeviceListList->flink; + } + else + { + if (oneDeviceData == oneTargetDeviceData) + { + oneExpanderDeviceData = oneDeviceData->ExpDevice; + if (oneExpanderDeviceData == agNULL) + { + TI_DBG1(("tiINIGetExpander: oneExpanderDeviceData is NULL\n")); + return tiError; + } + *tiExp = &(oneExpanderDeviceData->tiDeviceHandle); + return tiSuccess; + } + DeviceListList = DeviceListList->flink; + } + } + return tiError; +} + + +osGLOBAL void tiIniGetDirectSataSasAddr(tiRoot_t * tiRoot, bit32 phyId, bit8 **sasAddressHi, bit8 **sasAddressLo) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + agsaRoot_t *agRoot = &tdsaAllShared->agRootInt; + tiIOCTLPayload_wwn_t agIoctlPayload; + bit8 nvmDev; + bit32 status; + int i; + agIoctlPayload.Length = 4096; + agIoctlPayload.Reserved = 0; + agIoctlPayload.MinorFunction = IOCTL_MN_NVMD_GET_CONFIG; + agIoctlPayload.MajorFunction = IOCTL_MJ_NVMD_GET; + tiCOMDelayedInterruptHandler(tiRoot, 0,1, tiNonInterruptContext); + if(tiIS_SPC(agRoot)) + { + nvmDev = 4; + status = tdsaNVMDGetIoctl(tiRoot, (tiIOCTLPayload_t *)&agIoctlPayload, agNULL, agNULL, &nvmDev); + } + else + { + nvmDev = 1; + status = tdsaNVMDGetIoctl(tiRoot, (tiIOCTLPayload_t *)&agIoctlPayload, agNULL, agNULL, &nvmDev); + } + if(status == IOCTL_CALL_FAIL) + { +#if !(defined(__FreeBSD__)) + printk("Error getting Adapter WWN\n"); +#else + printf("Error getting Adapter WWN\n"); +#endif + return; + } + for(i=0; i< TD_MAX_NUM_PHYS; i++) + { + *(bit32 *)(tdsaAllShared->Ports[i].SASID.sasAddressHi) = *(bit32 *)&agIoctlPayload.FunctionSpecificArea[0]; + *(bit32 *)(tdsaAllShared->Ports[i].SASID.sasAddressLo) = *(bit32 *)&agIoctlPayload.FunctionSpecificArea[4]; + TI_DBG3(("SAS AddressHi is 0x%x\n", *(bit32 *)(tdsaAllShared->Ports[i].SASID.sasAddressHi))); + TI_DBG3(("SAS AddressLo is 0x%x\n", *(bit32 *)(tdsaAllShared->Ports[i].SASID.sasAddressLo))); + } + *sasAddressHi = tdsaAllShared->Ports[phyId].SASID.sasAddressHi; + *sasAddressLo = tdsaAllShared->Ports[phyId].SASID.sasAddressLo; +} +osGLOBAL tiDeviceHandle_t * +tiINIGetExpDeviceHandleBySasAddress( + tiRoot_t * tiRoot, + tiPortalContext_t * tiPortalContext, + bit32 sas_addr_hi, + bit32 sas_addr_lo, + bit32 maxDevs + ) + +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdList_t *PortContextList; + tdsaPortContext_t *onePortContext = agNULL; + tdsaDeviceData_t *oneDeviceData = agNULL; + tdList_t *DeviceListList; + //bit32 i; + //bit32 FoundDevices = 0; + bit32 DeviceIndex = 0; + bit32 found = agFALSE; + + + TI_DBG2(("tiINIGetExpDeviceHandleBySasAddress: start\n")); + TI_DBG2(("tiINIGetExpDeviceHandleBySasAddress: tiPortalContext %p\n", tiPortalContext)); + + + if (maxDevs == 0) + { + TI_DBG1(("tiINIGetExpDeviceHandleBySasAddress: maxDevs is 0\n")); + + return agNULL; + } + + tdsaSingleThreadedEnter(tiRoot, TD_PORT_LOCK); + if (TDLIST_EMPTY(&(tdsaAllShared->MainPortContextList))) + { + tdsaSingleThreadedLeave(tiRoot, TD_PORT_LOCK); + TI_DBG1(("tiINIGetExpDeviceHandleBySasAddress: No available tdsaPortContext\n")); + TI_DBG1(("tiINIGetExpDeviceHandleBySasAddress: second, returning 0\n")); + return agNULL; + } + else + { + tdsaSingleThreadedLeave(tiRoot, TD_PORT_LOCK); + } + /* find a corresponding portcontext */ + PortContextList = tdsaAllShared->MainPortContextList.flink; + + if(PortContextList == agNULL) + { + TI_DBG6(("tiINIGetExpDeviceHandleBySasAddress: PortContextList is NULL!!\n")); + return agNULL; + } + + while (PortContextList != &(tdsaAllShared->MainPortContextList)) + { + onePortContext = TDLIST_OBJECT_BASE(tdsaPortContext_t, MainLink, PortContextList); + + if(onePortContext == agNULL) + { + TI_DBG6(("tiINIGetExpDeviceHandleBySasAddress: onePortContext is NULL!!\n")); + return agNULL; + } + + TI_DBG3(("tiINIGetExpDeviceHandleBySasAddress: oneportContext pid %d\n", onePortContext->id)); + if (onePortContext->tiPortalContext == tiPortalContext && onePortContext->valid == agTRUE) + { + TI_DBG3(("tiINIGetExpDeviceHandleBySasAddress: found; oneportContext pid %d\n", onePortContext->id)); + found = agTRUE; + break; + } + + if(PortContextList != agNULL) + { + PortContextList = PortContextList->flink; + } + + } + + if (found == agFALSE) + { + TI_DBG1(("tiINIGetExpDeviceHandleBySasAddress: First, No corresponding tdsaPortContext\n")); + TI_DBG1(("tiINIGetExpDeviceHandleBySasAddress: third, returning 0\n")); + /* nullify all device handles */ + return agNULL; + } + + if (onePortContext == agNULL) + { + TI_DBG1(("tiINIGetExpDeviceHandleBySasAddress: Second, No corressponding tdsaPortContext\n")); + TI_DBG1(("tiINIGetExpDeviceHandleBySasAddress: fourth, returning 0\n")); + /* nullify all device handles */ + return agNULL; + } + + if (onePortContext->valid == agFALSE) + { + TI_DBG1(("tiINIGetExpDeviceHandleBySasAddress: Third, tdsaPortContext is invalid, pid %d\n", onePortContext->id)); + TI_DBG1(("tiINIGetExpDeviceHandleBySasAddress: fifth, returning 0\n")); + return agNULL; + } + + + TI_DBG2(("tiINIGetExpDeviceHandleBySasAddress: pid %d\n", onePortContext->id)); + + + /* to do: check maxdev and length of Mainlink */ + /* + From the device list, returns only valid devices + */ + DeviceListList = tdsaAllShared->MainDeviceList.flink; + + if(DeviceListList == agNULL) + { + TI_DBG1(("tiINIGetExpDeviceHandleBySasAddress: DeviceListList == agNULL\n")); + TI_DBG1(("tiINIGetExpDeviceHandleBySasAddress: seventh, returning not found, pid %d\n", onePortContext->id)); + return agNULL; + } + + while ((DeviceIndex < maxDevs) && + DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + + if(oneDeviceData == agNULL) + { + TI_DBG3(("tiINIGetExpDeviceHandleBySasAddress: oneDeviceData is NULL!!\n")); + return agNULL; + } + + + TI_DBG6(("tiINIGetExpDeviceHandleBySasAddress: handle %p\n", &(oneDeviceData->tiDeviceHandle))); + if (oneDeviceData->tdPortContext != onePortContext) + { + TI_DBG3(("tiINIGetExpDeviceHandleBySasAddress: different port\n")); + + if(DeviceListList != agNULL) + { + DeviceListList = DeviceListList->flink; + } + + } + else + { + + if ((oneDeviceData->valid == agTRUE) && + (oneDeviceData->registered == agTRUE) && + (oneDeviceData->tdPortContext == onePortContext) && + ( + (oneDeviceData->SASSpecDeviceType == SAS_EDGE_EXPANDER_DEVICE) || + (oneDeviceData->SASSpecDeviceType == SAS_FANOUT_EXPANDER_DEVICE) || + DEVICE_IS_SMP_TARGET(oneDeviceData) + ) + ) + + { + + if(oneDeviceData->SASAddressID.sasAddressLo == sas_addr_lo && oneDeviceData->SASAddressID.sasAddressHi == sas_addr_hi) + { + //TI_DBG3(("tiINIGetExpDeviceHandleBySasAddress: valid FoundDevices %d\n", FoundDevices)); + TI_DBG3(("tiINIGetExpDeviceHandleBySasAddress: agDevHandle %p\n", oneDeviceData->agDevHandle)); + TI_DBG3(("tiINIGetExpDeviceHandleBySasAddress: Matched sas address: low %x and high %x\n", oneDeviceData->SASAddressID.sasAddressLo, oneDeviceData->SASAddressID.sasAddressHi)); + return &(oneDeviceData->tiDeviceHandle); + } + } + DeviceIndex++; + DeviceListList = DeviceListList->flink; + } /* else */ + } + + return agNULL; +} + + + + +#ifdef TD_DISCOVER +/***************************************************************************** +*! \brief tdsaDiscover +* +* Purpose: This function is called to trigger topology discovery within a +* portcontext. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* \param type: Type of discovery. It can be SAS or SATA. +* \param option: discovery option. It can be Full or Incremental discovery. +* +* \return: +* tiSuccess Discovery initiated. +* tiError Discovery could not be initiated at this time. +* +* \note: +* +*****************************************************************************/ +osGLOBAL bit32 +tdsaDiscover( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + bit32 type, + bit32 option + ) + +{ + bit32 ret = tiError; + TI_DBG3(("tdsaDiscover: start\n")); + + if (onePortContext->valid == agFALSE) + { + TI_DBG1(("tdsaDiscover: aborting discovery\n")); + tdsaSASDiscoverAbort(tiRoot, onePortContext); + return ret; + } + + switch ( option ) + { + case TDSA_DISCOVERY_OPTION_FULL_START: + TI_DBG3(("tdsaDiscover: full\n")); + onePortContext->discovery.type = TDSA_DISCOVERY_OPTION_FULL_START; + if ( type == TDSA_DISCOVERY_TYPE_SAS ) + { + ret = tdsaSASFullDiscover(tiRoot, onePortContext); + } +#ifdef SATA_ENABLE + else if ( type == TDSA_DISCOVERY_TYPE_SATA ) + { + if (onePortContext->discovery.status == DISCOVERY_SAS_DONE) + { + ret = tdsaSATAFullDiscover(tiRoot, onePortContext); + } + } +#endif + break; + case TDSA_DISCOVERY_OPTION_INCREMENTAL_START: + TI_DBG3(("tdsaDiscover: incremental\n")); + onePortContext->discovery.type = TDSA_DISCOVERY_OPTION_INCREMENTAL_START; + if ( type == TDSA_DISCOVERY_TYPE_SAS ) + { + TI_DBG3(("tdsaDiscover: incremental SAS\n")); + ret = tdsaSASIncrementalDiscover(tiRoot, onePortContext); + } +#ifdef SATA_ENABLE + else if ( type == TDSA_DISCOVERY_TYPE_SATA ) + { + if (onePortContext->discovery.status == DISCOVERY_SAS_DONE) + { + TI_DBG3(("tdsaDiscover: incremental SATA\n")); + ret = tdsaSATAIncrementalDiscover(tiRoot, onePortContext); + } + } +#endif + break; + case TDSA_DISCOVERY_OPTION_ABORT: + TI_DBG1(("tdsaDiscover: abort\n")); + break; + default: + break; + + } + if (ret != tiSuccess) + { + TI_DBG1(("tdsaDiscover: fail, error 0x%x\n", ret)); + } + return ret; +} + +/***************************************************************************** +*! \brief tdsaSASFullDiscover +* +* Purpose: This function is called to trigger full SAS topology discovery +* within a portcontext. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* +* \return: +* tiSuccess Discovery initiated. +* tiError Discovery could not be initiated at this time. +* +* \note: +* +*****************************************************************************/ +osGLOBAL bit32 +tdsaSASFullDiscover( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdsaDeviceData_t *oneDeviceData = agNULL; + tdList_t *DeviceListList; + int i, j; + bit8 portMaxRate; + TI_DBG3(("tdsaSASFullDiscover: start\n")); + if (onePortContext->valid == agFALSE) + { + TI_DBG1(("tdsaSASFullDiscover: aborting discovery\n")); + tdsaSASDiscoverAbort(tiRoot, onePortContext); + return tiError; + } + /* + 1. abort all IO; may need a new LL API since TD does not queue IO's + 2. initializes(or invalidate) devices belonging to the port + 3. onePortContext->DiscoveryState == ITD_DSTATE_STARTED + 4. add directly connected one; if directed-SAS, spin-up + 5. tdsaSASUpStreamDiscoverStart(agRoot, pPort, pDevice) + */ + /* + invalidate all devices belonging to the portcontext except direct attached SAS/SATA + */ + DeviceListList = tdsaAllShared->MainDeviceList.flink; + while (DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + TI_DBG3(("tdsaSASFullDiscover: STARTED loop id %d\n", oneDeviceData->id)); + TI_DBG3(("tdsaSASFullDiscover: STARTED loop sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG3(("tdsaSASFullDiscover: STARTED loop sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + if (oneDeviceData->tdPortContext == onePortContext && + (onePortContext->nativeSATAMode == agFALSE && onePortContext->directAttatchedSAS == agFALSE) ) + + { + TI_DBG3(("tdsaSASFullDiscover: invalidate\n")); + oneDeviceData->valid = agFALSE; + oneDeviceData->processed = agFALSE; + } + else + { + TI_DBG3(("tdsaSASFullDiscover: not invalidate\n")); + /* no changes */ + } + DeviceListList = DeviceListList->flink; + } + + onePortContext->DiscoveryState = ITD_DSTATE_STARTED; + /* nativeSATAMode is set in ossaHwCB() in link up */ + if (onePortContext->nativeSATAMode == agFALSE) /* default: SAS and SAS/SATA mode */ + { + if (SA_IDFRM_GET_DEVICETTYPE(&onePortContext->sasIDframe) == SAS_END_DEVICE && + SA_IDFRM_IS_SSP_TARGET(&onePortContext->sasIDframe) ) + { + for(i=0;iPhyIDList[i] == agTRUE) + { + + for (j=0;jagRoot, agNULL, tdsaRotateQnumber(tiRoot, agNULL), i, AGSA_PHY_NOTIFY_ENABLE_SPINUP, agNULL); + } + break; + } + } + } + /* + add the device + 1. add device in TD layer + 2. call saRegisterNewDevice + 3. update agDevHandle in ossaDeviceRegistrationCB() + */ + portMaxRate = onePortContext->LinkRate; + oneDeviceData = tdsaPortSASDeviceAdd( + tiRoot, + onePortContext, + onePortContext->sasIDframe, + agFALSE, + portMaxRate, + IT_NEXUS_TIMEOUT, + 0, + SAS_DEVICE_TYPE, + agNULL, + 0xFF + ); + if (oneDeviceData) + { + if (oneDeviceData->registered == agFALSE) + { + /* + set the timer and wait till the device(directly attached. eg Expander) to be registered. + Then, in tdsaDeviceRegistrationTimerCB(), tdsaSASUpStreamDiscoverStart() is called + */ + tdsaDeviceRegistrationTimer(tiRoot, onePortContext, oneDeviceData); + } + else + { + tdsaSASUpStreamDiscoverStart(tiRoot, onePortContext, oneDeviceData); + } + } +#ifdef REMOVED + // temp testing code + tdsaReportManInfoSend(tiRoot, oneDeviceData); + //end temp testing code +#endif + } + else /* SATAOnlyMode*/ + { + tdsaSASDiscoverDone(tiRoot, onePortContext, tiSuccess); + } + + return tiSuccess; +} + +/***************************************************************************** +*! \brief tdsaSASUpStreamDiscoverStart +* +* Purpose: This function is called to trigger upstream traverse in topology +* within a portcontext. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* \param oneDeviceData: Pointer to the device data. +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaSASUpStreamDiscoverStart( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaDeviceData_t *oneDeviceData + ) +{ + tdsaExpander_t *oneExpander; + + TI_DBG3(("tdsaSASUpStreamDiscoverStart: start\n")); + + if (onePortContext->valid == agFALSE) + { + TI_DBG1(("tdsaSASUpStreamDiscoverStart: aborting discovery\n")); + tdsaSASDiscoverAbort(tiRoot, onePortContext); + return; + } + + /* + 1. update discovery state to UP_STREAM + 2. if (expander) add it + 3. tdsaSASUpStreamDiscovering + + */ + onePortContext->discovery.status = DISCOVERY_UP_STREAM; + if ( + (oneDeviceData->SASSpecDeviceType == SAS_EDGE_EXPANDER_DEVICE) + || + (oneDeviceData->SASSpecDeviceType == SAS_FANOUT_EXPANDER_DEVICE) + ) + { + oneExpander = tdssSASDiscoveringExpanderAlloc(tiRoot, onePortContext, oneDeviceData); + if ( oneExpander != agNULL) + { + /* (2.2.1) Add to discovering list */ + tdssSASDiscoveringExpanderAdd(tiRoot, onePortContext, oneExpander); + } + else + { + TI_DBG1(("tdsaSASUpStreamDiscoverStart: failed to allocate expander or discovey aborted\n")); + return; + } + } + + tdsaSASUpStreamDiscovering(tiRoot, onePortContext, oneDeviceData); + + return; +} + +/***************************************************************************** +*! \brief tdsaSASUpStreamDiscovering +* +* Purpose: For each expander in the expander list, this function sends SMP to +* find information for discovery and calls +* tdsaSASDownStreamDiscoverStart() function. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* \param oneDeviceData: Pointer to the device data. +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaSASUpStreamDiscovering( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaDeviceData_t *oneDeviceData + ) +{ + tdList_t *ExpanderList; + tdsaExpander_t *oneNextExpander = agNULL; + + TI_DBG3(("tdsaSASUpStreamDiscovering: start\n")); + if (onePortContext->valid == agFALSE) + { + TI_DBG1(("tdsaSASUpStreamDiscovering: aborting discovery\n")); + tdsaSASDiscoverAbort(tiRoot, onePortContext); + return; + } + /* + 1. find the next expander + 2. if (there is next expander) send report general with saSMPStart + else tdsaSASDownStreamDiscoverStart + + */ + tdsaSingleThreadedEnter(tiRoot, TD_DISC_LOCK); + if (TDLIST_EMPTY(&(onePortContext->discovery.discoveringExpanderList))) + { + tdsaSingleThreadedLeave(tiRoot, TD_DISC_LOCK); + TI_DBG3(("tdsaSASUpStreamDiscovering: should be the end\n")); + oneNextExpander = agNULL; + } + else + { + TDLIST_DEQUEUE_FROM_HEAD(&ExpanderList, &(onePortContext->discovery.discoveringExpanderList)); + oneNextExpander = TDLIST_OBJECT_BASE(tdsaExpander_t, linkNode, ExpanderList); + TDLIST_ENQUEUE_AT_HEAD(&(oneNextExpander->linkNode), &(onePortContext->discovery.discoveringExpanderList)); + tdsaSingleThreadedLeave(tiRoot, TD_DISC_LOCK); + + TI_DBG3(("tdssSASDiscoveringExpander tdsaSASUpStreamDiscovering: dequeue head\n")); + TI_DBG3(("tdsaSASUpStreamDiscovering: expander id %d\n", oneNextExpander->id)); + } + + if (oneNextExpander != agNULL) + { + tdsaReportGeneralSend(tiRoot, oneNextExpander->tdDevice); + } + else + { + TI_DBG3(("tdsaSASUpStreamDiscovering: No more expander list\n")); + tdsaSASDownStreamDiscoverStart(tiRoot, onePortContext, oneDeviceData); + } + + return; +} + +/***************************************************************************** +*! \brief tdsaSASDownStreamDiscoverStart +* +* Purpose: This function is called to trigger downstream traverse in topology +* within a portcontext. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* \param oneDeviceData: Pointer to the device data. +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaSASDownStreamDiscoverStart( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaDeviceData_t *oneDeviceData + ) +{ + tdsaExpander_t *oneExpander; + tdsaExpander_t *UpStreamExpander; + TI_DBG3(("tdsaSASDownStreamDiscoverStart: start\n")); + + if (onePortContext->valid == agFALSE) + { + TI_DBG1(("tdsaSASDownStreamDiscoverStart: aborting discovery\n")); + tdsaSASDiscoverAbort(tiRoot, onePortContext); + return; + } + /* + 1. update discover state + 2. if (expander is root) add it + else just add it + 3. tdsaSASDownStreamDiscovering + + */ + /* set discovery status */ + onePortContext->discovery.status = DISCOVERY_DOWN_STREAM; + + TI_DBG3(("tdsaSASDownStreamDiscoverStart: pPort=%p pDevice=%p\n", onePortContext, oneDeviceData)); + + /* If it's an expander */ + if ( (oneDeviceData->SASSpecDeviceType == SAS_EDGE_EXPANDER_DEVICE) + || (oneDeviceData->SASSpecDeviceType == SAS_FANOUT_EXPANDER_DEVICE)) + { + oneExpander = oneDeviceData->tdExpander; + UpStreamExpander = oneExpander->tdUpStreamExpander; + + /* If the two expanders are the root of two edge sets; sub-to-sub */ + if ( (UpStreamExpander != agNULL) && ( UpStreamExpander->tdUpStreamExpander == oneExpander ) ) + { + TI_DBG3(("tdsaSASDownStreamDiscoverStart: Root found pExpander=%p pUpStreamExpander=%p\n", + oneExpander, UpStreamExpander)); + //Saves the root expander + onePortContext->discovery.RootExp = oneExpander; + TI_DBG3(("tdsaSASDownStreamDiscoverStart: Root exp addrHi 0x%08x\n", oneExpander->tdDevice->SASAddressID.sasAddressHi)); + TI_DBG3(("tdsaSASDownStreamDiscoverStart: Root exp addrLo 0x%08x\n", oneExpander->tdDevice->SASAddressID.sasAddressLo)); + + /* reset up stream inform for pExpander */ + oneExpander->tdUpStreamExpander = agNULL; + /* Add the pExpander to discovering list */ + tdssSASDiscoveringExpanderAdd(tiRoot, onePortContext, oneExpander); + + /* reset up stream inform for oneExpander */ + UpStreamExpander->tdUpStreamExpander = agNULL; + /* Add the UpStreamExpander to discovering list */ + tdssSASDiscoveringExpanderAdd(tiRoot, onePortContext, UpStreamExpander); + } + /* If the two expanders are not the root of two edge sets. eg) one root */ + else + { + //Saves the root expander + onePortContext->discovery.RootExp = oneExpander; + + TI_DBG3(("tdsaSASDownStreamDiscoverStart: NO Root pExpander=%p\n", oneExpander)); + TI_DBG3(("tdsaSASDownStreamDiscoverStart: Root exp addrHi 0x%08x\n", oneExpander->tdDevice->SASAddressID.sasAddressHi)); + TI_DBG3(("tdsaSASDownStreamDiscoverStart: Root exp addrLo 0x%08x\n", oneExpander->tdDevice->SASAddressID.sasAddressLo)); + + /* (2.2.2.1) Add the pExpander to discovering list */ + tdssSASDiscoveringExpanderAdd(tiRoot, onePortContext, oneExpander); + } + } + + /* Continue down stream discovering */ + tdsaSASDownStreamDiscovering(tiRoot, onePortContext, oneDeviceData); + + return; +} + +/***************************************************************************** +*! \brief tdsaSASDownStreamDiscovering +* +* Purpose: For each expander in the expander list, this function sends SMP to +* find information for discovery and calls +* tdsaSASDownStreamDiscoverStart() function. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* \param oneDeviceData: Pointer to the device data. +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaSASDownStreamDiscovering( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaDeviceData_t *oneDeviceData + ) +{ + tdsaExpander_t *NextExpander = agNULL; + tdList_t *ExpanderList; + + TI_DBG3(("tdsaSASDownStreamDiscovering: start\n")); + + TI_DBG3(("tdsaSASDownStreamDiscovering: pPort=%p pDevice=%p\n", onePortContext, oneDeviceData)); + + if (onePortContext->valid == agFALSE) + { + TI_DBG1(("tdsaSASDownStreamDiscovering: aborting discovery\n")); + tdsaSASDiscoverAbort(tiRoot, onePortContext); + return; + } + + tdsaSingleThreadedEnter(tiRoot, TD_DISC_LOCK); + if (TDLIST_EMPTY(&(onePortContext->discovery.discoveringExpanderList))) + { + tdsaSingleThreadedLeave(tiRoot, TD_DISC_LOCK); + TI_DBG3(("tdsaSASDownStreamDiscovering: should be the end\n")); + NextExpander = agNULL; + } + else + { + TDLIST_DEQUEUE_FROM_HEAD(&ExpanderList, &(onePortContext->discovery.discoveringExpanderList));; + NextExpander = TDLIST_OBJECT_BASE(tdsaExpander_t, linkNode, ExpanderList); + TDLIST_ENQUEUE_AT_HEAD(&(NextExpander->linkNode), &(onePortContext->discovery.discoveringExpanderList));; + tdsaSingleThreadedLeave(tiRoot, TD_DISC_LOCK); + TI_DBG3(("tdssSASDiscoveringExpander tdsaSASDownStreamDiscovering: dequeue head\n")); + TI_DBG3(("tdsaSASDownStreamDiscovering: expander id %d\n", NextExpander->id)); + + } + + /* If there is an expander for continue discoving */ + if ( NextExpander != agNULL) + { + TI_DBG3(("tdsaSASDownStreamDiscovering: Found pNextExpander=%p\n, discoveryStatus=0x%x", + NextExpander, onePortContext->discovery.status)); + + switch (onePortContext->discovery.status) + { + /* If the discovery status is DISCOVERY_DOWN_STREAM */ + case DISCOVERY_DOWN_STREAM: + /* Send report general for the next expander */ + TI_DBG3(("tdsaSASDownStreamDiscovering: DownStream pNextExpander->pDevice=%p\n", NextExpander->tdDevice)); + tdsaReportGeneralSend(tiRoot, NextExpander->tdDevice); + break; + /* If the discovery status is DISCOVERY_CONFIG_ROUTING */ + case DISCOVERY_CONFIG_ROUTING: + case DISCOVERY_REPORT_PHY_SATA: + + /* set discovery status */ + onePortContext->discovery.status = DISCOVERY_DOWN_STREAM; + + TI_DBG3(("tdsaSASDownStreamDiscovering: pPort->discovery.status=DISCOVERY_CONFIG_ROUTING, nake it DOWN_STREAM\n")); + /* If not the last phy */ + if ( NextExpander->discoveringPhyId < NextExpander->tdDevice->numOfPhys ) + { + TI_DBG3(("tdsaSASDownStreamDiscovering: pNextExpander->discoveringPhyId=0x%x pNextExpander->pDevice->numOfPhys=0x%x. Send More Discover\n", + NextExpander->discoveringPhyId, NextExpander->tdDevice->numOfPhys)); + /* Send discover for the next expander */ + tdsaDiscoverSend(tiRoot, NextExpander->tdDevice); + } + /* If it's the last phy */ + else + { + TI_DBG3(("tdsaSASDownStreamDiscovering: Last Phy, remove expander%p start DownStream=%p\n", + NextExpander, NextExpander->tdDevice)); + tdssSASDiscoveringExpanderRemove(tiRoot, onePortContext, NextExpander); + tdsaSASDownStreamDiscovering(tiRoot, onePortContext, NextExpander->tdDevice); + } + break; + + default: + TI_DBG3(("tdsaSASDownStreamDiscovering: *** Unknown pPort->discovery.status=0x%x\n", onePortContext->discovery.status)); + } + } + /* If no expander for continue discoving */ + else + { + TI_DBG3(("tdsaSASDownStreamDiscovering: No more expander DONE\n")); + /* discover done */ + tdsaSASDiscoverDone(tiRoot, onePortContext, tiSuccess); + } + + return; +} + +/***************************************************************************** +*! \brief tdsaCleanAllExp +* +* Purpose: This function cleans up expander data structures after discovery +* is complete. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaCleanAllExp( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdList_t *ExpanderList; + tdsaExpander_t *tempExpander; + tdsaPortContext_t *tmpOnePortContext = onePortContext; + + TI_DBG3(("tdssSASDiscoveringExpander tdsaCleanAllExp: start\n")); + + TI_DBG3(("tdssSASDiscoveringExpander tdsaCleanAllExp: before all clean up\n")); + tdsaDumpAllFreeExp(tiRoot); + + /* clean up UpdiscoveringExpanderList*/ + TI_DBG3(("tdssSASDiscoveringExpander tdsaCleanAllExp: clean discoveringExpanderList\n")); + tdsaSingleThreadedEnter(tiRoot, TD_DISC_LOCK); + if (!TDLIST_EMPTY(&(tmpOnePortContext->discovery.discoveringExpanderList))) + { + tdsaSingleThreadedLeave(tiRoot, TD_DISC_LOCK); + ExpanderList = tmpOnePortContext->discovery.discoveringExpanderList.flink; + while (ExpanderList != &(tmpOnePortContext->discovery.discoveringExpanderList)) + { + tempExpander = TDLIST_OBJECT_BASE(tdsaExpander_t, linkNode, ExpanderList); + TI_DBG3(("tdssSASDiscoveringExpander tdsaCleanAllExp: exp addrHi 0x%08x\n", tempExpander->tdDevice->SASAddressID.sasAddressHi)); + TI_DBG3(("tdssSASDiscoveringExpander tdsaCleanAllExp: exp addrLo 0x%08x\n", tempExpander->tdDevice->SASAddressID.sasAddressLo)); + /* putting back to the free pool */ + tdsaSingleThreadedEnter(tiRoot, TD_DISC_LOCK); + TDLIST_DEQUEUE_THIS(&(tempExpander->linkNode)); + TDLIST_ENQUEUE_AT_TAIL(&(tempExpander->linkNode), &(tdsaAllShared->freeExpanderList)); + + if (TDLIST_EMPTY(&(tmpOnePortContext->discovery.discoveringExpanderList))) + { + tdsaSingleThreadedLeave(tiRoot, TD_DISC_LOCK); + break; + } + else + { + tdsaSingleThreadedLeave(tiRoot, TD_DISC_LOCK); + } + ExpanderList = tmpOnePortContext->discovery.discoveringExpanderList.flink; + +// ExpanderList = ExpanderList->flink; + } + } + else + { + tdsaSingleThreadedLeave(tiRoot, TD_DISC_LOCK); + TI_DBG3(("tdssSASDiscoveringExpander tdsaCleanAllExp: empty discoveringExpanderList\n")); + } + + /* reset UpdiscoveringExpanderList */ + TDLIST_INIT_HDR(&(tmpOnePortContext->discovery.UpdiscoveringExpanderList)); + + TI_DBG3(("tdssSASDiscoveringExpander tdsaCleanAllExp: after all clean up\n")); + tdsaDumpAllFreeExp(tiRoot); + + return; +} + +/***************************************************************************** +*! \brief tdsaFreeAllExp +* +* Purpose: This function frees up expander data structures as a part of +* soft reset. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaFreeAllExp( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdList_t *ExpanderList; + tdsaExpander_t *tempExpander; + tdsaPortContext_t *tmpOnePortContext = onePortContext; + + TI_DBG3(("tdssSASDiscoveringExpander tdsaFreeAllExp: start\n")); + + TI_DBG3(("tdssSASDiscoveringExpander tdsaFreeAllExp: before all clean up\n")); + tdsaDumpAllFreeExp(tiRoot); + + /* clean up UpdiscoveringExpanderList*/ + TI_DBG3(("tdssSASDiscoveringExpander tdsaFreeAllExp: clean discoveringExpanderList\n")); + tdsaSingleThreadedEnter(tiRoot, TD_DISC_LOCK); + if (!TDLIST_EMPTY(&(tmpOnePortContext->discovery.discoveringExpanderList))) + { + tdsaSingleThreadedLeave(tiRoot, TD_DISC_LOCK); + ExpanderList = tmpOnePortContext->discovery.discoveringExpanderList.flink; + while (ExpanderList != &(tmpOnePortContext->discovery.discoveringExpanderList)) + { + tempExpander = TDLIST_OBJECT_BASE(tdsaExpander_t, linkNode, ExpanderList); + TI_DBG3(("tdssSASDiscoveringExpander tdsaFreeAllExp: exp addrHi 0x%08x\n", tempExpander->tdDevice->SASAddressID.sasAddressHi)); + TI_DBG3(("tdssSASDiscoveringExpander tdsaFreeAllExp: exp addrLo 0x%08x\n", tempExpander->tdDevice->SASAddressID.sasAddressLo)); + /* putting back to the free pool */ + tdsaSingleThreadedEnter(tiRoot, TD_DISC_LOCK); + TDLIST_DEQUEUE_THIS(&(tempExpander->linkNode)); + TDLIST_ENQUEUE_AT_TAIL(&(tempExpander->linkNode), &(tdsaAllShared->freeExpanderList)); + + if (TDLIST_EMPTY(&(tmpOnePortContext->discovery.discoveringExpanderList))) + { + tdsaSingleThreadedLeave(tiRoot, TD_DISC_LOCK); + break; + } + else + { + tdsaSingleThreadedLeave(tiRoot, TD_DISC_LOCK); + } + ExpanderList = tmpOnePortContext->discovery.discoveringExpanderList.flink; + +// ExpanderList = ExpanderList->flink; + } + } + else + { + tdsaSingleThreadedLeave(tiRoot, TD_DISC_LOCK); + TI_DBG3(("tdssSASDiscoveringExpander tdsaFreeAllExp: empty discoveringExpanderList\n")); + } + + /* reset UpdiscoveringExpanderList */ + TDLIST_INIT_HDR(&(tmpOnePortContext->discovery.UpdiscoveringExpanderList)); + + return; +} +/***************************************************************************** +*! \brief tdsaResetValidDeviceData +* +* Purpose: This function resets valid and valid2 field for discovered devices +* in the device list. This is used only in incremental discovery. +* +* \param agRoot : Pointer to chip/driver Instance. +* \param onePortContext: Pointer to the portal context instance. +* \param oneDeviceData: Pointer to the device data. +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaResetValidDeviceData( + agsaRoot_t *agRoot, + tdsaPortContext_t *onePortContext + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdList_t *DeviceListList; + tdsaDeviceData_t *oneDeviceData; + + TI_DBG3(("tdsaResetValidDeviceData: start\n")); + + tdsaSingleThreadedEnter(tiRoot, TD_DEVICE_LOCK); + if (TDLIST_EMPTY(&(tdsaAllShared->MainDeviceList))) + { + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + TI_DBG1(("tdsaResetValidDeviceData: empty device list\n")); + } + else + { + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + DeviceListList = tdsaAllShared->MainDeviceList.flink; + while (DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + oneDeviceData->valid = oneDeviceData->valid2; + oneDeviceData->valid2 = agFALSE; + DeviceListList = DeviceListList->flink; + TI_DBG3(("tdsaResetValidDeviceData: valid %d valid2 %d\n", oneDeviceData->valid, oneDeviceData->valid2)); + } + } + + return; +} + +/***************************************************************************** +*! \brief tdssReportChanges +* +* Purpose: This function goes throuhg device list and finds out whether +* a device is removed and newly added. Based on the findings, +* this function notifies OS layer of the change. +* +* \param agRoot : Pointer to chip/driver Instance. +* \param onePortContext: Pointer to the portal context instance. +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdssReportChanges( + agsaRoot_t *agRoot, + tdsaPortContext_t *onePortContext + ) +{ + tdsaDeviceData_t *oneDeviceData = agNULL; + tdList_t *DeviceListList; + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + bit32 added = agFALSE, removed = agFALSE; + + TI_DBG1(("tdssReportChanges: start\n")); + + tdsaSingleThreadedEnter(tiRoot, TD_DEVICE_LOCK); + if (TDLIST_EMPTY(&(tdsaAllShared->MainDeviceList))) + { + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + TI_DBG1(("tdssReportChanges: empty device list\n")); + return; + } + else + { + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + } + DeviceListList = tdsaAllShared->MainDeviceList.flink; + while (DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + TI_DBG3(("tdssReportChanges: sasAddrHi 0x%08x \n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG3(("tdssReportChanges: sasAddrLo 0x%08x \n", oneDeviceData->SASAddressID.sasAddressLo)); + if ( oneDeviceData->tdPortContext == onePortContext) + { + TI_DBG3(("tdssReportChanges: right portcontext\n")); + if ( (oneDeviceData->valid == agTRUE) && (oneDeviceData->valid2 == agTRUE) ) + { + TI_DBG3(("tdssReportChanges: same\n")); + /* reset valid bit */ + oneDeviceData->valid = oneDeviceData->valid2; + oneDeviceData->valid2 = agFALSE; + } + else if ( (oneDeviceData->valid == agTRUE) && (oneDeviceData->valid2 == agFALSE) ) + { + TI_DBG3(("tdssReportChanges: removed\n")); + removed = agTRUE; + /* reset valid bit */ + oneDeviceData->valid = oneDeviceData->valid2; + oneDeviceData->valid2 = agFALSE; + /* reset NumOfFCA */ + oneDeviceData->satDevData.NumOfFCA = 0; + + if ( (oneDeviceData->registered == agTRUE) && + ( DEVICE_IS_SSP_TARGET(oneDeviceData) || DEVICE_IS_STP_TARGET(oneDeviceData) + || DEVICE_IS_SATA_DEVICE(oneDeviceData) || DEVICE_IS_SMP_TARGET(oneDeviceData) ) + ) + { + tdsaAbortAll(tiRoot, agRoot, oneDeviceData); + } + else if (oneDeviceData->registered == agTRUE) + { + TI_DBG1(("tdssReportChanges: calling saDeregisterDeviceHandle, did %d\n", oneDeviceData->id)); + saDeregisterDeviceHandle(agRoot, agNULL, oneDeviceData->agDevHandle, 0); + } + + oneDeviceData->registered = agFALSE; + +#ifdef REMOVED /* don't remove device from the device list. May screw up ordering of report */ + TDLIST_DEQUEUE_THIS(&(oneDeviceData->MainLink)); + TDLIST_ENQUEUE_AT_TAIL(&(oneDeviceData->FreeLink), &(tdsaAllShared->FreeDeviceList)); +#endif + } + else if ( (oneDeviceData->valid == agFALSE) && (oneDeviceData->valid2 == agTRUE) ) + { + TI_DBG3(("tdssReportChanges: added\n")); + added = agTRUE; + /* reset valid bit */ + oneDeviceData->valid = oneDeviceData->valid2; + oneDeviceData->valid2 = agFALSE; + } + else + { + TI_DBG6(("tdssReportChanges: else\n")); + } + } + else + { + TI_DBG1(("tdssReportChanges: different portcontext\n")); + } + DeviceListList = DeviceListList->flink; + } + /* arrival or removal at once */ + if (added == agTRUE) + { + TI_DBG3(("tdssReportChanges: added at the end\n")); +#ifdef AGTIAPI_CTL + if (tdsaAllShared->SASConnectTimeLimit) + tdsaCTLSet(tiRoot, onePortContext, tiIntrEventTypeDeviceChange, + tiDeviceArrival); + else +#endif + ostiInitiatorEvent( + tiRoot, + onePortContext->tiPortalContext, + agNULL, + tiIntrEventTypeDeviceChange, + tiDeviceArrival, + agNULL + ); + + } + if (removed == agTRUE) + { + TI_DBG3(("tdssReportChanges: removed at the end\n")); + ostiInitiatorEvent( + tiRoot, + onePortContext->tiPortalContext, + agNULL, + tiIntrEventTypeDeviceChange, + tiDeviceRemoval, + agNULL + ); + } + + if (onePortContext->discovery.forcedOK == agTRUE && added == agFALSE && removed == agFALSE) + { + TI_DBG1(("tdssReportChanges: missed chance to report. forced to report OK\n")); + onePortContext->discovery.forcedOK = agFALSE; + ostiInitiatorEvent( + tiRoot, + onePortContext->tiPortalContext, + agNULL, + tiIntrEventTypeDiscovery, + tiDiscOK, + agNULL + ); + } + + if (added == agFALSE && removed == agFALSE) + { + TI_DBG3(("tdssReportChanges: the same\n")); + } + return; +} +/***************************************************************************** +*! \brief tdssReportRemovals +* +* Purpose: This function goes through device list and removes all devices +* belong to the portcontext. This function also deregiters those +* devices. This function is called in case of incremental discovery +* failure. +* +* \param agRoot : Pointer to chip/driver Instance. +* \param onePortContext: Pointer to the portal context instance. +* \param oneDeviceData: Pointer to the device data. +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdssReportRemovals( + agsaRoot_t *agRoot, + tdsaPortContext_t *onePortContext, + bit32 flag + ) +{ + tdsaDeviceData_t *oneDeviceData = agNULL; + tdList_t *DeviceListList; + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + bit32 removed = agFALSE; + agsaEventSource_t *eventSource; + bit32 PhyID; + bit32 HwAckSatus; + agsaDevHandle_t *agDevHandle = agNULL; + + TI_DBG2(("tdssReportRemovals: start\n")); + /* in case nothing was registered */ + PhyID = onePortContext->eventPhyID; + if (tdsaAllShared->eventSource[PhyID].EventValid == agTRUE && + onePortContext->RegisteredDevNums == 0 && + PhyID != 0xFF + ) + { + TI_DBG2(("tdssReportRemovals: calling saHwEventAck\n")); + eventSource = &(tdsaAllShared->eventSource[PhyID].Source); + HwAckSatus = saHwEventAck( + agRoot, + agNULL, /* agContext */ + 0, + eventSource, /* agsaEventSource_t */ + 0, + 0 + ); + if ( HwAckSatus != AGSA_RC_SUCCESS) + { + TI_DBG1(("tdssReportRemovals: failing in saHwEventAck; status %d\n", HwAckSatus)); + } + + /* toggle */ + tdsaAllShared->eventSource[PhyID].EventValid = agFALSE; + if (onePortContext->valid == agFALSE) + { + /* put device belonging to the port to freedevice list */ + DeviceListList = tdsaAllShared->MainDeviceList.flink; + while (DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData->tdPortContext == onePortContext) + { + osti_memset(&(oneDeviceData->satDevData.satIdentifyData), 0xFF, sizeof(agsaSATAIdentifyData_t)); + tdsaSingleThreadedEnter(tiRoot, TD_DEVICE_LOCK); + TDLIST_DEQUEUE_THIS(&(oneDeviceData->MainLink)); + TDLIST_ENQUEUE_AT_TAIL(&(oneDeviceData->FreeLink), &(tdsaAllShared->FreeDeviceList)); + if (TDLIST_EMPTY(&(tdsaAllShared->MainDeviceList))) + { + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + break; + } + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + DeviceListList = tdsaAllShared->MainDeviceList.flink; + } + else + { + DeviceListList = DeviceListList->flink; + } + } /* while */ + + tdsaPortContextReInit(tiRoot, onePortContext); + /* + put all devices belonging to the onePortContext + back to the free link + */ + tdsaSingleThreadedEnter(tiRoot, TD_PORT_LOCK); + TDLIST_DEQUEUE_THIS(&(onePortContext->MainLink)); + TDLIST_ENQUEUE_AT_TAIL(&(onePortContext->FreeLink), &(tdsaAllShared->FreePortContextList)); + tdsaSingleThreadedLeave(tiRoot, TD_PORT_LOCK); + } + } + + else + { + tdsaSingleThreadedEnter(tiRoot, TD_DEVICE_LOCK); + if (TDLIST_EMPTY(&(tdsaAllShared->MainDeviceList))) + { + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + TI_DBG1(("tdssReportRemovals: 1st empty device list\n")); + return; + } + else + { + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + } + DeviceListList = tdsaAllShared->MainDeviceList.flink; + /* needs to clean up devices which were not removed in ossaDeregisterDeviceHandleCB() since port was in valid (discovery error) */ + while (DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + TI_DBG1(("tdssReportRemovals: oneDeviceData is NULL!!!\n")); + return; + } + TI_DBG2(("tdssReportRemovals: 1st loop did %d\n", oneDeviceData->id)); + TI_DBG2(("tdssReportRemovals: sasAddrHi 0x%08x \n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG2(("tdssReportRemovals: sasAddrLo 0x%08x \n", oneDeviceData->SASAddressID.sasAddressLo)); + TI_DBG2(("tdssReportRemovals: valid %d\n", oneDeviceData->valid)); + TI_DBG2(("tdssReportRemovals: valid2 %d\n", oneDeviceData->valid2)); + TI_DBG2(("tdssReportRemovals: directlyAttached %d\n", oneDeviceData->directlyAttached)); + TI_DBG2(("tdssReportRemovals: registered %d\n", oneDeviceData->registered)); + if ( oneDeviceData->tdPortContext == onePortContext && oneDeviceData->valid == agFALSE && + oneDeviceData->valid2 == agFALSE && oneDeviceData->registered == agFALSE + ) + { + /* remove oneDevice from MainLink */ + TI_DBG2(("tdssReportRemovals: delete from MainLink\n")); + agDevHandle = oneDeviceData->agDevHandle; + tdsaDeviceDataReInit(tiRoot, oneDeviceData); + //save agDevHandle and tdPortContext + oneDeviceData->agDevHandle = agDevHandle; + oneDeviceData->tdPortContext = onePortContext; + osti_memset(&(oneDeviceData->satDevData.satIdentifyData), 0xFF, sizeof(agsaSATAIdentifyData_t)); + tdsaSingleThreadedEnter(tiRoot, TD_DEVICE_LOCK); + TDLIST_DEQUEUE_THIS(&(oneDeviceData->MainLink)); + TDLIST_ENQUEUE_AT_TAIL(&(oneDeviceData->FreeLink), &(tdsaAllShared->FreeDeviceList)); + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + DeviceListList = tdsaAllShared->MainDeviceList.flink; + tdsaSingleThreadedEnter(tiRoot, TD_DEVICE_LOCK); + if (TDLIST_EMPTY(&(tdsaAllShared->MainDeviceList))) + { + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + break; + } + else + { + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + } + } + else + { + DeviceListList = DeviceListList->flink; + } + } /* while */ + + + tdsaSingleThreadedEnter(tiRoot, TD_DEVICE_LOCK); + if (TDLIST_EMPTY(&(tdsaAllShared->MainDeviceList))) + { + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + TI_DBG1(("tdssReportRemovals: 2nd empty device list\n")); + return; + } + else + { + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + } + DeviceListList = tdsaAllShared->MainDeviceList.flink; + while (DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + if (oneDeviceData == agNULL) + { + TI_DBG1(("tdssReportRemovals: oneDeviceData is NULL!!!\n")); + return; + } + TI_DBG2(("tdssReportRemovals: loop did %d\n", oneDeviceData->id)); + TI_DBG2(("tdssReportRemovals: sasAddrHi 0x%08x \n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG2(("tdssReportRemovals: sasAddrLo 0x%08x \n", oneDeviceData->SASAddressID.sasAddressLo)); + TI_DBG2(("tdssReportRemovals: valid %d\n", oneDeviceData->valid)); + TI_DBG2(("tdssReportRemovals: valid2 %d\n", oneDeviceData->valid2)); + TI_DBG2(("tdssReportRemovals: directlyAttached %d\n", oneDeviceData->directlyAttached)); + TI_DBG2(("tdssReportRemovals: registered %d\n", oneDeviceData->registered)); + if ( oneDeviceData->tdPortContext == onePortContext) + { + TI_DBG2(("tdssReportRemovals: right portcontext pid %d\n", onePortContext->id)); + if (oneDeviceData->valid == agTRUE && oneDeviceData->registered == agTRUE) + { + TI_DBG2(("tdssReportRemovals: removing\n")); + + /* notify only reported devices to OS layer*/ + if ( DEVICE_IS_SSP_TARGET(oneDeviceData) || + DEVICE_IS_STP_TARGET(oneDeviceData) || + DEVICE_IS_SATA_DEVICE(oneDeviceData) + ) + { + removed = agTRUE; + } + + if ( (oneDeviceData->registered == agTRUE) && + ( DEVICE_IS_SSP_TARGET(oneDeviceData) || DEVICE_IS_STP_TARGET(oneDeviceData) + || DEVICE_IS_SATA_DEVICE(oneDeviceData) || DEVICE_IS_SMP_TARGET(oneDeviceData) ) + ) + { + /* all targets except expanders */ + TI_DBG2(("tdssReportRemovals: calling tdsaAbortAll\n")); + TI_DBG2(("tdssReportRemovals: did %d\n", oneDeviceData->id)); + TI_DBG2(("tdssReportRemovals: sasAddrHi 0x%08x \n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG2(("tdssReportRemovals: sasAddrLo 0x%08x \n", oneDeviceData->SASAddressID.sasAddressLo)); + tdsaAbortAll(tiRoot, agRoot, oneDeviceData); + } + else if (oneDeviceData->registered == agTRUE) + { + /* expanders */ + TI_DBG1(("tdssReportRemovals: calling saDeregisterDeviceHandle, did %d\n", oneDeviceData->id)); + TI_DBG2(("tdssReportRemovals: sasAddrHi 0x%08x \n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG2(("tdssReportRemovals: sasAddrLo 0x%08x \n", oneDeviceData->SASAddressID.sasAddressLo)); + saDeregisterDeviceHandle(agRoot, agNULL, oneDeviceData->agDevHandle, 0); + } + + /* reset valid bit */ + oneDeviceData->valid = agFALSE; + oneDeviceData->valid2 = agFALSE; + oneDeviceData->registered = agFALSE; + /* reset NumOfFCA */ + oneDeviceData->satDevData.NumOfFCA = 0; + + } + /* called by port invalid case */ + if (flag == agTRUE) + { + oneDeviceData->tdPortContext = agNULL; + TI_DBG1(("tdssReportRemovals: nulling-out tdPortContext; oneDeviceData did %d\n", oneDeviceData->id)); + } +#ifdef REMOVED /* removed */ + /* directly attached SATA -> always remove it */ + if (oneDeviceData->DeviceType == TD_SATA_DEVICE && + oneDeviceData->directlyAttached == agTRUE) + { + TI_DBG1(("tdssReportRemovals: device did %d\n", oneDeviceData->id)); + TDLIST_DEQUEUE_THIS(&(oneDeviceData->MainLink)); + TDLIST_ENQUEUE_AT_TAIL(&(oneDeviceData->FreeLink), &(tdsaAllShared->FreeDeviceLis)); + DeviceListList = tdsaAllShared->MainDeviceList.flink; + if (TDLIST_EMPTY(&(tdsaAllShared->MainDeviceList))) + { + break; + } + } + else + { + DeviceListList = DeviceListList->flink; + } +#endif /* REMOVED */ + DeviceListList = DeviceListList->flink; + } + else + { + if (oneDeviceData->tdPortContext != agNULL) + { + TI_DBG2(("tdssReportRemovals: different portcontext; oneDeviceData->tdPortContext pid %d oneportcontext pid %d oneDeviceData did %d\n", + oneDeviceData->tdPortContext->id, onePortContext->id, oneDeviceData->id)); + } + else + { + TI_DBG1(("tdssReportRemovals: different portcontext; oneDeviceData->tdPortContext pid NULL oneportcontext pid %d oneDeviceData did %d\n", + onePortContext->id, oneDeviceData->id)); + } + DeviceListList = DeviceListList->flink; + } + } + + if (removed == agTRUE) + { + TI_DBG2(("tdssReportRemovals: removed at the end\n")); + ostiInitiatorEvent( + tiRoot, + onePortContext->tiPortalContext, + agNULL, + tiIntrEventTypeDeviceChange, + tiDeviceRemoval, + agNULL + ); + } + } /* big else */ + return; +} + +/* + changes valid and valid2 based on discovery type +*/ +osGLOBAL void +tdssInternalRemovals( + agsaRoot_t *agRoot, + tdsaPortContext_t *onePortContext + ) +{ + tdsaDeviceData_t *oneDeviceData = agNULL; + tdList_t *DeviceListList; + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + + TI_DBG2(("tdssInternalRemovals: start\n")); + + tdsaSingleThreadedEnter(tiRoot, TD_DEVICE_LOCK); + if (TDLIST_EMPTY(&(tdsaAllShared->MainDeviceList))) + { + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + TI_DBG1(("tdssInternalRemovals: empty device list\n")); + return; + } + else + { + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + } + DeviceListList = tdsaAllShared->MainDeviceList.flink; + while (DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + TI_DBG3(("tdssInternalRemovals: loop did %d\n", oneDeviceData->id)); + TI_DBG3(("tdssInternalRemovals: sasAddrHi 0x%08x \n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG3(("tdssInternalRemovals: sasAddrLo 0x%08x \n", oneDeviceData->SASAddressID.sasAddressLo)); + TI_DBG3(("tdssInternalRemovals: valid %d\n", oneDeviceData->valid)); + TI_DBG3(("tdssInternalRemovals: valid2 %d\n", oneDeviceData->valid2)); + TI_DBG3(("tdssInternalRemovals: directlyAttached %d\n", oneDeviceData->directlyAttached)); + TI_DBG3(("tdssInternalRemovals: registered %d\n", oneDeviceData->registered)); + if ( oneDeviceData->tdPortContext == onePortContext) + { + TI_DBG3(("tdssInternalRemovals: right portcontext pid %d\n", onePortContext->id)); + if (onePortContext->discovery.type == TDSA_DISCOVERY_OPTION_INCREMENTAL_START) + { + TI_DBG3(("tdssInternalRemovals: incremental discovery\n")); + oneDeviceData->valid2 = agFALSE; + } + else + { + TI_DBG3(("tdssInternalRemovals: full discovery\n")); + oneDeviceData->valid = agFALSE; + } + DeviceListList = DeviceListList->flink; + } + else + { + if (oneDeviceData->tdPortContext != agNULL) + { + TI_DBG3(("tdssInternalRemovals: different portcontext; oneDeviceData->tdPortContext pid %d oneportcontext pid %d\n", oneDeviceData->tdPortContext->id, onePortContext->id)); + } + else + { + TI_DBG3(("tdssInternalRemovals: different portcontext; oneDeviceData->tdPortContext pid NULL oneportcontext pid %d\n", onePortContext->id)); + } + DeviceListList = DeviceListList->flink; + } + } + + + return; +} + +/* resets all valid and valid2 */ +osGLOBAL void +tdssDiscoveryErrorRemovals( + agsaRoot_t *agRoot, + tdsaPortContext_t *onePortContext + ) +{ + tdsaDeviceData_t *oneDeviceData = agNULL; + tdList_t *DeviceListList; + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + + TI_DBG1(("tdssDiscoveryErrorRemovals: start\n")); + + tdsaSingleThreadedEnter(tiRoot, TD_DEVICE_LOCK); + if (TDLIST_EMPTY(&(tdsaAllShared->MainDeviceList))) + { + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + TI_DBG1(("tdssDiscoveryErrorRemovals: empty device list\n")); + return; + } + else + { + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + } + DeviceListList = tdsaAllShared->MainDeviceList.flink; + while (DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + TI_DBG2(("tdssDiscoveryErrorRemovals: loop did %d\n", oneDeviceData->id)); + TI_DBG2(("tdssDiscoveryErrorRemovals: sasAddrHi 0x%08x \n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG2(("tdssDiscoveryErrorRemovals: sasAddrLo 0x%08x \n", oneDeviceData->SASAddressID.sasAddressLo)); + TI_DBG2(("tdssDiscoveryErrorRemovals: valid %d\n", oneDeviceData->valid)); + TI_DBG2(("tdssDiscoveryErrorRemovals: valid2 %d\n", oneDeviceData->valid2)); + TI_DBG2(("tdssDiscoveryErrorRemovals: directlyAttached %d\n", oneDeviceData->directlyAttached)); + TI_DBG2(("tdssDiscoveryErrorRemovals: registered %d\n", oneDeviceData->registered)); + if ( oneDeviceData->tdPortContext == onePortContext) + { + TI_DBG2(("tdssDiscoveryErrorRemovals: right portcontext pid %d\n", onePortContext->id)); + oneDeviceData->valid = agFALSE; + oneDeviceData->valid2 = agFALSE; + /* reset NumOfFCA */ + oneDeviceData->satDevData.NumOfFCA = 0; + + if ( (oneDeviceData->registered == agTRUE) && + ( DEVICE_IS_SSP_TARGET(oneDeviceData) || DEVICE_IS_STP_TARGET(oneDeviceData) + || DEVICE_IS_SATA_DEVICE(oneDeviceData) || DEVICE_IS_SMP_TARGET(oneDeviceData) ) + ) + { + /* all targets other than expanders */ + TI_DBG2(("tdssDiscoveryErrorRemovals: calling tdsaAbortAll\n")); + TI_DBG2(("tdssDiscoveryErrorRemovals: did %d\n", oneDeviceData->id)); + TI_DBG2(("tdssDiscoveryErrorRemovals: sasAddrHi 0x%08x \n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG2(("tdssDiscoveryErrorRemovals: sasAddrLo 0x%08x \n", oneDeviceData->SASAddressID.sasAddressLo)); + tdsaAbortAll(tiRoot, agRoot, oneDeviceData); + } + else if (oneDeviceData->registered == agTRUE) + { + /* expanders */ + TI_DBG2(("tdssDiscoveryErrorRemovals: calling saDeregisterDeviceHandle\n")); + TI_DBG2(("tdssDiscoveryErrorRemovals: did %d\n", oneDeviceData->id)); + TI_DBG2(("tdssDiscoveryErrorRemovals: sasAddrHi 0x%08x \n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG2(("tdssDiscoveryErrorRemovals: sasAddrLo 0x%08x \n", oneDeviceData->SASAddressID.sasAddressLo)); + saDeregisterDeviceHandle(agRoot, agNULL, oneDeviceData->agDevHandle, 0); + } + + oneDeviceData->registered = agFALSE; + DeviceListList = DeviceListList->flink; + } + else + { + if (oneDeviceData->tdPortContext != agNULL) + { + TI_DBG2(("tdssDiscoveryErrorRemovals: different portcontext; oneDeviceData->tdPortContext pid %d oneportcontext pid %d\n", oneDeviceData->tdPortContext->id, onePortContext->id)); + } + else + { + TI_DBG2(("tdssDiscoveryErrorRemovals: different portcontext; oneDeviceData->tdPortContext pid NULL oneportcontext pid %d\n", onePortContext->id)); + } + DeviceListList = DeviceListList->flink; + } + } + + + return; +} + +/***************************************************************************** +*! \brief tdsaSASDiscoverAbort +* +* Purpose: This function aborts on-going discovery. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +/* this called when discovery is aborted + aborted by whom +*/ +osGLOBAL void +tdsaSASDiscoverAbort( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext + ) +{ + + TI_DBG2(("tdsaSASDiscoverAbort: start\n")); + TI_DBG2(("tdsaSASDiscoverAbort: pPort=%p DONE\n", onePortContext)); + TI_DBG2(("tdsaSASDiscoverAbort: DiscoveryState %d\n", onePortContext->DiscoveryState)); + + onePortContext->DiscoveryState = ITD_DSTATE_COMPLETED; + /* clean up expanders data strucures; move to free exp when device is cleaned */ + tdsaCleanAllExp(tiRoot, onePortContext); + + /* unregister devices */ + tdssReportRemovals(onePortContext->agRoot, + onePortContext, + agFALSE + ); +} + +#ifdef AGTIAPI_CTL + +STATIC void +tdsaCTLNextDevice( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdIORequest_t *tdIORequest, + tdList_t *DeviceList); + +STATIC void +tdsaCTLIOCompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit16 sspTag, + bit32 agOtherInfo) +{ + tiRoot_t *tiRoot = (tiRoot_t*) + ((tdsaRootOsData_t*)agRoot->osData)->tiRoot; + tdIORequestBody_t *tdIORequestBody; + tdIORequest_t *tdIORequest; + tdsaDeviceData_t *oneDeviceData; + + tdIORequest = (tdIORequest_t *)agIORequest->osData; + tdIORequestBody = &tdIORequest->tdIORequestBody; + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + oneDeviceData = (tdsaDeviceData_t *)tdIORequestBody->tiDevHandle->tdData; + + TI_DBG6(("tdsaCTLIOCompleted: stat x%x len %d id %d\n", agIOStatus, + agIOInfoLen, oneDeviceData->id)); + + //if ((agIOStatus == OSSA_IO_SUCCESS) && (agIOInfoLen == 0)) + /* SCSI command was completed OK, this is the normal path. */ + if (agIOInfoLen) + { + TI_DBG6(("tdsaCTLIOCompleted: SASDevAddr 0x%x / 0x%x PhyId 0x%x WARN " + "setting CTL\n", + oneDeviceData->SASAddressID.sasAddressHi, + oneDeviceData->SASAddressID.sasAddressLo, + oneDeviceData->SASAddressID.phyIdentifier)); + tdhexdump("tdsaCTLIOCompleted: response", (bit8 *)agParam, agIOInfoLen); + } + + tdsaCTLNextDevice(tiRoot, oneDeviceData->tdPortContext, tdIORequest, + oneDeviceData->MainLink.flink); +} /* tdsaCTLIOCompleted */ + +STATIC int +tdsaCTLModeSelect( + tiRoot_t *tiRoot, + tiDeviceHandle_t *tiDeviceHandle, + tdIORequest_t *tdIORequest) +{ + tiIORequest_t *tiIORequest; + tdsaDeviceData_t *oneDeviceData; + agsaRoot_t *agRoot = agNULL; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t*)tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t*) + &tdsaRoot->tdsaAllShared; + agsaIORequest_t *agIORequest = agNULL; + agsaDevHandle_t *agDevHandle = agNULL; + agsaSASRequestBody_t *agSASRequestBody = agNULL; + bit32 tiStatus; + bit32 saStatus; + tdIORequestBody_t *tdIORequestBody; + agsaSSPInitiatorRequest_t *agSSPInitiatorRequest; + unsigned char *virtAddr; + tiSgl_t agSgl; + static unsigned char cdb[6] = + { + MODE_SELECT, + PAGE_FORMAT, + 0, + 0, + DR_MODE_PG_SZ + }; + + virtAddr = (unsigned char*)tdIORequest->virtAddr; + virtAddr[0] = DR_MODE_PG_CODE; /* Disconnect-Reconnect mode page code */ + virtAddr[1] = DR_MODE_PG_LENGTH; /* DR Mode pg length */ + virtAddr[8] = tdsaAllShared->SASConnectTimeLimit >> 8; + virtAddr[9] = tdsaAllShared->SASConnectTimeLimit & 0xff; + + oneDeviceData = (tdsaDeviceData_t*)tiDeviceHandle->tdData; + TI_DBG4(("tdsaCTLModeSelect: id %d\n", oneDeviceData->id)); + + agRoot = oneDeviceData->agRoot; + agDevHandle = oneDeviceData->agDevHandle; + tiIORequest = &tdIORequest->tiIORequest; + + tdIORequestBody = &tdIORequest->tdIORequestBody; + + //tdIORequestBody->IOCompletionFunc = tdsaCTLIOCompleted;//itdssIOCompleted; + tdIORequestBody->tiDevHandle = tiDeviceHandle; + tdIORequestBody->IOType.InitiatorRegIO.expDataLength = DR_MODE_PG_SZ; + + agIORequest = &tdIORequestBody->agIORequest; + agIORequest->sdkData = agNULL; /* LL takes care of this */ + + agSASRequestBody = &(tdIORequestBody->transport.SAS.agSASRequestBody); + agSSPInitiatorRequest = &(agSASRequestBody->sspInitiatorReq); + + osti_memcpy(agSSPInitiatorRequest->sspCmdIU.cdb, cdb, 6); + agSSPInitiatorRequest->dataLength = DR_MODE_PG_SZ; + + agSSPInitiatorRequest->firstBurstSize = 0; + + tdIORequestBody->agRequestType = AGSA_SSP_INIT_WRITE; + tdIORequestBody->ioStarted = agTRUE; + tdIORequestBody->ioCompleted = agFALSE; + + agSgl.lower = BIT32_TO_LEBIT32(tdIORequest->physLower32); +#if (BITS_PER_LONG > 32) + agSgl.upper = BIT32_TO_LEBIT32(tdIORequest->physUpper32); +#else + agSgl1.upper = 0; +#endif + agSgl.type = BIT32_TO_LEBIT32(tiSgl); + agSgl.len = BIT32_TO_LEBIT32(DR_MODE_PG_SZ); + + /* initializes "agsaSgl_t agSgl" of "agsaDifSSPInitiatorRequest_t" */ + tiStatus = itdssIOPrepareSGL(tiRoot, tdIORequestBody, &agSgl, + tdIORequest->virtAddr); + if (tiStatus != tiSuccess) + { + TI_DBG1(("tdsaCTLModeSelect: can't get SGL\n")); + ostiFreeMemory(tiRoot, tdIORequest->osMemHandle2, DR_MODE_PG_SZ); + ostiFreeMemory(tiRoot, tdIORequest->osMemHandle, sizeof(*tdIORequest)); + return tiError; + } + + saStatus = saSSPStart(agRoot, agIORequest, + tdsaRotateQnumber(tiRoot, oneDeviceData), agDevHandle, + AGSA_SSP_INIT_WRITE, agSASRequestBody, agNULL, + &tdsaCTLIOCompleted); + if (saStatus == AGSA_RC_SUCCESS) + { + tiStatus = tiSuccess; + TI_DBG4(("tdsaCTLModeSelect: saSSPStart OK\n")); + } + else + { + tdIORequestBody->ioStarted = agFALSE; + tdIORequestBody->ioCompleted = agTRUE; + if (saStatus == AGSA_RC_BUSY) + { + tiStatus = tiBusy; + TI_DBG4(("tdsaCTLModeSelect: saSSPStart busy\n")); + } + else + { + tiStatus = tiError; + TI_DBG4(("tdsaCTLModeSelect: saSSPStart Error\n")); + } + tdsaCTLNextDevice(tiRoot, oneDeviceData->tdPortContext, tdIORequest, + oneDeviceData->MainLink.flink); + } + return tiStatus; +} /* tdsaCTLModeSelect */ + +STATIC void +tdsaCTLNextDevice( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdIORequest_t *tdIORequest, + tdList_t *DeviceList) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *)tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdsaDeviceData_t *oneDeviceData; + tiIntrEventType_t eventType; + bit32 eventStatus; + int rc; + + /* + * From the device list, returns only valid devices + */ + for (; DeviceList && DeviceList != &(tdsaAllShared->MainDeviceList); + DeviceList = DeviceList->flink) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceList); + TI_DBG6(("tdsaCTLNextDevice: devHandle %p\n", + &(oneDeviceData->tiDeviceHandle))); + if (oneDeviceData->tdPortContext != onePortContext) + continue; + if ((oneDeviceData->discovered == agFALSE) && + (oneDeviceData->registered == agTRUE) && + DEVICE_IS_SSP_TARGET(oneDeviceData) && + !DEVICE_IS_SSP_INITIATOR(oneDeviceData)) + { + oneDeviceData->discovered = agTRUE; + rc = tdsaCTLModeSelect(tiRoot, &oneDeviceData->tiDeviceHandle, + tdIORequest); + TI_DBG1(("tdsaCTLNextDevice: ModeSelect ret %d\n", rc)); + return; + } + } + TI_DBG2(("tdsaCTLNextDevice: no more devices found\n")); + + eventType = tdIORequest->eventType; + eventStatus = tdIORequest->eventStatus; + + /* no more devices, free the memory */ + ostiFreeMemory(tiRoot, tdIORequest->osMemHandle2, DR_MODE_PG_SZ); + ostiFreeMemory(tiRoot, tdIORequest->osMemHandle, sizeof(*tdIORequest)); + + /* send Discovery Done event */ + ostiInitiatorEvent(tiRoot, onePortContext->tiPortalContext, agNULL, + eventType, eventStatus, agNULL); +} /* tdsaCTLNextDevice */ + +osGLOBAL void +tdsaCTLSet( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tiIntrEventType_t eventType, + bit32 eventStatus) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *)tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequest_t *tdIORequest; + tdIORequestBody_t *tdIORequestBody; + tiIORequest_t *tiIORequest; + bit32 memAllocStatus; + void *osMemHandle; + bit32 physUpper32; + bit32 physLower32; + + TI_DBG2(("tdsaCTLSet: tiPortalContext pid %d etyp %x stat %x\n", + onePortContext->id, eventType, eventStatus)); + + if (onePortContext->DiscoveryState != ITD_DSTATE_COMPLETED) + { + TI_DBG1(("tdsaCTLSet: discovery not completed\n")); + return; + } + + /* use the same memory for all valid devices */ + memAllocStatus = ostiAllocMemory(tiRoot, &osMemHandle, (void **)&tdIORequest, + &physUpper32, &physLower32, 8, + sizeof(*tdIORequest), agTRUE); + if (memAllocStatus != tiSuccess || tdIORequest == agNULL) + { + TI_DBG1(("tdsaCTLSet: ostiAllocMemory failed\n")); + return;// tiError; + } + osti_memset(tdIORequest, 0, sizeof(*tdIORequest)); + + tdIORequest->osMemHandle = osMemHandle; + tdIORequest->eventType = eventType; + tdIORequest->eventStatus = eventStatus; + + tiIORequest = &tdIORequest->tiIORequest; + tdIORequestBody = &tdIORequest->tdIORequestBody; + /* save context if we need to abort later */ + tiIORequest->tdData = tdIORequestBody; + + tdIORequestBody->IOCompletionFunc = NULL;//itdssIOCompleted; + tdIORequestBody->tiIORequest = tiIORequest; + tdIORequestBody->IOType.InitiatorRegIO.expDataLength = 16; + + tdIORequestBody->agIORequest.osData = (void *)tdIORequest; //tdIORequestBody; + + memAllocStatus = ostiAllocMemory(tiRoot, &tdIORequest->osMemHandle2, + (void **)&tdIORequest->virtAddr, + &tdIORequest->physUpper32, + &tdIORequest->physLower32, + 8, DR_MODE_PG_SZ, agFALSE); + if (memAllocStatus != tiSuccess || tdIORequest == agNULL) + { + TI_DBG1(("tdsaCTLSet: ostiAllocMemory noncached failed\n")); + ostiFreeMemory(tiRoot, tdIORequest->osMemHandle, sizeof(*tdIORequest)); + return;// tiError; + } + + osti_memset(tdIORequest->virtAddr, 0, DR_MODE_PG_SZ); + tdsaCTLNextDevice(tiRoot, onePortContext, tdIORequest, + tdsaAllShared->MainDeviceList.flink); +} /* tdsaCTLSet*/ +#endif + +/***************************************************************************** +*! \brief tdsaSASDiscoverDone +* +* Purpose: This function called to finish up SAS discovery. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaSASDiscoverDone( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + bit32 flag + ) +{ +#ifndef SATA_ENABLE + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *)tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; +#endif + + TI_DBG3(("tdsaSASDiscoverDone: start\n")); + TI_DBG3(("tdsaSASDiscoverDone: pPort=%p DONE\n", onePortContext)); + TI_DBG3(("tdsaSASDiscoverDone: pid %d\n", onePortContext->id)); + + /* Set discovery status */ + onePortContext->discovery.status = DISCOVERY_SAS_DONE; + +#ifdef TD_INTERNAL_DEBUG /* debugging only */ + TI_DBG3(("tdsaSASDiscoverDone: BEFORE\n")); + tdsaDumpAllExp(tiRoot, onePortContext, agNULL); + tdsaDumpAllUpExp(tiRoot, onePortContext, agNULL); +#endif + + /* clean up expanders data strucures; move to free exp when device is cleaned */ + tdsaCleanAllExp(tiRoot, onePortContext); + +#ifdef TD_INTERNAL_DEBUG /* debugging only */ + TI_DBG3(("tdsaSASDiscoverDone: AFTER\n")); + tdsaDumpAllExp(tiRoot, onePortContext, agNULL); + tdsaDumpAllUpExp(tiRoot, onePortContext, agNULL); +#endif + + + /* call back to notify discovery is done */ + /* SATA is NOT enbled */ +#ifndef SATA_ENABLE + if (onePortContext->discovery.SeenBC == agTRUE) + { + TI_DBG3(("tdsaSASDiscoverDone: broadcast change; discover again\n")); + tdssInternalRemovals(onePortContext->agRoot, + onePortContext + ); + + /* processed broadcast change */ + onePortContext->discovery.SeenBC = agFALSE; + if (tdsaAllShared->ResetInDiscovery != 0 && + onePortContext->discovery.ResetTriggerred == agTRUE) + { + TI_DBG2(("tdsaSASDiscoverDone: tdsaBCTimer\n")); + tdsaBCTimer(tiRoot, onePortContext); + } + else + { + tdsaDiscover( + tiRoot, + onePortContext, + TDSA_DISCOVERY_TYPE_SAS, + TDSA_DISCOVERY_OPTION_INCREMENTAL_START + ); + } + } + else + { + onePortContext->DiscoveryState = ITD_DSTATE_COMPLETED; + + if (onePortContext->discovery.type == TDSA_DISCOVERY_OPTION_FULL_START) + { + if (flag == tiSuccess) + { +#ifdef AGTIAPI_CTL + if (tdsaAllShared->SASConnectTimeLimit) + tdsaCTLSet(tiRoot, onePortContext, tiIntrEventTypeDiscovery, + tiDiscOK); + else +#endif + ostiInitiatorEvent( + tiRoot, + onePortContext->tiPortalContext, + agNULL, + tiIntrEventTypeDiscovery, + tiDiscOK, + agNULL + ); + } + else + { + TI_DBG1(("tdsaSASDiscoverDone: discovery failed\n")); + tdssDiscoveryErrorRemovals(onePortContext->agRoot, + onePortContext + ); + + ostiInitiatorEvent( + tiRoot, + onePortContext->tiPortalContext, + agNULL, + tiIntrEventTypeDiscovery, + tiDiscFailed, + agNULL + ); + } + } + else + { + if (flag == tiSuccess) + { + tdssReportChanges(onePortContext->agRoot, + onePortContext + ); + } + else + { + tdssReportRemovals(onePortContext->agRoot, + onePortContext, + agFALSE + ); + } + } + } +#ifdef TBD + /* ACKing BC */ + tdsaAckBC(tiRoot, onePortContext); +#endif + +#endif + +#ifdef SATA_ENABLE + + if (flag == tiSuccess) + { + TI_DBG3(("tdsaSASDiscoverDone: calling SATA discovery\n")); + /* + tdsaSATAFullDiscover() or tdsaincrementalDiscover() + call sata discover + when sata discover is done, call ostiInitiatorEvent + */ + if (onePortContext->discovery.type == TDSA_DISCOVERY_OPTION_FULL_START) + { + TI_DBG3(("tdsaSASDiscoverDone: calling FULL SATA discovery\n")); + tdsaDiscover( + tiRoot, + onePortContext, + AG_SA_DISCOVERY_TYPE_SATA, + TDSA_DISCOVERY_OPTION_FULL_START + ); + } + else + { + TI_DBG3(("tdsaSASDiscoverDone: calling INCREMENTAL SATA discovery\n")); + tdsaDiscover( + tiRoot, + onePortContext, + AG_SA_DISCOVERY_TYPE_SATA, + TDSA_DISCOVERY_OPTION_INCREMENTAL_START + ); + } + } + else + { + /* error case */ + TI_DBG1(("tdsaSASDiscoverDone: Error; clean up\n")); + tdssDiscoveryErrorRemovals(onePortContext->agRoot, + onePortContext + ); + + onePortContext->discovery.SeenBC = agFALSE; + onePortContext->DiscoveryState = ITD_DSTATE_COMPLETED; + ostiInitiatorEvent( + tiRoot, + onePortContext->tiPortalContext, + agNULL, + tiIntrEventTypeDiscovery, + tiDiscFailed, + agNULL + ); + } +#endif + return; +} + +//temp only for testing +osGLOBAL void +tdsaReportManInfoSend( + tiRoot_t *tiRoot, + tdsaDeviceData_t *oneDeviceData + ) +{ + agsaRoot_t *agRoot; + + agRoot = oneDeviceData->agRoot; + + TI_DBG2(("tdsaReportManInfoSend: start\n")); + + tdSMPStart( + tiRoot, + agRoot, + oneDeviceData, + SMP_REPORT_MANUFACTURE_INFORMATION, + agNULL, + 0, + AGSA_SMP_INIT_REQ, + agNULL, + 0 + ); + + return; +} + + +osGLOBAL void +tdsaReportManInfoRespRcvd( + tiRoot_t *tiRoot, + agsaRoot_t *agRoot, + tdsaDeviceData_t *oneDeviceData, + tdssSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ) +{ + tdsaPortContext_t *onePortContext; + tdsaDiscovery_t *discovery; + + TI_DBG2(("tdsaReportManInfoRespRcvd: start\n")); + TI_DBG2(("tdsaReportManInfoRespRcvd: sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG2(("tdsaReportManInfoRespRcvd: sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + + onePortContext = oneDeviceData->tdPortContext; + discovery = &(onePortContext->discovery); + + if (frameHeader->smpFunctionResult == SMP_FUNCTION_ACCEPTED) + { + TI_DBG2(("tdsaReportManInfoRespRcvd: SMP accepted\n")); + } + else + { + TI_DBG1(("tdsaReportManInfoRespRcvd: SMP NOT accepted; fn result 0x%x\n", frameHeader->smpFunctionResult)); + } + + TI_DBG2(("tdsaReportManInfoRespRcvd: discovery retries %d\n", discovery->retries)); + discovery->retries++; + + if (discovery->retries >= DISCOVERY_RETRIES) + { + TI_DBG1(("tdsaReportManInfoRespRcvd: retries are over\n")); + discovery->retries = 0; + /* failed the discovery */ + } + else + { + TI_DBG1(("tdsaReportManInfoRespRcvd: keep retrying\n")); + // start timer + tdsaDiscoveryTimer(tiRoot, onePortContext, oneDeviceData); + } + + return; +} + +//end temp only for testing + +/***************************************************************************** +*! \brief tdsaReportGeneralSend +* +* Purpose: This function sends Report General SMP to a device. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param oneDeviceData: Pointer to the device data. +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaReportGeneralSend( + tiRoot_t *tiRoot, + tdsaDeviceData_t *oneDeviceData + ) +{ + agsaRoot_t *agRoot; + + agRoot = oneDeviceData->agRoot; + + TI_DBG3(("tdsaReportGeneralSend: start\n")); + + tdSMPStart( + tiRoot, + agRoot, + oneDeviceData, + SMP_REPORT_GENERAL, + agNULL, + 0, + AGSA_SMP_INIT_REQ, + agNULL, + 0 + ); + + return; +} + +/***************************************************************************** +*! \brief tdsaReportGeneralRespRcvd +* +* Purpose: This function processes Report General response. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param agRoot: Pointer to chip/driver Instance. +* \param oneDeviceData: Pointer to the device data. +* \param frameHeader: Pointer to SMP frame header. +* \param frameHandle: A Handle used to refer to the response frame +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaReportGeneralRespRcvd( + tiRoot_t *tiRoot, + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + tdsaDeviceData_t *oneDeviceData, + tdssSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ) +{ + smpRespReportGeneral_t tdSMPReportGeneralResp; + smpRespReportGeneral_t *ptdSMPReportGeneralResp; + tdsaExpander_t *oneExpander; + tdsaPortContext_t *onePortContext; + tdsaDiscovery_t *discovery; +#ifdef REMOVED + bit32 i; +#endif +#ifndef DIRECT_SMP + tdssSMPRequestBody_t *tdSMPRequestBody; + tdSMPRequestBody = (tdssSMPRequestBody_t *)agIORequest->osData; +#endif + + TI_DBG3(("tdsaReportGeneralRespRcvd: start\n")); + TI_DBG3(("tdsaReportGeneralRespRcvd: sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG3(("tdsaReportGeneralRespRcvd: sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + ptdSMPReportGeneralResp = &tdSMPReportGeneralResp; + osti_memset(&tdSMPReportGeneralResp, 0, sizeof(smpRespReportGeneral_t)); +#ifdef DIRECT_SMP + saFrameReadBlock(agRoot, frameHandle, 4, ptdSMPReportGeneralResp, sizeof(smpRespReportGeneral_t)); +#else + saFrameReadBlock(agRoot, tdSMPRequestBody->IndirectSMPResp, 4, ptdSMPReportGeneralResp, sizeof(smpRespReportGeneral_t)); +#endif + + //tdhexdump("tdsaReportGeneralRespRcvd", (bit8 *)ptdSMPReportGeneralResp, sizeof(smpRespReportGeneral_t)); +#ifndef DIRECT_SMP + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->IndirectSMPReqosMemHandle, + tdSMPRequestBody->IndirectSMPReqLen + ); + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->IndirectSMPResposMemHandle, + tdSMPRequestBody->IndirectSMPRespLen + ); +#endif + + onePortContext = oneDeviceData->tdPortContext; + discovery = &(onePortContext->discovery); + + if (onePortContext->valid == agFALSE) + { + TI_DBG1(("tdsaReportGeneralRespRcvd: aborting discovery\n")); + tdsaSASDiscoverAbort(tiRoot, onePortContext); + return; + } + if (frameHeader->smpFunctionResult == SMP_FUNCTION_ACCEPTED) + { + oneDeviceData->numOfPhys = (bit8) ptdSMPReportGeneralResp->numOfPhys; + oneExpander = oneDeviceData->tdExpander; + oneExpander->routingIndex = (bit16) REPORT_GENERAL_GET_ROUTEINDEXES(ptdSMPReportGeneralResp); +#ifdef REMOVED + for ( i = 0; i < oneDeviceData->numOfPhys; i++ ) + { + oneExpander->currentIndex[i] = 0; + } +#endif + oneExpander->configReserved = 0; + oneExpander->configRouteTable = REPORT_GENERAL_IS_CONFIGURABLE(ptdSMPReportGeneralResp) ? 1 : 0; + oneExpander->configuring = REPORT_GENERAL_IS_CONFIGURING(ptdSMPReportGeneralResp) ? 1 : 0; + TI_DBG3(("tdsaReportGeneralRespRcvd: oneExpander=%p numberofPhys=0x%x RoutingIndex=0x%x\n", + oneExpander, oneDeviceData->numOfPhys, oneExpander->routingIndex)); + TI_DBG3(("tdsaReportGeneralRespRcvd: configRouteTable=%d configuring=%d\n", + oneExpander->configRouteTable, oneExpander->configuring)); + if (oneExpander->configuring == 1) + { + discovery->retries++; + if (discovery->retries >= DISCOVERY_RETRIES) + { + TI_DBG1(("tdsaReportGeneralRespRcvd: retries are over\n")); + discovery->retries = 0; + /* failed the discovery */ + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + } + else + { + TI_DBG1(("tdsaReportGeneralRespRcvd: keep retrying\n")); + // start timer for sending ReportGeneral + tdsaDiscoveryTimer(tiRoot, onePortContext, oneDeviceData); + } + } + else + { + discovery->retries = 0; + tdsaDiscoverSend(tiRoot, oneDeviceData); + } + } + else + { + TI_DBG1(("tdsaReportGeneralRespRcvd: SMP failed; fn result 0x%x; stopping discovery\n", frameHeader->smpFunctionResult)); + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + } + return; +} + + +/***************************************************************************** +*! \brief tdsaDiscoverSend +* +* Purpose: This function sends Discovery SMP to a device. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param oneDeviceData: Pointer to the device data. +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaDiscoverSend( + tiRoot_t *tiRoot, + tdsaDeviceData_t *oneDeviceData + ) +{ + agsaRoot_t *agRoot; + tdsaExpander_t *oneExpander; + smpReqDiscover_t smpDiscoverReq; + + TI_DBG3(("tdsaDiscoverSend: start\n")); + TI_DBG3(("tdsaDiscoverSend: device %p did %d\n", oneDeviceData, oneDeviceData->id)); + agRoot = oneDeviceData->agRoot; + oneExpander = oneDeviceData->tdExpander; + TI_DBG3(("tdsaDiscoverSend: phyID 0x%x\n", oneExpander->discoveringPhyId)); + + + osti_memset(&smpDiscoverReq, 0, sizeof(smpReqDiscover_t)); + + smpDiscoverReq.reserved1 = 0; + smpDiscoverReq.reserved2 = 0; + smpDiscoverReq.phyIdentifier = oneExpander->discoveringPhyId; + smpDiscoverReq.reserved3 = 0; + + + tdSMPStart( + tiRoot, + agRoot, + oneDeviceData, + SMP_DISCOVER, + (bit8 *)&smpDiscoverReq, + sizeof(smpReqDiscover_t), + AGSA_SMP_INIT_REQ, + agNULL, + 0 + ); + return; +} + + +/***************************************************************************** +*! \brief tdsaDiscoverRespRcvd +* +* Purpose: This function processes Discovery response. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param agRoot: Pointer to chip/driver Instance. +* \param oneDeviceData: Pointer to the device data. +* \param frameHeader: Pointer to SMP frame header. +* \param frameHandle: A Handle used to refer to the response frame +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaDiscoverRespRcvd( + tiRoot_t *tiRoot, + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + tdsaDeviceData_t *oneDeviceData, + tdssSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ) +{ + smpRespDiscover_t *ptdSMPDiscoverResp; + tdsaPortContext_t *onePortContext; + tdsaExpander_t *oneExpander; + tdsaDiscovery_t *discovery; +#ifndef DIRECT_SMP + tdssSMPRequestBody_t *tdSMPRequestBody; +#endif + + TI_DBG3(("tdsaDiscoverRespRcvd: start\n")); + TI_DBG3(("tdsaDiscoverRespRcvd: sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG3(("tdsaDiscoverRespRcvd: sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + + + onePortContext = oneDeviceData->tdPortContext; + oneExpander = oneDeviceData->tdExpander; + discovery = &(onePortContext->discovery); +#ifndef DIRECT_SMP + tdSMPRequestBody = (tdssSMPRequestBody_t *)agIORequest->osData; +#endif + + if (onePortContext->valid == agFALSE) + { + TI_DBG1(("tdsaDiscoverRespRcvd: aborting discovery\n")); + tdsaSASDiscoverAbort(tiRoot, onePortContext); + return; + } + ptdSMPDiscoverResp = &(discovery->SMPDiscoverResp); +#ifdef DIRECT_SMP + saFrameReadBlock(agRoot, frameHandle, 4, ptdSMPDiscoverResp, sizeof(smpRespDiscover_t)); +#else + saFrameReadBlock(agRoot, tdSMPRequestBody->IndirectSMPResp, 4, ptdSMPDiscoverResp, sizeof(smpRespDiscover_t)); +#endif + //tdhexdump("tdsaDiscoverRespRcvd", (bit8 *)ptdSMPDiscoverResp, sizeof(smpRespDiscover_t)); + +#ifndef DIRECT_SMP + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->IndirectSMPReqosMemHandle, + tdSMPRequestBody->IndirectSMPReqLen + ); + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->IndirectSMPResposMemHandle, + tdSMPRequestBody->IndirectSMPRespLen + ); +#endif + + if ( frameHeader->smpFunctionResult == SMP_FUNCTION_ACCEPTED) + { + if ( onePortContext->discovery.status == DISCOVERY_UP_STREAM) + { + tdsaSASUpStreamDiscoverExpanderPhy(tiRoot, onePortContext, oneExpander, ptdSMPDiscoverResp); + } + else if ( onePortContext->discovery.status == DISCOVERY_DOWN_STREAM) + { + tdsaSASDownStreamDiscoverExpanderPhy(tiRoot, onePortContext, oneExpander, ptdSMPDiscoverResp); + } + else if (onePortContext->discovery.status == DISCOVERY_CONFIG_ROUTING) + { + /* not done with configuring routing + 1. set the timer + 2. on timer expiration, call tdsaSASDownStreamDiscoverExpanderPhy() + */ + TI_DBG2(("tdsaDiscoverRespRcvd: still configuring routing; setting timer\n")); + TI_DBG2(("tdsaDiscoverRespRcvd: onePortContext %p oneDeviceData %p ptdSMPDiscoverResp %p\n", onePortContext, oneDeviceData, ptdSMPDiscoverResp)); + tdhexdump("tdsaDiscoverRespRcvd", (bit8*)ptdSMPDiscoverResp, sizeof(smpRespDiscover_t)); + + tdsaConfigureRouteTimer(tiRoot, onePortContext, oneExpander, ptdSMPDiscoverResp); + } + else + { + /* nothing */ + } + } + else if (frameHeader->smpFunctionResult == PHY_VACANT) + { + TI_DBG3(("tdsaDiscoverRespRcvd: smpFunctionResult is PHY_VACANT, phyid %d\n", + oneExpander->discoveringPhyId)); + if ( onePortContext->discovery.status == DISCOVERY_UP_STREAM) + { + tdsaSASUpStreamDiscoverExpanderPhySkip(tiRoot, onePortContext, oneExpander); + } + else if ( onePortContext->discovery.status == DISCOVERY_DOWN_STREAM) + { + tdsaSASDownStreamDiscoverExpanderPhySkip(tiRoot, onePortContext, oneExpander); + } + else if (onePortContext->discovery.status == DISCOVERY_CONFIG_ROUTING) + { + /* not done with configuring routing + 1. set the timer + 2. on timer expiration, call tdsaSASDownStreamDiscoverExpanderPhy() + */ + TI_DBG1(("tdsaDiscoverRespRcvd: still configuring routing; setting timer\n")); + TI_DBG1(("tdsaDiscoverRespRcvd: onePortContext %p oneDeviceData %p ptdSMPDiscoverResp %p\n", onePortContext, oneDeviceData, ptdSMPDiscoverResp)); + tdhexdump("tdsaDiscoverRespRcvd", (bit8*)ptdSMPDiscoverResp, sizeof(smpRespDiscover_t)); + + tdsaConfigureRouteTimer(tiRoot, onePortContext, oneExpander, ptdSMPDiscoverResp); + } + } + else + { + TI_DBG1(("tdsaDiscoverRespRcvd: Discovery Error SMP function return result error=%x\n", + frameHeader->smpFunctionResult)); + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + } + return; +} + +/***************************************************************************** +*! \brief tdsaSASUpStreamDiscoverExpanderPhy +* +* Purpose: This function actully does upstream traverse and finds out detailed +* information about topology. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* \param oneExpander: Pointer to the expander data. +* \param pDiscoverResp: Pointer to the Discovery SMP respsonse. +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaSASUpStreamDiscoverExpanderPhy( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaExpander_t *oneExpander, + smpRespDiscover_t *pDiscoverResp + ) +{ + tdsaDeviceData_t *oneDeviceData; + tdsaDeviceData_t *AttachedDevice = agNULL; + tdsaExpander_t *AttachedExpander; + agsaSASIdentify_t sasIdentify; + bit8 connectionRate; + bit32 attachedSasHi, attachedSasLo; + tdsaSASSubID_t agSASSubID; + + TI_DBG3(("tdsaSASUpStreamDiscoverExpanderPhy: start\n")); + if (onePortContext->valid == agFALSE) + { + TI_DBG1(("tdsaSASUpStreamDiscoverExpanderPhy: aborting discovery\n")); + tdsaSASDiscoverAbort(tiRoot, onePortContext); + return; + } + + oneDeviceData = oneExpander->tdDevice; + TI_DBG3(("tdsaSASUpStreamDiscoverExpanderPhy: Phy #%d of SAS %08x-%08x\n", + oneExpander->discoveringPhyId, + oneDeviceData->SASAddressID.sasAddressHi, + oneDeviceData->SASAddressID.sasAddressLo)); + TI_DBG3((" Attached device: %s\n", + ( DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == 0 ? "No Device" : + (DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == 1 ? "End Device" : + (DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == 2 ? "Edge Expander" : "Fanout Expander"))))); + + if ( DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) != SAS_NO_DEVICE) + { + TI_DBG3((" SAS address : %08x-%08x\n", + DISCRSP_GET_ATTACHED_SAS_ADDRESSHI(pDiscoverResp), + DISCRSP_GET_ATTACHED_SAS_ADDRESSLO(pDiscoverResp))); + TI_DBG3((" SSP Target : %d\n", DISCRSP_IS_SSP_TARGET(pDiscoverResp)?1:0)); + TI_DBG3((" STP Target : %d\n", DISCRSP_IS_STP_TARGET(pDiscoverResp)?1:0)); + TI_DBG3((" SMP Target : %d\n", DISCRSP_IS_SMP_TARGET(pDiscoverResp)?1:0)); + TI_DBG3((" SATA DEVICE : %d\n", DISCRSP_IS_SATA_DEVICE(pDiscoverResp)?1:0)); + TI_DBG3((" SSP Initiator : %d\n", DISCRSP_IS_SSP_INITIATOR(pDiscoverResp)?1:0)); + TI_DBG3((" STP Initiator : %d\n", DISCRSP_IS_STP_INITIATOR(pDiscoverResp)?1:0)); + TI_DBG3((" SMP Initiator : %d\n", DISCRSP_IS_SMP_INITIATOR(pDiscoverResp)?1:0)); + TI_DBG3((" Phy ID : %d\n", pDiscoverResp->phyIdentifier)); + TI_DBG3((" Attached Phy ID: %d\n", pDiscoverResp->attachedPhyIdentifier)); + } + /* end for debugging */ + + /* for debugging */ + if (oneExpander->discoveringPhyId != pDiscoverResp->phyIdentifier) + { + TI_DBG1(("tdsaSASUpStreamDiscoverExpanderPhy: !!! Incorrect SMP response !!!\n")); + TI_DBG1(("tdsaSASUpStreamDiscoverExpanderPhy: Request PhyID #%d Response PhyID #%d\n", oneExpander->discoveringPhyId, pDiscoverResp->phyIdentifier)); + tdhexdump("NO_DEVICE", (bit8*)pDiscoverResp, sizeof(smpRespDiscover_t)); + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + return; + } + + /* saving routing attribute for non self-configuring expanders */ + oneExpander->routingAttribute[pDiscoverResp->phyIdentifier] = DISCRSP_GET_ROUTINGATTRIB(pDiscoverResp); + + /* for debugging */ +// dumpRoutingAttributes(tiRoot, oneExpander, pDiscoverResp->phyIdentifier); + + if ( oneDeviceData->SASSpecDeviceType == SAS_FANOUT_EXPANDER_DEVICE ) + { + TI_DBG3(("tdsaSASUpStreamDiscoverExpanderPhy: SA_SAS_DEV_TYPE_FANOUT_EXPANDER\n")); + if ( DISCRSP_GET_ROUTINGATTRIB(pDiscoverResp) == SAS_ROUTING_SUBTRACTIVE) + { + TI_DBG1(("tdsaSASUpStreamDiscoverExpanderPhy: **** Topology Error subtractive routing on fanout expander device\n")); + + /* discovery error */ + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier = oneExpander->discoveringPhyId; + + /* (2.1.3) discovery done */ + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + return; + } + } + else + { + TI_DBG3(("tdsaSASUpStreamDiscoverExpanderPhy: SA_SAS_DEV_TYPE_EDGE_EXPANDER\n")); + + if ( DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) != SAS_NO_DEVICE) + { + /* Setup sasIdentify for the attached device */ + sasIdentify.phyIdentifier = pDiscoverResp->phyIdentifier; + sasIdentify.deviceType_addressFrameType = (bit8)(pDiscoverResp->attachedDeviceType & 0x70); + sasIdentify.initiator_ssp_stp_smp = pDiscoverResp->attached_Ssp_Stp_Smp_Sata_Initiator; + sasIdentify.target_ssp_stp_smp = pDiscoverResp->attached_SataPS_Ssp_Stp_Smp_Sata_Target; + *(bit32*)sasIdentify.sasAddressHi = *(bit32*)pDiscoverResp->attachedSasAddressHi; + *(bit32*)sasIdentify.sasAddressLo = *(bit32*)pDiscoverResp->attachedSasAddressLo; + + /* incremental discovery */ + agSASSubID.sasAddressHi = SA_IDFRM_GET_SAS_ADDRESSHI(&sasIdentify); + agSASSubID.sasAddressLo = SA_IDFRM_GET_SAS_ADDRESSLO(&sasIdentify); + agSASSubID.initiator_ssp_stp_smp = sasIdentify.initiator_ssp_stp_smp; + agSASSubID.target_ssp_stp_smp = sasIdentify.target_ssp_stp_smp; + + attachedSasHi = DISCRSP_GET_ATTACHED_SAS_ADDRESSHI(pDiscoverResp); + attachedSasLo = DISCRSP_GET_ATTACHED_SAS_ADDRESSLO(pDiscoverResp); + + /* If the phy has subtractive routing attribute */ + if ( DISCRSP_GET_ROUTINGATTRIB(pDiscoverResp) == SAS_ROUTING_SUBTRACTIVE) + { + TI_DBG3(("tdsaSASUpStreamDiscoverExpanderPhy: SA_SAS_ROUTING_SUBTRACTIVE\n")); + /* Setup upstream phys */ + tdsaSASExpanderUpStreamPhyAdd(tiRoot, oneExpander, (bit8) pDiscoverResp->attachedPhyIdentifier); + /* If the expander already has an upsteam device set up */ + if (oneExpander->hasUpStreamDevice == agTRUE) + { + /* If the sas address doesn't match */ + if ( ((oneExpander->upStreamSASAddressHi != attachedSasHi) || + (oneExpander->upStreamSASAddressLo != attachedSasLo)) && + (DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_EDGE_EXPANDER_DEVICE || + DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_FANOUT_EXPANDER_DEVICE) + ) + { + /* TODO: discovery error, callback */ + TI_DBG1(("tdsaSASUpStreamDiscoverExpanderPhy: **** Topology Error subtractive routing error - inconsistent SAS address\n")); + /* call back to notify discovery error */ + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier = oneExpander->discoveringPhyId; + /* discovery done */ + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + } + } + else + { + /* Setup SAS address for up stream device */ + oneExpander->hasUpStreamDevice = agTRUE; + oneExpander->upStreamSASAddressHi = attachedSasHi; + oneExpander->upStreamSASAddressLo = attachedSasLo; + + if ( (onePortContext->sasLocalAddressHi != attachedSasHi) + || (onePortContext->sasLocalAddressLo != attachedSasLo) ) + { + /* Find the device from the discovered list */ + AttachedDevice = tdsaPortSASDeviceFind(tiRoot, onePortContext, attachedSasLo, attachedSasHi); + /* If the device has been discovered before */ + if ( AttachedDevice != agNULL) + { + TI_DBG3(("tdsaSASUpStreamDiscoverExpanderPhy: Seen This Device Before\n")); + /* If attached device is an edge expander */ + if ( AttachedDevice->SASSpecDeviceType == SAS_EDGE_EXPANDER_DEVICE) + { + /* The attached device is an expander */ + AttachedExpander = AttachedDevice->tdExpander; + /* If the two expanders are the root of the two edge expander sets */ + if ( (AttachedExpander->upStreamSASAddressHi == + DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo)) + && (AttachedExpander->upStreamSASAddressLo == + DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo)) ) + { + /* Setup upstream expander for the pExpander */ + oneExpander->tdUpStreamExpander = AttachedExpander; + } + /* If the two expanders are not the root of the two edge expander sets */ + else + { + /* TODO: loop found, discovery error, callback */ + TI_DBG1(("tdsaSASUpStreamDiscoverExpanderPhy: **** Topology Error loop detection\n")); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier = oneExpander->discoveringPhyId; + /* discovery done */ + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + } + } + /* If attached device is not an edge expander */ + else + { + /*TODO: should not happen, ASSERT */ + TI_DBG3(("tdsaSASUpStreamDiscoverExpanderPhy, *** Attached Device is not Edge. Confused!!\n")); + } + } + /* If the device has not been discovered before */ + else + { + /* Add the device */ + TI_DBG3(("tdsaSASUpStreamDiscoverExpanderPhy: New device\n")); + /* read minimum rate from the configuration + onePortContext->LinkRate is SPC's local link rate + */ + connectionRate = (bit8)(MIN(onePortContext->LinkRate, DISCRSP_GET_LINKRATE(pDiscoverResp))); + TI_DBG3(("siSASUpStreamDiscoverExpanderPhy: link rate 0x%x\n", onePortContext->LinkRate)); + TI_DBG3(("siSASUpStreamDiscoverExpanderPhy: negotiatedPhyLinkRate 0x%x\n", DISCRSP_GET_LINKRATE(pDiscoverResp))); + TI_DBG3(("siSASUpStreamDiscoverExpanderPhy: connectionRate 0x%x\n", connectionRate)); + //hhhhhhhh + if (DISCRSP_IS_STP_TARGET(pDiscoverResp) || DISCRSP_IS_SATA_DEVICE(pDiscoverResp)) + { + /* incremental discovery */ + if (onePortContext->discovery.type == TDSA_DISCOVERY_OPTION_FULL_START) + { + AttachedDevice = tdsaPortSASDeviceAdd( + tiRoot, + onePortContext, + sasIdentify, + agFALSE, + connectionRate, + IT_NEXUS_TIMEOUT, + 0, + STP_DEVICE_TYPE, + oneDeviceData, + pDiscoverResp->phyIdentifier + ); + } + else + { + /* incremental discovery */ + AttachedDevice = tdsaFindRegNValid( + onePortContext->agRoot, + onePortContext, + &agSASSubID + ); + /* not registered and not valid; add this*/ + if (AttachedDevice == agNULL) + { + AttachedDevice = tdsaPortSASDeviceAdd( + tiRoot, + onePortContext, + sasIdentify, + agFALSE, + connectionRate, + IT_NEXUS_TIMEOUT, + 0, + STP_DEVICE_TYPE, + oneDeviceData, + pDiscoverResp->phyIdentifier + ); + } + } + } + else + { + /* incremental discovery */ + if (onePortContext->discovery.type == TDSA_DISCOVERY_OPTION_FULL_START) + { + AttachedDevice = tdsaPortSASDeviceAdd( + tiRoot, + onePortContext, + sasIdentify, + agFALSE, + connectionRate, + IT_NEXUS_TIMEOUT, + 0, + SAS_DEVICE_TYPE, + oneDeviceData, + pDiscoverResp->phyIdentifier + ); + } + else + { + /* incremental discovery */ + AttachedDevice = tdsaFindRegNValid( + onePortContext->agRoot, + onePortContext, + &agSASSubID + ); + /* not registered and not valid; add this*/ + if (AttachedDevice == agNULL) + { + AttachedDevice = tdsaPortSASDeviceAdd( + tiRoot, + onePortContext, + sasIdentify, + agFALSE, + connectionRate, + IT_NEXUS_TIMEOUT, + 0, + SAS_DEVICE_TYPE, + oneDeviceData, + pDiscoverResp->phyIdentifier + ); + } + } + } + /* If the device is added successfully */ + if ( AttachedDevice != agNULL) + { + + /* (3.1.2.3.2.3.2.1) callback about new device */ + if ( DISCRSP_IS_SSP_TARGET(pDiscoverResp) + || DISCRSP_IS_SSP_INITIATOR(pDiscoverResp) + || DISCRSP_IS_SMP_INITIATOR(pDiscoverResp) + || DISCRSP_IS_SMP_INITIATOR(pDiscoverResp) ) + { + TI_DBG3(("tdsaSASUpStreamDiscoverExpanderPhy: Found SSP/SMP SAS %08x-%08x\n", + attachedSasHi, attachedSasLo)); + } + else + { + TI_DBG3(("tdsaSASUpStreamDiscoverExpanderPhy: Found a SAS STP device.\n")); + } + /* If the attached device is an expander */ + if ( (DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_EDGE_EXPANDER_DEVICE) + || (DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_FANOUT_EXPANDER_DEVICE) ) + { + /* Allocate an expander data structure */ + AttachedExpander = tdssSASDiscoveringExpanderAlloc( + tiRoot, + onePortContext, + AttachedDevice + ); + + TI_DBG3(("tdsaSASUpStreamDiscoverExpanderPhy: Found expander=%p\n", AttachedExpander)); + /* If allocate successfully */ + if ( AttachedExpander != agNULL) + { + /* Add the pAttachedExpander to discovering list */ + tdssSASDiscoveringExpanderAdd(tiRoot, onePortContext, AttachedExpander); + /* Setup upstream expander for the pExpander */ + oneExpander->tdUpStreamExpander = AttachedExpander; + } + /* If failed to allocate */ + else + { + TI_DBG1(("tdsaSASUpStreamDiscoverExpanderPhy, Failed to allocate expander data structure\n")); + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + } + } + /* If the attached device is an end device */ + else + { + TI_DBG3(("tdsaSASUpStreamDiscoverExpanderPhy: Found end device\n")); + /* LP2006-05-26 added upstream device to the newly found device */ + AttachedDevice->tdExpander = oneExpander; + oneExpander->tdUpStreamExpander = agNULL; + } + } + else + { + TI_DBG1(("tdsaSASUpStreamDiscoverExpanderPhy, Failed to add a device\n")); + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + } + } + } + } + } /* substractive routing */ + } + } + + + oneExpander->discoveringPhyId ++; + if (onePortContext->discovery.status == DISCOVERY_UP_STREAM) + { + if ( oneExpander->discoveringPhyId < oneDeviceData->numOfPhys ) + { + TI_DBG3(("tdsaSASUpStreamDiscoverExpanderPhy: DISCOVERY_UP_STREAM find more ...\n")); + /* continue discovery for the next phy */ + tdsaDiscoverSend(tiRoot, oneDeviceData); + } + else + { + TI_DBG3(("tdsaSASUpStreamDiscoverExpanderPhy: DISCOVERY_UP_STREAM last phy continue upstream..\n")); + + /* remove the expander from the discovering list */ + tdssSASDiscoveringExpanderRemove(tiRoot, onePortContext, oneExpander); + /* continue upstream discovering */ + tdsaSASUpStreamDiscovering(tiRoot, onePortContext, oneDeviceData); + } + } + else + { + TI_DBG3(("tdsaSASUpStreamDiscoverExpanderPhy: onePortContext->discovery.status not in DISCOVERY_UP_STREAM; status %d\n", onePortContext->discovery.status)); + + } + + TI_DBG3(("tdsaSASUpStreamDiscoverExpanderPhy: end return phyID#%d\n", oneExpander->discoveringPhyId - 1)); + + return; +} + +// for debugging only +osGLOBAL tdsaExpander_t * +tdsaFindUpStreamConfigurableExp(tiRoot_t *tiRoot, + tdsaExpander_t *oneExpander) +{ + tdsaExpander_t *ret=agNULL; + tdsaExpander_t *UpsreamExpander = oneExpander->tdUpStreamExpander; + + TI_DBG3(("tdsaFindUpStreamConfigurableExp: start\n")); + TI_DBG3(("tdsaFindUpStreamConfigurableExp: exp addrHi 0x%08x\n", oneExpander->tdDevice->SASAddressID.sasAddressHi)); + TI_DBG3(("tdsaFindUpStreamConfigurableExp: exp addrLo 0x%08x\n", oneExpander->tdDevice->SASAddressID.sasAddressLo)); + + + if (UpsreamExpander) + { + TI_DBG3(("tdsaFindUpStreamConfigurableExp: NO upsream expander\n")); + } + else + { + while (UpsreamExpander) + { + TI_DBG3(("tdsaFindUpStreamConfigurableExp: exp addrHi 0x%08x\n", UpsreamExpander->tdDevice->SASAddressID.sasAddressHi)); + TI_DBG3(("tdsaFindUpStreamConfigurableExp: exp addrLo 0x%08x\n", UpsreamExpander->tdDevice->SASAddressID.sasAddressLo)); + + UpsreamExpander = UpsreamExpander->tdUpStreamExpander; + } + } + return ret; +} + +/***************************************************************************** +*! \brief tdsaSASUpStreamDiscoverExpanderPhySkip +* +* Purpose: This function skips a phy which returned PHY_VACANT in SMP +* response in upstream +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* \param oneExpander: Pointer to the expander data. +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaSASUpStreamDiscoverExpanderPhySkip( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaExpander_t *oneExpander + ) +{ + tdsaDeviceData_t *oneDeviceData; + TI_DBG3(("tdsaSASUpStreamDiscoverExpanderPhySkip: start\n")); + oneDeviceData = oneExpander->tdDevice; + + TI_DBG3(("tdsaSASUpStreamDiscoverExpanderPhySkip: sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG3(("tdsaSASUpStreamDiscoverExpanderPhySkip: sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + + oneExpander->discoveringPhyId ++; + if (onePortContext->discovery.status == DISCOVERY_UP_STREAM) + { + if ( oneExpander->discoveringPhyId < oneDeviceData->numOfPhys ) + { + TI_DBG3(("tdsaSASUpStreamDiscoverExpanderPhySkip: More Phys to discover\n")); + /* continue discovery for the next phy */ + tdsaDiscoverSend(tiRoot, oneDeviceData); + } + else + { + TI_DBG3(("tdsaSASUpStreamDiscoverExpanderPhySkip: No More Phys\n")); + + /* remove the expander from the discovering list */ + tdssSASDiscoveringExpanderRemove(tiRoot, onePortContext, oneExpander); + /* continue upstream discovering */ + tdsaSASUpStreamDiscovering(tiRoot, onePortContext, oneDeviceData); + } + } + else + { + TI_DBG3(("tdsaSASUpStreamDiscoverExpanderPhySkip: onePortContext->discovery.status not in DISCOVERY_UP_STREAM; status %d\n", onePortContext->discovery.status)); + + } + + TI_DBG3(("tdsaSASUpStreamDiscoverExpanderPhySkip: end return phyID#%d\n", oneExpander->discoveringPhyId - 1)); + + + return; +} + + +// for debugging only +osGLOBAL tdsaExpander_t * +tdsaFindDownStreamConfigurableExp(tiRoot_t *tiRoot, + tdsaExpander_t *oneExpander) +{ + tdsaExpander_t *ret=agNULL; + tdsaExpander_t *DownsreamExpander = oneExpander->tdCurrentDownStreamExpander; + + TI_DBG3(("tdsaFindDownStreamConfigurableExp: start\n")); + TI_DBG3(("tdsaFindDownStreamConfigurableExp: exp addrHi 0x%08x\n", oneExpander->tdDevice->SASAddressID.sasAddressHi)); + TI_DBG3(("tdsaFindDownStreamConfigurableExp: exp addrLo 0x%08x\n", oneExpander->tdDevice->SASAddressID.sasAddressLo)); + + + if (DownsreamExpander) + { + TI_DBG3(("tdsaFindDownStreamConfigurableExp: NO downsream expander\n")); + } + else + { + while (DownsreamExpander) + { + TI_DBG3(("tdsaFindDownStreamConfigurableExp: exp addrHi 0x%08x\n", DownsreamExpander->tdDevice->SASAddressID.sasAddressHi)); + TI_DBG3(("tdsaFindDownStreamConfigurableExp: exp addrLo 0x%08x\n", DownsreamExpander->tdDevice->SASAddressID.sasAddressLo)); + + DownsreamExpander = DownsreamExpander->tdCurrentDownStreamExpander; + } + } + return ret; +} + +// for debugging only +osGLOBAL void +dumpRoutingAttributes( + tiRoot_t *tiRoot, + tdsaExpander_t *oneExpander, + bit8 phyID + ) +{ + bit32 i; + + TI_DBG3(("dumpRoutingAttributes: start\n")); + TI_DBG3(("dumpRoutingAttributes: phyID %d\n", phyID)); + TI_DBG3(("dumpRoutingAttributes: exp addrHi 0x%08x\n", oneExpander->tdDevice->SASAddressID.sasAddressHi)); + TI_DBG3(("dumpRoutingAttributes: exp addrLo 0x%08x\n", oneExpander->tdDevice->SASAddressID.sasAddressLo)); + + for(i=0;i <= ((bit32)phyID + 1); i++) + { + TI_DBG3(("dumpRoutingAttributes: index %d routing attribute %d\n", i, oneExpander->routingAttribute[i])); + } + return; +} + +/***************************************************************************** +*! \brief tdsaDumpAllExp +* +* Purpose: This function prints out all expanders seen by discovery. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* \param oneExpander: Pointer to the expander data. +* +* \return: +* None +* +* \note: For debugging only +* +*****************************************************************************/ +osGLOBAL void +tdsaDumpAllExp( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaExpander_t *oneExpander + ) +{ +#if 0 /* for debugging only */ + tdList_t *ExpanderList; + tdsaExpander_t *tempExpander; + tdsaExpander_t *UpsreamExpander; + tdsaExpander_t *DownsreamExpander; + tdsaPortContext_t *tmpOnePortContext = onePortContext; + + TI_DBG3(("tdssSASDiscoveringExpander tdsaDumpAllExp: start\n")); + TI_DBG3(("tdssSASDiscoveringExpander tdsaDumpAllExp: onePortcontext %p oneExpander %p\n", onePortContext, oneExpander)); + + /* debugging */ + tdsaSingleThreadedEnter(tiRoot, TD_DISC_LOCK); + if (TDLIST_EMPTY(&(tmpOnePortContext->discovery.discoveringExpanderList))) + { + tdsaSingleThreadedLeave(tiRoot, TD_DISC_LOCK); + TI_DBG3(("tdssSASDiscoveringExpander tdsaDumpAllExp: empty discoveringExpanderList\n")); + return; + } + else + { + tdsaSingleThreadedLeave(tiRoot, TD_DISC_LOCK); + } + ExpanderList = tmpOnePortContext->discovery.discoveringExpanderList.flink; + while (ExpanderList != &(tmpOnePortContext->discovery.discoveringExpanderList)) + { + tempExpander = TDLIST_OBJECT_BASE(tdsaExpander_t, linkNode, ExpanderList); + UpsreamExpander = tempExpander->tdUpStreamExpander; + DownsreamExpander = tempExpander->tdCurrentDownStreamExpander; + TI_DBG3(("tdssSASDiscoveringExpander tdsaDumpAllExp: expander id %d\n", tempExpander->id)); + TI_DBG3(("tdssSASDiscoveringExpander tdsaDumpAllExp: exp addrHi 0x%08x\n", tempExpander->tdDevice->SASAddressID.sasAddressHi)); + TI_DBG3(("tdssSASDiscoveringExpander tdsaDumpAllExp: exp addrLo 0x%08x\n", tempExpander->tdDevice->SASAddressID.sasAddressLo)); + if (UpsreamExpander) + { + TI_DBG3(("tdssSASDiscoveringExpander tdsaDumpAllExp: Up exp addrHi 0x%08x\n", UpsreamExpander->tdDevice->SASAddressID.sasAddressHi)); + TI_DBG3(("tdssSASDiscoveringExpander tdsaDumpAllExp: Up exp addrLo 0x%08x\n", UpsreamExpander->tdDevice->SASAddressID.sasAddressLo)); + } + else + { + TI_DBG3(("tdssSASDiscoveringExpander tdsaDumpAllExp: No Upstream expander\n")); + } + if (DownsreamExpander) + { + TI_DBG3(("tdssSASDiscoveringExpander tdsaDumpAllExp: Down exp addrHi 0x%08x\n", DownsreamExpander->tdDevice->SASAddressID.sasAddressHi)); + TI_DBG3(("tdssSASDiscoveringExpander tdsaDumpAllExp: Down exp addrLo 0x%08x\n", DownsreamExpander->tdDevice->SASAddressID.sasAddressLo)); + } + else + { + TI_DBG3(("tdssSASDiscoveringExpander tdsaDumpAllExp: No Downstream expander\n")); + } + + ExpanderList = ExpanderList->flink; + } +#endif + return; + +} + +/***************************************************************************** +*! \brief tdsaDumpAllUpExp +* +* Purpose: This function prints out all upstream expanders seen by discovery. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* \param oneExpander: Pointer to the expander data. +* +* \return: +* None +* +* \note: For debugging only +* +*****************************************************************************/ +osGLOBAL void +tdsaDumpAllUpExp( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaExpander_t *oneExpander + ) +{ + return; + +} + +/***************************************************************************** +*! \brief tdsaDumpAllFreeExp +* +* Purpose: This function prints out all free expanders. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \return: +* None +* +* \note: For debugging only +* +*****************************************************************************/ +osGLOBAL void +tdsaDumpAllFreeExp( + tiRoot_t *tiRoot + ) +{ + + return; +} + +/***************************************************************************** +*! \brief tdsaDuplicateConfigSASAddr +* +* Purpose: This function finds whether SAS address has added to the routing +* table of expander or not. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param oneExpander: Pointer to the expander data. +* \param configSASAddressHi: Upper 4 byte of SAS address. +* \param configSASAddressLo: Lower 4 byte of SAS address. +* +* \return: +* agTRUE No need to add configSASAddress. +* agFALSE Need to add configSASAddress. +* +* \note: +* +*****************************************************************************/ +osGLOBAL bit32 +tdsaDuplicateConfigSASAddr( + tiRoot_t *tiRoot, + tdsaExpander_t *oneExpander, + bit32 configSASAddressHi, + bit32 configSASAddressLo + ) +{ + bit32 i; + bit32 ret = agFALSE; + TI_DBG3(("tdsaDuplicateConfigSASAddr: start\n")); + + if (oneExpander == agNULL) + { + TI_DBG3(("tdsaDuplicateConfigSASAddr: NULL expander\n")); + return agTRUE; + } + + if (oneExpander->tdDevice->SASAddressID.sasAddressHi == configSASAddressHi && + oneExpander->tdDevice->SASAddressID.sasAddressLo == configSASAddressLo + ) + { + TI_DBG3(("tdsaDuplicateConfigSASAddr: unnecessary\n")); + return agTRUE; + } + + TI_DBG3(("tdsaDuplicateConfigSASAddr: exp addrHi 0x%08x\n", oneExpander->tdDevice->SASAddressID.sasAddressHi)); + TI_DBG3(("tdsaDuplicateConfigSASAddr: exp addrLo 0x%08x\n", oneExpander->tdDevice->SASAddressID.sasAddressLo)); + TI_DBG3(("tdsaDuplicateConfigSASAddr: configsasAddressHi 0x%08x\n", configSASAddressHi)); + TI_DBG3(("tdsaDuplicateConfigSASAddr: configsasAddressLo 0x%08x\n", configSASAddressLo)); + TI_DBG3(("tdsaDuplicateConfigSASAddr: configSASAddrTableIndex %d\n", oneExpander->configSASAddrTableIndex)); + for(i=0;iconfigSASAddrTableIndex;i++) + { + if (oneExpander->configSASAddressHiTable[i] == configSASAddressHi && + oneExpander->configSASAddressLoTable[i] == configSASAddressLo + ) + { + TI_DBG3(("tdsaDuplicateConfigSASAddr: FOUND!!!\n")); + ret = agTRUE; + break; + } + } + /* new one; let's add it */ + if (ret == agFALSE) + { + TI_DBG3(("tdsaDuplicateConfigSASAddr: adding configSAS Addr!!!\n")); + TI_DBG3(("tdsaDuplicateConfigSASAddr: configSASAddrTableIndex %d\n", oneExpander->configSASAddrTableIndex)); + oneExpander->configSASAddressHiTable[oneExpander->configSASAddrTableIndex] = configSASAddressHi; + oneExpander->configSASAddressLoTable[oneExpander->configSASAddrTableIndex] = configSASAddressLo; + oneExpander->configSASAddrTableIndex++; + } + + return ret; +} +/***************************************************************************** +*! \brief tdsaFindConfigurableExp +* +* Purpose: This function finds whether there is a configurable expander in +* the upstream expander list. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* \param oneExpander: Pointer to the expander data. +* +* \return: +* agTRUE There is configurable expander. +* agFALSE There is not configurable expander. +* +* \note: +* +*****************************************************************************/ +osGLOBAL tdsaExpander_t * +tdsaFindConfigurableExp( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaExpander_t *oneExpander + ) +{ + tdsaExpander_t *tempExpander; + tdsaPortContext_t *tmpOnePortContext = onePortContext; + tdsaExpander_t *ret = agNULL; + + TI_DBG3(("tdsaFindConfigurableExp: start\n")); + + if (oneExpander == agNULL) + { + TI_DBG3(("tdsaFindConfigurableExp: NULL expander\n")); + return agNULL; + } + + TI_DBG3(("tdsaFindConfigurableExp: exp addrHi 0x%08x\n", oneExpander->tdDevice->SASAddressID.sasAddressHi)); + TI_DBG3(("tdsaFindConfigurableExp: exp addrLo 0x%08x\n", oneExpander->tdDevice->SASAddressID.sasAddressLo)); + + tdsaSingleThreadedEnter(tiRoot, TD_DISC_LOCK); + if (TDLIST_EMPTY(&(tmpOnePortContext->discovery.discoveringExpanderList))) + { + tdsaSingleThreadedLeave(tiRoot, TD_DISC_LOCK); + TI_DBG3(("tdsaFindConfigurableExp: empty UpdiscoveringExpanderList\n")); + return agNULL; + } + else + { + tdsaSingleThreadedLeave(tiRoot, TD_DISC_LOCK); + } + tempExpander = oneExpander->tdUpStreamExpander; + while (tempExpander) + { + TI_DBG3(("tdsaFindConfigurableExp: loop exp addrHi 0x%08x\n", tempExpander->tdDevice->SASAddressID.sasAddressHi)); + TI_DBG3(("tdsaFindConfigurableExp: loop exp addrLo 0x%08x\n", tempExpander->tdDevice->SASAddressID.sasAddressLo)); + if (tempExpander->configRouteTable) + { + TI_DBG3(("tdsaFindConfigurableExp: found configurable expander\n")); + ret = tempExpander; + break; + } + tempExpander = tempExpander->tdUpStreamExpander; + } + + return ret; +} + +/***************************************************************************** +*! \brief tdsaSASDownStreamDiscoverExpanderPhy +* +* Purpose: This function actully does downstream traverse and finds out detailed +* information about topology. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* \param oneExpander: Pointer to the expander data. +* \param pDiscoverResp: Pointer to the Discovery SMP respsonse. +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaSASDownStreamDiscoverExpanderPhy( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaExpander_t *oneExpander, + smpRespDiscover_t *pDiscoverResp + ) +{ + tdsaDeviceData_t *oneDeviceData; + tdsaExpander_t *UpStreamExpander; + tdsaDeviceData_t *AttachedDevice = agNULL; + tdsaExpander_t *AttachedExpander; + agsaSASIdentify_t sasIdentify; + bit8 connectionRate; + bit32 attachedSasHi, attachedSasLo; + tdsaSASSubID_t agSASSubID; + tdsaExpander_t *ConfigurableExpander = agNULL; + bit32 dupConfigSASAddr = agFALSE; + bit32 configSASAddressHi; + bit32 configSASAddressLo; + + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhy: start\n")); + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhy: exp addrHi 0x%08x\n", oneExpander->tdDevice->SASAddressID.sasAddressHi)); + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhy: exp addrLo 0x%08x\n", oneExpander->tdDevice->SASAddressID.sasAddressLo)); + + TD_ASSERT(tiRoot, "(tdsaSASDownStreamDiscoverExpanderPhy) agRoot NULL"); + TD_ASSERT(onePortContext, "(tdsaSASDownStreamDiscoverExpanderPhy) pPort NULL"); + TD_ASSERT(oneExpander, "(tdsaSASDownStreamDiscoverExpanderPhy) pExpander NULL"); + TD_ASSERT(pDiscoverResp, "(tdsaSASDownStreamDiscoverExpanderPhy) pDiscoverResp NULL"); + + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhy: onePortContxt=%p oneExpander=%p oneDeviceData=%p\n", onePortContext, oneExpander, oneExpander->tdDevice)); + + if (onePortContext->valid == agFALSE) + { + TI_DBG1(("tdsaSASDownStreamDiscoverExpanderPhy: aborting discovery\n")); + tdsaSASDiscoverAbort(tiRoot, onePortContext); + return; + } +#ifdef TD_INTERNAL_DEBUG + tdsaDumpAllExp(tiRoot, onePortContext, oneExpander); + tdsaFindUpStreamConfigurableExp(tiRoot, oneExpander); + tdsaFindDownStreamConfigurableExp(tiRoot, oneExpander); +#endif + /* (1) Find the device structure of the expander */ + oneDeviceData = oneExpander->tdDevice; + TD_ASSERT(oneDeviceData, "(tdsaSASDownStreamDiscoverExpanderPhy) pDevice NULL"); + + /* for debugging */ + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhy: Phy #%d of SAS %08x-%08x\n", + oneExpander->discoveringPhyId, + oneDeviceData->SASAddressID.sasAddressHi, + oneDeviceData->SASAddressID.sasAddressLo)); + TI_DBG3((" Attached device: %s\n", + ( DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == 0 ? "No Device" : + (DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == 1 ? "End Device" : + (DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == 2 ? "Edge Expander" : "Fanout Expander"))))); + /* for debugging */ + if (oneExpander->discoveringPhyId != pDiscoverResp->phyIdentifier) + { + TI_DBG1(("tdsaSASDownStreamDiscoverExpanderPhy: !!! Incorrect SMP response !!!\n")); + TI_DBG1(("tdsaSASDownStreamDiscoverExpanderPhy: Request PhyID #%d Response PhyID #%d\n", oneExpander->discoveringPhyId, pDiscoverResp->phyIdentifier)); + tdhexdump("NO_DEVICE", (bit8*)pDiscoverResp, sizeof(smpRespDiscover_t)); + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + return; + } + +#ifdef TD_INTERNAL_DEBUG /* debugging only */ + if ( DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_NO_DEVICE) + { + tdhexdump("NO_DEVICE", (bit8*)pDiscoverResp, sizeof(smpRespDiscover_t)); + } +#endif + if ( DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) != SAS_NO_DEVICE) + { + TI_DBG3((" SAS address : %08x-%08x\n", + DISCRSP_GET_ATTACHED_SAS_ADDRESSHI(pDiscoverResp), + DISCRSP_GET_ATTACHED_SAS_ADDRESSLO(pDiscoverResp))); + TI_DBG3((" SSP Target : %d\n", DISCRSP_IS_SSP_TARGET(pDiscoverResp)?1:0)); + TI_DBG3((" STP Target : %d\n", DISCRSP_IS_STP_TARGET(pDiscoverResp)?1:0)); + TI_DBG3((" SMP Target : %d\n", DISCRSP_IS_SMP_TARGET(pDiscoverResp)?1:0)); + TI_DBG3((" SATA DEVICE : %d\n", DISCRSP_IS_SATA_DEVICE(pDiscoverResp)?1:0)); + TI_DBG3((" SSP Initiator : %d\n", DISCRSP_IS_SSP_INITIATOR(pDiscoverResp)?1:0)); + TI_DBG3((" STP Initiator : %d\n", DISCRSP_IS_STP_INITIATOR(pDiscoverResp)?1:0)); + TI_DBG3((" SMP Initiator : %d\n", DISCRSP_IS_SMP_INITIATOR(pDiscoverResp)?1:0)); + TI_DBG3((" Phy ID : %d\n", pDiscoverResp->phyIdentifier)); + TI_DBG3((" Attached Phy ID: %d\n", pDiscoverResp->attachedPhyIdentifier)); + + } + /* end for debugging */ + + /* saving routing attribute for non self-configuring expanders */ + oneExpander->routingAttribute[pDiscoverResp->phyIdentifier] = DISCRSP_GET_ROUTINGATTRIB(pDiscoverResp); + + /* for debugging */ +// dumpRoutingAttributes(tiRoot, oneExpander, pDiscoverResp->phyIdentifier); + + oneExpander->discoverSMPAllowed = agTRUE; + + /* If a device is attached */ + if ( DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) != SAS_NO_DEVICE) + { + /* Setup sasIdentify for the attached device */ + sasIdentify.phyIdentifier = pDiscoverResp->phyIdentifier; + sasIdentify.deviceType_addressFrameType = (bit8)(pDiscoverResp->attachedDeviceType & 0x70); + sasIdentify.initiator_ssp_stp_smp = pDiscoverResp->attached_Ssp_Stp_Smp_Sata_Initiator; + sasIdentify.target_ssp_stp_smp = pDiscoverResp->attached_SataPS_Ssp_Stp_Smp_Sata_Target; + *(bit32*)sasIdentify.sasAddressHi = *(bit32*)pDiscoverResp->attachedSasAddressHi; + *(bit32*)sasIdentify.sasAddressLo = *(bit32*)pDiscoverResp->attachedSasAddressLo; + + /* incremental discovery */ + agSASSubID.sasAddressHi = SA_IDFRM_GET_SAS_ADDRESSHI(&sasIdentify); + agSASSubID.sasAddressLo = SA_IDFRM_GET_SAS_ADDRESSLO(&sasIdentify); + agSASSubID.initiator_ssp_stp_smp = sasIdentify.initiator_ssp_stp_smp; + agSASSubID.target_ssp_stp_smp = sasIdentify.target_ssp_stp_smp; + + attachedSasHi = DISCRSP_GET_ATTACHED_SAS_ADDRESSHI(pDiscoverResp); + attachedSasLo = DISCRSP_GET_ATTACHED_SAS_ADDRESSLO(pDiscoverResp); + + /* If it's a direct routing */ + if ( DISCRSP_GET_ROUTINGATTRIB(pDiscoverResp) == SAS_ROUTING_DIRECT) + { + /* If the attached device is an expander */ + if ( (DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_FANOUT_EXPANDER_DEVICE) + || (DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_EDGE_EXPANDER_DEVICE) ) + + { + TI_DBG1(("tdsaSASDownStreamDiscoverExpanderPhy: **** Topology Error direct routing can't connect to expander\n")); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier = oneExpander->discoveringPhyId; + + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + + return; + } + } + + /* If the expander's attached device is not myself */ + if ( (attachedSasHi != onePortContext->sasLocalAddressHi) + || (attachedSasLo != onePortContext->sasLocalAddressLo) ) + { + /* Find the attached device from discovered list */ + AttachedDevice = tdsaPortSASDeviceFind(tiRoot, onePortContext, attachedSasLo, attachedSasHi); + /* If the device has not been discovered before */ + if ( AttachedDevice == agNULL) //11 + { + /* If the phy has subtractive routing attribute */ + if ( DISCRSP_GET_ROUTINGATTRIB(pDiscoverResp) == SAS_ROUTING_SUBTRACTIVE && + (DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_EDGE_EXPANDER_DEVICE || + DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_FANOUT_EXPANDER_DEVICE) + ) + { + /* TODO: discovery error, callback */ + TI_DBG1(("tdsaSASDownStreamDiscoverExpanderPhy: **** Topology Error subtractive routing error - inconsistent SAS address\n")); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier = oneExpander->discoveringPhyId; + /* discovery done */ + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + } + else + { + /* Add the device */ + /* read minimum rate from the configuration + onePortContext->LinkRate is SPC's local link rate + */ + connectionRate = (bit8)(MIN(onePortContext->LinkRate, DISCRSP_GET_LINKRATE(pDiscoverResp))); + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhy: link rate 0x%x\n", DEVINFO_GET_LINKRATE(&oneDeviceData->agDeviceInfo))); + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhy: negotiatedPhyLinkRate 0x%x\n", DISCRSP_GET_LINKRATE(pDiscoverResp))); + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhy: connectionRate 0x%x\n", connectionRate)); + + if (DISCRSP_IS_STP_TARGET(pDiscoverResp) || DISCRSP_IS_SATA_DEVICE(pDiscoverResp)) + { + if (onePortContext->discovery.type == TDSA_DISCOVERY_OPTION_FULL_START) + { + AttachedDevice = tdsaPortSASDeviceAdd( + tiRoot, + onePortContext, + sasIdentify, + agFALSE, + connectionRate, + IT_NEXUS_TIMEOUT, + 0, + STP_DEVICE_TYPE, + oneDeviceData, + pDiscoverResp->phyIdentifier + ); + } + else + { + /* incremental discovery */ + AttachedDevice = tdsaFindRegNValid( + onePortContext->agRoot, + onePortContext, + &agSASSubID + ); + /* not registered and not valid; add this*/ + if (AttachedDevice == agNULL) + { + AttachedDevice = tdsaPortSASDeviceAdd( + tiRoot, + onePortContext, + sasIdentify, + agFALSE, + connectionRate, + IT_NEXUS_TIMEOUT, + 0, + STP_DEVICE_TYPE, + oneDeviceData, + pDiscoverResp->phyIdentifier + ); + } + } + } + else + { + if (onePortContext->discovery.type == TDSA_DISCOVERY_OPTION_FULL_START) + { + AttachedDevice = tdsaPortSASDeviceAdd( + tiRoot, + onePortContext, + sasIdentify, + agFALSE, + connectionRate, + IT_NEXUS_TIMEOUT, + 0, + SAS_DEVICE_TYPE, + oneDeviceData, + pDiscoverResp->phyIdentifier + ); + } + else + { + /* incremental discovery */ + AttachedDevice = tdsaFindRegNValid( + onePortContext->agRoot, + onePortContext, + &agSASSubID + ); + /* not registered and not valid; add this*/ + if (AttachedDevice == agNULL) + { + AttachedDevice = tdsaPortSASDeviceAdd( + tiRoot, + onePortContext, + sasIdentify, + agFALSE, + connectionRate, + IT_NEXUS_TIMEOUT, + 0, + SAS_DEVICE_TYPE, + oneDeviceData, + pDiscoverResp->phyIdentifier + ); + } + } + } + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhy: newDevice pDevice=%p\n", AttachedDevice)); + /* If the device is added successfully */ + if ( AttachedDevice != agNULL) + { + if ( SA_IDFRM_IS_SSP_TARGET(&sasIdentify) + || SA_IDFRM_IS_SMP_TARGET(&sasIdentify) + || SA_IDFRM_IS_SSP_INITIATOR(&sasIdentify) + || SA_IDFRM_IS_SMP_INITIATOR(&sasIdentify) ) + { + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhy: Report a new SAS device !!\n")); + + } + else + { + if ( SA_IDFRM_IS_STP_TARGET(&sasIdentify) || + SA_IDFRM_IS_SATA_DEVICE(&sasIdentify) ) + { + + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhy: Found an STP or SATA device.\n")); + } + else + { + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhy: Found Other type of device.\n")); + } + } + + /* LP2006-05-26 added upstream device to the newly found device */ + AttachedDevice->tdExpander = oneExpander; + + /* If the phy has table routing attribute */ + if ( DISCRSP_GET_ROUTINGATTRIB(pDiscoverResp) == SAS_ROUTING_TABLE) + { + /* If the attached device is a fan out expander */ + if ( DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_FANOUT_EXPANDER_DEVICE) + { + /* TODO: discovery error, callback */ + TI_DBG1(("tdsaSASDownStreamDiscoverExpanderPhy: **** Topology Error two table routing phys are connected\n")); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier = oneExpander->discoveringPhyId; + /* discovery done */ + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + } + else if ( DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_EDGE_EXPANDER_DEVICE) + { + /* Allocate an expander data structure */ + AttachedExpander = tdssSASDiscoveringExpanderAlloc(tiRoot, onePortContext, AttachedDevice); + + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhy: Found a EDGE exp device.%p\n", AttachedExpander)); + /* If allocate successfully */ + if ( AttachedExpander != agNULL) + { + /* set up downstream information on configurable expander */ + if (oneExpander->configRouteTable) + { + tdsaSASExpanderDownStreamPhyAdd(tiRoot, oneExpander, (bit8) oneExpander->discoveringPhyId); + } + /* Setup upstream information */ + tdsaSASExpanderUpStreamPhyAdd(tiRoot, AttachedExpander, (bit8) oneExpander->discoveringPhyId); + AttachedExpander->hasUpStreamDevice = agTRUE; + AttachedExpander->upStreamSASAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + AttachedExpander->upStreamSASAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + AttachedExpander->tdUpStreamExpander = oneExpander; + /* (2.3.2.2.2.2.2.2.2) Add the pAttachedExpander to discovering list */ + tdssSASDiscoveringExpanderAdd(tiRoot, onePortContext, AttachedExpander); + } + /* If failed to allocate */ + else + { + TI_DBG1(("tdsaSASDownStreamDiscoverExpanderPhy, Failed to allocate expander data structure\n")); + /* discovery done */ + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + } + } + } + /* If status is still DISCOVERY_DOWN_STREAM */ + if ( onePortContext->discovery.status == DISCOVERY_DOWN_STREAM) + { + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhy: 1st before\n")); + tdsaDumpAllUpExp(tiRoot, onePortContext, oneExpander); + UpStreamExpander = oneExpander->tdUpStreamExpander; + ConfigurableExpander = tdsaFindConfigurableExp(tiRoot, onePortContext, oneExpander); + configSASAddressHi = DEVINFO_GET_SAS_ADDRESSHI(&AttachedDevice->agDeviceInfo); + configSASAddressLo = DEVINFO_GET_SAS_ADDRESSLO(&AttachedDevice->agDeviceInfo); + if (ConfigurableExpander) + { + if ( (ConfigurableExpander->tdDevice->SASAddressID.sasAddressHi + == DEVINFO_GET_SAS_ADDRESSHI(&AttachedDevice->agDeviceInfo)) && + (ConfigurableExpander->tdDevice->SASAddressID.sasAddressLo + == DEVINFO_GET_SAS_ADDRESSLO(&AttachedDevice->agDeviceInfo)) + ) + { /* directly attached between oneExpander and ConfigurableExpander */ + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhy: 1st before loc 1\n")); + configSASAddressHi = oneExpander->tdDevice->SASAddressID.sasAddressHi; + configSASAddressLo = oneExpander->tdDevice->SASAddressID.sasAddressLo; + } + else + { + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhy: 1st before loc 2\n")); + configSASAddressHi = DEVINFO_GET_SAS_ADDRESSHI(&AttachedDevice->agDeviceInfo); + configSASAddressLo = DEVINFO_GET_SAS_ADDRESSLO(&AttachedDevice->agDeviceInfo); + } + } /* if !ConfigurableExpander */ + dupConfigSASAddr = tdsaDuplicateConfigSASAddr(tiRoot, + ConfigurableExpander, + configSASAddressHi, + configSASAddressLo + ); + + + if ( ConfigurableExpander && dupConfigSASAddr == agFALSE) + { + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhy: 1st q123\n")); + UpStreamExpander->tdCurrentDownStreamExpander = oneExpander; + ConfigurableExpander->currentDownStreamPhyIndex = + tdsaFindCurrentDownStreamPhyIndex(tiRoot, ConfigurableExpander); + ConfigurableExpander->tdReturnginExpander = oneExpander; + tdsaSASRoutingEntryAdd(tiRoot, + ConfigurableExpander, + ConfigurableExpander->downStreamPhys[ConfigurableExpander->currentDownStreamPhyIndex], + configSASAddressHi, + configSASAddressLo + ); + } + } + } + /* If fail to add the device */ + else + { + TI_DBG1(("tdsaSASDownStreamDiscoverExpanderPhy, Failed to add a device\n")); + /* discovery done */ + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + } + } + } + /* If the device has been discovered before */ + else /* haha discovered before */ + { + /* If the phy has subtractive routing attribute */ + if ( DISCRSP_GET_ROUTINGATTRIB(pDiscoverResp) == SAS_ROUTING_SUBTRACTIVE) + { + /* If the expander doesn't have up stream device */ + if ( oneExpander->hasUpStreamDevice == agFALSE) + { + /* TODO: discovery error, callback */ + TI_DBG1(("tdsaSASDownStreamDiscoverExpanderPhy: **** Topology Error loop, or end device connects to two expanders\n")); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier = oneExpander->discoveringPhyId; + /* discovery done */ + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + } + /* If the expander has up stream device */ + else + { + /* If sas address doesn't match */ + if ( (oneExpander->upStreamSASAddressHi != attachedSasHi) + || (oneExpander->upStreamSASAddressLo != attachedSasLo) ) + { + /* TODO: discovery error, callback */ + TI_DBG1(("tdsaSASDownStreamDiscoverExpanderPhy: **** Topology Error two subtractive phys\n")); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier = oneExpander->discoveringPhyId; + /* discovery done */ + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + } + } + } + /* If the phy has table routing attribute */ + else if ( DISCRSP_GET_ROUTINGATTRIB(pDiscoverResp) == SAS_ROUTING_TABLE) + { + /* If the attached device is a fan out expander */ + if ( DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_FANOUT_EXPANDER_DEVICE) + { + /* (2.3.3.2.1.1) TODO: discovery error, callback */ + TI_DBG1(("tdsaSASDownStreamDiscoverExpanderPhy: **** Topology Error fan out expander to routing table phy\n")); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier = oneExpander->discoveringPhyId; + /* discovery done */ + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + } + /* If the attached device is an edge expander */ + else if ( DISCRSP_GET_ATTACHED_DEVTYPE(pDiscoverResp) == SAS_EDGE_EXPANDER_DEVICE) + { + /* Setup up stream inform */ + AttachedExpander = AttachedDevice->tdExpander; + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhy: Found edge expander=%p\n", AttachedExpander)); + //hhhhhh + /* If the attached expander has up stream device */ + if ( AttachedExpander->hasUpStreamDevice == agTRUE) + { + /* compare the sas address */ + if ( (AttachedExpander->upStreamSASAddressHi + != DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo)) + || (AttachedExpander->upStreamSASAddressLo + != DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo))) + { + /* TODO: discovery error, callback */ + TI_DBG1(("tdsaSASDownStreamDiscoverExpanderPhy: **** Topology Error two table routing phys connected (1)\n")); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier = oneExpander->discoveringPhyId; + /* discovery done */ + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + } + else + { + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhy: Add edge expander=%p\n", AttachedExpander)); + /* set up downstream information on configurable expander */ + if (oneExpander->configRouteTable) + { + tdsaSASExpanderDownStreamPhyAdd(tiRoot, oneExpander, (bit8) oneExpander->discoveringPhyId); + } + /* haha */ + tdsaSASExpanderUpStreamPhyAdd(tiRoot, AttachedExpander, (bit8) oneExpander->discoveringPhyId); + /* Add the pAttachedExpander to discovering list */ + tdssSASDiscoveringExpanderAdd(tiRoot, onePortContext, AttachedExpander); + } + } + /* If the attached expander doesn't have up stream device */ + else + { + /* TODO: discovery error, callback */ + TI_DBG1(("tdsaSASDownStreamDiscoverExpanderPhy: **** Topology Error two table routing phys connected (2)\n")); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressLo + = DEVINFO_GET_SAS_ADDRESSLO(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.sasAddressHi + = DEVINFO_GET_SAS_ADDRESSHI(&oneDeviceData->agDeviceInfo); + onePortContext->discovery.sasAddressIDDiscoverError.phyIdentifier = oneExpander->discoveringPhyId; + /* discovery done */ + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + } + } + } /* for else if (DISCRSP_GET_ROUTINGATTRIB(pDiscoverResp) == SAS_ROUTING_TABLE) */ + + /* do this regradless of sub or table */ + /* If status is still DISCOVERY_DOWN_STREAM */ + if ( onePortContext->discovery.status == DISCOVERY_DOWN_STREAM) + { + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhy: 2nd before\n")); + tdsaDumpAllUpExp(tiRoot, onePortContext, oneExpander); + + UpStreamExpander = oneExpander->tdUpStreamExpander; + ConfigurableExpander = tdsaFindConfigurableExp(tiRoot, onePortContext, oneExpander); + configSASAddressHi = DEVINFO_GET_SAS_ADDRESSHI(&AttachedDevice->agDeviceInfo); + configSASAddressLo = DEVINFO_GET_SAS_ADDRESSLO(&AttachedDevice->agDeviceInfo); + if (ConfigurableExpander) + { + if ( (ConfigurableExpander->tdDevice->SASAddressID.sasAddressHi + == DEVINFO_GET_SAS_ADDRESSHI(&AttachedDevice->agDeviceInfo)) && + (ConfigurableExpander->tdDevice->SASAddressID.sasAddressLo + == DEVINFO_GET_SAS_ADDRESSLO(&AttachedDevice->agDeviceInfo)) + ) + { /* directly attached between oneExpander and ConfigurableExpander */ + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhy: 2nd before loc 1\n")); + configSASAddressHi = oneExpander->tdDevice->SASAddressID.sasAddressHi; + configSASAddressLo = oneExpander->tdDevice->SASAddressID.sasAddressLo; + } + else + { + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhy: 2nd before loc 2\n")); + configSASAddressHi = DEVINFO_GET_SAS_ADDRESSHI(&AttachedDevice->agDeviceInfo); + configSASAddressLo = DEVINFO_GET_SAS_ADDRESSLO(&AttachedDevice->agDeviceInfo); + } + } /* if !ConfigurableExpander */ + dupConfigSASAddr = tdsaDuplicateConfigSASAddr(tiRoot, + ConfigurableExpander, + configSASAddressHi, + configSASAddressLo + ); + + if ( ConfigurableExpander && dupConfigSASAddr == agFALSE) + { + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhy: 2nd q123 \n")); + UpStreamExpander->tdCurrentDownStreamExpander = oneExpander; + ConfigurableExpander->currentDownStreamPhyIndex = + tdsaFindCurrentDownStreamPhyIndex(tiRoot, ConfigurableExpander); + ConfigurableExpander->tdReturnginExpander = oneExpander; + tdsaSASRoutingEntryAdd(tiRoot, + ConfigurableExpander, + ConfigurableExpander->downStreamPhys[ConfigurableExpander->currentDownStreamPhyIndex], + configSASAddressHi, + configSASAddressLo + ); + } + } /* if (onePortContext->discovery.status == DISCOVERY_DOWN_STREAM) */ + /* incremental discovery */ + if (onePortContext->discovery.type == TDSA_DISCOVERY_OPTION_INCREMENTAL_START) + { + connectionRate = (bit8)(MIN(onePortContext->LinkRate, DISCRSP_GET_LINKRATE(pDiscoverResp))); + + if (DISCRSP_IS_STP_TARGET(pDiscoverResp) || DISCRSP_IS_SATA_DEVICE(pDiscoverResp)) + { + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhy: incremental SATA_STP\n")); + + tdsaPortSASDeviceAdd( + tiRoot, + onePortContext, + sasIdentify, + agFALSE, + connectionRate, + IT_NEXUS_TIMEOUT, + 0, + STP_DEVICE_TYPE, + oneDeviceData, + pDiscoverResp->phyIdentifier + ); + } + else + { + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhy: incremental SAS\n")); + + tdsaPortSASDeviceAdd( + tiRoot, + onePortContext, + sasIdentify, + agFALSE, + connectionRate, + IT_NEXUS_TIMEOUT, + 0, + SAS_DEVICE_TYPE, + oneDeviceData, + pDiscoverResp->phyIdentifier + ); + + } + } + + + }/* else; existing devce */ + } /* not attached to myself */ + /* If the attached device is myself */ + else + { + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhy: Found Self\n")); + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhy: 3rd before\n")); + tdsaDumpAllUpExp(tiRoot, onePortContext, oneExpander); + + UpStreamExpander = oneExpander->tdUpStreamExpander; + ConfigurableExpander = tdsaFindConfigurableExp(tiRoot, onePortContext, oneExpander); + dupConfigSASAddr = tdsaDuplicateConfigSASAddr(tiRoot, + ConfigurableExpander, + onePortContext->sasLocalAddressHi, + onePortContext->sasLocalAddressLo + ); + + if ( ConfigurableExpander && dupConfigSASAddr == agFALSE) + { + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhy: 3rd q123 Setup routing table\n")); + UpStreamExpander->tdCurrentDownStreamExpander = oneExpander; + ConfigurableExpander->currentDownStreamPhyIndex = + tdsaFindCurrentDownStreamPhyIndex(tiRoot, ConfigurableExpander); + ConfigurableExpander->tdReturnginExpander = oneExpander; + tdsaSASRoutingEntryAdd(tiRoot, + ConfigurableExpander, + ConfigurableExpander->downStreamPhys[ConfigurableExpander->currentDownStreamPhyIndex], + onePortContext->sasLocalAddressHi, + onePortContext->sasLocalAddressLo + ); + } + } + } + /* If no device is attached */ + else + { + } + + + /* Increment the discovering phy id */ + oneExpander->discoveringPhyId ++; + + /* If the discovery status is DISCOVERY_DOWN_STREAM */ + if ( onePortContext->discovery.status == DISCOVERY_DOWN_STREAM ) + { + /* If not the last phy */ + if ( oneExpander->discoveringPhyId < oneDeviceData->numOfPhys ) + { + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhy: More Phys to discover\n")); + /* continue discovery for the next phy */ + tdsaDiscoverSend(tiRoot, oneDeviceData); + } + /* If the last phy */ + else + { + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhy: No More Phys\n")); + + /* remove the expander from the discovering list */ + tdssSASDiscoveringExpanderRemove(tiRoot, onePortContext, oneExpander); + /* continue downstream discovering */ + tdsaSASDownStreamDiscovering(tiRoot, onePortContext, oneDeviceData); + } + } + else + { + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhy: onePortContext->discovery.status not in DISCOVERY_DOWN_STREAM; status %d\n", onePortContext->discovery.status)); + } + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhy: end return phyID#%d\n", oneExpander->discoveringPhyId - 1)); + + return; +} + +/***************************************************************************** +*! \brief tdsaSASDownStreamDiscoverExpanderPhySkip +* +* Purpose: This function skips a phy which returned PHY_VACANT in SMP +* response in downstream +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* \param oneExpander: Pointer to the expander data. +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaSASDownStreamDiscoverExpanderPhySkip( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaExpander_t *oneExpander + ) +{ + tdsaDeviceData_t *oneDeviceData; + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhySkip: start\n")); + oneDeviceData = oneExpander->tdDevice; + + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhySkip: sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhySkip: sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + + /* Increment the discovering phy id */ + oneExpander->discoveringPhyId ++; + + /* If the discovery status is DISCOVERY_DOWN_STREAM */ + if ( onePortContext->discovery.status == DISCOVERY_DOWN_STREAM ) + { + /* If not the last phy */ + if ( oneExpander->discoveringPhyId < oneDeviceData->numOfPhys ) + { + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhySkip: More Phys to discover\n")); + /* continue discovery for the next phy */ + tdsaDiscoverSend(tiRoot, oneDeviceData); + } + /* If the last phy */ + else + { + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhySkip: No More Phys\n")); + + /* remove the expander from the discovering list */ + tdssSASDiscoveringExpanderRemove(tiRoot, onePortContext, oneExpander); + /* continue downstream discovering */ + tdsaSASDownStreamDiscovering(tiRoot, onePortContext, oneDeviceData); + } + } + else + { + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhySkip: onePortContext->discovery.status not in DISCOVERY_DOWN_STREAM; status %d\n", onePortContext->discovery.status)); + } + TI_DBG3(("tdsaSASDownStreamDiscoverExpanderPhySkip: end return phyID#%d\n", oneExpander->discoveringPhyId - 1)); + + return; +} + +/***************************************************************************** +*! \brief tdsaSASRoutingEntryAdd +* +* Purpose: This function adds a routing entry in the configurable expander. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param oneExpander: Pointer to the expander data. +* \param phyId: Phy identifier. +* \param configSASAddressHi: Upper 4 byte of SAS address. +* \param configSASAddressLo: Lower 4 byte of SAS address. +* +* \return: +* agTRUE Routing entry is added successfully +* agFALSE Routing entry is not added successfully +* +* \note: +* +*****************************************************************************/ +osGLOBAL bit32 +tdsaSASRoutingEntryAdd( + tiRoot_t *tiRoot, + tdsaExpander_t *oneExpander, + bit32 phyId, + bit32 configSASAddressHi, + bit32 configSASAddressLo + ) +{ + bit32 ret = agTRUE; + smpReqConfigureRouteInformation_t confRoutingInfo; + tdsaPortContext_t *onePortContext; + bit32 i; + agsaRoot_t *agRoot; + + TI_DBG3(("tdsaSASRoutingEntryAdd: start\n")); + TI_DBG3(("tdsaSASRoutingEntryAdd: exp addrHi 0x%08x\n", oneExpander->tdDevice->SASAddressID.sasAddressHi)); + TI_DBG3(("tdsaSASRoutingEntryAdd: exp addrLo 0x%08x\n", oneExpander->tdDevice->SASAddressID.sasAddressLo)); + TI_DBG3(("tdsaSASRoutingEntryAdd: phyid %d\n", phyId)); + + /* needs to compare the location of oneExpander and configSASAddress + add only if + oneExpander + | + configSASaddress + + */ + if (oneExpander->tdDevice->SASAddressID.sasAddressHi == configSASAddressHi && + oneExpander->tdDevice->SASAddressID.sasAddressLo == configSASAddressLo + ) + { + TI_DBG3(("tdsaSASRoutingEntryAdd: unnecessary\n")); + return ret; + } + if (oneExpander->routingAttribute[phyId] != SAS_ROUTING_TABLE) + { + TI_DBG3(("tdsaSASRoutingEntryAdd: not table routing, routing is %d\n", oneExpander->routingAttribute[phyId])); + return ret; + } + + agRoot = oneExpander->tdDevice->agRoot; + onePortContext = oneExpander->tdDevice->tdPortContext; + + onePortContext->discovery.status = DISCOVERY_CONFIG_ROUTING; + + /* reset smpReqConfigureRouteInformation_t */ + osti_memset(&confRoutingInfo, 0, sizeof(smpReqConfigureRouteInformation_t)); + if ( oneExpander->currentIndex[phyId] < oneExpander->routingIndex ) + { + TI_DBG3(("tdsaSASRoutingEntryAdd: adding sasAddressHi 0x%08x\n", configSASAddressHi)); + TI_DBG3(("tdsaSASRoutingEntryAdd: adding sasAddressLo 0x%08x\n", configSASAddressLo)); + TI_DBG3(("tdsaSASRoutingEntryAdd: phyid %d currentIndex[phyid] %d\n", phyId, oneExpander->currentIndex[phyId])); + + oneExpander->configSASAddressHi = configSASAddressHi; + oneExpander->configSASAddressLo = configSASAddressLo; + confRoutingInfo.reserved1[0] = 0; + confRoutingInfo.reserved1[1] = 0; + OSSA_WRITE_BE_16(agRoot, confRoutingInfo.expanderRouteIndex, 0, (oneExpander->currentIndex[phyId])); + confRoutingInfo.reserved2 = 0; + confRoutingInfo.phyIdentifier = (bit8)phyId; + confRoutingInfo.reserved3[0] = 0; + confRoutingInfo.reserved3[1] = 0; + confRoutingInfo.disabledBit_reserved4 = 0; + confRoutingInfo.reserved5[0] = 0; + confRoutingInfo.reserved5[1] = 0; + confRoutingInfo.reserved5[2] = 0; + OSSA_WRITE_BE_32(agRoot, confRoutingInfo.routedSasAddressHi, 0, configSASAddressHi); + OSSA_WRITE_BE_32(agRoot, confRoutingInfo.routedSasAddressLo, 0, configSASAddressLo); + for ( i = 0; i < 16; i ++ ) + { + confRoutingInfo.reserved6[i] = 0; + } + tdSMPStart(tiRoot, agRoot, oneExpander->tdDevice, SMP_CONFIGURE_ROUTING_INFORMATION, (bit8 *)&confRoutingInfo, sizeof(smpReqConfigureRouteInformation_t), AGSA_SMP_INIT_REQ, agNULL, 0); + + oneExpander->currentIndex[phyId] ++; + } + else + { + TI_DBG1(("tdsaSASRoutingEntryAdd: Discovery Error routing index overflow for currentIndex=%d, routingIndex=%d\n", oneExpander->currentIndex[phyId], oneExpander->routingIndex)); + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + + ret = agFALSE; + } + + + return ret; +} +/***************************************************************************** +*! \brief tdsaConfigRoutingInfoRespRcvd +* +* Purpose: This function processes Configure Routing Information response. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param agRoot: Pointer to chip/driver Instance. +* \param oneDeviceData: Pointer to the device data. +* \param frameHeader: Pointer to SMP frame header. +* \param frameHandle: A Handle used to refer to the response frame +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +/* needs to traverse only upstream not downstream */ +osGLOBAL void +tdsaConfigRoutingInfoRespRcvd( + tiRoot_t *tiRoot, + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + tdsaDeviceData_t *oneDeviceData, + tdssSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ) +{ + tdsaExpander_t *oneExpander = oneDeviceData->tdExpander; + tdsaExpander_t *UpStreamExpander; + tdsaExpander_t *DownStreamExpander; + tdsaExpander_t *ReturningExpander; + tdsaExpander_t *ConfigurableExpander; + + tdsaPortContext_t *onePortContext; + tdsaDeviceData_t *ReturningExpanderDeviceData; + bit32 dupConfigSASAddr = agFALSE; + + TI_DBG3(("tdsaConfigRoutingInfoRespRcvd: start\n")); + TI_DBG3(("tdsaConfigRoutingInfoRespRcvd: exp addrHi 0x%08x\n", oneExpander->tdDevice->SASAddressID.sasAddressHi)); + TI_DBG3(("tdsaConfigRoutingInfoRespRcvd: exp addrLo 0x%08x\n", oneExpander->tdDevice->SASAddressID.sasAddressLo)); + + onePortContext = oneDeviceData->tdPortContext; + + if (onePortContext->valid == agFALSE) + { + TI_DBG1(("tdsaConfigRoutingInfoRespRcvd: aborting discovery\n")); + tdsaSASDiscoverAbort(tiRoot, onePortContext); + return; + } + + if ( frameHeader->smpFunctionResult == SMP_FUNCTION_ACCEPTED || + frameHeader->smpFunctionResult == PHY_VACANT + ) + { + DownStreamExpander = oneExpander->tdCurrentDownStreamExpander; + if (DownStreamExpander != agNULL) + { + DownStreamExpander->currentUpStreamPhyIndex ++; + TI_DBG3(("tdsaConfigRoutingInfoRespRcvd: DownStreamExpander->currentUpStreamPhyIndex %d\n", DownStreamExpander->currentUpStreamPhyIndex)); + TI_DBG3(("tdsaConfigRoutingInfoRespRcvd: DownStreamExpander->numOfUpStreamPhys %d\n", DownStreamExpander->numOfUpStreamPhys)); + TI_DBG3(("tdsaConfigRoutingInfoRespRcvd: DownStreamExpander addrHi 0x%08x\n", DownStreamExpander->tdDevice->SASAddressID.sasAddressHi)); + TI_DBG3(("tdsaConfigRoutingInfoRespRcvd: DownStreamExpander addrLo 0x%08x\n", DownStreamExpander->tdDevice->SASAddressID.sasAddressLo)); + + } + + oneExpander->currentDownStreamPhyIndex++; + TI_DBG3(("tdsaConfigRoutingInfoRespRcvd: oneExpander->currentDownStreamPhyIndex %d oneExpander->numOfDownStreamPhys %d\n", oneExpander->currentDownStreamPhyIndex, oneExpander->numOfDownStreamPhys)); + + if ( DownStreamExpander != agNULL) + { + if (DownStreamExpander->currentUpStreamPhyIndex < DownStreamExpander->numOfUpStreamPhys) + { + TI_DBG3(("tdsaConfigRoutingInfoRespRcvd: first if\n")); + TI_DBG3(("tdsaConfigRoutingInfoRespRcvd: DownStreamExpander->currentUpStreamPhyIndex %d\n", DownStreamExpander->currentUpStreamPhyIndex)); + + TI_DBG3(("tdsaConfigRoutingInfoRespRcvd: DownStreamExpander->upStreamPhys[] %d\n", DownStreamExpander->upStreamPhys[DownStreamExpander->currentUpStreamPhyIndex])); + + tdsaSASRoutingEntryAdd(tiRoot, + oneExpander, + DownStreamExpander->upStreamPhys[DownStreamExpander->currentUpStreamPhyIndex], + oneExpander->configSASAddressHi, + oneExpander->configSASAddressLo + ); + } + else + { + /* traversing up till discovery Root onePortContext->discovery.RootExp */ + TI_DBG3(("tdsaConfigRoutingInfoRespRcvd: else\n")); + + UpStreamExpander = oneExpander->tdUpStreamExpander; + ConfigurableExpander = tdsaFindConfigurableExp(tiRoot, onePortContext, oneExpander); + if (UpStreamExpander != agNULL) + { + TI_DBG3(("tdsaConfigRoutingInfoRespRcvd: UpStreamExpander addrHi 0x%08x\n", UpStreamExpander->tdDevice->SASAddressID.sasAddressHi)); + TI_DBG3(("tdsaConfigRoutingInfoRespRcvd: UpStreamExpander addrLo 0x%08x\n", UpStreamExpander->tdDevice->SASAddressID.sasAddressLo)); + dupConfigSASAddr = tdsaDuplicateConfigSASAddr(tiRoot, + ConfigurableExpander, + oneExpander->configSASAddressHi, + oneExpander->configSASAddressLo + ); + + if ( ConfigurableExpander != agNULL && dupConfigSASAddr == agFALSE) + { + TI_DBG3(("tdsaConfigRoutingInfoRespRcvd: else if\n")); + + TI_DBG3(("tdsaConfigRoutingInfoRespRcvd: ConfigurableExpander addrHi 0x%08x\n", ConfigurableExpander->tdDevice->SASAddressID.sasAddressHi)); + TI_DBG3(("tdsaConfigRoutingInfoRespRcvd: ConfigurableExpander addrLo 0x%08x\n", ConfigurableExpander->tdDevice->SASAddressID.sasAddressLo)); + + UpStreamExpander->tdCurrentDownStreamExpander = oneExpander; + ConfigurableExpander->currentDownStreamPhyIndex = + tdsaFindCurrentDownStreamPhyIndex(tiRoot, ConfigurableExpander); + ConfigurableExpander->tdReturnginExpander = oneExpander->tdReturnginExpander; + DownStreamExpander->currentUpStreamPhyIndex = 0; + TI_DBG3(("tdsaConfigRoutingInfoRespRcvd: ConfigurableExpander->currentDownStreamPhyIndex %d\n", ConfigurableExpander->currentDownStreamPhyIndex)); + + TI_DBG3(("tdsaConfigRoutingInfoRespRcvd: ConfigurableExpander->downStreamPhys[] %d\n", ConfigurableExpander->downStreamPhys[ConfigurableExpander->currentDownStreamPhyIndex])); + tdsaSASRoutingEntryAdd(tiRoot, + ConfigurableExpander, + ConfigurableExpander->downStreamPhys[ConfigurableExpander->currentDownStreamPhyIndex], + oneExpander->configSASAddressHi, + oneExpander->configSASAddressLo + ); + } + else + { + /* going back to where it was */ + /* ConfigRoutingInfo is done for a target */ + TI_DBG3(("tdsaConfigRoutingInfoRespRcvd: $$$$$$ my change $$$$$ \n")); + ReturningExpander = oneExpander->tdReturnginExpander; + DownStreamExpander->currentUpStreamPhyIndex = 0; + /* debugging */ + if (ReturningExpander != agNULL) + { + TI_DBG3(("tdsaConfigRoutingInfoRespRcvd: ReturningExpander addrHi 0x%08x\n", ReturningExpander->tdDevice->SASAddressID.sasAddressHi)); + TI_DBG3(("tdsaConfigRoutingInfoRespRcvd: ReturningExpander addrLo 0x%08x\n", ReturningExpander->tdDevice->SASAddressID.sasAddressLo)); + + ReturningExpanderDeviceData = ReturningExpander->tdDevice; + + /* No longer in DISCOVERY_CONFIG_ROUTING */ + onePortContext->discovery.status = DISCOVERY_DOWN_STREAM; + + /* If not the last phy */ + if ( ReturningExpander->discoveringPhyId < ReturningExpanderDeviceData->numOfPhys ) + { + TI_DBG3(("tdsaConfigRoutingInfoRespRcvd: More Phys to discover\n")); + /* continue discovery for the next phy */ + /* needs to send only one Discovery not multiple times */ + if (ReturningExpander->discoverSMPAllowed == agTRUE) + { + tdsaDiscoverSend(tiRoot, ReturningExpanderDeviceData); + } + ReturningExpander->discoverSMPAllowed = agFALSE; + } + /* If the last phy */ + else + { + TI_DBG3(("tdsaConfigRoutingInfoRespRcvd: No More Phys\n")); + ReturningExpander->discoverSMPAllowed = agTRUE; + + /* remove the expander from the discovering list */ + tdssSASDiscoveringExpanderRemove(tiRoot, onePortContext, ReturningExpander); + /* continue downstream discovering */ + tdsaSASDownStreamDiscovering(tiRoot, onePortContext, ReturningExpanderDeviceData); + + //DownStreamExpander + } + } + else + { + TI_DBG3(("tdsaConfigRoutingInfoRespRcvd: ReturningExpander is NULL\n")); + } + } + } + else + { + TI_DBG3(("tdsaConfigRoutingInfoRespRcvd: UpStreamExpander is NULL\n")); + } + } + } + } + else + { + TI_DBG1(("tdsaConfigRoutingInfoRespRcvd: Discovery Error SMP function return result error=%x\n", frameHeader->smpFunctionResult)); + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + } + return; +} + +/***************************************************************************** +*! \brief tdsaReportPhySataSend +* +* Purpose: This function sends Report Phy SATA to a device. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param oneDeviceData: Pointer to the device data. +* \param phyId: Phy Identifier. +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaReportPhySataSend( + tiRoot_t *tiRoot, + tdsaDeviceData_t *oneDeviceData, + bit8 phyId + ) +{ + agsaRoot_t *agRoot; + tdsaExpander_t *oneExpander; + tdsaPortContext_t *onePortContext; + smpReqReportPhySata_t smpReportPhySataReq; + + TI_DBG3(("tdsaReportPhySataSend: start\n")); + + agRoot = oneDeviceData->agRoot; + onePortContext = oneDeviceData->tdPortContext; + oneExpander = oneDeviceData->tdExpander; + + if (onePortContext == agNULL) + { + TI_DBG1(("tdsaReportPhySataSend: Error!!! portcontext is NULL\n")); + } + + if (oneExpander == agNULL) + { + TI_DBG1(("tdsaReportPhySataSend: Error!!! expander is NULL\n")); + return; + } + TI_DBG3(("tdsaReportPhySataSend: device %p did %d\n", oneDeviceData, oneDeviceData->id)); + TI_DBG3(("tdsaReportPhySataSend: phyid %d\n", phyId)); + + oneExpander->tdDeviceToProcess = oneDeviceData; + + osti_memset(&smpReportPhySataReq, 0, sizeof(smpReqReportPhySata_t)); + + smpReportPhySataReq.phyIdentifier = phyId; + + + tdSMPStart( + tiRoot, + agRoot, + oneExpander->tdDevice, + SMP_REPORT_PHY_SATA, + (bit8 *)&smpReportPhySataReq, + sizeof(smpReqReportPhySata_t), + AGSA_SMP_INIT_REQ, + agNULL, + 0 + ); + + return; +} + +/***************************************************************************** +*! \brief tdsaReportPhySataRcvd +* +* Purpose: This function processes Report Phy SATA response. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param agRoot: Pointer to chip/driver Instance. +* \param oneDeviceData: Pointer to the device data. +* \param frameHeader: Pointer to SMP frame header. +* \param frameHandle: A Handle used to refer to the response frame +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaReportPhySataRcvd( + tiRoot_t *tiRoot, + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + tdsaDeviceData_t *oneDeviceData, + tdssSMPFrameHeader_t *frameHeader, + agsaFrameHandle_t frameHandle + ) +{ + smpRespReportPhySata_t SMPreportPhySataResp; + smpRespReportPhySata_t *pSMPReportPhySataResp; + tdsaExpander_t *oneExpander = oneDeviceData->tdExpander; + tdsaPortContext_t *onePortContext; + agsaFisRegDeviceToHost_t *fis; + tdsaDeviceData_t *SataDevice; +#ifndef DIRECT_SMP + tdssSMPRequestBody_t *tdSMPRequestBody; +#endif + + TI_DBG3(("tdsaReportPhySataRcvd: start\n")); + TI_DBG3(("tdsaReportPhySataRcvd: sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + TI_DBG3(("tdsaReportPhySataRcvd: sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); +#ifndef DIRECT_SMP + tdSMPRequestBody = (tdssSMPRequestBody_t *)agIORequest->osData; +#endif + /* get the current sata device hanlde stored in the expander structure */ + SataDevice = oneExpander->tdDeviceToProcess; + pSMPReportPhySataResp = &SMPreportPhySataResp; +#ifdef DIRECT_SMP + saFrameReadBlock(agRoot, frameHandle, 4, pSMPReportPhySataResp, sizeof(smpRespReportPhySata_t)); +#else + saFrameReadBlock(agRoot, tdSMPRequestBody->IndirectSMPResp, 4, pSMPReportPhySataResp, sizeof(smpRespReportPhySata_t)); +#endif + + //tdhexdump("tdsaReportPhySataRcvd", (bit8 *)pSMPReportPhySataResp, sizeof(smpRespReportPhySata_t)); + +#ifndef DIRECT_SMP + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->IndirectSMPReqosMemHandle, + tdSMPRequestBody->IndirectSMPReqLen + ); + ostiFreeMemory( + tiRoot, + tdSMPRequestBody->IndirectSMPResposMemHandle, + tdSMPRequestBody->IndirectSMPRespLen + ); +#endif + + onePortContext = oneDeviceData->tdPortContext; + + if (onePortContext->valid == agFALSE) + { + TI_DBG1(("tdsaReportPhySataRcvd: aborting discovery\n")); + tdsaSASDiscoverAbort(tiRoot, onePortContext); + return; + } + if (SataDevice == agNULL) + { + TI_DBG1(("tdsaReportPhySataRcvd: SataDevice is NULL, wrong\n")); + tdsaSASDiscoverAbort(tiRoot, onePortContext); + return; + } + if ( frameHeader->smpFunctionResult == SMP_FUNCTION_ACCEPTED || + frameHeader->smpFunctionResult == PHY_VACANT + ) + { + fis = (agsaFisRegDeviceToHost_t*) &SMPreportPhySataResp.regDevToHostFis; + if (fis->h.fisType == REG_DEV_TO_HOST_FIS) + { + /* save signature */ + TI_DBG3(("tdsaReportPhySataRcvd: saves the signature\n")); + /* saves signature */ + SataDevice->satDevData.satSignature[0] = fis->d.sectorCount; + SataDevice->satDevData.satSignature[1] = fis->d.lbaLow; + SataDevice->satDevData.satSignature[2] = fis->d.lbaMid; + SataDevice->satDevData.satSignature[3] = fis->d.lbaHigh; + SataDevice->satDevData.satSignature[4] = fis->d.device; + SataDevice->satDevData.satSignature[5] = 0; + SataDevice->satDevData.satSignature[6] = 0; + SataDevice->satDevData.satSignature[7] = 0; + + TI_DBG3(("tdsaReportPhySataRcvd: SATA Signature = %02x %02x %02x %02x %02x\n", + SataDevice->satDevData.satSignature[0], + SataDevice->satDevData.satSignature[1], + SataDevice->satDevData.satSignature[2], + SataDevice->satDevData.satSignature[3], + SataDevice->satDevData.satSignature[4])); + /* + no longer, discovery sends sata identify device command + tdsaSATAIdentifyDeviceCmdSend(tiRoot, SataDevice); + */ + SataDevice = tdsaFindRightDevice(tiRoot, onePortContext, SataDevice); + tdsaDiscoveringStpSATADevice(tiRoot, onePortContext, SataDevice); + } + else + { + TI_DBG3(("tdsaReportPhySataRcvd: getting next stp bride\n")); + SataDevice = tdsaFindRightDevice(tiRoot, onePortContext, SataDevice); + tdsaDiscoveringStpSATADevice(tiRoot, onePortContext, SataDevice); + } + } + else + { + TI_DBG3(("tdsaReportPhySataRcvd: siReportPhySataRcvd SMP function return result %x\n", + frameHeader->smpFunctionResult)); + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + } + return; +} + +/***************************************************************************** +*! \brief tdsaSASExpanderUpStreamPhyAdd +* +* Purpose: This function adds upstream expander to a specfic phy. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param oneExpander: Pointer to the expander data. +* \param phyId: Phy Identifier. +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaSASExpanderUpStreamPhyAdd( + tiRoot_t *tiRoot, + tdsaExpander_t *oneExpander, + bit8 phyId + ) +{ + bit32 i; + bit32 hasSet = agFALSE; + + TI_DBG3(("tdsaSASExpanderUpStreamPhyAdd: start, phyid %d\n", phyId)); + TI_DBG3(("tdsaSASExpanderUpStreamPhyAdd: exp addrHi 0x%08x\n", oneExpander->tdDevice->SASAddressID.sasAddressHi)); + TI_DBG3(("tdsaSASExpanderUpStreamPhyAdd: exp addrLo 0x%08x\n", oneExpander->tdDevice->SASAddressID.sasAddressLo)); + TI_DBG3(("tdsaSASExpanderUpStreamPhyAdd: phyid %d numOfUpStreamPhys %d\n", phyId, oneExpander->numOfUpStreamPhys)); + + for ( i = 0; i < oneExpander->numOfUpStreamPhys; i ++ ) + { + if ( oneExpander->upStreamPhys[i] == phyId ) + { + hasSet = agTRUE; + break; + } + } + + if ( hasSet == agFALSE ) + { + oneExpander->upStreamPhys[oneExpander->numOfUpStreamPhys ++] = phyId; + } + + TI_DBG3(("tdsaSASExpanderUpStreamPhyAdd: AFTER phyid %d numOfUpStreamPhys %d\n", phyId, oneExpander->numOfUpStreamPhys)); + + /* for debugging */ + for ( i = 0; i < oneExpander->numOfUpStreamPhys; i ++ ) + { + TI_DBG3(("tdsaSASExpanderUpStreamPhyAdd: index %d upstream[index] %d\n", i, oneExpander->upStreamPhys[i])); + } + return; +} + +/* + just add phys in downstream in configurable expnader +*/ +/***************************************************************************** +*! \brief tdsaSASExpanderDownStreamPhyAdd +* +* Purpose: This function adds downstream expander to a specfic phy. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param oneExpander: Pointer to the expander data. +* \param phyId: Phy Identifier. +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaSASExpanderDownStreamPhyAdd( + tiRoot_t *tiRoot, + tdsaExpander_t *oneExpander, + bit8 phyId + ) +{ + bit32 i; + bit32 hasSet = agFALSE; + + TI_DBG3(("tdsaSASExpanderDownStreamPhyAdd: start, phyid %d\n", phyId)); + TI_DBG3(("tdsaSASExpanderDownStreamPhyAdd: exp addrHi 0x%08x\n", oneExpander->tdDevice->SASAddressID.sasAddressHi)); + TI_DBG3(("tdsaSASExpanderDownStreamPhyAdd: exp addrLo 0x%08x\n", oneExpander->tdDevice->SASAddressID.sasAddressLo)); + TI_DBG3(("tdsaSASExpanderDownStreamPhyAdd: phyid %d numOfDownStreamPhys %d\n", phyId, oneExpander->numOfDownStreamPhys)); + + for ( i = 0; i < oneExpander->numOfDownStreamPhys; i ++ ) + { + if ( oneExpander->downStreamPhys[i] == phyId ) + { + hasSet = agTRUE; + break; + } + } + + if ( hasSet == agFALSE ) + { + oneExpander->downStreamPhys[oneExpander->numOfDownStreamPhys ++] = phyId; + } + + TI_DBG3(("tdsaSASExpanderDownStreamPhyAdd: AFTER phyid %d numOfDownStreamPhys %d\n", phyId, oneExpander->numOfDownStreamPhys)); + + /* for debugging */ + for ( i = 0; i < oneExpander->numOfDownStreamPhys; i ++ ) + { + TI_DBG3(("tdsaSASExpanderDownStreamPhyAdd: index %d downstream[index] %d\n", i, oneExpander->downStreamPhys[i])); + } + return; +} + +/* oneExpander is the configurable expander of interest + phyId is the first phyID in upStreamPhys[0] of downExpander +*/ +/***************************************************************************** +*! \brief tdsaFindCurrentDownStreamPhyIndex +* +* Purpose: This function finds CurrentDownStreamPhyIndex from a configurable +* expander. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param oneExpander: Pointer to the configuralbe expander data. +* +* \return: +* CurrentDownStreamPhyIndex +* +* +*****************************************************************************/ +osGLOBAL bit16 +tdsaFindCurrentDownStreamPhyIndex( + tiRoot_t *tiRoot, + tdsaExpander_t *oneExpander + ) +{ + tdsaExpander_t *DownStreamExpander; + bit16 index = 0; + bit16 i; + bit8 phyId = 0; + + TI_DBG3(("tdsaFindCurrentDownStreamPhyIndex: start\n")); + + if (oneExpander == agNULL) + { + TI_DBG3(("tdsaFindCurrentDownStreamPhyIndex: wrong!!! oneExpander is NULL\n")); + return 0; + } + + DownStreamExpander = oneExpander->tdCurrentDownStreamExpander; + + if (DownStreamExpander == agNULL) + { + TI_DBG3(("tdsaFindCurrentDownStreamPhyIndex: wrong!!! DownStreamExpander is NULL\n")); + return 0; + } + + TI_DBG3(("tdsaFindCurrentDownStreamPhyIndex: exp addrHi 0x%08x\n", oneExpander->tdDevice->SASAddressID.sasAddressHi)); + TI_DBG3(("tdsaFindCurrentDownStreamPhyIndex: exp addrLo 0x%08x\n", oneExpander->tdDevice->SASAddressID.sasAddressLo)); + TI_DBG3(("tdsaFindCurrentDownStreamPhyIndex: downstream exp addrHi 0x%08x\n", DownStreamExpander->tdDevice->SASAddressID.sasAddressHi)); + TI_DBG3(("tdsaFindCurrentDownStreamPhyIndex: downstream exp addrLo 0x%08x\n", DownStreamExpander->tdDevice->SASAddressID.sasAddressLo)); + TI_DBG3(("tdsaFindCurrentDownStreamPhyIndex: numOfDownStreamPhys %d\n", oneExpander->numOfDownStreamPhys)); + + phyId = DownStreamExpander->upStreamPhys[0]; + + TI_DBG3(("tdsaFindCurrentDownStreamPhyIndex: phyId %d\n", phyId)); + + for (i=0; inumOfDownStreamPhys;i++) + { + if (oneExpander->downStreamPhys[i] == phyId) + { + index = i; + break; + } + } + TI_DBG3(("tdsaFindCurrentDownStreamPhyIndex: index %d\n", index)); + return index; +} +/***************************************************************************** +*! \brief tdsaPortSASDeviceFind +* +* Purpose: Given SAS address, this function finds a device with that SAS address +* in the device list. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* \param sasAddrLo: Lower 4 byte of SAS address. +* \param sasAddrHi: Upper 4 byte of SAS address. +* +* \return: +* agNULL When no device found +* Pointer to device When device is found +* +* \note: +* +*****************************************************************************/ +osGLOBAL tdsaDeviceData_t * +tdsaPortSASDeviceFind( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + bit32 sasAddrLo, + bit32 sasAddrHi + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdsaDeviceData_t *oneDeviceData, *RetDeviceData=agNULL; + tdList_t *DeviceListList; + + TI_DBG3(("tdsaPortSASDeviceFind: start\n")); + + TD_ASSERT((agNULL != tiRoot), ""); + TD_ASSERT((agNULL != onePortContext), ""); + + tdsaSingleThreadedEnter(tiRoot, TD_DEVICE_LOCK); + + /* find a device's existence */ + DeviceListList = tdsaAllShared->MainDeviceList.flink; + if (onePortContext->discovery.type == TDSA_DISCOVERY_OPTION_FULL_START) + { + TI_DBG3(("tdsaPortSASDeviceFind: Full discovery\n")); + while (DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + if ((oneDeviceData->SASAddressID.sasAddressHi == sasAddrHi) && + (oneDeviceData->SASAddressID.sasAddressLo == sasAddrLo) && + (oneDeviceData->valid == agTRUE) && + (oneDeviceData->tdPortContext == onePortContext) + ) + { + TI_DBG3(("tdsaPortSASDeviceFind: Found pid %d did %d\n", onePortContext->id, oneDeviceData->id)); + TI_DBG3(("tdsaPortSASDeviceFind: sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG3(("tdsaPortSASDeviceFind: sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + RetDeviceData = oneDeviceData; + break; + } + DeviceListList = DeviceListList->flink; + } + } + else + { + /* incremental discovery */ + TI_DBG3(("tdsaPortSASDeviceFind: Incremental discovery\n")); + while (DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + if ((oneDeviceData->SASAddressID.sasAddressHi == sasAddrHi) && + (oneDeviceData->SASAddressID.sasAddressLo == sasAddrLo) && + (oneDeviceData->valid2 == agTRUE) && + (oneDeviceData->tdPortContext == onePortContext) + ) + { + TI_DBG3(("tdsaPortSASDeviceFind: Found pid %d did %d\n", onePortContext->id, oneDeviceData->id)); + TI_DBG3(("tdsaPortSASDeviceFind: sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG3(("tdsaPortSASDeviceFind: sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + + RetDeviceData = oneDeviceData; + break; + } + DeviceListList = DeviceListList->flink; + } + } + + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + + return RetDeviceData; +} + +/* include both sas and stp-sata targets*/ +/***************************************************************************** +*! \brief tdsaPortSASDeviceAdd +* +* Purpose: This function adds the SAS device to the device list. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* \param sasIdentify: SAS identify address frame. +* \param sasInitiator: SAS initiator. +* \param connectionRate: Connection Rate. +* \param itNexusTimeout: IT NEXUS timeout value. +* \param firstBurstSize: First Burst Size. +* \param deviceType: Device Type. +* +* \return: +* Pointer to device data. +* +* \note: +* +*****************************************************************************/ +GLOBAL tdsaDeviceData_t * +tdsaPortSASDeviceAdd( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + agsaSASIdentify_t sasIdentify, + bit32 sasInitiator, + bit8 connectionRate, + bit32 itNexusTimeout, + bit32 firstBurstSize, + bit32 deviceType, + tdsaDeviceData_t *oneExpDeviceData, + bit8 phyID + ) +{ + tdsaDeviceData_t *oneDeviceData = agNULL; + bit8 dev_s_rate = 0; + bit8 sasorsata = 1; +// bit8 devicetype; + tdsaSASSubID_t agSASSubID; + tdsaDeviceData_t *oneAttachedExpDeviceData = agNULL; + + TI_DBG3(("tdsaPortSASDeviceAdd: start\n")); + TI_DBG3(("tdsaPortSASDeviceAdd: connectionRate %d\n", connectionRate)); + + agSASSubID.sasAddressHi = SA_IDFRM_GET_SAS_ADDRESSHI(&sasIdentify); + agSASSubID.sasAddressLo = SA_IDFRM_GET_SAS_ADDRESSLO(&sasIdentify); + agSASSubID.initiator_ssp_stp_smp = sasIdentify.initiator_ssp_stp_smp; + agSASSubID.target_ssp_stp_smp = sasIdentify.target_ssp_stp_smp; + + /* old device and already registered to LL; added by link-up event */ + if ( agFALSE == tdssNewSASorNot( + onePortContext->agRoot, + onePortContext, + &agSASSubID + ) + ) + { + /* old device and already registered to LL; added by link-up event */ + TI_DBG3(("tdsaPortSASDeviceAdd: OLD qqqq initiator_ssp_stp_smp %d target_ssp_stp_smp %d\n", agSASSubID.initiator_ssp_stp_smp, agSASSubID.target_ssp_stp_smp)); + /* find the old device */ + oneDeviceData = tdssNewAddSASToSharedcontext( + onePortContext->agRoot, + onePortContext, + &agSASSubID, + oneExpDeviceData, + phyID + ); + + if (oneDeviceData == agNULL) + { + TI_DBG1(("tdsaPortSASDeviceAdd: no more device!!! oneDeviceData is null\n")); + } + + /* If a device is allocated */ + if ( oneDeviceData != agNULL ) + { + + TI_DBG3(("tdsaPortSASDeviceAdd: sasAddressHi 0x%08x\n", SA_IDFRM_GET_SAS_ADDRESSHI(&sasIdentify))); + TI_DBG3(("tdsaPortSASDeviceAdd: sasAddressLo 0x%08x\n", SA_IDFRM_GET_SAS_ADDRESSLO(&sasIdentify))); + + oneDeviceData->sasIdentify = sasIdentify; + + TI_DBG3(("tdsaPortSASDeviceAdd: sasAddressHi 0x%08x\n", SA_IDFRM_GET_SAS_ADDRESSHI(&oneDeviceData->sasIdentify))); + TI_DBG3(("tdsaPortSASDeviceAdd: sasAddressLo 0x%08x\n", SA_IDFRM_GET_SAS_ADDRESSLO(&oneDeviceData->sasIdentify))); + + /* parse sasIDframe to fill in agDeviceInfo */ + DEVINFO_PUT_SMPTO(&oneDeviceData->agDeviceInfo, DEFAULT_SMP_TIMEOUT); + DEVINFO_PUT_ITNEXUSTO(&oneDeviceData->agDeviceInfo, (bit16)itNexusTimeout); + DEVINFO_PUT_FBS(&oneDeviceData->agDeviceInfo, (bit16)firstBurstSize); + DEVINFO_PUT_FLAG(&oneDeviceData->agDeviceInfo, 1); + + oneDeviceData->SASSpecDeviceType = (bit8)(SA_IDFRM_GET_DEVICETTYPE(&sasIdentify)); + + /* adjusting connectionRate */ + oneAttachedExpDeviceData = oneDeviceData->ExpDevice; + if (oneAttachedExpDeviceData != agNULL) + { + connectionRate = (bit8)(MIN(connectionRate, DEVINFO_GET_LINKRATE(&oneAttachedExpDeviceData->agDeviceInfo))); + TI_DBG3(("tdsaPortSASDeviceAdd: 1st connectionRate 0x%x DEVINFO_GET_LINKRATE(&oneAttachedExpDeviceData->agDeviceInfo) 0x%x\n", + connectionRate, DEVINFO_GET_LINKRATE(&oneAttachedExpDeviceData->agDeviceInfo))); + } + else + { + TI_DBG3(("tdsaPortSASDeviceAdd: 1st oneAttachedExpDeviceData is NULL\n")); + } + + /* Device Type, SAS or SATA, connection rate; bit7 --- bit0 */ + sasorsata = (bit8)deviceType; + /* sTSDK spec device typ */ + dev_s_rate = (bit8)(dev_s_rate | (sasorsata << 4)); + dev_s_rate = (bit8)(dev_s_rate | connectionRate); + DEVINFO_PUT_DEV_S_RATE(&oneDeviceData->agDeviceInfo, dev_s_rate); + + + DEVINFO_PUT_SAS_ADDRESSLO( + &oneDeviceData->agDeviceInfo, + SA_IDFRM_GET_SAS_ADDRESSLO(&oneDeviceData->sasIdentify) + ); + DEVINFO_PUT_SAS_ADDRESSHI( + &oneDeviceData->agDeviceInfo, + SA_IDFRM_GET_SAS_ADDRESSHI(&oneDeviceData->sasIdentify) + ); + oneDeviceData->agContext.osData = oneDeviceData; + oneDeviceData->agContext.sdkData = agNULL; + + } + return oneDeviceData; + } /* old device */ + + /* new device */ + + TI_DBG3(("tdsaPortSASDeviceAdd: NEW qqqq initiator_ssp_stp_smp %d target_ssp_stp_smp %d\n", agSASSubID.initiator_ssp_stp_smp, agSASSubID.target_ssp_stp_smp)); + + /* allocate a new device and set the valid bit */ + oneDeviceData = tdssNewAddSASToSharedcontext( + onePortContext->agRoot, + onePortContext, + &agSASSubID, + oneExpDeviceData, + phyID + ); + + if (oneDeviceData == agNULL) + { + TI_DBG1(("tdsaPortSASDeviceAdd: no more device!!! oneDeviceData is null\n")); + } + + /* If a device is allocated */ + if ( oneDeviceData != agNULL ) + { + + TI_DBG3(("tdsaPortSASDeviceAdd: sasAddressHi 0x%08x\n", SA_IDFRM_GET_SAS_ADDRESSHI(&sasIdentify))); + TI_DBG3(("tdsaPortSASDeviceAdd: sasAddressLo 0x%08x\n", SA_IDFRM_GET_SAS_ADDRESSLO(&sasIdentify))); + + oneDeviceData->sasIdentify = sasIdentify; + + TI_DBG3(("tdsaPortSASDeviceAdd: sasAddressHi 0x%08x\n", SA_IDFRM_GET_SAS_ADDRESSHI(&oneDeviceData->sasIdentify))); + TI_DBG3(("tdsaPortSASDeviceAdd: sasAddressLo 0x%08x\n", SA_IDFRM_GET_SAS_ADDRESSLO(&oneDeviceData->sasIdentify))); + + + /* parse sasIDframe to fill in agDeviceInfo */ + DEVINFO_PUT_SMPTO(&oneDeviceData->agDeviceInfo, DEFAULT_SMP_TIMEOUT); + DEVINFO_PUT_ITNEXUSTO(&oneDeviceData->agDeviceInfo, (bit16)itNexusTimeout); + DEVINFO_PUT_FBS(&oneDeviceData->agDeviceInfo, (bit16)firstBurstSize); + DEVINFO_PUT_FLAG(&oneDeviceData->agDeviceInfo, 1); + + oneDeviceData->SASSpecDeviceType = (bit8)(SA_IDFRM_GET_DEVICETTYPE(&sasIdentify)); + + /* adjusting connectionRate */ + oneAttachedExpDeviceData = oneDeviceData->ExpDevice; + if (oneAttachedExpDeviceData != agNULL) + { + connectionRate = (bit8)(MIN(connectionRate, DEVINFO_GET_LINKRATE(&oneAttachedExpDeviceData->agDeviceInfo))); + TI_DBG3(("tdsaPortSASDeviceAdd: 2nd connectionRate 0x%x DEVINFO_GET_LINKRATE(&oneAttachedExpDeviceData->agDeviceInfo) 0x%x\n", + connectionRate, DEVINFO_GET_LINKRATE(&oneAttachedExpDeviceData->agDeviceInfo))); + } + else + { + TI_DBG3(("tdsaPortSASDeviceAdd: 2nd oneAttachedExpDeviceData is NULL\n")); + } + + /* Device Type, SAS or SATA, connection rate; bit7 --- bit0 */ + sasorsata = (bit8)deviceType; + dev_s_rate = (bit8)(dev_s_rate | (sasorsata << 4)); + dev_s_rate = (bit8)(dev_s_rate | connectionRate); + DEVINFO_PUT_DEV_S_RATE(&oneDeviceData->agDeviceInfo, dev_s_rate); + + + DEVINFO_PUT_SAS_ADDRESSLO( + &oneDeviceData->agDeviceInfo, + SA_IDFRM_GET_SAS_ADDRESSLO(&oneDeviceData->sasIdentify) + ); + DEVINFO_PUT_SAS_ADDRESSHI( + &oneDeviceData->agDeviceInfo, + SA_IDFRM_GET_SAS_ADDRESSHI(&oneDeviceData->sasIdentify) + ); + oneDeviceData->agContext.osData = oneDeviceData; + oneDeviceData->agContext.sdkData = agNULL; + + TI_DBG3(("tdsaPortSASDeviceAdd: did %d\n", oneDeviceData->id)); + + /* don't add and register initiator for T2D */ + if ( (((sasIdentify.initiator_ssp_stp_smp & DEVICE_SSP_BIT) == DEVICE_SSP_BIT) && + ((sasIdentify.target_ssp_stp_smp & DEVICE_SSP_BIT) != DEVICE_SSP_BIT)) + || + (((sasIdentify.initiator_ssp_stp_smp & DEVICE_STP_BIT) == DEVICE_STP_BIT) && + ((sasIdentify.target_ssp_stp_smp & DEVICE_SSP_BIT) != DEVICE_SSP_BIT)) + ) + { + TI_DBG1(("tdsaPortSASDeviceAdd: initiator. no add and registration\n")); + TI_DBG1(("tdsaPortSASDeviceAdd: sasAddressHi 0x%08x\n", SA_IDFRM_GET_SAS_ADDRESSHI(&oneDeviceData->sasIdentify))); + TI_DBG1(("tdsaPortSASDeviceAdd: sasAddressLo 0x%08x\n", SA_IDFRM_GET_SAS_ADDRESSLO(&oneDeviceData->sasIdentify))); + + } + else + { + if (oneDeviceData->registered == agFALSE) + { + TI_DBG2(("tdsaPortSASDeviceAdd: did %d\n", oneDeviceData->id)); + saRegisterNewDevice( /* tdsaPortSASDeviceAdd */ + onePortContext->agRoot, + &oneDeviceData->agContext, + tdsaRotateQnumber(tiRoot, oneDeviceData), + &oneDeviceData->agDeviceInfo, + onePortContext->agPortContext, + 0 + ); + } + } + } + + return oneDeviceData; +} + +/***************************************************************************** +*! \brief tdsaDiscoveryResetProcessed +* +* Purpose: This function called to reset "processed flag" of device belong to +* a specified port. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ + +osGLOBAL void +tdsaDiscoveryResetProcessed( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext + ) +{ + tdsaDeviceData_t *oneDeviceData = agNULL; + tdList_t *DeviceListList; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + + TI_DBG6(("tdsaDiscoveryResetProcessed: start\n")); + + /* reinitialize the device data belonging to this portcontext */ + DeviceListList = tdsaAllShared->MainDeviceList.flink; + while (DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + TI_DBG6(("tdsaDiscoveryResetProcessed: loop did %d\n", oneDeviceData->id)); + if (oneDeviceData->tdPortContext == onePortContext) + { + TI_DBG6(("tdsaDiscoveryResetProcessed: resetting procssed flag\n")); + oneDeviceData->processed = agFALSE; + } + DeviceListList = DeviceListList->flink; + } + + return; +} + +/***************************************************************************** +*! \brief tdsaSATADiscoverDone +* +* Purpose: This function called to finish up SATA discovery. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* \param flag: status of discovery (success or failure). +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaSATADiscoverDone( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + bit32 flag + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + TI_DBG3(("tdsaSATADiscoverDone: start\n")); + tdsaDiscoveryResetProcessed(tiRoot, onePortContext); + + if (onePortContext->discovery.SeenBC == agTRUE) + { + TI_DBG3(("tdsaSATADiscoverDone: broadcast change; discover again\n")); + tdssInternalRemovals(onePortContext->agRoot, + onePortContext + ); + + /* processed broadcast change */ + onePortContext->discovery.SeenBC = agFALSE; + if (tdsaAllShared->ResetInDiscovery != 0 && + onePortContext->discovery.ResetTriggerred == agTRUE) + { + TI_DBG1(("tdsaSATADiscoverDone: tdsaBCTimer\n")); + tdsaBCTimer(tiRoot, onePortContext); + } + else + { + tdsaDiscover( + tiRoot, + onePortContext, + TDSA_DISCOVERY_TYPE_SAS, + TDSA_DISCOVERY_OPTION_INCREMENTAL_START + ); + } + } + else + { + onePortContext->DiscoveryState = ITD_DSTATE_COMPLETED; + + if (onePortContext->discovery.type == TDSA_DISCOVERY_OPTION_FULL_START) + { + if (flag == tiSuccess) + { +#ifdef AGTIAPI_CTL + tdsaContext_t *tdsaAllShared = + &((tdsaRoot_t*)tiRoot->tdData)->tdsaAllShared; + + if (tdsaAllShared->SASConnectTimeLimit) + tdsaCTLSet(tiRoot, onePortContext, tiIntrEventTypeDiscovery, + tiDiscOK); + else +#endif + ostiInitiatorEvent( + tiRoot, + onePortContext->tiPortalContext, + agNULL, + tiIntrEventTypeDiscovery, + tiDiscOK, + agNULL + ); + } + else + { + TI_DBG1(("tdsaSATADiscoverDone: Error; clean up\n")); + tdssDiscoveryErrorRemovals(onePortContext->agRoot, + onePortContext + ); + + ostiInitiatorEvent( + tiRoot, + onePortContext->tiPortalContext, + agNULL, + tiIntrEventTypeDiscovery, + tiDiscFailed, + agNULL + ); + } + } + else + { + if (flag == tiSuccess) + { + tdssReportChanges(onePortContext->agRoot, + onePortContext + ); + } + else + { + tdssReportRemovals(onePortContext->agRoot, + onePortContext, + agFALSE + ); + } + } + } +#ifdef TBD + /* ACKing BC */ + tdsaAckBC(tiRoot, onePortContext); +#endif + return; +} + +osGLOBAL void +tdsaAckBC( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext + ) +{ +#ifdef TBD /* not yet */ + agsaEventSource_t eventSource[TD_MAX_NUM_PHYS]; + bit32 HwAckSatus = AGSA_RC_SUCCESS; + int i; + TI_DBG3(("tdsaAckBC: start\n")); + + for (i=0;iBCPhyID[i] == agTRUE) + { + /* saHwEventAck() */ + eventSource[i].agPortContext = onePortContext->agPortContext; + eventSource[i].event = OSSA_HW_EVENT_BROADCAST_CHANGE; + /* phy ID */ + eventSource[i].param = i; + HwAckSatus = saHwEventAck( + onePortContext->agRoot, + agNULL, /* agContext */ + 0, + &eventSource[i], /* agsaEventSource_t */ + 0, + 0 + ); + TI_DBG3(("tdsaAckBC: calling saHwEventAck\n")); + + if ( HwAckSatus != AGSA_RC_SUCCESS) + { + TI_DBG1(("tdsaAckBC: failing in saHwEventAck; status %d\n", HwAckSatus)); + return; + } + } + onePortContext->BCPhyID[i] = agFALSE; + } +#endif +} + +#ifdef SATA_ENABLE + +/***************************************************************************** +*! \brief tdsaSATAFullDiscover +* +* Purpose: This function is called to trigger full SATA topology discovery +* within a portcontext. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* +* \return: +* tiSuccess Discovery initiated. +* tiError Discovery could not be initiated at this time. +* +* \note: +* +*****************************************************************************/ +osGLOBAL bit32 +tdsaSATAFullDiscover( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext + ) +{ + bit32 ret = tiSuccess; + tdsaDeviceData_t *oneDeviceData = agNULL; + bit32 deviceType; + bit8 phyRate = SAS_CONNECTION_RATE_3_0G; + bit32 i; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; +// tdsaDeviceData_t *tdsaDeviceData = (tdsaDeviceData_t *)tdsaAllShared->DeviceMem; + tdsaDeviceData_t *tdsaDeviceData; + tdList_t *DeviceListList; + + TI_DBG3(("tdsaSATAFullDiscover: start\n")); + if (onePortContext->valid == agFALSE) + { + TI_DBG1(("tdsaSATAFullDiscover: aborting discovery\n")); + tdsaSASDiscoverAbort(tiRoot, onePortContext); + return tiError; + } + phyRate = onePortContext->LinkRate; + DeviceListList = tdsaAllShared->MainDeviceList.flink; + tdsaDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + /* If port is SATA mode */ + /* + Native SATA mode is decided in ossaHWCB() SAS_LINK_UP or SATA_LINK_UP + */ + if (onePortContext->nativeSATAMode == agTRUE) + { + /* Decode device type */ + deviceType = tdssSATADeviceTypeDecode(onePortContext->remoteSignature); + /* Create a device descriptor for the SATA device attached to the port */ + if ( deviceType == SATA_PM_DEVICE) + { + TI_DBG3(("tdsaSATAFullDiscover: Found a PM device\n")); + oneDeviceData = tdsaPortSATADeviceAdd( + tiRoot, + onePortContext, + agNULL, + onePortContext->remoteSignature, + agTRUE, + 0xF, + phyRate, + agNULL, + 0xFF + ); + } + else + { + /* already added in ossahwcb() in SATA link up */ + TI_DBG3(("tdsaSATAFullDiscover: Found a DIRECT SATA device\n")); + } + + /* Process for different device type */ + switch ( deviceType ) + { + /* if it's PM */ + case SATA_PM_DEVICE: + { + + TI_DBG3(("tdsaSATAFullDiscover: Process a PM device\n")); + /* For each port of the PM */ + for ( i = 0; i < SATA_MAX_PM_PORTS; i ++ ) + { + /* Read the signature */ + /* Decode the device type */ + /* Create device descriptor */ + /* Callback with the discovered devices */ + } + break; + } + /* if it's ATA device */ + case SATA_ATA_DEVICE: + case SATA_ATAPI_DEVICE: + { + TI_DBG3(("tdsaSATAFullDiscover: Process an ATA device. Sending Identify Device cmd\n")); + + /* to-check: for this direct attached one, already added and do nothing */ + /* no longer, discovery sends sata identify device command */ + //tdsaSATAIdentifyDeviceCmdSend(tiRoot, oneDeviceData); + tdsaSATADiscoverDone(tiRoot, onePortContext, tiSuccess); + break; + } + /* Other devices */ + default: + { + /* callback */ + TI_DBG3(("siSATAFullDiscover: Process OTHER SATA device. Just report the device\n")); + break; + } + } + } + /* If port is SAS mode */ + else + { + TI_DBG3(("tdsaSATAFullDiscover: Discovering attached STP devices starts....\n")); + oneDeviceData = tdsaFindRightDevice(tiRoot, onePortContext, tdsaDeviceData); + tdsaDiscoveringStpSATADevice(tiRoot, onePortContext, oneDeviceData); + } + return ret; +} + +/* adding only direct attached SATA such as PM + Other directly attached SATA device such as disk is reported by ossahwcb() in link up + used in sata native mode + */ +/***************************************************************************** +*! \brief tdsaPortSATADeviceAdd +* +* Purpose: This function adds the SATA device to the device list. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* \param oneSTPBridge: STP bridge. +* \param Signature: SATA signature. +* \param pm: Port Multiplier. +* \param pmField: Port Multiplier field. +* \param connectionRate: Connection Rate. +* +* \return: +* Pointer to device data. +* +* \note: +* +*****************************************************************************/ +GLOBAL tdsaDeviceData_t * +tdsaPortSATADeviceAdd( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaDeviceData_t *oneSTPBridge, + bit8 *Signature, + bit8 pm, + bit8 pmField, + bit8 connectionRate, + tdsaDeviceData_t *oneExpDeviceData, + bit8 phyID + ) +{ + tdsaDeviceData_t *oneDeviceData = agNULL; + agsaRoot_t *agRoot = onePortContext->agRoot; + bit8 dev_s_rate = 0; + bit8 sasorsata = SATA_DEVICE_TYPE; +// bit8 devicetype = 0; + bit8 flag = 0; + bit8 TLR = 0; + tdsaDeviceData_t *oneAttachedExpDeviceData = agNULL; + + TI_DBG3(("tdsaPortSATADeviceAdd: start\n")); + + /* sanity check */ + TD_ASSERT((agNULL != tiRoot), ""); + TD_ASSERT((agNULL != agRoot), ""); + TD_ASSERT((agNULL != onePortContext), ""); + TD_ASSERT((agNULL != Signature), ""); + + oneDeviceData = tdssNewAddSATAToSharedcontext( + tiRoot, + agRoot, + onePortContext, + agNULL, + Signature, + pm, + pmField, + connectionRate, + oneExpDeviceData, + phyID + ); + if (oneDeviceData == agNULL) + { + TI_DBG1(("tdsaPortSATADeviceAdd: no more device!!! oneDeviceData is null\n")); + return agNULL; + } + + flag = (bit8)((phyID << 4) | TLR); + DEVINFO_PUT_SMPTO(&oneDeviceData->agDeviceInfo, DEFAULT_SMP_TIMEOUT); + DEVINFO_PUT_ITNEXUSTO(&oneDeviceData->agDeviceInfo, 0xFFF); + DEVINFO_PUT_FBS(&oneDeviceData->agDeviceInfo, 0); + DEVINFO_PUT_FLAG(&oneDeviceData->agDeviceInfo, flag); + + /* adjusting connectionRate */ + oneAttachedExpDeviceData = oneDeviceData->ExpDevice; + if (oneAttachedExpDeviceData != agNULL) + { + connectionRate = (bit8)(MIN(connectionRate, DEVINFO_GET_LINKRATE(&oneAttachedExpDeviceData->agDeviceInfo))); + TI_DBG3(("tdsaPortSATADeviceAdd: 1st connectionRate 0x%x DEVINFO_GET_LINKRATE(&oneAttachedExpDeviceData->agDeviceInfo) 0x%x\n", + connectionRate, DEVINFO_GET_LINKRATE(&oneAttachedExpDeviceData->agDeviceInfo))); + } + else + { + TI_DBG3(("tdsaPortSATADeviceAdd: 1st oneAttachedExpDeviceData is NULL\n")); + } + + /* Device Type, SAS or SATA, connection rate; bit7 --- bit0*/ +// dev_s_rate = dev_s_rate | (devicetype << 6); + dev_s_rate = (bit8)(dev_s_rate | (sasorsata << 4)); + dev_s_rate = (bit8)(dev_s_rate | connectionRate); + DEVINFO_PUT_DEV_S_RATE(&oneDeviceData->agDeviceInfo, dev_s_rate); + + osti_memset(&oneDeviceData->agDeviceInfo.sasAddressHi, 0, 4); + osti_memset(&oneDeviceData->agDeviceInfo.sasAddressLo, 0, 4); + + oneDeviceData->agContext.osData = oneDeviceData; + oneDeviceData->agContext.sdkData = agNULL; + + TI_DBG1(("tdsaPortSATADeviceAdd: did %d\n", oneDeviceData->id)); + if (oneDeviceData->registered == agFALSE) + { + TI_DBG2(("tdsaPortSATADeviceAdd: did %d\n", oneDeviceData->id)); + saRegisterNewDevice( /* tdsaPortSATADeviceAdd */ + onePortContext->agRoot, + &oneDeviceData->agContext, + tdsaRotateQnumber(tiRoot, oneDeviceData), + &oneDeviceData->agDeviceInfo, + onePortContext->agPortContext, + 0 + ); + } + + return oneDeviceData; +} +#endif + +/***************************************************************************** +*! \brief tdsaFindRightDevice +* +* Purpose: This function returns device-to-be processed. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* \param tdsaDeviceData: Pointer to the starting device data. +* +* \return: +* Pointer to device data. +* +* \note: +* +*****************************************************************************/ +osGLOBAL tdsaDeviceData_t * +tdsaFindRightDevice( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaDeviceData_t *tdsaDeviceData + ) +{ + tdList_t *DeviceListList; + tdsaDeviceData_t *oneDeviceData = agNULL; + bit32 found = agFALSE; + + TI_DBG3(("tdsaFindHeadDevice: start\n")); + + DeviceListList = tdsaDeviceData->MainLink.flink; + + while (DeviceListList != &(tdsaDeviceData->MainLink)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + TI_DBG3(("tdsaFindRightDevice: did %d STP %d SATA %d \n", onePortContext->id, DEVICE_IS_STP_TARGET(oneDeviceData), DEVICE_IS_SATA_DEVICE(oneDeviceData))); + DeviceListList = DeviceListList->flink; + } + + DeviceListList = tdsaDeviceData->MainLink.flink; + + while (DeviceListList != &(tdsaDeviceData->MainLink)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + if ((oneDeviceData->registered == agTRUE) && + (oneDeviceData->tdPortContext == onePortContext) && + (oneDeviceData->processed == agFALSE) && + (SA_IDFRM_IS_STP_TARGET(&oneDeviceData->sasIdentify) || + SA_IDFRM_IS_SATA_DEVICE(&oneDeviceData->sasIdentify)) + ) + { + TI_DBG3(("tdsaFindRightDevice: pid %d did %d\n", onePortContext->id, oneDeviceData->id)); + oneDeviceData->processed = agTRUE; + found = agTRUE; + break; + } + DeviceListList = DeviceListList->flink; + } + + if (found == agTRUE) + { + return oneDeviceData; + } + else + { + return agNULL; + } +} + + + +// tdsaDeviceData is head of list +/***************************************************************************** +*! \brief tdsaDiscoveringStpSATADevice +* +* Purpose: For each device in the device list, this function peforms +* SATA discovery. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* \param oneDeviceData: Pointer to the heade of device list. +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaDiscoveringStpSATADevice( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaDeviceData_t *oneDeviceData + ) +{ + bit32 status; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; +// tdsaDeviceData_t *tdsaDeviceData = (tdsaDeviceData_t *)tdsaAllShared->DeviceMem; + tdsaDeviceData_t *tdsaDeviceData; + tdList_t *DeviceListList; + + TI_DBG3(("tdsaDiscoveringStpSATADevice: start\n")); + + DeviceListList = tdsaAllShared->MainDeviceList.flink; + tdsaDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + + if (oneDeviceData) + { + TI_DBG3(("tdsaDiscoveringStpSATADevice: Found STP-SATA Device=%p\n", oneDeviceData)); + if ((SA_IDFRM_IS_SATA_DEVICE(&oneDeviceData->sasIdentify) || SA_IDFRM_IS_STP_TARGET(&oneDeviceData->sasIdentify)) + && + ((onePortContext->discovery.type == TDSA_DISCOVERY_OPTION_FULL_START && + oneDeviceData->valid == agTRUE) || + (onePortContext->discovery.type == TDSA_DISCOVERY_OPTION_INCREMENTAL_START && + oneDeviceData->valid2 == agTRUE)) && + (oneDeviceData->tdPortContext == onePortContext) + ) + { + /* if found an STP bridges */ + /* in order to get sata signature and etc */ + TI_DBG3(("tdsaDiscoveringStpSATADevice: sending report phy sata\n")); + tdsaReportPhySataSend(tiRoot, oneDeviceData, oneDeviceData->sasIdentify.phyIdentifier); + //send ID in every discovery? No + if (oneDeviceData->satDevData.IDDeviceValid == agFALSE) + { + TI_DBG3(("tdsaDiscoveringStpSATADevice: sending identify device data\n")); + /* all internal */ + status = tdsaDiscoveryStartIDDev(tiRoot, + agNULL, + &(oneDeviceData->tiDeviceHandle), + agNULL, + oneDeviceData); + + if (status != tiSuccess) + { + /* identify device data is not valid */ + TI_DBG1(("tdsaDiscoveringStpSATADevice: fail or busy %d\n", status)); + oneDeviceData->satDevData.IDDeviceValid = agFALSE; + } + } + } + else + { + TI_DBG2(("tdsaDiscoveringStpSATADevice: moving to the next\n")); + oneDeviceData = tdsaFindRightDevice(tiRoot, onePortContext, tdsaDeviceData); + tdsaDiscoveringStpSATADevice(tiRoot, onePortContext, oneDeviceData); + } + } + else + { + /* otherwise, there is no more SATA device found */ + TI_DBG3(("tdsaDiscoveringStpSATADevice: No More Device; SATA discovery finished\n")); + + tdsaSATADiscoverDone(tiRoot, onePortContext, tiSuccess); + } + + return; +} + +/***************************************************************************** +*! \brief tdsaSASIncrementalDiscover +* +* Purpose: This function is called to trigger incremental SAS topology discovery +* within a portcontext. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* +* \return: +* tiSuccess Discovery initiated. +* tiError Discovery could not be initiated at this time. +* +* \note: +* +*****************************************************************************/ +osGLOBAL bit32 +tdsaSASIncrementalDiscover( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext + ) +{ + tdsaDeviceData_t *oneDeviceData = agNULL; + int i,j; + bit8 portMaxRate; + + TI_DBG3(("tdsaSASIncrementalDiscover: start\n")); + + if (onePortContext->valid == agFALSE) + { + TI_DBG1(("tdsaSASIncrementalDiscover: aborting discovery\n")); + tdsaSASDiscoverAbort(tiRoot, onePortContext); + return tiError; + } + + onePortContext->DiscoveryState = ITD_DSTATE_STARTED; + + /* nativeSATAMode is set in ossaHwCB() in link up */ + if (onePortContext->nativeSATAMode == agFALSE) /* default: SAS and SAS/SATA mode */ + { + if (SA_IDFRM_GET_DEVICETTYPE(&onePortContext->sasIDframe) == SAS_END_DEVICE && + SA_IDFRM_IS_SSP_TARGET(&onePortContext->sasIDframe) ) + { + for(i=0;iPhyIDList[i] == agTRUE) + { + + for (j=0;jagRoot, agNULL, tdsaRotateQnumber(tiRoot, agNULL), i, AGSA_PHY_NOTIFY_ENABLE_SPINUP, agNULL); + } + break; + } + } + } + /* + add the device + 1. add device in TD layer + 2. call saRegisterNewDevice + 3. update agDevHandle in ossaDeviceRegistrationCB() + */ + portMaxRate = onePortContext->LinkRate; + oneDeviceData = tdsaPortSASDeviceAdd( + tiRoot, + onePortContext, + onePortContext->sasIDframe, + agFALSE, + portMaxRate, + IT_NEXUS_TIMEOUT, + 0, + SAS_DEVICE_TYPE, + agNULL, + 0xFF + ); + if (oneDeviceData) + { + if (oneDeviceData->registered == agFALSE) + { + /* + set the timer and wait till the device(directly attached. eg Expander) to be registered. + Then, in tdsaDeviceRegistrationTimerCB(), tdsaSASUpStreamDiscoverStart() is called + */ + tdsaDeviceRegistrationTimer(tiRoot, onePortContext, oneDeviceData); + } + else + { + tdsaSASUpStreamDiscoverStart(tiRoot, onePortContext, oneDeviceData); + } + } + } + else /* SATAOnlyMode*/ + { + tdsaSASDiscoverDone(tiRoot, onePortContext, tiSuccess); + } + return tiSuccess; +} + +#ifdef SATA_ENABLE +/* For the sake of completness; this is the same as tdsaSATAFullDiscover*/ +/***************************************************************************** +*! \brief tdsaSATAIncrementalDiscover +* +* Purpose: This function is called to trigger incremental SATA topology discovery +* within a portcontext. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* +* \return: +* tiSuccess Discovery initiated. +* tiError Discovery could not be initiated at this time. +* +* \note: +* +*****************************************************************************/ +osGLOBAL bit32 +tdsaSATAIncrementalDiscover( + tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext + ) +{ + bit32 ret = tiSuccess; + tdsaDeviceData_t *oneDeviceData = agNULL; + bit32 deviceType; + bit8 phyRate = SAS_CONNECTION_RATE_3_0G; + bit32 i; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; +// tdsaDeviceData_t *tdsaDeviceData = (tdsaDeviceData_t *)tdsaAllShared->DeviceMem; + tdsaDeviceData_t *tdsaDeviceData; + tdList_t *DeviceListList; + + TI_DBG3(("tdsaSATAIncrementalDiscover: start\n")); + + if (onePortContext->valid == agFALSE) + { + TI_DBG1(("tdsaSATAIncrementalDiscover: aborting discovery\n")); + tdsaSASDiscoverAbort(tiRoot, onePortContext); + return tiError; + } + + DeviceListList = tdsaAllShared->MainDeviceList.flink; + tdsaDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + + /* If port is SATA mode */ + /* + Native SATA mode is decided in ossaHWCB() SAS_LINK_UP or SATA_LINK_UP + */ + if (onePortContext->nativeSATAMode == agTRUE) + { + /* Decode device type */ + deviceType = tdssSATADeviceTypeDecode(onePortContext->remoteSignature); + /* Create a device descriptor for the SATA device attached to the port */ + if ( deviceType == SATA_PM_DEVICE) + { + TI_DBG3(("tdsaSATAIncrementalDiscover: Found a PM device\n")); + oneDeviceData = tdsaPortSATADeviceAdd( + tiRoot, + onePortContext, + agNULL, + onePortContext->remoteSignature, + agTRUE, + 0xF, + phyRate, + agNULL, + 0xFF); + } + else + { + /* already added in ossahwcb() in SATA link up */ + TI_DBG3(("tdsaSATAIncrementalDiscover: Found a DIRECT SATA device\n")); + } + + /* Process for different device type */ + switch ( deviceType ) + { + /* if it's PM */ + case SATA_PM_DEVICE: + { + + TI_DBG3(("tdsaSATAIncrementalDiscover: Process a PM device\n")); + /* For each port of the PM */ + for ( i = 0; i < SATA_MAX_PM_PORTS; i ++ ) + { + /* Read the signature */ + /* Decode the device type */ + /* Create device descriptor */ + /* Callback with the discovered devices */ + } + break; + } + /* if it's ATA device */ + case SATA_ATA_DEVICE: + case SATA_ATAPI_DEVICE: + { + TI_DBG3(("tdsaSATAIncrementalDiscover: Process an ATA device. Sending Identify Device cmd\n")); + + /* to-check: for this direct attached one, already added and do nothing */ + /* no longer, discovery sends sata identify device command */ + //tdsaSATAIdentifyDeviceCmdSend(tiRoot, oneDeviceData); + + tdsaSATADiscoverDone(tiRoot, onePortContext, tiSuccess); + + break; + } + /* Other devices */ + default: + { + /* callback */ + TI_DBG3(("siSATAIncrementalDiscover: Process OTHER SATA device. Just report the device\n")); + + break; + } + } + } + /* If port is SAS mode */ + else + { + TI_DBG3(("tdsaSATAIncrementalDiscover: Discovering attached STP devices starts....\n")); + oneDeviceData = tdsaFindRightDevice(tiRoot, onePortContext, tdsaDeviceData); + + tdsaDiscoveringStpSATADevice(tiRoot, onePortContext, oneDeviceData); + } + return ret; + +} +#endif + + +/******************** SMP *******************************/ + +/***************************************************************************** +*! \brief tdSMPStart +* +* Purpose: This function sends SMP request. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param agRoot: Pointer to chip/driver Instance. +* \param oneDeviceData: Pointer to the device data. +* \param functionCode: SMP function code. +* \param pSmpBody: Pointer to SMP payload. +* \param smpBodySize: Size of SMP request without SMP header. +* \param agRequestType: SPC-specfic request type +* +* \return: +* tiSuccess SMP is sent successfully +* tiError SMP is not sent successfully +* +* \note: +* +*****************************************************************************/ +osGLOBAL bit32 +tdSMPStart( + tiRoot_t *tiRoot, + agsaRoot_t *agRoot, + tdsaDeviceData_t *oneDeviceData, + bit32 functionCode, + bit8 *pSmpBody, /* smp payload itself w/o first 4 bytes(header) */ + bit32 smpBodySize, /* smp payload size w/o first 4 bytes(header) */ + bit32 agRequestType, + tiIORequest_t *CurrentTaskTag, + bit32 queueNumber + ) +{ + void *osMemHandle; + bit32 PhysUpper32; + bit32 PhysLower32; + bit32 memAllocStatus; + bit32 expectedRspLen = 0; + +#ifdef REMOVED + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&(tdsaRoot->tdsaAllShared); +#endif + tdssSMPRequestBody_t *tdSMPRequestBody; + agsaSASRequestBody_t *agSASRequestBody; + agsaSMPFrame_t *agSMPFrame; + agsaIORequest_t *agIORequest; + agsaDevHandle_t *agDevHandle; + tdssSMPFrameHeader_t tdSMPFrameHeader; + tdsaPortContext_t *onePortContext = agNULL; + bit32 status; + +#ifndef DIRECT_SMP + void *IndirectSMPReqosMemHandle; + bit32 IndirectSMPReqPhysUpper32; + bit32 IndirectSMPReqPhysLower32; + bit32 IndirectSMPReqmemAllocStatus; + bit8 *IndirectSMPReq; + + void *IndirectSMPResposMemHandle; + bit32 IndirectSMPRespPhysUpper32; + bit32 IndirectSMPRespPhysLower32; + bit32 IndirectSMPRespmemAllocStatus; + bit8 *IndirectSMPResp; +#endif + + TI_DBG3(("tdSMPStart: start\n")); + TI_DBG3(("tdSMPStart: oneDeviceData %p\n", oneDeviceData)); + TI_DBG3(("tdSMPStart: sasAddressHi 0x%08x\n", SA_IDFRM_GET_SAS_ADDRESSHI(&oneDeviceData->sasIdentify))); + TI_DBG3(("tdSMPStart: sasAddressLo 0x%08x\n", SA_IDFRM_GET_SAS_ADDRESSLO(&oneDeviceData->sasIdentify))); + TI_DBG3(("tdSMPStart: 2nd sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + TI_DBG3(("tdSMPStart: 2nd sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + + onePortContext = oneDeviceData->tdPortContext; + + if (onePortContext != agNULL) + { + TI_DBG3(("tdSMPStart: pid %d\n", onePortContext->id)); + /* increment the number of pending SMP */ + onePortContext->discovery.pendingSMP++; + } + else + { + TI_DBG1(("tdSMPStart: Wrong!!! onePortContext is NULL\n")); + return tiError; + } + + + + memAllocStatus = ostiAllocMemory( + tiRoot, + &osMemHandle, + (void **)&tdSMPRequestBody, + &PhysUpper32, + &PhysLower32, + 8, + sizeof(tdssSMPRequestBody_t), + agTRUE + ); + + if (memAllocStatus != tiSuccess) + { + TI_DBG1(("tdSMPStart: ostiAllocMemory failed...\n")); + return tiError; + } + + if (tdSMPRequestBody == agNULL) + { + TI_DBG1(("tdSMPStart: ostiAllocMemory returned NULL tdSMPRequestBody\n")); + return tiError; + } + /* saves mem handle for freeing later */ + tdSMPRequestBody->osMemHandle = osMemHandle; + + /* saves tdsaDeviceData */ + tdSMPRequestBody->tdDevice = oneDeviceData; + + /* saving port id */ + tdSMPRequestBody->tdPortContext = onePortContext; + + + agDevHandle = oneDeviceData->agDevHandle; + + /* save the callback funtion */ + tdSMPRequestBody->SMPCompletionFunc = itdssSMPCompleted; /* in itdcb.c */ + + /* for simulate warm target reset */ + tdSMPRequestBody->CurrentTaskTag = CurrentTaskTag; + + /* initializes the number of SMP retries */ + tdSMPRequestBody->retries = 0; + +#ifdef TD_INTERNAL_DEBUG /* debugging */ + TI_DBG4(("tdSMPStart: SMPRequestbody %p\n", tdSMPRequestBody)); + TI_DBG4(("tdSMPStart: callback fn %p\n", tdSMPRequestBody->SMPCompletionFunc)); +#endif + + agIORequest = &(tdSMPRequestBody->agIORequest); + agIORequest->osData = (void *) tdSMPRequestBody; + agIORequest->sdkData = agNULL; /* SALL takes care of this */ + + + agSASRequestBody = &(tdSMPRequestBody->agSASRequestBody); + agSMPFrame = &(agSASRequestBody->smpFrame); + + TI_DBG3(("tdSMPStart: agIORequest %p\n", agIORequest)); + TI_DBG3(("tdSMPStart: SMPRequestbody %p\n", tdSMPRequestBody)); + + /* + depending on functionCode, set expectedRspLen in smp + */ + switch (functionCode) + { + case SMP_REPORT_GENERAL: + expectedRspLen = sizeof(smpRespReportGeneral_t) + 4; + break; + case SMP_REPORT_MANUFACTURE_INFORMATION: + expectedRspLen = sizeof(smpRespReportManufactureInfo_t) + 4; + break; + case SMP_DISCOVER: + expectedRspLen = sizeof(smpRespDiscover_t) + 4; + break; + case SMP_REPORT_PHY_ERROR_LOG: + expectedRspLen = 32 - 4; + break; + case SMP_REPORT_PHY_SATA: + expectedRspLen = sizeof(smpRespReportPhySata_t) + 4; + break; + case SMP_REPORT_ROUTING_INFORMATION: + expectedRspLen = sizeof(smpRespReportRouteTable_t) + 4; + break; + case SMP_CONFIGURE_ROUTING_INFORMATION: + expectedRspLen = 4; + break; + case SMP_PHY_CONTROL: + expectedRspLen = 4; + break; + case SMP_PHY_TEST_FUNCTION: + expectedRspLen = 4; + break; + case SMP_PMC_SPECIFIC: + expectedRspLen = 4; + break; + default: + expectedRspLen = 0; + TI_DBG1(("tdSMPStart: error!!! undefined or unused smp function code 0x%x\n", functionCode)); + return tiError; + } + + if (tiIS_SPC(agRoot)) + { +#ifdef DIRECT_SMP /* direct SMP with 48 or less payload */ + if ( (smpBodySize + 4) <= SMP_DIRECT_PAYLOAD_LIMIT) /* 48 */ + { + TI_DBG3(("tdSMPStart: DIRECT smp payload\n")); + osti_memset(&tdSMPFrameHeader, 0, sizeof(tdssSMPFrameHeader_t)); + osti_memset(tdSMPRequestBody->smpPayload, 0, SMP_DIRECT_PAYLOAD_LIMIT); + + /* SMP header */ + tdSMPFrameHeader.smpFrameType = SMP_REQUEST; /* SMP request */ + tdSMPFrameHeader.smpFunction = (bit8)functionCode; + tdSMPFrameHeader.smpFunctionResult = 0; + tdSMPFrameHeader.smpReserved = 0; + + osti_memcpy(tdSMPRequestBody->smpPayload, &tdSMPFrameHeader, 4); +// osti_memcpy((tdSMPRequestBody->smpPayload)+4, pSmpBody, smpBodySize); + osti_memcpy(&(tdSMPRequestBody->smpPayload[4]), pSmpBody, smpBodySize); + + /* direct SMP payload eg) REPORT_GENERAL, DISCOVER etc */ + agSMPFrame->outFrameBuf = tdSMPRequestBody->smpPayload; + agSMPFrame->outFrameLen = smpBodySize + 4; /* without last 4 byte crc */ + /* to specify DIRECT SMP response */ + agSMPFrame->inFrameLen = 0; + + /* temporary solution for T2D Combo*/ +#if defined (INITIATOR_DRIVER) && defined (TARGET_DRIVER) + /* force smp repsonse to be direct */ + agSMPFrame->expectedRespLen = 0; +#else + agSMPFrame->expectedRespLen = expectedRspLen; +#endif +// tdhexdump("tdSMPStart", (bit8*)agSMPFrame->outFrameBuf, agSMPFrame->outFrameLen); +// tdhexdump("tdSMPStart new", (bit8*)tdSMPRequestBody->smpPayload, agSMPFrame->outFrameLen); +// tdhexdump("tdSMPStart - tdSMPRequestBody", (bit8*)tdSMPRequestBody, sizeof(tdssSMPRequestBody_t)); + } + else + { + TI_DBG3(("tdSMPStart: INDIRECT smp payload\n")); + } + +#else + + /* indirect SMP */ + /* allocate Direct SMP request payload */ + IndirectSMPReqmemAllocStatus = ostiAllocMemory( + tiRoot, + &IndirectSMPReqosMemHandle, + (void **)&IndirectSMPReq, + &IndirectSMPReqPhysUpper32, + &IndirectSMPReqPhysLower32, + 8, + smpBodySize + 4, + agFALSE + ); + + if (IndirectSMPReqmemAllocStatus != tiSuccess) + { + TI_DBG1(("tdSMPStart: ostiAllocMemory failed for indirect SMP request...\n")); + return tiError; + } + + if (IndirectSMPReq == agNULL) + { + TI_DBG1(("tdSMPStart: ostiAllocMemory returned NULL IndirectSMPReq\n")); + return tiError; + } + + /* allocate indirect SMP response payload */ + IndirectSMPRespmemAllocStatus = ostiAllocMemory( + tiRoot, + &IndirectSMPResposMemHandle, + (void **)&IndirectSMPResp, + &IndirectSMPRespPhysUpper32, + &IndirectSMPRespPhysLower32, + 8, + expectedRspLen, + agFALSE + ); + + if (IndirectSMPRespmemAllocStatus != tiSuccess) + { + TI_DBG1(("tdSMPStart: ostiAllocMemory failed for indirect SMP reponse...\n")); + return tiError; + } + + if (IndirectSMPResp == agNULL) + { + TI_DBG1(("tdSMPStart: ostiAllocMemory returned NULL IndirectSMPResp\n")); + return tiError; + } + + /* saves mem handle for freeing later */ + tdSMPRequestBody->IndirectSMPReqosMemHandle = IndirectSMPReqosMemHandle; + tdSMPRequestBody->IndirectSMPResposMemHandle = IndirectSMPResposMemHandle; + + /* saves Indirect SMP request/repsonse pointer and length for free them later */ + tdSMPRequestBody->IndirectSMPReq = IndirectSMPReq; + tdSMPRequestBody->IndirectSMPResp = IndirectSMPResp; + tdSMPRequestBody->IndirectSMPReqLen = smpBodySize + 4; + tdSMPRequestBody->IndirectSMPRespLen = expectedRspLen; + + /* fill in indirect SMP request fields */ + TI_DBG3(("tdSMPStart: INDIRECT smp payload\n")); + + /* SMP request and response initialization */ + osti_memset(&tdSMPFrameHeader, 0, sizeof(tdssSMPFrameHeader_t)); + osti_memset(IndirectSMPReq, 0, smpBodySize + 4); + osti_memset(IndirectSMPResp, 0, expectedRspLen); + + /* SMP request header */ + tdSMPFrameHeader.smpFrameType = SMP_REQUEST; /* SMP request */ + tdSMPFrameHeader.smpFunction = (bit8)functionCode; + tdSMPFrameHeader.smpFunctionResult = 0; + tdSMPFrameHeader.smpReserved = 0; + + osti_memcpy(IndirectSMPReq, &tdSMPFrameHeader, 4); + osti_memcpy(IndirectSMPReq+4, pSmpBody, smpBodySize); + + /* Indirect SMP request */ + agSMPFrame->outFrameBuf = agNULL; + agSMPFrame->outFrameAddrUpper32 = IndirectSMPReqPhysUpper32; + agSMPFrame->outFrameAddrLower32 = IndirectSMPReqPhysLower32; + agSMPFrame->outFrameLen = smpBodySize + 4; /* without last 4 byte crc */ + + /* Indirect SMP response */ + agSMPFrame->expectedRespLen = expectedRspLen; + agSMPFrame->inFrameLen = expectedRspLen; /* without last 4 byte crc */ + agSMPFrame->inFrameAddrUpper32 = IndirectSMPRespPhysUpper32; + agSMPFrame->inFrameAddrLower32 = IndirectSMPRespPhysLower32; +#endif + } + else /* SPCv controller */ + { + /* only direct mode for both request and response */ + TI_DBG3(("tdSMPStart: DIRECT smp payload\n")); + agSMPFrame->flag = 0; + osti_memset(&tdSMPFrameHeader, 0, sizeof(tdssSMPFrameHeader_t)); + osti_memset(tdSMPRequestBody->smpPayload, 0, SMP_DIRECT_PAYLOAD_LIMIT); + + /* SMP header */ + tdSMPFrameHeader.smpFrameType = SMP_REQUEST; /* SMP request */ + tdSMPFrameHeader.smpFunction = (bit8)functionCode; + tdSMPFrameHeader.smpFunctionResult = 0; + tdSMPFrameHeader.smpReserved = 0; + + osti_memcpy(tdSMPRequestBody->smpPayload, &tdSMPFrameHeader, 4); +// osti_memcpy((tdSMPRequestBody->smpPayload)+4, pSmpBody, smpBodySize); + osti_memcpy(&(tdSMPRequestBody->smpPayload[4]), pSmpBody, smpBodySize); + + /* direct SMP payload eg) REPORT_GENERAL, DISCOVER etc */ + agSMPFrame->outFrameBuf = tdSMPRequestBody->smpPayload; + agSMPFrame->outFrameLen = smpBodySize + 4; /* without last 4 byte crc */ + /* to specify DIRECT SMP response */ + agSMPFrame->inFrameLen = 0; + + /* temporary solution for T2D Combo*/ +#if defined (INITIATOR_DRIVER) && defined (TARGET_DRIVER) + /* force smp repsonse to be direct */ + agSMPFrame->expectedRespLen = 0; +#else + agSMPFrame->expectedRespLen = expectedRspLen; +#endif +// tdhexdump("tdSMPStart", (bit8*)agSMPFrame->outFrameBuf, agSMPFrame->outFrameLen); +// tdhexdump("tdSMPStart new", (bit8*)tdSMPRequestBody->smpPayload, agSMPFrame->outFrameLen); +// tdhexdump("tdSMPStart - tdSMPRequestBody", (bit8*)tdSMPRequestBody, sizeof(tdssSMPRequestBody_t)); + } + + + if (agDevHandle == agNULL) + { + TI_DBG1(("tdSMPStart: !!! agDevHandle is NULL !!! \n")); + return tiError; + } + + tdSMPRequestBody->queueNumber = queueNumber; + status = saSMPStart( + agRoot, + agIORequest, + queueNumber, //tdsaAllShared->SMPQNum, //tdsaRotateQnumber(tiRoot, oneDeviceData), + agDevHandle, + agRequestType, + agSASRequestBody, + &ossaSMPCompleted + ); + + if (status == AGSA_RC_SUCCESS) + { + /* start SMP timer */ + if (functionCode == SMP_REPORT_GENERAL || functionCode == SMP_DISCOVER || + functionCode == SMP_REPORT_PHY_SATA || functionCode == SMP_CONFIGURE_ROUTING_INFORMATION + ) + { + tdsaDiscoverySMPTimer(tiRoot, onePortContext, functionCode, tdSMPRequestBody); + } + return tiSuccess; + } + else if (status == AGSA_RC_BUSY) + { + /* set timer */ + if (functionCode == SMP_REPORT_GENERAL || functionCode == SMP_DISCOVER || + functionCode == SMP_REPORT_PHY_SATA || functionCode == SMP_CONFIGURE_ROUTING_INFORMATION) + { + /* only for discovery related SMPs*/ + tdsaSMPBusyTimer(tiRoot, onePortContext, oneDeviceData, tdSMPRequestBody); + return tiSuccess; + } + else if (functionCode == SMP_PHY_CONTROL) + { + ostiFreeMemory( + tiRoot, + osMemHandle, + sizeof(tdssSMPRequestBody_t) + ); + return tiBusy; + } + else + { + ostiFreeMemory( + tiRoot, + osMemHandle, + sizeof(tdssSMPRequestBody_t) + ); + return tiBusy; + } + } + else /* AGSA_RC_FAILURE */ + { + /* discovery failure or task management failure */ + if (functionCode == SMP_REPORT_GENERAL || functionCode == SMP_DISCOVER || + functionCode == SMP_REPORT_PHY_SATA || functionCode == SMP_CONFIGURE_ROUTING_INFORMATION) + { + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + } + ostiFreeMemory( + tiRoot, + osMemHandle, + sizeof(tdssSMPRequestBody_t) + ); + + return tiError; + } +} + +#ifdef REMOVED +/***************************************************************************** +*! \brief tdsaFindLocalLinkRate +* +* Purpose: This function finds local link rate. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param tdsaPortStartInfo: Pointer to the port start information. +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL bit8 +tdsaFindLocalLinkRate( + tiRoot_t *tiRoot, + tdsaPortStartInfo_t *tdsaPortStartInfo + ) +{ + bit8 ans = SAS_CONNECTION_RATE_3_0G; /* default */ + bit32 phyProperties; + + phyProperties = tdsaPortStartInfo->agPhyConfig.phyProperties; + + TI_DBG3(("tdsaFindLocalLinkRate: start\n")); + if (phyProperties & 0x4) + { + ans = SAS_CONNECTION_RATE_6_0G; + } + if (phyProperties & 0x2) + { + ans = SAS_CONNECTION_RATE_3_0G; + } + if (phyProperties & 0x1) + { + ans = SAS_CONNECTION_RATE_1_5G; + } + TI_DBG3(("tdsaFindLocalLinkRate: ans 0x%x\n", ans)); + return ans; +} +#endif +/***************************************************************************** +*! \brief tdsaConfigureRouteTimer +* +* Purpose: This function sets timers for configuring routing of discovery and +* its callback function. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* \param oneExpander: Pointer to the expander. +* \param ptdSMPDiscoverResp: Pointer to SMP discover repsonse data. +* +* \return: +* None +* +* \note: called by tdsaDiscoverRespRcvd() +* +*****************************************************************************/ +osGLOBAL void +tdsaConfigureRouteTimer(tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaExpander_t *oneExpander, + smpRespDiscover_t *ptdSMPDiscoverResp + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + itdsaIni_t *Initiator = (itdsaIni_t *)tdsaAllShared->itdsaIni; + tdsaDiscovery_t *discovery; + + TI_DBG1(("tdsaConfigureRouteTimer: start\n")); + TI_DBG1(("tdsaConfigureRouteTimer: pid %d\n", onePortContext->id)); + + discovery = &(onePortContext->discovery); + + TI_DBG1(("tdsaConfigureRouteTimer: onePortContext %p oneExpander %p ptdSMPDiscoverResp %p\n", onePortContext, oneExpander, ptdSMPDiscoverResp)); + + TI_DBG1(("tdsaConfigureRouteTimer: discovery %p \n", discovery)); + + TI_DBG1(("tdsaConfigureRouteTimer: pid %d configureRouteRetries %d\n", onePortContext->id, discovery->configureRouteRetries)); + + TI_DBG1(("tdsaConfigureRouteTimer: discovery->status %d\n", discovery->status)); + + if (discovery->configureRouteTimer.timerRunning == agTRUE) + { + tdsaKillTimer( + tiRoot, + &discovery->configureRouteTimer + ); + } + + TI_DBG1(("tdsaConfigureRouteTimer: UsecsPerTick %d\n", Initiator->OperatingOption.UsecsPerTick)); + TI_DBG1(("tdsaConfigureRouteTimer: Timervalue %d\n", CONFIGURE_ROUTE_TIMER_VALUE/Initiator->OperatingOption.UsecsPerTick)); + + tdsaSetTimerRequest( + tiRoot, + &discovery->configureRouteTimer, + CONFIGURE_ROUTE_TIMER_VALUE/Initiator->OperatingOption.UsecsPerTick, + tdsaConfigureRouteTimerCB, + (void *)onePortContext, + (void *)oneExpander, + (void *)ptdSMPDiscoverResp + ); + + tdsaAddTimer ( + tiRoot, + &Initiator->timerlist, + &discovery->configureRouteTimer + ); + + return; +} + +/***************************************************************************** +*! \brief tdsaConfigureRouteTimerCB +* +* Purpose: This function is callback function for tdsaConfigureRouteTimer. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param timerData1: Pointer to timer-related data structure +* \param timerData2: Pointer to timer-related data structure +* \param timerData3: Pointer to timer-related data structure +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaConfigureRouteTimerCB( + tiRoot_t * tiRoot, + void * timerData1, + void * timerData2, + void * timerData3 + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + itdsaIni_t *Initiator = (itdsaIni_t *)tdsaAllShared->itdsaIni; + tdsaPortContext_t *onePortContext; + tdsaExpander_t *oneExpander; + smpRespDiscover_t *ptdSMPDiscoverResp; + tdsaDiscovery_t *discovery; + + TI_DBG1(("tdsaConfigureRouteTimerCB: start\n")); + + onePortContext = (tdsaPortContext_t *)timerData1; + oneExpander = (tdsaExpander_t *)timerData2; + ptdSMPDiscoverResp = (smpRespDiscover_t *)timerData3; + + discovery = &(onePortContext->discovery); + + TI_DBG1(("tdsaConfigureRouteTimerCB: onePortContext %p oneExpander %p ptdSMPDiscoverResp %p\n", onePortContext, oneExpander, ptdSMPDiscoverResp)); + + TI_DBG1(("tdsaConfigureRouteTimerCB: discovery %p\n", discovery)); + + TI_DBG1(("tdsaConfigureRouteTimerCB: pid %d configureRouteRetries %d\n", onePortContext->id, discovery->configureRouteRetries)); + + TI_DBG1(("tdsaConfigureRouteTimerCB: discovery.status %d\n", discovery->status)); + + discovery->configureRouteRetries++; + if (discovery->configureRouteRetries >= DISCOVERY_RETRIES) + { + TI_DBG1(("tdsaConfigureRouteTimerCB: retries are over\n")); + discovery->configureRouteRetries = 0; + /* failed the discovery */ + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + if (discovery->configureRouteTimer.timerRunning == agTRUE) + { + tdsaKillTimer( + tiRoot, + &discovery->configureRouteTimer + ); + } + return; + } + + + if (onePortContext->discovery.status == DISCOVERY_DOWN_STREAM) + { + TI_DBG1(("tdsaConfigureRouteTimerCB: proceed by calling tdsaSASDownStreamDiscoverExpanderPhy\n")); + tdhexdump("tdsaConfigureRouteTimerCB", (bit8*)ptdSMPDiscoverResp, sizeof(smpRespDiscover_t)); + discovery->configureRouteRetries = 0; + + tdsaSASDownStreamDiscoverExpanderPhy(tiRoot, onePortContext, oneExpander, ptdSMPDiscoverResp); + } + else + { + TI_DBG1(("tdsaConfigureRouteTimerCB: setting timer again\n")); + /* set the timer again */ + tdsaSetTimerRequest( + tiRoot, + &discovery->configureRouteTimer, + CONFIGURE_ROUTE_TIMER_VALUE/Initiator->OperatingOption.UsecsPerTick, + tdsaConfigureRouteTimerCB, + (void *)onePortContext, + (void *)oneExpander, + (void *)ptdSMPDiscoverResp + ); + + tdsaAddTimer ( + tiRoot, + &Initiator->timerlist, + &discovery->configureRouteTimer + ); + } +// tdsaReportGeneralSend(tiRoot, oneDeviceData); + return; +} + +/***************************************************************************** +*! \brief tdsaDiscoveryTimer +* +* Purpose: This function sets timers for discovery and its callback +* function. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* \param oneDeviceData: Pointer to the device data. +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaDiscoveryTimer(tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaDeviceData_t *oneDeviceData + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + itdsaIni_t *Initiator = (itdsaIni_t *)tdsaAllShared->itdsaIni; + tdsaDiscovery_t *discovery; + + TI_DBG1(("tdsaDiscoveryTimer: start\n")); + TI_DBG1(("tdsaDiscoveryTimer: pid %d\n", onePortContext->id)); + + discovery = &(onePortContext->discovery); + + if (discovery->discoveryTimer.timerRunning == agTRUE) + { + tdsaKillTimer( + tiRoot, + &discovery->discoveryTimer + ); + } + + TI_DBG1(("tdsaDiscoveryTimer: UsecsPerTick %d\n", Initiator->OperatingOption.UsecsPerTick)); + TI_DBG1(("tdsaDiscoveryTimer: Timervalue %d\n", DISCOVERY_TIMER_VALUE/Initiator->OperatingOption.UsecsPerTick)); + + tdsaSetTimerRequest( + tiRoot, + &discovery->discoveryTimer, + DISCOVERY_TIMER_VALUE/Initiator->OperatingOption.UsecsPerTick, + tdsaDiscoveryTimerCB, + oneDeviceData, + agNULL, + agNULL + ); + + tdsaAddTimer ( + tiRoot, + &Initiator->timerlist, + &discovery->discoveryTimer + ); + + return; +} + +/***************************************************************************** +*! \brief tdsaDiscoveryTimerCB +* +* Purpose: This function is callback function for discovery timer. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param timerData1: Pointer to timer-related data structure +* \param timerData2: Pointer to timer-related data structure +* \param timerData3: Pointer to timer-related data structure +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaDiscoveryTimerCB( + tiRoot_t * tiRoot, + void * timerData1, + void * timerData2, + void * timerData3 + ) +{ + tdsaDeviceData_t *oneDeviceData; + oneDeviceData = (tdsaDeviceData_t *)timerData1; + + TI_DBG1(("tdsaDiscoveryTimerCB: start\n")); + + if (oneDeviceData->registered == agTRUE) + { + TI_DBG1(("tdsaDiscoveryTimerCB: resumes discovery\n")); + tdsaReportGeneralSend(tiRoot, oneDeviceData); + } + + return; +} + +/***************************************************************************** +*! \brief tdsaDeviceRegistrationTimer +* +* Purpose: This function sets timers for device registration in discovery +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* \param oneDeviceData: Pointer to the device data. +* \return: +* None +* +* \note: called by tdsaSASFullDiscover() or tdsaSASIncrementalDiscover() +* or tdsaDeviceRegistrationTimerCB() +* +*****************************************************************************/ +osGLOBAL void +tdsaDeviceRegistrationTimer(tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaDeviceData_t *oneDeviceData + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + itdsaIni_t *Initiator = (itdsaIni_t *)tdsaAllShared->itdsaIni; + tdsaDiscovery_t *discovery; + + TI_DBG1(("tdsaDeviceRegistrationTimer: start\n")); + TI_DBG1(("tdsaDeviceRegistrationTimer: pid %d\n", onePortContext->id)); + + discovery = &(onePortContext->discovery); + + if (discovery->deviceRegistrationTimer.timerRunning == agTRUE) + { + tdsaKillTimer( + tiRoot, + &discovery->deviceRegistrationTimer + ); + } + + TI_DBG1(("tdsaDeviceRegistrationTimer: UsecsPerTick %d\n", Initiator->OperatingOption.UsecsPerTick)); + TI_DBG1(("tdsaDeviceRegistrationTimer: Timervalue %d\n", DEVICE_REGISTRATION_TIMER_VALUE/Initiator->OperatingOption.UsecsPerTick)); + + tdsaSetTimerRequest( + tiRoot, + &discovery->deviceRegistrationTimer, + DEVICE_REGISTRATION_TIMER_VALUE/Initiator->OperatingOption.UsecsPerTick, + tdsaDeviceRegistrationTimerCB, + onePortContext, + oneDeviceData, + agNULL + ); + + tdsaAddTimer ( + tiRoot, + &Initiator->timerlist, + &discovery->deviceRegistrationTimer + ); + return; +} + +/***************************************************************************** +*! \brief tdsaDeviceRegistrationTimerCB +* +* Purpose: This function is callback function for tdsaDeviceRegistrationTimer. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param timerData1: Pointer to timer-related data structure +* \param timerData2: Pointer to timer-related data structure +* \param timerData3: Pointer to timer-related data structure +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaDeviceRegistrationTimerCB( + tiRoot_t * tiRoot, + void * timerData1, + void * timerData2, + void * timerData3 + ) +{ + tdsaPortContext_t *onePortContext; + tdsaDeviceData_t *oneDeviceData; + tdsaDiscovery_t *discovery; + + TI_DBG1(("tdsaDeviceRegistrationTimerCB: start\n")); + + onePortContext = (tdsaPortContext_t *)timerData1; + oneDeviceData = (tdsaDeviceData_t *)timerData2; + discovery = &(onePortContext->discovery); + + if (oneDeviceData->registered == agFALSE) + { + discovery->deviceRetistrationRetries++; + if (discovery->deviceRetistrationRetries >= DISCOVERY_RETRIES) + { + TI_DBG1(("tdsaDeviceRegistrationTimerCB: retries are over\n")); + discovery->deviceRetistrationRetries = 0; + /* failed the discovery */ + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + if (discovery->deviceRegistrationTimer.timerRunning == agTRUE) + { + tdsaKillTimer( + tiRoot, + &discovery->deviceRegistrationTimer + ); + } + } + else + { + TI_DBG1(("tdsaDeviceRegistrationTimerCB: keep retrying\n")); + /* start timer for device registration */ + tdsaDeviceRegistrationTimer(tiRoot, onePortContext, oneDeviceData); + } + } + else + { + /* go ahead; continue the discovery */ + discovery->deviceRetistrationRetries = 0; + tdsaSASUpStreamDiscoverStart(tiRoot, onePortContext, oneDeviceData); + } +} + +/***************************************************************************** +*! \brief tdsaSMPBusyTimer +* +* Purpose: This function sets timers for busy of saSMPStart. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* \param oneDeviceData: Pointer to the device data. +* \param tdSMPRequestBody: Pointer to the SMP request body. +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaSMPBusyTimer(tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + tdsaDeviceData_t *oneDeviceData, + tdssSMPRequestBody_t *tdSMPRequestBody + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + itdsaIni_t *Initiator = (itdsaIni_t *)tdsaAllShared->itdsaIni; + tdsaDiscovery_t *discovery; + + TI_DBG1(("tdsaSMPBusyTimer: start\n")); + TI_DBG1(("tdsaSMPBusyTimer: pid %d\n", onePortContext->id)); + + discovery = &(onePortContext->discovery); + + if (discovery->SMPBusyTimer.timerRunning == agTRUE) + { + tdsaKillTimer( + tiRoot, + &discovery->SMPBusyTimer + ); + } + + tdsaSetTimerRequest( + tiRoot, + &discovery->SMPBusyTimer, + SMP_BUSY_TIMER_VALUE/Initiator->OperatingOption.UsecsPerTick, + tdsaSMPBusyTimerCB, + onePortContext, + oneDeviceData, + tdSMPRequestBody + ); + + tdsaAddTimer ( + tiRoot, + &Initiator->timerlist, + &discovery->SMPBusyTimer + ); + return; +} + +/***************************************************************************** +*! \brief tdsaSMPBusyTimerCB +* +* Purpose: This function is callback function for SMP busy timer. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param timerData1: Pointer to timer-related data structure +* \param timerData2: Pointer to timer-related data structure +* \param timerData3: Pointer to timer-related data structure +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaSMPBusyTimerCB( + tiRoot_t * tiRoot, + void * timerData1, + void * timerData2, + void * timerData3 + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&(tdsaRoot->tdsaAllShared); + agsaRoot_t *agRoot; + tdsaPortContext_t *onePortContext; + tdsaDeviceData_t *oneDeviceData; + tdssSMPRequestBody_t *tdSMPRequestBody; + agsaSASRequestBody_t *agSASRequestBody; + agsaIORequest_t *agIORequest; + agsaDevHandle_t *agDevHandle; + tdsaDiscovery_t *discovery; + bit32 status = AGSA_RC_FAILURE; + + TI_DBG1(("tdsaSMPBusyTimerCB: start\n")); + + onePortContext = (tdsaPortContext_t *)timerData1; + oneDeviceData = (tdsaDeviceData_t *)timerData2; + tdSMPRequestBody = (tdssSMPRequestBody_t *)timerData3; + agRoot = oneDeviceData->agRoot; + agIORequest = &(tdSMPRequestBody->agIORequest); + agDevHandle = oneDeviceData->agDevHandle; + agSASRequestBody = &(tdSMPRequestBody->agSASRequestBody); + discovery = &(onePortContext->discovery); + + discovery->SMPRetries++; + + if (discovery->SMPRetries < SMP_BUSY_RETRIES) + { + status = saSMPStart( + agRoot, + agIORequest, + tdsaAllShared->SMPQNum, //tdsaRotateQnumber(tiRoot, oneDeviceData), + agDevHandle, + AGSA_SMP_INIT_REQ, + agSASRequestBody, + &ossaSMPCompleted + ); + } + + if (status == AGSA_RC_SUCCESS) + { + discovery->SMPRetries = 0; + if (discovery->SMPBusyTimer.timerRunning == agTRUE) + { + tdsaKillTimer( + tiRoot, + &discovery->SMPBusyTimer + ); + } + } + else if (status == AGSA_RC_FAILURE) + { + discovery->SMPRetries = 0; + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + if (discovery->SMPBusyTimer.timerRunning == agTRUE) + { + tdsaKillTimer( + tiRoot, + &discovery->SMPBusyTimer + ); + } + } + else /* AGSA_RC_BUSY */ + { + if (discovery->SMPRetries >= SMP_BUSY_RETRIES) + { + /* done with retris; give up */ + TI_DBG1(("tdsaSMPBusyTimerCB: retries are over\n")); + discovery->SMPRetries = 0; + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + if (discovery->SMPBusyTimer.timerRunning == agTRUE) + { + tdsaKillTimer( + tiRoot, + &discovery->SMPBusyTimer + ); + } + } + else + { + /* keep retrying */ + tdsaSMPBusyTimer(tiRoot, onePortContext, oneDeviceData, tdSMPRequestBody); + } + } + + return; +} + +/***************************************************************************** +*! \brief tdsaBCTimer +* +* Purpose: This function sets timers for sending ID device data only for +* directly attached SATA device. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* \param oneDeviceData: Pointer to the device data. +* \param tdSMPRequestBody: Pointer to the SMP request body. +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaBCTimer(tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + itdsaIni_t *Initiator = (itdsaIni_t *)tdsaAllShared->itdsaIni; + tdsaDiscovery_t *discovery; + + + TI_DBG1(("tdsaBCTimer: start\n")); + + discovery = &(onePortContext->discovery); + + if (discovery->BCTimer.timerRunning == agTRUE) + { + tdsaKillTimer( + tiRoot, + &discovery->BCTimer + ); + } + + if (onePortContext->valid == agTRUE) + { + tdsaSetTimerRequest( + tiRoot, + &discovery->BCTimer, + BC_TIMER_VALUE/Initiator->OperatingOption.UsecsPerTick, + tdsaBCTimerCB, + onePortContext, + agNULL, + agNULL + ); + + tdsaAddTimer( + tiRoot, + &Initiator->timerlist, + &discovery->BCTimer + ); + + } + + return; +} + +/***************************************************************************** +*! \brief tdsaBCTimerCB +* +* Purpose: This function is callback function for SATA ID device data. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param timerData1: Pointer to timer-related data structure +* \param timerData2: Pointer to timer-related data structure +* \param timerData3: Pointer to timer-related data structure +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaBCTimerCB( + tiRoot_t * tiRoot, + void * timerData1, + void * timerData2, + void * timerData3 + ) +{ + tdsaPortContext_t *onePortContext; + tdsaDiscovery_t *discovery; + + TI_DBG1(("tdsaBCTimerCB: start\n")); + + onePortContext = (tdsaPortContext_t *)timerData1; + discovery = &(onePortContext->discovery); + + discovery->ResetTriggerred = agFALSE; + + if (onePortContext->valid == agTRUE) + { + tdsaDiscover( + tiRoot, + onePortContext, + TDSA_DISCOVERY_TYPE_SAS, + TDSA_DISCOVERY_OPTION_INCREMENTAL_START + ); + } + if (discovery->BCTimer.timerRunning == agTRUE) + { + tdsaKillTimer( + tiRoot, + &discovery->BCTimer + ); + } + + return; +} + +/***************************************************************************** +*! \brief tdsaDiscoverySMPTimer +* +* Purpose: This function sets timers for sending discovery-related SMP +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* \param functionCode: SMP function. +* \param tdSMPRequestBody: Pointer to the SMP request body. +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaDiscoverySMPTimer(tiRoot_t *tiRoot, + tdsaPortContext_t *onePortContext, + bit32 functionCode, /* smp function code */ + tdssSMPRequestBody_t *tdSMPRequestBody + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + itdsaIni_t *Initiator = (itdsaIni_t *)tdsaAllShared->itdsaIni; + tdsaDiscovery_t *discovery; + + TI_DBG3(("tdsaDiscoverySMPTimer: start\n")); + TI_DBG3(("tdsaDiscoverySMPTimer: pid %d SMPFn 0x%x\n", onePortContext->id, functionCode)); + + /* start the SMP timer which works as SMP application timer */ + discovery = &(onePortContext->discovery); + + if (discovery->DiscoverySMPTimer.timerRunning == agTRUE) + { + tdsaKillTimer( + tiRoot, + &discovery->DiscoverySMPTimer + ); + } + tdsaSetTimerRequest( + tiRoot, + &discovery->DiscoverySMPTimer, + SMP_TIMER_VALUE/Initiator->OperatingOption.UsecsPerTick, + tdsaDiscoverySMPTimerCB, + onePortContext, + tdSMPRequestBody, + agNULL + ); + + tdsaAddTimer ( + tiRoot, + &Initiator->timerlist, + &discovery->DiscoverySMPTimer + ); + + return; +} + +/***************************************************************************** +*! \brief tdsaDiscoverySMPTimerCB +* +* Purpose: This function is callback function for tdsaDiscoverySMPTimer. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param timerData1: Pointer to timer-related data structure +* \param timerData2: Pointer to timer-related data structure +* \param timerData3: Pointer to timer-related data structure +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaDiscoverySMPTimerCB( + tiRoot_t * tiRoot, + void * timerData1, + void * timerData2, + void * timerData3 + ) +{ + agsaRoot_t *agRoot; + tdsaPortContext_t *onePortContext; + bit8 SMPFunction; +#ifndef DIRECT_SMP + tdssSMPFrameHeader_t *tdSMPFrameHeader; + bit8 smpHeader[4]; +#endif + tdssSMPRequestBody_t *tdSMPRequestBody; + tdsaDiscovery_t *discovery; + tdsaDeviceData_t *oneDeviceData; + agsaIORequest_t *agAbortIORequest = agNULL; + tdIORequestBody_t *tdAbortIORequestBody = agNULL; + bit32 PhysUpper32; + bit32 PhysLower32; + bit32 memAllocStatus; + void *osMemHandle; + agsaIORequest_t *agToBeAbortIORequest = agNULL; + + TI_DBG1(("tdsaDiscoverySMPTimerCB: start\n")); + + /* no retry + if discovery related SMP, fail the discovery + else .... + be sure to abort SMP + */ + onePortContext = (tdsaPortContext_t *)timerData1; + tdSMPRequestBody = (tdssSMPRequestBody_t *)timerData2; + + discovery = &(onePortContext->discovery); + oneDeviceData = tdSMPRequestBody->tdDevice; + agToBeAbortIORequest = &(tdSMPRequestBody->agIORequest); + agRoot = oneDeviceData->agRoot; + +#ifdef DIRECT_SMP + SMPFunction = tdSMPRequestBody->smpPayload[1]; +#else + saFrameReadBlock(agRoot, tdSMPRequestBody->IndirectSMPResp, 0, smpHeader, 4); + tdSMPFrameHeader = (tdssSMPFrameHeader_t *)smpHeader; + SMPFunction = tdSMPFrameHeader->smpFunction; +#endif + + TI_DBG1(("tdsaDiscoverySMPTimerCB: SMP function 0x%x\n", SMPFunction)); + + if (discovery->DiscoverySMPTimer.timerRunning == agTRUE) + { + tdsaKillTimer( + tiRoot, + &discovery->DiscoverySMPTimer + ); + } + switch (SMPFunction) + { + case SMP_REPORT_GENERAL: /* fall through */ + case SMP_DISCOVER: /* fall through */ + case SMP_CONFIGURE_ROUTING_INFORMATION: /* fall through */ + TI_DBG1(("tdsaDiscoverySMPTimerCB: failing discovery, SMP function 0x%x\n", SMPFunction)); + tdsaSASDiscoverDone(tiRoot, onePortContext, tiError); + return; + case SMP_REPORT_PHY_SATA: + TI_DBG1(("tdsaDiscoverySMPTimerCB: failing discovery, SMP function SMP_REPORT_PHY_SATA\n")); + tdsaSATADiscoverDone(tiRoot, onePortContext, tiError); + break; + default: + /* do nothing */ + TI_DBG1(("tdsaDiscoverySMPTimerCB: Error!!!! not allowed case\n")); + break; + } + + if (onePortContext->discovery.SeenBC == agTRUE) + { + /* allocating agIORequest for abort itself */ + memAllocStatus = ostiAllocMemory( + tiRoot, + &osMemHandle, + (void **)&tdAbortIORequestBody, + &PhysUpper32, + &PhysLower32, + 8, + sizeof(tdIORequestBody_t), + agTRUE + ); + if (memAllocStatus != tiSuccess) + { + /* let os process IO */ + TI_DBG1(("tdsaDiscoverySMPTimerCB: ostiAllocMemory failed...\n")); + return; + } + + if (tdAbortIORequestBody == agNULL) + { + /* let os process IO */ + TI_DBG1(("tdsaDiscoverySMPTimerCB: ostiAllocMemory returned NULL tdAbortIORequestBody\n")); + return; + } + + /* setup task management structure */ + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle = osMemHandle; + /* setting callback */ + tdAbortIORequestBody->IOCompletionFunc = itdssIOAbortedHandler; + + tdAbortIORequestBody->tiDevHandle = (tiDeviceHandle_t *)&(oneDeviceData->tiDeviceHandle); + + /* initialize agIORequest */ + agAbortIORequest = &(tdAbortIORequestBody->agIORequest); + agAbortIORequest->osData = (void *) tdAbortIORequestBody; + agAbortIORequest->sdkData = agNULL; /* LL takes care of this */ + + /* SMPAbort - abort one */ + saSMPAbort(agRoot, + agAbortIORequest, + 0, + oneDeviceData->agDevHandle, + 0, /* abort one */ + agToBeAbortIORequest, + agNULL + ); + + } + return; +} + + +/***************************************************************************** +*! \brief tdsaSATAIDDeviceTimer +* +* Purpose: This function sets timers for sending ID device data only for +* directly attached SATA device. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param onePortContext: Pointer to the portal context instance. +* \param oneDeviceData: Pointer to the device data. +* \param tdSMPRequestBody: Pointer to the SMP request body. +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaSATAIDDeviceTimer(tiRoot_t *tiRoot, + tdsaDeviceData_t *oneDeviceData + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + itdsaIni_t *Initiator = (itdsaIni_t *)tdsaAllShared->itdsaIni; + + TI_DBG1(("tdsaSATAIDDeviceTimer: start\n")); + + if (oneDeviceData->SATAIDDeviceTimer.timerRunning == agTRUE) + { + tdsaKillTimer( + tiRoot, + &oneDeviceData->SATAIDDeviceTimer + ); + } + + tdsaSetTimerRequest( + tiRoot, + &oneDeviceData->SATAIDDeviceTimer, + SATA_ID_DEVICE_DATA_TIMER_VALUE/Initiator->OperatingOption.UsecsPerTick, + tdsaSATAIDDeviceTimerCB, + oneDeviceData, + agNULL, + agNULL + ); + + tdsaAddTimer ( + tiRoot, + &Initiator->timerlist, + &oneDeviceData->SATAIDDeviceTimer + ); + + return; +} + +/***************************************************************************** +*! \brief tdsaSATAIDDeviceTimerCB +* +* Purpose: This function is callback function for SATA ID device data. +* +* \param tiRoot: Pointer to the OS Specific module allocated tiRoot_t +* instance. +* \param timerData1: Pointer to timer-related data structure +* \param timerData2: Pointer to timer-related data structure +* \param timerData3: Pointer to timer-related data structure +* +* \return: +* None +* +* \note: +* +*****************************************************************************/ +osGLOBAL void +tdsaSATAIDDeviceTimerCB( + tiRoot_t * tiRoot, + void * timerData1, + void * timerData2, + void * timerData3 + ) +{ + tdsaDeviceData_t *oneDeviceData; + + TI_DBG1(("tdsaSATAIDDeviceTimerCB: start\n")); + + oneDeviceData = (tdsaDeviceData_t *)timerData1; + + /* send identify device data */ + tdssSubAddSATAToSharedcontext(tiRoot, oneDeviceData); + + if (oneDeviceData->SATAIDDeviceTimer.timerRunning == agTRUE) + { + tdsaKillTimer( + tiRoot, + &oneDeviceData->SATAIDDeviceTimer + ); + } + + return; +} + +#endif /* TD_DISCOVER */ diff --git a/sys/dev/pms/RefTisa/tisa/sassata/sas/ini/itdglobl.h b/sys/dev/pms/RefTisa/tisa/sassata/sas/ini/itdglobl.h new file mode 100644 index 000000000000..3253021c64b5 --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/sas/ini/itdglobl.h @@ -0,0 +1,51 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/*******************************************************************************/ +/** \file + * + * #define for SAS intiator in SAS/SATA TD layer + * + */ + + +#ifndef __ITD_GLOBALS_H__ + +#define __ITD_GLOBALS_H__ + + +/* + * Transport specific default parameters. + */ +#define DEFAULT_NUM_DOMAINS 1 +#define DEFAULT_NUM_AREAS_PER_DOMAIN 1 +#define DEFAULT_DEVSLOTS_PER_AREA 128 +#define DEFAULT_MAX_TARGETS 256 +#define DEFAULT_EVENT_LOG_ELEMENTS 64 +#define DEFAULT_INI_TIMER_TICK 1000000 /* 1 second */ +#define DEFAULT_TOTAL_DYNAMIC_MEM 0 + + + + +#endif /* __ITD_GLOBALS_H__ */ diff --git a/sys/dev/pms/RefTisa/tisa/sassata/sas/ini/itdinit.c b/sys/dev/pms/RefTisa/tisa/sassata/sas/ini/itdinit.c new file mode 100644 index 000000000000..2e8a7d970ea6 --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/sas/ini/itdinit.c @@ -0,0 +1,456 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +/*******************************************************************************/ +/** \file + * + * + * This file contains initiator initialization functions + * + */ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#ifdef FDS_SM +#include +#include +#include +#endif + +#ifdef FDS_DM +#include +#include +#include +#endif + +#include +#include +#include + +#ifdef INITIATOR_DRIVER +#include +#include +#include +#endif + +#ifdef TARGET_DRIVER +#include +#include +#include +#endif + +#include +#include + +/***************************************************************************** +*! \brief itdssGetResource +* +* Purpose: This function is called to determine the Transport +* Dependent Layer internal resource requirement for the initiator +* side. +* +* /param tiRoot: Pointer to driver/port instance. +* /param initiatorResource: Pointer to initiator functionality memory and +* option requirement. +* +* /return: None +* +* /note - This function only return the memory requirement in the tiMem_t +* structure in initiatorResource. It does not allocated memory, so the +* address fields in tiMem_t are not used. +* +*****************************************************************************/ +osGLOBAL void +itdssGetResource( + tiRoot_t * tiRoot, + tiInitiatorResource_t * initiatorResource + ) +{ + itdssOperatingOption_t OperatingOption; + tiInitiatorMem_t *iniMem; + bit32 i; + + iniMem = &initiatorResource->initiatorMem; + iniMem->count = 1; /* Only 1 memory descriptors are used */ + + TI_DBG6(("itdssGetResource: start\n")); + + /* other than [0], nothing is used + * tdCachedMem[0]: cached mem for initiator TD Layer main functionality : + * itdssIni_t + * tdCachedMem[1-5]: is availalbe + */ + + /* + * Get default parameters from the OS Specific area + * and reads parameters from the configuration file + */ + itdssGetOperatingOptionParams(tiRoot, &OperatingOption); + + /* + * Cached mem for initiator Transport Dependent Layer main functionality + */ + + iniMem->tdCachedMem[0].singleElementLength = sizeof(itdsaIni_t); + iniMem->tdCachedMem[0].numElements = 1; + iniMem->tdCachedMem[0].totalLength = + iniMem->tdCachedMem[0].singleElementLength * + iniMem->tdCachedMem[0].numElements; + iniMem->tdCachedMem[0].alignment = sizeof (void *); /* 4 bytes */ + iniMem->tdCachedMem[0].type = TI_CACHED_MEM; + iniMem->tdCachedMem[0].reserved = 0; + iniMem->tdCachedMem[0].virtPtr = agNULL; + iniMem->tdCachedMem[0].osHandle = agNULL; + iniMem->tdCachedMem[0].physAddrUpper = 0; + iniMem->tdCachedMem[0].physAddrLower = 0; + + + /* + * Not used mem structure. Initialize them. + */ + for (i = iniMem->count; i < 6; i++) + { + iniMem->tdCachedMem[i].singleElementLength = 0; + iniMem->tdCachedMem[i].numElements = 0; + iniMem->tdCachedMem[i].totalLength = 0; + iniMem->tdCachedMem[i].alignment = 0; + iniMem->tdCachedMem[i].type = TI_CACHED_MEM; + iniMem->tdCachedMem[i].reserved = 0; + + iniMem->tdCachedMem[i].virtPtr = agNULL; + iniMem->tdCachedMem[i].osHandle = agNULL; + iniMem->tdCachedMem[i].physAddrUpper = 0; + iniMem->tdCachedMem[i].physAddrLower = 0; + + } + + /* + * Operating option of TISA + * fills in tiInitiatorOption + */ + initiatorResource->initiatorOption.usecsPerTick = OperatingOption.UsecsPerTick; /* default value 1 sec*/ + + initiatorResource->initiatorOption.pageSize = 0; + + /* initialization */ + initiatorResource->initiatorOption.dynamicDmaMem.numElements = 0; + initiatorResource->initiatorOption.dynamicDmaMem.singleElementLength = 0; + initiatorResource->initiatorOption.dynamicDmaMem.totalLength = 0; + initiatorResource->initiatorOption.dynamicDmaMem.alignment = 0; + + /* initialization */ + initiatorResource->initiatorOption.dynamicCachedMem.numElements = 0; + initiatorResource->initiatorOption.dynamicCachedMem.singleElementLength = 0; + initiatorResource->initiatorOption.dynamicCachedMem.totalLength = 0; + initiatorResource->initiatorOption.dynamicCachedMem.alignment = 0; + + + /* This is not used in OS like Linux which supports dynamic memeory allocation + In short, this is for Windows, which does not support dynamic memory allocation */ + /* ostiallocmemory(..... ,agFALSE) is supported by the following code eg) sat.c + The memory is DMA capable(uncached) + */ +#ifdef CCBUILD_EncryptionDriver + /* extend the DMA memory for supporting two encryption DEK tables */ + initiatorResource->initiatorOption.dynamicDmaMem.numElements = 128 + DEK_MAX_TABLE_ENTRIES / 2; +#else + initiatorResource->initiatorOption.dynamicDmaMem.numElements = 128; +#endif + /* worked + initiatorResource->initiatorOption.dynamicDmaMem.singleElementLength = sizeof(tdIORequestBody_t); + */ + initiatorResource->initiatorOption.dynamicDmaMem.singleElementLength = 512; + initiatorResource->initiatorOption.dynamicDmaMem.totalLength = + initiatorResource->initiatorOption.dynamicDmaMem.numElements * + initiatorResource->initiatorOption.dynamicDmaMem.singleElementLength; + initiatorResource->initiatorOption.dynamicDmaMem.alignment = sizeof(void *); + + + /* This is not used in OS like Linux which supports dynamic memeory allocation + In short, this is for Windows, which does not support dynamic memory allocation */ + /* ostiallocmemory(..... ,agTRUE) is supported by the following code eg) sat.c + The memory is DMA incapable(cached) + */ + initiatorResource->initiatorOption.dynamicCachedMem.numElements = 1024 + 256; + /* worked + initiatorResource->initiatorOption.dynamicCachedMem.singleElementLength = sizeof(tdIORequestBody_t); + initiatorResource->initiatorOption.dynamicCachedMem.singleElementLength = sizeof(tdssSMPRequestBody_t); + */ + initiatorResource->initiatorOption.dynamicCachedMem.singleElementLength = 512; + initiatorResource->initiatorOption.dynamicCachedMem.totalLength = + initiatorResource->initiatorOption.dynamicCachedMem.numElements * + initiatorResource->initiatorOption.dynamicCachedMem.singleElementLength; + initiatorResource->initiatorOption.dynamicCachedMem.alignment = sizeof(void *); + + /* + * set the I/O request body size + */ + initiatorResource->initiatorOption.ioRequestBodySize = sizeof(tdIORequestBody_t); + TI_DBG6(("itdssGetResource: sizeof(tdssSMPRequestBody_t) %d\n", (int)sizeof(tdssSMPRequestBody_t))); + TI_DBG6(("itdssGetResource: end\n")); + + return; +} + + +/***************************************************************************** +*! \brief itdssGetOperatingOptionParams +* +* Purpose: This function is called to get default parameters from the +* OS Specific area. This function is called in the context of +* tiCOMGetResource() and tiCOMInit(). +* +* +* \param tiRoot: Pointer to initiator driver/port instance. +* \param option: Pointer to the Transport Dependent options. +* +* \return: None +* +* \note - +* +*****************************************************************************/ +osGLOBAL void +itdssGetOperatingOptionParams( + tiRoot_t *tiRoot, + itdssOperatingOption_t *OperatingOption + ) +{ + char *key = agNULL; + char *subkey1 = agNULL; + char *subkey2 = agNULL; + char *buffer; + bit32 buffLen; + bit32 lenRecv = 0; + char *pLastUsedChar = agNULL; + char tmpBuffer[DEFAULT_KEY_BUFFER_SIZE]; + char globalStr[] = "Global"; + char iniParmsStr[] = "InitiatorParms"; + + TI_DBG6(("itdssGetOperatingOptionParams: start\n")); + + /* + first set the values to Default values + Then, overwrite them using ostiGetTransportParam() + */ + + + /* to remove compiler warnings */ + pLastUsedChar = pLastUsedChar; + lenRecv = lenRecv; + subkey2 = subkey2; + subkey1 = subkey1; + key = key; + buffer = &tmpBuffer[0]; + buffLen = sizeof (tmpBuffer); + + osti_memset(buffer, 0, buffLen); + + + + /* default values */ + OperatingOption->MaxTargets = DEFAULT_MAX_DEV; /* DEFAULT_MAX_TARGETS; */ /* 256 */ + OperatingOption->UsecsPerTick = DEFAULT_INI_TIMER_TICK; /* 1 sec */ + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + /* defaults are overwritten in the following */ + /* Get MaxTargets */ + if ((ostiGetTransportParam( + tiRoot, + globalStr, + iniParmsStr, + agNULL, + agNULL, + agNULL, + agNULL, + "MaxTargets", + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + OperatingOption->MaxTargets = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + OperatingOption->MaxTargets = osti_strtoul (buffer, &pLastUsedChar, 10); + } + TI_DBG2(("itdssGetOperatingOptionParams: MaxTargets %d\n", OperatingOption->MaxTargets )); + } + +#ifdef REMOVED + /* get UsecsPerTick */ + if ((ostiGetTransportParam( + tiRoot, + globalStr, + iniParmsStr, + agNULL, + agNULL, + agNULL, + agNULL, + "UsecsPerTick", + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + OperatingOption->UsecsPerTick = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + OperatingOption->UsecsPerTick = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + osti_memset(buffer, 0, buffLen); + lenRecv = 0; +#endif + + return; +} + + +/***************************************************************************** +*! \brief itdssInit +* +* Purpose: This function is called to initialize the initiator specific +* Transport Dependent Layer. +* This function is not directly called by OS Specific module, +* as it is internally called by tiCOMInit(). +* +* /param tiRoot: Pointer to driver/port instance. +* /param initiatorResource: Pointer to initiator functionality memory +* and option requirement. +* /param tdSharedMem: Pointer to cached memory required by the +* target/initiator shared functionality. +* +* /return: +* tiSuccess OK +* others not OK +* +* /note - +* +*****************************************************************************/ +osGLOBAL bit32 +itdssInit( + tiRoot_t *tiRoot, + tiInitiatorResource_t *initiatorResource, + tiTdSharedMem_t *tdSharedMem + ) +{ + tiInitiatorMem_t *iniMem; + itdsaIni_t *Initiator; + itdssOperatingOption_t *OperatingOption; + tdsaRoot_t *tdsaRoot; + + TI_DBG6(("itdssInit: start\n")); + iniMem = &initiatorResource->initiatorMem; + tdsaRoot = (tdsaRoot_t *)tiRoot->tdData; + /* + * Cached mem for initiator Transport Dependent Layer main functionality + */ + Initiator = iniMem->tdCachedMem[0].virtPtr; + + /* + * Get default parameters from the OS Specific area + */ + OperatingOption = &Initiator->OperatingOption; + + /* + * Get default parameters from the OS Specific area + * and reads parameters from the configuration file + */ + + itdssGetOperatingOptionParams(tiRoot, OperatingOption); + /* + * Update TD operating options with OS-layer-saved value + * Only UsecsPerTick is updated + */ + OperatingOption->UsecsPerTick = + initiatorResource->initiatorOption.usecsPerTick; + + Initiator->NumIOsActive = 0; + + /* + * tdCachedMem[0]: cached mem for initiator TD Layer main functionality : + * itdssIni_t + * tdCachedMem[1-5]: not in use + */ + + /* initialize the timerlist */ + itdssInitTimers(tiRoot); + + + /* Initialize the tdsaAllShared, tdssSASShared pointers */ + + Initiator->tdsaAllShared = &(tdsaRoot->tdsaAllShared); + + TI_DBG6(("itdssInit: end\n")); + return (tiSuccess); + +} + +/***************************************************************************** +*! \brief +* itdssInitTimers +* +* Purpose: This function is called to initialize the timers +* for initiator +* +* \param tiRoot: pointer to the driver instance +* +* \return: None +* +* \note - +* +*****************************************************************************/ +osGLOBAL void +itdssInitTimers( + tiRoot_t *tiRoot + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *)(tiRoot->tdData); + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + itdsaIni_t *Initiator = (itdsaIni_t *)tdsaAllShared->itdsaIni; + + /* initialize the timerlist */ + TDLIST_INIT_HDR(&(Initiator->timerlist)); + + return; +} diff --git a/sys/dev/pms/RefTisa/tisa/sassata/sas/ini/itdio.c b/sys/dev/pms/RefTisa/tisa/sassata/sas/ini/itdio.c new file mode 100644 index 000000000000..5147f8066888 --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/sas/ini/itdio.c @@ -0,0 +1,1899 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +/*******************************************************************************/ +/** \file + * + * + * This file contains initiator IO related functions in TD layer + * + */ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#ifdef FDS_SM +#include +#include +#include +#endif + +#ifdef FDS_DM +#include +#include +#include +#endif + +#include +#include +#include + +#ifdef INITIATOR_DRIVER +#include +#include +#include +#endif + +#ifdef TARGET_DRIVER +#include +#include +#include +#endif + +#include +#include + +/***************************************************************************** +*! \brief tiINIIOStart +* +* Purpose: This routine is called to initiate a new SCSI request. +* +* \param tiRoot: Pointer to initiator driver/port instance. +* \param tiIORequest: Pointer to the I/O request context for this I/O. +* \param tiDeviceHandle: Pointer to device handle for this I/O. +* \param tiScsiRequest: Pointer to the SCSI-3 I/O request and SGL list. +* \param tiRequestBody: Pointer to the OS Specific module allocated storage +* to be used by the TD layer for executing this I/O. +* \param interruptContext: The interrupt context within which this function +* is called. +* \return: +* +* tiSuccess: I/O request successfully initiated. +* tiBusy: No resources available, try again later. +* tiIONoDevice: Invalid device handle. +* tiError: Other errors that prevent the I/O request to be started. +* +* +*****************************************************************************/ +osGLOBAL bit32 +tiINIIOStart( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + void *tiRequestBody, + bit32 interruptContext + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + itdsaIni_t *Initiator = (itdsaIni_t *)tdsaAllShared->itdsaIni; + tdsaDeviceData_t *oneDeviceData; + agsaRoot_t *agRoot = agNULL; + agsaIORequest_t *agIORequest = agNULL; + agsaDevHandle_t *agDevHandle = agNULL; + bit32 agRequestType; + agsaSASRequestBody_t *agSASRequestBody = agNULL; + bit32 tiStatus = tiError; + bit32 saStatus = AGSA_RC_FAILURE; + + tdIORequestBody_t *tdIORequestBody; + agsaSSPInitiatorRequest_t *agSSPInitiatorRequest; +#ifdef REMOVED + /* only for debugging */ + bit32 i; +#endif + +#ifdef SATA_ENABLE +#ifndef FDS_SM + satIOContext_t *satIOContext; +#endif +#endif +#ifdef FDS_SM + smRoot_t *smRoot = &(tdsaAllShared->smRoot); + smIORequest_t *smIORequest; + smDeviceHandle_t *smDeviceHandle; + smScsiInitiatorRequest_t *smSCSIRequest; +#endif + + TDSA_INP_ENTER(tiRoot); + TI_DBG6(("tiINIIOStart: start\n")); + TI_DBG6(("tiINIIOStart:: ******* tdsaRoot %p tdsaAllShared %p \n", tdsaRoot,tdsaAllShared)); + + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + + TI_DBG6(("tiINIIOStart: onedevicedata %p\n", oneDeviceData)); + + if(oneDeviceData == agNULL) + { + TI_DBG1(("tiINIIOStart: tiDeviceHandle=%p DeviceData is NULL\n", tiDeviceHandle )); + tiStatus = tiIONoDevice; + goto ext; + } + + /* for hotplug */ + if (oneDeviceData->valid != agTRUE || oneDeviceData->registered != agTRUE || + oneDeviceData->tdPortContext == agNULL ) + { + TI_DBG1(("tiINIIOStart: tiDeviceHandle=%p did %d DeviceData was removed\n", tiDeviceHandle, oneDeviceData->id)); + TI_DBG6(("tiINIIOStart: device AddrHi 0x%08x AddrLo 0x%08x\n", + oneDeviceData->SASAddressID.sasAddressHi, oneDeviceData->SASAddressID.sasAddressLo)); + // for debugging + tdIORequestBody = (tdIORequestBody_t *)tiRequestBody; + tdIORequestBody->IOCompletionFunc = itdssIOForDebugging1Completed; + TI_DBG6(("tiINIIOStart: IOCompletionFunc %p\n", tdIORequestBody->IOCompletionFunc)); + tiStatus = tiIONoDevice; + goto ext; + } +#if 1 + if (tiIORequest->osData == agNULL) + { + TI_DBG1(("tiINIIOStart: tiIORequest->osData is NULL, wrong\n")); + } +#endif + + /* starting IO with SAS device */ + if (oneDeviceData->DeviceType == TD_SAS_DEVICE) + { + TI_DBG6(("tiINIIOStart: calling saSSPStart\n")); + + agRoot = oneDeviceData->agRoot; + agDevHandle = oneDeviceData->agDevHandle; + + /* OS layer has tdlayer data structure pointer in + tdIORequestBody_t tdIOReqBody; + in ccb_t in agtiapi.h + */ + tdIORequestBody = (tdIORequestBody_t *)tiRequestBody; + + /* initialize */ + osti_memset(tdIORequestBody, 0, sizeof(tdIORequestBody_t)); + + /* let's initialize tdIOrequestBody */ + /* initialize callback */ + tdIORequestBody->IOCompletionFunc = itdssIOCompleted; + + /* initialize tiDevhandle */ + tdIORequestBody->tiDevHandle = tiDeviceHandle; + + /* initialize tiIORequest */ + tdIORequestBody->tiIORequest = tiIORequest; + + /* save context if we need to abort later */ + tiIORequest->tdData = tdIORequestBody; + + /* initialize expDataLength */ + tdIORequestBody->IOType.InitiatorRegIO.expDataLength + = tiScsiRequest->scsiCmnd.expDataLength; + + tdIORequestBody->IOType.InitiatorRegIO.sglVirtualAddr + = tiScsiRequest->sglVirtualAddr; + + /* initializes "agsaSgl_t agSgl" of "agsaDifSSPInitiatorRequest_t" */ + tiStatus = itdssIOPrepareSGL( + tiRoot, + tdIORequestBody, + &tiScsiRequest->agSgl1, + tiScsiRequest->sglVirtualAddr + ); + + if (tiStatus != tiSuccess) + { + TI_DBG1(("tiINIIOStart: can't get SGL\n")); + goto ext; + } + + + /* initialize agIORequest */ + agIORequest = &(tdIORequestBody->agIORequest); + agIORequest->osData = (void *) tdIORequestBody; + agIORequest->sdkData = agNULL; /* LL takes care of this */ + + + /* + initialize + tdIORequestBody_t tdIORequestBody -> agSASRequestBody + */ + agSASRequestBody = &(tdIORequestBody->transport.SAS.agSASRequestBody); + agSSPInitiatorRequest = &(agSASRequestBody->sspInitiatorReq); + + agSSPInitiatorRequest->flag = 0; + + /* copy cdb bytes */ + osti_memcpy(agSSPInitiatorRequest->sspCmdIU.cdb, tiScsiRequest->scsiCmnd.cdb, 16); + + /* copy lun field */ + osti_memcpy(agSSPInitiatorRequest->sspCmdIU.lun, + tiScsiRequest->scsiCmnd.lun.lun, 8); + + + /* setting the data length */ + agSSPInitiatorRequest->dataLength = tiScsiRequest->scsiCmnd.expDataLength; + TI_DBG6(("tiINIIOStart: tiScsiRequest->scsiCmnd.expDataLength %d\n", tiScsiRequest->scsiCmnd.expDataLength)); + + agSSPInitiatorRequest->firstBurstSize = 0; + + /* + process taskattribute + */ + if (tiScsiRequest->scsiCmnd.taskAttribute == TASK_SIMPLE) + { + agSSPInitiatorRequest->sspCmdIU.efb_tp_taskAttribute = (bit8) + agSSPInitiatorRequest->sspCmdIU.efb_tp_taskAttribute | TD_TASK_SIMPLE; + } + else if (tiScsiRequest->scsiCmnd.taskAttribute == TASK_ORDERED) + { + agSSPInitiatorRequest->sspCmdIU.efb_tp_taskAttribute = (bit8) + agSSPInitiatorRequest->sspCmdIU.efb_tp_taskAttribute | TD_TASK_ORDERED; + } + else if (tiScsiRequest->scsiCmnd.taskAttribute == TASK_HEAD_OF_QUEUE) + { + agSSPInitiatorRequest->sspCmdIU.efb_tp_taskAttribute = (bit8) + agSSPInitiatorRequest->sspCmdIU.efb_tp_taskAttribute | TD_TASK_HEAD_OF_QUEUE; + } + else if (tiScsiRequest->scsiCmnd.taskAttribute == TASK_ACA) + { + agSSPInitiatorRequest->sspCmdIU.efb_tp_taskAttribute = (bit8) + agSSPInitiatorRequest->sspCmdIU.efb_tp_taskAttribute | TD_TASK_ACA; + } + + if (tiScsiRequest->dataDirection == tiDirectionIn) + { + agRequestType = AGSA_SSP_INIT_READ; + TI_DBG6(("tiINIIOStart: READ\n")); + } + else if (tiScsiRequest->dataDirection == tiDirectionOut) + { + agRequestType = AGSA_SSP_INIT_WRITE; + TI_DBG6(("tiINIIOStart: WRITE\n")); + } + else + { + agRequestType = AGSA_REQ_TYPE_UNKNOWN; + TI_DBG1(("tiINIIOStart: unknown data direction\n")); + } + + tdIORequestBody->agRequestType = agRequestType; + + TI_DBG6(("tiINIIOStart: device AddrHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG6(("tiINIIOStart: device AddrLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + + /* for debugging */ + if (tdIORequestBody->IOCompletionFunc == agNULL) + { + TI_DBG1(("tiINIIOStart: Error!!!! IOCompletionFunc is NULL\n")); + } + saStatus = saSSPStart(agRoot, + agIORequest, + tdsaRotateQnumber(tiRoot, oneDeviceData), + agDevHandle, + agRequestType, + agSASRequestBody, + agNULL, + &ossaSSPCompleted); + + tdIORequestBody->ioStarted = agTRUE; + tdIORequestBody->ioCompleted = agFALSE; + tdIORequestBody->reTries = 0; + + if (saStatus == AGSA_RC_SUCCESS) + { + Initiator->NumIOsActive++; + tiStatus = tiSuccess; + } + else + { + tdIORequestBody->ioStarted = agFALSE; + tdIORequestBody->ioCompleted = agTRUE; + if (saStatus == AGSA_RC_BUSY) + { + TI_DBG4(("tiINIIOStart: saSSPStart busy\n")); + tiStatus = tiBusy; + } + else + { + tiStatus = tiError; + } + goto ext; + } + } +#ifdef FDS_SM + else if (oneDeviceData->DeviceType == TD_SATA_DEVICE) + { + TI_DBG5(("tiINIIOStart: calling satIOStart\n")); + TI_DBG5(("tiINIIOStart: onedevicedata did %d\n", oneDeviceData->id)); + tdIORequestBody = (tdIORequestBody_t *)tiRequestBody; + /* initialize */ + osti_memset(tdIORequestBody, 0, sizeof(tdIORequestBody_t)); + /* initialize tiDevhandle */ + tdIORequestBody->tiDevHandle = tiDeviceHandle; + tdIORequestBody->superIOFlag = agFALSE; + + tiIORequest->tdData = tdIORequestBody; + tdIORequestBody->tiIORequest = tiIORequest; + smIORequest = (smIORequest_t *)&(tdIORequestBody->smIORequest); + smIORequest->tdData = tdIORequestBody; + + smDeviceHandle = (smDeviceHandle_t *)&(oneDeviceData->smDeviceHandle); + smDeviceHandle->tdData = oneDeviceData; + + smSCSIRequest = (smScsiInitiatorRequest_t *)&(tdIORequestBody->SM.smSCSIRequest); + osti_memcpy(smSCSIRequest, tiScsiRequest, sizeof(smScsiInitiatorRequest_t)); + + tiStatus = smIOStart(smRoot, + smIORequest, + smDeviceHandle, + smSCSIRequest, + interruptContext); + /* +osGLOBAL bit32 +smIOStart( + smRoot_t *smRoot, + smIORequest_t *smIORequest, + smDeviceHandle_t *smDeviceHandle, + smScsiInitiatorRequest_t *smSCSIRequest, + bit32 interruptContext + ) + + + */ + } +#else + else if (oneDeviceData->DeviceType == TD_SATA_DEVICE) + { + TI_DBG5(("tiINIIOStart: calling satIOStart\n")); + TI_DBG5(("tiINIIOStart: onedevicedata did %d\n", oneDeviceData->id)); + +#ifdef SATA_ENABLE + tdIORequestBody = (tdIORequestBody_t *)tiRequestBody; + + /* initialize */ + osti_memset(tdIORequestBody, 0, sizeof(tdIORequestBody_t)); + + /* initialize tiDevhandle */ + tdIORequestBody->tiDevHandle = tiDeviceHandle; + + /* initialize tiIORequest */ + tdIORequestBody->tiIORequest = tiIORequest; + tdIORequestBody->IOCompletionFunc = itdssIOForDebugging2Completed; + + satIOContext = &(tdIORequestBody->transport.SATA.satIOContext); + + /* + * Need to initialize all the fields within satIOContext except + * reqType and satCompleteCB which will be set in sat.c depending on cmd. + */ + tdIORequestBody->transport.SATA.tiSenseData.senseData = agNULL; + tdIORequestBody->transport.SATA.tiSenseData.senseLen = 0; + satIOContext->pSatDevData = &oneDeviceData->satDevData; + satIOContext->pFis = + &tdIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev; + satIOContext->pScsiCmnd = &tiScsiRequest->scsiCmnd; + satIOContext->pSense = &tdIORequestBody->transport.SATA.sensePayload; + satIOContext->pTiSenseData = &tdIORequestBody->transport.SATA.tiSenseData; + satIOContext->pTiSenseData->senseData = satIOContext->pSense; + /* satIOContext->pSense = (scsiRspSense_t *)satIOContext->pTiSenseData->senseData; */ + satIOContext->tiRequestBody = tiRequestBody; + satIOContext->interruptContext = interruptContext; + satIOContext->ptiDeviceHandle = tiDeviceHandle; + satIOContext->tiScsiXchg = tiScsiRequest; + satIOContext->satIntIoContext = agNULL; + satIOContext->satOrgIOContext = agNULL; + /* satIOContext->tiIORequest = tiIORequest; */ + + /* save context if we need to abort later */ + tiIORequest->tdData = tdIORequestBody; + + /* followings are used only for internal IO */ + satIOContext->currentLBA = 0; + satIOContext->OrgTL = 0; + + TI_DBG5(("tiINIIOStart: pSatDevData=%p\n", satIOContext->pSatDevData )); + + tiStatus = satIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + goto ext; +#endif + } +#endif /* else of FDS_SM */ + else + { + + tdIORequestBody = (tdIORequestBody_t *)tiRequestBody; + tdIORequestBody->IOCompletionFunc = itdssIOForDebugging3Completed; + TI_DBG1(("tiINIIOStart: wrong unspported Device %d\n", oneDeviceData->DeviceType)); + /* + error. unsupported IO + */ + } +ext: + TDSA_INP_LEAVE(tiRoot); + return tiStatus; +} + +#ifdef FAST_IO_TEST +osGLOBAL bit32 +tiINIFastIOSend(void *ioh) +{ + bit32 saStatus, tiStatus; + + saStatus = saFastSSPSend(ioh); + if (saStatus == AGSA_RC_SUCCESS) + tiStatus = tiSuccess; + else + tiStatus = tiError; + return tiStatus; +} + +osGLOBAL bit32 +tiINIFastIOCancel(void *ioh) +{ + bit32 saStatus, tiStatus; + + saStatus = saFastSSPCancel(ioh); + if (saStatus == AGSA_RC_SUCCESS) + tiStatus = tiSuccess; + else + tiStatus = tiError; + return tiStatus; +} + +osGLOBAL void* +tiINIFastIOPrepare( + tiRoot_t *tiRoot, + void *ioHandle, + agsaFastCommand_t *fc) +{ + tdsaDeviceData_t *oneDeviceData; + tiDeviceHandle_t *tiDeviceHandle = fc->devHandle; + bit32 taskAttribute = fc->taskAttribute; + void *ioh = ioHandle; + + TDSA_INP_ENTER(tiRoot); + TI_DBG6(("tiINIFastIOPrepare: enter\n")); + + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + if(oneDeviceData == agNULL) + { + TI_DBG1(("tiINIFastIOPrepare: tiDeviceHandle=%p DeviceData is NULL\n", + tiDeviceHandle)); + ioHandle = 0; + TD_ASSERT((0), ""); + goto ext; + } + TI_DBG6(("tiINIFastIOPrepare: onedevicedata %p\n", oneDeviceData)); + + /* starting IO with SAS device */ + if (oneDeviceData->DeviceType != TD_SAS_DEVICE) + { + TI_DBG1(("tiINISuperIOSend: wrong Device %d\n", oneDeviceData->DeviceType)); + /* error: unsupported IO */ + ioHandle = 0; + TD_ASSERT((0), ""); + goto ext; + } + + fc->agRoot = oneDeviceData->agRoot; + TD_ASSERT((NULL != fc->agRoot), ""); + + fc->devHandle = oneDeviceData->agDevHandle; + TD_ASSERT((NULL != fc->devHandle), ""); + fc->safb->oneDeviceData = oneDeviceData; + + /* + process taskattribute + */ + switch (taskAttribute) + { + case TASK_SIMPLE: + fc->taskAttribute = TD_TASK_SIMPLE; + break; + case TASK_ORDERED: + fc->taskAttribute = TD_TASK_ORDERED; + break; + case TASK_HEAD_OF_QUEUE: + fc->taskAttribute = TD_TASK_HEAD_OF_QUEUE; + break; + case TASK_ACA: + fc->taskAttribute = TD_TASK_ACA; + break; + /* compile out for "iniload" */ + } + + + TI_DBG3(("tiINIFastIOPrepare: data direction: %x\n", fc->agRequestType)); + TI_DBG6(("tiINIFastIOPrepare: device AddrHi/Lo 0x%08x / 0x%08x\n", + oneDeviceData->SASAddressID.sasAddressHi, + oneDeviceData->SASAddressID.sasAddressLo)); + + fc->queueNum = tdsaRotateQnumber(tiRoot, oneDeviceData); + + ioHandle = saFastSSPPrepare(ioHandle, fc, ossaFastSSPCompleted, fc->safb); + if (!ioHandle) + { + TI_DBG1(("tiINIFastIOPrepare: saSuperSSPSend error\n")); + TD_ASSERT((0), ""); + //goto ext; + } + +ext: + if (ioh && !ioHandle) + { + saFastSSPCancel(ioh); + } + + TI_DBG6(("tiINIFastIOPrepare: leave\n")); + + TDSA_INP_LEAVE(tiRoot); + return ioHandle; +} /* tiINIFastIOPrepare */ +#endif + +/***************************************************************************** +* +* tiINIIOStartDif +* +* Purpose: This routine is called to initiate a new SCSI request with +* DIF enable. +* +* Parameters: +* tiRoot: Pointer to initiator driver/port instance. +* tiIORequest: Pointer to the I/O request context for this I/O. +* tiDeviceHandle: Pointer to device handle for this I/O. +* tiScsiRequest: Pointer to the SCSI-3 I/O request and SGL list. +* tiRequestBody: Pointer to the OS Specific module allocated storage +* to be used by the TD layer for executing this I/O. +* interruptContext: The interrupt context within which this function +* is called. +* difOption: DIF option. +* +* Return: +* +* tiSuccess: I/O request successfully initiated. +* tiBusy: No resources available, try again later. +* tiIONoDevice: Invalid device handle. +* tiError: Other errors that prevent the I/O request to be started. +* +* +*****************************************************************************/ +osGLOBAL bit32 tiINIIOStartDif( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + void *tiRequestBody, + bit32 interruptContext, + tiDif_t *difOption + ) +{ + + /* This function was never used by SAS/SATA. Use tiINISuperIOStart() instead. */ + return tiBusy; +} + + +/***************************************************************************** +* +* tiINISuperIOStart +* +* Purpose: This routine is called to initiate a new SCSI request. +* +* Parameters: +* tiRoot: Pointer to initiator driver/port instance. +* tiIORequest: Pointer to the I/O request context for this I/O. +* tiDeviceHandle: Pointer to device handle for this I/O. +* tiScsiRequest: Pointer to the SCSI-3 I/O request and SGL list. +* tiRequestBody: Pointer to the OS Specific module allocated storage +* to be used by the TD layer for executing this I/O. +* interruptContext: The interrupt context within which this function +* is called. +* Return: +* +* tiSuccess: I/O request successfully initiated. +* tiBusy: No resources available, try again later. +* tiIONoDevice: Invalid device handle. +* tiError: Other errors that prevent the I/O request to be started. +* +* +*****************************************************************************/ +osGLOBAL bit32 +tiINISuperIOStart( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiSuperScsiInitiatorRequest_t *tiScsiRequest, + void *tiRequestBody, + bit32 interruptContext + ) +{ + tdsaRoot_t *tdsaRoot = agNULL; + tdsaContext_t *tdsaAllShared = agNULL; + itdsaIni_t *Initiator = agNULL; + tdsaDeviceData_t *oneDeviceData = agNULL; + tdIORequestBody_t *tdIORequestBody = agNULL; + agsaSSPInitiatorRequest_t *agSSPInitiatorRequest = agNULL; + agsaRoot_t *agRoot = agNULL; + agsaIORequest_t *agIORequest = agNULL; + agsaDevHandle_t *agDevHandle = agNULL; + agsaSASRequestBody_t *agSASRequestBody = agNULL; + bit32 tiStatus = tiError; + bit32 saStatus = AGSA_RC_FAILURE; + bit32 adjusted_length = 0; + bit32 agRequestType = 0; + agBOOLEAN needPlusDataLenAdjustment = agFALSE; + agBOOLEAN needMinusDataLenAdjustment = agFALSE; + +#ifdef SATA_ENABLE +#ifndef FDS_SM + satIOContext_t *satIOContext; +#endif +#endif +#ifdef FDS_SM + smRoot_t *smRoot; + smIORequest_t *smIORequest; + smDeviceHandle_t *smDeviceHandle; + smSuperScsiInitiatorRequest_t *smSuperSCSIRequest; +#endif +#ifdef CCBUILD_INDIRECT_CDB + agsaSSPInitiatorRequestIndirect_t *agSSPInitiatorIndRequest = agNULL; +#endif + TD_ASSERT(tiRoot , "tiRoot"); + TD_ASSERT(tiIORequest, "tiIORequest"); + TD_ASSERT(tiDeviceHandle, "tiDeviceHandle"); + TD_ASSERT(tiRequestBody, "tiRequestBody"); + TD_ASSERT(tiRoot->tdData, "tiRoot->tdData"); + TD_ASSERT(tiDeviceHandle, "tiDeviceHandle"); + + tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + TD_ASSERT(tdsaRoot, "tdsaRoot"); + + tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + TD_ASSERT(tdsaAllShared, "tdsaAllShared"); + + Initiator = (itdsaIni_t *)tdsaAllShared->itdsaIni; + TD_ASSERT(Initiator, "Initiator"); + + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + TD_ASSERT(oneDeviceData, "oneDeviceData"); + + +#ifdef FDS_SM + smRoot = &(tdsaAllShared->smRoot); + TD_ASSERT(smRoot , "smRoot"); +#endif + + + TI_DBG6(("tiINISuperIOStart: start\n")); + TI_DBG6(("tiINISuperIOStart:: ******* tdsaRoot %p tdsaAllShared %p \n", tdsaRoot,tdsaAllShared)); + + TI_DBG6(("tiINISuperIOStart: onedevicedata %p\n", oneDeviceData)); + + if (oneDeviceData == agNULL) + { + TI_DBG1(("tiINISuperIOStart: tiDeviceHandle=%p DeviceData is NULL\n", tiDeviceHandle )); + return tiIONoDevice; + } + + /* for hotplug */ + if (oneDeviceData->valid != agTRUE || oneDeviceData->registered != agTRUE || + oneDeviceData->tdPortContext == agNULL ) + { + TI_DBG1(("tiINISuperIOStart: tiDeviceHandle=%p did %d DeviceData was removed\n", tiDeviceHandle, oneDeviceData->id)); + TI_DBG6(("tiINISuperIOStart: device AddrHi 0x%08x AddrLo 0x%08x\n", + oneDeviceData->SASAddressID.sasAddressHi, oneDeviceData->SASAddressID.sasAddressLo)); + // for debugging + tdIORequestBody = (tdIORequestBody_t *)tiRequestBody; + tdIORequestBody->IOCompletionFunc = itdssIOForDebugging1Completed; + TI_DBG6(("tiINISuperIOStart: IOCompletionFunc %p\n", tdIORequestBody->IOCompletionFunc)); + return tiIONoDevice; + } + +#ifdef DBG + if (tiIORequest->osData == agNULL) + { + TI_DBG1(("tiINISuperIOStart: tiIORequest->osData is NULL, wrong\n")); + return tiError; + } +#endif + /* starting IO with SAS device */ + if (oneDeviceData->DeviceType == TD_SAS_DEVICE) + { + TI_DBG3(("tiINISuperIOStart: calling saSSPStart\n")); + + agRoot = oneDeviceData->agRoot; + agDevHandle = oneDeviceData->agDevHandle; + + /* OS layer has tdlayer data structure pointer in tdIORequestBody_t tdIOReqBody; in ccb_t in agtiapi.h */ + tdIORequestBody = (tdIORequestBody_t *)tiRequestBody; + + /* initialize */ + /*the tdIORequestBody has been initialized in HwBuildIo routine */ + /*osti_memset(tdIORequestBody, 0, sizeof(tdIORequestBody_t));*/ + + /* let's initialize tdIOrequestBody */ + /* initialize callback */ + tdIORequestBody->IOCompletionFunc = itdssIOCompleted; + + /* initialize tiDevhandle */ + tdIORequestBody->tiDevHandle = tiDeviceHandle; + + /* initialize tiIORequest */ + tdIORequestBody->tiIORequest = tiIORequest; + + /* save context if we need to abort later */ + tiIORequest->tdData = tdIORequestBody; + + /* initialize expDataLength */ + tdIORequestBody->IOType.InitiatorRegIO.expDataLength + = tiScsiRequest->scsiCmnd.expDataLength; + + tdIORequestBody->IOType.InitiatorRegIO.sglVirtualAddr + = tiScsiRequest->sglVirtualAddr; + + /* initialize agIORequest */ + agIORequest = &(tdIORequestBody->agIORequest); + agIORequest->osData = (void *) tdIORequestBody; + + /* initialize tdIORequestBody_t tdIORequestBody -> agSASRequestBody */ + agSASRequestBody = &(tdIORequestBody->transport.SAS.agSASRequestBody); + agSSPInitiatorRequest = &(agSASRequestBody->sspInitiatorReq); + + agSSPInitiatorRequest->flag = 0; + if (tiScsiRequest->flags & TI_SCSI_INITIATOR_ENCRYPT) + { + TI_DBG3(("tiINISuperIOStart: TI_SCSI_INITIATOR_ENCRYPT\n")); + + /* Copy all of the relevant encrypt information */ + agSSPInitiatorRequest->flag |= AGSA_SAS_ENABLE_ENCRYPTION; + TD_ASSERT( sizeof(tiEncrypt_t) == sizeof(agsaEncrypt_t) , "sizeof(tiEncrypt_t) == sizeof(agsaEncrypt_t)"); + osti_memcpy(&agSSPInitiatorRequest->encrypt, &tiScsiRequest->Encrypt, sizeof(agsaEncrypt_t)); + } + + if ((tiScsiRequest->flags & TI_SCSI_INITIATOR_DIF) && + (tiScsiRequest->scsiCmnd.cdb[0] == SCSIOPC_READ_10 || + tiScsiRequest->scsiCmnd.cdb[0] == SCSIOPC_WRITE_10 || + tiScsiRequest->scsiCmnd.cdb[0] == SCSIOPC_WRITE_6 || + tiScsiRequest->scsiCmnd.cdb[0] == SCSIOPC_READ_6 || + tiScsiRequest->scsiCmnd.cdb[0] == SCSIOPC_READ_12 || + tiScsiRequest->scsiCmnd.cdb[0] == SCSIOPC_WRITE_12 || + tiScsiRequest->scsiCmnd.cdb[0] == SCSIOPC_WRITE_16 || + tiScsiRequest->scsiCmnd.cdb[0] == SCSIOPC_READ_16 )) + { + TI_DBG3(("tiINISuperIOStart: TI_SCSI_INITIATOR_DIF\n")); + /* Copy all of the relevant DIF information */ + agSSPInitiatorRequest->flag |= AGSA_SAS_ENABLE_DIF; + osti_memcpy(&agSSPInitiatorRequest->dif, &tiScsiRequest->Dif, sizeof(agsaDif_t)); + + /* Check if need to adjust dataLength. */ + switch (tiScsiRequest->dataDirection) + { + case tiDirectionOut: /* Write/Outbound */ + break; + + case tiDirectionIn: /* Read/Inbound */ + if ((agSSPInitiatorRequest->dif.flags & DIF_ACTION_FLAG_MASK) == DIF_INSERT) + { + needPlusDataLenAdjustment = agTRUE; + } + break; + } + + /* Set SGL data len XXX This code needs to support more sector sizes */ + /* Length adjustment for PCIe DMA only not SAS */ + if (needPlusDataLenAdjustment == agTRUE) + { + adjusted_length = tiScsiRequest->scsiCmnd.expDataLength; + adjusted_length += (adjusted_length/512) * 8; + agSSPInitiatorRequest->dataLength = adjusted_length; + } + else if (needMinusDataLenAdjustment == agTRUE) + { + adjusted_length = tiScsiRequest->scsiCmnd.expDataLength; + adjusted_length -= (adjusted_length/520) * 8; + agSSPInitiatorRequest->dataLength = adjusted_length; + } + else + { + /* setting the data length */ + agSSPInitiatorRequest->dataLength = tiScsiRequest->scsiCmnd.expDataLength; + } + + /* initializes "agsaSgl_t agSgl" of "agsaDifSSPInitiatorRequest_t" */ + tiStatus = itdssIOPrepareSGL( + tiRoot, + tdIORequestBody, + &tiScsiRequest->agSgl1, + tiScsiRequest->sglVirtualAddr + ); + TI_DBG2(("tiINISuperIOStart:TI_SCSI_INITIATOR_DIF needMinusDataLenAdjustment %d needPlusDataLenAdjustment %d difAction %X\n", + needMinusDataLenAdjustment, + needPlusDataLenAdjustment, + agSSPInitiatorRequest->dif.flags & DIF_ACTION_FLAG_MASK)); + + } + else + { + /* setting the data length */ + agSSPInitiatorRequest->dataLength = tiScsiRequest->scsiCmnd.expDataLength; + + /* initializes "agsaSgl_t agSgl" of "agsaSSPInitiatorRequest_t" */ + tiStatus = itdssIOPrepareSGL( + tiRoot, + tdIORequestBody, + &tiScsiRequest->agSgl1, + tiScsiRequest->sglVirtualAddr + ); + } + + if (tiStatus != tiSuccess) + { + TI_DBG1(("tiINISuperIOStart: can't get SGL\n")); + return tiStatus; + } + + TI_DBG6(("tiINISuperIOStart: tiScsiRequest->scsiCmnd.expDataLength %d\n", tiScsiRequest->scsiCmnd.expDataLength)); + + /* process taskattribute */ + if (tiScsiRequest->scsiCmnd.taskAttribute == TASK_SIMPLE) + { + agSSPInitiatorRequest->sspCmdIU.efb_tp_taskAttribute = (bit8) + agSSPInitiatorRequest->sspCmdIU.efb_tp_taskAttribute | TD_TASK_SIMPLE; + } + else if (tiScsiRequest->scsiCmnd.taskAttribute == TASK_ORDERED) + { + agSSPInitiatorRequest->sspCmdIU.efb_tp_taskAttribute = (bit8) + agSSPInitiatorRequest->sspCmdIU.efb_tp_taskAttribute | TD_TASK_ORDERED; + } + else if (tiScsiRequest->scsiCmnd.taskAttribute == TASK_HEAD_OF_QUEUE) + { + agSSPInitiatorRequest->sspCmdIU.efb_tp_taskAttribute = (bit8) + agSSPInitiatorRequest->sspCmdIU.efb_tp_taskAttribute | TD_TASK_HEAD_OF_QUEUE; + } + else if (tiScsiRequest->scsiCmnd.taskAttribute == TASK_ACA) + { + agSSPInitiatorRequest->sspCmdIU.efb_tp_taskAttribute = (bit8) + agSSPInitiatorRequest->sspCmdIU.efb_tp_taskAttribute | TD_TASK_ACA; + } + + /* copy cdb bytes */ + osti_memcpy(agSSPInitiatorRequest->sspCmdIU.cdb, tiScsiRequest->scsiCmnd.cdb, 16); + /* copy lun field */ + osti_memcpy(agSSPInitiatorRequest->sspCmdIU.lun, tiScsiRequest->scsiCmnd.lun.lun, 8); +#ifdef CCBUILD_INDIRECT_CDB + /* check the Indirect CDB flag */ + if (tiScsiRequest->flags & TI_SCSI_INITIATOR_INDIRECT_CDB) + { + /* Indirect CDB */ + if (tiScsiRequest->dataDirection == tiDirectionIn) + { + agRequestType = AGSA_SSP_INIT_READ_INDIRECT; + TI_DBG6(("tiINISuperIOStart: Indirect READ\n")); + } + else if (tiScsiRequest->dataDirection == tiDirectionOut) + { + agRequestType = AGSA_SSP_INIT_WRITE_INDIRECT; + TI_DBG6(("tiINISuperIOStart: Indirect WRITE\n")); + } + else + { + agRequestType = AGSA_REQ_TYPE_UNKNOWN; + TI_DBG1(("tiINISuperIOStart: unknown data direction\n")); + } + agSSPInitiatorIndRequest = &(agSASRequestBody->sspInitiatorReqIndirect); + /* copy the constructed SSPIU info to indirect SSPIU buffer */ + osti_memcpy(tiScsiRequest->IndCDBBuffer, &agSSPInitiatorRequest->sspCmdIU, sizeof(agsaSSPCmdInfoUnit_t)); + /* initialize the indirect CDB buffer address and length */ + agSSPInitiatorIndRequest->sspInitiatorReqAddrLower32 = tiScsiRequest->IndCDBLowAddr; + agSSPInitiatorIndRequest->sspInitiatorReqAddrUpper32 = tiScsiRequest->IndCDBHighAddr; + agSSPInitiatorIndRequest->sspInitiatorReqLen = sizeof(agsaSSPCmdInfoUnit_t); + } + else +#endif //CCBUILD_INDIRECT_CDB + { + /* Direct CDB */ + if (tiScsiRequest->dataDirection == tiDirectionIn) + { + agRequestType = AGSA_SSP_INIT_READ; + TI_DBG6(("tiINISuperIOStart: READ\n")); + } + else if (tiScsiRequest->dataDirection == tiDirectionOut) + { + agRequestType = AGSA_SSP_INIT_WRITE; + TI_DBG6(("tiINISuperIOStart: WRITE\n")); + } + else + { + agRequestType = AGSA_REQ_TYPE_UNKNOWN; + TI_DBG1(("tiINISuperIOStart: unknown data direction\n")); + } + } + + tdIORequestBody->agRequestType = agRequestType; + + TI_DBG6(("tiINISuperIOStart: device AddrHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG6(("tiINISuperIOStart: device AddrLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + +#ifdef DBG + /* for debugging */ + if (tdIORequestBody->IOCompletionFunc == agNULL) + { + TI_DBG1(("tiINISuperIOStart: Error!!!! IOCompletionFunc is NULL\n")); + return tiError; + } +#endif + saStatus = saSSPStart(agRoot, + agIORequest, + tdsaRotateQnumber(tiRoot, oneDeviceData), + agDevHandle, + agRequestType, + agSASRequestBody, + agNULL, + &ossaSSPCompleted); + + if (saStatus == AGSA_RC_SUCCESS) + { + Initiator->NumIOsActive++; + tdIORequestBody->ioStarted = agTRUE; + tdIORequestBody->ioCompleted = agFALSE; + tiStatus = tiSuccess; + } + else + { + tdIORequestBody->ioStarted = agFALSE; + tdIORequestBody->ioCompleted = agTRUE; + if (saStatus == AGSA_RC_BUSY) + { + TI_DBG4(("tiINISuperIOStart: saSSPStart busy\n")); + tiStatus = tiBusy; + } + else + { + tiStatus = tiError; + } + return tiStatus; + } + } +#ifdef FDS_SM + else if (oneDeviceData->DeviceType == TD_SATA_DEVICE) + { + TI_DBG5(("tiINISuperIOStart: calling satIOStart\n")); + TI_DBG5(("tiINISuperIOStart: onedevicedata did %d\n", oneDeviceData->id)); + TI_DBG5(("tiINISuperIOStart: SATA sasAddressHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG5(("tiINISuperIOStart: SATA sasAddressLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + + tdIORequestBody = (tdIORequestBody_t *)tiRequestBody; + /* initialize */ + /* the tdIORequestBody has been initialized by Storport in SRB Extension */ + /*osti_memset(tdIORequestBody, 0, sizeof(tdIORequestBody_t));*/ + /* initialize tiDevhandle */ + tdIORequestBody->tiDevHandle = tiDeviceHandle; + tdIORequestBody->superIOFlag = agTRUE; + + tiIORequest->tdData = tdIORequestBody; + tdIORequestBody->tiIORequest = tiIORequest; + smIORequest = (smIORequest_t *)&(tdIORequestBody->smIORequest); + smIORequest->tdData = tdIORequestBody; + smIORequest->smData = &tdIORequestBody->smIORequestBody; + + smDeviceHandle = (smDeviceHandle_t *)&(oneDeviceData->smDeviceHandle); + smDeviceHandle->tdData = oneDeviceData; + + smSuperSCSIRequest = (smSuperScsiInitiatorRequest_t *)&(tdIORequestBody->SM.smSuperSCSIRequest); + osti_memcpy(smSuperSCSIRequest, tiScsiRequest, sizeof(smSuperScsiInitiatorRequest_t)); + + tiStatus = smSuperIOStart(smRoot, + smIORequest, + smDeviceHandle, + smSuperSCSIRequest, + oneDeviceData->SASAddressID.sasAddressHi, + oneDeviceData->SASAddressID.sasAddressLo, + interruptContext); + + } +#else + else if (oneDeviceData->DeviceType == TD_SATA_DEVICE) + { + + TI_DBG5(("tiINISuperIOStart: calling satIOStart\n")); + TI_DBG5(("tiINISuperIOStart: onedevicedata did %d\n", oneDeviceData->id)); + +#ifdef SATA_ENABLE + tdIORequestBody = (tdIORequestBody_t *)tiRequestBody; + + /* initialize */ + osti_memset(tdIORequestBody, 0, sizeof(tdIORequestBody_t)); + + /* initialize tiDevhandle */ + tdIORequestBody->tiDevHandle = tiDeviceHandle; + + /* initialize tiIORequest */ + tdIORequestBody->tiIORequest = tiIORequest; + tdIORequestBody->IOCompletionFunc = itdssIOForDebugging2Completed; + + satIOContext = &(tdIORequestBody->transport.SATA.satIOContext); + + /* + * Need to initialize all the fields within satIOContext except + * reqType and satCompleteCB which will be set in sat.c depending on cmd. + */ + tdIORequestBody->transport.SATA.tiSenseData.senseData = agNULL; + tdIORequestBody->transport.SATA.tiSenseData.senseLen = 0; + satIOContext->pSatDevData = &oneDeviceData->satDevData; + satIOContext->pFis = + &tdIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev; + satIOContext->pScsiCmnd = &tiScsiRequest->scsiCmnd; + satIOContext->pSense = &tdIORequestBody->transport.SATA.sensePayload; + satIOContext->pTiSenseData = &tdIORequestBody->transport.SATA.tiSenseData; + satIOContext->pTiSenseData->senseData = satIOContext->pSense; + /* satIOContext->pSense = (scsiRspSense_t *)satIOContext->pTiSenseData->senseData; */ + satIOContext->tiRequestBody = tiRequestBody; + satIOContext->interruptContext = interruptContext; + satIOContext->ptiDeviceHandle = tiDeviceHandle; + /* + This code uses a kludge for the tiScsiXchg. Many subroutines in the SATA code + require a tiScsiInitiatorRequest. Since it would be a lot of work to replicate + those functions for a tiSuperScsiInitiatorRequest, we will use a short cut. + The standard pointer will be passed, but the superIOFlag marks the real type of the structure. + */ + satIOContext->tiScsiXchg = tiScsiRequest; + satIOContext->superIOFlag = agTRUE; + + satIOContext->satIntIoContext = agNULL; + satIOContext->satOrgIOContext = agNULL; + /* satIOContext->tiIORequest = tiIORequest; */ + + /* save context if we need to abort later */ + tiIORequest->tdData = tdIORequestBody; + + /* followings are used only for internal IO */ + satIOContext->currentLBA = 0; + satIOContext->OrgTL = 0; + + TI_DBG5(("tiINISuperIOStart: pSatDevData=%p\n", satIOContext->pSatDevData )); + + tiStatus = satIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + satIOContext->tiScsiXchg, + satIOContext); + + return tiStatus; +#endif + } +#endif /* else of FDS_SM */ + + else + { + + tdIORequestBody = (tdIORequestBody_t *)tiRequestBody; + tdIORequestBody->IOCompletionFunc = itdssIOForDebugging3Completed; + TI_DBG1(("tiINISuperIOStart: wrong unspported Device %d\n", oneDeviceData->DeviceType)); + /* + error. unsupported IO + */ + } + return tiStatus; +} + +osGLOBAL bit32 +tiINISMPStart( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiSMPFrame_t *tiSMPFrame, + void *tiSMPBody, + bit32 interruptContext + ) +{ + tdsaDeviceData_t *oneDeviceData; + agsaIORequest_t *agIORequest = agNULL; + tdIORequestBody_t *tdSMPRequestBody = agNULL; + agsaRoot_t *agRoot = agNULL; + agsaDevHandle_t *agDevHandle = agNULL; + agsaSASRequestBody_t *agRequestBody = agNULL; + agsaSMPFrame_t *agSMPFrame = agNULL; + bit32 agRequestType; + bit32 tiStatus = tiError; + bit32 saStatus = AGSA_RC_FAILURE; + bit32 queueNum; + TDSA_INP_ENTER(tiRoot); + TI_DBG6(("tiINISMPStart: start\n")); + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + TI_DBG6(("tiINISMPStart: onedevicedata %p\n", oneDeviceData)); + TI_DBG6(("tiINISMPStart: tiDeviceHandle %p\n", tiDeviceHandle)); + if (oneDeviceData == agNULL) + { + TI_DBG1(("tiINISMPStart: tiDeviceHandle=%p Expander DeviceData is NULL\n", tiDeviceHandle )); + return tiError; + } + if (tiIORequest->osData == agNULL) + { + TI_DBG1(("tiINISMPStart: tiIORequest->osData is NULL, wrong\n")); + return tiError; + } + agRoot = oneDeviceData->agRoot; + agDevHandle = oneDeviceData->agDevHandle; + tdSMPRequestBody = (tdIORequestBody_t *)tiSMPBody; + tdSMPRequestBody->tiIORequest = tiIORequest; + tiIORequest->tdData = tdSMPRequestBody; + agIORequest = &(tdSMPRequestBody->agIORequest); + agIORequest->osData = (void *) tdSMPRequestBody; + agRequestBody = &(tdSMPRequestBody->transport.SAS.agSASRequestBody); + agSMPFrame = &(agRequestBody->smpFrame); + if (!DEVICE_IS_SMP_TARGET(oneDeviceData)) + { + TI_DBG1(("tiINISMPStart: Target Device is not SMP device\n")); + return tiError; + } + if (tiSMPFrame->flag == 0) // define DIRECT SMP at td layer? + { + TI_DBG6(("tiINISMPStart: Direct SMP\n")); + agSMPFrame->outFrameBuf = tiSMPFrame->outFrameBuf; + agSMPFrame->outFrameLen = tiSMPFrame->outFrameLen; + tdhexdump("tiINISMPStart agSMPFrame", (bit8 *)agSMPFrame->outFrameBuf, agSMPFrame->outFrameLen); + agSMPFrame->expectedRespLen = tiSMPFrame->expectedRespLen; + agSMPFrame->inFrameLen = 0; + agSMPFrame->flag = tiSMPFrame->flag; + agRequestType = AGSA_SMP_INIT_REQ; + queueNum = 0; + saStatus = saSMPStart(agRoot, + agIORequest, + queueNum, + agDevHandle, + agRequestType, + agRequestBody, + &ossaSMPCAMCompleted + ); + if (saStatus == AGSA_RC_SUCCESS) + { + tiStatus = tiSuccess; + } + else + { + if (saStatus == AGSA_RC_BUSY) + { + TI_DBG1(("tiINISMPStart: saSSPStart busy\n")); + tiStatus = tiBusy; + } + else + { + TI_DBG1(("tiINISMPStart: saSSPStart error\n")); + tiStatus = tiError; + } + return tiStatus; + } + } + else + { + TI_DBG1(("tiINISMPStart: Indirect SMP! Not supported yet\n")); + tiStatus = tiError; + } + return tiStatus; +} +#ifdef TD_INT_COALESCE +osGLOBAL bit32 +tiINIIOStartIntCoalesce( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + void *tiRequestBody, + bit32 interruptContext, + tiIntCoalesceContext_t *tiIntCoalesceCxt + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + itdsaIni_t *Initiator = (itdsaIni_t *)tdsaAllShared->itdsaIni; + tdsaDeviceData_t *oneDeviceData; + agsaRoot_t *agRoot = agNULL; + agsaIORequest_t *agIORequest = agNULL; + agsaDevHandle_t *agDevHandle = agNULL; + bit32 agRequestType; + agsaSASRequestBody_t *agSASRequestBody = agNULL; + bit32 tiStatus = tiError; + bit32 saStatus = AGSA_RC_FAILURE; + + tdIORequestBody_t *tdIORequestBody; + agsaSSPInitiatorRequest_t *agSSPInitiatorRequest; + tdsaIntCoalesceContext_t *tdsaIntCoalCxt; + agsaIntCoalesceContext_t *agIntCoalCxt; + + TI_DBG1(("tiINIIOStartIntCoalesce: start\n")); + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + + TI_DBG6(("tiINIIOStartIntCoalesce: onedevicedata %p\n", oneDeviceData)); + + if(oneDeviceData == agNULL) + { + TI_DBG1(("tiINIIOStartIntCoalesce: tiDeviceHandle=%p DeviceData is NULL\n", tiDeviceHandle )); + return tiIONoDevice; + } + + /* starting IO with SAS device */ + if (oneDeviceData->DeviceType == TD_SAS_DEVICE) + { + TI_DBG6(("tiINIIOStartIntCoalesce: calling saSSPStart\n")); + + agRoot = oneDeviceData->agRoot; + agDevHandle = oneDeviceData->agDevHandle; + + /* OS layer has tdlayer data structure pointer in + tdIORequestBody_t tdIOReqBody; + in ccb_t in agtiapi.h + */ + tdIORequestBody = (tdIORequestBody_t *)tiRequestBody; + + /* let's initialize tdIOrequestBody */ + /* initialize callback */ + tdIORequestBody->IOCompletionFunc = itdssIOCompleted; + + /* initialize tiDevhandle */ + tdIORequestBody->tiDevHandle = tiDeviceHandle; + + /* initialize tiIORequest */ + tdIORequestBody->tiIORequest = tiIORequest; + + /* save context if we need to abort later */ + tiIORequest->tdData = tdIORequestBody; + + /* initialize expDataLength */ + tdIORequestBody->IOType.InitiatorRegIO.expDataLength + = tiScsiRequest->scsiCmnd.expDataLength; + + /* initializes "agsaSgl_t agSgl" of "agsaDifSSPInitiatorRequest_t" */ + tiStatus = itdssIOPrepareSGL( + tiRoot, + tdIORequestBody, + &tiScsiRequest->agSgl1, + tiScsiRequest->sglVirtualAddr + ); + + if (tiStatus != tiSuccess) + { + TI_DBG1(("tiINIIOStartIntCoalesce: can't get SGL\n")); + return tiStatus; + } + + + /* initialize agIORequest */ + agIORequest = &(tdIORequestBody->agIORequest); + agIORequest->osData = (void *) tdIORequestBody; + agIORequest->sdkData = agNULL; /* LL takes care of this */ + + + /* + initialize + tdIORequestBody_t tdIORequestBody -> agSASRequestBody + */ + agSASRequestBody = &(tdIORequestBody->transport.SAS.agSASRequestBody); + agSSPInitiatorRequest = &(agSASRequestBody->sspInitiatorReq); + + + /* copy cdb bytes */ + osti_memcpy(agSSPInitiatorRequest->sspCmdIU.cdb, tiScsiRequest->scsiCmnd.cdb, 16); + + /* copy lun field */ + osti_memcpy(agSSPInitiatorRequest->sspCmdIU.lun, + tiScsiRequest->scsiCmnd.lun.lun, 8); + + /* setting the data length */ + agSSPInitiatorRequest->dataLength = tiScsiRequest->scsiCmnd.expDataLength; + TI_DBG6(("tiINIIOStartIntCoalesce: tiScsiRequest->scsiCmnd.expDataLength %d\n", tiScsiRequest->scsiCmnd.expDataLength)); + + agSSPInitiatorRequest->firstBurstSize = 0; + + if (tiScsiRequest->dataDirection == tiDirectionIn) + { + agRequestType = AGSA_SSP_INIT_READ; + TI_DBG6(("tiINIIOStartIntCoalesce: READ\n")); + } + else if (tiScsiRequest->dataDirection == tiDirectionOut) + { + agRequestType = AGSA_SSP_INIT_WRITE; + TI_DBG6(("tiINIIOStartIntCoalesce: WRITE\n")); + } + else + { + agRequestType = AGSA_REQ_TYPE_UNKNOWN; + TI_DBG1(("tiINIIOStartIntCoalesce: unknown data direction\n")); + } + + tdIORequestBody->agRequestType = agRequestType; + + tdsaIntCoalCxt = (tdsaIntCoalesceContext_t *)tiIntCoalesceCxt->tdData; + agIntCoalCxt = &(tdsaIntCoalCxt->agIntCoalCxt); + + + +#ifdef LL_INT_COALESCE + saStatus = saSSPStartIntCoalesce(agRoot, + agIORequest, + agIntCoalCxt, + agDevHandle, + agRequestType, + agSASRequestBody, + &ossaSSPCompleted); +#endif + + tdIORequestBody->ioStarted = agTRUE; + tdIORequestBody->ioCompleted = agFALSE; + + if (saStatus == AGSA_RC_SUCCESS) + { + Initiator->NumIOsActive++; + tiStatus = tiSuccess; + } + else + { + TI_DBG1(("tiINIIOStartIntCoalesce: saSSPStart failed\n")); + tdIORequestBody->ioStarted = agFALSE; + tdIORequestBody->ioCompleted = agTRUE; + if (saStatus == AGSA_RC_BUSY) + { + tiStatus = tiBusy; + } + else + { + tiStatus = tiError; + } + return tiStatus; + } + } + + else if (oneDeviceData->DeviceType == TD_SATA_DEVICE) + { + /* + satIOStart() -> saSATAStartIntCoalesce() + */ + TI_DBG1(("tiINIIOStartIntCoalesce: SATA not supported yet\n")); + return tiStatus; + } + else + { + TI_DBG1(("tiINIIOStartIntCoalesce: wrong unspported Device %d\n", oneDeviceData->DeviceType)); + /* + error. unsupported IO + */ + } + return tiStatus; + + +} + +osGLOBAL bit32 +tiINIIOStartIntCoalesceDif( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + void *tiRequestBody, + bit32 interruptContext, + tiIntCoalesceContext_t *tiIntCoalesceCxt, + tiDif_t *difOption + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + itdsaIni_t *Initiator = (itdsaIni_t *)tdsaAllShared->itdsaIni; + tdsaDeviceData_t *oneDeviceData; + agsaRoot_t *agRoot = agNULL; + agsaIORequest_t *agIORequest = agNULL; + agsaDevHandle_t *agDevHandle = agNULL; + bit32 agRequestType; + agsaDifSSPRequestBody_t *agEdcSSPRequestBody = agNULL; + bit32 tiStatus = tiError; + bit32 saStatus = AGSA_RC_FAILURE; + + tdIORequestBody_t *tdIORequestBody; + agsaDifSSPInitiatorRequest_t *agEdcSSPInitiatorRequest; + agsaDif_t *agEdc; + bit32 agUpdateMask = 0; + bit32 agVerifyMask = 0; + tdsaIntCoalesceContext_t *tdsaIntCoalCxt; + agsaIntCoalesceContext_t *agIntCoalCxt; + + TI_DBG1(("tiINIIOStartIntCoalesceDif: start\n")); + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + + TI_DBG6(("tiINIIOStartIntCoalesceDif: onedevicedata %p\n", oneDeviceData)); + + if(oneDeviceData == agNULL) + { + TI_DBG1(("tiINIIOStartIntCoalesceDif: tiDeviceHandle=%p DeviceData is NULL\n", tiDeviceHandle )); + return tiIONoDevice; + } + + /* starting IO with SAS device */ + if (oneDeviceData->DeviceType == TD_SAS_DEVICE) + { + TI_DBG6(("tiINIIOStartIntCoalesceDif: calling saSSPStart\n")); + + agRoot = oneDeviceData->agRoot; + agDevHandle = oneDeviceData->agDevHandle; + + /* OS layer has tdlayer data structure pointer in + tdIORequestBody_t tdIOReqBody; + in ccb_t in agtiapi.h + */ + tdIORequestBody = (tdIORequestBody_t *)tiRequestBody; + + /* let's initialize tdIOrequestBody */ + /* initialize callback */ + tdIORequestBody->IOCompletionFunc = itdssIOCompleted; + + /* initialize tiDevhandle */ + tdIORequestBody->tiDevHandle = tiDeviceHandle; + + /* initialize tiIORequest */ + tdIORequestBody->tiIORequest = tiIORequest; + + /* save context if we need to abort later */ + tiIORequest->tdData = tdIORequestBody; + + /* initialize expDataLength */ + tdIORequestBody->IOType.InitiatorRegIO.expDataLength + = tiScsiRequest->scsiCmnd.expDataLength; + + /* initializes "agsaSgl_t agSgl" of "agsaDifSSPInitiatorRequest_t" */ + tiStatus = itdssIOPrepareSGL( + tiRoot, + tdIORequestBody, + &tiScsiRequest->agSgl1, + tiScsiRequest->sglVirtualAddr + ); + + if (tiStatus != tiSuccess) + { + TI_DBG1(("tiINIIOStartIntCoalesceDif: can't get SGL\n")); + return tiStatus; + } + + + /* initialize agIORequest */ + agIORequest = &(tdIORequestBody->agIORequest); + agIORequest->osData = (void *) tdIORequestBody; + agIORequest->sdkData = agNULL; /* LL takes care of this */ + + + /* + initialize + tdIORequestBody_t tdIORequestBody -> agSASRequestBody + */ + agEdcSSPRequestBody = &(tdIORequestBody->transport.SAS.agEdcSSPRequestBody); + agEdcSSPInitiatorRequest = &(agEdcSSPRequestBody->edcSSPInitiatorReq); + + + /* copy cdb bytes */ + osti_memcpy(agEdcSSPInitiatorRequest->sspCmdIU.cdb, tiScsiRequest->scsiCmnd.cdb, 16); + + /* copy lun field */ + osti_memcpy(agEdcSSPInitiatorRequest->sspCmdIU.lun, + tiScsiRequest->scsiCmnd.lun.lun, 8); + + + /* setting the data length */ + agEdcSSPInitiatorRequest->dataLength = tiScsiRequest->scsiCmnd.expDataLength; + TI_DBG6(("tiINIIOStartIntCoalesceDif: tiScsiRequest->scsiCmnd.expDataLength %d\n", tiScsiRequest->scsiCmnd.expDataLength)); + + agEdcSSPInitiatorRequest->firstBurstSize = 0; + + + if (tiScsiRequest->dataDirection == tiDirectionIn) + { + agRequestType = AGSA_SSP_INIT_READ; + TI_DBG1(("tiINIIOStartIntCoalesceDif: READ difAction %X\n",difOption->difAction)); + } + else if (tiScsiRequest->dataDirection == tiDirectionOut) + { + agRequestType = AGSA_SSP_INIT_WRITE; + TI_DBG1(("tiINIIOStartIntCoalesceDif: WRITE difAction %X\n",difOption->difAction)); + } + else + { + agRequestType = AGSA_REQ_TYPE_UNKNOWN; + TI_DBG1(("tiINIIOStartIntCoalesceDif: unknown data direction\n")); + } + + tdIORequestBody->agRequestType = agRequestType; + + /* process interrupt coalesce context */ + tdsaIntCoalCxt = (tdsaIntCoalesceContext_t *)tiIntCoalesceCxt->tdData; + agIntCoalCxt = &(tdsaIntCoalCxt->agIntCoalCxt); + + /* process DIF */ + + agEdc = &(agEdcSSPInitiatorRequest->edc); + + osti_memset(agEdc, 0, sizeof(agsaDif_t)); + + /* setting edcFlag */ + if (difOption->enableBlockCount) + { + /* enables block count; bit5 */ + agEdc->edcFlag = agEdc->edcFlag | 0x20; /* 0010 0000 */ + } + + if (difOption->enableCrc) + { + /* enables CRC verification; bit6 */ + agEdc->edcFlag = agEdc->edcFlag | 0x40; /* 0100 0000 */ + } + + if (difOption->enableIOSeed) + { + + } + if (difOption->difAction == DIF_INSERT) + { + /* bit 0 - 2; 000 */ + agEdc->edcFlag = agEdc->edcFlag & 0xFFFFFFF8; + } + else if (difOption->difAction == DIF_VERIFY_FORWARD) + { + /* bit 0 - 2; 001 */ + agEdc->edcFlag = agEdc->edcFlag | 0x01; + } + else if (difOption->difAction == DIF_VERIFY_DELETE) + { + /* bit 0 - 2; 010 */ + agEdc->edcFlag = agEdc->edcFlag | 0x02; + } + else + { + /* DIF_VERIFY_REPLACE */ + /* bit 0 - 2; 011 */ + agEdc->edcFlag = agEdc->edcFlag | 0x04; + } + + /* set Update Mask; bit 16-21 */ + agUpdateMask = (difOption->tagUpdateMask) & 0x3F; /* 0011 1111 */ + agUpdateMask = agUpdateMask << 16; + agEdc->edcFlag = agEdc->edcFlag | agUpdateMask; + + /* set Verify Mask bit 24-29 */ + agVerifyMask = (difOption->tagVerifyMask) & 0x3F; /* 0011 1111 */ + agVerifyMask = agVerifyMask << 24; + agEdc->edcFlag = agEdc->edcFlag | agVerifyMask; + + agEdc->appTag = difOption->udtArray[0]; + agEdc->appTag = (agEdc->appTag << 8) | difOption->udtArray[1]; + + agEdc->lbaReferenceTag = difOption->udtArray[2]; + agEdc->lbaReferenceTag = (agEdc->lbaReferenceTag << 8) | difOption->udtArray[3]; + agEdc->lbaReferenceTag = (agEdc->lbaReferenceTag << 8) | difOption->udtArray[4]; + agEdc->lbaReferenceTag = (agEdc->lbaReferenceTag << 8) | difOption->udtArray[5]; + + /* currently TISA supports only 512 logical block size */ + agEdc->lbSize = 512; + + +#ifdef LL_INT_COALESCE + saStatus = saSSPStartIntCoalesceEdc(agRoot, + agIORequest, + agIntCoalCxt, + agDevHandle, + agRequestType, + agEdcSSPRequestBody, + &ossaSSPCompleted); +#endif + + tdIORequestBody->ioStarted = agTRUE; + tdIORequestBody->ioCompleted = agFALSE; + + if (saStatus == AGSA_RC_SUCCESS) + { + Initiator->NumIOsActive++; + tiStatus = tiSuccess; + } + else + { + TI_DBG1(("tiINIIOStartIntCoalesceDif: saSSPStart failed\n")); + tdIORequestBody->ioStarted = agFALSE; + tdIORequestBody->ioCompleted = agTRUE; + if (saStatus == AGSA_RC_BUSY) + { + tiStatus = tiBusy; + } + else + { + tiStatus = tiError; + } + return tiStatus; + } + } + else if (oneDeviceData->DeviceType == TD_SATA_DEVICE) + { + /* + satIOStart() -> saSATAStartIntCoalesceEdc() + */ + TI_DBG1(("tiINIIOStartIntCoalesceDif: SATA not supported yet\n")); + return tiStatus; + } + else + { + TI_DBG1(("tiINIIOStartIntCoalesceDif: wrong unspported Device %d\n", oneDeviceData->DeviceType)); + /* + error. unsupported IO + */ + } + return tiStatus; +} + + +osGLOBAL bit32 +tiINIIntCoalesceInit( + tiRoot_t *tiRoot, + tiIntCoalesceContext_t *tiIntCoalesceCxt, + bit32 count + ) +{ + + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + agsaRoot_t *agRoot = agNULL; + tdsaIntCoalesceContext_t *tdsaIntCoalCxtHead + = (tdsaIntCoalesceContext_t *)tdsaAllShared->IntCoalesce; + tdsaIntCoalesceContext_t *tdsaIntCoalCxt; + agsaIntCoalesceContext_t *agIntCoalCxt; + tdList_t *tdsaIntCoalCxtList = agNULL; + + bit32 tiStatus = tiError; + + TI_DBG1(("tiINIIntCoalesceInit: start\n")); + + tdsaSingleThreadedEnter(tiRoot, TD_INTCOAL_LOCK); + if (TDLIST_NOT_EMPTY(&(tdsaIntCoalCxtHead->FreeLink))) + { + TDLIST_DEQUEUE_FROM_HEAD(&tdsaIntCoalCxtList, &(tdsaIntCoalCxtHead->FreeLink)); + tdsaSingleThreadedLeave(tiRoot, TD_INTCOAL_LOCK); + tdsaIntCoalCxt + = TDLIST_OBJECT_BASE(tdsaIntCoalesceContext_t, FreeLink, tdsaIntCoalCxtList); + + TI_DBG1(("tiINIIntCoalesceInit: id %d\n", tdsaIntCoalCxt->id)); + + agRoot = &(tdsaAllShared->agRootNonInt); + + agIntCoalCxt = &(tdsaIntCoalCxt->agIntCoalCxt); + tdsaIntCoalCxt->tiIntCoalesceCxt = tiIntCoalesceCxt; + tiIntCoalesceCxt->tdData = tdsaIntCoalCxt; + agIntCoalCxt->osData = tdsaIntCoalCxt; + + tdsaSingleThreadedEnter(tiRoot, TD_INTCOAL_LOCK); + TDLIST_ENQUEUE_AT_TAIL(&(tdsaIntCoalCxt->MainLink), &(tdsaIntCoalCxtHead->MainLink)); + tdsaSingleThreadedLeave(tiRoot, TD_INTCOAL_LOCK); + + /* + note: currently asynchronously call is assumed. In other words, + "ossaIntCoalesceInitCB()" -> "ostiInitiatorCoalesceInitCB()" are used + */ +#ifdef LL_INT_COALESCE + tiStatus = saIntCoalesceInit(agRoot, agIntCoalCxt, count); +#endif + + TI_DBG6(("tiINIIntCoalesceInit: status %d\n", tiStatus)); + return tiStatus; + } + else + { + tdsaSingleThreadedLeave(tiRoot, TD_INTCOAL_LOCK); + TI_DBG1(("tiINIIntCoalesceInit: no more interrupt coalesce context; return fail\n")); + return tiStatus; + } +} +#endif /* TD_INT_COALESCE */ + +/***************************************************************************** +*! \brief itdssIOPrepareSGL +* +* Purpose: This function is called to translate TISA SGL information to the +* LL layer SGL. +* +* \param tiRoot: Pointer to initiator driver/port instance. +* \param IORequestBody: TD layer request body for the I/O. +* \param tiSgl1: First TISA SGL info. +* \param sglVirtualAddr: The virtual address of the first element in +* tiSgl1 when tiSgl1 is used with the type tiSglList. +* +* \return: +* +* tiSuccess: SGL initialized successfully. +* tiError: Failed to initialize SGL. +* +* +*****************************************************************************/ +osGLOBAL FORCEINLINE bit32 +itdssIOPrepareSGL( + tiRoot_t *tiRoot, + tdIORequestBody_t *tdIORequestBody, + tiSgl_t *tiSgl1, + void *sglVirtualAddr + ) +{ + agsaSgl_t *agSgl; + + TI_DBG6(("itdssIOPrepareSGL: start\n")); + + agSgl = &(tdIORequestBody->transport.SAS.agSASRequestBody.sspInitiatorReq.agSgl); + + agSgl->len = 0; + + if (tiSgl1 == agNULL) + { + TI_DBG1(("itdssIOPrepareSGL: Error tiSgl1 is NULL\n")); + return tiError; + } + + if (tdIORequestBody->IOType.InitiatorRegIO.expDataLength == 0) + { + TI_DBG6(("itdssIOPrepareSGL: expDataLength is 0\n")); + agSgl->sgUpper = 0; + agSgl->sgLower = 0; + agSgl->len = 0; + CLEAR_ESGL_EXTEND(agSgl->extReserved); + return tiSuccess; + } + + agSgl->sgUpper = tiSgl1->upper; + agSgl->sgLower = tiSgl1->lower; + agSgl->len = tiSgl1->len; + agSgl->extReserved = tiSgl1->type; + + return tiSuccess; +} + +osGLOBAL bit32 +tiNumOfLunIOCTLreq( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + void *tiRequestBody, + tiIOCTLPayload_t *agIOCTLPayload, + void *agParam1, + void *agParam2 + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + agsaRoot_t *agRoot = &(tdsaAllShared->agRootInt); + void *respBuffer = agNULL; + void *osMemHandle = agNULL; + bit32 ostiMemoryStatus = 0; + tdsaDeviceData_t *oneDeviceData = agNULL; + agsaSSPInitiatorRequest_t *agSSPFrame = agNULL; + bit32 status = IOCTL_CALL_SUCCESS; + bit32 agRequestType = 0; + agsaDevHandle_t *agDevHandle = agNULL; + agsaIORequest_t *agIORequest = agNULL; + tdIORequestBody_t *tdIORequestBody = agNULL; + agsaSASRequestBody_t *agSASRequestBody = agNULL; + + do + { + if((tiIORequest == agNULL) || (tiRequestBody == agNULL)) + { + status = IOCTL_CALL_FAIL; + break; + } + tdIORequestBody = (tdIORequestBody_t *)tiRequestBody; + + if(tdIORequestBody == agNULL) + { + status = IOCTL_CALL_FAIL; + break; + } + tdIORequestBody->tiIORequest = tiIORequest; + + /* save context if we need to abort later */ + tiIORequest->tdData = tdIORequestBody; + + agIORequest = &(tdIORequestBody->agIORequest); + agIORequest->osData = (void *) tdIORequestBody; + agSASRequestBody = &(tdIORequestBody->transport.SAS.agSASRequestBody); + agSSPFrame = &(agSASRequestBody->sspInitiatorReq); + + ostiMemoryStatus = ostiAllocMemory( tiRoot, + &osMemHandle, + (void **)&respBuffer, + &(agSSPFrame->agSgl.sgUpper), + &(agSSPFrame->agSgl.sgLower), + 8, + REPORT_LUN_LEN, + agFALSE); + if((ostiMemoryStatus != tiSuccess) && (respBuffer == agNULL )) + { + status = IOCTL_CALL_FAIL; + break; + } + + osti_memset((void *)respBuffer, 0, REPORT_LUN_LEN); + + // use FW control place in shared structure to keep the neccesary information + tdsaAllShared->tdFWControlEx.virtAddr = respBuffer; + tdsaAllShared->tdFWControlEx.len = REPORT_LUN_LEN; + tdsaAllShared->tdFWControlEx.param1 = agParam1; + tdsaAllShared->tdFWControlEx.param2 = agParam2; + tdsaAllShared->tdFWControlEx.payload = agIOCTLPayload; + tdsaAllShared->tdFWControlEx.inProgress = 1; + agRequestType = AGSA_SSP_INIT_READ; + + status = IOCTL_CALL_PENDING; + oneDeviceData = (tdsaDeviceData_t *)(tiDeviceHandle->tdData); + agDevHandle = oneDeviceData->agDevHandle; + + agSSPFrame->sspCmdIU.cdb[0] = REPORT_LUN_OPCODE; + agSSPFrame->sspCmdIU.cdb[1] = 0x0; + agSSPFrame->sspCmdIU.cdb[2] = 0x0; + agSSPFrame->sspCmdIU.cdb[3] = 0x0; + agSSPFrame->sspCmdIU.cdb[4] = 0x0; + agSSPFrame->sspCmdIU.cdb[5] = 0x0; + agSSPFrame->sspCmdIU.cdb[6] = 0x0; + agSSPFrame->sspCmdIU.cdb[7] = 0x0; + agSSPFrame->sspCmdIU.cdb[8] = 0x0; + agSSPFrame->sspCmdIU.cdb[9] = REPORT_LUN_LEN; + agSSPFrame->sspCmdIU.cdb[10] = 0x0; + agSSPFrame->sspCmdIU.cdb[11] = 0x0; + + agSSPFrame->dataLength = REPORT_LUN_LEN; + agSSPFrame->agSgl.len = sizeof(agsaSSPCmdInfoUnit_t); + + status = saSSPStart(agRoot, agIORequest, 0, agDevHandle, agRequestType,agSASRequestBody,agNULL, + &ossaSSPIoctlCompleted); + if(status != AGSA_RC_SUCCESS) + { + ostiFreeMemory(tiRoot, + tdsaAllShared->tdFWControlEx.virtAddr, + tdsaAllShared->tdFWControlEx.len); + tdsaAllShared->tdFWControlEx.payload = NULL; + tdsaAllShared->tdFWControlEx.inProgress = 0; + status = IOCTL_CALL_FAIL; + } + }while(0); + return status; +} + + diff --git a/sys/dev/pms/RefTisa/tisa/sassata/sas/ini/itdtypes.h b/sys/dev/pms/RefTisa/tisa/sassata/sas/ini/itdtypes.h new file mode 100644 index 000000000000..41c4775f8782 --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/sas/ini/itdtypes.h @@ -0,0 +1,59 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/*******************************************************************************/ +/** \file + * + * + * data structures for SAS intiator in SAS/SATA TD layer + * + */ + +#ifndef __ITDTYPES_H__ + +#define __ITDTYPES_H__ + +#include +#include +#include +#include +#include + +/** \brief data structure for the options of SAS initiator + * + * This data structure contains options for SAS initiator such as the maximum + * number of allowed targets and DIF capability + * + */ +typedef struct itdssOperatingOption_s { + bit32 MaxTargets; /**< the maximum number of allowed targets */ + /* this is read from a file or #defined + then passed to TD layer from tiInitiatorResource_t + */ + bit32 UsecsPerTick; /* in micro seconds */ +} itdssOperatingOption_t; + + + + +#endif /* __ITDTYPES_H__ */ diff --git a/sys/dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdcb.c b/sys/dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdcb.c new file mode 100644 index 000000000000..2f2e83781f01 --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdcb.c @@ -0,0 +1,62 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#ifdef INITIATOR_DRIVER +#include +#include +#include +#endif + +#ifdef TARGET_DRIVER +#include "ttdglobl.h" +#include "ttdtxchg.h" +#include "ttdtypes.h" +#endif + +#include +#include + +/* STUBS */ +osGLOBAL void ossaSATAAbortCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 flag, + bit32 status) +{ + return; +} diff --git a/sys/dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdglobl.h b/sys/dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdglobl.h new file mode 100644 index 000000000000..de00e813d313 --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdglobl.h @@ -0,0 +1,71 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +/*******************************************************************************/ +/** \file + * + * $RCSfile: ttdglobl.h,v $ + * + * Copyright 2006 PMC-Sierra, Inc. + * + * $Author: vempatin $ + * $Revision: 113679 $ + * $Date: 2012-04-16 14:35:19 -0700 (Mon, 16 Apr 2012) $ + * + * #define for SAS target in SAS/SATA TD layer + * + */ + + +#ifndef __TTD_GLOBALS_H__ + +#define __TTD_GLOBALS_H__ + +/* + * Transport Target specific default parameters. + */ +#define DEFAULT_XCHGS 256 +#define DEFAULT_TGT_TIMER_TICK 1000000 /* 1 second */ +#define DEFAULT_MAX_TARGETS 256 +#define DEFAULT_BLOCK_SIZE 512 + + +/* Exchange field accessors */ +#define TD_XCHG_CONTEXT(ti_root) (&TD_GET_TITGT_CONTEXT(ti_root)->ttdsaXchgData) +#define TD_XCHG_CONTEXT_MAX_NUM_XCHGS(ti_root) (TD_XCHG_CONTEXT(ti_root)->maxNumXchgs) +#define TD_XCHG_CONTEXT_NO_USED(ti_root) (TD_XCHG_CONTEXT(ti_root)->noUsed) +#define TD_XCHG_CONTEXT_NO_FREED(ti_root) (TD_XCHG_CONTEXT(ti_root)->noFreed) +#define TD_XCHG_CONTEXT_NO_CMD_RCVD(ti_root) (TD_XCHG_CONTEXT(ti_root)->noCmdRcvd) +#define TD_XCHG_CONTEXT_NO_START_IO(ti_root) (TD_XCHG_CONTEXT(ti_root)->noStartIo) +#define TD_XCHG_CONTEXT_NO_SEND_RSP(ti_root) (TD_XCHG_CONTEXT(ti_root)->noSendRsp) +#define TD_XCHG_CONTEXT_NO_IO_COMPLETED(ti_root) (TD_XCHG_CONTEXT(ti_root)->noCompleted) + +#define TD_XCHG_GET_CONTEXT(ti_request) ((ttdsaXchg_t *)(ti_request)->tdData) +#define TD_XCHG_GET_STATE(xchg) (xchg->state) +#define TD_XCHG_SET_STATE(xchg, val) (xchg->state) = (val) + +#define TD_XCHG_STATE_ACTIVE 1 +#define TD_XCHG_STATE_INACTIVE 0 + +#define READ_GOOD_RESPONSE 0x1 +#define WRITE_GOOD_RESPONSE 0x2 + +#endif /* __TTD_GLOBALS_H__ */ diff --git a/sys/dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdinit.c b/sys/dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdinit.c new file mode 100644 index 000000000000..19889237890f --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdinit.c @@ -0,0 +1,922 @@ +/******************************************************************************* + *Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + ********************************************************************************/ +/*******************************************************************************/ +/** \file + * + * $RCSfile: ttdinit.c,v $ + * + * Copyright 2006 PMC-Sierra, Inc. + * + * $Author: vempatin $ + * $Revision: 113679 $ + * $Date: 2012-04-16 14:35:19 -0700 (Mon, 16 Apr 2012) $ + * + * This file contains initiator IO related functions in TD layer + * + */ +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#ifdef INITIATOR_DRIVER +#include +#include +#include +#endif + +#ifdef TARGET_DRIVER +#include "ttdglobl.h" +#include "ttdtxchg.h" +#include "ttdtypes.h" +#endif + +#include +#include + +/* io trace only */ +extern void TDTraceInit(void); +/* io trace only */ + + +osGLOBAL bit32 +ttdssInit( + tiRoot_t *tiRoot, + tiTargetResource_t *targetResource, + tiTdSharedMem_t *tdSharedMem +) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *)tiRoot->tdData; + tiTargetMem_t *tgtMem; + ttdsaTgt_t *Target; + ttdssOperatingOption_t *OperatingOption; + char *buffer; + bit32 buffLen; + bit32 lenRecv = 0; + char *pLastUsedChar = agNULL; + char tmpBuffer[DEFAULT_KEY_BUFFER_SIZE]; + char globalStr[] = "OSParms"; + + TI_DBG5(("ttdssInit: start\n")); + + /* + first set the values to Default values + Then, overwrite them using ostiGetTransportParam() + */ + + /* to remove compiler warnings */ + buffer = &tmpBuffer[0]; + buffLen = sizeof (tmpBuffer); + + osti_memset(buffer, 0, buffLen); + + tgtMem = &targetResource->targetMem; + + /* + * Cached mem for target Transport Dependent Layer main functionality + */ + Target = tgtMem->tdMem[0].virtPtr; + + OperatingOption = &Target->OperatingOption; + /* + * Get default parameters from the OS Specific area + * and reads parameters from the configuration file + */ + ttdssGetOperatingOptionParams(tiRoot, OperatingOption); + + + /* + * Update TD operating options + */ + OperatingOption->UsecsPerTick = + targetResource->targetOption.usecsPerTick; + OperatingOption->numXchgs = tgtMem->tdMem[1].numElements; + + + if (ttdsaXchgInit(tiRoot, + &Target->ttdsaXchgData, + tgtMem, + OperatingOption->numXchgs + ) == agFALSE) + { + TI_DBG1(("ttdInit: ttdsaXchgInit failed\n")); + return tiError; + } + + /* Get number of AutoGoodResponse entry */ + if ((ostiGetTransportParam( + tiRoot, + globalStr, + agNULL, + agNULL, + agNULL, + agNULL, + agNULL, + "AutoGoodResponse", + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + tdsaRoot->autoGoodRSP = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + tdsaRoot->autoGoodRSP = osti_strtoul (buffer, &pLastUsedChar, 10); + } + + } + + return tiSuccess; +} + +/* + this combines ttdGetDefaultParams and ttdGetTargetParms + + */ +osGLOBAL void +ttdssGetOperatingOptionParams( + tiRoot_t *tiRoot, + ttdssOperatingOption_t *OperatingOption +) +{ + char *key = agNULL; + char *subkey1 = agNULL; + char *subkey2 = agNULL; + char *buffer; + bit32 buffLen; + bit32 lenRecv = 0; + char *pLastUsedChar = agNULL; + char tmpBuffer[DEFAULT_KEY_BUFFER_SIZE]; + char globalStr[] = "Global"; + char iniParmsStr[] = "TargetParms"; + + TI_DBG5(("ttdssGetOperatingOptionParams: start\n")); + + /* + first set the values to Default values + Then, overwrite them using ostiGetTransportParam() + */ + + + /* to remove compiler warnings */ + pLastUsedChar = pLastUsedChar; + lenRecv = lenRecv; + subkey2 = subkey2; + subkey1 = subkey1; + key = key; + buffer = &tmpBuffer[0]; + buffLen = sizeof (tmpBuffer); + + osti_memset(buffer, 0, buffLen); + + + /* in ttgglobl.h */ + OperatingOption->numXchgs = DEFAULT_XCHGS; + OperatingOption->UsecsPerTick = DEFAULT_TGT_TIMER_TICK; /* 1 sec */ + OperatingOption->MaxTargets = DEFAULT_MAX_TARGETS; + OperatingOption->BlockSize = DEFAULT_BLOCK_SIZE; + + + /* defaults are overwritten in the following */ + /* Get number of exchanges */ + if ((ostiGetTransportParam( + tiRoot, + globalStr, + iniParmsStr, + agNULL, + agNULL, + agNULL, + agNULL, + "NumberExchanges", + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + OperatingOption->numXchgs = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + OperatingOption->numXchgs = osti_strtoul (buffer, &pLastUsedChar, 10); + } + + } + + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + /* Get number of MaxTargets */ + if ((ostiGetTransportParam( + tiRoot, + globalStr, + iniParmsStr, + agNULL, + agNULL, + agNULL, + agNULL, + "MaxTargets", + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + OperatingOption->MaxTargets = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + OperatingOption->MaxTargets = osti_strtoul (buffer, &pLastUsedChar, 10); + } + + } + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + /* Get number of BlockSize */ + if ((ostiGetTransportParam( + tiRoot, + globalStr, + iniParmsStr, + agNULL, + agNULL, + agNULL, + agNULL, + "BlockSize", + buffer, + buffLen, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + OperatingOption->BlockSize = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + OperatingOption->BlockSize = osti_strtoul (buffer, &pLastUsedChar, 10); + } + } + osti_memset(buffer, 0, buffLen); + lenRecv = 0; + + + + TI_DBG5(("ttdssGetOperatingOptionParams: NumberExchanges %d UsecsPerTick %d MaxTargets %d BlockSize %d\n", OperatingOption->numXchgs, OperatingOption->UsecsPerTick, OperatingOption->MaxTargets, OperatingOption->BlockSize)); + + return; +} + +/* not yet */ +osGLOBAL void +ttdssGetResource( + tiRoot_t *tiRoot, + tiTargetResource_t *targetResource +) +{ + tiTargetMem_t *tgtMem; + int i; + ttdssOperatingOption_t OperatingOption; + bit32 xchgSize; + bit32 respSize; + bit32 smprespSize; + + TI_DBG4(("ttdssGetResource: start\n")); + + tgtMem = &targetResource->targetMem; + + /* + only 4 memory descriptors are used + */ + tgtMem->count = 4; + + /* initiailization */ + for (i = 0 ; i < 10 ; i++) + { + tgtMem->tdMem[i].singleElementLength = 0; + tgtMem->tdMem[i].numElements = 0; + tgtMem->tdMem[i].totalLength = 0; + tgtMem->tdMem[i].alignment = 0; + tgtMem->tdMem[i].type = TI_CACHED_MEM; + tgtMem->tdMem[i].reserved = 0; + tgtMem->tdMem[i].virtPtr = agNULL; + tgtMem->tdMem[i].osHandle = agNULL; + tgtMem->tdMem[i].physAddrUpper = 0; + tgtMem->tdMem[i].physAddrLower = 0; + } + + /* + * Get default parameters from the OS Specific area + * and reads parameters from the configuration file + */ + ttdssGetOperatingOptionParams(tiRoot, &OperatingOption); + + /* target */ + tgtMem->tdMem[0].singleElementLength = sizeof(ttdsaTgt_t); + tgtMem->tdMem[0].numElements = 1; + tgtMem->tdMem[0].totalLength = + tgtMem->tdMem[0].singleElementLength * + tgtMem->tdMem[0].numElements; + tgtMem->tdMem[0].alignment = sizeof (void *); + tgtMem->tdMem[0].type = TI_CACHED_MEM; + tgtMem->tdMem[0].reserved = 0; + tgtMem->tdMem[0].virtPtr = agNULL; + tgtMem->tdMem[0].osHandle = agNULL; + tgtMem->tdMem[0].physAddrUpper = 0; + tgtMem->tdMem[0].physAddrLower = 0; + + /* + * Cached memory for I/O exchange structures + */ + xchgSize = sizeof(ttdsaXchg_t); + xchgSize = AG_ALIGNSIZE(xchgSize, 8); + + tgtMem->tdMem[1].singleElementLength = xchgSize; + tgtMem->tdMem[1].numElements = OperatingOption.numXchgs; + tgtMem->tdMem[1].totalLength = tgtMem->tdMem[1].singleElementLength * + tgtMem->tdMem[1].numElements; + tgtMem->tdMem[1].alignment = sizeof(void *); + tgtMem->tdMem[1].type = TI_CACHED_MEM; + tgtMem->tdMem[1].reserved = 0; + tgtMem->tdMem[1].virtPtr = agNULL; + tgtMem->tdMem[1].osHandle = agNULL; + tgtMem->tdMem[1].physAddrUpper = 0; + tgtMem->tdMem[1].physAddrLower = 0; + + /* + * Uncached memory for response buffer structures + */ + TI_DBG4(("ttdssGetResource: sas_resp_t size 0x%x %d\n", + (unsigned int)sizeof(sas_resp_t), (int)sizeof(sas_resp_t))); + + respSize = (sizeof(sas_resp_t) + AG_WORD_ALIGN_ADD) & AG_WORD_ALIGN_MASK; + TI_DBG4(("ttdssGetResource: response size 0x%x %d\n", respSize,respSize)); + respSize = AG_ALIGNSIZE(respSize, 8); + TI_DBG4(("ttdssGetResource: response size 0x%x %d\n", respSize,respSize)); + tgtMem->tdMem[2].singleElementLength = 0x1000; /* respSize; 0x1000; */ + tgtMem->tdMem[2].numElements = OperatingOption.numXchgs; /* Same as num of xchg */ + tgtMem->tdMem[2].totalLength = tgtMem->tdMem[2].singleElementLength * + tgtMem->tdMem[2].numElements; + /* 8;4;16;256;sizeof(void *); all worked */ + tgtMem->tdMem[2].alignment = 16; + tgtMem->tdMem[2].type = TI_DMA_MEM; /* uncached memory */ + tgtMem->tdMem[2].reserved = 0; + tgtMem->tdMem[2].virtPtr = agNULL; + tgtMem->tdMem[2].osHandle = agNULL; + tgtMem->tdMem[2].physAddrUpper = 0; + tgtMem->tdMem[2].physAddrLower = 0; + + /* + * Uncached memory for SMP response buffer structures + */ + smprespSize = sizeof(smp_resp_t); + smprespSize = AG_ALIGNSIZE(smprespSize, 8); + TI_DBG4(("ttdssGetResource: SMP response size 0x%x %d\n", smprespSize,smprespSize)); + + tgtMem->tdMem[3].singleElementLength = smprespSize; /*0x1000; smprespSize; */ + tgtMem->tdMem[3].numElements = OperatingOption.numXchgs; /* Same as num of xchg */ + tgtMem->tdMem[3].totalLength + = tgtMem->tdMem[3].singleElementLength * tgtMem->tdMem[3].numElements; + tgtMem->tdMem[3].alignment = 16; /* 4; 256; 16; sizeof(void *); */ + tgtMem->tdMem[3].type = TI_DMA_MEM; /* uncached memory */ + tgtMem->tdMem[3].reserved = 0; + tgtMem->tdMem[3].virtPtr = agNULL; + tgtMem->tdMem[3].osHandle = agNULL; + tgtMem->tdMem[3].physAddrUpper = 0; + tgtMem->tdMem[3].physAddrLower = 0; + + + + targetResource->targetOption.usecsPerTick = OperatingOption.UsecsPerTick; + targetResource->targetOption.pageSize = 0; /* not applicable to SAS/SATA */ + targetResource->targetOption.numLgns = 0; /* not applicable to SAS/SATA */ + targetResource->targetOption.numSessions = 0; /* not applicable to SAS/SATA */ + targetResource->targetOption.numXchgs = OperatingOption.numXchgs; + + + /* + This is not used in OS like Linux which supports dynamic memeory allocation + In short, this is for Windows + */ + /* Estimate dynamic DMA memory */ + targetResource->targetOption.dynamicDmaMem.alignment = sizeof(void *); + + targetResource->targetOption.dynamicDmaMem.numElements = 128; + targetResource->targetOption.dynamicDmaMem.singleElementLength = sizeof(tdssSMPRequestBody_t); + targetResource->targetOption.dynamicDmaMem.totalLength = + targetResource->targetOption.dynamicDmaMem.numElements * + targetResource->targetOption.dynamicDmaMem.singleElementLength; + + /* Estimate dynamic cached memory */ + targetResource->targetOption.dynamicCachedMem.alignment = sizeof(void *); + targetResource->targetOption.dynamicCachedMem.numElements = 128; + targetResource->targetOption.dynamicCachedMem.singleElementLength = sizeof(tdssSMPRequestBody_t); + targetResource->targetOption.dynamicCachedMem.totalLength = + targetResource->targetOption.dynamicCachedMem.numElements * + targetResource->targetOption.dynamicCachedMem.singleElementLength; + + + return; +} + +/* not in use */ +osGLOBAL void +ttdssGetTargetParams( + tiRoot_t *tiRoot +) +{ + TI_DBG6(("ttdssGetTargetParams: start\n")); + return; +} + +osGLOBAL agBOOLEAN +ttdsaXchgInit( + tiRoot_t *tiRoot, + ttdsaXchgData_t *ttdsaXchgData, + tiTargetMem_t *tgtMem, + bit32 maxNumXchgs +) +{ + ttdsaXchg_t *ttdsaXchg; + bit32 i, respLen; + bit8 *virtualAddr; + bit32 phyAddrLower, phyAddrUpper; + bit32 smprespLen; + bit32 smpphyAddrLower, smpphyAddrUpper; + bit8 *smpvirtualAddr; + + + + TI_DBG5(("ttdsaXchgInit: start\n")); + /* io trace only */ + TDTraceInit(); + /* io trace only */ + + /* + * Set and initialize some global exchange information + */ + TDLIST_INIT_HDR(&ttdsaXchgData->xchgFreeList); + TDLIST_INIT_HDR(&ttdsaXchgData->xchgBusyList); + + ttdsaXchgData->maxNumXchgs = maxNumXchgs; + + /* Initialize exchange and response buffer structures */ + ttdsaXchg = (ttdsaXchg_t *) tgtMem->tdMem[1].virtPtr; + + /* Initialize response buffer */ + virtualAddr = tgtMem->tdMem[2].virtPtr; + phyAddrUpper = tgtMem->tdMem[2].physAddrUpper; + phyAddrLower = tgtMem->tdMem[2].physAddrLower; + respLen = tgtMem->tdMem[2].singleElementLength; + + ttdsaXchg->resp.virtAddr = virtualAddr; + ttdsaXchg->resp.phyAddrUpper = phyAddrUpper; + ttdsaXchg->resp.phyAddrLower = phyAddrLower; + ttdsaXchg->resp.length = respLen; + + /* Initialize SMP response buffer */ + smpvirtualAddr = tgtMem->tdMem[3].virtPtr; + smpphyAddrUpper = tgtMem->tdMem[3].physAddrUpper; + smpphyAddrLower = tgtMem->tdMem[3].physAddrLower; + smprespLen = tgtMem->tdMem[3].singleElementLength; + + ttdsaXchg->smpresp.virtAddr = smpvirtualAddr; + ttdsaXchg->smpresp.phyAddrUpper = smpphyAddrUpper; + ttdsaXchg->smpresp.phyAddrLower = smpphyAddrLower; + ttdsaXchg->smpresp.length = smprespLen; + + /* Initialization of callback and etc */ + for (i=0;iid = i; + ttdsaXchg->usedEsgl = agFALSE; + ttdsaXchg->io_found = agTRUE; + ttdsaXchg->DeviceData = agNULL; + /* callback for IO(ssp) and SMP */ + ttdsaXchg->IORequestBody.IOCompletionFunc = ttdsaIOCompleted; + ttdsaXchg->SMPRequestBody.SMPCompletionFunc = ttdsaSMPCompleted; + + + TDLIST_INIT_ELEMENT(&ttdsaXchg->XchgLinks ); + + ttdsaXchg->IORequestBody.agIORequest.osData = (void *)ttdsaXchg; + ttdsaXchg->IORequestBody.tiIORequest + = &(ttdsaXchg->IORequestBody.IOType.TargetIO.tiIORequest); + + /* Init the tdData portion of tiIORequest context for this exchange */ + ttdsaXchg->IORequestBody.tiIORequest->tdData = ttdsaXchg; + + /* SMP */ + ttdsaXchg->SMPRequestBody.agIORequest.osData = (void *)ttdsaXchg; + /* ttdsaXchg->SMPRequestBody.agIORequest.osData = (void *)&ttdsaXchg->SMPRequestBody; */ + /*ttdsaXchg->SMPRequestBody.tiIORequest.tdData = (void *)&ttdsaXchg->SMPRequestBody; */ + + + + + /* Initialize the CDB and LUN addresses */ + ttdsaXchg->tiTgtScsiCmnd.reqCDB = &(ttdsaXchg->agSSPCmndIU.cdb[0]); + ttdsaXchg->tiTgtScsiCmnd.scsiLun = &(ttdsaXchg->agSSPCmndIU.lun[0]); + + ttdsaXchg->index = i; + ttdsaXchg->respLen = respLen; /* 100 */ + ttdsaXchg->smprespLen = smprespLen; /* 100 */ + ttdsaXchg->TLR = 0; + TD_XCHG_SET_STATE(ttdsaXchg, TD_XCHG_STATE_INACTIVE); + ttdsaXchg->retries = 0; + + ttdsaXchgLinkInit(tiRoot,ttdsaXchg); + + /* Save current response payload/buffer address */ + virtualAddr = ttdsaXchg->resp.virtAddr; + phyAddrLower = ttdsaXchg->resp.phyAddrLower; + smpvirtualAddr = ttdsaXchg->smpresp.virtAddr; + smpphyAddrLower = ttdsaXchg->smpresp.phyAddrLower; + + TI_DBG5(("ttdsaXchgInit: +1 before\n")); + if (i == (maxNumXchgs - 1)) + { + /* at the last one */ + TI_DBG5(("ttdsaXchgInit: last one break\n")); + break; + } + + /* Advance to next exchange */ + ttdsaXchg = ttdsaXchg + 1; + TI_DBG5(("ttdsaXchgInit: +1 after\n")); + + /* Update response payload/buffer address */ + ttdsaXchg->resp.virtAddr = virtualAddr + respLen; + TI_DBG5(("ttdsaXchgInit: pos 1\n")); + ttdsaXchg->resp.phyAddrUpper = phyAddrUpper; + TI_DBG5(("ttdsaXchgInit: pos 2\n")); + ttdsaXchg->resp.phyAddrLower = phyAddrLower + respLen; + TI_DBG5(("ttdsaXchgInit: pos 3\n")); + ttdsaXchg->resp.length = respLen; + TI_DBG5(("ttdsaXchgInit: pos 4\n")); + + /* Update SMP response payload/buffer address */ + ttdsaXchg->smpresp.virtAddr = smpvirtualAddr + smprespLen; + ttdsaXchg->smpresp.phyAddrUpper = smpphyAddrUpper; + ttdsaXchg->smpresp.phyAddrLower = smpphyAddrLower + smprespLen; + ttdsaXchg->smpresp.length = smprespLen; + + } + + /* Reinitialize counters. + * This must be done at the end + */ + TD_XCHG_CONTEXT_NO_USED(tiRoot) = 0; + TD_XCHG_CONTEXT_NO_FREED(tiRoot) = 0; + TD_XCHG_CONTEXT_NO_CMD_RCVD(tiRoot) = 0; + TD_XCHG_CONTEXT_NO_START_IO(tiRoot) = 0; + TD_XCHG_CONTEXT_NO_SEND_RSP(tiRoot) = 0; + TD_XCHG_CONTEXT_NO_IO_COMPLETED(tiRoot) = 0; + + TI_DBG5(("ttdsaXchgInit: end\n")); + return agTRUE; +} + +osGLOBAL void +ttdsaXchgLinkInit( + tiRoot_t *tiRoot, + ttdsaXchg_t *ttdsaXchg +) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *)tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + ttdsaTgt_t *Target = (ttdsaTgt_t *)tdsaAllShared->ttdsaTgt; + bit32 i; + bit8 *data; + + TI_DBG5(("ttdsaXchgLinkInit: start\n")); + TI_DBG5(("ttdsaXchgLinkInit: xchg %p\n",ttdsaXchg)); + TI_DBG5(("ttdsaXchgLinkInit: resp %p\n",ttdsaXchg->resp.virtAddr)); + TI_DBG5(("ttdsaXchgLinkInit: smpresp %p\n",ttdsaXchg->smpresp.virtAddr)); + + if (TD_XCHG_GET_STATE(ttdsaXchg) == TD_XCHG_STATE_ACTIVE) + { + TI_DBG1(("ttdsaXchgLinkInit: active xchg *****************; wrong\n")); + return; + } + + ttdsaXchg->tag = 0xFFFF; + ttdsaXchg->IORequestBody.agIORequest.sdkData = agNULL; + ttdsaXchg->SMPRequestBody.agIORequest.sdkData = agNULL; + ttdsaXchg->statusSent = agFALSE; + ttdsaXchg->responseSent = agFALSE; + ttdsaXchg->readRspCollapsed = agFALSE; + ttdsaXchg->wrtRspCollapsed = agFALSE; + ttdsaXchg->pTMResp = agNULL; + ttdsaXchg->oustandingIos = 0; + ttdsaXchg->isAborting = agFALSE; + ttdsaXchg->oslayerAborting = agFALSE; + ttdsaXchg->isTMRequest = agFALSE; + ttdsaXchg->io_found = agTRUE; + ttdsaXchg->tiIOToBeAbortedRequest = agNULL; + ttdsaXchg->XchgToBeAborted = agNULL; + + osti_memset((void *)ttdsaXchg->resp.virtAddr, 0, ttdsaXchg->respLen); + osti_memset((void *)ttdsaXchg->smpresp.virtAddr, 0, ttdsaXchg->smprespLen); + + data = (bit8 *)ttdsaXchg->resp.virtAddr; + for (i = 0; i< ttdsaXchg->respLen; i++) + { + if (data[i] != 0) + { + TI_DBG5(("!! ttdsaXchgLinkInit: data[%d] 0x%x\n", i, data[i])); + } + } + + ttdsaXchg->resp.length = 0; + + ttdsaXchg->DeviceData = agNULL; + TI_DBG5(("ttdsaXchgLinkInit: id %d\n", ttdsaXchg->id)); + + TD_XCHG_SET_STATE(ttdsaXchg, TD_XCHG_STATE_INACTIVE); + tdsaSingleThreadedEnter(tiRoot, TD_TGT_LOCK); + TDLIST_ENQUEUE_AT_TAIL( &ttdsaXchg->XchgLinks, &Target->ttdsaXchgData.xchgFreeList); + tdsaSingleThreadedLeave(tiRoot, TD_TGT_LOCK); + + + TD_XCHG_CONTEXT_NO_FREED(tiRoot) = TD_XCHG_CONTEXT_NO_FREED(tiRoot) +1; + TI_DBG5(("ttdsaXchgLinkInit: end\n")); + return; +} + +/* + before: ttdsaXchg is in xchgBusyList + after: ttdsaXchg is in xchgFreeList + */ +osGLOBAL void +ttdsaXchgFreeStruct( + tiRoot_t *tiRoot, + ttdsaXchg_t *ttdsaXchg +) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *)tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + ttdsaTgt_t *Target = (ttdsaTgt_t *)tdsaAllShared->ttdsaTgt; + bit32 i; + bit8 *data; + + TI_DBG5(("ttdsaXchgFreeStruct: start\n")); + TI_DBG5(("ttdsaXchgFreeStruct: xchg %p\n",ttdsaXchg)); + TI_DBG5(("ttdsaXchgFreeStruct: resp %p\n",ttdsaXchg->resp.virtAddr)); + TI_DBG5(("ttdsaXchgFreeStruct: smpresp %p\n",ttdsaXchg->smpresp.virtAddr)); + + if (TD_XCHG_GET_STATE(ttdsaXchg) == TD_XCHG_STATE_INACTIVE) + { + TI_DBG1(("tdsaXchgFreeStruct: INACTIVE xchg *****************, wrong\n")); + return; + } + + ttdsaXchg->tag = 0xFFFF; + ttdsaXchg->IORequestBody.agIORequest.sdkData = agNULL; + ttdsaXchg->SMPRequestBody.agIORequest.sdkData = agNULL; + ttdsaXchg->statusSent = agFALSE; + ttdsaXchg->responseSent = agFALSE; + ttdsaXchg->readRspCollapsed = agFALSE; + ttdsaXchg->wrtRspCollapsed = agFALSE; + ttdsaXchg->pTMResp = agNULL; + ttdsaXchg->oustandingIos = 0; + ttdsaXchg->isAborting = agFALSE; + ttdsaXchg->oslayerAborting = agFALSE; + ttdsaXchg->isTMRequest = agFALSE; + ttdsaXchg->io_found = agTRUE; + ttdsaXchg->tiIOToBeAbortedRequest = agNULL; + ttdsaXchg->XchgToBeAborted = agNULL; + + osti_memset((void *)ttdsaXchg->resp.virtAddr, 0, ttdsaXchg->respLen); + osti_memset((void *)ttdsaXchg->smpresp.virtAddr, 0, ttdsaXchg->smprespLen); + + data = (bit8 *)ttdsaXchg->resp.virtAddr; + for (i = 0; i< ttdsaXchg->respLen; i++) + { + if (data[i] != 0) + { + TI_DBG5(("!! ttdsaXchgFreeStruct: data[%d] 0x%x\n", i, data[i])); + } + } + + ttdsaXchg->resp.length = 0; + + ttdsaXchg->DeviceData = agNULL; + TI_DBG5(("ttdsaXchgFreeStruct: id %d\n", ttdsaXchg->id)); + + tdsaSingleThreadedEnter(tiRoot, TD_TGT_LOCK); + TD_XCHG_SET_STATE(ttdsaXchg, TD_XCHG_STATE_INACTIVE); + TDLIST_DEQUEUE_THIS(&ttdsaXchg->XchgLinks); + TDLIST_ENQUEUE_AT_TAIL( &ttdsaXchg->XchgLinks, &Target->ttdsaXchgData.xchgFreeList); + tdsaSingleThreadedLeave(tiRoot, TD_TGT_LOCK); + + TD_XCHG_CONTEXT_NO_FREED(tiRoot) = TD_XCHG_CONTEXT_NO_FREED(tiRoot) +1; + TI_DBG5(("ttdsaXchgFreeStruct: end\n")); + return; +} + + +/* + before: ttdsaXchg is in xchgFreeList + after: ttdsaXchg is in xchgBusyList + */ +osGLOBAL ttdsaXchg_t *ttdsaXchgGetStruct(agsaRoot_t *agRoot) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + ttdsaTgt_t *Target = (ttdsaTgt_t *)osData->ttdsaTgt; + tdList_t *Link; + ttdsaXchg_t *ttdsaXchg = agNULL; + + TI_DBG3 (("ttdsaXchgGetStruct: enter\n")); + + tdsaSingleThreadedEnter(tiRoot, TD_TGT_LOCK); + if (TDLIST_EMPTY(&(Target->ttdsaXchgData.xchgFreeList))) + { + tdsaSingleThreadedLeave(tiRoot, TD_TGT_LOCK); + TI_DBG1(("ttdsaXchgGetStruct: no free ttdsaXchgData\n")); + // ttdsaDumpallXchg(tiRoot); + return agNULL; + } + + TDLIST_DEQUEUE_FROM_HEAD(&Link, &Target->ttdsaXchgData.xchgFreeList); + if ( Link == agNULL ) + { + tdsaSingleThreadedLeave(tiRoot, TD_TGT_LOCK); + TI_DBG1(("ttdsaXchgGetStruct: Link NULL: PRBLM \n")); + return agNULL; + } + + ttdsaXchg = TDLIST_OBJECT_BASE(ttdsaXchg_t, XchgLinks, Link); + + if (TD_XCHG_GET_STATE(ttdsaXchg) == TD_XCHG_STATE_ACTIVE) + { + TI_DBG1(("ttdsaXchgGetStruct: ACTIVE xchg *****************, wrong\n")); + TDLIST_DEQUEUE_THIS(&ttdsaXchg->XchgLinks); + TDLIST_ENQUEUE_AT_TAIL(&ttdsaXchg->XchgLinks, &Target->ttdsaXchgData.xchgFreeList); + TD_XCHG_SET_STATE(ttdsaXchg, TD_XCHG_STATE_INACTIVE); + tdsaSingleThreadedLeave(tiRoot, TD_TGT_LOCK); + + return agNULL; + } + + TDLIST_DEQUEUE_THIS(&ttdsaXchg->XchgLinks); + TDLIST_ENQUEUE_AT_TAIL(&ttdsaXchg->XchgLinks, &Target->ttdsaXchgData.xchgBusyList); + TD_XCHG_SET_STATE(ttdsaXchg, TD_XCHG_STATE_ACTIVE); + tdsaSingleThreadedLeave(tiRoot, TD_TGT_LOCK); + + TD_XCHG_CONTEXT_NO_USED(tiRoot) = TD_XCHG_CONTEXT_NO_USED(tiRoot) +1; + TI_DBG5(("ttdsaXchgGetStruct: id %d\n", ttdsaXchg->id)); + return ttdsaXchg; +} + +/* for debugging */ +osGLOBAL void +ttdsaDumpallXchg(tiRoot_t *tiRoot) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + ttdsaTgt_t *Target = (ttdsaTgt_t *)tdsaAllShared->ttdsaTgt; + ttdsaTgt_t *tmpTarget; + tdList_t *XchgList; +#ifdef TD_DEBUG_ENABLE + ttdsaXchg_t *ttdsaXchg = agNULL; +#endif + + tmpTarget = Target; + + tdsaSingleThreadedEnter(tiRoot, TD_TGT_LOCK); + if (TDLIST_EMPTY(&(tmpTarget->ttdsaXchgData.xchgFreeList))) + { + tdsaSingleThreadedLeave(tiRoot, TD_TGT_LOCK); + TI_DBG1(("ttdsaDumpallXchg: no FREE ttdsaXchgData\n")); + } + else + { + tdsaSingleThreadedLeave(tiRoot, TD_TGT_LOCK); + XchgList = tmpTarget->ttdsaXchgData.xchgFreeList.flink; + + while(XchgList != &(tmpTarget->ttdsaXchgData.xchgFreeList)) + { +#ifdef TD_DEBUG_ENABLE + ttdsaXchg = TDLIST_OBJECT_BASE(ttdsaXchg_t, XchgLinks, XchgList); +#endif + TI_DBG1(("ttdsaDumpallXchg: FREE id %d state %d\n", ttdsaXchg->id, TD_XCHG_GET_STATE(ttdsaXchg))); + XchgList = XchgList->flink; + } + } + + tdsaSingleThreadedEnter(tiRoot, TD_TGT_LOCK); + if (TDLIST_EMPTY(&(tmpTarget->ttdsaXchgData.xchgBusyList))) + { + tdsaSingleThreadedLeave(tiRoot, TD_TGT_LOCK); + TI_DBG1(("ttdsaDumpallXchg: no BUSY ttdsaXchgData\n")); + } + else + { + tdsaSingleThreadedLeave(tiRoot, TD_TGT_LOCK); + XchgList = tmpTarget->ttdsaXchgData.xchgBusyList.flink; + + while(XchgList != &(tmpTarget->ttdsaXchgData.xchgBusyList)) + { +#ifdef TD_DEBUG_ENABLE + ttdsaXchg = TDLIST_OBJECT_BASE(ttdsaXchg_t, XchgLinks, XchgList); +#endif + TI_DBG1(("ttdsaDumpallXchg: BUSY id %d state %d\n", ttdsaXchg->id, TD_XCHG_GET_STATE(ttdsaXchg))); + XchgList = XchgList->flink; + } + } + + + return; +} + + +#ifdef PASSTHROUGH + +osGLOBAL bit32 +tiTGTPassthroughCmndRegister( + tiRoot_t *tiRoot, + tiPortalContext_t *tiportalContext, + tiPassthroughProtocol_t tiProtocol, + tiPassthroughSubProtocol_t tiSubProtocol, + tiPassthroughFrameType_t tiFrameType, + ostiProcessPassthroughCmnd_t agPasthroughCB +) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + ttdsaTgt_t *Target = (ttdsaTgt_t *)tdsaAllShared->ttdsaTgt; + + TI_DBG1(("tiTGTPassthroughCmndRegister: start\n")); + /* error checking */ + if (tiProtocol != tiSASATA) + { + TI_DBG1(("tiTGTPassthroughCmndRegister: not supported protocol %d\n", tiProtocol)); + return tiError; + } + + if (tiSubProtocol != tiSSP || tiSubProtocol != tiSTP || tiSubProtocol != tiSMP) + { + TI_DBG1(("tiTGTPassthroughCmndRegister: not supported sub protocol %d\n", tiSubProtocol)); + return tiError; + } + + + if (tiFrameType == tiSMPResponse) + { + TI_DBG1(("tiTGTPassthroughCmndRegister: SMP response frametype %d\n")); + Target->PasthroughCB = agPasthroughCB; + } + + else if (tiFrameType == tiSSPPMC) + { + TI_DBG1(("tiTGTPassthroughCmndRegister: RMC response frametype %d\n")); + Target->PasthroughCB = agPasthroughCB; + } + else + { + TI_DBG1(("tiTGTPassthroughCmndRegister: not supported frametype %d\n", tiFrameType)); + return tiError; + } + + + return tiSuccess; +} + +#endif diff --git a/sys/dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdio.c b/sys/dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdio.c new file mode 100644 index 000000000000..d688e18fdeb9 --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdio.c @@ -0,0 +1,2401 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + ********************************************************************************/ +/*******************************************************************************/ +/** \file + * + * $RCSfile: ttdio.c,v $ + * + * Copyright 2006 PMC-Sierra, Inc. + * + * + * This file contains initiator IO related functions in TD layer + * + */ +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#ifdef INITIATOR_DRIVER +#include +#include +#include +#endif + +#ifdef TARGET_DRIVER +#include +#include +#include +#endif + +#include +#include + + +/* Start For trace only */ +#ifdef REMOVED +unsigned __int64 +GetHiResTimeStamp(void); +#endif +#undef TD_DEBUG_TRACE_ENABLE +#define TD_DEBUG_IO_TRACE_BUFFER_MAX 1024 + + +typedef struct TDDebugTraceEntry_s +{ + bit64 Time; + ttdsaXchg_t ttdsaXchg; + tdsaDeviceData_t oneDeviceData; +} TDDebugTraceEntry_t; + +typedef struct TDDebugTrace_s +{ + bit32 Idx; + bit32 pad; + TDDebugTraceEntry_t Data[TD_DEBUG_IO_TRACE_BUFFER_MAX]; +} TDDebugTrace_t; + +void TDTraceInit(void); +void TDTraceAdd(ttdsaXchg_t *ttdsaXchg, tdsaDeviceData_t *oneDeviceData); + +#ifdef TD_DEBUG_TRACE_ENABLE +#define TD_DEBUG_TRACE(ttdsaXchg, oneDeviceData) TDTraceAdd(ttdsaXchg, oneDeviceData) +#else +#define TD_DEBUG_TRACE(ttdsaXchg, oneDeviceData) +#endif + +TDDebugTrace_t TraceData; + +void TDTraceInit(void) +{ + osti_memset(&TraceData, 0, sizeof(TraceData)); +} + +void TDTraceAdd(ttdsaXchg_t *ttdsaXchg, tdsaDeviceData_t *oneDeviceData) +{ + static bit32 TraceIdx = 0; + + TraceData.Idx = TraceIdx; +#ifdef REMOVED + TraceData.Data[TraceIdx].Time = GetHiResTimeStamp(); +#endif + osti_memcpy((bit8 *)&(TraceData.Data[TraceIdx].ttdsaXchg), (bit8 *)ttdsaXchg, sizeof(ttdsaXchg_t)); + osti_memcpy((bit8 *)&(TraceData.Data[TraceIdx].oneDeviceData), (bit8 *)oneDeviceData, sizeof(tdsaDeviceData_t)); +#ifdef REMOVED + TraceData.Data[TraceIdx].ttdsaXchg = ttdsaXchg; + TraceData.Data[TraceIdx].oneDeviceData = oneDeviceData; +#endif + + TraceIdx++; + if (TraceIdx >= TD_DEBUG_IO_TRACE_BUFFER_MAX) + { + TraceIdx = 0; + } + + return; +} + + +/* End For trace only */ + + +osGLOBAL void +ttdsaSSPReqReceived( + agsaRoot_t *agRoot, + agsaDevHandle_t *agDevHandle, + agsaFrameHandle_t agFrameHandle, + bit32 agInitiatorTag, + bit32 parameter, + bit32 agFrameLen +) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + ttdsaXchg_t *ttdsaXchg; + /* agsaSSPCmdInfoUnit_t cmdIU; */ + tdsaDeviceData_t *oneDeviceData = agNULL; + bit32 agFrameType, TLR; + + TD_XCHG_CONTEXT_NO_CMD_RCVD(tiRoot) = TD_XCHG_CONTEXT_NO_CMD_RCVD(tiRoot)+1; + + TI_DBG4(("ttdsaSSPReqReceived: start\n")); + + agFrameType = TD_GET_FRAME_TYPE(parameter); + TLR = TD_GET_TLR(parameter); + + + /*note: + in ini, agDevHandle->osData = tdsaDeviceData_t + is set in tdssAddDevicedataToSharedcontext() + + in tdsaDeviceDataInit() + oneDeviceData->tiDeviceHandle.tdData has been initialized + */ + oneDeviceData = (tdsaDeviceData_t *)agDevHandle->osData; + + if (oneDeviceData == agNULL) + { + TI_DBG1(("ttdsaSSPReqReceived: no device data\n")); + return; + } + + + + ttdsaXchg = ttdsaXchgGetStruct(agRoot); + + if (ttdsaXchg == agNULL) + { + TI_DBG1(("ttdsaSSPReqReceived: no free xchg structures\n")); + // ttdsaDumpallXchg(tiRoot); + return; + } + + if (ttdsaXchg->IORequestBody.tiIORequest == agNULL) + { + TI_DBG1(("ttdsaSSPReqReceived: tiIORequest is NULL\n")); + // ttdsaDumpallXchg(tiRoot); + return; + } + + oneDeviceData->agDevHandle = agDevHandle; + oneDeviceData->agRoot = agRoot; + + /* saving the device */ + ttdsaXchg->DeviceData = oneDeviceData; + + ttdsaXchg->agRoot = agRoot; + ttdsaXchg->tiRoot = tiRoot; + + ttdsaXchg->IORequestBody.agIORequest.sdkData = agNULL; + + /* initiator tag */ + ttdsaXchg->tag = (bit16)agInitiatorTag; + ttdsaXchg->IORequestBody.transport.SAS.agSASRequestBody.sspTargetReq.agTag + = ttdsaXchg->tag; + ttdsaXchg->IORequestBody.transport.SAS.agSASRequestBody.sspTargetResponse.agTag + = ttdsaXchg->tag; + + TI_DBG6(("ttdsaSSPReqReceived: initiator tag 0x%x\n", agInitiatorTag)); + + if (agFrameType == OSSA_FRAME_TYPE_SSP_CMD) + { + TI_DBG4(("ttdsaSSPReqReceived: CMD frame type\n")); + /* reads agsaSSPResponseInfoUnit_t */ + saFrameReadBlock( + agRoot, + agFrameHandle, + 0, + &ttdsaXchg->agSSPCmndIU, + agFrameLen + ); + + tdsaProcessCDB(&ttdsaXchg->agSSPCmndIU, ttdsaXchg); + ttdsaXchg->FrameType = SAS_CMND; + + /* + ** As the last thing we call the disk module to handle the SCSI CDB. + ** The disk module will call tiTGTIOStart to start a data phase. + */ + + /* typedef struct + { + bit8 *reqCDB; + bit8 *scsiLun, + bit32 taskAttribute; + bi32 taskId; + bit32 crn; + } tiTargetScsiCmnd_t; + */ + /* what about reqCDB and scsiLun */ + + /* coverting task attributes from SAS TISA */ + switch (SA_SSPCMD_GET_TASKATTRIB(&ttdsaXchg->agSSPCmndIU)) + { + case 0: + ttdsaXchg->tiTgtScsiCmnd.taskAttribute = TASK_SIMPLE; + break; + case 1: + ttdsaXchg->tiTgtScsiCmnd.taskAttribute = TASK_HEAD_OF_QUEUE; + break; + case 2: + ttdsaXchg->tiTgtScsiCmnd.taskAttribute = TASK_ORDERED; + break; + case 3: + TI_DBG1(("ttdsaSSPReqReceived: reserved taskAttribute 0x%x\n",ttdsaXchg->agSSPCmndIU.efb_tp_taskAttribute)); + ttdsaXchg->tiTgtScsiCmnd.taskAttribute = TASK_SIMPLE; + break; + case 4: + ttdsaXchg->tiTgtScsiCmnd.taskAttribute = TASK_ACA; + break; + default: + TI_DBG1(("ttdsaSSPReqReceived: unknown taskAttribute 0x%x\n",ttdsaXchg->agSSPCmndIU.efb_tp_taskAttribute)); + ttdsaXchg->agSSPCmndIU.efb_tp_taskAttribute = TASK_SIMPLE; + break; + } + + ttdsaXchg->tiTgtScsiCmnd.taskId = agInitiatorTag; + ttdsaXchg->tiTgtScsiCmnd.crn = 0; + ttdsaXchg->TLR = TLR; + + /* call ostiProcessScsiReq */ + ostiProcessScsiReq( tiRoot, + &ttdsaXchg->tiTgtScsiCmnd, + agFrameHandle, + 0, + ttdsaXchg->IORequestBody.tiIORequest, + &ttdsaXchg->DeviceData->tiDeviceHandle); + + + } + else if (agFrameType == OSSA_FRAME_TYPE_SSP_TASK) + { + TI_DBG4(("ttdsaSSPReqReceived: TM frame type\n")); + + /* + reads aagsaSSPScsiTaskMgntReq_t + including lun + */ + saFrameReadBlock( + agRoot, + agFrameHandle, + 0, + &ttdsaXchg->agTMIU, + agFrameLen + ); + + ttdsaXchg->FrameType = SAS_TM; + /* + call task process mangement fn + */ + ttdsaTMProcess(tiRoot, ttdsaXchg); + return; + } + else + { + TI_DBG1(("ttdsaSSPReqReceived: unknown frame type\n")); + return; + } + + return; +} + +void +dumpCDB(bit8 *cdb) +{ + bit32 i; + for(i=0;i<10;i++) + { + TI_DBG4(("cdb[%d] 0x%x\n", i, cdb[i])); + } + return; +} + +osGLOBAL void +tdsaProcessCDB( + agsaSSPCmdInfoUnit_t *cmdIU, + ttdsaXchg_t *ttdsaXchg +) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) ttdsaXchg->tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *) &tdsaRoot->tdsaAllShared; + ttdsaTgt_t *Target = (ttdsaTgt_t *) tdsaAllShared->ttdsaTgt; + bit8 group; +#ifdef TD_DEBUG_ENABLE + CDB6_t *cdb6; +#endif + CDB10_t *cdb10; + CDB12_t *cdb12; + CDB16_t *cdb16; + bit32 unknown = agFALSE; + bit32 len=0; + group = cmdIU->cdb[0] & CDB_GRP_MASK; + + TI_DBG4(("tdsaProcessCDB: start\n")); + + switch (cmdIU->cdb[0]) + { + case SCSIOPC_REPORT_LUN: + TI_DBG4(("tdsaProcessCDB: REPORT_LUN\n")); + ttdsaXchg->XchType = AGSA_SSP_TGT_READ_DATA; + break; + case SCSIOPC_INQUIRY: + TI_DBG4(("tdsaProcessCDB: INQUIRY\n")); + ttdsaXchg->XchType = AGSA_SSP_TGT_READ_DATA; + break; + + case SCSIOPC_TEST_UNIT_READY: + TI_DBG4(("tdsaProcessCDB: TEST_UNIT_READY\n")); + ttdsaXchg->XchType = AGSA_SSP_TGT_READ_DATA; + break; + + case SCSIOPC_READ_CAPACITY_10: + case SCSIOPC_READ_CAPACITY_16: + TI_DBG4(("tdsaProcessCDB: READ CAPACITY\n")); + ttdsaXchg->XchType = AGSA_SSP_TGT_READ_DATA; + break; + + case SCSIOPC_READ_6: /* fall through */ + case SCSIOPC_READ_10: + TI_DBG4(("tdsaProcessCDB: READ\n")); + ttdsaXchg->XchType = AGSA_SSP_TGT_READ_DATA; + break; + + case SCSIOPC_WRITE_6: /* fall through */ + case SCSIOPC_WRITE_10: + TI_DBG4(("tdsaProcessCDB: WRITE\n")); + ttdsaXchg->XchType = AGSA_SSP_TGT_WRITE_DATA; + break; + + case SCSIOPC_MODE_SENSE_6: /* fall through */ + case SCSIOPC_MODE_SENSE_10: + TI_DBG4(("tdsaProcessCDB: MODE SENSE\n")); + ttdsaXchg->XchType = AGSA_SSP_TGT_READ_DATA; + break; + case SCSIOPC_SYNCHRONIZE_CACHE_10: + TI_DBG4(("tdsaProcessCDB: SCSIOPC_SYNCHRONIZE_CACHE_10\n")); + ttdsaXchg->XchType = AGSA_SSP_TGT_CMD_OR_TASK_RSP; + break; + case SCSIOPC_REQUEST_SENSE: + TI_DBG2(("tdsaProcessCDB: SCSIOPC_REQUEST_SENSE\n")); + ttdsaXchg->XchType = AGSA_SSP_TGT_READ_DATA; + break; + default: + TI_DBG4(("tdsaProcessCDB: UNKNOWN, cbd %d 0x%x\n", cmdIU->cdb[0], cmdIU->cdb[0])); + ttdsaXchg->XchType = TargetUnknown; + break; + } + + /* parse datalen */ + switch (group) + { + case CDB_6BYTE: + TI_DBG4(("tdsaProcessCDB: CDB 6 byte, not yet\n")); +#ifdef TD_DEBUG_ENABLE + cdb6 = (CDB6_t *)(cmdIU->cdb); +#endif + TI_DBG4(("tdsaProcessCDB: CDB len 0x%x\n", cdb6->len)); + break; + case CDB_10BYTE1: /* fall through */ + case CDB_10BYTE2: + TI_DBG4(("tdsaProcessCDB: CDB 10 byte\n")); + cdb10 = (CDB10_t *)(cmdIU->cdb); + OSSA_READ_BE_16(AGROOT, &len, cdb10->len, 0); + TI_DBG4(("tdsaProcessCDB: CDB len 0x%x\n", len)); + dumpCDB(cmdIU->cdb); + break; + case CDB_12BYTE: + TI_DBG4(("tdsaProcessCDB: CDB 12 byte, not yet\n")); + cdb12 = (CDB12_t *)(cmdIU->cdb); + OSSA_READ_BE_32(AGROOT, &len, cdb12->len, 0); + TI_DBG4(("tdsaProcessCDB: CDB len 0x%x\n", len)); + break; + case CDB_16BYTE: + TI_DBG4(("tdsaProcessCDB: CDB 16 byte, not yet\n")); + cdb16 = (CDB16_t *)(cmdIU->cdb); + OSSA_READ_BE_32(AGROOT, &len, cdb16->len, 0); + TI_DBG4(("tdsaProcessCDB: CDB len 0x%x\n", len)); + break; + default: + TI_DBG4(("tdsaProcessCDB: unknow CDB, group %d 0x%x\n", group, group)); + len = 0; + unknown = agTRUE; + break; + } + if (cmdIU->cdb[0] == SCSIOPC_READ_6 || cmdIU->cdb[0] == SCSIOPC_READ_10 || + cmdIU->cdb[0] == SCSIOPC_WRITE_6 || cmdIU->cdb[0] == SCSIOPC_WRITE_10 ) + { + ttdsaXchg->dataLen = len * Target->OperatingOption.BlockSize; + } + else + { + ttdsaXchg->dataLen = len; + } + + if (ttdsaXchg->dataLen == 0 && unknown == agFALSE) + { + /* this is needed because of min operation in tiTGTIOstart() */ + ttdsaXchg->dataLen = 0xffffffff; + } + /* TI_DBG4(("tdsaProcessCDB: datalen 0x%x %d\n", ttdsaXchg->dataLen, ttdsaXchg->dataLen)); */ + return; +} + + + + +/***************************************************************************** + * + * tiTGTIOStart + * + * Purpose: This function is called by the target OS Specific Module to start + * the next phase of a SCSI Request. + * + * Parameters: + * tiRoot: Pointer to driver Instance. + * tiIORequest: Pointer to the I/O request context for this I/O. + * This context was initially passed to the OS Specific Module + * in ostiProcessScsiReq(). + * dataOffset: Offset into the buffer space for this phase. + * dataLength: Length of data to move for this phase. + * dataSGL: Length/Address pair of where the data is. The SGL list is + * allocated and initialized by the OS Specific module. + * sglVirtualAddr: The virtual address of the first element in agSgl1 when + * agSgl1 is used with the type tiSglList. + * This field is needed for the TD Layer. + * + * Return: + * tiSuccess: I/O request successfully initiated. + * tiBusy: No resources available, try again later. + * tiError: Other errors that prevent the I/O request to be started. + * + * Note: + * + *****************************************************************************/ +osGLOBAL bit32 +tiTGTIOStart( tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + bit32 dataOffset, + bit32 dataLength, + tiSgl_t *dataSGL, + void *sglVirtualAddr +) + +{ + ttdsaXchg_t *ttdsaXchg; + agsaSSPTargetRequest_t *agSSPTargetReq; + bit32 tiStatus; + bit32 saStatus; + bit32 tdStatus; + tdsaPortContext_t *onePortContext = agNULL; + tdsaDeviceData_t *oneDeviceData = agNULL; + + TI_DBG4(("tiTGTIOStart: start\n")); + TI_DBG4(("tiTGTIOStart: dataLength 0x%x %d\n", dataLength, dataLength)); + TI_DBG4(("tiTGTIOStart: dataOffset 0x%x %d\n", dataOffset, dataOffset)); + + /* save infor in ttdsaXchg */ + ttdsaXchg = (ttdsaXchg_t *)tiIORequest->tdData; + + /* check the state of port */ + oneDeviceData = ttdsaXchg->DeviceData; + onePortContext= oneDeviceData->tdPortContext; + if (onePortContext->valid == agFALSE) + { + TI_DBG1(("tiTGTIOStart: portcontext pid %d is invalid\n", onePortContext->id)); + return tiError; + } + + + agSSPTargetReq + = &(ttdsaXchg->IORequestBody.transport.SAS.agSASRequestBody.sspTargetReq); + + /* fills in agsaSASRequestBody_t.agsaSSPTargetRequest_t */ + agSSPTargetReq->dataLength = (bit32) MIN(dataLength, ttdsaXchg->dataLen); + agSSPTargetReq->offset = dataOffset; + agSSPTargetReq->agTag = ttdsaXchg->tag; + /* SSPTargetReq->agTag has been set in ttdsaSSPReqReceived() */ + + /* Process TLR */ + if (ttdsaXchg->TLR == 2) + { + /* diable TLR */ + agSSPTargetReq->sspOption = 0; + } + else + { + /* enable TLR */ + /* bit5: 0 1 11 11 :bit0 */ + agSSPTargetReq->sspOption = 0x1F; + } + + ttdsaXchg->IORequestBody.IOType.TargetIO.TargetIOType.RegIO.sglVirtualAddr + = sglVirtualAddr; + + if (agSSPTargetReq->dataLength != 0) + { + TI_DBG6(("tiTGTIOStart: pos 1\n")); + ttdsaXchg->IORequestBody.IOType.TargetIO.TargetIOType.RegIO.tiSgl1 + = *dataSGL; + } + else + { + TI_DBG6(("tiTGTIOStart: pos 2\n")); + ttdsaXchg->IORequestBody.IOType.TargetIO.TargetIOType.RegIO.tiSgl1.len + = 0; + ttdsaXchg->IORequestBody.IOType.TargetIO.TargetIOType.RegIO.tiSgl1.type + = tiSgl; + + /* let's send response frame */ + if (ttdsaXchg->resp.length != 0) + { + /* senselen != 0, send respsonse */ + TI_DBG4(("tiTGTIOStart: send respsonse\n")); + TI_DBG4(("tiTGTIOStart: resp.length 0x%x\n", + ttdsaXchg->resp.length)); + ttdsaXchg->responseSent = agTRUE; + ttdsaXchg->DeviceData->IOResponse++; + TD_DEBUG_TRACE(ttdsaXchg, ttdsaXchg->DeviceData); + tdStatus = ttdsaSendResp(ttdsaXchg->agRoot, ttdsaXchg); + if (tdStatus == AGSA_RC_SUCCESS) + { + return tiSuccess; + } + else if (tdStatus == AGSA_RC_FAILURE) + { + TI_DBG1(("tiTGTIOStart: (ttdsaSendResp) sending not successful\n")); + return tiError; + } + else + { + TI_DBG1(("tiTGTIOStart: (ttdsaSendResp) sending busy\n")); + return tiBusy; + } + } + } + + + /* sets SSPTargetReq->agSgl */ + tiStatus = ttdssIOPrepareSGL(tiRoot, &ttdsaXchg->IORequestBody, dataSGL, NULL, sglVirtualAddr); + + if (tiStatus != tiSuccess) + { + TI_DBG1(("tiTGTIOStart: ttdIOPrepareSGL did not return success\n")); + return tiStatus; + } + + TI_DBG4(("tiTGTIOStart: agroot %p ttdsaXchg %p\n", ttdsaXchg->agRoot, ttdsaXchg)); + TI_DBG4(("tiTGTIOStart: agDevHanlde %p\n", ttdsaXchg->DeviceData->agDevHandle)); + + if ( (ttdsaXchg->readRspCollapsed == agTRUE) || (ttdsaXchg->wrtRspCollapsed == agTRUE) ) + { + /* collapse good response with read */ + TI_DBG4(("tiTGTIOStart: read rsp collapse\n")); + TI_DBG4(("tiTGTIOStart: initiator tag 0x%x\n", ttdsaXchg->tag)); + + TD_XCHG_CONTEXT_NO_START_IO(tiRoot) = TD_XCHG_CONTEXT_NO_START_IO(tiRoot)+1; + ttdsaXchg->DeviceData->IOStart++; + TD_DEBUG_TRACE(ttdsaXchg, ttdsaXchg->DeviceData); + saStatus = saSSPStart( + ttdsaXchg->agRoot, + &ttdsaXchg->IORequestBody.agIORequest, + tdsaRotateQnumber(tiRoot, oneDeviceData), + ttdsaXchg->DeviceData->agDevHandle, + ttdsaXchg->readRspCollapsed ? AGSA_SSP_TGT_READ_GOOD_RESP : AGSA_SSP_TGT_WRITE_GOOD_RESP, + &ttdsaXchg->IORequestBody.transport.SAS.agSASRequestBody, + agNULL, + &ossaSSPCompleted + ); + } + else + { + TI_DBG4(("tiTGTIOStart: normal\n")); + TI_DBG4(("tiTGTIOStart: initiator tag 0x%x\n", ttdsaXchg->tag)); + TD_XCHG_CONTEXT_NO_START_IO(tiRoot) = TD_XCHG_CONTEXT_NO_START_IO(tiRoot)+1; + ttdsaXchg->DeviceData->IOStart++; + TD_DEBUG_TRACE(ttdsaXchg, ttdsaXchg->DeviceData); + saStatus = saSSPStart( + ttdsaXchg->agRoot, /* agRoot, */ + &ttdsaXchg->IORequestBody.agIORequest, + tdsaRotateQnumber(tiRoot, oneDeviceData), + ttdsaXchg->DeviceData->agDevHandle, + ttdsaXchg->XchType, + &ttdsaXchg->IORequestBody.transport.SAS.agSASRequestBody, + agNULL, + &ossaSSPCompleted + ); + + } + + if (saStatus == AGSA_RC_SUCCESS) + { + return tiSuccess; + } + else if (saStatus == AGSA_RC_FAILURE) + { + TI_DBG1(("tiTGTIOStart: sending not successful\n")); + return tiError; + } + else + { + TI_DBG1(("tiTGTIOStart: sending busy\n")); + return tiBusy; + } + +} + +#ifdef EDC_ENABLE +/***************************************************************************** + * + * tiTGTIOStart + * + * Purpose: This function is called by the target OS Specific Module to start + * the next phase of a SCSI Request. + * + * Parameters: + * tiRoot: Pointer to driver Instance. + * tiIORequest: Pointer to the I/O request context for this I/O. + * This context was initially passed to the OS Specific Module + * in ostiProcessScsiReq(). + * dataOffset: Offset into the buffer space for this phase. + * dataLength: Length of data to move for this phase. + * dataSGL: Length/Address pair of where the data is. The SGL list is + * allocated and initialized by the OS Specific module. + * sglVirtualAddr: The virtual address of the first element in agSgl1 when + * agSgl1 is used with the type tiSglList. + * This field is needed for the TD Layer. + * difOption: DIF option. + * + * Return: + * tiSuccess: I/O request successfully initiated. + * tiBusy: No resources available, try again later. + * tiError: Other errors that prevent the I/O request to be started. + * + * Note: + * + *****************************************************************************/ +osGLOBAL bit32 tiTGTIOStartDif( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + bit32 dataOffset, + bit32 dataLength, + tiSgl_t *dataSGL, + void *sglVirtualAddr, + tiDif_t *difOption +) +{ + + /* This function was never used by SAS/SATA. Use tiTGTSuperIOStart() instead. */ + return tiBusy; +} +#endif + +osGLOBAL bit32 +ttdssIOPrepareSGL( + tiRoot_t *tiRoot, + tdIORequestBody_t *tdIORequestBody, + tiSgl_t *tiSgl1, + tiSgl_t *tiSgl2, + void *sglVirtualAddr +) +{ + agsaSgl_t *agSgl; + + TI_DBG6(("ttdssIOPrepareSGL: start\n")); + + agSgl = &(tdIORequestBody->transport.SAS.agSASRequestBody.sspTargetReq.agSgl); + + agSgl->len = 0; + + if (tiSgl1 == agNULL) + { + TI_DBG1(("ttdssIOPrepareSGL: Error tiSgl1 is NULL\n")); + return tiError; + } + + agSgl->sgUpper = tiSgl1->upper; + agSgl->sgLower = tiSgl1->lower; + agSgl->len = tiSgl1->len; + agSgl->extReserved = tiSgl1->type; + + return tiSuccess; +} + +/* temp for debugging */ +void +dumpresp(bit8 *resp, bit32 len) +{ + bit32 i; + + for(i=0;iosData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaDeviceData_t *oneDeviceData = agNULL; + bit32 agRequestType; + bit32 saStatus; + agsaSSPTargetResponse_t *agSSPTargetResp; + agRequestType = AGSA_SSP_TGT_CMD_OR_TASK_RSP; + + TI_DBG4(("ttdsaSendResp: start\n")); + TI_DBG4(("ttdsaSendResp: agroot %p ttdsaXchg %p\n", ttdsaXchg->agRoot, ttdsaXchg)); + + TI_DBG4(("ttdsaSendResp:: agDevHanlde %p\n", ttdsaXchg->DeviceData->agDevHandle)); + + /* sas response */ + TI_DBG4(("ttdsaSendResp: len 0x%x \n", + ttdsaXchg->resp.length)); + TI_DBG4(("ttdsaSendResp: upper 0x%x \n", + ttdsaXchg->resp.phyAddrUpper)); + TI_DBG4(("ttdsaSendResp: lower 0x%x \n", + ttdsaXchg->resp.phyAddrLower)); + TI_DBG4(("ttdsaSendResp: initiator tag 0x%x\n", ttdsaXchg->tag)); + + agSSPTargetResp = &(ttdsaXchg->IORequestBody.transport.SAS.agSASRequestBody.sspTargetResponse); + agSSPTargetResp->agTag = ttdsaXchg->tag; + agSSPTargetResp->respBufLength = ttdsaXchg->resp.length; + agSSPTargetResp->respBufUpper = ttdsaXchg->resp.phyAddrUpper; + agSSPTargetResp->respBufLower = ttdsaXchg->resp.phyAddrLower; + agSSPTargetResp->respOption = 3; /* Retry on both ACK/NAK timeout and NAK received */ + /* temporary solution for T2D Combo*/ +#if defined (INITIATOR_DRIVER) && defined (TARGET_DRIVER) + /* nothing */ +#else + if (agSSPTargetResp->respBufLength <= AGSA_MAX_SSPPAYLOAD_VIA_SFO) + agSSPTargetResp->frameBuf = ttdsaXchg->resp.virtAddr; + else + agSSPTargetResp->frameBuf = NULL; +#endif + dumpresp((bit8 *)ttdsaXchg->resp.virtAddr, ttdsaXchg->resp.length); + + TD_XCHG_CONTEXT_NO_SEND_RSP(TD_GET_TIROOT(agRoot)) = + TD_XCHG_CONTEXT_NO_SEND_RSP(TD_GET_TIROOT(agRoot))+1; + + oneDeviceData = ttdsaXchg->DeviceData; + saStatus = saSSPStart( + ttdsaXchg->agRoot, /* agRoot,*/ + &ttdsaXchg->IORequestBody.agIORequest, + tdsaRotateQnumber(tiRoot, oneDeviceData), + ttdsaXchg->DeviceData->agDevHandle, /* agDevHandle, */ + agRequestType, + &ttdsaXchg->IORequestBody.transport.SAS.agSASRequestBody, + agNULL, + &ossaSSPCompleted + ); + + if (saStatus == AGSA_RC_SUCCESS) + { + TI_DBG4(("ttdsaSendResp: sending successful\n")); + return AGSA_RC_SUCCESS; + } + else if (saStatus == AGSA_RC_FAILURE) + { + TI_DBG1(("ttdsaSendResp: sending not successful\n")); + return AGSA_RC_FAILURE; + } + else + { + TI_DBG1(("ttdsaSendResp: sending busy\n")); + return AGSA_RC_BUSY; + } + +} + +osGLOBAL void +ttdsaIOCompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + bit32 agOtherInfo +) +{ + + ttdsaXchg_t *ttdsaXchg = (ttdsaXchg_t *)agIORequest->osData; + /* done in ttdsaXchgInit() */ + bit32 IOFailed = agFALSE; + bit32 status; + bit32 statusDetail = 0; + tiRoot_t *tiRoot; +#ifdef REMOVED + tdsaRoot_t *tdsaRoot; + tdsaContext_t *tdsaAllShared; +#endif + bit32 tdStatus; + bit32 saStatus = AGSA_RC_FAILURE; +#ifdef TD_DEBUG_ENABLE + agsaDifDetails_t *DifDetail; +#endif + + TI_DBG4(("ttdsaIOCompleted: start\n")); + tiRoot = ((tdsaRootOsData_t *)agRoot->osData)->tiRoot; +#ifdef REMOVED + tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; +#endif +#ifdef TD_DEBUG_ENABLE + DifDetail = (agsaDifDetails_t *)agFrameHandle; +#endif + + if (tiRoot == agNULL) + { + TI_DBG1(("ttdsaIOCompleted: tiRoot is NULL\n")); + return; + } + + TD_XCHG_CONTEXT_NO_IO_COMPLETED(tiRoot) = TD_XCHG_CONTEXT_NO_IO_COMPLETED(tiRoot)+1; + + if(TD_XCHG_GET_STATE(ttdsaXchg) != TD_XCHG_STATE_ACTIVE) + { + TI_DBG1(("ttdsaIOCompleted: XCHG is not active *****************\n")); + return; + } + + if (ttdsaXchg->isTMRequest != agTRUE) + { + TI_DBG6(("ttdsaIOCompleted: COMMAND \n")); + TI_DBG6(("ttdsaIOCompleted: ttdsaXchg %p\n", ttdsaXchg)); + TI_DBG6(("ttdsaIOCompleted: ttdsaXchg->IORequestBody.EsglPageList %p\n", &ttdsaXchg->IORequestBody.EsglPageList)); + TI_DBG6(("ttdsaIOCompleted: command initiator tag 0x%x\n", ttdsaXchg->tag)); + +#ifdef REMOVED + /* call tdsafreeesglpages only for xchg that used eslg */ + if (ttdsaXchg->usedEsgl == agTRUE) + { + tdsaFreeEsglPages(tiRoot, &ttdsaXchg->IORequestBody.EsglPageList); + ttdsaXchg->usedEsgl = agFALSE; + } +#endif + + /* successful case */ + if (agIOStatus == OSSA_IO_SUCCESS) + { + TI_DBG6(("ttdsaIOCompleted: osIOSuccess\n")); + if ( (ttdsaXchg->readRspCollapsed == agTRUE) || (ttdsaXchg->wrtRspCollapsed == agTRUE) ) + { + ttdsaXchg->responseSent = agTRUE; + TI_DBG4(("ttdsaIOCompleted: read rsp collapse\n")); + } + + if (ttdsaXchg->statusSent == agTRUE) + { + /* + the response has already been set and ready + but has NOT been sent + */ + if (ttdsaXchg->responseSent == agFALSE) + { + /* let's send the response for IO */ + TI_DBG6(("ttdsaIOCompleted: sending response\n")); + TD_DEBUG_TRACE(ttdsaXchg, ttdsaXchg->DeviceData); + tdStatus = ttdsaSendResp(agRoot, ttdsaXchg); + if (tdStatus != AGSA_RC_SUCCESS) + { + TI_DBG1(("ttdsaIOCompleted: attention needed\n")); + return; + } + ttdsaXchg->responseSent = agTRUE; + } + else + { + TI_DBG4(("ttdsaIOCompleted: read rsp collapse and complete \n")); + /* the response has been sent */ + TI_DBG6(("ttdsaIOCompleted: already sent response, notify OS\n")); + + if (TD_XCHG_GET_STATE(ttdsaXchg) == TD_XCHG_STATE_INACTIVE) + { + TI_DBG1(("ttdsaIOCompleted: wrong DEQUEUE_THIS\n")); + } + + /* + * Notify the OS Specific Module, so it can free its resource. + */ + TI_DBG4(("ttdsaIOCompleted: calling ostiTargetIOCompleted\n")); + ostiTargetIOCompleted( tiRoot, + ttdsaXchg->IORequestBody.tiIORequest, + tiIOSuccess ); + + /* clean up resources */ + ttdsaXchgFreeStruct(tiRoot,ttdsaXchg); + } + } /* sent */ + else + { + TI_DBG4(("ttdsaIOCompleted: osIOSuccess: nextphase\n")); + /* the response has not been set; still in data phase */ + /* we need to tell the disk module to start the next phase */ + ostiNextDataPhase(ttdsaXchg->tiRoot, + ttdsaXchg->IORequestBody.tiIORequest ); + } + return; + } /* success */ + + /* handle error cases */ + if (agIOStatus == OSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH || agIOStatus == OSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH + || agIOStatus == OSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH) + { + TI_DBG1(("ttdsaIOCompleted: DIF detail UpperLBA 0x%08x LowerLBA 0x%08x\n", DifDetail->UpperLBA, DifDetail->LowerLBA)); + } + switch (agIOStatus) + { + case OSSA_IO_ABORTED: + TI_DBG1(("ttdsaIOCompleted: ABORTED\n")); + status = tiIOFailed; + statusDetail = tiDetailAborted; + IOFailed = agTRUE; + break; +#ifdef REMOVED + case OSSA_IO_OVERFLOW: + TI_DBG1(("ttdsaIOCompleted: OVERFLOW\n")); + status = tiIOOverRun; + IOFailed = agTRUE; + break; +#endif + case OSSA_IO_UNDERFLOW: + TI_DBG1(("ttdsaIOCompleted: UNDERFLOW\n")); + status = tiIOUnderRun; + IOFailed = agTRUE; + break; + case OSSA_IO_ABORT_RESET: + TI_DBG1(("ttdsaIOCompleted: ABORT_RESET\n")); + status = tiIOFailed; + statusDetail = tiDetailAbortReset; + IOFailed = agTRUE; + break; + case OSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS: + TI_DBG1(("ttdsaIOCompleted: OSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS\n")); + status = tiIOEncryptError; + statusDetail = tiDetailDekKeyCacheMiss; + IOFailed = agTRUE; + break; + case OSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH: + TI_DBG1(("ttdsaIOCompleted: OSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH\n")); + status = tiIOEncryptError; + statusDetail = tiDetailDekKeyCacheMiss; + IOFailed = agTRUE; + break; + case OSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH: + TI_DBG1(("ttdsaIOCompleted: OSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH\n")); + status = tiIODifError; + statusDetail = tiDetailDifAppTagMismatch; + IOFailed = agTRUE; + break; + case OSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH: + TI_DBG1(("ttdsaIOCompleted: OSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH\n")); + status = tiIODifError; + statusDetail = tiDetailDifRefTagMismatch; + IOFailed = agTRUE; + break; + case OSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH: + TI_DBG1(("ttdsaIOCompleted: OSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH\n")); + status = tiIODifError; + statusDetail = tiDetailDifCrcMismatch; + IOFailed = agTRUE; + break; + case OSSA_IO_FAILED: /* fall through */ + case OSSA_IO_NO_DEVICE: /* fall through */ + //case OSSA_IO_NO_SUPPORT: /* fall through */ /*added to compile tgt_drv (TP)*/ + case OSSA_IO_LINK_FAILURE: /* fall through */ + case OSSA_IO_PROG_ERROR: /* fall through */ + case OSSA_IO_DS_NON_OPERATIONAL: /* fall through */ + case OSSA_IO_DS_IN_RECOVERY: /* fall through */ + case OSSA_IO_TM_TAG_NOT_FOUND: /* fall through */ + case OSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE: /* fall through */ + default: + status = tiIOFailed; + statusDetail = tiDetailOtherError; + IOFailed = agTRUE; + TI_DBG1(("ttdsaIOCompleted: Fail!!!!!!! agIOStatus=0x%x agIOInfoLen=0x%x agOtherInfo=0x%x\n", agIOStatus, agIOInfoLen, agOtherInfo)); + // ttdsaDumpallXchg(tiRoot); + if (agIOStatus == OSSA_IO_XFER_OPEN_RETRY_TIMEOUT) + { + TI_DBG1(("ttdsaIOCompleted: OSSA_IO_XFER_OPEN_RETRY_TIMEOUT ttdsaXchg->id 0x%x datalen 0x%x offset 0x%x agTag 0x%x\n", + ttdsaXchg->id, + ttdsaXchg->IORequestBody.transport.SAS.agSASRequestBody.sspTargetReq.dataLength, + ttdsaXchg->IORequestBody.transport.SAS.agSASRequestBody.sspTargetReq.offset, + ttdsaXchg->IORequestBody.transport.SAS.agSASRequestBody.sspTargetReq.agTag)); + TI_DBG1(("ttdsaIOCompleted: statusSent %d responseSent %d\n", ttdsaXchg->statusSent, ttdsaXchg->responseSent)); + + } + break; + } /* switch */ + + if (IOFailed == agTRUE) + { + if (agIORequest->sdkData == agNULL) + { + tiIORequest_t tiIORequest; + TI_DBG1(("ttdsaIOCompleted: ERROR ttdsaXchg=%p agIOStatus= 0x%x\n", + ttdsaXchg, + agIOStatus )); + TI_DBG1(("CDB= 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", + ttdsaXchg->agSSPCmndIU.cdb[0], + ttdsaXchg->agSSPCmndIU.cdb[1], + ttdsaXchg->agSSPCmndIU.cdb[2], + ttdsaXchg->agSSPCmndIU.cdb[3], + ttdsaXchg->agSSPCmndIU.cdb[4], + ttdsaXchg->agSSPCmndIU.cdb[5], + ttdsaXchg->agSSPCmndIU.cdb[6], + ttdsaXchg->agSSPCmndIU.cdb[7], + ttdsaXchg->agSSPCmndIU.cdb[8], + ttdsaXchg->agSSPCmndIU.cdb[9], + ttdsaXchg->agSSPCmndIU.cdb[10], + ttdsaXchg->agSSPCmndIU.cdb[11], + ttdsaXchg->agSSPCmndIU.cdb[12], + ttdsaXchg->agSSPCmndIU.cdb[13], + ttdsaXchg->agSSPCmndIU.cdb[14], + ttdsaXchg->agSSPCmndIU.cdb[15] )); + + if (TD_XCHG_GET_STATE(ttdsaXchg) == TD_XCHG_STATE_INACTIVE) + { + TI_DBG1(("ttdsaIOCompleted: wrong DEQUEUE_THIS 1\n")); + } + if (ttdsaXchg->retries <= OPEN_RETRY_RETRIES && agIOStatus == OSSA_IO_XFER_OPEN_RETRY_TIMEOUT) + { + TI_DBG2(("ttdsaIOCompleted: 1 loc retries on OSSA_IO_XFER_OPEN_RETRY_TIMEOUT\n")); + if ( (agOtherInfo & 0x1) == 1) + { + /* repsonse phase */ + TI_DBG2(("ttdsaIOCompleted: 0 loc response retry\n")); + /* repsonse retry */ + saStatus = ttdsaSendResp(ttdsaXchg->agRoot, ttdsaXchg); + if (saStatus == AGSA_RC_SUCCESS) + { + TI_DBG2(("ttdsaIOCompleted: 0 loc retried\n")); + ttdsaXchg->retries++; + } + else + { + TI_DBG1(("ttdsaIOCompleted: 0 loc retry failed\n")); + ttdsaXchg->retries = 0; + /* + * because we are freeing up the exchange + * we must let the oslayer know that + * we are releasing the resources by + * setting the tdData to NULL + */ + tiIORequest = ttdsaXchg->IORequestBody.IOType.TargetIO.tiIORequest; + tiIORequest.tdData = agNULL; + + ostiTargetIOError( + tiRoot, + &tiIORequest, + status, + statusDetail + ); + + /* clean up resources */ + ttdsaXchgFreeStruct(tiRoot,ttdsaXchg); + } + } + else if ( (ttdsaXchg->readRspCollapsed == agTRUE) || (ttdsaXchg->wrtRspCollapsed == agTRUE) ) + { + saStatus = saSSPStart( + ttdsaXchg->agRoot, /* agRoot, */ + &ttdsaXchg->IORequestBody.agIORequest, + 0, + ttdsaXchg->DeviceData->agDevHandle, /* agDevHandle, */ + ttdsaXchg->readRspCollapsed ? AGSA_SSP_TGT_READ_GOOD_RESP : AGSA_SSP_TGT_WRITE_GOOD_RESP, + &ttdsaXchg->IORequestBody.transport.SAS.agSASRequestBody, + agNULL, + &ossaSSPCompleted + ); + if (saStatus == AGSA_RC_SUCCESS) + { + TI_DBG1(("ttdsaIOCompleted: 1 loc retried\n")); + ttdsaXchg->retries++; + } + else + { + TI_DBG1(("ttdsaIOCompleted: 1 loc retry failed\n")); + ttdsaXchg->retries = 0; + /* + * because we are freeing up the exchange + * we must let the oslayer know that + * we are releasing the resources by + * setting the tdData to NULL + */ + tiIORequest = ttdsaXchg->IORequestBody.IOType.TargetIO.tiIORequest; + tiIORequest.tdData = agNULL; + + ostiTargetIOError( + tiRoot, + &tiIORequest, + status, + statusDetail + ); + + /* clean up resources */ + ttdsaXchgFreeStruct(tiRoot,ttdsaXchg); + } + } + else + { + if (ttdsaXchg->responseSent == agFALSE) + { + saStatus = saSSPStart( + ttdsaXchg->agRoot, /* agRoot, */ + &ttdsaXchg->IORequestBody.agIORequest, /*agIORequest, */ + 0, /* queue number */ + ttdsaXchg->DeviceData->agDevHandle, /* agDevHandle, */ + ttdsaXchg->XchType, + &ttdsaXchg->IORequestBody.transport.SAS.agSASRequestBody, + agNULL, + &ossaSSPCompleted + ); + } + else + { + /* repsonse retry */ + TI_DBG1(("ttdsaIOCompleted: 2 loc reponse retry\n")); + saStatus = ttdsaSendResp(ttdsaXchg->agRoot, ttdsaXchg); + } + if (saStatus == AGSA_RC_SUCCESS) + { + TI_DBG1(("ttdsaIOCompleted: 2 loc retried\n")); + ttdsaXchg->retries++; + } + else + { + TI_DBG1(("ttdsaIOCompleted: 2 loc retry failed\n")); + ttdsaXchg->retries = 0; + /* + * because we are freeing up the exchange + * we must let the oslayer know that + * we are releasing the resources by + * setting the tdData to NULL + */ + tiIORequest = ttdsaXchg->IORequestBody.IOType.TargetIO.tiIORequest; + tiIORequest.tdData = agNULL; + + ostiTargetIOError( + tiRoot, + &tiIORequest, + status, + statusDetail + ); + + /* clean up resources */ + ttdsaXchgFreeStruct(tiRoot,ttdsaXchg); + } + } + } + else + { + ttdsaXchg->retries = 0; + /* + * because we are freeing up the exchange + * we must let the oslayer know that + * we are releasing the resources by + * setting the tdData to NULL + */ + tiIORequest = ttdsaXchg->IORequestBody.IOType.TargetIO.tiIORequest; + tiIORequest.tdData = agNULL; + + ostiTargetIOError( + tiRoot, + &tiIORequest, + status, + statusDetail + ); + + /* clean up resources */ + ttdsaXchgFreeStruct(tiRoot,ttdsaXchg); + } + } /* saData == agNULL */ + else + { + tiIORequest_t tiIORequest; + + TI_DBG1(("ttdsaIOCompleted: 2\n")); + if (TD_XCHG_GET_STATE(ttdsaXchg) == TD_XCHG_STATE_INACTIVE) + { + TI_DBG1(("ttdsaIOCompleted: wrong DEQUEUE_THIS 2\n")); + } + if (ttdsaXchg->retries <= OPEN_RETRY_RETRIES && agIOStatus == OSSA_IO_XFER_OPEN_RETRY_TIMEOUT) + { + TI_DBG1(("ttdsaIOCompleted: 2 loc retries on OSSA_IO_XFER_OPEN_RETRY_TIMEOUT\n")); + if ( (agOtherInfo & 0x1) == 1) + { + /* repsonse phase */ + TI_DBG2(("ttdsaIOCompleted: 0 loc response retry\n")); + /* repsonse retry */ + saStatus = ttdsaSendResp(ttdsaXchg->agRoot, ttdsaXchg); + if (saStatus == AGSA_RC_SUCCESS) + { + TI_DBG2(("ttdsaIOCompleted: 0 loc retried\n")); + ttdsaXchg->retries++; + } + else + { + TI_DBG1(("ttdsaIOCompleted: 0 loc retry failed\n")); + ttdsaXchg->retries = 0; + /* + * because we are freeing up the exchange + * we must let the oslayer know that + * we are releasing the resources by + * setting the tdData to NULL + */ + tiIORequest = ttdsaXchg->IORequestBody.IOType.TargetIO.tiIORequest; + tiIORequest.tdData = agNULL; + + ostiTargetIOError( + tiRoot, + &tiIORequest, + status, + statusDetail + ); + + /* clean up resources */ + ttdsaXchgFreeStruct(tiRoot,ttdsaXchg); + } + } + else if ( (ttdsaXchg->readRspCollapsed == agTRUE) || (ttdsaXchg->wrtRspCollapsed == agTRUE) ) + { + saStatus = saSSPStart( + ttdsaXchg->agRoot, /* agRoot, */ + &ttdsaXchg->IORequestBody.agIORequest, /* agIORequest, */ + 0, /* queue number */ + ttdsaXchg->DeviceData->agDevHandle, /* agDevHandle, */ + ttdsaXchg->readRspCollapsed ? AGSA_SSP_TGT_READ_GOOD_RESP : AGSA_SSP_TGT_WRITE_GOOD_RESP, + &ttdsaXchg->IORequestBody.transport.SAS.agSASRequestBody, + agNULL, + &ossaSSPCompleted + ); + if (saStatus == AGSA_RC_SUCCESS) + { + TI_DBG1(("ttdsaIOCompleted: 1 loc retried\n")); + ttdsaXchg->retries++; + } + else + { + TI_DBG1(("ttdsaIOCompleted: 1 loc retry failed\n")); + ttdsaXchg->retries = 0; + /* + * because we are freeing up the exchange + * we must let the oslayer know that + * we are releasing the resources by + * setting the tdData to NULL + */ + tiIORequest = ttdsaXchg->IORequestBody.IOType.TargetIO.tiIORequest; + tiIORequest.tdData = agNULL; + + ostiTargetIOError( + tiRoot, + &tiIORequest, + status, + statusDetail + ); + + /* clean up resources */ + ttdsaXchgFreeStruct(tiRoot,ttdsaXchg); + } + } + else + { + TI_DBG1(("ttdsaIOCompleted: 2 loc ttdsaXchg->id 0x%x datalen 0x%x offset 0x%x agTag 0x%x\n", + ttdsaXchg->id, + ttdsaXchg->IORequestBody.transport.SAS.agSASRequestBody.sspTargetReq.dataLength, + ttdsaXchg->IORequestBody.transport.SAS.agSASRequestBody.sspTargetReq.offset, + ttdsaXchg->IORequestBody.transport.SAS.agSASRequestBody.sspTargetReq.agTag)); + if (ttdsaXchg->responseSent == agFALSE) + { + saStatus = saSSPStart( + ttdsaXchg->agRoot, /* agRoot, */ + &ttdsaXchg->IORequestBody.agIORequest, /* agIORequest, */ + 0, /* queue number */ + ttdsaXchg->DeviceData->agDevHandle, /* agDevHandle, */ + ttdsaXchg->XchType, + &ttdsaXchg->IORequestBody.transport.SAS.agSASRequestBody, + agNULL, + &ossaSSPCompleted + ); + } + else + { + TI_DBG1(("ttdsaIOCompleted: 2 loc response retry\n")); + /* repsonse retry */ + saStatus = ttdsaSendResp(ttdsaXchg->agRoot, ttdsaXchg); + } + if (saStatus == AGSA_RC_SUCCESS) + { + TI_DBG1(("ttdsaIOCompleted: 2 loc retried\n")); + ttdsaXchg->retries++; + } + else + { + TI_DBG1(("ttdsaIOCompleted: 2 loc retry failed\n")); + ttdsaXchg->retries = 0; + /* + * because we are freeing up the exchange + * we must let the oslayer know that + * we are releasing the resources by + * setting the tdData to NULL + */ + tiIORequest = ttdsaXchg->IORequestBody.IOType.TargetIO.tiIORequest; + tiIORequest.tdData = agNULL; + + ostiTargetIOError( + tiRoot, + &tiIORequest, + status, + statusDetail + ); + + /* clean up resources */ + ttdsaXchgFreeStruct(tiRoot,ttdsaXchg); + } + } + } + else + { + TI_DBG1(("ttdsaIOCompleted: retry is over\n")); + ttdsaXchg->retries = 0; + + tiIORequest = ttdsaXchg->IORequestBody.IOType.TargetIO.tiIORequest; + tiIORequest.tdData = agNULL; + + ostiTargetIOError( + tiRoot, + &tiIORequest, + status, + statusDetail + ); + + /* clean up resources */ + ttdsaXchgFreeStruct(tiRoot,ttdsaXchg); + } + } /* saData != agNULL */ + }/* if (IOFailed == agTRUE) */ + } /* not TMrequest */ + else /* TMrequest */ + { + TI_DBG1(("ttdsaIOCompleted: TM request\n")); + TI_DBG1(("ttdsaIOCompleted: TM initiator tag 0x%x\n", ttdsaXchg->tag)); + + switch(agIOStatus) + { + case OSSA_IO_SUCCESS: + TI_DBG1(("ttdsaIOCompleted: success\n")); + status = tiIOSuccess; + break; + case OSSA_IO_ABORTED: + TI_DBG1(("ttdsaIOCompleted: ABORTED\n")); + status = tiIOFailed; + statusDetail = tiDetailAborted; + IOFailed = agTRUE; + break; + case OSSA_IO_ABORT_RESET: + TI_DBG1(("ttdsaIOCompleted: ABORT_RESET\n")); + status = tiIOFailed; + statusDetail = tiDetailAbortReset; + IOFailed = agTRUE; + break; +#ifdef REMOVED + case OSSA_IO_OVERFLOW: /* fall through */ +#endif + case OSSA_IO_UNDERFLOW: /* fall through */ + case OSSA_IO_FAILED: /* fall through */ +#ifdef REMOVED + case OSSA_IO_NOT_VALID: /* fall through */ +#endif + case OSSA_IO_NO_DEVICE: /* fall through */ + //case OSSA_IO_NO_SUPPORT: /* fall through */ /*added to compile tgt_drv (TP)*/ + case OSSA_IO_LINK_FAILURE: /* fall through */ + case OSSA_IO_PROG_ERROR: /* fall through */ + case OSSA_IO_DS_NON_OPERATIONAL: /* fall through */ + case OSSA_IO_DS_IN_RECOVERY: /* fall through */ + case OSSA_IO_TM_TAG_NOT_FOUND: /* fall through */ + case OSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE: /* fall through */ + default: + status = tiIOFailed; + statusDetail = tiDetailOtherError; + IOFailed = agTRUE; + break; + } /* switch */ + + /* for not found IO, we don't call OS */ + if (ttdsaXchg->io_found == agTRUE) + { + ostiTargetTmCompleted( + tiRoot, + ttdsaXchg->IORequestBody.tiIORequest, + status, + statusDetail + ); + } + + /* clean up resources */ + ttdsaXchgFreeStruct(tiRoot, ttdsaXchg); + + + } /* TM Request */ + return; +} + +osGLOBAL void +ttdsaTMProcess( + tiRoot_t *tiRoot, + ttdsaXchg_t *ttdsaXchg +) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + + ttdsaTgt_t *Target = (ttdsaTgt_t *)tdsaAllShared->ttdsaTgt; + agsaSSPScsiTaskMgntReq_t *agTMIU; + bit8 TMFun; + bit32 tiTMFun; + tiIORequest_t *reftiIORequest = agNULL; + tdList_t *IOList; + bit32 IOFound = agFALSE; + ttdsaXchg_t *tmp_ttdsaXchg = agNULL; + agsaRoot_t *agRoot = (agsaRoot_t *)&(tdsaAllShared->agRootNonInt); + agsaIORequest_t *agIORequest = agNULL; + agsaIORequest_t *agIOAbortRequest = agNULL; + tdsaDeviceData_t *oneDeviceData = agNULL; + agsaDevHandle_t *agDevHandle = agNULL; + + TI_DBG1(("ttdsaTMProcess: start\n")); + + ttdsaXchg->isTMRequest = agTRUE; + + agTMIU = (agsaSSPScsiTaskMgntReq_t *)&(ttdsaXchg->agTMIU); + TMFun = agTMIU->taskMgntFunction; + + switch (TMFun) + { + case AGSA_ABORT_TASK: + TI_DBG1(("ttdsaTMProcess: ABORT_TASK\n")); + tiTMFun = AG_ABORT_TASK; + break; + case AGSA_ABORT_TASK_SET: + TI_DBG1(("ttdsaTMProcess: ABORT_TASK_SET\n")); + tiTMFun = AG_ABORT_TASK_SET; + break; + case AGSA_CLEAR_TASK_SET: + TI_DBG1(("ttdsaTMProcess: CLEAR_TASK_SET\n")); + tiTMFun = AG_CLEAR_TASK_SET; + break; + case AGSA_LOGICAL_UNIT_RESET: + TI_DBG1(("ttdsaTMProcess: LOGICAL_UNIT_RESET\n")); + tiTMFun = AG_LOGICAL_UNIT_RESET; + break; + case AGSA_CLEAR_ACA: + TI_DBG1(("ttdsaTMProcess: CLEAR_ACA\n")); + tiTMFun = AG_CLEAR_ACA; + break; + case AGSA_QUERY_TASK: + TI_DBG1(("ttdsaTMProcess: QUERY_TASK\n")); + tiTMFun = AG_QUERY_TASK; + break; + default: + TI_DBG1(("ttdsaTMProcess: RESERVED TM 0x%x %d\n", TMFun, TMFun)); + tiTMFun = 0xff; /* unknown task management request */ + break; + } + + /* + * Give the OS Specific module to apply it's Task management policy. + */ + + + /* + osGLOBAL void ostiTaskManagement ( + tiRoot_t *tiRoot, + bit32 task, + bit8 *scsiLun, + tiIORequest_t *refTiIORequest, + tiIORequest_t *tiTMRequest, + tiDeviceHandle_t *tiDeviceHandle); + */ + if (TMFun == AGSA_ABORT_TASK) + { + TI_DBG1(("ttdsaTMProcess: if abort task; to be tested \n")); + /* + needs to find a reftIIORequest and set it + */ + + IOList = Target->ttdsaXchgData.xchgBusyList.flink; + IOFound = agFALSE; + + /* search through the current IOList */ + while (IOList != &Target->ttdsaXchgData.xchgBusyList) + { + + tmp_ttdsaXchg = TDLIST_OBJECT_BASE(ttdsaXchg_t, XchgLinks, IOList); + if (tmp_ttdsaXchg->tag == agTMIU->tagOfTaskToBeManaged) + { + TI_DBG1(("ttdsaTMProcess: tag 0x%x\n",tmp_ttdsaXchg->tag)); + IOFound = agTRUE; + break; + } + IOList = IOList->flink; + } /* while */ + + if (IOFound == agTRUE) + { + + TI_DBG1(("ttdsaTMProcess: found \n")); + /* call saSSPAbort() */ + + TI_DBG1(("ttdsaTMProcess: loc 1\n")); + /* abort taskmanagement itself */ + agIOAbortRequest = (agsaIORequest_t *)&(ttdsaXchg->IORequestBody.agIORequest); + + /* IO to be aborted */ + agIORequest = (agsaIORequest_t *)&(tmp_ttdsaXchg->IORequestBody.agIORequest); + oneDeviceData = tmp_ttdsaXchg->DeviceData; + agDevHandle = oneDeviceData->agDevHandle; + + if (agIORequest == agNULL) + { + TI_DBG1(("ttdsaTMProcess: agIORequest is NULL\n")); + } + else + { + TI_DBG1(("ttdsaTMProcess: agIORequest is NOT NULL\n")); + if (agIORequest->sdkData == agNULL) + { + TI_DBG1(("ttdsaTMProcess: agIORequest->saData is NULL\n")); + } + else + { + TI_DBG1(("ttdsaTMProcess: agIORequest->saData is NOT NULL\n")); +#ifdef RPM_SOC + saSSPAbort(agRoot, agIORequest); +#else + saSSPAbort(agRoot, agIOAbortRequest,0,agDevHandle,0,agIORequest, agNULL); +#endif + } + } + + } /* FOUND */ + else + { + ttdsaXchg->io_found = agFALSE; + tiTGTSendTmResp(tiRoot, + ttdsaXchg->IORequestBody.tiIORequest, + tiError /* this is FUNCTION_FAILED */ ); + TI_DBG1(("ttdsaTMProcess: ABORT_TASK not found\n")); + return; + } + + } /* ABORT_TASK */ + /* + reftiIORequest: referred IO request. + If found, not null. But not used in ramdisk + */ + TI_DBG1(("ttdsaTMProcess: calling ostiTaskManagement\n")); + ostiTaskManagement( + tiRoot, + tiTMFun, + ttdsaXchg->agTMIU.lun, + reftiIORequest, + ttdsaXchg->IORequestBody.tiIORequest, + &ttdsaXchg->DeviceData->tiDeviceHandle + ); + + + + return; +} + +/***************************************************************************** + * + * tiTGTIOAbort + * + * Purpose: This function is called to abort an IO previously reported + * to oslayer through ostiProcessRequest() function. + * + * Parameters: + * tiRoot: Pointer to driver Instance. + * tiIORequest: Pointer to the I/O request context for this I/O. + * This context was initially passed to the OS Specific + * Module in ostiProcessScsiReq(). + * Return: + * tiSuccess: Abort request was successfully initiated + * tiBusy: No resources available, try again later + * tiError: Other errors that prevent the abort request from being + * started + * Note: + * + *****************************************************************************/ +osGLOBAL bit32 +tiTGTIOAbort ( + tiRoot_t *tiRoot, + tiIORequest_t *taskTag +) +{ + ttdsaXchg_t *ttdsaXchg; + ttdsaXchg_t *ttdsaIOAbortXchg; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + agsaRoot_t *agRoot = (agsaRoot_t *)&(tdsaAllShared->agRootNonInt); + agsaIORequest_t *agIORequest = agNULL; + agsaIORequest_t *agIOAbortRequest = agNULL; + tdsaDeviceData_t *oneDeviceData = agNULL; + agsaDevHandle_t *agDevHandle = agNULL; + + TI_DBG1(("tiTGTIOAbort: start\n")); + + ttdsaXchg = (ttdsaXchg_t *)taskTag->tdData; + + if (ttdsaXchg == agNULL) + { + TI_DBG1(("tiTGTIOAbort: IOError 1 \n")); + /* + * this exchange has already been freed. + * No need to free it + */ + ostiTargetIOError( + tiRoot, + taskTag, + tiIOFailed, + tiDetailAborted + ); + } + else if (ttdsaXchg->IORequestBody.agIORequest.sdkData == agNULL) + { + TI_DBG1(("tiTGTIOAbort: IOError 2 \n")); + /* We have not issued this IO to the salayer. + * Abort it right here. + */ + if (TD_XCHG_GET_STATE(ttdsaXchg) == TD_XCHG_STATE_INACTIVE) + { + TI_DBG1(("tiTGTIOAbort: wrong DEQUEUE_THIS\n")); + } + + TI_DBG1(("tiTGTIOAbort: IOError 3\n")); + + ostiTargetIOError( + tiRoot, + taskTag, + tiIOFailed, + tiDetailAborted + ); + TI_DBG1(("tiTGTIOAbort: IOError 4\n")); + + ttdsaXchgFreeStruct( + ttdsaXchg->tiRoot, + ttdsaXchg + ); + TI_DBG1(("tiTGTIOAbort: IOError 5\n")); + + } + else /* to be tested */ + { + TI_DBG1(("tiTGTIOAbort: aborting; to be tested \n")); + /* abort io request itself */ + ttdsaIOAbortXchg = ttdsaXchgGetStruct(agRoot); + + if (ttdsaIOAbortXchg == agNULL) + { + TI_DBG1(("tiTGTIOAbort: no free xchg structures\n")); + // ttdsaDumpallXchg(tiRoot); + return tiError; + } + ttdsaIOAbortXchg->agRoot = agRoot; + ttdsaIOAbortXchg->tiRoot = tiRoot; + agIOAbortRequest= &(ttdsaXchg->IORequestBody.agIORequest); + /* remember IO to be aborted */ + ttdsaIOAbortXchg->tiIOToBeAbortedRequest = taskTag; + ttdsaIOAbortXchg->XchgToBeAborted = ttdsaXchg; + + // ttdsaIOAbortXchg->FrameType = SAS_TM; + + /* io is being aborted */ + ttdsaXchg->oslayerAborting = agTRUE; + agIORequest = (agsaIORequest_t *)&(ttdsaXchg->IORequestBody.agIORequest); + oneDeviceData = ttdsaXchg->DeviceData; + if (oneDeviceData == agNULL) + { + TI_DBG1(("tiTGTIOAbort: oneDeviceData is null; wrong\n")); + } + else + { + agDevHandle = oneDeviceData->agDevHandle; + ttdsaIOAbortXchg->DeviceData = oneDeviceData; + } +#ifdef RPM_SOC + saSSPAbort(agRoot, agIORequest); +#else + saSSPAbort(agRoot, agIOAbortRequest,0,agDevHandle,0,agIORequest, agNULL); + } + + return tiSuccess; +} + +osGLOBAL bit32 +tiTGTIOAbortAll( + tiRoot_t *tiRoot, + tiDeviceHandle_t *tiDeviceHandle +) +{ + agsaRoot_t *agRoot = agNULL; + tdsaDeviceData_t *oneDeviceData = agNULL; + bit32 status = tiError; + + TI_DBG3(("tiTGTIOAbortAll: start\n")); + + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + + if (oneDeviceData == agNULL) + { + TI_DBG1(("tiTGTIOAbortAll: oneDeviceData is NULL!!!\n")); + return tiError; + } + + /* for hotplug */ + if (oneDeviceData->valid != agTRUE || oneDeviceData->registered != agTRUE || + oneDeviceData->tdPortContext == agNULL ) + { + TI_DBG1(("tiTGTIOAbortAll: NO Device did %d\n", oneDeviceData->id )); + TI_DBG1(("tiTGTIOAbortAll: device AddrHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG1(("tiTGTIOAbortAll: device AddrLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + return tiError; + } + + agRoot = oneDeviceData->agRoot; + + if (agRoot == agNULL) + { + TI_DBG1(("tiTGTIOAbortAll: agRoot is NULL!!!\n")); + return tiError; + } + + /* this is processed in ossaSSPAbortCB, ossaSATAAbortCB, ossaSMPAbortCB */ + oneDeviceData->OSAbortAll = agTRUE; + + status = tdsaAbortAll(tiRoot, agRoot, oneDeviceData); + + return status; + +} + + +/***************************************************************************** + * + * tiTGTSendTmResp + * + * Purpose: This function is called to abort an IO previously reported + * to oslayer through ostiProcessRequest() function. + * + * Parameters: + * tiRoot: Pointer to driver Instance. + * tiIORequest: Pointer to the I/O request context for this I/O. + * This context was initially passed to the OS Specific + * Module in ostiProcessScsiReq(). + * Return: + * tiSuccess: Abort request was successfully initiated + * tiBusy: No resources available, try again later + * tiError: Other errors that prevent the abort request from being + * started + * Note: + * + *****************************************************************************/ +osGLOBAL bit32 +tiTGTSendTmResp( + tiRoot_t *tiRoot, + tiIORequest_t *tiTMRequest, + bit32 status +) +{ + ttdsaXchg_t *ttdsaXchg; + sas_resp_t *SASResp; + bit32 tdStatus; + TI_DBG1(("tiTGTSendTmResp: start 1\n")); + + ttdsaXchg = (ttdsaXchg_t *)tiTMRequest->tdData; + /* set the response and send it */ + /* response status is 0 */ + /* status is TM status */ + + TI_DBG1(("tiTGTSendTmResp: start 2\n")); + SASResp = (sas_resp_t *)ttdsaXchg->resp.virtAddr; + TI_DBG1(("tiTGTSendTmResp: start 3\n")); + + if (ttdsaXchg->FrameType == SAS_TM) + { + SASResp->agResp.status = 0; + SASResp->agResp.dataPres = RESPONSE_DATA; + OSSA_WRITE_BE_32(agRoot, SASResp->agResp.responsedataLen, 0, RESPONSE_DATA_LEN); + OSSA_WRITE_BE_32(agRoot, SASResp->agResp.senseDataLen, 0, 0); + switch (status) + { + case tiSuccess: + TI_DBG2(("tiTGTSendTmResp: tiSuccess\n")); + SASResp->RespData[3] = AGSA_TASK_MANAGEMENT_FUNCTION_SUCCEEDED; + break; + case tiError: + TI_DBG1(("tiTGTSendTmResp: tiError\n")); + SASResp->RespData[3] = AGSA_TASK_MANAGEMENT_FUNCTION_FAILED; + break; + case tiBusy: + TI_DBG1(("tiTGTSendTmResp: tibusy\n")); + SASResp->RespData[3] = AGSA_TASK_MANAGEMENT_FUNCTION_FAILED; + break; + case tiIONoDevice: + TI_DBG1(("tiTGTSendTmResp: tiionodevicee\n")); + SASResp->RespData[3] = AGSA_TASK_MANAGEMENT_FUNCTION_FAILED; + break; + case tiMemoryTooLarge: + TI_DBG1(("tiTGTSendTmResp: timemorytoolarge\n")); + SASResp->RespData[3] = AGSA_TASK_MANAGEMENT_FUNCTION_FAILED; + break; + case tiMemoryNotAvail: + TI_DBG1(("tiTGTSendTmResp: timemorynotavail\n")); + SASResp->RespData[3] = AGSA_TASK_MANAGEMENT_FUNCTION_FAILED; + break; + case tiInvalidHandle: + TI_DBG1(("tiTGTSendTmResp: tiinvalidhandle\n")); + SASResp->RespData[3] = AGSA_TASK_MANAGEMENT_FUNCTION_FAILED; + break; + case tiNotSupported: + TI_DBG1(("tiTGTSendTmResp: tiNotsupported\n")); + SASResp->RespData[3] = AGSA_TASK_MANAGEMENT_FUNCTION_NOT_SUPPORTED; + break; + case tiReject: + TI_DBG1(("tiTGTSendTmResp: tireject\n")); + SASResp->RespData[3] = AGSA_TASK_MANAGEMENT_FUNCTION_FAILED; + break; + case tiIncorrectLun: + TI_DBG1(("tiTGTSendTmResp: tiincorrectlun\n")); + SASResp->RespData[3] = AGSA_INCORRECT_LOGICAL_UNIT_NUMBER; + break; + default: + TI_DBG1(("tiTGTSendTmResp: default\n")); + SASResp->RespData[3] = AGSA_TASK_MANAGEMENT_FUNCTION_FAILED; + break; + } + ttdsaXchg->resp.length = sizeof(agsaSSPResponseInfoUnit_t) + RESPONSE_DATA_LEN; + ttdsaXchg->statusSent = agTRUE; + } + else + { + TI_DBG1(("tiTGTSendTmResp: not TM frame\n")); + return tiError; + } + + tdStatus = ttdsaSendResp(ttdsaXchg->agRoot, ttdsaXchg); + if (tdStatus == AGSA_RC_SUCCESS) + { + TI_DBG1(("tiTGTSendTmResp: send success\n")); + return tiSuccess; + } + else if (tdStatus == AGSA_RC_FAILURE) + { + TI_DBG1(("tiTGTSendTmResp: sending not successful\n")); + return tiError; + } + else + { + TI_DBG1(("tiTGTSendTmResp: send busy\n")); + return tiBusy; + } + + +#ifdef REMOVED + + tiTGTSetResp(tiRoot, tiTMRequest, 0, 0, 0); +#endif + +#ifdef REMOVED + + if (ttdsaXchg->resp.length != 0) + { + TI_DBG1(("tiTGTSendTmResp: respsonse is set \n")); + TI_DBG1(("tiTGTSendTmResp: resp.length 0x%x\n", + ttdsaXchg->resp.length)); + ttdsaXchg->responseSent = agTRUE; + + ttdsaSendResp(ttdsaXchg->agRoot, ttdsaXchg); + } + else + { + /* no respsonse is set, direct call */ + TI_DBG1(("tiTGTSendTmResp: direct call\n")); + tiTGTSetResp(tiRoot, tiTMRequest, 0, 0, 0); + ttdsaXchg->responseSent = agTRUE; + ttdsaSendResp(ttdsaXchg->agRoot, ttdsaXchg); + } + +#define TASK_MANAGEMENT_FUNCTION_COMPLETE 0x0 +#define INVALID_FRAME 0x2 +#define TASK_MANAGEMENT_FUNCTION_NOT_SUPPORTED 0x4 +#define TASK_MANAGEMENT_FUNCTION_FAILED 0x5 +#define TASK_MANAGEMENT_FUNCTION_SUCCEEDED 0x8 +#define INVALID_LOGICAL_UNIT_NUMBER 0x9 +#endif + +} + + + +/***************************************************************************** + * + * tiTGTSenseBufferGet + * + * Purpose: This function is called to get the address of sense buffer from + * the target specific Transport Dependent Layer. + * + * Parameters: + * tiRoot: Pointer to driver/port instance. + * tiIORequest: I/O request context. + * length: Lenght in bytes of the sense buffer. + * + * Return: none + * + * Note: + * + *****************************************************************************/ +osGLOBAL void *tiTGTSenseBufferGet( tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + bit32 length +) +{ + + ttdsaXchg_t *ttdsaXchg; + + ttdsaXchg = (ttdsaXchg_t *)tiIORequest->tdData; + + TI_DBG4(("tiTGTSenseBufferGet: start\n")); + OS_ASSERT((length <= 64), "length too big in tiTGTSenseBufferGet"); + + return &ttdsaXchg->resp.virtAddr[sizeof(agsaSSPResponseInfoUnit_t)]; +} + +/***************************************************************************** + * + * tiTGTSetResp + * + * Purpose: This function is called when the target OS Specific Module is ready + * to send a response with the next tiTGTIOStart() + * function call. This function allows the TD Layer to setup its + * portion of the status and mark it to be sent on the next + * tiTGTIOStart() function call. + * + * Parameters: + * tiRoot: Pointer to driver Instance. + * tiIORequest: Pointer to the I/O request context for this I/O. + * This context was initially passed to the OS Specific Module + * in ostiProcessScsiReq(). + * dataSentLength: How much data sent or received for this Request. + * ScsiStatus: Status for this SCSI command. + * senseLength: Length of sense data if any. + * + * Return: none + * + * Note: + * + *****************************************************************************/ +osGLOBAL void +tiTGTSetResp( tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + bit32 dataSentLength, + bit8 ScsiStatus, + bit32 senseLength +) +{ + /* no call to saSSPStart() in this function */ + /* + response is normally for task management + sense is for command with error + need to know this is for TM or cmd + */ + /* + tiTGTSetResp(rdRoot->pTiRoot, + rdIORequest->tiIORequest, + dataSentLength, + ScsiStatus, + senseLength); + + + + */ + ttdsaXchg_t *ttdsaXchg; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *)tiRoot->tdData; +#ifdef REMOVED + agsaSSPTargetResponse_t *agSSPTargetResp; +#endif + sas_resp_t *SASResp; + bit32 TotalRespLen = 0; + + TI_DBG4 (("tiTGTSetResp: start\n")); + TI_DBG4 (("tiTGTSetResp: datelen %d senselen %d\n", dataSentLength, senseLength)); + + ttdsaXchg = (ttdsaXchg_t *)tiIORequest->tdData; + SASResp = (sas_resp_t *)ttdsaXchg->resp.virtAddr; + + SASResp->agResp.status = ScsiStatus; + + if (ttdsaXchg->FrameType == SAS_TM) + { + + TI_DBG1(("tiTGTSetResp: TM\n")); + if (senseLength != 0) + { + TI_DBG1 (("tiTGTSetResp: non-zero sensedatalen for TM\n")); + return; + } + SASResp->agResp.dataPres = RESPONSE_DATA; + OSSA_WRITE_BE_32(agRoot, SASResp->agResp.responsedataLen, 0, RESPONSE_DATA_LEN); + OSSA_WRITE_BE_32(agRoot, SASResp->agResp.senseDataLen, 0, 0); + SASResp->RespData[3] = AGSA_TASK_MANAGEMENT_FUNCTION_NOT_SUPPORTED; + TotalRespLen = sizeof(agsaSSPResponseInfoUnit_t) + RESPONSE_DATA_LEN; + } + else + { + if (senseLength == 0) + { + TI_DBG4 (("tiTGTSetResp: CMND, no data\n")); + /* good and no data present */ + SASResp->agResp.dataPres = NO_DATA; + OSSA_WRITE_BE_32(agRoot, SASResp->agResp.responsedataLen, 0, 0); + OSSA_WRITE_BE_32(agRoot, SASResp->agResp.senseDataLen, 0, 0); + TotalRespLen = sizeof(agsaSSPResponseInfoUnit_t); + /* collapse good response with READ */ + if (ttdsaXchg->XchType == AGSA_SSP_TGT_READ_DATA) + { + TI_DBG4(("tiTGTSetResp: read rsp collapse\n")); + + if (tdsaRoot->autoGoodRSP & READ_GOOD_RESPONSE) + ttdsaXchg->readRspCollapsed = agTRUE; + } + /* collapse good response with WRITE */ + if (ttdsaXchg->XchType == AGSA_SSP_TGT_WRITE_DATA) + { + TI_DBG4(("tiTGTSetResp: write rsp collapse\n")); + if (tdsaRoot->autoGoodRSP & WRITE_GOOD_RESPONSE) + { + if (tiIS_SPC(TI_TIROOT_TO_AGROOT(tiRoot))) + { + ttdsaXchg->wrtRspCollapsed = agFALSE; + } + else + { + ttdsaXchg->wrtRspCollapsed = agTRUE; + } + + } + } + } + else + { + TI_DBG4 (("tiTGTSetResp: CMND, sense data\n")); + /* bad and sense data */ + SASResp->agResp.dataPres = SENSE_DATA; + OSSA_WRITE_BE_32(agRoot, SASResp->agResp.responsedataLen, 0, 0); + OSSA_WRITE_BE_32(agRoot, SASResp->agResp.senseDataLen, 0, senseLength); + TotalRespLen = sizeof(agsaSSPResponseInfoUnit_t) + senseLength; + } + } + + ttdsaXchg->statusSent = agTRUE; + + TI_DBG4(("tiTGTSetResp: ttdsaXchg %p\n", ttdsaXchg)); + TI_DBG4(("tiTGTSetResp: TotalRespLen 0x%x \n", TotalRespLen)); + TI_DBG4(("tiTGTSetResp: upper 0x%x \n", + ttdsaXchg->resp.phyAddrUpper)); + TI_DBG4(("tiTGTSetResp: lower 0x%x \n", + ttdsaXchg->resp.phyAddrLower)); + + + + /* set the correct response length */ + ttdsaXchg->resp.length = TotalRespLen; + + dumpresp((bit8 *)ttdsaXchg->resp.virtAddr, ttdsaXchg->resp.length); + +#ifdef REMOVED + /* + send TM reponse (which has only response data not sense data here + since ramdisk does not call IOstart for this + */ + + if (ttdsaXchg->FrameType == SAS_TM) + { + TI_DBG1(("tiTGTSetResp: respsonse is set \n")); + TI_DBG1(("tiTGTSetResp: resp.length 0x%x\n", + ttdsaXchg->resp.length)); + ttdsaSendResp(ttdsaXchg->agRoot, ttdsaXchg); + } +#endif +#ifdef REMOVED + /* sas response */ + agSSPTargetResp = + &(ttdsaXchg->IORequestBody.transport.SAS.agSASRequestBody.sspTargetResponse); + + agSSPTargetResp->agTag = ttdsaXchg->tag; + agSSPTargetResp->respBufLength = TotalRespLen; + agSSPTargetResp->respBufUpper + = ttdsaXchg->IORequestBody.transport.SAS.agSASRequestBody.sspTargetResponse.respBufUpper; + agSSPTargetResp->respBufLower + = ttdsaXchg->IORequestBody.transport.SAS.agSASRequestBody.sspTargetResponse.respBufLower; + + + + TI_DBG4(("tiTGTSetResp: len 0x%x \n", + ttdsaXchg->IORequestBody.transport.SAS.agSASRequestBody.sspTargetResponse.respBufLength)); + TI_DBG4(("tiTGTSetResp: upper 0x%x \n", + ttdsaXchg->IORequestBody.transport.SAS.agSASRequestBody.sspTargetResponse.respBufUpper)); + TI_DBG4(("tiTGTSetResp: lower 0x%x \n", + ttdsaXchg->IORequestBody.transport.SAS.agSASRequestBody.sspTargetResponse.respBufLower)); +#endif + + return; +} + + + +/****************************************************************************** + * + * tiTGTGetDeviceHandles + * + * Purpose: This routine is called to to return the device handles for each + * device currently available. + * + * Parameters: + * tiRoot: Pointer to driver Instance. + * agDev[]: Array to receive pointers to the device handles. + * maxDevs: Number of device handles which will fit in array pointed + * by agDev. + * Return: + * Number of device handle slots present (however, only maxDevs + * are copied into tiDev[]) which may be greater than the number of + * handles actually present. + * + * Note: + * + ******************************************************************************/ + +osGLOBAL bit32 +tiTGTGetDeviceHandles( + tiRoot_t *tiRoot, + tiPortalContext_t *tiPortalContext, + tiDeviceHandle_t *tiDev[], + bit32 maxDevs +) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + ttdsaTgt_t *Target = (ttdsaTgt_t *)tdsaAllShared->ttdsaTgt; + bit32 deviceToReturn; + bit32 devicePresent=0; + bit32 deviceIndex=0; + tdList_t *PortContextList; + tdsaPortContext_t *onePortContext = agNULL; + tdList_t *DeviceListList; + tdsaDeviceData_t *oneDeviceData = agNULL; + bit32 found = agFALSE; + + + TI_DBG4 (("tiTGTGetDeviceHandles: start\n")); + + /* Check boundary condition */ + if (maxDevs > Target->OperatingOption.MaxTargets) + { + deviceToReturn = Target->OperatingOption.MaxTargets; + } + else + { + deviceToReturn = maxDevs; + } + + + /* make sure tiPortalContext is valid */ + PortContextList = tdsaAllShared->MainPortContextList.flink; + while (PortContextList != &(tdsaAllShared->MainPortContextList)) + { + onePortContext = TDLIST_OBJECT_BASE(tdsaPortContext_t, MainLink, PortContextList); + if (onePortContext->tiPortalContext == tiPortalContext) + { + TI_DBG4(("tiTGTGetDeviceHandles: found; oneportContext ID %d\n", onePortContext->id)); + found = agTRUE; + break; + } + PortContextList = PortContextList->flink; + } + + if (found == agFALSE) + { + TI_DBG4(("tiTGTGetDeviceHandles: No corressponding tdsaPortContext\n")); + return 0; + } + + + /* go through device list and returns them */ + DeviceListList = tdsaAllShared->MainDeviceList.flink; + while (DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + TI_DBG4(("tiTGTGetDeviceHandles: pid %d did %d\n", onePortContext->id, oneDeviceData->id)); + TI_DBG4(("tiTGTGetDeviceHandles: device AddrHi 0x%08x\n", oneDeviceData->SASAddressID.sasAddressHi)); + TI_DBG4(("tiTGTGetDeviceHandles: device AddrLo 0x%08x\n", oneDeviceData->SASAddressID.sasAddressLo)); + TI_DBG4(("tiTGTGetDeviceHandles: handle %p\n", &(oneDeviceData->tiDeviceHandle))); + if (oneDeviceData->valid == agTRUE) + { + TI_DBG4(("tiTGTGetDeviceHandles: valid deviceindex %d devicePresent %d\n", deviceIndex, devicePresent)); + + tiDev[deviceIndex] = &(oneDeviceData->tiDeviceHandle); + devicePresent++; + } + else + { + tiDev[deviceIndex] = agNULL; + TI_DBG4(("tiTGTGetDeviceHandles: not valid deviceindex %d devicePresent %d\n", deviceIndex, devicePresent)); + } + deviceIndex++; + + if (devicePresent >= deviceToReturn ) + { + break; + } + DeviceListList = DeviceListList->flink; + } + + return devicePresent; +} + + + + +/****************************************************************************** + * + * tiTGTGetDeviceInfo + * + * Purpose: This routine is called to to return the device information for + * specified device handle. + * + * Parameters: + * tiRoot: Pointer to driver Instance. + * tiDeviceHandle: device handle associated with the device for which + * information is queried + * tiDeviceInfo: device information structure containing address and name. + * + * Return: + * tiSuccess: if the device handle is valid. + * tiError : if the device handle is not valid. + * + * Note: + * + ******************************************************************************/ +osGLOBAL bit32 +tiTGTGetDeviceInfo( + tiRoot_t *tiRoot, + tiDeviceHandle_t *tiDeviceHandle, + tiDeviceInfo_t *tiDeviceInfo) +{ + tdsaDeviceData_t *oneDeviceData = agNULL; + + + TI_DBG4 (("tiTGTGetDeviceInfo: start\n")); + + if (tiDeviceHandle == agNULL) + { + TI_DBG4 (("tiTGTGetDeviceInfo: tiDeviceHandle is NULL\n")); + return tiError; + } + + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + + if (oneDeviceData == agNULL) + { + TI_DBG4 (("tiTGTGetDeviceInfo: oneDeviceData is NULL\n")); + return tiError; + } + + /* filling in the link rate */ + if (oneDeviceData->registered == agTRUE) + { + tiDeviceInfo->info.devType_S_Rate = oneDeviceData->agDeviceInfo.devType_S_Rate; + } + else + { + tiDeviceInfo->info.devType_S_Rate = oneDeviceData->agDeviceInfo.devType_S_Rate & 0x0f; + } + + /* temp just returning local and remote SAS address; doesn't have a name */ + tiDeviceInfo->remoteName = (char *)&(oneDeviceData->tdPortContext->sasRemoteAddressHi); + tiDeviceInfo->remoteAddress = (char *)&(oneDeviceData->tdPortContext->sasRemoteAddressLo); + + tiDeviceInfo->localName = (char *)&(oneDeviceData->tdPortContext->sasLocalAddressHi); + tiDeviceInfo->localAddress = (char *)&(oneDeviceData->tdPortContext->sasLocalAddressLo); + + return tiSuccess; +} + +/***************************************************************************** + *! \brief ttdssIOAbortedHandler + * + * Purpose: This function processes I/Os completed and returned by SAS/SATA lower + * layer with agIOStatus = OSSA_IO_ABORTED + * + * \param agRoot: pointer to port instance + * \param agIORequest: pointer to I/O request + * \param agIOStatus: I/O status given by LL layer + * \param agIOInfoLen: lenth of complete SAS RESP frame + * \param agParam A Handle used to refer to the response frame or handle + * of abort request + * \param agOtherInfo Residual count + * \return: None + * + * + *****************************************************************************/ +/* see itdosIOCompleted() and itdinit.c and itdIoAbortedHandler in itdio.c*/ +osGLOBAL void +ttdssIOAbortedHandler ( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo +) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdIORequestBody_t *tdIORequestBody; + + TI_DBG1(("itdssIOAbortedHandler: start\n")); + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + if (agIOStatus != OSSA_IO_ABORTED) + { + TI_DBG1(("itdssIOAbortedHandler: incorrect agIOStatus 0x%x\n", agIOStatus)); + + } + + ostiTargetIOError( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailAborted + ); + + return; +} + + diff --git a/sys/dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdreset.c b/sys/dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdreset.c new file mode 100644 index 000000000000..d90718d5b8c2 --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdreset.c @@ -0,0 +1,52 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#ifdef INITIATOR_DRIVER +#include +#include +#include +#endif + +#ifdef TARGET_DRIVER +#include "ttdglobl.h" +#include "ttdtxchg.h" +#include "ttdtypes.h" +#endif + +#include +#include diff --git a/sys/dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdsmp.c b/sys/dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdsmp.c new file mode 100644 index 000000000000..7d15b0c438ac --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdsmp.c @@ -0,0 +1,446 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +/*******************************************************************************/ +/** \file + * + * $RCSfile: ttdsmp.c,v $ + * + * Copyright 2006 PMC-Sierra, Inc. + * + * $Author: hasungwo $ + * $Revision: 112322 $ + * $Date: 2012-01-04 19:23:42 -0800 (Wed, 04 Jan 2012) $ + * + * This file contains initiator IO related functions in TD layer + * + */ +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#ifdef INITIATOR_DRIVER +#include +#include +#include +#endif + +#ifdef TARGET_DRIVER +#include "ttdglobl.h" +#include "ttdtxchg.h" +#include "ttdtypes.h" +#endif + +#include +#include + +osGLOBAL void +ttdsaSMPCompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + //agsaSMPFrameHeader_t *agFrameHeader, //(TP) + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + ttdsaXchg_t *ttdsaXchg = (ttdsaXchg_t *)agIORequest->osData; + + /* cf) ttdsaIOCompleted */ + TI_DBG1(("ttdsaSMPCompleted: start\n")); + if (tiRoot == agNULL) + { + TI_DBG1(("ttdsaSMPCompleted: tiRoot is NULL, wrong\n")); + return; + } + + if (ttdsaXchg == agNULL) + { + TI_DBG1(("ttdsaSMPCompleted: ttdsaXchg is NULL, wrong\n")); + return; + } + + ttdsaXchgFreeStruct(tiRoot,ttdsaXchg); + + + /* to-do: no callback to OS layer */ + return; +} + +osGLOBAL void +ttdsaNotSupportRespSend( + agsaRoot_t *agRoot, + agsaDevHandle_t *agDevHandle, + ttdsaXchg_t *ttdsaXchg, + bit8 smpfn + ) +{ + bit32 agRequestType; + agsaSASRequestBody_t *agSASRequestBody; + agsaSMPFrame_t *agSMPFrame; + agsaIORequest_t *agIORequest; + bit8 SMPPayload[SMP_DIRECT_PAYLOAD_LIMIT]; /*(TP)*/ + tdssSMPFrameHeader_t tdSMPFrameHeader; /*(TP)*/ + + TI_DBG1(("ttdsaNotSupportSend:\n")); + agRequestType = AGSA_SMP_TGT_RESPONSE; + + agIORequest = &(ttdsaXchg->SMPRequestBody.agIORequest); + + agSASRequestBody = &(ttdsaXchg->SMPRequestBody.agSASRequestBody); + agSMPFrame = &(agSASRequestBody->smpFrame); + + osti_memset(&tdSMPFrameHeader, 0, sizeof(tdssSMPFrameHeader_t)); /*(TP)*/ + + /* smp header */ /*(TP)*/ + tdSMPFrameHeader.smpFrameType = SMP_RESPONSE; /* SMP response */ + tdSMPFrameHeader.smpFunction = smpfn; + tdSMPFrameHeader.smpFunctionResult = UNKNOWN_SMP_FUNCTION; /* unknown smp */ + tdSMPFrameHeader.smpReserved = 0; + + /*old*/ + //agSMPFrame->frameHeader.smpFrameType = SMP_RESPONSE; /* SMP response */ + //agSMPFrame->frameHeader.smpFunction = smpfn; + //agSMPFrame->frameHeader.smpFunctionResult = UNKNOWN_SMP_FUNCTION; /* unknown smp */ + + osti_memcpy(SMPPayload, &tdSMPFrameHeader, 4); /*TP)*/ + + agSMPFrame->outFrameBuf = SMPPayload; /*(TP)*/ + agSMPFrame->outFrameAddrUpper32 = ttdsaXchg->smpresp.phyAddrUpper; + agSMPFrame->outFrameAddrLower32 = ttdsaXchg->smpresp.phyAddrLower; + agSMPFrame->outFrameLen = 0; /* no smp response payload */ + + //agSMPFrame->phyId = ttdsaXchg->SMPphyId; + +#ifdef RPM_SOC + /* not work yet because of high priority q */ + saSMPStart( + agRoot, + agIORequest, + agDevHandle, + agRequestType, + agSASRequestBody, + &ossaSMPCompleted + ); +#else + saSMPStart( + agRoot, + agIORequest, + 0, /* queue number */ + agDevHandle, + agRequestType, + agSASRequestBody, + &ossaSMPCompleted + ); +#endif + return; +} + +osGLOBAL void +ttdsaDiscoverRespSend( + agsaRoot_t *agRoot, + agsaDevHandle_t *agDevHandle, + ttdsaXchg_t *ttdsaXchg + ) +{ + bit32 agRequestType; + agsaSASRequestBody_t *agSASRequestBody; + agsaSMPFrame_t *agSMPFrame; + smpRespDiscover_t *Resp; + smp_resp_t *SMPResp; + agsaIORequest_t *agIORequest; + bit8 SMPPayload[SMP_DIRECT_PAYLOAD_LIMIT]; /*(TP)*/ + tdssSMPFrameHeader_t tdSMPFrameHeader; /*(TP)*/ + + TI_DBG1(("ttdsaDiscoverRespSend:\n")); + + agRequestType = AGSA_SMP_TGT_RESPONSE; + + SMPResp = (smp_resp_t *)ttdsaXchg->smpresp.virtAddr; + + agIORequest = &(ttdsaXchg->SMPRequestBody.agIORequest); + + agSASRequestBody = &(ttdsaXchg->SMPRequestBody.agSASRequestBody); + agSMPFrame = &(agSASRequestBody->smpFrame); + + osti_memset(&tdSMPFrameHeader, 0, sizeof(tdssSMPFrameHeader_t)); /*(TP)*/ + + /* smp header */ /*(TP)*/ + tdSMPFrameHeader.smpFrameType = SMP_RESPONSE; /* SMP response */ + tdSMPFrameHeader.smpFunction = SMP_DISCOVER; /* discover */ + tdSMPFrameHeader.smpFunctionResult = SMP_FUNCTION_ACCEPTED; + tdSMPFrameHeader.smpReserved = 0; + + /*old*/ + //agSMPFrame->frameHeader.smpFrameType = SMP_RESPONSE; /* SMP response */ + //agSMPFrame->frameHeader.smpFunction = SMP_DISCOVER; /* discover */ + //agSMPFrame->frameHeader.smpFunctionResult = SMP_FUNCTION_ACCEPTED; + + osti_memcpy(SMPPayload, &tdSMPFrameHeader, 4); /*TP)*/ + + agSMPFrame->outFrameBuf = SMPPayload; /*(TP)*/ + agSMPFrame->outFrameAddrUpper32 = ttdsaXchg->smpresp.phyAddrUpper; + agSMPFrame->outFrameAddrLower32 = ttdsaXchg->smpresp.phyAddrLower; + agSMPFrame->outFrameLen = sizeof(smpRespDiscover_t); + + //agSMPFrame->phyId = ttdsaXchg->SMPphyId; + + /* smp response payload */ + Resp = (smpRespDiscover_t *)&(SMPResp->RespData); + osti_memset(Resp, 0, sizeof(smpRespDiscover_t)); + /* temp, hardcode smp discover response */ + /* needs to read contents from ID frame */ + /* assumption: for now, attached to edge expander */ + Resp->phyIdentifier = 0; + Resp->attachedDeviceType = SAS_EDGE_EXPANDER_DEVICE; + Resp->negotiatedPhyLinkRate = 0x9; /* enabled, 1.5G */ + Resp->attached_Ssp_Stp_Smp_Sata_Initiator = 0; + Resp->attached_SataPS_Ssp_Stp_Smp_Sata_Target = 0x2; /* SMP target */ + Resp->sasAddressHi[3] = 0x01; + Resp->sasAddressHi[2] = 0x02; + Resp->sasAddressHi[1] = 0x03; + Resp->sasAddressHi[0] = 0x04; + Resp->sasAddressLo[3] = 0x05; + Resp->sasAddressLo[2] = 0x06; + Resp->sasAddressLo[1] = 0x07; + Resp->sasAddressLo[0] = 0x08; + + Resp->attachedSasAddressHi[3] = 0x01; + Resp->attachedSasAddressHi[2] = 0x01; + Resp->attachedSasAddressHi[1] = 0x01; + Resp->attachedSasAddressHi[0] = 0x01; + Resp->attachedSasAddressLo[3] = 0x02; + Resp->attachedSasAddressLo[2] = 0x02; + Resp->attachedSasAddressLo[1] = 0x02; + Resp->attachedSasAddressLo[0] = 0x02; + + Resp->attachedPhyIdentifier = 0; + Resp->programmedAndHardware_MinPhyLinkRate = 0x8; /* not programmable and 1.5 G */ + Resp->programmedAndHardware_MaxPhyLinkRate = 0x8; /* not programmable and 1.5 G */ + Resp->phyChangeCount = 0; /* No broadcast(Change) received */ + Resp->virtualPhy_partialPathwayTimeout = 0x7; /* no virutal phy and see spec 10.4.3.5, p 404 rev 7 */ + Resp->routingAttribute = 0; + osti_memset(&Resp->reserved13, 0, 5); + osti_memset(&Resp->vendorSpecific, 0, 2); + +#ifdef RPM_SOC + /* not work yet because of high priority q */ + saSMPStart( + agRoot, + agIORequest, + agDevHandle, + agRequestType, + agSASRequestBody, + &ossaSMPCompleted + ); +#else + saSMPStart( + agRoot, + agIORequest, + 0, /* queue number */ + agDevHandle, + agRequestType, + agSASRequestBody, + &ossaSMPCompleted + ); +#endif + return; +} + +osGLOBAL void +ttdsaReportGeneralRespSend( + agsaRoot_t *agRoot, + agsaDevHandle_t *agDevHandle, + ttdsaXchg_t *ttdsaXchg + ) +{ + bit32 agRequestType; + agsaSASRequestBody_t *agSASRequestBody; + agsaSMPFrame_t *agSMPFrame; + smpRespReportGeneral_t *Resp; + smp_resp_t *SMPResp; + agsaIORequest_t *agIORequest; + bit8 SMPPayload[SMP_DIRECT_PAYLOAD_LIMIT]; /*(TP)*/ + tdssSMPFrameHeader_t tdSMPFrameHeader; /*(TP)*/ + + TI_DBG1(("ttdsaReportGeneralRespSend:\n")); + + agRequestType = AGSA_SMP_TGT_RESPONSE; + + SMPResp = (smp_resp_t *)ttdsaXchg->smpresp.virtAddr; + + agIORequest = &(ttdsaXchg->SMPRequestBody.agIORequest); + + agSASRequestBody = &(ttdsaXchg->SMPRequestBody.agSASRequestBody); + agSMPFrame = &(agSASRequestBody->smpFrame); + + osti_memset(&tdSMPFrameHeader, 0, sizeof(tdssSMPFrameHeader_t)); /*(TP)*/ + + tdSMPFrameHeader.smpFrameType = SMP_RESPONSE; /* SMP response */ + tdSMPFrameHeader.smpFunction = SMP_REPORT_GENERAL; /* report general */ + tdSMPFrameHeader.smpFunctionResult = SMP_FUNCTION_ACCEPTED; + tdSMPFrameHeader.smpReserved = 0; + + /*old*/ + //agSMPFrame->frameHeader.smpFrameType = SMP_RESPONSE; /* SMP response */ + //agSMPFrame->frameHeader.smpFunction = SMP_REPORT_GENERAL; /* report general */ + //agSMPFrame->frameHeader.smpFunctionResult = SMP_FUNCTION_ACCEPTED; + + osti_memcpy(SMPPayload, &tdSMPFrameHeader, 4); /*(TP)*/ + + agSMPFrame->outFrameBuf = SMPPayload; /*(TP)*/ + agSMPFrame->outFrameAddrUpper32 = ttdsaXchg->smpresp.phyAddrUpper; + agSMPFrame->outFrameAddrLower32 = ttdsaXchg->smpresp.phyAddrLower; + agSMPFrame->outFrameLen = sizeof(smpRespReportGeneral_t); + + //agSMPFrame->phyId = ttdsaXchg->SMPphyId; + + /* smp response payload */ + Resp = (smpRespReportGeneral_t *)&(SMPResp->RespData); + osti_memset(Resp, 0, sizeof(smpRespReportGeneral_t)); + /* temp, hardcode smp general response */ + Resp->expanderChangeCount16[0] = 1; + Resp->expanderRouteIndexes16[0] = 2; + Resp->numOfPhys = 0x5; /* 0x1; */ + Resp->configuring_configurable = 0; + tdhexdump("smp general response", (bit8 *)Resp, sizeof(smpRespReportGeneral_t)); + +#ifdef RPM_SOC + /* not work yet because of high priority q */ + saSMPStart( + agRoot, + agIORequest, + agDevHandle, + agRequestType, + agSASRequestBody, + &ossaSMPCompleted + ); + #else + saSMPStart( + agRoot, + agIORequest, + 0, /* queue number */ + agDevHandle, + agRequestType, + agSASRequestBody, + &ossaSMPCompleted + ); +#endif + return; +} + + +osGLOBAL void +ttdsaSMPReqReceived( + agsaRoot_t *agRoot, + agsaDevHandle_t *agDevHandle, + agsaSMPFrameHeader_t *agFrameHeader, + agsaFrameHandle_t agFrameHandle, + bit32 agFrameLength, + bit32 phyId + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + ttdsaXchg_t *ttdsaXchg; + tdsaDeviceData_t *oneDeviceData = agNULL; + + + TI_DBG1(("ttdsaSMPReqReceived: start\n")); + + oneDeviceData = (tdsaDeviceData_t *)agDevHandle->osData; + + if (oneDeviceData == agNULL) + { + TI_DBG1(("ttdsaSMPReqReceived: no device data\n")); + return; + } + + ttdsaXchg = ttdsaXchgGetStruct(agRoot); + + if (ttdsaXchg == agNULL) + { + TI_DBG1(("ttdsaSMPReqReceived: no free xchg structures\n")); + return; + } + + + oneDeviceData->agDevHandle = agDevHandle; + oneDeviceData->agRoot = agRoot; + + /* saving the device */ + ttdsaXchg->DeviceData = oneDeviceData; + + ttdsaXchg->agRoot = agRoot; + ttdsaXchg->tiRoot = tiRoot; + + ttdsaXchg->SMPRequestBody.agIORequest.sdkData = agNULL; + + ttdsaXchg->SMPphyId = phyId; + + switch ( agFrameHeader->smpFunction ) + { + case SMP_REPORT_GENERAL: + { + /* must spec p392, rev7*/ + TI_DBG1(("ttdsaSMPReqReceived: REPORT_GENERAL\n")); + ttdsaReportGeneralRespSend(agRoot, agDevHandle, ttdsaXchg); + break; + } + case SMP_REPORT_MANUFACTURE_INFORMATION: + { + /* optional, spec p394, rev7*/ + TI_DBG1(("ttdsaSMPReqReceived: REPORT_MANUFACTURE_INFORMATION\n")); + ttdsaNotSupportRespSend(agRoot, agDevHandle, ttdsaXchg, SMP_REPORT_MANUFACTURE_INFORMATION); + break; + } + case SMP_DISCOVER: + { + /* must, spec p398, rev7*/ + TI_DBG1(("ttdsaSMPReqReceived: DISCOVER\n")); + ttdsaDiscoverRespSend(agRoot, agDevHandle, ttdsaXchg); + break; + } + default: + { + TI_DBG1(("ttdsaSMPReqReceived: UKNOWN or not yet supported 0x%x\n", agFrameHeader->smpFunction)); + ttdsaNotSupportRespSend(agRoot, agDevHandle, ttdsaXchg, (bit8) agFrameHeader->smpFunction); + break; + } + } + + return; +} diff --git a/sys/dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdtimer.c b/sys/dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdtimer.c new file mode 100644 index 000000000000..5b97e7707a6c --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdtimer.c @@ -0,0 +1,90 @@ +/******************************************************************************* +** +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +/*******************************************************************************/ +/** \file + * + * $RCSfile: ttdtimer.c,v $ + * + * Copyright 2006 PMC-Sierra, Inc. + * + * $Author: hasungwo $ + * $Revision: 112322 $ + * $Date: 2012-01-04 19:23:42 -0800 (Wed, 04 Jan 2012) $ + * + * This file contains initiator IO related functions in TD layer + * + */ +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#ifdef INITIATOR_DRIVER +#include +#include +#include +#endif + +#ifdef TARGET_DRIVER +#include "ttdglobl.h" +#include "ttdtxchg.h" +#include "ttdtypes.h" +#endif + +#include +#include + +/***************************************************************************** +* +* tiTargetTimerTick +* +* Purpose: This function is called by the os-specific module +* +* Parameters: +* +* tiRoot: Pointer to driver/port instance. +* +* +* Return: None +* +* +*****************************************************************************/ + +osGLOBAL void +tiTGTTimerTick(tiRoot_t *tiRoot) +{ + /* does nothing for now */ + return; +} diff --git a/sys/dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdtxchg.h b/sys/dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdtxchg.h new file mode 100644 index 000000000000..05be1eb95284 --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdtxchg.h @@ -0,0 +1,127 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +/*******************************************************************************/ +/** \file + * + * $RCSfile: ttdtxchg.h,v $ + * + * Copyright 2006 PMC-Sierra, Inc. + * + * + * #define and data structures for SAS target in SAS/SATA TD layer + * + */ + +typedef struct sas_resp_s +{ + agsaSSPResponseInfoUnit_t agResp; + bit8 RespData[4]; + bit8 SenseData[64]; +} sas_resp_t; + +typedef struct smp_resp_s +{ + bit8 RespData[1024]; /* SAS Spec */ +} smp_resp_t; + + +typedef struct +{ + bit8 *virtAddr; + bit32 phyAddrUpper; + bit32 phyAddrLower; + bit32 length; +} ttdsaDmaMemoryArea_t; + +struct tdsaDeviceData_s; + +/* I/O structurre */ +typedef struct ttdsaXchg_s +{ + + tdIORequestBody_t IORequestBody; /* has to be at the top */ + tdssSMPRequestBody_t SMPRequestBody; /* has to be at the second top */ + + tdList_t XchgLinks; + /* pointer to device(initiator) for which the I/O was initiated */ + struct tdsaDeviceData_s *DeviceData; + struct ttdsaXchg_s *pTMResp; + bit32 oustandingIos; + bit32 isAborting; + bit32 oslayerAborting; + bit32 isTMRequest; + bit32 index; /* index of structure */ + agsaSSPCmdInfoUnit_t agSSPCmndIU; + agsaSSPScsiTaskMgntReq_t agTMIU; + /* SSPTargetRead/SSPTargetWrite */ + bit32 XchType; + bit32 FrameType; /* cmnd or TM */ + agsaRoot_t *agRoot; + tiRoot_t *tiRoot; + /* indicates that at the completion of this data phase, this + exchange structure will be freed */ + bit32 statusSent; + bit32 responseSent; + bit32 readRspCollapsed : 1; + bit32 wrtRspCollapsed : 1; + bit32 readWrtCollapsedRes : 30; + tiTargetScsiCmnd_t tiTgtScsiCmnd; + + /* initiator tag a target received */ + bit16 tag; + bit64 dataLen; + bit32 respLen; + bit32 smprespLen; + ttdsaDmaMemoryArea_t resp; /* sas response */ + ttdsaDmaMemoryArea_t smpresp; /* sas smp response */ + bit32 usedEsgl; + /* for abort task io which is not founded in TD */ + bit32 io_found; + /* for debugging only */ + bit32 id; + /* PhyId for SMP*/ + bit32 SMPphyId; + bit32 state; + bit32 TLR; /* Transport Layer Retransmit bits */ + bit32 retries; /* retries */ + tiIORequest_t *tiIOToBeAbortedRequest; /* IO to be aborted */ + struct ttdsaXchg_s *XchgToBeAborted; /* Xchg to be aborted */ +} ttdsaXchg_t; + +/************************************************************************* +** now ttdssIOData_t and old tgtXchgData_t - +**************************************************************************/ + +typedef struct ttdsaXchgData_s +{ + bit32 maxNumXchgs; + tdList_t xchgFreeList; + tdList_t xchgBusyList; + bit32 noUsed; + bit32 noFreed; + bit32 noCmdRcvd; + bit32 noStartIo; + bit32 noSendRsp; + bit32 noCompleted; +} ttdsaXchgData_t; + + diff --git a/sys/dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdtypes.h b/sys/dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdtypes.h new file mode 100644 index 000000000000..09eab519456a --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdtypes.h @@ -0,0 +1,47 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +/*******************************************************************************/ +/** \file + * + * $RCSfile: ttdtypes.h,v $ + * + * Copyright 2006 PMC-Sierra, Inc. + * + * $Author: hasungwo $ + * $Revision: 112322 $ + * $Date: 2012-01-04 19:23:42 -0800 (Wed, 04 Jan 2012) $ + * + * data structures for SAS target in SAS/SATA TD layer + * + */ + +struct tdsaContext_s; + +typedef struct ttdssOperatingOption_s { + bit32 numXchgs; + bit32 UsecsPerTick; /* in micro seconds */ + /* bad name but to be consistent with configuration file */ + bit32 MaxTargets; + bit32 BlockSize; +} ttdssOperatingOption_t; + + diff --git a/sys/dev/pms/RefTisa/tisa/sassata/sata/host/ossasat.c b/sys/dev/pms/RefTisa/tisa/sassata/sata/host/ossasat.c new file mode 100644 index 000000000000..597b6ab0bd31 --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/sata/host/ossasat.c @@ -0,0 +1,11881 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +/*****************************************************************************/ +/** \file + * + * The file implementing SCSI/ATA Translation (SAT) for LL Layer callback + * + */ +/*****************************************************************************/ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#include +#include + +#ifdef SATA_ENABLE + +#include +#include +#include + +#include +#include +#include +#include + +#ifdef FDS_SM +#include +#include +#include +#endif + +#ifdef FDS_DM +#include +#include +#include +#endif + +#include +#include +#include + +#ifdef INITIATOR_DRIVER +#include +#include +#include +#endif + +#ifdef TARGET_DRIVER +#include +#include +#include +#endif + +#include +#include + +#include +#include + +/***************************************************************************** +*! \brief ossaSATACompleted +* +* This routine is called to complete a SATA request previously issued to the +* LL Layer in saSATAStart() +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* +* \return: none +* +*****************************************************************************/ +GLOBAL void +ossaSATACompleted( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + void *agFirstDword, + bit32 agIOInfoLen, + void *agParam + ) + +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&(tdsaRoot->tdsaAllShared); + tdIORequestBody_t *tdIORequestBody; + satIOContext_t *satIOContext; + satDeviceData_t *pSatDevData; + tdsaDeviceData_t *tdsaDeviceData = agNULL; + tdsaPortContext_t *onePortContext; + tiDeviceHandle_t *tiDeviceHandle = agNULL; + agsaDevHandle_t *agDevHandle = agNULL; + bit32 status; + tdsaDeviceData_t *oneDeviceData = agNULL; + + TDSA_OUT_ENTER(tiRoot); + + TI_DBG6(("ossaSATACompleted: agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", + agIORequest, agIOStatus, agIOInfoLen)); + + if (agIORequest == agNULL) + { + TI_DBG1(("ossaSATACompleted: agIORequest is NULL!!!!\n")); + return; + } + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + if (tdIORequestBody == agNULL) + { + TI_DBG1(("ossaSATACompleted: tdIORequestBody is NULL!!!!\n")); + return; + } + /* for debugging */ + if (tdIORequestBody->ioCompleted == agTRUE) + { + tiDeviceHandle = tdIORequestBody->tiDevHandle; + if (tiDeviceHandle == agNULL) + { + TI_DBG1(("ossaSATACompleted: tiDeviceHandle is NULL!!!!\n")); + return; + } + tdsaDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + TI_DBG1(("ossaSATACompleted: Error!!!!!! double completion\n")); + if (tdsaDeviceData == agNULL) + { + TI_DBG1(("ossaSATACompleted: tdsaDeviceData is NULL!!!!\n")); + return; + } + TI_DBG1(("ossaSATACompleted: did %d \n", tdsaDeviceData->id)); + return; + } + + tdIORequestBody->ioCompleted = agTRUE; + satIOContext = &(tdIORequestBody->transport.SATA.satIOContext); + + if (satIOContext == agNULL) + { + TI_DBG1(("ossaSATACompleted: satIOContext is NULL!!!!\n")); + return; + } + + pSatDevData = satIOContext->pSatDevData; + + if (tdIORequestBody->tiDevHandle != agNULL) + { + oneDeviceData = (tdsaDeviceData_t *)tdIORequestBody->tiDevHandle->tdData; + } + + if (pSatDevData == agNULL && oneDeviceData != agNULL) + { + TI_DBG1(("ossaSATACompleted: pSatDevData is NULL, loc 1, wrong\n")); + pSatDevData = &(oneDeviceData->satDevData); + } + + if (pSatDevData == agNULL) + { + TI_DBG1(("ossaSATACompleted: pSatDevData is NULL loc 2, wrong\n")); + if (satIOContext->satOrgIOContext == agNULL) + { + TI_DBG1(("ossaSATACompleted: external command\n")); + } + else + { + TI_DBG1(("ossaSATACompleted: internal command\n")); + } + goto ext; + } + + tdsaDeviceData = (tdsaDeviceData_t *)pSatDevData->satSaDeviceData; + if (oneDeviceData != tdsaDeviceData) + { + if (satIOContext->satOrgIOContext == agNULL) + { + TI_DBG1(("ossaSATACompleted: diff device handle; external command\n")); + } + else + { + TI_DBG1(("ossaSATACompleted: diff device handle; internal command\n")); + } + } + + if (tdsaDeviceData == agNULL) + { + TI_DBG1(("ossaSATACompleted: tdsaDeviceData is NULL!!!!\n")); + return; + } + + onePortContext = tdsaDeviceData->tdPortContext; + + /* retries in OSSA_IO_XFER_OPEN_RETRY_TIMEOUT */ + if (agIOStatus == OSSA_IO_XFER_OPEN_RETRY_TIMEOUT) + { + if (tdsaDeviceData->valid == agTRUE && tdsaDeviceData->registered == agTRUE && + tdsaDeviceData->tdPortContext != agNULL ) + { + if (tdIORequestBody->reTries <= OPEN_RETRY_RETRIES) /* 10 */ + { + agDevHandle = tdsaDeviceData->agDevHandle; + status = saSATAStart( agRoot, + agIORequest, + tdsaRotateQnumber(tiRoot, tdsaDeviceData), + agDevHandle, + satIOContext->reqType, + &(tdIORequestBody->transport.SATA.agSATARequestBody), + satIOContext->sataTag, + ossaSATACompleted); + + if (status == AGSA_RC_SUCCESS) + { + TI_DBG1(("ossaSATACompleted: retried\n")); + tdIORequestBody->ioStarted = agTRUE; + tdIORequestBody->ioCompleted = agFALSE; + tdIORequestBody->reTries++; + goto ext; + } + else + { + TI_DBG1(("ossaSATACompleted: retry failed\n")); + tdIORequestBody->ioStarted = agFALSE; + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->reTries = 0; + } + } + else + { + /* retries is over, do nothing */ + TI_DBG1(("ossaSATACompleted: retry is over and fail\n")); + tdIORequestBody->reTries = 0; + } + } + else + { + TI_DBG1(("ossaSATACompleted: incorrect device state or no portcontext\n")); + tdIORequestBody->reTries = 0; + } + } /* if OSSA_IO_XFER_OPEN_RETRY_TIMEOUT*/ + + /* release tag value for SATA */ + if ( (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_WRITE) || + (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_READ) ) + { + satTagRelease(tiRoot, pSatDevData, satIOContext->sataTag); + } + + /* send SMP_PHY_CONTROL_HARD_RESET */ + if (agIOStatus == OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY && tdsaAllShared->FCA) + { + if (pSatDevData->NumOfFCA <= 0) /* does SMP HARD RESET only upto one time */ + { + TI_DBG1(("ossaSATACompleted: OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY; sending HARD_RESET\n")); + pSatDevData->NumOfFCA++; + tdsaPhyControlSend(tiRoot, + tdsaDeviceData, + SMP_PHY_CONTROL_HARD_RESET, + agNULL, + tdsaRotateQnumber(tiRoot, tdsaDeviceData) + ); + } + else + { + /* given up after one time of SMP HARD RESET; */ + TI_DBG1(("ossaSATACompleted: OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY; NO!!! sending HARD_RESET\n")); + if (tdsaDeviceData->registered == agTRUE && tdsaAllShared->ResetInDiscovery == 0) + { + /* + 1. remove this device + 2. device removal event + */ + tdsaAbortAll(tiRoot, agRoot, tdsaDeviceData); + tdsaDeviceData->valid = agFALSE; + tdsaDeviceData->valid2 = agFALSE; + tdsaDeviceData->registered = agFALSE; +// pSatDevData->NumOfFCA = 0; + ostiInitiatorEvent( + tiRoot, + onePortContext->tiPortalContext, + agNULL, + tiIntrEventTypeDeviceChange, + tiDeviceRemoval, + agNULL + ); + } + } + } + + if (agIOStatus == OSSA_IO_ABORTED) + { + /* + free abort IO request itself - agParam; done in ossaSATAEvent() + */ + } + /* just for debugging */ + if (agIOStatus == OSSA_IO_DS_NON_OPERATIONAL) + { + TI_DBG1(("ossaSATACompleted: agIOStatus is OSSA_IO_DS_NON_OPERATIONAL\n")); + } + if (agIOStatus == OSSA_IO_DS_IN_RECOVERY) + { + TI_DBG1(("ossaSATACompleted: agIOStatus is OSSA_IO_DS_IN_RECOVERY\n")); + } + + satIOContext->satCompleteCB( agRoot, + agIORequest, + agIOStatus, + agFirstDword, + agIOInfoLen, + agParam, + satIOContext); +ext: + TDSA_OUT_LEAVE(tiRoot); +} + +/***************************************************************************** +*! \brief satPacketCB +* +* This routine is a callback function called from ossaSATACompleted(). +* This CB routine deals with normal Packet command I/O SATA request. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ + +void satPacketCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdIORequestBody; + tdIORequestBody_t *tdOrgIORequestBody; + satIOContext_t *satIOContext; + satIOContext_t *satOrgIOContext; + satIOContext_t *satNewIOContext; + satInternalIo_t *satIntIo; + satInternalIo_t *satNewIntIo = agNULL; + satDeviceData_t *satDevData; + scsiRspSense_t *pSense; + tiIORequest_t *tiOrgIORequest; + tiIniScsiCmnd_t *scsiCmnd; + bit32 interruptContext = osData->IntContext; + bit8 bSenseKey = 0; + bit16 bSenseCodeInfo = 0; + bit32 status = 0; + + TI_DBG4(("satPacketCB:agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate tiIOContext */ + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satIOContext = (satIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + satDevData = satIOContext->pSatDevData; + + /*ttttttthe one */ + if (satIntIo == agNULL) + { + TI_DBG4(("satPacketCB: External satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + tiOrgIORequest = tdIORequestBody->tiIORequest; + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + else + { + TI_DBG4(("satPacketCB: Internal satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + TI_DBG4(("satPacketCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + TI_DBG4(("satPacketCB: satOrgIOContext is NOT NULL\n")); + } + tdOrgIORequestBody = (tdIORequestBody_t *)satOrgIOContext->tiRequestBody; + tiOrgIORequest = (tiIORequest_t *)tdOrgIORequestBody->tiIORequest; + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + + /* Parse CDB */ + switch(scsiCmnd->cdb[0]) + { + case SCSIOPC_TEST_UNIT_READY: + //satTestUnitReadyCB(agRoot, agIORequest, agIOStatus, agFirstDword, agIOInfoLen, agParam, ioContext); + //break; + case SCSIOPC_GET_EVENT_STATUS_NOTIFICATION: + //break; + case SCSIOPC_READ_CAPACITY_10: + case SCSIOPC_READ_CAPACITY_16: + //satPacketReadCapacityCB(agRoot, agIORequest, agIOStatus, agFirstDword, agIOInfoLen, agParam, ioContext); + //break; + default: + break; + } + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + /* interal structure free */ + satFreeIntIoResource( tiRoot, satDevData, satIntIo); + + if( agIOStatus == OSSA_IO_SUCCESS && agFirstDword == agNULL) + { + TI_DBG1(("satPacketCB: agIOStatus == OSSA_IO_SUCCESS, agFirstDword == agNULL \n")); + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + interruptContext); + } + else if (agIOStatus == OSSA_IO_SUCCESS && agFirstDword != agNULL) + { + TI_DBG1(("satPacketCB: wrong. agIOStatus == OSSA_IO_SUCCESS && agFirstDword != agNULL \n")); + satNewIntIo = satAllocIntIoResource( tiRoot, + tiOrgIORequest, + satDevData, + 32, + satNewIntIo); + if (satNewIntIo == agNULL) + { + /* memory allocation failure */ + /* just translate the ATAPI error register to sense information */ + satTranslateATAPIErrorsToSCSIErrors( + scsiCmnd->cdb[0], + agFirstDword->D2H.status, + agFirstDword->D2H.error, + &bSenseKey, + &bSenseCodeInfo + ); + satSetSensePayload(pSense, bSenseKey, 0, bSenseCodeInfo, satOrgIOContext); + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + interruptContext); + TI_DBG1(("satPacketCB: momory allocation fails\n")); + return; + } /* end memory allocation */ + + satNewIOContext = satPrepareNewIO(satNewIntIo, + tiOrgIORequest, + satDevData, + scsiCmnd, + satOrgIOContext + ); + /* sends request sense to ATAPI device for acquiring sense information */ + status = satRequestSenseForATAPI(tiRoot, + &satNewIntIo->satIntTiIORequest, + satNewIOContext->ptiDeviceHandle, + &satNewIntIo->satIntTiScsiXchg, + satNewIOContext + ); + if (status != tiSuccess) + { + satFreeIntIoResource( tiRoot, + satDevData, + satNewIntIo); + /* just translate the ATAPI error register to sense information */ + satTranslateATAPIErrorsToSCSIErrors( + scsiCmnd->cdb[0], + agFirstDword->D2H.status, + agFirstDword->D2H.error, + &bSenseKey, + &bSenseCodeInfo + ); + satSetSensePayload(pSense, bSenseKey, 0, bSenseCodeInfo, satOrgIOContext); + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + interruptContext); + TI_DBG1(("satPacketCB: failed to call satRequestSenseForATAPI()\n")); + } + } + else if (agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satPacketCB: wrong. agIOStatus != OSSA_IO_SUCCESS, status %d\n", agIOStatus)); + itdsatProcessAbnormalCompletion( + agRoot, + agIORequest, + agIOStatus, + agFirstDword, + agIOInfoLen, + agParam, + satIOContext); + } + else + { + TI_DBG1(("satPacketCB: Unknown error \n")); + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + interruptContext); + } +} +/***************************************************************************** +*! \brief satRequestSenseForATAPICB +* +* This routine is a callback function called from ossaSATACompleted(). +* This CB routine deals with normal non-chained data I/O SATA request. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void satRequestSenseForATAPICB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdIORequestBody; + tdIORequestBody_t *tdOrgIORequestBody; + satIOContext_t *satIOContext; + satIOContext_t *satOrgIOContext; + satInternalIo_t *satIntIo; + satDeviceData_t *satDevData; + tiIORequest_t *tiOrgIORequest; + bit32 interruptContext = osData->IntContext; + + TI_DBG4(("satPacketCB:agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate tiIOContext */ + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satIOContext = (satIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + satDevData = satIOContext->pSatDevData; + + /*ttttttthe one */ + if (satIntIo == agNULL) + { + TI_DBG4(("satPacketCB: External satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + tiOrgIORequest = tdIORequestBody->tiIORequest; + } + else + { + TI_DBG4(("satPacketCB: Internal satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + TI_DBG4(("satPacketCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + TI_DBG4(("satPacketCB: satOrgIOContext is NOT NULL\n")); + } + tdOrgIORequestBody = (tdIORequestBody_t *)satOrgIOContext->tiRequestBody; + tiOrgIORequest = (tiIORequest_t *)tdOrgIORequestBody->tiIORequest; + } + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + /* copy the request sense buffer to original IO buffer*/ + if (satIntIo != agNULL) + { + osti_memcpy(satOrgIOContext->pTiSenseData->senseData, satIntIo->satIntDmaMem.virtPtr, SENSE_DATA_LENGTH); + satOrgIOContext->pTiSenseData->senseLen = SENSE_DATA_LENGTH; + /* interal structure free */ + satFreeIntIoResource( tiRoot, satDevData, satIntIo); + } + + /* notify the OS to complete this SRB */ + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + interruptContext); +} +/***************************************************************************** +*! \brief satSetFeaturesPIOCB +* +* This routine is a callback function called from ossaSATACompleted(). +* This CB routine deals with normal non-chained data I/O SATA request. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void satSetFeaturesPIOCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdIORequestBody; + tdIORequestBody_t *tdOrgIORequestBody; + satIOContext_t *satIOContext; + satIOContext_t *satOrgIOContext; + satIOContext_t *satNewIOContext; + satInternalIo_t *satIntIo; + satInternalIo_t *satNewIntIo = agNULL; + satDeviceData_t *satDevData; + tiIORequest_t *tiOrgIORequest; + tiIniScsiCmnd_t *scsiCmnd; + bit32 status; + + TI_DBG3(("satSetFeaturesPIOCB start\n")); + + /* internally generate tiIOContext */ + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satIOContext = (satIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + satDevData = satIOContext->pSatDevData; + + /*ttttttthe one */ + if (satIntIo == agNULL) + { + TI_DBG4(("satSetFeaturesPIOCB: External satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + tiOrgIORequest = tdIORequestBody->tiIORequest; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + else + { + TI_DBG4(("satSetFeaturesPIOCB: Internal satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + TI_DBG4(("satSetFeaturesPIOCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + TI_DBG4(("satSetFeaturesPIOCB: satOrgIOContext is NOT NULL\n")); + } + tdOrgIORequestBody = (tdIORequestBody_t *)satOrgIOContext->tiRequestBody; + tiOrgIORequest = (tiIORequest_t *)tdOrgIORequestBody->tiIORequest; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + /* interal structure free */ + satFreeIntIoResource(tiRoot, + satDevData, + satIntIo); + + /*if the ATAPI device support DMA, then enble this feature*/ + if (satDevData->satDMASupport && satDevData->satDMAEnabled) + { + satNewIntIo = satAllocIntIoResource( tiRoot, + tiOrgIORequest, + satDevData, + 0, + satNewIntIo); + if (satNewIntIo == agNULL) + { + TI_DBG1(("satSetFeaturesPIOCB: momory allocation fails\n")); + return; + } /* end memory allocation */ + + satNewIOContext = satPrepareNewIO(satNewIntIo, + tiOrgIORequest, + satDevData, + scsiCmnd, + satOrgIOContext + ); + /* sends either ATA SET FEATURES based on DMA bit */ + status = satSetFeatures(tiRoot, + &satNewIntIo->satIntTiIORequest, + satNewIOContext->ptiDeviceHandle, + &satNewIntIo->satIntTiScsiXchg, + satNewIOContext, + agTRUE + ); + if (status != tiSuccess) + { + satFreeIntIoResource( tiRoot, satDevData, satNewIntIo); + TI_DBG1(("satSetFeaturesPIOCB: failed to call satSetFeatures()\n")); + } + } +} + +/***************************************************************************** +*! \brief satSetFeaturesCB +* +* This routine is a callback function called from ossaSATACompleted(). +* This CB routine deals with normal non-chained data I/O SATA request. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void satSetFeaturesCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdIORequestBody; + tdIORequestBody_t *tdOrgIORequestBody = agNULL; + satIOContext_t *satIOContext; + satIOContext_t *satOrgIOContext; + satInternalIo_t *satIntIo; + satDeviceData_t *satDevData; + tdsaPortContext_t *onePortContext = agNULL; + tiPortalContext_t *tiPortalContext = agNULL; + tdsaDeviceData_t *oneDeviceData = agNULL; + bit8 PhyID =0; + TI_DBG3(("satSetFeaturesCB start\n")); + + /* internally generate tiIOContext */ + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satIOContext = (satIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + satDevData = satIOContext->pSatDevData; + oneDeviceData = (tdsaDeviceData_t *)tdIORequestBody->tiDevHandle->tdData; + onePortContext = oneDeviceData->tdPortContext; + if (onePortContext == agNULL) + { + TI_DBG4(("satSetFeaturesCB: onePortContext is NULL, wrong\n")); + return; + } + tiPortalContext = onePortContext->tiPortalContext; + PhyID = oneDeviceData->phyID; + /*ttttttthe one */ + if (satIntIo == agNULL) + { + TI_DBG4(("satSetFeaturesCB: External satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + } + else + { + TI_DBG4(("satSetFeaturesCB: Internal satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + TI_DBG4(("satSetFeaturesCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + TI_DBG4(("satSetFeaturesCB: satOrgIOContext is NOT NULL\n")); + } + tdOrgIORequestBody = (tdIORequestBody_t *)satOrgIOContext->tiRequestBody; + } + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + /* interal structure free */ + satFreeIntIoResource(tiRoot, + satDevData, + satIntIo); + + + /* clean up TD layer's IORequestBody */ + if (tdOrgIORequestBody!= agNULL) + { + ostiFreeMemory(tiRoot, + tdOrgIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + + if (onePortContext != agNULL) + { + /* this condition is for tdsaDiscoveryStartIDDevCB routine*/ + if (onePortContext->DiscoveryState == ITD_DSTATE_COMPLETED) + { + TI_DBG1(("satSetFeaturesCB: ID completed after discovery is done; tiDeviceArrival\n")); + /* in case registration is finished after discovery is finished */ + ostiInitiatorEvent( + tiRoot, + tiPortalContext, + agNULL, + tiIntrEventTypeDeviceChange, + tiDeviceArrival, + agNULL + ); + return; + } + TI_DBG2(("satSetFeaturesCB: pid %d\n", tdsaAllShared->Ports[PhyID].portContext->id)); + /* the below codes is for satAddSATAIDDevCB routine*/ + /* notifying link up */ + ostiPortEvent ( + tiRoot, + tiPortLinkUp, + tiSuccess, + (void *)tdsaAllShared->Ports[PhyID].tiPortalContext + ); + #ifdef INITIATOR_DRIVER + /* triggers discovery */ + ostiPortEvent( + tiRoot, + tiPortDiscoveryReady, + tiSuccess, + (void *) tdsaAllShared->Ports[PhyID].tiPortalContext + ); + #endif + } + else + { + TI_DBG1(("satSetFeaturesCB: onePortContext is NULL, wrong\n")); + } +} +/***************************************************************************** +*! \brief satDeviceResetCB +* +* This routine is a callback function called from ossaSATACompleted(). +* This CB routine deals with normal non-chained data I/O SATA request. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void satDeviceResetCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + /* callback for satResetDevice */ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdIORequestBody; + tdIORequestBody_t *tdOrgIORequestBody = agNULL; + satIOContext_t *satIOContext; + satIOContext_t *satOrgIOContext; +// satIOContext_t *satNewIOContext; + satInternalIo_t *satIntIo; +// satInternalIo_t *satNewIntIo = agNULL; + satDeviceData_t *satDevData; + tiIORequest_t *tiOrgIORequest; +#ifdef TD_DEBUG_ENABLE + bit32 ataStatus = 0; + bit32 ataError; + agsaFisPioSetupHeader_t *satPIOSetupHeader = agNULL; +#endif +// bit32 status; + bit32 report = agFALSE; + bit32 AbortTM = agFALSE; + + TI_DBG1(("satDeviceResetCB: start\n")); + + TI_DBG6(("satDeviceResetCB: agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satIOContext = (satIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + satDevData = satIOContext->pSatDevData; + + if (satIntIo == agNULL) + { + TI_DBG6(("satDeviceResetCB: External, OS generated\n")); + satOrgIOContext = satIOContext; + tiOrgIORequest = tdIORequestBody->tiIORequest; + } + else + { + TI_DBG6(("satDeviceResetCB: Internal, TD generated\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + TI_DBG6(("satDeviceResetCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + TI_DBG6(("satDeviceResetCB: satOrgIOContext is NOT NULL\n")); + } + tdOrgIORequestBody = (tdIORequestBody_t *)satOrgIOContext->tiRequestBody; + tiOrgIORequest = (tiIORequest_t *)tdOrgIORequestBody->tiIORequest; + } + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satDeviceResetCB: wrong. agFirstDword is NULL when error, status %d\n", agIOStatus)); + + if (satOrgIOContext->NotifyOS == agTRUE) + { + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMFailed, + tiOrgIORequest ); + } + + satDevData->satTmTaskTag = agNULL; + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + if (agIOStatus == OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_BREAK || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_UNKNOWN_ERROR || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY + ) + { + TI_DBG1(("satDeviceResetCB: OSSA_IO_OPEN_CNX_ERROR\n")); + + if (satOrgIOContext->NotifyOS == agTRUE) + { + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMFailed, + tiOrgIORequest ); + } + + satDevData->satTmTaskTag = agNULL; + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* only agsaFisPioSetup_t is expected */ +#ifdef TD_DEBUG_ENABLE + satPIOSetupHeader = (agsaFisPioSetupHeader_t *)&(agFirstDword->PioSetup); + ataStatus = satPIOSetupHeader->status; /* ATA Status register */ + ataError = satPIOSetupHeader->error; /* ATA Eror register */ +#endif + TI_DBG1(("satDeviceResetCB: ataStatus 0x%x ataError 0x%x\n", ataStatus, ataError)); + + if (satOrgIOContext->NotifyOS == agTRUE) + { + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMFailed, + tiOrgIORequest ); + } + + satDevData->satTmTaskTag = agNULL; + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + /* success */ + if (satOrgIOContext->TMF == AG_ABORT_TASK) + { + AbortTM = agTRUE; + } + + if (satOrgIOContext->NotifyOS == agTRUE) + { + report = agTRUE; + } + + if (AbortTM == agTRUE) + { + TI_DBG1(("satDeResetDeviceCB: calling satAbort\n")); + satAbort(agRoot, satOrgIOContext->satToBeAbortedIOContext); + } + satDevData->satTmTaskTag = agNULL; + + satDevData->satDriveState = SAT_DEV_STATE_NORMAL; + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + TI_DBG1(("satDeviceResetCB: satPendingIO %d satNCQMaxIO %d\n", satDevData->satPendingIO, satDevData->satNCQMaxIO )); + TI_DBG1(("satDeviceResetCB: satPendingNCQIO %d satPendingNONNCQIO %d\n", satDevData->satPendingNCQIO, satDevData->satPendingNONNCQIO)); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + /* clean up TD layer's IORequestBody */ + if (tdOrgIORequestBody != agNULL) + { + ostiFreeMemory( + tiRoot, + tdOrgIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + else + { + TI_DBG1(("satDeviceResetCB: tdOrgIORequestBody is NULL, wrong\n")); + } + + + if (report) + { + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMOK, + tiOrgIORequest ); + } + + + TI_DBG5(("satDeviceResetCB: device %p pending IO %d\n", satDevData, satDevData->satPendingIO)); + TI_DBG6(("satDeviceResetCB: end\n")); + return; +} + +/***************************************************************************** +*! \brief satExecuteDeviceDiagnosticCB +* +* This routine is a callback function called from ossaSATACompleted(). +* This CB routine deals with normal non-chained data I/O SATA request. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void satExecuteDeviceDiagnosticCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdIORequestBody; + satIOContext_t *satIOContext; + satIOContext_t *satOrgIOContext; + satInternalIo_t *satIntIo; + satDeviceData_t *satDevData; + + TI_DBG3(("satExecuteDeviceDiagnosticCB start\n")); + + /* internally generate tiIOContext */ + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satIOContext = (satIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + satDevData = satIOContext->pSatDevData; + + /*ttttttthe one */ + if (satIntIo == agNULL) + { + TI_DBG4(("satExecuteDeviceDiagnosticCB: External satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + } + else + { + TI_DBG4(("satExecuteDeviceDiagnosticCB: Internal satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + TI_DBG4(("satExecuteDeviceDiagnosticCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + TI_DBG4(("satExecuteDeviceDiagnosticCB: satOrgIOContext is NOT NULL\n")); + } + } + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + /* interal structure free */ + satFreeIntIoResource(tiRoot, + satDevData, + satIntIo); +} +/***************************************************************************** +*! \brief satNonChainedDataIOCB +* +* This routine is a callback function called from ossaSATACompleted(). +* This CB routine deals with normal non-chained data I/O SATA request. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ + +void satNonChainedDataIOCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdIORequestBody; + bit32 interruptContext = osData->IntContext; + satIOContext_t *satIOContext; + satInternalIo_t *SatIntIo; + satDeviceData_t *SatDevData; + + TI_DBG6(("satNonChainedDataIOCB: agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", + agIORequest, agIOStatus, agIOInfoLen)); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satIOContext = (satIOContext_t *) ioContext; + SatIntIo = satIOContext->satIntIoContext; + SatDevData = satIOContext->pSatDevData; + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + /* interal structure free */ + satFreeIntIoResource( tiRoot, + SatDevData, + SatIntIo); + + /* Process completion */ + if( (agIOStatus == OSSA_IO_SUCCESS) && (agIOInfoLen == 0)) + { + TI_DBG5(("satNonChainedDataIOCB: success\n")); + TI_DBG5(("satNonChainedDataIOCB: success agIORequest %p\n", agIORequest)); + /* + * Command was completed OK, this is the normal path. + * Now call the OS-App Specific layer about this completion. + */ + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + interruptContext); + } + else + { + TI_DBG1(("satNonChainedDataIOCB: calling itdsatProcessAbnormalCompletion\n")); + /* More checking needed */ + itdsatProcessAbnormalCompletion( agRoot, + agIORequest, + agIOStatus, + agFirstDword, + agIOInfoLen, + agParam, + satIOContext); + } + + return; + + +} +/***************************************************************************** +*! \brief satChainedDataIOCB +* +* This routine is a callback function called from ossaSATACompleted(). +* This CB routine deals with normal chained data I/O SATA request. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void satChainedDataIOCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdIORequestBody; + tdIORequestBody_t *tdOrgIORequestBody; + satIOContext_t *satIOContext; + satIOContext_t *satOrgIOContext; + satIOContext_t *satNewIOContext; + satInternalIo_t *satIntIo; + satInternalIo_t *satNewIntIo = agNULL; + satDeviceData_t *satDevData; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + tiIORequest_t *tiOrgIORequest; + + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + bit32 status = tiError; + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + bit32 dataLength; + + TI_DBG6(("satChainedDataIOCB: agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", + agIORequest, agIOStatus, agIOInfoLen)); + + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satIOContext = (satIOContext_t *) ioContext; + if (satIOContext == agNULL) + { + TI_DBG1(("satChainedDataIOCB: satIOContext is NULL\n")); + return; + } + satIntIo = satIOContext->satIntIoContext; + satDevData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + + if (satIntIo == agNULL) + { + TI_DBG5(("satChainedDataIOCB: External satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + tiOrgIORequest = tdIORequestBody->tiIORequest; + pSense = satIOContext->pSense; + scsiCmnd = satIOContext->pScsiCmnd; + } + else + { + TI_DBG5(("satChainedDataIOCB: Internal satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + TI_DBG5(("satChainedDataIOCB: satOrgIOContext is NULL\n")); + } + else + { + TI_DBG5(("satChainedDataIOCB: satOrgIOContext is NOT NULL\n")); + } + + tdOrgIORequestBody = (tdIORequestBody_t *)satOrgIOContext->tiRequestBody; + tiOrgIORequest = (tiIORequest_t *)tdOrgIORequestBody->tiIORequest; + + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satChainedDataIOCB: wrong. agFirstDword is NULL when error, status %d\n", agIOStatus)); + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + /* + checking IO status, FIS type and error status + */ + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* agsaFisPioSetup_t or agsaFisRegDeviceToHost_t or agsaFisSetDevBits_t for read + agsaFisRegDeviceToHost_t or agsaFisSetDevBits_t for write + first, assumed to be Reg Device to Host FIS + This is OK to just find fis type + */ + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + /* for debugging */ + if( (statDevToHostFisHeader->fisType != PIO_SETUP_DEV_TO_HOST_FIS) && + (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) && + (statDevToHostFisHeader->fisType != SET_DEV_BITS_FIS) + ) + { + TI_DBG1(("satChainedDataIOCB: FAILED, Wrong FIS type 0x%x\n", statDevToHostFisHeader->fisType)); + } + + /* for debugging */ + if ( (ataStatus & ERR_ATA_STATUS_MASK) || + (ataStatus & DF_ATA_STATUS_MASK) + ) + { + TI_DBG1(("satChainedDataIOCB: FAILED, error status and command 0x%x\n", hostToDevFis->h.command)); + } + + /* the function below handles abort case */ + itdsatDelayedProcessAbnormalCompletion(agRoot, + agIORequest, + agIOStatus, + agFirstDword, + agIOInfoLen, + agParam, + satIOContext); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } /* end of error */ + + switch (hostToDevFis->h.command) + { + case SAT_READ_DMA: /* fall through */ + case SAT_READ_SECTORS: /* fall through */ + case SAT_READ_DMA_EXT: /* fall through */ + case SAT_READ_SECTORS_EXT: /* fall through */ + case SAT_READ_FPDMA_QUEUED: /* fall through */ + case SAT_WRITE_DMA: /* fall through */ + case SAT_WRITE_SECTORS:/* fall through */ + case SAT_WRITE_DMA_FUA_EXT: /* fall through */ + case SAT_WRITE_DMA_EXT: /* fall through */ + case SAT_WRITE_SECTORS_EXT: /* fall through */ + case SAT_WRITE_FPDMA_QUEUED: + + TI_DBG5(("satChainedDataIOCB: READ/WRITE success case\n")); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + /* done with internally genereated SAT_SMART_RETURN_STATUS */ + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + /* let's loop till TL */ + + /* lba = lba + tl + loopnum--; + if (loopnum == 0) done + */ + (satOrgIOContext->LoopNum)--; + if (satOrgIOContext->LoopNum == 0) + { + /* done with read */ + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + return; + } + if (satOrgIOContext->superIOFlag) + { + dataLength = ((tiSuperScsiInitiatorRequest_t *) satOrgIOContext->tiScsiXchg)->scsiCmnd.expDataLength; + } + else + { + dataLength = ((tiScsiInitiatorRequest_t *) satOrgIOContext->tiScsiXchg)->scsiCmnd.expDataLength; + } + + satNewIntIo = satAllocIntIoResource( tiRoot, + tiOrgIORequest, + satDevData, + dataLength, + satNewIntIo); + if (satNewIntIo == agNULL) + { + /* memory allocation failure */ + satFreeIntIoResource( tiRoot, + satDevData, + satNewIntIo); + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOFailed, + tiDetailOtherError, + agNULL, + satOrgIOContext->interruptContext ); + + TI_DBG1(("satChainedDataIOCB: momory allocation fails\n")); + return; + } /* end of memory allocation failure */ + + /* + * Need to initialize all the fields within satIOContext + */ + + satNewIOContext = satPrepareNewIO( + satNewIntIo, + tiOrgIORequest, + satDevData, + scsiCmnd, + satOrgIOContext + ); + + /* sending another ATA command */ + switch (scsiCmnd->cdb[0]) + { + case SCSIOPC_READ_6: + /* no loop should occur with READ6 since it fits in one ATA command */ + break; + case SCSIOPC_READ_10: /* fall through */ + case SCSIOPC_READ_12: /* fall through */ + case SCSIOPC_READ_16: /* fall through */ + status = satRead_1( tiRoot, + &satNewIntIo->satIntTiIORequest, + satNewIOContext->ptiDeviceHandle, + &satNewIntIo->satIntTiScsiXchg, + satNewIOContext); + break; + case SCSIOPC_WRITE_6: + /* no loop should occur with WRITE6 since it fits in one ATA command */ + break; + case SCSIOPC_WRITE_10: /* fall through */ + case SCSIOPC_WRITE_12: /* fall through */ + case SCSIOPC_WRITE_16: /* fall through */ + status = satWrite_1( tiRoot, + &satNewIntIo->satIntTiIORequest, + satNewIOContext->ptiDeviceHandle, + &satNewIntIo->satIntTiScsiXchg, + satNewIOContext); + break; + default: + TI_DBG1(("satChainedDataIOCB: success but default case scsi cmd 0x%x ata cmd 0x%x\n",scsiCmnd->cdb[0], hostToDevFis->h.command)); + status = tiError; + break; + } + + + + if (status != tiSuccess) + { + satFreeIntIoResource( tiRoot, + satDevData, + satNewIntIo); + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOFailed, + tiDetailOtherError, + agNULL, + satOrgIOContext->interruptContext ); + TI_DBG1(("satChainedDataIOCB: calling satRead10_1 fails\n")); + return; + } + + break; + + + default: + TI_DBG1(("satChainedDataIOCB: success but default case command 0x%x\n",hostToDevFis->h.command)); + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOFailed, + tiDetailOtherError, + agNULL, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + break; + } + + + return; +} +void satNonChainedWriteNVerifyCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdIORequestBody; + tdIORequestBody_t *tdOrgIORequestBody; + satIOContext_t *satIOContext; + satIOContext_t *satOrgIOContext; + satIOContext_t *satNewIOContext; + satInternalIo_t *satIntIo; + satInternalIo_t *satNewIntIo = agNULL; + satDeviceData_t *satDevData; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + tiIORequest_t *tiOrgIORequest; + + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + bit32 status; + tiScsiInitiatorRequest_t *tiScsiRequest; /* tiScsiXchg */ + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + agsaFisSetDevBitsHeader_t *statSetDevBitFisHeader = agNULL; + + TI_DBG5(("satNonChainedWriteNVerifyCB:agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate tiIOContext */ + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satIOContext = (satIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + satDevData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + + /* SPC: Self-Test Result Log page */ + tiScsiRequest = satIOContext->tiScsiXchg; + + if (satIntIo == agNULL) + { + TI_DBG4(("satNonChainedWriteNVerifyCB: External satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + tiOrgIORequest = tdIORequestBody->tiIORequest; + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + else + { + TI_DBG4(("satNonChainedWriteNVerifyCB: Internal satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + TI_DBG4(("satNonChainedWriteNVerifyCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + TI_DBG4(("satNonChainedWriteNVerifyCB: satOrgIOContext is NOT NULL\n")); + } + tdOrgIORequestBody = (tdIORequestBody_t *)satOrgIOContext->tiRequestBody; + tiOrgIORequest = (tiIORequest_t *)tdOrgIORequestBody->tiIORequest; + + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satNonChainedWriteNVerifyCB: wrong. agFirstDword is NULL when error, status %d\n", agIOStatus)); + ostiInitiatorIOCompleted ( + tiRoot, + tiOrgIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* + FIS type should be either REG_DEV_TO_HOST_FIS or SET_DEV_BITS_FIS + */ + /* First, assumed to be Reg Device to Host FIS */ + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + } + + if (agIOStatus != OSSA_IO_SUCCESS) + { + if (statDevToHostFisHeader->fisType == SET_DEV_BITS_FIS) + { + statSetDevBitFisHeader = (agsaFisSetDevBitsHeader_t *)&(agFirstDword->D2H); + + /* Get ATA Status register */ + ataStatus = (statSetDevBitFisHeader->statusHi_Lo & 0x70); /* bits 4,5,6 */ + ataStatus = ataStatus | (statSetDevBitFisHeader->statusHi_Lo & 0x07); /* bits 0,1,2 */ + + /* ATA Eror register */ + } + } + + + if( agIOStatus != OSSA_IO_SUCCESS) + { + /* + checking IO status, FIS type and error status + FIS type should be either REG_DEV_TO_HOST_FIS or SET_DEV_BITS_FIS + Both have fisType in the same location + */ + if ( ((statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) && + (statDevToHostFisHeader->fisType != SET_DEV_BITS_FIS)) || + ((ataStatus & ERR_ATA_STATUS_MASK) || (ataStatus & DF_ATA_STATUS_MASK)) + ) + { + /* for debugging */ + if( agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satNonChainedWriteNVerifyCB: FAILED, NOT IO_SUCCESS\n")); + } + else if (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) + { + TI_DBG1(("satNonChainedWriteNVerifyCB: FAILED, Wrong FIS type 0x%x\n",statDevToHostFisHeader->fisType)); + } + else if (statDevToHostFisHeader->fisType != SET_DEV_BITS_FIS) + { + TI_DBG1(("satNonChainedWriteNVerifyCB: FAILED, Wrong FIS type 0x%x\n",statDevToHostFisHeader->fisType)); + } + else if ( (ataStatus & ERR_ATA_STATUS_MASK) || + (ataStatus & DF_ATA_STATUS_MASK) + ) + { + TI_DBG1(("satNonChainedWriteNVerifyCB: FAILED, FAILED, error status\n")); + } + + + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + satProcessAbort(tiRoot, + tiOrgIORequest, + satOrgIOContext + ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + /* for debugging */ + switch (hostToDevFis->h.command) + { + case SAT_WRITE_DMA_FUA_EXT: + TI_DBG1(("satNonChainedWriteNVerifyCB: SAT_WRITE_DMA_FUA_EXT\n")); + break; + case SAT_WRITE_DMA_EXT: + TI_DBG1(("satNonChainedWriteNVerifyCB: SAT_WRITE_DMA_EXT\n")); + break; + case SAT_WRITE_SECTORS_EXT: + TI_DBG1(("satNonChainedWriteNVerifyCB: SAT_WRITE_SECTORS_EXT\n")); + break; + case SAT_WRITE_FPDMA_QUEUED: + TI_DBG1(("satNonChainedWriteNVerifyCB: SAT_WRITE_FPDMA_QUEUED\n")); + break; + case SAT_READ_VERIFY_SECTORS: + TI_DBG1(("satNonChainedWriteNVerifyCB: SAT_READ_VERIFY_SECTORS\n")); + break; + case SAT_READ_VERIFY_SECTORS_EXT: + TI_DBG1(("satNonChainedWriteNVerifyCB: SAT_READ_VERIFY_SECTORS_EXT\n")); + break; + default: + TI_DBG1(("satNonChainedWriteNVerifyCB: error default case command 0x%x\n", hostToDevFis->h.command)); + break; + } + + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } /* end error checking */ + } + + /* process success from this point on */ + + switch (hostToDevFis->h.command) + { + case SAT_WRITE_DMA_FUA_EXT: + TI_DBG5(("satNonChainedWriteNVerifyCB: SAT_WRITE_DMA_FUA_EXT success\n")); + break; + case SAT_WRITE_DMA_EXT: + TI_DBG5(("satNonChainedWriteNVerifyCB: SAT_WRITE_DMA_EXT success\n")); + break; + case SAT_WRITE_SECTORS_EXT: + TI_DBG5(("satNonChainedWriteNVerifyCB: SAT_WRITE_SECTORS_EXT succes\n")); + + break; + case SAT_WRITE_FPDMA_QUEUED: + TI_DBG5(("satNonChainedWriteNVerifyCB: SAT_WRITE_FPDMA_QUEUED succes\n")); + break; + case SAT_READ_VERIFY_SECTORS: + TI_DBG5(("satNonChainedWriteNVerifyCB: SAT_READ_VERIFY_SECTORS succes\n")); + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + /* free */ + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + /* return stat_good */ + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + return; + break; + case SAT_READ_VERIFY_SECTORS_EXT: + TI_DBG5(("satNonChainedWriteNVerifyCB: SAT_READ_VERIFY_SECTORS_EXT succes\n")); + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + /* free */ + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + /* return stat_good */ + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + return; + break; + default: + TI_DBG1(("satNonChainedWriteNVerifyCB: error default case command 0x%x success\n", hostToDevFis->h.command)); + + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + break; + } + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + /* free */ + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + satNewIntIo = satAllocIntIoResource( tiRoot, + tiOrgIORequest, + satDevData, + 0, + satNewIntIo); + if (satNewIntIo == agNULL) + { + /* memory allocation failure */ + satFreeIntIoResource( tiRoot, + satDevData, + satNewIntIo); + + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + TI_DBG1(("satNonChainedWriteNVerifyCB: momory allocation fails\n")); + return; + } /* end memory allocation */ + + satNewIOContext = satPrepareNewIO( + satNewIntIo, + tiOrgIORequest, + satDevData, + scsiCmnd, + satOrgIOContext + ); + + /* sends ATA verify command(READ_VERIFY_SECTORS or READ_VERIFY_SECTORS_EXT) */ + status = satNonChainedWriteNVerify_Verify(tiRoot, + &satNewIntIo->satIntTiIORequest, + satNewIOContext->ptiDeviceHandle, + tiScsiRequest, /* orginal from OS layer */ + satNewIOContext + ); + + + if (status != tiSuccess) + { + /* sending ATA command fails */ + satFreeIntIoResource( tiRoot, + satDevData, + satNewIntIo); + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + TI_DBG1(("satNonChainedWriteNVerifyCB: calling satWriteAndVerify10_1 fails\n")); + return; + } /* end send fails */ + + return; +} + + +void satChainedWriteNVerifyCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + /* + send write in loop + then, send verify in loop + */ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdIORequestBody; + tdIORequestBody_t *tdOrgIORequestBody; + satIOContext_t *satIOContext; + satIOContext_t *satOrgIOContext; + satIOContext_t *satNewIOContext; + satInternalIo_t *satIntIo; + satInternalIo_t *satNewIntIo = agNULL; + satDeviceData_t *satDevData; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + tiIORequest_t *tiOrgIORequest; + + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + bit32 dataLength; + bit32 status = tiError; + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + + TI_DBG6(("satChainedWriteNVerifyCB: agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", + agIORequest, agIOStatus, agIOInfoLen)); + + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satIOContext = (satIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + satDevData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + + if (satIntIo == agNULL) + { + TI_DBG5(("satChainedWriteNVerifyCB: External satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + tiOrgIORequest = tdIORequestBody->tiIORequest; + pSense = satIOContext->pSense; + scsiCmnd = satIOContext->pScsiCmnd; + } + else + { + TI_DBG5(("satChainedWriteNVerifyCB: Internal satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + TI_DBG5(("satChainedWriteNVerifyCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + TI_DBG5(("satChainedWriteNVerifyCB: satOrgIOContext is NOT NULL\n")); + } + tdOrgIORequestBody = (tdIORequestBody_t *)satOrgIOContext->tiRequestBody; + tiOrgIORequest = (tiIORequest_t *)tdOrgIORequestBody->tiIORequest; + + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satChainedWriteNVerifyCB: wrong. agFirstDword is NULL when error, status %d\n", agIOStatus)); + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + /* + checking IO status, FIS type and error status + */ + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* agsaFisPioSetup_t or agsaFisRegDeviceToHost_t or agsaFisSetDevBits_t for read + agsaFisRegDeviceToHost_t or agsaFisSetDevBits_t for write + first, assumed to be Reg Device to Host FIS + This is OK to just find fis type + */ + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + /* for debugging */ + if( (statDevToHostFisHeader->fisType != PIO_SETUP_DEV_TO_HOST_FIS) && + (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) && + (statDevToHostFisHeader->fisType != SET_DEV_BITS_FIS) + ) + { + TI_DBG1(("satChainedWriteNVerifyCB: FAILED, Wrong FIS type 0x%x\n", statDevToHostFisHeader->fisType)); + } + + /* for debugging */ + if ( (ataStatus & ERR_ATA_STATUS_MASK) || + (ataStatus & DF_ATA_STATUS_MASK) + ) + { + TI_DBG1(("satChainedWriteNVerifyCB: FAILED, error status and command 0x%x\n", hostToDevFis->h.command)); + } + + /* the function below handles abort case */ + itdsatDelayedProcessAbnormalCompletion(agRoot, + agIORequest, + agIOStatus, + agFirstDword, + agIOInfoLen, + agParam, + satIOContext); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } /* end of error */ + + /* process the success case */ + switch (hostToDevFis->h.command) + { + case SAT_WRITE_DMA: /* fall through */ + case SAT_WRITE_SECTORS:/* fall through */ +// case SAT_WRITE_DMA_FUA_EXT: /* fall through */ + case SAT_WRITE_DMA_EXT: /* fall through */ + case SAT_WRITE_SECTORS_EXT: /* fall through */ + case SAT_WRITE_FPDMA_QUEUED: + + TI_DBG5(("satChainedWriteNVerifyCB: WRITE success case\n")); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + /* done with internally genereated SAT_SMART_RETURN_STATUS */ + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + /* let's loop till TL */ + + + (satOrgIOContext->LoopNum)--; + + if (satOrgIOContext->superIOFlag) + { + dataLength = ((tiSuperScsiInitiatorRequest_t *) satOrgIOContext->tiScsiXchg)->scsiCmnd.expDataLength; + } + else + { + dataLength = ((tiScsiInitiatorRequest_t *) satOrgIOContext->tiScsiXchg)->scsiCmnd.expDataLength; + } + + satNewIntIo = satAllocIntIoResource( tiRoot, + tiOrgIORequest, + satDevData, + dataLength, + satNewIntIo); + if (satNewIntIo == agNULL) + { + /* memory allocation failure */ + satFreeIntIoResource( tiRoot, + satDevData, + satNewIntIo); + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOFailed, + tiDetailOtherError, + agNULL, + satOrgIOContext->interruptContext ); + + TI_DBG1(("satChainedWriteNVerifyCB: momory allocation fails\n")); + return; + } /* end of memory allocation failure */ + + /* + * Need to initialize all the fields within satIOContext + */ + + satNewIOContext = satPrepareNewIO( + satNewIntIo, + tiOrgIORequest, + satDevData, + scsiCmnd, + satOrgIOContext + ); + + if (satOrgIOContext->LoopNum == 0) + { + /* + done with write + start with verify + */ + satOrgIOContext->LoopNum = satOrgIOContext->LoopNum2; + status = satChainedWriteNVerify_Start_Verify(tiRoot, + &satNewIntIo->satIntTiIORequest, + satNewIOContext->ptiDeviceHandle, + &satNewIntIo->satIntTiScsiXchg, + satNewIOContext); + } + else + { + status = satChainedWriteNVerify_Write(tiRoot, + &satNewIntIo->satIntTiIORequest, + satNewIOContext->ptiDeviceHandle, + &satNewIntIo->satIntTiScsiXchg, + satNewIOContext); + } + + if (status != tiSuccess) + { + satFreeIntIoResource( tiRoot, + satDevData, + satNewIntIo); + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOFailed, + tiDetailOtherError, + agNULL, + satOrgIOContext->interruptContext ); + TI_DBG1(("satChainedWriteNVerifyCB: calling satChainedWriteNVerify_Write fails\n")); + return; + } + + break; + + case SAT_READ_VERIFY_SECTORS: /* fall through */ + case SAT_READ_VERIFY_SECTORS_EXT: + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + /* done with internally genereated SAT_SMART_RETURN_STATUS */ + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + /* let's loop till TL */ + + /* lba = lba + tl + loopnum--; + if (loopnum == 0) done + */ + (satOrgIOContext->LoopNum)--; + if (satOrgIOContext->LoopNum == 0) + { + /* + done with write and verify + */ + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + return; + } + + if (satOrgIOContext->superIOFlag) + { + dataLength = ((tiSuperScsiInitiatorRequest_t *) satOrgIOContext->tiScsiXchg)->scsiCmnd.expDataLength; + } + else + { + dataLength = ((tiScsiInitiatorRequest_t *) satOrgIOContext->tiScsiXchg)->scsiCmnd.expDataLength; + } + + satNewIntIo = satAllocIntIoResource( tiRoot, + tiOrgIORequest, + satDevData, + dataLength, + satNewIntIo); + if (satNewIntIo == agNULL) + { + /* memory allocation failure */ + satFreeIntIoResource( tiRoot, + satDevData, + satNewIntIo); + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOFailed, + tiDetailOtherError, + agNULL, + satOrgIOContext->interruptContext ); + + TI_DBG1(("satChainedWriteNVerifyCB: momory allocation fails\n")); + return; + } /* end of memory allocation failure */ + + /* + * Need to initialize all the fields within satIOContext + */ + + satNewIOContext = satPrepareNewIO( + satNewIntIo, + tiOrgIORequest, + satDevData, + scsiCmnd, + satOrgIOContext + ); + status = satChainedWriteNVerify_Verify(tiRoot, + &satNewIntIo->satIntTiIORequest, + satNewIOContext->ptiDeviceHandle, + &satNewIntIo->satIntTiScsiXchg, + satNewIOContext); + + if (status != tiSuccess) + { + satFreeIntIoResource( tiRoot, + satDevData, + satNewIntIo); + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOFailed, + tiDetailOtherError, + agNULL, + satOrgIOContext->interruptContext ); + TI_DBG1(("satChainedWriteNVerifyCB: calling satChainedWriteNVerify_Verify fails\n")); + return; + } + + break; + + default: + TI_DBG1(("satChainedWriteNVerifyCB: success but default case command 0x%x\n",hostToDevFis->h.command)); + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOFailed, + tiDetailOtherError, + agNULL, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + break; + } + + + return; +} +/***************************************************************************** +*! \brief itdsatProcessAbnormalCompletion +* +* This routine is called to complete error case for SATA request previously +* issued to the LL Layer in saSATAStart() +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void itdsatProcessAbnormalCompletion( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + satIOContext_t *satIOContext + ) +{ + + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 interruptContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + satDeviceData_t *pSatDevData; + tiDeviceHandle_t *tiDeviceHandle; + tdsaDeviceData_t *oneDeviceData = agNULL; + agsaDevHandle_t *agDevHandle = agNULL; + + TI_DBG5(("itdsatProcessAbnormalCompletion: agIORequest=%p agIOStatus=0x%x agIOInfoLen=%d\n", + agIORequest, agIOStatus, agIOInfoLen)); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + pSatDevData = satIOContext->pSatDevData; + tiDeviceHandle = satIOContext->ptiDeviceHandle; + + /* Get into the detail */ + switch(agIOStatus) + { + case OSSA_IO_SUCCESS: + TI_DBG1(("itdsatProcessAbnormalCompletion: agIOStatus = OSSA_IO_SUCCESS agIOInfoLen %d calling osSatIOCompleted\n", agIOInfoLen)); + /* + * At this point agIOInfoLen should be non-zero and there is valid FIS + * to read. Pass this info to the SAT layer in order to do the ATA status + * to SCSI status translation. + */ + osSatIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + agFirstDword, + agIOInfoLen, + agParam, + satIOContext, + interruptContext); + break; + + + case OSSA_IO_ABORTED: + TI_DBG1(("itdsatProcessAbnormalCompletion: agIOStatus = OSSA_IO_ABORTED\n")); + + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailAborted, + agNULL, + interruptContext); + + if ( pSatDevData->satTmTaskTag != agNULL ) + { + TI_DBG1(("itdsatProcessAbnormalCompletion: TM callback\n")); + if (tiDeviceHandle == agNULL) + { + TI_DBG1(("itdsatProcessAbnormalCompletion: wrong, tiDeviceHandle is NULL\n")); + } + /* TM completed */ + ostiInitiatorEvent( tiRoot, + agNULL, /* portalContext not used */ + tiDeviceHandle, + tiIntrEventTypeTaskManagement, + tiTMOK, + pSatDevData->satTmTaskTag); + /* + * Reset flag + */ + pSatDevData->satTmTaskTag = agNULL; + } + + /* + * Check if we are in recovery mode and need to update the recovery flag + */ + if ((pSatDevData->satDriveState == SAT_DEV_STATE_IN_RECOVERY ) && + (pSatDevData->satPendingIO == 0 )) + { + pSatDevData->satDriveState = SAT_DEV_STATE_NORMAL; + TI_DBG1(("itdsatProcessAbnormalCompletion: STATE NORMAL.\n")); + } + + TI_DBG1(("itdsatProcessAbnormalCompletion: satDriveState %d\n", pSatDevData->satDriveState)); + TI_DBG1(("itdsatProcessAbnormalCompletion: satPendingIO %d satNCQMaxIO %d\n", pSatDevData->satPendingIO, pSatDevData->satNCQMaxIO )); + TI_DBG1(("itdsatProcessAbnormalCompletion: satPendingNCQIO %d satPendingNONNCQIO %d\n", pSatDevData->satPendingNCQIO, pSatDevData->satPendingNONNCQIO)); + + break; + case OSSA_IO_UNDERFLOW: + TI_DBG1(("itdsatProcessAbnormalCompletion: agIOStatus = OSSA_IO_UNDERFLOW\n")); + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOUnderRun, + agIOInfoLen, + agNULL, + interruptContext); + break; + + + case OSSA_IO_FAILED: + TI_DBG1(("itdsatProcessAbnormalCompletion: agIOStatus = OSSA_IO_FAILED\n")); + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + interruptContext); + break; + + case OSSA_IO_ABORT_RESET: + TI_DBG1(("itdsatProcessAbnormalCompletion: agIOStatus = OSSA_IO_ABORT_RESET\n")); + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailAbortReset, + agNULL, + interruptContext); + /* + * Check if we are in recovery mode and need to update the recovery flag + */ + if ((pSatDevData->satDriveState == SAT_DEV_STATE_IN_RECOVERY ) && + (pSatDevData->satPendingIO == 0 )) + { + pSatDevData->satDriveState = SAT_DEV_STATE_NORMAL; + TI_DBG1(("itdsatProcessAbnormalCompletion: STATE NORMAL.\n")); + } + + TI_DBG1(("itdsatProcessAbnormalCompletion: satDriveState %d\n", pSatDevData->satDriveState)); + TI_DBG1(("itdsatProcessAbnormalCompletion: satPendingIO %d satNCQMaxIO %d\n", pSatDevData->satPendingIO, pSatDevData->satNCQMaxIO )); + TI_DBG1(("itdsatProcessAbnormalCompletion: satPendingNCQIO %d satPendingNONNCQIO %d\n", pSatDevData->satPendingNCQIO, pSatDevData->satPendingNONNCQIO)); + + break; + + + case OSSA_IO_NO_DEVICE: + TI_DBG1(("itdsatProcessAbnormalCompletion: agIOStatus = OSSA_IO_NO_DEVICE\n")); + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailNoLogin, + agNULL, + interruptContext); + break; + + case OSSA_IO_PROG_ERROR: + TI_DBG1(("itdsatProcessAbnormalCompletion: agIOStatus = OSSA_IO_PROG_ERROR\n")); + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + interruptContext); + break; + case OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: /* fall through */ + case OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION: /* fall through */ + case OSSA_IO_OPEN_CNX_ERROR_BREAK: /* fall through */ + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: /* fall through */ + case OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION: /* fall through */ + case OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: /* fall through */ + case OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION: /* fall through */ + case OSSA_IO_OPEN_CNX_ERROR_UNKNOWN_ERROR: /* fall through */ + TI_DBG1(("itdsatProcessAbnormalCompletion: agIOStatus = OSSA_IO_OPEN_CNX_ERROR_* 0x%x\n", agIOStatus)); + if (tiDeviceHandle == agNULL) + { + TI_DBG1(("itdsatProcessAbnormalCompletion: wrong, tiDeviceHandle is NULL\n")); + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + interruptContext); + return; + } + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + if (oneDeviceData == agNULL) + { + TI_DBG1(("itdsatProcessAbnormalCompletion: wrong, oneDeviceData is NULL\n")); + } + else + { + TI_DBG1(("itdsatProcessAbnormalCompletion: did %d\n", oneDeviceData->id)); + } + + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + interruptContext); + break; + + case OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: + TI_DBG1(("itdsatProcessAbnormalCompletion: agIOStatus = OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n")); + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, //tiDetailNoDeviceError, //tiDetailAborted, + agNULL, + interruptContext); + break; + + case OSSA_IO_XFER_ERROR_BREAK: /* fall throuth */ + case OSSA_IO_XFER_ERROR_PHY_NOT_READY: /* fall throuth */ + case OSSA_IO_XFER_ERROR_PEER_ABORTED: /* fall throuth */ + case OSSA_IO_XFER_ERROR_DMA: /* fall throuth */ + case OSSA_IO_XFER_ERROR_SATA_LINK_TIMEOUT: /* fall throuth */ + case OSSA_IO_XFER_ERROR_ABORTED_DUE_TO_SRST: /* fall throuth */ + case OSSA_IO_XFER_ERROR_REJECTED_NCQ_MODE: /* fall throuth */ + TI_DBG1(("itdsatProcessAbnormalCompletion: agIOStatus = OSSA_IO_XFER_ERROR_* 0x%x\n", agIOStatus)); + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + interruptContext); + break; + case OSSA_IO_DS_IN_ERROR: + TI_DBG1(("itdsatProcessAbnormalCompletion: agIOStatus = OSSA_IO_DS_IN_ERROR\n")); + if (tiDeviceHandle == agNULL) + { + TI_DBG1(("itdsatProcessAbnormalCompletion: wrong, tiDeviceHandle is NULL\n")); + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + interruptContext); + return; + } + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + if (oneDeviceData == agNULL) + { + TI_DBG1(("itdsatProcessAbnormalCompletion: wrong, oneDeviceData is NULL\n")); + } + else + { + TI_DBG1(("itdsatProcessAbnormalCompletion: did %d\n", oneDeviceData->id)); + } + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + interruptContext); + break; + case OSSA_IO_DS_NON_OPERATIONAL: + TI_DBG1(("itdsatProcessAbnormalCompletion: agIOStatus = OSSA_IO_DS_NON_OPERATIONAL\n")); + if (tiDeviceHandle == agNULL) + { + TI_DBG1(("itdsatProcessAbnormalCompletion: wrong, tiDeviceHandle is NULL\n")); + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + interruptContext); + return; + } + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + if (oneDeviceData == agNULL) + { + TI_DBG1(("itdsatProcessAbnormalCompletion: wrong, oneDeviceData is NULL\n")); + } + else + { + TI_DBG1(("itdsatProcessAbnormalCompletion: did %d\n", oneDeviceData->id)); + agDevHandle = oneDeviceData->agDevHandle; + if (oneDeviceData->valid == agTRUE && oneDeviceData->registered == agTRUE && + oneDeviceData->tdPortContext != agNULL ) + { + saSetDeviceState(agRoot, agNULL, tdsaRotateQnumber(tiRoot, oneDeviceData), agDevHandle, SA_DS_OPERATIONAL); + } + } + + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + interruptContext); + break; + case OSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS: /* fall through */ + case OSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH: + TI_DBG1(("itdsatProcessAbnormalCompletion: agIOStatus = ENCRYPTION ERROR 0x%x\n", agIOStatus)); + itdsatEncryptionHandler(agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + 0); + break; + case OSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH: /* fall through */ + case OSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH: /* fall through */ + case OSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH: + TI_DBG1(("itdsatProcessAbnormalCompletion: agIOStatus = DIF ERROR 0x%x\n", agIOStatus)); + itdsatDifHandler(agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + 0); + break; + default: + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + TI_DBG1(("itdsatProcessAbnormalCompletion: agIOStatus = unknown 0x%x\n", agIOStatus)); + if (oneDeviceData != agNULL) + { + TI_DBG1(("itdsatProcessAbnormalCompletion: did %d\n", oneDeviceData->id)); + } + else + { + TI_DBG1(("itdsatProcessAbnormalCompletion: oneDeviceData is NULL\n")); + } + + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + interruptContext); + break; + + } /* switch */ +} + + +/***************************************************************************** +*! \brief itdsatDelayedProcessAbnormalCompletion +* +* This routine is called to complete error case for SATA request previously +* issued to the LL Layer in saSATAStart(). +* This is used when command is chained. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void itdsatDelayedProcessAbnormalCompletion( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + satIOContext_t *satIOContext + ) +{ + + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 interruptContext = osData->IntContext; + tdIORequestBody_t *tdIORequestBody; + satDeviceData_t *pSatDevData; + tiDeviceHandle_t *tiDeviceHandle; + tdsaDeviceData_t *oneDeviceData = agNULL; + agsaDevHandle_t *agDevHandle = agNULL; + + TI_DBG5(("itdsatDelayedProcessAbnormalCompletion: agIORequest=%p agIOStatus=0x%x agIOInfoLen=%d\n", + agIORequest, agIOStatus, agIOInfoLen)); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + pSatDevData = satIOContext->pSatDevData; + tiDeviceHandle = satIOContext->ptiDeviceHandle; + + /* Get into the detail */ + switch(agIOStatus) + { + case OSSA_IO_SUCCESS: + TI_DBG1(("itdsatDelayedProcessAbnormalCompletion: agIOStatus = OSSA_IO_SUCCESS calling osSatIOCompleted\n")); + /* do nothing */ + break; + + + case OSSA_IO_ABORTED: + TI_DBG1(("itdsatDelayedProcessAbnormalCompletion: agIOStatus = OSSA_IO_ABORTED\n")); + + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailAborted, + agNULL, + interruptContext); + + if ( pSatDevData->satTmTaskTag != agNULL ) + { + TI_DBG1(("itdsatDelayedProcessAbnormalCompletion: TM callback\n")); + if (tiDeviceHandle == agNULL) + { + TI_DBG1(("itdsatDelayedProcessAbnormalCompletion: wrong, tiDeviceHandle is NULL\n")); + } + /* TM completed */ + ostiInitiatorEvent( tiRoot, + agNULL, /* portalContext not used */ + tiDeviceHandle, + tiIntrEventTypeTaskManagement, + tiTMOK, + pSatDevData->satTmTaskTag); + /* + * Reset flag + */ + pSatDevData->satTmTaskTag = agNULL; + } + + /* + * Check if we are in recovery mode and need to update the recovery flag + */ + if ((pSatDevData->satDriveState == SAT_DEV_STATE_IN_RECOVERY ) && + (pSatDevData->satPendingIO == 0 )) + { + pSatDevData->satDriveState = SAT_DEV_STATE_NORMAL; + TI_DBG1(("itdsatDelayedProcessAbnormalCompletion: STATE NORMAL.\n")); + } + + TI_DBG1(("itdsatDelayedProcessAbnormalCompletion: satDriveState %d\n", pSatDevData->satDriveState)); + TI_DBG1(("itdsatDelayedProcessAbnormalCompletion: satPendingIO %d satNCQMaxIO %d\n", pSatDevData->satPendingIO, pSatDevData->satNCQMaxIO )); + TI_DBG1(("itdsatDelayedProcessAbnormalCompletion: satPendingNCQIO %d satPendingNONNCQIO %d\n", pSatDevData->satPendingNCQIO, pSatDevData->satPendingNONNCQIO)); + + break; + case OSSA_IO_UNDERFLOW: + TI_DBG1(("itdsatDelayedProcessAbnormalCompletion: agIOStatus = OSSA_IO_UNDERFLOW\n")); + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOUnderRun, + agIOInfoLen, + agNULL, + interruptContext); + break; + + + case OSSA_IO_FAILED: + TI_DBG1(("itdsatDelayedProcessAbnormalCompletion: agIOStatus = OSSA_IO_FAILED\n")); + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + interruptContext); + break; + + case OSSA_IO_ABORT_RESET: + TI_DBG1(("itdsatDelayedProcessAbnormalCompletion: agIOStatus = OSSA_IO_ABORT_RESET\n")); + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailAbortReset, + agNULL, + interruptContext); + /* + * Check if we are in recovery mode and need to update the recovery flag + */ + if ((pSatDevData->satDriveState == SAT_DEV_STATE_IN_RECOVERY ) && + (pSatDevData->satPendingIO == 0 )) + { + pSatDevData->satDriveState = SAT_DEV_STATE_NORMAL; + TI_DBG1(("itdsatDelayedProcessAbnormalCompletion: STATE NORMAL.\n")); + } + + TI_DBG1(("itdsatDelayedProcessAbnormalCompletion: satDriveState %d\n", pSatDevData->satDriveState)); + TI_DBG1(("itdsatDelayedProcessAbnormalCompletion: satPendingIO %d satNCQMaxIO %d\n", pSatDevData->satPendingIO, pSatDevData->satNCQMaxIO )); + TI_DBG1(("itdsatDelayedProcessAbnormalCompletion: satPendingNCQIO %d satPendingNONNCQIO %d\n", pSatDevData->satPendingNCQIO, pSatDevData->satPendingNONNCQIO)); + + break; + + + case OSSA_IO_NO_DEVICE: + TI_DBG1(("itdsatDelayedProcessAbnormalCompletion: agIOStatus = OSSA_IO_NO_DEVICE\n")); + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailNoLogin, + agNULL, + interruptContext); + break; + + case OSSA_IO_PROG_ERROR: + TI_DBG1(("itdsatDelayedProcessAbnormalCompletion: agIOStatus = OSSA_IO_PROG_ERROR\n")); + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + interruptContext); + break; + case OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: /* fall through */ + case OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION: /* fall through */ + case OSSA_IO_OPEN_CNX_ERROR_BREAK: /* fall through */ + case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: /* fall through */ + case OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION: /* fall through */ + case OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: /* fall through */ + case OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION: /* fall through */ + case OSSA_IO_OPEN_CNX_ERROR_UNKNOWN_ERROR: /* fall through */ + TI_DBG1(("itdsatDelayedProcessAbnormalCompletion: agIOStatus = OSSA_IO_OPEN_CNX_ERROR_* 0x%x\n", agIOStatus)); + if (tiDeviceHandle == agNULL) + { + TI_DBG1(("itdsatDelayedProcessAbnormalCompletion: wrong, tiDeviceHandle is NULL\n")); + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + interruptContext); + return; + } + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + if (oneDeviceData == agNULL) + { + TI_DBG1(("itdsatDelayedProcessAbnormalCompletion: wrong, oneDeviceData is NULL\n")); + } + else + { + TI_DBG1(("itdsatDelayedProcessAbnormalCompletion: did %d\n", oneDeviceData->id)); + } + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + interruptContext); + break; + + case OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: + TI_DBG1(("itdsatDelayedProcessAbnormalCompletion: agIOStatus = OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n")); + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, //tiDetailNoDeviceError, //tiDetailAborted, + agNULL, + interruptContext); + break; + + case OSSA_IO_XFER_ERROR_BREAK: /* fall throuth */ + case OSSA_IO_XFER_ERROR_PHY_NOT_READY: /* fall throuth */ + case OSSA_IO_XFER_ERROR_PEER_ABORTED: /* fall throuth */ + case OSSA_IO_XFER_ERROR_DMA: /* fall throuth */ + case OSSA_IO_XFER_ERROR_SATA_LINK_TIMEOUT: /* fall throuth */ + case OSSA_IO_XFER_ERROR_ABORTED_DUE_TO_SRST: /* fall throuth */ + case OSSA_IO_XFER_ERROR_REJECTED_NCQ_MODE: /* fall throuth */ + TI_DBG1(("itdsatDelayedProcessAbnormalCompletion: agIOStatus = OSSA_IO_XFER_ERROR_* 0x%x\n", agIOStatus)); + + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + interruptContext); + break; + case OSSA_IO_DS_IN_ERROR: + TI_DBG1(("itdsatDelayedProcessAbnormalCompletion: agIOStatus = OSSA_IO_DS_IN_ERROR\n")); + if (tiDeviceHandle == agNULL) + { + TI_DBG1(("itdsatDelayedProcessAbnormalCompletion: wrong, tiDeviceHandle is NULL\n")); + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + interruptContext); + return; + } + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + if (oneDeviceData == agNULL) + { + TI_DBG1(("itdsatDelayedProcessAbnormalCompletion: wrong, oneDeviceData is NULL\n")); + } + else + { + TI_DBG1(("itdsatDelayedProcessAbnormalCompletion: did %d\n", oneDeviceData->id)); + } + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + interruptContext); + break; + case OSSA_IO_DS_NON_OPERATIONAL: + TI_DBG1(("itdsatDelayedProcessAbnormalCompletion: agIOStatus = OSSA_IO_DS_NON_OPERATIONAL\n")); + if (tiDeviceHandle == agNULL) + { + TI_DBG1(("itdsatDelayedProcessAbnormalCompletion: wrong, tiDeviceHandle is NULL\n")); + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + interruptContext); + return; + } + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + if (oneDeviceData == agNULL) + { + TI_DBG1(("itdsatDelayedProcessAbnormalCompletion: wrong, oneDeviceData is NULL\n")); + } + else + { + TI_DBG1(("itdsatDelayedProcessAbnormalCompletion: did %d\n", oneDeviceData->id)); + agDevHandle = oneDeviceData->agDevHandle; + if (oneDeviceData->valid == agTRUE && oneDeviceData->registered == agTRUE && + oneDeviceData->tdPortContext != agNULL ) + { + saSetDeviceState(agRoot, agNULL, tdsaRotateQnumber(tiRoot, oneDeviceData), agDevHandle, SA_DS_OPERATIONAL); + } + } + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + interruptContext); + break; + case OSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS: /* fall through */ + case OSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH: + TI_DBG1(("itdsatDelayedProcessAbnormalCompletion: agIOStatus = ENCRYPTION ERROR 0x%x\n", agIOStatus)); + itdsatEncryptionHandler(agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + 0); + break; + case OSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH: /* fall through */ + case OSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH: /* fall through */ + case OSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH: + TI_DBG1(("itdsatDelayedProcessAbnormalCompletion: agIOStatus = DIF ERROR 0x%x\n", agIOStatus)); + itdsatDifHandler(agRoot, + agIORequest, + agIOStatus, + agIOInfoLen, + agParam, + 0); + break; + default: + TI_DBG1(("itdsatDelayedProcessAbnormalCompletion: agIOStatus = unknown\n")); + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + interruptContext); + break; + + } /* switch */ +} + +/***************************************************************************** +*! \brief itdsatEncryptionHandler +* +* Purpose: This function processes I/Os completed and returned by SATA lower +* layer with any encryption specific agIOStatus. +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdsatEncryptionHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + bit32 errorDetail = tiDetailOtherError; + tdIORequestBody_t *tdIORequestBody; + TI_DBG1(("itdsatEncryptionHandler: start\n")); + TI_DBG1(("itdsatEncryptionHandler: agIOStatus 0x%x\n", agIOStatus)); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + + switch (agIOStatus) + { + case OSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS: + TI_DBG1(("itdsatEncryptionHandler: OSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS\n")); + errorDetail = tiDetailDekKeyCacheMiss; + break; + case OSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID: + TI_DBG1(("itdsatEncryptionHandler: OSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID\n")); + errorDetail = tiDetailCipherModeInvalid; + break; + case OSSA_IO_XFR_ERROR_DEK_IV_MISMATCH: + TI_DBG1(("itdsatEncryptionHandler: OSSA_IO_XFR_ERROR_DEK_IV_MISMATCH\n")); + errorDetail = tiDetailDekIVMismatch; + break; + case OSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR: + TI_DBG1(("itdsatEncryptionHandler: OSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR\n")); + errorDetail = tiDetailDekRamInterfaceError; + break; + default: + TI_DBG1(("itdsatEncryptionHandler: other error!!! 0x%x\n", agIOStatus)); + errorDetail = tiDetailOtherError; + break; + } + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIOEncryptError, + errorDetail, + agNULL, + intContext + ); + return; +} + +/***************************************************************************** +*! \brief itdsatDifHandler +* +* Purpose: This function processes I/Os completed and returned by SATA lower +* layer with any DIF specific agIOStatus. +* +* \param agRoot: pointer to port instance +* \param agIORequest: pointer to I/O request +* \param agIOStatus: I/O status given by LL layer +* \param agIOInfoLen: lenth of complete SAS RESP frame +* \param agParam A Handle used to refer to the response frame or handle +* of abort request +* \return: None +* +* +*****************************************************************************/ +osGLOBAL void +itdsatDifHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + bit32 intContext = osData->IntContext; + bit32 errorDetail = tiDetailOtherError; + tdIORequestBody_t *tdIORequestBody; +#ifdef TD_DEBUG_ENABLE + agsaDifDetails_t *DifDetail; +#endif + + TI_DBG2(("itdsatDifHandler: start\n")); + TI_DBG2(("itdsatDifHandler: agIOStatus 0x%x\n", agIOStatus)); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; +#ifdef TD_DEBUG_ENABLE + DifDetail = (agsaDifDetails_t *)agParam; +#endif + switch (agIOStatus) + { + case OSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH: + TI_DBG1(("itdsatDifHandler: OSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH\n")); + errorDetail = tiDetailDifAppTagMismatch; + break; + case OSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH: + TI_DBG1(("itdsatDifHandler: OSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH\n")); + errorDetail = tiDetailDifRefTagMismatch; + break; + case OSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH: + TI_DBG1(("itdsatDifHandler: OSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH\n")); + errorDetail = tiDetailDifCrcMismatch; + break; + default: + TI_DBG1(("itdsatDifHandler: other error!!! 0x%x\n", agIOStatus)); + errorDetail = tiDetailOtherError; + break; + } + + TI_DBG1(("smsatDifHandler: DIF detail UpperLBA 0x%08x LowerLBA 0x%08x\n", DifDetail->UpperLBA, DifDetail->LowerLBA)); + + ostiInitiatorIOCompleted ( + tiRoot, + tdIORequestBody->tiIORequest, + tiIODifError, + errorDetail, + agNULL, + intContext + ); + return; +} + +/*****************************************************************************/ +/*! \brief satProcessAbort + * + * This function processes abort. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return + * None + */ +/*****************************************************************************/ +void satProcessAbort( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + satIOContext_t *satIOContext + ) +{ + satDeviceData_t *pSatDevData; + //tiDeviceHandle_t *tiDeviceHandle; + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + + TI_DBG5(("satProcessAbort: start\n")); + + pSatDevData = satIOContext->pSatDevData; + //tiDeviceHandle = satIOContext->ptiDeviceHandle; + hostToDevFis = satIOContext->pFis; + if ( (hostToDevFis->h.command == SAT_SMART_EXEUTE_OFF_LINE_IMMEDIATE) && + (hostToDevFis->d.lbaLow != 0x01 && hostToDevFis->d.lbaLow != 0x02) + ) + { + /* no completion for send diagnotic in background. It is done in satSendDiagnostic() */ + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOFailed, + tiDetailAborted, + agNULL, + satIOContext->interruptContext); + } + + if ( pSatDevData->satTmTaskTag != agNULL ) + { + TI_DBG1(("satProcessAbort: TM callback\n")); + /* + * Reset flag + */ + pSatDevData->satTmTaskTag = agNULL; + } + + /* + * Check if we are in recovery mode and need to update the recovery flag + */ + if ((pSatDevData->satDriveState == SAT_DEV_STATE_IN_RECOVERY ) && + (pSatDevData->satPendingIO == 0 )) + { + pSatDevData->satDriveState = SAT_DEV_STATE_NORMAL; + TI_DBG1(("satProcessAbort: STATE NORMAL.\n")); + } + TI_DBG1(("satProcessAbort: satDriveState %d\n", pSatDevData->satDriveState)); + TI_DBG1(("satProcessAbort: satPendingIO %d satNCQMaxIO %d\n", pSatDevData->satPendingIO, pSatDevData->satNCQMaxIO )); + TI_DBG1(("satProcessAbort: satPendingNCQIO %d satPendingNONNCQIO %d\n", pSatDevData->satPendingNCQIO, pSatDevData->satPendingNONNCQIO)); + + + + return; +} + +/***************************************************************************** +*! \brief satNonDataIOCB +* +* This routine is a callback function called from ossaSATACompleted(). +* This CB routine deals with non-data I/O SATA request. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void satNonDataIOCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdIORequestBody; + bit32 interruptContext = osData->IntContext; + satIOContext_t *satIOContext; + + TI_DBG5(("satNonDataIOCB: agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", + agIORequest, agIOStatus, agIOInfoLen)); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satIOContext = (satIOContext_t *) ioContext; + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + /* Process completion */ + if( (agIOStatus == OSSA_IO_SUCCESS) && (agIOInfoLen==0)) + { + /* + * !!! We expect that agIOInfoLen should be non-zero !!!!. + * Now call the OS-App Specific layer about this unexpected completion. + */ + TI_DBG1(("satNonDataIOCB: *** ERROR*** agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", + agIORequest, agIOStatus, agIOInfoLen)); + + ostiInitiatorIOCompleted( tiRoot, + tdIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + interruptContext); + } + else + { + /* More checking needed, for non-data IO this should be the normal case */ + itdsatProcessAbnormalCompletion( agRoot, + agIORequest, + agIOStatus, + agFirstDword, + agIOInfoLen, + agParam, + satIOContext); + } + +} + +/***************************************************************************** +*! \brief tdssSATADeviceTypeDecode +* +* This routine decodes ATA signature +* +* \param pSignature: ATA signature +* +* +* \return: +* TRUE if ATA signature +* FALSE otherwise +* +*****************************************************************************/ +/* + ATA p65 + PM p65 + SATAII p79, p80 + */ +GLOBAL bit32 +tdssSATADeviceTypeDecode( + bit8 *pSignature + ) +{ + bit32 deviceType = UNKNOWN_DEVICE; + + if ( (pSignature)[0] == 0x01 && (pSignature)[1] == 0x01 + && (pSignature)[2] == 0x00 && (pSignature)[3] == 0x00 + && (pSignature)[4] == 0xA0 ) /* this is the signature of a Hitachi SATA HDD*/ + { + deviceType = SATA_ATA_DEVICE; + } + else if ( (pSignature)[0] == 0x01 && (pSignature)[1] == 0x01 + && (pSignature)[2] == 0x00 && (pSignature)[3] == 0x00 + && (pSignature)[4] == 0x00 ) + { + deviceType = SATA_ATA_DEVICE; + } + else if ( (pSignature)[0] == 0x01 && (pSignature)[1] == 0x01 + && (pSignature)[2] == 0x14 && (pSignature)[3] == 0xEB + && ( (pSignature)[4] == 0x00 || (pSignature)[4] == 0x10) ) + { + deviceType = SATA_ATAPI_DEVICE; + } + else if ( (pSignature)[0] == 0x01 && (pSignature)[1] == 0x01 + && (pSignature)[2] == 0x69 && (pSignature)[3] == 0x96 + && (pSignature)[4] == 0x00 ) + { + deviceType = SATA_PM_DEVICE; + } + else if ( (pSignature)[0] == 0x01 && (pSignature)[1] == 0x01 + && (pSignature)[2] == 0x3C && (pSignature)[3] == 0xC3 + && (pSignature)[4] == 0x00 ) + { + deviceType = SATA_SEMB_DEVICE; + } + else if ( (pSignature)[0] == 0xFF && (pSignature)[1] == 0xFF + && (pSignature)[2] == 0xFF && (pSignature)[3] == 0xFF + && (pSignature)[4] == 0xFF ) + { + deviceType = SATA_SEMB_WO_SEP_DEVICE; + } + + return deviceType; +} + +/***************************************************************************** +*! \brief ossaDiscoverSataCB +* +* Purpose: This function is called by lower layer to inform TD layer of +* STP/SATA discovery results +* +* +* \param agRoot Pointer to chip/driver Instance. +* \param agPortContext Pointer to the port context of TD and Lower layer +* \param event event type +* \param pParm1 Pointer to data associated with event +* \param pParm2 Pointer to data associated with event +* +* \return: none +* +* \note - For details, refer to SAS/SATA Low-Level API Specification +* +*****************************************************************************/ + +osGLOBAL void ossaDiscoverSataCB( agsaRoot_t *agRoot, + agsaPortContext_t *agPortContext, + bit32 event, + void *pParm1, + void *pParm2 + ) +{ + tdsaRootOsData_t *osData; + tiRoot_t *tiRoot; + tdsaPortContext_t *onePortContext; + tdsaDeviceData_t *oneDeviceData; + agsaDevHandle_t *agDevHandle; + agsaSATADeviceInfo_t *agSATADeviceInfo; + tiPortalContext_t *tiPortalContext; + + bit32 devicetype = UNKNOWN_DEVICE; + + osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot = (tiRoot_t *)osData->tiRoot; + + TI_DBG5(("ossaDiscoverSataCB: start\n")); + + if (agPortContext == agNULL) + { + TI_DBG1(("ossaDiscoverSataCB: NULL agsaPortContext; wrong\n")); + return; + } + + onePortContext = (tdsaPortContext_t *)agPortContext->osData; + tiPortalContext = (tiPortalContext_t *)onePortContext->tiPortalContext; + + switch ( event ) + { + case OSSA_DISCOVER_STARTED: + { + TI_DBG5(("ossaDiscoverSataCB: STARTED\n")); + /* Do nothing */ + break; + } + + case OSSA_DISCOVER_FOUND_DEVICE: + { + TI_DBG5(("ossaDiscoverSataCB: ***** FOUND DEVICE\n")); + agDevHandle = (agsaDevHandle_t *) pParm1; + agSATADeviceInfo = (agsaSATADeviceInfo_t *) pParm2; + + /* parse the device type */ + devicetype = tdssSATADeviceTypeDecode(agSATADeviceInfo->signature); + + + /* for now, TD handles only ATA Device or ATAPI Device */ + if (devicetype == SATA_ATA_DEVICE || devicetype == SATA_ATAPI_DEVICE) + { + TI_DBG5(("ossaDiscoverSataCB: ***** adding ....\n")); + /* Add SATA device */ + tdssAddSATAToSharedcontext( onePortContext, + agRoot, + agDevHandle, + agSATADeviceInfo, + agTRUE, + agSATADeviceInfo->stpPhyIdentifier + ); +#ifdef INITIATOR_DRIVER + ostiInitiatorEvent( + tiRoot, + tiPortalContext, + agNULL, + tiIntrEventTypeDeviceChange, + tiDeviceArrival, + agNULL + ); +#endif + } /* end of ATA_ATA_DEVICE or ATA_ATAPI_DEVICE */ + else + { + TI_DBG5(("ossaDiscoverSataCB: ***** not adding ..... devicetype 0x%x\n", devicetype)); + } + break; + } + + case OSSA_DISCOVER_REMOVED_DEVICE: + { + TI_DBG1(("ossaDiscoverSataCB: REMOVED_DEVICE\n")); + agDevHandle = (agsaDevHandle_t *) pParm1; + agSATADeviceInfo = (agsaSATADeviceInfo_t *) pParm2; + + oneDeviceData = (tdsaDeviceData_t *) agDevHandle->osData; + + TI_DBG1(("ossaDiscoverSataCB: signature: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", + agSATADeviceInfo->signature[0], agSATADeviceInfo->signature[1], + agSATADeviceInfo->signature[2], agSATADeviceInfo->signature[3], + agSATADeviceInfo->signature[4], agSATADeviceInfo->signature[5], + agSATADeviceInfo->signature[6], agSATADeviceInfo->signature[7] )); + + if (oneDeviceData == agNULL) + { + TI_DBG1(("ossaDiscoverSataCB: Wrong. DevHandle->osData is NULL but is being removed\n")); + } + tdssRemoveSATAFromSharedcontext( onePortContext, + oneDeviceData, + agRoot + ); + agDevHandle->osData = agNULL; +#ifdef INITIATOR_DRIVER + ostiInitiatorEvent( + tiRoot, + tiPortalContext, + agNULL, + tiIntrEventTypeDeviceChange, + tiDeviceRemoval, + agNULL + ); +#endif + break; + } + + case OSSA_DISCOVER_COMPLETE: + { + TI_DBG1(("ossaDiscoverSataCB: COMPLETE\n")); + onePortContext->DiscoveryState = ITD_DSTATE_COMPLETED; + TI_DBG6(("ossaDiscoverSataCB: COMPLETE pid %d\n", onePortContext->id)); + + /* Let OS-Apps specific layer know discovery has been successfully complete */ + ostiInitiatorEvent( tiRoot, + tiPortalContext, + agNULL, + tiIntrEventTypeDiscovery, + tiDiscOK, + agNULL ); + break; + } + + case OSSA_DISCOVER_ABORT: + { + TI_DBG1(("ossaDiscoverSataCB: OSSA_DISCOVER_ABORT\n")); + /* Let OS-Apps specific layer know discovery has failed */ + ostiInitiatorEvent( tiRoot, + tiPortalContext, + agNULL, + tiIntrEventTypeDiscovery, + tiDiscFailed, + agNULL ); + + break; + } + + default: + { + TI_DBG1(("ossaDiscoverSataCB: error default event 0x%x\n", event)); + /* Let OS-Apps specific layer know discovery has failed */ + ostiInitiatorEvent( tiRoot, + tiPortalContext, + agNULL, + tiIntrEventTypeDiscovery, + tiDiscFailed, + agNULL ); + break; + } + + } /* end of switch */ + + return; +} + +/***************************************************************************** +*! \brief tdssAddSataToSharedcontext +* +* Purpose: This function adds a discovered SATA device to a device list of +* a port context +* +* \param tsddPortContext_Instance Pointer to the target port context +* \param agRoot Pointer to the root data structure of +* TD and Lower layer +* \param agDevHandle Pointer to a device handle +* \param agSATADeviceInfo Pointer to SATA device info structure +* \param registered indication flag for registration to LL +* +* \Return: none +* +*****************************************************************************/ +/* split into devicedata allocation/registration and sending identify device data */ +osGLOBAL void +tdssAddSATAToSharedcontext( tdsaPortContext_t *tdsaPortContext_Instance, + agsaRoot_t *agRoot, + agsaDevHandle_t *agDevHandle, + agsaSATADeviceInfo_t *agSATADeviceInfo, + bit32 registered, + bit8 phyID + ) +{ + tdsaPortContext_t *onePortContext = agNULL; + tdList_t *PortContextList; + tdsaDeviceData_t *oneDeviceData = agNULL; + tdList_t *DeviceListList = agNULL; + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + satDeviceData_t *pSatDevData; + bit32 Indenom = tdsaAllShared->QueueConfig.numInboundQueues; + bit32 Outdenom = tdsaAllShared->QueueConfig.numOutboundQueues; + bit8 dev_s_rate = 0; + bit8 sasorsata = 1; + bit8 connectionRate; + bit8 flag = 0; + bit8 TLR = 0; + bit32 found = agFALSE; + TI_DBG5(("tdssAddSataToSharedcontext: start\n")); + + /* + * Find a right portcontext, then get devicedata from FreeLink in DeviceList. + * Then, add the devicedata to the portcontext. + */ + + /* Find a right portcontext */ + PortContextList = tdsaAllShared->MainPortContextList.flink; + while (PortContextList != &(tdsaAllShared->MainPortContextList)) + { + onePortContext = TDLIST_OBJECT_BASE(tdsaPortContext_t, MainLink, PortContextList); + if (onePortContext == tdsaPortContext_Instance) + { + TI_DBG5(("tdssAddSataToSharedcontext: found; oneportContext ID %d\n", + onePortContext->id)); + found = agTRUE; + break; + } + PortContextList = PortContextList->flink; + } + + if (found == agFALSE) + { + TI_DBG1(("tdssAddSataToSharedcontext: No corressponding tdsaPortContext\n")); + return; + } + + /* + 1. add the devicedata + 2. Send Identify Device Data + 3. In CB of Identify Device Data (satAddSATAIDDevCB), finds out the devicedata is new or old + */ + + + tdsaSingleThreadedEnter(tiRoot, TD_DEVICE_LOCK); + if (!TDLIST_NOT_EMPTY(&(tdsaAllShared->FreeDeviceList))) + { + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + TI_DBG1(("tdssAddSataToSharedcontext: ERROR empty DeviceData FreeLink\n")); + /* notifying link up */ + ostiPortEvent ( + tiRoot, + tiPortLinkUp, + tiSuccess, + (void *)tdsaAllShared->Ports[phyID].tiPortalContext + ); +#ifdef INITIATOR_DRIVER + /* triggers discovery */ + ostiPortEvent( + tiRoot, + tiPortDiscoveryReady, + tiSuccess, + (void *) tdsaAllShared->Ports[phyID].tiPortalContext + ); +#endif + return; + } + + TDLIST_DEQUEUE_FROM_HEAD(&DeviceListList, &(tdsaAllShared->FreeDeviceList)); + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, FreeLink, DeviceListList); + TDLIST_DEQUEUE_THIS(&(oneDeviceData->FreeLink)); + + TI_DBG1(("tdssAddSataToSharedcontext: oneDeviceData %p did %d\n", oneDeviceData, oneDeviceData->id)); + oneDeviceData->InQID = oneDeviceData->id % Indenom; + oneDeviceData->OutQID = oneDeviceData->id % Outdenom; + + pSatDevData = (satDeviceData_t *)&(oneDeviceData->satDevData); + pSatDevData->satDriveState = SAT_DEV_STATE_NORMAL; + pSatDevData->satPendingIO = 0; + pSatDevData->satNCQMaxIO = 0; + pSatDevData->satPendingNCQIO = 0; + pSatDevData->satPendingNONNCQIO = 0; + pSatDevData->IDDeviceValid = agFALSE; + pSatDevData->satDeviceType = tdssSATADeviceTypeDecode(onePortContext->remoteSignature); + + osti_memset(&(oneDeviceData->satDevData.satIdentifyData), 0xFF, sizeof(agsaSATAIdentifyData_t)); + + onePortContext->Count++; + oneDeviceData->DeviceType = TD_SATA_DEVICE; // either TD_SAS_DEVICE or TD_SATA_DEVICE + oneDeviceData->agRoot = agRoot; +// oneDeviceData->agDevHandle = agDevHandle; + +// agDevHandle->osData = oneDeviceData; /* TD layer */ + oneDeviceData->tdPortContext = onePortContext; + oneDeviceData->valid = agTRUE; + + oneDeviceData->directlyAttached = agTRUE; + oneDeviceData->initiator_ssp_stp_smp = 0; + oneDeviceData->target_ssp_stp_smp = 0x1; /* setting SATA device bit */ + oneDeviceData->phyID = phyID; + + /* parse sasIDframe to fill in agDeviceInfo */ + flag = (bit8)((phyID << 4) | TLR); + DEVINFO_PUT_SMPTO(&oneDeviceData->agDeviceInfo, DEFAULT_SMP_TIMEOUT); + DEVINFO_PUT_ITNEXUSTO(&oneDeviceData->agDeviceInfo, (bit16)tdsaAllShared->itNexusTimeout); + DEVINFO_PUT_FBS(&oneDeviceData->agDeviceInfo, 0); + //temp + //DEVINFO_PUT_FLAG(&oneDeviceData->agDeviceInfo, 0); + DEVINFO_PUT_FLAG(&oneDeviceData->agDeviceInfo, flag); + + sasorsata = SATA_DEVICE_TYPE; /* SATA disk */ + connectionRate = onePortContext->LinkRate; + dev_s_rate = (bit8)(dev_s_rate | (sasorsata << 4)); + dev_s_rate = (bit8)(dev_s_rate | connectionRate); + DEVINFO_PUT_DEV_S_RATE(&oneDeviceData->agDeviceInfo, dev_s_rate); + + DEVINFO_PUT_SAS_ADDRESSLO( + &oneDeviceData->agDeviceInfo, + 0 + ); + DEVINFO_PUT_SAS_ADDRESSHI( + &oneDeviceData->agDeviceInfo, + 0 + ); + + if (pSatDevData->satDeviceType == SATA_ATAPI_DEVICE ) + { + oneDeviceData->agDeviceInfo.flag |= ATAPI_DEVICE_FLAG; /* ATAPI device flag*/ + } + + oneDeviceData->agContext.osData = oneDeviceData; + oneDeviceData->agContext.sdkData = agNULL; + + if (oneDeviceData->registered == agFALSE) + { + saRegisterNewDevice( /* tdssAddSATAToSharedcontext */ + agRoot, + &oneDeviceData->agContext, + 0,/*tdsaRotateQnumber(tiRoot, oneDeviceData),*/ + &oneDeviceData->agDeviceInfo, + onePortContext->agPortContext, + 0 + ); + } + return; +} +/***************************************************************************** +*! \brief tdssRetrySATAID +* +* Purpose: This function retries identify device data to directly attached SATA +* device after device registration +* +* \param tiRoot: Pointer to TISA initiator driver/port instance. +* \param oneDeviceData Pointer to a device data +* \Return: none +* +*****************************************************************************/ +osGLOBAL void +tdssRetrySATAID( tiRoot_t *tiRoot, + tdsaDeviceData_t *oneDeviceData + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + void *osMemHandle; + tdIORequestBody_t *tdIORequestBody; + bit32 PhysUpper32; + bit32 PhysLower32; + bit32 memAllocStatus; + agsaIORequest_t *agIORequest = agNULL; /* identify device data itself */ + satIOContext_t *satIOContext = agNULL; + bit32 status; + + TI_DBG5(("tdssRetrySATAID: start\n")); + /* allocate identify device data and sends it */ + /* allocation tdIORequestBody and pass it to satTM() */ + memAllocStatus = ostiAllocMemory( + tiRoot, + &osMemHandle, + (void **)&tdIORequestBody, + &PhysUpper32, + &PhysLower32, + 8, + sizeof(tdIORequestBody_t), + agTRUE + ); + + if (memAllocStatus != tiSuccess) + { + TI_DBG1(("tdssRetrySATAID: ostiAllocMemory failed... loc 2\n")); + /* notifying link up */ + ostiPortEvent ( + tiRoot, + tiPortLinkUp, + tiSuccess, + (void *)tdsaAllShared->Ports[oneDeviceData->phyID].tiPortalContext + ); +#ifdef INITIATOR_DRIVER + /* triggers discovery */ + ostiPortEvent( + tiRoot, + tiPortDiscoveryReady, + tiSuccess, + (void *) tdsaAllShared->Ports[oneDeviceData->phyID].tiPortalContext + ); +#endif + + return; + } + + if (tdIORequestBody == agNULL) + { + TI_DBG1(("tdssRetrySATAID: ostiAllocMemory returned NULL tdIORequestBody loc 2\n")); + /* notifying link up */ + ostiPortEvent ( + tiRoot, + tiPortLinkUp, + tiSuccess, + (void *)tdsaAllShared->Ports[oneDeviceData->phyID].tiPortalContext + ); +#ifdef INITIATOR_DRIVER + /* triggers discovery */ + ostiPortEvent( + tiRoot, + tiPortDiscoveryReady, + tiSuccess, + (void *) tdsaAllShared->Ports[oneDeviceData->phyID].tiPortalContext + ); +#endif + + return; + } + + /* setup identify device data IO structure */ + tdIORequestBody->IOType.InitiatorTMIO.osMemHandle = osMemHandle; + tdIORequestBody->IOType.InitiatorTMIO.CurrentTaskTag = agNULL; + tdIORequestBody->IOType.InitiatorTMIO.TaskTag = agNULL; + + /* initialize tiDevhandle */ + tdIORequestBody->tiDevHandle = &(oneDeviceData->tiDeviceHandle); + tdIORequestBody->tiDevHandle->tdData = oneDeviceData; + + /* initialize tiIORequest */ + tdIORequestBody->tiIORequest = agNULL; + + /* initialize agIORequest */ + agIORequest = &(tdIORequestBody->agIORequest); + agIORequest->osData = (void *) tdIORequestBody; + agIORequest->sdkData = agNULL; /* SA takes care of this */ + + /* set up satIOContext */ + satIOContext = &(tdIORequestBody->transport.SATA.satIOContext); + satIOContext->pSatDevData = &(oneDeviceData->satDevData); + satIOContext->pFis = + &(tdIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev); + + + satIOContext->tiRequestBody = tdIORequestBody; + satIOContext->ptiDeviceHandle = &(oneDeviceData->tiDeviceHandle); + satIOContext->tiScsiXchg = agNULL; + satIOContext->satIntIoContext = agNULL; + satIOContext->satOrgIOContext = agNULL; + + /* followings are used only for internal IO */ + satIOContext->currentLBA = 0; + satIOContext->OrgTL = 0; + + + satIOContext->satToBeAbortedIOContext = agNULL; + + satIOContext->NotifyOS = agFALSE; + + satIOContext->pid = tdsaAllShared->Ports[oneDeviceData->phyID].portContext->id; + + status = satAddSATAStartIDDev(tiRoot, + agNULL, + &(oneDeviceData->tiDeviceHandle), + agNULL, + satIOContext + ); + + /* assumption; always new device data */ + + + if (status == tiSuccess) + { + TI_DBG6(("tdssRetrySATAID: successfully sent identify device data\n")); + TI_DBG6(("tdssRetrySATAID: one case did %d \n", oneDeviceData->id)); + } + else + { + TI_DBG1(("tdssRetrySATAID: failed in sending identify device data\n")); + /* put onedevicedata back to free list */ + tdsaSingleThreadedEnter(tiRoot, TD_DEVICE_LOCK); + TDLIST_ENQUEUE_AT_TAIL(&(oneDeviceData->FreeLink), &(tdsaAllShared->FreeDeviceList)); + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + /* notifying link up */ + ostiPortEvent ( + tiRoot, + tiPortLinkUp, + tiSuccess, + (void *)tdsaAllShared->Ports[oneDeviceData->phyID].tiPortalContext + ); +#ifdef INITIATOR_DRIVER + /* triggers discovery */ + ostiPortEvent( + tiRoot, + tiPortDiscoveryReady, + tiSuccess, + (void *) tdsaAllShared->Ports[oneDeviceData->phyID].tiPortalContext + ); +#endif + + } + + return; +} + +/***************************************************************************** +*! \brief tdssSubAddSATAToSharedcontext +* +* Purpose: This function sends identify device data to directly attached SATA +* device after device registration +* +* \param tiRoot: Pointer to TISA initiator driver/port instance. +* \param oneDeviceData Pointer to a device data +* \Return: none +* +*****************************************************************************/ +osGLOBAL void +tdssSubAddSATAToSharedcontext( tiRoot_t *tiRoot, + tdsaDeviceData_t *oneDeviceData + ) +{ + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + void *osMemHandle; + tdIORequestBody_t *tdIORequestBody; + bit32 PhysUpper32; + bit32 PhysLower32; + bit32 memAllocStatus; + agsaIORequest_t *agIORequest = agNULL; /* identify device data itself */ + satIOContext_t *satIOContext = agNULL; + bit32 status; + + TI_DBG1(("tdssSubAddSATAToSharedcontext: start\n")); + /* allocate identify device data and sends it */ + /* allocation tdIORequestBody and pass it to satTM() */ + memAllocStatus = ostiAllocMemory( + tiRoot, + &osMemHandle, + (void **)&tdIORequestBody, + &PhysUpper32, + &PhysLower32, + 8, + sizeof(tdIORequestBody_t), + agTRUE + ); + + if (memAllocStatus != tiSuccess) + { + TI_DBG1(("tdssSubAddSATAToSharedcontext: ostiAllocMemory failed... loc 2\n")); + /* notifying link up */ + ostiPortEvent ( + tiRoot, + tiPortLinkUp, + tiSuccess, + (void *)tdsaAllShared->Ports[oneDeviceData->phyID].tiPortalContext + ); +#ifdef INITIATOR_DRIVER + /* triggers discovery */ + ostiPortEvent( + tiRoot, + tiPortDiscoveryReady, + tiSuccess, + (void *) tdsaAllShared->Ports[oneDeviceData->phyID].tiPortalContext + ); +#endif + + return; + } + + if (tdIORequestBody == agNULL) + { + TI_DBG1(("tdssSubAddSATAToSharedcontext: ostiAllocMemory returned NULL tdIORequestBody loc 2\n")); + /* notifying link up */ + ostiPortEvent ( + tiRoot, + tiPortLinkUp, + tiSuccess, + (void *)tdsaAllShared->Ports[oneDeviceData->phyID].tiPortalContext + ); +#ifdef INITIATOR_DRIVER + /* triggers discovery */ + ostiPortEvent( + tiRoot, + tiPortDiscoveryReady, + tiSuccess, + (void *) tdsaAllShared->Ports[oneDeviceData->phyID].tiPortalContext + ); +#endif + + return; + } + + /* setup identify device data IO structure */ + tdIORequestBody->IOType.InitiatorTMIO.osMemHandle = osMemHandle; + tdIORequestBody->IOType.InitiatorTMIO.CurrentTaskTag = agNULL; + tdIORequestBody->IOType.InitiatorTMIO.TaskTag = agNULL; + + /* initialize tiDevhandle */ + tdIORequestBody->tiDevHandle = &(oneDeviceData->tiDeviceHandle); + tdIORequestBody->tiDevHandle->tdData = oneDeviceData; + + /* initialize tiIORequest */ + tdIORequestBody->tiIORequest = agNULL; + + /* initialize agIORequest */ + agIORequest = &(tdIORequestBody->agIORequest); + agIORequest->osData = (void *) tdIORequestBody; + agIORequest->sdkData = agNULL; /* SA takes care of this */ + + /* set up satIOContext */ + satIOContext = &(tdIORequestBody->transport.SATA.satIOContext); + satIOContext->pSatDevData = &(oneDeviceData->satDevData); + satIOContext->pFis = + &(tdIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev); + + + satIOContext->tiRequestBody = tdIORequestBody; + satIOContext->ptiDeviceHandle = &(oneDeviceData->tiDeviceHandle); + satIOContext->tiScsiXchg = agNULL; + satIOContext->satIntIoContext = agNULL; + satIOContext->satOrgIOContext = agNULL; + + /* followings are used only for internal IO */ + satIOContext->currentLBA = 0; + satIOContext->OrgTL = 0; + + + satIOContext->satToBeAbortedIOContext = agNULL; + + satIOContext->NotifyOS = agFALSE; + + satIOContext->pid = tdsaAllShared->Ports[oneDeviceData->phyID].portContext->id; + + status = satAddSATAStartIDDev(tiRoot, + agNULL, + &(oneDeviceData->tiDeviceHandle), + agNULL, + satIOContext + ); + + /* assumption; always new device data */ + + + if (status == tiSuccess) + { + TI_DBG6(("tdssSubAddSATAToSharedcontext: successfully sent identify device data\n")); + + /* Add the devicedata to the mainlink */ + tdsaSingleThreadedEnter(tiRoot, TD_DEVICE_LOCK); + TDLIST_ENQUEUE_AT_TAIL(&(oneDeviceData->MainLink), &(tdsaAllShared->MainDeviceList)); + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + TI_DBG6(("tdssSubAddSATAToSharedcontext: one case did %d \n", oneDeviceData->id)); + } + else + { + TI_DBG1(("tdssSubAddSATAToSharedcontext: failed in sending identify device data\n")); + /* put onedevicedata back to free list */ + tdsaSingleThreadedEnter(tiRoot, TD_DEVICE_LOCK); + TDLIST_ENQUEUE_AT_TAIL(&(oneDeviceData->FreeLink), &(tdsaAllShared->FreeDeviceList)); + tdsaSingleThreadedLeave(tiRoot, TD_DEVICE_LOCK); + /* notifying link up */ + ostiPortEvent ( + tiRoot, + tiPortLinkUp, + tiSuccess, + (void *)tdsaAllShared->Ports[oneDeviceData->phyID].tiPortalContext + ); +#ifdef INITIATOR_DRIVER + /* triggers discovery */ + ostiPortEvent( + tiRoot, + tiPortDiscoveryReady, + tiSuccess, + (void *) tdsaAllShared->Ports[oneDeviceData->phyID].tiPortalContext + ); +#endif + + } + + return; +} + + +/***************************************************************************** +*! \brief tdssRemoveSATAFromSharedcontext +* +* Purpose: This function removes a discovered device from a device list of +* a port context +* +* \param tsddPortContext_Ins Pointer to the target port context +* \param tdsaDeviceData_Ins Pointer to the target device +* \param agRoot Pointer to the root data structure of +* TD and Lower layer + +* +* \Return: none +* +*****************************************************************************/ +osGLOBAL void +tdssRemoveSATAFromSharedcontext( + tdsaPortContext_t *tdsaPortContext_Ins, + tdsaDeviceData_t *tdsaDeviceData_ins, + agsaRoot_t *agRoot + ) +{ + TI_DBG1(("tdssRemoveSATAFromSharedcontex: start\n")); + return; +} + + +/***************************************************************************** +*! \brief satSetDevInfo +* +* Purpose: Based on ATA identify device data, this functions sets fields of +* device data maintained in TD layer +* +* \param satDevData Pointer to a device data +* \param SATAIdData Pointer to ATA identify device data +* +* +* \Return: none +* +*****************************************************************************/ +void satSetDevInfo( + satDeviceData_t *satDevData, + agsaSATAIdentifyData_t *SATAIdData + ) +{ + TI_DBG3(("satSetDevInfo: start\n")); + + satDevData->satDriveState = SAT_DEV_STATE_NORMAL; + satDevData->satFormatState = agFALSE; + satDevData->satDeviceFaultState = agFALSE; + satDevData->satTmTaskTag = agNULL; + satDevData->satAbortAfterReset = agFALSE; + satDevData->satAbortCalled = agFALSE; + satDevData->satSectorDone = 0; + + /* Qeueu depth, Word 75 */ + satDevData->satNCQMaxIO = SATAIdData->queueDepth + 1; + TI_DBG3(("satSetDevInfo: max queue depth %d\n",satDevData->satNCQMaxIO)); + + /* Support NCQ, if Word 76 bit 8 is set */ + if (SATAIdData->sataCapabilities & 0x100) + { + TI_DBG3(("satSetDevInfo: device supports NCQ\n")); + satDevData->satNCQ = agTRUE; + } + else + { + TI_DBG3(("satSetDevInfo: no NCQ\n")); + satDevData->satNCQ = agFALSE; + } + + /* Support 48 bit addressing, if Word 83 bit 10 and Word 86 bit 10 are set */ + if ((SATAIdData->commandSetSupported1 & 0x400) && + (SATAIdData->commandSetFeatureEnabled1 & 0x400) ) + { + TI_DBG3(("satSetDevInfo: support 48 bit addressing\n")); + satDevData->sat48BitSupport = agTRUE; + } + else + { + TI_DBG3(("satSetDevInfo: NO 48 bit addressing\n")); + satDevData->sat48BitSupport = agFALSE; + } + + /* Support SMART Self Test, word84 bit 1 */ + if (SATAIdData->commandSetFeatureSupportedExt & 0x02) + { + TI_DBG3(("satSetDevInfo: SMART self-test supported \n")); + satDevData->satSMARTSelfTest = agTRUE; + } + else + { + TI_DBG3(("satSetDevInfo: no SMART self-test suppored\n")); + satDevData->satSMARTSelfTest = agFALSE; + } + + + + /* Support SMART feature set, word82 bit 0 */ + if (SATAIdData->commandSetSupported & 0x01) + { + TI_DBG3(("satSetDevInfo: SMART feature set supported \n")); + satDevData->satSMARTFeatureSet = agTRUE; + } + else + { + TI_DBG3(("satSetDevInfo: no SMART feature set suppored\n")); + satDevData->satSMARTFeatureSet = agFALSE; + } + + + + /* Support SMART enabled, word85 bit 0 */ + if (SATAIdData->commandSetFeatureEnabled & 0x01) + { + TI_DBG3(("satSetDevInfo: SMART enabled \n")); + satDevData->satSMARTEnabled = agTRUE; + } + else + { + TI_DBG3(("satSetDevInfo: no SMART enabled\n")); + satDevData->satSMARTEnabled = agFALSE; + } + + satDevData->satVerifyState = 0; + + /* Removable Media feature set support, word82 bit 2 */ + if (SATAIdData->commandSetSupported & 0x4) + { + TI_DBG3(("satSetDevInfo: Removable Media supported \n")); + satDevData->satRemovableMedia = agTRUE; + } + else + { + TI_DBG3(("satSetDevInfo: no Removable Media suppored\n")); + satDevData->satRemovableMedia = agFALSE; + } + + /* Removable Media feature set enabled, word 85, bit 2 */ + if (SATAIdData->commandSetFeatureEnabled & 0x4) + { + TI_DBG3(("satSetDevInfo: Removable Media enabled\n")); + satDevData->satRemovableMediaEnabled = agTRUE; + } + else + { + TI_DBG3(("satSetDevInfo: no Removable Media enabled\n")); + satDevData->satRemovableMediaEnabled = agFALSE; + } + + /* DMA Support, word49 bit8 */ + if (SATAIdData->dma_lba_iod_ios_stimer & 0x100) + { + TI_DBG3(("satSetDevInfo: DMA supported \n")); + satDevData->satDMASupport = agTRUE; + } + else + { + TI_DBG3(("satSetDevInfo: no DMA suppored\n")); + satDevData->satDMASupport = agFALSE; + } + + /* DMA Enabled, word88 bit0-6, bit8-14*/ + /* 0x7F7F = 0111 1111 0111 1111*/ + if (SATAIdData->ultraDMAModes & 0x7F7F) + { + TI_DBG3(("satSetDevInfo: DMA enabled \n")); + satDevData->satDMAEnabled = agTRUE; + } + else + { + TI_DBG3(("satSetDevInfo: no DMA enabled\n")); + satDevData->satDMAEnabled = agFALSE; + } + + /* + setting MaxUserAddrSectors: max user addressable setctors + word60 - 61, should be 0x 0F FF FF FF + */ + satDevData->satMaxUserAddrSectors + = (SATAIdData->numOfUserAddressableSectorsHi << (8*2) ) + + SATAIdData->numOfUserAddressableSectorsLo; + TI_DBG3(("satSetDevInfo: MaxUserAddrSectors 0x%x decimal %d\n", satDevData->satMaxUserAddrSectors, satDevData->satMaxUserAddrSectors)); + /* Support DMADIR, if Word 62 bit 8 is set */ + if (SATAIdData->word62_74[0] & 0x8000) + { + TI_DBG3(("satSetDevInfo: DMADIR enabled\n")); + satDevData->satDMADIRSupport = agTRUE; + } + else + { + TI_DBG3(("satSetDevInfo: DMADIR disabled\n")); + satDevData->satDMADIRSupport = agFALSE; + } + + + /* write cache enabled for caching mode page SAT Table 67 p69, word85 bit5 */ + if (SATAIdData->commandSetFeatureEnabled & 0x20) + { + TI_DBG3(("satSetDevInfo: write cache enabled\n")); + satDevData->satWriteCacheEnabled = agTRUE; + } + else + { + TI_DBG3(("satSetDevInfo: no write cache enabled\n")); + satDevData->satWriteCacheEnabled = agFALSE; + } + + /* look ahead enabled for caching mode page SAT Table 67 p69, word85 bit6 */ + if (SATAIdData->commandSetFeatureEnabled & 0x40) + { + TI_DBG3(("satSetDevInfo: look ahead enabled\n")); + satDevData->satLookAheadEnabled = agTRUE; + } + else + { + TI_DBG3(("satSetDevInfo: no look ahead enabled\n")); + satDevData->satLookAheadEnabled = agFALSE; + } + + /* Support WWN, if Word 87 bit 8 is set */ + if (SATAIdData->commandSetFeatureDefault & 0x100) + { + TI_DBG3(("satSetDevInfo: device supports WWN\n")); + satDevData->satWWNSupport = agTRUE; + } + else + { + TI_DBG3(("satSetDevInfo: no WWN\n")); + satDevData->satWWNSupport = agFALSE; + } + + + return; +} + +/***************************************************************************** +*! \brief satInquiryCB +* +* This routine is a callback function for satInquiry() +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void satInquiryCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + /* + In the process of Inquiry + Process SAT_IDENTIFY_DEVICE + */ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdIORequestBody; + tdIORequestBody_t *tdOrgIORequestBody; + satIOContext_t *satIOContext; + satIOContext_t *satOrgIOContext; + satInternalIo_t *satIntIo; + satDeviceData_t *satDevData; +#ifdef TD_DEBUG_ENABLE + tdsaDeviceData_t *tdsaDeviceData; + bit32 ataStatus = 0; + bit32 ataError; + agsaFisPioSetupHeader_t *satPIOSetupHeader = agNULL; +#endif + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + tiIORequest_t *tiOrgIORequest; + tiScsiInitiatorRequest_t *tiScsiRequest; /* TD's tiScsiXchg */ + tiScsiInitiatorRequest_t *tiOrgScsiRequest; /* OS's tiScsiXchg */ + agsaSATAIdentifyData_t *pSATAIdData; + bit8 *pInquiry; + bit8 page = 0xFF; + bit16 *tmpptr,tmpptr_tmp; + bit32 x; + bit32 lenReceived; + bit32 lenNeeded = 0; + + TI_DBG6(("satInquiryCB: start\n")); + TI_DBG6(("satInquiryCB: agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satIOContext = (satIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + satDevData = satIOContext->pSatDevData; +#ifdef TD_DEBUG_ENABLE + tdsaDeviceData = (tdsaDeviceData_t *)satDevData->satSaDeviceData; +#endif + tiScsiRequest = satIOContext->tiScsiXchg; + if (satIntIo == agNULL) + { + TI_DBG6(("satInquiryCB: External, OS generated\n")); + pSense = satIOContext->pSense; + scsiCmnd = satIOContext->pScsiCmnd; + satOrgIOContext = satIOContext; + tiOrgIORequest = tdIORequestBody->tiIORequest; + } + else + { + TI_DBG6(("satInquiryCB: Internal, TD generated\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + TI_DBG1(("satInquiryCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + TI_DBG6(("satInquiryCB: satOrgIOContext is NOT NULL\n")); + } + tdOrgIORequestBody = (tdIORequestBody_t *)satOrgIOContext->tiRequestBody; + tiOrgIORequest = (tiIORequest_t *)tdOrgIORequestBody->tiIORequest; + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + + tiOrgScsiRequest = satOrgIOContext->tiScsiXchg; + pInquiry = (bit8 *) tiOrgScsiRequest->sglVirtualAddr; + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + TI_DBG3(("satInquiryCB: did %d\n", tdsaDeviceData->id)); + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satInquiryCB: wrong. agFirstDword is NULL when error, status %d\n", agIOStatus)); + if (agIOStatus == OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY) + { + TI_DBG1(("satInquiryCB: OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n")); + /* should NOT be retried */ + ostiInitiatorIOCompleted ( + tiRoot, + tiOrgIORequest, + tiIOFailed, + tiDetailNoLogin, + agNULL, + satOrgIOContext->interruptContext + ); + } + else + { + TI_DBG1(("satInquiryCB: NOT OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n")); + ostiInitiatorIOCompleted ( + tiRoot, + tiOrgIORequest, + tiIOFailed, + tiDetailNoLogin, + agNULL, + satOrgIOContext->interruptContext + ); + } + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + if (agIOStatus == OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_BREAK || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_UNKNOWN_ERROR || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY + ) + { + TI_DBG1(("satInquiryCB: OSSA_IO_OPEN_CNX_ERROR\n")); + + ostiInitiatorIOCompleted ( + tiRoot, + tiOrgIORequest, + tiIOFailed, + tiDetailNoLogin, + agNULL, + satOrgIOContext->interruptContext + ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + if ( agIOStatus != OSSA_IO_SUCCESS || + (agIOStatus == OSSA_IO_SUCCESS && agFirstDword != agNULL && agIOInfoLen != 0) + ) + { +#ifdef TD_DEBUG_ENABLE + // only agsaFisPioSetup_t is expected + satPIOSetupHeader = (agsaFisPioSetupHeader_t *)&(agFirstDword->PioSetup); + ataStatus = satPIOSetupHeader->status; // ATA Status register + ataError = satPIOSetupHeader->error; // ATA Eror register +#endif + TI_DBG1(("satInquiryCB: ataStatus 0x%x ataError 0x%x\n", ataStatus, ataError)); + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + satProcessAbort(tiRoot, + tiOrgIORequest, + satOrgIOContext + ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + ostiInitiatorIOCompleted ( + tiRoot, + tiOrgIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + /* success */ + + + /* Convert to host endian */ + tmpptr = (bit16*)(tiScsiRequest->sglVirtualAddr); + for (x=0; x < sizeof(agsaSATAIdentifyData_t)/sizeof(bit16); x++) + { + OSSA_READ_LE_16(AGROOT, &tmpptr_tmp, tmpptr, 0); + *tmpptr = tmpptr_tmp; + tmpptr++; + /*Print tmpptr_tmp here for debugging purpose*/ + } + + pSATAIdData = (agsaSATAIdentifyData_t *)(tiScsiRequest->sglVirtualAddr); + + TI_DBG5(("satInquiryCB: OS satOrgIOContext %p \n", satOrgIOContext)); + TI_DBG5(("satInquiryCB: TD satIOContext %p \n", satIOContext)); + TI_DBG5(("satInquiryCB: OS tiScsiXchg %p \n", satOrgIOContext->tiScsiXchg)); + TI_DBG5(("satInquiryCB: TD tiScsiXchg %p \n", satIOContext->tiScsiXchg)); + + /* copy ID Dev data to satDevData */ + satDevData->satIdentifyData = *pSATAIdData; + satDevData->IDDeviceValid = agTRUE; +#ifdef TD_INTERNAL_DEBUG + tdhexdump("satInquiryCB ID Dev data",(bit8 *)pSATAIdData, sizeof(agsaSATAIdentifyData_t)); + tdhexdump("satInquiryCB Device ID Dev data",(bit8 *)&satDevData->satIdentifyData, sizeof(agsaSATAIdentifyData_t)); +#endif +// tdhexdump("satInquiryCB Device ID Dev data",(bit8 *)&satDevData->satIdentifyData, sizeof(agsaSATAIdentifyData_t)); + + /* set satDevData fields from IndentifyData */ + satSetDevInfo(satDevData,pSATAIdData); + + lenReceived = ((scsiCmnd->cdb[3]) << 8) + scsiCmnd->cdb[4]; + + /* SPC-4, spec 6.4 p 141 */ + /* EVPD bit == 0 */ + if (!(scsiCmnd->cdb[1] & SCSI_EVPD_MASK)) + { + /* Returns the standard INQUIRY data */ + lenNeeded = STANDARD_INQUIRY_SIZE; + + + satInquiryStandard(pInquiry, pSATAIdData, scsiCmnd); + //tdhexdump("satInquiryCB ***standard***", (bit8 *)pInquiry, 36); + + } + else + { + /* EVPD bit != 0 && PAGE CODE != 0 */ + /* returns the pages of vital product data information */ + + /* we must support page 00h, 83h and 89h */ + page = scsiCmnd->cdb[2]; + if ((page != INQUIRY_SUPPORTED_VPD_PAGE) && + (page != INQUIRY_DEVICE_IDENTIFICATION_VPD_PAGE) && + (page != INQUIRY_ATA_INFORMATION_VPD_PAGE)) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + TI_DBG1(("satInquiryCB: invalid PAGE CODE 0x%x\n", page)); + return; + } + + /* checking length */ + switch (page) + { + case INQUIRY_SUPPORTED_VPD_PAGE: + lenNeeded = SATA_PAGE0_INQUIRY_SIZE; /* 36 */ + break; + case INQUIRY_DEVICE_IDENTIFICATION_VPD_PAGE: + if (satDevData->satWWNSupport) + { + lenNeeded = SATA_PAGE83_INQUIRY_WWN_SIZE; /* 16 */ + } + else + { + lenNeeded = SATA_PAGE83_INQUIRY_NO_WWN_SIZE; /* 76 */ + } + break; + case INQUIRY_ATA_INFORMATION_VPD_PAGE: + lenNeeded = SATA_PAGE89_INQUIRY_SIZE; /* 572 */ + break; + default: + TI_DBG1(("satInquiryCB: wrong!!! invalid PAGE CODE 0x%x\n", page)); + break; + } + + + /* + * Fill in the Inquiry data depending on what Inquiry data we are returning. + */ + switch (page) + { + case INQUIRY_SUPPORTED_VPD_PAGE: + satInquiryPage0(pInquiry, pSATAIdData); + break; + case INQUIRY_DEVICE_IDENTIFICATION_VPD_PAGE: + satInquiryPage83(pInquiry, pSATAIdData, satDevData); + break; + case INQUIRY_ATA_INFORMATION_VPD_PAGE: + satInquiryPage89(pInquiry, pSATAIdData, satDevData); + break; + default: + TI_DBG1(("satInquiryCB: wrong!!! invalidinvalid PAGE CODE 0x%x\n", page)); + break; + } + } /* else */ + + TI_DBG6(("satInquiryCB: calling ostiInitiatorIOCompleted\n")); + + if (lenReceived > lenNeeded) + { + TI_DBG6(("satInquiryCB reporting underrun lenNeeded=0x%x lenReceived=0x%x tiIORequest=%p\n", + lenNeeded, lenReceived, tiOrgIORequest)); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, + tiIOUnderRun, + lenReceived - lenNeeded, + agNULL, + satOrgIOContext->interruptContext ); + } + else + { + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext); + } + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + TI_DBG5(("satInquiryCB: device %p pending IO %d\n", satDevData, satDevData->satPendingIO)); + TI_DBG6(("satInquiryCB: end\n")); + return; +} + + +/*****************************************************************************/ +/*! \brief satInquiryIntCB. + * + * This function is part of INQUIRY SAT implementation. This is called when + * ATA identify device data is available. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +void satInquiryIntCB( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext + ) +{ + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + satDeviceData_t *satDevData; + agsaSATAIdentifyData_t *pSATAIdData; + + bit8 *pInquiry; + bit8 page = 0xFF; + bit32 lenReceived; + bit32 lenNeeded = 0; + + TI_DBG6(("satInquiryIntCB: start\n")); + + pSense = satIOContext->pSense; + scsiCmnd = &tiScsiRequest->scsiCmnd; + pInquiry = (bit8 *) tiScsiRequest->sglVirtualAddr; + satDevData = satIOContext->pSatDevData; + pSATAIdData = &satDevData->satIdentifyData; + + + lenReceived = ((scsiCmnd->cdb[3]) << 8) + scsiCmnd->cdb[4]; + + /* SPC-4, spec 6.4 p 141 */ + /* EVPD bit == 0 */ + if (!(scsiCmnd->cdb[1] & SCSI_EVPD_MASK)) + { + /* Returns the standard INQUIRY data */ + lenNeeded = STANDARD_INQUIRY_SIZE; + + satInquiryStandard(pInquiry, pSATAIdData, scsiCmnd); + //tdhexdump("satInquiryIntCB ***standard***", (bit8 *)pInquiry, 36); + + } + else + { + /* EVPD bit != 0 && PAGE CODE != 0 */ + /* returns the pages of vital product data information */ + + /* we must support page 00h, 83h and 89h */ + page = scsiCmnd->cdb[2]; + if ((page != INQUIRY_SUPPORTED_VPD_PAGE) && + (page != INQUIRY_DEVICE_IDENTIFICATION_VPD_PAGE) && + (page != INQUIRY_ATA_INFORMATION_VPD_PAGE) && + (page != INQUIRY_UNIT_SERIAL_NUMBER_VPD_PAGE)) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satInquiryIntCB: invalid PAGE CODE 0x%x\n", page)); + return; + } + + /* checking length */ + switch (page) + { + case INQUIRY_SUPPORTED_VPD_PAGE: + lenNeeded = SATA_PAGE0_INQUIRY_SIZE; /* 36 */ + break; + case INQUIRY_DEVICE_IDENTIFICATION_VPD_PAGE: + if (satDevData->satWWNSupport) + { + lenNeeded = SATA_PAGE83_INQUIRY_WWN_SIZE; /* 16 */ + } + else + { + lenNeeded = SATA_PAGE83_INQUIRY_NO_WWN_SIZE; /* 76 */ + } + break; + case INQUIRY_ATA_INFORMATION_VPD_PAGE: + lenNeeded = SATA_PAGE89_INQUIRY_SIZE; /* 572 */ + break; + case INQUIRY_UNIT_SERIAL_NUMBER_VPD_PAGE: + lenNeeded = SATA_PAGE80_INQUIRY_SIZE; /* 24 */ + break; + + default: + TI_DBG1(("satInquiryIntCB: wrong!!! invalidinvalid PAGE CODE 0x%x\n", page)); + break; + } + + + /* + * Fill in the Inquiry data depending on what Inquiry data we are returning. + */ + switch (page) + { + case INQUIRY_SUPPORTED_VPD_PAGE: + satInquiryPage0(pInquiry, pSATAIdData); + break; + case INQUIRY_DEVICE_IDENTIFICATION_VPD_PAGE: + satInquiryPage83(pInquiry, pSATAIdData, satDevData); + break; + case INQUIRY_ATA_INFORMATION_VPD_PAGE: + satInquiryPage89(pInquiry, pSATAIdData, satDevData); + break; + case INQUIRY_UNIT_SERIAL_NUMBER_VPD_PAGE: + satInquiryPage80(pInquiry, pSATAIdData); + break; + default: + TI_DBG1(("satInquiryIntCB: wrong!!! invalidinvalid PAGE CODE 0x%x\n", page)); + break; + } + } /* else */ + + TI_DBG6(("satInquiryIntCB: calling ostiInitiatorIOCompleted\n")); + + if (lenReceived > lenNeeded) + { + TI_DBG6(("satInquiryIntCB reporting underrun lenNeeded=0x%x lenReceived=0x%x tiIORequest=%p\n", + lenNeeded, lenReceived, tiIORequest)); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOUnderRun, + lenReceived - lenNeeded, + agNULL, + satIOContext->interruptContext ); + } + else + { + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + } + + TI_DBG5(("satInquiryIntCB: device %p pending IO %d\n", satDevData, satDevData->satPendingIO)); + TI_DBG6(("satInquiryIntCB: end\n")); + return; +} + + +/***************************************************************************** +*! \brief satVerify10CB +* +* This routine is a callback function called from ossaSATACompleted(). +* This CB routine deals with Verify(10) completion. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void satVerify10CB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdIORequestBody; + tdIORequestBody_t *tdOrgIORequestBody; + satIOContext_t *satIOContext; + satIOContext_t *satOrgIOContext; + satInternalIo_t *satIntIo; + satDeviceData_t *satDevData; + scsiRspSense_t *pSense; + tiIORequest_t *tiOrgIORequest; + + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + + TI_DBG5(("satVerify10CB: agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate tiIOContext */ + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satIOContext = (satIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + satDevData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + + if (satIntIo == agNULL) + { + TI_DBG4(("satVerify10CB: External satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + tiOrgIORequest = tdIORequestBody->tiIORequest; + pSense = satIOContext->pSense; + } + else + { + TI_DBG4(("satVerify10CB: Internal satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + TI_DBG4(("satVerify10CB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + TI_DBG4(("satVerify10CB: satOrgIOContext is NOT NULL\n")); + } + tdOrgIORequestBody = (tdIORequestBody_t *)satOrgIOContext->tiRequestBody; + tiOrgIORequest = (tiIORequest_t *)tdOrgIORequestBody->tiIORequest; + pSense = satOrgIOContext->pSense; + } + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satVerify10CB: wrong. agFirstDword is NULL when error, status %d\n", agIOStatus)); + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* only agsaFisRegDeviceToHost_t is expected */ + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + } + + if( agIOStatus != OSSA_IO_SUCCESS) + { + if ( (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) || + ((ataStatus & ERR_ATA_STATUS_MASK) || (ataStatus & DF_ATA_STATUS_MASK)) + ) + { + /* for debugging */ + if( agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satVerify10CB: FAILED, NOT IO_SUCCESS\n")); + } + else if (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) + { + TI_DBG1(("satVerify10CB: FAILED, Wrong FIS type 0x%x\n",statDevToHostFisHeader->fisType)); + } + else if ( (ataStatus & ERR_ATA_STATUS_MASK) || + (ataStatus & DF_ATA_STATUS_MASK) + ) + { + TI_DBG1(("satVerify10CB: FAILED, FAILED, error status\n")); + } + + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + satProcessAbort(tiRoot, + tiOrgIORequest, + satOrgIOContext + ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + /* for debugging */ + switch (hostToDevFis->h.command) + { + case SAT_READ_VERIFY_SECTORS_EXT: + TI_DBG1(("satVerify10CB: SAT_READ_VERIFY_SECTORS_EXT\n")); + break; + default: + TI_DBG1(("satVerify10CB: error default case command 0x%x\n", hostToDevFis->h.command)); + break; + } + + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } /* end error checking */ + } + + /* process success from this point on */ + switch (hostToDevFis->h.command) + { + case SAT_READ_VERIFY_SECTORS_EXT: + TI_DBG5(("satVerify10CB: SAT_WRITE_DMA_EXT success \n")); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext); + break; + default: + TI_DBG1(("satVerify10CB: success but error default case command 0x%x\n", hostToDevFis->h.command)); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + break; + } + + return; +} + +/* similar to satVerify10CB */ +void satNonChainedVerifyCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdIORequestBody; + tdIORequestBody_t *tdOrgIORequestBody; + satIOContext_t *satIOContext; + satIOContext_t *satOrgIOContext; + satInternalIo_t *satIntIo; + satDeviceData_t *satDevData; + scsiRspSense_t *pSense; + tiIORequest_t *tiOrgIORequest; + + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + + TI_DBG5(("satNonChainedVerifyCB: agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate tiIOContext */ + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satIOContext = (satIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + satDevData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + + if (satIntIo == agNULL) + { + TI_DBG4(("satNonChainedVerifyCB: External satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + tiOrgIORequest = tdIORequestBody->tiIORequest; + pSense = satIOContext->pSense; + } + else + { + TI_DBG4(("satNonChainedVerifyCB: Internal satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + TI_DBG4(("satNonChainedVerifyCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + TI_DBG4(("satNonChainedVerifyCB: satOrgIOContext is NOT NULL\n")); + } + tdOrgIORequestBody = (tdIORequestBody_t *)satOrgIOContext->tiRequestBody; + tiOrgIORequest = (tiIORequest_t *)tdOrgIORequestBody->tiIORequest; + pSense = satOrgIOContext->pSense; + } + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satNonChainedVerifyCB: wrong. agFirstDword is NULL when error, status %d\n", agIOStatus)); + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* only agsaFisRegDeviceToHost_t is expected */ + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + } + + if( agIOStatus != OSSA_IO_SUCCESS) + { + if ( (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) || + ((ataStatus & ERR_ATA_STATUS_MASK) || (ataStatus & DF_ATA_STATUS_MASK)) + ) + { + /* for debugging */ + if( agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satNonChainedVerifyCB: FAILED, NOT IO_SUCCESS\n")); + } + else if (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) + { + TI_DBG1(("satNonChainedVerifyCB: FAILED, Wrong FIS type 0x%x\n",statDevToHostFisHeader->fisType)); + } + else if ( (ataStatus & ERR_ATA_STATUS_MASK) || + (ataStatus & DF_ATA_STATUS_MASK) + ) + { + TI_DBG1(("satNonChainedVerifyCB: FAILED, FAILED, error status\n")); + } + + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + satProcessAbort(tiRoot, + tiOrgIORequest, + satOrgIOContext + ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + /* for debugging */ + switch (hostToDevFis->h.command) + { + case SAT_READ_VERIFY_SECTORS: + TI_DBG1(("satNonChainedVerifyCB: SAT_READ_VERIFY_SECTORS\n")); + break; + case SAT_READ_VERIFY_SECTORS_EXT: + TI_DBG1(("satNonChainedVerifyCB: SAT_READ_VERIFY_SECTORS_EXT\n")); + break; + default: + TI_DBG1(("satNonChainedVerifyCB: error default case command 0x%x\n", hostToDevFis->h.command)); + break; + } + + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } /* end error checking */ + } + + /* process success from this point on */ + switch (hostToDevFis->h.command) + { + case SAT_READ_VERIFY_SECTORS: /* fall through */ + case SAT_READ_VERIFY_SECTORS_EXT: + TI_DBG5(("satNonChainedVerifyCB: SAT_WRITE_DMA_EXT success \n")); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext); + break; + default: + TI_DBG1(("satNonChainedVerifyCB: success but error default case command 0x%x\n", hostToDevFis->h.command)); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + break; + } + + return; +} + +void satChainedVerifyCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdIORequestBody; + tdIORequestBody_t *tdOrgIORequestBody; + satIOContext_t *satIOContext; + satIOContext_t *satOrgIOContext; + satIOContext_t *satNewIOContext; + satInternalIo_t *satIntIo; + satInternalIo_t *satNewIntIo = agNULL; + satDeviceData_t *satDevData; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + tiIORequest_t *tiOrgIORequest; + + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + bit32 status = tiError; + bit32 dataLength; + + TI_DBG5(("satChainedVerifyCB: agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate tiIOContext */ + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satIOContext = (satIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + satDevData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + + if (satIntIo == agNULL) + { + TI_DBG4(("satChainedVerifyCB: External satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + tiOrgIORequest = tdIORequestBody->tiIORequest; + pSense = satIOContext->pSense; + scsiCmnd = satIOContext->pScsiCmnd; + } + else + { + TI_DBG4(("satChainedVerifyCB: Internal satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + TI_DBG4(("satChainedVerifyCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + TI_DBG4(("satChainedVerifyCB: satOrgIOContext is NOT NULL\n")); + } + tdOrgIORequestBody = (tdIORequestBody_t *)satOrgIOContext->tiRequestBody; + tiOrgIORequest = (tiIORequest_t *)tdOrgIORequestBody->tiIORequest; + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satChainedVerifyCB: wrong. agFirstDword is NULL when error, status %d\n", agIOStatus)); + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* only agsaFisRegDeviceToHost_t is expected */ + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + } + + if( agIOStatus != OSSA_IO_SUCCESS) + { + if ( (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) || + ((ataStatus & ERR_ATA_STATUS_MASK) || (ataStatus & DF_ATA_STATUS_MASK)) + ) + { + /* for debugging */ + if( agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satChainedVerifyCB: FAILED, NOT IO_SUCCESS\n")); + } + else if (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) + { + TI_DBG1(("satChainedVerifyCB: FAILED, Wrong FIS type 0x%x\n",statDevToHostFisHeader->fisType)); + } + else if ( (ataStatus & ERR_ATA_STATUS_MASK) || + (ataStatus & DF_ATA_STATUS_MASK) + ) + { + TI_DBG1(("satChainedVerifyCB: FAILED, FAILED, error status\n")); + } + + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + satProcessAbort(tiRoot, + tiOrgIORequest, + satOrgIOContext + ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + /* for debugging */ + switch (hostToDevFis->h.command) + { + case SAT_READ_VERIFY_SECTORS: + TI_DBG1(("satChainedVerifyCB: SAT_READ_VERIFY_SECTORS\n")); + break; + case SAT_READ_VERIFY_SECTORS_EXT: + TI_DBG1(("satChainedVerifyCB: SAT_READ_VERIFY_SECTORS_EXT\n")); + break; + default: + TI_DBG1(("satChainedVerifyCB: error default case command 0x%x\n", hostToDevFis->h.command)); + break; + } + + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } /* end error checking */ + } + + /* process success from this point on */ + switch (hostToDevFis->h.command) + { + case SAT_READ_VERIFY_SECTORS: /* fall through */ + case SAT_READ_VERIFY_SECTORS_EXT: + TI_DBG5(("satChainedVerifyCB: SAT_WRITE_DMA_EXT success \n")); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + /* let's loop till TL */ + + /* lba = lba + tl + loopnum--; + if (loopnum == 0) done + */ + (satOrgIOContext->LoopNum)--; + if (satOrgIOContext->LoopNum == 0) + { + /* + done with write and verify + */ + ostiInitiatorIOCompleted( tiRoot, + + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + return; + } + + if (satOrgIOContext->superIOFlag) + { + dataLength = ((tiSuperScsiInitiatorRequest_t *) satOrgIOContext->tiScsiXchg)->scsiCmnd.expDataLength; + } + else + { + dataLength = ((tiScsiInitiatorRequest_t *) satOrgIOContext->tiScsiXchg)->scsiCmnd.expDataLength; + } + + satNewIntIo = satAllocIntIoResource( tiRoot, + tiOrgIORequest, + satDevData, + dataLength, + satNewIntIo); + if (satNewIntIo == agNULL) + { + /* memory allocation failure */ + satFreeIntIoResource( tiRoot, + satDevData, + satNewIntIo); + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOFailed, + tiDetailOtherError, + agNULL, + satOrgIOContext->interruptContext ); + + TI_DBG1(("satChainedVerifyCB: momory allocation fails\n")); + return; + } /* end of memory allocation failure */ + + /* + * Need to initialize all the fields within satIOContext + */ + + satNewIOContext = satPrepareNewIO( + satNewIntIo, + tiOrgIORequest, + satDevData, + scsiCmnd, + satOrgIOContext + ); + status = satChainedVerify(tiRoot, + &satNewIntIo->satIntTiIORequest, + satNewIOContext->ptiDeviceHandle, + &satNewIntIo->satIntTiScsiXchg, + satNewIOContext); + + if (status != tiSuccess) + { + satFreeIntIoResource( tiRoot, + satDevData, + satNewIntIo); + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOFailed, + tiDetailOtherError, + agNULL, + satOrgIOContext->interruptContext ); + TI_DBG1(("satChainedVerifyCB: calling satChainedVerify fails\n")); + return; + } + + break; + default: + TI_DBG1(("satChainedVerifyCB: success but error default case command 0x%x\n", hostToDevFis->h.command)); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + break; + } + return; +} + +/***************************************************************************** +*! \brief satTestUnitReadyCB +* +* This routine is a callback function for satTestUnitReady() +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void satTestUnitReadyCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + /* + In the process of TestUnitReady + Process SAT_GET_MEDIA_STATUS + Process SAT_CHECK_POWER_MODE + */ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdIORequestBody; + tdIORequestBody_t *tdOrgIORequestBody; + satIOContext_t *satIOContext; + satIOContext_t *satOrgIOContext; + satIOContext_t *satNewIOContext; + satInternalIo_t *satIntIo; + satInternalIo_t *satNewIntIo = agNULL; + satDeviceData_t *satDevData; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + tiIORequest_t *tiOrgIORequest; + + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + bit32 ataError; + + bit32 status; + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + + TI_DBG6(("satTestUnitReadyCB: agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate tiIOContext */ + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satIOContext = (satIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + satDevData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + + if (satIntIo == agNULL) + { + TI_DBG5(("satTestUnitReadyCB: no internal satInternalIo_t satIntIoContext\n")); + pSense = satIOContext->pSense; + scsiCmnd = satIOContext->pScsiCmnd; + satOrgIOContext = satIOContext; + tiOrgIORequest = tdIORequestBody->tiIORequest; + } + else + { + TI_DBG5(("satTestUnitReadyCB: yes internal satInternalIo_t satIntIoContext\n")); + + /* orginal tiIOContext */ + tiOrgIORequest = (tiIORequest_t *)satIOContext->satIntIoContext->satOrgTiIORequest; + tdOrgIORequestBody = (tdIORequestBody_t *)tiOrgIORequest->tdData; + satOrgIOContext = &(tdOrgIORequestBody->transport.SATA.satIOContext); + + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satTestUnitReadyCB: wrong. agFirstDword is NULL when error, status %d\n", agIOStatus)); + satSetSensePayload( pSense, + SCSI_SNSKEY_NOT_READY, + 0, + SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_CAUSE_NOT_REPORTABLE, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + return; + } + /* + HW checks an error for us and the results is agIOStatus + */ + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* only agsaFisRegDeviceToHost_t is expected */ + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + ataError = statDevToHostFisHeader->error; /* ATA Eror register */ + + if (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) + { + TI_DBG1(("satTestUnitReadyCB: FAILED, Wrong FIS type 0x%x\n",statDevToHostFisHeader->fisType)); + } + else if ( (ataStatus & ERR_ATA_STATUS_MASK) || + (ataStatus & DF_ATA_STATUS_MASK) + ) + { + TI_DBG1(("satTestUnitReadyCB: FAILED, FAILED, error status\n")); + } + + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + satProcessAbort(tiRoot, + tiOrgIORequest, + satOrgIOContext + ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + switch (hostToDevFis->h.command) + { + case SAT_GET_MEDIA_STATUS: + TI_DBG1(("satTestUnitReadyCB: SAT_GET_MEDIA_STATUS failed \n")); + + /* checking NM bit */ + if (ataError & SCSI_NM_MASK) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_NOT_READY, + 0, + SCSI_SNSCODE_MEDIUM_NOT_PRESENT, + satOrgIOContext); + } + else + { + satSetSensePayload( pSense, + SCSI_SNSKEY_NOT_READY, + 0, + SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_CAUSE_NOT_REPORTABLE, + satOrgIOContext); + } + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + break; + case SAT_CHECK_POWER_MODE: + TI_DBG1(("satTestUnitReadyCB: SAT_CHECK_POWER_MODE failed \n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_NOT_READY, + 0, + SCSI_SNSCODE_LOGICAL_UNIT_DOES_NOT_RESPOND_TO_SELECTION, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + break; + default: + TI_DBG1(("satTestUnitReadyCB: default failed command %d\n", hostToDevFis->h.command)); + + satSetSensePayload( pSense, + SCSI_SNSKEY_NOT_READY, + 0, + SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_CAUSE_NOT_REPORTABLE, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + break; + + } + return; + }/* end error */ + + /* ATA command completes sucessfully */ + switch (hostToDevFis->h.command) + { + case SAT_GET_MEDIA_STATUS: + + TI_DBG5(("satTestUnitReadyCB: SAT_GET_MEDIA_STATUS success\n")); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + satNewIntIo = satAllocIntIoResource( tiRoot, + tiOrgIORequest, + satDevData, + 0, + satNewIntIo); + if (satNewIntIo == agNULL) + { + /* memory allocation failure */ + satFreeIntIoResource( tiRoot, + satDevData, + satNewIntIo); + satSetSensePayload( pSense, + SCSI_SNSKEY_NOT_READY, + 0, + SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_CAUSE_NOT_REPORTABLE, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + TI_DBG1(("satTestUnitReadyCB: momory allocation fails\n")); + return; + } + + /* + * Need to initialize all the fields within satIOContext + */ + + satNewIOContext = satPrepareNewIO( + satNewIntIo, + tiOrgIORequest, + satDevData, + scsiCmnd, + satOrgIOContext + ); + + /* sends SAT_CHECK_POWER_MODE */ + status = satTestUnitReady_1( tiRoot, + &satNewIntIo->satIntTiIORequest, + satNewIOContext->ptiDeviceHandle, + &satNewIntIo->satIntTiScsiXchg, + satNewIOContext); + + if (status != tiSuccess) + { + /* sending SAT_CHECK_POWER_MODE fails */ + satFreeIntIoResource( tiRoot, + satDevData, + satNewIntIo); + satSetSensePayload( pSense, + SCSI_SNSKEY_NOT_READY, + 0, + SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_CAUSE_NOT_REPORTABLE, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + TI_DBG1(("satTestUnitReadyCB: calling satTestUnitReady_1 fails\n")); + return; + } + + break; + case SAT_CHECK_POWER_MODE: + TI_DBG5(("satTestUnitReadyCB: SAT_CHECK_POWER_MODE success\n")); + + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + /* returns good status */ + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + + break; + default: + TI_DBG1(("satTestUnitReadyCB: default success command %d\n", hostToDevFis->h.command)); + satSetSensePayload( pSense, + SCSI_SNSKEY_NOT_READY, + 0, + SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_CAUSE_NOT_REPORTABLE, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + break; + } + + return; +} + +/***************************************************************************** +*! \brief satWriteSame10CB +* +* This routine is a callback function for satWriteSame10() +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void satWriteSame10CB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdIORequestBody; + tdIORequestBody_t *tdOrgIORequestBody; + tdIORequestBody_t *tdNewIORequestBody; + satIOContext_t *satIOContext; + satIOContext_t *satOrgIOContext; + satIOContext_t *satNewIOContext; + satInternalIo_t *satIntIo; + satInternalIo_t *satNewIntIo = agNULL; + satDeviceData_t *satDevData; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + tiIORequest_t *tiOrgIORequest; + + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + bit32 status; + + bit32 sectorcount = 0; + bit32 lba = 0, tl = 0; + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + agsaFisSetDevBitsHeader_t *statSetDevBitFisHeader = agNULL; + + TI_DBG5(("satWriteSame10CB: agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate tiIOContext */ + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satIOContext = (satIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + satDevData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + + if (satIntIo == agNULL) + { + TI_DBG4(("satWriteSame10CB: External satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + tiOrgIORequest = tdIORequestBody->tiIORequest; + pSense = satIOContext->pSense; + scsiCmnd = satIOContext->pScsiCmnd; + } + else + { + TI_DBG4(("satWriteSame10CB: Internal satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + TI_DBG4(("satWriteSame10CB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + TI_DBG4(("satWriteSame10CB: satOrgIOContext is NOT NULL\n")); + } + tdOrgIORequestBody = (tdIORequestBody_t *)satOrgIOContext->tiRequestBody; + tiOrgIORequest = (tiIORequest_t *)tdOrgIORequestBody->tiIORequest; + + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satWriteSame10CB: wrong. agFirstDword is NULL when error, status %d\n", agIOStatus)); + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* FP, DMA and PIO write */ + /* First, assumed to be Reg Device to Host FIS */ + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + } + + if (agIOStatus != OSSA_IO_SUCCESS) + { + if (statDevToHostFisHeader->fisType == SET_DEV_BITS_FIS) + { + statSetDevBitFisHeader = (agsaFisSetDevBitsHeader_t *)&(agFirstDword->D2H); + + /* Get ATA Status register */ + ataStatus = (statSetDevBitFisHeader->statusHi_Lo & 0x70); /* bits 4,5,6 */ + ataStatus = ataStatus | (statSetDevBitFisHeader->statusHi_Lo & 0x07); /* bits 0,1,2 */ + + /* ATA Eror register */ + + } + } + + if( agIOStatus != OSSA_IO_SUCCESS) + { + /* + checking IO status, FIS type and error status + FIS type should be either REG_DEV_TO_HOST_FIS or SET_DEV_BITS_FIS + */ + if ( ((statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) && + (statDevToHostFisHeader->fisType != SET_DEV_BITS_FIS)) || + ((ataStatus & ERR_ATA_STATUS_MASK) || (ataStatus & DF_ATA_STATUS_MASK)) + ) + { + /* for debugging */ + if( agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satWriteSame10CB: FAILED, NOT IO_SUCCESS\n")); + } + else if (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) + { + TI_DBG1(("satWriteSame10CB: FAILED, Wrong FIS type 0x%x\n",statDevToHostFisHeader->fisType)); + } + else if (statDevToHostFisHeader->fisType != SET_DEV_BITS_FIS) + { + TI_DBG1(("satWriteSame10CB: FAILED, Wrong FIS type 0x%x\n",statDevToHostFisHeader->fisType)); + } + else if ( (ataStatus & ERR_ATA_STATUS_MASK) || + (ataStatus & DF_ATA_STATUS_MASK) + ) + { + TI_DBG1(("satWriteSame10CB: FAILED, FAILED, error status\n")); + } + + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + satProcessAbort(tiRoot, + tiOrgIORequest, + satOrgIOContext + ); + + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + /* for debugging */ + switch (hostToDevFis->h.command) + { + case SAT_WRITE_DMA_EXT: + TI_DBG1(("satWriteSame10CB: SAT_WRITE_DMA_EXT\n")); + break; + case SAT_WRITE_SECTORS_EXT: + TI_DBG1(("satWriteSame10CB: SAT_WRITE_SECTORS_EXT\n")); + break; + case SAT_WRITE_FPDMA_QUEUED: + TI_DBG1(("satWriteSame10CB: SAT_WRITE_FPDMA_QUEUED\n")); + break; + default: + TI_DBG1(("satWriteSame10CB: error default case command 0x%x\n", hostToDevFis->h.command)); + break; + } + + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } /* end error */ + } + + /* process success from this point on */ + /* + note: inefficient implementation until a single block can be manipulated + */ + + if (hostToDevFis->h.command == SAT_WRITE_DMA_EXT) + { + TI_DBG5(("satWriteSame10CB: SAT_WRITE_DMA_EXT success\n")); + } + else if (hostToDevFis->h.command == SAT_WRITE_SECTORS_EXT) + { + TI_DBG5(("satWriteSame10CB: SAT_WRITE_SECTORS_EXT success\n")); + } + else if (hostToDevFis->h.command == SAT_WRITE_FPDMA_QUEUED) + { + TI_DBG5(("satWriteSame10CB: SAT_WRITE_FPDMA_QUEUED success\n")); + } + else + { + TI_DBG1(("satWriteSame10CB: error case command 0x%x success\n", hostToDevFis->h.command)); + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + /* free */ + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + /* + increment LBA by one, keeping the same sector count(1) + sends another ATA command with the changed parameters + */ + + tdsaSingleThreadedEnter(tiRoot, TD_SATA_LOCK); + satDevData->satSectorDone++; + tdsaSingleThreadedLeave(tiRoot, TD_SATA_LOCK); + + TI_DBG1(("satWriteSame10CB: sectordone %d\n", satDevData->satSectorDone)); + + lba = (scsiCmnd->cdb[2] << (8*3)) + (scsiCmnd->cdb[3] << (8*2)) + + (scsiCmnd->cdb[4] << 8) + scsiCmnd->cdb[5]; + tl = (scsiCmnd->cdb[7] << 8) + scsiCmnd->cdb[8]; + + TI_DBG5(("satWriteSame10CB: lba 0x%x tl 0x%x\n", lba, tl)); + + if (tl == 0) + { + /* (satDevData->satMaxUserAddrSectors - 1) - lba*/ + sectorcount = (0x0FFFFFFF - 1) - lba; + } + else + { + sectorcount = tl; + } + + if (sectorcount <= 0) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + TI_DBG1(("satWriteSame10CB: incorrect sectorcount 0x%x\n", sectorcount)); + return; + } + + if (sectorcount == satDevData->satSectorDone) + { + /* + done with writesame + */ + TI_DBG1(("satWriteSame10CB: return writesame done\n")); + satDevData->satSectorDone = 0; + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + } + else + { + /* sends another ATA command */ + if (hostToDevFis->h.command == SAT_WRITE_DMA_EXT) + { + TI_DBG1(("satWriteSame10CB: sends another SAT_WRITE_DMA_EXT\n")); + } + else if (hostToDevFis->h.command == SAT_WRITE_SECTORS_EXT) + { + TI_DBG1(("satWriteSame10CB: sends another SAT_WRITE_SECTORS_EXT\n")); + } + else if (hostToDevFis->h.command == SAT_WRITE_FPDMA_QUEUED) + { + TI_DBG1(("satWriteSame10CB: sends another SAT_WRITE_FPDMA_QUEUED\n")); + } + + satNewIntIo = satAllocIntIoResource( tiRoot, + tiOrgIORequest, + satDevData, + 0, + satNewIntIo); + if (satNewIntIo == agNULL) + { + /* memory allocation failure */ + satFreeIntIoResource( tiRoot, + satDevData, + satNewIntIo); + + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + TI_DBG1(("satWriteSame10CB: momory allocation fails\n")); + return; + } /* end memory allocation */ + + /* the one to be used */ + tdNewIORequestBody = satNewIntIo->satIntRequestBody; + satNewIOContext = &tdNewIORequestBody->transport.SATA.satIOContext; + + satNewIOContext->pSatDevData = satDevData; + satNewIOContext->pFis = &tdNewIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev; + satNewIOContext->pScsiCmnd = &satNewIntIo->satIntTiScsiXchg.scsiCmnd; + /* saves scsi command for LBA and number of blocks */ + osti_memcpy(satNewIOContext->pScsiCmnd, scsiCmnd, sizeof(tiIniScsiCmnd_t)); + satNewIOContext->pSense = &tdNewIORequestBody->transport.SATA.sensePayload; + satNewIOContext->pTiSenseData = &tdNewIORequestBody->transport.SATA.tiSenseData; + satNewIOContext->pTiSenseData->senseData = satNewIOContext->pSense; + satNewIOContext->tiRequestBody = satNewIntIo->satIntRequestBody; + satNewIOContext->interruptContext = satNewIOContext->interruptContext; + satNewIOContext->satIntIoContext = satNewIntIo; + satNewIOContext->ptiDeviceHandle = satIOContext->ptiDeviceHandle; + /* saves tiScsiXchg; only for writesame10() */ + satNewIOContext->tiScsiXchg = satOrgIOContext->tiScsiXchg; + + if (hostToDevFis->h.command == SAT_WRITE_DMA_EXT) + { + status = satWriteSame10_1( tiRoot, + &satNewIntIo->satIntTiIORequest, + satNewIOContext->ptiDeviceHandle, + &satNewIntIo->satIntTiScsiXchg, + satNewIOContext, + lba + satDevData->satSectorDone + ); + } + else if (hostToDevFis->h.command == SAT_WRITE_SECTORS_EXT) + { + status = satWriteSame10_2( tiRoot, + &satNewIntIo->satIntTiIORequest, + satNewIOContext->ptiDeviceHandle, + &satNewIntIo->satIntTiScsiXchg, + satNewIOContext, + lba + satDevData->satSectorDone + ); + } + else if (hostToDevFis->h.command == SAT_WRITE_FPDMA_QUEUED) + { + status = satWriteSame10_3( tiRoot, + &satNewIntIo->satIntTiIORequest, + satNewIOContext->ptiDeviceHandle, + &satNewIntIo->satIntTiScsiXchg, + satNewIOContext, + lba + satDevData->satSectorDone + ); + } + else + { + status = tiError; + TI_DBG1(("satWriteSame10CB: sucess but error in command 0x%x\n", hostToDevFis->h.command)); + } + + if (status != tiSuccess) + { + /* sending ATA command fails */ + satFreeIntIoResource( tiRoot, + satDevData, + satNewIntIo); + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + TI_DBG1(("satWriteSame10CB:calling satWriteSame10_1 fails\n")); + return; + } /* end send fails */ + + } /* end sends another ATA command */ + + return; +} +/***************************************************************************** +*! \brief satStartStopUnitCB +* +* This routine is a callback function called from ossaSATACompleted(). +* This CB routine deals with Send Diagnostic completion. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void satStartStopUnitCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + /* + In the process of StartStopUnit + Process FLUSH CACHE (EXT) + Process STANDBY + Process READ VERIFY SECTOR(S) EXT + Process MEDIA EJECT + */ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdIORequestBody; + tdIORequestBody_t *tdOrgIORequestBody; + satIOContext_t *satIOContext; + satIOContext_t *satOrgIOContext; + satIOContext_t *satNewIOContext; + satInternalIo_t *satIntIo; + satInternalIo_t *satNewIntIo = agNULL; + satDeviceData_t *satDevData; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + tiIORequest_t *tiOrgIORequest; + + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + bit32 status; + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + + TI_DBG5(("satStartStopUnitCB:agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate tiIOContext */ + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satIOContext = (satIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + satDevData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + + if (satIntIo == agNULL) + { + TI_DBG4(("satStartStopUnitCB: External satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + tiOrgIORequest = tdIORequestBody->tiIORequest; + pSense = satIOContext->pSense; + scsiCmnd = satIOContext->pScsiCmnd; + } + else + { + TI_DBG4(("satStartStopUnitCB: Internal satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + TI_DBG4(("satStartStopUnitCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + TI_DBG4(("satStartStopUnitCB: satOrgIOContext is NOT NULL\n")); + } + tdOrgIORequestBody = (tdIORequestBody_t *)satOrgIOContext->tiRequestBody; + tiOrgIORequest = (tiIORequest_t *)tdOrgIORequestBody->tiIORequest; + + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satStartStopUnitCB: wrong. agFirstDword is NULL when error, status %d\n", agIOStatus)); + + /* IMMED == 0 */ + if (!( scsiCmnd->cdb[1] & SCSI_IMMED_MASK)) + { + TI_DBG1(("satStartStopUnitCB: immed bit 0\n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_COMMAND_SEQUENCE_ERROR, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + } + /* IMMED == 1 */ + if ( scsiCmnd->cdb[1] & SCSI_IMMED_MASK) + { + TI_DBG1(("satStartStopUnitCB: immed bit 1\n")); + satSetDeferredSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_COMMAND_SEQUENCE_ERROR, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + } + + + + return; + } + + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* only agsaFisRegDeviceToHost_t is expected */ + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + } + /* + checking IO status, FIS type and error status + */ + if( agIOStatus != OSSA_IO_SUCCESS) + { + if( (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) || + ((ataStatus & ERR_ATA_STATUS_MASK) || (ataStatus & DF_ATA_STATUS_MASK)) + ) + { + /* for debugging */ + if( agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satStartStopUnitCB: FAILED, NOT IO_SUCCESS\n")); + } + else if (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) + { + TI_DBG1(("satStartStopUnitCB: FAILED, Wrong FIS type 0x%x\n",statDevToHostFisHeader->fisType)); + } + else if ( (ataStatus & ERR_ATA_STATUS_MASK) || + (ataStatus & DF_ATA_STATUS_MASK) + ) + { + TI_DBG1(("satStartStopUnitCB: FAILED, FAILED, error status\n")); + } + + + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + satProcessAbort(tiRoot, + tiOrgIORequest, + satOrgIOContext + ); + + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + switch (hostToDevFis->h.command) + { + case SAT_FLUSH_CACHE: /* fall through */ + case SAT_FLUSH_CACHE_EXT: + TI_DBG1(("satStartStopUnitCB: SAT_FLUSH_CACHE(_EXT)\n")); + /* check immed bit in scsi command */ + /* IMMED == 0 */ + if (!( scsiCmnd->cdb[1] & SCSI_IMMED_MASK)) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_COMMAND_SEQUENCE_ERROR, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + } + /* IMMED == 1 */ + if ( scsiCmnd->cdb[1] & SCSI_IMMED_MASK) + { + satSetDeferredSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_COMMAND_SEQUENCE_ERROR, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + } + break; + case SAT_STANDBY: + TI_DBG5(("satStartStopUnitCB: SAT_STANDBY\n")); + /* check immed bit in scsi command */ + /* IMMED == 0 */ + if (!( scsiCmnd->cdb[1] & SCSI_IMMED_MASK)) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_COMMAND_SEQUENCE_ERROR, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + } + /* IMMED == 1 */ + if ( scsiCmnd->cdb[1] & SCSI_IMMED_MASK) + { + satSetDeferredSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_COMMAND_SEQUENCE_ERROR, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + } + break; + case SAT_READ_VERIFY_SECTORS: /* fall through */ + case SAT_READ_VERIFY_SECTORS_EXT: + TI_DBG5(("satStartStopUnitCB: SAT_READ_VERIFY_SECTORS(_EXT)\n")); + /* IMMED == 0 */ + if (!( scsiCmnd->cdb[1] & SCSI_IMMED_MASK)) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_COMMAND_SEQUENCE_ERROR, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + } + /* IMMED == 1 */ + if ( scsiCmnd->cdb[1] & SCSI_IMMED_MASK) + { + satSetDeferredSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_COMMAND_SEQUENCE_ERROR, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + } + break; + case SAT_MEDIA_EJECT: + TI_DBG5(("satStartStopUnitCB: SAT_MEDIA_EJECT\n")); + /* IMMED == 0 */ + if (!( scsiCmnd->cdb[1] & SCSI_IMMED_MASK)) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_MEDIA_LOAD_OR_EJECT_FAILED, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + } + /* IMMED == 1 */ + if ( scsiCmnd->cdb[1] & SCSI_IMMED_MASK) + { + satSetDeferredSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_MEDIA_LOAD_OR_EJECT_FAILED, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + } + break; + default: + /* unspecified case, return no sense and no addition info */ + TI_DBG5(("satStartStopUnitCB: default command %d\n", hostToDevFis->h.command)); + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + break; + } /* switch */ + + return; + } /* error check */ + } + + /* ATA command completes sucessfully */ + switch (hostToDevFis->h.command) + { + case SAT_FLUSH_CACHE: /* fall through */ + case SAT_FLUSH_CACHE_EXT: + TI_DBG5(("satStartStopUnitCB: SAT_READ_VERIFY_SECTORS(_EXT) success case\n")); + + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + /* done with SAT_FLUSH_CACHE(_EXT) */ + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + /* at this point, successful SAT_READ_VERIFY_SECTORS(_EXT) + send SAT_SATNDBY + */ + satNewIntIo = satAllocIntIoResource( tiRoot, + tiOrgIORequest, + satDevData, + 0, + satNewIntIo); + if (satNewIntIo == agNULL) + { + /* memory allocation failure */ + satFreeIntIoResource( tiRoot, + satDevData, + satNewIntIo); + /* IMMED == 0 */ + if (!( scsiCmnd->cdb[1] & SCSI_IMMED_MASK)) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_COMMAND_SEQUENCE_ERROR, + satOrgIOContext); + } + else /* IMMED == 1 */ + { + satSetDeferredSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_COMMAND_SEQUENCE_ERROR, + satOrgIOContext); + } + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + TI_DBG1(("satStartStopUnitCB: momory allocation fails\n")); + return; + } /* end of memory allocation failure */ + + /* + * Need to initialize all the fields within satIOContext + */ + + satNewIOContext = satPrepareNewIO( + satNewIntIo, + tiOrgIORequest, + satDevData, + scsiCmnd, + satOrgIOContext + ); + + /* sending SAT_STANDBY */ + status = satStartStopUnit_1( tiRoot, + &satNewIntIo->satIntTiIORequest, + satNewIOContext->ptiDeviceHandle, + &satNewIntIo->satIntTiScsiXchg, + satNewIOContext); + + if (status != tiSuccess) + { + /* sending SAT_CHECK_POWER_MODE fails */ + satFreeIntIoResource( tiRoot, + satDevData, + satNewIntIo); + + /* IMMED == 0 */ + if (!( scsiCmnd->cdb[1] & SCSI_IMMED_MASK)) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_COMMAND_SEQUENCE_ERROR, + satOrgIOContext); + } + else /* IMMED == 1 */ + { + satSetDeferredSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_COMMAND_SEQUENCE_ERROR, + satOrgIOContext); + } + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + TI_DBG1(("satStartStopUnitCB: calling satStartStopUnit_1 fails\n")); + return; + } + break; + case SAT_STANDBY: + TI_DBG5(("satStartStopUnitCB: SAT_STANDBY success case\n")); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + /* done with SAT_STANDBY */ + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + /* + if immed == 0, return good status + */ + /* IMMED == 0 */ + if (!( scsiCmnd->cdb[1] & SCSI_IMMED_MASK)) + { + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + } + satDevData->satStopState = agTRUE; + break; + case SAT_READ_VERIFY_SECTORS: /* fall through */ + case SAT_READ_VERIFY_SECTORS_EXT: + TI_DBG5(("satStartStopUnitCB: SAT_READ_VERIFY_SECTORS(_EXT) success case\n")); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + /* done with SAT_READ_VERIFY_SECTORS(_EXT) */ + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + /* + if immed == 0, return good status + */ + if (!( scsiCmnd->cdb[1] & SCSI_IMMED_MASK)) + { + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + } + /* + if immed == 0, return good status + */ + /* + don't forget to check and set driver state; Active power state + */ + satDevData->satStopState = agFALSE; + break; + case SAT_MEDIA_EJECT: + TI_DBG5(("satStartStopUnitCB: SAT_MEDIA_EJECT success case\n")); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + /* done with SAT_READ_VERIFY_SECTORS(_EXT) */ + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + /* + if immed == 0, return good status + */ + if (!( scsiCmnd->cdb[1] & SCSI_IMMED_MASK)) + { + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + } + break; + default: + TI_DBG1(("satStartStopUnitCB:success but error default case command 0x%x\n", hostToDevFis->h.command)); + + /* unspecified case, return no sense and no addition info */ + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + break; + } + return; +} + +/***************************************************************************** +*! \brief satSendDiagnosticCB +* +* This routine is a callback function called from ossaSATACompleted(). +* This CB routine deals with Send Diagnostic completion. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void satSendDiagnosticCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + /* + In the process of SendDiagnotic + Process READ VERIFY SECTOR(S) EXT two time + Process SMART ECECUTE OFF-LINE IMMEDIATE + */ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdIORequestBody; + tdIORequestBody_t *tdOrgIORequestBody; + satIOContext_t *satIOContext; + satIOContext_t *satOrgIOContext; + satIOContext_t *satNewIOContext; + satInternalIo_t *satIntIo; + satInternalIo_t *satNewIntIo = agNULL; + satDeviceData_t *satDevData; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + tiIORequest_t *tiOrgIORequest; + + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + bit32 status; + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + + + TI_DBG5(("satSendDiagnosticCB:agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate tiIOContext */ + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satIOContext = (satIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + satDevData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + + if (satIntIo == agNULL) + { + TI_DBG4(("satSendDiagnosticCB: External satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + tiOrgIORequest = tdIORequestBody->tiIORequest; + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + else + { + TI_DBG4(("satSendDiagnosticCB: Internal satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + TI_DBG4(("satSendDiagnosticCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + TI_DBG4(("satSendDiagnosticCB: satOrgIOContext is NOT NULL\n")); + } + tdOrgIORequestBody = (tdIORequestBody_t *)satOrgIOContext->tiRequestBody; + tiOrgIORequest = (tiIORequest_t *)tdOrgIORequestBody->tiIORequest; + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satSendDiagnosticCB: wrong. agFirstDword is NULL when error, status %d\n", agIOStatus)); + satDevData->satVerifyState = 0; + satDevData->satBGPendingDiag = agFALSE; + + if (hostToDevFis->d.lbaLow != 0x01 && hostToDevFis->d.lbaLow != 0x02) + { + /* no completion for background send diagnotic. It is done in satSendDiagnostic() */ + ostiInitiatorIOCompleted ( + tiRoot, + tiOrgIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + } + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + + } + + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* only agsaFisRegDeviceToHost_t is expected */ + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + } + + TI_DBG5(("satSendDiagnosticCB: fis command 0x%x\n", hostToDevFis->h.command)); + + if( agIOStatus != OSSA_IO_SUCCESS) + { + /* + checking IO status, FIS type and error status + */ + satDevData->satVerifyState = 0; + satDevData->satBGPendingDiag = agFALSE; + + if( (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) || + ((ataStatus & ERR_ATA_STATUS_MASK) || (ataStatus & DF_ATA_STATUS_MASK)) + ) + { + + /* for debugging */ + if( agIOStatus != OSSA_IO_SUCCESS) + { + if ( (hostToDevFis->h.command == SAT_SMART_RETURN_STATUS) || + (hostToDevFis->h.command == SAT_READ_VERIFY_SECTORS_EXT) ) + { + TI_DBG1(("satSendDiagnosticCB: FAILED, NOT IO_SUCCESS and SAT_READ_VERIFY_SECTORS(_EXT)\n")); + } + else + { + TI_DBG1(("satSendDiagnosticCB: FAILED, NOT IO_SUCCESS and SAT_SMART_EXEUTE_OFF_LINE_IMMEDIATE\n")); + } + } + + /* for debugging */ + if( statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) + { + if ( (hostToDevFis->h.command == SAT_SMART_RETURN_STATUS) || + (hostToDevFis->h.command == SAT_READ_VERIFY_SECTORS_EXT) ) + { + TI_DBG1(("satSendDiagnosticCB: FAILED, Wrong FIS type 0x%x and SAT_READ_VERIFY_SECTORS(_EXT)\n", statDevToHostFisHeader->fisType)); + } + else + { + TI_DBG1(("satSendDiagnosticCB: FAILED, Wrong FIS type 0x%x and SAT_SMART_EXEUTE_OFF_LINE_IMMEDIATE\n",statDevToHostFisHeader->fisType)); + } + } + + /* for debugging */ + if ( (ataStatus & ERR_ATA_STATUS_MASK) || + (ataStatus & DF_ATA_STATUS_MASK) + ) + { + if ( (hostToDevFis->h.command == SAT_SMART_RETURN_STATUS) || + (hostToDevFis->h.command == SAT_READ_VERIFY_SECTORS_EXT) ) + { + TI_DBG1(("satSendDiagnosticCB: FAILED, error status and SAT_READ_VERIFY_SECTORS(_EXT)\n")); + } + else + { + TI_DBG1(("satSendDiagnosticCB: FAILED, error status and SAT_SMART_EXEUTE_OFF_LINE_IMMEDIATE\n")); + } + } + + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + satProcessAbort(tiRoot, + tiOrgIORequest, + satOrgIOContext + ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + if ( (hostToDevFis->h.command == SAT_READ_VERIFY_SECTORS) || + (hostToDevFis->h.command == SAT_READ_VERIFY_SECTORS_EXT) ) + { + /* report using the original tiIOrequst */ + /* failed during sending SAT_READ_VERIFY_SECTORS(_EXT) */ + satSetSensePayload( pSense, + SCSI_SNSKEY_HARDWARE_ERROR, + 0, + SCSI_SNSCODE_LOGICAL_UNIT_FAILED_SELF_TEST, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + else + { + /* report using the original tiIOrequst */ + /* failed during sending SAT_SMART_EXEUTE_OFF_LINE_IMMEDIATE */ + satSetSensePayload( pSense, + SCSI_SNSKEY_HARDWARE_ERROR, + 0, + SCSI_SNSCODE_LOGICAL_UNIT_FAILED_SELF_TEST, + satOrgIOContext); + + if (hostToDevFis->d.lbaLow != 0x01 && hostToDevFis->d.lbaLow != 0x02) + { + /* no completion for background send diagnotic. It is done in satSendDiagnostic() */ + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + } + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + } + } + + /* processing success case */ + switch (hostToDevFis->h.command) + { + case SAT_READ_VERIFY_SECTORS: /* fall through */ + case SAT_READ_VERIFY_SECTORS_EXT: + TI_DBG5(("satSendDiagnosticCB: SAT_READ_VERIFY_SECTORS(_EXT) case\n")); + tdsaSingleThreadedEnter(tiRoot, TD_SATA_LOCK); + satDevData->satVerifyState++; + tdsaSingleThreadedLeave(tiRoot, TD_SATA_LOCK); + TI_DBG5(("satSendDiagnosticCB: satVerifyState %d\n",satDevData->satVerifyState)); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + /* done with internally genereated AT_READ_VERIFY_SECTORS(_EXT) */ + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + if (satDevData->satVerifyState == 3) + { + /* reset satVerifyState */ + satDevData->satVerifyState = 0; + /* return GOOD status */ + TI_DBG5(("satSendDiagnosticCB: return GOOD status\n")); + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + return; + } + else + { + + /* prepare SAT_READ_VERIFY_SECTORS(_EXT) */ + satNewIntIo = satAllocIntIoResource( tiRoot, + tiOrgIORequest, + satDevData, + 0, + satNewIntIo); + if (satNewIntIo == agNULL) + { + /* reset satVerifyState */ + satDevData->satVerifyState = 0; + /* memory allocation failure */ + satFreeIntIoResource( tiRoot, + satDevData, + satNewIntIo); + + /* failed as a part of sending SAT_READ_VERIFY_SECTORS(_EXT) */ + satSetSensePayload( pSense, + SCSI_SNSKEY_HARDWARE_ERROR, + 0, + SCSI_SNSCODE_LOGICAL_UNIT_FAILED_SELF_TEST, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + TI_DBG1(("satSendDiagnosticCB: momory allocation fails\n")); + return; + } /* end of memory allocation failure */ + + /* + * Need to initialize all the fields within satIOContext + */ + + satNewIOContext = satPrepareNewIO( + satNewIntIo, + tiOrgIORequest, + satDevData, + scsiCmnd, + satOrgIOContext + ); + + if (satDevData->satVerifyState == 1) + { + /* sending SAT_CHECK_POWER_MODE */ + status = satSendDiagnostic_1( tiRoot, + &satNewIntIo->satIntTiIORequest, + satNewIOContext->ptiDeviceHandle, + &satNewIntIo->satIntTiScsiXchg, + satNewIOContext); + } + else + { + /* satDevData->satVerifyState == 2 */ + status = satSendDiagnostic_2( tiRoot, + &satNewIntIo->satIntTiIORequest, + satNewIOContext->ptiDeviceHandle, + &satNewIntIo->satIntTiScsiXchg, + satNewIOContext); + } + + if (status != tiSuccess) + { + /* sending SAT_READ_VERIFY_SECTORS(_EXT) fails */ + satFreeIntIoResource( tiRoot, + satDevData, + satNewIntIo); + + /* failed during sending SAT_READ_VERIFY_SECTORS(_EXT) */ + satSetSensePayload( pSense, + SCSI_SNSKEY_HARDWARE_ERROR, + 0, + SCSI_SNSCODE_LOGICAL_UNIT_FAILED_SELF_TEST, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + /* reset satVerifyState */ + satDevData->satVerifyState = 0; + TI_DBG1(("satSendDiagnosticCB: calling satSendDiagnostic_1 or _2 fails\n")); + return; + } + } /* satDevData->satVerifyState == 1 or 2 */ + + break; + case SAT_SMART_EXEUTE_OFF_LINE_IMMEDIATE: + TI_DBG5(("satSendDiagnosticCB: SAT_SMART_EXEUTE_OFF_LINE_IMMEDIATE case\n")); + + satDevData->satBGPendingDiag = agFALSE; + + if (hostToDevFis->d.lbaLow == 0x01 || hostToDevFis->d.lbaLow == 0x02) + { + /* for background send diagnostic, no completion here. It is done already. */ + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + /* done with AT_SMART_EXEUTE_OFF_LINE_IMMEDIATE */ + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + TI_DBG5(("satSendDiagnosticCB: returning but no IOCompleted\n")); + } + else + { + TI_DBG5(("satSendDiagnosticCB: returning good status for senddiagnostic\n")); + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + /* done with AT_SMART_EXEUTE_OFF_LINE_IMMEDIATE */ + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + } + + break; + default: + TI_DBG1(("satSendDiagnosticCB: success but error default case command 0x%x\n", hostToDevFis->h.command)); + /* unspecified case, return no sense and no addition info */ + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + break; + } + return; +} +/***************************************************************************** +*! \brief satRequestSenseCB +* +* This routine is a callback function called from ossaSATACompleted(). +* This CB routine deals with Request Sense completion. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +/* + CB for internnaly generated SMART_RETURN_STATUS and SAT_CHECK_POWER_MODE + in the process of RequestSense + +*/ +void satRequestSenseCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + /* ATA Vol 1, p299 SAT_SMART_RETURN_STATUS */ + /* + if threshold exceeds, return SCSI_SNSCODE_HARDWARE_IMPENDING_FAILURE + else call satRequestSense_1 to send CHECK_POWER_MODE + */ + + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdIORequestBody; + tdIORequestBody_t *tdOrgIORequestBody; + satIOContext_t *satIOContext; + satIOContext_t *satOrgIOContext; + satIOContext_t *satNewIOContext; + satInternalIo_t *satIntIo; + satInternalIo_t *satNewIntIo = agNULL; + satDeviceData_t *satDevData; + scsiRspSense_t *pSense; + tiIORequest_t *tiOrgIORequest; + tiIniScsiCmnd_t *scsiCmnd; + + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + bit32 status; + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + agsaFisRegD2HData_t statDevToHostFisData; + bit32 lenReceived = 0; + bit32 dataLength; + + TI_DBG4(("satRequestSenseCB:agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate tiIOContext */ + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satIOContext = (satIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + satDevData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + + /*ttttttthe one */ + if (satIntIo == agNULL) + { + TI_DBG4(("satRequestSenseCB: External satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + tiOrgIORequest = tdIORequestBody->tiIORequest; + if (satOrgIOContext->superIOFlag) + { + pSense = (scsiRspSense_t *)(((tiSuperScsiInitiatorRequest_t *)satOrgIOContext->tiScsiXchg)->sglVirtualAddr);//satOrgIOContext->pSense; + } + else + { + pSense = (scsiRspSense_t *)(((tiScsiInitiatorRequest_t *) satOrgIOContext->tiScsiXchg)->sglVirtualAddr);//satOrgIOContext->pSense; + } + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + else + { + TI_DBG4(("satRequestSenseCB: Internal satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + TI_DBG4(("satRequestSenseCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + TI_DBG4(("satRequestSenseCB: satOrgIOContext is NOT NULL\n")); + } + tdOrgIORequestBody = (tdIORequestBody_t *)satOrgIOContext->tiRequestBody; + tiOrgIORequest = (tiIORequest_t *)tdOrgIORequestBody->tiIORequest; + + if (satOrgIOContext->superIOFlag) + { + pSense = (scsiRspSense_t *)(((tiSuperScsiInitiatorRequest_t *)satOrgIOContext->tiScsiXchg)->sglVirtualAddr);//satOrgIOContext->pSense; + } + else + { + pSense = (scsiRspSense_t *)(((tiScsiInitiatorRequest_t *) satOrgIOContext->tiScsiXchg)->sglVirtualAddr);//satOrgIOContext->pSense; + } + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + TI_DBG4(("satRequestSenseCB: fis command 0x%x\n", hostToDevFis->h.command)); + + lenReceived = scsiCmnd->cdb[4]; + TI_DBG1(("satRequestSenseCB: lenReceived in CDB %d 0x%x\n", lenReceived,lenReceived)); + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satRequestSenseCB: wrong. agFirstDword is NULL when error, status %d\n", agIOStatus)); + ostiInitiatorIOCompleted ( + tiRoot, + tiOrgIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + return; + } + + /* + checking IO status, FIS type and error status + */ + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* only agsaFisRegDeviceToHost_t is expected */ + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + + /* for debugging */ + if( statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) + { + if (hostToDevFis->h.command == SAT_SMART_RETURN_STATUS) + { + TI_DBG1(("satRequestSenseCB: FAILED, Wrong FIS type 0x%x and SAT_SMART_RETURN_STATU\n", statDevToHostFisHeader->fisType)); + } + else + { + TI_DBG1(("satRequestSenseCB: FAILED, Wrong FIS type 0x%x and SAT_CHECK_POWER_MODE\n",statDevToHostFisHeader->fisType)); + } + } + + /* for debugging */ + if ( (ataStatus & ERR_ATA_STATUS_MASK) || + (ataStatus & DF_ATA_STATUS_MASK) + ) + { + if (hostToDevFis->h.command == SAT_SMART_RETURN_STATUS) + { + TI_DBG1(("satRequestSenseCB: FAILED, error status and SAT_SMART_RETURN_STATU\n")); + } + else + { + TI_DBG1(("satRequestSenseCB: FAILED, error status and SAT_CHECK_POWER_MODE\n")); + } + } + + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + satProcessAbort(tiRoot, + tiOrgIORequest, + satOrgIOContext + ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + if (hostToDevFis->h.command == SAT_SMART_RETURN_STATUS) + { + /* report using the original tiIOrequst */ + /* failed during sending SMART RETURN STATUS */ + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_HARDWARE_IMPENDING_FAILURE, + satOrgIOContext); + + if (SENSE_DATA_LENGTH < lenReceived) + { + /* underrun */ + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == satIntIo->satOrgTiIORequest */ + tiIOUnderRun, + lenReceived - SENSE_DATA_LENGTH, + agNULL, + satOrgIOContext->interruptContext ); + } + else + { + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + } + } + else + { + /* report using the original tiIOrequst */ + /* failed during sending SAT_CHECK_POWER_MODE */ + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_LOW_POWER_CONDITION_ON, + satOrgIOContext); + + if (SENSE_DATA_LENGTH < lenReceived) + { + /* underrun */ + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == satIntIo->satOrgTiIORequest */ + tiIOUnderRun, + lenReceived - SENSE_DATA_LENGTH, + agNULL, + satOrgIOContext->interruptContext ); + } + else + { + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + } + } + + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + saFrameReadBlock(agRoot, agParam, 0, &statDevToHostFisData, sizeof(agsaFisRegD2HData_t)); + + switch (hostToDevFis->h.command) + { + case SAT_SMART_RETURN_STATUS: + TI_DBG4(("satRequestSenseCB: SAT_SMART_RETURN_STATUS case\n")); + if (statDevToHostFisData.lbaMid == 0xF4 || statDevToHostFisData.lbaHigh == 0x2C) + { + /* threshold exceeds */ + TI_DBG1(("satRequestSenseCB: threshold exceeds\n")); + + + /* report using the original tiIOrequst */ + /* failed during sending SMART RETURN STATUS */ + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_HARDWARE_IMPENDING_FAILURE, + satOrgIOContext); + + if (SENSE_DATA_LENGTH < lenReceived) + { + /* underrun */ + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOUnderRun, + lenReceived - SENSE_DATA_LENGTH, + agNULL, + satOrgIOContext->interruptContext ); } + else + { + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); } + + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + /* done with internally genereated SAT_SMART_RETURN_STATUS */ + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + /* at this point, successful SMART_RETURN_STATUS + xmit SAT_CHECK_POWER_MODE + */ + if (satOrgIOContext->superIOFlag) + { + dataLength = ((tiSuperScsiInitiatorRequest_t *) satOrgIOContext->tiScsiXchg)->scsiCmnd.expDataLength; + } + else + { + dataLength = ((tiScsiInitiatorRequest_t *) satOrgIOContext->tiScsiXchg)->scsiCmnd.expDataLength; + } + + satNewIntIo = satAllocIntIoResource( tiRoot, + tiOrgIORequest, + satDevData, + dataLength, + satNewIntIo); + if (satNewIntIo == agNULL) + { + /* memory allocation failure */ + satFreeIntIoResource( tiRoot, + satDevData, + satNewIntIo); + + /* failed as a part of sending SMART RETURN STATUS */ + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_HARDWARE_IMPENDING_FAILURE, + satOrgIOContext); + + if (SENSE_DATA_LENGTH < lenReceived) + { + /* underrun */ + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, + tiIOUnderRun, + lenReceived - SENSE_DATA_LENGTH, + agNULL, + satOrgIOContext->interruptContext ); + } + else + { + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + } + + TI_DBG1(("satRequestSenseCB: momory allocation fails\n")); + return; + } /* end of memory allocation failure */ + + + /* + * Need to initialize all the fields within satIOContext + */ + + satNewIOContext = satPrepareNewIO( + satNewIntIo, + tiOrgIORequest, + satDevData, + scsiCmnd, + satOrgIOContext + ); + + /* sending SAT_CHECK_POWER_MODE */ + status = satRequestSense_1( tiRoot, + &satNewIntIo->satIntTiIORequest, + satNewIOContext->ptiDeviceHandle, + &satNewIntIo->satIntTiScsiXchg, + satNewIOContext); + + if (status != tiSuccess) + { + /* sending SAT_CHECK_POWER_MODE fails */ + satFreeIntIoResource( tiRoot, + satDevData, + satNewIntIo); + + /* failed during sending SAT_CHECK_POWER_MODE */ + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_LOW_POWER_CONDITION_ON, + satOrgIOContext); + + if (SENSE_DATA_LENGTH < lenReceived) + { + /* underrun */ + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, + tiIOUnderRun, + lenReceived - SENSE_DATA_LENGTH, + agNULL, + satOrgIOContext->interruptContext ); + } + else + { + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + } + + TI_DBG1(("satRequestSenseCB: calling satRequestSense_1 fails\n")); + return; + } + + break; + case SAT_CHECK_POWER_MODE: + TI_DBG4(("satRequestSenseCB: SAT_CHECK_POWER_MODE case\n")); + + /* check ATA STANDBY state */ + if (statDevToHostFisData.sectorCount == 0x00) + { + /* in STANDBY */ + TI_DBG1(("satRequestSenseCB: in standby\n")); + + + /* report using the original tiIOrequst */ + /* failed during sending SAT_CHECK_POWER_MODE */ + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_LOW_POWER_CONDITION_ON, + satOrgIOContext); + + if (SENSE_DATA_LENGTH < lenReceived) + { + /* underrun */ + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOUnderRun, + lenReceived - SENSE_DATA_LENGTH, + agNULL, + satOrgIOContext->interruptContext ); + } + else + { + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + } + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + /* done with internnaly generated SAT_CHECK_POWER_MODE */ + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + if (satDevData->satFormatState == agTRUE) + { + TI_DBG1(("satRequestSenseCB: in format\n")); + + + /* report using the original tiIOrequst */ + satSetSensePayload( pSense, + SCSI_SNSKEY_NOT_READY, + 0, + SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_FORMAT_IN_PROGRESS, + satOrgIOContext); + + if (SENSE_DATA_LENGTH < lenReceived) + { + /* underrun */ + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOUnderRun, + lenReceived - SENSE_DATA_LENGTH, + agNULL, + satOrgIOContext->interruptContext ); + } + else + { + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + } + + return; + } + + /* normal: returns good status for requestsense */ + /* report using the original tiIOrequst */ + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + TI_DBG4(("satRequestSenseCB: returning good status for requestsense\n")); + if (SENSE_DATA_LENGTH < lenReceived) + { + /* underrun */ + TI_DBG6(("satRequestSenseCB reporting underrun lenNeeded=0x%x lenReceived=0x%x tiIORequest=%p\n", + SENSE_DATA_LENGTH, lenReceived, tiOrgIORequest)); + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOUnderRun, + lenReceived - SENSE_DATA_LENGTH, + agNULL, + satOrgIOContext->interruptContext ); + + } + else + { + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + } + + break; + default: + TI_DBG1(("satRequestSenseCB: success but error default case command 0x%x\n", hostToDevFis->h.command)); + /* pSense here is a part of satOrgIOContext */ + pSense = satOrgIOContext->pTiSenseData->senseData; + satOrgIOContext->pTiSenseData->senseLen = SENSE_DATA_LENGTH; + /* unspecified case, return no sense and no addition info */ + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + break; + } /* switch */ + + return; +} + +/***************************************************************************** +*! \brief satSynchronizeCache10n16CB +* +* This routine is a callback function for satSynchronizeCache10 and +* satSynchronizeCache1016() +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void satSynchronizeCache10n16CB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdIORequestBody; + tdIORequestBody_t *tdOrgIORequestBody; + satIOContext_t *satIOContext; + satIOContext_t *satOrgIOContext; + satInternalIo_t *satIntIo; + satDeviceData_t *satDevData; + + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + tiIORequest_t *tiOrgIORequest; + + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + + TI_DBG5(("satSynchronizeCache10n16CB:agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate tiIOContext */ + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satIOContext = (satIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + satDevData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + + /* SPC: Self-Test Result Log page */ + + if (satIntIo == agNULL) + { + TI_DBG4(("satSynchronizeCache10n16CB: External satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + tiOrgIORequest = tdIORequestBody->tiIORequest; + pSense = satIOContext->pSense; + scsiCmnd = satIOContext->pScsiCmnd; + } + else + { + TI_DBG4(("satSynchronizeCache10n16CB: Internal satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + TI_DBG4(("satSynchronizeCache10n16CB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + TI_DBG4(("satSynchronizeCache10n16CB: satOrgIOContext is NOT NULL\n")); + } + tdOrgIORequestBody = (tdIORequestBody_t *)satOrgIOContext->tiRequestBody; + tiOrgIORequest = (tiIORequest_t *)tdOrgIORequestBody->tiIORequest; + + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satSynchronizeCache10n16CB: wrong. agFirstDword is NULL when error, status %d\n", agIOStatus)); + + ostiInitiatorIOCompleted ( + tiRoot, + tiOrgIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + if( agIOStatus != OSSA_IO_SUCCESS) + { + /* only agsaFisRegDeviceToHost_t is expected */ + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + } + + if( agIOStatus != OSSA_IO_SUCCESS) + { + if ( (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) || + ((ataStatus & ERR_ATA_STATUS_MASK) || (ataStatus & DF_ATA_STATUS_MASK)) + ) + { + /* for debugging */ + if( agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satSynchronizeCache10n16CB: FAILED, NOT IO_SUCCESS\n")); + } + else if (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) + { + TI_DBG1(("satSynchronizeCache10n16CB: FAILED, Wrong FIS type 0x%x\n",statDevToHostFisHeader->fisType)); + } + else if ( (ataStatus & ERR_ATA_STATUS_MASK) || + (ataStatus & DF_ATA_STATUS_MASK) + ) + { + TI_DBG1(("satSynchronizeCache10n16CB: FAILED, FAILED, error status\n")); + } + + + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + satProcessAbort(tiRoot, + tiOrgIORequest, + satOrgIOContext + ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + switch (hostToDevFis->h.command) + { + case SAT_FLUSH_CACHE: + TI_DBG1(("satSynchronizeCache10n16CB: SAT_FLUSH_CACHE failed\n")); + /* checking IMMED bit */ + if (scsiCmnd->cdb[1] & SCSI_FLUSH_CACHE_IMMED_MASK) + { + satSetDeferredSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + } + else + { + satSetDeferredSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + } + + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + break; + case SAT_FLUSH_CACHE_EXT: + TI_DBG1(("satSynchronizeCache10n16CB: SAT_FLUSH_CACHE_EXT failed\n")); + /* checking IMMED bit */ + if (scsiCmnd->cdb[1] & SCSI_FLUSH_CACHE_IMMED_MASK) + { + satSetDeferredSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + } + else + { + satSetDeferredSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + } + + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + break; + default: + TI_DBG1(("satSynchronizeCache10n16CB: error unknown command 0x%x\n", hostToDevFis->h.command)); + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + break; + } + + return; + } /* end of error checking */ + } + + /* prcessing the success case */ + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + + switch (hostToDevFis->h.command) + { + case SAT_FLUSH_CACHE: + TI_DBG5(("satSynchronizeCache10n16CB: SAT_FLUSH_CACHE success\n")); + + /* checking IMMED bit */ + if ( !(scsiCmnd->cdb[1] & SCSI_FLUSH_CACHE_IMMED_MASK)) + { + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + return; + } + + + break; + case SAT_FLUSH_CACHE_EXT: + TI_DBG5(("satSynchronizeCache10n16CB: SAT_FLUSH_CACHE_EXT success\n")); + + /* checking IMMED bit */ + if ( !(scsiCmnd->cdb[1] & SCSI_FLUSH_CACHE_IMMED_MASK)) + { + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + return; + } + + break; + default: + TI_DBG5(("satSynchronizeCache10n16CB: error unknown command 0x%x\n", hostToDevFis->h.command)); + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + return; + break; + } + + return; +} + +/***************************************************************************** +*! \brief satModeSelect6n10CB +* +* This routine is a callback function for satModeSelect6() and +* satModeSelect10() +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void satModeSelect6n10CB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdIORequestBody; + tdIORequestBody_t *tdOrgIORequestBody; + satIOContext_t *satIOContext; + satIOContext_t *satOrgIOContext; + satIOContext_t *satNewIOContext; + satInternalIo_t *satIntIo; + satInternalIo_t *satNewIntIo = agNULL; + satDeviceData_t *satDevData; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + tiIORequest_t *tiOrgIORequest; + + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + bit32 status; + tiScsiInitiatorRequest_t *tiScsiRequest; /* tiScsiXchg */ + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + + TI_DBG5(("satModeSelect6n10CB: agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate tiIOContext */ + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satIOContext = (satIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + satDevData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + + if (satIntIo == agNULL) + { + TI_DBG4(("satModeSelect6n10CB: External satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + tiOrgIORequest = tdIORequestBody->tiIORequest; + tiScsiRequest = satOrgIOContext->tiScsiXchg; + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + else + { + TI_DBG4(("satModeSelect6n10CB: Internal satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + TI_DBG4(("satModeSelect6n10CB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + TI_DBG4(("satModeSelect6n10CB: satOrgIOContext is NOT NULL\n")); + } + tdOrgIORequestBody = (tdIORequestBody_t *)satOrgIOContext->tiRequestBody; + tiOrgIORequest = (tiIORequest_t *)tdOrgIORequestBody->tiIORequest; + + tiScsiRequest = satOrgIOContext->tiScsiXchg; + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satModeSelect6n10CB: wrong. agFirstDword is NULL when error, status %d\n", agIOStatus)); + ostiInitiatorIOCompleted ( + tiRoot, + tiOrgIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* only agsaFisRegDeviceToHost_t is expected */ + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + } + + if (agIOStatus != OSSA_IO_SUCCESS) + { + if ( (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) || + ((ataStatus & ERR_ATA_STATUS_MASK) || (ataStatus & DF_ATA_STATUS_MASK)) + ) + { + /* for debugging */ + if( agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satModeSelect6n10CB FAILED, NOT IO_SUCCESS\n")); + } + else if (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) + { + TI_DBG1(("satModeSelect6n10CB FAILED, Wrong FIS type 0x%x\n",statDevToHostFisHeader->fisType)); + } + else if ( (ataStatus & ERR_ATA_STATUS_MASK) || + (ataStatus & DF_ATA_STATUS_MASK) + ) + { + TI_DBG1(("satModeSelect6n10CB FAILED, FAILED, error status\n")); + } + + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + satProcessAbort(tiRoot, + tiOrgIORequest, + satOrgIOContext + ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + /* for debugging */ + if (hostToDevFis->h.command == SAT_SET_FEATURES) + { + if ((hostToDevFis->h.features == 0x82) || (hostToDevFis->h.features == 0x02)) + { + TI_DBG1(("satModeSelect6n10CB 1 SAT_SET_FEATURES failed, feature 0x%x\n", hostToDevFis->h.features)); + } + else if ((hostToDevFis->h.features == 0xAA) || (hostToDevFis->h.features == 0x55)) + { + TI_DBG1(("ssatModeSelect6n10CB 2 SAT_SET_FEATURES failed, feature 0x%x\n", hostToDevFis->h.features)); + } + else + { + TI_DBG1(("satModeSelect6n10CB error unknown command 0x%x feature 0x%x\n", hostToDevFis->h.command, hostToDevFis->h.features)); + } + } + else if (hostToDevFis->h.command == SAT_SMART) + { + if ((hostToDevFis->h.features == SAT_SMART_ENABLE_OPERATIONS) || (hostToDevFis->h.features == SAT_SMART_DISABLE_OPERATIONS)) + { + TI_DBG1(("satModeSelect6n10CB SAT_SMART_ENABLE/DISABLE_OPERATIONS failed, feature 0x%x\n", hostToDevFis->h.features)); + } + else + { + TI_DBG1(("satModeSelect6n10CB error unknown command 0x%x feature 0x%x\n", hostToDevFis->h.command, hostToDevFis->h.features)); + } + } + else + { + TI_DBG1(("satModeSelect6n10CB error default case command 0x%x\n", hostToDevFis->h.command)); + } + + + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } /* error checking */ + } + + + /* prcessing the success case */ + + + if (hostToDevFis->h.command == SAT_SET_FEATURES) + { + if ((hostToDevFis->h.features == 0x82) || (hostToDevFis->h.features == 0x02)) + { + TI_DBG5(("satModeSelect6n10CB 1 SAT_SET_FEATURES success, feature 0x%x\n", hostToDevFis->h.features)); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + satNewIntIo = satAllocIntIoResource( tiRoot, + tiOrgIORequest, + satDevData, + 0, + satNewIntIo); + if (satNewIntIo == agNULL) + { + /* memory allocation failure */ + satFreeIntIoResource( tiRoot, + satDevData, + satNewIntIo); + + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + TI_DBG1(("satModeSelect6n10CB: momory allocation fails\n")); + return; + } /* end memory allocation */ + + satNewIOContext = satPrepareNewIO( + satNewIntIo, + tiOrgIORequest, + satDevData, + scsiCmnd, + satOrgIOContext + ); + /* sends either ATA SET FEATURES based on DRA bit */ + status = satModeSelect6n10_1( tiRoot, + &satNewIntIo->satIntTiIORequest, + satNewIOContext->ptiDeviceHandle, + tiScsiRequest, /* orginal from OS layer */ + satNewIOContext + ); + + if (status != tiSuccess) + { + /* sending ATA command fails */ + satFreeIntIoResource( tiRoot, + satDevData, + satNewIntIo); + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + TI_DBG1(("satModeSelect6n10CB calling satModeSelect6_1 fails\n")); + return; + } /* end send fails */ + return; + } + else if ((hostToDevFis->h.features == 0xAA) || (hostToDevFis->h.features == 0x55)) + { + TI_DBG5(("satModeSelect6n10CB 2 SAT_SET_FEATURES success, feature 0x%x\n", hostToDevFis->h.features)); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + /* return stat_good */ + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + return; + } + else + { + TI_DBG1(("satModeSelect6n10CB error unknown command success 0x%x feature 0x%x\n", hostToDevFis->h.command, hostToDevFis->h.features)); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + return; + } + } + else if (hostToDevFis->h.command == SAT_SMART_ENABLE_OPERATIONS || + hostToDevFis->h.command == SAT_SMART_DISABLE_OPERATIONS + ) + { + if ((hostToDevFis->h.features == 0xD8) || (hostToDevFis->h.features == 0xD9)) + { + TI_DBG5(("satModeSelect6n10CB SAT_SMART_ENABLE/DISABLE_OPERATIONS success, feature 0x%x\n", hostToDevFis->h.features)); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + /* return stat_good */ + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + return; + } + else + { + TI_DBG1(("satModeSelect6n10CB error unknown command failed 0x%x feature 0x%x\n", hostToDevFis->h.command, hostToDevFis->h.features)); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + return; + } + } + + else + { + TI_DBG1(("satModeSelect6n10CB error default case command success 0x%x\n", hostToDevFis->h.command)); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + return; + } + + return; +} + +/***************************************************************************** +*! \brief satSMARTEnableCB +* +* This routine is a callback function for satSMARTEnable() +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void satSMARTEnableCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdIORequestBody; + tdIORequestBody_t *tdOrgIORequestBody; + satIOContext_t *satIOContext; + satIOContext_t *satOrgIOContext; + satIOContext_t *satNewIOContext; + satInternalIo_t *satIntIo; + satInternalIo_t *satNewIntIo = agNULL; + satDeviceData_t *satDevData; + tiIORequest_t *tiOrgIORequest; + tiIniScsiCmnd_t *scsiCmnd; + bit32 status; + + TI_DBG4(("satSMARTEnableCB:agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate tiIOContext */ + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satIOContext = (satIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + satDevData = satIOContext->pSatDevData; + + /*ttttttthe one */ + if (satIntIo == agNULL) + { + TI_DBG4(("satSMARTEnableCB: External satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + tiOrgIORequest = tdIORequestBody->tiIORequest; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + else + { + TI_DBG4(("satSMARTEnableCB: Internal satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + TI_DBG4(("satSMARTEnableCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + TI_DBG4(("satSMARTEnableCB: satOrgIOContext is NOT NULL\n")); + } + tdOrgIORequestBody = (tdIORequestBody_t *)satOrgIOContext->tiRequestBody; + tiOrgIORequest = (tiIORequest_t *)tdOrgIORequestBody->tiIORequest; + + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satSMARTEnableCB: wrong. agFirstDword is NULL when error, status %d\n", agIOStatus)); + ostiInitiatorIOCompleted ( + tiRoot, + tiOrgIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + return; + } + + /* + checking IO status, FIS type and error status + */ + if (agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satSMARTEnableCB: not success status, status %d\n", agIOStatus)); + ostiInitiatorIOCompleted ( + tiRoot, + tiOrgIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + return; + } + + /* process success case */ + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + satNewIntIo = satAllocIntIoResource( tiRoot, + tiOrgIORequest, + satDevData, + 512, + satNewIntIo); + + if (satNewIntIo == agNULL) + { + /* memory allocation failure */ + satFreeIntIoResource( tiRoot, + satDevData, + satNewIntIo); + + ostiInitiatorIOCompleted ( + tiRoot, + tiOrgIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + return; + } + + satNewIOContext = satPrepareNewIO( + satNewIntIo, + tiOrgIORequest, + satDevData, + scsiCmnd, + satOrgIOContext + ); + + status = satLogSense_1(tiRoot, + &satNewIntIo->satIntTiIORequest, + satNewIOContext->ptiDeviceHandle, + &satNewIntIo->satIntTiScsiXchg, + satNewIOContext); + + if (status != tiSuccess) + { + /* sending SAT_CHECK_POWER_MODE fails */ + satFreeIntIoResource( tiRoot, + satDevData, + satNewIntIo); + + ostiInitiatorIOCompleted ( + tiRoot, + tiOrgIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + + return; + } + + return; +} + + +/***************************************************************************** +*! \brief satLogSenseCB +* +* This routine is a callback function for satLogSense() +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void satLogSenseCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdIORequestBody; + tdIORequestBody_t *tdOrgIORequestBody; + satIOContext_t *satIOContext; + satIOContext_t *satOrgIOContext; + satInternalIo_t *satIntIo; + satDeviceData_t *satDevData; + + scsiRspSense_t *pSense; + tiIORequest_t *tiOrgIORequest; + + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + tiScsiInitiatorRequest_t *tiScsiRequest; /* tiScsiXchg */ + tiScsiInitiatorRequest_t *tiOrgScsiRequest; /* tiScsiXchg */ + satReadLogExtSelfTest_t *virtAddr1; + satSmartReadLogSelfTest_t *virtAddr2; + bit8 *pLogPage; + bit8 SelfTestExecutionStatus = 0; + bit32 i = 0; + + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + agsaFisRegD2HData_t statDevToHostFisData; + tiIniScsiCmnd_t *scsiCmnd; + bit32 lenReceived = 0; + + TI_DBG5(("satLogSenseCB:agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate tiIOContext */ + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satIOContext = (satIOContext_t *) ioContext; + if (satIOContext == agNULL) + { + TI_DBG1(("satLogSenseCB: satIOContext is NULL\n")); + return; + } + satIntIo = satIOContext->satIntIoContext; + satDevData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + + if (satIntIo == agNULL) + { + TI_DBG4(("satLogSenseCB: External satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + tiOrgIORequest = tdIORequestBody->tiIORequest; + pSense = satOrgIOContext->pSense; + tiOrgScsiRequest = satOrgIOContext->tiScsiXchg; + /* SCSI command response payload to OS layer */ + pLogPage = (bit8 *) tiOrgScsiRequest->sglVirtualAddr; + /* ATA command response payload */ + tiScsiRequest = satOrgIOContext->tiScsiXchg; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + else + { + TI_DBG4(("satLogSenseCB: Internal satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + TI_DBG4(("satLogSenseCB: satOrgIOContext is NULL\n")); + } + else + { + TI_DBG4(("satLogSenseCB: satOrgIOContext is NOT NULL\n")); + } + + tdOrgIORequestBody = (tdIORequestBody_t *)satOrgIOContext->tiRequestBody; + tiOrgIORequest = (tiIORequest_t *)tdOrgIORequestBody->tiIORequest; + + pSense = satOrgIOContext->pSense; + tiOrgScsiRequest = satOrgIOContext->tiScsiXchg; + /* SCSI command response payload to OS layer */ + pLogPage = (bit8 *) tiOrgScsiRequest->sglVirtualAddr; + /* ATA command response payload */ + tiScsiRequest = (tiScsiInitiatorRequest_t *)&(satIntIo->satIntTiScsiXchg); + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satLogSenseCB: wrong. agFirstDword is NULL when error, status %d\n", agIOStatus)); + ostiInitiatorIOCompleted ( + tiRoot, + tiOrgIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* non-data and pio read -> device to host and pio setup fis are expected */ + /* + first, assumed to be Reg Device to Host FIS + This is OK to just find fis type + */ + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + } + + if( agIOStatus != OSSA_IO_SUCCESS) + { + if ( ((statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) && + (statDevToHostFisHeader->fisType != PIO_SETUP_DEV_TO_HOST_FIS)) || + ((ataStatus & ERR_ATA_STATUS_MASK) || (ataStatus & DF_ATA_STATUS_MASK)) + ) + { + /* for debugging */ + if( agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satLogSenseCB: FAILED, NOT IO_SUCCESS\n")); + } + else if (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) + { + TI_DBG1(("satLogSenseCB: FAILED, Wrong FIS type 0x%x\n",statDevToHostFisHeader->fisType)); + } + else if (statDevToHostFisHeader->fisType != PIO_SETUP_DEV_TO_HOST_FIS) + { + TI_DBG1(("satLogSenseCB: FAILED, Wrong FIS type 0x%x\n",statDevToHostFisHeader->fisType)); + } + else if ( (ataStatus & ERR_ATA_STATUS_MASK) || + (ataStatus & DF_ATA_STATUS_MASK) + ) + { + TI_DBG1(("satLogSenseCB: FAILED, FAILED, error status\n")); + } + + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + satProcessAbort(tiRoot, + tiOrgIORequest, + satOrgIOContext + ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + /* for debugging */ + if (hostToDevFis->h.command == SAT_READ_LOG_EXT) + { + TI_DBG1(("satLogSenseCB: SAT_READ_LOG_EXT failed\n")); + } + else if (hostToDevFis->h.command == SAT_SMART) + { + if (hostToDevFis->h.features == SAT_SMART_READ_LOG) + { + TI_DBG1(("satLogSenseCB: SAT_SMART_READ_LOG failed\n")); + } + else if (hostToDevFis->h.features == SAT_SMART_RETURN_STATUS) + { + TI_DBG1(("satLogSenseCB: SAT_SMART_RETURN_STATUS failed\n")); + } + else + { + TI_DBG1(("satLogSenseCB: error unknown command 0x%x feature 0x%x\n", hostToDevFis->h.command, hostToDevFis->h.features)); + } + } + else + { + TI_DBG1(("satLogSenseCB: error default case command 0x%x\n", hostToDevFis->h.command)); + } + + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + + } /* error checking */ + } + + /* prcessing the success case */ + saFrameReadBlock(agRoot, agParam, 0, &statDevToHostFisData, sizeof(agsaFisRegD2HData_t)); + + lenReceived = (scsiCmnd->cdb[7] << 8) + scsiCmnd->cdb[8]; + TI_DBG5(("satLogSenseCB: lenReceived in CDB %d 0x%x\n", lenReceived,lenReceived)); + + + if (hostToDevFis->h.command == SAT_READ_LOG_EXT) + { + TI_DBG5(("satLogSenseCB: SAT_READ_LOG_EXT success\n")); + + /* process log data and sends it to upper */ + + /* ATA: Extended Self-Test Log */ + virtAddr1 = (satReadLogExtSelfTest_t *)(tiScsiRequest->sglVirtualAddr); + /* + ATA/ATAPI VOLII, p197, 287 + self-test execution status (4 bits); ((virtAddr1->byte[5] & 0xF0) >> 4) + */ + SelfTestExecutionStatus = (bit8)(((virtAddr1->byte[5] & 0xF0) >> 4)); + + /* fills in the log page from ATA log page */ + /* SPC-4, 7.2.10, Table 216, 217, p 259 - 260 */ + pLogPage[0] = 0x10; /* page code */ + pLogPage[1] = 0; + pLogPage[2] = 0x01; /* 0x190, page length */ + pLogPage[3] = 0x90; + + /* SPC-4, Table 217 */ + pLogPage[4] = 0; /* Parameter Code */ + pLogPage[5] = 0x01; /* Parameter Code, unspecfied but ... */ + pLogPage[6] = 3; /* unspecified but ... */ + pLogPage[7] = 0x10; /* Parameter Length */ + pLogPage[8] = (bit8)(0 | ((virtAddr1->byte[5] & 0xF0) >> 4)); /* Self Test Code and Self-Test Result */ + pLogPage[9] = 0; /* self test number */ + pLogPage[10] = virtAddr1->byte[7]; /* time stamp, MSB */ + pLogPage[11] = virtAddr1->byte[6]; /* time stamp, LSB */ + + pLogPage[12] = 0; /* address of first failure MSB*/ + pLogPage[13] = 0; /* address of first failure */ + pLogPage[14] = virtAddr1->byte[14]; /* address of first failure */ + pLogPage[15] = virtAddr1->byte[13]; /* address of first failure */ + pLogPage[16] = virtAddr1->byte[12]; /* address of first failure */ + pLogPage[17] = virtAddr1->byte[11]; /* address of first failure */ + pLogPage[18] = virtAddr1->byte[10]; /* address of first failure */ + pLogPage[19] = virtAddr1->byte[9]; /* address of first failure LSB */ + + /* SAT rev8 Table75, p 76 */ + switch (SelfTestExecutionStatus) + { + case 0: + pLogPage[20] = 0 | SCSI_SNSKEY_NO_SENSE; + pLogPage[21] = (SCSI_SNSCODE_NO_ADDITIONAL_INFO >> 8) & 0xFF; + pLogPage[22] = SCSI_SNSCODE_NO_ADDITIONAL_INFO & 0xFF; + break; + case 1: + pLogPage[20] = 0 | SCSI_SNSKEY_ABORTED_COMMAND; + pLogPage[21] = (SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN >> 8) & 0xFF; + pLogPage[22] = 0x81; + break; + case 2: + pLogPage[20] = 0 | SCSI_SNSKEY_ABORTED_COMMAND; + pLogPage[21] = (SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN >> 8) & 0xFF; + pLogPage[22] = 0x82; + break; + case 3: + pLogPage[20] = 0 | SCSI_SNSKEY_ABORTED_COMMAND; + pLogPage[21] = (SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN >> 8) & 0xFF; + pLogPage[22] = 0x83; + break; + case 4: + pLogPage[20] = 0 | SCSI_SNSKEY_HARDWARE_ERROR; + pLogPage[21] = (SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN >> 8) & 0xFF; + pLogPage[22] = 0x84; + break; + case 5: + pLogPage[20] = 0 | SCSI_SNSKEY_HARDWARE_ERROR; + pLogPage[21] = (SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN >> 8) & 0xFF; + pLogPage[22] = 0x85; + break; + case 6: + pLogPage[20] = 0 | SCSI_SNSKEY_HARDWARE_ERROR; + pLogPage[21] = (SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN >> 8) & 0xFF; + pLogPage[22] = 0x86; + break; + case 7: + pLogPage[20] = 0 | SCSI_SNSKEY_MEDIUM_ERROR; + pLogPage[21] = (SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN >> 8) & 0xFF; + pLogPage[22] = 0x87; + break; + case 8: + pLogPage[20] = 0 | SCSI_SNSKEY_HARDWARE_ERROR; + pLogPage[21] = (SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN >> 8) & 0xFF; + pLogPage[22] = 0x88; + break; + case 9: /* fall through */ + case 10:/* fall through */ + case 11:/* fall through */ + case 12:/* fall through */ + case 13:/* fall through */ + case 14: + pLogPage[20] = 0 | SCSI_SNSKEY_NO_SENSE; + pLogPage[21] = (SCSI_SNSCODE_NO_ADDITIONAL_INFO >> 8) & 0xFF; + pLogPage[22] = SCSI_SNSCODE_NO_ADDITIONAL_INFO & 0xFF; + break; + case 15: + pLogPage[20] = 0 | SCSI_SNSKEY_NO_SENSE; + pLogPage[21] = (SCSI_SNSCODE_NO_ADDITIONAL_INFO >> 8) & 0xFF; + pLogPage[22] = SCSI_SNSCODE_NO_ADDITIONAL_INFO & 0xFF; + break; + default: + TI_DBG1(("satLogSenseCB: Error, incorrect SelfTestExecutionStatus 0x%x\n", SelfTestExecutionStatus)); + + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + return; + } + + pLogPage[23] = 0; /* vendor specific */ + + /* the rest of Self-test results log */ + /* 403 is from SPC-4, 7.2.10, Table 216, p 259*/ + for (i=24;i<=403;i++) + { + pLogPage[i] = 0; /* vendor specific */ + } + + if (SELFTEST_RESULTS_LOG_PAGE_LENGTH < lenReceived) + { + TI_DBG6(("satLogSenseCB: 1st underrun lenReceived %d len %d \n", lenReceived, SELFTEST_RESULTS_LOG_PAGE_LENGTH)); + + /* underrun */ + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == satIntIo->satOrgTiIORequest */ + tiIOUnderRun, + lenReceived - SELFTEST_RESULTS_LOG_PAGE_LENGTH, + agNULL, + satOrgIOContext->interruptContext ); + + } + else + { + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext); + } + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + return; + } + else if (hostToDevFis->h.command == SAT_SMART_READ_LOG + || hostToDevFis->h.command == SAT_SMART_RETURN_STATUS) + { + if (hostToDevFis->h.features == 0xd5) + { + TI_DBG5(("satLogSenseCB: SAT_SMART_READ_LOG success\n")); + /* process log data and sends it to upper */ + + /* ATA: Extended Self-Test Log */ + virtAddr2 = (satSmartReadLogSelfTest_t *)(tiScsiRequest->sglVirtualAddr); + /* + SPC-4, p197, 287 + self-test execution status (4 bits); ((virtAddr2->byte[3] & 0xF0) >> 4) + */ + SelfTestExecutionStatus = (bit8)(((virtAddr2->byte[3] & 0xF0) >> 4)); + + /* fills in the log page from ATA log page */ + /* SPC-4, 7.2.10, Table 216, 217, p 259 - 260 */ + pLogPage[0] = 0x10; /* page code */ + pLogPage[1] = 0; + pLogPage[2] = 0x01; /* 0x190, page length */ + pLogPage[3] = 0x90; /* 0x190, page length */ + + /* SPC-4, Table 217 */ + pLogPage[4] = 0; /* Parameter Code */ + pLogPage[5] = 0x01; /* Parameter Code unspecfied but ... */ + pLogPage[6] = 3; /* unspecified but ... */ + pLogPage[7] = 0x10; /* Parameter Length */ + pLogPage[8] = (bit8)(0 | ((virtAddr2->byte[3] & 0xF0) >> 4)); /* Self Test Code and Self-Test Result */ + pLogPage[9] = 0; /* self test number */ + pLogPage[10] = virtAddr2->byte[5]; /* time stamp, MSB */ + pLogPage[11] = virtAddr2->byte[4]; /* time stamp, LSB */ + + pLogPage[12] = 0; /* address of first failure MSB*/ + pLogPage[13] = 0; /* address of first failure */ + pLogPage[14] = 0; /* address of first failure */ + pLogPage[15] = 0; /* address of first failure */ + pLogPage[16] = virtAddr2->byte[10]; /* address of first failure */ + pLogPage[17] = virtAddr2->byte[9]; /* address of first failure */ + pLogPage[18] = virtAddr2->byte[8]; /* address of first failure */ + pLogPage[19] = virtAddr2->byte[7]; /* address of first failure LSB */ + + /* SAT rev8 Table75, p 76 */ + switch (SelfTestExecutionStatus) + { + case 0: + pLogPage[20] = 0 | SCSI_SNSKEY_NO_SENSE; + pLogPage[21] = (SCSI_SNSCODE_NO_ADDITIONAL_INFO >> 8) & 0xFF; + pLogPage[22] = SCSI_SNSCODE_NO_ADDITIONAL_INFO & 0xFF; + break; + case 1: + pLogPage[20] = 0 | SCSI_SNSKEY_ABORTED_COMMAND; + pLogPage[21] = (SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN >> 8) & 0xFF; + pLogPage[22] = 0x81; + break; + case 2: + pLogPage[20] = 0 | SCSI_SNSKEY_ABORTED_COMMAND; + pLogPage[21] = (SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN >> 8) & 0xFF; + pLogPage[22] = 0x82; + break; + case 3: + pLogPage[20] = 0 | SCSI_SNSKEY_ABORTED_COMMAND; + pLogPage[21] = (SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN >> 8) & 0xFF; + pLogPage[22] = 0x83; + break; + case 4: + pLogPage[20] = 0 | SCSI_SNSKEY_HARDWARE_ERROR; + pLogPage[21] = (SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN >> 8) & 0xFF; + pLogPage[22] = 0x84; + break; + case 5: + pLogPage[20] = 0 | SCSI_SNSKEY_HARDWARE_ERROR; + pLogPage[21] = (SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN >> 8) & 0xFF; + pLogPage[22] = 0x85; + break; + case 6: + pLogPage[20] = 0 | SCSI_SNSKEY_HARDWARE_ERROR; + pLogPage[21] = (SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN >> 8) & 0xFF; + pLogPage[22] = 0x86; + break; + case 7: + pLogPage[20] = 0 | SCSI_SNSKEY_MEDIUM_ERROR; + pLogPage[21] = (SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN >> 8) & 0xFF; + pLogPage[22] = 0x87; + break; + case 8: + pLogPage[20] = 0 | SCSI_SNSKEY_HARDWARE_ERROR; + pLogPage[21] = (SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN >> 8) & 0xFF; + pLogPage[22] = 0x88; + break; + case 9: /* fall through */ + case 10:/* fall through */ + case 11:/* fall through */ + case 12:/* fall through */ + case 13:/* fall through */ + case 14: + /* unspecified */ + pLogPage[20] = 0 | SCSI_SNSKEY_NO_SENSE; + pLogPage[21] = (SCSI_SNSCODE_NO_ADDITIONAL_INFO >> 8) & 0xFF; + pLogPage[22] = SCSI_SNSCODE_NO_ADDITIONAL_INFO & 0xFF; + break; + case 15: + pLogPage[20] = 0 | SCSI_SNSKEY_NO_SENSE; + pLogPage[21] = (SCSI_SNSCODE_NO_ADDITIONAL_INFO >> 8) & 0xFF; + pLogPage[22] = SCSI_SNSCODE_NO_ADDITIONAL_INFO & 0xFF; + break; + default: + TI_DBG1(("satLogSenseCB: Error, incorrect SelfTestExecutionStatus 0x%x\n", SelfTestExecutionStatus)); + + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + return; + } + + pLogPage[23] = 0; /* vendor specific */ + + /* the rest of Self-test results log */ + /* 403 is from SPC-4, 7.2.10, Table 216, p 259*/ + for (i=24;i<=403;i++) + { + pLogPage[i] = 0; /* vendor specific */ + } + + if (SELFTEST_RESULTS_LOG_PAGE_LENGTH < lenReceived) + { + TI_DBG6(("satLogSenseCB: 2nd underrun lenReceived %d len %d \n", lenReceived, SELFTEST_RESULTS_LOG_PAGE_LENGTH)); + + /* underrun */ + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == satIntIo->satOrgTiIORequest */ + tiIOUnderRun, + lenReceived - SELFTEST_RESULTS_LOG_PAGE_LENGTH, + agNULL, + satOrgIOContext->interruptContext ); + + } + else + { + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext); + } + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + return; + } + else if (hostToDevFis->h.features == 0xda) + { + TI_DBG5(("satLogSenseCB: SAT_SMART_RETURN_STATUS success\n")); + + /* fills in the log page from ATA output */ + /* SPC-4, 7.2.5, Table 209, 211, p 255 */ + pLogPage[0] = 0x2F; /* page code unspecified */ + pLogPage[1] = 0; /* reserved */ + pLogPage[2] = 0; /* page length */ + pLogPage[3] = 0x07; /* page length */ + + /* + SPC-4, 7.2.5, Table 211, p 255 + no vendor specific field + */ + pLogPage[4] = 0; /* Parameter Code */ + pLogPage[5] = 0; /* Parameter Code unspecfied but to do: */ + pLogPage[6] = 0; /* unspecified */ + pLogPage[7] = 0x03; /* Parameter length, unspecified */ + + /* SAT rev8, 10.2.3.1 Table 72, p 73 */ + if (statDevToHostFisData.lbaMid == 0x4F || statDevToHostFisData.lbaHigh == 0xC2) + { + pLogPage[8] = 0; /* Sense code */ + pLogPage[9] = 0; /* Sense code qualifier */ + } + else if (statDevToHostFisData.lbaMid == 0xF4 || statDevToHostFisData.lbaHigh == 0x2C) + { + pLogPage[8] = 0x5D; /* Sense code */ + pLogPage[9] = 0x10; /* Sense code qualifier */ + } + + /* Assumption: No support for SCT */ + pLogPage[10] = 0xFF; /* Most Recent Temperature Reading */ + + if (INFORMATION_EXCEPTIONS_LOG_PAGE_LENGTH < lenReceived) + { + TI_DBG6(("satLogSenseCB: 3rd underrun lenReceived %d len %d \n", lenReceived, INFORMATION_EXCEPTIONS_LOG_PAGE_LENGTH)); + + /* underrun */ + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == satIntIo->satOrgTiIORequest */ + tiIOUnderRun, + lenReceived - INFORMATION_EXCEPTIONS_LOG_PAGE_LENGTH, + agNULL, + satOrgIOContext->interruptContext ); + + } + else + { + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext); + } + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + + return; + } + else + { + TI_DBG1(("satLogSenseCB: error unknown command success 0x%x feature 0x%x\n", hostToDevFis->h.command, hostToDevFis->h.features)); + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + return; + } + } + else + { + TI_DBG1(("satLogSenseCB: error unknown command success 0x%x\n", hostToDevFis->h.command)); + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + return; + } + + return; +} + +/***************************************************************************** +*! \brief satReadMediaSerialNumberCB +* +* This routine is a callback function called from ossaSATACompleted(). +* This CB routine deals with Read Media Serial Number completion. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agSATAParm1: Additional info based on status. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void satReadMediaSerialNumberCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdIORequestBody; + tdIORequestBody_t *tdOrgIORequestBody; + satIOContext_t *satIOContext; + satIOContext_t *satOrgIOContext; + satInternalIo_t *satIntIo; + satDeviceData_t *satDevData; + + scsiRspSense_t *pSense; + tiIORequest_t *tiOrgIORequest; + + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + tiScsiInitiatorRequest_t *tiOrgScsiRequest; /* tiScsiXchg */ + bit8 *pMediaSerialNumber; + + tiIniScsiCmnd_t *scsiCmnd; + bit32 lenReceived = 0; + + TI_DBG4(("satReadMediaSerialNumberCB:agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate tiIOContext */ + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satIOContext = (satIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + satDevData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + + if (satIntIo == agNULL) + { + TI_DBG4(("satReadMediaSerialNumberCB: External satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + tiOrgIORequest = tdIORequestBody->tiIORequest; + pSense = satOrgIOContext->pSense; + tiOrgScsiRequest = satOrgIOContext->tiScsiXchg; + /* SCSI command response payload to OS layer */ + pMediaSerialNumber = (bit8 *) tiOrgScsiRequest->sglVirtualAddr; + /* ATA command response payload */ + scsiCmnd = satOrgIOContext->pScsiCmnd; + + + } + else + { + TI_DBG4(("satReadMediaSerialNumberCB: Internal satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + TI_DBG4(("satReadMediaSerialNumberCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + TI_DBG4(("satReadMediaSerialNumberCB: satOrgIOContext is NOT NULL\n")); + } + tdOrgIORequestBody = (tdIORequestBody_t *)satOrgIOContext->tiRequestBody; + tiOrgIORequest = (tiIORequest_t *)tdOrgIORequestBody->tiIORequest; + + pSense = satOrgIOContext->pSense; + tiOrgScsiRequest = satOrgIOContext->tiScsiXchg; + /* SCSI command response payload to OS layer */ + pMediaSerialNumber = (bit8 *) tiOrgScsiRequest->sglVirtualAddr; + /* ATA command response payload */ + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satReadMediaSerialNumberCB: wrong. agFirstDword is NULL when error, status %d\n", agIOStatus)); + ostiInitiatorIOCompleted ( + tiRoot, + tiOrgIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + if( agIOStatus != OSSA_IO_SUCCESS) + { + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + satProcessAbort(tiRoot, + tiOrgIORequest, + satOrgIOContext + ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + satSetSensePayload( pSense, + SCSI_SNSKEY_NOT_READY, + 0, + SCSI_SNSCODE_MEDIUM_NOT_PRESENT, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + /* process success case */ + lenReceived = (scsiCmnd->cdb[6] << (8*3)) + (scsiCmnd->cdb[7] << (8*2)) + + (scsiCmnd->cdb[8] << 8) + scsiCmnd->cdb[9]; + TI_DBG5(("satReadMediaSerialNumberCB: lenReceived in CDB %d 0x%x\n", lenReceived,lenReceived)); + + if (hostToDevFis->h.command == SAT_READ_SECTORS || + hostToDevFis->h.command == SAT_READ_SECTORS_EXT + ) + { + pMediaSerialNumber[0] = 0; + pMediaSerialNumber[1] = 0; + pMediaSerialNumber[2] = 0; + pMediaSerialNumber[3] = 4; + pMediaSerialNumber[4] = 0; + pMediaSerialNumber[5] = 0; + pMediaSerialNumber[6] = 0; + pMediaSerialNumber[7] = 0; + + if (ZERO_MEDIA_SERIAL_NUMBER_LENGTH < lenReceived) + { + TI_DBG1(("satReadMediaSerialNumberCB: 1st underrun lenReceived %d len %d \n", lenReceived, ZERO_MEDIA_SERIAL_NUMBER_LENGTH)); + + /* underrun */ + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == satIntIo->satOrgTiIORequest */ + tiIOUnderRun, + lenReceived - ZERO_MEDIA_SERIAL_NUMBER_LENGTH, + agNULL, + satOrgIOContext->interruptContext ); + + } + else + { + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext); + } + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + else + { + TI_DBG1(("satReadMediaSerialNumberCB: error unknown command success 0x%x\n", hostToDevFis->h.command)); + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + return; + } + return; +} + +/***************************************************************************** +*! \brief satReadBufferCB +* +* This routine is a callback function called from ossaSATACompleted(). +* This CB routine deals with Read Buffer. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agSATAParm1: Additional info based on status. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void satReadBufferCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdIORequestBody; + tdIORequestBody_t *tdOrgIORequestBody; + satIOContext_t *satIOContext; + satIOContext_t *satOrgIOContext; + satInternalIo_t *satIntIo; + satDeviceData_t *satDevData; + scsiRspSense_t *pSense; + tiIORequest_t *tiOrgIORequest; + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + + TI_DBG4(("satReadBufferCB:agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate tiIOContext */ + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satIOContext = (satIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + satDevData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + + + if (satIntIo == agNULL) + { + TI_DBG4(("satReadBufferCB: External satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + tiOrgIORequest = tdIORequestBody->tiIORequest; + pSense = satOrgIOContext->pSense; + + /* SCSI command response payload to OS layer */ + + /* ATA command response payload */ + + } + else + { + TI_DBG4(("satReadBufferCB: Internal satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + TI_DBG4(("satReadBufferCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + TI_DBG4(("satReadBufferCB: satOrgIOContext is NOT NULL\n")); + } + tdOrgIORequestBody = (tdIORequestBody_t *)satOrgIOContext->tiRequestBody; + tiOrgIORequest = (tiIORequest_t *)tdOrgIORequestBody->tiIORequest; + + pSense = satOrgIOContext->pSense; + + /* SCSI command response payload to OS layer */ + + /* ATA command response payload */ + + } + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satReadBufferCB: wrong. agFirstDword is NULL when error, status %d\n", agIOStatus)); + ostiInitiatorIOCompleted ( + tiRoot, + tiOrgIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + if( agIOStatus != OSSA_IO_SUCCESS) + { + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + satProcessAbort(tiRoot, + tiOrgIORequest, + satOrgIOContext + ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + satSetSensePayload( pSense, + SCSI_SNSKEY_NOT_READY, + 0, + SCSI_SNSCODE_MEDIUM_NOT_PRESENT, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + /* process success case */ + if (hostToDevFis->h.command == SAT_READ_BUFFER ) + { + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext); + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + else + { + TI_DBG1(("satReadBufferCB: error unknown command success 0x%x\n", hostToDevFis->h.command)); + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + return; + } + + return; +} + +/***************************************************************************** +*! \brief satWriteBufferCB +* +* This routine is a callback function called from ossaSATACompleted(). +* This CB routine deals with Write Buffer. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agSATAParm1: Additional info based on status. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void satWriteBufferCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdIORequestBody; + tdIORequestBody_t *tdOrgIORequestBody; + satIOContext_t *satIOContext; + satIOContext_t *satOrgIOContext; + satInternalIo_t *satIntIo; + satDeviceData_t *satDevData; + scsiRspSense_t *pSense; + tiIORequest_t *tiOrgIORequest; + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + + TI_DBG4(("satWriteBufferCB:agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate tiIOContext */ + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satIOContext = (satIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + satDevData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + + + if (satIntIo == agNULL) + { + TI_DBG4(("satWriteBufferCB: External satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + tiOrgIORequest = tdIORequestBody->tiIORequest; + pSense = satOrgIOContext->pSense; + /* SCSI command response payload to OS layer */ + + /* ATA command response payload */ + + } + else + { + TI_DBG4(("satWriteBufferCB: Internal satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + TI_DBG4(("satWriteBufferCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + TI_DBG4(("satWriteBufferCB: satOrgIOContext is NOT NULL\n")); + } + tdOrgIORequestBody = (tdIORequestBody_t *)satOrgIOContext->tiRequestBody; + tiOrgIORequest = (tiIORequest_t *)tdOrgIORequestBody->tiIORequest; + + pSense = satOrgIOContext->pSense; + /* SCSI command response payload to OS layer */ + + /* ATA command response payload */ + + } + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satWriteBufferCB: wrong. agFirstDword is NULL when error, status %d\n", agIOStatus)); + ostiInitiatorIOCompleted ( + tiRoot, + tiOrgIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + if( agIOStatus != OSSA_IO_SUCCESS) + { + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + satProcessAbort(tiRoot, + tiOrgIORequest, + satOrgIOContext + ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + satSetSensePayload( pSense, + SCSI_SNSKEY_NOT_READY, + 0, + SCSI_SNSCODE_MEDIUM_NOT_PRESENT, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + /* process success case */ + if (hostToDevFis->h.command == SAT_WRITE_BUFFER ) + { + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext); + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + else + { + TI_DBG1(("satWriteBufferCB: error unknown command success 0x%x\n", hostToDevFis->h.command)); + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + return; + } + + return; +} + +/***************************************************************************** +*! \brief satReassignBlocksCB +* +* This routine is a callback function called from ossaSATACompleted(). +* This CB routine deals with Reassign Blocks. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agSATAParm1: Additional info based on status. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void satReassignBlocksCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdIORequestBody; + tdIORequestBody_t *tdOrgIORequestBody; + satIOContext_t *satIOContext; + satIOContext_t *satOrgIOContext; + satIOContext_t *satNewIOContext; + satInternalIo_t *satIntIo; + satInternalIo_t *satNewIntIo = agNULL; + satDeviceData_t *satDevData; + + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + tiIORequest_t *tiOrgIORequest; + + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + bit32 status; + tiScsiInitiatorRequest_t *tiScsiRequest; /* tiScsiXchg */ + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + + TI_DBG5(("satReassignBlocksCB: agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + /* internally generate tiIOContext */ + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satIOContext = (satIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + satDevData = satIOContext->pSatDevData; + hostToDevFis = satIOContext->pFis; + + if (satIntIo == agNULL) + { + TI_DBG4(("satReassignBlocksCB: External satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext; + tiOrgIORequest = tdIORequestBody->tiIORequest; + tiScsiRequest = satOrgIOContext->tiScsiXchg; + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + else + { + TI_DBG4(("satReassignBlocksCB: Internal satInternalIo_t satIntIoContext\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + TI_DBG4(("satReassignBlocksCB: satOrgIOContext is NULL, Wrong\n")); + return; + } + else + { + TI_DBG4(("satReassignBlocksCB: satOrgIOContext is NOT NULL, Wrong\n")); + } + tdOrgIORequestBody = (tdIORequestBody_t *)satOrgIOContext->tiRequestBody; + tiOrgIORequest = (tiIORequest_t *)tdOrgIORequestBody->tiIORequest; + + tiScsiRequest = satOrgIOContext->tiScsiXchg; + pSense = satOrgIOContext->pSense; + scsiCmnd = satOrgIOContext->pScsiCmnd; + } + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satReassignBlocksCB: wrong. agFirstDword is NULL when error, status %d\n", agIOStatus)); + ostiInitiatorIOCompleted ( + tiRoot, + tiOrgIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + satOrgIOContext->interruptContext + ); + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + if (agIOStatus != OSSA_IO_SUCCESS) + { + /* only agsaFisRegDeviceToHost_t is expected */ + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + } + + if (agIOStatus != OSSA_IO_SUCCESS) + { + if ( (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) || + ((ataStatus & ERR_ATA_STATUS_MASK) || (ataStatus & DF_ATA_STATUS_MASK)) + ) + { + /* for debugging */ + if( agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satReassignBlocksCB FAILED, NOT IO_SUCCESS\n")); + } + else if (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) + { + TI_DBG1(("satReassignBlocksCB FAILED, Wrong FIS type 0x%x\n",statDevToHostFisHeader->fisType)); + } + else if ( (ataStatus & ERR_ATA_STATUS_MASK) || + (ataStatus & DF_ATA_STATUS_MASK) + ) + { + TI_DBG1(("satReassignBlocksCB FAILED, FAILED, error status\n")); + } + + /* Process abort case */ + if (agIOStatus == OSSA_IO_ABORTED) + { + satProcessAbort(tiRoot, + tiOrgIORequest, + satOrgIOContext + ); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + /* for debugging */ + if (hostToDevFis->h.command == SAT_READ_VERIFY_SECTORS || + hostToDevFis->h.command == SAT_READ_VERIFY_SECTORS_EXT + ) + { + TI_DBG1(("satReassignBlocksCB SAT_READ_VERIFY_SECTORS(_EXT) failed\n")); + /* Verify failed; send Write with same LBA */ + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + satNewIntIo = satAllocIntIoResource( tiRoot, + tiOrgIORequest, + satDevData, + 512, /* writing 1 sector */ + satNewIntIo); + if (satNewIntIo == agNULL) + { + /* memory allocation failure */ + satFreeIntIoResource( tiRoot, + satDevData, + satNewIntIo); + + satSetSensePayload( pSense, + SCSI_SNSKEY_HARDWARE_ERROR, + 0, + SCSI_SNSCODE_WRITE_ERROR_AUTO_REALLOCATION_FAILED, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + TI_DBG1(("satReassignBlocksCB: momory allocation fails\n")); + return; + } /* end memory allocation */ + + satNewIOContext = satPrepareNewIO( + satNewIntIo, + tiOrgIORequest, + satDevData, + scsiCmnd, + satOrgIOContext + ); + + /* send Write with same LBA */ + status = satReassignBlocks_2( + tiRoot, + &satNewIntIo->satIntTiIORequest, + satNewIOContext->ptiDeviceHandle, + &satNewIntIo->satIntTiScsiXchg, + satNewIOContext, + satOrgIOContext->LBA + ); + + if (status != tiSuccess) + { + /* sending ATA command fails */ + satFreeIntIoResource( tiRoot, + satDevData, + satNewIntIo); + satSetSensePayload( pSense, + SCSI_SNSKEY_HARDWARE_ERROR, + 0, + SCSI_SNSCODE_WRITE_ERROR_AUTO_REALLOCATION_FAILED, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + TI_DBG1(("satReassignBlocksCB calling fail 1\n")); + return; + } /* end send fails */ + + return; + } + else if (hostToDevFis->h.command == SAT_WRITE_DMA || + hostToDevFis->h.command == SAT_WRITE_SECTORS || + hostToDevFis->h.command == SAT_WRITE_DMA_EXT || + hostToDevFis->h.command == SAT_WRITE_SECTORS_EXT || + hostToDevFis->h.command == SAT_WRITE_FPDMA_QUEUED + ) + { + TI_DBG1(("satReassignBlocksCB SAT_WRITE failed\n")); + /* fall through */ + } + else + { + TI_DBG1(("satReassignBlocksCB error default case unexpected command 0x%x\n", hostToDevFis->h.command)); + } + + + satSetSensePayload( pSense, + SCSI_SNSKEY_HARDWARE_ERROR, + 0, + SCSI_SNSCODE_WRITE_ERROR_AUTO_REALLOCATION_FAILED, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } /* error checking */ + } + + + /* prcessing the success case */ + if (hostToDevFis->h.command == SAT_READ_VERIFY_SECTORS || + hostToDevFis->h.command == SAT_READ_VERIFY_SECTORS_EXT || + hostToDevFis->h.command == SAT_WRITE_DMA || + hostToDevFis->h.command == SAT_WRITE_SECTORS || + hostToDevFis->h.command == SAT_WRITE_DMA_EXT || + hostToDevFis->h.command == SAT_WRITE_SECTORS_EXT || + hostToDevFis->h.command == SAT_WRITE_FPDMA_QUEUED + ) + { + /* next LBA; verify */ + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + if (satOrgIOContext->ParmIndex >= satOrgIOContext->ParmLen) + { + TI_DBG5(("satReassignBlocksCB: GOOD status\n")); + /* return stat_good */ + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satOrgIOContext->interruptContext ); + return; + } + else + { + TI_DBG5(("satReassignBlocksCB: processing next LBA\n")); + satNewIntIo = satAllocIntIoResource( tiRoot, + tiOrgIORequest, + satDevData, + 0, + satNewIntIo); + if (satNewIntIo == agNULL) + { + /* memory allocation failure */ + satFreeIntIoResource( tiRoot, + satDevData, + satNewIntIo); + + satSetSensePayload( pSense, + SCSI_SNSKEY_HARDWARE_ERROR, + 0, + SCSI_SNSCODE_WRITE_ERROR_AUTO_REALLOCATION_FAILED, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + TI_DBG1(("satReassignBlocksCB: momory allocation fails\n")); + return; + } /* end memory allocation */ + + satNewIOContext = satPrepareNewIO( + satNewIntIo, + tiOrgIORequest, + satDevData, + scsiCmnd, + satOrgIOContext + ); + + /* send Verify with the next LBA */ + status = satReassignBlocks_1( + tiRoot, + &satNewIntIo->satIntTiIORequest, + satNewIOContext->ptiDeviceHandle, + tiScsiRequest, /* orginal from OS layer */ + satNewIOContext, + satOrgIOContext + ); + + if (status != tiSuccess) + { + /* sending ATA command fails */ + satFreeIntIoResource( tiRoot, + satDevData, + satNewIntIo); + satSetSensePayload( pSense, + SCSI_SNSKEY_HARDWARE_ERROR, + 0, + SCSI_SNSCODE_WRITE_ERROR_AUTO_REALLOCATION_FAILED, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + TI_DBG1(("satReassignBlocksCB calling satModeSelect6_1 fails\n")); + return; + } /* end send fails */ + } /* else */ + return; + + } + else if (hostToDevFis->h.command == SAT_WRITE_DMA || + hostToDevFis->h.command == SAT_WRITE_SECTORS || + hostToDevFis->h.command == SAT_WRITE_DMA_EXT || + hostToDevFis->h.command == SAT_WRITE_SECTORS_EXT || + hostToDevFis->h.command == SAT_WRITE_FPDMA_QUEUED + ) + { + /* next LBA; verify */ + } + else + { + TI_DBG1(("satReassignBlocksCB error unknown command success 0x%x \n", hostToDevFis->h.command)); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + satSetSensePayload( pSense, + SCSI_SNSKEY_HARDWARE_ERROR, + 0, + SCSI_SNSCODE_WRITE_ERROR_AUTO_REALLOCATION_FAILED, + satOrgIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiOrgIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satOrgIOContext->pTiSenseData, + satOrgIOContext->interruptContext ); + return; + } + return; +} +/***************************************************************************** +*! \brief satReadLogExtCB +* +* This routine is a callback function called from ossaSATACompleted(). +* This CB routine deals READ LOG EXT completion. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +/* + SATAII spec p42 + +*/ +void satReadLogExtCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) + +{ + + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdIORequestBody; + satIOContext_t *satReadLogExtIOContext; + satInternalIo_t *satIntIo; + satDeviceData_t *satDevData; + tdsaDeviceData_t *tdsaDeviceData; + agsaIORequest_t *agAbortIORequest; + tdIORequestBody_t *tdAbortIORequestBody; + bit32 PhysUpper32; + bit32 PhysLower32; + bit32 memAllocStatus; + void *osMemHandle; + + TI_DBG1(("satReadLogExtCB: agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", + agIORequest, agIOStatus, agIOInfoLen)); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satReadLogExtIOContext = (satIOContext_t *) ioContext; + satIntIo = satReadLogExtIOContext->satIntIoContext; + satDevData = satReadLogExtIOContext->pSatDevData; + tdsaDeviceData = (tdsaDeviceData_t *)satDevData->satSaDeviceData; + + TI_DBG1(("satReadLogExtCB: did %d\n", tdsaDeviceData->id)); + satDecrementPendingIO(tiRoot, tdsaAllShared, satReadLogExtIOContext); + + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + /* + * If READ LOG EXT failed, we issue device reset. + */ + if ( agIOStatus != OSSA_IO_SUCCESS || + (agIOStatus == OSSA_IO_SUCCESS && agFirstDword != agNULL && agIOInfoLen != 0) + ) + { + TI_DBG1(("satReadLogExtCB: FAILED.\n")); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + /* Abort I/O after completion of device reset */ + satDevData->satAbortAfterReset = agTRUE; +#ifdef NOT_YET + /* needs to investigate this case */ + /* no report to OS layer */ + satSubTM(tiRoot, + satReadLogExtIOContext->ptiDeviceHandle, + TD_INTERNAL_TM_RESET, + agNULL, + agNULL, + agNULL, + agFALSE); +#endif + return; + } + + + /*************************************************************************** + * The following steps take place when READ LOG EXT successfully completed. + ***************************************************************************/ + + /************************************************************************ + * + * 1. Issue abort to LL layer to all other pending I/Os for the same SATA + * drive. + * + * 2. Free resource allocated for the internally generated READ LOG EXT. + * + * 3. At the completion of abort, in the context of ossaSATACompleted(), + * return the I/O with error status to the OS-App Specific layer. + * When all I/O aborts are completed, clear SATA device flag to + * indicate ready to process new request. + * + ***********************************************************************/ + + /* + * Issue abort to LL layer to all other pending I/Os for the same SATA drive + */ + /* + replace the single IO abort with device abort + */ + + TI_DBG1(("satReadLogExtCB: issuing saSATAAbort. Device Abort\n")); + /* do not deregister this device */ + tdsaDeviceData->OSAbortAll = agTRUE; + + /* allocating agIORequest for abort itself */ + memAllocStatus = ostiAllocMemory( + tiRoot, + &osMemHandle, + (void **)&tdAbortIORequestBody, + &PhysUpper32, + &PhysLower32, + 8, + sizeof(tdIORequestBody_t), + agTRUE + ); + + if (memAllocStatus != tiSuccess) + { + /* let os process IO */ + TI_DBG1(("satReadLogExtCB: ostiAllocMemory failed...\n")); + return; + } + + if (tdAbortIORequestBody == agNULL) + { + /* let os process IO */ + TI_DBG1(("satReadLogExtCB: ostiAllocMemory returned NULL tdAbortIORequestBody\n")); + return; + } + + /* setup task management structure */ + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle = osMemHandle; + tdAbortIORequestBody->tiDevHandle = (tiDeviceHandle_t *)&(tdsaDeviceData->tiDeviceHandle); + /* initialize agIORequest */ + agAbortIORequest = &(tdAbortIORequestBody->agIORequest); + agAbortIORequest->osData = (void *) tdAbortIORequestBody; + agAbortIORequest->sdkData = agNULL; /* LL takes care of this */ + + /* + * Issue abort + */ + saSATAAbort( agRoot, agAbortIORequest, 0, tdsaDeviceData->agDevHandle, 1, agNULL, agNULL); + + + /* + * Free resource allocated for the internally generated READ LOG EXT. + */ + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + /* + * Sequence of recovery continue at some other context: + * At the completion of abort, in the context of ossaSATACompleted(), + * return the I/O with error status to the OS-App Specific layer. + * When all I/O aborts are completed, clear SATA device flag to + * indicate ready to process new request. + */ + + satDevData->satDriveState = SAT_DEV_STATE_NORMAL; + + TI_DBG1(("satReadLogExtCB: end return\n")); + return; +} + +#ifndef FDS_SM +/***************************************************************************** +*! \brief ossaSATAEvent +* +* This routine is called to notify the OS Layer of an event associated with +* SATA port or SATA device +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agPortContext Pointer to the port context of TD and Lower layer +* \param agDevHandle: Pointer to a device handle +* \param event: event type +* +* \return: none +* +*****************************************************************************/ +osGLOBAL void ossaSATAEvent( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + agsaPortContext_t *agPortContext, + agsaDevHandle_t *agDevHandle, + bit32 event, + bit32 agIOInfoLen, + void *agParam + ) +{ + + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + bit32 interruptContext = osData->IntContext; + tdsaDeviceData_t *pDeviceData; + satDeviceData_t *pSatDevData; + satInternalIo_t *satIntIo = agNULL; + bit32 status; + satIOContext_t *satIOContext2; + tdIORequestBody_t *tdIORequestBody; + tiDeviceHandle_t *tiDeviceHandle; + tiIORequest_t tiIORequestTMP; + agsaDifDetails_t agDifDetails; + bit8 framePayload[256]; + bit16 frameOffset = 0; + bit16 frameLen = 0; + + /* new */ + tdsaDeviceData_t *tdsaDeviceData = agNULL; + satIOContext_t *satIOContext; + tdsaPortContext_t *onePortContext; + + if (event == OSSA_IO_XFER_ERROR_ABORTED_NCQ_MODE) + { + + /************************************************************************** + * + * !!!! See Section 13.5.2.4 of SATA 2.5 specs. !!!! + * !!!! If the NCQ error ends up here, it means that the device sent !!!! + * !!!! Register Device To Host FIS (which does not have SActive !!!! + * !!!! register) instead of Set Device Bit FIS (which has SActive !!!! + * !!!! register). The routine osSatIOCompleted() deals with the case !!!! + * !!!! where Set Device Bit FIS was sent by the device. !!!! + * + * For NCQ we need to issue READ LOG EXT command with log page 10h + * to get the error and to allow other I/Os to continue. + * + * Here is the basic flow or sequence of error recovery, this sequence is + * similar to the one described in SATA 2.5: + * + * 1. Set SATA device flag to indicate error condition and returning busy + * for all new request. + * + * 2. Prepare READ LOG EXT page 10h command. Set flag to indicate that + * the failed I/O has NOT been returned to the OS Layer. Send command. + * + * 3. When the device receives READ LOG EXT page 10h request all other + * pending I/O are implicitly aborted. No completion (aborted) status + * will be sent to the host for these aborted commands. + * + * 4. SATL receives the completion for READ LOG EXT command in + * satReadLogExtCB(). Steps 5,6,7,8 below are the step 1,2,3,4 in + * satReadLogExtCB(). + * + * 5. Check flag that indicates whether the failed I/O has been returned + * to the OS Layer. If not, search the I/O context in device data + * looking for a matched tag. Then return the completion of the failed + * NCQ command with the appopriate/trasnlated SCSI status. + * + * 6. Issue abort to LL layer to all other pending I/Os for the same SATA + * drive. + * + * 7. Free resource allocated for the internally generated READ LOG EXT. + * + * 8. At the completion of abort, in the context of ossaSATACompleted(), + * return the I/O with error status to the OS-App Specific layer. + * When all I/O aborts are completed, clear SATA device flag to + * indicate ready to process new request. + * + *************************************************************************/ + + pDeviceData = (tdsaDeviceData_t *) agDevHandle->osData; + pSatDevData = &pDeviceData->satDevData; + tiDeviceHandle = &((tdsaDeviceData_t *)(pSatDevData->satSaDeviceData))->tiDeviceHandle; + + TI_DBG1(("ossaSATAEvent: did %d\n", pDeviceData->id)); + + if (pSatDevData->satDriveState == SAT_DEV_STATE_NORMAL) + { + TI_DBG1(("ossaSATAEvent: NCQ ERROR agDevHandle=%p.\n", agDevHandle )); + + /* Set flag to indicate we are in recovery */ + pSatDevData->satDriveState = SAT_DEV_STATE_IN_RECOVERY; + + /* + * Allocate resource for READ LOG EXIT page 10h + */ + satIntIo = satAllocIntIoResource( tiRoot, + &(tiIORequestTMP), /* anything but NULL */ + pSatDevData, + sizeof (satReadLogExtPage10h_t), + satIntIo); + + /* + * If we cannot allocate resource to do the normal NCQ recovery, we + * will do SATA device reset. + */ + if (satIntIo == agNULL) + { + /* Abort I/O after completion of device reset */ + pSatDevData->satAbortAfterReset = agTRUE; + TI_DBG1(("ossaSATAEvent: can't send RLE due to resource lack\n")); + +#ifdef NOT_YET + /* needs to investigate this case */ + /* no report to OS layer */ + satSubTM(tiRoot, + tiDeviceHandle, + TD_INTERNAL_TM_RESET, + agNULL, + agNULL, + agNULL, + agFALSE); +#endif + + return; + } + + + /* + * Clear flag to indicate that the failed I/O has NOT been returned to the + * OS-App specific Layer. + */ + satIntIo->satIntFlag = 0; + + /* compare to satPrepareNewIO() */ + /* Send READ LOG EXIT page 10h command */ + + /* + * Need to initialize all the fields within satIOContext except + * reqType and satCompleteCB which will be set depending on cmd. + */ + + tdIORequestBody = (tdIORequestBody_t *)satIntIo->satIntRequestBody; + satIOContext2 = &(tdIORequestBody->transport.SATA.satIOContext); + + satIOContext2->pSatDevData = pSatDevData; + satIOContext2->pFis = &(tdIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev); + satIOContext2->pScsiCmnd = &(satIntIo->satIntTiScsiXchg.scsiCmnd); + satIOContext2->pSense = &(tdIORequestBody->transport.SATA.sensePayload); + satIOContext2->pTiSenseData = &(tdIORequestBody->transport.SATA.tiSenseData); + satIOContext2->pTiSenseData->senseData = satIOContext2->pSense; + + satIOContext2->tiRequestBody = satIntIo->satIntRequestBody; + satIOContext2->interruptContext = interruptContext; + satIOContext2->satIntIoContext = satIntIo; + + satIOContext2->ptiDeviceHandle = tiDeviceHandle; + satIOContext2->satOrgIOContext = agNULL; + satIOContext2->tiScsiXchg = agNULL; + + status = satSendReadLogExt( tiRoot, + &satIntIo->satIntTiIORequest, + tiDeviceHandle, + &satIntIo->satIntTiScsiXchg, + satIOContext2); + + if (status !=tiSuccess) + { + TI_DBG1(("ossaSATAEvent: can't send RLE due to LL api failure\n")); + satFreeIntIoResource( tiRoot, + pSatDevData, + satIntIo); + /* Abort I/O after completion of device reset */ + pSatDevData->satAbortAfterReset = agTRUE; +#ifdef NOT_YET + /* needs to investigate this case */ + /* no report to OS layer */ + satSubTM(tiRoot, + tiDeviceHandle, + TD_INTERNAL_TM_RESET, + agNULL, + agNULL, + agNULL, + agFALSE); +#endif + + return; + } + } + else + { + TI_DBG1(("ossaSATAEvent: NCQ ERROR but recovery in progress\n")); + } + + } + else if (event == OSSA_IO_XFER_CMD_FRAME_ISSUED) + { + TI_DBG1(("ossaSATAEvent: OSSA_IO_XFER_CMD_FRAME_ISSUED\n")); + } + else if (event == OSSA_IO_XFER_PIO_SETUP_ERROR) + { + TI_DBG1(("ossaSATAEvent: OSSA_IO_XFER_PIO_SETUP_ERROR\n")); + + } + else if (event == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED) + { + TI_DBG1(("ossaSATAEvent: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED\n")); + } + else if (event == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO) + { + TI_DBG1(("ossaSATAEvent: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO\n")); + } + else if (event == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST) + { + TI_DBG1(("ossaSATAEvent: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST\n")); + } + else if (event == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE) + { + TI_DBG1(("ossaSATAEvent: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE\n")); + } + else if (event == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED) + { + TI_DBG1(("ossaSATAEvent: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED\n")); + } + else if (event == OSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH) + { + TI_DBG1(("ossaSATAEvent: OSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH\n")); + } + else if (event == OSSA_IO_XFR_ERROR_DIF_MISMATCH || event == OSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH || + event == OSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH || event == OSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH) + { + TI_DBG1(("ossaSSPEvent: DIF related, event 0x%x\n", event)); + /* process DIF detail information */ + TI_DBG2(("ossaSSPEvent: agIOInfoLen %d\n", agIOInfoLen)); + if (agParam == agNULL) + { + TI_DBG2(("ossaSSPEvent: agParam is NULL!!!\n")); + return; + } + if (agIOInfoLen < sizeof(agsaDifDetails_t)) + { + TI_DBG2(("ossaSSPEvent: wrong agIOInfoLen!!! agIOInfoLen %d sizeof(agsaDifDetails_t) %d\n", agIOInfoLen, sizeof(agsaDifDetails_t))); + return; + } + /* reads agsaDifDetails_t */ + saFrameReadBlock(agRoot, agParam, 0, &agDifDetails, sizeof(agsaDifDetails_t)); + frameOffset = (agDifDetails.ErrBoffsetEDataLen & 0xFFFF); + frameLen = (agDifDetails.ErrBoffsetEDataLen & 0xFFFF0000) >> 16; + + TI_DBG2(("ossaSSPEvent: UpperLBA 0x%08x LowerLBA 0x%08x\n", agDifDetails.UpperLBA, agDifDetails.LowerLBA)); + TI_DBG2(("ossaSSPEvent: SASAddrHI 0x%08x SASAddrLO 0x%08x\n", + TD_GET_SAS_ADDRESSHI(agDifDetails.sasAddressHi), TD_GET_SAS_ADDRESSLO(agDifDetails.sasAddressLo))); + TI_DBG2(("ossaSSPEvent: DIF error mask 0x%x Device ID 0x%x\n", + (agDifDetails.DIFErrDevID) & 0xFF, (agDifDetails.DIFErrDevID & 0xFFFF0000) >> 16)); + if (frameLen != 0 && frameLen <= 256) + { + saFrameReadBlock(agRoot, agParam, sizeof(agsaDifDetails_t), framePayload, frameLen); + tdhexdump("ossaSSPEvent frame", framePayload, frameLen); + } + } + else + { + TI_DBG1(("ossaSATAEvent: ERROR event %d agDevHandle=%p.\n", event, agDevHandle )); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satIOContext = &(tdIORequestBody->transport.SATA.satIOContext); + pSatDevData = satIOContext->pSatDevData; + tdsaDeviceData = (tdsaDeviceData_t *)pSatDevData->satSaDeviceData; + onePortContext = tdsaDeviceData->tdPortContext; + TI_DBG1(("ossaSATAEvent: did %d\n", tdsaDeviceData->id)); + + /* send SMP_PHY_CONTROL_HARD_RESET */ + if (event == OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY && tdsaAllShared->FCA) + { + if (pSatDevData->NumOfFCA <= 0) /* does SMP HARD RESET only upto one time */ + { + TI_DBG1(("ossaSATAEvent: OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY; sending HARD_RESET\n")); + pSatDevData->NumOfFCA++; + tdsaPhyControlSend(tiRoot, + tdsaDeviceData, + SMP_PHY_CONTROL_HARD_RESET, + agNULL); + } + else + { + /* given up after one time of SMP HARD RESET; */ + TI_DBG1(("ossaSATAEvent: OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY; NO!!! sending HARD_RESET\n")); + if (tdsaDeviceData->registered == agTRUE && tdsaAllShared->ResetInDiscovery == 0) + { + /* + 1. remove this device + 2. device removal event + */ + tdsaAbortAll(tiRoot, agRoot, tdsaDeviceData); + tdsaDeviceData->valid = agFALSE; + tdsaDeviceData->valid2 = agFALSE; + tdsaDeviceData->registered = agFALSE; + ostiInitiatorEvent( + tiRoot, + onePortContext->tiPortalContext, + agNULL, + tiIntrEventTypeDeviceChange, + tiDeviceRemoval, + agNULL + ); + } + } + } + + } +} +#endif /* FDS_SM */ + +/***************************************************************************** +*! \brief itdsatErrorSATAEventHandle +* +* This routine is called to handle SATA error event +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agPortContext Pointer to the port context of TD and Lower layer +* \param agDevHandle: Pointer to a device handle +* \param event: event type +* \param ioContext: Pointer to satIOContext_t +* +* \return: none +* +*****************************************************************************/ +osGLOBAL void itdsatErrorSATAEventHandle( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + agsaPortContext_t *agPortContext, + agsaDevHandle_t *agDevHandle, + bit32 event, + satIOContext_t *ioContext + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdOrgIORequestBody; + satIOContext_t *satIOContext; + satIOContext_t *satOrgIOContext; + satInternalIo_t *satIntIo; + satDeviceData_t *satDevData; + bit32 interruptContext = osData->IntContext; + + TI_DBG1(("itdsatErrorSATAEventHandle: start\n")); + satIOContext = (satIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + satDevData = satIOContext->pSatDevData; + + + TI_DBG1(("itdsatErrorSATAEventHandle: event 0x%x\n", event)); + + if (satIntIo == agNULL) + { + TI_DBG1(("itdsatErrorSATAEventHandle: External, OS generated\n")); + satOrgIOContext = satIOContext; + tdOrgIORequestBody = (tdIORequestBody_t *)satOrgIOContext->tiRequestBody; + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + if (event == OSSA_IO_OVERFLOW) + { + TI_DBG1(("itdsatErrorSATAEventHandle: tiIOOverRun\n")); + ostiInitiatorIOCompleted( tiRoot, + tdOrgIORequestBody->tiIORequest, + tiIOOverRun, + 0, + agNULL, + interruptContext); + } + else + { + TI_DBG1(("itdsatErrorSATAEventHandle: else\n")); + ostiInitiatorIOCompleted( tiRoot, + tdOrgIORequestBody->tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + interruptContext); + } + } + else + { + TI_DBG1(("itdsatErrorSATAEventHandle: Internal, TD generated\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + TI_DBG1(("itdsatErrorSATAEventHandle: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + TI_DBG6(("itdsatErrorSATAEventHandle: satOrgIOContext is NOT NULL\n")); + } + tdOrgIORequestBody = (tdIORequestBody_t *)satOrgIOContext->tiRequestBody; + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + /* clean up TD layer's IORequestBody */ + ostiFreeMemory( + tiRoot, + tdOrgIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + + } + return; +} + +osGLOBAL void ossaSATAAbortCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 flag, + bit32 status) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdIORequestBody_t *tdAbortIORequestBody = agNULL; + tdsaDeviceData_t *oneDeviceData = agNULL; + tiDeviceHandle_t *tiDeviceHandle = agNULL; + tiIORequest_t *taskTag = agNULL; + + TI_DBG1(("ossaSATAAbortCB: start\n")); + + tdAbortIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + if (tdAbortIORequestBody == agNULL) + { + TI_DBG1(("ossaSATAAbortCB: tdAbortIORequestBody is NULL warning!!!!\n")); + return; + } + + if (flag == 2) + { + /* abort per port */ + TI_DBG1(("ossaSATAAbortCB: abort per port\n")); + } + else if (flag == 1) + { + TI_DBG1(("ossaSATAAbortCB: abort all\n")); + tiDeviceHandle = (tiDeviceHandle_t *)tdAbortIORequestBody->tiDevHandle; + if (tiDeviceHandle == agNULL) + { + TI_DBG1(("ossaSATAAbortCB: tiDeviceHandle is NULL warning!!!!\n")); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; + } + + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + if (oneDeviceData == agNULL) + { + TI_DBG1(("ossaSATAAbortCB: oneDeviceData is NULL warning!!!!\n")); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; + } + + if (status == OSSA_IO_SUCCESS) + { + TI_DBG1(("ossaSATAAbortCB: OSSA_IO_SUCCESS\n")); + /* clean up TD layer's IORequestBody */ + if (oneDeviceData->OSAbortAll == agTRUE) + { + oneDeviceData->OSAbortAll = agFALSE; + ostiInitiatorEvent( tiRoot, + agNULL, + tiDeviceHandle, + tiIntrEventTypeLocalAbort, + tiAbortOK, + agNULL); + } + else + { + TI_DBG1(("ossaSATAAbortCB: calling saDeregisterDeviceHandle did %d\n", oneDeviceData->id)); + saDeregisterDeviceHandle(agRoot, agNULL, oneDeviceData->agDevHandle, tdsaRotateQnumber(tiRoot, oneDeviceData)); + } + /* callback to OS layer here ??? */ + TI_DBG1(("ossaSATAAbortCB: did %d\n", oneDeviceData->id)); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + + } + else if (status == OSSA_IO_NOT_VALID) + { + TI_DBG1(("ossaSATAAbortCB: OSSA_IO_NOT_VALID\n")); + /* + Nothing is reproted to OS layer + */ + if (oneDeviceData->OSAbortAll == agTRUE) + { + oneDeviceData->OSAbortAll = agFALSE; + ostiInitiatorEvent( tiRoot, + agNULL, + tiDeviceHandle, + tiIntrEventTypeLocalAbort, + tiAbortFailed, + agNULL ); + } + else + { + TI_DBG1(("ossaSATAAbortCB: calling saDeregisterDeviceHandle did %d\n", oneDeviceData->id)); + saDeregisterDeviceHandle(agRoot, agNULL, oneDeviceData->agDevHandle, tdsaRotateQnumber(tiRoot, oneDeviceData)); + } + TI_DBG1(("ossaSATAAbortCB: did %d\n", oneDeviceData->id)); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + else if (status == OSSA_IO_NO_DEVICE) + { + TI_DBG1(("ossaSATAAbortCB: OSSA_IO_NO_DEVICE\n")); + /* + Nothing is reproted to OS layer + */ + if (oneDeviceData->OSAbortAll == agTRUE) + { + oneDeviceData->OSAbortAll = agFALSE; + ostiInitiatorEvent( tiRoot, + agNULL, + tiDeviceHandle, + tiIntrEventTypeLocalAbort, + tiAbortInProgress, + agNULL ); + } + else + { + TI_DBG1(("ossaSATAAbortCB: calling saDeregisterDeviceHandle did %d\n", oneDeviceData->id)); + saDeregisterDeviceHandle(agRoot, agNULL, oneDeviceData->agDevHandle, tdsaRotateQnumber(tiRoot, oneDeviceData)); + } + TI_DBG1(("ossaSATAAbortCB: did %d\n", oneDeviceData->id)); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + else if (status == OSSA_IO_ABORT_IN_PROGRESS) + { + TI_DBG1(("ossaSATAAbortCB: OSSA_IO_ABORT_IN_PROGRESS\n")); + /* + Nothing is reproted to OS layer + */ + if (oneDeviceData->OSAbortAll == agTRUE) + { + oneDeviceData->OSAbortAll = agFALSE; + ostiInitiatorEvent( tiRoot, + agNULL, + tiDeviceHandle, + tiIntrEventTypeLocalAbort, + tiAbortInProgress, + agNULL ); + } + else + { + TI_DBG1(("ossaSATAAbortCB: calling saDeregisterDeviceHandle did %d\n", oneDeviceData->id)); + saDeregisterDeviceHandle(agRoot, agNULL, oneDeviceData->agDevHandle, tdsaRotateQnumber(tiRoot, oneDeviceData)); + } + TI_DBG1(("ossaSATAAbortCB: did %d\n", oneDeviceData->id)); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + else + { + TI_DBG1(("ossaSATAAbortCB: unspecified status 0x%x\n", status )); + /* + Nothing is reproted to OS layer + */ + if (oneDeviceData->OSAbortAll == agTRUE) + { + oneDeviceData->OSAbortAll = agFALSE; + ostiInitiatorEvent( tiRoot, + agNULL, + tiDeviceHandle, + tiIntrEventTypeLocalAbort, + tiAbortInProgress, + agNULL ); + } + else + { + TI_DBG1(("ossaSATAAbortCB: calling saDeregisterDeviceHandle did %d\n", oneDeviceData->id)); + saDeregisterDeviceHandle(agRoot, agNULL, oneDeviceData->agDevHandle, tdsaRotateQnumber(tiRoot, oneDeviceData)); + } + TI_DBG1(("ossaSATAAbortCB: did %d\n", oneDeviceData->id)); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + } + else if (flag == 0) + { + TI_DBG1(("ossaSATAAbortCB: abort one\n")); + taskTag = tdAbortIORequestBody->tiIOToBeAbortedRequest; + + if (status == OSSA_IO_SUCCESS) + { + TI_DBG1(("ossaSATAAbortCB: OSSA_IO_SUCCESS\n")); + + ostiInitiatorEvent( tiRoot, + agNULL, + agNULL, + tiIntrEventTypeLocalAbort, + tiAbortOK, + taskTag ); + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + + } + else if (status == OSSA_IO_NOT_VALID) + { + TI_DBG1(("ossaSATAAbortCB: OSSA_IO_NOT_VALID\n")); + + ostiInitiatorEvent( tiRoot, + agNULL, + agNULL, + tiIntrEventTypeLocalAbort, + tiAbortFailed, + taskTag ); + + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + else if (status == OSSA_IO_NO_DEVICE) + { + TI_DBG1(("ossaSATAAbortCB: OSSA_IO_NO_DEVICE\n")); + + ostiInitiatorEvent( tiRoot, + agNULL, + agNULL, + tiIntrEventTypeLocalAbort, + tiAbortInProgress, + taskTag ); + + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + else if (status == OSSA_IO_ABORT_IN_PROGRESS) + { + TI_DBG1(("ossaSATAAbortCB: OSSA_IO_ABORT_IN_PROGRESS\n")); + + ostiInitiatorEvent( tiRoot, + agNULL, + agNULL, + tiIntrEventTypeLocalAbort, + tiAbortInProgress, + taskTag ); + + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + else + { + TI_DBG1(("ossaSATAAbortCB: unspecified status 0x%x\n", status )); + + ostiInitiatorEvent( tiRoot, + agNULL, + agNULL, + tiIntrEventTypeLocalAbort, + tiAbortFailed, + taskTag ); + + ostiFreeMemory( + tiRoot, + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + } + else + { + TI_DBG1(("ossaSATAAbortCB: wrong flag %d\n", flag)); + } + return; +} + +/***************************************************************************** +*! \brief ossaSATADeviceResetCB +* +* This routine is called to complete a SATA device reset request previously +* issued to the LL Layer in saSATADeviceReset(). +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agDevHandle: Pointer to a device handle +* \param resetStatus: Reset status: +* OSSA_SUCCESS: The reset operation completed successfully. +* OSSA_FAILURE: The reset operation failed. +* \param resetparm: Pointer to the Device-To-Host FIS received from the device. +* +* \return: none +* +*****************************************************************************/ +osGLOBAL void +ossaSATADeviceResetCB( + agsaRoot_t *agRoot, + agsaDevHandle_t *agDevHandle, + bit32 resetStatus, + void *resetparm) +{ + bit32 tiResetStatus; + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaDeviceData_t *pDeviceData; + tiDeviceHandle_t *tiDeviceHandle; + + TI_DBG1(("ossaSATADeviceResetCB: agDevHandle=%p resetStatus=0x%x\n", + agDevHandle, resetStatus )); + + pDeviceData = (tdsaDeviceData_t *) agDevHandle->osData; + tiDeviceHandle = &(pDeviceData->tiDeviceHandle); + + if (resetStatus == OSSA_SUCCESS ) + tiResetStatus = tiSuccess; + else + tiResetStatus = tiError; + + osSatResetCB( tiRoot, + tiDeviceHandle, + tiResetStatus, + resetparm); + +} + + +/*****************************************************************************/ +/*! \brief satDecrementPendingIO + * + * This function decrements the number of pending IO's + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tdsaAllShared: Pointer to TD context. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return + * None + */ +/*****************************************************************************/ +GLOBAL void +satDecrementPendingIO( + tiRoot_t *tiRoot, + tdsaContext_t *tdsaAllShared, + satIOContext_t *satIOContext + ) +{ + satDeviceData_t *satDevData; + + TI_DBG4(("satDecrementPendingIO: start\n")); + + satDevData = satIOContext->pSatDevData; + + if ( (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_WRITE) || + (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_READ) ) + { + tdsaSingleThreadedEnter(tiRoot, TD_SATA_LOCK); + satDevData->satPendingNCQIO--; + satIOContext->pSatDevData->satPendingIO--; + TDLIST_DEQUEUE_THIS (&satIOContext->satIoContextLink); + tdsaSingleThreadedLeave(tiRoot, TD_SATA_LOCK); + } + else + { + tdsaSingleThreadedEnter(tiRoot, TD_SATA_LOCK); + satDevData->satPendingNONNCQIO--; + satIOContext->pSatDevData->satPendingIO--; + TDLIST_DEQUEUE_THIS (&satIOContext->satIoContextLink); + tdsaSingleThreadedLeave(tiRoot, TD_SATA_LOCK); + } + + return; +} + +GLOBAL void +satTranslateATAPIErrorsToSCSIErrors( + bit8 bCommand, + bit8 bATAStatus, + bit8 bATAError, + bit8 *pSenseKey, + bit16 *pSenseCodeInfo + ) +{ + if (pSenseKey == agNULL || pSenseCodeInfo == agNULL) + { + TI_DBG0(("TranslateATAErrorsToSCSIErros: pSenseKey == agNULL || pSenseCodeInfo == agNULL\n")); + return; + } + + if((bATAStatus & ERR_ATA_STATUS_MASK) && (bATAError & NM_ATA_ERROR_MASK)) + { + *pSenseKey = SCSI_SNSKEY_NOT_READY; + *pSenseCodeInfo = 0x3a00; + } + else if((bATAStatus & ERR_ATA_STATUS_MASK) && (bATAError & ABRT_ATA_ERROR_MASK)) + { + *pSenseKey = SCSI_SNSKEY_ABORTED_COMMAND; + *pSenseCodeInfo = 0; + } + else if((bATAStatus & ERR_ATA_STATUS_MASK) && (bATAError & MCR_ATA_ERROR_MASK)) + { + *pSenseKey = SCSI_SNSKEY_UNIT_ATTENTION; + *pSenseCodeInfo = 0x5a01; + } + else if((bATAStatus & ERR_ATA_STATUS_MASK) && (bATAError & IDNF_ATA_ERROR_MASK)) + { + *pSenseKey = SCSI_SNSKEY_MEDIUM_ERROR; + *pSenseCodeInfo = 0x1401; + } + else if((bATAStatus & ERR_ATA_STATUS_MASK) && (bATAError & MC_ATA_ERROR_MASK)) + { + *pSenseKey = SCSI_SNSKEY_UNIT_ATTENTION; + *pSenseCodeInfo = 0x2800; + } + else if((bATAStatus & ERR_ATA_STATUS_MASK) && (bATAError & UNC_ATA_ERROR_MASK)) + { + /*READ*/ + *pSenseKey = SCSI_SNSKEY_MEDIUM_ERROR; + *pSenseCodeInfo = 0x1100; + + /*add WRITE here */ + } + else if((bATAStatus & ERR_ATA_STATUS_MASK) && (bATAError & ICRC_ATA_ERROR_MASK)) + { + *pSenseKey = SCSI_SNSKEY_ABORTED_COMMAND; + *pSenseCodeInfo = 0x4703; + } + else if((bATAStatus & DF_ATA_STATUS_MASK)) + { + *pSenseKey = SCSI_SNSKEY_HARDWARE_ERROR; + *pSenseCodeInfo = 0x4400; + } + else + { + TI_DBG0(("unhandled ata error: bATAStatus = 0x%x, bATAError = 0x%x\n", + bATAStatus, bATAError)); + } + +} + +#endif /* #ifdef SATA_ENABLE */ + diff --git a/sys/dev/pms/RefTisa/tisa/sassata/sata/host/sat.c b/sys/dev/pms/RefTisa/tisa/sassata/sata/host/sat.c new file mode 100644 index 000000000000..e46fb329b204 --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/sata/host/sat.c @@ -0,0 +1,23309 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +/*****************************************************************************/ +/** \file + * + * The file implementing SCSI/ATA Translation (SAT). + * The routines in this file are independent from HW LL API. + * + */ +/*****************************************************************************/ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#include +#include + +#ifdef SATA_ENABLE + +#include +#include +#include + +#include +#include +#include +#include + +#ifdef FDS_SM +#include +#include +#include +#endif + +#ifdef FDS_DM +#include +#include +#include +#endif + +#include +#include +#include + +#ifdef INITIATOR_DRIVER +#include +#include +#include +#endif + +#ifdef TARGET_DRIVER +#include +#include +#include +#endif + +#include +#include + +#include +#include + +/***************************************************************************** + *! \brief satIOStart + * + * This routine is called to initiate a new SCSI request to SATL. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return: + * + * \e tiSuccess: I/O request successfully initiated. + * \e tiBusy: No resources available, try again later. + * \e tiIONoDevice: Invalid device handle. + * \e tiError: Other errors that prevent the I/O request to be started. + * + * + *****************************************************************************/ +GLOBAL bit32 satIOStart( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext + ) +{ + + bit32 retVal = tiSuccess; + satDeviceData_t *pSatDevData; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + tiLUN_t *pLun; + satInternalIo_t *pSatIntIo; +#ifdef TD_DEBUG_ENABLE + tdsaDeviceData_t *oneDeviceData; +#endif + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &tiScsiRequest->scsiCmnd; + pLun = &scsiCmnd->lun; + + /* + * Reject all other LUN other than LUN 0. + */ + if ( ((pLun->lun[0] | pLun->lun[1] | pLun->lun[2] | pLun->lun[3] | + pLun->lun[4] | pLun->lun[5] | pLun->lun[6] | pLun->lun[7] ) != 0) && + (scsiCmnd->cdb[0] != SCSIOPC_INQUIRY) + ) + { + TI_DBG1(("satIOStart: *** REJECT *** LUN not zero, cdb[0]=0x%x tiIORequest=%p tiDeviceHandle=%p\n", + scsiCmnd->cdb[0], tiIORequest, tiDeviceHandle)); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_NOT_SUPPORTED, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + retVal = tiSuccess; + goto ext; + } + + TI_DBG6(("satIOStart: satPendingIO %d satNCQMaxIO %d\n",pSatDevData->satPendingIO, pSatDevData->satNCQMaxIO )); + + /* this may happen after tiCOMReset until OS sends inquiry */ + if (pSatDevData->IDDeviceValid == agFALSE && (scsiCmnd->cdb[0] != SCSIOPC_INQUIRY)) + { +#ifdef TD_DEBUG_ENABLE + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; +#endif + TI_DBG1(("satIOStart: invalid identify device data did %d\n", oneDeviceData->id)); + retVal = tiIONoDevice; + goto ext; + } + /* + * Check if we need to return BUSY, i.e. recovery in progress + */ + if (pSatDevData->satDriveState == SAT_DEV_STATE_IN_RECOVERY) + { +#ifdef TD_DEBUG_ENABLE + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; +#endif + TI_DBG1(("satIOStart: IN RECOVERY STATE cdb[0]=0x%x tiIORequest=%p tiDeviceHandle=%p\n", + scsiCmnd->cdb[0], tiIORequest, tiDeviceHandle)); + TI_DBG1(("satIOStart: IN RECOVERY STATE did %d\n", oneDeviceData->id)); + + TI_DBG1(("satIOStart: device %p satPendingIO %d satNCQMaxIO %d\n",pSatDevData, pSatDevData->satPendingIO, pSatDevData->satNCQMaxIO )); + TI_DBG1(("satIOStart: device %p satPendingNCQIO %d satPendingNONNCQIO %d\n",pSatDevData, pSatDevData->satPendingNCQIO, pSatDevData->satPendingNONNCQIO)); + retVal = tiError; + goto ext; +// return tiBusy; + } + + if (pSatDevData->satDeviceType == SATA_ATAPI_DEVICE) + { + if (scsiCmnd->cdb[0] == SCSIOPC_REPORT_LUN) + { + return satReportLun(tiRoot, tiIORequest, tiDeviceHandle, tiScsiRequest, satIOContext); + } + else + { + return satPacket(tiRoot, tiIORequest, tiDeviceHandle, tiScsiRequest, satIOContext); + } + } + else /* pSatDevData->satDeviceType != SATA_ATAPI_DEVICE */ + { + /* Parse CDB */ + switch(scsiCmnd->cdb[0]) + { + case SCSIOPC_READ_6: + retVal = satRead6( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + break; + + case SCSIOPC_READ_10: + retVal = satRead10( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + break; + + case SCSIOPC_READ_12: + TI_DBG5(("satIOStart: SCSIOPC_READ_12\n")); + retVal = satRead12( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + break; + + case SCSIOPC_READ_16: + retVal = satRead16( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + break; + + case SCSIOPC_WRITE_6: + retVal = satWrite6( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + break; + + case SCSIOPC_WRITE_10: + retVal = satWrite10( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + break; + + case SCSIOPC_WRITE_12: + TI_DBG5(("satIOStart: SCSIOPC_WRITE_12 \n")); + retVal = satWrite12( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + break; + + case SCSIOPC_WRITE_16: + TI_DBG5(("satIOStart: SCSIOPC_WRITE_16\n")); + retVal = satWrite16( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + break; + + case SCSIOPC_VERIFY_10: + retVal = satVerify10( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + break; + + case SCSIOPC_VERIFY_12: + TI_DBG5(("satIOStart: SCSIOPC_VERIFY_12\n")); + retVal = satVerify12( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + break; + + case SCSIOPC_VERIFY_16: + TI_DBG5(("satIOStart: SCSIOPC_VERIFY_16\n")); + retVal = satVerify16( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + break; + + case SCSIOPC_TEST_UNIT_READY: + retVal = satTestUnitReady( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + break; + + case SCSIOPC_INQUIRY: + retVal = satInquiry( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + break; + + case SCSIOPC_REQUEST_SENSE: + retVal = satRequestSense( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + break; + + case SCSIOPC_MODE_SENSE_6: + retVal = satModeSense6( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + break; + + case SCSIOPC_MODE_SENSE_10: + retVal = satModeSense10( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + break; + + + case SCSIOPC_READ_CAPACITY_10: + retVal = satReadCapacity10( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + break; + + case SCSIOPC_READ_CAPACITY_16: + retVal = satReadCapacity16( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + break; + + case SCSIOPC_REPORT_LUN: + retVal = satReportLun( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + break; + + case SCSIOPC_FORMAT_UNIT: + TI_DBG5(("satIOStart: SCSIOPC_FORMAT_UNIT\n")); + retVal = satFormatUnit( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + break; + case SCSIOPC_SEND_DIAGNOSTIC: /* Table 28, p40 */ + TI_DBG5(("satIOStart: SCSIOPC_SEND_DIAGNOSTIC\n")); + retVal = satSendDiagnostic( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + break; + + case SCSIOPC_START_STOP_UNIT: + TI_DBG5(("satIOStart: SCSIOPC_START_STOP_UNIT\n")); + retVal = satStartStopUnit( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + break; + + case SCSIOPC_WRITE_SAME_10: /* sector and LBA; SAT p64 case 3 accessing payload and very + inefficient now */ + TI_DBG5(("satIOStart: SCSIOPC_WRITE_SAME_10\n")); + retVal = satWriteSame10( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + break; + + case SCSIOPC_WRITE_SAME_16: /* no support due to transfer length(sector count) */ + TI_DBG5(("satIOStart: SCSIOPC_WRITE_SAME_16\n")); + retVal = satWriteSame16( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + break; + + case SCSIOPC_LOG_SENSE: /* SCT and log parameter(informational exceptions) */ + TI_DBG5(("satIOStart: SCSIOPC_LOG_SENSE\n")); + retVal = satLogSense( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + break; + + case SCSIOPC_MODE_SELECT_6: /*mode layout and AlloLen check */ + TI_DBG5(("satIOStart: SCSIOPC_MODE_SELECT_6\n")); + retVal = satModeSelect6( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + break; + + case SCSIOPC_MODE_SELECT_10: /* mode layout and AlloLen check and sharing CB with satModeSelect6*/ + TI_DBG5(("satIOStart: SCSIOPC_MODE_SELECT_10\n")); + retVal = satModeSelect10( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + break; + + case SCSIOPC_SYNCHRONIZE_CACHE_10: /* on error what to return, sharing CB with + satSynchronizeCache16 */ + TI_DBG5(("satIOStart: SCSIOPC_SYNCHRONIZE_CACHE_10\n")); + retVal = satSynchronizeCache10( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + break; + + case SCSIOPC_SYNCHRONIZE_CACHE_16:/* on error what to return, sharing CB with + satSynchronizeCache16 */ + + TI_DBG5(("satIOStart: SCSIOPC_SYNCHRONIZE_CACHE_16\n")); + retVal = satSynchronizeCache16( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + break; + + case SCSIOPC_WRITE_AND_VERIFY_10: /* single write and multiple writes */ + TI_DBG5(("satIOStart: SCSIOPC_WRITE_AND_VERIFY_10\n")); + retVal = satWriteAndVerify10( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + break; + + case SCSIOPC_WRITE_AND_VERIFY_12: + TI_DBG5(("satIOStart: SCSIOPC_WRITE_AND_VERIFY_12\n")); + retVal = satWriteAndVerify12( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + break; + + case SCSIOPC_WRITE_AND_VERIFY_16: + TI_DBG5(("satIOStart: SCSIOPC_WRITE_AND_VERIFY_16\n")); + retVal = satWriteAndVerify16( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + break; + + case SCSIOPC_READ_MEDIA_SERIAL_NUMBER: + TI_DBG5(("satIOStart: SCSIOPC_READ_MEDIA_SERIAL_NUMBER\n")); + retVal = satReadMediaSerialNumber( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + break; + + case SCSIOPC_READ_BUFFER: + TI_DBG5(("satIOStart: SCSIOPC_READ_BUFFER\n")); + retVal = satReadBuffer( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + break; + + case SCSIOPC_WRITE_BUFFER: + TI_DBG5(("satIOStart: SCSIOPC_WRITE_BUFFER\n")); + retVal = satWriteBuffer( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + break; + + case SCSIOPC_REASSIGN_BLOCKS: + TI_DBG5(("satIOStart: SCSIOPC_REASSIGN_BLOCKS\n")); + retVal = satReassignBlocks( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + break; + + default: + /* Not implemented SCSI cmd, set up error response */ + TI_DBG1(("satIOStart: unsupported SCSI cdb[0]=0x%x tiIORequest=%p tiDeviceHandle=%p\n", + scsiCmnd->cdb[0], tiIORequest, tiDeviceHandle)); + + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_COMMAND, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + retVal = tiSuccess; + + break; + + } /* end switch */ + } + if (retVal == tiBusy) + { +#ifdef TD_DEBUG_ENABLE + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; +#endif + TI_DBG1(("satIOStart: BUSY did %d\n", oneDeviceData->id)); + TI_DBG3(("satIOStart: LL is busy or target queue is full\n")); + TI_DBG3(("satIOStart: device %p satPendingIO %d satNCQMaxIO %d\n",pSatDevData, pSatDevData->satPendingIO, pSatDevData->satNCQMaxIO )); + TI_DBG3(("satIOStart: device %p satPendingNCQIO %d satPendingNONNCQIO %d\n",pSatDevData, pSatDevData->satPendingNCQIO, pSatDevData->satPendingNONNCQIO)); + pSatIntIo = satIOContext->satIntIoContext; + + /* interal structure free */ + satFreeIntIoResource( tiRoot, + pSatDevData, + pSatIntIo); + } + +ext: + return retVal; +} + + +/*****************************************************************************/ +/*! \brief Setup up the SCSI Sense response. + * + * This function is used to setup up the Sense Data payload for + * CHECK CONDITION status. + * + * \param pSense: Pointer to the scsiRspSense_t sense data structure. + * \param SnsKey: SCSI Sense Key. + * \param SnsInfo: SCSI Sense Info. + * \param SnsCode: SCSI Sense Code. + * + * \return: None + */ +/*****************************************************************************/ +void satSetSensePayload( scsiRspSense_t *pSense, + bit8 SnsKey, + bit32 SnsInfo, + bit16 SnsCode, + satIOContext_t *satIOContext + ) +{ + /* for fixed format sense data, SPC-4, p37 */ + bit32 i; + bit32 senseLength; + + TI_DBG5(("satSetSensePayload: start\n")); + + senseLength = sizeof(scsiRspSense_t); + + /* zero out the data area */ + for (i=0;i< senseLength;i++) + { + ((bit8*)pSense)[i] = 0; + } + + /* + * SCSI Sense Data part of response data + */ + pSense->snsRespCode = 0x70; /* 0xC0 == vendor specific */ + /* 0x70 == standard current error */ + pSense->senseKey = SnsKey; + /* + * Put sense info in scsi order format + */ + pSense->info[0] = (bit8)((SnsInfo >> 24) & 0xff); + pSense->info[1] = (bit8)((SnsInfo >> 16) & 0xff); + pSense->info[2] = (bit8)((SnsInfo >> 8) & 0xff); + pSense->info[3] = (bit8)((SnsInfo) & 0xff); + pSense->addSenseLen = 11; /* fixed size of sense data = 18 */ + pSense->addSenseCode = (bit8)((SnsCode >> 8) & 0xFF); + pSense->senseQual = (bit8)(SnsCode & 0xFF); + /* + * Set pointer in scsi status + */ + switch(SnsKey) + { + /* + * set illegal request sense key specific error in cdb, no bit pointer + */ + case SCSI_SNSKEY_ILLEGAL_REQUEST: + pSense->skeySpecific[0] = 0xC8; + break; + + default: + break; + } + /* setting sense data length */ + if (satIOContext != agNULL) + { + satIOContext->pTiSenseData->senseLen = 18; + } + else + { + TI_DBG1(("satSetSensePayload: satIOContext is NULL\n")); + } +} + +/*****************************************************************************/ +/*! \brief Setup up the SCSI Sense response. + * + * This function is used to setup up the Sense Data payload for + * CHECK CONDITION status. + * + * \param pSense: Pointer to the scsiRspSense_t sense data structure. + * \param SnsKey: SCSI Sense Key. + * \param SnsInfo: SCSI Sense Info. + * \param SnsCode: SCSI Sense Code. + * + * \return: None + */ +/*****************************************************************************/ + +void satSetDeferredSensePayload( scsiRspSense_t *pSense, + bit8 SnsKey, + bit32 SnsInfo, + bit16 SnsCode, + satIOContext_t *satIOContext + ) +{ + /* for fixed format sense data, SPC-4, p37 */ + bit32 i; + bit32 senseLength; + + senseLength = sizeof(scsiRspSense_t); + + /* zero out the data area */ + for (i=0;i< senseLength;i++) + { + ((bit8*)pSense)[i] = 0; + } + + /* + * SCSI Sense Data part of response data + */ + pSense->snsRespCode = 0x71; /* 0xC0 == vendor specific */ + /* 0x70 == standard current error */ + pSense->senseKey = SnsKey; + /* + * Put sense info in scsi order format + */ + pSense->info[0] = (bit8)((SnsInfo >> 24) & 0xff); + pSense->info[1] = (bit8)((SnsInfo >> 16) & 0xff); + pSense->info[2] = (bit8)((SnsInfo >> 8) & 0xff); + pSense->info[3] = (bit8)((SnsInfo) & 0xff); + pSense->addSenseLen = 11; /* fixed size of sense data = 18 */ + pSense->addSenseCode = (bit8)((SnsCode >> 8) & 0xFF); + pSense->senseQual = (bit8)(SnsCode & 0xFF); + /* + * Set pointer in scsi status + */ + switch(SnsKey) + { + /* + * set illegal request sense key specific error in cdb, no bit pointer + */ + case SCSI_SNSKEY_ILLEGAL_REQUEST: + pSense->skeySpecific[0] = 0xC8; + break; + + default: + break; + } + + /* setting sense data length */ + if (satIOContext != agNULL) + { + satIOContext->pTiSenseData->senseLen = 18; + } + else + { + TI_DBG1(("satSetDeferredSensePayload: satIOContext is NULL\n")); + } + +} +/*****************************************************************************/ +/*! \brief SAT implementation for ATAPI Packet Command. + * + * SAT implementation for ATAPI Packet and send FIS request to LL layer. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satPacket( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_D2H_PKT; + satDeviceData_t *pSatDevData; + tiIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &tiScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + TI_DBG3(("satPacket: start, SCSI CDB is 0x%X %X %X %X %X %X %X %X %X %X %X %X\n", + scsiCmnd->cdb[0],scsiCmnd->cdb[1],scsiCmnd->cdb[2],scsiCmnd->cdb[3], + scsiCmnd->cdb[4],scsiCmnd->cdb[5],scsiCmnd->cdb[6],scsiCmnd->cdb[7], + scsiCmnd->cdb[8],scsiCmnd->cdb[9],scsiCmnd->cdb[10],scsiCmnd->cdb[11])); + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set 1*/ + fis->h.command = SAT_PACKET; /* 0xA0 */ + if (pSatDevData->satDMADIRSupport) /* DMADIR enabled*/ + { + fis->h.features = (tiScsiRequest->dataDirection == tiDirectionIn)? 0x04 : 0; /* 1 for D2H, 0 for H2D */ + } + else + { + fis->h.features = 0; /* FIS reserve */ + } + /* Byte count low and byte count high */ + if ( scsiCmnd->expDataLength > 0xFFFF ) + { + fis->d.lbaMid = 0xFF; /* FIS LBA (7 :0 ) */ + fis->d.lbaHigh = 0xFF; /* FIS LBA (15:8 ) */ + } + else + { + fis->d.lbaMid = (bit8)scsiCmnd->expDataLength; /* FIS LBA (7 :0 ) */ + fis->d.lbaHigh = (bit8)(scsiCmnd->expDataLength>>8); /* FIS LBA (15:8 ) */ + } + + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.device = 0; /* FIS LBA (27:24) and FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + satIOContext->ATACmd = SAT_PACKET; + + if (tiScsiRequest->dataDirection == tiDirectionIn) + { + agRequestType = AGSA_SATA_PROTOCOL_D2H_PKT; + } + else + { + agRequestType = AGSA_SATA_PROTOCOL_H2D_PKT; + } + + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /*DMA transfer mode*/ + fis->h.features |= 0x01; + } + else + { + /*PIO transfer mode*/ + fis->h.features |= 0x0; + } + + satIOContext->satCompleteCB = &satPacketCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + TI_DBG5(("satPacket: return\n")); + return (status); +} + +/*****************************************************************************/ +/*! \brief SAT implementation for satSetFeatures. + * + * This function creates SetFeatures fis and sends the request to LL layer + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satSetFeatures( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext, + bit8 bIsDMAMode + ) +{ + bit32 status; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; + + fis = satIOContext->pFis; + TI_DBG3(("satSetFeatures: start\n")); + + /* + * Send the Set Features command. + */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_SET_FEATURES; /* 0xEF */ + fis->h.features = 0x03; /* set transfer mode */ + fis->d.lbaLow = 0; + fis->d.lbaMid = 0; + fis->d.lbaHigh = 0; + fis->d.device = 0; + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + if (bIsDMAMode) + { + fis->d.sectorCount = 0x45; + /*satIOContext->satCompleteCB = &satSetFeaturesDMACB;*/ + } + else + { + fis->d.sectorCount = 0x0C; + /*satIOContext->satCompleteCB = &satSetFeaturesPIOCB;*/ + } + satIOContext->satCompleteCB = &satSetFeaturesCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + TI_DBG5(("satSetFeatures: return\n")); + + return status; +} +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI REQUEST SENSE to ATAPI device. + * + * SAT implementation for SCSI REQUEST SENSE. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satRequestSenseForATAPI( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_D2H_PKT; + satDeviceData_t *pSatDevData; + tiIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &tiScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + scsiCmnd->cdb[0] = SCSIOPC_REQUEST_SENSE; + scsiCmnd->cdb[1] = 0; + scsiCmnd->cdb[2] = 0; + scsiCmnd->cdb[3] = 0; + scsiCmnd->cdb[4] = SENSE_DATA_LENGTH; + scsiCmnd->cdb[5] = 0; + TI_DBG3(("satRequestSenseForATAPI: start, SCSI CDB is 0x%X %X %X %X %X %X %X %X %X %X %X %X\n", + scsiCmnd->cdb[0],scsiCmnd->cdb[1],scsiCmnd->cdb[2],scsiCmnd->cdb[3], + scsiCmnd->cdb[4],scsiCmnd->cdb[5],scsiCmnd->cdb[6],scsiCmnd->cdb[7], + scsiCmnd->cdb[8],scsiCmnd->cdb[9],scsiCmnd->cdb[10],scsiCmnd->cdb[11])); + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set 1*/ + fis->h.command = SAT_PACKET; /* 0xA0 */ + if (pSatDevData->satDMADIRSupport) /* DMADIR enabled*/ + { + fis->h.features = (tiScsiRequest->dataDirection == tiDirectionIn)? 0x04 : 0; /* 1 for D2H, 0 for H2D */ + } + else + { + fis->h.features = 0; /* FIS reserve */ + } + + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0x20; /* FIS LBA (23:16) */ + fis->d.device = 0; /* FIS LBA (27:24) and FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = (bit32)(scsiCmnd->cdb[0]|(scsiCmnd->cdb[1]<<8)|(scsiCmnd->cdb[2]<<16)|(scsiCmnd->cdb[3]<<24)); + + satIOContext->ATACmd = SAT_PACKET; + + agRequestType = AGSA_SATA_PROTOCOL_D2H_PKT; + + //if (pSatDevData->sat48BitSupport == agTRUE) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + fis->h.features |= 0x01; + } + else + { + fis->h.features |= 0x0; + } + } + + satIOContext->satCompleteCB = &satRequestSenseForATAPICB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + TI_DBG5(("satRequestSenseForATAPI: return\n")); + return (status); +} +/*****************************************************************************/ +/*! \brief SAT implementation for satDeviceReset. + * + * This function creates DEVICE RESET fis and sends the request to LL layer + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satDeviceReset( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext + ) +{ + bit32 status; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; + + fis = satIOContext->pFis; + + TI_DBG3(("satDeviceReset: start\n")); + + /* + * Send the Execute Device Diagnostic command. + */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_DEVICE_RESET; /* 0x90 */ + fis->h.features = 0; + fis->d.lbaLow = 0; + fis->d.lbaMid = 0; + fis->d.lbaHigh = 0; + fis->d.device = 0; + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DEV_RESET; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satDeviceResetCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + TI_DBG3(("satDeviceReset: return\n")); + + return status; +} + +/*****************************************************************************/ +/*! \brief SAT implementation for saExecuteDeviceDiagnostic. + * + * This function creates Execute Device Diagnostic fis and sends the request to LL layer + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satExecuteDeviceDiagnostic( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext + ) +{ + bit32 status; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; + + fis = satIOContext->pFis; + + TI_DBG3(("satExecuteDeviceDiagnostic: start\n")); + + /* + * Send the Execute Device Diagnostic command. + */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_EXECUTE_DEVICE_DIAGNOSTIC; /* 0x90 */ + fis->h.features = 0; + fis->d.lbaLow = 0; + fis->d.lbaMid = 0; + fis->d.lbaHigh = 0; + fis->d.device = 0; + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satExecuteDeviceDiagnosticCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + TI_DBG5(("satExecuteDeviceDiagnostic: return\n")); + + return status; +} + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI READ10. + * + * SAT implementation for SCSI READ10 and send FIS request to LL layer. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satRead10( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_DMA_READ; + satDeviceData_t *pSatDevData; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 lba = 0; + bit32 tl = 0; + bit32 LoopNum = 1; + bit8 LBA[4]; + bit8 TL[4]; + bit32 rangeChk = agFALSE; /* lba and tl range check */ + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &tiScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + TI_DBG5(("satRead10: start\n")); + TI_DBG5(("satRead10: pSatDevData=%p\n", pSatDevData)); + // tdhexdump("satRead10", (bit8 *)scsiCmnd->cdb, 10); + + /* checking FUA_NV */ + if (scsiCmnd->cdb[1] & SCSI_FUA_NV_MASK) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satRead10: return FUA_NV\n")); + return tiSuccess; + + } + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[9] & SCSI_NACA_MASK) || (scsiCmnd->cdb[9] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satRead10: return control\n")); + return tiSuccess; + } + + osti_memset(LBA, 0, sizeof(LBA)); + osti_memset(TL, 0, sizeof(TL)); + + /* do not use memcpy due to indexing in LBA and TL */ + LBA[0] = scsiCmnd->cdb[2]; /* MSB */ + LBA[1] = scsiCmnd->cdb[3]; + LBA[2] = scsiCmnd->cdb[4]; + LBA[3] = scsiCmnd->cdb[5]; /* LSB */ + + TL[0] = 0; + TL[1] = 0; + TL[2] = scsiCmnd->cdb[7]; /* MSB */ + TL[3] = scsiCmnd->cdb[8]; /* LSB */ + + rangeChk = satAddNComparebit32(LBA, TL); + + /* cbd10; computing LBA and transfer length */ + lba = (scsiCmnd->cdb[2] << (8*3)) + (scsiCmnd->cdb[3] << (8*2)) + + (scsiCmnd->cdb[4] << 8) + scsiCmnd->cdb[5]; + tl = (scsiCmnd->cdb[7] << 8) + scsiCmnd->cdb[8]; + + + TI_DBG5(("satRead10: lba %d functioned lba %d\n", lba, satComputeCDB10LBA(satIOContext))); + TI_DBG5(("satRead10: lba 0x%x functioned lba 0x%x\n", lba, satComputeCDB10LBA(satIOContext))); + TI_DBG5(("satRead10: tl %d functioned tl %d\n", tl, satComputeCDB10TL(satIOContext))); + + /* Table 34, 9.1, p 46 */ + /* + note: As of 2/10/2006, no support for DMA QUEUED + */ + + /* + Table 34, 9.1, p 46, b + When no 48-bit addressing support or NCQ, if LBA is beyond (2^28 - 1), + return check condition + */ + + if (pSatDevData->satNCQ != agTRUE && + pSatDevData->sat48BitSupport != agTRUE + ) + { + if (lba > SAT_TR_LBA_LIMIT - 1) + { + TI_DBG1(("satRead10: return LBA out of range, not EXT\n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + return tiSuccess; + } + + + if (rangeChk) // if (lba + tl > SAT_TR_LBA_LIMIT) + { + TI_DBG1(("satRead10: return LBA+TL out of range, not EXT\n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + return tiSuccess; + } + } + + /* case 1 and 2 */ + if (!rangeChk) // if (lba + tl <= SAT_TR_LBA_LIMIT) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 2 */ + /* READ DMA*/ + /* in case that we can't fit the transfer length, + we need to make it fit by sending multiple ATA cmnds */ + TI_DBG5(("satRead10: case 2\n")); + + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_DMA; /* 0xC8 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = + (bit8)((0x4 << 4) | (scsiCmnd->cdb[2] & 0xF)); /* FIS LBA (27:24) and FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + + agRequestType = AGSA_SATA_PROTOCOL_DMA_READ; + satIOContext->ATACmd = SAT_READ_DMA; + } + else + { + /* case 1 */ + /* READ MULTIPLE or READ SECTOR(S) */ + /* READ SECTORS for easier implemetation */ + /* in case that we can't fit the transfer length, + we need to make it fit by sending multiple ATA cmnds */ + TI_DBG5(("satRead10: case 1\n")); + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_SECTORS; /* 0x20 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = + (bit8)((0x4 << 4) | (scsiCmnd->cdb[2] & 0xF)); /* FIS LBA (27:24) and FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + satIOContext->ATACmd = SAT_READ_SECTORS; + } + } + + /* case 3 and 4 */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 3 */ + /* READ DMA EXT */ + TI_DBG5(("satRead10: case 3\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_DMA_EXT; /* 0x25 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[7]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_READ; + satIOContext->ATACmd = SAT_READ_DMA_EXT; + + } + else + { + /* case 4 */ + /* READ MULTIPLE EXT or READ SECTOR(S) EXT or READ VERIFY SECTOR(S) EXT*/ + /* READ SECTORS EXT for easier implemetation */ + TI_DBG5(("satRead10: case 4\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + /* Check FUA bit */ + if (scsiCmnd->cdb[1] & SCSI_READ10_FUA_MASK) + { + + /* for now, no support for FUA */ + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + + fis->h.command = SAT_READ_SECTORS_EXT; /* 0x24 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[7]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + satIOContext->ATACmd = SAT_READ_SECTORS_EXT; + } + } + + /* case 5 */ + if (pSatDevData->satNCQ == agTRUE) + { + /* READ FPDMA QUEUED */ + if (pSatDevData->sat48BitSupport != agTRUE) + { + TI_DBG5(("satRead10: case 5 !!! error NCQ but 28 bit address support \n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + + TI_DBG6(("satRead10: case 5\n")); + + /* Support 48-bit FPDMA addressing, use READ FPDMA QUEUE command */ + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_FPDMA_QUEUED; /* 0x60 */ + fis->h.features = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + + /* Check FUA bit */ + if (scsiCmnd->cdb[1] & SCSI_READ10_FUA_MASK) + fis->d.device = 0xC0; /* FIS FUA set */ + else + fis->d.device = 0x40; /* FIS FUA clear */ + + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = scsiCmnd->cdb[7]; /* FIS sector count (15:8) */ + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_READ; + satIOContext->ATACmd = SAT_READ_FPDMA_QUEUED; + } + + + // tdhexdump("satRead10 final fis", (bit8 *)fis, sizeof(agsaFisRegHostToDevice_t)); + + /* saves the current LBA and orginal TL */ + satIOContext->currentLBA = lba; + satIOContext->OrgTL = tl; + + /* + computing number of loop and remainder for tl + 0xFF in case not ext + 0xFFFF in case EXT + */ + if (fis->h.command == SAT_READ_SECTORS || fis->h.command == SAT_READ_DMA) + { + LoopNum = satComputeLoopNum(tl, 0xFF); + } + else if (fis->h.command == SAT_READ_SECTORS_EXT || fis->h.command == SAT_READ_DMA_EXT) + { + /* SAT_READ_SECTORS_EXT, SAT_READ_DMA_EXT */ + LoopNum = satComputeLoopNum(tl, 0xFFFF); + } + else + { + /* SAT_READ_FPDMA_QUEUED */ + LoopNum = satComputeLoopNum(tl, 0xFFFF); + } + + satIOContext->LoopNum = LoopNum; + + /* Initialize CB for SATA completion. + */ + if (LoopNum == 1) + { + TI_DBG5(("satRead10: NON CHAINED data\n")); + satIOContext->satCompleteCB = &satNonChainedDataIOCB; + } + else + { + TI_DBG1(("satRead10: CHAINED data\n")); + /* re-setting tl */ + if (fis->h.command == SAT_READ_SECTORS || fis->h.command == SAT_READ_DMA) + { + fis->d.sectorCount = 0xFF; + } + else if (fis->h.command == SAT_READ_SECTORS_EXT || fis->h.command == SAT_READ_DMA_EXT) + { + /* SAT_READ_SECTORS_EXT, SAT_READ_DMA_EXT */ + fis->d.sectorCount = 0xFF; + fis->d.sectorCountExp = 0xFF; + } + else + { + /* SAT_READ_FPDMA_QUEUED */ + fis->h.features = 0xFF; + fis->d.featuresExp = 0xFF; + } + + /* chained data */ + satIOContext->satCompleteCB = &satChainedDataIOCB; + + } + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + TI_DBG5(("satRead10: return\n")); + return (status); + +} + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satRead_1. + * + * SAT implementation for SCSI satRead_1 + * Sub function of satRead10 + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +/* + * as a part of loop for read10 + */ +GLOBAL bit32 satRead_1( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + /* + Assumption: error check on lba and tl has been done in satRead*() + lba = lba + tl; + */ + bit32 status; + satIOContext_t *satOrgIOContext = agNULL; + tiIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 agRequestType = AGSA_SATA_PROTOCOL_DMA_READ; + bit32 lba = 0; + bit32 DenomTL = 0xFF; + bit32 Remainder = 0; + bit8 LBA[4]; /* 0 MSB, 3 LSB */ + + TI_DBG2(("satRead_1: start\n")); + + fis = satIOContext->pFis; + satOrgIOContext = satIOContext->satOrgIOContext; + scsiCmnd = satOrgIOContext->pScsiCmnd; + + osti_memset(LBA,0, sizeof(LBA)); + + switch (satOrgIOContext->ATACmd) + { + case SAT_READ_DMA: + DenomTL = 0xFF; + break; + case SAT_READ_SECTORS: + DenomTL = 0xFF; + break; + case SAT_READ_DMA_EXT: + DenomTL = 0xFFFF; + break; + case SAT_READ_SECTORS_EXT: + DenomTL = 0xFFFF; + break; + case SAT_READ_FPDMA_QUEUED: + DenomTL = 0xFFFF; + break; + default: + TI_DBG1(("satRead_1: error incorrect ata command 0x%x\n", satIOContext->ATACmd)); + return tiError; + break; + } + + Remainder = satOrgIOContext->OrgTL % DenomTL; + satOrgIOContext->currentLBA = satOrgIOContext->currentLBA + DenomTL; + lba = satOrgIOContext->currentLBA; + + LBA[0] = (bit8)((lba & 0xF000) >> (8 * 3)); + LBA[1] = (bit8)((lba & 0xF00) >> (8 * 2)); + LBA[2] = (bit8)((lba & 0xF0) >> 8); + LBA[3] = (bit8)(lba & 0xF); + + + switch (satOrgIOContext->ATACmd) + { + case SAT_READ_DMA: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_DMA; /* 0xC8 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + fis->d.device = + (bit8)((0x4 << 4) | (LBA[0] & 0xF)); /* FIS LBA (27:24) and FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->d.sectorCount = (bit8)Remainder; /* FIS sector count (7:0) */ + } + else + { + fis->d.sectorCount = 0xFF; /* FIS sector count (7:0) */ + } + + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_READ; + + break; + case SAT_READ_SECTORS: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_SECTORS; /* 0x20 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + fis->d.device = + (bit8)((0x4 << 4) | (LBA[0] & 0xF)); /* FIS LBA (27:24) and FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->d.sectorCount = (bit8)Remainder; /* FIS sector count (7:0) */ + } + else + { + fis->d.sectorCount = 0xFF; /* FIS sector count (7:0) */ + } + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + + break; + case SAT_READ_DMA_EXT: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_DMA_EXT; /* 0x25 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = LBA[0]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->d.sectorCount = (bit8)(Remainder & 0xFF); /* FIS sector count (7:0) */ + fis->d.sectorCountExp = (bit8)((Remainder & 0xFF00) >> 8); /* FIS sector count (15:8) */ + + } + else + { + fis->d.sectorCount = 0xFF; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0xFF; /* FIS sector count (15:8) */ + } + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_READ; + + break; + case SAT_READ_SECTORS_EXT: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_SECTORS_EXT; /* 0x24 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = LBA[0]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->d.sectorCount = (bit8)(Remainder & 0xFF); /* FIS sector count (7:0) */ + fis->d.sectorCountExp = (bit8)((Remainder & 0xFF00) >> 8); /* FIS sector count (15:8) */ + } + else + { + fis->d.sectorCount = 0xFF; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0xFF; /* FIS sector count (15:8) */ + } + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + break; + case SAT_READ_FPDMA_QUEUED: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_FPDMA_QUEUED; /* 0x60 */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + + /* Check FUA bit */ + if (scsiCmnd->cdb[1] & SCSI_READ10_FUA_MASK) + fis->d.device = 0xC0; /* FIS FUA set */ + else + fis->d.device = 0x40; /* FIS FUA clear */ + + fis->d.lbaLowExp = LBA[0]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->h.features = (bit8)(Remainder & 0xFF); /* FIS sector count (7:0) */ + fis->d.featuresExp = (bit8)((Remainder & 0xFF00) >> 8); /* FIS sector count (15:8) */ + } + else + { + fis->h.features = 0xFF; /* FIS sector count (7:0) */ + fis->d.featuresExp = 0xFF; /* FIS sector count (15:8) */ + } + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_READ; + break; + default: + TI_DBG1(("satRead_1: error incorrect ata command 0x%x\n", satIOContext->ATACmd)); + return tiError; + break; + } + + /* Initialize CB for SATA completion. + */ + /* chained data */ + satIOContext->satCompleteCB = &satChainedDataIOCB; + + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + TI_DBG5(("satRead_1: return\n")); + return (status); +} +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI READ12. + * + * SAT implementation for SCSI READ12 and send FIS request to LL layer. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satRead12( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_DMA_READ; + satDeviceData_t *pSatDevData; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 lba = 0; + bit32 tl = 0; + bit32 LoopNum = 1; + bit8 LBA[4]; + bit8 TL[4]; + bit32 rangeChk = agFALSE; /* lba and tl range check */ + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &tiScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + TI_DBG5(("satRead12: start\n")); + + /* checking FUA_NV */ + if (scsiCmnd->cdb[1] & SCSI_FUA_NV_MASK) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satRead12: return FUA_NV\n")); + return tiSuccess; + + } + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[11] & SCSI_NACA_MASK) || (scsiCmnd->cdb[11] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG2(("satRead12: return control\n")); + return tiSuccess; + } + + osti_memset(LBA, 0, sizeof(LBA)); + osti_memset(TL, 0, sizeof(TL)); + + /* do not use memcpy due to indexing in LBA and TL */ + LBA[0] = scsiCmnd->cdb[2]; /* MSB */ + LBA[1] = scsiCmnd->cdb[3]; + LBA[2] = scsiCmnd->cdb[4]; + LBA[3] = scsiCmnd->cdb[5]; /* LSB */ + + TL[0] = scsiCmnd->cdb[6]; /* MSB */ + TL[1] = scsiCmnd->cdb[7]; + TL[2] = scsiCmnd->cdb[8]; + TL[3] = scsiCmnd->cdb[9]; /* LSB */ + + rangeChk = satAddNComparebit32(LBA, TL); + + lba = satComputeCDB12LBA(satIOContext); + tl = satComputeCDB12TL(satIOContext); + + /* Table 34, 9.1, p 46 */ + /* + note: As of 2/10/2006, no support for DMA QUEUED + */ + + /* + Table 34, 9.1, p 46, b + When no 48-bit addressing support or NCQ, if LBA is beyond (2^28 - 1), + return check condition + */ + if (pSatDevData->satNCQ != agTRUE && + pSatDevData->sat48BitSupport != agTRUE + ) + { + if (lba > SAT_TR_LBA_LIMIT - 1) + { + TI_DBG1(("satRead12: return LBA out of range, not EXT\n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + return tiSuccess; + } + if (rangeChk) // if (lba + tl > SAT_TR_LBA_LIMIT) + { + TI_DBG1(("satRead12: return LBA+TL out of range, not EXT\n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + return tiSuccess; + } + } + + /* case 1 and 2 */ + if (!rangeChk) // if (lba + tl <= SAT_TR_LBA_LIMIT) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 2 */ + /* READ DMA*/ + /* in case that we can't fit the transfer length, + we need to make it fit by sending multiple ATA cmnds */ + TI_DBG5(("satRead12: case 2\n")); + + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_DMA; /* 0xC8 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = + (bit8)((0x4 << 4) | (scsiCmnd->cdb[2] & 0xF)); /* FIS LBA (27:24) and FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[9]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + + agRequestType = AGSA_SATA_PROTOCOL_DMA_READ; + satIOContext->ATACmd = SAT_READ_DMA; + } + else + { + /* case 1 */ + /* READ MULTIPLE or READ SECTOR(S) */ + /* READ SECTORS for easier implemetation */ + /* can't fit the transfer length but need to make it fit by sending multiple*/ + TI_DBG5(("satRead12: case 1\n")); + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_SECTORS; /* 0x20 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = + (bit8)((0x4 << 4) | (scsiCmnd->cdb[2] & 0xF)); /* FIS LBA (27:24) and FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[9]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + satIOContext->ATACmd = SAT_READ_SECTORS; + } + } + + /* case 3 and 4 */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 3 */ + /* READ DMA EXT */ + TI_DBG5(("satRead12: case 3\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_DMA_EXT; /* 0x25 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[9]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[8]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_READ; + satIOContext->ATACmd = SAT_READ_DMA_EXT; + + } + else + { + /* case 4 */ + /* READ MULTIPLE EXT or READ SECTOR(S) EXT or READ VERIFY SECTOR(S) EXT*/ + /* READ SECTORS EXT for easier implemetation */ + TI_DBG5(("satRead12: case 4\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + /* Check FUA bit */ + if (scsiCmnd->cdb[1] & SCSI_READ12_FUA_MASK) + { + /* for now, no support for FUA */ + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + + fis->h.command = SAT_READ_SECTORS_EXT; /* 0x24 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[9]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[8]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + satIOContext->ATACmd = SAT_READ_SECTORS_EXT; + } + } + + /* case 5 */ + if (pSatDevData->satNCQ == agTRUE) + { + /* READ FPDMA QUEUED */ + if (pSatDevData->sat48BitSupport != agTRUE) + { + TI_DBG5(("satRead12: case 5 !!! error NCQ but 28 bit address support \n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + + TI_DBG6(("satRead12: case 5\n")); + + /* Support 48-bit FPDMA addressing, use READ FPDMA QUEUE command */ + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_FPDMA_QUEUED; /* 0x60 */ + fis->h.features = scsiCmnd->cdb[9]; /* FIS sector count (7:0) */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + + /* Check FUA bit */ + if (scsiCmnd->cdb[1] & SCSI_READ12_FUA_MASK) + fis->d.device = 0xC0; /* FIS FUA set */ + else + fis->d.device = 0x40; /* FIS FUA clear */ + + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = scsiCmnd->cdb[8]; /* FIS sector count (15:8) */ + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_READ; + satIOContext->ATACmd = SAT_READ_FPDMA_QUEUED; + } + + /* saves the current LBA and orginal TL */ + satIOContext->currentLBA = lba; + satIOContext->OrgTL = tl; + + /* + computing number of loop and remainder for tl + 0xFF in case not ext + 0xFFFF in case EXT + */ + if (fis->h.command == SAT_READ_SECTORS || fis->h.command == SAT_READ_DMA) + { + LoopNum = satComputeLoopNum(tl, 0xFF); + } + else if (fis->h.command == SAT_READ_SECTORS_EXT || fis->h.command == SAT_READ_DMA_EXT) + { + /* SAT_READ_SECTORS_EXT, SAT_READ_DMA_EXT */ + LoopNum = satComputeLoopNum(tl, 0xFFFF); + } + else + { + /* SAT_READ_FPDMA_QUEUEDK */ + LoopNum = satComputeLoopNum(tl, 0xFFFF); + } + + satIOContext->LoopNum = LoopNum; + + if (LoopNum == 1) + { + TI_DBG5(("satRead12: NON CHAINED data\n")); + satIOContext->satCompleteCB = &satNonChainedDataIOCB; + } + else + { + TI_DBG1(("satRead12: CHAINED data\n")); + /* re-setting tl */ + if (fis->h.command == SAT_READ_SECTORS || fis->h.command == SAT_READ_DMA) + { + fis->d.sectorCount = 0xFF; + } + else if (fis->h.command == SAT_READ_SECTORS_EXT || fis->h.command == SAT_READ_DMA_EXT) + { + /* SAT_READ_SECTORS_EXT, SAT_READ_DMA_EXT */ + fis->d.sectorCount = 0xFF; + fis->d.sectorCountExp = 0xFF; + } + else + { + /* SAT_READ_FPDMA_QUEUED */ + fis->h.features = 0xFF; + fis->d.featuresExp = 0xFF; + } + + /* chained data */ + satIOContext->satCompleteCB = &satChainedDataIOCB; + } + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + TI_DBG5(("satRead12: return\n")); + return (status); +} +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI READ16. + * + * SAT implementation for SCSI READ16 and send FIS request to LL layer. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satRead16( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_DMA_READ; + satDeviceData_t *pSatDevData; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 lba = 0; + bit32 tl = 0; + bit32 LoopNum = 1; + bit8 LBA[8]; + bit8 TL[8]; + bit32 rangeChk = agFALSE; /* lba and tl range check */ + bit32 limitChk = agFALSE; /* lba and tl range check */ + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &tiScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + TI_DBG5(("satRead16: start\n")); + + /* checking FUA_NV */ + if (scsiCmnd->cdb[1] & SCSI_FUA_NV_MASK) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satRead16: return FUA_NV\n")); + return tiSuccess; + + } + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[15] & SCSI_NACA_MASK) || (scsiCmnd->cdb[15] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satRead16: return control\n")); + return tiSuccess; + } + + + osti_memset(LBA, 0, sizeof(LBA)); + osti_memset(TL, 0, sizeof(TL)); + + + /* do not use memcpy due to indexing in LBA and TL */ + LBA[0] = scsiCmnd->cdb[2]; /* MSB */ + LBA[1] = scsiCmnd->cdb[3]; + LBA[2] = scsiCmnd->cdb[4]; + LBA[3] = scsiCmnd->cdb[5]; + LBA[4] = scsiCmnd->cdb[6]; + LBA[5] = scsiCmnd->cdb[7]; + LBA[6] = scsiCmnd->cdb[8]; + LBA[7] = scsiCmnd->cdb[9]; /* LSB */ + + TL[0] = 0; + TL[1] = 0; + TL[2] = 0; + TL[3] = 0; + TL[4] = scsiCmnd->cdb[10]; /* MSB */ + TL[5] = scsiCmnd->cdb[11]; + TL[6] = scsiCmnd->cdb[12]; + TL[7] = scsiCmnd->cdb[13]; /* LSB */ + + rangeChk = satAddNComparebit64(LBA, TL); + + limitChk = satCompareLBALimitbit(LBA); + + lba = satComputeCDB16LBA(satIOContext); + tl = satComputeCDB16TL(satIOContext); + + + /* Table 34, 9.1, p 46 */ + /* + note: As of 2/10/2006, no support for DMA QUEUED + */ + + /* + Table 34, 9.1, p 46, b + When no 48-bit addressing support or NCQ, if LBA is beyond (2^28 - 1), + return check condition + */ + if (pSatDevData->satNCQ != agTRUE && + pSatDevData->sat48BitSupport != agTRUE + ) + { + if (limitChk) + { + TI_DBG1(("satRead16: return LBA out of range, not EXT\n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + return tiSuccess; + } + if (rangeChk) // if (lba + tl > SAT_TR_LBA_LIMIT) + { + TI_DBG1(("satRead16: return LBA+TL out of range, not EXT\n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + return tiSuccess; + } + } + + /* case 1 and 2 */ + if (!rangeChk) // if (lba + tl <= SAT_TR_LBA_LIMIT) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 2 */ + /* READ DMA*/ + /* in case that we can't fit the transfer length, + we need to make it fit by sending multiple ATA cmnds */ + TI_DBG5(("satRead16: case 2\n")); + + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_DMA; /* 0xC8 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[9]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[8]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[7]; /* FIS LBA (23:16) */ + fis->d.device = + (bit8)((0x4 << 4) | (scsiCmnd->cdb[6] & 0xF)); /* FIS LBA (27:24) and FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[13]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + + agRequestType = AGSA_SATA_PROTOCOL_DMA_READ; + satIOContext->ATACmd = SAT_READ_DMA; + } + else + { + /* case 1 */ + /* READ MULTIPLE or READ SECTOR(S) */ + /* READ SECTORS for easier implemetation */ + /* can't fit the transfer length but need to make it fit by sending multiple*/ + TI_DBG5(("satRead16: case 1\n")); + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_SECTORS; /* 0x20 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[9]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[8]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[7]; /* FIS LBA (23:16) */ + fis->d.device = + (bit8)((0x4 << 4) | (scsiCmnd->cdb[6] & 0xF)); /* FIS LBA (27:24) and FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[13]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + satIOContext->ATACmd = SAT_READ_SECTORS; + } + } + + /* case 3 and 4 */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 3 */ + /* READ DMA EXT */ + TI_DBG5(("satRead16: case 3\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_DMA_EXT; /* 0x25 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[9]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[8]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[7]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[6]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = scsiCmnd->cdb[5]; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = scsiCmnd->cdb[4]; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[13]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[12]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_READ; + satIOContext->ATACmd = SAT_READ_DMA_EXT; + + } + else + { + /* case 4 */ + /* READ MULTIPLE EXT or READ SECTOR(S) EXT or READ VERIFY SECTOR(S) EXT*/ + /* READ SECTORS EXT for easier implemetation */ + TI_DBG5(("satRead16: case 4\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + /* Check FUA bit */ + if (scsiCmnd->cdb[1] & SCSI_READ16_FUA_MASK) + { + + /* for now, no support for FUA */ + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + + fis->h.command = SAT_READ_SECTORS_EXT; /* 0x24 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[9]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[8]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[7]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[6]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = scsiCmnd->cdb[5]; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = scsiCmnd->cdb[4]; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[13]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[12]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + satIOContext->ATACmd = SAT_READ_SECTORS_EXT; + } + } + + + /* case 5 */ + if (pSatDevData->satNCQ == agTRUE) + { + /* READ FPDMA QUEUED */ + if (pSatDevData->sat48BitSupport != agTRUE) + { + TI_DBG5(("satRead16: case 5 !!! error NCQ but 28 bit address support \n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + + TI_DBG6(("satRead16: case 5\n")); + + /* Support 48-bit FPDMA addressing, use READ FPDMA QUEUE command */ + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_FPDMA_QUEUED; /* 0x60 */ + fis->h.features = scsiCmnd->cdb[13]; /* FIS sector count (7:0) */ + fis->d.lbaLow = scsiCmnd->cdb[9]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[8]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[7]; /* FIS LBA (23:16) */ + + /* Check FUA bit */ + if (scsiCmnd->cdb[1] & SCSI_READ16_FUA_MASK) + fis->d.device = 0xC0; /* FIS FUA set */ + else + fis->d.device = 0x40; /* FIS FUA clear */ + + fis->d.lbaLowExp = scsiCmnd->cdb[6]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = scsiCmnd->cdb[5]; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = scsiCmnd->cdb[4]; /* FIS LBA (47:40) */ + fis->d.featuresExp = scsiCmnd->cdb[12]; /* FIS sector count (15:8) */ + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_READ; + satIOContext->ATACmd = SAT_READ_FPDMA_QUEUED; + } + + /* saves the current LBA and orginal TL */ + satIOContext->currentLBA = lba; + satIOContext->OrgTL = tl; + + /* + computing number of loop and remainder for tl + 0xFF in case not ext + 0xFFFF in case EXT + */ + if (fis->h.command == SAT_READ_SECTORS || fis->h.command == SAT_READ_DMA) + { + LoopNum = satComputeLoopNum(tl, 0xFF); + } + else if (fis->h.command == SAT_READ_SECTORS_EXT || fis->h.command == SAT_READ_DMA_EXT) + { + /* SAT_READ_SECTORS_EXT, SAT_READ_DMA_EXT */ + LoopNum = satComputeLoopNum(tl, 0xFFFF); + } + else + { + /* SAT_READ_FPDMA_QUEUEDK */ + LoopNum = satComputeLoopNum(tl, 0xFFFF); + } + satIOContext->LoopNum = LoopNum; + + if (LoopNum == 1) + { + TI_DBG5(("satRead16: NON CHAINED data\n")); + satIOContext->satCompleteCB = &satNonChainedDataIOCB; + } + else + { + TI_DBG1(("satRead16: CHAINED data\n")); + /* re-setting tl */ + if (fis->h.command == SAT_READ_SECTORS || fis->h.command == SAT_READ_DMA) + { + fis->d.sectorCount = 0xFF; + } + else if (fis->h.command == SAT_READ_SECTORS_EXT || fis->h.command == SAT_READ_DMA_EXT) + { + /* SAT_READ_SECTORS_EXT, SAT_READ_DMA_EXT */ + fis->d.sectorCount = 0xFF; + fis->d.sectorCountExp = 0xFF; + } + else + { + /* SAT_READ_FPDMA_QUEUED */ + fis->h.features = 0xFF; + fis->d.featuresExp = 0xFF; + } + + /* chained data */ + satIOContext->satCompleteCB = &satChainedDataIOCB; + } + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + TI_DBG5(("satRead16: return\n")); + return (status); + +} + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI READ6. + * + * SAT implementation for SCSI READ6 and send FIS request to LL layer. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satRead6( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_DMA_READ; + satDeviceData_t *pSatDevData; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 lba = 0; + bit16 tl = 0; + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &tiScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + + TI_DBG5(("satRead6: start\n")); + + /* no FUA checking since read6 */ + + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[5] & SCSI_NACA_MASK) || (scsiCmnd->cdb[5] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG2(("satRead6: return control\n")); + return tiSuccess; + } + + /* cbd6; computing LBA and transfer length */ + lba = (((scsiCmnd->cdb[1]) & 0x1f) << (8*2)) + + (scsiCmnd->cdb[2] << 8) + scsiCmnd->cdb[3]; + tl = scsiCmnd->cdb[4]; + + + /* Table 34, 9.1, p 46 */ + /* + note: As of 2/10/2006, no support for DMA QUEUED + */ + + /* + Table 34, 9.1, p 46, b + When no 48-bit addressing support or NCQ, if LBA is beyond (2^28 - 1), + return check condition + */ + if (pSatDevData->satNCQ != agTRUE && + pSatDevData->sat48BitSupport != agTRUE + ) + { + if (lba > SAT_TR_LBA_LIMIT - 1) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satRead6: return LBA out of range\n")); + return tiSuccess; + } + } + + /* case 1 and 2 */ + if (lba + tl <= SAT_TR_LBA_LIMIT) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 2 */ + /* READ DMA*/ + TI_DBG5(("satRead6: case 2\n")); + + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_DMA; /* 0xC8 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = (bit8)((scsiCmnd->cdb[1]) & 0x1f); /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + if (tl == 0) + { + /* temporary fix */ + fis->d.sectorCount = 0xff; /* FIS sector count (7:0) */ + } + else + { + fis->d.sectorCount = scsiCmnd->cdb[4]; /* FIS sector count (7:0) */ + } + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_READ; + } + else + { + /* case 1 */ + /* READ SECTORS for easier implemetation */ + TI_DBG5(("satRead6: case 1\n")); + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_SECTORS; /* 0x20 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = (bit8)((scsiCmnd->cdb[1]) & 0x1f); /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + if (tl == 0) + { + /* temporary fix */ + fis->d.sectorCount = 0xff; /* FIS sector count (7:0) */ + } + else + { + fis->d.sectorCount = scsiCmnd->cdb[4]; /* FIS sector count (7:0) */ + } + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + + } + } + + /* case 3 and 4 */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 3 */ + /* READ DMA EXT only */ + TI_DBG5(("satRead6: case 3\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_DMA_EXT; /* 0x25 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = (bit8)((scsiCmnd->cdb[1]) & 0x1f); /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = 0; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + if (tl == 0) + { + /* sector count is 256, 0x100*/ + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0x01; /* FIS sector count (15:8) */ + } + else + { + fis->d.sectorCount = scsiCmnd->cdb[4]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + } + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_READ; + } + else + { + /* case 4 */ + /* READ SECTORS EXT for easier implemetation */ + TI_DBG5(("satRead6: case 4\n")); + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_SECTORS_EXT; /* 0x24 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = (bit8)((scsiCmnd->cdb[1]) & 0x1f); /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = 0; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + if (tl == 0) + { + /* sector count is 256, 0x100*/ + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0x01; /* FIS sector count (15:8) */ + } + else + { + fis->d.sectorCount = scsiCmnd->cdb[4]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + } + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + } + } + + /* case 5 */ + if (pSatDevData->satNCQ == agTRUE) + { + /* READ FPDMA QUEUED */ + if (pSatDevData->sat48BitSupport != agTRUE) + { + /* sanity check */ + TI_DBG5(("satRead6: case 5 !!! error NCQ but 28 bit address support \n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + TI_DBG5(("satRead6: case 5\n")); + + /* Support 48-bit FPDMA addressing, use READ FPDMA QUEUE command */ + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_FPDMA_QUEUED; /* 0x60 */ + fis->d.lbaLow = scsiCmnd->cdb[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = (bit8)((scsiCmnd->cdb[1]) & 0x1f); /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS FUA clear */ + fis->d.lbaLowExp = 0; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + if (tl == 0) + { + /* sector count is 256, 0x100*/ + fis->h.features = 0; /* FIS sector count (7:0) */ + fis->d.featuresExp = 0x01; /* FIS sector count (15:8) */ + } + else + { + fis->h.features = scsiCmnd->cdb[4]; /* FIS sector count (7:0) */ + fis->d.featuresExp = 0; /* FIS sector count (15:8) */ + } + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_READ; + } + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satNonChainedDataIOCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + return (status); + +} + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI WRITE16. + * + * SAT implementation for SCSI WRITE16 and send FIS request to LL layer. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satWrite16( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satDeviceData_t *pSatDevData; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 lba = 0; + bit32 tl = 0; + bit32 LoopNum = 1; + bit8 LBA[8]; + bit8 TL[8]; + bit32 rangeChk = agFALSE; /* lba and tl range check */ + bit32 limitChk = agFALSE; /* lba and tl range check */ + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &tiScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + TI_DBG5(("satWrite16: start\n")); + + /* checking FUA_NV */ + if (scsiCmnd->cdb[1] & SCSI_FUA_NV_MASK) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satWrite16: return FUA_NV\n")); + return tiSuccess; + + } + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[15] & SCSI_NACA_MASK) || (scsiCmnd->cdb[15] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satWrite16: return control\n")); + return tiSuccess; + } + + + osti_memset(LBA, 0, sizeof(LBA)); + osti_memset(TL, 0, sizeof(TL)); + + + /* do not use memcpy due to indexing in LBA and TL */ + LBA[0] = scsiCmnd->cdb[2]; /* MSB */ + LBA[1] = scsiCmnd->cdb[3]; + LBA[2] = scsiCmnd->cdb[4]; + LBA[3] = scsiCmnd->cdb[5]; + LBA[4] = scsiCmnd->cdb[6]; + LBA[5] = scsiCmnd->cdb[7]; + LBA[6] = scsiCmnd->cdb[8]; + LBA[7] = scsiCmnd->cdb[9]; /* LSB */ + + TL[0] = 0; + TL[1] = 0; + TL[2] = 0; + TL[3] = 0; + TL[4] = scsiCmnd->cdb[10]; /* MSB */ + TL[5] = scsiCmnd->cdb[11]; + TL[6] = scsiCmnd->cdb[12]; + TL[7] = scsiCmnd->cdb[13]; /* LSB */ + + rangeChk = satAddNComparebit64(LBA, TL); + + limitChk = satCompareLBALimitbit(LBA); + + lba = satComputeCDB16LBA(satIOContext); + tl = satComputeCDB16TL(satIOContext); + + + + /* Table 34, 9.1, p 46 */ + /* + note: As of 2/10/2006, no support for DMA QUEUED + */ + + /* + Table 34, 9.1, p 46, b + When no 48-bit addressing support or NCQ, if LBA is beyond (2^28 - 1), + return check condition + */ + if (pSatDevData->satNCQ != agTRUE && + pSatDevData->sat48BitSupport != agTRUE + ) + { + if (limitChk) + { + TI_DBG1(("satWrite16: return LBA out of range, not EXT\n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + return tiSuccess; + } + if (rangeChk) // if (lba + tl > SAT_TR_LBA_LIMIT) + { + TI_DBG1(("satWrite16: return LBA+TL out of range, not EXT\n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + return tiSuccess; + } + } + + /* case 1 and 2 */ + if (!rangeChk) // if (lba + tl <= SAT_TR_LBA_LIMIT) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 2 */ + /* WRITE DMA*/ + /* In case that we can't fit the transfer length, we loop */ + TI_DBG5(("satWrite16: case 2\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_DMA; /* 0xCA */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[9]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[8]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[7]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (scsiCmnd->cdb[6] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[13]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_DMA; + } + else + { + /* case 1 */ + /* WRITE MULTIPLE or WRITE SECTOR(S) */ + /* WRITE SECTORS for easier implemetation */ + /* In case that we can't fit the transfer length, we loop */ + TI_DBG5(("satWrite16: case 1\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_SECTORS; /* 0x30 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[9]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[8]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[7]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (scsiCmnd->cdb[6] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[13]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + satIOContext->ATACmd = SAT_WRITE_SECTORS; + } + } + + /* case 3 and 4 */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 3 */ + /* WRITE DMA EXT or WRITE DMA FUA EXT */ + TI_DBG5(("satWrite16: case 3\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + /* SAT_WRITE_DMA_FUA_EXT is optional and we don't support it */ + fis->h.command = SAT_WRITE_DMA_EXT; /* 0x35 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[9]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[8]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[7]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[6]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = scsiCmnd->cdb[5]; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = scsiCmnd->cdb[4]; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[13]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[12]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_DMA_EXT; + } + else + { + /* case 4 */ + /* WRITE MULTIPLE EXT or WRITE MULTIPLE FUA EXT or WRITE SECTOR(S) EXT */ + /* WRITE SECTORS EXT for easier implemetation */ + TI_DBG5(("satWrite16: case 4\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_SECTORS_EXT; /* 0x34 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[9]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[8]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[7]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[6]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = scsiCmnd->cdb[5]; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = scsiCmnd->cdb[4]; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[13]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[12]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + satIOContext->ATACmd = SAT_WRITE_SECTORS_EXT; + } + } + + /* case 5 */ + if (pSatDevData->satNCQ == agTRUE) + { + /* WRITE FPDMA QUEUED */ + if (pSatDevData->sat48BitSupport != agTRUE) + { + TI_DBG5(("satWrite16: case 5 !!! error NCQ but 28 bit address support \n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + TI_DBG6(("satWrite16: case 5\n")); + + /* Support 48-bit FPDMA addressing, use WRITE FPDMA QUEUE command */ + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_FPDMA_QUEUED; /* 0x61 */ + fis->h.features = scsiCmnd->cdb[13]; /* FIS sector count (7:0) */ + fis->d.lbaLow = scsiCmnd->cdb[9]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[8]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[7]; /* FIS LBA (23:16) */ + + /* Check FUA bit */ + if (scsiCmnd->cdb[1] & SCSI_WRITE16_FUA_MASK) + fis->d.device = 0xC0; /* FIS FUA set */ + else + fis->d.device = 0x40; /* FIS FUA clear */ + + fis->d.lbaLowExp = scsiCmnd->cdb[6]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = scsiCmnd->cdb[5]; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = scsiCmnd->cdb[4]; /* FIS LBA (47:40) */ + fis->d.featuresExp = scsiCmnd->cdb[12]; /* FIS sector count (15:8) */ + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_FPDMA_QUEUED; + } + + satIOContext->currentLBA = lba; + satIOContext->OrgTL = tl; + + /* + computing number of loop and remainder for tl + 0xFF in case not ext + 0xFFFF in case EXT + */ + if (fis->h.command == SAT_WRITE_SECTORS || fis->h.command == SAT_WRITE_DMA) + { + LoopNum = satComputeLoopNum(tl, 0xFF); + } + else if (fis->h.command == SAT_WRITE_SECTORS_EXT || + fis->h.command == SAT_WRITE_DMA_EXT || + fis->h.command == SAT_WRITE_DMA_FUA_EXT + ) + { + /* SAT_READ_SECTORS_EXT, SAT_READ_DMA_EXT */ + LoopNum = satComputeLoopNum(tl, 0xFFFF); + } + else + { + /* SAT_WRITE_FPDMA_QUEUEDK */ + LoopNum = satComputeLoopNum(tl, 0xFFFF); + } + + satIOContext->LoopNum = LoopNum; + + + if (LoopNum == 1) + { + TI_DBG5(("satWrite16: NON CHAINED data\n")); + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satNonChainedDataIOCB; + } + else + { + TI_DBG1(("satWrite16: CHAINED data\n")); + /* re-setting tl */ + if (fis->h.command == SAT_WRITE_SECTORS || fis->h.command == SAT_WRITE_DMA) + { + fis->d.sectorCount = 0xFF; + } + else if (fis->h.command == SAT_WRITE_SECTORS_EXT || + fis->h.command == SAT_WRITE_DMA_EXT || + fis->h.command == SAT_WRITE_DMA_FUA_EXT + ) + { + fis->d.sectorCount = 0xFF; + fis->d.sectorCountExp = 0xFF; + } + else + { + /* SAT_WRITE_FPDMA_QUEUED */ + fis->h.features = 0xFF; + fis->d.featuresExp = 0xFF; + } + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satChainedDataIOCB; + } + + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + return (status); +} + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI WRITE12. + * + * SAT implementation for SCSI WRITE12 and send FIS request to LL layer. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satWrite12( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satDeviceData_t *pSatDevData; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 lba = 0; + bit32 tl = 0; + bit32 LoopNum = 1; + bit8 LBA[4]; + bit8 TL[4]; + bit32 rangeChk = agFALSE; /* lba and tl range check */ + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &tiScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + TI_DBG5(("satWrite12: start\n")); + + /* checking FUA_NV */ + if (scsiCmnd->cdb[1] & SCSI_FUA_NV_MASK) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satWrite12: return FUA_NV\n")); + return tiSuccess; + + } + + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[11] & SCSI_NACA_MASK) || (scsiCmnd->cdb[11] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satWrite12: return control\n")); + return tiSuccess; + } + + + osti_memset(LBA, 0, sizeof(LBA)); + osti_memset(TL, 0, sizeof(TL)); + + /* do not use memcpy due to indexing in LBA and TL */ + LBA[0] = scsiCmnd->cdb[2]; /* MSB */ + LBA[1] = scsiCmnd->cdb[3]; + LBA[2] = scsiCmnd->cdb[4]; + LBA[3] = scsiCmnd->cdb[5]; /* LSB */ + + TL[0] = scsiCmnd->cdb[6]; /* MSB */ + TL[1] = scsiCmnd->cdb[7]; + TL[2] = scsiCmnd->cdb[8]; + TL[3] = scsiCmnd->cdb[9]; /* LSB */ + + rangeChk = satAddNComparebit32(LBA, TL); + + lba = satComputeCDB12LBA(satIOContext); + tl = satComputeCDB12TL(satIOContext); + + + /* Table 34, 9.1, p 46 */ + /* + note: As of 2/10/2006, no support for DMA QUEUED + */ + + /* + Table 34, 9.1, p 46, b + When no 48-bit addressing support or NCQ, if LBA is beyond (2^28 - 1), + return check condition + */ + if (pSatDevData->satNCQ != agTRUE && + pSatDevData->sat48BitSupport != agTRUE + ) + { + if (lba > SAT_TR_LBA_LIMIT - 1) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satWrite12: return LBA out of range, not EXT\n")); + return tiSuccess; + } + + if (rangeChk) // if (lba + tl > SAT_TR_LBA_LIMIT) + { + TI_DBG1(("satWrite12: return LBA+TL out of range, not EXT\n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + return tiSuccess; + } + } + + + /* case 1 and 2 */ + if (!rangeChk) // if (lba + tl <= SAT_TR_LBA_LIMIT) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 2 */ + /* WRITE DMA*/ + /* In case that we can't fit the transfer length, we loop */ + TI_DBG5(("satWrite12: case 2\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_DMA; /* 0xCA */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (scsiCmnd->cdb[2] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[9]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_DMA; + } + else + { + /* case 1 */ + /* WRITE MULTIPLE or WRITE SECTOR(S) */ + /* WRITE SECTORS for easier implemetation */ + /* In case that we can't fit the transfer length, we loop */ + TI_DBG5(("satWrite12: case 1\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_SECTORS; /* 0x30 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (scsiCmnd->cdb[2] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[9]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + satIOContext->ATACmd = SAT_WRITE_SECTORS; + } + } + + /* case 3 and 4 */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 3 */ + /* WRITE DMA EXT or WRITE DMA FUA EXT */ + TI_DBG5(("satWrite12: case 3\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + /* SAT_WRITE_DMA_FUA_EXT is optional and we don't support it */ + fis->h.command = SAT_WRITE_DMA_EXT; /* 0x35 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[9]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[8]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_DMA_EXT; + } + else + { + /* case 4 */ + /* WRITE MULTIPLE EXT or WRITE MULTIPLE FUA EXT or WRITE SECTOR(S) EXT */ + /* WRITE SECTORS EXT for easier implemetation */ + TI_DBG5(("satWrite12: case 4\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_SECTORS_EXT; /* 0x34 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[9]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[8]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + satIOContext->ATACmd = SAT_WRITE_SECTORS_EXT; + } + } + + /* case 5 */ + if (pSatDevData->satNCQ == agTRUE) + { + /* WRITE FPDMA QUEUED */ + if (pSatDevData->sat48BitSupport != agTRUE) + { + TI_DBG5(("satWrite12: case 5 !!! error NCQ but 28 bit address support \n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + TI_DBG6(("satWrite12: case 5\n")); + + /* Support 48-bit FPDMA addressing, use WRITE FPDMA QUEUE command */ + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_FPDMA_QUEUED; /* 0x61 */ + fis->h.features = scsiCmnd->cdb[9]; /* FIS sector count (7:0) */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + + /* Check FUA bit */ + if (scsiCmnd->cdb[1] & SCSI_WRITE12_FUA_MASK) + fis->d.device = 0xC0; /* FIS FUA set */ + else + fis->d.device = 0x40; /* FIS FUA clear */ + + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = scsiCmnd->cdb[8]; /* FIS sector count (15:8) */ + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_FPDMA_QUEUED; + } + + satIOContext->currentLBA = lba; + satIOContext->OrgTL = tl; + + /* + computing number of loop and remainder for tl + 0xFF in case not ext + 0xFFFF in case EXT + */ + if (fis->h.command == SAT_WRITE_SECTORS || fis->h.command == SAT_WRITE_DMA) + { + LoopNum = satComputeLoopNum(tl, 0xFF); + } + else if (fis->h.command == SAT_WRITE_SECTORS_EXT || + fis->h.command == SAT_WRITE_DMA_EXT || + fis->h.command == SAT_WRITE_DMA_FUA_EXT + ) + { + /* SAT_READ_SECTORS_EXT, SAT_READ_DMA_EXT */ + LoopNum = satComputeLoopNum(tl, 0xFFFF); + } + else + { + /* SAT_WRITE_FPDMA_QUEUEDK */ + LoopNum = satComputeLoopNum(tl, 0xFFFF); + } + + satIOContext->LoopNum = LoopNum; + + + if (LoopNum == 1) + { + TI_DBG5(("satWrite12: NON CHAINED data\n")); + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satNonChainedDataIOCB; + } + else + { + TI_DBG1(("satWrite12: CHAINED data\n")); + /* re-setting tl */ + if (fis->h.command == SAT_WRITE_SECTORS || fis->h.command == SAT_WRITE_DMA) + { + fis->d.sectorCount = 0xFF; + } + else if (fis->h.command == SAT_WRITE_SECTORS_EXT || + fis->h.command == SAT_WRITE_DMA_EXT || + fis->h.command == SAT_WRITE_DMA_FUA_EXT + ) + { + fis->d.sectorCount = 0xFF; + fis->d.sectorCountExp = 0xFF; + } + else + { + /* SAT_WRITE_FPDMA_QUEUED */ + fis->h.features = 0xFF; + fis->d.featuresExp = 0xFF; + } + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satChainedDataIOCB; + } + + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + return (status); +} + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI WRITE10. + * + * SAT implementation for SCSI WRITE10 and send FIS request to LL layer. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satWrite10( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satDeviceData_t *pSatDevData; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 lba = 0; + bit32 tl = 0; + bit32 LoopNum = 1; + bit8 LBA[4]; + bit8 TL[4]; + bit32 rangeChk = agFALSE; /* lba and tl range check */ + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &tiScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + TI_DBG5(("satWrite10: start\n")); + + /* checking FUA_NV */ + if (scsiCmnd->cdb[1] & SCSI_FUA_NV_MASK) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satWrite10: return FUA_NV\n")); + return tiSuccess; + + } + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[9] & SCSI_NACA_MASK) || (scsiCmnd->cdb[9] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satWrite10: return control\n")); + return tiSuccess; + } + + osti_memset(LBA, 0, sizeof(LBA)); + osti_memset(TL, 0, sizeof(TL)); + + /* do not use memcpy due to indexing in LBA and TL */ + LBA[0] = scsiCmnd->cdb[2]; /* MSB */ + LBA[1] = scsiCmnd->cdb[3]; + LBA[2] = scsiCmnd->cdb[4]; + LBA[3] = scsiCmnd->cdb[5]; /* LSB */ + + TL[0] = 0; + TL[1] = 0; + TL[2] = scsiCmnd->cdb[7]; /* MSB */ + TL[3] = scsiCmnd->cdb[8]; /* LSB */ + + rangeChk = satAddNComparebit32(LBA, TL); + + + /* cbd10; computing LBA and transfer length */ + lba = (scsiCmnd->cdb[2] << (8*3)) + (scsiCmnd->cdb[3] << (8*2)) + + (scsiCmnd->cdb[4] << 8) + scsiCmnd->cdb[5]; + tl = (scsiCmnd->cdb[7] << 8) + scsiCmnd->cdb[8]; + + TI_DBG5(("satWrite10: lba %d functioned lba %d\n", lba, satComputeCDB10LBA(satIOContext))); + TI_DBG5(("satWrite10: tl %d functioned tl %d\n", tl, satComputeCDB10TL(satIOContext))); + + /* Table 34, 9.1, p 46 */ + /* + note: As of 2/10/2006, no support for DMA QUEUED + */ + + /* + Table 34, 9.1, p 46, b + When no 48-bit addressing support or NCQ, if LBA is beyond (2^28 - 1), + return check condition + */ + if (pSatDevData->satNCQ != agTRUE && + pSatDevData->sat48BitSupport != agTRUE + ) + { + if (lba > SAT_TR_LBA_LIMIT - 1) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satWrite10: return LBA out of range, not EXT\n")); + TI_DBG1(("satWrite10: cdb 0x%x 0x%x 0x%x 0x%x\n",scsiCmnd->cdb[2], scsiCmnd->cdb[3], + scsiCmnd->cdb[4], scsiCmnd->cdb[5])); + TI_DBG1(("satWrite10: lba 0x%x SAT_TR_LBA_LIMIT 0x%x\n", lba, SAT_TR_LBA_LIMIT)); + return tiSuccess; + } + + if (rangeChk) // if (lba + tl > SAT_TR_LBA_LIMIT) + { + TI_DBG1(("satWrite10: return LBA+TL out of range, not EXT\n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + return tiSuccess; + } + + } + + + /* case 1 and 2 */ + if (!rangeChk) // if (lba + tl <= SAT_TR_LBA_LIMIT) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 2 */ + /* WRITE DMA*/ + /* can't fit the transfer length */ + TI_DBG5(("satWrite10: case 2\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_DMA; /* 0xCA */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (scsiCmnd->cdb[2] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_DMA; + } + else + { + /* case 1 */ + /* WRITE MULTIPLE or WRITE SECTOR(S) */ + /* WRITE SECTORS for easier implemetation */ + /* can't fit the transfer length */ + TI_DBG5(("satWrite10: case 1\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_SECTORS; /* 0x30 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (scsiCmnd->cdb[2] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + satIOContext->ATACmd = SAT_WRITE_SECTORS; + } + } + /* case 3 and 4 */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 3 */ + /* WRITE DMA EXT or WRITE DMA FUA EXT */ + TI_DBG5(("satWrite10: case 3\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + /* SAT_WRITE_DMA_FUA_EXT is optional and we don't support it */ + fis->h.command = SAT_WRITE_DMA_EXT; /* 0x35 */ + satIOContext->ATACmd = SAT_WRITE_DMA_EXT; + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[7]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + } + else + { + /* case 4 */ + /* WRITE MULTIPLE EXT or WRITE MULTIPLE FUA EXT or WRITE SECTOR(S) EXT */ + /* WRITE SECTORS EXT for easier implemetation */ + TI_DBG5(("satWrite10: case 4\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_SECTORS_EXT; /* 0x34 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[7]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + satIOContext->ATACmd = SAT_WRITE_SECTORS_EXT; + } + } + /* case 5 */ + if (pSatDevData->satNCQ == agTRUE) + { + /* WRITE FPDMA QUEUED */ + if (pSatDevData->sat48BitSupport != agTRUE) + { + TI_DBG5(("satWrite10: case 5 !!! error NCQ but 28 bit address support \n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + TI_DBG6(("satWrite10: case 5\n")); + + /* Support 48-bit FPDMA addressing, use WRITE FPDMA QUEUE command */ + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_FPDMA_QUEUED; /* 0x61 */ + fis->h.features = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + + /* Check FUA bit */ + if (scsiCmnd->cdb[1] & SCSI_WRITE10_FUA_MASK) + fis->d.device = 0xC0; /* FIS FUA set */ + else + fis->d.device = 0x40; /* FIS FUA clear */ + + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = scsiCmnd->cdb[7]; /* FIS sector count (15:8) */ + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_FPDMA_QUEUED; + } + + // tdhexdump("satWrite10 final fis", (bit8 *)fis, sizeof(agsaFisRegHostToDevice_t)); + + satIOContext->currentLBA = lba; + satIOContext->OrgTL = tl; + + /* + computing number of loop and remainder for tl + 0xFF in case not ext + 0xFFFF in case EXT + */ + if (fis->h.command == SAT_WRITE_SECTORS || fis->h.command == SAT_WRITE_DMA) + { + LoopNum = satComputeLoopNum(tl, 0xFF); + } + else if (fis->h.command == SAT_WRITE_SECTORS_EXT || + fis->h.command == SAT_WRITE_DMA_EXT || + fis->h.command == SAT_WRITE_DMA_FUA_EXT + ) + { + /* SAT_READ_SECTORS_EXT, SAT_READ_DMA_EXT */ + LoopNum = satComputeLoopNum(tl, 0xFFFF); + } + else + { + /* SAT_WRITE_FPDMA_QUEUEDK */ + LoopNum = satComputeLoopNum(tl, 0xFFFF); + } + + satIOContext->LoopNum = LoopNum; + + + if (LoopNum == 1) + { + TI_DBG5(("satWrite10: NON CHAINED data\n")); + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satNonChainedDataIOCB; + } + else + { + TI_DBG1(("satWrite10: CHAINED data\n")); + /* re-setting tl */ + if (fis->h.command == SAT_WRITE_SECTORS || fis->h.command == SAT_WRITE_DMA) + { + fis->d.sectorCount = 0xFF; + } + else if (fis->h.command == SAT_WRITE_SECTORS_EXT || + fis->h.command == SAT_WRITE_DMA_EXT || + fis->h.command == SAT_WRITE_DMA_FUA_EXT + ) + { + fis->d.sectorCount = 0xFF; + fis->d.sectorCountExp = 0xFF; + } + else + { + /* SAT_WRITE_FPDMA_QUEUED */ + fis->h.features = 0xFF; + fis->d.featuresExp = 0xFF; + } + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satChainedDataIOCB; + } + + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + return (status); +} + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satWrite_1. + * + * SAT implementation for SCSI WRITE10 and send FIS request to LL layer. + * This is used when WRITE10 is divided into multiple ATA commands + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satWrite_1( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + /* + Assumption: error check on lba and tl has been done in satWrite*() + lba = lba + tl; + */ + bit32 status; + satIOContext_t *satOrgIOContext = agNULL; + tiIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + bit32 lba = 0; + bit32 DenomTL = 0xFF; + bit32 Remainder = 0; + bit8 LBA[4]; /* 0 MSB, 3 LSB */ + + TI_DBG2(("satWrite_1: start\n")); + + fis = satIOContext->pFis; + satOrgIOContext = satIOContext->satOrgIOContext; + scsiCmnd = satOrgIOContext->pScsiCmnd; + + osti_memset(LBA,0, sizeof(LBA)); + + switch (satOrgIOContext->ATACmd) + { + case SAT_WRITE_DMA: + DenomTL = 0xFF; + break; + case SAT_WRITE_SECTORS: + DenomTL = 0xFF; + break; + case SAT_WRITE_DMA_EXT: + DenomTL = 0xFFFF; + break; + case SAT_WRITE_DMA_FUA_EXT: + DenomTL = 0xFFFF; + break; + case SAT_WRITE_SECTORS_EXT: + DenomTL = 0xFFFF; + break; + case SAT_WRITE_FPDMA_QUEUED: + DenomTL = 0xFFFF; + break; + default: + TI_DBG1(("satWrite_1: error incorrect ata command 0x%x\n", satIOContext->ATACmd)); + return tiError; + break; + } + + Remainder = satOrgIOContext->OrgTL % DenomTL; + satOrgIOContext->currentLBA = satOrgIOContext->currentLBA + DenomTL; + lba = satOrgIOContext->currentLBA; + + LBA[0] = (bit8)((lba & 0xF000) >> (8 * 3)); /* MSB */ + LBA[1] = (bit8)((lba & 0xF00) >> (8 * 2)); + LBA[2] = (bit8)((lba & 0xF0) >> 8); + LBA[3] = (bit8)(lba & 0xF); /* LSB */ + + switch (satOrgIOContext->ATACmd) + { + case SAT_WRITE_DMA: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_DMA; /* 0xCA */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (LBA[0] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->d.sectorCount = (bit8)Remainder; /* FIS sector count (7:0) */ + } + else + { + fis->d.sectorCount = 0xFF; /* FIS sector count (7:0) */ + } + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + + break; + case SAT_WRITE_SECTORS: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_SECTORS; /* 0x30 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (LBA[0] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->d.sectorCount = (bit8)Remainder; /* FIS sector count (7:0) */ + } + else + { + fis->d.sectorCount = 0xFF; /* FIS sector count (7:0) */ + } + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + + break; + case SAT_WRITE_DMA_EXT: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_DMA_EXT; /* 0x3D */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = LBA[0]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->d.sectorCount = (bit8)(Remainder & 0xFF); /* FIS sector count (7:0) */ + fis->d.sectorCountExp = (bit8)((Remainder & 0xFF00) >> 8); /* FIS sector count (15:8) */ + } + else + { + fis->d.sectorCount = 0xFF; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0xFF; /* FIS sector count (15:8) */ + } + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + + break; + case SAT_WRITE_SECTORS_EXT: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_SECTORS_EXT; /* 0x34 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = LBA[0]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->d.sectorCount = (bit8)(Remainder & 0xFF); /* FIS sector count (7:0) */ + fis->d.sectorCountExp = (bit8)((Remainder & 0xFF00) >> 8); /* FIS sector count (15:8) */ + } + else + { + fis->d.sectorCount = 0xFF; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0xFF; /* FIS sector count (15:8) */ + } + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + + break; + case SAT_WRITE_FPDMA_QUEUED: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_FPDMA_QUEUED; /* 0x61 */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + + /* Check FUA bit */ + if (scsiCmnd->cdb[1] & SCSI_WRITE10_FUA_MASK) + fis->d.device = 0xC0; /* FIS FUA set */ + else + fis->d.device = 0x40; /* FIS FUA clear */ + + fis->d.lbaLowExp = LBA[0];; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->h.features = (bit8)(Remainder & 0xFF); /* FIS sector count (7:0) */ + fis->d.featuresExp = (bit8)((Remainder & 0xFF00) >> 8); /* FIS sector count (15:8) */ + } + else + { + fis->h.features = 0xFF; /* FIS sector count (7:0) */ + fis->d.featuresExp = 0xFF; /* FIS sector count (15:8) */ + } + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_WRITE; + break; + + default: + TI_DBG1(("satWrite_1: error incorrect ata command 0x%x\n", satIOContext->ATACmd)); + return tiError; + break; + } + + /* Initialize CB for SATA completion. + */ + /* chained data */ + satIOContext->satCompleteCB = &satChainedDataIOCB; + + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + TI_DBG5(("satWrite_1: return\n")); + return (status); +} + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI WRITE6. + * + * SAT implementation for SCSI WRITE6 and send FIS request to LL layer. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satWrite6( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satDeviceData_t *pSatDevData; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 lba = 0; + bit16 tl = 0; + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &tiScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + TI_DBG5(("satWrite6: start\n")); + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[5] & SCSI_NACA_MASK) || (scsiCmnd->cdb[5] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satWrite6: return control\n")); + return tiSuccess; + } + + + /* cbd6; computing LBA and transfer length */ + lba = (((scsiCmnd->cdb[1]) & 0x1f) << (8*2)) + + (scsiCmnd->cdb[2] << 8) + scsiCmnd->cdb[3]; + tl = scsiCmnd->cdb[4]; + + + /* Table 34, 9.1, p 46 */ + /* + note: As of 2/10/2006, no support for DMA QUEUED + */ + + /* + Table 34, 9.1, p 46, b + When no 48-bit addressing support or NCQ, if LBA is beyond (2^28 - 1), + return check condition + */ + if (pSatDevData->satNCQ != agTRUE && + pSatDevData->sat48BitSupport != agTRUE + ) + { + if (lba > SAT_TR_LBA_LIMIT - 1) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satWrite6: return LBA out of range\n")); + return tiSuccess; + } + } + + /* case 1 and 2 */ + if (lba + tl <= SAT_TR_LBA_LIMIT) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 2 */ + /* WRITE DMA*/ + TI_DBG5(("satWrite6: case 2\n")); + + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_DMA; /* 0xCA */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = (bit8)((scsiCmnd->cdb[1]) & 0x1f); /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + if (tl == 0) + { + /* temporary fix */ + fis->d.sectorCount = 0xff; /* FIS sector count (7:0) */ + } + else + { + fis->d.sectorCount = scsiCmnd->cdb[4]; /* FIS sector count (7:0) */ + } + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + } + else + { + /* case 1 */ + /* WRITE SECTORS for easier implemetation */ + TI_DBG5(("satWrite6: case 1\n")); + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_SECTORS; /* 0xCA */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = (bit8)((scsiCmnd->cdb[1]) & 0x1f); /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + if (tl == 0) + { + /* temporary fix */ + fis->d.sectorCount = 0xff; /* FIS sector count (7:0) */ + } + else + { + fis->d.sectorCount = scsiCmnd->cdb[4]; /* FIS sector count (7:0) */ + } + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + + } + } + + /* case 3 and 4 */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 3 */ + /* WRITE DMA EXT only */ + TI_DBG5(("satWrite6: case 3\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_DMA_EXT; /* 0x35 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = (bit8)((scsiCmnd->cdb[1]) & 0x1f); /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = 0; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + if (tl == 0) + { + /* sector count is 256, 0x100*/ + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0x01; /* FIS sector count (15:8) */ + } + else + { + fis->d.sectorCount = scsiCmnd->cdb[4]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + } + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + } + else + { + /* case 4 */ + /* WRITE SECTORS EXT for easier implemetation */ + TI_DBG5(("satWrite6: case 4\n")); + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_SECTORS_EXT; /* 0x34 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = (bit8)((scsiCmnd->cdb[1]) & 0x1f); /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = 0; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + if (tl == 0) + { + /* sector count is 256, 0x100*/ + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0x01; /* FIS sector count (15:8) */ + } + else + { + fis->d.sectorCount = scsiCmnd->cdb[4]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + } + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + } + } + + /* case 5 */ + if (pSatDevData->satNCQ == agTRUE) + { + /* WRITE FPDMA QUEUED */ + if (pSatDevData->sat48BitSupport != agTRUE) + { + /* sanity check */ + TI_DBG5(("satWrite6: case 5 !!! error NCQ but 28 bit address support \n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + TI_DBG5(("satWrite6: case 5\n")); + + /* Support 48-bit FPDMA addressing, use WRITE FPDMA QUEUE command */ + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_FPDMA_QUEUED; /* 0x61 */ + fis->d.lbaLow = scsiCmnd->cdb[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = (bit8)((scsiCmnd->cdb[1]) & 0x1f); /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS FUA clear */ + fis->d.lbaLowExp = 0; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + if (tl == 0) + { + /* sector count is 256, 0x100*/ + fis->h.features = 0; /* FIS sector count (7:0) */ + fis->d.featuresExp = 0x01; /* FIS sector count (15:8) */ + } + else + { + fis->h.features = scsiCmnd->cdb[4]; /* FIS sector count (7:0) */ + fis->d.featuresExp = 0; /* FIS sector count (15:8) */ + } + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_WRITE; + } + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satNonChainedDataIOCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + return (status); +} + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI TEST UNIT READY. + * + * SAT implementation for SCSI TUR and send FIS request to LL layer. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satTestUnitReady( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + + bit32 status; + bit32 agRequestType; + satDeviceData_t *pSatDevData; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &tiScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + TI_DBG6(("satTestUnitReady: entry tiDeviceHandle=%p tiIORequest=%p\n", + tiDeviceHandle, tiIORequest)); + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[5] & SCSI_NACA_MASK) || (scsiCmnd->cdb[5] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satTestUnitReady: return control\n")); + return tiSuccess; + } + + /* SAT revision 8, 8.11.2, p42*/ + if (pSatDevData->satStopState == agTRUE) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_NOT_READY, + 0, + SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_INITIALIZING_COMMAND_REQUIRED, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + TI_DBG1(("satTestUnitReady: stop state\n")); + return tiSuccess; + } + + /* + * Check if format is in progress + */ + + if (pSatDevData->satDriveState == SAT_DEV_STATE_FORMAT_IN_PROGRESS) + { + TI_DBG1(("satTestUnitReady() FORMAT_IN_PROGRESS tiDeviceHandle=%p tiIORequest=%p\n", + tiDeviceHandle, tiIORequest)); + + satSetSensePayload( pSense, + SCSI_SNSKEY_NOT_READY, + 0, + SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_FORMAT_IN_PROGRESS, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + TI_DBG1(("satTestUnitReady: format in progress\n")); + return tiSuccess; + } + + /* + check previously issued ATA command + */ + if (pSatDevData->satPendingIO != 0) + { + if (pSatDevData->satDeviceFaultState == agTRUE) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_HARDWARE_ERROR, + 0, + SCSI_SNSCODE_LOGICAL_UNIT_FAILURE, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + TI_DBG1(("satTestUnitReady: previous command ended in error\n")); + return tiSuccess; + } + } + /* + check removalbe media feature set + */ + if(pSatDevData->satRemovableMedia && pSatDevData->satRemovableMediaEnabled) + { + TI_DBG5(("satTestUnitReady: sending get media status cmnd\n")); + /* send GET MEDIA STATUS command */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_GET_MEDIA_STATUS; /* 0xDA */ + fis->h.features = 0; /* FIS features NA */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.device = 0; /* FIS DEV is discared in SATA */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satTestUnitReadyCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + return (status); + } + /* + number 6) in SAT p42 + send ATA CHECK POWER MODE + */ + TI_DBG5(("satTestUnitReady: sending check power mode cmnd\n")); + status = satTestUnitReady_1( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + return (status); +} + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satTestUnitReady_1. + * + * SAT implementation for SCSI satTestUnitReady_1. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satTestUnitReady_1( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + /* + sends SAT_CHECK_POWER_MODE as a part of TESTUNITREADY + internally generated - no directly corresponding scsi + called in satIOCompleted as a part of satTestUnitReady(), SAT, revision8, 8.11.2, p42 + */ + bit32 status; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; + + fis = satIOContext->pFis; + + TI_DBG5(("satTestUnitReady_1: start\n")); + + /* + * Send the ATA CHECK POWER MODE command. + */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_CHECK_POWER_MODE; /* 0xE5 */ + fis->h.features = 0; + fis->d.lbaLow = 0; + fis->d.lbaMid = 0; + fis->d.lbaHigh = 0; + fis->d.device = 0; + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satTestUnitReadyCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + TI_DBG5(("satTestUnitReady_1: return\n")); + + return status; +} + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satReportLun. + * + * SAT implementation for SCSI satReportLun. Only LUN0 is reported. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satReportLun( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + scsiRspSense_t *pSense; + bit32 allocationLen; + bit32 reportLunLen; + scsiReportLun_t *pReportLun; + tiIniScsiCmnd_t *scsiCmnd; + + TI_DBG5(("satReportLun entry: tiDeviceHandle=%p tiIORequest=%p\n", + tiDeviceHandle, tiIORequest)); + + pSense = satIOContext->pSense; + pReportLun = (scsiReportLun_t *) tiScsiRequest->sglVirtualAddr; + scsiCmnd = &tiScsiRequest->scsiCmnd; + +// tdhexdump("satReportLun cdb", (bit8 *)scsiCmnd, 16); + + /* Find the buffer size allocated by Initiator */ + allocationLen = (((bit32)scsiCmnd->cdb[6]) << 24) | + (((bit32)scsiCmnd->cdb[7]) << 16) | + (((bit32)scsiCmnd->cdb[8]) << 8 ) | + (((bit32)scsiCmnd->cdb[9]) ); + + reportLunLen = 16; /* 8 byte header and 8 bytes of LUN0 */ + + if (allocationLen < reportLunLen) + { + TI_DBG1(("satReportLun *** ERROR *** insufficient len=0x%x tiDeviceHandle=%p tiIORequest=%p\n", + reportLunLen, tiDeviceHandle, tiIORequest)); + + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + + } + + /* Set length to one entry */ + pReportLun->len[0] = 0; + pReportLun->len[1] = 0; + pReportLun->len[2] = 0; + pReportLun->len[3] = sizeof (tiLUN_t); + + pReportLun->reserved = 0; + + /* Set to LUN 0: + * - address method to 0x00: Peripheral device addressing method, + * - bus identifier to 0 + */ + pReportLun->lunList[0].lun[0] = 0; + pReportLun->lunList[0].lun[1] = 0; + pReportLun->lunList[0].lun[2] = 0; + pReportLun->lunList[0].lun[3] = 0; + pReportLun->lunList[0].lun[4] = 0; + pReportLun->lunList[0].lun[5] = 0; + pReportLun->lunList[0].lun[6] = 0; + pReportLun->lunList[0].lun[7] = 0; + + if (allocationLen > reportLunLen) + { + /* underrun */ + TI_DBG1(("satReportLun reporting underrun reportLunLen=0x%x allocationLen=0x%x \n", reportLunLen, allocationLen)); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOUnderRun, + allocationLen - reportLunLen, + agNULL, + satIOContext->interruptContext ); + + + } + else + { + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + } + return tiSuccess; +} + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI REQUEST SENSE. + * + * SAT implementation for SCSI REQUEST SENSE. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satRequestSense( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + /* + SAT Rev 8 p38, Table25 + sending SMART RETURN STATUS + Checking SMART Treshold Exceeded Condition is done in satRequestSenseCB() + Only fixed format sense data is support. In other words, we don't support DESC bit is set + in Request Sense + */ + bit32 status; + bit32 agRequestType; + scsiRspSense_t *pSense; + satDeviceData_t *pSatDevData; + tiIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + tdIORequestBody_t *tdIORequestBody; + satInternalIo_t *satIntIo = agNULL; + satIOContext_t *satIOContext2; + + TI_DBG4(("satRequestSense entry: tiDeviceHandle=%p tiIORequest=%p\n", + tiDeviceHandle, tiIORequest)); + + pSense = (scsiRspSense_t *) tiScsiRequest->sglVirtualAddr; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &tiScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + TI_DBG4(("satRequestSense: pSatDevData=%p\n", pSatDevData)); + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[5] & SCSI_NACA_MASK) || (scsiCmnd->cdb[5] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satRequestSense: return control\n")); + return tiSuccess; + } + + /* + Only fixed format sense data is support. In other words, we don't support DESC bit is set + in Request Sense + */ + if ( scsiCmnd->cdb[1] & ATA_REMOVABLE_MEDIA_DEVICE_MASK ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satRequestSense: DESC bit is set, which we don't support\n")); + return tiSuccess; + } + + + if (pSatDevData->satSMARTEnabled == agTRUE) + { + /* sends SMART RETURN STATUS */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_SMART_RETURN_STATUS; /* 0xB0 */ + fis->h.features = 0xDA; /* FIS features */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaLowExp = 0; /* FIS LBA (31:24) */ + fis->d.lbaMid = 0x4F; /* FIS LBA (15:8 ) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHigh = 0xC2; /* FIS LBA (23:16) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.device = 0; /* FIS DEV is discared in SATA */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved4 = 0; + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satRequestSenseCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + TI_DBG4(("satRequestSense: if return, status %d\n", status)); + return (status); + } + else + { + /*allocate iocontext for xmitting xmit SAT_CHECK_POWER_MODE + then call satRequestSense2 */ + + TI_DBG4(("satRequestSense: before satIntIo %p\n", satIntIo)); + /* allocate iocontext */ + satIntIo = satAllocIntIoResource( tiRoot, + tiIORequest, /* original request */ + pSatDevData, + tiScsiRequest->scsiCmnd.expDataLength, + satIntIo); + + TI_DBG4(("satRequestSense: after satIntIo %p\n", satIntIo)); + + if (satIntIo == agNULL) + { + /* memory allocation failure */ + satFreeIntIoResource( tiRoot, + pSatDevData, + satIntIo); + + /* failed during sending SMART RETURN STATUS */ + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_HARDWARE_IMPENDING_FAILURE, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext ); + + TI_DBG4(("satRequestSense: else fail 1\n")); + return tiSuccess; + } /* end of memory allocation failure */ + + + /* + * Need to initialize all the fields within satIOContext except + * reqType and satCompleteCB which will be set depending on cmd. + */ + + if (satIntIo == agNULL) + { + TI_DBG4(("satRequestSense: satIntIo is NULL\n")); + } + else + { + TI_DBG4(("satRequestSense: satIntIo is NOT NULL\n")); + } + /* use this --- tttttthe one the same */ + + + satIntIo->satOrgTiIORequest = tiIORequest; + tdIORequestBody = (tdIORequestBody_t *)satIntIo->satIntRequestBody; + satIOContext2 = &(tdIORequestBody->transport.SATA.satIOContext); + + satIOContext2->pSatDevData = pSatDevData; + satIOContext2->pFis = &(tdIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev); + satIOContext2->pScsiCmnd = &(satIntIo->satIntTiScsiXchg.scsiCmnd); + satIOContext2->pSense = &(tdIORequestBody->transport.SATA.sensePayload); + satIOContext2->pTiSenseData = &(tdIORequestBody->transport.SATA.tiSenseData); + satIOContext2->pTiSenseData->senseData = satIOContext2->pSense; + satIOContext2->tiRequestBody = satIntIo->satIntRequestBody; + satIOContext2->interruptContext = satIOContext->interruptContext; + satIOContext2->satIntIoContext = satIntIo; + satIOContext2->ptiDeviceHandle = tiDeviceHandle; + satIOContext2->satOrgIOContext = satIOContext; + + TI_DBG4(("satRequestSense: satIntIo->satIntTiScsiXchg.agSgl1.len %d\n", satIntIo->satIntTiScsiXchg.agSgl1.len)); + + TI_DBG4(("satRequestSense: satIntIo->satIntTiScsiXchg.agSgl1.upper %d\n", satIntIo->satIntTiScsiXchg.agSgl1.upper)); + + TI_DBG4(("satRequestSense: satIntIo->satIntTiScsiXchg.agSgl1.lower %d\n", satIntIo->satIntTiScsiXchg.agSgl1.lower)); + + TI_DBG4(("satRequestSense: satIntIo->satIntTiScsiXchg.agSgl1.type %d\n", satIntIo->satIntTiScsiXchg.agSgl1.type)); + + status = satRequestSense_1( tiRoot, + &(satIntIo->satIntTiIORequest), + tiDeviceHandle, + &(satIntIo->satIntTiScsiXchg), + satIOContext2); + + if (status != tiSuccess) + { + satFreeIntIoResource( tiRoot, + pSatDevData, + satIntIo); + + /* failed during sending SMART RETURN STATUS */ + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_HARDWARE_IMPENDING_FAILURE, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + agNULL, + satIOContext->interruptContext ); + + TI_DBG1(("satRequestSense: else fail 2\n")); + return tiSuccess; + } + TI_DBG4(("satRequestSense: else return success\n")); + return tiSuccess; + } +} + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI REQUEST SENSE. + * + * SAT implementation for SCSI REQUEST SENSE. + * Sub function of satRequestSense + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satRequestSense_1( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + /* + sends SAT_CHECK_POWER_MODE + */ + bit32 status; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; + + TI_DBG4(("satRequestSense_1 entry: tiDeviceHandle=%p tiIORequest=%p\n", + tiDeviceHandle, tiIORequest)); + + fis = satIOContext->pFis; + /* + * Send the ATA CHECK POWER MODE command. + */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_CHECK_POWER_MODE; /* 0xE5 */ + fis->h.features = 0; + fis->d.lbaLow = 0; + fis->d.lbaMid = 0; + fis->d.lbaHigh = 0; + fis->d.device = 0; + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satRequestSenseCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + + TI_DBG4(("satRequestSense_1: agSgl1.len %d\n", tiScsiRequest->agSgl1.len)); + + TI_DBG4(("satRequestSense_1: agSgl1.upper %d\n", tiScsiRequest->agSgl1.upper)); + + TI_DBG4(("satRequestSense_1: agSgl1.lower %d\n", tiScsiRequest->agSgl1.lower)); + + TI_DBG4(("satRequestSense_1: agSgl1.type %d\n", tiScsiRequest->agSgl1.type)); + + // tdhexdump("satRequestSense_1", (bit8 *)fis, sizeof(agsaFisRegHostToDevice_t)); + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + + + return status; +} + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI INQUIRY. + * + * SAT implementation for SCSI INQUIRY. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satInquiry( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + /* + CMDDT bit is obsolete in SPC-3 and this is assumed in SAT revision 8 + */ + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + satDeviceData_t *pSatDevData; + bit32 status; + + TI_DBG5(("satInquiry: start\n")); + TI_DBG5(("satInquiry entry: tiDeviceHandle=%p tiIORequest=%p\n", + tiDeviceHandle, tiIORequest)); + pSense = satIOContext->pSense; + scsiCmnd = &tiScsiRequest->scsiCmnd; + pSatDevData = satIOContext->pSatDevData; + TI_DBG5(("satInquiry: pSatDevData=%p\n", pSatDevData)); + //tdhexdump("satInquiry", (bit8 *)scsiCmnd->cdb, 6); + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[5] & SCSI_NACA_MASK) || (scsiCmnd->cdb[5] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + TI_DBG2(("satInquiry: return control\n")); + return tiSuccess; + } + + /* checking EVPD and Allocation Length */ + /* SPC-4 spec 6.4 p141 */ + /* EVPD bit == 0 && PAGE CODE != 0 */ + if ( !(scsiCmnd->cdb[1] & SCSI_EVPD_MASK) && + (scsiCmnd->cdb[2] != 0) + ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + TI_DBG1(("satInquiry: return EVPD and PAGE CODE\n")); + return tiSuccess; + } + TI_DBG6(("satInquiry: allocation length 0x%x %d\n", ((scsiCmnd->cdb[3]) << 8) + scsiCmnd->cdb[4], ((scsiCmnd->cdb[3]) << 8) + scsiCmnd->cdb[4])); + + /* convert OS IO to TD internal IO */ + if ( pSatDevData->IDDeviceValid == agFALSE) + { + status = satStartIDDev( + tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext + ); + TI_DBG6(("satInquiry: end status %d\n", status)); + return status; + } + else + { + TI_DBG6(("satInquiry: calling satInquiryIntCB\n")); + satInquiryIntCB( + tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext + ); + + return tiSuccess; + } + +} + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satReadCapacity10. + * + * SAT implementation for SCSI satReadCapacity10. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satReadCapacity10( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + bit8 *pVirtAddr; + satDeviceData_t *pSatDevData; + agsaSATAIdentifyData_t *pSATAIdData; + bit32 lastLba; + bit32 word117_118; + bit32 word117; + bit32 word118; + TI_DBG5(("satReadCapacity10: start: tiDeviceHandle=%p tiIORequest=%p\n", + tiDeviceHandle, tiIORequest)); + + pSense = satIOContext->pSense; + pVirtAddr = (bit8 *) tiScsiRequest->sglVirtualAddr; + scsiCmnd = &tiScsiRequest->scsiCmnd; + pSatDevData = satIOContext->pSatDevData; + pSATAIdData = &pSatDevData->satIdentifyData; + + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[9] & SCSI_NACA_MASK) || (scsiCmnd->cdb[9] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satReadCapacity10: return control\n")); + return tiSuccess; + } + + + /* + * If Logical block address is not set to zero, return error + */ + if ((scsiCmnd->cdb[2] || scsiCmnd->cdb[3] || scsiCmnd->cdb[4] || scsiCmnd->cdb[5])) + { + TI_DBG1(("satReadCapacity10 *** ERROR *** logical address non zero, tiDeviceHandle=%p tiIORequest=%p\n", + tiDeviceHandle, tiIORequest)); + + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + + } + + /* + * If PMI bit is not zero, return error + */ + if ( ((scsiCmnd->cdb[8]) & SCSI_READ_CAPACITY10_PMI_MASK) != 0 ) + { + TI_DBG1(("satReadCapacity10 *** ERROR *** PMI is not zero, tiDeviceHandle=%p tiIORequest=%p\n", + tiDeviceHandle, tiIORequest)); + + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + + } + + /* + filling in Read Capacity parameter data + saved identify device has been already flipped + See ATA spec p125 and p136 and SBC spec p54 + */ + /* + * If 48-bit addressing is supported, set capacity information from Identify + * Device Word 100-103. + */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + /* + * Setting RETURNED LOGICAL BLOCK ADDRESS in READ CAPACITY(10) response data: + * SBC-2 specifies that if the capacity exceeded the 4-byte RETURNED LOGICAL + * BLOCK ADDRESS in READ CAPACITY(10) parameter data, the the RETURNED LOGICAL + * BLOCK ADDRESS should be set to 0xFFFFFFFF so the application client would + * then issue a READ CAPACITY(16) command. + */ + /* ATA Identify Device information word 100 - 103 */ + if ( (pSATAIdData->maxLBA32_47 != 0 ) || (pSATAIdData->maxLBA48_63 != 0)) + { + pVirtAddr[0] = 0xFF; /* MSB number of block */ + pVirtAddr[1] = 0xFF; + pVirtAddr[2] = 0xFF; + pVirtAddr[3] = 0xFF; /* LSB number of block */ + TI_DBG1(("satReadCapacity10: returns 0xFFFFFFFF\n")); + } + else /* Fit the Readcapacity10 4-bytes response length */ + { + lastLba = (((pSATAIdData->maxLBA16_31) << 16) ) | + (pSATAIdData->maxLBA0_15); + lastLba = lastLba - 1; /* LBA starts from zero */ + + /* + for testing + lastLba = lastLba - (512*10) - 1; + */ + + + pVirtAddr[0] = (bit8)((lastLba >> 24) & 0xFF); /* MSB */ + pVirtAddr[1] = (bit8)((lastLba >> 16) & 0xFF); + pVirtAddr[2] = (bit8)((lastLba >> 8) & 0xFF); + pVirtAddr[3] = (bit8)((lastLba ) & 0xFF); /* LSB */ + + TI_DBG3(("satReadCapacity10: lastLba is 0x%x %d\n", lastLba, lastLba)); + TI_DBG3(("satReadCapacity10: LBA 0 is 0x%x %d\n", pVirtAddr[0], pVirtAddr[0])); + TI_DBG3(("satReadCapacity10: LBA 1 is 0x%x %d\n", pVirtAddr[1], pVirtAddr[1])); + TI_DBG3(("satReadCapacity10: LBA 2 is 0x%x %d\n", pVirtAddr[2], pVirtAddr[2])); + TI_DBG3(("satReadCapacity10: LBA 3 is 0x%x %d\n", pVirtAddr[3], pVirtAddr[3])); + + } + } + + /* + * For 28-bit addressing, set capacity information from Identify + * Device Word 60-61. + */ + else + { + /* ATA Identify Device information word 60 - 61 */ + lastLba = (((pSATAIdData->numOfUserAddressableSectorsHi) << 16) ) | + (pSATAIdData->numOfUserAddressableSectorsLo); + lastLba = lastLba - 1; /* LBA starts from zero */ + + pVirtAddr[0] = (bit8)((lastLba >> 24) & 0xFF); /* MSB */ + pVirtAddr[1] = (bit8)((lastLba >> 16) & 0xFF); + pVirtAddr[2] = (bit8)((lastLba >> 8) & 0xFF); + pVirtAddr[3] = (bit8)((lastLba ) & 0xFF); /* LSB */ + } + /* SAT Rev 8d */ + if (((pSATAIdData->word104_107[2]) & 0x1000) == 0) + { + TI_DBG5(("satReadCapacity10: Default Block Length is 512\n")); + /* + * Set the block size, fixed at 512 bytes. + */ + pVirtAddr[4] = 0x00; /* MSB block size in bytes */ + pVirtAddr[5] = 0x00; + pVirtAddr[6] = 0x02; + pVirtAddr[7] = 0x00; /* LSB block size in bytes */ + } + else + { + word118 = pSATAIdData->word112_126[6]; + word117 = pSATAIdData->word112_126[5]; + + word117_118 = (word118 << 16) + word117; + word117_118 = word117_118 * 2; + pVirtAddr[4] = (bit8)((word117_118 >> 24) & 0xFF); /* MSB block size in bytes */ + pVirtAddr[5] = (bit8)((word117_118 >> 16) & 0xFF); + pVirtAddr[6] = (bit8)((word117_118 >> 8) & 0xFF); + pVirtAddr[7] = (bit8)(word117_118 & 0xFF); /* LSB block size in bytes */ + + TI_DBG1(("satReadCapacity10: Nondefault word118 %d 0x%x \n", word118, word118)); + TI_DBG1(("satReadCapacity10: Nondefault word117 %d 0x%x \n", word117, word117)); + TI_DBG1(("satReadCapacity10: Nondefault Block Length is %d 0x%x \n",word117_118, word117_118)); + + } + + /* fill in MAX LBA, which is used in satSendDiagnostic_1() */ + pSatDevData->satMaxLBA[0] = 0; /* MSB */ + pSatDevData->satMaxLBA[1] = 0; + pSatDevData->satMaxLBA[2] = 0; + pSatDevData->satMaxLBA[3] = 0; + pSatDevData->satMaxLBA[4] = pVirtAddr[0]; + pSatDevData->satMaxLBA[5] = pVirtAddr[1]; + pSatDevData->satMaxLBA[6] = pVirtAddr[2]; + pSatDevData->satMaxLBA[7] = pVirtAddr[3]; /* LSB */ + + + TI_DBG4(("satReadCapacity10 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x , tiDeviceHandle=%p tiIORequest=%p\n", + pVirtAddr[0], pVirtAddr[1], pVirtAddr[2], pVirtAddr[3], + pVirtAddr[4], pVirtAddr[5], pVirtAddr[6], pVirtAddr[7], + tiDeviceHandle, tiIORequest)); + + + /* + * Send the completion response now. + */ + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + return tiSuccess; +} + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satReadCapacity16. + * + * SAT implementation for SCSI satReadCapacity16. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satReadCapacity16( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + bit8 *pVirtAddr; + satDeviceData_t *pSatDevData; + agsaSATAIdentifyData_t *pSATAIdData; + bit32 lastLbaLo; + bit32 allocationLen; + bit32 readCapacityLen = 32; + bit32 i = 0; + TI_DBG5(("satReadCapacity16 start: tiDeviceHandle=%p tiIORequest=%p\n", + tiDeviceHandle, tiIORequest)); + + pSense = satIOContext->pSense; + pVirtAddr = (bit8 *) tiScsiRequest->sglVirtualAddr; + scsiCmnd = &tiScsiRequest->scsiCmnd; + pSatDevData = satIOContext->pSatDevData; + pSATAIdData = &pSatDevData->satIdentifyData; + + /* Find the buffer size allocated by Initiator */ + allocationLen = (((bit32)scsiCmnd->cdb[10]) << 24) | + (((bit32)scsiCmnd->cdb[11]) << 16) | + (((bit32)scsiCmnd->cdb[12]) << 8 ) | + (((bit32)scsiCmnd->cdb[13]) ); + + + if (allocationLen < readCapacityLen) + { + TI_DBG1(("satReadCapacity16 *** ERROR *** insufficient len=0x%x readCapacityLen=0x%x\n", allocationLen, readCapacityLen)); + + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + + } + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[15] & SCSI_NACA_MASK) || (scsiCmnd->cdb[15] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satReadCapacity16: return control\n")); + return tiSuccess; + } + + /* + * If Logical blcok address is not set to zero, return error + */ + if ((scsiCmnd->cdb[2] || scsiCmnd->cdb[3] || scsiCmnd->cdb[4] || scsiCmnd->cdb[5]) || + (scsiCmnd->cdb[6] || scsiCmnd->cdb[7] || scsiCmnd->cdb[8] || scsiCmnd->cdb[9]) ) + { + TI_DBG1(("satReadCapacity16 *** ERROR *** logical address non zero, tiDeviceHandle=%p tiIORequest=%p\n", + tiDeviceHandle, tiIORequest)); + + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + + } + + /* + * If PMI bit is not zero, return error + */ + if ( ((scsiCmnd->cdb[14]) & SCSI_READ_CAPACITY16_PMI_MASK) != 0 ) + { + TI_DBG1(("satReadCapacity16 *** ERROR *** PMI is not zero, tiDeviceHandle=%p tiIORequest=%p\n", + tiDeviceHandle, tiIORequest)); + + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + + } + + /* + filling in Read Capacity parameter data + */ + + /* + * If 48-bit addressing is supported, set capacity information from Identify + * Device Word 100-103. + */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + pVirtAddr[0] = (bit8)(((pSATAIdData->maxLBA48_63) >> 8) & 0xff); /* MSB */ + pVirtAddr[1] = (bit8)((pSATAIdData->maxLBA48_63) & 0xff); + pVirtAddr[2] = (bit8)(((pSATAIdData->maxLBA32_47) >> 8) & 0xff); + pVirtAddr[3] = (bit8)((pSATAIdData->maxLBA32_47) & 0xff); + + lastLbaLo = (((pSATAIdData->maxLBA16_31) << 16) ) | (pSATAIdData->maxLBA0_15); + lastLbaLo = lastLbaLo - 1; /* LBA starts from zero */ + + pVirtAddr[4] = (bit8)((lastLbaLo >> 24) & 0xFF); + pVirtAddr[5] = (bit8)((lastLbaLo >> 16) & 0xFF); + pVirtAddr[6] = (bit8)((lastLbaLo >> 8) & 0xFF); + pVirtAddr[7] = (bit8)((lastLbaLo ) & 0xFF); /* LSB */ + + } + + /* + * For 28-bit addressing, set capacity information from Identify + * Device Word 60-61. + */ + else + { + pVirtAddr[0] = 0; /* MSB */ + pVirtAddr[1] = 0; + pVirtAddr[2] = 0; + pVirtAddr[3] = 0; + + lastLbaLo = (((pSATAIdData->numOfUserAddressableSectorsHi) << 16) ) | + (pSATAIdData->numOfUserAddressableSectorsLo); + lastLbaLo = lastLbaLo - 1; /* LBA starts from zero */ + + pVirtAddr[4] = (bit8)((lastLbaLo >> 24) & 0xFF); + pVirtAddr[5] = (bit8)((lastLbaLo >> 16) & 0xFF); + pVirtAddr[6] = (bit8)((lastLbaLo >> 8) & 0xFF); + pVirtAddr[7] = (bit8)((lastLbaLo ) & 0xFF); /* LSB */ + + } + + /* + * Set the block size, fixed at 512 bytes. + */ + pVirtAddr[8] = 0x00; /* MSB block size in bytes */ + pVirtAddr[9] = 0x00; + pVirtAddr[10] = 0x02; + pVirtAddr[11] = 0x00; /* LSB block size in bytes */ + + + /* fill in MAX LBA, which is used in satSendDiagnostic_1() */ + pSatDevData->satMaxLBA[0] = pVirtAddr[0]; /* MSB */ + pSatDevData->satMaxLBA[1] = pVirtAddr[1]; + pSatDevData->satMaxLBA[2] = pVirtAddr[2]; + pSatDevData->satMaxLBA[3] = pVirtAddr[3]; + pSatDevData->satMaxLBA[4] = pVirtAddr[4]; + pSatDevData->satMaxLBA[5] = pVirtAddr[5]; + pSatDevData->satMaxLBA[6] = pVirtAddr[6]; + pSatDevData->satMaxLBA[7] = pVirtAddr[7]; /* LSB */ + + TI_DBG5(("satReadCapacity16 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x , tiDeviceHandle=%p tiIORequest=%p\n", + pVirtAddr[0], pVirtAddr[1], pVirtAddr[2], pVirtAddr[3], + pVirtAddr[4], pVirtAddr[5], pVirtAddr[6], pVirtAddr[7], + pVirtAddr[8], pVirtAddr[9], pVirtAddr[10], pVirtAddr[11], + tiDeviceHandle, tiIORequest)); + + for(i=12;i<=31;i++) + { + pVirtAddr[i] = 0x00; + } + + /* + * Send the completion response now. + */ + if (allocationLen > readCapacityLen) + { + /* underrun */ + TI_DBG1(("satReadCapacity16 reporting underrun readCapacityLen=0x%x allocationLen=0x%x \n", readCapacityLen, allocationLen)); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOUnderRun, + allocationLen - readCapacityLen, + agNULL, + satIOContext->interruptContext ); + + + } + else + { + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + } + return tiSuccess; + +} + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI MODE SENSE (6). + * + * SAT implementation for SCSI MODE SENSE (6). + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satModeSense6( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + + scsiRspSense_t *pSense; + bit32 requestLen; + tiIniScsiCmnd_t *scsiCmnd; + bit32 pageSupported; + bit8 page; + bit8 *pModeSense; /* Mode Sense data buffer */ + satDeviceData_t *pSatDevData; + bit8 PC; + bit8 AllPages[MODE_SENSE6_RETURN_ALL_PAGES_LEN]; + bit8 Control[MODE_SENSE6_CONTROL_PAGE_LEN]; + bit8 RWErrorRecovery[MODE_SENSE6_READ_WRITE_ERROR_RECOVERY_PAGE_LEN]; + bit8 Caching[MODE_SENSE6_CACHING_LEN]; + bit8 InfoExceptionCtrl[MODE_SENSE6_INFORMATION_EXCEPTION_CONTROL_PAGE_LEN]; + bit8 lenRead = 0; + + + TI_DBG5(("satModeSense6 entry: tiDeviceHandle=%p tiIORequest=%p\n", + tiDeviceHandle, tiIORequest)); + + pSense = satIOContext->pSense; + scsiCmnd = &tiScsiRequest->scsiCmnd; + pModeSense = (bit8 *) tiScsiRequest->sglVirtualAddr; + pSatDevData = satIOContext->pSatDevData; + + //tdhexdump("satModeSense6", (bit8 *)scsiCmnd->cdb, 6); + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[5] & SCSI_NACA_MASK) || (scsiCmnd->cdb[5] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG2(("satModeSense6: return control\n")); + return tiSuccess; + } + + /* checking PC(Page Control) + SAT revion 8, 8.5.3 p33 and 10.1.2, p66 + */ + PC = (bit8)((scsiCmnd->cdb[2]) & SCSI_MODE_SENSE6_PC_MASK); + if (PC != 0) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satModeSense6: return due to PC value pc 0x%x\n", PC >> 6)); + return tiSuccess; + } + + /* reading PAGE CODE */ + page = (bit8)((scsiCmnd->cdb[2]) & SCSI_MODE_SENSE6_PAGE_CODE_MASK); + + + TI_DBG5(("satModeSense6: page=0x%x, tiDeviceHandle=%p tiIORequest=%p\n", + page, tiDeviceHandle, tiIORequest)); + + requestLen = scsiCmnd->cdb[4]; + + /* + Based on page code value, returns a corresponding mode page + note: no support for subpage + */ + + switch(page) + { + case MODESENSE_RETURN_ALL_PAGES: + case MODESENSE_CONTROL_PAGE: /* control */ + case MODESENSE_READ_WRITE_ERROR_RECOVERY_PAGE: /* Read-Write Error Recovery */ + case MODESENSE_CACHING: /* caching */ + case MODESENSE_INFORMATION_EXCEPTION_CONTROL_PAGE: /* informational exceptions control*/ + pageSupported = agTRUE; + break; + case MODESENSE_VENDOR_SPECIFIC_PAGE: /* vendor specific */ + default: + pageSupported = agFALSE; + break; + } + + if (pageSupported == agFALSE) + { + + TI_DBG1(("satModeSense6 *** ERROR *** not supported page 0x%x tiDeviceHandle=%p tiIORequest=%p\n", + page, tiDeviceHandle, tiIORequest)); + + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_COMMAND, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + + switch(page) + { + case MODESENSE_RETURN_ALL_PAGES: + lenRead = (bit8)MIN(requestLen, MODE_SENSE6_RETURN_ALL_PAGES_LEN); + break; + case MODESENSE_CONTROL_PAGE: /* control */ + lenRead = (bit8)MIN(requestLen, MODE_SENSE6_CONTROL_PAGE_LEN); + break; + case MODESENSE_READ_WRITE_ERROR_RECOVERY_PAGE: /* Read-Write Error Recovery */ + lenRead = (bit8)MIN(requestLen, MODE_SENSE6_READ_WRITE_ERROR_RECOVERY_PAGE_LEN); + break; + case MODESENSE_CACHING: /* caching */ + lenRead = (bit8)MIN(requestLen, MODE_SENSE6_CACHING_LEN); + break; + case MODESENSE_INFORMATION_EXCEPTION_CONTROL_PAGE: /* informational exceptions control*/ + lenRead = (bit8)MIN(requestLen, MODE_SENSE6_INFORMATION_EXCEPTION_CONTROL_PAGE_LEN); + break; + default: + TI_DBG1(("satModeSense6: default error page %d\n", page)); + break; + } + + if (page == MODESENSE_RETURN_ALL_PAGES) + { + TI_DBG5(("satModeSense6: MODESENSE_RETURN_ALL_PAGES\n")); + AllPages[0] = (bit8)(lenRead - 1); + AllPages[1] = 0x00; /* default medium type (currently mounted medium type) */ + AllPages[2] = 0x00; /* no write-protect, no support for DPO-FUA */ + AllPages[3] = 0x08; /* block descriptor length */ + + /* + * Fill-up direct-access device block-descriptor, SAT, Table 19 + */ + + /* density code */ + AllPages[4] = 0x04; /* density-code : reserved for direct-access */ + /* number of blocks */ + AllPages[5] = 0x00; /* unspecified */ + AllPages[6] = 0x00; /* unspecified */ + AllPages[7] = 0x00; /* unspecified */ + /* reserved */ + AllPages[8] = 0x00; /* reserved */ + /* Block size */ + AllPages[9] = 0x00; + AllPages[10] = 0x02; /* Block size is always 512 bytes */ + AllPages[11] = 0x00; + + /* MODESENSE_READ_WRITE_ERROR_RECOVERY_PAGE */ + AllPages[12] = 0x01; /* page code */ + AllPages[13] = 0x0A; /* page length */ + AllPages[14] = 0x40; /* ARRE is set */ + AllPages[15] = 0x00; + AllPages[16] = 0x00; + AllPages[17] = 0x00; + AllPages[18] = 0x00; + AllPages[19] = 0x00; + AllPages[20] = 0x00; + AllPages[21] = 0x00; + AllPages[22] = 0x00; + AllPages[23] = 0x00; + /* MODESENSE_CACHING */ + AllPages[24] = 0x08; /* page code */ + AllPages[25] = 0x12; /* page length */ +#ifdef NOT_YET + if (pSatDevData->satWriteCacheEnabled == agTRUE) + { + AllPages[26] = 0x04;/* WCE bit is set */ + } + else + { + AllPages[26] = 0x00;/* WCE bit is NOT set */ + } +#endif + AllPages[26] = 0x00;/* WCE bit is NOT set */ + + AllPages[27] = 0x00; + AllPages[28] = 0x00; + AllPages[29] = 0x00; + AllPages[30] = 0x00; + AllPages[31] = 0x00; + AllPages[32] = 0x00; + AllPages[33] = 0x00; + AllPages[34] = 0x00; + AllPages[35] = 0x00; + if (pSatDevData->satLookAheadEnabled == agTRUE) + { + AllPages[36] = 0x00;/* DRA bit is NOT set */ + } + else + { + AllPages[36] = 0x20;/* DRA bit is set */ + } + AllPages[37] = 0x00; + AllPages[38] = 0x00; + AllPages[39] = 0x00; + AllPages[40] = 0x00; + AllPages[41] = 0x00; + AllPages[42] = 0x00; + AllPages[43] = 0x00; + /* MODESENSE_CONTROL_PAGE */ + AllPages[44] = 0x0A; /* page code */ + AllPages[45] = 0x0A; /* page length */ + AllPages[46] = 0x02; /* only GLTSD bit is set */ + if (pSatDevData->satNCQ == agTRUE) + { + AllPages[47] = 0x12; /* Queue Alogorithm modifier 1b and QErr 01b*/ + } + else + { + AllPages[47] = 0x02; /* Queue Alogorithm modifier 0b and QErr 01b */ + } + AllPages[48] = 0x00; + AllPages[49] = 0x00; + AllPages[50] = 0x00; /* obsolete */ + AllPages[51] = 0x00; /* obsolete */ + AllPages[52] = 0xFF; /* Busy Timeout Period */ + AllPages[53] = 0xFF; /* Busy Timeout Period */ + AllPages[54] = 0x00; /* we don't support non-000b value for the self-test code */ + AllPages[55] = 0x00; /* we don't support non-000b value for the self-test code */ + /* MODESENSE_INFORMATION_EXCEPTION_CONTROL_PAGE */ + AllPages[56] = 0x1C; /* page code */ + AllPages[57] = 0x0A; /* page length */ + if (pSatDevData->satSMARTEnabled == agTRUE) + { + AllPages[58] = 0x00;/* DEXCPT bit is NOT set */ + } + else + { + AllPages[58] = 0x08;/* DEXCPT bit is set */ + } + AllPages[59] = 0x00; /* We don't support MRIE */ + AllPages[60] = 0x00; /* Interval timer vendor-specific */ + AllPages[61] = 0x00; + AllPages[62] = 0x00; + AllPages[63] = 0x00; + AllPages[64] = 0x00; /* REPORT-COUNT */ + AllPages[65] = 0x00; + AllPages[66] = 0x00; + AllPages[67] = 0x00; + + osti_memcpy(pModeSense, &AllPages, lenRead); + } + else if (page == MODESENSE_CONTROL_PAGE) + { + TI_DBG5(("satModeSense6: MODESENSE_CONTROL_PAGE\n")); + Control[0] = MODE_SENSE6_CONTROL_PAGE_LEN - 1; + Control[1] = 0x00; /* default medium type (currently mounted medium type) */ + Control[2] = 0x00; /* no write-protect, no support for DPO-FUA */ + Control[3] = 0x08; /* block descriptor length */ + /* + * Fill-up direct-access device block-descriptor, SAT, Table 19 + */ + + /* density code */ + Control[4] = 0x04; /* density-code : reserved for direct-access */ + /* number of blocks */ + Control[5] = 0x00; /* unspecified */ + Control[6] = 0x00; /* unspecified */ + Control[7] = 0x00; /* unspecified */ + /* reserved */ + Control[8] = 0x00; /* reserved */ + /* Block size */ + Control[9] = 0x00; + Control[10] = 0x02; /* Block size is always 512 bytes */ + Control[11] = 0x00; + /* + * Fill-up control mode page, SAT, Table 65 + */ + Control[12] = 0x0A; /* page code */ + Control[13] = 0x0A; /* page length */ + Control[14] = 0x02; /* only GLTSD bit is set */ + if (pSatDevData->satNCQ == agTRUE) + { + Control[15] = 0x12; /* Queue Alogorithm modifier 1b and QErr 01b*/ + } + else + { + Control[15] = 0x02; /* Queue Alogorithm modifier 0b and QErr 01b */ + } + Control[16] = 0x00; + Control[17] = 0x00; + Control[18] = 0x00; /* obsolete */ + Control[19] = 0x00; /* obsolete */ + Control[20] = 0xFF; /* Busy Timeout Period */ + Control[21] = 0xFF; /* Busy Timeout Period */ + Control[22] = 0x00; /* we don't support non-000b value for the self-test code */ + Control[23] = 0x00; /* we don't support non-000b value for the self-test code */ + + osti_memcpy(pModeSense, &Control, lenRead); + + } + else if (page == MODESENSE_READ_WRITE_ERROR_RECOVERY_PAGE) + { + TI_DBG5(("satModeSense6: MODESENSE_READ_WRITE_ERROR_RECOVERY_PAGE\n")); + RWErrorRecovery[0] = MODE_SENSE6_READ_WRITE_ERROR_RECOVERY_PAGE_LEN - 1; + RWErrorRecovery[1] = 0x00; /* default medium type (currently mounted medium type) */ + RWErrorRecovery[2] = 0x00; /* no write-protect, no support for DPO-FUA */ + RWErrorRecovery[3] = 0x08; /* block descriptor length */ + /* + * Fill-up direct-access device block-descriptor, SAT, Table 19 + */ + + /* density code */ + RWErrorRecovery[4] = 0x04; /* density-code : reserved for direct-access */ + /* number of blocks */ + RWErrorRecovery[5] = 0x00; /* unspecified */ + RWErrorRecovery[6] = 0x00; /* unspecified */ + RWErrorRecovery[7] = 0x00; /* unspecified */ + /* reserved */ + RWErrorRecovery[8] = 0x00; /* reserved */ + /* Block size */ + RWErrorRecovery[9] = 0x00; + RWErrorRecovery[10] = 0x02; /* Block size is always 512 bytes */ + RWErrorRecovery[11] = 0x00; + /* + * Fill-up Read-Write Error Recovery mode page, SAT, Table 66 + */ + RWErrorRecovery[12] = 0x01; /* page code */ + RWErrorRecovery[13] = 0x0A; /* page length */ + RWErrorRecovery[14] = 0x40; /* ARRE is set */ + RWErrorRecovery[15] = 0x00; + RWErrorRecovery[16] = 0x00; + RWErrorRecovery[17] = 0x00; + RWErrorRecovery[18] = 0x00; + RWErrorRecovery[19] = 0x00; + RWErrorRecovery[20] = 0x00; + RWErrorRecovery[21] = 0x00; + RWErrorRecovery[22] = 0x00; + RWErrorRecovery[23] = 0x00; + + osti_memcpy(pModeSense, &RWErrorRecovery, lenRead); + + } + else if (page == MODESENSE_CACHING) + { + TI_DBG5(("satModeSense6: MODESENSE_CACHING\n")); + /* special case */ + if (requestLen == 4 && page == MODESENSE_CACHING) + { + TI_DBG5(("satModeSense6: linux 2.6.8.24 support\n")); + + pModeSense[0] = 0x20 - 1; /* 32 - 1 */ + pModeSense[1] = 0x00; /* default medium type (currently mounted medium type) */ + pModeSense[2] = 0x00; /* no write-protect, no support for DPO-FUA */ + pModeSense[3] = 0x08; /* block descriptor length */ + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + return tiSuccess; + } + Caching[0] = MODE_SENSE6_CACHING_LEN - 1; + Caching[1] = 0x00; /* default medium type (currently mounted medium type) */ + Caching[2] = 0x00; /* no write-protect, no support for DPO-FUA */ + Caching[3] = 0x08; /* block descriptor length */ + /* + * Fill-up direct-access device block-descriptor, SAT, Table 19 + */ + + /* density code */ + Caching[4] = 0x04; /* density-code : reserved for direct-access */ + /* number of blocks */ + Caching[5] = 0x00; /* unspecified */ + Caching[6] = 0x00; /* unspecified */ + Caching[7] = 0x00; /* unspecified */ + /* reserved */ + Caching[8] = 0x00; /* reserved */ + /* Block size */ + Caching[9] = 0x00; + Caching[10] = 0x02; /* Block size is always 512 bytes */ + Caching[11] = 0x00; + /* + * Fill-up Caching mode page, SAT, Table 67 + */ + /* length 20 */ + Caching[12] = 0x08; /* page code */ + Caching[13] = 0x12; /* page length */ +#ifdef NOT_YET + if (pSatDevData->satWriteCacheEnabled == agTRUE) + { + Caching[14] = 0x04;/* WCE bit is set */ + } + else + { + Caching[14] = 0x00;/* WCE bit is NOT set */ + } +#endif + Caching[14] = 0x00;/* WCE bit is NOT set */ + + Caching[15] = 0x00; + Caching[16] = 0x00; + Caching[17] = 0x00; + Caching[18] = 0x00; + Caching[19] = 0x00; + Caching[20] = 0x00; + Caching[21] = 0x00; + Caching[22] = 0x00; + Caching[23] = 0x00; + if (pSatDevData->satLookAheadEnabled == agTRUE) + { + Caching[24] = 0x00;/* DRA bit is NOT set */ + } + else + { + Caching[24] = 0x20;/* DRA bit is set */ + } + Caching[25] = 0x00; + Caching[26] = 0x00; + Caching[27] = 0x00; + Caching[28] = 0x00; + Caching[29] = 0x00; + Caching[30] = 0x00; + Caching[31] = 0x00; + + osti_memcpy(pModeSense, &Caching, lenRead); + + } + else if (page == MODESENSE_INFORMATION_EXCEPTION_CONTROL_PAGE) + { + TI_DBG5(("satModeSense6: MODESENSE_INFORMATION_EXCEPTION_CONTROL_PAGE\n")); + InfoExceptionCtrl[0] = MODE_SENSE6_INFORMATION_EXCEPTION_CONTROL_PAGE_LEN - 1; + InfoExceptionCtrl[1] = 0x00; /* default medium type (currently mounted medium type) */ + InfoExceptionCtrl[2] = 0x00; /* no write-protect, no support for DPO-FUA */ + InfoExceptionCtrl[3] = 0x08; /* block descriptor length */ + /* + * Fill-up direct-access device block-descriptor, SAT, Table 19 + */ + + /* density code */ + InfoExceptionCtrl[4] = 0x04; /* density-code : reserved for direct-access */ + /* number of blocks */ + InfoExceptionCtrl[5] = 0x00; /* unspecified */ + InfoExceptionCtrl[6] = 0x00; /* unspecified */ + InfoExceptionCtrl[7] = 0x00; /* unspecified */ + /* reserved */ + InfoExceptionCtrl[8] = 0x00; /* reserved */ + /* Block size */ + InfoExceptionCtrl[9] = 0x00; + InfoExceptionCtrl[10] = 0x02; /* Block size is always 512 bytes */ + InfoExceptionCtrl[11] = 0x00; + /* + * Fill-up informational-exceptions control mode page, SAT, Table 68 + */ + InfoExceptionCtrl[12] = 0x1C; /* page code */ + InfoExceptionCtrl[13] = 0x0A; /* page length */ + if (pSatDevData->satSMARTEnabled == agTRUE) + { + InfoExceptionCtrl[14] = 0x00;/* DEXCPT bit is NOT set */ + } + else + { + InfoExceptionCtrl[14] = 0x08;/* DEXCPT bit is set */ + } + InfoExceptionCtrl[15] = 0x00; /* We don't support MRIE */ + InfoExceptionCtrl[16] = 0x00; /* Interval timer vendor-specific */ + InfoExceptionCtrl[17] = 0x00; + InfoExceptionCtrl[18] = 0x00; + InfoExceptionCtrl[19] = 0x00; + InfoExceptionCtrl[20] = 0x00; /* REPORT-COUNT */ + InfoExceptionCtrl[21] = 0x00; + InfoExceptionCtrl[22] = 0x00; + InfoExceptionCtrl[23] = 0x00; + osti_memcpy(pModeSense, &InfoExceptionCtrl, lenRead); + + } + else + { + /* Error */ + TI_DBG1(("satModeSense6: Error page %d\n", page)); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_COMMAND, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + + /* there can be only underrun not overrun in error case */ + if (requestLen > lenRead) + { + TI_DBG6(("satModeSense6 reporting underrun lenRead=0x%x requestLen=0x%x tiIORequest=%p\n", lenRead, requestLen, tiIORequest)); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOUnderRun, + requestLen - lenRead, + agNULL, + satIOContext->interruptContext ); + + + } + else + { + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + } + + return tiSuccess; + +} + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI MODE SENSE (10). + * + * SAT implementation for SCSI MODE SENSE (10). + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satModeSense10( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + + scsiRspSense_t *pSense; + bit32 requestLen; + tiIniScsiCmnd_t *scsiCmnd; + bit32 pageSupported; + bit8 page; + bit8 *pModeSense; /* Mode Sense data buffer */ + satDeviceData_t *pSatDevData; + bit8 PC; /* page control */ + bit8 LLBAA; /* Long LBA Accepted */ + bit32 index; + bit8 AllPages[MODE_SENSE10_RETURN_ALL_PAGES_LLBAA_LEN]; + bit8 Control[MODE_SENSE10_CONTROL_PAGE_LLBAA_LEN]; + bit8 RWErrorRecovery[MODE_SENSE10_READ_WRITE_ERROR_RECOVERY_PAGE_LLBAA_LEN]; + bit8 Caching[MODE_SENSE10_CACHING_LLBAA_LEN]; + bit8 InfoExceptionCtrl[MODE_SENSE10_INFORMATION_EXCEPTION_CONTROL_PAGE_LLBAA_LEN]; + bit8 lenRead = 0; + + TI_DBG5(("satModeSense10 entry: tiDeviceHandle=%p tiIORequest=%p\n", + tiDeviceHandle, tiIORequest)); + + pSense = satIOContext->pSense; + scsiCmnd = &tiScsiRequest->scsiCmnd; + pModeSense = (bit8 *) tiScsiRequest->sglVirtualAddr; + pSatDevData = satIOContext->pSatDevData; + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[9] & SCSI_NACA_MASK) || (scsiCmnd->cdb[9] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG2(("satModeSense10: return control\n")); + return tiSuccess; + } + + /* checking PC(Page Control) + SAT revion 8, 8.5.3 p33 and 10.1.2, p66 + */ + PC = (bit8)((scsiCmnd->cdb[2]) & SCSI_MODE_SENSE10_PC_MASK); + if (PC != 0) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satModeSense10: return due to PC value pc 0x%x\n", PC)); + return tiSuccess; + } + /* finding LLBAA bit */ + LLBAA = (bit8)((scsiCmnd->cdb[1]) & SCSI_MODE_SENSE10_LLBAA_MASK); + /* reading PAGE CODE */ + page = (bit8)((scsiCmnd->cdb[2]) & SCSI_MODE_SENSE10_PAGE_CODE_MASK); + + TI_DBG5(("satModeSense10: page=0x%x, tiDeviceHandle=%p tiIORequest=%p\n", + page, tiDeviceHandle, tiIORequest)); + requestLen = (scsiCmnd->cdb[7] << 8) + scsiCmnd->cdb[8]; + + /* + Based on page code value, returns a corresponding mode page + note: no support for subpage + */ + switch(page) + { + case MODESENSE_RETURN_ALL_PAGES: /* return all pages */ + case MODESENSE_CONTROL_PAGE: /* control */ + case MODESENSE_READ_WRITE_ERROR_RECOVERY_PAGE: /* Read-Write Error Recovery */ + case MODESENSE_CACHING: /* caching */ + case MODESENSE_INFORMATION_EXCEPTION_CONTROL_PAGE: /* informational exceptions control*/ + pageSupported = agTRUE; + break; + case MODESENSE_VENDOR_SPECIFIC_PAGE: /* vendor specific */ + default: + pageSupported = agFALSE; + break; + } + + if (pageSupported == agFALSE) + { + + TI_DBG1(("satModeSense10 *** ERROR *** not supported page 0x%x tiDeviceHandle=%p tiIORequest=%p\n", + page, tiDeviceHandle, tiIORequest)); + + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_COMMAND, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + + switch(page) + { + case MODESENSE_RETURN_ALL_PAGES: + if (LLBAA) + { + lenRead = (bit8)MIN(requestLen, MODE_SENSE10_RETURN_ALL_PAGES_LLBAA_LEN); + } + else + { + lenRead = (bit8)MIN(requestLen, MODE_SENSE10_RETURN_ALL_PAGES_LEN); + } + break; + case MODESENSE_CONTROL_PAGE: /* control */ + if (LLBAA) + { + lenRead = (bit8)MIN(requestLen, MODE_SENSE10_CONTROL_PAGE_LLBAA_LEN); + } + else + { + lenRead = (bit8)MIN(requestLen, MODE_SENSE10_CONTROL_PAGE_LEN); + } + break; + case MODESENSE_READ_WRITE_ERROR_RECOVERY_PAGE: /* Read-Write Error Recovery */ + if (LLBAA) + { + lenRead = (bit8)MIN(requestLen, MODE_SENSE10_READ_WRITE_ERROR_RECOVERY_PAGE_LLBAA_LEN); + } + else + { + lenRead = (bit8)MIN(requestLen, MODE_SENSE10_READ_WRITE_ERROR_RECOVERY_PAGE_LEN); + } + break; + case MODESENSE_CACHING: /* caching */ + if (LLBAA) + { + lenRead = (bit8)MIN(requestLen, MODE_SENSE10_CACHING_LLBAA_LEN); + } + else + { + lenRead = (bit8)MIN(requestLen, MODE_SENSE10_CACHING_LEN); + } + break; + case MODESENSE_INFORMATION_EXCEPTION_CONTROL_PAGE: /* informational exceptions control*/ + if (LLBAA) + { + lenRead = (bit8)MIN(requestLen, MODE_SENSE10_INFORMATION_EXCEPTION_CONTROL_PAGE_LLBAA_LEN); + } + else + { + lenRead = (bit8)MIN(requestLen, MODE_SENSE10_INFORMATION_EXCEPTION_CONTROL_PAGE_LEN); + } + break; + default: + TI_DBG1(("satModeSense10: default error page %d\n", page)); + break; + } + + if (page == MODESENSE_RETURN_ALL_PAGES) + { + TI_DBG5(("satModeSense10: MODESENSE_RETURN_ALL_PAGES\n")); + AllPages[0] = 0; + AllPages[1] = (bit8)(lenRead - 2); + AllPages[2] = 0x00; /* medium type: default medium type (currently mounted medium type) */ + AllPages[3] = 0x00; /* device-specific param: no write-protect, no support for DPO-FUA */ + if (LLBAA) + { + AllPages[4] = 0x00; /* reserved and LONGLBA */ + AllPages[4] = (bit8)(AllPages[4] | 0x1); /* LONGLBA is set */ + } + else + { + AllPages[4] = 0x00; /* reserved and LONGLBA: LONGLBA is not set */ + } + AllPages[5] = 0x00; /* reserved */ + AllPages[6] = 0x00; /* block descriptot length */ + if (LLBAA) + { + AllPages[7] = 0x10; /* block descriptor length: LONGLBA is set. So, length is 16 */ + } + else + { + AllPages[7] = 0x08; /* block descriptor length: LONGLBA is NOT set. So, length is 8 */ + } + + /* + * Fill-up direct-access device block-descriptor, SAT, Table 19 + */ + + if (LLBAA) + { + /* density code */ + AllPages[8] = 0x04; /* density-code : reserved for direct-access */ + /* number of blocks */ + AllPages[9] = 0x00; /* unspecified */ + AllPages[10] = 0x00; /* unspecified */ + AllPages[11] = 0x00; /* unspecified */ + AllPages[12] = 0x00; /* unspecified */ + AllPages[13] = 0x00; /* unspecified */ + AllPages[14] = 0x00; /* unspecified */ + AllPages[15] = 0x00; /* unspecified */ + /* reserved */ + AllPages[16] = 0x00; /* reserved */ + AllPages[17] = 0x00; /* reserved */ + AllPages[18] = 0x00; /* reserved */ + AllPages[19] = 0x00; /* reserved */ + /* Block size */ + AllPages[20] = 0x00; + AllPages[21] = 0x00; + AllPages[22] = 0x02; /* Block size is always 512 bytes */ + AllPages[23] = 0x00; + } + else + { + /* density code */ + AllPages[8] = 0x04; /* density-code : reserved for direct-access */ + /* number of blocks */ + AllPages[9] = 0x00; /* unspecified */ + AllPages[10] = 0x00; /* unspecified */ + AllPages[11] = 0x00; /* unspecified */ + /* reserved */ + AllPages[12] = 0x00; /* reserved */ + /* Block size */ + AllPages[13] = 0x00; + AllPages[14] = 0x02; /* Block size is always 512 bytes */ + AllPages[15] = 0x00; + } + + if (LLBAA) + { + index = 24; + } + else + { + index = 16; + } + /* MODESENSE_READ_WRITE_ERROR_RECOVERY_PAGE */ + AllPages[index+0] = 0x01; /* page code */ + AllPages[index+1] = 0x0A; /* page length */ + AllPages[index+2] = 0x40; /* ARRE is set */ + AllPages[index+3] = 0x00; + AllPages[index+4] = 0x00; + AllPages[index+5] = 0x00; + AllPages[index+6] = 0x00; + AllPages[index+7] = 0x00; + AllPages[index+8] = 0x00; + AllPages[index+9] = 0x00; + AllPages[index+10] = 0x00; + AllPages[index+11] = 0x00; + + /* MODESENSE_CACHING */ + /* + * Fill-up Caching mode page, SAT, Table 67 + */ + /* length 20 */ + AllPages[index+12] = 0x08; /* page code */ + AllPages[index+13] = 0x12; /* page length */ +#ifdef NOT_YET + if (pSatDevData->satWriteCacheEnabled == agTRUE) + { + AllPages[index+14] = 0x04;/* WCE bit is set */ + } + else + { + AllPages[index+14] = 0x00;/* WCE bit is NOT set */ + } +#endif + AllPages[index+14] = 0x00;/* WCE bit is NOT set */ + AllPages[index+15] = 0x00; + AllPages[index+16] = 0x00; + AllPages[index+17] = 0x00; + AllPages[index+18] = 0x00; + AllPages[index+19] = 0x00; + AllPages[index+20] = 0x00; + AllPages[index+21] = 0x00; + AllPages[index+22] = 0x00; + AllPages[index+23] = 0x00; + if (pSatDevData->satLookAheadEnabled == agTRUE) + { + AllPages[index+24] = 0x00;/* DRA bit is NOT set */ + } + else + { + AllPages[index+24] = 0x20;/* DRA bit is set */ + } + AllPages[index+25] = 0x00; + AllPages[index+26] = 0x00; + AllPages[index+27] = 0x00; + AllPages[index+28] = 0x00; + AllPages[index+29] = 0x00; + AllPages[index+30] = 0x00; + AllPages[index+31] = 0x00; + + /* MODESENSE_CONTROL_PAGE */ + /* + * Fill-up control mode page, SAT, Table 65 + */ + AllPages[index+32] = 0x0A; /* page code */ + AllPages[index+33] = 0x0A; /* page length */ + AllPages[index+34] = 0x02; /* only GLTSD bit is set */ + if (pSatDevData->satNCQ == agTRUE) + { + AllPages[index+35] = 0x12; /* Queue Alogorithm modifier 1b and QErr 01b*/ + } + else + { + AllPages[index+35] = 0x02; /* Queue Alogorithm modifier 0b and QErr 01b */ + } + AllPages[index+36] = 0x00; + AllPages[index+37] = 0x00; + AllPages[index+38] = 0x00; /* obsolete */ + AllPages[index+39] = 0x00; /* obsolete */ + AllPages[index+40] = 0xFF; /* Busy Timeout Period */ + AllPages[index+41] = 0xFF; /* Busy Timeout Period */ + AllPages[index+42] = 0x00; /* we don't support non-000b value for the self-test code */ + AllPages[index+43] = 0x00; /* we don't support non-000b value for the self-test code */ + + /* MODESENSE_INFORMATION_EXCEPTION_CONTROL_PAGE */ + /* + * Fill-up informational-exceptions control mode page, SAT, Table 68 + */ + AllPages[index+44] = 0x1C; /* page code */ + AllPages[index+45] = 0x0A; /* page length */ + if (pSatDevData->satSMARTEnabled == agTRUE) + { + AllPages[index+46] = 0x00;/* DEXCPT bit is NOT set */ + } + else + { + AllPages[index+46] = 0x08;/* DEXCPT bit is set */ + } + AllPages[index+47] = 0x00; /* We don't support MRIE */ + AllPages[index+48] = 0x00; /* Interval timer vendor-specific */ + AllPages[index+49] = 0x00; + AllPages[index+50] = 0x00; + AllPages[index+51] = 0x00; + AllPages[index+52] = 0x00; /* REPORT-COUNT */ + AllPages[index+53] = 0x00; + AllPages[index+54] = 0x00; + AllPages[index+55] = 0x00; + + osti_memcpy(pModeSense, &AllPages, lenRead); + } + else if (page == MODESENSE_CONTROL_PAGE) + { + TI_DBG5(("satModeSense10: MODESENSE_CONTROL_PAGE\n")); + Control[0] = 0; + Control[1] = (bit8)(lenRead - 2); + Control[2] = 0x00; /* medium type: default medium type (currently mounted medium type) */ + Control[3] = 0x00; /* device-specific param: no write-protect, no support for DPO-FUA */ + if (LLBAA) + { + Control[4] = 0x00; /* reserved and LONGLBA */ + Control[4] = (bit8)(Control[4] | 0x1); /* LONGLBA is set */ + } + else + { + Control[4] = 0x00; /* reserved and LONGLBA: LONGLBA is not set */ + } + Control[5] = 0x00; /* reserved */ + Control[6] = 0x00; /* block descriptot length */ + if (LLBAA) + { + Control[7] = 0x10; /* block descriptor length: LONGLBA is set. So, length is 16 */ + } + else + { + Control[7] = 0x08; /* block descriptor length: LONGLBA is NOT set. So, length is 8 */ + } + + /* + * Fill-up direct-access device block-descriptor, SAT, Table 19 + */ + + if (LLBAA) + { + /* density code */ + Control[8] = 0x04; /* density-code : reserved for direct-access */ + /* number of blocks */ + Control[9] = 0x00; /* unspecified */ + Control[10] = 0x00; /* unspecified */ + Control[11] = 0x00; /* unspecified */ + Control[12] = 0x00; /* unspecified */ + Control[13] = 0x00; /* unspecified */ + Control[14] = 0x00; /* unspecified */ + Control[15] = 0x00; /* unspecified */ + /* reserved */ + Control[16] = 0x00; /* reserved */ + Control[17] = 0x00; /* reserved */ + Control[18] = 0x00; /* reserved */ + Control[19] = 0x00; /* reserved */ + /* Block size */ + Control[20] = 0x00; + Control[21] = 0x00; + Control[22] = 0x02; /* Block size is always 512 bytes */ + Control[23] = 0x00; + } + else + { + /* density code */ + Control[8] = 0x04; /* density-code : reserved for direct-access */ + /* number of blocks */ + Control[9] = 0x00; /* unspecified */ + Control[10] = 0x00; /* unspecified */ + Control[11] = 0x00; /* unspecified */ + /* reserved */ + Control[12] = 0x00; /* reserved */ + /* Block size */ + Control[13] = 0x00; + Control[14] = 0x02; /* Block size is always 512 bytes */ + Control[15] = 0x00; + } + + if (LLBAA) + { + index = 24; + } + else + { + index = 16; + } + /* + * Fill-up control mode page, SAT, Table 65 + */ + Control[index+0] = 0x0A; /* page code */ + Control[index+1] = 0x0A; /* page length */ + Control[index+2] = 0x02; /* only GLTSD bit is set */ + if (pSatDevData->satNCQ == agTRUE) + { + Control[index+3] = 0x12; /* Queue Alogorithm modifier 1b and QErr 01b*/ + } + else + { + Control[index+3] = 0x02; /* Queue Alogorithm modifier 0b and QErr 01b */ + } + Control[index+4] = 0x00; + Control[index+5] = 0x00; + Control[index+6] = 0x00; /* obsolete */ + Control[index+7] = 0x00; /* obsolete */ + Control[index+8] = 0xFF; /* Busy Timeout Period */ + Control[index+9] = 0xFF; /* Busy Timeout Period */ + Control[index+10] = 0x00; /* we don't support non-000b value for the self-test code */ + Control[index+11] = 0x00; /* we don't support non-000b value for the self-test code */ + + osti_memcpy(pModeSense, &Control, lenRead); + } + else if (page == MODESENSE_READ_WRITE_ERROR_RECOVERY_PAGE) + { + TI_DBG5(("satModeSense10: MODESENSE_READ_WRITE_ERROR_RECOVERY_PAGE\n")); + RWErrorRecovery[0] = 0; + RWErrorRecovery[1] = (bit8)(lenRead - 2); + RWErrorRecovery[2] = 0x00; /* medium type: default medium type (currently mounted medium type) */ + RWErrorRecovery[3] = 0x00; /* device-specific param: no write-protect, no support for DPO-FUA */ + if (LLBAA) + { + RWErrorRecovery[4] = 0x00; /* reserved and LONGLBA */ + RWErrorRecovery[4] = (bit8)(RWErrorRecovery[4] | 0x1); /* LONGLBA is set */ + } + else + { + RWErrorRecovery[4] = 0x00; /* reserved and LONGLBA: LONGLBA is not set */ + } + RWErrorRecovery[5] = 0x00; /* reserved */ + RWErrorRecovery[6] = 0x00; /* block descriptot length */ + if (LLBAA) + { + RWErrorRecovery[7] = 0x10; /* block descriptor length: LONGLBA is set. So, length is 16 */ + } + else + { + RWErrorRecovery[7] = 0x08; /* block descriptor length: LONGLBA is NOT set. So, length is 8 */ + } + + /* + * Fill-up direct-access device block-descriptor, SAT, Table 19 + */ + + if (LLBAA) + { + /* density code */ + RWErrorRecovery[8] = 0x04; /* density-code : reserved for direct-access */ + /* number of blocks */ + RWErrorRecovery[9] = 0x00; /* unspecified */ + RWErrorRecovery[10] = 0x00; /* unspecified */ + RWErrorRecovery[11] = 0x00; /* unspecified */ + RWErrorRecovery[12] = 0x00; /* unspecified */ + RWErrorRecovery[13] = 0x00; /* unspecified */ + RWErrorRecovery[14] = 0x00; /* unspecified */ + RWErrorRecovery[15] = 0x00; /* unspecified */ + /* reserved */ + RWErrorRecovery[16] = 0x00; /* reserved */ + RWErrorRecovery[17] = 0x00; /* reserved */ + RWErrorRecovery[18] = 0x00; /* reserved */ + RWErrorRecovery[19] = 0x00; /* reserved */ + /* Block size */ + RWErrorRecovery[20] = 0x00; + RWErrorRecovery[21] = 0x00; + RWErrorRecovery[22] = 0x02; /* Block size is always 512 bytes */ + RWErrorRecovery[23] = 0x00; + } + else + { + /* density code */ + RWErrorRecovery[8] = 0x04; /* density-code : reserved for direct-access */ + /* number of blocks */ + RWErrorRecovery[9] = 0x00; /* unspecified */ + RWErrorRecovery[10] = 0x00; /* unspecified */ + RWErrorRecovery[11] = 0x00; /* unspecified */ + /* reserved */ + RWErrorRecovery[12] = 0x00; /* reserved */ + /* Block size */ + RWErrorRecovery[13] = 0x00; + RWErrorRecovery[14] = 0x02; /* Block size is always 512 bytes */ + RWErrorRecovery[15] = 0x00; + } + + if (LLBAA) + { + index = 24; + } + else + { + index = 16; + } + /* + * Fill-up Read-Write Error Recovery mode page, SAT, Table 66 + */ + RWErrorRecovery[index+0] = 0x01; /* page code */ + RWErrorRecovery[index+1] = 0x0A; /* page length */ + RWErrorRecovery[index+2] = 0x40; /* ARRE is set */ + RWErrorRecovery[index+3] = 0x00; + RWErrorRecovery[index+4] = 0x00; + RWErrorRecovery[index+5] = 0x00; + RWErrorRecovery[index+6] = 0x00; + RWErrorRecovery[index+7] = 0x00; + RWErrorRecovery[index+8] = 0x00; + RWErrorRecovery[index+9] = 0x00; + RWErrorRecovery[index+10] = 0x00; + RWErrorRecovery[index+11] = 0x00; + + osti_memcpy(pModeSense, &RWErrorRecovery, lenRead); + } + else if (page == MODESENSE_CACHING) + { + TI_DBG5(("satModeSense10: MODESENSE_CACHING\n")); + Caching[0] = 0; + Caching[1] = (bit8)(lenRead - 2); + Caching[2] = 0x00; /* medium type: default medium type (currently mounted medium type) */ + Caching[3] = 0x00; /* device-specific param: no write-protect, no support for DPO-FUA */ + if (LLBAA) + { + Caching[4] = 0x00; /* reserved and LONGLBA */ + Caching[4] = (bit8)(Caching[4] | 0x1); /* LONGLBA is set */ + } + else + { + Caching[4] = 0x00; /* reserved and LONGLBA: LONGLBA is not set */ + } + Caching[5] = 0x00; /* reserved */ + Caching[6] = 0x00; /* block descriptot length */ + if (LLBAA) + { + Caching[7] = 0x10; /* block descriptor length: LONGLBA is set. So, length is 16 */ + } + else + { + Caching[7] = 0x08; /* block descriptor length: LONGLBA is NOT set. So, length is 8 */ + } + + /* + * Fill-up direct-access device block-descriptor, SAT, Table 19 + */ + + if (LLBAA) + { + /* density code */ + Caching[8] = 0x04; /* density-code : reserved for direct-access */ + /* number of blocks */ + Caching[9] = 0x00; /* unspecified */ + Caching[10] = 0x00; /* unspecified */ + Caching[11] = 0x00; /* unspecified */ + Caching[12] = 0x00; /* unspecified */ + Caching[13] = 0x00; /* unspecified */ + Caching[14] = 0x00; /* unspecified */ + Caching[15] = 0x00; /* unspecified */ + /* reserved */ + Caching[16] = 0x00; /* reserved */ + Caching[17] = 0x00; /* reserved */ + Caching[18] = 0x00; /* reserved */ + Caching[19] = 0x00; /* reserved */ + /* Block size */ + Caching[20] = 0x00; + Caching[21] = 0x00; + Caching[22] = 0x02; /* Block size is always 512 bytes */ + Caching[23] = 0x00; + } + else + { + /* density code */ + Caching[8] = 0x04; /* density-code : reserved for direct-access */ + /* number of blocks */ + Caching[9] = 0x00; /* unspecified */ + Caching[10] = 0x00; /* unspecified */ + Caching[11] = 0x00; /* unspecified */ + /* reserved */ + Caching[12] = 0x00; /* reserved */ + /* Block size */ + Caching[13] = 0x00; + Caching[14] = 0x02; /* Block size is always 512 bytes */ + Caching[15] = 0x00; + } + + if (LLBAA) + { + index = 24; + } + else + { + index = 16; + } + /* + * Fill-up Caching mode page, SAT, Table 67 + */ + /* length 20 */ + Caching[index+0] = 0x08; /* page code */ + Caching[index+1] = 0x12; /* page length */ +#ifdef NOT_YET + if (pSatDevData->satWriteCacheEnabled == agTRUE) + { + Caching[index+2] = 0x04;/* WCE bit is set */ + } + else + { + Caching[index+2] = 0x00;/* WCE bit is NOT set */ + } +#endif + Caching[index+2] = 0x00;/* WCE bit is NOT set */ + Caching[index+3] = 0x00; + Caching[index+4] = 0x00; + Caching[index+5] = 0x00; + Caching[index+6] = 0x00; + Caching[index+7] = 0x00; + Caching[index+8] = 0x00; + Caching[index+9] = 0x00; + Caching[index+10] = 0x00; + Caching[index+11] = 0x00; + if (pSatDevData->satLookAheadEnabled == agTRUE) + { + Caching[index+12] = 0x00;/* DRA bit is NOT set */ + } + else + { + Caching[index+12] = 0x20;/* DRA bit is set */ + } + Caching[index+13] = 0x00; + Caching[index+14] = 0x00; + Caching[index+15] = 0x00; + Caching[index+16] = 0x00; + Caching[index+17] = 0x00; + Caching[index+18] = 0x00; + Caching[index+19] = 0x00; + osti_memcpy(pModeSense, &Caching, lenRead); + + } + else if (page == MODESENSE_INFORMATION_EXCEPTION_CONTROL_PAGE) + { + TI_DBG5(("satModeSense10: MODESENSE_INFORMATION_EXCEPTION_CONTROL_PAGE\n")); + InfoExceptionCtrl[0] = 0; + InfoExceptionCtrl[1] = (bit8)(lenRead - 2); + InfoExceptionCtrl[2] = 0x00; /* medium type: default medium type (currently mounted medium type) */ + InfoExceptionCtrl[3] = 0x00; /* device-specific param: no write-protect, no support for DPO-FUA */ + if (LLBAA) + { + InfoExceptionCtrl[4] = 0x00; /* reserved and LONGLBA */ + InfoExceptionCtrl[4] = (bit8)(InfoExceptionCtrl[4] | 0x1); /* LONGLBA is set */ + } + else + { + InfoExceptionCtrl[4] = 0x00; /* reserved and LONGLBA: LONGLBA is not set */ + } + InfoExceptionCtrl[5] = 0x00; /* reserved */ + InfoExceptionCtrl[6] = 0x00; /* block descriptot length */ + if (LLBAA) + { + InfoExceptionCtrl[7] = 0x10; /* block descriptor length: LONGLBA is set. So, length is 16 */ + } + else + { + InfoExceptionCtrl[7] = 0x08; /* block descriptor length: LONGLBA is NOT set. So, length is 8 */ + } + + /* + * Fill-up direct-access device block-descriptor, SAT, Table 19 + */ + + if (LLBAA) + { + /* density code */ + InfoExceptionCtrl[8] = 0x04; /* density-code : reserved for direct-access */ + /* number of blocks */ + InfoExceptionCtrl[9] = 0x00; /* unspecified */ + InfoExceptionCtrl[10] = 0x00; /* unspecified */ + InfoExceptionCtrl[11] = 0x00; /* unspecified */ + InfoExceptionCtrl[12] = 0x00; /* unspecified */ + InfoExceptionCtrl[13] = 0x00; /* unspecified */ + InfoExceptionCtrl[14] = 0x00; /* unspecified */ + InfoExceptionCtrl[15] = 0x00; /* unspecified */ + /* reserved */ + InfoExceptionCtrl[16] = 0x00; /* reserved */ + InfoExceptionCtrl[17] = 0x00; /* reserved */ + InfoExceptionCtrl[18] = 0x00; /* reserved */ + InfoExceptionCtrl[19] = 0x00; /* reserved */ + /* Block size */ + InfoExceptionCtrl[20] = 0x00; + InfoExceptionCtrl[21] = 0x00; + InfoExceptionCtrl[22] = 0x02; /* Block size is always 512 bytes */ + InfoExceptionCtrl[23] = 0x00; + } + else + { + /* density code */ + InfoExceptionCtrl[8] = 0x04; /* density-code : reserved for direct-access */ + /* number of blocks */ + InfoExceptionCtrl[9] = 0x00; /* unspecified */ + InfoExceptionCtrl[10] = 0x00; /* unspecified */ + InfoExceptionCtrl[11] = 0x00; /* unspecified */ + /* reserved */ + InfoExceptionCtrl[12] = 0x00; /* reserved */ + /* Block size */ + InfoExceptionCtrl[13] = 0x00; + InfoExceptionCtrl[14] = 0x02; /* Block size is always 512 bytes */ + InfoExceptionCtrl[15] = 0x00; + } + + if (LLBAA) + { + index = 24; + } + else + { + index = 16; + } + /* + * Fill-up informational-exceptions control mode page, SAT, Table 68 + */ + InfoExceptionCtrl[index+0] = 0x1C; /* page code */ + InfoExceptionCtrl[index+1] = 0x0A; /* page length */ + if (pSatDevData->satSMARTEnabled == agTRUE) + { + InfoExceptionCtrl[index+2] = 0x00;/* DEXCPT bit is NOT set */ + } + else + { + InfoExceptionCtrl[index+2] = 0x08;/* DEXCPT bit is set */ + } + InfoExceptionCtrl[index+3] = 0x00; /* We don't support MRIE */ + InfoExceptionCtrl[index+4] = 0x00; /* Interval timer vendor-specific */ + InfoExceptionCtrl[index+5] = 0x00; + InfoExceptionCtrl[index+6] = 0x00; + InfoExceptionCtrl[index+7] = 0x00; + InfoExceptionCtrl[index+8] = 0x00; /* REPORT-COUNT */ + InfoExceptionCtrl[index+9] = 0x00; + InfoExceptionCtrl[index+10] = 0x00; + InfoExceptionCtrl[index+11] = 0x00; + osti_memcpy(pModeSense, &InfoExceptionCtrl, lenRead); + + } + else + { + /* Error */ + TI_DBG1(("satModeSense10: Error page %d\n", page)); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_COMMAND, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + + if (requestLen > lenRead) + { + TI_DBG1(("satModeSense10 reporting underrun lenRead=0x%x requestLen=0x%x tiIORequest=%p\n", lenRead, requestLen, tiIORequest)); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOUnderRun, + requestLen - lenRead, + agNULL, + satIOContext->interruptContext ); + + + } + else + { + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + } + + return tiSuccess; +} + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI VERIFY (10). + * + * SAT implementation for SCSI VERIFY (10). + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satVerify10( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + /* + For simple implementation, + no byte comparison supported as of 4/5/06 + */ + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + satDeviceData_t *pSatDevData; + agsaFisRegHostToDevice_t *fis; + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + bit32 lba = 0; + bit32 tl = 0; + bit32 LoopNum = 1; + bit8 LBA[4]; + bit8 TL[4]; + bit32 rangeChk = agFALSE; /* lba and tl range check */ + + + TI_DBG5(("satVerify10 entry: tiDeviceHandle=%p tiIORequest=%p\n", + tiDeviceHandle, tiIORequest)); + + pSense = satIOContext->pSense; + scsiCmnd = &tiScsiRequest->scsiCmnd; + pSatDevData = satIOContext->pSatDevData; + fis = satIOContext->pFis; + + /* checking BYTCHK */ + if (scsiCmnd->cdb[1] & SCSI_VERIFY_BYTCHK_MASK) + { + /* + should do the byte check + but not supported in this version + */ + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satVerify10: no byte checking \n")); + return tiSuccess; + } + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[9] & SCSI_NACA_MASK) || (scsiCmnd->cdb[9] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG2(("satVerify10: return control\n")); + return tiSuccess; + } + + osti_memset(LBA, 0, sizeof(LBA)); + osti_memset(TL, 0, sizeof(TL)); + + /* do not use memcpy due to indexing in LBA and TL */ + LBA[0] = scsiCmnd->cdb[2]; /* MSB */ + LBA[1] = scsiCmnd->cdb[3]; + LBA[2] = scsiCmnd->cdb[4]; + LBA[3] = scsiCmnd->cdb[5]; /* LSB */ + + TL[0] = 0; + TL[1] = 0; + TL[2] = scsiCmnd->cdb[7]; /* MSB */ + TL[3] = scsiCmnd->cdb[8]; /* LSB */ + + rangeChk = satAddNComparebit32(LBA, TL); + + /* cbd10; computing LBA and transfer length */ + lba = (scsiCmnd->cdb[2] << (8*3)) + (scsiCmnd->cdb[3] << (8*2)) + + (scsiCmnd->cdb[4] << 8) + scsiCmnd->cdb[5]; + tl = (scsiCmnd->cdb[7] << 8) + scsiCmnd->cdb[8]; + + if (pSatDevData->satNCQ != agTRUE && + pSatDevData->sat48BitSupport != agTRUE + ) + { + if (lba > SAT_TR_LBA_LIMIT - 1) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satVerify10: return LBA out of range, not EXT\n")); + TI_DBG1(("satVerify10: cdb 0x%x 0x%x 0x%x 0x%x\n",scsiCmnd->cdb[2], scsiCmnd->cdb[3], + scsiCmnd->cdb[4], scsiCmnd->cdb[5])); + TI_DBG1(("satVerify10: lba 0x%x SAT_TR_LBA_LIMIT 0x%x\n", lba, SAT_TR_LBA_LIMIT)); + return tiSuccess; + } + + if (rangeChk) // if (lba + tl > SAT_TR_LBA_LIMIT) + { + TI_DBG1(("satVerify10: return LBA+TL out of range, not EXT\n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + return tiSuccess; + } + } + + if (pSatDevData->sat48BitSupport == agTRUE) + { + TI_DBG5(("satVerify10: SAT_READ_VERIFY_SECTORS_EXT\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_READ_VERIFY_SECTORS_EXT;/* 0x42 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set 01000000 */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[7]; /* FIS sector count (15:8) */ + + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + satIOContext->ATACmd = SAT_READ_VERIFY_SECTORS_EXT; + } + else + { + TI_DBG5(("satVerify10: SAT_READ_VERIFY_SECTORS\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS; /* 0x40 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (scsiCmnd->cdb[2] & 0xF)); + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + satIOContext->ATACmd = SAT_READ_VERIFY_SECTORS; + + } + + satIOContext->currentLBA = lba; + satIOContext->OrgTL = tl; + + /* + computing number of loop and remainder for tl + 0xFF in case not ext + 0xFFFF in case EXT + */ + if (fis->h.command == SAT_READ_VERIFY_SECTORS) + { + LoopNum = satComputeLoopNum(tl, 0xFF); + } + else if (fis->h.command == SAT_READ_VERIFY_SECTORS_EXT) + { + /* SAT_READ_SECTORS_EXT, SAT_READ_DMA_EXT */ + LoopNum = satComputeLoopNum(tl, 0xFFFF); + } + else + { + TI_DBG1(("satVerify10: error case 1!!!\n")); + LoopNum = 1; + } + + satIOContext->LoopNum = LoopNum; + + if (LoopNum == 1) + { + TI_DBG5(("satVerify10: NON CHAINED data\n")); + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satNonChainedVerifyCB; + } + else + { + TI_DBG1(("satVerify10: CHAINED data\n")); + /* re-setting tl */ + if (fis->h.command == SAT_READ_VERIFY_SECTORS) + { + fis->d.sectorCount = 0xFF; + } + else if (fis->h.command == SAT_READ_VERIFY_SECTORS_EXT) + { + fis->d.sectorCount = 0xFF; + fis->d.sectorCountExp = 0xFF; + } + else + { + TI_DBG1(("satVerify10: error case 2!!!\n")); + } + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satChainedVerifyCB; + } + + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + return (status); +} + +GLOBAL bit32 satChainedVerify( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + bit32 status; + satIOContext_t *satOrgIOContext = agNULL; + agsaFisRegHostToDevice_t *fis; + bit32 agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + bit32 lba = 0; + bit32 DenomTL = 0xFF; + bit32 Remainder = 0; + bit8 LBA[4]; /* 0 MSB, 3 LSB */ + + TI_DBG2(("satChainedVerify: start\n")); + + fis = satIOContext->pFis; + satOrgIOContext = satIOContext->satOrgIOContext; + osti_memset(LBA,0, sizeof(LBA)); + + switch (satOrgIOContext->ATACmd) + { + case SAT_READ_VERIFY_SECTORS: + DenomTL = 0xFF; + break; + case SAT_READ_VERIFY_SECTORS_EXT: + DenomTL = 0xFFFF; + break; + default: + TI_DBG1(("satChainedVerify: error incorrect ata command 0x%x\n", satIOContext->ATACmd)); + return tiError; + break; + } + + Remainder = satOrgIOContext->OrgTL % DenomTL; + satOrgIOContext->currentLBA = satOrgIOContext->currentLBA + DenomTL; + lba = satOrgIOContext->currentLBA; + + LBA[0] = (bit8)((lba & 0xF000) >> (8 * 3)); /* MSB */ + LBA[1] = (bit8)((lba & 0xF00) >> (8 * 2)); + LBA[2] = (bit8)((lba & 0xF0) >> 8); + LBA[3] = (bit8)(lba & 0xF); /* LSB */ + + switch (satOrgIOContext->ATACmd) + { + case SAT_READ_VERIFY_SECTORS: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS; /* 0x40 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (LBA[0] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->d.sectorCount = (bit8)Remainder; /* FIS sector count (7:0) */ + } + else + { + fis->d.sectorCount = 0xFF; /* FIS sector count (7:0) */ + } + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + break; + case SAT_READ_VERIFY_SECTORS_EXT: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS_EXT; /* 0x42 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = LBA[0]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->d.sectorCount = (bit8)(Remainder & 0xFF); /* FIS sector count (7:0) */ + fis->d.sectorCountExp = (bit8)((Remainder & 0xFF00) >> 8); /* FIS sector count (15:8) */ + } + else + { + fis->d.sectorCount = 0xFF; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0xFF; /* FIS sector count (15:8) */ + } + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + break; + + default: + TI_DBG1(("satChainedVerify: error incorrect ata command 0x%x\n", satIOContext->ATACmd)); + return tiError; + break; + } + + /* Initialize CB for SATA completion. + */ + /* chained data */ + satIOContext->satCompleteCB = &satChainedVerifyCB; + + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + TI_DBG5(("satChainedVerify: return\n")); + return (status); + +} + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI VERIFY (12). + * + * SAT implementation for SCSI VERIFY (12). + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satVerify12( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + /* + For simple implementation, + no byte comparison supported as of 4/5/06 + */ + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + satDeviceData_t *pSatDevData; + agsaFisRegHostToDevice_t *fis; + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + bit32 lba = 0; + bit32 tl = 0; + bit32 LoopNum = 1; + bit8 LBA[4]; + bit8 TL[4]; + bit32 rangeChk = agFALSE; /* lba and tl range check */ + + TI_DBG5(("satVerify12 entry: tiDeviceHandle=%p tiIORequest=%p\n", + tiDeviceHandle, tiIORequest)); + + pSense = satIOContext->pSense; + scsiCmnd = &tiScsiRequest->scsiCmnd; + pSatDevData = satIOContext->pSatDevData; + fis = satIOContext->pFis; + + + /* checking BYTCHK */ + if (scsiCmnd->cdb[1] & SCSI_VERIFY_BYTCHK_MASK) + { + /* + should do the byte check + but not supported in this version + */ + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satVerify12: no byte checking \n")); + return tiSuccess; + } + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[11] & SCSI_NACA_MASK) || (scsiCmnd->cdb[11] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satVerify12: return control\n")); + return tiSuccess; + } + + osti_memset(LBA, 0, sizeof(LBA)); + osti_memset(TL, 0, sizeof(TL)); + + /* do not use memcpy due to indexing in LBA and TL */ + LBA[0] = scsiCmnd->cdb[2]; /* MSB */ + LBA[1] = scsiCmnd->cdb[3]; + LBA[2] = scsiCmnd->cdb[4]; + LBA[3] = scsiCmnd->cdb[5]; /* LSB */ + + TL[0] = scsiCmnd->cdb[6]; /* MSB */ + TL[1] = scsiCmnd->cdb[7]; + TL[2] = scsiCmnd->cdb[7]; + TL[3] = scsiCmnd->cdb[8]; /* LSB */ + + rangeChk = satAddNComparebit32(LBA, TL); + + lba = satComputeCDB12LBA(satIOContext); + tl = satComputeCDB12TL(satIOContext); + + if (pSatDevData->satNCQ != agTRUE && + pSatDevData->sat48BitSupport != agTRUE + ) + { + if (lba > SAT_TR_LBA_LIMIT - 1) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satVerify12: return LBA out of range, not EXT\n")); + TI_DBG1(("satVerify12: cdb 0x%x 0x%x 0x%x 0x%x\n",scsiCmnd->cdb[2], scsiCmnd->cdb[3], + scsiCmnd->cdb[4], scsiCmnd->cdb[5])); + TI_DBG1(("satVerify12: lba 0x%x SAT_TR_LBA_LIMIT 0x%x\n", lba, SAT_TR_LBA_LIMIT)); + return tiSuccess; + } + + if (rangeChk) // if (lba + tl > SAT_TR_LBA_LIMIT) + { + TI_DBG1(("satVerify12: return LBA+TL out of range, not EXT\n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + return tiSuccess; + } + } + + if (pSatDevData->sat48BitSupport == agTRUE) + { + TI_DBG5(("satVerify12: SAT_READ_VERIFY_SECTORS_EXT\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_READ_VERIFY_SECTORS_EXT;/* 0x42 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set 01000000 */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[9]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[8]; /* FIS sector count (15:8) */ + + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + satIOContext->ATACmd = SAT_READ_VERIFY_SECTORS_EXT; + } + else + { + TI_DBG5(("satVerify12: SAT_READ_VERIFY_SECTORS\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS; /* 0x40 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (scsiCmnd->cdb[2] & 0xF)); + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[9]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + satIOContext->ATACmd = SAT_READ_VERIFY_SECTORS; + + } + + satIOContext->currentLBA = lba; + satIOContext->OrgTL = tl; + + /* + computing number of loop and remainder for tl + 0xFF in case not ext + 0xFFFF in case EXT + */ + if (fis->h.command == SAT_READ_VERIFY_SECTORS) + { + LoopNum = satComputeLoopNum(tl, 0xFF); + } + else if (fis->h.command == SAT_READ_VERIFY_SECTORS_EXT) + { + /* SAT_READ_SECTORS_EXT, SAT_READ_DMA_EXT */ + LoopNum = satComputeLoopNum(tl, 0xFFFF); + } + else + { + TI_DBG1(("satVerify12: error case 1!!!\n")); + LoopNum = 1; + } + + satIOContext->LoopNum = LoopNum; + + if (LoopNum == 1) + { + TI_DBG5(("satVerify12: NON CHAINED data\n")); + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satNonChainedVerifyCB; + } + else + { + TI_DBG1(("satVerify12: CHAINED data\n")); + /* re-setting tl */ + if (fis->h.command == SAT_READ_VERIFY_SECTORS) + { + fis->d.sectorCount = 0xFF; + } + else if (fis->h.command == SAT_READ_VERIFY_SECTORS_EXT) + { + fis->d.sectorCount = 0xFF; + fis->d.sectorCountExp = 0xFF; + } + else + { + TI_DBG1(("satVerify10: error case 2!!!\n")); + } + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satChainedVerifyCB; + } + + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + return (status); +} +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI VERIFY (16). + * + * SAT implementation for SCSI VERIFY (16). + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satVerify16( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + /* + For simple implementation, + no byte comparison supported as of 4/5/06 + */ + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + satDeviceData_t *pSatDevData; + agsaFisRegHostToDevice_t *fis; + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + bit32 lba = 0; + bit32 tl = 0; + bit32 LoopNum = 1; + bit8 LBA[8]; + bit8 TL[8]; + bit32 rangeChk = agFALSE; /* lba and tl range check */ + bit32 limitChk = agFALSE; /* lba and tl range check */ + + TI_DBG5(("satVerify16 entry: tiDeviceHandle=%p tiIORequest=%p\n", + tiDeviceHandle, tiIORequest)); + + pSense = satIOContext->pSense; + scsiCmnd = &tiScsiRequest->scsiCmnd; + pSatDevData = satIOContext->pSatDevData; + fis = satIOContext->pFis; + + /* checking BYTCHK */ + if (scsiCmnd->cdb[1] & SCSI_VERIFY_BYTCHK_MASK) + { + /* + should do the byte check + but not supported in this version + */ + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satVerify16: no byte checking \n")); + return tiSuccess; + } + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[15] & SCSI_NACA_MASK) || (scsiCmnd->cdb[15] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG2(("satVerify16: return control\n")); + return tiSuccess; + } + + osti_memset(LBA, 0, sizeof(LBA)); + osti_memset(TL, 0, sizeof(TL)); + + + /* do not use memcpy due to indexing in LBA and TL */ + LBA[0] = scsiCmnd->cdb[2]; /* MSB */ + LBA[1] = scsiCmnd->cdb[3]; + LBA[2] = scsiCmnd->cdb[4]; + LBA[3] = scsiCmnd->cdb[5]; + LBA[4] = scsiCmnd->cdb[6]; + LBA[5] = scsiCmnd->cdb[7]; + LBA[6] = scsiCmnd->cdb[8]; + LBA[7] = scsiCmnd->cdb[9]; /* LSB */ + + TL[0] = 0; + TL[1] = 0; + TL[2] = 0; + TL[3] = 0; + TL[4] = scsiCmnd->cdb[10]; /* MSB */ + TL[5] = scsiCmnd->cdb[11]; + TL[6] = scsiCmnd->cdb[12]; + TL[7] = scsiCmnd->cdb[13]; /* LSB */ + + rangeChk = satAddNComparebit64(LBA, TL); + + limitChk = satCompareLBALimitbit(LBA); + + lba = satComputeCDB16LBA(satIOContext); + tl = satComputeCDB16TL(satIOContext); + + if (pSatDevData->satNCQ != agTRUE && + pSatDevData->sat48BitSupport != agTRUE + ) + { + if (limitChk) + { + TI_DBG1(("satVerify16: return LBA out of range, not EXT\n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + return tiSuccess; + } + if (rangeChk) // if (lba + tl > SAT_TR_LBA_LIMIT) + { + TI_DBG1(("satVerify16: return LBA+TL out of range, not EXT\n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + return tiSuccess; + } + } + + if (pSatDevData->sat48BitSupport == agTRUE) + { + TI_DBG5(("satVerify16: SAT_READ_VERIFY_SECTORS_EXT\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_READ_VERIFY_SECTORS_EXT;/* 0x42 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[9]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[8]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[7]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set 01000000 */ + fis->d.lbaLowExp = scsiCmnd->cdb[6]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = scsiCmnd->cdb[5]; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = scsiCmnd->cdb[4]; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[13]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[12]; /* FIS sector count (15:8) */ + + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + satIOContext->ATACmd = SAT_READ_VERIFY_SECTORS_EXT; + } + else + { + TI_DBG5(("satVerify12: SAT_READ_VERIFY_SECTORS\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS; /* 0x40 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[9]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[8]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[7]; /* FIS LBA (23:16) */ + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (scsiCmnd->cdb[6] & 0xF)); + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[13]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + satIOContext->ATACmd = SAT_READ_VERIFY_SECTORS; + + } + + satIOContext->currentLBA = lba; + satIOContext->OrgTL = tl; + + /* + computing number of loop and remainder for tl + 0xFF in case not ext + 0xFFFF in case EXT + */ + if (fis->h.command == SAT_READ_VERIFY_SECTORS) + { + LoopNum = satComputeLoopNum(tl, 0xFF); + } + else if (fis->h.command == SAT_READ_VERIFY_SECTORS_EXT) + { + /* SAT_READ_SECTORS_EXT, SAT_READ_DMA_EXT */ + LoopNum = satComputeLoopNum(tl, 0xFFFF); + } + else + { + TI_DBG1(("satVerify12: error case 1!!!\n")); + LoopNum = 1; + } + + satIOContext->LoopNum = LoopNum; + + if (LoopNum == 1) + { + TI_DBG5(("satVerify12: NON CHAINED data\n")); + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satNonChainedVerifyCB; + } + else + { + TI_DBG1(("satVerify12: CHAINED data\n")); + /* re-setting tl */ + if (fis->h.command == SAT_READ_VERIFY_SECTORS) + { + fis->d.sectorCount = 0xFF; + } + else if (fis->h.command == SAT_READ_VERIFY_SECTORS_EXT) + { + fis->d.sectorCount = 0xFF; + fis->d.sectorCountExp = 0xFF; + } + else + { + TI_DBG1(("satVerify10: error case 2!!!\n")); + } + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satChainedVerifyCB; + } + + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + return (status); +} +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satFormatUnit. + * + * SAT implementation for SCSI satFormatUnit. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satFormatUnit( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + /* + note: we don't support media certification in this version and IP bit + satDevData->satFormatState will be agFalse since SAT does not actually sends + any ATA command + */ + + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + bit32 index = 0; + + pSense = satIOContext->pSense; + scsiCmnd = &tiScsiRequest->scsiCmnd; + + TI_DBG5(("satFormatUnit:start\n")); + + /* + checking opcode + 1. FMTDATA bit == 0(no defect list header) + 2. FMTDATA bit == 1 and DCRT bit == 1(defect list header is provided + with DCRT bit set) + */ + if ( ((scsiCmnd->cdb[1] & SCSI_FORMAT_UNIT_FMTDATA_MASK) == 0) || + ((scsiCmnd->cdb[1] & SCSI_FORMAT_UNIT_FMTDATA_MASK) && + (scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_DCRT_MASK)) + ) + { + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + + TI_DBG2(("satFormatUnit: return opcode\n")); + return tiSuccess; + } + + /* + checking DEFECT LIST FORMAT and defect list length + */ + if ( (((scsiCmnd->cdb[1] & SCSI_FORMAT_UNIT_DEFECT_LIST_FORMAT_MASK) == 0x00) || + ((scsiCmnd->cdb[1] & SCSI_FORMAT_UNIT_DEFECT_LIST_FORMAT_MASK) == 0x06)) ) + { + /* short parameter header */ + if ((scsiCmnd->cdb[2] & SCSI_FORMAT_UNIT_LONGLIST_MASK) == 0x00) + { + index = 8; + } + /* long parameter header */ + if ((scsiCmnd->cdb[2] & SCSI_FORMAT_UNIT_LONGLIST_MASK) == 0x01) + { + index = 10; + } + /* defect list length */ + if ((scsiCmnd->cdb[index] != 0) || (scsiCmnd->cdb[index+1] != 0)) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satFormatUnit: return defect list format\n")); + return tiSuccess; + } + } + + /* FMTDATA == 1 && CMPLIST == 1*/ + if ( (scsiCmnd->cdb[1] & SCSI_FORMAT_UNIT_FMTDATA_MASK) && + (scsiCmnd->cdb[1] & SCSI_FORMAT_UNIT_CMPLIST_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satFormatUnit: return cmplist\n")); + return tiSuccess; + + } + + if ( (scsiCmnd->cdb[5] & SCSI_NACA_MASK) || (scsiCmnd->cdb[5] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satFormatUnit: return control\n")); + return tiSuccess; + } + + /* defect list header filed, if exists, SAT rev8, Table 37, p48 */ + if (scsiCmnd->cdb[1] & SCSI_FORMAT_UNIT_FMTDATA_MASK) + { + /* case 1,2,3 */ + /* IMMED 1; FOV 0; FOV 1, DCRT 1, IP 0 */ + if ( (scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_IMMED_MASK) || + ( !(scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_FOV_MASK)) || + ( (scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_FOV_MASK) && + (scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_DCRT_MASK) && + !(scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_IP_MASK)) + ) + { + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + + TI_DBG5(("satFormatUnit: return defect list case 1\n")); + return tiSuccess; + } + /* case 4,5,6 */ + /* + 1. IMMED 0, FOV 1, DCRT 0, IP 0 + 2. IMMED 0, FOV 1, DCRT 0, IP 1 + 3. IMMED 0, FOV 1, DCRT 1, IP 1 + */ + + if ( ( !(scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_IMMED_MASK) && + (scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_FOV_MASK) && + !(scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_DCRT_MASK) && + !(scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_IP_MASK) ) + || + ( !(scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_IMMED_MASK) && + (scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_FOV_MASK) && + !(scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_DCRT_MASK) && + (scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_IP_MASK) ) + || + ( !(scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_IMMED_MASK) && + (scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_FOV_MASK) && + (scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_DCRT_MASK) && + (scsiCmnd->cdb[7] & SCSI_FORMAT_UNIT_IP_MASK) ) + ) + { + + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_PARAMETER_LIST, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG5(("satFormatUnit: return defect list case 2\n")); + return tiSuccess; + + } + } + + + /* + * Send the completion response now. + */ + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + + TI_DBG5(("satFormatUnit: return last\n")); + return tiSuccess; +} + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satSendDiagnostic. + * + * SAT implementation for SCSI satSendDiagnostic. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satSendDiagnostic( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + bit32 status; + bit32 agRequestType; + satDeviceData_t *pSatDevData; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 parmLen; + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &tiScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + TI_DBG5(("satSendDiagnostic:start\n")); + + /* reset satVerifyState */ + pSatDevData->satVerifyState = 0; + /* no pending diagnostic in background */ + pSatDevData->satBGPendingDiag = agFALSE; + + /* table 27, 8.10 p39 SAT Rev8 */ + /* + 1. checking PF == 1 + 2. checking DEVOFFL == 1 + 3. checking UNITOFFL == 1 + 4. checking PARAMETER LIST LENGTH != 0 + + */ + if ( (scsiCmnd->cdb[1] & SCSI_PF_MASK) || + (scsiCmnd->cdb[1] & SCSI_DEVOFFL_MASK) || + (scsiCmnd->cdb[1] & SCSI_UNITOFFL_MASK) || + ( (scsiCmnd->cdb[3] != 0) || (scsiCmnd->cdb[4] != 0) ) + ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satSendDiagnostic: return PF, DEVOFFL, UNITOFFL, PARAM LIST\n")); + return tiSuccess; + } + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[5] & SCSI_NACA_MASK) || (scsiCmnd->cdb[5] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG2(("satSendDiagnostic: return control\n")); + return tiSuccess; + } + + parmLen = (scsiCmnd->cdb[3] << 8) + scsiCmnd->cdb[4]; + + /* checking SELFTEST bit*/ + /* table 29, 8.10.3, p41 SAT Rev8 */ + /* case 1 */ + if ( !(scsiCmnd->cdb[1] & SCSI_SEND_DIAGNOSTIC_SELFTEST_MASK) && + (pSatDevData->satSMARTSelfTest == agFALSE) + ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satSendDiagnostic: return Table 29 case 1\n")); + return tiSuccess; + } + + /* case 2 */ + if ( !(scsiCmnd->cdb[1] & SCSI_SEND_DIAGNOSTIC_SELFTEST_MASK) && + (pSatDevData->satSMARTSelfTest == agTRUE) && + (pSatDevData->satSMARTEnabled == agFALSE) + ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_ATA_DEVICE_FEATURE_NOT_ENABLED, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG5(("satSendDiagnostic: return Table 29 case 2\n")); + return tiSuccess; + } + /* + case 3 + see SELF TEST CODE later + */ + + + + /* case 4 */ + + /* + sends three ATA verify commands + + */ + if ( ((scsiCmnd->cdb[1] & SCSI_SEND_DIAGNOSTIC_SELFTEST_MASK) && + (pSatDevData->satSMARTSelfTest == agFALSE)) + || + ((scsiCmnd->cdb[1] & SCSI_SEND_DIAGNOSTIC_SELFTEST_MASK) && + (pSatDevData->satSMARTSelfTest == agTRUE) && + (pSatDevData->satSMARTEnabled == agFALSE)) + ) + { + /* + sector count 1, LBA 0 + sector count 1, LBA MAX + sector count 1, LBA random + */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + /* sends READ VERIFY SECTOR(S) EXT*/ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS_EXT;/* 0x42 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.device = 0x40; /* 01000000 */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + } + else + { + /* READ VERIFY SECTOR(S)*/ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS;/* 0x40 */ + fis->h.features = 0; /* FIS features NA */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.device = 0x40; /* 01000000 */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + } + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satSendDiagnosticCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + + TI_DBG5(("satSendDiagnostic: return Table 29 case 4\n")); + return (status); + } + /* case 5 */ + if ( (scsiCmnd->cdb[1] & SCSI_SEND_DIAGNOSTIC_SELFTEST_MASK) && + (pSatDevData->satSMARTSelfTest == agTRUE) && + (pSatDevData->satSMARTEnabled == agTRUE) + ) + { + /* sends SMART EXECUTE OFF-LINE IMMEDIATE */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_SMART_EXEUTE_OFF_LINE_IMMEDIATE;/* 0xB0 */ + fis->h.features = 0xD4; /* FIS features NA */ + fis->d.lbaLow = 0x81; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0x4F; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0xC2; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.device = 0; /* FIS DEV is discared in SATA */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satSendDiagnosticCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + + TI_DBG5(("satSendDiagnostic: return Table 29 case 5\n")); + return (status); + } + + + + + /* SAT rev8 Table29 p41 case 3*/ + /* checking SELF TEST CODE*/ + if ( !(scsiCmnd->cdb[1] & SCSI_SEND_DIAGNOSTIC_SELFTEST_MASK) && + (pSatDevData->satSMARTSelfTest == agTRUE) && + (pSatDevData->satSMARTEnabled == agTRUE) + ) + { + /* SAT rev8 Table28 p40 */ + /* finding self-test code */ + switch ((scsiCmnd->cdb[1] & SCSI_SEND_DIAGNOSTIC_TEST_CODE_MASK) >> 5) + { + case 1: + pSatDevData->satBGPendingDiag = agTRUE; + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext ); + /* sends SMART EXECUTE OFF-LINE IMMEDIATE */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_SMART_EXEUTE_OFF_LINE_IMMEDIATE;/* 0x40 */ + fis->h.features = 0xD4; /* FIS features NA */ + fis->d.lbaLow = 0x01; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0x4F; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0xC2; /* FIS LBA (23:16) */ + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.device = 0; /* FIS DEV is discared in SATA */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satSendDiagnosticCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + + TI_DBG5(("satSendDiagnostic: return Table 28 case 1\n")); + return (status); + case 2: + pSatDevData->satBGPendingDiag = agTRUE; + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext ); + + + /* issuing SMART EXECUTE OFF-LINE IMMEDIATE */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_SMART_EXEUTE_OFF_LINE_IMMEDIATE;/* 0x40 */ + fis->h.features = 0xD4; /* FIS features NA */ + fis->d.lbaLow = 0x02; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0x4F; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0xC2; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.device = 0; /* FIS DEV is discared in SATA */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satSendDiagnosticCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + + TI_DBG5(("satSendDiagnostic: return Table 28 case 2\n")); + return (status); + case 4: + /* For simplicity, no abort is supported + Returns good status + need a flag in device data for previously sent background Send Diagnostic + */ + if (parmLen != 0) + { + /* check condition */ + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satSendDiagnostic: case 4, non zero ParmLen %d\n", parmLen)); + return tiSuccess; + } + if (pSatDevData->satBGPendingDiag == agTRUE) + { + /* sends SMART EXECUTE OFF-LINE IMMEDIATE abort */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_SMART_EXEUTE_OFF_LINE_IMMEDIATE;/* 0x40 */ + fis->h.features = 0xD4; /* FIS features NA */ + fis->d.lbaLow = 0x7F; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0x4F; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0xC2; /* FIS LBA (23:16) */ + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.device = 0; /* FIS DEV is discared in SATA */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satSendDiagnosticCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + + TI_DBG5(("satSendDiagnostic: send SAT_SMART_EXEUTE_OFF_LINE_IMMEDIATE case 3\n")); + TI_DBG5(("satSendDiagnostic: Table 28 case 4\n")); + return (status); + } + else + { + /* check condition */ + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satSendDiagnostic: case 4, no pending diagnostic in background\n")); + TI_DBG5(("satSendDiagnostic: Table 28 case 4\n")); + return tiSuccess; + } + break; + case 5: + /* issuing SMART EXECUTE OFF-LINE IMMEDIATE */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_SMART_EXEUTE_OFF_LINE_IMMEDIATE;/* 0x40 */ + fis->h.features = 0xD4; /* FIS features NA */ + fis->d.lbaLow = 0x81; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0x4F; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0xC2; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.device = 0; /* FIS DEV is discared in SATA */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satSendDiagnosticCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + + TI_DBG5(("satSendDiagnostic: return Table 28 case 5\n")); + return (status); + case 6: + /* issuing SMART EXECUTE OFF-LINE IMMEDIATE */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_SMART_EXEUTE_OFF_LINE_IMMEDIATE;/* 0x40 */ + fis->h.features = 0xD4; /* FIS features NA */ + fis->d.lbaLow = 0x82; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0x4F; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0xC2; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.device = 0; /* FIS DEV is discared in SATA */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satSendDiagnosticCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + + TI_DBG5(("satSendDiagnostic: return Table 28 case 6\n")); + return (status); + case 0: + case 3: /* fall through */ + case 7: /* fall through */ + default: + break; + }/* switch */ + + /* returns the results of default self-testing, which is good */ + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext ); + + TI_DBG5(("satSendDiagnostic: return Table 28 case 0,3,7 and default\n")); + return tiSuccess; + } + + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext ); + + + TI_DBG5(("satSendDiagnostic: return last\n")); + return tiSuccess; +} + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satSendDiagnostic_1. + * + * SAT implementation for SCSI satSendDiagnostic_1. + * Sub function of satSendDiagnostic. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satSendDiagnostic_1( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + /* + SAT Rev9, Table29, p41 + send 2nd SAT_READ_VERIFY_SECTORS(_EXT) + */ + bit32 status; + bit32 agRequestType; + satDeviceData_t *pSatDevData; + agsaFisRegHostToDevice_t *fis; + + TI_DBG5(("satSendDiagnostic_1 entry: tiDeviceHandle=%p tiIORequest=%p\n", + tiDeviceHandle, tiIORequest)); + + pSatDevData = satIOContext->pSatDevData; + fis = satIOContext->pFis; + + /* + sector count 1, LBA MAX + */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + /* sends READ VERIFY SECTOR(S) EXT*/ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS_EXT;/* 0x42 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = pSatDevData->satMaxLBA[7]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = pSatDevData->satMaxLBA[6]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = pSatDevData->satMaxLBA[5]; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = pSatDevData->satMaxLBA[4]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = pSatDevData->satMaxLBA[3]; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = pSatDevData->satMaxLBA[2]; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.device = 0x40; /* 01000000 */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + } + else + { + /* READ VERIFY SECTOR(S)*/ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS;/* 0x40 */ + fis->h.features = 0; /* FIS features NA */ + fis->d.lbaLow = pSatDevData->satMaxLBA[7]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = pSatDevData->satMaxLBA[6]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = pSatDevData->satMaxLBA[5]; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.device = (bit8)((0x4 << 4) | (pSatDevData->satMaxLBA[4] & 0xF)); + /* DEV and LBA 27:24 */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + } + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satSendDiagnosticCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + + return status; +} + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satSendDiagnostic_2. + * + * SAT implementation for SCSI satSendDiagnostic_2. + * Sub function of satSendDiagnostic. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satSendDiagnostic_2( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + /* + SAT Rev9, Table29, p41 + send 3rd SAT_READ_VERIFY_SECTORS(_EXT) + */ + bit32 status; + bit32 agRequestType; + satDeviceData_t *pSatDevData; + agsaFisRegHostToDevice_t *fis; + + TI_DBG5(("satSendDiagnostic_2 entry: tiDeviceHandle=%p tiIORequest=%p\n", + tiDeviceHandle, tiIORequest)); + + pSatDevData = satIOContext->pSatDevData; + fis = satIOContext->pFis; + + /* + sector count 1, LBA Random + */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + /* sends READ VERIFY SECTOR(S) EXT*/ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS_EXT;/* 0x42 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = 0x7F; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.device = 0x40; /* 01000000 */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + } + else + { + /* READ VERIFY SECTOR(S)*/ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS;/* 0x40 */ + fis->h.features = 0; /* FIS features NA */ + fis->d.lbaLow = 0x7F; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.device = 0x40; /* FIS LBA mode set 01000000 */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + } + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satSendDiagnosticCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + + return status; +} +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satStartStopUnit. + * + * SAT implementation for SCSI satStartStopUnit. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satStartStopUnit( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + bit32 status; + bit32 agRequestType; + satDeviceData_t *pSatDevData; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &tiScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + TI_DBG5(("satStartStopUnit:start\n")); + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[5] & SCSI_NACA_MASK) || (scsiCmnd->cdb[5] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satStartStopUnit: return control\n")); + return tiSuccess; + } + + /* Spec p55, Table 48 checking START and LOEJ bit */ + /* case 1 */ + if ( !(scsiCmnd->cdb[4] & SCSI_START_MASK) && !(scsiCmnd->cdb[4] & SCSI_LOEJ_MASK) ) + { + if ( (scsiCmnd->cdb[1] & SCSI_IMMED_MASK) ) + { + /* immed bit , SAT rev 8, 9.11.2.1 p 54*/ + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext ); + TI_DBG5(("satStartStopUnit: return table48 case 1-1\n")); + return tiSuccess; + } + /* sends FLUSH CACHE or FLUSH CACHE EXT */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + /* FLUSH CACHE EXT */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_FLUSH_CACHE_EXT; /* 0xEA */ + fis->h.features = 0; /* FIS reserve */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaLowExp = 0; /* FIS LBA (31:24) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.device = 0; /* FIS DEV is discared in SATA */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved4 = 0; + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + } + else + { + /* FLUSH CACHE */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_FLUSH_CACHE; /* 0xE7 */ + fis->h.features = 0; /* FIS features NA */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.device = 0; /* FIS DEV is discared in SATA */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved4 = 0; + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + } + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satStartStopUnitCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + + TI_DBG5(("satStartStopUnit: return table48 case 1\n")); + return (status); + } + /* case 2 */ + else if ( (scsiCmnd->cdb[4] & SCSI_START_MASK) && !(scsiCmnd->cdb[4] & SCSI_LOEJ_MASK) ) + { + /* immed bit , SAT rev 8, 9.11.2.1 p 54*/ + if ( (scsiCmnd->cdb[1] & SCSI_IMMED_MASK) ) + { + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext ); + + TI_DBG5(("satStartStopUnit: return table48 case 2 1\n")); + return tiSuccess; + } + /* + sends READ_VERIFY_SECTORS(_EXT) + sector count 1, any LBA between zero to Maximum + */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + /* READ VERIFY SECTOR(S) EXT*/ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_READ_VERIFY_SECTORS_EXT;/* 0x42 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = 0x01; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0x00; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0x00; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0x00; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0x00; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0x00; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.device = 0x40; /* 01000000 */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + } + else + { + /* READ VERIFY SECTOR(S)*/ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_READ_VERIFY_SECTORS;/* 0x40 */ + fis->h.features = 0; /* FIS features NA */ + fis->d.lbaLow = 0x01; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0x00; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0x00; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.device = 0x40; /* 01000000 */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + } + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satStartStopUnitCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + TI_DBG5(("satStartStopUnit: return table48 case 2 2\n")); + return status; + } + /* case 3 */ + else if ( !(scsiCmnd->cdb[4] & SCSI_START_MASK) && (scsiCmnd->cdb[4] & SCSI_LOEJ_MASK) ) + { + if(pSatDevData->satRemovableMedia && pSatDevData->satRemovableMediaEnabled) + { + /* support for removal media */ + /* immed bit , SAT rev 8, 9.11.2.1 p 54*/ + if ( (scsiCmnd->cdb[1] & SCSI_IMMED_MASK) ) + { + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext ); + + TI_DBG5(("satStartStopUnit: return table48 case 3 1\n")); + return tiSuccess; + } + /* + sends MEDIA EJECT + */ + /* Media Eject fis */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_MEDIA_EJECT; /* 0xED */ + fis->h.features = 0; /* FIS features NA */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + /* sector count zero */ + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.device = 0; /* FIS DEV is discared in SATA */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved4 = 0; + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satStartStopUnitCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + return status; + } + else + { + /* no support for removal media */ + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG5(("satStartStopUnit: return Table 29 case 3 2\n")); + return tiSuccess; + } + + } + /* case 4 */ + else /* ( (scsiCmnd->cdb[4] & SCSI_START_MASK) && (scsiCmnd->cdb[4] & SCSI_LOEJ_MASK) ) */ + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG5(("satStartStopUnit: return Table 29 case 4\n")); + return tiSuccess; + } + + +} + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satStartStopUnit_1. + * + * SAT implementation for SCSI satStartStopUnit_1. + * Sub function of satStartStopUnit + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satStartStopUnit_1( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + /* + SAT Rev 8, Table 48, 9.11.3 p55 + sends STANDBY + */ + bit32 status; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; + + TI_DBG5(("satStartStopUnit_1 entry: tiDeviceHandle=%p tiIORequest=%p\n", + tiDeviceHandle, tiIORequest)); + + fis = satIOContext->pFis; + + /* STANDBY */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_STANDBY; /* 0xE2 */ + fis->h.features = 0; /* FIS features NA */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.device = 0; /* 0 */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satStartStopUnitCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + TI_DBG5(("satStartStopUnit_1 return status %d\n", status)); + return status; +} + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satRead10_2. + * + * SAT implementation for SCSI satRead10_2 + * Sub function of satRead10 + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satRead10_2( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + /* + externally generated ATA cmd, there is corresponding scsi cmnd + called by satStartStopUnit() or maybe satRead10() + */ + + bit32 status; + bit32 agRequestType; + satDeviceData_t *pSatDevData; + agsaFisRegHostToDevice_t *fis; + + pSatDevData = satIOContext->pSatDevData; + fis = satIOContext->pFis; + + TI_DBG5(("satReadVerifySectorsNoChain: start\n")); + + /* specifying ReadVerifySectors has no chain */ + pSatDevData->satVerifyState = 0xFFFFFFFF; + + if (pSatDevData->sat48BitSupport == agTRUE) + { + /* READ VERIFY SECTOR(S) EXT*/ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS_EXT;/* 0x42 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = 0x7F; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0x4F; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0x00; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0xF1; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0x5F; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0xFF; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.device = 0x4E; /* 01001110 */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + } + else + { + /* READ VERIFY SECTOR(S)*/ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS;/* 0x40 */ + fis->h.features = 0; /* FIS features NA */ + fis->d.lbaLow = 0x7F; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0x4F; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0x00; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.device = 0x4E; /* 01001110 */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + } + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satNonDataIOCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + TI_DBG5(("satReadVerifySectorsNoChain: return last\n")); + + return status; +} + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satWriteSame10. + * + * SAT implementation for SCSI satWriteSame10. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satWriteSame10( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satDeviceData_t *pSatDevData; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 lba = 0; + bit32 tl = 0; + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &tiScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + TI_DBG5(("satWriteSame10: start\n")); + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[9] & SCSI_NACA_MASK) || (scsiCmnd->cdb[9] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satWriteSame10: return control\n")); + return tiSuccess; + } + + + /* checking LBDATA and PBDATA */ + /* case 1 */ + if ( !(scsiCmnd->cdb[1] & SCSI_WRITE_SAME_LBDATA_MASK) && + !(scsiCmnd->cdb[1] & SCSI_WRITE_SAME_PBDATA_MASK)) + { + TI_DBG5(("satWriteSame10: case 1\n")); + /* spec 9.26.2, Table 62, p64, case 1*/ + /* + normal case + just like write in 9.17.1 + */ + + if ( pSatDevData->sat48BitSupport != agTRUE ) + { + /* + writeSame10 but no support for 48 bit addressing + -> problem in transfer length. Therefore, return check condition + */ + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satWriteSame10: return internal checking\n")); + return tiSuccess; + } + + /* cdb10; computing LBA and transfer length */ + lba = (scsiCmnd->cdb[2] << (8*3)) + (scsiCmnd->cdb[3] << (8*2)) + + (scsiCmnd->cdb[4] << 8) + scsiCmnd->cdb[5]; + tl = (scsiCmnd->cdb[7] << 8) + scsiCmnd->cdb[8]; + + + /* Table 34, 9.1, p 46 */ + /* + note: As of 2/10/2006, no support for DMA QUEUED + */ + + /* + Table 34, 9.1, p 46, b (footnote) + When no 48-bit addressing support or NCQ, if LBA is beyond (2^28 - 1), + return check condition + */ + if (pSatDevData->satNCQ != agTRUE && + pSatDevData->sat48BitSupport != agTRUE + ) + { + if (lba > SAT_TR_LBA_LIMIT - 1) /* SAT_TR_LBA_LIMIT is 2^28, 0x10000000 */ + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satWriteSame10: return LBA out of range\n")); + return tiSuccess; + } + } + + if (lba + tl <= SAT_TR_LBA_LIMIT) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 2 */ + /* WRITE DMA */ + /* can't fit the transfer length since WRITE DMA has 1 byte for sector count */ + TI_DBG5(("satWriteSame10: case 1-2 !!! error due to writeSame10\n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + else + { + /* case 1 */ + /* WRITE MULTIPLE or WRITE SECTOR(S) */ + /* WRITE SECTORS is chosen for easier implemetation */ + /* can't fit the transfer length since WRITE DMA has 1 byte for sector count */ + TI_DBG5(("satWriteSame10: case 1-1 !!! error due to writesame10\n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + } /* end of case 1 and 2 */ + + /* case 3 and 4 */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 3 */ + /* WRITE DMA EXT or WRITE DMA FUA EXT */ + /* WRITE DMA EXT is chosen since WRITE SAME does not have FUA bit */ + TI_DBG5(("satWriteSame10: case 1-3\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_WRITE_DMA_EXT; /* 0x35 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + if (tl == 0) + { + /* error check + ATA spec, p125, 6.17.29 + pSatDevData->satMaxUserAddrSectors should be 0x0FFFFFFF + and allowed value is 0x0FFFFFFF - 1 + */ + if (pSatDevData->satMaxUserAddrSectors > 0x0FFFFFFF) + { + TI_DBG5(("satWriteSame10: case 3 !!! warning can't fit sectors\n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + } + /* one sector at a time */ + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + } + else + { + /* case 4 */ + /* WRITE MULTIPLE EXT or WRITE MULTIPLE FUA EXT or WRITE SECTOR(S) EXT */ + /* WRITE SECTORS EXT is chosen for easier implemetation */ + TI_DBG5(("satWriteSame10: case 1-4\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_WRITE_SECTORS_EXT; /* 0x34 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + if (tl == 0) + { + /* error check + ATA spec, p125, 6.17.29 + pSatDevData->satMaxUserAddrSectors should be 0x0FFFFFFF + and allowed value is 0x0FFFFFFF - 1 + */ + if (pSatDevData->satMaxUserAddrSectors > 0x0FFFFFFF) + { + TI_DBG5(("satWriteSame10: case 4 !!! warning can't fit sectors\n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + } + /* one sector at a time */ + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + } + } + + /* case 5 */ + if (pSatDevData->satNCQ == agTRUE) + { + /* WRITE FPDMA QUEUED */ + if (pSatDevData->sat48BitSupport != agTRUE) + { + TI_DBG5(("satWriteSame10: case 1-5 !!! error NCQ but 28 bit address support \n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + TI_DBG5(("satWriteSame10: case 1-5\n")); + + /* Support 48-bit FPDMA addressing, use WRITE FPDMA QUEUE command */ + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_FPDMA_QUEUED; /* 0x61 */ + + if (tl == 0) + { + /* error check + ATA spec, p125, 6.17.29 + pSatDevData->satMaxUserAddrSectors should be 0x0FFFFFFF + and allowed value is 0x0FFFFFFF - 1 + */ + if (pSatDevData->satMaxUserAddrSectors > 0x0FFFFFFF) + { + TI_DBG5(("satWriteSame10: case 4 !!! warning can't fit sectors\n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + } + /* one sector at a time */ + fis->h.features = 1; /* FIS sector count (7:0) */ + fis->d.featuresExp = 0; /* FIS sector count (15:8) */ + + + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + + /* NO FUA bit in the WRITE SAME 10 */ + fis->d.device = 0x40; /* FIS FUA clear */ + + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_WRITE; + } + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satWriteSame10CB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + return (status); + + + } /* end of case 1 */ + else if ( !(scsiCmnd->cdb[1] & SCSI_WRITE_SAME_LBDATA_MASK) && + (scsiCmnd->cdb[1] & SCSI_WRITE_SAME_PBDATA_MASK)) + { + /* spec 9.26.2, Table 62, p64, case 2*/ + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG5(("satWriteSame10: return Table 62 case 2\n")); + return tiSuccess; + } + else if ( (scsiCmnd->cdb[1] & SCSI_WRITE_SAME_LBDATA_MASK) && + !(scsiCmnd->cdb[1] & SCSI_WRITE_SAME_PBDATA_MASK)) + { + TI_DBG5(("satWriteSame10: Table 62 case 3\n")); + + } + else /* ( (scsiCmnd->cdb[1] & SCSI_WRITE_SAME_LBDATA_MASK) && + (scsiCmnd->cdb[1] & SCSI_WRITE_SAME_PBDATA_MASK)) */ + { + + /* spec 9.26.2, Table 62, p64, case 4*/ + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG5(("satWriteSame10: return Table 62 case 4\n")); + return tiSuccess; + } + + + return tiSuccess; +} + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satWriteSame10_1. + * + * SAT implementation for SCSI WRITESANE10 and send FIS request to LL layer. + * This is used when WRITESAME10 is divided into multiple ATA commands + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * \param lba: LBA + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satWriteSame10_1( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext, + bit32 lba + ) +{ + /* + sends SAT_WRITE_DMA_EXT + */ + + bit32 status; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; + bit8 lba1, lba2 ,lba3, lba4; + + TI_DBG5(("satWriteSame10_1 entry: tiDeviceHandle=%p tiIORequest=%p\n", + tiDeviceHandle, tiIORequest)); + + fis = satIOContext->pFis; + + /* MSB */ + lba1 = (bit8)((lba & 0xFF000000) >> (8*3)); + lba2 = (bit8)((lba & 0x00FF0000) >> (8*2)); + lba3 = (bit8)((lba & 0x0000FF00) >> (8*1)); + /* LSB */ + lba4 = (bit8)(lba & 0x000000FF); + + /* SAT_WRITE_DMA_EXT */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_WRITE_DMA_EXT; /* 0x35 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = lba4; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = lba3; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = lba2; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = lba1; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + /* one sector at a time */ + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satWriteSame10CB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + TI_DBG5(("satWriteSame10_1 return status %d\n", status)); + return status; +} + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satWriteSame10_2. + * + * SAT implementation for SCSI WRITESANE10 and send FIS request to LL layer. + * This is used when WRITESAME10 is divided into multiple ATA commands + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * \param lba: LBA + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satWriteSame10_2( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext, + bit32 lba + ) +{ + /* + sends SAT_WRITE_SECTORS_EXT + */ + + bit32 status; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; + bit8 lba1, lba2 ,lba3, lba4; + + TI_DBG5(("satWriteSame10_2 entry: tiDeviceHandle=%p tiIORequest=%p\n", + tiDeviceHandle, tiIORequest)); + + fis = satIOContext->pFis; + + /* MSB */ + lba1 = (bit8)((lba & 0xFF000000) >> (8*3)); + lba2 = (bit8)((lba & 0x00FF0000) >> (8*2)); + lba3 = (bit8)((lba & 0x0000FF00) >> (8*1)); + /* LSB */ + lba4 = (bit8)(lba & 0x000000FF); + + + /* SAT_WRITE_SECTORS_EXT */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_WRITE_SECTORS_EXT; /* 0x34 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = lba4; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = lba3; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = lba2; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = lba1; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + /* one sector at a time */ + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satWriteSame10CB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + TI_DBG5(("satWriteSame10_2 return status %d\n", status)); + return status; +} + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satWriteSame10_3. + * + * SAT implementation for SCSI WRITESANE10 and send FIS request to LL layer. + * This is used when WRITESAME10 is divided into multiple ATA commands + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * \param lba: LBA + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satWriteSame10_3( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext, + bit32 lba + ) +{ + /* + sends SAT_WRITE_FPDMA_QUEUED + */ + + bit32 status; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; + bit8 lba1, lba2 ,lba3, lba4; + + TI_DBG5(("satWriteSame10_3 entry: tiDeviceHandle=%p tiIORequest=%p\n", + tiDeviceHandle, tiIORequest)); + + fis = satIOContext->pFis; + + /* MSB */ + lba1 = (bit8)((lba & 0xFF000000) >> (8*3)); + lba2 = (bit8)((lba & 0x00FF0000) >> (8*2)); + lba3 = (bit8)((lba & 0x0000FF00) >> (8*1)); + /* LSB */ + lba4 = (bit8)(lba & 0x000000FF); + + /* SAT_WRITE_FPDMA_QUEUED */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_FPDMA_QUEUED; /* 0x61 */ + + + /* one sector at a time */ + fis->h.features = 1; /* FIS sector count (7:0) */ + fis->d.featuresExp = 0; /* FIS sector count (15:8) */ + + + fis->d.lbaLow = lba4; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = lba3; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = lba2; /* FIS LBA (23:16) */ + + /* NO FUA bit in the WRITE SAME 10 */ + fis->d.device = 0x40; /* FIS FUA clear */ + + fis->d.lbaLowExp = lba1; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_WRITE; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satWriteSame10CB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + TI_DBG5(("satWriteSame10_2 return status %d\n", status)); + return status; +} +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satWriteSame16. + * + * SAT implementation for SCSI satWriteSame16. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satWriteSame16( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + scsiRspSense_t *pSense; + + pSense = satIOContext->pSense; + + TI_DBG5(("satWriteSame16:start\n")); + + + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, /* == &satIntIo->satOrgTiIORequest */ + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + TI_DBG5(("satWriteSame16: return internal checking\n")); + return tiSuccess; +} + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satLogSense_1. + * + * Part of SAT implementation for SCSI satLogSense. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satLogSense_1( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + bit32 status; + bit32 agRequestType; + satDeviceData_t *pSatDevData; + agsaFisRegHostToDevice_t *fis; + + pSatDevData = satIOContext->pSatDevData; + fis = satIOContext->pFis; + + TI_DBG5(("satLogSense_1: start\n")); + + + /* SAT Rev 8, 10.2.4 p74 */ + if ( pSatDevData->sat48BitSupport == agTRUE ) + { + TI_DBG5(("satLogSense_1: case 2-1 sends READ LOG EXT\n")); + /* sends READ LOG EXT */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_READ_LOG_EXT; /* 0x2F */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = 0x07; /* 0x07 */ + fis->d.lbaMid = 0; /* */ + fis->d.lbaHigh = 0; /* */ + fis->d.device = 0; /* */ + fis->d.lbaLowExp = 0; /* */ + fis->d.lbaMidExp = 0; /* */ + fis->d.lbaHighExp = 0; /* */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 0x01; /* 1 sector counts */ + fis->d.sectorCountExp = 0x00; /* 1 sector counts */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satLogSenseCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + return status; + + } + else + { + TI_DBG5(("satLogSense_1: case 2-2 sends SMART READ LOG\n")); + /* sends SMART READ LOG */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_SMART_READ_LOG; /* 0x2F */ + fis->h.features = 0x00; /* 0xd5 */ + fis->d.lbaLow = 0x06; /* 0x06 */ + fis->d.lbaMid = 0x00; /* 0x4f */ + fis->d.lbaHigh = 0x00; /* 0xc2 */ + fis->d.device = 0; /* */ + fis->d.lbaLowExp = 0; /* */ + fis->d.lbaMidExp = 0; /* */ + fis->d.lbaHighExp = 0; /* */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 0x01; /* */ + fis->d.sectorCountExp = 0x00; /* */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satLogSenseCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + return status; + + } +} + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satSMARTEnable. + * + * Part of SAT implementation for SCSI satLogSense. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satSMARTEnable( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + bit32 status; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; + + TI_DBG4(("satSMARTEnable entry: tiDeviceHandle=%p tiIORequest=%p\n", + tiDeviceHandle, tiIORequest)); + + fis = satIOContext->pFis; + + /* + * Send the SAT_SMART_ENABLE_OPERATIONS command. + */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_SMART_ENABLE_OPERATIONS; /* 0xB0 */ + fis->h.features = 0xD8; + fis->d.lbaLow = 0; + fis->d.lbaMid = 0x4F; + fis->d.lbaHigh = 0xC2; + fis->d.device = 0; + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satSMARTEnableCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + + return status; +} + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satLogSense_3. + * + * Part of SAT implementation for SCSI satLogSense. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satLogSense_3( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + bit32 status; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; + + TI_DBG4(("satLogSense_3 entry: tiDeviceHandle=%p tiIORequest=%p\n", + tiDeviceHandle, tiIORequest)); + + fis = satIOContext->pFis; + /* sends READ LOG EXT */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_SMART_READ_LOG; /* 0x2F */ + fis->h.features = 0xD5; /* 0xd5 */ + fis->d.lbaLow = 0x06; /* 0x06 */ + fis->d.lbaMid = 0x4F; /* 0x4f */ + fis->d.lbaHigh = 0xC2; /* 0xc2 */ + fis->d.device = 0; /* */ + fis->d.lbaLowExp = 0; /* */ + fis->d.lbaMidExp = 0; /* */ + fis->d.lbaHighExp = 0; /* */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 0x01; /* 1 sector counts */ + fis->d.sectorCountExp = 0x00; /* 1 sector counts */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satLogSenseCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + return status; +} + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satLogSense_2. + * + * Part of SAT implementation for SCSI satLogSense. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satLogSense_2( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + bit32 status; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; + + TI_DBG4(("satLogSense_2 entry: tiDeviceHandle=%p tiIORequest=%p\n", + tiDeviceHandle, tiIORequest)); + + fis = satIOContext->pFis; + /* sends READ LOG EXT */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_READ_LOG_EXT; /* 0x2F */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = 0x07; /* 0x07 */ + fis->d.lbaMid = 0; /* */ + fis->d.lbaHigh = 0; /* */ + fis->d.device = 0; /* */ + fis->d.lbaLowExp = 0; /* */ + fis->d.lbaMidExp = 0; /* */ + fis->d.lbaHighExp = 0; /* */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 0x01; /* 1 sector counts */ + fis->d.sectorCountExp = 0x00; /* 1 sector counts */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satLogSenseCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + return status; +} + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satLogSenseAllocate. + * + * Part of SAT implementation for SCSI satLogSense. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * \param payloadSize: size of payload to be allocated. + * \param flag: flag value + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + * \note + * - flag values: LOG_SENSE_0, LOG_SENSE_1, LOG_SENSE_2 + */ +/*****************************************************************************/ +GLOBAL bit32 satLogSenseAllocate( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext, + bit32 payloadSize, + bit32 flag + ) +{ + satDeviceData_t *pSatDevData; + tdIORequestBody_t *tdIORequestBody; + satInternalIo_t *satIntIo = agNULL; + satIOContext_t *satIOContext2; + bit32 status; + + TI_DBG4(("satLogSense_2 entry: tiDeviceHandle=%p tiIORequest=%p\n", + tiDeviceHandle, tiIORequest)); + + pSatDevData = satIOContext->pSatDevData; + + /* create internal satIOContext */ + satIntIo = satAllocIntIoResource( tiRoot, + tiIORequest, /* original request */ + pSatDevData, + payloadSize, + satIntIo); + + if (satIntIo == agNULL) + { + /* memory allocation failure */ + satFreeIntIoResource( tiRoot, + pSatDevData, + satIntIo); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + satIOContext->interruptContext ); + + TI_DBG4(("satLogSense_2: fail in allocation\n")); + return tiSuccess; + } /* end of memory allocation failure */ + + satIntIo->satOrgTiIORequest = tiIORequest; + tdIORequestBody = (tdIORequestBody_t *)satIntIo->satIntRequestBody; + satIOContext2 = &(tdIORequestBody->transport.SATA.satIOContext); + + satIOContext2->pSatDevData = pSatDevData; + satIOContext2->pFis = &(tdIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev); + satIOContext2->pScsiCmnd = &(satIntIo->satIntTiScsiXchg.scsiCmnd); + satIOContext2->pSense = &(tdIORequestBody->transport.SATA.sensePayload); + satIOContext2->pTiSenseData = &(tdIORequestBody->transport.SATA.tiSenseData); + satIOContext2->pTiSenseData->senseData = satIOContext2->pSense; + satIOContext2->tiRequestBody = satIntIo->satIntRequestBody; + satIOContext2->interruptContext = satIOContext->interruptContext; + satIOContext2->satIntIoContext = satIntIo; + satIOContext2->ptiDeviceHandle = tiDeviceHandle; + satIOContext2->satOrgIOContext = satIOContext; + + if (flag == LOG_SENSE_0) + { + /* SAT_SMART_ENABLE_OPERATIONS */ + status = satSMARTEnable( tiRoot, + &(satIntIo->satIntTiIORequest), + tiDeviceHandle, + &(satIntIo->satIntTiScsiXchg), + satIOContext2); + } + else if (flag == LOG_SENSE_1) + { + /* SAT_READ_LOG_EXT */ + status = satLogSense_2( tiRoot, + &(satIntIo->satIntTiIORequest), + tiDeviceHandle, + &(satIntIo->satIntTiScsiXchg), + satIOContext2); + } + else + { + /* SAT_SMART_READ_LOG */ + /* SAT_READ_LOG_EXT */ + status = satLogSense_3( tiRoot, + &(satIntIo->satIntTiIORequest), + tiDeviceHandle, + &(satIntIo->satIntTiScsiXchg), + satIOContext2); + + } + if (status != tiSuccess) + { + satFreeIntIoResource( tiRoot, + pSatDevData, + satIntIo); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + satIOContext->interruptContext ); + return tiSuccess; + } + + + return tiSuccess; +} + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satLogSense. + * + * SAT implementation for SCSI satLogSense. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satLogSense( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + bit32 status; + bit32 agRequestType; + satDeviceData_t *pSatDevData; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit8 *pLogPage; /* Log Page data buffer */ + bit32 flag = 0; + bit16 AllocLen = 0; /* allocation length */ + bit8 AllLogPages[8]; + bit16 lenRead = 0; + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &tiScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + pLogPage = (bit8 *) tiScsiRequest->sglVirtualAddr; + + TI_DBG5(("satLogSense: start\n")); + + osti_memset(&AllLogPages, 0, 8); + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[9] & SCSI_NACA_MASK) || (scsiCmnd->cdb[9] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG2(("satLogSense: return control\n")); + return tiSuccess; + } + + + AllocLen = (bit8)((scsiCmnd->cdb[7] << 8) + scsiCmnd->cdb[8]); + + /* checking PC (Page Control) */ + /* nothing */ + + /* special cases */ + if (AllocLen == 4) + { + TI_DBG1(("satLogSense: AllocLen is 4\n")); + switch (scsiCmnd->cdb[2] & SCSI_LOG_SENSE_PAGE_CODE_MASK) + { + case LOGSENSE_SUPPORTED_LOG_PAGES: + TI_DBG5(("satLogSense: case LOGSENSE_SUPPORTED_LOG_PAGES\n")); + + /* SAT Rev 8, 10.2.5 p76 */ + if (pSatDevData->satSMARTFeatureSet == agTRUE) + { + /* add informational exception log */ + flag = 1; + if (pSatDevData->satSMARTSelfTest == agTRUE) + { + /* add Self-Test results log page */ + flag = 2; + } + } + else + { + /* only supported, no informational exception log, no Self-Test results log page */ + flag = 0; + } + lenRead = 4; + AllLogPages[0] = LOGSENSE_SUPPORTED_LOG_PAGES; /* page code */ + AllLogPages[1] = 0; /* reserved */ + switch (flag) + { + case 0: + /* only supported */ + AllLogPages[2] = 0; /* page length */ + AllLogPages[3] = 1; /* page length */ + break; + case 1: + /* supported and informational exception log */ + AllLogPages[2] = 0; /* page length */ + AllLogPages[3] = 2; /* page length */ + break; + case 2: + /* supported and informational exception log */ + AllLogPages[2] = 0; /* page length */ + AllLogPages[3] = 3; /* page length */ + break; + default: + TI_DBG1(("satLogSense: error unallowed flag value %d\n", flag)); + break; + } + osti_memcpy(pLogPage, &AllLogPages, lenRead); + break; + case LOGSENSE_SELFTEST_RESULTS_PAGE: + TI_DBG5(("satLogSense: case LOGSENSE_SUPPORTED_LOG_PAGES\n")); + lenRead = 4; + AllLogPages[0] = LOGSENSE_SELFTEST_RESULTS_PAGE; /* page code */ + AllLogPages[1] = 0; /* reserved */ + /* page length = SELFTEST_RESULTS_LOG_PAGE_LENGTH - 1 - 3 = 400 = 0x190 */ + AllLogPages[2] = 0x01; + AllLogPages[3] = 0x90; /* page length */ + osti_memcpy(pLogPage, &AllLogPages, lenRead); + + break; + case LOGSENSE_INFORMATION_EXCEPTIONS_PAGE: + TI_DBG5(("satLogSense: case LOGSENSE_SUPPORTED_LOG_PAGES\n")); + lenRead = 4; + AllLogPages[0] = LOGSENSE_INFORMATION_EXCEPTIONS_PAGE; /* page code */ + AllLogPages[1] = 0; /* reserved */ + AllLogPages[2] = 0; /* page length */ + AllLogPages[3] = INFORMATION_EXCEPTIONS_LOG_PAGE_LENGTH - 1 - 3; /* page length */ + osti_memcpy(pLogPage, &AllLogPages, lenRead); + break; + default: + TI_DBG1(("satLogSense: default Page Code 0x%x\n", scsiCmnd->cdb[2] & SCSI_LOG_SENSE_PAGE_CODE_MASK)); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + return tiSuccess; + + } /* if */ + + /* SAT rev8 Table 11 p30*/ + /* checking Page Code */ + switch (scsiCmnd->cdb[2] & SCSI_LOG_SENSE_PAGE_CODE_MASK) + { + case LOGSENSE_SUPPORTED_LOG_PAGES: + TI_DBG5(("satLogSense: case 1\n")); + + /* SAT Rev 8, 10.2.5 p76 */ + + if (pSatDevData->satSMARTFeatureSet == agTRUE) + { + /* add informational exception log */ + flag = 1; + if (pSatDevData->satSMARTSelfTest == agTRUE) + { + /* add Self-Test results log page */ + flag = 2; + } + } + else + { + /* only supported, no informational exception log, no Self-Test results log page */ + flag = 0; + } + AllLogPages[0] = 0; /* page code */ + AllLogPages[1] = 0; /* reserved */ + switch (flag) + { + case 0: + /* only supported */ + AllLogPages[2] = 0; /* page length */ + AllLogPages[3] = 1; /* page length */ + AllLogPages[4] = 0x00; /* supported page list */ + lenRead = (bit8)(MIN(AllocLen, 5)); + break; + case 1: + /* supported and informational exception log */ + AllLogPages[2] = 0; /* page length */ + AllLogPages[3] = 2; /* page length */ + AllLogPages[4] = 0x00; /* supported page list */ + AllLogPages[5] = 0x10; /* supported page list */ + lenRead = (bit8)(MIN(AllocLen, 6)); + break; + case 2: + /* supported and informational exception log */ + AllLogPages[2] = 0; /* page length */ + AllLogPages[3] = 3; /* page length */ + AllLogPages[4] = 0x00; /* supported page list */ + AllLogPages[5] = 0x10; /* supported page list */ + AllLogPages[6] = 0x2F; /* supported page list */ + lenRead = (bit8)(MIN(AllocLen, 7)); + break; + default: + TI_DBG1(("satLogSense: error unallowed flag value %d\n", flag)); + break; + } + + osti_memcpy(pLogPage, &AllLogPages, lenRead); + /* comparing allocation length to Log Page byte size */ + /* SPC-4, 4.3.4.6, p28 */ + if (AllocLen > lenRead ) + { + TI_DBG1(("satLogSense reporting underrun lenRead=0x%x AllocLen=0x%x tiIORequest=%p\n", lenRead, AllocLen, tiIORequest)); + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOUnderRun, + AllocLen - lenRead, + agNULL, + satIOContext->interruptContext ); + } + else + { + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + } + break; + case LOGSENSE_SELFTEST_RESULTS_PAGE: + TI_DBG5(("satLogSense: case 2\n")); + /* checking SMART self-test */ + if (pSatDevData->satSMARTSelfTest == agFALSE) + { + TI_DBG5(("satLogSense: case 2 no SMART Self Test\n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + } + else + { + /* if satSMARTEnabled is false, send SMART_ENABLE_OPERATIONS */ + if (pSatDevData->satSMARTEnabled == agFALSE) + { + TI_DBG5(("satLogSense: case 2 calling satSMARTEnable\n")); + status = satLogSenseAllocate(tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext, + 0, + LOG_SENSE_0 + ); + + return status; + + } + else + { + /* SAT Rev 8, 10.2.4 p74 */ + if ( pSatDevData->sat48BitSupport == agTRUE ) + { + TI_DBG5(("satLogSense: case 2-1 sends READ LOG EXT\n")); + status = satLogSenseAllocate(tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext, + 512, + LOG_SENSE_1 + ); + + return status; + } + else + { + TI_DBG5(("satLogSense: case 2-2 sends SMART READ LOG\n")); + status = satLogSenseAllocate(tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext, + 512, + LOG_SENSE_2 + ); + + return status; + } + } + } + break; + case LOGSENSE_INFORMATION_EXCEPTIONS_PAGE: + TI_DBG5(("satLogSense: case 3\n")); + /* checking SMART feature set */ + if (pSatDevData->satSMARTFeatureSet == agFALSE) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + } + else + { + /* checking SMART feature enabled */ + if (pSatDevData->satSMARTEnabled == agFALSE) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_ATA_DEVICE_FEATURE_NOT_ENABLED, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + } + else + { + /* SAT Rev 8, 10.2.3 p72 */ + TI_DBG5(("satLogSense: case 3 sends SMART RETURN STATUS\n")); + + /* sends SMART RETURN STATUS */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_SMART_RETURN_STATUS;/* 0xB0 */ + fis->h.features = 0xDA; /* FIS features */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaLowExp = 0; /* FIS LBA (31:24) */ + fis->d.lbaMid = 0x4F; /* FIS LBA (15:8 ) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHigh = 0xC2; /* FIS LBA (23:16) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.device = 0; /* FIS DEV is discared in SATA */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved4 = 0; + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satLogSenseCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + + return status; + } + } + break; + default: + TI_DBG1(("satLogSense: default Page Code 0x%x\n", scsiCmnd->cdb[2] & SCSI_LOG_SENSE_PAGE_CODE_MASK)); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + break; + } /* end switch */ + + return tiSuccess; + + +} + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satModeSelect6. + * + * SAT implementation for SCSI satModeSelect6. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satModeSelect6( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + bit32 status; + bit32 agRequestType; + satDeviceData_t *pSatDevData; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit8 *pLogPage; /* Log Page data buffer */ + bit32 StartingIndex = 0; + bit8 PageCode = 0; + bit32 chkCnd = agFALSE; + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &tiScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + pLogPage = (bit8 *) tiScsiRequest->sglVirtualAddr; + + TI_DBG5(("satModeSelect6: start\n")); + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[5] & SCSI_NACA_MASK) || (scsiCmnd->cdb[5] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG2(("satModeSelect6: return control\n")); + return tiSuccess; + } + + /* checking PF bit */ + if ( !(scsiCmnd->cdb[1] & SCSI_MODE_SELECT6_PF_MASK)) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satModeSelect6: PF bit check \n")); + return tiSuccess; + + } + + /* checking Block Descriptor Length on Mode parameter header(6)*/ + if (pLogPage[3] == 8) + { + /* mode parameter block descriptor exists */ + PageCode = (bit8)(pLogPage[12] & 0x3F); /* page code and index is 4 + 8 */ + StartingIndex = 12; + } + else if (pLogPage[3] == 0) + { + /* mode parameter block descriptor does not exist */ + PageCode = (bit8)(pLogPage[4] & 0x3F); /* page code and index is 4 + 0 */ + StartingIndex = 4; + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + return tiSuccess; + } + else + { + TI_DBG1(("satModeSelect6: return mode parameter block descriptor 0x%x\n", pLogPage[3])); + /* no more than one mode parameter block descriptor shall be supported */ + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + + + + switch (PageCode) /* page code */ + { + case MODESELECT_CONTROL_PAGE: + TI_DBG1(("satModeSelect6: Control mode page\n")); + /* + compare pLogPage to expected value (SAT Table 65, p67) + If not match, return check condition + */ + if ( pLogPage[StartingIndex+1] != 0x0A || + pLogPage[StartingIndex+2] != 0x02 || + (pSatDevData->satNCQ == agTRUE && pLogPage[StartingIndex+3] != 0x12) || + (pSatDevData->satNCQ == agFALSE && pLogPage[StartingIndex+3] != 0x02) || + (pLogPage[StartingIndex+4] & BIT3_MASK) != 0x00 || /* SWP bit */ + (pLogPage[StartingIndex+4] & BIT4_MASK) != 0x00 || /* UA_INTLCK_CTRL */ + (pLogPage[StartingIndex+4] & BIT5_MASK) != 0x00 || /* UA_INTLCK_CTRL */ + + (pLogPage[StartingIndex+5] & BIT0_MASK) != 0x00 || /* AUTOLOAD MODE */ + (pLogPage[StartingIndex+5] & BIT1_MASK) != 0x00 || /* AUTOLOAD MODE */ + (pLogPage[StartingIndex+5] & BIT2_MASK) != 0x00 || /* AUTOLOAD MODE */ + (pLogPage[StartingIndex+5] & BIT6_MASK) != 0x00 || /* TAS bit */ + + pLogPage[StartingIndex+8] != 0xFF || + pLogPage[StartingIndex+9] != 0xFF || + pLogPage[StartingIndex+10] != 0x00 || + pLogPage[StartingIndex+11] != 0x00 + ) + { + chkCnd = agTRUE; + } + if (chkCnd == agTRUE) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satModeSelect10: unexpected values\n")); + } + else + { + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + } + return tiSuccess; + break; + case MODESELECT_READ_WRITE_ERROR_RECOVERY_PAGE: + TI_DBG1(("satModeSelect6: Read-Write Error Recovery mode page\n")); + + if ( (pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT6_AWRE_MASK) || + (pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT6_RC_MASK) || + (pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT6_EER_MASK) || + (pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT6_PER_MASK) || + (pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT6_DTE_MASK) || + (pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT6_DCR_MASK) || + (pLogPage[StartingIndex + 10]) || + (pLogPage[StartingIndex + 11]) + ) + { + TI_DBG5(("satModeSelect6: return check condition \n")); + + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_PARAMETER_LIST, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + else + { + TI_DBG5(("satModeSelect6: return GOOD \n")); + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + return tiSuccess; + } + + break; + case MODESELECT_CACHING: + /* SAT rev8 Table67, p69*/ + TI_DBG5(("satModeSelect6: Caching mode page\n")); + if ( (pLogPage[StartingIndex + 2] & 0xFB) || /* 1111 1011 */ + (pLogPage[StartingIndex + 3]) || + (pLogPage[StartingIndex + 4]) || + (pLogPage[StartingIndex + 5]) || + (pLogPage[StartingIndex + 6]) || + (pLogPage[StartingIndex + 7]) || + (pLogPage[StartingIndex + 8]) || + (pLogPage[StartingIndex + 9]) || + (pLogPage[StartingIndex + 10]) || + (pLogPage[StartingIndex + 11]) || + + (pLogPage[StartingIndex + 12] & 0xC1) || /* 1100 0001 */ + (pLogPage[StartingIndex + 13]) || + (pLogPage[StartingIndex + 14]) || + (pLogPage[StartingIndex + 15]) + ) + { + TI_DBG1(("satModeSelect6: return check condition \n")); + + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_PARAMETER_LIST, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + + } + else + { + /* sends ATA SET FEATURES based on WCE bit */ + if ( !(pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT6_WCE_MASK) ) + { + TI_DBG5(("satModeSelect6: disable write cache\n")); + /* sends SET FEATURES */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_SET_FEATURES; /* 0xEF */ + fis->h.features = 0x82; /* disable write cache */ + fis->d.lbaLow = 0; /* */ + fis->d.lbaMid = 0; /* */ + fis->d.lbaHigh = 0; /* */ + fis->d.device = 0; /* */ + fis->d.lbaLowExp = 0; /* */ + fis->d.lbaMidExp = 0; /* */ + fis->d.lbaHighExp = 0; /* */ + fis->d.featuresExp = 0; /* */ + fis->d.sectorCount = 0; /* */ + fis->d.sectorCountExp = 0; /* */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satModeSelect6n10CB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + return status; + } + else + { + TI_DBG5(("satModeSelect6: enable write cache\n")); + /* sends SET FEATURES */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_SET_FEATURES; /* 0xEF */ + fis->h.features = 0x02; /* enable write cache */ + fis->d.lbaLow = 0; /* */ + fis->d.lbaMid = 0; /* */ + fis->d.lbaHigh = 0; /* */ + fis->d.device = 0; /* */ + fis->d.lbaLowExp = 0; /* */ + fis->d.lbaMidExp = 0; /* */ + fis->d.lbaHighExp = 0; /* */ + fis->d.featuresExp = 0; /* */ + fis->d.sectorCount = 0; /* */ + fis->d.sectorCountExp = 0; /* */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satModeSelect6n10CB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + return status; + + } + } + break; + case MODESELECT_INFORMATION_EXCEPTION_CONTROL_PAGE: + TI_DBG5(("satModeSelect6: Informational Exception Control mode page\n")); + if ( (pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT6_PERF_MASK) || + (pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT6_TEST_MASK) + ) + { + TI_DBG1(("satModeSelect6: return check condition \n")); + + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_PARAMETER_LIST, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + else + { + /* sends either ATA SMART ENABLE/DISABLE OPERATIONS based on DEXCPT bit */ + if ( !(pLogPage[StartingIndex + 2] & 0x08) ) + { + TI_DBG5(("satModeSelect6: enable information exceptions reporting\n")); + /* sends SMART ENABLE OPERATIONS */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_SMART_ENABLE_OPERATIONS; /* 0xB0 */ + fis->h.features = 0xD8; /* enable */ + fis->d.lbaLow = 0; /* */ + fis->d.lbaMid = 0x4F; /* 0x4F */ + fis->d.lbaHigh = 0xC2; /* 0xC2 */ + fis->d.device = 0; /* */ + fis->d.lbaLowExp = 0; /* */ + fis->d.lbaMidExp = 0; /* */ + fis->d.lbaHighExp = 0; /* */ + fis->d.featuresExp = 0; /* */ + fis->d.sectorCount = 0; /* */ + fis->d.sectorCountExp = 0; /* */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satModeSelect6n10CB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + return status; + } + else + { + TI_DBG5(("satModeSelect6: disable information exceptions reporting\n")); + /* sends SMART DISABLE OPERATIONS */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_SMART_DISABLE_OPERATIONS; /* 0xB0 */ + fis->h.features = 0xD9; /* disable */ + fis->d.lbaLow = 0; /* */ + fis->d.lbaMid = 0x4F; /* 0x4F */ + fis->d.lbaHigh = 0xC2; /* 0xC2 */ + fis->d.device = 0; /* */ + fis->d.lbaLowExp = 0; /* */ + fis->d.lbaMidExp = 0; /* */ + fis->d.lbaHighExp = 0; /* */ + fis->d.featuresExp = 0; /* */ + fis->d.sectorCount = 0; /* */ + fis->d.sectorCountExp = 0; /* */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satModeSelect6n10CB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + return status; + + } + } + break; + default: + TI_DBG1(("satModeSelect6: Error unknown page code 0x%x\n", pLogPage[12])); + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + +} + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satModeSelect6n10_1. + * + * This function is part of implementation of ModeSelect6 and ModeSelect10. + * When ModeSelect6 or ModeSelect10 is coverted into multiple ATA commands, + * this function is used. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satModeSelect6n10_1( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + /* sends either ATA SET FEATURES based on DRA bit */ + bit32 status; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; + bit8 *pLogPage; /* Log Page data buffer */ + bit32 StartingIndex = 0; + + fis = satIOContext->pFis; + pLogPage = (bit8 *) tiScsiRequest->sglVirtualAddr; + TI_DBG5(("satModeSelect6_1: start\n")); + /* checking Block Descriptor Length on Mode parameter header(6)*/ + if (pLogPage[3] == 8) + { + /* mode parameter block descriptor exists */ + StartingIndex = 12; + } + else + { + /* mode parameter block descriptor does not exist */ + StartingIndex = 4; + } + + /* sends ATA SET FEATURES based on DRA bit */ + if ( !(pLogPage[StartingIndex + 12] & SCSI_MODE_SELECT6_DRA_MASK) ) + { + TI_DBG5(("satModeSelect6_1: enable read look-ahead feature\n")); + /* sends SET FEATURES */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_SET_FEATURES; /* 0xEF */ + fis->h.features = 0xAA; /* enable read look-ahead */ + fis->d.lbaLow = 0; /* */ + fis->d.lbaMid = 0; /* */ + fis->d.lbaHigh = 0; /* */ + fis->d.device = 0; /* */ + fis->d.lbaLowExp = 0; /* */ + fis->d.lbaMidExp = 0; /* */ + fis->d.lbaHighExp = 0; /* */ + fis->d.featuresExp = 0; /* */ + fis->d.sectorCount = 0; /* */ + fis->d.sectorCountExp = 0; /* */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satModeSelect6n10CB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + return status; + } + else + { + TI_DBG5(("satModeSelect6_1: disable read look-ahead feature\n")); + /* sends SET FEATURES */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_SET_FEATURES; /* 0xEF */ + fis->h.features = 0x55; /* disable read look-ahead */ + fis->d.lbaLow = 0; /* */ + fis->d.lbaMid = 0; /* */ + fis->d.lbaHigh = 0; /* */ + fis->d.device = 0; /* */ + fis->d.lbaLowExp = 0; /* */ + fis->d.lbaMidExp = 0; /* */ + fis->d.lbaHighExp = 0; /* */ + fis->d.featuresExp = 0; /* */ + fis->d.sectorCount = 0; /* */ + fis->d.sectorCountExp = 0; /* */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satModeSelect6n10CB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + return status; + } + +} + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satModeSelect10. + * + * SAT implementation for SCSI satModeSelect10. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satModeSelect10( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + bit32 status; + bit32 agRequestType; + satDeviceData_t *pSatDevData; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit8 *pLogPage; /* Log Page data buffer */ + bit16 BlkDescLen = 0; /* Block Descriptor Length */ + bit32 StartingIndex = 0; + bit8 PageCode = 0; + bit32 chkCnd = agFALSE; + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &tiScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + pLogPage = (bit8 *) tiScsiRequest->sglVirtualAddr; + + TI_DBG5(("satModeSelect10: start\n")); + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[9] & SCSI_NACA_MASK) || (scsiCmnd->cdb[9] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG2(("satModeSelect10: return control\n")); + return tiSuccess; + } + + /* checking PF bit */ + if ( !(scsiCmnd->cdb[1] & SCSI_MODE_SELECT10_PF_MASK)) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satModeSelect10: PF bit check \n")); + return tiSuccess; + + } + + BlkDescLen = (bit8)((pLogPage[6] << 8) + pLogPage[7]); + + /* checking Block Descriptor Length on Mode parameter header(10) and LONGLBA bit*/ + if ( (BlkDescLen == 8) && !(pLogPage[4] & SCSI_MODE_SELECT10_LONGLBA_MASK) ) + { + /* mode parameter block descriptor exists and length is 8 byte */ + PageCode = (bit8)(pLogPage[16] & 0x3F); /* page code and index is 8 + 8 */ + StartingIndex = 16; + } + else if ( (BlkDescLen == 16) && (pLogPage[4] & SCSI_MODE_SELECT10_LONGLBA_MASK) ) + { + /* mode parameter block descriptor exists and length is 16 byte */ + PageCode = (bit8)(pLogPage[24] & 0x3F); /* page code and index is 8 + 16 */ + StartingIndex = 24; + } + else if (BlkDescLen == 0) + { + /* + mode parameter block descriptor does not exist + */ + PageCode = (bit8)(pLogPage[8] & 0x3F); /* page code and index is 8 + 0 */ + StartingIndex = 8; + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + return tiSuccess; + } + else + { + TI_DBG1(("satModeSelect10: return mode parameter block descriptor 0x%x\n", BlkDescLen)); + /* no more than one mode parameter block descriptor shall be supported */ + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + /* + for debugging only + */ + if (StartingIndex == 8) + { + tdhexdump("startingindex 8", (bit8 *)pLogPage, 8); + } + else if(StartingIndex == 16) + { + if (PageCode == MODESELECT_CACHING) + { + tdhexdump("startingindex 16", (bit8 *)pLogPage, 16+20); + } + else + { + tdhexdump("startingindex 16", (bit8 *)pLogPage, 16+12); + } + } + else + { + if (PageCode == MODESELECT_CACHING) + { + tdhexdump("startingindex 24", (bit8 *)pLogPage, 24+20); + } + else + { + tdhexdump("startingindex 24", (bit8 *)pLogPage, 24+12); + } + } + switch (PageCode) /* page code */ + { + case MODESELECT_CONTROL_PAGE: + TI_DBG5(("satModeSelect10: Control mode page\n")); + /* + compare pLogPage to expected value (SAT Table 65, p67) + If not match, return check condition + */ + if ( pLogPage[StartingIndex+1] != 0x0A || + pLogPage[StartingIndex+2] != 0x02 || + (pSatDevData->satNCQ == agTRUE && pLogPage[StartingIndex+3] != 0x12) || + (pSatDevData->satNCQ == agFALSE && pLogPage[StartingIndex+3] != 0x02) || + (pLogPage[StartingIndex+4] & BIT3_MASK) != 0x00 || /* SWP bit */ + (pLogPage[StartingIndex+4] & BIT4_MASK) != 0x00 || /* UA_INTLCK_CTRL */ + (pLogPage[StartingIndex+4] & BIT5_MASK) != 0x00 || /* UA_INTLCK_CTRL */ + + (pLogPage[StartingIndex+5] & BIT0_MASK) != 0x00 || /* AUTOLOAD MODE */ + (pLogPage[StartingIndex+5] & BIT1_MASK) != 0x00 || /* AUTOLOAD MODE */ + (pLogPage[StartingIndex+5] & BIT2_MASK) != 0x00 || /* AUTOLOAD MODE */ + (pLogPage[StartingIndex+5] & BIT6_MASK) != 0x00 || /* TAS bit */ + + pLogPage[StartingIndex+8] != 0xFF || + pLogPage[StartingIndex+9] != 0xFF || + pLogPage[StartingIndex+10] != 0x00 || + pLogPage[StartingIndex+11] != 0x00 + ) + { + chkCnd = agTRUE; + } + if (chkCnd == agTRUE) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satModeSelect10: unexpected values\n")); + } + else + { + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + } + return tiSuccess; + break; + case MODESELECT_READ_WRITE_ERROR_RECOVERY_PAGE: + TI_DBG5(("satModeSelect10: Read-Write Error Recovery mode page\n")); + if ( (pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT10_AWRE_MASK) || + (pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT10_RC_MASK) || + (pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT10_EER_MASK) || + (pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT10_PER_MASK) || + (pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT10_DTE_MASK) || + (pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT10_DCR_MASK) || + (pLogPage[StartingIndex + 10]) || + (pLogPage[StartingIndex + 11]) + ) + { + TI_DBG1(("satModeSelect10: return check condition \n")); + + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_PARAMETER_LIST, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + else + { + TI_DBG2(("satModeSelect10: return GOOD \n")); + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + return tiSuccess; + } + + break; + case MODESELECT_CACHING: + /* SAT rev8 Table67, p69*/ + TI_DBG5(("satModeSelect10: Caching mode page\n")); + if ( (pLogPage[StartingIndex + 2] & 0xFB) || /* 1111 1011 */ + (pLogPage[StartingIndex + 3]) || + (pLogPage[StartingIndex + 4]) || + (pLogPage[StartingIndex + 5]) || + (pLogPage[StartingIndex + 6]) || + (pLogPage[StartingIndex + 7]) || + (pLogPage[StartingIndex + 8]) || + (pLogPage[StartingIndex + 9]) || + (pLogPage[StartingIndex + 10]) || + (pLogPage[StartingIndex + 11]) || + + (pLogPage[StartingIndex + 12] & 0xC1) || /* 1100 0001 */ + (pLogPage[StartingIndex + 13]) || + (pLogPage[StartingIndex + 14]) || + (pLogPage[StartingIndex + 15]) + ) + { + TI_DBG1(("satModeSelect10: return check condition \n")); + + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_PARAMETER_LIST, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + + } + else + { + /* sends ATA SET FEATURES based on WCE bit */ + if ( !(pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT10_WCE_MASK) ) + { + TI_DBG5(("satModeSelect10: disable write cache\n")); + /* sends SET FEATURES */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_SET_FEATURES; /* 0xEF */ + fis->h.features = 0x82; /* disable write cache */ + fis->d.lbaLow = 0; /* */ + fis->d.lbaMid = 0; /* */ + fis->d.lbaHigh = 0; /* */ + fis->d.device = 0; /* */ + fis->d.lbaLowExp = 0; /* */ + fis->d.lbaMidExp = 0; /* */ + fis->d.lbaHighExp = 0; /* */ + fis->d.featuresExp = 0; /* */ + fis->d.sectorCount = 0; /* */ + fis->d.sectorCountExp = 0; /* */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satModeSelect6n10CB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + return status; + } + else + { + TI_DBG5(("satModeSelect10: enable write cache\n")); + /* sends SET FEATURES */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_SET_FEATURES; /* 0xEF */ + fis->h.features = 0x02; /* enable write cache */ + fis->d.lbaLow = 0; /* */ + fis->d.lbaMid = 0; /* */ + fis->d.lbaHigh = 0; /* */ + fis->d.device = 0; /* */ + fis->d.lbaLowExp = 0; /* */ + fis->d.lbaMidExp = 0; /* */ + fis->d.lbaHighExp = 0; /* */ + fis->d.featuresExp = 0; /* */ + fis->d.sectorCount = 0; /* */ + fis->d.sectorCountExp = 0; /* */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satModeSelect6n10CB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + return status; + + } + } + break; + case MODESELECT_INFORMATION_EXCEPTION_CONTROL_PAGE: + TI_DBG5(("satModeSelect10: Informational Exception Control mode page\n")); + + if ( (pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT10_PERF_MASK) || + (pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT10_TEST_MASK) + ) + { + TI_DBG1(("satModeSelect10: return check condition \n")); + + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_PARAMETER_LIST, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + else + { + /* sends either ATA SMART ENABLE/DISABLE OPERATIONS based on DEXCPT bit */ + if ( !(pLogPage[StartingIndex + 2] & SCSI_MODE_SELECT10_DEXCPT_MASK) ) + { + TI_DBG5(("satModeSelect10: enable information exceptions reporting\n")); + /* sends SMART ENABLE OPERATIONS */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_SMART_ENABLE_OPERATIONS; /* 0xB0 */ + fis->h.features = 0xD8; /* enable */ + fis->d.lbaLow = 0; /* */ + fis->d.lbaMid = 0x4F; /* 0x4F */ + fis->d.lbaHigh = 0xC2; /* 0xC2 */ + fis->d.device = 0; /* */ + fis->d.lbaLowExp = 0; /* */ + fis->d.lbaMidExp = 0; /* */ + fis->d.lbaHighExp = 0; /* */ + fis->d.featuresExp = 0; /* */ + fis->d.sectorCount = 0; /* */ + fis->d.sectorCountExp = 0; /* */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satModeSelect6n10CB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + return status; + } + else + { + TI_DBG5(("satModeSelect10: disable information exceptions reporting\n")); + /* sends SMART DISABLE OPERATIONS */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_SMART_DISABLE_OPERATIONS; /* 0xB0 */ + fis->h.features = 0xD9; /* disable */ + fis->d.lbaLow = 0; /* */ + fis->d.lbaMid = 0x4F; /* 0x4F */ + fis->d.lbaHigh = 0xC2; /* 0xC2 */ + fis->d.device = 0; /* */ + fis->d.lbaLowExp = 0; /* */ + fis->d.lbaMidExp = 0; /* */ + fis->d.lbaHighExp = 0; /* */ + fis->d.featuresExp = 0; /* */ + fis->d.sectorCount = 0; /* */ + fis->d.sectorCountExp = 0; /* */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satModeSelect6n10CB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + return status; + + } + } + break; + default: + TI_DBG1(("satModeSelect10: Error unknown page code 0x%x\n", pLogPage[12])); + satSetSensePayload( pSense, + SCSI_SNSKEY_NO_SENSE, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + +} + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satSynchronizeCache10. + * + * SAT implementation for SCSI satSynchronizeCache10. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satSynchronizeCache10( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + bit32 status; + bit32 agRequestType; + satDeviceData_t *pSatDevData; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &tiScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + TI_DBG5(("satSynchronizeCache10: start\n")); + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[9] & SCSI_NACA_MASK) || (scsiCmnd->cdb[9] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG2(("satSynchronizeCache10: return control\n")); + return tiSuccess; + } + + /* checking IMMED bit */ + if (scsiCmnd->cdb[1] & SCSI_SYNC_CACHE_IMMED_MASK) + { + TI_DBG1(("satSynchronizeCache10: GOOD status due to IMMED bit\n")); + + /* return GOOD status first here */ + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + } + + /* sends FLUSH CACHE or FLUSH CACHE EXT */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + TI_DBG5(("satSynchronizeCache10: sends FLUSH CACHE EXT\n")); + /* FLUSH CACHE EXT */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_FLUSH_CACHE_EXT; /* 0xEA */ + fis->h.features = 0; /* FIS reserve */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaLowExp = 0; /* FIS LBA (31:24) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.device = 0; /* FIS DEV is discared in SATA */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved4 = 0; + fis->d.reserved5 = 0; + + } + else + { + TI_DBG5(("satSynchronizeCache10: sends FLUSH CACHE\n")); + /* FLUSH CACHE */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_FLUSH_CACHE; /* 0xE7 */ + fis->h.features = 0; /* FIS features NA */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.device = 0; /* FIS DEV is discared in SATA */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved4 = 0; + fis->d.reserved5 = 0; + + } + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satSynchronizeCache10n16CB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + + return (status); +} + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satSynchronizeCache16. + * + * SAT implementation for SCSI satSynchronizeCache16. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satSynchronizeCache16( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + bit32 status; + bit32 agRequestType; + satDeviceData_t *pSatDevData; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &tiScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + TI_DBG5(("satSynchronizeCache16: start\n")); + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[15] & SCSI_NACA_MASK) || (scsiCmnd->cdb[15] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satSynchronizeCache16: return control\n")); + return tiSuccess; + } + + + /* checking IMMED bit */ + if (scsiCmnd->cdb[1] & SCSI_SYNC_CACHE_IMMED_MASK) + { + TI_DBG1(("satSynchronizeCache16: GOOD status due to IMMED bit\n")); + + /* return GOOD status first here */ + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + } + + /* sends FLUSH CACHE or FLUSH CACHE EXT */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + TI_DBG5(("satSynchronizeCache16: sends FLUSH CACHE EXT\n")); + /* FLUSH CACHE EXT */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_FLUSH_CACHE_EXT; /* 0xEA */ + fis->h.features = 0; /* FIS reserve */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaLowExp = 0; /* FIS LBA (31:24) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.device = 0; /* FIS DEV is discared in SATA */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved4 = 0; + fis->d.reserved5 = 0; + + } + else + { + TI_DBG5(("satSynchronizeCache16: sends FLUSH CACHE\n")); + /* FLUSH CACHE */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_FLUSH_CACHE; /* 0xE7 */ + fis->h.features = 0; /* FIS features NA */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.device = 0; /* FIS DEV is discared in SATA */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved4 = 0; + fis->d.reserved5 = 0; + + } + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satSynchronizeCache10n16CB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + + return (status); +} + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satWriteAndVerify10. + * + * SAT implementation for SCSI satWriteAndVerify10. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satWriteAndVerify10( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + /* + combination of write10 and verify10 + */ + + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satDeviceData_t *pSatDevData; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 lba = 0; + bit32 tl = 0; + bit32 LoopNum = 1; + bit8 LBA[4]; + bit8 TL[4]; + bit32 rangeChk = agFALSE; /* lba and tl range check */ + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &tiScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + TI_DBG5(("satWriteAndVerify10: start\n")); + + + /* checking BYTCHK bit */ + if (scsiCmnd->cdb[1] & SCSI_WRITE_N_VERIFY_BYTCHK_MASK) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satWriteAndVerify10: BYTCHK bit checking \n")); + return tiSuccess; + } + + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[9] & SCSI_NACA_MASK) || (scsiCmnd->cdb[9] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satWriteAndVerify10: return control\n")); + return tiSuccess; + } + + osti_memset(LBA, 0, sizeof(LBA)); + osti_memset(TL, 0, sizeof(TL)); + + /* do not use memcpy due to indexing in LBA and TL */ + LBA[0] = scsiCmnd->cdb[2]; /* MSB */ + LBA[1] = scsiCmnd->cdb[3]; + LBA[2] = scsiCmnd->cdb[4]; + LBA[3] = scsiCmnd->cdb[5]; /* LSB */ + + TL[0] = 0; + TL[1] = 0; + TL[2] = scsiCmnd->cdb[7]; /* MSB */ + TL[3] = scsiCmnd->cdb[8]; /* LSB */ + + rangeChk = satAddNComparebit32(LBA, TL); + + /* cbd10; computing LBA and transfer length */ + lba = (scsiCmnd->cdb[2] << (8*3)) + (scsiCmnd->cdb[3] << (8*2)) + + (scsiCmnd->cdb[4] << 8) + scsiCmnd->cdb[5]; + tl = (scsiCmnd->cdb[7] << 8) + scsiCmnd->cdb[8]; + + + /* Table 34, 9.1, p 46 */ + /* + note: As of 2/10/2006, no support for DMA QUEUED + */ + + /* + Table 34, 9.1, p 46, b + When no 48-bit addressing support or NCQ, if LBA is beyond (2^28 - 1), + return check condition + */ + if (pSatDevData->satNCQ != agTRUE && + pSatDevData->sat48BitSupport != agTRUE + ) + { + if (lba > SAT_TR_LBA_LIMIT - 1) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satWriteAndVerify10: return LBA out of range\n")); + return tiSuccess; + } + + if (rangeChk) // if (lba + tl > SAT_TR_LBA_LIMIT) + { + TI_DBG1(("satWrite10: return LBA+TL out of range, not EXT\n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + return tiSuccess; + } + } + + + /* case 1 and 2 */ + if (!rangeChk) // if (lba + tl <= SAT_TR_LBA_LIMIT) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 2 */ + /* WRITE DMA*/ + /* can't fit the transfer length */ + TI_DBG5(("satWriteAndVerify10: case 2 !!!\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_DMA; /* 0xCA */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (scsiCmnd->cdb[2] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_DMA; + } + else + { + /* case 1 */ + /* WRITE MULTIPLE or WRITE SECTOR(S) */ + /* WRITE SECTORS for easier implemetation */ + /* can't fit the transfer length */ + TI_DBG5(("satWriteAndVerify10: case 1 !!!\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_SECTORS; /* 0x30 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (scsiCmnd->cdb[2] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + satIOContext->ATACmd = SAT_WRITE_SECTORS; + + } + } + + /* case 3 and 4 */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 3 */ + /* WRITE DMA EXT or WRITE DMA FUA EXT */ + TI_DBG5(("satWriteAndVerify10: case 3\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + /* SAT_WRITE_DMA_FUA_EXT is optional and we don't support it */ + fis->h.command = SAT_WRITE_DMA_EXT; /* 0x35 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[7]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_DMA_EXT; + } + else + { + /* case 4 */ + /* WRITE MULTIPLE EXT or WRITE MULTIPLE FUA EXT or WRITE SECTOR(S) EXT */ + /* WRITE SECTORS EXT for easier implemetation */ + TI_DBG5(("satWriteAndVerify10: case 4\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_SECTORS_EXT; /* 0x34 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[7]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + satIOContext->ATACmd = SAT_WRITE_SECTORS_EXT; + } + } + /* case 5 */ + if (pSatDevData->satNCQ == agTRUE) + { + /* WRITE FPDMA QUEUED */ + if (pSatDevData->sat48BitSupport != agTRUE) + { + TI_DBG5(("satWriteAndVerify10: case 5 !!! error NCQ but 28 bit address support \n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + TI_DBG5(("satWriteAndVerify10: case 5\n")); + + /* Support 48-bit FPDMA addressing, use WRITE FPDMA QUEUE command */ + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_FPDMA_QUEUED; /* 0x61 */ + fis->h.features = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + + /* Check FUA bit */ + if (scsiCmnd->cdb[1] & SCSI_WRITE_N_VERIFY10_FUA_MASK) + fis->d.device = 0xC0; /* FIS FUA set */ + else + fis->d.device = 0x40; /* FIS FUA clear */ + + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = scsiCmnd->cdb[7]; /* FIS sector count (15:8) */ + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_FPDMA_QUEUED; + } + + satIOContext->currentLBA = lba; + satIOContext->OrgTL = tl; + + /* + computing number of loop and remainder for tl + 0xFF in case not ext + 0xFFFF in case EXT + */ + if (fis->h.command == SAT_WRITE_SECTORS || fis->h.command == SAT_WRITE_DMA) + { + LoopNum = satComputeLoopNum(tl, 0xFF); + } + else if (fis->h.command == SAT_WRITE_SECTORS_EXT || + fis->h.command == SAT_WRITE_DMA_EXT || + fis->h.command == SAT_WRITE_DMA_FUA_EXT + ) + { + /* SAT_READ_SECTORS_EXT, SAT_READ_DMA_EXT */ + LoopNum = satComputeLoopNum(tl, 0xFFFF); + } + else + { + /* SAT_WRITE_FPDMA_QUEUED */ + LoopNum = satComputeLoopNum(tl, 0xFFFF); + } + + satIOContext->LoopNum = LoopNum; + + + if (LoopNum == 1) + { + TI_DBG5(("satWriteAndVerify10: NON CHAINED data\n")); + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satNonChainedWriteNVerifyCB; + } + else + { + TI_DBG1(("satWriteAndVerify10: CHAINED data\n")); + /* re-setting tl */ + if (fis->h.command == SAT_WRITE_SECTORS || fis->h.command == SAT_WRITE_DMA) + { + fis->d.sectorCount = 0xFF; + } + else if (fis->h.command == SAT_WRITE_SECTORS_EXT || + fis->h.command == SAT_WRITE_DMA_EXT || + fis->h.command == SAT_WRITE_DMA_FUA_EXT + ) + { + fis->d.sectorCount = 0xFF; + fis->d.sectorCountExp = 0xFF; + } + else + { + /* SAT_WRITE_FPDMA_QUEUED */ + fis->h.features = 0xFF; + fis->d.featuresExp = 0xFF; + } + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satChainedWriteNVerifyCB; + } + + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + return (status); + +} + + + + + + +#ifdef REMOVED +GLOBAL bit32 satWriteAndVerify10( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + /* + combination of write10 and verify10 + */ + + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satDeviceData_t *pSatDevData; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 lba = 0; + bit32 tl = 0; + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &tiScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + TI_DBG5(("satWriteAndVerify10: start\n")); + + + /* checking BYTCHK bit */ + if (scsiCmnd->cdb[1] & SCSI_WRITE_N_VERIFY_BYTCHK_MASK) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satWriteAndVerify10: BYTCHK bit checking \n")); + return tiSuccess; + } + + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[9] & SCSI_NACA_MASK) || (scsiCmnd->cdb[9] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG2(("satWriteAndVerify10: return control\n")); + return tiSuccess; + } + + /* let's do write10 */ + if ( pSatDevData->sat48BitSupport != agTRUE ) + { + /* + writeandverify10 but no support for 48 bit addressing -> problem in transfer + length(sector count) + */ + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satWriteAndVerify10: return internal checking\n")); + return tiSuccess; + } + + /* cbd10; computing LBA and transfer length */ + lba = (scsiCmnd->cdb[2] << (8*3)) + (scsiCmnd->cdb[3] << (8*2)) + + (scsiCmnd->cdb[4] << 8) + scsiCmnd->cdb[5]; + tl = (scsiCmnd->cdb[7] << 8) + scsiCmnd->cdb[8]; + + + /* Table 34, 9.1, p 46 */ + /* + note: As of 2/10/2006, no support for DMA QUEUED + */ + + /* + Table 34, 9.1, p 46, b + When no 48-bit addressing support or NCQ, if LBA is beyond (2^28 - 1), + return check condition + */ + if (pSatDevData->satNCQ != agTRUE && + pSatDevData->sat48BitSupport != agTRUE + ) + { + if (lba > SAT_TR_LBA_LIMIT - 1) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satWriteAndVerify10: return LBA out of range\n")); + return tiSuccess; + } + } + + + /* case 1 and 2 */ + if (lba + tl <= SAT_TR_LBA_LIMIT) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 2 */ + /* WRITE DMA*/ + /* can't fit the transfer length */ + TI_DBG5(("satWriteAndVerify10: case 2 !!!\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_DMA; /* 0xCA */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (0x4 << 4) | (scsiCmnd->cdb[2] & 0xF); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_DMA; + } + else + { + /* case 1 */ + /* WRITE MULTIPLE or WRITE SECTOR(S) */ + /* WRITE SECTORS for easier implemetation */ + /* can't fit the transfer length */ + TI_DBG5(("satWriteAndVerify10: case 1 !!!\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_SECTORS; /* 0x30 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (0x4 << 4) | (scsiCmnd->cdb[2] & 0xF); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + satIOContext->ATACmd = SAT_WRITE_SECTORS; + + } + } + + /* case 3 and 4 */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 3 */ + /* WRITE DMA EXT or WRITE DMA FUA EXT */ + TI_DBG5(("satWriteAndVerify10: case 3\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + /* SAT_WRITE_DMA_FUA_EXT is optional and we don't support it */ + fis->h.command = SAT_WRITE_DMA_EXT; /* 0x35 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[7]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + } + else + { + /* case 4 */ + /* WRITE MULTIPLE EXT or WRITE MULTIPLE FUA EXT or WRITE SECTOR(S) EXT */ + /* WRITE SECTORS EXT for easier implemetation */ + TI_DBG5(("satWriteAndVerify10: case 4\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_SECTORS_EXT; /* 0x34 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[7]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + } + } + /* case 5 */ + if (pSatDevData->satNCQ == agTRUE) + { + /* WRITE FPDMA QUEUED */ + if (pSatDevData->sat48BitSupport != agTRUE) + { + TI_DBG5(("satWriteAndVerify10: case 5 !!! error NCQ but 28 bit address support \n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + TI_DBG5(("satWriteAndVerify10: case 5\n")); + + /* Support 48-bit FPDMA addressing, use WRITE FPDMA QUEUE command */ + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_FPDMA_QUEUED; /* 0x61 */ + fis->h.features = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + + /* Check FUA bit */ + if (scsiCmnd->cdb[1] & SCSI_WRITE_N_VERIFY10_FUA_MASK) + fis->d.device = 0xC0; /* FIS FUA set */ + else + fis->d.device = 0x40; /* FIS FUA clear */ + + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = scsiCmnd->cdb[7]; /* FIS sector count (15:8) */ + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_WRITE; + } + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satWriteAndVerify10CB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + return (status); + +} +#endif /* REMOVED */ + +#ifdef REMOVED +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satWriteAndVerify10_1. + * + * SAT implementation for SCSI satWriteAndVerify10_1. + * Sub function of satWriteAndVerify10 + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satWriteAndVerify10_1( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satDeviceData_t *pSatDevData; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &tiScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + TI_DBG5(("satWriteAndVerify10_1: start\n")); + + if (pSatDevData->sat48BitSupport == agTRUE) + { + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_READ_VERIFY_SECTORS_EXT;/* 0x42 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set 01000000 */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[7]; /* FIS sector count (15:8) */ + + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satWriteAndVerify10CB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + + TI_DBG1(("satWriteAndVerify10_1: return status %d\n", status)); + return (status); + } + else + { + /* can't fit in SAT_READ_VERIFY_SECTORS becasue of Sector Count and LBA */ + TI_DBG1(("satWriteAndVerify10_1: can't fit in SAT_READ_VERIFY_SECTORS\n")); + return tiError; + } + + + return tiSuccess; +} +#endif /* REMOVED */ + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satWriteAndVerify12. + * + * SAT implementation for SCSI satWriteAndVerify12. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satWriteAndVerify12( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + /* + combination of write12 and verify12 + temp: since write12 is not support (due to internal checking), no support + */ + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satDeviceData_t *pSatDevData; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 lba = 0; + bit32 tl = 0; + bit32 LoopNum = 1; + bit8 LBA[4]; + bit8 TL[4]; + bit32 rangeChk = agFALSE; /* lba and tl range check */ + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &tiScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + TI_DBG5(("satWriteAndVerify12: start\n")); + + /* checking BYTCHK bit */ + if (scsiCmnd->cdb[1] & SCSI_WRITE_N_VERIFY_BYTCHK_MASK) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satWriteAndVerify12: BYTCHK bit checking \n")); + return tiSuccess; + } + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[11] & SCSI_NACA_MASK) || (scsiCmnd->cdb[11] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG2(("satWriteAndVerify12: return control\n")); + return tiSuccess; + } + + osti_memset(LBA, 0, sizeof(LBA)); + osti_memset(TL, 0, sizeof(TL)); + + /* do not use memcpy due to indexing in LBA and TL */ + LBA[0] = scsiCmnd->cdb[2]; /* MSB */ + LBA[1] = scsiCmnd->cdb[3]; + LBA[2] = scsiCmnd->cdb[4]; + LBA[3] = scsiCmnd->cdb[5]; /* LSB */ + + TL[0] = scsiCmnd->cdb[6]; /* MSB */ + TL[1] = scsiCmnd->cdb[7]; + TL[2] = scsiCmnd->cdb[7]; + TL[3] = scsiCmnd->cdb[8]; /* LSB */ + + rangeChk = satAddNComparebit32(LBA, TL); + + lba = satComputeCDB12LBA(satIOContext); + tl = satComputeCDB12TL(satIOContext); + + + /* Table 34, 9.1, p 46 */ + /* + note: As of 2/10/2006, no support for DMA QUEUED + */ + + /* + Table 34, 9.1, p 46, b + When no 48-bit addressing support or NCQ, if LBA is beyond (2^28 - 1), + return check condition + */ + if (pSatDevData->satNCQ != agTRUE && + pSatDevData->sat48BitSupport != agTRUE + ) + { + if (lba > SAT_TR_LBA_LIMIT - 1) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satWriteAndVerify12: return LBA out of range, not EXT\n")); + return tiSuccess; + } + + if (rangeChk) // if (lba + tl > SAT_TR_LBA_LIMIT) + { + TI_DBG1(("satWriteAndVerify12: return LBA+TL out of range, not EXT\n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + return tiSuccess; + } + } + + /* case 1 and 2 */ + if (!rangeChk) // if (lba + tl <= SAT_TR_LBA_LIMIT) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 2 */ + /* WRITE DMA*/ + /* In case that we can't fit the transfer length, we loop */ + TI_DBG5(("satWriteAndVerify12: case 2\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_DMA; /* 0xCA */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (scsiCmnd->cdb[2] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[9]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_DMA; + } + else + { + /* case 1 */ + /* WRITE MULTIPLE or WRITE SECTOR(S) */ + /* WRITE SECTORS for easier implemetation */ + /* In case that we can't fit the transfer length, we loop */ + TI_DBG5(("satWriteAndVerify12: case 1\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_SECTORS; /* 0x30 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (scsiCmnd->cdb[2] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[9]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + satIOContext->ATACmd = SAT_WRITE_SECTORS; + } + } + + /* case 3 and 4 */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 3 */ + /* WRITE DMA EXT or WRITE DMA FUA EXT */ + TI_DBG5(("satWriteAndVerify12: case 3\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + /* SAT_WRITE_DMA_FUA_EXT is optional and we don't support it */ + fis->h.command = SAT_WRITE_DMA_EXT; /* 0x35 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[9]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[8]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_DMA_EXT; + } + else + { + /* case 4 */ + /* WRITE MULTIPLE EXT or WRITE MULTIPLE FUA EXT or WRITE SECTOR(S) EXT */ + /* WRITE SECTORS EXT for easier implemetation */ + TI_DBG5(("satWriteAndVerify12: case 4\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_SECTORS_EXT; /* 0x34 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[9]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[8]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + satIOContext->ATACmd = SAT_WRITE_SECTORS_EXT; + } + } + + /* case 5 */ + if (pSatDevData->satNCQ == agTRUE) + { + /* WRITE FPDMA QUEUED */ + if (pSatDevData->sat48BitSupport != agTRUE) + { + TI_DBG5(("satWriteAndVerify12: case 5 !!! error NCQ but 28 bit address support \n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + TI_DBG6(("satWriteAndVerify12: case 5\n")); + + /* Support 48-bit FPDMA addressing, use WRITE FPDMA QUEUE command */ + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_FPDMA_QUEUED; /* 0x61 */ + fis->h.features = scsiCmnd->cdb[9]; /* FIS sector count (7:0) */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + + /* Check FUA bit */ + if (scsiCmnd->cdb[1] & SCSI_WRITE12_FUA_MASK) + fis->d.device = 0xC0; /* FIS FUA set */ + else + fis->d.device = 0x40; /* FIS FUA clear */ + + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = scsiCmnd->cdb[8]; /* FIS sector count (15:8) */ + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_FPDMA_QUEUED; + } + + satIOContext->currentLBA = lba; +// satIOContext->OrgLBA = lba; + satIOContext->OrgTL = tl; + + /* + computing number of loop and remainder for tl + 0xFF in case not ext + 0xFFFF in case EXT + */ + if (fis->h.command == SAT_WRITE_SECTORS || fis->h.command == SAT_WRITE_DMA) + { + LoopNum = satComputeLoopNum(tl, 0xFF); + } + else if (fis->h.command == SAT_WRITE_SECTORS_EXT || + fis->h.command == SAT_WRITE_DMA_EXT || + fis->h.command == SAT_WRITE_DMA_FUA_EXT + ) + { + /* SAT_READ_SECTORS_EXT, SAT_READ_DMA_EXT */ + LoopNum = satComputeLoopNum(tl, 0xFFFF); + } + else + { + /* SAT_WRITE_FPDMA_QUEUEDK */ + LoopNum = satComputeLoopNum(tl, 0xFFFF); + } + + satIOContext->LoopNum = LoopNum; + satIOContext->LoopNum2 = LoopNum; + + + if (LoopNum == 1) + { + TI_DBG5(("satWriteAndVerify12: NON CHAINED data\n")); + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satNonChainedWriteNVerifyCB; + } + else + { + TI_DBG1(("satWriteAndVerify12: CHAINED data\n")); + /* re-setting tl */ + if (fis->h.command == SAT_WRITE_SECTORS || fis->h.command == SAT_WRITE_DMA) + { + fis->d.sectorCount = 0xFF; + } + else if (fis->h.command == SAT_WRITE_SECTORS_EXT || + fis->h.command == SAT_WRITE_DMA_EXT || + fis->h.command == SAT_WRITE_DMA_FUA_EXT + ) + { + fis->d.sectorCount = 0xFF; + fis->d.sectorCountExp = 0xFF; + } + else + { + /* SAT_WRITE_FPDMA_QUEUED */ + fis->h.features = 0xFF; + fis->d.featuresExp = 0xFF; + } + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satChainedWriteNVerifyCB; + } + + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + return (status); +} + +GLOBAL bit32 satNonChainedWriteNVerify_Verify( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satDeviceData_t *pSatDevData; + tiIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &tiScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + TI_DBG5(("satNonChainedWriteNVerify_Verify: start\n")); + + if (pSatDevData->sat48BitSupport == agTRUE) + { + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_READ_VERIFY_SECTORS_EXT;/* 0x42 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set 01000000 */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[7]; /* FIS sector count (15:8) */ + + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satNonChainedWriteNVerifyCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + + TI_DBG1(("satNonChainedWriteNVerify_Verify: return status %d\n", status)); + return (status); + } + else + { + /* can't fit in SAT_READ_VERIFY_SECTORS becasue of Sector Count and LBA */ + TI_DBG1(("satNonChainedWriteNVerify_Verify: can't fit in SAT_READ_VERIFY_SECTORS\n")); + return tiError; + } + +} + +GLOBAL bit32 satChainedWriteNVerify_Write( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + /* + Assumption: error check on lba and tl has been done in satWrite*() + lba = lba + tl; + */ + bit32 status; + satIOContext_t *satOrgIOContext = agNULL; + tiIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + bit32 lba = 0; + bit32 DenomTL = 0xFF; + bit32 Remainder = 0; + bit8 LBA[4]; /* 0 MSB, 3 LSB */ + + TI_DBG1(("satChainedWriteNVerify_Write: start\n")); + + fis = satIOContext->pFis; + satOrgIOContext = satIOContext->satOrgIOContext; + scsiCmnd = satOrgIOContext->pScsiCmnd; + + osti_memset(LBA,0, sizeof(LBA)); + + switch (satOrgIOContext->ATACmd) + { + case SAT_WRITE_DMA: + DenomTL = 0xFF; + break; + case SAT_WRITE_SECTORS: + DenomTL = 0xFF; + break; + case SAT_WRITE_DMA_EXT: + DenomTL = 0xFFFF; + break; + case SAT_WRITE_DMA_FUA_EXT: + DenomTL = 0xFFFF; + break; + case SAT_WRITE_SECTORS_EXT: + DenomTL = 0xFFFF; + break; + case SAT_WRITE_FPDMA_QUEUED: + DenomTL = 0xFFFF; + break; + default: + TI_DBG1(("satChainedWriteNVerify_Write: error incorrect ata command 0x%x\n", satIOContext->ATACmd)); + return tiError; + break; + } + + Remainder = satOrgIOContext->OrgTL % DenomTL; + satOrgIOContext->currentLBA = satOrgIOContext->currentLBA + DenomTL; + lba = satOrgIOContext->currentLBA; + + LBA[0] = (bit8)((lba & 0xF000) >> (8 * 3)); /* MSB */ + LBA[1] = (bit8)((lba & 0xF00) >> (8 * 2)); + LBA[2] = (bit8)((lba & 0xF0) >> 8); + LBA[3] = (bit8)(lba & 0xF); /* LSB */ + + switch (satOrgIOContext->ATACmd) + { + case SAT_WRITE_DMA: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_DMA; /* 0xCA */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (LBA[0] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->d.sectorCount = (bit8)Remainder; /* FIS sector count (7:0) */ + } + else + { + fis->d.sectorCount = 0xFF; /* FIS sector count (7:0) */ + } + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + + break; + case SAT_WRITE_SECTORS: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_SECTORS; /* 0x30 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (LBA[0] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->d.sectorCount = (bit8)Remainder; /* FIS sector count (7:0) */ + } + else + { + fis->d.sectorCount = 0xFF; /* FIS sector count (7:0) */ + } + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + + break; + case SAT_WRITE_DMA_EXT: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_DMA_EXT; /* 0x3D */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = LBA[0]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->d.sectorCount = (bit8)(Remainder & 0xFF); /* FIS sector count (7:0) */ + fis->d.sectorCountExp = (bit8)((Remainder & 0xFF00) >> 8); /* FIS sector count (15:8) */ + } + else + { + fis->d.sectorCount = 0xFF; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0xFF; /* FIS sector count (15:8) */ + } + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + + break; + case SAT_WRITE_SECTORS_EXT: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_SECTORS_EXT; /* 0x34 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = LBA[0]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->d.sectorCount = (bit8)(Remainder & 0xFF); /* FIS sector count (7:0) */ + fis->d.sectorCountExp = (bit8)((Remainder & 0xFF00) >> 8); /* FIS sector count (15:8) */ + } + else + { + fis->d.sectorCount = 0xFF; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0xFF; /* FIS sector count (15:8) */ + } + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + + break; + case SAT_WRITE_FPDMA_QUEUED: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_FPDMA_QUEUED; /* 0x61 */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + + /* Check FUA bit */ + if (scsiCmnd->cdb[1] & SCSI_WRITE10_FUA_MASK) + fis->d.device = 0xC0; /* FIS FUA set */ + else + fis->d.device = 0x40; /* FIS FUA clear */ + + fis->d.lbaLowExp = LBA[0];; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->h.features = (bit8)(Remainder & 0xFF); /* FIS sector count (7:0) */ + fis->d.featuresExp = (bit8)((Remainder & 0xFF00) >> 8); /* FIS sector count (15:8) */ + } + else + { + fis->h.features = 0xFF; /* FIS sector count (7:0) */ + fis->d.featuresExp = 0xFF; /* FIS sector count (15:8) */ + } + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_WRITE; + break; + + default: + TI_DBG1(("satChainedWriteNVerify_Write: error incorrect ata command 0x%x\n", satIOContext->ATACmd)); + return tiError; + break; + } + + /* Initialize CB for SATA completion. + */ + /* chained data */ + satIOContext->satCompleteCB = &satChainedWriteNVerifyCB; + + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + TI_DBG5(("satChainedWriteNVerify_Write: return\n")); + return (status); + +} + +/* + similar to write12 and verify10; + this will be similar to verify12 + */ +GLOBAL bit32 satChainedWriteNVerify_Start_Verify( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + /* + deal with transfer length; others have been handled previously at this point; + no LBA check; no range check; + */ + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + satDeviceData_t *pSatDevData; + tiIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 lba = 0; + bit32 tl = 0; + bit32 LoopNum = 1; + bit8 LBA[4]; + bit8 TL[4]; + + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &tiScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + + TI_DBG5(("satChainedWriteNVerify_Start_Verify: start\n")); + + osti_memset(LBA, 0, sizeof(LBA)); + osti_memset(TL, 0, sizeof(TL)); + + /* do not use memcpy due to indexing in LBA and TL */ + LBA[0] = scsiCmnd->cdb[2]; /* MSB */ + LBA[1] = scsiCmnd->cdb[3]; + LBA[2] = scsiCmnd->cdb[4]; + LBA[3] = scsiCmnd->cdb[5]; /* LSB */ + + TL[0] = scsiCmnd->cdb[6]; /* MSB */ + TL[1] = scsiCmnd->cdb[7]; + TL[2] = scsiCmnd->cdb[7]; + TL[3] = scsiCmnd->cdb[8]; /* LSB */ + + lba = satComputeCDB12LBA(satIOContext); + tl = satComputeCDB12TL(satIOContext); + + if (pSatDevData->sat48BitSupport == agTRUE) + { + TI_DBG5(("satChainedWriteNVerify_Start_Verify: SAT_READ_VERIFY_SECTORS_EXT\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + fis->h.command = SAT_READ_VERIFY_SECTORS_EXT;/* 0x42 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set 01000000 */ + fis->d.lbaLowExp = scsiCmnd->cdb[2]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[7]; /* FIS sector count (15:8) */ + + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + satIOContext->ATACmd = SAT_READ_VERIFY_SECTORS_EXT; + } + else + { + TI_DBG5(("satChainedWriteNVerify_Start_Verify: SAT_READ_VERIFY_SECTORS\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS; /* 0x40 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[5]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[4]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[3]; /* FIS LBA (23:16) */ + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (scsiCmnd->cdb[2] & 0xF)); + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[8]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + satIOContext->ATACmd = SAT_READ_VERIFY_SECTORS; + + } + + satIOContext->currentLBA = lba; + satIOContext->OrgTL = tl; + + /* + computing number of loop and remainder for tl + 0xFF in case not ext + 0xFFFF in case EXT + */ + if (fis->h.command == SAT_READ_VERIFY_SECTORS) + { + LoopNum = satComputeLoopNum(tl, 0xFF); + } + else if (fis->h.command == SAT_READ_VERIFY_SECTORS_EXT) + { + /* SAT_READ_SECTORS_EXT, SAT_READ_DMA_EXT */ + LoopNum = satComputeLoopNum(tl, 0xFFFF); + } + else + { + TI_DBG1(("satChainedWriteNVerify_Start_Verify: error case 1!!!\n")); + LoopNum = 1; + } + + satIOContext->LoopNum = LoopNum; + + if (LoopNum == 1) + { + TI_DBG5(("satChainedWriteNVerify_Start_Verify: NON CHAINED data\n")); + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satNonChainedWriteNVerifyCB; + } + else + { + TI_DBG1(("satChainedWriteNVerify_Start_Verify: CHAINED data\n")); + /* re-setting tl */ + if (fis->h.command == SAT_READ_VERIFY_SECTORS) + { + fis->d.sectorCount = 0xFF; + } + else if (fis->h.command == SAT_READ_VERIFY_SECTORS_EXT) + { + fis->d.sectorCount = 0xFF; + fis->d.sectorCountExp = 0xFF; + } + else + { + TI_DBG1(("satChainedWriteNVerify_Start_Verify: error case 2!!!\n")); + } + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satChainedWriteNVerifyCB; + } + + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + return (status); +} + +GLOBAL bit32 satChainedWriteNVerify_Verify( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + bit32 status; + satIOContext_t *satOrgIOContext = agNULL; + agsaFisRegHostToDevice_t *fis; + bit32 agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + bit32 lba = 0; + bit32 DenomTL = 0xFF; + bit32 Remainder = 0; + bit8 LBA[4]; /* 0 MSB, 3 LSB */ + + TI_DBG2(("satChainedWriteNVerify_Verify: start\n")); + + fis = satIOContext->pFis; + satOrgIOContext = satIOContext->satOrgIOContext; + + osti_memset(LBA,0, sizeof(LBA)); + + switch (satOrgIOContext->ATACmd) + { + case SAT_READ_VERIFY_SECTORS: + DenomTL = 0xFF; + break; + case SAT_READ_VERIFY_SECTORS_EXT: + DenomTL = 0xFFFF; + break; + default: + TI_DBG1(("satChainedWriteNVerify_Verify: error incorrect ata command 0x%x\n", satIOContext->ATACmd)); + return tiError; + break; + } + + Remainder = satOrgIOContext->OrgTL % DenomTL; + satOrgIOContext->currentLBA = satOrgIOContext->currentLBA + DenomTL; + lba = satOrgIOContext->currentLBA; + + LBA[0] = (bit8)((lba & 0xF000) >> (8 * 3)); /* MSB */ + LBA[1] = (bit8)((lba & 0xF00) >> (8 * 2)); + LBA[2] = (bit8)((lba & 0xF0) >> 8); + LBA[3] = (bit8)(lba & 0xF); /* LSB */ + + switch (satOrgIOContext->ATACmd) + { + case SAT_READ_VERIFY_SECTORS: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS; /* 0x40 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (LBA[0] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->d.sectorCount = (bit8)Remainder; /* FIS sector count (7:0) */ + } + else + { + fis->d.sectorCount = 0xFF; /* FIS sector count (7:0) */ + } + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + break; + case SAT_READ_VERIFY_SECTORS_EXT: + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS_EXT; /* 0x42 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[3]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[2]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[1]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = LBA[0]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + if (satOrgIOContext->LoopNum == 1) + { + /* last loop */ + fis->d.sectorCount = (bit8)(Remainder & 0xFF); /* FIS sector count (7:0) */ + fis->d.sectorCountExp = (bit8)((Remainder & 0xFF00) >> 8); /* FIS sector count (15:8) */ + } + else + { + fis->d.sectorCount = 0xFF; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0xFF; /* FIS sector count (15:8) */ + } + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + break; + + default: + TI_DBG1(("satChainedWriteNVerify_Verify: error incorrect ata command 0x%x\n", satIOContext->ATACmd)); + return tiError; + break; + } + + /* Initialize CB for SATA completion. + */ + /* chained data */ + satIOContext->satCompleteCB = &satChainedWriteNVerifyCB; + + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + TI_DBG5(("satChainedWriteNVerify_Verify: return\n")); + return (status); + +} + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satWriteAndVerify16. + * + * SAT implementation for SCSI satWriteAndVerify16. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satWriteAndVerify16( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + /* + combination of write16 and verify16 + since write16 has 8 bytes LBA -> problem ATA LBA(upto 6 bytes), no support + */ + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satDeviceData_t *pSatDevData; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 lba = 0; + bit32 tl = 0; + bit32 LoopNum = 1; + bit8 LBA[8]; + bit8 TL[8]; + bit32 rangeChk = agFALSE; /* lba and tl range check */ + bit32 limitChk = agFALSE; /* lba and tl range check */ + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &tiScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + TI_DBG5(("satWriteAndVerify16:start\n")); + + /* checking BYTCHK bit */ + if (scsiCmnd->cdb[1] & SCSI_WRITE_N_VERIFY_BYTCHK_MASK) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satWriteAndVerify16: BYTCHK bit checking \n")); + return tiSuccess; + } + + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[15] & SCSI_NACA_MASK) || (scsiCmnd->cdb[15] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG2(("satWriteAndVerify16: return control\n")); + return tiSuccess; + } + + osti_memset(LBA, 0, sizeof(LBA)); + osti_memset(TL, 0, sizeof(TL)); + + + /* do not use memcpy due to indexing in LBA and TL */ + LBA[0] = scsiCmnd->cdb[2]; /* MSB */ + LBA[1] = scsiCmnd->cdb[3]; + LBA[2] = scsiCmnd->cdb[4]; + LBA[3] = scsiCmnd->cdb[5]; + LBA[4] = scsiCmnd->cdb[6]; + LBA[5] = scsiCmnd->cdb[7]; + LBA[6] = scsiCmnd->cdb[8]; + LBA[7] = scsiCmnd->cdb[9]; /* LSB */ + + TL[0] = 0; + TL[1] = 0; + TL[2] = 0; + TL[3] = 0; + TL[4] = scsiCmnd->cdb[10]; /* MSB */ + TL[5] = scsiCmnd->cdb[11]; + TL[6] = scsiCmnd->cdb[12]; + TL[7] = scsiCmnd->cdb[13]; /* LSB */ + + rangeChk = satAddNComparebit64(LBA, TL); + + limitChk = satCompareLBALimitbit(LBA); + + lba = satComputeCDB16LBA(satIOContext); + tl = satComputeCDB16TL(satIOContext); + + + /* Table 34, 9.1, p 46 */ + /* + note: As of 2/10/2006, no support for DMA QUEUED + */ + + /* + Table 34, 9.1, p 46, b + When no 48-bit addressing support or NCQ, if LBA is beyond (2^28 - 1), + return check condition + */ + if (pSatDevData->satNCQ != agTRUE && + pSatDevData->sat48BitSupport != agTRUE + ) + { + if (limitChk) + { + TI_DBG1(("satWriteAndVerify16: return LBA out of range, not EXT\n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + return tiSuccess; + } + if (rangeChk) // if (lba + tl > SAT_TR_LBA_LIMIT) + { + TI_DBG1(("satWriteAndVerify16: return LBA+TL out of range, not EXT\n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + return tiSuccess; + } + } + + + /* case 1 and 2 */ + if (!rangeChk) // if (lba + tl <= SAT_TR_LBA_LIMIT) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 2 */ + /* WRITE DMA*/ + /* In case that we can't fit the transfer length, we loop */ + TI_DBG5(("satWriteAndVerify16: case 2\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_DMA; /* 0xCA */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[9]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[8]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[7]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (scsiCmnd->cdb[6] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[13]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_DMA; + } + else + { + /* case 1 */ + /* WRITE MULTIPLE or WRITE SECTOR(S) */ + /* WRITE SECTORS for easier implemetation */ + /* In case that we can't fit the transfer length, we loop */ + TI_DBG5(("satWriteAndVerify16: case 1\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_SECTORS; /* 0x30 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[9]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[8]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[7]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (scsiCmnd->cdb[6] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = scsiCmnd->cdb[13]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + satIOContext->ATACmd = SAT_WRITE_SECTORS; + } + } + + /* case 3 and 4 */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 3 */ + /* WRITE DMA EXT or WRITE DMA FUA EXT */ + TI_DBG5(("satWriteAndVerify16: case 3\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + /* SAT_WRITE_DMA_FUA_EXT is optional and we don't support it */ + fis->h.command = SAT_WRITE_DMA_EXT; /* 0x35 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[9]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[8]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[7]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[6]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = scsiCmnd->cdb[5]; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = scsiCmnd->cdb[4]; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[13]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[12]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_DMA_EXT; + } + else + { + /* case 4 */ + /* WRITE MULTIPLE EXT or WRITE MULTIPLE FUA EXT or WRITE SECTOR(S) EXT */ + /* WRITE SECTORS EXT for easier implemetation */ + TI_DBG5(("satWriteAndVerify16: case 4\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_SECTORS_EXT; /* 0x34 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = scsiCmnd->cdb[9]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[8]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[7]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = scsiCmnd->cdb[6]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = scsiCmnd->cdb[5]; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = scsiCmnd->cdb[4]; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = scsiCmnd->cdb[13]; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = scsiCmnd->cdb[12]; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + satIOContext->ATACmd = SAT_WRITE_SECTORS_EXT; + } + } + + /* case 5 */ + if (pSatDevData->satNCQ == agTRUE) + { + /* WRITE FPDMA QUEUED */ + if (pSatDevData->sat48BitSupport != agTRUE) + { + TI_DBG5(("satWriteAndVerify16: case 5 !!! error NCQ but 28 bit address support \n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + TI_DBG6(("satWriteAndVerify16: case 5\n")); + + /* Support 48-bit FPDMA addressing, use WRITE FPDMA QUEUE command */ + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_FPDMA_QUEUED; /* 0x61 */ + fis->h.features = scsiCmnd->cdb[13]; /* FIS sector count (7:0) */ + fis->d.lbaLow = scsiCmnd->cdb[9]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = scsiCmnd->cdb[8]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = scsiCmnd->cdb[7]; /* FIS LBA (23:16) */ + + /* Check FUA bit */ + if (scsiCmnd->cdb[1] & SCSI_WRITE16_FUA_MASK) + fis->d.device = 0xC0; /* FIS FUA set */ + else + fis->d.device = 0x40; /* FIS FUA clear */ + + fis->d.lbaLowExp = scsiCmnd->cdb[6]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = scsiCmnd->cdb[5]; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = scsiCmnd->cdb[4]; /* FIS LBA (47:40) */ + fis->d.featuresExp = scsiCmnd->cdb[12]; /* FIS sector count (15:8) */ + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_FPDMA_QUEUED; + } + + satIOContext->currentLBA = lba; + satIOContext->OrgTL = tl; + + /* + computing number of loop and remainder for tl + 0xFF in case not ext + 0xFFFF in case EXT + */ + if (fis->h.command == SAT_WRITE_SECTORS || fis->h.command == SAT_WRITE_DMA) + { + LoopNum = satComputeLoopNum(tl, 0xFF); + } + else if (fis->h.command == SAT_WRITE_SECTORS_EXT || + fis->h.command == SAT_WRITE_DMA_EXT || + fis->h.command == SAT_WRITE_DMA_FUA_EXT + ) + { + /* SAT_READ_SECTORS_EXT, SAT_READ_DMA_EXT */ + LoopNum = satComputeLoopNum(tl, 0xFFFF); + } + else + { + /* SAT_WRITE_FPDMA_QUEUEDK */ + LoopNum = satComputeLoopNum(tl, 0xFFFF); + } + + satIOContext->LoopNum = LoopNum; + + + if (LoopNum == 1) + { + TI_DBG5(("satWriteAndVerify16: NON CHAINED data\n")); + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satNonChainedWriteNVerifyCB; + } + else + { + TI_DBG1(("satWriteAndVerify16: CHAINED data\n")); + /* re-setting tl */ + if (fis->h.command == SAT_WRITE_SECTORS || fis->h.command == SAT_WRITE_DMA) + { + fis->d.sectorCount = 0xFF; + } + else if (fis->h.command == SAT_WRITE_SECTORS_EXT || + fis->h.command == SAT_WRITE_DMA_EXT || + fis->h.command == SAT_WRITE_DMA_FUA_EXT + ) + { + fis->d.sectorCount = 0xFF; + fis->d.sectorCountExp = 0xFF; + } + else + { + /* SAT_WRITE_FPDMA_QUEUED */ + fis->h.features = 0xFF; + fis->d.featuresExp = 0xFF; + } + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satChainedWriteNVerifyCB; + } + + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + return (status); +} + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satReadMediaSerialNumber. + * + * SAT implementation for SCSI Read Media Serial Number. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satReadMediaSerialNumber( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + bit32 status; + bit32 agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + satDeviceData_t *pSatDevData; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + agsaSATAIdentifyData_t *pSATAIdData; + bit8 *pSerialNumber; + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &tiScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + pSATAIdData = &(pSatDevData->satIdentifyData); + pSerialNumber = (bit8 *) tiScsiRequest->sglVirtualAddr; + + + TI_DBG1(("satReadMediaSerialNumber: start\n")); + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[11] & SCSI_NACA_MASK) || (scsiCmnd->cdb[11] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satReadMediaSerialNumber: return control\n")); + return tiSuccess; + } + + if (tiScsiRequest->scsiCmnd.expDataLength == 4) + { + if (pSATAIdData->commandSetFeatureDefault & 0x4) + { + TI_DBG1(("satReadMediaSerialNumber: Media serial number returning only length\n")); + /* SPC-3 6.16 p192; filling in length */ + pSerialNumber[0] = 0; + pSerialNumber[1] = 0; + pSerialNumber[2] = 0; + pSerialNumber[3] = 0x3C; + } + else + { + /* 1 sector - 4 = 512 - 4 to avoid underflow; 0x1fc*/ + pSerialNumber[0] = 0; + pSerialNumber[1] = 0; + pSerialNumber[2] = 0x1; + pSerialNumber[3] = 0xfc; + } + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + + return tiSuccess; + } + + if ( pSatDevData->IDDeviceValid == agTRUE) + { + if (pSATAIdData->commandSetFeatureDefault & 0x4) + { + /* word87 bit2 Media serial number is valid */ + /* read word 176 to 205; length is 2*30 = 60 = 0x3C*/ + tdhexdump("ID satReadMediaSerialNumber", (bit8*)pSATAIdData->currentMediaSerialNumber, 2*30); + /* SPC-3 6.16 p192; filling in length */ + pSerialNumber[0] = 0; + pSerialNumber[1] = 0; + pSerialNumber[2] = 0; + pSerialNumber[3] = 0x3C; + osti_memcpy(&pSerialNumber[4], (void *)pSATAIdData->currentMediaSerialNumber, 60); + tdhexdump("satReadMediaSerialNumber", (bit8*)pSerialNumber, 2*30 + 4); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + return tiSuccess; + + + } + else + { + /* word87 bit2 Media serial number is NOT valid */ + TI_DBG1(("satReadMediaSerialNumber: Media serial number is NOT valid \n")); + + if (pSatDevData->sat48BitSupport == agTRUE) + { + /* READ VERIFY SECTORS EXT */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_SECTORS_EXT; /* 0x24 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = 0; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = 0; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = 0; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + } + else + { + /* READ VERIFY SECTORS */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_SECTORS; /* 0x20 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA (27:24) and FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + } + satIOContext->satCompleteCB = &satReadMediaSerialNumberCB; + satIOContext->reqType = agRequestType; /* Save it */ + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + return status; + } + } + else + { + /* temporary failure */ + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + satIOContext->interruptContext); + + return tiSuccess; + + } + +} + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satReadBuffer. + * + * SAT implementation for SCSI Read Buffer. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +/* SAT-2, Revision 00*/ +GLOBAL bit32 satReadBuffer( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + bit32 status = tiSuccess; + bit32 agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit32 bufferOffset; + bit32 tl; + bit8 mode; + bit8 bufferID; + bit8 *pBuff; + + pSense = satIOContext->pSense; + scsiCmnd = &tiScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + pBuff = (bit8 *) tiScsiRequest->sglVirtualAddr; + + TI_DBG2(("satReadBuffer: start\n")); + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[9] & SCSI_NACA_MASK) || (scsiCmnd->cdb[9] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + TI_DBG1(("satReadBuffer: return control\n")); + return tiSuccess; + } + + bufferOffset = (scsiCmnd->cdb[3] << (8*2)) + (scsiCmnd->cdb[4] << 8) + scsiCmnd->cdb[5]; + tl = (scsiCmnd->cdb[6] << (8*2)) + (scsiCmnd->cdb[7] << 8) + scsiCmnd->cdb[8]; + + mode = (bit8)(scsiCmnd->cdb[1] & SCSI_READ_BUFFER_MODE_MASK); + bufferID = scsiCmnd->cdb[2]; + + if (mode == READ_BUFFER_DATA_MODE) /* 2 */ + { + if (bufferID == 0 && bufferOffset == 0 && tl == 512) + { + /* send ATA READ BUFFER */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_BUFFER; /* 0xE4 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA (27:24) and FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + satIOContext->satCompleteCB = &satReadBufferCB; + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + return status; + } + if (bufferID == 0 && bufferOffset == 0 && tl != 512) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + TI_DBG1(("satReadBuffer: allocation length is not 512; it is %d\n", tl)); + return tiSuccess; + } + if (bufferID == 0 && bufferOffset != 0) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + TI_DBG1(("satReadBuffer: buffer offset is not 0; it is %d\n", bufferOffset)); + return tiSuccess; + } + /* all other cases unsupported */ + TI_DBG1(("satReadBuffer: unsupported case 1\n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_COMMAND, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + else if (mode == READ_BUFFER_DESCRIPTOR_MODE) /* 3 */ + { + if (tl < READ_BUFFER_DESCRIPTOR_MODE_DATA_LEN) /* 4 */ + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + TI_DBG1(("satReadBuffer: tl < 4; tl is %d\n", tl)); + return tiSuccess; + } + if (bufferID == 0) + { + /* SPC-4, 6.15.5, p189; SAT-2 Rev00, 8.7.2.3, p41*/ + pBuff[0] = 0xFF; + pBuff[1] = 0x00; + pBuff[2] = 0x02; + pBuff[3] = 0x00; + if (READ_BUFFER_DESCRIPTOR_MODE_DATA_LEN < tl) + { + /* underrrun */ + TI_DBG1(("satReadBuffer: underrun tl %d data %d\n", tl, READ_BUFFER_DESCRIPTOR_MODE_DATA_LEN)); + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOUnderRun, + tl - READ_BUFFER_DESCRIPTOR_MODE_DATA_LEN, + agNULL, + satIOContext->interruptContext ); + return tiSuccess; + } + else + { + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + return tiSuccess; + } + } + else + { + /* We don't support other than bufferID 0 */ + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_COMMAND, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + } + else + { + /* We don't support any other mode */ + TI_DBG1(("satReadBuffer: unsupported mode %d\n", mode)); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_COMMAND, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } +} + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satWriteBuffer. + * + * SAT implementation for SCSI Write Buffer. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +/* SAT-2, Revision 00*/ +GLOBAL bit32 satWriteBuffer( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ +#ifdef NOT_YET + bit32 agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; +#endif + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + bit32 bufferOffset; + bit32 parmLen; + bit8 mode; + bit8 bufferID; + bit8 *pBuff; + + pSense = satIOContext->pSense; + scsiCmnd = &tiScsiRequest->scsiCmnd; + pBuff = (bit8 *) tiScsiRequest->sglVirtualAddr; + + TI_DBG2(("satWriteBuffer: start\n")); + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[9] & SCSI_NACA_MASK) || (scsiCmnd->cdb[9] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satWriteBuffer: return control\n")); + return tiSuccess; + } + + bufferOffset = (scsiCmnd->cdb[3] << (8*2)) + (scsiCmnd->cdb[4] << 8) + scsiCmnd->cdb[5]; + parmLen = (scsiCmnd->cdb[6] << (8*2)) + (scsiCmnd->cdb[7] << 8) + scsiCmnd->cdb[8]; + + mode = (bit8)(scsiCmnd->cdb[1] & SCSI_READ_BUFFER_MODE_MASK); + bufferID = scsiCmnd->cdb[2]; + + /* for debugging only */ + tdhexdump("satWriteBuffer pBuff", (bit8 *)pBuff, 24); + + if (mode == WRITE_BUFFER_DATA_MODE) /* 2 */ + { + if (bufferID == 0 && bufferOffset == 0 && parmLen == 512) + { + TI_DBG1(("satWriteBuffer: sending ATA WRITE BUFFER\n")); + /* send ATA WRITE BUFFER */ +#ifdef NOT_YET + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_BUFFER; /* 0xE8 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA (27:24) and FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + + satIOContext->satCompleteCB = &satWriteBufferCB; + + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + return status; +#endif + /* temp */ + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_GOOD, + agNULL, + satIOContext->interruptContext); + return tiSuccess; + } + if ( (bufferID == 0 && bufferOffset != 0) || + (bufferID == 0 && parmLen != 512) + ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satWriteBuffer: wrong buffer offset %d or parameter length parmLen %d\n", bufferOffset, parmLen)); + return tiSuccess; + } + + /* all other cases unsupported */ + TI_DBG1(("satWriteBuffer: unsupported case 1\n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_COMMAND, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + return tiSuccess; + + } + else if (mode == WRITE_BUFFER_DL_MICROCODE_SAVE_MODE) /* 5 */ + { + TI_DBG1(("satWriteBuffer: not yet supported mode %d\n", mode)); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_COMMAND, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + return tiSuccess; + } + else + { + /* We don't support any other mode */ + TI_DBG1(("satWriteBuffer: unsupported mode %d\n", mode)); + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_COMMAND, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + return tiSuccess; + } + +} + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satReassignBlocks. + * + * SAT implementation for SCSI Reassign Blocks. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satReassignBlocks( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + /* + assumes all LBA fits in ATA command; no boundary condition is checked here yet + */ + bit32 status; + bit32 agRequestType; + satDeviceData_t *pSatDevData; + scsiRspSense_t *pSense; + tiIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit8 *pParmList; /* Log Page data buffer */ + bit8 LongLBA; + bit8 LongList; + bit32 defectListLen; + bit8 LBA[8]; + bit32 startingIndex; + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &tiScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + pParmList = (bit8 *) tiScsiRequest->sglVirtualAddr; + + TI_DBG5(("satReassignBlocks: start\n")); + + /* checking CONTROL */ + /* NACA == 1 or LINK == 1*/ + if ( (scsiCmnd->cdb[5] & SCSI_NACA_MASK) || (scsiCmnd->cdb[5] & SCSI_LINK_MASK) ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_ILLEGAL_REQUEST, + 0, + SCSI_SNSCODE_INVALID_FIELD_IN_CDB, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + + TI_DBG1(("satReassignBlocks: return control\n")); + return tiSuccess; + } + + osti_memset(satIOContext->LBA, 0, 8); + satIOContext->ParmIndex = 0; + satIOContext->ParmLen = 0; + + LongList = (bit8)(scsiCmnd->cdb[1] & SCSI_REASSIGN_BLOCKS_LONGLIST_MASK); + LongLBA = (bit8)(scsiCmnd->cdb[1] & SCSI_REASSIGN_BLOCKS_LONGLBA_MASK); + osti_memset(LBA, 0, sizeof(LBA)); + + if (LongList == 0) + { + defectListLen = (pParmList[2] << 8) + pParmList[3]; + } + else + { + defectListLen = (pParmList[0] << (8*3)) + (pParmList[1] << (8*2)) + + (pParmList[2] << 8) + pParmList[3]; + } + /* SBC 5.16.2, p61*/ + satIOContext->ParmLen = defectListLen + 4 /* header size */; + + startingIndex = 4; + + if (LongLBA == 0) + { + LBA[4] = pParmList[startingIndex]; /* MSB */ + LBA[5] = pParmList[startingIndex+1]; + LBA[6] = pParmList[startingIndex+2]; + LBA[7] = pParmList[startingIndex+3]; /* LSB */ + startingIndex = startingIndex + 4; + } + else + { + LBA[0] = pParmList[startingIndex]; /* MSB */ + LBA[1] = pParmList[startingIndex+1]; + LBA[2] = pParmList[startingIndex+2]; + LBA[3] = pParmList[startingIndex+3]; + LBA[4] = pParmList[startingIndex+4]; + LBA[5] = pParmList[startingIndex+5]; + LBA[6] = pParmList[startingIndex+6]; + LBA[7] = pParmList[startingIndex+7]; /* LSB */ + startingIndex = startingIndex + 8; + } + + tdhexdump("satReassignBlocks Parameter list", (bit8 *)pParmList, 4 + defectListLen); + + if (pSatDevData->sat48BitSupport == agTRUE) + { + /* sends READ VERIFY SECTOR(S) EXT*/ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS_EXT;/* 0x42 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[7]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[6]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[5]; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = LBA[4]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = LBA[3]; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = LBA[2]; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.device = 0x40; /* 01000000 */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + } + else + { + /* READ VERIFY SECTOR(S)*/ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS;/* 0x40 */ + fis->h.features = 0; /* FIS features NA */ + fis->d.lbaLow = LBA[7]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[6]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[5]; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.device = (bit8)((0x4 << 4) | (LBA[4] & 0xF)); + /* DEV and LBA 27:24 */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + } + + osti_memcpy(satIOContext->LBA, LBA, 8); + satIOContext->ParmIndex = startingIndex; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satReassignBlocksCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + return status; +} + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satReassignBlocks_1. + * + * SAT implementation for SCSI Reassign Blocks. This is helper function for + * satReassignBlocks and satReassignBlocksCB. This sends ATA verify command. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +/* next LBA; sends READ VERIFY SECTOR; update LBA and ParmIdx */ +GLOBAL bit32 satReassignBlocks_1( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext, + satIOContext_t *satOrgIOContext + ) +{ + /* + assumes all LBA fits in ATA command; no boundary condition is checked here yet + tiScsiRequest is OS generated; needs for accessing parameter list + */ + bit32 agRequestType; + satDeviceData_t *pSatDevData; + tiIniScsiCmnd_t *scsiCmnd; + agsaFisRegHostToDevice_t *fis; + bit8 *pParmList; /* Log Page data buffer */ + bit8 LongLBA; + bit8 LBA[8]; + bit32 startingIndex; + + pSatDevData = satIOContext->pSatDevData; + scsiCmnd = &tiScsiRequest->scsiCmnd; + fis = satIOContext->pFis; + pParmList = (bit8 *) tiScsiRequest->sglVirtualAddr; + + TI_DBG5(("satReassignBlocks_1: start\n")); + + LongLBA = (bit8)(scsiCmnd->cdb[1] & SCSI_REASSIGN_BLOCKS_LONGLBA_MASK); + osti_memset(LBA, 0, sizeof(LBA)); + + startingIndex = satOrgIOContext->ParmIndex; + + if (LongLBA == 0) + { + LBA[4] = pParmList[startingIndex]; + LBA[5] = pParmList[startingIndex+1]; + LBA[6] = pParmList[startingIndex+2]; + LBA[7] = pParmList[startingIndex+3]; + startingIndex = startingIndex + 4; + } + else + { + LBA[0] = pParmList[startingIndex]; + LBA[1] = pParmList[startingIndex+1]; + LBA[2] = pParmList[startingIndex+2]; + LBA[3] = pParmList[startingIndex+3]; + LBA[4] = pParmList[startingIndex+4]; + LBA[5] = pParmList[startingIndex+5]; + LBA[6] = pParmList[startingIndex+6]; + LBA[7] = pParmList[startingIndex+7]; + startingIndex = startingIndex + 8; + } + + if (pSatDevData->sat48BitSupport == agTRUE) + { + /* sends READ VERIFY SECTOR(S) EXT*/ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS_EXT;/* 0x42 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[7]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[6]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[5]; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = LBA[4]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = LBA[3]; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = LBA[2]; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.device = 0x40; /* 01000000 */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + } + else + { + /* READ VERIFY SECTOR(S)*/ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_VERIFY_SECTORS;/* 0x40 */ + fis->h.features = 0; /* FIS features NA */ + fis->d.lbaLow = LBA[7]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[6]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[5]; /* FIS LBA (23:16) */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.device = (bit8)((0x4 << 4) | (LBA[4] & 0xF)); + /* DEV and LBA 27:24 */ + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + } + osti_memcpy(satOrgIOContext->LBA, LBA, 8); + satOrgIOContext->ParmIndex = startingIndex; + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satReassignBlocksCB; + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext ); + return tiSuccess; +} + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satReassignBlocks_2. + * + * SAT implementation for SCSI Reassign Blocks. This is helper function for + * satReassignBlocks and satReassignBlocksCB. This sends ATA write command. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * \param LBA: Pointer to the LBA to be processed + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +/* current LBA; sends WRITE */ +GLOBAL bit32 satReassignBlocks_2( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext, + bit8 *LBA + ) +{ + /* + assumes all LBA fits in ATA command; no boundary condition is checked here yet + tiScsiRequest is TD generated for writing + */ + bit32 status; + bit32 agRequestType; + satDeviceData_t *pSatDevData; + scsiRspSense_t *pSense; + agsaFisRegHostToDevice_t *fis; + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; + fis = satIOContext->pFis; + + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 2 */ + /* WRITE DMA*/ + /* can't fit the transfer length */ + TI_DBG5(("satReassignBlocks_2: case 2\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_DMA; /* 0xCA */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[7]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[6]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[5]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (LBA[4] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_DMA; + } + else + { + /* case 1 */ + /* WRITE MULTIPLE or WRITE SECTOR(S) */ + /* WRITE SECTORS for easier implemetation */ + /* can't fit the transfer length */ + TI_DBG5(("satReassignBlocks_2: case 1\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C bit is set */ + fis->h.command = SAT_WRITE_SECTORS; /* 0x30 */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[7]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[6]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[7]; /* FIS LBA (23:16) */ + + /* FIS LBA mode set LBA (27:24) */ + fis->d.device = (bit8)((0x4 << 4) | (LBA[4] & 0xF)); + + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + satIOContext->ATACmd = SAT_WRITE_SECTORS; + } + + /* case 3 and 4 */ + if (pSatDevData->sat48BitSupport == agTRUE) + { + if (pSatDevData->satDMASupport == agTRUE && pSatDevData->satDMAEnabled == agTRUE) + { + /* case 3 */ + /* WRITE DMA EXT or WRITE DMA FUA EXT */ + TI_DBG5(("satReassignBlocks_2: case 3\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + + /* SAT_WRITE_DMA_FUA_EXT is optional and we don't support it */ + fis->h.command = SAT_WRITE_DMA_EXT; /* 0x35 */ + satIOContext->ATACmd = SAT_WRITE_DMA_EXT; + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[7]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[6]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[5]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = LBA[4]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = LBA[3]; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = LBA[2]; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_DMA_WRITE; + } + else + { + /* case 4 */ + /* WRITE MULTIPLE EXT or WRITE MULTIPLE FUA EXT or WRITE SECTOR(S) EXT */ + /* WRITE SECTORS EXT for easier implemetation */ + TI_DBG5(("satReassignBlocks_2: case 4\n")); + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_SECTORS_EXT; /* 0x34 */ + + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = LBA[7]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[6]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[5]; /* FIS LBA (23:16) */ + fis->d.device = 0x40; /* FIS LBA mode set */ + fis->d.lbaLowExp = LBA[4]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = LBA[3]; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = LBA[2]; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 1; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; /* FIS sector count (15:8) */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_WRITE; + satIOContext->ATACmd = SAT_WRITE_SECTORS_EXT; + } + } + /* case 5 */ + if (pSatDevData->satNCQ == agTRUE) + { + /* WRITE FPDMA QUEUED */ + if (pSatDevData->sat48BitSupport != agTRUE) + { + TI_DBG5(("satReassignBlocks_2: case 5 !!! error NCQ but 28 bit address support \n")); + satSetSensePayload( pSense, + SCSI_SNSKEY_HARDWARE_ERROR, + 0, + SCSI_SNSCODE_WRITE_ERROR_AUTO_REALLOCATION_FAILED, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + satIOContext->interruptContext ); + return tiSuccess; + } + TI_DBG6(("satWrite10: case 5\n")); + + /* Support 48-bit FPDMA addressing, use WRITE FPDMA QUEUE command */ + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_WRITE_FPDMA_QUEUED; /* 0x61 */ + fis->h.features = 1; /* FIS sector count (7:0) */ + fis->d.lbaLow = LBA[7]; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = LBA[6]; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = LBA[5]; /* FIS LBA (23:16) */ + + /* Check FUA bit */ + fis->d.device = 0x40; /* FIS FUA clear */ + + fis->d.lbaLowExp = LBA[4]; /* FIS LBA (31:24) */ + fis->d.lbaMidExp = LBA[3]; /* FIS LBA (39:32) */ + fis->d.lbaHighExp = LBA[2]; /* FIS LBA (47:40) */ + fis->d.featuresExp = 0; /* FIS sector count (15:8) */ + fis->d.sectorCount = 0; /* Tag (7:3) set by LL layer */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_FPDMA_WRITE; + satIOContext->ATACmd = SAT_WRITE_FPDMA_QUEUED; + } + + satIOContext->satCompleteCB = &satReassignBlocksCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + /* not the original, should be the TD generated one */ + tiScsiRequest, + satIOContext); + return (status); +} + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satPrepareNewIO. + * + * This function fills in the fields of internal IO generated by TD layer. + * This is mostly used in the callback functions. + * + * \param satNewIntIo: Pointer to the internal IO structure. + * \param tiOrgIORequest: Pointer to the original tiIOrequest sent by OS layer + * \param satDevData: Pointer to the device data. + * \param scsiCmnd: Pointer to SCSI command. + * \param satOrgIOContext: Pointer to the original SAT IO Context + * + * \return + * - \e Pointer to the new SAT IO Context + */ +/*****************************************************************************/ +GLOBAL satIOContext_t *satPrepareNewIO( + satInternalIo_t *satNewIntIo, + tiIORequest_t *tiOrgIORequest, + satDeviceData_t *satDevData, + tiIniScsiCmnd_t *scsiCmnd, + satIOContext_t *satOrgIOContext + ) +{ + satIOContext_t *satNewIOContext; + tdIORequestBody_t *tdNewIORequestBody; + + TI_DBG2(("satPrepareNewIO: start\n")); + + /* the one to be used; good 8/2/07 */ + satNewIntIo->satOrgTiIORequest = tiOrgIORequest; /* this is already done in + satAllocIntIoResource() */ + + tdNewIORequestBody = (tdIORequestBody_t *)satNewIntIo->satIntRequestBody; + satNewIOContext = &(tdNewIORequestBody->transport.SATA.satIOContext); + + satNewIOContext->pSatDevData = satDevData; + satNewIOContext->pFis = &(tdNewIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev); + satNewIOContext->pScsiCmnd = &(satNewIntIo->satIntTiScsiXchg.scsiCmnd); + if (scsiCmnd != agNULL) + { + /* saves only CBD; not scsi command for LBA and number of blocks */ + osti_memcpy(satNewIOContext->pScsiCmnd->cdb, scsiCmnd->cdb, 16); + } + satNewIOContext->pSense = &(tdNewIORequestBody->transport.SATA.sensePayload); + satNewIOContext->pTiSenseData = &(tdNewIORequestBody->transport.SATA.tiSenseData); + satNewIOContext->pTiSenseData->senseData = satNewIOContext->pSense; + satNewIOContext->tiRequestBody = satNewIntIo->satIntRequestBody; + satNewIOContext->interruptContext = satNewIOContext->interruptContext; + satNewIOContext->satIntIoContext = satNewIntIo; + satNewIOContext->ptiDeviceHandle = satOrgIOContext->ptiDeviceHandle; + satNewIOContext->satOrgIOContext = satOrgIOContext; + /* saves tiScsiXchg; only for writesame10() */ + satNewIOContext->tiScsiXchg = satOrgIOContext->tiScsiXchg; + + return satNewIOContext; +} +/***************************************************************************** + *! \brief satIOAbort + * + * This routine is called to initiate a I/O abort to SATL. + * This routine is independent of HW/LL API. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param taskTag: Pointer to TISA I/O request context/tag to be aborted. + * + * \return: + * + * \e tiSuccess: I/O request successfully initiated. + * \e tiBusy: No resources available, try again later. + * \e tiError: Other errors that prevent the I/O request to be started. + * + * + *****************************************************************************/ +GLOBAL bit32 satIOAbort( + tiRoot_t *tiRoot, + tiIORequest_t *taskTag ) +{ + + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + agsaRoot_t *agRoot; + tdIORequestBody_t *tdIORequestBody; + tdIORequestBody_t *tdIONewRequestBody; + agsaIORequest_t *agIORequest; + bit32 status; + agsaIORequest_t *agAbortIORequest; + tdIORequestBody_t *tdAbortIORequestBody; + bit32 PhysUpper32; + bit32 PhysLower32; + bit32 memAllocStatus; + void *osMemHandle; + satIOContext_t *satIOContext; + satInternalIo_t *satIntIo; + + TI_DBG2(("satIOAbort: start\n")); + + agRoot = &(tdsaAllShared->agRootNonInt); + tdIORequestBody = (tdIORequestBody_t *)taskTag->tdData; + + /* needs to distinguish internally generated or externally generated */ + satIOContext = &(tdIORequestBody->transport.SATA.satIOContext); + satIntIo = satIOContext->satIntIoContext; + if (satIntIo == agNULL) + { + TI_DBG1(("satIOAbort: External, OS generated\n")); + agIORequest = &(tdIORequestBody->agIORequest); + } + else + { + TI_DBG1(("satIOAbort: Internal, TD generated\n")); + tdIONewRequestBody = (tdIORequestBody_t *)satIntIo->satIntRequestBody; + agIORequest = &(tdIONewRequestBody->agIORequest); + } + + /* allocating agIORequest for abort itself */ + memAllocStatus = ostiAllocMemory( + tiRoot, + &osMemHandle, + (void **)&tdAbortIORequestBody, + &PhysUpper32, + &PhysLower32, + 8, + sizeof(tdIORequestBody_t), + agTRUE + ); + if (memAllocStatus != tiSuccess) + { + /* let os process IO */ + TI_DBG1(("satIOAbort: ostiAllocMemory failed...\n")); + return tiError; + } + + if (tdAbortIORequestBody == agNULL) + { + /* let os process IO */ + TI_DBG1(("satIOAbort: ostiAllocMemory returned NULL tdAbortIORequestBody\n")); + return tiError; + } + + /* setup task management structure */ + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle = osMemHandle; + tdAbortIORequestBody->tiDevHandle = tdIORequestBody->tiDevHandle; + + /* initialize agIORequest */ + agAbortIORequest = &(tdAbortIORequestBody->agIORequest); + agAbortIORequest->osData = (void *) tdAbortIORequestBody; + agAbortIORequest->sdkData = agNULL; /* LL takes care of this */ + + /* remember IO to be aborted */ + tdAbortIORequestBody->tiIOToBeAbortedRequest = taskTag; + + status = saSATAAbort( agRoot, agAbortIORequest, 0, agNULL, 0, agIORequest, agNULL ); + + TI_DBG5(("satIOAbort: return status=0x%x\n", status)); + + if (status == AGSA_RC_SUCCESS) + return tiSuccess; + else + return tiError; + +} + + +/***************************************************************************** + *! \brief satTM + * + * This routine is called to initiate a TM request to SATL. + * This routine is independent of HW/LL API. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param task: SAM-3 task management request. + * \param lun: Pointer to LUN. + * \param taskTag: Pointer to the associated task where the TM + * command is to be applied. + * \param currentTaskTag: Pointer to tag/context for this TM request. + * + * \return: + * + * \e tiSuccess: I/O request successfully initiated. + * \e tiBusy: No resources available, try again later. + * \e tiIONoDevice: Invalid device handle. + * \e tiError: Other errors that prevent the I/O request to be started. + * + * + *****************************************************************************/ + /* save task in satIOContext */ +osGLOBAL bit32 satTM( + tiRoot_t *tiRoot, + tiDeviceHandle_t *tiDeviceHandle, + bit32 task, + tiLUN_t *lun, + tiIORequest_t *taskTag, + tiIORequest_t *currentTaskTag, + tdIORequestBody_t *tiRequestBody, + bit32 NotifyOS + ) +{ + tdIORequestBody_t *tdIORequestBody = agNULL; + satIOContext_t *satIOContext = agNULL; + tdsaDeviceData_t *oneDeviceData = agNULL; + bit32 status; + + TI_DBG3(("satTM: tiDeviceHandle=%p task=0x%x\n", tiDeviceHandle, task )); + + /* set satIOContext fields and etc */ + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + + + tdIORequestBody = (tdIORequestBody_t *)tiRequestBody; + satIOContext = &(tdIORequestBody->transport.SATA.satIOContext); + + satIOContext->pSatDevData = &oneDeviceData->satDevData; + satIOContext->pFis = + &tdIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev; + + + satIOContext->tiRequestBody = tiRequestBody; + satIOContext->ptiDeviceHandle = tiDeviceHandle; + satIOContext->satIntIoContext = agNULL; + satIOContext->satOrgIOContext = agNULL; + + /* followings are used only for internal IO */ + satIOContext->currentLBA = 0; + satIOContext->OrgTL = 0; + + /* saving task in satIOContext */ + satIOContext->TMF = task; + + satIOContext->satToBeAbortedIOContext = agNULL; + + if (NotifyOS == agTRUE) + { + satIOContext->NotifyOS = agTRUE; + } + else + { + satIOContext->NotifyOS = agFALSE; + } + /* + * Our SAT supports RESET LUN and partially support ABORT TASK (only if there + * is no more than one I/O pending on the drive. + */ + + if (task == AG_LOGICAL_UNIT_RESET) + { + status = satTmResetLUN( tiRoot, + currentTaskTag, + tiDeviceHandle, + agNULL, + satIOContext, + lun); + return status; + } +#ifdef TO_BE_REMOVED + else if (task == AG_TARGET_WARM_RESET) + { + status = satTmWarmReset( tiRoot, + currentTaskTag, + tiDeviceHandle, + agNULL, + satIOContext); + + return status; + } +#endif + else if (task == AG_ABORT_TASK) + { + status = satTmAbortTask( tiRoot, + currentTaskTag, + tiDeviceHandle, + agNULL, + satIOContext, + taskTag); + + return status; + } + else if (task == TD_INTERNAL_TM_RESET) + { + status = satTDInternalTmReset( tiRoot, + currentTaskTag, + tiDeviceHandle, + agNULL, + satIOContext); + return status; + } + else + { + TI_DBG1(("satTM: tiDeviceHandle=%p UNSUPPORTED TM task=0x%x\n", + tiDeviceHandle, task )); + + /* clean up TD layer's IORequestBody */ + ostiFreeMemory( + tiRoot, + tiRequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + return tiError; + } + +} + + +/***************************************************************************** + *! \brief satTmResetLUN + * + * This routine is called to initiate a TM RESET LUN request to SATL. + * This routine is independent of HW/LL API. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param lun: Pointer to LUN. + * \param currentTaskTag: Pointer to tag/context for this TM request. + * + * \return: + * + * \e tiSuccess: I/O request successfully initiated. + * \e tiBusy: No resources available, try again later. + * \e tiIONoDevice: Invalid device handle. + * \e tiError: Other errors that prevent the I/O request to be started. + * + * + *****************************************************************************/ +osGLOBAL bit32 satTmResetLUN( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, /* current task tag */ + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext, + tiLUN_t *lun) +{ + + tdsaDeviceData_t *tdsaDeviceData; + satDeviceData_t *satDevData; + + tdsaDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + satDevData = &tdsaDeviceData->satDevData; + + TI_DBG1(("satTmResetLUN: tiDeviceHandle=%p.\n", tiDeviceHandle )); + + /* + * Only support LUN 0 + */ + if ( (lun->lun[0] | lun->lun[1] | lun->lun[2] | lun->lun[3] | + lun->lun[4] | lun->lun[5] | lun->lun[6] | lun->lun[7] ) != 0 ) + { + TI_DBG1(("satTmResetLUN: *** REJECT *** LUN not zero, tiDeviceHandle=%p\n", + tiDeviceHandle)); + return tiError; + } + + /* + * Check if there is other TM request pending + */ + if (satDevData->satTmTaskTag != agNULL) + { + TI_DBG1(("satTmResetLUN: *** REJECT *** other TM pending, tiDeviceHandle=%p\n", + tiDeviceHandle)); + return tiError; + } + + /* + * Save tiIORequest, will be returned at device reset completion to return + * the TM completion. + */ + satDevData->satTmTaskTag = tiIORequest; + + /* + * Set flag to indicate device in recovery mode. + */ + satDevData->satDriveState = SAT_DEV_STATE_IN_RECOVERY; + + /* + * Issue SATA device reset. Set flag to indicate NOT to automatically abort + * at the completion of SATA device reset. + */ + satDevData->satAbortAfterReset = agFALSE; + + /* SAT rev8 6.3.6 p22 */ + satStartResetDevice( + tiRoot, + tiIORequest, /* currentTaskTag */ + tiDeviceHandle, + tiScsiRequest, + satIOContext + ); + + + return tiSuccess; + +} + +/***************************************************************************** + *! \brief satTmWarmReset + * + * This routine is called to initiate a TM warm RESET request to SATL. + * This routine is independent of HW/LL API. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param currentTaskTag: Pointer to tag/context for this TM request. + * + * \return: + * + * \e tiSuccess: I/O request successfully initiated. + * \e tiBusy: No resources available, try again later. + * \e tiIONoDevice: Invalid device handle. + * \e tiError: Other errors that prevent the I/O request to be started. + * + * + *****************************************************************************/ +osGLOBAL bit32 satTmWarmReset( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, /* current task tag */ + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + + tdsaDeviceData_t *tdsaDeviceData; + satDeviceData_t *satDevData; + + tdsaDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + satDevData = &tdsaDeviceData->satDevData; + + TI_DBG1(("satTmWarmReset: tiDeviceHandle=%p.\n", tiDeviceHandle )); + + /* + * Check if there is other TM request pending + */ + if (satDevData->satTmTaskTag != agNULL) + { + TI_DBG1(("satTmWarmReset: *** REJECT *** other TM pending, tiDeviceHandle=%p\n", + tiDeviceHandle)); + return tiError; + } + + /* + * Save tiIORequest, will be returned at device reset completion to return + * the TM completion. + */ + satDevData->satTmTaskTag = tiIORequest; + + /* + * Set flag to indicate device in recovery mode. + */ + satDevData->satDriveState = SAT_DEV_STATE_IN_RECOVERY; + + /* + * Issue SATA device reset. Set flag to indicate NOT to automatically abort + * at the completion of SATA device reset. + */ + satDevData->satAbortAfterReset = agFALSE; + + /* SAT rev8 6.3.6 p22 */ + satStartResetDevice( + tiRoot, + tiIORequest, /* currentTaskTag */ + tiDeviceHandle, + tiScsiRequest, + satIOContext + ); + + return tiSuccess; + +} + +osGLOBAL bit32 satTDInternalTmReset( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, /* current task tag */ + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + + tdsaDeviceData_t *tdsaDeviceData; + satDeviceData_t *satDevData; + + tdsaDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + satDevData = &tdsaDeviceData->satDevData; + + TI_DBG1(("satTmWarmReset: tiDeviceHandle=%p.\n", tiDeviceHandle )); + + /* + * Check if there is other TM request pending + */ + if (satDevData->satTmTaskTag != agNULL) + { + TI_DBG1(("satTmWarmReset: *** REJECT *** other TM pending, tiDeviceHandle=%p\n", + tiDeviceHandle)); + return tiError; + } + + /* + * Save tiIORequest, will be returned at device reset completion to return + * the TM completion. + */ + satDevData->satTmTaskTag = tiIORequest; + + /* + * Set flag to indicate device in recovery mode. + */ + satDevData->satDriveState = SAT_DEV_STATE_IN_RECOVERY; + + /* + * Issue SATA device reset. Set flag to indicate NOT to automatically abort + * at the completion of SATA device reset. + */ + satDevData->satAbortAfterReset = agFALSE; + + /* SAT rev8 6.3.6 p22 */ + satStartResetDevice( + tiRoot, + tiIORequest, /* currentTaskTag */ + tiDeviceHandle, + tiScsiRequest, + satIOContext + ); + + return tiSuccess; + +} + +/***************************************************************************** + *! \brief satTmAbortTask + * + * This routine is called to initiate a TM ABORT TASK request to SATL. + * This routine is independent of HW/LL API. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param taskTag: Pointer to the associated task where the TM + * command is to be applied. + * \param currentTaskTag: Pointer to tag/context for this TM request. + * + * \return: + * + * \e tiSuccess: I/O request successfully initiated. + * \e tiBusy: No resources available, try again later. + * \e tiIONoDevice: Invalid device handle. + * \e tiError: Other errors that prevent the I/O request to be started. + * + * + *****************************************************************************/ +osGLOBAL bit32 satTmAbortTask( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, /* current task tag */ + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, /* NULL */ + satIOContext_t *satIOContext, + tiIORequest_t *taskTag) +{ + + tdsaDeviceData_t *tdsaDeviceData; + satDeviceData_t *satDevData; + satIOContext_t *satTempIOContext = agNULL; + tdIORequestBody_t *tdIORequestBody; + tdIORequestBody_t *TMtdIORequestBody; + tdList_t *elementHdr; + bit32 found = agFALSE; + tiIORequest_t *tiIOReq; + + tdsaDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + satDevData = &tdsaDeviceData->satDevData; + TMtdIORequestBody = (tdIORequestBody_t *)tiIORequest->tdData; + + TI_DBG1(("satTmAbortTask: tiDeviceHandle=%p taskTag=%p.\n", tiDeviceHandle, taskTag )); + /* + * Check if there is other TM request pending + */ + if (satDevData->satTmTaskTag != agNULL) + { + TI_DBG1(("satTmAbortTask: REJECT other TM pending, tiDeviceHandle=%p\n", + tiDeviceHandle)); + /* clean up TD layer's IORequestBody */ + ostiFreeMemory( + tiRoot, + TMtdIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + return tiError; + } + +#ifdef REMOVED + /* + * Check if there is only one I/O pending. + */ + if (satDevData->satPendingIO > 0) + { + TI_DBG1(("satTmAbortTask: REJECT num pending I/O, tiDeviceHandle=%p, satPendingIO=0x%x\n", + tiDeviceHandle, satDevData->satPendingIO)); + /* clean up TD layer's IORequestBody */ + ostiFreeMemory( + tiRoot, + TMtdIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + + return tiError; + } +#endif + + /* + * Check that the only pending I/O matches taskTag. If not return tiError. + */ + elementHdr = satDevData->satIoLinkList.flink; + + while (elementHdr != &satDevData->satIoLinkList) + { + satTempIOContext = TDLIST_OBJECT_BASE( satIOContext_t, + satIoContextLink, + elementHdr ); + + tdIORequestBody = (tdIORequestBody_t *) satTempIOContext->tiRequestBody; + tiIOReq = tdIORequestBody->tiIORequest; + + elementHdr = elementHdr->flink; /* for the next while loop */ + + /* + * Check if the tag matches + */ + if ( tiIOReq == taskTag) + { + found = agTRUE; + satIOContext->satToBeAbortedIOContext = satTempIOContext; + TI_DBG1(("satTmAbortTask: found matching tag.\n")); + + break; + + } /* if matching tag */ + + } /* while loop */ + + + if (found == agFALSE ) + { + TI_DBG1(("satTmAbortTask: *** REJECT *** no match, tiDeviceHandle=%p\n", + tiDeviceHandle )); + + /* clean up TD layer's IORequestBody */ + ostiFreeMemory( + tiRoot, + TMtdIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + + return tiError; + } + + /* + * Save tiIORequest, will be returned at device reset completion to return + * the TM completion. + */ + satDevData->satTmTaskTag = tiIORequest; + + /* + * Set flag to indicate device in recovery mode. + */ + satDevData->satDriveState = SAT_DEV_STATE_IN_RECOVERY; + + + /* + * Issue SATA device reset or check power mode. Set flag to to automatically abort + * at the completion of SATA device reset. + * SAT r09 p25 + */ + satDevData->satAbortAfterReset = agTRUE; + + if ( (satTempIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_WRITE) || + (satTempIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_READ) + ) + { + TI_DBG1(("satTmAbortTask: calling satStartCheckPowerMode\n")); + /* send check power mode */ + satStartCheckPowerMode( + tiRoot, + tiIORequest, /* currentTaskTag */ + tiDeviceHandle, + tiScsiRequest, + satIOContext + ); + } + else + { + TI_DBG1(("satTmAbortTask: calling satStartResetDevice\n")); + /* send AGSA_SATA_PROTOCOL_SRST_ASSERT */ + satStartResetDevice( + tiRoot, + tiIORequest, /* currentTaskTag */ + tiDeviceHandle, + tiScsiRequest, + satIOContext + ); + } + + + return tiSuccess; +} + +/***************************************************************************** + *! \brief osSatResetCB + * + * This routine is called to notify the completion of SATA device reset + * which was initiated previously through the call to sataLLReset(). + * This routine is independent of HW/LL API. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param resetStatus: Reset status either tiSuccess or tiError. + * \param respFis: Pointer to the Register Device-To-Host FIS + * received from the device. + * + * \return: None + * + *****************************************************************************/ +osGLOBAL void osSatResetCB( + tiRoot_t *tiRoot, + tiDeviceHandle_t *tiDeviceHandle, + bit32 resetStatus, + void *respFis) +{ + + agsaRoot_t *agRoot; + tdsaDeviceData_t *tdsaDeviceData; + satDeviceData_t *satDevData; + satIOContext_t *satIOContext; + tdIORequestBody_t *tdIORequestBodyTmp; + tdList_t *elementHdr; + agsaIORequest_t *agAbortIORequest; + tdIORequestBody_t *tdAbortIORequestBody; + bit32 PhysUpper32; + bit32 PhysLower32; + bit32 memAllocStatus; + void *osMemHandle; + + tdsaDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + agRoot = tdsaDeviceData->agRoot; + satDevData = &tdsaDeviceData->satDevData; + + TI_DBG5(("osSatResetCB: tiDeviceHandle=%p resetStatus=0x%x\n", + tiDeviceHandle, resetStatus )); + + /* We may need to check FIS to check device operating condition */ + + + /* + * Check if need to abort all pending I/Os + */ + if ( satDevData->satAbortAfterReset == agTRUE ) + { + /* + * Issue abort to LL layer to all other pending I/Os for the same SATA drive + */ + elementHdr = satDevData->satIoLinkList.flink; + while (elementHdr != &satDevData->satIoLinkList) + { + satIOContext = TDLIST_OBJECT_BASE( satIOContext_t, + satIoContextLink, + elementHdr ); + + tdIORequestBodyTmp = (tdIORequestBody_t *)satIOContext->tiRequestBody; + + /* + * Issue abort + */ + TI_DBG5(("osSatResetCB: issuing ABORT tiDeviceHandle=%p agIORequest=%p\n", + tiDeviceHandle, &tdIORequestBodyTmp->agIORequest )); + + /* allocating agIORequest for abort itself */ + memAllocStatus = ostiAllocMemory( + tiRoot, + &osMemHandle, + (void **)&tdAbortIORequestBody, + &PhysUpper32, + &PhysLower32, + 8, + sizeof(tdIORequestBody_t), + agTRUE + ); + + if (memAllocStatus != tiSuccess) + { + /* let os process IO */ + TI_DBG1(("osSatResetCB: ostiAllocMemory failed...\n")); + return; + } + + if (tdAbortIORequestBody == agNULL) + { + /* let os process IO */ + TI_DBG1(("osSatResetCB: ostiAllocMemory returned NULL tdAbortIORequestBody\n")); + return; + } + /* setup task management structure */ + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle = osMemHandle; + tdAbortIORequestBody->tiDevHandle = tiDeviceHandle; + + /* initialize agIORequest */ + agAbortIORequest = &(tdAbortIORequestBody->agIORequest); + agAbortIORequest->osData = (void *) tdAbortIORequestBody; + agAbortIORequest->sdkData = agNULL; /* LL takes care of this */ + + saSATAAbort( agRoot, agAbortIORequest, 0, agNULL, 0, &(tdIORequestBodyTmp->agIORequest), agNULL ); + elementHdr = elementHdr->flink; /* for the next while loop */ + + } /* while */ + + /* Reset flag */ + satDevData->satAbortAfterReset = agFALSE; + + } + + + /* + * Check if the device reset if the result of TM request. + */ + if ( satDevData->satTmTaskTag != agNULL ) + { + TI_DBG5(("osSatResetCB: calling TM completion tiDeviceHandle=%p satTmTaskTag=%p\n", + tiDeviceHandle, satDevData->satTmTaskTag )); + + ostiInitiatorEvent( tiRoot, + agNULL, /* portalContext not used */ + tiDeviceHandle, + tiIntrEventTypeTaskManagement, + tiTMOK, + satDevData->satTmTaskTag); + /* + * Reset flag + */ + satDevData->satTmTaskTag = agNULL; + } + +} + + +/***************************************************************************** + *! \brief osSatIOCompleted + * + * This routine is a callback for SATA completion that required FIS status + * translation to SCSI status. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param respFis: Pointer to status FIS to read. + * \param respFisLen: Length of response FIS to read. + * \param satIOContext: Pointer to SAT context. + * \param interruptContext: Interrupt context + * + * \return: None + * + *****************************************************************************/ +osGLOBAL void osSatIOCompleted( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + agsaFisHeader_t *agFirstDword, + bit32 respFisLen, + agsaFrameHandle_t agFrameHandle, + satIOContext_t *satIOContext, + bit32 interruptContext) + +{ + satDeviceData_t *pSatDevData; + scsiRspSense_t *pSense; +#ifdef TD_DEBUG_ENABLE + tiIniScsiCmnd_t *pScsiCmnd; +#endif + agsaFisRegHostToDevice_t *hostToDevFis = agNULL; + bit32 ataStatus = 0; + bit32 ataError; + satInternalIo_t *satIntIo = agNULL; + bit32 status; + tiDeviceHandle_t *tiDeviceHandle; + satIOContext_t *satIOContext2; + tdIORequestBody_t *tdIORequestBody; + agsaFisRegD2HHeader_t *statDevToHostFisHeader = agNULL; + agsaFisSetDevBitsHeader_t *statSetDevBitFisHeader = agNULL; + tiIORequest_t tiIORequestTMP; + + pSense = satIOContext->pSense; + pSatDevData = satIOContext->pSatDevData; +#ifdef TD_DEBUG_ENABLE + pScsiCmnd = satIOContext->pScsiCmnd; +#endif + hostToDevFis = satIOContext->pFis; + + tiDeviceHandle = &((tdsaDeviceData_t *)(pSatDevData->satSaDeviceData))->tiDeviceHandle; + /* + * Find out the type of response FIS: + * Set Device Bit FIS or Reg Device To Host FIS. + */ + + /* First assume it is Reg Device to Host FIS */ + statDevToHostFisHeader = (agsaFisRegD2HHeader_t *)&(agFirstDword->D2H); + ataStatus = statDevToHostFisHeader->status; /* ATA Status register */ + ataError = statDevToHostFisHeader->error; /* ATA Eror register */ + + /* for debugging */ + TI_DBG1(("osSatIOCompleted: H to D command 0x%x\n", hostToDevFis->h.command)); + TI_DBG1(("osSatIOCompleted: D to H fistype 0x%x\n", statDevToHostFisHeader->fisType)); + + + if (statDevToHostFisHeader->fisType == SET_DEV_BITS_FIS) + { + /* It is Set Device Bits FIS */ + statSetDevBitFisHeader = (agsaFisSetDevBitsHeader_t *)&(agFirstDword->D2H); + /* Get ATA Status register */ + ataStatus = (statSetDevBitFisHeader->statusHi_Lo & 0x70); /* bits 4,5,6 */ + ataStatus = ataStatus | (statSetDevBitFisHeader->statusHi_Lo & 0x07); /* bits 0,1,2 */ + + /* ATA Eror register */ + ataError = statSetDevBitFisHeader->error; + + statDevToHostFisHeader = agNULL; + } + + else if (statDevToHostFisHeader->fisType != REG_DEV_TO_HOST_FIS) + { + TI_DBG1(("osSatIOCompleted: *** UNEXPECTED RESP FIS TYPE 0x%x *** tiIORequest=%p\n", + statDevToHostFisHeader->fisType, tiIORequest)); + + satSetSensePayload( pSense, + SCSI_SNSKEY_HARDWARE_ERROR, + 0, + SCSI_SNSCODE_INTERNAL_TARGET_FAILURE, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + interruptContext ); + return; + + } + + if ( ataStatus & DF_ATA_STATUS_MASK ) + { + pSatDevData->satDeviceFaultState = agTRUE; + } + else + { + pSatDevData->satDeviceFaultState = agFALSE; + } + + TI_DBG5(("osSatIOCompleted: tiIORequest=%p CDB=0x%x ATA CMD =0x%x\n", + tiIORequest, pScsiCmnd->cdb[0], hostToDevFis->h.command)); + + /* + * Decide which ATA command is the translation needed + */ + switch(hostToDevFis->h.command) + { + case SAT_READ_FPDMA_QUEUED: + case SAT_WRITE_FPDMA_QUEUED: + + /************************************************************************ + * + * !!!! See Section 13.5.2.4 of SATA 2.5 specs. !!!! + * !!!! If the NCQ error ends up here, it means that the device sent !!!! + * !!!! Set Device Bit FIS (which has SActive register) instead of !!!! + * !!!! Register Device To Host FIS (which does not have SActive !!!! + * !!!! register). The callback ossaSATAEvent() deals with the case !!!! + * !!!! where Register Device To Host FIS was sent by the device. !!!! + * + * For NCQ we need to issue READ LOG EXT command with log page 10h + * to get the error and to allow other I/Os to continue. + * + * Here is the basic flow or sequence of error recovery, note that due + * to the SATA HW assist that we have, this sequence is slighly different + * from the one described in SATA 2.5: + * + * 1. Set SATA device flag to indicate error condition and returning busy + * for all new request. + * return tiSuccess; + + * 2. Because the HW/LL layer received Set Device Bit FIS, it can get the + * tag or I/O context for NCQ request, SATL would translate the ATA error + * to SCSI status and return the original NCQ I/O with the appopriate + * SCSI status. + * + * 3. Prepare READ LOG EXT page 10h command. Set flag to indicate that + * the failed I/O has been returned to the OS Layer. Send command. + * + * 4. When the device receives READ LOG EXT page 10h request all other + * pending I/O are implicitly aborted. No completion (aborted) status + * will be sent to the host for these aborted commands. + * + * 5. SATL receives the completion for READ LOG EXT command in + * satReadLogExtCB(). Steps 6,7,8,9 below are the step 1,2,3,4 in + * satReadLogExtCB(). + * + * 6. Check flag that indicates whether the failed I/O has been returned + * to the OS Layer. If not, search the I/O context in device data + * looking for a matched tag. Then return the completion of the failed + * NCQ command with the appopriate/trasnlated SCSI status. + * + * 7. Issue abort to LL layer to all other pending I/Os for the same SATA + * drive. + * + * 8. Free resource allocated for the internally generated READ LOG EXT. + * + * 9. At the completion of abort, in the context of ossaSATACompleted(), + * return the I/O with error status to the OS-App Specific layer. + * When all I/O aborts are completed, clear SATA device flag to + * indicate ready to process new request. + * + ***********************************************************************/ + + TI_DBG1(("osSatIOCompleted: NCQ ERROR tiIORequest=%p ataStatus=0x%x ataError=0x%x\n", + tiIORequest, ataStatus, ataError )); + + /* Set flag to indicate we are in recovery */ + pSatDevData->satDriveState = SAT_DEV_STATE_IN_RECOVERY; + + /* Return the failed NCQ I/O to OS-Apps Specifiic layer */ + osSatDefaultTranslation( tiRoot, + tiIORequest, + satIOContext, + pSense, + (bit8)ataStatus, + (bit8)ataError, + interruptContext ); + + /* + * Allocate resource for READ LOG EXT page 10h + */ + satIntIo = satAllocIntIoResource( tiRoot, + &(tiIORequestTMP), /* anything but NULL */ + pSatDevData, + sizeof (satReadLogExtPage10h_t), + satIntIo); + + if (satIntIo == agNULL) + { + TI_DBG1(("osSatIOCompleted: can't send RLE due to resource lack\n")); + + /* Abort I/O after completion of device reset */ + pSatDevData->satAbortAfterReset = agTRUE; +#ifdef NOT_YET + /* needs further investigation */ + /* no report to OS layer */ + satSubTM(tiRoot, + tiDeviceHandle, + TD_INTERNAL_TM_RESET, + agNULL, + agNULL, + agNULL, + agFALSE); +#endif + + + TI_DBG1(("osSatIOCompleted: calling saSATADeviceReset 1\n")); + return; + } + + + /* + * Set flag to indicate that the failed I/O has been returned to the + * OS-App specific Layer. + */ + satIntIo->satIntFlag = AG_SAT_INT_IO_FLAG_ORG_IO_COMPLETED; + + /* compare to satPrepareNewIO() */ + /* Send READ LOG EXIT page 10h command */ + + /* + * Need to initialize all the fields within satIOContext except + * reqType and satCompleteCB which will be set depending on cmd. + */ + + tdIORequestBody = (tdIORequestBody_t *)satIntIo->satIntRequestBody; + satIOContext2 = &(tdIORequestBody->transport.SATA.satIOContext); + + satIOContext2->pSatDevData = pSatDevData; + satIOContext2->pFis = &(tdIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev); + satIOContext2->pScsiCmnd = &(satIntIo->satIntTiScsiXchg.scsiCmnd); + satIOContext2->pSense = &(tdIORequestBody->transport.SATA.sensePayload); + satIOContext2->pTiSenseData = &(tdIORequestBody->transport.SATA.tiSenseData); + satIOContext2->pTiSenseData->senseData = satIOContext2->pSense; + + satIOContext2->tiRequestBody = satIntIo->satIntRequestBody; + satIOContext2->interruptContext = interruptContext; + satIOContext2->satIntIoContext = satIntIo; + + satIOContext2->ptiDeviceHandle = tiDeviceHandle; + satIOContext2->satOrgIOContext = agNULL; + satIOContext2->tiScsiXchg = agNULL; + + status = satSendReadLogExt( tiRoot, + &satIntIo->satIntTiIORequest, + tiDeviceHandle, + &satIntIo->satIntTiScsiXchg, + satIOContext2); + + if (status != tiSuccess) + { + TI_DBG1(("osSatIOCompleted: can't send RLE due to LL api failure\n")); + satFreeIntIoResource( tiRoot, + pSatDevData, + satIntIo); + + /* Abort I/O after completion of device reset */ + pSatDevData->satAbortAfterReset = agTRUE; +#ifdef NOT_YET + /* needs further investigation */ + /* no report to OS layer */ + satSubTM(tiRoot, + tiDeviceHandle, + TD_INTERNAL_TM_RESET, + agNULL, + agNULL, + agNULL, + agFALSE); +#endif + + TI_DBG1(("osSatIOCompleted: calling saSATADeviceReset 2\n")); + return; + } + + break; + + case SAT_READ_DMA_EXT: + /* fall through */ + /* Use default status/error translation */ + + case SAT_READ_DMA: + /* fall through */ + /* Use default status/error translation */ + + default: + osSatDefaultTranslation( tiRoot, + tiIORequest, + satIOContext, + pSense, + (bit8)ataStatus, + (bit8)ataError, + interruptContext ); + break; + + } /* end switch */ +} + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI STANDARD INQUIRY. + * + * SAT implementation for SCSI STANDARD INQUIRY. + * + * \param pInquiry: Pointer to Inquiry Data buffer. + * \param pSATAIdData: Pointer to ATA IDENTIFY DEVICE data. + * + * \return None. + */ +/*****************************************************************************/ +GLOBAL void satInquiryStandard( + bit8 *pInquiry, + agsaSATAIdentifyData_t *pSATAIdData, + tiIniScsiCmnd_t *scsiCmnd + ) +{ + tiLUN_t *pLun; + pLun = &scsiCmnd->lun; + + /* + Assumption: Basic Task Mangement is supported + -> BQUE 1 and CMDQUE 0, SPC-4, Table96, p147 + */ + /* + See SPC-4, 6.4.2, p 143 + and SAT revision 8, 8.1.2, p 28 + */ + + TI_DBG5(("satInquiryStandard: start\n")); + + if (pInquiry == agNULL) + { + TI_DBG1(("satInquiryStandard: pInquiry is NULL, wrong\n")); + return; + } + else + { + TI_DBG5(("satInquiryStandard: pInquiry is NOT NULL\n")); + } + /* + * Reject all other LUN other than LUN 0. + */ + if ( ((pLun->lun[0] | pLun->lun[1] | pLun->lun[2] | pLun->lun[3] | + pLun->lun[4] | pLun->lun[5] | pLun->lun[6] | pLun->lun[7] ) != 0) ) + { + /* SAT Spec Table 8, p27, footnote 'a' */ + pInquiry[0] = 0x7F; + + } + else + { + pInquiry[0] = 0x00; + } + + if (pSATAIdData->rm_ataDevice & ATA_REMOVABLE_MEDIA_DEVICE_MASK ) + { + pInquiry[1] = 0x80; + } + else + { + pInquiry[1] = 0x00; + } + pInquiry[2] = 0x05; /* SPC-3 */ + pInquiry[3] = 0x12; /* set HiSup 1; resp data format set to 2 */ + pInquiry[4] = 0x1F; /* 35 - 4 = 31; Additional length */ + pInquiry[5] = 0x00; + /* The following two are for task management. SAT Rev8, p20 */ + if (pSATAIdData->sataCapabilities & 0x100) + { + /* NCQ supported; multiple outstanding SCSI IO are supported */ + pInquiry[6] = 0x00; /* BQUE bit is not set */ + pInquiry[7] = 0x02; /* CMDQUE bit is set */ + } + else + { + pInquiry[6] = 0x80; /* BQUE bit is set */ + pInquiry[7] = 0x00; /* CMDQUE bit is not set */ + } + /* + * Vendor ID. + */ + osti_strncpy((char*)&pInquiry[8], AG_SAT_VENDOR_ID_STRING,8); /* 8 bytes */ + + /* + * Product ID + */ + /* when flipped by LL */ + pInquiry[16] = pSATAIdData->modelNumber[1]; + pInquiry[17] = pSATAIdData->modelNumber[0]; + pInquiry[18] = pSATAIdData->modelNumber[3]; + pInquiry[19] = pSATAIdData->modelNumber[2]; + pInquiry[20] = pSATAIdData->modelNumber[5]; + pInquiry[21] = pSATAIdData->modelNumber[4]; + pInquiry[22] = pSATAIdData->modelNumber[7]; + pInquiry[23] = pSATAIdData->modelNumber[6]; + pInquiry[24] = pSATAIdData->modelNumber[9]; + pInquiry[25] = pSATAIdData->modelNumber[8]; + pInquiry[26] = pSATAIdData->modelNumber[11]; + pInquiry[27] = pSATAIdData->modelNumber[10]; + pInquiry[28] = pSATAIdData->modelNumber[13]; + pInquiry[29] = pSATAIdData->modelNumber[12]; + pInquiry[30] = pSATAIdData->modelNumber[15]; + pInquiry[31] = pSATAIdData->modelNumber[14]; + + /* when flipped */ + /* + * Product Revision level. + */ + + /* + * If the IDENTIFY DEVICE data received in words 25 and 26 from the ATA + * device are ASCII spaces (20h), do this translation. + */ + if ( (pSATAIdData->firmwareVersion[4] == 0x20 ) && + (pSATAIdData->firmwareVersion[5] == 0x00 ) && + (pSATAIdData->firmwareVersion[6] == 0x20 ) && + (pSATAIdData->firmwareVersion[7] == 0x00 ) + ) + { + pInquiry[32] = pSATAIdData->firmwareVersion[1]; + pInquiry[33] = pSATAIdData->firmwareVersion[0]; + pInquiry[34] = pSATAIdData->firmwareVersion[3]; + pInquiry[35] = pSATAIdData->firmwareVersion[2]; + } + else + { + pInquiry[32] = pSATAIdData->firmwareVersion[5]; + pInquiry[33] = pSATAIdData->firmwareVersion[4]; + pInquiry[34] = pSATAIdData->firmwareVersion[7]; + pInquiry[35] = pSATAIdData->firmwareVersion[6]; + } + + +#ifdef REMOVED + /* + * Product ID + */ + /* when flipped by LL */ + pInquiry[16] = pSATAIdData->modelNumber[0]; + pInquiry[17] = pSATAIdData->modelNumber[1]; + pInquiry[18] = pSATAIdData->modelNumber[2]; + pInquiry[19] = pSATAIdData->modelNumber[3]; + pInquiry[20] = pSATAIdData->modelNumber[4]; + pInquiry[21] = pSATAIdData->modelNumber[5]; + pInquiry[22] = pSATAIdData->modelNumber[6]; + pInquiry[23] = pSATAIdData->modelNumber[7]; + pInquiry[24] = pSATAIdData->modelNumber[8]; + pInquiry[25] = pSATAIdData->modelNumber[9]; + pInquiry[26] = pSATAIdData->modelNumber[10]; + pInquiry[27] = pSATAIdData->modelNumber[11]; + pInquiry[28] = pSATAIdData->modelNumber[12]; + pInquiry[29] = pSATAIdData->modelNumber[13]; + pInquiry[30] = pSATAIdData->modelNumber[14]; + pInquiry[31] = pSATAIdData->modelNumber[15]; + + /* when flipped */ + /* + * Product Revision level. + */ + + /* + * If the IDENTIFY DEVICE data received in words 25 and 26 from the ATA + * device are ASCII spaces (20h), do this translation. + */ + if ( (pSATAIdData->firmwareVersion[4] == 0x20 ) && + (pSATAIdData->firmwareVersion[5] == 0x00 ) && + (pSATAIdData->firmwareVersion[6] == 0x20 ) && + (pSATAIdData->firmwareVersion[7] == 0x00 ) + ) + { + pInquiry[32] = pSATAIdData->firmwareVersion[0]; + pInquiry[33] = pSATAIdData->firmwareVersion[1]; + pInquiry[34] = pSATAIdData->firmwareVersion[2]; + pInquiry[35] = pSATAIdData->firmwareVersion[3]; + } + else + { + pInquiry[32] = pSATAIdData->firmwareVersion[4]; + pInquiry[33] = pSATAIdData->firmwareVersion[5]; + pInquiry[34] = pSATAIdData->firmwareVersion[6]; + pInquiry[35] = pSATAIdData->firmwareVersion[7]; + } +#endif + + TI_DBG5(("satInquiryStandard: end\n")); + +} + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI INQUIRY page 0. + * + * SAT implementation for SCSI INQUIRY page 0. + * + * \param pInquiry: Pointer to Inquiry Data buffer. + * \param pSATAIdData: Pointer to ATA IDENTIFY DEVICE data. + * + * \return None. + */ +/*****************************************************************************/ +GLOBAL void satInquiryPage0( + bit8 *pInquiry, + agsaSATAIdentifyData_t *pSATAIdData) +{ + + TI_DBG5(("satInquiryPage0: entry\n")); + + /* + See SPC-4, 7.6.9, p 345 + and SAT revision 8, 10.3.2, p 77 + */ + pInquiry[0] = 0x00; + pInquiry[1] = 0x00; /* page code */ + pInquiry[2] = 0x00; /* reserved */ + pInquiry[3] = 7 - 3; /* last index(in this case, 6) - 3; page length */ + + /* supported vpd page list */ + pInquiry[4] = 0x00; /* page 0x00 supported */ + pInquiry[5] = 0x80; /* page 0x80 supported */ + pInquiry[6] = 0x83; /* page 0x83 supported */ + pInquiry[7] = 0x89; /* page 0x89 supported */ + +} + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI INQUIRY page 83. + * + * SAT implementation for SCSI INQUIRY page 83. + * + * \param pInquiry: Pointer to Inquiry Data buffer. + * \param pSATAIdData: Pointer to ATA IDENTIFY DEVICE data. + * + * \return None. + */ +/*****************************************************************************/ +GLOBAL void satInquiryPage83( + bit8 *pInquiry, + agsaSATAIdentifyData_t *pSATAIdData, + satDeviceData_t *pSatDevData) +{ + + satSimpleSATAIdentifyData_t *pSimpleData; + + /* + * When translating the fields, in some cases using the simple form of SATA + * Identify Device Data is easier. So we define it here. + * Both pSimpleData and pSATAIdData points to the same data. + */ + pSimpleData = ( satSimpleSATAIdentifyData_t *)pSATAIdData; + + TI_DBG5(("satInquiryPage83: entry\n")); + + pInquiry[0] = 0x00; + pInquiry[1] = 0x83; /* page code */ + pInquiry[2] = 0; /* Reserved */ + + /* + * If the ATA device returns word 87 bit 8 set to one in its IDENTIFY DEVICE + * data indicating that it supports the WORLD WIDE NAME field + * (i.e., words 108-111), the SATL shall include an identification descriptor + * containing a logical unit name. + */ + if ( pSatDevData->satWWNSupport) + { + /* Fill in SAT Rev8 Table85 */ + /* + * Logical unit name derived from the world wide name. + */ + pInquiry[3] = 12; /* 15-3; page length, no addition ID descriptor assumed*/ + + /* + * Identifier descriptor + */ + pInquiry[4] = 0x01; /* Code set: binary codes */ + pInquiry[5] = 0x03; /* Identifier type : NAA */ + pInquiry[6] = 0x00; /* Reserved */ + pInquiry[7] = 0x08; /* Identifier length */ + + /* Bit 4-7 NAA field, bit 0-3 MSB of IEEE Company ID */ + pInquiry[8] = (bit8)((pSATAIdData->namingAuthority) >> 8); + pInquiry[9] = (bit8)((pSATAIdData->namingAuthority) & 0xFF); /* IEEE Company ID */ + pInquiry[10] = (bit8)((pSATAIdData->namingAuthority1) >> 8); /* IEEE Company ID */ + /* Bit 4-7 LSB of IEEE Company ID, bit 0-3 MSB of Vendor Specific ID */ + pInquiry[11] = (bit8)((pSATAIdData->namingAuthority1) & 0xFF); + pInquiry[12] = (bit8)((pSATAIdData->uniqueID_bit16_31) >> 8); /* Vendor Specific ID */ + pInquiry[13] = (bit8)((pSATAIdData->uniqueID_bit16_31) & 0xFF); /* Vendor Specific ID */ + pInquiry[14] = (bit8)((pSATAIdData->uniqueID_bit0_15) >> 8); /* Vendor Specific ID */ + pInquiry[15] = (bit8)((pSATAIdData->uniqueID_bit0_15) & 0xFF); /* Vendor Specific ID */ + + } + else + { + /* Fill in SAT Rev8 Table86 */ + /* + * Logical unit name derived from the model number and serial number. + */ + pInquiry[3] = 72; /* 75 - 3; page length */ + + /* + * Identifier descriptor + */ + pInquiry[4] = 0x02; /* Code set: ASCII codes */ + pInquiry[5] = 0x01; /* Identifier type : T10 vendor ID based */ + pInquiry[6] = 0x00; /* Reserved */ + pInquiry[7] = 0x44; /* 0x44, 68 Identifier length */ + + /* Byte 8 to 15 is the vendor id string 'ATA '. */ + osti_strncpy((char *)&pInquiry[8], AG_SAT_VENDOR_ID_STRING, 8); + + + /* + * Byte 16 to 75 is vendor specific id + */ + pInquiry[16] = (bit8)((pSimpleData->word[27]) >> 8); + pInquiry[17] = (bit8)((pSimpleData->word[27]) & 0x00ff); + pInquiry[18] = (bit8)((pSimpleData->word[28]) >> 8); + pInquiry[19] = (bit8)((pSimpleData->word[28]) & 0x00ff); + pInquiry[20] = (bit8)((pSimpleData->word[29]) >> 8); + pInquiry[21] = (bit8)((pSimpleData->word[29]) & 0x00ff); + pInquiry[22] = (bit8)((pSimpleData->word[30]) >> 8); + pInquiry[23] = (bit8)((pSimpleData->word[30]) & 0x00ff); + pInquiry[24] = (bit8)((pSimpleData->word[31]) >> 8); + pInquiry[25] = (bit8)((pSimpleData->word[31]) & 0x00ff); + pInquiry[26] = (bit8)((pSimpleData->word[32]) >> 8); + pInquiry[27] = (bit8)((pSimpleData->word[32]) & 0x00ff); + pInquiry[28] = (bit8)((pSimpleData->word[33]) >> 8); + pInquiry[29] = (bit8)((pSimpleData->word[33]) & 0x00ff); + pInquiry[30] = (bit8)((pSimpleData->word[34]) >> 8); + pInquiry[31] = (bit8)((pSimpleData->word[34]) & 0x00ff); + pInquiry[32] = (bit8)((pSimpleData->word[35]) >> 8); + pInquiry[33] = (bit8)((pSimpleData->word[35]) & 0x00ff); + pInquiry[34] = (bit8)((pSimpleData->word[36]) >> 8); + pInquiry[35] = (bit8)((pSimpleData->word[36]) & 0x00ff); + pInquiry[36] = (bit8)((pSimpleData->word[37]) >> 8); + pInquiry[37] = (bit8)((pSimpleData->word[37]) & 0x00ff); + pInquiry[38] = (bit8)((pSimpleData->word[38]) >> 8); + pInquiry[39] = (bit8)((pSimpleData->word[38]) & 0x00ff); + pInquiry[40] = (bit8)((pSimpleData->word[39]) >> 8); + pInquiry[41] = (bit8)((pSimpleData->word[39]) & 0x00ff); + pInquiry[42] = (bit8)((pSimpleData->word[40]) >> 8); + pInquiry[43] = (bit8)((pSimpleData->word[40]) & 0x00ff); + pInquiry[44] = (bit8)((pSimpleData->word[41]) >> 8); + pInquiry[45] = (bit8)((pSimpleData->word[41]) & 0x00ff); + pInquiry[46] = (bit8)((pSimpleData->word[42]) >> 8); + pInquiry[47] = (bit8)((pSimpleData->word[42]) & 0x00ff); + pInquiry[48] = (bit8)((pSimpleData->word[43]) >> 8); + pInquiry[49] = (bit8)((pSimpleData->word[43]) & 0x00ff); + pInquiry[50] = (bit8)((pSimpleData->word[44]) >> 8); + pInquiry[51] = (bit8)((pSimpleData->word[44]) & 0x00ff); + pInquiry[52] = (bit8)((pSimpleData->word[45]) >> 8); + pInquiry[53] = (bit8)((pSimpleData->word[45]) & 0x00ff); + pInquiry[54] = (bit8)((pSimpleData->word[46]) >> 8); + pInquiry[55] = (bit8)((pSimpleData->word[46]) & 0x00ff); + + pInquiry[56] = (bit8)((pSimpleData->word[10]) >> 8); + pInquiry[57] = (bit8)((pSimpleData->word[10]) & 0x00ff); + pInquiry[58] = (bit8)((pSimpleData->word[11]) >> 8); + pInquiry[59] = (bit8)((pSimpleData->word[11]) & 0x00ff); + pInquiry[60] = (bit8)((pSimpleData->word[12]) >> 8); + pInquiry[61] = (bit8)((pSimpleData->word[12]) & 0x00ff); + pInquiry[62] = (bit8)((pSimpleData->word[13]) >> 8); + pInquiry[63] = (bit8)((pSimpleData->word[13]) & 0x00ff); + pInquiry[64] = (bit8)((pSimpleData->word[14]) >> 8); + pInquiry[65] = (bit8)((pSimpleData->word[14]) & 0x00ff); + pInquiry[66] = (bit8)((pSimpleData->word[15]) >> 8); + pInquiry[67] = (bit8)((pSimpleData->word[15]) & 0x00ff); + pInquiry[68] = (bit8)((pSimpleData->word[16]) >> 8); + pInquiry[69] = (bit8)((pSimpleData->word[16]) & 0x00ff); + pInquiry[70] = (bit8)((pSimpleData->word[17]) >> 8); + pInquiry[71] = (bit8)((pSimpleData->word[17]) & 0x00ff); + pInquiry[72] = (bit8)((pSimpleData->word[18]) >> 8); + pInquiry[73] = (bit8)((pSimpleData->word[18]) & 0x00ff); + pInquiry[74] = (bit8)((pSimpleData->word[19]) >> 8); + pInquiry[75] = (bit8)((pSimpleData->word[19]) & 0x00ff); + } + +} + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI INQUIRY page 89. + * + * SAT implementation for SCSI INQUIRY page 89. + * + * \param pInquiry: Pointer to Inquiry Data buffer. + * \param pSATAIdData: Pointer to ATA IDENTIFY DEVICE data. + * \param pSatDevData Pointer to internal device data structure + * + * \return None. + */ +/*****************************************************************************/ +GLOBAL void satInquiryPage89( + bit8 *pInquiry, + agsaSATAIdentifyData_t *pSATAIdData, + satDeviceData_t *pSatDevData) +{ + /* + SAT revision 8, 10.3.5, p 83 + */ + satSimpleSATAIdentifyData_t *pSimpleData; + + /* + * When translating the fields, in some cases using the simple form of SATA + * Identify Device Data is easier. So we define it here. + * Both pSimpleData and pSATAIdData points to the same data. + */ + pSimpleData = ( satSimpleSATAIdentifyData_t *)pSATAIdData; + + TI_DBG5(("satInquiryPage89: start\n")); + + pInquiry[0] = 0x00; /* Peripheral Qualifier and Peripheral Device Type */ + pInquiry[1] = 0x89; /* page code */ + + /* Page length 0x238 */ + pInquiry[2] = 0x02; + pInquiry[3] = 0x38; + + pInquiry[4] = 0x0; /* reserved */ + pInquiry[5] = 0x0; /* reserved */ + pInquiry[6] = 0x0; /* reserved */ + pInquiry[7] = 0x0; /* reserved */ + + /* SAT Vendor Identification */ + osti_strncpy((char*)&pInquiry[8], "PMC-SIERRA", 8); /* 8 bytes */ + + /* SAT Product Idetification */ + osti_strncpy((char*)&pInquiry[16], "Tachyon-SPC ", 16); /* 16 bytes */ + + /* SAT Product Revision Level */ + osti_strncpy((char*)&pInquiry[32], "01", 4); /* 4 bytes */ + + /* Signature, SAT revision8, Table88, p85 */ + + + pInquiry[36] = 0x34; /* FIS type */ + if (pSatDevData->satDeviceType == SATA_ATA_DEVICE) + { + /* interrupt assume to be 0 */ + pInquiry[37] = (bit8)((pSatDevData->satPMField) >> (4 * 7)); /* first four bits of PM field */ + } + else + { + /* interrupt assume to be 1 */ + pInquiry[37] = (bit8)(0x40 + (bit8)(((pSatDevData->satPMField) >> (4 * 7)))); /* first four bits of PM field */ + } + pInquiry[38] = 0; + pInquiry[39] = 0; + + if (pSatDevData->satDeviceType == SATA_ATA_DEVICE) + { + pInquiry[40] = 0x01; /* LBA Low */ + pInquiry[41] = 0x00; /* LBA Mid */ + pInquiry[42] = 0x00; /* LBA High */ + pInquiry[43] = 0x00; /* Device */ + pInquiry[44] = 0x00; /* LBA Low Exp */ + pInquiry[45] = 0x00; /* LBA Mid Exp */ + pInquiry[46] = 0x00; /* LBA High Exp */ + pInquiry[47] = 0x00; /* Reserved */ + pInquiry[48] = 0x01; /* Sector Count */ + pInquiry[49] = 0x00; /* Sector Count Exp */ + } + else + { + pInquiry[40] = 0x01; /* LBA Low */ + pInquiry[41] = 0x00; /* LBA Mid */ + pInquiry[42] = 0x00; /* LBA High */ + pInquiry[43] = 0x00; /* Device */ + pInquiry[44] = 0x00; /* LBA Low Exp */ + pInquiry[45] = 0x00; /* LBA Mid Exp */ + pInquiry[46] = 0x00; /* LBA High Exp */ + pInquiry[47] = 0x00; /* Reserved */ + pInquiry[48] = 0x01; /* Sector Count */ + pInquiry[49] = 0x00; /* Sector Count Exp */ + } + + /* Reserved */ + pInquiry[50] = 0x00; + pInquiry[51] = 0x00; + pInquiry[52] = 0x00; + pInquiry[53] = 0x00; + pInquiry[54] = 0x00; + pInquiry[55] = 0x00; + + /* Command Code */ + if (pSatDevData->satDeviceType == SATA_ATA_DEVICE) + { + pInquiry[56] = 0xEC; /* IDENTIFY DEVICE */ + } + else + { + pInquiry[56] = 0xA1; /* IDENTIFY PACKET DEVICE */ + } + /* Reserved */ + pInquiry[57] = 0x0; + pInquiry[58] = 0x0; + pInquiry[59] = 0x0; + + /* Identify Device */ + osti_memcpy(&pInquiry[60], pSimpleData, sizeof(satSimpleSATAIdentifyData_t)); + return; +} + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI INQUIRY page 0. + * + * SAT implementation for SCSI INQUIRY page 0. + * + * \param pInquiry: Pointer to Inquiry Data buffer. + * \param pSATAIdData: Pointer to ATA IDENTIFY DEVICE data. + * + * \return None. + */ +/*****************************************************************************/ +GLOBAL void satInquiryPage80( + bit8 *pInquiry, + agsaSATAIdentifyData_t *pSATAIdData) +{ + + TI_DBG5(("satInquiryPage80: entry\n")); + + /* + See SPC-4, 7.6.9, p 345 + and SAT revision 8, 10.3.3, p 77 + */ + pInquiry[0] = 0x00; + pInquiry[1] = 0x80; /* page code */ + pInquiry[2] = 0x00; /* reserved */ + pInquiry[3] = 0x14; /* page length */ + + /* supported vpd page list */ + pInquiry[4] = pSATAIdData->serialNumber[1]; + pInquiry[5] = pSATAIdData->serialNumber[0]; + pInquiry[6] = pSATAIdData->serialNumber[3]; + pInquiry[7] = pSATAIdData->serialNumber[2]; + pInquiry[8] = pSATAIdData->serialNumber[5]; + pInquiry[9] = pSATAIdData->serialNumber[4]; + pInquiry[10] = pSATAIdData->serialNumber[7]; + pInquiry[11] = pSATAIdData->serialNumber[6]; + pInquiry[12] = pSATAIdData->serialNumber[9]; + pInquiry[13] = pSATAIdData->serialNumber[8]; + pInquiry[14] = pSATAIdData->serialNumber[11]; + pInquiry[15] = pSATAIdData->serialNumber[10]; + pInquiry[16] = pSATAIdData->serialNumber[13]; + pInquiry[17] = pSATAIdData->serialNumber[12]; + pInquiry[18] = pSATAIdData->serialNumber[15]; + pInquiry[19] = pSATAIdData->serialNumber[14]; + pInquiry[20] = pSATAIdData->serialNumber[17]; + pInquiry[21] = pSATAIdData->serialNumber[16]; + pInquiry[22] = pSATAIdData->serialNumber[19]; + pInquiry[23] = pSATAIdData->serialNumber[18]; + + +} + + + +/*****************************************************************************/ +/*! \brief Send READ LOG EXT ATA PAGE 10h command to sata drive. + * + * Send READ LOG EXT ATA command PAGE 10h request to LL layer. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satSendReadLogExt( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) + +{ + + bit32 status; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; + + fis = satIOContext->pFis; + + TI_DBG1(("satSendReadLogExt: tiDeviceHandle=%p tiIORequest=%p\n", + tiDeviceHandle, tiIORequest)); + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_READ_LOG_EXT; /* 0x2F */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = 0x10; /* Page number */ + fis->d.lbaMid = 0; /* */ + fis->d.lbaHigh = 0; /* */ + fis->d.device = 0; /* DEV is ignored in SATA */ + fis->d.lbaLowExp = 0; /* */ + fis->d.lbaMidExp = 0; /* */ + fis->d.lbaHighExp = 0; /* */ + fis->d.featuresExp = 0; /* FIS reserve */ + fis->d.sectorCount = 0x01; /* 1 sector counts*/ + fis->d.sectorCountExp = 0x00; /* 1 sector counts */ + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satReadLogExtCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + TI_DBG1(("satSendReadLogExt: end status %d\n", status)); + + return (status); + +} + + +/*****************************************************************************/ +/*! \brief SAT default ATA status and ATA error translation to SCSI. + * + * SSAT default ATA status and ATA error translation to SCSI. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param satIOContext: Pointer to the SAT IO Context + * \param pSense: Pointer to scsiRspSense_t + * \param ataStatus: ATA status register + * \param ataError: ATA error register + * \param interruptContext: Interrupt context + * + * \return None + */ +/*****************************************************************************/ +GLOBAL void osSatDefaultTranslation( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + satIOContext_t *satIOContext, + scsiRspSense_t *pSense, + bit8 ataStatus, + bit8 ataError, + bit32 interruptContext ) +{ + + /* + * Check for device fault case + */ + if ( ataStatus & DF_ATA_STATUS_MASK ) + { + satSetSensePayload( pSense, + SCSI_SNSKEY_HARDWARE_ERROR, + 0, + SCSI_SNSCODE_INTERNAL_TARGET_FAILURE, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + interruptContext ); + return; + } + + /* + * If status error bit it set, need to check the error register + */ + if ( ataStatus & ERR_ATA_STATUS_MASK ) + { + if ( ataError & NM_ATA_ERROR_MASK ) + { + TI_DBG1(("osSatDefaultTranslation: NM_ATA_ERROR ataError= 0x%x, tiIORequest=%p\n", + ataError, tiIORequest)); + satSetSensePayload( pSense, + SCSI_SNSKEY_NOT_READY, + 0, + SCSI_SNSCODE_MEDIUM_NOT_PRESENT, + satIOContext); + } + + else if (ataError & UNC_ATA_ERROR_MASK) + { + TI_DBG1(("osSatDefaultTranslation: UNC_ATA_ERROR ataError= 0x%x, tiIORequest=%p\n", + ataError, tiIORequest)); + satSetSensePayload( pSense, + SCSI_SNSKEY_MEDIUM_ERROR, + 0, + SCSI_SNSCODE_UNRECOVERED_READ_ERROR, + satIOContext); + } + + else if (ataError & IDNF_ATA_ERROR_MASK) + { + TI_DBG1(("osSatDefaultTranslation: IDNF_ATA_ERROR ataError= 0x%x, tiIORequest=%p\n", + ataError, tiIORequest)); + satSetSensePayload( pSense, + SCSI_SNSKEY_MEDIUM_ERROR, + 0, + SCSI_SNSCODE_RECORD_NOT_FOUND, + satIOContext); + } + + else if (ataError & MC_ATA_ERROR_MASK) + { + TI_DBG1(("osSatDefaultTranslation: MC_ATA_ERROR ataError= 0x%x, tiIORequest=%p\n", + ataError, tiIORequest)); + satSetSensePayload( pSense, + SCSI_SNSKEY_UNIT_ATTENTION, + 0, + SCSI_SNSCODE_NOT_READY_TO_READY_CHANGE, + satIOContext); + } + + else if (ataError & MCR_ATA_ERROR_MASK) + { + TI_DBG1(("osSatDefaultTranslation: MCR_ATA_ERROR ataError= 0x%x, tiIORequest=%p\n", + ataError, tiIORequest)); + satSetSensePayload( pSense, + SCSI_SNSKEY_UNIT_ATTENTION, + 0, + SCSI_SNSCODE_OPERATOR_MEDIUM_REMOVAL_REQUEST, + satIOContext); + } + + else if (ataError & ICRC_ATA_ERROR_MASK) + { + TI_DBG1(("osSatDefaultTranslation: ICRC_ATA_ERROR ataError= 0x%x, tiIORequest=%p\n", + ataError, tiIORequest)); + satSetSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_INFORMATION_UNIT_CRC_ERROR, + satIOContext); + } + + else if (ataError & ABRT_ATA_ERROR_MASK) + { + TI_DBG1(("osSatDefaultTranslation: ABRT_ATA_ERROR ataError= 0x%x, tiIORequest=%p\n", + ataError, tiIORequest)); + satSetSensePayload( pSense, + SCSI_SNSKEY_ABORTED_COMMAND, + 0, + SCSI_SNSCODE_NO_ADDITIONAL_INFO, + satIOContext); + } + + else + { + TI_DBG1(("osSatDefaultTranslation: **** UNEXPECTED ATA_ERROR **** ataError= 0x%x, tiIORequest=%p\n", + ataError, tiIORequest)); + satSetSensePayload( pSense, + SCSI_SNSKEY_HARDWARE_ERROR, + 0, + SCSI_SNSCODE_INTERNAL_TARGET_FAILURE, + satIOContext); + } + + /* Send the completion response now */ + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + interruptContext ); + return; + + + } + + else /* (ataStatus & ERR_ATA_STATUS_MASK ) is false */ + { + /* This case should never happen */ + TI_DBG1(("osSatDefaultTranslation: *** UNEXPECTED ATA status 0x%x *** tiIORequest=%p\n", + ataStatus, tiIORequest)); + satSetSensePayload( pSense, + SCSI_SNSKEY_HARDWARE_ERROR, + 0, + SCSI_SNSCODE_INTERNAL_TARGET_FAILURE, + satIOContext); + + ostiInitiatorIOCompleted( tiRoot, + tiIORequest, + tiIOSuccess, + SCSI_STAT_CHECK_CONDITION, + satIOContext->pTiSenseData, + interruptContext ); + return; + + } + + +} + +/*****************************************************************************/ +/*! \brief Allocate resource for SAT intervally generated I/O. + * + * Allocate resource for SAT intervally generated I/O. + * + * \param tiRoot: Pointer to TISA driver/port instance. + * \param satDevData: Pointer to SAT specific device data. + * \param allocLength: Length in byte of the DMA mem to allocate, upto + * one page size. + * \param satIntIo: Pointer (output) to context for SAT internally + * generated I/O that is allocated by this routine. + * + * \return If command is started successfully + * - \e tiSuccess: Success. + * - \e tiError: Failed allocating resource. + */ +/*****************************************************************************/ +GLOBAL satInternalIo_t * satAllocIntIoResource( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + satDeviceData_t *satDevData, + bit32 dmaAllocLength, + satInternalIo_t *satIntIo) +{ + tdList_t *tdList = agNULL; + bit32 memAllocStatus; + + TI_DBG1(("satAllocIntIoResource: start\n")); + TI_DBG6(("satAllocIntIoResource: satIntIo %p\n", satIntIo)); + if (satDevData == agNULL) + { + TI_DBG1(("satAllocIntIoResource: ***** ASSERT satDevData is null\n")); + return agNULL; + } + + tdsaSingleThreadedEnter(tiRoot, TD_SATA_LOCK); + if (!TDLIST_EMPTY(&(satDevData->satFreeIntIoLinkList))) + { + TDLIST_DEQUEUE_FROM_HEAD(&tdList, &(satDevData->satFreeIntIoLinkList)); + } + else + { + tdsaSingleThreadedLeave(tiRoot, TD_SATA_LOCK); + TI_DBG1(("satAllocIntIoResource() no more internal free link.\n")); + return agNULL; + } + + if (tdList == agNULL) + { + tdsaSingleThreadedLeave(tiRoot, TD_SATA_LOCK); + TI_DBG1(("satAllocIntIoResource() FAIL to alloc satIntIo.\n")); + return agNULL; + } + + satIntIo = TDLIST_OBJECT_BASE( satInternalIo_t, satIntIoLink, tdList); + TI_DBG6(("satAllocIntIoResource: satDevData %p satIntIo id %d\n", satDevData, satIntIo->id)); + + /* Put in active list */ + TDLIST_DEQUEUE_THIS (&(satIntIo->satIntIoLink)); + TDLIST_ENQUEUE_AT_TAIL (&(satIntIo->satIntIoLink), &(satDevData->satActiveIntIoLinkList)); + tdsaSingleThreadedLeave(tiRoot, TD_SATA_LOCK); + +#ifdef REMOVED + /* Put in active list */ + tdsaSingleThreadedEnter(tiRoot, TD_SATA_LOCK); + TDLIST_DEQUEUE_THIS (tdList); + TDLIST_ENQUEUE_AT_TAIL (tdList, &(satDevData->satActiveIntIoLinkList)); + tdsaSingleThreadedLeave(tiRoot, TD_SATA_LOCK); + + satIntIo = TDLIST_OBJECT_BASE( satInternalIo_t, satIntIoLink, tdList); + TI_DBG6(("satAllocIntIoResource: satDevData %p satIntIo id %d\n", satDevData, satIntIo->id)); +#endif + + /* + typedef struct + { + tdList_t satIntIoLink; + tiIORequest_t satIntTiIORequest; + void *satIntRequestBody; + tiScsiInitiatorRequest_t satIntTiScsiXchg; + tiMem_t satIntDmaMem; + tiMem_t satIntReqBodyMem; + bit32 satIntFlag; + } satInternalIo_t; + */ + + /* + * Allocate mem for Request Body + */ + satIntIo->satIntReqBodyMem.totalLength = sizeof(tdIORequestBody_t); + + memAllocStatus = ostiAllocMemory( tiRoot, + &satIntIo->satIntReqBodyMem.osHandle, + (void **)&satIntIo->satIntRequestBody, + &satIntIo->satIntReqBodyMem.physAddrUpper, + &satIntIo->satIntReqBodyMem.physAddrLower, + 8, + satIntIo->satIntReqBodyMem.totalLength, + agTRUE ); + + if (memAllocStatus != tiSuccess) + { + TI_DBG1(("satAllocIntIoResource() FAIL to alloc mem for Req Body.\n")); + /* + * Return satIntIo to the free list + */ + tdsaSingleThreadedEnter(tiRoot, TD_SATA_LOCK); + TDLIST_DEQUEUE_THIS (&satIntIo->satIntIoLink); + TDLIST_ENQUEUE_AT_HEAD(&satIntIo->satIntIoLink, &satDevData->satFreeIntIoLinkList); + tdsaSingleThreadedLeave(tiRoot, TD_SATA_LOCK); + + return agNULL; + } + + /* + * Allocate DMA memory if required + */ + if (dmaAllocLength != 0) + { + satIntIo->satIntDmaMem.totalLength = dmaAllocLength; + + memAllocStatus = ostiAllocMemory( tiRoot, + &satIntIo->satIntDmaMem.osHandle, + (void **)&satIntIo->satIntDmaMem.virtPtr, + &satIntIo->satIntDmaMem.physAddrUpper, + &satIntIo->satIntDmaMem.physAddrLower, + 8, + satIntIo->satIntDmaMem.totalLength, + agFALSE); + TI_DBG6(("satAllocIntIoResource: len %d \n", satIntIo->satIntDmaMem.totalLength)); + TI_DBG6(("satAllocIntIoResource: pointer %p \n", satIntIo->satIntDmaMem.osHandle)); + + if (memAllocStatus != tiSuccess) + { + TI_DBG1(("satAllocIntIoResource() FAIL to alloc mem for DMA mem.\n")); + /* + * Return satIntIo to the free list + */ + tdsaSingleThreadedEnter(tiRoot, TD_SATA_LOCK); + TDLIST_DEQUEUE_THIS (&satIntIo->satIntIoLink); + TDLIST_ENQUEUE_AT_HEAD(&satIntIo->satIntIoLink, &satDevData->satFreeIntIoLinkList); + tdsaSingleThreadedLeave(tiRoot, TD_SATA_LOCK); + + /* + * Free mem allocated for Req body + */ + ostiFreeMemory( tiRoot, + satIntIo->satIntReqBodyMem.osHandle, + satIntIo->satIntReqBodyMem.totalLength); + + return agNULL; + } + } + + /* + typedef struct + { + tdList_t satIntIoLink; + tiIORequest_t satIntTiIORequest; + void *satIntRequestBody; + tiScsiInitiatorRequest_t satIntTiScsiXchg; + tiMem_t satIntDmaMem; + tiMem_t satIntReqBodyMem; + bit32 satIntFlag; + } satInternalIo_t; + */ + + /* + * Initialize satIntTiIORequest field + */ + satIntIo->satIntTiIORequest.osData = agNULL; /* Not used for internal SAT I/O */ + satIntIo->satIntTiIORequest.tdData = satIntIo->satIntRequestBody; + + /* + * saves the original tiIOrequest + */ + satIntIo->satOrgTiIORequest = tiIORequest; + /* + typedef struct tiIniScsiCmnd + { + tiLUN_t lun; + bit32 expDataLength; + bit32 taskAttribute; + bit32 crn; + bit8 cdb[16]; + } tiIniScsiCmnd_t; + + typedef struct tiScsiInitiatorExchange + { + void *sglVirtualAddr; + tiIniScsiCmnd_t scsiCmnd; + tiSgl_t agSgl1; + tiSgl_t agSgl2; + tiDataDirection_t dataDirection; + } tiScsiInitiatorRequest_t; + + */ + + /* + * Initialize satIntTiScsiXchg. Since the internal SAT request is NOT + * originated from SCSI request, only the following fields are initialized: + * - sglVirtualAddr if DMA transfer is involved + * - agSgl1 if DMA transfer is involved + * - expDataLength in scsiCmnd since this field is read by sataLLIOStart() + */ + if (dmaAllocLength != 0) + { + satIntIo->satIntTiScsiXchg.sglVirtualAddr = satIntIo->satIntDmaMem.virtPtr; + + OSSA_WRITE_LE_32(agNULL, &satIntIo->satIntTiScsiXchg.agSgl1.len, 0, + satIntIo->satIntDmaMem.totalLength); + satIntIo->satIntTiScsiXchg.agSgl1.lower = satIntIo->satIntDmaMem.physAddrLower; + satIntIo->satIntTiScsiXchg.agSgl1.upper = satIntIo->satIntDmaMem.physAddrUpper; + satIntIo->satIntTiScsiXchg.agSgl1.type = tiSgl; + + satIntIo->satIntTiScsiXchg.scsiCmnd.expDataLength = satIntIo->satIntDmaMem.totalLength; + } + else + { + satIntIo->satIntTiScsiXchg.sglVirtualAddr = agNULL; + + satIntIo->satIntTiScsiXchg.agSgl1.len = 0; + satIntIo->satIntTiScsiXchg.agSgl1.lower = 0; + satIntIo->satIntTiScsiXchg.agSgl1.upper = 0; + satIntIo->satIntTiScsiXchg.agSgl1.type = tiSgl; + + satIntIo->satIntTiScsiXchg.scsiCmnd.expDataLength = 0; + } + + TI_DBG5(("satAllocIntIoResource: satIntIo->satIntTiScsiXchg.agSgl1.len %d\n", satIntIo->satIntTiScsiXchg.agSgl1.len)); + + TI_DBG5(("satAllocIntIoResource: satIntIo->satIntTiScsiXchg.agSgl1.upper %d\n", satIntIo->satIntTiScsiXchg.agSgl1.upper)); + + TI_DBG5(("satAllocIntIoResource: satIntIo->satIntTiScsiXchg.agSgl1.lower %d\n", satIntIo->satIntTiScsiXchg.agSgl1.lower)); + + TI_DBG5(("satAllocIntIoResource: satIntIo->satIntTiScsiXchg.agSgl1.type %d\n", satIntIo->satIntTiScsiXchg.agSgl1.type)); + TI_DBG5(("satAllocIntIoResource: return satIntIo %p\n", satIntIo)); + return satIntIo; + +} + +/*****************************************************************************/ +/*! \brief Free resource for SAT intervally generated I/O. + * + * Free resource for SAT intervally generated I/O that was previously + * allocated in satAllocIntIoResource(). + * + * \param tiRoot: Pointer to TISA driver/port instance. + * \param satDevData: Pointer to SAT specific device data. + * \param satIntIo: Pointer to context for SAT internal I/O that was + * previously allocated in satAllocIntIoResource(). + * + * \return None + */ +/*****************************************************************************/ +GLOBAL void satFreeIntIoResource( + tiRoot_t *tiRoot, + satDeviceData_t *satDevData, + satInternalIo_t *satIntIo) +{ + TI_DBG6(("satFreeIntIoResource: start\n")); + + if (satIntIo == agNULL) + { + TI_DBG6(("satFreeIntIoResource: allowed call\n")); + return; + } + + /* sets the original tiIOrequest to agNULL for internally generated ATA cmnd */ + satIntIo->satOrgTiIORequest = agNULL; + + /* + * Free DMA memory if previosly alocated + */ + if (satIntIo->satIntTiScsiXchg.scsiCmnd.expDataLength != 0) + { + TI_DBG1(("satFreeIntIoResource: DMA len %d\n", satIntIo->satIntDmaMem.totalLength)); + TI_DBG6(("satFreeIntIoResource: pointer %p\n", satIntIo->satIntDmaMem.osHandle)); + + ostiFreeMemory( tiRoot, + satIntIo->satIntDmaMem.osHandle, + satIntIo->satIntDmaMem.totalLength); + satIntIo->satIntTiScsiXchg.scsiCmnd.expDataLength = 0; + } + + if (satIntIo->satIntReqBodyMem.totalLength != 0) + { + TI_DBG1(("satFreeIntIoResource: req body len %d\n", satIntIo->satIntReqBodyMem.totalLength)); + /* + * Free mem allocated for Req body + */ + ostiFreeMemory( tiRoot, + satIntIo->satIntReqBodyMem.osHandle, + satIntIo->satIntReqBodyMem.totalLength); + + satIntIo->satIntReqBodyMem.totalLength = 0; + } + + TI_DBG6(("satFreeIntIoResource: satDevData %p satIntIo id %d\n", satDevData, satIntIo->id)); + /* + * Return satIntIo to the free list + */ + tdsaSingleThreadedEnter(tiRoot, TD_SATA_LOCK); + TDLIST_DEQUEUE_THIS (&(satIntIo->satIntIoLink)); + TDLIST_ENQUEUE_AT_TAIL (&(satIntIo->satIntIoLink), &(satDevData->satFreeIntIoLinkList)); + tdsaSingleThreadedLeave(tiRoot, TD_SATA_LOCK); + +} + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI INQUIRY. + * + * SAT implementation for SCSI INQUIRY. + * This function sends ATA Identify Device data command for SCSI INQUIRY + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satSendIDDev( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) + +{ + bit32 status; + bit32 agRequestType; + satDeviceData_t *pSatDevData; + agsaFisRegHostToDevice_t *fis; +#ifdef TD_DEBUG_ENABLE + satInternalIo_t *satIntIoContext; + tdsaDeviceData_t *oneDeviceData; + tdIORequestBody_t *tdIORequestBody; +#endif + + pSatDevData = satIOContext->pSatDevData; + fis = satIOContext->pFis; + + TI_DBG5(("satSendIDDev: start\n")); +#ifdef TD_DEBUG_ENABLE + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; +#endif + TI_DBG5(("satSendIDDev: did %d\n", oneDeviceData->id)); + + +#ifdef TD_DEBUG_ENABLE + satIntIoContext = satIOContext->satIntIoContext; + tdIORequestBody = satIntIoContext->satIntRequestBody; +#endif + + TI_DBG5(("satSendIDDev: satIOContext %p tdIORequestBody %p\n", satIOContext, tdIORequestBody)); + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + if (pSatDevData->satDeviceType == SATA_ATAPI_DEVICE) + fis->h.command = SAT_IDENTIFY_PACKET_DEVICE; /* 0x40 */ + else + fis->h.command = SAT_IDENTIFY_DEVICE; /* 0xEC */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.device = 0; /* FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satInquiryCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + +#ifdef TD_INTERNAL_DEBUG + tdhexdump("satSendIDDev", (bit8 *)satIOContext->pFis, sizeof(agsaFisRegHostToDevice_t)); +#ifdef TD_DEBUG_ENABLE + tdhexdump("satSendIDDev LL", (bit8 *)&(tdIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev), sizeof(agsaFisRegHostToDevice_t)); +#endif +#endif + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + TI_DBG6(("satSendIDDev: end status %d\n", status)); + return status; +} + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI INQUIRY. + * + * SAT implementation for SCSI INQUIRY. + * This function prepares TD layer internal resource to send ATA + * Identify Device data command for SCSI INQUIRY + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +/* prerequsite: tdsaDeviceData and agdevhandle must exist; in other words, LL discovered the device + already */ +/* + convert OS generated IO to TD generated IO due to difference in sgl +*/ +GLOBAL bit32 satStartIDDev( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext + ) +{ + satInternalIo_t *satIntIo = agNULL; + satDeviceData_t *satDevData = agNULL; + tdIORequestBody_t *tdIORequestBody; + satIOContext_t *satNewIOContext; + bit32 status; + + TI_DBG6(("satStartIDDev: start\n")); + + satDevData = satIOContext->pSatDevData; + + TI_DBG6(("satStartIDDev: before alloc\n")); + + /* allocate identify device command */ + satIntIo = satAllocIntIoResource( tiRoot, + tiIORequest, + satDevData, + sizeof(agsaSATAIdentifyData_t), /* 512; size of identify device data */ + satIntIo); + + TI_DBG6(("satStartIDDev: before after\n")); + + if (satIntIo == agNULL) + { + TI_DBG1(("satStartIDDev: can't alloacate\n")); + +#if 0 + ostiInitiatorIOCompleted ( + tiRoot, + tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + satIOContext->interruptContext + ); +#endif + + return tiError; + } + + /* fill in fields */ + /* real ttttttthe one worked and the same; 5/21/07/ */ + satIntIo->satOrgTiIORequest = tiIORequest; /* changed */ + tdIORequestBody = satIntIo->satIntRequestBody; + satNewIOContext = &(tdIORequestBody->transport.SATA.satIOContext); + + satNewIOContext->pSatDevData = satDevData; + satNewIOContext->pFis = &(tdIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev); + satNewIOContext->pScsiCmnd = &(satIntIo->satIntTiScsiXchg.scsiCmnd); + satNewIOContext->pSense = &(tdIORequestBody->transport.SATA.sensePayload); + satNewIOContext->pTiSenseData = &(tdIORequestBody->transport.SATA.tiSenseData); + satNewIOContext->tiRequestBody = satIntIo->satIntRequestBody; /* key fix */ + satNewIOContext->interruptContext = tiInterruptContext; + satNewIOContext->satIntIoContext = satIntIo; + + satNewIOContext->ptiDeviceHandle = agNULL; + satNewIOContext->satOrgIOContext = satIOContext; /* changed */ + + /* this is valid only for TD layer generated (not triggered by OS at all) IO */ + satNewIOContext->tiScsiXchg = &(satIntIo->satIntTiScsiXchg); + + + TI_DBG6(("satStartIDDev: OS satIOContext %p \n", satIOContext)); + TI_DBG6(("satStartIDDev: TD satNewIOContext %p \n", satNewIOContext)); + TI_DBG6(("satStartIDDev: OS tiScsiXchg %p \n", satIOContext->tiScsiXchg)); + TI_DBG6(("satStartIDDev: TD tiScsiXchg %p \n", satNewIOContext->tiScsiXchg)); + + + + TI_DBG1(("satStartIDDev: satNewIOContext %p tdIORequestBody %p\n", satNewIOContext, tdIORequestBody)); + + status = satSendIDDev( tiRoot, + &satIntIo->satIntTiIORequest, /* New tiIORequest */ + tiDeviceHandle, + satNewIOContext->tiScsiXchg, /* New tiScsiInitiatorRequest_t *tiScsiRequest, */ + satNewIOContext); + + if (status != tiSuccess) + { + TI_DBG1(("satStartIDDev: failed in sending\n")); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + +#if 0 + ostiInitiatorIOCompleted ( + tiRoot, + tiIORequest, + tiIOFailed, + tiDetailOtherError, + agNULL, + satIOContext->interruptContext + ); +#endif + + return tiError; + } + + + TI_DBG6(("satStartIDDev: end\n")); + + return status; + + +} + +/*****************************************************************************/ +/*! \brief satComputeCDB10LBA. + * + * This fuctions computes LBA of CDB10. + * + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return + * - \e LBA + */ +/*****************************************************************************/ +bit32 satComputeCDB10LBA(satIOContext_t *satIOContext) +{ + tiIniScsiCmnd_t *scsiCmnd; + tiScsiInitiatorRequest_t *tiScsiRequest; + bit32 lba = 0; + + TI_DBG5(("satComputeCDB10LBA: start\n")); + tiScsiRequest = satIOContext->tiScsiXchg; + scsiCmnd = &(tiScsiRequest->scsiCmnd); + + lba = (scsiCmnd->cdb[2] << (8*3)) + (scsiCmnd->cdb[3] << (8*2)) + + (scsiCmnd->cdb[4] << 8) + scsiCmnd->cdb[5]; + + return lba; +} + +/*****************************************************************************/ +/*! \brief satComputeCDB10TL. + * + * This fuctions computes transfer length of CDB10. + * + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return + * - \e TL + */ +/*****************************************************************************/ +bit32 satComputeCDB10TL(satIOContext_t *satIOContext) +{ + + tiIniScsiCmnd_t *scsiCmnd; + tiScsiInitiatorRequest_t *tiScsiRequest; + bit32 tl = 0; + + TI_DBG5(("satComputeCDB10TL: start\n")); + tiScsiRequest = satIOContext->tiScsiXchg; + scsiCmnd = &(tiScsiRequest->scsiCmnd); + + tl = (scsiCmnd->cdb[7] << 8) + scsiCmnd->cdb[8]; + return tl; +} + +/*****************************************************************************/ +/*! \brief satComputeCDB12LBA. + * + * This fuctions computes LBA of CDB12. + * + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return + * - \e LBA + */ +/*****************************************************************************/ +bit32 satComputeCDB12LBA(satIOContext_t *satIOContext) +{ + tiIniScsiCmnd_t *scsiCmnd; + tiScsiInitiatorRequest_t *tiScsiRequest; + bit32 lba = 0; + + TI_DBG5(("satComputeCDB10LBA: start\n")); + tiScsiRequest = satIOContext->tiScsiXchg; + scsiCmnd = &(tiScsiRequest->scsiCmnd); + + lba = (scsiCmnd->cdb[2] << (8*3)) + (scsiCmnd->cdb[3] << (8*2)) + + (scsiCmnd->cdb[4] << 8) + scsiCmnd->cdb[5]; + + return lba; +} + +/*****************************************************************************/ +/*! \brief satComputeCDB12TL. + * + * This fuctions computes transfer length of CDB12. + * + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return + * - \e TL + */ +/*****************************************************************************/ +bit32 satComputeCDB12TL(satIOContext_t *satIOContext) +{ + + tiIniScsiCmnd_t *scsiCmnd; + tiScsiInitiatorRequest_t *tiScsiRequest; + bit32 tl = 0; + + TI_DBG5(("satComputeCDB10TL: start\n")); + tiScsiRequest = satIOContext->tiScsiXchg; + scsiCmnd = &(tiScsiRequest->scsiCmnd); + + tl = (scsiCmnd->cdb[6] << (8*3)) + (scsiCmnd->cdb[7] << (8*2)) + + (scsiCmnd->cdb[8] << 8) + scsiCmnd->cdb[9]; + return tl; +} + + +/*****************************************************************************/ +/*! \brief satComputeCDB16LBA. + * + * This fuctions computes LBA of CDB16. + * + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return + * - \e LBA + */ +/*****************************************************************************/ +/* + CBD16 has bit64 LBA + But it has to be less than (2^28 - 1) + Therefore, use last four bytes to compute LBA is OK +*/ +bit32 satComputeCDB16LBA(satIOContext_t *satIOContext) +{ + tiIniScsiCmnd_t *scsiCmnd; + tiScsiInitiatorRequest_t *tiScsiRequest; + bit32 lba = 0; + + TI_DBG5(("satComputeCDB10LBA: start\n")); + tiScsiRequest = satIOContext->tiScsiXchg; + scsiCmnd = &(tiScsiRequest->scsiCmnd); + + lba = (scsiCmnd->cdb[6] << (8*3)) + (scsiCmnd->cdb[7] << (8*2)) + + (scsiCmnd->cdb[8] << 8) + scsiCmnd->cdb[9]; + + return lba; +} + +/*****************************************************************************/ +/*! \brief satComputeCDB16TL. + * + * This fuctions computes transfer length of CDB16. + * + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return + * - \e TL + */ +/*****************************************************************************/ +bit32 satComputeCDB16TL(satIOContext_t *satIOContext) +{ + + tiIniScsiCmnd_t *scsiCmnd; + tiScsiInitiatorRequest_t *tiScsiRequest; + bit32 tl = 0; + + TI_DBG5(("satComputeCDB10TL: start\n")); + tiScsiRequest = satIOContext->tiScsiXchg; + scsiCmnd = &(tiScsiRequest->scsiCmnd); + + tl = (scsiCmnd->cdb[10] << (8*3)) + (scsiCmnd->cdb[11] << (8*2)) + + (scsiCmnd->cdb[12] << 8) + scsiCmnd->cdb[13]; + return tl; +} + +/*****************************************************************************/ +/*! \brief satComputeLoopNum. + * + * This fuctions computes the number of interation needed for a transfer + * length with a specific number. + * + * \param a: a numerator + * \param b: a denominator + * + * \return + * - \e number of interation + */ +/*****************************************************************************/ +/* + (tl, denom) + tl can be upto bit32 because CDB16 has bit32 tl + Therefore, fine + either (tl, 0xFF) or (tl, 0xFFFF) +*/ +bit32 satComputeLoopNum(bit32 a, bit32 b) +{ + + bit32 quo = 0, rem = 0; + bit32 LoopNum = 0; + + TI_DBG5(("satComputeLoopNum: start\n")); + + quo = a/b; + + if (quo == 0) + { + LoopNum = 1; + } + else + { + rem = a % b; + if (rem == 0) + { + LoopNum = quo; + } + else + { + LoopNum = quo + 1; + } + } + + return LoopNum; +} + +/*****************************************************************************/ +/*! \brief satAddNComparebit64. + * + * + * + * + * \param a: lba + * \param b: tl + * + * \return + * - \e TRUE if (lba + tl > SAT_TR_LBA_LIMIT) + * - \e FALSE otherwise + * \note: a and b must be in the same length + */ +/*****************************************************************************/ +/* + input: bit8 a[8], bit8 b[8] (lba, tl) must be in same length + if (lba + tl > SAT_TR_LBA_LIMIT) + then returns true + else returns false + (LBA,TL) +*/ +bit32 satAddNComparebit64(bit8 *a, bit8 *b) +{ + bit16 ans[8]; // 0 MSB, 8 LSB + bit8 final_ans[9]; // 0 MSB, 9 LSB + bit8 max[9]; + int i; + + TI_DBG5(("satAddNComparebit64: start\n")); + + osti_memset(ans, 0, sizeof(ans)); + osti_memset(final_ans, 0, sizeof(final_ans)); + osti_memset(max, 0, sizeof(max)); + + max[0] = 0x1; //max = 0x1 0000 0000 0000 0000 + + // adding from LSB to MSB + for(i=7;i>=0;i--) + { + ans[i] = (bit16)(a[i] + b[i]); + if (i != 7) + { + ans[i] = (bit16)(ans[i] + ((ans[i+1] & 0xFF00) >> 8)); + } + } + + /* + filling in the final answer + */ + final_ans[0] = (bit8)(((ans[0] & 0xFF00) >> 8)); + final_ans[1] = (bit8)(ans[0] & 0xFF); + + for(i=2;i<=8;i++) + { + final_ans[i] = (bit8)(ans[i-1] & 0xFF); + } + + //compare final_ans to max + for(i=0;i<=8;i++) + { + if (final_ans[i] > max[i]) + { + TI_DBG5(("satAddNComparebit64: yes at %d\n", i)); + return agTRUE; + } + else if (final_ans[i] < max[i]) + { + TI_DBG5(("satAddNComparebit64: no at %d\n", i)); + return agFALSE; + } + else + { + continue; + } + } + + + return agFALSE; +} + +/*****************************************************************************/ +/*! \brief satAddNComparebit32. + * + * + * + * + * \param a: lba + * \param b: tl + * + * \return + * - \e TRUE if (lba + tl > SAT_TR_LBA_LIMIT) + * - \e FALSE otherwise + * \note: a and b must be in the same length + */ +/*****************************************************************************/ +/* + input: bit8 a[4], bit8 b[4] (lba, tl) must be in same length + if (lba + tl > SAT_TR_LBA_LIMIT) + then returns true + else returns false + (LBA,TL) +*/ +bit32 satAddNComparebit32(bit8 *a, bit8 *b) +{ + bit16 ans[4]; // 0 MSB, 4 LSB + bit8 final_ans[5]; // 0 MSB, 5 LSB + bit8 max[4]; + int i; + + TI_DBG5(("satAddNComparebit32: start\n")); + + osti_memset(ans, 0, sizeof(ans)); + osti_memset(final_ans, 0, sizeof(final_ans)); + osti_memset(max, 0, sizeof(max)); + + max[0] = 0x10; // max =0x1000 0000 + + // adding from LSB to MSB + for(i=3;i>=0;i--) + { + ans[i] = (bit16)(a[i] + b[i]); + if (i != 3) + { + ans[i] = (bit16)(ans[i] + ((ans[i+1] & 0xFF00) >> 8)); + } + } + + + /* + filling in the final answer + */ + final_ans[0] = (bit8)(((ans[0] & 0xFF00) >> 8)); + final_ans[1] = (bit8)(ans[0] & 0xFF); + + for(i=2;i<=4;i++) + { + final_ans[i] = (bit8)(ans[i-1] & 0xFF); + } + + //compare final_ans to max + if (final_ans[0] != 0) + { + TI_DBG5(("satAddNComparebit32: yes bigger and out of range\n")); + return agTRUE; + } + for(i=1;i<=4;i++) + { + if (final_ans[i] > max[i-1]) + { + TI_DBG5(("satAddNComparebit32: yes at %d\n", i)); + return agTRUE; + } + else if (final_ans[i] < max[i-1]) + { + TI_DBG5(("satAddNComparebit32: no at %d\n", i)); + return agFALSE; + } + else + { + continue; + } + } + + + return agFALSE;; +} + +/*****************************************************************************/ +/*! \brief satCompareLBALimitbit. + * + * + * + * + * \param lba: lba + * + * \return + * - \e TRUE if (lba > SAT_TR_LBA_LIMIT - 1) + * - \e FALSE otherwise + * \note: a and b must be in the same length + */ +/*****************************************************************************/ + +/* + lba +*/ +/* + input: bit8 lba[8] + if (lba > SAT_TR_LBA_LIMIT - 1) + then returns true + else returns false + (LBA,TL) +*/ +bit32 satCompareLBALimitbit(bit8 *lba) +{ + bit32 i; + bit8 limit[8]; + + /* limit is 0xF FF FF = 2^28 - 1 */ + limit[0] = 0x0; /* MSB */ + limit[1] = 0x0; + limit[2] = 0x0; + limit[3] = 0x0; + limit[4] = 0xF; + limit[5] = 0xFF; + limit[6] = 0xFF; + limit[7] = 0xFF; /* LSB */ + + //compare lba to limit + for(i=0;i<8;i++) + { + if (lba[i] > limit[i]) + { + TI_DBG5(("satCompareLBALimitbit64: yes at %d\n", i)); + return agTRUE; + } + else if (lba[i] < limit[i]) + { + TI_DBG5(("satCompareLBALimitbit64: no at %d\n", i)); + return agFALSE; + } + else + { + continue; + } + } + + + return agFALSE; + +} +/***************************************************************************** +*! \brief +* Purpose: bitwise set +* +* Parameters: +* data - input output buffer +* index - bit to set +* +* Return: +* none +* +*****************************************************************************/ +GLOBAL void +satBitSet(bit8 *data, bit32 index) +{ + data[index/8] |= (1 << (index%8)); +} + +/***************************************************************************** +*! \brief +* Purpose: bitwise clear +* +* Parameters: +* data - input output buffer +* index - bit to clear +* +* Return: +* none +* +*****************************************************************************/ +GLOBAL void +satBitClear(bit8 *data, bit32 index) +{ + data[index/8] &= ~(1 << (index%8)); +} + +/***************************************************************************** +*! \brief +* Purpose: bitwise test +* +* Parameters: +* data - input output buffer +* index - bit to test +* +* Return: +* 0 - not set +* 1 - set +* +*****************************************************************************/ +GLOBAL agBOOLEAN +satBitTest(bit8 *data, bit32 index) +{ + return ( (BOOLEAN)((data[index/8] & (1 << (index%8)) ) ? 1: 0)); +} + + +/******************************************************************************/ +/*! \brief allocate an available SATA tag + * + * allocate an available SATA tag + * + * \param tiRoot Pointer to TISA initiator driver/port instance. + * \param pSatDevData + * \param pTag + * + * \return -Success or fail- + */ +/*******************************************************************************/ +GLOBAL bit32 satTagAlloc( + tiRoot_t *tiRoot, + satDeviceData_t *pSatDevData, + bit8 *pTag + ) +{ + bit32 retCode = agFALSE; + bit32 i; + + tdsaSingleThreadedEnter(tiRoot, TD_SATA_LOCK); + for ( i = 0; i < pSatDevData->satNCQMaxIO; i ++ ) + { + if ( 0 == satBitTest((bit8 *)&pSatDevData->freeSATAFDMATagBitmap, i) ) + { + satBitSet((bit8*)&pSatDevData->freeSATAFDMATagBitmap, i); + *pTag = (bit8) i; + retCode = agTRUE; + break; + } + } + tdsaSingleThreadedLeave(tiRoot, TD_SATA_LOCK); + return retCode; +} + +/******************************************************************************/ +/*! \brief release an SATA tag + * + * release an available SATA tag + * + * \param tiRoot Pointer to TISA initiator driver/port instance. + * \param pSatDevData + * \param Tag + * + * \return -the tag- + */ +/*******************************************************************************/ +GLOBAL bit32 satTagRelease( + tiRoot_t *tiRoot, + satDeviceData_t *pSatDevData, + bit8 tag + ) +{ + bit32 retCode = agFALSE; + + tdsaSingleThreadedEnter(tiRoot, TD_SATA_LOCK); + if ( tag < pSatDevData->satNCQMaxIO ) + { + satBitClear( (bit8 *)&pSatDevData->freeSATAFDMATagBitmap, (bit32)tag); + retCode = agTRUE; + } + tdsaSingleThreadedLeave(tiRoot, TD_SATA_LOCK); + return retCode; +} + +/***************************************************************************** + *! \brief satSubTM + * + * This routine is called to initiate a TM request to SATL. + * This routine is independent of HW/LL API. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param task: SAM-3 task management request. + * \param lun: Pointer to LUN. + * \param taskTag: Pointer to the associated task where the TM + * command is to be applied. + * \param currentTaskTag: Pointer to tag/context for this TM request. + * \param NotifyOS flag determines whether notify OS layer or not + * + * \return: + * + * \e tiSuccess: I/O request successfully initiated. + * \e tiBusy: No resources available, try again later. + * \e tiIONoDevice: Invalid device handle. + * \e tiError: Other errors that prevent the I/O request to be started. + * + * \note: + * This funcion is triggered bottom up. Not yet in use. + *****************************************************************************/ +/* called for bottom up */ +osGLOBAL bit32 satSubTM( + tiRoot_t *tiRoot, + tiDeviceHandle_t *tiDeviceHandle, + bit32 task, + tiLUN_t *lun, + tiIORequest_t *taskTag, + tiIORequest_t *currentTaskTag, + bit32 NotifyOS + ) +{ + void *osMemHandle; + tdIORequestBody_t *TMtdIORequestBody; + bit32 PhysUpper32; + bit32 PhysLower32; + bit32 memAllocStatus; + agsaIORequest_t *agIORequest = agNULL; + + TI_DBG6(("satSubTM: start\n")); + + /* allocation tdIORequestBody and pass it to satTM() */ + memAllocStatus = ostiAllocMemory( + tiRoot, + &osMemHandle, + (void **)&TMtdIORequestBody, + &PhysUpper32, + &PhysLower32, + 8, + sizeof(tdIORequestBody_t), + agTRUE + ); + + if (memAllocStatus != tiSuccess) + { + TI_DBG1(("satSubTM: ostiAllocMemory failed... \n")); + return tiError; + } + + if (TMtdIORequestBody == agNULL) + { + TI_DBG1(("satSubTM: ostiAllocMemory returned NULL TMIORequestBody\n")); + return tiError; + } + + /* setup task management structure */ + TMtdIORequestBody->IOType.InitiatorTMIO.osMemHandle = osMemHandle; + TMtdIORequestBody->IOType.InitiatorTMIO.CurrentTaskTag = agNULL; + TMtdIORequestBody->IOType.InitiatorTMIO.TaskTag = agNULL; + + /* initialize tiDevhandle */ + TMtdIORequestBody->tiDevHandle = tiDeviceHandle; + + /* initialize tiIORequest */ + TMtdIORequestBody->tiIORequest = agNULL; + + /* initialize agIORequest */ + agIORequest = &(TMtdIORequestBody->agIORequest); + agIORequest->osData = (void *) TMtdIORequestBody; + agIORequest->sdkData = agNULL; /* SA takes care of this */ + satTM(tiRoot, + tiDeviceHandle, + task, /* TD_INTERNAL_TM_RESET */ + agNULL, + agNULL, + agNULL, + TMtdIORequestBody, + agFALSE); + + return tiSuccess; +} + + +/*****************************************************************************/ +/*! \brief SAT implementation for satStartResetDevice. + * + * SAT implementation for sending SRT and send FIS request to LL layer. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + * \note : triggerred by OS layer or bottom up + */ +/*****************************************************************************/ +/* OS triggerred or bottom up */ +GLOBAL bit32 +satStartResetDevice( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, /* currentTaskTag */ + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, /* should be NULL */ + satIOContext_t *satIOContext + ) +{ + satInternalIo_t *satIntIo = agNULL; + satDeviceData_t *satDevData = agNULL; + satIOContext_t *satNewIOContext; + bit32 status; + tiIORequest_t *currentTaskTag = agNULL; + + TI_DBG1(("satStartResetDevice: start\n")); + + currentTaskTag = tiIORequest; + + satDevData = satIOContext->pSatDevData; + + TI_DBG6(("satStartResetDevice: before alloc\n")); + + /* allocate any fis for seting SRT bit in device control */ + satIntIo = satAllocIntIoResource( tiRoot, + tiIORequest, + satDevData, + 0, + satIntIo); + + TI_DBG6(("satStartResetDevice: before after\n")); + + if (satIntIo == agNULL) + { + TI_DBG1(("satStartResetDevice: can't alloacate\n")); + if (satIOContext->NotifyOS) + { + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMFailed, + currentTaskTag ); + } + return tiError; + } + + satNewIOContext = satPrepareNewIO(satIntIo, + tiIORequest, + satDevData, + agNULL, + satIOContext); + + TI_DBG6(("satStartResetDevice: OS satIOContext %p \n", satIOContext)); + TI_DBG6(("satStartResetDevice: TD satNewIOContext %p \n", satNewIOContext)); + TI_DBG6(("satStartResetDevice: OS tiScsiXchg %p \n", satIOContext->tiScsiXchg)); + TI_DBG6(("satStartResetDevice: TD tiScsiXchg %p \n", satNewIOContext->tiScsiXchg)); + + + + TI_DBG6(("satStartResetDevice: satNewIOContext %p \n", satNewIOContext)); + + if (satDevData->satDeviceType == SATA_ATAPI_DEVICE) + { + status = satDeviceReset(tiRoot, + &satIntIo->satIntTiIORequest, /* New tiIORequest */ + tiDeviceHandle, + satNewIOContext->tiScsiXchg, /* New tiScsiInitiatorRequest_t *tiScsiRequest, */ + satNewIOContext); + } + else + { + status = satResetDevice(tiRoot, + &satIntIo->satIntTiIORequest, /* New tiIORequest */ + tiDeviceHandle, + satNewIOContext->tiScsiXchg, /* New tiScsiInitiatorRequest_t *tiScsiRequest, */ + satNewIOContext); + } + + if (status != tiSuccess) + { + TI_DBG1(("satStartResetDevice: failed in sending\n")); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + if (satIOContext->NotifyOS) + { + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMFailed, + currentTaskTag ); + } + + return tiError; + } + + + TI_DBG6(("satStartResetDevice: end\n")); + + return status; +} + +/*****************************************************************************/ +/*! \brief SAT implementation for satResetDevice. + * + * SAT implementation for building SRT FIS and sends the request to LL layer. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ + +/* + create any fis and set SRST bit in device control +*/ +GLOBAL bit32 +satResetDevice( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext + ) +{ + bit32 status; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; +#ifdef TD_DEBUG_ENABLE + tdIORequestBody_t *tdIORequestBody; + satInternalIo_t *satIntIoContext; +#endif + + fis = satIOContext->pFis; + + TI_DBG2(("satResetDevice: start\n")); + +#ifdef TD_DEBUG_ENABLE + satIntIoContext = satIOContext->satIntIoContext; + tdIORequestBody = satIntIoContext->satIntRequestBody; +#endif + TI_DBG5(("satResetDevice: satIOContext %p tdIORequestBody %p\n", satIOContext, tdIORequestBody)); + /* any fis should work */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0; /* C Bit is not set */ + fis->h.command = 0; /* any command */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.device = 0; /* FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0x4; /* SRST bit is set */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_SRST_ASSERT; + + satIOContext->satCompleteCB = &satResetDeviceCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + +#ifdef TD_INTERNAL_DEBUG + tdhexdump("satResetDevice", (bit8 *)satIOContext->pFis, sizeof(agsaFisRegHostToDevice_t)); +#ifdef TD_DEBUG_ENABLE + tdhexdump("satResetDevice LL", (bit8 *)&(tdIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev), sizeof(agsaFisRegHostToDevice_t)); +#endif +#endif + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + TI_DBG6(("satResetDevice: end status %d\n", status)); + return status; +} + +/***************************************************************************** +*! \brief satResetDeviceCB +* +* This routine is a callback function called from ossaSATACompleted(). +* This CB routine deals with SRT completion. This function send DSRT +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +GLOBAL void satResetDeviceCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ) +{ + /* callback for satResetDevice */ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdIORequestBody; + tdIORequestBody_t *tdOrgIORequestBody; + satIOContext_t *satIOContext; + satIOContext_t *satOrgIOContext; + satIOContext_t *satNewIOContext; + satInternalIo_t *satIntIo; + satInternalIo_t *satNewIntIo = agNULL; + satDeviceData_t *satDevData; + tiIORequest_t *tiOrgIORequest; +#ifdef TD_DEBUG_ENABLE + bit32 ataStatus = 0; + bit32 ataError; + agsaFisPioSetupHeader_t *satPIOSetupHeader = agNULL; +#endif + bit32 status; + + TI_DBG1(("satResetDeviceCB: start\n")); + TI_DBG6(("satResetDeviceCB: agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satIOContext = (satIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + satDevData = satIOContext->pSatDevData; + if (satIntIo == agNULL) + { + TI_DBG6(("satResetDeviceCB: External, OS generated\n")); + satOrgIOContext = satIOContext; + tiOrgIORequest = tdIORequestBody->tiIORequest; + } + else + { + TI_DBG6(("satResetDeviceCB: Internal, TD generated\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + TI_DBG6(("satResetDeviceCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + TI_DBG6(("satResetDeviceCB: satOrgIOContext is NOT NULL\n")); + } + tdOrgIORequestBody = (tdIORequestBody_t *)satOrgIOContext->tiRequestBody; + tiOrgIORequest = (tiIORequest_t *)tdOrgIORequestBody->tiIORequest; + } + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satResetDeviceCB: wrong. agFirstDword is NULL when error, status %d\n", agIOStatus)); + if (satOrgIOContext->NotifyOS == agTRUE) + { + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMFailed, + tiOrgIORequest ); + } + + satDevData->satTmTaskTag = agNULL; + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + if (agIOStatus == OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_BREAK || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_UNKNOWN_ERROR || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY + ) + { + TI_DBG1(("satResetDeviceCB: OSSA_IO_OPEN_CNX_ERROR\n")); + + if (satOrgIOContext->NotifyOS == agTRUE) + { + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMFailed, + tiOrgIORequest ); + } + + satDevData->satTmTaskTag = agNULL; + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + if (agIOStatus != OSSA_IO_SUCCESS) + { +#ifdef TD_DEBUG_ENABLE + /* only agsaFisPioSetup_t is expected */ + satPIOSetupHeader = (agsaFisPioSetupHeader_t *)&(agFirstDword->PioSetup); + ataStatus = satPIOSetupHeader->status; /* ATA Status register */ + ataError = satPIOSetupHeader->error; /* ATA Eror register */ +#endif + TI_DBG1(("satResetDeviceCB: ataStatus 0x%x ataError 0x%x\n", ataStatus, ataError)); + + if (satOrgIOContext->NotifyOS == agTRUE) + { + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMFailed, + tiOrgIORequest ); + } + + satDevData->satTmTaskTag = agNULL; + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + /* success */ + + satNewIntIo = satAllocIntIoResource( tiRoot, + tiOrgIORequest, + satDevData, + 0, + satNewIntIo); + if (satNewIntIo == agNULL) + { + satDevData->satTmTaskTag = agNULL; + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + /* memory allocation failure */ + satFreeIntIoResource( tiRoot, + satDevData, + satNewIntIo); + + if (satOrgIOContext->NotifyOS == agTRUE) + { + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMFailed, + tiOrgIORequest ); + } + + + TI_DBG1(("satResetDeviceCB: momory allocation fails\n")); + return; + } /* end of memory allocation failure */ + + /* + * Need to initialize all the fields within satIOContext + */ + + satNewIOContext = satPrepareNewIO( + satNewIntIo, + tiOrgIORequest, + satDevData, + agNULL, + satOrgIOContext + ); + + + + + /* send AGSA_SATA_PROTOCOL_SRST_DEASSERT */ + status = satDeResetDevice(tiRoot, + tiOrgIORequest, + satOrgIOContext->ptiDeviceHandle, + agNULL, + satNewIOContext + ); + + if (status != tiSuccess) + { + if (satOrgIOContext->NotifyOS == agTRUE) + { + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMFailed, + tiOrgIORequest ); + } + + /* sending AGSA_SATA_PROTOCOL_SRST_DEASSERT fails */ + + satDevData->satTmTaskTag = agNULL; + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satNewIntIo); + return; + + } + + satDevData->satTmTaskTag = agNULL; + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + TI_DBG5(("satResetDeviceCB: device %p pending IO %d\n", satDevData, satDevData->satPendingIO)); + TI_DBG6(("satResetDeviceCB: end\n")); + return; + +} + + +/*****************************************************************************/ +/*! \brief SAT implementation for satDeResetDevice. + * + * SAT implementation for building DSRT FIS and sends the request to LL layer. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satDeResetDevice( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext + ) +{ + bit32 status; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; +#ifdef TD_DEBUG_ENABLE + tdIORequestBody_t *tdIORequestBody; + satInternalIo_t *satIntIoContext; +#endif + fis = satIOContext->pFis; + + TI_DBG6(("satDeResetDevice: start\n")); + +#ifdef TD_DEBUG_ENABLE + satIntIoContext = satIOContext->satIntIoContext; + tdIORequestBody = satIntIoContext->satIntRequestBody; + TI_DBG5(("satDeResetDevice: satIOContext %p tdIORequestBody %p\n", satIOContext, tdIORequestBody)); +#endif + /* any fis should work */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0; /* C Bit is not set */ + fis->h.command = 0; /* any command */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.device = 0; /* FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* SRST bit is not set */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_SRST_DEASSERT; + + satIOContext->satCompleteCB = &satDeResetDeviceCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + +#ifdef TD_INTERNAL_DEBUG + tdhexdump("satDeResetDevice", (bit8 *)satIOContext->pFis, sizeof(agsaFisRegHostToDevice_t)); +#ifdef TD_DEBUG_ENABLE + tdhexdump("satDeResetDevice LL", (bit8 *)&(tdIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev), sizeof(agsaFisRegHostToDevice_t)); +#endif +#endif + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + TI_DBG6(("satDeResetDevice: end status %d\n", status)); + return status; + +} + +/***************************************************************************** +*! \brief satDeResetDeviceCB +* +* This routine is a callback function called from ossaSATACompleted(). +* This CB routine deals with DSRT completion. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +GLOBAL void satDeResetDeviceCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ) +{ + /* callback for satDeResetDevice */ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdIORequestBody; + tdIORequestBody_t *tdOrgIORequestBody = agNULL; + satIOContext_t *satIOContext; + satIOContext_t *satOrgIOContext; + satInternalIo_t *satIntIo; + satDeviceData_t *satDevData; + tiIORequest_t *tiOrgIORequest; +#ifdef TD_DEBUG_ENABLE + bit32 ataStatus = 0; + bit32 ataError; + agsaFisPioSetupHeader_t *satPIOSetupHeader = agNULL; +#endif + bit32 report = agFALSE; + bit32 AbortTM = agFALSE; + + TI_DBG1(("satDeResetDeviceCB: start\n")); + TI_DBG6(("satDeResetDeviceCB: agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satIOContext = (satIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + satDevData = satIOContext->pSatDevData; + if (satIntIo == agNULL) + { + TI_DBG6(("satDeResetDeviceCB: External, OS generated\n")); + satOrgIOContext = satIOContext; + tiOrgIORequest = tdIORequestBody->tiIORequest; + } + else + { + TI_DBG6(("satDeResetDeviceCB: Internal, TD generated\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + TI_DBG6(("satDeResetDeviceCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + TI_DBG6(("satDeResetDeviceCB: satOrgIOContext is NOT NULL\n")); + } + tdOrgIORequestBody = (tdIORequestBody_t *)satOrgIOContext->tiRequestBody; + tiOrgIORequest = (tiIORequest_t *)tdOrgIORequestBody->tiIORequest; + } + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satDeResetDeviceCB: wrong. agFirstDword is NULL when error, status %d\n", agIOStatus)); + if (satOrgIOContext->NotifyOS == agTRUE) + { + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMFailed, + tiOrgIORequest ); + } + + satDevData->satTmTaskTag = agNULL; + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + if (agIOStatus == OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_BREAK || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_UNKNOWN_ERROR || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY + ) + { + TI_DBG1(("satDeResetDeviceCB: OSSA_IO_OPEN_CNX_ERROR\n")); + + if (satOrgIOContext->NotifyOS == agTRUE) + { + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMFailed, + tiOrgIORequest ); + } + + satDevData->satTmTaskTag = agNULL; + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + if (agIOStatus != OSSA_IO_SUCCESS) + { +#ifdef TD_DEBUG_ENABLE + /* only agsaFisPioSetup_t is expected */ + satPIOSetupHeader = (agsaFisPioSetupHeader_t *)&(agFirstDword->PioSetup); + ataStatus = satPIOSetupHeader->status; /* ATA Status register */ + ataError = satPIOSetupHeader->error; /* ATA Eror register */ +#endif + TI_DBG1(("satDeResetDeviceCB: ataStatus 0x%x ataError 0x%x\n", ataStatus, ataError)); + + if (satOrgIOContext->NotifyOS == agTRUE) + { + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMFailed, + tiOrgIORequest ); + } + + satDevData->satTmTaskTag = agNULL; + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + /* success */ + TI_DBG1(("satDeResetDeviceCB: success \n")); + TI_DBG1(("satDeResetDeviceCB: TMF %d\n", satOrgIOContext->TMF)); + + if (satOrgIOContext->TMF == AG_ABORT_TASK) + { + AbortTM = agTRUE; + } + + if (satOrgIOContext->NotifyOS == agTRUE) + { + report = agTRUE; + } + + if (AbortTM == agTRUE) + { + TI_DBG1(("satDeResetDeviceCB: calling satAbort\n")); + satAbort(agRoot, satOrgIOContext->satToBeAbortedIOContext); + } + satDevData->satTmTaskTag = agNULL; + + satDevData->satDriveState = SAT_DEV_STATE_NORMAL; + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + TI_DBG1(("satDeResetDeviceCB: satPendingIO %d satNCQMaxIO %d\n", satDevData->satPendingIO, satDevData->satNCQMaxIO )); + TI_DBG1(("satDeResetDeviceCB: satPendingNCQIO %d satPendingNONNCQIO %d\n", satDevData->satPendingNCQIO, satDevData->satPendingNONNCQIO)); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + /* clean up TD layer's IORequestBody */ + if (tdOrgIORequestBody != agNULL) + { + ostiFreeMemory( + tiRoot, + tdOrgIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + else + { + TI_DBG1(("satDeResetDeviceCB: tdOrgIORequestBody is NULL, wrong\n")); + } + + + if (report) + { + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMOK, + tiOrgIORequest ); + } + + + TI_DBG5(("satDeResetDeviceCB: device %p pending IO %d\n", satDevData, satDevData->satPendingIO)); + TI_DBG6(("satDeResetDeviceCB: end\n")); + return; + +} + +/*****************************************************************************/ +/*! \brief SAT implementation for satStartCheckPowerMode. + * + * SAT implementation for abort task management for non-ncq sata disk. + * This function sends CHECK POWER MODE + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satStartCheckPowerMode( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, /* NULL */ + satIOContext_t *satIOContext + ) +{ + satInternalIo_t *satIntIo = agNULL; + satDeviceData_t *satDevData = agNULL; + satIOContext_t *satNewIOContext; + bit32 status; + tiIORequest_t *currentTaskTag = agNULL; + + TI_DBG6(("satStartCheckPowerMode: start\n")); + + currentTaskTag = tiIORequest; + + satDevData = satIOContext->pSatDevData; + + TI_DBG6(("satStartCheckPowerMode: before alloc\n")); + + /* allocate any fis for seting SRT bit in device control */ + satIntIo = satAllocIntIoResource( tiRoot, + tiIORequest, + satDevData, + 0, + satIntIo); + + TI_DBG6(("satStartCheckPowerMode: before after\n")); + + if (satIntIo == agNULL) + { + TI_DBG1(("satStartCheckPowerMode: can't alloacate\n")); + if (satIOContext->NotifyOS) + { + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMFailed, + currentTaskTag ); + } + return tiError; + } + + satNewIOContext = satPrepareNewIO(satIntIo, + tiIORequest, + satDevData, + agNULL, + satIOContext); + + TI_DBG6(("satStartCheckPowerMode: OS satIOContext %p \n", satIOContext)); + TI_DBG6(("satStartCheckPowerMode: TD satNewIOContext %p \n", satNewIOContext)); + TI_DBG6(("satStartCheckPowerMode: OS tiScsiXchg %p \n", satIOContext->tiScsiXchg)); + TI_DBG6(("satStartCheckPowerMode: TD tiScsiXchg %p \n", satNewIOContext->tiScsiXchg)); + + + + TI_DBG1(("satStartCheckPowerMode: satNewIOContext %p \n", satNewIOContext)); + + status = satCheckPowerMode(tiRoot, + &satIntIo->satIntTiIORequest, /* New tiIORequest */ + tiDeviceHandle, + satNewIOContext->tiScsiXchg, /* New tiScsiInitiatorRequest_t *tiScsiRequest, */ + satNewIOContext); + + if (status != tiSuccess) + { + TI_DBG1(("satStartCheckPowerMode: failed in sending\n")); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + if (satIOContext->NotifyOS) + { + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMFailed, + currentTaskTag ); + } + + return tiError; + } + + + TI_DBG6(("satStartCheckPowerMode: end\n")); + + return status; +} + +/*****************************************************************************/ +/*! \brief SAT implementation for satCheckPowerMode. + * + * This function creates CHECK POWER MODE fis and sends the request to LL layer + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satCheckPowerMode( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext + ) +{ + /* + sends SAT_CHECK_POWER_MODE as a part of ABORT TASKMANGEMENT for NCQ commands + internally generated - no directly corresponding scsi + */ + bit32 status; + bit32 agRequestType; + agsaFisRegHostToDevice_t *fis; + + fis = satIOContext->pFis; + TI_DBG5(("satCheckPowerMode: start\n")); + /* + * Send the ATA CHECK POWER MODE command. + */ + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + fis->h.command = SAT_CHECK_POWER_MODE; /* 0xE5 */ + fis->h.features = 0; + fis->d.lbaLow = 0; + fis->d.lbaMid = 0; + fis->d.lbaHigh = 0; + fis->d.device = 0; + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_NON_DATA; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satCheckPowerModeCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + TI_DBG5(("satCheckPowerMode: return\n")); + + return status; +} + +/***************************************************************************** +*! \brief satCheckPowerModeCB +* +* This routine is a callback function called from ossaSATACompleted(). +* This CB routine deals with CHECK POWER MODE completion as abort task +* management. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +GLOBAL void satCheckPowerModeCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ) +{ + /* callback for satDeResetDevice */ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdIORequestBody; + tdIORequestBody_t *tdOrgIORequestBody = agNULL; + satIOContext_t *satIOContext; + satIOContext_t *satOrgIOContext; + satInternalIo_t *satIntIo; + satDeviceData_t *satDevData; + + tiIORequest_t *tiOrgIORequest; +#ifdef TD_DEBUG_ENABLE + bit32 ataStatus = 0; + bit32 ataError; + agsaFisPioSetupHeader_t *satPIOSetupHeader = agNULL; +#endif + bit32 report = agFALSE; + bit32 AbortTM = agFALSE; + + + TI_DBG1(("satCheckPowerModeCB: start\n")); + + TI_DBG1(("satCheckPowerModeCB: agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satIOContext = (satIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + satDevData = satIOContext->pSatDevData; + if (satIntIo == agNULL) + { + TI_DBG6(("satCheckPowerModeCB: External, OS generated\n")); + satOrgIOContext = satIOContext; + tiOrgIORequest = tdIORequestBody->tiIORequest; + } + else + { + TI_DBG6(("satCheckPowerModeCB: Internal, TD generated\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + TI_DBG6(("satCheckPowerModeCB: satOrgIOContext is NULL, wrong\n")); + return; + } + else + { + TI_DBG6(("satCheckPowerModeCB: satOrgIOContext is NOT NULL\n")); + } + tdOrgIORequestBody = (tdIORequestBody_t *)satOrgIOContext->tiRequestBody; + tiOrgIORequest = (tiIORequest_t *)tdOrgIORequestBody->tiIORequest; + } + + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satCheckPowerModeCB: wrong. agFirstDword is NULL when error, status %d\n", agIOStatus)); + + if (satOrgIOContext->NotifyOS == agTRUE) + { + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMFailed, + tiOrgIORequest ); + } + + satDevData->satTmTaskTag = agNULL; + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + if (agIOStatus == OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_BREAK || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_UNKNOWN_ERROR || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY + ) + { + TI_DBG1(("satCheckPowerModeCB: OSSA_IO_OPEN_CNX_ERROR\n")); + + if (satOrgIOContext->NotifyOS == agTRUE) + { + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMFailed, + tiOrgIORequest ); + } + + satDevData->satTmTaskTag = agNULL; + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + if (agIOStatus != OSSA_IO_SUCCESS) + { +#ifdef TD_DEBUG_ENABLE + /* only agsaFisPioSetup_t is expected */ + satPIOSetupHeader = (agsaFisPioSetupHeader_t *)&(agFirstDword->PioSetup); + ataStatus = satPIOSetupHeader->status; /* ATA Status register */ + ataError = satPIOSetupHeader->error; /* ATA Eror register */ +#endif + TI_DBG1(("satCheckPowerModeCB: ataStatus 0x%x ataError 0x%x\n", ataStatus, ataError)); + + if (satOrgIOContext->NotifyOS == agTRUE) + { + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMFailed, + tiOrgIORequest ); + } + + satDevData->satTmTaskTag = agNULL; + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + return; + } + + /* success */ + TI_DBG1(("satCheckPowerModeCB: success\n")); + TI_DBG1(("satCheckPowerModeCB: TMF %d\n", satOrgIOContext->TMF)); + + if (satOrgIOContext->TMF == AG_ABORT_TASK) + { + AbortTM = agTRUE; + } + + if (satOrgIOContext->NotifyOS == agTRUE) + { + report = agTRUE; + } + if (AbortTM == agTRUE) + { + TI_DBG1(("satCheckPowerModeCB: calling satAbort\n")); + satAbort(agRoot, satOrgIOContext->satToBeAbortedIOContext); + } + satDevData->satTmTaskTag = agNULL; + + satDevData->satDriveState = SAT_DEV_STATE_NORMAL; + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + TI_DBG1(("satCheckPowerModeCB: satPendingIO %d satNCQMaxIO %d\n", satDevData->satPendingIO, satDevData->satNCQMaxIO )); + TI_DBG1(("satCheckPowerModeCB: satPendingNCQIO %d satPendingNONNCQIO %d\n", satDevData->satPendingNCQIO, satDevData->satPendingNONNCQIO)); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + /* clean up TD layer's IORequestBody */ + if (tdOrgIORequestBody != agNULL) + { + ostiFreeMemory( + tiRoot, + tdOrgIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + else + { + TI_DBG1(("satCheckPowerModeCB: tdOrgIORequestBody is NULL, wrong\n")); + } + if (report) + { + ostiInitiatorEvent( tiRoot, + NULL, + NULL, + tiIntrEventTypeTaskManagement, + tiTMOK, + tiOrgIORequest ); + } + + TI_DBG5(("satCheckPowerModeCB: device %p pending IO %d\n", satDevData, satDevData->satPendingIO)); + TI_DBG2(("satCheckPowerModeCB: end\n")); + return; + +} + +/*****************************************************************************/ +/*! \brief SAT implementation for satAddSATAStartIDDev. + * + * This function sends identify device data to find out the uniqueness + * of device. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satAddSATAStartIDDev( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, // NULL + satIOContext_t *satIOContext + ) +{ + satInternalIo_t *satIntIo = agNULL; + satDeviceData_t *satDevData = agNULL; + tdIORequestBody_t *tdIORequestBody; + satIOContext_t *satNewIOContext; + bit32 status; + + TI_DBG2(("satAddSATAStartIDDev: start\n")); + + satDevData = satIOContext->pSatDevData; + + TI_DBG2(("satAddSATAStartIDDev: before alloc\n")); + + /* allocate identify device command */ + satIntIo = satAllocIntIoResource( tiRoot, + tiIORequest, + satDevData, + sizeof(agsaSATAIdentifyData_t), /* 512; size of identify device data */ + satIntIo); + + TI_DBG2(("satAddSATAStartIDDev: after alloc\n")); + + if (satIntIo == agNULL) + { + TI_DBG1(("satAddSATAStartIDDev: can't alloacate\n")); + + return tiError; + } + + /* fill in fields */ + /* real ttttttthe one worked and the same; 5/21/07/ */ + satIntIo->satOrgTiIORequest = tiIORequest; /* changed */ + tdIORequestBody = satIntIo->satIntRequestBody; + satNewIOContext = &(tdIORequestBody->transport.SATA.satIOContext); + + satNewIOContext->pSatDevData = satDevData; + satNewIOContext->pFis = &(tdIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev); + satNewIOContext->pScsiCmnd = &(satIntIo->satIntTiScsiXchg.scsiCmnd); + satNewIOContext->pSense = &(tdIORequestBody->transport.SATA.sensePayload); + satNewIOContext->pTiSenseData = &(tdIORequestBody->transport.SATA.tiSenseData); + satNewIOContext->tiRequestBody = satIntIo->satIntRequestBody; /* key fix */ + satNewIOContext->interruptContext = tiInterruptContext; + satNewIOContext->satIntIoContext = satIntIo; + + satNewIOContext->ptiDeviceHandle = agNULL; + satNewIOContext->satOrgIOContext = satIOContext; /* changed */ + + /* this is valid only for TD layer generated (not triggered by OS at all) IO */ + satNewIOContext->tiScsiXchg = &(satIntIo->satIntTiScsiXchg); + + + TI_DBG6(("satAddSATAStartIDDev: OS satIOContext %p \n", satIOContext)); + TI_DBG6(("satAddSATAStartIDDev: TD satNewIOContext %p \n", satNewIOContext)); + TI_DBG6(("satAddSATAStartIDDev: OS tiScsiXchg %p \n", satIOContext->tiScsiXchg)); + TI_DBG6(("satAddSATAStartIDDev: TD tiScsiXchg %p \n", satNewIOContext->tiScsiXchg)); + + + + TI_DBG2(("satAddSATAStartIDDev: satNewIOContext %p tdIORequestBody %p\n", satNewIOContext, tdIORequestBody)); + + status = satAddSATASendIDDev( tiRoot, + &satIntIo->satIntTiIORequest, /* New tiIORequest */ + tiDeviceHandle, + satNewIOContext->tiScsiXchg, /* New tiScsiInitiatorRequest_t *tiScsiRequest, */ + satNewIOContext); + + if (status != tiSuccess) + { + TI_DBG1(("satAddSATAStartIDDev: failed in sending\n")); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + return tiError; + } + + + TI_DBG6(("satAddSATAStartIDDev: end\n")); + + return status; + + +} + +/*****************************************************************************/ +/*! \brief SAT implementation for satAddSATASendIDDev. + * + * This function creates identify device data fis and send it to LL + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satAddSATASendIDDev( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext) +{ + bit32 status; + bit32 agRequestType; + satDeviceData_t *pSatDevData; + agsaFisRegHostToDevice_t *fis; +#ifdef TD_DEBUG_ENABLE + tdIORequestBody_t *tdIORequestBody; + satInternalIo_t *satIntIoContext; +#endif + + pSatDevData = satIOContext->pSatDevData; + fis = satIOContext->pFis; + TI_DBG2(("satAddSATASendIDDev: start\n")); +#ifdef TD_DEBUG_ENABLE + satIntIoContext = satIOContext->satIntIoContext; + tdIORequestBody = satIntIoContext->satIntRequestBody; +#endif + TI_DBG5(("satAddSATASendIDDev: satIOContext %p tdIORequestBody %p\n", satIOContext, tdIORequestBody)); + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + if (pSatDevData->satDeviceType == SATA_ATAPI_DEVICE) + fis->h.command = SAT_IDENTIFY_PACKET_DEVICE; /* 0x40 */ + else + fis->h.command = SAT_IDENTIFY_DEVICE; /* 0xEC */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.device = 0; /* FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &satAddSATAIDDevCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + +#ifdef TD_INTERNAL_DEBUG + tdhexdump("satAddSATASendIDDev", (bit8 *)satIOContext->pFis, sizeof(agsaFisRegHostToDevice_t)); +#ifdef TD_DEBUG_ENABLE + tdhexdump("satAddSATASendIDDev LL", (bit8 *)&(tdIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev), sizeof(agsaFisRegHostToDevice_t)); +#endif +#endif + + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + + TI_DBG2(("satAddSATASendIDDev: end status %d\n", status)); + return status; +} + +/***************************************************************************** +*! \brief satAddSATAIDDevCB +* +* This routine is a callback function for satAddSATASendIDDev() +* Using Identify Device Data, this function finds whether devicedata is +* new or old. If new, add it to the devicelist. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void satAddSATAIDDevCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + + /* + In the process of Inquiry + Process SAT_IDENTIFY_DEVICE + */ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdIORequestBody; + tdIORequestBody_t *tdOrgIORequestBody; + satIOContext_t *satIOContext; + satIOContext_t *satOrgIOContext; + satIOContext_t *satNewIOContext; + satInternalIo_t *satIntIo; + satInternalIo_t *satNewIntIo = agNULL; + satDeviceData_t *satDevData; + tiIORequest_t *tiOrgIORequest = agNULL; + agsaSATAIdentifyData_t *pSATAIdData; + bit16 *tmpptr, tmpptr_tmp; + bit32 x; + tdsaDeviceData_t *NewOneDeviceData = agNULL; + tdsaDeviceData_t *oneDeviceData = agNULL; + tdList_t *DeviceListList; + int new_device = agTRUE; + bit8 PhyID; + void *sglVirtualAddr; + bit32 retry_status; + agsaContext_t *agContext; + tdsaPortContext_t *onePortContext; + bit32 status = 0; + + TI_DBG2(("satAddSATAIDDevCB: start\n")); + TI_DBG6(("satAddSATAIDDevCB: agIORequest=%p agIOStatus=0x%x agIOInfoLen %d\n", agIORequest, agIOStatus, agIOInfoLen)); + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satIOContext = (satIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + satDevData = satIOContext->pSatDevData; + + NewOneDeviceData = (tdsaDeviceData_t *)tdIORequestBody->tiDevHandle->tdData; + TI_DBG2(("satAddSATAIDDevCB: NewOneDeviceData %p did %d\n", NewOneDeviceData, NewOneDeviceData->id)); + PhyID = NewOneDeviceData->phyID; + TI_DBG2(("satAddSATAIDDevCB: phyID %d\n", PhyID)); + agContext = &(NewOneDeviceData->agDeviceResetContext); + agContext->osData = agNULL; + if (satIntIo == agNULL) + { + TI_DBG1(("satAddSATAIDDevCB: External, OS generated\n")); + TI_DBG1(("satAddSATAIDDevCB: Not possible case\n")); + satOrgIOContext = satIOContext; + tdOrgIORequestBody = (tdIORequestBody_t *)satOrgIOContext->tiRequestBody; + tdsaAbortAll(tiRoot, agRoot, NewOneDeviceData); + + /* put onedevicedata back to free list */ + osti_memset(&(NewOneDeviceData->satDevData.satIdentifyData), 0xFF, sizeof(agsaSATAIdentifyData_t)); + TDLIST_DEQUEUE_THIS(&(NewOneDeviceData->MainLink)); + TDLIST_ENQUEUE_AT_TAIL(&(NewOneDeviceData->FreeLink), &(tdsaAllShared->FreeDeviceList)); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + /* clean up TD layer's IORequestBody */ + ostiFreeMemory( + tiRoot, + tdOrgIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + + /* notifying link up */ + ostiPortEvent ( + tiRoot, + tiPortLinkUp, + tiSuccess, + (void *)tdsaAllShared->Ports[PhyID].tiPortalContext + ); +#ifdef INITIATOR_DRIVER + /* triggers discovery */ + ostiPortEvent( + tiRoot, + tiPortDiscoveryReady, + tiSuccess, + (void *) tdsaAllShared->Ports[PhyID].tiPortalContext + ); +#endif + return; + } + else + { + TI_DBG1(("satAddSATAIDDevCB: Internal, TD generated\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + TI_DBG6(("satAddSATAIDDevCB: satOrgIOContext is NULL\n")); + return; + } + else + { + TI_DBG6(("satAddSATAIDDevCB: satOrgIOContext is NOT NULL\n")); + tdOrgIORequestBody = (tdIORequestBody_t *)satOrgIOContext->tiRequestBody; + sglVirtualAddr = satIntIo->satIntTiScsiXchg.sglVirtualAddr; + } + } + tiOrgIORequest = tdIORequestBody->tiIORequest; + + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + TI_DBG2(("satAddSATAIDDevCB: satOrgIOContext->pid %d\n", satOrgIOContext->pid)); + /* protect against double completion for old port */ + if (satOrgIOContext->pid != tdsaAllShared->Ports[PhyID].portContext->id) + { + TI_DBG2(("satAddSATAIDDevCB: incorrect pid\n")); + TI_DBG2(("satAddSATAIDDevCB: satOrgIOContext->pid %d\n", satOrgIOContext->pid)); + TI_DBG2(("satAddSATAIDDevCB: tiPortalContext pid %d\n", tdsaAllShared->Ports[PhyID].portContext->id)); + tdsaAbortAll(tiRoot, agRoot, NewOneDeviceData); + /* put onedevicedata back to free list */ + osti_memset(&(NewOneDeviceData->satDevData.satIdentifyData), 0xFF, sizeof(agsaSATAIdentifyData_t)); + TDLIST_DEQUEUE_THIS(&(NewOneDeviceData->MainLink)); + TDLIST_ENQUEUE_AT_TAIL(&(NewOneDeviceData->FreeLink), &(tdsaAllShared->FreeDeviceList)); + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + /* clean up TD layer's IORequestBody */ + ostiFreeMemory( + tiRoot, + tdOrgIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + /* no notification to OS layer */ + return; + } + /* completion after portcontext is invalidated */ + onePortContext = NewOneDeviceData->tdPortContext; + if (onePortContext != agNULL) + { + if (onePortContext->valid == agFALSE) + { + TI_DBG1(("satAddSATAIDDevCB: portcontext is invalid\n")); + TI_DBG1(("satAddSATAIDDevCB: onePortContext->id pid %d\n", onePortContext->id)); + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + /* clean up TD layer's IORequestBody */ + ostiFreeMemory( + tiRoot, + tdOrgIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + /* no notification to OS layer */ + return; + } + } + else + { + TI_DBG1(("satAddSATAIDDevCB: onePortContext is NULL!!!\n")); + return; + } + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("satAddSATAIDDevCB: wrong. agFirstDword is NULL when error, status %d\n", agIOStatus)); + if (tdsaAllShared->ResetInDiscovery != 0 && satDevData->ID_Retries < SATA_ID_DEVICE_DATA_RETRIES) + { + satDevData->satPendingNONNCQIO--; + satDevData->satPendingIO--; + retry_status = sataLLIOStart(tiRoot, + &satIntIo->satIntTiIORequest, + &(NewOneDeviceData->tiDeviceHandle), + satIOContext->tiScsiXchg, + satIOContext); + if (retry_status != tiSuccess) + { + /* simply give up */ + satDevData->ID_Retries = 0; + satAddSATAIDDevCBCleanup(agRoot, NewOneDeviceData, satIOContext, tdOrgIORequestBody); + return; + } + satDevData->ID_Retries++; + tdIORequestBody->ioCompleted = agFALSE; + tdIORequestBody->ioStarted = agTRUE; + return; + } + else + { + if (tdsaAllShared->ResetInDiscovery == 0) + { + satAddSATAIDDevCBCleanup(agRoot, NewOneDeviceData, satIOContext, tdOrgIORequestBody); + } + else /* ResetInDiscovery in on */ + { + /* RESET only one after ID retries */ + if (satDevData->NumOfIDRetries <= 0) + { + satDevData->NumOfIDRetries++; + satDevData->ID_Retries = 0; + satAddSATAIDDevCBReset(agRoot, NewOneDeviceData, satIOContext, tdOrgIORequestBody); + /* send link reset */ + saLocalPhyControl(agRoot, + agContext, + tdsaRotateQnumber(tiRoot, NewOneDeviceData), + PhyID, + AGSA_PHY_HARD_RESET, + agNULL); + } + else + { + satDevData->ID_Retries = 0; + satAddSATAIDDevCBCleanup(agRoot, NewOneDeviceData, satIOContext, tdOrgIORequestBody); + } + } + return; + } + } + if (agIOStatus == OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_BREAK || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_UNKNOWN_ERROR || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY + ) + { + TI_DBG1(("satAddSATAIDDevCB: OSSA_IO_OPEN_CNX_ERROR\n")); + if (tdsaAllShared->ResetInDiscovery != 0 && satDevData->ID_Retries < SATA_ID_DEVICE_DATA_RETRIES) + { + satDevData->satPendingNONNCQIO--; + satDevData->satPendingIO--; + retry_status = sataLLIOStart(tiRoot, + &satIntIo->satIntTiIORequest, + &(NewOneDeviceData->tiDeviceHandle), + satIOContext->tiScsiXchg, + satIOContext); + if (retry_status != tiSuccess) + { + /* simply give up */ + satDevData->ID_Retries = 0; + satAddSATAIDDevCBCleanup(agRoot, NewOneDeviceData, satIOContext, tdOrgIORequestBody); + return; + } + satDevData->ID_Retries++; + tdIORequestBody->ioCompleted = agFALSE; + tdIORequestBody->ioStarted = agTRUE; + return; + } + else + { + if (tdsaAllShared->ResetInDiscovery == 0) + { + satAddSATAIDDevCBCleanup(agRoot, NewOneDeviceData, satIOContext, tdOrgIORequestBody); + } + else /* ResetInDiscovery in on */ + { + /* RESET only one after ID retries */ + if (satDevData->NumOfIDRetries <= 0) + { + satDevData->NumOfIDRetries++; + satDevData->ID_Retries = 0; + satAddSATAIDDevCBReset(agRoot, NewOneDeviceData, satIOContext, tdOrgIORequestBody); + /* send link reset */ + saLocalPhyControl(agRoot, + agContext, + tdsaRotateQnumber(tiRoot, NewOneDeviceData), + PhyID, + AGSA_PHY_HARD_RESET, + agNULL); + } + else + { + satDevData->ID_Retries = 0; + satAddSATAIDDevCBCleanup(agRoot, NewOneDeviceData, satIOContext, tdOrgIORequestBody); + } + } + return; + } + } + + if ( agIOStatus != OSSA_IO_SUCCESS || + (agIOStatus == OSSA_IO_SUCCESS && agFirstDword != agNULL && agIOInfoLen != 0) + ) + { + if (tdsaAllShared->ResetInDiscovery != 0 && satDevData->ID_Retries < SATA_ID_DEVICE_DATA_RETRIES) + { + satIOContext->pSatDevData->satPendingNONNCQIO--; + satIOContext->pSatDevData->satPendingIO--; + retry_status = sataLLIOStart(tiRoot, + &satIntIo->satIntTiIORequest, + &(NewOneDeviceData->tiDeviceHandle), + satIOContext->tiScsiXchg, + satIOContext); + if (retry_status != tiSuccess) + { + /* simply give up */ + satDevData->ID_Retries = 0; + satAddSATAIDDevCBCleanup(agRoot, NewOneDeviceData, satIOContext, tdOrgIORequestBody); + return; + } + satDevData->ID_Retries++; + tdIORequestBody->ioCompleted = agFALSE; + tdIORequestBody->ioStarted = agTRUE; + return; + } + else + { + if (tdsaAllShared->ResetInDiscovery == 0) + { + satAddSATAIDDevCBCleanup(agRoot, NewOneDeviceData, satIOContext, tdOrgIORequestBody); + } + else /* ResetInDiscovery in on */ + { + /* RESET only one after ID retries */ + if (satDevData->NumOfIDRetries <= 0) + { + satDevData->NumOfIDRetries++; + satDevData->ID_Retries = 0; + satAddSATAIDDevCBReset(agRoot, NewOneDeviceData, satIOContext, tdOrgIORequestBody); + /* send link reset */ + saLocalPhyControl(agRoot, + agContext, + tdsaRotateQnumber(tiRoot, NewOneDeviceData), + PhyID, + AGSA_PHY_HARD_RESET, + agNULL); + } + else + { + satDevData->ID_Retries = 0; + satAddSATAIDDevCBCleanup(agRoot, NewOneDeviceData, satIOContext, tdOrgIORequestBody); + } + } + return; + } + } + + /* success */ + TI_DBG2(("satAddSATAIDDevCB: Success\n")); + /* Convert to host endian */ + tmpptr = (bit16*)sglVirtualAddr; + //tdhexdump("satAddSATAIDDevCB before", (bit8 *)sglVirtualAddr, sizeof(agsaSATAIdentifyData_t)); + for (x=0; x < sizeof(agsaSATAIdentifyData_t)/sizeof(bit16); x++) + { + OSSA_READ_LE_16(AGROOT, &tmpptr_tmp, tmpptr, 0); + *tmpptr = tmpptr_tmp; + tmpptr++; + /*Print tmpptr_tmp here for debugging purpose*/ + } + + pSATAIdData = (agsaSATAIdentifyData_t *)sglVirtualAddr; + //tdhexdump("satAddSATAIDDevCB after", (bit8 *)pSATAIdData, sizeof(agsaSATAIdentifyData_t)); + + TI_DBG5(("satAddSATAIDDevCB: OS satOrgIOContext %p \n", satOrgIOContext)); + TI_DBG5(("satAddSATAIDDevCB: TD satIOContext %p \n", satIOContext)); + TI_DBG5(("satAddSATAIDDevCB: OS tiScsiXchg %p \n", satOrgIOContext->tiScsiXchg)); + TI_DBG5(("satAddSATAIDDevCB: TD tiScsiXchg %p \n", satIOContext->tiScsiXchg)); + + + /* compare idenitfy device data to the exiting list */ + DeviceListList = tdsaAllShared->MainDeviceList.flink; + while (DeviceListList != &(tdsaAllShared->MainDeviceList)) + { + oneDeviceData = TDLIST_OBJECT_BASE(tdsaDeviceData_t, MainLink, DeviceListList); + TI_DBG1(("satAddSATAIDDevCB: LOOP oneDeviceData %p did %d\n", oneDeviceData, oneDeviceData->id)); + //tdhexdump("satAddSATAIDDevCB LOOP", (bit8 *)&oneDeviceData->satDevData.satIdentifyData, sizeof(agsaSATAIdentifyData_t)); + + /* what is unique ID for sata device -> response of identify devicedata; not really + Let's compare serial number, firmware version, model number + */ + if ( oneDeviceData->DeviceType == TD_SATA_DEVICE && + (osti_memcmp (oneDeviceData->satDevData.satIdentifyData.serialNumber, + pSATAIdData->serialNumber, + 20) == 0) && + (osti_memcmp (oneDeviceData->satDevData.satIdentifyData.firmwareVersion, + pSATAIdData->firmwareVersion, + 8) == 0) && + (osti_memcmp (oneDeviceData->satDevData.satIdentifyData.modelNumber, + pSATAIdData->modelNumber, + 40) == 0) + ) + { + TI_DBG2(("satAddSATAIDDevCB: did %d\n", oneDeviceData->id)); + new_device = agFALSE; + break; + } + DeviceListList = DeviceListList->flink; + } + + if (new_device == agFALSE) + { + TI_DBG2(("satAddSATAIDDevCB: old device data\n")); + oneDeviceData->valid = agTRUE; + oneDeviceData->valid2 = agTRUE; + /* save data field from new device data */ + oneDeviceData->agRoot = agRoot; + oneDeviceData->agDevHandle = NewOneDeviceData->agDevHandle; + oneDeviceData->agDevHandle->osData = oneDeviceData; /* TD layer */ + oneDeviceData->tdPortContext = NewOneDeviceData->tdPortContext; + oneDeviceData->phyID = NewOneDeviceData->phyID; + + /* + one SATA directly attached device per phy; + Therefore, deregister then register + */ + saDeregisterDeviceHandle(agRoot, agNULL, NewOneDeviceData->agDevHandle, 0); + + if (oneDeviceData->registered == agFALSE) + { + TI_DBG2(("satAddSATAIDDevCB: re-registering old device data\n")); + /* already has old information; just register it again */ + saRegisterNewDevice( /* satAddSATAIDDevCB */ + agRoot, + &oneDeviceData->agContext, + tdsaRotateQnumber(tiRoot, oneDeviceData), + &oneDeviceData->agDeviceInfo, + oneDeviceData->tdPortContext->agPortContext, + 0 + ); + } + +// tdsaAbortAll(tiRoot, agRoot, NewOneDeviceData); + /* put onedevicedata back to free list */ + osti_memset(&(NewOneDeviceData->satDevData.satIdentifyData), 0xFF, sizeof(agsaSATAIdentifyData_t)); + TDLIST_DEQUEUE_THIS(&(NewOneDeviceData->MainLink)); + TDLIST_ENQUEUE_AT_TAIL(&(NewOneDeviceData->FreeLink), &(tdsaAllShared->FreeDeviceList)); + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + if (satDevData->satDeviceType == SATA_ATAPI_DEVICE) + { + /* send the Set Feature ATA command to ATAPI device for enbling PIO and DMA transfer mode*/ + satNewIntIo = satAllocIntIoResource( tiRoot, + tiOrgIORequest, + satDevData, + 0, + satNewIntIo); + + if (satNewIntIo == agNULL) + { + TI_DBG1(("tdsaDiscoveryStartIDDevCB: momory allocation fails\n")); + /* clean up TD layer's IORequestBody */ + ostiFreeMemory( + tiRoot, + tdOrgIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; + } /* end memory allocation */ + + satNewIOContext = satPrepareNewIO(satNewIntIo, + tiOrgIORequest, + satDevData, + agNULL, + satOrgIOContext + ); + /* enable PIO mode, then enable Ultra DMA mode in the satSetFeaturesCB callback function*/ + status = satSetFeatures(tiRoot, + &satNewIntIo->satIntTiIORequest, + satNewIOContext->ptiDeviceHandle, + &satNewIntIo->satIntTiScsiXchg, /* orginal from OS layer */ + satNewIOContext, + agFALSE); + if (status != tiSuccess) + { + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + /* clean up TD layer's IORequestBody */ + ostiFreeMemory( + tiRoot, + tdOrgIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + } + else + { + /* clean up TD layer's IORequestBody */ + ostiFreeMemory( + tiRoot, + tdOrgIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + TI_DBG2(("satAddSATAIDDevCB: pid %d\n", tdsaAllShared->Ports[PhyID].portContext->id)); + /* notifying link up */ + ostiPortEvent( + tiRoot, + tiPortLinkUp, + tiSuccess, + (void *)tdsaAllShared->Ports[PhyID].tiPortalContext + ); + + + #ifdef INITIATOR_DRIVER + /* triggers discovery */ + ostiPortEvent( + tiRoot, + tiPortDiscoveryReady, + tiSuccess, + (void *) tdsaAllShared->Ports[PhyID].tiPortalContext + ); + #endif + } + return; + } + + TI_DBG2(("satAddSATAIDDevCB: new device data\n")); + /* copy ID Dev data to satDevData */ + satDevData->satIdentifyData = *pSATAIdData; + + + satDevData->IDDeviceValid = agTRUE; +#ifdef TD_INTERNAL_DEBUG + tdhexdump("satAddSATAIDDevCB ID Dev data",(bit8 *)pSATAIdData, sizeof(agsaSATAIdentifyData_t)); + tdhexdump("satAddSATAIDDevCB Device ID Dev data",(bit8 *)&satDevData->satIdentifyData, sizeof(agsaSATAIdentifyData_t)); +#endif + + /* set satDevData fields from IndentifyData */ + satSetDevInfo(satDevData,pSATAIdData); + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + if (satDevData->satDeviceType == SATA_ATAPI_DEVICE) + { + /* send the Set Feature ATA command to ATAPI device for enbling PIO and DMA transfer mode*/ + satNewIntIo = satAllocIntIoResource( tiRoot, + tiOrgIORequest, + satDevData, + 0, + satNewIntIo); + + if (satNewIntIo == agNULL) + { + TI_DBG1(("tdsaDiscoveryStartIDDevCB: momory allocation fails\n")); + /* clean up TD layer's IORequestBody */ + ostiFreeMemory( + tiRoot, + tdOrgIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; + } /* end memory allocation */ + + satNewIOContext = satPrepareNewIO(satNewIntIo, + tiOrgIORequest, + satDevData, + agNULL, + satOrgIOContext + ); + /* enable PIO mode, then enable Ultra DMA mode in the satSetFeaturesCB callback function*/ + status = satSetFeatures(tiRoot, + &satNewIntIo->satIntTiIORequest, + satNewIOContext->ptiDeviceHandle, + &satNewIntIo->satIntTiScsiXchg, /* orginal from OS layer */ + satNewIOContext, + agFALSE); + if (status != tiSuccess) + { + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + /* clean up TD layer's IORequestBody */ + ostiFreeMemory( + tiRoot, + tdOrgIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + + } + else + { + /* clean up TD layer's IORequestBody */ + ostiFreeMemory( + tiRoot, + tdOrgIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + + TI_DBG2(("satAddSATAIDDevCB: pid %d\n", tdsaAllShared->Ports[PhyID].portContext->id)); + /* notifying link up */ + ostiPortEvent ( + tiRoot, + tiPortLinkUp, + tiSuccess, + (void *)tdsaAllShared->Ports[PhyID].tiPortalContext + ); + #ifdef INITIATOR_DRIVER + /* triggers discovery */ + ostiPortEvent( + tiRoot, + tiPortDiscoveryReady, + tiSuccess, + (void *) tdsaAllShared->Ports[PhyID].tiPortalContext + ); + #endif + } + + TI_DBG2(("satAddSATAIDDevCB: end\n")); + return; + +} + +/***************************************************************************** +*! \brief satAddSATAIDDevCBReset +* +* This routine cleans up IOs for failed Identify device data +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param oneDeviceData: Pointer to the device data. +* \param ioContext: Pointer to satIOContext_t. +* \param tdIORequestBody: Pointer to the request body +* \param flag: Decrement pending io or not +* +* \return: none +* +*****************************************************************************/ +void satAddSATAIDDevCBReset( + agsaRoot_t *agRoot, + tdsaDeviceData_t *oneDeviceData, + satIOContext_t *satIOContext, + tdIORequestBody_t *tdIORequestBody + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + satInternalIo_t *satIntIo; + satDeviceData_t *satDevData; + + TI_DBG2(("satAddSATAIDDevCBReset: start\n")); + satIntIo = satIOContext->satIntIoContext; + satDevData = satIOContext->pSatDevData; + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + /* clean up TD layer's IORequestBody */ + ostiFreeMemory( + tiRoot, + tdIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; +} + + +/***************************************************************************** +*! \brief satAddSATAIDDevCBCleanup +* +* This routine cleans up IOs for failed Identify device data +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param oneDeviceData: Pointer to the device data. +* \param ioContext: Pointer to satIOContext_t. +* \param tdIORequestBody: Pointer to the request body +* +* \return: none +* +*****************************************************************************/ +void satAddSATAIDDevCBCleanup( + agsaRoot_t *agRoot, + tdsaDeviceData_t *oneDeviceData, + satIOContext_t *satIOContext, + tdIORequestBody_t *tdIORequestBody + ) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + satInternalIo_t *satIntIo; + satDeviceData_t *satDevData; + bit8 PhyID; + + TI_DBG2(("satAddSATAIDDevCBCleanup: start\n")); + satIntIo = satIOContext->satIntIoContext; + satDevData = satIOContext->pSatDevData; + PhyID = oneDeviceData->phyID; + tdsaAbortAll(tiRoot, agRoot, oneDeviceData); + /* put onedevicedata back to free list */ + osti_memset(&(oneDeviceData->satDevData.satIdentifyData), 0xFF, sizeof(agsaSATAIdentifyData_t)); + TDLIST_DEQUEUE_THIS(&(oneDeviceData->MainLink)); + TDLIST_ENQUEUE_AT_TAIL(&(oneDeviceData->FreeLink), &(tdsaAllShared->FreeDeviceList)); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + /* clean up TD layer's IORequestBody */ + ostiFreeMemory( + tiRoot, + tdIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + + /* notifying link up */ + ostiPortEvent ( + tiRoot, + tiPortLinkUp, + tiSuccess, + (void *)tdsaAllShared->Ports[PhyID].tiPortalContext + ); +#ifdef INITIATOR_DRIVER + /* triggers discovery */ + ostiPortEvent( + tiRoot, + tiPortDiscoveryReady, + tiSuccess, + (void *) tdsaAllShared->Ports[PhyID].tiPortalContext + ); +#endif + + return; +} + +/*****************************************************************************/ +/*! \brief SAT implementation for tdsaDiscoveryStartIDDev. + * + * This function sends identify device data to SATA device in discovery + * + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param oneDeviceData : Pointer to the device data. + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 +tdsaDiscoveryStartIDDev(tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, /* agNULL */ + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, /* agNULL */ + tdsaDeviceData_t *oneDeviceData + ) +{ + void *osMemHandle; + tdIORequestBody_t *tdIORequestBody; + bit32 PhysUpper32; + bit32 PhysLower32; + bit32 memAllocStatus; + agsaIORequest_t *agIORequest = agNULL; /* identify device data itself */ + satIOContext_t *satIOContext = agNULL; + bit32 status; + + /* allocate tdiorequestbody and call tdsaDiscoveryIntStartIDDev + tdsaDiscoveryIntStartIDDev(tiRoot, agNULL, tiDeviceHandle, satIOContext); + + */ + + TI_DBG3(("tdsaDiscoveryStartIDDev: start\n")); + TI_DBG3(("tdsaDiscoveryStartIDDev: did %d\n", oneDeviceData->id)); + + /* allocation tdIORequestBody and pass it to satTM() */ + memAllocStatus = ostiAllocMemory( + tiRoot, + &osMemHandle, + (void **)&tdIORequestBody, + &PhysUpper32, + &PhysLower32, + 8, + sizeof(tdIORequestBody_t), + agTRUE + ); + + if (memAllocStatus != tiSuccess) + { + TI_DBG1(("tdsaDiscoveryStartIDDev: ostiAllocMemory failed... loc 1\n")); + return tiError; + } + if (tdIORequestBody == agNULL) + { + TI_DBG1(("tdsaDiscoveryStartIDDev: ostiAllocMemory returned NULL tdIORequestBody loc 2\n")); + return tiError; + } + + /* setup identify device data IO structure */ + tdIORequestBody->IOType.InitiatorTMIO.osMemHandle = osMemHandle; + tdIORequestBody->IOType.InitiatorTMIO.CurrentTaskTag = agNULL; + tdIORequestBody->IOType.InitiatorTMIO.TaskTag = agNULL; + + /* initialize tiDevhandle */ + tdIORequestBody->tiDevHandle = &(oneDeviceData->tiDeviceHandle); + tdIORequestBody->tiDevHandle->tdData = oneDeviceData; + + /* initialize tiIORequest */ + tdIORequestBody->tiIORequest = agNULL; + + /* initialize agIORequest */ + agIORequest = &(tdIORequestBody->agIORequest); + agIORequest->osData = (void *) tdIORequestBody; + agIORequest->sdkData = agNULL; /* SA takes care of this */ + + /* set up satIOContext */ + satIOContext = &(tdIORequestBody->transport.SATA.satIOContext); + satIOContext->pSatDevData = &(oneDeviceData->satDevData); + satIOContext->pFis = + &(tdIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev); + + satIOContext->tiRequestBody = tdIORequestBody; + satIOContext->ptiDeviceHandle = &(oneDeviceData->tiDeviceHandle); + satIOContext->tiScsiXchg = agNULL; + satIOContext->satIntIoContext = agNULL; + satIOContext->satOrgIOContext = agNULL; + /* followings are used only for internal IO */ + satIOContext->currentLBA = 0; + satIOContext->OrgTL = 0; + satIOContext->satToBeAbortedIOContext = agNULL; + satIOContext->NotifyOS = agFALSE; + + /* saving port ID just in case of full discovery to full discovery transition */ + satIOContext->pid = oneDeviceData->tdPortContext->id; + osti_memset(&(oneDeviceData->satDevData.satIdentifyData), 0x0, sizeof(agsaSATAIdentifyData_t)); + status = tdsaDiscoveryIntStartIDDev(tiRoot, + tiIORequest, /* agNULL */ + tiDeviceHandle, /* &(oneDeviceData->tiDeviceHandle)*/ + agNULL, + satIOContext + ); + if (status != tiSuccess) + { + TI_DBG1(("tdsaDiscoveryStartIDDev: failed in sending %d\n", status)); + ostiFreeMemory(tiRoot, osMemHandle, sizeof(tdIORequestBody_t)); + } + return status; +} + +/*****************************************************************************/ +/*! \brief SAT implementation for tdsaDiscoveryIntStartIDDev. + * + * This function sends identify device data to SATA device. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 +tdsaDiscoveryIntStartIDDev(tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, /* agNULL */ + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, /* agNULL */ + satIOContext_t *satIOContext + ) +{ + satInternalIo_t *satIntIo = agNULL; + satDeviceData_t *satDevData = agNULL; + tdIORequestBody_t *tdIORequestBody; + satIOContext_t *satNewIOContext; + bit32 status; + + TI_DBG3(("tdsaDiscoveryIntStartIDDev: start\n")); + + satDevData = satIOContext->pSatDevData; + + /* allocate identify device command */ + satIntIo = satAllocIntIoResource( tiRoot, + tiIORequest, + satDevData, + sizeof(agsaSATAIdentifyData_t), /* 512; size of identify device data */ + satIntIo); + + if (satIntIo == agNULL) + { + TI_DBG2(("tdsaDiscoveryIntStartIDDev: can't alloacate\n")); + + return tiError; + } + + /* fill in fields */ + /* real ttttttthe one worked and the same; 5/21/07/ */ + satIntIo->satOrgTiIORequest = tiIORequest; /* changed */ + tdIORequestBody = satIntIo->satIntRequestBody; + satNewIOContext = &(tdIORequestBody->transport.SATA.satIOContext); + + satNewIOContext->pSatDevData = satDevData; + satNewIOContext->pFis = &(tdIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev); + satNewIOContext->pScsiCmnd = &(satIntIo->satIntTiScsiXchg.scsiCmnd); + satNewIOContext->pSense = &(tdIORequestBody->transport.SATA.sensePayload); + satNewIOContext->pTiSenseData = &(tdIORequestBody->transport.SATA.tiSenseData); + satNewIOContext->tiRequestBody = satIntIo->satIntRequestBody; /* key fix */ + satNewIOContext->interruptContext = tiInterruptContext; + satNewIOContext->satIntIoContext = satIntIo; + + satNewIOContext->ptiDeviceHandle = agNULL; + satNewIOContext->satOrgIOContext = satIOContext; /* changed */ + + /* this is valid only for TD layer generated (not triggered by OS at all) IO */ + satNewIOContext->tiScsiXchg = &(satIntIo->satIntTiScsiXchg); + + + TI_DBG6(("tdsaDiscoveryIntStartIDDev: OS satIOContext %p \n", satIOContext)); + TI_DBG6(("tdsaDiscoveryIntStartIDDev: TD satNewIOContext %p \n", satNewIOContext)); + TI_DBG6(("tdsaDiscoveryIntStartIDDev: OS tiScsiXchg %p \n", satIOContext->tiScsiXchg)); + TI_DBG6(("tdsaDiscoveryIntStartIDDev: TD tiScsiXchg %p \n", satNewIOContext->tiScsiXchg)); + + + + TI_DBG3(("tdsaDiscoveryIntStartIDDev: satNewIOContext %p tdIORequestBody %p\n", satNewIOContext, tdIORequestBody)); + + status = tdsaDiscoverySendIDDev(tiRoot, + &satIntIo->satIntTiIORequest, /* New tiIORequest */ + tiDeviceHandle, + satNewIOContext->tiScsiXchg, /* New tiScsiInitiatorRequest_t *tiScsiRequest, */ + satNewIOContext); + + if (status != tiSuccess) + { + TI_DBG1(("tdsaDiscoveryIntStartIDDev: failed in sending %d\n", status)); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + return tiError; + } + + + TI_DBG6(("tdsaDiscoveryIntStartIDDev: end\n")); + + return status; +} + + +/*****************************************************************************/ +/*! \brief SAT implementation for tdsaDiscoverySendIDDev. + * + * This function prepares identify device data FIS and sends it to SATA device. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 +tdsaDiscoverySendIDDev(tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext + ) +{ + bit32 status; + bit32 agRequestType; + satDeviceData_t *pSatDevData; + agsaFisRegHostToDevice_t *fis; +#ifdef TD_DEBUG_ENABLE + tdIORequestBody_t *tdIORequestBody; + satInternalIo_t *satIntIoContext; +#endif + + pSatDevData = satIOContext->pSatDevData; + fis = satIOContext->pFis; + TI_DBG3(("tdsaDiscoverySendIDDev: start\n")); +#ifdef TD_DEBUG_ENABLE + satIntIoContext = satIOContext->satIntIoContext; + tdIORequestBody = satIntIoContext->satIntRequestBody; +#endif + TI_DBG5(("tdsaDiscoverySendIDDev: satIOContext %p tdIORequestBody %p\n", satIOContext, tdIORequestBody)); + + fis->h.fisType = 0x27; /* Reg host to device */ + fis->h.c_pmPort = 0x80; /* C Bit is set */ + if (pSatDevData->satDeviceType == SATA_ATAPI_DEVICE) + fis->h.command = SAT_IDENTIFY_PACKET_DEVICE; /* 0xA1 */ + else + fis->h.command = SAT_IDENTIFY_DEVICE; /* 0xEC */ + fis->h.features = 0; /* FIS reserve */ + fis->d.lbaLow = 0; /* FIS LBA (7 :0 ) */ + fis->d.lbaMid = 0; /* FIS LBA (15:8 ) */ + fis->d.lbaHigh = 0; /* FIS LBA (23:16) */ + fis->d.device = 0; /* FIS LBA mode */ + fis->d.lbaLowExp = 0; + fis->d.lbaMidExp = 0; + fis->d.lbaHighExp = 0; + fis->d.featuresExp = 0; + fis->d.sectorCount = 0; /* FIS sector count (7:0) */ + fis->d.sectorCountExp = 0; + fis->d.reserved4 = 0; + fis->d.control = 0; /* FIS HOB bit clear */ + fis->d.reserved5 = 0; + + agRequestType = AGSA_SATA_PROTOCOL_PIO_READ; + + /* Initialize CB for SATA completion. + */ + satIOContext->satCompleteCB = &tdsaDiscoveryStartIDDevCB; + + /* + * Prepare SGL and send FIS to LL layer. + */ + satIOContext->reqType = agRequestType; /* Save it */ + +#ifdef TD_INTERNAL_DEBUG + tdhexdump("tdsaDiscoverySendIDDev", (bit8 *)satIOContext->pFis, sizeof(agsaFisRegHostToDevice_t)); +#ifdef TD_DEBUG_ENABLE + tdhexdump("tdsaDiscoverySendIDDev LL", (bit8 *)&(tdIORequestBody->transport.SATA.agSATARequestBody.fis.fisRegHostToDev), sizeof(agsaFisRegHostToDevice_t)); +#endif +#endif + status = sataLLIOStart( tiRoot, + tiIORequest, + tiDeviceHandle, + tiScsiRequest, + satIOContext); + TI_DBG3(("tdsaDiscoverySendIDDev: end status %d\n", status)); + return status; +} + + +/***************************************************************************** +*! \brief tdsaDiscoveryStartIDDevCB +* +* This routine is a callback function for tdsaDiscoverySendIDDev() +* Using Identify Device Data, this function finds whether devicedata is +* new or old. If new, add it to the devicelist. This is done as a part +* of discovery. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agFirstDword:Pointer to the four bytes of FIS. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param agParam: Additional info based on status. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void tdsaDiscoveryStartIDDevCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ) +{ + /* + In the process of SAT_IDENTIFY_DEVICE during discovery + */ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + tdIORequestBody_t *tdIORequestBody; + tdIORequestBody_t *tdOrgIORequestBody; + satIOContext_t *satIOContext; + satIOContext_t *satOrgIOContext; + satIOContext_t *satNewIOContext; + satInternalIo_t *satIntIo; + satInternalIo_t *satNewIntIo = agNULL; + satDeviceData_t *satDevData; + tiIORequest_t *tiOrgIORequest = agNULL; + +#ifdef TD_DEBUG_ENABLE + bit32 ataStatus = 0; + bit32 ataError; + agsaFisPioSetupHeader_t *satPIOSetupHeader = agNULL; +#endif + agsaSATAIdentifyData_t *pSATAIdData; + bit16 *tmpptr, tmpptr_tmp; + bit32 x; + tdsaDeviceData_t *oneDeviceData = agNULL; + void *sglVirtualAddr; + tdsaPortContext_t *onePortContext = agNULL; + tiPortalContext_t *tiPortalContext = agNULL; + bit32 retry_status; + + TI_DBG3(("tdsaDiscoveryStartIDDevCB: start\n")); + + tdIORequestBody = (tdIORequestBody_t *)agIORequest->osData; + satIOContext = (satIOContext_t *) ioContext; + satIntIo = satIOContext->satIntIoContext; + satDevData = satIOContext->pSatDevData; + oneDeviceData = (tdsaDeviceData_t *)tdIORequestBody->tiDevHandle->tdData; + TI_DBG3(("tdsaDiscoveryStartIDDevCB: did %d\n", oneDeviceData->id)); + onePortContext = oneDeviceData->tdPortContext; + if (onePortContext == agNULL) + { + TI_DBG1(("tdsaDiscoveryStartIDDevCB: onePortContext is NULL\n")); + return; + } + tiPortalContext= onePortContext->tiPortalContext; + + satDevData->IDDeviceValid = agFALSE; + + if (satIntIo == agNULL) + { + TI_DBG1(("tdsaDiscoveryStartIDDevCB: External, OS generated\n")); + TI_DBG1(("tdsaDiscoveryStartIDDevCB: Not possible case\n")); + satOrgIOContext = satIOContext; + tdOrgIORequestBody = (tdIORequestBody_t *)satOrgIOContext->tiRequestBody; + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + /* clean up TD layer's IORequestBody */ + ostiFreeMemory( + tiRoot, + tdOrgIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; + } + else + { + TI_DBG3(("tdsaDiscoveryStartIDDevCB: Internal, TD generated\n")); + satOrgIOContext = satIOContext->satOrgIOContext; + if (satOrgIOContext == agNULL) + { + TI_DBG6(("tdsaDiscoveryStartIDDevCB: satOrgIOContext is NULL\n")); + return; + } + else + { + TI_DBG6(("tdsaDiscoveryStartIDDevCB: satOrgIOContext is NOT NULL\n")); + tdOrgIORequestBody = (tdIORequestBody_t *)satOrgIOContext->tiRequestBody; + sglVirtualAddr = satIntIo->satIntTiScsiXchg.sglVirtualAddr; + } + } + + tiOrgIORequest = tdIORequestBody->tiIORequest; + tdIORequestBody->ioCompleted = agTRUE; + tdIORequestBody->ioStarted = agFALSE; + + TI_DBG3(("tdsaDiscoveryStartIDDevCB: satOrgIOContext->pid %d\n", satOrgIOContext->pid)); + + /* protect against double completion for old port */ + if (satOrgIOContext->pid != oneDeviceData->tdPortContext->id) + { + TI_DBG3(("tdsaDiscoveryStartIDDevCB: incorrect pid\n")); + TI_DBG3(("tdsaDiscoveryStartIDDevCB: satOrgIOContext->pid %d\n", satOrgIOContext->pid)); + TI_DBG3(("tdsaDiscoveryStartIDDevCB: tiPortalContext pid %d\n", oneDeviceData->tdPortContext->id)); + + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + /* clean up TD layer's IORequestBody */ + ostiFreeMemory( + tiRoot, + tdOrgIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + + return; + } + + /* completion after portcontext is invalidated */ + if (onePortContext != agNULL) + { + if (onePortContext->valid == agFALSE) + { + TI_DBG1(("tdsaDiscoveryStartIDDevCB: portcontext is invalid\n")); + TI_DBG1(("tdsaDiscoveryStartIDDevCB: onePortContext->id pid %d\n", onePortContext->id)); + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + /* clean up TD layer's IORequestBody */ + ostiFreeMemory( + tiRoot, + tdOrgIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + + /* no notification to OS layer */ + return; + } + } + + if (agFirstDword == agNULL && agIOStatus != OSSA_IO_SUCCESS) + { + TI_DBG1(("tdsaDiscoveryStartIDDevCB: agFirstDword is NULL when error, status %d\n", agIOStatus)); + TI_DBG1(("tdsaDiscoveryStartIDDevCB: did %d\n", oneDeviceData->id)); + + if (tdsaAllShared->ResetInDiscovery != 0 && satDevData->ID_Retries < SATA_ID_DEVICE_DATA_RETRIES) + { + satIOContext->pSatDevData->satPendingNONNCQIO--; + satIOContext->pSatDevData->satPendingIO--; + retry_status = sataLLIOStart(tiRoot, + &satIntIo->satIntTiIORequest, + &(oneDeviceData->tiDeviceHandle), + satIOContext->tiScsiXchg, + satIOContext); + if (retry_status != tiSuccess) + { + /* simply give up */ + satDevData->ID_Retries = 0; + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + /* clean up TD layer's IORequestBody */ + ostiFreeMemory( + tiRoot, + tdOrgIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; + } + satDevData->ID_Retries++; + tdIORequestBody->ioCompleted = agFALSE; + tdIORequestBody->ioStarted = agTRUE; + return; + } + else + { + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + /* clean up TD layer's IORequestBody */ + ostiFreeMemory( + tiRoot, + tdOrgIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + if (tdsaAllShared->ResetInDiscovery != 0) + { + /* ResetInDiscovery in on */ + if (satDevData->NumOfIDRetries <= 0) + { + satDevData->NumOfIDRetries++; + satDevData->ID_Retries = 0; + /* send link reset */ + tdsaPhyControlSend(tiRoot, + oneDeviceData, + SMP_PHY_CONTROL_HARD_RESET, + agNULL, + tdsaRotateQnumber(tiRoot, oneDeviceData) + ); + } + } + return; + } + } + + if (agIOStatus == OSSA_IO_ABORTED || + agIOStatus == OSSA_IO_UNDERFLOW || + agIOStatus == OSSA_IO_XFER_ERROR_BREAK || + agIOStatus == OSSA_IO_XFER_ERROR_PHY_NOT_READY || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_BREAK || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION || + agIOStatus == OSSA_IO_XFER_ERROR_NAK_RECEIVED || + agIOStatus == OSSA_IO_XFER_ERROR_DMA || + agIOStatus == OSSA_IO_XFER_ERROR_SATA_LINK_TIMEOUT || + agIOStatus == OSSA_IO_XFER_ERROR_REJECTED_NCQ_MODE || + agIOStatus == OSSA_IO_XFER_OPEN_RETRY_TIMEOUT || + agIOStatus == OSSA_IO_NO_DEVICE || + agIOStatus == OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION || + agIOStatus == OSSA_IO_PORT_IN_RESET || + agIOStatus == OSSA_IO_DS_NON_OPERATIONAL || + agIOStatus == OSSA_IO_DS_IN_RECOVERY || + agIOStatus == OSSA_IO_DS_IN_ERROR + ) + { + TI_DBG1(("tdsaDiscoveryStartIDDevCB: OSSA_IO_OPEN_CNX_ERROR 0x%x\n", agIOStatus)); + if (tdsaAllShared->ResetInDiscovery != 0 && satDevData->ID_Retries < SATA_ID_DEVICE_DATA_RETRIES) + { + satIOContext->pSatDevData->satPendingNONNCQIO--; + satIOContext->pSatDevData->satPendingIO--; + retry_status = sataLLIOStart(tiRoot, + &satIntIo->satIntTiIORequest, + &(oneDeviceData->tiDeviceHandle), + satIOContext->tiScsiXchg, + satIOContext); + if (retry_status != tiSuccess) + { + /* simply give up */ + satDevData->ID_Retries = 0; + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + /* clean up TD layer's IORequestBody */ + ostiFreeMemory( + tiRoot, + tdOrgIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; + } + satDevData->ID_Retries++; + tdIORequestBody->ioCompleted = agFALSE; + tdIORequestBody->ioStarted = agTRUE; + return; + } + else + { + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + /* clean up TD layer's IORequestBody */ + ostiFreeMemory( + tiRoot, + tdOrgIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + if (tdsaAllShared->ResetInDiscovery != 0) + { + /* ResetInDiscovery in on */ + if (satDevData->NumOfIDRetries <= 0) + { + satDevData->NumOfIDRetries++; + satDevData->ID_Retries = 0; + /* send link reset */ + tdsaPhyControlSend(tiRoot, + oneDeviceData, + SMP_PHY_CONTROL_HARD_RESET, + agNULL, + tdsaRotateQnumber(tiRoot, oneDeviceData) + ); + } + } + return; + } + } + + if ( agIOStatus != OSSA_IO_SUCCESS || + (agIOStatus == OSSA_IO_SUCCESS && agFirstDword != agNULL && agIOInfoLen != 0) + ) + { +#ifdef TD_DEBUG_ENABLE + /* only agsaFisPioSetup_t is expected */ + satPIOSetupHeader = (agsaFisPioSetupHeader_t *)&(agFirstDword->PioSetup); + ataStatus = satPIOSetupHeader->status; /* ATA Status register */ + ataError = satPIOSetupHeader->error; /* ATA Eror register */ +#endif + TI_DBG1(("tdsaDiscoveryStartIDDevCB: ataStatus 0x%x ataError 0x%x\n", ataStatus, ataError)); + + if (tdsaAllShared->ResetInDiscovery != 0 && satDevData->ID_Retries < SATA_ID_DEVICE_DATA_RETRIES) + { + satIOContext->pSatDevData->satPendingNONNCQIO--; + satIOContext->pSatDevData->satPendingIO--; + retry_status = sataLLIOStart(tiRoot, + &satIntIo->satIntTiIORequest, + &(oneDeviceData->tiDeviceHandle), + satIOContext->tiScsiXchg, + satIOContext); + if (retry_status != tiSuccess) + { + /* simply give up */ + satDevData->ID_Retries = 0; + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + /* clean up TD layer's IORequestBody */ + ostiFreeMemory( + tiRoot, + tdOrgIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; + } + satDevData->ID_Retries++; + tdIORequestBody->ioCompleted = agFALSE; + tdIORequestBody->ioStarted = agTRUE; + return; + } + else + { + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + /* clean up TD layer's IORequestBody */ + ostiFreeMemory( + tiRoot, + tdOrgIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + if (tdsaAllShared->ResetInDiscovery != 0) + { + /* ResetInDiscovery in on */ + if (satDevData->NumOfIDRetries <= 0) + { + satDevData->NumOfIDRetries++; + satDevData->ID_Retries = 0; + /* send link reset */ + tdsaPhyControlSend(tiRoot, + oneDeviceData, + SMP_PHY_CONTROL_HARD_RESET, + agNULL, + tdsaRotateQnumber(tiRoot, oneDeviceData) + ); + } + } + return; + } + } + + + /* success */ + TI_DBG3(("tdsaDiscoveryStartIDDevCB: Success\n")); + TI_DBG3(("tdsaDiscoveryStartIDDevCB: Success did %d\n", oneDeviceData->id)); + + /* Convert to host endian */ + tmpptr = (bit16*)sglVirtualAddr; + for (x=0; x < sizeof(agsaSATAIdentifyData_t)/sizeof(bit16); x++) + { + OSSA_READ_LE_16(AGROOT, &tmpptr_tmp, tmpptr, 0); + *tmpptr = tmpptr_tmp; + tmpptr++; + } + + pSATAIdData = (agsaSATAIdentifyData_t *)sglVirtualAddr; + //tdhexdump("satAddSATAIDDevCB before", (bit8 *)pSATAIdData, sizeof(agsaSATAIdentifyData_t)); + + TI_DBG5(("tdsaDiscoveryStartIDDevCB: OS satOrgIOContext %p \n", satOrgIOContext)); + TI_DBG5(("tdsaDiscoveryStartIDDevCB: TD satIOContext %p \n", satIOContext)); + TI_DBG5(("tdsaDiscoveryStartIDDevCB: OS tiScsiXchg %p \n", satOrgIOContext->tiScsiXchg)); + TI_DBG5(("tdsaDiscoveryStartIDDevCB: TD tiScsiXchg %p \n", satIOContext->tiScsiXchg)); + + + /* copy ID Dev data to satDevData */ + satDevData->satIdentifyData = *pSATAIdData; + satDevData->IDDeviceValid = agTRUE; + +#ifdef TD_INTERNAL_DEBUG + tdhexdump("tdsaDiscoveryStartIDDevCB ID Dev data",(bit8 *)pSATAIdData, sizeof(agsaSATAIdentifyData_t)); + tdhexdump("tdsaDiscoveryStartIDDevCB Device ID Dev data",(bit8 *)&satDevData->satIdentifyData, sizeof(agsaSATAIdentifyData_t)); +#endif + + /* set satDevData fields from IndentifyData */ + satSetDevInfo(satDevData,pSATAIdData); + satDecrementPendingIO(tiRoot, tdsaAllShared, satIOContext); + + satFreeIntIoResource( tiRoot, + satDevData, + satIntIo); + + if (satDevData->satDeviceType == SATA_ATAPI_DEVICE) + { + /* send the Set Feature ATA command to ATAPI device for enbling PIO and DMA transfer mode*/ + satNewIntIo = satAllocIntIoResource( tiRoot, + tiOrgIORequest, + satDevData, + 0, + satNewIntIo); + + if (satNewIntIo == agNULL) + { + TI_DBG1(("tdsaDiscoveryStartIDDevCB: momory allocation fails\n")); + /* clean up TD layer's IORequestBody */ + ostiFreeMemory( + tiRoot, + tdOrgIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + return; + } /* end memory allocation */ + + satNewIOContext = satPrepareNewIO(satNewIntIo, + tiOrgIORequest, + satDevData, + agNULL, + satOrgIOContext + ); + /* enable PIO mode, then enable Ultra DMA mode in the satSetFeaturesCB callback function*/ + retry_status = satSetFeatures(tiRoot, + &satNewIntIo->satIntTiIORequest, + satNewIOContext->ptiDeviceHandle, + &satNewIntIo->satIntTiScsiXchg, /* orginal from OS layer */ + satNewIOContext, + agFALSE); + if (retry_status != tiSuccess) + { + satFreeIntIoResource(tiRoot, satDevData, satIntIo); + /* clean up TD layer's IORequestBody */ + ostiFreeMemory( + tiRoot, + tdOrgIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + } + } + else + { + /* clean up TD layer's IORequestBody */ + ostiFreeMemory( + tiRoot, + tdOrgIORequestBody->IOType.InitiatorTMIO.osMemHandle, + sizeof(tdIORequestBody_t) + ); + if (onePortContext != agNULL) + { + if (onePortContext->DiscoveryState == ITD_DSTATE_COMPLETED) + { + TI_DBG1(("tdsaDiscoveryStartIDDevCB: ID completed after discovery is done; tiDeviceArrival\n")); + /* in case registration is finished after discovery is finished */ + ostiInitiatorEvent( + tiRoot, + tiPortalContext, + agNULL, + tiIntrEventTypeDeviceChange, + tiDeviceArrival, + agNULL + ); + } + } + else + { + TI_DBG1(("tdsaDiscoveryStartIDDevCB: onePortContext is NULL, wrong\n")); + } + } + TI_DBG3(("tdsaDiscoveryStartIDDevCB: end\n")); + return; +} +/***************************************************************************** +*! \brief satAbort +* +* This routine does local abort for outstanding FIS. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param satIOContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +GLOBAL void satAbort(agsaRoot_t *agRoot, + satIOContext_t *satIOContext) +{ + tdsaRootOsData_t *osData = (tdsaRootOsData_t *)agRoot->osData; + tiRoot_t *tiRoot = (tiRoot_t *)osData->tiRoot; + tdIORequestBody_t *tdIORequestBody; /* io to be aborted */ + tdIORequestBody_t *tdAbortIORequestBody; /* abort io itself */ + agsaIORequest_t *agToBeAbortedIORequest; /* io to be aborted */ + agsaIORequest_t *agAbortIORequest; /* abort io itself */ + bit32 PhysUpper32; + bit32 PhysLower32; + bit32 memAllocStatus; + void *osMemHandle; + + TI_DBG1(("satAbort: start\n")); + + if (satIOContext == agNULL) + { + TI_DBG1(("satAbort: satIOContext is NULL, wrong\n")); + return; + } + tdIORequestBody = (tdIORequestBody_t *)satIOContext->tiRequestBody; + agToBeAbortedIORequest = (agsaIORequest_t *)&(tdIORequestBody->agIORequest); + /* allocating agIORequest for abort itself */ + memAllocStatus = ostiAllocMemory( + tiRoot, + &osMemHandle, + (void **)&tdAbortIORequestBody, + &PhysUpper32, + &PhysLower32, + 8, + sizeof(tdIORequestBody_t), + agTRUE + ); + + if (memAllocStatus != tiSuccess) + { + /* let os process IO */ + TI_DBG1(("satAbort: ostiAllocMemory failed...\n")); + return; + } + + if (tdAbortIORequestBody == agNULL) + { + /* let os process IO */ + TI_DBG1(("satAbort: ostiAllocMemory returned NULL tdAbortIORequestBody\n")); + return; + } + /* setup task management structure */ + tdAbortIORequestBody->IOType.InitiatorTMIO.osMemHandle = osMemHandle; + tdAbortIORequestBody->tiDevHandle = tdIORequestBody->tiDevHandle; + + /* initialize agIORequest */ + agAbortIORequest = &(tdAbortIORequestBody->agIORequest); + agAbortIORequest->osData = (void *) tdAbortIORequestBody; + agAbortIORequest->sdkData = agNULL; /* LL takes care of this */ + + + /* + * Issue abort + */ + saSATAAbort( agRoot, agAbortIORequest, 0, agNULL, 0, agToBeAbortedIORequest, agNULL ); + + + TI_DBG1(("satAbort: end\n")); + return; +} + +/***************************************************************************** + *! \brief satSATADeviceReset + * + * This routine is called to reset all phys of port which a device belongs to + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param oneDeviceData: Pointer to the device data. + * \param flag: reset flag + * + * \return: + * + * none + * + *****************************************************************************/ +osGLOBAL void +satSATADeviceReset( tiRoot_t *tiRoot, + tdsaDeviceData_t *oneDeviceData, + bit32 flag) +{ + agsaRoot_t *agRoot; + tdsaPortContext_t *onePortContext; + bit32 i; + + TI_DBG1(("satSATADeviceReset: start\n")); + agRoot = oneDeviceData->agRoot; + onePortContext = oneDeviceData->tdPortContext; + + if (agRoot == agNULL) + { + TI_DBG1(("satSATADeviceReset: Error!!! agRoot is NULL\n")); + return; + } + if (onePortContext == agNULL) + { + TI_DBG1(("satSATADeviceReset: Error!!! onePortContext is NULL\n")); + return; + } + + for(i=0;iPhyIDList[i] == agTRUE) + { + saLocalPhyControl(agRoot, agNULL, tdsaRotateQnumber(tiRoot, agNULL), i, flag, agNULL); + } + } + + return; +} + +#endif /* #ifdef SATA_ENABLE */ diff --git a/sys/dev/pms/RefTisa/tisa/sassata/sata/host/sat.h b/sys/dev/pms/RefTisa/tisa/sassata/sata/host/sat.h new file mode 100644 index 000000000000..12c352ae696b --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/sata/host/sat.h @@ -0,0 +1,329 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/*******************************************************************************/ +/** \file + * + * + * The file defines the constants, data structure, and functions defined by SAT + * layer. + * + */ + +#ifndef __SAT_H__ +#define __SAT_H__ + +/* + * ATA Command code + */ +#define SAT_READ_FPDMA_QUEUED 0x60 +#define SAT_READ_DMA_EXT 0x25 +#define SAT_READ_DMA 0xC8 +#define SAT_WRITE_FPDMA_QUEUED 0x61 +#define SAT_WRITE_DMA_EXT 0x35 +#define SAT_WRITE_DMA_FUA_EXT 0x3D +#define SAT_WRITE_DMA 0xCA +#define SAT_CHECK_POWER_MODE 0xE5 +#define SAT_READ_LOG_EXT 0x2F +#define SAT_READ_VERIFY_SECTORS 0x40 +#define SAT_READ_VERIFY_SECTORS_EXT 0x42 +#define SAT_SMART 0xB0 +#define SAT_SMART_EXEUTE_OFF_LINE_IMMEDIATE 0xD4 +#define SAT_SMART_RETURN_STATUS 0xDA +#define SAT_SMART_READ_LOG 0xD5 +#define SAT_SMART_ENABLE_OPERATIONS 0xD8 +#define SAT_SMART_DISABLE_OPERATIONS 0xD9 +#define SAT_FLUSH_CACHE 0xE7 +#define SAT_FLUSH_CACHE_EXT 0xEA +#define SAT_STANDBY 0xE2 +#define SAT_MEDIA_EJECT 0xED +#define SAT_WRITE_SECTORS 0x30 +#define SAT_WRITE_SECTORS_EXT 0x34 +#define SAT_READ_SECTORS 0x20 +#define SAT_READ_SECTORS_EXT 0x24 +#define SAT_GET_MEDIA_STATUS 0xDA +#define SAT_SET_FEATURES 0xEF +#define SAT_IDENTIFY_DEVICE 0xEC +#define SAT_READ_BUFFER 0xE4 +#define SAT_WRITE_BUFFER 0xE8 +/* + * ATAPI Command code +*/ +#define SAT_IDENTIFY_PACKET_DEVICE 0xA1 +#define SAT_PACKET 0xA0 +#define SAT_DEVICE_RESET 0x08 +#define SAT_EXECUTE_DEVICE_DIAGNOSTIC 0x90 +/* + * ATA Status Register Mask + */ +#define ERR_ATA_STATUS_MASK 0x01 /* Error/check bit */ +#define DRQ_ATA_STATUS_MASK 0x08 /* Data Request bit */ +#define DF_ATA_STATUS_MASK 0x20 /* Device Fault bit */ +#define DRDY_ATA_STATUS_MASK 0x40 /* Device Ready bit */ +#define BSY_ATA_STATUS_MASK 0x80 /* Busy bit */ + +/* + * ATA Error Register Mask + */ +#define NM_ATA_ERROR_MASK 0x02 /* No media present bit */ +#define ABRT_ATA_ERROR_MASK 0x04 /* Command aborted bit */ +#define MCR_ATA_ERROR_MASK 0x08 /* Media change request bit */ +#define IDNF_ATA_ERROR_MASK 0x10 /* Address not found bit */ +#define MC_ATA_ERROR_MASK 0x20 /* Media has changed bit */ +#define UNC_ATA_ERROR_MASK 0x40 /* Uncorrectable data error bit */ +#define ICRC_ATA_ERROR_MASK 0x80 /* Interface CRC error bit */ + + + + +/* + * transfer length and LBA limit 2^28 See identify device data word 61:60 + * ATA spec p125 + * 7 zeros + */ +#define SAT_TR_LBA_LIMIT 0x10000000 + +/* + * transfer length and LBA limit 2^48 See identify device data word 61:60 + * ATA spec p125 + * 12 zeros + */ +#define SAT_EXT_TR_LBA_LIMIT 0x1000000000000 + + +/* + * ATA command type. This is for setting LBA, Sector Count + */ +#define SAT_NON_EXT_TYPE 0 +#define SAT_EXT_TYPE 1 +#define SAT_FP_TYPE 2 + + +/* + * Report LUNs response data. + */ +typedef struct scsiReportLun_s +{ + bit8 len[4]; + bit32 reserved; + tiLUN_t lunList[1]; +} scsiReportLun_t; + +/* Inquiry vendor string */ +#define AG_SAT_VENDOR_ID_STRING "ATA " + +/* + * Simple form of SATA Identify Device Data, similar definition is defined by + * LL Layer as agsaSATAIdentifyData_t. + */ +typedef struct satSimpleSATAIdentifyData_s +{ + bit16 word[256]; +} satSimpleSATAIdentifyData_t; + + +/* + * READ LOG EXT page 10h + */ +typedef struct satReadLogExtPage10h_s +{ + bit8 byte[512]; +} satReadLogExtPage10h_t; + +/* + * READ LOG EXT Extended Self-test log + * ATA Table27 p196 + */ +typedef struct satReadLogExtSelfTest_s +{ + bit8 byte[512]; +} satReadLogExtSelfTest_t; + +/* + * SMART READ LOG Self-test log + * ATA Table60 p296 + */ +typedef struct satSmartReadLogSelfTest_s +{ + bit8 byte[512]; +} satSmartReadLogSelfTest_t; + + +/* + * Flag definition for satIntFlag field in satInternalIo_t. + */ + +/* Original NCQ I/O already completed, so at the completion of READ LOG EXT + * page 10h, ignore the TAG tranaltion to get the failed I/O + */ +#define AG_SAT_INT_IO_FLAG_ORG_IO_COMPLETED 0x00000001 + +#define INQUIRY_SUPPORTED_VPD_PAGE 0x00 +#define INQUIRY_UNIT_SERIAL_NUMBER_VPD_PAGE 0x80 +#define INQUIRY_DEVICE_IDENTIFICATION_VPD_PAGE 0x83 +#define INQUIRY_ATA_INFORMATION_VPD_PAGE 0x89 + +#define MODESENSE_CONTROL_PAGE 0x0A +#define MODESENSE_READ_WRITE_ERROR_RECOVERY_PAGE 0x01 +#define MODESENSE_CACHING 0x08 +#define MODESENSE_INFORMATION_EXCEPTION_CONTROL_PAGE 0x1C +#define MODESENSE_RETURN_ALL_PAGES 0x3F +#define MODESENSE_VENDOR_SPECIFIC_PAGE 0x00 + +#define MODESELECT_CONTROL_PAGE 0x0A +#define MODESELECT_READ_WRITE_ERROR_RECOVERY_PAGE 0x01 +#define MODESELECT_CACHING 0x08 +#define MODESELECT_INFORMATION_EXCEPTION_CONTROL_PAGE 0x1C +#define MODESELECT_RETURN_ALL_PAGES 0x3F +#define MODESELECT_VENDOR_SPECIFIC_PAGE 0x00 + +#define LOGSENSE_SUPPORTED_LOG_PAGES 0x00 +#define LOGSENSE_SELFTEST_RESULTS_PAGE 0x10 +#define LOGSENSE_INFORMATION_EXCEPTIONS_PAGE 0x2F + + +/* + * Bit mask definition + */ +#define SCSI_EVPD_MASK 0x01 +#define SCSI_IMMED_MASK 0x01 +#define SCSI_NACA_MASK 0x04 +#define SCSI_LINK_MASK 0x01 +#define SCSI_PF_MASK 0x10 +#define SCSI_DEVOFFL_MASK 0x02 +#define SCSI_UNITOFFL_MASK 0x01 +#define SCSI_START_MASK 0x01 +#define SCSI_LOEJ_MASK 0x02 +#define SCSI_NM_MASK 0x02 +#define SCSI_FLUSH_CACHE_IMMED_MASK 0x02 +#define SCSI_FUA_NV_MASK 0x02 +#define SCSI_VERIFY_BYTCHK_MASK 0x02 +#define SCSI_FORMAT_UNIT_IMMED_MASK 0x02 +#define SCSI_FORMAT_UNIT_FOV_MASK 0x80 +#define SCSI_FORMAT_UNIT_DCRT_MASK 0x20 +#define SCSI_FORMAT_UNIT_IP_MASK 0x08 +#define SCSI_WRITE_SAME_LBDATA_MASK 0x02 +#define SCSI_WRITE_SAME_PBDATA_MASK 0x04 +#define SCSI_SYNC_CACHE_IMMED_MASK 0x02 +#define SCSI_WRITE_N_VERIFY_BYTCHK_MASK 0x02 +#define SCSI_SEND_DIAGNOSTIC_SELFTEST_MASK 0x04 +#define SCSI_FORMAT_UNIT_DEFECT_LIST_FORMAT_MASK 0x07 +#define SCSI_FORMAT_UNIT_FMTDATA_MASK 0x10 +#define SCSI_FORMAT_UNIT_DCRT_MASK 0x20 +#define SCSI_FORMAT_UNIT_CMPLIST_MASK 0x08 +#define SCSI_FORMAT_UNIT_LONGLIST_MASK 0x20 +#define SCSI_READ10_FUA_MASK 0x08 +#define SCSI_READ12_FUA_MASK 0x08 +#define SCSI_READ16_FUA_MASK 0x08 +#define SCSI_WRITE10_FUA_MASK 0x08 +#define SCSI_WRITE12_FUA_MASK 0x08 +#define SCSI_WRITE16_FUA_MASK 0x08 +#define SCSI_READ_CAPACITY10_PMI_MASK 0x01 +#define SCSI_READ_CAPACITY16_PMI_MASK 0x01 +#define SCSI_MODE_SENSE6_PC_MASK 0xC0 +#define SCSI_MODE_SENSE6_PAGE_CODE_MASK 0x3F +#define SCSI_MODE_SENSE10_PC_MASK 0xC0 +#define SCSI_MODE_SENSE10_LLBAA_MASK 0x10 +#define SCSI_MODE_SENSE10_PAGE_CODE_MASK 0x3F +#define SCSI_SEND_DIAGNOSTIC_TEST_CODE_MASK 0xE0 +#define SCSI_LOG_SENSE_PAGE_CODE_MASK 0x3F +#define SCSI_MODE_SELECT6_PF_MASK 0x10 +#define SCSI_MODE_SELECT6_AWRE_MASK 0x80 +#define SCSI_MODE_SELECT6_RC_MASK 0x10 +#define SCSI_MODE_SELECT6_EER_MASK 0x08 +#define SCSI_MODE_SELECT6_PER_MASK 0x04 +#define SCSI_MODE_SELECT6_DTE_MASK 0x02 +#define SCSI_MODE_SELECT6_DCR_MASK 0x01 +#define SCSI_MODE_SELECT6_WCE_MASK 0x04 +#define SCSI_MODE_SELECT6_DRA_MASK 0x20 +#define SCSI_MODE_SELECT6_PERF_MASK 0x80 +#define SCSI_MODE_SELECT6_TEST_MASK 0x04 +#define SCSI_MODE_SELECT6_DEXCPT_MASK 0x08 +#define SCSI_MODE_SELECT10_PF_MASK 0x10 +#define SCSI_MODE_SELECT10_LONGLBA_MASK 0x01 +#define SCSI_MODE_SELECT10_AWRE_MASK 0x80 +#define SCSI_MODE_SELECT10_RC_MASK 0x10 +#define SCSI_MODE_SELECT10_EER_MASK 0x08 +#define SCSI_MODE_SELECT10_PER_MASK 0x04 +#define SCSI_MODE_SELECT10_DTE_MASK 0x02 +#define SCSI_MODE_SELECT10_DCR_MASK 0x01 +#define SCSI_MODE_SELECT10_WCE_MASK 0x04 +#define SCSI_MODE_SELECT10_DRA_MASK 0x20 +#define SCSI_MODE_SELECT10_PERF_MASK 0x80 +#define SCSI_MODE_SELECT10_TEST_MASK 0x04 +#define SCSI_MODE_SELECT10_DEXCPT_MASK 0x08 +#define SCSI_WRITE_N_VERIFY10_FUA_MASK 0x08 +#define SCSI_REQUEST_SENSE_DESC_MASK 0x01 +#define SCSI_READ_BUFFER_MODE_MASK 0x1F + +#define ATA_REMOVABLE_MEDIA_DEVICE_MASK 0x80 +#define SCSI_REASSIGN_BLOCKS_LONGLIST_MASK 0x01 +#define SCSI_REASSIGN_BLOCKS_LONGLBA_MASK 0x02 + + +#define SENSE_DATA_LENGTH 0x12 /* 18 */ +#define SELFTEST_RESULTS_LOG_PAGE_LENGTH 404 +#define INFORMATION_EXCEPTIONS_LOG_PAGE_LENGTH 11 +#define ZERO_MEDIA_SERIAL_NUMBER_LENGTH 8 + +#define LOG_SENSE_0 0 +#define LOG_SENSE_1 1 +#define LOG_SENSE_2 2 + +#define READ_BUFFER_DATA_MODE 0x02 +#define READ_BUFFER_DESCRIPTOR_MODE 0x03 +#define READ_BUFFER_DESCRIPTOR_MODE_DATA_LEN 0x04 + +#define WRITE_BUFFER_DATA_MODE 0x02 +#define WRITE_BUFFER_DL_MICROCODE_SAVE_MODE 0x05 + +/* bit mask */ +#define BIT0_MASK 0x01 +#define BIT1_MASK 0x02 +#define BIT2_MASK 0x04 +#define BIT3_MASK 0x08 +#define BIT4_MASK 0x10 +#define BIT5_MASK 0x20 +#define BIT6_MASK 0x40 +#define BIT7_MASK 0x80 + +#define MODE_SENSE6_RETURN_ALL_PAGES_LEN 68 +#define MODE_SENSE6_CONTROL_PAGE_LEN 24 +#define MODE_SENSE6_READ_WRITE_ERROR_RECOVERY_PAGE_LEN 24 +#define MODE_SENSE6_CACHING_LEN 32 +#define MODE_SENSE6_INFORMATION_EXCEPTION_CONTROL_PAGE_LEN 24 + + +#define MODE_SENSE10_RETURN_ALL_PAGES_LEN 68 + 4 +#define MODE_SENSE10_CONTROL_PAGE_LEN 24 + 4 +#define MODE_SENSE10_READ_WRITE_ERROR_RECOVERY_PAGE_LEN 24 + 4 +#define MODE_SENSE10_CACHING_LEN 32 + 4 +#define MODE_SENSE10_INFORMATION_EXCEPTION_CONTROL_PAGE_LEN 24 + 4 + +#define MODE_SENSE10_RETURN_ALL_PAGES_LLBAA_LEN 68 + 4 + 8 +#define MODE_SENSE10_CONTROL_PAGE_LLBAA_LEN 24 + 4 + 8 +#define MODE_SENSE10_READ_WRITE_ERROR_RECOVERY_PAGE_LLBAA_LEN 24 + 4 + 8 +#define MODE_SENSE10_CACHING_LLBAA_LEN 32 + 4 + 8 +#define MODE_SENSE10_INFORMATION_EXCEPTION_CONTROL_PAGE_LLBAA_LEN 24 + 4 + 8 + +#endif /*__SAT_H__ */ diff --git a/sys/dev/pms/RefTisa/tisa/sassata/sata/host/sathw.c b/sys/dev/pms/RefTisa/tisa/sassata/sata/host/sathw.c new file mode 100644 index 000000000000..ad55937a4c39 --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/sata/host/sathw.c @@ -0,0 +1,621 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +********************************************************************************/ +/*****************************************************************************/ +/** \file + * + * The file implementing LL HW encapsulation for SCSI/ATA Translation (SAT). + * + */ +/*****************************************************************************/ +#include +__FBSDID("$FreeBSD$"); +#include + +#include +#include +#include + +#include +#include +#include + +#ifdef SATA_ENABLE + +#include +#include +#include +#include + +#ifdef FDS_SM +#include +#include +#include +#endif + +#ifdef FDS_DM +#include +#include +#include +#endif + +#include +#include +#include + +#ifdef INITIATOR_DRIVER +#include +#include +#include +#endif + +#ifdef TARGET_DRIVER +#include +#include +#include +#endif + +#include +#include + +#include +#include + +/* + * This table is used to map LL Layer saSATAStart() status to TISA status. + */ +static bit32 mapStat[3] = +{ + tiSuccess, + tiError, + tiBusy +}; + + +/***************************************************************************** + *! \brief sataLLIOStart + * + * This routine is called to initiate a new SATA request to LL layer. + * This function implements/encapsulates HW and LL API dependency. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return: + * + * \e tiSuccess: I/O request successfully initiated. + * \e tiBusy: No resources available, try again later. + * \e tiIONoDevice: Invalid device handle. + * \e tiError: Other errors that prevent the I/O request to be started. + * + * + *****************************************************************************/ + +GLOBAL bit32 sataLLIOStart ( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext + ) +{ + + tdsaDeviceData_t *oneDeviceData; + agsaRoot_t *agRoot; + agsaIORequest_t *agIORequest; + agsaDevHandle_t *agDevHandle; + bit32 status; + tdIORequestBody_t *tdIORequestBody; + agsaSATAInitiatorRequest_t *agSATAReq; + satDeviceData_t *pSatDevData; + satInternalIo_t *satIntIo; + bit32 RLERecovery = agFALSE; + + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + agRoot = oneDeviceData->agRoot; + agDevHandle = oneDeviceData->agDevHandle; + tdIORequestBody = (tdIORequestBody_t *)satIOContext->tiRequestBody; + agSATAReq = &(tdIORequestBody->transport.SATA.agSATARequestBody); + pSatDevData = satIOContext->pSatDevData; + satIntIo = satIOContext->satIntIoContext; + + /* + * If this is a super I/O request, check for optional settings. + * Be careful. Use the superRequest pointer for all references + * in this block of code. + */ + agSATAReq->option = 0; + if (satIOContext->superIOFlag) + { + tiSuperScsiInitiatorRequest_t *superRequest = (tiSuperScsiInitiatorRequest_t *) tiScsiRequest; + agBOOLEAN needPlusDataLenAdjustment = agFALSE; + agBOOLEAN needMinusDataLenAdjustment = agFALSE; + bit32 adjusted_length; + + if (superRequest->flags & TI_SCSI_INITIATOR_ENCRYPT) + { + /* + * Copy all of the relevant encrypt information + */ + agSATAReq->option |= AGSA_SATA_ENABLE_ENCRYPTION; + osti_memcpy(&agSATAReq->encrypt, &superRequest->Encrypt, sizeof(agsaEncrypt_t)); + } + + if (superRequest->flags & TI_SCSI_INITIATOR_DIF) + { + /* + * Copy all of the relevant DIF information + */ + agSATAReq->option |= AGSA_SATA_ENABLE_DIF; + osti_memcpy(&agSATAReq->dif, &superRequest->Dif, sizeof(agsaDif_t)); + + /* + * Set SGL data len + * XXX This code needs to support more sector sizes + */ + if (needPlusDataLenAdjustment == agTRUE) + { + adjusted_length = superRequest->scsiCmnd.expDataLength; + adjusted_length += (adjusted_length/512) * 8; + agSATAReq->dataLength = adjusted_length; + } + else if (needMinusDataLenAdjustment == agTRUE) + { + adjusted_length = superRequest->scsiCmnd.expDataLength; + adjusted_length -= (adjusted_length/520) * 8; + agSATAReq->dataLength = adjusted_length; + } + else + { + /* setting the data length */ + agSATAReq->dataLength = superRequest->scsiCmnd.expDataLength; + } + + tdIORequestBody->IOType.InitiatorRegIO.expDataLength = agSATAReq->dataLength; + } + else + { + /* initialize expDataLength */ + if (satIOContext->reqType == AGSA_SATA_PROTOCOL_NON_DATA || + satIOContext->reqType == AGSA_SATA_PROTOCOL_SRST_ASSERT || + satIOContext->reqType == AGSA_SATA_PROTOCOL_SRST_DEASSERT + ) + { + tdIORequestBody->IOType.InitiatorRegIO.expDataLength = 0; + } + else + { + tdIORequestBody->IOType.InitiatorRegIO.expDataLength = tiScsiRequest->scsiCmnd.expDataLength; + } + + agSATAReq->dataLength = tdIORequestBody->IOType.InitiatorRegIO.expDataLength; + } + } + else + { + agSATAReq->option = 0; + /* initialize expDataLength */ + if (satIOContext->reqType == AGSA_SATA_PROTOCOL_NON_DATA || + satIOContext->reqType == AGSA_SATA_PROTOCOL_SRST_ASSERT || + satIOContext->reqType == AGSA_SATA_PROTOCOL_SRST_DEASSERT + ) + { + tdIORequestBody->IOType.InitiatorRegIO.expDataLength = 0; + } + else + { + tdIORequestBody->IOType.InitiatorRegIO.expDataLength = tiScsiRequest->scsiCmnd.expDataLength; + } + + agSATAReq->dataLength = tdIORequestBody->IOType.InitiatorRegIO.expDataLength; + } + + if ( (pSatDevData->satDriveState == SAT_DEV_STATE_IN_RECOVERY) && + (satIOContext->pFis->h.command == SAT_READ_LOG_EXT) + ) + { + RLERecovery = agTRUE; + } + + /* check max io */ + /* be sure to free */ + if ( (pSatDevData->satDriveState != SAT_DEV_STATE_IN_RECOVERY) || + (RLERecovery == agTRUE) + ) + { + if (RLERecovery == agFALSE) /* RLE is not checked against pending IO's */ + { + if ( (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_WRITE) || + (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_READ) ) + { + if (pSatDevData->satPendingNCQIO >= pSatDevData->satNCQMaxIO || + pSatDevData->satPendingNONNCQIO != 0) + { + TI_DBG1(("sataLLIOStart: 1st busy NCQ. NCQ Pending %d NONNCQ Pending %d\n", pSatDevData->satPendingNCQIO, pSatDevData->satPendingNONNCQIO)); + /* free resource */ + satFreeIntIoResource( tiRoot, + pSatDevData, + satIntIo); + return tiBusy; + } + } + else + { + if (pSatDevData->satPendingNONNCQIO >= SAT_NONNCQ_MAX || + pSatDevData->satPendingNCQIO != 0) + { + TI_DBG1(("sataLLIOStart: 2nd busy NON-NCQ. NCQ Pending %d NON-NCQ Pending %d\n", pSatDevData->satPendingNCQIO, pSatDevData->satPendingNONNCQIO)); + /* free resource */ + satFreeIntIoResource( tiRoot, + pSatDevData, + satIntIo); + return tiBusy; + } + } + } /* RLE */ + /* for internal SATA command only */ + if (satIOContext->satOrgIOContext != agNULL) + { + /* Initialize tiIORequest */ + tdIORequestBody->tiIORequest = tiIORequest; + } + /* Initialize tiDevhandle */ + tdIORequestBody->tiDevHandle = tiDeviceHandle; + + /* Initializes Scatter Gather and ESGL */ + status = itdsataIOPrepareSGL( tiRoot, + tdIORequestBody, + &tiScsiRequest->agSgl1, + tiScsiRequest->sglVirtualAddr ); + + if (status != tiSuccess) + { + TI_DBG1(("sataLLIOStart: can't get SGL\n")); + return status; + } + + + /* Initialize LL Layer agIORequest */ + agIORequest = &(tdIORequestBody->agIORequest); + agIORequest->osData = (void *) tdIORequestBody; + agIORequest->sdkData = agNULL; /* SA takes care of this */ + + tdIORequestBody->ioStarted = agTRUE; + tdIORequestBody->ioCompleted = agFALSE; + + /* + + #ifdef PRE_SALL_v033 +GLOBAL bit32 saSATAStart( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + agsaDevHandle_t *agDevHandle, + bit32 agRequestType, + agsaSATAInitiatorRequest_t *agSATAReq, + bit8 *agTag + ); +#endif +GLOBAL bit32 saSATAStart( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + agsaDevHandle_t *agDevHandle, + bit32 agRequestType, + agsaSATAInitiatorRequest_t *agSATAReq, + bit8 agTag, + ossaSATACompletedCB_t agCB + ); + */ + + /* assign tag value for SATA */ + if ( (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_WRITE) || + (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_READ) ) + { + if (agFALSE == satTagAlloc(tiRoot, pSatDevData, &satIOContext->sataTag)) + { + TI_DBG1(("sataLLIOStart: No more NCQ tag\n")); + tdIORequestBody->ioStarted = agFALSE; + tdIORequestBody->ioCompleted = agTRUE; + return tiBusy; + } + TI_DBG3(("sataLLIOStart: ncq tag 0x%x\n",satIOContext->sataTag)); + } + else + { + satIOContext->sataTag = 0xFF; + } + } + else /* AGSA_SATA_PROTOCOL_SRST_ASSERT or AGSA_SATA_PROTOCOL_SRST_DEASSERT + or SAT_CHECK_POWER_MODE as ABORT */ + { + agsaSgl_t *agSgl; + + /* for internal SATA command only */ + if (satIOContext->satOrgIOContext != agNULL) + { + /* Initialize tiIORequest */ + tdIORequestBody->tiIORequest = tiIORequest; + } + /* Initialize tiDevhandle */ + tdIORequestBody->tiDevHandle = tiDeviceHandle; + + + tdIORequestBody->IOType.InitiatorRegIO.expDataLength = 0; + /* SGL for SATA request */ + agSgl = &(tdIORequestBody->transport.SATA.agSATARequestBody.agSgl); + agSgl->len = 0; + + agSgl->sgUpper = 0; + agSgl->sgLower = 0; + agSgl->len = 0; + CLEAR_ESGL_EXTEND(agSgl->extReserved); + + /* Initialize LL Layer agIORequest */ + agIORequest = &(tdIORequestBody->agIORequest); + agIORequest->osData = (void *) tdIORequestBody; + agIORequest->sdkData = agNULL; /* SA takes care of this */ + + tdIORequestBody->ioStarted = agTRUE; + tdIORequestBody->ioCompleted = agFALSE; + + /* setting the data length */ + agSATAReq->dataLength = 0; + + } + + tdIORequestBody->reTries = 0; + osti_memset(agSATAReq->scsiCDB, 0, 16); + osti_memcpy(agSATAReq->scsiCDB, tiScsiRequest->scsiCmnd.cdb, 16); +#ifdef TD_INTERNAL_DEBUG + tdhexdump("sataLLIOStart", (bit8 *)satIOContext->pFis, sizeof(agsaFisRegHostToDevice_t)); + tdhexdump("sataLLIOStart LL", (bit8 *)&agSATAReq->fis.fisRegHostToDev, + sizeof(agsaFisRegHostToDevice_t)); +#endif + + TI_DBG6(("sataLLIOStart: agDevHandle %p\n", agDevHandle)); + status = saSATAStart( agRoot, + agIORequest, + tdsaRotateQnumber(tiRoot, oneDeviceData), + agDevHandle, + satIOContext->reqType, + agSATAReq, + satIOContext->sataTag, + ossaSATACompleted + ); + + if (status == AGSA_RC_SUCCESS) + { + tdsaSingleThreadedEnter(tiRoot, TD_SATA_LOCK); + oneDeviceData->satDevData.satPendingIO++; + if ( (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_WRITE) || + (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_READ) ) + { + oneDeviceData->satDevData.satPendingNCQIO++; + } + else + { + oneDeviceData->satDevData.satPendingNONNCQIO++; + } + + TDLIST_INIT_ELEMENT (&satIOContext->satIoContextLink); + TDLIST_ENQUEUE_AT_TAIL (&satIOContext->satIoContextLink, + &oneDeviceData->satDevData.satIoLinkList); + tdsaSingleThreadedLeave(tiRoot, TD_SATA_LOCK); + // TI_DBG5(("sataLLIOStart: device %p pending IO %d\n", oneDeviceData->satDevData,oneDeviceData->satDevData.satPendingIO)); + } + else + { + if (status == AGSA_RC_BUSY) + { + TI_DBG1(("sataLLIOStart: saSATAStart busy\n")); + } + else + { + TI_DBG1(("sataLLIOStart: saSATAStart failed\n")); + } + if ( (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_WRITE) || + (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_READ) ) + { + satTagRelease(tiRoot, pSatDevData, satIOContext->sataTag); + } + + /* Free the ESGL pages associated with this I/O */ + tdIORequestBody->ioStarted = agFALSE; + tdIORequestBody->ioCompleted = agTRUE; + /* + * Map the SAS/SATA LL layer status to the TISA status + */ + status = mapStat[status]; + return (status); + } + + return (tiSuccess); + +} + + +/***************************************************************************** +*! \brief itdsataIOPrepareSGL +* +* This function is called to prepare and translate the TISA SGL information +* to the SAS/SATA LL layer specific SGL. This function is similar to +* itdssIOPrepareSGL(), except the request body reflects SATA host request. +* +* \param tiRoot: Pointer to initiator driver/port instance. +* \param IORequestBody: TD layer request body for the I/O. +* \param tiSgl1: First TISA SGL info. +* \param tiSgl2: Second TISA SGL info. +* \param sglVirtualAddr: The virtual address of the first element in +* tiSgl1 when tiSgl1 is used with the type tiSglList. +* +* \return: +* +* \e tiSuccess: SGL initialized successfully. +* \e tiError: Failed to initialize SGL. +* +* +*****************************************************************************/\ +osGLOBAL bit32 itdsataIOPrepareSGL( + tiRoot_t *tiRoot, + tdIORequestBody_t *tdIORequestBody, + tiSgl_t *tiSgl1, + void *sglVirtualAddr + ) +{ + agsaSgl_t *agSgl; + + /* Uppper should be zero-out */ + TI_DBG5(("itdsataIOPrepareSGL: start\n")); + + TI_DBG5(("itdsataIOPrepareSGL: tiSgl1->upper %d tiSgl1->lower %d tiSgl1->len %d\n", + tiSgl1->upper, tiSgl1->lower, tiSgl1->len)); + TI_DBG5(("itdsataIOPrepareSGL: tiSgl1->type %d\n", tiSgl1->type)); + + /* SGL for SATA request */ + agSgl = &(tdIORequestBody->transport.SATA.agSATARequestBody.agSgl); + agSgl->len = 0; + + if (tiSgl1 == agNULL) + { + TI_DBG1(("itdsataIOPrepareSGL: Error tiSgl1 is NULL\n")); + return tiError; + } + + if (tdIORequestBody->IOType.InitiatorRegIO.expDataLength == 0) + { + TI_DBG3(("itdsataIOPrepareSGL: expDataLength is 0\n")); + agSgl->sgUpper = 0; + agSgl->sgLower = 0; + agSgl->len = 0; + CLEAR_ESGL_EXTEND(agSgl->extReserved); + return tiSuccess; + } + + agSgl->sgUpper = tiSgl1->upper; + agSgl->sgLower = tiSgl1->lower; + agSgl->len = tiSgl1->len; + agSgl->extReserved = tiSgl1->type; + + return tiSuccess; + +} + +/***************************************************************************** + *! \brief sataLLIOAbort + * + * This routine is called to initiate an I/O abort to LL layer. + * This function implements/encapsulates HW and LL API dependency. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param taskTag: Pointer to TISA I/O context to be aborted. + * + * \return: + * + * \e tiSuccess: Abort request was successfully initiated. + * \e tiBusy: No resources available, try again later. + * \e tiError: Other errors that prevent the abort request from being + * started.. + * + * + *****************************************************************************/ +#ifdef REMOVED /* not in use */ +GLOBAL bit32 sataLLIOAbort ( + tiRoot_t *tiRoot, + tiIORequest_t *taskTag ) + +{ + tdsaRoot_t *tdsaRoot; + tdsaContext_t *tdsaAllShared; + agsaRoot_t *agRoot; + tdIORequestBody_t *tdIORequestBody; + agsaIORequest_t *agIORequest; + bit32 status; + + TI_DBG2(("sataLLIOAbort: start\n")); + + tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + agRoot = &(tdsaAllShared->agRootNonInt); + tdIORequestBody = (tdIORequestBody_t *)taskTag->tdData; + agIORequest = &(tdIORequestBody->agIORequest); + + status = saSATAAbort(agRoot, 0, agIORequest); + + TI_DBG2(("sataLLIOAbort: agIORequest %p\n", agIORequest)); + TI_DBG2(("sataLLIOAbort: saSATAAbort returns status, %x\n", status)); + + if (status == AGSA_RC_SUCCESS) + { + return tiSuccess; + } + else + { + return tiError; + } + +} +#endif + +#ifdef REMOVED +/***************************************************************************** + *! \brief sataLLReset + * + * This routine is called to initiate a SATA device reset to LL layer. + * This function implements/encapsulates HW and LL API dependency. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param option: SATA device reset option + * + * \return: None + * + * + *****************************************************************************/ +/* not in use */ +GLOBAL void sataLLReset( + tiRoot_t *tiRoot, + tiDeviceHandle_t *tiDeviceHandle, + bit32 option) +{ + + tdsaRoot_t *tdsaRoot; + tdsaContext_t *tdsaAllShared; + tdsaDeviceData_t *oneDeviceData; + agsaRoot_t *agRoot; + agsaDevHandle_t *agDevHandle; + + TI_DBG2(("sataLLReset: extry\n")); + + tdsaRoot = (tdsaRoot_t *) tiRoot->tdData; + tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared; + agRoot = &(tdsaAllShared->agRootNonInt); + oneDeviceData = (tdsaDeviceData_t *)tiDeviceHandle->tdData; + agDevHandle = oneDeviceData->agDevHandle; + + satSATADeviceReset( tiRoot, + oneDeviceData, + AGSA_PHY_HARD_RESET); + +} +#endif /* 0 */ +#endif /* #ifdef SATA_ENABLE */ diff --git a/sys/dev/pms/RefTisa/tisa/sassata/sata/host/satproto.h b/sys/dev/pms/RefTisa/tisa/sassata/sata/host/satproto.h new file mode 100644 index 000000000000..516c6d002c0a --- /dev/null +++ b/sys/dev/pms/RefTisa/tisa/sassata/sata/host/satproto.h @@ -0,0 +1,2856 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ +/*******************************************************************************/ +/** \file + * + * + * The file contaning function protoptype used by SAT layer. + * + */ + +#ifndef __SATPROTO_H__ +#define __SATPROTO_H__ + + +/***************************************************************************** +*! \brief itdsatProcessAbnormalCompletion +* +* This routine is called to complete error case for SATA request previously +* issued to the LL Layer in saSATAStart() +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agSATAParm1: Additional info based on status. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param satIOContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void itdsatProcessAbnormalCompletion( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + satIOContext_t *satIOContext + ); +void itdsatDelayedProcessAbnormalCompletion( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + satIOContext_t *satIOContext + ); + +void itdsatErrorSATAEventHandle( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + agsaPortContext_t *agPortContext, + agsaDevHandle_t *agDevHandle, + bit32 event, + satIOContext_t *ioContext + ); + +void itdsatEncryptionHandler ( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); + +osGLOBAL void +itdsatDifHandler( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + bit32 agIOInfoLen, + void *agParam, + bit32 agOtherInfo + ); + +void satProcessAbort( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + satIOContext_t *satIOContext + ); +/*****************************************************************************/ +/*! \brief Setup up the SCSI Sense response. + * + * This function is used to setup up the Sense Data payload for + * CHECK CONDITION status. + * + * \param pSense: Pointer to the scsiRspSense_t sense data structure. + * \param SnsKey: SCSI Sense Key. + * \param SnsInfo: SCSI Sense Info. + * \param SnsCode: SCSI Sense Code. + * + * \return None + */ +/*****************************************************************************/ + +void satSetSensePayload( scsiRspSense_t *pSense, + bit8 SnsKey, + bit32 SnsInfo, + bit16 SnsCode, + satIOContext_t *satIOContext); + + +/*****************************************************************************/ +/*! \brief Setup up the SCSI Sense response. + * + * This function is used to setup up the Sense Data payload for + * CHECK CONDITION status. + * + * \param pSense: Pointer to the scsiRspSense_t sense data structure. + * \param SnsKey: SCSI Sense Key. + * \param SnsInfo: SCSI Sense Info. + * \param SnsCode: SCSI Sense Code. + * + * \return None + */ +/*****************************************************************************/ + +void satSetDeferredSensePayload( scsiRspSense_t *pSense, + bit8 SnsKey, + bit32 SnsInfo, + bit16 SnsCode, + satIOContext_t *satIOContext + ); + +/*****************************************************************************/ +/*! \brief SAT implementation for ATAPI Packet Command. + * + * SAT implementation for ATAPI Packet and send FIS request to LL layer. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satPacket( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +void satPacketCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ); +/*****************************************************************************/ +/*! \brief SAT implementation for satDeviceReset. + * + * This function creates DEVICE RESET fis and sends the request to LL layer + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satDeviceReset( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext + ); + +void satDeviceResetCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ); + +/*****************************************************************************/ +/*! \brief SAT implementation for satExecuteDeviceDiagnostic. + * + * This function creates Execute Device Diagnostic fis and sends the request to LL layer + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satExecuteDeviceDiagnostic( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext + ); + +void satExecuteDeviceDiagnosticCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ); + +/*****************************************************************************/ +/*! \brief SAT implementation for satSetFeatures. + * + * This function creates SetFeatures fis and sends the request to LL layer + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satSetFeatures( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext, + bit8 bTransferMode + ); + void satSetFeaturesPIOCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ); + + void satSetFeaturesCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ); +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI REQUEST SENSE to ATAPI device. + * + * SAT implementation for SCSI REQUEST SENSE. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satRequestSenseForATAPI( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + + void satRequestSenseForATAPICB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + void *agParam, + void *ioContext + ); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI READ12. + * + * SAT implementation for SCSI READ12 and send FIS request to LL layer. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satRead12( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI READ10. + * + * SAT implementation for SCSI READ10 and send FIS request to LL layer. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satRead10( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI READ16. + * + * SAT implementation for SCSI READ16 and send FIS request to LL layer. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satRead16( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI READ6. + * + * SAT implementation for SCSI READ6 and send FIS request to LL layer. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satRead6( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI WRITE16. + * + * SAT implementation for SCSI WRITE16 and send FIS request to LL layer. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satWrite16( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI WRITE12. + * + * SAT implementation for SCSI WRITE12 and send FIS request to LL layer. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satWrite12( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI WRITE10. + * + * SAT implementation for SCSI WRITE10 and send FIS request to LL layer. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satWrite10( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); +GLOBAL bit32 satWrite_1( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI WRITE6. + * + * SAT implementation for SCSI WRITE6 and send FIS request to LL layer. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satWrite6( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satReportLun. + * + * SAT implementation for SCSI satReportLun. Only LUN0 is reported. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satReportLun( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satReadCapacity10. + * + * SAT implementation for SCSI satReadCapacity10. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satReadCapacity10( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satReadCapacity16. + * + * SAT implementation for SCSI satReadCapacity16. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satReadCapacity16( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + + +GLOBAL bit32 satInquiry( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI REQUEST SENSE. + * + * SAT implementation for SCSI REQUEST SENSE. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satRequestSense( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI REQUEST SENSE. + * + * SAT implementation for SCSI REQUEST SENSE. + * Sub function of satRequestSense + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satRequestSense_1( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satFormatUnit. + * + * SAT implementation for SCSI satFormatUnit. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satFormatUnit( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satSendDiagnostic. + * + * SAT implementation for SCSI satSendDiagnostic. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satSendDiagnostic( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satSendDiagnostic_1. + * + * SAT implementation for SCSI satSendDiagnostic_1. + * Sub function of satSendDiagnostic. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satSendDiagnostic_1( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satSendDiagnostic_2. + * + * SAT implementation for SCSI satSendDiagnostic_2. + * Sub function of satSendDiagnostic. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satSendDiagnostic_2( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satStartStopUnit. + * + * SAT implementation for SCSI satStartStopUnit. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satStartStopUnit( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satStartStopUnit_1. + * + * SAT implementation for SCSI satStartStopUnit_1. + * Sub function of satStartStopUnit + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satStartStopUnit_1( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satRead10_1. + * + * SAT implementation for SCSI satRead10_1 + * Sub function of satRead10 + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satRead_1( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); +GLOBAL bit32 satRead10_2( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satWriteSame10. + * + * SAT implementation for SCSI satWriteSame10. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satWriteSame10( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +GLOBAL bit32 satWriteSame10_1( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext, + bit32 lba + ); +GLOBAL bit32 satWriteSame10_2( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext, + bit32 lba + ); +GLOBAL bit32 satWriteSame10_3( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext, + bit32 lba + ); +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satWriteSame16. + * + * SAT implementation for SCSI satWriteSame16. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satWriteSame16( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satLogSenseAllocate. + * + * Part of SAT implementation for SCSI satLogSense. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * \param payloadSize: size of payload to be allocated. + * \param flag: flag value + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + * \note + * - flag values: LOG_SENSE_0, LOG_SENSE_1, LOG_SENSE_2 + */ +/*****************************************************************************/ +GLOBAL bit32 satLogSenseAllocate( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext, + bit32 payloadSize, + bit32 flag + ); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satSMARTEnable. + * + * Part of SAT implementation for SCSI satLogSense. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satSMARTEnable( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satLogSense_1. + * + * Part of SAT implementation for SCSI satLogSense. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satLogSense_1( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satLogSense_2. + * + * Part of SAT implementation for SCSI satLogSense. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satLogSense_2( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satLogSense_3. + * + * Part of SAT implementation for SCSI satLogSense. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satLogSense_3( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satLogSense. + * + * SAT implementation for SCSI satLogSense. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satLogSense( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satModeSelect6. + * + * SAT implementation for SCSI satModeSelect6. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satModeSelect6( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); +GLOBAL bit32 satModeSelect6n10_1( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satModeSelect10. + * + * SAT implementation for SCSI satModeSelect10. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satModeSelect10( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satSynchronizeCache10. + * + * SAT implementation for SCSI satSynchronizeCache10. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satSynchronizeCache10( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satSynchronizeCache16. + * + * SAT implementation for SCSI satSynchronizeCache16. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satSynchronizeCache16( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satWriteAndVerify10. + * + * SAT implementation for SCSI satWriteAndVerify10. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satWriteAndVerify10( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +#ifdef REMOVED +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satWriteAndVerify10_1. + * + * SAT implementation for SCSI satWriteAndVerify10_1. + * Sub function of satWriteAndVerify10 + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satWriteAndVerify10_1( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); +#endif + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satWriteAndVerify12. + * + * SAT implementation for SCSI satWriteAndVerify12. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satWriteAndVerify12( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +GLOBAL bit32 satNonChainedWriteNVerify_Verify( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +GLOBAL bit32 satChainedWriteNVerify_Write( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +GLOBAL bit32 satChainedWriteNVerify_Verify( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +GLOBAL bit32 satChainedWriteNVerify_Start_Verify( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satWriteAndVerify16. + * + * SAT implementation for SCSI satWriteAndVerify16. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satWriteAndVerify16( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +GLOBAL bit32 satChainedVerify16( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI TEST UNIT READY. + * + * SAT implementation for SCSI TUR and send FIS request to LL layer. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satTestUnitReady( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI MODE SENSE (6). + * + * SAT implementation for SCSI MODE SENSE (6). + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satModeSense6( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI MODE SENSE (10). + * + * SAT implementation for SCSI MODE SENSE (10). + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satModeSense10( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI VERIFY (10). + * + * SAT implementation for SCSI VERIFY (10). + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satVerify10( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +GLOBAL bit32 satChainedVerify( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI VERIFY (12). + * + * SAT implementation for SCSI VERIFY (12). + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satVerify12( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI VERIFY (16). + * + * SAT implementation for SCSI VERIFY (16). + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satVerify16( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satTestUnitReady_1. + * + * SAT implementation for SCSI satTestUnitReady_1 + * Sub function of satTestUnitReady + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satTestUnitReady_1( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI STANDARD INQUIRY. + * + * SAT implementation for SCSI STANDARD INQUIRY. + * + * \param pInquiry: Pointer to Inquiry Data buffer. + * \param pSATAIdData: Pointer to ATA IDENTIFY DEVICE data. + * + * \return None. + */ +/*****************************************************************************/ +GLOBAL void satInquiryStandard( + bit8 *pInquiry, + agsaSATAIdentifyData_t *pSATAIdData, + tiIniScsiCmnd_t *scsiCmnd + ); + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI INQUIRY page 0. + * + * SAT implementation for SCSI INQUIRY page 0. + * + * \param pInquiry: Pointer to Inquiry Data buffer. + * \param pSATAIdData: Pointer to ATA IDENTIFY DEVICE data. + * + * \return None. + */ +/*****************************************************************************/ +GLOBAL void satInquiryPage0( + bit8 *pInquiry, + agsaSATAIdentifyData_t *pSATAIdData); + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI INQUIRY page 83. + * + * SAT implementation for SCSI INQUIRY page 83. + * + * \param pInquiry: Pointer to Inquiry Data buffer. + * \param pSATAIdData: Pointer to ATA IDENTIFY DEVICE data. + * \param pSatDevData Pointer to internal device data structure + * + * \return None. + */ +/*****************************************************************************/ +GLOBAL void satInquiryPage83( + bit8 *pInquiry, + agsaSATAIdentifyData_t *pSATAIdData, + satDeviceData_t *pSatDevData); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI INQUIRY page 89. + * + * SAT implementation for SCSI INQUIRY page 89. + * + * \param pInquiry: Pointer to Inquiry Data buffer. + * \param pSATAIdData: Pointer to ATA IDENTIFY DEVICE data. + * \param pSatDevData Pointer to internal device data structure + * + * \return None. + */ +/*****************************************************************************/ +GLOBAL void satInquiryPage89( + bit8 *pInquiry, + agsaSATAIdentifyData_t *pSATAIdData, + satDeviceData_t *pSatDevData); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI INQUIRY page 80. + * + * SAT implementation for SCSI INQUIRY page 80. + * + * \param pInquiry: Pointer to Inquiry Data buffer. + * \param pSATAIdData: Pointer to ATA IDENTIFY DEVICE data. + * + * \return None. + */ +/*****************************************************************************/ +GLOBAL void satInquiryPage80( + bit8 *pInquiry, + agsaSATAIdentifyData_t *pSATAIdData); + + +/***************************************************************************** + *! \brief sataLLIOStart + * + * This routine is called to initiate a new SATA request to LL layer. + * This function implements/encapsulates HW and LL API dependency. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return: + * + * tiSuccess: I/O request successfully initiated. + * tiBusy: No resources available, try again later. + * tiIONoDevice: Invalid device handle. + * tiError: Other errors that prevent the I/O request to be started. + * + * + *****************************************************************************/ + +GLOBAL bit32 sataLLIOStart ( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext + ); + +/***************************************************************************** +*! \brief itdsataIOPrepareSGL +* +* This function is called to prepare and translate the TISA SGL information +* to the SAS/SATA LL layer specific SGL. +* +* \param tiRoot: Pointer to initiator driver/port instance. +* \param IORequestBody: TD layer request body for the I/O. +* \param tiSgl1: First TISA SGL info. +* \param sglVirtualAddr: The virtual address of the first element in +* tiSgl1 when tiSgl1 is used with the type tiSglList. +* +* \return: +* +* tiSuccess: SGL initialized successfully. +* tiError: Failed to initialize SGL. +* +* +*****************************************************************************/ +osGLOBAL bit32 itdsataIOPrepareSGL( + tiRoot_t *tiRoot, + tdIORequestBody_t *tdIORequestBody, + tiSgl_t *tiSgl1, + void *sglVirtualAddr + ); + +/***************************************************************************** +*! \brief satNonChainedDataIOCB +* +* This routine is a callback function called from ossaSATACompleted(). +* This CB routine deals with normal non-chained data I/O SATA request. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agSATAParm1: Additional info based on status. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ + +void satNonChainedDataIOCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); +void satChainedDataIOCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); + +void satNonChainedWriteNVerifyCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); + +void satChainedWriteNVerifyCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); + +/***************************************************************************** +*! \brief satNonDataIOCB +* +* This routine is a callback function called from ossaSATACompleted(). +* This CB routine deals with non-data I/O SATA request. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agSATAParm1: Additional info based on status. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void satNonDataIOCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); + +/***************************************************************************** +*! \brief satSMARTEnableCB +* +* This routine is a callback function for satSMARTEnable() +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agSATAParm1: Additional info based on status. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void satSMARTEnableCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ) ; + +/***************************************************************************** +*! \brief satLogSenseCB +* +* This routine is a callback function for satLogSense() +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agSATAParm1: Additional info based on status. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void satLogSenseCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioCotext + ); +void satModeSelect6n10CB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); +void satSynchronizeCache10n16CB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); +#ifdef REMOVED +void satWriteAndVerify10CB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); +#endif + +/***************************************************************************** +*! \brief satReadLogExtCB +* +* This routine is a callback function called from ossaSATACompleted(). +* This CB routine deals READ LOG EXT completion. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agSATAParm1: Additional info based on status. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void satReadLogExtCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); +void satTestUnitReadyCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); +void satWriteSame10CB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); +/***************************************************************************** +*! \brief satSendDiagnosticCB +* +* This routine is a callback function called from ossaSATACompleted(). +* This CB routine deals with Send Diagnostic completion. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agSATAParm1: Additional info based on status. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void satSendDiagnosticCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); +/***************************************************************************** +*! \brief satRequestSenseCB +* +* This routine is a callback function called from ossaSATACompleted(). +* This CB routine deals with Request Sense completion. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agSATAParm1: Additional info based on status. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void satRequestSenseCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); +/***************************************************************************** +*! \brief satStartStopUnitCB +* +* This routine is a callback function called from ossaSATACompleted(). +* This CB routine deals with Send Diagnostic completion. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agSATAParm1: Additional info based on status. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void satStartStopUnitCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); +/***************************************************************************** +*! \brief satVerify10CB +* +* This routine is a callback function called from ossaSATACompleted(). +* This CB routine deals with Verify(10) completion. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agSATAParm1: Additional info based on status. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void satVerify10CB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContex + ); + +void satNonChainedVerifyCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); + +void satChainedVerifyCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); + +/***************************************************************************** + *! \brief satTmResetLUN + * + * This routine is called to initiate a TM RESET LUN request to SATL. + * This routine is independent of HW/LL API. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param lun: Pointer to LUN. + * \param currentTaskTag: Pointer to tag/context for this TM request. + * + * \return: + * + * \e tiSuccess: I/O request successfully initiated. + * \e tiBusy: No resources available, try again later. + * \e tiIONoDevice: Invalid device handle. + * \e tiError: Other errors that prevent the I/O request to be started. + * + * + *****************************************************************************/ +osGLOBAL bit32 satTmResetLUN( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext, + tiLUN_t *lun); + +osGLOBAL bit32 satTmWarmReset( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +osGLOBAL bit32 satTDInternalTmReset( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +/***************************************************************************** + *! \brief satTmAbortTask + * + * This routine is called to initiate a TM ABORT TASK request to SATL. + * This routine is independent of HW/LL API. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param taskTag: Pointer to the associated task where the TM + * command is to be applied. + * \param currentTaskTag: Pointer to tag/context for this TM request. + * + * \return: + * + * \e tiSuccess: I/O request successfully initiated. + * \e tiBusy: No resources available, try again later. + * \e tiIONoDevice: Invalid device handle. + * \e tiError: Other errors that prevent the I/O request to be started. + * + * + *****************************************************************************/ +osGLOBAL bit32 satTmAbortTask( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext, + tiIORequest_t *taskTag); + +/***************************************************************************** + *! \brief osSatResetCB + * + * This routine is called to notify the completion of SATA device reset + * which was initiated previously through the call to sataLLReset(). + * This routine is independent of HW/LL API. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param resetStatus: Reset status either tiSuccess or tiError. + * \param respFis: Pointer to the Register Device-To-Host FIS + * received from the device. + * + * \return: None + * + *****************************************************************************/ + +osGLOBAL void osSatResetCB( + tiRoot_t *tiRoot, + tiDeviceHandle_t *tiDeviceHandle, + bit32 resetStatus, + void *respFis); + +osGLOBAL void +ossaSATADeviceResetCB( + agsaRoot_t *agRoot, + agsaDevHandle_t *agDevHandle, + bit32 resetStatus, + void *resetparm); + +/***************************************************************************** + *! \brief osSatIOCompleted + * + * This routine is a callback for SATA completion that required FIS status + * translation to SCSI status. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param respFis: Pointer to status FIS to read. + * \param respFisLen: Length of response FIS to read. + * \param satIOContext: Pointer to SAT context. + * \param interruptContext: Interrupt context + * + * \return: None + * + *****************************************************************************/ +osGLOBAL void osSatIOCompleted( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + agsaFisHeader_t *agFirstDword, + bit32 respFisLen, + agsaFrameHandle_t agFrameHandle, + satIOContext_t *satIOContext, + bit32 interruptContext); + + +/***************************************************************************** +*! \brief tdssAddSataToSharedcontext +* +* Purpose: This function adds a discovered SATA device to a device list of +* a port context +* +* \param tdsaPortContext Pointer to a port context +* \param tdsaDeviceData Pointer to a device data +* \param tsddPortContext_Instance Pointer to the target port context +* \param agRoot Pointer to the root data structure of +* TD and Lower layer +* \param agDevHandle Pointer to a device handle +* \param agSATADeviceInfo Pointer to SATA device info structure +* +* \Return: none +* +*****************************************************************************/ +osGLOBAL void +tdssRemoveSATAFromSharedcontext( + tdsaPortContext_t *tdsaPortContext_Ins, + tdsaDeviceData_t *tdsaDeviceData_ins, + agsaRoot_t *agRoot + ); + +/*****************************************************************************/ +/*! \brief SAT default ATA status and ATA error translation to SCSI. + * + * SSAT default ATA status and ATA error translation to SCSI. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param satIOContext: Pointer to the SAT IO Context + * \param pSense: Pointer to scsiRspSense_t + * \param ataStatus: ATA status register + * \param ataError: ATA error register + * \param interruptContext: Interrupt context + * + * \return None + */ +/*****************************************************************************/ + +GLOBAL void osSatDefaultTranslation( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + satIOContext_t *satIOContext, + scsiRspSense_t *pSense, + bit8 ataStatus, + bit8 ataError, + bit32 interruptContext ); + +/*****************************************************************************/ +/*! \brief Allocate resource for SAT intervally generated I/O. + * + * Allocate resource for SAT intervally generated I/O. + * + * \param tiRoot: Pointer to TISA driver/port instance. + * \param satDevData: Pointer to SAT specific device data. + * \param allocLength: Length in byte of the DMA mem to allocate, upto + * one page size. + * \param satIntIo: Pointer (output) to context for SAT internally + * generated I/O that is allocated by this routine. + * + * \return If command is started successfully + * - \e tiSuccess: Success. + * - \e tiError: Failed allocating resource. + */ +/*****************************************************************************/ +GLOBAL satInternalIo_t * satAllocIntIoResource( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + satDeviceData_t *satDevData, + bit32 dmaAllocLength, + satInternalIo_t *satIntIo); + +/*****************************************************************************/ +/*! \brief Send READ LOG EXT ATA PAGE 10h command to sata drive. + * + * Send READ LOG EXT ATA command PAGE 10h request to LL layer. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satSendReadLogExt( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satReadMediaSerialNumber. + * + * SAT implementation for SCSI Read Media Serial Number. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satReadMediaSerialNumber( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +/***************************************************************************** +*! \brief satReadMediaSerialNumberCB +* +* This routine is a callback function called from ossaSATACompleted(). +* This CB routine deals with Read Media Serial Number completion. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agSATAParm1: Additional info based on status. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void satReadMediaSerialNumberCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satReadBuffer. + * + * SAT implementation for SCSI Read Buffer. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satReadBuffer( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +/***************************************************************************** +*! \brief satReadBufferCB +* +* This routine is a callback function called from ossaSATACompleted(). +* This CB routine deals with Read Buffer. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agSATAParm1: Additional info based on status. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void satReadBufferCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satWriteBuffer. + * + * SAT implementation for SCSI Write Buffer. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satWriteBuffer( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +/***************************************************************************** +*! \brief satWriteBufferCB +* +* This routine is a callback function called from ossaSATACompleted(). +* This CB routine deals with Write Buffer. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agSATAParm1: Additional info based on status. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void satWriteBufferCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satReassignBlocks. + * + * SAT implementation for SCSI Reassign Blocks. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satReassignBlocks( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + +/***************************************************************************** +*! \brief satReassignBlocksCB +* +* This routine is a callback function called from ossaSATACompleted(). +* This CB routine deals with Reassign Blocks. +* +* \param agRoot: Handles for this instance of SAS/SATA hardware +* \param agIORequest: Pointer to the LL I/O request context for this I/O. +* \param agIOStatus: Status of completed I/O. +* \param agSATAParm1: Additional info based on status. +* \param agIOInfoLen: Length in bytes of overrun/underrun residual or FIS +* length. +* \param ioContext: Pointer to satIOContext_t. +* +* \return: none +* +*****************************************************************************/ +void satReassignBlocksCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satReassignBlocks_1. + * + * SAT implementation for SCSI Reassign Blocks. This is helper function for + * satReassignBlocks and satReassignBlocksCB. This sends ATA verify command. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satReassignBlocks_1( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext, + satIOContext_t *satOrgIOContext); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satReassignBlocks_2. + * + * SAT implementation for SCSI Reassign Blocks. This is helper function for + * satReassignBlocks and satReassignBlocksCB. This sends ATA write command. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param tiIORequest: Pointer to TISA I/O request context for this I/O. + * \param tiDeviceHandle: Pointer to TISA device handle for this I/O. + * \param tiScsiRequest: Pointer to TISA SCSI I/O request and SGL list. + * \param satIOContext_t: Pointer to the SAT IO Context + * \param LBA: Pointer to the LBA to be processed + * + * \return If command is started successfully + * - \e tiSuccess: I/O request successfully initiated. + * - \e tiBusy: No resources available, try again later. + * - \e tiIONoDevice: Invalid device handle. + * - \e tiError: Other errors. + */ +/*****************************************************************************/ +GLOBAL bit32 satReassignBlocks_2( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext, + bit8 *LBA + ); + +/*****************************************************************************/ +/*! \brief SAT implementation for SCSI satPrepareNewIO. + * + * This function fills in the fields of internal IO generated by TD layer. + * This is mostly used in the callback functions. + * + * \param satNewIntIo: Pointer to the internal IO structure. + * \param tiOrgIORequest: Pointer to the original tiIOrequest sent by OS layer + * \param satDevData: Pointer to the device data. + * \param scsiCmnd: Pointer to SCSI command. + * \param satOrgIOContext: Pointer to the original SAT IO Context + * + * \return + * - \e Pointer to the new SAT IO Context + */ +/*****************************************************************************/ +GLOBAL satIOContext_t *satPrepareNewIO( + satInternalIo_t *satNewIntIo, + tiIORequest_t *tiOrgIORequest, + satDeviceData_t *satDevData, + tiIniScsiCmnd_t *scsiCmnd, + satIOContext_t *satOrgIOContext + ); + +/***************************************************************************** + *! \brief sataLLIOAbort + * + * This routine is called to initiate an I/O abort to LL layer. + * This function implements/encapsulates HW and LL API dependency. + * + * \param tiRoot: Pointer to TISA initiator driver/port instance. + * \param taskTag: Pointer to TISA I/O context to be aborted. + * + * \return: + * + * \e tiSuccess: Abort request was successfully initiated. + * \e tiBusy: No resources available, try again later. + * \e tiError: Other errors that prevent the abort request from being + * started.. + * + * + *****************************************************************************/ + +GLOBAL bit32 sataLLIOAbort ( + tiRoot_t *tiRoot, + tiIORequest_t *taskTag ); + + + +void satInquiryCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); + +void satInquiryIntCB( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext + ); + +GLOBAL bit32 satSendIDDev( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext); + + +GLOBAL bit32 satStartIDDev( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext + ); + +void satSetDevInfo( + satDeviceData_t *satDevData, + agsaSATAIdentifyData_t *SATAIdData + ); + +GLOBAL bit32 satAddSATAStartIDDev( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext + ); + +GLOBAL bit32 satAddSATASendIDDev( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext + ); + +void satAddSATAIDDevCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); + +void satAddSATAIDDevCBReset( + agsaRoot_t *agRoot, + tdsaDeviceData_t *oneDeviceData, + satIOContext_t *satIOContext, + tdIORequestBody_t *tdIORequestBody + ); + +void satAddSATAIDDevCBCleanup( + agsaRoot_t *agRoot, + tdsaDeviceData_t *oneDeviceData, + satIOContext_t *satIOContext, + tdIORequestBody_t *tdIORequestBody + ); + +GLOBAL bit32 tdsaDiscoveryIntStartIDDev( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext + ); + +GLOBAL bit32 tdsaDiscoverySendIDDev( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext + ); + +void tdsaDiscoveryStartIDDevCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); + + +/* + utility functions + */ + +bit32 satComputeCDB10LBA(satIOContext_t *satIOContext); +bit32 satComputeCDB10TL(satIOContext_t *satIOContext); +bit32 satComputeCDB12LBA(satIOContext_t *satIOContext); +bit32 satComputeCDB12TL(satIOContext_t *satIOContext); +bit32 satComputeCDB16LBA(satIOContext_t *satIOContext); +bit32 satComputeCDB16TL(satIOContext_t *satIOContext); +bit32 satComputeLoopNum(bit32 a, + bit32 b); +bit32 satAddNComparebit64(bit8 *a, bit8 *b); +bit32 satAddNComparebit32(bit8 *a, bit8 *b); +bit32 satCompareLBALimitbit(bit8 *lba); + +/***************************************************************************** +*! \brief +* Purpose: bitwise set +* +* Parameters: +* data - input output buffer +* index - bit to set +* +* Return: +* none +* +*****************************************************************************/ +GLOBAL void +satBitSet(bit8 *data, bit32 index); + +/***************************************************************************** +*! \brief +* Purpose: bitwise clear +* +* Parameters: +* data - input output buffer +* index - bit to clear +* +* Return: +* none +* +*****************************************************************************/ +GLOBAL void +satBitClear(bit8 *data, bit32 index); + +/***************************************************************************** +*! \brief +* Purpose: bitwise test +* +* Parameters: +* data - input output buffer +* index - bit to test +* +* Return: +* 0 - not set +* 1 - set +* +*****************************************************************************/ +GLOBAL agBOOLEAN +satBitTest(bit8 *data, bit32 index); + +/******************************************************************************/ +/*! \brief allocate an available SATA tag + * + * allocate an available SATA tag + * + * \param pSatDevData + * \param pTag + * + * \return -Success or fail- + */ +/*******************************************************************************/ +GLOBAL bit32 satTagAlloc( + tiRoot_t *tiRoot, + satDeviceData_t *pSatDevData, + bit8 *pTag + ); + +/******************************************************************************/ +/*! \brief release an SATA tag + * + * release an available SATA tag + * + * \param pSatDevData + * + * \return -the tag- + */ +/*******************************************************************************/ +GLOBAL bit32 satTagRelease( + tiRoot_t *tiRoot, + satDeviceData_t *pSatDevData, + bit8 tag + ); + +GLOBAL void +satDecrementPendingIO( + tiRoot_t *tiRoot, + tdsaContext_t *tdsaAllShared, + satIOContext_t *satIOContext + ); + +GLOBAL bit32 satStartResetDevice( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext + ); + +GLOBAL bit32 satResetDevice( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext + ); + +GLOBAL void satResetDeviceCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); + +osGLOBAL bit32 satSubTM( + tiRoot_t *tiRoot, + tiDeviceHandle_t *tiDeviceHandle, + bit32 task, + tiLUN_t *lun, + tiIORequest_t *taskTag, + tiIORequest_t *currentTaskTag, + bit32 NotifyOS + ); + +GLOBAL bit32 satStartDeResetDevice( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext + ); + +GLOBAL bit32 satDeResetDevice( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext + ); + + +GLOBAL void satDeResetDeviceCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); + + +GLOBAL bit32 satStartCheckPowerMode( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext + ); + +GLOBAL bit32 satCheckPowerMode( + tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + tiDeviceHandle_t *tiDeviceHandle, + tiScsiInitiatorRequest_t *tiScsiRequest, + satIOContext_t *satIOContext + ); + +GLOBAL void satCheckPowerModeCB( + agsaRoot_t *agRoot, + agsaIORequest_t *agIORequest, + bit32 agIOStatus, + agsaFisHeader_t *agFirstDword, + bit32 agIOInfoLen, + agsaFrameHandle_t agFrameHandle, + void *ioContext + ); + +GLOBAL void satAbort(agsaRoot_t *agRoot, + satIOContext_t *satIOContext + ); + +GLOBAL void satTranslateATAPIErrorsToSCSIErrors( + bit8 bCommand, + bit8 bATAStatus, + bit8 bATAError, + bit8 *pSenseKey, + bit16 *pSenseCodeInfo + ); + +osGLOBAL void +satSATADeviceReset(tiRoot_t *tiRoot, + tdsaDeviceData_t *oneDeviceData, + bit32 flag); + +#ifdef REMOVED +osGLOBAL void +satSATADeviceReset( tiRoot_t *tiRoot, + tdsaDeviceData_t *oneDeviceData, + bit32 flag + ); +#endif +#endif /*__SATPROTO_H__ */ diff --git a/sys/dev/pms/config.h b/sys/dev/pms/config.h new file mode 100644 index 000000000000..81250882b3bb --- /dev/null +++ b/sys/dev/pms/config.h @@ -0,0 +1,63 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +********************************************************************************/ + +#ifndef CONFIG_H +#define CONFIG_H + +#define LINUX_PERBI_SUPPORT +#define HIALEAH_ENCRYPTION +#define HOTPLUG_SUPPORT +#define AG_CPU_LITTLE_ENDIAN +#define INITIATOR_DRIVER +#define AGTIAPI_SA +#define AGTIAPI_EVENT_LOG +// #define AGTIAPI_DPC +#define AGTIAPI_SA +#define PMC_SPC +#define SPC_MSIX_INTR +#define SPC_INT_ENABLE +#define AGTIAPI_LOCAL_LOCK +#define AGTIAPI_LOCAL_RESET +#define MU_I2O_DISABLE +#define HOST_SAST_ENABLE +#define HOST_PM2_ENABLE +#define TD_DISCOVER +#define SA_ENABLE_HDA_FUNCTIONS +// #define SA_FW_TEST_INTERRUPT_REASSERT +// #define SALLSDK_DEBUG +// #define AGTIAPI_DEBUG +// #define TD_DEBUG_ENABLE +// #define AGTIAPI_IO_DEBUG +// #define AGTIAPI_FLOW_DEBUG +// #define AGTIAPI_INIT_DEBUG +#define PMC_PM8001_BAR64KB +// #define DM_DEBUG +#define FDS_DM +// #define SM_DEBUG +#define FDS_SM +#define SATA_ENABLE +#define CHAR_DEVICE +#define TD_4GB_WORKAROUND + +#endif /* CONFIG_H */ diff --git a/sys/dev/pms/freebsd/driver/common/encrypt_ioctl.h b/sys/dev/pms/freebsd/driver/common/encrypt_ioctl.h new file mode 100644 index 000000000000..2fc03530d0b1 --- /dev/null +++ b/sys/dev/pms/freebsd/driver/common/encrypt_ioctl.h @@ -0,0 +1,175 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +*******************************************************************************/ +/******************************************************************************* +** +** Version Control Information: +** +** $Revision: 114125 $ +** $Author: lindfors $ +** $Date: 2012-01-06 17:12:27 -0800 (Fri, 06 Jan 2012) $ +** $Id: encrypt_ioctl.h 112360 2012-01-07 01:12:27Z mcleanda $ +** +*******************************************************************************/ +#include + +#ifndef __ENCRYPT_IOCTL_H__ +#define __ENCRYPT_IOCTL_H__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +typedef struct IoctlEncryptGetInfo_s { + tiEncryptInfo_t tisaEncryptInfo; +} __attribute__ ((packed)) IoctlEncryptGetInfo_t; + +typedef struct IoctlEncryptSetMode_s { + bit32 securityCipherMode; +} __attribute__ ((packed)) IoctlEncryptSetMode_t; + +typedef struct IoctlEncryptKekAdd_s { + bit32 kekIndex; + bit32 wrapperKekIndex; + bit32 blobFormat; + tiEncryptKekBlob_t *EncryptKekBlob; +} __attribute__ ((packed)) IoctlEncryptKekAdd_t; + +typedef struct IoctlEncryptDekAdd_s { + bit32 kekIndex; + bit32 dekTable; + bit32 dekIndex; + bit32 dekBlobFormat; + bit32 dekTableKeyEntrySize; + tiEncryptDekBlob_t *dekBlob; +} __attribute__ ((packed)) IoctlEncryptDekAdd_t; + +typedef struct IoctlEncryptDekInvalidate_s { + tiEncryptDek_t dek; +} __attribute__ ((packed)) IoctlEncryptDekInvalidate_t; + +typedef struct IoctlEncryptKekNVRAM_s { + bit32 index; +} __attribute__ ((packed)) IoctlEncryptKekNVRAM_t; + +typedef struct IoctlEncryptDekTable_s { + tiMem_t DekTable1Addr; + tiMem_t DekTable2Addr; +} __attribute__ ((packed)) IoctlEncryptDekTable_t; + +typedef struct EncryptDekMapEntry_s { +#define ENCRYPT_DEK_MAP_ENTRY_CLEAR 0x00000001UL +#define ENCRYPT_DEK_MAP_ENTRY_VALID 0x80000000UL + bit32 flags; + unsigned long long startLBA; + unsigned long long endLBA; + tiEncryptDek_t dek; +} __attribute__ ((packed)) EncryptDekMapEntry_t; + +typedef struct EncryptDeviceDekMap_s { + bit32 host; + bit32 channel; + bit32 device; + bit32 lun; + bit32 keytag_check; + bit32 keytag[2]; + EncryptDekMapEntry_t dekMapEntry[1]; +} __attribute__ ((packed)) EncryptDeviceDekMap_t; + +typedef struct IoctlEncryptDekMapTable_s { + EncryptDeviceDekMap_t dekMap[1]; +} __attribute__ ((packed)) IoctlEncryptDekMapTable_t; + +typedef struct IoctlEncryptIOError_s { + bit64 error_id; + bit64 timestamp; + bit32 error_type; + bit32 host; + bit32 channel; + bit32 device; + bit32 lun; + bit32 scsi_cmd; + bit32 dek_index; + bit32 dek_table; + bit32 kek_index; + bit32 encrypt_mode; + bit32 keytag_check; + bit32 keytag[2]; +} __attribute__ ((packed)) IoctlEncryptIOError_t; + +typedef struct __attribute__ ((packed)) IoctlEncryptErrorQuery_s { +#define ERROR_QUERY_FLAG_BLOCK 1 + bit32 query_flag; + bit32 valid_mask; + IoctlEncryptIOError_t error[32]; +} __attribute__ ((packed)) IoctlEncryptErrorQuery_t; + +typedef union IoctlEncryptOp_u { + IoctlEncryptGetInfo_t encryptGetInfo; + IoctlEncryptSetMode_t encryptSetMode; + IoctlEncryptKekAdd_t encryptKekAdd; + IoctlEncryptDekAdd_t encryptDekAdd; + IoctlEncryptDekInvalidate_t encryptDekInvalidate; + IoctlEncryptKekNVRAM_t encryptKekNVRAM; + IoctlEncryptDekMapTable_t encryptDekMap; + IoctlEncryptErrorQuery_t encryptErrorQuery; +} __attribute__ ((packed)) IoctlEncryptOp_t; + +typedef struct tiIOCTLPayloadHeader_s { + bit32 Signature; + bit16 MajorFunction; + bit16 MinorFunction; + bit16 Length; + bit16 Status; +} __attribute__ ((packed)) tiIOCTLPayloadHeader_t; + +typedef struct IoctlTISAEncrypt_s { +#define encryptGetInfo 0x00000001 +#define encryptSetMode 0x00000002 +#define encryptKekAdd 0x00000003 +#define encryptDekAdd 0x00000004 +#define encryptDekInvalidate 0x00000005 +#define encryptKekStore 0x00000006 +#define encryptKekLoad 0x00000007 +#define encryptGetDekTable 0x00000008 +#define encryptSetDekMap 0x00000009 +#define encryptDekDump 0x0000000a +#define encryptErrorQuery 0x0000000c + bit32 encryptFunction; + bit32 status; + bit32 subEvent; + IoctlEncryptOp_t request; +} __attribute__ ((packed)) IoctlTISAEncrypt_t; + +typedef struct IOCTLEncrypt_s { + tiIOCTLPayloadHeader_t hdr; + IoctlTISAEncrypt_t body; +} __attribute__ ((packed)) IoctlEncrypt_t; + +#endif diff --git a/sys/dev/pms/freebsd/driver/common/lxcommon.h b/sys/dev/pms/freebsd/driver/common/lxcommon.h new file mode 100644 index 000000000000..0df2702ec4ec --- /dev/null +++ b/sys/dev/pms/freebsd/driver/common/lxcommon.h @@ -0,0 +1,886 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +*******************************************************************************/ +/****************************************************************************** + +Module Name: + lxcommon.h +Abstract: + TISA Initiator/target driver module constant define header file +Environment: + Kernel or loadable module + +******************************************************************************/ + + +#include + + +#define LINUX_DMA_MEM_MAX 0x1ffe0 /* 128k - 32, real 128k - 24 */ +#define DEK_MAX_TABLE_ITEMS DEK_MAX_TABLE_ENTRIES // from tisa/api/titypes.h + +/* +** IP address length based on character. +*/ +#ifdef AGTIAPI_IP6_SUPPORT +# define IP_ADDR_CHAR_LEN 64 +#else +# define IP_ADDR_CHAR_LEN 16 +#endif + +#define MSEC_PER_TICK (1000/hz) /* milisecond per tick */ +#define USEC_PER_TICK (1000000/hz) /* microsecond per tick */ +#define AGTIAPI_64BIT_ALIGN 8 /* 64 bit environment alignment */ + +/* +** Max device supported +*/ +#define AGTIAPI_MAX_CARDS 4 /* card supported up to system limit */ +#define AGTIAPI_TOO_MANY_CARDS -1 /* beyond defined max support */ +#define AGTIAPI_MAX_PORTALS 16 /* max portal per card */ +/* max device per portal */ + +/* +** Adjustable Parameter Options +*/ +#define AGTIAPI_OPTION_ON 1 /* adjustable parameter available */ +#define AGTIAPI_KEY_MAX 64 /* max number of keys */ +#define AGTIAPI_STRING_MAX 512 /* max length for string */ +#define AGTIAPI_PARAM_MAX 256 /* max number of parameters */ +#ifdef TARGET_DRIVER +#define AGTIAPI_DMA_MEM_LIST_MAX 4096 /* max number of DMA memory list */ +#define AGTIAPI_CACHE_MEM_LIST_MAX 24 /* max number of CACHE memory list */ +#else /* INITIATOR_DRIVER */ +#define AGTIAPI_DMA_MEM_LIST_MAX 1024 /* max number of DMA memory list */ +#define AGTIAPI_CACHE_MEM_LIST_MAX 1024 /* max number of CACHE memory list */ +#endif +#ifndef AGTIAPI_DYNAMIC_MAX +#define AGTIAPI_DYNAMIC_MAX 4096 /* max unreleased dynamic memory */ +#endif +#define AGTIAPI_LOOP_MAX 4 /* max loop for init process */ + +#define AGTIAPI_MAX_NAME 70 // Max string name length +#define AGTIAPI_MIN_NAME 10 // minimum space for SAS name string +#define AGTIAPI_MAX_ID 8 // Max string id length + +/* +** Card-port status definitions +*/ +#define AGTIAPI_INIT_TIME 0x00000001 +#define AGTIAPI_SOFT_RESET 0x00000002 +#define AGTIAPI_HAD_RESET 0x00000004 // ### +#define AGTIAPI_DISC_DONE 0x00000008 +#define AGTIAPI_INSTALLED 0x00000010 +#define AGTIAPI_RESET 0x00000020 +#define AGTIAPI_FLAG_UP 0x00000040 +#define AGTIAPI_CB_DONE 0x00000080 +#define AGTIAPI_DISC_COMPLETE 0x00000100 +#define AGTIAPI_IOREGION_REQUESTED 0x00000200 +#define AGTIAPI_IRQ_REQUESTED 0x00000400 +#define AGTIAPI_SCSI_REGISTERED 0x00000800 +#define AGTIAPI_NAME_SERVER_UP 0x00001000 +#define AGTIAPI_PORT_INITIALIZED 0x00002000 +#define AGTIAPI_PORT_LINK_UP 0x00004000 +#define AGTIAPI_LGN_LINK_UP 0x00008000 +#define AGTIAPI_PORT_PANIC 0x00010000 +#define AGTIAPI_RESET_SUCCESS 0x00020000 +#define AGTIAPI_PORT_START 0x00040000 +#define AGTIAPI_PORT_STOPPED 0x00080000 +#define AGTIAPI_PORT_SHUTDOWN 0x00100000 +#define AGTIAPI_IN_USE 0x00200000 +#define AGTIAPI_SYS_INTR_ON 0x00400000 +#define AGTIAPI_PORT_DISC_READY 0x00800000 +#define AGTIAPI_SIG_DOWN 0x01000000 +#define AGTIAPI_SIG_UP 0x02000000 +#define AGTIAPI_TASK 0x04000000 +#define AGTIAPI_INITIATOR 0x08000000 +#define AGTIAPI_TARGET 0x10000000 +#define AGTIAPI_TIMER_ON 0x20000000 +#define AGTIAPI_SHUT_DOWN 0x40000000 +/* reserved for ccb flag TASK_MANAGEMENT +#define AGTIAPI_RESERVED 0x80000000 +*/ +#define AGTIAPI_RESET_ALL 0xFFFFFFFF + +/* +** PCI defines +*/ +#ifndef PCI_VENDOR_ID_HP +#define PCI_VENDOR_ID_HP 0x103c +#endif + +#ifndef PCI_VENDOR_ID_PMC_SIERRA +#define PCI_VENDOR_ID_PMC_SIERRA 0x11F8 +#endif + +#ifndef PCI_VENDOR_ID_AGILENT +#define PCI_VENDOR_ID_AGILENT 0x15bc +#endif + +#ifndef PCI_VENDOR_ID_CYCLONE +#define PCI_VENDOR_ID_CYCLONE 0x113C +#endif + +#ifndef PCI_VENDOR_ID_SPCV_FPGA +#define PCI_VENDOR_ID_SPCV_FPGA 0x1855 +#endif + +#ifndef PCI_VENDOR_ID_HIALEAH +#define PCI_VENDOR_ID_HIALEAH 0x9005 +#endif + +#define PCI_DEVICE_ID_HP_TS 0x102a +#define PCI_DEVICE_ID_HP_TL 0x1028 +#define PCI_DEVICE_ID_HP_XL2 0x1029 +#define PCI_DEVICE_ID_AG_DX2 0x0100 +#define PCI_DEVICE_ID_AG_DX2PLUS 0x0101 +#define PCI_DEVICE_ID_AG_QX2 0x0102 +#define PCI_DEVICE_ID_AG_QX4 0x0103 +#define PCI_DEVICE_ID_AG_QE4 0x1200 +#define PCI_DEVICE_ID_AG_DE4 0x1203 +#define PCI_DEVICE_ID_AG_XL10 0x0104 +#define PCI_DEVICE_ID_AG_DX4PLUS 0x0105 +#define PCI_DEVICE_ID_AG_DIXL 0x0110 +#define PCI_DEVICE_ID_AG_IDX1 0x050A +#define PCI_DEVICE_ID_PMC_SIERRA_SPC 0x8001 +#define PCI_DEVICE_ID_PMC_SIERRA_SPCV 0x8008 +#define PCI_DEVICE_ID_PMC_SIERRA_SPCVE 0x8009 +#define PCI_DEVICE_ID_PMC_SIERRA_SPCVPLUS 0x8018 +#define PCI_DEVICE_ID_PMC_SIERRA_SPCVE_16 0x8019 +#define PCI_DEVICE_ID_SPCV_FPGA 0xabcd +#define PCI_DEVICE_ID_PMC_SIERRA_SPCV12G 0x8070 +#define PCI_DEVICE_ID_PMC_SIERRA_SPCVE12G 0x8071 +#define PCI_DEVICE_ID_PMC_SIERRA_SPCV12G_16 0x8072 +#define PCI_DEVICE_ID_PMC_SIERRA_SPCVE12G_16 0x8073 +#define PCI_DEVICE_ID_HIALEAH_HBA_SPC 0x8081 +#define PCI_DEVICE_ID_HIALEAH_RAID_SPC 0x8091 +#define PCI_DEVICE_ID_HIALEAH_HBA_SPCV 0x8088 +#define PCI_DEVICE_ID_HIALEAH_RAID_SPCV 0x8098 +#define PCI_DEVICE_ID_HIALEAH_HBA_SPCVE 0x8089 +#define PCI_DEVICE_ID_HIALEAH_RAID_SPCVE 0x8099 +#define PCI_DEVICE_ID_DELRAY_HBA_8PORTS_SPCV 0x8074 +#define PCI_DEVICE_ID_DELRAY_HBA_8PORTS_SPCVE 0x8075 +#define PCI_DEVICE_ID_DELRAY_HBA_16PORTS_SPCV 0x8076 +#define PCI_DEVICE_ID_DELRAY_HBA_16PORTS_SPCVE 0x8077 +#define PCI_DEVICE_ID_DELRAY_HBA_16PORTS_SPCV_SATA 0x8006 + + +#define PCI_SUB_VENDOR_ID_HP PCI_VENDOR_ID_HP +#define PCI_SUB_VENDOR_ID_AG PCI_VENDOR_ID_AGILENT +#define PCI_SUB_VENDOR_ID_MASK 0xFFFF +#define PCI_SUB_SYSTEM_ID_AG 0x0001 +#define PCI_BASE_MEM_MASK (~0x0F) + +#define PCI_DEVICE_ID_CYCLONE 0xB555 +#define PCI_ENABLE_VALUE 0x0157 +#ifdef PMC_SPC +#define PCI_NUMBER_BARS 6 +#endif +#define IOCTL_MN_GET_CARD_INFO 0x11 +/* +** Constant defines +*/ +#define _08B 8 +#define _16B 16 +#define _24B 24 +#define _32B 32 +#define _64B 64 +#define _128B 128 +#define _256B 256 +#define _512B 512 + +#define _1K 1024 +#define _2K 2048 +#define _4K 4096 +#define _128K (128*(_1K)) + +// Card property related info. +typedef struct _ag_card_id { + U16 vendorId; /* pci vendor id */ + U16 deviceId; /* pci device id */ + S32 cardNameIndex; /* structure index */ + U16 membar; /* pci memory bar offset */ + U16 iobar1; /* pci io bar 1 offset */ + U16 iobar2; /* pci io bar 2 offest */ + U16 reg; /* pci memory bar number */ +} ag_card_id_t; + + +#define PCI_BASE_ADDRESS_0 PCIR_BAR(0) +#define PCI_BASE_ADDRESS_1 PCIR_BAR(1) +#define PCI_BASE_ADDRESS_2 PCIR_BAR(2) +#define PCI_BASE_ADDRESS_3 PCIR_BAR(3) +#define PCI_BASE_ADDRESS_4 PCIR_BAR(4) + + +ag_card_id_t ag_card_type[] = { +#ifdef AGTIAPI_ISCSI + {PCI_VENDOR_ID_AGILENTj, PCI_DEVICE_ID_AG_DIXL, 1, + PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_0, 0}, + {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_IDX1, 2, + PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_0, 0}, +#endif +#ifdef AGTIAPI_FC + {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_TS, 3, + PCI_BASE_ADDRESS_3, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_2, 3}, + {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_TL, 4, + PCI_BASE_ADDRESS_3, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_2, 3}, + {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_XL2, 5, + PCI_BASE_ADDRESS_3, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_2, 3}, + {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_DX2, 6, + PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4}, + {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_DX2PLUS, 7, + PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4}, + {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_DX4PLUS, 8, + PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4}, + {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_QX2, 9, + PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4}, + {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_QX4, 10, + PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4}, + {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_DE4, 11, + PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4}, + {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_QE4, 12, + PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4}, + {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_XL10, 13, + PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4}, +#endif +#ifdef AGTIAPI_SA +#ifdef PMC_SPC + {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPC, 14, + PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, + {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCV, 15, + PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, + {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCVE, 16, + PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, + {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCVPLUS, 17, + PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, + {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCVE_16, 18, + PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, + {PCI_VENDOR_ID_SPCV_FPGA, PCI_DEVICE_ID_SPCV_FPGA, 19, + PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, + {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCV12G, 20, + PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, + {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCVE12G, 21, + PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, + {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCV12G_16, 22, + PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, + {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCVE12G_16, 23, + PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, + {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_HIALEAH_HBA_SPC, 24, + PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, + {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_HIALEAH_RAID_SPC, 25, + PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, + {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_HIALEAH_HBA_SPCV, 26, + PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, + {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_HIALEAH_RAID_SPCV, 27, + PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, + {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_HIALEAH_HBA_SPCVE, 28, + PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, + {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_HIALEAH_RAID_SPCVE, 29, + PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, + {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_DELRAY_HBA_8PORTS_SPCV, 30, + PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, + {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_DELRAY_HBA_8PORTS_SPCVE, 31, + PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, + {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_DELRAY_HBA_16PORTS_SPCV, 32, + PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, + {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_DELRAY_HBA_16PORTS_SPCVE, 33, + PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, + {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_DELRAY_HBA_16PORTS_SPCV_SATA, 34, + PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, + +#endif +#endif //AGTIAPI_SA +}; + +static const char *ag_card_names[] = { + "Unknown", + "iSCSI DiXL Card", + "iSCSI iDX1 Card", + "Tachyon TS Fibre Channel Card", + "Tachyon TL Fibre Channel Card", + "Tachyon XL2 Fibre Channel Card", + "Tachyon DX2 Fibre Channel Card", + "Tachyon DX2+ Fibre Channel Card", + "Tachyon DX4+ Fibre Channel Card", + "Tachyon QX2 Fibre Channel Card", + "Tachyon QX4 Fibre Channel Card", + "Tachyon DE4 Fibre Channel Card", + "Tachyon QE4 Fibre Channel Card", + "Tachyon XL10 Fibre Channel Card", +#ifdef AGTIAPI_SA +#ifdef PMC_SPC + "PMC Sierra SPC SAS-SATA Card", + "PMC Sierra SPC-V SAS-SATA Card", + "PMC Sierra SPC-VE SAS-SATA Card", + "PMC Sierra SPC-V 16 Port SAS-SATA Card", + "PMC Sierra SPC-VE 16 Port SAS-SATA Card", + "PMC Sierra FPGA", + "PMC Sierra SPC-V SAS-SATA Card 12Gig", + "PMC Sierra SPC-VE SAS-SATA Card 12Gig", + "PMC Sierra SPC-V 16 Port SAS-SATA Card 12Gig", + "PMC Sierra SPC-VE 16 Port SAS-SATA Card 12Gig", + "Adaptec Hialeah 4/8 Port SAS-SATA HBA Card 6Gig", + "Adaptec Hialeah 4/8 Port SAS-SATA RAID Card 6Gig", + "Adaptec Hialeah 8/16 Port SAS-SATA HBA Card 6Gig", + "Adaptec Hialeah 8/16 Port SAS-SATA RAID Card 6Gig", + "Adaptec Hialeah 8/16 Port SAS-SATA HBA Encryption Card 6Gig", + "Adaptec Hialeah 8/16 Port SAS-SATA RAID Encryption Card 6Gig", + "Adaptec Delray 8 Port SAS-SATA HBA Card 12Gig", + "Adaptec Delray 8 Port SAS-SATA HBA Encryption Card 12Gig", + "Adaptec Delray 16 Port SAS-SATA HBA Card 12Gig", + "Adaptec Delray 16 Port SAS-SATA HBA Encryption Card 12Gig", + "Adaptec SATA Adapter", + +#endif +#endif +}; + + + +/* +** Resource Info Structure +*/ +typedef struct _ag_resource_info { + tiLoLevelResource_t tiLoLevelResource; // Low level resource required + tiInitiatorResource_t tiInitiatorResource; // Initiator resource required + tiTargetResource_t tiTargetResource; // Target resource required + tiTdSharedMem_t tiSharedMem; // Shared memory by ti and td +} ag_resource_info_t; + + +// DMA memory address pair +typedef struct _ag_dma_addr { + void *dmaVirtAddr; + vm_paddr_t dmaPhysAddr; + U32 memSize; + bit32 type; + bus_addr_t nocache_busaddr; + void *nocache_mem; +} ag_dma_addr_t; + + +typedef struct _CardInfo +{ + U32 pciIOAddrLow; /* PCI IOBASE lower */ + U32 pciIOAddrUp; /* PCI IOBASE Upper */ + U32_64 pciMemBase; /* PCI MEMBASE, physical */ + U32_64 pciMemBaseSpc[PCI_NUMBER_BARS]; // PCI MEMBASE, physical + U16 deviceId; // PCI device id + U16 vendorId; // PCI Vendor id + U32 busNum; + U32 deviceNum; +}CardInfo_t; + +// Card info. for all cards and drivers +typedef struct _ag_card_info { + struct mtx pmIOLock; + device_t pPCIDev; // PCI device pointer + void *pCard; // pointer to per card data structure + S32 cardNameIndex; + U32 cardID; // card system ID + U32 cardIdIndex; + U32 pciIOAddrLow; // PCI IOBASE lower + U32 pciIOAddrUp; // PCI IOBASE Upper + U32_64 pciMemBase; // PCI MEMBASE, physical + caddr_t pciMemVirtAddr; // PCI MEMBASE, virtual ptr + U32 pciMemSize; // PCI MEMBASE memory size +#ifdef AGTIAPI_SA +#ifdef FPGA_CARD + U32_64 pciMemBase0; // PCI MEMBASE, physical + caddr_t pciMemVirtAddr0; // PCI MEMBASE, virtual ptr + U32 pciMemSize0; // PCI MEMBASE memory size +#endif +#ifdef PMC_SPC + struct resource *pciMemBaseRscSpc[PCI_NUMBER_BARS]; + int pciMemBaseRIDSpc[PCI_NUMBER_BARS]; + U32_64 pciMemBaseSpc[PCI_NUMBER_BARS]; // PCI MEMBASE, physical + caddr_t pciMemVirtAddrSpc[PCI_NUMBER_BARS];//PCI MEMBASE, virt ptr + U32 pciMemSizeSpc[PCI_NUMBER_BARS]; // PCI MEMBASE memory size +#endif +#endif + U16 memBar; + U16 memReg; + U32 cacheIndex; + U32 dmaIndex; + ag_dma_addr_t tiDmaMem[AGTIAPI_DMA_MEM_LIST_MAX]; // dma addr list + + // all (free and allocated) mem slots + ag_dma_addr_t dynamicMem[AGTIAPI_DYNAMIC_MAX]; + + // ptr to free mem slots + ag_dma_addr_t *freeDynamicMem[AGTIAPI_DYNAMIC_MAX]; + + U16 topOfFreeDynamicMem; // idx to the first free slot ptr + + void *tiCachedMem[AGTIAPI_CACHE_MEM_LIST_MAX];// cached mem list + ag_resource_info_t tiRscInfo; /* low level resource requirement */ + U08 WWN[AGTIAPI_MAX_NAME]; /* WWN for this card */ + U08 WWNLen; + +// #define MAX_MSIX_NUM_VECTOR 64 ## +#define MAX_MSIX_NUM_VECTOR 16 // 1 then 16 just for testing; +#define MAX_MSIX_NUM_DPC 64 // 16 +#define MAX_MSIX_NUM_ISR 64 // 16 +#ifdef SPC_MSIX_INTR + + // ## use as a map instead of presirq + struct resource *msix_entries[MAX_MSIX_NUM_VECTOR]; +#endif + U32 maxInterruptVectors; +} ag_card_info_t; + +/* +** Optional Adjustable Parameters Structures. +** Not using pointer stucture for easy read and access tree structure. +** In the future if more layer of key tree involved, it might be a good +** idea to change the structure and program. +*/ +typedef struct _ag_param_value{ + char valueName[AGTIAPI_MAX_NAME]; + char valueString[AGTIAPI_STRING_MAX]; + struct _ag_param_value *next; +} ag_value_t; + +typedef struct _ag_param_key{ + char keyName[AGTIAPI_MAX_NAME]; + ag_value_t *pValueHead; + ag_value_t *pValueTail; + struct _ag_param_key *pSubkeyHead; + struct _ag_param_key *pSubkeyTail; + struct _ag_param_key *next; +} ag_key_t; + +/* +** Portal info data structure +*/ +typedef struct _ag_portal_info { + U32 portID; + U32 portStatus; + U32 devTotal; + U32 devPrev; + tiPortInfo_t tiPortInfo; + tiPortalContext_t tiPortalContext; +#ifdef INITIATOR_DRIVER + void *pDevList[AGTIAPI_HW_LIMIT_DEVICE]; +#endif +} ag_portal_info_t; + +#define MAP_TABLE_ENTRY(pC, c, d, l) (pC->encrypt_map + \ + (c * pC->devDiscover * AGTIAPI_MAX_LUN) + \ + (d * AGTIAPI_MAX_LUN) + \ + (l)) + +#ifdef CHAR_DEVICE +/************************************************************************* +Purpose: Payload Wraper for ioctl commands +***********************************************************************/ +typedef struct datatosendt{ +bit32 datasize; //buffer size +bit8 *data; //buffer +}datatosend; +/***********************************************************************/ +#define AGTIAPI_IOCTL_BASE 'x' +#define AGTIAPI_IOCTL _IOWR(AGTIAPI_IOCTL_BASE, 0,datatosend ) //receiving payload here// +#define AGTIAPI_IOCTL_MAX 1 +#endif + +#ifdef AGTIAPI_FLOW_DEBUG +#define AGTIAPI_FLOW(format, a...) printf(format, ## a) +#else +#define AGTIAPI_FLOW(format, a...) +#endif + +#ifdef AGTIAPI_DEBUG +#define AGTIAPI_PRINTK(format, a...) printf(format, ## a) +#else +#define AGTIAPI_PRINTK(format, a...) +#endif + +#ifdef AGTIAPI_INIT_DEBUG +#define AGTIAPI_INIT(format, a...) printf(format, ## a) +/* to avoid losing the logs */ +#define AGTIAPI_INIT_MDELAY(dly) mdelay(dly) +#else +#define AGTIAPI_INIT(format, a...) +#define AGTIAPI_INIT_MDELAY(dly) +#endif + +#ifdef AGTIAPI_INIT2_DEBUG +#define AGTIAPI_INIT2(format, a...) printf(format, ## a) +#else +#define AGTIAPI_INIT2(format, a...) +#endif + +#ifdef AGTIAPI_INIT_MEM_DEBUG +#define AGTIAPI_INITMEM(format, a...) printf(format, ## a) +#else +#define AGTIAPI_INITMEM(format, a...) +#endif + +#ifdef AGTIAPI_IO_DEBUG +#define AGTIAPI_IO(format, a...) printf(format, ## a) +#else +#define AGTIAPI_IO(format, a...) +#endif + +#ifdef AGTIAPI_LOAD_DELAY +#define AGTIAPI_INIT_DELAY(delay_time) \ + { \ + agtiapi_DelayMSec(delay_time); \ + } +#else +#define AGTIAPI_INIT_DELAY(delay_time) +#endif + +/* + * AGTIAPI_KDB() will be used to drop into kernel debugger + * from driver code if kdb is involved. + */ +#ifdef AGTIAPI_KDB_ENABLE +#define AGTIAPI_KDB() KDB_ENTER() +#else +#define AGTIAPI_KDB() +#endif + +#if (BITS_PER_LONG == 64) +//#if 1 +#define LOW_32_BITS(addr) (U32)(addr & 0xffffffff) +#define HIGH_32_BITS(addr) (U32)((addr >> 32) & 0xffffffff) +#else +#define LOW_32_BITS(addr) (U32)addr +#define HIGH_32_BITS(addr) 0 +#endif + +#define AG_SWAP16(data) (((data<<8) & 0xFF00) | (data>>8)) +#define AG_SWAP24(data) (((data<<16) & 0xFF0000) | \ + ((data>>16) & 0xFF) | (data & 0xFF00)) +#define AG_SWAP32(data) ((data<<24) | ((data<<8) & 0xFF0000) | \ + ((data>>8) & 0xFF00) | (data>>24)) + +#define AG_PCI_DEV_INFO(pdev) ( \ + AGTIAPI_PRINTK("vendor id 0x%x device id 0x%x, slot %d, function %d\n", \ + pdev->vendor, pdev->device, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)) \ + ) + +#define COUNT(arr) (sizeof(arr) / sizeof(arr[0])) + +#define PORTAL_CONTEXT_TO_PORTALDATA(pPortalContext) \ + ((ag_portal_data_t *)(((tiPortalContext_t *)pPortalContext)->osData)) +#define PORTAL_STATUS(pPortalData) (pPortalData->portalInfo.portStatus) + +#if (defined(DEFINE_OSTI_PORT_EVENT_IN_IBE)) || \ + (defined(DEFINE_OSTI_PORT_EVENT_IN_TFE)) +#define TIROOT_TO_CARD(ptiRoot) \ + ((ag_card_t *)(((appRoot_t *)(ptiRoot->osData))->oscData)) +#define TIROOT_TO_CARDINFO(ptiRoot) (TIROOT_TO_CARD(ptiRoot)->pCardInfo) +#define TIROOT_TO_PCIDEV(ptiRoot) (TIROOT_TO_CARDINFO(ptiRoot)->pPCIDev) +#else + +#define TIROOT_TO_CARD(ptiRoot) ((struct agtiapi_softc *)(ptiRoot->osData)) +#define TIROOT_TO_CARDINFO(ptiRoot) (TIROOT_TO_CARD(ptiRoot)->pCardInfo) +#define TIROOT_TO_PCIDEV(ptiRoot) (TIROOT_TO_CARD(ptiRoot)->my_dev) + +#endif + + +#define Is_ADP7H(pmsc) ((0x90058088 == (pmsc->VidDid))?1:\ + (0x90058089 == (pmsc->VidDid))?1:0) +#define Is_ADP8H(pmsc) ((0x90058074 == (pmsc->VidDid))?1:\ + (0x90058076 == (pmsc->VidDid))?1:0) + + +#define __cacheline_aligned __attribute__((__aligned__(CACHE_LINE_SIZE))) + +/* +** link data, need to be included at the start (offset 0) +** of any strutures that are to be stored in the link list +*/ +typedef struct _LINK_NODE +{ + struct _LINK_NODE *pNext; + struct _LINK_NODE *pPrev; + + /* + ** for assertion purpose only + */ + struct _LINK_NODE * pHead; // track the link list the link is a member of + void * pad; + +} LINK_NODE, * PLINK_NODE __cacheline_aligned; + + +/* +** link list basic pointers +*/ +typedef struct _LINK_LIST +{ + PLINK_NODE pHead; + bit32 Count; + LINK_NODE Head __cacheline_aligned; // allways one link to speed up insert&rm +} LINK_LIST, * PLINK_LIST __cacheline_aligned; + + +/******************************************************************** +** MACROS +********************************************************************/ +/******************************************************************************* +** +** MODULE NAME: comListInitialize +** +** PURPOSE: Initialize a link list. +** +** PARAMETERS: PLINK_LIST OUT - Link list definition. +** +** SIDE EFFECTS & CAVEATS: +** +** ALGORITHM: +** +*******************************************************************************/ +#define comListInitialize(pList) {(pList)->pHead = &((pList)->Head); \ + (pList)->pHead->pNext = (pList)->pHead; \ + (pList)->pHead->pPrev = (pList)->pHead; \ + (pList)->Count = 0; \ + } + +/******************************************************************************* +** +** MODULE NAME: comLinkInitialize +** +** PURPOSE: Initialize a link. +** This function should be used to initialize a new link before it +** is used in the linked list. This will initialize the link so +** the assertion will work +** +** PARAMETERS: PLINK_NODE IN - Link to be initialized. +** +** SIDE EFFECTS & CAVEATS: +** +** ALGORITHM: +** +*******************************************************************************/ + +#define comLinkInitialize(pLink) { (pLink)->pHead = NULL; \ + (pLink)->pNext = NULL; \ + (pLink)->pPrev = NULL; \ + } + +/******************************************************************************* +** +** MODULE NAME: comListAdd +** +** PURPOSE: add a link at the tail of the list +** +** PARAMETERS: PLINK_LIST OUT - Link list definition. +** PLINK_NODE IN - Link to be inserted. +** +** SIDE EFFECTS & CAVEATS: +** !!! assumes that fcllistInitialize has been called on the linklist +** !!! if not, this function behavior is un-predictable +** +** ALGORITHM: +** +*******************************************************************************/ +#define comListAdd(pList, pLink) { \ + (pLink)->pNext = (pList)->pHead; \ + (pLink)->pPrev = (pList)->pHead->pPrev; \ + (pLink)->pPrev->pNext = (pLink); \ + (pList)->pHead->pPrev = (pLink); \ + (pList)->Count ++; \ + (pLink)->pHead = (pList)->pHead; \ + } + +/******************************************************************************* +** +** MODULE NAME: comListInsert +** +** PURPOSE: insert a link preceding the given one +** +** PARAMETERS: PLINK_LIST OUT - Link list definition. +** PLINK_NODE IN - Link to be inserted after. +** PLINK_NODE IN - Link to be inserted. +** +** SIDE EFFECTS & CAVEATS: +** !!! assumes that fcllistInitialize has been called on the linklist +** !!! if not, this function behavior is un-predictable +** +** ALGORITHM: +** +*******************************************************************************/ + +#define comListInsert(pList, pLink, pNew) { \ + (pNew)->pNext = (pLink); \ + (pNew)->pPrev = (pLink)->pPrev; \ + (pNew)->pPrev->pNext = (pNew); \ + (pLink)->pPrev = (pNew); \ + (pList)->Count ++; \ + (pNew)->pHead = (pList)->pHead; \ + } + +/******************************************************************************* +** +** MODULE NAME: comListRemove +** +** PURPOSE: remove the link from the list. +** +** PARAMETERS: PLINK_LIST OUT - Link list definition. +** PLINK_NODE IN - Link to delet from list +** +** SIDE EFFECTS & CAVEATS: +** !!! assumes that fcllistInitialize has been called on the linklist +** !!! if not, this function behavior is un-predictable +** +** !!! No validation is made on the list or the validity of the link +** !!! the caller must make sure that the link is in the list +** +** +** ALGORITHM: +** +*******************************************************************************/ +#define comListRemove(pList, pLink) { \ + (pLink)->pPrev->pNext = (pLink)->pNext; \ + (pLink)->pNext->pPrev = (pLink)->pPrev; \ + (pLink)->pHead = NULL; \ + (pList)->Count --; \ + } + +/******************************************************************************* +** +** MODULE NAME: comListGetHead +** +** PURPOSE: get the link following the head link. +** +** PARAMETERS: PLINK_LIST OUT - Link list definition. +** RETURNS - PLINK_NODE the link following the head +** NULL if the following link is the head +** +** SIDE EFFECTS & CAVEATS: +** !!! assumes that fcllistInitialize has been called on the linklist +** !!! if not, this function behavior is un-predictable +** +** ALGORITHM: +** +*******************************************************************************/ +#define comListGetHead(pList) comListGetNext(pList,(pList)->pHead) + +/******************************************************************************* +** +** MODULE NAME: comListGetTail +** +** PURPOSE: get the link preceding the tail link. +** +** PARAMETERS: PLINK_LIST OUT - Link list definition. +** RETURNS - PLINK_NODE the link preceding the head +** NULL if the preceding link is the head +** +** SIDE EFFECTS & CAVEATS: +** +** ALGORITHM: +** +*******************************************************************************/ +#define comListGetTail(pList) comListGetPrev((pList), (pList)->pHead) + +/******************************************************************************* +** +** MODULE NAME: comListGetCount +** +** PURPOSE: get the number of links in the list excluding head and tail. +** +** PARAMETERS: LINK_LIST OUT - Link list definition. +** +** SIDE EFFECTS & CAVEATS: +** !!! assumes that fcllistInitialize has been called on the linklist +** !!! if not, this function behavior is un-predictable +** +** ALGORITHM: +** +*******************************************************************************/ + +#define comListGetCount(pList) ((pList)->Count) + + + +/******************************************************************************* +** +** MODULE NAME: comListGetNext +** +** PURPOSE: get the next link in the list. (one toward tail) +** +** PARAMETERS: PLINK_LIST OUT - Link list definition. +** PLINK_NODE IN - Link to get next to +** +** return PLINK - points to next link +** NULL if next link is head +** +** SIDE EFFECTS & CAVEATS: +** !!! assumes that fcllistInitialize has been called on the linklist +** !!! if not, this function behavior is un-predictable +** +** !!! No validation is made on the list or the validity of the link +** !!! the caller must make sure that the link is in the list +** +** ALGORITHM: +** +*******************************************************************************/ + +#define comListGetNext(pList, pLink) (((pLink)->pNext == (pList)->pHead) ? \ + NULL : (pLink)->pNext) + + +/******************************************************************************* +** +** MODULE NAME: comListGetPrev +** +** PURPOSE: get the previous link in the list. (one toward head) +** +** PARAMETERS: PLINK_LIST OUT - Link list definition. +** PLINK_NODE IN - Link to get prev to +** +** return PLINK - points to previous link +** NULL if previous link is head +** +** SIDE EFFECTS & CAVEATS: +** !!! assumes that fcllistInitialize has been called on the linklist +** !!! if not, this function behavior is un-predictable +** +** !!! No validation is made on the list or the validity of the link +** !!! the caller must make sure that the link is in the list +** +** ALGORITHM: +** +*******************************************************************************/ + +/*lint -emacro(613,fiLlistGetPrev) */ + +#define comListGetPrev(pList, pLink) (((pLink)->pPrev == (pList)->pHead) ? \ + NULL : (pLink)->pPrev) + +#define AGT_INTERRUPT IRQF_DISABLED +#define AGT_SAMPLE_RANDOM IRQF_SAMPLE_RANDOM +#define AGT_SHIRQ IRQF_SHARED +#define AGT_PROBEIRQ IRQF_PROBE_SHARED +#define AGT_PERCPU IRQF_PERCPU + + +#include "lxproto.h" + diff --git a/sys/dev/pms/freebsd/driver/common/lxencrypt.c b/sys/dev/pms/freebsd/driver/common/lxencrypt.c new file mode 100644 index 000000000000..92e4ce1aae34 --- /dev/null +++ b/sys/dev/pms/freebsd/driver/common/lxencrypt.c @@ -0,0 +1,1165 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +*******************************************************************************/ +/******************************************************************************* +** +** Version Control Information: +** +** $Revision: 113920 $ +** $Author: mcleanda $ +** $Date: 2012-05-08 11:30:44 -0700 (Tue, 08 May 2012) $ +** $Id: lxencrypt.c 113920 2012-05-08 18:30:44Z mcleanda $ +** +*******************************************************************************/ + +#include +#include + +#include +#include +#include +#include + + +static atomic_t ioerr_queue_count; +#ifdef ENCRYPT_ENHANCE +/****************************************************************************** +careful_write(): + +Purpose: +Parameters: +Return: +Note: +******************************************************************************/ +static int +careful_write(char *buf, int offset, int max, const char *fmt, ...) +{ + static char s[PAGE_SIZE]; /* Assumes serialization */ + va_list args; + int i; + + if(offset > max) + return 0; + s[PAGE_SIZE - 1] = '\0'; + + va_start(args, fmt); + i = vsnprintf(s, PAGE_SIZE - 1, fmt, args); + if((offset + i) > max) + return 0; + memcpy(buf + offset, s, i); + va_end(args); + + return i; +} + +/****************************************************************************** +set_dek_table_entry(): + +Purpose: +Parameters: +Return: +Note: +******************************************************************************/ +static inline int +set_dek_table_entry(struct device *dev, const char *buf, size_t len, dek_table_e table) +{ + int index; + struct Scsi_Host *shost = class_to_shost(dev); + struct agtiapi_softc *pCard = (struct agtiapi_softc *) shost->hostdata; + + /* Check permissions */ + if(!capable(CAP_SYS_ADMIN)) + return -EACCES; + + if(!pCard->encrypt) + return -EINVAL; + + if(table != DEK_TABLE_0 && table != DEK_TABLE_1) + return -EINVAL; + + sscanf(buf, "%d", &index); + if(index >= 0 && index < DEK_MAX_TABLE_ITEMS) { + pCard->dek_index[table] = index; + return strlen(buf); + } + return -EINVAL; +} + +/****************************************************************************** +set_dek_table_entry0(): + +Purpose: +Parameters: +Return: +Note: +******************************************************************************/ +ssize_t +set_dek_table_entry0(struct device *dev, struct device_attribute *attr, const char *buf, size_t len) +{ + return set_dek_table_entry(dev, buf, len, DEK_TABLE_0); +} + +/****************************************************************************** +set_dek_table_entry1(): + +Purpose: +Parameters: +Return: +Note: +******************************************************************************/ +ssize_t +set_dek_table_entry1(struct device *dev, struct device_attribute *attr, const char *buf, size_t len) +{ + return set_dek_table_entry(dev, buf, len, DEK_TABLE_1); +} + + +/****************************************************************************** +show_dek_table_entry(): + +Purpose: +Parameters: +Return: +Note: +******************************************************************************/ +static inline int +show_dek_table_entry(struct device *dev, char *buf, unsigned int table) +{ + int i = 0, j; + unsigned char *p; + struct Scsi_Host *sh = class_to_shost(dev); + ag_card_t *pCard = (ag_card_t *) sh->hostdata; + ag_card_info_t *pCardInfo = pCard->pCardInfo; + ag_resource_info_t *pRscInfo = &pCardInfo->tiRscInfo; + tiEncryptDekBlob_t *pDekTable = NULL; + + if(!pCard->encrypt) + return -EINVAL; + + if(table == DEK_TABLE_0) + pDekTable = pRscInfo->tiLoLevelResource.loLevelMem.mem[DEK_MEM_INDEX_1].virtPtr; + else if(table == DEK_TABLE_1) + pDekTable = pRscInfo->tiLoLevelResource.loLevelMem.mem[DEK_MEM_INDEX_2].virtPtr; + if(pDekTable == NULL) + return -EINVAL; + + if(pCard->dek_index[table] >= 0 || pCard->dek_index[table] < DEK_MAX_TABLE_ITEMS) { + i += careful_write(buf, i, PAGE_SIZE, "%4d: ", pCard->dek_index[table]); + p = (unsigned char *) &pDekTable[pCard->dek_index[table]]; + for(j = 0; j < sizeof(tiEncryptDekBlob_t); j++) { + i += careful_write(buf, i, PAGE_SIZE, "%02x", p[j]); + } + i += careful_write(buf, i, PAGE_SIZE, "\n"); + } else { + i += careful_write(buf, i, PAGE_SIZE, "Bad DEK index %d; range: 0 - %d\n", pCard->dek_index[table], DEK_MAX_TABLE_ITEMS); + } + + /* BUG if we return more than a single page of data */ + //BUG_ON(i > PAGE_SIZE); + if (i > PAGE_SIZE) + i = PAGE_SIZE; + + return i; +} + +/****************************************************************************** +show_dek_table_entry0(): + +Purpose: +Parameters: +Return: +Note: +******************************************************************************/ +ssize_t +show_dek_table_entry0(struct device *dev, struct device_attribute *attr, char *buf) +{ + return show_dek_table_entry(dev, buf, DEK_TABLE_0); +} + +/****************************************************************************** +show_dek_table_entry1(): + +Purpose: +Parameters: +Return: +Note: +******************************************************************************/ +ssize_t +show_dek_table_entry1(struct device *dev, struct device_attribute *attr, char *buf) +{ + return show_dek_table_entry(dev, buf, DEK_TABLE_1); +} + +/****************************************************************************** +show_kek_table(): + +Purpose: +Parameters: +Return: +Note: +******************************************************************************/ +ssize_t +show_kek_table(struct device *dev, struct device_attribute *attr, char *buf) +{ + int i = 0, j, kek_index; + unsigned char *p; + struct Scsi_Host *sh = class_to_shost(dev); + ag_card_t *pCard = (ag_card_t *) sh->hostdata; + + if(!pCard->encrypt) + return -EINVAL; + + for(kek_index = 0; kek_index < KEK_TABLE_MAX_ENTRY; kek_index++) { + i += careful_write(buf, i, PAGE_SIZE, " %4d: %08x ", kek_index, pCard->kek_table[kek_index].wrapperIndex); + p = (unsigned char *) &pCard->kek_table[kek_index].kekBlob; + for(j = 0; j < sizeof(tiEncryptKekBlob_t); j++) { + i += careful_write(buf, i, PAGE_SIZE, "%02x", p[j]); + } + i += careful_write(buf, i, PAGE_SIZE, "\n"); + } + i += careful_write(buf, i, PAGE_SIZE, "\n"); + + /* BUG if we return more than a single page of data */ + //BUG_ON(i > PAGE_SIZE); + if (i > PAGE_SIZE) + i = PAGE_SIZE; + + return i; +} + +/****************************************************************************** +show_dek_kek_map(): + +Purpose: +Parameters: +Return: +Note: +******************************************************************************/ +static inline int +show_dek_kek_map(struct device *dev, char *buf, unsigned int table) +{ + int i = 0, dek_index; + struct Scsi_Host *sh = class_to_shost(dev); + ag_card_t *pCard = (ag_card_t *) sh->hostdata; + + if(!pCard->encrypt) + return -EINVAL; + + if(table != DEK_TABLE_0 && table != DEK_TABLE_1) + return -EINVAL; + + i += careful_write(buf, i, PAGE_SIZE, "Table %d\n", table); + i += careful_write(buf, i, PAGE_SIZE, "=======\n"); + for(dek_index = 0; dek_index < DEK_MAX_TABLE_ITEMS; dek_index++) { + i += careful_write(buf, i, PAGE_SIZE, " %4d: %08x\n", dek_index, pCard->dek_kek_map[table][dek_index].kekIndex); + } + i += sprintf(buf + i, "\n"); + + /* BUG if we return more than a single page of data */ + //BUG_ON(i > PAGE_SIZE); + if (i > PAGE_SIZE) + i = PAGE_SIZE; + + return i; +} + +/****************************************************************************** +show_dek_kek_map0(): + +Purpose: +Parameters: +Return: +Note: +******************************************************************************/ +ssize_t + +show_dek_kek_map0(struct device *dev, struct device_attribute *attr, char *buf) +{ + return show_dek_kek_map(dev, buf, 0); +} + +/****************************************************************************** +show_dek_kek_map1(): + +Purpose: +Parameters: +Return: +Note: +******************************************************************************/ +ssize_t +show_dek_kek_map1(struct device *dev, struct device_attribute *attr, char *buf) +{ + return show_dek_kek_map(dev, buf, 1); +} + +/****************************************************************************** +show_target_dek_map(): + +Purpose: +Parameters: +Return: +Note: +******************************************************************************/ +ssize_t +show_target_dek_map(struct device *dev, struct device_attribute *attr, char *buf) +{ + int i = 0; + unsigned int chan, device, lun = 0; + ag_encrypt_map_t *p; + struct list_head *lh; + struct Scsi_Host *sh = class_to_shost(dev); + ag_card_t *pCard = (ag_card_t *) sh->hostdata; + + if(!pCard->encrypt) + return -EINVAL; + + for(chan = 0; chan <= AGTIAPI_MAX_CHANNEL_NUM; chan++) { + for(device = 0; device < pCard->devDiscover; device++) { +#ifdef REPORT_ALL_LUNS + for(lun = 0; lun < AGTIAPI_MAX_LUN; lun++) { +#endif + lh = MAP_TABLE_ENTRY(pCard, chan, device, lun); + if(lh) { + list_for_each_entry(p, lh, list) { + if(p->dekIndex != DEK_INDEX_INVALID) + i += careful_write(buf, i, PAGE_SIZE, " %u:%u:%u: %x %8x %8x %16lx %16lx %08x:%08x %1x\n", chan, device, lun, p->dekTable, p->dekIndex, p->kekIndex, p->lbaMin, p->lbaMax, p->keyTag[1], p->keyTag[0], p->keyTagCheck); + } + } +#ifdef REPORT_ALL_LUNS + } +#endif + } + } + + if (i > PAGE_SIZE) + i = PAGE_SIZE; + + return i; +} + + +/****************************************************************************** +agtiapi_AddDek(): + +Purpose: +Parameters: +Return: +Note: +******************************************************************************/ +static int +agtiapi_AddDek(ag_card_t *pCard, bit32 dek_table, bit32 dek_index, bit32 blob_format, bit32 entry_sz, tiEncryptDekBlob_t *dek_blob, U32_64 *addr) +{ + ag_resource_info_t *pRscInfo = &pCard->pCardInfo->tiRscInfo; + tiEncryptDekBlob_t *pDekTable; + char *p; + + if (dek_index >= DEK_MAX_TABLE_ITEMS) { + printf("%s: Bad dek index 0x%x (MAX: 0x%x).\n", __FUNCTION__, dek_index, DEK_MAX_TABLE_ITEMS); + return -E_DEK_INDEX; + } + + switch(dek_table) { + case DEK_TABLE_0: + pDekTable = pRscInfo->tiLoLevelResource.loLevelMem.mem[DEK_MEM_INDEX_1].virtPtr; + break; + case DEK_TABLE_1: + pDekTable = pRscInfo->tiLoLevelResource.loLevelMem.mem[DEK_MEM_INDEX_2].virtPtr; + break; + default: + printf("%s: Unknown dek table %d\n", __FUNCTION__, dek_table); + return -E_DEK_TABLE; + } + + #ifdef __VMKLNX__ + *addr = (U32_64) __pa(&pDekTable[0]); + #else + *addr = (U32_64) virt_to_phys(&pDekTable[0]); + #endif + + p = (char *) &pDekTable[0] + (dek_index * pCard->dek_size); + + printf("%s: Base: %p, Index: %08x, Virt: %p Size: %d\n", __FUNCTION__, pDekTable, dek_index, &pDekTable[dek_index], pCard->dek_size); + memcpy(p, dek_blob, pCard->dek_size); + wmb(); + + /* Flush entry */ + ostiCacheFlush(&pCard->tiRoot, NULL, p, pCard->dek_size); + + return 0; +} + +/****************************************************************************** +agtiapi_MapDekKek(): + +Purpose: +Parameters: +Return: +Note: +******************************************************************************/ +static int +agtiapi_MapDekKek(ag_card_t *pCard, bit32 dek_table, bit32 dek_index, bit32 kek_index) +{ + if (dek_index >= DEK_MAX_TABLE_ITEMS) { + printf("%s: Bad dek index 0x%x (MAX: 0x%x).\n", __FUNCTION__, dek_index, DEK_MAX_TABLE_ITEMS); + return -E_DEK_INDEX; + } + + if (dek_table >= DEK_MAX_TABLES) { + printf("%s: Bad dek table.\n", __FUNCTION__); + return -E_DEK_TABLE; + } + + if (kek_index >= KEK_TABLE_MAX_ENTRY) { + printf("%s: Bad kek index.\n", __FUNCTION__); + return -E_KEK_INDEX; + } + + pCard->dek_kek_map[dek_table][dek_index].kekIndex = kek_index; + return 0; +} + +/****************************************************************************** +agtiapi_AddKek(): + +Purpose: +Parameters: +Return: +Note: +******************************************************************************/ +static int +agtiapi_AddKek(ag_card_t *pCard, bit32 kek_index, bit32 wrapper_kek_index, tiEncryptKekBlob_t *kek_blob) +{ + if (kek_index >= KEK_TABLE_MAX_ENTRY) { + printf("%s: Bad kek index.\n", __FUNCTION__); + return -E_KEK_INDEX; + } + if (wrapper_kek_index >= KEK_TABLE_MAX_ENTRY) { + printf("%s: Bad kek wrapper index.\n", __FUNCTION__); + return -E_KEK_INDEX; + } + pCard->kek_table[kek_index].wrapperIndex = wrapper_kek_index; + memcpy(&pCard->kek_table[kek_index].kekBlob, kek_blob, sizeof(tiEncryptKekBlob_t)); + return 0; +} + +/****************************************************************************** +agtiapi_MapDek(): + +Purpose: +Parameters: +Return: +Note: +******************************************************************************/ +static int +agtiapi_MapDek(ag_card_t *pCard, EncryptDeviceDekMap_t *dek_map) +{ + int found = 0; + bit32 chan, device, lun; + bit32 dek_table, dek_index, kek_index; + unsigned long long lba_min, lba_max; + ag_encrypt_map_t *p, *n; + struct list_head *lh; + + chan = dek_map->channel; + device = dek_map->device; + lun = dek_map->lun; + + lba_min = dek_map->dekMapEntry[0].startLBA; + lba_max = dek_map->dekMapEntry[0].endLBA; + + dek_table = dek_map->dekMapEntry[0].dek.dekTable; + dek_index = dek_map->dekMapEntry[0].dek.dekIndex; + + /* Sanity check channel, device, lun */ + if (chan > AGTIAPI_MAX_CHANNEL_NUM) { + printf("%s: Bad channel %d.\n", __FUNCTION__, chan); + return -E_CHANNEL_INDEX; + } + if (device >= pCard->devDiscover) { + printf("%s: Bad device %d.\n", __FUNCTION__, device); + return -E_DEVICE_INDEX; + } + if (lun >= AGTIAPI_MAX_LUN) { + printf("%s: Bad lun %d.\n", __FUNCTION__, lun); + return -E_LUN_INDEX; + } + + /* Sanity check dek index */ + if (dek_index >= DEK_MAX_TABLE_ITEMS) { + printf("%s: Bad dek index 0x%x (MAX: 0x%x).\n", __FUNCTION__, dek_index, DEK_MAX_TABLE_ITEMS); + return -E_DEK_INDEX; + } + + /* Sanity check dek table */ + if (dek_table >= DEK_MAX_TABLES) { + printf("%s: Bad dek table %d.\n", __FUNCTION__, dek_table); + return -E_DEK_TABLE; + } + + /* Check that lba min and lba max are sane */ + if (lba_min >= lba_max) { + printf("%s: Bad lba min and lba max: %llx %llx.\n", __FUNCTION__, lba_min, lba_max); + return -E_LBA_RANGE; + } + + /* dek_table and dek_index are valid, look up kek */ + kek_index = pCard->dek_kek_map[dek_table][dek_index].kekIndex; + + lh = MAP_TABLE_ENTRY(pCard, chan, device, lun); + + if (dek_map->dekMapEntry[0].flags & ENCRYPT_DEK_MAP_ENTRY_CLEAR) { + /* Delete the entry */ + found = 0; + list_for_each_entry_safe(p, n, lh, list) { + if (p->lbaMin == lba_min && + p->lbaMax == lba_max && + p->dekTable == dek_table && + p->dekIndex == dek_index && + p->kekIndex == kek_index) { + /* Entry found, unlink and reclaim it */ + found = 1; + list_del(&p->list); + mempool_free(p, pCard->map_mempool); + } + } + if (!found) { + printf("%s: Entry %x %x %x %llx %llx not found.\n", __FUNCTION__, dek_table, dek_index, kek_index, lba_min, lba_max); + return -E_NOT_FOUND; + } + } else if (dek_map->dekMapEntry[0].flags & ENCRYPT_DEK_MAP_ENTRY_VALID) { + /* Add the entry */ + + p = (ag_encrypt_map_t *)uma_zalloc(pCard->map_cache, M_WAITOK); //Encryption + if (!p) { + printf("%s: Unable to allocate from memory pool.\n", __FUNCTION__); + return -E_MEMPOOL_ALLOC; + } + + /* Populate it */ + p->lbaMin = lba_min; + p->lbaMax = lba_max; + p->dekTable = dek_table; + p->dekIndex = dek_index; + p->kekIndex = kek_index; + p->keyTagCheck = dek_map->keytag_check; + memcpy(&p->keyTag, &dek_map->keytag, sizeof(p->keyTag)); + + /* Test to see if this new mapping overlaps an existing mapping */ + list_for_each_entry(n, lh, list) { + /* + * Check if the start lba falls in existing range || + * Check if the end lba falls in existing range || + * Check if the start lba of the existing range falls in the new range + */ + if (((p->lbaMin >= n->lbaMin) && (p->lbaMin <= n->lbaMax)) || + ((p->lbaMax >= n->lbaMin) && (p->lbaMax <= n->lbaMax)) || + ((n->lbaMin >= p->lbaMin) && (n->lbaMin <= p->lbaMax))) { + printf("%s: WARNING: New entry lba range overlap: %llx - %llx vs %llx - %llx.\n", __FUNCTION__, p->lbaMin, p->lbaMax, n->lbaMin, n->lbaMax); + } + } + + /* Link it in to list at the head so it takes precedence */ + list_add(&p->list, lh); + + /* TODO: Decide if/how to refcount each dek/kek index used by the mapping */ + + } else { + printf("%s: Bad flags %08x\n", __FUNCTION__, dek_map->dekMapEntry[0].flags); + return -E_FLAGS; + } + + return 0; +} +#endif +#ifdef HIALEAH_ENCRYPTION +/****************************************************************************** +agtiapi_SetupEncryption(): + +Purpose: +Parameters: +Return: +Note: +******************************************************************************/ +int +agtiapi_SetupEncryption(struct agtiapi_softc *pCard) +{ + tiRoot_t *tiRoot = (tiRoot_t *) &pCard->tiRoot; + bit32 status = tiSuccess; + printf("agtiapi_SetupEncryption: HIALEAH_ENCRYPTION\n"); + if (pCard->encrypt == agTRUE) + { + status = tiCOMEncryptGetInfo(tiRoot); + printf("agtiapi_SetupEncryption: HIALEAH_ENCRYPTION tiCOMEncryptGetInfo Status 0x%x\n",status); + + if(status == 1 ) + { + status = tiCOMEncryptHilSet(tiRoot ); + if (status) { + pCard->encrypt = agFALSE; + printf("agtiapi_SetupEncryption: HIALEAH_ENCRYPTION not set\n"); + } + } + } + return 0; +} +#ifdef ENCRYPT_ENHANCE +/****************************************************************************** +agtiapi_SetupEncryptionPools(): + +Purpose: +Parameters: +Return: +Note: +******************************************************************************/ +int +agtiapi_SetupEncryptionPools(struct agtiapi_softc *pCard) +{ + /* Configure encryption memory pool */ + memset(pCard->map_cache_name, 0, sizeof(pCard->map_cache_name)); + snprintf(pCard->map_cache_name, sizeof(pCard->map_cache_name) - 1, "map_cache_%d", pCard->cardNo); + +//zone allocation + pCard->map_cache = uma_zcreate(pCard->map_cache_name, sizeof(ag_encrypt_map_t),NULL, NULL, NULL, NULL, 0, 0); + if(!pCard->map_cache) { + /* + * This error may be due to an existing cache in the kernel + * from an earlier kmem_cache that wasn't properly freed + */ + printf("Unable to create uma_zcreate cache for encryption map mempool.\n"); + return -EFAULT; + } + uma_zone_set_max(pCard->map_cache, ENCRYPTION_MAP_MEMPOOL_SIZE); + + + /* Configure encryption IO error pool */ + INIT_LIST_HEAD(&pCard->ioerr_queue); +/*#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34)) // #### + pCard->ioerr_queue_lock = SPIN_LOCK_UNLOCKED; +#else */ + pCard->ioerr_queue_lock = AG_SPIN_UNLOCK(pCard->ioerr_queue_lock); +//#endif + + + memset(pCard->ioerr_cache_name, 0, sizeof(pCard->ioerr_cache_name)); + snprintf(pCard->ioerr_cache_name, sizeof(pCard->ioerr_cache_name) - 1, "ioerr_cache_%d", pCard->cardNo); + + pCard->ioerr_cache = uma_zcreate(pCard->ioerr_cache_name, sizeof(ag_encrypt_ioerr_t), NULL, NULL, NULL, NULL, 0, 0); + if(!pCard->ioerr_cache) { + /* + * This error may be due to an existing cache in the kernel + * from an earlier kmem_cache that wasn't properly freed + */ + printf("Unable to create kmem cache for encryption IO error mempool.\n"); + return -EFAULT; + } + uma_zone_set_max(pCard->ioerr_cache, ENCRYPTION_IO_ERR_MEMPOOL_SIZE); + + /* Set cipher mode to something invalid */ + pCard->cipher_mode = CIPHER_MODE_INVALID; + + return 0; +} +#endif +/****************************************************************************** +agtiapi_CleanupEncryption(): + +Purpose: +Parameters: +Return: +Note: +******************************************************************************/ +void +agtiapi_CleanupEncryption(struct agtiapi_softc *pCard) +{ +#ifdef ENCRYPT_ENHANCE + if(pCard->encrypt_map) { + int chan, device, lun; + struct list_head *lh; + ag_encrypt_map_t *p, *n; + + for (chan = 0; chan < (AGTIAPI_MAX_CHANNEL_NUM + 1); chan++) { + for (device = 0; device < pCard->devDiscover; device++) { + for (lun = 0; lun < AGTIAPI_MAX_LUN; lun++) { + lh = MAP_TABLE_ENTRY(pCard, chan, device, lun); + list_for_each_entry_safe(p, n, lh, list) { + // mempool_free(p, pCard->map_mempool); + } + } + } + } + vfree(pCard->encrypt_map); + pCard->encrypt_map = NULL; + } +#endif +} + +#ifdef ENCRYPT_ENHANCE +/****************************************************************************** +agtiapi_CleanupEncryptionPools(): + +Purpose: +Parameters: +Return: +Note: +******************************************************************************/ +void +agtiapi_CleanupEncryptionPools(struct agtiapi_softc *pCard) +{ + ag_encrypt_ioerr_t *ioerr, *tmp; + atomic_set(&ioerr_queue_count); + + /* + * TODO: check "outstanding_encrypted_io_count" for non-zero + * and free all mempool items prior to destroying pool + */ + + /* Clean up memory pools */ + if (pCard->map_mempool) { + mempool_destroy(pCard->map_mempool); + printf("Encryption Map mempool released.\n"); + pCard->map_mempool = NULL; + } + + /* Clean up kmem cache */ + if (pCard->map_cache) { + kmem_cache_destroy(pCard->map_cache); + printf("Kernel memory cache %s released.\n", pCard->map_cache_name); + pCard->map_cache = NULL; + } + + /* Clean up memory pools */ + list_for_each_entry_safe(ioerr, tmp, &pCard->ioerr_queue, list) { + list_del_init(&ioerr->list); + mempool_free(ioerr, pCard->ioerr_mempool); + atomic_dec(&ioerr_queue_count); + } + + if (pCard->ioerr_mempool) { + mempool_destroy(pCard->ioerr_mempool); + printf("Encryption IO Error mempool released.\n"); + pCard->ioerr_mempool = NULL; + } + + /* Clean up kmem cache */ + if (pCard->ioerr_cache) { + kmem_cache_destroy(pCard->ioerr_cache); + printf("Kernel memory cache %s released.\n", pCard->ioerr_cache_name); + pCard->ioerr_cache = NULL; + } +} + +/****************************************************************************** +agtiapi_EncryptionIoctl(): + +Purpose: +Parameters: +Return: +Note: +******************************************************************************/ +int +agtiapi_EncryptionIoctl(struct agtiapi_softc *pCard, IoctlEncrypt_t *pIoctlPayload) +{ + int rv, rc = 0, skip_wait = 0; + tiRoot_t *tiRoot = (tiRoot_t *) &pCard->tiRoot; + IoctlTISAEncrypt_t *ioctl_data = &pIoctlPayload->body; + pIoctlPayload->hdr.Status = IOCTL_ERR_STATUS_INVALID_CODE; + pCard->ioctl_data = (void *) ioctl_data; + init_completion(&pCard->ioctl_completion); + + /* Check that the system is quiesced */ + if (atomic_read(&outstanding_encrypted_io_count) != 0) + printf("%s: WARNING: Attempting encryption management update with outstanding encrypted IOs!\n", __FUNCTION__); + +printf("%s: Minor %d\n", __FUNCTION__, pIoctlPayload->hdr.MinorFunction); + switch(pIoctlPayload->hdr.MinorFunction) { + case IOCTL_MN_ENCRYPTION_GET_INFO: + { + //IoctlEncryptGetInfo_t *get_info = (IoctlEncryptGetInfo_t *) &ioctl_data->request; + rc = tiCOMEncryptGetInfo(tiRoot); + } + break; + case IOCTL_MN_ENCRYPTION_SET_MODE: + { + u32 reg_val = 0, new_cipher_mode = 0; + IoctlEncryptSetMode_t *set_mode = (IoctlEncryptSetMode_t *) &ioctl_data->request; + + printf("%s: input %08x\n", __FUNCTION__, set_mode->securityCipherMode); + + /* Set security mode */ + if(TI_ENCRYPT_SEC_MODE_FACT_INIT) + if(set_mode->securityCipherMode & TI_ENCRYPT_SEC_MODE_FACT_INIT) { + reg_val |= TI_ENCRYPT_SEC_MODE_FACT_INIT; + pCard->dek_size = DEK_SIZE_PLAIN; + } + if(set_mode->securityCipherMode & TI_ENCRYPT_SEC_MODE_A) { + reg_val |= TI_ENCRYPT_SEC_MODE_A; + pCard->dek_size = DEK_SIZE_ENCRYPT; + } else if(set_mode->securityCipherMode & TI_ENCRYPT_SEC_MODE_B) { + reg_val |= TI_ENCRYPT_SEC_MODE_B; + pCard->dek_size = DEK_SIZE_ENCRYPT; + } + + /* Set cipher mode */ + if(set_mode->securityCipherMode & TI_ENCRYPT_ATTRIB_CIPHER_XTS) { + reg_val |= TI_ENCRYPT_ATTRIB_CIPHER_XTS; + new_cipher_mode = TI_ENCRYPT_MODE_XTS_AES; + } + + printf("%s: Setting security cipher mode to: 0x%08x\n", __FUNCTION__, reg_val); + pCard->cipher_mode = new_cipher_mode; + + rc = tiCOMEncryptSetMode(tiRoot, reg_val); + } + break; + case IOCTL_MN_ENCRYPTION_KEK_ADD: + { + tiEncryptKekBlob_t kek_blob; + IoctlEncryptKekAdd_t *kek_add = (IoctlEncryptKekAdd_t *) &ioctl_data->request; + printf("%s: Add kek at index 0x%x wrapper 0x%x format 0x%x\n", __FUNCTION__, kek_add->kekIndex, kek_add->wrapperKekIndex, kek_add->blobFormat); + + /* Copy kek_blob from user pointer to local buffer */ + if(access_ok(VERIFY_READ, kek_add->EncryptKekBlob, sizeof(kek_blob))) { + printf("%s: Starting copy from user %p to kernel %p\n", __FUNCTION__, kek_add->EncryptKekBlob, &kek_blob); + if((rv = copy_from_user(&kek_blob, kek_add->EncryptKekBlob, sizeof(kek_blob))) != 0) { + printf("%s: Copy error, %d left\n", __FUNCTION__, rv); + return IOCTL_CALL_FAIL; + } + rc = tiCOMEncryptKekAdd(tiRoot, kek_add->kekIndex, kek_add->wrapperKekIndex, kek_add->blobFormat, &kek_blob); + + /* Add kek to local kek table (in case of chip reset) */ + if(rc == tiSuccess) { + if(agtiapi_AddKek(pCard, kek_add->kekIndex, kek_add->wrapperKekIndex, &kek_blob) < 0) { + return IOCTL_CALL_FAIL; + } + } + } else { + return IOCTL_CALL_FAIL; + } + } + break; + case IOCTL_MN_ENCRYPTION_DEK_ADD: + { + tiEncryptDekBlob_t dek_blob; /* Copied in */ + IoctlEncryptDekAdd_t *dek_add = (IoctlEncryptDekAdd_t *) &ioctl_data->request; + bit32 kek_index = dek_add->kekIndex; + bit32 dek_index = dek_add->dekIndex; + bit32 dek_table = dek_add->dekTable; + bit32 blob_format = dek_add->dekBlobFormat; + bit32 entry_sz = dek_add->dekTableKeyEntrySize; + U32_64 addr = 0; + bit32 addr_table[2]; + memset(addr_table, 0, sizeof(addr_table)); + + printf("%s: Add dek at index 0x%x, table %x, kek index %x, blob format %x, entry size %x\n", __FUNCTION__, dek_index, dek_table, kek_index, blob_format, entry_sz); + + /* Copy dek_blob from user pointer to local buffer */ + if(access_ok(VERIFY_READ, dek_add->dekBlob, sizeof(dek_blob))) { + printf("%s: Starting copy from user %p to kernel %p\n", __FUNCTION__, dek_add->dekBlob, &dek_blob); + if((rv = copy_from_user(&dek_blob, dek_add->dekBlob, sizeof(dek_blob))) != 0) { + printf("%s: Copy error, %d left\n", __FUNCTION__, rv); + return IOCTL_CALL_FAIL; + } + + /* Add DEK to local table */ + if (agtiapi_AddDek(pCard, dek_table, dek_index, blob_format, entry_sz, &dek_blob, &addr) < 0) { + return IOCTL_CALL_FAIL; + } + memcpy(addr_table, &addr, sizeof(addr)); + + /* Add DEK-KEK association in local table */ + if (agtiapi_MapDekKek(pCard, dek_table, dek_index, kek_index) < 0) { + return IOCTL_CALL_FAIL; + } + + /* Push DEK to chip */ + rc = tiCOMEncryptDekAdd(tiRoot, kek_index, dek_table, addr_table[1], addr_table[0], dek_index, 1, blob_format, entry_sz); + } else { + return IOCTL_CALL_FAIL; + } + } + break; + case IOCTL_MN_ENCRYPTION_DEK_INVALID: + { + IoctlEncryptDekInvalidate_t *dek_to_invalidate = (IoctlEncryptDekInvalidate_t *) &ioctl_data->request; + printf("%s: Invalidating dek at index 0x%x, table %x\n", __FUNCTION__, dek_to_invalidate->dek.dekIndex, dek_to_invalidate->dek.dekTable); + + rc = tiCOMEncryptDekInvalidate(tiRoot, dek_to_invalidate->dek.dekTable, dek_to_invalidate->dek.dekIndex); + /* TODO: What to do in local tables? Mark it? */ + } + break; + case IOCTL_MN_ENCRYPTION_KEK_NVRAM: + { + rc = tiError; + } + break; + case IOCTL_MN_ENCRYPTION_DEK_ASSIGN: + { + IoctlEncryptDekMapTable_t *p_dek_map = (IoctlEncryptDekMapTable_t *) &ioctl_data->request; + + /* Fill in host */ + p_dek_map->dekMap[0].host = (bit32) pCard->pHost->host_no; + + printf("%s: Host %u: Mapping %u:%u:%u (%llx to %llx) to dek at index 0x%x, table %x, keytag %08x:%08x\n", __FUNCTION__, p_dek_map->dekMap[0].host, p_dek_map->dekMap[0].channel, p_dek_map->dekMap[0].device, p_dek_map->dekMap[0].lun, p_dek_map->dekMap[0].dekMapEntry[0].startLBA, p_dek_map->dekMap[0].dekMapEntry[0].endLBA, p_dek_map->dekMap[0].dekMapEntry[0].dek.dekIndex, p_dek_map->dekMap[0].dekMapEntry[0].dek.dekTable, p_dek_map->dekMap[0].keytag[1], p_dek_map->dekMap[0].keytag[0]); + + /* Create a mapping in local tables */ + if (agtiapi_MapDek(pCard, &p_dek_map->dekMap[0]) < 0) { + pIoctlPayload->hdr.Status = IOCTL_ERR_STATUS_INVALID_CODE; + return IOCTL_CALL_FAIL; + } + + rc = tiSuccess; + skip_wait = 1; + ioctl_data->encryptFunction = encryptSetDekMap; + ioctl_data->status = tiSuccess; + ioctl_data->subEvent = 0; + } + break; + case IOCTL_MN_ENCRYPTION_ERROR_QUERY: + { + unsigned long flags, i, query_flag; + ag_encrypt_ioerr_t *ioerr, *tmp; + IoctlEncryptErrorQuery_t *perr = (IoctlEncryptErrorQuery_t *) &ioctl_data->request; + + printf("%s: query flag %x\n", __FUNCTION__, perr->query_flag); + query_flag = perr->query_flag; + + /* initialize */ + memset(perr, 0, sizeof(IoctlEncryptErrorQuery_t)); + +error_query_restart: + /* Take spinlock */ + // spin_lock_irqsave(&pCard->ioerr_queue_lock, flags); + AG_SPIN_LOCK_IRQ(&pCard->ioerr_queue_lock, flags); + + /* Walk list */ + i = 0; + list_for_each_entry_safe(ioerr, tmp, &pCard->ioerr_queue, list) { + if (i >= 32) + break; + + perr->valid_mask |= (1 << i); + memcpy(&perr->error[i], &ioerr->ioerr, sizeof(IoctlEncryptIOError_t)); + list_del_init(&ioerr->list); + mempool_free(ioerr, pCard->ioerr_mempool); + i++; + atomic_dec(&ioerr_queue_count); + } + + /* Release spinlock */ + // spin_unlock_irqrestore(&pCard->ioerr_queue_lock, flags); + AG_SPIN_UNLOCK_IRQ(&pCard->ioerr_queue_lock, flags); //for test + + if (!perr->valid_mask) { + /* No encryption IO error events, check flags to see if blocking wait OK */ + if (query_flag == ERROR_QUERY_FLAG_BLOCK) { + if (wait_event_interruptible(ioerr_waitq, (atomic_read(&ioerr_queue_count)))) { + /* Awoken by signal */ + return IOCTL_CALL_FAIL; + } else { + /* Awoken by IO error */ + goto error_query_restart; + } + } + } + rc = tiSuccess; + skip_wait = 1; + ioctl_data->encryptFunction = encryptErrorQuery; + ioctl_data->status = tiSuccess; + ioctl_data->subEvent = 0; + } + break; + default: + printf("%s: Unrecognized Minor Function %d\n", __FUNCTION__, pIoctlPayload->hdr.MinorFunction); + pIoctlPayload->hdr.Status = IOCTL_ERR_STATUS_INVALID_CODE; + return IOCTL_CALL_FAIL; + break; + } + + /* Demux rc */ + switch(rc) { + case tiSuccess: + if(!skip_wait) + wait_for_completion(&pCard->ioctl_completion); + /* Maybe: wait_for_completion_timeout() */ + pIoctlPayload->hdr.Status = ioctl_data->status; + break; + case tiNotSupported: + pIoctlPayload->hdr.Status = IOCTL_ERR_STATUS_NOT_SUPPORTED; + break; + default: + printf("%s: Status: %d\n", __FUNCTION__, rc); + pIoctlPayload->hdr.Status = IOCTL_ERR_STATUS_INVALID_CODE; + break; + } + + printf("%s: Encryption ioctl %d successful.\n", __FUNCTION__, pIoctlPayload->hdr.MinorFunction); + return IOCTL_CALL_SUCCESS; +} +#endif +/****************************************************************************** +agtiapi_SetupEncryptedIO(): + +Purpose: +Parameters: +Return: +Note: +******************************************************************************/ +int +agtiapi_SetupEncryptedIO(struct agtiapi_softc *pCard, ccb_t *pccb, unsigned long long block) +{ + + pCard->cipher_mode = TI_ENCRYPT_ATTRIB_CIPHER_XTS; + /* Check that cipher mode is set properly */ + if (pCard->cipher_mode == CIPHER_MODE_INVALID) { + printf("%s: Cipher mode not yet set.\n", __FUNCTION__); + return -E_BAD_CIPHER_MODE; + } + + memset(&(pccb->tiSuperScsiRequest.Encrypt), 0, sizeof(pccb->tiSuperScsiRequest.Encrypt)); + pccb->tiSuperScsiRequest.Encrypt.keyTagCheck = FALSE; + pccb->tiSuperScsiRequest.Encrypt.encryptMode = pCard->cipher_mode; + pccb->tiSuperScsiRequest.Encrypt.tweakVal_W0 = block; + if(pccb->tiSuperScsiRequest.scsiCmnd.cdb[0] == READ_16 || + pccb->tiSuperScsiRequest.scsiCmnd.cdb[0] == WRITE_16) + { + pccb->tiSuperScsiRequest.Encrypt.tweakVal_W0 = ((pccb->tiSuperScsiRequest.scsiCmnd.cdb[6] << 24 ) | + (pccb->tiSuperScsiRequest.scsiCmnd.cdb[7] << 16 ) | + (pccb->tiSuperScsiRequest.scsiCmnd.cdb[8] << 8 ) | + (pccb->tiSuperScsiRequest.scsiCmnd.cdb[9])); + pccb->tiSuperScsiRequest.Encrypt.tweakVal_W1 = ((pccb->tiSuperScsiRequest.scsiCmnd.cdb[2] << 24 ) | + (pccb->tiSuperScsiRequest.scsiCmnd.cdb[3] << 16 ) | + (pccb->tiSuperScsiRequest.scsiCmnd.cdb[4] << 8 ) | + (pccb->tiSuperScsiRequest.scsiCmnd.cdb[5])); + } + /* Mark IO as valid encrypted IO */ + pccb->flags |= ENCRYPTED_IO; + pccb->tiSuperScsiRequest.flags = TI_SCSI_INITIATOR_ENCRYPT; + + /* Bump refcount (atomic) */ + atomic_inc(&outstanding_encrypted_io_count); + return 0; +} + +/****************************************************************************** +agtiapi_CleanupEncryptedIO(): + +Purpose: +Parameters: +Return: +Note: +******************************************************************************/ +void +agtiapi_CleanupEncryptedIO(struct agtiapi_softc *pCard, ccb_t *pccb) +{ + if ((pccb->flags & ENCRYPTED_IO)) { + /* Decrement refcount */ + atomic_dec(&outstanding_encrypted_io_count); + } + pccb->tiSuperScsiRequest.flags &= ~TI_SCSI_INITIATOR_ENCRYPT; + pccb->flags &= ~ENCRYPTED_IO; +} +#ifdef ENCRYPT_ENHANCE +/****************************************************************************** +agtiapi_HandleEncryptedIOFailure(): + +Purpose: +Parameters: +Return: +Note: +******************************************************************************/ +void +agtiapi_HandleEncryptedIOFailure(ag_device_t *pDev, ccb_t *pccb) +{ + unsigned long flags, qdepth; + struct scsi_cmnd *cmd; + ag_encrypt_ioerr_t *perr; + ag_card_t *pCard; + + cmd = pccb->cmd; + if (!cmd) { + printf("%s: Malformed pccb %p.\n", __FUNCTION__, pccb); + return; + } + + pCard = pDev->pCard; + + /* Sanity check */ + if (!(pccb->flags & ENCRYPTED_IO)) { + printf("%s: Skipping IO %lx: Not Encrypted.\n", __FUNCTION__, cmd->serial_number); + return; + } + + /* Check queue depth against max */ + qdepth = atomic_read(&ioerr_queue_count); + if (qdepth >= IOERR_QUEUE_DEPTH_MAX) { + printf("%s: Not queueing IO error due to queue full: %lu entries.\n", __FUNCTION__, qdepth); + return; + } + + /* Get a container for the ag_encrypt_ioerr_t item from the mempool */ +// perr = mempool_alloc(pCard->ioerr_mempool, GFP_ATOMIC); + p = (ag_encrypt_map_t *)uma_zalloc(pCard->map_cache, M_WAITOK); //Encryption + if (!perr) { + printf("%s: Mempool allocation failure.\n", __FUNCTION__); + return; + } + + /* Populate ag_encrypt_ioerr_t container */ + perr->ioerr.error_id = cmd->serial_number; + perr->ioerr.timestamp = cmd->jiffies_at_alloc; + perr->ioerr.host = (unsigned int) cmd->device->host->host_no; + perr->ioerr.channel = cmd->device->channel; + perr->ioerr.device = cmd->device->id; + perr->ioerr.lun = cmd->device->lun; + perr->ioerr.scsi_cmd = (unsigned int) cmd->cmnd[0]; + perr->ioerr.dek_index = pccb->tiSuperScsiRequest.Encrypt.dekInfo.dekIndex; + perr->ioerr.dek_table = pccb->tiSuperScsiRequest.Encrypt.dekInfo.dekTable; + perr->ioerr.kek_index = pccb->tiSuperScsiRequest.Encrypt.kekIndex; + perr->ioerr.keytag_check = pccb->tiSuperScsiRequest.Encrypt.keyTagCheck; + perr->ioerr.encrypt_mode = pccb->tiSuperScsiRequest.Encrypt.encryptMode; + perr->ioerr.keytag[0] = pccb->tiSuperScsiRequest.Encrypt.keyTag_W0; + perr->ioerr.keytag[1] = pccb->tiSuperScsiRequest.Encrypt.keyTag_W1; + + switch(pccb->scsiStatus) { + case tiDetailDekKeyCacheMiss: + case tiDetailDekIVMismatch: + perr->ioerr.error_type = pccb->scsiStatus; + break; + default: + printf("%s: Unrecognized encrypted IO completion error status: %d\n", __FUNCTION__, pccb->scsiStatus); + perr->ioerr.error_type = 0xffffffff; + break; + } + + /* Link IO err into queue */ + AG_SPIN_LOCK_IRQ(&pCard->ioerr_queue_lock, flags); + list_add_tail(&perr->list, &pCard->ioerr_queue); + AG_SPIN_UNLOCK_IRQ(&pCard->ioerr_queue_lock, flags); + + /* Notify any wait queue waiters that an IO error has occurred */ + atomic_inc(&ioerr_queue_count); + wake_up_interruptible(&ioerr_waitq); + +} +#endif +#endif diff --git a/sys/dev/pms/freebsd/driver/common/lxencrypt.h b/sys/dev/pms/freebsd/driver/common/lxencrypt.h new file mode 100644 index 000000000000..448cbca3d517 --- /dev/null +++ b/sys/dev/pms/freebsd/driver/common/lxencrypt.h @@ -0,0 +1,103 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +*******************************************************************************/ +/******************************************************************************* +** +** Version Control Information: +** +** $Revision: 114125 $ +** $Author: lindfors $ +** $Date: 2012-01-06 17:12:27 -0800 (Fri, 06 Jan 2012) $ +** $Id: lxencrypt.h 112360 2012-01-07 01:12:27Z mcleanda $ +** +*******************************************************************************/ + +//#ifndef __LXENCRYPT_H__ +//#define __LXENCRYPT_H__ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include //zone allocation +#include //zone allocation +#include //zone allocation + + +#ifndef __LXENCRYPT_H__ +#define __LXENCRYPT_H__ + +#define IOERR_QUEUE_DEPTH_MAX 1024 + +enum { + E_SUCCESS = 0, + E_DEK_INDEX, + E_DEK_TABLE, + E_KEK_INDEX, + E_CHANNEL_INDEX, + E_DEVICE_INDEX, + E_LUN_INDEX, + E_LBA_RANGE, + E_MEMPOOL_ALLOC, + E_FLAGS, + E_ENCRYPTION_DISABLED, + E_BAD_CIPHER_MODE, + E_NO_TARGET_MAP, + E_NO_LBA_MAP, + E_NOT_FOUND, +} encrypt_error_e; + +typedef struct ag_encrypt_ioerr_s { + struct list_head *list; +} ag_encrypt_ioerr_t; + +struct agtiapi_softc *pCard; +#ifdef ENCRYPT_ENHANCE + + +ssize_t set_dek_table_entry0(struct device *dev, struct device_attribute *attr, const char *buf, size_t len); +ssize_t show_dek_table_entry0(struct device *dev, struct device_attribute *attr, char *buf); +ssize_t set_dek_table_entry1(struct device *dev, struct device_attribute *attr, const char *buf, size_t len); +ssize_t show_dek_table_entry1(struct device *dev, struct device_attribute *attr, char *buf); +ssize_t show_kek_table(struct device *dev, struct device_attribute *attr, char *buf); +ssize_t show_dek_kek_map0(struct device *dev, struct device_attribute *attr, char *buf); +ssize_t show_dek_kek_map1(struct device *dev, struct device_attribute *attr, char *buf); +ssize_t show_target_dek_map(struct device *dev, struct device_attribute *attr, char *buf); + +#endif +int agtiapi_SetupEncryption(struct agtiapi_softc *pCard); +int agtiapi_SetupEncryptionPools(struct agtiapi_softc *pCard); +void agtiapi_CleanupEncryption(struct agtiapi_softc *pCard); +void agtiapi_CleanupEncryptionPools(struct agtiapi_softc *pCard); +int agtiapi_SetupEncryptedIO(struct agtiapi_softc *pCard, ccb_t *pccb, unsigned long long block); +void agtiapi_CleanupEncryptedIO(struct agtiapi_softc *pCard, ccb_t *pccb); +void agtiapi_HandleEncryptedIOFailure(ag_device_t *pDev, ccb_t *pccb); + +#endif + diff --git a/sys/dev/pms/freebsd/driver/common/lxosapi.c b/sys/dev/pms/freebsd/driver/common/lxosapi.c new file mode 100644 index 000000000000..738eab0a9b9e --- /dev/null +++ b/sys/dev/pms/freebsd/driver/common/lxosapi.c @@ -0,0 +1,785 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +*******************************************************************************/ + + +MALLOC_DEFINE( M_PMC_OSTI, "osti_cacheable", "allocated from ostiAllocMemory as cacheable memory" ); + + +/****************************************************************************** +ostiAllocMemory() +Purpose: + TD layer calls to get dma memory +Parameters: + tiRoot_t *ptiRoot (IN) Pointer refers to the current root + void **osMemHandle (IN_OUT) Pointer To OS Mem handle to fill in + void **agVirtAddr (IN_OUT) Pointer to allocated memory address + U32 *agPhysUpper32 (IN_OUT) Pointer to Up 32 bit mem phys addr. + U32 *agPhysLower32 (IN_OUT) Pointer to low 32 bit mem phys addr. + U32 alignment (IN) Alignment requirement + U32 allocLength (IN) Required memory length + agBOOLEAN isChacheable (IN) Required memory type +Return: + tiSuccess - success + tiMemoryTooLarge - requested memory size too large + tiMemoryNotAvail - no dma memory available +Note: + for sata use. + where a cacheable allocation inherently may be swapped, the values + agPhysUpper32 and agPhysLower32 are understood to mean nothing when the + value isCacheable is set to true. these phys values must not be used by + the caller. +******************************************************************************/ +osGLOBAL U32 ostiAllocMemory( tiRoot_t *ptiRoot, + void **osMemHandle, + void **agVirtAddr, + U32 *agPhysUpper32, + U32 *agPhysLower32, + U32 alignment, + U32 allocLength, + agBOOLEAN isCacheable ) +{ + ag_card_info_t *pCardInfo = TIROOT_TO_CARDINFO( ptiRoot ); + ag_dma_addr_t *pMem; + struct agtiapi_softc *pCard; + pCard = TIROOT_TO_CARD(ptiRoot); + + AGTIAPI_PRINTK( "ostiAllocMemory: debug, cache? %d size %d alloc algn %d ### \n", + isCacheable, allocLength, alignment ); + + if( pCardInfo->topOfFreeDynamicMem == 0 ) { + AGTIAPI_PRINTK( "ostiAllocMemory: No space left, increase " + "AGTIAPI_DYNAMIC_MAX! ERROR\n" ); + return tiMemoryNotAvail; + } + + pMem = pCardInfo->freeDynamicMem[pCardInfo->topOfFreeDynamicMem - 1]; + + // where this memory has bee preallocated, be sure requirements do not + // exceed the limits of resources available + if( allocLength > 4096 ) { + AGTIAPI_PRINTK( "ostiAllocMemory: no-cache size 0x%x alloc NOT AVAILABLE\n", + allocLength ); + return tiMemoryNotAvail; + } + if( alignment > 32 ) { + AGTIAPI_PRINTK( "ostiAllocMemory: no-cache alignment 0x%x NOT AVAILABLE\n", + alignment ); + return tiMemoryNotAvail; + } + + pMem->dmaPhysAddr = pMem->nocache_busaddr; + pMem->dmaVirtAddr = pMem->nocache_mem; + pMem->memSize = allocLength; + *agVirtAddr = pMem->dmaVirtAddr; + + *agPhysUpper32 = HIGH_32_BITS( pMem->dmaPhysAddr ); + *agPhysLower32 = LOW_32_BITS( pMem->dmaPhysAddr ); + + mtx_lock(&pCard->memLock); + pCardInfo->topOfFreeDynamicMem--; + *osMemHandle = (void *)pMem; // virtAddr; + mtx_unlock(&pCard->memLock); + + return tiSuccess; +} + +/****************************************************************************** +ostiIOCTLWaitForSignal() +Purpose: + Function to wait semaphore during ioctl +Parameters: + tiRoot_t *ptiRoot (IN) Pointer to the current HBA + void **agParam1 (IN_OUT) Pointer to context to be passed + void **agParam2 (IN_OUT) Pointer to context to be passed + void **agParam (IN_OUT) Pointer to context to be passed +Return: +Note: +******************************************************************************/ +osGLOBAL void +ostiIOCTLWaitForSignal(tiRoot_t *ptiRoot, + void *agParam1, + void *agParam2, + void *agParam3) +{ + struct agtiapi_softc *pCard; + pCard = TIROOT_TO_CARD(ptiRoot); + + pCard->down_count++; + sema_wait (pCard->pIoctlSem); +} + +/* Below function has to be changed to use wait for completion */ +osGLOBAL void +ostiIOCTLWaitForComplete(tiRoot_t *ptiRoot, + void *agParam1, + void *agParam2, + void *agParam3) +{ + struct agtiapi_softc *pCard; + pCard = TIROOT_TO_CARD(ptiRoot); + + pCard->down_count++; + sema_wait (pCard->pIoctlSem); +} + + +/****************************************************************************** +ostiChipConfigReadBit32() +Purpose: + Read 32-bit value from PCI configuration register +Parameters: + tiRoot_t *ptiRoot (IN) Pointer to tiRoot structure + U32 chipConfigOffset (IN) Offset to PCI configuration register +Return: + 32 bit data +******************************************************************************/ +U32 ostiChipConfigReadBit32( tiRoot_t *ptiRoot, U32 chipConfigOffset ) +{ + device_t lDev = TIROOT_TO_PCIDEV(ptiRoot); + u_int32_t lData = 0; + + lData = pci_read_config( lDev, chipConfigOffset, 4 ); + + return (U32)lData; +} + + +/****************************************************************************** +ostiChipConfigWriteBit32() +Purpose: + Write 32-bit value to PCI configuration register +Parameters: + tiRoot_t *ptiRoot (IN) Pointer to tiRoot structure + U32 chipConfigOffset (IN) Offset to PCI configuration register + U32 chipConfigValue (IN) Value to be written +Return: none +******************************************************************************/ +void ostiChipConfigWriteBit32( tiRoot_t *ptiRoot, + U32 chipConfigOffset, + U32 chipConfigValue ) +{ + device_t lDev = TIROOT_TO_PCIDEV(ptiRoot); + pci_write_config( lDev, chipConfigOffset, chipConfigValue, 4 ); +} + +/****************************************************************************** +ostiChipReadBit32() +Purpose: + Read 32-bit value from PCI address register +Parameters: + tiRoot_t *ptiRoot (IN) Pointer to tiRoot structure + U32 chipOffset (IN) Offset to PCI configuration register +Return: + 32 bit data +******************************************************************************/ +U32 ostiChipReadBit32(tiRoot_t *ptiRoot, U32 chipOffset) +{ + U32 data; + ag_card_info_t *pCardInfo; + + pCardInfo = TIROOT_TO_CARDINFO(ptiRoot); + data = *(U32 *)(pCardInfo->pciMemVirtAddr + chipOffset); + return data; +} + +/****************************************************************************** +ostiChipWriteBit32() +Purpose: + Write 32-bit value to PCI address register +Parameters: + tiRoot_t *ptiRoot (IN) Pointer to tiRoot structure + U32 chipOffset (IN) Offset to PCI configuration register + U32 chipValue (IN) Value to be written +Return: none +******************************************************************************/ +void ostiChipWriteBit32( tiRoot_t *ptiRoot, U32 chipOffset, U32 chipValue ) +{ + ag_card_info_t *pCardInfo; + pCardInfo = TIROOT_TO_CARDINFO(ptiRoot); + *(U32 *)(pCardInfo->pciMemVirtAddr + chipOffset) = chipValue; +} + +/****************************************************************************** +ostiChipReadBit32Ext() +Purpose: + Read 32-bit value from PCI address register +Parameters: + tiRoot_t *ptiRoot (IN) Pointer to tiRoot structure + busBaseNumber PCI BAR number + U32 chipOffset (IN) Offset to PCI configuration register +Return: + 32 bit data +******************************************************************************/ +U32 ostiChipReadBit32Ext( tiRoot_t *ptiRoot, + U32 busBaseNumber, + U32 chipOffset ) +{ + U32 data; + ag_card_info_t *pCardInfo; + + pCardInfo = TIROOT_TO_CARDINFO(ptiRoot); + data = *(U32 *)((pCardInfo->pciMemVirtAddrSpc[busBaseNumber]) + chipOffset ); + return data; +} + +/****************************************************************************** +ostiChipWriteBit32Ext() +Purpose: + Write 32-bit value to PCI address register +Parameters: + tiRoot_t *ptiRoot (IN) Pointer to tiRoot structure + busBaseNumber PCI BAR number + U32 chipOffset (IN) Offset to PCI configuration register + U32 chipValue (IN) Value to be written +Return: none +******************************************************************************/ +void ostiChipWriteBit32Ext( tiRoot_t *ptiRoot, + U32 busBaseNumber, + U32 chipOffset, + U32 aData ) +{ + ag_card_info_t *pCardInfo; + pCardInfo = TIROOT_TO_CARDINFO(ptiRoot); + *(U32 *)((pCardInfo->pciMemVirtAddrSpc[busBaseNumber]) + chipOffset ) = aData; +} + +/****************************************************************************** +ostiChipReadBit8() +Purpose: + Read 8-bit value from PCI address register +Parameters: + tiRoot_t *ptiRoot (IN) Pointer to tiRoot structure + U32 chipOffset (IN) Offset to PCI configuration register +Return: + 8 bit data +******************************************************************************/ +U08 ostiChipReadBit8( tiRoot_t *ptiRoot, U32 chipOffset ) +{ + ag_card_info_t *pCardInfo; + pCardInfo = TIROOT_TO_CARDINFO(ptiRoot); + return *(U08 *)( pCardInfo->pciMemVirtAddr + chipOffset ); +} + +/****************************************************************************** +ostiChipWriteBit8() +Purpose: + Write 8-bit value to PCI address register +Parameters: + tiRoot_t *ptiRoot (IN) Pointer to tiRoot structure + U32 chipOffset (IN) Offset to PCI configuration register + U8 chipValue (IN) Value to be written +Return: none +******************************************************************************/ +void ostiChipWriteBit8( tiRoot_t *ptiRoot, U32 chipOffset, U08 chipValue ) +{ + ag_card_info_t *pCardInfo; + pCardInfo = TIROOT_TO_CARDINFO(ptiRoot); + *(U08 *)( pCardInfo->pciMemVirtAddr + chipOffset ) = chipValue; +} + + +void ostiFlashReadBlock(tiRoot_t *ptiRoot, + U32 offset, + void *bufPtr, + U32 nbytes) +{ + AGTIAPI_PRINTK( "ostiFlashReadBlock: No support for iscsi device\n" ); +} + +/****************************************************************************** +ostiFreeMemory() +Purpose: + TD layer calls to free allocated dma memory +Parameters: + tiRoot_t *ptiRoot (IN) Pointer refers to the current root + void *osMemHandle (IN) Pointer to OS mem handle to be released + u32 allocLength (IN) Aloocated memory length in byte +Return: + tiSuccess - success + tiInvalidHandle - handle is invalid +******************************************************************************/ +osGLOBAL U32 ostiFreeMemory( tiRoot_t *ptiRoot, + void *osMemHandle, + U32 allocLength ) +{ + ag_card_info_t *pCardInfo = TIROOT_TO_CARDINFO( ptiRoot ); + ag_dma_addr_t *pMem = (ag_dma_addr_t*)osMemHandle; + struct agtiapi_softc *pCard; + pCard = TIROOT_TO_CARD(ptiRoot); + + if( !osMemHandle ) { + AGTIAPI_PRINTK( "ostiFreeMemory: NULL handle ERROR\n" ); + return tiInvalidHandle; + } + + AGTIAPI_PRINTK( "ostiFreeMemory: debug messsage %p ### \n", + (void*)pMem->dmaPhysAddr ); + + // mark as unused + pMem->memSize = 0; + pMem->dmaVirtAddr = NULL; + pMem->dmaPhysAddr = 0; + + if (pCardInfo->topOfFreeDynamicMem == AGTIAPI_DYNAMIC_MAX) { + AGTIAPI_PRINTK( "ostiFreeMemory: too many free slots ERROR\n" ); + return tiInvalidHandle; + } + + mtx_lock(&pCard->memLock); + pCardInfo->freeDynamicMem[pCardInfo->topOfFreeDynamicMem++] = pMem; + mtx_unlock(&pCard->memLock); + + return tiSuccess; +} + + +/****************************************************************************** +ostiMakeParamString() +Purpose: + Utility function to simplify flow in ostiGetTransportParam(). Produces + a string handle constructed from ostiGetTransportParam() values: + key, subkey1, subkey2, subkey3, subkey4, subkey5, and valueName. +Parameters: + S08 *aKey (IN) Pointer to 1st level parameter string + S08 *aSubkey1 (IN) Pointer to 2nd level parameter string + S08 *aSubkey2 (IN) Pointer to 3rd level parameter string + S08 *aSubkey3 (IN) Pointer to 4th level parameter string + S08 *aSubkey4 (IN) Pointer to 5th level parameter string + S08 *aSubkey5 (IN) Pointer to 6th level parameter string + S08 *aValueName (IN) Pointer to name string of the value under keys + S08 *aFullKey (OUT) Pointer to returned key-value-handle buffer + U32 *apLenFullKey (OUT) String length in the key-value-handle buffer +Return: + tiSuccess - Success + tiError - Failed +Note: + If all input strings are NULL, tiError will return with zero in apLenFullKey +*****************************************************************************/ +inline static U32 ostiMakeParamString( S08 *aKey, + S08 *aSubkey1, + S08 *aSubkey2, + S08 *aSubkey3, + S08 *aSubkey4, + S08 *aSubkey5, + S08 *aValueName, + S08 *aFullKey, + U32 *apLenFullKey ) +{ + // preliminary sanity checks + if( agNULL == aKey ) { + *apLenFullKey = 0; + printf( "ostiGetTransportParam called with no key. how odd.\n" ); + return tiError; + } + if( agNULL == aValueName ) { + *apLenFullKey = 0; + printf( "ostiGetTransportParam called with no value-name. how odd.\n" ); + return tiError; + } + + strcpy( aFullKey, "DPMC_" ); // start at the beginning of the string + strcat( aFullKey, aKey ); + + int lIdx; + S08 *lStrIdx = agNULL; + for( lIdx = 1; lIdx <= 5; lIdx++ ) { + if( 1 == lIdx) lStrIdx = aSubkey1; + if( 2 == lIdx) lStrIdx = aSubkey2; + if( 3 == lIdx) lStrIdx = aSubkey3; + if( 4 == lIdx) lStrIdx = aSubkey4; + if( 5 == lIdx) lStrIdx = aSubkey5; + if( agNULL == lStrIdx ) break; // no more key information + // append key information + strcat( aFullKey, "_" ); + strcat( aFullKey, lStrIdx ); + } + + // only the value name is left to append + strcat( aFullKey, "_" ); + strcat( aFullKey, aValueName ); + + *apLenFullKey = strlen( aFullKey ); // 58 is max len seen; June 11, 2012 + // printf( "ostiMakeParamString: x%d out-str:%s\n", // debug print + // *apLenFullKey, aFullKey ); + + return tiSuccess; // ship it chief +} + + +/****************************************************************************** +ostiGetTransportParam() +Purpose: + Call back function from lower layer to get parameters. +Parameters: + tiRoot_t *ptiRoot (IN) Pointer to driver root data structure + S08 *key (IN) Pointer to 1st level parameter + S08 *subkey1 (IN) Pointer to 2nd level parameter + S08 *subkey2 (IN) Pointer to 3rd level parameter + S08 *subkey3 (IN) Pointer to 4th level parameter + S08 *subkey4 (IN) Pointer to 5th level parameter + S08 *subkey5 (IN) Pointer to 6th level parameter + S08 *valueName (IN) Pointer to name of the value under keys + S08 *buffer (OUT) Pointer to returned information buffer + U32 bufferLen (OUT) Buffer length + U32 *lenReceived (OUT) String length in the buffer +Return: + tiSuccess - Success + Other - Failed +Note: + The scheme of searching adjustable parameter tree is the following: + key + - subkey1 + - subkey2 + - subkey3 + - subkey4 + - subkey5 + - value + If no match in any case, tiError will return with zero length. + + Where there is no indication of max key and subkey length, + an upper limit guess of 200 is used. + Perhaps a prudent revision would be to add some argument(s) to be + able to manage/check these "key" string lengths. + This function does no checking of buffer being a valid pointer. +*****************************************************************************/ +U32 ostiGetTransportParam( tiRoot_t *ptiRoot, + S08 *key, + S08 *subkey1, + S08 *subkey2, + S08 *subkey3, + S08 *subkey4, + S08 *subkey5, + S08 *valueName, + S08 *buffer, + U32 bufferLen, + U32 *lenReceived ) +{ + S08 lFullKey[200]; + U32 lLenFullKey = 0; + *lenReceived = 0; + + if( bufferLen > 1 ) + strcpy( buffer, "" ); + else { + printf( "ostiGetTransportParam: buffer too small at only %d", + bufferLen ); + return tiError; // not a reasonable buffer to work with + } + ostiMakeParamString( key, subkey1, subkey2, subkey3, subkey4, subkey5, + valueName, lFullKey, &lLenFullKey ); + if( lLenFullKey ) // clean ParamString extraction + TUNABLE_STR_FETCH( lFullKey, buffer, bufferLen ); + else + return tiError; // not working out, bail now + + *lenReceived = strlen( buffer ); + + //if( *lenReceived ) // handy debug print + // printf( "ostiGetTransportParam: sz%d val:%s hdl-str:%s\n", + // *lenReceived, buffer, lFullKey ); + + return tiSuccess; // ship it chief +} + + +/****************************************************************************** +ostiIOCTLClearSignal() + +Purpose: + Function to clear or reset semaphore during ioctl +Parameters: + tiRoot_t *ptiRoot (IN) Pointer to the current HBA + void **agParam1 (IN_OUT) Pointer to context to be passed + void **agParam2 (IN_OUT) Pointer to context to be passed + void **agParam (IN_OUT) Pointer to context to be passed +Return: +Note: + TBD, need more work for card based semaphore. Also needs to + consider the calling sequence. +******************************************************************************/ +osGLOBAL void +ostiIOCTLClearSignal(tiRoot_t *ptiRoot, + void **agParam1, + void **agParam2, + void **agParam3) +{ +} + + +/****************************************************************************** +ostiIOCTLSetSignal() ### function currently stubbed out +Purpose: + Function to set semaphore during ioctl +Parameters: + tiRoot_t *ptiRoot (IN) Pointer to the current HBA + void **agParam1 (IN_OUT) Pointer to context to be passed + void **agParam2 (IN_OUT) Pointer to context to be passed + void **agParam (IN_OUT) Pointer to context to be passed +Return: +Note: +******************************************************************************/ +osGLOBAL void +ostiIOCTLSetSignal(tiRoot_t *ptiRoot, + void *agParam1, + void *agParam2, + void *agParam3) +{ + struct agtiapi_softc *pCard; + pCard = TIROOT_TO_CARD(ptiRoot); + if (pCard->down_count != pCard->up_count) + { + pCard->up_count++; + sema_post (pCard->pIoctlSem); + } +} + +osGLOBAL void +ostiIOCTLComplete(tiRoot_t *ptiRoot, + void *agParam1, + void *agParam2, + void *agParam3) +{ + struct agtiapi_softc *pCard; + pCard = TIROOT_TO_CARD(ptiRoot); + if (pCard->down_count != pCard->up_count) + { + pCard->up_count++; + sema_post (pCard->pIoctlSem); + } +} + +/****************************************************************************** +ostiPortEvent() +Purpose: + Call back function to inform OS the events of port state change. +Parameters: + tiRoot_t *ptiRoot(IN) Pointer to driver root data structure + tiPortEvent_t eventType (IN) Type of port event: + tiPortPanic + tiPortResetComplete + tiPortNameServerDown + tiPortLinkDown + tiPortLinkUp + tiPortStarted + tiPortStopped + tiPortShutdown + tiPortInitComplete + void *pParm(IN) Pointer to event specific structure +Return: + None +******************************************************************************/ +void +ostiPortEvent(tiRoot_t *ptiRoot, + tiPortEvent_t eventType, + U32 status, + void *pParm) +{ + struct agtiapi_softc *pCard; + ag_portal_data_t *pPortalData; + + AGTIAPI_PRINTK("ostiPortEvent: start eventType 0x%x\n", eventType); + + pCard = TIROOT_TO_CARD(ptiRoot); + + switch (eventType) + { + case tiPortStarted: + pCard->flags |= AGTIAPI_CB_DONE; + pPortalData = PORTAL_CONTEXT_TO_PORTALDATA(pParm); + PORTAL_STATUS(pPortalData) |= AGTIAPI_PORT_START; + AGTIAPI_PRINTK("PortStarted - portal %p, status %x\n", + pPortalData, PORTAL_STATUS(pPortalData)); + break; + case tiPortLinkDown: + pPortalData = PORTAL_CONTEXT_TO_PORTALDATA(pParm); + PORTAL_STATUS(pPortalData) &= ~AGTIAPI_PORT_LINK_UP; + AGTIAPI_PRINTK("PortLinkDown - portal %p\n", pPortalData); + break; + case tiPortLinkUp: + pPortalData = PORTAL_CONTEXT_TO_PORTALDATA(pParm); + PORTAL_STATUS(pPortalData) |= AGTIAPI_PORT_LINK_UP; + AGTIAPI_PRINTK("PortLinkUp - portal %p\n", pPortalData); +#ifdef INITIATOR_DRIVER +#ifndef HOTPLUG_SUPPORT + if (!(pCard->flags & AGTIAPI_INIT_TIME)) +#endif +// agtiapi_StartIO(pCard); +#endif + break; +case tiPortDiscoveryReady: + pCard->flags |= AGTIAPI_CB_DONE; + pPortalData = PORTAL_CONTEXT_TO_PORTALDATA(pParm); + PORTAL_STATUS(pPortalData) |= AGTIAPI_PORT_DISC_READY; + AGTIAPI_PRINTK("PortDiscoveryReady - portal %p, status 0x%x\n", + pPortalData, PORTAL_STATUS(pPortalData)); +#ifdef INITIATOR_DRIVER +#ifndef HOTPLUG_SUPPORT + if (!(pCard->flags & AGTIAPI_INIT_TIME)) +#endif + tiINIDiscoverTargets(&pCard->tiRoot, + &pPortalData->portalInfo.tiPortalContext, + FORCE_PERSISTENT_ASSIGN_MASK); +#endif + break; + case tiPortNameServerDown: + AGTIAPI_PRINTK("PortNameSeverDown\n"); + pPortalData = PORTAL_CONTEXT_TO_PORTALDATA(pParm); + PORTAL_STATUS(pPortalData) &= ~AGTIAPI_NAME_SERVER_UP; + break; + case tiPortPanic: + AGTIAPI_PRINTK("PortPanic\n"); + AGTIAPI_PRINTK( "## PortEvent\n" ); + pCard->flags |= AGTIAPI_PORT_PANIC; + break; + case tiPortResetComplete: + AGTIAPI_PRINTK("PortResetComplete\n"); + pCard->flags |= AGTIAPI_CB_DONE; + if (status == tiSuccess) + pCard->flags |= AGTIAPI_RESET_SUCCESS; + break; + case tiPortShutdown: + AGTIAPI_PRINTK("PortShutdown\n"); + pCard->flags |= AGTIAPI_CB_DONE; + pCard->flags |= AGTIAPI_PORT_SHUTDOWN; + break; + case tiPortStopped: + pCard->flags |= AGTIAPI_CB_DONE; + pPortalData = PORTAL_CONTEXT_TO_PORTALDATA(pParm); + PORTAL_STATUS(pPortalData) |= AGTIAPI_PORT_STOPPED; + AGTIAPI_PRINTK("PortStopped - portal %p\n", pPortalData); + break; + case tiEncryptOperation: + break; + case tiModePageOperation: + break; + default: + AGTIAPI_PRINTK("PortEvent - %d (Unknown)\n", eventType); + break; + } + return; +} + + +/****************************************************************************** +ostiStallThread() +Purpose: + Stall the thread (busy wait) for a number of microseconds. +Parameters: + tiRoot_t *ptiRoot (IN) Pointer to the tiRoot data structure + U32 microseconds (IN) Micro-seconds to be hold +Returns: none +******************************************************************************/ +void ostiStallThread( tiRoot_t *ptiRoot, U32 microseconds ) +{ + DELAY( microseconds ); +} + + +/****************************************************************************** +ostiTimeStamp() ### stubbed out for now +Purpose: + Time stamp +Parameters: + tiRoot_t *ptiRoot (IN) Pointer to the tiRoot data structure +Returns: + Time stamp in milisecond +******************************************************************************/ +U32 +ostiTimeStamp(tiRoot_t *ptiRoot) +{ + return 0; +} + +// meant as stubbed out 64 bit version. +U64 ostiTimeStamp64( tiRoot_t *ptiRoot ) +{ + U64 retVal; + retVal = ostiTimeStamp( ptiRoot ); + return retVal; +} + +/****************************************************************************** +ostiCacheFlush() ### stubbed out for now +ostiCacheInvalidate() +ostiCachePreFlush() + +Purpose: + Cache-coherency APIs +Parameters: + +Returns: + +Note: + These 3 functions are to support new cache coherency applications. + Currently the APIs are implemented in FC for PPC platform. The + define CACHED_DMA enable for dma_cache_sync function call. However + this define is restricted for certain version of linux, such as + Linux 2.6.x and above, and certain platform such as PPC. + + DO NOT define the CACHED_DMA if the cache coherency is not required + or the environment does not match. +******************************************************************************/ +osGLOBAL void ostiCacheFlush( + tiRoot_t *ptiRoot, + void *osMemHandle, + void *virtPtr, + bit32 length + ) +{ +} + +osGLOBAL void ostiCacheInvalidate( + tiRoot_t *ptiRoot, + void *osMemHandle, + void *virtPtr, + bit32 length + ) +{ +} + +osGLOBAL void ostiCachePreFlush( + tiRoot_t *tiRoot, + void *osMemHandle, + void *virtPtr, + bit32 length + ) +{ +} + + +/* + added for SAS/SATA + this is called by ossaInterrruptEnable +*/ +GLOBAL void ostiInterruptEnable( tiRoot_t *ptiRoot, bit32 channelNum ) +{ + // yep, really nothing. +} + +/* + this is called by ossaInterrruptDisable +*/ +GLOBAL void ostiInterruptDisable( tiRoot_t *ptiRoot, bit32 channelNum ) +{ + // yep, really nothing. +} + diff --git a/sys/dev/pms/freebsd/driver/common/lxproto.h b/sys/dev/pms/freebsd/driver/common/lxproto.h new file mode 100644 index 000000000000..3deb44b4b95f --- /dev/null +++ b/sys/dev/pms/freebsd/driver/common/lxproto.h @@ -0,0 +1,80 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +*******************************************************************************/ + +/******************************************************************************* +Module Name: + lxproto.h +Abstract: + PMC-Sierra initiator/target driver common function prototype definition +Environment: + Kernel or loadable module +Notes: + +******************************************************************************/ + +#ifndef __LX_PROTO_H__ +#define __LX_PROTO_H__ + +void agtiapi_DelayMSec(U32); +void agtiapi_DelaySec(U32); +void agtiapi_DisplayRsc(ag_card_info_t *); +agBOOLEAN agtiapi_InitResource(ag_card_info_t *); +agBOOLEAN agtiapi_typhAlloc(ag_card_info_t *); +int agtiapi_ScopeDMARes(ag_card_info_t *); +void agtiapi_ReleasePCIMem(ag_card_info_t *); + +STATIC agBOOLEAN agtiapi_MemAlloc( ag_card_info_t *thisCardInst, + void **VirtAlloc, + vm_paddr_t *pDmaAddr, + void **VirtAddr, + U32 *pPhysAddrUp, + U32 *pPhysAddrLow, + U32 MemSize, + U32 Type, + U32 Align ); + +void agtiapi_MemFree(ag_card_info_t *); +U32 agtiapi_PCIMemSize(device_t, U32, U32); +void agtiapi_Probe(void); +int agtiapi_ProbeCard(device_t, ag_card_info_t *, int); +void agtiapi_Setup(S08 *, S32 *); + +#ifdef CHAR_DEVICE +//int agtiapi_Open(struct inode *, struct file *); +//int agtiapi_Close(struct inode *, struct file *); +#endif + +#ifdef AGTIAPI_INCLUDE_PROCS +static void agtiapi_ProcDel(ag_card_info_t *pInfo); +static int agtiapi_ProcAdd(ag_card_info_t *pInfo); +#endif + +#ifdef TEST_DUMP_FCTRACE_BUFFER +#if fcEnableTraceFunctions == 1 +static void agtiapi_DumpTraceBuffer(ag_card_info_t *pInfo); +#endif +#endif + + +#endif diff --git a/sys/dev/pms/freebsd/driver/common/lxutil.c b/sys/dev/pms/freebsd/driver/common/lxutil.c new file mode 100644 index 000000000000..4cc16c150792 --- /dev/null +++ b/sys/dev/pms/freebsd/driver/common/lxutil.c @@ -0,0 +1,792 @@ +/****************************************************************************** +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + +******************************************************************************/ +/****************************************************************************** +This program is part of PMC-Sierra initiator/target device driver. +The functions here are commonly used by different type of drivers that support +PMC-Sierra storage network initiator hardware. +******************************************************************************/ + + +MALLOC_DEFINE( M_PMC_MMAL, "agtiapi_MemAlloc malloc", + "allocated from agtiapi_MemAlloc as simple malloc case" ); + + +/***************************************************************************** +agtiapi_DelayMSec() + +Purpose: + Busy wait for number of mili-seconds +Parameters: + U32 MiliSeconds (IN) Number of mili-seconds to delay +Return: +Note: +*****************************************************************************/ +STATIC void agtiapi_DelayMSec( U32 MiliSeconds ) +{ + DELAY(MiliSeconds * 1000); // DELAY takes in usecs +} + +/****************************************************************************** +agtiapi_typhAlloc() +Purpose: + Preallocation handling + Allocate DMA memory which will be divided among proper pointers in + agtiapi_MemAlloc() later +Parameters: + ag_card_info_t *thisCardInst (IN) +Return: + AGTIAPI_SUCCESS - success + AGTIAPI_FAIL - fail +******************************************************************************/ +STATIC agBOOLEAN agtiapi_typhAlloc( ag_card_info_t *thisCardInst ) +{ + struct agtiapi_softc *pmsc = thisCardInst->pCard; + int wait = 0; + + if( bus_dma_tag_create( agNULL, // parent + 32, // alignment + 0, // boundary + BUS_SPACE_MAXADDR, // lowaddr + BUS_SPACE_MAXADDR, // highaddr + NULL, // filter + NULL, // filterarg + pmsc->typhn, // maxsize (size) + 1, // number of segments + pmsc->typhn, // maxsegsize + 0, // flags + NULL, // lockfunc + NULL, // lockarg + &pmsc->typh_dmat ) ) { + printf( "agtiapi_typhAlloc: Can't create no-cache mem tag\n" ); + return AGTIAPI_FAIL; + } + + if( bus_dmamem_alloc( pmsc->typh_dmat, + &pmsc->typh_mem, + BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_NOCACHE, + &pmsc->typh_mapp ) ) { + printf( "agtiapi_typhAlloc: Cannot allocate cache mem %d\n", + pmsc->typhn ); + return AGTIAPI_FAIL; + } + + if ( bus_dmamap_load( pmsc->typh_dmat, + pmsc->typh_mapp, + pmsc->typh_mem, + pmsc->typhn, + agtiapi_MemoryCB, // try reuse of CB for same goal + &pmsc->typh_busaddr, + 0 ) || !pmsc->typh_busaddr ) { + for( ; wait < 20; wait++ ) { + if( pmsc->typh_busaddr ) break; + DELAY( 50000 ); + } + + if( ! pmsc->typh_busaddr ) { + printf( "agtiapi_typhAlloc: cache mem won't load %d\n", + pmsc->typhn ); + return AGTIAPI_FAIL; + } + } + + pmsc->typhIdx = 0; + pmsc->tyPhsIx = 0; + + return AGTIAPI_SUCCESS; +} + + +/****************************************************************************** +agtiapi_InitResource() +Purpose: + Mapping PCI memory space + Allocate and initialize per card based resource +Parameters: + ag_card_info_t *pCardInfo (IN) +Return: + AGTIAPI_SUCCESS - success + AGTIAPI_FAIL - fail +Note: +******************************************************************************/ +STATIC agBOOLEAN agtiapi_InitResource( ag_card_info_t *thisCardInst ) +{ + struct agtiapi_softc *pmsc = thisCardInst->pCard; + device_t devx = thisCardInst->pPCIDev; + + //AGTIAPI_PRINTK( "agtiapi_InitResource: begin; pointer values %p / %p \n", + // devx, thisCardInst ); + // no IO mapped card implementation, we'll implement memory mapping + + if( agtiapi_typhAlloc( thisCardInst ) == AGTIAPI_FAIL ) { + printf( "agtiapi_InitResource: failed call to agtiapi_typhAlloc \n" ); + return AGTIAPI_FAIL; + } + + AGTIAPI_PRINTK( "agtiapi_InitResource: dma alloc MemSpan %p -- %p\n", + (void*) pmsc->typh_busaddr, + (void*) ( (U32_64)pmsc->typh_busaddr + pmsc->typhn ) ); + + // logical BARs for SPC: + // bar 0 and 1 - logical BAR0 + // bar 2 and 3 - logical BAR1 + // bar4 - logical BAR2 + // bar5 - logical BAR3 + // Skiping the assignments for bar 1 and bar 3 (making bar 0, 2 64-bit): + U32 bar; + U32 lBar = 0; // logicalBar + for (bar = 0; bar < PCI_NUMBER_BARS; bar++) { + if ((bar==1) || (bar==3)) + continue; + thisCardInst->pciMemBaseRIDSpc[lBar] = PCIR_BAR(bar); + thisCardInst->pciMemBaseRscSpc[lBar] = + bus_alloc_resource_any( devx, + SYS_RES_MEMORY, + &(thisCardInst->pciMemBaseRIDSpc[lBar]), + RF_ACTIVE ); + AGTIAPI_PRINTK( "agtiapi_InitResource: bus_alloc_resource_any rtn %p \n", + thisCardInst->pciMemBaseRscSpc[lBar] ); + if ( thisCardInst->pciMemBaseRscSpc[lBar] != NULL ) { + thisCardInst->pciMemVirtAddrSpc[lBar] = + (caddr_t)rman_get_virtual( + thisCardInst->pciMemBaseRscSpc[lBar] ); + thisCardInst->pciMemBaseSpc[lBar] = + bus_get_resource_start( devx, SYS_RES_MEMORY, + thisCardInst->pciMemBaseRIDSpc[lBar]); + thisCardInst->pciMemSizeSpc[lBar] = + bus_get_resource_count( devx, SYS_RES_MEMORY, + thisCardInst->pciMemBaseRIDSpc[lBar] ); + AGTIAPI_PRINTK( "agtiapi_InitResource: PCI: bar %d, lBar %d " + "VirtAddr=%lx, len=%d\n", bar, lBar, + (long unsigned int)thisCardInst->pciMemVirtAddrSpc[lBar], + thisCardInst->pciMemSizeSpc[lBar] ); + } + else { + thisCardInst->pciMemVirtAddrSpc[lBar] = 0; + thisCardInst->pciMemBaseSpc[lBar] = 0; + thisCardInst->pciMemSizeSpc[lBar] = 0; + } + lBar++; + } + thisCardInst->pciMemVirtAddr = thisCardInst->pciMemVirtAddrSpc[0]; + thisCardInst->pciMemSize = thisCardInst->pciMemSizeSpc[0]; + thisCardInst->pciMemBase = thisCardInst->pciMemBaseSpc[0]; + + // Allocate all TI data structure required resources. + // tiLoLevelResource + U32 numVal; + ag_resource_info_t *pRscInfo; + pRscInfo = &thisCardInst->tiRscInfo; + pRscInfo->tiLoLevelResource.loLevelOption.pciFunctionNumber = + pci_get_function( devx ); + + struct timeval tv; + tv.tv_sec = 1; + tv.tv_usec = 0; + int ticksPerSec; + ticksPerSec = tvtohz( &tv ); + int uSecPerTick = 1000000/USEC_PER_TICK; + + if (pRscInfo->tiLoLevelResource.loLevelMem.count != 0) { + //AGTIAPI_INIT("agtiapi_InitResource: loLevelMem count = %d\n", + // pRscInfo->tiLoLevelResource.loLevelMem.count); + + // adjust tick value to meet Linux requirement + pRscInfo->tiLoLevelResource.loLevelOption.usecsPerTick = uSecPerTick; + AGTIAPI_PRINTK( "agtiapi_InitResource: " + "pRscInfo->tiLoLevelResource.loLevelOption.usecsPerTick" + " 0x%x\n", + pRscInfo->tiLoLevelResource.loLevelOption.usecsPerTick ); + for( numVal = 0; numVal < pRscInfo->tiLoLevelResource.loLevelMem.count; + numVal++ ) { + if( pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].totalLength == + 0 ) { + AGTIAPI_PRINTK("agtiapi_InitResource: skip ZERO %d\n", numVal); + continue; + } + + // check for 64 bit alignment + if ( pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].alignment < + AGTIAPI_64BIT_ALIGN ) { + AGTIAPI_PRINTK("agtiapi_InitResource: set ALIGN %d\n", numVal); + pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].alignment = + AGTIAPI_64BIT_ALIGN; + } + if( ((pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].type + & (BIT(0) | BIT(1))) == TI_DMA_MEM) || + ((pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].type + & (BIT(0) | BIT(1))) == TI_CACHED_DMA_MEM)) { + if ( thisCardInst->dmaIndex >= + sizeof(thisCardInst->tiDmaMem) / + sizeof(thisCardInst->tiDmaMem[0]) ) { + AGTIAPI_PRINTK( "Invalid dmaIndex %d ERROR\n", + thisCardInst->dmaIndex ); + return AGTIAPI_FAIL; + } + thisCardInst->tiDmaMem[thisCardInst->dmaIndex].type = +#ifdef CACHED_DMA + pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].type + & (BIT(0) | BIT(1)); +#else + TI_DMA_MEM; +#endif + if( agtiapi_MemAlloc( thisCardInst, + &thisCardInst->tiDmaMem[thisCardInst->dmaIndex].dmaVirtAddr, + &thisCardInst->tiDmaMem[thisCardInst->dmaIndex].dmaPhysAddr, + &pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].virtPtr, + &pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal]. + physAddrUpper, + &pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal]. + physAddrLower, + pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].totalLength, + thisCardInst->tiDmaMem[thisCardInst->dmaIndex].type, + pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].alignment) + != AGTIAPI_SUCCESS ) { + return AGTIAPI_FAIL; + } + thisCardInst->tiDmaMem[thisCardInst->dmaIndex].memSize = + pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].totalLength; + //AGTIAPI_INIT("agtiapi_InitResource: LoMem %d dmaIndex=%d DMA virt" + // " %p, phys 0x%x, length %d align %d\n", + // numVal, pCardInfo->dmaIndex, + // pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].virtPtr, + // pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].physAddrLower, + // pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].totalLength, + // pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].alignment); + thisCardInst->dmaIndex++; + } + else if ( (pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].type & + (BIT(0) | BIT(1))) == TI_CACHED_MEM) { + if (thisCardInst->cacheIndex >= + sizeof(thisCardInst->tiCachedMem) / + sizeof(thisCardInst->tiCachedMem[0])) { + AGTIAPI_PRINTK( "Invalid cacheIndex %d ERROR\n", + thisCardInst->cacheIndex ); + return AGTIAPI_FAIL; + } + if ( agtiapi_MemAlloc( thisCardInst, + &thisCardInst->tiCachedMem[thisCardInst->cacheIndex], + (vm_paddr_t *)agNULL, + &pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].virtPtr, + (U32 *)agNULL, + (U32 *)agNULL, + pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].totalLength, + TI_CACHED_MEM, + pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].alignment) + != AGTIAPI_SUCCESS ) { + return AGTIAPI_FAIL; + } + + //AGTIAPI_INIT("agtiapi_InitResource: LoMem %d cacheIndex=%d CACHED " + // "vaddr %p / %p, length %d align %d\n", + // numVal, pCardInfo->cacheIndex, + // pCardInfo->tiCachedMem[pCardInfo->cacheIndex], + // pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].virtPtr, + // pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].totalLength, + // pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].alignment); + + thisCardInst->cacheIndex++; + } + else if ( ((pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].type + & (BIT(0) | BIT(1))) == TI_DMA_MEM_CHIP)) { + // not expecting this case, print warning that should get attention + printf( "RED ALARM: we need a BAR for TI_DMA_MEM_CHIP, ignoring!" ); + } + else { + printf( "agtiapi_InitResource: Unknown required memory type %d " + "ERROR!\n", + pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].type); + return AGTIAPI_FAIL; + } + } + } + // end: TI data structure resources ... + + // begin: tiInitiatorResource + if ( pmsc->flags & AGTIAPI_INITIATOR ) { + if ( pRscInfo->tiInitiatorResource.initiatorMem.count != 0 ) { + //AGTIAPI_INIT("agtiapi_InitResource: initiatorMem count = %d\n", + // pRscInfo->tiInitiatorResource.initiatorMem.count); + numVal = + (U32)( pRscInfo->tiInitiatorResource.initiatorOption.usecsPerTick + / uSecPerTick ); + if( pRscInfo->tiInitiatorResource.initiatorOption.usecsPerTick + % uSecPerTick > 0 ) + pRscInfo->tiInitiatorResource.initiatorOption.usecsPerTick = + (numVal + 1) * uSecPerTick; + else + pRscInfo->tiInitiatorResource.initiatorOption.usecsPerTick = + numVal * uSecPerTick; + for ( numVal = 0; + numVal < pRscInfo->tiInitiatorResource.initiatorMem.count; + numVal++ ) { + // check for 64 bit alignment + if( pRscInfo->tiInitiatorResource.initiatorMem.tdCachedMem[numVal]. + alignment < AGTIAPI_64BIT_ALIGN ) { + pRscInfo->tiInitiatorResource.initiatorMem.tdCachedMem[numVal]. + alignment = AGTIAPI_64BIT_ALIGN; + } + if( thisCardInst->cacheIndex >= + sizeof( thisCardInst->tiCachedMem) / + sizeof( thisCardInst->tiCachedMem[0])) { + AGTIAPI_PRINTK( "Invalid cacheIndex %d ERROR\n", + thisCardInst->cacheIndex ); + return AGTIAPI_FAIL; + } + // initiator memory is cached, no check is needed + if( agtiapi_MemAlloc( thisCardInst, + (void *)&thisCardInst->tiCachedMem[thisCardInst->cacheIndex], + (vm_paddr_t *)agNULL, + &pRscInfo->tiInitiatorResource.initiatorMem. + tdCachedMem[numVal].virtPtr, + (U32 *)agNULL, + (U32 *)agNULL, + pRscInfo->tiInitiatorResource.initiatorMem.tdCachedMem[numVal]. + totalLength, + TI_CACHED_MEM, + pRscInfo->tiInitiatorResource.initiatorMem.tdCachedMem[numVal]. + alignment) + != AGTIAPI_SUCCESS) { + return AGTIAPI_FAIL; + } + // AGTIAPI_INIT("agtiapi_InitResource: IniMem %d cacheIndex=%d CACHED " + // "vaddr %p / %p, length %d align 0x%x\n", + // numVal, + // pCardInfo->cacheIndex, + // pCardInfo->tiCachedMem[pCardInfo->cacheIndex], + // pRscInfo->tiInitiatorResource.initiatorMem.tdCachedMem[numVal]. + // virtPtr, + //pRscInfo->tiInitiatorResource.initiatorMem.tdCachedMem[numVal]. + // totalLength, + // pRscInfo->tiInitiatorResource.initiatorMem.tdCachedMem[numVal]. + // alignment); + thisCardInst->cacheIndex++; + } + } + } + // end: tiInitiatorResource + + // begin: tiTdSharedMem + if (pRscInfo->tiSharedMem.tdSharedCachedMem1.totalLength != 0) { + // check for 64 bit alignment + if( pRscInfo->tiSharedMem.tdSharedCachedMem1.alignment < + AGTIAPI_64BIT_ALIGN ) { + pRscInfo->tiSharedMem.tdSharedCachedMem1.alignment = AGTIAPI_64BIT_ALIGN; + } + if( (pRscInfo->tiSharedMem.tdSharedCachedMem1.type & (BIT(0) | BIT(1))) + == TI_DMA_MEM ) { + if( thisCardInst->dmaIndex >= + sizeof(thisCardInst->tiDmaMem) / sizeof(thisCardInst->tiDmaMem[0]) ) { + AGTIAPI_PRINTK( "Invalid dmaIndex %d ERROR\n", thisCardInst->dmaIndex); + return AGTIAPI_FAIL; + } + if( agtiapi_MemAlloc( thisCardInst, (void *)&thisCardInst-> + tiDmaMem[thisCardInst->dmaIndex].dmaVirtAddr, + &thisCardInst->tiDmaMem[thisCardInst->dmaIndex]. + dmaPhysAddr, + &pRscInfo->tiSharedMem.tdSharedCachedMem1.virtPtr, + &pRscInfo->tiSharedMem.tdSharedCachedMem1. + physAddrUpper, + &pRscInfo->tiSharedMem.tdSharedCachedMem1. + physAddrLower, + pRscInfo->tiSharedMem.tdSharedCachedMem1. + totalLength, + TI_DMA_MEM, + pRscInfo->tiSharedMem.tdSharedCachedMem1.alignment) + != AGTIAPI_SUCCESS ) + return AGTIAPI_FAIL; + + thisCardInst->tiDmaMem[thisCardInst->dmaIndex].memSize = + pRscInfo->tiSharedMem.tdSharedCachedMem1.totalLength + + pRscInfo->tiSharedMem.tdSharedCachedMem1.alignment; + // printf( "agtiapi_InitResource: SharedMem DmaIndex=%d DMA " + // "virt %p / %p, phys 0x%x, align %d\n", + // thisCardInst->dmaIndex, + // thisCardInst->tiDmaMem[thisCardInst->dmaIndex].dmaVirtAddr, + // pRscInfo->tiSharedMem.tdSharedCachedMem1.virtPtr, + // pRscInfo->tiSharedMem.tdSharedCachedMem1.physAddrLower, + // pRscInfo->tiSharedMem.tdSharedCachedMem1.alignment); + thisCardInst->dmaIndex++; + } + else if( (pRscInfo->tiSharedMem.tdSharedCachedMem1.type & + (BIT(0) | BIT(1))) + == TI_CACHED_MEM ) { + if( thisCardInst->cacheIndex >= + sizeof(thisCardInst->tiCachedMem) / + sizeof(thisCardInst->tiCachedMem[0]) ) { + AGTIAPI_PRINTK( "Invalid cacheIndex %d ERROR\n", thisCardInst->cacheIndex); + return AGTIAPI_FAIL; + } + if( agtiapi_MemAlloc( thisCardInst, (void *)&thisCardInst-> + tiCachedMem[thisCardInst->cacheIndex], + (vm_paddr_t *)agNULL, + &pRscInfo->tiSharedMem.tdSharedCachedMem1.virtPtr, + (U32 *)agNULL, + (U32 *)agNULL, + pRscInfo-> + tiSharedMem.tdSharedCachedMem1.totalLength, + TI_CACHED_MEM, + pRscInfo->tiSharedMem.tdSharedCachedMem1.alignment) + != AGTIAPI_SUCCESS ) + return AGTIAPI_FAIL; + // printf( "agtiapi_InitResource: SharedMem cacheIndex=%d CACHED " + // "vaddr %p / %p, length %d align 0x%x\n", + // thisCardInst->cacheIndex, + // thisCardInst->tiCachedMem[thisCardInst->cacheIndex], + // pRscInfo->tiSharedMem.tdSharedCachedMem1.virtPtr, + // pRscInfo->tiSharedMem.tdSharedCachedMem1.totalLength, + // pRscInfo->tiSharedMem.tdSharedCachedMem1.alignment); + AGTIAPI_PRINTK( "agtiapi_InitResource: SharedMem cacheIndex=%d CACHED " + "vaddr %p / %p, length %d align 0x%x\n", + thisCardInst->cacheIndex, + thisCardInst->tiCachedMem[thisCardInst->cacheIndex], + pRscInfo->tiSharedMem.tdSharedCachedMem1.virtPtr, + pRscInfo->tiSharedMem.tdSharedCachedMem1.totalLength, + pRscInfo->tiSharedMem.tdSharedCachedMem1.alignment ); + thisCardInst->cacheIndex++; + } + else { + AGTIAPI_PRINTK( "agtiapi_InitResource: " + "Unknown required memory type ERROR!\n" ); + return AGTIAPI_FAIL; + } + } + // end: tiTdSharedMem + DELAY( 200000 ); // or use AGTIAPI_INIT_MDELAY(200); + return AGTIAPI_SUCCESS; +} // agtiapi_InitResource() ends here + +/****************************************************************************** +agtiapi_ScopeDMARes() +Purpose: + Determine the amount of DMA (non-cache) memory resources which will be + required for a card ( and necessarily allocated in agtiapi_InitResource() ) +Parameters: + ag_card_info_t *thisCardInst (IN) +Return: + size of DMA memory which call to agtiapi_InitResource() will consume +Note: + this funcion mirrors the flow of agtiapi_InitResource() + results are stored in agtiapi_softc fields +******************************************************************************/ +STATIC int agtiapi_ScopeDMARes( ag_card_info_t *thisCardInst ) +{ + struct agtiapi_softc *pmsc = thisCardInst->pCard; + U32 lAllMem = 0; // total memory count; typhn + U32 lTmpAlign, lTmpType, lTmpLen; + + // tiLoLevelResource + U32 numVal; + ag_resource_info_t *pRscInfo; + pRscInfo = &thisCardInst->tiRscInfo; + + if (pRscInfo->tiLoLevelResource.loLevelMem.count != 0) { + for( numVal = 0; numVal < pRscInfo->tiLoLevelResource.loLevelMem.count; + numVal++ ) { + if( pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].totalLength == + 0 ) { + printf( "agtiapi_ScopeDMARes: skip ZERO %d\n", numVal ); + continue; + } + // check for 64 bit alignment + lTmpAlign = pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].alignment; + if( lTmpAlign < AGTIAPI_64BIT_ALIGN ) { + AGTIAPI_PRINTK("agtiapi_ScopeDMARes: set ALIGN %d\n", numVal); + //pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].alignment = + lTmpAlign = AGTIAPI_64BIT_ALIGN; + } + if( ((pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].type + & (BIT(0) | BIT(1))) == TI_DMA_MEM) || + ((pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].type + & (BIT(0) | BIT(1))) == TI_CACHED_DMA_MEM)) { + //thisCardInst->tiDmaMem[thisCardInst->dmaIndex].type = + lTmpType = +#ifdef CACHED_DMA + pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].type + & (BIT(0) | BIT(1)); +#else + TI_DMA_MEM; +#endif + if( lTmpType == TI_DMA_MEM ) { + lTmpLen = + pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].totalLength; + lAllMem += lTmpLen + lTmpAlign; + } + //printf( "agtiapi_ScopeDMARes: call 1 0x%x\n", lAllMem ); + } + else if ( ( pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].type & + (BIT(0) | BIT(1)) ) == TI_CACHED_MEM ) { + // these are not the droids we're looking for + if( thisCardInst->cacheIndex >= + sizeof(thisCardInst->tiCachedMem) / + sizeof(thisCardInst->tiCachedMem[0]) ) { + AGTIAPI_PRINTK( "agtiapi_ScopeDMARes: Invalid cacheIndex %d ERROR\n", + thisCardInst->cacheIndex ); + return lAllMem; + } + } + else { + printf( "agtiapi_ScopeDMARes: Unknown required memory type %d " + "ERROR!\n", + pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].type ); + return lAllMem; + } + } + } + // end: TI data structure resources ... + + // nothing for tiInitiatorResource + + // begin: tiTdSharedMem + if (pRscInfo->tiSharedMem.tdSharedCachedMem1.totalLength != 0) { + // check for 64 bit alignment + lTmpAlign = pRscInfo->tiSharedMem.tdSharedCachedMem1.alignment; + if( lTmpAlign < AGTIAPI_64BIT_ALIGN ) { + //pRscInfo->tiSharedMem.tdSharedCachedMem1.alignment=AGTIAPI_64BIT_ALIGN; + lTmpAlign = AGTIAPI_64BIT_ALIGN; + } + if( (pRscInfo->tiSharedMem.tdSharedCachedMem1.type & (BIT(0) | BIT(1))) + == TI_DMA_MEM ) { + lTmpLen = pRscInfo->tiSharedMem.tdSharedCachedMem1.totalLength; + lAllMem += lTmpLen + lTmpAlign; + // printf( "agtiapi_ScopeDMARes: call 4D 0x%x\n", lAllMem ); + } + else if( (pRscInfo->tiSharedMem.tdSharedCachedMem1.type & + (BIT(0) | BIT(1))) + != TI_CACHED_MEM ) { + printf( "agtiapi_ScopeDMARes: Unknown required memory type ERROR!\n" ); + } + } + // end: tiTdSharedMem + + pmsc->typhn = lAllMem; + return lAllMem; + +} // agtiapi_ScopeDMARes() ends here + + +STATIC void agtiapi_ReleasePCIMem( ag_card_info_t *pCardInfo ) { + U32 bar = 0; + int tmpRid = 0; + struct resource *tmpRsc = NULL; + device_t dev; + dev = pCardInfo->pPCIDev; + + for (bar=0; bar < PCI_NUMBER_BARS; bar++) { // clean up PCI resource + tmpRid = pCardInfo->pciMemBaseRIDSpc[bar]; + tmpRsc = pCardInfo->pciMemBaseRscSpc[bar]; + if (tmpRsc != NULL) { // Release PCI resources + bus_release_resource( dev, SYS_RES_MEMORY, tmpRid, tmpRsc ); + } + } + return; +} + + +/****************************************************************************** +agtiapi_MemAlloc() +Purpose: + Handle various memory allocation requests. +Parameters: + ag_card_info_t *pCardInfo (IN) Pointer to card info structure + void **VirtAlloc (OUT) Allocated memory virtual address + dma_addr_t *pDmaAddr (OUT) Allocated dma memory physical address + void **VirtAddr (OUT) Aligned memory virtual address + U32 *pPhysAddrUp (OUT) Allocated memory physical upper 32 bits + U32 *pPhysAddrLow (OUT) Allocated memory physical lower 32 bits + U32 MemSize (IN) Allocated memory size + U32 Type (IN) Type of memory required + U32 Align (IN) Required memory alignment +Return: + AGTIAPI_SUCCESS - success + AGTIAPI_FAIL - fail +******************************************************************************/ +STATIC agBOOLEAN agtiapi_MemAlloc( ag_card_info_t *thisCardInst, + void **VirtAlloc, + vm_paddr_t *pDmaAddr, + void **VirtAddr, + U32 *pPhysAddrUp, + U32 *pPhysAddrLow, + U32 MemSize, + U32 Type, + U32 Align ) +{ + U32_64 alignOffset = 0; + if( Align ) + alignOffset = Align - 1; + +// printf( "agtiapi_MemAlloc: debug find mem TYPE, %d vs. CACHE %d, DMA %d \n", +// ( Type & ( BIT(0) | BIT(1) ) ), TI_CACHED_MEM, TI_DMA_MEM ); + + if ((Type & (BIT(0) | BIT(1))) == TI_CACHED_MEM) { + *VirtAlloc = malloc( MemSize + Align, M_PMC_MMAL, M_ZERO | M_NOWAIT ); + *VirtAddr = (void *)(((U32_64)*VirtAlloc + alignOffset) & ~alignOffset); + } + else { + struct agtiapi_softc *pmsc = thisCardInst->pCard; // get card reference + U32 residAlign = 0; + // find virt index value + *VirtAlloc = (void*)( (U64)pmsc->typh_mem + pmsc->typhIdx ); + *VirtAddr = (void *)( ( (U32_64)*VirtAlloc + alignOffset) & ~alignOffset ); + if( *VirtAddr != *VirtAlloc ) + residAlign = (U64)*VirtAddr - (U64)*VirtAlloc; // find alignment needed + pmsc->typhIdx += residAlign + MemSize; // update index + residAlign = 0; // reset variable for reuse + // find phys index val + pDmaAddr = (vm_paddr_t*)( (U64)pmsc->typh_busaddr + pmsc->tyPhsIx ); + vm_paddr_t *lPhysAligned = + (vm_paddr_t*)( ( (U64)pDmaAddr + alignOffset ) & ~alignOffset ); + if( lPhysAligned != pDmaAddr ) + residAlign = (U64)lPhysAligned - (U64)pDmaAddr; // find alignment needed + pmsc->tyPhsIx += residAlign + MemSize; // update index + *pPhysAddrUp = HIGH_32_BITS( (U64)lPhysAligned ); + *pPhysAddrLow = LOW_32_BITS( (U64)lPhysAligned ); + //printf( "agtiapi_MemAlloc: physIx 0x%x size 0x%x resid:0x%x " + // "addr:0x%p addrAligned:0x%p Align:0x%x\n", + // pmsc->tyPhsIx, MemSize, residAlign, pDmaAddr, lPhysAligned, + // Align ); + } + if ( !*VirtAlloc ) { + AGTIAPI_PRINTK( "agtiapi_MemAlloc memory allocation ERROR x%x\n", + Type & (U32)(BIT(0) | BIT(1))); + return AGTIAPI_FAIL; + } + return AGTIAPI_SUCCESS; +} + + +/****************************************************************************** +agtiapi_MemFree() + +Purpose: + Free agtiapi_MemAlloc() allocated memory +Parameters: + ag_card_info_t *pCardInfo (IN) Pointer to card info structure +Return: none +******************************************************************************/ +STATIC void agtiapi_MemFree( ag_card_info_t *pCardInfo ) +{ + U32 idx; + + // release memory vs. alloc in agtiapi_MemAlloc; cached case + for( idx = 0; idx < pCardInfo->cacheIndex; idx++ ) { + if( pCardInfo->tiCachedMem[idx] ) { + free( pCardInfo->tiCachedMem[idx], M_PMC_MMAL ); + AGTIAPI_PRINTK( "agtiapi_MemFree: TI_CACHED_MEM Mem[%d] %p\n", + idx, pCardInfo->tiCachedMem[idx] ); + } + } + + // release memory vs. alloc in agtiapi_typhAlloc; used in agtiapi_MemAlloc + struct agtiapi_softc *pmsc = pCardInfo->pCard; // get card reference + if( pmsc->typh_busaddr != 0 ) { + bus_dmamap_unload( pmsc->typh_dmat, pmsc->typh_mapp ); + } + if( pmsc->typh_mem != NULL ) { + bus_dmamem_free( pmsc->typh_dmat, pmsc->typh_mem, pmsc->typh_mapp ); + } + if( pmsc->typh_dmat != NULL ) { + bus_dma_tag_destroy( pmsc->typh_dmat ); + } +//reference values: +// pCardInfo->dmaIndex +// pCardInfo->tiDmaMem[idx].dmaVirtAddr +// pCardInfo->tiDmaMem[idx].memSize +// pCardInfo->tiDmaMem[idx].type == TI_CACHED_DMA_MEM +// pCardInfo->tiDmaMem[idx].type == TI_DMA_MEM + +/* This code is redundant. Commenting out for now to maintain a placekeeper. + Free actually takes place in agtiapi_ReleaseHBA as calls on osti_dmat. dm + // release possible lower layer dynamic memory + for( idx = 0; idx < AGTIAPI_DYNAMIC_MAX; idx++ ) { + if( pCardInfo->dynamicMem[idx].dmaVirtAddr != NULL ) { + printf( "agtiapi_MemFree: dynMem[%d] virtAddr" + " %p / %lx size: %d\n", + idx, pCardInfo->dynamicMem[idx].dmaVirtAddr, + (long unsigned int)pCardInfo->dynamicMem[idx].dmaPhysAddr, + pCardInfo->dynamicMem[idx].memSize ); + if( pCardInfo->dynamicMem[idx].dmaPhysAddr ) + some form of free call would go here ( + pCardInfo->dynamicMem[idx].dmaVirtAddr, + pCardInfo->dynamicMem[idx].memSize, ... ); + else + free case for cacheable memory would go here + } + } +*/ + return; +} + +/****************************************************************************** +agtiapi_ProbeCard() +Purpose: + sets thisCardInst->cardIdIndex to structure variant consistent with card. + ag_card_type[idx].vendorId we already determined is PCI_VENDOR_ID_PMC_SIERRA. +Parameters: + device_t dev, + ag_card_info_t *thisCardInst, + int thisCard +Return: + 0 - success + other values are not as good +Note: + This implementation is tailored to FreeBSD in alignment with the probe + functionality of the FreeBSD environment. +******************************************************************************/ +STATIC int agtiapi_ProbeCard( device_t dev, + ag_card_info_t *thisCardInst, + int thisCard ) +{ + int idx; + static U32 cardMap[4] = { 0, 0, 0, 0 }; + u_int16_t agtiapi_dev; // PCI device ID + AGTIAPI_PRINTK("agtiapi_ProbeCard: start\n"); + + if ( ! atomic_cmpset_32( &cardMap[thisCard], 0, 5 ) ) { // card already ran + AGTIAPI_PRINTK( "We'll only ID this card once -- %d\n", thisCard ); + return 2; // error return value; card already ran this function + } + else { + agtiapi_dev = pci_get_device( dev ); // get PCI device ID + for( idx = 0; idx < COUNT(ag_card_type); idx++ ) + { + if( ag_card_type[idx].deviceId == agtiapi_dev ) + { // device ID match + memset( (void *)&agCardInfoList[ thisCard ], 0, + sizeof(ag_card_info_t) ); + thisCardInst->cardIdIndex = idx; + thisCardInst->pPCIDev = dev; + thisCardInst->cardNameIndex = ag_card_type[idx].cardNameIndex; + thisCardInst->cardID = + pci_read_config( dev, ag_card_type[idx].membar, 4 ); // memAddr + AGTIAPI_PRINTK("agtiapi_ProbeCard: We've got PMC SAS, probe successful %p / %p\n", + thisCardInst->pPCIDev, thisCardInst ); + device_printf( dev, + "agtiapi PCI Probe Vendor ID : 0x%x Device ID : 0x%x\n", + pci_get_vendor(dev), agtiapi_dev ); + device_set_desc( dev, ag_card_names[ag_card_type[idx].cardNameIndex] ); + return 0; + } + } + } + return 7; +} + diff --git a/sys/dev/pms/freebsd/driver/common/osdebug.h b/sys/dev/pms/freebsd/driver/common/osdebug.h new file mode 100644 index 000000000000..bec02846ed82 --- /dev/null +++ b/sys/dev/pms/freebsd/driver/common/osdebug.h @@ -0,0 +1,122 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +*******************************************************************************/ +/*************************************************************************** + +Version Control Information: + +$RCSfile: osdebug.h,v $ +$Revision: 114125 $ + +Note: +***************************************************************************/ + +#ifndef __OSDEBUG_H__ +#define __OSDEBUG_H__ + +#ifdef AGTIAPI_KDB_ENABLE +#include +#endif + +/*************************************************************************** +OS_ASSERT : This macro is used when an internal error is detected. +***************************************************************************/ +#ifdef AGTIAPI_KDB_ENABLE +#define OS_ASSERT(expr, message) \ +do { \ + if (!(expr)) \ + { \ + printf("ASSERT: %s", message); \ + printf(" - file %s, line %d\n", __FILE__, __LINE__); \ + BUG_ON(1); \ + KDB_ENTER(); \ + } \ +} while (0) +#else +#define OS_ASSERT(expr, message) \ +do { \ + if (!(expr)) \ + { \ + printf("ASSERT: %s", message); \ + printf(" - file %s, line %d\n", __FILE__, __LINE__); \ + } \ +} while (0) +#endif + +#define AG_ERROR_MSG(mask, val, format) \ +do { \ + if (mask) \ + { \ + if (mask >= val) \ + printf format; \ + } \ + else \ + printf format; \ +} while (0) + +#ifdef TD_DEBUG_ENABLE +#define TIDEBUG_MSG(mask, val, format) \ +do { \ + if (mask) \ + { \ + if (!val) \ + printf format ; \ + else \ + if (!(mask & 0x80000000)) \ + { \ + if (mask >= val) \ + printf format ; \ + } \ + else \ + { \ + if (mask & val) \ + printf format ; \ + } \ + } \ +} while (0) + +#define TIDEBUG_MSG0(format) \ +do { \ + printf format ; \ +} while (0) +#else +#define TIDEBUG_MSG(mask, val, format) +#define TIDEBUG_MSG0(format) +#endif + +/*************************************************************************** +FC debug - The following is used for FC specific debug. +**************************************************************************/ +#ifdef AG_PROTOCOL_FC +#ifndef fcEnableTraceFunctions +#define fcEnableTraceFunctions 1 +#endif +#else +#ifndef fcEnableTraceFunctions +#define fcEnableTraceFunctions 0 +#endif + +#endif /* AG_PROTOCOL_FC */ + +#endif /* #ifndef __OSDEBUG_H__ */ + diff --git a/sys/dev/pms/freebsd/driver/common/osenv.h b/sys/dev/pms/freebsd/driver/common/osenv.h new file mode 100644 index 000000000000..16b8aa9b4e19 --- /dev/null +++ b/sys/dev/pms/freebsd/driver/common/osenv.h @@ -0,0 +1,151 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +*******************************************************************************/ +/*************************************************************************** + +Version Control Information: + +$RCSfile: osenv.h,v $ +$Revision: 114125 $ + +Note: This file defines the working enviornment of the system. All + defines listed in this file could also be compiler flags. + I am listing all the defines (even if used as a compiler flag) + so that they can be seen and documented. +***************************************************************************/ + +#ifndef __OSENV_H__ +#define __OSENV_H__ +#include + +/* +** Define the protocols to compile with. Currently, these defines are +** only for this header file and are used further down to define the protocol +** specific enviornment: +** +** #define AG_PROTOCOL_ISCSI +** #define AG_PROTOCOL_FC +*/ + +/* +** Define the application types: +** +** #define INITIATOR_DRIVER +** #define TARGET_DRIVER +*/ + +/* +** Define the endian-ness of the host CPU using one of the following: +** +** #define AG_CPU_LITTLE_ENDIAN +** #define AG_CPU_BIG_ENDIAN +*/ + +/* +** Define the host CPU word size +** +** #define AG_CPU_32_BIT +** #define AG_CPU_64_BIT +** +*/ +#ifdef CONFIG_IA64 +#define AG_CPU_64_BIT +#else +#define AG_CPU_32_BIT +#endif + +/* +** The following allow the code to use defines for word alignment and adding +** to allow for 32bit and 64bit system differences. +*/ +#ifdef AG_CPU_32_BIT +#define AG_WORD_ALIGN_ADD 3 +#define AG_WORD_ALIGN_MASK 0xfffffffc +#else +#define AG_WORD_ALIGN_ADD 7 +#define AG_WORD_ALIGN_MASK 0xfffffff8 +#endif + +/*************************************************************************** +iSCSI enviornment - The following is used for compiling the iSCSI + protocol. +**************************************************************************/ + +/* +** Define the existance of an external bus swapper using on of the +** following: +** +** #define AG_SWAPPING_BUS +** #define AG_NON_SWAPPING_BUS +** +*/ + +/* +** Define the use of cache memory for message system: +** +** #define AG_CACHED_MSG_SYSTEM +** +*/ +/* #define AG_CACHED_MSG_SYSTEM */ + +/*************************************************************************** +FC enviornment - The following is used for compiling the FC protocol. +**************************************************************************/ + +/* +** Define if an PMC-Sierra card is being used: +** +** #define CCFLAGS_PMC_SIERRA_BOARD +** +*/ + +/* +** Define if the TSDK is being used: +** +** #define FCLayer_Tsdk +** +*/ + +/* +** The following defines are not changed directly, but use either previous +** defines, or compiler directives. +** +*/ +#ifdef AG_CPU_LITTLE_ENDIAN +#define FC_DMA_LITTLE_ENDIAN +#define FC_CPU_LITTLE_ENDIAN +#define SA_DMA_LITTLE_ENDIAN +#define SA_CPU_LITTLE_ENDIAN +#endif + +#ifdef AG_CPU_BIG_ENDIAN +#define FC_DMA_BIG_ENDIAN +#define FC_CPU_BIG_ENDIAN +#define SA_DMA_BIG_ENDIAN +#define SA_CPU_BIG_ENDIAN +#endif + +/* warning: leave this next line as-is. it is used for FC-Layer testing */ +#undef FC_CHECKMACRO + +#endif /* __OSENV_H__ */ diff --git a/sys/dev/pms/freebsd/driver/common/osstring.h b/sys/dev/pms/freebsd/driver/common/osstring.h new file mode 100644 index 000000000000..5979ede255df --- /dev/null +++ b/sys/dev/pms/freebsd/driver/common/osstring.h @@ -0,0 +1,85 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +*******************************************************************************/ +/****************************************************************************** + +Note: +This program is separated from main driver source due to the common usage +of both initiator and target. +******************************************************************************* +Module Name: + osstring.h +Abstract: + FreeBSD SPCv Initiator driver module OS API definitions +Authors: + EW - Eddie Wang +Environment: + Kernel or loadable module + +Version Control Information: + $ver. 1.0.0 + +Revision History: + $Revision: 114125 $0.1.0 + $Date: 2012-01-06 17:12:27 -0800 (Fri, 06 Jan 2012) $08-27-2001 + $Modtime: 11/12/01 11:15a $11:46:00 + +Notes: + +**************************** MODIFICATION HISTORY ***************************** +NAME DATE Rev. DESCRIPTION +---- ---- ---- ----------- +EW 05-27-2002 1.0.0 Code construction started. +******************************************************************************/ + +#ifndef __OSSTRING_H__ +#define __OSSTRING_H__ +#include +#include +#include +#include +#include + +#define osti_memcmp(s1, s2, n) memcmp((void *)s1, (void *)s2, (size_t)n) +#define osti_memcpy(des, src, n) memcpy((void *)des, (void *)src, (size_t)n) +#define osti_memset(s, c, n) memset((void *)s, (int)c, (size_t)n) +#define osti_strcat(des, src) strcat((char *)des, (char *)src) +#define osti_strchr(s, n) strchr((char *)s, (int)n) +#define osti_strcmp(s1, s2) strcmp((char *)s1, (char *)s2) +#define osti_strcpy(des, src) strcpy((char *)des, (char *)src) +#define osti_strlen(s) strlen((char *)s) +#define osti_strncmp(s1, s2, n) strncmp((char *)s1, (char *)s2, (size_t)n) +#define osti_strncpy(des, src, n) strncpy((char *)des, (char *)src, (size_t)n) +#define osti_strstr(s1, s2) strstr((char *)s1, (char *)s2) + +#define osti_strtoul(nptr, endptr, base) \ + strtoul((char *)nptr, (char **)endptr, 0) + +#define osti_isxdigit(c) isxdigit(c) +#define osti_isdigit(c) isdigit(c) +#define osti_islower(c) islower(c) + +#define osMemCpy(des, src, n) memcpy((void *)des, (void *)src, (size_t)n) +#define osMemSet(s, c, n) memset((void *)s, (int)c, (size_t)n) + +#endif /* __OSSTRING_H__ */ diff --git a/sys/dev/pms/freebsd/driver/common/ostypes.h b/sys/dev/pms/freebsd/driver/common/ostypes.h new file mode 100644 index 000000000000..34b77ccf0159 --- /dev/null +++ b/sys/dev/pms/freebsd/driver/common/ostypes.h @@ -0,0 +1,170 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +*******************************************************************************/ +/****************************************************************************** + +Note: +******************************************************************************* +Module Name: + ostypes.h +Abstract: + Request by fclayer for data type define. +Authors: + EW - Yiding(Eddie) Wang +Environment: + Kernel or loadable module + +Version Control Information: + $ver. 1.0.0 + +Revision History: + $Revision: 114125 $0.1.0 + $Date: 2012-04-23 23:37:56 -0700 (Mon, 23 Apr 2012) $09-27-2001 + $Modtime: 11/12/01 11:15a $15:56:00 + +Notes: +**************************** MODIFICATION HISTORY ***************************** +NAME DATE Rev. DESCRIPTION +---- ---- ---- ----------- +EW 09-16-2002 0.1.0 Header file for most constant definitions +******************************************************************************/ + +#ifndef __OSTYPES_H__ +#define __OSTYPES_H__ + +#include +#include + + +/* +** Included for Linux 2.4, built in kernel and other possible cases. +*/ +/* +#ifdef TARGET_DRIVER +#if !defined(AGBUILD_TFE_DRIVER) && !defined(COMBO_IBE_TFE_MODULE) +#include "lxtgtdef.h" +#endif +#endif +*/ +/* +** Included for possible lower layer ignorance. +*/ +#include "osdebug.h" + +#ifdef STATIC +#undef STATIC +#endif + +#define STATIC + +#ifndef INLINE +#define INLINE inline +#endif + + +#ifndef FORCEINLINE +#define FORCEINLINE +//#define FORCEINLINE inline + +#endif +#if defined (__amd64__) +#define BITS_PER_LONG 64 +#else +#define BITS_PER_LONG 32 +#endif + + +typedef unsigned char bit8; +typedef unsigned short bit16; +typedef unsigned int bit32; +typedef char sbit8; +typedef short sbit16; +typedef int sbit32; +typedef unsigned int BOOLEAN; +typedef unsigned long long bit64; +typedef long long sbit64; + +//typedef unsigned long long bitptr; +#if 1 +#if (BITS_PER_LONG == 64) +typedef unsigned long long bitptr; +#else +typedef unsigned long bitptr; +#endif +#endif + +typedef char S08; +typedef short S16; +typedef int S32; +typedef long S32_64; +typedef long long S64; + +typedef unsigned char U08; +typedef unsigned short U16; +typedef unsigned int U32; +typedef unsigned long U32_64; +typedef unsigned long long U64; + +/* +** some really basic defines +*/ +#define GLOBAL extern +#define LOCAL static +#ifndef TRUE +#define TRUE 1 +#define FALSE 0 +#endif +#ifndef SUCCESS +#define SUCCESS 0 +#define FAILURE 1 +#endif +#ifndef NULL +#define NULL ((void*)0) +#endif + + +#define agBOOLEAN BOOLEAN +#define osGLOBAL GLOBAL +#define osLOCAL LOCAL +#define agTRUE TRUE +#define agFALSE FALSE +#define agNULL NULL + +#define AGTIAPI_UNKNOWN 2 +#define AGTIAPI_SUCCESS 1 +#define AGTIAPI_FAIL 0 + +#define AGTIAPI_DRIVER_VERSION "1.4.0.10800" + +/*************************************************************************** +**************************************************************************** +* MACROS - some basic macros +**************************************************************************** +***************************************************************************/ +#ifndef BIT +#define BIT(x) (1< +__FBSDID("$FreeBSD$"); +#include + +#define MAJOR_REVISION 1 +#define MINOR_REVISION 3 +#define BUILD_REVISION 10800 + +#include // defines used in kernel.h +#include +#include +#include +#include +#include // types used in module initialization +#include // cdevsw struct +#include // uio struct +#include +#include +#include // structs, prototypes for pci bus stuff +#include +#include +#include +#include // 1. for vtophys +#include // 2. for vtophys +#include // 3. for vtophys (yes, three) +#include // For pci_get macros +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include // +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +MALLOC_DEFINE( M_PMC_MCCB, "CCB List", "CCB List for PMCS driver" ); + +MALLOC_DEFINE( M_PMC_MSTL, "STLock malloc", + "allocated in agtiapi_attach as memory for lock use" ); +MALLOC_DEFINE( M_PMC_MDVT, "ag_device_t malloc", + "allocated in agtiapi_attach as mem for ag_device_t pDevList" ); +MALLOC_DEFINE( M_PMC_MPRT, "ag_portal_data_t malloc", + "allocated in agtiapi_attach as mem for *pPortalData" ); +MALLOC_DEFINE( M_PMC_MDEV, "tiDeviceHandle_t * malloc", + "allocated in agtiapi_GetDevHandle as local mem for **agDev" ); +MALLOC_DEFINE( M_PMC_MFLG, "lDevFlags * malloc", + "allocated in agtiapi_GetDevHandle as local mem for * flags" ); +#ifdef LINUX_PERBI_SUPPORT +MALLOC_DEFINE( M_PMC_MSLR, "ag_slr_map_t malloc", + "mem allocated in agtiapi_attach for pSLRList" ); +MALLOC_DEFINE( M_PMC_MTGT, "ag_tgt_map_t malloc", + "mem allocated in agtiapi_attach for pWWNList" ); +#endif +MALLOC_DEFINE(TEMP,"tempbuff","buffer for payload"); +MALLOC_DEFINE(TEMP2, "tempbuff", "buffer for agtiapi_getdevlist"); +STATIC U32 agtiapi_intx_mode = 0; +STATIC U08 ag_Perbi = 0; +STATIC U32 agtiapi_polling_mode = 0; +STATIC U32 ag_card_good = 0; // * total card initialized +STATIC U32 ag_option_flag = 0; // * adjustable parameter flag +STATIC U32 agtiapi_1st_time = 1; +STATIC U32 ag_timeout_secs = 10; //Made timeout equivalent to linux + +U32 gTiDebugLevel = 1; +S32 ag_encryption_enable = 0; +atomic_t outstanding_encrypted_io_count; + +#define cache_line_size() CACHE_LINE_SIZE + +#define PMCoffsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) + +#define CPU_TO_LE32(dst, src) \ + dst.lower = htole32(LOW_32_BITS(src)); \ + dst.upper = htole32(HIGH_32_BITS(src)) + +#define CMND_TO_CHANNEL( ccb ) ( ccb->ccb_h.path_id ) +#define CMND_TO_TARGET( ccb ) ( ccb->ccb_h.target_id ) +#define CMND_TO_LUN( ccb ) ( ccb->ccb_h.target_lun ) + +STATIC U08 agtiapi_AddrModes[AGTIAPI_MAX_CHANNEL_NUM + 1] = + { AGTIAPI_PERIPHERAL }; + +#ifdef LINUX_PERBI_SUPPORT +// Holding area for target-WWN mapping assignments on the boot line +static ag_mapping_t *agMappingList = NULL; // modified by agtiapi_Setup() +#endif + +// * For Debugging Purpose +#ifdef AGTIAPI_DEBUG +#define AGTIAPI_WWN(name, len) wwnprintk(name, len) +#else +#define AGTIAPI_WWN(name, len) +#endif + + +#define AGTIAPI_WWNPRINTK(name, len, format, a...) \ + AGTIAPI_PRINTK(format "name ", a); \ + AGTIAPI_WWN((unsigned char*)name, len); + +#define AGTIAPI_ERR_WWNPRINTK(name, len, format, a...) \ + printk(KERN_DEBUG format "name ", ## a); \ + wwnprintk((unsigned char*)name, len); +#define AGTIAPI_CPY_DEV_INFO(root, dev, pDev) \ + tiINIGetDeviceInfo(root, dev, &pDev->devInfo); \ + wwncpy(pDev); + +#ifdef AGTIAPI_LOCAL_LOCK + +#define AG_CARD_LOCAL_LOCK(lock) ,(lock) +#define AG_SPIN_LOCK_IRQ(lock, flags) +#define AG_SPIN_UNLOCK_IRQ(lock, flags) +#define AG_SPIN_LOCK(lock) +#define AG_SPIN_UNLOCK(lock) +#define AG_GLOBAL_ARG(arg) +#define AG_PERF_SPINLOCK(lock) +#define AG_PERF_SPINLOCK_IRQ(lock, flags) + + +#define AG_LOCAL_LOCK(lock) if (lock) \ + mtx_lock(lock) +#define AG_LOCAL_UNLOCK(lock) if (lock) \ + mtx_unlock(lock) +#define AG_LOCAL_FLAGS(_flags) unsigned long _flags = 0 +#endif + + +#define AG_GET_DONE_PCCB(pccb, pmcsc) \ + { \ + AG_LOCAL_LOCK(&pmcsc->doneLock); \ + pccb = pmcsc->ccbDoneHead; \ + if (pccb != NULL) \ + { \ + pmcsc->ccbDoneHead = NULL; \ + pmcsc->ccbDoneTail = NULL; \ + AG_LOCAL_UNLOCK(&pmcsc->doneLock); \ + agtiapi_Done(pmcsc, pccb); \ + } \ + else \ + AG_LOCAL_UNLOCK(&pmcsc->doneLock); \ + } + +#define AG_GET_DONE_SMP_PCCB(pccb, pmcsc) \ + { \ + AG_LOCAL_LOCK(&pmcsc->doneSMPLock); \ + pccb = pmcsc->smpDoneHead; \ + if (pccb != NULL) \ + { \ + pmcsc->smpDoneHead = NULL; \ + pmcsc->smpDoneTail = NULL; \ + AG_LOCAL_UNLOCK(&pmcsc->doneSMPLock); \ + agtiapi_SMPDone(pmcsc, pccb); \ + } \ + else \ + AG_LOCAL_UNLOCK(&pmcsc->doneSMPLock); \ + } + +#ifdef AGTIAPI_DUMP_IO_DEBUG +#define AG_IO_DUMPCCB(pccb) agtiapi_DumpCCB(pccb) +#else +#define AG_IO_DUMPCCB(pccb) +#endif + +#define SCHED_DELAY_JIFFIES 4 /* in seconds */ + +#ifdef HOTPLUG_SUPPORT +#define AG_HOTPLUG_LOCK_INIT(lock) mxt_init(lock) +#define AG_LIST_LOCK(lock) mtx_lock(lock) +#define AG_LIST_UNLOCK(lock) mtx_unlock(lock) +#else +#define AG_HOTPLUG_LOCK_INIT(lock) +#define AG_LIST_LOCK(lock) +#define AG_LIST_UNLOCK(lock) +#endif + +STATIC void agtiapi_CheckIOTimeout(void *data); + + + +static unsigned char cardMap[AGTIAPI_MAX_CARDS] = { 0, 0, 0, 0 }; +static ag_card_info_t agCardInfoList[ AGTIAPI_MAX_CARDS ]; // card info list +static void agtiapi_cam_action( struct cam_sim *, union ccb * ); +static void agtiapi_cam_poll( struct cam_sim * ); + +// Function prototypes +static d_open_t agtiapi_open; +static d_close_t agtiapi_close; +static d_read_t agtiapi_read; +static d_write_t agtiapi_write; +static d_ioctl_t agtiapi_CharIoctl; +static void agtiapi_async(void *callback_arg, u_int32_t code, + struct cam_path *path, void *arg); +void agtiapi_adjust_queue_depth(struct cam_path *path, bit32 QueueDepth); + +// Character device entry points +static struct cdevsw agtiapi_cdevsw = { + .d_version = D_VERSION, + .d_open = agtiapi_open, + .d_close = agtiapi_close, + .d_read = agtiapi_read, + .d_write = agtiapi_write, + .d_ioctl = agtiapi_CharIoctl, + .d_name = "pmspcv", +}; + +U32 maxTargets = 0; +U32 ag_portal_count = 0; + +// In the cdevsw routines, we find our softc by using the si_drv1 member +// of struct cdev. We set this variable to point to our softc in our +// attach routine when we create the /dev entry. + +int agtiapi_open( struct cdev *dev, int oflags, int devtype, struct thread *td ) +{ + struct agtiapi_softc *sc; + /* Look up our softc. */ + sc = dev->si_drv1; + AGTIAPI_PRINTK("agtiapi_open\n"); + AGTIAPI_PRINTK("Opened successfully. sc->my_dev %p\n", sc->my_dev); + return( 0 ); +} + +int agtiapi_close( struct cdev *dev, int fflag, int devtype, struct thread *td ) +{ + struct agtiapi_softc *sc; + // Look up our softc + sc = dev->si_drv1; + AGTIAPI_PRINTK("agtiapi_close\n"); + AGTIAPI_PRINTK("Closed. sc->my_dev %p\n", sc->my_dev); + return( 0 ); +} + +int agtiapi_read( struct cdev *dev, struct uio *uio, int ioflag ) +{ + struct agtiapi_softc *sc; + // Look up our softc + sc = dev->si_drv1; + AGTIAPI_PRINTK( "agtiapi_read\n" ); + AGTIAPI_PRINTK( "Asked to read %lu bytes. sc->my_dev %p\n", + uio->uio_resid, sc->my_dev ); + return( 0 ); +} + +int agtiapi_write( struct cdev *dev, struct uio *uio, int ioflag ) +{ + struct agtiapi_softc *sc; + // Look up our softc + sc = dev->si_drv1; + AGTIAPI_PRINTK( "agtiapi_write\n" ); + AGTIAPI_PRINTK( "Asked to write %lu bytes. sc->my_dev %p\n", + uio->uio_resid, sc->my_dev ); + return( 0 ); +} + +int agtiapi_getdevlist( struct agtiapi_softc *pCard, + tiIOCTLPayload_t *agIOCTLPayload ) +{ + tdDeviceListPayload_t *pIoctlPayload = + (tdDeviceListPayload_t *) agIOCTLPayload->FunctionSpecificArea; + tdDeviceInfoIOCTL_t *pDeviceInfo = NULL; + bit8 *pDeviceInfoOrg; + tdsaDeviceData_t *pDeviceData = NULL; + tiDeviceHandle_t **devList = NULL; + tiDeviceHandle_t **devHandleArray = NULL; + tiDeviceHandle_t *pDeviceHandle = NULL; + bit32 x, memNeeded1; + bit32 count, total; + bit32 MaxDeviceCount; + bit32 ret_val=IOCTL_CALL_INVALID_CODE; + ag_portal_data_t *pPortalData; + bit8 *pDeviceHandleList = NULL; + AGTIAPI_PRINTK( "agtiapi_getdevlist: Enter\n" ); + + pDeviceInfoOrg = pIoctlPayload -> pDeviceInfo; + MaxDeviceCount = pCard->devDiscover; + if (MaxDeviceCount > pIoctlPayload->deviceLength ) + { + AGTIAPI_PRINTK( "agtiapi_getdevlist: MaxDeviceCount: %d > Requested device length: %d\n", MaxDeviceCount, pIoctlPayload->deviceLength ); + MaxDeviceCount = pIoctlPayload->deviceLength; + ret_val = IOCTL_CALL_FAIL; + } + AGTIAPI_PRINTK( "agtiapi_getdevlist: MaxDeviceCount: %d > Requested device length: %d\n", MaxDeviceCount, pIoctlPayload->deviceLength ); + memNeeded1 = AG_ALIGNSIZE( MaxDeviceCount * sizeof(tiDeviceHandle_t *), + sizeof(void *) ); + AGTIAPI_PRINTK("agtiapi_getdevlist: portCount %d\n", pCard->portCount); + devList = malloc(memNeeded1, TEMP2, M_WAITOK); + if (devList == NULL) + { + AGTIAPI_PRINTK("agtiapi_getdevlist: failed to allocate memory\n"); + ret_val = IOCTL_CALL_FAIL; + agIOCTLPayload->Status = IOCTL_ERR_STATUS_INTERNAL_ERROR; + return ret_val; + } + osti_memset(devList, 0, memNeeded1); + pPortalData = &pCard->pPortalData[0]; + pDeviceHandleList = (bit8*)devList; + for (total = x = 0; x < pCard->portCount; x++, pPortalData++) + { + count = tiINIGetDeviceHandlesForWinIOCTL(&pCard->tiRoot, + &pPortalData->portalInfo.tiPortalContext, + ( tiDeviceHandle_t **)pDeviceHandleList ,MaxDeviceCount ); + if (count == DISCOVERY_IN_PROGRESS) + { + AGTIAPI_PRINTK( "agtiapi_getdevlist: DISCOVERY_IN_PROGRESS on " + "portal %d\n", x ); + free(devList, TEMP2); + ret_val = IOCTL_CALL_FAIL; + agIOCTLPayload->Status = IOCTL_ERR_STATUS_INTERNAL_ERROR; + return ret_val; + } + total += count; + pDeviceHandleList+= count*sizeof(tiDeviceHandle_t *); + MaxDeviceCount-= count; + } + if (total > pIoctlPayload->deviceLength) + { + total = pIoctlPayload->deviceLength; + } + // dump device information from device handle list + count = 0; + + devHandleArray = devList; + for (x = 0; x < pCard->devDiscover; x++) + { + pDeviceHandle = (tiDeviceHandle_t*)devHandleArray[x]; + if (devList[x] != agNULL) + { + pDeviceData = devList [x]->tdData; + + pDeviceInfo = (tdDeviceInfoIOCTL_t*)(pDeviceInfoOrg + sizeof(tdDeviceInfoIOCTL_t) * count); + if (pDeviceData != agNULL && pDeviceInfo != agNULL) + { + osti_memcpy( &pDeviceInfo->sasAddressHi, + pDeviceData->agDeviceInfo.sasAddressHi, + sizeof(bit32) ); + osti_memcpy( &pDeviceInfo->sasAddressLo, + pDeviceData->agDeviceInfo.sasAddressLo, + sizeof(bit32) ); +#if 0 + pDeviceInfo->sasAddressHi = + DMA_BEBIT32_TO_BIT32( pDeviceInfo->sasAddressHi ); + pDeviceInfo->sasAddressLo = + DMA_BEBIT32_TO_BIT32( pDeviceInfo->sasAddressLo ); +#endif + + pDeviceInfo->deviceType = + ( pDeviceData->agDeviceInfo.devType_S_Rate & 0x30 ) >> 4; + pDeviceInfo->linkRate = + pDeviceData->agDeviceInfo.devType_S_Rate & 0x0F; + pDeviceInfo->phyId = pDeviceData->phyID; + pDeviceInfo->ishost = pDeviceData->target_ssp_stp_smp; + pDeviceInfo->DeviceHandle= (unsigned long)pDeviceHandle; + if(pDeviceInfo->deviceType == 0x02) + { + bit8 *sasAddressHi; + bit8 *sasAddressLo; + tiIniGetDirectSataSasAddr(&pCard->tiRoot, pDeviceData->phyID, &sasAddressHi, &sasAddressLo); + pDeviceInfo->sasAddressHi = DMA_BEBIT32_TO_BIT32(*(bit32*)sasAddressHi); + pDeviceInfo->sasAddressLo = DMA_BEBIT32_TO_BIT32(*(bit32*)sasAddressLo) + pDeviceData->phyID + 16; + } + else + { + pDeviceInfo->sasAddressHi = + DMA_BEBIT32_TO_BIT32( pDeviceInfo->sasAddressHi ); + pDeviceInfo->sasAddressLo = + DMA_BEBIT32_TO_BIT32( pDeviceInfo->sasAddressLo ); + } + + AGTIAPI_PRINTK( "agtiapi_getdevlist: devicetype %x\n", + pDeviceInfo->deviceType ); + AGTIAPI_PRINTK( "agtiapi_getdevlist: linkrate %x\n", + pDeviceInfo->linkRate ); + AGTIAPI_PRINTK( "agtiapi_getdevlist: phyID %x\n", + pDeviceInfo->phyId ); + AGTIAPI_PRINTK( "agtiapi_getdevlist: addresshi %x\n", + pDeviceInfo->sasAddressHi ); + AGTIAPI_PRINTK( "agtiapi_getdevlist: addresslo %x\n", + pDeviceInfo->sasAddressHi ); + } + else + { + AGTIAPI_PRINTK( "agtiapi_getdevlist: pDeviceData %p or pDeviceInfo " + "%p is NULL %d\n", pDeviceData, pDeviceInfo, x ); + } + count++; + } + } + pIoctlPayload->realDeviceCount = count; + AGTIAPI_PRINTK( "agtiapi_getdevlist: Exit RealDeviceCount = %d\n", count ); + if (devList) + { + free(devList, TEMP2); + } + if(ret_val != IOCTL_CALL_FAIL) + { + ret_val = IOCTL_CALL_SUCCESS; + } + agIOCTLPayload->Status = IOCTL_ERR_STATUS_OK; + return ret_val; +} + +/****************************************************************************** +agtiapi_getCardInfo() + +Purpose: + This function retrives the Card information +Parameters: + +Return: + A number - error + 0 - HBA has been detected +Note: +******************************************************************************/ +int agtiapi_getCardInfo ( struct agtiapi_softc *pCard, + U32_64 size, + void *buffer ) +{ + CardInfo_t *pCardInfo; + + pCardInfo = (CardInfo_t *)buffer; + + pCardInfo->deviceId = pci_get_device(pCard->my_dev); + pCardInfo->vendorId =pci_get_vendor(pCard->my_dev) ; + memcpy( pCardInfo->pciMemBaseSpc, + pCard->pCardInfo->pciMemBaseSpc, + ((sizeof(U32_64))*PCI_NUMBER_BARS) ); + pCardInfo->deviceNum = pci_get_slot(pCard->my_dev); + pCardInfo->pciMemBase = pCard->pCardInfo->pciMemBase; + pCardInfo->pciIOAddrLow = pCard->pCardInfo->pciIOAddrLow; + pCardInfo->pciIOAddrUp = pCard->pCardInfo->pciIOAddrUp; + pCardInfo->busNum =pci_get_bus(pCard->my_dev); + return 0; +} + +void agtiapi_adjust_queue_depth(struct cam_path *path, bit32 QueueDepth) +{ + struct ccb_relsim crs; + xpt_setup_ccb(&crs.ccb_h, path, 5); + crs.ccb_h.func_code = XPT_REL_SIMQ; + crs.ccb_h.flags = CAM_DEV_QFREEZE; + crs.release_flags = RELSIM_ADJUST_OPENINGS; + crs.openings = QueueDepth; + xpt_action((union ccb *)&crs); + if(crs.ccb_h.status != CAM_REQ_CMP) { + printf("XPT_REL_SIMQ failed\n"); + } +} +static void +agtiapi_async(void *callback_arg, u_int32_t code, + struct cam_path *path, void *arg) +{ + struct agtiapi_softc *pmsc; + U32 TID; + ag_device_t *targ; + pmsc = (struct agtiapi_softc*)callback_arg; + switch (code) { + case AC_FOUND_DEVICE: + { + struct ccb_getdev *cgd; + cgd = (struct ccb_getdev *)arg; + if (cgd == NULL) { + break; + } + TID = cgd->ccb_h.target_id; + if (TID >= 0 && TID < maxTargets){ + if (pmsc != NULL){ + TID = INDEX(pmsc, TID); + targ = &pmsc->pDevList[TID]; + agtiapi_adjust_queue_depth(path, targ->qdepth); + } + } + break; + } + default: + break; + } +} +/****************************************************************************** +agtiapi_CharIoctl() + +Purpose: + This function handles the ioctl from application layer +Parameters: + +Return: + A number - error + 0 - HBA has been detected +Note: +******************************************************************************/ +static int agtiapi_CharIoctl( struct cdev *dev, + u_long cmd, + caddr_t data, + int fflag, + struct thread *td ) +{ + struct sema mx; + datatosend *load; // structure defined in lxcommon.h + tiIOCTLPayload_t *pIoctlPayload; + struct agtiapi_softc *pCard; + pCard=dev->si_drv1; + void *param1 = NULL; + void *param2 = NULL; + void *param3 = NULL; + U32 status = 0; + U32 retValue; + int err = 0; + int error = 0; + tdDeviceListPayload_t *pDeviceList = NULL; + unsigned long flags; + + switch (cmd) + { + case AGTIAPI_IOCTL: + load=(datatosend*)data; + pIoctlPayload = malloc(load->datasize,TEMP,M_WAITOK); + AGTIAPI_PRINTK( "agtiapi_CharIoctl: old load->datasize = %d\n", load->datasize ); + //Copy payload to kernel buffer, on success it returns 0 + err = copyin(load->data,pIoctlPayload,load->datasize); + if (err) + { + status = IOCTL_CALL_FAIL; + return status; + } + sema_init(&mx,0,"sem"); + pCard->pIoctlSem =&mx; + pCard->up_count = pCard->down_count = 0; + if ( pIoctlPayload->MajorFunction == IOCTL_MJ_GET_DEVICE_LIST ) + { + retValue = agtiapi_getdevlist(pCard, pIoctlPayload); + if (retValue == 0) + { + pIoctlPayload->Status = IOCTL_CALL_SUCCESS; + status = IOCTL_CALL_SUCCESS; + } + else + { + pIoctlPayload->Status = IOCTL_CALL_FAIL; + status = IOCTL_CALL_FAIL; + } + //update new device length + pDeviceList = (tdDeviceListPayload_t*)pIoctlPayload->FunctionSpecificArea; + load->datasize =load->datasize - sizeof(tdDeviceInfoIOCTL_t) * (pDeviceList->deviceLength - pDeviceList->realDeviceCount); + AGTIAPI_PRINTK( "agtiapi_CharIoctl: new load->datasize = %d\n", load->datasize ); + + } + else if (pIoctlPayload->MajorFunction == IOCTL_MN_GET_CARD_INFO) + { + retValue = agtiapi_getCardInfo( pCard, + pIoctlPayload->Length, + (pIoctlPayload->FunctionSpecificArea) ); + if (retValue == 0) + { + pIoctlPayload->Status = IOCTL_CALL_SUCCESS; + status = IOCTL_CALL_SUCCESS; + } + else + { + pIoctlPayload->Status = IOCTL_CALL_FAIL; + status = IOCTL_CALL_FAIL; + } + } + else if ( pIoctlPayload->MajorFunction == IOCTL_MJ_CHECK_DPMC_EVENT ) + { + if ( pCard->flags & AGTIAPI_PORT_PANIC ) + { + strcpy ( pIoctlPayload->FunctionSpecificArea, "DPMC LEAN\n" ); + } + else + { + strcpy ( pIoctlPayload->FunctionSpecificArea, "do not dpmc lean\n" ); + } + pIoctlPayload->Status = IOCTL_CALL_SUCCESS; + status = IOCTL_CALL_SUCCESS; + } + else if (pIoctlPayload->MajorFunction == IOCTL_MJ_CHECK_FATAL_ERROR ) + { + AGTIAPI_PRINTK("agtiapi_CharIoctl: IOCTL_MJ_CHECK_FATAL_ERROR call received for card %d\n", pCard->cardNo); + //read port status to see if there is a fatal event + if(pCard->flags & AGTIAPI_PORT_PANIC) + { + printf("agtiapi_CharIoctl: Port Panic Status For Card %d is True\n",pCard->cardNo); + pIoctlPayload->Status = IOCTL_MJ_FATAL_ERR_CHK_SEND_TRUE; + } + else + { + AGTIAPI_PRINTK("agtiapi_CharIoctl: Port Panic Status For Card %d is False\n",pCard->cardNo); + pIoctlPayload->Status = IOCTL_MJ_FATAL_ERR_CHK_SEND_FALSE; + } + status = IOCTL_CALL_SUCCESS; + } + else if (pIoctlPayload->MajorFunction == IOCTL_MJ_FATAL_ERROR_DUMP_COMPLETE) + { + AGTIAPI_PRINTK("agtiapi_CharIoctl: IOCTL_MJ_FATAL_ERROR_DUMP_COMPLETE call received for card %d\n", pCard->cardNo); + //set flags bit status to be a soft reset + pCard->flags |= AGTIAPI_SOFT_RESET; + //trigger soft reset for the card + retValue = agtiapi_ResetCard (pCard, &flags); + + if(retValue == AGTIAPI_SUCCESS) + { + //clear port panic status + pCard->flags &= ~AGTIAPI_PORT_PANIC; + pIoctlPayload->Status = IOCTL_MJ_FATAL_ERROR_SOFT_RESET_TRIG; + status = IOCTL_CALL_SUCCESS; + } + else + { + pIoctlPayload->Status = IOCTL_CALL_FAIL; + status = IOCTL_CALL_FAIL; + } + } + else + { + status = tiCOMMgntIOCTL( &pCard->tiRoot, + pIoctlPayload, + pCard, + param2, + param3 ); + if (status == IOCTL_CALL_PENDING) + { + ostiIOCTLWaitForSignal(&pCard->tiRoot,NULL, NULL, NULL); + status = IOCTL_CALL_SUCCESS; + } + } + pCard->pIoctlSem = NULL; + err = 0; + + //copy kernel buffer to userland buffer + err=copyout(pIoctlPayload,load->data,load->datasize); + if (err) + { + status = IOCTL_CALL_FAIL; + return status; + } + free(pIoctlPayload,TEMP); + pIoctlPayload=NULL; + break; + default: + error = ENOTTY; + break; + } + return(status); +} + +/****************************************************************************** +agtiapi_probe() + +Purpose: + This function initialize and registere all detected HBAs. + The first function being called in driver after agtiapi_probe() +Parameters: + device_t dev (IN) - device pointer +Return: + A number - error + 0 - HBA has been detected +Note: +******************************************************************************/ +static int agtiapi_probe( device_t dev ) +{ + int retVal; + + if ( pci_get_vendor(dev) == PCI_VENDOR_ID_PMC_SIERRA || + pci_get_vendor(dev) == PCI_VENDOR_ID_HIALEAH ) + { + int thisCard = device_get_unit( dev ); +// AGTIAPI_PRINTK("agtiapi_probe: thisCard %d\n", thisCard); + if( thisCard >= AGTIAPI_MAX_CARDS) + { + device_printf( dev, "Too many PMC-Sierra cards detected ERROR!\n" ); + return (ENXIO); // maybe change to different return value? + } + ag_card_info_t *thisCardInst = &agCardInfoList[ thisCard ]; + retVal = agtiapi_ProbeCard( dev, thisCardInst, thisCard ); + if ( retVal ) { + // error on probe + if( retVal == 2 ) return 0; // another thread ran probe on this card + device_printf( dev, + "agtiapi_probe: PCI DEVICE NOT SUPPORTED by this driver!!" + "Vendor ID : 0x%x Device ID : 0x%x\n", + pci_get_vendor(dev), pci_get_device( dev ) ); + return (ENXIO); // maybe change to different return value? + } + else { + // AGTIAPI_PRINTK( "agtiapi_ProbeCard: returned with pointer values " + // "%p / %p\n", + // thisCardInst->pPCIDev, thisCardInst ); + cardMap[thisCard] = 11; // record this card is present + return( BUS_PROBE_DEFAULT ); // successful probe + } + } + return (ENXIO); +} + + +/****************************************************************************** +agtiapi_attach() + +Purpose: + This function initialize and registere all detected HBAs. + The first function being called in driver after agtiapi_probe() +Parameters: + device_t dev (IN) - device pointer +Return: + A number - error + 0 - HBA has been detected +Note: +******************************************************************************/ +static int agtiapi_attach( device_t devx ) +{ + // keeping get_unit call to once + int thisCard = device_get_unit( devx ); + struct agtiapi_softc *pmsc; + ag_card_info_t *thisCardInst = &agCardInfoList[ thisCard ]; + ag_resource_info_t *pRscInfo; + int idx; + int lenRecv; + char buffer [256], *pLastUsedChar; + union ccb *ccb; + int bus, tid, lun; + struct ccb_setasync csa; + + AGTIAPI_PRINTK("agtiapi_attach: start dev %p thisCard %d\n", devx, thisCard); + // AGTIAPI_PRINTK( "agtiapi_attach: entry pointer values A %p / %p\n", + // thisCardInst->pPCIDev, thisCardInst ); + AGTIAPI_PRINTK( "agtiapi_attach: deviceID: 0x%x\n", pci_get_devid( devx ) ); + + TUNABLE_INT_FETCH( "DPMC_TIMEOUT_SECS", &ag_timeout_secs ); + TUNABLE_INT_FETCH( "DPMC_TIDEBUG_LEVEL", &gTiDebugLevel ); + // printf( "agtiapi_attach: debugLevel %d, timeout %d\n", + // gTiDebugLevel, ag_timeout_secs ); + if ( ag_timeout_secs < 1 ) + { + ag_timeout_secs = 1; // set minimum timeout value of 1 second + } + ag_timeout_secs = (ag_timeout_secs * 1000); // convert to millisecond notation + + // Look up our softc and initialize its fields. + pmsc = device_get_softc( devx ); + pmsc->my_dev = devx; + + /* Get NumberOfPortals */ + if ((ostiGetTransportParam( + &pmsc->tiRoot, + "Global", + "CardDefault", + agNULL, + agNULL, + agNULL, + agNULL, + "NumberOfPortals", + buffer, + 255, + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + ag_portal_count = osti_strtoul (buffer, &pLastUsedChar, 0); + } + else + { + ag_portal_count = osti_strtoul (buffer, &pLastUsedChar, 10); + } + if (ag_portal_count > AGTIAPI_MAX_PORTALS) + ag_portal_count = AGTIAPI_MAX_PORTALS; + } + else + { + ag_portal_count = AGTIAPI_MAX_PORTALS; + } + AGTIAPI_PRINTK( "agtiapi_attach: ag_portal_count=%d\n", ag_portal_count ); + // initialize hostdata structure + pmsc->flags |= AGTIAPI_INIT_TIME | AGTIAPI_SCSI_REGISTERED | + AGTIAPI_INITIATOR; + pmsc->cardNo = thisCard; + pmsc->ccbTotal = 0; + pmsc->portCount = ag_portal_count; + pmsc->pCardInfo = thisCardInst; + pmsc->tiRoot.osData = pmsc; + pmsc->pCardInfo->pCard = (void *)pmsc; + pmsc->VidDid = ( pci_get_vendor(devx) << 16 ) | pci_get_device( devx ); + pmsc->SimQFrozen = agFALSE; + pmsc->devq_flag = agFALSE; + pRscInfo = &thisCardInst->tiRscInfo; + + osti_memset(buffer, 0, 256); + lenRecv = 0; + + /* Get MaxTargets */ + if ((ostiGetTransportParam( + &pmsc->tiRoot, + "Global", + "InitiatorParms", + agNULL, + agNULL, + agNULL, + agNULL, + "MaxTargets", + buffer, + sizeof(buffer), + &lenRecv + ) == tiSuccess) && (lenRecv != 0)) + { + if (osti_strncmp(buffer, "0x", 2) == 0) + { + maxTargets = osti_strtoul (buffer, &pLastUsedChar, 0); + AGTIAPI_PRINTK( "agtiapi_attach: maxTargets = osti_strtoul 0 \n" ); + } + else + { + maxTargets = osti_strtoul (buffer, &pLastUsedChar, 10); + AGTIAPI_PRINTK( "agtiapi_attach: maxTargets = osti_strtoul 10\n" ); + } + } + else + + { + if(Is_ADP8H(pmsc)) + maxTargets = AGTIAPI_MAX_DEVICE_8H; + else if(Is_ADP7H(pmsc)) + maxTargets = AGTIAPI_MAX_DEVICE_7H; + else + maxTargets = AGTIAPI_MAX_DEVICE; + } + + if (maxTargets > AGTIAPI_HW_LIMIT_DEVICE) + { + AGTIAPI_PRINTK( "agtiapi_attach: maxTargets: %d > AGTIAPI_HW_LIMIT_DEVICE: %d\n", maxTargets, AGTIAPI_HW_LIMIT_DEVICE ); + AGTIAPI_PRINTK( "agtiapi_attach: change maxTargets = AGTIAPI_HW_LIMIT_DEVICE\n" ); + maxTargets = AGTIAPI_HW_LIMIT_DEVICE; + } + pmsc->devDiscover = maxTargets ; + + #ifdef HIALEAH_ENCRYPTION + ag_encryption_enable = 1; + if(ag_encryption_enable && pci_get_device(pmsc->pCardInfo->pPCIDev) == + PCI_DEVICE_ID_HIALEAH_HBA_SPCVE) + { + pmsc->encrypt = 1; + pRscInfo->tiLoLevelResource.loLevelOption.encryption = agTRUE; + printf("agtiapi_attach: Encryption Enabled\n" ); + } +#endif + // ## for now, skip calls to ostiGetTransportParam(...) + // ## for now, skip references to DIF & EDC + + // Create a /dev entry for this device. The kernel will assign us + // a major number automatically. We use the unit number of this + // device as the minor number and name the character device + // "agtiapi". + pmsc->my_cdev = make_dev( &agtiapi_cdevsw, thisCard, UID_ROOT, GID_WHEEL, + 0600, "spcv%u", thisCard ); + pmsc->my_cdev->si_drv1 = pmsc; + + mtx_init( &thisCardInst->pmIOLock, "pmc SAS I/O lock", + NULL, MTX_DEF|MTX_RECURSE ); + + struct cam_devq *devq; + + /* set the maximum number of pending IOs */ + devq = cam_simq_alloc( AGTIAPI_MAX_CAM_Q_DEPTH ); + if (devq == NULL) + { + AGTIAPI_PRINTK("agtiapi_attach: cam_simq_alloc is NULL\n" ); + return( EIO ); + } + + struct cam_sim *lsim; + lsim = cam_sim_alloc( agtiapi_cam_action, + agtiapi_cam_poll, + "pmspcbsd", + pmsc, + thisCard, + &thisCardInst->pmIOLock, + 1, // queued per target + AGTIAPI_MAX_CAM_Q_DEPTH, // max tag depth + devq ); + if ( lsim == NULL ) { + cam_simq_free( devq ); + AGTIAPI_PRINTK("agtiapi_attach: cam_sim_alloc is NULL\n" ); + return( EIO ); + } + + pmsc->dev_scan = agFALSE; + //one cam sim per scsi bus + mtx_lock( &thisCardInst->pmIOLock ); + if ( xpt_bus_register( lsim, devx, 0 ) != CAM_SUCCESS ) + { // bus 0 + cam_sim_free( lsim, TRUE ); + mtx_unlock( &thisCardInst->pmIOLock ); + AGTIAPI_PRINTK("agtiapi_attach: xpt_bus_register fails\n" ); + return( EIO ); + } + + pmsc->sim = lsim; + bus = cam_sim_path(pmsc->sim); + tid = CAM_TARGET_WILDCARD; + lun = CAM_LUN_WILDCARD; + ccb = xpt_alloc_ccb_nowait(); + if (ccb == agNULL) + { + mtx_unlock( &thisCardInst->pmIOLock ); + cam_sim_free( lsim, TRUE ); + cam_simq_free( devq ); + return ( EIO ); + } + if (xpt_create_path(&ccb->ccb_h.path, agNULL, bus, tid, + CAM_LUN_WILDCARD) != CAM_REQ_CMP) + { + mtx_unlock( &thisCardInst->pmIOLock ); + cam_sim_free( lsim, TRUE ); + cam_simq_free( devq ); + xpt_free_ccb(ccb); + return( EIO ); + } + pmsc->path = ccb->ccb_h.path; + xpt_setup_ccb(&csa.ccb_h, pmsc->path, 5); + csa.ccb_h.func_code = XPT_SASYNC_CB; + csa.event_enable = AC_FOUND_DEVICE; + csa.callback = agtiapi_async; + csa.callback_arg = pmsc; + xpt_action((union ccb *)&csa); + if (csa.ccb_h.status != CAM_REQ_CMP) { + AGTIAPI_PRINTK("agtiapi_attach: Unable to register AC_FOUND_DEVICE\n" ); + } + lsim->devq = devq; + mtx_unlock( &thisCardInst->pmIOLock ); + + + + + // get TD and lower layer memory requirements + tiCOMGetResource( &pmsc->tiRoot, + &pRscInfo->tiLoLevelResource, + &pRscInfo->tiInitiatorResource, + NULL, + &pRscInfo->tiSharedMem ); + + agtiapi_ScopeDMARes( thisCardInst ); + AGTIAPI_PRINTK( "agtiapi_attach: size from the call agtiapi_ScopeDMARes" + " 0x%x \n", pmsc->typhn ); + + // initialize card information and get resource ready + if( agtiapi_InitResource( thisCardInst ) == AGTIAPI_FAIL ) { + AGTIAPI_PRINTK( "agtiapi_attach: Card %d initialize resource ERROR\n", + thisCard ); + } + + // begin: allocate and initialize card portal info resource + ag_portal_data_t *pPortalData; + if (pmsc->portCount == 0) + { + pmsc->pPortalData = NULL; + } + else + { + pmsc->pPortalData = (ag_portal_data_t *) + malloc( sizeof(ag_portal_data_t) * pmsc->portCount, + M_PMC_MPRT, M_ZERO | M_WAITOK ); + if (pmsc->pPortalData == NULL) + { + AGTIAPI_PRINTK( "agtiapi_attach: Portal memory allocation ERROR\n" ); + } + } + + pPortalData = pmsc->pPortalData; + for( idx = 0; idx < pmsc->portCount; idx++ ) { + pPortalData->pCard = pmsc; + pPortalData->portalInfo.portID = idx; + pPortalData->portalInfo.tiPortalContext.osData = (void *)pPortalData; + pPortalData++; + } + // end: allocate and initialize card portal info resource + + // begin: enable msix + + // setup msix + // map to interrupt handler + int error = 0; + int mesgs = MAX_MSIX_NUM_VECTOR; + int i, cnt; + + void (*intrHandler[MAX_MSIX_NUM_ISR])(void *arg) = + { + agtiapi_IntrHandler0, + agtiapi_IntrHandler1, + agtiapi_IntrHandler2, + agtiapi_IntrHandler3, + agtiapi_IntrHandler4, + agtiapi_IntrHandler5, + agtiapi_IntrHandler6, + agtiapi_IntrHandler7, + agtiapi_IntrHandler8, + agtiapi_IntrHandler9, + agtiapi_IntrHandler10, + agtiapi_IntrHandler11, + agtiapi_IntrHandler12, + agtiapi_IntrHandler13, + agtiapi_IntrHandler14, + agtiapi_IntrHandler15 + + }; + + cnt = pci_msix_count(devx); + AGTIAPI_PRINTK("supported MSIX %d\n", cnt); //this should be 64 + mesgs = MIN(mesgs, cnt); + error = pci_alloc_msix(devx, &mesgs); + if (error != 0) { + printf( "pci_alloc_msix error %d\n", error ); + AGTIAPI_PRINTK("error %d\n", error); + return( EIO ); + } + + for(i=0; i < mesgs; i++) { + pmsc->rscID[i] = i + 1; + pmsc->irq[i] = bus_alloc_resource_any( devx, + SYS_RES_IRQ, + &pmsc->rscID[i], + RF_ACTIVE ); + if( pmsc->irq[i] == NULL ) { + printf( "RES_IRQ went terribly bad at %d\n", i ); + return( EIO ); + } + + if ( (error = bus_setup_intr( devx, pmsc->irq[i], + INTR_TYPE_CAM | INTR_MPSAFE, + NULL, + intrHandler[i], + pmsc, + &pmsc->intrcookie[i] ) + ) != 0 ) { + device_printf( devx, "Failed to register handler" ); + return( EIO ); + } + } + pmsc->flags |= AGTIAPI_IRQ_REQUESTED; + pmsc->pCardInfo->maxInterruptVectors = MAX_MSIX_NUM_VECTOR; + // end: enable msix + + int ret = 0; + ret = agtiapi_InitCardSW(pmsc); + if (ret == AGTIAPI_FAIL || ret == AGTIAPI_UNKNOWN) + { + AGTIAPI_PRINTK( "agtiapi_attach: agtiapi_InitCardSW failure %d\n", + ret ); + return( EIO ); + } + + pmsc->ccbFreeList = NULL; + pmsc->ccbChainList = NULL; + pmsc->ccbAllocList = NULL; + + pmsc->flags |= ( AGTIAPI_INSTALLED ); + + ret = agtiapi_alloc_requests( pmsc ); + if( ret != 0 ) { + AGTIAPI_PRINTK( "agtiapi_attach: agtiapi_alloc_requests failure %d\n", + ret ); + return( EIO ); + } + + ret = agtiapi_alloc_ostimem( pmsc ); + if (ret != AGTIAPI_SUCCESS) + { + AGTIAPI_PRINTK( "agtiapi_attach: agtiapi_alloc_ostimem failure %d\n", + ret ); + return( EIO ); + } + + ret = agtiapi_InitCardHW( pmsc ); + if (ret != 0) + { + AGTIAPI_PRINTK( "agtiapi_attach: agtiapi_InitCardHW failure %d\n", + ret ); + return( EIO ); + } + +#ifdef HIALEAH_ENCRYPTION + if(pmsc->encrypt) + { + if((agtiapi_SetupEncryption(pmsc)) < 0) + AGTIAPI_PRINTK("SetupEncryption returned less than 0\n"); + } +#endif + + pmsc->flags &= ~AGTIAPI_INIT_TIME; + return( 0 ); +} + +/****************************************************************************** +agtiapi_InitCardSW() + +Purpose: + Host Bus Adapter Initialization +Parameters: + struct agtiapi_softc *pmsc (IN) Pointer to the HBA data structure +Return: + AGTIAPI_SUCCESS - success + AGTIAPI_FAIL - fail +Note: + TBD, need chip register information +******************************************************************************/ +STATIC agBOOLEAN agtiapi_InitCardSW( struct agtiapi_softc *pmsc ) +{ + ag_card_info_t *thisCardInst = pmsc->pCardInfo; + ag_resource_info_t *pRscInfo = &thisCardInst->tiRscInfo; + int initSWIdx; + + // begin: agtiapi_InitCardSW() + // now init some essential locks n agtiapi_InitCardSW + mtx_init( &pmsc->sendLock, "local q send lock", NULL, MTX_DEF ); + mtx_init( &pmsc->doneLock, "local q done lock", NULL, MTX_DEF ); + mtx_init( &pmsc->sendSMPLock, "local q send lock", NULL, MTX_DEF ); + mtx_init( &pmsc->doneSMPLock, "local q done lock", NULL, MTX_DEF ); + mtx_init( &pmsc->ccbLock, "ccb list lock", NULL, MTX_DEF ); + mtx_init( &pmsc->devListLock, "hotP devListLock", NULL, MTX_DEF ); + mtx_init( &pmsc->memLock, "dynamic memory lock", NULL, MTX_DEF ); + mtx_init( &pmsc->freezeLock, "sim freeze lock", NULL, MTX_DEF | MTX_RECURSE); + + // initialize lower layer resources + //## if (pCard->flags & AGTIAPI_INIT_TIME) { +#ifdef HIALEAH_ENCRYPTION + /* Enable encryption if chip supports it */ + if (pci_get_device(pmsc->pCardInfo->pPCIDev) == + PCI_DEVICE_ID_HIALEAH_HBA_SPCVE) + pmsc->encrypt = 1; + + if (pmsc->encrypt) + pRscInfo->tiLoLevelResource.loLevelOption.encryption = agTRUE; +#endif + pmsc->flags &= ~(AGTIAPI_PORT_INITIALIZED | AGTIAPI_SYS_INTR_ON); + + + // For now, up to 16 MSIX vectors are supported + thisCardInst->tiRscInfo.tiLoLevelResource.loLevelOption. + maxInterruptVectors = pmsc->pCardInfo->maxInterruptVectors; + AGTIAPI_PRINTK( "agtiapi_InitCardSW: maxInterruptVectors set to %d", + pmsc->pCardInfo->maxInterruptVectors ); + thisCardInst->tiRscInfo.tiLoLevelResource.loLevelOption.max_MSI_InterruptVectors = 0; + thisCardInst->tiRscInfo.tiLoLevelResource.loLevelOption.flag = 0; + pRscInfo->tiLoLevelResource.loLevelOption.maxNumOSLocks = 0; + + AGTIAPI_PRINTK( "agtiapi_InitCardSW: tiCOMInit root %p, dev %p, pmsc %p\n", + &pmsc->tiRoot, pmsc->my_dev, pmsc ); + if( tiCOMInit( &pmsc->tiRoot, + &thisCardInst->tiRscInfo.tiLoLevelResource, + &thisCardInst->tiRscInfo.tiInitiatorResource, + NULL, + &thisCardInst->tiRscInfo.tiSharedMem ) != tiSuccess ) { + AGTIAPI_PRINTK( "agtiapi_InitCardSW: tiCOMInit ERROR\n" ); + return AGTIAPI_FAIL; + } + int maxLocks; + maxLocks = pRscInfo->tiLoLevelResource.loLevelOption.numOfQueuesPerPort; + pmsc->STLock = malloc( ( maxLocks * sizeof(struct mtx) ), M_PMC_MSTL, + M_ZERO | M_WAITOK ); + + for( initSWIdx = 0; initSWIdx < maxLocks; initSWIdx++ ) + { + // init all indexes + mtx_init( &pmsc->STLock[initSWIdx], "LL & TD lock", NULL, MTX_DEF ); + } + + if( tiCOMPortInit( &pmsc->tiRoot, agFALSE ) != tiSuccess ) { + printf( "agtiapi_InitCardSW: tiCOMPortInit ERROR -- AGTIAPI_FAIL\n" ); + return AGTIAPI_FAIL; + } + AGTIAPI_PRINTK( "agtiapi_InitCardSW: tiCOMPortInit" + " root %p, dev %p, pmsc %p\n", + &pmsc->tiRoot, pmsc->my_dev, pmsc ); + + pmsc->flags |= AGTIAPI_PORT_INITIALIZED; + pmsc->freezeSim = agFALSE; + +#ifdef HIALEAH_ENCRYPTION + atomic_set(&outstanding_encrypted_io_count, 0); + /*fix below*/ + /*if(pmsc->encrypt && (pmsc->flags & AGTIAPI_INIT_TIME)) + if((agtiapi_SetupEncryptionPools(pmsc)) != 0) + printf("SetupEncryptionPools failed\n"); */ +#endif + return AGTIAPI_SUCCESS; + // end: agtiapi_InitCardSW() +} + +/****************************************************************************** +agtiapi_InitCardHW() + +Purpose: + Host Bus Adapter Initialization +Parameters: + struct agtiapi_softc *pmsc (IN) Pointer to the HBA data structure +Return: + AGTIAPI_SUCCESS - success + AGTIAPI_FAIL - fail +Note: + TBD, need chip register information +******************************************************************************/ +STATIC agBOOLEAN agtiapi_InitCardHW( struct agtiapi_softc *pmsc ) +{ + U32 numVal; + U32 count; + U32 loop; + // begin: agtiapi_InitCardHW() + + ag_portal_info_t *pPortalInfo = NULL; + ag_portal_data_t *pPortalData; + + // ISR is registered, enable chip interrupt. + tiCOMSystemInterruptsActive( &pmsc->tiRoot, agTRUE ); + pmsc->flags |= AGTIAPI_SYS_INTR_ON; + + numVal = sizeof(ag_device_t) * pmsc->devDiscover; + pmsc->pDevList = + (ag_device_t *)malloc( numVal, M_PMC_MDVT, M_ZERO | M_WAITOK ); + if( !pmsc->pDevList ) { + AGTIAPI_PRINTK( "agtiapi_InitCardHW: kmalloc %d DevList ERROR\n", numVal ); + panic( "agtiapi_InitCardHW\n" ); + return AGTIAPI_FAIL; + } + +#ifdef LINUX_PERBI_SUPPORT + numVal = sizeof(ag_slr_map_t) * pmsc->devDiscover; + pmsc->pSLRList = + (ag_slr_map_t *)malloc( numVal, M_PMC_MSLR, M_ZERO | M_WAITOK ); + if( !pmsc->pSLRList ) { + AGTIAPI_PRINTK( "agtiapi_InitCardHW: kmalloc %d SLRList ERROR\n", numVal ); + panic( "agtiapi_InitCardHW SLRL\n" ); + return AGTIAPI_FAIL; + } + + numVal = sizeof(ag_tgt_map_t) * pmsc->devDiscover; + pmsc->pWWNList = + (ag_tgt_map_t *)malloc( numVal, M_PMC_MTGT, M_ZERO | M_WAITOK ); + if( !pmsc->pWWNList ) { + AGTIAPI_PRINTK( "agtiapi_InitCardHW: kmalloc %d WWNList ERROR\n", numVal ); + panic( "agtiapi_InitCardHW WWNL\n" ); + return AGTIAPI_FAIL; + } + + // Get the WWN_to_target_ID mappings from the + // holding area which contains the input of the + // system configuration file. + if( ag_Perbi ) + agtiapi_GetWWNMappings( pmsc, agMappingList ); + else { + agtiapi_GetWWNMappings( pmsc, 0 ); + if( agMappingList ) + printf( "agtiapi_InitCardHW: WWN PERBI disabled WARN\n" ); + } +#endif + + //agtiapi_DelaySec(5); + DELAY( 500000 ); + + pmsc->tgtCount = 0; + + pmsc->flags &= ~AGTIAPI_CB_DONE; + pPortalData = pmsc->pPortalData; + + //start port + + for (count = 0; count < pmsc->portCount; count++) + { + AG_SPIN_LOCK_IRQ( agtiapi_host_lock, flags ); + + pPortalInfo = &pPortalData->portalInfo; + pPortalInfo->portStatus &= ~( AGTIAPI_PORT_START | + AGTIAPI_PORT_DISC_READY | + AGTIAPI_DISC_DONE | + AGTIAPI_DISC_COMPLETE ); + + for (loop = 0; loop < AGTIAPI_LOOP_MAX; loop++) + { + AGTIAPI_PRINTK( "tiCOMPortStart entry data %p / %d / %p\n", + &pmsc->tiRoot, + pPortalInfo->portID, + &pPortalInfo->tiPortalContext ); + + if( tiCOMPortStart( &pmsc->tiRoot, + pPortalInfo->portID, + &pPortalInfo->tiPortalContext, + 0 ) + != tiSuccess ) { + AG_SPIN_UNLOCK_IRQ( agtiapi_host_lock, flags ); + agtiapi_DelayMSec( AGTIAPI_EXTRA_DELAY ); + AG_SPIN_LOCK_IRQ(agtiapi_host_lock, flags); + AGTIAPI_PRINTK( "tiCOMPortStart failed -- no loop, portalData %p\n", + pPortalData ); + } + else { + AGTIAPI_PRINTK( "tiCOMPortStart success no loop, portalData %p\n", + pPortalData ); + break; + } + } // end of for loop + /* release lock */ + AG_SPIN_UNLOCK_IRQ( agtiapi_host_lock, flags ); + + if( loop >= AGTIAPI_LOOP_MAX ) { + return AGTIAPI_FAIL; + } + tiCOMGetPortInfo( &pmsc->tiRoot, + &pPortalInfo->tiPortalContext, + &pPortalInfo->tiPortInfo ); + pPortalData++; + } + + /* discover target device */ +#ifndef HOTPLUG_SUPPORT + agtiapi_DiscoverTgt( pCard ); +#endif + + + pmsc->flags |= AGTIAPI_INSTALLED; + + if( pmsc->flags & AGTIAPI_INIT_TIME ) { + agtiapi_TITimer( (void *)pmsc ); + pmsc->flags |= AGTIAPI_TIMER_ON; + } + + return 0; +} + + + +/****************************************************************************** +agtiapi_IntrHandlerx_() + +Purpose: + Interrupt service routine. +Parameters: + void arg (IN) Pointer to the HBA data structure + bit32 idx (IN) Vector index +******************************************************************************/ +void agtiapi_IntrHandlerx_( void *arg, int index ) +{ + + struct agtiapi_softc *pCard; + int rv; + + pCard = (struct agtiapi_softc *)arg; + +#ifndef AGTIAPI_DPC + ccb_t *pccb; +#endif + + AG_LOCAL_LOCK(&(pCard->pCardInfo->pmIOLock)); + AG_PERF_SPINLOCK(agtiapi_host_lock); + if (pCard->flags & AGTIAPI_SHUT_DOWN) + goto ext; + + rv = tiCOMInterruptHandler(&pCard->tiRoot, index); + if (rv == agFALSE) + { + /* not our irq */ + AG_SPIN_UNLOCK(agtiapi_host_lock); + AG_LOCAL_UNLOCK(&(pCard->pCardInfo->pmIOLock)); + return; + } + + +#ifdef AGTIAPI_DPC + tasklet_hi_schedule(&pCard->tasklet_dpc[idx]); +#else + /* consume all completed entries, 100 is random number to be big enough */ + tiCOMDelayedInterruptHandler(&pCard->tiRoot, index, 100, tiInterruptContext); + AG_GET_DONE_PCCB(pccb, pCard); + AG_GET_DONE_SMP_PCCB(pccb, pCard); +#endif + +ext: + AG_SPIN_UNLOCK(agtiapi_host_lock); + AG_LOCAL_UNLOCK(&(pCard->pCardInfo->pmIOLock)); + return; + +} + +/****************************************************************************** +agtiapi_IntrHandler0() +Purpose: Interrupt service routine for interrupt vector index 0. +Parameters: void arg (IN) Pointer to the HBA data structure +******************************************************************************/ +void agtiapi_IntrHandler0( void *arg ) +{ + agtiapi_IntrHandlerx_( arg, 0 ); + return; +} + +/****************************************************************************** +agtiapi_IntrHandler1() +Purpose: Interrupt service routine for interrupt vector index 1. +Parameters: void arg (IN) Pointer to the HBA data structure +******************************************************************************/ +void agtiapi_IntrHandler1( void *arg ) +{ + agtiapi_IntrHandlerx_( arg, 1 ); + return; +} + +/****************************************************************************** +agtiapi_IntrHandler2() +Purpose: Interrupt service routine for interrupt vector index 2. +Parameters: void arg (IN) Pointer to the HBA data structure +******************************************************************************/ +void agtiapi_IntrHandler2( void *arg ) +{ + agtiapi_IntrHandlerx_( arg, 2 ); + return; +} + +/****************************************************************************** +agtiapi_IntrHandler3() +Purpose: Interrupt service routine for interrupt vector index 3. +Parameters: void arg (IN) Pointer to the HBA data structure +******************************************************************************/ +void agtiapi_IntrHandler3( void *arg ) +{ + agtiapi_IntrHandlerx_( arg, 3 ); + return; +} + +/****************************************************************************** +agtiapi_IntrHandler4() +Purpose: Interrupt service routine for interrupt vector index 4. +Parameters: void arg (IN) Pointer to the HBA data structure +******************************************************************************/ +void agtiapi_IntrHandler4( void *arg ) +{ + agtiapi_IntrHandlerx_( arg, 4 ); + return; +} + +/****************************************************************************** +agtiapi_IntrHandler5() +Purpose: Interrupt service routine for interrupt vector index 5. +Parameters: void arg (IN) Pointer to the HBA data structure +******************************************************************************/ +void agtiapi_IntrHandler5( void *arg ) +{ + agtiapi_IntrHandlerx_( arg, 5 ); + return; +} + +/****************************************************************************** +agtiapi_IntrHandler6() +Purpose: Interrupt service routine for interrupt vector index 6. +Parameters: void arg (IN) Pointer to the HBA data structure +******************************************************************************/ +void agtiapi_IntrHandler6( void *arg ) +{ + agtiapi_IntrHandlerx_( arg, 6 ); + return; +} + +/****************************************************************************** +agtiapi_IntrHandler7() +Purpose: Interrupt service routine for interrupt vector index 7. +Parameters: void arg (IN) Pointer to the HBA data structure +******************************************************************************/ +void agtiapi_IntrHandler7( void *arg ) +{ + agtiapi_IntrHandlerx_( arg, 7 ); + return; +} + +/****************************************************************************** +agtiapi_IntrHandler8() +Purpose: Interrupt service routine for interrupt vector index 8. +Parameters: void arg (IN) Pointer to the HBA data structure +******************************************************************************/ +void agtiapi_IntrHandler8( void *arg ) +{ + agtiapi_IntrHandlerx_( arg, 8 ); + return; +} + +/****************************************************************************** +agtiapi_IntrHandler9() +Purpose: Interrupt service routine for interrupt vector index 9. +Parameters: void arg (IN) Pointer to the HBA data structure +******************************************************************************/ +void agtiapi_IntrHandler9( void *arg ) +{ + agtiapi_IntrHandlerx_( arg, 9 ); + return; +} + +/****************************************************************************** +agtiapi_IntrHandler10() +Purpose: Interrupt service routine for interrupt vector index 10. +Parameters: void arg (IN) Pointer to the HBA data structure +******************************************************************************/ +void agtiapi_IntrHandler10( void *arg ) +{ + agtiapi_IntrHandlerx_( arg, 10 ); + return; +} + +/****************************************************************************** +agtiapi_IntrHandler11() +Purpose: Interrupt service routine for interrupt vector index 11. +Parameters: void arg (IN) Pointer to the HBA data structure +******************************************************************************/ +void agtiapi_IntrHandler11( void *arg ) +{ + agtiapi_IntrHandlerx_( arg, 11 ); + return; +} + +/****************************************************************************** +agtiapi_IntrHandler12() +Purpose: Interrupt service routine for interrupt vector index 12. +Parameters: void arg (IN) Pointer to the HBA data structure +******************************************************************************/ +void agtiapi_IntrHandler12( void *arg ) +{ + agtiapi_IntrHandlerx_( arg, 12 ); + return; +} + +/****************************************************************************** +agtiapi_IntrHandler13() +Purpose: Interrupt service routine for interrupt vector index 13. +Parameters: void arg (IN) Pointer to the HBA data structure +******************************************************************************/ +void agtiapi_IntrHandler13( void *arg ) +{ + agtiapi_IntrHandlerx_( arg, 13 ); + return; +} + +/****************************************************************************** +agtiapi_IntrHandler14() +Purpose: Interrupt service routine for interrupt vector index 14. +Parameters: void arg (IN) Pointer to the HBA data structure +******************************************************************************/ +void agtiapi_IntrHandler14( void *arg ) +{ + agtiapi_IntrHandlerx_( arg, 14 ); + return; +} + +/****************************************************************************** +agtiapi_IntrHandler15() +Purpose: Interrupt service routine for interrupt vector index 15. +Parameters: void arg (IN) Pointer to the HBA data structure +******************************************************************************/ +void agtiapi_IntrHandler15( void *arg ) +{ + agtiapi_IntrHandlerx_( arg, 15 ); + return; +} + +static void agtiapi_SglMemoryCB( void *arg, + bus_dma_segment_t *dm_segs, + int nseg, + int error ) +{ + bus_addr_t *addr; + AGTIAPI_PRINTK("agtiapi_SglMemoryCB: start\n"); + if (error != 0) + { + AGTIAPI_PRINTK("agtiapi_SglMemoryCB: error %d\n", error); + panic("agtiapi_SglMemoryCB: error %d\n", error); + return; + } + addr = arg; + *addr = dm_segs[0].ds_addr; + return; +} + +static void agtiapi_MemoryCB( void *arg, + bus_dma_segment_t *dm_segs, + int nseg, + int error ) +{ + bus_addr_t *addr; + AGTIAPI_PRINTK("agtiapi_MemoryCB: start\n"); + if (error != 0) + { + AGTIAPI_PRINTK("agtiapi_MemoryCB: error %d\n", error); + panic("agtiapi_MemoryCB: error %d\n", error); + return; + } + addr = arg; + *addr = dm_segs[0].ds_addr; + return; +} + +/****************************************************************************** +agtiapi_alloc_requests() + +Purpose: + Allocates resources such as dma tag and timer +Parameters: + struct agtiapi_softc *pmsc (IN) Pointer to the HBA data structure +Return: + AGTIAPI_SUCCESS - success + AGTIAPI_FAIL - fail +Note: +******************************************************************************/ +int agtiapi_alloc_requests( struct agtiapi_softc *pmcsc ) +{ + + int rsize, nsegs; + U32 next_tick; + + nsegs = AGTIAPI_NSEGS; + rsize = AGTIAPI_MAX_DMA_SEGS; // 128 + AGTIAPI_PRINTK( "agtiapi_alloc_requests: MAXPHYS 0x%x PAGE_SIZE 0x%x \n", + MAXPHYS, PAGE_SIZE ); + AGTIAPI_PRINTK( "agtiapi_alloc_requests: nsegs %d rsize %d \n", + nsegs, rsize ); // 32, 128 + // This is for csio->data_ptr + if( bus_dma_tag_create( agNULL, // parent + 1, // alignment + 0, // boundary + BUS_SPACE_MAXADDR, // lowaddr + BUS_SPACE_MAXADDR, // highaddr + NULL, // filter + NULL, // filterarg + BUS_SPACE_MAXSIZE_32BIT, // maxsize + nsegs, // nsegments + BUS_SPACE_MAXSIZE_32BIT, // maxsegsize + BUS_DMA_ALLOCNOW, // flags + busdma_lock_mutex, // lockfunc + &pmcsc->pCardInfo->pmIOLock, // lockarg + &pmcsc->buffer_dmat ) ) { + AGTIAPI_PRINTK( "agtiapi_alloc_requests: Cannot alloc request DMA tag\n" ); + return( ENOMEM ); + } + + // This is for tiSgl_t of pccb in agtiapi_PrepCCBs() + rsize = + (sizeof(tiSgl_t) * AGTIAPI_NSEGS) * + AGTIAPI_CCB_PER_DEVICE * maxTargets; + AGTIAPI_PRINTK( "agtiapi_alloc_requests: rsize %d \n", rsize ); // 32, 128 + if( bus_dma_tag_create( agNULL, // parent + 32, // alignment + 0, // boundary + BUS_SPACE_MAXADDR_32BIT, // lowaddr + BUS_SPACE_MAXADDR, // highaddr + NULL, // filter + NULL, // filterarg + rsize, // maxsize + 1, // nsegments + rsize, // maxsegsize + BUS_DMA_ALLOCNOW, // flags + NULL, // lockfunc + NULL, // lockarg + &pmcsc->tisgl_dmat ) ) { + AGTIAPI_PRINTK( "agtiapi_alloc_requests: Cannot alloc request DMA tag\n" ); + return( ENOMEM ); + } + + if( bus_dmamem_alloc( pmcsc->tisgl_dmat, + (void **)&pmcsc->tisgl_mem, + BUS_DMA_NOWAIT, + &pmcsc->tisgl_map ) ) { + AGTIAPI_PRINTK( "agtiapi_alloc_requests: Cannot allocate SGL memory\n" ); + return( ENOMEM ); + } + + bzero( pmcsc->tisgl_mem, rsize ); + bus_dmamap_load( pmcsc->tisgl_dmat, + pmcsc->tisgl_map, + pmcsc->tisgl_mem, + rsize, + agtiapi_SglMemoryCB, + &pmcsc->tisgl_busaddr, + BUS_DMA_NOWAIT /* 0 */ ); + + mtx_init( &pmcsc->OS_timer_lock, "OS timer lock", NULL, MTX_DEF ); + mtx_init( &pmcsc->IO_timer_lock, "IO timer lock", NULL, MTX_DEF ); + mtx_init( &pmcsc->devRmTimerLock, "targ rm timer lock", NULL, MTX_DEF ); + callout_init_mtx( &pmcsc->OS_timer, &pmcsc->OS_timer_lock, 0 ); + callout_init_mtx( &pmcsc->IO_timer, &pmcsc->IO_timer_lock, 0 ); + callout_init_mtx( &pmcsc->devRmTimer, + &pmcsc->devRmTimerLock, 0); + + next_tick = pmcsc->pCardInfo->tiRscInfo.tiLoLevelResource. + loLevelOption.usecsPerTick / USEC_PER_TICK; + AGTIAPI_PRINTK( "agtiapi_alloc_requests: before callout_reset, " + "next_tick 0x%x\n", next_tick ); + callout_reset( &pmcsc->OS_timer, next_tick, agtiapi_TITimer, pmcsc ); + return 0; +} + +/****************************************************************************** +agtiapi_alloc_ostimem() + +Purpose: + Allocates memory used later in ostiAllocMemory +Parameters: + struct agtiapi_softc *pmcsc (IN) Pointer to the HBA data structure +Return: + AGTIAPI_SUCCESS - success + AGTIAPI_FAIL - fail +Note: + This is a pre-allocation for ostiAllocMemory() "non-cacheable" function calls +******************************************************************************/ +int agtiapi_alloc_ostimem( struct agtiapi_softc *pmcsc ) { + int rsize, nomsize; + + nomsize = 4096; + rsize = AGTIAPI_DYNAMIC_MAX * nomsize; // 8M + AGTIAPI_PRINTK("agtiapi_alloc_ostimem: rsize %d \n", rsize); + + if( bus_dma_tag_create( agNULL, // parent + 32, // alignment + 0, // boundary + BUS_SPACE_MAXADDR, // lowaddr + BUS_SPACE_MAXADDR, // highaddr + NULL, // filter + NULL, // filterarg + rsize, // maxsize (size) + 1, // number of segments + rsize, // maxsegsize + 0, // flags + NULL, // lockfunc + NULL, // lockarg + &pmcsc->osti_dmat ) ) { + AGTIAPI_PRINTK( "agtiapi_alloc_ostimem: Can't create no-cache mem tag\n" ); + return AGTIAPI_FAIL; + } + + + if( bus_dmamem_alloc( pmcsc->osti_dmat, + &pmcsc->osti_mem, + BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_NOCACHE, + &pmcsc->osti_mapp ) ) { + AGTIAPI_PRINTK( "agtiapi_alloc_ostimem: Cannot allocate cache mem %d\n", + rsize ); + return AGTIAPI_FAIL; + } + + + bus_dmamap_load( pmcsc->osti_dmat, + pmcsc->osti_mapp, + pmcsc->osti_mem, + rsize, + agtiapi_MemoryCB, // try reuse of CB for same goal + &pmcsc->osti_busaddr, + BUS_DMA_NOWAIT ); + + // populate all the ag_dma_addr_t osti_busaddr/mem fields with addresses for + // handy reference when driver is in motion + int idx; + ag_card_info_t *pCardInfo = pmcsc->pCardInfo; + ag_dma_addr_t *pMem; + + for( idx = 0; idx < AGTIAPI_DYNAMIC_MAX; idx++ ) { + pMem = &pCardInfo->dynamicMem[idx]; + pMem->nocache_busaddr = pmcsc->osti_busaddr + ( idx * nomsize ); + pMem->nocache_mem = (void*)((U64)pmcsc->osti_mem + ( idx * nomsize )); + pCardInfo->freeDynamicMem[idx] = &pCardInfo->dynamicMem[idx]; + } + + pCardInfo->topOfFreeDynamicMem = AGTIAPI_DYNAMIC_MAX; + + return AGTIAPI_SUCCESS; +} + + +/****************************************************************************** +agtiapi_cam_action() + +Purpose: + Parses CAM frames and triggers a corresponding action +Parameters: + struct cam_sim *sim (IN) Pointer to SIM data structure + union ccb * ccb (IN) Pointer to CAM ccb data structure +Return: +Note: +******************************************************************************/ +static void agtiapi_cam_action( struct cam_sim *sim, union ccb * ccb ) +{ + struct agtiapi_softc *pmcsc; + tiDeviceHandle_t *pDevHandle = NULL; // acts as flag as well + tiDeviceInfo_t devInfo; + int pathID, targetID, lunID; + int lRetVal; + U32 TID; + U32 speed = 150000; + + pmcsc = cam_sim_softc( sim ); + AGTIAPI_IO( "agtiapi_cam_action: start pmcs %p\n", pmcsc ); + + if (pmcsc == agNULL) + { + AGTIAPI_PRINTK( "agtiapi_cam_action: start pmcs is NULL\n" ); + return; + } + mtx_assert( &(pmcsc->pCardInfo->pmIOLock), MA_OWNED ); + + AGTIAPI_IO( "agtiapi_cam_action: cardNO %d func_code 0x%x\n", pmcsc->cardNo, ccb->ccb_h.func_code ); + + pathID = xpt_path_path_id( ccb->ccb_h.path ); + targetID = xpt_path_target_id( ccb->ccb_h.path ); + lunID = xpt_path_lun_id( ccb->ccb_h.path ); + + AGTIAPI_IO( "agtiapi_cam_action: P 0x%x T 0x%x L 0x%x\n", + pathID, targetID, lunID ); + + switch (ccb->ccb_h.func_code) + { + case XPT_PATH_INQ: + { + struct ccb_pathinq *cpi; + + /* See architecure book p180*/ + cpi = &ccb->cpi; + cpi->version_num = 1; + cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE | PI_WIDE_16; + cpi->target_sprt = 0; + cpi->hba_misc = PIM_NOBUSRESET | PIM_SEQSCAN; + cpi->hba_eng_cnt = 0; + cpi->max_target = maxTargets - 1; + cpi->max_lun = AGTIAPI_MAX_LUN; + cpi->maxio = 1024 *1024; /* Max supported I/O size, in bytes. */ + cpi->initiator_id = 255; + strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); + strncpy(cpi->hba_vid, "PMC", HBA_IDLEN); + strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); + cpi->unit_number = cam_sim_unit(sim); + cpi->bus_id = cam_sim_bus(sim); + // rate is set when XPT_GET_TRAN_SETTINGS is processed + cpi->base_transfer_speed = 150000; + cpi->transport = XPORT_SAS; + cpi->transport_version = 0; + cpi->protocol = PROTO_SCSI; + cpi->protocol_version = SCSI_REV_SPC3; + cpi->ccb_h.status = CAM_REQ_CMP; + break; + } + case XPT_GET_TRAN_SETTINGS: + { + struct ccb_trans_settings *cts; + struct ccb_trans_settings_sas *sas; + struct ccb_trans_settings_scsi *scsi; + + if ( pmcsc->flags & AGTIAPI_SHUT_DOWN ) + { + return; + } + + cts = &ccb->cts; + sas = &ccb->cts.xport_specific.sas; + scsi = &cts->proto_specific.scsi; + + cts->protocol = PROTO_SCSI; + cts->protocol_version = SCSI_REV_SPC3; + cts->transport = XPORT_SAS; + cts->transport_version = 0; + + sas->valid = CTS_SAS_VALID_SPEED; + + /* this sets the "MB/s transfers" */ + if (pmcsc != NULL && targetID >= 0 && targetID < maxTargets) + { + if (pmcsc->pWWNList != NULL) + { + TID = INDEX(pmcsc, targetID); + if (TID < maxTargets) + { + pDevHandle = pmcsc->pDevList[TID].pDevHandle; + } + } + } + if (pDevHandle) + { + tiINIGetDeviceInfo( &pmcsc->tiRoot, pDevHandle, &devInfo ); + switch (devInfo.info.devType_S_Rate & 0xF) + { + case 0x8: speed = 150000; + break; + case 0x9: speed = 300000; + break; + case 0xA: speed = 600000; + break; + case 0xB: speed = 1200000; + break; + default: speed = 150000; + break; + } + } + sas->bitrate = speed; + scsi->valid = CTS_SCSI_VALID_TQ; + scsi->flags = CTS_SCSI_FLAGS_TAG_ENB; + ccb->ccb_h.status = CAM_REQ_CMP; + break; + } + case XPT_RESET_BUS: + { + lRetVal = agtiapi_eh_HostReset( pmcsc, ccb ); // usually works first time + if ( SUCCESS == lRetVal ) + { + AGTIAPI_PRINTK( "agtiapi_cam_action: bus reset success.\n" ); + } + else + { + AGTIAPI_PRINTK( "agtiapi_cam_action: bus reset failed.\n" ); + } + ccb->ccb_h.status = CAM_REQ_CMP; + break; + } + case XPT_RESET_DEV: + { + ccb->ccb_h.status = CAM_REQ_CMP; + break; + } + case XPT_ABORT: + { + ccb->ccb_h.status = CAM_REQ_CMP; + break; + } +#if __FreeBSD_version >= 900026 + case XPT_SMP_IO: + { + agtiapi_QueueSMP( pmcsc, ccb ); + return; + } +#endif /* __FreeBSD_version >= 900026 */ + case XPT_SCSI_IO: + { + if(pmcsc->dev_scan == agFALSE) + { + ccb->ccb_h.status = CAM_SEL_TIMEOUT; + break; + } + if (pmcsc->flags & AGTIAPI_SHUT_DOWN) + { + AGTIAPI_PRINTK( "agtiapi_cam_action: shutdown, XPT_SCSI_IO 0x%x\n", + XPT_SCSI_IO ); + ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; + break; + } + else + { + AGTIAPI_IO( "agtiapi_cam_action: Zero XPT_SCSI_IO 0x%x, doing IOs\n", + XPT_SCSI_IO ); + agtiapi_QueueCmnd_( pmcsc, ccb ); + return; + } + } + + case XPT_CALC_GEOMETRY: + { + cam_calc_geometry(&ccb->ccg, 1); + ccb->ccb_h.status = CAM_REQ_CMP; + break; + } + default: + { + /* + XPT_SET_TRAN_SETTINGS + */ + AGTIAPI_IO( "agtiapi_cam_action: default function code 0x%x\n", + ccb->ccb_h.func_code ); + ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; + break; + } + } /* switch */ + xpt_done(ccb); +} + + +/****************************************************************************** +agtiapi_GetCCB() + +Purpose: + Get a ccb from free list or allocate a new one +Parameters: + struct agtiapi_softc *pmcsc (IN) Pointer to HBA structure +Return: + Pointer to a ccb structure, or NULL if not available +Note: +******************************************************************************/ +STATIC pccb_t agtiapi_GetCCB( struct agtiapi_softc *pmcsc ) +{ + pccb_t pccb; + + AGTIAPI_IO( "agtiapi_GetCCB: start\n" ); + + AG_LOCAL_LOCK( &pmcsc->ccbLock ); + + /* get the ccb from the head of the free list */ + if ((pccb = (pccb_t)pmcsc->ccbFreeList) != NULL) + { + pmcsc->ccbFreeList = (caddr_t *)pccb->pccbNext; + pccb->pccbNext = NULL; + pccb->flags = ACTIVE; + pccb->startTime = 0; + pmcsc->activeCCB++; + AGTIAPI_IO( "agtiapi_GetCCB: re-allocated ccb %p\n", pccb ); + } + else + { + AGTIAPI_PRINTK( "agtiapi_GetCCB: kmalloc ERROR - no ccb allocated\n" ); + } + + AG_LOCAL_UNLOCK( &pmcsc->ccbLock ); + return pccb; +} + +/****************************************************************************** +agtiapi_QueueCmnd_() + +Purpose: + Calls for sending CCB and excuting on HBA. +Parameters: + struct agtiapi_softc *pmsc (IN) Pointer to the HBA data structure + union ccb * ccb (IN) Pointer to CAM ccb data structure +Return: + 0 - Command is pending to execute + 1 - Command returned without further process +Note: +******************************************************************************/ +int agtiapi_QueueCmnd_(struct agtiapi_softc *pmcsc, union ccb * ccb) +{ + struct ccb_scsiio *csio = &ccb->csio; + pccb_t pccb = agNULL; // call dequeue + int status = tiSuccess; + U32 Channel = CMND_TO_CHANNEL(ccb); + U32 TID = CMND_TO_TARGET(ccb); + U32 LUN = CMND_TO_LUN(ccb); + + AGTIAPI_IO( "agtiapi_QueueCmnd_: start\n" ); + + /* no support for CBD > 16 */ + if (csio->cdb_len > 16) + { + AGTIAPI_PRINTK( "agtiapi_QueueCmnd_: unsupported CDB length %d\n", + csio->cdb_len ); + ccb->ccb_h.status &= ~CAM_SIM_QUEUED; + ccb->ccb_h.status &= ~CAM_STATUS_MASK; + ccb->ccb_h.status |= CAM_REQ_INVALID;//CAM_REQ_CMP; + xpt_done(ccb); + return tiError; + } + if (TID < 0 || TID >= maxTargets) + { + AGTIAPI_PRINTK("agtiapi_QueueCmnd_: INVALID TID ERROR\n"); + ccb->ccb_h.status &= ~CAM_SIM_QUEUED; + ccb->ccb_h.status &= ~CAM_STATUS_MASK; + ccb->ccb_h.status |= CAM_DEV_NOT_THERE;//CAM_REQ_CMP; + xpt_done(ccb); + return tiError; + } + /* get a ccb */ + if ((pccb = agtiapi_GetCCB(pmcsc)) == NULL) + { + ag_device_t *targ; + AGTIAPI_PRINTK("agtiapi_QueueCmnd_: GetCCB ERROR\n"); + if (pmcsc != NULL) + { + TID = INDEX(pmcsc, TID); + targ = &pmcsc->pDevList[TID]; + } + if (targ != NULL) + { + agtiapi_adjust_queue_depth(ccb->ccb_h.path,targ->qdepth); + } + ccb->ccb_h.status &= ~CAM_SIM_QUEUED; + ccb->ccb_h.status &= ~CAM_STATUS_MASK; + ccb->ccb_h.status |= CAM_REQUEUE_REQ; + xpt_done(ccb); + return tiBusy; + } + pccb->pmcsc = pmcsc; + /* initialize Command Control Block (CCB) */ + pccb->targetId = TID; + pccb->lun = LUN; + pccb->channel = Channel; + pccb->ccb = ccb; /* for struct scsi_cmnd */ + pccb->senseLen = csio->sense_len; + pccb->startTime = ticks; + pccb->pSenseData = (caddr_t) &csio->sense_data; + pccb->tiSuperScsiRequest.flags = 0; + + /* each channel is reserved for different addr modes */ + pccb->addrMode = agtiapi_AddrModes[Channel]; + + status = agtiapi_PrepareSGList(pmcsc, pccb); + if (status != tiSuccess) + { + AGTIAPI_PRINTK("agtiapi_QueueCmnd_: agtiapi_PrepareSGList failure\n"); + agtiapi_FreeCCB(pmcsc, pccb); + if (status == tiReject) + { + ccb->ccb_h.status = CAM_REQ_INVALID; + } + else + { + ccb->ccb_h.status = CAM_REQ_CMP; + } + xpt_done( ccb ); + return tiError; + } + return status; +} + +/****************************************************************************** +agtiapi_DumpCDB() + +Purpose: + Prints out CDB +Parameters: + const char *ptitle (IN) A string to be printed + ccb_t *pccb (IN) A pointer to the driver's own CCB, not CAM's CCB +Return: +Note: +******************************************************************************/ +STATIC void agtiapi_DumpCDB(const char *ptitle, ccb_t *pccb) +{ + union ccb *ccb; + struct ccb_scsiio *csio; + bit8 cdb[64]; + int len; + + if (pccb == NULL) + { + printf( "agtiapi_DumpCDB: no pccb here \n" ); + panic("agtiapi_DumpCDB: pccb is NULL. called from %s\n", ptitle); + return; + } + ccb = pccb->ccb; + if (ccb == NULL) + { + printf( "agtiapi_DumpCDB: no ccb here \n" ); + panic( "agtiapi_DumpCDB: pccb %p ccb %p flags %d ccb NULL! " + "called from %s\n", + pccb, pccb->ccb, pccb->flags, ptitle ); + return; + } + csio = &ccb->csio; + if (csio == NULL) + { + printf( "agtiapi_DumpCDB: no csio here \n" ); + panic( "agtiapi_DumpCDB: pccb%p ccb%p flags%d csio NULL! called from %s\n", + pccb, pccb->ccb, pccb->flags, ptitle ); + return; + } + len = MIN(64, csio->cdb_len); + if (csio->ccb_h.flags & CAM_CDB_POINTER) + { + bcopy(csio->cdb_io.cdb_ptr, &cdb[0], len); + } + else + { + bcopy(csio->cdb_io.cdb_bytes, &cdb[0], len); + } + + AGTIAPI_IO( "agtiapi_DumpCDB: pccb%p CDB0x%x csio->cdb_len %d" + " len %d from %s\n", + pccb, cdb[0], + csio->cdb_len, + len, + ptitle ); + return; +} + +/****************************************************************************** +agtiapi_DoSoftReset() + +Purpose: + Do card reset +Parameters: + *data (IN) point to pmcsc (struct agtiapi_softc *) +Return: +Note: +******************************************************************************/ +int agtiapi_DoSoftReset (struct agtiapi_softc *pmcsc) +{ + int ret; + unsigned long flags; + + pmcsc->flags |= AGTIAPI_SOFT_RESET; + AG_SPIN_LOCK_IRQ( agtiapi_host_lock, flags ); + ret = agtiapi_ResetCard( pmcsc, &flags ); + AG_SPIN_UNLOCK_IRQ( agtiapi_host_lock, flags ); + + if( ret != AGTIAPI_SUCCESS ) + return tiError; + + return SUCCESS; +} + +/****************************************************************************** +agtiapi_CheckIOTimeout() + +Purpose: + Timeout function for SCSI IO or TM +Parameters: + *data (IN) point to pCard (ag_card_t *) +Return: +Note: +******************************************************************************/ +STATIC void agtiapi_CheckIOTimeout(void *data) +{ + U32 status = AGTIAPI_SUCCESS; + ccb_t *pccb; + struct agtiapi_softc *pmcsc; + pccb_t pccb_curr; + pccb_t pccb_next; + pmcsc = (struct agtiapi_softc *)data; + + //AGTIAPI_PRINTK("agtiapi_CheckIOTimeout: Enter\n"); + + //AGTIAPI_PRINTK("agtiapi_CheckIOTimeout: Active CCB %d\n", pmcsc->activeCCB); + + pccb = (pccb_t)pmcsc->ccbChainList; + + /* if link is down, do nothing */ + if ((pccb == NULL) || (pmcsc->activeCCB == 0)) + { + //AGTIAPI_PRINTK("agtiapi_CheckIOTimeout: goto restart_timer\n"); + goto restart_timer; + } + + AG_SPIN_LOCK_IRQ(agtiapi_host_lock, flags); + if (pmcsc->flags & AGTIAPI_SHUT_DOWN) + goto ext; + + pccb_curr = pccb; + + /* Walk thorugh the IO Chain linked list to find the pending io */ + /* Set the TM flag based on the pccb type, i.e SCSI IO or TM cmd */ + while (pccb_curr != NULL) + { + /* start from 1st ccb in the chain */ + pccb_next = pccb_curr->pccbChainNext; + if( (pccb_curr->flags == 0) || (pccb_curr->tiIORequest.tdData == NULL) || + (pccb_curr->startTime == 0) /* && (pccb->startTime == 0) */) + { + //AGTIAPI_PRINTK("agtiapi_CheckIOTimeout: move to next element\n"); + } + else if ( ( (ticks-pccb_curr->startTime) >= ag_timeout_secs ) && + !(pccb_curr->flags & TIMEDOUT) ) + { + AGTIAPI_PRINTK( "agtiapi_CheckIOTimeout: pccb %p timed out, call TM " + "function -- flags=%x startTime=%ld tdData = %p\n", + pccb_curr, pccb_curr->flags, pccb->startTime, + pccb_curr->tiIORequest.tdData ); + pccb_curr->flags |= TIMEDOUT; + status = agtiapi_StartTM(pmcsc, pccb_curr); + if (status == AGTIAPI_SUCCESS) + { + AGTIAPI_PRINTK( "agtiapi_CheckIOTimeout: TM Request sent with " + "success\n" ); + goto restart_timer; + } + else + { +#ifdef AGTIAPI_LOCAL_RESET + /* abort request did not go through */ + AGTIAPI_PRINTK("agtiapi_CheckIOTimeout: Abort request failed\n"); + /* TODO: call Soft reset here */ + AGTIAPI_PRINTK( "agtiapi_CheckIOTimeout:in agtiapi_CheckIOTimeout() " + "abort request did not go thru ==> soft reset#7, then " + "restart timer\n" ); + agtiapi_DoSoftReset (pmcsc); + goto restart_timer; +#endif + } + } + pccb_curr = pccb_next; + } +restart_timer: + callout_reset(&pmcsc->IO_timer, 1*hz, agtiapi_CheckIOTimeout, pmcsc); + +ext: + AG_SPIN_UNLOCK_IRQ(agtiapi_host_lock, flags); + return; +} + +/****************************************************************************** +agtiapi_StartTM() + +Purpose: + DDI calls for aborting outstanding IO command +Parameters: + struct scsi_cmnd *pccb (IN) Pointer to the command to be aborted + unsigned long flags (IN/out) spinlock flags used in locking from + calling layers +Return: + AGTIAPI_SUCCESS - success + AGTIAPI_FAIL - fail +******************************************************************************/ +int +agtiapi_StartTM(struct agtiapi_softc *pCard, ccb_t *pccb) +{ + ccb_t *pTMccb = NULL; + U32 status = AGTIAPI_SUCCESS; + ag_device_t *pDevice = NULL; + U32 TMstatus = tiSuccess; + AGTIAPI_PRINTK( "agtiapi_StartTM: pccb %p, pccb->flags %x\n", + pccb, pccb->flags ); + if (pccb == NULL) + { + AGTIAPI_PRINTK("agtiapi_StartTM: %p not found\n",pccb); + status = AGTIAPI_SUCCESS; + goto ext; + } + if (!pccb->tiIORequest.tdData) + { + /* should not be the case */ + AGTIAPI_PRINTK("agtiapi_StartTM: ccb %p flag 0x%x tid %d no tdData " + "ERROR\n", pccb, pccb->flags, pccb->targetId); + status = AGTIAPI_FAIL; + } + else + { + /* If timedout CCB is TM_ABORT_TASK command, issue LocalAbort first to + clear pending TM_ABORT_TASK */ + /* Else Device State will not be put back to Operational, (refer FW) */ + if (pccb->flags & TASK_MANAGEMENT) + { + if (tiINIIOAbort(&pCard->tiRoot, &pccb->tiIORequest) != tiSuccess) + { + AGTIAPI_PRINTK( "agtiapi_StartTM: LocalAbort Request for Abort_TASK " + "TM failed\n" ); + /* TODO: call Soft reset here */ + AGTIAPI_PRINTK( "agtiapi_StartTM: in agtiapi_StartTM() abort " + "tiINIIOAbort() failed ==> soft reset#8\n" ); + agtiapi_DoSoftReset( pCard ); + } + else + { + AGTIAPI_PRINTK( "agtiapi_StartTM: LocalAbort for Abort_TASK TM " + "Request sent\n" ); + status = AGTIAPI_SUCCESS; + } + } + else + { + /* get a ccb */ + if ((pTMccb = agtiapi_GetCCB(pCard)) == NULL) + { + AGTIAPI_PRINTK("agtiapi_StartTM: TM resource unavailable!\n"); + status = AGTIAPI_FAIL; + goto ext; + } + pTMccb->pmcsc = pCard; + pTMccb->targetId = pccb->targetId; + pTMccb->devHandle = pccb->devHandle; + if (pTMccb->targetId >= pCard->devDiscover) + { + AGTIAPI_PRINTK("agtiapi_StartTM: Incorrect dev Id in TM!\n"); + status = AGTIAPI_FAIL; + goto ext; + } + if (pTMccb->targetId < 0 || pTMccb->targetId >= maxTargets) + { + return AGTIAPI_FAIL; + } + if (INDEX(pCard, pTMccb->targetId) >= maxTargets) + { + return AGTIAPI_FAIL; + } + pDevice = &pCard->pDevList[INDEX(pCard, pTMccb->targetId)]; + if ((pDevice == NULL) || !(pDevice->flags & ACTIVE)) + { + return AGTIAPI_FAIL; + } + + /* save pending io to issue local abort at Task mgmt CB */ + pTMccb->pccbIO = pccb; + AGTIAPI_PRINTK( "agtiapi_StartTM: pTMccb %p flag %x tid %d via TM " + "request !\n", + pTMccb, pTMccb->flags, pTMccb->targetId ); + pTMccb->flags &= ~(TASK_SUCCESS | ACTIVE); + pTMccb->flags |= TASK_MANAGEMENT; + TMstatus = tiINITaskManagement(&pCard->tiRoot, + pccb->devHandle, + AG_ABORT_TASK, + &pccb->tiSuperScsiRequest.scsiCmnd.lun, + &pccb->tiIORequest, + &pTMccb->tiIORequest); + if (TMstatus == tiSuccess) + { + AGTIAPI_PRINTK( "agtiapi_StartTM: TM_ABORT_TASK request success ccb " + "%p, pTMccb %p\n", + pccb, pTMccb ); + pTMccb->startTime = ticks; + status = AGTIAPI_SUCCESS; + } + else if (TMstatus == tiIONoDevice) + { + AGTIAPI_PRINTK( "agtiapi_StartTM: TM_ABORT_TASK request tiIONoDevice ccb " + "%p, pTMccb %p\n", + pccb, pTMccb ); + status = AGTIAPI_SUCCESS; + } + else + { + AGTIAPI_PRINTK( "agtiapi_StartTM: TM_ABORT_TASK request failed ccb %p, " + "pTMccb %p\n", + pccb, pTMccb ); + status = AGTIAPI_FAIL; + agtiapi_FreeTMCCB(pCard, pTMccb); + /* TODO */ + /* call TM_TARGET_RESET */ + } + } + } + ext: + AGTIAPI_PRINTK("agtiapi_StartTM: return %d flgs %x\n", status, + (pccb) ? pccb->flags : -1); + return status; +} /* agtiapi_StartTM */ + +#if __FreeBSD_version > 901000 +/****************************************************************************** +agtiapi_PrepareSGList() + +Purpose: + This function prepares scatter-gather list for the given ccb +Parameters: + struct agtiapi_softc *pmsc (IN) Pointer to the HBA data structure + ccb_t *pccb (IN) A pointer to the driver's own CCB, not CAM's CCB +Return: + 0 - success + 1 - failure + +Note: +******************************************************************************/ +static int agtiapi_PrepareSGList(struct agtiapi_softc *pmcsc, ccb_t *pccb) +{ + union ccb *ccb = pccb->ccb; + struct ccb_scsiio *csio = &ccb->csio; + struct ccb_hdr *ccbh = &ccb->ccb_h; + AGTIAPI_IO( "agtiapi_PrepareSGList: start\n" ); + +// agtiapi_DumpCDB("agtiapi_PrepareSGList", pccb); + AGTIAPI_IO( "agtiapi_PrepareSGList: dxfer_len %d\n", csio->dxfer_len ); + + if ((ccbh->flags & CAM_DIR_MASK) != CAM_DIR_NONE) + { + switch((ccbh->flags & CAM_DATA_MASK)) + { + int error; + struct bus_dma_segment seg; + case CAM_DATA_VADDR: + /* Virtual address that needs to translated into one or more physical address ranges. */ + // int error; + // AG_LOCAL_LOCK(&(pmcsc->pCardInfo->pmIOLock)); + AGTIAPI_IO( "agtiapi_PrepareSGList: virtual address\n" ); + error = bus_dmamap_load( pmcsc->buffer_dmat, + pccb->CCB_dmamap, + csio->data_ptr, + csio->dxfer_len, + agtiapi_PrepareSGListCB, + pccb, + BUS_DMA_NOWAIT/* 0 */ ); + // AG_LOCAL_UNLOCK( &(pmcsc->pCardInfo->pmIOLock) ); + + if (error == EINPROGRESS) + { + /* So as to maintain ordering, freeze the controller queue until our mapping is returned. */ + AGTIAPI_PRINTK("agtiapi_PrepareSGList: EINPROGRESS\n"); + xpt_freeze_simq(pmcsc->sim, 1); + pmcsc->SimQFrozen = agTRUE; + ccbh->status |= CAM_RELEASE_SIMQ; + } + break; + case CAM_DATA_PADDR: + /* We have been given a pointer to single physical buffer. */ + /* pccb->tiSuperScsiRequest.sglVirtualAddr = seg.ds_addr; */ + //struct bus_dma_segment seg; + AGTIAPI_PRINTK("agtiapi_PrepareSGList: physical address\n"); + seg.ds_addr = + (bus_addr_t)(vm_offset_t)csio->data_ptr; + seg.ds_len = csio->dxfer_len; + // * 0xFF to be defined + agtiapi_PrepareSGListCB(pccb, &seg, 1, 0xAABBCCDD); + break; + default: + AGTIAPI_PRINTK("agtiapi_PrepareSGList: unexpected case\n"); + return tiReject; + } + } + else + { + agtiapi_PrepareSGListCB(pccb, NULL, 0, 0xAAAAAAAA); + } + return tiSuccess; +} +#else +/****************************************************************************** +agtiapi_PrepareSGList() + +Purpose: + This function prepares scatter-gather list for the given ccb +Parameters: + struct agtiapi_softc *pmsc (IN) Pointer to the HBA data structure + ccb_t *pccb (IN) A pointer to the driver's own CCB, not CAM's CCB +Return: + 0 - success + 1 - failure + +Note: +******************************************************************************/ +static int agtiapi_PrepareSGList(struct agtiapi_softc *pmcsc, ccb_t *pccb) +{ + union ccb *ccb = pccb->ccb; + struct ccb_scsiio *csio = &ccb->csio; + struct ccb_hdr *ccbh = &ccb->ccb_h; + AGTIAPI_IO( "agtiapi_PrepareSGList: start\n" ); +// agtiapi_DumpCDB("agtiapi_PrepareSGList", pccb); + AGTIAPI_IO( "agtiapi_PrepareSGList: dxfer_len %d\n", csio->dxfer_len ); + + if ((ccbh->flags & CAM_DIR_MASK) != CAM_DIR_NONE) + { + if ((ccbh->flags & CAM_SCATTER_VALID) == 0) + { + /* We've been given a pointer to a single buffer. */ + if ((ccbh->flags & CAM_DATA_PHYS) == 0) + { + /* Virtual address that needs to translated into one or more physical address ranges. */ + int error; + // AG_LOCAL_LOCK(&(pmcsc->pCardInfo->pmIOLock)); + AGTIAPI_IO( "agtiapi_PrepareSGList: virtual address\n" ); + error = bus_dmamap_load( pmcsc->buffer_dmat, + pccb->CCB_dmamap, + csio->data_ptr, + csio->dxfer_len, + agtiapi_PrepareSGListCB, + pccb, + BUS_DMA_NOWAIT/* 0 */ ); + // AG_LOCAL_UNLOCK( &(pmcsc->pCardInfo->pmIOLock) ); + + if (error == EINPROGRESS) + { + /* So as to maintain ordering, freeze the controller queue until our mapping is returned. */ + AGTIAPI_PRINTK("agtiapi_PrepareSGList: EINPROGRESS\n"); + xpt_freeze_simq(pmcsc->sim, 1); + pmcsc->SimQFrozen = agTRUE; + ccbh->status |= CAM_RELEASE_SIMQ; + } + } + else + { + /* We have been given a pointer to single physical buffer. */ + /* pccb->tiSuperScsiRequest.sglVirtualAddr = seg.ds_addr; */ + struct bus_dma_segment seg; + AGTIAPI_PRINTK("agtiapi_PrepareSGList: physical address\n"); + seg.ds_addr = + (bus_addr_t)(vm_offset_t)csio->data_ptr; + seg.ds_len = csio->dxfer_len; + // * 0xFF to be defined + agtiapi_PrepareSGListCB(pccb, &seg, 1, 0xAABBCCDD); + } + } + else + { + + AGTIAPI_PRINTK("agtiapi_PrepareSGList: unexpected case\n"); + return tiReject; + } + } + else + { + agtiapi_PrepareSGListCB(pccb, NULL, 0, 0xAAAAAAAA); + } + return tiSuccess; +} + +#endif +/****************************************************************************** +agtiapi_PrepareSGListCB() + +Purpose: + Callback function for bus_dmamap_load() + This fuctions sends IO to LL layer. +Parameters: + void *arg (IN) Pointer to the HBA data structure + bus_dma_segment_t *segs (IN) Pointer to dma segment + int nsegs (IN) number of dma segment + int error (IN) error +Return: +Note: +******************************************************************************/ +static void agtiapi_PrepareSGListCB( void *arg, + bus_dma_segment_t *segs, + int nsegs, + int error ) +{ + pccb_t pccb = arg; + union ccb *ccb = pccb->ccb; + struct ccb_scsiio *csio = &ccb->csio; + + struct agtiapi_softc *pmcsc; + tiIniScsiCmnd_t *pScsiCmnd; + bit32 i; + bus_dmasync_op_t op; + U32_64 phys_addr; + U08 *CDB; + int io_is_encryptable = 0; + unsigned long long start_lba = 0; + ag_device_t *pDev; + U32 TID = CMND_TO_TARGET(ccb); + + AGTIAPI_IO( "agtiapi_PrepareSGListCB: start, nsegs %d error 0x%x\n", + nsegs, error ); + pmcsc = pccb->pmcsc; + + if (error != tiSuccess) + { + if (error == 0xAABBCCDD || error == 0xAAAAAAAA) + { + // do nothing + } + else + { + AGTIAPI_PRINTK("agtiapi_PrepareSGListCB: error status 0x%x\n", error); + bus_dmamap_unload(pmcsc->buffer_dmat, pccb->CCB_dmamap); + bus_dmamap_destroy(pmcsc->buffer_dmat, pccb->CCB_dmamap); + agtiapi_FreeCCB(pmcsc, pccb); + ccb->ccb_h.status = CAM_REQ_CMP; + xpt_done(ccb); + return; + } + } + + if (nsegs > AGTIAPI_MAX_DMA_SEGS) + { + AGTIAPI_PRINTK( "agtiapi_PrepareSGListCB: over the limit. nsegs %d" + " AGTIAPI_MAX_DMA_SEGS %d\n", + nsegs, AGTIAPI_MAX_DMA_SEGS ); + bus_dmamap_unload(pmcsc->buffer_dmat, pccb->CCB_dmamap); + bus_dmamap_destroy(pmcsc->buffer_dmat, pccb->CCB_dmamap); + agtiapi_FreeCCB(pmcsc, pccb); + ccb->ccb_h.status = CAM_REQ_CMP; + xpt_done(ccb); + return; + } + + + /* fill in IO information */ + pccb->dataLen = csio->dxfer_len; + + /* start fill in sgl structure */ + if (nsegs == 1 && error == 0xAABBCCDD) + { + /* to be tested */ + /* A single physical buffer */ + AGTIAPI_PRINTK("agtiapi_PrepareSGListCB: nsegs is 1\n"); + CPU_TO_LE32(pccb->tiSuperScsiRequest.agSgl1, segs[0].ds_addr); + pccb->tiSuperScsiRequest.agSgl1.len = htole32(pccb->dataLen); + pccb->tiSuperScsiRequest.agSgl1.type = htole32(tiSgl); + pccb->tiSuperScsiRequest.sglVirtualAddr = (void *)segs->ds_addr; + pccb->numSgElements = 1; + } + else if (nsegs == 0 && error == 0xAAAAAAAA) + { + /* no data transfer */ + AGTIAPI_IO( "agtiapi_PrepareSGListCB: no data transfer\n" ); + pccb->tiSuperScsiRequest.agSgl1.len = 0; + pccb->dataLen = 0; + pccb->numSgElements = 0; + } + else + { + /* virtual/logical buffer */ + if (nsegs == 1) + { + pccb->dataLen = segs[0].ds_len; + + CPU_TO_LE32(pccb->tiSuperScsiRequest.agSgl1, segs[0].ds_addr); + pccb->tiSuperScsiRequest.agSgl1.type = htole32(tiSgl); + pccb->tiSuperScsiRequest.agSgl1.len = htole32(segs[0].ds_len); + pccb->tiSuperScsiRequest.sglVirtualAddr = (void *)csio->data_ptr; + pccb->numSgElements = nsegs; + + } + else + { + pccb->dataLen = 0; + /* loop */ + for (i = 0; i < nsegs; i++) + { + pccb->sgList[i].len = htole32(segs[i].ds_len); + CPU_TO_LE32(pccb->sgList[i], segs[i].ds_addr); + pccb->sgList[i].type = htole32(tiSgl); + pccb->dataLen += segs[i].ds_len; + + } /* for */ + pccb->numSgElements = nsegs; + /* set up sgl buffer address */ + CPU_TO_LE32(pccb->tiSuperScsiRequest.agSgl1, pccb->tisgl_busaddr); + pccb->tiSuperScsiRequest.agSgl1.type = htole32(tiSglList); + pccb->tiSuperScsiRequest.agSgl1.len = htole32(pccb->dataLen); + pccb->tiSuperScsiRequest.sglVirtualAddr = (void *)csio->data_ptr; + pccb->numSgElements = nsegs; + } /* else */ + } + + /* set data transfer direction */ + if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) + { + op = BUS_DMASYNC_PREWRITE; + pccb->tiSuperScsiRequest.dataDirection = tiDirectionOut; + } + else + { + op = BUS_DMASYNC_PREREAD; + pccb->tiSuperScsiRequest.dataDirection = tiDirectionIn; + } + + pScsiCmnd = &pccb->tiSuperScsiRequest.scsiCmnd; + + pScsiCmnd->expDataLength = pccb->dataLen; + + if (csio->ccb_h.flags & CAM_CDB_POINTER) + { + bcopy(csio->cdb_io.cdb_ptr, &pScsiCmnd->cdb[0], csio->cdb_len); + } + else + { + bcopy(csio->cdb_io.cdb_bytes, &pScsiCmnd->cdb[0],csio->cdb_len); + } + + CDB = &pScsiCmnd->cdb[0]; + + switch (CDB[0]) + { + case REQUEST_SENSE: /* requires different buffer */ + /* This code should not be excercised because SAS support auto sense + For the completeness, vtophys() is still used here. + */ + AGTIAPI_PRINTK("agtiapi_PrepareSGListCB: QueueCmnd - REQUEST SENSE new\n"); + pccb->tiSuperScsiRequest.agSgl1.len = htole32(pccb->senseLen); + phys_addr = vtophys(&csio->sense_data); + CPU_TO_LE32(pccb->tiSuperScsiRequest.agSgl1, phys_addr); + pccb->tiSuperScsiRequest.agSgl1.type = htole32(tiSgl); + pccb->dataLen = pccb->senseLen; + pccb->numSgElements = 1; + break; + case INQUIRY: + /* only using lun 0 for device type detection */ + pccb->flags |= AGTIAPI_INQUIRY; + break; + case TEST_UNIT_READY: + case RESERVE: + case RELEASE: + case START_STOP: + pccb->tiSuperScsiRequest.agSgl1.len = 0; + pccb->dataLen = 0; + break; + case READ_6: + case WRITE_6: + /* Extract LBA */ + start_lba = ((CDB[1] & 0x1f) << 16) | + (CDB[2] << 8) | + (CDB[3]); +#ifdef HIALEAH_ENCRYPTION + io_is_encryptable = 1; +#endif + break; + case READ_10: + case WRITE_10: + case READ_12: + case WRITE_12: + /* Extract LBA */ + start_lba = (CDB[2] << 24) | + (CDB[3] << 16) | + (CDB[4] << 8) | + (CDB[5]); +#ifdef HIALEAH_ENCRYPTION + io_is_encryptable = 1; +#endif + break; + case READ_16: + case WRITE_16: + /* Extract LBA */ + start_lba = (CDB[2] << 24) | + (CDB[3] << 16) | + (CDB[4] << 8) | + (CDB[5]); + start_lba <<= 32; + start_lba |= ((CDB[6] << 24) | + (CDB[7] << 16) | + (CDB[8] << 8) | + (CDB[9])); +#ifdef HIALEAH_ENCRYPTION + io_is_encryptable = 1; +#endif + break; + default: + break; + } + + /* fill device lun based one address mode */ + agtiapi_SetLunField(pccb); + + if (pccb->targetId < 0 || pccb->targetId >= maxTargets) + { + pccb->ccbStatus = tiIOFailed; + pccb->scsiStatus = tiDetailNoLogin; + agtiapi_FreeCCB(pmcsc, pccb); + ccb->ccb_h.status = CAM_DEV_NOT_THERE; // ## v. CAM_FUNC_NOTAVAIL + xpt_done(ccb); + pccb->ccb = NULL; + return; + } + if (INDEX(pmcsc, pccb->targetId) >= maxTargets) + { + pccb->ccbStatus = tiIOFailed; + pccb->scsiStatus = tiDetailNoLogin; + agtiapi_FreeCCB(pmcsc, pccb); + ccb->ccb_h.status = CAM_DEV_NOT_THERE; // ## v. CAM_FUNC_NOTAVAIL + xpt_done(ccb); + pccb->ccb = NULL; + return; + } + pDev = &pmcsc->pDevList[INDEX(pmcsc, pccb->targetId)]; + +#if 1 + if ((pmcsc->flags & EDC_DATA) && + (pDev->flags & EDC_DATA)) + { + /* + * EDC support: + * + * Possible command supported - + * READ_6, READ_10, READ_12, READ_16, READ_LONG, READ_BUFFER, + * READ_DEFECT_DATA, etc. + * WRITE_6, WRITE_10, WRITE_12, WRITE_16, WRITE_LONG, WRITE_LONG2, + * WRITE_BUFFER, WRITE_VERIFY, WRITE_VERIFY_12, etc. + * + * Do some data length adjustment and set chip operation instruction. + */ + switch (CDB[0]) + { + case READ_6: + case READ_10: + case READ_12: + case READ_16: + // BUG_ON(pccb->tiSuperScsiRequest.flags & TI_SCSI_INITIATOR_ENCRYPT); +#ifdef AGTIAPI_TEST_DIF + pccb->tiSuperScsiRequest.flags |= TI_SCSI_INITIATOR_DIF; +#endif + pccb->flags |= EDC_DATA; + +#ifdef TEST_VERIFY_AND_FORWARD + pccb->tiSuperScsiRequest.Dif.flags = + DIF_VERIFY_FORWARD | DIF_UDT_REF_BLOCK_COUNT; + if(pDev->sector_size == 520) { + pScsiCmnd->expDataLength += (pccb->dataLen / 512) * 8; + } else if(pDev->sector_size == 4104) { + pScsiCmnd->expDataLength += (pccb->dataLen / 4096) * 8; + } +#else +#ifdef AGTIAPI_TEST_DIF + pccb->tiSuperScsiRequest.Dif.flags = + DIF_VERIFY_DELETE | DIF_UDT_REF_BLOCK_COUNT; +#endif +#endif +#ifdef AGTIAPI_TEST_DIF + switch(pDev->sector_size) { + case 528: + pccb->tiSuperScsiRequest.Dif.flags |= + ( DIF_BLOCK_SIZE_520 << 16 ); + break; + case 4104: + pccb->tiSuperScsiRequest.Dif.flags |= + ( DIF_BLOCK_SIZE_4096 << 16 ); + break; + case 4168: + pccb->tiSuperScsiRequest.Dif.flags |= + ( DIF_BLOCK_SIZE_4160 << 16 ); + break; + } + + if(pCard->flags & EDC_DATA_CRC) + pccb->tiSuperScsiRequest.Dif.flags |= DIF_CRC_VERIFICATION; + + /* Turn on upper 4 bits of UVM */ + pccb->tiSuperScsiRequest.Dif.flags |= 0x03c00000; + +#endif +#ifdef AGTIAPI_TEST_DPL + if(agtiapi_SetupDifPerLA(pCard, pccb, start_lba) < 0) { + printk(KERN_ERR "SetupDifPerLA Failed.\n"); + cmnd->result = SCSI_HOST(DID_ERROR); + goto err; + } + pccb->tiSuperScsiRequest.Dif.enableDIFPerLA = TRUE; +#endif +#ifdef AGTIAPI_TEST_DIF + /* Set App Tag */ + pccb->tiSuperScsiRequest.Dif.udtArray[0] = 0xaa; + pccb->tiSuperScsiRequest.Dif.udtArray[1] = 0xbb; + + /* Set LBA in UDT array */ + if(CDB[0] == READ_6) { + pccb->tiSuperScsiRequest.Dif.udtArray[2] = CDB[3]; + pccb->tiSuperScsiRequest.Dif.udtArray[3] = CDB[2]; + pccb->tiSuperScsiRequest.Dif.udtArray[4] = CDB[1] & 0x1f; + pccb->tiSuperScsiRequest.Dif.udtArray[5] = 0; + } else if(CDB[0] == READ_10 || CDB[0] == READ_12) { + pccb->tiSuperScsiRequest.Dif.udtArray[2] = CDB[5]; + pccb->tiSuperScsiRequest.Dif.udtArray[3] = CDB[4]; + pccb->tiSuperScsiRequest.Dif.udtArray[4] = CDB[3]; + pccb->tiSuperScsiRequest.Dif.udtArray[5] = CDB[2]; + } else if(CDB[0] == READ_16) { + pccb->tiSuperScsiRequest.Dif.udtArray[2] = CDB[9]; + pccb->tiSuperScsiRequest.Dif.udtArray[3] = CDB[8]; + pccb->tiSuperScsiRequest.Dif.udtArray[4] = CDB[7]; + pccb->tiSuperScsiRequest.Dif.udtArray[5] = CDB[6]; + /* Note: 32 bits lost */ + } +#endif + + break; + case WRITE_6: + case WRITE_10: + case WRITE_12: + case WRITE_16: + // BUG_ON(pccb->tiSuperScsiRequest.flags & TI_SCSI_INITIATOR_ENCRYPT); + pccb->flags |= EDC_DATA; +#ifdef AGTIAPI_TEST_DIF + pccb->tiSuperScsiRequest.flags |= TI_SCSI_INITIATOR_DIF; + pccb->tiSuperScsiRequest.Dif.flags = + DIF_INSERT | DIF_UDT_REF_BLOCK_COUNT; + switch(pDev->sector_size) { + case 528: + pccb->tiSuperScsiRequest.Dif.flags |= + (DIF_BLOCK_SIZE_520 << 16); + break; + case 4104: + pccb->tiSuperScsiRequest.Dif.flags |= + ( DIF_BLOCK_SIZE_4096 << 16 ); + break; + case 4168: + pccb->tiSuperScsiRequest.Dif.flags |= + ( DIF_BLOCK_SIZE_4160 << 16 ); + break; + } + + /* Turn on upper 4 bits of UUM */ + pccb->tiSuperScsiRequest.Dif.flags |= 0xf0000000; +#endif +#ifdef AGTIAPI_TEST_DPL + if(agtiapi_SetupDifPerLA(pCard, pccb, start_lba) < 0) { + printk(KERN_ERR "SetupDifPerLA Failed.\n"); + cmnd->result = SCSI_HOST(DID_ERROR); + goto err; + } + pccb->tiSuperScsiRequest.Dif.enableDIFPerLA = TRUE; +#endif +#ifdef AGTIAPI_TEST_DIF + /* Set App Tag */ + pccb->tiSuperScsiRequest.Dif.udtArray[0] = 0xaa; + pccb->tiSuperScsiRequest.Dif.udtArray[1] = 0xbb; + + /* Set LBA in UDT array */ + if(CDB[0] == WRITE_6) { + pccb->tiSuperScsiRequest.Dif.udtArray[2] = CDB[3]; + pccb->tiSuperScsiRequest.Dif.udtArray[3] = CDB[2]; + pccb->tiSuperScsiRequest.Dif.udtArray[4] = CDB[1] & 0x1f; + } else if(CDB[0] == WRITE_10 || CDB[0] == WRITE_12) { + pccb->tiSuperScsiRequest.Dif.udtArray[2] = CDB[5]; + pccb->tiSuperScsiRequest.Dif.udtArray[3] = CDB[4]; + pccb->tiSuperScsiRequest.Dif.udtArray[4] = CDB[3]; + pccb->tiSuperScsiRequest.Dif.udtArray[5] = CDB[2]; + } else if(CDB[0] == WRITE_16) { + pccb->tiSuperScsiRequest.Dif.udtArray[2] = CDB[5]; + pccb->tiSuperScsiRequest.Dif.udtArray[3] = CDB[4]; + pccb->tiSuperScsiRequest.Dif.udtArray[4] = CDB[3]; + pccb->tiSuperScsiRequest.Dif.udtArray[5] = CDB[2]; + /* Note: 32 bits lost */ + } +#endif + break; + } + } +#endif /* end of DIF */ + + if ((ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) != 0) + { + switch(csio->tag_action) + { + case MSG_HEAD_OF_Q_TAG: + pScsiCmnd->taskAttribute = TASK_HEAD_OF_QUEUE; + break; + case MSG_ACA_TASK: + pScsiCmnd->taskAttribute = TASK_ACA; + break; + case MSG_ORDERED_Q_TAG: + pScsiCmnd->taskAttribute = TASK_ORDERED; + break; + case MSG_SIMPLE_Q_TAG: /* fall through */ + default: + pScsiCmnd->taskAttribute = TASK_SIMPLE; + break; + } + } + + if (pccb->tiSuperScsiRequest.agSgl1.len != 0 && pccb->dataLen != 0) + { + /* should be just before start IO */ + bus_dmamap_sync(pmcsc->buffer_dmat, pccb->CCB_dmamap, op); + } + + /* + * If assigned pDevHandle is not available + * then there is no need to send it to StartIO() + */ + if (pccb->targetId < 0 || pccb->targetId >= maxTargets) + { + pccb->ccbStatus = tiIOFailed; + pccb->scsiStatus = tiDetailNoLogin; + agtiapi_FreeCCB(pmcsc, pccb); + ccb->ccb_h.status = CAM_DEV_NOT_THERE; // ## v. CAM_FUNC_NOTAVAIL + xpt_done(ccb); + pccb->ccb = NULL; + return; + } + TID = INDEX(pmcsc, pccb->targetId); + if ((TID >= pmcsc->devDiscover) || + !(pccb->devHandle = pmcsc->pDevList[TID].pDevHandle)) + { + /* + AGTIAPI_PRINTK( "agtiapi_PrepareSGListCB: not sending ccb devH %p," + " target %d tid %d/%d card %p ERROR pccb %p\n", + pccb->devHandle, pccb->targetId, TID, + pmcsc->devDiscover, pmcsc, pccb ); + */ + pccb->ccbStatus = tiIOFailed; + pccb->scsiStatus = tiDetailNoLogin; + agtiapi_FreeCCB(pmcsc, pccb); + ccb->ccb_h.status = CAM_DEV_NOT_THERE; // ## v. CAM_FUNC_NOTAVAIL + xpt_done(ccb); + pccb->ccb = NULL; + return; + } + AGTIAPI_IO( "agtiapi_PrepareSGListCB: send ccb pccb->devHandle %p, " + "pccb->targetId %d TID %d pmcsc->devDiscover %d card %p\n", + pccb->devHandle, pccb->targetId, TID, pmcsc->devDiscover, + pmcsc ); +#ifdef HIALEAH_ENCRYPTION + if(pmcsc->encrypt && io_is_encryptable) { + agtiapi_SetupEncryptedIO(pmcsc, pccb, start_lba); + } else{ + io_is_encryptable = 0; + pccb->tiSuperScsiRequest.flags = 0; + } +#endif + // put the request in send queue + agtiapi_QueueCCB( pmcsc, &pmcsc->ccbSendHead, &pmcsc->ccbSendTail + AG_CARD_LOCAL_LOCK(&pmcsc->sendLock), pccb ); + agtiapi_StartIO(pmcsc); + return; +} + +/****************************************************************************** +agtiapi_StartIO() + +Purpose: + Send IO request down for processing. +Parameters: + (struct agtiapi_softc *pmcsc (IN) Pointer to HBA data structure +Return: +Note: +******************************************************************************/ +STATIC void agtiapi_StartIO( struct agtiapi_softc *pmcsc ) +{ + ccb_t *pccb; + int TID; + ag_device_t *targ; + struct ccb_relsim crs; + + AGTIAPI_IO( "agtiapi_StartIO: start\n" ); + + AG_LOCAL_LOCK( &pmcsc->sendLock ); + pccb = pmcsc->ccbSendHead; + + /* if link is down, do nothing */ + if ((pccb == NULL) || pmcsc->flags & AGTIAPI_RESET) + { + AG_LOCAL_UNLOCK( &pmcsc->sendLock ); + AGTIAPI_PRINTK( "agtiapi_StartIO: goto ext\n" ); + goto ext; + } + + + if (pmcsc != NULL && pccb->targetId >= 0 && pccb->targetId < maxTargets) + { + TID = INDEX(pmcsc, pccb->targetId); + targ = &pmcsc->pDevList[TID]; + } + + + /* clear send queue */ + pmcsc->ccbSendHead = NULL; + pmcsc->ccbSendTail = NULL; + AG_LOCAL_UNLOCK( &pmcsc->sendLock ); + + /* send all ccbs down */ + while (pccb) + { + pccb_t pccb_next; + U32 status; + + pccb_next = pccb->pccbNext; + pccb->pccbNext = NULL; + + if (!pccb->ccb) + { + AGTIAPI_PRINTK( "agtiapi_StartIO: pccb->ccb is NULL ERROR!\n" ); + pccb = pccb_next; + continue; + } + AG_IO_DUMPCCB( pccb ); + + if (!pccb->devHandle) + { + agtiapi_DumpCCB( pccb ); + AGTIAPI_PRINTK( "agtiapi_StartIO: ccb NULL device ERROR!\n" ); + pccb = pccb_next; + continue; + } + AGTIAPI_IO( "agtiapi_StartIO: ccb %p retry %d\n", pccb, pccb->retryCount ); + +#ifndef ABORT_TEST + if( !pccb->devHandle || !pccb->devHandle->osData || /* in rmmod case */ + !(((ag_device_t *)(pccb->devHandle->osData))->flags & ACTIVE)) + { + AGTIAPI_PRINTK( "agtiapi_StartIO: device %p not active! ERROR\n", + pccb->devHandle ); + if( pccb->devHandle ) { + AGTIAPI_PRINTK( "agtiapi_StartIO: device not active detail" + " -- osData:%p\n", + pccb->devHandle->osData ); + if( pccb->devHandle->osData ) { + AGTIAPI_PRINTK( "agtiapi_StartIO: more device not active detail" + " -- active flag:%d\n", + ( (ag_device_t *) + (pccb->devHandle->osData))->flags & ACTIVE ); + } + } + pccb->ccbStatus = tiIOFailed; + pccb->scsiStatus = tiDetailNoLogin; + agtiapi_Done( pmcsc, pccb ); + pccb = pccb_next; + continue; + } +#endif + +#ifdef FAST_IO_TEST + status = agtiapi_FastIOTest( pmcsc, pccb ); +#else + status = tiINISuperIOStart( &pmcsc->tiRoot, + &pccb->tiIORequest, + pccb->devHandle, + &pccb->tiSuperScsiRequest, + (void *)&pccb->tdIOReqBody, + tiInterruptContext ); +#endif + switch( status ) + { + case tiSuccess: + /* + static int squelchCount = 0; + if ( 200000 == squelchCount++ ) // squelch prints + { + AGTIAPI_PRINTK( "agtiapi_StartIO: tiINIIOStart stat tiSuccess %p\n", + pccb ); + squelchCount = 0; // reset count + } + */ + + + break; + case tiDeviceBusy: + AGTIAPI_PRINTK( "agtiapi_StartIO: tiINIIOStart status tiDeviceBusy %p\n", + pccb->ccb ); +#ifdef LOGEVENT + agtiapi_LogEvent( pmcsc, + IOCTL_EVT_SEV_INFORMATIONAL, + 0, + agNULL, + 0, + "tiINIIOStart tiDeviceBusy " ); +#endif + pccb->ccbStatus = tiIOFailed; + pccb->scsiStatus = tiDeviceBusy; + agtiapi_Done(pmcsc, pccb); + break; + case tiBusy: + + AGTIAPI_PRINTK( "agtiapi_StartIO: tiINIIOStart status tiBusy %p\n", + pccb->ccb ); +#ifdef LOGEVENT + agtiapi_LogEvent( pmcsc, + IOCTL_EVT_SEV_INFORMATIONAL, + 0, + agNULL, + 0, + "tiINIIOStart tiBusy " ); +#endif + + pccb->ccbStatus = tiIOFailed; + pccb->scsiStatus = tiBusy; + agtiapi_Done(pmcsc, pccb); + + break; + case tiIONoDevice: + AGTIAPI_PRINTK( "agtiapi_StartIO: tiINIIOStart status tiNoDevice %p " + "ERROR\n", pccb->ccb ); +#ifdef LOGEVENT + agtiapi_LogEvent( pmcsc, + IOCTL_EVT_SEV_INFORMATIONAL, + 0, + agNULL, + 0, + "tiINIIOStart invalid device handle " ); +#endif +#ifndef ABORT_TEST + /* return command back to OS due to no device available */ + ((ag_device_t *)(pccb->devHandle->osData))->flags &= ~ACTIVE; + pccb->ccbStatus = tiIOFailed; + pccb->scsiStatus = tiDetailNoLogin; + agtiapi_Done(pmcsc, pccb); +#else + /* for short cable pull, we want IO retried - 3-18-2005 */ + agtiapi_QueueCCB(pmcsc, &pmcsc->ccbSendHead, &pmcsc->ccbSendTail + AG_CARD_LOCAL_LOCK(&pmcsc->sendLock), pccb); +#endif + break; + case tiError: + AGTIAPI_PRINTK("agtiapi_StartIO: tiINIIOStart status tiError %p\n", + pccb->ccb); +#ifdef LOGEVENT + agtiapi_LogEvent(pmcsc, + IOCTL_EVT_SEV_INFORMATIONAL, + 0, + agNULL, + 0, + "tiINIIOStart tiError "); +#endif + pccb->ccbStatus = tiIOFailed; + pccb->scsiStatus = tiDetailOtherError; + agtiapi_Done(pmcsc, pccb); + break; + default: + AGTIAPI_PRINTK("agtiapi_StartIO: tiINIIOStart status default %x %p\n", + status, pccb->ccb); +#ifdef LOGEVENT + agtiapi_LogEvent(pmcsc, + IOCTL_EVT_SEV_ERROR, + 0, + agNULL, + 0, + "tiINIIOStart unexpected status "); +#endif + pccb->ccbStatus = tiIOFailed; + pccb->scsiStatus = tiDetailOtherError; + agtiapi_Done(pmcsc, pccb); + } + + pccb = pccb_next; + } +ext: + /* some IO requests might have been completed */ + AG_GET_DONE_PCCB(pccb, pmcsc); + return; +} + +/****************************************************************************** +agtiapi_StartSMP() + +Purpose: + Send SMP request down for processing. +Parameters: + (struct agtiapi_softc *pmcsc (IN) Pointer to HBA data structure +Return: +Note: +******************************************************************************/ +STATIC void agtiapi_StartSMP(struct agtiapi_softc *pmcsc) +{ + ccb_t *pccb; + + AGTIAPI_PRINTK("agtiapi_StartSMP: start\n"); + + AG_LOCAL_LOCK(&pmcsc->sendSMPLock); + pccb = pmcsc->smpSendHead; + + /* if link is down, do nothing */ + if ((pccb == NULL) || pmcsc->flags & AGTIAPI_RESET) + { + AG_LOCAL_UNLOCK(&pmcsc->sendSMPLock); + AGTIAPI_PRINTK("agtiapi_StartSMP: goto ext\n"); + goto ext; + } + + /* clear send queue */ + pmcsc->smpSendHead = NULL; + pmcsc->smpSendTail = NULL; + AG_LOCAL_UNLOCK(&pmcsc->sendSMPLock); + + /* send all ccbs down */ + while (pccb) + { + pccb_t pccb_next; + U32 status; + + pccb_next = pccb->pccbNext; + pccb->pccbNext = NULL; + + if (!pccb->ccb) + { + AGTIAPI_PRINTK("agtiapi_StartSMP: pccb->ccb is NULL ERROR!\n"); + pccb = pccb_next; + continue; + } + + if (!pccb->devHandle) + { + AGTIAPI_PRINTK("agtiapi_StartSMP: ccb NULL device ERROR!\n"); + pccb = pccb_next; + continue; + } + pccb->flags |= TAG_SMP; // mark as SMP for later tracking + AGTIAPI_PRINTK( "agtiapi_StartSMP: ccb %p retry %d\n", + pccb, pccb->retryCount ); + status = tiINISMPStart( &pmcsc->tiRoot, + &pccb->tiIORequest, + pccb->devHandle, + &pccb->tiSMPFrame, + (void *)&pccb->tdIOReqBody, + tiInterruptContext); + + switch (status) + { + case tiSuccess: + break; + case tiBusy: + AGTIAPI_PRINTK("agtiapi_StartSMP: tiINISMPStart status tiBusy %p\n", + pccb->ccb); + /* pending ccb back to send queue */ + agtiapi_QueueCCB(pmcsc, &pmcsc->smpSendHead, &pmcsc->smpSendTail + AG_CARD_LOCAL_LOCK(&pmcsc->sendSMPLock), pccb); + break; + case tiError: + AGTIAPI_PRINTK("agtiapi_StartIO: tiINIIOStart status tiError %p\n", + pccb->ccb); + pccb->ccbStatus = tiSMPFailed; + agtiapi_SMPDone(pmcsc, pccb); + break; + default: + AGTIAPI_PRINTK("agtiapi_StartIO: tiINIIOStart status default %x %p\n", + status, pccb->ccb); + pccb->ccbStatus = tiSMPFailed; + agtiapi_SMPDone(pmcsc, pccb); + } + + pccb = pccb_next; + } + ext: + /* some SMP requests might have been completed */ + AG_GET_DONE_SMP_PCCB(pccb, pmcsc); + + return; +} + +#if __FreeBSD_version > 901000 +/****************************************************************************** +agtiapi_PrepareSMPSGList() + +Purpose: + This function prepares scatter-gather list for the given ccb +Parameters: + struct agtiapi_softc *pmsc (IN) Pointer to the HBA data structure + ccb_t *pccb (IN) A pointer to the driver's own CCB, not CAM's CCB +Return: + 0 - success + 1 - failure + +Note: +******************************************************************************/ +static int agtiapi_PrepareSMPSGList( struct agtiapi_softc *pmcsc, ccb_t *pccb ) +{ + /* Pointer to CAM's ccb */ + union ccb *ccb = pccb->ccb; + struct ccb_smpio *csmpio = &ccb->smpio; + struct ccb_hdr *ccbh = &ccb->ccb_h; + + AGTIAPI_PRINTK("agtiapi_PrepareSMPSGList: start\n"); + switch((ccbh->flags & CAM_DATA_MASK)) + { + case CAM_DATA_PADDR: + case CAM_DATA_SG_PADDR: + AGTIAPI_PRINTK( "agtiapi_PrepareSMPSGList: Physical Address not supported\n"); + ccb->ccb_h.status = CAM_REQ_INVALID; + xpt_done(ccb); + return tiReject; + case CAM_DATA_SG: + + /* + * Currently we do not support Multiple SG list + * return error for now + */ + if ( (csmpio->smp_request_sglist_cnt > 1) + || (csmpio->smp_response_sglist_cnt > 1) ) + { + AGTIAPI_PRINTK( "agtiapi_PrepareSMPSGList: Multiple SG list not supported\n"); + ccb->ccb_h.status = CAM_REQ_INVALID; + xpt_done(ccb); + return tiReject; + } + } + if ( csmpio->smp_request_sglist_cnt != 0 ) + { + /* + * Virtual address that needs to translated into + * one or more physical address ranges. + */ + int error; + //AG_LOCAL_LOCK(&(pmcsc->pCardInfo->pmIOLock)); + AGTIAPI_PRINTK("agtiapi_PrepareSGList: virtual address\n"); + error = bus_dmamap_load( pmcsc->buffer_dmat, + pccb->CCB_dmamap, + csmpio->smp_request, + csmpio->smp_request_len, + agtiapi_PrepareSMPSGListCB, + pccb, + BUS_DMA_NOWAIT /* 0 */ ); + + //AG_LOCAL_UNLOCK(&(pmcsc->pCardInfo->pmIOLock)); + + if (error == EINPROGRESS) + { + /* + * So as to maintain ordering, + * freeze the controller queue + * until our mapping is + * returned. + */ + AGTIAPI_PRINTK( "agtiapi_PrepareSGList: EINPROGRESS\n" ); + xpt_freeze_simq( pmcsc->sim, 1 ); + pmcsc->SimQFrozen = agTRUE; + ccbh->status |= CAM_RELEASE_SIMQ; + } + } + if( csmpio->smp_response_sglist_cnt != 0 ) + { + /* + * Virtual address that needs to translated into + * one or more physical address ranges. + */ + int error; + //AG_LOCAL_LOCK( &(pmcsc->pCardInfo->pmIOLock) ); + AGTIAPI_PRINTK( "agtiapi_PrepareSGList: virtual address\n" ); + error = bus_dmamap_load( pmcsc->buffer_dmat, + pccb->CCB_dmamap, + csmpio->smp_response, + csmpio->smp_response_len, + agtiapi_PrepareSMPSGListCB, + pccb, + BUS_DMA_NOWAIT /* 0 */ ); + + //AG_LOCAL_UNLOCK( &(pmcsc->pCardInfo->pmIOLock) ); + + if ( error == EINPROGRESS ) + { + /* + * So as to maintain ordering, + * freeze the controller queue + * until our mapping is + * returned. + */ + AGTIAPI_PRINTK( "agtiapi_PrepareSGList: EINPROGRESS\n" ); + xpt_freeze_simq( pmcsc->sim, 1 ); + pmcsc->SimQFrozen = agTRUE; + ccbh->status |= CAM_RELEASE_SIMQ; + } + } + + else + { + if ( (csmpio->smp_request_sglist_cnt == 0) && + (csmpio->smp_response_sglist_cnt == 0) ) + { + AGTIAPI_PRINTK( "agtiapi_PrepareSMPSGList: physical address\n" ); + pccb->tiSMPFrame.outFrameBuf = (void *)csmpio->smp_request; + pccb->tiSMPFrame.outFrameLen = csmpio->smp_request_len; + pccb->tiSMPFrame.expectedRespLen = csmpio->smp_response_len; + + // 0xFF to be defined + agtiapi_PrepareSMPSGListCB( pccb, NULL, 0, 0xAABBCCDD ); + } + pccb->tiSMPFrame.flag = 0; + } + + return tiSuccess; +} +#else + +/****************************************************************************** +agtiapi_PrepareSMPSGList() + +Purpose: + This function prepares scatter-gather list for the given ccb +Parameters: + struct agtiapi_softc *pmsc (IN) Pointer to the HBA data structure + ccb_t *pccb (IN) A pointer to the driver's own CCB, not CAM's CCB +Return: + 0 - success + 1 - failure + +Note: +******************************************************************************/ +static int agtiapi_PrepareSMPSGList( struct agtiapi_softc *pmcsc, ccb_t *pccb ) +{ + /* Pointer to CAM's ccb */ + union ccb *ccb = pccb->ccb; + struct ccb_smpio *csmpio = &ccb->smpio; + struct ccb_hdr *ccbh = &ccb->ccb_h; + + AGTIAPI_PRINTK("agtiapi_PrepareSMPSGList: start\n"); + + if (ccbh->flags & (CAM_DATA_PHYS|CAM_SG_LIST_PHYS)) + { + AGTIAPI_PRINTK( "agtiapi_PrepareSMPSGList: Physical Address " + "not supported\n" ); + ccb->ccb_h.status = CAM_REQ_INVALID; + xpt_done(ccb); + return tiReject;; + } + + if (ccbh->flags & CAM_SCATTER_VALID) + { + /* + * Currently we do not support Multiple SG list + * return error for now + */ + if ( (csmpio->smp_request_sglist_cnt > 1) + || (csmpio->smp_response_sglist_cnt > 1) ) + { + AGTIAPI_PRINTK( "agtiapi_PrepareSMPSGList: Multiple SG list " + "not supported\n" ); + ccb->ccb_h.status = CAM_REQ_INVALID; + xpt_done(ccb); + return tiReject;; + } + if ( csmpio->smp_request_sglist_cnt != 0 ) + { + /* + * Virtual address that needs to translated into + * one or more physical address ranges. + */ + int error; + //AG_LOCAL_LOCK(&(pmcsc->pCardInfo->pmIOLock)); + AGTIAPI_PRINTK("agtiapi_PrepareSGList: virtual address\n"); + error = bus_dmamap_load( pmcsc->buffer_dmat, + pccb->CCB_dmamap, + csmpio->smp_request, + csmpio->smp_request_len, + agtiapi_PrepareSMPSGListCB, + pccb, + BUS_DMA_NOWAIT /* 0 */ ); + + //AG_LOCAL_UNLOCK(&(pmcsc->pCardInfo->pmIOLock)); + + if (error == EINPROGRESS) + { + /* + * So as to maintain ordering, + * freeze the controller queue + * until our mapping is + * returned. + */ + AGTIAPI_PRINTK( "agtiapi_PrepareSGList: EINPROGRESS\n" ); + xpt_freeze_simq( pmcsc->sim, 1 ); + pmcsc->SimQFrozen = agTRUE; + ccbh->status |= CAM_RELEASE_SIMQ; + } + } + if( csmpio->smp_response_sglist_cnt != 0 ) + { + /* + * Virtual address that needs to translated into + * one or more physical address ranges. + */ + int error; + //AG_LOCAL_LOCK( &(pmcsc->pCardInfo->pmIOLock) ); + AGTIAPI_PRINTK( "agtiapi_PrepareSGList: virtual address\n" ); + error = bus_dmamap_load( pmcsc->buffer_dmat, + pccb->CCB_dmamap, + csmpio->smp_response, + csmpio->smp_response_len, + agtiapi_PrepareSMPSGListCB, + pccb, + BUS_DMA_NOWAIT /* 0 */ ); + + //AG_LOCAL_UNLOCK( &(pmcsc->pCardInfo->pmIOLock) ); + + if ( error == EINPROGRESS ) + { + /* + * So as to maintain ordering, + * freeze the controller queue + * until our mapping is + * returned. + */ + AGTIAPI_PRINTK( "agtiapi_PrepareSGList: EINPROGRESS\n" ); + xpt_freeze_simq( pmcsc->sim, 1 ); + pmcsc->SimQFrozen = agTRUE; + ccbh->status |= CAM_RELEASE_SIMQ; + } + } + } + else + { + if ( (csmpio->smp_request_sglist_cnt == 0) && + (csmpio->smp_response_sglist_cnt == 0) ) + { + AGTIAPI_PRINTK( "agtiapi_PrepareSMPSGList: physical address\n" ); + pccb->tiSMPFrame.outFrameBuf = (void *)csmpio->smp_request; + pccb->tiSMPFrame.outFrameLen = csmpio->smp_request_len; + pccb->tiSMPFrame.expectedRespLen = csmpio->smp_response_len; + + // 0xFF to be defined + agtiapi_PrepareSMPSGListCB( pccb, NULL, 0, 0xAABBCCDD ); + } + pccb->tiSMPFrame.flag = 0; + } + + return tiSuccess; +} + +#endif +/****************************************************************************** +agtiapi_PrepareSMPSGListCB() + +Purpose: + Callback function for bus_dmamap_load() + This fuctions sends IO to LL layer. +Parameters: + void *arg (IN) Pointer to the HBA data structure + bus_dma_segment_t *segs (IN) Pointer to dma segment + int nsegs (IN) number of dma segment + int error (IN) error +Return: +Note: +******************************************************************************/ +static void agtiapi_PrepareSMPSGListCB( void *arg, + bus_dma_segment_t *segs, + int nsegs, + int error ) +{ + pccb_t pccb = arg; + union ccb *ccb = pccb->ccb; + struct agtiapi_softc *pmcsc; + U32 TID = CMND_TO_TARGET(ccb); + int status; + tiDeviceHandle_t *tiExpDevHandle; + tiPortalContext_t *tiExpPortalContext; + ag_portal_info_t *tiExpPortalInfo; + + AGTIAPI_PRINTK( "agtiapi_PrepareSMPSGListCB: start, nsegs %d error 0x%x\n", + nsegs, error ); + pmcsc = pccb->pmcsc; + + if ( error != tiSuccess ) + { + if (error == 0xAABBCCDD) + { + // do nothing + } + else + { + AGTIAPI_PRINTK( "agtiapi_PrepareSMPSGListCB: error status 0x%x\n", + error ); + bus_dmamap_unload( pmcsc->buffer_dmat, pccb->CCB_dmamap ); + bus_dmamap_destroy( pmcsc->buffer_dmat, pccb->CCB_dmamap ); + agtiapi_FreeCCB( pmcsc, pccb ); + ccb->ccb_h.status = CAM_REQ_CMP; + xpt_done( ccb ); + return; + } + } + + if ( nsegs > AGTIAPI_MAX_DMA_SEGS ) + { + AGTIAPI_PRINTK( "agtiapi_PrepareSMPSGListCB: over the limit. nsegs %d " + "AGTIAPI_MAX_DMA_SEGS %d\n", + nsegs, AGTIAPI_MAX_DMA_SEGS ); + bus_dmamap_unload( pmcsc->buffer_dmat, pccb->CCB_dmamap ); + bus_dmamap_destroy( pmcsc->buffer_dmat, pccb->CCB_dmamap ); + agtiapi_FreeCCB( pmcsc, pccb ); + ccb->ccb_h.status = CAM_REQ_CMP; + xpt_done( ccb ); + return; + } + + /* + * If assigned pDevHandle is not available + * then there is no need to send it to StartIO() + */ + /* TODO: Add check for deviceType */ + if ( pccb->targetId < 0 || pccb->targetId >= maxTargets ) + { + agtiapi_FreeCCB( pmcsc, pccb ); + ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; + xpt_done(ccb); + pccb->ccb = NULL; + return; + } + TID = INDEX( pmcsc, pccb->targetId ); + if ( (TID >= pmcsc->devDiscover) || + !(pccb->devHandle = pmcsc->pDevList[TID].pDevHandle) ) + { + AGTIAPI_PRINTK( "agtiapi_PrepareSMPSGListCB: not sending ccb devH %p, " + "target %d tid %d/%d " + "card %p ERROR pccb %p\n", + pccb->devHandle, + pccb->targetId, + TID, + pmcsc->devDiscover, + pmcsc, + pccb ); + agtiapi_FreeCCB( pmcsc, pccb ); + ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; + xpt_done( ccb ); + pccb->ccb = NULL; + return; + } + /* TODO: add indirect handling */ + /* set the flag correctly based on Indiret SMP request and responce */ + + AGTIAPI_PRINTK( "agtiapi_PrepareSMPSGListCB: send ccb pccb->devHandle %p, " + "pccb->targetId %d TID %d pmcsc->devDiscover %d card %p\n", + pccb->devHandle, + pccb->targetId, TID, + pmcsc->devDiscover, + pmcsc ); + tiExpDevHandle = pccb->devHandle; + tiExpPortalInfo = pmcsc->pDevList[TID].pPortalInfo; + tiExpPortalContext = &tiExpPortalInfo->tiPortalContext; + /* Look for the expander associated with the ses device */ + status = tiINIGetExpander( &pmcsc->tiRoot, + tiExpPortalContext, + pccb->devHandle, + &tiExpDevHandle ); + + if ( status != tiSuccess ) + { + AGTIAPI_PRINTK( "agtiapi_PrepareSMPSGListCB: Error getting Expander " + "device\n" ); + agtiapi_FreeCCB( pmcsc, pccb ); + ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; + xpt_done( ccb ); + pccb->ccb = NULL; + return; + } + + /* this is expander device */ + pccb->devHandle = tiExpDevHandle; + /* put the request in send queue */ + agtiapi_QueueCCB( pmcsc, &pmcsc->smpSendHead, &pmcsc->smpSendTail + AG_CARD_LOCAL_LOCK(&pmcsc->sendSMPLock), pccb ); + + agtiapi_StartSMP( pmcsc ); + + return; +} + + +/****************************************************************************** +agtiapi_Done() + +Purpose: + Processing completed ccbs +Parameters: + struct agtiapi_softc *pmcsc (IN) Pointer to HBA data structure + ccb_t *pccb (IN) A pointer to the driver's own CCB, not CAM's CCB +Return: +Note: +******************************************************************************/ +STATIC void agtiapi_Done(struct agtiapi_softc *pmcsc, ccb_t *pccb) +{ + pccb_t pccb_curr = pccb; + pccb_t pccb_next; + + tiIniScsiCmnd_t *cmnd; + union ccb * ccb; + + AGTIAPI_IO("agtiapi_Done: start\n"); + while (pccb_curr) + { + /* start from 1st ccb in the chain */ + pccb_next = pccb_curr->pccbNext; + + if (agtiapi_CheckError(pmcsc, pccb_curr) != 0) + { + /* send command back and release the ccb */ + cmnd = &pccb_curr->tiSuperScsiRequest.scsiCmnd; + + if (cmnd->cdb[0] == RECEIVE_DIAGNOSTIC) + { + AGTIAPI_PRINTK("agtiapi_Done: RECEIVE_DIAG pg %d id %d cmnd %p pccb " + "%p\n", cmnd->cdb[2], pccb_curr->targetId, cmnd, + pccb_curr); + } + + CMND_DMA_UNMAP(pmcsc, ccb); + + /* send the request back to the CAM */ + ccb = pccb_curr->ccb; + agtiapi_FreeCCB(pmcsc, pccb_curr); + xpt_done(ccb); + } + pccb_curr = pccb_next; + } + return; +} + +/****************************************************************************** +agtiapi_SMPDone() + +Purpose: + Processing completed ccbs +Parameters: + struct agtiapi_softc *pmcsc (IN) Ponter to HBA data structure + ccb_t *pccb (IN) A pointer to the driver's own CCB, not + CAM's CCB +Return: +Note: +******************************************************************************/ +STATIC void agtiapi_SMPDone(struct agtiapi_softc *pmcsc, ccb_t *pccb) +{ + pccb_t pccb_curr = pccb; + pccb_t pccb_next; + + union ccb * ccb; + + AGTIAPI_PRINTK("agtiapi_SMPDone: start\n"); + + while (pccb_curr) + { + /* start from 1st ccb in the chain */ + pccb_next = pccb_curr->pccbNext; + + if (agtiapi_CheckSMPError(pmcsc, pccb_curr) != 0) + { + CMND_DMA_UNMAP(pmcsc, ccb); + + /* send the request back to the CAM */ + ccb = pccb_curr->ccb; + agtiapi_FreeSMPCCB(pmcsc, pccb_curr); + xpt_done(ccb); + + } + pccb_curr = pccb_next; + } + + AGTIAPI_PRINTK("agtiapi_SMPDone: Done\n"); + return; +} + +/****************************************************************************** +agtiapi_hexdump() + +Purpose: + Utility function for dumping in hex +Parameters: + const char *ptitle (IN) A string to be printed + bit8 *pbuf (IN) A pointer to a buffer to be printed. + int len (IN) The lengther of the buffer +Return: +Note: +******************************************************************************/ +void agtiapi_hexdump(const char *ptitle, bit8 *pbuf, int len) +{ + int i; + AGTIAPI_PRINTK("%s - hexdump(len=%d):\n", ptitle, (int)len); + if (!pbuf) + { + AGTIAPI_PRINTK("pbuf is NULL\n"); + return; + } + for (i = 0; i < len; ) + { + if (len - i > 4) + { + AGTIAPI_PRINTK( " 0x%02x, 0x%02x, 0x%02x, 0x%02x,\n", pbuf[i], pbuf[i+1], + pbuf[i+2], pbuf[i+3] ); + i += 4; + } + else + { + AGTIAPI_PRINTK(" 0x%02x,", pbuf[i]); + i++; + } + } + AGTIAPI_PRINTK("\n"); +} + + +/****************************************************************************** +agtiapi_CheckError() + +Purpose: + Processes status pertaining to the ccb -- whether it was + completed successfully, aborted, or error encountered. +Parameters: + ag_card_t *pCard (IN) Pointer to HBA data structure + ccb_t *pccd (IN) A pointer to the driver's own CCB, not CAM's CCB +Return: + 0 - the command retry is required + 1 - the command process is completed +Note: + +******************************************************************************/ +STATIC U32 agtiapi_CheckError(struct agtiapi_softc *pmcsc, ccb_t *pccb) +{ + ag_device_t *pDevice; + // union ccb * ccb = pccb->ccb; + union ccb * ccb; + int is_error, TID; + + if (pccb == NULL) { + return 0; + } + ccb = pccb->ccb; + AGTIAPI_IO("agtiapi_CheckError: start\n"); + if (ccb == NULL) + { + /* shouldn't be here but just in case we do */ + AGTIAPI_PRINTK("agtiapi_CheckError: CCB orphan = %p ERROR\n", pccb); + agtiapi_FreeCCB(pmcsc, pccb); + return 0; + } + + is_error = 1; + pDevice = NULL; + if (pmcsc != NULL && pccb->targetId >= 0 && pccb->targetId < maxTargets) + { + if (pmcsc->pWWNList != NULL) + { + TID = INDEX(pmcsc, pccb->targetId); + if (TID < maxTargets) + { + pDevice = &pmcsc->pDevList[TID]; + if (pDevice != NULL) + { + is_error = 0; + } + } + } + } + if (is_error) + { + AGTIAPI_PRINTK("agtiapi_CheckError: pDevice == NULL\n"); + agtiapi_FreeCCB(pmcsc, pccb); + return 0; + } + + /* SCSI status */ + ccb->csio.scsi_status = pccb->scsiStatus; + + if(pDevice->CCBCount > 0){ + atomic_subtract_int(&pDevice->CCBCount,1); +} + AG_LOCAL_LOCK(&pmcsc->freezeLock); + if(pmcsc->freezeSim == agTRUE) + { + pmcsc->freezeSim = agFALSE; + xpt_release_simq(pmcsc->sim, 1); + } + AG_LOCAL_UNLOCK(&pmcsc->freezeLock); + + switch (pccb->ccbStatus) + { + case tiIOSuccess: + AGTIAPI_IO("agtiapi_CheckError: tiIOSuccess pccb %p\n", pccb); + /* CAM status */ + if (pccb->scsiStatus == SCSI_STATUS_OK) + { + ccb->ccb_h.status = CAM_REQ_CMP; + } + else + if (pccb->scsiStatus == SCSI_TASK_ABORTED) + { + ccb->ccb_h.status = CAM_REQ_ABORTED; + } + else + { + ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; + } + if (ccb->csio.scsi_status == SCSI_CHECK_CONDITION) + { + ccb->ccb_h.status |= CAM_AUTOSNS_VALID; + } + + break; + + case tiIOOverRun: + AGTIAPI_PRINTK("agtiapi_CheckError: tiIOOverRun pccb %p\n", pccb); + /* resid is ignored for this condition */ + ccb->csio.resid = 0; + ccb->ccb_h.status = CAM_DATA_RUN_ERR; + break; + case tiIOUnderRun: + AGTIAPI_PRINTK("agtiapi_CheckError: tiIOUnderRun pccb %p\n", pccb); + ccb->csio.resid = pccb->scsiStatus; + ccb->ccb_h.status = CAM_REQ_CMP; + ccb->csio.scsi_status = SCSI_STATUS_OK; + break; + + case tiIOFailed: + AGTIAPI_PRINTK( "agtiapi_CheckError: pccb %p tiIOFailed %d id %d ERROR\n", + pccb, pccb->scsiStatus, pccb->targetId ); + if (pccb->scsiStatus == tiDeviceBusy) + { + AGTIAPI_IO( "agtiapi_CheckError: pccb %p tiIOFailed - tiDetailBusy\n", + pccb ); + ccb->ccb_h.status &= ~CAM_STATUS_MASK; + ccb->ccb_h.status |= CAM_REQUEUE_REQ; + if ((ccb->ccb_h.status & CAM_DEV_QFRZN) == 0) + { + ccb->ccb_h.status |= CAM_DEV_QFRZN; + xpt_freeze_devq(ccb->ccb_h.path, /*count*/1); + } + } + else if(pccb->scsiStatus == tiBusy) + { + AG_LOCAL_LOCK(&pmcsc->freezeLock); + if(pmcsc->freezeSim == agFALSE) + { + pmcsc->freezeSim = agTRUE; + xpt_freeze_simq(pmcsc->sim, 1); + } + AG_LOCAL_UNLOCK(&pmcsc->freezeLock); + ccb->ccb_h.status &= ~CAM_SIM_QUEUED; + ccb->ccb_h.status |= CAM_REQUEUE_REQ; + } + else if (pccb->scsiStatus == tiDetailNoLogin) + { + AGTIAPI_PRINTK( "agtiapi_CheckError: pccb %p tiIOFailed - " + "tiDetailNoLogin ERROR\n", pccb ); + ccb->ccb_h.status = CAM_DEV_NOT_THERE; + } + else if (pccb->scsiStatus == tiDetailNotValid) + { + AGTIAPI_PRINTK( "agtiapi_CheckError: pccb %p tiIOFailed - " + "tiDetailNotValid ERROR\n", pccb ); + ccb->ccb_h.status = CAM_REQ_INVALID; + } + else if (pccb->scsiStatus == tiDetailAbortLogin) + { + AGTIAPI_PRINTK( "agtiapi_CheckError: pccb %p tiIOFailed - " + "tiDetailAbortLogin ERROR\n", pccb ); + ccb->ccb_h.status = CAM_REQ_ABORTED; + } + else if (pccb->scsiStatus == tiDetailAbortReset) + { + AGTIAPI_PRINTK( "agtiapi_CheckError: pccb %p tiIOFailed - " + "tiDetailAbortReset ERROR\n", pccb ); + ccb->ccb_h.status = CAM_REQ_ABORTED; + } + else if (pccb->scsiStatus == tiDetailAborted) + { + AGTIAPI_PRINTK( "agtiapi_CheckError: pccb %p tiIOFailed - " + "tiDetailAborted ERROR\n", pccb ); + ccb->ccb_h.status = CAM_REQ_ABORTED; + } + else if (pccb->scsiStatus == tiDetailOtherError) + { + AGTIAPI_PRINTK( "agtiapi_CheckError: pccb %p tiIOFailed - " + "tiDetailOtherError ERROR\n", pccb ); + ccb->ccb_h.status = CAM_REQ_ABORTED; + } + break; + case tiIODifError: + AGTIAPI_PRINTK( "agtiapi_CheckError: pccb %p tiIOFailed %d id %d ERROR\n", + pccb, pccb->scsiStatus, pccb->targetId ); + if (pccb->scsiStatus == tiDetailDifAppTagMismatch) + { + AGTIAPI_IO( "agtiapi_CheckError: pccb %p tiIOFailed - " + "tiDetailDifAppTagMismatch\n", pccb ); + ccb->ccb_h.status = CAM_REQ_CMP_ERR; + } + else if (pccb->scsiStatus == tiDetailDifRefTagMismatch) + { + AGTIAPI_PRINTK( "agtiapi_CheckError: pccb %p tiIOFailed - " + "tiDetailDifRefTagMismatch\n", pccb ); + ccb->ccb_h.status = CAM_REQ_CMP_ERR; + } + else if (pccb->scsiStatus == tiDetailDifCrcMismatch) + { + AGTIAPI_PRINTK( "agtiapi_CheckError: pccb %p tiIOFailed - " + "tiDetailDifCrcMismatch\n", pccb ); + ccb->ccb_h.status = CAM_REQ_CMP_ERR; + } + break; +#ifdef HIALEAH_ENCRYPTION + case tiIOEncryptError: + AGTIAPI_PRINTK( "agtiapi_CheckError: pccb %p tiIOFailed %d id %d ERROR\n", + pccb, pccb->scsiStatus, pccb->targetId ); + if (pccb->scsiStatus == tiDetailDekKeyCacheMiss) + { + AGTIAPI_PRINTK( "agtiapi_CheckError: %s: pccb %p tiIOFailed - " + "tiDetailDekKeyCacheMiss ERROR\n", + __FUNCTION__, pccb ); + ccb->ccb_h.status = CAM_REQ_ABORTED; + agtiapi_HandleEncryptedIOFailure(pDevice, pccb); + } + else if (pccb->scsiStatus == tiDetailDekIVMismatch) + { + AGTIAPI_PRINTK( "agtiapi_CheckError: %s: pccb %p tiIOFailed - " + "tiDetailDekIVMismatch ERROR\n", __FUNCTION__, pccb ); + ccb->ccb_h.status = CAM_REQ_ABORTED; + agtiapi_HandleEncryptedIOFailure(pDevice, pccb); + } + break; +#endif + default: + AGTIAPI_PRINTK( "agtiapi_CheckError: pccb %p tiIOdefault %d id %d ERROR\n", + pccb, pccb->ccbStatus, pccb->targetId ); + ccb->ccb_h.status = CAM_REQ_CMP_ERR; + break; + } + + return 1; +} + + +/****************************************************************************** +agtiapi_SMPCheckError() + +Purpose: + Processes status pertaining to the ccb -- whether it was + completed successfully, aborted, or error encountered. +Parameters: + ag_card_t *pCard (IN) Pointer to HBA data structure + ccb_t *pccd (IN) A pointer to the driver's own CCB, not CAM's CCB +Return: + 0 - the command retry is required + 1 - the command process is completed +Note: + +******************************************************************************/ +STATIC U32 agtiapi_CheckSMPError( struct agtiapi_softc *pmcsc, ccb_t *pccb ) +{ + union ccb * ccb = pccb->ccb; + + AGTIAPI_PRINTK("agtiapi_CheckSMPError: start\n"); + + if (!ccb) + { + /* shouldn't be here but just in case we do */ + AGTIAPI_PRINTK( "agtiapi_CheckSMPError: CCB orphan = %p ERROR\n", + pccb ); + agtiapi_FreeSMPCCB(pmcsc, pccb); + return 0; + } + + switch (pccb->ccbStatus) + { + case tiSMPSuccess: + AGTIAPI_PRINTK( "agtiapi_CheckSMPError: tiSMPSuccess pccb %p\n", + pccb ); + /* CAM status */ + ccb->ccb_h.status = CAM_REQ_CMP; + break; + case tiSMPFailed: + AGTIAPI_PRINTK( "agtiapi_CheckSMPError: tiSMPFailed pccb %p\n", + pccb ); + /* CAM status */ + ccb->ccb_h.status = CAM_REQ_CMP_ERR; + break; + default: + AGTIAPI_PRINTK( "agtiapi_CheckSMPError: pccb %p tiSMPdefault %d " + "id %d ERROR\n", + pccb, + pccb->ccbStatus, + pccb->targetId ); + ccb->ccb_h.status = CAM_REQ_CMP_ERR; + break; + } + + + return 1; + +} + +/****************************************************************************** +agtiapi_HandleEncryptedIOFailure(): + +Purpose: +Parameters: +Return: +Note: + Currently not used. +******************************************************************************/ +void agtiapi_HandleEncryptedIOFailure(ag_device_t *pDev, ccb_t *pccb) +{ + + AGTIAPI_PRINTK("agtiapi_HandleEncryptedIOFailure: start\n"); + return; +} + +/****************************************************************************** +agtiapi_Retry() + +Purpose: + Retry a ccb. +Parameters: + struct agtiapi_softc *pmcsc (IN) Pointer to the HBA structure + ccb_t *pccb (IN) A pointer to the driver's own CCB, not CAM's CCB +Return: +Note: + Currently not used. +******************************************************************************/ +STATIC void agtiapi_Retry(struct agtiapi_softc *pmcsc, ccb_t *pccb) +{ + pccb->retryCount++; + pccb->flags = ACTIVE | AGTIAPI_RETRY; + pccb->ccbStatus = 0; + pccb->scsiStatus = 0; + pccb->startTime = ticks; + + AGTIAPI_PRINTK( "agtiapi_Retry: start\n" ); + AGTIAPI_PRINTK( "agtiapi_Retry: ccb %p retry %d flgs x%x\n", pccb, + pccb->retryCount, pccb->flags ); + + agtiapi_QueueCCB(pmcsc, &pmcsc->ccbSendHead, &pmcsc->ccbSendTail + AG_CARD_LOCAL_LOCK(&pmcsc->sendLock), pccb); + return; +} + + +/****************************************************************************** +agtiapi_DumpCCB() + +Purpose: + Dump CCB for debuging +Parameters: + ccb_t *pccb (IN) A pointer to the driver's own CCB, not CAM's CCB +Return: +Note: +******************************************************************************/ +STATIC void agtiapi_DumpCCB(ccb_t *pccb) +{ + AGTIAPI_PRINTK("agtiapi_DumpCCB: pccb %p, devHandle %p, tid %d, lun %d\n", + pccb, + pccb->devHandle, + pccb->targetId, + pccb->lun); + AGTIAPI_PRINTK("flag 0x%x, add_mode 0x%x, ccbStatus 0x%x, scsiStatus 0x%x\n", + pccb->flags, + pccb->addrMode, + pccb->ccbStatus, + pccb->scsiStatus); + AGTIAPI_PRINTK("scsi comand = 0x%x, numSgElements = %d\n", + pccb->tiSuperScsiRequest.scsiCmnd.cdb[0], + pccb->numSgElements); + AGTIAPI_PRINTK("dataLen = 0x%x, sens_len = 0x%x\n", + pccb->dataLen, + pccb->senseLen); + AGTIAPI_PRINTK("tiSuperScsiRequest:\n"); + AGTIAPI_PRINTK("scsiCmnd: expDataLength 0x%x, taskAttribute 0x%x\n", + pccb->tiSuperScsiRequest.scsiCmnd.expDataLength, + pccb->tiSuperScsiRequest.scsiCmnd.taskAttribute); + AGTIAPI_PRINTK("cdb[0] = 0x%x, cdb[1] = 0x%x, cdb[2] = 0x%x, cdb[3] = 0x%x\n", + pccb->tiSuperScsiRequest.scsiCmnd.cdb[0], + pccb->tiSuperScsiRequest.scsiCmnd.cdb[1], + pccb->tiSuperScsiRequest.scsiCmnd.cdb[2], + pccb->tiSuperScsiRequest.scsiCmnd.cdb[3]); + AGTIAPI_PRINTK("cdb[4] = 0x%x, cdb[5] = 0x%x, cdb[6] = 0x%x, cdb[7] = 0x%x\n", + pccb->tiSuperScsiRequest.scsiCmnd.cdb[4], + pccb->tiSuperScsiRequest.scsiCmnd.cdb[5], + pccb->tiSuperScsiRequest.scsiCmnd.cdb[6], + pccb->tiSuperScsiRequest.scsiCmnd.cdb[7]); + AGTIAPI_PRINTK( "cdb[8] = 0x%x, cdb[9] = 0x%x, cdb[10] = 0x%x, " + "cdb[11] = 0x%x\n", + pccb->tiSuperScsiRequest.scsiCmnd.cdb[8], + pccb->tiSuperScsiRequest.scsiCmnd.cdb[9], + pccb->tiSuperScsiRequest.scsiCmnd.cdb[10], + pccb->tiSuperScsiRequest.scsiCmnd.cdb[11] ); + AGTIAPI_PRINTK("agSgl1: upper 0x%x, lower 0x%x, len 0x%x, type %d\n", + pccb->tiSuperScsiRequest.agSgl1.upper, + pccb->tiSuperScsiRequest.agSgl1.lower, + pccb->tiSuperScsiRequest.agSgl1.len, + pccb->tiSuperScsiRequest.agSgl1.type); +} + +/****************************************************************************** +agtiapi_eh_HostReset() + +Purpose: + A new error handler of Host Reset command. +Parameters: + scsi_cmnd *cmnd (IN) Pointer to a command to the HBA to be reset +Return: + SUCCESS - success + FAILED - fail +Note: +******************************************************************************/ +int agtiapi_eh_HostReset( struct agtiapi_softc *pmcsc, union ccb *cmnd ) +{ + AGTIAPI_PRINTK( "agtiapi_eh_HostReset: ccb pointer %p\n", + cmnd ); + + if( cmnd == NULL ) + { + printf( "agtiapi_eh_HostReset: null command, skipping reset.\n" ); + return tiInvalidHandle; + } + +#ifdef LOGEVENT + agtiapi_LogEvent( pmcsc, + IOCTL_EVT_SEV_INFORMATIONAL, + 0, + agNULL, + 0, + "agtiapi_eh_HostReset! " ); +#endif + + return agtiapi_DoSoftReset( pmcsc ); +} + + +int agtiapi_eh_DeviceReset( struct agtiapi_softc *pmcsc, union ccb *cmnd ) +{ + AGTIAPI_PRINTK( "agtiapi_eh_HostReset: ccb pointer %p\n", + cmnd ); + + if( cmnd == NULL ) + { + printf( "agtiapi_eh_HostReset: null command, skipping reset.\n" ); + return tiInvalidHandle; + } + return agtiapi_DoSoftReset( pmcsc ); +} +/****************************************************************************** +agtiapi_QueueCCB() + +Purpose: + Put ccb in ccb queue at the tail +Parameters: + struct agtiapi_softc *pmcsc (IN) Pointer to HBA data structure + pccb_t *phead (IN) Double pointer to ccb queue head + pccb_t *ptail (IN) Double pointer to ccb queue tail + ccb_t *pccb (IN) Poiner to a ccb to be queued +Return: +Note: + Put the ccb to the tail of queue +******************************************************************************/ +STATIC void agtiapi_QueueCCB( struct agtiapi_softc *pmcsc, + pccb_t *phead, + pccb_t *ptail, +#ifdef AGTIAPI_LOCAL_LOCK + struct mtx *mutex, +#endif + ccb_t *pccb ) +{ + AGTIAPI_IO( "agtiapi_QueueCCB: start\n" ); + AGTIAPI_IO( "agtiapi_QueueCCB: %p to %p\n", pccb, phead ); + if (phead == NULL || ptail == NULL) + { + panic( "agtiapi_QueueCCB: phead %p ptail %p", phead, ptail ); + } + pccb->pccbNext = NULL; + AG_LOCAL_LOCK( mutex ); + if (*phead == NULL) + { + //WARN_ON(*ptail != NULL); /* critical, just get more logs */ + *phead = pccb; + } + else + { + //WARN_ON(*ptail == NULL); /* critical, just get more logs */ + if (*ptail) + (*ptail)->pccbNext = pccb; + } + *ptail = pccb; + AG_LOCAL_UNLOCK( mutex ); + return; +} + + +/****************************************************************************** +agtiapi_QueueCCB() + +Purpose: + +Parameters: + + +Return: +Note: + +******************************************************************************/ +static int agtiapi_QueueSMP(struct agtiapi_softc *pmcsc, union ccb * ccb) +{ + pccb_t pccb = agNULL; /* call dequeue */ + int status = tiSuccess; + int targetID = xpt_path_target_id(ccb->ccb_h.path); + + AGTIAPI_PRINTK("agtiapi_QueueSMP: start\n"); + + /* get a ccb */ + if ((pccb = agtiapi_GetCCB(pmcsc)) == NULL) + { + AGTIAPI_PRINTK("agtiapi_QueueSMP: GetCCB ERROR\n"); + ccb->ccb_h.status = CAM_REQ_CMP; + xpt_done(ccb); + return tiBusy; + } + pccb->pmcsc = pmcsc; + + /* initialize Command Control Block (CCB) */ + pccb->targetId = targetID; + pccb->ccb = ccb; /* for struct scsi_cmnd */ + + status = agtiapi_PrepareSMPSGList(pmcsc, pccb); + + if (status != tiSuccess) + { + AGTIAPI_PRINTK("agtiapi_QueueSMP: agtiapi_PrepareSMPSGList failure\n"); + agtiapi_FreeCCB(pmcsc, pccb); + if (status == tiReject) + { + ccb->ccb_h.status = CAM_REQ_INVALID; + } + else + { + ccb->ccb_h.status = CAM_REQ_CMP; + } + xpt_done(ccb); + return tiError; + } + + return status; +} + +/****************************************************************************** +agtiapi_SetLunField() + +Purpose: + Set LUN field based on different address mode +Parameters: + ccb_t *pccb (IN) A pointer to the driver's own CCB, not CAM's CCB +Return: +Note: +******************************************************************************/ +void agtiapi_SetLunField(ccb_t *pccb) +{ + U08 *pchar; + + pchar = (U08 *)&pccb->tiSuperScsiRequest.scsiCmnd.lun; + +// AGTIAPI_PRINTK("agtiapi_SetLunField: start\n"); + + switch (pccb->addrMode) + { + case AGTIAPI_PERIPHERAL: + *pchar++ = 0; + *pchar = (U08)pccb->lun; + break; + case AGTIAPI_VOLUME_SET: + *pchar++ = (AGTIAPI_VOLUME_SET << AGTIAPI_ADDRMODE_SHIFT) | + (U08)((pccb->lun >> 8) & 0x3F); + *pchar = (U08)pccb->lun; + break; + case AGTIAPI_LUN_ADDR: + *pchar++ = (AGTIAPI_LUN_ADDR << AGTIAPI_ADDRMODE_SHIFT) | + pccb->targetId; + *pchar = (U08)pccb->lun; + break; + } + + +} + + +/***************************************************************************** +agtiapi_FreeCCB() + +Purpose: + Free a ccb and put it back to ccbFreeList. +Parameters: + struct agtiapi_softc *pmcsc (IN) Pointer to HBA data structure + pccb_t pccb (IN) A pointer to the driver's own CCB, not + CAM's CCB +Returns: +Note: +*****************************************************************************/ +STATIC void agtiapi_FreeCCB(struct agtiapi_softc *pmcsc, pccb_t pccb) +{ + union ccb *ccb = pccb->ccb; + bus_dmasync_op_t op; + + AG_LOCAL_LOCK(&pmcsc->ccbLock); + AGTIAPI_IO( "agtiapi_FreeCCB: start %p\n", pccb ); + +#ifdef AGTIAPI_TEST_EPL + tiEncrypt_t *encrypt; +#endif + + agtiapi_DumpCDB( "agtiapi_FreeCCB", pccb ); + + if (pccb->sgList != agNULL) + { + AGTIAPI_IO( "agtiapi_FreeCCB: pccb->sgList is NOT null\n" ); + } + else + { + AGTIAPI_PRINTK( "agtiapi_FreeCCB: pccb->sgList is null\n" ); + } + + /* set data transfer direction */ + if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) + { + op = BUS_DMASYNC_POSTWRITE; + } + else + { + op = BUS_DMASYNC_POSTREAD; + } + + if (pccb->numSgElements == 0) + { + // do nothing + AGTIAPI_IO( "agtiapi_FreeCCB: numSgElements zero\n" ); + } + else if (pccb->numSgElements == 1) + { + AGTIAPI_IO( "agtiapi_FreeCCB: numSgElements is one\n" ); + //op is either BUS_DMASYNC_POSTWRITE or BUS_DMASYNC_POSTREAD + bus_dmamap_sync(pmcsc->buffer_dmat, pccb->CCB_dmamap, op); + bus_dmamap_unload(pmcsc->buffer_dmat, pccb->CCB_dmamap); + } + else + { + AGTIAPI_PRINTK( "agtiapi_FreeCCB: numSgElements 2 or higher \n" ); + //op is either BUS_DMASYNC_POSTWRITE or BUS_DMASYNC_POSTREAD + bus_dmamap_sync(pmcsc->buffer_dmat, pccb->CCB_dmamap, op); + bus_dmamap_unload(pmcsc->buffer_dmat, pccb->CCB_dmamap); + } + +#ifdef AGTIAPI_TEST_DPL + if (pccb->tiSuperScsiRequest.Dif.enableDIFPerLA == TRUE) { + if(pccb->dplPtr) + memset( (char *) pccb->dplPtr, + 0, + MAX_DPL_REGIONS * sizeof(dplaRegion_t) ); + pccb->tiSuperScsiRequest.Dif.enableDIFPerLA = FALSE; + pccb->tiSuperScsiRequest.Dif.DIFPerLAAddrLo = 0; + pccb->tiSuperScsiRequest.Dif.DIFPerLAAddrHi = 0; + } +#endif + +#ifdef AGTIAPI_TEST_EPL + encrypt = &pccb->tiSuperScsiRequest.Encrypt; + if (encrypt->enableEncryptionPerLA == TRUE) { + encrypt->enableEncryptionPerLA = FALSE; + encrypt->EncryptionPerLAAddrLo = 0; + encrypt->EncryptionPerLAAddrHi = 0; + } +#endif + +#ifdef ENABLE_SATA_DIF + if (pccb->holePtr && pccb->dmaHandleHole) + pci_free_consistent( pmcsc->pCardInfo->pPCIDev, + 512, + pccb->holePtr, + pccb->dmaHandleHole ); + pccb->holePtr = 0; + pccb->dmaHandleHole = 0; +#endif + + pccb->dataLen = 0; + pccb->retryCount = 0; + pccb->ccbStatus = 0; + pccb->scsiStatus = 0; + pccb->startTime = 0; + pccb->dmaHandle = 0; + pccb->numSgElements = 0; + pccb->tiIORequest.tdData = 0; + memset((void *)&pccb->tiSuperScsiRequest, 0, AGSCSI_INIT_XCHG_LEN); + +#ifdef HIALEAH_ENCRYPTION + if (pmcsc->encrypt) + agtiapi_CleanupEncryptedIO(pmcsc, pccb); +#endif + + pccb->flags = 0; + pccb->ccb = NULL; + pccb->pccbIO = NULL; + pccb->pccbNext = (pccb_t)pmcsc->ccbFreeList; + pmcsc->ccbFreeList = (caddr_t *)pccb; + + pmcsc->activeCCB--; + + AG_LOCAL_UNLOCK(&pmcsc->ccbLock); + return; +} + + +/****************************************************************************** +agtiapi_FlushCCBs() + +Purpose: + Flush all in processed ccbs. +Parameters: + ag_card_t *pCard (IN) Pointer to HBA data structure + U32 flag (IN) Flag to call back +Return: +Note: +******************************************************************************/ +STATIC void agtiapi_FlushCCBs( struct agtiapi_softc *pCard, U32 flag ) +{ + union ccb *ccb; + ccb_t *pccb; + + AGTIAPI_PRINTK( "agtiapi_FlushCCBs: enter \n" ); + for( pccb = (pccb_t)pCard->ccbChainList; + pccb != NULL; + pccb = pccb->pccbChainNext ) { + if( pccb->flags == 0 ) + { + // printf( "agtiapi_FlushCCBs: nothing, continue \n" ); + continue; + } + ccb = pccb->ccb; + if ( pccb->flags & ( TASK_MANAGEMENT | DEV_RESET ) ) + { + AGTIAPI_PRINTK( "agtiapi_FlushCCBs: agtiapi_FreeTMCCB \n" ); + agtiapi_FreeTMCCB( pCard, pccb ); + } + else + { + if ( pccb->flags & TAG_SMP ) + { + AGTIAPI_PRINTK( "agtiapi_FlushCCBs: agtiapi_FreeSMPCCB \n" ); + agtiapi_FreeSMPCCB( pCard, pccb ); + } + else + { + AGTIAPI_PRINTK( "agtiapi_FlushCCBs: agtiapi_FreeCCB \n" ); + agtiapi_FreeCCB( pCard, pccb ); + } + if( ccb ) { + CMND_DMA_UNMAP( pCard, ccb ); + if( flag == AGTIAPI_CALLBACK ) { + ccb->ccb_h.status = CAM_SCSI_BUS_RESET; + xpt_done( ccb ); + } + } + } + } +} + +/***************************************************************************** +agtiapi_FreeSMPCCB() + +Purpose: + Free a ccb and put it back to ccbFreeList. +Parameters: + struct agtiapi_softc *pmcsc (IN) Pointer to HBA data structure + pccb_t pccb (IN) A pointer to the driver's own CCB, not + CAM's CCB +Returns: +Note: +*****************************************************************************/ +STATIC void agtiapi_FreeSMPCCB(struct agtiapi_softc *pmcsc, pccb_t pccb) +{ + union ccb *ccb = pccb->ccb; + bus_dmasync_op_t op; + + AG_LOCAL_LOCK(&pmcsc->ccbLock); + AGTIAPI_PRINTK("agtiapi_FreeSMPCCB: start %p\n", pccb); + + /* set data transfer direction */ + if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) + { + op = BUS_DMASYNC_POSTWRITE; + } + else + { + op = BUS_DMASYNC_POSTREAD; + } + + if (pccb->numSgElements == 0) + { + // do nothing + AGTIAPI_PRINTK("agtiapi_FreeSMPCCB: numSgElements 0\n"); + } + else if (pccb->numSgElements == 1) + { + AGTIAPI_PRINTK("agtiapi_FreeSMPCCB: numSgElements 1\n"); + //op is either BUS_DMASYNC_POSTWRITE or BUS_DMASYNC_POSTREAD + bus_dmamap_sync(pmcsc->buffer_dmat, pccb->CCB_dmamap, op); + bus_dmamap_unload(pmcsc->buffer_dmat, pccb->CCB_dmamap); + } + else + { + AGTIAPI_PRINTK("agtiapi_FreeSMPCCB: numSgElements 2 or higher \n"); + //op is either BUS_DMASYNC_POSTWRITE or BUS_DMASYNC_POSTREAD + bus_dmamap_sync(pmcsc->buffer_dmat, pccb->CCB_dmamap, op); + bus_dmamap_unload(pmcsc->buffer_dmat, pccb->CCB_dmamap); + } + + /*dma api cleanning*/ + pccb->dataLen = 0; + pccb->retryCount = 0; + pccb->ccbStatus = 0; + pccb->startTime = 0; + pccb->dmaHandle = 0; + pccb->numSgElements = 0; + pccb->tiIORequest.tdData = 0; + memset((void *)&pccb->tiSMPFrame, 0, AGSMP_INIT_XCHG_LEN); + + pccb->flags = 0; + pccb->ccb = NULL; + pccb->pccbNext = (pccb_t)pmcsc->ccbFreeList; + pmcsc->ccbFreeList = (caddr_t *)pccb; + + pmcsc->activeCCB--; + + AG_LOCAL_UNLOCK(&pmcsc->ccbLock); + return; + +} + +/***************************************************************************** +agtiapi_FreeTMCCB() + +Purpose: + Free a ccb and put it back to ccbFreeList. +Parameters: + struct agtiapi_softc *pmcsc (IN) Pointer to HBA data structure + pccb_t pccb (IN) A pointer to the driver's own CCB, not + CAM's CCB +Returns: +Note: +*****************************************************************************/ +STATIC void agtiapi_FreeTMCCB(struct agtiapi_softc *pmcsc, pccb_t pccb) +{ + AG_LOCAL_LOCK(&pmcsc->ccbLock); + AGTIAPI_PRINTK("agtiapi_FreeTMCCB: start %p\n", pccb); + pccb->dataLen = 0; + pccb->retryCount = 0; + pccb->ccbStatus = 0; + pccb->scsiStatus = 0; + pccb->startTime = 0; + pccb->dmaHandle = 0; + pccb->numSgElements = 0; + pccb->tiIORequest.tdData = 0; + memset((void *)&pccb->tiSuperScsiRequest, 0, AGSCSI_INIT_XCHG_LEN); + pccb->flags = 0; + pccb->ccb = NULL; + pccb->pccbIO = NULL; + pccb->pccbNext = (pccb_t)pmcsc->ccbFreeList; + pmcsc->ccbFreeList = (caddr_t *)pccb; + pmcsc->activeCCB--; + AG_LOCAL_UNLOCK(&pmcsc->ccbLock); + return; +} +/****************************************************************************** +agtiapi_CheckAllVectors(): + +Purpose: +Parameters: +Return: +Note: + Currently, not used. +******************************************************************************/ +void agtiapi_CheckAllVectors( struct agtiapi_softc *pCard, bit32 context ) +{ +#ifdef SPC_MSIX_INTR + if (!agtiapi_intx_mode) + { + int i; + + for (i = 0; i < pCard->pCardInfo->maxInterruptVectors; i++) + if (tiCOMInterruptHandler(&pCard->tiRoot, i) == agTRUE) + tiCOMDelayedInterruptHandler(&pCard->tiRoot, i, 100, context); + } + else + if (tiCOMInterruptHandler(&pCard->tiRoot, 0) == agTRUE) + tiCOMDelayedInterruptHandler(&pCard->tiRoot, 0, 100, context); +#else + if (tiCOMInterruptHandler(&pCard->tiRoot, 0) == agTRUE) + tiCOMDelayedInterruptHandler(&pCard->tiRoot, 0, 100, context); +#endif + +} + + +/****************************************************************************** +agtiapi_CheckCB() + +Purpose: + Check call back function returned event for process completion +Parameters: + struct agtiapi_softc *pCard Pointer to card data structure + U32 milisec (IN) Waiting time for expected event + U32 flag (IN) Flag of the event to check + U32 *pStatus (IN) Pointer to status of the card or port to check +Return: + AGTIAPI_SUCCESS - event comes as expected + AGTIAPI_FAIL - event not coming +Note: + Currently, not used +******************************************************************************/ +agBOOLEAN agtiapi_CheckCB( struct agtiapi_softc *pCard, + U32 milisec, + U32 flag, + volatile U32 *pStatus ) +{ + U32 msecsPerTick = pCard->pCardInfo->tiRscInfo.tiInitiatorResource. + initiatorOption.usecsPerTick / 1000; + S32 i = milisec/msecsPerTick; + AG_GLOBAL_ARG( _flags ); + + AGTIAPI_PRINTK( "agtiapi_CheckCB: start\n" ); + AGTIAPI_FLOW( "agtiapi_CheckCB: start\n" ); + + if( i <= 0 ) + i = 1; + while (i > 0) + { + if (*pStatus & TASK_MANAGEMENT) + { + if (*pStatus & AGTIAPI_CB_DONE) + { + if( flag == 0 || *pStatus & flag ) + return AGTIAPI_SUCCESS; + else + return AGTIAPI_FAIL; + } + } + else if (pCard->flags & AGTIAPI_CB_DONE) + { + if( flag == 0 || *pStatus & flag ) + return AGTIAPI_SUCCESS; + else + return AGTIAPI_FAIL; + } + + agtiapi_DelayMSec( msecsPerTick ); + + AG_SPIN_LOCK_IRQ( agtiapi_host_lock, _flags ); + tiCOMTimerTick( &pCard->tiRoot ); + + agtiapi_CheckAllVectors( pCard, tiNonInterruptContext ); + AG_SPIN_UNLOCK_IRQ( agtiapi_host_lock, _flags ); + + i--; + } + + if( *pStatus & TASK_MANAGEMENT ) + *pStatus |= TASK_TIMEOUT; + + return AGTIAPI_FAIL; +} + + +/****************************************************************************** +agtiapi_DiscoverTgt() + +Purpose: + Discover available devices +Parameters: + struct agtiapi_softc *pCard (IN) Pointer to the HBA data structure +Return: +Note: +******************************************************************************/ +STATIC void agtiapi_DiscoverTgt(struct agtiapi_softc *pCard) +{ + + ag_portal_data_t *pPortalData; + U32 count; + + AGTIAPI_PRINTK("agtiapi_DiscoverTgt: start\n"); + AGTIAPI_FLOW("agtiapi_DiscoverTgt\n"); + AGTIAPI_INIT("agtiapi_DiscoverTgt\n"); + + pPortalData = pCard->pPortalData; + for (count = 0; count < pCard->portCount; count++, pPortalData++) + { + pCard->flags &= ~AGTIAPI_CB_DONE; + if (!(PORTAL_STATUS(pPortalData) & AGTIAPI_PORT_DISC_READY)) + { + if (pCard->flags & AGTIAPI_INIT_TIME) + { + if (agtiapi_CheckCB(pCard, 5000, AGTIAPI_PORT_DISC_READY, + &PORTAL_STATUS(pPortalData)) == AGTIAPI_FAIL) + { + AGTIAPI_PRINTK( "agtiapi_DiscoverTgt: Port %p / %d not ready for " + "discovery\n", + pPortalData, count ); + /* + * There is no need to spend time on discovering device + * if port is not ready to do so. + */ + continue; + } + } + else + continue; + } + + AGTIAPI_FLOW( "agtiapi_DiscoverTgt: Portal %p DiscoverTargets starts\n", + pPortalData ); + AGTIAPI_INIT_DELAY(1000); + + pCard->flags &= ~AGTIAPI_CB_DONE; + if (tiINIDiscoverTargets(&pCard->tiRoot, + &pPortalData->portalInfo.tiPortalContext, + FORCE_PERSISTENT_ASSIGN_MASK) + != tiSuccess) + AGTIAPI_PRINTK("agtiapi_DiscoverTgt: tiINIDiscoverTargets ERROR\n"); + + /* + * Should wait till discovery completion to start + * next portal. However, lower layer have issue on + * multi-portal case under Linux. + */ + } + + pPortalData = pCard->pPortalData; + for (count = 0; count < pCard->portCount; count++, pPortalData++) + { + if ((PORTAL_STATUS(pPortalData) & AGTIAPI_PORT_DISC_READY)) + { + if (agtiapi_CheckCB(pCard, 20000, AGTIAPI_DISC_COMPLETE, + &PORTAL_STATUS(pPortalData)) == AGTIAPI_FAIL) + { + if ((PORTAL_STATUS(pPortalData) & AGTIAPI_DISC_COMPLETE)) + AGTIAPI_PRINTK( "agtiapi_DiscoverTgt: Portal %p discover complete, " + "status 0x%x\n", + pPortalData, + PORTAL_STATUS(pPortalData) ); + else + AGTIAPI_PRINTK( "agtiapi_DiscoverTgt: Portal %p discover is not " + "completed, status 0x%x\n", + pPortalData, PORTAL_STATUS(pPortalData) ); + continue; + } + AGTIAPI_PRINTK( "agtiapi_DiscoverTgt: Portal %d discover target " + "success\n", + count ); + } + } + + /* + * Calling to get device handle should be done per portal based + * and better right after discovery is done. However, lower iscsi + * layer may not returns discovery complete in correct sequence or we + * ran out time. We get device handle for all portals together + * after discovery is done or timed out. + */ + pPortalData = pCard->pPortalData; + for (count = 0; count < pCard->portCount; count++, pPortalData++) + { + /* + * We try to get device handle no matter + * if discovery is completed or not. + */ + if (PORTAL_STATUS(pPortalData) & AGTIAPI_PORT_DISC_READY) + { + U32 i; + + for (i = 0; i < AGTIAPI_GET_DEV_MAX; i++) + { + if (agtiapi_GetDevHandle(pCard, &pPortalData->portalInfo, 0, 0) != 0) + break; + agtiapi_DelayMSec(AGTIAPI_EXTRA_DELAY); + } + + if ((PORTAL_STATUS(pPortalData) & AGTIAPI_DISC_COMPLETE) || + (pCard->tgtCount > 0)) + PORTAL_STATUS(pPortalData) |= ( AGTIAPI_DISC_DONE | + AGTIAPI_PORT_LINK_UP ); + } + } + + return; + +} + + + +/****************************************************************************** +agtiapi_PrepCCBs() + +Purpose: + Prepares CCB including DMA map. +Parameters: + struct agtiapi_softc *pCard (IN) Pointer to the HBA data structure + ccb_hdr_t *hdr (IN) Pointer to the CCB header + U32 size (IN) size + U32 max_ccb (IN) count + +Return: +Note: +******************************************************************************/ +STATIC void agtiapi_PrepCCBs( struct agtiapi_softc *pCard, + ccb_hdr_t *hdr, + U32 size, + U32 max_ccb, + int tid ) +{ + + int i; + U32 hdr_sz, ccb_sz; + ccb_t *pccb = 0; + int offset = 0; + int nsegs = 0; + int sgl_sz = 0; + + AGTIAPI_PRINTK("agtiapi_PrepCCBs: start\n"); + offset = tid * AGTIAPI_CCB_PER_DEVICE; + nsegs = AGTIAPI_NSEGS; + sgl_sz = sizeof(tiSgl_t) * nsegs; + AGTIAPI_PRINTK( "agtiapi_PrepCCBs: tid %d offset %d nsegs %d sizeof(tiSgl_t) " + "%lu, max_ccb %d\n", + tid, + offset, + nsegs, + sizeof(tiSgl_t), + max_ccb ); + + ccb_sz = (AGTIAPI_CCB_SIZE + cache_line_size() - 1) & ~(cache_line_size() -1); + hdr_sz = (sizeof(*hdr) + cache_line_size() - 1) & ~(cache_line_size() - 1); + + AGTIAPI_PRINTK("agtiapi_PrepCCBs: after cache line\n"); + + memset((void *)hdr, 0, size); + hdr->next = pCard->ccbAllocList; + pCard->ccbAllocList = hdr; + + AGTIAPI_PRINTK("agtiapi_PrepCCBs: after memset\n"); + + pccb = (ccb_t*) ((char*)hdr + hdr_sz); + + for (i = 0; i < max_ccb; i++, pccb = (ccb_t*)((char*)pccb + ccb_sz)) + { + pccb->tiIORequest.osData = (void *)pccb; + + /* + * Initially put all the ccbs on the free list + * in addition to chainlist. + * ccbChainList is a list of all available ccbs + * (free/active everything) + */ + pccb->pccbChainNext = (pccb_t)pCard->ccbChainList; + pccb->pccbNext = (pccb_t)pCard->ccbFreeList; + + pCard->ccbChainList = (caddr_t *)pccb; + pCard->ccbFreeList = (caddr_t *)pccb; + pCard->ccbTotal++; + +#ifdef AGTIAPI_ALIGN_CHECK + if (&pccb & 0x63) + AGTIAPI_PRINTK("pccb = %p\n", pccb); + if (pccb->devHandle & 0x63) + AGTIAPI_PRINTK("devHandle addr = %p\n", &pccb->devHandle); + if (&pccb->lun & 0x63) + AGTIAPI_PRINTK("lun addr = %p\n", &pccb->lun); + if (&pccb->targetId & 0x63) + AGTIAPI_PRINTK("tig addr = %p\n", &pccb->targetId); + if (&pccb->ccbStatus & 0x63) + AGTIAPI_PRINTK("ccbStatus addr = %p\n", &pccb->ccbStatus); + if (&pccb->scsiStatus & 0x63) + AGTIAPI_PRINTK("scsiStatus addr = %p\n", &pccb->scsiStatus); + if (&pccb->dataLen & 0x63) + AGTIAPI_PRINTK("dataLen addr = %p\n", &pccb->dataLen); + if (&pccb->senseLen & 0x63) + AGTIAPI_PRINTK("senseLen addr = %p\n", &pccb->senseLen); + if (&pccb->numSgElements & 0x63) + AGTIAPI_PRINTK("numSgElements addr = %p\n", &pccb->numSgElements); + if (&pccb->retryCount & 0x63) + AGTIAPI_PRINTK("retry cnt addr = %p\n", &pccb->retryCount); + if (&pccb->flags & 0x63) + AGTIAPI_PRINTK("flag addr = %p\n", &pccb->flags); + if (&pccb->pSenseData & 0x63) + AGTIAPI_PRINTK("senseData addr = %p\n", &pccb->pSenseData); + if (&pccb->sgList[0] & 0x63) + AGTIAPI_PRINTK("SgList 0 = %p\n", &pccb->sgList[0]); + if (&pccb->pccbNext & 0x63) + AGTIAPI_PRINTK("ccb next = %p\n", &pccb->pccbNext); + if (&pccb->pccbChainNext & 0x63) + AGTIAPI_PRINTK("ccbChainNext = %p\n", &pccb->pccbChainNext); + if (&pccb->cmd & 0x63) + AGTIAPI_PRINTK("command = %p\n", &pccb->cmd); + if( &pccb->startTime & 0x63 ) + AGTIAPI_PRINTK( "startTime = %p\n", &pccb->startTime ); + if (&pccb->tiIORequest & 0x63) + AGTIAPI_PRINTK("tiIOReq addr = %p\n", &pccb->tiIORequest); + if (&pccb->tdIOReqBody & 0x63) + AGTIAPI_PRINTK("tdIORequestBody addr = %p\n", &pccb->tdIOReqBody); + if (&pccb->tiSuperScsiRequest & 0x63) + AGTIAPI_PRINTK( "InitiatorExchange addr = %p\n", + &pccb->tiSuperScsiRequest ); +#endif + if ( bus_dmamap_create( pCard->buffer_dmat, 0, &pccb->CCB_dmamap ) != + tiSuccess) + { + AGTIAPI_PRINTK("agtiapi_PrepCCBs: can't create dma\n"); + return; + } + /* assigns tiSgl_t memory to pccb */ + pccb->sgList = (void*)((U64)pCard->tisgl_mem + ((i + offset) * sgl_sz)); + pccb->tisgl_busaddr = pCard->tisgl_busaddr + ((i + offset) * sgl_sz); + pccb->ccb = NULL; + pccb->pccbIO = NULL; + pccb->startTime = 0; + } + +#ifdef AGTIAPI_ALIGN_CHECK + AGTIAPI_PRINTK("ccb size = %d / %d\n", sizeof(ccb_t), ccb_sz); +#endif + return; +} + +/****************************************************************************** +agtiapi_InitCCBs() + +Purpose: + Create and initialize per card based CCB pool. +Parameters: + struct agtiapi_softc *pCard (IN) Pointer to the HBA data structure + int tgtCount (IN) Count +Return: + Total number of ccb allocated +Note: +******************************************************************************/ +STATIC U32 agtiapi_InitCCBs(struct agtiapi_softc *pCard, int tgtCount, int tid) +{ + + U32 max_ccb, size, ccb_sz, hdr_sz; + int no_allocs = 0, i; + ccb_hdr_t *hdr = 0; + + AGTIAPI_PRINTK("agtiapi_InitCCBs: start\n"); + AGTIAPI_PRINTK("agtiapi_InitCCBs: tgtCount %d tid %d\n", tgtCount, tid); + AGTIAPI_FLOW("agtiapi_InitCCBs: tgtCount %d tid %d\n", tgtCount, tid); + +#ifndef HOTPLUG_SUPPORT + if (pCard->tgtCount > AGSA_MAX_INBOUND_Q) + return 1; +#else + if (tgtCount > AGSA_MAX_INBOUND_Q) + tgtCount = AGSA_MAX_INBOUND_Q; +#endif + + max_ccb = tgtCount * AGTIAPI_CCB_PER_DEVICE;// / 4; // TBR + ccb_sz = ( (AGTIAPI_CCB_SIZE + cache_line_size() - 1) & + ~(cache_line_size() -1) ); + hdr_sz = (sizeof(*hdr) + cache_line_size() - 1) & ~(cache_line_size() - 1); + size = ccb_sz * max_ccb + hdr_sz; + + for (i = 0; i < (1 << no_allocs); i++) + { + hdr = (ccb_hdr_t*)malloc( size, M_PMC_MCCB, M_NOWAIT ); + if( !hdr ) + { + panic( "agtiapi_InitCCBs: bug!!!\n" ); + } + else + { + agtiapi_PrepCCBs( pCard, hdr, size, max_ccb, tid ); + } + } + + return 1; + +} + + +#ifdef LINUX_PERBI_SUPPORT +/****************************************************************************** +agtiapi_GetWWNMappings() + +Purpose: + Get the mappings from target IDs to WWNs, if any. + Store them in the WWN_list array, indexed by target ID. + Leave the devListIndex field blank; this will be filled-in later. +Parameters: + ag_card_t *pCard (IN) Pointer to HBA data structure + ag_mapping_t *pMapList (IN) Pointer to mapped device list +Return: +Note: The boot command line parameters are used to load the + mapping information, which is contained in the system + configuration file. +******************************************************************************/ +STATIC void agtiapi_GetWWNMappings( struct agtiapi_softc *pCard, + ag_mapping_t *pMapList ) +{ + int devDisc; + int lIdx = 0; + ag_tgt_map_t *pWWNList; + ag_slr_map_t *pSLRList; + ag_device_t *pDevList; + + if( !pCard ) + panic( "agtiapi_GetWWNMappings: no pCard \n" ); + + AGTIAPI_PRINTK( "agtiapi_GetWWNMappings: start\n" ); + + pWWNList = pCard->pWWNList; + pSLRList = pCard->pSLRList; + pDevList = pCard->pDevList; + pCard->numTgtHardMapped = 0; + devDisc = pCard->devDiscover; + + pWWNList[devDisc-1].devListIndex = maxTargets; + pSLRList[devDisc-1].localeNameLen = -2; + pSLRList[devDisc-1].remoteNameLen = -2; + pDevList[devDisc-1].targetId = maxTargets; + + /* + * Get the mappings from holding area which contains + * the input of the system file and store them + * in the WWN_list array, indexed by target ID. + */ + for ( lIdx = 0; lIdx < devDisc - 1; lIdx++) { + pWWNList[lIdx].flags = 0; + pWWNList[lIdx].devListIndex = maxTargets; + pSLRList[lIdx].localeNameLen = -1; + pSLRList[lIdx].remoteNameLen = -1; + } + + // this is where we would propagate values fed to pMapList + +} /* agtiapi_GetWWNMappings */ + +#endif + + +/****************************************************************************** +agtiapi_FindWWNListNext() +Purpose: + finds first available new (unused) wwn list entry + +Parameters: + ag_tgt_map_t *pWWNList Pointer to head of wwn list + int lstMax Number of entries in WWNList +Return: + index into WWNList indicating available entry space; + if available entry space is not found, return negative value +******************************************************************************/ +STATIC int agtiapi_FindWWNListNext( ag_tgt_map_t *pWWNList, int lstMax ) +{ + int lLstIdx; + + for ( lLstIdx = 0; lLstIdx < lstMax; lLstIdx++ ) + { + if ( pWWNList[lLstIdx].devListIndex == lstMax && + pWWNList[lLstIdx].targetLen == 0 ) + { + AGTIAPI_PRINTK( "agtiapi_FindWWNListNext: %d %d %d %d v. %d\n", + lLstIdx, + pWWNList[lLstIdx].devListIndex, + pWWNList[lLstIdx].targetLen, + pWWNList[lLstIdx].portId, + lstMax ); + return lLstIdx; + } + } + return -1; +} + + +/****************************************************************************** +agtiapi_GetDevHandle() + +Purpose: + Get device handle. Handles will be placed in the + devlist array with same order as TargetList provided and + will be mapped to a scsi target id and registered to OS later. +Parameters: + struct agtiapi_softc *pCard (IN) Pointer to the HBA data structure + ag_portal_info_t *pPortalInfo (IN) Pointer to the portal data structure + U32 eType (IN) Port event + U32 eStatus (IN) Port event status +Return: + Number of device handle slot present +Note: + The sequence of device handle will match the sequence of taregt list +******************************************************************************/ +STATIC U32 agtiapi_GetDevHandle( struct agtiapi_softc *pCard, + ag_portal_info_t *pPortalInfo, + U32 eType, + U32 eStatus ) +{ + ag_device_t *pDevice; + // tiDeviceHandle_t *agDev[pCard->devDiscover]; + tiDeviceHandle_t **agDev; + int devIdx, szdv, devTotal, cmpsetRtn; + int lDevIndex = 0, lRunScanFlag = FALSE; + int *lDevFlags; + tiPortInfo_t portInfT; + ag_device_t lTmpDevice; + ag_tgt_map_t *pWWNList; + ag_slr_map_t *pSLRList; + bit32 lReadRm; + bit16 lReadCt; + + + AGTIAPI_PRINTK( "agtiapi_GetDevHandle: start\n" ); + AGTIAPI_PRINTK( "agtiapi_GetDevHandle: pCard->devDiscover %d / tgtCt %d\n", + pCard->devDiscover, pCard->tgtCount ); + AGTIAPI_FLOW( "agtiapi_GetDevHandle: portalInfo %p\n", pPortalInfo ); + AGTIAPI_INIT_DELAY( 1000 ); + + agDev = (tiDeviceHandle_t **) malloc( sizeof(tiDeviceHandle_t *) * pCard->devDiscover, + M_PMC_MDEV, M_ZERO | M_NOWAIT); + if (agDev == NULL) + { + AGTIAPI_PRINTK( "agtiapi_GetDevHandle: failed to alloc agDev[]\n" ); + return 0; + } + + lDevFlags = (int *) malloc( sizeof(int) * pCard->devDiscover, + M_PMC_MFLG, M_ZERO | M_NOWAIT ); + if (lDevFlags == NULL) + { + free((caddr_t)agDev, M_PMC_MDEV); + AGTIAPI_PRINTK( "agtiapi_GetDevHandle: failed to alloc lDevFlags[]\n" ); + return 0; + } + + pWWNList = pCard->pWWNList; + pSLRList = pCard->pSLRList; + + memset( (void *)agDev, 0, sizeof(void *) * pCard->devDiscover ); + memset( lDevFlags, 0, sizeof(int) * pCard->devDiscover ); + + // get device handles + devTotal = tiINIGetDeviceHandles( &pCard->tiRoot, + &pPortalInfo->tiPortalContext, + (tiDeviceHandle_t **)agDev, + pCard->devDiscover ); + + AGTIAPI_PRINTK( "agtiapi_GetDevHandle: portalInfo %p port id %d event %u " + "status %u card %p pCard->devDiscover %d devTotal %d " + "pPortalInfo->devTotal %d pPortalInfo->devPrev %d " + "AGTIAPI_INIT_TIME %x\n", + pPortalInfo, pPortalInfo->portID, eType, eStatus, pCard, + pCard->devDiscover, devTotal, pPortalInfo->devTotal, + pPortalInfo->devPrev, + pCard->flags & AGTIAPI_INIT_TIME ); + + // reset devTotal from any previous runs of this + pPortalInfo->devPrev = devTotal; + pPortalInfo->devTotal = devTotal; + + AG_LIST_LOCK( &pCard->devListLock ); + + if ( tiCOMGetPortInfo( &pCard->tiRoot, + &pPortalInfo->tiPortalContext, + &portInfT ) + != tiSuccess) + { + AGTIAPI_PRINTK( "agtiapi_GetDevHandle: tiCOMGetPortInfo did not succeed. \n" ); + } + + + szdv = sizeof( pPortalInfo->pDevList ) / sizeof( pPortalInfo->pDevList[0] ); + if (szdv > pCard->devDiscover) + { + szdv = pCard->devDiscover; + } + + // reconstructing dev list via comparison of wwn + + for ( devIdx = 0; devIdx < pCard->devDiscover; devIdx++ ) + { + if ( agDev[devIdx] != 0 ) + { + // AGTIAPI_PRINTK( "agtiapi_GetDevHandle: agDev %d not NULL %p\n", + // devIdx, agDev[devIdx] ); + + // pack temp device structure for tiINIGetDeviceInfo call + pDevice = &lTmpDevice; + pDevice->devType = DIRECT_DEVICE; + pDevice->pCard = (void *)pCard; + pDevice->flags = ACTIVE; + pDevice->pPortalInfo = pPortalInfo; + pDevice->pDevHandle = agDev[devIdx]; + pDevice->qbusy = agFALSE; + + //AGTIAPI_PRINTK( "agtiapi_GetDevHandle: idx %d / %d : %p \n", + // devIdx, pCard->devDiscover, agDev[devIdx] ); + + tiINIGetDeviceInfo( &pCard->tiRoot, agDev[devIdx], + &pDevice->devInfo ); + + //AGTIAPI_PRINTK( "agtiapi_GetDevHandle: wwn sizes %ld %d/%d ", + // sizeof(pDevice->targetName), + // pDevice->devInfo.osAddress1, + // pDevice->devInfo.osAddress2 ); + + wwncpy( pDevice ); + wwnprintk( (unsigned char*)pDevice->targetName, pDevice->targetLen ); + + for ( lDevIndex = 0; lDevIndex < szdv; lDevIndex++ ) // match w/ wwn list + { + if ( (pCard->pDevList[lDevIndex].portalId == pPortalInfo->portID) && + pDevice->targetLen > 0 && + portInfT.localNameLen > 0 && + portInfT.remoteNameLen > 0 && + pSLRList[pWWNList[lDevIndex].sasLrIdx].localeNameLen > 0 && + pSLRList[pWWNList[lDevIndex].sasLrIdx].remoteNameLen > 0 && + ( portInfT.localNameLen == + pSLRList[pWWNList[lDevIndex].sasLrIdx].localeNameLen ) && + ( portInfT.remoteNameLen == + pSLRList[pWWNList[lDevIndex].sasLrIdx].remoteNameLen ) && + memcmp( pWWNList[lDevIndex].targetName, pDevice->targetName, + pDevice->targetLen ) == 0 && + memcmp( pSLRList[pWWNList[lDevIndex].sasLrIdx].localeName, + portInfT.localName, + portInfT.localNameLen ) == 0 && + memcmp( pSLRList[pWWNList[lDevIndex].sasLrIdx].remoteName, + portInfT.remoteName, + portInfT.remoteNameLen ) == 0 ) + { + AGTIAPI_PRINTK( " pWWNList match @ %d/%d/%d \n", + lDevIndex, devIdx, pPortalInfo->portID ); + + if ( (pCard->pDevList[lDevIndex].targetId == lDevIndex) && + ( pPortalInfo->pDevList[lDevIndex] == + &pCard->pDevList[lDevIndex] ) ) // active + { + + AGTIAPI_PRINTK( "agtiapi_GetDevHandle: dev in use %d of %d/%d\n", + lDevIndex, devTotal, pPortalInfo->portID ); + lDevFlags[devIdx] |= DPMC_LEANFLAG_AGDEVUSED; // agDev handle + lDevFlags[lDevIndex] |= DPMC_LEANFLAG_PDEVSUSED; // pDevice used + lReadRm = atomic_readandclear_32( &pWWNList[lDevIndex].devRemoved ); + if ( lReadRm ) // cleared timeout, now remove count for timer + { + AGTIAPI_PRINTK( "agtiapi_GetDevHandle: clear timer count for" + " %d of %d\n", + lDevIndex, pPortalInfo->portID ); + atomic_subtract_16( &pCard->rmChkCt, 1 ); + lReadCt = atomic_load_acq_16( &pCard->rmChkCt ); + if ( 0 == lReadCt ) + { + callout_stop( &pCard->devRmTimer ); + } + } + break; + } + + AGTIAPI_PRINTK( "agtiapi_GetDevHandle: goin fresh on %d of %d/%d\n", + lDevIndex, // reactivate now + devTotal, pPortalInfo->portID ); + + // pDevice going fresh + lRunScanFlag = TRUE; // scan and clear outstanding removals + + // pCard->tgtCount++; ## + pDevice->targetId = lDevIndex; + pDevice->portalId = pPortalInfo->portID; + + memcpy ( &pCard->pDevList[lDevIndex], pDevice, sizeof(lTmpDevice) ); + agDev[devIdx]->osData = (void *)&pCard->pDevList[lDevIndex]; + if ( agtiapi_InitCCBs( pCard, 1, pDevice->targetId ) == 0 ) + { + AGTIAPI_PRINTK( "agtiapi_GetDevHandle: InitCCB " + "tgtCnt %d ERROR!\n", pCard->tgtCount ); + AG_LIST_UNLOCK( &pCard->devListLock ); + free((caddr_t)lDevFlags, M_PMC_MFLG); + free((caddr_t)agDev, M_PMC_MDEV); + return 0; + } + pPortalInfo->pDevList[lDevIndex] = &pCard->pDevList[lDevIndex]; // (ag_device_t *) + if ( 0 == lDevFlags[devIdx] ) + { + pPortalInfo->devTotal++; + lDevFlags[devIdx] |= DPMC_LEANFLAG_AGDEVUSED; // agDev used + lDevFlags[lDevIndex] |= DPMC_LEANFLAG_PDEVSUSED; // pDevice used + } + else + { + AGTIAPI_PRINTK( "agtiapi_GetDevHandle: odd dev handle " + "status inspect %d %d %d\n", + lDevFlags[devIdx], devIdx, lDevIndex ); + pPortalInfo->devTotal++; + lDevFlags[devIdx] |= DPMC_LEANFLAG_AGDEVUSED; // agDev used + lDevFlags[lDevIndex] |= DPMC_LEANFLAG_PDEVSUSED; // pDevice used + + } + break; + } + } + // end: match this wwn with previous wwn list + + // we have an agDev entry, but no pWWNList target for it + if ( !(lDevFlags[devIdx] & DPMC_LEANFLAG_AGDEVUSED) ) + { // flag dev handle not accounted for yet + lDevFlags[devIdx] |= DPMC_LEANFLAG_NOWWNLIST; + // later, get an empty pDevice and map this agDev. + // AGTIAPI_PRINTK( "agtiapi_GetDevHandle: devIdx %d flags 0x%x, %d\n", + // devIdx, lDevFlags[devIdx], (lDevFlags[devIdx] & 8) ); + } + } + else + { + lDevFlags[devIdx] |= DPMC_LEANFLAG_NOAGDEVYT; // known empty agDev handle + } + } + + // AGTIAPI_PRINTK( "agtiapi_GetDevHandle: all WWN all the time, " + // "devLstIdx/flags/(WWNL)portId ... \n" ); + // review device list for further action needed + for ( devIdx = 0; devIdx < pCard->devDiscover; devIdx++ ) + { + if ( lDevFlags[devIdx] & DPMC_LEANFLAG_NOWWNLIST ) // new target, register + { + int lNextDyad; // find next available dyad entry + + AGTIAPI_PRINTK( "agtiapi_GetDevHandle: register new target, " + "devIdx %d -- %d \n", devIdx, pCard->devDiscover ); + lRunScanFlag = TRUE; // scan and clear outstanding removals + for ( lNextDyad = 0; lNextDyad < pCard->devDiscover; lNextDyad++ ) + { + if ( pSLRList[lNextDyad].localeNameLen < 0 && + pSLRList[lNextDyad].remoteNameLen < 0 ) + break; + } + + if ( lNextDyad == pCard->devDiscover ) + { + printf( "agtiapi_GetDevHandle: failed to find available SAS LR\n" ); + AG_LIST_UNLOCK( &pCard->devListLock ); + free( (caddr_t)lDevFlags, M_PMC_MFLG ); + free( (caddr_t)agDev, M_PMC_MDEV ); + return 0; + } + // index of new entry + lDevIndex = agtiapi_FindWWNListNext( pWWNList, pCard->devDiscover ); + AGTIAPI_PRINTK( "agtiapi_GetDevHandle: listIdx new target %d of %d/%d\n", + lDevIndex, devTotal, pPortalInfo->portID ); + if ( 0 > lDevIndex ) + { + printf( "agtiapi_GetDevHandle: WARNING -- WWNList exhausted.\n" ); + continue; + } + + pDevice = &pCard->pDevList[lDevIndex]; + + tiINIGetDeviceInfo( &pCard->tiRoot, agDev[devIdx], &pDevice->devInfo ); + wwncpy( pDevice ); + agtiapi_InitCCBs( pCard, 1, lDevIndex ); + + pDevice->pCard = (void *)pCard; + pDevice->devType = DIRECT_DEVICE; + + // begin to populate new WWNList entry + memcpy( pWWNList[lDevIndex].targetName, pDevice->targetName, pDevice->targetLen ); + pWWNList[lDevIndex].targetLen = pDevice->targetLen; + + pWWNList[lDevIndex].flags = SOFT_MAPPED; + pWWNList[lDevIndex].portId = pPortalInfo->portID; + pWWNList[lDevIndex].devListIndex = lDevIndex; + pWWNList[lDevIndex].sasLrIdx = lNextDyad; + + pSLRList[lNextDyad].localeNameLen = portInfT.localNameLen; + pSLRList[lNextDyad].remoteNameLen = portInfT.remoteNameLen; + memcpy( pSLRList[lNextDyad].localeName, portInfT.localName, portInfT.localNameLen ); + memcpy( pSLRList[lNextDyad].remoteName, portInfT.remoteName, portInfT.remoteNameLen ); + // end of populating new WWNList entry + + pDevice->targetId = lDevIndex; + + pDevice->flags = ACTIVE; + pDevice->CCBCount = 0; + pDevice->pDevHandle = agDev[devIdx]; + agDev[devIdx]->osData = (void*)pDevice; + + pDevice->pPortalInfo = pPortalInfo; + pDevice->portalId = pPortalInfo->portID; + pPortalInfo->pDevList[lDevIndex] = (void*)pDevice; + lDevFlags[lDevIndex] |= DPMC_LEANFLAG_PDEVSUSED; // mark pDevice slot used + } + + if ( (pCard->pDevList[devIdx].portalId == pPortalInfo->portID) && + !(lDevFlags[devIdx] & DPMC_LEANFLAG_PDEVSUSED) ) // pDevice not used + { + pDevice = &pCard->pDevList[devIdx]; + //pDevice->flags &= ~ACTIVE; + if ( ( pDevice->pDevHandle != NULL || + pPortalInfo->pDevList[devIdx] != NULL ) ) + { + atomic_add_16( &pCard->rmChkCt, 1 ); // show count of lost device + + if (FALSE == lRunScanFlag) + { + + AGTIAPI_PRINTK( "agtiapi_GetDevHandle: targ dropped out %d of %d/%d\n", + devIdx, devTotal, pPortalInfo->portID ); + // if ( 0 == pWWNList[devIdx].devRemoved ) '.devRemoved = 5; + cmpsetRtn = atomic_cmpset_32( &pWWNList[devIdx].devRemoved, 0, 5 ); + if ( 0 == cmpsetRtn ) + { + AGTIAPI_PRINTK( "agtiapi_GetDevHandle: target %d timer already set\n", + devIdx ); + } + else + { + callout_reset( &pCard->devRmTimer, 1 * hz, agtiapi_devRmCheck, pCard ); + } + } + // else ... scan coming soon enough anyway, ignore timer for dropout + } + } + } // end of for ( devIdx = 0; ... + + AG_LIST_UNLOCK( &pCard->devListLock ); + + free((caddr_t)lDevFlags, M_PMC_MFLG); + free((caddr_t)agDev, M_PMC_MDEV); + + if ( TRUE == lRunScanFlag ) + agtiapi_clrRmScan( pCard ); + + return devTotal; +} // end agtiapi_GetDevHandle + +/****************************************************************************** +agtiapi_scan() + +Purpose: + Triggers CAM's scan +Parameters: + struct agtiapi_softc *pCard (IN) Pointer to the HBA data structure +Return: +Note: +******************************************************************************/ +static void agtiapi_scan(struct agtiapi_softc *pmcsc) +{ + union ccb *ccb; + int bus, tid, lun, card_no; + static int num=0; + + AGTIAPI_PRINTK("agtiapi_scan: start cardNO %d \n", pmcsc->cardNo); + + bus = cam_sim_path(pmcsc->sim); + + tid = CAM_TARGET_WILDCARD; + lun = CAM_LUN_WILDCARD; + + mtx_lock(&(pmcsc->pCardInfo->pmIOLock)); + ccb = xpt_alloc_ccb_nowait(); + if (ccb == agNULL) + { + mtx_unlock(&(pmcsc->pCardInfo->pmIOLock)); + return; + } + if (xpt_create_path(&ccb->ccb_h.path, agNULL, bus, tid, + CAM_LUN_WILDCARD) != CAM_REQ_CMP) + { + mtx_unlock(&(pmcsc->pCardInfo->pmIOLock)); + xpt_free_ccb(ccb); + return; + } + + mtx_unlock(&(pmcsc->pCardInfo->pmIOLock)); + pmcsc->dev_scan = agTRUE; + xpt_rescan(ccb); + return; +} + +/****************************************************************************** +agtiapi_DeQueueCCB() + +Purpose: + Remove a ccb from a queue +Parameters: + struct agtiapi_softc *pCard (IN) Pointer to the card structure + pccb_t *phead (IN) Pointer to a head of ccb queue + ccb_t *pccd (IN) Pointer to the ccb to be processed +Return: + AGTIAPI_SUCCESS - the ccb is removed from queue + AGTIAPI_FAIL - the ccb is not found from queue +Note: +******************************************************************************/ +STATIC agBOOLEAN +agtiapi_DeQueueCCB(struct agtiapi_softc *pCard, pccb_t *phead, pccb_t *ptail, +#ifdef AGTIAPI_LOCAL_LOCK + struct mtx *lock, +#endif + ccb_t *pccb) +{ + ccb_t *pccb_curr; + U32 status = AGTIAPI_FAIL; + + AGTIAPI_PRINTK("agtiapi_DeQueueCCB: %p from %p\n", pccb, phead); + + if (pccb == NULL || *phead == NULL) + { + return AGTIAPI_FAIL; + } + + AGTIAPI_PRINTK("agtiapi_DeQueueCCB: %p from %p\n", pccb, phead); + AG_LOCAL_LOCK(lock); + + if (pccb == *phead) + { + *phead = (*phead)->pccbNext; + if (pccb == *ptail) + { + *ptail = NULL; + } + else + pccb->pccbNext = NULL; + status = AGTIAPI_SUCCESS; + } + else + { + pccb_curr = *phead; + while (pccb_curr->pccbNext != NULL) + { + if (pccb_curr->pccbNext == pccb) + { + pccb_curr->pccbNext = pccb->pccbNext; + pccb->pccbNext = NULL; + if (pccb == *ptail) + { + *ptail = pccb_curr; + } + else + pccb->pccbNext = NULL; + status = AGTIAPI_SUCCESS; + break; + } + pccb_curr = pccb_curr->pccbNext; + } + } + AG_LOCAL_UNLOCK(lock); + + return status; +} + + +STATIC void wwnprintk( unsigned char *name, int len ) +{ + int i; + + for (i = 0; i < len; i++, name++) + AGTIAPI_PRINTK("%02x", *name); + AGTIAPI_PRINTK("\n"); +} +/* + * SAS and SATA behind expander has 8 byte long unique address. + * However, direct connect SATA device use 512 byte unique device id. + * SPC uses remoteName to indicate length of ID and remoteAddress for the + * address of memory that holding ID. + */ +STATIC int wwncpy( ag_device_t *pDevice ) +{ + int rc = 0; + + if (sizeof(pDevice->targetName) >= pDevice->devInfo.osAddress1 + + pDevice->devInfo.osAddress2) + { + memcpy(pDevice->targetName, + pDevice->devInfo.remoteName, + pDevice->devInfo.osAddress1); + memcpy(pDevice->targetName + pDevice->devInfo.osAddress1, + pDevice->devInfo.remoteAddress, + pDevice->devInfo.osAddress2); + pDevice->targetLen = pDevice->devInfo.osAddress1 + + pDevice->devInfo.osAddress2; + rc = pDevice->targetLen; + } + else + { + AGTIAPI_PRINTK("WWN wrong size: %d + %d ERROR\n", + pDevice->devInfo.osAddress1, pDevice->devInfo.osAddress2); + rc = -1; + } + return rc; +} + + +/****************************************************************************** +agtiapi_ReleaseCCBs() + +Purpose: + Free all allocated CCB memories for the Host Adapter. +Parameters: + struct agtiapi_softc *pCard (IN) Pointer to HBA data stucture +Return: +Note: +******************************************************************************/ +STATIC void agtiapi_ReleaseCCBs( struct agtiapi_softc *pCard ) +{ + + ccb_hdr_t *hdr; + U32 hdr_sz; + ccb_t *pccb = 0; + + AGTIAPI_PRINTK( "agtiapi_ReleaseCCBs: start\n" ); + +#if ( defined AGTIAPI_TEST_DPL || defined AGTIAPI_TEST_EPL ) + ccb_t *pccb; +#endif + +#ifdef AGTIAPI_TEST_DPL + for (pccb = (pccb_t)pCard->ccbChainList; pccb != NULL; + pccb = pccb->pccbChainNext) + { + if(pccb->dplPtr && pccb->dplDma) + pci_pool_free(pCard->dpl_ctx_pool, pccb->dplPtr, pccb->dplDma); + } +#endif + +#ifdef AGTIAPI_TEST_EPL + for (pccb = (pccb_t)pCard->ccbChainList; pccb != NULL; + pccb = pccb->pccbChainNext) + { + if(pccb->epl_ptr && pccb->epl_dma_ptr) + pci_pool_free( + pCard->epl_ctx_pool, + pccb->epl_ptr, + pccb->epl_dma_ptr + ); + } +#endif + + while ((hdr = pCard->ccbAllocList) != NULL) + { + pCard->ccbAllocList = hdr->next; + hdr_sz = (sizeof(*hdr) + cache_line_size() - 1) & ~(cache_line_size() - 1); + pccb = (ccb_t*) ((char*)hdr + hdr_sz); + if (pCard->buffer_dmat != NULL && pccb->CCB_dmamap != NULL) + { + bus_dmamap_destroy(pCard->buffer_dmat, pccb->CCB_dmamap); + } + free(hdr, M_PMC_MCCB); + } + pCard->ccbAllocList = NULL; + + + return; +} + +/****************************************************************************** +agtiapi_TITimer() + +Purpose: + Timer tick for tisa common layer +Parameters: + void *data (IN) Pointer to the HBA data structure +Return: +Note: +******************************************************************************/ +STATIC void agtiapi_TITimer( void *data ) +{ + + U32 next_tick; + struct agtiapi_softc *pCard; + + pCard = (struct agtiapi_softc *)data; + +// AGTIAPI_PRINTK("agtiapi_TITimer: start\n"); + AG_GLOBAL_ARG( flags ); + + next_tick = pCard->pCardInfo->tiRscInfo.tiLoLevelResource. + loLevelOption.usecsPerTick / USEC_PER_TICK; + + if( next_tick == 0 ) /* no timer required */ + return; + AG_SPIN_LOCK_IRQ( agtiapi_host_lock, flags ); + if( pCard->flags & AGTIAPI_SHUT_DOWN ) + goto ext; + tiCOMTimerTick( &pCard->tiRoot ); /* tisa common layer timer tick */ + + //add for polling mode +#ifdef PMC_SPC + if( agtiapi_polling_mode ) + agtiapi_CheckAllVectors( pCard, tiNonInterruptContext ); +#endif + callout_reset( &pCard->OS_timer, next_tick, agtiapi_TITimer, pCard ); +ext: + AG_SPIN_UNLOCK_IRQ( agtiapi_host_lock, flags ); + return; +} + +/****************************************************************************** +agtiapi_clrRmScan() + +Purpose: + Clears device list entries scheduled for timeout and calls scan +Parameters: + struct agtiapi_softc *pCard (IN) Pointer to HBA data structure +******************************************************************************/ +STATIC void agtiapi_clrRmScan( struct agtiapi_softc *pCard ) +{ + ag_tgt_map_t *pWWNList; + ag_portal_info_t *pPortalInfo; + ag_portal_data_t *pPortalData; + int lIdx; + bit32 lReadRm; + bit16 lReadCt; + + pWWNList = pCard->pWWNList; + + AGTIAPI_PRINTK( "agtiapi_clrRmScan: start\n" ); + + AG_LIST_LOCK( &pCard->devListLock ); + + for ( lIdx = 0; lIdx < pCard->devDiscover; lIdx++ ) + { + lReadCt = atomic_load_acq_16( &pCard->rmChkCt ); + if ( 0 == lReadCt ) + { + break; // trim to who cares + } + + lReadRm = atomic_readandclear_32( &pWWNList[lIdx].devRemoved ); + if ( lReadRm > 0 ) + { + pCard->pDevList[lIdx].flags &= ~ACTIVE; + pCard->pDevList[lIdx].pDevHandle = NULL; + + pPortalData = &pCard->pPortalData[pWWNList[lIdx].portId]; + pPortalInfo = &pPortalData->portalInfo; + pPortalInfo->pDevList[lIdx] = NULL; + AGTIAPI_PRINTK( "agtiapi_clrRmScan: cleared dev %d at port %d\n", + lIdx, pWWNList[lIdx].portId ); + atomic_subtract_16( &pCard->rmChkCt, 1 ); + } + } + AG_LIST_UNLOCK( &pCard->devListLock ); + + agtiapi_scan( pCard ); +} + + +/****************************************************************************** +agtiapi_devRmCheck() + +Purpose: + Timer tick to check for timeout on missing targets + Removes device list entry when timeout is reached +Parameters: + void *data (IN) Pointer to the HBA data structure +******************************************************************************/ +STATIC void agtiapi_devRmCheck( void *data ) +{ + struct agtiapi_softc *pCard; + ag_tgt_map_t *pWWNList; + int lIdx, cmpsetRtn, lRunScanFlag = FALSE; + bit16 lReadCt; + bit32 lReadRm; + + pCard = ( struct agtiapi_softc * )data; + + // routine overhead + if ( callout_pending( &pCard->devRmTimer ) ) // callout was reset + { + return; + } + if ( !callout_active( &pCard->devRmTimer ) ) // callout was stopped + { + return; + } + callout_deactivate( &pCard->devRmTimer ); + + if( pCard->flags & AGTIAPI_SHUT_DOWN ) + { + return; // implicit timer clear + } + + pWWNList = pCard->pWWNList; + + AG_LIST_LOCK( &pCard->devListLock ); + lReadCt = atomic_load_acq_16( &pCard->rmChkCt ); + if ( lReadCt ) + { + if ( callout_pending(&pCard->devRmTimer) == FALSE ) + { + callout_reset( &pCard->devRmTimer, 1 * hz, agtiapi_devRmCheck, pCard ); + } + else + { + AG_LIST_UNLOCK( &pCard->devListLock ); + return; + } + + for ( lIdx = 0; lIdx < pCard->devDiscover; lIdx++ ) + { + lReadCt = atomic_load_acq_16( &pCard->rmChkCt ); + if ( 0 == lReadCt ) + { + break; // if handled somewhere else, get out + } + + lReadRm = atomic_load_acq_32( &pWWNList[lIdx].devRemoved ); + if ( lReadRm > 0 ) + { + if ( 1 == lReadRm ) // timed out + { // no decrement of devRemoved as way to leave a clrRmScan marker + lRunScanFlag = TRUE; // other devRemoved values are about to get wiped + break; // ... so bail out + } + else + { + AGTIAPI_PRINTK( "agtiapi_devRmCheck: counting down dev %d @ %d; %d\n", + lIdx, lReadRm, lReadCt ); + cmpsetRtn = atomic_cmpset_32( &pWWNList[lIdx].devRemoved, + lReadRm, + lReadRm-1 ); + if ( 0 == cmpsetRtn ) + { + printf( "agtiapi_devRmCheck: %d decrement already handled\n", + lIdx ); + } + } + } + } + AG_LIST_UNLOCK( &pCard->devListLock ); + + if ( TRUE == lRunScanFlag ) + agtiapi_clrRmScan( pCard ); + } + else + { + AG_LIST_UNLOCK( &pCard->devListLock ); + } + + return; +} + + +static void agtiapi_cam_poll( struct cam_sim *asim ) +{ + return; +} + +/***************************************************************************** +agtiapi_ResetCard() + +Purpose: + Hard or soft reset on the controller and resend any + outstanding requests if needed. +Parameters: + struct agtiapi_softc *pCard (IN) Pointer to HBA data structure + unsigned lomg flags (IN/OUT) Flags used in locking done from calling layers +Return: + AGTIAPI_SUCCESS - reset successful + AGTIAPI_FAIL - reset failed +Note: +*****************************************************************************/ +U32 agtiapi_ResetCard( struct agtiapi_softc *pCard, unsigned long *flags ) +{ + ag_device_t *pDevice; + U32 lIdx = 0; + U32 lFlagVal; + agBOOLEAN ret; + ag_portal_info_t *pPortalInfo; + ag_portal_data_t *pPortalData; + U32 count, loop; + int szdv; + + if( pCard->flags & AGTIAPI_RESET ) { + AGTIAPI_PRINTK( "agtiapi_ResetCard: reset card already in progress!\n" ); + return AGTIAPI_FAIL; + } + + AGTIAPI_PRINTK( "agtiapi_ResetCard: Enter cnt %d\n", + pCard->resetCount ); +#ifdef LOGEVENT + agtiapi_LogEvent( pCard, + IOCTL_EVT_SEV_INFORMATIONAL, + 0, + agNULL, + 0, + "Reset initiator time = %d!", + pCard->resetCount + 1 ); +#endif + + pCard->flags |= AGTIAPI_RESET; + pCard->flags &= ~(AGTIAPI_CB_DONE | AGTIAPI_RESET_SUCCESS); + tiCOMSystemInterruptsActive( &pCard->tiRoot, FALSE ); + pCard->flags &= ~AGTIAPI_SYS_INTR_ON; + + agtiapi_FlushCCBs( pCard, AGTIAPI_CALLBACK ); + + for ( lIdx = 1; 3 >= lIdx; lIdx++ ) // we try reset up to 3 times + { + if( pCard->flags & AGTIAPI_SOFT_RESET ) + { + AGTIAPI_PRINTK( "agtiapi_ResetCard: soft variant\n" ); + tiCOMReset( &pCard->tiRoot, tiSoftReset ); + } + else + { + AGTIAPI_PRINTK( "agtiapi_ResetCard: no flag, no reset!\n" ); + } + + lFlagVal = AGTIAPI_RESET_SUCCESS; + AG_SPIN_UNLOCK_IRQ( agtiapi_host_lock, *flags ); + ret = agtiapi_CheckCB( pCard, 50000, lFlagVal, &pCard->flags ); + AG_SPIN_LOCK_IRQ( agtiapi_host_lock, *flags ); + + if( ret == AGTIAPI_FAIL ) + { + AGTIAPI_PRINTK( "agtiapi_ResetCard: CheckCB indicates failed reset call, " + "try again?\n" ); + } + else + { + break; + } + } + if ( 1 < lIdx ) + { + if ( AGTIAPI_FAIL == ret ) + { + AGTIAPI_PRINTK( "agtiapi_ResetCard: soft reset failed after try %d\n", + lIdx ); + } + else + { + AGTIAPI_PRINTK( "agtiapi_ResetCard: soft reset success at try %d\n", + lIdx ); + } + } + if( AGTIAPI_FAIL == ret ) + { + printf( "agtiapi_ResetCard: reset ERROR\n" ); + pCard->flags &= ~AGTIAPI_INSTALLED; + return AGTIAPI_FAIL; + } + + pCard->flags &= ~AGTIAPI_SOFT_RESET; + + // disable all devices + pDevice = pCard->pDevList; + for( lIdx = 0; lIdx < maxTargets; lIdx++, pDevice++ ) + { + /* if ( pDevice->flags & ACTIVE ) + { + printf( "agtiapi_ResetCard: before ... active device %d\n", lIdx ); + } */ + pDevice->flags &= ~ACTIVE; + } + + AG_SPIN_UNLOCK_IRQ( agtiapi_host_lock, *flags ); + if( tiCOMPortInit( &pCard->tiRoot, agFALSE ) != tiSuccess ) + printf( "agtiapi_ResetCard: tiCOMPortInit FAILED \n" ); + else + AGTIAPI_PRINTK( "agtiapi_ResetCard: tiCOMPortInit success\n" ); + + if( !pCard->pDevList ) { // try to get a little sanity here + AGTIAPI_PRINTK( "agtiapi_ResetCard: no pDevList ERROR %p\n", + pCard->pDevList ); + return AGTIAPI_FAIL; + } + + AGTIAPI_PRINTK( "agtiapi_ResetCard: pre target-count %d port-count %d\n", + pCard->tgtCount, pCard->portCount ); + pCard->tgtCount = 0; + + DELAY( 500000 ); + + pCard->flags &= ~AGTIAPI_CB_DONE; + + pPortalData = pCard->pPortalData; + + for( count = 0; count < pCard->portCount; count++ ) { + AG_SPIN_LOCK_IRQ( agtiapi_host_lock, flags ); + pPortalInfo = &pPortalData->portalInfo; + pPortalInfo->portStatus = 0; + pPortalInfo->portStatus &= ~( AGTIAPI_PORT_START | + AGTIAPI_PORT_DISC_READY | + AGTIAPI_DISC_DONE | + AGTIAPI_DISC_COMPLETE ); + + szdv = + sizeof( pPortalInfo->pDevList ) / sizeof( pPortalInfo->pDevList[0] ); + if (szdv > pCard->devDiscover) + { + szdv = pCard->devDiscover; + } + + for( lIdx = 0, loop = 0; + lIdx < szdv && loop < pPortalInfo->devTotal; + lIdx++ ) + { + pDevice = (ag_device_t*)pPortalInfo->pDevList[lIdx]; + if( pDevice ) + { + loop++; + pDevice->pDevHandle = 0; // mark for availability in pCard->pDevList[] + // don't erase more as the device is scheduled for removal on DPC + } + AGTIAPI_PRINTK( "agtiapi_ResetCard: reset pDev %p pDevList %p idx %d\n", + pDevice, pPortalInfo->pDevList, lIdx ); + pPortalInfo->devTotal = pPortalInfo->devPrev = 0; + } + + for( lIdx = 0; lIdx < maxTargets; lIdx++ ) + { // we reconstruct dev list later in get dev handle + pPortalInfo->pDevList[lIdx] = NULL; + } + + for( loop = 0; loop < AGTIAPI_LOOP_MAX; loop++ ) + { + AGTIAPI_PRINTK( "agtiapi_ResetCard: tiCOMPortStart entry data " + "%p / %d / %p\n", + &pCard->tiRoot, + pPortalInfo->portID, + &pPortalInfo->tiPortalContext ); + + if( tiCOMPortStart( &pCard->tiRoot, + pPortalInfo->portID, + &pPortalInfo->tiPortalContext, + 0 ) + != tiSuccess ) + { + printf( "agtiapi_ResetCard: tiCOMPortStart %d FAILED\n", + pPortalInfo->portID ); + } + else + { + AGTIAPI_PRINTK( "agtiapi_ResetCard: tiCOMPortStart %d success\n", + pPortalInfo->portID ); + break; + } + } + AG_SPIN_UNLOCK_IRQ( agtiapi_host_lock, flags ); + tiCOMGetPortInfo( &pCard->tiRoot, + &pPortalInfo->tiPortalContext, + &pPortalInfo->tiPortInfo ); + pPortalData++; + } + // ## fail case: pCard->flags &= ~AGTIAPI_INSTALLED; + + + AG_SPIN_LOCK_IRQ(agtiapi_host_lock, *flags); + + if( !(pCard->flags & AGTIAPI_INSTALLED) ) // driver not installed ! + { + printf( "agtiapi_ResetCard: error, driver not intstalled? " + "!AGTIAPI_INSTALLED \n" ); + return AGTIAPI_FAIL; + } + + AGTIAPI_PRINTK( "agtiapi_ResetCard: total device %d\n", pCard->tgtCount ); + +#ifdef LOGEVENT + agtiapi_LogEvent( pCard, + IOCTL_EVT_SEV_INFORMATIONAL, + 0, + agNULL, + 0, + "Reset initiator total device = %d!", + pCard->tgtCount ); +#endif + pCard->resetCount++; + + AGTIAPI_PRINTK( "agtiapi_ResetCard: clear send and done queues\n" ); + // clear send & done queue + AG_LOCAL_LOCK( &pCard->sendLock ); + pCard->ccbSendHead = NULL; + pCard->ccbSendTail = NULL; + AG_LOCAL_UNLOCK( &pCard->sendLock ); + + AG_LOCAL_LOCK( &pCard->doneLock ); + pCard->ccbDoneHead = NULL; + pCard->ccbDoneTail = NULL; + AG_LOCAL_UNLOCK( &pCard->doneLock ); + + // clear smp queues also + AG_LOCAL_LOCK( &pCard->sendSMPLock ); + pCard->smpSendHead = NULL; + pCard->smpSendTail = NULL; + AG_LOCAL_UNLOCK( &pCard->sendSMPLock ); + + AG_LOCAL_LOCK( &pCard->doneSMPLock ); + pCard->smpDoneHead = NULL; + pCard->smpDoneTail = NULL; + AG_LOCAL_UNLOCK( &pCard->doneSMPLock ); + + // finished with all reset stuff, now start things back up + tiCOMSystemInterruptsActive( &pCard->tiRoot, TRUE ); + pCard->flags |= AGTIAPI_SYS_INTR_ON; + pCard->flags |= AGTIAPI_HAD_RESET; + pCard->flags &= ~AGTIAPI_RESET; // ## + agtiapi_StartIO( pCard ); + AGTIAPI_PRINTK( "agtiapi_ResetCard: local return success\n" ); + return AGTIAPI_SUCCESS; +} // agtiapi_ResetCard + + +/****************************************************************************** +agtiapi_ReleaseHBA() + +Purpose: + Releases all resources previously acquired to support + a specific Host Adapter, including the I/O Address range, + and unregisters the agtiapi Host Adapter. +Parameters: + device_t dev (IN) - device pointer +Return: + always return 0 - success +Note: +******************************************************************************/ +int agtiapi_ReleaseHBA( device_t dev ) +{ + + int thisCard = device_get_unit( dev ); // keeping get_unit call to once + int i; + ag_card_info_t *thisCardInst = &agCardInfoList[ thisCard ]; + struct ccb_setasync csa; + struct agtiapi_softc *pCard; + pCard = device_get_softc( dev ); + ag_card_info_t *pCardInfo = pCard->pCardInfo; + ag_resource_info_t *pRscInfo = &thisCardInst->tiRscInfo; + + AG_GLOBAL_ARG(flags); + + AGTIAPI_PRINTK( "agtiapi_ReleaseHBA: start\n" ); + + if (thisCardInst != pCardInfo) + { + AGTIAPI_PRINTK( "agtiapi_ReleaseHBA: Wrong ag_card_info_t thisCardInst %p " + "pCardInfo %p\n", + thisCardInst, + pCardInfo ); + panic( "agtiapi_ReleaseHBA: Wrong ag_card_info_t thisCardInst %p pCardInfo " + "%p\n", + thisCardInst, + pCardInfo ); + return( EIO ); + } + + + AGTIAPI_PRINTK( "agtiapi_ReleaseHBA card %p\n", pCard ); + pCard->flags |= AGTIAPI_SHUT_DOWN; + + + // remove timer + if (pCard->flags & AGTIAPI_TIMER_ON) + { + AG_SPIN_LOCK_IRQ( agtiapi_host_lock, flags ); + callout_drain( &pCard->OS_timer ); + callout_drain( &pCard->devRmTimer ); + callout_drain(&pCard->IO_timer); + AG_SPIN_UNLOCK_IRQ( agtiapi_host_lock, flags ); + AGTIAPI_PRINTK( "agtiapi_ReleaseHBA: timer released\n" ); + } + +#ifdef HIALEAH_ENCRYPTION +//Release encryption table memory - Fix it + //if(pCard->encrypt && (pCard->flags & AGTIAPI_INSTALLED)) + //agtiapi_CleanupEncryption(pCard); +#endif + + /* + * Shutdown the channel so that chip gets frozen + * and it does not do any more pci-bus accesses. + */ + if (pCard->flags & AGTIAPI_SYS_INTR_ON) + { + tiCOMSystemInterruptsActive( &pCard->tiRoot, FALSE ); + pCard->flags &= ~AGTIAPI_SYS_INTR_ON; + AGTIAPI_PRINTK( "agtiapi_ReleaseHBA: card interrupt off\n" ); + } + if (pCard->flags & AGTIAPI_INSTALLED) + { + tiCOMShutDown( &pCard->tiRoot ); + AGTIAPI_PRINTK( "agtiapi_ReleaseHBA: low layers shutdown\n" ); + } + + /* + * first release IRQ, so that we do not get any more interrupts + * from this host + */ + if (pCard->flags & AGTIAPI_IRQ_REQUESTED) + { + if (!agtiapi_intx_mode) + { + int i; + for (i = 0; i< MAX_MSIX_NUM_VECTOR; i++) + { + if (pCard->irq[i] != agNULL && pCard->rscID[i] != 0) + { + bus_teardown_intr(dev, pCard->irq[i], pCard->intrcookie[i]); + bus_release_resource( dev, + SYS_RES_IRQ, + pCard->rscID[i], + pCard->irq[i] ); + } + } + pci_release_msi(dev); + } + pCard->flags &= ~AGTIAPI_IRQ_REQUESTED; + + + +#ifdef AGTIAPI_DPC + for (i = 0; i < MAX_MSIX_NUM_DPC; i++) + tasklet_kill(&pCard->tasklet_dpc[i]); +#endif + AGTIAPI_PRINTK("agtiapi_ReleaseHBA: IRQ released\n"); + } + + // release memory vs. alloc in agtiapi_alloc_ostimem; used in ostiAllocMemory + if( pCard->osti_busaddr != 0 ) { + bus_dmamap_unload( pCard->osti_dmat, pCard->osti_mapp ); + } + if( pCard->osti_mem != NULL ) { + bus_dmamem_free( pCard->osti_dmat, pCard->osti_mem, pCard->osti_mapp ); + } + if( pCard->osti_dmat != NULL ) { + bus_dma_tag_destroy( pCard->osti_dmat ); + } + + /* unmap the mapped PCI memory */ + /* calls bus_release_resource( ,SYS_RES_MEMORY, ..) */ + agtiapi_ReleasePCIMem(thisCardInst); + + /* release all ccbs */ + if (pCard->ccbTotal) + { + //calls bus_dmamap_destroy() for all pccbs + agtiapi_ReleaseCCBs(pCard); + AGTIAPI_PRINTK("agtiapi_ReleaseHBA: CCB released\n"); + } + +#ifdef HIALEAH_ENCRYPTION +/*release encryption resources - Fix it*/ + if(pCard->encrypt) + { + /*Check that all IO's are completed */ + if(atomic_read (&outstanding_encrypted_io_count) > 0) + { + printf("%s: WARNING: %d outstanding encrypted IOs !\n", __FUNCTION__, atomic_read(&outstanding_encrypted_io_count)); + } + //agtiapi_CleanupEncryptionPools(pCard); + } +#endif + + + /* release device list */ + if( pCard->pDevList ) { + free((caddr_t)pCard->pDevList, M_PMC_MDVT); + pCard->pDevList = NULL; + AGTIAPI_PRINTK("agtiapi_ReleaseHBA: device list released\n"); + } +#ifdef LINUX_PERBI_SUPPORT // ## review use of PERBI + AGTIAPI_PRINTK( "agtiapi_ReleaseHBA: WWN list %p \n", pCard->pWWNList ); + if( pCard->pWWNList ) { + free( (caddr_t)pCard->pWWNList, M_PMC_MTGT ); + pCard->pWWNList = NULL; + AGTIAPI_PRINTK("agtiapi_ReleaseHBA: WWN list released\n"); + } + if( pCard->pSLRList ) { + free( (caddr_t)pCard->pSLRList, M_PMC_MSLR ); + pCard->pSLRList = NULL; + AGTIAPI_PRINTK("agtiapi_ReleaseHBA: SAS Local Remote list released\n"); + } + +#endif + if (pCard->pPortalData) + { + free((caddr_t)pCard->pPortalData, M_PMC_MPRT); + pCard->pPortalData = NULL; + AGTIAPI_PRINTK("agtiapi_ReleaseHBA: PortalData released\n"); + } + //calls contigfree() or free() + agtiapi_MemFree(pCardInfo); + AGTIAPI_PRINTK("agtiapi_ReleaseHBA: low level resource released\n"); + +#ifdef HOTPLUG_SUPPORT + if (pCard->flags & AGTIAPI_PORT_INITIALIZED) + { + // agtiapi_FreeDevWorkList(pCard); + AGTIAPI_PRINTK("agtiapi_ReleaseHBA: (HP dev) work resources released\n"); + } +#endif + + /* + * TBD, scsi_unregister may release wrong host data structure + * which cause NULL pointer shows up. + */ + if (pCard->flags & AGTIAPI_SCSI_REGISTERED) + { + pCard->flags &= ~AGTIAPI_SCSI_REGISTERED; + + +#ifdef AGTIAPI_LOCAL_LOCK + if (pCard->STLock) + { + //destroy mtx + int maxLocks; + maxLocks = pRscInfo->tiLoLevelResource.loLevelOption.numOfQueuesPerPort; + + for( i = 0; i < maxLocks; i++ ) + { + mtx_destroy(&pCard->STLock[i]); + } + free(pCard->STLock, M_PMC_MSTL); + pCard->STLock = NULL; + } +#endif + + } + ag_card_good--; + + /* reset agtiapi_1st_time if this is the only card */ + if (!ag_card_good && !agtiapi_1st_time) + { + agtiapi_1st_time = 1; + } + + /* for tiSgl_t memeory */ + if (pCard->tisgl_busaddr != 0) + { + bus_dmamap_unload(pCard->tisgl_dmat, pCard->tisgl_map); + } + if (pCard->tisgl_mem != NULL) + { + bus_dmamem_free(pCard->tisgl_dmat, pCard->tisgl_mem, pCard->tisgl_map); + } + if (pCard->tisgl_dmat != NULL) + { + bus_dma_tag_destroy(pCard->tisgl_dmat); + } + + if (pCard->buffer_dmat != agNULL) + { + bus_dma_tag_destroy(pCard->buffer_dmat); + } + + if (pCard->sim != NULL) + { + mtx_lock(&thisCardInst->pmIOLock); + xpt_setup_ccb(&csa.ccb_h, pCard->path, 5); + csa.ccb_h.func_code = XPT_SASYNC_CB; + csa.event_enable = 0; + csa.callback = agtiapi_async; + csa.callback_arg = pCard; + xpt_action((union ccb *)&csa); + xpt_free_path(pCard->path); + // if (pCard->ccbTotal == 0) + if (pCard->ccbTotal <= thisCard) + { + /* + no link up so that simq has not been released. + In order to remove cam, we call this. + */ + xpt_release_simq(pCard->sim, 1); + } + xpt_bus_deregister(cam_sim_path(pCard->sim)); + cam_sim_free(pCard->sim, FALSE); + mtx_unlock(&thisCardInst->pmIOLock); + } + if (pCard->devq != NULL) + { + cam_simq_free(pCard->devq); + } + + //destroy mtx + mtx_destroy( &thisCardInst->pmIOLock ); + mtx_destroy( &pCard->sendLock ); + mtx_destroy( &pCard->doneLock ); + mtx_destroy( &pCard->sendSMPLock ); + mtx_destroy( &pCard->doneSMPLock ); + mtx_destroy( &pCard->ccbLock ); + mtx_destroy( &pCard->devListLock ); + mtx_destroy( &pCard->OS_timer_lock ); + mtx_destroy( &pCard->devRmTimerLock ); + mtx_destroy( &pCard->memLock ); + mtx_destroy( &pCard->freezeLock ); + + destroy_dev( pCard->my_cdev ); + memset((void *)pCardInfo, 0, sizeof(ag_card_info_t)); + return 0; +} + + +// Called during system shutdown after sync +static int agtiapi_shutdown( device_t dev ) +{ + AGTIAPI_PRINTK( "agtiapi_shutdown\n" ); + return( 0 ); +} + +static int agtiapi_suspend( device_t dev ) // Device suspend routine. +{ + AGTIAPI_PRINTK( "agtiapi_suspend\n" ); + return( 0 ); +} + +static int agtiapi_resume( device_t dev ) // Device resume routine. +{ + AGTIAPI_PRINTK( "agtiapi_resume\n" ); + return( 0 ); +} + +static device_method_t agtiapi_methods[] = { // Device interface + DEVMETHOD( device_probe, agtiapi_probe ), + DEVMETHOD( device_attach, agtiapi_attach ), + DEVMETHOD( device_detach, agtiapi_ReleaseHBA ), + DEVMETHOD( device_shutdown, agtiapi_shutdown ), + DEVMETHOD( device_suspend, agtiapi_suspend ), + DEVMETHOD( device_resume, agtiapi_resume ), + { 0, 0 } +}; + +static devclass_t pmspcv_devclass; + +static driver_t pmspcv_driver = { + "pmspcv", + agtiapi_methods, + sizeof( struct agtiapi_softc ) +}; + +DRIVER_MODULE( pmspcv, pci, pmspcv_driver, pmspcv_devclass, 0, 0 ); +MODULE_DEPEND( pmspcv, cam, 1, 1, 1 ); +MODULE_DEPEND( pmspcv, pci, 1, 1, 1 ); + +#include +#include +#include +#include + + diff --git a/sys/dev/pms/freebsd/driver/ini/src/agtiapi.h b/sys/dev/pms/freebsd/driver/ini/src/agtiapi.h new file mode 100644 index 000000000000..1098f90cd58b --- /dev/null +++ b/sys/dev/pms/freebsd/driver/ini/src/agtiapi.h @@ -0,0 +1,408 @@ +/******************************************************************************* +** +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, +* +*INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +*ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +*SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +*OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +*WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +*THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +** +* $FreeBSD$ +** +*******************************************************************************/ + +#include +#include +#include +#include +#include +#ifdef AGTIAPI_ISCSI +#include "cmtypes.h" +#include "bktypes.h" +#endif +#ifdef FDS_DM +#include +#endif +#include +#include +#include +#include + +typedef u_int32_t atomic_t; + +#define atomic_set(p,v) (*(p) = (v)) +#define atomic_read(p) (*(p)) +#define atomic_inc(p) atomic_add_int(p,1) +#define atomic_dec(p) atomic_subtract_int(p,1) +#define atomic_add(n,p) atomic_add_int(p,n) +#define atomic_sub(n,p) atomic_subtract_int(p,n) + +#define AGSCSI_INIT_XCHG_LEN sizeof(tiScsiInitiatorRequest_t) +#define AGSMP_INIT_XCHG_LEN sizeof(tiSMPFrame_t) +#define CMND_DMA_UNMAP( pCard, cmnd ) + + +// define PMC lean flags used for bit operations to track dev listing state +#define DPMC_LEANFLAG_NOAGDEVYT 2 // agDev handle not present yet +#define DPMC_LEANFLAG_NOWWNLIST 4 // WWNList entry not present +#define DPMC_LEANFLAG_AGDEVUSED 8 // agDev handle used +#define DPMC_LEANFLAG_PDEVSUSED 16 // pDevice slot used + +typedef bus_dmamap_t dma_addr_t; // ## + +#define timer_list callout + +typedef struct ccb_hdr_s { + void *next; +} ccb_hdr_t; + + +typedef struct _CCB { + U32 targetId; + U32 lun; + U32 channel; + U16 ccbStatus; + U16 scsiStatus; + U32 dataLen; + U08 senseLen; + U08 addrMode; + U08 retryCount; + U16 numSgElements; + U32 flags; + U32_64 dmaHandle; + caddr_t pSenseData; // auto request sense data + tiSgl_t *sgList; // [AGTIAPI_MAX_DMA_SEGS] + bus_addr_t tisgl_busaddr; + // dma_addr_t sglDmaHandle; // ## dmaHandle for sgList + tiDeviceHandle_t *devHandle; + struct _CCB *pccbNext; + struct _CCB *pccbChainNext; // forward link pointers + struct scsi_cmnd *cmd; // call back owner pointer + struct _CCB *pccbIO; // for TM TARGET_RESET + U32_64 startTime; + tiIORequest_t tiIORequest; + tdIORequestBody_t tdIOReqBody; + tiSuperScsiInitiatorRequest_t tiSuperScsiRequest; + tiSMPFrame_t tiSMPFrame; +#ifdef CCBUILD_TEST_EPL + caddr_t epl_ptr; + dma_addr_t epl_dma_ptr; +#endif + +#ifdef CCBUILD_TEST_DPL + caddr_t dplPtr; + dma_addr_t dplDma; +#endif + +#if defined (PERF_COUNT) + u64 startCmnd; // temp var to hold cmnd arrival +#endif +#ifdef ENABLE_NONSTANDARD_SECTORS + caddr_t metaPtr; + dma_addr_t dmaHandleMeta; +#endif +#ifdef ENABLE_SATA_DIF + caddr_t holePtr; + dma_addr_t dmaHandleHole; + int scaling_done; +#endif + +#ifdef SUPER_FAST_IO_TEST + agsaIORequest_t IoContext; + agsaSASRequestBody_t sasRequestBody; + u32 reqType; + u32 queueId; + agsaSgl_t *sgl; // Used for esgl +#endif + //new + bus_dmamap_t CCB_dmamap; + union ccb *ccb; /* replacement of struct scsi_cmnd */ + struct agtiapi_softc *pmcsc; + +} ccb_t, *pccb_t; + + +#define AGTIAPI_CCB_SIZE sizeof(struct _CCB) + +/* +typedef struct _ag_portal_data +{ + ag_portal_info_t portalInfo; + void *pCard; +} ag_portal_data_t; +*/ + +typedef enum { + DEK_TABLE_0 = 0, + DEK_TABLE_1 = 1, + DEK_TABLE_INVALID = DEK_MAX_TABLES, + } dek_table_e; + +typedef struct ag_encrypt_map_s { + unsigned long long lbaMin; + unsigned long long lbaMax; + dek_table_e dekTable; + bit32 dekIndex; + bit32 kekIndex; + bit32 kekTagCheck; + bit32 kekTag[2]; + struct list_head *list; + } ag_encrypt_map_t; + +typedef struct ag_kek_table_s { + #define KEK_TABLE_MAX_ENTRY 8 + bit32 wrapperIndex; + tiEncryptKekBlob_t kekBlob; + } ag_kek_table_t; + +typedef struct ag_dek_kek_map_s { + bit32 kekIndex; + } ag_dek_kek_map_t; + +/* +** There is no LUN filed for the device structure. +** The reason is if the device is a single lun device, it +** will be lun 0. If is a multi-lun device such as EMC +** or Galaxi, only one device structure is associated with +** the device since only one device handler is provided. +*/ +typedef struct _ag_device { +//#ifdef HOTPLUG_SUPPORT + /* used for hot-plug, temporarily either in new or removed devices list */ + LINK_NODE devLink; +//#endif + U32 targetId; + U32 flags; + U16 devType; + U16 resetCount; + U32 portalId; + void *pCard; + U32 sector_size; + U32 CCBCount; +#ifdef HOTPLUG_SUPPORT + struct scsi_device *sdev; +#endif + tiDeviceHandle_t *pDevHandle; + tiDeviceInfo_t devInfo; + ag_portal_info_t *pPortalInfo; + U08 targetName[AGTIAPI_MAX_NAME]; + U16 targetLen; + U32 qbusy; + U32 qdepth; +} ag_device_t; + + +/* +** Use an array of these structures to map from assigned +** device target id (which is the index into the array) to +** the entry in the bd_devlist. +** +** Please note that an extra entry has been added to both +** the bd_devlist array and the bd_WWN_list. This last +** entry is the "no mapping" entry -- used for initialization +** and to indicate an inactive entry. +*/ +typedef struct _ag_tgt_map { + U16 devListIndex; + U16 flags; + U08 targetName[AGTIAPI_MAX_NAME]; + U16 targetLen; + U08 portId; + int sasLrIdx; // Index into SAS Local/Remote list (part of extend-portID) + uint32_t devRemoved; // when set, ghost target device is timing out +} ag_tgt_map_t; + + +// use an array of this struct to map local/remote dyads to ag_tgt_map_t +// entries +typedef struct _ag_slr_map { + U08 localeName[AGTIAPI_MIN_NAME]; + U08 remoteName[AGTIAPI_MAX_NAME]; + int localeNameLen; + int remoteNameLen; +} ag_slr_map_t; + + +#ifdef LINUX_PERBI_SUPPORT +// Use a list of these structures to hold target-WWN +// mapping assignments on the boot line during driver +// loading. +typedef struct _ag_mapping_s +{ + struct _ag_mapping_s *next; + U16 targetId; + U08 cardNo; + U08 targetLen; + U08 targetName[AGTIAPI_MAX_NAME]; +} ag_mapping_t; +#endif + +typedef struct _ag_portal_data +{ + ag_portal_info_t portalInfo; + void *pCard; +} ag_portal_data_t; + + +// The softc holds our per-instance data +struct agtiapi_softc { + device_t my_dev; + struct cdev *my_cdev; + struct cam_sim *sim; + struct cam_path *path; + struct resource *resirq; + void *intr_cookie; + + int rscID[MAX_MSIX_NUM_VECTOR]; + struct resource *irq[MAX_MSIX_NUM_VECTOR]; + void *intrcookie[MAX_MSIX_NUM_VECTOR]; + + // timer stuff; mc lean + bus_dma_tag_t buffer_dmat; + struct cam_devq *devq; + struct callout OS_timer; + struct mtx OS_timer_lock; + struct callout IO_timer; + struct mtx IO_timer_lock; + struct callout devRmTimer; + struct mtx devRmTimerLock; + uint16_t rmChkCt; + + // for tiSgl_t memory + tiSgl_t *tisgl_mem; + bus_addr_t tisgl_busaddr; + bus_dma_tag_t tisgl_dmat; + bus_dmamap_t tisgl_map; + + // for ostiAllocMemory() pre allocation pool + void *osti_mem; + bus_addr_t osti_busaddr; + bus_dma_tag_t osti_dmat; + bus_dmamap_t osti_mapp; + + // pre-allocation pool + U32 typhn; // size needed + void *typh_mem; + bus_addr_t typh_busaddr; + bus_dma_tag_t typh_dmat; + bus_dmamap_t typh_mapp; + U32 typhIdx; + U32 tyPhsIx; + + + // begin ag_card_t references (AKA pCard) + struct Scsi_Host *pHost; + tiRoot_t tiRoot; // tiRoot for the card + U32 VidDid; + U32 SVID_SSID; + U32 flags; // keep track of state + U32 freezeSim; + U32 up_count; + U32 down_count; + U08 hostNo; // host number signed by OS + U08 cardNo; // host no signed by driver + U16 tgtCount; // total target devices + U16 badTgtCount; // total bad target devices + U16 activeCCB; // number of active CCB + U32 ccbTotal; // total # of CCB allocated + U32 devDiscover; // # of device to be discovered + U32 resetCount; + U32 timeoutTicks; + U32 portCount; // portal count + U32 SimQFrozen; // simq frozen state + U32 devq_flag; //device busy flag + U32 dev_scan; //device ready + pccb_t ccbSendHead; // CCB send list head + pccb_t ccbSendTail; // CCB send list tail + pccb_t ccbDoneHead; // CCB done list head + pccb_t ccbDoneTail; // CCB done list tail + pccb_t smpSendHead; // CCB send list head + pccb_t smpSendTail; // CCB send list tail + pccb_t smpDoneHead; // CCB done list head + pccb_t smpDoneTail; // CCB done list tail + caddr_t *ccbChainList; // ccb chain list head + caddr_t *ccbFreeList; // free ccb list head + ccb_hdr_t *ccbAllocList; // ### ccb allocation chain list head + struct pci_pool *sglPool; // for SGL pci_alloc_consistent + struct timer_list osTimerList; // card timer list +#ifdef TD_TIMER + struct timer_list tdTimerList; // tdlayer timer list +#endif + struct timer_list tiTimerList; // tilayer timer list + ag_portal_data_t *pPortalData; // wrapper + ag_card_info_t *pCardInfo; + ag_device_t *pDevList; + +#define CIPHER_MODE_INVALID 0xffffffffUL +#define DEK_INDEX_INVALID 0xffffffffUL +#define KEK_INDEX_INVALID 0xffffffffUL + int encrypt; // enable/disable encryption flag + bit32 dek_size; // size of dek + void *ioctl_data; // encryption ioctl data pointer + + struct list_head *encrypt_map; // encryption map + ag_kek_table_t kek_table[KEK_TABLE_MAX_ENTRY]; + // KEK table + ag_dek_kek_map_t dek_kek_map[DEK_MAX_TABLES][DEK_MAX_TABLE_ITEMS]; + // storage for dek index in tables (sysfs) + int dek_index[2]; +#define DEK_SIZE_PLAIN 72 +#define DEK_SIZE_ENCRYPT 80 +#define ENCRYPTION_MAP_MEMPOOL_SIZE 64 + char map_cache_name[32]; // name of mapping memory pool + struct kmem_cache *map_cache; // handle to mapping cache + bit32 cipher_mode; // storage of cipher mode +#define ENCRYPTION_IO_ERR_MEMPOOL_SIZE 256 + struct mtx ioerr_queue_lock; + char ioerr_cache_name[32]; + struct kmem_cache *ioerr_cache; // handle to IO error cache + +//#ifdef LINUX_PERBI_SUPPORT + ag_tgt_map_t *pWWNList; + ag_slr_map_t *pSLRList; // SAS Local/Remote map list + U32 numTgtHardMapped; // hard mapped target number +//#endif + struct sema *pIoctlSem; // for ioctl sync. + U32_64 osLockFlag; // flag for oslayer spin lock TBU +#ifdef AGTIAPI_LOCAL_LOCK + struct mtx sendLock; // local queue lock + struct mtx doneLock; // local queue lock + struct mtx sendSMPLock; // local queue lock + struct mtx doneSMPLock; // local queue lock + struct mtx ccbLock; // ccb list lock + struct mtx *STLock; // Low Level & TD locks + unsigned long *STLockFlags; // Low Level & TD locks flags + struct mtx memLock; // dynamic memory allocation lock + struct mtx freezeLock; +#endif +#ifdef AGTIAPI_DPC // card deferred intr process tasklet + struct callout tasklet_dpc[MAX_MSIX_NUM_DPC]; +#endif +//#ifdef HOTPLUG_SUPPORT + struct mtx devListLock; // device lists lock +//#endif + +}; + +int agtiapi_getdevlist( struct agtiapi_softc *pCard, + tiIOCTLPayload_t *agIOCTLPayload ); +int agtiapi_getCardInfo ( struct agtiapi_softc *pCard, + U32_64 size, + void *buffer ); + +#ifndef LINUX_PERBI_SUPPORT +#define INDEX(_pCard, _T) (_T) +#else +#define INDEX(_pCard, _T) (((_pCard)->pWWNList + (_T))->devListIndex) +#endif + diff --git a/sys/dev/pms/freebsd/driver/ini/src/agtiproto.h b/sys/dev/pms/freebsd/driver/ini/src/agtiproto.h new file mode 100644 index 000000000000..c7ed7b7a29f6 --- /dev/null +++ b/sys/dev/pms/freebsd/driver/ini/src/agtiproto.h @@ -0,0 +1,144 @@ +/******************************************************************************* +**Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. + * +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, +* +*INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +*ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +*SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +*OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +*WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +*THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +** +* $FreeBSD$ +** +*******************************************************************************/ + +//void agtiapi_cam_init(struct agtiapi_softc *sc); +//void agtiapi_cam_poll( struct cam_sim *asim ); +int agtiapi_QueueCmnd_(struct agtiapi_softc *, union ccb * ); +int agtiapi_alloc_ostimem(struct agtiapi_softc *); +int agtiapi_alloc_requests(struct agtiapi_softc *); +static int agtiapi_PrepareSGList(struct agtiapi_softc *, ccb_t *); +static void agtiapi_PrepareSGListCB( void *arg, + bus_dma_segment_t *dm_segs, + int nseg, + int error ); +static int agtiapi_PrepareSMPSGList(struct agtiapi_softc *pmcsc, ccb_t *); +static void agtiapi_PrepareSMPSGListCB( void *arg, + bus_dma_segment_t *dm_segs, + int nsegs, + int error ); +int agtiapi_eh_HostReset( struct agtiapi_softc *pmcsc, union ccb *cmnd ); +STATIC void agtiapi_FreeCCB(struct agtiapi_softc *pmcsc, pccb_t pccb); +STATIC void agtiapi_FreeSMPCCB(struct agtiapi_softc *pmcsc, pccb_t pccb); +STATIC void agtiapi_FreeTMCCB(struct agtiapi_softc *pmcsc, pccb_t pccb); +STATIC pccb_t agtiapi_GetCCB(struct agtiapi_softc *pmcsc); +void agtiapi_SetLunField( ccb_t *pccb ); +STATIC void agtiapi_QueueCCB( struct agtiapi_softc *pmcsc, + pccb_t *phead, + pccb_t *ptail, +#ifdef AGTIAPI_LOCAL_LOCK + struct mtx *mutex, +#endif + ccb_t *pccb ); +static int agtiapi_QueueSMP(struct agtiapi_softc *, union ccb * ); +STATIC void agtiapi_StartIO(struct agtiapi_softc *pmcsc); +STATIC void agtiapi_StartSMP(struct agtiapi_softc *pmcsc); +STATIC void agtiapi_DumpCCB(ccb_t *pccb); +STATIC void agtiapi_Done(struct agtiapi_softc *pmcsc, ccb_t *pccb); +STATIC void agtiapi_SMPDone(struct agtiapi_softc *pmcsc, ccb_t *pccb); +// void agtiapi_LogEvent(ag_card_t *, U16, U16, U32 *, U08, S08 *, ...); +STATIC U32 agtiapi_CheckError(struct agtiapi_softc *pmcsc, ccb_t *pccb); +STATIC U32 agtiapi_CheckSMPError(struct agtiapi_softc *pmcsc, ccb_t *pccb); +STATIC void agtiapi_Retry(struct agtiapi_softc *pmcsc, ccb_t *pccb); +static void agtiapi_scan(struct agtiapi_softc *pmcsc); +STATIC int agtiapi_FindWWNListNext( ag_tgt_map_t * pWWNList, int lstMax ); +STATIC U32 agtiapi_GetDevHandle(struct agtiapi_softc *pmcsc, + ag_portal_info_t *pPortalInfo, + U32 eType, U32 eStatus); + +int agtiapi_StartTM(struct agtiapi_softc *pCard, ccb_t *pccb); + +STATIC void wwnprintk(unsigned char *name, int len); +STATIC int wwncpy(ag_device_t *pDevice); + +STATIC void agtiapi_DiscoverTgt(struct agtiapi_softc *pCard); +agBOOLEAN agtiapi_CheckCB( struct agtiapi_softc *pCard, + U32 milisec, + U32 flag, + volatile U32 *pStatus ); +STATIC agBOOLEAN agtiapi_DeQueueCCB( struct agtiapi_softc *, + pccb_t *, + pccb_t *, +#ifdef AGTIAPI_LOCAL_LOCK + struct mtx *, +#endif + ccb_t * ); + +void agtiapi_CheckAllVectors( struct agtiapi_softc *pCard, bit32 context ); + +STATIC U32 agtiapi_InitCCBs( struct agtiapi_softc *pCard, + int tgtCount, + int tid ); +STATIC void agtiapi_PrepCCBs( struct agtiapi_softc *pCard, + ccb_hdr_t *hdr, + U32 size, + U32 max_ccb, + int tid ); + + +#ifdef LINUX_PERBI_SUPPORT +void agtiapi_GetWWNMappings( struct agtiapi_softc *, ag_mapping_t * ); +//#ifndef HOTPLUG_SUPPORT +STATIC void agtiapi_MapWWNList( struct agtiapi_softc *pCard ); +//#endif +#endif + +STATIC void agtiapi_ReleaseCCBs( struct agtiapi_softc *pCard ); +STATIC void agtiapi_clrRmScan( struct agtiapi_softc *pCard ); +STATIC void agtiapi_TITimer( void *data ); +STATIC void agtiapi_devRmCheck( void *data ); + +int agtiapi_ReleaseHBA( device_t dev ); + +void agtiapi_IntrHandler0( void *arg ); +void agtiapi_IntrHandler1( void *arg ); +void agtiapi_IntrHandler2( void *arg ); +void agtiapi_IntrHandler3( void *arg ); +void agtiapi_IntrHandler4( void *arg ); +void agtiapi_IntrHandler5( void *arg ); +void agtiapi_IntrHandler6( void *arg ); +void agtiapi_IntrHandler7( void *arg ); +void agtiapi_IntrHandler8( void *arg ); +void agtiapi_IntrHandler9( void *arg ); +void agtiapi_IntrHandler10( void *arg ); +void agtiapi_IntrHandler11( void *arg ); +void agtiapi_IntrHandler12( void *arg ); +void agtiapi_IntrHandler13( void *arg ); +void agtiapi_IntrHandler14( void *arg ); +void agtiapi_IntrHandler15( void *arg ); +void agtiapi_IntrHandlerx_( void *arg, int index ); +STATIC agBOOLEAN agtiapi_InitCardSW( struct agtiapi_softc *pmsc ); +STATIC agBOOLEAN agtiapi_InitCardHW( struct agtiapi_softc *pmsc ); +STATIC void agtiapi_DumpCDB( const char *ptitle, ccb_t *pccb ); +void agtiapi_hexdump( const char *ptitle, bit8 *pbuf, int len ); +static void agtiapi_SglMemoryCB( void *arg, + bus_dma_segment_t *dm_segs, + int nseg, + int error ); +static void agtiapi_MemoryCB( void *arg, + bus_dma_segment_t *dm_segs, + int nseg, + int error ); +U32 agtiapi_ResetCard( struct agtiapi_softc *pCard, unsigned long *flags ); +int agtiapi_DoSoftReset( struct agtiapi_softc *pmcsc ); + +STATIC void agtiapi_FlushCCBs( struct agtiapi_softc *pCard, U32 flag ); + diff --git a/sys/dev/pms/freebsd/driver/ini/src/osapi.c b/sys/dev/pms/freebsd/driver/ini/src/osapi.c new file mode 100644 index 000000000000..e47bf7c79309 --- /dev/null +++ b/sys/dev/pms/freebsd/driver/ini/src/osapi.c @@ -0,0 +1,835 @@ +/******************************************************************************* +*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. +* +*Redistribution and use in source and binary forms, with or without modification, are permitted provided +*that the following conditions are met: +*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the +*following disclaimer. +*2. Redistributions in binary form must reproduce the above copyright notice, +*this list of conditions and the following disclaimer in the documentation and/or other materials provided +*with the distribution. +* +*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED +*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE +* +* $FreeBSD$ +* +*******************************************************************************/ +/****************************************************************************** +PMC-Sierra TISA Initiator Device Driver for Linux 2.x.x. + +Module Name: + osapi.c +Abstract: + Linux iSCSI/FC Initiator driver module itsdk required OS functions +Environment: + Part of oslayer module, Kernel or loadable module + +******************************************************************************* +ostiInitiatorEvent() + +Purpose: + TI layer call back to OSlayer to inform events +Parameters: + tiRoot_t *ptiRoot (IN) Pointer to HBA data structure + tiDeviceHandle_t *ptiDevHandle (IN) Pointer to device handle + tiIntrEvenType_t evenType (IN) Event type + tiIntrEventStatus_t evetStatus (IN) Event status + void *parm (IN) pointer to even specific data +Return: +Note: + TBD, further event process required. +******************************************************************************/ +void ostiInitiatorEvent( tiRoot_t *ptiRoot, + tiPortalContext_t *ptiPortalContext, + tiDeviceHandle_t *ptiDevHandle, + tiIntrEventType_t eventType, + U32 eventStatus, + void *parm ) +{ + ag_portal_data_t *pPortalData; + ag_portal_info_t *pPortalInfo; + struct agtiapi_softc *pCard = TIROOT_TO_CARD( ptiRoot ); + ccb_t *pccb; + ccb_t *pTMccb; + ccb_t *ccbIO; + +#ifdef AGTIAPI_EVENT_LOG + AGTIAPI_PRINTK("Initiator Event:\n"); + AGTIAPI_PRINTK("DevHandle %p, eventType 0x%x, eventStatus 0x%x\n", + ptiDevHandle, eventType, eventStatus); + AGTIAPI_PRINTK("Parameter: %s\n", (char *)parm); +#endif + + AGTIAPI_PRINTK("ostiInitiatorEvent: eventType 0x%x eventStatus 0x%x\n", eventType, eventStatus); + + switch (eventType) + { + case tiIntrEventTypeCnxError: + if (eventStatus == tiCnxUp) + { + AGTIAPI_PRINTK("tiIntrEventTypeCnxError - tiCnxUp!\n"); + } + if (eventStatus == tiCnxDown) + { + AGTIAPI_PRINTK("tiIntrEventTypeCnxError - tiCnxDown!\n"); + } + break; + case tiIntrEventTypeDiscovery: + pPortalData = PORTAL_CONTEXT_TO_PORTALDATA(ptiPortalContext); + pCard->flags |= AGTIAPI_CB_DONE; + if (eventStatus == tiDiscOK) + { + AGTIAPI_PRINTK("eventStatus - tiDiscOK\n"); + AGTIAPI_PRINTK("ostiInitiatorEvent: pcard %d eventStatus - tiDiscOK\n", pCard->cardNo ); + PORTAL_STATUS(pPortalData) |= AGTIAPI_DISC_COMPLETE; +#ifndef HOTPLUG_SUPPORT + if (!(pCard->flags & AGTIAPI_INIT_TIME)) +#else + if (TRUE) +#endif + { + + agtiapi_GetDevHandle(pCard, &pPortalData->portalInfo, + tiIntrEventTypeDiscovery, tiDiscOK); + PORTAL_STATUS(pPortalData) |= + (AGTIAPI_DISC_DONE | AGTIAPI_PORT_LINK_UP); + } + /* Trigger CheckIOTimeout */ + callout_reset(&pCard->IO_timer, 20*hz, agtiapi_CheckIOTimeout, pCard); + } + else if (eventStatus == tiDiscFailed) + { + AGTIAPI_PRINTK("eventStatus - tiDiscFailed\n"); + agtiapi_GetDevHandle(pCard, &pPortalData->portalInfo, + tiIntrEventTypeDiscovery, tiDiscFailed); + PORTAL_STATUS(pPortalData) &= ~AGTIAPI_DISC_DONE; + } + AGTIAPI_PRINTK("tiIntrEventTypeDiscovery - portal %p, status 0x%x\n", + pPortalData, + PORTAL_STATUS(pPortalData)); + break; + case tiIntrEventTypeDeviceChange: + AGTIAPI_PRINTK("tiIntrEventTypeDeviceChange - portal %p es %d\n", + ptiPortalContext->osData, eventStatus); + pPortalData = PORTAL_CONTEXT_TO_PORTALDATA(ptiPortalContext); + pPortalInfo = &pPortalData->portalInfo; +#ifndef HOTPLUG_SUPPORT + if (!(pCard->flags & AGTIAPI_INIT_TIME)) +#else + if (TRUE) +#endif + { + agtiapi_GetDevHandle(pCard, pPortalInfo, tiIntrEventTypeDeviceChange, + eventStatus); +// agtiapi_StartIO(pCard); + } + break; + case tiIntrEventTypeTransportRecovery: + AGTIAPI_PRINTK("tiIntrEventTypeTransportRecovery!\n"); + break; + case tiIntrEventTypeTaskManagement: + AGTIAPI_PRINTK("tiIntrEventTypeTaskManagement!\n"); + pccb = (pccb_t)((tiIORequest_t *)parm)->osData; + if (pccb->flags & TASK_TIMEOUT) + { + AGTIAPI_PRINTK("tiIntrEventTypeTaskManagement: TM timeout!\n"); + agtiapi_FreeTMCCB(pCard, pccb); + } + else + { + pccb->flags |= AGTIAPI_CB_DONE; + if (eventStatus == tiTMOK) + { + pccb->flags |= TASK_SUCCESS; + AGTIAPI_PRINTK("tiIntrEventTypeTaskManagement: pTMccb %p flag %x \n", + pccb, pccb->flags); + + /* Incase of TM_DEV_RESET, issue LocalAbort to abort pending IO */ + if (pccb->flags & DEV_RESET) + { + AGTIAPI_PRINTK("tiIntrEventTypeTaskManagement: Target Reset\n"); + ccbIO = pccb->pccbIO; + AGTIAPI_PRINTK("tiIntrEventTypeTaskManagement: IO to be aborted locally %p flag %x \n", + ccbIO, ccbIO->flags); + if (ccbIO->startTime == 0) /* IO has been completed. No local abort */ + { + } + else if (tiINIIOAbort(&pCard->tiRoot, &ccbIO->tiIORequest) != tiSuccess) + { + AGTIAPI_PRINTK("tiIntrEventTypeTaskManagement: Local Abort failed\n"); + /* TODO: call Soft reset here */ + } + } + else if (eventStatus == tiTMFailed) + { + ccbIO = pccb->pccbIO; + if (ccbIO->startTime == 0) /* IO has been completed. */ + { + AGTIAPI_PRINTK("tiIntrEventTypeTaskManagement: TM failed becasue IO has been completed! pTMccb %p flag %x \n", + pccb, pccb->flags); + } + else + { + AGTIAPI_PRINTK("tiIntrEventTypeTaskManagement: TM failed! pTMccb %p flag %x \n", + pccb, pccb->flags); + /* TODO:*/ + /* if TM_ABORT_TASK, call TM_TARGET_RESET */ + /* if TM_TARGET_RESET, call Soft_Reset */ + } + } + /* Free TM_DEV_RESET ccb */ + agtiapi_FreeTMCCB(pCard, pccb); + } + } + break; + case tiIntrEventTypeLocalAbort: + AGTIAPI_PRINTK("tiIntrEventTypeLocalAbort!\n"); + pccb = (pccb_t)((tiIORequest_t *)parm)->osData; + pccb->flags |= AGTIAPI_CB_DONE; + if (eventStatus == tiAbortOK) + { + AGTIAPI_PRINTK("tiIntrEventTypeLocalAbort: taskTag pccb %p flag %x \n", + pccb, pccb->flags); + /* If this was LocalAbort for TM ABORT_TASK, issue TM_DEV_RESET */ + if (pccb->flags & TASK_MANAGEMENT) + { + if ((pTMccb = agtiapi_GetCCB(pCard)) == NULL) + { + AGTIAPI_PRINTK("tiIntrEventTypeLocalAbort: TM resource unavailable!\n"); + /* TODO: SoftReset here? */ + } + pTMccb->pmcsc = pCard; + pTMccb->targetId = pccb->targetId; + pTMccb->devHandle = pccb->devHandle; + + /* save pending io to issue local abort at Task mgmt CB */ + pTMccb->pccbIO = pccb->pccbIO; + pTMccb->flags &= ~(TASK_SUCCESS | ACTIVE); + pTMccb->flags |= DEV_RESET; + if (tiINITaskManagement(&pCard->tiRoot, + pccb->devHandle, + AG_TARGET_WARM_RESET, + &pccb->tiSuperScsiRequest.scsiCmnd.lun, + &pccb->tiIORequest, + &pTMccb->tiIORequest) + == tiSuccess) + { + AGTIAPI_PRINTK("tiIntrEventTypeLocalAbort: TM_TARGET_RESET request success ccb %p, pTMccb %p\n", + pccb, pTMccb); + pTMccb->startTime = ticks; + } + else + { + AGTIAPI_PRINTK("tiIntrEventTypeLocalAbort: TM_TARGET_RESET request failed ccb %p, pTMccb %p\n", + pccb, pTMccb); + agtiapi_FreeTMCCB(pCard, pTMccb); + /* TODO: SoftReset here? */ + } + /* Free ABORT_TASK TM ccb */ + agtiapi_FreeTMCCB(pCard, pccb); + } + } + else if (eventStatus == tiAbortFailed) + { + /* TODO: */ + /* If TM_ABORT_TASK fails, issue TM_DEV_RESET */ + /* if TM_DEV_RESET fails, issue Soft_Reset */ + AGTIAPI_PRINTK("tiIntrEventTypeLocalAbort: Abort Failed pccb %p\n", pccb); + } + break; + default: + AGTIAPI_PRINTK("tiIntrEventType default!\n"); + break; + } +} + + +/****************************************************************************** +ostiInitiatorIOCompleted() + +Purpose: + IO request completion call back +Parameters: + tiRoot_t *ptiRoot (IN) Pointer to the HBA tiRoot + tiIORequest_t *ptiIORequest (IN) Pointer to the tiIORequest structure + tiIOStatus_t IOStatus (IN) I/O complated status + U32 statusDetail (IN) Additional information on status + tiSenseData_t *pSensedata (IN) Sense data buffer pointer + U32 context (IN) Interrupt dealing context +Returns: +Note: +******************************************************************************/ +void +ostiInitiatorIOCompleted(tiRoot_t *ptiRoot, + tiIORequest_t *ptiIORequest, + tiIOStatus_t IOStatus, + U32 statusDetail, + tiSenseData_t *pSenseData, + U32 context ) +{ + struct agtiapi_softc *pCard; + ccb_t *pccb; + + pCard = TIROOT_TO_CARD(ptiRoot); + pccb = (ccb_t *)ptiIORequest->osData; + + AGTIAPI_IO( "ostiInitiatorIOCompleted: start\n" ); + + if (IOStatus == tiIODifError) + { + return; + } + OSTI_OUT_ENTER(ptiRoot); + + pccb->ccbStatus = (U16)IOStatus; + pccb->scsiStatus = statusDetail; + + if ((IOStatus == tiIOSuccess) && (statusDetail == SCSI_CHECK_CONDITION)) + { + if (pSenseData == (tiSenseData_t *)agNULL) + { + AGTIAPI_PRINTK( "ostiInitiatorIOCompleted: " + "check condition without sense data!\n" ); + } + else + { + union ccb *ccb = pccb->ccb; + struct ccb_scsiio *csio = &ccb->csio; + int sense_len = 0; + if (pccb->senseLen > pSenseData->senseLen) + { + csio->sense_resid = pccb->senseLen - pSenseData->senseLen; + } + else + { + csio->sense_resid = 0; + } + sense_len = MIN( pSenseData->senseLen, + pccb->senseLen - csio->sense_resid ); + bzero(&csio->sense_data, sizeof(&csio->sense_data)); + AGTIAPI_PRINTK("ostiInitiatorIOCompleted: check condition copying\n"); + memcpy( (void *)pccb->pSenseData, + pSenseData->senseData, + sense_len ); + agtiapi_hexdump( "ostiInitiatorIOCompleted check condition", + (bit8 *)&csio->sense_data, sense_len ); + } + } + if ((IOStatus == tiIOFailed) && (statusDetail == tiDetailAborted)) + { + AGTIAPI_PRINTK("ostiInitiatorIOCompleted - aborted ccb %p, flag %x\n", + pccb, pccb->flags); + /* indicate aborted IO completion */ + pccb->startTime = 0; + agtiapi_Done(pCard, pccb); + } + else + { +#ifdef AGTIAPI_SA + /* + * SAS no data command does not trigger interrupt. + * Command is completed in tdlayer and IO completion is called directly. + * The completed IO therefore is not post processed. + * Flag is raised and TDTimer will check and process IO for SAS. + * This is a temporary solution. - Eddie, 07-17-2006 + */ + pCard->flags |= AGTIAPI_FLAG_UP; +#endif + pccb->flags |= REQ_DONE; + agtiapi_QueueCCB(pCard, &pCard->ccbDoneHead, &pCard->ccbDoneTail + AG_CARD_LOCAL_LOCK(&pCard->doneLock), pccb); + } + OSTI_OUT_LEAVE(ptiRoot); + return; +} +#ifdef HIALEAH_ENCRYPTION +osGLOBAL void +ostidisableEncryption(tiRoot_t *ptiRoot) +{ + struct agtiapi_softc *pCard; + pCard = TIROOT_TO_CARD(ptiRoot); + pCard->encrypt=agFALSE; +} +#endif +/* device Handle */ +osGLOBAL //FORCEINLINE +tiDeviceHandle_t* +ostiGetDevHandleFromSasAddr( + tiRoot_t *root, + unsigned char *sas_addr +) +{ + int i; + unsigned long x; + + ag_portal_data_t *pPortal = NULL; + tiDeviceHandle_t *devHandle = NULL; + struct agtiapi_softc *pCard = TIROOT_TO_CARD(root); + bit8 sas_addr_hi[4], sas_addr_lo[4]; + + + for(i=0; i<4; i++) + { + sas_addr_hi[i] = sas_addr[3-i]; + } + + for(i=0; i<4; i++) + { + sas_addr_lo[i] = sas_addr[7-i]; + } + + /* Retrieve the handles for each portal */ + for (x=0; x < pCard->portCount; x++) + { + pPortal = &pCard->pPortalData[x]; + devHandle = tiINIGetExpDeviceHandleBySasAddress(&pCard->tiRoot, + &pPortal->portalInfo.tiPortalContext, + *(bit32*)sas_addr_hi, + *(bit32*)sas_addr_lo, + (bit32)1024/*gMaxTargets*/); + if(devHandle != NULL) + break; + } + return devHandle; + + return NULL; +} +/****************************************************************************** +ostiInitiatorSMPCompleted() + +Purpose: + IO request completion call back +Parameters: + tiRoot_t *ptiRoot (IN) Pointer to the HBA tiRoot + tiIORequest_t *ptiSMPRequest (IN) Pointer to the SMP request structure + tiIOStatus_t IOStatus (IN) I/O complated status + U32 tiSMPInfoLen (IN) Number of bytes of response frame len + tiFrameHandle (IN) Handle that referes to response frame + U32 context (IN) Interrupt dealing context +Returns: +Note: +******************************************************************************/ +void +ostiInitiatorSMPCompleted(tiRoot_t *ptiRoot, + tiIORequest_t *ptiSMPRequest, + tiSMPStatus_t smpStatus, + bit32 tiSMPInfoLen, + void *tiFrameHandle, + bit32 context) +{ + struct agtiapi_softc *pCard; + ccb_t *pccb; + pCard = TIROOT_TO_CARD(ptiRoot); + pccb = (ccb_t *)ptiSMPRequest->osData; + + AGTIAPI_PRINTK("ostiInitiatorSMPCompleted: start\n"); + + OSTI_OUT_ENTER(ptiRoot); + pccb->ccbStatus = (U16)smpStatus; + if(smpStatus != tiSMPSuccess) + { + AGTIAPI_PRINTK("ostiInitiatorSMPCompleted: SMP Error\n"); + } + else + { + union ccb *ccb = pccb->ccb; + struct ccb_smpio *csmpio = &ccb->smpio; + memcpy(csmpio->smp_response, tiFrameHandle, tiSMPInfoLen); + csmpio->smp_response_len = tiSMPInfoLen; + agtiapi_hexdump("ostiInitiatorSMPCompleted: Responce Payload in CAM", (bit8 *)csmpio->smp_response, csmpio->smp_response_len); + } + pccb->flags |= REQ_DONE; + agtiapi_QueueCCB(pCard, &pCard->smpDoneHead, &pCard->smpDoneTail + AG_CARD_LOCAL_LOCK(&pCard->doneSMPLock), pccb); + AGTIAPI_PRINTK("ostiInitiatorSMPCompleted: Done\n"); + OSTI_OUT_LEAVE(ptiRoot); + + return; +} + +#ifdef FAST_IO_TEST +void +osti_FastIOCb(tiRoot_t *ptiRoot, + void *arg, + tiIOStatus_t IOStatus, + U32 statusDetail) +{ + ccb_t *pccb = (ccb_t*)arg; + ag_card_t *pCard; + + static int callNum = 0; + + callNum++; + + BUG_ON(!pccb); + + if ((callNum % CMDS_PER_IO_DUP) != 0) + { + goto err; + } + + pccb->ccbStatus = IOStatus; + pccb->scsiStatus = statusDetail; + + /* pccb->pSenseData is copied already */ + + if (pccb->flags & AGTIAPI_ABORT) + { + AGTIAPI_PRINTK("agtiapi_SuperIOCb: aborted ccb %p, flag %x\n", + pccb, pccb->flags); + pccb->startTime = 0; /* indicate aborted IO completion */ + BUG_ON(1); + goto err; + } + pCard = TIROOT_TO_CARD(ptiRoot); + pccb->flags |= REQ_DONE; + agtiapi_QueueCCB(pCard, &pCard->ccbDoneHead, &pCard->ccbDoneTail + AG_CARD_LOCAL_LOCK(&pCard->doneLock), pccb); +err: + return; +} /* osti_FastIOCb */ +#endif + + +/****************************************************************************** +ostiSingleThreadedEnter() + +Purpose: + Critical region code excution protection. +Parameters: + tiRoot_t *ptiRoot (IN) Pointer to tiRoot data structure + U32 queueId (IN) spinlock Id +Returns: +Note: + Lock is held by oslayer. +******************************************************************************/ +void +ostiSingleThreadedEnter(tiRoot_t *ptiRoot, U32 queueId) +{ + struct agtiapi_softc *pCard = TIROOT_TO_CARD(ptiRoot); + mtx_lock( &pCard->STLock[queueId] ); // review: need irq save? ## +} + + +/****************************************************************************** +ostiSingleThreadedLeave() + +Purpose: + Restore multi-threading environment. +Parameters: + tiRoot_t *ptiRoot (IN) Pointer to the tiRoot data structure + U32 queueId (IN) spinlock Id +Returns: +Note: + Lock is held by oslayer. +******************************************************************************/ +void +ostiSingleThreadedLeave(tiRoot_t *ptiRoot, U32 queueId) +{ + struct agtiapi_softc *pCard = TIROOT_TO_CARD(ptiRoot); + mtx_unlock( &pCard->STLock[queueId] ); // review: need irq restore? ## +} + + +osGLOBAL tiDeviceHandle_t* +ostiMapToDevHandle(tiRoot_t *root, + bit8 pathId, + bit8 targetId, + bit8 LUN + ) +{ + tiDeviceHandle_t *dev = NULL; + struct agtiapi_softc *pCard; + bit32 offset; + + pCard = TIROOT_TO_CARD(root); + + offset = pathId * pCard->tgtCount + targetId; + + if (offset > (pCard->tgtCount - 1) ) + { + dev = NULL; + } + else + { + dev = pCard->pDevList[offset].pDevHandle; + } + + return dev; +} + + + +#ifdef PERF_COUNT + +#ifdef AGTIAPI_LOCAL_LOCK +#define OSTI_SPIN_LOCK(lock) spin_lock(lock) +#define OSTI_SPIN_UNLOCK(lock) spin_unlock(lock) +#else +#define OSTI_SPIN_LOCK(lock) +#define OSTI_SPIN_UNLOCK(lock) +#endif + + +void +ostiEnter(tiRoot_t *ptiRoot, U32 layer, int io) +{ + ag_card_t *pCard = ((ag_card_info_t*)ptiRoot->osData)->pCard; + int ini = ((pCard->flags & AGTIAPI_INIT_TIME) == AGTIAPI_INIT_TIME); + + BUG_ON((io != 0 && io != 1) || (layer != 0 && layer != 1 && layer != 2)); + if (!ini) + { + unsigned long long cycles = get_cycles(); + + OSTI_SPIN_LOCK(&pCard->latLock); + BUG_ON(pCard->callLevel[io] >= sizeof(pCard->layer[0]) / + sizeof(pCard->layer[0][0])); + if (pCard->callLevel[io] > 0) + { + unsigned int prev_layer = pCard->layer[io][pCard->callLevel[io] - 1]; + + pCard->totalCycles[io][prev_layer] += cycles - + pCard->enterCycles[io][prev_layer]; + } + pCard->enterCycles[io][layer] = cycles; + pCard->layer[io][pCard->callLevel[io]] = layer; + pCard->callLevel[io]++; + OSTI_SPIN_UNLOCK(&pCard->latLock); + } +} + +void +ostiLeave(tiRoot_t *ptiRoot, U32 layer, int io) +{ + ag_card_t *pCard = ((ag_card_info_t*)ptiRoot->osData)->pCard; + int ini = ((pCard->flags & AGTIAPI_INIT_TIME) == AGTIAPI_INIT_TIME); + + BUG_ON((io != 0 && io != 1) || (layer != 0 && layer != 1 && layer != 2)); + if (!ini) + { + unsigned long long cycles = get_cycles(); + + OSTI_SPIN_LOCK(&pCard->latLock); + pCard->callLevel[io]--; + + BUG_ON(pCard->callLevel[io] < 0); + BUG_ON(pCard->layer[io][pCard->callLevel[io]] != layer); + + pCard->totalCycles[io][layer] += cycles - pCard->enterCycles[io][layer]; + if (pCard->callLevel[io] > 0) + pCard->enterCycles[io][pCard->layer[io][pCard->callLevel[io] - 1]] = + cycles; + OSTI_SPIN_UNLOCK(&pCard->latLock); + } +} +#endif + + + +osGLOBAL FORCEINLINE bit8 +ostiBitScanForward( + tiRoot_t *root, + bit32 *Index, + bit32 Mask + ) +{ + return 1; + +} + +#ifdef REMOVED +osGLOBAL sbit32 +ostiAtomicIncrement( + tiRoot_t *root, + sbit32 volatile *Addend + ) +{ + return 1; + +} + +osGLOBAL sbit32 +ostiAtomicDecrement( + tiRoot_t *root, + sbit32 volatile *Addend + ) +{ + + return 1; + +} + +osGLOBAL sbit32 +ostiAtomicBitClear( + tiRoot_t *root, + sbit32 volatile *Destination, + sbit32 Value + ) +{ + + return 0; + +} + +osGLOBAL sbit32 +ostiAtomicBitSet( + tiRoot_t *root, + sbit32 volatile *Destination, + sbit32 Value + ) +{ + return 0; + + /* + set_bit(Value, (volatile unsigned long *)Destination); + return 0; + */ +} + +osGLOBAL sbit32 +ostiAtomicExchange( + tiRoot_t *root, + sbit32 volatile *Target, + sbit32 Value + ) +{ + return 0; + +} +#endif + +osGLOBAL FORCEINLINE sbit32 +ostiInterlockedExchange( + tiRoot_t *root, + sbit32 volatile *Target, + sbit32 Value + ) +{ + return 0; +} + +osGLOBAL FORCEINLINE sbit32 +ostiInterlockedIncrement( + tiRoot_t *root, + sbit32 volatile *Addend + ) +{ + return 0; +} + +osGLOBAL FORCEINLINE sbit32 +ostiInterlockedDecrement( + tiRoot_t *root, + sbit32 volatile *Addend + ) +{ + return 0; +} + +osGLOBAL FORCEINLINE sbit32 +ostiInterlockedAnd( + tiRoot_t *root, + sbit32 volatile *Destination, + sbit32 Value + ) +{ + return 0; +} + +osGLOBAL FORCEINLINE sbit32 +ostiInterlockedOr( + tiRoot_t *root, + sbit32 volatile *Destination, + sbit32 Value + ) +{ + return 0; +} + +// this is just stub code to allow compile and use of the module ... +// now that a call to this function has been added with windows specific +// intentions. +osGLOBAL bit32 +ostiSetDeviceQueueDepth( tiRoot_t *tiRoot, + tiIORequest_t *tiIORequest, + bit32 QueueDepth + ) +{ + bit32 retVal = 0; + struct agtiapi_softc *pCard = TIROOT_TO_CARD(tiRoot); + ccb_t *pccb = (ccb_t *) tiIORequest->osData; + tiDeviceHandle_t *tiDeviceHandle = pccb->devHandle; + ag_device_t *pDevice = (ag_device_t *)tiDeviceHandle->osData; + AGTIAPI_PRINTK( "ostiSetDeviceQueueDepth stub only: root%p, req%p, qdeep%d\n", + tiRoot, tiIORequest, QueueDepth ); + pDevice->qdepth = QueueDepth; + return retVal; +} + + +// this is just stub code to allow compile and use of the module ... +// now that a call to this function has been added with windows specific +// intentions. +osGLOBAL void +ostiGetSenseKeyCount(tiRoot_t *root, + bit32 fIsClear, + void *SenseKeyCount, + bit32 length + ) +{ + AGTIAPI_PRINTK( "ostiGetSenseKeyCount stub only: rt%p, fcl%d, kyCt%p, ln%d\n", + root, fIsClear, SenseKeyCount, length ); +} + +osGLOBAL void +ostiGetSCSIStatusCount(tiRoot_t *root, + bit32 fIsClear, + void *ScsiStatusCount, + bit32 length + ) +{ + AGTIAPI_PRINTK( "ostiGetSCSIStatusCount: stub only rt%p, fcl%d, kyCt%p, ln%d\n", + root, fIsClear, ScsiStatusCount, length ); + +} + +osGLOBAL void ostiPCI_TRIGGER( tiRoot_t *tiRoot ) +{ + ostiChipReadBit32Ext(tiRoot, 0, 0x5C); + +} + +osGLOBAL bit32 +ostiNumOfLUNIOCTLreq( tiRoot_t *root, + void *param1, + void *param2, + void **tiRequestBody, + tiIORequest_t **tiIORequest + ) +{ + bit32 status = IOCTL_CALL_SUCCESS; + pccb_t pccb; + AGTIAPI_PRINTK("ostiNumOfLUNIOCTLreq: start\n"); + struct agtiapi_softc *pCard = TIROOT_TO_CARD(root); + /* get a ccb */ + if ((pccb = agtiapi_GetCCB(pCard)) == NULL) + { + printf("ostiNumOfLUNIOCTLreq - GetCCB ERROR\n"); + status = IOCTL_CALL_FAIL; + //BUG_ON(1); + } + + *tiIORequest = (tiIORequest_t*)&pccb->tiIORequest; + *tiRequestBody = &pccb->tdIOReqBody; + AGTIAPI_PRINTK("ostiNumOfLUNIOCTLreq:end\n"); + return status; +} + diff --git a/sys/dev/proto/proto.h b/sys/dev/proto/proto.h index 690d71fff85a..cf89512f6ea7 100644 --- a/sys/dev/proto/proto.h +++ b/sys/dev/proto/proto.h @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2014 Marcel Moolenaar + * Copyright (c) 2014, 2015 Marcel Moolenaar * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -61,6 +61,7 @@ extern char proto_driver_name[]; int proto_add_resource(struct proto_softc *, int, int, struct resource *); +int proto_probe(device_t dev, const char *prefix, char ***devnamesp); int proto_attach(device_t dev); int proto_detach(device_t dev); diff --git a/sys/dev/proto/proto_bus_isa.c b/sys/dev/proto/proto_bus_isa.c index 0bbd469c8636..e7438bf1b4d5 100644 --- a/sys/dev/proto/proto_bus_isa.c +++ b/sys/dev/proto/proto_bus_isa.c @@ -59,6 +59,9 @@ static driver_t proto_isa_driver = { sizeof(struct proto_softc), }; +static char proto_isa_prefix[] = "isa"; +static char **proto_isa_devnames; + static int proto_isa_probe(device_t dev) { @@ -77,12 +80,12 @@ proto_isa_probe(device_t dev) return (ENODEV); sb = sbuf_new_auto(); - sbuf_printf(sb, "isa:%#lx", rman_get_start(res)); + sbuf_printf(sb, "%s:%#lx", proto_isa_prefix, rman_get_start(res)); sbuf_finish(sb); device_set_desc_copy(dev, sbuf_data(sb)); sbuf_delete(sb); bus_release_resource(dev, type, rid, res); - return (BUS_PROBE_HOOVER); + return (proto_probe(dev, proto_isa_prefix, &proto_isa_devnames)); } static int diff --git a/sys/dev/proto/proto_bus_pci.c b/sys/dev/proto/proto_bus_pci.c index 2d47fe6923b7..38155ce7c624 100644 --- a/sys/dev/proto/proto_bus_pci.c +++ b/sys/dev/proto/proto_bus_pci.c @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2014 Marcel Moolenaar + * Copyright (c) 2014, 2015 Marcel Moolenaar * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -59,6 +59,9 @@ static driver_t proto_pci_driver = { sizeof(struct proto_softc), }; +static char proto_pci_prefix[] = "pci"; +static char **proto_pci_devnames; + static int proto_pci_probe(device_t dev) { @@ -68,12 +71,12 @@ proto_pci_probe(device_t dev) return (ENXIO); sb = sbuf_new_auto(); - sbuf_printf(sb, "pci%d:%d:%d:%d", pci_get_domain(dev), + sbuf_printf(sb, "%s%d:%d:%d:%d", proto_pci_prefix, pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev), pci_get_function(dev)); sbuf_finish(sb); device_set_desc_copy(dev, sbuf_data(sb)); sbuf_delete(sb); - return (BUS_PROBE_HOOVER); + return (proto_probe(dev, proto_pci_prefix, &proto_pci_devnames)); } static int diff --git a/sys/dev/proto/proto_core.c b/sys/dev/proto/proto_core.c index 420df2bd9612..817f58e5aff2 100644 --- a/sys/dev/proto/proto_core.c +++ b/sys/dev/proto/proto_core.c @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2014 Marcel Moolenaar + * Copyright (c) 2014, 2015 Marcel Moolenaar * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -119,6 +119,62 @@ proto_intr(void *arg) } #endif +int +proto_probe(device_t dev, const char *prefix, char ***devnamesp) +{ + char **devnames = *devnamesp; + const char *dn, *ep, *ev; + size_t pfxlen; + int idx, names; + + if (devnames == NULL) { + pfxlen = strlen(prefix); + names = 1; /* NULL pointer */ + ev = kern_getenv("hw.proto.attach"); + if (ev != NULL) { + dn = ev; + while (*dn != '\0') { + ep = dn; + while (*ep != ',' && *ep != '\0') + ep++; + if ((ep - dn) > pfxlen && + strncmp(dn, prefix, pfxlen) == 0) + names++; + dn = (*ep == ',') ? ep + 1 : ep; + } + } + devnames = malloc(names * sizeof(caddr_t), M_DEVBUF, + M_WAITOK | M_ZERO); + *devnamesp = devnames; + if (ev != NULL) { + dn = ev; + idx = 0; + while (*dn != '\0') { + ep = dn; + while (*ep != ',' && *ep != '\0') + ep++; + if ((ep - dn) > pfxlen && + strncmp(dn, prefix, pfxlen) == 0) { + devnames[idx] = malloc(ep - dn + 1, + M_DEVBUF, M_WAITOK | M_ZERO); + memcpy(devnames[idx], dn, ep - dn); + idx++; + } + dn = (*ep == ',') ? ep + 1 : ep; + } + freeenv(__DECONST(char *, ev)); + } + } + + dn = device_get_desc(dev); + while (*devnames != NULL) { + if (strcmp(dn, *devnames) == 0) + return (BUS_PROBE_SPECIFIC); + devnames++; + } + return (BUS_PROBE_HOOVER); +} + int proto_attach(device_t dev) { diff --git a/sys/dev/random/build.sh b/sys/dev/random/build.sh index 95800c1f3ba8..d1351c403c42 100755 --- a/sys/dev/random/build.sh +++ b/sys/dev/random/build.sh @@ -28,7 +28,14 @@ # # Basic script to build crude unit tests. # -cc -g -O0 -pthread -DRANDOM_DEBUG -DRANDOM_YARROW \ +# Diff-reduction checking between Yarrow and fortuna is done like so: +# +# $ diff -u -B <(sed -e 's/yarrow/wombat/g' \ +# -e 's/YARROW/WOMBAT/g' yarrow.c) \ +# <(sed -e 's/fortuna/wombat/g' \ +# -e 's/FORTUNA/WOMBAT/g' fortuna.c) | less +# +cc -g -O0 -pthread -DRANDOM_DEBUG \ -I../.. -lstdthreads -Wall \ unit_test.c \ yarrow.c \ @@ -39,7 +46,7 @@ cc -g -O0 -pthread -DRANDOM_DEBUG -DRANDOM_YARROW \ ../../crypto/sha2/sha256c.c \ -lz \ -o yunit_test -cc -g -O0 -pthread -DRANDOM_DEBUG -DRANDOM_FORTUNA \ +cc -g -O0 -pthread -DRANDOM_DEBUG \ -I../.. -lstdthreads -Wall \ unit_test.c \ fortuna.c \ diff --git a/sys/dev/random/fortuna.c b/sys/dev/random/fortuna.c index 00beaacf530c..2aafba4217e5 100644 --- a/sys/dev/random/fortuna.c +++ b/sys/dev/random/fortuna.c @@ -39,10 +39,8 @@ __FBSDID("$FreeBSD$"); #ifdef _KERNEL #include #include -#include #include #include -#include #include #include #include @@ -71,6 +69,7 @@ __FBSDID("$FreeBSD$"); #include #include +#include #include #include #endif /* _KERNEL */ @@ -125,26 +124,27 @@ static uint8_t zero_region[RANDOM_ZERO_BLOCKSIZE]; static void random_fortuna_pre_read(void); static void random_fortuna_read(uint8_t *, u_int); -static void random_fortuna_post_read(void); static void random_fortuna_write(uint8_t *, u_int); static void random_fortuna_reseed(void); static int random_fortuna_seeded(void); static void random_fortuna_process_event(struct harvest_event *); +static void random_fortuna_init_alg(void *); +static void random_fortuna_deinit_alg(void *); + +static void random_fortuna_reseed_internal(uint32_t *entropy_data, u_int blockcount); -#ifdef _KERNEL -/* Interface to Adaptors system */ struct random_algorithm random_alg_context = { .ra_ident = "Fortuna", + .ra_init_alg = random_fortuna_init_alg, + .ra_deinit_alg = random_fortuna_deinit_alg, .ra_pre_read = random_fortuna_pre_read, .ra_read = random_fortuna_read, - .ra_post_read = random_fortuna_post_read, .ra_write = random_fortuna_write, .ra_reseed = random_fortuna_reseed, .ra_seeded = random_fortuna_seeded, .ra_event_processor = random_fortuna_process_event, .ra_poolcount = RANDOM_FORTUNA_NPOOLS, }; -#endif /* ARGSUSED */ static void @@ -194,9 +194,6 @@ random_fortuna_init_alg(void *unused __unused) fortuna_state.fs_counter = UINT128_ZERO; explicit_bzero(&fortuna_state.fs_key, sizeof(fortuna_state.fs_key)); } -#ifdef _KERNEL -SYSINIT(random_fortuna, SI_SUB_RANDOM, SI_ORDER_THIRD, random_fortuna_init_alg, NULL); -#endif /* ARGSUSED */ static void @@ -209,15 +206,12 @@ random_fortuna_deinit_alg(void *unused __unused) sysctl_ctx_free(&random_clist); #endif } -#ifdef _KERNEL -SYSUNINIT(random_fortuna, SI_SUB_RANDOM, SI_ORDER_THIRD, random_fortuna_deinit_alg, NULL); -#endif /*- * FS&K - AddRandomEvent() * Process a single stochastic event off the harvest queue */ -void +static void random_fortuna_process_event(struct harvest_event *event) { u_int pl; @@ -250,29 +244,6 @@ random_fortuna_process_event(struct harvest_event *event) RANDOM_RESEED_UNLOCK(); } -/*- - * Process a block of data suspected to be slightly stochastic. - * Do this by breaking it up and inserting the pieces as if - * they were separate events. - */ -static void -random_fortuna_process_buffer(uint32_t *buf, u_int wordcount) -{ - static struct harvest_event event; - static u_int destination = 0; - int i; - - for (i = 0; i < wordcount; i += sizeof(event.he_entropy)/sizeof(event.he_entropy[0])) { - event.he_somecounter = (uint32_t)get_cyclecount(); - event.he_size = sizeof(event.he_entropy); - event.he_bits = event.he_size/8; - event.he_source = RANDOM_CACHED; - event.he_destination = destination++; /* Harmless cheating */ - memcpy(event.he_entropy, buf + i, sizeof(event.he_entropy)); - random_fortuna_process_event(&event); - } -} - /*- * FS&K - Reseed() * This introduces new key material into the output generator. @@ -358,13 +329,10 @@ random_fortuna_genrandom(uint8_t *buf, u_int bytecount) } /*- - * FS&K - RandomData() - * Used to return processed entropy from the PRNG. - * There is a pre_read and a post_read required to be present - * (but they can be null functions) in order to allow specific - * actions at the begin or the end of a read. Fortuna does its - * reseeding in the _pre_read() part, and _post_read() is not - * used. + * FS&K - RandomData() (Part 1) + * Used to return processed entropy from the PRNG. There is a pre_read + * required to be present (but it can be a stub) in order to allow + * specific actions at the begin of the read. */ void random_fortuna_pre_read(void) @@ -435,8 +403,10 @@ random_fortuna_pre_read(void) } /*- - * Main read from Fortuna. - * The supplied buf MUST be a multiple (>=0) of RANDOM_BLOCKSIZE in size. + * FS&K - RandomData() (Part 2) + * Main read from Fortuna, continued. May be called multiple times after + * the random_fortuna_pre_read() above. + * The supplied buf MUST be a multiple of RANDOM_BLOCKSIZE in size. * Lots of code presumes this for efficiency, both here and in other * routines. You are NOT allowed to break this! */ @@ -444,24 +414,21 @@ void random_fortuna_read(uint8_t *buf, u_int bytecount) { + KASSERT((bytecount % RANDOM_BLOCKSIZE) == 0, ("%s(): bytecount (= %d) must be a multiple of %d", __func__, bytecount, RANDOM_BLOCKSIZE )); RANDOM_RESEED_LOCK(); random_fortuna_genrandom(buf, bytecount); RANDOM_RESEED_UNLOCK(); } -void -random_fortuna_post_read(void) -{ - - /* CWOT */ -} - /* Internal function to hand external entropy to the PRNG. */ void random_fortuna_write(uint8_t *buf, u_int count) { + static u_int destination = 0; + struct harvest_event event; struct randomdev_hash hash; uint32_t entropy_data[RANDOM_KEYSIZE_WORDS], timestamp; + int i; /* Extra timing here is helpful to scrape scheduler timing entropy */ randomdev_hash_init(&hash); @@ -472,15 +439,21 @@ random_fortuna_write(uint8_t *buf, u_int count) randomdev_hash_iterate(&hash, ×tamp, sizeof(timestamp)); randomdev_hash_finish(&hash, entropy_data); explicit_bzero(&hash, sizeof(hash)); - random_fortuna_process_buffer(entropy_data, sizeof(entropy_data)/sizeof(entropy_data[0])); + for (i = 0; i < RANDOM_KEYSIZE_WORDS; i += sizeof(event.he_entropy)/sizeof(event.he_entropy[0])) { + event.he_somecounter = (uint32_t)get_cyclecount(); + event.he_size = sizeof(event.he_entropy); + event.he_bits = event.he_size/8; + event.he_source = RANDOM_CACHED; + event.he_destination = destination++; /* Harmless cheating */ + memcpy(event.he_entropy, entropy_data + i, sizeof(event.he_entropy)); + random_fortuna_process_event(&event); + } explicit_bzero(entropy_data, sizeof(entropy_data)); } void random_fortuna_reseed(void) { - - /* CWOT */ } int diff --git a/sys/dev/random/hash.h b/sys/dev/random/hash.h index ef7a922027af..41dcf9089f0e 100644 --- a/sys/dev/random/hash.h +++ b/sys/dev/random/hash.h @@ -29,18 +29,21 @@ #ifndef SYS_DEV_RANDOM_HASH_H_INCLUDED #define SYS_DEV_RANDOM_HASH_H_INCLUDED +/* Keys are formed from cipher blocks */ #define RANDOM_KEYSIZE 32 /* (in bytes) == 256 bits */ #define RANDOM_KEYSIZE_WORDS (RANDOM_KEYSIZE/sizeof(uint32_t)) #define RANDOM_BLOCKSIZE 16 /* (in bytes) == 128 bits */ #define RANDOM_BLOCKSIZE_WORDS (RANDOM_BLOCKSIZE/sizeof(uint32_t)) #define RANDOM_KEYS_PER_BLOCK (RANDOM_KEYSIZE/RANDOM_BLOCKSIZE) + +/* The size of the zero block portion used to form H_d(m) */ #define RANDOM_ZERO_BLOCKSIZE 64 /* (in bytes) == 512 zero bits */ -struct randomdev_hash { /* Big! Make static! */ +struct randomdev_hash { SHA256_CTX sha; }; -struct randomdev_key { /* Big! Make static! */ +struct randomdev_key { keyInstance key; /* Key schedule */ cipherInstance cipher; /* Rijndael internal */ }; diff --git a/sys/dev/random/random_harvestq.c b/sys/dev/random/random_harvestq.c index 93c1ed532b0c..34a809be00f9 100644 --- a/sys/dev/random/random_harvestq.c +++ b/sys/dev/random/random_harvestq.c @@ -74,8 +74,8 @@ volatile int random_kthread_control; * this make is a bit easier to lock and protect. */ static struct harvest_context { - /* The harvest mutex protects the consistency of the entropy Fifos and - * empty fifo and other associated structures. + /* The harvest mutex protects all of harvest_context and + * the related data. */ struct mtx hc_mtx; /* Round-robin destination cache. */ @@ -95,6 +95,9 @@ static struct harvest_context { * If (ring.in + 1) == ring.out (mod RANDOM_RING_MAX), * the buffer is full. * + * NOTE: ring.in points to the last added element, + * and ring.out points to the last consumed element. + * * The ring.in variable needs locking as there are multiple * sources to the ring. Only the sources may change ring.in, * but the consumer may examine it. @@ -110,7 +113,7 @@ static struct harvest_context { } hc_entropy_ring; struct fast_entropy_accumulator { volatile u_int pos; - uint32_t buf[8]; + uint32_t buf[RANDOM_ACCUM_MAX]; } hc_entropy_fast_accumulator; } harvest_context; @@ -150,7 +153,7 @@ random_kthread(void) break; } random_sources_feed(); - /* XXX: FIX!! This This seems a little slow; 8 items every 0.1s from UMA? */ + /* XXX: FIX!! Increase the high-performance data rate? Need some measurements first. */ for (i = 0; i < RANDOM_ACCUM_MAX; i++) { if (harvest_context.hc_entropy_fast_accumulator.buf[i]) { random_harvest_direct(harvest_context.hc_entropy_fast_accumulator.buf + i, sizeof(harvest_context.hc_entropy_fast_accumulator.buf[0]), 4, RANDOM_FAST); @@ -238,8 +241,6 @@ random_harvestq_init(void *unused __unused) { struct sysctl_oid *random_sys_o; - if (bootverbose) - printf("random: %s\n", __func__); random_sys_o = SYSCTL_ADD_NODE(&random_clist, SYSCTL_STATIC_CHILDREN(_kern_random), OID_AUTO, "harvest", CTLFLAG_RW, 0, @@ -285,6 +286,8 @@ random_harvestq_prime(void *unused __unused) if (keyfile != NULL) { data = preload_fetch_addr(keyfile); size = preload_fetch_size(keyfile); + /* Trim the size. If the admin has a file with a funny size, we lose some. Tough. */ + size -= (size % sizeof(event.he_entropy)); if (data != NULL && size != 0) { for (i = 0; i < size; i += sizeof(event.he_entropy)) { count = sizeof(event.he_entropy); @@ -314,7 +317,7 @@ random_harvestq_deinit(void *unused __unused) /* Command the hash/reseed thread to end and wait for it to finish */ random_kthread_control = 0; - tsleep(&harvest_context.hc_kthread_proc, 0, "term", 0); + tsleep(&harvest_context.hc_kthread_proc, 0, "harvqterm", 0); sysctl_ctx_free(&random_clist); } SYSUNINIT(random_device_h_init, SI_SUB_RANDOM, SI_ORDER_SECOND, random_harvestq_deinit, NULL); @@ -334,7 +337,7 @@ SYSUNINIT(random_device_h_init, SI_SUB_RANDOM, SI_ORDER_SECOND, random_harvestq_ * read which can be quite expensive. */ void -random_harvest_queue(const void *entropy, u_int count, u_int bits, enum random_entropy_source origin) +random_harvest_queue(const void *entropy, u_int size, u_int bits, enum random_entropy_source origin) { struct harvest_event *event; u_int ring_in; @@ -351,14 +354,14 @@ random_harvest_queue(const void *entropy, u_int count, u_int bits, enum random_e event->he_source = origin; event->he_destination = harvest_context.hc_destination[origin]++; event->he_bits = bits; - if (count <= sizeof(event->he_entropy)) { - event->he_size = count; - memcpy(event->he_entropy, entropy, count); + if (size <= sizeof(event->he_entropy)) { + event->he_size = size; + memcpy(event->he_entropy, entropy, size); } else { /* Big event, so squash it */ event->he_size = sizeof(event->he_entropy[0]); - event->he_entropy[0] = jenkins_hash(entropy, count, (uint32_t)(uintptr_t)event); + event->he_entropy[0] = jenkins_hash(entropy, size, (uint32_t)(uintptr_t)event); } harvest_context.hc_entropy_ring.in = ring_in; } @@ -372,7 +375,7 @@ random_harvest_queue(const void *entropy, u_int count, u_int bits, enum random_e * This is the right place for high-rate harvested data. */ void -random_harvest_fast(const void *entropy, u_int count, u_int bits, enum random_entropy_source origin) +random_harvest_fast(const void *entropy, u_int size, u_int bits, enum random_entropy_source origin) { u_int pos; @@ -381,7 +384,7 @@ random_harvest_fast(const void *entropy, u_int count, u_int bits, enum random_en if (!(harvest_context.hc_source_mask & (1 << origin))) return; pos = harvest_context.hc_entropy_fast_accumulator.pos; - harvest_context.hc_entropy_fast_accumulator.buf[pos] ^= jenkins_hash(entropy, count, (uint32_t)get_cyclecount()); + harvest_context.hc_entropy_fast_accumulator.buf[pos] ^= jenkins_hash(entropy, size, (uint32_t)get_cyclecount()); harvest_context.hc_entropy_fast_accumulator.pos = (pos + 1)%RANDOM_ACCUM_MAX; } @@ -392,20 +395,20 @@ random_harvest_fast(const void *entropy, u_int count, u_int bits, enum random_en * (e.g.) booting when initial entropy is being gathered. */ void -random_harvest_direct(const void *entropy, u_int count, u_int bits, enum random_entropy_source origin) +random_harvest_direct(const void *entropy, u_int size, u_int bits, enum random_entropy_source origin) { struct harvest_event event; KASSERT(origin >= RANDOM_START && origin < ENTROPYSOURCE, ("%s: origin %d invalid\n", __func__, origin)); if (!(harvest_context.hc_source_mask & (1 << origin))) return; - count = MIN(count, sizeof(event.he_entropy)); + size = MIN(size, sizeof(event.he_entropy)); event.he_somecounter = (uint32_t)get_cyclecount(); - event.he_size = count; + event.he_size = size; event.he_bits = bits; event.he_source = origin; event.he_destination = harvest_context.hc_destination[origin]++; - memcpy(event.he_entropy, entropy, count); + memcpy(event.he_entropy, entropy, size); random_harvestq_fast_process_event(&event); explicit_bzero(&event, sizeof(event)); } diff --git a/sys/dev/random/randomdev.c b/sys/dev/random/randomdev.c index 1d9dcbe5fd46..5c20c5d53452 100644 --- a/sys/dev/random/randomdev.c +++ b/sys/dev/random/randomdev.c @@ -62,7 +62,10 @@ __FBSDID("$FreeBSD$"); #error "Cannot define both RANDOM_DUMMY and RANDOM_YARROW" #endif -#define RANDOM_MINOR 0 +#define RANDOM_UNIT 0 + +/* Return the largest number >= x that is a multiple of m */ +#define CEIL_TO_MULTIPLE(x, m) ((((x) + (m) - 1)/(m))*(m)) static d_read_t randomdev_read; static d_write_t randomdev_write; @@ -107,12 +110,13 @@ dummy_random(void) struct random_algorithm random_alg_context = { .ra_ident = "Dummy", - .ra_reseed = dummy_random, - .ra_seeded = (random_alg_seeded_t *)dummy_random_zero, + .ra_init_alg = NULL, + .ra_deinit_alg = NULL, .ra_pre_read = dummy_random, .ra_read = (random_alg_read_t *)dummy_random_zero, - .ra_post_read = dummy_random, .ra_write = (random_alg_write_t *)dummy_random_zero, + .ra_reseed = dummy_random, + .ra_seeded = (random_alg_seeded_t *)dummy_random_zero, .ra_event_processor = NULL, .ra_poolcount = 0, }; @@ -123,6 +127,23 @@ LIST_HEAD(sources_head, random_sources); static struct sources_head source_list = LIST_HEAD_INITIALIZER(source_list); static u_int read_rate; +static void +random_alg_context_ra_init_alg(void *data) +{ + + random_alg_context.ra_init_alg(data); +} + +static void +random_alg_context_ra_deinit_alg(void *data) +{ + + random_alg_context.ra_deinit_alg(data); +} + +SYSINIT(random_device, SI_SUB_RANDOM, SI_ORDER_THIRD, random_alg_context_ra_init_alg, NULL); +SYSUNINIT(random_device, SI_SUB_RANDOM, SI_ORDER_THIRD, random_alg_context_ra_deinit_alg, NULL); + #endif /* defined(RANDOM_DUMMY) */ static struct selinfo rsel; @@ -133,38 +154,61 @@ static struct selinfo rsel; /* ARGSUSED */ static int randomdev_read(struct cdev *dev __unused, struct uio *uio, int flags) +{ + + return (read_random_uio(uio, (flags & O_NONBLOCK) != 0)); +} + +int +read_random_uio(struct uio *uio, bool nonblock) { uint8_t *random_buf; - int c, error; - ssize_t nbytes; + int error, spamcount; + ssize_t read_len, total_read, c; random_buf = malloc(PAGE_SIZE, M_ENTROPY, M_WAITOK); random_alg_context.ra_pre_read(); - /* (Un)Blocking logic */ error = 0; - while (!random_alg_context.ra_seeded() && error == 0) { - if (flags & O_NONBLOCK) { + spamcount = 0; + /* (Un)Blocking logic */ + while (!random_alg_context.ra_seeded()) { + if (nonblock) { error = EWOULDBLOCK; break; } - tsleep(&random_alg_context, 0, "randrd", hz/10); /* keep tapping away at the pre-read until we seed/unblock. */ random_alg_context.ra_pre_read(); - printf("random: %s unblock (error = %d)\n", __func__, error); + /* Only bother the console every 10 seconds or so */ + if (spamcount == 0) + printf("random: %s unblock wait\n", __func__); + spamcount = (spamcount + 1)%100; + error = tsleep(&random_alg_context, PCATCH, "randseed", hz/10); + if (error == ERESTART || error == EINTR) + break; } if (error == 0) { #if !defined(RANDOM_DUMMY) /* XXX: FIX!! Next line as an atomic operation? */ read_rate += (uio->uio_resid + sizeof(uint32_t))/sizeof(uint32_t); #endif - nbytes = uio->uio_resid; + total_read = 0; while (uio->uio_resid && !error) { - c = MIN(uio->uio_resid, PAGE_SIZE); - random_alg_context.ra_read(random_buf, c); + read_len = uio->uio_resid; + /* + * Belt-and-braces. + * Round up the read length to a crypto block size multiple, + * which is what the underlying generator is expecting. + * See the random_buf size requirements in the Yarrow/Fortuna code. + */ + read_len = CEIL_TO_MULTIPLE(read_len, RANDOM_BLOCKSIZE); + /* Work in chunks page-sized or less */ + read_len = MIN(read_len, PAGE_SIZE); + random_alg_context.ra_read(random_buf, read_len); + c = MIN(uio->uio_resid, read_len); error = uiomove(random_buf, c, uio); + total_read += c; } - random_alg_context.ra_post_read(); - if (nbytes != uio->uio_resid && (error == ERESTART || error == EINTR) ) + if (total_read != uio->uio_resid && (error == ERESTART || error == EINTR)) /* Return partial read, not error. */ error = 0; } @@ -182,7 +226,7 @@ randomdev_read(struct cdev *dev __unused, struct uio *uio, int flags) u_int read_random(void *random_buf, u_int len) { - u_int read_len, total_read, c; + u_int read_len; uint8_t local_buf[len + RANDOM_BLOCKSIZE]; KASSERT(random_buf != NULL, ("No suitable random buffer in %s", __func__)); @@ -193,18 +237,18 @@ read_random(void *random_buf, u_int len) /* XXX: FIX!! Next line as an atomic operation? */ read_rate += (len + sizeof(uint32_t))/sizeof(uint32_t); #endif - read_len = len; - total_read = 0; - while (read_len) { - c = MIN(read_len, PAGE_SIZE); - random_alg_context.ra_read(&local_buf[total_read], c); - read_len -= c; - total_read += c; + if (len > 0) { + /* + * Belt-and-braces. + * Round up the read length to a crypto block size multiple, + * which is what the underlying generator is expecting. + */ + read_len = CEIL_TO_MULTIPLE(len, RANDOM_BLOCKSIZE); + random_alg_context.ra_read(local_buf, read_len); + memcpy(random_buf, local_buf, len); } - memcpy(random_buf, local_buf, len); } else len = 0; - random_alg_context.ra_post_read(); return (len); } @@ -382,7 +426,7 @@ randomdev_modevent(module_t mod __unused, int type, void *data __unused) case MOD_LOAD: printf("random: entropy device external interface\n"); random_dev = make_dev_credf(MAKEDEV_ETERNAL_KLD, &random_cdevsw, - RANDOM_MINOR, NULL, UID_ROOT, GID_WHEEL, 0644, "random"); + RANDOM_UNIT, NULL, UID_ROOT, GID_WHEEL, 0644, "random"); make_dev_alias(random_dev, "urandom"); /* compatibility */ break; case MOD_UNLOAD: diff --git a/sys/dev/random/randomdev.h b/sys/dev/random/randomdev.h index 0af741fb3b91..799efb1b0612 100644 --- a/sys/dev/random/randomdev.h +++ b/sys/dev/random/randomdev.h @@ -29,6 +29,8 @@ #ifndef SYS_DEV_RANDOM_RANDOMDEV_H_INCLUDED #define SYS_DEV_RANDOM_RANDOMDEV_H_INCLUDED +#ifdef _KERNEL + /* This header contains only those definitions that are global * and non algorithm-specific for the entropy processor */ @@ -55,11 +57,12 @@ MALLOC_DECLARE(M_ENTROPY); #define RANDOM_ALG_READ_RATE_MINIMUM 32 +#endif /* _KERNEL */ + struct harvest_event; typedef void random_alg_pre_read_t(void); typedef void random_alg_read_t(uint8_t *, u_int); -typedef void random_alg_post_read_t(void); typedef void random_alg_write_t(uint8_t *, u_int); typedef int random_alg_seeded_t(void); typedef void random_alg_reseed_t(void); @@ -74,9 +77,10 @@ typedef u_int random_source_read_t(void *, u_int); struct random_algorithm { const char *ra_ident; u_int ra_poolcount; + void (*ra_init_alg)(void *); + void (*ra_deinit_alg)(void *); random_alg_pre_read_t *ra_pre_read; random_alg_read_t *ra_read; - random_alg_post_read_t *ra_post_read; random_alg_write_t *ra_write; random_alg_reseed_t *ra_reseed; random_alg_seeded_t *ra_seeded; @@ -85,6 +89,8 @@ struct random_algorithm { extern struct random_algorithm random_alg_context; +#ifdef _KERNEL + /* * Random Source is a source of entropy that can provide * specified or approximate amount of entropy immediately @@ -108,6 +114,8 @@ void random_source_deregister(struct random_source *); void random_sources_feed(void); +#endif /* _KERNEL */ + void randomdev_unblock(void); #endif /* SYS_DEV_RANDOM_RANDOMDEV_H_INCLUDED */ diff --git a/sys/dev/random/unit_test.c b/sys/dev/random/unit_test.c index 80b32cf9bece..7ae571677049 100644 --- a/sys/dev/random/unit_test.c +++ b/sys/dev/random/unit_test.c @@ -52,15 +52,9 @@ Where is YARROW or FORTUNA. #include #include +#include "randomdev.h" #include "unit_test.h" -#ifdef RANDOM_YARROW -#include "dev/random/yarrow.h" -#endif -#ifdef RANDOM_FORTUNA -#include "dev/random/fortuna.h" -#endif - #define NUM_THREADS 3 #define DEBUG @@ -112,7 +106,7 @@ block_deflate(uint8_t *uncompr, uint8_t *compr, const size_t len) while (c_stream.total_in != len && c_stream.total_out < (len*2u + 512u)) { err = deflate(&c_stream, Z_NO_FLUSH); #ifdef DEBUG - printf("deflate: len = %zd total_in = %lu total_out = %lu\n", len, c_stream.total_in, c_stream.total_out); + printf("deflate progress: len = %zd total_in = %lu total_out = %lu\n", len, c_stream.total_in, c_stream.total_out); #endif check_err(err, "deflate(..., Z_NO_FLUSH)"); } @@ -120,7 +114,7 @@ block_deflate(uint8_t *uncompr, uint8_t *compr, const size_t len) for (;;) { err = deflate(&c_stream, Z_FINISH); #ifdef DEBUG - printf("deflate: len = %zd total_in = %lu total_out = %lu\n", len, c_stream.total_in, c_stream.total_out); + printf("deflate final: len = %zd total_in = %lu total_out = %lu\n", len, c_stream.total_in, c_stream.total_out); #endif if (err == Z_STREAM_END) break; check_err(err, "deflate(..., Z_STREAM_END)"); @@ -133,7 +127,7 @@ block_deflate(uint8_t *uncompr, uint8_t *compr, const size_t len) } void -random_adaptor_unblock(void) +randomdev_unblock(void) { #if 0 @@ -166,12 +160,7 @@ RunHarvester(void *arg __unused) e.he_destination = i; e.he_source = (i + 3)%7; e.he_next = NULL; -#ifdef RANDOM_YARROW - random_yarrow_process_event(&e); -#endif -#ifdef RANDOM_FORTUNA - random_fortuna_process_event(&e); -#endif + random_alg_context.ra_event_processor(&e); usleep(r); } @@ -198,12 +187,7 @@ WriteCSPRNG(void *threadid) printf("Thread write 1 - %d\n", i); if (buf != NULL) { printf("Thread 1 writing.\n"); -#ifdef RANDOM_YARROW - random_yarrow_write(buf, i); -#endif -#ifdef RANDOM_FORTUNA - random_fortuna_write(buf, i); -#endif + random_alg_context.ra_write(buf, i); free(buf); } usleep(1000000); @@ -220,6 +204,7 @@ static int ReadCSPRNG(void *threadid) { size_t tid, zsize; + u_int buffersize; uint8_t *buf, *zbuf; int i; #ifdef DEBUG @@ -229,40 +214,22 @@ ReadCSPRNG(void *threadid) tid = (size_t)threadid; printf("Thread #%zd starts\n", tid); -#ifdef RANDOM_YARROW - while (!random_yarrow_seeded()) -#endif -#ifdef RANDOM_FORTUNA - while (!random_fortuna_seeded()) -#endif + while (!random_alg_context.ra_seeded()) { -#ifdef RANDOM_YARROW - random_yarrow_pre_read(); - random_yarrow_post_read(); -#endif -#ifdef RANDOM_FORTUNA - random_fortuna_pre_read(); - random_fortuna_post_read(); -#endif + random_alg_context.ra_pre_read(); usleep(100); } for (i = 0; i < 100000; i++) { - buf = malloc(i); + buffersize = i + RANDOM_BLOCKSIZE; + buffersize -= buffersize%RANDOM_BLOCKSIZE; + buf = malloc(buffersize); zbuf = malloc(2*i + 1024); if (i % 1000 == 0) printf("Thread read %zd - %d\n", tid, i); if (buf != NULL && zbuf != NULL) { -#ifdef RANDOM_YARROW - random_yarrow_pre_read(); - random_yarrow_read(buf, i); - random_yarrow_post_read(); -#endif -#ifdef RANDOM_FORTUNA - random_fortuna_pre_read(); - random_fortuna_read(buf, i); - random_fortuna_post_read(); -#endif + random_alg_context.ra_pre_read(); + random_alg_context.ra_read(buf, buffersize); zsize = block_deflate(buf, zbuf, i); if (zsize < i) printf("ERROR!! Compressible RNG output!\n"); @@ -300,12 +267,7 @@ main(int argc, char *argv[]) int rc; long t; -#ifdef RANDOM_YARROW - random_yarrow_init_alg(); -#endif -#ifdef RANDOM_FORTUNA - random_fortuna_init_alg(); -#endif + random_alg_context.ra_init_alg(NULL); for (t = 0; t < NUM_THREADS; t++) { printf("In main: creating thread %ld\n", t); @@ -324,12 +286,7 @@ main(int argc, char *argv[]) thrd_join(threads[1], &rc); thrd_join(threads[0], &rc); -#ifdef RANDOM_YARROW - random_yarrow_deinit_alg(); -#endif -#ifdef RANDOM_FORTUNA - random_fortuna_deinit_alg(); -#endif + random_alg_context.ra_deinit_alg(NULL); /* Last thing that main() should do */ thrd_exit(0); diff --git a/sys/dev/random/unit_test.h b/sys/dev/random/unit_test.h index 648d2943322c..3c05ad0bf0f6 100644 --- a/sys/dev/random/unit_test.h +++ b/sys/dev/random/unit_test.h @@ -34,7 +34,9 @@ #error "Random unit tests cannot be compiled into the kernel." #endif -void random_adaptor_unblock(void); +#include +#include +#include #if defined(clang) && __has_builtin(__builtin_readcyclecounter) #define rdtsc __builtin_readcyclecounter @@ -61,6 +63,7 @@ get_cyclecount(void) } #define HARVESTSIZE 2 +#define RANDOM_BLOCKSIZE 16 enum random_entropy_source { RANDOM_START = 0, diff --git a/sys/dev/random/yarrow.c b/sys/dev/random/yarrow.c index 540d643022da..d6ebd46102ca 100644 --- a/sys/dev/random/yarrow.c +++ b/sys/dev/random/yarrow.c @@ -30,11 +30,8 @@ __FBSDID("$FreeBSD$"); #ifdef _KERNEL #include -#include -#include #include #include -#include #include #include #include @@ -54,6 +51,7 @@ __FBSDID("$FreeBSD$"); #include #include #include +#include #include #include @@ -63,6 +61,7 @@ __FBSDID("$FreeBSD$"); #include #include +#include #include #include #endif /* _KERNEL */ @@ -109,27 +108,27 @@ RANDOM_CHECK_UINT(slowoverthresh, 1, 5); static void random_yarrow_pre_read(void); static void random_yarrow_read(uint8_t *, u_int); -static void random_yarrow_post_read(void); static void random_yarrow_write(uint8_t *, u_int); static void random_yarrow_reseed(void); static int random_yarrow_seeded(void); -static void random_yarrow_reseed_internal(u_int); static void random_yarrow_process_event(struct harvest_event *); +static void random_yarrow_init_alg(void *); +static void random_yarrow_deinit_alg(void *); + +static void random_yarrow_reseed_internal(u_int); -#ifdef _KERNEL -/* Interface to Adaptors system */ struct random_algorithm random_alg_context = { .ra_ident = "Yarrow", + .ra_init_alg = random_yarrow_init_alg, + .ra_deinit_alg = random_yarrow_deinit_alg, .ra_pre_read = random_yarrow_pre_read, .ra_read = random_yarrow_read, - .ra_post_read = random_yarrow_post_read, .ra_write = random_yarrow_write, .ra_reseed = random_yarrow_reseed, .ra_seeded = random_yarrow_seeded, .ra_event_processor = random_yarrow_process_event, .ra_poolcount = RANDOM_YARROW_NPOOLS, }; -#endif /* ARGSUSED */ static void @@ -199,9 +198,6 @@ random_yarrow_init_alg(void *unused __unused) /* Clear the counter */ yarrow_state.ys_counter = UINT128_ZERO; } -#ifdef _KERNEL -SYSINIT(random_yarrow, SI_SUB_RANDOM, SI_ORDER_THIRD, random_yarrow_init_alg, NULL); -#endif /* ARGSUSED */ static void @@ -214,9 +210,6 @@ random_yarrow_deinit_alg(void *unused __unused) sysctl_ctx_free(&random_clist); #endif } -#ifdef _KERNEL -SYSUNINIT(random_yarrow, SI_SUB_RANDOM, SI_ORDER_THIRD, random_yarrow_deinit_alg, NULL); -#endif /* Process a single stochastic event off the harvest queue */ static void @@ -255,25 +248,6 @@ random_yarrow_process_event(struct harvest_event *event) RANDOM_RESEED_UNLOCK(); } -/* Process a block of data suspected to be slightly stochastic. */ -static void -random_yarrow_process_buffer(uint32_t *buf, u_int wordcount) -{ - static struct harvest_event event; - static u_int destination = 0; - int i; - - for (i = 0; i < wordcount; i += sizeof(event.he_entropy)/sizeof(event.he_entropy[0])) { - event.he_somecounter = (uint32_t)get_cyclecount(); - event.he_size = sizeof(event.he_entropy); - event.he_bits = event.he_size/8; - event.he_source = RANDOM_CACHED; - event.he_destination = destination++; /* Harmless cheating */ - memcpy(event.he_entropy, buf + i, sizeof(event.he_entropy)); - random_yarrow_process_event(&event); - } -} - static void random_yarrow_reseed_internal(u_int fastslow) { @@ -384,12 +358,11 @@ random_yarrow_generator_gate(void) } /*- - * Used to return processed entropy from the PRNG. - * There is a pre_read and a post_read required to be present - * (but they can be null functions) in order to allow specific - * actions at the begin or the end of a read. Yarrow does its - * reseeding in its own thread. The _pre_read() and _post_read() - * are not used here, and must be kept for completeness. + * Used to return processed entropy from the PRNG. There is a pre_read + * required to be present (but it can be a stub) in order to allow + * specific actions at the begin of the read. + * Yarrow does its reseeding in its own thread; _pre_read() is not used + * by Yarrow but must be kept for completeness. */ void random_yarrow_pre_read(void) @@ -407,6 +380,7 @@ random_yarrow_read(uint8_t *buf, u_int bytecount) { u_int blockcount, i; + KASSERT((bytecount % RANDOM_BLOCKSIZE) == 0, ("%s(): bytecount (= %d) must be a multiple of %d", __func__, bytecount, RANDOM_BLOCKSIZE )); RANDOM_RESEED_LOCK(); blockcount = (bytecount + RANDOM_BLOCKSIZE - 1)/RANDOM_BLOCKSIZE; for (i = 0; i < blockcount; i++) { @@ -421,19 +395,15 @@ random_yarrow_read(uint8_t *buf, u_int bytecount) RANDOM_RESEED_UNLOCK(); } -void -random_yarrow_post_read(void) -{ - - /* CWOT */ -} - /* Internal function to hand external entropy to the PRNG. */ void random_yarrow_write(uint8_t *buf, u_int count) { + static u_int destination = 0; + static struct harvest_event event; struct randomdev_hash hash; uint32_t entropy_data[RANDOM_KEYSIZE_WORDS], timestamp; + int i; /* Extra timing here is helpful to scrape scheduler timing entropy */ randomdev_hash_init(&hash); @@ -444,7 +414,15 @@ random_yarrow_write(uint8_t *buf, u_int count) randomdev_hash_iterate(&hash, ×tamp, sizeof(timestamp)); randomdev_hash_finish(&hash, entropy_data); explicit_bzero(&hash, sizeof(hash)); - random_yarrow_process_buffer(entropy_data, sizeof(entropy_data)/sizeof(entropy_data[0])); + for (i = 0; i < RANDOM_KEYSIZE_WORDS; i += sizeof(event.he_entropy)/sizeof(event.he_entropy[0])) { + event.he_somecounter = (uint32_t)get_cyclecount(); + event.he_size = sizeof(event.he_entropy); + event.he_bits = event.he_size/8; + event.he_source = RANDOM_CACHED; + event.he_destination = destination++; /* Harmless cheating */ + memcpy(event.he_entropy, entropy_data + i, sizeof(event.he_entropy)); + random_yarrow_process_event(&event); + } explicit_bzero(entropy_data, sizeof(entropy_data)); } diff --git a/sys/dev/re/if_re.c b/sys/dev/re/if_re.c index a67d367cfdf9..677d397a1c7a 100644 --- a/sys/dev/re/if_re.c +++ b/sys/dev/re/if_re.c @@ -304,6 +304,7 @@ static void re_set_linkspeed (struct rl_softc *); #ifdef DEV_NETMAP /* see ixgbe.c for details */ #include +MODULE_DEPEND(re, netmap, 1, 1, 1); #endif /* !DEV_NETMAP */ #ifdef RE_DIAG diff --git a/sys/dev/sound/pci/hda/hdaa_patches.c b/sys/dev/sound/pci/hda/hdaa_patches.c index 8852215faf14..548cb60d438a 100644 --- a/sys/dev/sound/pci/hda/hdaa_patches.c +++ b/sys/dev/sound/pci/hda/hdaa_patches.c @@ -696,6 +696,22 @@ hdaa_patch(struct hdaa_devinfo *devinfo) } } +static uint32_t +hdaa_read_coef(device_t dev, nid_t nid, uint16_t idx) +{ + + hda_command(dev, HDA_CMD_SET_COEFF_INDEX(0, nid, idx)); + return (hda_command(dev, HDA_CMD_GET_PROCESSING_COEFF(0, nid))); +} + +static uint32_t +hdaa_write_coef(device_t dev, nid_t nid, uint16_t idx, uint16_t val) +{ + + hda_command(dev, HDA_CMD_SET_COEFF_INDEX(0, nid, idx)); + return (hda_command(dev, HDA_CMD_SET_PROCESSING_COEFF(0, nid, val))); +} + void hdaa_patch_direct(struct hdaa_devinfo *devinfo) { @@ -737,10 +753,12 @@ hdaa_patch_direct(struct hdaa_devinfo *devinfo) * That results in silence if downmix it to mono. * To workaround, make codec to handle signal as mono. */ - hda_command(dev, HDA_CMD_SET_COEFF_INDEX(0, 0x20, 0x07)); - val = hda_command(dev, HDA_CMD_GET_PROCESSING_COEFF(0, 0x20)); - hda_command(dev, HDA_CMD_SET_COEFF_INDEX(0, 0x20, 0x07)); - hda_command(dev, HDA_CMD_SET_PROCESSING_COEFF(0, 0x20, val|0x80)); + val = hdaa_read_coef(dev, 0x20, 0x07); + hdaa_write_coef(dev, 0x20, 0x07, val|0x80); + } + if (subid == 0x15171043) { + /* Increase output amp on ASUS UX31A by +5dB. */ + hdaa_write_coef(dev, 0x20, 0x12, 0x2800); } } } diff --git a/sys/dev/uart/uart_core.c b/sys/dev/uart/uart_core.c index bbb06ff5c1f5..4114f375986e 100644 --- a/sys/dev/uart/uart_core.c +++ b/sys/dev/uart/uart_core.c @@ -39,6 +39,7 @@ __FBSDID("$FreeBSD$"); #include #include #include +#include #include #include #include @@ -62,7 +63,12 @@ static MALLOC_DEFINE(M_UART, "UART", "UART driver"); #define UART_POLL_FREQ 50 #endif static int uart_poll_freq = UART_POLL_FREQ; -TUNABLE_INT("debug.uart_poll_freq", &uart_poll_freq); +SYSCTL_INT(_debug, OID_AUTO, uart_poll_freq, CTLFLAG_RDTUN, &uart_poll_freq, + 0, "UART poll frequency"); + +static int uart_force_poll; +SYSCTL_INT(_debug, OID_AUTO, uart_force_poll, CTLFLAG_RDTUN, &uart_force_poll, + 0, "Force UART polling"); void uart_add_sysdev(struct uart_devinfo *di) @@ -514,7 +520,7 @@ uart_bus_attach(device_t dev) * conditions. We may have broken H/W and polling is probably the * safest thing to do. */ - if (filt != FILTER_SCHEDULE_THREAD) { + if (filt != FILTER_SCHEDULE_THREAD && !uart_force_poll) { sc->sc_irid = 0; sc->sc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irid, RF_ACTIVE | RF_SHAREABLE); @@ -540,6 +546,8 @@ uart_bus_attach(device_t dev) /* No interrupt resource. Force polled mode. */ sc->sc_polled = 1; callout_init(&sc->sc_timer, 1); + callout_reset(&sc->sc_timer, hz / uart_poll_freq, + (timeout_t *)uart_intr, sc); } if (bootverbose && (sc->sc_fastintr || sc->sc_polled)) { diff --git a/sys/dev/usb/controller/dwc_otg.c b/sys/dev/usb/controller/dwc_otg.c index 868c7c7e3461..17d792a5db54 100644 --- a/sys/dev/usb/controller/dwc_otg.c +++ b/sys/dev/usb/controller/dwc_otg.c @@ -1,5 +1,6 @@ /* $FreeBSD$ */ /*- + * Copyright (c) 2015 Daisuke Aoyama. All rights reserved. * Copyright (c) 2012 Hans Petter Selasky. All rights reserved. * Copyright (c) 2010-2011 Aleksandr Rybalko. All rights reserved. * @@ -151,7 +152,6 @@ static void dwc_otg_do_poll(struct usb_bus *); static void dwc_otg_standard_done(struct usb_xfer *); static void dwc_otg_root_intr(struct dwc_otg_softc *); static void dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *); -static void dwc_otg_host_channel_disable(struct dwc_otg_softc *, uint8_t); /* * Here is a configuration that the chip supports. @@ -224,7 +224,7 @@ dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode) /* split equally for IN and OUT */ fifo_size /= 2; - /* align to 4 bytes boundary */ + /* Align to 4 bytes boundary (refer to PGM) */ fifo_size &= ~3; /* set global receive FIFO size */ @@ -237,13 +237,6 @@ dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode) return (EINVAL); } - /* disable any leftover host channels */ - for (x = 0; x != sc->sc_host_ch_max; x++) { - if (sc->sc_chan_state[x].wait_sof == 0) - continue; - dwc_otg_host_channel_disable(sc, x); - } - if (mode == DWC_MODE_HOST) { /* reset active endpoints */ @@ -252,6 +245,8 @@ dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode) /* split equally for periodic and non-periodic */ fifo_size /= 2; + DPRINTF("PTX/NPTX FIFO=%u\n", fifo_size); + /* align to 4 bytes boundary */ fifo_size &= ~3; @@ -262,7 +257,7 @@ dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode) tx_start += fifo_size; for (x = 0; x != sc->sc_host_ch_max; x++) { - /* disable all host interrupts */ + /* enable all host interrupts */ DWC_OTG_WRITE_4(sc, DOTG_HCINTMSK(x), HCINT_DEFAULT_MASK); } @@ -274,13 +269,6 @@ dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode) /* reset host channel state */ memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state)); - /* reset FIFO TX levels */ - sc->sc_tx_cur_p_level = 0; - sc->sc_tx_cur_np_level = 0; - - /* store maximum periodic and non-periodic FIFO TX size */ - sc->sc_tx_max_size = fifo_size; - /* enable all host channel interrupts */ DWC_OTG_WRITE_4(sc, DOTG_HAINTMSK, (1U << sc->sc_host_ch_max) - 1U); @@ -358,15 +346,8 @@ dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode) /* reset active endpoints */ sc->sc_active_rx_ep = 0; - /* reset periodic and non-periodic FIFO TX size */ - sc->sc_tx_max_size = fifo_size; - /* reset host channel state */ memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state)); - - /* reset FIFO TX levels */ - sc->sc_tx_cur_p_level = 0; - sc->sc_tx_cur_np_level = 0; } return (0); } @@ -612,10 +593,39 @@ dwc_otg_clear_hcint(struct dwc_otg_softc *sc, uint8_t x) } static uint8_t -dwc_otg_host_channel_alloc(struct dwc_otg_softc *sc, struct dwc_otg_td *td, uint8_t is_out) +dwc_otg_host_check_fifo_empty(struct dwc_otg_softc *sc, struct dwc_otg_td *td) +{ + uint32_t temp; + + temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS); + + if (td->ep_type == UE_INTERRUPT || + td->ep_type == UE_ISOCHRONOUS) { + if (!(temp & GINTSTS_PTXFEMP)) { + DPRINTF("Periodic TX FIFO is not empty\n"); + if (!(sc->sc_irq_mask & GINTMSK_PTXFEMPMSK)) { + sc->sc_irq_mask |= GINTMSK_PTXFEMPMSK; + DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); + } + return (1); /* busy */ + } + } else { + if (!(temp & GINTSTS_NPTXFEMP)) { + DPRINTF("Non-periodic TX FIFO is not empty\n"); + if (!(sc->sc_irq_mask & GINTMSK_NPTXFEMPMSK)) { + sc->sc_irq_mask |= GINTMSK_NPTXFEMPMSK; + DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); + } + return (1); /* busy */ + } + } + return (0); /* ready for transmit */ +} + +static uint8_t +dwc_otg_host_channel_alloc(struct dwc_otg_softc *sc, + struct dwc_otg_td *td, uint8_t is_out) { - uint32_t tx_p_size; - uint32_t tx_np_size; uint8_t x; if (td->channel < DWC_OTG_MAX_CHANNELS) @@ -627,45 +637,19 @@ dwc_otg_host_channel_alloc(struct dwc_otg_softc *sc, struct dwc_otg_td *td, uint /* compute needed TX FIFO size */ if (is_out != 0) { - if (td->ep_type == UE_ISOCHRONOUS) { - tx_p_size = td->max_packet_size; - tx_np_size = 0; - if (td->hcsplt != 0 && tx_p_size > HCSPLT_XACTLEN_BURST) - tx_p_size = HCSPLT_XACTLEN_BURST; - if ((sc->sc_tx_cur_p_level + tx_p_size) > sc->sc_tx_max_size) { - DPRINTF("Too little FIFO space\n"); - return (1); /* too little FIFO */ - } - } else { - tx_p_size = 0; - tx_np_size = td->max_packet_size; - if (td->hcsplt != 0 && tx_np_size > HCSPLT_XACTLEN_BURST) - tx_np_size = HCSPLT_XACTLEN_BURST; - if ((sc->sc_tx_cur_np_level + tx_np_size) > sc->sc_tx_max_size) { - DPRINTF("Too little FIFO space\n"); - return (1); /* too little FIFO */ - } - } - } else { - /* not a TX transaction */ - tx_p_size = 0; - tx_np_size = 0; + if (dwc_otg_host_check_fifo_empty(sc, td) != 0) + return (1); /* busy - cannot transfer data */ } for (x = 0; x != sc->sc_host_ch_max; x++) { + /* check if channel is allocated */ if (sc->sc_chan_state[x].allocated != 0) continue; /* check if channel is still enabled */ - if (sc->sc_chan_state[x].wait_sof != 0) + if (sc->sc_chan_state[x].wait_halted != 0) continue; sc->sc_chan_state[x].allocated = 1; - sc->sc_chan_state[x].tx_p_size = tx_p_size; - sc->sc_chan_state[x].tx_np_size = tx_np_size; - - /* keep track of used TX FIFO, if any */ - sc->sc_tx_cur_p_level += tx_p_size; - sc->sc_tx_cur_np_level += tx_np_size; /* clear interrupts */ dwc_otg_clear_hcint(sc, x); @@ -689,6 +673,7 @@ dwc_otg_host_channel_alloc(struct dwc_otg_softc *sc, struct dwc_otg_td *td, uint static void dwc_otg_host_channel_free(struct dwc_otg_softc *sc, struct dwc_otg_td *td) { + uint32_t hcchar; uint8_t x; if (td->channel >= DWC_OTG_MAX_CHANNELS) @@ -702,18 +687,8 @@ dwc_otg_host_channel_free(struct dwc_otg_softc *sc, struct dwc_otg_td *td) /* * We need to let programmed host channels run till complete - * else the host channel will stop functioning. Assume that - * after a fixed given amount of time the host channel is no - * longer doing any USB traffic: + * else the host channel will stop functioning. */ - if (td->ep_type == UE_ISOCHRONOUS) { - /* double buffered */ - sc->sc_chan_state[x].wait_sof = DWC_OTG_SLOT_IDLE_MAX; - } else { - /* single buffered */ - sc->sc_chan_state[x].wait_sof = DWC_OTG_SLOT_IDLE_MIN; - } - sc->sc_chan_state[x].allocated = 0; /* ack any pending messages */ @@ -724,6 +699,16 @@ dwc_otg_host_channel_free(struct dwc_otg_softc *sc, struct dwc_otg_td *td) /* clear active channel */ sc->sc_active_rx_ep &= ~(1 << x); + + /* disable host channel */ + hcchar = DWC_OTG_READ_4(sc, DOTG_HCCHAR(x)); + if (hcchar & HCCHAR_CHENA) { + DPRINTF("Halting channel %d\n", x); + DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(x), + hcchar | HCCHAR_CHDIS); + sc->sc_chan_state[x].wait_halted = 1; + /* don't write HCCHAR until the channel is halted */ + } } static void @@ -1402,7 +1387,8 @@ receive_pkt: hcchar |= HCCHAR_EPDIR_IN; /* receive complete split ASAP */ - if ((sc->sc_last_frame_num & 1) != 0) + if ((sc->sc_last_frame_num & 1) != 0 && + (td->ep_type == UE_INTERRUPT || td->ep_type == UE_ISOCHRONOUS)) hcchar |= HCCHAR_ODDFRM; else hcchar &= ~HCCHAR_ODDFRM; @@ -1450,7 +1436,8 @@ receive_spkt: DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); /* send after next SOF event */ - if ((sc->sc_last_frame_num & 1) == 0) + if ((sc->sc_last_frame_num & 1) == 0 && + (td->ep_type == UE_INTERRUPT || td->ep_type == UE_ISOCHRONOUS)) td->hcchar |= HCCHAR_ODDFRM; else td->hcchar &= ~HCCHAR_ODDFRM; @@ -1890,7 +1877,8 @@ send_isoc_pkt: hcchar &= ~HCCHAR_EPDIR_IN; /* send after next SOF event */ - if ((sc->sc_last_frame_num & 1) == 0) + if ((sc->sc_last_frame_num & 1) == 0 && + (td->ep_type == UE_INTERRUPT || td->ep_type == UE_ISOCHRONOUS)) hcchar |= HCCHAR_ODDFRM; else hcchar &= ~HCCHAR_ODDFRM; @@ -1954,7 +1942,8 @@ send_cpkt: hcchar &= ~HCCHAR_EPDIR_IN; /* receive complete split ASAP */ - if ((sc->sc_last_frame_num & 1) != 0) + if ((sc->sc_last_frame_num & 1) != 0 && + (td->ep_type == UE_INTERRUPT || td->ep_type == UE_ISOCHRONOUS)) hcchar |= HCCHAR_ODDFRM; else hcchar &= ~HCCHAR_ODDFRM; @@ -2350,31 +2339,6 @@ dwc_otg_timer_stop(struct dwc_otg_softc *sc) usb_callout_stop(&sc->sc_timer); } -static void -dwc_otg_host_channel_disable(struct dwc_otg_softc *sc, uint8_t x) -{ - uint32_t hcchar; - - hcchar = DWC_OTG_READ_4(sc, DOTG_HCCHAR(x)); - - /* disable host channel, if any */ - if (hcchar & (HCCHAR_CHENA | HCCHAR_CHDIS)) { - /* disable channel */ - DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(x), - HCCHAR_CHENA | HCCHAR_CHDIS); - /* wait for chip to get its brains in order */ - sc->sc_chan_state[x].wait_sof = 2; - } - - /* release TX FIFO usage, if any */ - sc->sc_tx_cur_p_level -= sc->sc_chan_state[x].tx_p_size; - sc->sc_tx_cur_np_level -= sc->sc_chan_state[x].tx_np_size; - - /* don't release TX FIFO usage twice */ - sc->sc_chan_state[x].tx_p_size = 0; - sc->sc_chan_state[x].tx_np_size = 0; -} - static uint16_t dwc_otg_compute_isoc_rx_tt_slot(struct dwc_otg_tt_info *pinfo) { @@ -2392,7 +2356,6 @@ dwc_otg_update_host_transfer_schedule_locked(struct dwc_otg_softc *sc) struct dwc_otg_td *td; uint16_t temp; uint16_t slot; - uint8_t x; temp = DWC_OTG_READ_4(sc, DOTG_HFNUM) & DWC_OTG_FRAME_MASK; @@ -2403,15 +2366,6 @@ dwc_otg_update_host_transfer_schedule_locked(struct dwc_otg_softc *sc) TAILQ_INIT(&head); - for (x = 0; x != sc->sc_host_ch_max; x++) { - if (sc->sc_chan_state[x].wait_sof == 0) - continue; - - sc->sc_needsof = 1; - if (--(sc->sc_chan_state[x].wait_sof) == 0) - dwc_otg_host_channel_disable(sc, x); - } - if ((temp & 7) == 0) { /* reset the schedule */ @@ -2631,6 +2585,12 @@ repeat: if (temp != GRXSTSRD_STP_DATA && temp != GRXSTSRD_STP_COMPLETE && temp != GRXSTSRD_OUT_DATA) { + /* check for halted channel */ + if (temp == GRXSTSRH_HALTED) { + ep_no = GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status); + sc->sc_chan_state[ep_no].wait_halted = 0; + DPRINTFN(5, "channel halt complete ch=%u\n", ep_no); + } dwc_otg_common_rx_ack(sc); goto repeat; } @@ -2764,6 +2724,12 @@ dwc_otg_filter_interrupt(void *arg) if ((status & DWC_OTG_MSK_GINT_THREAD_IRQ) != 0) retval = FILTER_SCHEDULE_THREAD; + /* clear FIFO empty interrupts */ + if (status & sc->sc_irq_mask & + (GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP)) { + sc->sc_irq_mask &= ~(GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP); + DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); + } /* clear all IN endpoint interrupts */ if (status & GINTSTS_IEPINT) { uint32_t temp; diff --git a/sys/dev/usb/controller/dwc_otg.h b/sys/dev/usb/controller/dwc_otg.h index 52b3b914a0db..1ba0a5e4ce7e 100644 --- a/sys/dev/usb/controller/dwc_otg.h +++ b/sys/dev/usb/controller/dwc_otg.h @@ -37,7 +37,7 @@ #define DWC_OTG_TT_SLOT_MAX 8 #define DWC_OTG_SLOT_IDLE_MAX 3 #define DWC_OTG_SLOT_IDLE_MIN 2 -#define DWC_OTG_NAK_MAX 8 /* 1 ms */ +#define DWC_OTG_NAK_MAX 16 /* 16 NAKs = 2 ms */ #ifndef DWC_OTG_TX_MAX_FIFO_SIZE #define DWC_OTG_TX_MAX_FIFO_SIZE DWC_OTG_MAX_TXN #endif @@ -156,10 +156,8 @@ struct dwc_otg_profile { struct dwc_otg_chan_state { uint16_t allocated; - uint16_t wait_sof; + uint16_t wait_halted; uint32_t hcint; - uint16_t tx_p_size; /* periodic */ - uint16_t tx_np_size; /* non-periodic */ }; struct dwc_otg_softc { @@ -181,9 +179,6 @@ struct dwc_otg_softc { uint32_t sc_tx_bounce_buffer[MAX(512 * DWC_OTG_MAX_TXP, 1024) / 4]; uint32_t sc_fifo_size; - uint32_t sc_tx_max_size; - uint32_t sc_tx_cur_p_level; /* periodic */ - uint32_t sc_tx_cur_np_level; /* non-periodic */ uint32_t sc_irq_mask; uint32_t sc_last_rx_status; uint32_t sc_out_ctl[DWC_OTG_MAX_ENDPOINTS]; diff --git a/sys/dev/usb/controller/dwc_otgreg.h b/sys/dev/usb/controller/dwc_otgreg.h index 8ab35829ddab..8b9538aef0be 100644 --- a/sys/dev/usb/controller/dwc_otgreg.h +++ b/sys/dev/usb/controller/dwc_otgreg.h @@ -47,6 +47,8 @@ #define DOTG_GGPIO 0x0038 #define DOTG_GUID 0x003C #define DOTG_GSNPSID 0x0040 +#define DOTG_GSNPSID_REV_2_80a 0x4f54280a /* RPi model B/RPi2 */ +#define DOTG_GSNPSID_REV_3_10a 0x4f54310a /* ODROID-C1 */ #define DOTG_GHWCFG1 0x0044 #define DOTG_GHWCFG2 0x0048 #define DOTG_GHWCFG3 0x004C diff --git a/sys/dev/virtio/network/if_vtnet.c b/sys/dev/virtio/network/if_vtnet.c index 3b6438f048f1..4908fe000093 100644 --- a/sys/dev/virtio/network/if_vtnet.c +++ b/sys/dev/virtio/network/if_vtnet.c @@ -304,6 +304,9 @@ DRIVER_MODULE(vtnet, virtio_pci, vtnet_driver, vtnet_devclass, vtnet_modevent, 0); MODULE_VERSION(vtnet, 1); MODULE_DEPEND(vtnet, virtio, 1, 1, 1); +#ifdef DEV_NETMAP +MODULE_DEPEND(vtnet, netmap, 1, 1, 1); +#endif /* DEV_NETMAP */ static int vtnet_modevent(module_t mod, int type, void *unused) diff --git a/sys/dev/vt/logo/logo_beastie.c b/sys/dev/vt/logo/logo_beastie.c new file mode 100644 index 000000000000..7c7895172885 --- /dev/null +++ b/sys/dev/vt/logo/logo_beastie.c @@ -0,0 +1,398 @@ +/*- + * Copyright (c) 2015 Conrad Meyer + * Copyright (c) 2005 The FreeBSD Foundation + * Copyright (c) 1996 Larry Ewing + * Copyright (c) 1988 Kirk McKusick + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include + +const unsigned int vt_logo_sprite_width = 80; +const unsigned int vt_logo_sprite_height = 80; + +const unsigned char vt_beastie_vga16[] = { + 0x16, 0x00, 0x62, 0x16, 0x88, 0x03, 0x80, 0x16, 0x00, 0x23, 0x88, 0x80, + 0x00, 0x00, 0x08, 0x88, 0x16, 0x00, 0x21, 0x08, 0x16, 0x00, 0x06, 0x88, + 0x16, 0x00, 0x20, 0x80, 0x16, 0x00, 0x06, 0x08, 0x80, 0x16, 0x00, 0x1e, + 0x08, 0x16, 0x00, 0x08, 0x88, 0x16, 0x00, 0x1e, 0x08, 0x16, 0x00, 0x06, + 0x87, 0x00, 0x08, 0x16, 0x00, 0x1e, 0x80, 0x16, 0x00, 0x06, 0x77, 0x80, + 0x00, 0x80, 0x16, 0x00, 0x1d, 0x80, 0x16, 0x00, 0x06, 0x08, 0x00, 0x00, + 0x08, 0x16, 0x00, 0x1d, 0x80, 0x16, 0x00, 0x09, 0x08, 0x16, 0x00, 0x1c, + 0x08, 0x16, 0x00, 0x0a, 0x08, 0x16, 0x00, 0x1c, 0x08, 0x16, 0x00, 0x0b, + 0x80, 0x16, 0x00, 0x1b, 0x08, 0x16, 0x00, 0x0b, 0x80, 0x16, 0x00, 0x1b, + 0x08, 0x00, 0x08, 0x70, 0x16, 0x00, 0x03, 0x77, 0x70, 0x16, 0x00, 0x03, + 0x80, 0x16, 0x00, 0x1b, 0x08, 0x00, 0x87, 0x77, 0x00, 0x00, 0x07, 0xff, + 0xf7, 0x16, 0x00, 0x03, 0x80, 0x16, 0x00, 0x1b, 0x08, 0x08, 0x77, 0xff, + 0x00, 0x00, 0x7f, 0x77, 0xf7, 0x16, 0x00, 0x03, 0x80, 0x16, 0x00, 0x1b, + 0x08, 0x08, 0x70, 0x0f, 0x80, 0x00, 0xf7, 0x08, 0x7f, 0x70, 0x00, 0x00, + 0x80, 0x16, 0x00, 0x1b, 0x08, 0x08, 0x80, 0x07, 0x80, 0x00, 0xf8, 0x00, + 0x8f, 0x70, 0x00, 0x00, 0x80, 0x16, 0x00, 0x1b, 0x08, 0x08, 0x70, 0x07, + 0x88, 0x88, 0xf8, 0x00, 0x8f, 0x70, 0x00, 0x00, 0x80, 0x16, 0x00, 0x1b, + 0x08, 0x00, 0xf0, 0x06, 0x16, 0xe6, 0x03, 0x00, 0x8f, 0x16, 0x00, 0x03, + 0x80, 0x16, 0x00, 0x1b, 0x08, 0x00, 0x77, 0x16, 0x6e, 0x05, 0x77, 0x16, + 0x00, 0x03, 0x80, 0x16, 0x00, 0x1b, 0x08, 0x00, 0x06, 0x16, 0xe6, 0x06, + 0x16, 0x00, 0x03, 0x80, 0x16, 0x00, 0x1b, 0x08, 0x00, 0x16, 0x6e, 0x07, + 0x60, 0x00, 0x00, 0x08, 0x16, 0x00, 0x1b, 0x08, 0x80, 0x16, 0xe6, 0x07, + 0x60, 0x00, 0x00, 0x08, 0x16, 0x00, 0x1b, 0x08, 0x80, 0x16, 0x6e, 0x05, + 0x66, 0x66, 0x80, 0x08, 0x00, 0x00, 0x80, 0x16, 0x00, 0x1a, 0x08, 0x80, + 0x86, 0x16, 0xe6, 0x03, 0x16, 0x66, 0x03, 0x80, 0x08, 0x78, 0x00, 0x80, + 0x16, 0x00, 0x1a, 0x08, 0x80, 0x86, 0x16, 0x66, 0x05, 0x77, 0x70, 0x00, + 0x77, 0x00, 0x08, 0x16, 0x00, 0x1a, 0x08, 0x00, 0x87, 0x16, 0x66, 0x04, + 0x77, 0x77, 0x78, 0x00, 0x88, 0x00, 0x08, 0x16, 0x00, 0x1a, 0x08, 0x00, + 0x87, 0x76, 0x66, 0x66, 0x77, 0x77, 0xff, 0xf7, 0x16, 0x00, 0x03, 0x08, + 0x16, 0x00, 0x1a, 0x80, 0x08, 0xff, 0x16, 0x77, 0x04, 0x16, 0xff, 0x03, + 0x80, 0x16, 0x00, 0x03, 0x80, 0x16, 0x00, 0x19, 0x80, 0x07, 0xff, 0x16, + 0x77, 0x03, 0x7f, 0x16, 0xff, 0x03, 0x70, 0x16, 0x00, 0x03, 0x80, 0x16, + 0x00, 0x18, 0x08, 0x00, 0x8f, 0xff, 0xf7, 0x77, 0x77, 0x16, 0xff, 0x04, + 0xf0, 0x16, 0x00, 0x03, 0x08, 0x16, 0x00, 0x18, 0x80, 0x08, 0x7f, 0x16, + 0xff, 0x08, 0xf8, 0x16, 0x00, 0x04, 0x80, 0x16, 0x00, 0x16, 0x08, 0x00, + 0x08, 0x16, 0xff, 0x09, 0xf7, 0x16, 0x00, 0x04, 0x08, 0x16, 0x00, 0x16, + 0x08, 0x00, 0x08, 0x16, 0xff, 0x0a, 0x16, 0x00, 0x05, 0x80, 0x16, 0x00, + 0x15, 0x80, 0x00, 0x87, 0x16, 0xff, 0x0a, 0x80, 0x16, 0x00, 0x04, 0x08, + 0x16, 0x00, 0x14, 0x08, 0x00, 0x00, 0x87, 0x77, 0xff, 0xf7, 0x77, 0x16, + 0xff, 0x03, 0x16, 0x77, 0x03, 0x78, 0x16, 0x00, 0x04, 0x08, 0x16, 0x00, + 0x14, 0x08, 0x00, 0x00, 0x77, 0x7f, 0xff, 0xff, 0x7f, 0x16, 0xff, 0x04, + 0x77, 0x77, 0x78, 0x00, 0x80, 0x16, 0x00, 0x03, 0x80, 0x16, 0x00, 0x13, + 0x80, 0x00, 0x00, 0x7f, 0x16, 0xff, 0x09, 0xf7, 0x77, 0x00, 0x08, 0x80, + 0x00, 0x00, 0x80, 0x16, 0x00, 0x13, 0x80, 0x80, 0x08, 0x16, 0xff, 0x0b, + 0x77, 0x80, 0x00, 0x08, 0x00, 0x00, 0x08, 0x16, 0x00, 0x12, 0x08, 0x00, + 0x80, 0x07, 0x16, 0xff, 0x0c, 0x78, 0x00, 0x08, 0x80, 0x00, 0x08, 0x16, + 0x00, 0x12, 0x08, 0x08, 0x00, 0x8f, 0x16, 0xff, 0x0c, 0xf7, 0x08, 0x80, + 0x80, 0x00, 0x08, 0x16, 0x00, 0x12, 0x16, 0x08, 0x03, 0x7f, 0x16, 0xff, + 0x0c, 0xf7, 0x08, 0x80, 0x80, 0x00, 0x00, 0x80, 0x16, 0x00, 0x11, 0x80, + 0x08, 0x07, 0x16, 0xff, 0x0e, 0x80, 0x00, 0x08, 0x00, 0x00, 0x80, 0x16, + 0x00, 0x11, 0x80, 0x80, 0x0f, 0x16, 0xff, 0x0e, 0x70, 0x00, 0x08, 0x00, + 0x00, 0x80, 0x16, 0x00, 0x10, 0x08, 0x00, 0x80, 0x8f, 0x16, 0xff, 0x0e, + 0x70, 0x00, 0x08, 0x00, 0x00, 0x80, 0x16, 0x00, 0x10, 0x08, 0x08, 0x00, + 0x7f, 0x16, 0xff, 0x0e, 0x70, 0x00, 0x08, 0x00, 0x00, 0x08, 0x16, 0x00, + 0x10, 0x80, 0x08, 0x00, 0x16, 0xff, 0x05, 0x7f, 0x16, 0xff, 0x09, 0xf0, + 0x00, 0x08, 0x00, 0x00, 0x08, 0x16, 0x00, 0x0f, 0x08, 0x00, 0x08, 0x00, + 0x16, 0xff, 0x05, 0x7f, 0x16, 0xff, 0x09, 0xf0, 0x00, 0x08, 0x00, 0x00, + 0x08, 0x16, 0x00, 0x0f, 0x08, 0x00, 0x08, 0x08, 0x16, 0xff, 0x05, 0x7f, + 0x16, 0xff, 0x09, 0xf0, 0x00, 0x08, 0x00, 0x00, 0x08, 0x16, 0x00, 0x0f, + 0x08, 0x00, 0x08, 0x08, 0x16, 0xff, 0x05, 0x7f, 0x16, 0xff, 0x09, 0xf0, + 0x00, 0x08, 0x00, 0x00, 0x08, 0x16, 0x00, 0x0f, 0x08, 0x00, 0x00, 0x88, + 0x16, 0xff, 0x05, 0x7f, 0x16, 0xff, 0x09, 0xf0, 0x00, 0x08, 0x00, 0x00, + 0x08, 0x16, 0x00, 0x0f, 0x08, 0x00, 0x00, 0x08, 0x16, 0xff, 0x05, 0x7f, + 0x16, 0xff, 0x09, 0xf0, 0x88, 0x88, 0x80, 0x00, 0x08, 0x16, 0x00, 0x0f, + 0x08, 0x06, 0xe6, 0x00, 0x8f, 0x16, 0xff, 0x04, 0x7f, 0x16, 0xff, 0x09, + 0xf8, 0x00, 0x00, 0x08, 0x80, 0x08, 0x16, 0x00, 0x10, 0x6e, 0x6e, 0x60, + 0x08, 0x16, 0xff, 0x04, 0x7f, 0x16, 0xff, 0x08, 0xe6, 0xe0, 0x16, 0x00, + 0x03, 0x88, 0x80, 0x16, 0x00, 0x0f, 0x06, 0x16, 0xe6, 0x03, 0x00, 0x8f, + 0x16, 0xff, 0x0b, 0xfe, 0x6e, 0x60, 0x16, 0x00, 0x04, 0x60, 0x16, 0x00, + 0x0f, 0x16, 0x6e, 0x04, 0x60, 0x08, 0x16, 0xff, 0x0b, 0xf6, 0xe6, 0xe0, + 0x16, 0x00, 0x03, 0x06, 0xe6, 0x16, 0x00, 0x0c, 0x06, 0x16, 0xe6, 0x06, + 0xe0, 0x00, 0x8f, 0x16, 0xff, 0x0a, 0xfe, 0x6e, 0x60, 0x16, 0x00, 0x03, + 0x0e, 0x6e, 0x16, 0x00, 0x0c, 0x16, 0x6e, 0x08, 0x00, 0x08, 0x16, 0xff, + 0x0a, 0x76, 0xe6, 0xe6, 0x16, 0x00, 0x03, 0xe6, 0xe6, 0x16, 0x00, 0x0c, + 0x16, 0xe6, 0x08, 0xe0, 0x00, 0x8f, 0x16, 0xff, 0x08, 0xf7, 0x7e, 0x16, + 0x6e, 0x07, 0x16, 0x00, 0x0c, 0x16, 0x6e, 0x08, 0x60, 0x00, 0x08, 0x16, + 0xff, 0x08, 0xf7, 0x76, 0x16, 0xe6, 0x07, 0xe0, 0x16, 0x00, 0x0b, 0x16, + 0xe6, 0x09, 0x00, 0x00, 0x0f, 0x16, 0xff, 0x07, 0xf7, 0x7e, 0x16, 0x6e, + 0x08, 0x16, 0x00, 0x0b, 0x16, 0x6e, 0x09, 0x60, 0x00, 0x0f, 0x16, 0xff, + 0x07, 0xf7, 0x76, 0x16, 0xe6, 0x08, 0xe0, 0x16, 0x00, 0x0a, 0x16, 0xe6, + 0x09, 0xe0, 0x00, 0x8f, 0x16, 0xff, 0x07, 0xf7, 0x8e, 0x16, 0x6e, 0x09, + 0x16, 0x00, 0x0a, 0x16, 0x6e, 0x0a, 0x88, 0x16, 0xff, 0x08, 0x78, 0x86, + 0x16, 0xe6, 0x0a, 0x16, 0x00, 0x09, 0x16, 0xe6, 0x0a, 0xef, 0x16, 0xff, + 0x07, 0xf7, 0x80, 0x06, 0x16, 0x6e, 0x0a, 0x16, 0x00, 0x09, 0x16, 0x6e, + 0x0b, 0x16, 0xff, 0x07, 0x78, 0x00, 0x06, 0x16, 0xe6, 0x09, 0xe0, 0x16, + 0x00, 0x09, 0x16, 0xe6, 0x0b, 0x7f, 0x16, 0xff, 0x05, 0x78, 0x80, 0x00, + 0x06, 0x16, 0x6e, 0x09, 0x16, 0x00, 0x09, 0x0e, 0x16, 0x6e, 0x0a, 0x66, + 0x67, 0x16, 0xff, 0x04, 0x78, 0x80, 0x00, 0x00, 0x86, 0x16, 0xe6, 0x08, + 0xe0, 0x16, 0x00, 0x09, 0x06, 0x16, 0xe6, 0x0b, 0x60, 0x16, 0x00, 0x08, + 0x86, 0x16, 0x6e, 0x06, 0x66, 0x60, 0x16, 0x00, 0x0a, 0x0e, 0x16, 0x6e, + 0x0a, 0x66, 0x60, 0x16, 0x00, 0x08, 0x86, 0x16, 0xe6, 0x06, 0x60, 0x16, + 0x00, 0x0c, 0x16, 0xe6, 0x0b, 0x60, 0x16, 0x00, 0x08, 0x86, 0x16, 0x6e, + 0x04, 0x66, 0x66, 0x16, 0x00, 0x0f, 0x16, 0x66, 0x03, 0x16, 0x6e, 0x05, + 0x66, 0x60, 0x00, 0x16, 0x88, 0x05, 0x80, 0x00, 0x06, 0x66, 0x16, 0xe6, + 0x03, 0x66, 0x16, 0x00, 0x12, 0x16, 0x66, 0x04, 0xe6, 0xe6, 0x66, 0x88, + 0x88, 0x16, 0x00, 0x05, 0x08, 0x88, 0x86, 0x66, 0x6e, 0x6e, 0x66, 0x60, + 0x16, 0x00, 0x14, 0x06, 0x16, 0x66, 0x04, 0x16, 0x00, 0x09, 0x06, 0x16, + 0x66, 0x04, 0x16, 0x00, 0x16, 0x06, 0x66, 0x66, 0x60, 0x16, 0x00, 0x0a, + 0x16, 0x66, 0x03, 0x60, 0x16, 0x00, 0x82 +}; + +const unsigned char vt_beastie2_vga16[] = { + 0x16, 0x00, 0x11, 0x04, 0x16, 0x00, 0x26, 0x04, 0x44, 0x16, 0x00, 0x26, + 0x44, 0x40, 0x16, 0x00, 0x25, 0x44, 0x44, 0x16, 0x00, 0x0b, 0x44, 0x16, + 0x00, 0x19, 0x04, 0x44, 0x40, 0x16, 0x00, 0x0b, 0x04, 0x40, 0x16, 0x00, + 0x18, 0x44, 0x44, 0x40, 0x16, 0x00, 0x0b, 0x04, 0x44, 0x16, 0x00, 0x17, + 0x04, 0x44, 0x44, 0x16, 0x00, 0x0d, 0x44, 0x40, 0x16, 0x00, 0x16, 0x16, + 0x44, 0x03, 0x16, 0x00, 0x03, 0x04, 0x04, 0x16, 0x00, 0x08, 0x44, 0x44, + 0x16, 0x00, 0x16, 0x16, 0x44, 0x03, 0x00, 0x04, 0x16, 0x44, 0x05, 0x16, + 0x00, 0x06, 0x44, 0x44, 0x16, 0x00, 0x15, 0x04, 0x44, 0x44, 0x40, 0x40, + 0x16, 0x44, 0x07, 0x40, 0x16, 0x00, 0x04, 0x44, 0x44, 0x40, 0x16, 0x00, + 0x14, 0x04, 0x16, 0x44, 0x06, 0x04, 0x04, 0x16, 0x44, 0x03, 0x04, 0x16, + 0x00, 0x03, 0x04, 0x44, 0x44, 0x40, 0x16, 0x00, 0x14, 0x04, 0x16, 0x44, + 0x07, 0x40, 0x16, 0x44, 0x04, 0x40, 0x00, 0x00, 0x16, 0x44, 0x03, 0x40, + 0x16, 0x00, 0x14, 0x04, 0x16, 0x44, 0x03, 0x84, 0x16, 0x44, 0x04, 0x04, + 0x16, 0x44, 0x04, 0x04, 0x16, 0x44, 0x04, 0x40, 0x16, 0x00, 0x14, 0x04, + 0x44, 0x44, 0x0f, 0xf8, 0x44, 0x48, 0x84, 0x16, 0x44, 0x0b, 0x40, 0x16, + 0x00, 0x14, 0x04, 0x44, 0x40, 0xff, 0xf8, 0x40, 0xff, 0xff, 0x16, 0x44, + 0x0b, 0x40, 0x16, 0x00, 0x14, 0x04, 0x44, 0x0f, 0xff, 0x74, 0x47, 0xff, + 0xff, 0x74, 0x16, 0x44, 0x0a, 0x40, 0x16, 0x00, 0x14, 0x04, 0x04, 0xff, + 0xff, 0x44, 0x7f, 0xff, 0xff, 0xf4, 0x16, 0x44, 0x0a, 0x16, 0x00, 0x15, + 0x04, 0x48, 0xff, 0xf7, 0x40, 0x16, 0xff, 0x03, 0xf6, 0x16, 0x44, 0x0a, + 0x16, 0x00, 0x16, 0x4f, 0xff, 0xf8, 0x47, 0x16, 0xff, 0x03, 0xf8, 0x16, + 0x44, 0x09, 0x40, 0x16, 0x00, 0x16, 0x07, 0x07, 0xf8, 0x0f, 0x16, 0xff, + 0x03, 0xf8, 0x16, 0x44, 0x08, 0x40, 0x40, 0x16, 0x00, 0x15, 0x04, 0x77, + 0x80, 0xf4, 0x78, 0x0f, 0xff, 0xff, 0xf8, 0x16, 0x44, 0x09, 0x16, 0x00, + 0x16, 0x04, 0x8f, 0x00, 0xf0, 0x8f, 0x88, 0xff, 0xff, 0xf8, 0x16, 0x44, + 0x08, 0x16, 0x00, 0x17, 0x04, 0x00, 0x00, 0x88, 0x0f, 0x00, 0xff, 0xff, + 0xf6, 0x16, 0x44, 0x07, 0x40, 0x16, 0x00, 0x17, 0x40, 0x00, 0x00, 0x48, + 0x07, 0x00, 0xff, 0xff, 0xf4, 0x16, 0x44, 0x06, 0x40, 0x16, 0x00, 0x18, + 0x44, 0x80, 0x08, 0x48, 0x00, 0x00, 0xff, 0xff, 0xf4, 0x16, 0x44, 0x06, + 0x16, 0x00, 0x18, 0x04, 0x44, 0x40, 0x04, 0x48, 0x00, 0x00, 0xff, 0xff, + 0x84, 0x16, 0x44, 0x06, 0x40, 0x16, 0x00, 0x17, 0x44, 0x44, 0x04, 0x00, + 0x48, 0x00, 0x07, 0xff, 0xff, 0x16, 0x44, 0x07, 0x40, 0x16, 0x00, 0x17, + 0x44, 0x40, 0x16, 0x44, 0x03, 0xf7, 0xff, 0xff, 0xf0, 0x16, 0x44, 0x07, + 0x40, 0x16, 0x00, 0x16, 0x04, 0x44, 0x40, 0x44, 0x44, 0x40, 0x0f, 0xff, + 0xf7, 0x00, 0x16, 0x44, 0x07, 0x40, 0x16, 0x00, 0x14, 0x6e, 0x00, 0x04, + 0x16, 0x44, 0x05, 0x40, 0x40, 0x16, 0x44, 0x08, 0x40, 0x40, 0x16, 0x00, + 0x14, 0x0e, 0xe0, 0x00, 0x44, 0x44, 0x04, 0x16, 0x44, 0x0d, 0x16, 0x00, + 0x15, 0x06, 0x66, 0x00, 0x16, 0x44, 0x03, 0x16, 0x40, 0x03, 0x16, 0x44, + 0x09, 0x04, 0x16, 0x00, 0x13, 0x60, 0x00, 0x00, 0x06, 0x60, 0x44, 0x44, + 0x04, 0x16, 0x44, 0x0c, 0x40, 0x16, 0x00, 0x13, 0x0e, 0xe0, 0x00, 0x00, + 0xe0, 0x04, 0x44, 0x40, 0x16, 0x44, 0x0b, 0x40, 0x40, 0x16, 0x00, 0x13, + 0x06, 0xee, 0x00, 0x00, 0xe0, 0x00, 0x04, 0x16, 0x44, 0x07, 0x40, 0x40, + 0x16, 0x44, 0x04, 0x16, 0x00, 0x14, 0x06, 0x06, 0xe6, 0x00, 0xe0, 0x00, + 0x00, 0x04, 0x04, 0x16, 0x44, 0x04, 0x40, 0x16, 0x44, 0x05, 0x16, 0x00, + 0x17, 0x6e, 0x6e, 0x60, 0x16, 0x00, 0x04, 0x16, 0x44, 0x03, 0x40, 0x16, + 0x44, 0x04, 0x40, 0x40, 0x16, 0x00, 0x13, 0x68, 0x60, 0x00, 0x00, 0x06, + 0xee, 0x60, 0x16, 0x00, 0x05, 0x40, 0x40, 0x16, 0x44, 0x03, 0x04, 0x16, + 0x00, 0x16, 0x0e, 0xe0, 0x00, 0x00, 0x6e, 0xe6, 0xe6, 0x04, 0x44, 0x44, + 0x00, 0x00, 0x16, 0x44, 0x04, 0x04, 0x44, 0x40, 0x40, 0x16, 0x00, 0x15, + 0x6e, 0x66, 0x6e, 0xe6, 0x66, 0xee, 0x04, 0x44, 0x44, 0x16, 0x00, 0x03, + 0x16, 0x40, 0x03, 0x44, 0x44, 0x40, 0x16, 0x00, 0x16, 0x06, 0x6e, 0xee, + 0x68, 0x00, 0x0e, 0x64, 0x44, 0x44, 0x16, 0x00, 0x03, 0x16, 0x44, 0x06, + 0x04, 0x16, 0x00, 0x1b, 0x60, 0x44, 0x40, 0x16, 0x00, 0x03, 0x16, 0x44, + 0x06, 0x40, 0x16, 0x00, 0x1a, 0x04, 0x44, 0x40, 0x16, 0x00, 0x03, 0x04, + 0x16, 0x44, 0x06, 0x04, 0x16, 0x00, 0x1a, 0x04, 0x16, 0x44, 0x05, 0x04, + 0x16, 0x44, 0x06, 0x40, 0x16, 0x00, 0x1a, 0x04, 0x16, 0x44, 0x04, 0x04, + 0x04, 0x44, 0x04, 0x16, 0x44, 0x03, 0x04, 0x40, 0x40, 0x16, 0x00, 0x19, + 0x04, 0x44, 0x44, 0x04, 0x40, 0x44, 0x04, 0x44, 0x44, 0x04, 0x44, 0x40, + 0x44, 0x44, 0x16, 0x00, 0x1b, 0x04, 0x40, 0x44, 0x04, 0x16, 0x44, 0x04, + 0x40, 0x40, 0x44, 0x44, 0x40, 0x40, 0x16, 0x00, 0x1a, 0x04, 0x16, 0x44, + 0x03, 0x40, 0x16, 0x44, 0x08, 0x16, 0x00, 0x1c, 0x04, 0x40, 0x44, 0x04, + 0x16, 0x44, 0x07, 0x40, 0x40, 0x16, 0x00, 0x1e, 0x16, 0x44, 0x09, 0x16, + 0x00, 0x1e, 0x04, 0x16, 0x44, 0x06, 0x40, 0x44, 0x44, 0x04, 0x16, 0x00, + 0x1d, 0x04, 0x16, 0x44, 0x06, 0x40, 0x44, 0x44, 0x40, 0x16, 0x00, 0x1e, + 0x16, 0x44, 0x06, 0x40, 0x44, 0x16, 0x00, 0x20, 0x04, 0x00, 0x16, 0x44, + 0x04, 0x04, 0x00, 0x04, 0x16, 0x00, 0x1f, 0x40, 0x16, 0x44, 0x05, 0x00, + 0x04, 0x16, 0x00, 0x1f, 0x04, 0x44, 0x00, 0x04, 0x04, 0x40, 0x40, 0x04, + 0x00, 0x40, 0x40, 0x16, 0x00, 0x1d, 0x04, 0x44, 0x44, 0x00, 0x40, 0x06, + 0x6e, 0x60, 0x04, 0x16, 0x00, 0x20, 0x16, 0x44, 0x04, 0x40, 0x6e, 0xe6, + 0x00, 0x40, 0x40, 0x16, 0x00, 0x1e, 0x16, 0x44, 0x05, 0x46, 0xee, 0x60, + 0x16, 0x00, 0x20, 0x16, 0x44, 0x05, 0x04, 0x6e, 0xee, 0x04, 0x04, 0x16, + 0x00, 0x1e, 0x04, 0x16, 0x44, 0x05, 0x06, 0x6e, 0xe0, 0x00, 0x04, 0x16, + 0x00, 0x1e, 0x16, 0x44, 0x06, 0x6e, 0x64, 0x04, 0x16, 0x00, 0x1f, 0x04, + 0x04, 0x00, 0x00, 0x16, 0x04, 0x04, 0x00, 0x04, 0x16, 0x00, 0x1e, 0x04, + 0x44, 0x04, 0x04, 0x16, 0x40, 0x04, 0x44, 0x40, 0x04, 0x16, 0x00, 0x1d, + 0x44, 0x84, 0x74, 0x86, 0x87, 0x84, 0x44, 0x04, 0x00, 0x44, 0x40, 0x04, + 0x16, 0x00, 0x1c, 0x87, 0xc7, 0x40, 0x77, 0x74, 0x04, 0x04, 0x80, 0x00, + 0x00, 0x44, 0x40, 0x16, 0x00, 0x1b, 0x7c, 0x7c, 0x84, 0x74, 0x84, 0x44, + 0x84, 0x48, 0x78, 0x40, 0x00, 0x00, 0x44, 0x44, 0x04, 0x16, 0x00, 0x16, + 0x40, 0x48, 0xc8, 0xc7, 0x44, 0x40, 0x84, 0x44, 0x76, 0x04, 0x48, 0x78, + 0x16, 0x00, 0x04, 0x04, 0x40, 0x44, 0x04, 0x16, 0x00, 0x10, 0x08, 0x77, + 0xff, 0x77, 0x84, 0x44, 0x04, 0x00, 0x00, 0x46, 0x48, 0x74, 0x04, 0x44, + 0x40, 0x80, 0x40, 0x16, 0x00, 0x04, 0x04, 0x16, 0x44, 0x05, 0x40, 0x40, + 0x16, 0x00, 0x0a, 0x87, 0x16, 0xff, 0x03, 0xf7, 0x70, 0x88, 0x77, 0x77, + 0x84, 0x04, 0x44, 0x40, 0x44, 0x04, 0x44, 0x44, 0x04, 0x16, 0x00, 0x07, + 0x04, 0x16, 0x44, 0x03, 0x04, 0x40, 0x16, 0x00, 0x08, 0x07, 0x88, 0x16, + 0xff, 0x03, 0x77, 0x87, 0x16, 0xff, 0x03, 0x77, 0x84, 0x04, 0x04, 0x44, + 0x44, 0x16, 0x40, 0x03, 0x80, 0x16, 0x00, 0x09, 0x04, 0x44, 0x44, 0x40, + 0x16, 0x00, 0x07, 0x0f, 0xff, 0x16, 0x88, 0x03, 0x80, 0x7f, 0x16, 0xff, + 0x03, 0xf7, 0x78, 0x16, 0x44, 0x03, 0x04, 0x04, 0x48, 0x87, 0x80, 0x16, + 0x00, 0x0b, 0x04, 0x44, 0x16, 0x00, 0x07, 0x08, 0x16, 0xff, 0x03, 0x77, + 0x88, 0x87, 0x16, 0xff, 0x03, 0x77, 0x77, 0x16, 0x04, 0x03, 0x40, 0x48, + 0x87, 0x77, 0x16, 0x00, 0x0d, 0x44, 0x40, 0x16, 0x00, 0x07, 0x88, 0x77, + 0xf7, 0x77, 0x8f, 0x77, 0x16, 0x88, 0x05, 0x80, 0x88, 0x88, 0x87, 0x77, + 0x77, 0x80, 0x16, 0x00, 0x0d, 0x44, 0x40, 0x16, 0x00, 0x0b, 0x07, 0x16, + 0xff, 0x03, 0x7f, 0x16, 0x77, 0x06, 0x78, 0x16, 0x00, 0x0a, 0x04, 0x40, + 0x16, 0x00, 0x03, 0x44, 0x40, 0x16, 0x00, 0x0c, 0x87, 0x7f, 0xff, 0xff, + 0x16, 0x77, 0x04, 0x88, 0x80, 0x16, 0x00, 0x0a, 0x04, 0x44, 0x44, 0x00, + 0x00, 0x04, 0x44, 0x40, 0x16, 0x00, 0x0e, 0x08, 0x08, 0x88, 0x08, 0x16, + 0x00, 0x0e, 0x16, 0x44, 0x06, 0x40, 0x16, 0x00, 0x20, 0x16, 0x44, 0x06, + 0x16, 0x00, 0x21, 0x16, 0x44, 0x05, 0x40, 0x16, 0x00, 0x22, 0x40, 0x40, + 0x16, 0x00, 0x08 +}; + +const unsigned char vt_orb_vga16[] = { + 0x16, 0x00, 0x52, 0x04, 0x04, 0x16, 0x00, 0x0c, 0x16, 0x80, 0x03, 0x88, + 0x88, 0x16, 0x80, 0x04, 0x16, 0x00, 0x0b, 0x40, 0x40, 0x16, 0x00, 0x03, + 0x04, 0x44, 0x6c, 0xcc, 0x64, 0x16, 0x00, 0x08, 0x08, 0x08, 0x88, 0x77, + 0x16, 0x7f, 0x04, 0x77, 0x78, 0x88, 0x80, 0x80, 0x16, 0x00, 0x07, 0x04, + 0x6c, 0x6c, 0x44, 0x40, 0x00, 0x00, 0x04, 0x46, 0x4c, 0x77, 0x7c, 0xcc, + 0x40, 0x16, 0x00, 0x04, 0x08, 0x08, 0x88, 0x7f, 0x16, 0xff, 0x08, 0xf7, + 0x78, 0x80, 0x80, 0x16, 0x00, 0x05, 0x4c, 0xc7, 0xc7, 0xcc, 0x44, 0x44, + 0x00, 0x00, 0x44, 0x44, 0x46, 0xcc, 0xf7, 0xfc, 0x7c, 0x60, 0x00, 0x00, + 0x08, 0x08, 0x87, 0x16, 0xff, 0x0c, 0xf7, 0x88, 0x08, 0x16, 0x00, 0x03, + 0x6c, 0x16, 0xf7, 0x03, 0xc6, 0x44, 0x44, 0x00, 0x00, 0x16, 0x44, 0x03, + 0xc7, 0x7f, 0xf7, 0x77, 0xc7, 0x60, 0x00, 0x80, 0x77, 0x16, 0xff, 0x0e, + 0xf7, 0x70, 0x80, 0x08, 0x67, 0xff, 0x7f, 0x7f, 0x7c, 0xc4, 0x44, 0x44, + 0x00, 0x00, 0x16, 0x44, 0x03, 0x4c, 0xc7, 0xff, 0xf7, 0xf7, 0x77, 0x68, + 0x8f, 0x16, 0xff, 0x09, 0x16, 0xf7, 0x03, 0x16, 0xff, 0x05, 0x88, 0x67, + 0xff, 0x7f, 0xff, 0xff, 0x7c, 0x64, 0x44, 0x44, 0x00, 0x00, 0x04, 0x16, + 0x44, 0x03, 0x6c, 0xcf, 0x16, 0x7f, 0x04, 0x16, 0xff, 0x0d, 0x16, 0xf7, + 0x03, 0xff, 0xff, 0x7e, 0x16, 0xff, 0x04, 0x7c, 0xc6, 0x16, 0x44, 0x03, + 0x00, 0x00, 0x04, 0x16, 0x44, 0x03, 0x46, 0xcc, 0x7c, 0xf7, 0x16, 0xff, + 0x0d, 0x16, 0x7f, 0x03, 0x7c, 0xc6, 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0x7f, 0x80, 0x16, 0x00, 0x09, 0x07, + 0xf7, 0x16, 0x44, 0x0a, 0x16, 0x64, 0x04, 0x66, 0xc6, 0x64, 0x64, 0x16, + 0x66, 0x04, 0xc6, 0xc6, 0x6c, 0xc7, 0xe7, 0x77, 0x16, 0x00, 0x0a, 0x08, + 0x7f, 0x74, 0x16, 0x44, 0x06, 0x16, 0x46, 0x03, 0x44, 0x16, 0x64, 0x05, + 0xc6, 0x66, 0x66, 0x16, 0xc6, 0x03, 0x66, 0x6c, 0x6c, 0xe7, 0x77, 0x70, + 0x16, 0x00, 0x0b, 0x87, 0xfc, 0x16, 0x44, 0x09, 0x64, 0x16, 0x46, 0x03, + 0x4c, 0x16, 0x46, 0x04, 0x16, 0x66, 0x03, 0xc6, 0xc6, 0xce, 0xde, 0x77, + 0x80, 0x16, 0x00, 0x0b, 0x08, 0x7f, 0xc4, 0x16, 0x44, 0x07, 0x64, 0x44, + 0x16, 0x64, 0x05, 0x16, 0x66, 0x03, 0x46, 0xc6, 0xc6, 0x66, 0x6c, 0x77, + 0xe7, 0x78, 0x16, 0x00, 0x0d, 0x87, 0xfc, 0x16, 0x44, 0x08, 0x64, 0x44, + 0x46, 0x46, 0x4c, 0x16, 0x46, 0x04, 0x16, 0x66, 0x03, 0xc6, 0xce, 0x7e, + 0xd7, 0x80, 0x16, 0x00, 0x0d, 0x08, 0x7f, 0xc4, 0x16, 0x44, 0x08, 0x16, + 0x64, 0x06, 0xc6, 0x66, 0x4c, 0x46, 0xc6, 0xce, 0x7c, 0x77, 0x78, 0x16, + 0x00, 0x0f, 0x87, 0xf7, 0x16, 0x44, 0x0a, 0x16, 0x46, 0x06, 0x66, 0x66, + 0x6c, 0xec, 0xe7, 0xe7, 0x16, 0x00, 0x11, 0x8f, 0x7c, 0x16, 0x44, 0x07, + 0x16, 0x64, 0x09, 0x6c, 0xec, 0xe7, 0xc7, 0x80, 0x16, 0x00, 0x11, 0x08, + 0x77, 0xc6, 0x16, 0x44, 0x09, 0x16, 0x46, 0x04, 0x4c, 0x6c, 0xec, 0xee, + 0xc7, 0x78, 0x16, 0x00, 0x13, 0x07, 0x77, 0xcc, 0x16, 0x44, 0x06, 0x16, + 0x64, 0x05, 0xc4, 0xc6, 0xce, 0xce, 0xec, 0x78, 0x16, 0x00, 0x15, 0x88, + 0x77, 0xc6, 0xc4, 0xc4, 0x16, 0x44, 0x07, 0xc6, 0xc6, 0x16, 0xec, 0x03, + 0x78, 0x80, 0x16, 0x00, 0x16, 0x88, 0x77, 0xcc, 0x16, 0x4c, 0x06, 0x16, + 0x6c, 0x03, 0xec, 0xec, 0xe6, 0xe8, 0x80, 0x16, 0x00, 0x18, 0x88, 0x87, + 0xcc, 0x16, 0xc6, 0x03, 0x16, 0xcc, 0x03, 0xe6, 0xec, 0xe6, 0xe6, 0x78, + 0x16, 0x00, 0x1c, 0x88, 0x87, 0x16, 0xcc, 0x06, 0xc6, 0x76, 0x88, 0x16, + 0x00, 0x1f, 0x80, 0x16, 0x88, 0x05, 0x80, 0x16, 0x00, 0x88 +}; diff --git a/sys/dev/vt/vt.h b/sys/dev/vt/vt.h index bdfcf46808cf..1aa7b10d45ca 100644 --- a/sys/dev/vt/vt.h +++ b/sys/dev/vt/vt.h @@ -83,7 +83,7 @@ #define ISSIGVALID(sig) ((sig) > 0 && (sig) < NSIG) #define VT_SYSCTL_INT(_name, _default, _descr) \ -static int vt_##_name = (_default); \ +int vt_##_name = (_default); \ SYSCTL_INT(_kern_vt, OID_AUTO, _name, CTLFLAG_RWTUN, &vt_##_name, 0, _descr) struct vt_driver; @@ -164,7 +164,12 @@ struct vt_device { #define VD_PASTEBUFSZ(vd) ((vd)->vd_pastebuf.vpb_bufsz) #define VD_PASTEBUFLEN(vd) ((vd)->vd_pastebuf.vpb_len) +#define VT_LOCK(vd) mtx_lock(&(vd)->vd_lock) +#define VT_UNLOCK(vd) mtx_unlock(&(vd)->vd_lock) +#define VT_LOCK_ASSERT(vd, what) mtx_assert(&(vd)->vd_lock, what) + void vt_resume(struct vt_device *vd); +void vt_resume_flush_timer(struct vt_device *vd, int ms); void vt_suspend(struct vt_device *vd); /* @@ -363,6 +368,7 @@ struct vt_driver { * Utility macro to make early vt(4) instances work. */ +extern struct terminal vt_consterm; extern const struct terminal_class vt_termclass; void vt_upgrade(struct vt_device *vd); @@ -427,10 +433,29 @@ void vt_mouse_state(int show); #define VT_MOUSE_HIDE 0 /* Utilities. */ +void vt_compute_drawable_area(struct vt_window *); void vt_determine_colors(term_char_t c, int cursor, term_color_t *fg, term_color_t *bg); int vt_is_cursor_in_area(const struct vt_device *vd, const term_rect_t *area); +void vt_termsize(struct vt_device *, struct vt_font *, term_pos_t *); +void vt_winsize(struct vt_device *, struct vt_font *, struct winsize *); + +/* Logos-on-boot. */ +#define VT_LOGOS_DRAW_BEASTIE 0 +#define VT_LOGOS_DRAW_ALT_BEASTIE 1 +#define VT_LOGOS_DRAW_ORB 2 + +extern int vt_draw_logo_cpus; +extern int vt_splash_cpu; +extern int vt_splash_ncpu; +extern int vt_splash_cpu_style; +extern int vt_splash_cpu_duration; + +extern const unsigned int vt_logo_sprite_height; +extern const unsigned int vt_logo_sprite_width; + +void vtterm_draw_cpu_logos(struct vt_device *); #endif /* !_DEV_VT_VT_H_ */ diff --git a/sys/dev/vt/vt_core.c b/sys/dev/vt/vt_core.c index 907a4a11266e..1b633fdd3e28 100644 --- a/sys/dev/vt/vt_core.c +++ b/sys/dev/vt/vt_core.c @@ -113,32 +113,37 @@ const struct terminal_class vt_termclass = { #define VT_BELLDURATION ((5 * hz + 99) / 100) #define VT_BELLPITCH 800 -#define VT_LOCK(vd) mtx_lock(&(vd)->vd_lock) -#define VT_UNLOCK(vd) mtx_unlock(&(vd)->vd_lock) -#define VT_LOCK_ASSERT(vd, what) mtx_assert(&(vd)->vd_lock, what) - #define VT_UNIT(vw) ((vw)->vw_device->vd_unit * VT_MAXWINDOWS + \ (vw)->vw_number) static SYSCTL_NODE(_kern, OID_AUTO, vt, CTLFLAG_RD, 0, "vt(9) parameters"); -VT_SYSCTL_INT(enable_altgr, 1, "Enable AltGr key (Do not assume R.Alt as Alt)"); -VT_SYSCTL_INT(enable_bell, 1, "Enable bell"); -VT_SYSCTL_INT(debug, 0, "vt(9) debug level"); -VT_SYSCTL_INT(deadtimer, 15, "Time to wait busy process in VT_PROCESS mode"); -VT_SYSCTL_INT(suspendswitch, 1, "Switch to VT0 before suspend"); +static VT_SYSCTL_INT(enable_altgr, 1, "Enable AltGr key (Do not assume R.Alt as Alt)"); +static VT_SYSCTL_INT(enable_bell, 1, "Enable bell"); +static VT_SYSCTL_INT(debug, 0, "vt(9) debug level"); +static VT_SYSCTL_INT(deadtimer, 15, "Time to wait busy process in VT_PROCESS mode"); +static VT_SYSCTL_INT(suspendswitch, 1, "Switch to VT0 before suspend"); /* Allow to disable some keyboard combinations. */ -VT_SYSCTL_INT(kbd_halt, 1, "Enable halt keyboard combination. " +static VT_SYSCTL_INT(kbd_halt, 1, "Enable halt keyboard combination. " "See kbdmap(5) to configure."); -VT_SYSCTL_INT(kbd_poweroff, 1, "Enable Power Off keyboard combination. " +static VT_SYSCTL_INT(kbd_poweroff, 1, "Enable Power Off keyboard combination. " "See kbdmap(5) to configure."); -VT_SYSCTL_INT(kbd_reboot, 1, "Enable reboot keyboard combination. " +static VT_SYSCTL_INT(kbd_reboot, 1, "Enable reboot keyboard combination. " "See kbdmap(5) to configure (typically Ctrl-Alt-Delete)."); -VT_SYSCTL_INT(kbd_debug, 1, "Enable key combination to enter debugger. " +static VT_SYSCTL_INT(kbd_debug, 1, "Enable key combination to enter debugger. " "See kbdmap(5) to configure (typically Ctrl-Alt-Esc)."); -VT_SYSCTL_INT(kbd_panic, 0, "Enable request to panic. " +static VT_SYSCTL_INT(kbd_panic, 0, "Enable request to panic. " "See kbdmap(5) to configure."); +/* Used internally, not a tunable. */ +int vt_draw_logo_cpus; +VT_SYSCTL_INT(splash_cpu, 1, "Show logo CPUs during boot"); +VT_SYSCTL_INT(splash_ncpu, 0, "Override number of logos displayed " + "(0 = do not override)"); +VT_SYSCTL_INT(splash_cpu_style, 1, "Draw logo style " + "(0=Beastie, 1=Alternate beastie, 2=Orb)"); +VT_SYSCTL_INT(splash_cpu_duration, 10, "Hide logos after (seconds)"); + static struct vt_device vt_consdev; static unsigned int vt_unit = 0; static MALLOC_DEFINE(M_VT, "vt", "vt device"); @@ -176,7 +181,7 @@ SET_DECLARE(vt_drv_set, struct vt_driver); #define _VTDEFH MAX(100, PIXEL_HEIGHT(VT_FB_DEFAULT_HEIGHT)) #define _VTDEFW MAX(200, PIXEL_WIDTH(VT_FB_DEFAULT_WIDTH)) -static struct terminal vt_consterm; +struct terminal vt_consterm; static struct vt_window vt_conswindow; static struct vt_device vt_consdev = { .vd_driver = NULL, @@ -223,7 +228,7 @@ static struct vt_window vt_conswindow = { .vw_kbdmode = K_XLATE, .vw_grabbed = 0, }; -static struct terminal vt_consterm = { +struct terminal vt_consterm = { .tm_class = &vt_termclass, .tm_softc = &vt_conswindow, .tm_flags = TF_CONS, @@ -275,7 +280,7 @@ vt_schedule_flush(struct vt_device *vd, int ms) callout_schedule(&vd->vd_timer, hz / (1000 / ms)); } -static void +void vt_resume_flush_timer(struct vt_device *vd, int ms) { @@ -548,11 +553,13 @@ vt_window_switch(struct vt_window *vw) return (0); } -static inline void +void vt_termsize(struct vt_device *vd, struct vt_font *vf, term_pos_t *size) { size->tp_row = vd->vd_height; + if (vt_draw_logo_cpus) + size->tp_row -= vt_logo_sprite_height; size->tp_col = vd->vd_width; if (vf != NULL) { size->tp_row /= vf->vf_height; @@ -561,10 +568,33 @@ vt_termsize(struct vt_device *vd, struct vt_font *vf, term_pos_t *size) } static inline void +vt_termrect(struct vt_device *vd, struct vt_font *vf, term_rect_t *rect) +{ + + rect->tr_begin.tp_row = rect->tr_begin.tp_col = 0; + if (vt_draw_logo_cpus) + rect->tr_begin.tp_row = vt_logo_sprite_height; + + rect->tr_end.tp_row = vd->vd_height; + rect->tr_end.tp_col = vd->vd_width; + + if (vf != NULL) { + rect->tr_begin.tp_row = + howmany(rect->tr_begin.tp_row, vf->vf_height); + + rect->tr_end.tp_row /= vf->vf_height; + rect->tr_end.tp_col /= vf->vf_width; + } +} + +void vt_winsize(struct vt_device *vd, struct vt_font *vf, struct winsize *size) { - size->ws_row = size->ws_ypixel = vd->vd_height; + size->ws_ypixel = vd->vd_height; + if (vt_draw_logo_cpus) + size->ws_ypixel -= vt_logo_sprite_height; + size->ws_row = size->ws_ypixel; size->ws_col = size->ws_xpixel = vd->vd_width; if (vf != NULL) { size->ws_row /= vf->vf_height; @@ -572,17 +602,20 @@ vt_winsize(struct vt_device *vd, struct vt_font *vf, struct winsize *size) } } -static inline void +void vt_compute_drawable_area(struct vt_window *vw) { struct vt_device *vd; struct vt_font *vf; + vt_axis_t height; vd = vw->vw_device; if (vw->vw_font == NULL) { vw->vw_draw_area.tr_begin.tp_col = 0; vw->vw_draw_area.tr_begin.tp_row = 0; + if (vt_draw_logo_cpus) + vw->vw_draw_area.tr_begin.tp_row = vt_logo_sprite_height; vw->vw_draw_area.tr_end.tp_col = vd->vd_width; vw->vw_draw_area.tr_end.tp_row = vd->vd_height; return; @@ -595,12 +628,17 @@ vt_compute_drawable_area(struct vt_window *vw) * the screen. */ + height = vd->vd_height; + if (vt_draw_logo_cpus) + height -= vt_logo_sprite_height; vw->vw_draw_area.tr_begin.tp_col = (vd->vd_width % vf->vf_width) / 2; - vw->vw_draw_area.tr_begin.tp_row = (vd->vd_height % vf->vf_height) / 2; + vw->vw_draw_area.tr_begin.tp_row = (height % vf->vf_height) / 2; + if (vt_draw_logo_cpus) + vw->vw_draw_area.tr_begin.tp_row += vt_logo_sprite_height; vw->vw_draw_area.tr_end.tp_col = vw->vw_draw_area.tr_begin.tp_col + vd->vd_width / vf->vf_width * vf->vf_width; vw->vw_draw_area.tr_end.tp_row = vw->vw_draw_area.tr_begin.tp_row + - vd->vd_height / vf->vf_height * vf->vf_height; + height / vf->vf_height * vf->vf_height; } static void @@ -1111,7 +1149,6 @@ vt_flush(struct vt_device *vd) struct vt_window *vw; struct vt_font *vf; term_rect_t tarea; - term_pos_t size; #ifndef SC_NO_CUTPASTE int cursor_was_shown, cursor_moved; #endif @@ -1166,14 +1203,14 @@ vt_flush(struct vt_device *vd) #endif vtbuf_undirty(&vw->vw_buf, &tarea); - vt_termsize(vd, vf, &size); /* Force a full redraw when the screen contents are invalid. */ if (vd->vd_flags & VDF_INVALID) { - tarea.tr_begin.tp_row = tarea.tr_begin.tp_col = 0; - tarea.tr_end = size; - vd->vd_flags &= ~VDF_INVALID; + + vt_termrect(vd, vf, &tarea); + if (vt_draw_logo_cpus) + vtterm_draw_cpu_logos(vd); } if (tarea.tr_begin.tp_col < tarea.tr_end.tp_col) { @@ -1318,7 +1355,8 @@ vtterm_cnprobe(struct terminal *tm, struct consdev *cp) if (vtdbest != NULL) { #ifdef DEV_SPLASH - vtterm_splash(vd); + if (!vt_splash_cpu) + vtterm_splash(vd); #endif vd->vd_flags |= VDF_INITIALIZED; } diff --git a/sys/dev/vt/vt_cpulogos.c b/sys/dev/vt/vt_cpulogos.c new file mode 100644 index 000000000000..af604a806b0c --- /dev/null +++ b/sys/dev/vt/vt_cpulogos.c @@ -0,0 +1,266 @@ +/*- + * Copyright (c) 2015 Conrad Meyer + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +#include + +extern const unsigned char vt_beastie_vga16[]; +extern const unsigned char vt_beastie2_vga16[]; +extern const unsigned char vt_orb_vga16[]; + +static struct callout vt_splash_cpu_callout; + +static inline unsigned char +vt_vga2bsd(unsigned char vga) +{ + static const unsigned char lut[8] = { + 0, + 4, /* 1 and 4 swap */ + 2, + 6, /* 3 and 6 swap */ + 1, /* 4 and 1 swap */ + 5, + 3, /* 6 and 3 swap */ + 7, + }; + unsigned int bright; + + bright = (vga & 0x8); + return (lut[vga & 0x7] | bright); +} + +static void +vt_draw_2_vga16_px(struct vt_device *vd, vt_axis_t x, vt_axis_t y, + unsigned char color) +{ + + vd->vd_driver->vd_setpixel(vd, x, y, vt_vga2bsd(color >> 4)); + vd->vd_driver->vd_setpixel(vd, x + 1, y, vt_vga2bsd(color & 0xf)); +} + +static void +vt_draw_1_logo(struct vt_device *vd, vt_axis_t top, vt_axis_t left) +{ + const unsigned char rle_sent = 0x16, *data; + unsigned int xy, run, runcolor, i; + + switch (vt_splash_cpu_style) { + case VT_LOGOS_DRAW_ALT_BEASTIE: + data = vt_beastie2_vga16; + break; + case VT_LOGOS_DRAW_ORB: + data = vt_orb_vga16; + break; + case VT_LOGOS_DRAW_BEASTIE: + /* FALLTHROUGH */ + default: + data = vt_beastie_vga16; + break; + } + + /* Decode basic RLE (gets us to 30-40% of uncompressed data size): */ + for (i = 0, xy = 0; xy < vt_logo_sprite_height * vt_logo_sprite_width;) { + if (data[i] == rle_sent) { + runcolor = data[i + 1]; + run = data[i + 2]; + + for (; run; run--, xy += 2) + vt_draw_2_vga16_px(vd, + left + (xy % vt_logo_sprite_width), + top + (xy / vt_logo_sprite_width), + runcolor); + + i += 3; + } else { + vt_draw_2_vga16_px(vd, left + (xy % vt_logo_sprite_width), + top + (xy / vt_logo_sprite_width), data[i]); + + i++; + xy += 2; + } + } +} + +void +vtterm_draw_cpu_logos(struct vt_device *vd) +{ + unsigned int ncpu, i; + vt_axis_t left; + + if (vt_splash_ncpu) + ncpu = vt_splash_ncpu; + else { + ncpu = mp_ncpus; + if (ncpu < 1) + ncpu = 1; + } + + if (vd->vd_driver->vd_drawrect) + vd->vd_driver->vd_drawrect(vd, 0, 0, vd->vd_width, + vt_logo_sprite_height, 1, TC_BLACK); + /* + * Blank is okay because we only ever draw beasties on full screen + * refreshes. + */ + else if (vd->vd_driver->vd_blank) + vd->vd_driver->vd_blank(vd, TC_BLACK); + + ncpu = MIN(ncpu, vd->vd_width / vt_logo_sprite_width); + for (i = 0, left = 0; i < ncpu; left += vt_logo_sprite_width, i++) + vt_draw_1_logo(vd, 0, left); +} + +static void +vt_fini_logos(void *dummy __unused) +{ + struct vt_device *vd; + struct vt_window *vw; + struct terminal *tm; + struct vt_font *vf; + struct winsize wsz; + term_pos_t size; + + if (!vt_draw_logo_cpus) + return; + if (!vty_enabled(VTY_VT)) + return; + if (!vt_splash_cpu) + return; + + tm = &vt_consterm; + vw = tm->tm_softc; + if (vw == NULL) + return; + vd = vw->vw_device; + if (vd == NULL) + return; + vf = vw->vw_font; + if (vf == NULL) + return; + + VT_LOCK(vd); + if ((vd->vd_flags & (VDF_DEAD | VDF_TEXTMODE)) != 0) + goto out; + + vt_draw_logo_cpus = 0; + VT_UNLOCK(vd); + + vt_termsize(vd, vf, &size); + vt_winsize(vd, vf, &wsz); + + /* Resize screen buffer and terminal. */ + terminal_mute(tm, 1); + vtbuf_grow(&vw->vw_buf, &size, vw->vw_buf.vb_history_size); + terminal_set_winsize_blank(tm, &wsz, 0, NULL); + terminal_set_cursor(tm, &vw->vw_buf.vb_cursor); + terminal_mute(tm, 0); + + VT_LOCK(vd); + vt_compute_drawable_area(vw); + + if (vd->vd_curwindow == vw) { + vd->vd_flags |= VDF_INVALID; + vt_resume_flush_timer(vd, 0); + } + +out: + VT_UNLOCK(vd); +} + +static void +vt_init_logos(void *dummy) +{ + struct vt_device *vd; + struct vt_window *vw; + struct terminal *tm; + struct vt_font *vf; + struct winsize wsz; + term_pos_t size; + + if (!vty_enabled(VTY_VT)) + return; + if (!vt_splash_cpu) + return; + + tm = &vt_consterm; + vw = tm->tm_softc; + if (vw == NULL) + return; + vd = vw->vw_device; + if (vd == NULL) + return; + vf = vw->vw_font; + if (vf == NULL) + return; + + VT_LOCK(vd); + KASSERT((vd->vd_flags & VDF_INITIALIZED) != 0, + ("vd %p not initialized", vd)); + + if ((vd->vd_flags & (VDF_DEAD | VDF_TEXTMODE)) != 0) + goto out; + if (vd->vd_height <= vt_logo_sprite_height) + goto out; + + vt_draw_logo_cpus = 1; + VT_UNLOCK(vd); + + vt_termsize(vd, vf, &size); + vt_winsize(vd, vf, &wsz); + + /* Resize screen buffer and terminal. */ + terminal_mute(tm, 1); + vtbuf_grow(&vw->vw_buf, &size, vw->vw_buf.vb_history_size); + terminal_set_winsize_blank(tm, &wsz, 0, NULL); + terminal_set_cursor(tm, &vw->vw_buf.vb_cursor); + terminal_mute(tm, 0); + + VT_LOCK(vd); + vt_compute_drawable_area(vw); + + if (vd->vd_curwindow == vw) { + vd->vd_flags |= VDF_INVALID; + vt_resume_flush_timer(vd, 0); + } + + callout_init(&vt_splash_cpu_callout, 1); + callout_reset(&vt_splash_cpu_callout, vt_splash_cpu_duration * hz, + vt_fini_logos, NULL); + +out: + VT_UNLOCK(vd); +} +SYSINIT(vt_logos, SI_SUB_CPU + 1, SI_ORDER_ANY, vt_init_logos, NULL); diff --git a/sys/dev/xen/blkback/blkback.c b/sys/dev/xen/blkback/blkback.c index 459271ea26f8..f266ffd29020 100644 --- a/sys/dev/xen/blkback/blkback.c +++ b/sys/dev/xen/blkback/blkback.c @@ -2692,18 +2692,7 @@ xbb_open_backend(struct xbb_softc *xbb) if ((xbb->flags & XBBF_READ_ONLY) == 0) flags |= FWRITE; - if (!curthread->td_proc->p_fd->fd_cdir) { - curthread->td_proc->p_fd->fd_cdir = rootvnode; - VREF(rootvnode); - } - if (!curthread->td_proc->p_fd->fd_rdir) { - curthread->td_proc->p_fd->fd_rdir = rootvnode; - VREF(rootvnode); - } - if (!curthread->td_proc->p_fd->fd_jdir) { - curthread->td_proc->p_fd->fd_jdir = rootvnode; - VREF(rootvnode); - } + pwd_ensure_dirs(); again: NDINIT(&nd, LOOKUP, FOLLOW, UIO_SYSSPACE, xbb->dev_name, curthread); diff --git a/sys/fs/procfs/procfs_ctl.c b/sys/fs/procfs/procfs_ctl.c index 15679e36da32..b1f1cc863eef 100644 --- a/sys/fs/procfs/procfs_ctl.c +++ b/sys/fs/procfs/procfs_ctl.c @@ -142,7 +142,7 @@ procfs_control(struct thread *td, struct proc *p, int op) */ p->p_flag |= P_TRACED; faultin(p); - p->p_xstat = 0; /* XXX ? */ + p->p_xsig = 0; /* XXX ? */ p->p_oppid = p->p_pptr->p_pid; if (p->p_pptr != td->td_proc) { proc_reparent(p, td->td_proc); @@ -198,7 +198,7 @@ out: * To continue with a signal, just send * the signal name to the ctl file */ - p->p_xstat = 0; + p->p_xsig = 0; switch (op) { /* @@ -340,7 +340,7 @@ procfs_doprocctl(PFS_FILL_ARGS) PROC_LOCK(p); if (TRACE_WAIT_P(td->td_proc, p)) { - p->p_xstat = nm->nm_val; + p->p_xsig = nm->nm_val; #ifdef FIX_SSTEP FIX_SSTEP(FIRST_THREAD_IN_PROC(p)); #endif diff --git a/sys/fs/procfs/procfs_ioctl.c b/sys/fs/procfs/procfs_ioctl.c index 3fa00bcdfc69..0f37f07c3e35 100644 --- a/sys/fs/procfs/procfs_ioctl.c +++ b/sys/fs/procfs/procfs_ioctl.c @@ -140,7 +140,7 @@ procfs_ioctl(PFS_IOCTL_ARGS) ps->flags = 0; /* nope */ ps->events = p->p_stops; ps->why = p->p_step ? p->p_stype : 0; - ps->val = p->p_step ? p->p_xstat : 0; + ps->val = p->p_step ? p->p_xsig : 0; break; #ifdef COMPAT_FREEBSD32 case PIOCWAIT32: @@ -160,7 +160,7 @@ procfs_ioctl(PFS_IOCTL_ARGS) ps32->flags = 0; /* nope */ ps32->events = p->p_stops; ps32->why = p->p_step ? p->p_stype : 0; - ps32->val = p->p_step ? p->p_xstat : 0; + ps32->val = p->p_step ? p->p_xsig : 0; break; #endif #if defined(COMPAT_FREEBSD5) || defined(COMPAT_FREEBSD4) || defined(COMPAT_43) @@ -182,7 +182,7 @@ procfs_ioctl(PFS_IOCTL_ARGS) #if 0 p->p_step = 0; if (P_SHOULDSTOP(p)) { - p->p_xstat = sig; + p->p_xsig = sig; p->p_flag &= ~(P_STOPPED_TRACE|P_STOPPED_SIG); PROC_SLOCK(p); thread_unsuspend(p); diff --git a/sys/geom/eli/g_eli.c b/sys/geom/eli/g_eli.c index 6eea018286c4..a09472052b48 100644 --- a/sys/geom/eli/g_eli.c +++ b/sys/geom/eli/g_eli.c @@ -730,10 +730,10 @@ g_eli_create(struct gctl_req *req, struct g_class *mp, struct g_provider *bpp, sc = malloc(sizeof(*sc), M_ELI, M_WAITOK | M_ZERO); gp->start = g_eli_start; /* - * Spoiling cannot happen actually, because we keep provider open for - * writing all the time or provider is read-only. + * Spoiling can happen even though we have the provider open + * exclusively, e.g. through media change events. */ - gp->spoiled = g_eli_orphan_spoil_assert; + gp->spoiled = g_eli_orphan; gp->orphan = g_eli_orphan; gp->dumpconf = g_eli_dumpconf; /* diff --git a/sys/geom/part/g_part_gpt.c b/sys/geom/part/g_part_gpt.c index 08a31983a134..922e814735f8 100644 --- a/sys/geom/part/g_part_gpt.c +++ b/sys/geom/part/g_part_gpt.c @@ -1007,6 +1007,7 @@ g_part_gpt_setunset(struct g_part_table *basetable, { struct g_part_gpt_entry *entry; struct g_part_gpt_table *table; + struct g_provider *pp; uint8_t *p; uint64_t attr; int i; @@ -1036,6 +1037,21 @@ g_part_gpt_setunset(struct g_part_table *basetable, } } return (0); + } else if (strcasecmp(attrib, "lenovofix") == 0) { + /* + * Write the 0xee GPT entry to slot #1 (2nd slot) in the pMBR. + * This workaround allows Lenovo X220, T420, T520, etc to boot + * from GPT Partitions in BIOS mode. + */ + + if (entry != NULL) + return (ENXIO); + + pp = LIST_FIRST(&basetable->gpt_gp->consumer)->provider; + bzero(table->mbr + DOSPARTOFF, DOSPARTSIZE * NDOSPART); + gpt_write_mbr_entry(table->mbr, ((set) ? 1 : 0), 0xee, 1, + MIN(pp->mediasize / pp->sectorsize - 1, UINT32_MAX)); + return (0); } if (entry == NULL) diff --git a/sys/i386/conf/GENERIC b/sys/i386/conf/GENERIC index cc2b56fd00ef..dc11f73c4302 100644 --- a/sys/i386/conf/GENERIC +++ b/sys/i386/conf/GENERIC @@ -175,6 +175,7 @@ device ida # Compaq Smart RAID device mfi # LSI MegaRAID SAS device mlx # Mylex DAC960 family device mrsas # LSI/Avago MegaRAID SAS/SATA, 6Gb/s and 12Gb/s +device pmspcv # PMC-Sierra SAS/SATA Controller driver device pst # Promise Supertrak SX6000 device twe # 3ware ATA RAID @@ -379,5 +380,5 @@ device xenpci # Xen HVM Hypervisor services driver # VMware support device vmx # VMware VMXNET3 Ethernet -# The cypto framework is required by IPSEC +# The crypto framework is required by IPSEC device crypto # Required by IPSEC diff --git a/sys/i386/conf/NOTES b/sys/i386/conf/NOTES index 1bf81639f057..8ee521966990 100644 --- a/sys/i386/conf/NOTES +++ b/sys/i386/conf/NOTES @@ -22,7 +22,6 @@ options KDTRACE_HOOKS #device dtrace # DTrace modules -#device dtrace_lockstat #device dtrace_profile #device dtrace_sdt #device dtrace_fbt @@ -790,6 +789,9 @@ options ISCI_LOGGING # enable debugging in isci HAL device nvme # base NVMe driver device nvd # expose NVMe namespaces as disks, depends on nvme +# +# PMC-Sierra SAS/SATA controller +device pmspcv # # SafeNet crypto driver: can be moved to the MI NOTES as soon as # it's tested on a big-endian machine diff --git a/sys/i386/i386/db_trace.c b/sys/i386/i386/db_trace.c index f79765674bb6..356357919bda 100644 --- a/sys/i386/i386/db_trace.c +++ b/sys/i386/i386/db_trace.c @@ -48,16 +48,10 @@ __FBSDID("$FreeBSD$"); #include #include -static db_varfcn_t db_dr0; -static db_varfcn_t db_dr1; -static db_varfcn_t db_dr2; -static db_varfcn_t db_dr3; -static db_varfcn_t db_dr4; -static db_varfcn_t db_dr5; -static db_varfcn_t db_dr6; -static db_varfcn_t db_dr7; static db_varfcn_t db_esp; static db_varfcn_t db_frame; +static db_varfcn_t db_frame_seg; +static db_varfcn_t db_gs; static db_varfcn_t db_ss; /* @@ -65,10 +59,11 @@ static db_varfcn_t db_ss; */ #define DB_OFFSET(x) (db_expr_t *)offsetof(struct trapframe, x) struct db_variable db_regs[] = { - { "cs", DB_OFFSET(tf_cs), db_frame }, - { "ds", DB_OFFSET(tf_ds), db_frame }, - { "es", DB_OFFSET(tf_es), db_frame }, - { "fs", DB_OFFSET(tf_fs), db_frame }, + { "cs", DB_OFFSET(tf_cs), db_frame_seg }, + { "ds", DB_OFFSET(tf_ds), db_frame_seg }, + { "es", DB_OFFSET(tf_es), db_frame_seg }, + { "fs", DB_OFFSET(tf_fs), db_frame_seg }, + { "gs", NULL, db_gs }, { "ss", NULL, db_ss }, { "eax", DB_OFFSET(tf_eax), db_frame }, { "ecx", DB_OFFSET(tf_ecx), db_frame }, @@ -80,40 +75,8 @@ struct db_variable db_regs[] = { { "edi", DB_OFFSET(tf_edi), db_frame }, { "eip", DB_OFFSET(tf_eip), db_frame }, { "efl", DB_OFFSET(tf_eflags), db_frame }, -#define DB_N_SHOW_REGS 15 /* Don't show registers after here. */ - { "dr0", NULL, db_dr0 }, - { "dr1", NULL, db_dr1 }, - { "dr2", NULL, db_dr2 }, - { "dr3", NULL, db_dr3 }, - { "dr4", NULL, db_dr4 }, - { "dr5", NULL, db_dr5 }, - { "dr6", NULL, db_dr6 }, - { "dr7", NULL, db_dr7 }, }; -struct db_variable *db_eregs = db_regs + DB_N_SHOW_REGS; - -#define DB_DRX_FUNC(reg) \ -static int \ -db_ ## reg (vp, valuep, op) \ - struct db_variable *vp; \ - db_expr_t * valuep; \ - int op; \ -{ \ - if (op == DB_VAR_GET) \ - *valuep = r ## reg (); \ - else \ - load_ ## reg (*valuep); \ - return (1); \ -} - -DB_DRX_FUNC(dr0) -DB_DRX_FUNC(dr1) -DB_DRX_FUNC(dr2) -DB_DRX_FUNC(dr3) -DB_DRX_FUNC(dr4) -DB_DRX_FUNC(dr5) -DB_DRX_FUNC(dr6) -DB_DRX_FUNC(dr7) +struct db_variable *db_eregs = db_regs + nitems(db_regs); static __inline int get_esp(struct trapframe *tf) @@ -138,6 +101,22 @@ db_frame(struct db_variable *vp, db_expr_t *valuep, int op) return (1); } +static int +db_frame_seg(struct db_variable *vp, db_expr_t *valuep, int op) +{ + uint16_t *reg; + + if (kdb_frame == NULL) + return (0); + + reg = (uint16_t *)((uintptr_t)kdb_frame + (db_expr_t)vp->valuep); + if (op == DB_VAR_GET) + *valuep = *reg; + else + *reg = *valuep; + return (1); +} + static int db_esp(struct db_variable *vp, db_expr_t *valuep, int op) { @@ -152,6 +131,17 @@ db_esp(struct db_variable *vp, db_expr_t *valuep, int op) return (1); } +static int +db_gs(struct db_variable *vp, db_expr_t *valuep, int op) +{ + + if (op == DB_VAR_GET) + *valuep = rgs(); + else + load_gs(*valuep); + return (1); +} + static int db_ss(struct db_variable *vp, db_expr_t *valuep, int op) { @@ -389,7 +379,7 @@ db_nextframe(struct i386_frame **fp, db_addr_t *ip, struct thread *td) static int db_backtrace(struct thread *td, struct trapframe *tf, struct i386_frame *frame, - db_addr_t pc, int count) + db_addr_t pc, register_t sp, int count) { struct i386_frame *actframe; #define MAXNARG 16 @@ -446,7 +436,21 @@ db_backtrace(struct thread *td, struct trapframe *tf, struct i386_frame *frame, */ actframe = frame; if (first) { - if (tf != NULL) { + first = FALSE; + if (sym == C_DB_SYM_NULL && sp != 0) { + /* + * If a symbol couldn't be found, we've probably + * jumped to a bogus location, so try and use + * the return address to find our caller. + */ + db_print_stack_entry(name, 0, 0, 0, pc, + NULL); + pc = db_get_value(sp, 4, FALSE); + if (db_search_symbol(pc, DB_STGY_PROC, + &offset) == C_DB_SYM_NULL) + break; + continue; + } else if (tf != NULL) { instr = db_get_value(pc, 4, FALSE); if ((instr & 0xffffff) == 0x00e58955) { /* pushl %ebp; movl %esp, %ebp */ @@ -474,7 +478,6 @@ db_backtrace(struct thread *td, struct trapframe *tf, struct i386_frame *frame, actframe); break; } - first = FALSE; } argp = &actframe->f_arg0; @@ -521,17 +524,19 @@ db_trace_self(void) frame = (struct i386_frame *)ebp; callpc = (db_addr_t)db_get_value((int)&frame->f_retaddr, 4, FALSE); frame = frame->f_frame; - db_backtrace(curthread, NULL, frame, callpc, -1); + db_backtrace(curthread, NULL, frame, callpc, 0, -1); } int db_trace_thread(struct thread *thr, int count) { struct pcb *ctx; + struct trapframe *tf; ctx = kdb_thr_ctx(thr); - return (db_backtrace(thr, NULL, (struct i386_frame *)ctx->pcb_ebp, - ctx->pcb_eip, count)); + tf = thr == kdb_thread ? kdb_frame : NULL; + return (db_backtrace(thr, tf, (struct i386_frame *)ctx->pcb_ebp, + ctx->pcb_eip, ctx->pcb_esp, count)); } int diff --git a/sys/i386/i386/machdep.c b/sys/i386/i386/machdep.c index e014a785f908..2be5dbc5070e 100644 --- a/sys/i386/i386/machdep.c +++ b/sys/i386/i386/machdep.c @@ -1582,6 +1582,29 @@ DB_SHOW_COMMAND(sysregs, db_show_sysregs) db_printf("cr2\t0x%08x\n", rcr2()); db_printf("cr3\t0x%08x\n", rcr3()); db_printf("cr4\t0x%08x\n", rcr4()); + if (rcr4() & CR4_XSAVE) + db_printf("xcr0\t0x%016llx\n", rxcr(0)); + if (amd_feature & (AMDID_NX | AMDID_LM)) + db_printf("EFER\t0x%016llx\n", rdmsr(MSR_EFER)); + if (cpu_feature2 & (CPUID2_VMX | CPUID2_SMX)) + db_printf("FEATURES_CTL\t0x%016llx\n", + rdmsr(MSR_IA32_FEATURE_CONTROL)); + if ((cpu_vendor_id == CPU_VENDOR_INTEL || + cpu_vendor_id == CPU_VENDOR_AMD) && CPUID_TO_FAMILY(cpu_id) >= 6) + db_printf("DEBUG_CTL\t0x%016llx\n", rdmsr(MSR_DEBUGCTLMSR)); + if (cpu_feature & CPUID_PAT) + db_printf("PAT\t0x%016llx\n", rdmsr(MSR_PAT)); +} + +DB_SHOW_COMMAND(dbregs, db_show_dbregs) +{ + + db_printf("dr0\t0x%08x\n", rdr0()); + db_printf("dr1\t0x%08x\n", rdr1()); + db_printf("dr2\t0x%08x\n", rdr2()); + db_printf("dr3\t0x%08x\n", rdr3()); + db_printf("dr6\t0x%08x\n", rdr6()); + db_printf("dr7\t0x%08x\n", rdr7()); } #endif diff --git a/sys/i386/i386/mp_machdep.c b/sys/i386/i386/mp_machdep.c index bad69ee14839..083aa4af0ec9 100644 --- a/sys/i386/i386/mp_machdep.c +++ b/sys/i386/i386/mp_machdep.c @@ -144,7 +144,6 @@ volatile int smp_tlb_wait; static void install_ap_tramp(void); static int start_all_aps(void); static int start_ap(int apic_id); -static void release_aps(void *dummy); static u_int boot_address; diff --git a/sys/i386/i386/stack_machdep.c b/sys/i386/i386/stack_machdep.c index 2a5dfdac88ae..8dbb9ab84602 100644 --- a/sys/i386/i386/stack_machdep.c +++ b/sys/i386/i386/stack_machdep.c @@ -40,7 +40,7 @@ __FBSDID("$FreeBSD$"); #include static void -stack_capture(struct stack *st, register_t ebp) +stack_capture(struct thread *td, struct stack *st, register_t ebp) { struct i386_frame *frame; vm_offset_t callpc; @@ -56,8 +56,8 @@ stack_capture(struct stack *st, register_t ebp) if (stack_put(st, callpc) == -1) break; if (frame->f_frame <= frame || - (vm_offset_t)frame->f_frame >= - (vm_offset_t)ebp + KSTACK_PAGES * PAGE_SIZE) + (vm_offset_t)frame->f_frame >= td->td_kstack + + td->td_kstack_pages * PAGE_SIZE) break; frame = frame->f_frame; } @@ -74,7 +74,7 @@ stack_save_td(struct stack *st, struct thread *td) panic("stack_save_td: running"); ebp = td->td_pcb->pcb_ebp; - stack_capture(st, ebp); + stack_capture(td, st, ebp); } void @@ -83,5 +83,5 @@ stack_save(struct stack *st) register_t ebp; __asm __volatile("movl %%ebp,%0" : "=r" (ebp)); - stack_capture(st, ebp); + stack_capture(curthread, st, ebp); } diff --git a/sys/i386/include/frame.h b/sys/i386/include/frame.h index 150ea207f87e..b006c1ea70ba 100644 --- a/sys/i386/include/frame.h +++ b/sys/i386/include/frame.h @@ -1,14 +1,44 @@ /*- - * This file is in the public domain. + * Copyright (c) 2003 Peter Wemm. + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * William Jolitz. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ */ -/* $FreeBSD$ */ + +#ifndef _I386_FRAME_H_ +#define _I386_FRAME_H_ #include -#ifndef __I386_FRAME_H__ -#define __i386_FRAME_H__ - #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) -#endif +#endif /* _I386_FRAME_H_ */ diff --git a/sys/i386/include/smp.h b/sys/i386/include/smp.h index 71c830ea895a..46184195e17a 100644 --- a/sys/i386/include/smp.h +++ b/sys/i386/include/smp.h @@ -39,7 +39,6 @@ extern int cpu_apic_ids[]; extern int bootAP; extern void *dpcpu; extern char *bootSTK; -extern int bootAP; extern void *bootstacks[]; extern volatile u_int cpu_ipi_pending[]; extern volatile int aps_ready; diff --git a/sys/i386/isa/npx.c b/sys/i386/isa/npx.c index d3cd628dc990..ed21a183222a 100644 --- a/sys/i386/isa/npx.c +++ b/sys/i386/isa/npx.c @@ -1173,16 +1173,20 @@ npx_fill_fpregs_xmm1(struct savexmm *sv_xmm, struct save87 *sv_87) /* FPU control/status */ penv_87->en_cw = penv_xmm->en_cw; penv_87->en_sw = penv_xmm->en_sw; - penv_87->en_tw = penv_xmm->en_tw; penv_87->en_fip = penv_xmm->en_fip; penv_87->en_fcs = penv_xmm->en_fcs; penv_87->en_opcode = penv_xmm->en_opcode; penv_87->en_foo = penv_xmm->en_foo; penv_87->en_fos = penv_xmm->en_fos; - /* FPU registers */ - for (i = 0; i < 8; ++i) + /* FPU registers and tags */ + penv_87->en_tw = 0xffff; + for (i = 0; i < 8; ++i) { sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc; + if ((penv_xmm->en_tw & (1 << i)) != 0) + /* zero and special are set as valid */ + penv_87->en_tw &= ~(3 << i); + } } void @@ -1206,16 +1210,19 @@ npx_set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm) /* FPU control/status */ penv_xmm->en_cw = penv_87->en_cw; penv_xmm->en_sw = penv_87->en_sw; - penv_xmm->en_tw = penv_87->en_tw; penv_xmm->en_fip = penv_87->en_fip; penv_xmm->en_fcs = penv_87->en_fcs; penv_xmm->en_opcode = penv_87->en_opcode; penv_xmm->en_foo = penv_87->en_foo; penv_xmm->en_fos = penv_87->en_fos; - /* FPU registers */ - for (i = 0; i < 8; ++i) + /* FPU registers and tags */ + penv_xmm->en_tw = 0; + for (i = 0; i < 8; ++i) { sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i]; + if ((penv_87->en_tw && (3 << i)) != (3 << i)) + penv_xmm->en_tw |= 1 << i; + } } #endif /* CPU_ENABLE_SSE */ diff --git a/sys/kern/imgact_elf.c b/sys/kern/imgact_elf.c index 067512831e3e..cfe5f109b705 100644 --- a/sys/kern/imgact_elf.c +++ b/sys/kern/imgact_elf.c @@ -1241,6 +1241,7 @@ __elfN(coredump)(struct thread *td, struct vnode *vp, off_t limit, int flags) compress = (flags & IMGACT_CORE_COMPRESS) != 0; hdr = NULL; + tmpbuf = NULL; TAILQ_INIT(¬elst); /* Size the program segments. */ @@ -1255,6 +1256,14 @@ __elfN(coredump)(struct thread *td, struct vnode *vp, off_t limit, int flags) __elfN(prepare_notes)(td, ¬elst, ¬esz); coresize = round_page(hdrsize + notesz) + seginfo.size; + /* Set up core dump parameters. */ + params.offset = 0; + params.active_cred = cred; + params.file_cred = NOCRED; + params.td = td; + params.vp = vp; + params.gzs = NULL; + #ifdef RACCT if (racct_enable) { PROC_LOCK(td->td_proc); @@ -1271,15 +1280,6 @@ __elfN(coredump)(struct thread *td, struct vnode *vp, off_t limit, int flags) goto done; } - /* Set up core dump parameters. */ - params.offset = 0; - params.active_cred = cred; - params.file_cred = NOCRED; - params.td = td; - params.vp = vp; - params.gzs = NULL; - - tmpbuf = NULL; #ifdef GZIO /* Create a compression stream if necessary. */ if (compress) { @@ -1336,7 +1336,8 @@ done: #ifdef GZIO if (compress) { free(tmpbuf, M_TEMP); - gzio_fini(params.gzs); + if (params.gzs != NULL) + gzio_fini(params.gzs); } #endif while ((ninfo = TAILQ_FIRST(¬elst)) != NULL) { diff --git a/sys/kern/init_main.c b/sys/kern/init_main.c index 37539c41dc9f..a362d00fbfdf 100644 --- a/sys/kern/init_main.c +++ b/sys/kern/init_main.c @@ -87,6 +87,7 @@ __FBSDID("$FreeBSD$"); #include #include #include +#include #include #include @@ -496,6 +497,10 @@ proc0_init(void *dummy __unused) td->td_flags = TDF_INMEM; td->td_pflags = TDP_KTHREAD; td->td_cpuset = cpuset_thread0(); + vm_domain_policy_init(&td->td_vm_dom_policy); + vm_domain_policy_set(&td->td_vm_dom_policy, VM_POLICY_NONE, -1); + vm_domain_policy_init(&p->p_vm_dom_policy); + vm_domain_policy_set(&p->p_vm_dom_policy, VM_POLICY_NONE, -1); prison0_init(); p->p_peers = 0; p->p_leader = p; @@ -822,6 +827,7 @@ static void create_init(const void *udata __unused) { struct ucred *newcred, *oldcred; + struct thread *td; int error; error = fork1(&thread0, RFFDG | RFPROC | RFSTOPPED, 0, &initproc, @@ -845,7 +851,9 @@ create_init(const void *udata __unused) audit_cred_proc1(newcred); #endif proc_set_cred(initproc, newcred); - cred_update_thread(FIRST_THREAD_IN_PROC(initproc)); + td = FIRST_THREAD_IN_PROC(initproc); + crfree(td->td_ucred); + td->td_ucred = crhold(initproc->p_ucred); PROC_UNLOCK(initproc); sx_xunlock(&proctree_lock); crfree(oldcred); diff --git a/sys/kern/init_sysent.c b/sys/kern/init_sysent.c index 14e828161f7f..a32890698727 100644 --- a/sys/kern/init_sysent.c +++ b/sys/kern/init_sysent.c @@ -588,4 +588,6 @@ struct sysent sysent[] = { { AS(ppoll_args), (sy_call_t *)sys_ppoll, AUE_POLL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 545 = ppoll */ { AS(futimens_args), (sy_call_t *)sys_futimens, AUE_FUTIMES, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC }, /* 546 = futimens */ { AS(utimensat_args), (sy_call_t *)sys_utimensat, AUE_FUTIMESAT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC }, /* 547 = utimensat */ + { AS(numa_getaffinity_args), (sy_call_t *)sys_numa_getaffinity, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 548 = numa_getaffinity */ + { AS(numa_setaffinity_args), (sy_call_t *)sys_numa_setaffinity, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 549 = numa_setaffinity */ }; diff --git a/sys/kern/kern_clocksource.c b/sys/kern/kern_clocksource.c index cbbbce445420..cc7847c2b5de 100644 --- a/sys/kern/kern_clocksource.c +++ b/sys/kern/kern_clocksource.c @@ -116,7 +116,7 @@ struct pcpu_state { sbintime_t now; /* Last tick time. */ sbintime_t nextevent; /* Next scheduled event on this CPU. */ sbintime_t nexttick; /* Next timer tick time. */ - sbintime_t nexthard; /* Next hardlock() event. */ + sbintime_t nexthard; /* Next hardclock() event. */ sbintime_t nextstat; /* Next statclock() event. */ sbintime_t nextprof; /* Next profclock() event. */ sbintime_t nextcall; /* Next callout event. */ diff --git a/sys/kern/kern_descrip.c b/sys/kern/kern_descrip.c index 3f2a4e432bee..933e4cc5cc81 100644 --- a/sys/kern/kern_descrip.c +++ b/sys/kern/kern_descrip.c @@ -68,6 +68,7 @@ __FBSDID("$FreeBSD$"); #include #include #include +#include #include #include #include @@ -224,7 +225,6 @@ fd_last_used(struct filedesc *fdp, int size) return (-1); } -#ifdef INVARIANTS static int fdisused(struct filedesc *fdp, int fd) { @@ -234,7 +234,6 @@ fdisused(struct filedesc *fdp, int fd) return ((fdp->fd_map[NDSLOT(fd)] & NDBIT(fd)) != 0); } -#endif /* * Mark a file descriptor as used. @@ -310,6 +309,24 @@ fdfree(struct filedesc *fdp, int fd) #endif } +void +pwd_ensure_dirs(void) +{ + struct filedesc *fdp; + + fdp = curproc->p_fd; + FILEDESC_XLOCK(fdp); + if (fdp->fd_cdir == NULL) { + fdp->fd_cdir = rootvnode; + VREF(rootvnode); + } + if (fdp->fd_rdir == NULL) { + fdp->fd_rdir = rootvnode; + VREF(rootvnode); + } + FILEDESC_XUNLOCK(fdp); +} + /* * System calls on descriptors. */ @@ -355,7 +372,7 @@ int sys_dup2(struct thread *td, struct dup2_args *uap) { - return (kern_dup(td, FDDUP_FIXED, (int)uap->from, (int)uap->to)); + return (kern_dup(td, FDDUP_FIXED, 0, (int)uap->from, (int)uap->to)); } /* @@ -371,7 +388,7 @@ int sys_dup(struct thread *td, struct dup_args *uap) { - return (kern_dup(td, 0, (int)uap->fd, 0)); + return (kern_dup(td, FDDUP_NORMAL, 0, (int)uap->fd, 0)); } /* @@ -481,22 +498,22 @@ kern_fcntl(struct thread *td, int fd, int cmd, intptr_t arg) switch (cmd) { case F_DUPFD: tmp = arg; - error = kern_dup(td, FDDUP_FCNTL, fd, tmp); + error = kern_dup(td, FDDUP_FCNTL, 0, fd, tmp); break; case F_DUPFD_CLOEXEC: tmp = arg; - error = kern_dup(td, FDDUP_FCNTL | FDDUP_CLOEXEC, fd, tmp); + error = kern_dup(td, FDDUP_FCNTL, FDDUP_FLAG_CLOEXEC, fd, tmp); break; case F_DUP2FD: tmp = arg; - error = kern_dup(td, FDDUP_FIXED, fd, tmp); + error = kern_dup(td, FDDUP_FIXED, 0, fd, tmp); break; case F_DUP2FD_CLOEXEC: tmp = arg; - error = kern_dup(td, FDDUP_FIXED | FDDUP_CLOEXEC, fd, tmp); + error = kern_dup(td, FDDUP_FIXED, FDDUP_FLAG_CLOEXEC, fd, tmp); break; case F_GETFD: @@ -789,22 +806,19 @@ getmaxfd(struct thread *td) * Common code for dup, dup2, fcntl(F_DUPFD) and fcntl(F_DUP2FD). */ int -kern_dup(struct thread *td, int flags, int old, int new) +kern_dup(struct thread *td, u_int mode, int flags, int old, int new) { struct filedesc *fdp; struct filedescent *oldfde, *newfde; struct proc *p; - struct file *fp; struct file *delfp; int error, maxfd; p = td->td_proc; fdp = p->p_fd; - MPASS((flags & ~(FDDUP_FIXED | FDDUP_FCNTL | FDDUP_CLOEXEC | - FDDUP_MUSTREPLACE)) == 0); - MPASS((flags & (FDDUP_FIXED | FDDUP_MUSTREPLACE)) != - (FDDUP_FIXED | FDDUP_MUSTREPLACE)); + MPASS((flags & ~(FDDUP_FLAG_CLOEXEC)) == 0); + MPASS(mode < FDDUP_LASTMODE); /* * Verify we have a valid descriptor to dup from and possibly to @@ -814,42 +828,45 @@ kern_dup(struct thread *td, int flags, int old, int new) if (old < 0) return (EBADF); if (new < 0) - return (flags & FDDUP_FCNTL ? EINVAL : EBADF); + return (mode == FDDUP_FCNTL ? EINVAL : EBADF); maxfd = getmaxfd(td); if (new >= maxfd) - return (flags & FDDUP_FCNTL ? EINVAL : EBADF); + return (mode == FDDUP_FCNTL ? EINVAL : EBADF); FILEDESC_XLOCK(fdp); if (fget_locked(fdp, old) == NULL) { FILEDESC_XUNLOCK(fdp); return (EBADF); } - oldfde = &fdp->fd_ofiles[old]; - if (flags & (FDDUP_FIXED | FDDUP_MUSTREPLACE) && old == new) { + if ((mode == FDDUP_FIXED || mode == FDDUP_MUSTREPLACE) && old == new) { td->td_retval[0] = new; - if (flags & FDDUP_CLOEXEC) + if (flags & FDDUP_FLAG_CLOEXEC) fdp->fd_ofiles[new].fde_flags |= UF_EXCLOSE; FILEDESC_XUNLOCK(fdp); return (0); } - fp = oldfde->fde_file; - fhold(fp); /* * If the caller specified a file descriptor, make sure the file * table is large enough to hold it, and grab it. Otherwise, just * allocate a new descriptor the usual way. */ - if (flags & FDDUP_MUSTREPLACE) { - /* Target file descriptor must exist. */ - if (new >= fdp->fd_nfiles || - fdp->fd_ofiles[new].fde_file == NULL) { + switch (mode) { + case FDDUP_NORMAL: + case FDDUP_FCNTL: + if ((error = fdalloc(td, new, &new)) != 0) { + FILEDESC_XUNLOCK(fdp); + return (error); + } + break; + case FDDUP_MUSTREPLACE: + /* Target file descriptor must exist. */ + if (fget_locked(fdp, new) == NULL) { FILEDESC_XUNLOCK(fdp); - fdrop(fp, td); return (EBADF); } - newfde = &fdp->fd_ofiles[new]; - } else if (flags & FDDUP_FIXED) { + break; + case FDDUP_FIXED: if (new >= fdp->fd_nfiles) { /* * The resource limits are here instead of e.g. @@ -866,29 +883,24 @@ kern_dup(struct thread *td, int flags, int old, int new) PROC_UNLOCK(p); if (error != 0) { FILEDESC_XUNLOCK(fdp); - fdrop(fp, td); return (EMFILE); } } #endif fdgrowtable_exp(fdp, new + 1); - oldfde = &fdp->fd_ofiles[old]; } - newfde = &fdp->fd_ofiles[new]; - if (newfde->fde_file == NULL) + if (!fdisused(fdp, new)) fdused(fdp, new); - } else { - if ((error = fdalloc(td, new, &new)) != 0) { - FILEDESC_XUNLOCK(fdp); - fdrop(fp, td); - return (error); - } - newfde = &fdp->fd_ofiles[new]; + break; + default: + KASSERT(0, ("%s unsupported mode %d", __func__, mode)); } - KASSERT(fp == oldfde->fde_file, ("old fd has been modified")); KASSERT(old != new, ("new fd is same as old")); + oldfde = &fdp->fd_ofiles[old]; + fhold(oldfde->fde_file); + newfde = &fdp->fd_ofiles[new]; delfp = newfde->fde_file; /* @@ -900,7 +912,7 @@ kern_dup(struct thread *td, int flags, int old, int new) filecaps_free(&newfde->fde_caps); memcpy(newfde, oldfde, fde_change_size); filecaps_copy(&oldfde->fde_caps, &newfde->fde_caps); - if ((flags & FDDUP_CLOEXEC) != 0) + if ((flags & FDDUP_FLAG_CLOEXEC) != 0) newfde->fde_flags = oldfde->fde_flags | UF_EXCLOSE; else newfde->fde_flags = oldfde->fde_flags & ~UF_EXCLOSE; @@ -1909,6 +1921,14 @@ fdunshare(struct thread *td) p->p_fd = tmp; } +void +fdinstall_remapped(struct thread *td, struct filedesc *fdp) +{ + + fdescfree(td); + td->td_proc->p_fd = fdp; +} + /* * Copy a filedesc structure. A NULL pointer in returns a NULL reference, * this is to ease callers, not catch errors. @@ -1947,6 +1967,65 @@ fdcopy(struct filedesc *fdp) return (newfdp); } +/* + * Copies a filedesc structure, while remapping all file descriptors + * stored inside using a translation table. + * + * File descriptors are copied over to the new file descriptor table, + * regardless of whether the close-on-exec flag is set. + */ +int +fdcopy_remapped(struct filedesc *fdp, const int *fds, size_t nfds, + struct filedesc **ret) +{ + struct filedesc *newfdp; + struct filedescent *nfde, *ofde; + int error, i; + + MPASS(fdp != NULL); + + newfdp = fdinit(fdp, true); + if (nfds > fdp->fd_lastfile + 1) { + /* New table cannot be larger than the old one. */ + error = E2BIG; + goto bad; + } + /* Copy all passable descriptors (i.e. not kqueue). */ + newfdp->fd_freefile = nfds; + for (i = 0; i < nfds; ++i) { + if (fds[i] < 0 || fds[i] > fdp->fd_lastfile) { + /* File descriptor out of bounds. */ + error = EBADF; + goto bad; + } + ofde = &fdp->fd_ofiles[fds[i]]; + if (ofde->fde_file == NULL) { + /* Unused file descriptor. */ + error = EBADF; + goto bad; + } + if ((ofde->fde_file->f_ops->fo_flags & DFLAG_PASSABLE) == 0) { + /* File descriptor cannot be passed. */ + error = EINVAL; + goto bad; + } + nfde = &newfdp->fd_ofiles[i]; + *nfde = *ofde; + filecaps_copy(&ofde->fde_caps, &nfde->fde_caps); + fhold(nfde->fde_file); + fdused_init(newfdp, i); + newfdp->fd_lastfile = i; + } + newfdp->fd_cmask = fdp->fd_cmask; + FILEDESC_SUNLOCK(fdp); + *ret = newfdp; + return (0); +bad: + FILEDESC_SUNLOCK(fdp); + fdescfree_remapped(newfdp); + return (error); +} + /* * Clear POSIX style locks. This is only used when fdp looses a reference (i.e. * one of processes using it exits) and the table used to be shared. @@ -2031,17 +2110,45 @@ retry: /* * Release a filedesc structure. */ +static void +fdescfree_fds(struct thread *td, struct filedesc *fdp, bool needclose) +{ + struct filedesc0 *fdp0; + struct freetable *ft, *tft; + struct filedescent *fde; + struct file *fp; + int i; + + for (i = 0; i <= fdp->fd_lastfile; i++) { + fde = &fdp->fd_ofiles[i]; + fp = fde->fde_file; + if (fp != NULL) { + fdefree_last(fde); + if (needclose) + (void) closef(fp, td); + else + fdrop(fp, td); + } + } + + if (NDSLOTS(fdp->fd_nfiles) > NDSLOTS(NDFILE)) + free(fdp->fd_map, M_FILEDESC); + if (fdp->fd_nfiles > NDFILE) + free(fdp->fd_files, M_FILEDESC); + + fdp0 = (struct filedesc0 *)fdp; + SLIST_FOREACH_SAFE(ft, &fdp0->fd_free, ft_next, tft) + free(ft->ft_table, M_FILEDESC); + + fddrop(fdp); +} + void fdescfree(struct thread *td) { struct proc *p; - struct filedesc0 *fdp0; struct filedesc *fdp; - struct freetable *ft, *tft; - struct filedescent *fde; - struct file *fp; struct vnode *cdir, *jdir, *rdir; - int i; p = td->td_proc; fdp = p->p_fd; @@ -2055,7 +2162,7 @@ fdescfree(struct thread *td) } #endif - if (td->td_proc->p_fdtol != NULL) + if (p->p_fdtol != NULL) fdclearlocks(td); PROC_LOCK(p); @@ -2074,24 +2181,6 @@ fdescfree(struct thread *td) fdp->fd_jdir = NULL; FILEDESC_XUNLOCK(fdp); - for (i = 0; i <= fdp->fd_lastfile; i++) { - fde = &fdp->fd_ofiles[i]; - fp = fde->fde_file; - if (fp != NULL) { - fdefree_last(fde); - (void) closef(fp, td); - } - } - - if (NDSLOTS(fdp->fd_nfiles) > NDSLOTS(NDFILE)) - free(fdp->fd_map, M_FILEDESC); - if (fdp->fd_nfiles > NDFILE) - free(fdp->fd_files, M_FILEDESC); - - fdp0 = (struct filedesc0 *)fdp; - SLIST_FOREACH_SAFE(ft, &fdp0->fd_free, ft_next, tft) - free(ft->ft_table, M_FILEDESC); - if (cdir != NULL) vrele(cdir); if (rdir != NULL) @@ -2099,7 +2188,21 @@ fdescfree(struct thread *td) if (jdir != NULL) vrele(jdir); - fddrop(fdp); + fdescfree_fds(td, fdp, 1); +} + +void +fdescfree_remapped(struct filedesc *fdp) +{ + + if (fdp->fd_cdir != NULL) + vrele(fdp->fd_cdir); + if (fdp->fd_rdir != NULL) + vrele(fdp->fd_rdir); + if (fdp->fd_jdir != NULL) + vrele(fdp->fd_jdir); + + fdescfree_fds(curthread, fdp, 0); } /* @@ -2223,7 +2326,7 @@ fdcheckstd(struct thread *td) save = td->td_retval[0]; if (devnull != -1) { - error = kern_dup(td, FDDUP_FIXED, devnull, i); + error = kern_dup(td, FDDUP_FIXED, 0, devnull, i); } else { error = kern_openat(td, AT_FDCWD, "/dev/null", UIO_SYSSPACE, O_RDWR, 0); @@ -2861,6 +2964,96 @@ dupfdopen(struct thread *td, struct filedesc *fdp, int dfd, int mode, return (0); } +/* + * This sysctl determines if we will allow a process to chroot(2) if it + * has a directory open: + * 0: disallowed for all processes. + * 1: allowed for processes that were not already chroot(2)'ed. + * 2: allowed for all processes. + */ + +static int chroot_allow_open_directories = 1; + +SYSCTL_INT(_kern, OID_AUTO, chroot_allow_open_directories, CTLFLAG_RW, + &chroot_allow_open_directories, 0, + "Allow a process to chroot(2) if it has a directory open"); + +/* + * Helper function for raised chroot(2) security function: Refuse if + * any filedescriptors are open directories. + */ +static int +chroot_refuse_vdir_fds(struct filedesc *fdp) +{ + struct vnode *vp; + struct file *fp; + int fd; + + FILEDESC_LOCK_ASSERT(fdp); + + for (fd = 0; fd <= fdp->fd_lastfile; fd++) { + fp = fget_locked(fdp, fd); + if (fp == NULL) + continue; + if (fp->f_type == DTYPE_VNODE) { + vp = fp->f_vnode; + if (vp->v_type == VDIR) + return (EPERM); + } + } + return (0); +} + +/* + * Common routine for kern_chroot() and jail_attach(). The caller is + * responsible for invoking priv_check() and mac_vnode_check_chroot() to + * authorize this operation. + */ +int +pwd_chroot(struct thread *td, struct vnode *vp) +{ + struct filedesc *fdp; + struct vnode *oldvp; + int error; + + fdp = td->td_proc->p_fd; + FILEDESC_XLOCK(fdp); + if (chroot_allow_open_directories == 0 || + (chroot_allow_open_directories == 1 && fdp->fd_rdir != rootvnode)) { + error = chroot_refuse_vdir_fds(fdp); + if (error != 0) { + FILEDESC_XUNLOCK(fdp); + return (error); + } + } + oldvp = fdp->fd_rdir; + VREF(vp); + fdp->fd_rdir = vp; + if (fdp->fd_jdir == NULL) { + VREF(vp); + fdp->fd_jdir = vp; + } + FILEDESC_XUNLOCK(fdp); + vrele(oldvp); + return (0); +} + +void +pwd_chdir(struct thread *td, struct vnode *vp) +{ + struct filedesc *fdp; + struct vnode *oldvp; + + fdp = td->td_proc->p_fd; + FILEDESC_XLOCK(fdp); + VNASSERT(vp->v_usecount > 0, vp, + ("chdir to a vnode with zero usecount")); + oldvp = fdp->fd_cdir; + fdp->fd_cdir = vp; + FILEDESC_XUNLOCK(fdp); + vrele(oldvp); +} + /* * Scan all active processes and prisons to see if any of them have a current * or root directory of `olddp'. If so, replace them with the new mount point. diff --git a/sys/kern/kern_event.c b/sys/kern/kern_event.c index ff17fe9b8d7c..f8c6cf099fe5 100644 --- a/sys/kern/kern_event.c +++ b/sys/kern/kern_event.c @@ -436,7 +436,7 @@ filt_proc(struct knote *kn, long hint) kn->kn_flags |= EV_EOF | EV_ONESHOT; kn->kn_ptr.p_proc = NULL; if (kn->kn_fflags & NOTE_EXIT) - kn->kn_data = p->p_xstat; + kn->kn_data = KW_EXITCODE(p->p_xexit, p->p_xsig); if (kn->kn_fflags == 0) kn->kn_flags |= EV_DROP; return (1); diff --git a/sys/kern/kern_exec.c b/sys/kern/kern_exec.c index 859b2e342825..517b68978338 100644 --- a/sys/kern/kern_exec.c +++ b/sys/kern/kern_exec.c @@ -359,7 +359,7 @@ do_execve(td, args, mac_p) struct vnode *tracevp = NULL; struct ucred *tracecred = NULL; #endif - struct vnode *textvp = NULL, *binvp; + struct vnode *oldtextvp = NULL, *newtextvp; cap_rights_t rights; int credential_changing; int textset; @@ -433,20 +433,20 @@ interpret: if (error) goto exec_fail; - binvp = nd.ni_vp; - imgp->vp = binvp; + newtextvp = nd.ni_vp; + imgp->vp = newtextvp; } else { AUDIT_ARG_FD(args->fd); /* * Descriptors opened only with O_EXEC or O_RDONLY are allowed. */ error = fgetvp_exec(td, args->fd, - cap_rights_init(&rights, CAP_FEXECVE), &binvp); + cap_rights_init(&rights, CAP_FEXECVE), &newtextvp); if (error) goto exec_fail; - vn_lock(binvp, LK_EXCLUSIVE | LK_RETRY); - AUDIT_ARG_VNODE1(binvp); - imgp->vp = binvp; + vn_lock(newtextvp, LK_EXCLUSIVE | LK_RETRY); + AUDIT_ARG_VNODE1(newtextvp); + imgp->vp = newtextvp; } /* @@ -523,13 +523,13 @@ interpret: if (args->fname != NULL) NDFREE(&nd, NDF_ONLY_PNBUF); #ifdef MAC - mac_execve_interpreter_enter(binvp, &interpvplabel); + mac_execve_interpreter_enter(newtextvp, &interpvplabel); #endif if (imgp->opened) { - VOP_CLOSE(binvp, FREAD, td->td_ucred, td); + VOP_CLOSE(newtextvp, FREAD, td->td_ucred, td); imgp->opened = 0; } - vput(binvp); + vput(newtextvp); vm_object_deallocate(imgp->object); imgp->object = NULL; /* set new name to that of the interpreter */ @@ -580,13 +580,20 @@ interpret: else suword(--stack_base, imgp->args->argc); - /* - * For security and other reasons, the file descriptor table cannot - * be shared after an exec. - */ - fdunshare(td); - /* close files on exec */ - fdcloseexec(td); + if (args->fdp != NULL) { + /* Install a brand new file descriptor table. */ + fdinstall_remapped(td, args->fdp); + args->fdp = NULL; + } else { + /* + * Keep on using the existing file descriptor table. For + * security and other reasons, the file descriptor table + * cannot be shared after an exec. + */ + fdunshare(td); + /* close files on exec */ + fdcloseexec(td); + } /* * Malloc things before we need locks. @@ -600,9 +607,6 @@ interpret: vn_lock(imgp->vp, LK_SHARED | LK_RETRY); - /* Get a reference to the vnode prior to locking the proc */ - VREF(binvp); - /* * For security and other reasons, signal handlers cannot * be shared after an exec. The new process gets a copy of the old @@ -633,7 +637,7 @@ interpret: if (args->fname) bcopy(nd.ni_cnd.cn_nameptr, p->p_comm, min(nd.ni_cnd.cn_namelen, MAXCOMLEN)); - else if (vn_commname(binvp, p->p_comm, sizeof(p->p_comm)) != 0) + else if (vn_commname(newtextvp, p->p_comm, sizeof(p->p_comm)) != 0) bcopy(fexecv_proc_title, p->p_comm, sizeof(fexecv_proc_title)); bcopy(p->p_comm, td->td_name, sizeof(td->td_name)); #ifdef KTR @@ -767,11 +771,11 @@ interpret: } /* - * Store the vp for use in procfs. This vnode was referenced prior - * to locking the proc lock. + * Store the vp for use in procfs. This vnode was referenced by namei + * or fgetvp_exec. */ - textvp = p->p_textvp; - p->p_textvp = binvp; + oldtextvp = p->p_textvp; + p->p_textvp = newtextvp; #ifdef KDTRACE_HOOKS /* @@ -848,10 +852,8 @@ done1: /* * Handle deferred decrement of ref counts. */ - if (textvp != NULL) - vrele(textvp); - if (error != 0) - vrele(binvp); + if (oldtextvp != NULL) + vrele(oldtextvp); #ifdef KTRACE if (tracevp != NULL) vrele(tracevp); @@ -877,7 +879,10 @@ exec_fail_dealloc: NDFREE(&nd, NDF_ONLY_PNBUF); if (imgp->opened) VOP_CLOSE(imgp->vp, FREAD, td->td_ucred, td); - vput(imgp->vp); + if (error != 0) + vput(imgp->vp); + else + VOP_UNLOCK(imgp->vp, 0); } if (imgp->object != NULL) @@ -915,7 +920,7 @@ done2: if (error && imgp->vmspace_destroyed) { /* sorry, no more process anymore. exit gracefully */ - exit1(td, W_EXITCODE(0, SIGABRT)); + exit1(td, 0, SIGABRT); /* NOT REACHED */ } @@ -1199,6 +1204,71 @@ err_exit: return (error); } +int +exec_copyin_data_fds(struct thread *td, struct image_args *args, + const void *data, size_t datalen, const int *fds, size_t fdslen) +{ + struct filedesc *ofdp; + const char *p; + int *kfds; + int error; + + memset(args, '\0', sizeof(*args)); + ofdp = td->td_proc->p_fd; + if (datalen >= ARG_MAX || fdslen > ofdp->fd_lastfile + 1) + return (E2BIG); + error = exec_alloc_args(args); + if (error != 0) + return (error); + + args->begin_argv = args->buf; + args->stringspace = ARG_MAX; + + if (datalen > 0) { + /* + * Argument buffer has been provided. Copy it into the + * kernel as a single string and add a terminating null + * byte. + */ + error = copyin(data, args->begin_argv, datalen); + if (error != 0) + goto err_exit; + args->begin_argv[datalen] = '\0'; + args->endp = args->begin_argv + datalen + 1; + args->stringspace -= datalen + 1; + + /* + * Traditional argument counting. Count the number of + * null bytes. + */ + for (p = args->begin_argv; p < args->endp; ++p) + if (*p == '\0') + ++args->argc; + } else { + /* No argument buffer provided. */ + args->endp = args->begin_argv; + } + /* There are no environment variables. */ + args->begin_envv = args->endp; + + /* Create new file descriptor table. */ + kfds = malloc(fdslen * sizeof(int), M_TEMP, M_WAITOK); + error = copyin(fds, kfds, fdslen * sizeof(int)); + if (error != 0) { + free(kfds, M_TEMP); + goto err_exit; + } + error = fdcopy_remapped(ofdp, kfds, fdslen, &args->fdp); + free(kfds, M_TEMP); + if (error != 0) + goto err_exit; + + return (0); +err_exit: + exec_free_args(args); + return (error); +} + /* * Allocate temporary demand-paged, zero-filled memory for the file name, * argument, and environment strings. Returns zero if the allocation succeeds @@ -1225,6 +1295,8 @@ exec_free_args(struct image_args *args) free(args->fname_buf, M_TEMP); args->fname_buf = NULL; } + if (args->fdp != NULL) + fdescfree_remapped(args->fdp); } /* diff --git a/sys/kern/kern_exit.c b/sys/kern/kern_exit.c index 60691f011299..3310d1d92904 100644 --- a/sys/kern/kern_exit.c +++ b/sys/kern/kern_exit.c @@ -86,6 +86,7 @@ __FBSDID("$FreeBSD$"); #include #include #include +#include #ifdef KDTRACE_HOOKS #include @@ -174,7 +175,7 @@ void sys_sys_exit(struct thread *td, struct sys_exit_args *uap) { - exit1(td, W_EXITCODE(uap->rval, 0)); + exit1(td, uap->rval, 0); /* NOTREACHED */ } @@ -184,13 +185,14 @@ sys_sys_exit(struct thread *td, struct sys_exit_args *uap) * and rusage for wait(). Check for child processes and orphan them. */ void -exit1(struct thread *td, int rv) +exit1(struct thread *td, int rval, int signo) { struct proc *p, *nq, *q, *t; struct thread *tdt; struct vnode *ttyvp = NULL; mtx_assert(&Giant, MA_NOTOWNED); + KASSERT(rval == 0 || signo == 0, ("exit1 rv %d sig %d", rval, signo)); p = td->td_proc; /* @@ -199,8 +201,7 @@ exit1(struct thread *td, int rv) * shutdown on sparc64 when the gmirror worker process exists. */ if (p == initproc && rebooting == 0) { - printf("init died (signal %d, exit %d)\n", - WTERMSIG(rv), WEXITSTATUS(rv)); + printf("init died (signal %d, exit %d)\n", signo, rval); panic("Going nowhere without my init!"); } @@ -256,6 +257,11 @@ exit1(struct thread *td, int rv) KASSERT(p->p_numthreads == 1, ("exit1: proc %p exiting with %d threads", p, p->p_numthreads)); racct_sub(p, RACCT_NTHR, 1); + + /* Let event handler change exit status */ + p->p_xexit = rval; + p->p_xsig = signo; + /* * Wakeup anyone in procfs' PIOCWAIT. They should have a hold * on our vmspace, so we should block below until they have @@ -263,7 +269,7 @@ exit1(struct thread *td, int rv) * requested S_EXIT stops we will block here until they ack * via PIOCCONT. */ - _STOPEVENT(p, S_EXIT, rv); + _STOPEVENT(p, S_EXIT, 0); /* * Ignore any pending request to stop due to a stop signal. @@ -288,7 +294,6 @@ exit1(struct thread *td, int rv) while (p->p_lock > 0) msleep(&p->p_lock, &p->p_mtx, PWAIT, "exithold", 0); - p->p_xstat = rv; /* Let event handler change exit status */ PROC_UNLOCK(p); /* Drain the limit callout while we don't have the proc locked */ callout_drain(&p->p_limco); @@ -300,7 +305,7 @@ exit1(struct thread *td, int rv) * it was. The exit status is WEXITSTATUS(rv), but it's not clear * what the return value is. */ - AUDIT_ARG_EXIT(WEXITSTATUS(rv), 0); + AUDIT_ARG_EXIT(rval, 0); AUDIT_SYSCALL_EXIT(0, td); #endif @@ -321,7 +326,8 @@ exit1(struct thread *td, int rv) /* * Check if any loadable modules need anything done at process exit. - * E.g. SYSV IPC stuff + * E.g. SYSV IPC stuff. + * Event handler could change exit status. * XXX what if one of these generates an error? */ EVENTHANDLER_INVOKE(process_exit, p); @@ -331,7 +337,6 @@ exit1(struct thread *td, int rv) * P_PPWAIT is set; we will wakeup the parent below. */ PROC_LOCK(p); - rv = p->p_xstat; /* Event handler could change exit status */ stopprofclock(p); p->p_flag &= ~(P_TRACED | P_PPWAIT | P_PPTRACE); @@ -560,9 +565,9 @@ exit1(struct thread *td, int rv) #ifdef KDTRACE_HOOKS int reason = CLD_EXITED; - if (WCOREDUMP(rv)) + if (WCOREDUMP(signo)) reason = CLD_DUMPED; - else if (WIFSIGNALED(rv)) + else if (WIFSIGNALED(signo)) reason = CLD_KILLED; SDT_PROBE(proc, kernel, , exit, reason, 0, 0, 0, 0); #endif @@ -741,7 +746,7 @@ out: sbuf_finish(sb); log(LOG_INFO, "%s", sbuf_data(sb)); sbuf_delete(sb); - exit1(td, W_EXITCODE(0, sig)); + exit1(td, 0, sig); return (0); } @@ -840,7 +845,7 @@ proc_reap(struct thread *td, struct proc *p, int *status, int options) PROC_SUNLOCK(p); if (status) - *status = p->p_xstat; /* convert to int */ + *status = KW_EXITCODE(p->p_xexit, p->p_xsig); if (options & WNOWAIT) { /* * Only poll, returning the status. Caller does not wish to @@ -904,7 +909,7 @@ proc_reap(struct thread *td, struct proc *p, int *status, int options) * nothing can reach this process anymore. As such further locking * is unnecessary. */ - p->p_xstat = 0; /* XXX: why? */ + p->p_xexit = p->p_xsig = 0; /* XXX: why? */ PROC_LOCK(q); ruadd(&q->p_stats->p_cru, &q->p_crux, &p->p_ru, &p->p_rux); @@ -950,6 +955,11 @@ proc_reap(struct thread *td, struct proc *p, int *status, int options) #ifdef MAC mac_proc_destroy(p); #endif + /* + * Free any domain policy that's still hiding around. + */ + vm_domain_policy_cleanup(&p->p_vm_dom_policy); + KASSERT(FIRST_THREAD_IN_PROC(p), ("proc_reap: no residual thread!")); uma_zfree(proc_zone, p); @@ -1058,15 +1068,15 @@ proc_to_reap(struct thread *td, struct proc *p, idtype_t idtype, id_t id, * This is still a rough estimate. We will fix the * cases TRAPPED, STOPPED, and CONTINUED later. */ - if (WCOREDUMP(p->p_xstat)) { + if (WCOREDUMP(p->p_xsig)) { siginfo->si_code = CLD_DUMPED; - siginfo->si_status = WTERMSIG(p->p_xstat); - } else if (WIFSIGNALED(p->p_xstat)) { + siginfo->si_status = WTERMSIG(p->p_xsig); + } else if (WIFSIGNALED(p->p_xsig)) { siginfo->si_code = CLD_KILLED; - siginfo->si_status = WTERMSIG(p->p_xstat); + siginfo->si_status = WTERMSIG(p->p_xsig); } else { siginfo->si_code = CLD_EXITED; - siginfo->si_status = WEXITSTATUS(p->p_xstat); + siginfo->si_status = p->p_xexit; } siginfo->si_pid = p->p_pid; @@ -1217,9 +1227,9 @@ loop: sx_xunlock(&proctree_lock); if (status != NULL) - *status = W_STOPCODE(p->p_xstat); + *status = W_STOPCODE(p->p_xsig); if (siginfo != NULL) { - siginfo->si_status = p->p_xstat; + siginfo->si_status = p->p_xsig; siginfo->si_code = CLD_TRAPPED; } if ((options & WNOWAIT) == 0) { @@ -1230,7 +1240,7 @@ loop: CTR4(KTR_PTRACE, "wait: returning trapped pid %d status %#x (xstat %d) xthread %d", - p->p_pid, W_STOPCODE(p->p_xstat), p->p_xstat, + p->p_pid, W_STOPCODE(p->p_xsig), p->p_xsig, p->p_xthread != NULL ? p->p_xthread->td_tid : -1); PROC_UNLOCK(p); td->td_retval[0] = pid; @@ -1246,9 +1256,9 @@ loop: sx_xunlock(&proctree_lock); if (status != NULL) - *status = W_STOPCODE(p->p_xstat); + *status = W_STOPCODE(p->p_xsig); if (siginfo != NULL) { - siginfo->si_status = p->p_xstat; + siginfo->si_status = p->p_xsig; siginfo->si_code = CLD_STOPPED; } if ((options & WNOWAIT) == 0) { diff --git a/sys/kern/kern_fork.c b/sys/kern/kern_fork.c index 3fd4f09b9912..a031435455aa 100644 --- a/sys/kern/kern_fork.c +++ b/sys/kern/kern_fork.c @@ -80,6 +80,7 @@ __FBSDID("$FreeBSD$"); #include #include #include +#include #ifdef KDTRACE_HOOKS #include @@ -405,6 +406,7 @@ do_fork(struct thread *td, int flags, struct proc *p2, struct thread *td2, bcopy(&p1->p_startcopy, &p2->p_startcopy, __rangeof(struct proc, p_startcopy, p_endcopy)); pargs_hold(p2->p_args); + PROC_UNLOCK(p1); bzero(&p2->p_startzero, @@ -497,6 +499,14 @@ do_fork(struct thread *td, int flags, struct proc *p2, struct thread *td2, if (p1->p_flag & P_PROFIL) startprofclock(p2); + /* + * Whilst the proc lock is held, copy the VM domain data out + * using the VM domain method. + */ + vm_domain_policy_init(&p2->p_vm_dom_policy); + vm_domain_policy_localcopy(&p2->p_vm_dom_policy, + &p1->p_vm_dom_policy); + if (flags & RFSIGSHARE) { p2->p_sigacts = sigacts_hold(p1->p_sigacts); } else { diff --git a/sys/kern/kern_intr.c b/sys/kern/kern_intr.c index e509fbc01880..d7ff94ec2608 100644 --- a/sys/kern/kern_intr.c +++ b/sys/kern/kern_intr.c @@ -829,6 +829,12 @@ ok: * Ensure that the thread will process the handler list * again and remove this handler if it has already passed * it on the list. + * + * The release part of the following store ensures + * that the update of ih_flags is ordered before the + * it_need setting. See the comment before + * atomic_cmpset_acq(&ithd->it_need, ...) operation in + * the ithread_execute_handlers(). */ atomic_store_rel_int(&ie->ie_thread->it_need, 1); } else @@ -897,6 +903,10 @@ intr_event_schedule_thread(struct intr_event *ie) * Set it_need to tell the thread to keep running if it is already * running. Then, lock the thread and see if we actually need to * put it on the runqueue. + * + * Use store_rel to arrange that the store to ih_need in + * swi_sched() is before the store to it_need and prepare for + * transfer of this order to loads in the ithread. */ atomic_store_rel_int(&it->it_need, 1); thread_lock(td); @@ -975,6 +985,12 @@ ok: * Ensure that the thread will process the handler list * again and remove this handler if it has already passed * it on the list. + * + * The release part of the following store ensures + * that the update of ih_flags is ordered before the + * it_need setting. See the comment before + * atomic_cmpset_acq(&ithd->it_need, ...) operation in + * the ithread_execute_handlers(). */ atomic_store_rel_int(&it->it_need, 1); } else @@ -1048,6 +1064,10 @@ intr_event_schedule_thread(struct intr_event *ie, struct intr_thread *it) * Set it_need to tell the thread to keep running if it is already * running. Then, lock the thread and see if we actually need to * put it on the runqueue. + * + * Use store_rel to arrange that the store to ih_need in + * swi_sched() is before the store to it_need and prepare for + * transfer of this order to loads in the ithread. */ atomic_store_rel_int(&it->it_need, 1); thread_lock(td); @@ -1133,7 +1153,7 @@ swi_sched(void *cookie, int flags) * running it will execute this handler on the next pass. Otherwise, * it will execute it the next time it runs. */ - atomic_store_rel_int(&ih->ih_need, 1); + ih->ih_need = 1; if (!(flags & SWI_DELAY)) { PCPU_INC(cnt.v_soft); @@ -1223,13 +1243,14 @@ intr_event_execute_handlers(struct proc *p, struct intr_event *ie) * For software interrupt threads, we only execute * handlers that have their need flag set. Hardware * interrupt threads always invoke all of their handlers. + * + * ih_need can only be 0 or 1. Failed cmpset below + * means that there is no request to execute handlers, + * so a retry of the cmpset is not needed. */ - if (ie->ie_flags & IE_SOFT) { - if (atomic_load_acq_int(&ih->ih_need) == 0) - continue; - else - atomic_store_rel_int(&ih->ih_need, 0); - } + if ((ie->ie_flags & IE_SOFT) != 0 && + atomic_cmpset_int(&ih->ih_need, 1, 0) == 0) + continue; /* Execute this handler. */ CTR6(KTR_INTR, "%s: pid %d exec %p(%p) for %s flg=%x", @@ -1326,17 +1347,13 @@ ithread_loop(void *arg) * Service interrupts. If another interrupt arrives while * we are running, it will set it_need to note that we * should make another pass. + * + * The load_acq part of the following cmpset ensures + * that the load of ih_need in ithread_execute_handlers() + * is ordered after the load of it_need here. */ - while (atomic_load_acq_int(&ithd->it_need) != 0) { - /* - * This might need a full read and write barrier - * to make sure that this write posts before any - * of the memory or device accesses in the - * handlers. - */ - atomic_store_rel_int(&ithd->it_need, 0); + while (atomic_cmpset_acq_int(&ithd->it_need, 1, 0) != 0) ithread_execute_handlers(p, ie); - } WITNESS_WARN(WARN_PANIC, NULL, "suspending ithread"); mtx_assert(&Giant, MA_NOTOWNED); @@ -1346,8 +1363,8 @@ ithread_loop(void *arg) * set again, so we have to check it again. */ thread_lock(td); - if ((atomic_load_acq_int(&ithd->it_need) == 0) && - !(ithd->it_flags & (IT_DEAD | IT_WAIT))) { + if (atomic_load_acq_int(&ithd->it_need) == 0 && + (ithd->it_flags & (IT_DEAD | IT_WAIT)) == 0) { TD_SET_IWAIT(td); ie->ie_count = 0; mi_switch(SW_VOL | SWT_IWAIT, NULL); @@ -1506,15 +1523,12 @@ ithread_loop(void *arg) * Service interrupts. If another interrupt arrives while * we are running, it will set it_need to note that we * should make another pass. + * + * The load_acq part of the following cmpset ensures + * that the load of ih_need in ithread_execute_handlers() + * is ordered after the load of it_need here. */ - while (atomic_load_acq_int(&ithd->it_need) != 0) { - /* - * This might need a full read and write barrier - * to make sure that this write posts before any - * of the memory or device accesses in the - * handlers. - */ - atomic_store_rel_int(&ithd->it_need, 0); + while (atomic_cmpset_acq_int(&ithd->it_need, 1, 0) != 0) { if (priv) priv_ithread_execute_handler(p, ih); else @@ -1529,8 +1543,8 @@ ithread_loop(void *arg) * set again, so we have to check it again. */ thread_lock(td); - if ((atomic_load_acq_int(&ithd->it_need) == 0) && - !(ithd->it_flags & (IT_DEAD | IT_WAIT))) { + if (atomic_load_acq_int(&ithd->it_need) == 0 && + (ithd->it_flags & (IT_DEAD | IT_WAIT)) == 0) { TD_SET_IWAIT(td); ie->ie_count = 0; mi_switch(SW_VOL | SWT_IWAIT, NULL); diff --git a/sys/kern/kern_jail.c b/sys/kern/kern_jail.c index c118d74ed5fb..05a56324db67 100644 --- a/sys/kern/kern_jail.c +++ b/sys/kern/kern_jail.c @@ -205,6 +205,8 @@ static char *pr_allow_names[] = { "allow.mount.procfs", "allow.mount.tmpfs", "allow.mount.fdescfs", + "allow.mount.linprocfs", + "allow.mount.linsysfs", }; const size_t pr_allow_names_size = sizeof(pr_allow_names); @@ -222,6 +224,8 @@ static char *pr_allow_nonames[] = { "allow.mount.noprocfs", "allow.mount.notmpfs", "allow.mount.nofdescfs", + "allow.mount.nolinprocfs", + "allow.mount.nolinsysfs", }; const size_t pr_allow_nonames_size = sizeof(pr_allow_nonames); @@ -2432,7 +2436,7 @@ do_jail_attach(struct thread *td, struct prison *pr) goto e_unlock; #endif VOP_UNLOCK(pr->pr_root, 0); - if ((error = change_root(pr->pr_root, td))) + if ((error = pwd_chroot(td, pr->pr_root))) goto e_revert_osd; newcred = crget(); @@ -4290,6 +4294,14 @@ SYSCTL_PROC(_security_jail, OID_AUTO, mount_procfs_allowed, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, NULL, PR_ALLOW_MOUNT_PROCFS, sysctl_jail_default_allow, "I", "Processes in jail can mount the procfs file system"); +SYSCTL_PROC(_security_jail, OID_AUTO, mount_linprocfs_allowed, + CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, + NULL, PR_ALLOW_MOUNT_LINPROCFS, sysctl_jail_default_allow, "I", + "Processes in jail can mount the linprocfs file system"); +SYSCTL_PROC(_security_jail, OID_AUTO, mount_linsysfs_allowed, + CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, + NULL, PR_ALLOW_MOUNT_LINSYSFS, sysctl_jail_default_allow, "I", + "Processes in jail can mount the linsysfs file system"); SYSCTL_PROC(_security_jail, OID_AUTO, mount_tmpfs_allowed, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, NULL, PR_ALLOW_MOUNT_TMPFS, sysctl_jail_default_allow, "I", @@ -4456,6 +4468,10 @@ SYSCTL_JAIL_PARAM(_allow_mount, nullfs, CTLTYPE_INT | CTLFLAG_RW, "B", "Jail may mount the nullfs file system"); SYSCTL_JAIL_PARAM(_allow_mount, procfs, CTLTYPE_INT | CTLFLAG_RW, "B", "Jail may mount the procfs file system"); +SYSCTL_JAIL_PARAM(_allow_mount, linprocfs, CTLTYPE_INT | CTLFLAG_RW, + "B", "Jail may mount the linprocfs file system"); +SYSCTL_JAIL_PARAM(_allow_mount, linsysfs, CTLTYPE_INT | CTLFLAG_RW, + "B", "Jail may mount the linsysfs file system"); SYSCTL_JAIL_PARAM(_allow_mount, tmpfs, CTLTYPE_INT | CTLFLAG_RW, "B", "Jail may mount the tmpfs file system"); SYSCTL_JAIL_PARAM(_allow_mount, zfs, CTLTYPE_INT | CTLFLAG_RW, diff --git a/sys/kern/kern_kthread.c b/sys/kern/kern_kthread.c index d24e5cda096a..68903ba079e5 100644 --- a/sys/kern/kern_kthread.c +++ b/sys/kern/kern_kthread.c @@ -162,7 +162,7 @@ kproc_exit(int ecode) wakeup(p); /* Buh-bye! */ - exit1(td, W_EXITCODE(ecode, 0)); + exit1(td, ecode, 0); } /* diff --git a/sys/kern/kern_lockstat.c b/sys/kern/kern_lockstat.c index 1c773128da99..c5a26a333055 100644 --- a/sys/kern/kern_lockstat.c +++ b/sys/kern/kern_lockstat.c @@ -21,42 +21,61 @@ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. - * - * $FreeBSD$ */ -/* - * Backend for the lock tracing (lockstat) kernel support. This is required - * to allow a module to load even though DTrace kernel support may not be - * present. - * - */ +#include +__FBSDID("$FreeBSD$"); -#ifdef KDTRACE_HOOKS - -#include -#include +#include +#include #include +#include +#include -/* - * The following must match the type definition of dtrace_probe. It is - * defined this way to avoid having to rely on CDDL code. - */ -uint32_t lockstat_probemap[LS_NPROBES]; -void (*lockstat_probe_func)(uint32_t, uintptr_t, uintptr_t, - uintptr_t, uintptr_t, uintptr_t); +SDT_PROVIDER_DEFINE(lockstat); +SDT_PROBE_DEFINE1(lockstat, , , adaptive__acquire, "struct mtx *"); +SDT_PROBE_DEFINE1(lockstat, , , adaptive__release, "struct mtx *"); +SDT_PROBE_DEFINE2(lockstat, , , adaptive__spin, "struct mtx *", "uint64_t"); +SDT_PROBE_DEFINE2(lockstat, , , adaptive__block, "struct mtx *", "uint64_t"); + +SDT_PROBE_DEFINE1(lockstat, , , spin__acquire, "struct mtx *"); +SDT_PROBE_DEFINE1(lockstat, , , spin__release, "struct mtx *"); +SDT_PROBE_DEFINE2(lockstat, , , spin__spin, "struct mtx *", "uint64_t"); + +SDT_PROBE_DEFINE2(lockstat, , , rw__acquire, "struct rwlock *", "int"); +SDT_PROBE_DEFINE2(lockstat, , , rw__release, "struct rwlock *", "int"); +SDT_PROBE_DEFINE5(lockstat, , , rw__block, "struct rwlock *", "uint64_t", "int", + "int", "int"); +SDT_PROBE_DEFINE2(lockstat, , , rw__spin, "struct rwlock *", "uint64_t"); +SDT_PROBE_DEFINE1(lockstat, , , rw__upgrade, "struct rwlock *"); +SDT_PROBE_DEFINE1(lockstat, , , rw__downgrade, "struct rwlock *"); + +SDT_PROBE_DEFINE2(lockstat, , , sx__acquire, "struct sx *", "int"); +SDT_PROBE_DEFINE2(lockstat, , , sx__release, "struct sx *", "int"); +SDT_PROBE_DEFINE5(lockstat, , , sx__block, "struct sx *", "uint64_t", "int", + "int", "int"); +SDT_PROBE_DEFINE2(lockstat, , , sx__spin, "struct sx *", "uint64_t"); +SDT_PROBE_DEFINE1(lockstat, , , sx__upgrade, "struct sx *"); +SDT_PROBE_DEFINE1(lockstat, , , sx__downgrade, "struct sx *"); + +SDT_PROBE_DEFINE2(lockstat, , , thread__spin, "struct mtx *", "uint64_t"); + +int lockstat_enabled = 0; uint64_t -lockstat_nsecs(void) +lockstat_nsecs(struct lock_object *lo) { struct bintime bt; uint64_t ns; + if (!lockstat_enabled) + return (0); + if ((lo->lo_flags & LO_NOPROFILE) != 0) + return (0); + binuptime(&bt); ns = bt.sec * (uint64_t)1000000000; ns += ((uint64_t)1000000000 * (uint32_t)(bt.frac >> 32)) >> 32; return (ns); } - -#endif /* KDTRACE_HOOKS */ diff --git a/sys/kern/kern_mutex.c b/sys/kern/kern_mutex.c index 72fc4348ff1d..97e198584ddb 100644 --- a/sys/kern/kern_mutex.c +++ b/sys/kern/kern_mutex.c @@ -349,7 +349,7 @@ _mtx_trylock_flags_(volatile uintptr_t *c, int opts, const char *file, int line) file, line); curthread->td_locks++; if (m->mtx_recurse == 0) - LOCKSTAT_PROFILE_OBTAIN_LOCK_SUCCESS(LS_MTX_LOCK_ACQUIRE, + LOCKSTAT_PROFILE_OBTAIN_LOCK_SUCCESS(adaptive__acquire, m, contested, waittime, file, line); } @@ -416,7 +416,7 @@ __mtx_lock_sleep(volatile uintptr_t *c, uintptr_t tid, int opts, "_mtx_lock_sleep: %s contested (lock=%p) at %s:%d", m->lock_object.lo_name, (void *)m->mtx_lock, file, line); #ifdef KDTRACE_HOOKS - all_time -= lockstat_nsecs(); + all_time -= lockstat_nsecs(&m->lock_object); #endif while (!_mtx_obtain_lock(m, tid)) { @@ -513,16 +513,16 @@ __mtx_lock_sleep(volatile uintptr_t *c, uintptr_t tid, int opts, * Block on the turnstile. */ #ifdef KDTRACE_HOOKS - sleep_time -= lockstat_nsecs(); + sleep_time -= lockstat_nsecs(&m->lock_object); #endif turnstile_wait(ts, mtx_owner(m), TS_EXCLUSIVE_QUEUE); #ifdef KDTRACE_HOOKS - sleep_time += lockstat_nsecs(); + sleep_time += lockstat_nsecs(&m->lock_object); sleep_cnt++; #endif } #ifdef KDTRACE_HOOKS - all_time += lockstat_nsecs(); + all_time += lockstat_nsecs(&m->lock_object); #endif #ifdef KTR if (cont_logged) { @@ -531,17 +531,17 @@ __mtx_lock_sleep(volatile uintptr_t *c, uintptr_t tid, int opts, m->lock_object.lo_name, (void *)tid, file, line); } #endif - LOCKSTAT_PROFILE_OBTAIN_LOCK_SUCCESS(LS_MTX_LOCK_ACQUIRE, m, contested, + LOCKSTAT_PROFILE_OBTAIN_LOCK_SUCCESS(adaptive__acquire, m, contested, waittime, file, line); #ifdef KDTRACE_HOOKS if (sleep_time) - LOCKSTAT_RECORD1(LS_MTX_LOCK_BLOCK, m, sleep_time); + LOCKSTAT_RECORD1(adaptive__block, m, sleep_time); /* * Only record the loops spinning and not sleeping. */ if (spin_cnt > sleep_cnt) - LOCKSTAT_RECORD1(LS_MTX_LOCK_SPIN, m, (all_time - sleep_time)); + LOCKSTAT_RECORD1(adaptive__spin, m, all_time - sleep_time); #endif } @@ -600,7 +600,7 @@ _mtx_lock_spin_cookie(volatile uintptr_t *c, uintptr_t tid, int opts, #endif lock_profile_obtain_lock_failed(&m->lock_object, &contested, &waittime); #ifdef KDTRACE_HOOKS - spin_time -= lockstat_nsecs(); + spin_time -= lockstat_nsecs(&m->lock_object); #endif while (!_mtx_obtain_lock(m, tid)) { @@ -620,7 +620,7 @@ _mtx_lock_spin_cookie(volatile uintptr_t *c, uintptr_t tid, int opts, spinlock_enter(); } #ifdef KDTRACE_HOOKS - spin_time += lockstat_nsecs(); + spin_time += lockstat_nsecs(&m->lock_object); #endif if (LOCK_LOG_TEST(&m->lock_object, opts)) @@ -628,9 +628,12 @@ _mtx_lock_spin_cookie(volatile uintptr_t *c, uintptr_t tid, int opts, KTR_STATE0(KTR_SCHED, "thread", sched_tdname((struct thread *)tid), "running"); - LOCKSTAT_PROFILE_OBTAIN_LOCK_SUCCESS(LS_MTX_SPIN_LOCK_ACQUIRE, m, - contested, waittime, (file), (line)); - LOCKSTAT_RECORD1(LS_MTX_SPIN_LOCK_SPIN, m, spin_time); +#ifdef KDTRACE_HOOKS + LOCKSTAT_PROFILE_OBTAIN_LOCK_SUCCESS(spin__acquire, m, + contested, waittime, file, line); + if (spin_time != 0) + LOCKSTAT_RECORD1(spin__spin, m, spin_time); +#endif } #endif /* SMP */ @@ -655,7 +658,7 @@ thread_lock_flags_(struct thread *td, int opts, const char *file, int line) return; #ifdef KDTRACE_HOOKS - spin_time -= lockstat_nsecs(); + spin_time -= lockstat_nsecs(&td->td_lock->lock_object); #endif for (;;) { retry: @@ -703,15 +706,15 @@ retry: __mtx_unlock_spin(m); /* does spinlock_exit() */ } #ifdef KDTRACE_HOOKS - spin_time += lockstat_nsecs(); + spin_time += lockstat_nsecs(&m->lock_object); #endif if (m->mtx_recurse == 0) - LOCKSTAT_PROFILE_OBTAIN_LOCK_SUCCESS(LS_MTX_SPIN_LOCK_ACQUIRE, - m, contested, waittime, (file), (line)); + LOCKSTAT_PROFILE_OBTAIN_LOCK_SUCCESS(spin__acquire, m, + contested, waittime, file, line); LOCK_LOG_LOCK("LOCK", &m->lock_object, opts, m->mtx_recurse, file, line); WITNESS_LOCK(&m->lock_object, opts | LOP_EXCLUSIVE, file, line); - LOCKSTAT_RECORD1(LS_THREAD_LOCK_SPIN, m, spin_time); + LOCKSTAT_RECORD1(thread__spin, m, spin_time); } struct mtx * diff --git a/sys/kern/kern_ntptime.c b/sys/kern/kern_ntptime.c index 638cd53332aa..82062064dc8d 100644 --- a/sys/kern/kern_ntptime.c +++ b/sys/kern/kern_ntptime.c @@ -155,7 +155,7 @@ static long time_constant; /* poll interval (shift) (s) */ static long time_precision = 1; /* clock precision (ns) */ static long time_maxerror = MAXPHASE / 1000; /* maximum error (us) */ long time_esterror = MAXPHASE / 1000; /* estimated error (us) */ -static long time_reftime; /* time at last adjustment (s) */ +static long time_reftime; /* uptime at last adjustment (s) */ static l_fp time_offset; /* time offset (ns) */ static l_fp time_freq; /* frequency offset (ns/s) */ static l_fp time_adj; /* tick adjust (ns/s) */ @@ -696,12 +696,12 @@ hardupdate(offset) * otherwise, the argument offset is used to compute it. */ if (time_status & STA_PPSFREQ && time_status & STA_PPSSIGNAL) { - time_reftime = time_second; + time_reftime = time_uptime; return; } if (time_status & STA_FREQHOLD || time_reftime == 0) - time_reftime = time_second; - mtemp = time_second - time_reftime; + time_reftime = time_uptime; + mtemp = time_uptime - time_reftime; L_LINT(ftemp, time_monitor); L_RSHIFT(ftemp, (SHIFT_PLL + 2 + time_constant) << 1); L_MPY(ftemp, mtemp); @@ -714,7 +714,7 @@ hardupdate(offset) L_ADD(time_freq, ftemp); time_status |= STA_MODE; } - time_reftime = time_second; + time_reftime = time_uptime; if (L_GINT(time_freq) > MAXFREQ) L_LINT(time_freq, MAXFREQ); else if (L_GINT(time_freq) < -MAXFREQ) diff --git a/sys/kern/kern_numa.c b/sys/kern/kern_numa.c new file mode 100644 index 000000000000..e3a5837dc71a --- /dev/null +++ b/sys/kern/kern_numa.c @@ -0,0 +1,170 @@ +/*- + * Copyright (c) 2015, Adrian Chadd + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice unmodified, this list of conditions, and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +int +sys_numa_setaffinity(struct thread *td, struct numa_setaffinity_args *uap) +{ + int error; + struct vm_domain_policy vp; + struct thread *ttd; + struct proc *p; + struct cpuset *set; + + set = NULL; + p = NULL; + + /* + * Copy in just the policy information into the policy + * struct. Userland only supplies vm_domain_policy_entry. + */ + error = copyin(uap->policy, &vp.p, sizeof(vp.p)); + if (error) + goto out; + + /* + * Ensure the seq number is zero - otherwise seq.h + * may get very confused. + */ + vp.seq = 0; + + /* + * Validate policy. + */ + if (vm_domain_policy_validate(&vp) != 0) { + error = EINVAL; + goto out; + } + + /* + * Go find the desired proc/tid for this operation. + */ + error = cpuset_which(uap->which, uap->id, &p, + &ttd, &set); + if (error) + goto out; + + /* Only handle CPU_WHICH_TID and CPU_WHICH_PID */ + /* + * XXX if cpuset_which is called with WHICH_CPUSET and NULL cpuset, + * it'll return ESRCH. We should just return EINVAL. + */ + switch (uap->which) { + case CPU_WHICH_TID: + vm_domain_policy_copy(&ttd->td_vm_dom_policy, &vp); + break; + case CPU_WHICH_PID: + vm_domain_policy_copy(&p->p_vm_dom_policy, &vp); + break; + default: + error = EINVAL; + break; + } + + PROC_UNLOCK(p); +out: + if (set) + cpuset_rel(set); + return (error); +} + +int +sys_numa_getaffinity(struct thread *td, struct numa_getaffinity_args *uap) +{ + int error; + struct vm_domain_policy vp; + struct thread *ttd; + struct proc *p; + struct cpuset *set; + + set = NULL; + p = NULL; + + error = cpuset_which(uap->which, uap->id, &p, + &ttd, &set); + if (error) + goto out; + + /* Only handle CPU_WHICH_TID and CPU_WHICH_PID */ + /* + * XXX if cpuset_which is called with WHICH_CPUSET and NULL cpuset, + * it'll return ESRCH. We should just return EINVAL. + */ + switch (uap->which) { + case CPU_WHICH_TID: + vm_domain_policy_localcopy(&vp, &ttd->td_vm_dom_policy); + break; + case CPU_WHICH_PID: + vm_domain_policy_localcopy(&vp, &p->p_vm_dom_policy); + break; + default: + error = EINVAL; + break; + } + if (p) + PROC_UNLOCK(p); + /* + * Copy out only the vm_domain_policy_entry part. + */ + if (error == 0) + error = copyout(&vp.p, uap->policy, sizeof(vp.p)); +out: + if (set) + cpuset_rel(set); + return (error); +} diff --git a/sys/kern/kern_proc.c b/sys/kern/kern_proc.c index 27c6f407d5a5..3c88a59ca7a5 100644 --- a/sys/kern/kern_proc.c +++ b/sys/kern/kern_proc.c @@ -41,7 +41,9 @@ __FBSDID("$FreeBSD$"); #include #include #include +#include #include +#include #include #include #include @@ -68,9 +70,8 @@ __FBSDID("$FreeBSD$"); #include #include #include -#include #include -#include +#include #ifdef DDB #include @@ -920,7 +921,7 @@ fill_kinfo_proc_only(struct proc *p, struct kinfo_proc *kp) p->p_sysent->sv_name[0] != '\0') strlcpy(kp->ki_emul, p->p_sysent->sv_name, sizeof(kp->ki_emul)); kp->ki_siglist = p->p_siglist; - kp->ki_xstat = p->p_xstat; + kp->ki_xstat = KW_EXITCODE(p->p_xexit, p->p_xsig); kp->ki_acflag = p->p_acflag; kp->ki_lock = p->p_lock; if (p->p_pptr) { diff --git a/sys/kern/kern_prot.c b/sys/kern/kern_prot.c index b531763b8b14..d7ec70134ddf 100644 --- a/sys/kern/kern_prot.c +++ b/sys/kern/kern_prot.c @@ -1934,24 +1934,6 @@ cru2x(struct ucred *cr, struct xucred *xcr) ngroups * sizeof(*cr->cr_groups)); } -/* - * small routine to swap a thread's current ucred for the correct one taken - * from the process. - */ -void -cred_update_thread(struct thread *td) -{ - struct proc *p; - struct ucred *cred; - - p = td->td_proc; - cred = td->td_ucred; - PROC_LOCK_ASSERT(p, MA_OWNED); - td->td_ucred = crhold(p->p_ucred); - if (cred != NULL) - crfree(cred); -} - /* * Set initial process credentials. * Callers are responsible for providing the reference for provided credentials. diff --git a/sys/kern/kern_resource.c b/sys/kern/kern_resource.c index 48427637338f..b6dbab99188c 100644 --- a/sys/kern/kern_resource.c +++ b/sys/kern/kern_resource.c @@ -1436,17 +1436,3 @@ chgkqcnt(struct uidinfo *uip, int diff, rlim_t max) return (chglimit(uip, &uip->ui_kqcnt, diff, max, "kqcnt")); } - -void -lim_update_thread(struct thread *td) -{ - struct proc *p; - struct plimit *lim; - - p = td->td_proc; - lim = td->td_limit; - PROC_LOCK_ASSERT(p, MA_OWNED); - td->td_limit = lim_hold(p->p_limit); - if (lim != NULL) - lim_free(lim); -} diff --git a/sys/kern/kern_rwlock.c b/sys/kern/kern_rwlock.c index f75912b2e9b6..370d0d6fca4b 100644 --- a/sys/kern/kern_rwlock.c +++ b/sys/kern/kern_rwlock.c @@ -301,8 +301,8 @@ __rw_try_wlock(volatile uintptr_t *c, const char *file, int line) WITNESS_LOCK(&rw->lock_object, LOP_EXCLUSIVE | LOP_TRYLOCK, file, line); if (!rw_recursed(rw)) - LOCKSTAT_PROFILE_OBTAIN_LOCK_SUCCESS(LS_RW_WLOCK_ACQUIRE, - rw, 0, 0, file, line); + LOCKSTAT_PROFILE_OBTAIN_RWLOCK_SUCCESS(rw__acquire, + rw, 0, 0, file, line, LOCKSTAT_WRITER); curthread->td_locks++; } return (rval); @@ -378,13 +378,10 @@ __rw_rlock(volatile uintptr_t *c, const char *file, int line) WITNESS_CHECKORDER(&rw->lock_object, LOP_NEWORDER, file, line, NULL); #ifdef KDTRACE_HOOKS - all_time -= lockstat_nsecs(); + all_time -= lockstat_nsecs(&rw->lock_object); state = rw->rw_lock; #endif for (;;) { -#ifdef KDTRACE_HOOKS - spin_cnt++; -#endif /* * Handle the easy case. If no other thread has a write * lock, then try to bump up the count of read locks. Note @@ -413,6 +410,9 @@ __rw_rlock(volatile uintptr_t *c, const char *file, int line) } continue; } +#ifdef KDTRACE_HOOKS + spin_cnt++; +#endif #ifdef HWPMC_HOOKS PMC_SOFT_CALL( , , lock, failed); #endif @@ -532,11 +532,11 @@ __rw_rlock(volatile uintptr_t *c, const char *file, int line) CTR2(KTR_LOCK, "%s: %p blocking on turnstile", __func__, rw); #ifdef KDTRACE_HOOKS - sleep_time -= lockstat_nsecs(); + sleep_time -= lockstat_nsecs(&rw->lock_object); #endif turnstile_wait(ts, rw_owner(rw), TS_SHARED_QUEUE); #ifdef KDTRACE_HOOKS - sleep_time += lockstat_nsecs(); + sleep_time += lockstat_nsecs(&rw->lock_object); sleep_cnt++; #endif if (LOCK_LOG_TEST(&rw->lock_object, 0)) @@ -544,15 +544,15 @@ __rw_rlock(volatile uintptr_t *c, const char *file, int line) __func__, rw); } #ifdef KDTRACE_HOOKS - all_time += lockstat_nsecs(); + all_time += lockstat_nsecs(&rw->lock_object); if (sleep_time) - LOCKSTAT_RECORD4(LS_RW_RLOCK_BLOCK, rw, sleep_time, + LOCKSTAT_RECORD4(rw__block, rw, sleep_time, LOCKSTAT_READER, (state & RW_LOCK_READ) == 0, (state & RW_LOCK_READ) == 0 ? 0 : RW_READERS(state)); /* Record only the loops spinning and not sleeping. */ if (spin_cnt > sleep_cnt) - LOCKSTAT_RECORD4(LS_RW_RLOCK_SPIN, rw, all_time - sleep_time, + LOCKSTAT_RECORD4(rw__spin, rw, all_time - sleep_time, LOCKSTAT_READER, (state & RW_LOCK_READ) == 0, (state & RW_LOCK_READ) == 0 ? 0 : RW_READERS(state)); #endif @@ -561,8 +561,8 @@ __rw_rlock(volatile uintptr_t *c, const char *file, int line) * however. turnstiles don't like owners changing between calls to * turnstile_wait() currently. */ - LOCKSTAT_PROFILE_OBTAIN_LOCK_SUCCESS(LS_RW_RLOCK_ACQUIRE, rw, contested, - waittime, file, line); + LOCKSTAT_PROFILE_OBTAIN_RWLOCK_SUCCESS(rw__acquire, rw, contested, + waittime, file, line, LOCKSTAT_READER); LOCK_LOG_LOCK("RLOCK", &rw->lock_object, 0, 0, file, line); WITNESS_LOCK(&rw->lock_object, 0, file, line); curthread->td_locks++; @@ -594,8 +594,8 @@ __rw_try_rlock(volatile uintptr_t *c, const char *file, int line) LOCK_LOG_TRY("RLOCK", &rw->lock_object, 0, 1, file, line); WITNESS_LOCK(&rw->lock_object, LOP_TRYLOCK, file, line); - LOCKSTAT_PROFILE_OBTAIN_LOCK_SUCCESS(LS_RW_RLOCK_ACQUIRE, - rw, 0, 0, file, line); + LOCKSTAT_PROFILE_OBTAIN_RWLOCK_SUCCESS(rw__acquire, + rw, 0, 0, file, line, LOCKSTAT_READER); curthread->td_locks++; curthread->td_rw_rlocks++; return (1); @@ -713,7 +713,7 @@ _rw_runlock_cookie(volatile uintptr_t *c, const char *file, int line) turnstile_chain_unlock(&rw->lock_object); break; } - LOCKSTAT_PROFILE_RELEASE_LOCK(LS_RW_RUNLOCK_RELEASE, rw); + LOCKSTAT_PROFILE_RELEASE_RWLOCK(rw__release, rw, LOCKSTAT_READER); curthread->td_locks--; curthread->td_rw_rlocks--; } @@ -767,7 +767,7 @@ __rw_wlock_hard(volatile uintptr_t *c, uintptr_t tid, const char *file, rw->lock_object.lo_name, (void *)rw->rw_lock, file, line); #ifdef KDTRACE_HOOKS - all_time -= lockstat_nsecs(); + all_time -= lockstat_nsecs(&rw->lock_object); state = rw->rw_lock; #endif while (!_rw_write_lock(rw, tid)) { @@ -893,11 +893,11 @@ __rw_wlock_hard(volatile uintptr_t *c, uintptr_t tid, const char *file, CTR2(KTR_LOCK, "%s: %p blocking on turnstile", __func__, rw); #ifdef KDTRACE_HOOKS - sleep_time -= lockstat_nsecs(); + sleep_time -= lockstat_nsecs(&rw->lock_object); #endif turnstile_wait(ts, rw_owner(rw), TS_EXCLUSIVE_QUEUE); #ifdef KDTRACE_HOOKS - sleep_time += lockstat_nsecs(); + sleep_time += lockstat_nsecs(&rw->lock_object); sleep_cnt++; #endif if (LOCK_LOG_TEST(&rw->lock_object, 0)) @@ -908,20 +908,20 @@ __rw_wlock_hard(volatile uintptr_t *c, uintptr_t tid, const char *file, #endif } #ifdef KDTRACE_HOOKS - all_time += lockstat_nsecs(); + all_time += lockstat_nsecs(&rw->lock_object); if (sleep_time) - LOCKSTAT_RECORD4(LS_RW_WLOCK_BLOCK, rw, sleep_time, + LOCKSTAT_RECORD4(rw__block, rw, sleep_time, LOCKSTAT_WRITER, (state & RW_LOCK_READ) == 0, (state & RW_LOCK_READ) == 0 ? 0 : RW_READERS(state)); /* Record only the loops spinning and not sleeping. */ if (spin_cnt > sleep_cnt) - LOCKSTAT_RECORD4(LS_RW_WLOCK_SPIN, rw, all_time - sleep_time, + LOCKSTAT_RECORD4(rw__spin, rw, all_time - sleep_time, LOCKSTAT_READER, (state & RW_LOCK_READ) == 0, (state & RW_LOCK_READ) == 0 ? 0 : RW_READERS(state)); #endif - LOCKSTAT_PROFILE_OBTAIN_LOCK_SUCCESS(LS_RW_WLOCK_ACQUIRE, rw, contested, - waittime, file, line); + LOCKSTAT_PROFILE_OBTAIN_RWLOCK_SUCCESS(rw__acquire, rw, contested, + waittime, file, line, LOCKSTAT_WRITER); } /* @@ -1066,7 +1066,7 @@ __rw_try_upgrade(volatile uintptr_t *c, const char *file, int line) curthread->td_rw_rlocks--; WITNESS_UPGRADE(&rw->lock_object, LOP_EXCLUSIVE | LOP_TRYLOCK, file, line); - LOCKSTAT_RECORD0(LS_RW_TRYUPGRADE_UPGRADE, rw); + LOCKSTAT_RECORD0(rw__upgrade, rw); } return (success); } @@ -1138,7 +1138,7 @@ __rw_downgrade(volatile uintptr_t *c, const char *file, int line) out: curthread->td_rw_rlocks++; LOCK_LOG_LOCK("WDOWNGRADE", &rw->lock_object, 0, 0, file, line); - LOCKSTAT_RECORD0(LS_RW_DOWNGRADE_DOWNGRADE, rw); + LOCKSTAT_RECORD0(rw__downgrade, rw); } #ifdef INVARIANT_SUPPORT diff --git a/sys/kern/kern_sig.c b/sys/kern/kern_sig.c index b70da5bd98a2..e39290dd43c9 100644 --- a/sys/kern/kern_sig.c +++ b/sys/kern/kern_sig.c @@ -628,7 +628,7 @@ sig_ffs(sigset_t *set) } static bool -sigact_flag_test(struct sigaction *act, int flag) +sigact_flag_test(const struct sigaction *act, int flag) { /* @@ -648,11 +648,8 @@ sigact_flag_test(struct sigaction *act, int flag) * osigaction */ int -kern_sigaction(td, sig, act, oact, flags) - struct thread *td; - register int sig; - struct sigaction *act, *oact; - int flags; +kern_sigaction(struct thread *td, int sig, const struct sigaction *act, + struct sigaction *oact, int flags) { struct sigacts *ps; struct proc *p = td->td_proc; @@ -2230,7 +2227,7 @@ tdsendsignal(struct proc *p, struct thread *td, int sig, ksiginfo_t *ksi) if (p->p_numthreads == p->p_suspcount) { PROC_SUNLOCK(p); p->p_flag |= P_CONTINUED; - p->p_xstat = SIGCONT; + p->p_xsig = SIGCONT; PROC_LOCK(p->p_pptr); childproc_continued(p); PROC_UNLOCK(p->p_pptr); @@ -2309,7 +2306,7 @@ tdsendsignal(struct proc *p, struct thread *td, int sig, ksiginfo_t *ksi) if (p->p_flag & (P_PPWAIT|P_WEXIT)) goto out; p->p_flag |= P_STOPPED_SIG; - p->p_xstat = sig; + p->p_xsig = sig; PROC_SLOCK(p); sig_suspend_threads(td, p, 1); if (p->p_numthreads == p->p_suspcount) { @@ -2322,7 +2319,7 @@ tdsendsignal(struct proc *p, struct thread *td, int sig, ksiginfo_t *ksi) */ thread_stopped(p); PROC_SUNLOCK(p); - sigqueue_delete_proc(p, p->p_xstat); + sigqueue_delete_proc(p, p->p_xsig); } else PROC_SUNLOCK(p); goto out; @@ -2494,7 +2491,7 @@ ptracestop(struct thread *td, int sig) * Just make wait() to work, the last stopped thread * will win. */ - p->p_xstat = sig; + p->p_xsig = sig; p->p_xthread = td; p->p_flag |= (P_STOPPED_SIG|P_STOPPED_TRACE); sig_suspend_threads(td, p, 0); @@ -2687,7 +2684,7 @@ issignal(struct thread *td) /* * If parent wants us to take the signal, - * then it will leave it in p->p_xstat; + * then it will leave it in p->p_xsig; * otherwise we just look for signals again. */ if (newsig == 0) @@ -2764,7 +2761,7 @@ issignal(struct thread *td) WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, &p->p_mtx.lock_object, "Catching SIGSTOP"); p->p_flag |= P_STOPPED_SIG; - p->p_xstat = sig; + p->p_xsig = sig; PROC_SLOCK(p); sig_suspend_threads(td, p, 0); thread_suspend_switch(td, p); @@ -2968,7 +2965,7 @@ sigexit(td, sig) sig & WCOREFLAG ? " (core dumped)" : ""); } else PROC_UNLOCK(p); - exit1(td, W_EXITCODE(0, sig)); + exit1(td, 0, sig); /* NOTREACHED */ } @@ -3023,8 +3020,8 @@ childproc_jobstate(struct proc *p, int reason, int sig) void childproc_stopped(struct proc *p, int reason) { - /* p_xstat is a plain signal number, not a full wait() status here. */ - childproc_jobstate(p, reason, p->p_xstat); + + childproc_jobstate(p, reason, p->p_xsig); } void @@ -3036,16 +3033,18 @@ childproc_continued(struct proc *p) void childproc_exited(struct proc *p) { - int reason; - int xstat = p->p_xstat; /* convert to int */ - int status; + int reason, status; - if (WCOREDUMP(xstat)) - reason = CLD_DUMPED, status = WTERMSIG(xstat); - else if (WIFSIGNALED(xstat)) - reason = CLD_KILLED, status = WTERMSIG(xstat); - else - reason = CLD_EXITED, status = WEXITSTATUS(xstat); + if (WCOREDUMP(p->p_xsig)) { + reason = CLD_DUMPED; + status = WTERMSIG(p->p_xsig); + } else if (WIFSIGNALED(p->p_xsig)) { + reason = CLD_KILLED; + status = WTERMSIG(p->p_xsig); + } else { + reason = CLD_EXITED; + status = p->p_xexit; + } /* * XXX avoid calling wakeup(p->p_pptr), the work is * done in exit1(). diff --git a/sys/kern/kern_sx.c b/sys/kern/kern_sx.c index 91e8c60f899d..1ba1ab2aff53 100644 --- a/sys/kern/kern_sx.c +++ b/sys/kern/kern_sx.c @@ -288,8 +288,8 @@ sx_try_slock_(struct sx *sx, const char *file, int line) if (atomic_cmpset_acq_ptr(&sx->sx_lock, x, x + SX_ONE_SHARER)) { LOCK_LOG_TRY("SLOCK", &sx->lock_object, 0, 1, file, line); WITNESS_LOCK(&sx->lock_object, LOP_TRYLOCK, file, line); - LOCKSTAT_PROFILE_OBTAIN_LOCK_SUCCESS(LS_SX_SLOCK_ACQUIRE, - sx, 0, 0, file, line); + LOCKSTAT_PROFILE_OBTAIN_RWLOCK_SUCCESS(sx__acquire, + sx, 0, 0, file, line, LOCKSTAT_READER); curthread->td_locks++; return (1); } @@ -351,8 +351,8 @@ sx_try_xlock_(struct sx *sx, const char *file, int line) WITNESS_LOCK(&sx->lock_object, LOP_EXCLUSIVE | LOP_TRYLOCK, file, line); if (!sx_recursed(sx)) - LOCKSTAT_PROFILE_OBTAIN_LOCK_SUCCESS(LS_SX_XLOCK_ACQUIRE, - sx, 0, 0, file, line); + LOCKSTAT_PROFILE_OBTAIN_RWLOCK_SUCCESS(sx__acquire, + sx, 0, 0, file, line, LOCKSTAT_WRITER); curthread->td_locks++; } @@ -420,7 +420,7 @@ sx_try_upgrade_(struct sx *sx, const char *file, int line) if (success) { WITNESS_UPGRADE(&sx->lock_object, LOP_EXCLUSIVE | LOP_TRYLOCK, file, line); - LOCKSTAT_RECORD0(LS_SX_TRYUPGRADE_UPGRADE, sx); + LOCKSTAT_RECORD0(sx__upgrade, sx); } return (success); } @@ -486,7 +486,7 @@ sx_downgrade_(struct sx *sx, const char *file, int line) sleepq_release(&sx->lock_object); LOCK_LOG_LOCK("XDOWNGRADE", &sx->lock_object, 0, 0, file, line); - LOCKSTAT_RECORD0(LS_SX_DOWNGRADE_DOWNGRADE, sx); + LOCKSTAT_RECORD0(sx__downgrade, sx); if (wakeup_swapper) kick_proc0(); @@ -541,7 +541,7 @@ _sx_xlock_hard(struct sx *sx, uintptr_t tid, int opts, const char *file, sx->lock_object.lo_name, (void *)sx->sx_lock, file, line); #ifdef KDTRACE_HOOKS - all_time -= lockstat_nsecs(); + all_time -= lockstat_nsecs(&sx->lock_object); state = sx->sx_lock; #endif while (!atomic_cmpset_acq_ptr(&sx->sx_lock, SX_LOCK_UNLOCKED, tid)) { @@ -691,7 +691,7 @@ _sx_xlock_hard(struct sx *sx, uintptr_t tid, int opts, const char *file, __func__, sx); #ifdef KDTRACE_HOOKS - sleep_time -= lockstat_nsecs(); + sleep_time -= lockstat_nsecs(&sx->lock_object); #endif GIANT_SAVE(); sleepq_add(&sx->lock_object, NULL, sx->lock_object.lo_name, @@ -702,7 +702,7 @@ _sx_xlock_hard(struct sx *sx, uintptr_t tid, int opts, const char *file, else error = sleepq_wait_sig(&sx->lock_object, 0); #ifdef KDTRACE_HOOKS - sleep_time += lockstat_nsecs(); + sleep_time += lockstat_nsecs(&sx->lock_object); sleep_cnt++; #endif if (error) { @@ -717,19 +717,19 @@ _sx_xlock_hard(struct sx *sx, uintptr_t tid, int opts, const char *file, __func__, sx); } #ifdef KDTRACE_HOOKS - all_time += lockstat_nsecs(); + all_time += lockstat_nsecs(&sx->lock_object); if (sleep_time) - LOCKSTAT_RECORD4(LS_SX_XLOCK_BLOCK, sx, sleep_time, + LOCKSTAT_RECORD4(sx__block, sx, sleep_time, LOCKSTAT_WRITER, (state & SX_LOCK_SHARED) == 0, (state & SX_LOCK_SHARED) == 0 ? 0 : SX_SHARERS(state)); if (spin_cnt > sleep_cnt) - LOCKSTAT_RECORD4(LS_SX_XLOCK_SPIN, sx, all_time - sleep_time, + LOCKSTAT_RECORD4(sx__spin, sx, all_time - sleep_time, LOCKSTAT_WRITER, (state & SX_LOCK_SHARED) == 0, (state & SX_LOCK_SHARED) == 0 ? 0 : SX_SHARERS(state)); #endif if (!error) - LOCKSTAT_PROFILE_OBTAIN_LOCK_SUCCESS(LS_SX_XLOCK_ACQUIRE, sx, - contested, waittime, file, line); + LOCKSTAT_PROFILE_OBTAIN_RWLOCK_SUCCESS(sx__acquire, sx, + contested, waittime, file, line, LOCKSTAT_WRITER); GIANT_RESTORE(); return (error); } @@ -828,7 +828,7 @@ _sx_slock_hard(struct sx *sx, int opts, const char *file, int line) #ifdef KDTRACE_HOOKS state = sx->sx_lock; - all_time -= lockstat_nsecs(); + all_time -= lockstat_nsecs(&sx->lock_object); #endif /* @@ -955,7 +955,7 @@ _sx_slock_hard(struct sx *sx, int opts, const char *file, int line) __func__, sx); #ifdef KDTRACE_HOOKS - sleep_time -= lockstat_nsecs(); + sleep_time -= lockstat_nsecs(&sx->lock_object); #endif GIANT_SAVE(); sleepq_add(&sx->lock_object, NULL, sx->lock_object.lo_name, @@ -966,7 +966,7 @@ _sx_slock_hard(struct sx *sx, int opts, const char *file, int line) else error = sleepq_wait_sig(&sx->lock_object, 0); #ifdef KDTRACE_HOOKS - sleep_time += lockstat_nsecs(); + sleep_time += lockstat_nsecs(&sx->lock_object); sleep_cnt++; #endif if (error) { @@ -981,19 +981,19 @@ _sx_slock_hard(struct sx *sx, int opts, const char *file, int line) __func__, sx); } #ifdef KDTRACE_HOOKS - all_time += lockstat_nsecs(); + all_time += lockstat_nsecs(&sx->lock_object); if (sleep_time) - LOCKSTAT_RECORD4(LS_SX_SLOCK_BLOCK, sx, sleep_time, + LOCKSTAT_RECORD4(sx__block, sx, sleep_time, LOCKSTAT_READER, (state & SX_LOCK_SHARED) == 0, (state & SX_LOCK_SHARED) == 0 ? 0 : SX_SHARERS(state)); if (spin_cnt > sleep_cnt) - LOCKSTAT_RECORD4(LS_SX_SLOCK_SPIN, sx, all_time - sleep_time, + LOCKSTAT_RECORD4(sx__spin, sx, all_time - sleep_time, LOCKSTAT_READER, (state & SX_LOCK_SHARED) == 0, (state & SX_LOCK_SHARED) == 0 ? 0 : SX_SHARERS(state)); #endif if (error == 0) - LOCKSTAT_PROFILE_OBTAIN_LOCK_SUCCESS(LS_SX_SLOCK_ACQUIRE, sx, - contested, waittime, file, line); + LOCKSTAT_PROFILE_OBTAIN_RWLOCK_SUCCESS(sx__acquire, sx, + contested, waittime, file, line, LOCKSTAT_READER); GIANT_RESTORE(); return (error); } diff --git a/sys/kern/kern_thr.c b/sys/kern/kern_thr.c index e6b0a59fcc7a..9e878d8dd7cb 100644 --- a/sys/kern/kern_thr.c +++ b/sys/kern/kern_thr.c @@ -54,6 +54,8 @@ __FBSDID("$FreeBSD$"); #include #include +#include + #include #include @@ -87,29 +89,39 @@ suword_lwpid(void *addr, lwpid_t lwpid) #define suword_lwpid suword #endif -static int create_thread(struct thread *td, mcontext_t *ctx, - void (*start_func)(void *), void *arg, - char *stack_base, size_t stack_size, - char *tls_base, - long *child_tid, long *parent_tid, - int flags, struct rtprio *rtp); - /* * System call interface. */ + +struct thr_create_initthr_args { + ucontext_t ctx; + long *tid; +}; + +static int +thr_create_initthr(struct thread *td, void *thunk) +{ + struct thr_create_initthr_args *args; + + /* Copy out the child tid. */ + args = thunk; + if (args->tid != NULL && suword_lwpid(args->tid, td->td_tid)) + return (EFAULT); + + return (set_mcontext(td, &args->ctx.uc_mcontext)); +} + int sys_thr_create(struct thread *td, struct thr_create_args *uap) /* ucontext_t *ctx, long *id, int flags */ { - ucontext_t ctx; + struct thr_create_initthr_args args; int error; - if ((error = copyin(uap->ctx, &ctx, sizeof(ctx)))) + if ((error = copyin(uap->ctx, &args.ctx, sizeof(args.ctx)))) return (error); - - error = create_thread(td, &ctx.uc_mcontext, NULL, NULL, - NULL, 0, NULL, uap->id, NULL, uap->flags, NULL); - return (error); + args.tid = uap->id; + return (thread_create(td, NULL, thr_create_initthr, &args)); } int @@ -127,6 +139,35 @@ sys_thr_new(struct thread *td, struct thr_new_args *uap) return (kern_thr_new(td, ¶m)); } +static int +thr_new_initthr(struct thread *td, void *thunk) +{ + stack_t stack; + struct thr_param *param; + + /* + * Here we copy out tid to two places, one for child and one + * for parent, because pthread can create a detached thread, + * if parent wants to safely access child tid, it has to provide + * its storage, because child thread may exit quickly and + * memory is freed before parent thread can access it. + */ + param = thunk; + if ((param->child_tid != NULL && + suword_lwpid(param->child_tid, td->td_tid)) || + (param->parent_tid != NULL && + suword_lwpid(param->parent_tid, td->td_tid))) + return (EFAULT); + + /* Set up our machine context. */ + stack.ss_sp = param->stack_base; + stack.ss_size = param->stack_size; + /* Set upcall address to user thread entry function. */ + cpu_set_upcall_kse(td, param->start_func, param->arg, &stack); + /* Setup user TLS address and TLS pointer register. */ + return (cpu_set_user_tls(td, param->tls_base)); +} + int kern_thr_new(struct thread *td, struct thr_param *param) { @@ -140,22 +181,13 @@ kern_thr_new(struct thread *td, struct thr_param *param) return (error); rtpp = &rtp; } - error = create_thread(td, NULL, param->start_func, param->arg, - param->stack_base, param->stack_size, param->tls_base, - param->child_tid, param->parent_tid, param->flags, - rtpp); - return (error); + return (thread_create(td, rtpp, thr_new_initthr, param)); } -static int -create_thread(struct thread *td, mcontext_t *ctx, - void (*start_func)(void *), void *arg, - char *stack_base, size_t stack_size, - char *tls_base, - long *child_tid, long *parent_tid, - int flags, struct rtprio *rtp) +int +thread_create(struct thread *td, struct rtprio *rtp, + int (*initialize_thread)(struct thread *, void *), void *thunk) { - stack_t stack; struct thread *newtd; struct proc *p; int error; @@ -197,24 +229,6 @@ create_thread(struct thread *td, mcontext_t *ctx, cpu_set_upcall(newtd, td); - /* - * Try the copyout as soon as we allocate the td so we don't - * have to tear things down in a failure case below. - * Here we copy out tid to two places, one for child and one - * for parent, because pthread can create a detached thread, - * if parent wants to safely access child tid, it has to provide - * its storage, because child thread may exit quickly and - * memory is freed before parent thread can access it. - */ - if ((child_tid != NULL && - suword_lwpid(child_tid, newtd->td_tid)) || - (parent_tid != NULL && - suword_lwpid(parent_tid, newtd->td_tid))) { - thread_free(newtd); - error = EFAULT; - goto fail; - } - bzero(&newtd->td_startzero, __rangeof(struct thread, td_startzero, td_endzero)); bcopy(&td->td_startcopy, &newtd->td_startcopy, @@ -222,26 +236,11 @@ create_thread(struct thread *td, mcontext_t *ctx, newtd->td_proc = td->td_proc; thread_cow_get(newtd, td); - if (ctx != NULL) { /* old way to set user context */ - error = set_mcontext(newtd, ctx); - if (error != 0) { - thread_cow_free(newtd); - thread_free(newtd); - goto fail; - } - } else { - /* Set up our machine context. */ - stack.ss_sp = stack_base; - stack.ss_size = stack_size; - /* Set upcall address to user thread entry function. */ - cpu_set_upcall_kse(newtd, start_func, arg, &stack); - /* Setup user TLS address and TLS pointer register. */ - error = cpu_set_user_tls(newtd, tls_base); - if (error != 0) { - thread_cow_free(newtd); - thread_free(newtd); - goto fail; - } + error = initialize_thread(newtd, thunk); + if (error != 0) { + thread_cow_free(newtd); + thread_free(newtd); + goto fail; } PROC_LOCK(p); @@ -254,6 +253,13 @@ create_thread(struct thread *td, mcontext_t *ctx, thread_unlock(td); if (P_SHOULDSTOP(p)) newtd->td_flags |= TDF_ASTPENDING | TDF_NEEDSUSPCHK; + + /* + * Copy the existing thread VM policy into the new thread. + */ + vm_domain_policy_localcopy(&newtd->td_vm_dom_policy, + &td->td_vm_dom_policy); + PROC_UNLOCK(p); tidhash_add(newtd); diff --git a/sys/kern/kern_thread.c b/sys/kern/kern_thread.c index 4343b643c867..3c6232cc1e21 100644 --- a/sys/kern/kern_thread.c +++ b/sys/kern/kern_thread.c @@ -60,6 +60,7 @@ __FBSDID("$FreeBSD$"); #include #include #include +#include #include SDT_PROVIDER_DECLARE(proc); @@ -351,6 +352,7 @@ thread_alloc(int pages) return (NULL); } cpu_thread_alloc(td); + vm_domain_policy_init(&td->td_vm_dom_policy); return (td); } @@ -380,6 +382,7 @@ thread_free(struct thread *td) cpu_thread_free(td); if (td->td_kstack != 0) vm_thread_dispose(td); + vm_domain_policy_cleanup(&td->td_vm_dom_policy); uma_zfree(thread_zone, td); } @@ -406,9 +409,9 @@ void thread_cow_free(struct thread *td) { - if (td->td_ucred) + if (td->td_ucred != NULL) crfree(td->td_ucred); - if (td->td_limit) + if (td->td_limit != NULL) lim_free(td->td_limit); } @@ -416,15 +419,27 @@ void thread_cow_update(struct thread *td) { struct proc *p; + struct ucred *oldcred; + struct plimit *oldlimit; p = td->td_proc; + oldcred = NULL; + oldlimit = NULL; PROC_LOCK(p); - if (td->td_ucred != p->p_ucred) - cred_update_thread(td); - if (td->td_limit != p->p_limit) - lim_update_thread(td); + if (td->td_ucred != p->p_ucred) { + oldcred = td->td_ucred; + td->td_ucred = crhold(p->p_ucred); + } + if (td->td_limit != p->p_limit) { + oldlimit = td->td_limit; + td->td_limit = lim_hold(p->p_limit); + } td->td_cowgen = p->p_cowgen; PROC_UNLOCK(p); + if (oldcred != NULL) + crfree(oldcred); + if (oldlimit != NULL) + lim_free(oldlimit); } /* diff --git a/sys/kern/sched_ule.c b/sys/kern/sched_ule.c index 47278527c2c4..74ae85f5efcf 100644 --- a/sys/kern/sched_ule.c +++ b/sys/kern/sched_ule.c @@ -1057,7 +1057,7 @@ tdq_notify(struct tdq *tdq, struct thread *td) * globally visible before we read tdq_cpu_idle. Idle thread * accesses both of them without locks, and the order is important. */ - mb(); + atomic_thread_fence_seq_cst(); if (TD_IS_IDLETHREAD(ctd)) { /* @@ -2667,7 +2667,7 @@ sched_idletd(void *dummy) * before cpu_idle() read tdq_load. The order is important * to avoid race with tdq_notify. */ - mb(); + atomic_thread_fence_seq_cst(); cpu_idle(switchcnt * 4 > sched_idlespinthresh); tdq->tdq_cpu_idle = 0; diff --git a/sys/kern/subr_firmware.c b/sys/kern/subr_firmware.c index 20ab76e282be..172d7198dc66 100644 --- a/sys/kern/subr_firmware.c +++ b/sys/kern/subr_firmware.c @@ -383,19 +383,8 @@ firmware_put(const struct firmware *p, int flags) static void set_rootvnode(void *arg, int npending) { - struct thread *td = curthread; - struct proc *p = td->td_proc; - FILEDESC_XLOCK(p->p_fd); - if (p->p_fd->fd_cdir == NULL) { - p->p_fd->fd_cdir = rootvnode; - VREF(rootvnode); - } - if (p->p_fd->fd_rdir == NULL) { - p->p_fd->fd_rdir = rootvnode; - VREF(rootvnode); - } - FILEDESC_XUNLOCK(p->p_fd); + pwd_ensure_dirs(); free(arg, M_TEMP); } diff --git a/sys/kern/subr_smp.c b/sys/kern/subr_smp.c index 90bbc5fd22a1..0ac3b17aa148 100644 --- a/sys/kern/subr_smp.c +++ b/sys/kern/subr_smp.c @@ -455,8 +455,13 @@ smp_rendezvous_action(void) * This means that no member of smp_rv_* pseudo-structure will be * accessed by this target CPU after this point; in particular, * memory pointed by smp_rv_func_arg. + * + * The release semantic ensures that all accesses performed by + * the current CPU are visible when smp_rendezvous_cpus() + * returns, by synchronizing with the + * atomic_load_acq_int(&smp_rv_waiters[3]). */ - atomic_add_int(&smp_rv_waiters[3], 1); + atomic_add_rel_int(&smp_rv_waiters[3], 1); td->td_critnest--; KASSERT(owepreempt == td->td_owepreempt, @@ -522,6 +527,11 @@ smp_rendezvous_cpus(cpuset_t map, * CPUs to finish the rendezvous, so that smp_rv_* * pseudo-structure and the arg are guaranteed to not * be in use. + * + * Load acquire synchronizes with the release add in + * smp_rendezvous_action(), which ensures that our caller sees + * all memory actions done by the called functions on other + * CPUs. */ while (atomic_load_acq_int(&smp_rv_waiters[3]) < ncpus) cpu_spinwait(); diff --git a/sys/kern/subr_trap.c b/sys/kern/subr_trap.c index 375bb321485d..a3714563ccac 100644 --- a/sys/kern/subr_trap.c +++ b/sys/kern/subr_trap.c @@ -172,7 +172,7 @@ userret(struct thread *td, struct trapframe *frame) (td->td_vnet_lpush != NULL) ? td->td_vnet_lpush : "N/A")); #endif #ifdef RACCT - if (racct_enable) { + if (racct_enable && p->p_throttled == 1) { PROC_LOCK(p); while (p->p_throttled == 1) msleep(p->p_racct, &p->p_mtx, 0, "racct", 0); diff --git a/sys/kern/sys_pipe.c b/sys/kern/sys_pipe.c index 06a4d5acc4f4..70e76ad39952 100644 --- a/sys/kern/sys_pipe.c +++ b/sys/kern/sys_pipe.c @@ -946,9 +946,10 @@ pipe_direct_write(wpipe, uio) retry: PIPE_LOCK_ASSERT(wpipe, MA_OWNED); error = pipelock(wpipe, 1); - if (wpipe->pipe_state & PIPE_EOF) + if (error != 0) + goto error1; + if ((wpipe->pipe_state & PIPE_EOF) != 0) { error = EPIPE; - if (error) { pipeunlock(wpipe); goto error1; } diff --git a/sys/kern/sys_procdesc.c b/sys/kern/sys_procdesc.c index 948595f8751e..0d3b1f4334bd 100644 --- a/sys/kern/sys_procdesc.c +++ b/sys/kern/sys_procdesc.c @@ -295,7 +295,7 @@ procdesc_exit(struct proc *p) ("procdesc_exit: closed && parent not init")); pd->pd_flags |= PDF_EXITED; - pd->pd_xstat = p->p_xstat; + pd->pd_xstat = KW_EXITCODE(p->p_xexit, p->p_xsig); /* * If the process descriptor has been closed, then we have nothing diff --git a/sys/kern/sys_process.c b/sys/kern/sys_process.c index d82fda030cb8..cb88034b06fa 100644 --- a/sys/kern/sys_process.c +++ b/sys/kern/sys_process.c @@ -41,6 +41,7 @@ __FBSDID("$FreeBSD$"); #include #include #include +#include #include #include #include @@ -975,7 +976,7 @@ kern_ptrace(struct thread *td, int req, pid_t pid, void *addr, int data) sx_xunlock(&proctree_lock); proctree_locked = 0; } - p->p_xstat = data; + p->p_xsig = data; p->p_xthread = NULL; if ((p->p_flag & (P_STOPPED_SIG | P_STOPPED_TRACE)) != 0) { /* deliver or queue signal */ @@ -1300,7 +1301,8 @@ stopevent(struct proc *p, unsigned int event, unsigned int val) CTR3(KTR_PTRACE, "stopevent: pid %d event %u val %u", p->p_pid, event, val); do { - p->p_xstat = val; + if (event != S_EXIT) + p->p_xsig = val; p->p_xthread = NULL; p->p_stype = event; /* Which event caused the stop? */ wakeup(&p->p_stype); /* Wake up any PIOCWAIT'ing procs */ diff --git a/sys/kern/syscalls.c b/sys/kern/syscalls.c index a404c5135a81..3c563c9f3c3b 100644 --- a/sys/kern/syscalls.c +++ b/sys/kern/syscalls.c @@ -555,4 +555,6 @@ const char *syscallnames[] = { "ppoll", /* 545 = ppoll */ "futimens", /* 546 = futimens */ "utimensat", /* 547 = utimensat */ + "numa_getaffinity", /* 548 = numa_getaffinity */ + "numa_setaffinity", /* 549 = numa_setaffinity */ }; diff --git a/sys/kern/syscalls.master b/sys/kern/syscalls.master index 9873868fbbf6..6e6fb387db88 100644 --- a/sys/kern/syscalls.master +++ b/sys/kern/syscalls.master @@ -988,5 +988,12 @@ 547 AUE_FUTIMESAT STD { int utimensat(int fd, \ char *path, \ struct timespec *times, int flag); } +548 AUE_NULL STD { int numa_getaffinity(cpuwhich_t which, \ + id_t id, \ + struct vm_domain_policy_entry *policy); } +549 AUE_NULL STD { int numa_setaffinity(cpuwhich_t which, \ + id_t id, \ + const struct vm_domain_policy_entry *policy); } + ; Please copy any additions and changes to the following compatability tables: ; sys/compat/freebsd32/syscalls.master diff --git a/sys/kern/systrace_args.c b/sys/kern/systrace_args.c index a06d7dc8ebe0..00a050f6929a 100644 --- a/sys/kern/systrace_args.c +++ b/sys/kern/systrace_args.c @@ -3337,6 +3337,24 @@ systrace_args(int sysnum, void *params, uint64_t *uarg, int *n_args) *n_args = 4; break; } + /* numa_getaffinity */ + case 548: { + struct numa_getaffinity_args *p = params; + iarg[0] = p->which; /* cpuwhich_t */ + iarg[1] = p->id; /* id_t */ + uarg[2] = (intptr_t) p->policy; /* struct vm_domain_policy_entry * */ + *n_args = 3; + break; + } + /* numa_setaffinity */ + case 549: { + struct numa_setaffinity_args *p = params; + iarg[0] = p->which; /* cpuwhich_t */ + iarg[1] = p->id; /* id_t */ + uarg[2] = (intptr_t) p->policy; /* const struct vm_domain_policy_entry * */ + *n_args = 3; + break; + } default: *n_args = 0; break; @@ -8883,6 +8901,38 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz) break; }; break; + /* numa_getaffinity */ + case 548: + switch(ndx) { + case 0: + p = "cpuwhich_t"; + break; + case 1: + p = "id_t"; + break; + case 2: + p = "struct vm_domain_policy_entry *"; + break; + default: + break; + }; + break; + /* numa_setaffinity */ + case 549: + switch(ndx) { + case 0: + p = "cpuwhich_t"; + break; + case 1: + p = "id_t"; + break; + case 2: + p = "const struct vm_domain_policy_entry *"; + break; + default: + break; + }; + break; default: break; }; @@ -10806,6 +10856,16 @@ systrace_return_setargdesc(int sysnum, int ndx, char *desc, size_t descsz) if (ndx == 0 || ndx == 1) p = "int"; break; + /* numa_getaffinity */ + case 548: + if (ndx == 0 || ndx == 1) + p = "int"; + break; + /* numa_setaffinity */ + case 549: + if (ndx == 0 || ndx == 1) + p = "int"; + break; default: break; }; diff --git a/sys/kern/uipc_debug.c b/sys/kern/uipc_debug.c index c3081a497ae6..caecad9bac84 100644 --- a/sys/kern/uipc_debug.c +++ b/sys/kern/uipc_debug.c @@ -209,15 +209,15 @@ db_print_sbstate(short sb_state) comma = 0; if (sb_state & SBS_CANTSENDMORE) { - db_printf("%sSS_CANTSENDMORE", comma ? ", " : ""); + db_printf("%sSBS_CANTSENDMORE", comma ? ", " : ""); comma = 1; } if (sb_state & SBS_CANTRCVMORE) { - db_printf("%sSS_CANTRCVMORE", comma ? ", " : ""); + db_printf("%sSBS_CANTRCVMORE", comma ? ", " : ""); comma = 1; } if (sb_state & SBS_RCVATMARK) { - db_printf("%sSS_RCVATMARK", comma ? ", " : ""); + db_printf("%sSBS_RCVATMARK", comma ? ", " : ""); comma = 1; } } diff --git a/sys/kern/uipc_socket.c b/sys/kern/uipc_socket.c index a431b4be6ace..c9d817954b97 100644 --- a/sys/kern/uipc_socket.c +++ b/sys/kern/uipc_socket.c @@ -805,7 +805,7 @@ sofree(struct socket *so) VNET_SO_ASSERT(so); if (pr->pr_flags & PR_RIGHTS && pr->pr_domain->dom_dispose != NULL) - (*pr->pr_domain->dom_dispose)(so->so_rcv.sb_mb); + (*pr->pr_domain->dom_dispose)(so); if (pr->pr_usrreqs->pru_detach != NULL) (*pr->pr_usrreqs->pru_detach)(so); @@ -2356,7 +2356,7 @@ sorflush(struct socket *so) { struct sockbuf *sb = &so->so_rcv; struct protosw *pr = so->so_proto; - struct sockbuf asb; + struct socket aso; VNET_SO_ASSERT(so); @@ -2381,8 +2381,9 @@ sorflush(struct socket *so) * and mutex data unchanged. */ SOCKBUF_LOCK(sb); - bzero(&asb, offsetof(struct sockbuf, sb_startzero)); - bcopy(&sb->sb_startzero, &asb.sb_startzero, + bzero(&aso, sizeof(aso)); + aso.so_pcb = so->so_pcb; + bcopy(&sb->sb_startzero, &aso.so_rcv.sb_startzero, sizeof(*sb) - offsetof(struct sockbuf, sb_startzero)); bzero(&sb->sb_startzero, sizeof(*sb) - offsetof(struct sockbuf, sb_startzero)); @@ -2390,12 +2391,12 @@ sorflush(struct socket *so) sbunlock(sb); /* - * Dispose of special rights and flush the socket buffer. Don't call - * any unsafe routines (that rely on locks being initialized) on asb. + * Dispose of special rights and flush the copied socket. Don't call + * any unsafe routines (that rely on locks being initialized) on aso. */ if (pr->pr_flags & PR_RIGHTS && pr->pr_domain->dom_dispose != NULL) - (*pr->pr_domain->dom_dispose)(asb.sb_mb); - sbrelease_internal(&asb, so); + (*pr->pr_domain->dom_dispose)(&aso); + sbrelease_internal(&aso.so_rcv, so); } /* diff --git a/sys/kern/uipc_usrreq.c b/sys/kern/uipc_usrreq.c index acf9fe9bd1e0..c3a71c8fb351 100644 --- a/sys/kern/uipc_usrreq.c +++ b/sys/kern/uipc_usrreq.c @@ -278,6 +278,7 @@ static int unp_connectat(int, struct socket *, struct sockaddr *, static int unp_connect2(struct socket *so, struct socket *so2, int); static void unp_disconnect(struct unpcb *unp, struct unpcb *unp2); static void unp_dispose(struct mbuf *); +static void unp_dispose_so(struct socket *so); static void unp_shutdown(struct unpcb *); static void unp_drop(struct unpcb *, int); static void unp_gc(__unused void *, int); @@ -334,7 +335,7 @@ static struct domain localdomain = { .dom_name = "local", .dom_init = unp_init, .dom_externalize = unp_externalize, - .dom_dispose = unp_dispose, + .dom_dispose = unp_dispose_so, .dom_protosw = localsw, .dom_protoswNPROTOSW = &localsw[sizeof(localsw)/sizeof(localsw[0])] }; @@ -736,8 +737,10 @@ uipc_listen(struct socket *so, int backlog, struct thread *td) UNP_PCB_LOCK(unp); if (unp->unp_vnode == NULL) { + /* Already connected or not bound to an address. */ + error = unp->unp_conn != NULL ? EINVAL : EDESTADDRREQ; UNP_PCB_UNLOCK(unp); - return (EINVAL); + return (error); } SOCK_LOCK(so); @@ -2214,15 +2217,19 @@ unp_gc_process(struct unpcb *unp) * Mark all sockets we reference with RIGHTS. */ so = unp->unp_socket; - SOCKBUF_LOCK(&so->so_rcv); - unp_scan(so->so_rcv.sb_mb, unp_accessable); - SOCKBUF_UNLOCK(&so->so_rcv); + if ((unp->unp_gcflag & UNPGC_IGNORE_RIGHTS) == 0) { + SOCKBUF_LOCK(&so->so_rcv); + unp_scan(so->so_rcv.sb_mb, unp_accessable); + SOCKBUF_UNLOCK(&so->so_rcv); + } /* * Mark all sockets in our accept queue. */ ACCEPT_LOCK(); TAILQ_FOREACH(soa, &so->so_comp, so_list) { + if ((sotounpcb(soa)->unp_gcflag & UNPGC_IGNORE_RIGHTS) != 0) + continue; SOCKBUF_LOCK(&soa->so_rcv); unp_scan(soa->so_rcv.sb_mb, unp_accessable); SOCKBUF_UNLOCK(&soa->so_rcv); @@ -2252,11 +2259,13 @@ unp_gc(__unused void *arg, int pending) unp_taskcount++; UNP_LIST_LOCK(); /* - * First clear all gc flags from previous runs. + * First clear all gc flags from previous runs, apart from + * UNPGC_IGNORE_RIGHTS. */ for (head = heads; *head != NULL; head++) LIST_FOREACH(unp, *head, unp_link) - unp->unp_gcflag = 0; + unp->unp_gcflag = + (unp->unp_gcflag & UNPGC_IGNORE_RIGHTS); /* * Scan marking all reachable sockets with UNPGC_REF. Once a socket @@ -2333,6 +2342,21 @@ unp_dispose(struct mbuf *m) unp_scan(m, unp_freerights); } +/* + * Synchronize against unp_gc, which can trip over data as we are freeing it. + */ +static void +unp_dispose_so(struct socket *so) +{ + struct unpcb *unp; + + unp = sotounpcb(so); + UNP_LIST_LOCK(); + unp->unp_gcflag |= UNPGC_IGNORE_RIGHTS; + UNP_LIST_UNLOCK(); + unp_dispose(so->so_rcv.sb_mb); +} + static void unp_scan(struct mbuf *m0, void (*op)(struct filedescent **, int)) { diff --git a/sys/kern/vfs_bio.c b/sys/kern/vfs_bio.c index b38057890396..19ec6ddc1b9a 100644 --- a/sys/kern/vfs_bio.c +++ b/sys/kern/vfs_bio.c @@ -1205,6 +1205,12 @@ bufwrite(struct buf *bp) int vp_md; CTR3(KTR_BUF, "bufwrite(%p) vp %p flags %X", bp, bp->b_vp, bp->b_flags); + if ((bp->b_bufobj->bo_flag & BO_DEAD) != 0) { + bp->b_flags |= B_INVAL | B_RELBUF; + bp->b_flags &= ~B_CACHE; + brelse(bp); + return (ENXIO); + } if (bp->b_flags & B_INVAL) { brelse(bp); return (0); diff --git a/sys/kern/vfs_cache.c b/sys/kern/vfs_cache.c index 19ef783c8959..cb4ea94b890f 100644 --- a/sys/kern/vfs_cache.c +++ b/sys/kern/vfs_cache.c @@ -661,12 +661,12 @@ success: ltype = VOP_ISLOCKED(dvp); VOP_UNLOCK(dvp, 0); } - VI_LOCK(*vpp); + vhold(*vpp); if (wlocked) CACHE_WUNLOCK(); else CACHE_RUNLOCK(); - error = vget(*vpp, cnp->cn_lkflags | LK_INTERLOCK, cnp->cn_thread); + error = vget(*vpp, cnp->cn_lkflags | LK_VNHELD, cnp->cn_thread); if (cnp->cn_flags & ISDOTDOT) { vn_lock(dvp, ltype | LK_RETRY); if (dvp->v_iflag & VI_DOOMED) { @@ -1366,9 +1366,9 @@ vn_dir_dd_ino(struct vnode *vp) if ((ncp->nc_flag & NCF_ISDOTDOT) != 0) continue; ddvp = ncp->nc_dvp; - VI_LOCK(ddvp); + vhold(ddvp); CACHE_RUNLOCK(); - if (vget(ddvp, LK_INTERLOCK | LK_SHARED | LK_NOWAIT, curthread)) + if (vget(ddvp, LK_SHARED | LK_NOWAIT | LK_VNHELD, curthread)) return (NULL); return (ddvp); } diff --git a/sys/kern/vfs_hash.c b/sys/kern/vfs_hash.c index 930fca1a3f7f..48601e762181 100644 --- a/sys/kern/vfs_hash.c +++ b/sys/kern/vfs_hash.c @@ -84,9 +84,9 @@ vfs_hash_get(const struct mount *mp, u_int hash, int flags, struct thread *td, s continue; if (fn != NULL && fn(vp, arg)) continue; - VI_LOCK(vp); + vhold(vp); rw_runlock(&vfs_hash_lock); - error = vget(vp, flags | LK_INTERLOCK, td); + error = vget(vp, flags | LK_VNHELD, td); if (error == ENOENT && (flags & LK_NOWAIT) == 0) break; if (error) @@ -128,9 +128,9 @@ vfs_hash_insert(struct vnode *vp, u_int hash, int flags, struct thread *td, stru continue; if (fn != NULL && fn(vp2, arg)) continue; - VI_LOCK(vp2); + vhold(vp2); rw_wunlock(&vfs_hash_lock); - error = vget(vp2, flags | LK_INTERLOCK, td); + error = vget(vp2, flags | LK_VNHELD, td); if (error == ENOENT && (flags & LK_NOWAIT) == 0) break; rw_wlock(&vfs_hash_lock); diff --git a/sys/kern/vfs_subr.c b/sys/kern/vfs_subr.c index 30aea6221b61..b24a6aeb761a 100644 --- a/sys/kern/vfs_subr.c +++ b/sys/kern/vfs_subr.c @@ -68,6 +68,7 @@ __FBSDID("$FreeBSD$"); #include #include #include +#include #include #include #include @@ -101,10 +102,10 @@ static int flushbuflist(struct bufv *bufv, int flags, struct bufobj *bo, int slpflag, int slptimeo); static void syncer_shutdown(void *arg, int howto); static int vtryrecycle(struct vnode *vp); +static void v_init_counters(struct vnode *); static void v_incr_usecount(struct vnode *); -static void v_decr_usecount(struct vnode *); -static void v_decr_useonly(struct vnode *); -static void v_upgrade_usecount(struct vnode *); +static void v_incr_devcount(struct vnode *); +static void v_decr_devcount(struct vnode *); static void vnlru_free(int); static void vgonel(struct vnode *); static void vfs_knllock(void *arg); @@ -868,7 +869,7 @@ vnlru_free(int count) */ freevnodes--; vp->v_iflag &= ~VI_FREE; - vp->v_holdcnt++; + refcount_acquire(&vp->v_holdcnt); mtx_unlock(&vnode_free_list_mtx); VI_UNLOCK(vp); @@ -1142,7 +1143,7 @@ alloc: vp->v_type = VNON; vp->v_tag = tag; vp->v_op = vops; - v_incr_usecount(vp); + v_init_counters(vp); vp->v_data = NULL; #ifdef MAC mac_vnode_init(vp); @@ -1584,7 +1585,8 @@ buf_vlist_add(struct buf *bp, struct bufobj *bo, b_xflags_t xflags) int error; ASSERT_BO_WLOCKED(bo); - KASSERT((bo->bo_flag & BO_DEAD) == 0, ("dead bo %p", bo)); + KASSERT((xflags & BX_VNDIRTY) == 0 || (bo->bo_flag & BO_DEAD) == 0, + ("dead bo %p", bo)); KASSERT((bp->b_xflags & (BX_VNDIRTY|BX_VNCLEAN)) == 0, ("buf_vlist_add: Buf %p has existing xflags %d", bp, bp->b_xflags)); bp->b_xflags |= xflags; @@ -2068,19 +2070,96 @@ reassignbuf(struct buf *bp) BO_UNLOCK(bo); } +/* + * A temporary hack until refcount_* APIs are sorted out. + */ +static __inline int +vfs_refcount_acquire_if_not_zero(volatile u_int *count) +{ + u_int old; + + for (;;) { + old = *count; + if (old == 0) + return (0); + if (atomic_cmpset_int(count, old, old + 1)) + return (1); + } +} + +static __inline int +vfs_refcount_release_if_not_last(volatile u_int *count) +{ + u_int old; + + for (;;) { + old = *count; + if (old == 1) + return (0); + if (atomic_cmpset_int(count, old, old - 1)) + return (1); + } +} + +static void +v_init_counters(struct vnode *vp) +{ + + VNASSERT(vp->v_type == VNON && vp->v_data == NULL && vp->v_iflag == 0, + vp, ("%s called for an initialized vnode", __FUNCTION__)); + ASSERT_VI_UNLOCKED(vp, __FUNCTION__); + + refcount_init(&vp->v_holdcnt, 1); + refcount_init(&vp->v_usecount, 1); +} + /* * Increment the use and hold counts on the vnode, taking care to reference - * the driver's usecount if this is a chardev. The vholdl() will remove - * the vnode from the free list if it is presently free. Requires the - * vnode interlock and returns with it held. + * the driver's usecount if this is a chardev. The _vhold() will remove + * the vnode from the free list if it is presently free. */ static void v_incr_usecount(struct vnode *vp) { + ASSERT_VI_UNLOCKED(vp, __func__); CTR2(KTR_VFS, "%s: vp %p", __func__, vp); - vholdl(vp); - vp->v_usecount++; + + if (vp->v_type == VCHR) { + VI_LOCK(vp); + _vhold(vp, true); + if (vp->v_iflag & VI_OWEINACT) { + VNASSERT(vp->v_usecount == 0, vp, + ("vnode with usecount and VI_OWEINACT set")); + vp->v_iflag &= ~VI_OWEINACT; + } + refcount_acquire(&vp->v_usecount); + v_incr_devcount(vp); + VI_UNLOCK(vp); + return; + } + + _vhold(vp, false); + if (vfs_refcount_acquire_if_not_zero(&vp->v_usecount)) { + VNASSERT((vp->v_iflag & VI_OWEINACT) == 0, vp, + ("vnode with usecount and VI_OWEINACT set")); + } else { + VI_LOCK(vp); + if (vp->v_iflag & VI_OWEINACT) + vp->v_iflag &= ~VI_OWEINACT; + refcount_acquire(&vp->v_usecount); + VI_UNLOCK(vp); + } +} + +/* + * Increment si_usecount of the associated device, if any. + */ +static void +v_incr_devcount(struct vnode *vp) +{ + + ASSERT_VI_LOCKED(vp, __FUNCTION__); if (vp->v_type == VCHR && vp->v_rdev != NULL) { dev_lock(); vp->v_rdev->si_usecount++; @@ -2089,59 +2168,13 @@ v_incr_usecount(struct vnode *vp) } /* - * Turn a holdcnt into a use+holdcnt such that only one call to - * v_decr_usecount is needed. + * Decrement si_usecount of the associated device, if any. */ static void -v_upgrade_usecount(struct vnode *vp) -{ - - CTR2(KTR_VFS, "%s: vp %p", __func__, vp); - vp->v_usecount++; - if (vp->v_type == VCHR && vp->v_rdev != NULL) { - dev_lock(); - vp->v_rdev->si_usecount++; - dev_unlock(); - } -} - -/* - * Decrement the vnode use and hold count along with the driver's usecount - * if this is a chardev. The vdropl() below releases the vnode interlock - * as it may free the vnode. - */ -static void -v_decr_usecount(struct vnode *vp) +v_decr_devcount(struct vnode *vp) { ASSERT_VI_LOCKED(vp, __FUNCTION__); - VNASSERT(vp->v_usecount > 0, vp, - ("v_decr_usecount: negative usecount")); - CTR2(KTR_VFS, "%s: vp %p", __func__, vp); - vp->v_usecount--; - if (vp->v_type == VCHR && vp->v_rdev != NULL) { - dev_lock(); - vp->v_rdev->si_usecount--; - dev_unlock(); - } - vdropl(vp); -} - -/* - * Decrement only the use count and driver use count. This is intended to - * be paired with a follow on vdropl() to release the remaining hold count. - * In this way we may vgone() a vnode with a 0 usecount without risk of - * having it end up on a free list because the hold count is kept above 0. - */ -static void -v_decr_useonly(struct vnode *vp) -{ - - ASSERT_VI_LOCKED(vp, __FUNCTION__); - VNASSERT(vp->v_usecount > 0, vp, - ("v_decr_useonly: negative usecount")); - CTR2(KTR_VFS, "%s: vp %p", __func__, vp); - vp->v_usecount--; if (vp->v_type == VCHR && vp->v_rdev != NULL) { dev_lock(); vp->v_rdev->si_usecount--; @@ -2155,21 +2188,35 @@ v_decr_useonly(struct vnode *vp) * is being destroyed. Only callers who specify LK_RETRY will * see doomed vnodes. If inactive processing was delayed in * vput try to do it here. + * + * Notes on lockless counter manipulation: + * _vhold, vputx and other routines make various decisions based + * on either holdcnt or usecount being 0. As long as either contuner + * is not transitioning 0->1 nor 1->0, the manipulation can be done + * with atomic operations. Otherwise the interlock is taken. */ int vget(struct vnode *vp, int flags, struct thread *td) { - int error; + int error, oweinact; - error = 0; VNASSERT((flags & LK_TYPE_MASK) != 0, vp, ("vget: invalid lock operation")); + + if ((flags & LK_INTERLOCK) != 0) + ASSERT_VI_LOCKED(vp, __func__); + else + ASSERT_VI_UNLOCKED(vp, __func__); + if ((flags & LK_VNHELD) != 0) + VNASSERT((vp->v_holdcnt > 0), vp, + ("vget: LK_VNHELD passed but vnode not held")); + CTR3(KTR_VFS, "%s: vp %p with flags %d", __func__, vp, flags); - if ((flags & LK_INTERLOCK) == 0) - VI_LOCK(vp); - vholdl(vp); - if ((error = vn_lock(vp, flags | LK_INTERLOCK)) != 0) { + if ((flags & LK_VNHELD) == 0) + _vhold(vp, (flags & LK_INTERLOCK) != 0); + + if ((error = vn_lock(vp, flags)) != 0) { vdrop(vp); CTR2(KTR_VFS, "%s: impossible to lock vnode %p", __func__, vp); @@ -2177,22 +2224,33 @@ vget(struct vnode *vp, int flags, struct thread *td) } if (vp->v_iflag & VI_DOOMED && (flags & LK_RETRY) == 0) panic("vget: vn_lock failed to return ENOENT\n"); - VI_LOCK(vp); - /* Upgrade our holdcnt to a usecount. */ - v_upgrade_usecount(vp); /* * We don't guarantee that any particular close will * trigger inactive processing so just make a best effort * here at preventing a reference to a removed file. If * we don't succeed no harm is done. + * + * Upgrade our holdcnt to a usecount. */ - if (vp->v_iflag & VI_OWEINACT) { - if (VOP_ISLOCKED(vp) == LK_EXCLUSIVE && + if (vp->v_type != VCHR && + vfs_refcount_acquire_if_not_zero(&vp->v_usecount)) { + VNASSERT((vp->v_iflag & VI_OWEINACT) == 0, vp, + ("vnode with usecount and VI_OWEINACT set")); + } else { + VI_LOCK(vp); + if ((vp->v_iflag & VI_OWEINACT) == 0) { + oweinact = 0; + } else { + oweinact = 1; + vp->v_iflag &= ~VI_OWEINACT; + } + refcount_acquire(&vp->v_usecount); + v_incr_devcount(vp); + if (oweinact && VOP_ISLOCKED(vp) == LK_EXCLUSIVE && (flags & LK_NOWAIT) == 0) vinactive(vp, td); - vp->v_iflag &= ~VI_OWEINACT; + VI_UNLOCK(vp); } - VI_UNLOCK(vp); return (0); } @@ -2204,36 +2262,34 @@ vref(struct vnode *vp) { CTR2(KTR_VFS, "%s: vp %p", __func__, vp); - VI_LOCK(vp); v_incr_usecount(vp); - VI_UNLOCK(vp); } /* * Return reference count of a vnode. * - * The results of this call are only guaranteed when some mechanism other - * than the VI lock is used to stop other processes from gaining references - * to the vnode. This may be the case if the caller holds the only reference. - * This is also useful when stale data is acceptable as race conditions may - * be accounted for by some other means. + * The results of this call are only guaranteed when some mechanism is used to + * stop other processes from gaining references to the vnode. This may be the + * case if the caller holds the only reference. This is also useful when stale + * data is acceptable as race conditions may be accounted for by some other + * means. */ int vrefcnt(struct vnode *vp) { - int usecnt; - VI_LOCK(vp); - usecnt = vp->v_usecount; - VI_UNLOCK(vp); - - return (usecnt); + return (vp->v_usecount); } #define VPUTX_VRELE 1 #define VPUTX_VPUT 2 #define VPUTX_VUNREF 3 +/* + * Decrement the use and hold counts for a vnode. + * + * See an explanation near vget() as to why atomic operation is safe. + */ static void vputx(struct vnode *vp, int func) { @@ -2246,33 +2302,44 @@ vputx(struct vnode *vp, int func) ASSERT_VOP_LOCKED(vp, "vput"); else KASSERT(func == VPUTX_VRELE, ("vputx: wrong func")); + ASSERT_VI_UNLOCKED(vp, __func__); CTR2(KTR_VFS, "%s: vp %p", __func__, vp); - VI_LOCK(vp); - /* Skip this v_writecount check if we're going to panic below. */ - VNASSERT(vp->v_writecount < vp->v_usecount || vp->v_usecount < 1, vp, - ("vputx: missed vn_close")); - error = 0; - - if (vp->v_usecount > 1 || ((vp->v_iflag & VI_DOINGINACT) && - vp->v_usecount == 1)) { + if (vp->v_type != VCHR && + vfs_refcount_release_if_not_last(&vp->v_usecount)) { if (func == VPUTX_VPUT) VOP_UNLOCK(vp, 0); - v_decr_usecount(vp); + vdrop(vp); return; } - if (vp->v_usecount != 1) { - vprint("vputx: negative ref count", vp); - panic("vputx: negative ref cnt"); - } - CTR2(KTR_VFS, "%s: return vnode %p to the freelist", __func__, vp); + VI_LOCK(vp); + /* * We want to hold the vnode until the inactive finishes to * prevent vgone() races. We drop the use count here and the * hold count below when we're done. */ - v_decr_useonly(vp); + if (!refcount_release(&vp->v_usecount) || + (vp->v_iflag & VI_DOINGINACT)) { + if (func == VPUTX_VPUT) + VOP_UNLOCK(vp, 0); + v_decr_devcount(vp); + vdropl(vp); + return; + } + + v_decr_devcount(vp); + + error = 0; + + if (vp->v_usecount != 0) { + vprint("vputx: usecount not zero", vp); + panic("vputx: usecount not zero"); + } + + CTR2(KTR_VFS, "%s: return vnode %p to the freelist", __func__, vp); + /* * We must call VOP_INACTIVE with the node locked. Mark * as VI_DOINGINACT to avoid recursion. @@ -2297,8 +2364,8 @@ vputx(struct vnode *vp, int func) } break; } - if (vp->v_usecount > 0) - vp->v_iflag &= ~VI_OWEINACT; + VNASSERT(vp->v_usecount == 0 || (vp->v_iflag & VI_OWEINACT) == 0, vp, + ("vnode with usecount and VI_OWEINACT set")); if (error == 0) { if (vp->v_iflag & VI_OWEINACT) vinactive(vp, curthread); @@ -2341,37 +2408,37 @@ vunref(struct vnode *vp) vputx(vp, VPUTX_VUNREF); } -/* - * Somebody doesn't want the vnode recycled. - */ -void -vhold(struct vnode *vp) -{ - - VI_LOCK(vp); - vholdl(vp); - VI_UNLOCK(vp); -} - /* * Increase the hold count and activate if this is the first reference. */ void -vholdl(struct vnode *vp) +_vhold(struct vnode *vp, bool locked) { struct mount *mp; + if (locked) + ASSERT_VI_LOCKED(vp, __func__); + else + ASSERT_VI_UNLOCKED(vp, __func__); CTR2(KTR_VFS, "%s: vp %p", __func__, vp); -#ifdef INVARIANTS - /* getnewvnode() calls v_incr_usecount() without holding interlock. */ - if (vp->v_type != VNON || vp->v_data != NULL) - ASSERT_VI_LOCKED(vp, "vholdl"); -#endif - vp->v_holdcnt++; - if ((vp->v_iflag & VI_FREE) == 0) + if (!locked && vfs_refcount_acquire_if_not_zero(&vp->v_holdcnt)) { + VNASSERT((vp->v_iflag & VI_FREE) == 0, vp, + ("_vhold: vnode with holdcnt is free")); return; - VNASSERT(vp->v_holdcnt == 1, vp, ("vholdl: wrong hold count")); - VNASSERT(vp->v_op != NULL, vp, ("vholdl: vnode already reclaimed.")); + } + + if (!locked) + VI_LOCK(vp); + if ((vp->v_iflag & VI_FREE) == 0) { + refcount_acquire(&vp->v_holdcnt); + if (!locked) + VI_UNLOCK(vp); + return; + } + VNASSERT(vp->v_holdcnt == 0, vp, + ("%s: wrong hold count", __func__)); + VNASSERT(vp->v_op != NULL, vp, + ("%s: vnode already reclaimed.", __func__)); /* * Remove a vnode from the free list, mark it as in use, * and put it on the active list. @@ -2387,18 +2454,9 @@ vholdl(struct vnode *vp) TAILQ_INSERT_HEAD(&mp->mnt_activevnodelist, vp, v_actfreelist); mp->mnt_activevnodelistsize++; mtx_unlock(&vnode_free_list_mtx); -} - -/* - * Note that there is one less who cares about this vnode. - * vdrop() is the opposite of vhold(). - */ -void -vdrop(struct vnode *vp) -{ - - VI_LOCK(vp); - vdropl(vp); + refcount_acquire(&vp->v_holdcnt); + if (!locked) + VI_UNLOCK(vp); } /* @@ -2407,20 +2465,28 @@ vdrop(struct vnode *vp) * (marked VI_DOOMED) in which case we will free it. */ void -vdropl(struct vnode *vp) +_vdrop(struct vnode *vp, bool locked) { struct bufobj *bo; struct mount *mp; int active; - ASSERT_VI_LOCKED(vp, "vdropl"); + if (locked) + ASSERT_VI_LOCKED(vp, __func__); + else + ASSERT_VI_UNLOCKED(vp, __func__); CTR2(KTR_VFS, "%s: vp %p", __func__, vp); - if (vp->v_holdcnt <= 0) + if ((int)vp->v_holdcnt <= 0) panic("vdrop: holdcnt %d", vp->v_holdcnt); - vp->v_holdcnt--; - VNASSERT(vp->v_holdcnt >= vp->v_usecount, vp, - ("hold count less than use count")); - if (vp->v_holdcnt > 0) { + if (vfs_refcount_release_if_not_last(&vp->v_holdcnt)) { + if (locked) + VI_UNLOCK(vp); + return; + } + + if (!locked) + VI_LOCK(vp); + if (refcount_release(&vp->v_holdcnt) == 0) { VI_UNLOCK(vp); return; } @@ -2841,7 +2907,7 @@ vgonel(struct vnode *vp) while (vinvalbuf(vp, 0, 0, 0) != 0) ; } -#ifdef INVARIANTS + BO_LOCK(&vp->v_bufobj); KASSERT(TAILQ_EMPTY(&vp->v_bufobj.bo_dirty.bv_hd) && vp->v_bufobj.bo_dirty.bv_cnt == 0 && @@ -2850,7 +2916,6 @@ vgonel(struct vnode *vp) ("vp %p bufobj not invalidated", vp)); vp->v_bufobj.bo_flag |= BO_DEAD; BO_UNLOCK(&vp->v_bufobj); -#endif /* * Reclaim the vnode. diff --git a/sys/kern/vfs_syscalls.c b/sys/kern/vfs_syscalls.c index 9088017af133..ba914e68da69 100644 --- a/sys/kern/vfs_syscalls.c +++ b/sys/kern/vfs_syscalls.c @@ -94,7 +94,6 @@ SDT_PROVIDER_DEFINE(vfs); SDT_PROBE_DEFINE2(vfs, , stat, mode, "char *", "int"); SDT_PROBE_DEFINE2(vfs, , stat, reg, "char *", "int"); -static int chroot_refuse_vdir_fds(struct filedesc *fdp); static int kern_chflagsat(struct thread *td, int fd, const char *path, enum uio_seg pathseg, u_long flags, int atflag); static int setfflags(struct thread *td, struct vnode *, u_long); @@ -728,8 +727,7 @@ sys_fchdir(td, uap) int fd; } */ *uap; { - register struct filedesc *fdp = td->td_proc->p_fd; - struct vnode *vp, *tdp, *vpold; + struct vnode *vp, *tdp; struct mount *mp; struct file *fp; cap_rights_t rights; @@ -761,11 +759,7 @@ sys_fchdir(td, uap) return (error); } VOP_UNLOCK(vp, 0); - FILEDESC_XLOCK(fdp); - vpold = fdp->fd_cdir; - fdp->fd_cdir = vp; - FILEDESC_XUNLOCK(fdp); - vrele(vpold); + pwd_chdir(td, vp); return (0); } @@ -791,9 +785,7 @@ sys_chdir(td, uap) int kern_chdir(struct thread *td, char *path, enum uio_seg pathseg) { - register struct filedesc *fdp = td->td_proc->p_fd; struct nameidata nd; - struct vnode *vp; int error; NDINIT(&nd, LOOKUP, FOLLOW | LOCKSHARED | LOCKLEAF | AUDITVNODE1, @@ -807,55 +799,10 @@ kern_chdir(struct thread *td, char *path, enum uio_seg pathseg) } VOP_UNLOCK(nd.ni_vp, 0); NDFREE(&nd, NDF_ONLY_PNBUF); - FILEDESC_XLOCK(fdp); - vp = fdp->fd_cdir; - fdp->fd_cdir = nd.ni_vp; - FILEDESC_XUNLOCK(fdp); - vrele(vp); + pwd_chdir(td, nd.ni_vp); return (0); } -/* - * Helper function for raised chroot(2) security function: Refuse if - * any filedescriptors are open directories. - */ -static int -chroot_refuse_vdir_fds(fdp) - struct filedesc *fdp; -{ - struct vnode *vp; - struct file *fp; - int fd; - - FILEDESC_LOCK_ASSERT(fdp); - - for (fd = 0; fd <= fdp->fd_lastfile; fd++) { - fp = fget_locked(fdp, fd); - if (fp == NULL) - continue; - if (fp->f_type == DTYPE_VNODE) { - vp = fp->f_vnode; - if (vp->v_type == VDIR) - return (EPERM); - } - } - return (0); -} - -/* - * This sysctl determines if we will allow a process to chroot(2) if it - * has a directory open: - * 0: disallowed for all processes. - * 1: allowed for processes that were not already chroot(2)'ed. - * 2: allowed for all processes. - */ - -static int chroot_allow_open_directories = 1; - -SYSCTL_INT(_kern, OID_AUTO, chroot_allow_open_directories, CTLFLAG_RW, - &chroot_allow_open_directories, 0, - "Allow a process to chroot(2) if it has a directory open"); - /* * Change notion of root (``/'') directory. */ @@ -891,7 +838,7 @@ sys_chroot(td, uap) goto e_vunlock; #endif VOP_UNLOCK(nd.ni_vp, 0); - error = change_root(nd.ni_vp, td); + error = pwd_chroot(td, nd.ni_vp); vrele(nd.ni_vp); NDFREE(&nd, NDF_ONLY_PNBUF); return (error); @@ -926,42 +873,6 @@ change_dir(vp, td) return (VOP_ACCESS(vp, VEXEC, td->td_ucred, td)); } -/* - * Common routine for kern_chroot() and jail_attach(). The caller is - * responsible for invoking priv_check() and mac_vnode_check_chroot() to - * authorize this operation. - */ -int -change_root(vp, td) - struct vnode *vp; - struct thread *td; -{ - struct filedesc *fdp; - struct vnode *oldvp; - int error; - - fdp = td->td_proc->p_fd; - FILEDESC_XLOCK(fdp); - if (chroot_allow_open_directories == 0 || - (chroot_allow_open_directories == 1 && fdp->fd_rdir != rootvnode)) { - error = chroot_refuse_vdir_fds(fdp); - if (error != 0) { - FILEDESC_XUNLOCK(fdp); - return (error); - } - } - oldvp = fdp->fd_rdir; - fdp->fd_rdir = vp; - VREF(fdp->fd_rdir); - if (!fdp->fd_jdir) { - fdp->fd_jdir = vp; - VREF(fdp->fd_jdir); - } - FILEDESC_XUNLOCK(fdp); - vrele(oldvp); - return (0); -} - static __inline void flags_to_rights(int flags, cap_rights_t *rightsp) { diff --git a/sys/mips/atheros/ar71xx_machdep.c b/sys/mips/atheros/ar71xx_machdep.c index 02302fd38297..a974bba86c45 100644 --- a/sys/mips/atheros/ar71xx_machdep.c +++ b/sys/mips/atheros/ar71xx_machdep.c @@ -304,6 +304,8 @@ ar71xx_platform_check_mac_hints(void) return (0); } +extern char cpu_model[]; + void platform_start(__register_t a0 __unused, __register_t a1 __unused, __register_t a2 __unused, __register_t a3 __unused) @@ -417,6 +419,8 @@ platform_start(__register_t a0 __unused, __register_t a1 __unused, printf(" a2 = %08x\n", a2); printf(" a3 = %08x\n", a3); + strcpy(cpu_model, ar71xx_get_system_type()); + /* * XXX this code is very redboot specific. */ diff --git a/sys/modules/Makefile b/sys/modules/Makefile index 5f8ba1d62aad..508488414136 100644 --- a/sys/modules/Makefile +++ b/sys/modules/Makefile @@ -72,6 +72,8 @@ SUBDIR= \ ${_ce} \ ${_cfi} \ ${_ciss} \ + cloudabi \ + ${_cloudabi64} \ ${_cm} \ ${_cmx} \ ${_coff} \ @@ -276,6 +278,7 @@ SUBDIR= \ ${_pfsync} \ plip \ ${_pmc} \ + ${_pms} \ ppbus \ ppc \ ppi \ @@ -615,11 +618,13 @@ _x86bios= x86bios .endif .if ${MACHINE_CPUARCH} == "amd64" +_cloudabi64= cloudabi64 _ixl= ixl _ixlv= ixlv _linux64= linux64 _linux_common= linux_common _ntb= ntb +_pms= pms _qlxge= qlxge _qlxgb= qlxgb _qlxgbe= qlxgbe diff --git a/sys/modules/cloudabi/Makefile b/sys/modules/cloudabi/Makefile new file mode 100644 index 000000000000..bba50362eab1 --- /dev/null +++ b/sys/modules/cloudabi/Makefile @@ -0,0 +1,10 @@ +# $FreeBSD$ + +.PATH: ${.CURDIR}/../../compat/cloudabi + +KMOD= cloudabi +SRCS= cloudabi_clock.c cloudabi_errno.c cloudabi_fd.c cloudabi_file.c \ + cloudabi_futex.c cloudabi_mem.c cloudabi_proc.c cloudabi_random.c \ + cloudabi_sock.c cloudabi_thread.c vnode_if.h + +.include diff --git a/sys/modules/cloudabi64/Makefile b/sys/modules/cloudabi64/Makefile new file mode 100644 index 000000000000..1e1a058acc71 --- /dev/null +++ b/sys/modules/cloudabi64/Makefile @@ -0,0 +1,11 @@ +# $FreeBSD$ + +.PATH: ${.CURDIR}/../../compat/cloudabi64 +.PATH: ${.CURDIR}/../../${MACHINE_CPUARCH}/cloudabi64 + +KMOD= cloudabi64 +SRCS= cloudabi64_fd.c cloudabi64_poll.c cloudabi64_sock.c \ + cloudabi64_syscalls.c cloudabi64_sysent.c cloudabi64_sysvec.c \ + cloudabi64_thread.c + +.include diff --git a/sys/modules/cxgbe/t4_firmware/Makefile b/sys/modules/cxgbe/t4_firmware/Makefile index de2b601165a1..16be94005f55 100644 --- a/sys/modules/cxgbe/t4_firmware/Makefile +++ b/sys/modules/cxgbe/t4_firmware/Makefile @@ -17,7 +17,7 @@ FIRMWS+= ${F}:${F:C/.txt//}:1.0.0.0 .endif .endfor -T4FW_VER= 1.11.27.0 +T4FW_VER= 1.14.2.0 FIRMWS+= t4fw.fw:t4fw:${T4FW_VER} CLEANFILES+= t4fw.fw diff --git a/sys/modules/cxgbe/t5_firmware/Makefile b/sys/modules/cxgbe/t5_firmware/Makefile index 2f414f3ede08..eba2faa20b43 100644 --- a/sys/modules/cxgbe/t5_firmware/Makefile +++ b/sys/modules/cxgbe/t5_firmware/Makefile @@ -17,7 +17,7 @@ FIRMWS+= ${F}:${F:C/.txt//}:1.0.0.0 .endif .endfor -T5FW_VER= 1.11.27.0 +T5FW_VER= 1.14.2.0 FIRMWS+= t5fw.fw:t5fw:${T5FW_VER} CLEANFILES+= t5fw.fw diff --git a/sys/modules/dtrace/Makefile b/sys/modules/dtrace/Makefile index d7540d958233..7be4c32889c5 100644 --- a/sys/modules/dtrace/Makefile +++ b/sys/modules/dtrace/Makefile @@ -7,7 +7,6 @@ SUBDIR= dtmalloc \ dtrace \ dtraceall \ dtrace_test \ - lockstat \ profile \ prototype \ sdt \ diff --git a/sys/modules/dtrace/Makefile.inc b/sys/modules/dtrace/Makefile.inc index 204e046706b9..3520c38d9655 100644 --- a/sys/modules/dtrace/Makefile.inc +++ b/sys/modules/dtrace/Makefile.inc @@ -6,7 +6,6 @@ load : -kldload dtrace .if ${MACHINE_CPUARCH} == "i386" -kldload sdt - -kldload lockstat -kldload fbt -kldload prototype .endif @@ -20,7 +19,6 @@ unload : .if ${MACHINE_CPUARCH} == "i386" -kldunload prototype -kldunload fbt - -kldunload lockstat -kldunload sdt .endif -kldunload dtrace diff --git a/sys/modules/dtrace/dtraceall/dtraceall.c b/sys/modules/dtrace/dtraceall/dtraceall.c index ecab4f7fdf82..754c1c4499bc 100644 --- a/sys/modules/dtrace/dtraceall/dtraceall.c +++ b/sys/modules/dtrace/dtraceall/dtraceall.c @@ -76,7 +76,6 @@ MODULE_DEPEND(dtraceall, fbt, 1, 1, 1); #if defined(__amd64__) || defined(__i386__) MODULE_DEPEND(dtraceall, fasttrap, 1, 1, 1); #endif -MODULE_DEPEND(dtraceall, lockstat, 1, 1, 1); MODULE_DEPEND(dtraceall, sdt, 1, 1, 1); MODULE_DEPEND(dtraceall, systrace, 1, 1, 1); #if defined(COMPAT_FREEBSD32) diff --git a/sys/modules/dtrace/lockstat/Makefile b/sys/modules/dtrace/lockstat/Makefile deleted file mode 100644 index 8780dd8cea41..000000000000 --- a/sys/modules/dtrace/lockstat/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# $FreeBSD$ - -SYSDIR?= ${.CURDIR}/../../.. - -.PATH: ${SYSDIR}/cddl/dev/lockstat - -KMOD= lockstat -SRCS= lockstat.c - -SRCS+= vnode_if.h - -CFLAGS+= -I${SYSDIR}/cddl/compat/opensolaris \ - -I${SYSDIR}/cddl/contrib/opensolaris/uts/common \ - -I${SYSDIR} - -.include - -CFLAGS+= -include ${SYSDIR}/cddl/compat/opensolaris/sys/debug_compat.h diff --git a/sys/modules/pms/Makefile b/sys/modules/pms/Makefile new file mode 100644 index 000000000000..128fe0868289 --- /dev/null +++ b/sys/modules/pms/Makefile @@ -0,0 +1,61 @@ +# $FreeBSD$ +# 5/31/2012 +#PATH shall include all directories + +.PATH: ${.CURDIR}/../../dev/pms/freebsd/driver/ini/src \ + ${.CURDIR}/../../dev/pms/RefTisa/sallsdk/api \ + ${.CURDIR}/../../dev/pms/RefTisa/sallsdk/spc \ + ${.CURDIR}/../../dev/pms/RefTisa/sallsdk/hda/64k \ + ${.CURDIR}/../../dev/pms/RefTisa/discovery/api \ + ${.CURDIR}/../../dev/pms/RefTisa/discovery/dm \ + ${.CURDIR}/../../dev/pms/RefTisa/sat/api \ + ${.CURDIR}/../../dev/pms/RefTisa/sat/src \ + ${.CURDIR}/../../dev/pms/RefTisa/tisa/api \ + ${.CURDIR}/../../dev/pms/RefTisa/tisa/sassata/common \ + ${.CURDIR}/../../dev/pms/RefTisa/tisa/sassata/sas/common \ + ${.CURDIR}/../../dev/pms/RefTisa/tisa/sassata/sas/ini \ + ${.CURDIR}/../../dev/pms/RefTisa/tisa/sassata/sata/host \ + ${.CURDIR}/../../dev/pms/freebsd/driver/common + +CFLAGS+=-fno-builtin +CFLAGS+=-fms-extensions + +CFLAGS+=-Wredundant-decls +CFLAGS+=-Wunused-variable +CFLAGS+=-Wnested-externs +CFLAGS+=-Woverflow +CFLAGS+=-Wmissing-prototypes +CFLAGS+=-Wparentheses +CFLAGS+=-w + +#CFLAGS+=-g + + +#SUBDIR= tisa tisa/drivers tisa/drivers/FreeBSD tisa/drivers/FreeBSD/ini tisa/drivers/FreeBSD/ini/src +#SUBDIR= Hialeah_driver Hialeah_driver/freebsd Hialeah_driver/freebsd/ini Hialeah_driver/freebsd/ini/src + +KMOD= pmspcv +#OS files +SRCS=agtiapi.c + +#LL files +SRCS+= sadisc.c mpi.c saframe.c sahw.c sainit.c saint.c sampicmd.c sampirsp.c saphy.c saport.c +SRCS+= sasata.c sasmp.c sassp.c satimer.c sautil.c saioctlcmd.c mpidebug.c +#DM files +SRCS+= dminit.c dmsmp.c dmdisc.c dmport.c dmtimer.c dmmisc.c +#SM files +SRCS+= sminit.c smmisc.c smsat.c smsatcb.c smsathw.c smtimer.c +#TD files +SRCS+= tdinit.c tdmisc.c tdesgl.c tdport.c tdint.c tdioctl.c tdhw.c ossacmnapi.c tddmcmnapi.c tdsmcmnapi.c +SRCS+= tdtimers.c itdio.c itdcb.c itdinit.c itddisc.c sat.c ossasat.c sathw.c + +#header files +SRCS+= agtiapi.h agtiproto.h agdef.h +# +SRCS+= osenv.h ostypes.h +SRCS+= opt_scsi.h opt_cam.h +SRCS+= device_if.h bus_if.h pci_if.h +#INCSRC= ../../common + + +.include diff --git a/sys/modules/pms/Makefile.inc b/sys/modules/pms/Makefile.inc new file mode 100644 index 000000000000..265f86d1ed55 --- /dev/null +++ b/sys/modules/pms/Makefile.inc @@ -0,0 +1,3 @@ +# $FreeBSD$ + +.include "../Makefile.inc" diff --git a/sys/net/if.c b/sys/net/if.c index a3e9e3eaf008..6ebfdbf639ca 100644 --- a/sys/net/if.c +++ b/sys/net/if.c @@ -335,11 +335,12 @@ ifnet_setbyindex(u_short idx, struct ifnet *ifp) struct ifaddr * ifaddr_byindex(u_short idx) { - struct ifaddr *ifa; + struct ifnet *ifp; + struct ifaddr *ifa = NULL; IFNET_RLOCK_NOSLEEP(); - ifa = ifnet_byindex_locked(idx)->if_addr; - if (ifa != NULL) + ifp = ifnet_byindex_locked(idx); + if (ifp != NULL && (ifa = ifp->if_addr) != NULL) ifa_ref(ifa); IFNET_RUNLOCK_NOSLEEP(); return (ifa); diff --git a/sys/net/if_tun.c b/sys/net/if_tun.c index 4dda87a08401..f5aba001e2f8 100644 --- a/sys/net/if_tun.c +++ b/sys/net/if_tun.c @@ -906,7 +906,7 @@ tunwrite(struct cdev *dev, struct uio *uio, int flag) m_freem(m); return (EAFNOSUPPORT); } - random_harvest_queue(&(m->m_data), 12, 2, RANDOM_NET_TUN); + random_harvest_queue(m, sizeof(*m), 2, RANDOM_NET_TUN); if_inc_counter(ifp, IFCOUNTER_IBYTES, m->m_pkthdr.len); if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); CURVNET_SET(ifp->if_vnet); diff --git a/sys/net/netmap.h b/sys/net/netmap.h index 1203bfb37fff..88b2957502ab 100644 --- a/sys/net/netmap.h +++ b/sys/net/netmap.h @@ -157,6 +157,11 @@ struct netmap_slot { /* * must be set whenever buf_idx is changed (as it might be * necessary to recompute the physical address and mapping) + * + * It is also set by the kernel whenever the buf_idx is + * changed internally (e.g., by pipes). Applications may + * use this information to know when they can reuse the + * contents of previously prepared buffers. */ #define NS_REPORT 0x0002 /* ask the hardware to report results */ @@ -513,6 +518,9 @@ enum { NR_REG_DEFAULT = 0, /* backward compat, should not be used. */ /* monitor uses the NR_REG to select the rings to monitor */ #define NR_MONITOR_TX 0x100 #define NR_MONITOR_RX 0x200 +#define NR_ZCOPY_MON 0x400 +/* request exclusive access to the selected rings */ +#define NR_EXCLUSIVE 0x800 /* diff --git a/sys/net/netmap_user.h b/sys/net/netmap_user.h index aab6c358de73..130117db7a2e 100644 --- a/sys/net/netmap_user.h +++ b/sys/net/netmap_user.h @@ -284,6 +284,12 @@ typedef void (*nm_cb_t)(u_char *, const struct nm_pkthdr *, const u_char *d); * -NN bind individual NIC ring pair * {NN bind master side of pipe NN * }NN bind slave side of pipe NN + * a suffix starting with + and the following flags, + * in any order: + * x exclusive access + * z zero copy monitor + * t monitor tx side + * r monitor rx side * * req provides the initial values of nmreq before parsing ifname. * Remember that the ifname parsing will override the ring @@ -351,9 +357,12 @@ nm_open(const char *ifname, const struct nmreq *req, struct nm_desc *d = NULL; const struct nm_desc *parent = arg; u_int namelen; - uint32_t nr_ringid = 0, nr_flags; + uint32_t nr_ringid = 0, nr_flags, nr_reg; const char *port = NULL; - const char *errmsg = NULL; +#define MAXERRMSG 80 + char errmsg[MAXERRMSG] = ""; + enum { P_START, P_RNGSFXOK, P_GETNUM, P_FLAGS, P_FLAGSOK } p_state; + long num; if (strncmp(ifname, "netmap:", 7) && strncmp(ifname, "vale", 4)) { errno = 0; /* name not recognised, not an error */ @@ -362,60 +371,112 @@ nm_open(const char *ifname, const struct nmreq *req, if (ifname[0] == 'n') ifname += 7; /* scan for a separator */ - for (port = ifname; *port && !index("-*^{}", *port); port++) + for (port = ifname; *port && !index("-*^{}/", *port); port++) ; namelen = port - ifname; if (namelen >= sizeof(d->req.nr_name)) { - errmsg = "name too long"; + snprintf(errmsg, MAXERRMSG, "name too long"); goto fail; } - switch (*port) { - default: /* '\0', no suffix */ - nr_flags = NR_REG_ALL_NIC; - break; - case '-': /* one NIC */ - nr_flags = NR_REG_ONE_NIC; - nr_ringid = atoi(port + 1); - break; - case '*': /* NIC and SW, ignore port */ - nr_flags = NR_REG_NIC_SW; - if (port[1]) { - errmsg = "invalid port for nic+sw"; - goto fail; + p_state = P_START; + nr_flags = NR_REG_ALL_NIC; /* default for no suffix */ + while (*port) { + switch (p_state) { + case P_START: + switch (*port) { + case '^': /* only SW ring */ + nr_flags = NR_REG_SW; + p_state = P_RNGSFXOK; + break; + case '*': /* NIC and SW */ + nr_flags = NR_REG_NIC_SW; + p_state = P_RNGSFXOK; + break; + case '-': /* one NIC ring pair */ + nr_flags = NR_REG_ONE_NIC; + p_state = P_GETNUM; + break; + case '{': /* pipe (master endpoint) */ + nr_flags = NR_REG_PIPE_MASTER; + p_state = P_GETNUM; + break; + case '}': /* pipe (slave endoint) */ + nr_flags = NR_REG_PIPE_SLAVE; + p_state = P_GETNUM; + break; + case '/': /* start of flags */ + p_state = P_FLAGS; + break; + default: + snprintf(errmsg, MAXERRMSG, "unknown modifier: '%c'", *port); + goto fail; + } + port++; + break; + case P_RNGSFXOK: + switch (*port) { + case '/': + p_state = P_FLAGS; + break; + default: + snprintf(errmsg, MAXERRMSG, "unexpected character: '%c'", *port); + goto fail; + } + port++; + break; + case P_GETNUM: + num = strtol(port, (char **)&port, 10); + if (num < 0 || num >= NETMAP_RING_MASK) { + snprintf(errmsg, MAXERRMSG, "'%ld' out of range [0, %d)", + num, NETMAP_RING_MASK); + goto fail; + } + nr_ringid = num & NETMAP_RING_MASK; + p_state = P_RNGSFXOK; + break; + case P_FLAGS: + case P_FLAGSOK: + switch (*port) { + case 'x': + nr_flags |= NR_EXCLUSIVE; + break; + case 'z': + nr_flags |= NR_ZCOPY_MON; + break; + case 't': + nr_flags |= NR_MONITOR_TX; + break; + case 'r': + nr_flags |= NR_MONITOR_RX; + break; + default: + snprintf(errmsg, MAXERRMSG, "unrecognized flag: '%c'", *port); + goto fail; + } + port++; + p_state = P_FLAGSOK; + break; } - break; - case '^': /* only sw ring */ - nr_flags = NR_REG_SW; - if (port[1]) { - errmsg = "invalid port for sw ring"; - goto fail; - } - break; - case '{': - nr_flags = NR_REG_PIPE_MASTER; - nr_ringid = atoi(port + 1); - break; - case '}': - nr_flags = NR_REG_PIPE_SLAVE; - nr_ringid = atoi(port + 1); - break; } - - if (nr_ringid >= NETMAP_RING_MASK) { - errmsg = "invalid ringid"; + if (p_state != P_START && p_state != P_RNGSFXOK && p_state != P_FLAGSOK) { + snprintf(errmsg, MAXERRMSG, "unexpected end of port name"); goto fail; } - + ND("flags: %s %s %s %s", + (nr_flags & NR_EXCLUSIVE) ? "EXCLUSIVE" : "", + (nr_flags & NR_ZCOPY_MON) ? "ZCOPY_MON" : "", + (nr_flags & NR_MONITOR_TX) ? "MONITOR_TX" : "", + (nr_flags & NR_MONITOR_RX) ? "MONITOR_RX" : ""); d = (struct nm_desc *)calloc(1, sizeof(*d)); if (d == NULL) { - errmsg = "nm_desc alloc failure"; + snprintf(errmsg, MAXERRMSG, "nm_desc alloc failure"); errno = ENOMEM; return NULL; } d->self = d; /* set this early so nm_close() works */ d->fd = open("/dev/netmap", O_RDWR); if (d->fd < 0) { - errmsg = "cannot open /dev/netmap"; + snprintf(errmsg, MAXERRMSG, "cannot open /dev/netmap: %s", strerror(errno)); goto fail; } @@ -464,7 +525,7 @@ nm_open(const char *ifname, const struct nmreq *req, d->req.nr_ringid |= new_flags & (NETMAP_NO_TX_POLL | NETMAP_DO_RX_POLL); if (ioctl(d->fd, NIOCREGIF, &d->req)) { - errmsg = "NIOCREGIF failed"; + snprintf(errmsg, MAXERRMSG, "NIOCREGIF failed: %s", strerror(errno)); goto fail; } @@ -479,7 +540,7 @@ nm_open(const char *ifname, const struct nmreq *req, d->mem = mmap(0, d->memsize, PROT_WRITE | PROT_READ, MAP_SHARED, d->fd, 0); if (d->mem == MAP_FAILED) { - errmsg = "mmap failed"; + snprintf(errmsg, MAXERRMSG, "mmap failed: %s", strerror(errno)); goto fail; } d->done_mmap = 1; @@ -495,20 +556,22 @@ nm_open(const char *ifname, const struct nmreq *req, (char *)d->mem + d->memsize; } - if (d->req.nr_flags == NR_REG_SW) { /* host stack */ + nr_reg = d->req.nr_flags & NR_REG_MASK; + + if (nr_reg == NR_REG_SW) { /* host stack */ d->first_tx_ring = d->last_tx_ring = d->req.nr_tx_rings; d->first_rx_ring = d->last_rx_ring = d->req.nr_rx_rings; - } else if (d->req.nr_flags == NR_REG_ALL_NIC) { /* only nic */ + } else if (nr_reg == NR_REG_ALL_NIC) { /* only nic */ d->first_tx_ring = 0; d->first_rx_ring = 0; d->last_tx_ring = d->req.nr_tx_rings - 1; d->last_rx_ring = d->req.nr_rx_rings - 1; - } else if (d->req.nr_flags == NR_REG_NIC_SW) { + } else if (nr_reg == NR_REG_NIC_SW) { d->first_tx_ring = 0; d->first_rx_ring = 0; d->last_tx_ring = d->req.nr_tx_rings; d->last_rx_ring = d->req.nr_rx_rings; - } else if (d->req.nr_flags == NR_REG_ONE_NIC) { + } else if (nr_reg == NR_REG_ONE_NIC) { /* XXX check validity */ d->first_tx_ring = d->last_tx_ring = d->first_rx_ring = d->last_rx_ring = d->req.nr_ringid & NETMAP_RING_MASK; @@ -541,7 +604,7 @@ nm_open(const char *ifname, const struct nmreq *req, fail: nm_close(d); - if (errmsg) + if (errmsg[0]) D("%s %s", errmsg, ifname); if (errno == 0) errno = EINVAL; diff --git a/sys/netgraph/ng_iface.c b/sys/netgraph/ng_iface.c index d84dbdf4d46d..7bbc1dac1c9a 100644 --- a/sys/netgraph/ng_iface.c +++ b/sys/netgraph/ng_iface.c @@ -705,7 +705,7 @@ ng_iface_rcvdata(hook_p hook, item_p item) m_freem(m); return (EAFNOSUPPORT); } - random_harvest_queue(&(m->m_data), 12, 2, RANDOM_NET_NG); + random_harvest_queue(m, sizeof(*m), 2, RANDOM_NET_NG); M_SETFIB(m, ifp->if_fib); netisr_dispatch(isr, m); return (0); diff --git a/sys/netinet/ip.h b/sys/netinet/ip.h index 848703734274..92693965c7bd 100644 --- a/sys/netinet/ip.h +++ b/sys/netinet/ip.h @@ -80,19 +80,19 @@ struct ip { #define IPTOS_MINCOST 0x02 /* - * Definitions for IP precedence (also in ip_tos) (hopefully unused). + * Definitions for IP precedence (also in ip_tos) (deprecated). */ -#define IPTOS_PREC_NETCONTROL 0xe0 -#define IPTOS_PREC_INTERNETCONTROL 0xc0 -#define IPTOS_PREC_CRITIC_ECP 0xa0 -#define IPTOS_PREC_FLASHOVERRIDE 0x80 -#define IPTOS_PREC_FLASH 0x60 -#define IPTOS_PREC_IMMEDIATE 0x40 -#define IPTOS_PREC_PRIORITY 0x20 -#define IPTOS_PREC_ROUTINE 0x00 +#define IPTOS_PREC_NETCONTROL IPTOS_DSCP_CS7 +#define IPTOS_PREC_INTERNETCONTROL IPTOS_DSCP_CS6 +#define IPTOS_PREC_CRITIC_ECP IPTOS_DSCP_CS5 +#define IPTOS_PREC_FLASHOVERRIDE IPTOS_DSCP_CS4 +#define IPTOS_PREC_FLASH IPTOS_DSCP_CS3 +#define IPTOS_PREC_IMMEDIATE IPTOS_DSCP_CS2 +#define IPTOS_PREC_PRIORITY IPTOS_DSCP_CS1 +#define IPTOS_PREC_ROUTINE IPTOS_DSCP_CS0 /* - * Definitions for DiffServ Codepoints as per RFC2474 + * Definitions for DiffServ Codepoints as per RFC2474 and RFC5865. */ #define IPTOS_DSCP_CS0 0x00 #define IPTOS_DSCP_CS1 0x20 @@ -112,6 +112,7 @@ struct ip { #define IPTOS_DSCP_AF42 0x90 #define IPTOS_DSCP_AF43 0x98 #define IPTOS_DSCP_CS5 0xa0 +#define IPTOS_DSCP_VA 0xb0 #define IPTOS_DSCP_EF 0xb8 #define IPTOS_DSCP_CS6 0xc0 #define IPTOS_DSCP_CS7 0xe0 diff --git a/sys/netinet/ip_var.h b/sys/netinet/ip_var.h index 239bc7342f80..34168054ee28 100644 --- a/sys/netinet/ip_var.h +++ b/sys/netinet/ip_var.h @@ -281,7 +281,7 @@ enum { IPFW_IS_MASK = 0x30000000, /* which source ? */ IPFW_IS_DIVERT = 0x20000000, IPFW_IS_DUMMYNET =0x10000000, - IPFW_IS_PIPE = 0x08000000, /* pip1=1, queue = 0 */ + IPFW_IS_PIPE = 0x08000000, /* pipe=1, queue = 0 */ }; #define MTAG_IPFW 1148380143 /* IPFW-tagged cookie */ #define MTAG_IPFW_RULE 1262273568 /* rule reference */ diff --git a/sys/netinet/sctp_indata.c b/sys/netinet/sctp_indata.c index 50a662864a02..9bfdddc13c80 100644 --- a/sys/netinet/sctp_indata.c +++ b/sys/netinet/sctp_indata.c @@ -1886,6 +1886,7 @@ finish_express_del: sctp_reset_in_stream(stcb, liste->number_entries, liste->list_of_streams); TAILQ_REMOVE(&asoc->resetHead, liste, next_resp); + sctp_send_deferred_reset_response(stcb, liste, SCTP_STREAM_RESET_RESULT_PERFORMED); SCTP_FREE(liste, SCTP_M_STRESET); /* sa_ignore FREED_MEMORY */ liste = TAILQ_FIRST(&asoc->resetHead); diff --git a/sys/netinet/sctp_input.c b/sys/netinet/sctp_input.c index c6bea83f1992..341982124786 100644 --- a/sys/netinet/sctp_input.c +++ b/sys/netinet/sctp_input.c @@ -357,14 +357,17 @@ sctp_process_init(struct sctp_init_chunk *cp, struct sctp_tcb *stcb) sctp_free_a_strmoq(stcb, sp, SCTP_SO_NOT_LOCKED); /* sa_ignore FREED_MEMORY */ } + outs->state = SCTP_STREAM_CLOSED; } } /* cut back the count */ asoc->pre_open_streams = newcnt; } SCTP_TCB_SEND_UNLOCK(stcb); - asoc->strm_realoutsize = asoc->streamoutcnt = asoc->pre_open_streams; - + asoc->streamoutcnt = asoc->pre_open_streams; + for (i = 0; i < asoc->streamoutcnt; i++) { + asoc->strmout[i].state = SCTP_STREAM_OPEN; + } /* EY - nr_sack: initialize highest tsn in nr_mapping_array */ asoc->highest_tsn_inside_nr_map = asoc->highest_tsn_inside_map; if (SCTP_BASE_SYSCTL(sctp_logging_level) & SCTP_MAP_LOGGING_ENABLE) { @@ -3506,6 +3509,28 @@ sctp_reset_out_streams(struct sctp_tcb *stcb, uint32_t number_entries, uint16_t sctp_ulp_notify(SCTP_NOTIFY_STR_RESET_SEND, stcb, number_entries, (void *)list, SCTP_SO_NOT_LOCKED); } +static void +sctp_reset_clear_pending(struct sctp_tcb *stcb, uint32_t number_entries, uint16_t * list) +{ + uint32_t i; + uint16_t temp; + + if (number_entries > 0) { + for (i = 0; i < number_entries; i++) { + temp = ntohs(list[i]); + if (temp >= stcb->asoc.streamoutcnt) { + /* no such stream */ + continue; + } + stcb->asoc.strmout[temp].state = SCTP_STREAM_OPEN; + } + } else { + for (i = 0; i < stcb->asoc.streamoutcnt; i++) { + stcb->asoc.strmout[i].state = SCTP_STREAM_OPEN; + } + } +} + struct sctp_stream_reset_request * sctp_find_stream_reset(struct sctp_tcb *stcb, uint32_t seq, struct sctp_tmit_chunk **bchk) @@ -3604,6 +3629,8 @@ sctp_handle_stream_reset_response(struct sctp_tcb *stcb, type = ntohs(req_param->ph.param_type); lparm_len = ntohs(req_param->ph.param_length); if (type == SCTP_STR_RESET_OUT_REQUEST) { + int no_clear = 0; + req_out_param = (struct sctp_stream_reset_out_request *)req_param; number_entries = (lparm_len - sizeof(struct sctp_stream_reset_out_request)) / sizeof(uint16_t); asoc->stream_reset_out_is_outstanding = 0; @@ -3614,9 +3641,20 @@ sctp_handle_stream_reset_response(struct sctp_tcb *stcb, sctp_reset_out_streams(stcb, number_entries, req_out_param->list_of_streams); } else if (action == SCTP_STREAM_RESET_RESULT_DENIED) { sctp_ulp_notify(SCTP_NOTIFY_STR_RESET_DENIED_OUT, stcb, number_entries, req_out_param->list_of_streams, SCTP_SO_NOT_LOCKED); + } else if (action == SCTP_STREAM_RESET_RESULT_IN_PROGRESS) { + /* + * Set it up so we don't stop + * retransmitting + */ + stcb->asoc.str_reset_seq_out--; + asoc->stream_reset_out_is_outstanding = 1; + no_clear = 1; } else { sctp_ulp_notify(SCTP_NOTIFY_STR_RESET_FAILED_OUT, stcb, number_entries, req_out_param->list_of_streams, SCTP_SO_NOT_LOCKED); } + if (no_clear == 0) { + sctp_reset_clear_pending(stcb, number_entries, req_out_param->list_of_streams); + } } else if (type == SCTP_STR_RESET_IN_REQUEST) { req_in_param = (struct sctp_stream_reset_in_request *)req_param; number_entries = (lparm_len - sizeof(struct sctp_stream_reset_in_request)) / sizeof(uint16_t); @@ -3643,7 +3681,12 @@ sctp_handle_stream_reset_response(struct sctp_tcb *stcb, asoc->stream_reset_outstanding--; if (action == SCTP_STREAM_RESET_RESULT_PERFORMED) { /* Put the new streams into effect */ - stcb->asoc.streamoutcnt += num_stream; + int i; + + for (i = asoc->streamoutcnt; i < (asoc->streamoutcnt + num_stream); i++) { + asoc->strmout[i].state = SCTP_STREAM_OPEN; + } + asoc->streamoutcnt += num_stream; sctp_notify_stream_reset_add(stcb, stcb->asoc.streamincnt, stcb->asoc.streamoutcnt, 0); } else if (action == SCTP_STREAM_RESET_RESULT_DENIED) { sctp_notify_stream_reset_add(stcb, stcb->asoc.streamincnt, stcb->asoc.streamoutcnt, @@ -3720,6 +3763,9 @@ sctp_handle_stream_reset_response(struct sctp_tcb *stcb, } } } + if (asoc->stream_reset_outstanding == 0) { + sctp_send_stream_reset_out_if_possible(stcb); + } return (0); } @@ -3750,22 +3796,33 @@ sctp_handle_str_reset_request_in(struct sctp_tcb *stcb, } else if (stcb->asoc.stream_reset_out_is_outstanding == 0) { len = ntohs(req->ph.param_length); number_entries = ((len - sizeof(struct sctp_stream_reset_in_request)) / sizeof(uint16_t)); - for (i = 0; i < number_entries; i++) { - temp = ntohs(req->list_of_streams[i]); - req->list_of_streams[i] = temp; + if (number_entries) { + for (i = 0; i < number_entries; i++) { + temp = ntohs(req->list_of_streams[i]); + if (temp >= stcb->asoc.streamoutcnt) { + asoc->last_reset_action[0] = SCTP_STREAM_RESET_RESULT_DENIED; + goto bad_boy; + } + req->list_of_streams[i] = temp; + } + for (i = 0; i < number_entries; i++) { + if (stcb->asoc.strmout[req->list_of_streams[i]].state == SCTP_STREAM_OPEN) { + stcb->asoc.strmout[req->list_of_streams[i]].state = SCTP_STREAM_RESET_PENDING; + } + } + } else { + /* Its all */ + for (i = 0; i < stcb->asoc.streamoutcnt; i++) { + if (stcb->asoc.strmout[i].state == SCTP_STREAM_OPEN) + stcb->asoc.strmout[i].state = SCTP_STREAM_RESET_PENDING; + } } asoc->last_reset_action[0] = SCTP_STREAM_RESET_RESULT_PERFORMED; - sctp_add_stream_reset_out(chk, number_entries, req->list_of_streams, - asoc->str_reset_seq_out, - seq, (asoc->sending_seq - 1)); - asoc->stream_reset_out_is_outstanding = 1; - asoc->str_reset = chk; - sctp_timer_start(SCTP_TIMER_TYPE_STRRESET, stcb->sctp_ep, stcb, chk->whoTo); - stcb->asoc.stream_reset_outstanding++; } else { /* Can't do it, since we have sent one out */ asoc->last_reset_action[0] = SCTP_STREAM_RESET_RESULT_ERR_IN_PROGRESS; } +bad_boy: sctp_add_stream_reset_result(chk, seq, asoc->last_reset_action[0]); asoc->str_reset_seq_in++; } else if (asoc->str_reset_seq_in - 1 == seq) { @@ -3775,6 +3832,7 @@ sctp_handle_str_reset_request_in(struct sctp_tcb *stcb, } else { sctp_add_stream_reset_result(chk, seq, SCTP_STREAM_RESET_RESULT_ERR_BAD_SEQNO); } + sctp_send_stream_reset_out_if_possible(stcb); } static int @@ -3893,11 +3951,12 @@ sctp_handle_str_reset_request_out(struct sctp_tcb *stcb, sctp_add_stream_reset_result(chk, seq, asoc->last_reset_action[0]); return; } + liste->seq = seq; liste->tsn = tsn; liste->number_entries = number_entries; memcpy(&liste->list_of_streams, req->list_of_streams, number_entries * sizeof(uint16_t)); TAILQ_INSERT_TAIL(&asoc->resetHead, liste, next_resp); - asoc->last_reset_action[0] = SCTP_STREAM_RESET_RESULT_PERFORMED; + asoc->last_reset_action[0] = SCTP_STREAM_RESET_RESULT_IN_PROGRESS; } sctp_add_stream_reset_result(chk, seq, asoc->last_reset_action[0]); asoc->str_reset_seq_in++; @@ -4034,7 +4093,7 @@ sctp_handle_str_reset_add_out_strm(struct sctp_tcb *stcb, struct sctp_tmit_chunk mychk += num_stream; if (mychk < 0x10000) { stcb->asoc.last_reset_action[0] = SCTP_STREAM_RESET_RESULT_PERFORMED; - if (sctp_send_str_reset_req(stcb, 0, NULL, 0, 0, 0, 1, num_stream, 0, 1)) { + if (sctp_send_str_reset_req(stcb, 0, NULL, 0, 0, 1, num_stream, 0, 1)) { stcb->asoc.last_reset_action[0] = SCTP_STREAM_RESET_RESULT_DENIED; } } else { diff --git a/sys/netinet/sctp_output.c b/sys/netinet/sctp_output.c index 3ef837c03e1f..59f0e49360a2 100644 --- a/sys/netinet/sctp_output.c +++ b/sys/netinet/sctp_output.c @@ -7162,6 +7162,10 @@ one_more_time: } atomic_subtract_int(&asoc->stream_queue_cnt, 1); TAILQ_REMOVE(&strq->outqueue, sp, next); + if (strq->state == SCTP_STREAM_RESET_PENDING && + TAILQ_EMPTY(&strq->outqueue)) { + stcb->asoc.trigger_reset = 1; + } stcb->asoc.ss_functions.sctp_ss_remove_from_stream(stcb, asoc, strq, sp, send_lock_up); if (sp->net) { sctp_free_remote_addr(sp->net); @@ -7560,6 +7564,10 @@ dont_do_it: send_lock_up = 1; } TAILQ_REMOVE(&strq->outqueue, sp, next); + if (strq->state == SCTP_STREAM_RESET_PENDING && + TAILQ_EMPTY(&strq->outqueue)) { + stcb->asoc.trigger_reset = 1; + } stcb->asoc.ss_functions.sctp_ss_remove_from_stream(stcb, asoc, strq, sp, send_lock_up); if (sp->net) { sctp_free_remote_addr(sp->net); @@ -7787,7 +7795,7 @@ sctp_med_chunk_output(struct sctp_inpcb *inp, #endif SCTP_TCB_LOCK_ASSERT(stcb); hbflag = 0; - if ((control_only) || (asoc->stream_reset_outstanding)) + if (control_only) no_data_chunks = 1; else no_data_chunks = 0; @@ -9856,7 +9864,9 @@ sctp_chunk_output(struct sctp_inpcb *inp, unsigned int tot_frs = 0; asoc = &stcb->asoc; +do_it_again: /* The Nagle algorithm is only applied when handling a send call. */ + stcb->asoc.trigger_reset = 0; if (from_where == SCTP_OUTPUT_FROM_USR_SEND) { if (sctp_is_feature_on(inp, SCTP_PCB_FLAGS_NODELAY)) { nagle_on = 0; @@ -10092,6 +10102,12 @@ sctp_chunk_output(struct sctp_inpcb *inp, */ if (stcb->asoc.ecn_echo_cnt_onq) sctp_fix_ecn_echo(asoc); + + if (stcb->asoc.trigger_reset) { + if (sctp_send_stream_reset_out_if_possible(stcb) == 0) { + goto do_it_again; + } + } return; } @@ -11494,30 +11510,58 @@ sctp_send_cwr(struct sctp_tcb *stcb, struct sctp_nets *net, uint32_t high_tsn, u asoc->ctrl_queue_cnt++; } -void -sctp_add_stream_reset_out(struct sctp_tmit_chunk *chk, - int number_entries, uint16_t * list, +static int +sctp_add_stream_reset_out(struct sctp_tcb *stcb, struct sctp_tmit_chunk *chk, uint32_t seq, uint32_t resp_seq, uint32_t last_sent) { uint16_t len, old_len, i; struct sctp_stream_reset_out_request *req_out; struct sctp_chunkhdr *ch; + int at; + int number_entries = 0; ch = mtod(chk->data, struct sctp_chunkhdr *); old_len = len = SCTP_SIZE32(ntohs(ch->chunk_length)); - /* get to new offset for the param. */ req_out = (struct sctp_stream_reset_out_request *)((caddr_t)ch + len); /* now how long will this param be? */ + for (i = 0; i < stcb->asoc.streamoutcnt; i++) { + if ((stcb->asoc.strmout[i].state == SCTP_STREAM_RESET_PENDING) && + (TAILQ_EMPTY(&stcb->asoc.strmout[i].outqueue))) { + number_entries++; + } + } + if (number_entries == 0) { + return (0); + } + if (number_entries == stcb->asoc.streamoutcnt) { + number_entries = 0; + } + if (number_entries > SCTP_MAX_STREAMS_AT_ONCE_RESET) { + number_entries = SCTP_MAX_STREAMS_AT_ONCE_RESET; + } len = (sizeof(struct sctp_stream_reset_out_request) + (sizeof(uint16_t) * number_entries)); req_out->ph.param_type = htons(SCTP_STR_RESET_OUT_REQUEST); req_out->ph.param_length = htons(len); req_out->request_seq = htonl(seq); req_out->response_seq = htonl(resp_seq); req_out->send_reset_at_tsn = htonl(last_sent); + at = 0; if (number_entries) { - for (i = 0; i < number_entries; i++) { - req_out->list_of_streams[i] = htons(list[i]); + for (i = 0; i < stcb->asoc.streamoutcnt; i++) { + if ((stcb->asoc.strmout[i].state == SCTP_STREAM_RESET_PENDING) && + (TAILQ_EMPTY(&stcb->asoc.strmout[i].outqueue))) { + req_out->list_of_streams[at] = htons(i); + at++; + stcb->asoc.strmout[i].state = SCTP_STREAM_RESET_IN_FLIGHT; + if (at >= number_entries) { + break; + } + } + } + } else { + for (i = 0; i < stcb->asoc.streamoutcnt; i++) { + stcb->asoc.strmout[i].state = SCTP_STREAM_RESET_IN_FLIGHT; } } if (SCTP_SIZE32(len) > len) { @@ -11534,7 +11578,7 @@ sctp_add_stream_reset_out(struct sctp_tmit_chunk *chk, chk->book_size_scale = 0; chk->send_size = SCTP_SIZE32(chk->book_size); SCTP_BUF_LEN(chk->data) = chk->send_size; - return; + return (1); } static void @@ -11635,6 +11679,68 @@ sctp_add_stream_reset_result(struct sctp_tmit_chunk *chk, return; } +void +sctp_send_deferred_reset_response(struct sctp_tcb *stcb, + struct sctp_stream_reset_list *ent, + int response) +{ + struct sctp_association *asoc; + struct sctp_tmit_chunk *chk; + struct sctp_chunkhdr *ch; + + asoc = &stcb->asoc; + + /* + * Reset our last reset action to the new one IP -> response + * (PERFORMED probably). This assures that if we fail to send, a + * retran from the peer will get the new response. + */ + asoc->last_reset_action[0] = response; + if (asoc->stream_reset_outstanding) { + return; + } + sctp_alloc_a_chunk(stcb, chk); + if (chk == NULL) { + SCTP_LTRACE_ERR_RET(NULL, stcb, NULL, SCTP_FROM_SCTP_OUTPUT, ENOMEM); + return; + } + chk->copy_by_ref = 0; + chk->rec.chunk_id.id = SCTP_STREAM_RESET; + chk->rec.chunk_id.can_take_data = 0; + chk->flags = 0; + chk->asoc = &stcb->asoc; + chk->book_size = sizeof(struct sctp_chunkhdr); + chk->send_size = SCTP_SIZE32(chk->book_size); + chk->book_size_scale = 0; + chk->data = sctp_get_mbuf_for_msg(MCLBYTES, 0, M_NOWAIT, 1, MT_DATA); + if (chk->data == NULL) { + sctp_free_a_chunk(stcb, chk, SCTP_SO_LOCKED); + SCTP_LTRACE_ERR_RET(NULL, stcb, NULL, SCTP_FROM_SCTP_OUTPUT, ENOMEM); + return; + } + SCTP_BUF_RESV_UF(chk->data, SCTP_MIN_OVERHEAD); + sctp_add_stream_reset_result(chk, ent->seq, response); + /* setup chunk parameters */ + chk->sent = SCTP_DATAGRAM_UNSENT; + chk->snd_count = 0; + if (stcb->asoc.alternate) { + chk->whoTo = stcb->asoc.alternate; + } else { + chk->whoTo = stcb->asoc.primary_destination; + } + ch = mtod(chk->data, struct sctp_chunkhdr *); + ch->chunk_type = SCTP_STREAM_RESET; + ch->chunk_flags = 0; + ch->chunk_length = htons(chk->book_size); + atomic_add_int(&chk->whoTo->ref_count, 1); + SCTP_BUF_LEN(chk->data) = chk->send_size; + /* insert the chunk for sending */ + TAILQ_INSERT_TAIL(&asoc->control_send_queue, + chk, + sctp_next); + asoc->ctrl_queue_cnt++; +} + void sctp_add_stream_reset_result_tsn(struct sctp_tmit_chunk *chk, uint32_t resp_seq, uint32_t result, @@ -11732,20 +11838,86 @@ sctp_add_an_in_stream(struct sctp_tmit_chunk *chk, return; } +int +sctp_send_stream_reset_out_if_possible(struct sctp_tcb *stcb) +{ + struct sctp_association *asoc; + struct sctp_tmit_chunk *chk; + struct sctp_chunkhdr *ch; + uint32_t seq; + + asoc = &stcb->asoc; + if (asoc->stream_reset_outstanding) { + return (EALREADY); + } + sctp_alloc_a_chunk(stcb, chk); + if (chk == NULL) { + SCTP_LTRACE_ERR_RET(NULL, stcb, NULL, SCTP_FROM_SCTP_OUTPUT, ENOMEM); + return (ENOMEM); + } + chk->copy_by_ref = 0; + chk->rec.chunk_id.id = SCTP_STREAM_RESET; + chk->rec.chunk_id.can_take_data = 0; + chk->flags = 0; + chk->asoc = &stcb->asoc; + chk->book_size = sizeof(struct sctp_chunkhdr); + chk->send_size = SCTP_SIZE32(chk->book_size); + chk->book_size_scale = 0; + chk->data = sctp_get_mbuf_for_msg(MCLBYTES, 0, M_NOWAIT, 1, MT_DATA); + if (chk->data == NULL) { + sctp_free_a_chunk(stcb, chk, SCTP_SO_LOCKED); + SCTP_LTRACE_ERR_RET(NULL, stcb, NULL, SCTP_FROM_SCTP_OUTPUT, ENOMEM); + return (ENOMEM); + } + SCTP_BUF_RESV_UF(chk->data, SCTP_MIN_OVERHEAD); + + /* setup chunk parameters */ + chk->sent = SCTP_DATAGRAM_UNSENT; + chk->snd_count = 0; + if (stcb->asoc.alternate) { + chk->whoTo = stcb->asoc.alternate; + } else { + chk->whoTo = stcb->asoc.primary_destination; + } + ch = mtod(chk->data, struct sctp_chunkhdr *); + ch->chunk_type = SCTP_STREAM_RESET; + ch->chunk_flags = 0; + ch->chunk_length = htons(chk->book_size); + atomic_add_int(&chk->whoTo->ref_count, 1); + SCTP_BUF_LEN(chk->data) = chk->send_size; + seq = stcb->asoc.str_reset_seq_out; + if (sctp_add_stream_reset_out(stcb, chk, seq, (stcb->asoc.str_reset_seq_in - 1), (stcb->asoc.sending_seq - 1))) { + seq++; + asoc->stream_reset_outstanding++; + } else { + m_freem(chk->data); + chk->data = NULL; + sctp_free_a_chunk(stcb, chk, SCTP_SO_LOCKED); + return (ENOENT); + } + asoc->str_reset = chk; + /* insert the chunk for sending */ + TAILQ_INSERT_TAIL(&asoc->control_send_queue, + chk, + sctp_next); + asoc->ctrl_queue_cnt++; + sctp_timer_start(SCTP_TIMER_TYPE_STRRESET, stcb->sctp_ep, stcb, chk->whoTo); + return (0); +} + int sctp_send_str_reset_req(struct sctp_tcb *stcb, uint16_t number_entries, uint16_t * list, - uint8_t send_out_req, uint8_t send_in_req, uint8_t send_tsn_req, uint8_t add_stream, uint16_t adding_o, uint16_t adding_i, uint8_t peer_asked) { - struct sctp_association *asoc; struct sctp_tmit_chunk *chk; struct sctp_chunkhdr *ch; + int can_send_out_req = 0; uint32_t seq; asoc = &stcb->asoc; @@ -11756,16 +11928,18 @@ sctp_send_str_reset_req(struct sctp_tcb *stcb, SCTP_LTRACE_ERR_RET(NULL, stcb, NULL, SCTP_FROM_SCTP_OUTPUT, EBUSY); return (EBUSY); } - if ((send_out_req == 0) && (send_in_req == 0) && (send_tsn_req == 0) && + if ((send_in_req == 0) && (send_tsn_req == 0) && (add_stream == 0)) { /* nothing to do */ SCTP_LTRACE_ERR_RET(NULL, stcb, NULL, SCTP_FROM_SCTP_OUTPUT, EINVAL); return (EINVAL); } - if (send_tsn_req && (send_out_req || send_in_req)) { + if (send_tsn_req && send_in_req) { /* error, can't do that */ SCTP_LTRACE_ERR_RET(NULL, stcb, NULL, SCTP_FROM_SCTP_OUTPUT, EINVAL); return (EINVAL); + } else if (send_in_req) { + can_send_out_req = 1; } if (number_entries > (MCLBYTES - SCTP_MIN_OVERHEAD - @@ -11813,12 +11987,14 @@ sctp_send_str_reset_req(struct sctp_tcb *stcb, SCTP_BUF_LEN(chk->data) = chk->send_size; seq = stcb->asoc.str_reset_seq_out; - if (send_out_req) { - sctp_add_stream_reset_out(chk, number_entries, list, - seq, (stcb->asoc.str_reset_seq_in - 1), (stcb->asoc.sending_seq - 1)); - asoc->stream_reset_out_is_outstanding = 1; - seq++; - asoc->stream_reset_outstanding++; + if (can_send_out_req) { + int ret; + + ret = sctp_add_stream_reset_out(stcb, chk, seq, (stcb->asoc.str_reset_seq_in - 1), (stcb->asoc.sending_seq - 1)); + if (ret) { + seq++; + asoc->stream_reset_outstanding++; + } } if ((add_stream & 1) && ((stcb->asoc.strm_realoutsize - stcb->asoc.streamoutcnt) < adding_o)) { @@ -11858,6 +12034,7 @@ sctp_send_str_reset_req(struct sctp_tcb *stcb, stcb->asoc.strmout[i].next_sequence_send = oldstream[i].next_sequence_send; stcb->asoc.strmout[i].last_msg_incomplete = oldstream[i].last_msg_incomplete; stcb->asoc.strmout[i].stream_no = i; + stcb->asoc.strmout[i].state = oldstream[i].state; stcb->asoc.ss_functions.sctp_ss_init_stream(&stcb->asoc.strmout[i], &oldstream[i]); /* now anything on those queues? */ TAILQ_FOREACH_SAFE(sp, &oldstream[i].outqueue, next, nsp) { @@ -11890,6 +12067,7 @@ sctp_send_str_reset_req(struct sctp_tcb *stcb, stcb->asoc.strmout[i].stream_no = i; stcb->asoc.strmout[i].last_msg_incomplete = 0; stcb->asoc.ss_functions.sctp_ss_init_stream(&stcb->asoc.strmout[i], NULL); + stcb->asoc.strmout[i].state = SCTP_STREAM_CLOSED; } stcb->asoc.strm_realoutsize = stcb->asoc.streamoutcnt + adding_o; SCTP_FREE(oldstream, SCTP_M_STRMO); @@ -12499,12 +12677,24 @@ sctp_lower_sosend(struct socket *so, SCTP_ASOC_CREATE_UNLOCK(inp); create_lock_applied = 0; } - if (asoc->stream_reset_outstanding) { + /* Is the stream no. valid? */ + if (srcv->sinfo_stream >= asoc->streamoutcnt) { + /* Invalid stream number */ + SCTP_LTRACE_ERR_RET(inp, stcb, net, SCTP_FROM_SCTP_OUTPUT, EINVAL); + error = EINVAL; + goto out_unlocked; + } + if ((asoc->strmout[srcv->sinfo_stream].state != SCTP_STREAM_OPEN) && + (asoc->strmout[srcv->sinfo_stream].state != SCTP_STREAM_OPENING)) { /* * Can't queue any data while stream reset is underway. */ - SCTP_LTRACE_ERR_RET(inp, stcb, net, SCTP_FROM_SCTP_OUTPUT, EAGAIN); - error = EAGAIN; + if (asoc->strmout[srcv->sinfo_stream].state > SCTP_STREAM_OPEN) { + error = EAGAIN; + } else { + error = EINVAL; + } + SCTP_LTRACE_ERR_RET(inp, stcb, net, SCTP_FROM_SCTP_OUTPUT, error); goto out_unlocked; } if ((SCTP_GET_STATE(asoc) == SCTP_STATE_COOKIE_WAIT) || @@ -12643,13 +12833,6 @@ sctp_lower_sosend(struct socket *so, SCTP_TCB_UNLOCK(stcb); hold_tcblock = 0; } - /* Is the stream no. valid? */ - if (srcv->sinfo_stream >= asoc->streamoutcnt) { - /* Invalid stream number */ - SCTP_LTRACE_ERR_RET(inp, stcb, net, SCTP_FROM_SCTP_OUTPUT, EINVAL); - error = EINVAL; - goto out_unlocked; - } if (asoc->strmout == NULL) { /* huh? software error */ SCTP_LTRACE_ERR_RET(inp, stcb, net, SCTP_FROM_SCTP_OUTPUT, EFAULT); @@ -12945,7 +13128,7 @@ skip_preblock: /*- * Ok, Nagle is set on and we have data outstanding. * Don't send anything and let SACKs drive out the - * data unless wen have a "full" segment to send. + * data unless we have a "full" segment to send. */ if (SCTP_BASE_SYSCTL(sctp_logging_level) & SCTP_NAGLE_LOGGING_ENABLE) { sctp_log_nagle_event(stcb, SCTP_NAGLE_APPLIED); diff --git a/sys/netinet/sctp_output.h b/sys/netinet/sctp_output.h index 8e45e5cbfdc1..8fd5659c5c8a 100644 --- a/sys/netinet/sctp_output.h +++ b/sys/netinet/sctp_output.h @@ -170,18 +170,21 @@ void sctp_send_cwr(struct sctp_tcb *, struct sctp_nets *, uint32_t, uint8_t); void -sctp_add_stream_reset_out(struct sctp_tmit_chunk *, - int, uint16_t *, uint32_t, uint32_t, uint32_t); + sctp_add_stream_reset_result(struct sctp_tmit_chunk *, uint32_t, uint32_t); void - sctp_add_stream_reset_result(struct sctp_tmit_chunk *, uint32_t, uint32_t); +sctp_send_deferred_reset_response(struct sctp_tcb *, + struct sctp_stream_reset_list *, + int); void sctp_add_stream_reset_result_tsn(struct sctp_tmit_chunk *, uint32_t, uint32_t, uint32_t, uint32_t); +int + sctp_send_stream_reset_out_if_possible(struct sctp_tcb *); int -sctp_send_str_reset_req(struct sctp_tcb *, uint16_t, uint16_t *, uint8_t, +sctp_send_str_reset_req(struct sctp_tcb *, uint16_t, uint16_t *, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t, uint8_t); void diff --git a/sys/netinet/sctp_structs.h b/sys/netinet/sctp_structs.h index 8f61cd7b19db..eda99fe7d5d8 100644 --- a/sys/netinet/sctp_structs.h +++ b/sys/netinet/sctp_structs.h @@ -76,6 +76,7 @@ TAILQ_HEAD(sctpnetlisthead, sctp_nets); struct sctp_stream_reset_list { TAILQ_ENTRY(sctp_stream_reset_list) next_resp; + uint32_t seq; uint32_t tsn; uint32_t number_entries; uint16_t list_of_streams[]; @@ -580,11 +581,20 @@ union scheduling_parameters { struct ss_fb fb; }; +/* States for outgoing streams */ +#define SCTP_STREAM_CLOSED 0x00 +#define SCTP_STREAM_OPENING 0x01 +#define SCTP_STREAM_OPEN 0x02 +#define SCTP_STREAM_RESET_PENDING 0x03 +#define SCTP_STREAM_RESET_IN_FLIGHT 0x04 + +#define SCTP_MAX_STREAMS_AT_ONCE_RESET 200 + /* This struct is used to track the traffic on outbound streams */ struct sctp_stream_out { struct sctp_streamhead outqueue; union scheduling_parameters ss_params; - uint32_t chunks_on_queues; + uint32_t chunks_on_queues; /* send queue and sent queue */ #if defined(SCTP_DETAILED_STR_STATS) uint32_t abandoned_unsent[SCTP_PR_SCTP_MAX + 1]; uint32_t abandoned_sent[SCTP_PR_SCTP_MAX + 1]; @@ -596,6 +606,7 @@ struct sctp_stream_out { uint16_t stream_no; uint16_t next_sequence_send; /* next one I expect to send out */ uint8_t last_msg_incomplete; + uint8_t state; }; /* used to keep track of the addresses yet to try to add/delete */ @@ -1148,7 +1159,7 @@ struct sctp_association { uint8_t hb_random_idx; uint8_t default_dscp; uint8_t asconf_del_pending; /* asconf delete last addr pending */ - + uint8_t trigger_reset; /* * This value, plus all other ack'd but above cum-ack is added * together to cross check against the bit that we have yet to diff --git a/sys/netinet/sctp_usrreq.c b/sys/netinet/sctp_usrreq.c index 907412cd6e8a..53a0a0adc5f7 100644 --- a/sys/netinet/sctp_usrreq.c +++ b/sys/netinet/sctp_usrreq.c @@ -4620,18 +4620,24 @@ sctp_setopt(struct socket *so, int optname, void *optval, size_t optsize, SCTP_TCB_UNLOCK(stcb); break; } - if (stcb->asoc.stream_reset_outstanding) { - SCTP_LTRACE_ERR_RET(inp, NULL, NULL, SCTP_FROM_SCTP_USRREQ, EALREADY); - error = EALREADY; - SCTP_TCB_UNLOCK(stcb); - break; - } if (strrst->srs_flags & SCTP_STREAM_RESET_INCOMING) { send_in = 1; + if (stcb->asoc.stream_reset_outstanding) { + SCTP_LTRACE_ERR_RET(inp, NULL, NULL, SCTP_FROM_SCTP_USRREQ, EALREADY); + error = EALREADY; + SCTP_TCB_UNLOCK(stcb); + break; + } } if (strrst->srs_flags & SCTP_STREAM_RESET_OUTGOING) { send_out = 1; } + if ((strrst->srs_number_streams > SCTP_MAX_STREAMS_AT_ONCE_RESET) && send_in) { + SCTP_LTRACE_ERR_RET(inp, NULL, NULL, SCTP_FROM_SCTP_USRREQ, ENOMEM); + error = ENOMEM; + SCTP_TCB_UNLOCK(stcb); + break; + } if ((send_in == 0) && (send_out == 0)) { SCTP_LTRACE_ERR_RET(inp, NULL, NULL, SCTP_FROM_SCTP_USRREQ, EINVAL); error = EINVAL; @@ -4656,11 +4662,38 @@ sctp_setopt(struct socket *so, int optname, void *optval, size_t optsize, SCTP_TCB_UNLOCK(stcb); break; } - error = sctp_send_str_reset_req(stcb, strrst->srs_number_streams, - strrst->srs_stream_list, - send_out, send_in, 0, 0, 0, 0, 0); + if (send_out) { + int cnt; + uint16_t strm; + + if (strrst->srs_number_streams) { + for (i = 0, cnt = 0; i < strrst->srs_number_streams; i++) { + strm = strrst->srs_stream_list[i]; + if (stcb->asoc.strmout[strm].state == SCTP_STREAM_OPEN) { + stcb->asoc.strmout[strm].state = SCTP_STREAM_RESET_PENDING; + cnt++; + } + } + } else { + /* Its all */ + for (i = 0, cnt = 0; i < stcb->asoc.streamoutcnt; i++) { + if (stcb->asoc.strmout[i].state == SCTP_STREAM_OPEN) { + stcb->asoc.strmout[i].state = SCTP_STREAM_RESET_PENDING; + cnt++; + } + } + } + } + if (send_in) { + error = sctp_send_str_reset_req(stcb, strrst->srs_number_streams, + strrst->srs_stream_list, + send_in, 0, 0, 0, 0, 0); + } else + error = sctp_send_stream_reset_out_if_possible(stcb); + + if (!error) + sctp_chunk_output(inp, stcb, SCTP_OUTPUT_FROM_STRRST_REQ, SCTP_SO_LOCKED); - sctp_chunk_output(inp, stcb, SCTP_OUTPUT_FROM_STRRST_REQ, SCTP_SO_LOCKED); SCTP_TCB_UNLOCK(stcb); break; } @@ -4730,7 +4763,7 @@ sctp_setopt(struct socket *so, int optname, void *optval, size_t optsize, goto skip_stuff; } } - error = sctp_send_str_reset_req(stcb, 0, NULL, 0, 0, 0, addstream, add_o_strmcnt, add_i_strmcnt, 0); + error = sctp_send_str_reset_req(stcb, 0, NULL, 0, 0, addstream, add_o_strmcnt, add_i_strmcnt, 0); sctp_chunk_output(inp, stcb, SCTP_OUTPUT_FROM_STRRST_REQ, SCTP_SO_LOCKED); skip_stuff: SCTP_TCB_UNLOCK(stcb); @@ -4738,6 +4771,7 @@ sctp_setopt(struct socket *so, int optname, void *optval, size_t optsize, } case SCTP_RESET_ASSOC: { + int i; uint32_t *value; SCTP_CHECK_AND_CAST(value, optval, uint32_t, optsize); @@ -4762,7 +4796,25 @@ sctp_setopt(struct socket *so, int optname, void *optval, size_t optsize, SCTP_TCB_UNLOCK(stcb); break; } - error = sctp_send_str_reset_req(stcb, 0, NULL, 0, 0, 1, 0, 0, 0, 0); + /* + * Is there any data pending in the send or sent + * queues? + */ + if (!TAILQ_EMPTY(&stcb->asoc.send_queue) || + !TAILQ_EMPTY(&stcb->asoc.sent_queue)) { + busy_out: + error = EBUSY; + SCTP_LTRACE_ERR_RET(inp, NULL, NULL, SCTP_FROM_SCTP_USRREQ, error); + SCTP_TCB_UNLOCK(stcb); + break; + } + /* Do any streams have data queued? */ + for (i = 0; i < stcb->asoc.streamoutcnt; i++) { + if (!TAILQ_EMPTY(&stcb->asoc.strmout[i].outqueue)) { + goto busy_out; + } + } + error = sctp_send_str_reset_req(stcb, 0, NULL, 0, 1, 0, 0, 0, 0); sctp_chunk_output(inp, stcb, SCTP_OUTPUT_FROM_STRRST_REQ, SCTP_SO_LOCKED); SCTP_TCB_UNLOCK(stcb); break; diff --git a/sys/netinet/sctputil.c b/sys/netinet/sctputil.c index c25ec397f2e8..b613992fb5ae 100644 --- a/sys/netinet/sctputil.c +++ b/sys/netinet/sctputil.c @@ -1089,6 +1089,7 @@ sctp_init_asoc(struct sctp_inpcb *inp, struct sctp_tcb *stcb, #endif asoc->strmout[i].stream_no = i; asoc->strmout[i].last_msg_incomplete = 0; + asoc->strmout[i].state = SCTP_STREAM_OPENING; asoc->ss_functions.sctp_ss_init_stream(&asoc->strmout[i], NULL); } asoc->ss_functions.sctp_ss_init(stcb, asoc, 0); @@ -6855,7 +6856,7 @@ sctp_log_trace(uint32_t subsys, const char *str SCTP_UNUSED, uint32_t a, uint32_ #endif static void -sctp_recv_udp_tunneled_packet(struct mbuf *m, int off, struct inpcb *ignored, +sctp_recv_udp_tunneled_packet(struct mbuf *m, int off, struct inpcb *inp, const struct sockaddr *sa SCTP_UNUSED, void *ctx SCTP_UNUSED) { struct ip *iph; diff --git a/sys/netinet/tcp_input.c b/sys/netinet/tcp_input.c index aaf227c50a22..9454a6565b03 100644 --- a/sys/netinet/tcp_input.c +++ b/sys/netinet/tcp_input.c @@ -1856,6 +1856,7 @@ tcp_do_segment(struct mbuf *m, struct tcphdr *th, struct socket *so, * the buffer to better manage the socket buffer resources. */ if (V_tcp_do_autorcvbuf && + (to.to_flags & TOF_TS) && to.to_tsecr && (so->so_rcv.sb_flags & SB_AUTOSIZE)) { if (TSTMP_GT(to.to_tsecr, tp->rfbuf_ts) && diff --git a/sys/netinet/tcp_output.c b/sys/netinet/tcp_output.c index 111f22e2edda..9413721624cb 100644 --- a/sys/netinet/tcp_output.c +++ b/sys/netinet/tcp_output.c @@ -400,7 +400,7 @@ after_sack_rexmit: flags &= ~TH_FIN; } - if (len < 0) { + if (len <= 0) { /* * If FIN has been sent but not acked, * but we haven't been called to retransmit, @@ -410,9 +410,16 @@ after_sack_rexmit: * to (closed) window, and set the persist timer * if it isn't already going. If the window didn't * close completely, just wait for an ACK. + * + * We also do a general check here to ensure that + * we will set the persist timer when we have data + * to send, but a 0-byte window. This makes sure + * the persist timer is set even if the packet + * hits one of the "goto send" lines below. */ len = 0; - if (sendwin == 0) { + if ((sendwin == 0) && (TCPS_HAVEESTABLISHED(tp->t_state)) && + (off < (int) sbavail(&so->so_snd))) { tcp_timer_activate(tp, TT_REXMT, 0); tp->t_rxtshift = 0; tp->snd_nxt = tp->snd_una; diff --git a/sys/netinet/udp_usrreq.c b/sys/netinet/udp_usrreq.c index d13821fbb5c3..7c57e6b1ee47 100644 --- a/sys/netinet/udp_usrreq.c +++ b/sys/netinet/udp_usrreq.c @@ -293,8 +293,17 @@ udplite_destroy(void) * contains the source address. If the socket ends up being an IPv6 socket, * udp_append() will convert to a sockaddr_in6 before passing the address * into the socket code. + * + * In the normal case udp_append() will return 0, indicating that you + * must unlock the inp. However if a tunneling protocol is in place we increment + * the inpcb refcnt and unlock the inp, on return from the tunneling protocol we + * then decrement the reference count. If the inp_rele returns 1, indicating the + * inp is gone, we return that to the caller to tell them *not* to unlock + * the inp. In the case of multi-cast this will cause the distribution + * to stop (though most tunneling protocols known currently do *not* use + * multicast). */ -static void +static int udp_append(struct inpcb *inp, struct ip *ip, struct mbuf *n, int off, struct sockaddr_in *udp_in) { @@ -313,9 +322,12 @@ udp_append(struct inpcb *inp, struct ip *ip, struct mbuf *n, int off, */ up = intoudpcb(inp); if (up->u_tun_func != NULL) { + in_pcbref(inp); + INP_RUNLOCK(inp); (*up->u_tun_func)(n, off, inp, (struct sockaddr *)udp_in, up->u_tun_ctx); - return; + INP_RLOCK(inp); + return (in_pcbrele_rlocked(inp)); } off += sizeof(struct udphdr); @@ -324,7 +336,7 @@ udp_append(struct inpcb *inp, struct ip *ip, struct mbuf *n, int off, /* Check AH/ESP integrity. */ if (ipsec4_in_reject(n, inp)) { m_freem(n); - return; + return (0); } #ifdef IPSEC_NAT_T up = intoudpcb(inp); @@ -332,14 +344,14 @@ udp_append(struct inpcb *inp, struct ip *ip, struct mbuf *n, int off, if (up->u_flags & UF_ESPINUDP_ALL) { /* IPSec UDP encaps. */ n = udp4_espdecap(inp, n, off); if (n == NULL) /* Consumed. */ - return; + return (0); } #endif /* IPSEC_NAT_T */ #endif /* IPSEC */ #ifdef MAC if (mac_inpcb_check_deliver(inp, n) != 0) { m_freem(n); - return; + return (0); } #endif /* MAC */ if (inp->inp_flags & INP_CONTROLOPTS || @@ -373,6 +385,7 @@ udp_append(struct inpcb *inp, struct ip *ip, struct mbuf *n, int off, UDPSTAT_INC(udps_fullsock); } else sorwakeup_locked(so); + return (0); } int @@ -579,8 +592,10 @@ udp_input(struct mbuf **mp, int *offp, int proto) if ((n = m_copy(m, 0, M_COPYALL)) != NULL) { UDP_PROBE(receive, NULL, last, ip, last, uh); - udp_append(last, ip, n, iphlen, - &udp_in); + if (udp_append(last, ip, n, iphlen, + &udp_in)) { + goto inp_lost; + } } INP_RUNLOCK(last); } @@ -611,8 +626,9 @@ udp_input(struct mbuf **mp, int *offp, int proto) goto badunlocked; } UDP_PROBE(receive, NULL, last, ip, last, uh); - udp_append(last, ip, m, iphlen, &udp_in); - INP_RUNLOCK(last); + if (udp_append(last, ip, m, iphlen, &udp_in) == 0) + INP_RUNLOCK(last); + inp_lost: INP_INFO_RUNLOCK(pcbinfo); return (IPPROTO_DONE); } @@ -700,8 +716,8 @@ udp_input(struct mbuf **mp, int *offp, int proto) } UDP_PROBE(receive, NULL, inp, ip, inp, uh); - udp_append(inp, ip, m, iphlen, &udp_in); - INP_RUNLOCK(inp); + if (udp_append(inp, ip, m, iphlen, &udp_in) == 0) + INP_RUNLOCK(inp); return (IPPROTO_DONE); badunlocked: @@ -1650,7 +1666,8 @@ udp4_espdecap(struct inpcb *inp, struct mbuf *m, int off) if (m->m_pkthdr.csum_flags & CSUM_DATA_VALID) m->m_pkthdr.csum_flags &= ~(CSUM_DATA_VALID|CSUM_PSEUDO_HDR); - (void) ipsec4_common_input(m, iphlen, ip->ip_p); + (void) ipsec_common_input(m, iphlen, offsetof(struct ip, ip_p), + AF_INET, ip->ip_p); return (NULL); /* NB: consumed, bypass processing. */ } #endif /* defined(IPSEC) && defined(IPSEC_NAT_T) */ diff --git a/sys/netinet6/in6.c b/sys/netinet6/in6.c index fe98f0c8c51c..4340150a7f14 100644 --- a/sys/netinet6/in6.c +++ b/sys/netinet6/in6.c @@ -2203,6 +2203,7 @@ in6_lltable_lookup(struct lltable *llt, u_int flags, if (!(lle->la_flags & LLE_IFADDR) || (flags & LLE_IFADDR)) { LLE_WLOCK(lle); lle->la_flags |= LLE_DELETED; + EVENTHANDLER_INVOKE(lle_event, lle, LLENTRY_DELETED); #ifdef DIAGNOSTIC log(LOG_INFO, "ifaddr cache = %p is deleted\n", lle); #endif diff --git a/sys/netinet6/nd6.c b/sys/netinet6/nd6.c index daac188f5812..bcb2d0bf941d 100644 --- a/sys/netinet6/nd6.c +++ b/sys/netinet6/nd6.c @@ -112,6 +112,8 @@ VNET_DEFINE(int, nd6_debug) = 1; VNET_DEFINE(int, nd6_debug) = 0; #endif +static eventhandler_tag lle_event_eh; + /* for debugging? */ #if 0 static int nd6_inuse, nd6_allocated; @@ -144,6 +146,58 @@ static VNET_DEFINE(struct callout, nd6_slowtimo_ch); VNET_DEFINE(struct callout, nd6_timer_ch); +static void +nd6_lle_event(void *arg __unused, struct llentry *lle, int evt) +{ + struct rt_addrinfo rtinfo; + struct sockaddr_in6 dst, *sa6; + struct sockaddr_dl gw; + struct ifnet *ifp; + int type; + + LLE_WLOCK_ASSERT(lle); + + switch (evt) { + case LLENTRY_RESOLVED: + type = RTM_ADD; + KASSERT(lle->la_flags & LLE_VALID, + ("%s: %p resolved but not valid?", __func__, lle)); + break; + case LLENTRY_EXPIRED: + type = RTM_DELETE; + break; + default: + return; + } + + sa6 = L3_ADDR_SIN6(lle); + if (sa6->sin6_family != AF_INET6) + return; + ifp = lle->lle_tbl->llt_ifp; + + bzero(&dst, sizeof(dst)); + bzero(&gw, sizeof(gw)); + bzero(&rtinfo, sizeof(rtinfo)); + dst.sin6_len = sizeof(struct sockaddr_in6); + dst.sin6_family = AF_INET6; + dst.sin6_addr = sa6->sin6_addr; + dst.sin6_scope_id = in6_getscopezone(ifp, + in6_addrscope(&sa6->sin6_addr)); + in6_clearscope(&dst.sin6_addr); /* XXX */ + gw.sdl_len = sizeof(struct sockaddr_dl); + gw.sdl_family = AF_LINK; + gw.sdl_alen = ifp->if_addrlen; + gw.sdl_index = ifp->if_index; + gw.sdl_type = ifp->if_type; + if (evt == LLENTRY_RESOLVED) + bcopy(&lle->ll_addr, gw.sdl_data, ifp->if_addrlen); + rtinfo.rti_info[RTAX_DST] = (struct sockaddr *)&dst; + rtinfo.rti_info[RTAX_GATEWAY] = (struct sockaddr *)&gw; + rtinfo.rti_addrs = RTA_DST | RTA_GATEWAY; + rt_missmsg_fib(type, &rtinfo, RTF_HOST | RTF_LLDATA | ( + type == RTM_ADD ? RTF_UP: 0), 0, RT_DEFAULT_FIB); +} + void nd6_init(void) { @@ -159,6 +213,9 @@ nd6_init(void) nd6_slowtimo, curvnet); nd6_dad_init(); + if (IS_DEFAULT_VNET(curvnet)) + lle_event_eh = EVENTHANDLER_REGISTER(lle_event, nd6_lle_event, + NULL, EVENTHANDLER_PRI_ANY); } #ifdef VIMAGE @@ -168,6 +225,8 @@ nd6_destroy() callout_drain(&V_nd6_slowtimo_ch); callout_drain(&V_nd6_timer_ch); + if (IS_DEFAULT_VNET(curvnet)) + EVENTHANDLER_DEREGISTER(lle_event, lle_event_eh); } #endif diff --git a/sys/netinet6/udp6_usrreq.c b/sys/netinet6/udp6_usrreq.c index ab4dc7a8ce3b..eb97c1ee552a 100644 --- a/sys/netinet6/udp6_usrreq.c +++ b/sys/netinet6/udp6_usrreq.c @@ -136,7 +136,7 @@ __FBSDID("$FreeBSD$"); extern struct protosw inetsw[]; static void udp6_detach(struct socket *so); -static void +static int udp6_append(struct inpcb *inp, struct mbuf *n, int off, struct sockaddr_in6 *fromsa) { @@ -151,21 +151,24 @@ udp6_append(struct inpcb *inp, struct mbuf *n, int off, */ up = intoudpcb(inp); if (up->u_tun_func != NULL) { + in_pcbref(inp); + INP_RUNLOCK(inp); (*up->u_tun_func)(n, off, inp, (struct sockaddr *)fromsa, up->u_tun_ctx); - return; + INP_RLOCK(inp); + return (in_pcbrele_rlocked(inp)); } #ifdef IPSEC /* Check AH/ESP integrity. */ if (ipsec6_in_reject(n, inp)) { m_freem(n); - return; + return (0); } #endif /* IPSEC */ #ifdef MAC if (mac_inpcb_check_deliver(inp, n) != 0) { m_freem(n); - return; + return (0); } #endif opts = NULL; @@ -185,6 +188,7 @@ udp6_append(struct inpcb *inp, struct mbuf *n, int off, UDPSTAT_INC(udps_fullsock); } else sorwakeup_locked(so); + return (0); } int @@ -367,7 +371,8 @@ udp6_input(struct mbuf **mp, int *offp, int proto) INP_RLOCK(last); UDP_PROBE(receive, NULL, last, ip6, last, uh); - udp6_append(last, n, off, &fromsa); + if (udp6_append(last, n, off, &fromsa)) + goto inp_lost; INP_RUNLOCK(last); } } @@ -398,8 +403,9 @@ udp6_input(struct mbuf **mp, int *offp, int proto) INP_RLOCK(last); INP_INFO_RUNLOCK(pcbinfo); UDP_PROBE(receive, NULL, last, ip6, last, uh); - udp6_append(last, m, off, &fromsa); - INP_RUNLOCK(last); + if (udp6_append(last, m, off, &fromsa) == 0) + INP_RUNLOCK(last); + inp_lost: return (IPPROTO_DONE); } /* @@ -477,8 +483,8 @@ udp6_input(struct mbuf **mp, int *offp, int proto) } } UDP_PROBE(receive, NULL, inp, ip6, inp, uh); - udp6_append(inp, m, off, &fromsa); - INP_RUNLOCK(inp); + if (udp6_append(inp, m, off, &fromsa) == 0) + INP_RUNLOCK(inp); return (IPPROTO_DONE); badheadlocked: diff --git a/sys/netipsec/ipsec.h b/sys/netipsec/ipsec.h index 442387aefe44..328e8a37eb78 100644 --- a/sys/netipsec/ipsec.h +++ b/sys/netipsec/ipsec.h @@ -337,7 +337,7 @@ extern void ah4_ctlinput(int cmd, struct sockaddr *sa, void *); extern int esp4_input(struct mbuf **mp, int *offp, int proto); extern void esp4_ctlinput(int cmd, struct sockaddr *sa, void *); extern int ipcomp4_input(struct mbuf **mp, int *offp, int proto); -extern int ipsec4_common_input(struct mbuf *m, ...); +extern int ipsec_common_input(struct mbuf *m, int, int, int, int); extern int ipsec4_common_input_cb(struct mbuf *m, struct secasvar *sav, int skip, int protoff); extern int ipsec4_process_packet(struct mbuf *, struct ipsecrequest *); diff --git a/sys/netipsec/ipsec_input.c b/sys/netipsec/ipsec_input.c index 583769952ff7..6a41ad9f92da 100644 --- a/sys/netipsec/ipsec_input.c +++ b/sys/netipsec/ipsec_input.c @@ -118,7 +118,7 @@ static void ipsec4_common_ctlinput(int, struct sockaddr *, void *, int); * and call the appropriate transform. The transform callback * takes care of further processing (like ingress filtering). */ -static int +int ipsec_common_input(struct mbuf *m, int skip, int protoff, int af, int sproto) { char buf[INET6_ADDRSTRLEN]; @@ -243,24 +243,6 @@ ipsec_common_input(struct mbuf *m, int skip, int protoff, int af, int sproto) } #ifdef INET -/* - * Common input handler for IPv4 AH, ESP, and IPCOMP. - */ -int -ipsec4_common_input(struct mbuf *m, ...) -{ - va_list ap; - int off, nxt; - - va_start(ap, m); - off = va_arg(ap, int); - nxt = va_arg(ap, int); - va_end(ap); - - return ipsec_common_input(m, off, offsetof(struct ip, ip_p), - AF_INET, nxt); -} - int ah4_input(struct mbuf **mp, int *offp, int proto) { @@ -271,7 +253,8 @@ ah4_input(struct mbuf **mp, int *offp, int proto) off = *offp; *mp = NULL; - ipsec4_common_input(m, off, IPPROTO_AH); + ipsec_common_input(m, off, offsetof(struct ip, ip_p), + AF_INET, IPPROTO_AH); return (IPPROTO_DONE); } void @@ -292,7 +275,8 @@ esp4_input(struct mbuf **mp, int *offp, int proto) off = *offp; mp = NULL; - ipsec4_common_input(m, off, IPPROTO_ESP); + ipsec_common_input(m, off, offsetof(struct ip, ip_p), + AF_INET, IPPROTO_ESP); return (IPPROTO_DONE); } @@ -314,7 +298,8 @@ ipcomp4_input(struct mbuf **mp, int *offp, int proto) off = *offp; mp = NULL; - ipsec4_common_input(m, off, IPPROTO_IPCOMP); + ipsec_common_input(m, off, offsetof(struct ip, ip_p), + AF_INET, IPPROTO_IPCOMP); return (IPPROTO_DONE); } diff --git a/sys/netipsec/xform_esp.c b/sys/netipsec/xform_esp.c index 3d9ba14062ed..e0dc2b2728e6 100644 --- a/sys/netipsec/xform_esp.c +++ b/sys/netipsec/xform_esp.c @@ -989,9 +989,9 @@ esp_output_cb(struct cryptop *crp) case CRYPTO_SHA2_512_HMAC: alen = esph->hashsize/2; break; - case CRYPTO_AES_128_GMAC: - case CRYPTO_AES_192_GMAC: - case CRYPTO_AES_256_GMAC: + case CRYPTO_AES_128_NIST_GMAC: + case CRYPTO_AES_192_NIST_GMAC: + case CRYPTO_AES_256_NIST_GMAC: alen = esph->hashsize; break; default: diff --git a/sys/netpfil/ipfw/dn_heap.c b/sys/netpfil/ipfw/dn_heap.c index 1d585116d075..42431b00a72c 100644 --- a/sys/netpfil/ipfw/dn_heap.c +++ b/sys/netpfil/ipfw/dn_heap.c @@ -52,7 +52,7 @@ __FBSDID("$FreeBSD$"); #include "dn_heap.h" #define log(x, arg...) fprintf(stderr, ## arg) #define panic(x...) fprintf(stderr, ## x), exit(1) -#define MALLOC_DEFINE(a, b, c) +#define MALLOC_DEFINE(a, b, c) volatile int __dummy__ ## a __attribute__((__unused__)) static void *my_malloc(int s) { return malloc(s); } static void my_free(void *p) { free(p); } #define malloc(s, t, w) my_malloc(s) diff --git a/sys/netpfil/ipfw/dn_sched_qfq.c b/sys/netpfil/ipfw/dn_sched_qfq.c index 5bbff8a91344..ea27b3ea7a3a 100644 --- a/sys/netpfil/ipfw/dn_sched_qfq.c +++ b/sys/netpfil/ipfw/dn_sched_qfq.c @@ -172,8 +172,6 @@ for the scheduler: bitmaps and bucket lists. #define QFQ_MAX_WEIGHT (1<i_wsum) -#define IWSUM ((1<inv_w, cl->lmax); cl->grp = &q->groups[i]; q->wsum += w; + q->iwsum = ONE_FP / q->wsum; /* XXX note theory */ // XXX cl->S = q->V; ? - // XXX compute q->i_wsum return 0; } @@ -325,6 +324,8 @@ qfq_free_queue(struct dn_queue *_q) struct qfq_class *cl = (struct qfq_class *)_q; if (cl->inv_w) { q->wsum -= ONE_FP/cl->inv_w; + if (q->wsum != 0) + q->iwsum = ONE_FP / q->wsum; cl->inv_w = 0; /* reset weight to avoid run twice */ } return 0; @@ -408,7 +409,8 @@ qfq_make_eligible(struct qfq_sched *q, uint64_t old_V) old_vslot = old_V >> QFQ_MIN_SLOT_SHIFT; if (vslot != old_vslot) { - mask = (2UL << (__fls(vslot ^ old_vslot))) - 1; + /* should be 1ULL not 2ULL */ + mask = (1ULL << (__fls(vslot ^ old_vslot))) - 1; qfq_move_groups(q, mask, IR, ER); qfq_move_groups(q, mask, IB, EB); } @@ -557,7 +559,7 @@ qfq_dequeue(struct dn_sch_inst *si) } NO(q->queued--;) old_V = q->V; - q->V += (uint64_t)m->m_pkthdr.len * IWSUM; + q->V += (uint64_t)m->m_pkthdr.len * q->iwsum; ND("m is %p F 0x%llx V now 0x%llx", m, cl->F, q->V); if (qfq_update_class(q, grp, cl)) { @@ -612,7 +614,7 @@ qfq_update_start(struct qfq_sched *q, struct qfq_class *cl) int slot_shift = cl->grp->slot_shift; roundedF = qfq_round_down(cl->F, slot_shift); - limit = qfq_round_down(q->V, slot_shift) + (1UL << slot_shift); + limit = qfq_round_down(q->V, slot_shift) + (1ULL << slot_shift); if (!qfq_gt(cl->F, q->V) || qfq_gt(roundedF, limit)) { /* timestamp was stale */ @@ -620,7 +622,11 @@ qfq_update_start(struct qfq_sched *q, struct qfq_class *cl) if (mask) { struct qfq_group *next = qfq_ffs(q, mask); if (qfq_gt(roundedF, next->F)) { - cl->S = next->F; + /* from pv 71261956973ba9e0637848a5adb4a5819b4bae83 */ + if (qfq_gt(limit, next->F)) + cl->S = next->F; + else /* preserve timestamp correctness */ + cl->S = limit; return; } } diff --git a/sys/netpfil/ipfw/ip_dn_io.c b/sys/netpfil/ipfw/ip_dn_io.c index 399d9b189437..a5c4e0f98b30 100644 --- a/sys/netpfil/ipfw/ip_dn_io.c +++ b/sys/netpfil/ipfw/ip_dn_io.c @@ -429,8 +429,7 @@ ecn_mark(struct mbuf* m) switch (ip->ip_v) { case IPVERSION: { - u_int8_t otos; - int sum; + uint16_t old; if ((ip->ip_tos & IPTOS_ECN_MASK) == IPTOS_ECN_NOTECT) return (0); /* not-ECT */ @@ -441,17 +440,9 @@ ecn_mark(struct mbuf* m) * ecn-capable but not marked, * mark CE and update checksum */ - otos = ip->ip_tos; + old = *(uint16_t *)ip; ip->ip_tos |= IPTOS_ECN_CE; - /* - * update checksum (from RFC1624) - * HC' = ~(~HC + ~m + m') - */ - sum = ~ntohs(ip->ip_sum) & 0xffff; - sum += (~otos & 0xffff) + ip->ip_tos; - sum = (sum >> 16) + (sum & 0xffff); - sum += (sum >> 16); /* add carry */ - ip->ip_sum = htons(~sum & 0xffff); + ip->ip_sum = cksum_adjust(ip->ip_sum, old, *(uint16_t *)ip); return (1); } #ifdef INET6 diff --git a/sys/netpfil/ipfw/ip_fw2.c b/sys/netpfil/ipfw/ip_fw2.c index e5017d621672..afa3944244a6 100644 --- a/sys/netpfil/ipfw/ip_fw2.c +++ b/sys/netpfil/ipfw/ip_fw2.c @@ -2487,12 +2487,13 @@ do { \ code = TARG(cmd->arg1, dscp) & 0x3F; l = 0; /* exit inner loop */ if (is_ipv4) { - uint16_t a; + uint16_t old; - a = ip->ip_tos; - ip->ip_tos = (code << 2) | (ip->ip_tos & 0x03); - a += ntohs(ip->ip_sum) - ip->ip_tos; - ip->ip_sum = htons(a); + old = *(uint16_t *)ip; + ip->ip_tos = (code << 2) | + (ip->ip_tos & 0x03); + ip->ip_sum = cksum_adjust(ip->ip_sum, + old, *(uint16_t *)ip); } else if (is_ipv6) { uint8_t *v; diff --git a/sys/netpfil/ipfw/ip_fw_private.h b/sys/netpfil/ipfw/ip_fw_private.h index 504093bce6d1..ad445291eaf1 100644 --- a/sys/netpfil/ipfw/ip_fw_private.h +++ b/sys/netpfil/ipfw/ip_fw_private.h @@ -725,5 +725,22 @@ extern ipfw_nat_cfg_t *ipfw_nat_del_ptr; extern ipfw_nat_cfg_t *ipfw_nat_get_cfg_ptr; extern ipfw_nat_cfg_t *ipfw_nat_get_log_ptr; +/* Helper functions for IP checksum adjustment */ +static __inline uint16_t +cksum_add(uint16_t sum, uint16_t a) +{ + uint16_t res; + + res = sum + a; + return (res + (res < a)); +} + +static __inline uint16_t +cksum_adjust(uint16_t oldsum, uint16_t old, uint16_t new) +{ + + return (~cksum_add(cksum_add(~oldsum, ~old), new)); +} + #endif /* _KERNEL */ #endif /* _IPFW2_PRIVATE_H */ diff --git a/sys/netpfil/ipfw/test/dn_test.h b/sys/netpfil/ipfw/test/dn_test.h index 4e079bc4d68b..3b309cce082f 100644 --- a/sys/netpfil/ipfw/test/dn_test.h +++ b/sys/netpfil/ipfw/test/dn_test.h @@ -30,9 +30,13 @@ extern int debug; #ifndef offsetof -#define offsetof(t,m) (int)((&((t *)0L)->m)) +#define offsetof(t,m) (int)(intptr_t)((&((t *)0L)->m)) #endif +#if defined(__APPLE__) // XXX osx +typedef unsigned int u_int; +#endif /* osx */ + #include /* prevent include of other system headers */ @@ -85,6 +89,11 @@ struct dn_flow { uint64_t tot_bytes; uint32_t flow_id; struct list_head h; /* used by the generator */ + + /* bytes served by the flow since the last backlog time */ + uint64_t bytes; + /* bytes served by the system at the last backlog time */ + uint64_t sch_bytes; }; struct dn_link { @@ -103,7 +112,7 @@ struct mbuf { void *cfg; /* config args */ }; -#define MALLOC_DECLARE(x) +#define MALLOC_DECLARE(x) extern volatile int __dummy__ ## x #define KASSERT(x, y) do { if (!(x)) printf y ; exit(0); } while (0) struct ipfw_flow_id { }; diff --git a/sys/netpfil/ipfw/test/main.c b/sys/netpfil/ipfw/test/main.c index be9fdf53612c..ce86f49615e7 100644 --- a/sys/netpfil/ipfw/test/main.c +++ b/sys/netpfil/ipfw/test/main.c @@ -75,6 +75,9 @@ struct cfg_s { #define BACKLOG 30 uint32_t llmask; struct list_head ll[BACKLOG + 10]; + + double *q_wfi; /* (byte) Worst-case Fair Index of the flows */ + double wfi; /* (byte) Worst-case Fair Index of the system */ }; /* FI2Q and Q2FI converts from flow_id to dn_queue and back. @@ -145,6 +148,39 @@ dequeue(struct cfg_s *c) return m; } +static void +gnet_stats_enq(struct cfg_s *c, struct mbuf *mb) +{ + struct dn_sch_inst *si = c->si; + struct dn_queue *_q = FI2Q(c, mb->flow_id); + + if (_q->ni.length == 1) { + _q->ni.bytes = 0; + _q->ni.sch_bytes = si->ni.bytes; + } +} + +static void +gnet_stats_deq(struct cfg_s *c, struct mbuf *mb) +{ + struct dn_sch_inst *si = c->si; + struct dn_queue *_q = FI2Q(c, mb->flow_id); + int len = mb->m_pkthdr.len; + + _q->ni.bytes += len; + si->ni.bytes += len; + + if (_q->ni.length == 0) { + double bytes = (double)_q->ni.bytes; + double sch_bytes = (double)si->ni.bytes - _q->ni.sch_bytes; + double weight = (double)_q->fs->fs.par[0] / c->wsum; + double wfi = sch_bytes * weight - bytes; + + if (c->q_wfi[mb->flow_id] < wfi) + c->q_wfi[mb->flow_id] = wfi; + } +} + static int mainloop(struct cfg_s *c) { @@ -164,6 +200,7 @@ mainloop(struct cfg_s *c) } else { ND("enqueue ok"); c->pending++; + gnet_stats_enq(c, m); } } if (c->can_dequeue) { @@ -172,6 +209,7 @@ mainloop(struct cfg_s *c) c->pending--; drop(c, m); c->drop--; /* compensate */ + gnet_stats_deq(c, m); } } } @@ -187,7 +225,8 @@ dump(struct cfg_s *c) for (i=0; i < c->flows; i++) { q = FI2Q(c, i); - DX(1, "queue %4d tot %10lld", i, q->ni.tot_bytes); + DX(1, "queue %4d tot %10llu", i, + (unsigned long long)q->ni.tot_bytes); } DX(1, "done %d loops\n", c->loops); return 0; @@ -373,6 +412,9 @@ init(struct cfg_s *c) extern moduledata_t *_g_dn_wf2qp; extern moduledata_t *_g_dn_rr; extern moduledata_t *_g_dn_qfq; +#ifdef WITH_QFQP + extern moduledata_t *_g_dn_qfqp; +#endif #ifdef WITH_KPS extern moduledata_t *_g_dn_kps; #endif @@ -384,6 +426,11 @@ init(struct cfg_s *c) mod = _g_dn_fifo; else if (!strcmp(av[1], "qfq")) mod = _g_dn_qfq; +#ifdef WITH_QFQP + else if (!strcmp(av[1], "qfq+") || + !strcmp(av[1], "qfqp") ) + mod = _g_dn_qfqp; +#endif #ifdef WITH_KPS else if (!strcmp(av[1], "kps")) mod = _g_dn_kps; @@ -447,10 +494,11 @@ init(struct cfg_s *c) } /* allocate queues, flowsets and one scheduler */ c->q = calloc(c->flows, c->q_len); + c->q_wfi = (double *)calloc(c->flows, sizeof(double)); c->fs = calloc(c->flowsets, sizeof(struct dn_fsk)); c->si = calloc(1, c->si_len); c->sched = calloc(c->flows, c->schk_len); - if (c->q == NULL || c->fs == NULL) { + if (c->q == NULL || c->fs == NULL || !c->q_wfi) { D("error allocating memory for flows"); exit(1); } @@ -520,11 +568,13 @@ main(int ac, char *av[]) ll *= 1000; /* convert to nanoseconds */ ll /= c._enqueue; sprintf(msg, "1::%d", c.flows); - D("%-8s n %d %d time %d.%06d %8.3f qlen %d %d flows %s drops %d", - c.name, c._enqueue, c.loops, - (int)c.time.tv_sec, (int)c.time.tv_usec, ll, - c.th_min, c.th_max, - c.fs_config ? c.fs_config : msg, c.drop); + for (i = 0; i < c.flows; i++) { + if (c.wfi < c.q_wfi[i]) + c.wfi = c.q_wfi[i]; + } + D("sched=%-12s\ttime=%d.%03d sec (%.0f nsec)\twfi=%.02f\tflow=%-16s", + c.name, (int)c.time.tv_sec, (int)c.time.tv_usec / 1000, ll, c.wfi, + c.fs_config ? c.fs_config : msg); dump(&c); DX(1, "done ac %d av %p", ac, av); for (i=0; i < ac; i++) diff --git a/sys/opencrypto/cryptodev.h b/sys/opencrypto/cryptodev.h index 48f094bfa3f6..5aa450f6a44b 100644 --- a/sys/opencrypto/cryptodev.h +++ b/sys/opencrypto/cryptodev.h @@ -115,7 +115,7 @@ #define CAST128_BLOCK_LEN 8 #define RIJNDAEL128_BLOCK_LEN 16 #define AES_BLOCK_LEN 16 -#define AES_MIN_BLOCK_LEN 1 +#define AES_ICM_BLOCK_LEN 1 #define ARC4_BLOCK_LEN 1 #define CAMELLIA_BLOCK_LEN 16 #define EALG_MAX_BLOCK_LEN AES_BLOCK_LEN /* Keep this updated */ @@ -123,12 +123,10 @@ /* IV Lengths */ #define ARC4_IV_LEN 1 -#define AES_IV_LEN 12 +#define AES_GCM_IV_LEN 12 #define AES_XTS_IV_LEN 8 #define AES_XTS_ALPHA 0x87 /* GF(2^128) generator polynomial */ -#define AES_CTR_NONCE_SIZE 4 - /* Min and Max Encryption Key Sizes */ #define NULL_MIN_KEY 0 #define NULL_MAX_KEY 256 /* 2048 bits, max key */ @@ -144,10 +142,10 @@ #define SKIPJACK_MAX_KEY SKIPJACK_MIN_KEY #define RIJNDAEL_MIN_KEY 16 #define RIJNDAEL_MAX_KEY 32 -#define AES_MIN_KEY 16 -#define AES_MAX_KEY 32 -#define AES_XTS_MIN_KEY 32 -#define AES_XTS_MAX_KEY 64 +#define AES_MIN_KEY RIJNDAEL_MIN_KEY +#define AES_MAX_KEY RIJNDAEL_MAX_KEY +#define AES_XTS_MIN_KEY (2 * AES_MIN_KEY) +#define AES_XTS_MAX_KEY (2 * AES_MAX_KEY) #define ARC4_MIN_KEY 1 #define ARC4_MAX_KEY 32 #define CAMELLIA_MIN_KEY 8 diff --git a/sys/opencrypto/xform.c b/sys/opencrypto/xform.c index 265e0b456c2b..9e8a1c1afec8 100644 --- a/sys/opencrypto/xform.c +++ b/sys/opencrypto/xform.c @@ -227,7 +227,7 @@ struct enc_xform enc_xform_rijndael128 = { struct enc_xform enc_xform_aes_icm = { CRYPTO_AES_ICM, "AES-ICM", - RIJNDAEL128_BLOCK_LEN, RIJNDAEL128_BLOCK_LEN, AES_MIN_KEY, AES_MAX_KEY, + AES_BLOCK_LEN, AES_BLOCK_LEN, AES_MIN_KEY, AES_MAX_KEY, aes_icm_crypt, aes_icm_crypt, aes_icm_setkey, @@ -237,7 +237,7 @@ struct enc_xform enc_xform_aes_icm = { struct enc_xform enc_xform_aes_nist_gcm = { CRYPTO_AES_NIST_GCM_16, "AES-GCM", - AES_MIN_BLOCK_LEN, AES_IV_LEN, AES_MIN_KEY, AES_MAX_KEY, + AES_ICM_BLOCK_LEN, AES_GCM_IV_LEN, AES_MIN_KEY, AES_MAX_KEY, aes_icm_crypt, aes_icm_crypt, aes_icm_setkey, @@ -247,7 +247,7 @@ struct enc_xform enc_xform_aes_nist_gcm = { struct enc_xform enc_xform_aes_nist_gmac = { CRYPTO_AES_NIST_GMAC, "AES-GMAC", - AES_MIN_BLOCK_LEN, AES_IV_LEN, AES_MIN_KEY, AES_MAX_KEY, + AES_ICM_BLOCK_LEN, AES_GCM_IV_LEN, AES_MIN_KEY, AES_MAX_KEY, NULL, NULL, NULL, @@ -257,7 +257,7 @@ struct enc_xform enc_xform_aes_nist_gmac = { struct enc_xform enc_xform_aes_xts = { CRYPTO_AES_XTS, "AES-XTS", - AES_MIN_BLOCK_LEN, AES_XTS_IV_LEN, AES_XTS_MIN_KEY, AES_XTS_MAX_KEY, + AES_BLOCK_LEN, AES_XTS_IV_LEN, AES_XTS_MIN_KEY, AES_XTS_MAX_KEY, aes_xts_encrypt, aes_xts_decrypt, aes_xts_setkey, diff --git a/sys/pc98/conf/GENERIC b/sys/pc98/conf/GENERIC index 8646a0e5bf40..e7876ba8cdd8 100644 --- a/sys/pc98/conf/GENERIC +++ b/sys/pc98/conf/GENERIC @@ -257,5 +257,5 @@ device bpf # Berkeley packet filter #device "snd_sb16" # Sound Blaster 16 #device snd_sbc # Sound Blaster -# The cypto framework is required by IPSEC +# The crypto framework is required by IPSEC device crypto # Required by IPSEC diff --git a/sys/powerpc/aim/trap_subr64.S b/sys/powerpc/aim/trap_subr64.S index 5f531551b344..7ad0a7039ea2 100644 --- a/sys/powerpc/aim/trap_subr64.S +++ b/sys/powerpc/aim/trap_subr64.S @@ -842,11 +842,7 @@ CNAME(dblow): mflr %r1 /* save LR */ mtsprg2 %r1 /* And then in SPRG2 */ - nop /* Begin branching to generictrap */ - bl 9f - .llong generictrap -9: mflr %r1 - ld %r1,0(%r1) + ld %r1, TRAP_GENTRAP(0) /* Get branch address */ mtlr %r1 li %r1, 0 /* How to get the vector from LR */ blrl /* Branch to generictrap */ diff --git a/sys/powerpc/booke/pmap.c b/sys/powerpc/booke/pmap.c index fc6917fc605d..656b7a336fb3 100644 --- a/sys/powerpc/booke/pmap.c +++ b/sys/powerpc/booke/pmap.c @@ -51,6 +51,8 @@ #include __FBSDID("$FreeBSD$"); +#include "opt_kstack_pages.h" + #include #include #include diff --git a/sys/powerpc/conf/GENERIC b/sys/powerpc/conf/GENERIC index 37cafbc666f6..e2ed7876f452 100644 --- a/sys/powerpc/conf/GENERIC +++ b/sys/powerpc/conf/GENERIC @@ -217,5 +217,5 @@ device snd_ai2s # Apple I2S audio device snd_davbus # Apple DAVBUS audio device snd_uaudio # USB Audio -# The cypto framework is required by IPSEC +# The crypto framework is required by IPSEC device crypto # Required by IPSEC diff --git a/sys/powerpc/conf/NOTES b/sys/powerpc/conf/NOTES index 9bfe6a956e04..75e774fb94d6 100644 --- a/sys/powerpc/conf/NOTES +++ b/sys/powerpc/conf/NOTES @@ -14,7 +14,6 @@ options KDTRACE_HOOKS #device dtrace # DTrace modules -#device dtrace_lockstat #device dtrace_profile #device dtrace_sdt #device dtrace_fbt diff --git a/sys/powerpc/include/cpu.h b/sys/powerpc/include/cpu.h index c4fa94a3ec6f..ba45eb0372e4 100644 --- a/sys/powerpc/include/cpu.h +++ b/sys/powerpc/include/cpu.h @@ -65,9 +65,6 @@ extern int cpu_features; #define TRAPF_USERMODE(frame) (((frame)->srr1 & PSL_PR) != 0) #define TRAPF_PC(frame) ((frame)->srr0) -#define cpu_swapout(p) -#define cpu_number() 0 - /* * CTL_MACHDEP definitions. */ diff --git a/sys/sparc64/conf/GENERIC b/sys/sparc64/conf/GENERIC index 04df77db69b7..0038c66e48cd 100644 --- a/sys/sparc64/conf/GENERIC +++ b/sys/sparc64/conf/GENERIC @@ -251,5 +251,5 @@ device snd_audiocs # Crystal Semiconductor CS4231 device snd_es137x # Ensoniq AudioPCI ES137x device snd_t4dwave # Acer Labs M5451 -# The cypto framework is required by IPSEC +# The crypto framework is required by IPSEC device crypto # Required by IPSEC diff --git a/sys/sparc64/sparc64/exception.S b/sys/sparc64/sparc64/exception.S index 09db4e0797b4..b3830c08049d 100644 --- a/sys/sparc64/sparc64/exception.S +++ b/sys/sparc64/sparc64/exception.S @@ -58,6 +58,7 @@ __FBSDID("$FreeBSD$"); #include "opt_compat.h" #include "opt_ddb.h" +#include "opt_kstack_pages.h" #include #include diff --git a/sys/sparc64/sparc64/stack_machdep.c b/sys/sparc64/sparc64/stack_machdep.c index a4309ef45c48..923d72cc8d2d 100644 --- a/sys/sparc64/sparc64/stack_machdep.c +++ b/sys/sparc64/sparc64/stack_machdep.c @@ -27,6 +27,8 @@ #include __FBSDID("$FreeBSD$"); +#include "opt_kstack_pages.h" + #include #include #include diff --git a/sys/sparc64/sparc64/support.S b/sys/sparc64/sparc64/support.S index d6468cf4f4fe..b446ddeac7ef 100644 --- a/sys/sparc64/sparc64/support.S +++ b/sys/sparc64/sparc64/support.S @@ -27,6 +27,8 @@ #include __FBSDID("$FreeBSD$"); +#include "opt_kstack_pages.h" + #include #include diff --git a/sys/sys/_vm_domain.h b/sys/sys/_vm_domain.h new file mode 100644 index 000000000000..36d107a110b0 --- /dev/null +++ b/sys/sys/_vm_domain.h @@ -0,0 +1,61 @@ +/*- + * Copyright (c) 2015 Adrian Chadd . + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + * $FreeBSD$ + */ +#ifndef __SYS_VM_DOMAIN_H__ +#define __SYS_VM_DOMAIN_H__ + +#include + +typedef enum { + VM_POLICY_NONE, + VM_POLICY_ROUND_ROBIN, + VM_POLICY_FIXED_DOMAIN, + VM_POLICY_FIXED_DOMAIN_ROUND_ROBIN, + VM_POLICY_FIRST_TOUCH, + VM_POLICY_FIRST_TOUCH_ROUND_ROBIN, + VM_POLICY_MAX +} vm_domain_policy_type_t; + +struct vm_domain_policy_entry { + vm_domain_policy_type_t policy; + int domain; +}; + +struct vm_domain_policy { + seq_t seq; + struct vm_domain_policy_entry p; +}; + +#define VM_DOMAIN_POLICY_STATIC_INITIALISER(vt, vd) \ + { .seq = 0, \ + .p.policy = vt, \ + .p.domain = vd } + +#endif /* __SYS_VM_DOMAIN_H__ */ diff --git a/sys/sys/domain.h b/sys/sys/domain.h index bacdad143f07..1817e7881c6f 100644 --- a/sys/sys/domain.h +++ b/sys/sys/domain.h @@ -42,6 +42,7 @@ */ struct mbuf; struct ifnet; +struct socket; struct domain { int dom_family; /* AF_xxx */ @@ -53,7 +54,7 @@ struct domain { int (*dom_externalize) /* externalize access rights */ (struct mbuf *, struct mbuf **, int); void (*dom_dispose) /* dispose of internalized rights */ - (struct mbuf *); + (struct socket *); struct protosw *dom_protosw, *dom_protoswNPROTOSW; struct domain *dom_next; int (*dom_rtattach) /* initialize routing table */ diff --git a/sys/sys/filedesc.h b/sys/sys/filedesc.h index 74cc5fd55f3b..b557706bb04e 100644 --- a/sys/sys/filedesc.h +++ b/sys/sys/filedesc.h @@ -134,11 +134,17 @@ struct filedesc_to_leader { SX_NOTRECURSED) #define FILEDESC_UNLOCK_ASSERT(fdp) sx_assert(&(fdp)->fd_sx, SX_UNLOCKED) +/* Operation types for kern_dup(). */ +enum { + FDDUP_NORMAL, /* dup() behavior. */ + FDDUP_FCNTL, /* fcntl()-style errors. */ + FDDUP_FIXED, /* Force fixed allocation. */ + FDDUP_MUSTREPLACE, /* Target must exist. */ + FDDUP_LASTMODE, +}; + /* Flags for kern_dup(). */ -#define FDDUP_FIXED 0x1 /* Force fixed allocation. */ -#define FDDUP_FCNTL 0x2 /* fcntl()-style errors. */ -#define FDDUP_CLOEXEC 0x4 /* Atomically set FD_CLOEXEC. */ -#define FDDUP_MUSTREPLACE 0x8 /* Target must exist. */ +#define FDDUP_FLAG_CLOEXEC 0x1 /* Atomically set UF_EXCLOSE. */ struct thread; @@ -164,8 +170,12 @@ void fdclose(struct thread *td, struct file *fp, int idx); void fdcloseexec(struct thread *td); void fdsetugidsafety(struct thread *td); struct filedesc *fdcopy(struct filedesc *fdp); +int fdcopy_remapped(struct filedesc *fdp, const int *fds, size_t nfds, + struct filedesc **newfdp); +void fdinstall_remapped(struct thread *td, struct filedesc *fdp); void fdunshare(struct thread *td); void fdescfree(struct thread *td); +void fdescfree_remapped(struct filedesc *fdp); struct filedesc *fdinit(struct filedesc *fdp, bool prepfiles); struct filedesc *fdshare(struct filedesc *fdp); struct filedesc_to_leader * @@ -199,6 +209,11 @@ fd_modified(struct filedesc *fdp, int fd, seq_t seq) return (!seq_consistent(fd_seq(fdp->fd_files, fd), seq)); } +/* cdir/rdir/jdir manipulation functions. */ +void pwd_chdir(struct thread *td, struct vnode *vp); +int pwd_chroot(struct thread *td, struct vnode *vp); +void pwd_ensure_dirs(void); + #endif /* _KERNEL */ #endif /* !_SYS_FILEDESC_H_ */ diff --git a/sys/sys/imgact.h b/sys/sys/imgact.h index 4a5ce9c4ac07..1746d402c639 100644 --- a/sys/sys/imgact.h +++ b/sys/sys/imgact.h @@ -49,6 +49,7 @@ struct image_args { int argc; /* count of argument strings */ int envc; /* count of environment strings */ int fd; /* file descriptor of the executable */ + struct filedesc *fdp; /* new file descriptor table */ }; struct image_params { @@ -99,6 +100,8 @@ void exec_setregs(struct thread *, struct image_params *, u_long); int exec_shell_imgact(struct image_params *); int exec_copyin_args(struct image_args *, char *, enum uio_seg, char **, char **); +int exec_copyin_data_fds(struct thread *, struct image_args *, const void *, + size_t, const int *, size_t); int pre_execve(struct thread *td, struct vmspace **oldvmspace); void post_execve(struct thread *td, int error, struct vmspace *oldvmspace); #endif diff --git a/sys/sys/jail.h b/sys/sys/jail.h index 916bd5909fb1..70e70856e6dc 100644 --- a/sys/sys/jail.h +++ b/sys/sys/jail.h @@ -230,7 +230,9 @@ struct prison_racct { #define PR_ALLOW_MOUNT_PROCFS 0x0400 #define PR_ALLOW_MOUNT_TMPFS 0x0800 #define PR_ALLOW_MOUNT_FDESCFS 0x1000 -#define PR_ALLOW_ALL 0x1fff +#define PR_ALLOW_MOUNT_LINPROCFS 0x2000 +#define PR_ALLOW_MOUNT_LINSYSFS 0x4000 +#define PR_ALLOW_ALL 0x7fff /* * OSD methods diff --git a/sys/sys/lockmgr.h b/sys/sys/lockmgr.h index ff0473d61b88..a74d5f537d8e 100644 --- a/sys/sys/lockmgr.h +++ b/sys/sys/lockmgr.h @@ -159,6 +159,7 @@ _lockmgr_args_rw(struct lock *lk, u_int flags, struct rwlock *ilk, #define LK_SLEEPFAIL 0x000800 #define LK_TIMELOCK 0x001000 #define LK_NODDLKTREAT 0x002000 +#define LK_VNHELD 0x004000 /* * Operations for lockmgr(). diff --git a/sys/sys/lockstat.h b/sys/sys/lockstat.h index 2a7853fb95bf..e5503539298f 100644 --- a/sys/sys/lockstat.h +++ b/sys/sys/lockstat.h @@ -27,183 +27,91 @@ /* * DTrace lockstat provider definitions - * */ -#ifndef _SYS_LOCKSTAT_H +#ifndef _SYS_LOCKSTAT_H #define _SYS_LOCKSTAT_H -#ifdef _KERNEL +#ifdef _KERNEL -/* - * Spin Locks - */ -#define LS_MTX_SPIN_LOCK_ACQUIRE 0 -#define LS_MTX_SPIN_UNLOCK_RELEASE 1 -#define LS_MTX_SPIN_LOCK_SPIN 2 +#include +#include +#include -/* - * Adaptive Locks - */ -#define LS_MTX_LOCK_ACQUIRE 3 -#define LS_MTX_UNLOCK_RELEASE 4 -#define LS_MTX_LOCK_SPIN 5 -#define LS_MTX_LOCK_BLOCK 6 -#define LS_MTX_TRYLOCK_ACQUIRE 7 +SDT_PROVIDER_DECLARE(lockstat); -/* - * Reader/Writer Locks - */ -#define LS_RW_RLOCK_ACQUIRE 8 -#define LS_RW_RUNLOCK_RELEASE 9 -#define LS_RW_WLOCK_ACQUIRE 10 -#define LS_RW_WUNLOCK_RELEASE 11 -#define LS_RW_RLOCK_SPIN 12 -#define LS_RW_RLOCK_BLOCK 13 -#define LS_RW_WLOCK_SPIN 14 -#define LS_RW_WLOCK_BLOCK 15 -#define LS_RW_TRYUPGRADE_UPGRADE 16 -#define LS_RW_DOWNGRADE_DOWNGRADE 17 +SDT_PROBE_DECLARE(lockstat, , , adaptive__acquire); +SDT_PROBE_DECLARE(lockstat, , , adaptive__release); +SDT_PROBE_DECLARE(lockstat, , , adaptive__spin); +SDT_PROBE_DECLARE(lockstat, , , adaptive__block); -/* - * Shared/Exclusive Locks - */ -#define LS_SX_SLOCK_ACQUIRE 18 -#define LS_SX_SUNLOCK_RELEASE 19 -#define LS_SX_XLOCK_ACQUIRE 20 -#define LS_SX_XUNLOCK_RELEASE 21 -#define LS_SX_SLOCK_SPIN 22 -#define LS_SX_SLOCK_BLOCK 23 -#define LS_SX_XLOCK_SPIN 24 -#define LS_SX_XLOCK_BLOCK 25 -#define LS_SX_TRYUPGRADE_UPGRADE 26 -#define LS_SX_DOWNGRADE_DOWNGRADE 27 +SDT_PROBE_DECLARE(lockstat, , , spin__acquire); +SDT_PROBE_DECLARE(lockstat, , , spin__release); +SDT_PROBE_DECLARE(lockstat, , , spin__spin); -/* - * Thread Locks - */ -#define LS_THREAD_LOCK_SPIN 28 +SDT_PROBE_DECLARE(lockstat, , , rw__acquire); +SDT_PROBE_DECLARE(lockstat, , , rw__release); +SDT_PROBE_DECLARE(lockstat, , , rw__block); +SDT_PROBE_DECLARE(lockstat, , , rw__spin); +SDT_PROBE_DECLARE(lockstat, , , rw__upgrade); +SDT_PROBE_DECLARE(lockstat, , , rw__downgrade); -/* - * Lockmanager Locks - * According to locking(9) Lockmgr locks are "Largely deprecated" - * so no support for these have been added in the lockstat provider. - */ +SDT_PROBE_DECLARE(lockstat, , , sx__acquire); +SDT_PROBE_DECLARE(lockstat, , , sx__release); +SDT_PROBE_DECLARE(lockstat, , , sx__block); +SDT_PROBE_DECLARE(lockstat, , , sx__spin); +SDT_PROBE_DECLARE(lockstat, , , sx__upgrade); +SDT_PROBE_DECLARE(lockstat, , , sx__downgrade); -#define LS_NPROBES 29 - -#define LS_MTX_LOCK "mtx_lock" -#define LS_MTX_UNLOCK "mtx_unlock" -#define LS_MTX_SPIN_LOCK "mtx_lock_spin" -#define LS_MTX_SPIN_UNLOCK "mtx_unlock_spin" -#define LS_MTX_TRYLOCK "mtx_trylock" -#define LS_RW_RLOCK "rw_rlock" -#define LS_RW_WLOCK "rw_wlock" -#define LS_RW_RUNLOCK "rw_runlock" -#define LS_RW_WUNLOCK "rw_wunlock" -#define LS_RW_TRYUPGRADE "rw_try_upgrade" -#define LS_RW_DOWNGRADE "rw_downgrade" -#define LS_SX_SLOCK "sx_slock" -#define LS_SX_XLOCK "sx_xlock" -#define LS_SX_SUNLOCK "sx_sunlock" -#define LS_SX_XUNLOCK "sx_xunlock" -#define LS_SX_TRYUPGRADE "sx_try_upgrade" -#define LS_SX_DOWNGRADE "sx_downgrade" -#define LS_THREAD_LOCK "thread_lock" - -#define LS_ACQUIRE "acquire" -#define LS_RELEASE "release" -#define LS_SPIN "spin" -#define LS_BLOCK "block" -#define LS_UPGRADE "upgrade" -#define LS_DOWNGRADE "downgrade" - -#define LS_TYPE_ADAPTIVE "adaptive" -#define LS_TYPE_SPIN "spin" -#define LS_TYPE_THREAD "thread" -#define LS_TYPE_RW "rw" -#define LS_TYPE_SX "sx" - -#define LSA_ACQUIRE (LS_TYPE_ADAPTIVE "-" LS_ACQUIRE) -#define LSA_RELEASE (LS_TYPE_ADAPTIVE "-" LS_RELEASE) -#define LSA_SPIN (LS_TYPE_ADAPTIVE "-" LS_SPIN) -#define LSA_BLOCK (LS_TYPE_ADAPTIVE "-" LS_BLOCK) -#define LSS_ACQUIRE (LS_TYPE_SPIN "-" LS_ACQUIRE) -#define LSS_RELEASE (LS_TYPE_SPIN "-" LS_RELEASE) -#define LSS_SPIN (LS_TYPE_SPIN "-" LS_SPIN) -#define LSR_ACQUIRE (LS_TYPE_RW "-" LS_ACQUIRE) -#define LSR_RELEASE (LS_TYPE_RW "-" LS_RELEASE) -#define LSR_BLOCK (LS_TYPE_RW "-" LS_BLOCK) -#define LSR_SPIN (LS_TYPE_RW "-" LS_SPIN) -#define LSR_UPGRADE (LS_TYPE_RW "-" LS_UPGRADE) -#define LSR_DOWNGRADE (LS_TYPE_RW "-" LS_DOWNGRADE) -#define LSX_ACQUIRE (LS_TYPE_SX "-" LS_ACQUIRE) -#define LSX_RELEASE (LS_TYPE_SX "-" LS_RELEASE) -#define LSX_BLOCK (LS_TYPE_SX "-" LS_BLOCK) -#define LSX_SPIN (LS_TYPE_SX "-" LS_SPIN) -#define LSX_UPGRADE (LS_TYPE_SX "-" LS_UPGRADE) -#define LSX_DOWNGRADE (LS_TYPE_SX "-" LS_DOWNGRADE) -#define LST_SPIN (LS_TYPE_THREAD "-" LS_SPIN) - -/* - * The following must match the type definition of dtrace_probe. It is - * defined this way to avoid having to rely on CDDL code. - */ -extern uint32_t lockstat_probemap[LS_NPROBES]; -typedef void (*lockstat_probe_func_t)(uint32_t, uintptr_t arg0, uintptr_t arg1, - uintptr_t arg2, uintptr_t arg3, uintptr_t arg4); -extern lockstat_probe_func_t lockstat_probe_func; -extern uint64_t lockstat_nsecs(void); - -#ifdef KDTRACE_HOOKS -/* - * Macros to record lockstat probes. - */ -#define LOCKSTAT_RECORD4(probe, lp, arg1, arg2, arg3, arg4) do { \ - uint32_t id; \ - \ - if ((id = lockstat_probemap[(probe)])) \ - (*lockstat_probe_func)(id, (uintptr_t)(lp), (arg1), (arg2), \ - (arg3), (arg4)); \ -} while (0) - -#define LOCKSTAT_RECORD(probe, lp, arg1) \ - LOCKSTAT_RECORD4(probe, lp, arg1, 0, 0, 0) - -#define LOCKSTAT_RECORD0(probe, lp) \ - LOCKSTAT_RECORD4(probe, lp, 0, 0, 0, 0) - -#define LOCKSTAT_RECORD1(probe, lp, arg1) \ - LOCKSTAT_RECORD4(probe, lp, arg1, 0, 0, 0) - -#define LOCKSTAT_RECORD2(probe, lp, arg1, arg2) \ - LOCKSTAT_RECORD4(probe, lp, arg1, arg2, 0, 0) - -#define LOCKSTAT_RECORD3(probe, lp, arg1, arg2, arg3) \ - LOCKSTAT_RECORD4(probe, lp, arg1, arg2, arg3, 0) - -#define LOCKSTAT_PROFILE_OBTAIN_LOCK_SUCCESS(probe, lp, c, wt, f, l) do { \ - uint32_t id; \ - \ - lock_profile_obtain_lock_success(&(lp)->lock_object, c, wt, f, l); \ - if ((id = lockstat_probemap[(probe)])) \ - (*lockstat_probe_func)(id, (uintptr_t)(lp), 0, 0, 0, 0); \ -} while (0) - -#define LOCKSTAT_PROFILE_RELEASE_LOCK(probe, lp) do { \ - uint32_t id; \ - \ - lock_profile_release_lock(&(lp)->lock_object); \ - if ((id = lockstat_probemap[(probe)])) \ - (*lockstat_probe_func)(id, (uintptr_t)(lp), 0, 0, 0, 0); \ -} while (0) +SDT_PROBE_DECLARE(lockstat, , , thread__spin); #define LOCKSTAT_WRITER 0 #define LOCKSTAT_READER 1 -#else /* !KDTRACE_HOOKS */ +extern int lockstat_enabled; + +#ifdef KDTRACE_HOOKS + +#define LOCKSTAT_RECORD0(probe, lp) \ + SDT_PROBE1(lockstat, , , probe, lp) + +#define LOCKSTAT_RECORD1(probe, lp, arg1) \ + SDT_PROBE2(lockstat, , , probe, lp, arg1) + +#define LOCKSTAT_RECORD2(probe, lp, arg1, arg2) \ + SDT_PROBE3(lockstat, , , probe, lp, arg1, arg2) + +#define LOCKSTAT_RECORD3(probe, lp, arg1, arg2, arg3) \ + SDT_PROBE4(lockstat, , , probe, lp, arg1, arg2, arg3) + +#define LOCKSTAT_RECORD4(probe, lp, arg1, arg2, arg3, arg4) \ + SDT_PROBE5(lockstat, , , probe, lp, arg1, arg2, arg3, arg4) + +#define LOCKSTAT_PROFILE_OBTAIN_LOCK_SUCCESS(probe, lp, c, wt, f, l) do { \ + lock_profile_obtain_lock_success(&(lp)->lock_object, c, wt, f, l); \ + LOCKSTAT_RECORD0(probe, lp); \ +} while (0) + +#define LOCKSTAT_PROFILE_OBTAIN_RWLOCK_SUCCESS(probe, lp, c, wt, f, l, a) do { \ + lock_profile_obtain_lock_success(&(lp)->lock_object, c, wt, f, l); \ + LOCKSTAT_RECORD1(probe, lp, a); \ +} while (0) + +#define LOCKSTAT_PROFILE_RELEASE_LOCK(probe, lp) do { \ + lock_profile_release_lock(&(lp)->lock_object); \ + LOCKSTAT_RECORD0(probe, lp); \ +} while (0) + +#define LOCKSTAT_PROFILE_RELEASE_RWLOCK(probe, lp, a) do { \ + lock_profile_release_lock(&(lp)->lock_object); \ + LOCKSTAT_RECORD1(probe, lp, a); \ +} while (0) + +struct lock_object; +uint64_t lockstat_nsecs(struct lock_object *); + +#else /* !KDTRACE_HOOKS */ -#define LOCKSTAT_RECORD(probe, lp, arg1) #define LOCKSTAT_RECORD0(probe, lp) #define LOCKSTAT_RECORD1(probe, lp, arg1) #define LOCKSTAT_RECORD2(probe, lp, arg1, arg2) @@ -213,11 +121,15 @@ extern uint64_t lockstat_nsecs(void); #define LOCKSTAT_PROFILE_OBTAIN_LOCK_SUCCESS(probe, lp, c, wt, f, l) \ lock_profile_obtain_lock_success(&(lp)->lock_object, c, wt, f, l) +#define LOCKSTAT_PROFILE_OBTAIN_RWLOCK_SUCCESS(probe, lp, c, wt, f, l, a) \ + LOCKSTAT_PROFILE_OBTAIN_LOCK_SUCCESS(probe, lp, c, wt, f, l) + #define LOCKSTAT_PROFILE_RELEASE_LOCK(probe, lp) \ lock_profile_release_lock(&(lp)->lock_object) -#endif /* !KDTRACE_HOOKS */ +#define LOCKSTAT_PROFILE_RELEASE_RWLOCK(probe, lp, a) \ + LOCKSTAT_PROFILE_RELEASE_LOCK(probe, lp) -#endif /* _KERNEL */ - -#endif /* _SYS_LOCKSTAT_H */ +#endif /* !KDTRACE_HOOKS */ +#endif /* _KERNEL */ +#endif /* _SYS_LOCKSTAT_H */ diff --git a/sys/sys/mutex.h b/sys/sys/mutex.h index ec0c24163676..a9ec072f8d7a 100644 --- a/sys/sys/mutex.h +++ b/sys/sys/mutex.h @@ -188,8 +188,8 @@ void thread_lock_flags_(struct thread *, int, const char *, int); if (!_mtx_obtain_lock((mp), _tid)) \ _mtx_lock_sleep((mp), _tid, (opts), (file), (line)); \ else \ - LOCKSTAT_PROFILE_OBTAIN_LOCK_SUCCESS(LS_MTX_LOCK_ACQUIRE, \ - mp, 0, 0, (file), (line)); \ + LOCKSTAT_PROFILE_OBTAIN_LOCK_SUCCESS(adaptive__acquire, \ + mp, 0, 0, file, line); \ } while (0) /* @@ -209,8 +209,8 @@ void thread_lock_flags_(struct thread *, int, const char *, int); else \ _mtx_lock_spin((mp), _tid, (opts), (file), (line)); \ } else \ - LOCKSTAT_PROFILE_OBTAIN_LOCK_SUCCESS(LS_MTX_SPIN_LOCK_ACQUIRE, \ - mp, 0, 0, (file), (line)); \ + LOCKSTAT_PROFILE_OBTAIN_LOCK_SUCCESS(spin__acquire, \ + mp, 0, 0, file, line); \ } while (0) #else /* SMP */ #define __mtx_lock_spin(mp, tid, opts, file, line) do { \ @@ -231,8 +231,7 @@ void thread_lock_flags_(struct thread *, int, const char *, int); uintptr_t _tid = (uintptr_t)(tid); \ \ if ((mp)->mtx_recurse == 0) \ - LOCKSTAT_PROFILE_RELEASE_LOCK(LS_MTX_UNLOCK_RELEASE, \ - (mp)); \ + LOCKSTAT_PROFILE_RELEASE_LOCK(adaptive__release, mp); \ if (!_mtx_release_lock((mp), _tid)) \ _mtx_unlock_sleep((mp), (opts), (file), (line)); \ } while (0) @@ -252,21 +251,19 @@ void thread_lock_flags_(struct thread *, int, const char *, int); if (mtx_recursed((mp))) \ (mp)->mtx_recurse--; \ else { \ - LOCKSTAT_PROFILE_RELEASE_LOCK(LS_MTX_SPIN_UNLOCK_RELEASE, \ - mp); \ + LOCKSTAT_PROFILE_RELEASE_LOCK(spin__release, mp); \ _mtx_release_lock_quick((mp)); \ - } \ - spinlock_exit(); \ + } \ + spinlock_exit(); \ } while (0) #else /* SMP */ #define __mtx_unlock_spin(mp) do { \ if (mtx_recursed((mp))) \ (mp)->mtx_recurse--; \ else { \ - LOCKSTAT_PROFILE_RELEASE_LOCK(LS_MTX_SPIN_UNLOCK_RELEASE, \ - mp); \ + LOCKSTAT_PROFILE_RELEASE_LOCK(spin__release, mp); \ (mp)->mtx_lock = MTX_UNOWNED; \ - } \ + } \ spinlock_exit(); \ } while (0) #endif /* SMP */ diff --git a/lib/libmd/sha256.h b/sys/sys/numa.h similarity index 50% rename from lib/libmd/sha256.h rename to sys/sys/numa.h index f55d1d39d327..982f9e7ed2dc 100644 --- a/lib/libmd/sha256.h +++ b/sys/sys/numa.h @@ -1,5 +1,5 @@ -/*- - * Copyright 2005 Colin Percival +/* + * Copyright (c) 2015 Adrian Chadd . * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -10,6 +10,9 @@ * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE @@ -25,58 +28,14 @@ * * $FreeBSD$ */ +#ifndef __SYS_NUMA_H__ +#define __SYS_NUMA_H__ -#ifndef _SHA256_H_ -#define _SHA256_H_ +#include -#include +extern int numa_setaffinity(cpuwhich_t which, id_t id, + struct vm_domain_policy_entry *vd); +extern int numa_getaffinity(cpuwhich_t which, id_t id, + struct vm_domain_policy_entry *vd); -typedef struct SHA256Context { - uint32_t state[8]; - uint64_t count; - unsigned char buf[64]; -} SHA256_CTX; - -__BEGIN_DECLS - -/* Ensure libmd symbols do not clash with libcrypto */ - -#ifndef SHA256_Init -#define SHA256_Init _libmd_SHA256_Init -#endif -#ifndef SHA256_Update -#define SHA256_Update _libmd_SHA256_Update -#endif -#ifndef SHA256_Final -#define SHA256_Final _libmd_SHA256_Final -#endif -#ifndef SHA256_End -#define SHA256_End _libmd_SHA256_End -#endif -#ifndef SHA256_File -#define SHA256_File _libmd_SHA256_File -#endif -#ifndef SHA256_FileChunk -#define SHA256_FileChunk _libmd_SHA256_FileChunk -#endif -#ifndef SHA256_Data -#define SHA256_Data _libmd_SHA256_Data -#endif - -#ifndef SHA256_Transform -#define SHA256_Transform _libmd_SHA256_Transform -#endif -#ifndef SHA256_version -#define SHA256_version _libmd_SHA256_version -#endif - -void SHA256_Init(SHA256_CTX *); -void SHA256_Update(SHA256_CTX *, const void *, size_t); -void SHA256_Final(unsigned char [32], SHA256_CTX *); -char *SHA256_End(SHA256_CTX *, char *); -char *SHA256_File(const char *, char *); -char *SHA256_FileChunk(const char *, char *, off_t, off_t); -char *SHA256_Data(const void *, unsigned int, char *); -__END_DECLS - -#endif /* !_SHA256_H_ */ +#endif /* __SYS_NUMA_H__ */ diff --git a/sys/sys/proc.h b/sys/sys/proc.h index e6c83b43940b..40893ed34477 100644 --- a/sys/sys/proc.h +++ b/sys/sys/proc.h @@ -63,6 +63,7 @@ #endif #include #include +#include #include /* Machine-dependent proc substruct. */ /* @@ -217,6 +218,7 @@ struct thread { struct turnstile *td_turnstile; /* (k) Associated turnstile. */ struct rl_q_entry *td_rlqe; /* (k) Associated range lock entry. */ struct umtx_q *td_umtxq; /* (c?) Link for when we're blocked. */ + struct vm_domain_policy td_vm_dom_policy; /* (c) current numa domain policy */ lwpid_t td_tid; /* (b) Thread ID. */ sigqueue_t td_sigqueue; /* (c) Sigs arrived, not delivered. */ #define td_siglist td_sigqueue.sq_signals @@ -583,10 +585,10 @@ struct proc { pid_t p_reapsubtree; /* (e) Pid of the direct child of the reaper which spawned our subtree. */ + u_int p_xexit; /* (c) Exit code. */ + u_int p_xsig; /* (c) Stop/kill sig. */ /* End area that is copied on creation. */ -#define p_endcopy p_xstat - - u_short p_xstat; /* (c) Exit status; also stop sig. */ +#define p_endcopy p_xsig struct knlist p_klist; /* (c) Knotes attached to this proc. */ int p_numthreads; /* (c) Number of threads. */ struct mdproc p_md; /* Any machine-dependent fields. */ @@ -606,6 +608,7 @@ struct proc { uint64_t p_prev_runtime; /* (c) Resource usage accounting. */ struct racct *p_racct; /* (b) Resource accounting. */ u_char p_throttled; /* (c) Flag for racct pcpu throttling */ + struct vm_domain_policy p_vm_dom_policy; /* (c) process default VM domain, or -1 */ /* * An orphan is the child that has beed re-parented to the * debugger as a result of attaching to it. Need to keep @@ -967,7 +970,7 @@ void unsleep(struct thread *); void userret(struct thread *, struct trapframe *); void cpu_exit(struct thread *); -void exit1(struct thread *, int) __dead2; +void exit1(struct thread *, int, int) __dead2; struct syscall_args; int cpu_fetch_syscall_args(struct thread *td, struct syscall_args *sa); void cpu_fork(struct thread *, struct proc *, struct thread *, int); @@ -989,6 +992,8 @@ void thread_cow_get_proc(struct thread *newtd, struct proc *p); void thread_cow_get(struct thread *newtd, struct thread *td); void thread_cow_free(struct thread *td); void thread_cow_update(struct thread *td); +int thread_create(struct thread *td, struct rtprio *rtp, + int (*initialize_thread)(struct thread *, void *), void *thunk); void thread_exit(void) __dead2; void thread_free(struct thread *td); void thread_link(struct thread *td, struct proc *p); diff --git a/sys/sys/random.h b/sys/sys/random.h index 920d36b09431..78a9955a0e10 100644 --- a/sys/sys/random.h +++ b/sys/sys/random.h @@ -31,7 +31,12 @@ #ifdef _KERNEL +#include + +struct uio; + u_int read_random(void *, u_int); +int read_random_uio(struct uio *, bool); /* * Note: if you add or remove members of random_entropy_source, remember to also update the diff --git a/sys/sys/resourcevar.h b/sys/sys/resourcevar.h index d374472c8269..9612f12aacea 100644 --- a/sys/sys/resourcevar.h +++ b/sys/sys/resourcevar.h @@ -159,7 +159,5 @@ void ui_racct_foreach(void (*callback)(struct racct *racct, void *arg2, void *arg3), void *arg2, void *arg3); #endif -void lim_update_thread(struct thread *td); - #endif /* _KERNEL */ #endif /* !_SYS_RESOURCEVAR_H_ */ diff --git a/sys/sys/rwlock.h b/sys/sys/rwlock.h index b638d3efa0bf..f8947c55617a 100644 --- a/sys/sys/rwlock.h +++ b/sys/sys/rwlock.h @@ -95,12 +95,12 @@ /* Acquire a write lock. */ #define __rw_wlock(rw, tid, file, line) do { \ uintptr_t _tid = (uintptr_t)(tid); \ - \ + \ if (!_rw_write_lock((rw), _tid)) \ _rw_wlock_hard((rw), _tid, (file), (line)); \ else \ - LOCKSTAT_PROFILE_OBTAIN_LOCK_SUCCESS(LS_RW_WLOCK_ACQUIRE, \ - rw, 0, 0, (file), (line)); \ + LOCKSTAT_PROFILE_OBTAIN_RWLOCK_SUCCESS(rw__acquire, rw, \ + 0, 0, file, line, LOCKSTAT_WRITER); \ } while (0) /* Release a write lock. */ @@ -110,8 +110,8 @@ if ((rw)->rw_recurse) \ (rw)->rw_recurse--; \ else { \ - LOCKSTAT_PROFILE_RELEASE_LOCK(LS_RW_WUNLOCK_RELEASE, \ - (rw)); \ + LOCKSTAT_PROFILE_RELEASE_RWLOCK(rw__release, rw, \ + LOCKSTAT_WRITER); \ if (!_rw_write_unlock((rw), _tid)) \ _rw_wunlock_hard((rw), _tid, (file), (line)); \ } \ diff --git a/sys/sys/sx.h b/sys/sys/sx.h index 1da4356bebc6..96a664f35e52 100644 --- a/sys/sys/sx.h +++ b/sys/sys/sx.h @@ -153,8 +153,8 @@ __sx_xlock(struct sx *sx, struct thread *td, int opts, const char *file, if (!atomic_cmpset_acq_ptr(&sx->sx_lock, SX_LOCK_UNLOCKED, tid)) error = _sx_xlock_hard(sx, tid, opts, file, line); else - LOCKSTAT_PROFILE_OBTAIN_LOCK_SUCCESS(LS_SX_XLOCK_ACQUIRE, - sx, 0, 0, file, line); + LOCKSTAT_PROFILE_OBTAIN_RWLOCK_SUCCESS(sx__acquire, sx, + 0, 0, file, line, LOCKSTAT_WRITER); return (error); } @@ -166,7 +166,8 @@ __sx_xunlock(struct sx *sx, struct thread *td, const char *file, int line) uintptr_t tid = (uintptr_t)td; if (sx->sx_recurse == 0) - LOCKSTAT_PROFILE_RELEASE_LOCK(LS_SX_XUNLOCK_RELEASE, sx); + LOCKSTAT_PROFILE_RELEASE_RWLOCK(sx__release, sx, + LOCKSTAT_WRITER); if (!atomic_cmpset_rel_ptr(&sx->sx_lock, tid, SX_LOCK_UNLOCKED)) _sx_xunlock_hard(sx, tid, file, line); } @@ -182,8 +183,8 @@ __sx_slock(struct sx *sx, int opts, const char *file, int line) !atomic_cmpset_acq_ptr(&sx->sx_lock, x, x + SX_ONE_SHARER)) error = _sx_slock_hard(sx, opts, file, line); else - LOCKSTAT_PROFILE_OBTAIN_LOCK_SUCCESS(LS_SX_SLOCK_ACQUIRE, sx, 0, - 0, file, line); + LOCKSTAT_PROFILE_OBTAIN_RWLOCK_SUCCESS(sx__acquire, sx, + 0, 0, file, line, LOCKSTAT_READER); return (error); } @@ -200,7 +201,7 @@ __sx_sunlock(struct sx *sx, const char *file, int line) { uintptr_t x = sx->sx_lock; - LOCKSTAT_PROFILE_RELEASE_LOCK(LS_SX_SUNLOCK_RELEASE, sx); + LOCKSTAT_PROFILE_RELEASE_RWLOCK(sx__release, sx, LOCKSTAT_READER); if (x == (SX_SHARERS_LOCK(1) | SX_LOCK_EXCLUSIVE_WAITERS) || !atomic_cmpset_rel_ptr(&sx->sx_lock, x, x - SX_ONE_SHARER)) _sx_sunlock_hard(sx, file, line); diff --git a/sys/sys/syscall.h b/sys/sys/syscall.h index 5e757bf6cd78..2fb8c604ee02 100644 --- a/sys/sys/syscall.h +++ b/sys/sys/syscall.h @@ -465,4 +465,6 @@ #define SYS_ppoll 545 #define SYS_futimens 546 #define SYS_utimensat 547 -#define SYS_MAXSYSCALL 548 +#define SYS_numa_getaffinity 548 +#define SYS_numa_setaffinity 549 +#define SYS_MAXSYSCALL 550 diff --git a/sys/sys/syscall.mk b/sys/sys/syscall.mk index 50c02cb571af..e7d3a107f10d 100644 --- a/sys/sys/syscall.mk +++ b/sys/sys/syscall.mk @@ -412,4 +412,6 @@ MIASM = \ procctl.o \ ppoll.o \ futimens.o \ - utimensat.o + utimensat.o \ + numa_getaffinity.o \ + numa_setaffinity.o diff --git a/sys/sys/syscallsubr.h b/sys/sys/syscallsubr.h index 625f8341cbc3..d22c349bb678 100644 --- a/sys/sys/syscallsubr.h +++ b/sys/sys/syscallsubr.h @@ -85,7 +85,7 @@ int kern_clock_settime(struct thread *td, clockid_t clock_id, int kern_close(struct thread *td, int fd); int kern_connectat(struct thread *td, int dirfd, int fd, struct sockaddr *sa); -int kern_dup(struct thread *td, int flags, int old, int new); +int kern_dup(struct thread *td, u_int mode, int flags, int old, int new); int kern_execve(struct thread *td, struct image_args *args, struct mac *mac_p); int kern_fchmodat(struct thread *td, int fd, char *path, @@ -207,7 +207,7 @@ int kern_shmat(struct thread *td, int shmid, const void *shmaddr, int shmflg); int kern_shmctl(struct thread *td, int shmid, int cmd, void *buf, size_t *bufsz); -int kern_sigaction(struct thread *td, int sig, struct sigaction *act, +int kern_sigaction(struct thread *td, int sig, const struct sigaction *act, struct sigaction *oact, int flags); int kern_sigaltstack(struct thread *td, stack_t *ss, stack_t *oss); int kern_sigprocmask(struct thread *td, int how, diff --git a/sys/sys/sysent.h b/sys/sys/sysent.h index b1f61a9d06cc..980c79667fbc 100644 --- a/sys/sys/sysent.h +++ b/sys/sys/sysent.h @@ -153,6 +153,7 @@ struct sysentvec { /* same as ELFOSABI_XXX, to prevent header pollution */ #define SV_ABI_LINUX 3 #define SV_ABI_FREEBSD 9 +#define SV_ABI_CLOUDABI 17 #define SV_ABI_UNDEF 255 #ifdef _KERNEL diff --git a/sys/sys/sysproto.h b/sys/sys/sysproto.h index 3a3586172ab6..aaf7cbae9f36 100644 --- a/sys/sys/sysproto.h +++ b/sys/sys/sysproto.h @@ -1790,6 +1790,16 @@ struct utimensat_args { char times_l_[PADL_(struct timespec *)]; struct timespec * times; char times_r_[PADR_(struct timespec *)]; char flag_l_[PADL_(int)]; int flag; char flag_r_[PADR_(int)]; }; +struct numa_getaffinity_args { + char which_l_[PADL_(cpuwhich_t)]; cpuwhich_t which; char which_r_[PADR_(cpuwhich_t)]; + char id_l_[PADL_(id_t)]; id_t id; char id_r_[PADR_(id_t)]; + char policy_l_[PADL_(struct vm_domain_policy_entry *)]; struct vm_domain_policy_entry * policy; char policy_r_[PADR_(struct vm_domain_policy_entry *)]; +}; +struct numa_setaffinity_args { + char which_l_[PADL_(cpuwhich_t)]; cpuwhich_t which; char which_r_[PADR_(cpuwhich_t)]; + char id_l_[PADL_(id_t)]; id_t id; char id_r_[PADR_(id_t)]; + char policy_l_[PADL_(const struct vm_domain_policy_entry *)]; const struct vm_domain_policy_entry * policy; char policy_r_[PADR_(const struct vm_domain_policy_entry *)]; +}; int nosys(struct thread *, struct nosys_args *); void sys_sys_exit(struct thread *, struct sys_exit_args *); int sys_fork(struct thread *, struct fork_args *); @@ -2178,6 +2188,8 @@ int sys_procctl(struct thread *, struct procctl_args *); int sys_ppoll(struct thread *, struct ppoll_args *); int sys_futimens(struct thread *, struct futimens_args *); int sys_utimensat(struct thread *, struct utimensat_args *); +int sys_numa_getaffinity(struct thread *, struct numa_getaffinity_args *); +int sys_numa_setaffinity(struct thread *, struct numa_setaffinity_args *); #ifdef COMPAT_43 @@ -2931,6 +2943,8 @@ int freebsd7_shmctl(struct thread *, struct freebsd7_shmctl_args *); #define SYS_AUE_ppoll AUE_POLL #define SYS_AUE_futimens AUE_FUTIMES #define SYS_AUE_utimensat AUE_FUTIMESAT +#define SYS_AUE_numa_getaffinity AUE_NULL +#define SYS_AUE_numa_setaffinity AUE_NULL #undef PAD_ #undef PADL_ diff --git a/sys/sys/ucred.h b/sys/sys/ucred.h index 9a453087ff0e..d7e7fa5a947c 100644 --- a/sys/sys/ucred.h +++ b/sys/sys/ucred.h @@ -105,7 +105,6 @@ void change_svuid(struct ucred *newcred, uid_t svuid); void crcopy(struct ucred *dest, struct ucred *src); struct ucred *crcopysafe(struct proc *p, struct ucred *cr); struct ucred *crdup(struct ucred *cr); -void cred_update_thread(struct thread *td); void proc_set_cred_init(struct proc *p, struct ucred *cr); struct ucred *proc_set_cred(struct proc *p, struct ucred *cr); void crfree(struct ucred *cr); diff --git a/sys/sys/unpcb.h b/sys/sys/unpcb.h index ba63f3044374..41fd5745bbd7 100644 --- a/sys/sys/unpcb.h +++ b/sys/sys/unpcb.h @@ -106,6 +106,7 @@ struct unpcb { #define UNPGC_REF 0x1 /* unpcb has external ref. */ #define UNPGC_DEAD 0x2 /* unpcb might be dead. */ #define UNPGC_SCANNED 0x4 /* Has been scanned. */ +#define UNPGC_IGNORE_RIGHTS 0x8 /* Attached rights are freed */ /* * These flags are used to handle non-atomicity in connect() and bind() diff --git a/sys/sys/vnode.h b/sys/sys/vnode.h index 36ef8af08e89..41b610b5bd58 100644 --- a/sys/sys/vnode.h +++ b/sys/sys/vnode.h @@ -77,6 +77,7 @@ struct vpollinfo { * c - namecache mutex * f - freelist mutex * i - interlock + * I - updated with atomics, 0->1 and 1->0 transitions with interlock held * m - mount point interlock * p - pollinfo lock * u - Only a reference to the vnode is needed to read. @@ -162,8 +163,8 @@ struct vnode { daddr_t v_lastw; /* v last write */ int v_clen; /* v length of cur. cluster */ - int v_holdcnt; /* i prevents recycling. */ - int v_usecount; /* i ref count of users */ + u_int v_holdcnt; /* I prevents recycling. */ + u_int v_usecount; /* I ref count of users */ u_int v_iflag; /* i vnode flags (see below) */ u_int v_vflag; /* v vnode flags */ int v_writecount; /* v ref count of writers */ @@ -616,7 +617,6 @@ void cache_purge(struct vnode *vp); void cache_purge_negative(struct vnode *vp); void cache_purgevfs(struct mount *mp); int change_dir(struct vnode *vp, struct thread *td); -int change_root(struct vnode *vp, struct thread *td); void cvtstat(struct stat *st, struct ostat *ost); void cvtnstat(struct stat *sb, struct nstat *nsb); int getnewvnode(const char *tag, struct mount *mp, struct vop_vector *vops, @@ -652,13 +652,15 @@ int vaccess_acl_posix1e(enum vtype type, uid_t file_uid, struct ucred *cred, int *privused); void vattr_null(struct vattr *vap); int vcount(struct vnode *vp); -void vdrop(struct vnode *); -void vdropl(struct vnode *); +#define vdrop(vp) _vdrop((vp), 0) +#define vdropl(vp) _vdrop((vp), 1) +void _vdrop(struct vnode *, bool); int vflush(struct mount *mp, int rootrefs, int flags, struct thread *td); int vget(struct vnode *vp, int lockflag, struct thread *td); void vgone(struct vnode *vp); -void vhold(struct vnode *); -void vholdl(struct vnode *); +#define vhold(vp) _vhold((vp), 0) +#define vholdl(vp) _vhold((vp), 1) +void _vhold(struct vnode *, bool); void vinactive(struct vnode *, struct thread *); int vinvalbuf(struct vnode *vp, int save, int slpflag, int slptimeo); int vtruncbuf(struct vnode *vp, struct ucred *cred, off_t length, diff --git a/sys/sys/wait.h b/sys/sys/wait.h index 098830e3ef84..338211649f60 100644 --- a/sys/sys/wait.h +++ b/sys/sys/wait.h @@ -138,7 +138,19 @@ typedef enum #define WAIT_MYPGRP 0 /* any process in my process group */ #endif /* __BSD_VISIBLE */ +#if defined(_KERNEL) || defined(_WANT_KW_EXITCODE) + +/* + * Clamp the return code to the low 8 bits from full 32 bit value. + * Should be used in kernel to construct the wait(2)-compatible process + * status to usermode. + */ +#define KW_EXITCODE(ret, sig) W_EXITCODE((ret) & 0xff, (sig)) + +#endif /* _KERNEL || _WANT_KW_EXITCODE */ + #ifndef _KERNEL + #include __BEGIN_DECLS diff --git a/sys/ufs/ffs/ffs_alloc.c b/sys/ufs/ffs/ffs_alloc.c index 2b9c334f1691..c587dfb3bbe5 100644 --- a/sys/ufs/ffs/ffs_alloc.c +++ b/sys/ufs/ffs/ffs_alloc.c @@ -2748,13 +2748,12 @@ sysctl_ffs_fsck(SYSCTL_HANDLER_ARGS) struct thread *td = curthread; struct fsck_cmd cmd; struct ufsmount *ump; - struct vnode *vp, *vpold, *dvp, *fdvp; + struct vnode *vp, *dvp, *fdvp; struct inode *ip, *dp; struct mount *mp; struct fs *fs; ufs2_daddr_t blkno; long blkcnt, blksize; - struct filedesc *fdp; struct file *fp, *vfp; cap_rights_t rights; int filetype, error; @@ -2968,12 +2967,7 @@ sysctl_ffs_fsck(SYSCTL_HANDLER_ARGS) break; } VOP_UNLOCK(vp, 0); - fdp = td->td_proc->p_fd; - FILEDESC_XLOCK(fdp); - vpold = fdp->fd_cdir; - fdp->fd_cdir = vp; - FILEDESC_XUNLOCK(fdp); - vrele(vpold); + pwd_chdir(td, vp); break; case FFS_SET_DOTDOT: diff --git a/sys/vm/vm_domain.c b/sys/vm/vm_domain.c new file mode 100644 index 000000000000..83814d516d11 --- /dev/null +++ b/sys/vm/vm_domain.c @@ -0,0 +1,374 @@ +/*- + * Copyright (c) 2015 Adrian Chadd . + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include "opt_vm.h" +#include "opt_ddb.h" + +#include +#include +#include +#include +#include +#include +#if MAXMEMDOM > 1 +#include +#endif +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + +#include + +static __inline int +vm_domain_rr_selectdomain(void) +{ +#if MAXMEMDOM > 1 + struct thread *td; + + td = curthread; + + td->td_dom_rr_idx++; + td->td_dom_rr_idx %= vm_ndomains; + return (td->td_dom_rr_idx); +#else + return (0); +#endif +} + +/* + * This implements a very simple set of VM domain memory allocation + * policies and iterators. + */ + +/* + * A VM domain policy represents a desired VM domain policy. + * Iterators implement searching through VM domains in a specific + * order. + */ + +/* + * When setting a policy, the caller must establish their own + * exclusive write protection for the contents of the domain + * policy. + */ +int +vm_domain_policy_init(struct vm_domain_policy *vp) +{ + + bzero(vp, sizeof(*vp)); + vp->p.policy = VM_POLICY_NONE; + vp->p.domain = -1; + return (0); +} + +int +vm_domain_policy_set(struct vm_domain_policy *vp, + vm_domain_policy_type_t vt, int domain) +{ + + seq_write_begin(&vp->seq); + vp->p.policy = vt; + vp->p.domain = domain; + seq_write_end(&vp->seq); + return (0); +} + +/* + * Take a local copy of a policy. + * + * The destination policy isn't write-barriered; this is used + * for doing local copies into something that isn't shared. + */ +void +vm_domain_policy_localcopy(struct vm_domain_policy *dst, + const struct vm_domain_policy *src) +{ + seq_t seq; + + for (;;) { + seq = seq_read(&src->seq); + *dst = *src; + if (seq_consistent(&src->seq, seq)) + return; + cpu_spinwait(); + } +} + +/* + * Take a write-barrier copy of a policy. + * + * The destination policy is write -barriered; this is used + * for doing copies into policies that may be read by other + * threads. + */ +void +vm_domain_policy_copy(struct vm_domain_policy *dst, + const struct vm_domain_policy *src) +{ + seq_t seq; + struct vm_domain_policy d; + + for (;;) { + seq = seq_read(&src->seq); + d = *src; + if (seq_consistent(&src->seq, seq)) { + seq_write_begin(&dst->seq); + dst->p.domain = d.p.domain; + dst->p.policy = d.p.policy; + seq_write_end(&dst->seq); + return; + } + cpu_spinwait(); + } +} + +int +vm_domain_policy_validate(const struct vm_domain_policy *vp) +{ + + switch (vp->p.policy) { + case VM_POLICY_NONE: + case VM_POLICY_ROUND_ROBIN: + case VM_POLICY_FIRST_TOUCH: + case VM_POLICY_FIRST_TOUCH_ROUND_ROBIN: + if (vp->p.domain == -1) + return (0); + return (-1); + case VM_POLICY_FIXED_DOMAIN: + case VM_POLICY_FIXED_DOMAIN_ROUND_ROBIN: + if (vp->p.domain >= 0 && vp->p.domain < vm_ndomains) + return (0); + return (-1); + default: + return (-1); + } + return (-1); +} + +int +vm_domain_policy_cleanup(struct vm_domain_policy *vp) +{ + + /* For now, empty */ + return (0); +} + +int +vm_domain_iterator_init(struct vm_domain_iterator *vi) +{ + + /* Nothing to do for now */ + return (0); +} + +/* + * Manually setup an iterator with the given details. + */ +int +vm_domain_iterator_set(struct vm_domain_iterator *vi, + vm_domain_policy_type_t vt, int domain) +{ + + switch (vt) { + case VM_POLICY_FIXED_DOMAIN: + vi->policy = VM_POLICY_FIXED_DOMAIN; + vi->domain = domain; + vi->n = 1; + break; + case VM_POLICY_FIXED_DOMAIN_ROUND_ROBIN: + vi->policy = VM_POLICY_FIXED_DOMAIN_ROUND_ROBIN; + vi->domain = domain; + vi->n = vm_ndomains; + break; + case VM_POLICY_FIRST_TOUCH: + vi->policy = VM_POLICY_FIRST_TOUCH; + vi->domain = PCPU_GET(domain); + vi->n = 1; + break; + case VM_POLICY_FIRST_TOUCH_ROUND_ROBIN: + vi->policy = VM_POLICY_FIRST_TOUCH_ROUND_ROBIN; + vi->domain = PCPU_GET(domain); + vi->n = vm_ndomains; + break; + case VM_POLICY_ROUND_ROBIN: + default: + vi->policy = VM_POLICY_ROUND_ROBIN; + vi->domain = -1; + vi->n = vm_ndomains; + break; + } + return (0); +} + +/* + * Setup an iterator based on the given policy. + */ +static inline void +_vm_domain_iterator_set_policy(struct vm_domain_iterator *vi, + const struct vm_domain_policy *vt) +{ + /* + * Initialise the iterator. + * + * For first-touch, the initial domain is set + * via the current thread CPU domain. + * + * For fixed-domain, it's assumed that the + * caller has initialised the specific domain + * it is after. + */ + switch (vt->p.policy) { + case VM_POLICY_FIXED_DOMAIN: + vi->policy = vt->p.policy; + vi->domain = vt->p.domain; + vi->n = 1; + break; + case VM_POLICY_FIXED_DOMAIN_ROUND_ROBIN: + vi->policy = vt->p.policy; + vi->domain = vt->p.domain; + vi->n = vm_ndomains; + break; + case VM_POLICY_FIRST_TOUCH: + vi->policy = vt->p.policy; + vi->domain = PCPU_GET(domain); + vi->n = 1; + break; + case VM_POLICY_FIRST_TOUCH_ROUND_ROBIN: + vi->policy = vt->p.policy; + vi->domain = PCPU_GET(domain); + vi->n = vm_ndomains; + break; + case VM_POLICY_ROUND_ROBIN: + default: + /* + * Default to round-robin policy. + */ + vi->policy = VM_POLICY_ROUND_ROBIN; + vi->domain = -1; + vi->n = vm_ndomains; + break; + } +} + +void +vm_domain_iterator_set_policy(struct vm_domain_iterator *vi, + const struct vm_domain_policy *vt) +{ + seq_t seq; + struct vm_domain_policy vt_lcl; + + for (;;) { + seq = seq_read(&vt->seq); + vt_lcl = *vt; + if (seq_consistent(&vt->seq, seq)) { + _vm_domain_iterator_set_policy(vi, &vt_lcl); + return; + } + cpu_spinwait(); + } +} + +/* + * Return the next VM domain to use. + * + * Returns 0 w/ domain set to the next domain to use, or + * -1 to indicate no more domains are available. + */ +int +vm_domain_iterator_run(struct vm_domain_iterator *vi, int *domain) +{ + + /* General catch-all */ + if (vi->n <= 0) + return (-1); + + switch (vi->policy) { + case VM_POLICY_FIXED_DOMAIN: + case VM_POLICY_FIRST_TOUCH: + *domain = vi->domain; + vi->n--; + break; + case VM_POLICY_FIXED_DOMAIN_ROUND_ROBIN: + case VM_POLICY_FIRST_TOUCH_ROUND_ROBIN: + /* + * XXX TODO: skip over the rr'ed domain + * if it equals the one we started with. + */ + if (vi->n == vm_ndomains) + *domain = vi->domain; + else + *domain = vm_domain_rr_selectdomain(); + vi->n--; + break; + case VM_POLICY_ROUND_ROBIN: + default: + *domain = vm_domain_rr_selectdomain(); + vi->n--; + break; + } + + return (0); +} + +/* + * Returns 1 if the iteration is done, or 0 if it has not. + + * This can only be called after at least one loop through + * the iterator. Ie, it's designed to be used as a tail + * check of a loop, not the head check of a loop. + */ +int +vm_domain_iterator_isdone(struct vm_domain_iterator *vi) +{ + + return (vi->n <= 0); +} + +int +vm_domain_iterator_cleanup(struct vm_domain_iterator *vi) +{ + + return (0); +} diff --git a/sys/vm/vm_domain.h b/sys/vm/vm_domain.h new file mode 100644 index 000000000000..7d9e07c23628 --- /dev/null +++ b/sys/vm/vm_domain.h @@ -0,0 +1,66 @@ +/*- + * Copyright (c) 2015 Adrian Chadd . + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + * $FreeBSD$ + */ +#ifndef __VM_DOMAIN_H__ +#define __VM_DOMAIN_H__ + +#include + +struct vm_domain_iterator { + vm_domain_policy_type_t policy; + int domain; + int n; +}; + +/* + * TODO: check to see if these should just become inline functions + * at some point. + */ +extern int vm_domain_policy_init(struct vm_domain_policy *vp); +extern int vm_domain_policy_set(struct vm_domain_policy *vp, + vm_domain_policy_type_t vt, int domain); +extern int vm_domain_policy_cleanup(struct vm_domain_policy *vp); +extern void vm_domain_policy_localcopy(struct vm_domain_policy *dst, + const struct vm_domain_policy *src); +extern void vm_domain_policy_copy(struct vm_domain_policy *dst, + const struct vm_domain_policy *src); +extern int vm_domain_policy_validate(const struct vm_domain_policy *vp); + +extern int vm_domain_iterator_init(struct vm_domain_iterator *vi); +extern int vm_domain_iterator_set(struct vm_domain_iterator *vi, + vm_domain_policy_type_t vt, int domain); +extern void vm_domain_iterator_set_policy(struct vm_domain_iterator *vi, + const struct vm_domain_policy *vt); +extern int vm_domain_iterator_run(struct vm_domain_iterator *vi, + int *domain); +extern int vm_domain_iterator_isdone(struct vm_domain_iterator *vi); +extern int vm_domain_iterator_cleanup(struct vm_domain_iterator *vi); + +#endif /* __VM_DOMAIN_H__ */ diff --git a/sys/vm/vm_phys.c b/sys/vm/vm_phys.c index 71fadd75893d..d26b8b580952 100644 --- a/sys/vm/vm_phys.c +++ b/sys/vm/vm_phys.c @@ -57,6 +57,7 @@ __FBSDID("$FreeBSD$"); #include #include #include +#include #include @@ -67,6 +68,8 @@ __FBSDID("$FreeBSD$"); #include #include +#include + _Static_assert(sizeof(long) * NBBY >= VM_PHYSSEG_MAX, "Too many physsegs."); @@ -141,13 +144,30 @@ static int sysctl_vm_phys_segs(SYSCTL_HANDLER_ARGS); SYSCTL_OID(_vm, OID_AUTO, phys_segs, CTLTYPE_STRING | CTLFLAG_RD, NULL, 0, sysctl_vm_phys_segs, "A", "Phys Seg Info"); +#if MAXMEMDOM > 1 static int sysctl_vm_phys_locality(SYSCTL_HANDLER_ARGS); SYSCTL_OID(_vm, OID_AUTO, phys_locality, CTLTYPE_STRING | CTLFLAG_RD, NULL, 0, sysctl_vm_phys_locality, "A", "Phys Locality Info"); +#endif SYSCTL_INT(_vm, OID_AUTO, ndomains, CTLFLAG_RD, &vm_ndomains, 0, "Number of physical memory domains available."); +/* + * Default to first-touch + round-robin. + */ +static struct mtx vm_default_policy_mtx; +MTX_SYSINIT(vm_default_policy, &vm_default_policy_mtx, "default policy mutex", + MTX_DEF); +#if MAXMEMDOM > 1 +static struct vm_domain_policy vm_default_policy = + VM_DOMAIN_POLICY_STATIC_INITIALISER(VM_POLICY_FIRST_TOUCH_ROUND_ROBIN, 0); +#else +/* Use round-robin so the domain policy code will only try once per allocation */ +static struct vm_domain_policy vm_default_policy = + VM_DOMAIN_POLICY_STATIC_INITIALISER(VM_POLICY_ROUND_ROBIN, 0); +#endif + static vm_page_t vm_phys_alloc_domain_pages(int domain, int flind, int pool, int order); static void _vm_phys_create_seg(vm_paddr_t start, vm_paddr_t end, int domain); @@ -156,6 +176,60 @@ static int vm_phys_paddr_to_segind(vm_paddr_t pa); static void vm_phys_split_pages(vm_page_t m, int oind, struct vm_freelist *fl, int order); +static int +sysctl_vm_default_policy(SYSCTL_HANDLER_ARGS) +{ + char policy_name[32]; + int error; + + mtx_lock(&vm_default_policy_mtx); + + /* Map policy to output string */ + switch (vm_default_policy.p.policy) { + case VM_POLICY_FIRST_TOUCH: + strcpy(policy_name, "first-touch"); + break; + case VM_POLICY_FIRST_TOUCH_ROUND_ROBIN: + strcpy(policy_name, "first-touch-rr"); + break; + case VM_POLICY_ROUND_ROBIN: + default: + strcpy(policy_name, "rr"); + break; + } + mtx_unlock(&vm_default_policy_mtx); + + error = sysctl_handle_string(oidp, &policy_name[0], + sizeof(policy_name), req); + if (error != 0 || req->newptr == NULL) + return (error); + + mtx_lock(&vm_default_policy_mtx); + /* Set: match on the subset of policies that make sense as a default */ + if (strcmp("first-touch-rr", policy_name) == 0) { + vm_domain_policy_set(&vm_default_policy, + VM_POLICY_FIRST_TOUCH_ROUND_ROBIN, 0); + } else if (strcmp("first-touch", policy_name) == 0) { + vm_domain_policy_set(&vm_default_policy, + VM_POLICY_FIRST_TOUCH, 0); + } else if (strcmp("rr", policy_name) == 0) { + vm_domain_policy_set(&vm_default_policy, + VM_POLICY_ROUND_ROBIN, 0); + } else { + error = EINVAL; + goto finish; + } + + error = 0; +finish: + mtx_unlock(&vm_default_policy_mtx); + return (error); +} + +SYSCTL_PROC(_vm, OID_AUTO, default_policy, CTLTYPE_STRING | CTLFLAG_RW, + 0, 0, sysctl_vm_default_policy, "A", + "Default policy (rr, first-touch, first-touch-rr"); + /* * Red-black tree helpers for vm fictitious range management. */ @@ -213,6 +287,53 @@ vm_rr_selectdomain(void) #endif } +/* + * Initialise a VM domain iterator. + * + * Check the thread policy, then the proc policy, + * then default to the system policy. + * + * Later on the various layers will have this logic + * plumbed into them and the phys code will be explicitly + * handed a VM domain policy to use. + */ +static void +vm_policy_iterator_init(struct vm_domain_iterator *vi) +{ +#if MAXMEMDOM > 1 + struct vm_domain_policy lcl; +#endif + + vm_domain_iterator_init(vi); + +#if MAXMEMDOM > 1 + /* Copy out the thread policy */ + vm_domain_policy_localcopy(&lcl, &curthread->td_vm_dom_policy); + if (lcl.p.policy != VM_POLICY_NONE) { + /* Thread policy is present; use it */ + vm_domain_iterator_set_policy(vi, &lcl); + return; + } + + vm_domain_policy_localcopy(&lcl, + &curthread->td_proc->p_vm_dom_policy); + if (lcl.p.policy != VM_POLICY_NONE) { + /* Process policy is present; use it */ + vm_domain_iterator_set_policy(vi, &lcl); + return; + } +#endif + /* Use system default policy */ + vm_domain_iterator_set_policy(vi, &vm_default_policy); +} + +static void +vm_policy_iterator_finish(struct vm_domain_iterator *vi) +{ + + vm_domain_iterator_cleanup(vi); +} + boolean_t vm_phys_domain_intersects(long mask, vm_paddr_t low, vm_paddr_t high) { @@ -305,17 +426,22 @@ sysctl_vm_phys_segs(SYSCTL_HANDLER_ARGS) /* * Return affinity, or -1 if there's no affinity information. */ -static int +int vm_phys_mem_affinity(int f, int t) { +#if MAXMEMDOM > 1 if (mem_locality == NULL) return (-1); if (f >= vm_ndomains || t >= vm_ndomains) return (-1); return (mem_locality[f * vm_ndomains + t]); +#else + return (-1); +#endif } +#if MAXMEMDOM > 1 /* * Outputs the VM locality table. */ @@ -343,6 +469,7 @@ sysctl_vm_phys_locality(SYSCTL_HANDLER_ARGS) sbuf_delete(&sbuf); return (error); } +#endif static void vm_freelist_add(struct vm_freelist *fl, vm_page_t m, int order, int tail) @@ -634,15 +761,17 @@ vm_page_t vm_phys_alloc_pages(int pool, int order) { vm_page_t m; - int dom, domain, flind; + int domain, flind; + struct vm_domain_iterator vi; KASSERT(pool < VM_NFREEPOOL, ("vm_phys_alloc_pages: pool %d is out of range", pool)); KASSERT(order < VM_NFREEORDER, ("vm_phys_alloc_pages: order %d is out of range", order)); - for (dom = 0; dom < vm_ndomains; dom++) { - domain = vm_rr_selectdomain(); + vm_policy_iterator_init(&vi); + + while ((vm_domain_iterator_run(&vi, &domain)) == 0) { for (flind = 0; flind < vm_nfreelists; flind++) { m = vm_phys_alloc_domain_pages(domain, flind, pool, order); @@ -650,6 +779,8 @@ vm_phys_alloc_pages(int pool, int order) return (m); } } + + vm_policy_iterator_finish(&vi); return (NULL); } @@ -664,7 +795,8 @@ vm_page_t vm_phys_alloc_freelist_pages(int freelist, int pool, int order) { vm_page_t m; - int dom, domain; + struct vm_domain_iterator vi; + int domain; KASSERT(freelist < VM_NFREELIST, ("vm_phys_alloc_freelist_pages: freelist %d is out of range", @@ -673,13 +805,17 @@ vm_phys_alloc_freelist_pages(int freelist, int pool, int order) ("vm_phys_alloc_freelist_pages: pool %d is out of range", pool)); KASSERT(order < VM_NFREEORDER, ("vm_phys_alloc_freelist_pages: order %d is out of range", order)); - for (dom = 0; dom < vm_ndomains; dom++) { - domain = vm_rr_selectdomain(); + + vm_policy_iterator_init(&vi); + + while ((vm_domain_iterator_run(&vi, &domain)) == 0) { m = vm_phys_alloc_domain_pages(domain, vm_freelist_to_flind[freelist], pool, order); if (m != NULL) return (m); } + + vm_policy_iterator_finish(&vi); return (NULL); } @@ -1169,7 +1305,8 @@ vm_phys_alloc_contig(u_long npages, vm_paddr_t low, vm_paddr_t high, vm_paddr_t pa, pa_last, size; vm_page_t m, m_ret; u_long npages_end; - int dom, domain, flind, oind, order, pind; + int domain, flind, oind, order, pind; + struct vm_domain_iterator vi; mtx_assert(&vm_page_queue_free_mtx, MA_OWNED); size = npages << PAGE_SHIFT; @@ -1181,9 +1318,15 @@ vm_phys_alloc_contig(u_long npages, vm_paddr_t low, vm_paddr_t high, ("vm_phys_alloc_contig: boundary must be a power of 2")); /* Compute the queue that is the best fit for npages. */ for (order = 0; (1 << order) < npages; order++); - dom = 0; + + vm_policy_iterator_init(&vi); + restartdom: - domain = vm_rr_selectdomain(); + if (vm_domain_iterator_run(&vi, &domain) != 0) { + vm_policy_iterator_finish(&vi); + return (NULL); + } + for (flind = 0; flind < vm_nfreelists; flind++) { for (oind = min(order, VM_NFREEORDER - 1); oind < VM_NFREEORDER; oind++) { for (pind = 0; pind < VM_NFREEPOOL; pind++) { @@ -1241,8 +1384,9 @@ restartdom: } } } - if (++dom < vm_ndomains) + if (!vm_domain_iterator_isdone(&vi)) goto restartdom; + vm_policy_iterator_finish(&vi); return (NULL); done: for (m = m_ret; m < &m_ret[npages]; m = &m[1 << oind]) { diff --git a/sys/vm/vm_phys.h b/sys/vm/vm_phys.h index 575b93cde1a6..37864dbd832b 100644 --- a/sys/vm/vm_phys.h +++ b/sys/vm/vm_phys.h @@ -87,6 +87,7 @@ vm_page_t vm_phys_paddr_to_vm_page(vm_paddr_t pa); void vm_phys_set_pool(int pool, vm_page_t m, int order); boolean_t vm_phys_unfree_page(vm_page_t m); boolean_t vm_phys_zero_pages_idle(void); +int vm_phys_mem_affinity(int f, int t); /* * vm_phys_domain: diff --git a/sys/x86/iommu/intel_idpgtbl.c b/sys/x86/iommu/intel_idpgtbl.c index e105b9b13b75..405976b26801 100644 --- a/sys/x86/iommu/intel_idpgtbl.c +++ b/sys/x86/iommu/intel_idpgtbl.c @@ -386,7 +386,7 @@ retry: * Prevent potential free while pgtbl_obj is * unlocked in the recursive call to * domain_pgtbl_map_pte(), if other thread did - * pte write and clean while the lock if + * pte write and clean while the lock is * dropped. */ m->wire_count++; diff --git a/sys/x86/x86/local_apic.c b/sys/x86/x86/local_apic.c index d75a45236ea2..cf2114dbc911 100644 --- a/sys/x86/x86/local_apic.c +++ b/sys/x86/x86/local_apic.c @@ -204,6 +204,7 @@ lapic_write32_nofence(enum LAPIC_REGISTERS reg, uint32_t val) } } +#ifdef SMP static uint64_t lapic_read_icr(void) { @@ -241,6 +242,7 @@ lapic_write_icr(uint32_t vhi, uint32_t vlo) lapic_write32(LAPIC_ICR_LO, vlo); } } +#endif /* SMP */ static void native_lapic_enable_x2apic(void) @@ -292,9 +294,6 @@ static int native_lapic_enable_pmc(void); static void native_lapic_disable_pmc(void); static void native_lapic_reenable_pmc(void); static void native_lapic_enable_cmc(void); -static void native_lapic_ipi_raw(register_t icrlo, u_int dest); -static void native_lapic_ipi_vectored(u_int vector, int dest); -static int native_lapic_ipi_wait(int delay); static int native_lapic_set_lvt_mask(u_int apic_id, u_int lvt, u_char masked); static int native_lapic_set_lvt_mode(u_int apic_id, u_int lvt, @@ -303,8 +302,13 @@ static int native_lapic_set_lvt_polarity(u_int apic_id, u_int lvt, enum intr_polarity pol); static int native_lapic_set_lvt_triggermode(u_int apic_id, u_int lvt, enum intr_trigger trigger); +#ifdef SMP +static void native_lapic_ipi_raw(register_t icrlo, u_int dest); +static void native_lapic_ipi_vectored(u_int vector, int dest); +static int native_lapic_ipi_wait(int delay); static int native_lapic_ipi_alloc(inthand_t *ipifunc); static void native_lapic_ipi_free(int vector); +#endif /* SMP */ struct apic_ops apic_ops = { .create = native_lapic_create, diff --git a/sys/x86/xen/pv.c b/sys/x86/xen/pv.c index 233bf3e013b9..6b913fb9cb4e 100644 --- a/sys/x86/xen/pv.c +++ b/sys/x86/xen/pv.c @@ -31,6 +31,7 @@ __FBSDID("$FreeBSD$"); #include "opt_ddb.h" +#include "opt_kstack_pages.h" #include #include diff --git a/tools/build/mk/OptionalObsoleteFiles.inc b/tools/build/mk/OptionalObsoleteFiles.inc index 476b01855a9d..4bec221e0f1f 100644 --- a/tools/build/mk/OptionalObsoleteFiles.inc +++ b/tools/build/mk/OptionalObsoleteFiles.inc @@ -5138,7 +5138,10 @@ OLD_FILES+=usr/share/misc/mail.tildehelp .if ${MK_MAILWRAPPER} == no OLD_FILES+=etc/mail/mailer.conf -OLD_FILES+=usr/sbin/mailwrapper +# Don't remove, for no mailwrapper case: +# /usr/sbin/sendmail -> /usr/sbin/mailwrapper +# /usr/sbin/mailwrapper -> /usr/libexec/sendmail/sendmail +#OLD_FILES+=usr/sbin/mailwrapper OLD_FILES+=usr/share/man/man8/mailwrapper.8.gz .endif diff --git a/tools/regression/lib/libc/nss/test-getaddr.c b/tools/regression/lib/libc/nss/test-getaddr.c index 309c94b1c242..aae1605f6860 100644 --- a/tools/regression/lib/libc/nss/test-getaddr.c +++ b/tools/regression/lib/libc/nss/test-getaddr.c @@ -448,6 +448,7 @@ main(int argc, char **argv) switch (c) { case '4': hints.ai_family = PF_INET; + break; case '6': hints.ai_family = PF_INET6; break; diff --git a/usr.bin/Makefile b/usr.bin/Makefile index 1187dc2c1a56..fd786025fa78 100644 --- a/usr.bin/Makefile +++ b/usr.bin/Makefile @@ -117,6 +117,7 @@ SUBDIR= ${_addr2line} \ nice \ nl \ ${_nm} \ + numactl \ nohup \ opieinfo \ opiekey \ diff --git a/usr.bin/c99/c99.1 b/usr.bin/c99/c99.1 index 36864956cc1e..c993397496f6 100644 --- a/usr.bin/c99/c99.1 +++ b/usr.bin/c99/c99.1 @@ -26,7 +26,7 @@ .\" From FreeBSD: src/usr.bin/c89/c89.1,v 1.11 2007/03/10 07:10:01 ru Exp .\" $FreeBSD$ .\" -.Dd June 17, 2010 +.Dd July 13, 2015 .Dt C99 1 .Os .Sh NAME @@ -188,12 +188,3 @@ The .Nm utility interface conforms to .St -p1003.1-2001 . -Since it is a wrapper around -.Tn GCC , -it is limited to the -.Tn C99 -features that -.Tn GCC -actually implements. -See -.Pa http://gcc.gnu.org/gcc-4.2/c99status.html . diff --git a/usr.bin/calendar/io.c b/usr.bin/calendar/io.c index 5e5c146459d9..89863f45d7f0 100644 --- a/usr.bin/calendar/io.c +++ b/usr.bin/calendar/io.c @@ -87,11 +87,16 @@ static void trimlr(char **buf) { char *walk = *buf; + char *last; while (isspace(*walk)) walk++; - while (isspace(walk[strlen(walk) -1])) - walk[strlen(walk) -1] = '\0'; + if (*walk != '\0') { + last = walk + strlen(walk) - 1; + while (last > walk && isspace(*last)) + last--; + *(last+1) = 0; + } *buf = walk; } diff --git a/usr.bin/last/last.c b/usr.bin/last/last.c index 945cc4119ee0..1db10b399dfa 100644 --- a/usr.bin/last/last.c +++ b/usr.bin/last/last.c @@ -64,6 +64,7 @@ __FBSDID("$FreeBSD$"); typedef struct arg { char *name; /* argument */ +#define REBOOT_TYPE -1 #define HOST_TYPE -2 #define TTY_TYPE -3 #define USER_TYPE -4 @@ -180,6 +181,8 @@ main(int argc, char *argv[]) if (argc) { setlinebuf(stdout); for (argv += optind; *argv; ++argv) { + if (strcmp(*argv, "reboot") == 0) + addarg(REBOOT_TYPE, *argv); #define COMPATIBILITY #ifdef COMPATIBILITY /* code to allow "last p5" to work */ @@ -389,6 +392,11 @@ want(struct utmpx *bp) for (step = arglist; step; step = step->next) switch(step->type) { + case REBOOT_TYPE: + if (bp->ut_type == BOOT_TIME || + bp->ut_type == SHUTDOWN_TIME) + return (YES); + break; case HOST_TYPE: if (!strcasecmp(step->name, bp->ut_host)) return (YES); diff --git a/usr.bin/ministat/ministat.c b/usr.bin/ministat/ministat.c index 4c0ddd056a64..59beac7127f9 100644 --- a/usr.bin/ministat/ministat.c +++ b/usr.bin/ministat/ministat.c @@ -487,7 +487,7 @@ ReadSet(const char *n, int column, const char *delim) d = strtod(t, &p); if (p != NULL && *p != '\0') - err(2, "Invalid data on line %d in %s\n", line, n); + errx(2, "Invalid data on line %d in %s", line, n); if (*buf != '\0') AddPoint(s, d); } diff --git a/usr.bin/netstat/main.c b/usr.bin/netstat/main.c index acc27f773878..477add6fe06b 100644 --- a/usr.bin/netstat/main.c +++ b/usr.bin/netstat/main.c @@ -776,19 +776,31 @@ kread_counter(u_long addr) int kread_counters(u_long addr, void *buf, size_t size) { - uint64_t *c = buf; + uint64_t *c; + u_long *counters; + size_t i, n; if (kvmd_init() < 0) return (-1); - if (kread(addr, buf, size) < 0) + if (size % sizeof(uint64_t) != 0) { + xo_warnx("kread_counters: invalid counter set size"); return (-1); - - while (size != 0) { - *c = kvm_counter_u64_fetch(kvmd, *c); - size -= sizeof(*c); - c++; } + + n = size / sizeof(uint64_t); + if ((counters = malloc(n * sizeof(u_long))) == NULL) + xo_err(-1, "malloc"); + if (kread(addr, counters, n * sizeof(u_long)) < 0) { + free(counters); + return (-1); + } + + c = buf; + for (i = 0; i < n; i++) + c[i] = kvm_counter_u64_fetch(kvmd, counters[i]); + + free(counters); return (0); } diff --git a/usr.bin/netstat/pfkey.c b/usr.bin/netstat/pfkey.c index fbf330f88246..1a60b488462c 100644 --- a/usr.bin/netstat/pfkey.c +++ b/usr.bin/netstat/pfkey.c @@ -128,7 +128,7 @@ pfkey_stats(u_long off, const char *name, int family __unused, xo_emit(m, (uintmax_t)pfkeystat.f, plural(pfkeystat.f)) /* userland -> kernel */ - p(out_total, "\t{:sent-requests//%ju} " + p(out_total, "\t{:sent-requests/%ju} " "{N:/request%s sent from userland}\n"); p(out_bytes, "\t{:sent-bytes/%ju} " "{N:/byte%s sent from userland}\n"); @@ -165,7 +165,7 @@ pfkey_stats(u_long off, const char *name, int family __unused, "{N:/message%s with duplicate extension}\n"); p(out_invexttype, "\t{:dropped-bad-extension/%ju} " "{N:/message%s with invalid extension type}\n"); - p(out_invsatype, "\t:dropped-bad-sa-type/%ju} " + p(out_invsatype, "\t{:dropped-bad-sa-type/%ju} " "{N:/message%s with invalid sa type}\n"); p(out_invaddr, "\t{:dropped-bad-address-extension/%ju} " "{N:/message%s with invalid address extension}\n"); diff --git a/usr.bin/numactl/Makefile b/usr.bin/numactl/Makefile new file mode 100644 index 000000000000..715848724cf7 --- /dev/null +++ b/usr.bin/numactl/Makefile @@ -0,0 +1,5 @@ +# $FreeBSD$ + +PROG= numactl + +.include diff --git a/usr.bin/numactl/numactl.1 b/usr.bin/numactl/numactl.1 new file mode 100644 index 000000000000..750e23b5125b --- /dev/null +++ b/usr.bin/numactl/numactl.1 @@ -0,0 +1,132 @@ +.\" Copyright (c) 2015 Adrian Chadd +.\" All rights reserved. +.\" +.\" Redistribution and use in source and binary forms, with or without +.\" modification, are permitted provided that the following conditions +.\" are met: +.\" 1. Redistributions of source code must retain the above copyright +.\" notice, this list of conditions and the following disclaimer. +.\" 2. Redistributions in binary form must reproduce the above copyright +.\" notice, this list of conditions and the following disclaimer in the +.\" documentation and/or other materials provided with the distribution. +.\" +.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +.\" SUCH DAMAGE. +.\" +.\" $FreeBSD$ +.\" +.Dd May 9, 2015 +.Dt NUMACTL 1 +.Os +.Sh NAME +.Nm numactl +.Nd "manage NUMA policy configuration" +.Sh SYNOPSIS +.Nm +.Op Fl l Ar policy +.Op Fl m Ar domain +.Op Fl c Ar domain +.Ar cmd ... +.Nm +.Fl g +.Op Fl p Ar pid +.Op Fl t Ar tid +.Nm +.Fl s +.Op Fl l Ar policy +.Op Fl m Ar domain +.Op Fl c Ar domain +.Op Fl p Ar pid +.Op Fl t Ar tid +.Sh DESCRIPTION +The +.Nm +command can be used to assign NUMA policies to processes/threads, +run commands with a given NUMA policy, and query information +about NUMA policies on running processes. +.Pp +.Nm +requires a target to modify or query. +The target may be specified as a command, process id or a thread id. +Using +.Fl -get +the target's NUMA policy may be queried. +Using +.Fl -set +the target's NUMA policy may be queried. +If no target is specified, +.Nm +operates on itself. +Not all combinations of operations and targets are supported. +For example, +you may not set the id of an existing set or query and launch a command +at the same time. +.Pp +Each process and thread has a NUMA policy. +By default the policy is NONE. +If a thread policy is NONE, then the policy will fall back to the process. +If the process policy is NONE, then the policy will fall back to the +system default. +The policy may be queried by using +.Fl -get. +.Pp +The options are as follows: +.Bl -tag -width ".Fl -cpudomain Ar domain" +.It Fl -cpudomain Ar domain , Fl c Ar domain +Set the given CPU scheduling policy. +Constrain the the object (tid, pid, command) to run on CPUs +that belong to the given domain. +.It Fl -get , Fl g +Retrieve the NUMA policy for the given thread or process id. +.It Fl -set , Fl s +Set the NUMA policy for the given thread or process id. +.It Fl -memdomain Ar domain , Fl m Ar domain +Constrain the object (tid, pid, command) to the given +domain. +This is only valid for fixed-domain and fixed-domain-rr. +It must not be set for other policies. +.It Fl -mempolicy Ar policy , Fl l Ar policy +Set the given memory allocation policy. +Valid policies are none, rr, fixed-domain, fixed-domain-rr, +first-touch, and first-touch-rr. +A memdomain argument is required for fixed-domain and +fixed-domain-rr. +.It Fl -pid Ar pid , Fl p Ar pid +Operate on the given pid. +.It Fl -tid Ar tid , Fl t Ar tid +Operate on the given tid. +.El +.Sh EXIT STATUS +.Ex -std +.Sh EXAMPLES +Create a +.Pa /bin/sh +process with memory coming from domain 0, but +CPUs coming from domain 1: +.Dl numactl --mempolicy=fixed-domain --memdomain=0 --cpudomain=1 /bin/sh +.Pp +Query the NUMA policy for the +.Aq sh pid : +.Dl numactl --get --pid= +.Pp +Set the NUMA policy for the given TID to round-robin: +.Dl numactl --set --mempolicy=rr --tid= +.Sh SEE ALSO +.Xr cpuset 2 , +.Xr numa 4 +.Sh HISTORY +The +.Nm +command first appeared in +.Fx 11.0 . +.Sh AUTHORS +.An Adrian Chadd Aq Mt adrian@FreeBSD.org diff --git a/usr.bin/numactl/numactl.c b/usr.bin/numactl/numactl.c new file mode 100644 index 000000000000..ce1dfaecabc7 --- /dev/null +++ b/usr.bin/numactl/numactl.c @@ -0,0 +1,284 @@ +/* + * Copyright (c) 2015 Adrian Chadd + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct option longopts[] = { + { "tid", required_argument, NULL, 't' }, + { "pid", required_argument, NULL, 'p' }, + { "memdomain", required_argument, NULL, 'm' }, + { "cpudomain", required_argument, NULL, 'c' }, + { "mempolicy", required_argument, NULL, 'l' }, + { "set", no_argument, NULL, 's' }, + { "get", no_argument, NULL, 'g' }, + { NULL, 0, NULL, 0 } +}; + +static const char * +policy_to_str(vm_domain_policy_type_t vt) +{ + + switch (vt) { + case VM_POLICY_NONE: + return ("none"); + case VM_POLICY_ROUND_ROBIN: + return ("rr"); + case VM_POLICY_FIXED_DOMAIN: + return ("fixed-domain"); + case VM_POLICY_FIXED_DOMAIN_ROUND_ROBIN: + return ("fixed-domain-rr"); + case VM_POLICY_FIRST_TOUCH: + return ("first-touch"); + case VM_POLICY_FIRST_TOUCH_ROUND_ROBIN: + return ("first-touch-rr"); + default: + return ("unknown"); + } +} + +static int +parse_policy(struct vm_domain_policy_entry *vd, const char *str) +{ + + if (strcmp(str, "rr") == 0) { + vd->policy = VM_POLICY_ROUND_ROBIN; + vd->domain = -1; + return (0); + } + + if (strcmp(str, "first-touch-rr") == 0) { + vd->policy = VM_POLICY_FIRST_TOUCH_ROUND_ROBIN; + vd->domain = -1; + return (0); + } + + if (strcmp(str, "first-touch") == 0) { + vd->policy = VM_POLICY_FIRST_TOUCH; + vd->domain = -1; + return (0); + } + + if (strcmp(str, "fixed-domain") == 0) { + vd->policy = VM_POLICY_FIXED_DOMAIN; + vd->domain = 0; + return (0); + } + + if (strcmp(str, "fixed-domain-rr") == 0) { + vd->policy = VM_POLICY_FIXED_DOMAIN_ROUND_ROBIN; + vd->domain = 0; + return (0); + } + + return (-1); +} + +static void +usage(void) +{ + + printf("usage: numactl --get [--tid/-t ] [--pid/-p ]\n"); + printf(" numactl --set [--tid=] [--pid/-p]\n"); + printf(" [--mempolicy/-l ] [--memdomain/" + "-m ]\n"); + printf(" [--cpudomain/-c ]\n"); + printf(" numactl [--mempolicy/-l ] [--memdomain/-m " + "]\n"); + printf(" [--cpudomain/-c ] ...\n"); + + exit(EX_USAGE); +} + +static int +set_numa_domain_cpuaffinity(int cpu_domain) +{ + cpuset_t set; + int error; + + error = cpuset_getaffinity(CPU_LEVEL_WHICH, CPU_WHICH_DOMAIN, + cpu_domain, sizeof(set), &set); + if (error != 0) + err(1, "cpuset_getaffinity"); + error = cpuset_setaffinity(CPU_LEVEL_WHICH, CPU_WHICH_PID, -1, + sizeof(set), &set); + if (error != 0) + err(1, "cpuset_setaffinity"); + + return (0); +} + +int +main(int argc, char *argv[]) +{ + struct vm_domain_policy_entry vd; + lwpid_t tid; + pid_t pid; + cpuwhich_t which; + id_t id; + int error; + int is_set, is_get; + int mem_policy_set; + int ch; + int cpu_domain; + + id = -1; + which = -1; + is_set = 0; + is_get = 0; + mem_policy_set = 0; + tid = -1; + pid = -1; + cpu_domain = -1; + + while ((ch = getopt_long(argc, argv, "c:gl:m:p:st:", longopts, + NULL)) != -1) { + switch (ch) { + case 'c': + cpu_domain = atoi(optarg); + break; + case 'g': + is_get = 1; + break; + case 'l': + if (parse_policy(&vd, optarg) != 0) { + fprintf(stderr, + "Could not parse policy: '%s'\n", optarg); + exit(1); + } + mem_policy_set = 1; + break; + case 'm': + if (mem_policy_set == 0) { + fprintf(stderr, + "Error: set policy first before domain\n"); + exit(1); + } + vd.domain = atoi(optarg); + break; + case 'p': + pid = atoi(optarg); + break; + case 's': + is_set = 1; + break; + case 't': + tid = atoi(optarg); + break; + default: + usage(); + } + } + argc -= optind; + argv += optind; + + /* Handle the user wishing to run a command */ + if (argc) { + /* Ensure that a policy was set */ + if (mem_policy_set == 0) { + fprintf(stderr, "Error: no policy given\n"); + usage(); + } + + /* Set current memory process policy, will be inherited */ + if (numa_setaffinity(CPU_WHICH_PID, -1, &vd) != 0) + err(1, "numa_setaffinity"); + + /* If a CPU domain policy was given, include that too */ + if (cpu_domain != -1) + (void) set_numa_domain_cpuaffinity(cpu_domain); + + errno = 0; + execvp(*argv, argv); + err(errno == ENOENT ? 127 : 126, "%s", *argv); + } + + /* Figure out which */ + if (tid != -1) { + which = CPU_WHICH_TID; + id = tid; + } else if (pid != -1) { + which = CPU_WHICH_PID; + id = pid; + } else { + fprintf(stderr, "Error: one of tid or pid must be given\n"); + usage(); + } + + /* Sanity checks */ + if (is_set && is_get) { + fprintf(stderr, "Error: can't set both 'set' and 'get'\n"); + usage(); + } + + if (is_set && ! mem_policy_set) { + fprintf(stderr, "Error: --set given, but no policy\n"); + usage(); + } + + /* If it's get, then get the policy and return */ + if (is_get) { + error = numa_getaffinity(which, id, &vd); + if (error != 0) + err(1, "numa_getaffinity"); + printf(" Policy: %s; domain: %d\n", + policy_to_str(vd.policy), + vd.domain); + exit(0); + } + + /* Assume it's set */ + + /* Syscall */ + error = numa_setaffinity(which, id, &vd); + if (error != 0) + err(1, "numa_setaffinity"); + + /* If a CPU domain policy was given, include that too */ + if (cpu_domain != -1) + (void) set_numa_domain_cpuaffinity(cpu_domain); + + exit(0); +} diff --git a/usr.bin/patch/backupfile.c b/usr.bin/patch/backupfile.c index d22d607ccc4f..ecdca19e2a71 100644 --- a/usr.bin/patch/backupfile.c +++ b/usr.bin/patch/backupfile.c @@ -219,11 +219,11 @@ invalid_arg(const char *kind, const char *value, int problem) } static const char *backup_args[] = { - "never", "simple", "nil", "existing", "t", "numbered", 0 + "none", "never", "simple", "nil", "existing", "t", "numbered", 0 }; static enum backup_type backup_types[] = { - simple, simple, numbered_existing, + none, simple, simple, numbered_existing, numbered_existing, numbered, numbered }; diff --git a/usr.bin/patch/patch.1 b/usr.bin/patch/patch.1 index aac69dee9ce0..25adf5f9237a 100644 --- a/usr.bin/patch/patch.1 +++ b/usr.bin/patch/patch.1 @@ -21,7 +21,7 @@ .\" .\" $OpenBSD: patch.1,v 1.27 2014/04/15 06:26:54 jmc Exp $ .\" $FreeBSD$ -.Dd June 15, 2014 +.Dd July 21, 2015 .Dt PATCH 1 .Os .Sh NAME @@ -39,7 +39,7 @@ .Op Fl o Ar out-file .Op Fl p Ar strip-count .Op Fl r Ar rej-name -.Op Fl V Cm t | nil | never +.Op Fl V Cm t | nil | never | none .Op Fl x Ar number .Op Fl z Ar backup-ext .Op Fl Fl posix @@ -296,8 +296,8 @@ Forces .Nm to interpret the patch file as a unified context diff (a unidiff). .It Xo -.Fl V Cm t | nil | never , -.Fl Fl version-control Cm t | nil | never +.Fl V Cm t | nil | never | none , +.Fl Fl version-control Cm t | nil | never | none .Xc Causes the next argument to be interpreted as a method for creating backup file names. @@ -328,6 +328,8 @@ Make numbered backups of files that already have them, simple backups of the others. .It Cm never , simple Always make simple backups. +.It Cm none +Do not make backups. .El .It Fl v , Fl Fl version Causes diff --git a/usr.bin/patch/patch.c b/usr.bin/patch/patch.c index 22f302741aea..b061041dd053 100644 --- a/usr.bin/patch/patch.c +++ b/usr.bin/patch/patch.c @@ -109,6 +109,8 @@ static bool remove_empty_files = false; /* true if -R was specified on command line. */ static bool reverse_flag_specified = false; +static bool Vflag = false; + /* buffer holding the name of the rejected patch file. */ static char rejname[NAME_MAX + 1]; @@ -201,7 +203,7 @@ main(int argc, char *argv[]) Argv = argv; get_some_switches(); - if (backup_type == none) { + if (!Vflag) { if ((v = getenv("PATCH_VERSION_CONTROL")) == NULL) v = getenv("VERSION_CONTROL"); if (v != NULL || !posix) @@ -595,6 +597,7 @@ get_some_switches(void) break; case 'V': backup_type = get_version(optarg); + Vflag = true; break; #ifdef DEBUGGING case 'x': @@ -631,8 +634,8 @@ usage(void) fprintf(stderr, "usage: patch [-bCcEeflNnRstuv] [-B backup-prefix] [-D symbol] [-d directory]\n" " [-F max-fuzz] [-i patchfile] [-o out-file] [-p strip-count]\n" -" [-r rej-name] [-V t | nil | never] [-x number] [-z backup-ext]\n" -" [--posix] [origfile [patchfile]]\n" +" [-r rej-name] [-V t | nil | never | none] [-x number]\n" +" [-z backup-ext] [--posix] [origfile [patchfile]]\n" " patch #include #include +#define TCPSTATES /* load state names */ +#include #include #include #include @@ -71,6 +73,7 @@ static int opt_c; /* Show connected sockets */ static int opt_j; /* Show specified jail */ static int opt_L; /* Don't show IPv4 or IPv6 loopback sockets */ static int opt_l; /* Show listening sockets */ +static int opt_s; /* Show protocol state if applicable */ static int opt_u; /* Show Unix domain sockets */ static int opt_v; /* Verbose mode */ @@ -101,6 +104,7 @@ struct sock { int vflag; int family; int proto; + int state; const char *protoname; struct addr *laddr; struct addr *faddr; @@ -538,9 +542,9 @@ gather_inet(int proto) const char *varname, *protoname; size_t len, bufsize; void *buf; - int hash, retry, vflag; + int hash, retry, state, vflag; - vflag = 0; + state = vflag = 0; if (opt_4) vflag |= INP_IPV4; if (opt_6) @@ -594,9 +598,10 @@ gather_inet(int proto) xig = (struct xinpgen *)(void *)((char *)xig + xig->xig_len); if (xig >= exig) break; + xip = (struct xinpcb *)xig; + xtp = (struct xtcpcb *)xig; switch (proto) { case IPPROTO_TCP: - xtp = (struct xtcpcb *)xig; if (xtp->xt_len != sizeof(*xtp)) { warnx("struct xtcpcb size mismatch"); goto out; @@ -604,10 +609,10 @@ gather_inet(int proto) inp = &xtp->xt_inp; so = &xtp->xt_socket; protoname = xtp->xt_tp.t_flags & TF_TOE ? "toe" : "tcp"; + state = xtp->xt_tp.t_state; break; case IPPROTO_UDP: case IPPROTO_DIVERT: - xip = (struct xinpcb *)xig; if (xip->xi_len != sizeof(*xip)) { warnx("struct xinpcb size mismatch"); goto out; @@ -670,6 +675,8 @@ gather_inet(int proto) sock->laddr = laddr; sock->faddr = faddr; sock->vflag = inp->inp_vflag; + if (proto == IPPROTO_TCP) + sock->state = xtp->xt_tp.t_state; sock->protoname = protoname; hash = (int)((uintptr_t)sock->socket % HASHSIZE); sock->next = sockhash[hash]; @@ -977,7 +984,14 @@ displaysock(struct sock *s, int pos) pos = 0; } } - xprintf("\n"); + if (opt_s && s->proto == IPPROTO_TCP) { + while (pos < 80) + pos += xprintf(" "); + if (s->state >= 0 && s->state < TCP_NSTATES) + pos += xprintf("%s", tcpstates[s->state]); + else + pos += xprintf("?"); + } } static void @@ -988,9 +1002,12 @@ display(void) struct sock *s; int hash, n, pos; - printf("%-8s %-10s %-5s %-2s %-6s %-21s %-21s\n", + printf("%-8s %-10s %-5s %-2s %-6s %-21s %-21s", "USER", "COMMAND", "PID", "FD", "PROTO", "LOCAL ADDRESS", "FOREIGN ADDRESS"); + if (opt_s) + printf(" %-12s", "STATE"); + printf("\n"); setpassent(1); for (xf = xfiles, n = 0; n < nxfiles; ++n, ++xf) { if (xf->xf_data == NULL) @@ -1019,6 +1036,7 @@ display(void) pos += xprintf(" "); pos += xprintf("%d ", xf->xf_fd); displaysock(s, pos); + xprintf("\n"); } } if (opt_j >= 0) @@ -1033,6 +1051,7 @@ display(void) pos += xprintf("%-8s %-10s %-5s %-2s ", "?", "?", "?", "?"); displaysock(s, pos); + xprintf("\n"); } } } @@ -1061,7 +1080,7 @@ static void usage(void) { fprintf(stderr, - "Usage: sockstat [-46cLlu] [-j jid] [-p ports] [-P protocols]\n"); + "usage: sockstat [-46cLlsu] [-j jid] [-p ports] [-P protocols]\n"); exit(1); } @@ -1072,7 +1091,7 @@ main(int argc, char *argv[]) int o, i; opt_j = -1; - while ((o = getopt(argc, argv, "46cj:Llp:P:uv")) != -1) + while ((o = getopt(argc, argv, "46cj:Llp:P:suv")) != -1) switch (o) { case '4': opt_4 = 1; @@ -1098,6 +1117,9 @@ main(int argc, char *argv[]) case 'P': protos_defined = parse_protos(optarg); break; + case 's': + opt_s = 1; + break; case 'u': opt_u = 1; break; diff --git a/usr.bin/w/w.c b/usr.bin/w/w.c index f94d8a600cf9..4df4abd96816 100644 --- a/usr.bin/w/w.c +++ b/usr.bin/w/w.c @@ -120,7 +120,7 @@ static struct entry { #define W_DISPUSERSIZE 10 #define W_DISPLINESIZE 8 -#define W_DISPHOSTSIZE 24 +#define W_DISPHOSTSIZE 40 static void pr_header(time_t *, int); static struct stat *ttystat(char *); diff --git a/usr.bin/xargs/xargs.c b/usr.bin/xargs/xargs.c index 6bd3e9fd46fb..b95c7d47bb60 100644 --- a/usr.bin/xargs/xargs.c +++ b/usr.bin/xargs/xargs.c @@ -101,6 +101,7 @@ main(int argc, char *argv[]) int ch, Jflag, nargs, nflag, nline; size_t linelen; char *endptr; + const char *errstr; inpline = replstr = NULL; ep = environ; @@ -148,19 +149,23 @@ main(int argc, char *argv[]) replstr = optarg; break; case 'L': - Lflag = atoi(optarg); + Lflag = strtonum(optarg, 0, INT_MAX, &errstr); + if (errstr) + errx(1, "-L %s: %s", optarg, errstr); break; case 'n': nflag = 1; - if ((nargs = atoi(optarg)) <= 0) - errx(1, "illegal argument count"); + nargs = strtonum(optarg, 1, INT_MAX, &errstr); + if (errstr) + errx(1, "-n %s: %s", optarg, errstr); break; case 'o': oflag = 1; break; case 'P': - if ((maxprocs = atoi(optarg)) <= 0) - errx(1, "max. processes must be >0"); + maxprocs = strtonum(optarg, 1, INT_MAX, &errstr); + if (errstr) + errx(1, "-P %s: %s", optarg, errstr); break; case 'p': pflag = 1; @@ -179,7 +184,9 @@ main(int argc, char *argv[]) errx(1, "replsize must be a number"); break; case 's': - nline = atoi(optarg); + nline = strtonum(optarg, 0, INT_MAX, &errstr); + if (errstr) + errx(1, "-s %s: %s", optarg, errstr); break; case 't': tflag = 1; diff --git a/usr.sbin/bsdinstall/partedit/gpart_ops.c b/usr.sbin/bsdinstall/partedit/gpart_ops.c index 37b172e8cb39..48bbb68ca28e 100644 --- a/usr.sbin/bsdinstall/partedit/gpart_ops.c +++ b/usr.sbin/bsdinstall/partedit/gpart_ops.c @@ -206,12 +206,11 @@ newfs_command(const char *fstype, char *command, int use_default) } } -int -gpart_partition(const char *lg_name, const char *scheme) +const char * +choose_part_type(const char *def_scheme) { int cancel, choice; - struct gctl_req *r; - const char *errstr; + const char *scheme = NULL; DIALOG_LISTITEM items[] = { {"APM", "Apple Partition Map", @@ -228,30 +227,61 @@ gpart_partition(const char *lg_name, const char *scheme) "Bootable on Sun SPARC systems", 0 }, }; +parttypemenu: + dialog_vars.default_item = __DECONST(char *, def_scheme); + cancel = dlg_menu("Partition Scheme", + "Select a partition scheme for this volume:", 0, 0, 0, + sizeof(items) / sizeof(items[0]), items, &choice, NULL); + dialog_vars.default_item = NULL; + + if (cancel) + return NULL; + + if (!is_scheme_bootable(items[choice].name)) { + char message[512]; + sprintf(message, "This partition scheme (%s) is not " + "bootable on this platform. Are you sure you want " + "to proceed?", items[choice].name); + dialog_vars.defaultno = TRUE; + cancel = dialog_yesno("Warning", message, 0, 0); + dialog_vars.defaultno = FALSE; + if (cancel) /* cancel */ + goto parttypemenu; + } + + scheme = items[choice].name; + + return scheme; +} + +int +gpart_partition(const char *lg_name, const char *scheme) +{ + int cancel; + struct gctl_req *r; + const char *errstr; + schememenu: if (scheme == NULL) { - dialog_vars.default_item = __DECONST(char *, default_scheme()); - cancel = dlg_menu("Partition Scheme", - "Select a partition scheme for this volume:", 0, 0, 0, - sizeof(items) / sizeof(items[0]), items, &choice, NULL); - dialog_vars.default_item = NULL; + scheme = choose_part_type(default_scheme()); - if (cancel) + if (scheme == NULL) return (-1); - if (!is_scheme_bootable(items[choice].name)) { + if (!is_scheme_bootable(scheme)) { char message[512]; sprintf(message, "This partition scheme (%s) is not " "bootable on this platform. Are you sure you want " - "to proceed?", items[choice].name); + "to proceed?", scheme); dialog_vars.defaultno = TRUE; cancel = dialog_yesno("Warning", message, 0, 0); dialog_vars.defaultno = FALSE; - if (cancel) /* cancel */ + if (cancel) { /* cancel */ + /* Reset scheme so user can choose another */ + scheme = NULL; goto schememenu; + } } - - scheme = items[choice].name; } r = gctl_get_handle(); @@ -322,6 +352,26 @@ gpart_activate(struct gprovider *pp) gctl_free(r); } +void +gpart_set_root(const char *lg_name, const char *attribute) +{ + struct gctl_req *r; + const char *errstr; + + r = gctl_get_handle(); + gctl_ro_param(r, "class", -1, "PART"); + gctl_ro_param(r, "arg0", -1, lg_name); + gctl_ro_param(r, "flags", -1, "C"); + gctl_ro_param(r, "verb", -1, "set"); + gctl_ro_param(r, "attrib", -1, attribute); + + errstr = gctl_issue(r); + if (errstr != NULL && errstr[0] != '\0') + gpart_show_error("Error", "Error setting parameter on disk:", + errstr); + gctl_free(r); +} + static void gpart_bootcode(struct ggeom *gp) { diff --git a/usr.sbin/bsdinstall/partedit/part_wizard.c b/usr.sbin/bsdinstall/partedit/part_wizard.c index 3f7ccd59a1a2..1e9c89919238 100644 --- a/usr.sbin/bsdinstall/partedit/part_wizard.c +++ b/usr.sbin/bsdinstall/partedit/part_wizard.c @@ -257,8 +257,10 @@ query: goto query; gpart_destroy(gpart); - gpart_partition(disk, default_scheme()); - scheme = default_scheme(); + scheme = choose_part_type(default_scheme()); + if (scheme == NULL) + return NULL; + gpart_partition(disk, scheme); } if (scheme == NULL || choice == 0) { @@ -272,8 +274,10 @@ query: gpart_destroy(gpart); } - gpart_partition(disk, default_scheme()); - scheme = default_scheme(); + scheme = choose_part_type(default_scheme()); + if (scheme == NULL) + return NULL; + gpart_partition(disk, scheme); } if (strcmp(scheme, "PC98") == 0 || strcmp(scheme, "MBR") == 0) { diff --git a/usr.sbin/bsdinstall/partedit/partedit.c b/usr.sbin/bsdinstall/partedit/partedit.c index ac3cd8a9c9c0..f02204437b8b 100644 --- a/usr.sbin/bsdinstall/partedit/partedit.c +++ b/usr.sbin/bsdinstall/partedit/partedit.c @@ -44,6 +44,7 @@ struct pmetadata_head part_metadata; static int sade_mode = 0; static int apply_changes(struct gmesh *mesh); +static void apply_workaround(struct gmesh *mesh); static struct partedit_item *read_geom_mesh(struct gmesh *mesh, int *nitems); static void add_geom_children(struct ggeom *gp, int recurse, struct partedit_item **items, int *nitems); @@ -189,6 +190,8 @@ main(int argc, const char **argv) if (op == 0 && validate_setup()) { /* Save */ error = apply_changes(&mesh); + if (!error) + apply_workaround(&mesh); break; } else if (op == 3) { /* Quit */ gpart_revert_all(&mesh); @@ -390,6 +393,43 @@ apply_changes(struct gmesh *mesh) return (0); } +static void +apply_workaround(struct gmesh *mesh) +{ + struct gclass *classp; + struct ggeom *gp; + struct gconfig *gc; + const char *scheme = NULL, *modified = NULL; + + LIST_FOREACH(classp, &mesh->lg_class, lg_class) { + if (strcmp(classp->lg_name, "PART") == 0) + break; + } + + if (strcmp(classp->lg_name, "PART") != 0) { + dialog_msgbox("Error", "gpart not found!", 0, 0, TRUE); + return; + } + + LIST_FOREACH(gp, &classp->lg_geom, lg_geom) { + LIST_FOREACH(gc, &gp->lg_config, lg_config) { + if (strcmp(gc->lg_name, "scheme") == 0) { + scheme = gc->lg_val; + } else if (strcmp(gc->lg_name, "modified") == 0) { + modified = gc->lg_val; + } + } + + if (scheme && strcmp(scheme, "GPT") == 0 && + modified && strcmp(modified, "true") == 0) { + if (getenv("WORKAROUND_LENOVO")) + gpart_set_root(gp->lg_name, "lenovofix"); + if (getenv("WORKAROUND_GPTACTIVE")) + gpart_set_root(gp->lg_name, "active"); + } + } +} + static struct partedit_item * read_geom_mesh(struct gmesh *mesh, int *nitems) { diff --git a/usr.sbin/bsdinstall/partedit/partedit.h b/usr.sbin/bsdinstall/partedit/partedit.h index b6f725893cbd..3eb9173dcf42 100644 --- a/usr.sbin/bsdinstall/partedit/partedit.h +++ b/usr.sbin/bsdinstall/partedit/partedit.h @@ -72,6 +72,8 @@ void gpart_commit(struct gmesh *mesh); int gpart_partition(const char *lg_name, const char *scheme); void set_default_part_metadata(const char *name, const char *scheme, const char *type, const char *mountpoint, const char *newfs); +void gpart_set_root(const char *lg_name, const char *attribute); +const char *choose_part_type(const char *def_scheme); /* machine-dependent bootability checks */ const char *default_scheme(void); diff --git a/usr.sbin/bsdinstall/scripts/auto b/usr.sbin/bsdinstall/scripts/auto index 433744e9bb62..891419ae37e9 100755 --- a/usr.sbin/bsdinstall/scripts/auto +++ b/usr.sbin/bsdinstall/scripts/auto @@ -31,6 +31,7 @@ BSDCFG_SHARE="/usr/share/bsdconfig" . $BSDCFG_SHARE/common.subr || exit 1 +f_include $BSDCFG_SHARE/dialog.subr ############################################################ FUNCTIONS @@ -51,6 +52,54 @@ error() { fi } +hline_arrows_tab_enter="Press arrows, TAB or ENTER" +msg_gpt_active_fix="Your hardware is known to have issues booting in CSM/Legacy/BIOS mode from GPT partitions that are not set active. Would you like the installer to apply this workaround for you?" +msg_lenovo_fix="Your model of Lenovo is known to have a BIOS bug that prevents it booting from GPT partitions without UEFI. Would you like the installer to apply a workaround for you?" +msg_no="NO" +msg_yes="YES" + +# dialog_workaround +# +# Ask the user if they wish to apply a workaround +# +dialog_workaround() +{ + local passed_msg="$1" + local title="$DIALOG_TITLE" + local btitle="$DIALOG_BACKTITLE" + local prompt # Calculated below + local hline="$hline_arrows_tab_enter" + + local height=8 width=50 prefix=" " + local plen=${#prefix} list= line= + local max_width=$(( $width - 3 - $plen )) + + local yes no defaultno extra_args format + if [ "$USE_XDIALOG" ]; then + yes=ok no=cancel defaultno=default-no + extra_args="--wrap --left" + format="$passed_msg" + else + yes=yes no=no defaultno=defaultno + extra_args="--cr-wrap" + format="$passed_msg" + fi + + # Add height for Xdialog(1) + [ "$USE_XDIALOG" ] && height=$(( $height + $height / 5 + 3 )) + + prompt=$( printf "$format" ) + f_dprintf "%s: Workaround prompt" "$0" + $DIALOG \ + --title "$title" \ + --backtitle "$btitle" \ + --hline "$hline" \ + --$yes-label "$msg_yes" \ + --$no-label "$msg_no" \ + $extra_args \ + --yesno "$prompt" $height $width +} + ############################################################ MAIN f_dprintf "Began Installation at %s" "$( date )" @@ -106,6 +155,73 @@ fi rm -f $PATH_FSTAB touch $PATH_FSTAB +# +# Try to detect known broken platforms and apply their workarounds +# + +if f_interactive; then + sys_maker=$( kenv -q smbios.system.maker ) + f_dprintf "smbios.system.maker=[%s]" "$sys_maker" + sys_model=$( kenv -q smbios.system.product ) + f_dprintf "smbios.system.product=[%s]" "$sys_model" + sys_version=$( kenv -q smbios.system.version ) + f_dprintf "smbios.system.version=[%s]" "$sys_version" + sys_mb_maker=$( kenv -q smbios.planar.maker ) + f_dprintf "smbios.planar.maker=[%s]" "$sys_mb_maker" + sys_mb_product=$( kenv -q smbios.planar.product ) + f_dprintf "smbios.planar.product=[%s]" "$sys_mb_product" + + # + # Laptop Models + # + case "$sys_maker" in + "LENOVO") + case "$sys_version" in + "ThinkPad X220"|"ThinkPad T420"|"ThinkPad T520") + dialog_workaround "$msg_lenovo_fix" + retval=$? + f_dprintf "lenovofix_prompt=[%s]" "$retval" + if [ $retval -eq $DIALOG_OK ]; then + export ZFSBOOT_PARTITION_SCHEME="GPT + Lenovo Fix" + export WORKAROUND_LENOVO=1 + fi + ;; + esac + ;; + "Dell Inc.") + case "$sys_model" in + "Latitude E7440"|"Latitude E7240") + dialog_workaround "$msg_gpt_active_fix" + retval=$? + f_dprintf "gpt_active_fix_prompt=[%s]" "$retval" + if [ $retval -eq $DIALOG_OK ]; then + export ZFSBOOT_PARTITION_SCHEME="GPT + Active" + export WORKAROUND_GPTACTIVE=1 + fi + ;; + esac + ;; + esac + # + # Motherboard Models + # + case "$sys_mb_maker" in + "Intel Corporation") + case "$sys_mb_product" in + "DP965LT") + dialog_workaround "$msg_gpt_active_fix" + retval=$? + f_dprintf "gpt_active_fix_prompt=[%s]" "$retval" + if [ $retval -eq $DIALOG_OK ]; then + export ZFSBOOT_PARTITION_SCHEME="GPT + Active" + export WORKAROUND_GPTACTIVE=1 + fi + ;; + esac + ;; + esac +fi + PMODES="\ \"Auto (UFS)\" \"Guided Disk Setup\" \ Manual \"Manual Disk Setup (experts)\" \ diff --git a/usr.sbin/bsdinstall/scripts/zfsboot b/usr.sbin/bsdinstall/scripts/zfsboot index c759e85f2598..e6124da42986 100755 --- a/usr.sbin/bsdinstall/scripts/zfsboot +++ b/usr.sbin/bsdinstall/scripts/zfsboot @@ -1,6 +1,6 @@ #!/bin/sh #- -# Copyright (c) 2013-2014 Allan Jude +# Copyright (c) 2013-2015 Allan Jude # Copyright (c) 2013-2015 Devin Teske # All rights reserved. # @@ -157,6 +157,7 @@ f_isset ZFSBOOT_DATASETS || ZFSBOOT_DATASETS=" # Create /var and friends /var mountpoint=/var,canmount=off + /var/audit exec=off,setuid=off /var/crash exec=off,setuid=off /var/log exec=off,setuid=off /var/mail atime=on @@ -185,16 +186,18 @@ ECHO_APPEND='echo "%s" >> "%s"' GELI_ATTACH='geli attach -j - -k "%s" "%s"' GELI_DETACH_F='geli detach -f "%s"' GELI_PASSWORD_INIT='geli init -b -B "%s" -e %s -J - -K "%s" -l 256 -s 4096 "%s"' -GPART_ADD='gpart add -t %s "%s"' -GPART_ADD_INDEX='gpart add -i %s -t %s "%s"' -GPART_ADD_INDEX_WITH_SIZE='gpart add -i %s -t %s -s %s "%s"' -GPART_ADD_LABEL='gpart add -l %s -t %s "%s"' -GPART_ADD_LABEL_WITH_SIZE='gpart add -l %s -t %s -s %s "%s"' +GPART_ADD_ALIGN='gpart add %s -t %s "%s"' +GPART_ADD_ALIGN_INDEX='gpart add %s -i %s -t %s "%s"' +GPART_ADD_ALIGN_INDEX_WITH_SIZE='gpart add %s -i %s -t %s -s %s "%s"' +GPART_ADD_ALIGN_LABEL='gpart add %s -l %s -t %s "%s"' +GPART_ADD_ALIGN_LABEL_WITH_SIZE='gpart add %s -l %s -t %s -s %s "%s"' GPART_BOOTCODE='gpart bootcode -b "%s" "%s"' GPART_BOOTCODE_PART='gpart bootcode -b "%s" -p "%s" -i %s "%s"' GPART_CREATE='gpart create -s %s "%s"' GPART_DESTROY_F='gpart destroy -F "%s"' GPART_SET_ACTIVE='gpart set -a active -i %s "%s"' +GPART_SET_LENOVOFIX='gpart set -a lenovofix "%s"' +GPART_SET_PMBR_ACTIVE='gpart set -a active "%s"' GRAID_DELETE='graid delete "%s"' LN_SF='ln -sf "%s" "%s"' MKDIR_P='mkdir -p "%s"' @@ -235,7 +238,7 @@ msg_encrypt_disks="Encrypt Disks?" msg_encrypt_disks_help="Use geli(8) to encrypt all data partitions" msg_error="Error" msg_force_4k_sectors="Force 4K Sectors?" -msg_force_4k_sectors_help="Use sysctl(8) vfs.zfs.min_auto_ashift=12 to force 4K sectors" +msg_force_4k_sectors_help="Align partitions to 4K sector boundries and set vfs.zfs.min_auto_ashift=12" msg_freebsd_installer="FreeBSD Installer" msg_geli_password="Enter a strong passphrase, used to protect your encryption keys. You will be required to enter this passphrase each time the system is booted" msg_geli_setup="Initializing encryption on selected disks,\n this will take several seconds per disk" @@ -262,7 +265,7 @@ msg_null_index_argument="NULL index argument" msg_null_poolname="NULL poolname" msg_ok="OK" msg_partition_scheme="Partition Scheme" -msg_partition_scheme_help="Toggle between GPT and MBR partitioning schemes" +msg_partition_scheme_help="Select partitioning scheme. GPT is recommended." msg_please_enter_a_name_for_your_zpool="Please enter a name for your zpool:" msg_please_enter_amount_of_swap_space="Please enter amount of swap space (SI-Unit suffixes\nrecommended; e.g., \`2g' for 2 Gigabytes):" msg_please_select_one_or_more_disks="Please select one or more disks to create a zpool:" @@ -778,7 +781,7 @@ zfs_create_diskpart() # Check for unknown partition scheme before proceeding further case "$ZFSBOOT_PARTITION_SCHEME" in - ""|MBR|GPT) : known good ;; + ""|MBR|GPT*) : known good ;; *) f_dprintf "$funcname: %s is an unsupported partition scheme" \ "$ZFSBOOT_PARTITION_SCHEME" @@ -810,20 +813,44 @@ zfs_create_diskpart() # # Lay down the desired type of partition scheme # - local setsize mbrindex + local setsize mbrindex align_small align_big + # + # If user has requested 4 K alignment, add these params to the + # gpart add calls. With GPT, we align large partitions to 1 M for + # improved performance on SSDs. MBR does not always play well with gaps + # between partitions, so all alignment is only 4k for that case. + # With MBR, we align the BSD partition that contains the MBR, otherwise + # the system fails to boot. + # + if [ "$ZFSBOOT_FORCE_4K_SECTORS" ]; then + align_small="-a 4k" + align_big="-a 1m" + fi + case "$ZFSBOOT_PARTITION_SCHEME" in - ""|GPT) f_dprintf "$funcname: Creating GPT layout..." + ""|GPT*) f_dprintf "$funcname: Creating GPT layout..." # # 1. Create GPT layout using labels # f_eval_catch $funcname gpart "$GPART_CREATE" gpt $disk || return $FAILURE + # + # Apply workarounds if requested by the user + # + if [ "$ZFSBOOT_PARTITION_SCHEME" = "GPT + Lenovo Fix" ]; then + f_eval_catch $funcname gpart "$GPART_SET_LENOVOFIX" \ + $disk || return $FAILURE + elif [ "$ZFSBOOT_PARTITION_SCHEME" = "GPT + Active" ]; then + f_eval_catch $funcname gpart "$GPART_SET_PMBR_ACTIVE" \ + $disk || return $FAILURE + fi + # # 2. Add small freebsd-boot partition labeled `boot#' # - f_eval_catch $funcname gpart "$GPART_ADD_LABEL_WITH_SIZE" \ - gptboot$index freebsd-boot 512k $disk || + f_eval_catch $funcname gpart "$GPART_ADD_ALIGN_LABEL_WITH_SIZE" \ + "$align_small" gptboot$index freebsd-boot 512k $disk || return $FAILURE f_eval_catch $funcname gpart "$GPART_BOOTCODE_PART" \ /boot/pmbr /boot/gptzfsboot 1 $disk || @@ -840,8 +867,9 @@ zfs_create_diskpart() bootpart=p2 swappart=p3 targetpart=p3 [ ${swapsize:-0} -gt 0 ] && targetpart=p4 f_eval_catch $funcname gpart \ - "$GPART_ADD_LABEL_WITH_SIZE" boot$index \ - freebsd-zfs ${bootsize}b $disk || + "$GPART_ADD_ALIGN_LABEL_WITH_SIZE" \ + "$align_big" boot$index freebsd-zfs \ + ${bootsize}b $disk || return $FAILURE # Pedantically nuke any old labels f_eval_catch -d $funcname zpool "$ZPOOL_LABELCLEAR_F" \ @@ -859,8 +887,9 @@ zfs_create_diskpart() # if [ ${swapsize:-0} -gt 0 ]; then f_eval_catch $funcname gpart \ - "$GPART_ADD_LABEL_WITH_SIZE" swap$index \ - freebsd-swap ${swapsize}b $disk || + "$GPART_ADD_ALIGN_LABEL_WITH_SIZE" \ + "$align_big" swap$index freebsd-swap \ + ${swapsize}b $disk || return $FAILURE # Pedantically nuke any old labels on the swap f_eval_catch -d $funcname zpool "$ZPOOL_LABELCLEAR_F" \ @@ -870,8 +899,9 @@ zfs_create_diskpart() # # 4. Add freebsd-zfs partition labeled `zfs#' for zroot # - f_eval_catch $funcname gpart "$GPART_ADD_LABEL" \ - zfs$index freebsd-zfs $disk || return $FAILURE + f_eval_catch $funcname gpart "$GPART_ADD_ALIGN_LABEL" \ + "$align_big" zfs$index freebsd-zfs $disk || + return $FAILURE f_eval_catch -d $funcname zpool "$ZPOOL_LABELCLEAR_F" \ /dev/$disk$targetpart ;; @@ -888,7 +918,8 @@ zfs_create_diskpart() # # 2. Add freebsd slice with all available space # - f_eval_catch $funcname gpart "$GPART_ADD" freebsd $disk || + f_eval_catch $funcname gpart "$GPART_ADD_ALIGN" "$align_small" \ + freebsd $disk || return $FAILURE f_eval_catch $funcname gpart "$GPART_SET_ACTIVE" 1 $disk || return $FAILURE @@ -912,8 +943,8 @@ zfs_create_diskpart() # ZFSBOOT_BOOT_POOL=1 f_eval_catch $funcname gpart \ - "$GPART_ADD_INDEX_WITH_SIZE" \ - 1 freebsd-zfs ${bootsize}b ${disk}s1 || + "$GPART_ADD_ALIGN_INDEX_WITH_SIZE" \ + "$align_small" 1 freebsd-zfs ${bootsize}b ${disk}s1 || return $FAILURE # Pedantically nuke any old labels f_eval_catch -d $funcname zpool "$ZPOOL_LABELCLEAR_F" \ @@ -930,8 +961,8 @@ zfs_create_diskpart() # if [ ${swapsize:-0} -gt 0 ]; then f_eval_catch $funcname gpart \ - "$GPART_ADD_INDEX_WITH_SIZE" 2 \ - freebsd-swap ${swapsize}b ${disk}s1 || + "$GPART_ADD_ALIGN_INDEX_WITH_SIZE" \ + "$align_small" 2 freebsd-swap ${swapsize}b ${disk}s1 || return $FAILURE # Pedantically nuke any old labels on the swap f_eval_catch -d $funcname zpool "$ZPOOL_LABELCLEAR_F" \ @@ -941,8 +972,8 @@ zfs_create_diskpart() # # 5. Add freebsd-zfs partition for zroot # - f_eval_catch $funcname gpart "$GPART_ADD_INDEX" \ - $mbrindex freebsd-zfs ${disk}s1 || return $FAILURE + f_eval_catch $funcname gpart "$GPART_ADD_ALIGN_INDEX" \ + "$align_small" $mbrindex freebsd-zfs ${disk}s1 || return $FAILURE f_eval_catch -d $funcname zpool "$ZPOOL_LABELCLEAR_F" \ /dev/$disk$targetpart # Pedantic f_eval_catch $funcname dd "$DD_WITH_OPTIONS" \ @@ -1236,12 +1267,21 @@ zfs_create_boot() return $FAILURE done + # + # Set a mountpoint for the root of the pool so newly created datasets + # have a mountpoint to inherit + # + f_dprintf "$funcname: Setting mountpoint for root of the pool..." + f_eval_catch $funcname zfs "$ZFS_SET" \ + "mountpoint=/$zroot_name" "$zroot_name" || + return $FAILURE + # Touch up permissions on the tmp directories f_dprintf "$funcname: Modifying directory permissions..." local dir for dir in /tmp /var/tmp; do f_eval_catch $funcname chmod "$CHMOD_MODE" 1777 \ - $BSDINSTALL_CHROOTDIR$dir || return $FAILURE + $BSDINSTALL_CHROOT$dir || return $FAILURE done # Create symlink(s) @@ -1557,6 +1597,10 @@ while :; do # Toggle between GPT and MBR if [ "$ZFSBOOT_PARTITION_SCHEME" = GPT ]; then ZFSBOOT_PARTITION_SCHEME=MBR + elif [ "$ZFSBOOT_PARTITION_SCHEME" = MBR ]; then + ZFSBOOT_PARTITION_SCHEME="GPT + Active" + elif [ "$ZFSBOOT_PARTITION_SCHEME" = "GPT + Active" ]; then + ZFSBOOT_PARTITION_SCHEME="GPT + Lenovo Fix" else ZFSBOOT_PARTITION_SCHEME=GPT fi diff --git a/usr.sbin/bsnmpd/modules/snmp_hostres/hostres_printer_tbl.c b/usr.sbin/bsnmpd/modules/snmp_hostres/hostres_printer_tbl.c index 883d67a53bcb..33a54b58fb1f 100644 --- a/usr.sbin/bsnmpd/modules/snmp_hostres/hostres_printer_tbl.c +++ b/usr.sbin/bsnmpd/modules/snmp_hostres/hostres_printer_tbl.c @@ -175,7 +175,7 @@ get_printer_status(const struct printer *pp) goto LABEL_DONE; } - memset(&fline[0], '\0', sizeof(line)); + memset(&fline[0], '\0', sizeof(fline)); if (fgets(fline, sizeof(fline) -1, f) == NULL) { ps = PS_UNKNOWN; goto LABEL_DONE; diff --git a/usr.sbin/ctladm/ctladm.c b/usr.sbin/ctladm/ctladm.c index aefba042aa54..6baf0902823d 100644 --- a/usr.sbin/ctladm/ctladm.c +++ b/usr.sbin/ctladm/ctladm.c @@ -3661,6 +3661,7 @@ retry: retval = 1; goto bailout; } + retval = 0; XML_ParserFree(parser); if (verbose != 0) { @@ -4080,6 +4081,7 @@ retry: retval = 1; goto bailout; } + retval = 0; XML_ParserFree(parser); printf("LUN Backend %18s %4s %-16s %-16s\n", "Size (Blocks)", "BS", @@ -4376,6 +4378,7 @@ retry: retval = 1; goto bailout; } + retval = 0; XML_ParserFree(parser); if (quiet == 0) diff --git a/usr.sbin/devctl/devctl.8 b/usr.sbin/devctl/devctl.8 index 77c803a7af29..fef42be13073 100644 --- a/usr.sbin/devctl/devctl.8 +++ b/usr.sbin/devctl/devctl.8 @@ -109,7 +109,7 @@ loader tunable. .It Cm suspend Ar device Suspend a device. This may include placing the device in a reduced power state. -.It Cm resume device +.It Cm resume Ar device Resume a suspended device to a fully working state. .It Xo Cm set driver .Op Fl f diff --git a/usr.sbin/fstyp/fstyp.8 b/usr.sbin/fstyp/fstyp.8 index 981a8d33f0e4..835feff0f70e 100644 --- a/usr.sbin/fstyp/fstyp.8 +++ b/usr.sbin/fstyp/fstyp.8 @@ -27,7 +27,7 @@ .\" .\" $FreeBSD$ .\" -.Dd June 15, 2015 +.Dd July 11, 2015 .Dt FSTYP 8 .Os .Sh NAME @@ -116,7 +116,7 @@ type is not recognized. The .Nm command appeared in -.Fx 11.0 . +.Fx 10.2 . .Sh AUTHORS The .Nm diff --git a/usr.sbin/fstyp/geli.c b/usr.sbin/fstyp/geli.c index 1c15ca6779dd..a6ce740e87e5 100644 --- a/usr.sbin/fstyp/geli.c +++ b/usr.sbin/fstyp/geli.c @@ -2,9 +2,6 @@ * Copyright (c) 2015 Allan Jude * All rights reserved. * - * This software was developed by Edward Tomasz Napierala under sponsorship - * from the FreeBSD Foundation. - * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: diff --git a/usr.sbin/fstyp/zfs.c b/usr.sbin/fstyp/zfs.c index 9d91db650157..af3965ec0476 100644 --- a/usr.sbin/fstyp/zfs.c +++ b/usr.sbin/fstyp/zfs.c @@ -2,9 +2,6 @@ * Copyright (c) 2015 Allan Jude * All rights reserved. * - * This software was developed by Edward Tomasz Napierala under sponsorship - * from the FreeBSD Foundation. - * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: diff --git a/usr.sbin/jail/jail.8 b/usr.sbin/jail/jail.8 index 189fa36a59d1..5122e0f22eea 100644 --- a/usr.sbin/jail/jail.8 +++ b/usr.sbin/jail/jail.8 @@ -25,7 +25,7 @@ .\" .\" $FreeBSD$ .\" -.Dd February 25, 2015 +.Dd July 20, 2015 .Dt JAIL 8 .Os .Sh NAME @@ -563,6 +563,22 @@ This permission is effective only together with and only when .Va enforce_statfs is set to a value lower than 2. +.It Va allow.mount.linprocfs +privileged users inside the jail will be able to mount and unmount the +linprocfs file system. +This permission is effective only together with +.Va allow.mount +and only when +.Va enforce_statfs +is set to a value lower than 2. +.It Va allow.mount.linsysfs +privileged users inside the jail will be able to mount and unmount the +linsysfs file system. +This permission is effective only together with +.Va allow.mount +and only when +.Va enforce_statfs +is set to a value lower than 2. .It Va allow.mount.tmpfs privileged users inside the jail will be able to mount and unmount the tmpfs file system. @@ -1209,6 +1225,8 @@ environment of the first jail. .Xr devfs 5 , .Xr fdescfs 5 , .Xr jail.conf 5 , +.Xr linprocfs 5 , +.Xr linsysfs 5 , .Xr procfs 5 , .Xr rc.conf 5 , .Xr sysctl.conf 5 , diff --git a/usr.sbin/jexec/jexec.8 b/usr.sbin/jexec/jexec.8 index a98af67b5017..19ed42d7be50 100644 --- a/usr.sbin/jexec/jexec.8 +++ b/usr.sbin/jexec/jexec.8 @@ -25,7 +25,7 @@ .\" .\" $FreeBSD$ .\" -.Dd May 27, 2009 +.Dd Jul 11, 2015 .Dt JEXEC 8 .Os .Sh NAME @@ -33,8 +33,9 @@ .Nd "execute a command inside an existing jail" .Sh SYNOPSIS .Nm +.Op Fl l .Op Fl u Ar username | Fl U Ar username -.Ar jail command ... +.Ar jail Op Ar command ... .Sh DESCRIPTION The .Nm @@ -43,9 +44,17 @@ utility executes inside the .Ar jail identified by its jid or name. +If +.Ar command +is not specified then the user's shell is used. .Pp The following options are available: .Bl -tag -width indent +.It Fl l +Execute in a clean environment. +The environment is discarded except for +.Ev HOME , SHELL , TERM , USER , +and anything from the login class capability database for the user. .It Fl u Ar username The user name from host environment as whom the .Ar command diff --git a/usr.sbin/jexec/jexec.c b/usr.sbin/jexec/jexec.c index 8c15ebe98591..f8974dc4e916 100644 --- a/usr.sbin/jexec/jexec.c +++ b/usr.sbin/jexec/jexec.c @@ -40,49 +40,37 @@ #include #include #include +#include +#include #include #include #include -#include #include -static void usage(void); +extern char **environ; -#define GET_USER_INFO do { \ - pwd = getpwnam(username); \ - if (pwd == NULL) { \ - if (errno) \ - err(1, "getpwnam: %s", username); \ - else \ - errx(1, "%s: no such user", username); \ - } \ - lcap = login_getpwclass(pwd); \ - if (lcap == NULL) \ - err(1, "getpwclass: %s", username); \ - ngroups = ngroups_max; \ - if (getgrouplist(username, pwd->pw_gid, groups, &ngroups) != 0) \ - err(1, "getgrouplist: %s", username); \ -} while (0) +static void get_user_info(const char *username, const struct passwd **pwdp, + login_cap_t **lcapp); +static void usage(void); int main(int argc, char *argv[]) { int jid; login_cap_t *lcap = NULL; - struct passwd *pwd = NULL; - gid_t *groups = NULL; - int ch, ngroups, uflag, Uflag; - long ngroups_max; - char *username; + int ch, clean, uflag, Uflag; + char *cleanenv; + const struct passwd *pwd = NULL; + const char *username, *shell, *term; - ch = uflag = Uflag = 0; + ch = clean = uflag = Uflag = 0; username = NULL; - ngroups_max = sysconf(_SC_NGROUPS_MAX) + 1; - if ((groups = malloc(sizeof(gid_t) * ngroups_max)) == NULL) - err(1, "malloc"); - while ((ch = getopt(argc, argv, "nu:U:")) != -1) { + while ((ch = getopt(argc, argv, "lnu:U:")) != -1) { switch (ch) { + case 'l': + clean = 1; + break; case 'n': /* Specified name, now unused */ break; @@ -100,12 +88,15 @@ main(int argc, char *argv[]) } argc -= optind; argv += optind; - if (argc < 2) + if (argc < 1) usage(); if (uflag && Uflag) usage(); - if (uflag) - GET_USER_INFO; + if (uflag || (clean && !Uflag)) + /* User info from the home environment */ + get_user_info(username, &pwd, &lcap); + + /* Attach to the jail */ jid = jail_getid(argv[0]); if (jid < 0) errx(1, "%s", jail_errmsg); @@ -113,28 +104,88 @@ main(int argc, char *argv[]) err(1, "jail_attach(%d)", jid); if (chdir("/") == -1) err(1, "chdir(): /"); - if (username != NULL) { + + /* Set up user environment */ + if (clean || username != NULL) { if (Uflag) - GET_USER_INFO; - if (setgroups(ngroups, groups) != 0) - err(1, "setgroups"); + /* User info from the jail environment */ + get_user_info(username, &pwd, &lcap); + if (clean) { + term = getenv("TERM"); + cleanenv = NULL; + environ = &cleanenv; + setenv("PATH", "/bin:/usr/bin", 1); + if (term != NULL) + setenv("TERM", term, 1); + } if (setgid(pwd->pw_gid) != 0) err(1, "setgid"); - if (setusercontext(lcap, pwd, pwd->pw_uid, - LOGIN_SETALL & ~LOGIN_SETGROUP & ~LOGIN_SETLOGIN) != 0) + if (setusercontext(lcap, pwd, pwd->pw_uid, username + ? LOGIN_SETALL & ~LOGIN_SETGROUP & ~LOGIN_SETLOGIN + : LOGIN_SETPATH | LOGIN_SETENV) != 0) err(1, "setusercontext"); login_close(lcap); + setenv("USER", pwd->pw_name, 1); + setenv("HOME", pwd->pw_dir, 1); + setenv("SHELL", + *pwd->pw_shell ? pwd->pw_shell : _PATH_BSHELL, 1); + if (clean && chdir(pwd->pw_dir) < 0) + err(1, "chdir: %s", pwd->pw_dir); + endpwent(); + } + + /* Run the specified command, or the shell */ + if (argc > 1) { + if (execvp(argv[1], argv + 1) < 0) + err(1, "execvp: %s", argv[1]); + } else { + if (!(shell = getenv("SHELL"))) + shell = _PATH_BSHELL; + if (execlp(shell, shell, "-i", NULL) < 0) + err(1, "execlp: %s", shell); } - if (execvp(argv[1], argv + 1) == -1) - err(1, "execvp(): %s", argv[1]); exit(0); } +static void +get_user_info(const char *username, const struct passwd **pwdp, + login_cap_t **lcapp) +{ + uid_t uid; + const struct passwd *pwd; + + errno = 0; + if (username) { + pwd = getpwnam(username); + if (pwd == NULL) { + if (errno) + err(1, "getpwnam: %s", username); + else + errx(1, "%s: no such user", username); + } + } else { + uid = getuid(); + pwd = getpwuid(uid); + if (pwd == NULL) { + if (errno) + err(1, "getpwuid: %d", uid); + else + errx(1, "unknown uid: %d", uid); + } + } + *pwdp = pwd; + *lcapp = login_getpwclass(pwd); + if (*lcapp == NULL) + err(1, "getpwclass: %s", pwd->pw_name); + if (initgroups(pwd->pw_name, pwd->pw_gid) < 0) + err(1, "initgroups: %s", pwd->pw_name); +} + static void usage(void) { fprintf(stderr, "%s\n", - "usage: jexec [-u username | -U username] jail command ..."); + "usage: jexec [-l] [-u username | -U username] jail [command ...]"); exit(1); } diff --git a/usr.sbin/ntp/config.h b/usr.sbin/ntp/config.h index 30c325f36038..d8c341ca2c26 100644 --- a/usr.sbin/ntp/config.h +++ b/usr.sbin/ntp/config.h @@ -1782,3 +1782,8 @@ typedef union mpinfou { # endif #endif /* !defined(_KERNEL) && !defined(PARSESTREAM) */ +/* + * FreeBSD specific: Explicitly specify date/time for reproducible build. + */ +#define MKREPRO_DATE "Jul 04 2015" +#define MKREPRO_TIME "15:42:16" diff --git a/usr.sbin/ntp/scripts/mkver b/usr.sbin/ntp/scripts/mkver index f34267d20efb..0fc94beab0ab 100755 --- a/usr.sbin/ntp/scripts/mkver +++ b/usr.sbin/ntp/scripts/mkver @@ -6,7 +6,7 @@ PROG=${1-UNKNOWN} ConfStr="$PROG" -ConfStr="$ConfStr 4.2.8p2" +ConfStr="$ConfStr 4.2.8p3" case "$CSET" in '') ;; diff --git a/usr.sbin/pw/Makefile b/usr.sbin/pw/Makefile index 4bcf6917ff13..c265399730c7 100644 --- a/usr.sbin/pw/Makefile +++ b/usr.sbin/pw/Makefile @@ -3,8 +3,7 @@ PROG= pw MAN= pw.conf.5 pw.8 SRCS= pw.c pw_conf.c pw_user.c pw_group.c pw_log.c pw_nis.c pw_vpw.c \ - grupd.c pwupd.c fileupd.c psdate.c \ - bitmap.c cpdir.c rm_r.c + grupd.c pwupd.c psdate.c bitmap.c cpdir.c rm_r.c WARNS?= 3 diff --git a/usr.sbin/pw/cpdir.c b/usr.sbin/pw/cpdir.c index 0fd671b049d5..e84d0f34a6bc 100644 --- a/usr.sbin/pw/cpdir.c +++ b/usr.sbin/pw/cpdir.c @@ -45,87 +45,85 @@ static const char rcsid[] = #include "pwupd.h" void -copymkdir(char const * dir, char const * skel, mode_t mode, uid_t uid, gid_t gid) +copymkdir(int rootfd, char const * dir, int skelfd, mode_t mode, uid_t uid, + gid_t gid, int flags) { - char src[MAXPATHLEN]; - char dst[MAXPATHLEN]; - char lnk[MAXPATHLEN]; - int len; + char *p, lnk[MAXPATHLEN], copybuf[4096]; + int len, homefd, srcfd, destfd; + ssize_t sz; + struct stat st; + struct dirent *e; + DIR *d; - if (mkdir(dir, mode) != 0 && errno != EEXIST) { + if (*dir == '/') + dir++; + + if (mkdirat(rootfd, dir, mode) != 0 && errno != EEXIST) { warn("mkdir(%s)", dir); - } else { - int infd, outfd; - struct stat st; - - static char counter = 0; - static char *copybuf = NULL; - - ++counter; - chown(dir, uid, gid); - if (skel != NULL && *skel != '\0') { - DIR *d = opendir(skel); - - if (d != NULL) { - struct dirent *e; - - while ((e = readdir(d)) != NULL) { - char *p = e->d_name; - - if (snprintf(src, sizeof(src), "%s/%s", skel, p) >= (int)sizeof(src)) - warn("warning: pathname too long '%s/%s' (skel not copied)", skel, p); - else if (lstat(src, &st) == 0) { - if (strncmp(p, "dot.", 4) == 0) /* Conversion */ - p += 3; - if (snprintf(dst, sizeof(dst), "%s/%s", dir, p) >= (int)sizeof(dst)) - warn("warning: path too long '%s/%s' (skel file skipped)", dir, p); - else { - if (S_ISDIR(st.st_mode)) { /* Recurse for this */ - if (strcmp(e->d_name, ".") != 0 && strcmp(e->d_name, "..") != 0) - copymkdir(dst, src, st.st_mode & _DEF_DIRMODE, uid, gid); - chflags(dst, st.st_flags); /* propagate flags */ - } else if (S_ISLNK(st.st_mode) && (len = readlink(src, lnk, sizeof(lnk) - 1)) != -1) { - lnk[len] = '\0'; - symlink(lnk, dst); - lchown(dst, uid, gid); - /* - * Note: don't propagate special attributes - * but do propagate file flags - */ - } else if (S_ISREG(st.st_mode) && (outfd = open(dst, O_RDWR | O_CREAT | O_EXCL, st.st_mode)) != -1) { - if ((infd = open(src, O_RDONLY)) == -1) { - close(outfd); - remove(dst); - } else { - int b; - - /* - * Allocate our copy buffer if we need to - */ - if (copybuf == NULL) - copybuf = malloc(4096); - while ((b = read(infd, copybuf, 4096)) > 0) - write(outfd, copybuf, b); - close(infd); - /* - * Propagate special filesystem flags - */ - fchown(outfd, uid, gid); - fchflags(outfd, st.st_flags); - close(outfd); - chown(dst, uid, gid); - } - } - } - } - } - closedir(d); - } - } - if (--counter == 0 && copybuf != NULL) { - free(copybuf); - copybuf = NULL; - } + return; } -} + fchownat(rootfd, dir, uid, gid, AT_SYMLINK_NOFOLLOW); + if (flags > 0) + chflagsat(rootfd, dir, flags, AT_SYMLINK_NOFOLLOW); + if (skelfd == -1) + return; + + homefd = openat(rootfd, dir, O_DIRECTORY); + if ((d = fdopendir(skelfd)) == NULL) { + close(skelfd); + close(homefd); + return; + } + + while ((e = readdir(d)) != NULL) { + if (strcmp(e->d_name, ".") == 0 || strcmp(e->d_name, "..") == 0) + continue; + + p = e->d_name; + if (fstatat(skelfd, p, &st, AT_SYMLINK_NOFOLLOW) == -1) + continue; + + if (strncmp(p, "dot.", 4) == 0) /* Conversion */ + p += 3; + + if (S_ISDIR(st.st_mode)) { + copymkdir(homefd, p, openat(skelfd, e->d_name, O_DIRECTORY), + st.st_mode & _DEF_DIRMODE, uid, gid, st.st_flags); + continue; + } + + if (S_ISLNK(st.st_mode) && + (len = readlinkat(skelfd, e->d_name, lnk, sizeof(lnk) -1)) + != -1) { + lnk[len] = '\0'; + symlinkat(lnk, homefd, p); + fchownat(homefd, p, uid, gid, AT_SYMLINK_NOFOLLOW); + continue; + } + + if (!S_ISREG(st.st_mode)) + continue; + + if ((srcfd = openat(skelfd, e->d_name, O_RDONLY)) == -1) + continue; + destfd = openat(homefd, p, O_RDWR | O_CREAT | O_EXCL, + st.st_mode); + if (destfd == -1) { + close(srcfd); + continue; + } + + while ((sz = read(srcfd, copybuf, sizeof(copybuf))) > 0) + write(destfd, copybuf, sz); + + close(srcfd); + /* + * Propagate special filesystem flags + */ + fchown(destfd, uid, gid); + fchflags(destfd, st.st_flags); + close(destfd); + } + closedir(d); +} diff --git a/usr.sbin/pw/pw.c b/usr.sbin/pw/pw.c index 6769738fbe30..5ad2511aeb10 100644 --- a/usr.sbin/pw/pw.c +++ b/usr.sbin/pw/pw.c @@ -136,8 +136,10 @@ main(int argc, char *argv[]) name = NULL; relocated = nis = false; memset(&conf, 0, sizeof(conf)); + strlcpy(conf.rootdir, "/", sizeof(conf.rootdir)); strlcpy(conf.etcpath, _PATH_PWD, sizeof(conf.etcpath)); conf.fd = -1; + conf.checkduplicate = true; LIST_INIT(&arglist); @@ -215,6 +217,9 @@ main(int argc, char *argv[]) if (mode == -1 || which == -1) cmdhelp(mode, which); + conf.rootfd = open(conf.rootdir, O_DIRECTORY|O_CLOEXEC); + if (conf.rootfd == -1) + errx(EXIT_FAILURE, "Unable to open '%s'", conf.rootdir); conf.which = which; /* * We know which mode we're in and what we're about to do, so now @@ -234,6 +239,9 @@ main(int argc, char *argv[]) conf.config = optarg; config = conf.config; break; + case 'F': + conf.force = true; + break; case 'N': conf.dryrun = true; break; @@ -248,6 +256,12 @@ main(int argc, char *argv[]) case 'Y': nis = true; break; + case 'a': + conf.all = true; + break; + case 'c': + conf.gecos = pw_checkname(optarg, 1); + break; case 'g': if (which == 0) { /* for user* */ addarg(&arglist, 'g', optarg); @@ -312,7 +326,13 @@ main(int argc, char *argv[]) "descriptor or '-'"); break; case 'o': - conf.checkduplicate = true; + conf.checkduplicate = false; + break; + case 'q': + conf.quiet = true; + break; + case 'r': + conf.deletehome = true; break; default: addarg(&arglist, ch, optarg); @@ -334,7 +354,7 @@ main(int argc, char *argv[]) * We should immediately look for the -q 'quiet' switch so that we * don't bother with extraneous errors */ - if (getarg(&arglist, 'q') != NULL) + if (conf.quiet) freopen(_PATH_DEVNULL, "w", stderr); /* @@ -567,7 +587,12 @@ cmdhelp(int mode, int which) struct carg * getarg(struct cargs * _args, int ch) { - struct carg *c = LIST_FIRST(_args); + struct carg *c; + + if (_args == NULL) + return (NULL); + + c = LIST_FIRST(_args); while (c != NULL && c->ch != ch) c = LIST_NEXT(c, list); diff --git a/usr.sbin/pw/pw.h b/usr.sbin/pw/pw.h index 6239004b61f7..ed3b7158e907 100644 --- a/usr.sbin/pw/pw.h +++ b/usr.sbin/pw/pw.h @@ -83,7 +83,9 @@ struct carg *addarg(struct cargs * _args, int ch, char *argstr); struct carg *getarg(struct cargs * _args, int ch); int pw_user(int mode, char *name, long id, struct cargs * _args); +int pw_usernext(struct userconf *cnf, bool quiet); int pw_group(int mode, char *name, long id, struct cargs * _args); +int pw_groupnext(struct userconf *cnf, bool quiet); char *pw_checkname(char *name, int gecos); int addnispwent(const char *path, struct passwd *pwd); diff --git a/usr.sbin/pw/pw_conf.c b/usr.sbin/pw/pw_conf.c index 24c06508aba4..33bb6b3105e7 100644 --- a/usr.sbin/pw/pw_conf.c +++ b/usr.sbin/pw/pw_conf.c @@ -104,8 +104,7 @@ static struct userconf config = 1000, 32000, /* Allowed range of uids */ 1000, 32000, /* Allowed range of gids */ 0, /* Days until account expires */ - 0, /* Days until password expires */ - 0 /* size of default_group array */ + 0 /* Days until password expires */ }; static char const *comments[_UC_FIELDS] = @@ -234,10 +233,9 @@ read_userconfig(char const * file) buf = NULL; linecap = 0; - config.numgroups = 200; - config.groups = calloc(config.numgroups, sizeof(char *)); + config.groups = sl_init(); if (config.groups == NULL) - err(1, "calloc()"); + err(1, "sl_init()"); if (file == NULL) file = _PATH_PW_CONF; @@ -316,13 +314,8 @@ read_userconfig(char const * file) ? NULL : newstr(q); break; case _UC_EXTRAGROUPS: - for (i = 0; q != NULL; q = strtok(NULL, toks)) { - if (extendarray(&config.groups, &config.numgroups, i + 2) != -1) - config.groups[i++] = newstr(q); - } - if (i > 0) - while (i < config.numgroups) - config.groups[i++] = NULL; + for (i = 0; q != NULL; q = strtok(NULL, toks)) + sl_add(config.groups, newstr(q)); break; case _UC_DEFAULTCLASS: config.default_class = (q == NULL || !boolean_val(q, 1)) @@ -442,10 +435,10 @@ write_userconfig(char const * file) config.default_group : ""); break; case _UC_EXTRAGROUPS: - for (j = 0; j < config.numgroups && - config.groups[j] != NULL; j++) + for (j = 0; config.groups != NULL && + j < (int)config.groups->sl_cur; j++) sbuf_printf(buf, "%s\"%s\"", j ? - "," : "", config.groups[j]); + "," : "", config.groups->sl_str[j]); quote = 0; break; case _UC_DEFAULTCLASS: diff --git a/usr.sbin/pw/pw_group.c b/usr.sbin/pw/pw_group.c index c664ef5a70d6..b0db3cffbc45 100644 --- a/usr.sbin/pw/pw_group.c +++ b/usr.sbin/pw/pw_group.c @@ -42,8 +42,7 @@ static const char rcsid[] = static struct passwd *lookup_pwent(const char *user); -static void delete_members(char ***members, int *grmembers, int *i, - struct carg *arg, struct group *grp); +static void delete_members(struct group *grp, char *list); static int print_group(struct group * grp); static gid_t gr_gidpolicy(struct userconf * cnf, long id); @@ -91,14 +90,78 @@ set_passwd(struct group *grp, bool update) grp->gr_passwd = pw_pwcrypt(line); } +int +pw_groupnext(struct userconf *cnf, bool quiet) +{ + gid_t next = gr_gidpolicy(cnf, -1); + + if (quiet) + return (next); + printf("%u\n", next); + + return (EXIT_SUCCESS); +} + +static int +pw_groupshow(const char *name, long id, struct group *fakegroup) +{ + struct group *grp = NULL; + + if (id < 0 && name == NULL && !conf.all) + errx(EX_DATAERR, "groupname or id or '-a' required"); + + if (conf.all) { + SETGRENT(); + while ((grp = GETGRENT()) != NULL) + print_group(grp); + ENDGRENT(); + + return (EXIT_SUCCESS); + } + + grp = (name != NULL) ? GETGRNAM(name) : GETGRGID(id); + if (grp == NULL) { + if (conf.force) { + grp = fakegroup; + } else { + if (name == NULL) + errx(EX_DATAERR, "unknown gid `%ld'", id); + errx(EX_DATAERR, "unknown group `%s'", name); + } + } + + return (print_group(grp)); +} + +static int +pw_groupdel(const char *name, long id) +{ + struct group *grp = NULL; + int rc; + + grp = (name != NULL) ? GETGRNAM(name) : GETGRGID(id); + if (grp == NULL) { + if (name == NULL) + errx(EX_DATAERR, "unknown gid `%ld'", id); + errx(EX_DATAERR, "unknown group `%s'", name); + } + + rc = delgrent(grp); + if (rc == -1) + err(EX_IOERR, "group '%s' not available (NIS?)", name); + else if (rc != 0) + err(EX_IOERR, "group update"); + pw_log(conf.userconf, M_DELETE, W_GROUP, "%s(%ld) removed", name, id); + + return (EXIT_SUCCESS); +} + int pw_group(int mode, char *name, long id, struct cargs * args) { int rc; struct carg *arg; struct group *grp = NULL; - int grmembers = 0; - char **members = NULL; struct userconf *cnf = conf.userconf; static struct group fakegroup = @@ -109,46 +172,28 @@ pw_group(int mode, char *name, long id, struct cargs * args) NULL }; + if (mode == M_NEXT) + return (pw_groupnext(cnf, conf.quiet)); + + if (mode == M_PRINT) + return (pw_groupshow(name, id, &fakegroup)); + + if (mode == M_DELETE) + return (pw_groupdel(name, id)); + if (mode == M_LOCK || mode == M_UNLOCK) errx(EX_USAGE, "'lock' command is not available for groups"); - /* - * With M_NEXT, we only need to return the - * next gid to stdout - */ - if (mode == M_NEXT) { - gid_t next = gr_gidpolicy(cnf, id); - if (getarg(args, 'q')) - return next; - printf("%u\n", next); - return EXIT_SUCCESS; - } - - if (mode == M_PRINT && getarg(args, 'a')) { - SETGRENT(); - while ((grp = GETGRENT()) != NULL) - print_group(grp); - ENDGRENT(); - return EXIT_SUCCESS; - } if (id < 0 && name == NULL) errx(EX_DATAERR, "group name or id required"); grp = (name != NULL) ? GETGRNAM(name) : GETGRGID(id); - if (mode == M_UPDATE || mode == M_DELETE || mode == M_PRINT) { + if (mode == M_UPDATE) { if (name == NULL && grp == NULL) /* Try harder */ grp = GETGRGID(id); if (grp == NULL) { - if (mode == M_PRINT && getarg(args, 'F')) { - char *fmems[1]; - fmems[0] = NULL; - fakegroup.gr_name = name ? name : "nogroup"; - fakegroup.gr_gid = (gid_t) id; - fakegroup.gr_mem = fmems; - return print_group(&fakegroup); - } if (name == NULL) errx(EX_DATAERR, "unknown group `%s'", name); else @@ -157,22 +202,6 @@ pw_group(int mode, char *name, long id, struct cargs * args) if (name == NULL) /* Needed later */ name = grp->gr_name; - /* - * Handle deletions now - */ - if (mode == M_DELETE) { - rc = delgrent(grp); - if (rc == -1) - err(EX_IOERR, "group '%s' not available (NIS?)", - name); - else if (rc != 0) { - err(EX_IOERR, "group update"); - } - pw_log(cnf, mode, W_GROUP, "%s(%ld) removed", name, id); - return EXIT_SUCCESS; - } else if (mode == M_PRINT) - return print_group(grp); - if (id > 0) grp->gr_gid = (gid_t) id; @@ -184,13 +213,11 @@ pw_group(int mode, char *name, long id, struct cargs * args) else if (grp != NULL) /* Exists */ errx(EX_DATAERR, "group name `%s' already exists", name); - extendarray(&members, &grmembers, 200); - members[0] = NULL; grp = &fakegroup; grp->gr_name = pw_checkname(name, 0); grp->gr_passwd = "*"; grp->gr_gid = gr_gidpolicy(cnf, id); - grp->gr_mem = members; + grp->gr_mem = NULL; } /* @@ -206,42 +233,31 @@ pw_group(int mode, char *name, long id, struct cargs * args) if (((arg = getarg(args, 'M')) != NULL || (arg = getarg(args, 'd')) != NULL || (arg = getarg(args, 'm')) != NULL) && arg->val) { - int i = 0; char *p; struct passwd *pwd; /* Make sure this is not stay NULL with -M "" */ - extendarray(&members, &grmembers, 200); if (arg->ch == 'd') - delete_members(&members, &grmembers, &i, arg, grp); - else if (arg->ch == 'm') { - int k = 0; + delete_members(grp, arg->val); + else if (arg->ch == 'M') + grp->gr_mem = NULL; - if (grp->gr_mem != NULL) { - while (grp->gr_mem[k] != NULL) { - if (extendarray(&members, &grmembers, i + 2) != -1) - members[i++] = grp->gr_mem[k]; - k++; - } + for (p = strtok(arg->val, ", \t"); arg->ch != 'd' && p != NULL; + p = strtok(NULL, ", \t")) { + int j; + + /* + * Check for duplicates + */ + pwd = lookup_pwent(p); + for (j = 0; grp->gr_mem != NULL && grp->gr_mem[j] != NULL; j++) { + if (strcmp(grp->gr_mem[j], pwd->pw_name) == 0) + break; } + if (grp->gr_mem != NULL && grp->gr_mem[j] != NULL) + continue; + grp = gr_add(grp, pwd->pw_name); } - - if (arg->ch != 'd') - for (p = strtok(arg->val, ", \t"); p != NULL; p = strtok(NULL, ", \t")) { - int j; - - /* - * Check for duplicates - */ - pwd = lookup_pwent(p); - for (j = 0; j < i && strcmp(members[j], pwd->pw_name) != 0; j++) - ; - if (j == i && extendarray(&members, &grmembers, i + 2) != -1) - members[i++] = newstr(pwd->pw_name); - } - while (i < grmembers) - members[i++] = NULL; - grp->gr_mem = members; } if (conf.dryrun) @@ -269,8 +285,6 @@ pw_group(int mode, char *name, long id, struct cargs * args) pw_log(cnf, mode, W_GROUP, "%s(%u)", grp->gr_name, grp->gr_gid); - free(members); - return EXIT_SUCCESS; } @@ -296,42 +310,25 @@ lookup_pwent(const char *user) * Delete requested members from a group. */ static void -delete_members(char ***members, int *grmembers, int *i, struct carg *arg, - struct group *grp) +delete_members(struct group *grp, char *list) { - bool matchFound; - char *user; - char *valueCopy; - char *valuePtr; + char *p; int k; - struct passwd *pwd; if (grp->gr_mem == NULL) return; - k = 0; - while (grp->gr_mem[k] != NULL) { - matchFound = false; - if ((valueCopy = strdup(arg->val)) == NULL) - errx(EX_UNAVAILABLE, "out of memory"); - valuePtr = valueCopy; - while ((user = strsep(&valuePtr, ", \t")) != NULL) { - pwd = lookup_pwent(user); - if (strcmp(grp->gr_mem[k], pwd->pw_name) == 0) { - matchFound = true; + for (p = strtok(list, ", \t"); p != NULL; p = strtok(NULL, ", \t")) { + for (k = 0; grp->gr_mem[k] != NULL; k++) { + if (strcmp(grp->gr_mem[k], p) == 0) break; - } } - free(valueCopy); + if (grp->gr_mem[k] == NULL) /* No match */ + continue; - if (!matchFound && - extendarray(members, grmembers, *i + 2) != -1) - (*members)[(*i)++] = grp->gr_mem[k]; - - k++; + for (; grp->gr_mem[k] != NULL; k++) + grp->gr_mem[k] = grp->gr_mem[k+1]; } - - return; } diff --git a/usr.sbin/pw/pw_user.c b/usr.sbin/pw/pw_user.c index e123786474ee..d6dad3f3c52b 100644 --- a/usr.sbin/pw/pw_user.c +++ b/usr.sbin/pw/pw_user.c @@ -51,8 +51,7 @@ static const char rcsid[] = static char locked_str[] = "*LOCKED*"; -static int delete_user(struct userconf *cnf, struct passwd *pwd, - char *name, int delete, int mode); +static int pw_userdel(char *name, long id); static int print_user(struct passwd * pwd); static uid_t pw_uidpolicy(struct userconf * cnf, long id); static uid_t pw_gidpolicy(struct cargs * args, char *nam, gid_t prefer); @@ -60,29 +59,29 @@ static time_t pw_pwdpolicy(struct userconf * cnf, struct cargs * args); static time_t pw_exppolicy(struct userconf * cnf, struct cargs * args); static char *pw_homepolicy(struct userconf * cnf, struct cargs * args, char const * user); static char *pw_shellpolicy(struct userconf * cnf, struct cargs * args, char *newshell); -static char *pw_password(struct userconf * cnf, struct cargs * args, char const * user); +static char *pw_password(struct userconf * cnf, char const * user); static char *shell_path(char const * path, char *shells[], char *sh); static void rmat(uid_t uid); static void rmopie(char const * name); static void -create_and_populate_homedir(int mode, struct passwd *pwd) +create_and_populate_homedir(struct passwd *pwd) { - char *homedir, *dotdir; struct userconf *cnf = conf.userconf; + const char *skeldir; + int skelfd = -1; - homedir = dotdir = NULL; + skeldir = cnf->dotdir; - if (conf.rootdir[0] != '\0') { - asprintf(&homedir, "%s/%s", conf.rootdir, pwd->pw_dir); - if (homedir == NULL) - errx(EX_OSERR, "out of memory"); - asprintf(&dotdir, "%s/%s", conf.rootdir, cnf->dotdir); + if (skeldir != NULL && *skeldir != '\0') { + if (*skeldir == '/') + skeldir++; + skelfd = openat(conf.rootfd, skeldir, O_DIRECTORY|O_CLOEXEC); } - copymkdir(homedir ? homedir : pwd->pw_dir, dotdir ? dotdir: cnf->dotdir, - cnf->homemode, pwd->pw_uid, pwd->pw_gid); - pw_log(cnf, mode, W_USER, "%s(%u) home %s made", pwd->pw_name, + copymkdir(conf.rootfd, pwd->pw_dir, skelfd, cnf->homemode, pwd->pw_uid, + pwd->pw_gid, 0); + pw_log(cnf, M_ADD, W_USER, "%s(%u) home %s made", pwd->pw_name, pwd->pw_uid, pwd->pw_dir); } @@ -148,6 +147,122 @@ set_passwd(struct passwd *pwd, bool update) return (1); } +int +pw_usernext(struct userconf *cnf, bool quiet) +{ + uid_t next = pw_uidpolicy(cnf, -1); + + if (quiet) + return (next); + + printf("%u:", next); + pw_groupnext(cnf, quiet); + + return (EXIT_SUCCESS); +} + +static int +pw_usershow(char *name, long id, struct passwd *fakeuser) +{ + struct passwd *pwd = NULL; + + if (id < 0 && name == NULL && !conf.all) + errx(EX_DATAERR, "username or id or '-a' required"); + + if (conf.all) { + SETPWENT(); + while ((pwd = GETPWENT()) != NULL) + print_user(pwd); + ENDPWENT(); + return (EXIT_SUCCESS); + } + + pwd = (name != NULL) ? GETPWNAM(pw_checkname(name, 0)) : GETPWUID(id); + if (pwd == NULL) { + if (conf.force) { + pwd = fakeuser; + } else { + if (name == NULL) + errx(EX_NOUSER, "no such uid `%ld'", id); + errx(EX_NOUSER, "no such user `%s'", name); + } + } + + return (print_user(pwd)); +} + +static void +perform_chgpwent(const char *name, struct passwd *pwd) +{ + int rc; + + rc = chgpwent(name, pwd); + if (rc == -1) + errx(EX_IOERR, "user '%s' does not exist (NIS?)", pwd->pw_name); + else if (rc != 0) + err(EX_IOERR, "passwd file update"); + + if (conf.userconf->nispasswd && *conf.userconf->nispasswd == '/') { + rc = chgnispwent(conf.userconf->nispasswd, name, pwd); + if (rc == -1) + warn("User '%s' not found in NIS passwd", pwd->pw_name); + else + warn("NIS passwd update"); + /* NOTE: NIS-only update errors are not fatal */ + } +} + +/* + * The M_LOCK and M_UNLOCK functions simply add or remove + * a "*LOCKED*" prefix from in front of the password to + * prevent it decoding correctly, and therefore prevents + * access. Of course, this only prevents access via + * password authentication (not ssh, kerberos or any + * other method that does not use the UNIX password) but + * that is a known limitation. + */ +static int +pw_userlock(char *name, long id, int mode) +{ + struct passwd *pwd = NULL; + char *passtmp = NULL; + bool locked = false; + + if (id < 0 && name == NULL) + errx(EX_DATAERR, "username or id required"); + + pwd = (name != NULL) ? GETPWNAM(pw_checkname(name, 0)) : GETPWUID(id); + if (pwd == NULL) { + if (name == NULL) + errx(EX_NOUSER, "no such uid `%ld'", id); + errx(EX_NOUSER, "no such user `%s'", name); + } + + if (name == NULL) + name = pwd->pw_name; + + if (strncmp(pwd->pw_passwd, locked_str, sizeof(locked_str) -1) == 0) + locked = true; + if (mode == M_LOCK && locked) + errx(EX_DATAERR, "user '%s' is already locked", pwd->pw_name); + if (mode == M_UNLOCK && !locked) + errx(EX_DATAERR, "user '%s' is not locked", pwd->pw_name); + + if (mode == M_LOCK) { + asprintf(&passtmp, "%s%s", locked_str, pwd->pw_passwd); + if (passtmp == NULL) /* disaster */ + errx(EX_UNAVAILABLE, "out of memory"); + pwd->pw_passwd = passtmp; + } else { + pwd->pw_passwd += sizeof(locked_str)-1; + } + + perform_chgpwent(name, pwd); + free(passtmp); + + return (EXIT_SUCCESS); +} + /*- * -C config configuration file * -q quiet operation @@ -185,7 +300,6 @@ pw_user(int mode, char *name, long id, struct cargs * args) { int rc, edited = 0; char *p = NULL; - char *passtmp; struct carg *arg; struct passwd *pwd = NULL; struct group *grp; @@ -199,7 +313,7 @@ pw_user(int mode, char *name, long id, struct cargs * args) static struct passwd fakeuser = { - NULL, + "nouser", "*", -1, -1, @@ -216,19 +330,17 @@ pw_user(int mode, char *name, long id, struct cargs * args) cnf = conf.userconf; - /* - * With M_NEXT, we only need to return the - * next uid to stdout - */ if (mode == M_NEXT) - { - uid_t next = pw_uidpolicy(cnf, id); - if (getarg(args, 'q')) - return next; - printf("%u:", next); - pw_group(mode, name, -1, args); - return EXIT_SUCCESS; - } + return (pw_usernext(cnf, conf.quiet)); + + if (mode == M_PRINT) + return (pw_usershow(name, id, &fakeuser)); + + if (mode == M_DELETE) + return (pw_userdel(name, id)); + + if (mode == M_LOCK || mode == M_UNLOCK) + return (pw_userlock(name, id, mode)); /* * We can do all of the common legwork here @@ -288,7 +400,7 @@ pw_user(int mode, char *name, long id, struct cargs * args) *p = '\0'; if (stat(dbuf, &st) == -1) { if (mkdir(dbuf, _DEF_DIRMODE) == -1) - goto direrr; + err(EX_OSFILE, "mkdir '%s'", dbuf); chown(dbuf, 0, 0); } else if (!S_ISDIR(st.st_mode)) errx(EX_OSFILE, "'%s' (root home parent) is not a directory", dbuf); @@ -296,9 +408,8 @@ pw_user(int mode, char *name, long id, struct cargs * args) } } if (stat(dbuf, &st) == -1) { - if (mkdir(dbuf, _DEF_DIRMODE) == -1) { - direrr: err(EX_OSFILE, "mkdir '%s'", dbuf); - } + if (mkdir(dbuf, _DEF_DIRMODE) == -1) + err(EX_OSFILE, "mkdir '%s'", dbuf); chown(dbuf, 0, 0); } } else if (!S_ISDIR(st.st_mode)) @@ -329,23 +440,23 @@ pw_user(int mode, char *name, long id, struct cargs * args) cnf->default_class = pw_checkname(arg->val, 0); if ((arg = getarg(args, 'G')) != NULL && arg->val) { - int i = 0; - for (p = strtok(arg->val, ", \t"); p != NULL; p = strtok(NULL, ", \t")) { if ((grp = GETGRNAM(p)) == NULL) { if (!isdigit((unsigned char)*p) || (grp = GETGRGID((gid_t) atoi(p))) == NULL) errx(EX_NOUSER, "group `%s' does not exist", p); } - if (extendarray(&cnf->groups, &cnf->numgroups, i + 2) != -1) - cnf->groups[i++] = newstr(grp->gr_name); + sl_add(cnf->groups, newstr(grp->gr_name)); } - while (i < cnf->numgroups) - cnf->groups[i++] = NULL; } if ((arg = getarg(args, 'k')) != NULL) { - if (stat(cnf->dotdir = arg->val, &st) == -1 || !S_ISDIR(st.st_mode)) - errx(EX_OSFILE, "skeleton `%s' is not a directory or does not exist", cnf->dotdir); + char *tmp = cnf->dotdir = arg->val; + if (*tmp == '/') + tmp++; + if ((fstatat(conf.rootfd, tmp, &st, 0) == -1) || + !S_ISDIR(st.st_mode)) + errx(EX_OSFILE, "skeleton `%s' is not a directory or " + "does not exist", cnf->dotdir); } if ((arg = getarg(args, 's')) != NULL) @@ -374,14 +485,6 @@ pw_user(int mode, char *name, long id, struct cargs * args) err(EX_IOERR, "config udpate"); } - if (mode == M_PRINT && getarg(args, 'a')) { - SETPWENT(); - while ((pwd = GETPWENT()) != NULL) - print_user(pwd); - ENDPWENT(); - return EXIT_SUCCESS; - } - if (name != NULL) pwd = GETPWNAM(pw_checkname(name, 0)); @@ -389,20 +492,14 @@ pw_user(int mode, char *name, long id, struct cargs * args) errx(EX_DATAERR, "user name or id required"); /* - * Update, delete & print require that the user exists + * Update require that the user exists */ - if (mode == M_UPDATE || mode == M_DELETE || - mode == M_PRINT || mode == M_LOCK || mode == M_UNLOCK) { + if (mode == M_UPDATE) { if (name == NULL && pwd == NULL) /* Try harder */ pwd = GETPWUID(id); if (pwd == NULL) { - if (mode == M_PRINT && getarg(args, 'F')) { - fakeuser.pw_name = name ? name : "nouser"; - fakeuser.pw_uid = (uid_t) id; - return print_user(&fakeuser); - } if (name == NULL) errx(EX_NOUSER, "no such uid `%ld'", id); errx(EX_NOUSER, "no such user `%s'", name); @@ -411,35 +508,6 @@ pw_user(int mode, char *name, long id, struct cargs * args) if (name == NULL) name = pwd->pw_name; - /* - * The M_LOCK and M_UNLOCK functions simply add or remove - * a "*LOCKED*" prefix from in front of the password to - * prevent it decoding correctly, and therefore prevents - * access. Of course, this only prevents access via - * password authentication (not ssh, kerberos or any - * other method that does not use the UNIX password) but - * that is a known limitation. - */ - - if (mode == M_LOCK) { - if (strncmp(pwd->pw_passwd, locked_str, sizeof(locked_str)-1) == 0) - errx(EX_DATAERR, "user '%s' is already locked", pwd->pw_name); - asprintf(&passtmp, "%s%s", locked_str, pwd->pw_passwd); - if (passtmp == NULL) /* disaster */ - errx(EX_UNAVAILABLE, "out of memory"); - pwd->pw_passwd = passtmp; - edited = 1; - } else if (mode == M_UNLOCK) { - if (strncmp(pwd->pw_passwd, locked_str, sizeof(locked_str)-1) != 0) - errx(EX_DATAERR, "user '%s' is not locked", pwd->pw_name); - pwd->pw_passwd += sizeof(locked_str)-1; - edited = 1; - } else if (mode == M_DELETE) - return (delete_user(cnf, pwd, name, - getarg(args, 'r') != NULL, mode)); - else if (mode == M_PRINT) - return print_user(pwd); - /* * The rest is edit code */ @@ -540,7 +608,7 @@ pw_user(int mode, char *name, long id, struct cargs * args) login_setcryptfmt(lc, "sha512", NULL) == NULL) warn("setting crypt(3) format"); login_close(lc); - pwd->pw_passwd = pw_password(cnf, args, pwd->pw_name); + pwd->pw_passwd = pw_password(cnf, pwd->pw_name); edited = 1; } @@ -572,7 +640,7 @@ pw_user(int mode, char *name, long id, struct cargs * args) if (lc == NULL || login_setcryptfmt(lc, "sha512", NULL) == NULL) warn("setting crypt(3) format"); login_close(lc); - pwd->pw_passwd = pw_password(cnf, args, pwd->pw_name); + pwd->pw_passwd = pw_password(cnf, pwd->pw_name); edited = 1; if (pwd->pw_uid == 0 && strcmp(pwd->pw_name, "root") != 0) @@ -582,10 +650,9 @@ pw_user(int mode, char *name, long id, struct cargs * args) /* * Shared add/edit code */ - if ((arg = getarg(args, 'c')) != NULL) { - char *gecos = pw_checkname(arg->val, 1); - if (strcmp(pwd->pw_gecos, gecos) != 0) { - pwd->pw_gecos = gecos; + if (conf.gecos != NULL) { + if (strcmp(pwd->pw_gecos, conf.gecos) != 0) { + pwd->pw_gecos = conf.gecos; edited = 1; } } @@ -615,30 +682,16 @@ pw_user(int mode, char *name, long id, struct cargs * args) warn("NIS passwd update"); /* NOTE: we treat NIS-only update errors as non-fatal */ } - } else if (mode == M_UPDATE || mode == M_LOCK || mode == M_UNLOCK) { - if (edited) { /* Only updated this if required */ - rc = chgpwent(name, pwd); - if (rc == -1) - errx(EX_IOERR, "user '%s' does not exist (NIS?)", pwd->pw_name); - else if (rc != 0) - err(EX_IOERR, "passwd file update"); - if ( cnf->nispasswd && *cnf->nispasswd=='/') { - rc = chgnispwent(cnf->nispasswd, name, pwd); - if (rc == -1) - warn("User '%s' not found in NIS passwd", pwd->pw_name); - else - warn("NIS passwd update"); - /* NOTE: NIS-only update errors are not fatal */ - } - } - } + } else if (mode == M_UPDATE && edited) /* Only updated this if required */ + perform_chgpwent(name, pwd); /* * Ok, user is created or changed - now edit group file */ if (mode == M_ADD || getarg(args, 'G') != NULL) { - int i, j; + int j; + size_t i; /* First remove the user from all group */ SETGRENT(); while ((grp = GETGRENT()) != NULL) { @@ -657,8 +710,8 @@ pw_user(int mode, char *name, long id, struct cargs * args) ENDGRENT(); /* now add to group where needed */ - for (i = 0; cnf->groups[i] != NULL; i++) { - grp = GETGRNAM(cnf->groups[i]); + for (i = 0; i < cnf->groups->sl_cur; i++) { + grp = GETGRNAM(cnf->groups->sl_str[i]); grp = gr_add(grp, pwd->pw_name); /* * grp can only be NULL in 2 cases: @@ -668,7 +721,7 @@ pw_user(int mode, char *name, long id, struct cargs * args) */ if (grp == NULL) continue; - chggrent(cnf->groups[i], grp); + chggrent(grp->gr_name, grp); free(grp); } } @@ -699,12 +752,12 @@ pw_user(int mode, char *name, long id, struct cargs * args) */ if (mode == M_ADD) { if (PWALTDIR() != PWF_ALT) { - arg = getarg(args, 'R'); - snprintf(path, sizeof(path), "%s%s/%s", - arg ? arg->val : "", _PATH_MAILDIR, pwd->pw_name); - close(open(path, O_RDWR | O_CREAT, 0600)); /* Preserve contents & - * mtime */ - chown(path, pwd->pw_uid, pwd->pw_gid); + snprintf(path, sizeof(path), "%s/%s", _PATH_MAILDIR, + pwd->pw_name); + close(openat(conf.rootfd, path +1, O_RDWR | O_CREAT, + 0600)); /* Preserve contents & mtime */ + fchownat(conf.rootfd, path + 1, pwd->pw_uid, + pwd->pw_gid, AT_SYMLINK_NOFOLLOW); } } @@ -715,7 +768,7 @@ pw_user(int mode, char *name, long id, struct cargs * args) */ if (PWALTDIR() != PWF_ALT && getarg(args, 'm') != NULL && pwd->pw_dir && *pwd->pw_dir == '/' && pwd->pw_dir[1]) - create_and_populate_homedir(mode, pwd); + create_and_populate_homedir(pwd); /* * Finally, send mail to the new user as well, if we are asked to @@ -751,7 +804,7 @@ pw_uidpolicy(struct userconf * cnf, long id) /* * Check the given uid, if any */ - if (id > 0) { + if (id >= 0) { uid = (uid_t) id; if ((pwd = GETPWUID(uid)) != NULL && conf.checkduplicate) @@ -826,10 +879,7 @@ pw_gidpolicy(struct cargs * args, char *nam, gid_t prefer) (grp->gr_mem == NULL || grp->gr_mem[0] == NULL)) { gid = grp->gr_gid; /* Already created? Use it anyway... */ } else { - struct cargs grpargs; - char tmp[32]; - - LIST_INIT(&grpargs); + gid_t grid = -1; /* * We need to auto-create a group with the user's name. We @@ -840,26 +890,15 @@ pw_gidpolicy(struct cargs * args, char *nam, gid_t prefer) * user's name dups an existing group, then the group add * function will happily handle that case for us and exit. */ - if (GETGRGID(prefer) == NULL) { - snprintf(tmp, sizeof(tmp), "%u", prefer); - addarg(&grpargs, 'g', tmp); - } + if (GETGRGID(prefer) == NULL) + grid = prefer; if (conf.dryrun) { - addarg(&grpargs, 'q', NULL); - gid = pw_group(M_NEXT, nam, -1, &grpargs); - } - else - { - pw_group(M_ADD, nam, -1, &grpargs); + gid = pw_groupnext(cnf, true); + } else { + pw_group(M_ADD, nam, grid, NULL); if ((grp = GETGRNAM(nam)) != NULL) gid = grp->gr_gid; } - a_gid = LIST_FIRST(&grpargs); - while (a_gid != NULL) { - struct carg *t = LIST_NEXT(a_gid, list); - LIST_REMOVE(a_gid, list); - a_gid = t; - } } ENDGRENT(); return gid; @@ -989,7 +1028,7 @@ pw_pwcrypt(char *password) static char * -pw_password(struct userconf * cnf, struct cargs * args, char const * user) +pw_password(struct userconf * cnf, char const * user) { int i, l; char pwbuf[32]; @@ -1027,30 +1066,40 @@ pw_password(struct userconf * cnf, struct cargs * args, char const * user) } static int -delete_user(struct userconf *cnf, struct passwd *pwd, char *name, - int delete, int mode) +pw_userdel(char *name, long id) { + struct passwd *pwd = NULL; char file[MAXPATHLEN]; char home[MAXPATHLEN]; - uid_t uid = pwd->pw_uid; + uid_t uid; struct group *gr, *grp; char grname[LOGNAMESIZE]; int rc; struct stat st; + if (id < 0 && name == NULL) + errx(EX_DATAERR, "username or id required"); + + pwd = (name != NULL) ? GETPWNAM(pw_checkname(name, 0)) : GETPWUID(id); + if (pwd == NULL) { + if (name == NULL) + errx(EX_NOUSER, "no such uid `%ld'", id); + errx(EX_NOUSER, "no such user `%s'", name); + } + uid = pwd->pw_uid; + if (name == NULL) + name = pwd->pw_name; + if (strcmp(pwd->pw_name, "root") == 0) errx(EX_DATAERR, "cannot remove user 'root'"); - if (!PWALTDIR()) { - /* - * Remove opie record from /etc/opiekeys - */ + /* Remove opie record from /etc/opiekeys */ + if (PWALTDIR() != PWF_ALT) rmopie(pwd->pw_name); - /* - * Remove crontabs - */ + if (!PWALTDIR()) { + /* Remove crontabs */ snprintf(file, sizeof(file), "/var/cron/tabs/%s", pwd->pw_name); if (access(file, F_OK) == 0) { snprintf(file, sizeof(file), "crontab -u %s -r", pwd->pw_name); @@ -1075,10 +1124,11 @@ delete_user(struct userconf *cnf, struct passwd *pwd, char *name, else if (rc != 0) err(EX_IOERR, "passwd update"); - if (cnf->nispasswd && *cnf->nispasswd=='/') { - rc = delnispwent(cnf->nispasswd, name); + if (conf.userconf->nispasswd && *conf.userconf->nispasswd=='/') { + rc = delnispwent(conf.userconf->nispasswd, name); if (rc == -1) - warnx("WARNING: user '%s' does not exist in NIS passwd", pwd->pw_name); + warnx("WARNING: user '%s' does not exist in NIS passwd", + pwd->pw_name); else if (rc != 0) warn("WARNING: NIS passwd update"); /* non-fatal */ @@ -1108,30 +1158,26 @@ delete_user(struct userconf *cnf, struct passwd *pwd, char *name, } ENDGRENT(); - pw_log(cnf, mode, W_USER, "%s(%u) account removed", name, uid); + pw_log(conf.userconf, M_DELETE, W_USER, "%s(%u) account removed", name, + uid); - if (!PWALTDIR()) { - /* - * Remove mail file - */ - remove(file); + /* Remove mail file */ + if (PWALTDIR() != PWF_ALT) + unlinkat(conf.rootfd, file + 1, 0); - /* - * Remove at jobs - */ - if (getpwuid(uid) == NULL) - rmat(uid); + /* Remove at jobs */ + if (!PWALTDIR() && getpwuid(uid) == NULL) + rmat(uid); - /* - * Remove home directory and contents - */ - if (delete && *home == '/' && getpwuid(uid) == NULL && - stat(home, &st) != -1) { - rm_r(home, uid); - pw_log(cnf, mode, W_USER, "%s(%u) home '%s' %sremoved", - name, uid, home, - stat(home, &st) == -1 ? "" : "not completely "); - } + /* Remove home directory and contents */ + if (PWALTDIR() != PWF_ALT && conf.deletehome && *home == '/' && + getpwuid(uid) == NULL && + fstatat(conf.rootfd, home + 1, &st, 0) != -1) { + rm_r(conf.rootfd, home, uid); + pw_log(conf.userconf, M_DELETE, W_USER, "%s(%u) home '%s' %s" + "removed", name, uid, home, + fstatat(conf.rootfd, home + 1, &st, 0) == -1 ? "" : "not " + "completely "); } return (EXIT_SUCCESS); @@ -1305,27 +1351,29 @@ rmat(uid_t uid) static void rmopie(char const * name) { - static const char etcopie[] = "/etc/opiekeys"; - FILE *fp = fopen(etcopie, "r+"); + char tmp[1014]; + FILE *fp; + int fd; + size_t len; + off_t atofs = 0; + + if ((fd = openat(conf.rootfd, "etc/opiekeys", O_RDWR)) == -1) + return; - if (fp != NULL) { - char tmp[1024]; - off_t atofs = 0; - int length = strlen(name); + fp = fdopen(fd, "r+"); + len = strlen(name); - while (fgets(tmp, sizeof tmp, fp) != NULL) { - if (strncmp(name, tmp, length) == 0 && tmp[length]==' ') { - if (fseek(fp, atofs, SEEK_SET) == 0) { - fwrite("#", 1, 1, fp); /* Comment username out */ - } - break; - } - atofs = ftell(fp); + while (fgets(tmp, sizeof(tmp), fp) != NULL) { + if (strncmp(name, tmp, len) == 0 && tmp[len]==' ') { + /* Comment username out */ + if (fseek(fp, atofs, SEEK_SET) == 0) + fwrite("#", 1, 1, fp); + break; } - /* - * If we got an error of any sort, don't update! - */ - fclose(fp); + atofs = ftell(fp); } + /* + * If we got an error of any sort, don't update! + */ + fclose(fp); } - diff --git a/usr.sbin/pw/pwupd.h b/usr.sbin/pw/pwupd.h index 37303de4e63d..054c5a55293b 100644 --- a/usr.sbin/pw/pwupd.h +++ b/usr.sbin/pw/pwupd.h @@ -36,6 +36,7 @@ #include #include #include +#include #if defined(__FreeBSD__) #define RET_SETGRENT int @@ -58,26 +59,25 @@ struct pwf { }; struct userconf { - int default_password; /* Default password for new users? */ - int reuse_uids; /* Reuse uids? */ - int reuse_gids; /* Reuse gids? */ - char *nispasswd; /* Path to NIS version of the passwd file */ - char *dotdir; /* Where to obtain skeleton files */ - char *newmail; /* Mail to send to new accounts */ - char *logfile; /* Where to log changes */ - char *home; /* Where to create home directory */ - mode_t homemode; /* Home directory permissions */ - char *shelldir; /* Where shells are located */ - char **shells; /* List of shells */ - char *shell_default; /* Default shell */ - char *default_group; /* Default group number */ - char **groups; /* Default (additional) groups */ - char *default_class; /* Default user class */ - uid_t min_uid, max_uid; /* Allowed range of uids */ - gid_t min_gid, max_gid; /* Allowed range of gids */ - int expire_days; /* Days to expiry */ - int password_days; /* Days to password expiry */ - int numgroups; /* (internal) size of default_group array */ + int default_password; /* Default password for new users? */ + int reuse_uids; /* Reuse uids? */ + int reuse_gids; /* Reuse gids? */ + char *nispasswd; /* Path to NIS version of the passwd file */ + char *dotdir; /* Where to obtain skeleton files */ + char *newmail; /* Mail to send to new accounts */ + char *logfile; /* Where to log changes */ + char *home; /* Where to create home directory */ + mode_t homemode; /* Home directory permissions */ + char *shelldir; /* Where shells are located */ + char **shells; /* List of shells */ + char *shell_default; /* Default shell */ + char *default_group; /* Default group number */ + StringList *groups; /* Default (additional) groups */ + char *default_class; /* Default user class */ + uid_t min_uid, max_uid; /* Allowed range of uids */ + gid_t min_gid, max_gid; /* Allowed range of gids */ + int expire_days; /* Days to expiry */ + int password_days; /* Days to password expiry */ }; struct pwconf { @@ -85,12 +85,18 @@ struct pwconf { char etcpath[MAXPATHLEN]; char *newname; char *config; + char *gecos; int fd; + int rootfd; int which; + bool quiet; + bool force; + bool all; bool dryrun; bool pretty; bool v7; bool checkduplicate; + bool deletehome; bool precrypted; struct userconf *userconf; }; @@ -151,9 +157,9 @@ struct group * vgetgrnam(const char * nam); RET_SETGRENT vsetgrent(void); void vendgrent(void); -void copymkdir(char const * dir, char const * skel, mode_t mode, uid_t uid, gid_t gid); -void rm_r(char const * dir, uid_t uid); -int extendarray(char ***buf, int *buflen, int needed); +void copymkdir(int rootfd, char const * dir, int skelfd, mode_t mode, uid_t uid, + gid_t gid, int flags); +void rm_r(int rootfd, char const * dir, uid_t uid); __END_DECLS #endif /* !_PWUPD_H */ diff --git a/usr.sbin/pw/rm_r.c b/usr.sbin/pw/rm_r.c index 797ca9de8827..65a63e6e0cbe 100644 --- a/usr.sbin/pw/rm_r.c +++ b/usr.sbin/pw/rm_r.c @@ -37,39 +37,37 @@ static const char rcsid[] = #include #include #include +#include #include "pwupd.h" void -rm_r(char const * dir, uid_t uid) +rm_r(int rootfd, const char *path, uid_t uid) { - DIR *d = opendir(dir); + int dirfd; + DIR *d; + struct dirent *e; + struct stat st; - if (d != NULL) { - struct dirent *e; - struct stat st; - char file[MAXPATHLEN]; + if (*path == '/') + path++; - while ((e = readdir(d)) != NULL) { - if (strcmp(e->d_name, ".") != 0 && strcmp(e->d_name, "..") != 0) { - snprintf(file, sizeof(file), "%s/%s", dir, e->d_name); - if (lstat(file, &st) == 0) { /* Need symlinks, not - * linked file */ - if (S_ISDIR(st.st_mode)) /* Directory - recurse */ - rm_r(file, uid); - else { - if (S_ISLNK(st.st_mode) || st.st_uid == uid) - remove(file); - } - } - } - } - closedir(d); - if (lstat(dir, &st) == 0) { - if (S_ISLNK(st.st_mode)) - remove(dir); - else if (st.st_uid == uid) - rmdir(dir); - } + dirfd = openat(rootfd, path, O_DIRECTORY); + + d = fdopendir(dirfd); + while ((e = readdir(d)) != NULL) { + if (strcmp(e->d_name, ".") == 0 || strcmp(e->d_name, "..") == 0) + continue; + + if (fstatat(dirfd, e->d_name, &st, AT_SYMLINK_NOFOLLOW) != 0) + continue; + if (S_ISDIR(st.st_mode)) + rm_r(dirfd, e->d_name, uid); + else if (S_ISLNK(st.st_mode) || st.st_uid == uid) + unlinkat(dirfd, e->d_name, 0); } + closedir(d); + if (fstatat(rootfd, path, &st, AT_SYMLINK_NOFOLLOW) != 0) + return; + unlinkat(rootfd, path, S_ISDIR(st.st_mode) ? AT_REMOVEDIR : 0); } diff --git a/usr.sbin/pw/tests/helper_functions.shin b/usr.sbin/pw/tests/helper_functions.shin index 3680dfe608eb..1ee731a786ef 100755 --- a/usr.sbin/pw/tests/helper_functions.shin +++ b/usr.sbin/pw/tests/helper_functions.shin @@ -2,11 +2,12 @@ # The pw command PW="pw -V ${HOME}" +RPW="pw -R ${HOME}" # Workdir to run tests in TESTDIR=$(atf_get_srcdir) -# Populate the files pw needs to use into $HOME/etc +# Populate the files pw needs to use into $HOME populate_etc_skel() { cp ${TESTDIR}/master.passwd ${HOME} || \ atf_fail "Populating master.passwd in ${HOME}" @@ -16,3 +17,16 @@ populate_etc_skel() { pwd_mkdb -p -d ${HOME} ${HOME}/master.passwd || \ atf_fail "generate passwd from master.passwd" } + +# Populate the files pw needs to use into $HOME/etc +populate_root_etc_skel() { + mkdir ${HOME}/etc + cp ${TESTDIR}/master.passwd ${HOME}/etc || \ + atf_fail "Populating master.passwd in ${HOME}/etc" + cp ${TESTDIR}/group ${HOME}/etc || \ + atf_fail "Populating group in ${HOME}/etc" + + # Generate the passwd file + pwd_mkdb -p -d ${HOME}/etc ${HOME}//etc/master.passwd || \ + atf_fail "generate passwd from master.passwd" +} diff --git a/usr.sbin/pw/tests/pw_groupmod.sh b/usr.sbin/pw/tests/pw_groupmod.sh index 9ea8a6d6c9dd..580692553847 100755 --- a/usr.sbin/pw/tests/pw_groupmod.sh +++ b/usr.sbin/pw/tests/pw_groupmod.sh @@ -81,6 +81,32 @@ groupmod_rename_body() { grep "^bar:.*" ${HOME}/group } +atf_test_case groupmod_members +groupmod_members_body() { + populate_etc_skel + + for i in user1 user2 user3 user4; do + atf_check -s exit:0 ${PW} useradd $i + done + + atf_check -s exit:0 ${PW} groupadd foo -M "user1, user2" + atf_check -o inline:"foo:*:1005:user1,user2\n" -s exit:0 \ + ${PW} groupshow foo + atf_check -s exit:0 ${PW} groupmod foo -m "user3, user4" + atf_check -o inline:"foo:*:1005:user1,user2,user3,user4\n" -s exit:0 \ + ${PW} groupshow foo + atf_check -s exit:0 ${PW} groupmod foo -M "user1, user4" + atf_check -o inline:"foo:*:1005:user1,user4\n" -s exit:0 \ + ${PW} groupshow foo + # what about duplicates + atf_check -s exit:0 ${PW} groupmod foo -m "user1, user2, user3, user4" + atf_check -o inline:"foo:*:1005:user1,user4,user2,user3\n" -s exit:0 \ + ${PW} groupshow foo + atf_check -s exit:0 ${PW} groupmod foo -d "user1, user3" + atf_check -o inline:"foo:*:1005:user4,user2\n" -s exit:0 \ + ${PW} groupshow foo +} + atf_init_test_cases() { atf_add_test_case groupmod_user atf_add_test_case groupmod_invalid_user @@ -88,4 +114,5 @@ atf_init_test_cases() { atf_add_test_case usermod_bug_185666 atf_add_test_case do_not_duplicate_group_on_gid_change atf_add_test_case groupmod_rename + atf_add_test_case groupmod_members } diff --git a/usr.sbin/pw/tests/pw_useradd.sh b/usr.sbin/pw/tests/pw_useradd.sh index 469c1e5cde52..880dab5ca7bb 100755 --- a/usr.sbin/pw/tests/pw_useradd.sh +++ b/usr.sbin/pw/tests/pw_useradd.sh @@ -240,6 +240,55 @@ user_add_password_from_h_body() { EOF } +atf_test_case user_add_R +user_add_R_body() { + populate_root_etc_skel + + atf_check -s exit:0 ${RPW} useradd foo + mkdir -p ${HOME}/home + atf_check -s exit:0 ${RPW} useradd bar -m + test -d ${HOME}/home/bar || atf_fail "Directory not created" + atf_check -s exit:0 ${RPW} userdel bar + test -d ${HOME}/home/bar || atf_fail "Directory removed" +# atf_check -s exit:0 ${RPW} useradd bar +# atf_check -s exit:0 ${RPW} userdel bar -r +# test -d ${HOME}/home/bar && atf_fail "Directory not removed" +} + +atf_test_case user_add_skel +user_add_skel_body() { + populate_root_etc_skel + + mkdir ${HOME}/skel + echo "a" > ${HOME}/skel/.a + echo "b" > ${HOME}/skel/b + mkdir ${HOME}/skel/c + mkdir ${HOME}/skel/c/d + mkdir ${HOME}/skel/dot.plop + echo "c" > ${HOME}/skel/c/d/dot.c + mkdir ${HOME}/home + ln -sf /nonexistent ${HOME}/skel/c/foo + atf_check -s exit:0 ${RPW} useradd foo -k /skel -m + test -d ${HOME}/home/foo || atf_fail "Directory not created" + test -f ${HOME}/home/foo/.a || atf_fail "File not created" + atf_check -o file:${HOME}/skel/.a -s exit:0 cat ${HOME}/home/foo/.a + atf_check -o file:${HOME}/skel/b -s exit:0 cat ${HOME}/home/foo/b + test -d ${HOME}/home/foo/c || atf_fail "Dotted directory in skel not copied" + test -d ${HOME}/home/foo/.plop || atf_fail "Directory in skell not created" + atf_check -o inline:"/nonexistent\n" -s ignore readlink -f ${HOME}/home/foo/c/foo + atf_check -o file:${HOME}/skel/c/d/dot.c -s exit:0 cat ${HOME}/home/foo/c/d/.c +} + +atf_test_case user_add_uid0 +user_add_uid0_body() { + populate_etc_skel + atf_check -e inline:"pw: WARNING: new account \`foo' has a uid of 0 (superuser access!)\n" \ + -s exit:0 ${PW} useradd foo -u 0 -g 0 -d /root -s /bin/sh -c "Bourne-again Superuser" -o + atf_check \ + -o inline:"foo:*:0:0::0:0:Bourne-again Superuser:/root:/bin/sh\n" \ + -s exit:0 ${PW} usershow foo +} + atf_init_test_cases() { atf_add_test_case user_add atf_add_test_case user_add_noupdate @@ -261,4 +310,7 @@ atf_init_test_cases() { atf_add_test_case user_add_invalid_user_entry atf_add_test_case user_add_invalid_group_entry atf_add_test_case user_add_password_from_h + atf_add_test_case user_add_R + atf_add_test_case user_add_skel + atf_add_test_case user_add_uid0 } diff --git a/usr.sbin/pw/tests/pw_userdel.sh b/usr.sbin/pw/tests/pw_userdel.sh index 71a7033d36b2..5ba87c258dea 100755 --- a/usr.sbin/pw/tests/pw_userdel.sh +++ b/usr.sbin/pw/tests/pw_userdel.sh @@ -31,7 +31,27 @@ user_do_not_try_to_delete_root_if_user_unknown_body() { ${PW} userdel -u plop } +atf_test_case delete_files +delete_files_body() { + populate_root_etc_skel + + mkdir -p ${HOME}/skel + touch ${HOME}/skel/a + mkdir -p ${HOME}/home + mkdir -p ${HOME}/var/mail + echo "foo wedontcare" > ${HOME}/etc/opiekeys + atf_check -s exit:0 ${RPW} useradd foo -k /skel -m + test -d ${HOME}/home || atf_fail "Fail to create home directory" + test -f ${HOME}/var/mail/foo || atf_fail "Mail file not created" + atf_check -s exit:0 ${RPW} userdel foo -r + atf_check -s exit:0 -o inline:"#oo wedontcare\n" cat ${HOME}/etc/opiekeys + if test -f ${HOME}/var/mail/foo; then + atf_fail "Mail file not removed" + fi +} + atf_init_test_cases() { atf_add_test_case rmuser_seperate_group atf_add_test_case user_do_not_try_to_delete_root_if_user_unknown + atf_add_test_case delete_files } diff --git a/usr.sbin/uefisign/uefisign.8 b/usr.sbin/uefisign/uefisign.8 index 0bda8c924236..5ef79d927735 100644 --- a/usr.sbin/uefisign/uefisign.8 +++ b/usr.sbin/uefisign/uefisign.8 @@ -27,7 +27,7 @@ .\" .\" $FreeBSD$ .\" -.Dd December 10, 2014 +.Dd July 11, 2015 .Dt UEFISIGN 8 .Os .Sh NAME @@ -84,7 +84,7 @@ View signature: The .Nm command appeared in -.Fx 11.0 . +.Fx 10.2 . .Sh AUTHORS The .Nm diff --git a/usr.sbin/ypbind/ypbind.c b/usr.sbin/ypbind/ypbind.c index 700365f55755..7d18d22c7347 100644 --- a/usr.sbin/ypbind/ypbind.c +++ b/usr.sbin/ypbind/ypbind.c @@ -106,16 +106,16 @@ void terminate(int); void yp_restricted_mode(char *); int verify(struct in_addr); -char *domain_name; -struct _dom_binding *ypbindlist; +static char *domain_name; +static struct _dom_binding *ypbindlist; static struct _dom_binding *broad_domain; #define YPSET_NO 0 #define YPSET_LOCAL 1 #define YPSET_ALL 2 -int ypsetmode = YPSET_NO; -int ypsecuremode = 0; -int ppid; +static int ypsetmode = YPSET_NO; +static int ypsecuremode = 0; +static int ppid; #define NOT_RESPONDING_HYSTERESIS 10 static int not_responding_count = 0; @@ -126,9 +126,9 @@ static int not_responding_count = 0; * in restricted_addrs will be used for binding. */ #define RESTRICTED_SERVERS 10 -int yp_restricted = 0; -int yp_manycast = 0; -struct in_addr restricted_addrs[RESTRICTED_SERVERS]; +static int yp_restricted = 0; +static int yp_manycast = 0; +static struct in_addr restricted_addrs[RESTRICTED_SERVERS]; /* No more than MAX_CHILDREN child broadcasters at a time. */ #ifndef MAX_CHILDREN @@ -148,13 +148,13 @@ struct in_addr restricted_addrs[RESTRICTED_SERVERS]; #define MAX_RETRIES 30 #endif -int retries = 0; -int children = 0; -int domains = 0; -int yplockfd; -fd_set fdsr; +static int retries = 0; +static int children = 0; +static int domains = 0; +static int yplockfd; +static fd_set fdsr; -SVCXPRT *udptransp, *tcptransp; +static SVCXPRT *udptransp, *tcptransp; void * ypbindproc_null_2_yp(SVCXPRT *transp, void *argp, CLIENT *clnt) @@ -165,7 +165,7 @@ ypbindproc_null_2_yp(SVCXPRT *transp, void *argp, CLIENT *clnt) return &res; } -struct ypbind_resp * +static struct ypbind_resp * ypbindproc_domain_2_yp(SVCXPRT *transp, domainname *argp, CLIENT *clnt) { static struct ypbind_resp res; @@ -225,10 +225,10 @@ rejecting.", *argp); res.ypbind_status = YPBIND_SUCC_VAL; res.ypbind_resp_u.ypbind_error = 0; /* Success */ - *(u_int32_t *)&res.ypbind_resp_u.ypbind_bindinfo.ypbind_binding_addr = - ypdb->dom_server_addr.sin_addr.s_addr; - *(u_short *)&res.ypbind_resp_u.ypbind_bindinfo.ypbind_binding_port = - ypdb->dom_server_addr.sin_port; + memcpy(&res.ypbind_resp_u.ypbind_bindinfo.ypbind_binding_addr, + &ypdb->dom_server_addr.sin_addr.s_addr, sizeof(u_int32_t)); + memcpy(&res.ypbind_resp_u.ypbind_bindinfo.ypbind_binding_port, + &ypdb->dom_server_addr.sin_port, sizeof(u_short)); /*printf("domain %s at %s/%d\n", ypdb->dom_domain, inet_ntoa(ypdb->dom_server_addr.sin_addr), ntohs(ypdb->dom_server_addr.sin_port));*/ @@ -275,8 +275,12 @@ rejecting.", argp->ypsetdom_domain); bzero(&bindsin, sizeof bindsin); bindsin.sin_family = AF_INET; - bindsin.sin_addr.s_addr = *(u_int32_t *)argp->ypsetdom_binding.ypbind_binding_addr; - bindsin.sin_port = *(u_short *)argp->ypsetdom_binding.ypbind_binding_port; + memcpy(&bindsin.sin_addr.s_addr, + &argp->ypsetdom_binding.ypbind_binding_addr, + sizeof(u_int32_t)); + memcpy(&bindsin.sin_port, + &argp->ypsetdom_binding.ypbind_binding_port, + sizeof(u_short)); rpc_received(argp->ypsetdom_domain, &bindsin, 1); return((void *) &result); @@ -615,9 +619,8 @@ tell_parent(char *dom, struct sockaddr_in *addr) return (0); } -bool_t broadcast_result(out, addr) -bool_t *out; -struct sockaddr_in *addr; +static bool_t +broadcast_result(bool_t *out, struct sockaddr_in *addr) { if (retries >= MAX_RETRIES) { bzero(addr, sizeof(struct sockaddr_in)); @@ -945,8 +948,10 @@ rpc_received(char *dom, struct sockaddr_in *raddrp, int force) bzero(&ybr, sizeof ybr); ybr.ypbind_status = YPBIND_SUCC_VAL; - *(u_int32_t *)&ybr.ypbind_resp_u.ypbind_bindinfo.ypbind_binding_addr = raddrp->sin_addr.s_addr; - *(u_short *)&ybr.ypbind_resp_u.ypbind_bindinfo.ypbind_binding_port = raddrp->sin_port; + memcpy(&ybr.ypbind_resp_u.ypbind_bindinfo.ypbind_binding_addr, + &raddrp->sin_addr.s_addr, sizeof(u_int32_t)); + memcpy(&ybr.ypbind_resp_u.ypbind_bindinfo.ypbind_binding_port, + &raddrp->sin_port, sizeof(u_short)); if (writev(ypdb->dom_lockfd, iov, 2) != iov[0].iov_len + iov[1].iov_len) { syslog(LOG_WARNING, "write: %m");