Turn on NAP mode on G5 systems, and refactor the HID0 setup code a little.
This makes my G5 Xserve sound slightly less like it is filled with howling banshees.
This commit is contained in:
Nathan Whitehorn
parent
37a7f59644
commit
570d2b25a6
@ -41,6 +41,7 @@
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#define HID0_ECLK 0x02000000 /* CLK_OUT clock type selection */
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#define HID0_PAR 0x01000000 /* Disable precharge of ARTRY */
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#define HID0_STEN 0x01000000 /* Software table search enable (7450) */
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#define HID0_DEEPNAP 0x01000000 /* Enable deep nap mode (970) */
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#define HID0_HBATEN 0x00800000 /* High BAT enable (74[45][578]) */
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#define HID0_DOZE 0x00800000 /* Enable doze mode */
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#define HID0_NAP 0x00400000 /* Enable nap mode */
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@ -98,6 +99,12 @@
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"\020b16\017TBEN\016SEL_TBCLK\015b19\014b20\013b21\012b22\011b23" \
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"\010EN_MAS7_UPDATE\007DCFA\006b26\005b27\004b28\003b29\002b30\001NOPTI"
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#define HID0_970_BITMASK \
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"\20" \
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"\040ONEPPC\037SINGLE\036ISYNCSC\035SERGP\031DEEPNAP\030DOZE" \
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"\027NAP\025DPM\023TG\022HANGDETECT\021NHR\020INORDER" \
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"\016TBCTRL\015TBEN\012CIABREN\011HDICEEN\001ENATTN"
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/*
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* HID0 bit definitions per cpu model
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*
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@ -114,16 +114,19 @@ static char model[64];
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SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, model, 0, "");
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static void cpu_print_speed(void);
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static void cpu_print_cacheinfo(u_int, uint16_t);
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static void cpu_6xx_setup(int cpuid, uint16_t vers);
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static void cpu_6xx_print_cacheinfo(u_int, uint16_t);
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static void cpu_e500_setup(int cpuid, uint16_t vers);
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static void cpu_970_setup(int cpuid, uint16_t vers);
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void
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cpu_setup(u_int cpuid)
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{
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u_int pvr, maj, min, hid0;
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u_int pvr, maj, min;
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uint16_t vers, rev, revfmt;
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const struct cputab *cp;
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const char *name;
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char *bitmask;
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pvr = mfpvr();
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vers = pvr >> 16;
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@ -170,10 +173,8 @@ cpu_setup(u_int cpuid)
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break;
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}
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hid0 = mfspr(SPR_HID0);
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/*
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* Configure power-saving mode.
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* Configure CPU
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*/
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switch (vers) {
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case MPC603:
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@ -184,102 +185,34 @@ cpu_setup(u_int cpuid)
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case IBM750FX:
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case MPC7400:
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case MPC7410:
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case MPC7447A:
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case MPC7448:
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case MPC7450:
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case MPC7455:
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case MPC7457:
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case MPC8240:
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case MPC8245:
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/* Select DOZE mode. */
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hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
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hid0 |= HID0_DOZE | HID0_DPM;
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powerpc_pow_enabled = 1;
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cpu_6xx_setup(cpuid, vers);
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break;
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case MPC7448:
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case MPC7447A:
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case MPC7457:
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case MPC7455:
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case MPC7450:
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/* Enable the 7450 branch caches */
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hid0 |= HID0_SGE | HID0_BTIC;
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hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT;
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/* Disable BTIC on 7450 Rev 2.0 or earlier and on 7457 */
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if (((pvr >> 16) == MPC7450 && (pvr & 0xFFFF) <= 0x0200)
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|| (pvr >> 16) == MPC7457)
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hid0 &= ~HID0_BTIC;
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/* Select NAP mode. */
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hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
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hid0 |= HID0_NAP | HID0_DPM;
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powerpc_pow_enabled = 1;
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break;
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default:
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/* No power-saving mode is available. */ ;
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}
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switch (vers) {
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case IBM750FX:
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case MPC750:
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hid0 &= ~HID0_DBP; /* XXX correct? */
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hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
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break;
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case MPC7400:
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case MPC7410:
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hid0 &= ~HID0_SPD;
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hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
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hid0 |= HID0_EIEC;
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break;
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case FSL_E500v1:
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case FSL_E500v2:
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break;
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}
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mtspr(SPR_HID0, hid0);
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switch (vers) {
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case MPC7447A:
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case MPC7448:
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case MPC7450:
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case MPC7455:
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case MPC7457:
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bitmask = HID0_7450_BITMASK;
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break;
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case FSL_E500v1:
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case FSL_E500v2:
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bitmask = HID0_E500_BITMASK;
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break;
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default:
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bitmask = HID0_BITMASK;
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break;
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}
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switch (vers) {
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case MPC7450:
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case MPC7455:
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case MPC7457:
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case MPC750:
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case IBM750FX:
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case MPC7400:
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case MPC7410:
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case MPC7447A:
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case MPC7448:
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cpu_print_speed();
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printf("\n");
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if (bootverbose)
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cpu_print_cacheinfo(cpuid, vers);
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break;
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case IBM970:
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case IBM970FX:
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case IBM970GX:
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case IBM970MP:
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cpu_print_speed();
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printf("\n");
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cpu_970_setup(cpuid, vers);
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break;
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case FSL_E500v1:
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case FSL_E500v2:
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cpu_e500_setup(cpuid, vers);
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break;
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default:
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printf("\n");
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/* HID setup is unknown */
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break;
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}
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printf("cpu%d: HID0 %b\n", cpuid, hid0, bitmask);
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printf("\n");
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}
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void
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@ -346,10 +279,101 @@ cpu_est_clockrate(int cpu_id, uint64_t *cps)
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}
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void
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cpu_print_cacheinfo(u_int cpuid, uint16_t vers)
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cpu_6xx_setup(int cpuid, uint16_t vers)
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{
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uint32_t hid;
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register_t hid0, pvr;
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const char *bitmask;
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hid0 = mfspr(SPR_HID0);
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pvr = mfpvr();
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/*
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* Configure power-saving mode.
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*/
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switch (vers) {
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case MPC603:
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case MPC603e:
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case MPC603ev:
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case MPC604ev:
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case MPC750:
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case IBM750FX:
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case MPC7400:
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case MPC7410:
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case MPC8240:
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case MPC8245:
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/* Select DOZE mode. */
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hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
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hid0 |= HID0_DOZE | HID0_DPM;
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powerpc_pow_enabled = 1;
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break;
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case MPC7448:
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case MPC7447A:
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case MPC7457:
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case MPC7455:
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case MPC7450:
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/* Enable the 7450 branch caches */
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hid0 |= HID0_SGE | HID0_BTIC;
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hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT;
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/* Disable BTIC on 7450 Rev 2.0 or earlier and on 7457 */
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if (((pvr >> 16) == MPC7450 && (pvr & 0xFFFF) <= 0x0200)
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|| (pvr >> 16) == MPC7457)
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hid0 &= ~HID0_BTIC;
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/* Select NAP mode. */
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hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
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hid0 |= HID0_NAP | HID0_DPM;
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powerpc_pow_enabled = 1;
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break;
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default:
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/* No power-saving mode is available. */ ;
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}
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switch (vers) {
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case IBM750FX:
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case MPC750:
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hid0 &= ~HID0_DBP; /* XXX correct? */
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hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
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break;
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case MPC7400:
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case MPC7410:
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hid0 &= ~HID0_SPD;
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hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
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hid0 |= HID0_EIEC;
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break;
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}
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mtspr(SPR_HID0, hid0);
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cpu_print_speed();
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printf("\n");
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if (bootverbose)
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cpu_6xx_print_cacheinfo(cpuid, vers);
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switch (vers) {
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case MPC7447A:
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case MPC7448:
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case MPC7450:
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case MPC7455:
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case MPC7457:
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bitmask = HID0_7450_BITMASK;
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break;
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default:
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bitmask = HID0_BITMASK;
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break;
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}
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printf("cpu%d: HID0 %b", cpuid, (int)hid0, bitmask);
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}
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static void
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cpu_6xx_print_cacheinfo(u_int cpuid, uint16_t vers)
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{
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register_t hid;
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hid = mfspr(SPR_HID0);
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printf("cpu%u: ", cpuid);
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@ -395,3 +419,43 @@ cpu_print_cacheinfo(u_int cpuid, uint16_t vers)
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} else
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printf("L2 cache disabled\n");
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}
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static void
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cpu_e500_setup(int cpuid, uint16_t vers)
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{
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register_t hid0;
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hid0 = mfspr(SPR_HID0);
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printf("cpu%d: HID0 %b", cpuid, (int)hid0, HID0_E500_BITMASK);
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}
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static void
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cpu_970_setup(int cpuid, uint16_t vers)
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{
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uint32_t hid0_hi, hid0_lo;
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__asm __volatile ("mfspr %0,%2; clrldi %1,%0,32; srdi %0,%0,32;"
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: "=r" (hid0_hi), "=r" (hid0_lo) : "K" (SPR_HID0));
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/* Configure power-saving mode */
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hid0_hi |= (HID0_NAP | HID0_DPM);
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hid0_hi &= ~(HID0_DOZE | HID0_DEEPNAP);
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powerpc_pow_enabled = 1;
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__asm __volatile (" \
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sync; isync; \
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sldi %0,%0,32; or %0,%0,%1; \
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mtspr %2, %0; \
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mfspr %0, %2; mfspr %0, %2; mfspr %0, %2; \
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mfspr %0, %2; mfspr %0, %2; mfspr %0, %2; \
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sync; isync"
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:: "r" (hid0_hi), "r"(hid0_lo), "K" (SPR_HID0));
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cpu_print_speed();
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printf("\n");
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__asm __volatile ("mfspr %0,%1; srdi %0,%0,32;"
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: "=r" (hid0_hi) : "K" (SPR_HID0));
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printf("cpu%d: HID0 %b", cpuid, (int)(hid0_hi), HID0_970_BITMASK);
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}
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