d/freebsd-skq
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Disable branch-target instruction cache on MPC7457 as outlined

Browse Source 
in Motorola processor errata.

Submitted by:  Suleiman Souhlal <refugee@segfaulted.com>
This commit is contained in:
grehan 2004-02-09 07:04:01 +00:00
parent c2a792a65d
commit 5715cbfdf1
1 changed files with 3 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
sys/powerpc/powerpc/cpu.c
View File

@ -177,8 +177,9 @@ cpu_setup(u_int cpuid)
case MPC7457: case MPC7457:
case MPC7455: case MPC7455:
case MPC7450: case MPC7450:
/* Disable BTIC on 7450 Rev 2.0 or earlier */ /* Disable BTIC on 7450 Rev 2.0 or earlier and on 7457 */
if ((pvr >> 16) == MPC7450 && (pvr & 0xFFFF) <= 0x0200) if (((pvr >> 16) == MPC7450 && (pvr & 0xFFFF) <= 0x0200)
|| (pvr >> 16) == MPC7457)
hid0 &= ~HID0_BTIC; hid0 &= ~HID0_BTIC;
/* Select NAP mode. */ /* Select NAP mode. */
hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);