mips: fix build w/ TICK_USE_MALTA_RTC defined
This was mainly broken by 7e82012aff
and
r178192 respectively.
Also, remove unused #include.
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parent
7d7fad7bd9
commit
5731987b71
@ -73,8 +73,7 @@ __FBSDID("$FreeBSD$");
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#endif
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#ifdef TICK_USE_MALTA_RTC
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#include <mips/mips4k/malta/maltareg.h>
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#include <dev/mc146818/mc146818reg.h>
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#include <mips/malta/maltareg.h>
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#include <isa/rtc.h>
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#endif
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@ -157,7 +156,7 @@ lcd_puts(char *s)
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#ifdef TICK_USE_MALTA_RTC
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static __inline uint8_t
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rtcin(uint8_t addr)
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malta_rtcin(uint8_t addr)
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{
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*((volatile uint8_t *)
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@ -167,7 +166,7 @@ rtcin(uint8_t addr)
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}
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static __inline void
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writertc(uint8_t addr, uint8_t val)
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malta_writertc(uint8_t addr, uint8_t val)
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{
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*((volatile uint8_t *)
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@ -257,19 +256,19 @@ malta_cpu_freq(void)
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u_int64_t counterval[2];
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/* Set RTC to binary mode. */
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writertc(RTC_STATUSB, (rtcin(RTC_STATUSB) | RTCSB_BCD));
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malta_writertc(RTC_STATUSB, (malta_rtcin(RTC_STATUSB) | RTCSB_BCD));
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/* Busy-wait for falling edge of RTC update. */
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while (((rtcin(RTC_STATUSA) & RTCSA_TUP) == 0))
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while (((malta_rtcin(RTC_STATUSA) & RTCSA_TUP) == 0))
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;
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while (((rtcin(RTC_STATUSA)& RTCSA_TUP) != 0))
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while (((malta_rtcin(RTC_STATUSA)& RTCSA_TUP) != 0))
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;
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counterval[0] = mips_rd_count();
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/* Busy-wait for falling edge of RTC update. */
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while (((rtcin(RTC_STATUSA) & RTCSA_TUP) == 0))
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while (((malta_rtcin(RTC_STATUSA) & RTCSA_TUP) == 0))
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;
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while (((rtcin(RTC_STATUSA)& RTCSA_TUP) != 0))
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while (((malta_rtcin(RTC_STATUSA)& RTCSA_TUP) != 0))
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;
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counterval[1] = mips_rd_count();
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