Fix inconsistencies in the comments.
MFC after: 1 week
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575a30d883
@ -803,7 +803,7 @@ cpu_setregs(void)
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* Initialize segments & interrupt table
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*/
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struct user_segment_descriptor gdt[NGDT * MAXCPU];/* global descriptor table */
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struct user_segment_descriptor gdt[NGDT * MAXCPU];/* global descriptor tables */
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static struct gate_descriptor idt0[NIDT];
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struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */
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@ -870,7 +870,7 @@ struct soft_segment_descriptor gdt_segs[] = {
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/* GPROC0_SEL 6 Proc 0 Tss Descriptor */
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{
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0x0, /* segment base address */
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sizeof(struct amd64tss)-1,/* length - all address space */
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sizeof(struct amd64tss)-1,/* length */
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SDT_SYSTSS, /* segment type */
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SEL_KPL, /* segment descriptor priority level */
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1, /* segment descriptor present */
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@ -201,7 +201,7 @@ struct region_descriptor {
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#define GUDATA_SEL 4 /* User 32/64 bit Data Descriptor */
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#define GUCODE_SEL 5 /* User 64 bit Code Descriptor */
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#define GPROC0_SEL 6 /* TSS for entering kernel etc */
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/* slot 6 is second half of GPROC0_SEL */
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/* slot 7 is second half of GPROC0_SEL */
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#define GUGS32_SEL 8 /* User 32 bit GS Descriptor */
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#define NGDT 9
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