From 57ae6edf31f64b06d8d6dae2163a5687a019f043 Mon Sep 17 00:00:00 2001 From: Aleksandr Rybalko Date: Fri, 28 Jun 2013 22:31:17 +0000 Subject: [PATCH] Add identification for Cortex-A15 (R0) cores. Submitted by: Ruslan Bukin --- sys/arm/arm/cpufunc.c | 3 ++- sys/arm/arm/identcpu.c | 2 ++ sys/arm/include/armreg.h | 1 + 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/sys/arm/arm/cpufunc.c b/sys/arm/arm/cpufunc.c index f2359518850c..4d9889e3af43 100644 --- a/sys/arm/arm/cpufunc.c +++ b/sys/arm/arm/cpufunc.c @@ -1481,7 +1481,8 @@ set_cpufuncs() cputype == CPU_ID_CORTEXA8R3 || cputype == CPU_ID_CORTEXA9R1 || cputype == CPU_ID_CORTEXA9R2 || - cputype == CPU_ID_CORTEXA9R3) { + cputype == CPU_ID_CORTEXA9R3 || + cputype == CPU_ID_CORTEXA15 ) { cpufuncs = cortexa_cpufuncs; cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */ get_cachetype_cp15(); diff --git a/sys/arm/arm/identcpu.c b/sys/arm/arm/identcpu.c index 414396a9e468..33cfa1e1fa44 100644 --- a/sys/arm/arm/identcpu.c +++ b/sys/arm/arm/identcpu.c @@ -248,6 +248,8 @@ const struct cpuidtab cpuids[] = { generic_steppings }, { CPU_ID_CORTEXA9R3, CPU_CLASS_CORTEXA, "Cortex A9-r3", generic_steppings }, + { CPU_ID_CORTEXA15, CPU_CLASS_CORTEXA, "Cortex A15", + generic_steppings }, { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110", sa110_steppings }, diff --git a/sys/arm/include/armreg.h b/sys/arm/include/armreg.h index 1f54f91d809f..049d140110ef 100644 --- a/sys/arm/include/armreg.h +++ b/sys/arm/include/armreg.h @@ -153,6 +153,7 @@ #define CPU_ID_CORTEXA9R1 0x411fc090 #define CPU_ID_CORTEXA9R2 0x412fc090 #define CPU_ID_CORTEXA9R3 0x413fc090 +#define CPU_ID_CORTEXA15 0x410fc0f0 #define CPU_ID_SA110 0x4401a100 #define CPU_ID_SA1100 0x4401a110 #define CPU_ID_TI925T 0x54029250