aw_sid: Add nvmem interface
Rework aw_sid so it can work with the nvmem interface. Each SoC expose a set of fuses (for now rootkey/boardid and, if available, the thermal calibration data). A fuse can be private or public, reading private fuse needs to be done via some registers instead of reading directly. Each fuse is exposed as a sysctl. For now leave the possibility for a driver to read any fuse without using the nvmem interface as the awg and emac driver use this to generate a mac address.
This commit is contained in:
manu
parent
beb0f2d23d
commit
5836e9a6b2
@ -50,7 +50,12 @@ __FBSDID("$FreeBSD$");
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#include <arm/allwinner/aw_sid.h>
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/* efuse registers */
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#include "nvmem_if.h"
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/*
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* Starting at least from sun8iw6 (A83T) EFUSE starts at 0x200
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* There is 3 registers in the low area to read/write protected EFUSE.
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*/
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#define SID_PRCTL 0x40
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#define SID_PRCTL_OFFSET_MASK 0xff
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#define SID_PRCTL_OFFSET(n) (((n) & SID_PRCTL_OFFSET_MASK) << 16)
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@ -60,53 +65,148 @@ __FBSDID("$FreeBSD$");
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#define SID_PRKEY 0x50
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#define SID_RDKEY 0x60
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#define SID_SRAM 0x200
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/* Offsets into efuse space, for convenience */
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#define SID_THERMAL_CALIB0_OFF (0x34)
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#define SID_THERMAL_CALIB1_OFF (0x38)
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#define SID_THERMAL_CALIB0 (SID_SRAM + SID_THERMAL_CALIB0_OFF)
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#define SID_THERMAL_CALIB1 (SID_SRAM + SID_THERMAL_CALIB1_OFF)
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#define EFUSE_OFFSET 0x200
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#define EFUSE_NAME_SIZE 32
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#define EFUSE_DESC_SIZE 64
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#define ROOT_KEY_SIZE 4
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struct aw_sid_efuse {
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char name[EFUSE_NAME_SIZE];
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char desc[EFUSE_DESC_SIZE];
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bus_size_t base;
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bus_size_t offset;
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uint32_t size;
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enum aw_sid_fuse_id id;
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bool public;
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};
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static struct aw_sid_efuse a10_efuses[] = {
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{
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.name = "rootkey",
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.desc = "Root Key or ChipID",
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.offset = 0x0,
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.size = 16,
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.id = AW_SID_FUSE_ROOTKEY,
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.public = true,
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},
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};
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static struct aw_sid_efuse a64_efuses[] = {
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{
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.name = "rootkey",
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.desc = "Root Key or ChipID",
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.base = EFUSE_OFFSET,
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.offset = 0x00,
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.size = 16,
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.id = AW_SID_FUSE_ROOTKEY,
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.public = true,
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},
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{
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.name = "ths-calib",
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.desc = "Thermal Sensor Calibration Data",
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.base = EFUSE_OFFSET,
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.offset = 0x34,
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.size = 6,
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.id = AW_SID_FUSE_THSSENSOR,
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.public = true,
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},
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};
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static struct aw_sid_efuse a83t_efuses[] = {
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{
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.name = "rootkey",
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.desc = "Root Key or ChipID",
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.base = EFUSE_OFFSET,
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.offset = 0x00,
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.size = 16,
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.id = AW_SID_FUSE_ROOTKEY,
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.public = true,
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},
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{
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.name = "ths-calib",
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.desc = "Thermal Sensor Calibration Data",
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.base = EFUSE_OFFSET,
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.offset = 0x34,
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.size = 8,
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.id = AW_SID_FUSE_THSSENSOR,
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.public = true,
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},
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};
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static struct aw_sid_efuse h3_efuses[] = {
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{
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.name = "rootkey",
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.desc = "Root Key or ChipID",
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.base = EFUSE_OFFSET,
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.offset = 0x00,
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.size = 16,
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.id = AW_SID_FUSE_ROOTKEY,
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.public = true,
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},
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{
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.name = "ths-calib",
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.desc = "Thermal Sensor Calibration Data",
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.base = EFUSE_OFFSET,
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.offset = 0x34,
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.size = 2,
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.id = AW_SID_FUSE_THSSENSOR,
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.public = false,
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},
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};
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static struct aw_sid_efuse h5_efuses[] = {
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{
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.name = "rootkey",
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.desc = "Root Key or ChipID",
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.base = EFUSE_OFFSET,
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.offset = 0x00,
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.size = 16,
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.id = AW_SID_FUSE_ROOTKEY,
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.public = true,
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},
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{
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.name = "ths-calib",
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.desc = "Thermal Sensor Calibration Data",
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.base = EFUSE_OFFSET,
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.offset = 0x34,
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.size = 4,
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.id = AW_SID_FUSE_THSSENSOR,
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.public = true,
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},
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};
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struct aw_sid_conf {
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bus_size_t efuse_size;
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bus_size_t rootkey_offset;
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bool has_prctl;
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bool has_thermal;
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bool requires_prctl_read;
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struct aw_sid_efuse *efuses;
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size_t nfuses;
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};
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static const struct aw_sid_conf a10_conf = {
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.efuse_size = 0x10,
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.rootkey_offset = 0,
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.efuses = a10_efuses,
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.nfuses = nitems(a10_efuses),
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};
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static const struct aw_sid_conf a20_conf = {
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.efuse_size = 0x10,
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.rootkey_offset = 0,
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.efuses = a10_efuses,
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.nfuses = nitems(a10_efuses),
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};
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static const struct aw_sid_conf a64_conf = {
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.efuse_size = 0x100,
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.rootkey_offset = SID_SRAM,
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.has_prctl = true,
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.has_thermal = true,
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.efuses = a64_efuses,
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.nfuses = nitems(a64_efuses),
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};
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static const struct aw_sid_conf a83t_conf = {
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.efuse_size = 0x100,
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.rootkey_offset = SID_SRAM,
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.has_prctl = true,
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.has_thermal = true,
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.efuses = a83t_efuses,
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.nfuses = nitems(a83t_efuses),
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};
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static const struct aw_sid_conf h3_conf = {
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.efuse_size = 0x100,
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.rootkey_offset = SID_SRAM,
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.has_prctl = true,
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.has_thermal = true,
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.requires_prctl_read = true,
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.efuses = h3_efuses,
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.nfuses = nitems(h3_efuses),
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};
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static const struct aw_sid_conf h5_conf = {
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.efuses = h5_efuses,
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.nfuses = nitems(h5_efuses),
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};
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static struct ofw_compat_data compat_data[] = {
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@ -115,6 +215,7 @@ static struct ofw_compat_data compat_data[] = {
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{ "allwinner,sun50i-a64-sid", (uintptr_t)&a64_conf},
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{ "allwinner,sun8i-a83t-sid", (uintptr_t)&a83t_conf},
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{ "allwinner,sun8i-h3-sid", (uintptr_t)&h3_conf},
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{ "allwinner,sun50i-h5-sid", (uintptr_t)&h5_conf},
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{ NULL, 0 }
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};
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@ -132,45 +233,11 @@ static struct resource_spec aw_sid_spec[] = {
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{ -1, 0 }
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};
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enum sid_keys {
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AW_SID_ROOT_KEY,
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};
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#define RD1(sc, reg) bus_read_1((sc)->res, (reg))
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#define RD4(sc, reg) bus_read_4((sc)->res, (reg))
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#define WR4(sc, reg, val) bus_write_4((sc)->res, (reg), (val))
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#define PRCTL_RD4(sc, reg, val) aw_sid_prctl_read((sc)->sid_dev, (reg), (val))
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static int aw_sid_sysctl(SYSCTL_HANDLER_ARGS);
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static int aw_sid_prctl_read(device_t dev, bus_size_t offset, uint32_t *val);
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/*
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* offset here is offset into efuse space, rather than offset into sid register
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* space. This form of read is only an option for newer SoC: A83t, H3, A64
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*/
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static int
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aw_sid_prctl_read(device_t dev, bus_size_t offset, uint32_t *val)
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{
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struct aw_sid_softc *sc;
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uint32_t readval;
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sc = device_get_softc(dev);
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if (!sc->sid_conf->has_prctl)
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return (1);
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mtx_lock(&sc->prctl_mtx);
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readval = SID_PRCTL_OFFSET(offset) | SID_PRCTL_LOCK | SID_PRCTL_READ;
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WR4(sc, SID_PRCTL, readval);
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/* Read bit will be cleared once read has concluded */
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while (RD4(sc, SID_PRCTL) & SID_PRCTL_READ)
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continue;
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readval = RD4(sc, SID_RDKEY);
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mtx_unlock(&sc->prctl_mtx);
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*val = readval;
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return (0);
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}
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static int
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aw_sid_probe(device_t dev)
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@ -189,7 +256,10 @@ static int
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aw_sid_attach(device_t dev)
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{
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struct aw_sid_softc *sc;
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phandle_t node;
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int i;
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node = ofw_bus_get_node(dev);
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sc = device_get_softc(dev);
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sc->sid_dev = dev;
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@ -202,74 +272,123 @@ aw_sid_attach(device_t dev)
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sc->sid_conf = (struct aw_sid_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data;
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aw_sid_sc = sc;
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SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
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SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
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OID_AUTO, "rootkey",
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CTLTYPE_STRING | CTLFLAG_RD,
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dev, AW_SID_ROOT_KEY, aw_sid_sysctl, "A", "Root Key");
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/* Register ourself so device can resolve who we are */
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OF_device_register_xref(OF_xref_from_node(node), dev);
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for (i = 0; i < sc->sid_conf->nfuses ;i++) {\
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SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
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SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
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OID_AUTO, sc->sid_conf->efuses[i].name,
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CTLTYPE_STRING | CTLFLAG_RD,
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dev, sc->sid_conf->efuses[i].id, aw_sid_sysctl,
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"A", sc->sid_conf->efuses[i].desc);
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}
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return (0);
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}
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int
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aw_sid_read_tscalib(uint32_t *calib0, uint32_t *calib1)
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aw_sid_get_fuse(enum aw_sid_fuse_id id, uint8_t *out, uint32_t *size)
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{
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struct aw_sid_softc *sc;
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uint32_t val;
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int i, j;
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sc = aw_sid_sc;
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if (sc == NULL)
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return (ENXIO);
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if (!sc->sid_conf->has_thermal)
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return (ENXIO);
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if (sc->sid_conf->requires_prctl_read) {
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PRCTL_RD4(sc, SID_THERMAL_CALIB0_OFF, calib0);
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PRCTL_RD4(sc, SID_THERMAL_CALIB1_OFF, calib1);
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} else {
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*calib0 = RD4(sc, SID_THERMAL_CALIB0);
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*calib1 = RD4(sc, SID_THERMAL_CALIB1);
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for (i = 0; i < sc->sid_conf->nfuses; i++)
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if (id == sc->sid_conf->efuses[i].id)
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break;
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if (i == sc->sid_conf->nfuses)
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return (ENOENT);
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if (*size != sc->sid_conf->efuses[i].size) {
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*size = sc->sid_conf->efuses[i].size;
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return (ENOMEM);
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}
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return (0);
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}
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if (out == NULL)
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return (ENOMEM);
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int
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aw_sid_get_rootkey(u_char *out)
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{
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struct aw_sid_softc *sc;
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int i;
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bus_size_t root_key_off;
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u_int tmp;
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sc = aw_sid_sc;
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if (sc == NULL)
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return (ENXIO);
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root_key_off = aw_sid_sc->sid_conf->rootkey_offset;
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for (i = 0; i < ROOT_KEY_SIZE ; i++) {
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if (sc->sid_conf->requires_prctl_read)
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PRCTL_RD4(sc, (i * 4), &tmp);
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else
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tmp = RD4(aw_sid_sc, root_key_off + (i * 4));
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be32enc(&out[i * 4], tmp);
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if (sc->sid_conf->efuses[i].public == false)
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mtx_lock(&sc->prctl_mtx);
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for (j = 0; j < sc->sid_conf->efuses[i].size; j += 4) {
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if (sc->sid_conf->efuses[i].public == false) {
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val = SID_PRCTL_OFFSET(sc->sid_conf->efuses[i].offset + j) |
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SID_PRCTL_LOCK |
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SID_PRCTL_READ;
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WR4(sc, SID_PRCTL, val);
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/* Read bit will be cleared once read has concluded */
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while (RD4(sc, SID_PRCTL) & SID_PRCTL_READ)
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continue;
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val = RD4(sc, SID_RDKEY);
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} else
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val = RD4(sc, sc->sid_conf->efuses[i].base +
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sc->sid_conf->efuses[i].offset + j);
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out[j] = val & 0xFF;
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if (j + 1 < *size)
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out[j + 1] = (val & 0xFF00) >> 8;
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if (j + 2 < *size)
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out[j + 2] = (val & 0xFF0000) >> 16;
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if (j + 3 < *size)
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out[j + 3] = (val & 0xFF000000) >> 24;
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}
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if (sc->sid_conf->efuses[i].public == false)
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mtx_unlock(&sc->prctl_mtx);
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return (0);
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}
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static int
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aw_sid_read(device_t dev, uint32_t offset, uint32_t size, uint8_t *buffer)
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{
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struct aw_sid_softc *sc;
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enum aw_sid_fuse_id fuse_id = 0;
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int i;
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sc = device_get_softc(dev);
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for (i = 0; i < sc->sid_conf->nfuses; i++)
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if (offset == (sc->sid_conf->efuses[i].base +
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sc->sid_conf->efuses[i].offset)) {
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fuse_id = sc->sid_conf->efuses[i].id;
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break;
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}
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if (fuse_id == 0)
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return (ENOENT);
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return (aw_sid_get_fuse(fuse_id, buffer, &size));
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}
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static int
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aw_sid_sysctl(SYSCTL_HANDLER_ARGS)
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{
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enum sid_keys key = arg2;
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u_char rootkey[16];
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char out[33];
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struct aw_sid_softc *sc;
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device_t dev = arg1;
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enum aw_sid_fuse_id fuse = arg2;
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uint8_t data[32];
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char out[128];
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uint32_t size;
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int ret, i;
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if (key != AW_SID_ROOT_KEY)
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return (ENOENT);
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sc = device_get_softc(dev);
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if (aw_sid_get_rootkey(rootkey) != 0)
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/* Get the size of the efuse data */
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size = 0;
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aw_sid_get_fuse(fuse, NULL, &size);
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/* We now have the real size */
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ret = aw_sid_get_fuse(fuse, data, &size);
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if (ret != 0) {
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device_printf(dev, "Cannot get fuse id %d: %d\n", fuse, ret);
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return (ENOENT);
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snprintf(out, sizeof(out),
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"%16D", rootkey, "");
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}
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for (i = 0; i < size; i++)
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snprintf(out + (i * 2), sizeof(out) - (i * 2),
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"%.2x", data[i]);
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return sysctl_handle_string(oidp, out, sizeof(out), req);
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}
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@ -279,6 +398,8 @@ static device_method_t aw_sid_methods[] = {
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DEVMETHOD(device_probe, aw_sid_probe),
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DEVMETHOD(device_attach, aw_sid_attach),
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/* NVMEM interface */
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DEVMETHOD(nvmem_read, aw_sid_read),
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DEVMETHOD_END
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};
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@ -29,7 +29,12 @@
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#ifndef __AW_SID_H__
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#define __AW_SID_H__
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enum aw_sid_fuse_id {
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AW_SID_FUSE_ROOTKEY = 1,
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AW_SID_FUSE_THSSENSOR,
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};
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int aw_sid_read_tscalib(uint32_t *, uint32_t *);
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int aw_sid_get_rootkey(u_char *out);
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int aw_sid_get_fuse(enum aw_sid_fuse_id id, uint8_t *out, uint32_t *size);
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#endif /* !__AW_SID_H__ */
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@ -50,10 +50,12 @@ __FBSDID("$FreeBSD$");
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/hwreset/hwreset.h>
|
||||
#include <dev/extres/nvmem/nvmem.h>
|
||||
|
||||
#include <arm/allwinner/aw_sid.h>
|
||||
|
||||
#include "cpufreq_if.h"
|
||||
#include "nvmem_if.h"
|
||||
|
||||
#define THS_CTRL0 0x00
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||||
#define THS_CTRL1 0x04
|
||||
@ -281,23 +283,31 @@ static struct resource_spec aw_thermal_spec[] = {
|
||||
static int
|
||||
aw_thermal_init(struct aw_thermal_softc *sc)
|
||||
{
|
||||
uint32_t calib0, calib1;
|
||||
phandle_t node;
|
||||
uint32_t calib[2];
|
||||
int error;
|
||||
|
||||
node = ofw_bus_get_node(sc->dev);
|
||||
if (sc->conf->calib0_mask != 0 || sc->conf->calib1_mask != 0) {
|
||||
/* Read calibration settings from SRAM */
|
||||
error = aw_sid_read_tscalib(&calib0, &calib1);
|
||||
if (error != 0)
|
||||
error = nvmem_read_cell_by_name(node, "ths_calibration",
|
||||
(void *)calib, sizeof(calib));
|
||||
/* Read calibration settings from EFUSE */
|
||||
if (error != 0) {
|
||||
device_printf(sc->dev, "Cannot read THS efuse\n");
|
||||
return (error);
|
||||
}
|
||||
|
||||
calib0 &= sc->conf->calib0_mask;
|
||||
calib1 &= sc->conf->calib1_mask;
|
||||
device_printf(sc->dev, "calib0: %x\n", calib[0]);
|
||||
device_printf(sc->dev, "calib1: %x\n", calib[1]);
|
||||
|
||||
calib[0] &= sc->conf->calib0_mask;
|
||||
calib[1] &= sc->conf->calib1_mask;
|
||||
|
||||
/* Write calibration settings to thermal controller */
|
||||
if (calib0 != 0)
|
||||
WR4(sc, THS_CALIB0, calib0);
|
||||
if (calib1 != 0)
|
||||
WR4(sc, THS_CALIB1, calib1);
|
||||
if (calib[0] != 0)
|
||||
WR4(sc, THS_CALIB0, calib[0]);
|
||||
if (calib[1] != 0)
|
||||
WR4(sc, THS_CALIB1, calib[1]);
|
||||
}
|
||||
|
||||
/* Configure ADC acquire time (CLK_IN/(N+1)) and enable sensors */
|
||||
|
||||
@ -1529,15 +1529,18 @@ awg_get_eaddr(device_t dev, uint8_t *eaddr)
|
||||
struct awg_softc *sc;
|
||||
uint32_t maclo, machi, rnd;
|
||||
u_char rootkey[16];
|
||||
uint32_t rootkey_size;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
machi = RD4(sc, EMAC_ADDR_HIGH(0)) & 0xffff;
|
||||
maclo = RD4(sc, EMAC_ADDR_LOW(0));
|
||||
|
||||
rootkey_size = sizeof(rootkey);
|
||||
if (maclo == 0xffffffff && machi == 0xffff) {
|
||||
/* MAC address in hardware is invalid, create one */
|
||||
if (aw_sid_get_rootkey(rootkey) == 0 &&
|
||||
if (aw_sid_get_fuse(AW_SID_FUSE_ROOTKEY, rootkey,
|
||||
&rootkey_size) == 0 &&
|
||||
(rootkey[3] | rootkey[12] | rootkey[13] | rootkey[14] |
|
||||
rootkey[15]) != 0) {
|
||||
/* MAC address is derived from the root key in SID */
|
||||
|
||||
@ -170,6 +170,7 @@ emac_get_hwaddr(struct emac_softc *sc, uint8_t *hwaddr)
|
||||
{
|
||||
uint32_t val0, val1, rnd;
|
||||
u_char rootkey[16];
|
||||
size_t rootkey_size;
|
||||
|
||||
/*
|
||||
* Try to get MAC address from running hardware.
|
||||
@ -193,7 +194,9 @@ emac_get_hwaddr(struct emac_softc *sc, uint8_t *hwaddr)
|
||||
hwaddr[4] = (val0 >> 8) & 0xff;
|
||||
hwaddr[5] = (val0 >> 0) & 0xff;
|
||||
} else {
|
||||
if (aw_sid_get_rootkey(rootkey) == 0) {
|
||||
rootkey_size = sizeof(rootkey);
|
||||
if (aw_sid_get_fuse(AW_SID_FUSE_ROOTKEY, rootkey,
|
||||
&rootkey_size) == 0) {
|
||||
hwaddr[0] = 0x2;
|
||||
hwaddr[1] = rootkey[3];
|
||||
hwaddr[2] = rootkey[12];
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user