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Add support for the AdvanSys ASC38C0800 Ultra2 chipset. Preliminary

Browse Source 
support is also included for the ASC38C1600 Ultra160 chipset, but
as firmware is not yet available for this chip, it is disabled.

Approved by: jkh@FreeBSD.org
This commit is contained in:
gibbs 2000-02-03 16:34:57 +00:00
parent d85ed62d80
commit 595b411966
7 changed files with 2539 additions and 1010 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

354
sys/dev/advansys/adw_pci.c
View File

@ -2,9 +2,11 @@
* Device probe and attach routines for the following
* Advanced Systems Inc. SCSI controllers:
*
* ABP940UW - Bus-Master PCI Ultra-Wide (240 CDB)
* ABP[3]940UW - Bus-Master PCI Ultra-Wide (253 CDB)
* ABP950UW - Dual Channel Bus-Master PCI Ultra-Wide (253 CDB/Channel)
* ABP3940U2W - Bus-Master PCI LVD/Ultra2-Wide (253 CDB)
*
* Copyright (c) 1998 Justin Gibbs.
* Copyright (c) 1998, 1999, 2000 Justin Gibbs.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -12,7 +14,7 @@
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification, immediately at the beginning of the file.
* without modification.
* 2. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
@ -34,9 +36,14 @@
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/bus.h>
#include <machine/bus_pio.h>
#include <machine/bus.h>
#include <machine/resource.h>
#include <sys/rman.h>
#include <pci/pcireg.h>
#include <pci/pcivar.h>
@ -48,91 +55,202 @@
#include <dev/advansys/adwlib.h>
#include <dev/advansys/adwmcode.h>
#define PCI_BASEADR0 PCI_MAP_REG_START /* I/O Address */
#define PCI_BASEADR1 PCI_MAP_REG_START + 4 /* Mem I/O Address */
#define ADW_PCI_IOBASE PCI_MAP_REG_START /* I/O Address */
#define ADW_PCI_MEMBASE PCI_MAP_REG_START + 4 /* Mem I/O Address */
#define PCI_DEVICE_ID_ADVANSYS_3550 0x230010CD
#define PCI_ID_ADVANSYS_3550 0x230010CD00000000ull
#define PCI_ID_ADVANSYS_38C0800_REV1 0x250010CD00000000ull
#define PCI_ID_ADVANSYS_38C1600_REV1 0x270010CD00000000ull
#define PCI_ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
#define PCI_ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
struct adw_pci_identity;
typedef int (adw_device_setup_t)(device_t, struct adw_pci_identity *,
struct adw_softc *adw);
struct adw_pci_identity {
u_int64_t full_id;
u_int64_t id_mask;
char *name;
adw_device_setup_t *setup;
const struct adw_mcode *mcode_data;
const struct adw_eeprom *default_eeprom;
};
static adw_device_setup_t adw_asc3550_setup;
static adw_device_setup_t adw_asc38C0800_setup;
#ifdef NOTYET
static adw_device_setup_t adw_asc38C1600_setup;
#endif
struct adw_pci_identity adw_pci_ident_table[] =
{
/* asc3550 based controllers */
{
PCI_ID_ADVANSYS_3550,
PCI_ID_DEV_VENDOR_MASK,
"AdvanSys 3550 Ultra SCSI Adapter",
adw_asc3550_setup,
&adw_asc3550_mcode_data,
&adw_asc3550_default_eeprom
},
/* asc38C0800 based controllers */
{
PCI_ID_ADVANSYS_38C0800_REV1,
PCI_ID_DEV_VENDOR_MASK,
"AdvanSys 38C0800 Ultra2 SCSI Adapter",
adw_asc38C0800_setup,
&adw_asc38C0800_mcode_data,
&adw_asc38C0800_default_eeprom
},
#if NOTYET
/* XXX Disabled until I have hardware to test with */
/* asc38C1600 based controllers */
{
PCI_ID_ADVANSYS_38C1600_REV1,
PCI_ID_DEV_VENDOR_MASK,
"AdvanSys 38C1600 Ultra160 SCSI Adapter",
adw_asc38C1600_setup,
NULL, /* None provided by vendor thus far */
NULL /* None provided by vendor thus far */
}
#endif
};
static const int adw_num_pci_devs =
sizeof(adw_pci_ident_table) / sizeof(*adw_pci_ident_table);
#define ADW_PCI_MAX_DMA_ADDR (0xFFFFFFFFUL)
#define ADW_PCI_MAX_DMA_COUNT (0xFFFFFFFFUL)
static const char* adwpciprobe(pcici_t tag, pcidi_t type);
static void adwpciattach(pcici_t config_id, int unit);
static int adw_pci_probe(device_t dev);
static int adw_pci_attach(device_t dev);
static struct pci_device adw_pci_driver = {
"adw",
adwpciprobe,
adwpciattach,
&adw_unit,
NULL
static device_method_t adw_pci_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, adw_pci_probe),
DEVMETHOD(device_attach, adw_pci_attach),
{ 0, 0 }
};
COMPAT_PCI_DRIVER (adw_pci, adw_pci_driver);
static driver_t adw_pci_driver = {
"adw",
adw_pci_methods,
sizeof(struct adw_softc)
};
static const char*
adwpciprobe(pcici_t tag, pcidi_t type)
static devclass_t adw_devclass;
DRIVER_MODULE(adw, pci, adw_pci_driver, adw_devclass, 0, 0);
static __inline u_int64_t
adw_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
{
switch (type) {
case PCI_DEVICE_ID_ADVANSYS_3550:
return ("AdvanSys ASC3550 SCSI controller");
default:
break;
u_int64_t id;
id = subvendor
| (subdevice << 16)
| ((u_int64_t)vendor << 32)
| ((u_int64_t)device << 48);
return (id);
}
static struct adw_pci_identity *
adw_find_pci_device(device_t dev)
{
u_int64_t full_id;
struct adw_pci_identity *entry;
u_int i;
full_id = adw_compose_id(pci_get_device(dev),
pci_get_vendor(dev),
pci_get_subdevice(dev),
pci_get_subvendor(dev));
for (i = 0; i < adw_num_pci_devs; i++) {
entry = &adw_pci_ident_table[i];
if (entry->full_id == (full_id & entry->id_mask))
return (entry);
}
return (NULL);
}
static void
adwpciattach(pcici_t config_id, int unit)
static int
adw_pci_probe(device_t dev)
{
u_int32_t id;
u_int32_t command;
vm_offset_t vaddr;
#ifdef ADW_ALLOW_MEMIO
vm_offset_t paddr;
#endif
u_int16_t io_port;
bus_space_tag_t tag;
bus_space_handle_t bsh;
struct adw_softc *adw;
int error;
struct adw_pci_identity *entry;
entry = adw_find_pci_device(dev);
if (entry != NULL) {
device_set_desc(dev, entry->name);
return (0);
}
return (ENXIO);
}
static int
adw_pci_attach(device_t dev)
{
struct adw_softc *adw;
struct adw_pci_identity *entry;
u_int32_t command;
struct resource *regs;
int regs_type;
int regs_id;
int error;
int zero;
/*
* Determine the chip version.
*/
id = pci_cfgread(config_id, PCI_ID_REG, /*bytes*/4);
command = pci_cfgread(config_id, PCIR_COMMAND, /*bytes*/1);
/*
* These cards do not allow memory mapped accesses, so we must
* ensure that I/O accesses are available or we won't be able
* to talk to them.
*/
vaddr = 0;
command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1);
entry = adw_find_pci_device(dev);
if (entry == NULL)
return (ENXIO);
regs = NULL;
regs_type = 0;
regs_id = 0;
#ifdef ADW_ALLOW_MEMIO
if ((command & PCI_COMMAND_MEM_ENABLE) == 0
|| (pci_map_mem(config_id, PCI_BASEADR1, &vaddr, &paddr)) == 0)
if ((command & PCIM_CMD_MEMEN) != 0)
regs_type = SYS_RES_MEMORY;
regs_id = ADW_PCI_MEMBASE;
regs = bus_alloc_resource(dev, regs_type,
&regs_id, 0, ~0, 1, RF_ACTIVE);
}
#endif
if ((command & PCI_COMMAND_IO_ENABLE) == 0
|| (pci_map_port(config_id, PCI_BASEADR0, &io_port)) == 0)
return;
/* XXX Should be passed in by parent bus */
/* XXX Why isn't the 0x10 offset incorporated into the reg defs? */
if (vaddr != 0) {
tag = I386_BUS_SPACE_MEM;
bsh = vaddr;
} else {
tag = I386_BUS_SPACE_IO;
bsh = io_port;
if (regs == NULL && (command & PCI_COMMAND_IO_ENABLE) != 0) {
regs_type = SYS_RES_IOPORT;
regs_id = ADW_PCI_IOBASE;
regs = bus_alloc_resource(dev, regs_type,
&regs_id, 0, ~0, 1, RF_ACTIVE);
}
if (regs == NULL) {
device_printf(dev, "can't allocate register resources\n");
return (ENOMEM);
}
if (adw_find_signature(tag, bsh) == 0)
return;
adw = adw_alloc(unit, tag, bsh);
adw = adw_alloc(dev, regs, regs_type, regs_id);
if (adw == NULL)
return;
return(ENOMEM);
/*
* Now that we have access to our registers, just verify that
* this really is an AdvanSys device.
*/
if (adw_find_signature(adw) == 0) {
adw_free(adw);
return (ENXIO);
}
adw_reset_chip(adw);
error = entry->setup(dev, entry, adw);
if (error != 0)
return (error);
/* Ensure busmastering is enabled */
command |= PCIM_CMD_BUSMASTEREN;
pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1);
/* Allocate a dmatag for our transfer DMA maps */
/* XXX Should be a child of the PCI bus dma tag */
@ -153,14 +271,15 @@ adwpciattach(pcici_t config_id, int unit)
printf("%s: Could not allocate DMA tag - error %d\n",
adw_name(adw), error);
adw_free(adw);
return;
return (error);
}
adw->init_level++;
if (adw_init(adw) != 0) {
error = adw_init(adw);
if (error != 0) {
adw_free(adw);
return;
return (error);
}
/*
@ -174,10 +293,99 @@ adwpciattach(pcici_t config_id, int unit)
adw_lram_read_16(adw, ADW_MC_CONTROL_FLAG)
| ADW_MC_CONTROL_IGN_PERR);
if ((pci_map_int(config_id, adw_intr, (void *)adw, &cam_imask)) == 0) {
zero = 0;
adw->irq_res_type = SYS_RES_IRQ;
adw->irq = bus_alloc_resource(dev, adw->irq_res_type, &zero,
0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
if (adw->irq == NULL) {
adw_free(adw);
return;
return (ENOMEM);
}
adw_attach(adw);
error = adw_attach(adw);
if (error != 0)
adw_free(adw);
return (error);
}
static int
adw_generic_setup(device_t dev, struct adw_pci_identity *entry,
struct adw_softc *adw)
{
adw->channel = pci_get_function(dev) == 1 ? 'B' : 'A';
adw->chip = ADW_CHIP_NONE;
adw->features = ADW_FENONE;
adw->flags = ADW_FNONE;
adw->mcode_data = entry->mcode_data;
adw->default_eeprom = entry->default_eeprom;
return (0);
}
static int
adw_asc3550_setup(device_t dev, struct adw_pci_identity *entry,
struct adw_softc *adw)
{
int error;
error = adw_generic_setup(dev, entry, adw);
if (error != 0)
return (error);
adw->chip = ADW_CHIP_ASC3550;
adw->features = ADW_ASC3550_FE;
adw->memsize = ADW_3550_MEMSIZE;
/*
* For ASC-3550, setting the START_CTL_EMFU [3:2] bits
* sets a FIFO threshold of 128 bytes. This register is
* only accessible to the host.
*/
adw_outb(adw, ADW_DMA_CFG0,
ADW_DMA_CFG0_START_CTL_EM_FU|ADW_DMA_CFG0_READ_CMD_MRM);
adw_outb(adw, ADW_MEM_CFG,
adw_inb(adw, ADW_MEM_CFG) | ADW_MEM_CFG_RAM_SZ_8KB);
return (0);
}
static int
adw_asc38C0800_setup(device_t dev, struct adw_pci_identity *entry,
struct adw_softc *adw)
{
int error;
error = adw_generic_setup(dev, entry, adw);
if (error != 0)
return (error);
/*
* For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and
* START_CTL_TH [3:2] bits for the default FIFO threshold.
*
* Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
*
* For DMA Errata #4 set the BC_THRESH_ENB bit.
*/
adw_outb(adw, ADW_DMA_CFG0,
ADW_DMA_CFG0_BC_THRESH_ENB|ADW_DMA_CFG0_FIFO_THRESH_80B
|ADW_DMA_CFG0_START_CTL_TH|ADW_DMA_CFG0_READ_CMD_MRM);
adw_outb(adw, ADW_MEM_CFG,
adw_inb(adw, ADW_MEM_CFG) | ADW_MEM_CFG_RAM_SZ_16KB);
adw->chip = ADW_CHIP_ASC38C0800;
adw->features = ADW_ASC38C0800_FE;
adw->memsize = ADW_38C0800_MEMSIZE;
return (error);
}
#ifdef NOTYET
static int
adw_asc38C1600_setup(device_t dev, struct adw_pci_identity *entry,
struct adw_softc *adw)
{
int error;
error = adw_generic_setup(dev, entry, adw);
if (error != 0)
return (error);
adw->chip = ADW_CHIP_ASC38C1600;
adw->features = ADW_ASC38C1600_FE;
adw->memsize = ADW_38C1600_MEMSIZE;
return (error);
}
#endif

561
sys/dev/advansys/adwcam.c
View File

@ -4,9 +4,9 @@
*
* Product specific probe and attach routines can be found in:
*
* pci/adw_pci.c ABP940UW
* adw_pci.c ABP[3]940UW, ABP950UW, ABP3940U2W
*
* Copyright (c) 1998 Justin Gibbs.
* Copyright (c) 1998, 1999, 2000 Justin Gibbs.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -14,7 +14,7 @@
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification, immediately at the beginning of the file.
* without modification.
* 2. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
@ -50,11 +50,15 @@
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/malloc.h>
#include <sys/bus.h>
#include <machine/bus_pio.h>
#include <machine/bus_memio.h>
#include <machine/bus.h>
#include <machine/clock.h>
#include <machine/resource.h>
#include <sys/rman.h>
#include <cam/cam.h>
#include <cam/cam_ccb.h>
@ -74,10 +78,6 @@
u_long adw_unit;
static __inline u_int32_t acbvtop(struct adw_softc *adw,
struct acb *acb);
static __inline struct acb * acbptov(struct adw_softc *adw,
u_int32_t busaddr);
static __inline struct acb* adwgetacb(struct adw_softc *adw);
static __inline void adwfreeacb(struct adw_softc *adw,
struct acb *acb);
@ -101,20 +101,6 @@ static void adw_handle_device_reset(struct adw_softc *adw,
static void adw_handle_bus_reset(struct adw_softc *adw,
int initiated);
static __inline u_int32_t
acbvtop(struct adw_softc *adw, struct acb *acb)
{
return (adw->acb_busbase
+ (u_int32_t)((caddr_t)acb - (caddr_t)adw->acbs));
}
static __inline struct acb *
acbptov(struct adw_softc *adw, u_int32_t busaddr)
{
return (adw->acbs
+ ((struct acb *)busaddr - (struct acb *)adw->acb_busbase));
}
static __inline struct acb*
adwgetacb(struct adw_softc *adw)
{
@ -208,7 +194,6 @@ adwallocacbs(struct adw_softc *adw)
int i;
next_acb = &adw->acbs[adw->num_acbs];
sg_map = adwallocsgmap(adw);
if (sg_map == NULL)
@ -220,22 +205,17 @@ adwallocacbs(struct adw_softc *adw)
newcount = (PAGE_SIZE / (ADW_SG_BLOCKCNT * sizeof(*blocks)));
for (i = 0; adw->num_acbs < adw->max_acbs && i < newcount; i++) {
int error;
int j;
error = bus_dmamap_create(adw->buffer_dmat, /*flags*/0,
&next_acb->dmamap);
if (error != 0)
break;
next_acb->queue.scsi_req_baddr = acbvtop(adw, next_acb);
next_acb->queue.sense_addr =
acbvtop(adw, next_acb) + offsetof(struct acb, sense_data);
next_acb->queue.scsi_req_baddr = acbvtob(adw, next_acb);
next_acb->queue.scsi_req_bo = acbvtobo(adw, next_acb);
next_acb->queue.sense_baddr =
acbvtob(adw, next_acb) + offsetof(struct acb, sense_data);
next_acb->sg_blocks = blocks;
next_acb->sg_busaddr = busaddr;
/* Setup static data in the sg blocks */
for (j = 0; j < ADW_SG_BLOCKCNT; j++) {
next_acb->sg_blocks[j].first_entry_no =
j * ADW_NO_OF_SG_PER_BLOCK;
}
next_acb->state = ACB_FREE;
SLIST_INSERT_HEAD(&adw->free_acb_list, next_acb, links);
blocks += ADW_SG_BLOCKCNT;
@ -289,19 +269,20 @@ adwexecuteacb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
sg_index = 0;
/* Copy the segments into our SG list */
for (sg_block = acb->sg_blocks;; sg_block++) {
u_int sg_left;
u_int i;
sg_left = ADW_NO_OF_SG_PER_BLOCK;
sg = sg_block->sg_list;
while (dm_segs < end_seg && sg_left != 0) {
for (i = 0; i < ADW_NO_OF_SG_PER_BLOCK; i++) {
if (dm_segs >= end_seg)
break;
sg->sg_addr = dm_segs->ds_addr;
sg->sg_count = dm_segs->ds_len;
sg++;
dm_segs++;
sg_left--;
}
sg_index += ADW_NO_OF_SG_PER_BLOCK - sg_left;
sg_block->last_entry_no = sg_index - 1;
sg_block->sg_cnt = i;
sg_index += i;
if (dm_segs == end_seg) {
sg_block->sg_busaddr_next = 0;
break;
@ -311,11 +292,8 @@ adwexecuteacb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
sg_block->sg_busaddr_next = sg_busaddr;
}
}
acb->queue.sg_entry_cnt = nseg;
acb->queue.sg_real_addr = acb->sg_busaddr;
} else {
acb->queue.sg_entry_cnt = 0;
acb->queue.sg_real_addr = 0;
}
@ -327,13 +305,10 @@ adwexecuteacb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
bus_dmamap_sync(adw->buffer_dmat, acb->dmamap, op);
} else {
acb->queue.sg_entry_cnt = 0;
acb->queue.data_addr = 0;
acb->queue.data_cnt = 0;
acb->queue.sg_real_addr = 0;
}
acb->queue.free_scsiq_link = 0;
acb->queue.ux_wk_data_cnt = 0;
s = splcam();
@ -357,7 +332,7 @@ adwexecuteacb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
timeout(adwtimeout, (caddr_t)acb,
(ccb->ccb_h.timeout * hz) / 1000);
adw_send_acb(adw, acb, acbvtop(adw, acb));
adw_send_acb(adw, acb, acbvtob(adw, acb));
splx(s);
}
@ -381,6 +356,7 @@ adw_action(struct cam_sim *sim, union ccb *ccb)
csio = &ccb->csio;
ccbh = &ccb->ccb_h;
/* Max supported CDB length is 12 bytes */
if (csio->cdb_len > 12) {
ccb->ccb_h.status = CAM_REQ_INVALID;
@ -400,31 +376,42 @@ adw_action(struct cam_sim *sim, union ccb *ccb)
return;
}
/* Link dccb and ccb so we can find one from the other */
/* Link acb and ccb so we can find one from the other */
acb->ccb = ccb;
ccb->ccb_h.ccb_acb_ptr = acb;
ccb->ccb_h.ccb_adw_ptr = adw;
acb->queue.cntl = 0;
acb->queue.target_cmd = 0;
acb->queue.target_id = ccb->ccb_h.target_id;
acb->queue.target_lun = ccb->ccb_h.target_lun;
acb->queue.srb_ptr = 0;
acb->queue.a_flag = 0;
acb->queue.mflag = 0;
acb->queue.sense_len =
MIN(csio->sense_len, sizeof(acb->sense_data));
acb->queue.cdb_len = csio->cdb_len;
if ((ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) != 0) {
switch (csio->tag_action) {
case MSG_SIMPLE_Q_TAG:
acb->queue.scsi_cntl = 0;
break;
case MSG_HEAD_OF_Q_TAG:
acb->queue.scsi_cntl = ADW_QSC_HEAD_OF_Q_TAG;
break;
case MSG_ORDERED_Q_TAG:
acb->queue.scsi_cntl = ADW_QSC_ORDERED_Q_TAG;
break;
}
} else
acb->queue.scsi_cntl = ADW_QSC_NO_TAGMSG;
if ((ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) != 0)
acb->queue.tag_code = csio->tag_action;
else
acb->queue.tag_code = 0;
if ((ccb->ccb_h.flags & CAM_DIS_DISCONNECT) != 0)
acb->queue.scsi_cntl |= ADW_QSC_NO_DISC;
acb->queue.done_status = 0;
acb->queue.scsi_status = 0;
acb->queue.host_status = 0;
acb->queue.ux_sg_ix = 0;
acb->queue.sg_wk_ix = 0;
if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0) {
if ((ccb->ccb_h.flags & CAM_CDB_PHYS) == 0) {
bcopy(csio->cdb_io.cdb_ptr,
@ -541,6 +528,9 @@ adw_action(struct cam_sim *sim, union ccb *ccb)
s = splcam();
if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) {
u_int sdtrdone;
sdtrdone = adw_lram_read_16(adw, ADW_MC_SDTR_DONE);
if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) {
u_int discenb;
@ -592,58 +582,57 @@ adw_action(struct cam_sim *sim, union ccb *ccb)
adw_lram_write_16(adw,
ADW_MC_WDTR_DONE,
wdtrdone);
/* Wide negotiation forces async */
sdtrdone &= ~target_mask;
adw_lram_write_16(adw,
ADW_MC_SDTR_DONE,
sdtrdone);
}
}
if (((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0)
|| ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) != 0)) {
u_int sdtrenb_orig;
u_int sdtrenb;
u_int ultraenb_orig;
u_int ultraenb;
u_int sdtrdone;
u_int sdtr_orig;
u_int sdtr;
u_int sdtrable_orig;
u_int sdtrable;
sdtrenb_orig =
adw_lram_read_16(adw, ADW_MC_SDTR_ABLE);
sdtrenb = sdtrenb_orig;
ultraenb_orig =
adw_lram_read_16(adw, ADW_MC_ULTRA_ABLE);
ultraenb = ultraenb_orig;
sdtrdone = adw_lram_read_16(adw,
ADW_MC_SDTR_DONE);
sdtr = adw_get_chip_sdtr(adw,
ccb->ccb_h.target_id);
sdtr_orig = sdtr;
sdtrable = adw_lram_read_16(adw,
ADW_MC_SDTR_ABLE);
sdtrable_orig = sdtrable;
if ((cts->valid
& CCB_TRANS_SYNC_RATE_VALID) != 0) {
if (cts->sync_period == 0) {
sdtrenb &= ~target_mask;
} else if (cts->sync_period > 12) {
ultraenb &= ~target_mask;
sdtrenb |= target_mask;
} else {
ultraenb |= target_mask;
sdtrenb |= target_mask;
}
sdtr =
adw_find_sdtr(adw,
cts->sync_period);
}
if ((cts->valid
& CCB_TRANS_SYNC_OFFSET_VALID) != 0) {
if (cts->sync_offset == 0)
sdtrenb &= ~target_mask;
sdtr = ADW_MC_SDTR_ASYNC;
}
if (sdtrenb != sdtrenb_orig
|| ultraenb != ultraenb_orig) {
adw_lram_write_16(adw, ADW_MC_SDTR_ABLE,
sdtrenb);
adw_lram_write_16(adw,
ADW_MC_ULTRA_ABLE,
ultraenb);
if (sdtr == ADW_MC_SDTR_ASYNC)
sdtrable &= ~target_mask;
else
sdtrable |= target_mask;
if (sdtr != sdtr_orig
|| sdtrable != sdtrable_orig) {
adw_set_chip_sdtr(adw,
ccb->ccb_h.target_id,
sdtr);
sdtrdone &= ~target_mask;
adw_lram_write_16(adw, ADW_MC_SDTR_ABLE,
sdtrable);
adw_lram_write_16(adw, ADW_MC_SDTR_DONE,
sdtrdone);
}
}
}
@ -661,6 +650,8 @@ adw_action(struct cam_sim *sim, union ccb *ccb)
cts = &ccb->cts;
target_mask = 0x01 << ccb->ccb_h.target_id;
if ((cts->flags & CCB_TRANS_USER_SETTINGS) != 0) {
u_int mc_sdtr;
cts->flags = 0;
if ((adw->user_discenb & target_mask) != 0)
cts->flags |= CCB_TRANS_DISC_ENB;
@ -673,13 +664,12 @@ adw_action(struct cam_sim *sim, union ccb *ccb)
else
cts->bus_width = MSG_EXT_WDTR_BUS_8_BIT;
if ((adw->user_sdtr & target_mask) != 0) {
if ((adw->user_ultra & target_mask) != 0)
cts->sync_period = 12; /* 20MHz */
else
cts->sync_period = 25; /* 10MHz */
mc_sdtr = adw_get_user_sdtr(adw, ccb->ccb_h.target_id);
cts->sync_period = adw_find_period(adw, mc_sdtr);
if (cts->sync_period != 0)
cts->sync_offset = 15; /* XXX ??? */
}
else
cts->sync_offset = 0;
cts->valid = CCB_TRANS_SYNC_RATE_VALID
| CCB_TRANS_SYNC_OFFSET_VALID
@ -709,7 +699,7 @@ adw_action(struct cam_sim *sim, union ccb *ccb)
cts->bus_width = MSG_EXT_WDTR_BUS_8_BIT;
cts->sync_period =
ADW_HSHK_CFG_PERIOD_FACTOR(targ_tinfo);
adw_hshk_cfg_period_factor(targ_tinfo);
cts->sync_offset = targ_tinfo & ADW_HSHK_CFG_OFFSET;
if (cts->sync_period == 0)
@ -760,16 +750,27 @@ adw_action(struct cam_sim *sim, union ccb *ccb)
{
adw_idle_cmd_status_t status;
adw_idle_cmd_send(adw, ADW_IDLE_CMD_SCSI_RESET, /*param*/0);
adw_idle_cmd_send(adw, ADW_IDLE_CMD_SCSI_RESET_START,
/*param*/0);
status = adw_idle_cmd_wait(adw);
if (status == ADW_IDLE_CMD_SUCCESS) {
ccb->ccb_h.status = CAM_REQ_CMP;
if (bootverbose) {
xpt_print_path(adw->path);
printf("Bus Reset Delivered\n");
}
} else
if (status != ADW_IDLE_CMD_SUCCESS) {
ccb->ccb_h.status = CAM_REQ_CMP_ERR;
xpt_done(ccb);
break;
}
DELAY(100);
adw_idle_cmd_send(adw, ADW_IDLE_CMD_SCSI_RESET_END, /*param*/0);
status = adw_idle_cmd_wait(adw);
if (status != ADW_IDLE_CMD_SUCCESS) {
ccb->ccb_h.status = CAM_REQ_CMP_ERR;
xpt_done(ccb);
break;
}
ccb->ccb_h.status = CAM_REQ_CMP;
if (bootverbose) {
xpt_print_path(adw->path);
printf("Bus Reset Delivered\n");
}
xpt_done(ccb);
break;
}
@ -819,7 +820,7 @@ adw_async(void *callback_arg, u_int32_t code, struct cam_path *path, void *arg)
}
struct adw_softc *
adw_alloc(int unit, bus_space_tag_t tag, bus_space_handle_t bsh)
adw_alloc(device_t dev, struct resource *regs, int regs_type, int regs_id)
{
struct adw_softc *adw;
int i;
@ -829,19 +830,23 @@ adw_alloc(int unit, bus_space_tag_t tag, bus_space_handle_t bsh)
*/
adw = malloc(sizeof(struct adw_softc), M_DEVBUF, M_NOWAIT);
if (adw == NULL) {
printf("adw%d: cannot malloc!\n", unit);
printf("adw%d: cannot malloc!\n", device_get_unit(dev));
return NULL;
}
bzero(adw, sizeof(struct adw_softc));
LIST_INIT(&adw->pending_ccbs);
SLIST_INIT(&adw->sg_maps);
adw->unit = unit;
adw->tag = tag;
adw->bsh = bsh;
adw->device = dev;
adw->unit = device_get_unit(dev);
adw->regs_res_type = regs_type;
adw->regs_res_id = regs_id;
adw->regs = regs;
adw->tag = rman_get_bustag(regs);
adw->bsh = rman_get_bushandle(regs);
i = adw->unit / 10;
adw->name = malloc(sizeof("adw") + i + 1, M_DEVBUF, M_NOWAIT);
if (adw->name == NULL) {
printf("adw%d: cannot malloc name!\n", unit);
printf("adw%d: cannot malloc name!\n", adw->unit);
free(adw, M_DEVBUF);
return NULL;
}
@ -853,7 +858,7 @@ void
adw_free(struct adw_softc *adw)
{
switch (adw->init_level) {
case 6:
case 9:
{
struct sg_map_node *sg_map;
@ -867,14 +872,22 @@ adw_free(struct adw_softc *adw)
}
bus_dma_tag_destroy(adw->sg_dmat);
}
case 5:
case 8:
bus_dmamap_unload(adw->acb_dmat, adw->acb_dmamap);
case 4:
case 7:
bus_dmamem_free(adw->acb_dmat, adw->acbs,
adw->acb_dmamap);
bus_dmamap_destroy(adw->acb_dmat, adw->acb_dmamap);
case 3:
case 6:
bus_dma_tag_destroy(adw->acb_dmat);
case 5:
bus_dmamap_unload(adw->carrier_dmat, adw->carrier_dmamap);
case 4:
bus_dmamem_free(adw->carrier_dmat, adw->carriers,
adw->carrier_dmamap);
bus_dmamap_destroy(adw->carrier_dmat, adw->carrier_dmamap);
case 3:
bus_dma_tag_destroy(adw->carrier_dmat);
case 2:
bus_dma_tag_destroy(adw->buffer_dmat);
case 1:
@ -890,16 +903,18 @@ int
adw_init(struct adw_softc *adw)
{
struct adw_eeprom eep_config;
u_int tid;
u_int i;
u_int16_t checksum;
u_int16_t scsicfg1;
adw_reset_chip(adw);
checksum = adw_eeprom_read(adw, &eep_config);
bcopy(eep_config.serial_number, adw->serial_number,
sizeof(adw->serial_number));
if (checksum != eep_config.checksum) {
u_int16_t serial_number[3];
adw->flags |= ADW_EEPROM_FAILED;
printf("%s: EEPROM checksum failed. Restoring Defaults\n",
adw_name(adw));
@ -909,7 +924,7 @@ adw_init(struct adw_softc *adw)
* from EEPROM is correct even if the EEPROM checksum
* failed.
*/
bcopy(&adw_default_eeprom, &eep_config, sizeof(eep_config));
bcopy(adw->default_eeprom, &eep_config, sizeof(eep_config));
bcopy(adw->serial_number, eep_config.serial_number,
sizeof(serial_number));
adw_eeprom_write(adw, &eep_config);
@ -918,8 +933,46 @@ adw_init(struct adw_softc *adw)
/* Pull eeprom information into our softc. */
adw->bios_ctrl = eep_config.bios_ctrl;
adw->user_wdtr = eep_config.wdtr_able;
adw->user_sdtr = eep_config.sdtr_able;
adw->user_ultra = eep_config.ultra_able;
for (tid = 0; tid < ADW_MAX_TID; tid++) {
u_int mc_sdtr;
u_int16_t tid_mask;
tid_mask = 0x1 << tid;
if ((adw->features & ADW_ULTRA) != 0) {
/*
* Ultra chips store sdtr and ultraenb
* bits in their seeprom, so we must
* construct valid mc_sdtr entries for
* indirectly.
*/
if (eep_config.sync1.sync_enable & tid_mask) {
if (eep_config.sync2.ultra_enable & tid_mask)
mc_sdtr = ADW_MC_SDTR_20;
else
mc_sdtr = ADW_MC_SDTR_10;
} else
mc_sdtr = ADW_MC_SDTR_ASYNC;
} else {
switch (ADW_TARGET_GROUP(tid)) {
case 3:
mc_sdtr = eep_config.sync4.sdtr4;
break;
case 2:
mc_sdtr = eep_config.sync3.sdtr3;
break;
case 1:
mc_sdtr = eep_config.sync2.sdtr2;
break;
default: /* Shut up compiler */
case 0:
mc_sdtr = eep_config.sync1.sdtr1;
break;
}
mc_sdtr >>= ADW_TARGET_GROUP_SHIFT(tid);
mc_sdtr &= 0xFF;
}
adw_set_user_sdtr(adw, tid, mc_sdtr);
}
adw->user_tagenb = eep_config.tagqng_able;
adw->user_discenb = eep_config.disc_enable;
adw->max_acbs = eep_config.max_host_qng;
@ -936,15 +989,36 @@ adw_init(struct adw_softc *adw)
adw->max_acbs = ADW_DEF_MAX_HOST_QNG;
else
adw->max_acbs = ADW_DEF_MIN_HOST_QNG;
}
scsicfg1 = 0;
switch (eep_config.termination) {
if ((adw->features & ADW_ULTRA2) != 0) {
switch (eep_config.termination_lvd) {
default:
printf("%s: Invalid EEPROM LVD Termination Settings.\n",
adw_name(adw));
printf("%s: Reverting to Automatic LVD Termination\n",
adw_name(adw));
/* FALLTHROUGH */
case ADW_EEPROM_TERM_AUTO:
break;
case ADW_EEPROM_TERM_BOTH_ON:
scsicfg1 |= ADW2_SCSI_CFG1_TERM_LVD_LO;
/* FALLTHROUGH */
case ADW_EEPROM_TERM_HIGH_ON:
scsicfg1 |= ADW2_SCSI_CFG1_TERM_LVD_HI;
/* FALLTHROUGH */
case ADW_EEPROM_TERM_OFF:
scsicfg1 |= ADW2_SCSI_CFG1_DIS_TERM_DRV;
break;
}
}
switch (eep_config.termination_se) {
default:
printf("%s: Invalid EEPROM Termination Settings.\n",
printf("%s: Invalid SE EEPROM Termination Settings.\n",
adw_name(adw));
printf("%s: Reverting to Automatic Termination\n",
printf("%s: Reverting to Automatic SE Termination\n",
adw_name(adw));
/* FALLTHROUGH */
case ADW_EEPROM_TERM_AUTO:
@ -959,29 +1033,79 @@ adw_init(struct adw_softc *adw)
scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_MANUAL;
break;
}
printf("%s: SCSI ID %d, ", adw_name(adw), adw->initiator_id);
if (adw_init_chip(adw, scsicfg1) != 0)
return (-1);
printf("Queue Depth %d\n", adw->max_acbs);
/* DMA tag for mapping buffers into device visible space. */
if (bus_dma_tag_create(adw->parent_dmat, /*alignment*/1, /*boundary*/0,
/*lowaddr*/BUS_SPACE_MAXADDR,
/*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
/*highaddr*/BUS_SPACE_MAXADDR,
/*filter*/NULL, /*filterarg*/NULL,
/*maxsize*/MAXBSIZE, /*nsegments*/ADW_SGSIZE,
/*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
/*flags*/BUS_DMA_ALLOCNOW,
&adw->buffer_dmat) != 0) {
return (-1);
return (ENOMEM);
}
adw->init_level++;
/* DMA tag for our ccb structures */
/* DMA tag for our ccb carrier structures */
if (bus_dma_tag_create(adw->parent_dmat, /*alignment*/0x10,
/*boundary*/0,
/*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
/*highaddr*/BUS_SPACE_MAXADDR,
/*filter*/NULL, /*filterarg*/NULL,
(adw->max_acbs + ADW_NUM_CARRIER_QUEUES + 1)
* sizeof(struct adw_carrier),
/*nsegments*/1,
/*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
/*flags*/0, &adw->carrier_dmat) != 0) {
return (ENOMEM);
}
adw->init_level++;
/* Allocation for our ccb carrier structures */
if (bus_dmamem_alloc(adw->carrier_dmat, (void **)&adw->carriers,
BUS_DMA_NOWAIT, &adw->carrier_dmamap) != 0) {
return (ENOMEM);
}
adw->init_level++;
/* And permanently map them */
bus_dmamap_load(adw->carrier_dmat, adw->carrier_dmamap,
adw->carriers,
(adw->max_acbs + ADW_NUM_CARRIER_QUEUES + 1)
* sizeof(struct adw_carrier),
adwmapmem, &adw->carrier_busbase, /*flags*/0);
/* Clear them out. */
bzero(adw->carriers, (adw->max_acbs + ADW_NUM_CARRIER_QUEUES + 1)
* sizeof(struct adw_carrier));
/* Setup our free carrier list */
adw->free_carriers = adw->carriers;
for (i = 0; i < adw->max_acbs + ADW_NUM_CARRIER_QUEUES; i++) {
adw->carriers[i].carr_offset =
carriervtobo(adw, &adw->carriers[i]);
adw->carriers[i].carr_ba =
carriervtob(adw, &adw->carriers[i]);
adw->carriers[i].areq_ba = 0;
adw->carriers[i].next_ba =
carriervtobo(adw, &adw->carriers[i+1]);
}
/* Terminal carrier. Never leaves the freelist */
adw->carriers[i].carr_offset =
carriervtobo(adw, &adw->carriers[i]);
adw->carriers[i].carr_ba =
carriervtob(adw, &adw->carriers[i]);
adw->carriers[i].areq_ba = 0;
adw->carriers[i].next_ba = ~0;
adw->init_level++;
/* DMA tag for our acb structures */
if (bus_dma_tag_create(adw->parent_dmat, /*alignment*/1, /*boundary*/0,
/*lowaddr*/BUS_SPACE_MAXADDR,
/*highaddr*/BUS_SPACE_MAXADDR,
@ -990,16 +1114,15 @@ adw_init(struct adw_softc *adw)
/*nsegments*/1,
/*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
/*flags*/0, &adw->acb_dmat) != 0) {
return (-1);
return (ENOMEM);
}
adw->init_level++;
/* Allocation for our ccbs */
if (bus_dmamem_alloc(adw->acb_dmat, (void **)&adw->acbs,
BUS_DMA_NOWAIT, &adw->acb_dmamap) != 0) {
return (-1);
}
BUS_DMA_NOWAIT, &adw->acb_dmamap) != 0)
return (ENOMEM);
adw->init_level++;
@ -1020,14 +1143,19 @@ adw_init(struct adw_softc *adw)
PAGE_SIZE, /*nsegments*/1,
/*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
/*flags*/0, &adw->sg_dmat) != 0) {
return (-1);
return (ENOMEM);
}
adw->init_level++;
/* Allocate our first batch of ccbs */
if (adwallocacbs(adw) == 0)
return (-1);
return (ENOMEM);
if (adw_init_chip(adw, scsicfg1) != 0)
return (ENXIO);
printf("Queue Depth %d\n", adw->max_acbs);
return (0);
}
@ -1040,6 +1168,18 @@ adw_attach(struct adw_softc *adw)
{
struct ccb_setasync csa;
struct cam_devq *devq;
int s;
int error;
error = 0;
s = splcam();
/* Hook up our interrupt handler */
if ((error = bus_setup_intr(adw->device, adw->irq, INTR_TYPE_CAM,
adw_intr, adw, &adw->ih)) != 0) {
device_printf(adw->device, "bus_setup_intr() failed: %d\n",
error);
goto fail;
}
/* Start the Risc processor now that we are fully configured. */
adw_outw(adw, ADW_RISC_CSR, ADW_RISC_CSR_RUN);
@ -1049,22 +1189,25 @@ adw_attach(struct adw_softc *adw)
*/
devq = cam_simq_alloc(adw->max_acbs);
if (devq == NULL)
return (0);
return (ENOMEM);
/*
* Construct our SIM entry.
*/
adw->sim = cam_sim_alloc(adw_action, adw_poll, "adw", adw, adw->unit,
1, adw->max_acbs, devq);
if (adw->sim == NULL)
return (0);
if (adw->sim == NULL) {
error = ENOMEM;
goto fail;
}
/*
* Register the bus.
*/
if (xpt_bus_register(adw->sim, 0) != CAM_SUCCESS) {
cam_sim_free(adw->sim, /*free devq*/TRUE);
return (0);
error = ENOMEM;
goto fail;
}
if (xpt_create_path(&adw->path, /*periph*/NULL, cam_sim_path(adw->sim),
@ -1078,7 +1221,9 @@ adw_attach(struct adw_softc *adw)
xpt_action((union ccb *)&csa);
}
return (0);
fail:
splx(s);
return (error);
}
void
@ -1086,9 +1231,6 @@ adw_intr(void *arg)
{
struct adw_softc *adw;
u_int int_stat;
u_int next_doneq;
u_int next_completeq;
u_int doneq_start;
adw = (struct adw_softc *)arg;
if ((adw_inw(adw, ADW_CTRL_REG) & ADW_CTRL_REG_HOST_INTR) == 0)
@ -1098,61 +1240,80 @@ adw_intr(void *arg)
int_stat = adw_inb(adw, ADW_INTR_STATUS_REG);
if ((int_stat & ADW_INTR_STATUS_INTRB) != 0) {
/* Idle Command Complete */
adw->idle_command_cmp = 1;
switch (adw->idle_cmd) {
case ADW_IDLE_CMD_DEVICE_RESET:
adw_handle_device_reset(adw,
/*target*/adw->idle_cmd_param);
u_int intrb_code;
/* Async Microcode Event */
intrb_code = adw_lram_read_8(adw, ADW_MC_INTRB_CODE);
switch (intrb_code) {
case ADW_ASYNC_CARRIER_READY_FAILURE:
/*
* The RISC missed our update of
* the commandq.
*/
if (LIST_FIRST(&adw->pending_ccbs) != NULL)
adw_tickle_risc(adw, ADW_TICKLE_A);
break;
case ADW_IDLE_CMD_SCSI_RESET:
case ADW_ASYNC_SCSI_BUS_RESET_DET:
/*
* The firmware detected a SCSI Bus reset.
*/
printf("Someone Reset the Bus\n");
adw_handle_bus_reset(adw, /*initiated*/FALSE);
break;
case ADW_ASYNC_RDMA_FAILURE:
/*
* Handle RDMA failure by resetting the
* SCSI Bus and chip.
*/
#if XXX
AdvResetChipAndSB(adv_dvc_varp);
#endif
break;
case ADW_ASYNC_HOST_SCSI_BUS_RESET:
/*
* Host generated SCSI bus reset occurred.
*/
adw_handle_bus_reset(adw, /*initiated*/TRUE);
break;
default:
break;
default:
printf("adw_intr: unknown async code 0x%x\n",
intrb_code);
break;
}
adw->idle_cmd = ADW_IDLE_CMD_COMPLETED;
}
if ((int_stat & ADW_INTR_STATUS_INTRC) != 0) {
/* SCSI Bus Reset */
adw_handle_bus_reset(adw, /*initiated*/FALSE);
}
/*
* ADW_MC_HOST_NEXT_DONE is actually the last completed RISC
* Queue List request. Its forward pointer (RQL_FWD) points to the
* current completed RISC Queue List request.
* Run down the RequestQ.
*/
next_doneq = adw_lram_read_8(adw, ADW_MC_HOST_NEXT_DONE);
next_doneq = ADW_MC_RISC_Q_LIST_BASE + RQL_FWD
+ (next_doneq * ADW_MC_RISC_Q_LIST_SIZE);
while ((adw->responseq->next_ba & ADW_RQ_DONE) != 0) {
struct adw_carrier *free_carrier;
struct acb *acb;
union ccb *ccb;
next_completeq = adw_lram_read_8(adw, next_doneq);
doneq_start = ADW_MC_NULL_Q;
/* Loop until all completed Q's are processed. */
while (next_completeq != ADW_MC_NULL_Q) {
u_int32_t acb_busaddr;
struct acb *acb;
union ccb *ccb;
doneq_start = next_completeq;
next_doneq = ADW_MC_RISC_Q_LIST_BASE +
(next_completeq * ADW_MC_RISC_Q_LIST_SIZE);
#if 0
printf("0x%x, 0x%x, 0x%x, 0x%x\n",
adw->responseq->carr_offset,
adw->responseq->carr_ba,
adw->responseq->areq_ba,
adw->responseq->next_ba);
#endif
/*
* The firmware copies the adw_scsi_req_q.acb_baddr
* field into the areq_ba field of the carrier.
*/
acb = acbbotov(adw, adw->responseq->areq_ba);
/*
* Read the ADW_SCSI_REQ_Q physical address pointer from
* the RISC list entry.
* The least significant four bits of the next_ba
* field are used as flags. Mask them out and then
* advance through the list.
*/
acb_busaddr = adw_lram_read_32(adw, next_doneq + RQL_PHYADDR);
acb = acbptov(adw, acb_busaddr);
/* Change the RISC Queue List state to free. */
adw_lram_write_8(adw, next_doneq + RQL_STATE, ADW_MC_QS_FREE);
/* Get the RISC Queue List forward pointer. */
next_completeq = adw_lram_read_8(adw, next_doneq + RQL_FWD);
free_carrier = adw->responseq;
adw->responseq =
carrierbotov(adw, free_carrier->next_ba & ADW_NEXT_BA_MASK);
free_carrier->next_ba = adw->free_carriers->carr_offset;
adw->free_carriers = free_carrier;
/* Process CCB */
ccb = acb->ccb;
@ -1195,14 +1356,10 @@ adw_intr(void *arg)
}
adwfreeacb(adw, acb);
xpt_done(ccb);
} else {
adwprocesserror(adw, acb);
}
}
if (doneq_start != ADW_MC_NULL_Q)
adw_lram_write_8(adw, ADW_MC_HOST_NEXT_DONE, doneq_start);
}
static void
@ -1239,11 +1396,26 @@ adwprocesserror(struct adw_softc *adw, struct acb *acb)
break;
case QHSTA_M_WTM_TIMEOUT:
case QHSTA_M_SXFR_WD_TMO:
{
adw_idle_cmd_status_t status;
/* The SCSI bus hung in a phase */
ccb->ccb_h.status = CAM_SEQUENCE_FAIL;
adw_idle_cmd_send(adw, ADW_IDLE_CMD_SCSI_RESET,
adw_idle_cmd_send(adw, ADW_IDLE_CMD_SCSI_RESET_START,
/*param*/0);
status = adw_idle_cmd_wait(adw);
if (status != ADW_IDLE_CMD_SUCCESS)
panic("%s: Bus Reset during WD timeout failed",
adw_name(adw));
DELAY(100);
adw_idle_cmd_send(adw, ADW_IDLE_CMD_SCSI_RESET_END,
/*param*/0);
status = adw_idle_cmd_wait(adw);
if (status != ADW_IDLE_CMD_SUCCESS)
panic("%s: Bus Reset during WD timeout failed",
adw_name(adw));
break;
}
case QHSTA_M_SXFR_XFR_PH_ERR:
ccb->ccb_h.status = CAM_SEQUENCE_FAIL;
break;
@ -1314,8 +1486,17 @@ adwtimeout(void *arg)
if (status == ADW_IDLE_CMD_SUCCESS) {
printf("%s: BDR Delivered. No longer in timeout\n",
adw_name(adw));
adw_handle_device_reset(adw, ccb->ccb_h.target_id);
} else {
adw_idle_cmd_send(adw, ADW_IDLE_CMD_SCSI_RESET, /*param*/0);
adw_idle_cmd_send(adw, ADW_IDLE_CMD_SCSI_RESET_START,
/*param*/0);
status = adw_idle_cmd_wait(adw);
if (status != ADW_IDLE_CMD_SUCCESS)
panic("%s: Bus Reset during timeout failed",
adw_name(adw));
DELAY(100);
adw_idle_cmd_send(adw, ADW_IDLE_CMD_SCSI_RESET_END,
/*param*/0);
status = adw_idle_cmd_wait(adw);
if (status != ADW_IDLE_CMD_SUCCESS)
panic("%s: Bus Reset during timeout failed",

661
sys/dev/advansys/adwlib.c
View File

@ -2,7 +2,7 @@
* Low level routines for Second Generation
* Advanced Systems Inc. SCSI controllers chips
*
* Copyright (c) 1998 Justin Gibbs.
* Copyright (c) 1998, 1999, 2000 Justin Gibbs.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -10,7 +10,7 @@
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification, immediately at the beginning of the file.
* without modification.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
@ -46,6 +46,7 @@
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <machine/bus_pio.h>
#include <machine/bus_memio.h>
@ -57,57 +58,116 @@
#include <dev/advansys/adwlib.h>
struct adw_eeprom adw_default_eeprom = {
ADW_EEPROM_BIOS_ENABLE, /* cfg_lsw */
0x0000, /* cfg_msw */
0xFFFF, /* disc_enable */
0xFFFF, /* wdtr_able */
0xFFFF, /* sdtr_able */
0xFFFF, /* start_motor */
0xFFFF, /* tagqng_able */
0xFFFF, /* bios_scan */
0, /* scam_tolerant */
7, /* adapter_scsi_id */
0, /* bios_boot_delay */
3, /* scsi_reset_delay */
0, /* bios_id_lun */
0, /* termination */
0, /* reserved1 */
{ /* Bios Ctrl */
1, 1, 1, 1, 1,
1, 1, 1, 1, 1,
},
0xFFFF, /* ultra_able */
0, /* reserved2 */
ADW_DEF_MAX_HOST_QNG, /* max_host_qng */
ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */
0, /* dvc_cntl */
0, /* bug_fix */
{ 0, 0, 0 }, /* serial_number */
0, /* check_sum */
{ /* oem_name[16] */
const struct adw_eeprom adw_asc3550_default_eeprom =
{
ADW_EEPROM_BIOS_ENABLE, /* cfg_lsw */
0x0000, /* cfg_msw */
0xFFFF, /* disc_enable */
0xFFFF, /* wdtr_able */
{ 0xFFFF }, /* sdtr_able */
0xFFFF, /* start_motor */
0xFFFF, /* tagqng_able */
0xFFFF, /* bios_scan */
0, /* scam_tolerant */
7, /* adapter_scsi_id */
0, /* bios_boot_delay */
3, /* scsi_reset_delay */
0, /* bios_id_lun */
0, /* termination */
0, /* reserved1 */
0xFFE7, /* bios_ctrl */
{ 0xFFFF }, /* ultra_able */
{ 0 }, /* reserved2 */
ADW_DEF_MAX_HOST_QNG, /* max_host_qng */
ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */
0, /* dvc_cntl */
{ 0 }, /* bug_fix */
{ 0, 0, 0 }, /* serial_number */
0, /* check_sum */
{ /* oem_name[16] */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0
},
0, /* dvc_err_code */
0, /* adv_err_code */
0, /* adv_err_addr */
0, /* saved_dvc_err_code */
0, /* saved_adv_err_code */
0, /* saved_adv_err_addr */
0 /* num_of_err */
0, /* dvc_err_code */
0, /* adv_err_code */
0, /* adv_err_addr */
0, /* saved_dvc_err_code */
0, /* saved_adv_err_code */
0 /* saved_adv_err_addr */
};
const struct adw_eeprom adw_asc38C0800_default_eeprom =
{
ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
0x0000, /* 01 cfg_msw */
0xFFFF, /* 02 disc_enable */
0xFFFF, /* 03 wdtr_able */
{ 0x4444 }, /* 04 sdtr_speed1 */
0xFFFF, /* 05 start_motor */
0xFFFF, /* 06 tagqng_able */
0xFFFF, /* 07 bios_scan */
0, /* 08 scam_tolerant */
7, /* 09 adapter_scsi_id */
0, /* bios_boot_delay */
3, /* 10 scsi_reset_delay */
0, /* bios_id_lun */
0, /* 11 termination_se */
0, /* termination_lvd */
0xFFE7, /* 12 bios_ctrl */
{ 0x4444 }, /* 13 sdtr_speed2 */
{ 0x4444 }, /* 14 sdtr_speed3 */
ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */
0, /* 16 dvc_cntl */
{ 0x4444 } , /* 17 sdtr_speed4 */
{ 0, 0, 0 }, /* 18-20 serial_number */
0, /* 21 check_sum */
{ /* 22-29 oem_name[16] */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0
},
0, /* 30 dvc_err_code */
0, /* 31 adv_err_code */
0, /* 32 adv_err_addr */
0, /* 33 saved_dvc_err_code */
0, /* 34 saved_adv_err_code */
0, /* 35 saved_adv_err_addr */
{ /* 36 - 55 reserved */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
},
0, /* 56 cisptr_lsw */
0, /* 57 cisprt_msw */
/* 58-59 sub-id */
(PCI_ID_ADVANSYS_38C0800_REV1 & PCI_ID_DEV_VENDOR_MASK) >> 32,
};
#define ADW_MC_SDTR_OFFSET_ULTRA2_DT 0
#define ADW_MC_SDTR_OFFSET_ULTRA2 1
#define ADW_MC_SDTR_OFFSET_ULTRA 2
const struct adw_syncrate adw_syncrates[] =
{
/* mc_sdtr period rate */
{ ADW_MC_SDTR_80, 9, "80.0" },
{ ADW_MC_SDTR_40, 10, "40.0" },
{ ADW_MC_SDTR_20, 12, "20.0" },
{ ADW_MC_SDTR_10, 25, "10.0" },
{ ADW_MC_SDTR_5, 50, "5.0" },
{ ADW_MC_SDTR_ASYNC, 0, "async" }
};
const int adw_num_syncrates = sizeof(adw_syncrates) / sizeof(adw_syncrates[0]);
static u_int16_t adw_eeprom_read_16(struct adw_softc *adw, int addr);
static void adw_eeprom_write_16(struct adw_softc *adw, int addr,
u_int data);
static void adw_eeprom_wait(struct adw_softc *adw);
int
adw_find_signature(bus_space_tag_t tag, bus_space_handle_t bsh)
adw_find_signature(struct adw_softc *adw)
{
if (bus_space_read_1(tag, bsh, ADW_SIGNATURE_BYTE) == ADW_CHIP_ID_BYTE
&& bus_space_read_2(tag, bsh, ADW_SIGNATURE_WORD) == ADW_CHIP_ID_WORD)
if (adw_inb(adw, ADW_SIGNATURE_BYTE) == ADW_CHIP_ID_BYTE
&& adw_inw(adw, ADW_SIGNATURE_WORD) == ADW_CHIP_ID_WORD)
return (1);
return (0);
}
@ -119,24 +179,14 @@ void
adw_reset_chip(struct adw_softc *adw)
{
adw_outw(adw, ADW_CTRL_REG, ADW_CTRL_REG_CMD_RESET);
DELAY(100);
DELAY(1000 * 100);
adw_outw(adw, ADW_CTRL_REG, ADW_CTRL_REG_CMD_WR_IO_REG);
/*
* Initialize Chip registers.
*/
adw_outb(adw, ADW_MEM_CFG,
adw_inb(adw, ADW_MEM_CFG) | ADW_MEM_CFG_RAM_SZ_8KB);
adw_outw(adw, ADW_SCSI_CFG1,
adw_inw(adw, ADW_SCSI_CFG1) & ~ADW_SCSI_CFG1_BIG_ENDIAN);
/*
* Setting the START_CTL_EM_FU 3:2 bits sets a FIFO threshold
* of 128 bytes. This register is only accessible to the host.
*/
adw_outb(adw, ADW_DMA_CFG0,
ADW_DMA_CFG0_START_CTL_EM_FU|ADW_DMA_CFG0_READ_CMD_MRM);
}
/*
@ -256,13 +306,17 @@ adw_eeprom_write(struct adw_softc *adw, struct adw_eeprom *eep_buf)
int
adw_init_chip(struct adw_softc *adw, u_int term_scsicfg1)
{
u_int8_t biosmem[ADW_MC_BIOSLEN];
u_int16_t *mcodebuf;
u_int addr;
u_int end_addr;
u_int checksum;
u_int scsicfg1;
u_int i;
u_int8_t biosmem[ADW_MC_BIOSLEN];
const u_int16_t *word_table;
const u_int8_t *byte_codes;
const u_int8_t *byte_codes_end;
u_int bios_sig;
u_int bytes_downloaded;
u_int addr;
u_int end_addr;
u_int checksum;
u_int scsicfg1;
u_int tid;
/*
* Save the RISC memory BIOS region before writing the microcode.
@ -273,19 +327,114 @@ adw_init_chip(struct adw_softc *adw, u_int term_scsicfg1)
biosmem[addr] = adw_lram_read_8(adw, ADW_MC_BIOSMEM + addr);
/*
* Load the Microcode. Casting here was less work than
* reformatting the supplied microcode into an array of
* 16bit values...
* Save current per TID negotiated values if the BIOS has been
* loaded (BIOS signature is present). These will be used if
* we cannot get information from the EEPROM.
*/
mcodebuf = (u_int16_t *)adw_mcode;
addr = ADW_MC_BIOS_SIGNATURE - ADW_MC_BIOSMEM;
bios_sig = biosmem[addr]
| (biosmem[addr + 1] << 8);
if (bios_sig == 0x55AA
&& (adw->flags & ADW_EEPROM_FAILED) != 0) {
u_int major_ver;
u_int minor_ver;
u_int sdtr_able;
addr = ADW_MC_BIOS_VERSION - ADW_MC_BIOSMEM;
minor_ver = biosmem[addr + 1] & 0xF;
major_ver = (biosmem[addr + 1] >> 4) & 0xF;
if ((adw->chip == ADW_CHIP_ASC3550)
&& (major_ver <= 3
|| (major_ver == 3 && minor_ver == 1))) {
/*
* BIOS 3.1 and earlier location of
* 'wdtr_able' variable.
*/
adw->user_wdtr =
adw_lram_read_16(adw, ADW_MC_WDTR_ABLE_BIOS_31);
} else {
adw->user_wdtr =
adw_lram_read_16(adw, ADW_MC_WDTR_ABLE);
}
sdtr_able = adw_lram_read_16(adw, ADW_MC_SDTR_ABLE);
for (tid = 0; tid < ADW_MAX_TID; tid++) {
u_int tid_mask;
u_int mc_sdtr;
tid_mask = 0x1 << tid;
if ((sdtr_able & tid_mask) == 0)
mc_sdtr = ADW_MC_SDTR_ASYNC;
else if ((adw->features & ADW_DT) != 0)
mc_sdtr = ADW_MC_SDTR_80;
else if ((adw->features & ADW_ULTRA2) != 0)
mc_sdtr = ADW_MC_SDTR_40;
else
mc_sdtr = ADW_MC_SDTR_20;
adw_set_user_sdtr(adw, tid, mc_sdtr);
}
adw->user_tagenb = adw_lram_read_16(adw, ADW_MC_TAGQNG_ABLE);
}
/*
* Load the Microcode.
*
* Assume the following compressed format of the microcode buffer:
*
* 253 word (506 byte) table indexed by byte code followed
* by the following byte codes:
*
* 1-Byte Code:
* 00: Emit word 0 in table.
* 01: Emit word 1 in table.
* .
* FD: Emit word 253 in table.
*
* Multi-Byte Code:
* FD RESEVED
*
* FE WW WW: (3 byte code)
* Word to emit is the next word WW WW.
* FF BB WW WW: (4 byte code)
* Emit BB count times next word WW WW.
*
*/
bytes_downloaded = 0;
word_table = (const u_int16_t *)adw->mcode_data->mcode_buf;
byte_codes = (const u_int8_t *)&word_table[253];
byte_codes_end = adw->mcode_data->mcode_buf
+ adw->mcode_data->mcode_size;
adw_outw(adw, ADW_RAM_ADDR, 0);
for (addr = 0; addr < adw_mcode_size/2; addr++)
adw_outw(adw, ADW_RAM_DATA, mcodebuf[addr]);
while (byte_codes < byte_codes_end) {
if (*byte_codes == 0xFF) {
u_int16_t value;
value = byte_codes[2]
| byte_codes[3] << 8;
adw_set_multi_2(adw, ADW_RAM_DATA,
value, byte_codes[1]);
bytes_downloaded += byte_codes[1];
byte_codes += 4;
} else if (*byte_codes == 0xFE) {
u_int16_t value;
value = byte_codes[1]
| byte_codes[2] << 8;
adw_outw(adw, ADW_RAM_DATA, value);
bytes_downloaded++;
byte_codes += 3;
} else {
adw_outw(adw, ADW_RAM_DATA, word_table[*byte_codes]);
bytes_downloaded++;
byte_codes++;
}
}
/* Convert from words to bytes */
bytes_downloaded *= 2;
/*
* Clear the rest of LRAM.
*/
for (; addr < ADW_CONDOR_MEMSIZE/2; addr++)
for (addr = bytes_downloaded; addr < adw->memsize; addr += 2)
adw_outw(adw, ADW_RAM_DATA, 0);
/*
@ -293,12 +442,12 @@ adw_init_chip(struct adw_softc *adw, u_int term_scsicfg1)
*/
checksum = 0;
adw_outw(adw, ADW_RAM_ADDR, 0);
for (addr = 0; addr < adw_mcode_size/2; addr++)
for (addr = 0; addr < bytes_downloaded; addr += 2)
checksum += adw_inw(adw, ADW_RAM_DATA);
if (checksum != adw_mcode_chksum) {
if (checksum != adw->mcode_data->mcode_chksum) {
printf("%s: Firmware load failed!\n", adw_name(adw));
return (-1);
return (EIO);
}
/*
@ -311,27 +460,36 @@ adw_init_chip(struct adw_softc *adw, u_int term_scsicfg1)
* Calculate and write the microcode code checksum to
* the microcode code checksum location.
*/
addr = adw_lram_read_16(adw, ADW_MC_CODE_BEGIN_ADDR) / 2;
end_addr = adw_lram_read_16(adw, ADW_MC_CODE_END_ADDR) / 2;
addr = adw_lram_read_16(adw, ADW_MC_CODE_BEGIN_ADDR);
end_addr = adw_lram_read_16(adw, ADW_MC_CODE_END_ADDR);
checksum = 0;
for (; addr < end_addr; addr++)
checksum += mcodebuf[addr];
adw_outw(adw, ADW_RAM_ADDR, addr);
for (; addr < end_addr; addr += 2)
checksum += adw_inw(adw, ADW_RAM_DATA);
adw_lram_write_16(adw, ADW_MC_CODE_CHK_SUM, checksum);
/*
* Initialize microcode operating variables
* Tell the microcode what kind of chip it's running on.
*/
adw_lram_write_16(adw, ADW_MC_ADAPTER_SCSI_ID, adw->initiator_id);
adw_lram_write_16(adw, ADW_MC_CHIP_TYPE, adw->chip);
/*
* Leave WDTR and SDTR negotiation disabled until the XPT has
* informed us of device capabilities, but do set the ultra mask
* in case we receive an SDTR request from the target before we
* negotiate. We turn on tagged queuing at the microcode level
* for all devices, and modulate this on a per command basis.
* informed us of device capabilities, but do set the desired
* user rates in case we receive an SDTR request from the target
* before we negotiate. We turn on tagged queuing at the microcode
* level for all devices, and modulate this on a per command basis.
*/
adw_lram_write_16(adw, ADW_MC_ULTRA_ABLE, adw->user_ultra);
adw_lram_write_16(adw, ADW_MC_SDTR_SPEED1, adw->user_sdtr[0]);
adw_lram_write_16(adw, ADW_MC_SDTR_SPEED2, adw->user_sdtr[1]);
adw_lram_write_16(adw, ADW_MC_SDTR_SPEED3, adw->user_sdtr[2]);
adw_lram_write_16(adw, ADW_MC_SDTR_SPEED4, adw->user_sdtr[3]);
adw_lram_write_16(adw, ADW_MC_DISC_ENABLE, adw->user_discenb);
for (tid = 0; tid < ADW_MAX_TID; tid++) {
/* Cam limits the maximum number of commands for us */
adw_lram_write_8(adw, ADW_MC_NUMBER_OF_MAX_CMD + tid,
adw->max_acbs);
}
adw_lram_write_16(adw, ADW_MC_TAGQNG_ABLE, ~0);
/*
@ -343,7 +501,14 @@ adw_init_chip(struct adw_softc *adw, u_int term_scsicfg1)
adw_lram_write_16(adw, ADW_MC_DEFAULT_SCSI_CFG0,
ADW_SCSI_CFG0_PARITY_EN|ADW_SCSI_CFG0_SEL_TMO_LONG|
ADW_SCSI_CFG0_OUR_ID_EN|adw->initiator_id);
/*
* Tell the MC about the memory size that
* was setup by the probe code.
*/
adw_lram_write_16(adw, ADW_MC_DEFAULT_MEM_CFG,
adw_inb(adw, ADW_MEM_CFG) & ADW_MEM_CFG_RAM_SZ_MASK);
/*
* Determine SCSI_CFG1 Microcode Default Value.
*
@ -352,17 +517,6 @@ adw_init_chip(struct adw_softc *adw, u_int term_scsicfg1)
*/
scsicfg1 = adw_inw(adw, ADW_SCSI_CFG1);
/*
* If all three connectors are in use, return an error.
*/
if ((scsicfg1 & ADW_SCSI_CFG1_ILLEGAL_CABLE_CONF_A_MASK) == 0
|| (scsicfg1 & ADW_SCSI_CFG1_ILLEGAL_CABLE_CONF_B_MASK) == 0) {
printf("%s: Illegal Cable Config!\n", adw_name(adw));
printf("%s: Only Two Ports may be used at a time!\n",
adw_name(adw));
return (-1);
}
/*
* If the internal narrow cable is reversed all of the SCSI_CTRL
* register signals will be set. Check for and return an error if
@ -371,91 +525,168 @@ adw_init_chip(struct adw_softc *adw, u_int term_scsicfg1)
if ((adw_inw(adw, ADW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
printf("%s: Illegal Cable Config!\n", adw_name(adw));
printf("%s: Internal cable is reversed!\n", adw_name(adw));
return (-1);
return (EIO);
}
/*
* If this is a differential board and a single-ended device
* is attached to one of the connectors, return an error.
*/
if ((scsicfg1 & ADW_SCSI_CFG1_DIFF_MODE) != 0
&& (scsicfg1 & ADW_SCSI_CFG1_DIFF_SENSE) == 0) {
printf("%s: A Single Ended Device is attached to our "
"differential bus!\n", adw_name(adw));
return (-1);
if ((adw->features & ADW_ULTRA) != 0) {
if ((scsicfg1 & ADW_SCSI_CFG1_DIFF_MODE) != 0
&& (scsicfg1 & ADW_SCSI_CFG1_DIFF_SENSE) == 0) {
printf("%s: A Single Ended Device is attached to our "
"differential bus!\n", adw_name(adw));
return (EIO);
}
} else {
if ((scsicfg1 & ADW2_SCSI_CFG1_DEV_DETECT_HVD) != 0) {
printf("%s: A High Voltage Differential Device "
"is attached to this controller.\n",
adw_name(adw));
printf("%s: HVD devices are not supported.\n",
adw_name(adw));
return (EIO);
}
}
/*
* Perform automatic termination control if desired.
*/
if (term_scsicfg1 == 0) {
switch(scsicfg1 & ADW_SCSI_CFG1_CABLE_DETECT) {
case (ADW_SCSI_CFG1_INT16_MASK|ADW_SCSI_CFG1_INT8_MASK):
case (ADW_SCSI_CFG1_INT16_MASK|
ADW_SCSI_CFG1_INT8_MASK|ADW_SCSI_CFG1_EXT8_MASK):
case (ADW_SCSI_CFG1_INT16_MASK|
ADW_SCSI_CFG1_INT8_MASK|ADW_SCSI_CFG1_EXT16_MASK):
case (ADW_SCSI_CFG1_INT16_MASK|
ADW_SCSI_CFG1_EXT8_MASK|ADW_SCSI_CFG1_EXT16_MASK):
case (ADW_SCSI_CFG1_INT8_MASK|
ADW_SCSI_CFG1_EXT8_MASK|ADW_SCSI_CFG1_EXT16_MASK):
case (ADW_SCSI_CFG1_INT16_MASK|ADW_SCSI_CFG1_INT8_MASK|
ADW_SCSI_CFG1_EXT8_MASK|ADW_SCSI_CFG1_EXT16_MASK):
/* Two out of three cables missing. Both on. */
term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_L
| ADW_SCSI_CFG1_TERM_CTL_H;
break;
case (ADW_SCSI_CFG1_INT16_MASK):
case (ADW_SCSI_CFG1_INT16_MASK|ADW_SCSI_CFG1_EXT8_MASK):
case (ADW_SCSI_CFG1_INT16_MASK|ADW_SCSI_CFG1_EXT16_MASK):
case (ADW_SCSI_CFG1_INT8_MASK|ADW_SCSI_CFG1_EXT16_MASK):
case (ADW_SCSI_CFG1_EXT8_MASK|ADW_SCSI_CFG1_EXT16_MASK):
/* No two 16bit cables present. High on. */
if ((adw->features & ADW_ULTRA2) != 0) {
u_int cable_det;
/*
* Ultra2 Chips require termination disabled to
* detect cable presence.
*/
adw_outw(adw, ADW_SCSI_CFG1,
scsicfg1 | ADW2_SCSI_CFG1_DIS_TERM_DRV);
cable_det = adw_inw(adw, ADW_SCSI_CFG1);
adw_outw(adw, ADW_SCSI_CFG1, scsicfg1);
/* SE Termination first if auto-term has been specified */
if ((term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) == 0) {
/*
* For all SE cable configurations, high byte
* termination is enabled.
*/
term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H;
break;
case (ADW_SCSI_CFG1_INT8_MASK):
case (ADW_SCSI_CFG1_INT8_MASK|ADW_SCSI_CFG1_EXT8_MASK):
/* Wide -> Wide or Narrow -> Wide. Both off */
break;
if ((cable_det & ADW_SCSI_CFG1_INT8_MASK) != 0
|| (cable_det & ADW_SCSI_CFG1_INT16_MASK) != 0) {
/*
* If either cable is not present, the
* low byte must be terminated as well.
*/
term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_L;
}
}
/* LVD auto-term */
if ((term_scsicfg1 & ADW2_SCSI_CFG1_TERM_CTL_LVD) == 0
&& (term_scsicfg1 & ADW2_SCSI_CFG1_DIS_TERM_DRV) == 0) {
/*
* If both cables are installed, termination
* is disabled. Otherwise it is enabled.
*/
if ((cable_det & ADW2_SCSI_CFG1_EXTLVD_MASK) != 0
|| (cable_det & ADW2_SCSI_CFG1_INTLVD_MASK) != 0) {
term_scsicfg1 |= ADW2_SCSI_CFG1_TERM_CTL_LVD;
}
}
term_scsicfg1 &= ~ADW2_SCSI_CFG1_DIS_TERM_DRV;
} else {
/* Ultra Controller Termination */
if ((term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) == 0) {
int cable_count;
int wide_cable_count;
cable_count = 0;
wide_cable_count = 0;
if ((scsicfg1 & ADW_SCSI_CFG1_INT16_MASK) == 0) {
cable_count++;
wide_cable_count++;
}
if ((scsicfg1 & ADW_SCSI_CFG1_INT8_MASK) == 0)
cable_count++;
/* There is only one external port */
if ((scsicfg1 & ADW_SCSI_CFG1_EXT16_MASK) == 0) {
cable_count++;
wide_cable_count++;
} else if ((scsicfg1 & ADW_SCSI_CFG1_EXT8_MASK) == 0)
cable_count++;
if (cable_count == 3) {
printf("%s: Illegal Cable Config!\n",
adw_name(adw));
printf("%s: Only Two Ports may be used at "
"a time!\n", adw_name(adw));
} else if (cable_count <= 1) {
/*
* At least two out of three cables missing.
* Terminate both bytes.
*/
term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H
| ADW_SCSI_CFG1_TERM_CTL_L;
} else if (wide_cable_count <= 1) {
/* No two 16bit cables present. High on. */
term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H;
}
}
}
/* Tell the user about our decission */
switch (term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) {
case ADW_SCSI_CFG1_TERM_CTL_MASK:
printf("High & Low Termination Enabled, ");
printf("High & Low SE Term Enabled, ");
break;
case ADW_SCSI_CFG1_TERM_CTL_H:
printf("High Termination Enabled, ");
printf("High SE Termination Enabled, ");
break;
case ADW_SCSI_CFG1_TERM_CTL_L:
printf("Low Termination Enabled, ");
printf("Low SE Term Enabled, ");
break;
default:
break;
}
if ((adw->features & ADW_ULTRA2) != 0
&& (term_scsicfg1 & ADW2_SCSI_CFG1_TERM_CTL_LVD) != 0)
printf("LVD Term Enabled, ");
/*
* Invert the TERM_CTL_H and TERM_CTL_L bits and then
* set 'scsicfg1'. The TERM_POL bit does not need to be
* referenced, because the hardware internally inverts
* the Termination High and Low bits if TERM_POL is set.
*/
term_scsicfg1 = ~term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK;
scsicfg1 &= ~ADW_SCSI_CFG1_TERM_CTL_MASK;
scsicfg1 |= term_scsicfg1 | ADW_SCSI_CFG1_TERM_CTL_MANUAL;
if ((adw->features & ADW_ULTRA2) != 0) {
term_scsicfg1 = ~term_scsicfg1;
term_scsicfg1 &= ADW_SCSI_CFG1_TERM_CTL_MASK
| ADW2_SCSI_CFG1_TERM_CTL_LVD;
scsicfg1 &= ~(ADW_SCSI_CFG1_TERM_CTL_MASK
|ADW2_SCSI_CFG1_TERM_CTL_LVD
|ADW_SCSI_CFG1_BIG_ENDIAN
|ADW_SCSI_CFG1_TERM_POL
|ADW2_SCSI_CFG1_DEV_DETECT);
scsicfg1 |= term_scsicfg1;
} else {
term_scsicfg1 = ~term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK;
scsicfg1 &= ~ADW_SCSI_CFG1_TERM_CTL_MASK;
scsicfg1 |= term_scsicfg1 | ADW_SCSI_CFG1_TERM_CTL_MANUAL;
scsicfg1 |= ADW_SCSI_CFG1_FLTR_DISABLE;
}
/*
* Set SCSI_CFG1 Microcode Default Value
*
* Set filter value and possibly modified termination control
* bits in the Microcode SCSI_CFG1 Register Value.
*
* The microcode will set the SCSI_CFG1 register using this value
* after it is started below.
*/
adw_lram_write_16(adw, ADW_MC_DEFAULT_SCSI_CFG1,
scsicfg1 | ADW_SCSI_CFG1_FLTR_11_TO_20NS);
adw_lram_write_16(adw, ADW_MC_DEFAULT_SCSI_CFG1, scsicfg1);
/*
* Only accept selections on our initiator target id.
@ -465,42 +696,24 @@ adw_init_chip(struct adw_softc *adw, u_int term_scsicfg1)
(0x01 << adw->initiator_id));
/*
* Link all the RISC Queue Lists together in a doubly-linked
* NULL terminated list.
*
* Skip the NULL (0) queue which is not used.
* Tell the microcode where it can find our
* Initiator Command Queue (ICQ). It is
* currently empty hence the "stopper" address.
*/
for (i = 1, addr = ADW_MC_RISC_Q_LIST_BASE + ADW_MC_RISC_Q_LIST_SIZE;
i < ADW_MC_RISC_Q_TOTAL_CNT;
i++, addr += ADW_MC_RISC_Q_LIST_SIZE) {
/*
* Set the current RISC Queue List's
* RQL_FWD and RQL_BWD pointers in a
* one word write and set the state
* (RQL_STATE) to free.
*/
adw_lram_write_16(adw, addr, ((i + 1) | ((i - 1) << 8)));
adw_lram_write_8(adw, addr + RQL_STATE, ADW_MC_QS_FREE);
}
adw->commandq = adw->free_carriers;
adw->free_carriers = carrierbotov(adw, adw->commandq->next_ba);
adw->commandq->next_ba = ADW_CQ_STOPPER;
adw_lram_write_32(adw, ADW_MC_ICQ, adw->commandq->carr_ba);
/*
* Set the Host and RISC Queue List pointers.
*
* Both sets of pointers are initialized with the same values:
* ADW_MC_RISC_Q_FIRST(0x01) and ADW_MC_RISC_Q_LAST (0xFF).
* Tell the microcode where it can find our
* Initiator Response Queue (IRQ). It too
* is currently empty.
*/
adw_lram_write_8(adw, ADW_MC_HOST_NEXT_READY, ADW_MC_RISC_Q_FIRST);
adw_lram_write_8(adw, ADW_MC_HOST_NEXT_DONE, ADW_MC_RISC_Q_LAST);
adw_lram_write_8(adw, ADW_MC_RISC_NEXT_READY, ADW_MC_RISC_Q_FIRST);
adw_lram_write_8(adw, ADW_MC_RISC_NEXT_DONE, ADW_MC_RISC_Q_LAST);
/*
* Set up the last RISC Queue List (255) with a NULL forward pointer.
*/
adw_lram_write_16(adw, addr, (ADW_MC_NULL_Q + ((i - 1) << 8)));
adw_lram_write_8(adw, addr + RQL_STATE, ADW_MC_QS_FREE);
adw->responseq = adw->free_carriers;
adw->free_carriers = carrierbotov(adw, adw->responseq->next_ba);
adw->responseq->next_ba = ADW_CQ_STOPPER;
adw_lram_write_32(adw, ADW_MC_IRQ, adw->responseq->carr_ba);
adw_outb(adw, ADW_INTR_ENABLES,
ADW_INTR_ENABLE_HOST_INTR|ADW_INTR_ENABLE_GLOBAL_INTR);
@ -510,6 +723,100 @@ adw_init_chip(struct adw_softc *adw, u_int term_scsicfg1)
return (0);
}
void
adw_set_user_sdtr(struct adw_softc *adw, u_int tid, u_int mc_sdtr)
{
adw->user_sdtr[ADW_TARGET_GROUP(tid)] &= ~ADW_TARGET_GROUP_MASK(tid);
adw->user_sdtr[ADW_TARGET_GROUP(tid)] |=
mc_sdtr << ADW_TARGET_GROUP_SHIFT(tid);
}
u_int
adw_get_user_sdtr(struct adw_softc *adw, u_int tid)
{
u_int mc_sdtr;
mc_sdtr = adw->user_sdtr[ADW_TARGET_GROUP(tid)];
mc_sdtr &= ADW_TARGET_GROUP_MASK(tid);
mc_sdtr >>= ADW_TARGET_GROUP_SHIFT(tid);
return (mc_sdtr);
}
void
adw_set_chip_sdtr(struct adw_softc *adw, u_int tid, u_int sdtr)
{
u_int mc_sdtr_offset;
u_int mc_sdtr;
mc_sdtr_offset = ADW_MC_SDTR_SPEED1;
mc_sdtr_offset += ADW_TARGET_GROUP(tid) * 2;
mc_sdtr = adw_lram_read_16(adw, mc_sdtr_offset);
mc_sdtr &= ~ADW_TARGET_GROUP_MASK(tid);
mc_sdtr |= sdtr << ADW_TARGET_GROUP_SHIFT(tid);
adw_lram_write_16(adw, mc_sdtr_offset, mc_sdtr);
}
u_int
adw_get_chip_sdtr(struct adw_softc *adw, u_int tid)
{
u_int mc_sdtr_offset;
u_int mc_sdtr;
mc_sdtr_offset = ADW_MC_SDTR_SPEED1;
mc_sdtr_offset += ADW_TARGET_GROUP(tid) * 2;
mc_sdtr = adw_lram_read_16(adw, mc_sdtr_offset);
mc_sdtr &= ADW_TARGET_GROUP_MASK(tid);
mc_sdtr >>= ADW_TARGET_GROUP_SHIFT(tid);
return (mc_sdtr);
}
u_int
adw_find_sdtr(struct adw_softc *adw, u_int period)
{
int i;
i = 0;
if ((adw->features & ADW_DT) == 0)
i = ADW_MC_SDTR_OFFSET_ULTRA2;
if ((adw->features & ADW_ULTRA2) == 0)
i = ADW_MC_SDTR_OFFSET_ULTRA;
if (period == 0)
return ADW_MC_SDTR_ASYNC;
for (; i < adw_num_syncrates; i++) {
if (period <= adw_syncrates[i].period)
return (adw_syncrates[i].mc_sdtr);
}
return ADW_MC_SDTR_ASYNC;
}
u_int
adw_find_period(struct adw_softc *adw, u_int mc_sdtr)
{
int i;
for (i = 0; i < adw_num_syncrates; i++) {
if (mc_sdtr == adw_syncrates[i].mc_sdtr)
break;
}
return (adw_syncrates[i].period);
}
u_int
adw_hshk_cfg_period_factor(u_int tinfo)
{
tinfo &= ADW_HSHK_CFG_RATE_MASK;
tinfo >>= ADW_HSHK_CFG_RATE_SHIFT;
if (tinfo == 0x11)
/* 80MHz/DT */
return (9);
else if (tinfo == 0x10)
/* 40MHz */
return (10);
else
return (((tinfo * 25) + 50) / 4);
}
/*
* Send an idle command to the chip and optionally wait for completion.
*/
@ -534,8 +841,13 @@ adw_idle_cmd_send(struct adw_softc *adw, adw_idle_cmd_t cmd, u_int parameter)
* followed, the microcode may process the idle command before the
* parameters have been written to LRAM.
*/
adw_lram_write_16(adw, ADW_MC_IDLE_PARA_STAT, parameter);
adw_lram_write_16(adw, ADW_MC_IDLE_CMD_PARAMETER, parameter);
adw_lram_write_16(adw, ADW_MC_IDLE_CMD, cmd);
/*
* Tickle the RISC to tell it to process the idle command.
*/
adw_tickle_risc(adw, ADW_TICKLE_B);
splx(s);
}
@ -550,15 +862,16 @@ adw_idle_cmd_wait(struct adw_softc *adw)
/* Wait for up to 10 seconds for the command to complete */
timeout = 10000;
while (--timeout) {
if (adw->idle_command_cmp != 0)
s = splcam();
status = adw_lram_read_16(adw, ADW_MC_IDLE_CMD_STATUS);
splx(s);
if (status != 0)
break;
DELAY(1000);
}
if (timeout == 0)
panic("%s: Idle Command Timed Out!\n", adw_name(adw));
s = splcam();
status = adw_lram_read_16(adw, ADW_MC_IDLE_PARA_STAT);
splx(s);
adw->idle_cmd = ADW_IDLE_CMD_COMPLETED;
return (status);
}

455
sys/dev/advansys/adwlib.h
View File

@ -2,7 +2,7 @@
* Definitions for low level routines and data structures
* for the Advanced Systems Inc. SCSI controllers chips.
*
* Copyright (c) 1998 Justin T. Gibbs.
* Copyright (c) 1998, 1999, 2000 Justin T. Gibbs.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -10,7 +10,7 @@
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification, immediately at the beginning of the file.
* without modification.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
@ -61,6 +61,12 @@
#define ADW_MAX_TID 15
#define ADW_MAX_LUN 7
#define ADW_ALL_TARGETS 0xFFFF
#define ADW_TARGET_GROUP(tid) ((tid) & ~0x3)
#define ADW_TARGET_GROUP_SHIFT(tid) (((tid) & 0x3) * 4)
#define ADW_TARGET_GROUP_MASK(tid) (0xF << ADW_TARGET_GROUP_SHIFT(tid))
/*
* Board Register offsets.
*/
@ -68,6 +74,7 @@
#define ADW_INTR_STATUS_INTRA 0x01
#define ADW_INTR_STATUS_INTRB 0x02
#define ADW_INTR_STATUS_INTRC 0x04
#define ADW_INTR_STATUS_INTRALL 0x07
#define ADW_SIGNATURE_WORD 0x0000
@ -164,6 +171,27 @@
#define ADW_SCSI_CFG1_ILLEGAL_CABLE_CONF_B_MASK \
(ADW_SCSI_CFG1_EXT8_MASK|ADW_SCSI_CFG1_INT8_MASK|ADW_SCSI_CFG1_INT16_MASK)
/*
* Addendum for ASC-38C0800 Chip
*/
#define ADW2_SCSI_CFG1_DIS_TERM_DRV 0x4000 /*
* The Terminators
* must be disabled
* in order to detect
* cable presence
*/
#define ADW2_SCSI_CFG1_DEV_DETECT 0x1C00
#define ADW2_SCSI_CFG1_DEV_DETECT_HVD 0x1000
#define ADW2_SCSI_CFG1_DEV_DETECT_LVD 0x0800
#define ADW2_SCSI_CFG1_DEV_DETECT_SE 0x0400
#define ADW2_SCSI_CFG1_TERM_CTL_LVD 0x00C0 /* Ultra2 Only */
#define ADW2_SCSI_CFG1_TERM_LVD_HI 0x0080
#define ADW2_SCSI_CFG1_TERM_LVD_LO 0x0040
#define ADW2_SCSI_CFG1_EXTLVD_MASK 0x0008 /* ExtLVD cable pres */
#define ADW2_SCSI_CFG1_INTLVD_MASK 0x0004 /* IntLVD cable pres */
#define ADW_MEM_CFG 0x0010
#define ADW_MEM_CFG_BIOS_EN 0x40
#define ADW_MEM_CFG_FAST_EE_CLK 0x20 /* Diagnostic Bit */
@ -175,6 +203,12 @@
#define ADW_MEM_CFG_RAM_SZ_32KB 0x10
#define ADW_MEM_CFG_RAM_SZ_64KB 0x14
#define ADW_GPIO_CNTL 0x0011
#define ADW_GPIO_DATA 0x0012
#define ADW_COMMA 0x0014
#define ADW_COMMB 0x0018
#define ADW_EEP_CMD 0x001A
#define ADW_EEP_CMD_READ 0x0080 /* or in address */
#define ADW_EEP_CMD_WRITE 0x0040 /* or in address */
@ -191,11 +225,11 @@
#define ADW_DMA_CFG0_FIFO_THRESH 0x70
#define ADW_DMA_CFG0_FIFO_THRESH_16B 0x00
#define ADW_DMA_CFG0_FIFO_THRESH_32B 0x20
#define ADW_DMA_CFG0_IFO_THRESH_48B 0x30
#define ADW_DMA_CFG0_IFO_THRESH_64B 0x40
#define ADW_DMA_CFG0_IFO_THRESH_80B 0x50
#define ADW_DMA_CFG0_IFO_THRESH_96B 0x60
#define ADW_DMA_CFG0_IFO_THRESH_112B 0x70
#define ADW_DMA_CFG0_FIFO_THRESH_48B 0x30
#define ADW_DMA_CFG0_FIFO_THRESH_64B 0x40
#define ADW_DMA_CFG0_FIFO_THRESH_80B 0x50
#define ADW_DMA_CFG0_FIFO_THRESH_96B 0x60
#define ADW_DMA_CFG0_FIFO_THRESH_112B 0x70
#define ADW_DMA_CFG0_START_CTL_MASK 0x0C
#define ADW_DMA_CFG0_START_CTL_TH 0x00 /* Start on thresh */
#define ADW_DMA_CFG0_START_CTL_IDLE 0x04 /* Start when idle */
@ -206,18 +240,57 @@
#define ADW_DMA_CFG0_READ_CMD_MRL 0x02
#define ADW_DMA_CFG0_READ_CMD_MRM 0x03
#define ADW_TICKLE 0x0022
#define ADW_TICKLE_NOP 0x00
#define ADW_TICKLE_A 0x01
#define ADW_TICKLE_B 0x02
#define ADW_TICKLE_C 0x03
/* Program Counter */
#define ADW_PC 0x2A
#define ADW_SCSI_CTRL 0x0034
#define ADW_SCSI_CTRL_RSTOUT 0x2000
/*
* ASC-38C0800 RAM BIST Register bit definitions
*/
#define ADW_RAM_BIST 0x0038
#define ADW_RAM_BIST_RAM_TEST_MODE 0x80
#define ADW_RAM_BIST_PRE_TEST_MODE 0x40
#define ADW_RAM_BIST_NORMAL_MODE 0x00
#define ADW_RAM_BIST_RAM_TEST_DONE 0x10
#define ADW_RAM_BIST_RAM_TEST_STATUS 0x0F
#define ADW_RAM_BIST_RAM_TEST_HOST_ERR 0x08
#define ADW_RAM_BIST_RAM_TEST_RAM_ERR 0x04
#define ADW_RAM_BIST_RAM_TEST_RISC_ERR 0x02
#define ADW_RAM_BIST_RAM_TEST_SCSI_ERR 0x01
#define ADW_RAM_BIST_RAM_TEST_SUCCESS 0x00
#define ADW_RAM_BIST_PRE_TEST_VALUE 0x05
#define ADW_RAM_BIST_NORMAL_VALUE 0x00
#define ADW_PLL_TEST 0x0039
#define ADW_SCSI_RESET_HOLD_TIME_US 60
/* LRAM Constants */
#define ADW_CONDOR_MEMSIZE 0x2000 /* 8 KB Internal Memory */
#define ADW_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
#define ADW_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
#define ADW_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
#define ADW_3550_IOLEN 0x40 /* I/O Port Range in bytes */
#define ADW_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
#define ADW_38C0800_IOLEN 0x100 /* I/O Port Range in bytes */
#define ADW_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
#define ADW_38C1600_IOLEN 0x100 /* I/O Port Range in bytes */
#define ADW_38C1600_MEMLEN 0x1000 /* Memory Range 4KB */
#define ADW_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
#define ADW_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
#define PCI_ID_ADVANSYS_3550 0x230010CD00000000ull
#define PCI_ID_ADVANSYS_38C0800_REV1 0x250010CD00000000ull
#define PCI_ID_ADVANSYS_38C1600_REV1 0x270010CD00000000ull
#define PCI_ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
#define PCI_ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
/* ====================== SCSI Request Structures =========================== */
@ -240,8 +313,8 @@ struct adw_sg_elm {
struct adw_sg_block {
u_int8_t reserved1;
u_int8_t reserved2;
u_int8_t first_entry_no; /* starting entry number */
u_int8_t last_entry_no; /* last entry number */
u_int8_t reserved3;
u_int8_t sg_cnt; /* Valid entries in this block */
u_int32_t sg_busaddr_next; /* link to the next sg block */
struct adw_sg_elm sg_list[ADW_NO_OF_SG_PER_BLOCK];
};
@ -291,28 +364,42 @@ typedef enum {
*/
struct adw_scsi_req_q {
u_int8_t cntl; /* Ucode flags and state. */
u_int8_t sg_entry_cnt; /* SG element count. Zero for no SG. */
u_int8_t target_cmd;
u_int8_t target_id; /* Device target identifier. */
u_int8_t target_lun; /* Device target logical unit number. */
u_int32_t data_addr; /* Data buffer physical address. */
u_int32_t data_cnt; /* Data count. Ucode sets to residual. */
u_int32_t sense_addr; /* Sense buffer physical address. */
u_int32_t srb_ptr; /* Driver request pointer. */
u_int8_t a_flag; /* Adv Library flag field. */
u_int32_t sense_baddr; /* Sense buffer bus address. */
u_int32_t carrier_baddr; /* Carrier bus address. */
u_int8_t mflag; /* microcode flag field. */
u_int8_t sense_len; /* Auto-sense length. Residual on complete. */
u_int8_t cdb_len; /* SCSI CDB length. */
u_int8_t tag_code; /* SCSI-2 Tag Queue Code: 00, 20-22. */
u_int8_t scsi_cntl; /* SCSI command control flags (tags, nego) */
#define ADW_QSC_NO_DISC 0x01
#define ADW_QSC_NO_TAGMSG 0x02
#define ADW_QSC_NO_SYNC 0x04
#define ADW_QSC_NO_WIDE 0x08
#define ADW_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR */
#define ADW_QSC_HEAD_OF_Q_TAG 0x40
#define ADW_QSC_ORDERED_Q_TAG 0x80
u_int8_t done_status; /* Completion status. */
u_int8_t scsi_status; /* SCSI status byte. */
u_int8_t host_status; /* Ucode host status. */
u_int8_t ux_sg_ix; /* Ucode working SG variable. */
u_int8_t sg_wk_ix; /* Microcode working SG index. */
u_int8_t cdb[12]; /* SCSI command block. */
u_int32_t sg_real_addr; /* SG list physical address. */
u_int32_t free_scsiq_link;/* Unused */
u_int32_t ux_wk_data_cnt; /* Saved data count at disconnection. */
u_int32_t scsi_req_baddr; /* Bus address of this request. */
u_int32_t sg_block_index; /* sg_block tag (Unused) */
u_int32_t scsi_req_baddr; /* Bus address of this structure. */
u_int32_t sg_wk_data_cnt; /* Saved data count at disconnection. */
/*
* The 'tokens' placed in these two fields are
* used to identify the scsi request and the next
* carrier in the response queue, *not* physical
* addresses. This driver uses byte offsets for
* portability and speed of mapping back to either
* a virtual or physical address.
*/
u_int32_t scsi_req_bo; /* byte offset of this structure */
u_int32_t carrier_bo; /* byte offst of our carrier. */
};
typedef enum {
@ -332,23 +419,6 @@ struct acb {
SLIST_ENTRY(acb) links;
};
typedef struct {
u_int16_t bios_init_dis :1,/* don't act as initiator. */
bios_ext_trans :1,/* > 1 GB support */
bios_more_2disk :1,/* > 2 Disk Support */
bios_no_removable:1,/* don't support removables */
bios_cd_boot :1,/* support bootable CD */
:1,
bios_multi_lun :1,/* support multiple LUNs */
bios_message :1,/* display BIOS message */
:1,
bios_reset_sb :1,/* Reset SCSI bus during init. */
:1,
bios_quiet :1,/* No verbose initialization. */
bios_scsi_par_en :1,/* SCSI parity enabled */
:3;
} adw_bios_ctrl;
/*
* EEPROM configuration format
*
@ -371,6 +441,7 @@ struct adw_eeprom
#define ADW_EEPROM_BIG_ENDIAN 0x8000
#define ADW_EEPROM_BIOS_ENABLE 0x4000
#define ADW_EEPROM_TERM_POL 0x2000
#define ADW_EEPROM_CIS_LD 0x1000
/* bit 13 set - Term Polarity Control */
/* bit 14 set - BIOS Enable */
@ -378,7 +449,15 @@ struct adw_eeprom
u_int16_t cfg_msw; /* unused */
u_int16_t disc_enable;
u_int16_t wdtr_able;
u_int16_t sdtr_able;
union {
/*
* sync enable bits for UW cards,
* actual sync rate for TID 0-3
* on U2W and U160 cards.
*/
u_int16_t sync_enable;
u_int16_t sdtr1;
} sync1;
u_int16_t start_motor;
u_int16_t tagqng_able;
u_int16_t bios_scan;
@ -391,31 +470,70 @@ struct adw_eeprom
u_int8_t bios_id_lun; /* high nibble is lun */
/* low nibble is scsi id */
u_int8_t termination; /* 0 - automatic */
u_int8_t termination_se; /* 0 - automatic */
#define ADW_EEPROM_TERM_AUTO 0
#define ADW_EEPROM_TERM_OFF 1
#define ADW_EEPROM_TERM_HIGH_ON 2
#define ADW_EEPROM_TERM_BOTH_ON 3
u_int8_t reserved1; /* reserved byte (not used) */
adw_bios_ctrl bios_ctrl;
u_int8_t termination_lvd;
u_int16_t bios_ctrl;
#define ADW_BIOS_INIT_DIS 0x0001 /* Don't act as initiator */
#define ADW_BIOS_EXT_TRANS 0x0002 /* > 1 GB support */
#define ADW_BIOS_MORE_2DISK 0x0004 /* > 1 GB support */
#define ADW_BIOS_NO_REMOVABLE 0x0008 /* don't support removable media */
#define ADW_BIOS_CD_BOOT 0x0010 /* support bootable CD */
#define ADW_BIOS_SCAN_EN 0x0020 /* BIOS SCAN enabled */
#define ADW_BIOS_MULTI_LUN 0x0040 /* probe luns */
#define ADW_BIOS_MESSAGE 0x0080 /* display BIOS message */
#define ADW_BIOS_RESET_BUS 0x0200 /* reset SCSI bus durint init */
#define ADW_BIOS_QUIET 0x0800 /* No verbose initialization */
#define ADW_BIOS_SCSI_PAR_EN 0x1000 /* SCSI parity enabled */
u_int16_t ultra_able; /* 13 ULTRA speed able */
u_int16_t reserved2; /* 14 reserved */
union {
/* 13
* ultra enable bits for UW cards,
* actual sync rate for TID 4-7
* on U2W and U160 cards.
*/
u_int16_t ultra_enable;
u_int16_t sdtr2;
} sync2;
union {
/* 14
* reserved for UW cards,
* actual sync rate for TID 8-11
* on U2W and U160 cards.
*/
u_int16_t reserved;
u_int16_t sdtr3;
} sync3;
u_int8_t max_host_qng; /* 15 maximum host queuing */
u_int8_t max_dvc_qng; /* maximum per device queuing */
u_int16_t dvc_cntl; /* 16 control bit for driver */
u_int16_t bug_fix; /* 17 control bit for bug fix */
u_int16_t serial_number[3];
u_int16_t checksum;
u_int8_t oem_name[16];
u_int16_t dvc_err_code;
u_int16_t adv_err_code;
u_int16_t adv_err_addr;
u_int16_t saved_dvc_err_code;
u_int16_t saved_adv_err_code;
u_int16_t saved_adv_err_addr;
u_int16_t num_of_err;
union {
/* 17
* reserved for UW cards,
* actual sync rate for TID 12-15
* on U2W and U160 cards.
*/
u_int16_t reserved;
u_int16_t sdtr4;
} sync4;
u_int16_t serial_number[3]; /* 18-20 */
u_int16_t checksum; /* 21 */
u_int8_t oem_name[16]; /* 22 - 29 */
u_int16_t dvc_err_code; /* 30 */
u_int16_t adv_err_code; /* 31 */
u_int16_t adv_err_addr; /* 32 */
u_int16_t saved_dvc_err_code; /* 33 */
u_int16_t saved_adv_err_code; /* 34 */
u_int16_t saved_adv_err_addr; /* 35 */
u_int16_t reserved[20]; /* 36 - 55 */
u_int16_t cisptr_lsw; /* 56 CIS data */
u_int16_t cisptr_msw; /* 57 CIS data */
u_int32_t subid; /* 58-59 SubSystem Vendor/Dev ID */
u_int16_t reserved2[4];
};
/* EEProm Addresses */
@ -424,11 +542,54 @@ struct adw_eeprom
#define ADW_EEP_DVC_CTL_BEGIN (offsetof(struct adw_eeprom, oem_name)/2)
#define ADW_EEP_MAX_WORD_ADDR (sizeof(struct adw_eeprom)/2)
typedef enum {
ADW_CHIP_NONE,
ADW_CHIP_ASC3550, /* Ultra-Wide IC */
ADW_CHIP_ASC38C0800, /* Ultra2-Wide/LVD IC */
ADW_CHIP_ASC38C1600 /* Ultra3-Wide/LVD2 IC */
} adw_chip;
typedef enum {
ADW_FENONE = 0x0000,
ADW_ULTRA = 0x0001, /* Supports 20MHz Transfers */
ADW_ULTRA2 = 0x0002, /* Supports 40MHz Transfers */
ADW_DT = 0x0004, /* Supports Double Transistion REQ/ACK*/
ADW_WIDE = 0x0008, /* Wide Channel */
ADW_ASC3550_FE = ADW_ULTRA,
ADW_ASC38C0800_FE = ADW_ULTRA2,
ADW_ASC38C1600_FE = ADW_ULTRA2|ADW_DT
} adw_feature;
typedef enum {
ADW_FNONE = 0x0000,
ADW_EEPROM_FAILED = 0x0001
} adw_flag;
typedef enum {
ADW_STATE_NORMAL = 0x00,
ADW_RESOURCE_SHORTAGE = 0x01
} adw_state;
typedef enum {
ADW_MC_SDTR_ASYNC,
ADW_MC_SDTR_5,
ADW_MC_SDTR_10,
ADW_MC_SDTR_20,
ADW_MC_SDTR_40,
ADW_MC_SDTR_80
} adw_mc_sdtr;
struct adw_syncrate
{
adw_mc_sdtr mc_sdtr;
u_int8_t period;
char *rate;
};
/* We have an input and output queue for our carrier structures */
#define ADW_OUTPUT_QUEUE 0 /* Offset into carriers member */
#define ADW_INPUT_QUEUE 1 /* Offset into carriers member */
#define ADW_NUM_CARRIER_QUEUES 2
struct adw_softc
{
bus_space_tag_t tag;
@ -436,16 +597,37 @@ struct adw_softc
adw_state state;
bus_dma_tag_t buffer_dmat;
struct acb *acbs;
struct adw_carrier *carriers;
struct adw_carrier *free_carriers;
struct adw_carrier *commandq;
struct adw_carrier *responseq;
LIST_HEAD(, ccb_hdr) pending_ccbs;
SLIST_HEAD(, acb) free_acb_list;
bus_dma_tag_t parent_dmat;
bus_dma_tag_t carrier_dmat; /* dmat for our acb carriers*/
bus_dmamap_t carrier_dmamap;
bus_dma_tag_t acb_dmat; /* dmat for our ccb array */
bus_dmamap_t acb_dmamap;
bus_dma_tag_t sg_dmat; /* dmat for our sg maps */
SLIST_HEAD(, sg_map_node) sg_maps;
bus_addr_t acb_busbase;
bus_addr_t carrier_busbase;
adw_chip chip;
adw_feature features;
adw_flag flags;
u_int memsize;
char channel;
struct cam_path *path;
struct cam_sim *sim;
struct resource *regs;
struct resource *irq;
void *ih;
const struct adw_mcode *mcode_data;
const struct adw_eeprom *default_eeprom;
device_t device;
int regs_res_type;
int regs_res_id;
int irq_res_type;
u_int max_acbs;
u_int num_acbs;
u_int initiator_id;
@ -453,20 +635,22 @@ struct adw_softc
u_int unit;
char* name;
cam_status last_reset; /* Last reset type */
adw_bios_ctrl bios_ctrl;
u_int16_t bios_ctrl;
adw_idle_cmd_t idle_cmd;
u_int idle_cmd_param;
volatile int idle_command_cmp;
u_int16_t user_wdtr;
u_int16_t user_sdtr;
u_int16_t user_ultra;
u_int16_t user_sdtr[4]; /* A nibble per-device */
u_int16_t user_tagenb;
u_int16_t tagenb;
u_int16_t user_discenb;
u_int16_t serial_number[3];
};
extern struct adw_eeprom adw_default_eeprom;
extern const struct adw_eeprom adw_asc3550_default_eeprom;
extern const struct adw_eeprom adw_asc38C0800_default_eeprom;
extern const struct adw_syncrate adw_syncrates[];
extern const int adw_num_syncrates;
#define adw_inb(adw, port) \
bus_space_read_1((adw)->tag, (adw)->bsh, port)
@ -482,6 +666,9 @@ extern struct adw_eeprom adw_default_eeprom;
#define adw_outl(adw, port, value) \
bus_space_write_4((adw)->tag, (adw)->bsh, port, value)
#define adw_set_multi_2(adw, port, value, count) \
bus_space_set_multi_2((adw)->tag, (adw)->bsh, port, value, count)
static __inline const char* adw_name(struct adw_softc *adw);
static __inline u_int adw_lram_read_8(struct adw_softc *adw, u_int addr);
static __inline u_int adw_lram_read_16(struct adw_softc *adw, u_int addr);
@ -493,6 +680,25 @@ static __inline void adw_lram_write_16(struct adw_softc *adw, u_int addr,
static __inline void adw_lram_write_32(struct adw_softc *adw, u_int addr,
u_int value);
static __inline u_int32_t acbvtobo(struct adw_softc *adw,
struct acb *acb);
static __inline u_int32_t acbvtob(struct adw_softc *adw,
struct acb *acb);
static __inline struct acb * acbbotov(struct adw_softc *adw,
u_int32_t busaddr);
static __inline struct acb * acbbtov(struct adw_softc *adw,
u_int32_t busaddr);
static __inline u_int32_t carriervtobo(struct adw_softc *adw,
struct adw_carrier *carrier);
static __inline u_int32_t carriervtob(struct adw_softc *adw,
struct adw_carrier *carrier);
static __inline struct adw_carrier *
carrierbotov(struct adw_softc *adw,
u_int32_t byte_offset);
static __inline struct adw_carrier *
carrierbtov(struct adw_softc *adw,
u_int32_t baddr);
static __inline const char*
adw_name(struct adw_softc *adw)
{
@ -546,12 +752,71 @@ adw_lram_write_32(struct adw_softc *adw, u_int addr, u_int value)
adw_outw(adw, ADW_RAM_DATA, value >> 16);
}
static __inline u_int32_t
acbvtobo(struct adw_softc *adw, struct acb *acb)
{
return ((u_int32_t)((caddr_t)acb - (caddr_t)adw->acbs));
}
static __inline u_int32_t
acbvtob(struct adw_softc *adw, struct acb *acb)
{
return (adw->acb_busbase + acbvtobo(adw, acb));
}
static __inline struct acb *
acbbotov(struct adw_softc *adw, u_int32_t byteoffset)
{
return ((struct acb *)((caddr_t)adw->acbs + byteoffset));
}
static __inline struct acb *
acbbtov(struct adw_softc *adw, u_int32_t busaddr)
{
return (acbbotov(adw, busaddr - adw->acb_busbase));
}
/*
* Return the byte offset for a carrier relative to our array of carriers.
*/
static __inline u_int32_t
carriervtobo(struct adw_softc *adw, struct adw_carrier *carrier)
{
return ((u_int32_t)((caddr_t)carrier - (caddr_t)adw->carriers));
}
static __inline u_int32_t
carriervtob(struct adw_softc *adw, struct adw_carrier *carrier)
{
return (adw->carrier_busbase + carriervtobo(adw, carrier));
}
static __inline struct adw_carrier *
carrierbotov(struct adw_softc *adw, u_int32_t byte_offset)
{
return ((struct adw_carrier *)((caddr_t)adw->carriers + byte_offset));
}
static __inline struct adw_carrier *
carrierbtov(struct adw_softc *adw, u_int32_t baddr)
{
return (carrierbotov(adw, baddr - adw->carrier_busbase));
}
/* Intialization */
int adw_find_signature(bus_space_tag_t tag, bus_space_handle_t bsh);
int adw_find_signature(struct adw_softc *adw);
void adw_reset_chip(struct adw_softc *adw);
u_int16_t adw_eeprom_read(struct adw_softc *adw, struct adw_eeprom *buf);
void adw_eeprom_write(struct adw_softc *adw, struct adw_eeprom *buf);
int adw_init_chip(struct adw_softc *adw, u_int term_scsicfg1);
void adw_set_user_sdtr(struct adw_softc *adw,
u_int tid, u_int mc_sdtr);
u_int adw_get_user_sdtr(struct adw_softc *adw, u_int tid);
void adw_set_chip_sdtr(struct adw_softc *adw, u_int tid, u_int sdtr);
u_int adw_get_chip_sdtr(struct adw_softc *adw, u_int tid);
u_int adw_find_sdtr(struct adw_softc *adw, u_int period);
u_int adw_find_period(struct adw_softc *adw, u_int mc_sdtr);
u_int adw_hshk_cfg_period_factor(u_int tinfo);
/* Idle Commands */
void adw_idle_cmd_send(struct adw_softc *adw, u_int cmd,
@ -562,44 +827,46 @@ adw_idle_cmd_status_t adw_idle_cmd_wait(struct adw_softc *adw);
static __inline void adw_send_acb(struct adw_softc *adw, struct acb *acb,
u_int32_t acb_baddr);
static __inline void adw_tickle_risc(struct adw_softc *adw, u_int value)
{
/*
* Tickle the RISC to tell it to read its Command Queue Head pointer.
*/
adw_outb(adw, ADW_TICKLE, value);
if (adw->chip == ADW_CHIP_ASC3550) {
/*
* Clear the tickle value. In the ASC-3550 the RISC flag
* command 'clr_tickle_a' does not work unless the host
* value is cleared.
*/
adw_outb(adw, ADW_TICKLE, ADW_TICKLE_NOP);
}
}
static __inline void
adw_send_acb(struct adw_softc *adw, struct acb *acb, u_int32_t acb_baddr)
{
u_int next_queue;
struct adw_carrier *new_cq;
/* Determine the next free queue. */
next_queue = adw_lram_read_8(adw, ADW_MC_HOST_NEXT_READY);
next_queue = ADW_MC_RISC_Q_LIST_BASE
+ (next_queue * ADW_MC_RISC_Q_LIST_SIZE);
new_cq = adw->free_carriers;
adw->free_carriers = carrierbotov(adw, new_cq->next_ba);
new_cq->next_ba = ADW_CQ_STOPPER;
/*
* Write the physical address of the host Q to the free Q.
*/
adw_lram_write_32(adw, next_queue + RQL_PHYADDR, acb_baddr);
acb->queue.carrier_baddr = adw->commandq->carr_ba;
acb->queue.carrier_bo = adw->commandq->carr_offset;
adw->commandq->areq_ba = acbvtob(adw, acb);
adw->commandq->next_ba = new_cq->carr_ba;
#if 0
printf("EnQ 0x%x 0x%x 0x%x 0x%x\n",
adw->commandq->carr_offset,
adw->commandq->carr_ba,
adw->commandq->areq_ba,
adw->commandq->next_ba);
#endif
adw->commandq = new_cq;
adw_lram_write_8(adw, next_queue + RQL_TID, acb->queue.target_id);
/*
* Set the ADW_MC_HOST_NEXT_READY (0x128) microcode variable to
* the 'next_queue' request forward pointer.
*
* Do this *before* changing the 'next_queue' queue to QS_READY.
* After the state is changed to QS_READY 'RQL_FWD' will be changed
* by the microcode.
*
*/
adw_lram_write_8(adw, ADW_MC_HOST_NEXT_READY,
adw_lram_read_8(adw, next_queue + RQL_FWD));
/*
* Change the state of 'next_queue' request from QS_FREE to
* QS_READY which will cause the microcode to pick it up and
* execute it.
*
* Can't reference 'next_queue' after changing the request
* state to QS_READY. The microcode now owns the request.
*/
adw_lram_write_8(adw, next_queue + RQL_STATE, ADW_MC_QS_READY);
adw_tickle_risc(adw, ADW_TICKLE_A);
}
#endif /* _ADWLIB_H_ */

1391
sys/dev/advansys/adwmcode.c
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File diff suppressed because it is too large Load Diff

119
sys/dev/advansys/adwmcode.h
View File

@ -5,7 +5,7 @@
*
* Obtained from:
*
* Copyright (c) 1995-1998 Advanced System Products, Inc.
* Copyright (c) 1995-1999 Advanced System Products, Inc.
* All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -17,9 +17,15 @@
#ifndef _ADMCODE_H_
#define _ADMCODE_H_
extern u_int16_t adw_mcode[];
extern u_int16_t adw_mcode_size;
extern u_int32_t adw_mcode_chksum;
struct adw_mcode
{
const u_int8_t* mcode_buf;
const u_int32_t mcode_chksum;
const u_int16_t mcode_size;
};
extern const struct adw_mcode adw_asc3550_mcode_data;
extern const struct adw_mcode adw_asc38C0800_mcode_data;
/*
* Fixed LRAM locations of microcode operating variables.
@ -27,21 +33,33 @@ extern u_int32_t adw_mcode_chksum;
#define ADW_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
#define ADW_MC_CODE_END_ADDR 0x002A /* microcode end address */
#define ADW_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
#define ADW_MC_STACK_BEGIN 0x002E /* microcode stack begin */
#define ADW_MC_STACK_END 0x0030 /* microcode stack end */
#define ADW_MC_VERSION_DATE 0x0038 /* microcode version */
#define ADW_MC_VERSION_NUM 0x003A /* microcode number */
#define ADW_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
#define ADW_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
#define ADW_MC_HALTCODE 0x0094 /* microcode halt code */
#define ADW_MC_CALLERPC 0x0096 /* microcode halt caller PC */
#define ADW_MC_ADAPTER_SCSI_ID 0x0098 /* one ID byte + reserved */
#define ADW_MC_ULTRA_ABLE 0x009C
#define ADW_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
#define ADW_MC_BIOS_VERSION 0x005A /* BIOS Version (2 Bytes) */
#define ADW_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
#define ADW_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
#define ADW_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
#define ADW_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
#define ADW_MC_CHIP_TYPE 0x009A
#define ADW_MC_INTRB_CODE 0x009B
#define ADW_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
#define ADW_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected Bus Reset. */
#define ADW_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure.*/
#define ADW_ASYNC_HOST_SCSI_BUS_RESET 0x80 /*
* Host Initiated
* SCSI Bus Reset.
*/
#define ADW_MC_WDTR_ABLE_BIOS_31 0x0120
#define ADW_MC_WDTR_ABLE 0x009C
#define ADW_MC_SDTR_ABLE 0x009E
#define ADW_MC_TAGQNG_ABLE 0x00A0
#define ADW_MC_DISC_ENABLE 0x00A2
#define ADW_MC_IDLE_CMD_STATUS 0x00A4
#define ADW_MC_IDLE_CMD 0x00A6
#define ADW_MC_IDLE_PARA_STAT 0x00A8
#define ADW_MC_IDLE_CMD_PARAMETER 0x00A8
#define ADW_MC_DEFAULT_SCSI_CFG0 0x00AC
#define ADW_MC_DEFAULT_SCSI_CFG1 0x00AE
#define ADW_MC_DEFAULT_MEM_CFG 0x00B0
@ -53,56 +71,45 @@ extern u_int32_t adw_mcode_chksum;
#define ADW_MC_NUMBER_OF_MAX_CMD 0x00D0
#define ADW_MC_DEVICE_HSHK_CFG_TABLE 0x0100
#define ADW_HSHK_CFG_WIDE_XFR 0x8000
#define ADW_HSHK_CFG_RATE_MASK 0x0F00
#define ADW_HSHK_CFG_RATE_MASK 0x7F00
#define ADW_HSHK_CFG_RATE_SHIFT 8
#define ADW_HSHK_CFG_PERIOD_FACTOR(cfg_val) \
((((((cfg_val) & ADW_HSHK_CFG_RATE_MASK) >> ADW_HSHK_CFG_RATE_SHIFT) \
* 25) + 50)/4)
#define ADW_HSHK_CFG_OFFSET 0x001F
#define ADW_MC_WDTR_ABLE 0x0120 /* Wide Transfer TID bitmask. */
#define ADW_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
#define ADW_MC_CONTROL_IGN_PERR 0x0001 /* Ignore DMA Parity Errors */
#define ADW_MC_WDTR_DONE 0x0124
#define ADW_MC_HOST_NEXT_READY 0x0128 /* Host Next Ready RQL Entry. */
#define ADW_MC_HOST_NEXT_DONE 0x0129 /* Host Next Done RQL Entry. */
/*
* LRAM RISC Queue Lists (LRAM addresses 0x1200 - 0x19FF)
*
* Each of the 255 Adv Library/Microcode RISC queue lists or mailboxes
* starting at LRAM address 0x1200 is 8 bytes and has the following
* structure. Only 253 of these are actually used for command queues.
*/
#define ADW_MC_RISC_Q_LIST_BASE 0x1200
#define ADW_MC_RISC_Q_LIST_SIZE 0x0008
#define ADW_MC_RISC_Q_TOTAL_CNT 0x00FF /* Num. queue slots in LRAM. */
#define ADW_MC_RISC_Q_FIRST 0x0001
#define ADW_MC_RISC_Q_LAST 0x00FF
/* RISC Queue List structure - 8 bytes */
#define RQL_FWD 0 /* forward pointer (1 byte) */
#define RQL_BWD 1 /* backward pointer (1 byte) */
#define RQL_STATE 2 /* state byte - free, ready, done, aborted (1 byte) */
#define RQL_TID 3 /* request target id (1 byte) */
#define RQL_PHYADDR 4 /* request physical pointer (4 bytes) */
/* RISC Queue List state values */
#define ADW_MC_QS_FREE 0x00
#define ADW_MC_QS_READY 0x01
#define ADW_MC_QS_DONE 0x40
#define ADW_MC_QS_ABORTED 0x80
/* RISC Queue List pointer values */
#define ADW_MC_NULL_Q 0x00
#define ADW_MC_BIOS_Q 0xFF
#define ADW_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
#define ADW_MC_ICQ 0x0160
#define ADW_MC_IRQ 0x0164
/* ADW_SCSI_REQ_Q 'cntl' field values */
#define ADW_MC_QC_START_MOTOR 0x02 /* Issue start motor. */
#define ADW_MC_QC_NO_OVERRUN 0x04 /* Don't report overrun. */
#define ADW_MC_QC_FIRST_DMA 0x08 /* Internal microcode flag. */
#define ADW_MC_QC_ABORTED 0x10 /* Request aborted by host. */
#define ADW_MC_QC_REQ_SENSE 0x20 /* Auto-Request Sense. */
#define ADW_MC_QC_DOS_REQ 0x80 /* Request issued by DOS. */
#define ADW_QC_DATA_CHECK 0x01 /* Require ADW_QC_DATA_OUT set or clear. */
#define ADW_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
#define ADW_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
#define ADW_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
#define ADW_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request.XXXTBD */
#define ADW_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
#define ADW_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
#define ADW_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request.*/
#define ADW_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
#define ADW_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request.*/
/*
* Note: If a Tag Message is to be sent and neither ADW_QSC_HEAD_TAG or
* ADW_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
*/
#define ADW_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
#define ADW_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
struct adw_carrier
{
u_int32_t carr_offset; /* Carrier byte offset into our array */
u_int32_t carr_ba; /* Carrier Bus Address */
u_int32_t areq_ba; /* SCSI Req Queue Bus Address */
u_int32_t next_ba;
#define ADW_RQ_DONE 0x00000001
#define ADW_CQ_STOPPER 0x00000000
#define ADW_NEXT_BA_MASK 0xFFFFFFF0
};
/*
* Microcode idle loop commands
@ -114,7 +121,9 @@ typedef enum {
ADW_IDLE_CMD_SEND_INT = 0x0004,
ADW_IDLE_CMD_ABORT = 0x0008,
ADW_IDLE_CMD_DEVICE_RESET = 0x0010,
ADW_IDLE_CMD_SCSI_RESET = 0x0020
ADW_IDLE_CMD_SCSI_RESET_START = 0x0020,
ADW_IDLE_CMD_SCSI_RESET_END = 0x0040,
ADW_IDLE_CMD_SCSIREQ = 0x0080
} adw_idle_cmd_t;
typedef enum {

8
sys/dev/advansys/adwvar.h
View File

@ -2,7 +2,7 @@
* Generic driver definitions and exported functions for the Advanced
* Systems Inc. Second Generation SCSI controllers
*
* Copyright (c) 1998 Justin Gibbs.
* Copyright (c) 1998, 1999, 2000 Justin Gibbs.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -10,7 +10,7 @@
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification, immediately at the beginning of the file.
* without modification.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
@ -39,8 +39,8 @@
#include "adw.h"
#include <dev/advansys/adwlib.h>
struct adw_softc * adw_alloc(int unit, bus_space_tag_t tag,
bus_space_handle_t bsh);
struct adw_softc * adw_alloc(device_t dev, struct resource *regs,
int regs_type, int regs_id);
void adw_map(void *arg, bus_dma_segment_t *segs,
int nseg, int error);
void adw_free(struct adw_softc *adw);