Don't use multiprocessing-extensions instruction on processors that don't
support SMP. Submitted by: loos@ Pointy hat to: me
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@ -251,7 +251,11 @@ ENTRY(armv7_idcache_wbinv_range)
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END(armv7_idcache_wbinv_range)
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ENTRY_NP(armv7_icache_sync_all)
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#ifdef SMP
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mcr p15, 0, r0, c7, c1, 0 /* Invalidate all I cache to PoU Inner Shareable */
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#else
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mcr p15, 0, r0, c7, c5, 0 /* Invalidate all I cache to PoU (ICIALLU) */
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#endif
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isb /* instruction synchronization barrier */
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dsb /* data synchronization barrier */
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RET
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