[etherswitch] [rtl8366] add phy4cpu setting and support mdioproxy
Tested on WZR-HP-G301NH(RTL8366RB) and WZR-HP-G300NH(RTL8366SR). Submitted by: Hiroki Mori <yamori813@yahoo.co.jp> Differential Revision: https://reviews.freebsd.org/D10740
This commit is contained in:
Michael Zhilin
parent
97721228b8
commit
5a4380b565
@ -54,10 +54,12 @@
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#include <dev/iicbus/iicbus.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include <dev/mdio/mdio.h>
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#include <dev/etherswitch/etherswitch.h>
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#include <dev/etherswitch/rtl8366/rtl8366rbvar.h>
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#include "mdio_if.h"
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#include "iicbus_if.h"
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#include "miibus_if.h"
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#include "etherswitch_if.h"
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@ -74,7 +76,9 @@ struct rtl8366rb_softc {
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struct ifnet *ifp[RTL8366_NUM_PHYS];
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struct callout callout_tick;
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etherswitch_info_t info;
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int chip_type; /* 0 = RTL8366RB, 1 = RTL8366SR */
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int chip_type;
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int phy4cpu;
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int numphys;
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};
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#define RTL_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
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@ -145,7 +149,7 @@ rtl8366rb_probe(device_t dev)
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bzero(sc, sizeof(*sc));
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if (smi_probe(dev) != 0)
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return (ENXIO);
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if(sc->chip_type == 0)
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if (sc->chip_type == RTL8366RB)
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device_set_desc(dev, "RTL8366RB Ethernet Switch Controller");
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else
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device_set_desc(dev, "RTL8366SR Ethernet Switch Controller");
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@ -215,17 +219,23 @@ rtl8366rb_attach(device_t dev)
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smi_read(dev, RTL8366_CVCR, &rev, RTL_WAITOK);
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device_printf(dev, "rev. %d\n", rev & 0x000f);
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sc->info.es_nports = RTL8366_NUM_PORTS;
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sc->phy4cpu = 0;
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(void) resource_int_value(device_get_name(dev), device_get_unit(dev),
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"phy4cpu", &sc->phy4cpu);
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sc->numphys = sc->phy4cpu ? RTL8366_NUM_PHYS - 1 : RTL8366_NUM_PHYS;
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sc->info.es_nports = sc->numphys + 1;
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sc->info.es_nvlangroups = RTL8366_NUM_VLANS;
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sc->info.es_vlan_caps = ETHERSWITCH_VLAN_DOT1Q;
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if(sc->chip_type == 0)
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if (sc->chip_type == RTL8366RB)
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sprintf(sc->info.es_name, "Realtek RTL8366RB");
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else
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sprintf(sc->info.es_name, "Realtek RTL8366SR");
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/* attach miibus and phys */
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/* PHYs need an interface, so we generate a dummy one */
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for (i = 0; i < RTL8366_NUM_PHYS; i++) {
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for (i = 0; i < sc->numphys; i++) {
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sc->ifp[i] = if_alloc(IFT_ETHER);
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sc->ifp[i]->if_softc = sc;
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sc->ifp[i]->if_flags |= IFF_UP | IFF_BROADCAST | IFF_DRV_RUNNING
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@ -263,7 +273,7 @@ rtl8366rb_detach(device_t dev)
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sc = device_get_softc(dev);
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for (i=0; i < RTL8366_NUM_PHYS; i++) {
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for (i=0; i < sc->numphys; i++) {
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if (sc->miibus[i])
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device_delete_child(dev, sc->miibus[i]);
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if (sc->ifp[i] != NULL)
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@ -319,7 +329,7 @@ rtl833rb_miipollstat(struct rtl8366rb_softc *sc)
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uint16_t value;
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int portstatus;
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for (i = 0; i < RTL8366_NUM_PHYS; i++) {
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for (i = 0; i < sc->numphys; i++) {
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mii = device_get_softc(sc->miibus[i]);
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if ((i % 2) == 0) {
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if (smi_read(sc->dev, RTL8366_PLSR_BASE + i/2, &value, RTL_NOWAIT) != 0) {
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@ -365,7 +375,7 @@ smi_probe(device_t dev)
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iicbus = device_get_parent(dev);
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iicha = device_get_parent(iicbus);
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for(i = 0; i < 2; ++i) {
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for (i = 0; i < 2; ++i) {
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iicbus_reset(iicbus, IIC_FASTEST, RTL8366_IIC_ADDR, NULL);
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for (j=3; j--; ) {
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IICBUS_STOP(iicha);
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@ -380,7 +390,7 @@ smi_probe(device_t dev)
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err = iicbus_start(iicbus, RTL8366_IIC_ADDR | RTL_IICBUS_READ, RTL_IICBUS_TIMEOUT);
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if (err != 0)
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goto out;
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if(i == 0) {
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if (i == 0) {
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bytes[0] = RTL8366RB_CIR & 0xff;
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bytes[1] = (RTL8366RB_CIR >> 8) & 0xff;
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} else {
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@ -396,22 +406,22 @@ smi_probe(device_t dev)
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chipid = ((bytes[1] & 0xff) << 8) | (bytes[0] & 0xff);
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if (i == 0 && chipid == RTL8366RB_CIR_ID8366RB) {
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DPRINTF(dev, "chip id 0x%04x\n", chipid);
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sc->chip_type = 0;
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sc->chip_type = RTL8366RB;
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err = 0;
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break;
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}
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if (i == 1 && chipid == RTL8366SR_CIR_ID8366SR) {
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DPRINTF(dev, "chip id 0x%04x\n", chipid);
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sc->chip_type = 1;
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sc->chip_type = RTL8366SR;
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err = 0;
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break;
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}
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if(i == 0) {
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if (i == 0) {
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iicbus_stop(iicbus);
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iicbus_release_bus(iicbus, dev);
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}
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}
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if(i == 2)
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if (i == 2)
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err = ENXIO;
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out:
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iicbus_stop(iicbus);
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@ -472,7 +482,7 @@ smi_select(device_t dev, int op, int sleep)
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RTL_SMI_ACQUIRED_ASSERT((struct rtl8366rb_softc *)device_get_softc(dev));
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if(sc->chip_type == 1) { // RTL8366SR work around
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if (sc->chip_type == RTL8366SR) { // RTL8366SR work around
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// this is same work around at probe
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for (int i=3; i--; )
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IICBUS_STOP(device_get_parent(device_get_parent(dev)));
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@ -648,13 +658,18 @@ rtl_getport(device_t dev, etherswitch_port_t *p)
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ifmr = &p->es_ifmr;
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if (p->es_port < 0 || p->es_port >= RTL8366_NUM_PORTS)
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if (p->es_port < 0 || p->es_port >= (sc->numphys + 1))
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return (ENXIO);
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vlangroup = RTL8366_PVCR_GET(p->es_port,
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rtl_readreg(dev, RTL8366_PVCR_REG(p->es_port)));
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if (sc->phy4cpu && p->es_port == sc->numphys) {
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vlangroup = RTL8366_PVCR_GET(p->es_port + 1,
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rtl_readreg(dev, RTL8366_PVCR_REG(p->es_port + 1)));
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} else {
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vlangroup = RTL8366_PVCR_GET(p->es_port,
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rtl_readreg(dev, RTL8366_PVCR_REG(p->es_port)));
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}
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p->es_pvid = sc->vid[vlangroup] & ETHERSWITCH_VID_MASK;
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if (p->es_port < RTL8366_NUM_PHYS) {
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if (p->es_port < sc->numphys) {
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mii = device_get_softc(sc->miibus[p->es_port]);
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ifm = &mii->mii_media;
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err = ifmedia_ioctl(sc->ifp[p->es_port], &p->es_ifr, ifm, SIOCGIFMEDIA);
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@ -687,10 +702,11 @@ rtl_setport(device_t dev, etherswitch_port_t *p)
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int i, err, vlangroup;
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struct ifmedia *ifm;
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struct mii_data *mii;
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int port;
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sc = device_get_softc(dev);
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if (p->es_port < 0 || p->es_port >= RTL8366_NUM_PORTS)
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if (p->es_port < 0 || p->es_port >= (sc->numphys + 1))
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return (ENXIO);
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vlangroup = -1;
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for (i = 0; i < RTL8366_NUM_VLANS; i++) {
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@ -701,12 +717,18 @@ rtl_setport(device_t dev, etherswitch_port_t *p)
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}
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if (vlangroup == -1)
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return (ENXIO);
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err = smi_rmw(dev, RTL8366_PVCR_REG(p->es_port),
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RTL8366_PVCR_VAL(p->es_port, RTL8366_PVCR_PORT_MASK),
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RTL8366_PVCR_VAL(p->es_port, vlangroup), RTL_WAITOK);
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if (sc->phy4cpu && p->es_port == sc->numphys) {
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port = p->es_port + 1;
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} else {
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port = p->es_port;
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}
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err = smi_rmw(dev, RTL8366_PVCR_REG(port),
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RTL8366_PVCR_VAL(port, RTL8366_PVCR_PORT_MASK),
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RTL8366_PVCR_VAL(port, vlangroup), RTL_WAITOK);
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if (err)
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return (err);
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if (p->es_port == RTL8366_CPU_PORT)
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/* CPU Port */
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if (p->es_port == sc->numphys)
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return (0);
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mii = device_get_softc(sc->miibus[p->es_port]);
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ifm = &mii->mii_media;
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@ -720,6 +742,7 @@ rtl_getvgroup(device_t dev, etherswitch_vlangroup_t *vg)
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struct rtl8366rb_softc *sc;
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uint16_t vmcr[3];
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int i;
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int member, untagged;
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sc = device_get_softc(dev);
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@ -727,8 +750,15 @@ rtl_getvgroup(device_t dev, etherswitch_vlangroup_t *vg)
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vmcr[i] = rtl_readreg(dev, RTL8366_VMCR(i, vg->es_vlangroup));
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vg->es_vid = sc->vid[vg->es_vlangroup];
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vg->es_member_ports = RTL8366_VMCR_MEMBER(vmcr);
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vg->es_untagged_ports = RTL8366_VMCR_UNTAG(vmcr);
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member = RTL8366_VMCR_MEMBER(vmcr);
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untagged = RTL8366_VMCR_UNTAG(vmcr);
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if (sc->phy4cpu) {
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vg->es_member_ports = ((member & 0x20) >> 1) | (member & 0x0f);
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vg->es_untagged_ports = ((untagged & 0x20) >> 1) | (untagged & 0x0f);
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} else {
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vg->es_member_ports = member;
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vg->es_untagged_ports = untagged;
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}
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vg->es_fid = RTL8366_VMCR_FID(vmcr);
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return (0);
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}
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@ -738,6 +768,7 @@ rtl_setvgroup(device_t dev, etherswitch_vlangroup_t *vg)
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{
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struct rtl8366rb_softc *sc;
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int g;
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int member, untagged;
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sc = device_get_softc(dev);
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@ -750,16 +781,26 @@ rtl_setvgroup(device_t dev, etherswitch_vlangroup_t *vg)
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sc->vid[g] |= ETHERSWITCH_VID_VALID;
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rtl_writereg(dev, RTL8366_VMCR(RTL8366_VMCR_DOT1Q_REG, g),
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(vg->es_vid << RTL8366_VMCR_DOT1Q_VID_SHIFT) & RTL8366_VMCR_DOT1Q_VID_MASK);
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if(sc->chip_type == 0) {
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if (sc->phy4cpu) {
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/* add space at phy4 */
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member = (vg->es_member_ports & 0x0f) |
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((vg->es_member_ports & 0x10) << 1);
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untagged = (vg->es_untagged_ports & 0x0f) |
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((vg->es_untagged_ports & 0x10) << 1);
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} else {
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member = vg->es_member_ports;
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untagged = vg->es_untagged_ports;
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}
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if (sc->chip_type == RTL8366RB) {
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rtl_writereg(dev, RTL8366_VMCR(RTL8366_VMCR_MU_REG, g),
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((vg->es_member_ports << RTL8366_VMCR_MU_MEMBER_SHIFT) & RTL8366_VMCR_MU_MEMBER_MASK) |
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((vg->es_untagged_ports << RTL8366_VMCR_MU_UNTAG_SHIFT) & RTL8366_VMCR_MU_UNTAG_MASK));
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((member << RTL8366_VMCR_MU_MEMBER_SHIFT) & RTL8366_VMCR_MU_MEMBER_MASK) |
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((untagged << RTL8366_VMCR_MU_UNTAG_SHIFT) & RTL8366_VMCR_MU_UNTAG_MASK));
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rtl_writereg(dev, RTL8366_VMCR(RTL8366_VMCR_FID_REG, g),
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vg->es_fid);
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} else {
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rtl_writereg(dev, RTL8366_VMCR(RTL8366_VMCR_MU_REG, g),
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((vg->es_member_ports << RTL8366_VMCR_MU_MEMBER_SHIFT) & RTL8366_VMCR_MU_MEMBER_MASK) |
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((vg->es_untagged_ports << RTL8366_VMCR_MU_UNTAG_SHIFT) & RTL8366_VMCR_MU_UNTAG_MASK) |
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((member << RTL8366_VMCR_MU_MEMBER_SHIFT) & RTL8366_VMCR_MU_MEMBER_MASK) |
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((untagged << RTL8366_VMCR_MU_UNTAG_SHIFT) & RTL8366_VMCR_MU_UNTAG_MASK) |
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((vg->es_fid << RTL8366_VMCR_FID_FID_SHIFT) & RTL8366_VMCR_FID_FID_MASK));
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}
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return (0);
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@ -886,6 +927,10 @@ static device_method_t rtl8366rb_methods[] = {
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DEVMETHOD(miibus_readreg, rtl_readphy),
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DEVMETHOD(miibus_writereg, rtl_writephy),
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/* MDIO interface */
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DEVMETHOD(mdio_readreg, rtl_readphy),
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DEVMETHOD(mdio_writereg, rtl_writephy),
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/* etherswitch interface */
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DEVMETHOD(etherswitch_getconf, rtl_getconf),
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DEVMETHOD(etherswitch_getinfo, rtl_getinfo),
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@ -907,6 +952,7 @@ static devclass_t rtl8366rb_devclass;
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DRIVER_MODULE(rtl8366rb, iicbus, rtl8366rb_driver, rtl8366rb_devclass, 0, 0);
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DRIVER_MODULE(miibus, rtl8366rb, miibus_driver, miibus_devclass, 0, 0);
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DRIVER_MODULE(mdio, rtl8366rb, mdio_driver, mdio_devclass, 0, 0);
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DRIVER_MODULE(etherswitch, rtl8366rb, etherswitch_driver, etherswitch_devclass, 0, 0);
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MODULE_VERSION(rtl8366rb, 1);
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MODULE_DEPEND(rtl8366rb, iicbus, 1, 1, 1); /* XXX which versions? */
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@ -30,6 +30,9 @@
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#ifndef _DEV_ETHERSWITCH_RTL8366RBVAR_H_
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#define _DEV_ETHERSWITCH_RTL8366RBVAR_H_
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#define RTL8366RB 0
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#define RTL8366SR 1
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#define RTL8366_IIC_ADDR 0xa8
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#define RTL_IICBUS_TIMEOUT 100 /* us */
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#define RTL_IICBUS_READ 1
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@ -173,9 +176,7 @@
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(0x8000 | (1 << (((phy) & 0x1f) + 9)) | (((page) & (sc->chip_type == 0 ? 0xf : 0x7)) << 5) | ((reg) & 0x1f))
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/* general characteristics of the chip */
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#define RTL8366_CPU_PORT 5
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#define RTL8366_NUM_PORTS 6
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#define RTL8366_NUM_PHYS (RTL8366_NUM_PORTS-1)
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#define RTL8366_NUM_PHYS 5
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#define RTL8366_NUM_VLANS 16
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#define RTL8366_NUM_PHY_REG 32
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