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cxgbe(4): Read the MPS buffer group map from the firmware as it could be

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different from hardware defaults.  The congestion channel map, which is
still fixed, needs to be tracked separately now.  Change the congestion
setting for TOE rx queues to match the drivers on other OSes while here.

MFC after:	2 weeks
Sponsored by:	Chelsio Communications
This commit is contained in:
Navdeep Parhar 2017-10-24 05:41:48 +00:00
parent 6ca2fb6623
commit 5bcae8ddfa
5 changed files with 57 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
sys/dev/cxgbe/adapter.h
View File

@ -287,7 +287,8 @@ struct port_info {
uint8_t mod_type;
uint8_t port_id;
uint8_t tx_chan;
uint8_t rx_chan_map; /* rx MPS channel bitmap */
uint8_t mps_bg_map; /* rx MPS buffer group bitmap */
uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */
struct link_config link_cfg;
struct link_config old_link_cfg;
@ -796,7 +797,7 @@ struct adapter {
struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */
struct port_info *port[MAX_NPORTS];
uint8_t chan_map[MAX_NCHAN];
uint8_t chan_map[MAX_NCHAN]; /* channel -> port */
void *tom_softc; /* (struct tom_data *) */
struct tom_tunables tt;

2
sys/dev/cxgbe/common/common.h
View File

@ -369,6 +369,8 @@ struct adapter_params {
unsigned int max_ordird_qp;
unsigned int max_ird_adapter;
uint32_t mps_bg_map; /* rx buffer group map for all ports (upto 4) */
};
#define CHELSIO_T4 0x4

27
sys/dev/cxgbe/common/t4_hw.c
View File

@ -5894,6 +5894,24 @@ void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
* port.
*/
static unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
{
u32 n;
if (adap->params.mps_bg_map)
return ((adap->params.mps_bg_map >> (idx << 3)) & 0xff);
n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL));
if (n == 0)
return idx == 0 ? 0xf : 0;
if (n == 1 && chip_id(adap) <= CHELSIO_T5)
return idx < 2 ? (3 << (2 * idx)) : 0;
return 1 << idx;
}
/*
* TP RX e-channels associated with the port.
*/
static unsigned int t4_get_rx_e_chan_map(struct adapter *adap, int idx)
{
u32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL));
@ -5972,7 +5990,7 @@ void t4_get_port_stats_offset(struct adapter *adap, int idx,
*/
void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
{
u32 bgmap = t4_get_mps_bg_map(adap, idx);
u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map;
u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL);
#define GET_STAT(name) \
@ -6074,7 +6092,7 @@ void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
*/
void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
{
u32 bgmap = t4_get_mps_bg_map(adap, idx);
u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map;
#define GET_STAT(name) \
t4_read_reg64(adap, \
@ -8379,7 +8397,8 @@ int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id)
else
p->vi[0].smt_idx = (ret & 0x7f);
p->tx_chan = j;
p->rx_chan_map = t4_get_mps_bg_map(adap, j);
p->mps_bg_map = t4_get_mps_bg_map(adap, j);
p->rx_e_chan_map = t4_get_rx_e_chan_map(adap, j);
p->lport = j;
p->vi[0].rss_size = rss_size;
t4_os_set_hw_addr(p, addr);
@ -9374,7 +9393,7 @@ int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map,
void t4_clr_port_stats(struct adapter *adap, int idx)
{
unsigned int i;
u32 bgmap = t4_get_mps_bg_map(adap, idx);
u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map;
u32 port_base_addr;
if (is_t4(adap))

37
sys/dev/cxgbe/t4_main.c
View File

@ -3563,6 +3563,19 @@ get_params__post_init(struct adapter *sc)
("%s: L2 table size (%u) larger than expected (%u)",
__func__, sc->vres.l2t.size, L2T_SIZE));
/*
* MPSBGMAP is queried separately because only recent firmwares support
* it as a parameter and we don't want the compound query above to fail
* on older firmwares.
*/
param[0] = FW_PARAM_DEV(MPSBGMAP);
val[0] = 0;
rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
if (rc == 0)
sc->params.mps_bg_map = val[0];
else
sc->params.mps_bg_map = 0;
/* get capabilites */
bzero(&caps, sizeof(caps));
caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
@ -5061,8 +5074,7 @@ vi_refresh_stats(struct adapter *sc, struct vi_info *vi)
static void
cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi)
{
int i;
u_int v, tnl_cong_drops;
u_int i, v, tnl_cong_drops, bg_map;
struct timeval tv;
const struct timeval interval = {0, 250000}; /* 250ms */
@ -5073,14 +5085,15 @@ cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi)
tnl_cong_drops = 0;
t4_get_port_stats(sc, pi->tx_chan, &pi->stats);
for (i = 0; i < sc->chip_params->nchan; i++) {
if (pi->rx_chan_map & (1 << i)) {
mtx_lock(&sc->reg_lock);
t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v,
1, A_TP_MIB_TNL_CNG_DROP_0 + i);
mtx_unlock(&sc->reg_lock);
tnl_cong_drops += v;
}
bg_map = pi->mps_bg_map;
while (bg_map) {
i = ffs(bg_map) - 1;
mtx_lock(&sc->reg_lock);
t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1,
A_TP_MIB_TNL_CNG_DROP_0 + i);
mtx_unlock(&sc->reg_lock);
tnl_cong_drops += v;
bg_map &= ~(1 << i);
}
pi->tnl_cong_drops = tnl_cong_drops;
getmicrotime(&pi->last_refreshed);
@ -5672,6 +5685,10 @@ cxgbe_sysctls(struct port_info *pi)
SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL,
port_top_speed(pi), "max speed (in Gbps)");
SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL,
pi->mps_bg_map, "MPS buffer group map");
SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD,
NULL, pi->rx_e_chan_map, "TP rx e-channel map");
if (sc->flags & IS_VF)
return;

5
sys/dev/cxgbe/t4_sge.c
View File

@ -3085,7 +3085,7 @@ tnl_cong(struct port_info *pi, int drop)
else if (drop == 1)
return (0);
else
return (pi->rx_chan_map);
return (pi->rx_e_chan_map);
}
static int
@ -3195,8 +3195,7 @@ alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq,
struct sysctl_oid_list *children;
char name[16];
rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx,
pi->rx_chan_map);
rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 0);
if (rc != 0)
return (rc);