Similar to the (1 << 31) case it is not defined to do (2 << 30).
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@ -297,8 +297,8 @@ struct cesa_chain_info {
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#define CESA_CSH_AES_KLEN_MASK (3 << 24)
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#define CESA_CSHD_FRAG_FIRST (1 << 30)
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#define CESA_CSHD_FRAG_LAST (2 << 30)
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#define CESA_CSHD_FRAG_MIDDLE (3 << 30)
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#define CESA_CSHD_FRAG_LAST (2U << 30)
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#define CESA_CSHD_FRAG_MIDDLE (3U << 30)
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/* CESA registers definitions */
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#define CESA_ICR 0xDE20
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@ -807,8 +807,8 @@ extern int r600_cs_init(struct drm_device *dev);
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#define RADEON_DST_PITCH_OFFSET_C 0x1c80
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# define RADEON_DST_TILE_LINEAR (0 << 30)
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# define RADEON_DST_TILE_MACRO (1 << 30)
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# define RADEON_DST_TILE_MICRO (2 << 30)
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# define RADEON_DST_TILE_BOTH (3 << 30)
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# define RADEON_DST_TILE_MICRO (2U << 30)
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# define RADEON_DST_TILE_BOTH (3U << 30)
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#define RADEON_SCRATCH_REG0 0x15e0
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#define RADEON_SCRATCH_REG1 0x15e4
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@ -3611,8 +3611,8 @@ __FBSDID("$FreeBSD$");
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#define PANEL_PORT_SELECT_LVDS (0 << 30)
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#define PANEL_PORT_SELECT_DPA (1 << 30)
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#define EDP_PANEL (1 << 30)
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#define PANEL_PORT_SELECT_DPC (2 << 30)
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#define PANEL_PORT_SELECT_DPD (3 << 30)
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#define PANEL_PORT_SELECT_DPC (2U << 30)
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#define PANEL_PORT_SELECT_DPD (3U << 30)
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#define PANEL_POWER_UP_DELAY_MASK (0x1fff0000)
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#define PANEL_POWER_UP_DELAY_SHIFT 16
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#define PANEL_LIGHT_ON_DELAY_MASK (0x1fff)
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@ -196,7 +196,7 @@ set_vtx_resource(drm_radeon_private_t *dev_priv, u64 gpu_addr)
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sq_vtx_constant_word2 = (((gpu_addr >> 32) & 0xff) | (16 << 8));
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#ifdef __BIG_ENDIAN
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sq_vtx_constant_word2 |= (2 << 30);
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sq_vtx_constant_word2 |= (2U << 30);
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#endif
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BEGIN_RING(9);
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@ -720,8 +720,8 @@ void radeon_unregister_atpx_handler(void);
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#define RADEON_DST_PITCH_OFFSET_C 0x1c80
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# define RADEON_DST_TILE_LINEAR (0 << 30)
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# define RADEON_DST_TILE_MACRO (1 << 30)
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# define RADEON_DST_TILE_MICRO (2 << 30)
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# define RADEON_DST_TILE_BOTH (3 << 30)
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# define RADEON_DST_TILE_MICRO (2U << 30)
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# define RADEON_DST_TILE_BOTH (3U << 30)
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#define RADEON_SCRATCH_REG0 0x15e0
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#define RADEON_SCRATCH_REG1 0x15e4
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@ -854,8 +854,8 @@ __FBSDID("$FreeBSD$");
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# define RADEON_PITCH_SHIFT 21
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# define RADEON_DST_TILE_LINEAR (0 << 30)
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# define RADEON_DST_TILE_MACRO (1 << 30)
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# define RADEON_DST_TILE_MICRO (2 << 30)
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# define RADEON_DST_TILE_BOTH (3 << 30)
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# define RADEON_DST_TILE_MICRO (2U << 30)
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# define RADEON_DST_TILE_BOTH (3U << 30)
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#define RADEON_DST_WIDTH 0x140c
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#define RADEON_DST_WIDTH_HEIGHT 0x1598
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#define RADEON_DST_WIDTH_X 0x1588
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@ -294,7 +294,7 @@
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#define HE_REGO_CON_DAT 0x807F8
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#define HE_REGO_CON_CTL 0x807FC
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#define HE_REGM_CON_MBOX (2 << 30)
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#define HE_REGM_CON_MBOX (2U << 30)
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#define HE_REGM_CON_TCM (1 << 30)
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#define HE_REGM_CON_RCM (0 << 30)
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#define HE_REGM_CON_WE (1 << 29)
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