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Disable MSI-x for AHCI on Alpine plattform

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Changes introduced to AHCI code adding support for MSI-x
caused interrupt storm on Alpine boards.
This is unintended behaviour so added quirk to omit this functionality.

Reviewed by:   mav
Submitted by:  Marcin Mazurek <mma@semihalf.com>
Obtained from: Semihalf
Sponsored by:  Annapurna Labs
Differential Revision: https://reviews.freebsd.org/D4301
This commit is contained in:
Zbigniew Bodek 2016-03-31 11:18:52 +00:00
parent f2f21faf62
commit 5bf8f18273
2 changed files with 7 additions and 2 deletions
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4
sys/dev/ahci/ahci.h
View File

@ -597,6 +597,7 @@ enum ahci_err_type {
#define AHCI_Q_1MSI 0x00020000
#define AHCI_Q_FORCE_PI 0x00040000
#define AHCI_Q_RESTORE_CAP 0x00080000
#define AHCI_Q_NOMSIX 0x00100000
#define AHCI_Q_BIT_STRING \
"\020" \
@ -619,7 +620,8 @@ enum ahci_err_type {
"\021ABAR0" \
"\0221MSI" \
"\023FORCE_PI" \
"\024RESTORE_CAP"
"\024RESTORE_CAP" \
"\025NOMSIX"
int ahci_attach(device_t dev);
int ahci_detach(device_t dev);

5
sys/dev/ahci/ahci_pci.c
View File

@ -293,7 +293,7 @@ static const struct {
{0x11851039, 0x00, "SiS 968", 0},
{0x01861039, 0x00, "SiS 968", 0},
{0xa01c177d, 0x00, "ThunderX", AHCI_Q_ABAR0|AHCI_Q_1MSI},
{0x00311c36, 0x00, "Annapurna", AHCI_Q_FORCE_PI|AHCI_Q_RESTORE_CAP},
{0x00311c36, 0x00, "Annapurna", AHCI_Q_FORCE_PI|AHCI_Q_RESTORE_CAP|AHCI_Q_NOMSIX},
{0x00000000, 0x00, NULL, 0}
};
@ -437,6 +437,9 @@ ahci_pci_attach(device_t dev)
&ctlr->r_rid, RF_ACTIVE)))
return ENXIO;
if (ctlr->quirks & AHCI_Q_NOMSIX)
msix_count = 0;
/* Read MSI-x BAR IDs if supported */
if (msix_count > 0) {
error = ahci_pci_read_msix_bars(dev, &table_bar, &pba_bar);