Vendor import of llvm release_70 branch r338892:
https://llvm.org/svn/llvm-project/llvm/branches/release_70@338892
This commit is contained in:
Dimitry Andric
parent
b7eb8e35e4
commit
5c03f3e190
@ -32,7 +32,7 @@ if(NOT DEFINED LLVM_VERSION_PATCH)
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set(LLVM_VERSION_PATCH 0)
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endif()
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if(NOT DEFINED LLVM_VERSION_SUFFIX)
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set(LLVM_VERSION_SUFFIX svn)
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set(LLVM_VERSION_SUFFIX "")
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endif()
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if (NOT PACKAGE_VERSION)
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@ -557,8 +557,6 @@ if(LLVM_LINK_LLVM_DYLIB OR LLVM_BUILD_LLVM_C_DYLIB)
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endif()
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option(LLVM_BUILD_LLVM_DYLIB "Build libllvm dynamic library" ${LLVM_BUILD_LLVM_DYLIB_default})
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option(LLVM_DYLIB_SYMBOL_VERSIONING OFF)
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option(LLVM_OPTIMIZED_TABLEGEN "Force TableGen to be built with optimization" OFF)
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if(CMAKE_CROSSCOMPILING OR (LLVM_OPTIMIZED_TABLEGEN AND (LLVM_ENABLE_ASSERTIONS OR CMAKE_CONFIGURATION_TYPES)))
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set(LLVM_USE_HOST_TOOLS ON)
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@ -65,7 +65,7 @@ Non-comprehensive list of changes in this release
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results for code that is relying on the undefined behavior of overflowing
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casts. The optimization can be disabled by specifying a function attribute:
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"strict-float-cast-overflow"="false". This attribute may be created by the
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clang option :option:`-fno-strict-float-cast-overflow`.
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clang option ``-fno-strict-float-cast-overflow``.
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Code sanitizers can be used to detect affected patterns. The option for
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detecting this problem alone is "-fsanitize=float-cast-overflow":
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@ -109,6 +109,12 @@ Non-comprehensive list of changes in this release
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it's now a better choice even on the heap (although when TinyPtrVector works,
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it's even smaller).
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* Preliminary/experimental support for DWARF v5 debugging information,
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including the new .debug_names accelerator table. DWARF emitted at ``-O0``
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should be fully DWARF v5 compliant. Type units and split DWARF are known
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not to be compliant, and higher optimization levels will still emit some
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information in v4 format.
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* Note..
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.. NOTE
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@ -70,10 +70,9 @@ class DebugCounter {
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return instance().addCounter(Name, Desc);
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}
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inline static bool shouldExecute(unsigned CounterName) {
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// Compile to nothing when debugging is off
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#ifdef NDEBUG
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return true;
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#else
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if (!isCountingEnabled())
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return true;
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auto &Us = instance();
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auto Result = Us.Counters.find(CounterName);
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if (Result != Us.Counters.end()) {
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@ -93,7 +92,6 @@ class DebugCounter {
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}
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// Didn't find the counter, should we warn?
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return true;
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#endif // NDEBUG
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}
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// Return true if a given counter had values set (either programatically or on
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@ -142,7 +140,23 @@ class DebugCounter {
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}
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CounterVector::const_iterator end() const { return RegisteredCounters.end(); }
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// Force-enables counting all DebugCounters.
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//
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// Since DebugCounters are incompatible with threading (not only do they not
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// make sense, but we'll also see data races), this should only be used in
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// contexts where we're certain we won't spawn threads.
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static void enableAllCounters() { instance().Enabled = true; }
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private:
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static bool isCountingEnabled() {
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// Compile to nothing when debugging is off
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#ifdef NDEBUG
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return false;
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#else
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return instance().Enabled;
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#endif
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}
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unsigned addCounter(const std::string &Name, const std::string &Desc) {
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unsigned Result = RegisteredCounters.insert(Name);
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Counters[Result] = {};
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@ -159,6 +173,10 @@ class DebugCounter {
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};
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DenseMap<unsigned, CounterInfo> Counters;
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CounterVector RegisteredCounters;
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// Whether we should do DebugCounting at all. DebugCounters aren't
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// thread-safe, so this should always be false in multithreaded scenarios.
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bool Enabled = false;
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};
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#define DEBUG_COUNTER(VARNAME, COUNTERNAME, DESC) \
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@ -82,6 +82,7 @@ void DebugCounter::push_back(const std::string &Val) {
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<< " is not a registered counter\n";
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return;
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}
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enableAllCounters();
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Counters[CounterID].Skip = CounterVal;
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Counters[CounterID].IsSet = true;
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} else if (CounterPair.first.endswith("-count")) {
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@ -92,6 +93,7 @@ void DebugCounter::push_back(const std::string &Val) {
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<< " is not a registered counter\n";
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return;
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}
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enableAllCounters();
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Counters[CounterID].StopAfter = CounterVal;
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Counters[CounterID].IsSet = true;
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} else {
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@ -4639,7 +4639,9 @@ class BaseFPCondComparison<bit signalAllNans, RegisterClass regtype,
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multiclass FPCondComparison<bit signalAllNans, string mnemonic,
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SDPatternOperator OpNode = null_frag> {
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def Hrr : BaseFPCondComparison<signalAllNans, FPR16, mnemonic, []> {
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def Hrr : BaseFPCondComparison<signalAllNans, FPR16, mnemonic,
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[(set NZCV, (OpNode (f16 FPR16:$Rn), (f16 FPR16:$Rm), (i32 imm:$nzcv),
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(i32 imm:$cond), NZCV))]> {
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let Inst{23-22} = 0b11;
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let Predicates = [HasFullFP16];
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}
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@ -11761,6 +11761,14 @@ SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
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ShiftCst);
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}
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// Is this an extending load from an f32 to an f64?
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static bool isFPExtLoad(SDValue Op) {
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if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op.getNode()))
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return LD->getExtensionType() == ISD::EXTLOAD &&
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Op.getValueType() == MVT::f64;
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return false;
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}
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/// Reduces the number of fp-to-int conversion when building a vector.
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///
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/// If this vector is built out of floating to integer conversions,
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@ -11795,11 +11803,18 @@ combineElementTruncationToVectorTruncation(SDNode *N,
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SmallVector<SDValue, 4> Ops;
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EVT TargetVT = N->getValueType(0);
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for (int i = 0, e = N->getNumOperands(); i < e; ++i) {
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if (N->getOperand(i).getOpcode() != PPCISD::MFVSR)
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SDValue NextOp = N->getOperand(i);
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if (NextOp.getOpcode() != PPCISD::MFVSR)
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return SDValue();
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unsigned NextConversion = N->getOperand(i).getOperand(0).getOpcode();
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unsigned NextConversion = NextOp.getOperand(0).getOpcode();
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if (NextConversion != FirstConversion)
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return SDValue();
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// If we are converting to 32-bit integers, we need to add an FP_ROUND.
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// This is not valid if the input was originally double precision. It is
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// also not profitable to do unless this is an extending load in which
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// case doing this combine will allow us to combine consecutive loads.
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if (Is32Bit && !isFPExtLoad(NextOp.getOperand(0).getOperand(0)))
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return SDValue();
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if (N->getOperand(i) != FirstInput)
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IsSplat = false;
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}
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@ -11813,8 +11828,9 @@ combineElementTruncationToVectorTruncation(SDNode *N,
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// Now that we know we have the right type of node, get its operands
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for (int i = 0, e = N->getNumOperands(); i < e; ++i) {
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SDValue In = N->getOperand(i).getOperand(0);
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// For 32-bit values, we need to add an FP_ROUND node.
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if (Is32Bit) {
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// For 32-bit values, we need to add an FP_ROUND node (if we made it
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// here, we know that all inputs are extending loads so this is safe).
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if (In.isUndef())
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Ops.push_back(DAG.getUNDEF(SrcVT));
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else {
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@ -3494,6 +3494,17 @@ def DblToFlt {
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dag B1 = (f32 (fpround (f64 (extractelt v2f64:$B, 1))));
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}
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def ExtDbl {
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dag A0S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$A, 0))))));
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dag A1S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$A, 1))))));
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dag B0S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$B, 0))))));
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dag B1S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$B, 1))))));
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dag A0U = (i32 (PPCmfvsr (f64 (PPCfctiwuz (f64 (extractelt v2f64:$A, 0))))));
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dag A1U = (i32 (PPCmfvsr (f64 (PPCfctiwuz (f64 (extractelt v2f64:$A, 1))))));
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dag B0U = (i32 (PPCmfvsr (f64 (PPCfctiwuz (f64 (extractelt v2f64:$B, 0))))));
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dag B1U = (i32 (PPCmfvsr (f64 (PPCfctiwuz (f64 (extractelt v2f64:$B, 1))))));
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}
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def ByteToWord {
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dag LE_A0 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 0)), i8));
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dag LE_A1 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 4)), i8));
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@ -3571,9 +3582,15 @@ def FltToULong {
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}
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def DblToInt {
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dag A = (i32 (PPCmfvsr (f64 (PPCfctiwz f64:$A))));
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dag B = (i32 (PPCmfvsr (f64 (PPCfctiwz f64:$B))));
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dag C = (i32 (PPCmfvsr (f64 (PPCfctiwz f64:$C))));
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dag D = (i32 (PPCmfvsr (f64 (PPCfctiwz f64:$D))));
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}
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def DblToUInt {
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dag A = (i32 (PPCmfvsr (f64 (PPCfctiwuz f64:$A))));
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dag B = (i32 (PPCmfvsr (f64 (PPCfctiwuz f64:$B))));
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dag C = (i32 (PPCmfvsr (f64 (PPCfctiwuz f64:$C))));
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dag D = (i32 (PPCmfvsr (f64 (PPCfctiwuz f64:$D))));
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}
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def DblToLong {
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dag A = (i64 (PPCmfvsr (f64 (PPCfctidz f64:$A))));
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@ -3612,6 +3629,47 @@ def MrgFP {
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dag BAlToFlt = (XVCVDPSP (XXPERMDI $B, $A, 3));
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}
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// Word-element merge dags - conversions from f64 to i32 merged into vectors.
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def MrgWords {
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// For big endian, we merge low and hi doublewords (A, B).
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dag A0B0 = (v2f64 (XXPERMDI v2f64:$A, v2f64:$B, 0));
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dag A1B1 = (v2f64 (XXPERMDI v2f64:$A, v2f64:$B, 3));
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dag CVA1B1S = (v4i32 (XVCVDPSXWS A1B1));
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dag CVA0B0S = (v4i32 (XVCVDPSXWS A0B0));
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dag CVA1B1U = (v4i32 (XVCVDPUXWS A1B1));
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dag CVA0B0U = (v4i32 (XVCVDPUXWS A0B0));
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// For little endian, we merge low and hi doublewords (B, A).
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dag B1A1 = (v2f64 (XXPERMDI v2f64:$B, v2f64:$A, 0));
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dag B0A0 = (v2f64 (XXPERMDI v2f64:$B, v2f64:$A, 3));
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dag CVB1A1S = (v4i32 (XVCVDPSXWS B1A1));
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dag CVB0A0S = (v4i32 (XVCVDPSXWS B0A0));
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dag CVB1A1U = (v4i32 (XVCVDPUXWS B1A1));
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dag CVB0A0U = (v4i32 (XVCVDPUXWS B0A0));
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// For big endian, we merge hi doublewords of (A, C) and (B, D), convert
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// then merge.
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dag AC = (v2f64 (XXPERMDI (COPY_TO_REGCLASS f64:$A, VSRC),
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(COPY_TO_REGCLASS f64:$C, VSRC), 0));
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dag BD = (v2f64 (XXPERMDI (COPY_TO_REGCLASS f64:$B, VSRC),
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(COPY_TO_REGCLASS f64:$D, VSRC), 0));
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dag CVACS = (v4i32 (XVCVDPSXWS AC));
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dag CVBDS = (v4i32 (XVCVDPSXWS BD));
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dag CVACU = (v4i32 (XVCVDPUXWS AC));
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dag CVBDU = (v4i32 (XVCVDPUXWS BD));
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// For little endian, we merge hi doublewords of (D, B) and (C, A), convert
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// then merge.
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dag DB = (v2f64 (XXPERMDI (COPY_TO_REGCLASS f64:$D, VSRC),
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(COPY_TO_REGCLASS f64:$B, VSRC), 0));
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dag CA = (v2f64 (XXPERMDI (COPY_TO_REGCLASS f64:$C, VSRC),
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(COPY_TO_REGCLASS f64:$A, VSRC), 0));
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dag CVDBS = (v4i32 (XVCVDPSXWS DB));
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dag CVCAS = (v4i32 (XVCVDPSXWS CA));
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dag CVDBU = (v4i32 (XVCVDPUXWS DB));
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dag CVCAU = (v4i32 (XVCVDPUXWS CA));
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}
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// Patterns for BUILD_VECTOR nodes.
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let AddedComplexity = 400 in {
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@ -3679,6 +3737,20 @@ let AddedComplexity = 400 in {
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def : Pat<(v4f32 (build_vector DblToFlt.A0, DblToFlt.A1,
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DblToFlt.B0, DblToFlt.B1)),
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(v4f32 (VMRGEW MrgFP.ABhToFlt, MrgFP.ABlToFlt))>;
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// Convert 4 doubles to a vector of ints.
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def : Pat<(v4i32 (build_vector DblToInt.A, DblToInt.B,
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DblToInt.C, DblToInt.D)),
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(v4i32 (VMRGEW MrgWords.CVACS, MrgWords.CVBDS))>;
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def : Pat<(v4i32 (build_vector DblToUInt.A, DblToUInt.B,
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DblToUInt.C, DblToUInt.D)),
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(v4i32 (VMRGEW MrgWords.CVACU, MrgWords.CVBDU))>;
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def : Pat<(v4i32 (build_vector ExtDbl.A0S, ExtDbl.A1S,
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ExtDbl.B0S, ExtDbl.B1S)),
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(v4i32 (VMRGEW MrgWords.CVA0B0S, MrgWords.CVA1B1S))>;
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def : Pat<(v4i32 (build_vector ExtDbl.A0U, ExtDbl.A1U,
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ExtDbl.B0U, ExtDbl.B1U)),
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(v4i32 (VMRGEW MrgWords.CVA0B0U, MrgWords.CVA1B1U))>;
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}
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let Predicates = [IsLittleEndian, HasVSX] in {
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@ -3693,6 +3765,20 @@ let AddedComplexity = 400 in {
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def : Pat<(v4f32 (build_vector DblToFlt.A0, DblToFlt.A1,
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DblToFlt.B0, DblToFlt.B1)),
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(v4f32 (VMRGEW MrgFP.BAhToFlt, MrgFP.BAlToFlt))>;
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// Convert 4 doubles to a vector of ints.
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def : Pat<(v4i32 (build_vector DblToInt.A, DblToInt.B,
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DblToInt.C, DblToInt.D)),
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(v4i32 (VMRGEW MrgWords.CVDBS, MrgWords.CVCAS))>;
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def : Pat<(v4i32 (build_vector DblToUInt.A, DblToUInt.B,
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DblToUInt.C, DblToUInt.D)),
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(v4i32 (VMRGEW MrgWords.CVDBU, MrgWords.CVCAU))>;
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def : Pat<(v4i32 (build_vector ExtDbl.A0S, ExtDbl.A1S,
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ExtDbl.B0S, ExtDbl.B1S)),
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(v4i32 (VMRGEW MrgWords.CVB1A1S, MrgWords.CVB0A0S))>;
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def : Pat<(v4i32 (build_vector ExtDbl.A0U, ExtDbl.A1U,
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ExtDbl.B0U, ExtDbl.B1U)),
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(v4i32 (VMRGEW MrgWords.CVB1A1U, MrgWords.CVB0A0U))>;
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}
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let Predicates = [HasDirectMove] in {
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@ -738,6 +738,10 @@ bool X86FastISel::handleConstantAddresses(const Value *V, X86AddressMode &AM) {
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if (GV->isThreadLocal())
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return false;
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// Can't handle !absolute_symbol references yet.
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if (GV->isAbsoluteSymbolRef())
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return false;
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// RIP-relative addresses can't have additional register operands, so if
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// we've already folded stuff into the addressing mode, just force the
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// global value into its own register, which we can use as the basereg.
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@ -456,6 +456,36 @@ define i1 @test_fcmp_ord(half %a, half %b) #0 {
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ret i1 %r
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}
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; CHECK-COMMON-LABEL: test_fccmp:
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; CHECK-CVT: fcvt s0, h0
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; CHECK-CVT-NEXT: fmov s1, #8.00000000
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; CHECK-CVT-NEXT: fmov s2, #5.00000000
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; CHECK-CVT-NEXT: fcmp s0, s1
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; CHECK-CVT-NEXT: cset w8, gt
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; CHECK-CVT-NEXT: fcmp s0, s2
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; CHECK-CVT-NEXT: cset w9, mi
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; CHECK-CVT-NEXT: tst w8, w9
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; CHECK-CVT-NEXT: fcsel s0, s0, s2, ne
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; CHECK-CVT-NEXT: fcvt h0, s0
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; CHECK-CVT-NEXT: str h0, [x0]
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; CHECK-CVT-NEXT: ret
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; CHECK-FP16: fmov h1, #5.00000000
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; CHECK-FP16-NEXT: fcmp h0, h1
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; CHECK-FP16-NEXT: fmov h2, #8.00000000
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; CHECK-FP16-NEXT: fccmp h0, h2, #4, mi
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; CHECK-FP16-NEXT: fcsel h0, h0, h1, gt
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; CHECK-FP16-NEXT: str h0, [x0]
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; CHECK-FP16-NEXT: ret
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define void @test_fccmp(half %in, half* %out) {
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%cmp1 = fcmp ogt half %in, 0xH4800
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%cmp2 = fcmp olt half %in, 0xH4500
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%cond = and i1 %cmp1, %cmp2
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%result = select i1 %cond, half %in, half 0xH4500
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store half %result, half* %out
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ret void
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}
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; CHECK-CVT-LABEL: test_br_cc:
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; CHECK-CVT-NEXT: fcvt s1, h1
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; CHECK-CVT-NEXT: fcvt s0, h0
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@ -119,8 +119,8 @@
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;vector int spltCnstConvftoi() { //
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; return (vector int) 4.74f; //
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;} //
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||||
;// P8: 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws //
|
||||
;// P9: 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvdpsxws //
|
||||
;// P8: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
|
||||
;// P9: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
|
||||
;vector int fromRegsConvftoi(float a, float b, float c, float d) { //
|
||||
; return (vector int) { a, b, c, d }; //
|
||||
;} //
|
||||
@ -139,15 +139,15 @@
|
||||
;vector int fromDiffMemConsDConvftoi(float *ptr) { //
|
||||
; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; //
|
||||
;} //
|
||||
;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws //
|
||||
;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws //
|
||||
;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
|
||||
;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
|
||||
;// Note: if the consecutive loads learns to handle pre-inc, this can be: //
|
||||
;// sldi 2, load, xvcvspuxws //
|
||||
;vector int fromDiffMemVarAConvftoi(float *arr, int elem) { //
|
||||
; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; //
|
||||
;} //
|
||||
;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws //
|
||||
;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws //
|
||||
;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
|
||||
;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
|
||||
;// Note: if the consecutive loads learns to handle pre-inc, this can be: //
|
||||
;// sldi 2, 2 x load, vperm, xvcvspuxws //
|
||||
;vector int fromDiffMemVarDConvftoi(float *arr, int elem) { //
|
||||
@ -168,8 +168,8 @@
|
||||
;vector int spltCnstConvdtoi() { //
|
||||
; return (vector int) 4.74; //
|
||||
;} //
|
||||
;// P8: 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws //
|
||||
;// P9: 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws //
|
||||
;// P8: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
|
||||
;// P9: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
|
||||
;vector int fromRegsConvdtoi(double a, double b, double c, double d) { //
|
||||
; return (vector int) { a, b, c, d }; //
|
||||
;} //
|
||||
@ -178,25 +178,23 @@
|
||||
;vector int fromDiffConstsConvdtoi() { //
|
||||
; return (vector int) { 24.46, 234., 988.19, 422.39 }; //
|
||||
;} //
|
||||
;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvdpsp, vmrgew, //
|
||||
;// xvcvspsxws //
|
||||
;// P9: 2 x lxvx, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvdpsp, vmrgew, //
|
||||
;// xvcvspsxws //
|
||||
;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspsxws, vmrgew //
|
||||
;// P9: 2 x lxvx, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspsxws, vmrgew //
|
||||
;vector int fromDiffMemConsAConvdtoi(double *ptr) { //
|
||||
; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; //
|
||||
;} //
|
||||
;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws //
|
||||
;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws //
|
||||
;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
|
||||
;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
|
||||
;vector int fromDiffMemConsDConvdtoi(double *ptr) { //
|
||||
; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; //
|
||||
;} //
|
||||
;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws //
|
||||
;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws //
|
||||
;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
|
||||
;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
|
||||
;vector int fromDiffMemVarAConvdtoi(double *arr, int elem) { //
|
||||
; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; //
|
||||
;} //
|
||||
;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws //
|
||||
;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws //
|
||||
;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
|
||||
;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
|
||||
;vector int fromDiffMemVarDConvdtoi(double *arr, int elem) { //
|
||||
; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; //
|
||||
;} //
|
||||
@ -296,8 +294,8 @@
|
||||
;vector unsigned int spltCnstConvftoui() { //
|
||||
; return (vector unsigned int) 4.74f; //
|
||||
;} //
|
||||
;// P8: 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws //
|
||||
;// P9: 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws //
|
||||
;// P8: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
|
||||
;// P9: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
|
||||
;vector unsigned int fromRegsConvftoui(float a, float b, float c, float d) { //
|
||||
; return (vector unsigned int) { a, b, c, d }; //
|
||||
;} //
|
||||
@ -316,16 +314,16 @@
|
||||
;vector unsigned int fromDiffMemConsDConvftoui(float *ptr) { //
|
||||
; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; //
|
||||
;} //
|
||||
;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws //
|
||||
;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws //
|
||||
;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
|
||||
;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
|
||||
;// Note: if the consecutive loads learns to handle pre-inc, this can be: //
|
||||
;// sldi 2, load, xvcvspuxws //
|
||||
;vector unsigned int fromDiffMemVarAConvftoui(float *arr, int elem) { //
|
||||
; return (vector unsigned int) { arr[elem], arr[elem+1], //
|
||||
; arr[elem+2], arr[elem+3] }; //
|
||||
;} //
|
||||
;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws //
|
||||
;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws //
|
||||
;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
|
||||
;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
|
||||
;// Note: if the consecutive loads learns to handle pre-inc, this can be: //
|
||||
;// sldi 2, 2 x load, vperm, xvcvspuxws //
|
||||
;vector unsigned int fromDiffMemVarDConvftoui(float *arr, int elem) { //
|
||||
@ -347,8 +345,8 @@
|
||||
;vector unsigned int spltCnstConvdtoui() { //
|
||||
; return (vector unsigned int) 4.74; //
|
||||
;} //
|
||||
;// P8: 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws //
|
||||
;// P9: 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws //
|
||||
;// P8: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
|
||||
;// P9: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
|
||||
;vector unsigned int fromRegsConvdtoui(double a, double b, //
|
||||
; double c, double d) { //
|
||||
; return (vector unsigned int) { a, b, c, d }; //
|
||||
@ -358,25 +356,24 @@
|
||||
;vector unsigned int fromDiffConstsConvdtoui() { //
|
||||
; return (vector unsigned int) { 24.46, 234., 988.19, 422.39 }; //
|
||||
;} //
|
||||
;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvdpsp, vmrgew, //
|
||||
;// xvcvspuxws //
|
||||
;// P9: 2 x lxvx, xxmrgld, xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws //
|
||||
;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspuxws, vmrgew //
|
||||
;// P9: 2 x lxvx, xxmrgld, xxmrghd, 2 x xvcvspuxws, vmrgew //
|
||||
;vector unsigned int fromDiffMemConsAConvdtoui(double *ptr) { //
|
||||
; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; //
|
||||
;} //
|
||||
;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws //
|
||||
;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws //
|
||||
;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
|
||||
;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
|
||||
;vector unsigned int fromDiffMemConsDConvdtoui(double *ptr) { //
|
||||
; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; //
|
||||
;} //
|
||||
;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws //
|
||||
;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws //
|
||||
;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
|
||||
;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
|
||||
;vector unsigned int fromDiffMemVarAConvdtoui(double *arr, int elem) { //
|
||||
; return (vector unsigned int) { arr[elem], arr[elem+1], //
|
||||
; arr[elem+2], arr[elem+3] }; //
|
||||
;} //
|
||||
;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws //
|
||||
;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws //
|
||||
;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
|
||||
;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
|
||||
;vector unsigned int fromDiffMemVarDConvdtoui(double *arr, int elem) { //
|
||||
; return (vector unsigned int) { arr[elem], arr[elem-1], //
|
||||
; arr[elem-2], arr[elem-3] }; //
|
||||
@ -1253,28 +1250,24 @@ entry:
|
||||
; P8LE-LABEL: fromRegsConvftoi
|
||||
; P9BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3
|
||||
; P9BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4
|
||||
; P9BE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
|
||||
; P9BE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
|
||||
; P9BE-DAG: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
|
||||
; P9BE-DAG: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
|
||||
; P9BE: vmrgew v2, [[REG3]], [[REG4]]
|
||||
; P9BE: xvcvspsxws v2, v2
|
||||
; P9LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1
|
||||
; P9LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2
|
||||
; P9LE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
|
||||
; P9LE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
|
||||
; P9LE-DAG: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
|
||||
; P9LE-DAG: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
|
||||
; P9LE: vmrgew v2, [[REG4]], [[REG3]]
|
||||
; P9LE: xvcvspsxws v2, v2
|
||||
; P8BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3
|
||||
; P8BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4
|
||||
; P8BE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
|
||||
; P8BE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
|
||||
; P8BE-DAG: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
|
||||
; P8BE-DAG: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
|
||||
; P8BE: vmrgew v2, [[REG3]], [[REG4]]
|
||||
; P8BE: xvcvspsxws v2, v2
|
||||
; P8LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1
|
||||
; P8LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2
|
||||
; P8LE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
|
||||
; P8LE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
|
||||
; P8LE-DAG: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
|
||||
; P8LE-DAG: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
|
||||
; P8LE: vmrgew v2, [[REG4]], [[REG3]]
|
||||
; P8LE: xvcvspsxws v2, v2
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
@ -1529,28 +1522,24 @@ entry:
|
||||
; P8LE-LABEL: fromRegsConvdtoi
|
||||
; P9BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3
|
||||
; P9BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4
|
||||
; P9BE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
|
||||
; P9BE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
|
||||
; P9BE-DAG: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
|
||||
; P9BE-DAG: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
|
||||
; P9BE: vmrgew v2, [[REG3]], [[REG4]]
|
||||
; P9BE: xvcvspsxws v2, v2
|
||||
; P9LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1
|
||||
; P9LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2
|
||||
; P9LE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
|
||||
; P9LE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
|
||||
; P9LE-DAG: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
|
||||
; P9LE-DAG: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
|
||||
; P9LE: vmrgew v2, [[REG4]], [[REG3]]
|
||||
; P9LE: xvcvspsxws v2, v2
|
||||
; P8BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3
|
||||
; P8BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4
|
||||
; P8BE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
|
||||
; P8BE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
|
||||
; P8BE-DAG: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
|
||||
; P8BE-DAG: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
|
||||
; P8BE: vmrgew v2, [[REG3]], [[REG4]]
|
||||
; P8BE: xvcvspsxws v2, v2
|
||||
; P8LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1
|
||||
; P8LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2
|
||||
; P8LE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
|
||||
; P8LE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
|
||||
; P8LE-DAG: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
|
||||
; P8LE-DAG: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
|
||||
; P8LE: vmrgew v2, [[REG4]], [[REG3]]
|
||||
; P8LE: xvcvspsxws v2, v2
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
@ -1592,36 +1581,32 @@ entry:
|
||||
; P9BE-DAG: lxv [[REG2:[vs0-9]+]], 16(r3)
|
||||
; P9BE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG1]], [[REG2]]
|
||||
; P9BE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG1]], [[REG2]]
|
||||
; P9BE-DAG: xvcvdpsp [[REG5:[vs0-9]+]], [[REG3]]
|
||||
; P9BE-DAG: xvcvdpsp [[REG6:[vs0-9]+]], [[REG4]]
|
||||
; P9BE-DAG: xvcvdpsxws [[REG5:[vs0-9]+]], [[REG3]]
|
||||
; P9BE-DAG: xvcvdpsxws [[REG6:[vs0-9]+]], [[REG4]]
|
||||
; P9BE: vmrgew v2, [[REG6]], [[REG5]]
|
||||
; P9BE: xvcvspsxws v2, v2
|
||||
; P9LE-DAG: lxv [[REG1:[vs0-9]+]], 0(r3)
|
||||
; P9LE-DAG: lxv [[REG2:[vs0-9]+]], 16(r3)
|
||||
; P9LE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG2]], [[REG1]]
|
||||
; P9LE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG2]], [[REG1]]
|
||||
; P9LE-DAG: xvcvdpsp [[REG5:[vs0-9]+]], [[REG3]]
|
||||
; P9LE-DAG: xvcvdpsp [[REG6:[vs0-9]+]], [[REG4]]
|
||||
; P9LE-DAG: xvcvdpsxws [[REG5:[vs0-9]+]], [[REG3]]
|
||||
; P9LE-DAG: xvcvdpsxws [[REG6:[vs0-9]+]], [[REG4]]
|
||||
; P9LE: vmrgew v2, [[REG6]], [[REG5]]
|
||||
; P9LE: xvcvspsxws v2, v2
|
||||
; P8BE: lxvd2x [[REG1:[vs0-9]+]], 0, r3
|
||||
; P8BE: lxvd2x [[REG2:[vs0-9]+]], r3, r4
|
||||
; P8BE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG1]], [[REG2]]
|
||||
; P8BE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG1]], [[REG2]]
|
||||
; P8BE-DAG: xvcvdpsp [[REG5:[vs0-9]+]], [[REG3]]
|
||||
; P8BE-DAG: xvcvdpsp [[REG6:[vs0-9]+]], [[REG4]]
|
||||
; P8BE-DAG: xvcvdpsxws [[REG5:[vs0-9]+]], [[REG3]]
|
||||
; P8BE-DAG: xvcvdpsxws [[REG6:[vs0-9]+]], [[REG4]]
|
||||
; P8BE: vmrgew v2, [[REG6]], [[REG5]]
|
||||
; P8BE: xvcvspsxws v2, v2
|
||||
; P8LE: lxvd2x [[REG1:[vs0-9]+]], 0, r3
|
||||
; P8LE: lxvd2x [[REG2:[vs0-9]+]], r3, r4
|
||||
; P8LE-DAG: xxswapd [[REG3:[vs0-9]+]], [[REG1]]
|
||||
; P8LE-DAG: xxswapd [[REG4:[vs0-9]+]], [[REG2]]
|
||||
; P8LE-DAG: xxmrgld [[REG5:[vs0-9]+]], [[REG4]], [[REG3]]
|
||||
; P8LE-DAG: xxmrghd [[REG6:[vs0-9]+]], [[REG4]], [[REG3]]
|
||||
; P8LE-DAG: xvcvdpsp [[REG7:[vs0-9]+]], [[REG5]]
|
||||
; P8LE-DAG: xvcvdpsp [[REG8:[vs0-9]+]], [[REG6]]
|
||||
; P8LE-DAG: xvcvdpsxws [[REG7:[vs0-9]+]], [[REG5]]
|
||||
; P8LE-DAG: xvcvdpsxws [[REG8:[vs0-9]+]], [[REG6]]
|
||||
; P8LE: vmrgew v2, [[REG8]], [[REG7]]
|
||||
; P8LE: xvcvspsxws v2, v2
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readonly
|
||||
@ -1653,40 +1638,36 @@ entry:
|
||||
; P9BE: lfd
|
||||
; P9BE: xxmrghd
|
||||
; P9BE: xxmrghd
|
||||
; P9BE: xvcvdpsp
|
||||
; P9BE: xvcvdpsp
|
||||
; P9BE: vmrgew
|
||||
; P9BE: xvcvspsxws v2
|
||||
; P9BE: xvcvdpsxws
|
||||
; P9BE: xvcvdpsxws
|
||||
; P9BE: vmrgew v2
|
||||
; P9LE: lfd
|
||||
; P9LE: lfd
|
||||
; P9LE: lfd
|
||||
; P9LE: lfd
|
||||
; P9LE: xxmrghd
|
||||
; P9LE: xxmrghd
|
||||
; P9LE: xvcvdpsp
|
||||
; P9LE: xvcvdpsp
|
||||
; P9LE: vmrgew
|
||||
; P9LE: xvcvspsxws v2
|
||||
; P9LE: xvcvdpsxws
|
||||
; P9LE: xvcvdpsxws
|
||||
; P9LE: vmrgew v2
|
||||
; P8BE: lfdx
|
||||
; P8BE: lfd
|
||||
; P8BE: lfd
|
||||
; P8BE: lfd
|
||||
; P8BE: xxmrghd
|
||||
; P8BE: xxmrghd
|
||||
; P8BE: xvcvdpsp
|
||||
; P8BE: xvcvdpsp
|
||||
; P8BE: vmrgew
|
||||
; P8BE: xvcvspsxws v2
|
||||
; P8BE: xvcvdpsxws
|
||||
; P8BE: xvcvdpsxws
|
||||
; P8BE: vmrgew v2
|
||||
; P8LE: lfdx
|
||||
; P8LE: lfd
|
||||
; P8LE: lfd
|
||||
; P8LE: lfd
|
||||
; P8LE: xxmrghd
|
||||
; P8LE: xxmrghd
|
||||
; P8LE: xvcvdpsp
|
||||
; P8LE: xvcvdpsp
|
||||
; P8LE: vmrgew
|
||||
; P8LE: xvcvspsxws v2
|
||||
; P8LE: xvcvdpsxws
|
||||
; P8LE: xvcvdpsxws
|
||||
; P8LE: vmrgew v2
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readonly
|
||||
@ -1726,40 +1707,36 @@ entry:
|
||||
; P9BE: lfd
|
||||
; P9BE: xxmrghd
|
||||
; P9BE: xxmrghd
|
||||
; P9BE: xvcvdpsp
|
||||
; P9BE: xvcvdpsp
|
||||
; P9BE: vmrgew
|
||||
; P9BE: xvcvspsxws v2
|
||||
; P9BE: xvcvdpsxws
|
||||
; P9BE: xvcvdpsxws
|
||||
; P9BE: vmrgew v2
|
||||
; P9LE: lfdux
|
||||
; P9LE: lfd
|
||||
; P9LE: lfd
|
||||
; P9LE: lfd
|
||||
; P9LE: xxmrghd
|
||||
; P9LE: xxmrghd
|
||||
; P9LE: xvcvdpsp
|
||||
; P9LE: xvcvdpsp
|
||||
; P9LE: vmrgew
|
||||
; P9LE: xvcvspsxws v2
|
||||
; P9LE: xvcvdpsxws
|
||||
; P9LE: xvcvdpsxws
|
||||
; P9LE: vmrgew v2
|
||||
; P8BE: lfdux
|
||||
; P8BE: lfd
|
||||
; P8BE: lfd
|
||||
; P8BE: lfd
|
||||
; P8BE: xxmrghd
|
||||
; P8BE: xxmrghd
|
||||
; P8BE: xvcvdpsp
|
||||
; P8BE: xvcvdpsp
|
||||
; P8BE: vmrgew
|
||||
; P8BE: xvcvspsxws v2
|
||||
; P8BE: xvcvdpsxws
|
||||
; P8BE: xvcvdpsxws
|
||||
; P8BE: vmrgew v2
|
||||
; P8LE: lfdux
|
||||
; P8LE: lfd
|
||||
; P8LE: lfd
|
||||
; P8LE: lfd
|
||||
; P8LE: xxmrghd
|
||||
; P8LE: xxmrghd
|
||||
; P8LE: xvcvdpsp
|
||||
; P8LE: xvcvdpsp
|
||||
; P8LE: vmrgew
|
||||
; P8LE: xvcvspsxws v2
|
||||
; P8LE: xvcvdpsxws
|
||||
; P8LE: xvcvdpsxws
|
||||
; P8LE: vmrgew v2
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readonly
|
||||
@ -1799,40 +1776,36 @@ entry:
|
||||
; P9BE: lfd
|
||||
; P9BE: xxmrghd
|
||||
; P9BE: xxmrghd
|
||||
; P9BE: xvcvdpsp
|
||||
; P9BE: xvcvdpsp
|
||||
; P9BE: vmrgew
|
||||
; P9BE: xvcvspsxws v2
|
||||
; P9BE: xvcvdpsxws
|
||||
; P9BE: xvcvdpsxws
|
||||
; P9BE: vmrgew v2
|
||||
; P9LE: lfdux
|
||||
; P9LE: lfd
|
||||
; P9LE: lfd
|
||||
; P9LE: lfd
|
||||
; P9LE: xxmrghd
|
||||
; P9LE: xxmrghd
|
||||
; P9LE: xvcvdpsp
|
||||
; P9LE: xvcvdpsp
|
||||
; P9LE: vmrgew
|
||||
; P9LE: xvcvspsxws v2
|
||||
; P9LE: xvcvdpsxws
|
||||
; P9LE: xvcvdpsxws
|
||||
; P9LE: vmrgew v2
|
||||
; P8BE: lfdux
|
||||
; P8BE: lfd
|
||||
; P8BE: lfd
|
||||
; P8BE: lfd
|
||||
; P8BE: xxmrghd
|
||||
; P8BE: xxmrghd
|
||||
; P8BE: xvcvdpsp
|
||||
; P8BE: xvcvdpsp
|
||||
; P8BE: vmrgew
|
||||
; P8BE: xvcvspsxws v2
|
||||
; P8BE: xvcvdpsxws
|
||||
; P8BE: xvcvdpsxws
|
||||
; P8BE: vmrgew v2
|
||||
; P8LE: lfdux
|
||||
; P8LE: lfd
|
||||
; P8LE: lfd
|
||||
; P8LE: lfd
|
||||
; P8LE: xxmrghd
|
||||
; P8LE: xxmrghd
|
||||
; P8LE: xvcvdpsp
|
||||
; P8LE: xvcvdpsp
|
||||
; P8LE: vmrgew
|
||||
; P8LE: xvcvspsxws v2
|
||||
; P8LE: xvcvdpsxws
|
||||
; P8LE: xvcvdpsxws
|
||||
; P8LE: vmrgew v2
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
@ -2413,28 +2386,24 @@ entry:
|
||||
; P8LE-LABEL: fromRegsConvftoui
|
||||
; P9BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3
|
||||
; P9BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4
|
||||
; P9BE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
|
||||
; P9BE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
|
||||
; P9BE-DAG: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
|
||||
; P9BE-DAG: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
|
||||
; P9BE: vmrgew v2, [[REG3]], [[REG4]]
|
||||
; P9BE: xvcvspuxws v2, v2
|
||||
; P9LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1
|
||||
; P9LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2
|
||||
; P9LE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
|
||||
; P9LE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
|
||||
; P9LE-DAG: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
|
||||
; P9LE-DAG: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
|
||||
; P9LE: vmrgew v2, [[REG4]], [[REG3]]
|
||||
; P9LE: xvcvspuxws v2, v2
|
||||
; P8BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3
|
||||
; P8BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4
|
||||
; P8BE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
|
||||
; P8BE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
|
||||
; P8BE-DAG: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
|
||||
; P8BE-DAG: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
|
||||
; P8BE: vmrgew v2, [[REG3]], [[REG4]]
|
||||
; P8BE: xvcvspuxws v2, v2
|
||||
; P8LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1
|
||||
; P8LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2
|
||||
; P8LE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
|
||||
; P8LE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
|
||||
; P8LE-DAG: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
|
||||
; P8LE-DAG: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
|
||||
; P8LE: vmrgew v2, [[REG4]], [[REG3]]
|
||||
; P8LE: xvcvspuxws v2, v2
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
@ -2689,28 +2658,24 @@ entry:
|
||||
; P8LE-LABEL: fromRegsConvdtoui
|
||||
; P9BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3
|
||||
; P9BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4
|
||||
; P9BE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
|
||||
; P9BE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
|
||||
; P9BE-DAG: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
|
||||
; P9BE-DAG: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
|
||||
; P9BE: vmrgew v2, [[REG3]], [[REG4]]
|
||||
; P9BE: xvcvspuxws v2, v2
|
||||
; P9LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1
|
||||
; P9LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2
|
||||
; P9LE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
|
||||
; P9LE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
|
||||
; P9LE-DAG: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
|
||||
; P9LE-DAG: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
|
||||
; P9LE: vmrgew v2, [[REG4]], [[REG3]]
|
||||
; P9LE: xvcvspuxws v2, v2
|
||||
; P8BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3
|
||||
; P8BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4
|
||||
; P8BE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
|
||||
; P8BE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
|
||||
; P8BE-DAG: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
|
||||
; P8BE-DAG: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
|
||||
; P8BE: vmrgew v2, [[REG3]], [[REG4]]
|
||||
; P8BE: xvcvspuxws v2, v2
|
||||
; P8LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1
|
||||
; P8LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2
|
||||
; P8LE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
|
||||
; P8LE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
|
||||
; P8LE-DAG: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
|
||||
; P8LE-DAG: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
|
||||
; P8LE: vmrgew v2, [[REG4]], [[REG3]]
|
||||
; P8LE: xvcvspuxws v2, v2
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
@ -2752,36 +2717,32 @@ entry:
|
||||
; P9BE-DAG: lxv [[REG2:[vs0-9]+]], 16(r3)
|
||||
; P9BE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG1]], [[REG2]]
|
||||
; P9BE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG1]], [[REG2]]
|
||||
; P9BE-DAG: xvcvdpsp [[REG5:[vs0-9]+]], [[REG3]]
|
||||
; P9BE-DAG: xvcvdpsp [[REG6:[vs0-9]+]], [[REG4]]
|
||||
; P9BE-DAG: xvcvdpuxws [[REG5:[vs0-9]+]], [[REG3]]
|
||||
; P9BE-DAG: xvcvdpuxws [[REG6:[vs0-9]+]], [[REG4]]
|
||||
; P9BE: vmrgew v2, [[REG6]], [[REG5]]
|
||||
; P9BE: xvcvspuxws v2, v2
|
||||
; P9LE-DAG: lxv [[REG1:[vs0-9]+]], 0(r3)
|
||||
; P9LE-DAG: lxv [[REG2:[vs0-9]+]], 16(r3)
|
||||
; P9LE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG2]], [[REG1]]
|
||||
; P9LE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG2]], [[REG1]]
|
||||
; P9LE-DAG: xvcvdpsp [[REG5:[vs0-9]+]], [[REG3]]
|
||||
; P9LE-DAG: xvcvdpsp [[REG6:[vs0-9]+]], [[REG4]]
|
||||
; P9LE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG2]], [[REG1]]
|
||||
; P9LE-DAG: xvcvdpuxws [[REG5:[vs0-9]+]], [[REG3]]
|
||||
; P9LE-DAG: xvcvdpuxws [[REG6:[vs0-9]+]], [[REG4]]
|
||||
; P9LE: vmrgew v2, [[REG6]], [[REG5]]
|
||||
; P9LE: xvcvspuxws v2, v2
|
||||
; P8BE: lxvd2x [[REG1:[vs0-9]+]], 0, r3
|
||||
; P8BE: lxvd2x [[REG2:[vs0-9]+]], r3, r4
|
||||
; P8BE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG1]], [[REG2]]
|
||||
; P8BE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG1]], [[REG2]]
|
||||
; P8BE-DAG: xvcvdpsp [[REG5:[vs0-9]+]], [[REG3]]
|
||||
; P8BE-DAG: xvcvdpsp [[REG6:[vs0-9]+]], [[REG4]]
|
||||
; P8BE-DAG: xvcvdpuxws [[REG5:[vs0-9]+]], [[REG3]]
|
||||
; P8BE-DAG: xvcvdpuxws [[REG6:[vs0-9]+]], [[REG4]]
|
||||
; P8BE: vmrgew v2, [[REG6]], [[REG5]]
|
||||
; P8BE: xvcvspuxws v2, v2
|
||||
; P8LE: lxvd2x [[REG1:[vs0-9]+]], 0, r3
|
||||
; P8LE: lxvd2x [[REG2:[vs0-9]+]], r3, r4
|
||||
; P8LE-DAG: xxswapd [[REG3:[vs0-9]+]], [[REG1]]
|
||||
; P8LE-DAG: xxswapd [[REG4:[vs0-9]+]], [[REG2]]
|
||||
; P8LE-DAG: xxmrgld [[REG5:[vs0-9]+]], [[REG4]], [[REG3]]
|
||||
; P8LE-DAG: xxmrghd [[REG6:[vs0-9]+]], [[REG4]], [[REG3]]
|
||||
; P8LE-DAG: xvcvdpsp [[REG7:[vs0-9]+]], [[REG5]]
|
||||
; P8LE-DAG: xvcvdpsp [[REG8:[vs0-9]+]], [[REG6]]
|
||||
; P8LE-DAG: xvcvdpuxws [[REG7:[vs0-9]+]], [[REG5]]
|
||||
; P8LE-DAG: xvcvdpuxws [[REG8:[vs0-9]+]], [[REG6]]
|
||||
; P8LE: vmrgew v2, [[REG8]], [[REG7]]
|
||||
; P8LE: xvcvspuxws v2, v2
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readonly
|
||||
@ -2813,40 +2774,36 @@ entry:
|
||||
; P9BE: lfd
|
||||
; P9BE: xxmrghd
|
||||
; P9BE: xxmrghd
|
||||
; P9BE: xvcvdpsp
|
||||
; P9BE: xvcvdpsp
|
||||
; P9BE: vmrgew
|
||||
; P9BE: xvcvspuxws v2
|
||||
; P9BE: xvcvdpuxws
|
||||
; P9BE: xvcvdpuxws
|
||||
; P9BE: vmrgew v2
|
||||
; P9LE: lfd
|
||||
; P9LE: lfd
|
||||
; P9LE: lfd
|
||||
; P9LE: lfd
|
||||
; P9LE: xxmrghd
|
||||
; P9LE: xxmrghd
|
||||
; P9LE: xvcvdpsp
|
||||
; P9LE: xvcvdpsp
|
||||
; P9LE: vmrgew
|
||||
; P9LE: xvcvspuxws v2
|
||||
; P9LE: xvcvdpuxws
|
||||
; P9LE: xvcvdpuxws
|
||||
; P9LE: vmrgew v2
|
||||
; P8BE: lfdx
|
||||
; P8BE: lfd
|
||||
; P8BE: lfd
|
||||
; P8BE: lfd
|
||||
; P8BE: xxmrghd
|
||||
; P8BE: xxmrghd
|
||||
; P8BE: xvcvdpsp
|
||||
; P8BE: xvcvdpsp
|
||||
; P8BE: vmrgew
|
||||
; P8BE: xvcvspuxws v2
|
||||
; P8BE: xvcvdpuxws
|
||||
; P8BE: xvcvdpuxws
|
||||
; P8BE: vmrgew v2
|
||||
; P8LE: lfdx
|
||||
; P8LE: lfd
|
||||
; P8LE: lfd
|
||||
; P8LE: lfd
|
||||
; P8LE: xxmrghd
|
||||
; P8LE: xxmrghd
|
||||
; P8LE: xvcvdpsp
|
||||
; P8LE: xvcvdpsp
|
||||
; P8LE: vmrgew
|
||||
; P8LE: xvcvspuxws v2
|
||||
; P8LE: xvcvdpuxws
|
||||
; P8LE: xvcvdpuxws
|
||||
; P8LE: vmrgew v2
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readonly
|
||||
@ -2886,40 +2843,36 @@ entry:
|
||||
; P9BE: lfd
|
||||
; P9BE: xxmrghd
|
||||
; P9BE: xxmrghd
|
||||
; P9BE: xvcvdpsp
|
||||
; P9BE: xvcvdpsp
|
||||
; P9BE: vmrgew
|
||||
; P9BE: xvcvspuxws v2
|
||||
; P9BE: xvcvdpuxws
|
||||
; P9BE: xvcvdpuxws
|
||||
; P9BE: vmrgew v2
|
||||
; P9LE: lfdux
|
||||
; P9LE: lfd
|
||||
; P9LE: lfd
|
||||
; P9LE: lfd
|
||||
; P9LE: xxmrghd
|
||||
; P9LE: xxmrghd
|
||||
; P9LE: xvcvdpsp
|
||||
; P9LE: xvcvdpsp
|
||||
; P9LE: vmrgew
|
||||
; P9LE: xvcvspuxws v2
|
||||
; P9LE: xvcvdpuxws
|
||||
; P9LE: xvcvdpuxws
|
||||
; P9LE: vmrgew v2
|
||||
; P8BE: lfdux
|
||||
; P8BE: lfd
|
||||
; P8BE: lfd
|
||||
; P8BE: lfd
|
||||
; P8BE: xxmrghd
|
||||
; P8BE: xxmrghd
|
||||
; P8BE: xvcvdpsp
|
||||
; P8BE: xvcvdpsp
|
||||
; P8BE: vmrgew
|
||||
; P8BE: xvcvspuxws v2
|
||||
; P8BE: xvcvdpuxws
|
||||
; P8BE: xvcvdpuxws
|
||||
; P8BE: vmrgew v2
|
||||
; P8LE: lfdux
|
||||
; P8LE: lfd
|
||||
; P8LE: lfd
|
||||
; P8LE: lfd
|
||||
; P8LE: xxmrghd
|
||||
; P8LE: xxmrghd
|
||||
; P8LE: xvcvdpsp
|
||||
; P8LE: xvcvdpsp
|
||||
; P8LE: vmrgew
|
||||
; P8LE: xvcvspuxws v2
|
||||
; P8LE: xvcvdpuxws
|
||||
; P8LE: xvcvdpuxws
|
||||
; P8LE: vmrgew v2
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readonly
|
||||
@ -2959,40 +2912,36 @@ entry:
|
||||
; P9BE: lfd
|
||||
; P9BE: xxmrghd
|
||||
; P9BE: xxmrghd
|
||||
; P9BE: xvcvdpsp
|
||||
; P9BE: xvcvdpsp
|
||||
; P9BE: vmrgew
|
||||
; P9BE: xvcvspuxws v2
|
||||
; P9BE: xvcvdpuxws
|
||||
; P9BE: xvcvdpuxws
|
||||
; P9BE: vmrgew v2
|
||||
; P9LE: lfdux
|
||||
; P9LE: lfd
|
||||
; P9LE: lfd
|
||||
; P9LE: lfd
|
||||
; P9LE: xxmrghd
|
||||
; P9LE: xxmrghd
|
||||
; P9LE: xvcvdpsp
|
||||
; P9LE: xvcvdpsp
|
||||
; P9LE: vmrgew
|
||||
; P9LE: xvcvspuxws v2
|
||||
; P9LE: xvcvdpuxws
|
||||
; P9LE: xvcvdpuxws
|
||||
; P9LE: vmrgew v2
|
||||
; P8BE: lfdux
|
||||
; P8BE: lfd
|
||||
; P8BE: lfd
|
||||
; P8BE: lfd
|
||||
; P8BE: xxmrghd
|
||||
; P8BE: xxmrghd
|
||||
; P8BE: xvcvdpsp
|
||||
; P8BE: xvcvdpsp
|
||||
; P8BE: vmrgew
|
||||
; P8BE: xvcvspuxws v2
|
||||
; P8BE: xvcvdpuxws
|
||||
; P8BE: xvcvdpuxws
|
||||
; P8BE: vmrgew v2
|
||||
; P8LE: lfdux
|
||||
; P8LE: lfd
|
||||
; P8LE: lfd
|
||||
; P8LE: lfd
|
||||
; P8LE: xxmrghd
|
||||
; P8LE: xxmrghd
|
||||
; P8LE: xvcvdpsp
|
||||
; P8LE: xvcvdpsp
|
||||
; P8LE: vmrgew
|
||||
; P8LE: xvcvspuxws v2
|
||||
; P8LE: xvcvdpuxws
|
||||
; P8LE: xvcvdpuxws
|
||||
; P8LE: vmrgew v2
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
|
||||
28
test/CodeGen/X86/absolute-bit-mask-fastisel.ll
Normal file
28
test/CodeGen/X86/absolute-bit-mask-fastisel.ll
Normal file
@ -0,0 +1,28 @@
|
||||
; RUN: llc < %s | FileCheck %s
|
||||
; RUN: llc -relocation-model=pic < %s | FileCheck %s
|
||||
|
||||
; Regression test for PR38200
|
||||
|
||||
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
|
||||
target triple = "x86_64-unknown-linux-gnu"
|
||||
|
||||
@bit_mask8 = external hidden global i8, !absolute_symbol !0
|
||||
|
||||
declare void @f()
|
||||
|
||||
define void @foo8(i8* %ptr) noinline optnone {
|
||||
%load = load i8, i8* %ptr
|
||||
; CHECK: movl $bit_mask8, %ecx
|
||||
%and = and i8 %load, ptrtoint (i8* @bit_mask8 to i8)
|
||||
%icmp = icmp eq i8 %and, 0
|
||||
br i1 %icmp, label %t, label %f
|
||||
|
||||
t:
|
||||
call void @f()
|
||||
ret void
|
||||
|
||||
f:
|
||||
ret void
|
||||
}
|
||||
|
||||
!0 = !{i64 0, i64 256}
|
||||
@ -2,4 +2,4 @@ Test that llvm-ar exits with 1 when there is an error.
|
||||
|
||||
RUN: not llvm-ar e 2>&1 | FileCheck %s
|
||||
CHECK: unknown option e.
|
||||
CHECK: OVERVIEW: LLVM Archiver (llvm-ar)
|
||||
CHECK: OVERVIEW: LLVM Archiver
|
||||
|
||||
@ -63,46 +63,44 @@ USAGE: llvm-ranlib <archive-file>
|
||||
)";
|
||||
|
||||
const char ArHelp[] = R"(
|
||||
OVERVIEW: LLVM Archiver (llvm-ar)
|
||||
OVERVIEW: LLVM Archiver
|
||||
|
||||
This program archives bitcode files into single libraries
|
||||
|
||||
USAGE: llvm-ar [options] [relpos] [count] <archive-file> [members]...
|
||||
USAGE: llvm-ar [options] [-]<operation>[modifiers] [relpos] <archive> [files]
|
||||
llvm-ar -M [<mri-script]
|
||||
|
||||
OPTIONS:
|
||||
-M -
|
||||
-format - Archive format to create
|
||||
=default - default
|
||||
=gnu - gnu
|
||||
=darwin - darwin
|
||||
=bsd - bsd
|
||||
-plugin=<string> - plugin (ignored for compatibility
|
||||
-help - Display available options
|
||||
-version - Display the version of this program
|
||||
--format - Archive format to create
|
||||
=default - default
|
||||
=gnu - gnu
|
||||
=darwin - darwin
|
||||
=bsd - bsd
|
||||
--plugin=<string> - Ignored for compatibility
|
||||
--help - Display available options
|
||||
--version - Display the version of this program
|
||||
|
||||
OPERATIONS:
|
||||
d[NsS] - delete file(s) from the archive
|
||||
m[abiSs] - move file(s) in the archive
|
||||
p[kN] - print file(s) found in the archive
|
||||
q[ufsS] - quick append file(s) to the archive
|
||||
r[abfiuRsS] - replace or insert file(s) into the archive
|
||||
t - display contents of archive
|
||||
x[No] - extract file(s) from the archive
|
||||
d - delete [files] from the archive
|
||||
m - move [files] in the archive
|
||||
p - print [files] found in the archive
|
||||
q - quick append [files] to the archive
|
||||
r - replace or insert [files] into the archive
|
||||
s - act as ranlib
|
||||
t - display contents of archive
|
||||
x - extract [files] from the archive
|
||||
|
||||
MODIFIERS (operation specific):
|
||||
[a] - put file(s) after [relpos]
|
||||
[b] - put file(s) before [relpos] (same as [i])
|
||||
MODIFIERS:
|
||||
[a] - put [files] after [relpos]
|
||||
[b] - put [files] before [relpos] (same as [i])
|
||||
[c] - do not warn if archive had to be created
|
||||
[D] - use zero for timestamps and uids/gids (default)
|
||||
[i] - put file(s) before [relpos] (same as [b])
|
||||
[i] - put [files] before [relpos] (same as [b])
|
||||
[l] - ignored for compatibility
|
||||
[o] - preserve original dates
|
||||
[s] - create an archive index (cf. ranlib)
|
||||
[S] - do not build a symbol table
|
||||
[T] - create a thin archive
|
||||
[u] - update only files newer than archive contents
|
||||
[u] - update only [files] newer than archive contents
|
||||
[U] - use actual timestamps and uids/gids
|
||||
|
||||
MODIFIERS (generic):
|
||||
[c] - do not warn if the library had to be created
|
||||
[v] - be verbose about actions taken
|
||||
)";
|
||||
|
||||
|
||||
@ -59,10 +59,6 @@ endif()
|
||||
|
||||
target_link_libraries(LLVM PRIVATE ${LIB_NAMES})
|
||||
|
||||
if (LLVM_DYLIB_SYMBOL_VERSIONING)
|
||||
set_property(TARGET LLVM APPEND_STRING PROPERTY LINK_FLAGS " -Wl,--default-symver")
|
||||
endif()
|
||||
|
||||
if (APPLE)
|
||||
set_property(TARGET LLVM APPEND_STRING PROPERTY
|
||||
LINK_FLAGS
|
||||
|
||||
@ -17,7 +17,7 @@ set -e
|
||||
release=""
|
||||
rc=""
|
||||
rebranch="no"
|
||||
projects="llvm cfe test-suite compiler-rt libcxx libcxxabi clang-tools-extra polly lldb lld openmp libunwind"
|
||||
projects="llvm cfe test-suite compiler-rt libcxx libcxxabi clang-tools-extra polly lldb lld openmp libunwind debuginfo-tests"
|
||||
dryrun=""
|
||||
revision="HEAD"
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user