Lines were a bit too long. Wrap some of them to 60 columns.

Suggested by:   bjk@
MFC after:      3 days
This commit is contained in:
Sean Bruno 2012-06-04 22:46:04 +00:00
parent fe5cfeb46b
commit 5c8d326cba

View File

@ -28,7 +28,7 @@
.\"
.\" $FreeBSD$
.\"
.Dd June 1, 2012
.Dd June 4, 2012
.Dt BCE 4
.Os
.Sh NAME
@ -213,45 +213,58 @@ Enable/Disable strict RX frame size checking (default 0).
Enable/Disable frame header/payload splitting (default 1).
.It Va hw.bce.rx_pages
Set the number of memory pages assigned to recieve packets by the driver.
Due to alignment issues, this value can only be of the set 1, 2, 4 or 8 (default 2).
Due to alignment issues, this value can only be of the set
1, 2, 4 or 8 (default 2).
.It Va hw.bce.tx_pages
Set the number of memory pages assigned to transmit packets by the driver.
Due to alignment issues, this value can only be of the set 1, 2, 4 or 8 (default 2).
Set the number of memory pages assigned to transmit packets
by the driver.
Due to alignment issues, this value can only be of the set
1, 2, 4 or 8 (default 2).
.It Va hw.bce.rx_ticks
Time in microsecond ticks to wait before generating a status block updates due to RX processing activity.
Time in microsecond ticks to wait before generating a status
block updates due to RX processing activity.
Values from 0-100 are valid.
A value of 0 disables this status block update.
Cannot be set to 0 if hw.bce.rx_quick_cons_trip is also 0 (default 18).
Cannot be set to 0 if hw.bce.rx_quick_cons_trip is also 0
(default 18).
.It Va hw.bce.rx_ticks_int
Time in microsecond ticks to wait during RX interrupt processing before generating a status block update.
Time in microsecond ticks to wait during RX interrupt
processing before generating a status block update.
Values from 0-100 are valid.
Valid values are in the range from 0-100.
A value of 0 disables this status block update (default 18).
.It Va hw.bce.rx_quick_cons_trip
Number of RX Quick BD Chain entries that must be completed before a status block is generated.
Number of RX Quick BD Chain entries that must be completed
before a status block is generated.
Values from 0-256 are valid.
A value of 0 disables this status block update.
Cannot be set to 0 if hw.bce.rx_ticks is also 0 (default 6).
.It Va hw.bce.rx_quick_cons_trip_int
Number of RX quick BD entries that must be completed before a status block is generated duing interrupt processing.
Number of RX quick BD entries that must be completed before
a status block is generated duing interrupt processing.
Values from 0-256 are valid.
A value of 0 disables this status block update (default 6).
.It Va hw.bce.tx_ticks
Time in microsecond ticks to wait before a status block update is generated due to TX activitiy.
Time in microsecond ticks to wait before a status block
update is generated due to TX activitiy.
Values from 0-100 are valid.
A value of 0 disables this status block update.
Cannot be set to 0 if hw.bce.tx_quick_cons_trip is also 0 (default 80).
Cannot be set to 0 if hw.bce.tx_quick_cons_trip is also 0
(default 80).
.It Va hw.bce.tx_ticks_int
Time in microsecond ticks to wait in interrupt processing before a status block update is generated due to TX activity
Time in microsecond ticks to wait in interrupt processing
before a status block update is generated due to TX activity
Values from 0-100 are valid.
A value of 0 disables this status block update (default 80).
.It Va hw.bce.tx_cons_trip
How many TX Quick BD Chain entries that must be completed before a status block is generated.
How many TX Quick BD Chain entries that must be completed
before a status block is generated.
Values from 0-100 are valid.
A value of 0 disables this status block update.
Cannot be set to 0 if hw.bce.tx_ticks is also 0 (default 20).
.It Va hw.bce.tx_cons_trip_int
How many TX Quick BD Chain entries that must be completed before a status block is generated during an interrupt.
How many TX Quick BD Chain entries that must be completed
before a status block is generated during an interrupt.
Values from 0-100 are valid.
A value of 0 disables this status block update (default 20).
.El