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- Change the short hand representation of the various ASIC revisions

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- Implement the ONEDMA_AT_ONCE workaround as described in the
  5703/5704 eratta documents.
  Obtained from: NetBSD & Broadcom documentation
This commit is contained in:
Paul Saab 2003-05-03 22:58:45 +00:00
parent d9c32632b9
commit 5cba12d3bc
2 changed files with 47 additions and 11 deletions
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48
sys/dev/bge/if_bge.c
View File

@ -1003,6 +1003,7 @@ bge_chipinit(sc)
struct bge_softc *sc;
{
int i;
u_int32_t dma_rw_ctl;
/* Set endianness before we access any non-PCI registers. */
#if BYTE_ORDER == BIG_ENDIAN
@ -1042,14 +1043,45 @@ bge_chipinit(sc)
if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
BGE_PCISTATE_PCI_BUSMODE) {
/* Conventional PCI bus */
pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD|0x3F000F, 4);
dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
(0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
(0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
(0x0F);
} else {
/* PCI-X bus */
pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD|0x1B000F, 4);
/*
* The 5704 uses a different encoding of read/write
* watermarks.
*/
if (BGE_ASICREV(sc->bge_asicrev) == BGE_ASICREV_BCM5704)
dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
(0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
(0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
else
dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
(0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
(0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
(0x0F);
/*
* 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
* for hardware bugs.
*/
if (BGE_ASICREV(sc->bge_asicrev) == BGE_ASICREV_BCM5703 ||
BGE_ASICREV(sc->bge_asicrev) == BGE_ASICREV_BCM5704) {
u_int32_t tmp;
tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
if (tmp == 0x6 || tmp == 0x7)
dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
}
}
if (BGE_ASICREV(sc->bge_asicrev) == BGE_ASICREV_BCM5703 ||
BGE_ASICREV(sc->bge_asicrev) == BGE_ASICREV_BCM5704)
dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
/*
* Set up general mode register.
*/
@ -1415,7 +1447,7 @@ bge_blockinit(sc)
CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
} else {
BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
if (sc->bge_asicrev == BGE_ASICREV_BCM5700)
if (BGE_ASICREV(sc->bge_asicrev) == BGE_ASICREV_BCM5700)
CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
BGE_EVTENB_MI_INTERRUPT);
}
@ -1620,10 +1652,6 @@ bge_attach(dev)
pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
BGE_PCIMISCCTL_ASICREV;
/* Pretend all 5700s are the same */
if ((sc->bge_asicrev & 0xFF000000) == BGE_ASICREV_BCM5700)
sc->bge_asicrev = BGE_ASICREV_BCM5700;
/*
* Figure out what sort of media we have by checking the
* hardware config word in the first 32k of NIC internal memory,
@ -2037,7 +2065,7 @@ bge_intr(xsc)
* the interrupt handler.
*/
if (sc->bge_asicrev == BGE_ASICREV_BCM5700) {
if (BGE_ASICREV(sc->bge_asicrev) == BGE_ASICREV_BCM5700) {
u_int32_t status;
status = CSR_READ_4(sc, BGE_MAC_STS);

10
sys/dev/bge/if_bgereg.h
View File

@ -231,7 +231,11 @@
#define BGE_ASICREV_BCM5704_A2 0x20020000
/* shorthand one */
#define BGE_ASICREV_BCM5700 0x71000000
#define BGE_ASICREV(x) ((x) >> 28)
#define BGE_ASICREV_BCM5700 0x07
#define BGE_ASICREV_BCM5701 0x00
#define BGE_ASICREV_BCM5703 0x01
#define BGE_ASICREV_BCM5704 0x02
/* PCI DMA Read/Write Control register */
#define BGE_PCIDMARWCTL_MINDMA 0x000000FF
@ -239,11 +243,15 @@
#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800
#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000
#define BGE_PCIDMARWCTL_RD_WAT 0x00070000
# define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16
#define BGE_PCIDMARWCTL_WR_WAT 0x00380000
# define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19
#define BGE_PCIDMARWCTL_USE_MRM 0x00400000
#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000
#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000
# define BGE_PCIDMA_RWCTL_PCI_RD_CMD_SHIFT 24
#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000
# define BGE_PCIDMA_RWCTL_PCI_WR_CMD_SHIFT 28
#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000
#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100