Implement the AR933x interrupt driven UART code.
* Enable RX and host interrupts during bus probe/attach * Disable all interrupts (+ host ISR) during bus detach * Enable TX DONE interrupt only when we start transmitting; clear it when we're done. * The RX/TX FIFO depth is still conjecture on my part. I'll fix this shortly. * The TX FIFO interrupt isn't an "empty" interrupt, it's an "almost empty" interrupt. Sigh. So.. * .. in ar933x_bus_transmit(), wait for the FIFO to drain before continuing. I dislike having to wait for the FIFO to drain, alas. Tested: * Atheros AP121 board, AR9331 SoC. TODO: * RX/TX overflow, RX error, BREAK support, etc. * Figure out the true RX/TX FIFO depth.
This commit is contained in:
Adrian Chadd
parent
0580abc578
commit
5ccb3bf6af
@ -53,32 +53,6 @@ __FBSDID("$FreeBSD$");
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bus_space_write_4((bas)->bst, (bas)->bsh, reg, value)
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#if 0
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/*
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* Clear pending interrupts. THRE is cleared by reading IIR. Data
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* that may have been received gets lost here.
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*/
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static void
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ar933x_clrint(struct uart_bas *bas)
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{
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uint8_t iir, lsr;
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iir = uart_getreg(bas, REG_IIR);
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while ((iir & IIR_NOPEND) == 0) {
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iir &= IIR_IMASK;
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if (iir == IIR_RLS) {
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lsr = uart_getreg(bas, REG_LSR);
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if (lsr & (LSR_BI|LSR_FE|LSR_PE))
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(void)uart_getreg(bas, REG_DATA);
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} else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
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(void)uart_getreg(bas, REG_DATA);
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else if (iir == IIR_MLSC)
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(void)uart_getreg(bas, REG_MSR);
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uart_barrier(bas);
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iir = uart_getreg(bas, REG_IIR);
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}
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}
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#endif
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static int
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ar933x_drain(struct uart_bas *bas, int what)
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@ -386,11 +360,28 @@ struct uart_class uart_ar933x_class = {
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static int
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ar933x_bus_attach(struct uart_softc *sc)
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{
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struct ar933x_softc *u = (struct ar933x_softc *)sc;
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struct uart_bas *bas = &sc->sc_bas;
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uint32_t reg;
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/* XXX TODO: flush transmitter */
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/* XXX TODO: enable RX interrupts to kick-start things */
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/*
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* Setup initial interrupt notifications.
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*
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* XXX for now, just RX FIFO valid.
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* Later on (when they're handled), also handle
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* RX errors/overflow.
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*/
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u->u_ier = AR933X_UART_INT_RX_VALID;
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/* XXX TODO: enable the host interrupt now */
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/* Enable RX interrupts to kick-start things */
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ar933x_setreg(bas, AR933X_UART_INT_EN_REG, u->u_ier);
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/* Enable the host interrupt now */
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reg = ar933x_getreg(bas, AR933X_UART_CS_REG);
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reg |= AR933X_UART_CS_HOST_INT_EN;
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ar933x_setreg(bas, AR933X_UART_CS_REG, reg);
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return (0);
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}
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@ -398,21 +389,17 @@ ar933x_bus_attach(struct uart_softc *sc)
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static int
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ar933x_bus_detach(struct uart_softc *sc)
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{
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#if 0
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struct ar933x_softc *ns8250;
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struct uart_bas *bas;
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u_char ier;
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struct uart_bas *bas = &sc->sc_bas;
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uint32_t reg;
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ns8250 = (struct ar933x_softc *)sc;
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bas = &sc->sc_bas;
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ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
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uart_setreg(bas, REG_IER, ier);
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/* Disable all interrupts */
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ar933x_setreg(bas, AR933X_UART_INT_EN_REG, 0x00000000);
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/* Disable the host interrupt */
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reg = ar933x_getreg(bas, AR933X_UART_CS_REG);
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reg &= ~AR933X_UART_CS_HOST_INT_EN;
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ar933x_setreg(bas, AR933X_UART_CS_REG, reg);
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uart_barrier(bas);
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ar933x_clrint(bas);
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#endif
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/* XXX TODO: Disable all interrupts */
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/* XXX TODO: Disable the host interrupt */
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return (0);
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}
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@ -536,23 +523,63 @@ ar933x_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
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static int
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ar933x_bus_ipend(struct uart_softc *sc)
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{
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struct ar933x_softc *u = (struct ar933x_softc *)sc;
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struct uart_bas *bas = &sc->sc_bas;
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int ipend = 0;
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uint32_t isr;
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uart_lock(sc->sc_hwmtx);
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/*
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* Always notify the upper layer if RX is ready.
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* Fetch/ACK the ISR status.
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*/
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if (ar933x_rxready(bas)) {
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isr = ar933x_getreg(bas, AR933X_UART_INT_REG);
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ar933x_setreg(bas, AR933X_UART_INT_REG, isr);
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uart_barrier(bas);
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/*
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* RX ready - notify upper layer.
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*/
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if (isr & AR933X_UART_INT_RX_VALID) {
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ipend |= SER_INT_RXREADY;
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}
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/*
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* If we get this interrupt, we should disable
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* it from the interrupt mask and inform the uart
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* driver appropriately.
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*
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* We can't keep setting SER_INT_TXIDLE or SER_INT_SIGCHG
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* all the time or IO stops working. So we will always
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* clear this interrupt if we get it, then we only signal
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* the upper layer if we were doing active TX in the
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* first place.
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*
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* Also, the name is misleading. This actually means
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* "the FIFO is almost empty." So if we just write some
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* more data to the FIFO without checking whether it can
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* take said data, we'll overflow the thing.
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*
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* Unfortunately the FreeBSD uart device has no concept of
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* partial UART writes - it expects that the whole buffer
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* is written to the hardware. Thus for now, ar933x_bus_transmit()
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* will wait for the FIFO to finish draining before it pushes
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* more frames into it.
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*/
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if (isr & AR933X_UART_INT_TX_EMPTY) {
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/*
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* Update u_ier to disable TX notifications; update hardware
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*/
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u->u_ier &= ~AR933X_UART_INT_TX_EMPTY;
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ar933x_setreg(bas, AR933X_UART_INT_EN_REG, u->u_ier);
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uart_barrier(bas);
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}
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/*
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* Only signal TX idle if we're not busy transmitting.
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*/
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if (sc->sc_txbusy) {
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if ((ar933x_getreg(bas, AR933X_UART_DATA_REG)
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& AR933X_UART_DATA_TX_CSR)) {
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if (isr & AR933X_UART_INT_TX_EMPTY) {
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ipend |= SER_INT_TXIDLE;
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} else {
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ipend |= SER_INT_SIGCHG;
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@ -620,6 +647,7 @@ ar933x_bus_receive(struct uart_softc *sc)
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/* Remove that entry from said RX FIFO */
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ar933x_setreg(bas, AR933X_UART_DATA_REG,
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AR933X_UART_DATA_RX_CSR);
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uart_barrier(bas);
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/* XXX frame, parity error */
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uart_rx_put(sc, xc);
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@ -669,22 +697,51 @@ ar933x_bus_setsig(struct uart_softc *sc, int sig)
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return (0);
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}
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/*
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* Write the current transmit buffer to the TX FIFO.
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*
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* Unfortunately the FreeBSD uart device has no concept of
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* partial UART writes - it expects that the whole buffer
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* is written to the hardware. Thus for now, this will wait for
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* the FIFO to finish draining before it pushes more frames into it.
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*
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* If non-blocking operation is truely needed here, either
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* the FreeBSD uart device will need to handle partial writes
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* in xxx_bus_transmit(), or we'll need to do TX FIFO buffering
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* of our own here.
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*/
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static int
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ar933x_bus_transmit(struct uart_softc *sc)
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{
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struct uart_bas *bas = &sc->sc_bas;
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struct ar933x_softc *u = (struct ar933x_softc *)sc;
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int i;
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uart_lock(sc->sc_hwmtx);
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/* XXX wait for FIFO to be ready? */
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/* Wait for the FIFO to be clear - see above */
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while (ar933x_getreg(bas, AR933X_UART_CS_REG) &
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AR933X_UART_CS_TX_BUSY)
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;
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/*
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* Write some data!
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*/
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for (i = 0; i < sc->sc_txdatasz; i++) {
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/* Write the TX data */
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ar933x_setreg(bas, AR933X_UART_DATA_REG,
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(sc->sc_txbuf[i] & 0xff) | AR933X_UART_DATA_TX_CSR);
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uart_barrier(bas);
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}
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/*
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* Now that we're transmitting, get interrupt notification
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* when the FIFO is (almost) empty - see above.
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*/
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u->u_ier |= AR933X_UART_INT_TX_EMPTY;
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ar933x_setreg(bas, AR933X_UART_INT_EN_REG, u->u_ier);
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uart_barrier(bas);
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/*
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* Inform the upper layer that we are presently transmitting
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* data to the hardware; this will be cleared when the
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