This revision adds support to if_rt for more SoCs.
The SoCs I've tried the driver with include the following: RT3050, RT5350, RT3662, RT3883, MT7620, MT7621, MT7688. On boards, based on the above SoCs traffic is passing through correctly and the boards survive a flood ping with very little or no drops (drops may be caused elsewhere in my test setup, however). One issue still remains and needs to be fixed in the future: if_rt does not survive an ifconfig rt0 down/ifconfig rt0 up cycle. This issue existed before this commit as well, however. Reviewed by: ray Approved by: adrian (mentor) Sponsored by: Smartcom - Bulgaria AD Differential Revision: https://reviews.freebsd.org/D5864
This commit is contained in:
Stanislav Galabov
parent
e43d20993a
commit
5ce34567e6
@ -1,5 +1,5 @@
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/*-
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* Copyright (c) 2015, Stanislav Galabov
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* Copyright (c) 2015-2016, Stanislav Galabov
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* Copyright (c) 2014, Aleksandr A. Mityaev
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* Copyright (c) 2011, Aleksandr Rybalko
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* based on hard work
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@ -54,6 +54,7 @@ __FBSDID("$FreeBSD$");
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#include <vm/vm_param.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/pmap.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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@ -69,8 +70,10 @@ __FBSDID("$FreeBSD$");
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#if 0
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#include <mips/rt305x/rt305x_sysctlvar.h>
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#include <mips/rt305x/rt305xreg.h>
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#endif
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#ifdef IF_RT_PHY_SUPPORT
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#include "miibus_if.h"
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@ -89,19 +92,20 @@ __FBSDID("$FreeBSD$");
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#define RT_TX_WATCHDOG_TIMEOUT 5
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#define RT_CHIPID_RT3050 0x3050
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#define RT_CHIPID_RT3052 0x3052
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#define RT_CHIPID_RT5350 0x5350
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#define RT_CHIPID_RT6855 0x6855
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#define RT_CHIPID_MT7620 0x7620
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#define RT_CHIPID_MT7621 0x7621
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#ifdef FDT
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/* more specific and new models should go first */
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static const struct ofw_compat_data rt_compat_data[] = {
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{ "ralink,rt6855-eth", (uintptr_t)RT_CHIPID_RT6855 },
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{ "ralink,rt5350-eth", (uintptr_t)RT_CHIPID_RT5350 },
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{ "ralink,rt3052-eth", (uintptr_t)RT_CHIPID_RT3052 },
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{ "ralink,rt305x-eth", (uintptr_t)RT_CHIPID_RT3050 },
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{ NULL, (uintptr_t)NULL }
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{ "ralink,rt3050-eth", RT_CHIPID_RT3050 },
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{ "ralink,rt3352-eth", RT_CHIPID_RT3050 },
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{ "ralink,rt3883-eth", RT_CHIPID_RT3050 },
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{ "ralink,rt5350-eth", RT_CHIPID_RT5350 },
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{ "ralink,mt7620a-eth", RT_CHIPID_MT7620 },
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{ "ralink,mt7621-eth", RT_CHIPID_MT7621 },
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{ NULL, 0 }
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};
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#endif
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@ -182,21 +186,23 @@ rt_probe(device_t dev)
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const struct ofw_compat_data * cd;
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cd = ofw_bus_search_compatible(dev, rt_compat_data);
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if (cd->ocd_data == (uintptr_t)NULL)
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if (cd->ocd_data == 0)
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return (ENXIO);
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sc->rt_chipid = (unsigned int)(cd->ocd_data);
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#else
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#if defined(MT7620)
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sc->rt_chipid = RT_CHIPID_MT7620;
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#elif defined(MT7621)
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sc->rt_chipid = RT_CHIPID_MT7621;
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#elif defined(RT5350)
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sc->rt_chipid = RT_CHIPID_RT5350;
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#else
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sc->rt_chipid = RT_CHIPID_RT3050;
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#endif
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#endif
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snprintf(buf, sizeof(buf), "Ralink RT%x onChip Ethernet driver",
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sc->rt_chipid);
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snprintf(buf, sizeof(buf), "Ralink %cT%x onChip Ethernet driver",
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sc->rt_chipid >= 0x7600 ? 'M' : 'R', sc->rt_chipid);
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device_set_desc_copy(dev, buf);
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return (BUS_PROBE_GENERIC);
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}
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@ -373,12 +379,26 @@ rt_attach(device_t dev)
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/* Reset hardware */
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reset_freng(sc);
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if (sc->rt_chipid == RT_CHIPID_MT7620) {
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sc->csum_fail_ip = MT7620_RXD_SRC_IP_CSUM_FAIL;
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sc->csum_fail_l4 = MT7620_RXD_SRC_L4_CSUM_FAIL;
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} else if (sc->rt_chipid == RT_CHIPID_MT7621) {
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sc->csum_fail_ip = MT7621_RXD_SRC_IP_CSUM_FAIL;
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sc->csum_fail_l4 = MT7621_RXD_SRC_L4_CSUM_FAIL;
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} else {
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sc->csum_fail_ip = RT305X_RXD_SRC_IP_CSUM_FAIL;
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sc->csum_fail_l4 = RT305X_RXD_SRC_L4_CSUM_FAIL;
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}
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/* Fill in soc-specific registers map */
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switch(sc->rt_chipid) {
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case RT_CHIPID_MT7620:
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case RT_CHIPID_MT7621:
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case RT_CHIPID_RT5350:
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device_printf(dev, "RT%x Ethernet MAC (rev 0x%08x)\n",
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device_printf(dev, "%cT%x Ethernet MAC (rev 0x%08x)\n",
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sc->rt_chipid >= 0x7600 ? 'M' : 'R',
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sc->rt_chipid, sc->mac_rev);
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/* RT5350: No GDMA, PSE, CDMA, PPE */
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RT_WRITE(sc, GE_PORT_BASE + 0x0C00, // UDPCS, TCPCS, IPCS=1
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@ -406,10 +426,6 @@ rt_attach(device_t dev)
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sc->int_rx_done_mask=RT5350_INT_RXQ0_DONE;
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sc->int_tx_done_mask=RT5350_INT_TXQ0_DONE;
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break;
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case RT_CHIPID_RT6855:
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device_printf(dev, "RT6855 Ethernet MAC (rev 0x%08x)\n",
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sc->mac_rev);
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break;
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default:
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device_printf(dev, "RT305XF Ethernet MAC (rev 0x%08x)\n",
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sc->mac_rev);
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@ -533,7 +549,8 @@ rt_attach(device_t dev)
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/* set up interrupt */
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error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE,
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NULL, (sc->rt_chipid == RT_CHIPID_RT5350 ||
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sc->rt_chipid == RT_CHIPID_MT7620) ? rt_rt5350_intr : rt_intr,
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sc->rt_chipid == RT_CHIPID_MT7620 ||
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sc->rt_chipid == RT_CHIPID_MT7621) ? rt_rt5350_intr : rt_intr,
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sc, &sc->irqh);
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if (error != 0) {
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printf("%s: could not set up interrupt\n",
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@ -763,7 +780,7 @@ rt_init_locked(void *priv)
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//rt305x_sysctl_set(SYSCTL_RSTCTRL, SYSCTL_RSTCTRL_FRENG);
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/* Fwd to CPU (uni|broad|multi)cast and Unknown */
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if(sc->rt_chipid == RT_CHIPID_RT3050 || sc->rt_chipid == RT_CHIPID_RT3052)
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if(sc->rt_chipid == RT_CHIPID_RT3050)
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RT_WRITE(sc, GDMA1_BASE + GDMA_FWD_CFG,
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(
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GDM_ICS_EN | /* Enable IP Csum */
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@ -831,7 +848,8 @@ rt_init_locked(void *priv)
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/* write back DDONE, 16byte burst enable RX/TX DMA */
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tmp = FE_TX_WB_DDONE | FE_DMA_BT_SIZE16 | FE_RX_DMA_EN | FE_TX_DMA_EN;
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if (sc->rt_chipid == RT_CHIPID_MT7620)
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if (sc->rt_chipid == RT_CHIPID_MT7620 ||
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sc->rt_chipid == RT_CHIPID_MT7621)
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tmp |= (1<<31);
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RT_WRITE(sc, sc->pdma_glo_cfg, tmp);
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@ -843,7 +861,8 @@ rt_init_locked(void *priv)
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/* enable interrupts */
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if (sc->rt_chipid == RT_CHIPID_RT5350 ||
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sc->rt_chipid == RT_CHIPID_MT7620)
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sc->rt_chipid == RT_CHIPID_MT7620 ||
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sc->rt_chipid == RT_CHIPID_MT7621)
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tmp = RT5350_INT_TX_COHERENT |
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RT5350_INT_RX_COHERENT |
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RT5350_INT_TXQ3_DONE |
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@ -945,7 +964,8 @@ rt_stop_locked(void *priv)
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RT_WRITE(sc, sc->fe_int_enable, 0);
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if(sc->rt_chipid == RT_CHIPID_RT5350 ||
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sc->rt_chipid == RT_CHIPID_MT7620) {
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sc->rt_chipid == RT_CHIPID_MT7620 ||
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sc->rt_chipid == RT_CHIPID_MT7621) {
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} else {
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/* reset adapter */
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RT_WRITE(sc, GE_PORT_BASE + FE_RST_GLO, PSE_RESET);
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@ -1055,22 +1075,29 @@ rt_tx_data(struct rt_softc *sc, struct mbuf *m, int qid)
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/* TODO: this needs to be refined as MT7620 for example has
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* a different word3 layout than RT305x and RT5350 (the last
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* one doesn't use word3 at all).
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* one doesn't use word3 at all). And so does MT7621...
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*/
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/* Set destination */
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if (sc->rt_chipid != RT_CHIPID_MT7620)
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desc->dst = (TXDSCR_DST_PORT_GDMA1);
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if (sc->rt_chipid != RT_CHIPID_MT7621) {
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/* Set destination */
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if (sc->rt_chipid != RT_CHIPID_MT7620)
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desc->dst = (TXDSCR_DST_PORT_GDMA1);
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if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
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desc->dst |= (TXDSCR_IP_CSUM_GEN|TXDSCR_UDP_CSUM_GEN|
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TXDSCR_TCP_CSUM_GEN);
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/* Set queue id */
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desc->qn = qid;
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/* No PPPoE */
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desc->pppoe = 0;
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/* No VLAN */
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desc->vid = 0;
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if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
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desc->dst |= (TXDSCR_IP_CSUM_GEN |
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TXDSCR_UDP_CSUM_GEN | TXDSCR_TCP_CSUM_GEN);
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/* Set queue id */
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desc->qn = qid;
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/* No PPPoE */
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desc->pppoe = 0;
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/* No VLAN */
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desc->vid = 0;
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} else {
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desc->vid = 0;
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desc->pppoe = 0;
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desc->qn = 0;
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desc->dst = 2;
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}
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desc->sdp0 = htole32(dma_seg[i].ds_addr);
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desc->sdl0 = htole16(dma_seg[i].ds_len |
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@ -1714,7 +1741,8 @@ rt_tx_done_task(void *context, int pending)
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ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
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if(sc->rt_chipid == RT_CHIPID_RT5350 ||
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sc->rt_chipid == RT_CHIPID_MT7620)
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sc->rt_chipid == RT_CHIPID_MT7620 ||
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sc->rt_chipid == RT_CHIPID_MT7621)
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intr_mask = (
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RT5350_INT_TXQ3_DONE |
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RT5350_INT_TXQ2_DONE |
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@ -1870,15 +1898,13 @@ rt_rx_eof(struct rt_softc *sc, struct rt_softc_rx_ring *ring, int limit)
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BUS_DMASYNC_PREREAD);
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m = data->m;
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desc_flags = desc->src;
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desc_flags = desc->word3;
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data->m = mnew;
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/* Add 2 for proper align of RX IP header */
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desc->sdp0 = htole32(segs[0].ds_addr+2);
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desc->sdl0 = htole32(segs[0].ds_len-2);
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desc->src = 0;
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desc->ai = 0;
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desc->foe = 0;
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desc->word3 = 0;
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RT_DPRINTF(sc, RT_DEBUG_RX,
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"Rx frame: rxdesc flags=0x%08x\n", desc_flags);
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@ -1891,8 +1917,7 @@ rt_rx_eof(struct rt_softc *sc, struct rt_softc_rx_ring *ring, int limit)
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/* check for crc errors */
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if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
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/*check for valid checksum*/
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if (desc_flags & (RXDSXR_SRC_IP_CSUM_FAIL|
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RXDSXR_SRC_L4_CSUM_FAIL)) {
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if (desc_flags & (sc->csum_fail_ip|sc->csum_fail_l4)) {
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RT_DPRINTF(sc, RT_DEBUG_RX,
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"rxdesc: crc error\n");
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@ -1903,7 +1928,7 @@ rt_rx_eof(struct rt_softc *sc, struct rt_softc_rx_ring *ring, int limit)
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goto skip;
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}
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}
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if ((desc_flags & RXDSXR_SRC_IP_CSUM_FAIL) != 0) {
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if ((desc_flags & sc->csum_fail_ip) == 0) {
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m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
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m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
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m->m_pkthdr.csum_data = 0xffff;
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@ -2031,7 +2056,8 @@ rt_watchdog(struct rt_softc *sc)
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int ntries;
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#endif
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if(sc->rt_chipid != RT_CHIPID_RT5350 &&
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sc->rt_chipid != RT_CHIPID_MT7620) {
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sc->rt_chipid != RT_CHIPID_MT7620 &&
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sc->rt_chipid != RT_CHIPID_MT7621) {
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tmp = RT_READ(sc, PSE_BASE + CDMA_OQ_STA);
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RT_DPRINTF(sc, RT_DEBUG_WATCHDOG,
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@ -115,12 +115,21 @@ struct rt_txdesc
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} __packed;
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#define RT_RXDESC_SDL0_DDONE (1 << 15)
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#define RT305X_RXD_SRC_L4_CSUM_FAIL (1 << 28)
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#define RT305X_RXD_SRC_IP_CSUM_FAIL (1 << 29)
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#define MT7620_RXD_SRC_L4_CSUM_FAIL (1 << 22)
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#define MT7620_RXD_SRC_IP_CSUM_FAIL (1 << 25)
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#define MT7621_RXD_SRC_L4_CSUM_FAIL (1 << 23)
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#define MT7621_RXD_SRC_IP_CSUM_FAIL (1 << 26)
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struct rt_rxdesc
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{
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uint32_t sdp0;
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uint16_t sdl1;
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uint16_t sdl0;
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uint32_t sdp1;
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#if 0
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uint16_t foe;
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#define RXDSXR_FOE_ENTRY_VALID 0x40
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#define RXDSXR_FOE_ENTRY_MASK 0x3f
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@ -134,6 +143,8 @@ struct rt_rxdesc
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#define RXDSXR_SRC_L4_CSUM_FAIL 0x10
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#define RXDSXR_SRC_AIS 0x08
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#define RXDSXR_SRC_PORT_MASK 0x07
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#endif
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uint32_t word3;
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} __packed;
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struct rt_softc_rx_data
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@ -263,6 +274,8 @@ struct rt_softc
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uint32_t rt_chipid;
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/* chip specific registers config */
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int rx_ring_count;
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uint32_t csum_fail_l4;
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uint32_t csum_fail_ip;
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uint32_t int_rx_done_mask;
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uint32_t int_tx_done_mask;
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uint32_t delay_int_cfg;
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