d/freebsd-skq
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Fix two small bugs. The PowerPC 970 does not support non-coherent memory

Browse Source 
access, and reflects this by autonomously writing LPTE_M into PTE entries.
As such, we should not panic if LPTE_M changes by itself. While here,
fix a harmless typo in moea64_sync_icache().
This commit is contained in:
Nathan Whitehorn 2010-03-15 00:27:40 +00:00
parent b45923a62d
commit 5cf13d9573
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
sys/powerpc/aim/mmu_oea64.c
View File

@ -2268,7 +2268,7 @@ moea64_pvo_to_pte(const struct pvo_entry *pvo, int pteidx)
}
if (((pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo) &
~(LPTE_CHG|LPTE_REF)) != 0) {
~(LPTE_M|LPTE_CHG|LPTE_REF)) != 0) {
panic("moea64_pvo_to_pte: pvo %p pte does not match "
"pte %p in moea64_pteg_table difference is %#x",
pvo, pt,
@ -2511,7 +2511,7 @@ moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
len = MIN(lim - va, sz);
pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
if (pvo != NULL) {
pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) |
pa = (pvo->pvo_pte.pte.pte_lo & LPTE_RPGN) |
(va & ADDR_POFF);
moea64_syncicache(pm, va, pa, len);
}