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- Replace the magic numbers with something more readable.

Browse Source 
- Reset DMA indexes after disabling DMA.
This commit is contained in:
kevlo 2016-06-08 02:37:23 +00:00
parent b2dadb0e9a
commit 5d8bd6ca15
2 changed files with 25 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
sys/dev/ral/rt2860.c
View File

@ -900,7 +900,7 @@ rt2860_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni,
}
#endif
int
static int
rt2860_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
{
struct rt2860_vap *rvp = RT2860_VAP(vap);
@ -3824,9 +3824,16 @@ rt2860_init_locked(struct rt2860_softc *sc)
/* disable DMA */
tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
tmp &= 0xff0;
tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY |
RT2860_TX_DMA_EN);
tmp |= RT2860_TX_WB_DDONE;
RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
/* reset DMA indexes */
RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, RT2860_RST_DRX_IDX0 |
RT2860_RST_DTX_IDX5 | RT2860_RST_DTX_IDX4 | RT2860_RST_DTX_IDX3 |
RT2860_RST_DTX_IDX2 | RT2860_RST_DTX_IDX1 | RT2860_RST_DTX_IDX0);
/* PBF hardware reset */
RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f);
RAL_BARRIER_WRITE(sc);
@ -3858,7 +3865,9 @@ rt2860_init_locked(struct rt2860_softc *sc)
rt2860_stop_locked(sc);
return;
}
tmp &= 0xff0;
tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY |
RT2860_TX_DMA_EN);
tmp |= RT2860_TX_WB_DDONE;
RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
/* reset Rx ring and all 6 Tx rings */
@ -3958,7 +3967,9 @@ rt2860_init_locked(struct rt2860_softc *sc)
rt2860_stop_locked(sc);
return;
}
tmp &= 0xff0;
tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY |
RT2860_TX_DMA_EN);
tmp |= RT2860_TX_WB_DDONE;
RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
/* disable interrupts mitigation */

11
sys/dev/ral/rt2860reg.h
View File

@ -257,6 +257,15 @@
#define RT2860_TX_DMA_BUSY (1 << 1)
#define RT2860_TX_DMA_EN (1 << 0)
/* flags for register WPDMA_RST_IDX */
#define RT2860_RST_DRX_IDX0 (1 << 16)
#define RT2860_RST_DTX_IDX5 (1 << 5)
#define RT2860_RST_DTX_IDX4 (1 << 4)
#define RT2860_RST_DTX_IDX3 (1 << 3)
#define RT2860_RST_DTX_IDX2 (1 << 2)
#define RT2860_RST_DTX_IDX1 (1 << 1)
#define RT2860_RST_DTX_IDX0 (1 << 0)
/* possible flags for register DELAY_INT_CFG */
#define RT2860_TXDLY_INT_EN (1U << 31)
#define RT2860_TXMAX_PINT_SHIFT 24
@ -1233,7 +1242,7 @@ static const struct rt2860_rate {
{ 20, 0xba }, \
{ 21, 0xdb }, \
{ 24, 0x16 }, \
{ 25, 0x01 }, \
{ 25, 0x03 }, \
{ 29, 0x1f }
#define RT5390_DEF_RF \