From 5daa7f27c5de70744cc994bd4d4c4521c386d62a Mon Sep 17 00:00:00 2001 From: Warner Losh Date: Mon, 1 Jan 2018 04:10:25 +0000 Subject: [PATCH] Remove sys/mips/alchemy. It was still-born when I committed it and it never got better. It never worked on real hardware and is still mostly stubs after 8 years when I added it. It has had no real update in that time apart from API churn. It was added just so it didn't get lost in the project/mips merge, but maybe it should have been lost as nothing has come of it. It is time to give up the ghost on this one. Approved by: me, shooting my own dog Discussed on: mips@ --- sys/mips/alchemy/alchemy_machdep.c | 150 -------- sys/mips/alchemy/aureg.h | 377 -------------------- sys/mips/alchemy/files.alchemy | 9 - sys/mips/alchemy/obio.c | 534 ---------------------------- sys/mips/alchemy/std.alchemy | 8 - sys/mips/alchemy/uart_bus_alchemy.c | 89 ----- sys/mips/alchemy/uart_cpu_alchemy.c | 81 ----- sys/mips/conf/ALCHEMY | 65 ---- 8 files changed, 1313 deletions(-) delete mode 100644 sys/mips/alchemy/alchemy_machdep.c delete mode 100644 sys/mips/alchemy/aureg.h delete mode 100644 sys/mips/alchemy/files.alchemy delete mode 100644 sys/mips/alchemy/obio.c delete mode 100644 sys/mips/alchemy/std.alchemy delete mode 100644 sys/mips/alchemy/uart_bus_alchemy.c delete mode 100644 sys/mips/alchemy/uart_cpu_alchemy.c delete mode 100644 sys/mips/conf/ALCHEMY diff --git a/sys/mips/alchemy/alchemy_machdep.c b/sys/mips/alchemy/alchemy_machdep.c deleted file mode 100644 index 14f0845b6ea5..000000000000 --- a/sys/mips/alchemy/alchemy_machdep.c +++ /dev/null @@ -1,150 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (C) 2007 by Oleksandr Tymoshenko. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include -__FBSDID("$FreeBSD$"); - -#include "opt_ddb.h" - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -extern int *edata; -extern int *end; - -void -platform_cpu_init() -{ - /* Nothing special */ -} - -static void -mips_init(void) -{ - int i; - - printf("entry: mips_init()\n"); - - bootverbose = 1; - realmem = btoc(16 << 20); - - for (i = 0; i < 10; i++) { - phys_avail[i] = 0; - } - - /* phys_avail regions are in bytes */ - phys_avail[0] = MIPS_KSEG0_TO_PHYS(kernel_kseg0_end); - phys_avail[1] = ctob(realmem); - - dump_avail[0] = phys_avail[0]; - dump_avail[1] = phys_avail[1]; - - physmem = realmem; - - init_param1(); - init_param2(physmem); - mips_cpu_init(); - pmap_bootstrap(); - mips_proc0_init(); - mutex_init(); - - kdb_init(); -#ifdef KDB - if (boothowto & RB_KDB) - kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); -#endif -} - -void -platform_reset(void) -{ - - __asm __volatile("li $25, 0xbfc00000"); - __asm __volatile("j $25"); -} - -void -platform_start(__register_t a0 __unused, __register_t a1 __unused, - __register_t a2 __unused, __register_t a3 __unused) -{ - vm_offset_t kernend; - uint64_t platform_counter_freq = 175 * 1000 * 1000; - - /* clear the BSS and SBSS segments */ - kernend = (vm_offset_t)&end; - memset(&edata, 0, kernend - (vm_offset_t)(&edata)); - - mips_postboot_fixup(); - - /* Initialize pcpu stuff */ - mips_pcpu0_init(); - - cninit(); - mips_init(); - /* Set counter_freq for tick_init_params() */ - platform_counter_freq = 175 * 1000 * 1000; - - mips_timer_init_params(platform_counter_freq, 0); -} diff --git a/sys/mips/alchemy/aureg.h b/sys/mips/alchemy/aureg.h deleted file mode 100644 index f8e181695b05..000000000000 --- a/sys/mips/alchemy/aureg.h +++ /dev/null @@ -1,377 +0,0 @@ -/* $NetBSD: aureg.h,v 1.18 2006/10/02 06:44:00 gdamore Exp $ */ - -/*- - * SPDX-License-Identifier: BSD-4-Clause - * - * Copyright 2002 Wasabi Systems, Inc. - * All rights reserved. - * - * Written by Simon Burge for Wasabi Systems, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed for the NetBSD Project by - * Wasabi Systems, Inc. - * 4. The name of Wasabi Systems, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD$ - */ - -#ifndef _MIPS_ALCHEMY_AUREG_H -#define _MIPS_ALCHEMY_AUREG_H - -/************************************************************************/ -/******************** AC97 Controller registers *********************/ -/************************************************************************/ -#define AC97_BASE 0x10000000 - -/************************************************************************/ -/*********************** USB Host registers *************************/ -/************************************************************************/ -#define USBH_BASE 0x10100000 -#define AU1550_USBH_BASE 0x14020000 - -#define USBH_ENABLE 0x7fffc -#define USBH_SIZE 0x100000 - -#define AU1550_USBH_ENABLE 0x7ffc -#define AU1550_USBH_SIZE 0x60000 - -/************************************************************************/ -/********************** USB Device registers ************************/ -/************************************************************************/ -#define USBD_BASE 0x10200000 - -/************************************************************************/ -/************************* IRDA registers ***************************/ -/************************************************************************/ -#define IRDA_BASE 0x10300000 - -/************************************************************************/ -/****************** Interrupt Controller registers ******************/ -/************************************************************************/ - -#define IC0_BASE 0x10400000 -#define IC1_BASE 0x11800000 - -/* - * The *_READ registers read the current value of the register - * The *_SET registers set to 1 all bits that are written 1 - * The *_CLEAR registers clear to zero all bits that are written as 1 - */ -#define IC_CONFIG0_READ 0x40 /* See table below */ -#define IC_CONFIG0_SET 0x40 -#define IC_CONFIG0_CLEAR 0x44 - -#define IC_CONFIG1_READ 0x48 /* See table below */ -#define IC_CONFIG1_SET 0x48 -#define IC_CONFIG1_CLEAR 0x4c - -#define IC_CONFIG2_READ 0x50 /* See table below */ -#define IC_CONFIG2_SET 0x50 -#define IC_CONFIG2_CLEAR 0x54 - -#define IC_REQUEST0_INT 0x54 /* Show active interrupts on request 0 */ - -#define IC_SOURCE_READ 0x58 /* Interrupt source */ -#define IC_SOURCE_SET 0x58 /* 0 - test bit used as source */ -#define IC_SOURCE_CLEAR 0x5c /* 1 - peripheral/GPIO used as source */ - -#define IC_REQUEST1_INT 0x5c /* Show active interrupts on request 1 */ - -#define IC_ASSIGN_REQUEST_READ 0x60 /* Assigns the interrupt to one of the */ -#define IC_ASSIGN_REQUEST_SET 0x60 /* CPU requests (0 - assign to request 1, */ -#define IC_ASSIGN_REQUEST_CLEAR 0x64 /* 1 - assign to request 0) */ - -#define IC_WAKEUP_READ 0x68 /* Controls whether the interrupt can */ -#define IC_WAKEUP_SET 0x68 /* cause a wakeup from IDLE */ -#define IC_WAKEUP_CLEAR 0x6c - -#define IC_MASK_READ 0x70 /* Enables/Disables the interrupt */ -#define IC_MASK_SET 0x70 -#define IC_MASK_CLEAR 0x74 - -#define IC_RISING_EDGE 0x78 /* Check/clear rising edge */ - -#define IC_FALLING_EDGE 0x7c /* Check/clear falling edge */ - -#define IC_TEST_BIT 0x80 /* single bit source select */ - -/* - * Interrupt Configuration Register Functions - * - * Cfg2[n] Cfg1[n] Cfg0[n] Function - * 0 0 0 Interrupts Disabled - * 0 0 1 Rising Edge Enabled - * 0 1 0 Falling Edge Enabled - * 0 1 1 Rising and Falling Edge Enabled - * 1 0 0 Interrupts Disabled - * 1 0 1 High Level Enabled - * 1 1 0 Low Level Enabled - * 1 1 1 Both Levels and Both Edges Enabled - */ - -/************************************************************************/ -/************* Programable Serial Controller registers **************/ -/************************************************************************/ - -#define PSC0_BASE 0x11A00000 -#define PSC1_BASE 0x11B00000 -#define PSC2_BASE 0x10A00000 -#define PSC3_BASE 0x10B00000 - - -/************************************************************************/ -/********************** Ethernet MAC registers **********************/ -/************************************************************************/ - -#define MAC0_BASE 0x10500000 -#define MAC1_BASE 0x10510000 -#define MACx_SIZE 0x28 - -#define AU1500_MAC0_BASE 0x11500000 /* Grr, different on Au1500 */ -#define AU1500_MAC1_BASE 0x11510000 /* Grr, different on Au1500 */ - -#define MAC0_ENABLE 0x10520000 -#define MAC1_ENABLE 0x10520004 -#define MACENx_SIZE 0x04 - -#define AU1500_MAC0_ENABLE 0x11520000 /* Grr, different on Au1500 */ -#define AU1500_MAC1_ENABLE 0x11520004 /* Grr, different on Au1500 */ - -#define MAC0_DMA_BASE 0x14004000 -#define MAC1_DMA_BASE 0x14004200 -#define MACx_DMA_SIZE 0x140 - -/************************************************************************/ -/********************** Static Bus registers ************************/ -/************************************************************************/ -#define STATIC_BUS_BASE 0x14001000 - -/************************************************************************/ -/******************** Secure Digital registers **********************/ -/************************************************************************/ -#define SD0_BASE 0x10600000 -#define SD1_BASE 0x10680000 - -/************************************************************************/ -/************************* I^2S registers ***************************/ -/************************************************************************/ -#define I2S_BASE 0x11000000 - -/************************************************************************/ -/************************** UART registers **************************/ -/************************************************************************/ - -#define UART0_BASE 0x11100000 -#define UART1_BASE 0x11200000 -#define UART2_BASE 0x11300000 -#define UART3_BASE 0x11400000 - -/************************************************************************/ -/************************* SSI registers ****************************/ -/************************************************************************/ -#define SSI0_BASE 0x11600000 -#define SSI1_BASE 0x11680000 - -/************************************************************************/ -/************************ GPIO2 registers ***************************/ -/************************************************************************/ -#define GPIO_BASE 0x11900100 - -/************************************************************************/ -/************************ GPIO2 registers ***************************/ -/************************************************************************/ -#define GPIO2_BASE 0x11700000 - -/************************************************************************/ -/************************* PCI registers ****************************/ -/************************************************************************/ -#define PCI_BASE 0x14005000 -#define PCI_HEADER 0x14005100 -#define PCI_MEM_BASE 0x400000000ULL -#define PCI_IO_BASE 0x500000000ULL -#define PCI_CONFIG_BASE 0x600000000ULL - -/************************************************************************/ -/*********************** PCMCIA registers ***************************/ -/************************************************************************/ -#define PCMCIA_BASE 0xF00000000ULL - -/************************************************************************/ -/****************** Programmable Counter registers ******************/ -/************************************************************************/ - -#define SYS_BASE 0x11900000 - -#define PC_BASE SYS_BASE - -#define PC_TRIM0 0x00 /* PC0 Divide (16 bits) */ -#define PC_COUNTER_WRITE0 0x04 /* set PC0 */ -#define PC_MATCH0_0 0x08 /* match counter & interrupt */ -#define PC_MATCH1_0 0x0c /* match counter & interrupt */ -#define PC_MATCH2_0 0x10 /* match counter & interrupt */ -#define PC_COUNTER_CONTROL 0x14 /* Programmable Counter Control */ -#define CC_E1S 0x00800000 /* Enable PC1 write status */ -#define CC_T1S 0x00100000 /* Trim PC1 write status */ -#define CC_M21 0x00080000 /* Match 2 of PC1 write status */ -#define CC_M11 0x00040000 /* Match 1 of PC1 write status */ -#define CC_M01 0x00020000 /* Match 0 of PC1 write status */ -#define CC_C1S 0x00010000 /* PC1 write status */ -#define CC_BP 0x00004000 /* Bypass OSC (use GPIO1) */ -#define CC_EN1 0x00002000 /* Enable PC1 */ -#define CC_BT1 0x00001000 /* Bypass Trim on PC1 */ -#define CC_EN0 0x00000800 /* Enable PC0 */ -#define CC_BT0 0x00000400 /* Bypass Trim on PC0 */ -#define CC_EO 0x00000100 /* Enable Oscillator */ -#define CC_E0S 0x00000080 /* Enable PC0 write status */ -#define CC_32S 0x00000020 /* 32.768kHz OSC status */ -#define CC_T0S 0x00000010 /* Trim PC0 write status */ -#define CC_M20 0x00000008 /* Match 2 of PC0 write status */ -#define CC_M10 0x00000004 /* Match 1 of PC0 write status */ -#define CC_M00 0x00000002 /* Match 0 of PC0 write status */ -#define CC_C0S 0x00000001 /* PC0 write status */ -#define PC_COUNTER_READ_0 0x40 /* get PC0 */ -#define PC_TRIM1 0x44 /* PC1 Divide (16 bits) */ -#define PC_COUNTER_WRITE1 0x48 /* set PC1 */ -#define PC_MATCH0_1 0x4c /* match counter & interrupt */ -#define PC_MATCH1_1 0x50 /* match counter & interrupt */ -#define PC_MATCH2_1 0x54 /* match counter & interrupt */ -#define PC_COUNTER_READ_1 0x58 /* get PC1 */ - -#define PC_SIZE 0x5c /* size of register set */ -#define PC_RATE 32768 /* counter rate is 32.768kHz */ - -/************************************************************************/ -/******************* Frequency Generator Registers ******************/ -/************************************************************************/ - -#define SYS_FREQCTRL0 (SYS_BASE + 0x20) -#define SFC_FRDIV2(f) (f<<22) /* 29:22. Freq Divider 2 */ -#define SFC_FE2 (1<<21) /* Freq generator output enable 2 */ -#define SFC_FS2 (1<<20) /* Freq generator source 2 */ -#define SFC_FRDIV1(f) (f<<12) /* 19:12. Freq Divider 1 */ -#define SFC_FE1 (1<<11) /* Freq generator output enable 1 */ -#define SFC_FS1 (1<<10) /* Freq generator source 1 */ -#define SFC_FRDIV0(f) (f<<2) /* 9:2. Freq Divider 0 */ -#define SFC_FE0 2 /* Freq generator output enable 0 */ -#define SFC_FS0 1 /* Freq generator source 0 */ - -#define SYS_FREQCTRL1 (SYS_BASE + 0x24) -#define SFC_FRDIV5(f) (f<<22) /* 29:22. Freq Divider 5 */ -#define SFC_FE5 (1<<21) /* Freq generator output enable 5 */ -#define SFC_FS5 (1<<20) /* Freq generator source 5 */ -#define SFC_FRDIV4(f) (f<<12) /* 19:12. Freq Divider 4 */ -#define SFC_FE4 (1<<11) /* Freq generator output enable 4 */ -#define SFC_FS4 (1<<10) /* Freq generator source 4 */ -#define SFC_FRDIV3(f) (f<<2) /* 9:2. Freq Divider 3 */ -#define SFC_FE3 2 /* Freq generator output enable 3 */ -#define SFC_FS3 1 /* Freq generator source 3 */ - -/************************************************************************/ -/****************** Clock Source Control Registers ******************/ -/************************************************************************/ - -#define SYS_CLKSRC (SYS_BASE + 0x28) -#define SCS_ME1(n) (n<<27) /* EXTCLK1 Clock Mux input select */ -#define SCS_ME0(n) (n<<22) /* EXTCLK0 Clock Mux input select */ -#define SCS_MPC(n) (n<<17) /* PCI clock mux input select */ -#define SCS_MUH(n) (n<<12) /* USB Host clock mux input select */ -#define SCS_MUD(n) (n<<7) /* USB Device clock mux input select */ -#define SCS_MEx_AUX 0x1 /* Aux clock */ -#define SCS_MEx_FREQ0 0x2 /* FREQ0 */ -#define SCS_MEx_FREQ1 0x3 /* FREQ1 */ -#define SCS_MEx_FREQ2 0x4 /* FREQ2 */ -#define SCS_MEx_FREQ3 0x5 /* FREQ3 */ -#define SCS_MEx_FREQ4 0x6 /* FREQ4 */ -#define SCS_MEx_FREQ5 0x7 /* FREQ5 */ -#define SCS_DE1 (1<<26) /* EXTCLK1 clock divider select */ -#define SCS_CE1 (1<<25) /* EXTCLK1 clock select */ -#define SCS_DE0 (1<<21) /* EXTCLK0 clock divider select */ -#define SCS_CE0 (1<<20) /* EXTCLK0 clock select */ -#define SCS_DPC (1<<16) /* PCI clock divider select */ -#define SCS_CPC (1<<15) /* PCI clock select */ -#define SCS_DUH (1<<11) /* USB Host clock divider select */ -#define SCS_CUH (1<<10) /* USB Host clock select */ -#define SCS_DUD (1<<6) /* USB Device clock divider select */ -#define SCS_CUD (1<<5) /* USB Device clock select */ -/* - * Au1550 bits, needed for PSCs. Note that some bits collide with - * earlier parts. On Au1550, USB clocks (both device and host) are - * shared with PSC2, and must be configured for 48MHz. DBAU1550 YAMON - * does this by default. Also, EXTCLK0 is shared with PSC3. DBAU1550 - * YAMON does not configure any clocks besides PSC2. - */ -#define SCS_MP3(n) (n<<22) /* psc3_intclock mux */ -#define SCS_DP3 (1<<21) /* psc3_intclock divider */ -#define SCS_CP3 (1<<20) /* psc3_intclock select */ -#define SCS_MP1(n) (n<<12) /* psc1_intclock mux */ -#define SCS_DP1 (1<<11) /* psc1_intclock divider */ -#define SCS_CP1 (1<<10) /* psc1_intclock select */ -#define SCS_MP0(n) (n<<7) /* psc0_intclock mux */ -#define SCS_DP0 (1<<6) /* psc0_intclock divider */ -#define SCS_CP0 (1<<5) /* psc0_intclock seelct */ -#define SCS_MP2(n) (n<<2) /* psc2_intclock mux */ -#define SCS_DP2 (1<<1) /* psc2_intclock divider */ -#define SCS_CP2 (1<<0) /* psc2_intclock select */ - -/************************************************************************/ -/*************************** PIN Function *****************************/ -/************************************************************************/ - -#define SYS_PINFUNC (SYS_BASE + 0x2c) -#define SPF_PSC3_MASK (7<<20) -#define SPF_PSC3_AC97 (0<<17) /* select AC97/SPI */ -#define SPF_PSC3_I2S (1<<17) /* select I2S */ -#define SPF_PSC3_SMBUS (3<<17) /* select SMbus */ -#define SPF_PSC3_GPIO (7<<17) /* select gpio215:211 */ -#define SPF_PSC2_MASK (7<<17) -#define SPF_PSC2_AC97 (0<<17) /* select AC97/SPI */ -#define SPF_PSC2_I2S (1<<17) /* select I2S */ -#define SPF_PSC2_SMBUS (3<<17) /* select SMbus */ -#define SPF_PSC2_GPIO (7<<17) /* select gpio210:206*/ -#define SPF_CS (1<<16) /* extclk0 or 32kHz osc */ -#define SPF_USB (1<<15) /* host or device usb otg */ -#define SPF_U3T (1<<14) /* uart3 tx or gpio23 */ -#define SPF_U1R (1<<13) /* uart1 rx or gpio22 */ -#define SPF_U1T (1<<12) /* uart1 tx or gpio21 */ -#define SPF_EX1 (1<<10) /* gpio3 or extclk1 */ -#define SPF_EX0 (1<<9) /* gpio2 or extclk0/32kHz osc*/ -#define SPF_U3 (1<<7) /* gpio14:9 or uart3 */ -#define SPF_MBSa (1<<5) /* must be set */ -#define SPF_NI2 (1<<4) /* enet1 or gpio28:24 */ -#define SPF_U0 (1<<3) /* uart0 or gpio20 */ -#define SPF_MBSb (1<<2) /* must be set */ -#define SPF_S1 (1<<1) /* gpio17 or psc1_sync1 */ -#define SPF_S0 (1<<0) /* gpio16 or psc0_sync1 */ - -/************************************************************************/ -/*************************** PLL Control *****************************/ -/************************************************************************/ - -#define SYS_CPUPLL (SYS_BASE + 0x60) -#define SYS_AUXPLL (SYS_BASE + 0x64) - -#endif /* _MIPS_ALCHEMY_AUREG_H */ diff --git a/sys/mips/alchemy/files.alchemy b/sys/mips/alchemy/files.alchemy deleted file mode 100644 index 240869cdcbb4..000000000000 --- a/sys/mips/alchemy/files.alchemy +++ /dev/null @@ -1,9 +0,0 @@ -# $FreeBSD$ -# Alchmy on-board devices -# mips/alchemy/console.c standard -mips/alchemy/alchemy_machdep.c standard -mips/alchemy/obio.c standard -mips/alchemy/uart_bus_alchemy.c optional uart -mips/alchemy/uart_cpu_alchemy.c optional uart -mips/mips/intr_machdep.c standard -mips/mips/tick.c standard diff --git a/sys/mips/alchemy/obio.c b/sys/mips/alchemy/obio.c deleted file mode 100644 index 924cb08907d9..000000000000 --- a/sys/mips/alchemy/obio.c +++ /dev/null @@ -1,534 +0,0 @@ -/* $NetBSD: obio.c,v 1.11 2003/07/15 00:25:05 lukem Exp $ */ - -/*- - * SPDX-License-Identifier: BSD-4-Clause - * - * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc. - * All rights reserved. - * - * Written by Jason R. Thorpe for Wasabi Systems, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed for the NetBSD Project by - * Wasabi Systems, Inc. - * 4. The name of Wasabi Systems, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include - -/* MIPS HW interrupts of IRQ/FIQ respectively */ -#define ADM5120_INTR 0 -#define ADM5120_FAST_INTR 1 - -/* Interrupt levels */ -#define INTR_IRQ 0 -#define INTR_FIQ 1 - -int irq_priorities[NIRQS] = { - INTR_IRQ, /* flash */ - INTR_FIQ, /* uart0 */ - INTR_FIQ, /* uart1 */ - INTR_IRQ, /* ahci */ - INTR_IRQ, /* unknown */ - INTR_IRQ, /* unknown */ - INTR_IRQ, /* unknown */ - INTR_IRQ, /* unknown */ - INTR_IRQ, /* unknown */ - INTR_IRQ, /* admsw */ - INTR_IRQ, /* unknown */ - INTR_IRQ, /* unknown */ - INTR_IRQ, /* unknown */ - INTR_IRQ, /* unknown */ - INTR_IRQ, /* unknown */ - INTR_IRQ, /* unknown */ - INTR_IRQ, /* unknown */ - INTR_IRQ, /* unknown */ - INTR_IRQ, /* unknown */ - INTR_IRQ, /* unknown */ - INTR_IRQ, /* unknown */ - INTR_IRQ, /* unknown */ - INTR_IRQ, /* unknown */ - INTR_IRQ, /* unknown */ - INTR_IRQ, /* unknown */ - INTR_IRQ, /* unknown */ - INTR_IRQ, /* unknown */ - INTR_IRQ, /* unknown */ - INTR_IRQ, /* unknown */ - INTR_IRQ, /* unknown */ - INTR_IRQ, /* unknown */ - INTR_IRQ, /* unknown */ -}; - - -#define REG_READ(o) *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(ADM5120_BASE_ICU + (o))) -#define REG_WRITE(o,v) (REG_READ(o)) = (v) - -static int obio_activate_resource(device_t, device_t, int, int, - struct resource *); -static device_t obio_add_child(device_t, u_int, const char *, int); -static struct resource * - obio_alloc_resource(device_t, device_t, int, int *, rman_res_t, - rman_res_t, rman_res_t, u_int); -static int obio_attach(device_t); -static int obio_deactivate_resource(device_t, device_t, int, int, - struct resource *); -static struct resource_list * - obio_get_resource_list(device_t, device_t); -static void obio_hinted_child(device_t, const char *, int); -static int obio_intr(void *); -static int obio_probe(device_t); -static int obio_release_resource(device_t, device_t, int, int, - struct resource *); -static int obio_setup_intr(device_t, device_t, struct resource *, int, - driver_filter_t *, driver_intr_t *, void *, void **); -static int obio_teardown_intr(device_t, device_t, struct resource *, - void *); - -static void -obio_mask_irq(void *arg) -{ - /* XXX need to write */ -#if 0 - unsigned int irq = (unsigned int)arg; - int ip_bit, mask, mask_register; - - /* mask IRQ */ - mask_register = ICU_IRQ_MASK_REG(irq); - ip_bit = ICU_IP_BIT(irq); - - mask = ICU_REG_READ(mask_register); - ICU_REG_WRITE(mask_register, mask | ip_bit); -#endif -} - -static void -obio_unmask_irq(void *arg) -{ - /* XXX need to write */ -#if 0 - unsigned int irq = (unsigned int)arg; - int ip_bit, mask, mask_register; - - /* unmask IRQ */ - mask_register = ICU_IRQ_MASK_REG(irq); - ip_bit = ICU_IP_BIT(irq); - - mask = ICU_REG_READ(mask_register); - ICU_REG_WRITE(mask_register, mask & ~ip_bit); -#endif -} - -static int -obio_probe(device_t dev) -{ - - return (BUS_PROBE_NOWILDCARD); -} - -static int -obio_attach(device_t dev) -{ - struct obio_softc *sc = device_get_softc(dev); - int rid; - - sc->oba_mem_rman.rm_type = RMAN_ARRAY; - sc->oba_mem_rman.rm_descr = "OBIO memeory"; - if (rman_init(&sc->oba_mem_rman) != 0 || - rman_manage_region(&sc->oba_mem_rman, OBIO_MEM_START, - OBIO_MEM_START + OBIO_MEM_SIZE) != 0) - panic("obio_attach: failed to set up I/O rman"); - - sc->oba_irq_rman.rm_type = RMAN_ARRAY; - sc->oba_irq_rman.rm_descr = "OBIO IRQ"; - - if (rman_init(&sc->oba_irq_rman) != 0 || - rman_manage_region(&sc->oba_irq_rman, 0, NIRQS-1) != 0) - panic("obio_attach: failed to set up IRQ rman"); - - /* Hook up our interrupt handler. */ - if ((sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, - ADM5120_INTR, ADM5120_INTR, 1, - RF_SHAREABLE | RF_ACTIVE)) == NULL) { - device_printf(dev, "unable to allocate IRQ resource\n"); - return (ENXIO); - } - - if ((bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC, obio_intr, NULL, - sc, &sc->sc_ih))) { - device_printf(dev, - "WARNING: unable to register interrupt handler\n"); - return (ENXIO); - } - - /* Hook up our FAST interrupt handler. */ - if ((sc->sc_fast_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, - ADM5120_FAST_INTR, ADM5120_FAST_INTR, 1, - RF_SHAREABLE | RF_ACTIVE)) == NULL) { - device_printf(dev, "unable to allocate IRQ resource\n"); - return (ENXIO); - } - - if ((bus_setup_intr(dev, sc->sc_fast_irq, INTR_TYPE_MISC, obio_intr, - NULL, sc, &sc->sc_fast_ih))) { - device_printf(dev, - "WARNING: unable to register interrupt handler\n"); - return (ENXIO); - } - - /* disable all interrupts */ - REG_WRITE(ICU_ENABLE_REG, ICU_INT_MASK); - - bus_generic_probe(dev); - bus_enumerate_hinted_children(dev); - bus_generic_attach(dev); - - return (0); -} - -static struct resource * -obio_alloc_resource(device_t bus, device_t child, int type, int *rid, - rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) -{ - struct obio_softc *sc = device_get_softc(bus); - struct obio_ivar *ivar = device_get_ivars(child); - struct resource *rv; - struct resource_list_entry *rle; - struct rman *rm; - int isdefault, needactivate, passthrough; - - isdefault = (RMAN_IS_DEFAULT_RANGE(start, end) && count == 1); - needactivate = flags & RF_ACTIVE; - passthrough = (device_get_parent(child) != bus); - rle = NULL; - - if (passthrough) - return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type, - rid, start, end, count, flags)); - - /* - * If this is an allocation of the "default" range for a given RID, - * and we know what the resources for this device are (ie. they aren't - * maintained by a child bus), then work out the start/end values. - */ - if (isdefault) { - rle = resource_list_find(&ivar->resources, type, *rid); - if (rle == NULL) - return (NULL); - if (rle->res != NULL) { - panic("%s: resource entry is busy", __func__); - } - start = rle->start; - end = rle->end; - count = rle->count; - } - - switch (type) { - case SYS_RES_IRQ: - rm = &sc->oba_irq_rman; - break; - case SYS_RES_MEMORY: - rm = &sc->oba_mem_rman; - break; - default: - printf("%s: unknown resource type %d\n", __func__, type); - return (0); - } - - rv = rman_reserve_resource(rm, start, end, count, flags, child); - if (rv == NULL) { - printf("%s: could not reserve resource\n", __func__); - return (0); - } - - rman_set_rid(rv, *rid); - - if (needactivate) { - if (bus_activate_resource(child, type, *rid, rv)) { - printf("%s: could not activate resource\n", __func__); - rman_release_resource(rv); - return (0); - } - } - - return (rv); -} - -static int -obio_activate_resource(device_t bus, device_t child, int type, int rid, - struct resource *r) -{ - - /* - * If this is a memory resource, track the direct mapping - * in the uncached MIPS KSEG1 segment. - */ - if (type == SYS_RES_MEMORY) { - void *vaddr; - - vaddr = (void *)MIPS_PHYS_TO_KSEG1((intptr_t)rman_get_start(r)); - rman_set_virtual(r, vaddr); - rman_set_bustag(r, mips_bus_space_generic); - rman_set_bushandle(r, (bus_space_handle_t)vaddr); - } - - return (rman_activate_resource(r)); -} - -static int -obio_deactivate_resource(device_t bus, device_t child, int type, int rid, - struct resource *r) -{ - - return (rman_deactivate_resource(r)); -} - -static int -obio_release_resource(device_t dev, device_t child, int type, - int rid, struct resource *r) -{ - struct resource_list *rl; - struct resource_list_entry *rle; - - rl = obio_get_resource_list(dev, child); - if (rl == NULL) - return (EINVAL); - rle = resource_list_find(rl, type, rid); - if (rle == NULL) - return (EINVAL); - rman_release_resource(r); - rle->res = NULL; - - return (0); -} - -static int -obio_setup_intr(device_t dev, device_t child, struct resource *ires, - int flags, driver_filter_t *filt, driver_intr_t *handler, - void *arg, void **cookiep) -{ - struct obio_softc *sc = device_get_softc(dev); - struct intr_event *event; - int irq, error, priority; - uint32_t irqmask; - - irq = rman_get_start(ires); - - if (irq >= NIRQS) - panic("%s: bad irq %d", __func__, irq); - - event = sc->sc_eventstab[irq]; - if (event == NULL) { - error = intr_event_create(&event, (void *)irq, 0, irq, - obio_mask_irq, obio_unmask_irq, - NULL, NULL, - "obio intr%d:", irq); - - sc->sc_eventstab[irq] = event; - } - else - panic("obio: Can't share IRQs"); - - intr_event_add_handler(event, device_get_nameunit(child), filt, - handler, arg, intr_priority(flags), flags, cookiep); - - irqmask = 1 << irq; - priority = irq_priorities[irq]; - - if (priority == INTR_FIQ) - REG_WRITE(ICU_MODE_REG, REG_READ(ICU_MODE_REG) | irqmask); - else - REG_WRITE(ICU_MODE_REG, REG_READ(ICU_MODE_REG) & ~irqmask); - - /* enable */ - REG_WRITE(ICU_ENABLE_REG, irqmask); - - return (0); -} - -static int -obio_teardown_intr(device_t dev, device_t child, struct resource *ires, - void *cookie) -{ - struct obio_softc *sc = device_get_softc(dev); - int irq, result; - uint32_t irqmask; - - irq = rman_get_start(ires); - if (irq >= NIRQS) - panic("%s: bad irq %d", __func__, irq); - - if (sc->sc_eventstab[irq] == NULL) - panic("Trying to teardown unoccupied IRQ"); - - irqmask = 1 << irq; /* only used as a mask from here on */ - - /* disable this irq in HW */ - REG_WRITE(ICU_DISABLE_REG, irqmask); - - result = intr_event_remove_handler(cookie); - if (!result) { - sc->sc_eventstab[irq] = NULL; - } - - return (result); -} - -static int -obio_intr(void *arg) -{ - struct obio_softc *sc = arg; - struct intr_event *event; - uint32_t irqstat; - int irq; - - irqstat = REG_READ(ICU_FIQ_STATUS_REG); - irqstat |= REG_READ(ICU_STATUS_REG); - - irq = 0; - while (irqstat != 0) { - if ((irqstat & 1) == 1) { - event = sc->sc_eventstab[irq]; - if (!event || TAILQ_EMPTY(&event->ie_handlers)) - continue; - - /* TODO: pass frame as an argument*/ - /* TODO: log stray interrupt */ - intr_event_handle(event, NULL); - } - - irq++; - irqstat >>= 1; - } - - return (FILTER_HANDLED); -} - -static void -obio_hinted_child(device_t bus, const char *dname, int dunit) -{ - device_t child; - long maddr; - int msize; - int irq; - int result; - - child = BUS_ADD_CHILD(bus, 0, dname, dunit); - - /* - * Set hard-wired resources for hinted child using - * specific RIDs. - */ - resource_long_value(dname, dunit, "maddr", &maddr); - resource_int_value(dname, dunit, "msize", &msize); - - - result = bus_set_resource(child, SYS_RES_MEMORY, 0, - maddr, msize); - if (result != 0) - device_printf(bus, "warning: bus_set_resource() failed\n"); - - if (resource_int_value(dname, dunit, "irq", &irq) == 0) { - result = bus_set_resource(child, SYS_RES_IRQ, 0, irq, 1); - if (result != 0) - device_printf(bus, - "warning: bus_set_resource() failed\n"); - } -} - -static device_t -obio_add_child(device_t bus, u_int order, const char *name, int unit) -{ - device_t child; - struct obio_ivar *ivar; - - ivar = malloc(sizeof(struct obio_ivar), M_DEVBUF, M_WAITOK | M_ZERO); - resource_list_init(&ivar->resources); - - child = device_add_child_ordered(bus, order, name, unit); - if (child == NULL) { - printf("Can't add child %s%d ordered\n", name, unit); - return (0); - } - - device_set_ivars(child, ivar); - - return (child); -} - -/* - * Helper routine for bus_generic_rl_get_resource/bus_generic_rl_set_resource - * Provides pointer to resource_list for these routines - */ -static struct resource_list * -obio_get_resource_list(device_t dev, device_t child) -{ - struct obio_ivar *ivar; - - ivar = device_get_ivars(child); - return (&(ivar->resources)); -} - -static device_method_t obio_methods[] = { - DEVMETHOD(bus_activate_resource, obio_activate_resource), - DEVMETHOD(bus_add_child, obio_add_child), - DEVMETHOD(bus_alloc_resource, obio_alloc_resource), - DEVMETHOD(bus_deactivate_resource, obio_deactivate_resource), - DEVMETHOD(bus_get_resource_list, obio_get_resource_list), - DEVMETHOD(bus_hinted_child, obio_hinted_child), - DEVMETHOD(bus_release_resource, obio_release_resource), - DEVMETHOD(bus_setup_intr, obio_setup_intr), - DEVMETHOD(bus_teardown_intr, obio_teardown_intr), - DEVMETHOD(device_attach, obio_attach), - DEVMETHOD(device_probe, obio_probe), - DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), - DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), - - {0, 0}, -}; - -static driver_t obio_driver = { - "obio", - obio_methods, - sizeof(struct obio_softc), -}; -static devclass_t obio_devclass; - -DRIVER_MODULE(obio, nexus, obio_driver, obio_devclass, 0, 0); diff --git a/sys/mips/alchemy/std.alchemy b/sys/mips/alchemy/std.alchemy deleted file mode 100644 index 1b8b83b17f3d..000000000000 --- a/sys/mips/alchemy/std.alchemy +++ /dev/null @@ -1,8 +0,0 @@ -# $FreeBSD$ -# Standard include file for Alchemy Au1xxx CPUs: -# Au1000, Au1200, Au1250, Au1500 and Au1550 - -files "../alchemy/files.alchemy" - -machine mips mipsel -cpu CPU_MIPS4KC diff --git a/sys/mips/alchemy/uart_bus_alchemy.c b/sys/mips/alchemy/uart_bus_alchemy.c deleted file mode 100644 index c85aeb1649d6..000000000000 --- a/sys/mips/alchemy/uart_bus_alchemy.c +++ /dev/null @@ -1,89 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2007 Bruce M. Simpson. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * $Id$ - */ -/* - * Skeleton of this file was based on respective code for ARM - * code written by Olivier Houchard. - */ - -#include "opt_uart.h" - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include - -#include - -#include "uart_if.h" - -static int uart_alchemy_probe(device_t dev); - -static device_method_t uart_alchemy_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, uart_alchemy_probe), - DEVMETHOD(device_attach, uart_bus_attach), - DEVMETHOD(device_detach, uart_bus_detach), - { 0, 0 } -}; - -static driver_t uart_alchemy_driver = { - uart_driver_name, - uart_alchemy_methods, - sizeof(struct uart_softc), -}; - -extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs; - -static int -uart_alchemy_probe(device_t dev) -{ - struct uart_softc *sc; - - sc = device_get_softc(dev); - sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs); - sc->sc_class = &uart_ns8250_class; - bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas)); - - return (uart_bus_probe(dev, 0, 0, 0, 0, 0)); -} - -DRIVER_MODULE(uart, obio, uart_alchemy_driver, uart_devclass, 0, 0); diff --git a/sys/mips/alchemy/uart_cpu_alchemy.c b/sys/mips/alchemy/uart_cpu_alchemy.c deleted file mode 100644 index 7ef3ec6f8fc6..000000000000 --- a/sys/mips/alchemy/uart_cpu_alchemy.c +++ /dev/null @@ -1,81 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2006 Wojciech A. Koszek - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $Id$ - */ -/* - * Skeleton of this file was based on respective code for ARM - * code written by Olivier Houchard. - */ - -#include "opt_uart.h" - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include - -#include - -#include -#include - -#include - -bus_space_tag_t uart_bus_space_io; -bus_space_tag_t uart_bus_space_mem; - -int -uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2) -{ - - return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0); -} - -int -uart_cpu_getdev(int devtype, struct uart_devinfo *di) -{ - - di->ops = uart_getops(&uart_ns8250_class); - di->bas.chan = 0; - di->bas.bst = mips_bus_space_generic; - di->bas.regshft = 0; - di->bas.rclk = 0; - di->baudrate = 115200; - di->databits = 8; - di->stopbits = 1; - di->parity = UART_PARITY_NONE; - - uart_bus_space_io = 0; - uart_bus_space_mem = mips_bus_space_generic; - di->bas.bsh = MIPS_PHYS_TO_KSEG1(UART0_BASE); - - return (0); -} diff --git a/sys/mips/conf/ALCHEMY b/sys/mips/conf/ALCHEMY deleted file mode 100644 index 6bfe23865b87..000000000000 --- a/sys/mips/conf/ALCHEMY +++ /dev/null @@ -1,65 +0,0 @@ -# ALCHEMY -- Generic kernel for Alchemy Au1xxx CPUs. -# -# For more information on this file, please read the handbook section on -# Kernel Configuration Files: -# -# https://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html -# -# The handbook is also available locally in /usr/share/doc/handbook -# if you've installed the doc distribution, otherwise always see the -# FreeBSD World Wide Web server (https://www.FreeBSD.org/) for the -# latest information. -# -# An exhaustive list of options and more detailed explanations of the -# device lines is also present in the ../../conf/NOTES and NOTES files. -# If you are in doubt as to the purpose or necessity of a line, check first -# in NOTES. -# -# $FreeBSD$ - -ident ALCHEMY - -# Don't build any modules yet. -makeoptions MODULES_OVERRIDE="" - -include "../alchemy/std.alchemy" - -#hints "ALCHEMY.hints" #Default places to look for devices. - -makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols - -options DDB -options KDB - -options SCHED_4BSD #4BSD scheduler -options INET #InterNETworking -options TCP_HHOOK # hhook(9) framework for TCP -options NFSCL #Network Filesystem Client -options NFS_ROOT #NFS usable as /, requires NFSCL -options PSEUDOFS #Pseudo-filesystem framework -# options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions - -options BOOTP -options BOOTP_NFSROOT -options BOOTP_NFSV3 -options BOOTP_WIRED_TO=admsw0 -options BOOTP_COMPAT - -# options FFS #Berkeley Fast Filesystem -# options SOFTUPDATES #Enable FFS soft updates support -# options UFS_ACL #Support for access control lists -# options UFS_DIRHASH #Improve performance on big directories -options ROOTDEVNAME=\"nfs:10.0.0.1:/mnt/bsd\" - - -# Debugging for use in -current -#options DEADLKRES #Enable the deadlock resolver -options INVARIANTS #Enable calls of extra sanity checking -options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS -#options WITNESS #Enable checks to detect deadlocks and cycles -#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed - -device loop -device ether -device uart -# device md