diff --git a/sys/amd64/amd64/amd64_mem.c b/sys/amd64/amd64/amd64_mem.c
index 55e8f974a8b7..260b77b4955b 100644
--- a/sys/amd64/amd64/amd64_mem.c
+++ b/sys/amd64/amd64/amd64_mem.c
@@ -307,17 +307,17 @@ amd64_mrstoreone(void *arg)
 	struct mem_range_desc *mrd;
 	u_int64_t omsrv, msrv;
 	int i, j, msr;
-	u_int cr4save;
+	u_long cr0, cr4;
 
 	mrd = sc->mr_desc;
 
 	/* Disable PGE. */
-	cr4save = rcr4();
-	if (cr4save & CR4_PGE)
-		load_cr4(cr4save & ~CR4_PGE);
+	cr4 = rcr4();
+	load_cr4(cr4 & ~CR4_PGE);
 
 	/* Disable caches (CD = 1, NW = 0). */
-	load_cr0((rcr0() & ~CR0_NW) | CR0_CD);
+	cr0 = rcr0();
+	load_cr0((cr0 & ~CR0_NW) | CR0_CD);
 
 	/* Flushes caches and TLBs. */
 	wbinvd();
@@ -396,11 +396,9 @@ amd64_mrstoreone(void *arg)
 	/* Enable MTRRs. */
 	wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) | MTRR_DEF_ENABLE);
 
-	/* Enable caches (CD = 0, NW = 0). */
-	load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
-
-	/* Restore PGE. */
-	load_cr4(cr4save);
+	/* Restore caches and PGE. */
+	load_cr0(cr0);
+	load_cr4(cr4);
 }
 
 /*
diff --git a/sys/i386/i386/i686_mem.c b/sys/i386/i386/i686_mem.c
index f8580cd5a708..a8d8baf78d6a 100644
--- a/sys/i386/i386/i686_mem.c
+++ b/sys/i386/i386/i686_mem.c
@@ -301,17 +301,17 @@ i686_mrstoreone(void *arg)
 	struct mem_range_desc *mrd;
 	u_int64_t omsrv, msrv;
 	int i, j, msr;
-	u_int cr4save;
+	u_long cr0, cr4;
 
 	mrd = sc->mr_desc;
 
 	/* Disable PGE. */
-	cr4save = rcr4();
-	if (cr4save & CR4_PGE)
-		load_cr4(cr4save & ~CR4_PGE);
+	cr4 = rcr4();
+	load_cr4(cr4 & ~CR4_PGE);
 
 	/* Disable caches (CD = 1, NW = 0). */
-	load_cr0((rcr0() & ~CR0_NW) | CR0_CD);
+	cr0 = rcr0();
+	load_cr0((cr0 & ~CR0_NW) | CR0_CD);
 
 	/* Flushes caches and TLBs. */
 	wbinvd();
@@ -390,11 +390,9 @@ i686_mrstoreone(void *arg)
 	/* Enable MTRRs. */
 	wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) | MTRR_DEF_ENABLE);
 
-	/* Enable caches (CD = 0, NW = 0). */
-	load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
-
-	/* Restore PGE. */
-	load_cr4(cr4save);
+	/* Restore caches and PGE. */
+	load_cr0(cr0);
+	load_cr4(cr4);
 }
 
 /*